opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VZERO_Fixup (int, int);
  99 static void VCMP_Fixup (int, int);
 100 static void VPCMP_Fixup (int, int);
 101 static void VPCOM_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define EbndS { OP_E, bnd_swap_mode }
 252 #define Ev { OP_E, v_mode }
 253 #define Eva { OP_E, va_mode }
 254 #define Ev_bnd { OP_E, v_bnd_mode }
 255 #define EvS { OP_E, v_swap_mode }
 256 #define Ed { OP_E, d_mode }
 257 #define Edq { OP_E, dq_mode }
 258 #define Edqw { OP_E, dqw_mode }
 259 #define Edqb { OP_E, dqb_mode }
 260 #define Edb { OP_E, db_mode }
 261 #define Edw { OP_E, dw_mode }
 262 #define Edqd { OP_E, dqd_mode }
 263 #define Edqa { OP_E, dqa_mode }
 264 #define Eq { OP_E, q_mode }
 265 #define indirEv { OP_indirE, indir_v_mode }
 266 #define indirEp { OP_indirE, f_mode }
 267 #define stackEv { OP_E, stack_v_mode }
 268 #define Em { OP_E, m_mode }
 269 #define Ew { OP_E, w_mode }
 270 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 271 #define Ma { OP_M, a_mode }
 272 #define Mb { OP_M, b_mode }
 273 #define Md { OP_M, d_mode }
 274 #define Mo { OP_M, o_mode }
 275 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 276 #define Mq { OP_M, q_mode }
 277 #define Mv_bnd { OP_M, v_bndmk_mode }
 278 #define Mx { OP_M, x_mode }
 279 #define Mxmm { OP_M, xmm_mode }
 280 #define Gb { OP_G, b_mode }
 281 #define Gbnd { OP_G, bnd_mode }
 282 #define Gv { OP_G, v_mode }
 283 #define Gd { OP_G, d_mode }
 284 #define Gdq { OP_G, dq_mode }
 285 #define Gm { OP_G, m_mode }
 286 #define Gva { OP_G, va_mode }
 287 #define Gw { OP_G, w_mode }
 288 #define Rd { OP_R, d_mode }
 289 #define Rdq { OP_R, dq_mode }
 290 #define Rm { OP_R, m_mode }
 291 #define Ib { OP_I, b_mode }
 292 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 293 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 294 #define Iv { OP_I, v_mode }
 295 #define sIv { OP_sI, v_mode }
 296 #define Iq { OP_I, q_mode }
 297 #define Iv64 { OP_I64, v_mode }
 298 #define Iw { OP_I, w_mode }
 299 #define I1 { OP_I, const_1_mode }
 300 #define Jb { OP_J, b_mode }
 301 #define Jv { OP_J, v_mode }
 302 #define Cm { OP_C, m_mode }
 303 #define Dm { OP_D, m_mode }
 304 #define Td { OP_T, d_mode }
 305 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 306
 307 #define RMeAX { OP_REG, eAX_reg }
 308 #define RMeBX { OP_REG, eBX_reg }
 309 #define RMeCX { OP_REG, eCX_reg }
 310 #define RMeDX { OP_REG, eDX_reg }
 311 #define RMeSP { OP_REG, eSP_reg }
 312 #define RMeBP { OP_REG, eBP_reg }
 313 #define RMeSI { OP_REG, eSI_reg }
 314 #define RMeDI { OP_REG, eDI_reg }
 315 #define RMrAX { OP_REG, rAX_reg }
 316 #define RMrBX { OP_REG, rBX_reg }
 317 #define RMrCX { OP_REG, rCX_reg }
 318 #define RMrDX { OP_REG, rDX_reg }
 319 #define RMrSP { OP_REG, rSP_reg }
 320 #define RMrBP { OP_REG, rBP_reg }
 321 #define RMrSI { OP_REG, rSI_reg }
 322 #define RMrDI { OP_REG, rDI_reg }
 323 #define RMAL { OP_REG, al_reg }
 324 #define RMCL { OP_REG, cl_reg }
 325 #define RMDL { OP_REG, dl_reg }
 326 #define RMBL { OP_REG, bl_reg }
 327 #define RMAH { OP_REG, ah_reg }
 328 #define RMCH { OP_REG, ch_reg }
 329 #define RMDH { OP_REG, dh_reg }
 330 #define RMBH { OP_REG, bh_reg }
 331 #define RMAX { OP_REG, ax_reg }
 332 #define RMDX { OP_REG, dx_reg }
 333
 334 #define eAX { OP_IMREG, eAX_reg }
 335 #define eBX { OP_IMREG, eBX_reg }
 336 #define eCX { OP_IMREG, eCX_reg }
 337 #define eDX { OP_IMREG, eDX_reg }
 338 #define eSP { OP_IMREG, eSP_reg }
 339 #define eBP { OP_IMREG, eBP_reg }
 340 #define eSI { OP_IMREG, eSI_reg }
 341 #define eDI { OP_IMREG, eDI_reg }
 342 #define AL { OP_IMREG, al_reg }
 343 #define CL { OP_IMREG, cl_reg }
 344 #define DL { OP_IMREG, dl_reg }
 345 #define BL { OP_IMREG, bl_reg }
 346 #define AH { OP_IMREG, ah_reg }
 347 #define CH { OP_IMREG, ch_reg }
 348 #define DH { OP_IMREG, dh_reg }
 349 #define BH { OP_IMREG, bh_reg }
 350 #define AX { OP_IMREG, ax_reg }
 351 #define DX { OP_IMREG, dx_reg }
 352 #define zAX { OP_IMREG, z_mode_ax_reg }
 353 #define indirDX { OP_IMREG, indir_dx_reg }
 354
 355 #define Sw { OP_SEG, w_mode }
 356 #define Sv { OP_SEG, v_mode }
 357 #define Ap { OP_DIR, 0 }
 358 #define Ob { OP_OFF64, b_mode }
 359 #define Ov { OP_OFF64, v_mode }
 360 #define Xb { OP_DSreg, eSI_reg }
 361 #define Xv { OP_DSreg, eSI_reg }
 362 #define Xz { OP_DSreg, eSI_reg }
 363 #define Yb { OP_ESreg, eDI_reg }
 364 #define Yv { OP_ESreg, eDI_reg }
 365 #define DSBX { OP_DSreg, eBX_reg }
 366
 367 #define es { OP_REG, es_reg }
 368 #define ss { OP_REG, ss_reg }
 369 #define cs { OP_REG, cs_reg }
 370 #define ds { OP_REG, ds_reg }
 371 #define fs { OP_REG, fs_reg }
 372 #define gs { OP_REG, gs_reg }
 373
 374 #define MX { OP_MMX, 0 }
 375 #define XM { OP_XMM, 0 }
 376 #define XMScalar { OP_XMM, scalar_mode }
 377 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 378 #define XMM { OP_XMM, xmm_mode }
 379 #define XMxmmq { OP_XMM, xmmq_mode }
 380 #define EM { OP_EM, v_mode }
 381 #define EMS { OP_EM, v_swap_mode }
 382 #define EMd { OP_EM, d_mode }
 383 #define EMx { OP_EM, x_mode }
 384 #define EXbScalar { OP_EX, b_scalar_mode }
 385 #define EXw { OP_EX, w_mode }
 386 #define EXwScalar { OP_EX, w_scalar_mode }
 387 #define EXd { OP_EX, d_mode }
 388 #define EXdScalar { OP_EX, d_scalar_mode }
 389 #define EXdS { OP_EX, d_swap_mode }
 390 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 391 #define EXq { OP_EX, q_mode }
 392 #define EXqScalar { OP_EX, q_scalar_mode }
 393 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 394 #define EXqS { OP_EX, q_swap_mode }
 395 #define EXx { OP_EX, x_mode }
 396 #define EXxS { OP_EX, x_swap_mode }
 397 #define EXxmm { OP_EX, xmm_mode }
 398 #define EXymm { OP_EX, ymm_mode }
 399 #define EXxmmq { OP_EX, xmmq_mode }
 400 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 401 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 402 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 403 #define EXxmm_md { OP_EX, xmm_md_mode }
 404 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 405 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 406 #define EXxmmdw { OP_EX, xmmdw_mode }
 407 #define EXxmmqd { OP_EX, xmmqd_mode }
 408 #define EXymmq { OP_EX, ymmq_mode }
 409 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 410 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 411 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 412 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 413 #define MS { OP_MS, v_mode }
 414 #define XS { OP_XS, v_mode }
 415 #define EMCq { OP_EMC, q_mode }
 416 #define MXC { OP_MXC, 0 }
 417 #define OPSUF { OP_3DNowSuffix, 0 }
 418 #define CMP { CMP_Fixup, 0 }
 419 #define XMM0 { XMM_Fixup, 0 }
 420 #define FXSAVE { FXSAVE_Fixup, 0 }
 421 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 422 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 423
 424 #define Vex { OP_VEX, vex_mode }
 425 #define VexScalar { OP_VEX, vex_scalar_mode }
 426 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 427 #define Vex128 { OP_VEX, vex128_mode }
 428 #define Vex256 { OP_VEX, vex256_mode }
 429 #define VexGdq { OP_VEX, dq_mode }
 430 #define EXdVex { OP_EX_Vex, d_mode }
 431 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 432 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 433 #define EXqVex { OP_EX_Vex, q_mode }
 434 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 435 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 436 #define EXVexW { OP_EX_VexW, x_mode }
 437 #define EXdVexW { OP_EX_VexW, d_mode }
 438 #define EXqVexW { OP_EX_VexW, q_mode }
 439 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 440 #define XMVex { OP_XMM_Vex, 0 }
 441 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 442 #define XMVexW { OP_XMM_VexW, 0 }
 443 #define XMVexI4 { OP_REG_VexI4, x_mode }
 444 #define PCLMUL { PCLMUL_Fixup, 0 }
 445 #define VZERO { VZERO_Fixup, 0 }
 446 #define VCMP { VCMP_Fixup, 0 }
 447 #define VPCMP { VPCMP_Fixup, 0 }
 448 #define VPCOM { VPCOM_Fixup, 0 }
 449
 450 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 451 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 452 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 453
 454 #define XMask { OP_Mask, mask_mode }
 455 #define MaskG { OP_G, mask_mode }
 456 #define MaskE { OP_E, mask_mode }
 457 #define MaskBDE { OP_E, mask_bd_mode }
 458 #define MaskR { OP_R, mask_mode }
 459 #define MaskVex { OP_VEX, mask_mode }
 460
 461 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 462 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 463 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 464 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 465
 466 /* Used handle "rep" prefix for string instructions.  */
 467 #define Xbr { REP_Fixup, eSI_reg }
 468 #define Xvr { REP_Fixup, eSI_reg }
 469 #define Ybr { REP_Fixup, eDI_reg }
 470 #define Yvr { REP_Fixup, eDI_reg }
 471 #define Yzr { REP_Fixup, eDI_reg }
 472 #define indirDXr { REP_Fixup, indir_dx_reg }
 473 #define ALr { REP_Fixup, al_reg }
 474 #define eAXr { REP_Fixup, eAX_reg }
 475
 476 /* Used handle HLE prefix for lockable instructions.  */
 477 #define Ebh1 { HLE_Fixup1, b_mode }
 478 #define Evh1 { HLE_Fixup1, v_mode }
 479 #define Ebh2 { HLE_Fixup2, b_mode }
 480 #define Evh2 { HLE_Fixup2, v_mode }
 481 #define Ebh3 { HLE_Fixup3, b_mode }
 482 #define Evh3 { HLE_Fixup3, v_mode }
 483
 484 #define BND { BND_Fixup, 0 }
 485 #define NOTRACK { NOTRACK_Fixup, 0 }
 486
 487 #define cond_jump_flag { NULL, cond_jump_mode }
 488 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 489
 490 /* bits in sizeflag */
 491 #define SUFFIX_ALWAYS 4
 492 #define AFLAG 2
 493 #define DFLAG 1
 494
 495 enum
 496 {
 497   /* byte operand */
 498   b_mode = 1,
 499   /* byte operand with operand swapped */
 500   b_swap_mode,
 501   /* byte operand, sign extend like 'T' suffix */
 502   b_T_mode,
 503   /* operand size depends on prefixes */
 504   v_mode,
 505   /* operand size depends on prefixes with operand swapped */
 506   v_swap_mode,
 507   /* operand size depends on address prefix */
 508   va_mode,
 509   /* word operand */
 510   w_mode,
 511   /* double word operand  */
 512   d_mode,
 513   /* double word operand with operand swapped */
 514   d_swap_mode,
 515   /* quad word operand */
 516   q_mode,
 517   /* quad word operand with operand swapped */
 518   q_swap_mode,
 519   /* ten-byte operand */
 520   t_mode,
 521   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 522      broadcast enabled.  */
 523   x_mode,
 524   /* Similar to x_mode, but with different EVEX mem shifts.  */
 525   evex_x_gscat_mode,
 526   /* Similar to x_mode, but with disabled broadcast.  */
 527   evex_x_nobcst_mode,
 528   /* Similar to x_mode, but with operands swapped and disabled broadcast
 529      in EVEX.  */
 530   x_swap_mode,
 531   /* 16-byte XMM operand */
 532   xmm_mode,
 533   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 534      memory operand (depending on vector length).  Broadcast isn't
 535      allowed.  */
 536   xmmq_mode,
 537   /* Same as xmmq_mode, but broadcast is allowed.  */
 538   evex_half_bcst_xmmq_mode,
 539   /* XMM register or byte memory operand */
 540   xmm_mb_mode,
 541   /* XMM register or word memory operand */
 542   xmm_mw_mode,
 543   /* XMM register or double word memory operand */
 544   xmm_md_mode,
 545   /* XMM register or quad word memory operand */
 546   xmm_mq_mode,
 547   /* XMM register or double/quad word memory operand, depending on
 548      VEX.W.  */
 549   xmm_mdq_mode,
 550   /* 16-byte XMM, word, double word or quad word operand.  */
 551   xmmdw_mode,
 552   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 553   xmmqd_mode,
 554   /* 32-byte YMM operand */
 555   ymm_mode,
 556   /* quad word, ymmword or zmmword memory operand.  */
 557   ymmq_mode,
 558   /* 32-byte YMM or 16-byte word operand */
 559   ymmxmm_mode,
 560   /* d_mode in 32bit, q_mode in 64bit mode.  */
 561   m_mode,
 562   /* pair of v_mode operands */
 563   a_mode,
 564   cond_jump_mode,
 565   loop_jcxz_mode,
 566   v_bnd_mode,
 567   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 568   v_bndmk_mode,
 569   /* operand size depends on REX prefixes.  */
 570   dq_mode,
 571   /* registers like dq_mode, memory like w_mode.  */
 572   dqw_mode,
 573   /* bounds operand */
 574   bnd_mode,
 575   /* bounds operand with operand swapped */
 576   bnd_swap_mode,
 577   /* 4- or 6-byte pointer operand */
 578   f_mode,
 579   const_1_mode,
 580   /* v_mode for indirect branch opcodes.  */
 581   indir_v_mode,
 582   /* v_mode for stack-related opcodes.  */
 583   stack_v_mode,
 584   /* non-quad operand size depends on prefixes */
 585   z_mode,
 586   /* 16-byte operand */
 587   o_mode,
 588   /* registers like dq_mode, memory like b_mode.  */
 589   dqb_mode,
 590   /* registers like d_mode, memory like b_mode.  */
 591   db_mode,
 592   /* registers like d_mode, memory like w_mode.  */
 593   dw_mode,
 594   /* registers like dq_mode, memory like d_mode.  */
 595   dqd_mode,
 596   /* operand size depends on the W bit as well as address mode.  */
 597   dqa_mode,
 598   /* normal vex mode */
 599   vex_mode,
 600   /* 128bit vex mode */
 601   vex128_mode,
 602   /* 256bit vex mode */
 603   vex256_mode,
 604   /* operand size depends on the VEX.W bit.  */
 605   vex_w_dq_mode,
 606
 607   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 608   vex_vsib_d_w_dq_mode,
 609   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 610   vex_vsib_d_w_d_mode,
 611   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 612   vex_vsib_q_w_dq_mode,
 613   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 614   vex_vsib_q_w_d_mode,
 615
 616   /* scalar, ignore vector length.  */
 617   scalar_mode,
 618   /* like b_mode, ignore vector length.  */
 619   b_scalar_mode,
 620   /* like w_mode, ignore vector length.  */
 621   w_scalar_mode,
 622   /* like d_mode, ignore vector length.  */
 623   d_scalar_mode,
 624   /* like d_swap_mode, ignore vector length.  */
 625   d_scalar_swap_mode,
 626   /* like q_mode, ignore vector length.  */
 627   q_scalar_mode,
 628   /* like q_swap_mode, ignore vector length.  */
 629   q_scalar_swap_mode,
 630   /* like vex_mode, ignore vector length.  */
 631   vex_scalar_mode,
 632   /* like vex_w_dq_mode, ignore vector length.  */
 633   vex_scalar_w_dq_mode,
 634
 635   /* Static rounding.  */
 636   evex_rounding_mode,
 637   /* Static rounding, 64-bit mode only.  */
 638   evex_rounding_64_mode,
 639   /* Supress all exceptions.  */
 640   evex_sae_mode,
 641
 642   /* Mask register operand.  */
 643   mask_mode,
 644   /* Mask register operand.  */
 645   mask_bd_mode,
 646
 647   es_reg,
 648   cs_reg,
 649   ss_reg,
 650   ds_reg,
 651   fs_reg,
 652   gs_reg,
 653
 654   eAX_reg,
 655   eCX_reg,
 656   eDX_reg,
 657   eBX_reg,
 658   eSP_reg,
 659   eBP_reg,
 660   eSI_reg,
 661   eDI_reg,
 662
 663   al_reg,
 664   cl_reg,
 665   dl_reg,
 666   bl_reg,
 667   ah_reg,
 668   ch_reg,
 669   dh_reg,
 670   bh_reg,
 671
 672   ax_reg,
 673   cx_reg,
 674   dx_reg,
 675   bx_reg,
 676   sp_reg,
 677   bp_reg,
 678   si_reg,
 679   di_reg,
 680
 681   rAX_reg,
 682   rCX_reg,
 683   rDX_reg,
 684   rBX_reg,
 685   rSP_reg,
 686   rBP_reg,
 687   rSI_reg,
 688   rDI_reg,
 689
 690   z_mode_ax_reg,
 691   indir_dx_reg
 692 };
 693
 694 enum
 695 {
 696   FLOATCODE = 1,
 697   USE_REG_TABLE,
 698   USE_MOD_TABLE,
 699   USE_RM_TABLE,
 700   USE_PREFIX_TABLE,
 701   USE_X86_64_TABLE,
 702   USE_3BYTE_TABLE,
 703   USE_XOP_8F_TABLE,
 704   USE_VEX_C4_TABLE,
 705   USE_VEX_C5_TABLE,
 706   USE_VEX_LEN_TABLE,
 707   USE_VEX_W_TABLE,
 708   USE_EVEX_TABLE
 709 };
 710
 711 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 712
 713 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 714 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 715 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 716 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 717 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 718 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 719 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 720 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 721 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 722 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 723 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 724 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 725 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 726 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 727 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 728
 729 enum
 730 {
 731   REG_80 = 0,
 732   REG_81,
 733   REG_83,
 734   REG_8F,
 735   REG_C0,
 736   REG_C1,
 737   REG_C6,
 738   REG_C7,
 739   REG_D0,
 740   REG_D1,
 741   REG_D2,
 742   REG_D3,
 743   REG_F6,
 744   REG_F7,
 745   REG_FE,
 746   REG_FF,
 747   REG_0F00,
 748   REG_0F01,
 749   REG_0F0D,
 750   REG_0F18,
 751   REG_0F1C_MOD_0,
 752   REG_0F1E_MOD_3,
 753   REG_0F71,
 754   REG_0F72,
 755   REG_0F73,
 756   REG_0FA6,
 757   REG_0FA7,
 758   REG_0FAE,
 759   REG_0FBA,
 760   REG_0FC7,
 761   REG_VEX_0F71,
 762   REG_VEX_0F72,
 763   REG_VEX_0F73,
 764   REG_VEX_0FAE,
 765   REG_VEX_0F38F3,
 766   REG_XOP_LWPCB,
 767   REG_XOP_LWP,
 768   REG_XOP_TBM_01,
 769   REG_XOP_TBM_02,
 770
 771   REG_EVEX_0F71,
 772   REG_EVEX_0F72,
 773   REG_EVEX_0F73,
 774   REG_EVEX_0F38C6,
 775   REG_EVEX_0F38C7
 776 };
 777
 778 enum
 779 {
 780   MOD_8D = 0,
 781   MOD_C6_REG_7,
 782   MOD_C7_REG_7,
 783   MOD_FF_REG_3,
 784   MOD_FF_REG_5,
 785   MOD_0F01_REG_0,
 786   MOD_0F01_REG_1,
 787   MOD_0F01_REG_2,
 788   MOD_0F01_REG_3,
 789   MOD_0F01_REG_5,
 790   MOD_0F01_REG_7,
 791   MOD_0F12_PREFIX_0,
 792   MOD_0F13,
 793   MOD_0F16_PREFIX_0,
 794   MOD_0F17,
 795   MOD_0F18_REG_0,
 796   MOD_0F18_REG_1,
 797   MOD_0F18_REG_2,
 798   MOD_0F18_REG_3,
 799   MOD_0F18_REG_4,
 800   MOD_0F18_REG_5,
 801   MOD_0F18_REG_6,
 802   MOD_0F18_REG_7,
 803   MOD_0F1A_PREFIX_0,
 804   MOD_0F1B_PREFIX_0,
 805   MOD_0F1B_PREFIX_1,
 806   MOD_0F1C_PREFIX_0,
 807   MOD_0F1E_PREFIX_1,
 808   MOD_0F24,
 809   MOD_0F26,
 810   MOD_0F2B_PREFIX_0,
 811   MOD_0F2B_PREFIX_1,
 812   MOD_0F2B_PREFIX_2,
 813   MOD_0F2B_PREFIX_3,
 814   MOD_0F51,
 815   MOD_0F71_REG_2,
 816   MOD_0F71_REG_4,
 817   MOD_0F71_REG_6,
 818   MOD_0F72_REG_2,
 819   MOD_0F72_REG_4,
 820   MOD_0F72_REG_6,
 821   MOD_0F73_REG_2,
 822   MOD_0F73_REG_3,
 823   MOD_0F73_REG_6,
 824   MOD_0F73_REG_7,
 825   MOD_0FAE_REG_0,
 826   MOD_0FAE_REG_1,
 827   MOD_0FAE_REG_2,
 828   MOD_0FAE_REG_3,
 829   MOD_0FAE_REG_4,
 830   MOD_0FAE_REG_5,
 831   MOD_0FAE_REG_6,
 832   MOD_0FAE_REG_7,
 833   MOD_0FB2,
 834   MOD_0FB4,
 835   MOD_0FB5,
 836   MOD_0FC3,
 837   MOD_0FC7_REG_3,
 838   MOD_0FC7_REG_4,
 839   MOD_0FC7_REG_5,
 840   MOD_0FC7_REG_6,
 841   MOD_0FC7_REG_7,
 842   MOD_0FD7,
 843   MOD_0FE7_PREFIX_2,
 844   MOD_0FF0_PREFIX_3,
 845   MOD_0F382A_PREFIX_2,
 846   MOD_0F38F5_PREFIX_2,
 847   MOD_0F38F6_PREFIX_0,
 848   MOD_0F38F8_PREFIX_2,
 849   MOD_0F38F9_PREFIX_0,
 850   MOD_62_32BIT,
 851   MOD_C4_32BIT,
 852   MOD_C5_32BIT,
 853   MOD_VEX_0F12_PREFIX_0,
 854   MOD_VEX_0F13,
 855   MOD_VEX_0F16_PREFIX_0,
 856   MOD_VEX_0F17,
 857   MOD_VEX_0F2B,
 858   MOD_VEX_W_0_0F41_P_0_LEN_1,
 859   MOD_VEX_W_1_0F41_P_0_LEN_1,
 860   MOD_VEX_W_0_0F41_P_2_LEN_1,
 861   MOD_VEX_W_1_0F41_P_2_LEN_1,
 862   MOD_VEX_W_0_0F42_P_0_LEN_1,
 863   MOD_VEX_W_1_0F42_P_0_LEN_1,
 864   MOD_VEX_W_0_0F42_P_2_LEN_1,
 865   MOD_VEX_W_1_0F42_P_2_LEN_1,
 866   MOD_VEX_W_0_0F44_P_0_LEN_1,
 867   MOD_VEX_W_1_0F44_P_0_LEN_1,
 868   MOD_VEX_W_0_0F44_P_2_LEN_1,
 869   MOD_VEX_W_1_0F44_P_2_LEN_1,
 870   MOD_VEX_W_0_0F45_P_0_LEN_1,
 871   MOD_VEX_W_1_0F45_P_0_LEN_1,
 872   MOD_VEX_W_0_0F45_P_2_LEN_1,
 873   MOD_VEX_W_1_0F45_P_2_LEN_1,
 874   MOD_VEX_W_0_0F46_P_0_LEN_1,
 875   MOD_VEX_W_1_0F46_P_0_LEN_1,
 876   MOD_VEX_W_0_0F46_P_2_LEN_1,
 877   MOD_VEX_W_1_0F46_P_2_LEN_1,
 878   MOD_VEX_W_0_0F47_P_0_LEN_1,
 879   MOD_VEX_W_1_0F47_P_0_LEN_1,
 880   MOD_VEX_W_0_0F47_P_2_LEN_1,
 881   MOD_VEX_W_1_0F47_P_2_LEN_1,
 882   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 883   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 884   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 885   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 886   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 887   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 888   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 889   MOD_VEX_0F50,
 890   MOD_VEX_0F71_REG_2,
 891   MOD_VEX_0F71_REG_4,
 892   MOD_VEX_0F71_REG_6,
 893   MOD_VEX_0F72_REG_2,
 894   MOD_VEX_0F72_REG_4,
 895   MOD_VEX_0F72_REG_6,
 896   MOD_VEX_0F73_REG_2,
 897   MOD_VEX_0F73_REG_3,
 898   MOD_VEX_0F73_REG_6,
 899   MOD_VEX_0F73_REG_7,
 900   MOD_VEX_W_0_0F91_P_0_LEN_0,
 901   MOD_VEX_W_1_0F91_P_0_LEN_0,
 902   MOD_VEX_W_0_0F91_P_2_LEN_0,
 903   MOD_VEX_W_1_0F91_P_2_LEN_0,
 904   MOD_VEX_W_0_0F92_P_0_LEN_0,
 905   MOD_VEX_W_0_0F92_P_2_LEN_0,
 906   MOD_VEX_W_0_0F92_P_3_LEN_0,
 907   MOD_VEX_W_1_0F92_P_3_LEN_0,
 908   MOD_VEX_W_0_0F93_P_0_LEN_0,
 909   MOD_VEX_W_0_0F93_P_2_LEN_0,
 910   MOD_VEX_W_0_0F93_P_3_LEN_0,
 911   MOD_VEX_W_1_0F93_P_3_LEN_0,
 912   MOD_VEX_W_0_0F98_P_0_LEN_0,
 913   MOD_VEX_W_1_0F98_P_0_LEN_0,
 914   MOD_VEX_W_0_0F98_P_2_LEN_0,
 915   MOD_VEX_W_1_0F98_P_2_LEN_0,
 916   MOD_VEX_W_0_0F99_P_0_LEN_0,
 917   MOD_VEX_W_1_0F99_P_0_LEN_0,
 918   MOD_VEX_W_0_0F99_P_2_LEN_0,
 919   MOD_VEX_W_1_0F99_P_2_LEN_0,
 920   MOD_VEX_0FAE_REG_2,
 921   MOD_VEX_0FAE_REG_3,
 922   MOD_VEX_0FD7_PREFIX_2,
 923   MOD_VEX_0FE7_PREFIX_2,
 924   MOD_VEX_0FF0_PREFIX_3,
 925   MOD_VEX_0F381A_PREFIX_2,
 926   MOD_VEX_0F382A_PREFIX_2,
 927   MOD_VEX_0F382C_PREFIX_2,
 928   MOD_VEX_0F382D_PREFIX_2,
 929   MOD_VEX_0F382E_PREFIX_2,
 930   MOD_VEX_0F382F_PREFIX_2,
 931   MOD_VEX_0F385A_PREFIX_2,
 932   MOD_VEX_0F388C_PREFIX_2,
 933   MOD_VEX_0F388E_PREFIX_2,
 934   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 935   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 936   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 937   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 938   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 939   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 940   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 941   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 942
 943   MOD_EVEX_0F10_PREFIX_1,
 944   MOD_EVEX_0F10_PREFIX_3,
 945   MOD_EVEX_0F11_PREFIX_1,
 946   MOD_EVEX_0F11_PREFIX_3,
 947   MOD_EVEX_0F12_PREFIX_0,
 948   MOD_EVEX_0F16_PREFIX_0,
 949   MOD_EVEX_0F38C6_REG_1,
 950   MOD_EVEX_0F38C6_REG_2,
 951   MOD_EVEX_0F38C6_REG_5,
 952   MOD_EVEX_0F38C6_REG_6,
 953   MOD_EVEX_0F38C7_REG_1,
 954   MOD_EVEX_0F38C7_REG_2,
 955   MOD_EVEX_0F38C7_REG_5,
 956   MOD_EVEX_0F38C7_REG_6
 957 };
 958
 959 enum
 960 {
 961   RM_C6_REG_7 = 0,
 962   RM_C7_REG_7,
 963   RM_0F01_REG_0,
 964   RM_0F01_REG_1,
 965   RM_0F01_REG_2,
 966   RM_0F01_REG_3,
 967   RM_0F01_REG_5,
 968   RM_0F01_REG_7,
 969   RM_0F1E_MOD_3_REG_7,
 970   RM_0FAE_REG_6,
 971   RM_0FAE_REG_7
 972 };
 973
 974 enum
 975 {
 976   PREFIX_90 = 0,
 977   PREFIX_MOD_0_0F01_REG_5,
 978   PREFIX_MOD_3_0F01_REG_5_RM_0,
 979   PREFIX_MOD_3_0F01_REG_5_RM_2,
 980   PREFIX_0F09,
 981   PREFIX_0F10,
 982   PREFIX_0F11,
 983   PREFIX_0F12,
 984   PREFIX_0F16,
 985   PREFIX_0F1A,
 986   PREFIX_0F1B,
 987   PREFIX_0F1C,
 988   PREFIX_0F1E,
 989   PREFIX_0F2A,
 990   PREFIX_0F2B,
 991   PREFIX_0F2C,
 992   PREFIX_0F2D,
 993   PREFIX_0F2E,
 994   PREFIX_0F2F,
 995   PREFIX_0F51,
 996   PREFIX_0F52,
 997   PREFIX_0F53,
 998   PREFIX_0F58,
 999   PREFIX_0F59,
1000   PREFIX_0F5A,
1001   PREFIX_0F5B,
1002   PREFIX_0F5C,
1003   PREFIX_0F5D,
1004   PREFIX_0F5E,
1005   PREFIX_0F5F,
1006   PREFIX_0F60,
1007   PREFIX_0F61,
1008   PREFIX_0F62,
1009   PREFIX_0F6C,
1010   PREFIX_0F6D,
1011   PREFIX_0F6F,
1012   PREFIX_0F70,
1013   PREFIX_0F73_REG_3,
1014   PREFIX_0F73_REG_7,
1015   PREFIX_0F78,
1016   PREFIX_0F79,
1017   PREFIX_0F7C,
1018   PREFIX_0F7D,
1019   PREFIX_0F7E,
1020   PREFIX_0F7F,
1021   PREFIX_0FAE_REG_0,
1022   PREFIX_0FAE_REG_1,
1023   PREFIX_0FAE_REG_2,
1024   PREFIX_0FAE_REG_3,
1025   PREFIX_MOD_0_0FAE_REG_4,
1026   PREFIX_MOD_3_0FAE_REG_4,
1027   PREFIX_MOD_0_0FAE_REG_5,
1028   PREFIX_MOD_3_0FAE_REG_5,
1029   PREFIX_MOD_0_0FAE_REG_6,
1030   PREFIX_MOD_1_0FAE_REG_6,
1031   PREFIX_0FAE_REG_7,
1032   PREFIX_0FB8,
1033   PREFIX_0FBC,
1034   PREFIX_0FBD,
1035   PREFIX_0FC2,
1036   PREFIX_MOD_0_0FC3,
1037   PREFIX_MOD_0_0FC7_REG_6,
1038   PREFIX_MOD_3_0FC7_REG_6,
1039   PREFIX_MOD_3_0FC7_REG_7,
1040   PREFIX_0FD0,
1041   PREFIX_0FD6,
1042   PREFIX_0FE6,
1043   PREFIX_0FE7,
1044   PREFIX_0FF0,
1045   PREFIX_0FF7,
1046   PREFIX_0F3810,
1047   PREFIX_0F3814,
1048   PREFIX_0F3815,
1049   PREFIX_0F3817,
1050   PREFIX_0F3820,
1051   PREFIX_0F3821,
1052   PREFIX_0F3822,
1053   PREFIX_0F3823,
1054   PREFIX_0F3824,
1055   PREFIX_0F3825,
1056   PREFIX_0F3828,
1057   PREFIX_0F3829,
1058   PREFIX_0F382A,
1059   PREFIX_0F382B,
1060   PREFIX_0F3830,
1061   PREFIX_0F3831,
1062   PREFIX_0F3832,
1063   PREFIX_0F3833,
1064   PREFIX_0F3834,
1065   PREFIX_0F3835,
1066   PREFIX_0F3837,
1067   PREFIX_0F3838,
1068   PREFIX_0F3839,
1069   PREFIX_0F383A,
1070   PREFIX_0F383B,
1071   PREFIX_0F383C,
1072   PREFIX_0F383D,
1073   PREFIX_0F383E,
1074   PREFIX_0F383F,
1075   PREFIX_0F3840,
1076   PREFIX_0F3841,
1077   PREFIX_0F3880,
1078   PREFIX_0F3881,
1079   PREFIX_0F3882,
1080   PREFIX_0F38C8,
1081   PREFIX_0F38C9,
1082   PREFIX_0F38CA,
1083   PREFIX_0F38CB,
1084   PREFIX_0F38CC,
1085   PREFIX_0F38CD,
1086   PREFIX_0F38CF,
1087   PREFIX_0F38DB,
1088   PREFIX_0F38DC,
1089   PREFIX_0F38DD,
1090   PREFIX_0F38DE,
1091   PREFIX_0F38DF,
1092   PREFIX_0F38F0,
1093   PREFIX_0F38F1,
1094   PREFIX_0F38F5,
1095   PREFIX_0F38F6,
1096   PREFIX_0F38F8,
1097   PREFIX_0F38F9,
1098   PREFIX_0F3A08,
1099   PREFIX_0F3A09,
1100   PREFIX_0F3A0A,
1101   PREFIX_0F3A0B,
1102   PREFIX_0F3A0C,
1103   PREFIX_0F3A0D,
1104   PREFIX_0F3A0E,
1105   PREFIX_0F3A14,
1106   PREFIX_0F3A15,
1107   PREFIX_0F3A16,
1108   PREFIX_0F3A17,
1109   PREFIX_0F3A20,
1110   PREFIX_0F3A21,
1111   PREFIX_0F3A22,
1112   PREFIX_0F3A40,
1113   PREFIX_0F3A41,
1114   PREFIX_0F3A42,
1115   PREFIX_0F3A44,
1116   PREFIX_0F3A60,
1117   PREFIX_0F3A61,
1118   PREFIX_0F3A62,
1119   PREFIX_0F3A63,
1120   PREFIX_0F3ACC,
1121   PREFIX_0F3ACE,
1122   PREFIX_0F3ACF,
1123   PREFIX_0F3ADF,
1124   PREFIX_VEX_0F10,
1125   PREFIX_VEX_0F11,
1126   PREFIX_VEX_0F12,
1127   PREFIX_VEX_0F16,
1128   PREFIX_VEX_0F2A,
1129   PREFIX_VEX_0F2C,
1130   PREFIX_VEX_0F2D,
1131   PREFIX_VEX_0F2E,
1132   PREFIX_VEX_0F2F,
1133   PREFIX_VEX_0F41,
1134   PREFIX_VEX_0F42,
1135   PREFIX_VEX_0F44,
1136   PREFIX_VEX_0F45,
1137   PREFIX_VEX_0F46,
1138   PREFIX_VEX_0F47,
1139   PREFIX_VEX_0F4A,
1140   PREFIX_VEX_0F4B,
1141   PREFIX_VEX_0F51,
1142   PREFIX_VEX_0F52,
1143   PREFIX_VEX_0F53,
1144   PREFIX_VEX_0F58,
1145   PREFIX_VEX_0F59,
1146   PREFIX_VEX_0F5A,
1147   PREFIX_VEX_0F5B,
1148   PREFIX_VEX_0F5C,
1149   PREFIX_VEX_0F5D,
1150   PREFIX_VEX_0F5E,
1151   PREFIX_VEX_0F5F,
1152   PREFIX_VEX_0F60,
1153   PREFIX_VEX_0F61,
1154   PREFIX_VEX_0F62,
1155   PREFIX_VEX_0F63,
1156   PREFIX_VEX_0F64,
1157   PREFIX_VEX_0F65,
1158   PREFIX_VEX_0F66,
1159   PREFIX_VEX_0F67,
1160   PREFIX_VEX_0F68,
1161   PREFIX_VEX_0F69,
1162   PREFIX_VEX_0F6A,
1163   PREFIX_VEX_0F6B,
1164   PREFIX_VEX_0F6C,
1165   PREFIX_VEX_0F6D,
1166   PREFIX_VEX_0F6E,
1167   PREFIX_VEX_0F6F,
1168   PREFIX_VEX_0F70,
1169   PREFIX_VEX_0F71_REG_2,
1170   PREFIX_VEX_0F71_REG_4,
1171   PREFIX_VEX_0F71_REG_6,
1172   PREFIX_VEX_0F72_REG_2,
1173   PREFIX_VEX_0F72_REG_4,
1174   PREFIX_VEX_0F72_REG_6,
1175   PREFIX_VEX_0F73_REG_2,
1176   PREFIX_VEX_0F73_REG_3,
1177   PREFIX_VEX_0F73_REG_6,
1178   PREFIX_VEX_0F73_REG_7,
1179   PREFIX_VEX_0F74,
1180   PREFIX_VEX_0F75,
1181   PREFIX_VEX_0F76,
1182   PREFIX_VEX_0F77,
1183   PREFIX_VEX_0F7C,
1184   PREFIX_VEX_0F7D,
1185   PREFIX_VEX_0F7E,
1186   PREFIX_VEX_0F7F,
1187   PREFIX_VEX_0F90,
1188   PREFIX_VEX_0F91,
1189   PREFIX_VEX_0F92,
1190   PREFIX_VEX_0F93,
1191   PREFIX_VEX_0F98,
1192   PREFIX_VEX_0F99,
1193   PREFIX_VEX_0FC2,
1194   PREFIX_VEX_0FC4,
1195   PREFIX_VEX_0FC5,
1196   PREFIX_VEX_0FD0,
1197   PREFIX_VEX_0FD1,
1198   PREFIX_VEX_0FD2,
1199   PREFIX_VEX_0FD3,
1200   PREFIX_VEX_0FD4,
1201   PREFIX_VEX_0FD5,
1202   PREFIX_VEX_0FD6,
1203   PREFIX_VEX_0FD7,
1204   PREFIX_VEX_0FD8,
1205   PREFIX_VEX_0FD9,
1206   PREFIX_VEX_0FDA,
1207   PREFIX_VEX_0FDB,
1208   PREFIX_VEX_0FDC,
1209   PREFIX_VEX_0FDD,
1210   PREFIX_VEX_0FDE,
1211   PREFIX_VEX_0FDF,
1212   PREFIX_VEX_0FE0,
1213   PREFIX_VEX_0FE1,
1214   PREFIX_VEX_0FE2,
1215   PREFIX_VEX_0FE3,
1216   PREFIX_VEX_0FE4,
1217   PREFIX_VEX_0FE5,
1218   PREFIX_VEX_0FE6,
1219   PREFIX_VEX_0FE7,
1220   PREFIX_VEX_0FE8,
1221   PREFIX_VEX_0FE9,
1222   PREFIX_VEX_0FEA,
1223   PREFIX_VEX_0FEB,
1224   PREFIX_VEX_0FEC,
1225   PREFIX_VEX_0FED,
1226   PREFIX_VEX_0FEE,
1227   PREFIX_VEX_0FEF,
1228   PREFIX_VEX_0FF0,
1229   PREFIX_VEX_0FF1,
1230   PREFIX_VEX_0FF2,
1231   PREFIX_VEX_0FF3,
1232   PREFIX_VEX_0FF4,
1233   PREFIX_VEX_0FF5,
1234   PREFIX_VEX_0FF6,
1235   PREFIX_VEX_0FF7,
1236   PREFIX_VEX_0FF8,
1237   PREFIX_VEX_0FF9,
1238   PREFIX_VEX_0FFA,
1239   PREFIX_VEX_0FFB,
1240   PREFIX_VEX_0FFC,
1241   PREFIX_VEX_0FFD,
1242   PREFIX_VEX_0FFE,
1243   PREFIX_VEX_0F3800,
1244   PREFIX_VEX_0F3801,
1245   PREFIX_VEX_0F3802,
1246   PREFIX_VEX_0F3803,
1247   PREFIX_VEX_0F3804,
1248   PREFIX_VEX_0F3805,
1249   PREFIX_VEX_0F3806,
1250   PREFIX_VEX_0F3807,
1251   PREFIX_VEX_0F3808,
1252   PREFIX_VEX_0F3809,
1253   PREFIX_VEX_0F380A,
1254   PREFIX_VEX_0F380B,
1255   PREFIX_VEX_0F380C,
1256   PREFIX_VEX_0F380D,
1257   PREFIX_VEX_0F380E,
1258   PREFIX_VEX_0F380F,
1259   PREFIX_VEX_0F3813,
1260   PREFIX_VEX_0F3816,
1261   PREFIX_VEX_0F3817,
1262   PREFIX_VEX_0F3818,
1263   PREFIX_VEX_0F3819,
1264   PREFIX_VEX_0F381A,
1265   PREFIX_VEX_0F381C,
1266   PREFIX_VEX_0F381D,
1267   PREFIX_VEX_0F381E,
1268   PREFIX_VEX_0F3820,
1269   PREFIX_VEX_0F3821,
1270   PREFIX_VEX_0F3822,
1271   PREFIX_VEX_0F3823,
1272   PREFIX_VEX_0F3824,
1273   PREFIX_VEX_0F3825,
1274   PREFIX_VEX_0F3828,
1275   PREFIX_VEX_0F3829,
1276   PREFIX_VEX_0F382A,
1277   PREFIX_VEX_0F382B,
1278   PREFIX_VEX_0F382C,
1279   PREFIX_VEX_0F382D,
1280   PREFIX_VEX_0F382E,
1281   PREFIX_VEX_0F382F,
1282   PREFIX_VEX_0F3830,
1283   PREFIX_VEX_0F3831,
1284   PREFIX_VEX_0F3832,
1285   PREFIX_VEX_0F3833,
1286   PREFIX_VEX_0F3834,
1287   PREFIX_VEX_0F3835,
1288   PREFIX_VEX_0F3836,
1289   PREFIX_VEX_0F3837,
1290   PREFIX_VEX_0F3838,
1291   PREFIX_VEX_0F3839,
1292   PREFIX_VEX_0F383A,
1293   PREFIX_VEX_0F383B,
1294   PREFIX_VEX_0F383C,
1295   PREFIX_VEX_0F383D,
1296   PREFIX_VEX_0F383E,
1297   PREFIX_VEX_0F383F,
1298   PREFIX_VEX_0F3840,
1299   PREFIX_VEX_0F3841,
1300   PREFIX_VEX_0F3845,
1301   PREFIX_VEX_0F3846,
1302   PREFIX_VEX_0F3847,
1303   PREFIX_VEX_0F3858,
1304   PREFIX_VEX_0F3859,
1305   PREFIX_VEX_0F385A,
1306   PREFIX_VEX_0F3878,
1307   PREFIX_VEX_0F3879,
1308   PREFIX_VEX_0F388C,
1309   PREFIX_VEX_0F388E,
1310   PREFIX_VEX_0F3890,
1311   PREFIX_VEX_0F3891,
1312   PREFIX_VEX_0F3892,
1313   PREFIX_VEX_0F3893,
1314   PREFIX_VEX_0F3896,
1315   PREFIX_VEX_0F3897,
1316   PREFIX_VEX_0F3898,
1317   PREFIX_VEX_0F3899,
1318   PREFIX_VEX_0F389A,
1319   PREFIX_VEX_0F389B,
1320   PREFIX_VEX_0F389C,
1321   PREFIX_VEX_0F389D,
1322   PREFIX_VEX_0F389E,
1323   PREFIX_VEX_0F389F,
1324   PREFIX_VEX_0F38A6,
1325   PREFIX_VEX_0F38A7,
1326   PREFIX_VEX_0F38A8,
1327   PREFIX_VEX_0F38A9,
1328   PREFIX_VEX_0F38AA,
1329   PREFIX_VEX_0F38AB,
1330   PREFIX_VEX_0F38AC,
1331   PREFIX_VEX_0F38AD,
1332   PREFIX_VEX_0F38AE,
1333   PREFIX_VEX_0F38AF,
1334   PREFIX_VEX_0F38B6,
1335   PREFIX_VEX_0F38B7,
1336   PREFIX_VEX_0F38B8,
1337   PREFIX_VEX_0F38B9,
1338   PREFIX_VEX_0F38BA,
1339   PREFIX_VEX_0F38BB,
1340   PREFIX_VEX_0F38BC,
1341   PREFIX_VEX_0F38BD,
1342   PREFIX_VEX_0F38BE,
1343   PREFIX_VEX_0F38BF,
1344   PREFIX_VEX_0F38CF,
1345   PREFIX_VEX_0F38DB,
1346   PREFIX_VEX_0F38DC,
1347   PREFIX_VEX_0F38DD,
1348   PREFIX_VEX_0F38DE,
1349   PREFIX_VEX_0F38DF,
1350   PREFIX_VEX_0F38F2,
1351   PREFIX_VEX_0F38F3_REG_1,
1352   PREFIX_VEX_0F38F3_REG_2,
1353   PREFIX_VEX_0F38F3_REG_3,
1354   PREFIX_VEX_0F38F5,
1355   PREFIX_VEX_0F38F6,
1356   PREFIX_VEX_0F38F7,
1357   PREFIX_VEX_0F3A00,
1358   PREFIX_VEX_0F3A01,
1359   PREFIX_VEX_0F3A02,
1360   PREFIX_VEX_0F3A04,
1361   PREFIX_VEX_0F3A05,
1362   PREFIX_VEX_0F3A06,
1363   PREFIX_VEX_0F3A08,
1364   PREFIX_VEX_0F3A09,
1365   PREFIX_VEX_0F3A0A,
1366   PREFIX_VEX_0F3A0B,
1367   PREFIX_VEX_0F3A0C,
1368   PREFIX_VEX_0F3A0D,
1369   PREFIX_VEX_0F3A0E,
1370   PREFIX_VEX_0F3A0F,
1371   PREFIX_VEX_0F3A14,
1372   PREFIX_VEX_0F3A15,
1373   PREFIX_VEX_0F3A16,
1374   PREFIX_VEX_0F3A17,
1375   PREFIX_VEX_0F3A18,
1376   PREFIX_VEX_0F3A19,
1377   PREFIX_VEX_0F3A1D,
1378   PREFIX_VEX_0F3A20,
1379   PREFIX_VEX_0F3A21,
1380   PREFIX_VEX_0F3A22,
1381   PREFIX_VEX_0F3A30,
1382   PREFIX_VEX_0F3A31,
1383   PREFIX_VEX_0F3A32,
1384   PREFIX_VEX_0F3A33,
1385   PREFIX_VEX_0F3A38,
1386   PREFIX_VEX_0F3A39,
1387   PREFIX_VEX_0F3A40,
1388   PREFIX_VEX_0F3A41,
1389   PREFIX_VEX_0F3A42,
1390   PREFIX_VEX_0F3A44,
1391   PREFIX_VEX_0F3A46,
1392   PREFIX_VEX_0F3A48,
1393   PREFIX_VEX_0F3A49,
1394   PREFIX_VEX_0F3A4A,
1395   PREFIX_VEX_0F3A4B,
1396   PREFIX_VEX_0F3A4C,
1397   PREFIX_VEX_0F3A5C,
1398   PREFIX_VEX_0F3A5D,
1399   PREFIX_VEX_0F3A5E,
1400   PREFIX_VEX_0F3A5F,
1401   PREFIX_VEX_0F3A60,
1402   PREFIX_VEX_0F3A61,
1403   PREFIX_VEX_0F3A62,
1404   PREFIX_VEX_0F3A63,
1405   PREFIX_VEX_0F3A68,
1406   PREFIX_VEX_0F3A69,
1407   PREFIX_VEX_0F3A6A,
1408   PREFIX_VEX_0F3A6B,
1409   PREFIX_VEX_0F3A6C,
1410   PREFIX_VEX_0F3A6D,
1411   PREFIX_VEX_0F3A6E,
1412   PREFIX_VEX_0F3A6F,
1413   PREFIX_VEX_0F3A78,
1414   PREFIX_VEX_0F3A79,
1415   PREFIX_VEX_0F3A7A,
1416   PREFIX_VEX_0F3A7B,
1417   PREFIX_VEX_0F3A7C,
1418   PREFIX_VEX_0F3A7D,
1419   PREFIX_VEX_0F3A7E,
1420   PREFIX_VEX_0F3A7F,
1421   PREFIX_VEX_0F3ACE,
1422   PREFIX_VEX_0F3ACF,
1423   PREFIX_VEX_0F3ADF,
1424   PREFIX_VEX_0F3AF0,
1425
1426   PREFIX_EVEX_0F10,
1427   PREFIX_EVEX_0F11,
1428   PREFIX_EVEX_0F12,
1429   PREFIX_EVEX_0F13,
1430   PREFIX_EVEX_0F14,
1431   PREFIX_EVEX_0F15,
1432   PREFIX_EVEX_0F16,
1433   PREFIX_EVEX_0F17,
1434   PREFIX_EVEX_0F28,
1435   PREFIX_EVEX_0F29,
1436   PREFIX_EVEX_0F2A,
1437   PREFIX_EVEX_0F2B,
1438   PREFIX_EVEX_0F2C,
1439   PREFIX_EVEX_0F2D,
1440   PREFIX_EVEX_0F2E,
1441   PREFIX_EVEX_0F2F,
1442   PREFIX_EVEX_0F51,
1443   PREFIX_EVEX_0F54,
1444   PREFIX_EVEX_0F55,
1445   PREFIX_EVEX_0F56,
1446   PREFIX_EVEX_0F57,
1447   PREFIX_EVEX_0F58,
1448   PREFIX_EVEX_0F59,
1449   PREFIX_EVEX_0F5A,
1450   PREFIX_EVEX_0F5B,
1451   PREFIX_EVEX_0F5C,
1452   PREFIX_EVEX_0F5D,
1453   PREFIX_EVEX_0F5E,
1454   PREFIX_EVEX_0F5F,
1455   PREFIX_EVEX_0F60,
1456   PREFIX_EVEX_0F61,
1457   PREFIX_EVEX_0F62,
1458   PREFIX_EVEX_0F63,
1459   PREFIX_EVEX_0F64,
1460   PREFIX_EVEX_0F65,
1461   PREFIX_EVEX_0F66,
1462   PREFIX_EVEX_0F67,
1463   PREFIX_EVEX_0F68,
1464   PREFIX_EVEX_0F69,
1465   PREFIX_EVEX_0F6A,
1466   PREFIX_EVEX_0F6B,
1467   PREFIX_EVEX_0F6C,
1468   PREFIX_EVEX_0F6D,
1469   PREFIX_EVEX_0F6E,
1470   PREFIX_EVEX_0F6F,
1471   PREFIX_EVEX_0F70,
1472   PREFIX_EVEX_0F71_REG_2,
1473   PREFIX_EVEX_0F71_REG_4,
1474   PREFIX_EVEX_0F71_REG_6,
1475   PREFIX_EVEX_0F72_REG_0,
1476   PREFIX_EVEX_0F72_REG_1,
1477   PREFIX_EVEX_0F72_REG_2,
1478   PREFIX_EVEX_0F72_REG_4,
1479   PREFIX_EVEX_0F72_REG_6,
1480   PREFIX_EVEX_0F73_REG_2,
1481   PREFIX_EVEX_0F73_REG_3,
1482   PREFIX_EVEX_0F73_REG_6,
1483   PREFIX_EVEX_0F73_REG_7,
1484   PREFIX_EVEX_0F74,
1485   PREFIX_EVEX_0F75,
1486   PREFIX_EVEX_0F76,
1487   PREFIX_EVEX_0F78,
1488   PREFIX_EVEX_0F79,
1489   PREFIX_EVEX_0F7A,
1490   PREFIX_EVEX_0F7B,
1491   PREFIX_EVEX_0F7E,
1492   PREFIX_EVEX_0F7F,
1493   PREFIX_EVEX_0FC2,
1494   PREFIX_EVEX_0FC4,
1495   PREFIX_EVEX_0FC5,
1496   PREFIX_EVEX_0FC6,
1497   PREFIX_EVEX_0FD1,
1498   PREFIX_EVEX_0FD2,
1499   PREFIX_EVEX_0FD3,
1500   PREFIX_EVEX_0FD4,
1501   PREFIX_EVEX_0FD5,
1502   PREFIX_EVEX_0FD6,
1503   PREFIX_EVEX_0FD8,
1504   PREFIX_EVEX_0FD9,
1505   PREFIX_EVEX_0FDA,
1506   PREFIX_EVEX_0FDB,
1507   PREFIX_EVEX_0FDC,
1508   PREFIX_EVEX_0FDD,
1509   PREFIX_EVEX_0FDE,
1510   PREFIX_EVEX_0FDF,
1511   PREFIX_EVEX_0FE0,
1512   PREFIX_EVEX_0FE1,
1513   PREFIX_EVEX_0FE2,
1514   PREFIX_EVEX_0FE3,
1515   PREFIX_EVEX_0FE4,
1516   PREFIX_EVEX_0FE5,
1517   PREFIX_EVEX_0FE6,
1518   PREFIX_EVEX_0FE7,
1519   PREFIX_EVEX_0FE8,
1520   PREFIX_EVEX_0FE9,
1521   PREFIX_EVEX_0FEA,
1522   PREFIX_EVEX_0FEB,
1523   PREFIX_EVEX_0FEC,
1524   PREFIX_EVEX_0FED,
1525   PREFIX_EVEX_0FEE,
1526   PREFIX_EVEX_0FEF,
1527   PREFIX_EVEX_0FF1,
1528   PREFIX_EVEX_0FF2,
1529   PREFIX_EVEX_0FF3,
1530   PREFIX_EVEX_0FF4,
1531   PREFIX_EVEX_0FF5,
1532   PREFIX_EVEX_0FF6,
1533   PREFIX_EVEX_0FF8,
1534   PREFIX_EVEX_0FF9,
1535   PREFIX_EVEX_0FFA,
1536   PREFIX_EVEX_0FFB,
1537   PREFIX_EVEX_0FFC,
1538   PREFIX_EVEX_0FFD,
1539   PREFIX_EVEX_0FFE,
1540   PREFIX_EVEX_0F3800,
1541   PREFIX_EVEX_0F3804,
1542   PREFIX_EVEX_0F380B,
1543   PREFIX_EVEX_0F380C,
1544   PREFIX_EVEX_0F380D,
1545   PREFIX_EVEX_0F3810,
1546   PREFIX_EVEX_0F3811,
1547   PREFIX_EVEX_0F3812,
1548   PREFIX_EVEX_0F3813,
1549   PREFIX_EVEX_0F3814,
1550   PREFIX_EVEX_0F3815,
1551   PREFIX_EVEX_0F3816,
1552   PREFIX_EVEX_0F3818,
1553   PREFIX_EVEX_0F3819,
1554   PREFIX_EVEX_0F381A,
1555   PREFIX_EVEX_0F381B,
1556   PREFIX_EVEX_0F381C,
1557   PREFIX_EVEX_0F381D,
1558   PREFIX_EVEX_0F381E,
1559   PREFIX_EVEX_0F381F,
1560   PREFIX_EVEX_0F3820,
1561   PREFIX_EVEX_0F3821,
1562   PREFIX_EVEX_0F3822,
1563   PREFIX_EVEX_0F3823,
1564   PREFIX_EVEX_0F3824,
1565   PREFIX_EVEX_0F3825,
1566   PREFIX_EVEX_0F3826,
1567   PREFIX_EVEX_0F3827,
1568   PREFIX_EVEX_0F3828,
1569   PREFIX_EVEX_0F3829,
1570   PREFIX_EVEX_0F382A,
1571   PREFIX_EVEX_0F382B,
1572   PREFIX_EVEX_0F382C,
1573   PREFIX_EVEX_0F382D,
1574   PREFIX_EVEX_0F3830,
1575   PREFIX_EVEX_0F3831,
1576   PREFIX_EVEX_0F3832,
1577   PREFIX_EVEX_0F3833,
1578   PREFIX_EVEX_0F3834,
1579   PREFIX_EVEX_0F3835,
1580   PREFIX_EVEX_0F3836,
1581   PREFIX_EVEX_0F3837,
1582   PREFIX_EVEX_0F3838,
1583   PREFIX_EVEX_0F3839,
1584   PREFIX_EVEX_0F383A,
1585   PREFIX_EVEX_0F383B,
1586   PREFIX_EVEX_0F383C,
1587   PREFIX_EVEX_0F383D,
1588   PREFIX_EVEX_0F383E,
1589   PREFIX_EVEX_0F383F,
1590   PREFIX_EVEX_0F3840,
1591   PREFIX_EVEX_0F3842,
1592   PREFIX_EVEX_0F3843,
1593   PREFIX_EVEX_0F3844,
1594   PREFIX_EVEX_0F3845,
1595   PREFIX_EVEX_0F3846,
1596   PREFIX_EVEX_0F3847,
1597   PREFIX_EVEX_0F384C,
1598   PREFIX_EVEX_0F384D,
1599   PREFIX_EVEX_0F384E,
1600   PREFIX_EVEX_0F384F,
1601   PREFIX_EVEX_0F3850,
1602   PREFIX_EVEX_0F3851,
1603   PREFIX_EVEX_0F3852,
1604   PREFIX_EVEX_0F3853,
1605   PREFIX_EVEX_0F3854,
1606   PREFIX_EVEX_0F3855,
1607   PREFIX_EVEX_0F3858,
1608   PREFIX_EVEX_0F3859,
1609   PREFIX_EVEX_0F385A,
1610   PREFIX_EVEX_0F385B,
1611   PREFIX_EVEX_0F3862,
1612   PREFIX_EVEX_0F3863,
1613   PREFIX_EVEX_0F3864,
1614   PREFIX_EVEX_0F3865,
1615   PREFIX_EVEX_0F3866,
1616   PREFIX_EVEX_0F3870,
1617   PREFIX_EVEX_0F3871,
1618   PREFIX_EVEX_0F3872,
1619   PREFIX_EVEX_0F3873,
1620   PREFIX_EVEX_0F3875,
1621   PREFIX_EVEX_0F3876,
1622   PREFIX_EVEX_0F3877,
1623   PREFIX_EVEX_0F3878,
1624   PREFIX_EVEX_0F3879,
1625   PREFIX_EVEX_0F387A,
1626   PREFIX_EVEX_0F387B,
1627   PREFIX_EVEX_0F387C,
1628   PREFIX_EVEX_0F387D,
1629   PREFIX_EVEX_0F387E,
1630   PREFIX_EVEX_0F387F,
1631   PREFIX_EVEX_0F3883,
1632   PREFIX_EVEX_0F3888,
1633   PREFIX_EVEX_0F3889,
1634   PREFIX_EVEX_0F388A,
1635   PREFIX_EVEX_0F388B,
1636   PREFIX_EVEX_0F388D,
1637   PREFIX_EVEX_0F388F,
1638   PREFIX_EVEX_0F3890,
1639   PREFIX_EVEX_0F3891,
1640   PREFIX_EVEX_0F3892,
1641   PREFIX_EVEX_0F3893,
1642   PREFIX_EVEX_0F3896,
1643   PREFIX_EVEX_0F3897,
1644   PREFIX_EVEX_0F3898,
1645   PREFIX_EVEX_0F3899,
1646   PREFIX_EVEX_0F389A,
1647   PREFIX_EVEX_0F389B,
1648   PREFIX_EVEX_0F389C,
1649   PREFIX_EVEX_0F389D,
1650   PREFIX_EVEX_0F389E,
1651   PREFIX_EVEX_0F389F,
1652   PREFIX_EVEX_0F38A0,
1653   PREFIX_EVEX_0F38A1,
1654   PREFIX_EVEX_0F38A2,
1655   PREFIX_EVEX_0F38A3,
1656   PREFIX_EVEX_0F38A6,
1657   PREFIX_EVEX_0F38A7,
1658   PREFIX_EVEX_0F38A8,
1659   PREFIX_EVEX_0F38A9,
1660   PREFIX_EVEX_0F38AA,
1661   PREFIX_EVEX_0F38AB,
1662   PREFIX_EVEX_0F38AC,
1663   PREFIX_EVEX_0F38AD,
1664   PREFIX_EVEX_0F38AE,
1665   PREFIX_EVEX_0F38AF,
1666   PREFIX_EVEX_0F38B4,
1667   PREFIX_EVEX_0F38B5,
1668   PREFIX_EVEX_0F38B6,
1669   PREFIX_EVEX_0F38B7,
1670   PREFIX_EVEX_0F38B8,
1671   PREFIX_EVEX_0F38B9,
1672   PREFIX_EVEX_0F38BA,
1673   PREFIX_EVEX_0F38BB,
1674   PREFIX_EVEX_0F38BC,
1675   PREFIX_EVEX_0F38BD,
1676   PREFIX_EVEX_0F38BE,
1677   PREFIX_EVEX_0F38BF,
1678   PREFIX_EVEX_0F38C4,
1679   PREFIX_EVEX_0F38C6_REG_1,
1680   PREFIX_EVEX_0F38C6_REG_2,
1681   PREFIX_EVEX_0F38C6_REG_5,
1682   PREFIX_EVEX_0F38C6_REG_6,
1683   PREFIX_EVEX_0F38C7_REG_1,
1684   PREFIX_EVEX_0F38C7_REG_2,
1685   PREFIX_EVEX_0F38C7_REG_5,
1686   PREFIX_EVEX_0F38C7_REG_6,
1687   PREFIX_EVEX_0F38C8,
1688   PREFIX_EVEX_0F38CA,
1689   PREFIX_EVEX_0F38CB,
1690   PREFIX_EVEX_0F38CC,
1691   PREFIX_EVEX_0F38CD,
1692   PREFIX_EVEX_0F38CF,
1693   PREFIX_EVEX_0F38DC,
1694   PREFIX_EVEX_0F38DD,
1695   PREFIX_EVEX_0F38DE,
1696   PREFIX_EVEX_0F38DF,
1697
1698   PREFIX_EVEX_0F3A00,
1699   PREFIX_EVEX_0F3A01,
1700   PREFIX_EVEX_0F3A03,
1701   PREFIX_EVEX_0F3A04,
1702   PREFIX_EVEX_0F3A05,
1703   PREFIX_EVEX_0F3A08,
1704   PREFIX_EVEX_0F3A09,
1705   PREFIX_EVEX_0F3A0A,
1706   PREFIX_EVEX_0F3A0B,
1707   PREFIX_EVEX_0F3A0F,
1708   PREFIX_EVEX_0F3A14,
1709   PREFIX_EVEX_0F3A15,
1710   PREFIX_EVEX_0F3A16,
1711   PREFIX_EVEX_0F3A17,
1712   PREFIX_EVEX_0F3A18,
1713   PREFIX_EVEX_0F3A19,
1714   PREFIX_EVEX_0F3A1A,
1715   PREFIX_EVEX_0F3A1B,
1716   PREFIX_EVEX_0F3A1D,
1717   PREFIX_EVEX_0F3A1E,
1718   PREFIX_EVEX_0F3A1F,
1719   PREFIX_EVEX_0F3A20,
1720   PREFIX_EVEX_0F3A21,
1721   PREFIX_EVEX_0F3A22,
1722   PREFIX_EVEX_0F3A23,
1723   PREFIX_EVEX_0F3A25,
1724   PREFIX_EVEX_0F3A26,
1725   PREFIX_EVEX_0F3A27,
1726   PREFIX_EVEX_0F3A38,
1727   PREFIX_EVEX_0F3A39,
1728   PREFIX_EVEX_0F3A3A,
1729   PREFIX_EVEX_0F3A3B,
1730   PREFIX_EVEX_0F3A3E,
1731   PREFIX_EVEX_0F3A3F,
1732   PREFIX_EVEX_0F3A42,
1733   PREFIX_EVEX_0F3A43,
1734   PREFIX_EVEX_0F3A44,
1735   PREFIX_EVEX_0F3A50,
1736   PREFIX_EVEX_0F3A51,
1737   PREFIX_EVEX_0F3A54,
1738   PREFIX_EVEX_0F3A55,
1739   PREFIX_EVEX_0F3A56,
1740   PREFIX_EVEX_0F3A57,
1741   PREFIX_EVEX_0F3A66,
1742   PREFIX_EVEX_0F3A67,
1743   PREFIX_EVEX_0F3A70,
1744   PREFIX_EVEX_0F3A71,
1745   PREFIX_EVEX_0F3A72,
1746   PREFIX_EVEX_0F3A73,
1747   PREFIX_EVEX_0F3ACE,
1748   PREFIX_EVEX_0F3ACF
1749 };
1750
1751 enum
1752 {
1753   X86_64_06 = 0,
1754   X86_64_07,
1755   X86_64_0D,
1756   X86_64_16,
1757   X86_64_17,
1758   X86_64_1E,
1759   X86_64_1F,
1760   X86_64_27,
1761   X86_64_2F,
1762   X86_64_37,
1763   X86_64_3F,
1764   X86_64_60,
1765   X86_64_61,
1766   X86_64_62,
1767   X86_64_63,
1768   X86_64_6D,
1769   X86_64_6F,
1770   X86_64_82,
1771   X86_64_9A,
1772   X86_64_C4,
1773   X86_64_C5,
1774   X86_64_CE,
1775   X86_64_D4,
1776   X86_64_D5,
1777   X86_64_E8,
1778   X86_64_E9,
1779   X86_64_EA,
1780   X86_64_0F01_REG_0,
1781   X86_64_0F01_REG_1,
1782   X86_64_0F01_REG_2,
1783   X86_64_0F01_REG_3
1784 };
1785
1786 enum
1787 {
1788   THREE_BYTE_0F38 = 0,
1789   THREE_BYTE_0F3A
1790 };
1791
1792 enum
1793 {
1794   XOP_08 = 0,
1795   XOP_09,
1796   XOP_0A
1797 };
1798
1799 enum
1800 {
1801   VEX_0F = 0,
1802   VEX_0F38,
1803   VEX_0F3A
1804 };
1805
1806 enum
1807 {
1808   EVEX_0F = 0,
1809   EVEX_0F38,
1810   EVEX_0F3A
1811 };
1812
1813 enum
1814 {
1815   VEX_LEN_0F10_P_1 = 0,
1816   VEX_LEN_0F10_P_3,
1817   VEX_LEN_0F11_P_1,
1818   VEX_LEN_0F11_P_3,
1819   VEX_LEN_0F12_P_0_M_0,
1820   VEX_LEN_0F12_P_0_M_1,
1821   VEX_LEN_0F12_P_2,
1822   VEX_LEN_0F13_M_0,
1823   VEX_LEN_0F16_P_0_M_0,
1824   VEX_LEN_0F16_P_0_M_1,
1825   VEX_LEN_0F16_P_2,
1826   VEX_LEN_0F17_M_0,
1827   VEX_LEN_0F2A_P_1,
1828   VEX_LEN_0F2A_P_3,
1829   VEX_LEN_0F2C_P_1,
1830   VEX_LEN_0F2C_P_3,
1831   VEX_LEN_0F2D_P_1,
1832   VEX_LEN_0F2D_P_3,
1833   VEX_LEN_0F2E_P_0,
1834   VEX_LEN_0F2E_P_2,
1835   VEX_LEN_0F2F_P_0,
1836   VEX_LEN_0F2F_P_2,
1837   VEX_LEN_0F41_P_0,
1838   VEX_LEN_0F41_P_2,
1839   VEX_LEN_0F42_P_0,
1840   VEX_LEN_0F42_P_2,
1841   VEX_LEN_0F44_P_0,
1842   VEX_LEN_0F44_P_2,
1843   VEX_LEN_0F45_P_0,
1844   VEX_LEN_0F45_P_2,
1845   VEX_LEN_0F46_P_0,
1846   VEX_LEN_0F46_P_2,
1847   VEX_LEN_0F47_P_0,
1848   VEX_LEN_0F47_P_2,
1849   VEX_LEN_0F4A_P_0,
1850   VEX_LEN_0F4A_P_2,
1851   VEX_LEN_0F4B_P_0,
1852   VEX_LEN_0F4B_P_2,
1853   VEX_LEN_0F51_P_1,
1854   VEX_LEN_0F51_P_3,
1855   VEX_LEN_0F52_P_1,
1856   VEX_LEN_0F53_P_1,
1857   VEX_LEN_0F58_P_1,
1858   VEX_LEN_0F58_P_3,
1859   VEX_LEN_0F59_P_1,
1860   VEX_LEN_0F59_P_3,
1861   VEX_LEN_0F5A_P_1,
1862   VEX_LEN_0F5A_P_3,
1863   VEX_LEN_0F5C_P_1,
1864   VEX_LEN_0F5C_P_3,
1865   VEX_LEN_0F5D_P_1,
1866   VEX_LEN_0F5D_P_3,
1867   VEX_LEN_0F5E_P_1,
1868   VEX_LEN_0F5E_P_3,
1869   VEX_LEN_0F5F_P_1,
1870   VEX_LEN_0F5F_P_3,
1871   VEX_LEN_0F6E_P_2,
1872   VEX_LEN_0F7E_P_1,
1873   VEX_LEN_0F7E_P_2,
1874   VEX_LEN_0F90_P_0,
1875   VEX_LEN_0F90_P_2,
1876   VEX_LEN_0F91_P_0,
1877   VEX_LEN_0F91_P_2,
1878   VEX_LEN_0F92_P_0,
1879   VEX_LEN_0F92_P_2,
1880   VEX_LEN_0F92_P_3,
1881   VEX_LEN_0F93_P_0,
1882   VEX_LEN_0F93_P_2,
1883   VEX_LEN_0F93_P_3,
1884   VEX_LEN_0F98_P_0,
1885   VEX_LEN_0F98_P_2,
1886   VEX_LEN_0F99_P_0,
1887   VEX_LEN_0F99_P_2,
1888   VEX_LEN_0FAE_R_2_M_0,
1889   VEX_LEN_0FAE_R_3_M_0,
1890   VEX_LEN_0FC2_P_1,
1891   VEX_LEN_0FC2_P_3,
1892   VEX_LEN_0FC4_P_2,
1893   VEX_LEN_0FC5_P_2,
1894   VEX_LEN_0FD6_P_2,
1895   VEX_LEN_0FF7_P_2,
1896   VEX_LEN_0F3816_P_2,
1897   VEX_LEN_0F3819_P_2,
1898   VEX_LEN_0F381A_P_2_M_0,
1899   VEX_LEN_0F3836_P_2,
1900   VEX_LEN_0F3841_P_2,
1901   VEX_LEN_0F385A_P_2_M_0,
1902   VEX_LEN_0F38DB_P_2,
1903   VEX_LEN_0F38F2_P_0,
1904   VEX_LEN_0F38F3_R_1_P_0,
1905   VEX_LEN_0F38F3_R_2_P_0,
1906   VEX_LEN_0F38F3_R_3_P_0,
1907   VEX_LEN_0F38F5_P_0,
1908   VEX_LEN_0F38F5_P_1,
1909   VEX_LEN_0F38F5_P_3,
1910   VEX_LEN_0F38F6_P_3,
1911   VEX_LEN_0F38F7_P_0,
1912   VEX_LEN_0F38F7_P_1,
1913   VEX_LEN_0F38F7_P_2,
1914   VEX_LEN_0F38F7_P_3,
1915   VEX_LEN_0F3A00_P_2,
1916   VEX_LEN_0F3A01_P_2,
1917   VEX_LEN_0F3A06_P_2,
1918   VEX_LEN_0F3A0A_P_2,
1919   VEX_LEN_0F3A0B_P_2,
1920   VEX_LEN_0F3A14_P_2,
1921   VEX_LEN_0F3A15_P_2,
1922   VEX_LEN_0F3A16_P_2,
1923   VEX_LEN_0F3A17_P_2,
1924   VEX_LEN_0F3A18_P_2,
1925   VEX_LEN_0F3A19_P_2,
1926   VEX_LEN_0F3A20_P_2,
1927   VEX_LEN_0F3A21_P_2,
1928   VEX_LEN_0F3A22_P_2,
1929   VEX_LEN_0F3A30_P_2,
1930   VEX_LEN_0F3A31_P_2,
1931   VEX_LEN_0F3A32_P_2,
1932   VEX_LEN_0F3A33_P_2,
1933   VEX_LEN_0F3A38_P_2,
1934   VEX_LEN_0F3A39_P_2,
1935   VEX_LEN_0F3A41_P_2,
1936   VEX_LEN_0F3A46_P_2,
1937   VEX_LEN_0F3A60_P_2,
1938   VEX_LEN_0F3A61_P_2,
1939   VEX_LEN_0F3A62_P_2,
1940   VEX_LEN_0F3A63_P_2,
1941   VEX_LEN_0F3A6A_P_2,
1942   VEX_LEN_0F3A6B_P_2,
1943   VEX_LEN_0F3A6E_P_2,
1944   VEX_LEN_0F3A6F_P_2,
1945   VEX_LEN_0F3A7A_P_2,
1946   VEX_LEN_0F3A7B_P_2,
1947   VEX_LEN_0F3A7E_P_2,
1948   VEX_LEN_0F3A7F_P_2,
1949   VEX_LEN_0F3ADF_P_2,
1950   VEX_LEN_0F3AF0_P_3,
1951   VEX_LEN_0FXOP_08_CC,
1952   VEX_LEN_0FXOP_08_CD,
1953   VEX_LEN_0FXOP_08_CE,
1954   VEX_LEN_0FXOP_08_CF,
1955   VEX_LEN_0FXOP_08_EC,
1956   VEX_LEN_0FXOP_08_ED,
1957   VEX_LEN_0FXOP_08_EE,
1958   VEX_LEN_0FXOP_08_EF,
1959   VEX_LEN_0FXOP_09_80,
1960   VEX_LEN_0FXOP_09_81
1961 };
1962
1963 enum
1964 {
1965   VEX_W_0F10_P_0 = 0,
1966   VEX_W_0F10_P_1,
1967   VEX_W_0F10_P_2,
1968   VEX_W_0F10_P_3,
1969   VEX_W_0F11_P_0,
1970   VEX_W_0F11_P_1,
1971   VEX_W_0F11_P_2,
1972   VEX_W_0F11_P_3,
1973   VEX_W_0F12_P_0_M_0,
1974   VEX_W_0F12_P_0_M_1,
1975   VEX_W_0F12_P_1,
1976   VEX_W_0F12_P_2,
1977   VEX_W_0F12_P_3,
1978   VEX_W_0F13_M_0,
1979   VEX_W_0F14,
1980   VEX_W_0F15,
1981   VEX_W_0F16_P_0_M_0,
1982   VEX_W_0F16_P_0_M_1,
1983   VEX_W_0F16_P_1,
1984   VEX_W_0F16_P_2,
1985   VEX_W_0F17_M_0,
1986   VEX_W_0F28,
1987   VEX_W_0F29,
1988   VEX_W_0F2B_M_0,
1989   VEX_W_0F2E_P_0,
1990   VEX_W_0F2E_P_2,
1991   VEX_W_0F2F_P_0,
1992   VEX_W_0F2F_P_2,
1993   VEX_W_0F41_P_0_LEN_1,
1994   VEX_W_0F41_P_2_LEN_1,
1995   VEX_W_0F42_P_0_LEN_1,
1996   VEX_W_0F42_P_2_LEN_1,
1997   VEX_W_0F44_P_0_LEN_0,
1998   VEX_W_0F44_P_2_LEN_0,
1999   VEX_W_0F45_P_0_LEN_1,
2000   VEX_W_0F45_P_2_LEN_1,
2001   VEX_W_0F46_P_0_LEN_1,
2002   VEX_W_0F46_P_2_LEN_1,
2003   VEX_W_0F47_P_0_LEN_1,
2004   VEX_W_0F47_P_2_LEN_1,
2005   VEX_W_0F4A_P_0_LEN_1,
2006   VEX_W_0F4A_P_2_LEN_1,
2007   VEX_W_0F4B_P_0_LEN_1,
2008   VEX_W_0F4B_P_2_LEN_1,
2009   VEX_W_0F50_M_0,
2010   VEX_W_0F51_P_0,
2011   VEX_W_0F51_P_1,
2012   VEX_W_0F51_P_2,
2013   VEX_W_0F51_P_3,
2014   VEX_W_0F52_P_0,
2015   VEX_W_0F52_P_1,
2016   VEX_W_0F53_P_0,
2017   VEX_W_0F53_P_1,
2018   VEX_W_0F58_P_0,
2019   VEX_W_0F58_P_1,
2020   VEX_W_0F58_P_2,
2021   VEX_W_0F58_P_3,
2022   VEX_W_0F59_P_0,
2023   VEX_W_0F59_P_1,
2024   VEX_W_0F59_P_2,
2025   VEX_W_0F59_P_3,
2026   VEX_W_0F5A_P_0,
2027   VEX_W_0F5A_P_1,
2028   VEX_W_0F5A_P_3,
2029   VEX_W_0F5B_P_0,
2030   VEX_W_0F5B_P_1,
2031   VEX_W_0F5B_P_2,
2032   VEX_W_0F5C_P_0,
2033   VEX_W_0F5C_P_1,
2034   VEX_W_0F5C_P_2,
2035   VEX_W_0F5C_P_3,
2036   VEX_W_0F5D_P_0,
2037   VEX_W_0F5D_P_1,
2038   VEX_W_0F5D_P_2,
2039   VEX_W_0F5D_P_3,
2040   VEX_W_0F5E_P_0,
2041   VEX_W_0F5E_P_1,
2042   VEX_W_0F5E_P_2,
2043   VEX_W_0F5E_P_3,
2044   VEX_W_0F5F_P_0,
2045   VEX_W_0F5F_P_1,
2046   VEX_W_0F5F_P_2,
2047   VEX_W_0F5F_P_3,
2048   VEX_W_0F60_P_2,
2049   VEX_W_0F61_P_2,
2050   VEX_W_0F62_P_2,
2051   VEX_W_0F63_P_2,
2052   VEX_W_0F64_P_2,
2053   VEX_W_0F65_P_2,
2054   VEX_W_0F66_P_2,
2055   VEX_W_0F67_P_2,
2056   VEX_W_0F68_P_2,
2057   VEX_W_0F69_P_2,
2058   VEX_W_0F6A_P_2,
2059   VEX_W_0F6B_P_2,
2060   VEX_W_0F6C_P_2,
2061   VEX_W_0F6D_P_2,
2062   VEX_W_0F6F_P_1,
2063   VEX_W_0F6F_P_2,
2064   VEX_W_0F70_P_1,
2065   VEX_W_0F70_P_2,
2066   VEX_W_0F70_P_3,
2067   VEX_W_0F71_R_2_P_2,
2068   VEX_W_0F71_R_4_P_2,
2069   VEX_W_0F71_R_6_P_2,
2070   VEX_W_0F72_R_2_P_2,
2071   VEX_W_0F72_R_4_P_2,
2072   VEX_W_0F72_R_6_P_2,
2073   VEX_W_0F73_R_2_P_2,
2074   VEX_W_0F73_R_3_P_2,
2075   VEX_W_0F73_R_6_P_2,
2076   VEX_W_0F73_R_7_P_2,
2077   VEX_W_0F74_P_2,
2078   VEX_W_0F75_P_2,
2079   VEX_W_0F76_P_2,
2080   VEX_W_0F77_P_0,
2081   VEX_W_0F7C_P_2,
2082   VEX_W_0F7C_P_3,
2083   VEX_W_0F7D_P_2,
2084   VEX_W_0F7D_P_3,
2085   VEX_W_0F7E_P_1,
2086   VEX_W_0F7F_P_1,
2087   VEX_W_0F7F_P_2,
2088   VEX_W_0F90_P_0_LEN_0,
2089   VEX_W_0F90_P_2_LEN_0,
2090   VEX_W_0F91_P_0_LEN_0,
2091   VEX_W_0F91_P_2_LEN_0,
2092   VEX_W_0F92_P_0_LEN_0,
2093   VEX_W_0F92_P_2_LEN_0,
2094   VEX_W_0F92_P_3_LEN_0,
2095   VEX_W_0F93_P_0_LEN_0,
2096   VEX_W_0F93_P_2_LEN_0,
2097   VEX_W_0F93_P_3_LEN_0,
2098   VEX_W_0F98_P_0_LEN_0,
2099   VEX_W_0F98_P_2_LEN_0,
2100   VEX_W_0F99_P_0_LEN_0,
2101   VEX_W_0F99_P_2_LEN_0,
2102   VEX_W_0FAE_R_2_M_0,
2103   VEX_W_0FAE_R_3_M_0,
2104   VEX_W_0FC2_P_0,
2105   VEX_W_0FC2_P_1,
2106   VEX_W_0FC2_P_2,
2107   VEX_W_0FC2_P_3,
2108   VEX_W_0FC4_P_2,
2109   VEX_W_0FC5_P_2,
2110   VEX_W_0FD0_P_2,
2111   VEX_W_0FD0_P_3,
2112   VEX_W_0FD1_P_2,
2113   VEX_W_0FD2_P_2,
2114   VEX_W_0FD3_P_2,
2115   VEX_W_0FD4_P_2,
2116   VEX_W_0FD5_P_2,
2117   VEX_W_0FD6_P_2,
2118   VEX_W_0FD7_P_2_M_1,
2119   VEX_W_0FD8_P_2,
2120   VEX_W_0FD9_P_2,
2121   VEX_W_0FDA_P_2,
2122   VEX_W_0FDB_P_2,
2123   VEX_W_0FDC_P_2,
2124   VEX_W_0FDD_P_2,
2125   VEX_W_0FDE_P_2,
2126   VEX_W_0FDF_P_2,
2127   VEX_W_0FE0_P_2,
2128   VEX_W_0FE1_P_2,
2129   VEX_W_0FE2_P_2,
2130   VEX_W_0FE3_P_2,
2131   VEX_W_0FE4_P_2,
2132   VEX_W_0FE5_P_2,
2133   VEX_W_0FE6_P_1,
2134   VEX_W_0FE6_P_2,
2135   VEX_W_0FE6_P_3,
2136   VEX_W_0FE7_P_2_M_0,
2137   VEX_W_0FE8_P_2,
2138   VEX_W_0FE9_P_2,
2139   VEX_W_0FEA_P_2,
2140   VEX_W_0FEB_P_2,
2141   VEX_W_0FEC_P_2,
2142   VEX_W_0FED_P_2,
2143   VEX_W_0FEE_P_2,
2144   VEX_W_0FEF_P_2,
2145   VEX_W_0FF0_P_3_M_0,
2146   VEX_W_0FF1_P_2,
2147   VEX_W_0FF2_P_2,
2148   VEX_W_0FF3_P_2,
2149   VEX_W_0FF4_P_2,
2150   VEX_W_0FF5_P_2,
2151   VEX_W_0FF6_P_2,
2152   VEX_W_0FF7_P_2,
2153   VEX_W_0FF8_P_2,
2154   VEX_W_0FF9_P_2,
2155   VEX_W_0FFA_P_2,
2156   VEX_W_0FFB_P_2,
2157   VEX_W_0FFC_P_2,
2158   VEX_W_0FFD_P_2,
2159   VEX_W_0FFE_P_2,
2160   VEX_W_0F3800_P_2,
2161   VEX_W_0F3801_P_2,
2162   VEX_W_0F3802_P_2,
2163   VEX_W_0F3803_P_2,
2164   VEX_W_0F3804_P_2,
2165   VEX_W_0F3805_P_2,
2166   VEX_W_0F3806_P_2,
2167   VEX_W_0F3807_P_2,
2168   VEX_W_0F3808_P_2,
2169   VEX_W_0F3809_P_2,
2170   VEX_W_0F380A_P_2,
2171   VEX_W_0F380B_P_2,
2172   VEX_W_0F380C_P_2,
2173   VEX_W_0F380D_P_2,
2174   VEX_W_0F380E_P_2,
2175   VEX_W_0F380F_P_2,
2176   VEX_W_0F3816_P_2,
2177   VEX_W_0F3817_P_2,
2178   VEX_W_0F3818_P_2,
2179   VEX_W_0F3819_P_2,
2180   VEX_W_0F381A_P_2_M_0,
2181   VEX_W_0F381C_P_2,
2182   VEX_W_0F381D_P_2,
2183   VEX_W_0F381E_P_2,
2184   VEX_W_0F3820_P_2,
2185   VEX_W_0F3821_P_2,
2186   VEX_W_0F3822_P_2,
2187   VEX_W_0F3823_P_2,
2188   VEX_W_0F3824_P_2,
2189   VEX_W_0F3825_P_2,
2190   VEX_W_0F3828_P_2,
2191   VEX_W_0F3829_P_2,
2192   VEX_W_0F382A_P_2_M_0,
2193   VEX_W_0F382B_P_2,
2194   VEX_W_0F382C_P_2_M_0,
2195   VEX_W_0F382D_P_2_M_0,
2196   VEX_W_0F382E_P_2_M_0,
2197   VEX_W_0F382F_P_2_M_0,
2198   VEX_W_0F3830_P_2,
2199   VEX_W_0F3831_P_2,
2200   VEX_W_0F3832_P_2,
2201   VEX_W_0F3833_P_2,
2202   VEX_W_0F3834_P_2,
2203   VEX_W_0F3835_P_2,
2204   VEX_W_0F3836_P_2,
2205   VEX_W_0F3837_P_2,
2206   VEX_W_0F3838_P_2,
2207   VEX_W_0F3839_P_2,
2208   VEX_W_0F383A_P_2,
2209   VEX_W_0F383B_P_2,
2210   VEX_W_0F383C_P_2,
2211   VEX_W_0F383D_P_2,
2212   VEX_W_0F383E_P_2,
2213   VEX_W_0F383F_P_2,
2214   VEX_W_0F3840_P_2,
2215   VEX_W_0F3841_P_2,
2216   VEX_W_0F3846_P_2,
2217   VEX_W_0F3858_P_2,
2218   VEX_W_0F3859_P_2,
2219   VEX_W_0F385A_P_2_M_0,
2220   VEX_W_0F3878_P_2,
2221   VEX_W_0F3879_P_2,
2222   VEX_W_0F38CF_P_2,
2223   VEX_W_0F38DB_P_2,
2224   VEX_W_0F3A00_P_2,
2225   VEX_W_0F3A01_P_2,
2226   VEX_W_0F3A02_P_2,
2227   VEX_W_0F3A04_P_2,
2228   VEX_W_0F3A05_P_2,
2229   VEX_W_0F3A06_P_2,
2230   VEX_W_0F3A08_P_2,
2231   VEX_W_0F3A09_P_2,
2232   VEX_W_0F3A0A_P_2,
2233   VEX_W_0F3A0B_P_2,
2234   VEX_W_0F3A0C_P_2,
2235   VEX_W_0F3A0D_P_2,
2236   VEX_W_0F3A0E_P_2,
2237   VEX_W_0F3A0F_P_2,
2238   VEX_W_0F3A14_P_2,
2239   VEX_W_0F3A15_P_2,
2240   VEX_W_0F3A18_P_2,
2241   VEX_W_0F3A19_P_2,
2242   VEX_W_0F3A20_P_2,
2243   VEX_W_0F3A21_P_2,
2244   VEX_W_0F3A30_P_2_LEN_0,
2245   VEX_W_0F3A31_P_2_LEN_0,
2246   VEX_W_0F3A32_P_2_LEN_0,
2247   VEX_W_0F3A33_P_2_LEN_0,
2248   VEX_W_0F3A38_P_2,
2249   VEX_W_0F3A39_P_2,
2250   VEX_W_0F3A40_P_2,
2251   VEX_W_0F3A41_P_2,
2252   VEX_W_0F3A42_P_2,
2253   VEX_W_0F3A46_P_2,
2254   VEX_W_0F3A48_P_2,
2255   VEX_W_0F3A49_P_2,
2256   VEX_W_0F3A4A_P_2,
2257   VEX_W_0F3A4B_P_2,
2258   VEX_W_0F3A4C_P_2,
2259   VEX_W_0F3A62_P_2,
2260   VEX_W_0F3A63_P_2,
2261   VEX_W_0F3ACE_P_2,
2262   VEX_W_0F3ACF_P_2,
2263   VEX_W_0F3ADF_P_2,
2264
2265   EVEX_W_0F10_P_0,
2266   EVEX_W_0F10_P_1_M_0,
2267   EVEX_W_0F10_P_1_M_1,
2268   EVEX_W_0F10_P_2,
2269   EVEX_W_0F10_P_3_M_0,
2270   EVEX_W_0F10_P_3_M_1,
2271   EVEX_W_0F11_P_0,
2272   EVEX_W_0F11_P_1_M_0,
2273   EVEX_W_0F11_P_1_M_1,
2274   EVEX_W_0F11_P_2,
2275   EVEX_W_0F11_P_3_M_0,
2276   EVEX_W_0F11_P_3_M_1,
2277   EVEX_W_0F12_P_0_M_0,
2278   EVEX_W_0F12_P_0_M_1,
2279   EVEX_W_0F12_P_1,
2280   EVEX_W_0F12_P_2,
2281   EVEX_W_0F12_P_3,
2282   EVEX_W_0F13_P_0,
2283   EVEX_W_0F13_P_2,
2284   EVEX_W_0F14_P_0,
2285   EVEX_W_0F14_P_2,
2286   EVEX_W_0F15_P_0,
2287   EVEX_W_0F15_P_2,
2288   EVEX_W_0F16_P_0_M_0,
2289   EVEX_W_0F16_P_0_M_1,
2290   EVEX_W_0F16_P_1,
2291   EVEX_W_0F16_P_2,
2292   EVEX_W_0F17_P_0,
2293   EVEX_W_0F17_P_2,
2294   EVEX_W_0F28_P_0,
2295   EVEX_W_0F28_P_2,
2296   EVEX_W_0F29_P_0,
2297   EVEX_W_0F29_P_2,
2298   EVEX_W_0F2A_P_1,
2299   EVEX_W_0F2A_P_3,
2300   EVEX_W_0F2B_P_0,
2301   EVEX_W_0F2B_P_2,
2302   EVEX_W_0F2E_P_0,
2303   EVEX_W_0F2E_P_2,
2304   EVEX_W_0F2F_P_0,
2305   EVEX_W_0F2F_P_2,
2306   EVEX_W_0F51_P_0,
2307   EVEX_W_0F51_P_1,
2308   EVEX_W_0F51_P_2,
2309   EVEX_W_0F51_P_3,
2310   EVEX_W_0F54_P_0,
2311   EVEX_W_0F54_P_2,
2312   EVEX_W_0F55_P_0,
2313   EVEX_W_0F55_P_2,
2314   EVEX_W_0F56_P_0,
2315   EVEX_W_0F56_P_2,
2316   EVEX_W_0F57_P_0,
2317   EVEX_W_0F57_P_2,
2318   EVEX_W_0F58_P_0,
2319   EVEX_W_0F58_P_1,
2320   EVEX_W_0F58_P_2,
2321   EVEX_W_0F58_P_3,
2322   EVEX_W_0F59_P_0,
2323   EVEX_W_0F59_P_1,
2324   EVEX_W_0F59_P_2,
2325   EVEX_W_0F59_P_3,
2326   EVEX_W_0F5A_P_0,
2327   EVEX_W_0F5A_P_1,
2328   EVEX_W_0F5A_P_2,
2329   EVEX_W_0F5A_P_3,
2330   EVEX_W_0F5B_P_0,
2331   EVEX_W_0F5B_P_1,
2332   EVEX_W_0F5B_P_2,
2333   EVEX_W_0F5C_P_0,
2334   EVEX_W_0F5C_P_1,
2335   EVEX_W_0F5C_P_2,
2336   EVEX_W_0F5C_P_3,
2337   EVEX_W_0F5D_P_0,
2338   EVEX_W_0F5D_P_1,
2339   EVEX_W_0F5D_P_2,
2340   EVEX_W_0F5D_P_3,
2341   EVEX_W_0F5E_P_0,
2342   EVEX_W_0F5E_P_1,
2343   EVEX_W_0F5E_P_2,
2344   EVEX_W_0F5E_P_3,
2345   EVEX_W_0F5F_P_0,
2346   EVEX_W_0F5F_P_1,
2347   EVEX_W_0F5F_P_2,
2348   EVEX_W_0F5F_P_3,
2349   EVEX_W_0F62_P_2,
2350   EVEX_W_0F66_P_2,
2351   EVEX_W_0F6A_P_2,
2352   EVEX_W_0F6B_P_2,
2353   EVEX_W_0F6C_P_2,
2354   EVEX_W_0F6D_P_2,
2355   EVEX_W_0F6E_P_2,
2356   EVEX_W_0F6F_P_1,
2357   EVEX_W_0F6F_P_2,
2358   EVEX_W_0F6F_P_3,
2359   EVEX_W_0F70_P_2,
2360   EVEX_W_0F72_R_2_P_2,
2361   EVEX_W_0F72_R_6_P_2,
2362   EVEX_W_0F73_R_2_P_2,
2363   EVEX_W_0F73_R_6_P_2,
2364   EVEX_W_0F76_P_2,
2365   EVEX_W_0F78_P_0,
2366   EVEX_W_0F78_P_2,
2367   EVEX_W_0F79_P_0,
2368   EVEX_W_0F79_P_2,
2369   EVEX_W_0F7A_P_1,
2370   EVEX_W_0F7A_P_2,
2371   EVEX_W_0F7A_P_3,
2372   EVEX_W_0F7B_P_1,
2373   EVEX_W_0F7B_P_2,
2374   EVEX_W_0F7B_P_3,
2375   EVEX_W_0F7E_P_1,
2376   EVEX_W_0F7E_P_2,
2377   EVEX_W_0F7F_P_1,
2378   EVEX_W_0F7F_P_2,
2379   EVEX_W_0F7F_P_3,
2380   EVEX_W_0FC2_P_0,
2381   EVEX_W_0FC2_P_1,
2382   EVEX_W_0FC2_P_2,
2383   EVEX_W_0FC2_P_3,
2384   EVEX_W_0FC6_P_0,
2385   EVEX_W_0FC6_P_2,
2386   EVEX_W_0FD2_P_2,
2387   EVEX_W_0FD3_P_2,
2388   EVEX_W_0FD4_P_2,
2389   EVEX_W_0FD6_P_2,
2390   EVEX_W_0FE6_P_1,
2391   EVEX_W_0FE6_P_2,
2392   EVEX_W_0FE6_P_3,
2393   EVEX_W_0FE7_P_2,
2394   EVEX_W_0FF2_P_2,
2395   EVEX_W_0FF3_P_2,
2396   EVEX_W_0FF4_P_2,
2397   EVEX_W_0FFA_P_2,
2398   EVEX_W_0FFB_P_2,
2399   EVEX_W_0FFE_P_2,
2400   EVEX_W_0F380C_P_2,
2401   EVEX_W_0F380D_P_2,
2402   EVEX_W_0F3810_P_1,
2403   EVEX_W_0F3810_P_2,
2404   EVEX_W_0F3811_P_1,
2405   EVEX_W_0F3811_P_2,
2406   EVEX_W_0F3812_P_1,
2407   EVEX_W_0F3812_P_2,
2408   EVEX_W_0F3813_P_1,
2409   EVEX_W_0F3813_P_2,
2410   EVEX_W_0F3814_P_1,
2411   EVEX_W_0F3815_P_1,
2412   EVEX_W_0F3818_P_2,
2413   EVEX_W_0F3819_P_2,
2414   EVEX_W_0F381A_P_2,
2415   EVEX_W_0F381B_P_2,
2416   EVEX_W_0F381E_P_2,
2417   EVEX_W_0F381F_P_2,
2418   EVEX_W_0F3820_P_1,
2419   EVEX_W_0F3821_P_1,
2420   EVEX_W_0F3822_P_1,
2421   EVEX_W_0F3823_P_1,
2422   EVEX_W_0F3824_P_1,
2423   EVEX_W_0F3825_P_1,
2424   EVEX_W_0F3825_P_2,
2425   EVEX_W_0F3826_P_1,
2426   EVEX_W_0F3826_P_2,
2427   EVEX_W_0F3828_P_1,
2428   EVEX_W_0F3828_P_2,
2429   EVEX_W_0F3829_P_1,
2430   EVEX_W_0F3829_P_2,
2431   EVEX_W_0F382A_P_1,
2432   EVEX_W_0F382A_P_2,
2433   EVEX_W_0F382B_P_2,
2434   EVEX_W_0F3830_P_1,
2435   EVEX_W_0F3831_P_1,
2436   EVEX_W_0F3832_P_1,
2437   EVEX_W_0F3833_P_1,
2438   EVEX_W_0F3834_P_1,
2439   EVEX_W_0F3835_P_1,
2440   EVEX_W_0F3835_P_2,
2441   EVEX_W_0F3837_P_2,
2442   EVEX_W_0F3838_P_1,
2443   EVEX_W_0F3839_P_1,
2444   EVEX_W_0F383A_P_1,
2445   EVEX_W_0F3840_P_2,
2446   EVEX_W_0F3854_P_2,
2447   EVEX_W_0F3855_P_2,
2448   EVEX_W_0F3858_P_2,
2449   EVEX_W_0F3859_P_2,
2450   EVEX_W_0F385A_P_2,
2451   EVEX_W_0F385B_P_2,
2452   EVEX_W_0F3862_P_2,
2453   EVEX_W_0F3863_P_2,
2454   EVEX_W_0F3866_P_2,
2455   EVEX_W_0F3870_P_2,
2456   EVEX_W_0F3871_P_2,
2457   EVEX_W_0F3872_P_2,
2458   EVEX_W_0F3873_P_2,
2459   EVEX_W_0F3875_P_2,
2460   EVEX_W_0F3878_P_2,
2461   EVEX_W_0F3879_P_2,
2462   EVEX_W_0F387A_P_2,
2463   EVEX_W_0F387B_P_2,
2464   EVEX_W_0F387D_P_2,
2465   EVEX_W_0F3883_P_2,
2466   EVEX_W_0F388D_P_2,
2467   EVEX_W_0F3891_P_2,
2468   EVEX_W_0F3893_P_2,
2469   EVEX_W_0F38A1_P_2,
2470   EVEX_W_0F38A3_P_2,
2471   EVEX_W_0F38C7_R_1_P_2,
2472   EVEX_W_0F38C7_R_2_P_2,
2473   EVEX_W_0F38C7_R_5_P_2,
2474   EVEX_W_0F38C7_R_6_P_2,
2475
2476   EVEX_W_0F3A00_P_2,
2477   EVEX_W_0F3A01_P_2,
2478   EVEX_W_0F3A04_P_2,
2479   EVEX_W_0F3A05_P_2,
2480   EVEX_W_0F3A08_P_2,
2481   EVEX_W_0F3A09_P_2,
2482   EVEX_W_0F3A0A_P_2,
2483   EVEX_W_0F3A0B_P_2,
2484   EVEX_W_0F3A16_P_2,
2485   EVEX_W_0F3A18_P_2,
2486   EVEX_W_0F3A19_P_2,
2487   EVEX_W_0F3A1A_P_2,
2488   EVEX_W_0F3A1B_P_2,
2489   EVEX_W_0F3A1D_P_2,
2490   EVEX_W_0F3A21_P_2,
2491   EVEX_W_0F3A22_P_2,
2492   EVEX_W_0F3A23_P_2,
2493   EVEX_W_0F3A38_P_2,
2494   EVEX_W_0F3A39_P_2,
2495   EVEX_W_0F3A3A_P_2,
2496   EVEX_W_0F3A3B_P_2,
2497   EVEX_W_0F3A3E_P_2,
2498   EVEX_W_0F3A3F_P_2,
2499   EVEX_W_0F3A42_P_2,
2500   EVEX_W_0F3A43_P_2,
2501   EVEX_W_0F3A50_P_2,
2502   EVEX_W_0F3A51_P_2,
2503   EVEX_W_0F3A56_P_2,
2504   EVEX_W_0F3A57_P_2,
2505   EVEX_W_0F3A66_P_2,
2506   EVEX_W_0F3A67_P_2,
2507   EVEX_W_0F3A70_P_2,
2508   EVEX_W_0F3A71_P_2,
2509   EVEX_W_0F3A72_P_2,
2510   EVEX_W_0F3A73_P_2,
2511   EVEX_W_0F3ACE_P_2,
2512   EVEX_W_0F3ACF_P_2
2513 };
2514
2515 typedef void (*op_rtn) (int bytemode, int sizeflag);
2516
2517 struct dis386 {
2518   const char *name;
2519   struct
2520     {
2521       op_rtn rtn;
2522       int bytemode;
2523     } op[MAX_OPERANDS];
2524   unsigned int prefix_requirement;
2525 };
2526
2527 /* Upper case letters in the instruction names here are macros.
2528    'A' => print 'b' if no register operands or suffix_always is true
2529    'B' => print 'b' if suffix_always is true
2530    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2531           size prefix
2532    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2533           suffix_always is true
2534    'E' => print 'e' if 32-bit form of jcxz
2535    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2536    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2537    'H' => print ",pt" or ",pn" branch hint
2538    'I' => honor following macro letter even in Intel mode (implemented only
2539           for some of the macro letters)
2540    'J' => print 'l'
2541    'K' => print 'd' or 'q' if rex prefix is present.
2542    'L' => print 'l' if suffix_always is true
2543    'M' => print 'r' if intel_mnemonic is false.
2544    'N' => print 'n' if instruction has no wait "prefix"
2545    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2546    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2547           or suffix_always is true.  print 'q' if rex prefix is present.
2548    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2549           is true
2550    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2551    'S' => print 'w', 'l' or 'q' if suffix_always is true
2552    'T' => print 'q' in 64bit mode if instruction has no operand size
2553           prefix and behave as 'P' otherwise
2554    'U' => print 'q' in 64bit mode if instruction has no operand size
2555           prefix and behave as 'Q' otherwise
2556    'V' => print 'q' in 64bit mode if instruction has no operand size
2557           prefix and behave as 'S' otherwise
2558    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2559    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2560    'Y' unused.
2561    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2562    '!' => change condition from true to false or from false to true.
2563    '%' => add 1 upper case letter to the macro.
2564    '^' => print 'w' or 'l' depending on operand size prefix or
2565           suffix_always is true (lcall/ljmp).
2566    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2567           on operand size prefix.
2568    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2569           has no operand size prefix for AMD64 ISA, behave as 'P'
2570           otherwise
2571
2572    2 upper case letter macros:
2573    "XY" => print 'x' or 'y' if suffix_always is true or no register
2574            operands and no broadcast.
2575    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2576            register operands and no broadcast.
2577    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2578    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2579            or suffix_always is true
2580    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2581    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2582    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2583    "LW" => print 'd', 'q' depending on the VEX.W bit
2584    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2585            an operand size prefix, or suffix_always is true.  print
2586            'q' if rex prefix is present.
2587
2588    Many of the above letters print nothing in Intel mode.  See "putop"
2589    for the details.
2590
2591    Braces '{' and '}', and vertical bars '|', indicate alternative
2592    mnemonic strings for AT&T and Intel.  */
2593
2594 static const struct dis386 dis386[] = {
2595   /* 00 */
2596   { "addB",             { Ebh1, Gb }, 0 },
2597   { "addS",             { Evh1, Gv }, 0 },
2598   { "addB",             { Gb, EbS }, 0 },
2599   { "addS",             { Gv, EvS }, 0 },
2600   { "addB",             { AL, Ib }, 0 },
2601   { "addS",             { eAX, Iv }, 0 },
2602   { X86_64_TABLE (X86_64_06) },
2603   { X86_64_TABLE (X86_64_07) },
2604   /* 08 */
2605   { "orB",              { Ebh1, Gb }, 0 },
2606   { "orS",              { Evh1, Gv }, 0 },
2607   { "orB",              { Gb, EbS }, 0 },
2608   { "orS",              { Gv, EvS }, 0 },
2609   { "orB",              { AL, Ib }, 0 },
2610   { "orS",              { eAX, Iv }, 0 },
2611   { X86_64_TABLE (X86_64_0D) },
2612   { Bad_Opcode },       /* 0x0f extended opcode escape */
2613   /* 10 */
2614   { "adcB",             { Ebh1, Gb }, 0 },
2615   { "adcS",             { Evh1, Gv }, 0 },
2616   { "adcB",             { Gb, EbS }, 0 },
2617   { "adcS",             { Gv, EvS }, 0 },
2618   { "adcB",             { AL, Ib }, 0 },
2619   { "adcS",             { eAX, Iv }, 0 },
2620   { X86_64_TABLE (X86_64_16) },
2621   { X86_64_TABLE (X86_64_17) },
2622   /* 18 */
2623   { "sbbB",             { Ebh1, Gb }, 0 },
2624   { "sbbS",             { Evh1, Gv }, 0 },
2625   { "sbbB",             { Gb, EbS }, 0 },
2626   { "sbbS",             { Gv, EvS }, 0 },
2627   { "sbbB",             { AL, Ib }, 0 },
2628   { "sbbS",             { eAX, Iv }, 0 },
2629   { X86_64_TABLE (X86_64_1E) },
2630   { X86_64_TABLE (X86_64_1F) },
2631   /* 20 */
2632   { "andB",             { Ebh1, Gb }, 0 },
2633   { "andS",             { Evh1, Gv }, 0 },
2634   { "andB",             { Gb, EbS }, 0 },
2635   { "andS",             { Gv, EvS }, 0 },
2636   { "andB",             { AL, Ib }, 0 },
2637   { "andS",             { eAX, Iv }, 0 },
2638   { Bad_Opcode },       /* SEG ES prefix */
2639   { X86_64_TABLE (X86_64_27) },
2640   /* 28 */
2641   { "subB",             { Ebh1, Gb }, 0 },
2642   { "subS",             { Evh1, Gv }, 0 },
2643   { "subB",             { Gb, EbS }, 0 },
2644   { "subS",             { Gv, EvS }, 0 },
2645   { "subB",             { AL, Ib }, 0 },
2646   { "subS",             { eAX, Iv }, 0 },
2647   { Bad_Opcode },       /* SEG CS prefix */
2648   { X86_64_TABLE (X86_64_2F) },
2649   /* 30 */
2650   { "xorB",             { Ebh1, Gb }, 0 },
2651   { "xorS",             { Evh1, Gv }, 0 },
2652   { "xorB",             { Gb, EbS }, 0 },
2653   { "xorS",             { Gv, EvS }, 0 },
2654   { "xorB",             { AL, Ib }, 0 },
2655   { "xorS",             { eAX, Iv }, 0 },
2656   { Bad_Opcode },       /* SEG SS prefix */
2657   { X86_64_TABLE (X86_64_37) },
2658   /* 38 */
2659   { "cmpB",             { Eb, Gb }, 0 },
2660   { "cmpS",             { Ev, Gv }, 0 },
2661   { "cmpB",             { Gb, EbS }, 0 },
2662   { "cmpS",             { Gv, EvS }, 0 },
2663   { "cmpB",             { AL, Ib }, 0 },
2664   { "cmpS",             { eAX, Iv }, 0 },
2665   { Bad_Opcode },       /* SEG DS prefix */
2666   { X86_64_TABLE (X86_64_3F) },
2667   /* 40 */
2668   { "inc{S|}",          { RMeAX }, 0 },
2669   { "inc{S|}",          { RMeCX }, 0 },
2670   { "inc{S|}",          { RMeDX }, 0 },
2671   { "inc{S|}",          { RMeBX }, 0 },
2672   { "inc{S|}",          { RMeSP }, 0 },
2673   { "inc{S|}",          { RMeBP }, 0 },
2674   { "inc{S|}",          { RMeSI }, 0 },
2675   { "inc{S|}",          { RMeDI }, 0 },
2676   /* 48 */
2677   { "dec{S|}",          { RMeAX }, 0 },
2678   { "dec{S|}",          { RMeCX }, 0 },
2679   { "dec{S|}",          { RMeDX }, 0 },
2680   { "dec{S|}",          { RMeBX }, 0 },
2681   { "dec{S|}",          { RMeSP }, 0 },
2682   { "dec{S|}",          { RMeBP }, 0 },
2683   { "dec{S|}",          { RMeSI }, 0 },
2684   { "dec{S|}",          { RMeDI }, 0 },
2685   /* 50 */
2686   { "pushV",            { RMrAX }, 0 },
2687   { "pushV",            { RMrCX }, 0 },
2688   { "pushV",            { RMrDX }, 0 },
2689   { "pushV",            { RMrBX }, 0 },
2690   { "pushV",            { RMrSP }, 0 },
2691   { "pushV",            { RMrBP }, 0 },
2692   { "pushV",            { RMrSI }, 0 },
2693   { "pushV",            { RMrDI }, 0 },
2694   /* 58 */
2695   { "popV",             { RMrAX }, 0 },
2696   { "popV",             { RMrCX }, 0 },
2697   { "popV",             { RMrDX }, 0 },
2698   { "popV",             { RMrBX }, 0 },
2699   { "popV",             { RMrSP }, 0 },
2700   { "popV",             { RMrBP }, 0 },
2701   { "popV",             { RMrSI }, 0 },
2702   { "popV",             { RMrDI }, 0 },
2703   /* 60 */
2704   { X86_64_TABLE (X86_64_60) },
2705   { X86_64_TABLE (X86_64_61) },
2706   { X86_64_TABLE (X86_64_62) },
2707   { X86_64_TABLE (X86_64_63) },
2708   { Bad_Opcode },       /* seg fs */
2709   { Bad_Opcode },       /* seg gs */
2710   { Bad_Opcode },       /* op size prefix */
2711   { Bad_Opcode },       /* adr size prefix */
2712   /* 68 */
2713   { "pushT",            { sIv }, 0 },
2714   { "imulS",            { Gv, Ev, Iv }, 0 },
2715   { "pushT",            { sIbT }, 0 },
2716   { "imulS",            { Gv, Ev, sIb }, 0 },
2717   { "ins{b|}",          { Ybr, indirDX }, 0 },
2718   { X86_64_TABLE (X86_64_6D) },
2719   { "outs{b|}",         { indirDXr, Xb }, 0 },
2720   { X86_64_TABLE (X86_64_6F) },
2721   /* 70 */
2722   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2723   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2724   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2725   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2726   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2727   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2728   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2729   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2730   /* 78 */
2731   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2732   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2733   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2734   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2735   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2736   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2737   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2738   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2739   /* 80 */
2740   { REG_TABLE (REG_80) },
2741   { REG_TABLE (REG_81) },
2742   { X86_64_TABLE (X86_64_82) },
2743   { REG_TABLE (REG_83) },
2744   { "testB",            { Eb, Gb }, 0 },
2745   { "testS",            { Ev, Gv }, 0 },
2746   { "xchgB",            { Ebh2, Gb }, 0 },
2747   { "xchgS",            { Evh2, Gv }, 0 },
2748   /* 88 */
2749   { "movB",             { Ebh3, Gb }, 0 },
2750   { "movS",             { Evh3, Gv }, 0 },
2751   { "movB",             { Gb, EbS }, 0 },
2752   { "movS",             { Gv, EvS }, 0 },
2753   { "movD",             { Sv, Sw }, 0 },
2754   { MOD_TABLE (MOD_8D) },
2755   { "movD",             { Sw, Sv }, 0 },
2756   { REG_TABLE (REG_8F) },
2757   /* 90 */
2758   { PREFIX_TABLE (PREFIX_90) },
2759   { "xchgS",            { RMeCX, eAX }, 0 },
2760   { "xchgS",            { RMeDX, eAX }, 0 },
2761   { "xchgS",            { RMeBX, eAX }, 0 },
2762   { "xchgS",            { RMeSP, eAX }, 0 },
2763   { "xchgS",            { RMeBP, eAX }, 0 },
2764   { "xchgS",            { RMeSI, eAX }, 0 },
2765   { "xchgS",            { RMeDI, eAX }, 0 },
2766   /* 98 */
2767   { "cW{t|}R",          { XX }, 0 },
2768   { "cR{t|}O",          { XX }, 0 },
2769   { X86_64_TABLE (X86_64_9A) },
2770   { Bad_Opcode },       /* fwait */
2771   { "pushfT",           { XX }, 0 },
2772   { "popfT",            { XX }, 0 },
2773   { "sahf",             { XX }, 0 },
2774   { "lahf",             { XX }, 0 },
2775   /* a0 */
2776   { "mov%LB",           { AL, Ob }, 0 },
2777   { "mov%LS",           { eAX, Ov }, 0 },
2778   { "mov%LB",           { Ob, AL }, 0 },
2779   { "mov%LS",           { Ov, eAX }, 0 },
2780   { "movs{b|}",         { Ybr, Xb }, 0 },
2781   { "movs{R|}",         { Yvr, Xv }, 0 },
2782   { "cmps{b|}",         { Xb, Yb }, 0 },
2783   { "cmps{R|}",         { Xv, Yv }, 0 },
2784   /* a8 */
2785   { "testB",            { AL, Ib }, 0 },
2786   { "testS",            { eAX, Iv }, 0 },
2787   { "stosB",            { Ybr, AL }, 0 },
2788   { "stosS",            { Yvr, eAX }, 0 },
2789   { "lodsB",            { ALr, Xb }, 0 },
2790   { "lodsS",            { eAXr, Xv }, 0 },
2791   { "scasB",            { AL, Yb }, 0 },
2792   { "scasS",            { eAX, Yv }, 0 },
2793   /* b0 */
2794   { "movB",             { RMAL, Ib }, 0 },
2795   { "movB",             { RMCL, Ib }, 0 },
2796   { "movB",             { RMDL, Ib }, 0 },
2797   { "movB",             { RMBL, Ib }, 0 },
2798   { "movB",             { RMAH, Ib }, 0 },
2799   { "movB",             { RMCH, Ib }, 0 },
2800   { "movB",             { RMDH, Ib }, 0 },
2801   { "movB",             { RMBH, Ib }, 0 },
2802   /* b8 */
2803   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2804   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2805   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2806   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2807   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2808   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2809   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2810   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2811   /* c0 */
2812   { REG_TABLE (REG_C0) },
2813   { REG_TABLE (REG_C1) },
2814   { "retT",             { Iw, BND }, 0 },
2815   { "retT",             { BND }, 0 },
2816   { X86_64_TABLE (X86_64_C4) },
2817   { X86_64_TABLE (X86_64_C5) },
2818   { REG_TABLE (REG_C6) },
2819   { REG_TABLE (REG_C7) },
2820   /* c8 */
2821   { "enterT",           { Iw, Ib }, 0 },
2822   { "leaveT",           { XX }, 0 },
2823   { "Jret{|f}P",        { Iw }, 0 },
2824   { "Jret{|f}P",        { XX }, 0 },
2825   { "int3",             { XX }, 0 },
2826   { "int",              { Ib }, 0 },
2827   { X86_64_TABLE (X86_64_CE) },
2828   { "iret%LP",          { XX }, 0 },
2829   /* d0 */
2830   { REG_TABLE (REG_D0) },
2831   { REG_TABLE (REG_D1) },
2832   { REG_TABLE (REG_D2) },
2833   { REG_TABLE (REG_D3) },
2834   { X86_64_TABLE (X86_64_D4) },
2835   { X86_64_TABLE (X86_64_D5) },
2836   { Bad_Opcode },
2837   { "xlat",             { DSBX }, 0 },
2838   /* d8 */
2839   { FLOAT },
2840   { FLOAT },
2841   { FLOAT },
2842   { FLOAT },
2843   { FLOAT },
2844   { FLOAT },
2845   { FLOAT },
2846   { FLOAT },
2847   /* e0 */
2848   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2849   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2850   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2851   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2852   { "inB",              { AL, Ib }, 0 },
2853   { "inG",              { zAX, Ib }, 0 },
2854   { "outB",             { Ib, AL }, 0 },
2855   { "outG",             { Ib, zAX }, 0 },
2856   /* e8 */
2857   { X86_64_TABLE (X86_64_E8) },
2858   { X86_64_TABLE (X86_64_E9) },
2859   { X86_64_TABLE (X86_64_EA) },
2860   { "jmp",              { Jb, BND }, 0 },
2861   { "inB",              { AL, indirDX }, 0 },
2862   { "inG",              { zAX, indirDX }, 0 },
2863   { "outB",             { indirDX, AL }, 0 },
2864   { "outG",             { indirDX, zAX }, 0 },
2865   /* f0 */
2866   { Bad_Opcode },       /* lock prefix */
2867   { "icebp",            { XX }, 0 },
2868   { Bad_Opcode },       /* repne */
2869   { Bad_Opcode },       /* repz */
2870   { "hlt",              { XX }, 0 },
2871   { "cmc",              { XX }, 0 },
2872   { REG_TABLE (REG_F6) },
2873   { REG_TABLE (REG_F7) },
2874   /* f8 */
2875   { "clc",              { XX }, 0 },
2876   { "stc",              { XX }, 0 },
2877   { "cli",              { XX }, 0 },
2878   { "sti",              { XX }, 0 },
2879   { "cld",              { XX }, 0 },
2880   { "std",              { XX }, 0 },
2881   { REG_TABLE (REG_FE) },
2882   { REG_TABLE (REG_FF) },
2883 };
2884
2885 static const struct dis386 dis386_twobyte[] = {
2886   /* 00 */
2887   { REG_TABLE (REG_0F00 ) },
2888   { REG_TABLE (REG_0F01 ) },
2889   { "larS",             { Gv, Ew }, 0 },
2890   { "lslS",             { Gv, Ew }, 0 },
2891   { Bad_Opcode },
2892   { "syscall",          { XX }, 0 },
2893   { "clts",             { XX }, 0 },
2894   { "sysret%LP",                { XX }, 0 },
2895   /* 08 */
2896   { "invd",             { XX }, 0 },
2897   { PREFIX_TABLE (PREFIX_0F09) },
2898   { Bad_Opcode },
2899   { "ud2",              { XX }, 0 },
2900   { Bad_Opcode },
2901   { REG_TABLE (REG_0F0D) },
2902   { "femms",            { XX }, 0 },
2903   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2904   /* 10 */
2905   { PREFIX_TABLE (PREFIX_0F10) },
2906   { PREFIX_TABLE (PREFIX_0F11) },
2907   { PREFIX_TABLE (PREFIX_0F12) },
2908   { MOD_TABLE (MOD_0F13) },
2909   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2910   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2911   { PREFIX_TABLE (PREFIX_0F16) },
2912   { MOD_TABLE (MOD_0F17) },
2913   /* 18 */
2914   { REG_TABLE (REG_0F18) },
2915   { "nopQ",             { Ev }, 0 },
2916   { PREFIX_TABLE (PREFIX_0F1A) },
2917   { PREFIX_TABLE (PREFIX_0F1B) },
2918   { PREFIX_TABLE (PREFIX_0F1C) },
2919   { "nopQ",             { Ev }, 0 },
2920   { PREFIX_TABLE (PREFIX_0F1E) },
2921   { "nopQ",             { Ev }, 0 },
2922   /* 20 */
2923   { "movZ",             { Rm, Cm }, 0 },
2924   { "movZ",             { Rm, Dm }, 0 },
2925   { "movZ",             { Cm, Rm }, 0 },
2926   { "movZ",             { Dm, Rm }, 0 },
2927   { MOD_TABLE (MOD_0F24) },
2928   { Bad_Opcode },
2929   { MOD_TABLE (MOD_0F26) },
2930   { Bad_Opcode },
2931   /* 28 */
2932   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2933   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2934   { PREFIX_TABLE (PREFIX_0F2A) },
2935   { PREFIX_TABLE (PREFIX_0F2B) },
2936   { PREFIX_TABLE (PREFIX_0F2C) },
2937   { PREFIX_TABLE (PREFIX_0F2D) },
2938   { PREFIX_TABLE (PREFIX_0F2E) },
2939   { PREFIX_TABLE (PREFIX_0F2F) },
2940   /* 30 */
2941   { "wrmsr",            { XX }, 0 },
2942   { "rdtsc",            { XX }, 0 },
2943   { "rdmsr",            { XX }, 0 },
2944   { "rdpmc",            { XX }, 0 },
2945   { "sysenter",         { XX }, 0 },
2946   { "sysexit",          { XX }, 0 },
2947   { Bad_Opcode },
2948   { "getsec",           { XX }, 0 },
2949   /* 38 */
2950   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2951   { Bad_Opcode },
2952   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2953   { Bad_Opcode },
2954   { Bad_Opcode },
2955   { Bad_Opcode },
2956   { Bad_Opcode },
2957   { Bad_Opcode },
2958   /* 40 */
2959   { "cmovoS",           { Gv, Ev }, 0 },
2960   { "cmovnoS",          { Gv, Ev }, 0 },
2961   { "cmovbS",           { Gv, Ev }, 0 },
2962   { "cmovaeS",          { Gv, Ev }, 0 },
2963   { "cmoveS",           { Gv, Ev }, 0 },
2964   { "cmovneS",          { Gv, Ev }, 0 },
2965   { "cmovbeS",          { Gv, Ev }, 0 },
2966   { "cmovaS",           { Gv, Ev }, 0 },
2967   /* 48 */
2968   { "cmovsS",           { Gv, Ev }, 0 },
2969   { "cmovnsS",          { Gv, Ev }, 0 },
2970   { "cmovpS",           { Gv, Ev }, 0 },
2971   { "cmovnpS",          { Gv, Ev }, 0 },
2972   { "cmovlS",           { Gv, Ev }, 0 },
2973   { "cmovgeS",          { Gv, Ev }, 0 },
2974   { "cmovleS",          { Gv, Ev }, 0 },
2975   { "cmovgS",           { Gv, Ev }, 0 },
2976   /* 50 */
2977   { MOD_TABLE (MOD_0F51) },
2978   { PREFIX_TABLE (PREFIX_0F51) },
2979   { PREFIX_TABLE (PREFIX_0F52) },
2980   { PREFIX_TABLE (PREFIX_0F53) },
2981   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2982   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2983   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2984   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2985   /* 58 */
2986   { PREFIX_TABLE (PREFIX_0F58) },
2987   { PREFIX_TABLE (PREFIX_0F59) },
2988   { PREFIX_TABLE (PREFIX_0F5A) },
2989   { PREFIX_TABLE (PREFIX_0F5B) },
2990   { PREFIX_TABLE (PREFIX_0F5C) },
2991   { PREFIX_TABLE (PREFIX_0F5D) },
2992   { PREFIX_TABLE (PREFIX_0F5E) },
2993   { PREFIX_TABLE (PREFIX_0F5F) },
2994   /* 60 */
2995   { PREFIX_TABLE (PREFIX_0F60) },
2996   { PREFIX_TABLE (PREFIX_0F61) },
2997   { PREFIX_TABLE (PREFIX_0F62) },
2998   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2999   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
3000   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
3001   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
3002   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
3003   /* 68 */
3004   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
3005   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
3006   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
3007   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
3008   { PREFIX_TABLE (PREFIX_0F6C) },
3009   { PREFIX_TABLE (PREFIX_0F6D) },
3010   { "movK",             { MX, Edq }, PREFIX_OPCODE },
3011   { PREFIX_TABLE (PREFIX_0F6F) },
3012   /* 70 */
3013   { PREFIX_TABLE (PREFIX_0F70) },
3014   { REG_TABLE (REG_0F71) },
3015   { REG_TABLE (REG_0F72) },
3016   { REG_TABLE (REG_0F73) },
3017   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
3018   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
3019   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
3020   { "emms",             { XX }, PREFIX_OPCODE },
3021   /* 78 */
3022   { PREFIX_TABLE (PREFIX_0F78) },
3023   { PREFIX_TABLE (PREFIX_0F79) },
3024   { Bad_Opcode },
3025   { Bad_Opcode },
3026   { PREFIX_TABLE (PREFIX_0F7C) },
3027   { PREFIX_TABLE (PREFIX_0F7D) },
3028   { PREFIX_TABLE (PREFIX_0F7E) },
3029   { PREFIX_TABLE (PREFIX_0F7F) },
3030   /* 80 */
3031   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
3032   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
3033   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
3034   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
3035   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
3036   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
3037   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
3038   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
3039   /* 88 */
3040   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
3041   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
3042   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
3043   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
3044   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
3045   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
3046   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
3047   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
3048   /* 90 */
3049   { "seto",             { Eb }, 0 },
3050   { "setno",            { Eb }, 0 },
3051   { "setb",             { Eb }, 0 },
3052   { "setae",            { Eb }, 0 },
3053   { "sete",             { Eb }, 0 },
3054   { "setne",            { Eb }, 0 },
3055   { "setbe",            { Eb }, 0 },
3056   { "seta",             { Eb }, 0 },
3057   /* 98 */
3058   { "sets",             { Eb }, 0 },
3059   { "setns",            { Eb }, 0 },
3060   { "setp",             { Eb }, 0 },
3061   { "setnp",            { Eb }, 0 },
3062   { "setl",             { Eb }, 0 },
3063   { "setge",            { Eb }, 0 },
3064   { "setle",            { Eb }, 0 },
3065   { "setg",             { Eb }, 0 },
3066   /* a0 */
3067   { "pushT",            { fs }, 0 },
3068   { "popT",             { fs }, 0 },
3069   { "cpuid",            { XX }, 0 },
3070   { "btS",              { Ev, Gv }, 0 },
3071   { "shldS",            { Ev, Gv, Ib }, 0 },
3072   { "shldS",            { Ev, Gv, CL }, 0 },
3073   { REG_TABLE (REG_0FA6) },
3074   { REG_TABLE (REG_0FA7) },
3075   /* a8 */
3076   { "pushT",            { gs }, 0 },
3077   { "popT",             { gs }, 0 },
3078   { "rsm",              { XX }, 0 },
3079   { "btsS",             { Evh1, Gv }, 0 },
3080   { "shrdS",            { Ev, Gv, Ib }, 0 },
3081   { "shrdS",            { Ev, Gv, CL }, 0 },
3082   { REG_TABLE (REG_0FAE) },
3083   { "imulS",            { Gv, Ev }, 0 },
3084   /* b0 */
3085   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3086   { "cmpxchgS",         { Evh1, Gv }, 0 },
3087   { MOD_TABLE (MOD_0FB2) },
3088   { "btrS",             { Evh1, Gv }, 0 },
3089   { MOD_TABLE (MOD_0FB4) },
3090   { MOD_TABLE (MOD_0FB5) },
3091   { "movz{bR|x}",       { Gv, Eb }, 0 },
3092   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3093   /* b8 */
3094   { PREFIX_TABLE (PREFIX_0FB8) },
3095   { "ud1S",             { Gv, Ev }, 0 },
3096   { REG_TABLE (REG_0FBA) },
3097   { "btcS",             { Evh1, Gv }, 0 },
3098   { PREFIX_TABLE (PREFIX_0FBC) },
3099   { PREFIX_TABLE (PREFIX_0FBD) },
3100   { "movs{bR|x}",       { Gv, Eb }, 0 },
3101   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3102   /* c0 */
3103   { "xaddB",            { Ebh1, Gb }, 0 },
3104   { "xaddS",            { Evh1, Gv }, 0 },
3105   { PREFIX_TABLE (PREFIX_0FC2) },
3106   { MOD_TABLE (MOD_0FC3) },
3107   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3108   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3109   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3110   { REG_TABLE (REG_0FC7) },
3111   /* c8 */
3112   { "bswap",            { RMeAX }, 0 },
3113   { "bswap",            { RMeCX }, 0 },
3114   { "bswap",            { RMeDX }, 0 },
3115   { "bswap",            { RMeBX }, 0 },
3116   { "bswap",            { RMeSP }, 0 },
3117   { "bswap",            { RMeBP }, 0 },
3118   { "bswap",            { RMeSI }, 0 },
3119   { "bswap",            { RMeDI }, 0 },
3120   /* d0 */
3121   { PREFIX_TABLE (PREFIX_0FD0) },
3122   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3123   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3124   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3125   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3126   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3127   { PREFIX_TABLE (PREFIX_0FD6) },
3128   { MOD_TABLE (MOD_0FD7) },
3129   /* d8 */
3130   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3131   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3132   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3133   { "pand",             { MX, EM }, PREFIX_OPCODE },
3134   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3135   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3136   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3137   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3138   /* e0 */
3139   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3140   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3141   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3142   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3143   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3144   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3145   { PREFIX_TABLE (PREFIX_0FE6) },
3146   { PREFIX_TABLE (PREFIX_0FE7) },
3147   /* e8 */
3148   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3149   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3150   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3151   { "por",              { MX, EM }, PREFIX_OPCODE },
3152   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3153   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3154   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3155   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3156   /* f0 */
3157   { PREFIX_TABLE (PREFIX_0FF0) },
3158   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3159   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3160   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3161   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3162   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3163   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3164   { PREFIX_TABLE (PREFIX_0FF7) },
3165   /* f8 */
3166   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3167   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3168   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3169   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3170   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3171   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3172   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3173   { "ud0S",             { Gv, Ev }, 0 },
3174 };
3175
3176 static const unsigned char onebyte_has_modrm[256] = {
3177   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3178   /*       -------------------------------        */
3179   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3180   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3181   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3182   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3183   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3184   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3185   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3186   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3187   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3188   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3189   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3190   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3191   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3192   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3193   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3194   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3195   /*       -------------------------------        */
3196   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3197 };
3198
3199 static const unsigned char twobyte_has_modrm[256] = {
3200   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3201   /*       -------------------------------        */
3202   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3203   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3204   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3205   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3206   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3207   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3208   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3209   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3210   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3211   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3212   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3213   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
3214   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3215   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3216   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3217   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
3218   /*       -------------------------------        */
3219   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3220 };
3221
3222 static char obuf[100];
3223 static char *obufp;
3224 static char *mnemonicendp;
3225 static char scratchbuf[100];
3226 static unsigned char *start_codep;
3227 static unsigned char *insn_codep;
3228 static unsigned char *codep;
3229 static unsigned char *end_codep;
3230 static int last_lock_prefix;
3231 static int last_repz_prefix;
3232 static int last_repnz_prefix;
3233 static int last_data_prefix;
3234 static int last_addr_prefix;
3235 static int last_rex_prefix;
3236 static int last_seg_prefix;
3237 static int fwait_prefix;
3238 /* The active segment register prefix.  */
3239 static int active_seg_prefix;
3240 #define MAX_CODE_LENGTH 15
3241 /* We can up to 14 prefixes since the maximum instruction length is
3242    15bytes.  */
3243 static int all_prefixes[MAX_CODE_LENGTH - 1];
3244 static disassemble_info *the_info;
3245 static struct
3246   {
3247     int mod;
3248     int reg;
3249     int rm;
3250   }
3251 modrm;
3252 static unsigned char need_modrm;
3253 static struct
3254   {
3255     int scale;
3256     int index;
3257     int base;
3258   }
3259 sib;
3260 static struct
3261   {
3262     int register_specifier;
3263     int length;
3264     int prefix;
3265     int w;
3266     int evex;
3267     int r;
3268     int v;
3269     int mask_register_specifier;
3270     int zeroing;
3271     int ll;
3272     int b;
3273   }
3274 vex;
3275 static unsigned char need_vex;
3276 static unsigned char need_vex_reg;
3277 static unsigned char vex_w_done;
3278
3279 struct op
3280   {
3281     const char *name;
3282     unsigned int len;
3283   };
3284
3285 /* If we are accessing mod/rm/reg without need_modrm set, then the
3286    values are stale.  Hitting this abort likely indicates that you
3287    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3288 #define MODRM_CHECK  if (!need_modrm) abort ()
3289
3290 static const char **names64;
3291 static const char **names32;
3292 static const char **names16;
3293 static const char **names8;
3294 static const char **names8rex;
3295 static const char **names_seg;
3296 static const char *index64;
3297 static const char *index32;
3298 static const char **index16;
3299 static const char **names_bnd;
3300
3301 static const char *intel_names64[] = {
3302   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3303   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3304 };
3305 static const char *intel_names32[] = {
3306   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3307   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3308 };
3309 static const char *intel_names16[] = {
3310   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3311   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3312 };
3313 static const char *intel_names8[] = {
3314   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3315 };
3316 static const char *intel_names8rex[] = {
3317   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3318   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3319 };
3320 static const char *intel_names_seg[] = {
3321   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3322 };
3323 static const char *intel_index64 = "riz";
3324 static const char *intel_index32 = "eiz";
3325 static const char *intel_index16[] = {
3326   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3327 };
3328
3329 static const char *att_names64[] = {
3330   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3331   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3332 };
3333 static const char *att_names32[] = {
3334   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3335   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3336 };
3337 static const char *att_names16[] = {
3338   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3339   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3340 };
3341 static const char *att_names8[] = {
3342   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3343 };
3344 static const char *att_names8rex[] = {
3345   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3346   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3347 };
3348 static const char *att_names_seg[] = {
3349   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3350 };
3351 static const char *att_index64 = "%riz";
3352 static const char *att_index32 = "%eiz";
3353 static const char *att_index16[] = {
3354   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3355 };
3356
3357 static const char **names_mm;
3358 static const char *intel_names_mm[] = {
3359   "mm0", "mm1", "mm2", "mm3",
3360   "mm4", "mm5", "mm6", "mm7"
3361 };
3362 static const char *att_names_mm[] = {
3363   "%mm0", "%mm1", "%mm2", "%mm3",
3364   "%mm4", "%mm5", "%mm6", "%mm7"
3365 };
3366
3367 static const char *intel_names_bnd[] = {
3368   "bnd0", "bnd1", "bnd2", "bnd3"
3369 };
3370
3371 static const char *att_names_bnd[] = {
3372   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3373 };
3374
3375 static const char **names_xmm;
3376 static const char *intel_names_xmm[] = {
3377   "xmm0", "xmm1", "xmm2", "xmm3",
3378   "xmm4", "xmm5", "xmm6", "xmm7",
3379   "xmm8", "xmm9", "xmm10", "xmm11",
3380   "xmm12", "xmm13", "xmm14", "xmm15",
3381   "xmm16", "xmm17", "xmm18", "xmm19",
3382   "xmm20", "xmm21", "xmm22", "xmm23",
3383   "xmm24", "xmm25", "xmm26", "xmm27",
3384   "xmm28", "xmm29", "xmm30", "xmm31"
3385 };
3386 static const char *att_names_xmm[] = {
3387   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3388   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3389   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3390   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3391   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3392   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3393   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3394   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3395 };
3396
3397 static const char **names_ymm;
3398 static const char *intel_names_ymm[] = {
3399   "ymm0", "ymm1", "ymm2", "ymm3",
3400   "ymm4", "ymm5", "ymm6", "ymm7",
3401   "ymm8", "ymm9", "ymm10", "ymm11",
3402   "ymm12", "ymm13", "ymm14", "ymm15",
3403   "ymm16", "ymm17", "ymm18", "ymm19",
3404   "ymm20", "ymm21", "ymm22", "ymm23",
3405   "ymm24", "ymm25", "ymm26", "ymm27",
3406   "ymm28", "ymm29", "ymm30", "ymm31"
3407 };
3408 static const char *att_names_ymm[] = {
3409   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3410   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3411   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3412   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3413   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3414   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3415   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3416   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3417 };
3418
3419 static const char **names_zmm;
3420 static const char *intel_names_zmm[] = {
3421   "zmm0", "zmm1", "zmm2", "zmm3",
3422   "zmm4", "zmm5", "zmm6", "zmm7",
3423   "zmm8", "zmm9", "zmm10", "zmm11",
3424   "zmm12", "zmm13", "zmm14", "zmm15",
3425   "zmm16", "zmm17", "zmm18", "zmm19",
3426   "zmm20", "zmm21", "zmm22", "zmm23",
3427   "zmm24", "zmm25", "zmm26", "zmm27",
3428   "zmm28", "zmm29", "zmm30", "zmm31"
3429 };
3430 static const char *att_names_zmm[] = {
3431   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3432   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3433   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3434   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3435   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3436   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3437   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3438   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3439 };
3440
3441 static const char **names_mask;
3442 static const char *intel_names_mask[] = {
3443   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3444 };
3445 static const char *att_names_mask[] = {
3446   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3447 };
3448
3449 static const char *names_rounding[] =
3450 {
3451   "{rn-sae}",
3452   "{rd-sae}",
3453   "{ru-sae}",
3454   "{rz-sae}"
3455 };
3456
3457 static const struct dis386 reg_table[][8] = {
3458   /* REG_80 */
3459   {
3460     { "addA",   { Ebh1, Ib }, 0 },
3461     { "orA",    { Ebh1, Ib }, 0 },
3462     { "adcA",   { Ebh1, Ib }, 0 },
3463     { "sbbA",   { Ebh1, Ib }, 0 },
3464     { "andA",   { Ebh1, Ib }, 0 },
3465     { "subA",   { Ebh1, Ib }, 0 },
3466     { "xorA",   { Ebh1, Ib }, 0 },
3467     { "cmpA",   { Eb, Ib }, 0 },
3468   },
3469   /* REG_81 */
3470   {
3471     { "addQ",   { Evh1, Iv }, 0 },
3472     { "orQ",    { Evh1, Iv }, 0 },
3473     { "adcQ",   { Evh1, Iv }, 0 },
3474     { "sbbQ",   { Evh1, Iv }, 0 },
3475     { "andQ",   { Evh1, Iv }, 0 },
3476     { "subQ",   { Evh1, Iv }, 0 },
3477     { "xorQ",   { Evh1, Iv }, 0 },
3478     { "cmpQ",   { Ev, Iv }, 0 },
3479   },
3480   /* REG_83 */
3481   {
3482     { "addQ",   { Evh1, sIb }, 0 },
3483     { "orQ",    { Evh1, sIb }, 0 },
3484     { "adcQ",   { Evh1, sIb }, 0 },
3485     { "sbbQ",   { Evh1, sIb }, 0 },
3486     { "andQ",   { Evh1, sIb }, 0 },
3487     { "subQ",   { Evh1, sIb }, 0 },
3488     { "xorQ",   { Evh1, sIb }, 0 },
3489     { "cmpQ",   { Ev, sIb }, 0 },
3490   },
3491   /* REG_8F */
3492   {
3493     { "popU",   { stackEv }, 0 },
3494     { XOP_8F_TABLE (XOP_09) },
3495     { Bad_Opcode },
3496     { Bad_Opcode },
3497     { Bad_Opcode },
3498     { XOP_8F_TABLE (XOP_09) },
3499   },
3500   /* REG_C0 */
3501   {
3502     { "rolA",   { Eb, Ib }, 0 },
3503     { "rorA",   { Eb, Ib }, 0 },
3504     { "rclA",   { Eb, Ib }, 0 },
3505     { "rcrA",   { Eb, Ib }, 0 },
3506     { "shlA",   { Eb, Ib }, 0 },
3507     { "shrA",   { Eb, Ib }, 0 },
3508     { "shlA",   { Eb, Ib }, 0 },
3509     { "sarA",   { Eb, Ib }, 0 },
3510   },
3511   /* REG_C1 */
3512   {
3513     { "rolQ",   { Ev, Ib }, 0 },
3514     { "rorQ",   { Ev, Ib }, 0 },
3515     { "rclQ",   { Ev, Ib }, 0 },
3516     { "rcrQ",   { Ev, Ib }, 0 },
3517     { "shlQ",   { Ev, Ib }, 0 },
3518     { "shrQ",   { Ev, Ib }, 0 },
3519     { "shlQ",   { Ev, Ib }, 0 },
3520     { "sarQ",   { Ev, Ib }, 0 },
3521   },
3522   /* REG_C6 */
3523   {
3524     { "movA",   { Ebh3, Ib }, 0 },
3525     { Bad_Opcode },
3526     { Bad_Opcode },
3527     { Bad_Opcode },
3528     { Bad_Opcode },
3529     { Bad_Opcode },
3530     { Bad_Opcode },
3531     { MOD_TABLE (MOD_C6_REG_7) },
3532   },
3533   /* REG_C7 */
3534   {
3535     { "movQ",   { Evh3, Iv }, 0 },
3536     { Bad_Opcode },
3537     { Bad_Opcode },
3538     { Bad_Opcode },
3539     { Bad_Opcode },
3540     { Bad_Opcode },
3541     { Bad_Opcode },
3542     { MOD_TABLE (MOD_C7_REG_7) },
3543   },
3544   /* REG_D0 */
3545   {
3546     { "rolA",   { Eb, I1 }, 0 },
3547     { "rorA",   { Eb, I1 }, 0 },
3548     { "rclA",   { Eb, I1 }, 0 },
3549     { "rcrA",   { Eb, I1 }, 0 },
3550     { "shlA",   { Eb, I1 }, 0 },
3551     { "shrA",   { Eb, I1 }, 0 },
3552     { "shlA",   { Eb, I1 }, 0 },
3553     { "sarA",   { Eb, I1 }, 0 },
3554   },
3555   /* REG_D1 */
3556   {
3557     { "rolQ",   { Ev, I1 }, 0 },
3558     { "rorQ",   { Ev, I1 }, 0 },
3559     { "rclQ",   { Ev, I1 }, 0 },
3560     { "rcrQ",   { Ev, I1 }, 0 },
3561     { "shlQ",   { Ev, I1 }, 0 },
3562     { "shrQ",   { Ev, I1 }, 0 },
3563     { "shlQ",   { Ev, I1 }, 0 },
3564     { "sarQ",   { Ev, I1 }, 0 },
3565   },
3566   /* REG_D2 */
3567   {
3568     { "rolA",   { Eb, CL }, 0 },
3569     { "rorA",   { Eb, CL }, 0 },
3570     { "rclA",   { Eb, CL }, 0 },
3571     { "rcrA",   { Eb, CL }, 0 },
3572     { "shlA",   { Eb, CL }, 0 },
3573     { "shrA",   { Eb, CL }, 0 },
3574     { "shlA",   { Eb, CL }, 0 },
3575     { "sarA",   { Eb, CL }, 0 },
3576   },
3577   /* REG_D3 */
3578   {
3579     { "rolQ",   { Ev, CL }, 0 },
3580     { "rorQ",   { Ev, CL }, 0 },
3581     { "rclQ",   { Ev, CL }, 0 },
3582     { "rcrQ",   { Ev, CL }, 0 },
3583     { "shlQ",   { Ev, CL }, 0 },
3584     { "shrQ",   { Ev, CL }, 0 },
3585     { "shlQ",   { Ev, CL }, 0 },
3586     { "sarQ",   { Ev, CL }, 0 },
3587   },
3588   /* REG_F6 */
3589   {
3590     { "testA",  { Eb, Ib }, 0 },
3591     { "testA",  { Eb, Ib }, 0 },
3592     { "notA",   { Ebh1 }, 0 },
3593     { "negA",   { Ebh1 }, 0 },
3594     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3595     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3596     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3597     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3598   },
3599   /* REG_F7 */
3600   {
3601     { "testQ",  { Ev, Iv }, 0 },
3602     { "testQ",  { Ev, Iv }, 0 },
3603     { "notQ",   { Evh1 }, 0 },
3604     { "negQ",   { Evh1 }, 0 },
3605     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3606     { "imulQ",  { Ev }, 0 },
3607     { "divQ",   { Ev }, 0 },
3608     { "idivQ",  { Ev }, 0 },
3609   },
3610   /* REG_FE */
3611   {
3612     { "incA",   { Ebh1 }, 0 },
3613     { "decA",   { Ebh1 }, 0 },
3614   },
3615   /* REG_FF */
3616   {
3617     { "incQ",   { Evh1 }, 0 },
3618     { "decQ",   { Evh1 }, 0 },
3619     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3620     { MOD_TABLE (MOD_FF_REG_3) },
3621     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3622     { MOD_TABLE (MOD_FF_REG_5) },
3623     { "pushU",  { stackEv }, 0 },
3624     { Bad_Opcode },
3625   },
3626   /* REG_0F00 */
3627   {
3628     { "sldtD",  { Sv }, 0 },
3629     { "strD",   { Sv }, 0 },
3630     { "lldt",   { Ew }, 0 },
3631     { "ltr",    { Ew }, 0 },
3632     { "verr",   { Ew }, 0 },
3633     { "verw",   { Ew }, 0 },
3634     { Bad_Opcode },
3635     { Bad_Opcode },
3636   },
3637   /* REG_0F01 */
3638   {
3639     { MOD_TABLE (MOD_0F01_REG_0) },
3640     { MOD_TABLE (MOD_0F01_REG_1) },
3641     { MOD_TABLE (MOD_0F01_REG_2) },
3642     { MOD_TABLE (MOD_0F01_REG_3) },
3643     { "smswD",  { Sv }, 0 },
3644     { MOD_TABLE (MOD_0F01_REG_5) },
3645     { "lmsw",   { Ew }, 0 },
3646     { MOD_TABLE (MOD_0F01_REG_7) },
3647   },
3648   /* REG_0F0D */
3649   {
3650     { "prefetch",       { Mb }, 0 },
3651     { "prefetchw",      { Mb }, 0 },
3652     { "prefetchwt1",    { Mb }, 0 },
3653     { "prefetch",       { Mb }, 0 },
3654     { "prefetch",       { Mb }, 0 },
3655     { "prefetch",       { Mb }, 0 },
3656     { "prefetch",       { Mb }, 0 },
3657     { "prefetch",       { Mb }, 0 },
3658   },
3659   /* REG_0F18 */
3660   {
3661     { MOD_TABLE (MOD_0F18_REG_0) },
3662     { MOD_TABLE (MOD_0F18_REG_1) },
3663     { MOD_TABLE (MOD_0F18_REG_2) },
3664     { MOD_TABLE (MOD_0F18_REG_3) },
3665     { MOD_TABLE (MOD_0F18_REG_4) },
3666     { MOD_TABLE (MOD_0F18_REG_5) },
3667     { MOD_TABLE (MOD_0F18_REG_6) },
3668     { MOD_TABLE (MOD_0F18_REG_7) },
3669   },
3670   /* REG_0F1C_MOD_0 */
3671   {
3672     { "cldemote",       { Mb }, 0 },
3673     { "nopQ",           { Ev }, 0 },
3674     { "nopQ",           { Ev }, 0 },
3675     { "nopQ",           { Ev }, 0 },
3676     { "nopQ",           { Ev }, 0 },
3677     { "nopQ",           { Ev }, 0 },
3678     { "nopQ",           { Ev }, 0 },
3679     { "nopQ",           { Ev }, 0 },
3680   },
3681   /* REG_0F1E_MOD_3 */
3682   {
3683     { "nopQ",           { Ev }, 0 },
3684     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3685     { "nopQ",           { Ev }, 0 },
3686     { "nopQ",           { Ev }, 0 },
3687     { "nopQ",           { Ev }, 0 },
3688     { "nopQ",           { Ev }, 0 },
3689     { "nopQ",           { Ev }, 0 },
3690     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3691   },
3692   /* REG_0F71 */
3693   {
3694     { Bad_Opcode },
3695     { Bad_Opcode },
3696     { MOD_TABLE (MOD_0F71_REG_2) },
3697     { Bad_Opcode },
3698     { MOD_TABLE (MOD_0F71_REG_4) },
3699     { Bad_Opcode },
3700     { MOD_TABLE (MOD_0F71_REG_6) },
3701   },
3702   /* REG_0F72 */
3703   {
3704     { Bad_Opcode },
3705     { Bad_Opcode },
3706     { MOD_TABLE (MOD_0F72_REG_2) },
3707     { Bad_Opcode },
3708     { MOD_TABLE (MOD_0F72_REG_4) },
3709     { Bad_Opcode },
3710     { MOD_TABLE (MOD_0F72_REG_6) },
3711   },
3712   /* REG_0F73 */
3713   {
3714     { Bad_Opcode },
3715     { Bad_Opcode },
3716     { MOD_TABLE (MOD_0F73_REG_2) },
3717     { MOD_TABLE (MOD_0F73_REG_3) },
3718     { Bad_Opcode },
3719     { Bad_Opcode },
3720     { MOD_TABLE (MOD_0F73_REG_6) },
3721     { MOD_TABLE (MOD_0F73_REG_7) },
3722   },
3723   /* REG_0FA6 */
3724   {
3725     { "montmul",        { { OP_0f07, 0 } }, 0 },
3726     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3727     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3728   },
3729   /* REG_0FA7 */
3730   {
3731     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3732     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3733     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3734     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3735     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3736     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3737   },
3738   /* REG_0FAE */
3739   {
3740     { MOD_TABLE (MOD_0FAE_REG_0) },
3741     { MOD_TABLE (MOD_0FAE_REG_1) },
3742     { MOD_TABLE (MOD_0FAE_REG_2) },
3743     { MOD_TABLE (MOD_0FAE_REG_3) },
3744     { MOD_TABLE (MOD_0FAE_REG_4) },
3745     { MOD_TABLE (MOD_0FAE_REG_5) },
3746     { MOD_TABLE (MOD_0FAE_REG_6) },
3747     { MOD_TABLE (MOD_0FAE_REG_7) },
3748   },
3749   /* REG_0FBA */
3750   {
3751     { Bad_Opcode },
3752     { Bad_Opcode },
3753     { Bad_Opcode },
3754     { Bad_Opcode },
3755     { "btQ",    { Ev, Ib }, 0 },
3756     { "btsQ",   { Evh1, Ib }, 0 },
3757     { "btrQ",   { Evh1, Ib }, 0 },
3758     { "btcQ",   { Evh1, Ib }, 0 },
3759   },
3760   /* REG_0FC7 */
3761   {
3762     { Bad_Opcode },
3763     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3764     { Bad_Opcode },
3765     { MOD_TABLE (MOD_0FC7_REG_3) },
3766     { MOD_TABLE (MOD_0FC7_REG_4) },
3767     { MOD_TABLE (MOD_0FC7_REG_5) },
3768     { MOD_TABLE (MOD_0FC7_REG_6) },
3769     { MOD_TABLE (MOD_0FC7_REG_7) },
3770   },
3771   /* REG_VEX_0F71 */
3772   {
3773     { Bad_Opcode },
3774     { Bad_Opcode },
3775     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3776     { Bad_Opcode },
3777     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3778     { Bad_Opcode },
3779     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3780   },
3781   /* REG_VEX_0F72 */
3782   {
3783     { Bad_Opcode },
3784     { Bad_Opcode },
3785     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3786     { Bad_Opcode },
3787     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3788     { Bad_Opcode },
3789     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3790   },
3791   /* REG_VEX_0F73 */
3792   {
3793     { Bad_Opcode },
3794     { Bad_Opcode },
3795     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3796     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3797     { Bad_Opcode },
3798     { Bad_Opcode },
3799     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3800     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3801   },
3802   /* REG_VEX_0FAE */
3803   {
3804     { Bad_Opcode },
3805     { Bad_Opcode },
3806     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3807     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3808   },
3809   /* REG_VEX_0F38F3 */
3810   {
3811     { Bad_Opcode },
3812     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3813     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3814     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3815   },
3816   /* REG_XOP_LWPCB */
3817   {
3818     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3819     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3820   },
3821   /* REG_XOP_LWP */
3822   {
3823     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3824     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3825   },
3826   /* REG_XOP_TBM_01 */
3827   {
3828     { Bad_Opcode },
3829     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3830     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3831     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3832     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3833     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3834     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3835     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3836   },
3837   /* REG_XOP_TBM_02 */
3838   {
3839     { Bad_Opcode },
3840     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3841     { Bad_Opcode },
3842     { Bad_Opcode },
3843     { Bad_Opcode },
3844     { Bad_Opcode },
3845     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3846   },
3847 #define NEED_REG_TABLE
3848 #include "i386-dis-evex.h"
3849 #undef NEED_REG_TABLE
3850 };
3851
3852 static const struct dis386 prefix_table[][4] = {
3853   /* PREFIX_90 */
3854   {
3855     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3856     { "pause", { XX }, 0 },
3857     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3858     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3859   },
3860
3861   /* PREFIX_MOD_0_0F01_REG_5 */
3862   {
3863     { Bad_Opcode },
3864     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3865   },
3866
3867   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3868   {
3869     { Bad_Opcode },
3870     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3871   },
3872
3873   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3874   {
3875     { Bad_Opcode },
3876     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3877   },
3878
3879   /* PREFIX_0F09 */
3880   {
3881     { "wbinvd",   { XX }, 0 },
3882     { "wbnoinvd", { XX }, 0 },
3883   },
3884
3885   /* PREFIX_0F10 */
3886   {
3887     { "movups", { XM, EXx }, PREFIX_OPCODE },
3888     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3889     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3890     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3891   },
3892
3893   /* PREFIX_0F11 */
3894   {
3895     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3896     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3897     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3898     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3899   },
3900
3901   /* PREFIX_0F12 */
3902   {
3903     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3904     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3905     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3906     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3907   },
3908
3909   /* PREFIX_0F16 */
3910   {
3911     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3912     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3913     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3914   },
3915
3916   /* PREFIX_0F1A */
3917   {
3918     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3919     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3920     { "bndmov", { Gbnd, Ebnd }, 0 },
3921     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3922   },
3923
3924   /* PREFIX_0F1B */
3925   {
3926     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3927     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3928     { "bndmov", { EbndS, Gbnd }, 0 },
3929     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3930   },
3931
3932   /* PREFIX_0F1C */
3933   {
3934     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3935     { "nopQ",   { Ev }, PREFIX_OPCODE },
3936     { "nopQ",   { Ev }, PREFIX_OPCODE },
3937     { "nopQ",   { Ev }, PREFIX_OPCODE },
3938   },
3939
3940   /* PREFIX_0F1E */
3941   {
3942     { "nopQ",   { Ev }, PREFIX_OPCODE },
3943     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3944     { "nopQ",   { Ev }, PREFIX_OPCODE },
3945     { "nopQ",   { Ev }, PREFIX_OPCODE },
3946   },
3947
3948   /* PREFIX_0F2A */
3949   {
3950     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3951     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3952     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3953     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3954   },
3955
3956   /* PREFIX_0F2B */
3957   {
3958     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3959     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3960     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3961     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3962   },
3963
3964   /* PREFIX_0F2C */
3965   {
3966     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3967     { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3968     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3969     { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3970   },
3971
3972   /* PREFIX_0F2D */
3973   {
3974     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3975     { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3976     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3977     { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3978   },
3979
3980   /* PREFIX_0F2E */
3981   {
3982     { "ucomiss",{ XM, EXd }, 0 },
3983     { Bad_Opcode },
3984     { "ucomisd",{ XM, EXq }, 0 },
3985   },
3986
3987   /* PREFIX_0F2F */
3988   {
3989     { "comiss", { XM, EXd }, 0 },
3990     { Bad_Opcode },
3991     { "comisd", { XM, EXq }, 0 },
3992   },
3993
3994   /* PREFIX_0F51 */
3995   {
3996     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3997     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3998     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3999     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
4000   },
4001
4002   /* PREFIX_0F52 */
4003   {
4004     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
4005     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
4006   },
4007
4008   /* PREFIX_0F53 */
4009   {
4010     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
4011     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
4012   },
4013
4014   /* PREFIX_0F58 */
4015   {
4016     { "addps", { XM, EXx }, PREFIX_OPCODE },
4017     { "addss", { XM, EXd }, PREFIX_OPCODE },
4018     { "addpd", { XM, EXx }, PREFIX_OPCODE },
4019     { "addsd", { XM, EXq }, PREFIX_OPCODE },
4020   },
4021
4022   /* PREFIX_0F59 */
4023   {
4024     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
4025     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
4026     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
4027     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
4028   },
4029
4030   /* PREFIX_0F5A */
4031   {
4032     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
4033     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
4034     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
4035     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
4036   },
4037
4038   /* PREFIX_0F5B */
4039   {
4040     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
4041     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
4042     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
4043   },
4044
4045   /* PREFIX_0F5C */
4046   {
4047     { "subps",  { XM, EXx }, PREFIX_OPCODE },
4048     { "subss",  { XM, EXd }, PREFIX_OPCODE },
4049     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
4050     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
4051   },
4052
4053   /* PREFIX_0F5D */
4054   {
4055     { "minps",  { XM, EXx }, PREFIX_OPCODE },
4056     { "minss",  { XM, EXd }, PREFIX_OPCODE },
4057     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
4058     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
4059   },
4060
4061   /* PREFIX_0F5E */
4062   {
4063     { "divps",  { XM, EXx }, PREFIX_OPCODE },
4064     { "divss",  { XM, EXd }, PREFIX_OPCODE },
4065     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
4066     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
4067   },
4068
4069   /* PREFIX_0F5F */
4070   {
4071     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
4072     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
4073     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
4074     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
4075   },
4076
4077   /* PREFIX_0F60 */
4078   {
4079     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
4080     { Bad_Opcode },
4081     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
4082   },
4083
4084   /* PREFIX_0F61 */
4085   {
4086     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
4087     { Bad_Opcode },
4088     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4089   },
4090
4091   /* PREFIX_0F62 */
4092   {
4093     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4094     { Bad_Opcode },
4095     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4096   },
4097
4098   /* PREFIX_0F6C */
4099   {
4100     { Bad_Opcode },
4101     { Bad_Opcode },
4102     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4103   },
4104
4105   /* PREFIX_0F6D */
4106   {
4107     { Bad_Opcode },
4108     { Bad_Opcode },
4109     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4110   },
4111
4112   /* PREFIX_0F6F */
4113   {
4114     { "movq",   { MX, EM }, PREFIX_OPCODE },
4115     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4116     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4117   },
4118
4119   /* PREFIX_0F70 */
4120   {
4121     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4122     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4123     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4124     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4125   },
4126
4127   /* PREFIX_0F73_REG_3 */
4128   {
4129     { Bad_Opcode },
4130     { Bad_Opcode },
4131     { "psrldq", { XS, Ib }, 0 },
4132   },
4133
4134   /* PREFIX_0F73_REG_7 */
4135   {
4136     { Bad_Opcode },
4137     { Bad_Opcode },
4138     { "pslldq", { XS, Ib }, 0 },
4139   },
4140
4141   /* PREFIX_0F78 */
4142   {
4143     {"vmread",  { Em, Gm }, 0 },
4144     { Bad_Opcode },
4145     {"extrq",   { XS, Ib, Ib }, 0 },
4146     {"insertq", { XM, XS, Ib, Ib }, 0 },
4147   },
4148
4149   /* PREFIX_0F79 */
4150   {
4151     {"vmwrite", { Gm, Em }, 0 },
4152     { Bad_Opcode },
4153     {"extrq",   { XM, XS }, 0 },
4154     {"insertq", { XM, XS }, 0 },
4155   },
4156
4157   /* PREFIX_0F7C */
4158   {
4159     { Bad_Opcode },
4160     { Bad_Opcode },
4161     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4162     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4163   },
4164
4165   /* PREFIX_0F7D */
4166   {
4167     { Bad_Opcode },
4168     { Bad_Opcode },
4169     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4170     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4171   },
4172
4173   /* PREFIX_0F7E */
4174   {
4175     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4176     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4177     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4178   },
4179
4180   /* PREFIX_0F7F */
4181   {
4182     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4183     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4184     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4185   },
4186
4187   /* PREFIX_0FAE_REG_0 */
4188   {
4189     { Bad_Opcode },
4190     { "rdfsbase", { Ev }, 0 },
4191   },
4192
4193   /* PREFIX_0FAE_REG_1 */
4194   {
4195     { Bad_Opcode },
4196     { "rdgsbase", { Ev }, 0 },
4197   },
4198
4199   /* PREFIX_0FAE_REG_2 */
4200   {
4201     { Bad_Opcode },
4202     { "wrfsbase", { Ev }, 0 },
4203   },
4204
4205   /* PREFIX_0FAE_REG_3 */
4206   {
4207     { Bad_Opcode },
4208     { "wrgsbase", { Ev }, 0 },
4209   },
4210
4211   /* PREFIX_MOD_0_0FAE_REG_4 */
4212   {
4213     { "xsave",  { FXSAVE }, 0 },
4214     { "ptwrite%LQ", { Edq }, 0 },
4215   },
4216
4217   /* PREFIX_MOD_3_0FAE_REG_4 */
4218   {
4219     { Bad_Opcode },
4220     { "ptwrite%LQ", { Edq }, 0 },
4221   },
4222
4223   /* PREFIX_MOD_0_0FAE_REG_5 */
4224   {
4225     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4226   },
4227
4228   /* PREFIX_MOD_3_0FAE_REG_5 */
4229   {
4230     { "lfence",         { Skip_MODRM }, 0 },
4231     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4232   },
4233
4234   /* PREFIX_MOD_0_0FAE_REG_6 */
4235   {
4236     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4237     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4238     { "clwb",   { Mb }, PREFIX_OPCODE },
4239   },
4240
4241   /* PREFIX_MOD_1_0FAE_REG_6 */
4242   {
4243     { RM_TABLE (RM_0FAE_REG_6) },
4244     { "umonitor",       { Eva }, PREFIX_OPCODE },
4245     { "tpause", { Edq }, PREFIX_OPCODE },
4246     { "umwait", { Edq }, PREFIX_OPCODE },
4247   },
4248
4249   /* PREFIX_0FAE_REG_7 */
4250   {
4251     { "clflush",        { Mb }, 0 },
4252     { Bad_Opcode },
4253     { "clflushopt",     { Mb }, 0 },
4254   },
4255
4256   /* PREFIX_0FB8 */
4257   {
4258     { Bad_Opcode },
4259     { "popcntS", { Gv, Ev }, 0 },
4260   },
4261
4262   /* PREFIX_0FBC */
4263   {
4264     { "bsfS",   { Gv, Ev }, 0 },
4265     { "tzcntS", { Gv, Ev }, 0 },
4266     { "bsfS",   { Gv, Ev }, 0 },
4267   },
4268
4269   /* PREFIX_0FBD */
4270   {
4271     { "bsrS",   { Gv, Ev }, 0 },
4272     { "lzcntS", { Gv, Ev }, 0 },
4273     { "bsrS",   { Gv, Ev }, 0 },
4274   },
4275
4276   /* PREFIX_0FC2 */
4277   {
4278     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4279     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4280     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4281     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4282   },
4283
4284   /* PREFIX_MOD_0_0FC3 */
4285   {
4286     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4287   },
4288
4289   /* PREFIX_MOD_0_0FC7_REG_6 */
4290   {
4291     { "vmptrld",{ Mq }, 0 },
4292     { "vmxon",  { Mq }, 0 },
4293     { "vmclear",{ Mq }, 0 },
4294   },
4295
4296   /* PREFIX_MOD_3_0FC7_REG_6 */
4297   {
4298     { "rdrand", { Ev }, 0 },
4299     { Bad_Opcode },
4300     { "rdrand", { Ev }, 0 }
4301   },
4302
4303   /* PREFIX_MOD_3_0FC7_REG_7 */
4304   {
4305     { "rdseed", { Ev }, 0 },
4306     { "rdpid",  { Em }, 0 },
4307     { "rdseed", { Ev }, 0 },
4308   },
4309
4310   /* PREFIX_0FD0 */
4311   {
4312     { Bad_Opcode },
4313     { Bad_Opcode },
4314     { "addsubpd", { XM, EXx }, 0 },
4315     { "addsubps", { XM, EXx }, 0 },
4316   },
4317
4318   /* PREFIX_0FD6 */
4319   {
4320     { Bad_Opcode },
4321     { "movq2dq",{ XM, MS }, 0 },
4322     { "movq",   { EXqS, XM }, 0 },
4323     { "movdq2q",{ MX, XS }, 0 },
4324   },
4325
4326   /* PREFIX_0FE6 */
4327   {
4328     { Bad_Opcode },
4329     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4330     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4331     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4332   },
4333
4334   /* PREFIX_0FE7 */
4335   {
4336     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4337     { Bad_Opcode },
4338     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4339   },
4340
4341   /* PREFIX_0FF0 */
4342   {
4343     { Bad_Opcode },
4344     { Bad_Opcode },
4345     { Bad_Opcode },
4346     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4347   },
4348
4349   /* PREFIX_0FF7 */
4350   {
4351     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4352     { Bad_Opcode },
4353     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4354   },
4355
4356   /* PREFIX_0F3810 */
4357   {
4358     { Bad_Opcode },
4359     { Bad_Opcode },
4360     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4361   },
4362
4363   /* PREFIX_0F3814 */
4364   {
4365     { Bad_Opcode },
4366     { Bad_Opcode },
4367     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4368   },
4369
4370   /* PREFIX_0F3815 */
4371   {
4372     { Bad_Opcode },
4373     { Bad_Opcode },
4374     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4375   },
4376
4377   /* PREFIX_0F3817 */
4378   {
4379     { Bad_Opcode },
4380     { Bad_Opcode },
4381     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4382   },
4383
4384   /* PREFIX_0F3820 */
4385   {
4386     { Bad_Opcode },
4387     { Bad_Opcode },
4388     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4389   },
4390
4391   /* PREFIX_0F3821 */
4392   {
4393     { Bad_Opcode },
4394     { Bad_Opcode },
4395     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4396   },
4397
4398   /* PREFIX_0F3822 */
4399   {
4400     { Bad_Opcode },
4401     { Bad_Opcode },
4402     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4403   },
4404
4405   /* PREFIX_0F3823 */
4406   {
4407     { Bad_Opcode },
4408     { Bad_Opcode },
4409     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4410   },
4411
4412   /* PREFIX_0F3824 */
4413   {
4414     { Bad_Opcode },
4415     { Bad_Opcode },
4416     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4417   },
4418
4419   /* PREFIX_0F3825 */
4420   {
4421     { Bad_Opcode },
4422     { Bad_Opcode },
4423     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4424   },
4425
4426   /* PREFIX_0F3828 */
4427   {
4428     { Bad_Opcode },
4429     { Bad_Opcode },
4430     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4431   },
4432
4433   /* PREFIX_0F3829 */
4434   {
4435     { Bad_Opcode },
4436     { Bad_Opcode },
4437     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4438   },
4439
4440   /* PREFIX_0F382A */
4441   {
4442     { Bad_Opcode },
4443     { Bad_Opcode },
4444     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4445   },
4446
4447   /* PREFIX_0F382B */
4448   {
4449     { Bad_Opcode },
4450     { Bad_Opcode },
4451     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4452   },
4453
4454   /* PREFIX_0F3830 */
4455   {
4456     { Bad_Opcode },
4457     { Bad_Opcode },
4458     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4459   },
4460
4461   /* PREFIX_0F3831 */
4462   {
4463     { Bad_Opcode },
4464     { Bad_Opcode },
4465     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4466   },
4467
4468   /* PREFIX_0F3832 */
4469   {
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4473   },
4474
4475   /* PREFIX_0F3833 */
4476   {
4477     { Bad_Opcode },
4478     { Bad_Opcode },
4479     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4480   },
4481
4482   /* PREFIX_0F3834 */
4483   {
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4487   },
4488
4489   /* PREFIX_0F3835 */
4490   {
4491     { Bad_Opcode },
4492     { Bad_Opcode },
4493     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4494   },
4495
4496   /* PREFIX_0F3837 */
4497   {
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4501   },
4502
4503   /* PREFIX_0F3838 */
4504   {
4505     { Bad_Opcode },
4506     { Bad_Opcode },
4507     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4508   },
4509
4510   /* PREFIX_0F3839 */
4511   {
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4515   },
4516
4517   /* PREFIX_0F383A */
4518   {
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4522   },
4523
4524   /* PREFIX_0F383B */
4525   {
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4529   },
4530
4531   /* PREFIX_0F383C */
4532   {
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4536   },
4537
4538   /* PREFIX_0F383D */
4539   {
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4543   },
4544
4545   /* PREFIX_0F383E */
4546   {
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4550   },
4551
4552   /* PREFIX_0F383F */
4553   {
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4557   },
4558
4559   /* PREFIX_0F3840 */
4560   {
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4564   },
4565
4566   /* PREFIX_0F3841 */
4567   {
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F3880 */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4578   },
4579
4580   /* PREFIX_0F3881 */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4585   },
4586
4587   /* PREFIX_0F3882 */
4588   {
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4592   },
4593
4594   /* PREFIX_0F38C8 */
4595   {
4596     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4597   },
4598
4599   /* PREFIX_0F38C9 */
4600   {
4601     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4602   },
4603
4604   /* PREFIX_0F38CA */
4605   {
4606     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4607   },
4608
4609   /* PREFIX_0F38CB */
4610   {
4611     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4612   },
4613
4614   /* PREFIX_0F38CC */
4615   {
4616     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4617   },
4618
4619   /* PREFIX_0F38CD */
4620   {
4621     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4622   },
4623
4624   /* PREFIX_0F38CF */
4625   {
4626     { Bad_Opcode },
4627     { Bad_Opcode },
4628     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4629   },
4630
4631   /* PREFIX_0F38DB */
4632   {
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4636   },
4637
4638   /* PREFIX_0F38DC */
4639   {
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4643   },
4644
4645   /* PREFIX_0F38DD */
4646   {
4647     { Bad_Opcode },
4648     { Bad_Opcode },
4649     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4650   },
4651
4652   /* PREFIX_0F38DE */
4653   {
4654     { Bad_Opcode },
4655     { Bad_Opcode },
4656     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4657   },
4658
4659   /* PREFIX_0F38DF */
4660   {
4661     { Bad_Opcode },
4662     { Bad_Opcode },
4663     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4664   },
4665
4666   /* PREFIX_0F38F0 */
4667   {
4668     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4669     { Bad_Opcode },
4670     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4671     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4672   },
4673
4674   /* PREFIX_0F38F1 */
4675   {
4676     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4677     { Bad_Opcode },
4678     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4679     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4680   },
4681
4682   /* PREFIX_0F38F5 */
4683   {
4684     { Bad_Opcode },
4685     { Bad_Opcode },
4686     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4687   },
4688
4689   /* PREFIX_0F38F6 */
4690   {
4691     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4692     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4693     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4694     { Bad_Opcode },
4695   },
4696
4697   /* PREFIX_0F38F8 */
4698   {
4699     { Bad_Opcode },
4700     { Bad_Opcode },
4701     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4702   },
4703
4704   /* PREFIX_0F38F9 */
4705   {
4706     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4707   },
4708
4709   /* PREFIX_0F3A08 */
4710   {
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4714   },
4715
4716   /* PREFIX_0F3A09 */
4717   {
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4721   },
4722
4723   /* PREFIX_0F3A0A */
4724   {
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4728   },
4729
4730   /* PREFIX_0F3A0B */
4731   {
4732     { Bad_Opcode },
4733     { Bad_Opcode },
4734     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4735   },
4736
4737   /* PREFIX_0F3A0C */
4738   {
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4742   },
4743
4744   /* PREFIX_0F3A0D */
4745   {
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4749   },
4750
4751   /* PREFIX_0F3A0E */
4752   {
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4756   },
4757
4758   /* PREFIX_0F3A14 */
4759   {
4760     { Bad_Opcode },
4761     { Bad_Opcode },
4762     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4763   },
4764
4765   /* PREFIX_0F3A15 */
4766   {
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4770   },
4771
4772   /* PREFIX_0F3A16 */
4773   {
4774     { Bad_Opcode },
4775     { Bad_Opcode },
4776     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4777   },
4778
4779   /* PREFIX_0F3A17 */
4780   {
4781     { Bad_Opcode },
4782     { Bad_Opcode },
4783     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4784   },
4785
4786   /* PREFIX_0F3A20 */
4787   {
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4791   },
4792
4793   /* PREFIX_0F3A21 */
4794   {
4795     { Bad_Opcode },
4796     { Bad_Opcode },
4797     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4798   },
4799
4800   /* PREFIX_0F3A22 */
4801   {
4802     { Bad_Opcode },
4803     { Bad_Opcode },
4804     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4805   },
4806
4807   /* PREFIX_0F3A40 */
4808   {
4809     { Bad_Opcode },
4810     { Bad_Opcode },
4811     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4812   },
4813
4814   /* PREFIX_0F3A41 */
4815   {
4816     { Bad_Opcode },
4817     { Bad_Opcode },
4818     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4819   },
4820
4821   /* PREFIX_0F3A42 */
4822   {
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4826   },
4827
4828   /* PREFIX_0F3A44 */
4829   {
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4833   },
4834
4835   /* PREFIX_0F3A60 */
4836   {
4837     { Bad_Opcode },
4838     { Bad_Opcode },
4839     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4840   },
4841
4842   /* PREFIX_0F3A61 */
4843   {
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4847   },
4848
4849   /* PREFIX_0F3A62 */
4850   {
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4854   },
4855
4856   /* PREFIX_0F3A63 */
4857   {
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4861   },
4862
4863   /* PREFIX_0F3ACC */
4864   {
4865     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4866   },
4867
4868   /* PREFIX_0F3ACE */
4869   {
4870     { Bad_Opcode },
4871     { Bad_Opcode },
4872     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4873   },
4874
4875   /* PREFIX_0F3ACF */
4876   {
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4880   },
4881
4882   /* PREFIX_0F3ADF */
4883   {
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4887   },
4888
4889   /* PREFIX_VEX_0F10 */
4890   {
4891     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4892     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4893     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4894     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4895   },
4896
4897   /* PREFIX_VEX_0F11 */
4898   {
4899     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4900     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4901     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4902     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4903   },
4904
4905   /* PREFIX_VEX_0F12 */
4906   {
4907     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4908     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4909     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4910     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4911   },
4912
4913   /* PREFIX_VEX_0F16 */
4914   {
4915     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4916     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4917     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4918   },
4919
4920   /* PREFIX_VEX_0F2A */
4921   {
4922     { Bad_Opcode },
4923     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4924     { Bad_Opcode },
4925     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4926   },
4927
4928   /* PREFIX_VEX_0F2C */
4929   {
4930     { Bad_Opcode },
4931     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4932     { Bad_Opcode },
4933     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4934   },
4935
4936   /* PREFIX_VEX_0F2D */
4937   {
4938     { Bad_Opcode },
4939     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4940     { Bad_Opcode },
4941     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4942   },
4943
4944   /* PREFIX_VEX_0F2E */
4945   {
4946     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4947     { Bad_Opcode },
4948     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4949   },
4950
4951   /* PREFIX_VEX_0F2F */
4952   {
4953     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4954     { Bad_Opcode },
4955     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4956   },
4957
4958   /* PREFIX_VEX_0F41 */
4959   {
4960     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4961     { Bad_Opcode },
4962     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4963   },
4964
4965   /* PREFIX_VEX_0F42 */
4966   {
4967     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4968     { Bad_Opcode },
4969     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4970   },
4971
4972   /* PREFIX_VEX_0F44 */
4973   {
4974     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4975     { Bad_Opcode },
4976     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4977   },
4978
4979   /* PREFIX_VEX_0F45 */
4980   {
4981     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4982     { Bad_Opcode },
4983     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4984   },
4985
4986   /* PREFIX_VEX_0F46 */
4987   {
4988     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4989     { Bad_Opcode },
4990     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4991   },
4992
4993   /* PREFIX_VEX_0F47 */
4994   {
4995     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4996     { Bad_Opcode },
4997     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4998   },
4999
5000   /* PREFIX_VEX_0F4A */
5001   {
5002     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
5003     { Bad_Opcode },
5004     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
5005   },
5006
5007   /* PREFIX_VEX_0F4B */
5008   {
5009     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
5010     { Bad_Opcode },
5011     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
5012   },
5013
5014   /* PREFIX_VEX_0F51 */
5015   {
5016     { VEX_W_TABLE (VEX_W_0F51_P_0) },
5017     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
5018     { VEX_W_TABLE (VEX_W_0F51_P_2) },
5019     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
5020   },
5021
5022   /* PREFIX_VEX_0F52 */
5023   {
5024     { VEX_W_TABLE (VEX_W_0F52_P_0) },
5025     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
5026   },
5027
5028   /* PREFIX_VEX_0F53 */
5029   {
5030     { VEX_W_TABLE (VEX_W_0F53_P_0) },
5031     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
5032   },
5033
5034   /* PREFIX_VEX_0F58 */
5035   {
5036     { VEX_W_TABLE (VEX_W_0F58_P_0) },
5037     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
5038     { VEX_W_TABLE (VEX_W_0F58_P_2) },
5039     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
5040   },
5041
5042   /* PREFIX_VEX_0F59 */
5043   {
5044     { VEX_W_TABLE (VEX_W_0F59_P_0) },
5045     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
5046     { VEX_W_TABLE (VEX_W_0F59_P_2) },
5047     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
5048   },
5049
5050   /* PREFIX_VEX_0F5A */
5051   {
5052     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
5053     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
5054     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
5055     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
5056   },
5057
5058   /* PREFIX_VEX_0F5B */
5059   {
5060     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
5061     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
5062     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
5063   },
5064
5065   /* PREFIX_VEX_0F5C */
5066   {
5067     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
5068     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
5069     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
5070     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
5071   },
5072
5073   /* PREFIX_VEX_0F5D */
5074   {
5075     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
5076     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
5077     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
5078     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
5079   },
5080
5081   /* PREFIX_VEX_0F5E */
5082   {
5083     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
5084     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
5085     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
5086     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
5087   },
5088
5089   /* PREFIX_VEX_0F5F */
5090   {
5091     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
5092     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
5093     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
5094     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
5095   },
5096
5097   /* PREFIX_VEX_0F60 */
5098   {
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { VEX_W_TABLE (VEX_W_0F60_P_2) },
5102   },
5103
5104   /* PREFIX_VEX_0F61 */
5105   {
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { VEX_W_TABLE (VEX_W_0F61_P_2) },
5109   },
5110
5111   /* PREFIX_VEX_0F62 */
5112   {
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { VEX_W_TABLE (VEX_W_0F62_P_2) },
5116   },
5117
5118   /* PREFIX_VEX_0F63 */
5119   {
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { VEX_W_TABLE (VEX_W_0F63_P_2) },
5123   },
5124
5125   /* PREFIX_VEX_0F64 */
5126   {
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { VEX_W_TABLE (VEX_W_0F64_P_2) },
5130   },
5131
5132   /* PREFIX_VEX_0F65 */
5133   {
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { VEX_W_TABLE (VEX_W_0F65_P_2) },
5137   },
5138
5139   /* PREFIX_VEX_0F66 */
5140   {
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { VEX_W_TABLE (VEX_W_0F66_P_2) },
5144   },
5145
5146   /* PREFIX_VEX_0F67 */
5147   {
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { VEX_W_TABLE (VEX_W_0F67_P_2) },
5151   },
5152
5153   /* PREFIX_VEX_0F68 */
5154   {
5155     { Bad_Opcode },
5156     { Bad_Opcode },
5157     { VEX_W_TABLE (VEX_W_0F68_P_2) },
5158   },
5159
5160   /* PREFIX_VEX_0F69 */
5161   {
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     { VEX_W_TABLE (VEX_W_0F69_P_2) },
5165   },
5166
5167   /* PREFIX_VEX_0F6A */
5168   {
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5172   },
5173
5174   /* PREFIX_VEX_0F6B */
5175   {
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5179   },
5180
5181   /* PREFIX_VEX_0F6C */
5182   {
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5186   },
5187
5188   /* PREFIX_VEX_0F6D */
5189   {
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5193   },
5194
5195   /* PREFIX_VEX_0F6E */
5196   {
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5200   },
5201
5202   /* PREFIX_VEX_0F6F */
5203   {
5204     { Bad_Opcode },
5205     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5206     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5207   },
5208
5209   /* PREFIX_VEX_0F70 */
5210   {
5211     { Bad_Opcode },
5212     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5213     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5214     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5215   },
5216
5217   /* PREFIX_VEX_0F71_REG_2 */
5218   {
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5222   },
5223
5224   /* PREFIX_VEX_0F71_REG_4 */
5225   {
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5229   },
5230
5231   /* PREFIX_VEX_0F71_REG_6 */
5232   {
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5236   },
5237
5238   /* PREFIX_VEX_0F72_REG_2 */
5239   {
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5243   },
5244
5245   /* PREFIX_VEX_0F72_REG_4 */
5246   {
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5250   },
5251
5252   /* PREFIX_VEX_0F72_REG_6 */
5253   {
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5257   },
5258
5259   /* PREFIX_VEX_0F73_REG_2 */
5260   {
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5264   },
5265
5266   /* PREFIX_VEX_0F73_REG_3 */
5267   {
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5271   },
5272
5273   /* PREFIX_VEX_0F73_REG_6 */
5274   {
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5278   },
5279
5280   /* PREFIX_VEX_0F73_REG_7 */
5281   {
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5285   },
5286
5287   /* PREFIX_VEX_0F74 */
5288   {
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5292   },
5293
5294   /* PREFIX_VEX_0F75 */
5295   {
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5299   },
5300
5301   /* PREFIX_VEX_0F76 */
5302   {
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5306   },
5307
5308   /* PREFIX_VEX_0F77 */
5309   {
5310     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5311   },
5312
5313   /* PREFIX_VEX_0F7C */
5314   {
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5318     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5319   },
5320
5321   /* PREFIX_VEX_0F7D */
5322   {
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5326     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5327   },
5328
5329   /* PREFIX_VEX_0F7E */
5330   {
5331     { Bad_Opcode },
5332     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5333     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5334   },
5335
5336   /* PREFIX_VEX_0F7F */
5337   {
5338     { Bad_Opcode },
5339     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5340     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5341   },
5342
5343   /* PREFIX_VEX_0F90 */
5344   {
5345     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5346     { Bad_Opcode },
5347     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5348   },
5349
5350   /* PREFIX_VEX_0F91 */
5351   {
5352     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5353     { Bad_Opcode },
5354     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5355   },
5356
5357   /* PREFIX_VEX_0F92 */
5358   {
5359     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5360     { Bad_Opcode },
5361     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5362     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5363   },
5364
5365   /* PREFIX_VEX_0F93 */
5366   {
5367     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5368     { Bad_Opcode },
5369     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5370     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5371   },
5372
5373   /* PREFIX_VEX_0F98 */
5374   {
5375     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5376     { Bad_Opcode },
5377     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5378   },
5379
5380   /* PREFIX_VEX_0F99 */
5381   {
5382     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5383     { Bad_Opcode },
5384     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5385   },
5386
5387   /* PREFIX_VEX_0FC2 */
5388   {
5389     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5390     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5391     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5392     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5393   },
5394
5395   /* PREFIX_VEX_0FC4 */
5396   {
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5400   },
5401
5402   /* PREFIX_VEX_0FC5 */
5403   {
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5407   },
5408
5409   /* PREFIX_VEX_0FD0 */
5410   {
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5414     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5415   },
5416
5417   /* PREFIX_VEX_0FD1 */
5418   {
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5422   },
5423
5424   /* PREFIX_VEX_0FD2 */
5425   {
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5429   },
5430
5431   /* PREFIX_VEX_0FD3 */
5432   {
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5436   },
5437
5438   /* PREFIX_VEX_0FD4 */
5439   {
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5443   },
5444
5445   /* PREFIX_VEX_0FD5 */
5446   {
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5450   },
5451
5452   /* PREFIX_VEX_0FD6 */
5453   {
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5457   },
5458
5459   /* PREFIX_VEX_0FD7 */
5460   {
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5464   },
5465
5466   /* PREFIX_VEX_0FD8 */
5467   {
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5471   },
5472
5473   /* PREFIX_VEX_0FD9 */
5474   {
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5478   },
5479
5480   /* PREFIX_VEX_0FDA */
5481   {
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5485   },
5486
5487   /* PREFIX_VEX_0FDB */
5488   {
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5492   },
5493
5494   /* PREFIX_VEX_0FDC */
5495   {
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5499   },
5500
5501   /* PREFIX_VEX_0FDD */
5502   {
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5506   },
5507
5508   /* PREFIX_VEX_0FDE */
5509   {
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5513   },
5514
5515   /* PREFIX_VEX_0FDF */
5516   {
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5520   },
5521
5522   /* PREFIX_VEX_0FE0 */
5523   {
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5527   },
5528
5529   /* PREFIX_VEX_0FE1 */
5530   {
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5534   },
5535
5536   /* PREFIX_VEX_0FE2 */
5537   {
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5541   },
5542
5543   /* PREFIX_VEX_0FE3 */
5544   {
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5548   },
5549
5550   /* PREFIX_VEX_0FE4 */
5551   {
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5555   },
5556
5557   /* PREFIX_VEX_0FE5 */
5558   {
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5562   },
5563
5564   /* PREFIX_VEX_0FE6 */
5565   {
5566     { Bad_Opcode },
5567     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5568     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5569     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5570   },
5571
5572   /* PREFIX_VEX_0FE7 */
5573   {
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5577   },
5578
5579   /* PREFIX_VEX_0FE8 */
5580   {
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5584   },
5585
5586   /* PREFIX_VEX_0FE9 */
5587   {
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5591   },
5592
5593   /* PREFIX_VEX_0FEA */
5594   {
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5598   },
5599
5600   /* PREFIX_VEX_0FEB */
5601   {
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5605   },
5606
5607   /* PREFIX_VEX_0FEC */
5608   {
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5612   },
5613
5614   /* PREFIX_VEX_0FED */
5615   {
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5619   },
5620
5621   /* PREFIX_VEX_0FEE */
5622   {
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5626   },
5627
5628   /* PREFIX_VEX_0FEF */
5629   {
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5633   },
5634
5635   /* PREFIX_VEX_0FF0 */
5636   {
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5641   },
5642
5643   /* PREFIX_VEX_0FF1 */
5644   {
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5648   },
5649
5650   /* PREFIX_VEX_0FF2 */
5651   {
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5655   },
5656
5657   /* PREFIX_VEX_0FF3 */
5658   {
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5662   },
5663
5664   /* PREFIX_VEX_0FF4 */
5665   {
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5669   },
5670
5671   /* PREFIX_VEX_0FF5 */
5672   {
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5676   },
5677
5678   /* PREFIX_VEX_0FF6 */
5679   {
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5683   },
5684
5685   /* PREFIX_VEX_0FF7 */
5686   {
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5690   },
5691
5692   /* PREFIX_VEX_0FF8 */
5693   {
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5697   },
5698
5699   /* PREFIX_VEX_0FF9 */
5700   {
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5704   },
5705
5706   /* PREFIX_VEX_0FFA */
5707   {
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5711   },
5712
5713   /* PREFIX_VEX_0FFB */
5714   {
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5718   },
5719
5720   /* PREFIX_VEX_0FFC */
5721   {
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5725   },
5726
5727   /* PREFIX_VEX_0FFD */
5728   {
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5732   },
5733
5734   /* PREFIX_VEX_0FFE */
5735   {
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5739   },
5740
5741   /* PREFIX_VEX_0F3800 */
5742   {
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5746   },
5747
5748   /* PREFIX_VEX_0F3801 */
5749   {
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5753   },
5754
5755   /* PREFIX_VEX_0F3802 */
5756   {
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5760   },
5761
5762   /* PREFIX_VEX_0F3803 */
5763   {
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5767   },
5768
5769   /* PREFIX_VEX_0F3804 */
5770   {
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5774   },
5775
5776   /* PREFIX_VEX_0F3805 */
5777   {
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5781   },
5782
5783   /* PREFIX_VEX_0F3806 */
5784   {
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5788   },
5789
5790   /* PREFIX_VEX_0F3807 */
5791   {
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5795   },
5796
5797   /* PREFIX_VEX_0F3808 */
5798   {
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5802   },
5803
5804   /* PREFIX_VEX_0F3809 */
5805   {
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5809   },
5810
5811   /* PREFIX_VEX_0F380A */
5812   {
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5816   },
5817
5818   /* PREFIX_VEX_0F380B */
5819   {
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5823   },
5824
5825   /* PREFIX_VEX_0F380C */
5826   {
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5830   },
5831
5832   /* PREFIX_VEX_0F380D */
5833   {
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5837   },
5838
5839   /* PREFIX_VEX_0F380E */
5840   {
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5844   },
5845
5846   /* PREFIX_VEX_0F380F */
5847   {
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5851   },
5852
5853   /* PREFIX_VEX_0F3813 */
5854   {
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5858   },
5859
5860   /* PREFIX_VEX_0F3816 */
5861   {
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5865   },
5866
5867   /* PREFIX_VEX_0F3817 */
5868   {
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5872   },
5873
5874   /* PREFIX_VEX_0F3818 */
5875   {
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5879   },
5880
5881   /* PREFIX_VEX_0F3819 */
5882   {
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5886   },
5887
5888   /* PREFIX_VEX_0F381A */
5889   {
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5893   },
5894
5895   /* PREFIX_VEX_0F381C */
5896   {
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5900   },
5901
5902   /* PREFIX_VEX_0F381D */
5903   {
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5907   },
5908
5909   /* PREFIX_VEX_0F381E */
5910   {
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5914   },
5915
5916   /* PREFIX_VEX_0F3820 */
5917   {
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5921   },
5922
5923   /* PREFIX_VEX_0F3821 */
5924   {
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5928   },
5929
5930   /* PREFIX_VEX_0F3822 */
5931   {
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5935   },
5936
5937   /* PREFIX_VEX_0F3823 */
5938   {
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5942   },
5943
5944   /* PREFIX_VEX_0F3824 */
5945   {
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5949   },
5950
5951   /* PREFIX_VEX_0F3825 */
5952   {
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5956   },
5957
5958   /* PREFIX_VEX_0F3828 */
5959   {
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5963   },
5964
5965   /* PREFIX_VEX_0F3829 */
5966   {
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5970   },
5971
5972   /* PREFIX_VEX_0F382A */
5973   {
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5977   },
5978
5979   /* PREFIX_VEX_0F382B */
5980   {
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5984   },
5985
5986   /* PREFIX_VEX_0F382C */
5987   {
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5991   },
5992
5993   /* PREFIX_VEX_0F382D */
5994   {
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5998   },
5999
6000   /* PREFIX_VEX_0F382E */
6001   {
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
6005   },
6006
6007   /* PREFIX_VEX_0F382F */
6008   {
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
6012   },
6013
6014   /* PREFIX_VEX_0F3830 */
6015   {
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
6019   },
6020
6021   /* PREFIX_VEX_0F3831 */
6022   {
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
6026   },
6027
6028   /* PREFIX_VEX_0F3832 */
6029   {
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
6033   },
6034
6035   /* PREFIX_VEX_0F3833 */
6036   {
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
6040   },
6041
6042   /* PREFIX_VEX_0F3834 */
6043   {
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
6047   },
6048
6049   /* PREFIX_VEX_0F3835 */
6050   {
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
6054   },
6055
6056   /* PREFIX_VEX_0F3836 */
6057   {
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
6061   },
6062
6063   /* PREFIX_VEX_0F3837 */
6064   {
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
6068   },
6069
6070   /* PREFIX_VEX_0F3838 */
6071   {
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
6075   },
6076
6077   /* PREFIX_VEX_0F3839 */
6078   {
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
6082   },
6083
6084   /* PREFIX_VEX_0F383A */
6085   {
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
6089   },
6090
6091   /* PREFIX_VEX_0F383B */
6092   {
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
6096   },
6097
6098   /* PREFIX_VEX_0F383C */
6099   {
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
6103   },
6104
6105   /* PREFIX_VEX_0F383D */
6106   {
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
6110   },
6111
6112   /* PREFIX_VEX_0F383E */
6113   {
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
6117   },
6118
6119   /* PREFIX_VEX_0F383F */
6120   {
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
6124   },
6125
6126   /* PREFIX_VEX_0F3840 */
6127   {
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6131   },
6132
6133   /* PREFIX_VEX_0F3841 */
6134   {
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6138   },
6139
6140   /* PREFIX_VEX_0F3845 */
6141   {
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6145   },
6146
6147   /* PREFIX_VEX_0F3846 */
6148   {
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6152   },
6153
6154   /* PREFIX_VEX_0F3847 */
6155   {
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6159   },
6160
6161   /* PREFIX_VEX_0F3858 */
6162   {
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6166   },
6167
6168   /* PREFIX_VEX_0F3859 */
6169   {
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6173   },
6174
6175   /* PREFIX_VEX_0F385A */
6176   {
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6180   },
6181
6182   /* PREFIX_VEX_0F3878 */
6183   {
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6187   },
6188
6189   /* PREFIX_VEX_0F3879 */
6190   {
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6194   },
6195
6196   /* PREFIX_VEX_0F388C */
6197   {
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6201   },
6202
6203   /* PREFIX_VEX_0F388E */
6204   {
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6208   },
6209
6210   /* PREFIX_VEX_0F3890 */
6211   {
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6215   },
6216
6217   /* PREFIX_VEX_0F3891 */
6218   {
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6222   },
6223
6224   /* PREFIX_VEX_0F3892 */
6225   {
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6229   },
6230
6231   /* PREFIX_VEX_0F3893 */
6232   {
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6236   },
6237
6238   /* PREFIX_VEX_0F3896 */
6239   {
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6243   },
6244
6245   /* PREFIX_VEX_0F3897 */
6246   {
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6250   },
6251
6252   /* PREFIX_VEX_0F3898 */
6253   {
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6257   },
6258
6259   /* PREFIX_VEX_0F3899 */
6260   {
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6264   },
6265
6266   /* PREFIX_VEX_0F389A */
6267   {
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6271   },
6272
6273   /* PREFIX_VEX_0F389B */
6274   {
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6278   },
6279
6280   /* PREFIX_VEX_0F389C */
6281   {
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6285   },
6286
6287   /* PREFIX_VEX_0F389D */
6288   {
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6292   },
6293
6294   /* PREFIX_VEX_0F389E */
6295   {
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6299   },
6300
6301   /* PREFIX_VEX_0F389F */
6302   {
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6306   },
6307
6308   /* PREFIX_VEX_0F38A6 */
6309   {
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6313     { Bad_Opcode },
6314   },
6315
6316   /* PREFIX_VEX_0F38A7 */
6317   {
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6321   },
6322
6323   /* PREFIX_VEX_0F38A8 */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6328   },
6329
6330   /* PREFIX_VEX_0F38A9 */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6335   },
6336
6337   /* PREFIX_VEX_0F38AA */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6342   },
6343
6344   /* PREFIX_VEX_0F38AB */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6349   },
6350
6351   /* PREFIX_VEX_0F38AC */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6356   },
6357
6358   /* PREFIX_VEX_0F38AD */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6363   },
6364
6365   /* PREFIX_VEX_0F38AE */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6370   },
6371
6372   /* PREFIX_VEX_0F38AF */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6377   },
6378
6379   /* PREFIX_VEX_0F38B6 */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6384   },
6385
6386   /* PREFIX_VEX_0F38B7 */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6391   },
6392
6393   /* PREFIX_VEX_0F38B8 */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6398   },
6399
6400   /* PREFIX_VEX_0F38B9 */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6405   },
6406
6407   /* PREFIX_VEX_0F38BA */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6412   },
6413
6414   /* PREFIX_VEX_0F38BB */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6419   },
6420
6421   /* PREFIX_VEX_0F38BC */
6422   {
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6426   },
6427
6428   /* PREFIX_VEX_0F38BD */
6429   {
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6433   },
6434
6435   /* PREFIX_VEX_0F38BE */
6436   {
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6440   },
6441
6442   /* PREFIX_VEX_0F38BF */
6443   {
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6447   },
6448
6449   /* PREFIX_VEX_0F38CF */
6450   {
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6454   },
6455
6456   /* PREFIX_VEX_0F38DB */
6457   {
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6461   },
6462
6463   /* PREFIX_VEX_0F38DC */
6464   {
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { "vaesenc",        { XM, Vex, EXx }, 0 },
6468   },
6469
6470   /* PREFIX_VEX_0F38DD */
6471   {
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6475   },
6476
6477   /* PREFIX_VEX_0F38DE */
6478   {
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { "vaesdec",        { XM, Vex, EXx }, 0 },
6482   },
6483
6484   /* PREFIX_VEX_0F38DF */
6485   {
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6489   },
6490
6491   /* PREFIX_VEX_0F38F2 */
6492   {
6493     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6494   },
6495
6496   /* PREFIX_VEX_0F38F3_REG_1 */
6497   {
6498     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6499   },
6500
6501   /* PREFIX_VEX_0F38F3_REG_2 */
6502   {
6503     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6504   },
6505
6506   /* PREFIX_VEX_0F38F3_REG_3 */
6507   {
6508     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6509   },
6510
6511   /* PREFIX_VEX_0F38F5 */
6512   {
6513     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6514     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6515     { Bad_Opcode },
6516     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6517   },
6518
6519   /* PREFIX_VEX_0F38F6 */
6520   {
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6525   },
6526
6527   /* PREFIX_VEX_0F38F7 */
6528   {
6529     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6530     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6531     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6532     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6533   },
6534
6535   /* PREFIX_VEX_0F3A00 */
6536   {
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6540   },
6541
6542   /* PREFIX_VEX_0F3A01 */
6543   {
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6547   },
6548
6549   /* PREFIX_VEX_0F3A02 */
6550   {
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6554   },
6555
6556   /* PREFIX_VEX_0F3A04 */
6557   {
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6561   },
6562
6563   /* PREFIX_VEX_0F3A05 */
6564   {
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6568   },
6569
6570   /* PREFIX_VEX_0F3A06 */
6571   {
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6575   },
6576
6577   /* PREFIX_VEX_0F3A08 */
6578   {
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6582   },
6583
6584   /* PREFIX_VEX_0F3A09 */
6585   {
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6589   },
6590
6591   /* PREFIX_VEX_0F3A0A */
6592   {
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6596   },
6597
6598   /* PREFIX_VEX_0F3A0B */
6599   {
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6603   },
6604
6605   /* PREFIX_VEX_0F3A0C */
6606   {
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6610   },
6611
6612   /* PREFIX_VEX_0F3A0D */
6613   {
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6617   },
6618
6619   /* PREFIX_VEX_0F3A0E */
6620   {
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6624   },
6625
6626   /* PREFIX_VEX_0F3A0F */
6627   {
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6631   },
6632
6633   /* PREFIX_VEX_0F3A14 */
6634   {
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6638   },
6639
6640   /* PREFIX_VEX_0F3A15 */
6641   {
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6645   },
6646
6647   /* PREFIX_VEX_0F3A16 */
6648   {
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6652   },
6653
6654   /* PREFIX_VEX_0F3A17 */
6655   {
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6659   },
6660
6661   /* PREFIX_VEX_0F3A18 */
6662   {
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6666   },
6667
6668   /* PREFIX_VEX_0F3A19 */
6669   {
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6673   },
6674
6675   /* PREFIX_VEX_0F3A1D */
6676   {
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6680   },
6681
6682   /* PREFIX_VEX_0F3A20 */
6683   {
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6687   },
6688
6689   /* PREFIX_VEX_0F3A21 */
6690   {
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6694   },
6695
6696   /* PREFIX_VEX_0F3A22 */
6697   {
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6701   },
6702
6703   /* PREFIX_VEX_0F3A30 */
6704   {
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6708   },
6709
6710   /* PREFIX_VEX_0F3A31 */
6711   {
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6715   },
6716
6717   /* PREFIX_VEX_0F3A32 */
6718   {
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6722   },
6723
6724   /* PREFIX_VEX_0F3A33 */
6725   {
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6729   },
6730
6731   /* PREFIX_VEX_0F3A38 */
6732   {
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6736   },
6737
6738   /* PREFIX_VEX_0F3A39 */
6739   {
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6743   },
6744
6745   /* PREFIX_VEX_0F3A40 */
6746   {
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6750   },
6751
6752   /* PREFIX_VEX_0F3A41 */
6753   {
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6757   },
6758
6759   /* PREFIX_VEX_0F3A42 */
6760   {
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6764   },
6765
6766   /* PREFIX_VEX_0F3A44 */
6767   {
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6771   },
6772
6773   /* PREFIX_VEX_0F3A46 */
6774   {
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6778   },
6779
6780   /* PREFIX_VEX_0F3A48 */
6781   {
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6785   },
6786
6787   /* PREFIX_VEX_0F3A49 */
6788   {
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6792   },
6793
6794   /* PREFIX_VEX_0F3A4A */
6795   {
6796     { Bad_Opcode },
6797     { Bad_Opcode },
6798     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6799   },
6800
6801   /* PREFIX_VEX_0F3A4B */
6802   {
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6806   },
6807
6808   /* PREFIX_VEX_0F3A4C */
6809   {
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6813   },
6814
6815   /* PREFIX_VEX_0F3A5C */
6816   {
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6820   },
6821
6822   /* PREFIX_VEX_0F3A5D */
6823   {
6824     { Bad_Opcode },
6825     { Bad_Opcode },
6826     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6827   },
6828
6829   /* PREFIX_VEX_0F3A5E */
6830   {
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6834   },
6835
6836   /* PREFIX_VEX_0F3A5F */
6837   {
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6841   },
6842
6843   /* PREFIX_VEX_0F3A60 */
6844   {
6845     { Bad_Opcode },
6846     { Bad_Opcode },
6847     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6848     { Bad_Opcode },
6849   },
6850
6851   /* PREFIX_VEX_0F3A61 */
6852   {
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6856   },
6857
6858   /* PREFIX_VEX_0F3A62 */
6859   {
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6863   },
6864
6865   /* PREFIX_VEX_0F3A63 */
6866   {
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6870   },
6871
6872   /* PREFIX_VEX_0F3A68 */
6873   {
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6877   },
6878
6879   /* PREFIX_VEX_0F3A69 */
6880   {
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6884   },
6885
6886   /* PREFIX_VEX_0F3A6A */
6887   {
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6891   },
6892
6893   /* PREFIX_VEX_0F3A6B */
6894   {
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6898   },
6899
6900   /* PREFIX_VEX_0F3A6C */
6901   {
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6905   },
6906
6907   /* PREFIX_VEX_0F3A6D */
6908   {
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6912   },
6913
6914   /* PREFIX_VEX_0F3A6E */
6915   {
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6919   },
6920
6921   /* PREFIX_VEX_0F3A6F */
6922   {
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6926   },
6927
6928   /* PREFIX_VEX_0F3A78 */
6929   {
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6933   },
6934
6935   /* PREFIX_VEX_0F3A79 */
6936   {
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6940   },
6941
6942   /* PREFIX_VEX_0F3A7A */
6943   {
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6947   },
6948
6949   /* PREFIX_VEX_0F3A7B */
6950   {
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6954   },
6955
6956   /* PREFIX_VEX_0F3A7C */
6957   {
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6961     { Bad_Opcode },
6962   },
6963
6964   /* PREFIX_VEX_0F3A7D */
6965   {
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6969   },
6970
6971   /* PREFIX_VEX_0F3A7E */
6972   {
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6976   },
6977
6978   /* PREFIX_VEX_0F3A7F */
6979   {
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6983   },
6984
6985   /* PREFIX_VEX_0F3ACE */
6986   {
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6990   },
6991
6992   /* PREFIX_VEX_0F3ACF */
6993   {
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6997   },
6998
6999   /* PREFIX_VEX_0F3ADF */
7000   {
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
7004   },
7005
7006   /* PREFIX_VEX_0F3AF0 */
7007   {
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
7012   },
7013
7014 #define NEED_PREFIX_TABLE
7015 #include "i386-dis-evex.h"
7016 #undef NEED_PREFIX_TABLE
7017 };
7018
7019 static const struct dis386 x86_64_table[][2] = {
7020   /* X86_64_06 */
7021   {
7022     { "pushP", { es }, 0 },
7023   },
7024
7025   /* X86_64_07 */
7026   {
7027     { "popP", { es }, 0 },
7028   },
7029
7030   /* X86_64_0D */
7031   {
7032     { "pushP", { cs }, 0 },
7033   },
7034
7035   /* X86_64_16 */
7036   {
7037     { "pushP", { ss }, 0 },
7038   },
7039
7040   /* X86_64_17 */
7041   {
7042     { "popP", { ss }, 0 },
7043   },
7044
7045   /* X86_64_1E */
7046   {
7047     { "pushP", { ds }, 0 },
7048   },
7049
7050   /* X86_64_1F */
7051   {
7052     { "popP", { ds }, 0 },
7053   },
7054
7055   /* X86_64_27 */
7056   {
7057     { "daa", { XX }, 0 },
7058   },
7059
7060   /* X86_64_2F */
7061   {
7062     { "das", { XX }, 0 },
7063   },
7064
7065   /* X86_64_37 */
7066   {
7067     { "aaa", { XX }, 0 },
7068   },
7069
7070   /* X86_64_3F */
7071   {
7072     { "aas", { XX }, 0 },
7073   },
7074
7075   /* X86_64_60 */
7076   {
7077     { "pushaP", { XX }, 0 },
7078   },
7079
7080   /* X86_64_61 */
7081   {
7082     { "popaP", { XX }, 0 },
7083   },
7084
7085   /* X86_64_62 */
7086   {
7087     { MOD_TABLE (MOD_62_32BIT) },
7088     { EVEX_TABLE (EVEX_0F) },
7089   },
7090
7091   /* X86_64_63 */
7092   {
7093     { "arpl", { Ew, Gw }, 0 },
7094     { "movs{lq|xd}", { Gv, Ed }, 0 },
7095   },
7096
7097   /* X86_64_6D */
7098   {
7099     { "ins{R|}", { Yzr, indirDX }, 0 },
7100     { "ins{G|}", { Yzr, indirDX }, 0 },
7101   },
7102
7103   /* X86_64_6F */
7104   {
7105     { "outs{R|}", { indirDXr, Xz }, 0 },
7106     { "outs{G|}", { indirDXr, Xz }, 0 },
7107   },
7108
7109   /* X86_64_82 */
7110   {
7111     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
7112     { REG_TABLE (REG_80) },
7113   },
7114
7115   /* X86_64_9A */
7116   {
7117     { "Jcall{T|}", { Ap }, 0 },
7118   },
7119
7120   /* X86_64_C4 */
7121   {
7122     { MOD_TABLE (MOD_C4_32BIT) },
7123     { VEX_C4_TABLE (VEX_0F) },
7124   },
7125
7126   /* X86_64_C5 */
7127   {
7128     { MOD_TABLE (MOD_C5_32BIT) },
7129     { VEX_C5_TABLE (VEX_0F) },
7130   },
7131
7132   /* X86_64_CE */
7133   {
7134     { "into", { XX }, 0 },
7135   },
7136
7137   /* X86_64_D4 */
7138   {
7139     { "aam", { Ib }, 0 },
7140   },
7141
7142   /* X86_64_D5 */
7143   {
7144     { "aad", { Ib }, 0 },
7145   },
7146
7147   /* X86_64_E8 */
7148   {
7149     { "callP",          { Jv, BND }, 0 },
7150     { "call@",          { Jv, BND }, 0 }
7151   },
7152
7153   /* X86_64_E9 */
7154   {
7155     { "jmpP",           { Jv, BND }, 0 },
7156     { "jmp@",           { Jv, BND }, 0 }
7157   },
7158
7159   /* X86_64_EA */
7160   {
7161     { "Jjmp{T|}", { Ap }, 0 },
7162   },
7163
7164   /* X86_64_0F01_REG_0 */
7165   {
7166     { "sgdt{Q|IQ}", { M }, 0 },
7167     { "sgdt", { M }, 0 },
7168   },
7169
7170   /* X86_64_0F01_REG_1 */
7171   {
7172     { "sidt{Q|IQ}", { M }, 0 },
7173     { "sidt", { M }, 0 },
7174   },
7175
7176   /* X86_64_0F01_REG_2 */
7177   {
7178     { "lgdt{Q|Q}", { M }, 0 },
7179     { "lgdt", { M }, 0 },
7180   },
7181
7182   /* X86_64_0F01_REG_3 */
7183   {
7184     { "lidt{Q|Q}", { M }, 0 },
7185     { "lidt", { M }, 0 },
7186   },
7187 };
7188
7189 static const struct dis386 three_byte_table[][256] = {
7190
7191   /* THREE_BYTE_0F38 */
7192   {
7193     /* 00 */
7194     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7195     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7196     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7197     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7198     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7199     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7200     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7201     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7202     /* 08 */
7203     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7204     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7205     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7206     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     /* 10 */
7212     { PREFIX_TABLE (PREFIX_0F3810) },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { PREFIX_TABLE (PREFIX_0F3814) },
7217     { PREFIX_TABLE (PREFIX_0F3815) },
7218     { Bad_Opcode },
7219     { PREFIX_TABLE (PREFIX_0F3817) },
7220     /* 18 */
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7226     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7227     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7228     { Bad_Opcode },
7229     /* 20 */
7230     { PREFIX_TABLE (PREFIX_0F3820) },
7231     { PREFIX_TABLE (PREFIX_0F3821) },
7232     { PREFIX_TABLE (PREFIX_0F3822) },
7233     { PREFIX_TABLE (PREFIX_0F3823) },
7234     { PREFIX_TABLE (PREFIX_0F3824) },
7235     { PREFIX_TABLE (PREFIX_0F3825) },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     /* 28 */
7239     { PREFIX_TABLE (PREFIX_0F3828) },
7240     { PREFIX_TABLE (PREFIX_0F3829) },
7241     { PREFIX_TABLE (PREFIX_0F382A) },
7242     { PREFIX_TABLE (PREFIX_0F382B) },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     /* 30 */
7248     { PREFIX_TABLE (PREFIX_0F3830) },
7249     { PREFIX_TABLE (PREFIX_0F3831) },
7250     { PREFIX_TABLE (PREFIX_0F3832) },
7251     { PREFIX_TABLE (PREFIX_0F3833) },
7252     { PREFIX_TABLE (PREFIX_0F3834) },
7253     { PREFIX_TABLE (PREFIX_0F3835) },
7254     { Bad_Opcode },
7255     { PREFIX_TABLE (PREFIX_0F3837) },
7256     /* 38 */
7257     { PREFIX_TABLE (PREFIX_0F3838) },
7258     { PREFIX_TABLE (PREFIX_0F3839) },
7259     { PREFIX_TABLE (PREFIX_0F383A) },
7260     { PREFIX_TABLE (PREFIX_0F383B) },
7261     { PREFIX_TABLE (PREFIX_0F383C) },
7262     { PREFIX_TABLE (PREFIX_0F383D) },
7263     { PREFIX_TABLE (PREFIX_0F383E) },
7264     { PREFIX_TABLE (PREFIX_0F383F) },
7265     /* 40 */
7266     { PREFIX_TABLE (PREFIX_0F3840) },
7267     { PREFIX_TABLE (PREFIX_0F3841) },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     /* 48 */
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     /* 50 */
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     /* 58 */
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     /* 60 */
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     /* 68 */
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     /* 70 */
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     /* 78 */
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     /* 80 */
7338     { PREFIX_TABLE (PREFIX_0F3880) },
7339     { PREFIX_TABLE (PREFIX_0F3881) },
7340     { PREFIX_TABLE (PREFIX_0F3882) },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     /* 88 */
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     /* 90 */
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     /* 98 */
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     /* a0 */
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     /* a8 */
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     /* b0 */
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     /* b8 */
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     /* c0 */
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     /* c8 */
7419     { PREFIX_TABLE (PREFIX_0F38C8) },
7420     { PREFIX_TABLE (PREFIX_0F38C9) },
7421     { PREFIX_TABLE (PREFIX_0F38CA) },
7422     { PREFIX_TABLE (PREFIX_0F38CB) },
7423     { PREFIX_TABLE (PREFIX_0F38CC) },
7424     { PREFIX_TABLE (PREFIX_0F38CD) },
7425     { Bad_Opcode },
7426     { PREFIX_TABLE (PREFIX_0F38CF) },
7427     /* d0 */
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     /* d8 */
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { PREFIX_TABLE (PREFIX_0F38DB) },
7441     { PREFIX_TABLE (PREFIX_0F38DC) },
7442     { PREFIX_TABLE (PREFIX_0F38DD) },
7443     { PREFIX_TABLE (PREFIX_0F38DE) },
7444     { PREFIX_TABLE (PREFIX_0F38DF) },
7445     /* e0 */
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     /* e8 */
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     /* f0 */
7464     { PREFIX_TABLE (PREFIX_0F38F0) },
7465     { PREFIX_TABLE (PREFIX_0F38F1) },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { PREFIX_TABLE (PREFIX_0F38F5) },
7470     { PREFIX_TABLE (PREFIX_0F38F6) },
7471     { Bad_Opcode },
7472     /* f8 */
7473     { PREFIX_TABLE (PREFIX_0F38F8) },
7474     { PREFIX_TABLE (PREFIX_0F38F9) },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481   },
7482   /* THREE_BYTE_0F3A */
7483   {
7484     /* 00 */
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     /* 08 */
7494     { PREFIX_TABLE (PREFIX_0F3A08) },
7495     { PREFIX_TABLE (PREFIX_0F3A09) },
7496     { PREFIX_TABLE (PREFIX_0F3A0A) },
7497     { PREFIX_TABLE (PREFIX_0F3A0B) },
7498     { PREFIX_TABLE (PREFIX_0F3A0C) },
7499     { PREFIX_TABLE (PREFIX_0F3A0D) },
7500     { PREFIX_TABLE (PREFIX_0F3A0E) },
7501     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7502     /* 10 */
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { PREFIX_TABLE (PREFIX_0F3A14) },
7508     { PREFIX_TABLE (PREFIX_0F3A15) },
7509     { PREFIX_TABLE (PREFIX_0F3A16) },
7510     { PREFIX_TABLE (PREFIX_0F3A17) },
7511     /* 18 */
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     /* 20 */
7521     { PREFIX_TABLE (PREFIX_0F3A20) },
7522     { PREFIX_TABLE (PREFIX_0F3A21) },
7523     { PREFIX_TABLE (PREFIX_0F3A22) },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     /* 28 */
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     /* 30 */
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     /* 38 */
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     /* 40 */
7557     { PREFIX_TABLE (PREFIX_0F3A40) },
7558     { PREFIX_TABLE (PREFIX_0F3A41) },
7559     { PREFIX_TABLE (PREFIX_0F3A42) },
7560     { Bad_Opcode },
7561     { PREFIX_TABLE (PREFIX_0F3A44) },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     /* 48 */
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     /* 50 */
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     /* 58 */
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     /* 60 */
7593     { PREFIX_TABLE (PREFIX_0F3A60) },
7594     { PREFIX_TABLE (PREFIX_0F3A61) },
7595     { PREFIX_TABLE (PREFIX_0F3A62) },
7596     { PREFIX_TABLE (PREFIX_0F3A63) },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     /* 68 */
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     /* 70 */
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     /* 78 */
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     /* 80 */
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     /* 88 */
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     /* 90 */
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     /* 98 */
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     /* a0 */
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     /* a8 */
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     /* b0 */
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     /* b8 */
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     /* c0 */
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     /* c8 */
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { PREFIX_TABLE (PREFIX_0F3ACC) },
7715     { Bad_Opcode },
7716     { PREFIX_TABLE (PREFIX_0F3ACE) },
7717     { PREFIX_TABLE (PREFIX_0F3ACF) },
7718     /* d0 */
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     /* d8 */
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { PREFIX_TABLE (PREFIX_0F3ADF) },
7736     /* e0 */
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     /* e8 */
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     /* f0 */
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     /* f8 */
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772   },
7773 };
7774
7775 static const struct dis386 xop_table[][256] = {
7776   /* XOP_08 */
7777   {
7778     /* 00 */
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     /* 08 */
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     /* 10 */
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     /* 18 */
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     /* 20 */
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     /* 28 */
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     /* 30 */
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     /* 38 */
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     /* 40 */
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     /* 48 */
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     /* 50 */
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     /* 58 */
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     /* 60 */
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     /* 68 */
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     /* 70 */
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     /* 78 */
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     /* 80 */
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7929     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7930     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7931     /* 88 */
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7939     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7940     /* 90 */
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7947     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7948     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7949     /* 98 */
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7957     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7958     /* a0 */
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7962     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7966     { Bad_Opcode },
7967     /* a8 */
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     /* b0 */
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7984     { Bad_Opcode },
7985     /* b8 */
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     /* c0 */
7995     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7996     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7997     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7998     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     /* c8 */
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
8009     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
8010     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
8011     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
8012     /* d0 */
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     /* d8 */
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     /* e0 */
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     /* e8 */
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8045     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8046     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8047     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8048     /* f0 */
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     /* f8 */
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066   },
8067   /* XOP_09 */
8068   {
8069     /* 00 */
8070     { Bad_Opcode },
8071     { REG_TABLE (REG_XOP_TBM_01) },
8072     { REG_TABLE (REG_XOP_TBM_02) },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     /* 08 */
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     /* 10 */
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { REG_TABLE (REG_XOP_LWPCB) },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     /* 18 */
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     /* 20 */
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     /* 28 */
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     /* 30 */
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     /* 38 */
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     /* 40 */
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     /* 48 */
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     /* 50 */
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     /* 58 */
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     /* 60 */
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     /* 68 */
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     /* 70 */
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     /* 78 */
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     /* 80 */
8214     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8215     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8216     { "vfrczss",        { XM, EXd }, 0 },
8217     { "vfrczsd",        { XM, EXq }, 0 },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     /* 88 */
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     /* 90 */
8232     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8233     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8234     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8235     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8236     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8237     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8238     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8239     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8240     /* 98 */
8241     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8242     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8243     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8244     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     /* a0 */
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     /* a8 */
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     /* b0 */
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     /* b8 */
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     /* c0 */
8286     { Bad_Opcode },
8287     { "vphaddbw",       { XM, EXxmm }, 0 },
8288     { "vphaddbd",       { XM, EXxmm }, 0 },
8289     { "vphaddbq",       { XM, EXxmm }, 0 },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { "vphaddwd",       { XM, EXxmm }, 0 },
8293     { "vphaddwq",       { XM, EXxmm }, 0 },
8294     /* c8 */
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { "vphadddq",       { XM, EXxmm }, 0 },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     /* d0 */
8304     { Bad_Opcode },
8305     { "vphaddubw",      { XM, EXxmm }, 0 },
8306     { "vphaddubd",      { XM, EXxmm }, 0 },
8307     { "vphaddubq",      { XM, EXxmm }, 0 },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { "vphadduwd",      { XM, EXxmm }, 0 },
8311     { "vphadduwq",      { XM, EXxmm }, 0 },
8312     /* d8 */
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { "vphaddudq",      { XM, EXxmm }, 0 },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     /* e0 */
8322     { Bad_Opcode },
8323     { "vphsubbw",       { XM, EXxmm }, 0 },
8324     { "vphsubwd",       { XM, EXxmm }, 0 },
8325     { "vphsubdq",       { XM, EXxmm }, 0 },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     /* e8 */
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     /* f0 */
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     /* f8 */
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357   },
8358   /* XOP_0A */
8359   {
8360     /* 00 */
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     /* 08 */
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     /* 10 */
8379     { "bextr",  { Gv, Ev, Iq }, 0 },
8380     { Bad_Opcode },
8381     { REG_TABLE (REG_XOP_LWP) },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     /* 18 */
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     /* 20 */
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     /* 28 */
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     /* 30 */
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     /* 38 */
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     /* 40 */
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     /* 48 */
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     /* 50 */
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     /* 58 */
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     /* 60 */
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     /* 68 */
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     /* 70 */
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     /* 78 */
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     /* 80 */
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     /* 88 */
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     /* 90 */
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     /* 98 */
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     /* a0 */
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     /* a8 */
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     /* b0 */
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     /* b8 */
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     /* c0 */
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     /* c8 */
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     /* d0 */
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     /* d8 */
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     /* e0 */
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     /* e8 */
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     /* f0 */
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     /* f8 */
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648   },
8649 };
8650
8651 static const struct dis386 vex_table[][256] = {
8652   /* VEX_0F */
8653   {
8654     /* 00 */
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     /* 08 */
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     /* 10 */
8673     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8674     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8676     { MOD_TABLE (MOD_VEX_0F13) },
8677     { VEX_W_TABLE (VEX_W_0F14) },
8678     { VEX_W_TABLE (VEX_W_0F15) },
8679     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8680     { MOD_TABLE (MOD_VEX_0F17) },
8681     /* 18 */
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     /* 20 */
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     /* 28 */
8700     { VEX_W_TABLE (VEX_W_0F28) },
8701     { VEX_W_TABLE (VEX_W_0F29) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8703     { MOD_TABLE (MOD_VEX_0F2B) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8708     /* 30 */
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     /* 38 */
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     /* 40 */
8727     { Bad_Opcode },
8728     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8730     { Bad_Opcode },
8731     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8735     /* 48 */
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     /* 50 */
8745     { MOD_TABLE (MOD_VEX_0F50) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8749     { "vandpX",         { XM, Vex, EXx }, 0 },
8750     { "vandnpX",        { XM, Vex, EXx }, 0 },
8751     { "vorpX",          { XM, Vex, EXx }, 0 },
8752     { "vxorpX",         { XM, Vex, EXx }, 0 },
8753     /* 58 */
8754     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8762     /* 60 */
8763     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8771     /* 68 */
8772     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8780     /* 70 */
8781     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8782     { REG_TABLE (REG_VEX_0F71) },
8783     { REG_TABLE (REG_VEX_0F72) },
8784     { REG_TABLE (REG_VEX_0F73) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8789     /* 78 */
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8798     /* 80 */
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     /* 88 */
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     /* 90 */
8817     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8818     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8819     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     /* 98 */
8826     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     /* a0 */
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     /* a8 */
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { REG_TABLE (REG_VEX_0FAE) },
8851     { Bad_Opcode },
8852     /* b0 */
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     /* b8 */
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     /* c0 */
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8874     { Bad_Opcode },
8875     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8876     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8877     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8878     { Bad_Opcode },
8879     /* c8 */
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     /* d0 */
8889     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8890     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8891     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8892     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8893     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8894     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8895     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8896     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8897     /* d8 */
8898     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8899     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8900     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8901     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8902     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8903     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8904     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8905     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8906     /* e0 */
8907     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8908     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8909     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8910     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8911     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8912     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8913     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8914     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8915     /* e8 */
8916     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8917     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8918     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8919     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8920     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8921     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8922     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8923     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8924     /* f0 */
8925     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8926     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8927     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8928     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8929     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8930     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8931     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8932     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8933     /* f8 */
8934     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8935     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8936     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8937     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8938     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8939     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8940     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8941     { Bad_Opcode },
8942   },
8943   /* VEX_0F38 */
8944   {
8945     /* 00 */
8946     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8954     /* 08 */
8955     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8958     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8960     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8963     /* 10 */
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8972     /* 18 */
8973     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8976     { Bad_Opcode },
8977     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8979     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8980     { Bad_Opcode },
8981     /* 20 */
8982     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8985     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8986     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     /* 28 */
8991     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8999     /* 30 */
9000     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
9008     /* 38 */
9009     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
9015     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
9017     /* 40 */
9018     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
9024     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9026     /* 48 */
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     /* 50 */
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     /* 58 */
9045     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9046     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     /* 60 */
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     /* 68 */
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     /* 70 */
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     /* 78 */
9081     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9082     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     /* 80 */
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     /* 88 */
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9104     { Bad_Opcode },
9105     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9106     { Bad_Opcode },
9107     /* 90 */
9108     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9115     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9116     /* 98 */
9117     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9118     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9119     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9125     /* a0 */
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9134     /* a8 */
9135     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9140     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9141     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9142     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9143     /* b0 */
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9151     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9152     /* b8 */
9153     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9154     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9158     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9159     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9160     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9161     /* c0 */
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     /* c8 */
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9179     /* d0 */
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     /* d8 */
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9193     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9194     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9195     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9196     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9197     /* e0 */
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     /* e8 */
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     /* f0 */
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9219     { REG_TABLE (REG_VEX_0F38F3) },
9220     { Bad_Opcode },
9221     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9222     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9223     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9224     /* f8 */
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233   },
9234   /* VEX_0F3A */
9235   {
9236     /* 00 */
9237     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9238     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9239     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9240     { Bad_Opcode },
9241     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9242     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9243     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9244     { Bad_Opcode },
9245     /* 08 */
9246     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9247     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9248     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9249     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9250     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9251     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9252     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9253     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9254     /* 10 */
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9260     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9261     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9262     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9263     /* 18 */
9264     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9265     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     /* 20 */
9273     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9274     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9275     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     /* 28 */
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     /* 30 */
9291     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9292     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9293     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9294     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     /* 38 */
9300     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9301     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     /* 40 */
9309     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9310     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9311     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9312     { Bad_Opcode },
9313     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9314     { Bad_Opcode },
9315     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9316     { Bad_Opcode },
9317     /* 48 */
9318     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9319     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9320     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9321     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9322     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     /* 50 */
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     /* 58 */
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9341     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9342     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9343     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9344     /* 60 */
9345     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9346     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9347     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9348     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     /* 68 */
9354     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9355     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9356     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9357     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9358     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9359     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9360     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9361     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9362     /* 70 */
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     { Bad_Opcode },
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     /* 78 */
9372     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9373     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9374     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9375     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9376     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9377     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9378     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9379     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9380     /* 80 */
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     /* 88 */
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     /* 90 */
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     /* 98 */
9408     { Bad_Opcode },
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     /* a0 */
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     /* a8 */
9426     { Bad_Opcode },
9427     { Bad_Opcode },
9428     { Bad_Opcode },
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     /* b0 */
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     /* b8 */
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     /* c0 */
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461     /* c8 */
9462     { Bad_Opcode },
9463     { Bad_Opcode },
9464     { Bad_Opcode },
9465     { Bad_Opcode },
9466     { Bad_Opcode },
9467     { Bad_Opcode },
9468     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9469     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9470     /* d0 */
9471     { Bad_Opcode },
9472     { Bad_Opcode },
9473     { Bad_Opcode },
9474     { Bad_Opcode },
9475     { Bad_Opcode },
9476     { Bad_Opcode },
9477     { Bad_Opcode },
9478     { Bad_Opcode },
9479     /* d8 */
9480     { Bad_Opcode },
9481     { Bad_Opcode },
9482     { Bad_Opcode },
9483     { Bad_Opcode },
9484     { Bad_Opcode },
9485     { Bad_Opcode },
9486     { Bad_Opcode },
9487     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9488     /* e0 */
9489     { Bad_Opcode },
9490     { Bad_Opcode },
9491     { Bad_Opcode },
9492     { Bad_Opcode },
9493     { Bad_Opcode },
9494     { Bad_Opcode },
9495     { Bad_Opcode },
9496     { Bad_Opcode },
9497     /* e8 */
9498     { Bad_Opcode },
9499     { Bad_Opcode },
9500     { Bad_Opcode },
9501     { Bad_Opcode },
9502     { Bad_Opcode },
9503     { Bad_Opcode },
9504     { Bad_Opcode },
9505     { Bad_Opcode },
9506     /* f0 */
9507     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9508     { Bad_Opcode },
9509     { Bad_Opcode },
9510     { Bad_Opcode },
9511     { Bad_Opcode },
9512     { Bad_Opcode },
9513     { Bad_Opcode },
9514     { Bad_Opcode },
9515     /* f8 */
9516     { Bad_Opcode },
9517     { Bad_Opcode },
9518     { Bad_Opcode },
9519     { Bad_Opcode },
9520     { Bad_Opcode },
9521     { Bad_Opcode },
9522     { Bad_Opcode },
9523     { Bad_Opcode },
9524   },
9525 };
9526
9527 #define NEED_OPCODE_TABLE
9528 #include "i386-dis-evex.h"
9529 #undef NEED_OPCODE_TABLE
9530 static const struct dis386 vex_len_table[][2] = {
9531   /* VEX_LEN_0F10_P_1 */
9532   {
9533     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9534     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9535   },
9536
9537   /* VEX_LEN_0F10_P_3 */
9538   {
9539     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9540     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9541   },
9542
9543   /* VEX_LEN_0F11_P_1 */
9544   {
9545     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9546     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9547   },
9548
9549   /* VEX_LEN_0F11_P_3 */
9550   {
9551     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9552     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9553   },
9554
9555   /* VEX_LEN_0F12_P_0_M_0 */
9556   {
9557     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9558   },
9559
9560   /* VEX_LEN_0F12_P_0_M_1 */
9561   {
9562     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9563   },
9564
9565   /* VEX_LEN_0F12_P_2 */
9566   {
9567     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9568   },
9569
9570   /* VEX_LEN_0F13_M_0 */
9571   {
9572     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9573   },
9574
9575   /* VEX_LEN_0F16_P_0_M_0 */
9576   {
9577     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9578   },
9579
9580   /* VEX_LEN_0F16_P_0_M_1 */
9581   {
9582     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9583   },
9584
9585   /* VEX_LEN_0F16_P_2 */
9586   {
9587     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9588   },
9589
9590   /* VEX_LEN_0F17_M_0 */
9591   {
9592     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9593   },
9594
9595   /* VEX_LEN_0F2A_P_1 */
9596   {
9597     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9598     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9599   },
9600
9601   /* VEX_LEN_0F2A_P_3 */
9602   {
9603     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9604     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9605   },
9606
9607   /* VEX_LEN_0F2C_P_1 */
9608   {
9609     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9610     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9611   },
9612
9613   /* VEX_LEN_0F2C_P_3 */
9614   {
9615     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9616     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9617   },
9618
9619   /* VEX_LEN_0F2D_P_1 */
9620   {
9621     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9622     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9623   },
9624
9625   /* VEX_LEN_0F2D_P_3 */
9626   {
9627     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9628     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9629   },
9630
9631   /* VEX_LEN_0F2E_P_0 */
9632   {
9633     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9634     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9635   },
9636
9637   /* VEX_LEN_0F2E_P_2 */
9638   {
9639     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9640     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9641   },
9642
9643   /* VEX_LEN_0F2F_P_0 */
9644   {
9645     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9646     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9647   },
9648
9649   /* VEX_LEN_0F2F_P_2 */
9650   {
9651     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9652     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9653   },
9654
9655   /* VEX_LEN_0F41_P_0 */
9656   {
9657     { Bad_Opcode },
9658     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9659   },
9660   /* VEX_LEN_0F41_P_2 */
9661   {
9662     { Bad_Opcode },
9663     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9664   },
9665   /* VEX_LEN_0F42_P_0 */
9666   {
9667     { Bad_Opcode },
9668     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9669   },
9670   /* VEX_LEN_0F42_P_2 */
9671   {
9672     { Bad_Opcode },
9673     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9674   },
9675   /* VEX_LEN_0F44_P_0 */
9676   {
9677     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9678   },
9679   /* VEX_LEN_0F44_P_2 */
9680   {
9681     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9682   },
9683   /* VEX_LEN_0F45_P_0 */
9684   {
9685     { Bad_Opcode },
9686     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9687   },
9688   /* VEX_LEN_0F45_P_2 */
9689   {
9690     { Bad_Opcode },
9691     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9692   },
9693   /* VEX_LEN_0F46_P_0 */
9694   {
9695     { Bad_Opcode },
9696     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9697   },
9698   /* VEX_LEN_0F46_P_2 */
9699   {
9700     { Bad_Opcode },
9701     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9702   },
9703   /* VEX_LEN_0F47_P_0 */
9704   {
9705     { Bad_Opcode },
9706     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9707   },
9708   /* VEX_LEN_0F47_P_2 */
9709   {
9710     { Bad_Opcode },
9711     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9712   },
9713   /* VEX_LEN_0F4A_P_0 */
9714   {
9715     { Bad_Opcode },
9716     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9717   },
9718   /* VEX_LEN_0F4A_P_2 */
9719   {
9720     { Bad_Opcode },
9721     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9722   },
9723   /* VEX_LEN_0F4B_P_0 */
9724   {
9725     { Bad_Opcode },
9726     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9727   },
9728   /* VEX_LEN_0F4B_P_2 */
9729   {
9730     { Bad_Opcode },
9731     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9732   },
9733
9734   /* VEX_LEN_0F51_P_1 */
9735   {
9736     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9737     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9738   },
9739
9740   /* VEX_LEN_0F51_P_3 */
9741   {
9742     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9743     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9744   },
9745
9746   /* VEX_LEN_0F52_P_1 */
9747   {
9748     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9749     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9750   },
9751
9752   /* VEX_LEN_0F53_P_1 */
9753   {
9754     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9755     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9756   },
9757
9758   /* VEX_LEN_0F58_P_1 */
9759   {
9760     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9761     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9762   },
9763
9764   /* VEX_LEN_0F58_P_3 */
9765   {
9766     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9767     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9768   },
9769
9770   /* VEX_LEN_0F59_P_1 */
9771   {
9772     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9773     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9774   },
9775
9776   /* VEX_LEN_0F59_P_3 */
9777   {
9778     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9779     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9780   },
9781
9782   /* VEX_LEN_0F5A_P_1 */
9783   {
9784     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9785     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9786   },
9787
9788   /* VEX_LEN_0F5A_P_3 */
9789   {
9790     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9791     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9792   },
9793
9794   /* VEX_LEN_0F5C_P_1 */
9795   {
9796     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9797     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9798   },
9799
9800   /* VEX_LEN_0F5C_P_3 */
9801   {
9802     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9803     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9804   },
9805
9806   /* VEX_LEN_0F5D_P_1 */
9807   {
9808     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9809     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9810   },
9811
9812   /* VEX_LEN_0F5D_P_3 */
9813   {
9814     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9815     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9816   },
9817
9818   /* VEX_LEN_0F5E_P_1 */
9819   {
9820     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9821     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9822   },
9823
9824   /* VEX_LEN_0F5E_P_3 */
9825   {
9826     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9827     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9828   },
9829
9830   /* VEX_LEN_0F5F_P_1 */
9831   {
9832     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9833     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9834   },
9835
9836   /* VEX_LEN_0F5F_P_3 */
9837   {
9838     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9839     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9840   },
9841
9842   /* VEX_LEN_0F6E_P_2 */
9843   {
9844     { "vmovK",          { XMScalar, Edq }, 0 },
9845     { "vmovK",          { XMScalar, Edq }, 0 },
9846   },
9847
9848   /* VEX_LEN_0F7E_P_1 */
9849   {
9850     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9851     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9852   },
9853
9854   /* VEX_LEN_0F7E_P_2 */
9855   {
9856     { "vmovK",          { Edq, XMScalar }, 0 },
9857     { "vmovK",          { Edq, XMScalar }, 0 },
9858   },
9859
9860   /* VEX_LEN_0F90_P_0 */
9861   {
9862     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9863   },
9864
9865   /* VEX_LEN_0F90_P_2 */
9866   {
9867     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9868   },
9869
9870   /* VEX_LEN_0F91_P_0 */
9871   {
9872     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9873   },
9874
9875   /* VEX_LEN_0F91_P_2 */
9876   {
9877     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9878   },
9879
9880   /* VEX_LEN_0F92_P_0 */
9881   {
9882     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9883   },
9884
9885   /* VEX_LEN_0F92_P_2 */
9886   {
9887     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9888   },
9889
9890   /* VEX_LEN_0F92_P_3 */
9891   {
9892     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9893   },
9894
9895   /* VEX_LEN_0F93_P_0 */
9896   {
9897     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9898   },
9899
9900   /* VEX_LEN_0F93_P_2 */
9901   {
9902     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9903   },
9904
9905   /* VEX_LEN_0F93_P_3 */
9906   {
9907     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9908   },
9909
9910   /* VEX_LEN_0F98_P_0 */
9911   {
9912     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9913   },
9914
9915   /* VEX_LEN_0F98_P_2 */
9916   {
9917     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9918   },
9919
9920   /* VEX_LEN_0F99_P_0 */
9921   {
9922     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9923   },
9924
9925   /* VEX_LEN_0F99_P_2 */
9926   {
9927     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9928   },
9929
9930   /* VEX_LEN_0FAE_R_2_M_0 */
9931   {
9932     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9933   },
9934
9935   /* VEX_LEN_0FAE_R_3_M_0 */
9936   {
9937     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9938   },
9939
9940   /* VEX_LEN_0FC2_P_1 */
9941   {
9942     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9943     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9944   },
9945
9946   /* VEX_LEN_0FC2_P_3 */
9947   {
9948     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9949     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9950   },
9951
9952   /* VEX_LEN_0FC4_P_2 */
9953   {
9954     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9955   },
9956
9957   /* VEX_LEN_0FC5_P_2 */
9958   {
9959     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9960   },
9961
9962   /* VEX_LEN_0FD6_P_2 */
9963   {
9964     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9965     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9966   },
9967
9968   /* VEX_LEN_0FF7_P_2 */
9969   {
9970     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9971   },
9972
9973   /* VEX_LEN_0F3816_P_2 */
9974   {
9975     { Bad_Opcode },
9976     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9977   },
9978
9979   /* VEX_LEN_0F3819_P_2 */
9980   {
9981     { Bad_Opcode },
9982     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9983   },
9984
9985   /* VEX_LEN_0F381A_P_2_M_0 */
9986   {
9987     { Bad_Opcode },
9988     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9989   },
9990
9991   /* VEX_LEN_0F3836_P_2 */
9992   {
9993     { Bad_Opcode },
9994     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9995   },
9996
9997   /* VEX_LEN_0F3841_P_2 */
9998   {
9999     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
10000   },
10001
10002   /* VEX_LEN_0F385A_P_2_M_0 */
10003   {
10004     { Bad_Opcode },
10005     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
10006   },
10007
10008   /* VEX_LEN_0F38DB_P_2 */
10009   {
10010     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
10011   },
10012
10013   /* VEX_LEN_0F38F2_P_0 */
10014   {
10015     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
10016   },
10017
10018   /* VEX_LEN_0F38F3_R_1_P_0 */
10019   {
10020     { "blsrS",          { VexGdq, Edq }, 0 },
10021   },
10022
10023   /* VEX_LEN_0F38F3_R_2_P_0 */
10024   {
10025     { "blsmskS",        { VexGdq, Edq }, 0 },
10026   },
10027
10028   /* VEX_LEN_0F38F3_R_3_P_0 */
10029   {
10030     { "blsiS",          { VexGdq, Edq }, 0 },
10031   },
10032
10033   /* VEX_LEN_0F38F5_P_0 */
10034   {
10035     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
10036   },
10037
10038   /* VEX_LEN_0F38F5_P_1 */
10039   {
10040     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
10041   },
10042
10043   /* VEX_LEN_0F38F5_P_3 */
10044   {
10045     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
10046   },
10047
10048   /* VEX_LEN_0F38F6_P_3 */
10049   {
10050     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
10051   },
10052
10053   /* VEX_LEN_0F38F7_P_0 */
10054   {
10055     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
10056   },
10057
10058   /* VEX_LEN_0F38F7_P_1 */
10059   {
10060     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10061   },
10062
10063   /* VEX_LEN_0F38F7_P_2 */
10064   {
10065     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10066   },
10067
10068   /* VEX_LEN_0F38F7_P_3 */
10069   {
10070     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10071   },
10072
10073   /* VEX_LEN_0F3A00_P_2 */
10074   {
10075     { Bad_Opcode },
10076     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10077   },
10078
10079   /* VEX_LEN_0F3A01_P_2 */
10080   {
10081     { Bad_Opcode },
10082     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10083   },
10084
10085   /* VEX_LEN_0F3A06_P_2 */
10086   {
10087     { Bad_Opcode },
10088     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10089   },
10090
10091   /* VEX_LEN_0F3A0A_P_2 */
10092   {
10093     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10094     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10095   },
10096
10097   /* VEX_LEN_0F3A0B_P_2 */
10098   {
10099     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10100     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10101   },
10102
10103   /* VEX_LEN_0F3A14_P_2 */
10104   {
10105     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10106   },
10107
10108   /* VEX_LEN_0F3A15_P_2 */
10109   {
10110     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10111   },
10112
10113   /* VEX_LEN_0F3A16_P_2  */
10114   {
10115     { "vpextrK",        { Edq, XM, Ib }, 0 },
10116   },
10117
10118   /* VEX_LEN_0F3A17_P_2 */
10119   {
10120     { "vextractps",     { Edqd, XM, Ib }, 0 },
10121   },
10122
10123   /* VEX_LEN_0F3A18_P_2 */
10124   {
10125     { Bad_Opcode },
10126     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10127   },
10128
10129   /* VEX_LEN_0F3A19_P_2 */
10130   {
10131     { Bad_Opcode },
10132     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10133   },
10134
10135   /* VEX_LEN_0F3A20_P_2 */
10136   {
10137     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10138   },
10139
10140   /* VEX_LEN_0F3A21_P_2 */
10141   {
10142     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10143   },
10144
10145   /* VEX_LEN_0F3A22_P_2 */
10146   {
10147     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10148   },
10149
10150   /* VEX_LEN_0F3A30_P_2 */
10151   {
10152     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10153   },
10154
10155   /* VEX_LEN_0F3A31_P_2 */
10156   {
10157     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10158   },
10159
10160   /* VEX_LEN_0F3A32_P_2 */
10161   {
10162     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10163   },
10164
10165   /* VEX_LEN_0F3A33_P_2 */
10166   {
10167     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10168   },
10169
10170   /* VEX_LEN_0F3A38_P_2 */
10171   {
10172     { Bad_Opcode },
10173     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10174   },
10175
10176   /* VEX_LEN_0F3A39_P_2 */
10177   {
10178     { Bad_Opcode },
10179     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10180   },
10181
10182   /* VEX_LEN_0F3A41_P_2 */
10183   {
10184     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10185   },
10186
10187   /* VEX_LEN_0F3A46_P_2 */
10188   {
10189     { Bad_Opcode },
10190     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10191   },
10192
10193   /* VEX_LEN_0F3A60_P_2 */
10194   {
10195     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10196   },
10197
10198   /* VEX_LEN_0F3A61_P_2 */
10199   {
10200     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10201   },
10202
10203   /* VEX_LEN_0F3A62_P_2 */
10204   {
10205     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10206   },
10207
10208   /* VEX_LEN_0F3A63_P_2 */
10209   {
10210     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10211   },
10212
10213   /* VEX_LEN_0F3A6A_P_2 */
10214   {
10215     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10216   },
10217
10218   /* VEX_LEN_0F3A6B_P_2 */
10219   {
10220     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10221   },
10222
10223   /* VEX_LEN_0F3A6E_P_2 */
10224   {
10225     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10226   },
10227
10228   /* VEX_LEN_0F3A6F_P_2 */
10229   {
10230     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10231   },
10232
10233   /* VEX_LEN_0F3A7A_P_2 */
10234   {
10235     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10236   },
10237
10238   /* VEX_LEN_0F3A7B_P_2 */
10239   {
10240     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10241   },
10242
10243   /* VEX_LEN_0F3A7E_P_2 */
10244   {
10245     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10246   },
10247
10248   /* VEX_LEN_0F3A7F_P_2 */
10249   {
10250     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10251   },
10252
10253   /* VEX_LEN_0F3ADF_P_2 */
10254   {
10255     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10256   },
10257
10258   /* VEX_LEN_0F3AF0_P_3 */
10259   {
10260     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10261   },
10262
10263   /* VEX_LEN_0FXOP_08_CC */
10264   {
10265      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
10266   },
10267
10268   /* VEX_LEN_0FXOP_08_CD */
10269   {
10270      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
10271   },
10272
10273   /* VEX_LEN_0FXOP_08_CE */
10274   {
10275      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
10276   },
10277
10278   /* VEX_LEN_0FXOP_08_CF */
10279   {
10280      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
10281   },
10282
10283   /* VEX_LEN_0FXOP_08_EC */
10284   {
10285      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
10286   },
10287
10288   /* VEX_LEN_0FXOP_08_ED */
10289   {
10290      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
10291   },
10292
10293   /* VEX_LEN_0FXOP_08_EE */
10294   {
10295      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
10296   },
10297
10298   /* VEX_LEN_0FXOP_08_EF */
10299   {
10300      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
10301   },
10302
10303   /* VEX_LEN_0FXOP_09_80 */
10304   {
10305     { "vfrczps",        { XM, EXxmm }, 0 },
10306     { "vfrczps",        { XM, EXymmq }, 0 },
10307   },
10308
10309   /* VEX_LEN_0FXOP_09_81 */
10310   {
10311     { "vfrczpd",        { XM, EXxmm }, 0 },
10312     { "vfrczpd",        { XM, EXymmq }, 0 },
10313   },
10314 };
10315
10316 static const struct dis386 vex_w_table[][2] = {
10317   {
10318     /* VEX_W_0F10_P_0 */
10319     { "vmovups",        { XM, EXx }, 0 },
10320   },
10321   {
10322     /* VEX_W_0F10_P_1 */
10323     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10324   },
10325   {
10326     /* VEX_W_0F10_P_2 */
10327     { "vmovupd",        { XM, EXx }, 0 },
10328   },
10329   {
10330     /* VEX_W_0F10_P_3 */
10331     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10332   },
10333   {
10334     /* VEX_W_0F11_P_0 */
10335     { "vmovups",        { EXxS, XM }, 0 },
10336   },
10337   {
10338     /* VEX_W_0F11_P_1 */
10339     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10340   },
10341   {
10342     /* VEX_W_0F11_P_2 */
10343     { "vmovupd",        { EXxS, XM }, 0 },
10344   },
10345   {
10346     /* VEX_W_0F11_P_3 */
10347     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10348   },
10349   {
10350     /* VEX_W_0F12_P_0_M_0 */
10351     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10352   },
10353   {
10354     /* VEX_W_0F12_P_0_M_1 */
10355     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10356   },
10357   {
10358     /* VEX_W_0F12_P_1 */
10359     { "vmovsldup",      { XM, EXx }, 0 },
10360   },
10361   {
10362     /* VEX_W_0F12_P_2 */
10363     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10364   },
10365   {
10366     /* VEX_W_0F12_P_3 */
10367     { "vmovddup",       { XM, EXymmq }, 0 },
10368   },
10369   {
10370     /* VEX_W_0F13_M_0 */
10371     { "vmovlpX",        { EXq, XM }, 0 },
10372   },
10373   {
10374     /* VEX_W_0F14 */
10375     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10376   },
10377   {
10378     /* VEX_W_0F15 */
10379     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10380   },
10381   {
10382     /* VEX_W_0F16_P_0_M_0 */
10383     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10384   },
10385   {
10386     /* VEX_W_0F16_P_0_M_1 */
10387     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10388   },
10389   {
10390     /* VEX_W_0F16_P_1 */
10391     { "vmovshdup",      { XM, EXx }, 0 },
10392   },
10393   {
10394     /* VEX_W_0F16_P_2 */
10395     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10396   },
10397   {
10398     /* VEX_W_0F17_M_0 */
10399     { "vmovhpX",        { EXq, XM }, 0 },
10400   },
10401   {
10402     /* VEX_W_0F28 */
10403     { "vmovapX",        { XM, EXx }, 0 },
10404   },
10405   {
10406     /* VEX_W_0F29 */
10407     { "vmovapX",        { EXxS, XM }, 0 },
10408   },
10409   {
10410     /* VEX_W_0F2B_M_0 */
10411     { "vmovntpX",       { Mx, XM }, 0 },
10412   },
10413   {
10414     /* VEX_W_0F2E_P_0 */
10415     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10416   },
10417   {
10418     /* VEX_W_0F2E_P_2 */
10419     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10420   },
10421   {
10422     /* VEX_W_0F2F_P_0 */
10423     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10424   },
10425   {
10426     /* VEX_W_0F2F_P_2 */
10427     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10428   },
10429   {
10430     /* VEX_W_0F41_P_0_LEN_1 */
10431     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10432     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10433   },
10434   {
10435     /* VEX_W_0F41_P_2_LEN_1 */
10436     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10437     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10438   },
10439   {
10440     /* VEX_W_0F42_P_0_LEN_1 */
10441     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10442     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10443   },
10444   {
10445     /* VEX_W_0F42_P_2_LEN_1 */
10446     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10447     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10448   },
10449   {
10450     /* VEX_W_0F44_P_0_LEN_0 */
10451     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10452     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10453   },
10454   {
10455     /* VEX_W_0F44_P_2_LEN_0 */
10456     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10457     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10458   },
10459   {
10460     /* VEX_W_0F45_P_0_LEN_1 */
10461     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10462     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10463   },
10464   {
10465     /* VEX_W_0F45_P_2_LEN_1 */
10466     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10467     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10468   },
10469   {
10470     /* VEX_W_0F46_P_0_LEN_1 */
10471     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10472     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10473   },
10474   {
10475     /* VEX_W_0F46_P_2_LEN_1 */
10476     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10477     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10478   },
10479   {
10480     /* VEX_W_0F47_P_0_LEN_1 */
10481     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10482     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10483   },
10484   {
10485     /* VEX_W_0F47_P_2_LEN_1 */
10486     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10487     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10488   },
10489   {
10490     /* VEX_W_0F4A_P_0_LEN_1 */
10491     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10492     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10493   },
10494   {
10495     /* VEX_W_0F4A_P_2_LEN_1 */
10496     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10497     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10498   },
10499   {
10500     /* VEX_W_0F4B_P_0_LEN_1 */
10501     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10502     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10503   },
10504   {
10505     /* VEX_W_0F4B_P_2_LEN_1 */
10506     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10507   },
10508   {
10509     /* VEX_W_0F50_M_0 */
10510     { "vmovmskpX",      { Gdq, XS }, 0 },
10511   },
10512   {
10513     /* VEX_W_0F51_P_0 */
10514     { "vsqrtps",        { XM, EXx }, 0 },
10515   },
10516   {
10517     /* VEX_W_0F51_P_1 */
10518     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10519   },
10520   {
10521     /* VEX_W_0F51_P_2  */
10522     { "vsqrtpd",        { XM, EXx }, 0 },
10523   },
10524   {
10525     /* VEX_W_0F51_P_3 */
10526     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10527   },
10528   {
10529     /* VEX_W_0F52_P_0 */
10530     { "vrsqrtps",       { XM, EXx }, 0 },
10531   },
10532   {
10533     /* VEX_W_0F52_P_1 */
10534     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10535   },
10536   {
10537     /* VEX_W_0F53_P_0  */
10538     { "vrcpps",         { XM, EXx }, 0 },
10539   },
10540   {
10541     /* VEX_W_0F53_P_1  */
10542     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10543   },
10544   {
10545     /* VEX_W_0F58_P_0  */
10546     { "vaddps",         { XM, Vex, EXx }, 0 },
10547   },
10548   {
10549     /* VEX_W_0F58_P_1  */
10550     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10551   },
10552   {
10553     /* VEX_W_0F58_P_2  */
10554     { "vaddpd",         { XM, Vex, EXx }, 0 },
10555   },
10556   {
10557     /* VEX_W_0F58_P_3  */
10558     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10559   },
10560   {
10561     /* VEX_W_0F59_P_0  */
10562     { "vmulps",         { XM, Vex, EXx }, 0 },
10563   },
10564   {
10565     /* VEX_W_0F59_P_1  */
10566     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10567   },
10568   {
10569     /* VEX_W_0F59_P_2  */
10570     { "vmulpd",         { XM, Vex, EXx }, 0 },
10571   },
10572   {
10573     /* VEX_W_0F59_P_3  */
10574     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10575   },
10576   {
10577     /* VEX_W_0F5A_P_0  */
10578     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10579   },
10580   {
10581     /* VEX_W_0F5A_P_1  */
10582     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10583   },
10584   {
10585     /* VEX_W_0F5A_P_3  */
10586     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10587   },
10588   {
10589     /* VEX_W_0F5B_P_0  */
10590     { "vcvtdq2ps",      { XM, EXx }, 0 },
10591   },
10592   {
10593     /* VEX_W_0F5B_P_1  */
10594     { "vcvttps2dq",     { XM, EXx }, 0 },
10595   },
10596   {
10597     /* VEX_W_0F5B_P_2  */
10598     { "vcvtps2dq",      { XM, EXx }, 0 },
10599   },
10600   {
10601     /* VEX_W_0F5C_P_0  */
10602     { "vsubps",         { XM, Vex, EXx }, 0 },
10603   },
10604   {
10605     /* VEX_W_0F5C_P_1  */
10606     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10607   },
10608   {
10609     /* VEX_W_0F5C_P_2  */
10610     { "vsubpd",         { XM, Vex, EXx }, 0 },
10611   },
10612   {
10613     /* VEX_W_0F5C_P_3  */
10614     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10615   },
10616   {
10617     /* VEX_W_0F5D_P_0  */
10618     { "vminps",         { XM, Vex, EXx }, 0 },
10619   },
10620   {
10621     /* VEX_W_0F5D_P_1  */
10622     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10623   },
10624   {
10625     /* VEX_W_0F5D_P_2  */
10626     { "vminpd",         { XM, Vex, EXx }, 0 },
10627   },
10628   {
10629     /* VEX_W_0F5D_P_3  */
10630     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10631   },
10632   {
10633     /* VEX_W_0F5E_P_0  */
10634     { "vdivps",         { XM, Vex, EXx }, 0 },
10635   },
10636   {
10637     /* VEX_W_0F5E_P_1  */
10638     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10639   },
10640   {
10641     /* VEX_W_0F5E_P_2  */
10642     { "vdivpd",         { XM, Vex, EXx }, 0 },
10643   },
10644   {
10645     /* VEX_W_0F5E_P_3  */
10646     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10647   },
10648   {
10649     /* VEX_W_0F5F_P_0  */
10650     { "vmaxps",         { XM, Vex, EXx }, 0 },
10651   },
10652   {
10653     /* VEX_W_0F5F_P_1  */
10654     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10655   },
10656   {
10657     /* VEX_W_0F5F_P_2  */
10658     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10659   },
10660   {
10661     /* VEX_W_0F5F_P_3  */
10662     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10663   },
10664   {
10665     /* VEX_W_0F60_P_2  */
10666     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10667   },
10668   {
10669     /* VEX_W_0F61_P_2  */
10670     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10671   },
10672   {
10673     /* VEX_W_0F62_P_2  */
10674     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10675   },
10676   {
10677     /* VEX_W_0F63_P_2  */
10678     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10679   },
10680   {
10681     /* VEX_W_0F64_P_2  */
10682     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10683   },
10684   {
10685     /* VEX_W_0F65_P_2  */
10686     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10687   },
10688   {
10689     /* VEX_W_0F66_P_2  */
10690     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10691   },
10692   {
10693     /* VEX_W_0F67_P_2  */
10694     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10695   },
10696   {
10697     /* VEX_W_0F68_P_2  */
10698     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10699   },
10700   {
10701     /* VEX_W_0F69_P_2  */
10702     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10703   },
10704   {
10705     /* VEX_W_0F6A_P_2  */
10706     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10707   },
10708   {
10709     /* VEX_W_0F6B_P_2  */
10710     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10711   },
10712   {
10713     /* VEX_W_0F6C_P_2  */
10714     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10715   },
10716   {
10717     /* VEX_W_0F6D_P_2  */
10718     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10719   },
10720   {
10721     /* VEX_W_0F6F_P_1  */
10722     { "vmovdqu",        { XM, EXx }, 0 },
10723   },
10724   {
10725     /* VEX_W_0F6F_P_2  */
10726     { "vmovdqa",        { XM, EXx }, 0 },
10727   },
10728   {
10729     /* VEX_W_0F70_P_1 */
10730     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10731   },
10732   {
10733     /* VEX_W_0F70_P_2 */
10734     { "vpshufd",        { XM, EXx, Ib }, 0 },
10735   },
10736   {
10737     /* VEX_W_0F70_P_3 */
10738     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10739   },
10740   {
10741     /* VEX_W_0F71_R_2_P_2  */
10742     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10743   },
10744   {
10745     /* VEX_W_0F71_R_4_P_2  */
10746     { "vpsraw",         { Vex, XS, Ib }, 0 },
10747   },
10748   {
10749     /* VEX_W_0F71_R_6_P_2  */
10750     { "vpsllw",         { Vex, XS, Ib }, 0 },
10751   },
10752   {
10753     /* VEX_W_0F72_R_2_P_2  */
10754     { "vpsrld",         { Vex, XS, Ib }, 0 },
10755   },
10756   {
10757     /* VEX_W_0F72_R_4_P_2  */
10758     { "vpsrad",         { Vex, XS, Ib }, 0 },
10759   },
10760   {
10761     /* VEX_W_0F72_R_6_P_2  */
10762     { "vpslld",         { Vex, XS, Ib }, 0 },
10763   },
10764   {
10765     /* VEX_W_0F73_R_2_P_2  */
10766     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10767   },
10768   {
10769     /* VEX_W_0F73_R_3_P_2  */
10770     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10771   },
10772   {
10773     /* VEX_W_0F73_R_6_P_2  */
10774     { "vpsllq",         { Vex, XS, Ib }, 0 },
10775   },
10776   {
10777     /* VEX_W_0F73_R_7_P_2  */
10778     { "vpslldq",        { Vex, XS, Ib }, 0 },
10779   },
10780   {
10781     /* VEX_W_0F74_P_2 */
10782     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10783   },
10784   {
10785     /* VEX_W_0F75_P_2 */
10786     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10787   },
10788   {
10789     /* VEX_W_0F76_P_2 */
10790     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10791   },
10792   {
10793     /* VEX_W_0F77_P_0 */
10794     { "",               { VZERO }, 0 },
10795   },
10796   {
10797     /* VEX_W_0F7C_P_2 */
10798     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10799   },
10800   {
10801     /* VEX_W_0F7C_P_3 */
10802     { "vhaddps",        { XM, Vex, EXx }, 0 },
10803   },
10804   {
10805     /* VEX_W_0F7D_P_2 */
10806     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10807   },
10808   {
10809     /* VEX_W_0F7D_P_3 */
10810     { "vhsubps",        { XM, Vex, EXx }, 0 },
10811   },
10812   {
10813     /* VEX_W_0F7E_P_1 */
10814     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10815   },
10816   {
10817     /* VEX_W_0F7F_P_1 */
10818     { "vmovdqu",        { EXxS, XM }, 0 },
10819   },
10820   {
10821     /* VEX_W_0F7F_P_2 */
10822     { "vmovdqa",        { EXxS, XM }, 0 },
10823   },
10824   {
10825     /* VEX_W_0F90_P_0_LEN_0 */
10826     { "kmovw",          { MaskG, MaskE }, 0 },
10827     { "kmovq",          { MaskG, MaskE }, 0 },
10828   },
10829   {
10830     /* VEX_W_0F90_P_2_LEN_0 */
10831     { "kmovb",          { MaskG, MaskBDE }, 0 },
10832     { "kmovd",          { MaskG, MaskBDE }, 0 },
10833   },
10834   {
10835     /* VEX_W_0F91_P_0_LEN_0 */
10836     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10837     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10838   },
10839   {
10840     /* VEX_W_0F91_P_2_LEN_0 */
10841     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10842     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10843   },
10844   {
10845     /* VEX_W_0F92_P_0_LEN_0 */
10846     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10847   },
10848   {
10849     /* VEX_W_0F92_P_2_LEN_0 */
10850     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10851   },
10852   {
10853     /* VEX_W_0F92_P_3_LEN_0 */
10854     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10855     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10856   },
10857   {
10858     /* VEX_W_0F93_P_0_LEN_0 */
10859     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10860   },
10861   {
10862     /* VEX_W_0F93_P_2_LEN_0 */
10863     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10864   },
10865   {
10866     /* VEX_W_0F93_P_3_LEN_0 */
10867     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10868     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10869   },
10870   {
10871     /* VEX_W_0F98_P_0_LEN_0 */
10872     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10873     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10874   },
10875   {
10876     /* VEX_W_0F98_P_2_LEN_0 */
10877     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10878     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10879   },
10880   {
10881     /* VEX_W_0F99_P_0_LEN_0 */
10882     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10883     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10884   },
10885   {
10886     /* VEX_W_0F99_P_2_LEN_0 */
10887     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10888     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10889   },
10890   {
10891     /* VEX_W_0FAE_R_2_M_0 */
10892     { "vldmxcsr",       { Md }, 0 },
10893   },
10894   {
10895     /* VEX_W_0FAE_R_3_M_0 */
10896     { "vstmxcsr",       { Md }, 0 },
10897   },
10898   {
10899     /* VEX_W_0FC2_P_0 */
10900     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10901   },
10902   {
10903     /* VEX_W_0FC2_P_1 */
10904     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10905   },
10906   {
10907     /* VEX_W_0FC2_P_2 */
10908     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10909   },
10910   {
10911     /* VEX_W_0FC2_P_3 */
10912     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10913   },
10914   {
10915     /* VEX_W_0FC4_P_2 */
10916     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10917   },
10918   {
10919     /* VEX_W_0FC5_P_2 */
10920     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10921   },
10922   {
10923     /* VEX_W_0FD0_P_2 */
10924     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10925   },
10926   {
10927     /* VEX_W_0FD0_P_3 */
10928     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10929   },
10930   {
10931     /* VEX_W_0FD1_P_2 */
10932     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10933   },
10934   {
10935     /* VEX_W_0FD2_P_2 */
10936     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10937   },
10938   {
10939     /* VEX_W_0FD3_P_2 */
10940     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10941   },
10942   {
10943     /* VEX_W_0FD4_P_2 */
10944     { "vpaddq",         { XM, Vex, EXx }, 0 },
10945   },
10946   {
10947     /* VEX_W_0FD5_P_2 */
10948     { "vpmullw",        { XM, Vex, EXx }, 0 },
10949   },
10950   {
10951     /* VEX_W_0FD6_P_2 */
10952     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10953   },
10954   {
10955     /* VEX_W_0FD7_P_2_M_1 */
10956     { "vpmovmskb",      { Gdq, XS }, 0 },
10957   },
10958   {
10959     /* VEX_W_0FD8_P_2 */
10960     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10961   },
10962   {
10963     /* VEX_W_0FD9_P_2 */
10964     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10965   },
10966   {
10967     /* VEX_W_0FDA_P_2 */
10968     { "vpminub",        { XM, Vex, EXx }, 0 },
10969   },
10970   {
10971     /* VEX_W_0FDB_P_2 */
10972     { "vpand",          { XM, Vex, EXx }, 0 },
10973   },
10974   {
10975     /* VEX_W_0FDC_P_2 */
10976     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10977   },
10978   {
10979     /* VEX_W_0FDD_P_2 */
10980     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10981   },
10982   {
10983     /* VEX_W_0FDE_P_2 */
10984     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10985   },
10986   {
10987     /* VEX_W_0FDF_P_2 */
10988     { "vpandn",         { XM, Vex, EXx }, 0 },
10989   },
10990   {
10991     /* VEX_W_0FE0_P_2  */
10992     { "vpavgb",         { XM, Vex, EXx }, 0 },
10993   },
10994   {
10995     /* VEX_W_0FE1_P_2  */
10996     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10997   },
10998   {
10999     /* VEX_W_0FE2_P_2  */
11000     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
11001   },
11002   {
11003     /* VEX_W_0FE3_P_2  */
11004     { "vpavgw",         { XM, Vex, EXx }, 0 },
11005   },
11006   {
11007     /* VEX_W_0FE4_P_2  */
11008     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
11009   },
11010   {
11011     /* VEX_W_0FE5_P_2  */
11012     { "vpmulhw",        { XM, Vex, EXx }, 0 },
11013   },
11014   {
11015     /* VEX_W_0FE6_P_1  */
11016     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
11017   },
11018   {
11019     /* VEX_W_0FE6_P_2  */
11020     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
11021   },
11022   {
11023     /* VEX_W_0FE6_P_3  */
11024     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
11025   },
11026   {
11027     /* VEX_W_0FE7_P_2_M_0 */
11028     { "vmovntdq",       { Mx, XM }, 0 },
11029   },
11030   {
11031     /* VEX_W_0FE8_P_2  */
11032     { "vpsubsb",        { XM, Vex, EXx }, 0 },
11033   },
11034   {
11035     /* VEX_W_0FE9_P_2  */
11036     { "vpsubsw",        { XM, Vex, EXx }, 0 },
11037   },
11038   {
11039     /* VEX_W_0FEA_P_2  */
11040     { "vpminsw",        { XM, Vex, EXx }, 0 },
11041   },
11042   {
11043     /* VEX_W_0FEB_P_2  */
11044     { "vpor",           { XM, Vex, EXx }, 0 },
11045   },
11046   {
11047     /* VEX_W_0FEC_P_2  */
11048     { "vpaddsb",        { XM, Vex, EXx }, 0 },
11049   },
11050   {
11051     /* VEX_W_0FED_P_2  */
11052     { "vpaddsw",        { XM, Vex, EXx }, 0 },
11053   },
11054   {
11055     /* VEX_W_0FEE_P_2  */
11056     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
11057   },
11058   {
11059     /* VEX_W_0FEF_P_2  */
11060     { "vpxor",          { XM, Vex, EXx }, 0 },
11061   },
11062   {
11063     /* VEX_W_0FF0_P_3_M_0 */
11064     { "vlddqu",         { XM, M }, 0 },
11065   },
11066   {
11067     /* VEX_W_0FF1_P_2 */
11068     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11069   },
11070   {
11071     /* VEX_W_0FF2_P_2 */
11072     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11073   },
11074   {
11075     /* VEX_W_0FF3_P_2 */
11076     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11077   },
11078   {
11079     /* VEX_W_0FF4_P_2 */
11080     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11081   },
11082   {
11083     /* VEX_W_0FF5_P_2 */
11084     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11085   },
11086   {
11087     /* VEX_W_0FF6_P_2 */
11088     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11089   },
11090   {
11091     /* VEX_W_0FF7_P_2 */
11092     { "vmaskmovdqu",    { XM, XS }, 0 },
11093   },
11094   {
11095     /* VEX_W_0FF8_P_2 */
11096     { "vpsubb",         { XM, Vex, EXx }, 0 },
11097   },
11098   {
11099     /* VEX_W_0FF9_P_2 */
11100     { "vpsubw",         { XM, Vex, EXx }, 0 },
11101   },
11102   {
11103     /* VEX_W_0FFA_P_2 */
11104     { "vpsubd",         { XM, Vex, EXx }, 0 },
11105   },
11106   {
11107     /* VEX_W_0FFB_P_2 */
11108     { "vpsubq",         { XM, Vex, EXx }, 0 },
11109   },
11110   {
11111     /* VEX_W_0FFC_P_2 */
11112     { "vpaddb",         { XM, Vex, EXx }, 0 },
11113   },
11114   {
11115     /* VEX_W_0FFD_P_2 */
11116     { "vpaddw",         { XM, Vex, EXx }, 0 },
11117   },
11118   {
11119     /* VEX_W_0FFE_P_2 */
11120     { "vpaddd",         { XM, Vex, EXx }, 0 },
11121   },
11122   {
11123     /* VEX_W_0F3800_P_2  */
11124     { "vpshufb",        { XM, Vex, EXx }, 0 },
11125   },
11126   {
11127     /* VEX_W_0F3801_P_2  */
11128     { "vphaddw",        { XM, Vex, EXx }, 0 },
11129   },
11130   {
11131     /* VEX_W_0F3802_P_2  */
11132     { "vphaddd",        { XM, Vex, EXx }, 0 },
11133   },
11134   {
11135     /* VEX_W_0F3803_P_2  */
11136     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11137   },
11138   {
11139     /* VEX_W_0F3804_P_2  */
11140     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11141   },
11142   {
11143     /* VEX_W_0F3805_P_2  */
11144     { "vphsubw",        { XM, Vex, EXx }, 0 },
11145   },
11146   {
11147     /* VEX_W_0F3806_P_2  */
11148     { "vphsubd",        { XM, Vex, EXx }, 0 },
11149   },
11150   {
11151     /* VEX_W_0F3807_P_2  */
11152     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11153   },
11154   {
11155     /* VEX_W_0F3808_P_2  */
11156     { "vpsignb",        { XM, Vex, EXx }, 0 },
11157   },
11158   {
11159     /* VEX_W_0F3809_P_2  */
11160     { "vpsignw",        { XM, Vex, EXx }, 0 },
11161   },
11162   {
11163     /* VEX_W_0F380A_P_2  */
11164     { "vpsignd",        { XM, Vex, EXx }, 0 },
11165   },
11166   {
11167     /* VEX_W_0F380B_P_2  */
11168     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11169   },
11170   {
11171     /* VEX_W_0F380C_P_2  */
11172     { "vpermilps",      { XM, Vex, EXx }, 0 },
11173   },
11174   {
11175     /* VEX_W_0F380D_P_2  */
11176     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11177   },
11178   {
11179     /* VEX_W_0F380E_P_2  */
11180     { "vtestps",        { XM, EXx }, 0 },
11181   },
11182   {
11183     /* VEX_W_0F380F_P_2  */
11184     { "vtestpd",        { XM, EXx }, 0 },
11185   },
11186   {
11187     /* VEX_W_0F3816_P_2  */
11188     { "vpermps",        { XM, Vex, EXx }, 0 },
11189   },
11190   {
11191     /* VEX_W_0F3817_P_2 */
11192     { "vptest",         { XM, EXx }, 0 },
11193   },
11194   {
11195     /* VEX_W_0F3818_P_2 */
11196     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11197   },
11198   {
11199     /* VEX_W_0F3819_P_2 */
11200     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11201   },
11202   {
11203     /* VEX_W_0F381A_P_2_M_0 */
11204     { "vbroadcastf128", { XM, Mxmm }, 0 },
11205   },
11206   {
11207     /* VEX_W_0F381C_P_2 */
11208     { "vpabsb",         { XM, EXx }, 0 },
11209   },
11210   {
11211     /* VEX_W_0F381D_P_2 */
11212     { "vpabsw",         { XM, EXx }, 0 },
11213   },
11214   {
11215     /* VEX_W_0F381E_P_2 */
11216     { "vpabsd",         { XM, EXx }, 0 },
11217   },
11218   {
11219     /* VEX_W_0F3820_P_2 */
11220     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11221   },
11222   {
11223     /* VEX_W_0F3821_P_2 */
11224     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11225   },
11226   {
11227     /* VEX_W_0F3822_P_2 */
11228     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11229   },
11230   {
11231     /* VEX_W_0F3823_P_2 */
11232     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11233   },
11234   {
11235     /* VEX_W_0F3824_P_2 */
11236     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11237   },
11238   {
11239     /* VEX_W_0F3825_P_2 */
11240     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11241   },
11242   {
11243     /* VEX_W_0F3828_P_2 */
11244     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11245   },
11246   {
11247     /* VEX_W_0F3829_P_2 */
11248     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11249   },
11250   {
11251     /* VEX_W_0F382A_P_2_M_0 */
11252     { "vmovntdqa",      { XM, Mx }, 0 },
11253   },
11254   {
11255     /* VEX_W_0F382B_P_2 */
11256     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11257   },
11258   {
11259     /* VEX_W_0F382C_P_2_M_0 */
11260     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11261   },
11262   {
11263     /* VEX_W_0F382D_P_2_M_0 */
11264     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11265   },
11266   {
11267     /* VEX_W_0F382E_P_2_M_0 */
11268     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11269   },
11270   {
11271     /* VEX_W_0F382F_P_2_M_0 */
11272     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11273   },
11274   {
11275     /* VEX_W_0F3830_P_2 */
11276     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11277   },
11278   {
11279     /* VEX_W_0F3831_P_2 */
11280     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11281   },
11282   {
11283     /* VEX_W_0F3832_P_2 */
11284     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11285   },
11286   {
11287     /* VEX_W_0F3833_P_2 */
11288     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11289   },
11290   {
11291     /* VEX_W_0F3834_P_2 */
11292     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11293   },
11294   {
11295     /* VEX_W_0F3835_P_2 */
11296     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11297   },
11298   {
11299     /* VEX_W_0F3836_P_2  */
11300     { "vpermd",         { XM, Vex, EXx }, 0 },
11301   },
11302   {
11303     /* VEX_W_0F3837_P_2 */
11304     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11305   },
11306   {
11307     /* VEX_W_0F3838_P_2 */
11308     { "vpminsb",        { XM, Vex, EXx }, 0 },
11309   },
11310   {
11311     /* VEX_W_0F3839_P_2 */
11312     { "vpminsd",        { XM, Vex, EXx }, 0 },
11313   },
11314   {
11315     /* VEX_W_0F383A_P_2 */
11316     { "vpminuw",        { XM, Vex, EXx }, 0 },
11317   },
11318   {
11319     /* VEX_W_0F383B_P_2 */
11320     { "vpminud",        { XM, Vex, EXx }, 0 },
11321   },
11322   {
11323     /* VEX_W_0F383C_P_2 */
11324     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11325   },
11326   {
11327     /* VEX_W_0F383D_P_2 */
11328     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11329   },
11330   {
11331     /* VEX_W_0F383E_P_2 */
11332     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11333   },
11334   {
11335     /* VEX_W_0F383F_P_2 */
11336     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11337   },
11338   {
11339     /* VEX_W_0F3840_P_2 */
11340     { "vpmulld",        { XM, Vex, EXx }, 0 },
11341   },
11342   {
11343     /* VEX_W_0F3841_P_2 */
11344     { "vphminposuw",    { XM, EXx }, 0 },
11345   },
11346   {
11347     /* VEX_W_0F3846_P_2 */
11348     { "vpsravd",        { XM, Vex, EXx }, 0 },
11349   },
11350   {
11351     /* VEX_W_0F3858_P_2 */
11352     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11353   },
11354   {
11355     /* VEX_W_0F3859_P_2 */
11356     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11357   },
11358   {
11359     /* VEX_W_0F385A_P_2_M_0 */
11360     { "vbroadcasti128", { XM, Mxmm }, 0 },
11361   },
11362   {
11363     /* VEX_W_0F3878_P_2 */
11364     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11365   },
11366   {
11367     /* VEX_W_0F3879_P_2 */
11368     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11369   },
11370   {
11371     /* VEX_W_0F38CF_P_2 */
11372     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
11373   },
11374   {
11375     /* VEX_W_0F38DB_P_2 */
11376     { "vaesimc",        { XM, EXx }, 0 },
11377   },
11378   {
11379     /* VEX_W_0F3A00_P_2 */
11380     { Bad_Opcode },
11381     { "vpermq",         { XM, EXx, Ib }, 0 },
11382   },
11383   {
11384     /* VEX_W_0F3A01_P_2 */
11385     { Bad_Opcode },
11386     { "vpermpd",        { XM, EXx, Ib }, 0 },
11387   },
11388   {
11389     /* VEX_W_0F3A02_P_2 */
11390     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11391   },
11392   {
11393     /* VEX_W_0F3A04_P_2 */
11394     { "vpermilps",      { XM, EXx, Ib }, 0 },
11395   },
11396   {
11397     /* VEX_W_0F3A05_P_2 */
11398     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11399   },
11400   {
11401     /* VEX_W_0F3A06_P_2 */
11402     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11403   },
11404   {
11405     /* VEX_W_0F3A08_P_2 */
11406     { "vroundps",       { XM, EXx, Ib }, 0 },
11407   },
11408   {
11409     /* VEX_W_0F3A09_P_2 */
11410     { "vroundpd",       { XM, EXx, Ib }, 0 },
11411   },
11412   {
11413     /* VEX_W_0F3A0A_P_2 */
11414     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11415   },
11416   {
11417     /* VEX_W_0F3A0B_P_2 */
11418     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11419   },
11420   {
11421     /* VEX_W_0F3A0C_P_2 */
11422     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11423   },
11424   {
11425     /* VEX_W_0F3A0D_P_2 */
11426     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11427   },
11428   {
11429     /* VEX_W_0F3A0E_P_2 */
11430     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11431   },
11432   {
11433     /* VEX_W_0F3A0F_P_2 */
11434     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11435   },
11436   {
11437     /* VEX_W_0F3A14_P_2 */
11438     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11439   },
11440   {
11441     /* VEX_W_0F3A15_P_2 */
11442     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11443   },
11444   {
11445     /* VEX_W_0F3A18_P_2 */
11446     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11447   },
11448   {
11449     /* VEX_W_0F3A19_P_2 */
11450     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11451   },
11452   {
11453     /* VEX_W_0F3A20_P_2 */
11454     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11455   },
11456   {
11457     /* VEX_W_0F3A21_P_2 */
11458     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11459   },
11460   {
11461     /* VEX_W_0F3A30_P_2_LEN_0 */
11462     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11463     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11464   },
11465   {
11466     /* VEX_W_0F3A31_P_2_LEN_0 */
11467     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11468     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11469   },
11470   {
11471     /* VEX_W_0F3A32_P_2_LEN_0 */
11472     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11473     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11474   },
11475   {
11476     /* VEX_W_0F3A33_P_2_LEN_0 */
11477     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11478     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11479   },
11480   {
11481     /* VEX_W_0F3A38_P_2 */
11482     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11483   },
11484   {
11485     /* VEX_W_0F3A39_P_2 */
11486     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11487   },
11488   {
11489     /* VEX_W_0F3A40_P_2 */
11490     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11491   },
11492   {
11493     /* VEX_W_0F3A41_P_2 */
11494     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11495   },
11496   {
11497     /* VEX_W_0F3A42_P_2 */
11498     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11499   },
11500   {
11501     /* VEX_W_0F3A46_P_2 */
11502     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11503   },
11504   {
11505     /* VEX_W_0F3A48_P_2 */
11506     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11507     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11508   },
11509   {
11510     /* VEX_W_0F3A49_P_2 */
11511     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11512     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11513   },
11514   {
11515     /* VEX_W_0F3A4A_P_2 */
11516     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11517   },
11518   {
11519     /* VEX_W_0F3A4B_P_2 */
11520     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11521   },
11522   {
11523     /* VEX_W_0F3A4C_P_2 */
11524     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11525   },
11526   {
11527     /* VEX_W_0F3A62_P_2 */
11528     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11529   },
11530   {
11531     /* VEX_W_0F3A63_P_2 */
11532     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11533   },
11534   {
11535     /* VEX_W_0F3ACE_P_2 */
11536     { Bad_Opcode },
11537     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
11538   },
11539   {
11540     /* VEX_W_0F3ACF_P_2 */
11541     { Bad_Opcode },
11542     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
11543   },
11544   {
11545     /* VEX_W_0F3ADF_P_2 */
11546     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11547   },
11548 #define NEED_VEX_W_TABLE
11549 #include "i386-dis-evex.h"
11550 #undef NEED_VEX_W_TABLE
11551 };
11552
11553 static const struct dis386 mod_table[][2] = {
11554   {
11555     /* MOD_8D */
11556     { "leaS",           { Gv, M }, 0 },
11557   },
11558   {
11559     /* MOD_C6_REG_7 */
11560     { Bad_Opcode },
11561     { RM_TABLE (RM_C6_REG_7) },
11562   },
11563   {
11564     /* MOD_C7_REG_7 */
11565     { Bad_Opcode },
11566     { RM_TABLE (RM_C7_REG_7) },
11567   },
11568   {
11569     /* MOD_FF_REG_3 */
11570     { "Jcall^", { indirEp }, 0 },
11571   },
11572   {
11573     /* MOD_FF_REG_5 */
11574     { "Jjmp^", { indirEp }, 0 },
11575   },
11576   {
11577     /* MOD_0F01_REG_0 */
11578     { X86_64_TABLE (X86_64_0F01_REG_0) },
11579     { RM_TABLE (RM_0F01_REG_0) },
11580   },
11581   {
11582     /* MOD_0F01_REG_1 */
11583     { X86_64_TABLE (X86_64_0F01_REG_1) },
11584     { RM_TABLE (RM_0F01_REG_1) },
11585   },
11586   {
11587     /* MOD_0F01_REG_2 */
11588     { X86_64_TABLE (X86_64_0F01_REG_2) },
11589     { RM_TABLE (RM_0F01_REG_2) },
11590   },
11591   {
11592     /* MOD_0F01_REG_3 */
11593     { X86_64_TABLE (X86_64_0F01_REG_3) },
11594     { RM_TABLE (RM_0F01_REG_3) },
11595   },
11596   {
11597     /* MOD_0F01_REG_5 */
11598     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11599     { RM_TABLE (RM_0F01_REG_5) },
11600   },
11601   {
11602     /* MOD_0F01_REG_7 */
11603     { "invlpg",         { Mb }, 0 },
11604     { RM_TABLE (RM_0F01_REG_7) },
11605   },
11606   {
11607     /* MOD_0F12_PREFIX_0 */
11608     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11609     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11610   },
11611   {
11612     /* MOD_0F13 */
11613     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11614   },
11615   {
11616     /* MOD_0F16_PREFIX_0 */
11617     { "movhps",         { XM, EXq }, 0 },
11618     { "movlhps",        { XM, EXq }, 0 },
11619   },
11620   {
11621     /* MOD_0F17 */
11622     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11623   },
11624   {
11625     /* MOD_0F18_REG_0 */
11626     { "prefetchnta",    { Mb }, 0 },
11627   },
11628   {
11629     /* MOD_0F18_REG_1 */
11630     { "prefetcht0",     { Mb }, 0 },
11631   },
11632   {
11633     /* MOD_0F18_REG_2 */
11634     { "prefetcht1",     { Mb }, 0 },
11635   },
11636   {
11637     /* MOD_0F18_REG_3 */
11638     { "prefetcht2",     { Mb }, 0 },
11639   },
11640   {
11641     /* MOD_0F18_REG_4 */
11642     { "nop/reserved",   { Mb }, 0 },
11643   },
11644   {
11645     /* MOD_0F18_REG_5 */
11646     { "nop/reserved",   { Mb }, 0 },
11647   },
11648   {
11649     /* MOD_0F18_REG_6 */
11650     { "nop/reserved",   { Mb }, 0 },
11651   },
11652   {
11653     /* MOD_0F18_REG_7 */
11654     { "nop/reserved",   { Mb }, 0 },
11655   },
11656   {
11657     /* MOD_0F1A_PREFIX_0 */
11658     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
11659     { "nopQ",           { Ev }, 0 },
11660   },
11661   {
11662     /* MOD_0F1B_PREFIX_0 */
11663     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
11664     { "nopQ",           { Ev }, 0 },
11665   },
11666   {
11667     /* MOD_0F1B_PREFIX_1 */
11668     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
11669     { "nopQ",           { Ev }, 0 },
11670   },
11671   {
11672     /* MOD_0F1C_PREFIX_0 */
11673     { REG_TABLE (REG_0F1C_MOD_0) },
11674     { "nopQ",           { Ev }, 0 },
11675   },
11676   {
11677     /* MOD_0F1E_PREFIX_1 */
11678     { "nopQ",           { Ev }, 0 },
11679     { REG_TABLE (REG_0F1E_MOD_3) },
11680   },
11681   {
11682     /* MOD_0F24 */
11683     { Bad_Opcode },
11684     { "movL",           { Rd, Td }, 0 },
11685   },
11686   {
11687     /* MOD_0F26 */
11688     { Bad_Opcode },
11689     { "movL",           { Td, Rd }, 0 },
11690   },
11691   {
11692     /* MOD_0F2B_PREFIX_0 */
11693     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11694   },
11695   {
11696     /* MOD_0F2B_PREFIX_1 */
11697     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11698   },
11699   {
11700     /* MOD_0F2B_PREFIX_2 */
11701     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11702   },
11703   {
11704     /* MOD_0F2B_PREFIX_3 */
11705     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11706   },
11707   {
11708     /* MOD_0F51 */
11709     { Bad_Opcode },
11710     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11711   },
11712   {
11713     /* MOD_0F71_REG_2 */
11714     { Bad_Opcode },
11715     { "psrlw",          { MS, Ib }, 0 },
11716   },
11717   {
11718     /* MOD_0F71_REG_4 */
11719     { Bad_Opcode },
11720     { "psraw",          { MS, Ib }, 0 },
11721   },
11722   {
11723     /* MOD_0F71_REG_6 */
11724     { Bad_Opcode },
11725     { "psllw",          { MS, Ib }, 0 },
11726   },
11727   {
11728     /* MOD_0F72_REG_2 */
11729     { Bad_Opcode },
11730     { "psrld",          { MS, Ib }, 0 },
11731   },
11732   {
11733     /* MOD_0F72_REG_4 */
11734     { Bad_Opcode },
11735     { "psrad",          { MS, Ib }, 0 },
11736   },
11737   {
11738     /* MOD_0F72_REG_6 */
11739     { Bad_Opcode },
11740     { "pslld",          { MS, Ib }, 0 },
11741   },
11742   {
11743     /* MOD_0F73_REG_2 */
11744     { Bad_Opcode },
11745     { "psrlq",          { MS, Ib }, 0 },
11746   },
11747   {
11748     /* MOD_0F73_REG_3 */
11749     { Bad_Opcode },
11750     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11751   },
11752   {
11753     /* MOD_0F73_REG_6 */
11754     { Bad_Opcode },
11755     { "psllq",          { MS, Ib }, 0 },
11756   },
11757   {
11758     /* MOD_0F73_REG_7 */
11759     { Bad_Opcode },
11760     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11761   },
11762   {
11763     /* MOD_0FAE_REG_0 */
11764     { "fxsave",         { FXSAVE }, 0 },
11765     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11766   },
11767   {
11768     /* MOD_0FAE_REG_1 */
11769     { "fxrstor",        { FXSAVE }, 0 },
11770     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11771   },
11772   {
11773     /* MOD_0FAE_REG_2 */
11774     { "ldmxcsr",        { Md }, 0 },
11775     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11776   },
11777   {
11778     /* MOD_0FAE_REG_3 */
11779     { "stmxcsr",        { Md }, 0 },
11780     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11781   },
11782   {
11783     /* MOD_0FAE_REG_4 */
11784     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11785     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11786   },
11787   {
11788     /* MOD_0FAE_REG_5 */
11789     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11790     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11791   },
11792   {
11793     /* MOD_0FAE_REG_6 */
11794     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
11795     { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
11796   },
11797   {
11798     /* MOD_0FAE_REG_7 */
11799     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11800     { RM_TABLE (RM_0FAE_REG_7) },
11801   },
11802   {
11803     /* MOD_0FB2 */
11804     { "lssS",           { Gv, Mp }, 0 },
11805   },
11806   {
11807     /* MOD_0FB4 */
11808     { "lfsS",           { Gv, Mp }, 0 },
11809   },
11810   {
11811     /* MOD_0FB5 */
11812     { "lgsS",           { Gv, Mp }, 0 },
11813   },
11814   {
11815     /* MOD_0FC3 */
11816     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11817   },
11818   {
11819     /* MOD_0FC7_REG_3 */
11820     { "xrstors",        { FXSAVE }, 0 },
11821   },
11822   {
11823     /* MOD_0FC7_REG_4 */
11824     { "xsavec",         { FXSAVE }, 0 },
11825   },
11826   {
11827     /* MOD_0FC7_REG_5 */
11828     { "xsaves",         { FXSAVE }, 0 },
11829   },
11830   {
11831     /* MOD_0FC7_REG_6 */
11832     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11833     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11834   },
11835   {
11836     /* MOD_0FC7_REG_7 */
11837     { "vmptrst",        { Mq }, 0 },
11838     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11839   },
11840   {
11841     /* MOD_0FD7 */
11842     { Bad_Opcode },
11843     { "pmovmskb",       { Gdq, MS }, 0 },
11844   },
11845   {
11846     /* MOD_0FE7_PREFIX_2 */
11847     { "movntdq",        { Mx, XM }, 0 },
11848   },
11849   {
11850     /* MOD_0FF0_PREFIX_3 */
11851     { "lddqu",          { XM, M }, 0 },
11852   },
11853   {
11854     /* MOD_0F382A_PREFIX_2 */
11855     { "movntdqa",       { XM, Mx }, 0 },
11856   },
11857   {
11858     /* MOD_0F38F5_PREFIX_2 */
11859     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11860   },
11861   {
11862     /* MOD_0F38F6_PREFIX_0 */
11863     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11864   },
11865   {
11866     /* MOD_0F38F8_PREFIX_2 */
11867     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
11868   },
11869   {
11870     /* MOD_0F38F9_PREFIX_0 */
11871     { "movdiri",        { Em, Gv }, PREFIX_OPCODE },
11872   },
11873   {
11874     /* MOD_62_32BIT */
11875     { "bound{S|}",      { Gv, Ma }, 0 },
11876     { EVEX_TABLE (EVEX_0F) },
11877   },
11878   {
11879     /* MOD_C4_32BIT */
11880     { "lesS",           { Gv, Mp }, 0 },
11881     { VEX_C4_TABLE (VEX_0F) },
11882   },
11883   {
11884     /* MOD_C5_32BIT */
11885     { "ldsS",           { Gv, Mp }, 0 },
11886     { VEX_C5_TABLE (VEX_0F) },
11887   },
11888   {
11889     /* MOD_VEX_0F12_PREFIX_0 */
11890     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11891     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11892   },
11893   {
11894     /* MOD_VEX_0F13 */
11895     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11896   },
11897   {
11898     /* MOD_VEX_0F16_PREFIX_0 */
11899     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11900     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11901   },
11902   {
11903     /* MOD_VEX_0F17 */
11904     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11905   },
11906   {
11907     /* MOD_VEX_0F2B */
11908     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11909   },
11910   {
11911     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11912     { Bad_Opcode },
11913     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11914   },
11915   {
11916     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11917     { Bad_Opcode },
11918     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11919   },
11920   {
11921     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11922     { Bad_Opcode },
11923     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11924   },
11925   {
11926     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11927     { Bad_Opcode },
11928     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11929   },
11930   {
11931     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11932     { Bad_Opcode },
11933     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11934   },
11935   {
11936     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11937     { Bad_Opcode },
11938     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11939   },
11940   {
11941     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11942     { Bad_Opcode },
11943     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11944   },
11945   {
11946     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11947     { Bad_Opcode },
11948     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11949   },
11950   {
11951     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11952     { Bad_Opcode },
11953     { "knotw",          { MaskG, MaskR }, 0 },
11954   },
11955   {
11956     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11957     { Bad_Opcode },
11958     { "knotq",          { MaskG, MaskR }, 0 },
11959   },
11960   {
11961     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11962     { Bad_Opcode },
11963     { "knotb",          { MaskG, MaskR }, 0 },
11964   },
11965   {
11966     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11967     { Bad_Opcode },
11968     { "knotd",          { MaskG, MaskR }, 0 },
11969   },
11970   {
11971     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11972     { Bad_Opcode },
11973     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11974   },
11975   {
11976     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11977     { Bad_Opcode },
11978     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11979   },
11980   {
11981     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11982     { Bad_Opcode },
11983     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11984   },
11985   {
11986     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11987     { Bad_Opcode },
11988     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11989   },
11990  {
11991     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11992     { Bad_Opcode },
11993     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11994   },
11995   {
11996     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11997     { Bad_Opcode },
11998     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11999   },
12000   {
12001     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
12002     { Bad_Opcode },
12003     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
12004   },
12005   {
12006     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
12007     { Bad_Opcode },
12008     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
12009   },
12010   {
12011     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12012     { Bad_Opcode },
12013     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
12014   },
12015   {
12016     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12017     { Bad_Opcode },
12018     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
12019   },
12020   {
12021     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12022     { Bad_Opcode },
12023     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
12024   },
12025   {
12026     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12027     { Bad_Opcode },
12028     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
12029   },
12030   {
12031     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12032     { Bad_Opcode },
12033     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
12034   },
12035   {
12036     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12037     { Bad_Opcode },
12038     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
12039   },
12040   {
12041     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12042     { Bad_Opcode },
12043     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
12044   },
12045   {
12046     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12047     { Bad_Opcode },
12048     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
12049   },
12050   {
12051     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12052     { Bad_Opcode },
12053     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
12054   },
12055   {
12056     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12057     { Bad_Opcode },
12058     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
12059   },
12060   {
12061     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12062     { Bad_Opcode },
12063     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
12064   },
12065   {
12066     /* MOD_VEX_0F50 */
12067     { Bad_Opcode },
12068     { VEX_W_TABLE (VEX_W_0F50_M_0) },
12069   },
12070   {
12071     /* MOD_VEX_0F71_REG_2 */
12072     { Bad_Opcode },
12073     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
12074   },
12075   {
12076     /* MOD_VEX_0F71_REG_4 */
12077     { Bad_Opcode },
12078     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12079   },
12080   {
12081     /* MOD_VEX_0F71_REG_6 */
12082     { Bad_Opcode },
12083     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12084   },
12085   {
12086     /* MOD_VEX_0F72_REG_2 */
12087     { Bad_Opcode },
12088     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12089   },
12090   {
12091     /* MOD_VEX_0F72_REG_4 */
12092     { Bad_Opcode },
12093     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12094   },
12095   {
12096     /* MOD_VEX_0F72_REG_6 */
12097     { Bad_Opcode },
12098     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12099   },
12100   {
12101     /* MOD_VEX_0F73_REG_2 */
12102     { Bad_Opcode },
12103     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12104   },
12105   {
12106     /* MOD_VEX_0F73_REG_3 */
12107     { Bad_Opcode },
12108     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12109   },
12110   {
12111     /* MOD_VEX_0F73_REG_6 */
12112     { Bad_Opcode },
12113     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12114   },
12115   {
12116     /* MOD_VEX_0F73_REG_7 */
12117     { Bad_Opcode },
12118     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12119   },
12120   {
12121     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12122     { "kmovw",          { Ew, MaskG }, 0 },
12123     { Bad_Opcode },
12124   },
12125   {
12126     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12127     { "kmovq",          { Eq, MaskG }, 0 },
12128     { Bad_Opcode },
12129   },
12130   {
12131     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12132     { "kmovb",          { Eb, MaskG }, 0 },
12133     { Bad_Opcode },
12134   },
12135   {
12136     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12137     { "kmovd",          { Ed, MaskG }, 0 },
12138     { Bad_Opcode },
12139   },
12140   {
12141     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12142     { Bad_Opcode },
12143     { "kmovw",          { MaskG, Rdq }, 0 },
12144   },
12145   {
12146     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12147     { Bad_Opcode },
12148     { "kmovb",          { MaskG, Rdq }, 0 },
12149   },
12150   {
12151     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12152     { Bad_Opcode },
12153     { "kmovd",          { MaskG, Rdq }, 0 },
12154   },
12155   {
12156     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12157     { Bad_Opcode },
12158     { "kmovq",          { MaskG, Rdq }, 0 },
12159   },
12160   {
12161     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12162     { Bad_Opcode },
12163     { "kmovw",          { Gdq, MaskR }, 0 },
12164   },
12165   {
12166     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12167     { Bad_Opcode },
12168     { "kmovb",          { Gdq, MaskR }, 0 },
12169   },
12170   {
12171     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12172     { Bad_Opcode },
12173     { "kmovd",          { Gdq, MaskR }, 0 },
12174   },
12175   {
12176     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12177     { Bad_Opcode },
12178     { "kmovq",          { Gdq, MaskR }, 0 },
12179   },
12180   {
12181     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12182     { Bad_Opcode },
12183     { "kortestw", { MaskG, MaskR }, 0 },
12184   },
12185   {
12186     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12187     { Bad_Opcode },
12188     { "kortestq", { MaskG, MaskR }, 0 },
12189   },
12190   {
12191     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12192     { Bad_Opcode },
12193     { "kortestb", { MaskG, MaskR }, 0 },
12194   },
12195   {
12196     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12197     { Bad_Opcode },
12198     { "kortestd", { MaskG, MaskR }, 0 },
12199   },
12200   {
12201     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12202     { Bad_Opcode },
12203     { "ktestw", { MaskG, MaskR }, 0 },
12204   },
12205   {
12206     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12207     { Bad_Opcode },
12208     { "ktestq", { MaskG, MaskR }, 0 },
12209   },
12210   {
12211     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12212     { Bad_Opcode },
12213     { "ktestb", { MaskG, MaskR }, 0 },
12214   },
12215   {
12216     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12217     { Bad_Opcode },
12218     { "ktestd", { MaskG, MaskR }, 0 },
12219   },
12220   {
12221     /* MOD_VEX_0FAE_REG_2 */
12222     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12223   },
12224   {
12225     /* MOD_VEX_0FAE_REG_3 */
12226     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12227   },
12228   {
12229     /* MOD_VEX_0FD7_PREFIX_2 */
12230     { Bad_Opcode },
12231     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12232   },
12233   {
12234     /* MOD_VEX_0FE7_PREFIX_2 */
12235     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12236   },
12237   {
12238     /* MOD_VEX_0FF0_PREFIX_3 */
12239     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12240   },
12241   {
12242     /* MOD_VEX_0F381A_PREFIX_2 */
12243     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12244   },
12245   {
12246     /* MOD_VEX_0F382A_PREFIX_2 */
12247     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12248   },
12249   {
12250     /* MOD_VEX_0F382C_PREFIX_2 */
12251     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12252   },
12253   {
12254     /* MOD_VEX_0F382D_PREFIX_2 */
12255     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12256   },
12257   {
12258     /* MOD_VEX_0F382E_PREFIX_2 */
12259     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12260   },
12261   {
12262     /* MOD_VEX_0F382F_PREFIX_2 */
12263     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12264   },
12265   {
12266     /* MOD_VEX_0F385A_PREFIX_2 */
12267     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12268   },
12269   {
12270     /* MOD_VEX_0F388C_PREFIX_2 */
12271     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12272   },
12273   {
12274     /* MOD_VEX_0F388E_PREFIX_2 */
12275     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12276   },
12277   {
12278     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12279     { Bad_Opcode },
12280     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12281   },
12282   {
12283     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12284     { Bad_Opcode },
12285     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12286   },
12287   {
12288     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12289     { Bad_Opcode },
12290     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12291   },
12292   {
12293     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12294     { Bad_Opcode },
12295     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12296   },
12297   {
12298     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12299     { Bad_Opcode },
12300     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12301   },
12302   {
12303     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12304     { Bad_Opcode },
12305     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12306   },
12307   {
12308     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12309     { Bad_Opcode },
12310     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12311   },
12312   {
12313     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12314     { Bad_Opcode },
12315     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12316   },
12317 #define NEED_MOD_TABLE
12318 #include "i386-dis-evex.h"
12319 #undef NEED_MOD_TABLE
12320 };
12321
12322 static const struct dis386 rm_table[][8] = {
12323   {
12324     /* RM_C6_REG_7 */
12325     { "xabort",         { Skip_MODRM, Ib }, 0 },
12326   },
12327   {
12328     /* RM_C7_REG_7 */
12329     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12330   },
12331   {
12332     /* RM_0F01_REG_0 */
12333     { Bad_Opcode },
12334     { "vmcall",         { Skip_MODRM }, 0 },
12335     { "vmlaunch",       { Skip_MODRM }, 0 },
12336     { "vmresume",       { Skip_MODRM }, 0 },
12337     { "vmxoff",         { Skip_MODRM }, 0 },
12338     { "pconfig",        { Skip_MODRM }, 0 },
12339   },
12340   {
12341     /* RM_0F01_REG_1 */
12342     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12343     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12344     { "clac",           { Skip_MODRM }, 0 },
12345     { "stac",           { Skip_MODRM }, 0 },
12346     { Bad_Opcode },
12347     { Bad_Opcode },
12348     { Bad_Opcode },
12349     { "encls",          { Skip_MODRM }, 0 },
12350   },
12351   {
12352     /* RM_0F01_REG_2 */
12353     { "xgetbv",         { Skip_MODRM }, 0 },
12354     { "xsetbv",         { Skip_MODRM }, 0 },
12355     { Bad_Opcode },
12356     { Bad_Opcode },
12357     { "vmfunc",         { Skip_MODRM }, 0 },
12358     { "xend",           { Skip_MODRM }, 0 },
12359     { "xtest",          { Skip_MODRM }, 0 },
12360     { "enclu",          { Skip_MODRM }, 0 },
12361   },
12362   {
12363     /* RM_0F01_REG_3 */
12364     { "vmrun",          { Skip_MODRM }, 0 },
12365     { "vmmcall",        { Skip_MODRM }, 0 },
12366     { "vmload",         { Skip_MODRM }, 0 },
12367     { "vmsave",         { Skip_MODRM }, 0 },
12368     { "stgi",           { Skip_MODRM }, 0 },
12369     { "clgi",           { Skip_MODRM }, 0 },
12370     { "skinit",         { Skip_MODRM }, 0 },
12371     { "invlpga",        { Skip_MODRM }, 0 },
12372   },
12373   {
12374     /* RM_0F01_REG_5 */
12375     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12376     { Bad_Opcode },
12377     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12378     { Bad_Opcode },
12379     { Bad_Opcode },
12380     { Bad_Opcode },
12381     { "rdpkru",         { Skip_MODRM }, 0 },
12382     { "wrpkru",         { Skip_MODRM }, 0 },
12383   },
12384   {
12385     /* RM_0F01_REG_7 */
12386     { "swapgs",         { Skip_MODRM }, 0  },
12387     { "rdtscp",         { Skip_MODRM }, 0  },
12388     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12389     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12390     { "clzero",         { Skip_MODRM }, 0  },
12391   },
12392   {
12393     /* RM_0F1E_MOD_3_REG_7 */
12394     { "nopQ",           { Ev }, 0 },
12395     { "nopQ",           { Ev }, 0 },
12396     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
12397     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
12398     { "nopQ",           { Ev }, 0 },
12399     { "nopQ",           { Ev }, 0 },
12400     { "nopQ",           { Ev }, 0 },
12401     { "nopQ",           { Ev }, 0 },
12402   },
12403   {
12404     /* RM_0FAE_REG_6 */
12405     { "mfence",         { Skip_MODRM }, 0 },
12406   },
12407   {
12408     /* RM_0FAE_REG_7 */
12409     { "sfence",         { Skip_MODRM }, 0 },
12410
12411   },
12412 };
12413
12414 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12415
12416 /* We use the high bit to indicate different name for the same
12417    prefix.  */
12418 #define REP_PREFIX      (0xf3 | 0x100)
12419 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12420 #define XRELEASE_PREFIX (0xf3 | 0x400)
12421 #define BND_PREFIX      (0xf2 | 0x400)
12422 #define NOTRACK_PREFIX  (0x3e | 0x100)
12423
12424 static int
12425 ckprefix (void)
12426 {
12427   int newrex, i, length;
12428   rex = 0;
12429   rex_ignored = 0;
12430   prefixes = 0;
12431   used_prefixes = 0;
12432   rex_used = 0;
12433   last_lock_prefix = -1;
12434   last_repz_prefix = -1;
12435   last_repnz_prefix = -1;
12436   last_data_prefix = -1;
12437   last_addr_prefix = -1;
12438   last_rex_prefix = -1;
12439   last_seg_prefix = -1;
12440   fwait_prefix = -1;
12441   active_seg_prefix = 0;
12442   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12443     all_prefixes[i] = 0;
12444   i = 0;
12445   length = 0;
12446   /* The maximum instruction length is 15bytes.  */
12447   while (length < MAX_CODE_LENGTH - 1)
12448     {
12449       FETCH_DATA (the_info, codep + 1);
12450       newrex = 0;
12451       switch (*codep)
12452         {
12453         /* REX prefixes family.  */
12454         case 0x40:
12455         case 0x41:
12456         case 0x42:
12457         case 0x43:
12458         case 0x44:
12459         case 0x45:
12460         case 0x46:
12461         case 0x47:
12462         case 0x48:
12463         case 0x49:
12464         case 0x4a:
12465         case 0x4b:
12466         case 0x4c:
12467         case 0x4d:
12468         case 0x4e:
12469         case 0x4f:
12470           if (address_mode == mode_64bit)
12471             newrex = *codep;
12472           else
12473             return 1;
12474           last_rex_prefix = i;
12475           break;
12476         case 0xf3:
12477           prefixes |= PREFIX_REPZ;
12478           last_repz_prefix = i;
12479           break;
12480         case 0xf2:
12481           prefixes |= PREFIX_REPNZ;
12482           last_repnz_prefix = i;
12483           break;
12484         case 0xf0:
12485           prefixes |= PREFIX_LOCK;
12486           last_lock_prefix = i;
12487           break;
12488         case 0x2e:
12489           prefixes |= PREFIX_CS;
12490           last_seg_prefix = i;
12491           active_seg_prefix = PREFIX_CS;
12492           break;
12493         case 0x36:
12494           prefixes |= PREFIX_SS;
12495           last_seg_prefix = i;
12496           active_seg_prefix = PREFIX_SS;
12497           break;
12498         case 0x3e:
12499           prefixes |= PREFIX_DS;
12500           last_seg_prefix = i;
12501           active_seg_prefix = PREFIX_DS;
12502           break;
12503         case 0x26:
12504           prefixes |= PREFIX_ES;
12505           last_seg_prefix = i;
12506           active_seg_prefix = PREFIX_ES;
12507           break;
12508         case 0x64:
12509           prefixes |= PREFIX_FS;
12510           last_seg_prefix = i;
12511           active_seg_prefix = PREFIX_FS;
12512           break;
12513         case 0x65:
12514           prefixes |= PREFIX_GS;
12515           last_seg_prefix = i;
12516           active_seg_prefix = PREFIX_GS;
12517           break;
12518         case 0x66:
12519           prefixes |= PREFIX_DATA;
12520           last_data_prefix = i;
12521           break;
12522         case 0x67:
12523           prefixes |= PREFIX_ADDR;
12524           last_addr_prefix = i;
12525           break;
12526         case FWAIT_OPCODE:
12527           /* fwait is really an instruction.  If there are prefixes
12528              before the fwait, they belong to the fwait, *not* to the
12529              following instruction.  */
12530           fwait_prefix = i;
12531           if (prefixes || rex)
12532             {
12533               prefixes |= PREFIX_FWAIT;
12534               codep++;
12535               /* This ensures that the previous REX prefixes are noticed
12536                  as unused prefixes, as in the return case below.  */
12537               rex_used = rex;
12538               return 1;
12539             }
12540           prefixes = PREFIX_FWAIT;
12541           break;
12542         default:
12543           return 1;
12544         }
12545       /* Rex is ignored when followed by another prefix.  */
12546       if (rex)
12547         {
12548           rex_used = rex;
12549           return 1;
12550         }
12551       if (*codep != FWAIT_OPCODE)
12552         all_prefixes[i++] = *codep;
12553       rex = newrex;
12554       codep++;
12555       length++;
12556     }
12557   return 0;
12558 }
12559
12560 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12561    prefix byte.  */
12562
12563 static const char *
12564 prefix_name (int pref, int sizeflag)
12565 {
12566   static const char *rexes [16] =
12567     {
12568       "rex",            /* 0x40 */
12569       "rex.B",          /* 0x41 */
12570       "rex.X",          /* 0x42 */
12571       "rex.XB",         /* 0x43 */
12572       "rex.R",          /* 0x44 */
12573       "rex.RB",         /* 0x45 */
12574       "rex.RX",         /* 0x46 */
12575       "rex.RXB",        /* 0x47 */
12576       "rex.W",          /* 0x48 */
12577       "rex.WB",         /* 0x49 */
12578       "rex.WX",         /* 0x4a */
12579       "rex.WXB",        /* 0x4b */
12580       "rex.WR",         /* 0x4c */
12581       "rex.WRB",        /* 0x4d */
12582       "rex.WRX",        /* 0x4e */
12583       "rex.WRXB",       /* 0x4f */
12584     };
12585
12586   switch (pref)
12587     {
12588     /* REX prefixes family.  */
12589     case 0x40:
12590     case 0x41:
12591     case 0x42:
12592     case 0x43:
12593     case 0x44:
12594     case 0x45:
12595     case 0x46:
12596     case 0x47:
12597     case 0x48:
12598     case 0x49:
12599     case 0x4a:
12600     case 0x4b:
12601     case 0x4c:
12602     case 0x4d:
12603     case 0x4e:
12604     case 0x4f:
12605       return rexes [pref - 0x40];
12606     case 0xf3:
12607       return "repz";
12608     case 0xf2:
12609       return "repnz";
12610     case 0xf0:
12611       return "lock";
12612     case 0x2e:
12613       return "cs";
12614     case 0x36:
12615       return "ss";
12616     case 0x3e:
12617       return "ds";
12618     case 0x26:
12619       return "es";
12620     case 0x64:
12621       return "fs";
12622     case 0x65:
12623       return "gs";
12624     case 0x66:
12625       return (sizeflag & DFLAG) ? "data16" : "data32";
12626     case 0x67:
12627       if (address_mode == mode_64bit)
12628         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12629       else
12630         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12631     case FWAIT_OPCODE:
12632       return "fwait";
12633     case REP_PREFIX:
12634       return "rep";
12635     case XACQUIRE_PREFIX:
12636       return "xacquire";
12637     case XRELEASE_PREFIX:
12638       return "xrelease";
12639     case BND_PREFIX:
12640       return "bnd";
12641     case NOTRACK_PREFIX:
12642       return "notrack";
12643     default:
12644       return NULL;
12645     }
12646 }
12647
12648 static char op_out[MAX_OPERANDS][100];
12649 static int op_ad, op_index[MAX_OPERANDS];
12650 static int two_source_ops;
12651 static bfd_vma op_address[MAX_OPERANDS];
12652 static bfd_vma op_riprel[MAX_OPERANDS];
12653 static bfd_vma start_pc;
12654
12655 /*
12656  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12657  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12658  *   section of the "Virtual 8086 Mode" chapter.)
12659  * 'pc' should be the address of this instruction, it will
12660  *   be used to print the target address if this is a relative jump or call
12661  * The function returns the length of this instruction in bytes.
12662  */
12663
12664 static char intel_syntax;
12665 static char intel_mnemonic = !SYSV386_COMPAT;
12666 static char open_char;
12667 static char close_char;
12668 static char separator_char;
12669 static char scale_char;
12670
12671 enum x86_64_isa
12672 {
12673   amd64 = 0,
12674   intel64
12675 };
12676
12677 static enum x86_64_isa isa64;
12678
12679 /* Here for backwards compatibility.  When gdb stops using
12680    print_insn_i386_att and print_insn_i386_intel these functions can
12681    disappear, and print_insn_i386 be merged into print_insn.  */
12682 int
12683 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12684 {
12685   intel_syntax = 0;
12686
12687   return print_insn (pc, info);
12688 }
12689
12690 int
12691 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12692 {
12693   intel_syntax = 1;
12694
12695   return print_insn (pc, info);
12696 }
12697
12698 int
12699 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12700 {
12701   intel_syntax = -1;
12702
12703   return print_insn (pc, info);
12704 }
12705
12706 void
12707 print_i386_disassembler_options (FILE *stream)
12708 {
12709   fprintf (stream, _("\n\
12710 The following i386/x86-64 specific disassembler options are supported for use\n\
12711 with the -M switch (multiple options should be separated by commas):\n"));
12712
12713   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12714   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12715   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12716   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12717   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12718   fprintf (stream, _("  att-mnemonic\n"
12719                      "              Display instruction in AT&T mnemonic\n"));
12720   fprintf (stream, _("  intel-mnemonic\n"
12721                      "              Display instruction in Intel mnemonic\n"));
12722   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12723   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12724   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12725   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12726   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12727   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12728   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12729   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12730 }
12731
12732 /* Bad opcode.  */
12733 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12734
12735 /* Get a pointer to struct dis386 with a valid name.  */
12736
12737 static const struct dis386 *
12738 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12739 {
12740   int vindex, vex_table_index;
12741
12742   if (dp->name != NULL)
12743     return dp;
12744
12745   switch (dp->op[0].bytemode)
12746     {
12747     case USE_REG_TABLE:
12748       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12749       break;
12750
12751     case USE_MOD_TABLE:
12752       vindex = modrm.mod == 0x3 ? 1 : 0;
12753       dp = &mod_table[dp->op[1].bytemode][vindex];
12754       break;
12755
12756     case USE_RM_TABLE:
12757       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12758       break;
12759
12760     case USE_PREFIX_TABLE:
12761       if (need_vex)
12762         {
12763           /* The prefix in VEX is implicit.  */
12764           switch (vex.prefix)
12765             {
12766             case 0:
12767               vindex = 0;
12768               break;
12769             case REPE_PREFIX_OPCODE:
12770               vindex = 1;
12771               break;
12772             case DATA_PREFIX_OPCODE:
12773               vindex = 2;
12774               break;
12775             case REPNE_PREFIX_OPCODE:
12776               vindex = 3;
12777               break;
12778             default:
12779               abort ();
12780               break;
12781             }
12782         }
12783       else
12784         {
12785           int last_prefix = -1;
12786           int prefix = 0;
12787           vindex = 0;
12788           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12789              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12790              last one wins.  */
12791           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12792             {
12793               if (last_repz_prefix > last_repnz_prefix)
12794                 {
12795                   vindex = 1;
12796                   prefix = PREFIX_REPZ;
12797                   last_prefix = last_repz_prefix;
12798                 }
12799               else
12800                 {
12801                   vindex = 3;
12802                   prefix = PREFIX_REPNZ;
12803                   last_prefix = last_repnz_prefix;
12804                 }
12805
12806               /* Check if prefix should be ignored.  */
12807               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12808                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12809                    & prefix) != 0)
12810                 vindex = 0;
12811             }
12812
12813           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12814             {
12815               vindex = 2;
12816               prefix = PREFIX_DATA;
12817               last_prefix = last_data_prefix;
12818             }
12819
12820           if (vindex != 0)
12821             {
12822               used_prefixes |= prefix;
12823               all_prefixes[last_prefix] = 0;
12824             }
12825         }
12826       dp = &prefix_table[dp->op[1].bytemode][vindex];
12827       break;
12828
12829     case USE_X86_64_TABLE:
12830       vindex = address_mode == mode_64bit ? 1 : 0;
12831       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12832       break;
12833
12834     case USE_3BYTE_TABLE:
12835       FETCH_DATA (info, codep + 2);
12836       vindex = *codep++;
12837       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12838       end_codep = codep;
12839       modrm.mod = (*codep >> 6) & 3;
12840       modrm.reg = (*codep >> 3) & 7;
12841       modrm.rm = *codep & 7;
12842       break;
12843
12844     case USE_VEX_LEN_TABLE:
12845       if (!need_vex)
12846         abort ();
12847
12848       switch (vex.length)
12849         {
12850         case 128:
12851           vindex = 0;
12852           break;
12853         case 256:
12854           vindex = 1;
12855           break;
12856         default:
12857           abort ();
12858           break;
12859         }
12860
12861       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12862       break;
12863
12864     case USE_XOP_8F_TABLE:
12865       FETCH_DATA (info, codep + 3);
12866       /* All bits in the REX prefix are ignored.  */
12867       rex_ignored = rex;
12868       rex = ~(*codep >> 5) & 0x7;
12869
12870       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12871       switch ((*codep & 0x1f))
12872         {
12873         default:
12874           dp = &bad_opcode;
12875           return dp;
12876         case 0x8:
12877           vex_table_index = XOP_08;
12878           break;
12879         case 0x9:
12880           vex_table_index = XOP_09;
12881           break;
12882         case 0xa:
12883           vex_table_index = XOP_0A;
12884           break;
12885         }
12886       codep++;
12887       vex.w = *codep & 0x80;
12888       if (vex.w && address_mode == mode_64bit)
12889         rex |= REX_W;
12890
12891       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12892       if (address_mode != mode_64bit)
12893         {
12894           /* In 16/32-bit mode REX_B is silently ignored.  */
12895           rex &= ~REX_B;
12896         }
12897
12898       vex.length = (*codep & 0x4) ? 256 : 128;
12899       switch ((*codep & 0x3))
12900         {
12901         case 0:
12902           break;
12903         case 1:
12904           vex.prefix = DATA_PREFIX_OPCODE;
12905           break;
12906         case 2:
12907           vex.prefix = REPE_PREFIX_OPCODE;
12908           break;
12909         case 3:
12910           vex.prefix = REPNE_PREFIX_OPCODE;
12911           break;
12912         }
12913       need_vex = 1;
12914       need_vex_reg = 1;
12915       codep++;
12916       vindex = *codep++;
12917       dp = &xop_table[vex_table_index][vindex];
12918
12919       end_codep = codep;
12920       FETCH_DATA (info, codep + 1);
12921       modrm.mod = (*codep >> 6) & 3;
12922       modrm.reg = (*codep >> 3) & 7;
12923       modrm.rm = *codep & 7;
12924       break;
12925
12926     case USE_VEX_C4_TABLE:
12927       /* VEX prefix.  */
12928       FETCH_DATA (info, codep + 3);
12929       /* All bits in the REX prefix are ignored.  */
12930       rex_ignored = rex;
12931       rex = ~(*codep >> 5) & 0x7;
12932       switch ((*codep & 0x1f))
12933         {
12934         default:
12935           dp = &bad_opcode;
12936           return dp;
12937         case 0x1:
12938           vex_table_index = VEX_0F;
12939           break;
12940         case 0x2:
12941           vex_table_index = VEX_0F38;
12942           break;
12943         case 0x3:
12944           vex_table_index = VEX_0F3A;
12945           break;
12946         }
12947       codep++;
12948       vex.w = *codep & 0x80;
12949       if (address_mode == mode_64bit)
12950         {
12951           if (vex.w)
12952             rex |= REX_W;
12953         }
12954       else
12955         {
12956           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12957              is ignored, other REX bits are 0 and the highest bit in
12958              VEX.vvvv is also ignored (but we mustn't clear it here).  */
12959           rex = 0;
12960         }
12961       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12962       vex.length = (*codep & 0x4) ? 256 : 128;
12963       switch ((*codep & 0x3))
12964         {
12965         case 0:
12966           break;
12967         case 1:
12968           vex.prefix = DATA_PREFIX_OPCODE;
12969           break;
12970         case 2:
12971           vex.prefix = REPE_PREFIX_OPCODE;
12972           break;
12973         case 3:
12974           vex.prefix = REPNE_PREFIX_OPCODE;
12975           break;
12976         }
12977       need_vex = 1;
12978       need_vex_reg = 1;
12979       codep++;
12980       vindex = *codep++;
12981       dp = &vex_table[vex_table_index][vindex];
12982       end_codep = codep;
12983       /* There is no MODRM byte for VEX0F 77.  */
12984       if (vex_table_index != VEX_0F || vindex != 0x77)
12985         {
12986           FETCH_DATA (info, codep + 1);
12987           modrm.mod = (*codep >> 6) & 3;
12988           modrm.reg = (*codep >> 3) & 7;
12989           modrm.rm = *codep & 7;
12990         }
12991       break;
12992
12993     case USE_VEX_C5_TABLE:
12994       /* VEX prefix.  */
12995       FETCH_DATA (info, codep + 2);
12996       /* All bits in the REX prefix are ignored.  */
12997       rex_ignored = rex;
12998       rex = (*codep & 0x80) ? 0 : REX_R;
12999
13000       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
13001          VEX.vvvv is 1.  */
13002       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13003       vex.length = (*codep & 0x4) ? 256 : 128;
13004       switch ((*codep & 0x3))
13005         {
13006         case 0:
13007           break;
13008         case 1:
13009           vex.prefix = DATA_PREFIX_OPCODE;
13010           break;
13011         case 2:
13012           vex.prefix = REPE_PREFIX_OPCODE;
13013           break;
13014         case 3:
13015           vex.prefix = REPNE_PREFIX_OPCODE;
13016           break;
13017         }
13018       need_vex = 1;
13019       need_vex_reg = 1;
13020       codep++;
13021       vindex = *codep++;
13022       dp = &vex_table[dp->op[1].bytemode][vindex];
13023       end_codep = codep;
13024       /* There is no MODRM byte for VEX 77.  */
13025       if (vindex != 0x77)
13026         {
13027           FETCH_DATA (info, codep + 1);
13028           modrm.mod = (*codep >> 6) & 3;
13029           modrm.reg = (*codep >> 3) & 7;
13030           modrm.rm = *codep & 7;
13031         }
13032       break;
13033
13034     case USE_VEX_W_TABLE:
13035       if (!need_vex)
13036         abort ();
13037
13038       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
13039       break;
13040
13041     case USE_EVEX_TABLE:
13042       two_source_ops = 0;
13043       /* EVEX prefix.  */
13044       vex.evex = 1;
13045       FETCH_DATA (info, codep + 4);
13046       /* All bits in the REX prefix are ignored.  */
13047       rex_ignored = rex;
13048       /* The first byte after 0x62.  */
13049       rex = ~(*codep >> 5) & 0x7;
13050       vex.r = *codep & 0x10;
13051       switch ((*codep & 0xf))
13052         {
13053         default:
13054           return &bad_opcode;
13055         case 0x1:
13056           vex_table_index = EVEX_0F;
13057           break;
13058         case 0x2:
13059           vex_table_index = EVEX_0F38;
13060           break;
13061         case 0x3:
13062           vex_table_index = EVEX_0F3A;
13063           break;
13064         }
13065
13066       /* The second byte after 0x62.  */
13067       codep++;
13068       vex.w = *codep & 0x80;
13069       if (vex.w && address_mode == mode_64bit)
13070         rex |= REX_W;
13071
13072       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13073
13074       /* The U bit.  */
13075       if (!(*codep & 0x4))
13076         return &bad_opcode;
13077
13078       switch ((*codep & 0x3))
13079         {
13080         case 0:
13081           break;
13082         case 1:
13083           vex.prefix = DATA_PREFIX_OPCODE;
13084           break;
13085         case 2:
13086           vex.prefix = REPE_PREFIX_OPCODE;
13087           break;
13088         case 3:
13089           vex.prefix = REPNE_PREFIX_OPCODE;
13090           break;
13091         }
13092
13093       /* The third byte after 0x62.  */
13094       codep++;
13095
13096       /* Remember the static rounding bits.  */
13097       vex.ll = (*codep >> 5) & 3;
13098       vex.b = (*codep & 0x10) != 0;
13099
13100       vex.v = *codep & 0x8;
13101       vex.mask_register_specifier = *codep & 0x7;
13102       vex.zeroing = *codep & 0x80;
13103
13104       if (address_mode != mode_64bit)
13105         {
13106           /* In 16/32-bit mode silently ignore following bits.  */
13107           rex &= ~REX_B;
13108           vex.r = 1;
13109           vex.v = 1;
13110         }
13111
13112       need_vex = 1;
13113       need_vex_reg = 1;
13114       codep++;
13115       vindex = *codep++;
13116       dp = &evex_table[vex_table_index][vindex];
13117       end_codep = codep;
13118       FETCH_DATA (info, codep + 1);
13119       modrm.mod = (*codep >> 6) & 3;
13120       modrm.reg = (*codep >> 3) & 7;
13121       modrm.rm = *codep & 7;
13122
13123       /* Set vector length.  */
13124       if (modrm.mod == 3 && vex.b)
13125         vex.length = 512;
13126       else
13127         {
13128           switch (vex.ll)
13129             {
13130             case 0x0:
13131               vex.length = 128;
13132               break;
13133             case 0x1:
13134               vex.length = 256;
13135               break;
13136             case 0x2:
13137               vex.length = 512;
13138               break;
13139             default:
13140               return &bad_opcode;
13141             }
13142         }
13143       break;
13144
13145     case 0:
13146       dp = &bad_opcode;
13147       break;
13148
13149     default:
13150       abort ();
13151     }
13152
13153   if (dp->name != NULL)
13154     return dp;
13155   else
13156     return get_valid_dis386 (dp, info);
13157 }
13158
13159 static void
13160 get_sib (disassemble_info *info, int sizeflag)
13161 {
13162   /* If modrm.mod == 3, operand must be register.  */
13163   if (need_modrm
13164       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13165       && modrm.mod != 3
13166       && modrm.rm == 4)
13167     {
13168       FETCH_DATA (info, codep + 2);
13169       sib.index = (codep [1] >> 3) & 7;
13170       sib.scale = (codep [1] >> 6) & 3;
13171       sib.base = codep [1] & 7;
13172     }
13173 }
13174
13175 static int
13176 print_insn (bfd_vma pc, disassemble_info *info)
13177 {
13178   const struct dis386 *dp;
13179   int i;
13180   char *op_txt[MAX_OPERANDS];
13181   int needcomma;
13182   int sizeflag, orig_sizeflag;
13183   const char *p;
13184   struct dis_private priv;
13185   int prefix_length;
13186
13187   priv.orig_sizeflag = AFLAG | DFLAG;
13188   if ((info->mach & bfd_mach_i386_i386) != 0)
13189     address_mode = mode_32bit;
13190   else if (info->mach == bfd_mach_i386_i8086)
13191     {
13192       address_mode = mode_16bit;
13193       priv.orig_sizeflag = 0;
13194     }
13195   else
13196     address_mode = mode_64bit;
13197
13198   if (intel_syntax == (char) -1)
13199     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13200
13201   for (p = info->disassembler_options; p != NULL; )
13202     {
13203       if (CONST_STRNEQ (p, "amd64"))
13204         isa64 = amd64;
13205       else if (CONST_STRNEQ (p, "intel64"))
13206         isa64 = intel64;
13207       else if (CONST_STRNEQ (p, "x86-64"))
13208         {
13209           address_mode = mode_64bit;
13210           priv.orig_sizeflag = AFLAG | DFLAG;
13211         }
13212       else if (CONST_STRNEQ (p, "i386"))
13213         {
13214           address_mode = mode_32bit;
13215           priv.orig_sizeflag = AFLAG | DFLAG;
13216         }
13217       else if (CONST_STRNEQ (p, "i8086"))
13218         {
13219           address_mode = mode_16bit;
13220           priv.orig_sizeflag = 0;
13221         }
13222       else if (CONST_STRNEQ (p, "intel"))
13223         {
13224           intel_syntax = 1;
13225           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13226             intel_mnemonic = 1;
13227         }
13228       else if (CONST_STRNEQ (p, "att"))
13229         {
13230           intel_syntax = 0;
13231           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13232             intel_mnemonic = 0;
13233         }
13234       else if (CONST_STRNEQ (p, "addr"))
13235         {
13236           if (address_mode == mode_64bit)
13237             {
13238               if (p[4] == '3' && p[5] == '2')
13239                 priv.orig_sizeflag &= ~AFLAG;
13240               else if (p[4] == '6' && p[5] == '4')
13241                 priv.orig_sizeflag |= AFLAG;
13242             }
13243           else
13244             {
13245               if (p[4] == '1' && p[5] == '6')
13246                 priv.orig_sizeflag &= ~AFLAG;
13247               else if (p[4] == '3' && p[5] == '2')
13248                 priv.orig_sizeflag |= AFLAG;
13249             }
13250         }
13251       else if (CONST_STRNEQ (p, "data"))
13252         {
13253           if (p[4] == '1' && p[5] == '6')
13254             priv.orig_sizeflag &= ~DFLAG;
13255           else if (p[4] == '3' && p[5] == '2')
13256             priv.orig_sizeflag |= DFLAG;
13257         }
13258       else if (CONST_STRNEQ (p, "suffix"))
13259         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13260
13261       p = strchr (p, ',');
13262       if (p != NULL)
13263         p++;
13264     }
13265
13266   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13267     {
13268       (*info->fprintf_func) (info->stream,
13269                              _("64-bit address is disabled"));
13270       return -1;
13271     }
13272
13273   if (intel_syntax)
13274     {
13275       names64 = intel_names64;
13276       names32 = intel_names32;
13277       names16 = intel_names16;
13278       names8 = intel_names8;
13279       names8rex = intel_names8rex;
13280       names_seg = intel_names_seg;
13281       names_mm = intel_names_mm;
13282       names_bnd = intel_names_bnd;
13283       names_xmm = intel_names_xmm;
13284       names_ymm = intel_names_ymm;
13285       names_zmm = intel_names_zmm;
13286       index64 = intel_index64;
13287       index32 = intel_index32;
13288       names_mask = intel_names_mask;
13289       index16 = intel_index16;
13290       open_char = '[';
13291       close_char = ']';
13292       separator_char = '+';
13293       scale_char = '*';
13294     }
13295   else
13296     {
13297       names64 = att_names64;
13298       names32 = att_names32;
13299       names16 = att_names16;
13300       names8 = att_names8;
13301       names8rex = att_names8rex;
13302       names_seg = att_names_seg;
13303       names_mm = att_names_mm;
13304       names_bnd = att_names_bnd;
13305       names_xmm = att_names_xmm;
13306       names_ymm = att_names_ymm;
13307       names_zmm = att_names_zmm;
13308       index64 = att_index64;
13309       index32 = att_index32;
13310       names_mask = att_names_mask;
13311       index16 = att_index16;
13312       open_char = '(';
13313       close_char =  ')';
13314       separator_char = ',';
13315       scale_char = ',';
13316     }
13317
13318   /* The output looks better if we put 7 bytes on a line, since that
13319      puts most long word instructions on a single line.  Use 8 bytes
13320      for Intel L1OM.  */
13321   if ((info->mach & bfd_mach_l1om) != 0)
13322     info->bytes_per_line = 8;
13323   else
13324     info->bytes_per_line = 7;
13325
13326   info->private_data = &priv;
13327   priv.max_fetched = priv.the_buffer;
13328   priv.insn_start = pc;
13329
13330   obuf[0] = 0;
13331   for (i = 0; i < MAX_OPERANDS; ++i)
13332     {
13333       op_out[i][0] = 0;
13334       op_index[i] = -1;
13335     }
13336
13337   the_info = info;
13338   start_pc = pc;
13339   start_codep = priv.the_buffer;
13340   codep = priv.the_buffer;
13341
13342   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13343     {
13344       const char *name;
13345
13346       /* Getting here means we tried for data but didn't get it.  That
13347          means we have an incomplete instruction of some sort.  Just
13348          print the first byte as a prefix or a .byte pseudo-op.  */
13349       if (codep > priv.the_buffer)
13350         {
13351           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13352           if (name != NULL)
13353             (*info->fprintf_func) (info->stream, "%s", name);
13354           else
13355             {
13356               /* Just print the first byte as a .byte instruction.  */
13357               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13358                                      (unsigned int) priv.the_buffer[0]);
13359             }
13360
13361           return 1;
13362         }
13363
13364       return -1;
13365     }
13366
13367   obufp = obuf;
13368   sizeflag = priv.orig_sizeflag;
13369
13370   if (!ckprefix () || rex_used)
13371     {
13372       /* Too many prefixes or unused REX prefixes.  */
13373       for (i = 0;
13374            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13375            i++)
13376         (*info->fprintf_func) (info->stream, "%s%s",
13377                                i == 0 ? "" : " ",
13378                                prefix_name (all_prefixes[i], sizeflag));
13379       return i;
13380     }
13381
13382   insn_codep = codep;
13383
13384   FETCH_DATA (info, codep + 1);
13385   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13386
13387   if (((prefixes & PREFIX_FWAIT)
13388        && ((*codep < 0xd8) || (*codep > 0xdf))))
13389     {
13390       /* Handle prefixes before fwait.  */
13391       for (i = 0; i < fwait_prefix && all_prefixes[i];
13392            i++)
13393         (*info->fprintf_func) (info->stream, "%s ",
13394                                prefix_name (all_prefixes[i], sizeflag));
13395       (*info->fprintf_func) (info->stream, "fwait");
13396       return i + 1;
13397     }
13398
13399   if (*codep == 0x0f)
13400     {
13401       unsigned char threebyte;
13402
13403       codep++;
13404       FETCH_DATA (info, codep + 1);
13405       threebyte = *codep;
13406       dp = &dis386_twobyte[threebyte];
13407       need_modrm = twobyte_has_modrm[*codep];
13408       codep++;
13409     }
13410   else
13411     {
13412       dp = &dis386[*codep];
13413       need_modrm = onebyte_has_modrm[*codep];
13414       codep++;
13415     }
13416
13417   /* Save sizeflag for printing the extra prefixes later before updating
13418      it for mnemonic and operand processing.  The prefix names depend
13419      only on the address mode.  */
13420   orig_sizeflag = sizeflag;
13421   if (prefixes & PREFIX_ADDR)
13422     sizeflag ^= AFLAG;
13423   if ((prefixes & PREFIX_DATA))
13424     sizeflag ^= DFLAG;
13425
13426   end_codep = codep;
13427   if (need_modrm)
13428     {
13429       FETCH_DATA (info, codep + 1);
13430       modrm.mod = (*codep >> 6) & 3;
13431       modrm.reg = (*codep >> 3) & 7;
13432       modrm.rm = *codep & 7;
13433     }
13434
13435   need_vex = 0;
13436   need_vex_reg = 0;
13437   vex_w_done = 0;
13438   memset (&vex, 0, sizeof (vex));
13439
13440   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13441     {
13442       get_sib (info, sizeflag);
13443       dofloat (sizeflag);
13444     }
13445   else
13446     {
13447       dp = get_valid_dis386 (dp, info);
13448       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13449         {
13450           get_sib (info, sizeflag);
13451           for (i = 0; i < MAX_OPERANDS; ++i)
13452             {
13453               obufp = op_out[i];
13454               op_ad = MAX_OPERANDS - 1 - i;
13455               if (dp->op[i].rtn)
13456                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13457               /* For EVEX instruction after the last operand masking
13458                  should be printed.  */
13459               if (i == 0 && vex.evex)
13460                 {
13461                   /* Don't print {%k0}.  */
13462                   if (vex.mask_register_specifier)
13463                     {
13464                       oappend ("{");
13465                       oappend (names_mask[vex.mask_register_specifier]);
13466                       oappend ("}");
13467                     }
13468                   if (vex.zeroing)
13469                     oappend ("{z}");
13470                 }
13471             }
13472         }
13473     }
13474
13475   /* Check if the REX prefix is used.  */
13476   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13477     all_prefixes[last_rex_prefix] = 0;
13478
13479   /* Check if the SEG prefix is used.  */
13480   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13481                    | PREFIX_FS | PREFIX_GS)) != 0
13482       && (used_prefixes & active_seg_prefix) != 0)
13483     all_prefixes[last_seg_prefix] = 0;
13484
13485   /* Check if the ADDR prefix is used.  */
13486   if ((prefixes & PREFIX_ADDR) != 0
13487       && (used_prefixes & PREFIX_ADDR) != 0)
13488     all_prefixes[last_addr_prefix] = 0;
13489
13490   /* Check if the DATA prefix is used.  */
13491   if ((prefixes & PREFIX_DATA) != 0
13492       && (used_prefixes & PREFIX_DATA) != 0)
13493     all_prefixes[last_data_prefix] = 0;
13494
13495   /* Print the extra prefixes.  */
13496   prefix_length = 0;
13497   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13498     if (all_prefixes[i])
13499       {
13500         const char *name;
13501         name = prefix_name (all_prefixes[i], orig_sizeflag);
13502         if (name == NULL)
13503           abort ();
13504         prefix_length += strlen (name) + 1;
13505         (*info->fprintf_func) (info->stream, "%s ", name);
13506       }
13507
13508   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13509      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13510      used by putop and MMX/SSE operand and may be overriden by the
13511      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13512      separately.  */
13513   if (dp->prefix_requirement == PREFIX_OPCODE
13514       && dp != &bad_opcode
13515       && (((prefixes
13516             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13517            && (used_prefixes
13518                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13519           || ((((prefixes
13520                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13521                 == PREFIX_DATA)
13522                && (used_prefixes & PREFIX_DATA) == 0))))
13523     {
13524       (*info->fprintf_func) (info->stream, "(bad)");
13525       return end_codep - priv.the_buffer;
13526     }
13527
13528   /* Check maximum code length.  */
13529   if ((codep - start_codep) > MAX_CODE_LENGTH)
13530     {
13531       (*info->fprintf_func) (info->stream, "(bad)");
13532       return MAX_CODE_LENGTH;
13533     }
13534
13535   obufp = mnemonicendp;
13536   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13537     oappend (" ");
13538   oappend (" ");
13539   (*info->fprintf_func) (info->stream, "%s", obuf);
13540
13541   /* The enter and bound instructions are printed with operands in the same
13542      order as the intel book; everything else is printed in reverse order.  */
13543   if (intel_syntax || two_source_ops)
13544     {
13545       bfd_vma riprel;
13546
13547       for (i = 0; i < MAX_OPERANDS; ++i)
13548         op_txt[i] = op_out[i];
13549
13550       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13551           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13552         {
13553           op_txt[2] = op_out[3];
13554           op_txt[3] = op_out[2];
13555         }
13556
13557       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13558         {
13559           op_ad = op_index[i];
13560           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13561           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13562           riprel = op_riprel[i];
13563           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13564           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13565         }
13566     }
13567   else
13568     {
13569       for (i = 0; i < MAX_OPERANDS; ++i)
13570         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13571     }
13572
13573   needcomma = 0;
13574   for (i = 0; i < MAX_OPERANDS; ++i)
13575     if (*op_txt[i])
13576       {
13577         if (needcomma)
13578           (*info->fprintf_func) (info->stream, ",");
13579         if (op_index[i] != -1 && !op_riprel[i])
13580           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13581         else
13582           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13583         needcomma = 1;
13584       }
13585
13586   for (i = 0; i < MAX_OPERANDS; i++)
13587     if (op_index[i] != -1 && op_riprel[i])
13588       {
13589         (*info->fprintf_func) (info->stream, "        # ");
13590         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13591                                                 + op_address[op_index[i]]), info);
13592         break;
13593       }
13594   return codep - priv.the_buffer;
13595 }
13596
13597 static const char *float_mem[] = {
13598   /* d8 */
13599   "fadd{s|}",
13600   "fmul{s|}",
13601   "fcom{s|}",
13602   "fcomp{s|}",
13603   "fsub{s|}",
13604   "fsubr{s|}",
13605   "fdiv{s|}",
13606   "fdivr{s|}",
13607   /* d9 */
13608   "fld{s|}",
13609   "(bad)",
13610   "fst{s|}",
13611   "fstp{s|}",
13612   "fldenvIC",
13613   "fldcw",
13614   "fNstenvIC",
13615   "fNstcw",
13616   /* da */
13617   "fiadd{l|}",
13618   "fimul{l|}",
13619   "ficom{l|}",
13620   "ficomp{l|}",
13621   "fisub{l|}",
13622   "fisubr{l|}",
13623   "fidiv{l|}",
13624   "fidivr{l|}",
13625   /* db */
13626   "fild{l|}",
13627   "fisttp{l|}",
13628   "fist{l|}",
13629   "fistp{l|}",
13630   "(bad)",
13631   "fld{t||t|}",
13632   "(bad)",
13633   "fstp{t||t|}",
13634   /* dc */
13635   "fadd{l|}",
13636   "fmul{l|}",
13637   "fcom{l|}",
13638   "fcomp{l|}",
13639   "fsub{l|}",
13640   "fsubr{l|}",
13641   "fdiv{l|}",
13642   "fdivr{l|}",
13643   /* dd */
13644   "fld{l|}",
13645   "fisttp{ll|}",
13646   "fst{l||}",
13647   "fstp{l|}",
13648   "frstorIC",
13649   "(bad)",
13650   "fNsaveIC",
13651   "fNstsw",
13652   /* de */
13653   "fiadd{s|}",
13654   "fimul{s|}",
13655   "ficom{s|}",
13656   "ficomp{s|}",
13657   "fisub{s|}",
13658   "fisubr{s|}",
13659   "fidiv{s|}",
13660   "fidivr{s|}",
13661   /* df */
13662   "fild{s|}",
13663   "fisttp{s|}",
13664   "fist{s|}",
13665   "fistp{s|}",
13666   "fbld",
13667   "fild{ll|}",
13668   "fbstp",
13669   "fistp{ll|}",
13670 };
13671
13672 static const unsigned char float_mem_mode[] = {
13673   /* d8 */
13674   d_mode,
13675   d_mode,
13676   d_mode,
13677   d_mode,
13678   d_mode,
13679   d_mode,
13680   d_mode,
13681   d_mode,
13682   /* d9 */
13683   d_mode,
13684   0,
13685   d_mode,
13686   d_mode,
13687   0,
13688   w_mode,
13689   0,
13690   w_mode,
13691   /* da */
13692   d_mode,
13693   d_mode,
13694   d_mode,
13695   d_mode,
13696   d_mode,
13697   d_mode,
13698   d_mode,
13699   d_mode,
13700   /* db */
13701   d_mode,
13702   d_mode,
13703   d_mode,
13704   d_mode,
13705   0,
13706   t_mode,
13707   0,
13708   t_mode,
13709   /* dc */
13710   q_mode,
13711   q_mode,
13712   q_mode,
13713   q_mode,
13714   q_mode,
13715   q_mode,
13716   q_mode,
13717   q_mode,
13718   /* dd */
13719   q_mode,
13720   q_mode,
13721   q_mode,
13722   q_mode,
13723   0,
13724   0,
13725   0,
13726   w_mode,
13727   /* de */
13728   w_mode,
13729   w_mode,
13730   w_mode,
13731   w_mode,
13732   w_mode,
13733   w_mode,
13734   w_mode,
13735   w_mode,
13736   /* df */
13737   w_mode,
13738   w_mode,
13739   w_mode,
13740   w_mode,
13741   t_mode,
13742   q_mode,
13743   t_mode,
13744   q_mode
13745 };
13746
13747 #define ST { OP_ST, 0 }
13748 #define STi { OP_STi, 0 }
13749
13750 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13751 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13752 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13753 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13754 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13755 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13756 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13757 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13758 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13759
13760 static const struct dis386 float_reg[][8] = {
13761   /* d8 */
13762   {
13763     { "fadd",   { ST, STi }, 0 },
13764     { "fmul",   { ST, STi }, 0 },
13765     { "fcom",   { STi }, 0 },
13766     { "fcomp",  { STi }, 0 },
13767     { "fsub",   { ST, STi }, 0 },
13768     { "fsubr",  { ST, STi }, 0 },
13769     { "fdiv",   { ST, STi }, 0 },
13770     { "fdivr",  { ST, STi }, 0 },
13771   },
13772   /* d9 */
13773   {
13774     { "fld",    { STi }, 0 },
13775     { "fxch",   { STi }, 0 },
13776     { FGRPd9_2 },
13777     { Bad_Opcode },
13778     { FGRPd9_4 },
13779     { FGRPd9_5 },
13780     { FGRPd9_6 },
13781     { FGRPd9_7 },
13782   },
13783   /* da */
13784   {
13785     { "fcmovb", { ST, STi }, 0 },
13786     { "fcmove", { ST, STi }, 0 },
13787     { "fcmovbe",{ ST, STi }, 0 },
13788     { "fcmovu", { ST, STi }, 0 },
13789     { Bad_Opcode },
13790     { FGRPda_5 },
13791     { Bad_Opcode },
13792     { Bad_Opcode },
13793   },
13794   /* db */
13795   {
13796     { "fcmovnb",{ ST, STi }, 0 },
13797     { "fcmovne",{ ST, STi }, 0 },
13798     { "fcmovnbe",{ ST, STi }, 0 },
13799     { "fcmovnu",{ ST, STi }, 0 },
13800     { FGRPdb_4 },
13801     { "fucomi", { ST, STi }, 0 },
13802     { "fcomi",  { ST, STi }, 0 },
13803     { Bad_Opcode },
13804   },
13805   /* dc */
13806   {
13807     { "fadd",   { STi, ST }, 0 },
13808     { "fmul",   { STi, ST }, 0 },
13809     { Bad_Opcode },
13810     { Bad_Opcode },
13811     { "fsub{!M|r}",     { STi, ST }, 0 },
13812     { "fsub{M|}",       { STi, ST }, 0 },
13813     { "fdiv{!M|r}",     { STi, ST }, 0 },
13814     { "fdiv{M|}",       { STi, ST }, 0 },
13815   },
13816   /* dd */
13817   {
13818     { "ffree",  { STi }, 0 },
13819     { Bad_Opcode },
13820     { "fst",    { STi }, 0 },
13821     { "fstp",   { STi }, 0 },
13822     { "fucom",  { STi }, 0 },
13823     { "fucomp", { STi }, 0 },
13824     { Bad_Opcode },
13825     { Bad_Opcode },
13826   },
13827   /* de */
13828   {
13829     { "faddp",  { STi, ST }, 0 },
13830     { "fmulp",  { STi, ST }, 0 },
13831     { Bad_Opcode },
13832     { FGRPde_3 },
13833     { "fsub{!M|r}p",    { STi, ST }, 0 },
13834     { "fsub{M|}p",      { STi, ST }, 0 },
13835     { "fdiv{!M|r}p",    { STi, ST }, 0 },
13836     { "fdiv{M|}p",      { STi, ST }, 0 },
13837   },
13838   /* df */
13839   {
13840     { "ffreep", { STi }, 0 },
13841     { Bad_Opcode },
13842     { Bad_Opcode },
13843     { Bad_Opcode },
13844     { FGRPdf_4 },
13845     { "fucomip", { ST, STi }, 0 },
13846     { "fcomip", { ST, STi }, 0 },
13847     { Bad_Opcode },
13848   },
13849 };
13850
13851 static char *fgrps[][8] = {
13852   /* Bad opcode 0 */
13853   {
13854     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13855   },
13856
13857   /* d9_2  1 */
13858   {
13859     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13860   },
13861
13862   /* d9_4  2 */
13863   {
13864     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13865   },
13866
13867   /* d9_5  3 */
13868   {
13869     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13870   },
13871
13872   /* d9_6  4 */
13873   {
13874     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13875   },
13876
13877   /* d9_7  5 */
13878   {
13879     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13880   },
13881
13882   /* da_5  6 */
13883   {
13884     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13885   },
13886
13887   /* db_4  7 */
13888   {
13889     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13890     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13891   },
13892
13893   /* de_3  8 */
13894   {
13895     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13896   },
13897
13898   /* df_4  9 */
13899   {
13900     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13901   },
13902 };
13903
13904 static void
13905 swap_operand (void)
13906 {
13907   mnemonicendp[0] = '.';
13908   mnemonicendp[1] = 's';
13909   mnemonicendp += 2;
13910 }
13911
13912 static void
13913 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13914                int sizeflag ATTRIBUTE_UNUSED)
13915 {
13916   /* Skip mod/rm byte.  */
13917   MODRM_CHECK;
13918   codep++;
13919 }
13920
13921 static void
13922 dofloat (int sizeflag)
13923 {
13924   const struct dis386 *dp;
13925   unsigned char floatop;
13926
13927   floatop = codep[-1];
13928
13929   if (modrm.mod != 3)
13930     {
13931       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13932
13933       putop (float_mem[fp_indx], sizeflag);
13934       obufp = op_out[0];
13935       op_ad = 2;
13936       OP_E (float_mem_mode[fp_indx], sizeflag);
13937       return;
13938     }
13939   /* Skip mod/rm byte.  */
13940   MODRM_CHECK;
13941   codep++;
13942
13943   dp = &float_reg[floatop - 0xd8][modrm.reg];
13944   if (dp->name == NULL)
13945     {
13946       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13947
13948       /* Instruction fnstsw is only one with strange arg.  */
13949       if (floatop == 0xdf && codep[-1] == 0xe0)
13950         strcpy (op_out[0], names16[0]);
13951     }
13952   else
13953     {
13954       putop (dp->name, sizeflag);
13955
13956       obufp = op_out[0];
13957       op_ad = 2;
13958       if (dp->op[0].rtn)
13959         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13960
13961       obufp = op_out[1];
13962       op_ad = 1;
13963       if (dp->op[1].rtn)
13964         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13965     }
13966 }
13967
13968 /* Like oappend (below), but S is a string starting with '%'.
13969    In Intel syntax, the '%' is elided.  */
13970 static void
13971 oappend_maybe_intel (const char *s)
13972 {
13973   oappend (s + intel_syntax);
13974 }
13975
13976 static void
13977 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13978 {
13979   oappend_maybe_intel ("%st");
13980 }
13981
13982 static void
13983 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13984 {
13985   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13986   oappend_maybe_intel (scratchbuf);
13987 }
13988
13989 /* Capital letters in template are macros.  */
13990 static int
13991 putop (const char *in_template, int sizeflag)
13992 {
13993   const char *p;
13994   int alt = 0;
13995   int cond = 1;
13996   unsigned int l = 0, len = 1;
13997   char last[4];
13998
13999 #define SAVE_LAST(c)                    \
14000   if (l < len && l < sizeof (last))     \
14001     last[l++] = c;                      \
14002   else                                  \
14003     abort ();
14004
14005   for (p = in_template; *p; p++)
14006     {
14007       switch (*p)
14008         {
14009         default:
14010           *obufp++ = *p;
14011           break;
14012         case '%':
14013           len++;
14014           break;
14015         case '!':
14016           cond = 0;
14017           break;
14018         case '{':
14019           if (intel_syntax)
14020             {
14021               while (*++p != '|')
14022                 if (*p == '}' || *p == '\0')
14023                   abort ();
14024             }
14025           /* Fall through.  */
14026         case 'I':
14027           alt = 1;
14028           continue;
14029         case '|':
14030           while (*++p != '}')
14031             {
14032               if (*p == '\0')
14033                 abort ();
14034             }
14035           break;
14036         case '}':
14037           break;
14038         case 'A':
14039           if (intel_syntax)
14040             break;
14041           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14042             *obufp++ = 'b';
14043           break;
14044         case 'B':
14045           if (l == 0 && len == 1)
14046             {
14047 case_B:
14048               if (intel_syntax)
14049                 break;
14050               if (sizeflag & SUFFIX_ALWAYS)
14051                 *obufp++ = 'b';
14052             }
14053           else
14054             {
14055               if (l != 1
14056                   || len != 2
14057                   || last[0] != 'L')
14058                 {
14059                   SAVE_LAST (*p);
14060                   break;
14061                 }
14062
14063               if (address_mode == mode_64bit
14064                   && !(prefixes & PREFIX_ADDR))
14065                 {
14066                   *obufp++ = 'a';
14067                   *obufp++ = 'b';
14068                   *obufp++ = 's';
14069                 }
14070
14071               goto case_B;
14072             }
14073           break;
14074         case 'C':
14075           if (intel_syntax && !alt)
14076             break;
14077           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14078             {
14079               if (sizeflag & DFLAG)
14080                 *obufp++ = intel_syntax ? 'd' : 'l';
14081               else
14082                 *obufp++ = intel_syntax ? 'w' : 's';
14083               used_prefixes |= (prefixes & PREFIX_DATA);
14084             }
14085           break;
14086         case 'D':
14087           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14088             break;
14089           USED_REX (REX_W);
14090           if (modrm.mod == 3)
14091             {
14092               if (rex & REX_W)
14093                 *obufp++ = 'q';
14094               else
14095                 {
14096                   if (sizeflag & DFLAG)
14097                     *obufp++ = intel_syntax ? 'd' : 'l';
14098                   else
14099                     *obufp++ = 'w';
14100                   used_prefixes |= (prefixes & PREFIX_DATA);
14101                 }
14102             }
14103           else
14104             *obufp++ = 'w';
14105           break;
14106         case 'E':               /* For jcxz/jecxz */
14107           if (address_mode == mode_64bit)
14108             {
14109               if (sizeflag & AFLAG)
14110                 *obufp++ = 'r';
14111               else
14112                 *obufp++ = 'e';
14113             }
14114           else
14115             if (sizeflag & AFLAG)
14116               *obufp++ = 'e';
14117           used_prefixes |= (prefixes & PREFIX_ADDR);
14118           break;
14119         case 'F':
14120           if (intel_syntax)
14121             break;
14122           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14123             {
14124               if (sizeflag & AFLAG)
14125                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14126               else
14127                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14128               used_prefixes |= (prefixes & PREFIX_ADDR);
14129             }
14130           break;
14131         case 'G':
14132           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14133             break;
14134           if ((rex & REX_W) || (sizeflag & DFLAG))
14135             *obufp++ = 'l';
14136           else
14137             *obufp++ = 'w';
14138           if (!(rex & REX_W))
14139             used_prefixes |= (prefixes & PREFIX_DATA);
14140           break;
14141         case 'H':
14142           if (intel_syntax)
14143             break;
14144           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14145               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14146             {
14147               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14148               *obufp++ = ',';
14149               *obufp++ = 'p';
14150               if (prefixes & PREFIX_DS)
14151                 *obufp++ = 't';
14152               else
14153                 *obufp++ = 'n';
14154             }
14155           break;
14156         case 'J':
14157           if (intel_syntax)
14158             break;
14159           *obufp++ = 'l';
14160           break;
14161         case 'K':
14162           USED_REX (REX_W);
14163           if (rex & REX_W)
14164             *obufp++ = 'q';
14165           else
14166             *obufp++ = 'd';
14167           break;
14168         case 'Z':
14169           if (l != 0 || len != 1)
14170             {
14171               if (l != 1 || len != 2 || last[0] != 'X')
14172                 {
14173                   SAVE_LAST (*p);
14174                   break;
14175                 }
14176               if (!need_vex || !vex.evex)
14177                 abort ();
14178               if (intel_syntax
14179                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14180                 break;
14181               switch (vex.length)
14182                 {
14183                 case 128:
14184                   *obufp++ = 'x';
14185                   break;
14186                 case 256:
14187                   *obufp++ = 'y';
14188                   break;
14189                 case 512:
14190                   *obufp++ = 'z';
14191                   break;
14192                 default:
14193                   abort ();
14194                 }
14195               break;
14196             }
14197           if (intel_syntax)
14198             break;
14199           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14200             {
14201               *obufp++ = 'q';
14202               break;
14203             }
14204           /* Fall through.  */
14205           goto case_L;
14206         case 'L':
14207           if (l != 0 || len != 1)
14208             {
14209               SAVE_LAST (*p);
14210               break;
14211             }
14212 case_L:
14213           if (intel_syntax)
14214             break;
14215           if (sizeflag & SUFFIX_ALWAYS)
14216             *obufp++ = 'l';
14217           break;
14218         case 'M':
14219           if (intel_mnemonic != cond)
14220             *obufp++ = 'r';
14221           break;
14222         case 'N':
14223           if ((prefixes & PREFIX_FWAIT) == 0)
14224             *obufp++ = 'n';
14225           else
14226             used_prefixes |= PREFIX_FWAIT;
14227           break;
14228         case 'O':
14229           USED_REX (REX_W);
14230           if (rex & REX_W)
14231             *obufp++ = 'o';
14232           else if (intel_syntax && (sizeflag & DFLAG))
14233             *obufp++ = 'q';
14234           else
14235             *obufp++ = 'd';
14236           if (!(rex & REX_W))
14237             used_prefixes |= (prefixes & PREFIX_DATA);
14238           break;
14239         case '&':
14240           if (!intel_syntax
14241               && address_mode == mode_64bit
14242               && isa64 == intel64)
14243             {
14244               *obufp++ = 'q';
14245               break;
14246             }
14247           /* Fall through.  */
14248         case 'T':
14249           if (!intel_syntax
14250               && address_mode == mode_64bit
14251               && ((sizeflag & DFLAG) || (rex & REX_W)))
14252             {
14253               *obufp++ = 'q';
14254               break;
14255             }
14256           /* Fall through.  */
14257           goto case_P;
14258         case 'P':
14259           if (l == 0 && len == 1)
14260             {
14261 case_P:
14262               if (intel_syntax)
14263                 {
14264                   if ((rex & REX_W) == 0
14265                       && (prefixes & PREFIX_DATA))
14266                     {
14267                       if ((sizeflag & DFLAG) == 0)
14268                         *obufp++ = 'w';
14269                       used_prefixes |= (prefixes & PREFIX_DATA);
14270                     }
14271                   break;
14272                 }
14273               if ((prefixes & PREFIX_DATA)
14274                   || (rex & REX_W)
14275                   || (sizeflag & SUFFIX_ALWAYS))
14276                 {
14277                   USED_REX (REX_W);
14278                   if (rex & REX_W)
14279                     *obufp++ = 'q';
14280                   else
14281                     {
14282                       if (sizeflag & DFLAG)
14283                         *obufp++ = 'l';
14284                       else
14285                         *obufp++ = 'w';
14286                       used_prefixes |= (prefixes & PREFIX_DATA);
14287                     }
14288                 }
14289             }
14290           else
14291             {
14292               if (l != 1 || len != 2 || last[0] != 'L')
14293                 {
14294                   SAVE_LAST (*p);
14295                   break;
14296                 }
14297
14298               if ((prefixes & PREFIX_DATA)
14299                   || (rex & REX_W)
14300                   || (sizeflag & SUFFIX_ALWAYS))
14301                 {
14302                   USED_REX (REX_W);
14303                   if (rex & REX_W)
14304                     *obufp++ = 'q';
14305                   else
14306                     {
14307                       if (sizeflag & DFLAG)
14308                         *obufp++ = intel_syntax ? 'd' : 'l';
14309                       else
14310                         *obufp++ = 'w';
14311                       used_prefixes |= (prefixes & PREFIX_DATA);
14312                     }
14313                 }
14314             }
14315           break;
14316         case 'U':
14317           if (intel_syntax)
14318             break;
14319           if (address_mode == mode_64bit
14320               && ((sizeflag & DFLAG) || (rex & REX_W)))
14321             {
14322               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14323                 *obufp++ = 'q';
14324               break;
14325             }
14326           /* Fall through.  */
14327           goto case_Q;
14328         case 'Q':
14329           if (l == 0 && len == 1)
14330             {
14331 case_Q:
14332               if (intel_syntax && !alt)
14333                 break;
14334               USED_REX (REX_W);
14335               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14336                 {
14337                   if (rex & REX_W)
14338                     *obufp++ = 'q';
14339                   else
14340                     {
14341                       if (sizeflag & DFLAG)
14342                         *obufp++ = intel_syntax ? 'd' : 'l';
14343                       else
14344                         *obufp++ = 'w';
14345                       used_prefixes |= (prefixes & PREFIX_DATA);
14346                     }
14347                 }
14348             }
14349           else
14350             {
14351               if (l != 1 || len != 2 || last[0] != 'L')
14352                 {
14353                   SAVE_LAST (*p);
14354                   break;
14355                 }
14356               if (intel_syntax
14357                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14358                 break;
14359               if ((rex & REX_W))
14360                 {
14361                   USED_REX (REX_W);
14362                   *obufp++ = 'q';
14363                 }
14364               else
14365                 *obufp++ = 'l';
14366             }
14367           break;
14368         case 'R':
14369           USED_REX (REX_W);
14370           if (rex & REX_W)
14371             *obufp++ = 'q';
14372           else if (sizeflag & DFLAG)
14373             {
14374               if (intel_syntax)
14375                   *obufp++ = 'd';
14376               else
14377                   *obufp++ = 'l';
14378             }
14379           else
14380             *obufp++ = 'w';
14381           if (intel_syntax && !p[1]
14382               && ((rex & REX_W) || (sizeflag & DFLAG)))
14383             *obufp++ = 'e';
14384           if (!(rex & REX_W))
14385             used_prefixes |= (prefixes & PREFIX_DATA);
14386           break;
14387         case 'V':
14388           if (l == 0 && len == 1)
14389             {
14390               if (intel_syntax)
14391                 break;
14392               if (address_mode == mode_64bit
14393                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14394                 {
14395                   if (sizeflag & SUFFIX_ALWAYS)
14396                     *obufp++ = 'q';
14397                   break;
14398                 }
14399             }
14400           else
14401             {
14402               if (l != 1
14403                   || len != 2
14404                   || last[0] != 'L')
14405                 {
14406                   SAVE_LAST (*p);
14407                   break;
14408                 }
14409
14410               if (rex & REX_W)
14411                 {
14412                   *obufp++ = 'a';
14413                   *obufp++ = 'b';
14414                   *obufp++ = 's';
14415                 }
14416             }
14417           /* Fall through.  */
14418           goto case_S;
14419         case 'S':
14420           if (l == 0 && len == 1)
14421             {
14422 case_S:
14423               if (intel_syntax)
14424                 break;
14425               if (sizeflag & SUFFIX_ALWAYS)
14426                 {
14427                   if (rex & REX_W)
14428                     *obufp++ = 'q';
14429                   else
14430                     {
14431                       if (sizeflag & DFLAG)
14432                         *obufp++ = 'l';
14433                       else
14434                         *obufp++ = 'w';
14435                       used_prefixes |= (prefixes & PREFIX_DATA);
14436                     }
14437                 }
14438             }
14439           else
14440             {
14441               if (l != 1
14442                   || len != 2
14443                   || last[0] != 'L')
14444                 {
14445                   SAVE_LAST (*p);
14446                   break;
14447                 }
14448
14449               if (address_mode == mode_64bit
14450                   && !(prefixes & PREFIX_ADDR))
14451                 {
14452                   *obufp++ = 'a';
14453                   *obufp++ = 'b';
14454                   *obufp++ = 's';
14455                 }
14456
14457               goto case_S;
14458             }
14459           break;
14460         case 'X':
14461           if (l != 0 || len != 1)
14462             {
14463               SAVE_LAST (*p);
14464               break;
14465             }
14466           if (need_vex && vex.prefix)
14467             {
14468               if (vex.prefix == DATA_PREFIX_OPCODE)
14469                 *obufp++ = 'd';
14470               else
14471                 *obufp++ = 's';
14472             }
14473           else
14474             {
14475               if (prefixes & PREFIX_DATA)
14476                 *obufp++ = 'd';
14477               else
14478                 *obufp++ = 's';
14479               used_prefixes |= (prefixes & PREFIX_DATA);
14480             }
14481           break;
14482         case 'Y':
14483           if (l == 0 && len == 1)
14484             abort ();
14485           else
14486             {
14487               if (l != 1 || len != 2 || last[0] != 'X')
14488                 {
14489                   SAVE_LAST (*p);
14490                   break;
14491                 }
14492               if (!need_vex)
14493                 abort ();
14494               if (intel_syntax
14495                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14496                 break;
14497               switch (vex.length)
14498                 {
14499                 case 128:
14500                   *obufp++ = 'x';
14501                   break;
14502                 case 256:
14503                   *obufp++ = 'y';
14504                   break;
14505                 case 512:
14506                   if (!vex.evex)
14507                 default:
14508                     abort ();
14509                 }
14510             }
14511           break;
14512         case 'W':
14513           if (l == 0 && len == 1)
14514             {
14515               /* operand size flag for cwtl, cbtw */
14516               USED_REX (REX_W);
14517               if (rex & REX_W)
14518                 {
14519                   if (intel_syntax)
14520                     *obufp++ = 'd';
14521                   else
14522                     *obufp++ = 'l';
14523                 }
14524               else if (sizeflag & DFLAG)
14525                 *obufp++ = 'w';
14526               else
14527                 *obufp++ = 'b';
14528               if (!(rex & REX_W))
14529                 used_prefixes |= (prefixes & PREFIX_DATA);
14530             }
14531           else
14532             {
14533               if (l != 1
14534                   || len != 2
14535                   || (last[0] != 'X'
14536                       && last[0] != 'L'))
14537                 {
14538                   SAVE_LAST (*p);
14539                   break;
14540                 }
14541               if (!need_vex)
14542                 abort ();
14543               if (last[0] == 'X')
14544                 *obufp++ = vex.w ? 'd': 's';
14545               else
14546                 *obufp++ = vex.w ? 'q': 'd';
14547             }
14548           break;
14549         case '^':
14550           if (intel_syntax)
14551             break;
14552           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14553             {
14554               if (sizeflag & DFLAG)
14555                 *obufp++ = 'l';
14556               else
14557                 *obufp++ = 'w';
14558               used_prefixes |= (prefixes & PREFIX_DATA);
14559             }
14560           break;
14561         case '@':
14562           if (intel_syntax)
14563             break;
14564           if (address_mode == mode_64bit
14565               && (isa64 == intel64
14566                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14567               *obufp++ = 'q';
14568           else if ((prefixes & PREFIX_DATA))
14569             {
14570               if (!(sizeflag & DFLAG))
14571                 *obufp++ = 'w';
14572               used_prefixes |= (prefixes & PREFIX_DATA);
14573             }
14574           break;
14575         }
14576       alt = 0;
14577     }
14578   *obufp = 0;
14579   mnemonicendp = obufp;
14580   return 0;
14581 }
14582
14583 static void
14584 oappend (const char *s)
14585 {
14586   obufp = stpcpy (obufp, s);
14587 }
14588
14589 static void
14590 append_seg (void)
14591 {
14592   /* Only print the active segment register.  */
14593   if (!active_seg_prefix)
14594     return;
14595
14596   used_prefixes |= active_seg_prefix;
14597   switch (active_seg_prefix)
14598     {
14599     case PREFIX_CS:
14600       oappend_maybe_intel ("%cs:");
14601       break;
14602     case PREFIX_DS:
14603       oappend_maybe_intel ("%ds:");
14604       break;
14605     case PREFIX_SS:
14606       oappend_maybe_intel ("%ss:");
14607       break;
14608     case PREFIX_ES:
14609       oappend_maybe_intel ("%es:");
14610       break;
14611     case PREFIX_FS:
14612       oappend_maybe_intel ("%fs:");
14613       break;
14614     case PREFIX_GS:
14615       oappend_maybe_intel ("%gs:");
14616       break;
14617     default:
14618       break;
14619     }
14620 }
14621
14622 static void
14623 OP_indirE (int bytemode, int sizeflag)
14624 {
14625   if (!intel_syntax)
14626     oappend ("*");
14627   OP_E (bytemode, sizeflag);
14628 }
14629
14630 static void
14631 print_operand_value (char *buf, int hex, bfd_vma disp)
14632 {
14633   if (address_mode == mode_64bit)
14634     {
14635       if (hex)
14636         {
14637           char tmp[30];
14638           int i;
14639           buf[0] = '0';
14640           buf[1] = 'x';
14641           sprintf_vma (tmp, disp);
14642           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14643           strcpy (buf + 2, tmp + i);
14644         }
14645       else
14646         {
14647           bfd_signed_vma v = disp;
14648           char tmp[30];
14649           int i;
14650           if (v < 0)
14651             {
14652               *(buf++) = '-';
14653               v = -disp;
14654               /* Check for possible overflow on 0x8000000000000000.  */
14655               if (v < 0)
14656                 {
14657                   strcpy (buf, "9223372036854775808");
14658                   return;
14659                 }
14660             }
14661           if (!v)
14662             {
14663               strcpy (buf, "0");
14664               return;
14665             }
14666
14667           i = 0;
14668           tmp[29] = 0;
14669           while (v)
14670             {
14671               tmp[28 - i] = (v % 10) + '0';
14672               v /= 10;
14673               i++;
14674             }
14675           strcpy (buf, tmp + 29 - i);
14676         }
14677     }
14678   else
14679     {
14680       if (hex)
14681         sprintf (buf, "0x%x", (unsigned int) disp);
14682       else
14683         sprintf (buf, "%d", (int) disp);
14684     }
14685 }
14686
14687 /* Put DISP in BUF as signed hex number.  */
14688
14689 static void
14690 print_displacement (char *buf, bfd_vma disp)
14691 {
14692   bfd_signed_vma val = disp;
14693   char tmp[30];
14694   int i, j = 0;
14695
14696   if (val < 0)
14697     {
14698       buf[j++] = '-';
14699       val = -disp;
14700
14701       /* Check for possible overflow.  */
14702       if (val < 0)
14703         {
14704           switch (address_mode)
14705             {
14706             case mode_64bit:
14707               strcpy (buf + j, "0x8000000000000000");
14708               break;
14709             case mode_32bit:
14710               strcpy (buf + j, "0x80000000");
14711               break;
14712             case mode_16bit:
14713               strcpy (buf + j, "0x8000");
14714               break;
14715             }
14716           return;
14717         }
14718     }
14719
14720   buf[j++] = '0';
14721   buf[j++] = 'x';
14722
14723   sprintf_vma (tmp, (bfd_vma) val);
14724   for (i = 0; tmp[i] == '0'; i++)
14725     continue;
14726   if (tmp[i] == '\0')
14727     i--;
14728   strcpy (buf + j, tmp + i);
14729 }
14730
14731 static void
14732 intel_operand_size (int bytemode, int sizeflag)
14733 {
14734   if (vex.evex
14735       && vex.b
14736       && (bytemode == x_mode
14737           || bytemode == evex_half_bcst_xmmq_mode))
14738     {
14739       if (vex.w)
14740         oappend ("QWORD PTR ");
14741       else
14742         oappend ("DWORD PTR ");
14743       return;
14744     }
14745   switch (bytemode)
14746     {
14747     case b_mode:
14748     case b_swap_mode:
14749     case dqb_mode:
14750     case db_mode:
14751       oappend ("BYTE PTR ");
14752       break;
14753     case w_mode:
14754     case dw_mode:
14755     case dqw_mode:
14756       oappend ("WORD PTR ");
14757       break;
14758     case indir_v_mode:
14759       if (address_mode == mode_64bit && isa64 == intel64)
14760         {
14761           oappend ("QWORD PTR ");
14762           break;
14763         }
14764       /* Fall through.  */
14765     case stack_v_mode:
14766       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14767         {
14768           oappend ("QWORD PTR ");
14769           break;
14770         }
14771       /* Fall through.  */
14772     case v_mode:
14773     case v_swap_mode:
14774     case dq_mode:
14775       USED_REX (REX_W);
14776       if (rex & REX_W)
14777         oappend ("QWORD PTR ");
14778       else
14779         {
14780           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14781             oappend ("DWORD PTR ");
14782           else
14783             oappend ("WORD PTR ");
14784           used_prefixes |= (prefixes & PREFIX_DATA);
14785         }
14786       break;
14787     case z_mode:
14788       if ((rex & REX_W) || (sizeflag & DFLAG))
14789         *obufp++ = 'D';
14790       oappend ("WORD PTR ");
14791       if (!(rex & REX_W))
14792         used_prefixes |= (prefixes & PREFIX_DATA);
14793       break;
14794     case a_mode:
14795       if (sizeflag & DFLAG)
14796         oappend ("QWORD PTR ");
14797       else
14798         oappend ("DWORD PTR ");
14799       used_prefixes |= (prefixes & PREFIX_DATA);
14800       break;
14801     case d_mode:
14802     case d_scalar_mode:
14803     case d_scalar_swap_mode:
14804     case d_swap_mode:
14805     case dqd_mode:
14806       oappend ("DWORD PTR ");
14807       break;
14808     case q_mode:
14809     case q_scalar_mode:
14810     case q_scalar_swap_mode:
14811     case q_swap_mode:
14812       oappend ("QWORD PTR ");
14813       break;
14814     case dqa_mode:
14815     case m_mode:
14816       if (address_mode == mode_64bit)
14817         oappend ("QWORD PTR ");
14818       else
14819         oappend ("DWORD PTR ");
14820       break;
14821     case f_mode:
14822       if (sizeflag & DFLAG)
14823         oappend ("FWORD PTR ");
14824       else
14825         oappend ("DWORD PTR ");
14826       used_prefixes |= (prefixes & PREFIX_DATA);
14827       break;
14828     case t_mode:
14829       oappend ("TBYTE PTR ");
14830       break;
14831     case x_mode:
14832     case x_swap_mode:
14833     case evex_x_gscat_mode:
14834     case evex_x_nobcst_mode:
14835     case b_scalar_mode:
14836     case w_scalar_mode:
14837       if (need_vex)
14838         {
14839           switch (vex.length)
14840             {
14841             case 128:
14842               oappend ("XMMWORD PTR ");
14843               break;
14844             case 256:
14845               oappend ("YMMWORD PTR ");
14846               break;
14847             case 512:
14848               oappend ("ZMMWORD PTR ");
14849               break;
14850             default:
14851               abort ();
14852             }
14853         }
14854       else
14855         oappend ("XMMWORD PTR ");
14856       break;
14857     case xmm_mode:
14858       oappend ("XMMWORD PTR ");
14859       break;
14860     case ymm_mode:
14861       oappend ("YMMWORD PTR ");
14862       break;
14863     case xmmq_mode:
14864     case evex_half_bcst_xmmq_mode:
14865       if (!need_vex)
14866         abort ();
14867
14868       switch (vex.length)
14869         {
14870         case 128:
14871           oappend ("QWORD PTR ");
14872           break;
14873         case 256:
14874           oappend ("XMMWORD PTR ");
14875           break;
14876         case 512:
14877           oappend ("YMMWORD PTR ");
14878           break;
14879         default:
14880           abort ();
14881         }
14882       break;
14883     case xmm_mb_mode:
14884       if (!need_vex)
14885         abort ();
14886
14887       switch (vex.length)
14888         {
14889         case 128:
14890         case 256:
14891         case 512:
14892           oappend ("BYTE PTR ");
14893           break;
14894         default:
14895           abort ();
14896         }
14897       break;
14898     case xmm_mw_mode:
14899       if (!need_vex)
14900         abort ();
14901
14902       switch (vex.length)
14903         {
14904         case 128:
14905         case 256:
14906         case 512:
14907           oappend ("WORD PTR ");
14908           break;
14909         default:
14910           abort ();
14911         }
14912       break;
14913     case xmm_md_mode:
14914       if (!need_vex)
14915         abort ();
14916
14917       switch (vex.length)
14918         {
14919         case 128:
14920         case 256:
14921         case 512:
14922           oappend ("DWORD PTR ");
14923           break;
14924         default:
14925           abort ();
14926         }
14927       break;
14928     case xmm_mq_mode:
14929       if (!need_vex)
14930         abort ();
14931
14932       switch (vex.length)
14933         {
14934         case 128:
14935         case 256:
14936         case 512:
14937           oappend ("QWORD PTR ");
14938           break;
14939         default:
14940           abort ();
14941         }
14942       break;
14943     case xmmdw_mode:
14944       if (!need_vex)
14945         abort ();
14946
14947       switch (vex.length)
14948         {
14949         case 128:
14950           oappend ("WORD PTR ");
14951           break;
14952         case 256:
14953           oappend ("DWORD PTR ");
14954           break;
14955         case 512:
14956           oappend ("QWORD PTR ");
14957           break;
14958         default:
14959           abort ();
14960         }
14961       break;
14962     case xmmqd_mode:
14963       if (!need_vex)
14964         abort ();
14965
14966       switch (vex.length)
14967         {
14968         case 128:
14969           oappend ("DWORD PTR ");
14970           break;
14971         case 256:
14972           oappend ("QWORD PTR ");
14973           break;
14974         case 512:
14975           oappend ("XMMWORD PTR ");
14976           break;
14977         default:
14978           abort ();
14979         }
14980       break;
14981     case ymmq_mode:
14982       if (!need_vex)
14983         abort ();
14984
14985       switch (vex.length)
14986         {
14987         case 128:
14988           oappend ("QWORD PTR ");
14989           break;
14990         case 256:
14991           oappend ("YMMWORD PTR ");
14992           break;
14993         case 512:
14994           oappend ("ZMMWORD PTR ");
14995           break;
14996         default:
14997           abort ();
14998         }
14999       break;
15000     case ymmxmm_mode:
15001       if (!need_vex)
15002         abort ();
15003
15004       switch (vex.length)
15005         {
15006         case 128:
15007         case 256:
15008           oappend ("XMMWORD PTR ");
15009           break;
15010         default:
15011           abort ();
15012         }
15013       break;
15014     case o_mode:
15015       oappend ("OWORD PTR ");
15016       break;
15017     case xmm_mdq_mode:
15018     case vex_w_dq_mode:
15019     case vex_scalar_w_dq_mode:
15020       if (!need_vex)
15021         abort ();
15022
15023       if (vex.w)
15024         oappend ("QWORD PTR ");
15025       else
15026         oappend ("DWORD PTR ");
15027       break;
15028     case vex_vsib_d_w_dq_mode:
15029     case vex_vsib_q_w_dq_mode:
15030       if (!need_vex)
15031         abort ();
15032
15033       if (!vex.evex)
15034         {
15035           if (vex.w)
15036             oappend ("QWORD PTR ");
15037           else
15038             oappend ("DWORD PTR ");
15039         }
15040       else
15041         {
15042           switch (vex.length)
15043             {
15044             case 128:
15045               oappend ("XMMWORD PTR ");
15046               break;
15047             case 256:
15048               oappend ("YMMWORD PTR ");
15049               break;
15050             case 512:
15051               oappend ("ZMMWORD PTR ");
15052               break;
15053             default:
15054               abort ();
15055             }
15056         }
15057       break;
15058     case vex_vsib_q_w_d_mode:
15059     case vex_vsib_d_w_d_mode:
15060       if (!need_vex || !vex.evex)
15061         abort ();
15062
15063       switch (vex.length)
15064         {
15065         case 128:
15066           oappend ("QWORD PTR ");
15067           break;
15068         case 256:
15069           oappend ("XMMWORD PTR ");
15070           break;
15071         case 512:
15072           oappend ("YMMWORD PTR ");
15073           break;
15074         default:
15075           abort ();
15076         }
15077
15078       break;
15079     case mask_bd_mode:
15080       if (!need_vex || vex.length != 128)
15081         abort ();
15082       if (vex.w)
15083         oappend ("DWORD PTR ");
15084       else
15085         oappend ("BYTE PTR ");
15086       break;
15087     case mask_mode:
15088       if (!need_vex)
15089         abort ();
15090       if (vex.w)
15091         oappend ("QWORD PTR ");
15092       else
15093         oappend ("WORD PTR ");
15094       break;
15095     case v_bnd_mode:
15096     case v_bndmk_mode:
15097     default:
15098       break;
15099     }
15100 }
15101
15102 static void
15103 OP_E_register (int bytemode, int sizeflag)
15104 {
15105   int reg = modrm.rm;
15106   const char **names;
15107
15108   USED_REX (REX_B);
15109   if ((rex & REX_B))
15110     reg += 8;
15111
15112   if ((sizeflag & SUFFIX_ALWAYS)
15113       && (bytemode == b_swap_mode
15114           || bytemode == bnd_swap_mode
15115           || bytemode == v_swap_mode))
15116     swap_operand ();
15117
15118   switch (bytemode)
15119     {
15120     case b_mode:
15121     case b_swap_mode:
15122       USED_REX (0);
15123       if (rex)
15124         names = names8rex;
15125       else
15126         names = names8;
15127       break;
15128     case w_mode:
15129       names = names16;
15130       break;
15131     case d_mode:
15132     case dw_mode:
15133     case db_mode:
15134       names = names32;
15135       break;
15136     case q_mode:
15137       names = names64;
15138       break;
15139     case m_mode:
15140     case v_bnd_mode:
15141       names = address_mode == mode_64bit ? names64 : names32;
15142       break;
15143     case bnd_mode:
15144     case bnd_swap_mode:
15145       if (reg > 0x3)
15146         {
15147           oappend ("(bad)");
15148           return;
15149         }
15150       names = names_bnd;
15151       break;
15152     case indir_v_mode:
15153       if (address_mode == mode_64bit && isa64 == intel64)
15154         {
15155           names = names64;
15156           break;
15157         }
15158       /* Fall through.  */
15159     case stack_v_mode:
15160       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15161         {
15162           names = names64;
15163           break;
15164         }
15165       bytemode = v_mode;
15166       /* Fall through.  */
15167     case v_mode:
15168     case v_swap_mode:
15169     case dq_mode:
15170     case dqb_mode:
15171     case dqd_mode:
15172     case dqw_mode:
15173     case dqa_mode:
15174       USED_REX (REX_W);
15175       if (rex & REX_W)
15176         names = names64;
15177       else
15178         {
15179           if ((sizeflag & DFLAG)
15180               || (bytemode != v_mode
15181                   && bytemode != v_swap_mode))
15182             names = names32;
15183           else
15184             names = names16;
15185           used_prefixes |= (prefixes & PREFIX_DATA);
15186         }
15187       break;
15188     case va_mode:
15189       names = (address_mode == mode_64bit
15190                ? names64 : names32);
15191       if (!(prefixes & PREFIX_ADDR))
15192         names = (address_mode == mode_16bit
15193                      ? names16 : names);
15194       else
15195         {
15196           /* Remove "addr16/addr32".  */
15197           all_prefixes[last_addr_prefix] = 0;
15198           names = (address_mode != mode_32bit
15199                        ? names32 : names16);
15200           used_prefixes |= PREFIX_ADDR;
15201         }
15202       break;
15203     case mask_bd_mode:
15204     case mask_mode:
15205       if (reg > 0x7)
15206         {
15207           oappend ("(bad)");
15208           return;
15209         }
15210       names = names_mask;
15211       break;
15212     case 0:
15213       return;
15214     default:
15215       oappend (INTERNAL_DISASSEMBLER_ERROR);
15216       return;
15217     }
15218   oappend (names[reg]);
15219 }
15220
15221 static void
15222 OP_E_memory (int bytemode, int sizeflag)
15223 {
15224   bfd_vma disp = 0;
15225   int add = (rex & REX_B) ? 8 : 0;
15226   int riprel = 0;
15227   int shift;
15228
15229   if (vex.evex)
15230     {
15231       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15232       if (vex.b
15233           && bytemode != x_mode
15234           && bytemode != xmmq_mode
15235           && bytemode != evex_half_bcst_xmmq_mode)
15236         {
15237           BadOp ();
15238           return;
15239         }
15240       switch (bytemode)
15241         {
15242         case dqw_mode:
15243         case dw_mode:
15244           shift = 1;
15245           break;
15246         case dqb_mode:
15247         case db_mode:
15248           shift = 0;
15249           break;
15250         case vex_vsib_d_w_dq_mode:
15251         case vex_vsib_d_w_d_mode:
15252         case vex_vsib_q_w_dq_mode:
15253         case vex_vsib_q_w_d_mode:
15254         case evex_x_gscat_mode:
15255         case xmm_mdq_mode:
15256           shift = vex.w ? 3 : 2;
15257           break;
15258         case x_mode:
15259         case evex_half_bcst_xmmq_mode:
15260         case xmmq_mode:
15261           if (vex.b)
15262             {
15263               shift = vex.w ? 3 : 2;
15264               break;
15265             }
15266           /* Fall through.  */
15267         case xmmqd_mode:
15268         case xmmdw_mode:
15269         case ymmq_mode:
15270         case evex_x_nobcst_mode:
15271         case x_swap_mode:
15272           switch (vex.length)
15273             {
15274             case 128:
15275               shift = 4;
15276               break;
15277             case 256:
15278               shift = 5;
15279               break;
15280             case 512:
15281               shift = 6;
15282               break;
15283             default:
15284               abort ();
15285             }
15286           break;
15287         case ymm_mode:
15288           shift = 5;
15289           break;
15290         case xmm_mode:
15291           shift = 4;
15292           break;
15293         case xmm_mq_mode:
15294         case q_mode:
15295         case q_scalar_mode:
15296         case q_swap_mode:
15297         case q_scalar_swap_mode:
15298           shift = 3;
15299           break;
15300         case dqd_mode:
15301         case xmm_md_mode:
15302         case d_mode:
15303         case d_scalar_mode:
15304         case d_swap_mode:
15305         case d_scalar_swap_mode:
15306           shift = 2;
15307           break;
15308         case w_scalar_mode:
15309         case xmm_mw_mode:
15310           shift = 1;
15311           break;
15312         case b_scalar_mode:
15313         case xmm_mb_mode:
15314           shift = 0;
15315           break;
15316         case dqa_mode:
15317           shift = address_mode == mode_64bit ? 3 : 2;
15318           break;
15319         default:
15320           abort ();
15321         }
15322       /* Make necessary corrections to shift for modes that need it.
15323          For these modes we currently have shift 4, 5 or 6 depending on
15324          vex.length (it corresponds to xmmword, ymmword or zmmword
15325          operand).  We might want to make it 3, 4 or 5 (e.g. for
15326          xmmq_mode).  In case of broadcast enabled the corrections
15327          aren't needed, as element size is always 32 or 64 bits.  */
15328       if (!vex.b
15329           && (bytemode == xmmq_mode
15330               || bytemode == evex_half_bcst_xmmq_mode))
15331         shift -= 1;
15332       else if (bytemode == xmmqd_mode)
15333         shift -= 2;
15334       else if (bytemode == xmmdw_mode)
15335         shift -= 3;
15336       else if (bytemode == ymmq_mode && vex.length == 128)
15337         shift -= 1;
15338     }
15339   else
15340     shift = 0;
15341
15342   USED_REX (REX_B);
15343   if (intel_syntax)
15344     intel_operand_size (bytemode, sizeflag);
15345   append_seg ();
15346
15347   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15348     {
15349       /* 32/64 bit address mode */
15350       int havedisp;
15351       int havesib;
15352       int havebase;
15353       int haveindex;
15354       int needindex;
15355       int needaddr32;
15356       int base, rbase;
15357       int vindex = 0;
15358       int scale = 0;
15359       int addr32flag = !((sizeflag & AFLAG)
15360                          || bytemode == v_bnd_mode
15361                          || bytemode == v_bndmk_mode
15362                          || bytemode == bnd_mode
15363                          || bytemode == bnd_swap_mode);
15364       const char **indexes64 = names64;
15365       const char **indexes32 = names32;
15366
15367       havesib = 0;
15368       havebase = 1;
15369       haveindex = 0;
15370       base = modrm.rm;
15371
15372       if (base == 4)
15373         {
15374           havesib = 1;
15375           vindex = sib.index;
15376           USED_REX (REX_X);
15377           if (rex & REX_X)
15378             vindex += 8;
15379           switch (bytemode)
15380             {
15381             case vex_vsib_d_w_dq_mode:
15382             case vex_vsib_d_w_d_mode:
15383             case vex_vsib_q_w_dq_mode:
15384             case vex_vsib_q_w_d_mode:
15385               if (!need_vex)
15386                 abort ();
15387               if (vex.evex)
15388                 {
15389                   if (!vex.v)
15390                     vindex += 16;
15391                 }
15392
15393               haveindex = 1;
15394               switch (vex.length)
15395                 {
15396                 case 128:
15397                   indexes64 = indexes32 = names_xmm;
15398                   break;
15399                 case 256:
15400                   if (!vex.w
15401                       || bytemode == vex_vsib_q_w_dq_mode
15402                       || bytemode == vex_vsib_q_w_d_mode)
15403                     indexes64 = indexes32 = names_ymm;
15404                   else
15405                     indexes64 = indexes32 = names_xmm;
15406                   break;
15407                 case 512:
15408                   if (!vex.w
15409                       || bytemode == vex_vsib_q_w_dq_mode
15410                       || bytemode == vex_vsib_q_w_d_mode)
15411                     indexes64 = indexes32 = names_zmm;
15412                   else
15413                     indexes64 = indexes32 = names_ymm;
15414                   break;
15415                 default:
15416                   abort ();
15417                 }
15418               break;
15419             default:
15420               haveindex = vindex != 4;
15421               break;
15422             }
15423           scale = sib.scale;
15424           base = sib.base;
15425           codep++;
15426         }
15427       rbase = base + add;
15428
15429       switch (modrm.mod)
15430         {
15431         case 0:
15432           if (base == 5)
15433             {
15434               havebase = 0;
15435               if (address_mode == mode_64bit && !havesib)
15436                 riprel = 1;
15437               disp = get32s ();
15438               if (riprel && bytemode == v_bndmk_mode)
15439                 {
15440                   oappend ("(bad)");
15441                   return;
15442                 }
15443             }
15444           break;
15445         case 1:
15446           FETCH_DATA (the_info, codep + 1);
15447           disp = *codep++;
15448           if ((disp & 0x80) != 0)
15449             disp -= 0x100;
15450           if (vex.evex && shift > 0)
15451             disp <<= shift;
15452           break;
15453         case 2:
15454           disp = get32s ();
15455           break;
15456         }
15457
15458       needindex = 0;
15459       needaddr32 = 0;
15460       if (havesib
15461           && !havebase
15462           && !haveindex
15463           && address_mode != mode_16bit)
15464         {
15465           if (address_mode == mode_64bit)
15466             {
15467               /* Display eiz instead of addr32.  */
15468               needindex = addr32flag;
15469               needaddr32 = 1;
15470             }
15471           else
15472             {
15473               /* In 32-bit mode, we need index register to tell [offset]
15474                  from [eiz*1 + offset].  */
15475               needindex = 1;
15476             }
15477         }
15478
15479       havedisp = (havebase
15480                   || needindex
15481                   || (havesib && (haveindex || scale != 0)));
15482
15483       if (!intel_syntax)
15484         if (modrm.mod != 0 || base == 5)
15485           {
15486             if (havedisp || riprel)
15487               print_displacement (scratchbuf, disp);
15488             else
15489               print_operand_value (scratchbuf, 1, disp);
15490             oappend (scratchbuf);
15491             if (riprel)
15492               {
15493                 set_op (disp, 1);
15494                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15495               }
15496           }
15497
15498       if ((havebase || haveindex || needaddr32 || riprel)
15499           && (bytemode != v_bnd_mode)
15500           && (bytemode != v_bndmk_mode)
15501           && (bytemode != bnd_mode)
15502           && (bytemode != bnd_swap_mode))
15503         used_prefixes |= PREFIX_ADDR;
15504
15505       if (havedisp || (intel_syntax && riprel))
15506         {
15507           *obufp++ = open_char;
15508           if (intel_syntax && riprel)
15509             {
15510               set_op (disp, 1);
15511               oappend (!addr32flag ? "rip" : "eip");
15512             }
15513           *obufp = '\0';
15514           if (havebase)
15515             oappend (address_mode == mode_64bit && !addr32flag
15516                      ? names64[rbase] : names32[rbase]);
15517           if (havesib)
15518             {
15519               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15520                  print index to tell base + index from base.  */
15521               if (scale != 0
15522                   || needindex
15523                   || haveindex
15524                   || (havebase && base != ESP_REG_NUM))
15525                 {
15526                   if (!intel_syntax || havebase)
15527                     {
15528                       *obufp++ = separator_char;
15529                       *obufp = '\0';
15530                     }
15531                   if (haveindex)
15532                     oappend (address_mode == mode_64bit && !addr32flag
15533                              ? indexes64[vindex] : indexes32[vindex]);
15534                   else
15535                     oappend (address_mode == mode_64bit && !addr32flag
15536                              ? index64 : index32);
15537
15538                   *obufp++ = scale_char;
15539                   *obufp = '\0';
15540                   sprintf (scratchbuf, "%d", 1 << scale);
15541                   oappend (scratchbuf);
15542                 }
15543             }
15544           if (intel_syntax
15545               && (disp || modrm.mod != 0 || base == 5))
15546             {
15547               if (!havedisp || (bfd_signed_vma) disp >= 0)
15548                 {
15549                   *obufp++ = '+';
15550                   *obufp = '\0';
15551                 }
15552               else if (modrm.mod != 1 && disp != -disp)
15553                 {
15554                   *obufp++ = '-';
15555                   *obufp = '\0';
15556                   disp = - (bfd_signed_vma) disp;
15557                 }
15558
15559               if (havedisp)
15560                 print_displacement (scratchbuf, disp);
15561               else
15562                 print_operand_value (scratchbuf, 1, disp);
15563               oappend (scratchbuf);
15564             }
15565
15566           *obufp++ = close_char;
15567           *obufp = '\0';
15568         }
15569       else if (intel_syntax)
15570         {
15571           if (modrm.mod != 0 || base == 5)
15572             {
15573               if (!active_seg_prefix)
15574                 {
15575                   oappend (names_seg[ds_reg - es_reg]);
15576                   oappend (":");
15577                 }
15578               print_operand_value (scratchbuf, 1, disp);
15579               oappend (scratchbuf);
15580             }
15581         }
15582     }
15583   else
15584     {
15585       /* 16 bit address mode */
15586       used_prefixes |= prefixes & PREFIX_ADDR;
15587       switch (modrm.mod)
15588         {
15589         case 0:
15590           if (modrm.rm == 6)
15591             {
15592               disp = get16 ();
15593               if ((disp & 0x8000) != 0)
15594                 disp -= 0x10000;
15595             }
15596           break;
15597         case 1:
15598           FETCH_DATA (the_info, codep + 1);
15599           disp = *codep++;
15600           if ((disp & 0x80) != 0)
15601             disp -= 0x100;
15602           if (vex.evex && shift > 0)
15603             disp <<= shift;
15604           break;
15605         case 2:
15606           disp = get16 ();
15607           if ((disp & 0x8000) != 0)
15608             disp -= 0x10000;
15609           break;
15610         }
15611
15612       if (!intel_syntax)
15613         if (modrm.mod != 0 || modrm.rm == 6)
15614           {
15615             print_displacement (scratchbuf, disp);
15616             oappend (scratchbuf);
15617           }
15618
15619       if (modrm.mod != 0 || modrm.rm != 6)
15620         {
15621           *obufp++ = open_char;
15622           *obufp = '\0';
15623           oappend (index16[modrm.rm]);
15624           if (intel_syntax
15625               && (disp || modrm.mod != 0 || modrm.rm == 6))
15626             {
15627               if ((bfd_signed_vma) disp >= 0)
15628                 {
15629                   *obufp++ = '+';
15630                   *obufp = '\0';
15631                 }
15632               else if (modrm.mod != 1)
15633                 {
15634                   *obufp++ = '-';
15635                   *obufp = '\0';
15636                   disp = - (bfd_signed_vma) disp;
15637                 }
15638
15639               print_displacement (scratchbuf, disp);
15640               oappend (scratchbuf);
15641             }
15642
15643           *obufp++ = close_char;
15644           *obufp = '\0';
15645         }
15646       else if (intel_syntax)
15647         {
15648           if (!active_seg_prefix)
15649             {
15650               oappend (names_seg[ds_reg - es_reg]);
15651               oappend (":");
15652             }
15653           print_operand_value (scratchbuf, 1, disp & 0xffff);
15654           oappend (scratchbuf);
15655         }
15656     }
15657   if (vex.evex && vex.b
15658       && (bytemode == x_mode
15659           || bytemode == xmmq_mode
15660           || bytemode == evex_half_bcst_xmmq_mode))
15661     {
15662       if (vex.w
15663           || bytemode == xmmq_mode
15664           || bytemode == evex_half_bcst_xmmq_mode)
15665         {
15666           switch (vex.length)
15667             {
15668             case 128:
15669               oappend ("{1to2}");
15670               break;
15671             case 256:
15672               oappend ("{1to4}");
15673               break;
15674             case 512:
15675               oappend ("{1to8}");
15676               break;
15677             default:
15678               abort ();
15679             }
15680         }
15681       else
15682         {
15683           switch (vex.length)
15684             {
15685             case 128:
15686               oappend ("{1to4}");
15687               break;
15688             case 256:
15689               oappend ("{1to8}");
15690               break;
15691             case 512:
15692               oappend ("{1to16}");
15693               break;
15694             default:
15695               abort ();
15696             }
15697         }
15698     }
15699 }
15700
15701 static void
15702 OP_E (int bytemode, int sizeflag)
15703 {
15704   /* Skip mod/rm byte.  */
15705   MODRM_CHECK;
15706   codep++;
15707
15708   if (modrm.mod == 3)
15709     OP_E_register (bytemode, sizeflag);
15710   else
15711     OP_E_memory (bytemode, sizeflag);
15712 }
15713
15714 static void
15715 OP_G (int bytemode, int sizeflag)
15716 {
15717   int add = 0;
15718   const char **names;
15719   USED_REX (REX_R);
15720   if (rex & REX_R)
15721     add += 8;
15722   switch (bytemode)
15723     {
15724     case b_mode:
15725       USED_REX (0);
15726       if (rex)
15727         oappend (names8rex[modrm.reg + add]);
15728       else
15729         oappend (names8[modrm.reg + add]);
15730       break;
15731     case w_mode:
15732       oappend (names16[modrm.reg + add]);
15733       break;
15734     case d_mode:
15735     case db_mode:
15736     case dw_mode:
15737       oappend (names32[modrm.reg + add]);
15738       break;
15739     case q_mode:
15740       oappend (names64[modrm.reg + add]);
15741       break;
15742     case bnd_mode:
15743       if (modrm.reg > 0x3)
15744         {
15745           oappend ("(bad)");
15746           return;
15747         }
15748       oappend (names_bnd[modrm.reg]);
15749       break;
15750     case v_mode:
15751     case dq_mode:
15752     case dqb_mode:
15753     case dqd_mode:
15754     case dqw_mode:
15755       USED_REX (REX_W);
15756       if (rex & REX_W)
15757         oappend (names64[modrm.reg + add]);
15758       else
15759         {
15760           if ((sizeflag & DFLAG) || bytemode != v_mode)
15761             oappend (names32[modrm.reg + add]);
15762           else
15763             oappend (names16[modrm.reg + add]);
15764           used_prefixes |= (prefixes & PREFIX_DATA);
15765         }
15766       break;
15767     case va_mode:
15768       names = (address_mode == mode_64bit
15769                ? names64 : names32);
15770       if (!(prefixes & PREFIX_ADDR))
15771         {
15772           if (address_mode == mode_16bit)
15773             names = names16;
15774         }
15775       else
15776         {
15777           /* Remove "addr16/addr32".  */
15778           all_prefixes[last_addr_prefix] = 0;
15779           names = (address_mode != mode_32bit
15780                        ? names32 : names16);
15781           used_prefixes |= PREFIX_ADDR;
15782         }
15783       oappend (names[modrm.reg + add]);
15784       break;
15785     case m_mode:
15786       if (address_mode == mode_64bit)
15787         oappend (names64[modrm.reg + add]);
15788       else
15789         oappend (names32[modrm.reg + add]);
15790       break;
15791     case mask_bd_mode:
15792     case mask_mode:
15793       if ((modrm.reg + add) > 0x7)
15794         {
15795           oappend ("(bad)");
15796           return;
15797         }
15798       oappend (names_mask[modrm.reg + add]);
15799       break;
15800     default:
15801       oappend (INTERNAL_DISASSEMBLER_ERROR);
15802       break;
15803     }
15804 }
15805
15806 static bfd_vma
15807 get64 (void)
15808 {
15809   bfd_vma x;
15810 #ifdef BFD64
15811   unsigned int a;
15812   unsigned int b;
15813
15814   FETCH_DATA (the_info, codep + 8);
15815   a = *codep++ & 0xff;
15816   a |= (*codep++ & 0xff) << 8;
15817   a |= (*codep++ & 0xff) << 16;
15818   a |= (*codep++ & 0xffu) << 24;
15819   b = *codep++ & 0xff;
15820   b |= (*codep++ & 0xff) << 8;
15821   b |= (*codep++ & 0xff) << 16;
15822   b |= (*codep++ & 0xffu) << 24;
15823   x = a + ((bfd_vma) b << 32);
15824 #else
15825   abort ();
15826   x = 0;
15827 #endif
15828   return x;
15829 }
15830
15831 static bfd_signed_vma
15832 get32 (void)
15833 {
15834   bfd_signed_vma x = 0;
15835
15836   FETCH_DATA (the_info, codep + 4);
15837   x = *codep++ & (bfd_signed_vma) 0xff;
15838   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15839   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15840   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15841   return x;
15842 }
15843
15844 static bfd_signed_vma
15845 get32s (void)
15846 {
15847   bfd_signed_vma x = 0;
15848
15849   FETCH_DATA (the_info, codep + 4);
15850   x = *codep++ & (bfd_signed_vma) 0xff;
15851   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15852   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15853   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15854
15855   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15856
15857   return x;
15858 }
15859
15860 static int
15861 get16 (void)
15862 {
15863   int x = 0;
15864
15865   FETCH_DATA (the_info, codep + 2);
15866   x = *codep++ & 0xff;
15867   x |= (*codep++ & 0xff) << 8;
15868   return x;
15869 }
15870
15871 static void
15872 set_op (bfd_vma op, int riprel)
15873 {
15874   op_index[op_ad] = op_ad;
15875   if (address_mode == mode_64bit)
15876     {
15877       op_address[op_ad] = op;
15878       op_riprel[op_ad] = riprel;
15879     }
15880   else
15881     {
15882       /* Mask to get a 32-bit address.  */
15883       op_address[op_ad] = op & 0xffffffff;
15884       op_riprel[op_ad] = riprel & 0xffffffff;
15885     }
15886 }
15887
15888 static void
15889 OP_REG (int code, int sizeflag)
15890 {
15891   const char *s;
15892   int add;
15893
15894   switch (code)
15895     {
15896     case es_reg: case ss_reg: case cs_reg:
15897     case ds_reg: case fs_reg: case gs_reg:
15898       oappend (names_seg[code - es_reg]);
15899       return;
15900     }
15901
15902   USED_REX (REX_B);
15903   if (rex & REX_B)
15904     add = 8;
15905   else
15906     add = 0;
15907
15908   switch (code)
15909     {
15910     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15911     case sp_reg: case bp_reg: case si_reg: case di_reg:
15912       s = names16[code - ax_reg + add];
15913       break;
15914     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15915     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15916       USED_REX (0);
15917       if (rex)
15918         s = names8rex[code - al_reg + add];
15919       else
15920         s = names8[code - al_reg];
15921       break;
15922     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15923     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15924       if (address_mode == mode_64bit
15925           && ((sizeflag & DFLAG) || (rex & REX_W)))
15926         {
15927           s = names64[code - rAX_reg + add];
15928           break;
15929         }
15930       code += eAX_reg - rAX_reg;
15931       /* Fall through.  */
15932     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15933     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15934       USED_REX (REX_W);
15935       if (rex & REX_W)
15936         s = names64[code - eAX_reg + add];
15937       else
15938         {
15939           if (sizeflag & DFLAG)
15940             s = names32[code - eAX_reg + add];
15941           else
15942             s = names16[code - eAX_reg + add];
15943           used_prefixes |= (prefixes & PREFIX_DATA);
15944         }
15945       break;
15946     default:
15947       s = INTERNAL_DISASSEMBLER_ERROR;
15948       break;
15949     }
15950   oappend (s);
15951 }
15952
15953 static void
15954 OP_IMREG (int code, int sizeflag)
15955 {
15956   const char *s;
15957
15958   switch (code)
15959     {
15960     case indir_dx_reg:
15961       if (intel_syntax)
15962         s = "dx";
15963       else
15964         s = "(%dx)";
15965       break;
15966     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15967     case sp_reg: case bp_reg: case si_reg: case di_reg:
15968       s = names16[code - ax_reg];
15969       break;
15970     case es_reg: case ss_reg: case cs_reg:
15971     case ds_reg: case fs_reg: case gs_reg:
15972       s = names_seg[code - es_reg];
15973       break;
15974     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15975     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15976       USED_REX (0);
15977       if (rex)
15978         s = names8rex[code - al_reg];
15979       else
15980         s = names8[code - al_reg];
15981       break;
15982     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15983     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15984       USED_REX (REX_W);
15985       if (rex & REX_W)
15986         s = names64[code - eAX_reg];
15987       else
15988         {
15989           if (sizeflag & DFLAG)
15990             s = names32[code - eAX_reg];
15991           else
15992             s = names16[code - eAX_reg];
15993           used_prefixes |= (prefixes & PREFIX_DATA);
15994         }
15995       break;
15996     case z_mode_ax_reg:
15997       if ((rex & REX_W) || (sizeflag & DFLAG))
15998         s = *names32;
15999       else
16000         s = *names16;
16001       if (!(rex & REX_W))
16002         used_prefixes |= (prefixes & PREFIX_DATA);
16003       break;
16004     default:
16005       s = INTERNAL_DISASSEMBLER_ERROR;
16006       break;
16007     }
16008   oappend (s);
16009 }
16010
16011 static void
16012 OP_I (int bytemode, int sizeflag)
16013 {
16014   bfd_signed_vma op;
16015   bfd_signed_vma mask = -1;
16016
16017   switch (bytemode)
16018     {
16019     case b_mode:
16020       FETCH_DATA (the_info, codep + 1);
16021       op = *codep++;
16022       mask = 0xff;
16023       break;
16024     case q_mode:
16025       if (address_mode == mode_64bit)
16026         {
16027           op = get32s ();
16028           break;
16029         }
16030       /* Fall through.  */
16031     case v_mode:
16032       USED_REX (REX_W);
16033       if (rex & REX_W)
16034         op = get32s ();
16035       else
16036         {
16037           if (sizeflag & DFLAG)
16038             {
16039               op = get32 ();
16040               mask = 0xffffffff;
16041             }
16042           else
16043             {
16044               op = get16 ();
16045               mask = 0xfffff;
16046             }
16047           used_prefixes |= (prefixes & PREFIX_DATA);
16048         }
16049       break;
16050     case w_mode:
16051       mask = 0xfffff;
16052       op = get16 ();
16053       break;
16054     case const_1_mode:
16055       if (intel_syntax)
16056         oappend ("1");
16057       return;
16058     default:
16059       oappend (INTERNAL_DISASSEMBLER_ERROR);
16060       return;
16061     }
16062
16063   op &= mask;
16064   scratchbuf[0] = '$';
16065   print_operand_value (scratchbuf + 1, 1, op);
16066   oappend_maybe_intel (scratchbuf);
16067   scratchbuf[0] = '\0';
16068 }
16069
16070 static void
16071 OP_I64 (int bytemode, int sizeflag)
16072 {
16073   bfd_signed_vma op;
16074   bfd_signed_vma mask = -1;
16075
16076   if (address_mode != mode_64bit)
16077     {
16078       OP_I (bytemode, sizeflag);
16079       return;
16080     }
16081
16082   switch (bytemode)
16083     {
16084     case b_mode:
16085       FETCH_DATA (the_info, codep + 1);
16086       op = *codep++;
16087       mask = 0xff;
16088       break;
16089     case v_mode:
16090       USED_REX (REX_W);
16091       if (rex & REX_W)
16092         op = get64 ();
16093       else
16094         {
16095           if (sizeflag & DFLAG)
16096             {
16097               op = get32 ();
16098               mask = 0xffffffff;
16099             }
16100           else
16101             {
16102               op = get16 ();
16103               mask = 0xfffff;
16104             }
16105           used_prefixes |= (prefixes & PREFIX_DATA);
16106         }
16107       break;
16108     case w_mode:
16109       mask = 0xfffff;
16110       op = get16 ();
16111       break;
16112     default:
16113       oappend (INTERNAL_DISASSEMBLER_ERROR);
16114       return;
16115     }
16116
16117   op &= mask;
16118   scratchbuf[0] = '$';
16119   print_operand_value (scratchbuf + 1, 1, op);
16120   oappend_maybe_intel (scratchbuf);
16121   scratchbuf[0] = '\0';
16122 }
16123
16124 static void
16125 OP_sI (int bytemode, int sizeflag)
16126 {
16127   bfd_signed_vma op;
16128
16129   switch (bytemode)
16130     {
16131     case b_mode:
16132     case b_T_mode:
16133       FETCH_DATA (the_info, codep + 1);
16134       op = *codep++;
16135       if ((op & 0x80) != 0)
16136         op -= 0x100;
16137       if (bytemode == b_T_mode)
16138         {
16139           if (address_mode != mode_64bit
16140               || !((sizeflag & DFLAG) || (rex & REX_W)))
16141             {
16142               /* The operand-size prefix is overridden by a REX prefix.  */
16143               if ((sizeflag & DFLAG) || (rex & REX_W))
16144                 op &= 0xffffffff;
16145               else
16146                 op &= 0xffff;
16147           }
16148         }
16149       else
16150         {
16151           if (!(rex & REX_W))
16152             {
16153               if (sizeflag & DFLAG)
16154                 op &= 0xffffffff;
16155               else
16156                 op &= 0xffff;
16157             }
16158         }
16159       break;
16160     case v_mode:
16161       /* The operand-size prefix is overridden by a REX prefix.  */
16162       if ((sizeflag & DFLAG) || (rex & REX_W))
16163         op = get32s ();
16164       else
16165         op = get16 ();
16166       break;
16167     default:
16168       oappend (INTERNAL_DISASSEMBLER_ERROR);
16169       return;
16170     }
16171
16172   scratchbuf[0] = '$';
16173   print_operand_value (scratchbuf + 1, 1, op);
16174   oappend_maybe_intel (scratchbuf);
16175 }
16176
16177 static void
16178 OP_J (int bytemode, int sizeflag)
16179 {
16180   bfd_vma disp;
16181   bfd_vma mask = -1;
16182   bfd_vma segment = 0;
16183
16184   switch (bytemode)
16185     {
16186     case b_mode:
16187       FETCH_DATA (the_info, codep + 1);
16188       disp = *codep++;
16189       if ((disp & 0x80) != 0)
16190         disp -= 0x100;
16191       break;
16192     case v_mode:
16193       if (isa64 == amd64)
16194         USED_REX (REX_W);
16195       if ((sizeflag & DFLAG)
16196           || (address_mode == mode_64bit
16197               && (isa64 != amd64 || (rex & REX_W))))
16198         disp = get32s ();
16199       else
16200         {
16201           disp = get16 ();
16202           if ((disp & 0x8000) != 0)
16203             disp -= 0x10000;
16204           /* In 16bit mode, address is wrapped around at 64k within
16205              the same segment.  Otherwise, a data16 prefix on a jump
16206              instruction means that the pc is masked to 16 bits after
16207              the displacement is added!  */
16208           mask = 0xffff;
16209           if ((prefixes & PREFIX_DATA) == 0)
16210             segment = ((start_pc + (codep - start_codep))
16211                        & ~((bfd_vma) 0xffff));
16212         }
16213       if (address_mode != mode_64bit
16214           || (isa64 == amd64 && !(rex & REX_W)))
16215         used_prefixes |= (prefixes & PREFIX_DATA);
16216       break;
16217     default:
16218       oappend (INTERNAL_DISASSEMBLER_ERROR);
16219       return;
16220     }
16221   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16222   set_op (disp, 0);
16223   print_operand_value (scratchbuf, 1, disp);
16224   oappend (scratchbuf);
16225 }
16226
16227 static void
16228 OP_SEG (int bytemode, int sizeflag)
16229 {
16230   if (bytemode == w_mode)
16231     oappend (names_seg[modrm.reg]);
16232   else
16233     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16234 }
16235
16236 static void
16237 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16238 {
16239   int seg, offset;
16240
16241   if (sizeflag & DFLAG)
16242     {
16243       offset = get32 ();
16244       seg = get16 ();
16245     }
16246   else
16247     {
16248       offset = get16 ();
16249       seg = get16 ();
16250     }
16251   used_prefixes |= (prefixes & PREFIX_DATA);
16252   if (intel_syntax)
16253     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16254   else
16255     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16256   oappend (scratchbuf);
16257 }
16258
16259 static void
16260 OP_OFF (int bytemode, int sizeflag)
16261 {
16262   bfd_vma off;
16263
16264   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16265     intel_operand_size (bytemode, sizeflag);
16266   append_seg ();
16267
16268   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16269     off = get32 ();
16270   else
16271     off = get16 ();
16272
16273   if (intel_syntax)
16274     {
16275       if (!active_seg_prefix)
16276         {
16277           oappend (names_seg[ds_reg - es_reg]);
16278           oappend (":");
16279         }
16280     }
16281   print_operand_value (scratchbuf, 1, off);
16282   oappend (scratchbuf);
16283 }
16284
16285 static void
16286 OP_OFF64 (int bytemode, int sizeflag)
16287 {
16288   bfd_vma off;
16289
16290   if (address_mode != mode_64bit
16291       || (prefixes & PREFIX_ADDR))
16292     {
16293       OP_OFF (bytemode, sizeflag);
16294       return;
16295     }
16296
16297   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16298     intel_operand_size (bytemode, sizeflag);
16299   append_seg ();
16300
16301   off = get64 ();
16302
16303   if (intel_syntax)
16304     {
16305       if (!active_seg_prefix)
16306         {
16307           oappend (names_seg[ds_reg - es_reg]);
16308           oappend (":");
16309         }
16310     }
16311   print_operand_value (scratchbuf, 1, off);
16312   oappend (scratchbuf);
16313 }
16314
16315 static void
16316 ptr_reg (int code, int sizeflag)
16317 {
16318   const char *s;
16319
16320   *obufp++ = open_char;
16321   used_prefixes |= (prefixes & PREFIX_ADDR);
16322   if (address_mode == mode_64bit)
16323     {
16324       if (!(sizeflag & AFLAG))
16325         s = names32[code - eAX_reg];
16326       else
16327         s = names64[code - eAX_reg];
16328     }
16329   else if (sizeflag & AFLAG)
16330     s = names32[code - eAX_reg];
16331   else
16332     s = names16[code - eAX_reg];
16333   oappend (s);
16334   *obufp++ = close_char;
16335   *obufp = 0;
16336 }
16337
16338 static void
16339 OP_ESreg (int code, int sizeflag)
16340 {
16341   if (intel_syntax)
16342     {
16343       switch (codep[-1])
16344         {
16345         case 0x6d:      /* insw/insl */
16346           intel_operand_size (z_mode, sizeflag);
16347           break;
16348         case 0xa5:      /* movsw/movsl/movsq */
16349         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16350         case 0xab:      /* stosw/stosl */
16351         case 0xaf:      /* scasw/scasl */
16352           intel_operand_size (v_mode, sizeflag);
16353           break;
16354         default:
16355           intel_operand_size (b_mode, sizeflag);
16356         }
16357     }
16358   oappend_maybe_intel ("%es:");
16359   ptr_reg (code, sizeflag);
16360 }
16361
16362 static void
16363 OP_DSreg (int code, int sizeflag)
16364 {
16365   if (intel_syntax)
16366     {
16367       switch (codep[-1])
16368         {
16369         case 0x6f:      /* outsw/outsl */
16370           intel_operand_size (z_mode, sizeflag);
16371           break;
16372         case 0xa5:      /* movsw/movsl/movsq */
16373         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16374         case 0xad:      /* lodsw/lodsl/lodsq */
16375           intel_operand_size (v_mode, sizeflag);
16376           break;
16377         default:
16378           intel_operand_size (b_mode, sizeflag);
16379         }
16380     }
16381   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16382      default segment register DS is printed.  */
16383   if (!active_seg_prefix)
16384     active_seg_prefix = PREFIX_DS;
16385   append_seg ();
16386   ptr_reg (code, sizeflag);
16387 }
16388
16389 static void
16390 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16391 {
16392   int add;
16393   if (rex & REX_R)
16394     {
16395       USED_REX (REX_R);
16396       add = 8;
16397     }
16398   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16399     {
16400       all_prefixes[last_lock_prefix] = 0;
16401       used_prefixes |= PREFIX_LOCK;
16402       add = 8;
16403     }
16404   else
16405     add = 0;
16406   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16407   oappend_maybe_intel (scratchbuf);
16408 }
16409
16410 static void
16411 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16412 {
16413   int add;
16414   USED_REX (REX_R);
16415   if (rex & REX_R)
16416     add = 8;
16417   else
16418     add = 0;
16419   if (intel_syntax)
16420     sprintf (scratchbuf, "db%d", modrm.reg + add);
16421   else
16422     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16423   oappend (scratchbuf);
16424 }
16425
16426 static void
16427 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16428 {
16429   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16430   oappend_maybe_intel (scratchbuf);
16431 }
16432
16433 static void
16434 OP_R (int bytemode, int sizeflag)
16435 {
16436   /* Skip mod/rm byte.  */
16437   MODRM_CHECK;
16438   codep++;
16439   OP_E_register (bytemode, sizeflag);
16440 }
16441
16442 static void
16443 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16444 {
16445   int reg = modrm.reg;
16446   const char **names;
16447
16448   used_prefixes |= (prefixes & PREFIX_DATA);
16449   if (prefixes & PREFIX_DATA)
16450     {
16451       names = names_xmm;
16452       USED_REX (REX_R);
16453       if (rex & REX_R)
16454         reg += 8;
16455     }
16456   else
16457     names = names_mm;
16458   oappend (names[reg]);
16459 }
16460
16461 static void
16462 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16463 {
16464   int reg = modrm.reg;
16465   const char **names;
16466
16467   USED_REX (REX_R);
16468   if (rex & REX_R)
16469     reg += 8;
16470   if (vex.evex)
16471     {
16472       if (!vex.r)
16473         reg += 16;
16474     }
16475
16476   if (need_vex
16477       && bytemode != xmm_mode
16478       && bytemode != xmmq_mode
16479       && bytemode != evex_half_bcst_xmmq_mode
16480       && bytemode != ymm_mode
16481       && bytemode != scalar_mode)
16482     {
16483       switch (vex.length)
16484         {
16485         case 128:
16486           names = names_xmm;
16487           break;
16488         case 256:
16489           if (vex.w
16490               || (bytemode != vex_vsib_q_w_dq_mode
16491                   && bytemode != vex_vsib_q_w_d_mode))
16492             names = names_ymm;
16493           else
16494             names = names_xmm;
16495           break;
16496         case 512:
16497           names = names_zmm;
16498           break;
16499         default:
16500           abort ();
16501         }
16502     }
16503   else if (bytemode == xmmq_mode
16504            || bytemode == evex_half_bcst_xmmq_mode)
16505     {
16506       switch (vex.length)
16507         {
16508         case 128:
16509         case 256:
16510           names = names_xmm;
16511           break;
16512         case 512:
16513           names = names_ymm;
16514           break;
16515         default:
16516           abort ();
16517         }
16518     }
16519   else if (bytemode == ymm_mode)
16520     names = names_ymm;
16521   else
16522     names = names_xmm;
16523   oappend (names[reg]);
16524 }
16525
16526 static void
16527 OP_EM (int bytemode, int sizeflag)
16528 {
16529   int reg;
16530   const char **names;
16531
16532   if (modrm.mod != 3)
16533     {
16534       if (intel_syntax
16535           && (bytemode == v_mode || bytemode == v_swap_mode))
16536         {
16537           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16538           used_prefixes |= (prefixes & PREFIX_DATA);
16539         }
16540       OP_E (bytemode, sizeflag);
16541       return;
16542     }
16543
16544   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16545     swap_operand ();
16546
16547   /* Skip mod/rm byte.  */
16548   MODRM_CHECK;
16549   codep++;
16550   used_prefixes |= (prefixes & PREFIX_DATA);
16551   reg = modrm.rm;
16552   if (prefixes & PREFIX_DATA)
16553     {
16554       names = names_xmm;
16555       USED_REX (REX_B);
16556       if (rex & REX_B)
16557         reg += 8;
16558     }
16559   else
16560     names = names_mm;
16561   oappend (names[reg]);
16562 }
16563
16564 /* cvt* are the only instructions in sse2 which have
16565    both SSE and MMX operands and also have 0x66 prefix
16566    in their opcode. 0x66 was originally used to differentiate
16567    between SSE and MMX instruction(operands). So we have to handle the
16568    cvt* separately using OP_EMC and OP_MXC */
16569 static void
16570 OP_EMC (int bytemode, int sizeflag)
16571 {
16572   if (modrm.mod != 3)
16573     {
16574       if (intel_syntax && bytemode == v_mode)
16575         {
16576           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16577           used_prefixes |= (prefixes & PREFIX_DATA);
16578         }
16579       OP_E (bytemode, sizeflag);
16580       return;
16581     }
16582
16583   /* Skip mod/rm byte.  */
16584   MODRM_CHECK;
16585   codep++;
16586   used_prefixes |= (prefixes & PREFIX_DATA);
16587   oappend (names_mm[modrm.rm]);
16588 }
16589
16590 static void
16591 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16592 {
16593   used_prefixes |= (prefixes & PREFIX_DATA);
16594   oappend (names_mm[modrm.reg]);
16595 }
16596
16597 static void
16598 OP_EX (int bytemode, int sizeflag)
16599 {
16600   int reg;
16601   const char **names;
16602
16603   /* Skip mod/rm byte.  */
16604   MODRM_CHECK;
16605   codep++;
16606
16607   if (modrm.mod != 3)
16608     {
16609       OP_E_memory (bytemode, sizeflag);
16610       return;
16611     }
16612
16613   reg = modrm.rm;
16614   USED_REX (REX_B);
16615   if (rex & REX_B)
16616     reg += 8;
16617   if (vex.evex)
16618     {
16619       USED_REX (REX_X);
16620       if ((rex & REX_X))
16621         reg += 16;
16622     }
16623
16624   if ((sizeflag & SUFFIX_ALWAYS)
16625       && (bytemode == x_swap_mode
16626           || bytemode == d_swap_mode
16627           || bytemode == d_scalar_swap_mode
16628           || bytemode == q_swap_mode
16629           || bytemode == q_scalar_swap_mode))
16630     swap_operand ();
16631
16632   if (need_vex
16633       && bytemode != xmm_mode
16634       && bytemode != xmmdw_mode
16635       && bytemode != xmmqd_mode
16636       && bytemode != xmm_mb_mode
16637       && bytemode != xmm_mw_mode
16638       && bytemode != xmm_md_mode
16639       && bytemode != xmm_mq_mode
16640       && bytemode != xmm_mdq_mode
16641       && bytemode != xmmq_mode
16642       && bytemode != evex_half_bcst_xmmq_mode
16643       && bytemode != ymm_mode
16644       && bytemode != d_scalar_mode
16645       && bytemode != d_scalar_swap_mode
16646       && bytemode != q_scalar_mode
16647       && bytemode != q_scalar_swap_mode
16648       && bytemode != vex_scalar_w_dq_mode)
16649     {
16650       switch (vex.length)
16651         {
16652         case 128:
16653           names = names_xmm;
16654           break;
16655         case 256:
16656           names = names_ymm;
16657           break;
16658         case 512:
16659           names = names_zmm;
16660           break;
16661         default:
16662           abort ();
16663         }
16664     }
16665   else if (bytemode == xmmq_mode
16666            || bytemode == evex_half_bcst_xmmq_mode)
16667     {
16668       switch (vex.length)
16669         {
16670         case 128:
16671         case 256:
16672           names = names_xmm;
16673           break;
16674         case 512:
16675           names = names_ymm;
16676           break;
16677         default:
16678           abort ();
16679         }
16680     }
16681   else if (bytemode == ymm_mode)
16682     names = names_ymm;
16683   else
16684     names = names_xmm;
16685   oappend (names[reg]);
16686 }
16687
16688 static void
16689 OP_MS (int bytemode, int sizeflag)
16690 {
16691   if (modrm.mod == 3)
16692     OP_EM (bytemode, sizeflag);
16693   else
16694     BadOp ();
16695 }
16696
16697 static void
16698 OP_XS (int bytemode, int sizeflag)
16699 {
16700   if (modrm.mod == 3)
16701     OP_EX (bytemode, sizeflag);
16702   else
16703     BadOp ();
16704 }
16705
16706 static void
16707 OP_M (int bytemode, int sizeflag)
16708 {
16709   if (modrm.mod == 3)
16710     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16711     BadOp ();
16712   else
16713     OP_E (bytemode, sizeflag);
16714 }
16715
16716 static void
16717 OP_0f07 (int bytemode, int sizeflag)
16718 {
16719   if (modrm.mod != 3 || modrm.rm != 0)
16720     BadOp ();
16721   else
16722     OP_E (bytemode, sizeflag);
16723 }
16724
16725 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16726    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16727
16728 static void
16729 NOP_Fixup1 (int bytemode, int sizeflag)
16730 {
16731   if ((prefixes & PREFIX_DATA) != 0
16732       || (rex != 0
16733           && rex != 0x48
16734           && address_mode == mode_64bit))
16735     OP_REG (bytemode, sizeflag);
16736   else
16737     strcpy (obuf, "nop");
16738 }
16739
16740 static void
16741 NOP_Fixup2 (int bytemode, int sizeflag)
16742 {
16743   if ((prefixes & PREFIX_DATA) != 0
16744       || (rex != 0
16745           && rex != 0x48
16746           && address_mode == mode_64bit))
16747     OP_IMREG (bytemode, sizeflag);
16748 }
16749
16750 static const char *const Suffix3DNow[] = {
16751 /* 00 */        NULL,           NULL,           NULL,           NULL,
16752 /* 04 */        NULL,           NULL,           NULL,           NULL,
16753 /* 08 */        NULL,           NULL,           NULL,           NULL,
16754 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16755 /* 10 */        NULL,           NULL,           NULL,           NULL,
16756 /* 14 */        NULL,           NULL,           NULL,           NULL,
16757 /* 18 */        NULL,           NULL,           NULL,           NULL,
16758 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16759 /* 20 */        NULL,           NULL,           NULL,           NULL,
16760 /* 24 */        NULL,           NULL,           NULL,           NULL,
16761 /* 28 */        NULL,           NULL,           NULL,           NULL,
16762 /* 2C */        NULL,           NULL,           NULL,           NULL,
16763 /* 30 */        NULL,           NULL,           NULL,           NULL,
16764 /* 34 */        NULL,           NULL,           NULL,           NULL,
16765 /* 38 */        NULL,           NULL,           NULL,           NULL,
16766 /* 3C */        NULL,           NULL,           NULL,           NULL,
16767 /* 40 */        NULL,           NULL,           NULL,           NULL,
16768 /* 44 */        NULL,           NULL,           NULL,           NULL,
16769 /* 48 */        NULL,           NULL,           NULL,           NULL,
16770 /* 4C */        NULL,           NULL,           NULL,           NULL,
16771 /* 50 */        NULL,           NULL,           NULL,           NULL,
16772 /* 54 */        NULL,           NULL,           NULL,           NULL,
16773 /* 58 */        NULL,           NULL,           NULL,           NULL,
16774 /* 5C */        NULL,           NULL,           NULL,           NULL,
16775 /* 60 */        NULL,           NULL,           NULL,           NULL,
16776 /* 64 */        NULL,           NULL,           NULL,           NULL,
16777 /* 68 */        NULL,           NULL,           NULL,           NULL,
16778 /* 6C */        NULL,           NULL,           NULL,           NULL,
16779 /* 70 */        NULL,           NULL,           NULL,           NULL,
16780 /* 74 */        NULL,           NULL,           NULL,           NULL,
16781 /* 78 */        NULL,           NULL,           NULL,           NULL,
16782 /* 7C */        NULL,           NULL,           NULL,           NULL,
16783 /* 80 */        NULL,           NULL,           NULL,           NULL,
16784 /* 84 */        NULL,           NULL,           NULL,           NULL,
16785 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16786 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16787 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16788 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16789 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16790 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16791 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16792 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16793 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16794 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16795 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16796 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16797 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16798 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16799 /* C0 */        NULL,           NULL,           NULL,           NULL,
16800 /* C4 */        NULL,           NULL,           NULL,           NULL,
16801 /* C8 */        NULL,           NULL,           NULL,           NULL,
16802 /* CC */        NULL,           NULL,           NULL,           NULL,
16803 /* D0 */        NULL,           NULL,           NULL,           NULL,
16804 /* D4 */        NULL,           NULL,           NULL,           NULL,
16805 /* D8 */        NULL,           NULL,           NULL,           NULL,
16806 /* DC */        NULL,           NULL,           NULL,           NULL,
16807 /* E0 */        NULL,           NULL,           NULL,           NULL,
16808 /* E4 */        NULL,           NULL,           NULL,           NULL,
16809 /* E8 */        NULL,           NULL,           NULL,           NULL,
16810 /* EC */        NULL,           NULL,           NULL,           NULL,
16811 /* F0 */        NULL,           NULL,           NULL,           NULL,
16812 /* F4 */        NULL,           NULL,           NULL,           NULL,
16813 /* F8 */        NULL,           NULL,           NULL,           NULL,
16814 /* FC */        NULL,           NULL,           NULL,           NULL,
16815 };
16816
16817 static void
16818 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16819 {
16820   const char *mnemonic;
16821
16822   FETCH_DATA (the_info, codep + 1);
16823   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16824      place where an 8-bit immediate would normally go.  ie. the last
16825      byte of the instruction.  */
16826   obufp = mnemonicendp;
16827   mnemonic = Suffix3DNow[*codep++ & 0xff];
16828   if (mnemonic)
16829     oappend (mnemonic);
16830   else
16831     {
16832       /* Since a variable sized modrm/sib chunk is between the start
16833          of the opcode (0x0f0f) and the opcode suffix, we need to do
16834          all the modrm processing first, and don't know until now that
16835          we have a bad opcode.  This necessitates some cleaning up.  */
16836       op_out[0][0] = '\0';
16837       op_out[1][0] = '\0';
16838       BadOp ();
16839     }
16840   mnemonicendp = obufp;
16841 }
16842
16843 static struct op simd_cmp_op[] =
16844 {
16845   { STRING_COMMA_LEN ("eq") },
16846   { STRING_COMMA_LEN ("lt") },
16847   { STRING_COMMA_LEN ("le") },
16848   { STRING_COMMA_LEN ("unord") },
16849   { STRING_COMMA_LEN ("neq") },
16850   { STRING_COMMA_LEN ("nlt") },
16851   { STRING_COMMA_LEN ("nle") },
16852   { STRING_COMMA_LEN ("ord") }
16853 };
16854
16855 static void
16856 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16857 {
16858   unsigned int cmp_type;
16859
16860   FETCH_DATA (the_info, codep + 1);
16861   cmp_type = *codep++ & 0xff;
16862   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16863     {
16864       char suffix [3];
16865       char *p = mnemonicendp - 2;
16866       suffix[0] = p[0];
16867       suffix[1] = p[1];
16868       suffix[2] = '\0';
16869       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16870       mnemonicendp += simd_cmp_op[cmp_type].len;
16871     }
16872   else
16873     {
16874       /* We have a reserved extension byte.  Output it directly.  */
16875       scratchbuf[0] = '$';
16876       print_operand_value (scratchbuf + 1, 1, cmp_type);
16877       oappend_maybe_intel (scratchbuf);
16878       scratchbuf[0] = '\0';
16879     }
16880 }
16881
16882 static void
16883 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16884           int sizeflag ATTRIBUTE_UNUSED)
16885 {
16886   /* mwaitx %eax,%ecx,%ebx */
16887   if (!intel_syntax)
16888     {
16889       const char **names = (address_mode == mode_64bit
16890                             ? names64 : names32);
16891       strcpy (op_out[0], names[0]);
16892       strcpy (op_out[1], names[1]);
16893       strcpy (op_out[2], names[3]);
16894       two_source_ops = 1;
16895     }
16896   /* Skip mod/rm byte.  */
16897   MODRM_CHECK;
16898   codep++;
16899 }
16900
16901 static void
16902 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16903           int sizeflag ATTRIBUTE_UNUSED)
16904 {
16905   /* mwait %eax,%ecx  */
16906   if (!intel_syntax)
16907     {
16908       const char **names = (address_mode == mode_64bit
16909                             ? names64 : names32);
16910       strcpy (op_out[0], names[0]);
16911       strcpy (op_out[1], names[1]);
16912       two_source_ops = 1;
16913     }
16914   /* Skip mod/rm byte.  */
16915   MODRM_CHECK;
16916   codep++;
16917 }
16918
16919 static void
16920 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16921             int sizeflag ATTRIBUTE_UNUSED)
16922 {
16923   /* monitor %eax,%ecx,%edx"  */
16924   if (!intel_syntax)
16925     {
16926       const char **op1_names;
16927       const char **names = (address_mode == mode_64bit
16928                             ? names64 : names32);
16929
16930       if (!(prefixes & PREFIX_ADDR))
16931         op1_names = (address_mode == mode_16bit
16932                      ? names16 : names);
16933       else
16934         {
16935           /* Remove "addr16/addr32".  */
16936           all_prefixes[last_addr_prefix] = 0;
16937           op1_names = (address_mode != mode_32bit
16938                        ? names32 : names16);
16939           used_prefixes |= PREFIX_ADDR;
16940         }
16941       strcpy (op_out[0], op1_names[0]);
16942       strcpy (op_out[1], names[1]);
16943       strcpy (op_out[2], names[2]);
16944       two_source_ops = 1;
16945     }
16946   /* Skip mod/rm byte.  */
16947   MODRM_CHECK;
16948   codep++;
16949 }
16950
16951 static void
16952 BadOp (void)
16953 {
16954   /* Throw away prefixes and 1st. opcode byte.  */
16955   codep = insn_codep + 1;
16956   oappend ("(bad)");
16957 }
16958
16959 static void
16960 REP_Fixup (int bytemode, int sizeflag)
16961 {
16962   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16963      lods and stos.  */
16964   if (prefixes & PREFIX_REPZ)
16965     all_prefixes[last_repz_prefix] = REP_PREFIX;
16966
16967   switch (bytemode)
16968     {
16969     case al_reg:
16970     case eAX_reg:
16971     case indir_dx_reg:
16972       OP_IMREG (bytemode, sizeflag);
16973       break;
16974     case eDI_reg:
16975       OP_ESreg (bytemode, sizeflag);
16976       break;
16977     case eSI_reg:
16978       OP_DSreg (bytemode, sizeflag);
16979       break;
16980     default:
16981       abort ();
16982       break;
16983     }
16984 }
16985
16986 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16987    "bnd".  */
16988
16989 static void
16990 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16991 {
16992   if (prefixes & PREFIX_REPNZ)
16993     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16994 }
16995
16996 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16997    "notrack".  */
16998
16999 static void
17000 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
17001                int sizeflag ATTRIBUTE_UNUSED)
17002 {
17003   if (active_seg_prefix == PREFIX_DS
17004       && (address_mode != mode_64bit || last_data_prefix < 0))
17005     {
17006       /* NOTRACK prefix is only valid on indirect branch instructions.
17007          NB: DATA prefix is unsupported for Intel64.  */
17008       active_seg_prefix = 0;
17009       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
17010     }
17011 }
17012
17013 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
17014    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
17015  */
17016
17017 static void
17018 HLE_Fixup1 (int bytemode, int sizeflag)
17019 {
17020   if (modrm.mod != 3
17021       && (prefixes & PREFIX_LOCK) != 0)
17022     {
17023       if (prefixes & PREFIX_REPZ)
17024         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17025       if (prefixes & PREFIX_REPNZ)
17026         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17027     }
17028
17029   OP_E (bytemode, sizeflag);
17030 }
17031
17032 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
17033    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
17034  */
17035
17036 static void
17037 HLE_Fixup2 (int bytemode, int sizeflag)
17038 {
17039   if (modrm.mod != 3)
17040     {
17041       if (prefixes & PREFIX_REPZ)
17042         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17043       if (prefixes & PREFIX_REPNZ)
17044         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17045     }
17046
17047   OP_E (bytemode, sizeflag);
17048 }
17049
17050 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
17051    "xrelease" for memory operand.  No check for LOCK prefix.   */
17052
17053 static void
17054 HLE_Fixup3 (int bytemode, int sizeflag)
17055 {
17056   if (modrm.mod != 3
17057       && last_repz_prefix > last_repnz_prefix
17058       && (prefixes & PREFIX_REPZ) != 0)
17059     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17060
17061   OP_E (bytemode, sizeflag);
17062 }
17063
17064 static void
17065 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
17066 {
17067   USED_REX (REX_W);
17068   if (rex & REX_W)
17069     {
17070       /* Change cmpxchg8b to cmpxchg16b.  */
17071       char *p = mnemonicendp - 2;
17072       mnemonicendp = stpcpy (p, "16b");
17073       bytemode = o_mode;
17074     }
17075   else if ((prefixes & PREFIX_LOCK) != 0)
17076     {
17077       if (prefixes & PREFIX_REPZ)
17078         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17079       if (prefixes & PREFIX_REPNZ)
17080         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17081     }
17082
17083   OP_M (bytemode, sizeflag);
17084 }
17085
17086 static void
17087 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
17088 {
17089   const char **names;
17090
17091   if (need_vex)
17092     {
17093       switch (vex.length)
17094         {
17095         case 128:
17096           names = names_xmm;
17097           break;
17098         case 256:
17099           names = names_ymm;
17100           break;
17101         default:
17102           abort ();
17103         }
17104     }
17105   else
17106     names = names_xmm;
17107   oappend (names[reg]);
17108 }
17109
17110 static void
17111 CRC32_Fixup (int bytemode, int sizeflag)
17112 {
17113   /* Add proper suffix to "crc32".  */
17114   char *p = mnemonicendp;
17115
17116   switch (bytemode)
17117     {
17118     case b_mode:
17119       if (intel_syntax)
17120         goto skip;
17121
17122       *p++ = 'b';
17123       break;
17124     case v_mode:
17125       if (intel_syntax)
17126         goto skip;
17127
17128       USED_REX (REX_W);
17129       if (rex & REX_W)
17130         *p++ = 'q';
17131       else
17132         {
17133           if (sizeflag & DFLAG)
17134             *p++ = 'l';
17135           else
17136             *p++ = 'w';
17137           used_prefixes |= (prefixes & PREFIX_DATA);
17138         }
17139       break;
17140     default:
17141       oappend (INTERNAL_DISASSEMBLER_ERROR);
17142       break;
17143     }
17144   mnemonicendp = p;
17145   *p = '\0';
17146
17147 skip:
17148   if (modrm.mod == 3)
17149     {
17150       int add;
17151
17152       /* Skip mod/rm byte.  */
17153       MODRM_CHECK;
17154       codep++;
17155
17156       USED_REX (REX_B);
17157       add = (rex & REX_B) ? 8 : 0;
17158       if (bytemode == b_mode)
17159         {
17160           USED_REX (0);
17161           if (rex)
17162             oappend (names8rex[modrm.rm + add]);
17163           else
17164             oappend (names8[modrm.rm + add]);
17165         }
17166       else
17167         {
17168           USED_REX (REX_W);
17169           if (rex & REX_W)
17170             oappend (names64[modrm.rm + add]);
17171           else if ((prefixes & PREFIX_DATA))
17172             oappend (names16[modrm.rm + add]);
17173           else
17174             oappend (names32[modrm.rm + add]);
17175         }
17176     }
17177   else
17178     OP_E (bytemode, sizeflag);
17179 }
17180
17181 static void
17182 FXSAVE_Fixup (int bytemode, int sizeflag)
17183 {
17184   /* Add proper suffix to "fxsave" and "fxrstor".  */
17185   USED_REX (REX_W);
17186   if (rex & REX_W)
17187     {
17188       char *p = mnemonicendp;
17189       *p++ = '6';
17190       *p++ = '4';
17191       *p = '\0';
17192       mnemonicendp = p;
17193     }
17194   OP_M (bytemode, sizeflag);
17195 }
17196
17197 static void
17198 PCMPESTR_Fixup (int bytemode, int sizeflag)
17199 {
17200   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
17201   if (!intel_syntax)
17202     {
17203       char *p = mnemonicendp;
17204
17205       USED_REX (REX_W);
17206       if (rex & REX_W)
17207         *p++ = 'q';
17208       else if (sizeflag & SUFFIX_ALWAYS)
17209         *p++ = 'l';
17210
17211       *p = '\0';
17212       mnemonicendp = p;
17213     }
17214
17215   OP_EX (bytemode, sizeflag);
17216 }
17217
17218 /* Display the destination register operand for instructions with
17219    VEX. */
17220
17221 static void
17222 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17223 {
17224   int reg;
17225   const char **names;
17226
17227   if (!need_vex)
17228     abort ();
17229
17230   if (!need_vex_reg)
17231     return;
17232
17233   reg = vex.register_specifier;
17234   if (address_mode != mode_64bit)
17235     reg &= 7;
17236   else if (vex.evex && !vex.v)
17237     reg += 16;
17238
17239   if (bytemode == vex_scalar_mode)
17240     {
17241       oappend (names_xmm[reg]);
17242       return;
17243     }
17244
17245   switch (vex.length)
17246     {
17247     case 128:
17248       switch (bytemode)
17249         {
17250         case vex_mode:
17251         case vex128_mode:
17252         case vex_vsib_q_w_dq_mode:
17253         case vex_vsib_q_w_d_mode:
17254           names = names_xmm;
17255           break;
17256         case dq_mode:
17257           if (rex & REX_W)
17258             names = names64;
17259           else
17260             names = names32;
17261           break;
17262         case mask_bd_mode:
17263         case mask_mode:
17264           if (reg > 0x7)
17265             {
17266               oappend ("(bad)");
17267               return;
17268             }
17269           names = names_mask;
17270           break;
17271         default:
17272           abort ();
17273           return;
17274         }
17275       break;
17276     case 256:
17277       switch (bytemode)
17278         {
17279         case vex_mode:
17280         case vex256_mode:
17281           names = names_ymm;
17282           break;
17283         case vex_vsib_q_w_dq_mode:
17284         case vex_vsib_q_w_d_mode:
17285           names = vex.w ? names_ymm : names_xmm;
17286           break;
17287         case mask_bd_mode:
17288         case mask_mode:
17289           if (reg > 0x7)
17290             {
17291               oappend ("(bad)");
17292               return;
17293             }
17294           names = names_mask;
17295           break;
17296         default:
17297           /* See PR binutils/20893 for a reproducer.  */
17298           oappend ("(bad)");
17299           return;
17300         }
17301       break;
17302     case 512:
17303       names = names_zmm;
17304       break;
17305     default:
17306       abort ();
17307       break;
17308     }
17309   oappend (names[reg]);
17310 }
17311
17312 /* Get the VEX immediate byte without moving codep.  */
17313
17314 static unsigned char
17315 get_vex_imm8 (int sizeflag, int opnum)
17316 {
17317   int bytes_before_imm = 0;
17318
17319   if (modrm.mod != 3)
17320     {
17321       /* There are SIB/displacement bytes.  */
17322       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17323         {
17324           /* 32/64 bit address mode */
17325           int base = modrm.rm;
17326
17327           /* Check SIB byte.  */
17328           if (base == 4)
17329             {
17330               FETCH_DATA (the_info, codep + 1);
17331               base = *codep & 7;
17332               /* When decoding the third source, don't increase
17333                  bytes_before_imm as this has already been incremented
17334                  by one in OP_E_memory while decoding the second
17335                  source operand.  */
17336               if (opnum == 0)
17337                 bytes_before_imm++;
17338             }
17339
17340           /* Don't increase bytes_before_imm when decoding the third source,
17341              it has already been incremented by OP_E_memory while decoding
17342              the second source operand.  */
17343           if (opnum == 0)
17344             {
17345               switch (modrm.mod)
17346                 {
17347                   case 0:
17348                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17349                        SIB == 5, there is a 4 byte displacement.  */
17350                     if (base != 5)
17351                       /* No displacement. */
17352                       break;
17353                     /* Fall through.  */
17354                   case 2:
17355                     /* 4 byte displacement.  */
17356                     bytes_before_imm += 4;
17357                     break;
17358                   case 1:
17359                     /* 1 byte displacement.  */
17360                     bytes_before_imm++;
17361                     break;
17362                 }
17363             }
17364         }
17365       else
17366         {
17367           /* 16 bit address mode */
17368           /* Don't increase bytes_before_imm when decoding the third source,
17369              it has already been incremented by OP_E_memory while decoding
17370              the second source operand.  */
17371           if (opnum == 0)
17372             {
17373               switch (modrm.mod)
17374                 {
17375                 case 0:
17376                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17377                   if (modrm.rm != 6)
17378                     /* No displacement. */
17379                     break;
17380                   /* Fall through.  */
17381                 case 2:
17382                   /* 2 byte displacement.  */
17383                   bytes_before_imm += 2;
17384                   break;
17385                 case 1:
17386                   /* 1 byte displacement: when decoding the third source,
17387                      don't increase bytes_before_imm as this has already
17388                      been incremented by one in OP_E_memory while decoding
17389                      the second source operand.  */
17390                   if (opnum == 0)
17391                     bytes_before_imm++;
17392
17393                   break;
17394                 }
17395             }
17396         }
17397     }
17398
17399   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17400   return codep [bytes_before_imm];
17401 }
17402
17403 static void
17404 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17405 {
17406   const char **names;
17407
17408   if (reg == -1 && modrm.mod != 3)
17409     {
17410       OP_E_memory (bytemode, sizeflag);
17411       return;
17412     }
17413   else
17414     {
17415       if (reg == -1)
17416         {
17417           reg = modrm.rm;
17418           USED_REX (REX_B);
17419           if (rex & REX_B)
17420             reg += 8;
17421         }
17422       if (address_mode != mode_64bit)
17423         reg &= 7;
17424     }
17425
17426   switch (vex.length)
17427     {
17428     case 128:
17429       names = names_xmm;
17430       break;
17431     case 256:
17432       names = names_ymm;
17433       break;
17434     default:
17435       abort ();
17436     }
17437   oappend (names[reg]);
17438 }
17439
17440 static void
17441 OP_EX_VexImmW (int bytemode, int sizeflag)
17442 {
17443   int reg = -1;
17444   static unsigned char vex_imm8;
17445
17446   if (vex_w_done == 0)
17447     {
17448       vex_w_done = 1;
17449
17450       /* Skip mod/rm byte.  */
17451       MODRM_CHECK;
17452       codep++;
17453
17454       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17455
17456       if (vex.w)
17457           reg = vex_imm8 >> 4;
17458
17459       OP_EX_VexReg (bytemode, sizeflag, reg);
17460     }
17461   else if (vex_w_done == 1)
17462     {
17463       vex_w_done = 2;
17464
17465       if (!vex.w)
17466           reg = vex_imm8 >> 4;
17467
17468       OP_EX_VexReg (bytemode, sizeflag, reg);
17469     }
17470   else
17471     {
17472       /* Output the imm8 directly.  */
17473       scratchbuf[0] = '$';
17474       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17475       oappend_maybe_intel (scratchbuf);
17476       scratchbuf[0] = '\0';
17477       codep++;
17478     }
17479 }
17480
17481 static void
17482 OP_Vex_2src (int bytemode, int sizeflag)
17483 {
17484   if (modrm.mod == 3)
17485     {
17486       int reg = modrm.rm;
17487       USED_REX (REX_B);
17488       if (rex & REX_B)
17489         reg += 8;
17490       oappend (names_xmm[reg]);
17491     }
17492   else
17493     {
17494       if (intel_syntax
17495           && (bytemode == v_mode || bytemode == v_swap_mode))
17496         {
17497           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17498           used_prefixes |= (prefixes & PREFIX_DATA);
17499         }
17500       OP_E (bytemode, sizeflag);
17501     }
17502 }
17503
17504 static void
17505 OP_Vex_2src_1 (int bytemode, int sizeflag)
17506 {
17507   if (modrm.mod == 3)
17508     {
17509       /* Skip mod/rm byte.   */
17510       MODRM_CHECK;
17511       codep++;
17512     }
17513
17514   if (vex.w)
17515     {
17516       unsigned int reg = vex.register_specifier;
17517
17518       if (address_mode != mode_64bit)
17519         reg &= 7;
17520       oappend (names_xmm[reg]);
17521     }
17522   else
17523     OP_Vex_2src (bytemode, sizeflag);
17524 }
17525
17526 static void
17527 OP_Vex_2src_2 (int bytemode, int sizeflag)
17528 {
17529   if (vex.w)
17530     OP_Vex_2src (bytemode, sizeflag);
17531   else
17532     {
17533       unsigned int reg = vex.register_specifier;
17534
17535       if (address_mode != mode_64bit)
17536         reg &= 7;
17537       oappend (names_xmm[reg]);
17538     }
17539 }
17540
17541 static void
17542 OP_EX_VexW (int bytemode, int sizeflag)
17543 {
17544   int reg = -1;
17545
17546   if (!vex_w_done)
17547     {
17548       /* Skip mod/rm byte.  */
17549       MODRM_CHECK;
17550       codep++;
17551
17552       if (vex.w)
17553         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17554     }
17555   else
17556     {
17557       if (!vex.w)
17558         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17559     }
17560
17561   OP_EX_VexReg (bytemode, sizeflag, reg);
17562
17563   if (vex_w_done)
17564     codep++;
17565   vex_w_done = 1;
17566 }
17567
17568 static void
17569 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17570 {
17571   int reg;
17572   const char **names;
17573
17574   FETCH_DATA (the_info, codep + 1);
17575   reg = *codep++;
17576
17577   if (bytemode != x_mode)
17578     abort ();
17579
17580   reg >>= 4;
17581   if (address_mode != mode_64bit)
17582     reg &= 7;
17583
17584   switch (vex.length)
17585     {
17586     case 128:
17587       names = names_xmm;
17588       break;
17589     case 256:
17590       names = names_ymm;
17591       break;
17592     default:
17593       abort ();
17594     }
17595   oappend (names[reg]);
17596 }
17597
17598 static void
17599 OP_XMM_VexW (int bytemode, int sizeflag)
17600 {
17601   /* Turn off the REX.W bit since it is used for swapping operands
17602      now.  */
17603   rex &= ~REX_W;
17604   OP_XMM (bytemode, sizeflag);
17605 }
17606
17607 static void
17608 OP_EX_Vex (int bytemode, int sizeflag)
17609 {
17610   if (modrm.mod != 3)
17611     {
17612       if (vex.register_specifier != 0)
17613         BadOp ();
17614       need_vex_reg = 0;
17615     }
17616   OP_EX (bytemode, sizeflag);
17617 }
17618
17619 static void
17620 OP_XMM_Vex (int bytemode, int sizeflag)
17621 {
17622   if (modrm.mod != 3)
17623     {
17624       if (vex.register_specifier != 0)
17625         BadOp ();
17626       need_vex_reg = 0;
17627     }
17628   OP_XMM (bytemode, sizeflag);
17629 }
17630
17631 static void
17632 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17633 {
17634   switch (vex.length)
17635     {
17636     case 128:
17637       mnemonicendp = stpcpy (obuf, "vzeroupper");
17638       break;
17639     case 256:
17640       mnemonicendp = stpcpy (obuf, "vzeroall");
17641       break;
17642     default:
17643       abort ();
17644     }
17645 }
17646
17647 static struct op vex_cmp_op[] =
17648 {
17649   { STRING_COMMA_LEN ("eq") },
17650   { STRING_COMMA_LEN ("lt") },
17651   { STRING_COMMA_LEN ("le") },
17652   { STRING_COMMA_LEN ("unord") },
17653   { STRING_COMMA_LEN ("neq") },
17654   { STRING_COMMA_LEN ("nlt") },
17655   { STRING_COMMA_LEN ("nle") },
17656   { STRING_COMMA_LEN ("ord") },
17657   { STRING_COMMA_LEN ("eq_uq") },
17658   { STRING_COMMA_LEN ("nge") },
17659   { STRING_COMMA_LEN ("ngt") },
17660   { STRING_COMMA_LEN ("false") },
17661   { STRING_COMMA_LEN ("neq_oq") },
17662   { STRING_COMMA_LEN ("ge") },
17663   { STRING_COMMA_LEN ("gt") },
17664   { STRING_COMMA_LEN ("true") },
17665   { STRING_COMMA_LEN ("eq_os") },
17666   { STRING_COMMA_LEN ("lt_oq") },
17667   { STRING_COMMA_LEN ("le_oq") },
17668   { STRING_COMMA_LEN ("unord_s") },
17669   { STRING_COMMA_LEN ("neq_us") },
17670   { STRING_COMMA_LEN ("nlt_uq") },
17671   { STRING_COMMA_LEN ("nle_uq") },
17672   { STRING_COMMA_LEN ("ord_s") },
17673   { STRING_COMMA_LEN ("eq_us") },
17674   { STRING_COMMA_LEN ("nge_uq") },
17675   { STRING_COMMA_LEN ("ngt_uq") },
17676   { STRING_COMMA_LEN ("false_os") },
17677   { STRING_COMMA_LEN ("neq_os") },
17678   { STRING_COMMA_LEN ("ge_oq") },
17679   { STRING_COMMA_LEN ("gt_oq") },
17680   { STRING_COMMA_LEN ("true_us") },
17681 };
17682
17683 static void
17684 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17685 {
17686   unsigned int cmp_type;
17687
17688   FETCH_DATA (the_info, codep + 1);
17689   cmp_type = *codep++ & 0xff;
17690   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17691     {
17692       char suffix [3];
17693       char *p = mnemonicendp - 2;
17694       suffix[0] = p[0];
17695       suffix[1] = p[1];
17696       suffix[2] = '\0';
17697       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17698       mnemonicendp += vex_cmp_op[cmp_type].len;
17699     }
17700   else
17701     {
17702       /* We have a reserved extension byte.  Output it directly.  */
17703       scratchbuf[0] = '$';
17704       print_operand_value (scratchbuf + 1, 1, cmp_type);
17705       oappend_maybe_intel (scratchbuf);
17706       scratchbuf[0] = '\0';
17707     }
17708 }
17709
17710 static void
17711 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17712              int sizeflag ATTRIBUTE_UNUSED)
17713 {
17714   unsigned int cmp_type;
17715
17716   if (!vex.evex)
17717     abort ();
17718
17719   FETCH_DATA (the_info, codep + 1);
17720   cmp_type = *codep++ & 0xff;
17721   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17722      If it's the case, print suffix, otherwise - print the immediate.  */
17723   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17724       && cmp_type != 3
17725       && cmp_type != 7)
17726     {
17727       char suffix [3];
17728       char *p = mnemonicendp - 2;
17729
17730       /* vpcmp* can have both one- and two-lettered suffix.  */
17731       if (p[0] == 'p')
17732         {
17733           p++;
17734           suffix[0] = p[0];
17735           suffix[1] = '\0';
17736         }
17737       else
17738         {
17739           suffix[0] = p[0];
17740           suffix[1] = p[1];
17741           suffix[2] = '\0';
17742         }
17743
17744       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17745       mnemonicendp += simd_cmp_op[cmp_type].len;
17746     }
17747   else
17748     {
17749       /* We have a reserved extension byte.  Output it directly.  */
17750       scratchbuf[0] = '$';
17751       print_operand_value (scratchbuf + 1, 1, cmp_type);
17752       oappend_maybe_intel (scratchbuf);
17753       scratchbuf[0] = '\0';
17754     }
17755 }
17756
17757 static const struct op xop_cmp_op[] =
17758 {
17759   { STRING_COMMA_LEN ("lt") },
17760   { STRING_COMMA_LEN ("le") },
17761   { STRING_COMMA_LEN ("gt") },
17762   { STRING_COMMA_LEN ("ge") },
17763   { STRING_COMMA_LEN ("eq") },
17764   { STRING_COMMA_LEN ("neq") },
17765   { STRING_COMMA_LEN ("false") },
17766   { STRING_COMMA_LEN ("true") }
17767 };
17768
17769 static void
17770 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
17771              int sizeflag ATTRIBUTE_UNUSED)
17772 {
17773   unsigned int cmp_type;
17774
17775   FETCH_DATA (the_info, codep + 1);
17776   cmp_type = *codep++ & 0xff;
17777   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
17778     {
17779       char suffix[3];
17780       char *p = mnemonicendp - 2;
17781
17782       /* vpcom* can have both one- and two-lettered suffix.  */
17783       if (p[0] == 'm')
17784         {
17785           p++;
17786           suffix[0] = p[0];
17787           suffix[1] = '\0';
17788         }
17789       else
17790         {
17791           suffix[0] = p[0];
17792           suffix[1] = p[1];
17793           suffix[2] = '\0';
17794         }
17795
17796       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
17797       mnemonicendp += xop_cmp_op[cmp_type].len;
17798     }
17799   else
17800     {
17801       /* We have a reserved extension byte.  Output it directly.  */
17802       scratchbuf[0] = '$';
17803       print_operand_value (scratchbuf + 1, 1, cmp_type);
17804       oappend_maybe_intel (scratchbuf);
17805       scratchbuf[0] = '\0';
17806     }
17807 }
17808
17809 static const struct op pclmul_op[] =
17810 {
17811   { STRING_COMMA_LEN ("lql") },
17812   { STRING_COMMA_LEN ("hql") },
17813   { STRING_COMMA_LEN ("lqh") },
17814   { STRING_COMMA_LEN ("hqh") }
17815 };
17816
17817 static void
17818 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17819               int sizeflag ATTRIBUTE_UNUSED)
17820 {
17821   unsigned int pclmul_type;
17822
17823   FETCH_DATA (the_info, codep + 1);
17824   pclmul_type = *codep++ & 0xff;
17825   switch (pclmul_type)
17826     {
17827     case 0x10:
17828       pclmul_type = 2;
17829       break;
17830     case 0x11:
17831       pclmul_type = 3;
17832       break;
17833     default:
17834       break;
17835     }
17836   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17837     {
17838       char suffix [4];
17839       char *p = mnemonicendp - 3;
17840       suffix[0] = p[0];
17841       suffix[1] = p[1];
17842       suffix[2] = p[2];
17843       suffix[3] = '\0';
17844       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17845       mnemonicendp += pclmul_op[pclmul_type].len;
17846     }
17847   else
17848     {
17849       /* We have a reserved extension byte.  Output it directly.  */
17850       scratchbuf[0] = '$';
17851       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17852       oappend_maybe_intel (scratchbuf);
17853       scratchbuf[0] = '\0';
17854     }
17855 }
17856
17857 static void
17858 MOVBE_Fixup (int bytemode, int sizeflag)
17859 {
17860   /* Add proper suffix to "movbe".  */
17861   char *p = mnemonicendp;
17862
17863   switch (bytemode)
17864     {
17865     case v_mode:
17866       if (intel_syntax)
17867         goto skip;
17868
17869       USED_REX (REX_W);
17870       if (sizeflag & SUFFIX_ALWAYS)
17871         {
17872           if (rex & REX_W)
17873             *p++ = 'q';
17874           else
17875             {
17876               if (sizeflag & DFLAG)
17877                 *p++ = 'l';
17878               else
17879                 *p++ = 'w';
17880               used_prefixes |= (prefixes & PREFIX_DATA);
17881             }
17882         }
17883       break;
17884     default:
17885       oappend (INTERNAL_DISASSEMBLER_ERROR);
17886       break;
17887     }
17888   mnemonicendp = p;
17889   *p = '\0';
17890
17891 skip:
17892   OP_M (bytemode, sizeflag);
17893 }
17894
17895 static void
17896 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17897 {
17898   int reg;
17899   const char **names;
17900
17901   /* Skip mod/rm byte.  */
17902   MODRM_CHECK;
17903   codep++;
17904
17905   if (rex & REX_W)
17906     names = names64;
17907   else
17908     names = names32;
17909
17910   reg = modrm.rm;
17911   USED_REX (REX_B);
17912   if (rex & REX_B)
17913     reg += 8;
17914
17915   oappend (names[reg]);
17916 }
17917
17918 static void
17919 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17920 {
17921   const char **names;
17922   unsigned int reg = vex.register_specifier;
17923
17924   if (rex & REX_W)
17925     names = names64;
17926   else
17927     names = names32;
17928
17929   if (address_mode != mode_64bit)
17930     reg &= 7;
17931   oappend (names[reg]);
17932 }
17933
17934 static void
17935 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17936 {
17937   if (!vex.evex
17938       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17939     abort ();
17940
17941   USED_REX (REX_R);
17942   if ((rex & REX_R) != 0 || !vex.r)
17943     {
17944       BadOp ();
17945       return;
17946     }
17947
17948   oappend (names_mask [modrm.reg]);
17949 }
17950
17951 static void
17952 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17953 {
17954   if (!vex.evex
17955       || (bytemode != evex_rounding_mode
17956           && bytemode != evex_rounding_64_mode
17957           && bytemode != evex_sae_mode))
17958     abort ();
17959   if (modrm.mod == 3 && vex.b)
17960     switch (bytemode)
17961       {
17962       case evex_rounding_64_mode:
17963         if (address_mode != mode_64bit)
17964           {
17965             oappend ("(bad)");
17966             break;
17967           }
17968         /* Fall through.  */
17969       case evex_rounding_mode:
17970         oappend (names_rounding[vex.ll]);
17971         break;
17972       case evex_sae_mode:
17973         oappend ("{sae}");
17974         break;
17975       default:
17976         break;
17977       }
17978 }