1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2018 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VZERO_Fixup (int, int);
99 static void VCMP_Fixup (int, int);
100 static void VPCMP_Fixup (int, int);
101 static void VPCOM_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void NOTRACK_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void PCMPESTR_Fixup (int, int);
122 static void OP_LWPCB_E (int, int);
123 static void OP_LWP_E (int, int);
124 static void OP_Vex_2src_1 (int, int);
125 static void OP_Vex_2src_2 (int, int);
127 static void MOVBE_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte
*max_fetched
;
134 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
137 OPCODES_SIGJMP_BUF bailout
;
147 enum address_mode address_mode
;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* REX bits in original REX prefix ignored. */
157 static int rex_ignored
;
158 /* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162 #define USED_REX(value) \
167 rex_used |= (value) | REX_OPCODE; \
170 rex_used |= REX_OPCODE; \
173 /* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175 static int used_prefixes
;
177 /* Flags stored in PREFIXES. */
178 #define PREFIX_REPZ 1
179 #define PREFIX_REPNZ 2
180 #define PREFIX_LOCK 4
182 #define PREFIX_SS 0x10
183 #define PREFIX_DS 0x20
184 #define PREFIX_ES 0x40
185 #define PREFIX_FS 0x80
186 #define PREFIX_GS 0x100
187 #define PREFIX_DATA 0x200
188 #define PREFIX_ADDR 0x400
189 #define PREFIX_FWAIT 0x800
191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
194 #define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
199 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
202 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
203 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
205 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
206 status
= (*info
->read_memory_func
) (start
,
208 addr
- priv
->max_fetched
,
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
218 if (priv
->max_fetched
== priv
->the_buffer
)
219 (*info
->memory_error_func
) (status
, start
, info
);
220 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
223 priv
->max_fetched
= addr
;
227 /* Possible values for prefix requirement. */
228 #define PREFIX_IGNORED_SHIFT 16
229 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
235 /* Opcode prefixes. */
236 #define PREFIX_OPCODE (PREFIX_REPZ \
240 /* Prefixes ignored. */
241 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
245 #define XX { NULL, 0 }
246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
248 #define Eb { OP_E, b_mode }
249 #define Ebnd { OP_E, bnd_mode }
250 #define EbS { OP_E, b_swap_mode }
251 #define EbndS { OP_E, bnd_swap_mode }
252 #define Ev { OP_E, v_mode }
253 #define Eva { OP_E, va_mode }
254 #define Ev_bnd { OP_E, v_bnd_mode }
255 #define EvS { OP_E, v_swap_mode }
256 #define Ed { OP_E, d_mode }
257 #define Edq { OP_E, dq_mode }
258 #define Edqw { OP_E, dqw_mode }
259 #define Edqb { OP_E, dqb_mode }
260 #define Edb { OP_E, db_mode }
261 #define Edw { OP_E, dw_mode }
262 #define Edqd { OP_E, dqd_mode }
263 #define Eq { OP_E, q_mode }
264 #define indirEv { OP_indirE, indir_v_mode }
265 #define indirEp { OP_indirE, f_mode }
266 #define stackEv { OP_E, stack_v_mode }
267 #define Em { OP_E, m_mode }
268 #define Ew { OP_E, w_mode }
269 #define M { OP_M, 0 } /* lea, lgdt, etc. */
270 #define Ma { OP_M, a_mode }
271 #define Mb { OP_M, b_mode }
272 #define Md { OP_M, d_mode }
273 #define Mo { OP_M, o_mode }
274 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
275 #define Mq { OP_M, q_mode }
276 #define Mx { OP_M, x_mode }
277 #define Mxmm { OP_M, xmm_mode }
278 #define Gb { OP_G, b_mode }
279 #define Gbnd { OP_G, bnd_mode }
280 #define Gv { OP_G, v_mode }
281 #define Gd { OP_G, d_mode }
282 #define Gdq { OP_G, dq_mode }
283 #define Gm { OP_G, m_mode }
284 #define Gw { OP_G, w_mode }
285 #define Rd { OP_R, d_mode }
286 #define Rdq { OP_R, dq_mode }
287 #define Rm { OP_R, m_mode }
288 #define Ib { OP_I, b_mode }
289 #define sIb { OP_sI, b_mode } /* sign extened byte */
290 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
291 #define Iv { OP_I, v_mode }
292 #define sIv { OP_sI, v_mode }
293 #define Iq { OP_I, q_mode }
294 #define Iv64 { OP_I64, v_mode }
295 #define Iw { OP_I, w_mode }
296 #define I1 { OP_I, const_1_mode }
297 #define Jb { OP_J, b_mode }
298 #define Jv { OP_J, v_mode }
299 #define Cm { OP_C, m_mode }
300 #define Dm { OP_D, m_mode }
301 #define Td { OP_T, d_mode }
302 #define Skip_MODRM { OP_Skip_MODRM, 0 }
304 #define RMeAX { OP_REG, eAX_reg }
305 #define RMeBX { OP_REG, eBX_reg }
306 #define RMeCX { OP_REG, eCX_reg }
307 #define RMeDX { OP_REG, eDX_reg }
308 #define RMeSP { OP_REG, eSP_reg }
309 #define RMeBP { OP_REG, eBP_reg }
310 #define RMeSI { OP_REG, eSI_reg }
311 #define RMeDI { OP_REG, eDI_reg }
312 #define RMrAX { OP_REG, rAX_reg }
313 #define RMrBX { OP_REG, rBX_reg }
314 #define RMrCX { OP_REG, rCX_reg }
315 #define RMrDX { OP_REG, rDX_reg }
316 #define RMrSP { OP_REG, rSP_reg }
317 #define RMrBP { OP_REG, rBP_reg }
318 #define RMrSI { OP_REG, rSI_reg }
319 #define RMrDI { OP_REG, rDI_reg }
320 #define RMAL { OP_REG, al_reg }
321 #define RMCL { OP_REG, cl_reg }
322 #define RMDL { OP_REG, dl_reg }
323 #define RMBL { OP_REG, bl_reg }
324 #define RMAH { OP_REG, ah_reg }
325 #define RMCH { OP_REG, ch_reg }
326 #define RMDH { OP_REG, dh_reg }
327 #define RMBH { OP_REG, bh_reg }
328 #define RMAX { OP_REG, ax_reg }
329 #define RMDX { OP_REG, dx_reg }
331 #define eAX { OP_IMREG, eAX_reg }
332 #define eBX { OP_IMREG, eBX_reg }
333 #define eCX { OP_IMREG, eCX_reg }
334 #define eDX { OP_IMREG, eDX_reg }
335 #define eSP { OP_IMREG, eSP_reg }
336 #define eBP { OP_IMREG, eBP_reg }
337 #define eSI { OP_IMREG, eSI_reg }
338 #define eDI { OP_IMREG, eDI_reg }
339 #define AL { OP_IMREG, al_reg }
340 #define CL { OP_IMREG, cl_reg }
341 #define DL { OP_IMREG, dl_reg }
342 #define BL { OP_IMREG, bl_reg }
343 #define AH { OP_IMREG, ah_reg }
344 #define CH { OP_IMREG, ch_reg }
345 #define DH { OP_IMREG, dh_reg }
346 #define BH { OP_IMREG, bh_reg }
347 #define AX { OP_IMREG, ax_reg }
348 #define DX { OP_IMREG, dx_reg }
349 #define zAX { OP_IMREG, z_mode_ax_reg }
350 #define indirDX { OP_IMREG, indir_dx_reg }
352 #define Sw { OP_SEG, w_mode }
353 #define Sv { OP_SEG, v_mode }
354 #define Ap { OP_DIR, 0 }
355 #define Ob { OP_OFF64, b_mode }
356 #define Ov { OP_OFF64, v_mode }
357 #define Xb { OP_DSreg, eSI_reg }
358 #define Xv { OP_DSreg, eSI_reg }
359 #define Xz { OP_DSreg, eSI_reg }
360 #define Yb { OP_ESreg, eDI_reg }
361 #define Yv { OP_ESreg, eDI_reg }
362 #define DSBX { OP_DSreg, eBX_reg }
364 #define es { OP_REG, es_reg }
365 #define ss { OP_REG, ss_reg }
366 #define cs { OP_REG, cs_reg }
367 #define ds { OP_REG, ds_reg }
368 #define fs { OP_REG, fs_reg }
369 #define gs { OP_REG, gs_reg }
371 #define MX { OP_MMX, 0 }
372 #define XM { OP_XMM, 0 }
373 #define XMScalar { OP_XMM, scalar_mode }
374 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
375 #define XMM { OP_XMM, xmm_mode }
376 #define XMxmmq { OP_XMM, xmmq_mode }
377 #define EM { OP_EM, v_mode }
378 #define EMS { OP_EM, v_swap_mode }
379 #define EMd { OP_EM, d_mode }
380 #define EMx { OP_EM, x_mode }
381 #define EXbScalar { OP_EX, b_scalar_mode }
382 #define EXw { OP_EX, w_mode }
383 #define EXwScalar { OP_EX, w_scalar_mode }
384 #define EXd { OP_EX, d_mode }
385 #define EXdScalar { OP_EX, d_scalar_mode }
386 #define EXdS { OP_EX, d_swap_mode }
387 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
388 #define EXq { OP_EX, q_mode }
389 #define EXqScalar { OP_EX, q_scalar_mode }
390 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
391 #define EXqS { OP_EX, q_swap_mode }
392 #define EXx { OP_EX, x_mode }
393 #define EXxS { OP_EX, x_swap_mode }
394 #define EXxmm { OP_EX, xmm_mode }
395 #define EXymm { OP_EX, ymm_mode }
396 #define EXxmmq { OP_EX, xmmq_mode }
397 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
398 #define EXxmm_mb { OP_EX, xmm_mb_mode }
399 #define EXxmm_mw { OP_EX, xmm_mw_mode }
400 #define EXxmm_md { OP_EX, xmm_md_mode }
401 #define EXxmm_mq { OP_EX, xmm_mq_mode }
402 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
403 #define EXxmmdw { OP_EX, xmmdw_mode }
404 #define EXxmmqd { OP_EX, xmmqd_mode }
405 #define EXymmq { OP_EX, ymmq_mode }
406 #define EXVexWdq { OP_EX, vex_w_dq_mode }
407 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
408 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
409 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
410 #define MS { OP_MS, v_mode }
411 #define XS { OP_XS, v_mode }
412 #define EMCq { OP_EMC, q_mode }
413 #define MXC { OP_MXC, 0 }
414 #define OPSUF { OP_3DNowSuffix, 0 }
415 #define CMP { CMP_Fixup, 0 }
416 #define XMM0 { XMM_Fixup, 0 }
417 #define FXSAVE { FXSAVE_Fixup, 0 }
418 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
419 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
421 #define Vex { OP_VEX, vex_mode }
422 #define VexScalar { OP_VEX, vex_scalar_mode }
423 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
424 #define Vex128 { OP_VEX, vex128_mode }
425 #define Vex256 { OP_VEX, vex256_mode }
426 #define VexGdq { OP_VEX, dq_mode }
427 #define EXdVex { OP_EX_Vex, d_mode }
428 #define EXdVexS { OP_EX_Vex, d_swap_mode }
429 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
430 #define EXqVex { OP_EX_Vex, q_mode }
431 #define EXqVexS { OP_EX_Vex, q_swap_mode }
432 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
433 #define EXVexW { OP_EX_VexW, x_mode }
434 #define EXdVexW { OP_EX_VexW, d_mode }
435 #define EXqVexW { OP_EX_VexW, q_mode }
436 #define EXVexImmW { OP_EX_VexImmW, x_mode }
437 #define XMVex { OP_XMM_Vex, 0 }
438 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
439 #define XMVexW { OP_XMM_VexW, 0 }
440 #define XMVexI4 { OP_REG_VexI4, x_mode }
441 #define PCLMUL { PCLMUL_Fixup, 0 }
442 #define VZERO { VZERO_Fixup, 0 }
443 #define VCMP { VCMP_Fixup, 0 }
444 #define VPCMP { VPCMP_Fixup, 0 }
445 #define VPCOM { VPCOM_Fixup, 0 }
447 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
448 #define EXxEVexS { OP_Rounding, evex_sae_mode }
450 #define XMask { OP_Mask, mask_mode }
451 #define MaskG { OP_G, mask_mode }
452 #define MaskE { OP_E, mask_mode }
453 #define MaskBDE { OP_E, mask_bd_mode }
454 #define MaskR { OP_R, mask_mode }
455 #define MaskVex { OP_VEX, mask_mode }
457 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
458 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
459 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
460 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
462 /* Used handle "rep" prefix for string instructions. */
463 #define Xbr { REP_Fixup, eSI_reg }
464 #define Xvr { REP_Fixup, eSI_reg }
465 #define Ybr { REP_Fixup, eDI_reg }
466 #define Yvr { REP_Fixup, eDI_reg }
467 #define Yzr { REP_Fixup, eDI_reg }
468 #define indirDXr { REP_Fixup, indir_dx_reg }
469 #define ALr { REP_Fixup, al_reg }
470 #define eAXr { REP_Fixup, eAX_reg }
472 /* Used handle HLE prefix for lockable instructions. */
473 #define Ebh1 { HLE_Fixup1, b_mode }
474 #define Evh1 { HLE_Fixup1, v_mode }
475 #define Ebh2 { HLE_Fixup2, b_mode }
476 #define Evh2 { HLE_Fixup2, v_mode }
477 #define Ebh3 { HLE_Fixup3, b_mode }
478 #define Evh3 { HLE_Fixup3, v_mode }
480 #define BND { BND_Fixup, 0 }
481 #define NOTRACK { NOTRACK_Fixup, 0 }
483 #define cond_jump_flag { NULL, cond_jump_mode }
484 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
486 /* bits in sizeflag */
487 #define SUFFIX_ALWAYS 4
495 /* byte operand with operand swapped */
497 /* byte operand, sign extend like 'T' suffix */
499 /* operand size depends on prefixes */
501 /* operand size depends on prefixes with operand swapped */
503 /* operand size depends on address prefix */
507 /* double word operand */
509 /* double word operand with operand swapped */
511 /* quad word operand */
513 /* quad word operand with operand swapped */
515 /* ten-byte operand */
517 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
518 broadcast enabled. */
520 /* Similar to x_mode, but with different EVEX mem shifts. */
522 /* Similar to x_mode, but with disabled broadcast. */
524 /* Similar to x_mode, but with operands swapped and disabled broadcast
527 /* 16-byte XMM operand */
529 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
530 memory operand (depending on vector length). Broadcast isn't
533 /* Same as xmmq_mode, but broadcast is allowed. */
534 evex_half_bcst_xmmq_mode
,
535 /* XMM register or byte memory operand */
537 /* XMM register or word memory operand */
539 /* XMM register or double word memory operand */
541 /* XMM register or quad word memory operand */
543 /* XMM register or double/quad word memory operand, depending on
546 /* 16-byte XMM, word, double word or quad word operand. */
548 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
550 /* 32-byte YMM operand */
552 /* quad word, ymmword or zmmword memory operand. */
554 /* 32-byte YMM or 16-byte word operand */
556 /* d_mode in 32bit, q_mode in 64bit mode. */
558 /* pair of v_mode operands */
563 /* operand size depends on REX prefixes. */
565 /* registers like dq_mode, memory like w_mode. */
569 /* bounds operand with operand swapped */
571 /* 4- or 6-byte pointer operand */
574 /* v_mode for indirect branch opcodes. */
576 /* v_mode for stack-related opcodes. */
578 /* non-quad operand size depends on prefixes */
580 /* 16-byte operand */
582 /* registers like dq_mode, memory like b_mode. */
584 /* registers like d_mode, memory like b_mode. */
586 /* registers like d_mode, memory like w_mode. */
588 /* registers like dq_mode, memory like d_mode. */
590 /* normal vex mode */
592 /* 128bit vex mode */
594 /* 256bit vex mode */
596 /* operand size depends on the VEX.W bit. */
599 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
600 vex_vsib_d_w_dq_mode
,
601 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
603 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
604 vex_vsib_q_w_dq_mode
,
605 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
608 /* scalar, ignore vector length. */
610 /* like b_mode, ignore vector length. */
612 /* like w_mode, ignore vector length. */
614 /* like d_mode, ignore vector length. */
616 /* like d_swap_mode, ignore vector length. */
618 /* like q_mode, ignore vector length. */
620 /* like q_swap_mode, ignore vector length. */
622 /* like vex_mode, ignore vector length. */
624 /* like vex_w_dq_mode, ignore vector length. */
625 vex_scalar_w_dq_mode
,
627 /* Static rounding. */
629 /* Supress all exceptions. */
632 /* Mask register operand. */
634 /* Mask register operand. */
701 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
703 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
704 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
705 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
706 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
707 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
708 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
709 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
710 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
711 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
712 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
713 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
714 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
715 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
716 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
717 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
841 MOD_VEX_0F12_PREFIX_0
,
843 MOD_VEX_0F16_PREFIX_0
,
846 MOD_VEX_W_0_0F41_P_0_LEN_1
,
847 MOD_VEX_W_1_0F41_P_0_LEN_1
,
848 MOD_VEX_W_0_0F41_P_2_LEN_1
,
849 MOD_VEX_W_1_0F41_P_2_LEN_1
,
850 MOD_VEX_W_0_0F42_P_0_LEN_1
,
851 MOD_VEX_W_1_0F42_P_0_LEN_1
,
852 MOD_VEX_W_0_0F42_P_2_LEN_1
,
853 MOD_VEX_W_1_0F42_P_2_LEN_1
,
854 MOD_VEX_W_0_0F44_P_0_LEN_1
,
855 MOD_VEX_W_1_0F44_P_0_LEN_1
,
856 MOD_VEX_W_0_0F44_P_2_LEN_1
,
857 MOD_VEX_W_1_0F44_P_2_LEN_1
,
858 MOD_VEX_W_0_0F45_P_0_LEN_1
,
859 MOD_VEX_W_1_0F45_P_0_LEN_1
,
860 MOD_VEX_W_0_0F45_P_2_LEN_1
,
861 MOD_VEX_W_1_0F45_P_2_LEN_1
,
862 MOD_VEX_W_0_0F46_P_0_LEN_1
,
863 MOD_VEX_W_1_0F46_P_0_LEN_1
,
864 MOD_VEX_W_0_0F46_P_2_LEN_1
,
865 MOD_VEX_W_1_0F46_P_2_LEN_1
,
866 MOD_VEX_W_0_0F47_P_0_LEN_1
,
867 MOD_VEX_W_1_0F47_P_0_LEN_1
,
868 MOD_VEX_W_0_0F47_P_2_LEN_1
,
869 MOD_VEX_W_1_0F47_P_2_LEN_1
,
870 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
871 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
872 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
873 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
874 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
875 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
876 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
888 MOD_VEX_W_0_0F91_P_0_LEN_0
,
889 MOD_VEX_W_1_0F91_P_0_LEN_0
,
890 MOD_VEX_W_0_0F91_P_2_LEN_0
,
891 MOD_VEX_W_1_0F91_P_2_LEN_0
,
892 MOD_VEX_W_0_0F92_P_0_LEN_0
,
893 MOD_VEX_W_0_0F92_P_2_LEN_0
,
894 MOD_VEX_W_0_0F92_P_3_LEN_0
,
895 MOD_VEX_W_1_0F92_P_3_LEN_0
,
896 MOD_VEX_W_0_0F93_P_0_LEN_0
,
897 MOD_VEX_W_0_0F93_P_2_LEN_0
,
898 MOD_VEX_W_0_0F93_P_3_LEN_0
,
899 MOD_VEX_W_1_0F93_P_3_LEN_0
,
900 MOD_VEX_W_0_0F98_P_0_LEN_0
,
901 MOD_VEX_W_1_0F98_P_0_LEN_0
,
902 MOD_VEX_W_0_0F98_P_2_LEN_0
,
903 MOD_VEX_W_1_0F98_P_2_LEN_0
,
904 MOD_VEX_W_0_0F99_P_0_LEN_0
,
905 MOD_VEX_W_1_0F99_P_0_LEN_0
,
906 MOD_VEX_W_0_0F99_P_2_LEN_0
,
907 MOD_VEX_W_1_0F99_P_2_LEN_0
,
910 MOD_VEX_0FD7_PREFIX_2
,
911 MOD_VEX_0FE7_PREFIX_2
,
912 MOD_VEX_0FF0_PREFIX_3
,
913 MOD_VEX_0F381A_PREFIX_2
,
914 MOD_VEX_0F382A_PREFIX_2
,
915 MOD_VEX_0F382C_PREFIX_2
,
916 MOD_VEX_0F382D_PREFIX_2
,
917 MOD_VEX_0F382E_PREFIX_2
,
918 MOD_VEX_0F382F_PREFIX_2
,
919 MOD_VEX_0F385A_PREFIX_2
,
920 MOD_VEX_0F388C_PREFIX_2
,
921 MOD_VEX_0F388E_PREFIX_2
,
922 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
923 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
924 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
925 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
926 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
927 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
928 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
929 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
931 MOD_EVEX_0F10_PREFIX_1
,
932 MOD_EVEX_0F10_PREFIX_3
,
933 MOD_EVEX_0F11_PREFIX_1
,
934 MOD_EVEX_0F11_PREFIX_3
,
935 MOD_EVEX_0F12_PREFIX_0
,
936 MOD_EVEX_0F16_PREFIX_0
,
937 MOD_EVEX_0F38C6_REG_1
,
938 MOD_EVEX_0F38C6_REG_2
,
939 MOD_EVEX_0F38C6_REG_5
,
940 MOD_EVEX_0F38C6_REG_6
,
941 MOD_EVEX_0F38C7_REG_1
,
942 MOD_EVEX_0F38C7_REG_2
,
943 MOD_EVEX_0F38C7_REG_5
,
944 MOD_EVEX_0F38C7_REG_6
965 PREFIX_MOD_0_0F01_REG_5
,
966 PREFIX_MOD_3_0F01_REG_5_RM_0
,
967 PREFIX_MOD_3_0F01_REG_5_RM_2
,
1013 PREFIX_MOD_0_0FAE_REG_4
,
1014 PREFIX_MOD_3_0FAE_REG_4
,
1015 PREFIX_MOD_0_0FAE_REG_5
,
1016 PREFIX_MOD_3_0FAE_REG_5
,
1017 PREFIX_MOD_0_0FAE_REG_6
,
1018 PREFIX_MOD_1_0FAE_REG_6
,
1025 PREFIX_MOD_0_0FC7_REG_6
,
1026 PREFIX_MOD_3_0FC7_REG_6
,
1027 PREFIX_MOD_3_0FC7_REG_7
,
1155 PREFIX_VEX_0F71_REG_2
,
1156 PREFIX_VEX_0F71_REG_4
,
1157 PREFIX_VEX_0F71_REG_6
,
1158 PREFIX_VEX_0F72_REG_2
,
1159 PREFIX_VEX_0F72_REG_4
,
1160 PREFIX_VEX_0F72_REG_6
,
1161 PREFIX_VEX_0F73_REG_2
,
1162 PREFIX_VEX_0F73_REG_3
,
1163 PREFIX_VEX_0F73_REG_6
,
1164 PREFIX_VEX_0F73_REG_7
,
1337 PREFIX_VEX_0F38F3_REG_1
,
1338 PREFIX_VEX_0F38F3_REG_2
,
1339 PREFIX_VEX_0F38F3_REG_3
,
1458 PREFIX_EVEX_0F71_REG_2
,
1459 PREFIX_EVEX_0F71_REG_4
,
1460 PREFIX_EVEX_0F71_REG_6
,
1461 PREFIX_EVEX_0F72_REG_0
,
1462 PREFIX_EVEX_0F72_REG_1
,
1463 PREFIX_EVEX_0F72_REG_2
,
1464 PREFIX_EVEX_0F72_REG_4
,
1465 PREFIX_EVEX_0F72_REG_6
,
1466 PREFIX_EVEX_0F73_REG_2
,
1467 PREFIX_EVEX_0F73_REG_3
,
1468 PREFIX_EVEX_0F73_REG_6
,
1469 PREFIX_EVEX_0F73_REG_7
,
1665 PREFIX_EVEX_0F38C6_REG_1
,
1666 PREFIX_EVEX_0F38C6_REG_2
,
1667 PREFIX_EVEX_0F38C6_REG_5
,
1668 PREFIX_EVEX_0F38C6_REG_6
,
1669 PREFIX_EVEX_0F38C7_REG_1
,
1670 PREFIX_EVEX_0F38C7_REG_2
,
1671 PREFIX_EVEX_0F38C7_REG_5
,
1672 PREFIX_EVEX_0F38C7_REG_6
,
1774 THREE_BYTE_0F38
= 0,
1801 VEX_LEN_0F10_P_1
= 0,
1805 VEX_LEN_0F12_P_0_M_0
,
1806 VEX_LEN_0F12_P_0_M_1
,
1809 VEX_LEN_0F16_P_0_M_0
,
1810 VEX_LEN_0F16_P_0_M_1
,
1874 VEX_LEN_0FAE_R_2_M_0
,
1875 VEX_LEN_0FAE_R_3_M_0
,
1884 VEX_LEN_0F381A_P_2_M_0
,
1887 VEX_LEN_0F385A_P_2_M_0
,
1890 VEX_LEN_0F38F3_R_1_P_0
,
1891 VEX_LEN_0F38F3_R_2_P_0
,
1892 VEX_LEN_0F38F3_R_3_P_0
,
1937 VEX_LEN_0FXOP_08_CC
,
1938 VEX_LEN_0FXOP_08_CD
,
1939 VEX_LEN_0FXOP_08_CE
,
1940 VEX_LEN_0FXOP_08_CF
,
1941 VEX_LEN_0FXOP_08_EC
,
1942 VEX_LEN_0FXOP_08_ED
,
1943 VEX_LEN_0FXOP_08_EE
,
1944 VEX_LEN_0FXOP_08_EF
,
1945 VEX_LEN_0FXOP_09_80
,
1979 VEX_W_0F41_P_0_LEN_1
,
1980 VEX_W_0F41_P_2_LEN_1
,
1981 VEX_W_0F42_P_0_LEN_1
,
1982 VEX_W_0F42_P_2_LEN_1
,
1983 VEX_W_0F44_P_0_LEN_0
,
1984 VEX_W_0F44_P_2_LEN_0
,
1985 VEX_W_0F45_P_0_LEN_1
,
1986 VEX_W_0F45_P_2_LEN_1
,
1987 VEX_W_0F46_P_0_LEN_1
,
1988 VEX_W_0F46_P_2_LEN_1
,
1989 VEX_W_0F47_P_0_LEN_1
,
1990 VEX_W_0F47_P_2_LEN_1
,
1991 VEX_W_0F4A_P_0_LEN_1
,
1992 VEX_W_0F4A_P_2_LEN_1
,
1993 VEX_W_0F4B_P_0_LEN_1
,
1994 VEX_W_0F4B_P_2_LEN_1
,
2074 VEX_W_0F90_P_0_LEN_0
,
2075 VEX_W_0F90_P_2_LEN_0
,
2076 VEX_W_0F91_P_0_LEN_0
,
2077 VEX_W_0F91_P_2_LEN_0
,
2078 VEX_W_0F92_P_0_LEN_0
,
2079 VEX_W_0F92_P_2_LEN_0
,
2080 VEX_W_0F92_P_3_LEN_0
,
2081 VEX_W_0F93_P_0_LEN_0
,
2082 VEX_W_0F93_P_2_LEN_0
,
2083 VEX_W_0F93_P_3_LEN_0
,
2084 VEX_W_0F98_P_0_LEN_0
,
2085 VEX_W_0F98_P_2_LEN_0
,
2086 VEX_W_0F99_P_0_LEN_0
,
2087 VEX_W_0F99_P_2_LEN_0
,
2166 VEX_W_0F381A_P_2_M_0
,
2178 VEX_W_0F382A_P_2_M_0
,
2180 VEX_W_0F382C_P_2_M_0
,
2181 VEX_W_0F382D_P_2_M_0
,
2182 VEX_W_0F382E_P_2_M_0
,
2183 VEX_W_0F382F_P_2_M_0
,
2205 VEX_W_0F385A_P_2_M_0
,
2230 VEX_W_0F3A30_P_2_LEN_0
,
2231 VEX_W_0F3A31_P_2_LEN_0
,
2232 VEX_W_0F3A32_P_2_LEN_0
,
2233 VEX_W_0F3A33_P_2_LEN_0
,
2252 EVEX_W_0F10_P_1_M_0
,
2253 EVEX_W_0F10_P_1_M_1
,
2255 EVEX_W_0F10_P_3_M_0
,
2256 EVEX_W_0F10_P_3_M_1
,
2258 EVEX_W_0F11_P_1_M_0
,
2259 EVEX_W_0F11_P_1_M_1
,
2261 EVEX_W_0F11_P_3_M_0
,
2262 EVEX_W_0F11_P_3_M_1
,
2263 EVEX_W_0F12_P_0_M_0
,
2264 EVEX_W_0F12_P_0_M_1
,
2274 EVEX_W_0F16_P_0_M_0
,
2275 EVEX_W_0F16_P_0_M_1
,
2346 EVEX_W_0F72_R_2_P_2
,
2347 EVEX_W_0F72_R_6_P_2
,
2348 EVEX_W_0F73_R_2_P_2
,
2349 EVEX_W_0F73_R_6_P_2
,
2457 EVEX_W_0F38C7_R_1_P_2
,
2458 EVEX_W_0F38C7_R_2_P_2
,
2459 EVEX_W_0F38C7_R_5_P_2
,
2460 EVEX_W_0F38C7_R_6_P_2
,
2501 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2510 unsigned int prefix_requirement
;
2513 /* Upper case letters in the instruction names here are macros.
2514 'A' => print 'b' if no register operands or suffix_always is true
2515 'B' => print 'b' if suffix_always is true
2516 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2518 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2519 suffix_always is true
2520 'E' => print 'e' if 32-bit form of jcxz
2521 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2522 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2523 'H' => print ",pt" or ",pn" branch hint
2524 'I' => honor following macro letter even in Intel mode (implemented only
2525 for some of the macro letters)
2527 'K' => print 'd' or 'q' if rex prefix is present.
2528 'L' => print 'l' if suffix_always is true
2529 'M' => print 'r' if intel_mnemonic is false.
2530 'N' => print 'n' if instruction has no wait "prefix"
2531 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2532 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2533 or suffix_always is true. print 'q' if rex prefix is present.
2534 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2536 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2537 'S' => print 'w', 'l' or 'q' if suffix_always is true
2538 'T' => print 'q' in 64bit mode if instruction has no operand size
2539 prefix and behave as 'P' otherwise
2540 'U' => print 'q' in 64bit mode if instruction has no operand size
2541 prefix and behave as 'Q' otherwise
2542 'V' => print 'q' in 64bit mode if instruction has no operand size
2543 prefix and behave as 'S' otherwise
2544 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2545 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2547 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2548 '!' => change condition from true to false or from false to true.
2549 '%' => add 1 upper case letter to the macro.
2550 '^' => print 'w' or 'l' depending on operand size prefix or
2551 suffix_always is true (lcall/ljmp).
2552 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2553 on operand size prefix.
2554 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2555 has no operand size prefix for AMD64 ISA, behave as 'P'
2558 2 upper case letter macros:
2559 "XY" => print 'x' or 'y' if suffix_always is true or no register
2560 operands and no broadcast.
2561 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2562 register operands and no broadcast.
2563 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2564 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2565 or suffix_always is true
2566 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2567 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2568 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2569 "LW" => print 'd', 'q' depending on the VEX.W bit
2570 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2571 an operand size prefix, or suffix_always is true. print
2572 'q' if rex prefix is present.
2574 Many of the above letters print nothing in Intel mode. See "putop"
2577 Braces '{' and '}', and vertical bars '|', indicate alternative
2578 mnemonic strings for AT&T and Intel. */
2580 static const struct dis386 dis386
[] = {
2582 { "addB", { Ebh1
, Gb
}, 0 },
2583 { "addS", { Evh1
, Gv
}, 0 },
2584 { "addB", { Gb
, EbS
}, 0 },
2585 { "addS", { Gv
, EvS
}, 0 },
2586 { "addB", { AL
, Ib
}, 0 },
2587 { "addS", { eAX
, Iv
}, 0 },
2588 { X86_64_TABLE (X86_64_06
) },
2589 { X86_64_TABLE (X86_64_07
) },
2591 { "orB", { Ebh1
, Gb
}, 0 },
2592 { "orS", { Evh1
, Gv
}, 0 },
2593 { "orB", { Gb
, EbS
}, 0 },
2594 { "orS", { Gv
, EvS
}, 0 },
2595 { "orB", { AL
, Ib
}, 0 },
2596 { "orS", { eAX
, Iv
}, 0 },
2597 { X86_64_TABLE (X86_64_0D
) },
2598 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2600 { "adcB", { Ebh1
, Gb
}, 0 },
2601 { "adcS", { Evh1
, Gv
}, 0 },
2602 { "adcB", { Gb
, EbS
}, 0 },
2603 { "adcS", { Gv
, EvS
}, 0 },
2604 { "adcB", { AL
, Ib
}, 0 },
2605 { "adcS", { eAX
, Iv
}, 0 },
2606 { X86_64_TABLE (X86_64_16
) },
2607 { X86_64_TABLE (X86_64_17
) },
2609 { "sbbB", { Ebh1
, Gb
}, 0 },
2610 { "sbbS", { Evh1
, Gv
}, 0 },
2611 { "sbbB", { Gb
, EbS
}, 0 },
2612 { "sbbS", { Gv
, EvS
}, 0 },
2613 { "sbbB", { AL
, Ib
}, 0 },
2614 { "sbbS", { eAX
, Iv
}, 0 },
2615 { X86_64_TABLE (X86_64_1E
) },
2616 { X86_64_TABLE (X86_64_1F
) },
2618 { "andB", { Ebh1
, Gb
}, 0 },
2619 { "andS", { Evh1
, Gv
}, 0 },
2620 { "andB", { Gb
, EbS
}, 0 },
2621 { "andS", { Gv
, EvS
}, 0 },
2622 { "andB", { AL
, Ib
}, 0 },
2623 { "andS", { eAX
, Iv
}, 0 },
2624 { Bad_Opcode
}, /* SEG ES prefix */
2625 { X86_64_TABLE (X86_64_27
) },
2627 { "subB", { Ebh1
, Gb
}, 0 },
2628 { "subS", { Evh1
, Gv
}, 0 },
2629 { "subB", { Gb
, EbS
}, 0 },
2630 { "subS", { Gv
, EvS
}, 0 },
2631 { "subB", { AL
, Ib
}, 0 },
2632 { "subS", { eAX
, Iv
}, 0 },
2633 { Bad_Opcode
}, /* SEG CS prefix */
2634 { X86_64_TABLE (X86_64_2F
) },
2636 { "xorB", { Ebh1
, Gb
}, 0 },
2637 { "xorS", { Evh1
, Gv
}, 0 },
2638 { "xorB", { Gb
, EbS
}, 0 },
2639 { "xorS", { Gv
, EvS
}, 0 },
2640 { "xorB", { AL
, Ib
}, 0 },
2641 { "xorS", { eAX
, Iv
}, 0 },
2642 { Bad_Opcode
}, /* SEG SS prefix */
2643 { X86_64_TABLE (X86_64_37
) },
2645 { "cmpB", { Eb
, Gb
}, 0 },
2646 { "cmpS", { Ev
, Gv
}, 0 },
2647 { "cmpB", { Gb
, EbS
}, 0 },
2648 { "cmpS", { Gv
, EvS
}, 0 },
2649 { "cmpB", { AL
, Ib
}, 0 },
2650 { "cmpS", { eAX
, Iv
}, 0 },
2651 { Bad_Opcode
}, /* SEG DS prefix */
2652 { X86_64_TABLE (X86_64_3F
) },
2654 { "inc{S|}", { RMeAX
}, 0 },
2655 { "inc{S|}", { RMeCX
}, 0 },
2656 { "inc{S|}", { RMeDX
}, 0 },
2657 { "inc{S|}", { RMeBX
}, 0 },
2658 { "inc{S|}", { RMeSP
}, 0 },
2659 { "inc{S|}", { RMeBP
}, 0 },
2660 { "inc{S|}", { RMeSI
}, 0 },
2661 { "inc{S|}", { RMeDI
}, 0 },
2663 { "dec{S|}", { RMeAX
}, 0 },
2664 { "dec{S|}", { RMeCX
}, 0 },
2665 { "dec{S|}", { RMeDX
}, 0 },
2666 { "dec{S|}", { RMeBX
}, 0 },
2667 { "dec{S|}", { RMeSP
}, 0 },
2668 { "dec{S|}", { RMeBP
}, 0 },
2669 { "dec{S|}", { RMeSI
}, 0 },
2670 { "dec{S|}", { RMeDI
}, 0 },
2672 { "pushV", { RMrAX
}, 0 },
2673 { "pushV", { RMrCX
}, 0 },
2674 { "pushV", { RMrDX
}, 0 },
2675 { "pushV", { RMrBX
}, 0 },
2676 { "pushV", { RMrSP
}, 0 },
2677 { "pushV", { RMrBP
}, 0 },
2678 { "pushV", { RMrSI
}, 0 },
2679 { "pushV", { RMrDI
}, 0 },
2681 { "popV", { RMrAX
}, 0 },
2682 { "popV", { RMrCX
}, 0 },
2683 { "popV", { RMrDX
}, 0 },
2684 { "popV", { RMrBX
}, 0 },
2685 { "popV", { RMrSP
}, 0 },
2686 { "popV", { RMrBP
}, 0 },
2687 { "popV", { RMrSI
}, 0 },
2688 { "popV", { RMrDI
}, 0 },
2690 { X86_64_TABLE (X86_64_60
) },
2691 { X86_64_TABLE (X86_64_61
) },
2692 { X86_64_TABLE (X86_64_62
) },
2693 { X86_64_TABLE (X86_64_63
) },
2694 { Bad_Opcode
}, /* seg fs */
2695 { Bad_Opcode
}, /* seg gs */
2696 { Bad_Opcode
}, /* op size prefix */
2697 { Bad_Opcode
}, /* adr size prefix */
2699 { "pushT", { sIv
}, 0 },
2700 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2701 { "pushT", { sIbT
}, 0 },
2702 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2703 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2704 { X86_64_TABLE (X86_64_6D
) },
2705 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2706 { X86_64_TABLE (X86_64_6F
) },
2708 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2709 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2710 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2711 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2712 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2713 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2714 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2715 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2717 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2718 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2719 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2720 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2721 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2722 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2723 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2724 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2726 { REG_TABLE (REG_80
) },
2727 { REG_TABLE (REG_81
) },
2728 { X86_64_TABLE (X86_64_82
) },
2729 { REG_TABLE (REG_83
) },
2730 { "testB", { Eb
, Gb
}, 0 },
2731 { "testS", { Ev
, Gv
}, 0 },
2732 { "xchgB", { Ebh2
, Gb
}, 0 },
2733 { "xchgS", { Evh2
, Gv
}, 0 },
2735 { "movB", { Ebh3
, Gb
}, 0 },
2736 { "movS", { Evh3
, Gv
}, 0 },
2737 { "movB", { Gb
, EbS
}, 0 },
2738 { "movS", { Gv
, EvS
}, 0 },
2739 { "movD", { Sv
, Sw
}, 0 },
2740 { MOD_TABLE (MOD_8D
) },
2741 { "movD", { Sw
, Sv
}, 0 },
2742 { REG_TABLE (REG_8F
) },
2744 { PREFIX_TABLE (PREFIX_90
) },
2745 { "xchgS", { RMeCX
, eAX
}, 0 },
2746 { "xchgS", { RMeDX
, eAX
}, 0 },
2747 { "xchgS", { RMeBX
, eAX
}, 0 },
2748 { "xchgS", { RMeSP
, eAX
}, 0 },
2749 { "xchgS", { RMeBP
, eAX
}, 0 },
2750 { "xchgS", { RMeSI
, eAX
}, 0 },
2751 { "xchgS", { RMeDI
, eAX
}, 0 },
2753 { "cW{t|}R", { XX
}, 0 },
2754 { "cR{t|}O", { XX
}, 0 },
2755 { X86_64_TABLE (X86_64_9A
) },
2756 { Bad_Opcode
}, /* fwait */
2757 { "pushfT", { XX
}, 0 },
2758 { "popfT", { XX
}, 0 },
2759 { "sahf", { XX
}, 0 },
2760 { "lahf", { XX
}, 0 },
2762 { "mov%LB", { AL
, Ob
}, 0 },
2763 { "mov%LS", { eAX
, Ov
}, 0 },
2764 { "mov%LB", { Ob
, AL
}, 0 },
2765 { "mov%LS", { Ov
, eAX
}, 0 },
2766 { "movs{b|}", { Ybr
, Xb
}, 0 },
2767 { "movs{R|}", { Yvr
, Xv
}, 0 },
2768 { "cmps{b|}", { Xb
, Yb
}, 0 },
2769 { "cmps{R|}", { Xv
, Yv
}, 0 },
2771 { "testB", { AL
, Ib
}, 0 },
2772 { "testS", { eAX
, Iv
}, 0 },
2773 { "stosB", { Ybr
, AL
}, 0 },
2774 { "stosS", { Yvr
, eAX
}, 0 },
2775 { "lodsB", { ALr
, Xb
}, 0 },
2776 { "lodsS", { eAXr
, Xv
}, 0 },
2777 { "scasB", { AL
, Yb
}, 0 },
2778 { "scasS", { eAX
, Yv
}, 0 },
2780 { "movB", { RMAL
, Ib
}, 0 },
2781 { "movB", { RMCL
, Ib
}, 0 },
2782 { "movB", { RMDL
, Ib
}, 0 },
2783 { "movB", { RMBL
, Ib
}, 0 },
2784 { "movB", { RMAH
, Ib
}, 0 },
2785 { "movB", { RMCH
, Ib
}, 0 },
2786 { "movB", { RMDH
, Ib
}, 0 },
2787 { "movB", { RMBH
, Ib
}, 0 },
2789 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2790 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2791 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2792 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2793 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2794 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2795 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2796 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2798 { REG_TABLE (REG_C0
) },
2799 { REG_TABLE (REG_C1
) },
2800 { "retT", { Iw
, BND
}, 0 },
2801 { "retT", { BND
}, 0 },
2802 { X86_64_TABLE (X86_64_C4
) },
2803 { X86_64_TABLE (X86_64_C5
) },
2804 { REG_TABLE (REG_C6
) },
2805 { REG_TABLE (REG_C7
) },
2807 { "enterT", { Iw
, Ib
}, 0 },
2808 { "leaveT", { XX
}, 0 },
2809 { "Jret{|f}P", { Iw
}, 0 },
2810 { "Jret{|f}P", { XX
}, 0 },
2811 { "int3", { XX
}, 0 },
2812 { "int", { Ib
}, 0 },
2813 { X86_64_TABLE (X86_64_CE
) },
2814 { "iret%LP", { XX
}, 0 },
2816 { REG_TABLE (REG_D0
) },
2817 { REG_TABLE (REG_D1
) },
2818 { REG_TABLE (REG_D2
) },
2819 { REG_TABLE (REG_D3
) },
2820 { X86_64_TABLE (X86_64_D4
) },
2821 { X86_64_TABLE (X86_64_D5
) },
2823 { "xlat", { DSBX
}, 0 },
2834 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2835 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2836 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2837 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2838 { "inB", { AL
, Ib
}, 0 },
2839 { "inG", { zAX
, Ib
}, 0 },
2840 { "outB", { Ib
, AL
}, 0 },
2841 { "outG", { Ib
, zAX
}, 0 },
2843 { X86_64_TABLE (X86_64_E8
) },
2844 { X86_64_TABLE (X86_64_E9
) },
2845 { X86_64_TABLE (X86_64_EA
) },
2846 { "jmp", { Jb
, BND
}, 0 },
2847 { "inB", { AL
, indirDX
}, 0 },
2848 { "inG", { zAX
, indirDX
}, 0 },
2849 { "outB", { indirDX
, AL
}, 0 },
2850 { "outG", { indirDX
, zAX
}, 0 },
2852 { Bad_Opcode
}, /* lock prefix */
2853 { "icebp", { XX
}, 0 },
2854 { Bad_Opcode
}, /* repne */
2855 { Bad_Opcode
}, /* repz */
2856 { "hlt", { XX
}, 0 },
2857 { "cmc", { XX
}, 0 },
2858 { REG_TABLE (REG_F6
) },
2859 { REG_TABLE (REG_F7
) },
2861 { "clc", { XX
}, 0 },
2862 { "stc", { XX
}, 0 },
2863 { "cli", { XX
}, 0 },
2864 { "sti", { XX
}, 0 },
2865 { "cld", { XX
}, 0 },
2866 { "std", { XX
}, 0 },
2867 { REG_TABLE (REG_FE
) },
2868 { REG_TABLE (REG_FF
) },
2871 static const struct dis386 dis386_twobyte
[] = {
2873 { REG_TABLE (REG_0F00
) },
2874 { REG_TABLE (REG_0F01
) },
2875 { "larS", { Gv
, Ew
}, 0 },
2876 { "lslS", { Gv
, Ew
}, 0 },
2878 { "syscall", { XX
}, 0 },
2879 { "clts", { XX
}, 0 },
2880 { "sysret%LP", { XX
}, 0 },
2882 { "invd", { XX
}, 0 },
2883 { PREFIX_TABLE (PREFIX_0F09
) },
2885 { "ud2", { XX
}, 0 },
2887 { REG_TABLE (REG_0F0D
) },
2888 { "femms", { XX
}, 0 },
2889 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2891 { PREFIX_TABLE (PREFIX_0F10
) },
2892 { PREFIX_TABLE (PREFIX_0F11
) },
2893 { PREFIX_TABLE (PREFIX_0F12
) },
2894 { MOD_TABLE (MOD_0F13
) },
2895 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2896 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2897 { PREFIX_TABLE (PREFIX_0F16
) },
2898 { MOD_TABLE (MOD_0F17
) },
2900 { REG_TABLE (REG_0F18
) },
2901 { "nopQ", { Ev
}, 0 },
2902 { PREFIX_TABLE (PREFIX_0F1A
) },
2903 { PREFIX_TABLE (PREFIX_0F1B
) },
2904 { PREFIX_TABLE (PREFIX_0F1C
) },
2905 { "nopQ", { Ev
}, 0 },
2906 { PREFIX_TABLE (PREFIX_0F1E
) },
2907 { "nopQ", { Ev
}, 0 },
2909 { "movZ", { Rm
, Cm
}, 0 },
2910 { "movZ", { Rm
, Dm
}, 0 },
2911 { "movZ", { Cm
, Rm
}, 0 },
2912 { "movZ", { Dm
, Rm
}, 0 },
2913 { MOD_TABLE (MOD_0F24
) },
2915 { MOD_TABLE (MOD_0F26
) },
2918 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2919 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2920 { PREFIX_TABLE (PREFIX_0F2A
) },
2921 { PREFIX_TABLE (PREFIX_0F2B
) },
2922 { PREFIX_TABLE (PREFIX_0F2C
) },
2923 { PREFIX_TABLE (PREFIX_0F2D
) },
2924 { PREFIX_TABLE (PREFIX_0F2E
) },
2925 { PREFIX_TABLE (PREFIX_0F2F
) },
2927 { "wrmsr", { XX
}, 0 },
2928 { "rdtsc", { XX
}, 0 },
2929 { "rdmsr", { XX
}, 0 },
2930 { "rdpmc", { XX
}, 0 },
2931 { "sysenter", { XX
}, 0 },
2932 { "sysexit", { XX
}, 0 },
2934 { "getsec", { XX
}, 0 },
2936 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2938 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2945 { "cmovoS", { Gv
, Ev
}, 0 },
2946 { "cmovnoS", { Gv
, Ev
}, 0 },
2947 { "cmovbS", { Gv
, Ev
}, 0 },
2948 { "cmovaeS", { Gv
, Ev
}, 0 },
2949 { "cmoveS", { Gv
, Ev
}, 0 },
2950 { "cmovneS", { Gv
, Ev
}, 0 },
2951 { "cmovbeS", { Gv
, Ev
}, 0 },
2952 { "cmovaS", { Gv
, Ev
}, 0 },
2954 { "cmovsS", { Gv
, Ev
}, 0 },
2955 { "cmovnsS", { Gv
, Ev
}, 0 },
2956 { "cmovpS", { Gv
, Ev
}, 0 },
2957 { "cmovnpS", { Gv
, Ev
}, 0 },
2958 { "cmovlS", { Gv
, Ev
}, 0 },
2959 { "cmovgeS", { Gv
, Ev
}, 0 },
2960 { "cmovleS", { Gv
, Ev
}, 0 },
2961 { "cmovgS", { Gv
, Ev
}, 0 },
2963 { MOD_TABLE (MOD_0F51
) },
2964 { PREFIX_TABLE (PREFIX_0F51
) },
2965 { PREFIX_TABLE (PREFIX_0F52
) },
2966 { PREFIX_TABLE (PREFIX_0F53
) },
2967 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2968 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2969 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2970 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2972 { PREFIX_TABLE (PREFIX_0F58
) },
2973 { PREFIX_TABLE (PREFIX_0F59
) },
2974 { PREFIX_TABLE (PREFIX_0F5A
) },
2975 { PREFIX_TABLE (PREFIX_0F5B
) },
2976 { PREFIX_TABLE (PREFIX_0F5C
) },
2977 { PREFIX_TABLE (PREFIX_0F5D
) },
2978 { PREFIX_TABLE (PREFIX_0F5E
) },
2979 { PREFIX_TABLE (PREFIX_0F5F
) },
2981 { PREFIX_TABLE (PREFIX_0F60
) },
2982 { PREFIX_TABLE (PREFIX_0F61
) },
2983 { PREFIX_TABLE (PREFIX_0F62
) },
2984 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2985 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2986 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2987 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2988 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2990 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2991 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2992 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2993 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2994 { PREFIX_TABLE (PREFIX_0F6C
) },
2995 { PREFIX_TABLE (PREFIX_0F6D
) },
2996 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2997 { PREFIX_TABLE (PREFIX_0F6F
) },
2999 { PREFIX_TABLE (PREFIX_0F70
) },
3000 { REG_TABLE (REG_0F71
) },
3001 { REG_TABLE (REG_0F72
) },
3002 { REG_TABLE (REG_0F73
) },
3003 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
3004 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
3005 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
3006 { "emms", { XX
}, PREFIX_OPCODE
},
3008 { PREFIX_TABLE (PREFIX_0F78
) },
3009 { PREFIX_TABLE (PREFIX_0F79
) },
3012 { PREFIX_TABLE (PREFIX_0F7C
) },
3013 { PREFIX_TABLE (PREFIX_0F7D
) },
3014 { PREFIX_TABLE (PREFIX_0F7E
) },
3015 { PREFIX_TABLE (PREFIX_0F7F
) },
3017 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
3018 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
3019 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
3020 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3021 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3022 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
3023 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3024 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
3026 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
3027 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
3028 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
3029 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
3030 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
3031 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3032 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
3033 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
3035 { "seto", { Eb
}, 0 },
3036 { "setno", { Eb
}, 0 },
3037 { "setb", { Eb
}, 0 },
3038 { "setae", { Eb
}, 0 },
3039 { "sete", { Eb
}, 0 },
3040 { "setne", { Eb
}, 0 },
3041 { "setbe", { Eb
}, 0 },
3042 { "seta", { Eb
}, 0 },
3044 { "sets", { Eb
}, 0 },
3045 { "setns", { Eb
}, 0 },
3046 { "setp", { Eb
}, 0 },
3047 { "setnp", { Eb
}, 0 },
3048 { "setl", { Eb
}, 0 },
3049 { "setge", { Eb
}, 0 },
3050 { "setle", { Eb
}, 0 },
3051 { "setg", { Eb
}, 0 },
3053 { "pushT", { fs
}, 0 },
3054 { "popT", { fs
}, 0 },
3055 { "cpuid", { XX
}, 0 },
3056 { "btS", { Ev
, Gv
}, 0 },
3057 { "shldS", { Ev
, Gv
, Ib
}, 0 },
3058 { "shldS", { Ev
, Gv
, CL
}, 0 },
3059 { REG_TABLE (REG_0FA6
) },
3060 { REG_TABLE (REG_0FA7
) },
3062 { "pushT", { gs
}, 0 },
3063 { "popT", { gs
}, 0 },
3064 { "rsm", { XX
}, 0 },
3065 { "btsS", { Evh1
, Gv
}, 0 },
3066 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
3067 { "shrdS", { Ev
, Gv
, CL
}, 0 },
3068 { REG_TABLE (REG_0FAE
) },
3069 { "imulS", { Gv
, Ev
}, 0 },
3071 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
3072 { "cmpxchgS", { Evh1
, Gv
}, 0 },
3073 { MOD_TABLE (MOD_0FB2
) },
3074 { "btrS", { Evh1
, Gv
}, 0 },
3075 { MOD_TABLE (MOD_0FB4
) },
3076 { MOD_TABLE (MOD_0FB5
) },
3077 { "movz{bR|x}", { Gv
, Eb
}, 0 },
3078 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
3080 { PREFIX_TABLE (PREFIX_0FB8
) },
3081 { "ud1S", { Gv
, Ev
}, 0 },
3082 { REG_TABLE (REG_0FBA
) },
3083 { "btcS", { Evh1
, Gv
}, 0 },
3084 { PREFIX_TABLE (PREFIX_0FBC
) },
3085 { PREFIX_TABLE (PREFIX_0FBD
) },
3086 { "movs{bR|x}", { Gv
, Eb
}, 0 },
3087 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
3089 { "xaddB", { Ebh1
, Gb
}, 0 },
3090 { "xaddS", { Evh1
, Gv
}, 0 },
3091 { PREFIX_TABLE (PREFIX_0FC2
) },
3092 { MOD_TABLE (MOD_0FC3
) },
3093 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
3094 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
3095 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3096 { REG_TABLE (REG_0FC7
) },
3098 { "bswap", { RMeAX
}, 0 },
3099 { "bswap", { RMeCX
}, 0 },
3100 { "bswap", { RMeDX
}, 0 },
3101 { "bswap", { RMeBX
}, 0 },
3102 { "bswap", { RMeSP
}, 0 },
3103 { "bswap", { RMeBP
}, 0 },
3104 { "bswap", { RMeSI
}, 0 },
3105 { "bswap", { RMeDI
}, 0 },
3107 { PREFIX_TABLE (PREFIX_0FD0
) },
3108 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
3109 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
3110 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
3111 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
3112 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
3113 { PREFIX_TABLE (PREFIX_0FD6
) },
3114 { MOD_TABLE (MOD_0FD7
) },
3116 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
3117 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
3118 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
3119 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
3120 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
3121 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
3122 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
3123 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
3125 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
3126 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
3127 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
3128 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
3129 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
3130 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
3131 { PREFIX_TABLE (PREFIX_0FE6
) },
3132 { PREFIX_TABLE (PREFIX_0FE7
) },
3134 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
3135 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
3136 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
3137 { "por", { MX
, EM
}, PREFIX_OPCODE
},
3138 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
3139 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
3140 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
3141 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
3143 { PREFIX_TABLE (PREFIX_0FF0
) },
3144 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
3145 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
3146 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
3147 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
3148 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
3149 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
3150 { PREFIX_TABLE (PREFIX_0FF7
) },
3152 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
3153 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
3154 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
3155 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
3156 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
3157 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
3158 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
3159 { "ud0S", { Gv
, Ev
}, 0 },
3162 static const unsigned char onebyte_has_modrm
[256] = {
3163 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3164 /* ------------------------------- */
3165 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3166 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3167 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3168 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3169 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3170 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3171 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3172 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3173 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3174 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3175 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3176 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3177 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3178 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3179 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3180 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3181 /* ------------------------------- */
3182 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3185 static const unsigned char twobyte_has_modrm
[256] = {
3186 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3187 /* ------------------------------- */
3188 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3189 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3190 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3191 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3192 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3193 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3194 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3195 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3196 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3197 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3198 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3199 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
3200 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3201 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3202 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3203 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
3204 /* ------------------------------- */
3205 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3208 static char obuf
[100];
3210 static char *mnemonicendp
;
3211 static char scratchbuf
[100];
3212 static unsigned char *start_codep
;
3213 static unsigned char *insn_codep
;
3214 static unsigned char *codep
;
3215 static unsigned char *end_codep
;
3216 static int last_lock_prefix
;
3217 static int last_repz_prefix
;
3218 static int last_repnz_prefix
;
3219 static int last_data_prefix
;
3220 static int last_addr_prefix
;
3221 static int last_rex_prefix
;
3222 static int last_seg_prefix
;
3223 static int fwait_prefix
;
3224 /* The active segment register prefix. */
3225 static int active_seg_prefix
;
3226 #define MAX_CODE_LENGTH 15
3227 /* We can up to 14 prefixes since the maximum instruction length is
3229 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3230 static disassemble_info
*the_info
;
3238 static unsigned char need_modrm
;
3248 int register_specifier
;
3255 int mask_register_specifier
;
3261 static unsigned char need_vex
;
3262 static unsigned char need_vex_reg
;
3263 static unsigned char vex_w_done
;
3271 /* If we are accessing mod/rm/reg without need_modrm set, then the
3272 values are stale. Hitting this abort likely indicates that you
3273 need to update onebyte_has_modrm or twobyte_has_modrm. */
3274 #define MODRM_CHECK if (!need_modrm) abort ()
3276 static const char **names64
;
3277 static const char **names32
;
3278 static const char **names16
;
3279 static const char **names8
;
3280 static const char **names8rex
;
3281 static const char **names_seg
;
3282 static const char *index64
;
3283 static const char *index32
;
3284 static const char **index16
;
3285 static const char **names_bnd
;
3287 static const char *intel_names64
[] = {
3288 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3289 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3291 static const char *intel_names32
[] = {
3292 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3293 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3295 static const char *intel_names16
[] = {
3296 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3297 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3299 static const char *intel_names8
[] = {
3300 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3302 static const char *intel_names8rex
[] = {
3303 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3304 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3306 static const char *intel_names_seg
[] = {
3307 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3309 static const char *intel_index64
= "riz";
3310 static const char *intel_index32
= "eiz";
3311 static const char *intel_index16
[] = {
3312 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3315 static const char *att_names64
[] = {
3316 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3317 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3319 static const char *att_names32
[] = {
3320 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3321 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3323 static const char *att_names16
[] = {
3324 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3325 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3327 static const char *att_names8
[] = {
3328 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3330 static const char *att_names8rex
[] = {
3331 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3332 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3334 static const char *att_names_seg
[] = {
3335 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3337 static const char *att_index64
= "%riz";
3338 static const char *att_index32
= "%eiz";
3339 static const char *att_index16
[] = {
3340 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3343 static const char **names_mm
;
3344 static const char *intel_names_mm
[] = {
3345 "mm0", "mm1", "mm2", "mm3",
3346 "mm4", "mm5", "mm6", "mm7"
3348 static const char *att_names_mm
[] = {
3349 "%mm0", "%mm1", "%mm2", "%mm3",
3350 "%mm4", "%mm5", "%mm6", "%mm7"
3353 static const char *intel_names_bnd
[] = {
3354 "bnd0", "bnd1", "bnd2", "bnd3"
3357 static const char *att_names_bnd
[] = {
3358 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3361 static const char **names_xmm
;
3362 static const char *intel_names_xmm
[] = {
3363 "xmm0", "xmm1", "xmm2", "xmm3",
3364 "xmm4", "xmm5", "xmm6", "xmm7",
3365 "xmm8", "xmm9", "xmm10", "xmm11",
3366 "xmm12", "xmm13", "xmm14", "xmm15",
3367 "xmm16", "xmm17", "xmm18", "xmm19",
3368 "xmm20", "xmm21", "xmm22", "xmm23",
3369 "xmm24", "xmm25", "xmm26", "xmm27",
3370 "xmm28", "xmm29", "xmm30", "xmm31"
3372 static const char *att_names_xmm
[] = {
3373 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3374 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3375 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3376 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3377 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3378 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3379 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3380 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3383 static const char **names_ymm
;
3384 static const char *intel_names_ymm
[] = {
3385 "ymm0", "ymm1", "ymm2", "ymm3",
3386 "ymm4", "ymm5", "ymm6", "ymm7",
3387 "ymm8", "ymm9", "ymm10", "ymm11",
3388 "ymm12", "ymm13", "ymm14", "ymm15",
3389 "ymm16", "ymm17", "ymm18", "ymm19",
3390 "ymm20", "ymm21", "ymm22", "ymm23",
3391 "ymm24", "ymm25", "ymm26", "ymm27",
3392 "ymm28", "ymm29", "ymm30", "ymm31"
3394 static const char *att_names_ymm
[] = {
3395 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3396 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3397 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3398 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3399 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3400 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3401 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3402 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3405 static const char **names_zmm
;
3406 static const char *intel_names_zmm
[] = {
3407 "zmm0", "zmm1", "zmm2", "zmm3",
3408 "zmm4", "zmm5", "zmm6", "zmm7",
3409 "zmm8", "zmm9", "zmm10", "zmm11",
3410 "zmm12", "zmm13", "zmm14", "zmm15",
3411 "zmm16", "zmm17", "zmm18", "zmm19",
3412 "zmm20", "zmm21", "zmm22", "zmm23",
3413 "zmm24", "zmm25", "zmm26", "zmm27",
3414 "zmm28", "zmm29", "zmm30", "zmm31"
3416 static const char *att_names_zmm
[] = {
3417 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3418 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3419 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3420 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3421 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3422 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3423 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3424 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3427 static const char **names_mask
;
3428 static const char *intel_names_mask
[] = {
3429 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3431 static const char *att_names_mask
[] = {
3432 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3435 static const char *names_rounding
[] =
3443 static const struct dis386 reg_table
[][8] = {
3446 { "addA", { Ebh1
, Ib
}, 0 },
3447 { "orA", { Ebh1
, Ib
}, 0 },
3448 { "adcA", { Ebh1
, Ib
}, 0 },
3449 { "sbbA", { Ebh1
, Ib
}, 0 },
3450 { "andA", { Ebh1
, Ib
}, 0 },
3451 { "subA", { Ebh1
, Ib
}, 0 },
3452 { "xorA", { Ebh1
, Ib
}, 0 },
3453 { "cmpA", { Eb
, Ib
}, 0 },
3457 { "addQ", { Evh1
, Iv
}, 0 },
3458 { "orQ", { Evh1
, Iv
}, 0 },
3459 { "adcQ", { Evh1
, Iv
}, 0 },
3460 { "sbbQ", { Evh1
, Iv
}, 0 },
3461 { "andQ", { Evh1
, Iv
}, 0 },
3462 { "subQ", { Evh1
, Iv
}, 0 },
3463 { "xorQ", { Evh1
, Iv
}, 0 },
3464 { "cmpQ", { Ev
, Iv
}, 0 },
3468 { "addQ", { Evh1
, sIb
}, 0 },
3469 { "orQ", { Evh1
, sIb
}, 0 },
3470 { "adcQ", { Evh1
, sIb
}, 0 },
3471 { "sbbQ", { Evh1
, sIb
}, 0 },
3472 { "andQ", { Evh1
, sIb
}, 0 },
3473 { "subQ", { Evh1
, sIb
}, 0 },
3474 { "xorQ", { Evh1
, sIb
}, 0 },
3475 { "cmpQ", { Ev
, sIb
}, 0 },
3479 { "popU", { stackEv
}, 0 },
3480 { XOP_8F_TABLE (XOP_09
) },
3484 { XOP_8F_TABLE (XOP_09
) },
3488 { "rolA", { Eb
, Ib
}, 0 },
3489 { "rorA", { Eb
, Ib
}, 0 },
3490 { "rclA", { Eb
, Ib
}, 0 },
3491 { "rcrA", { Eb
, Ib
}, 0 },
3492 { "shlA", { Eb
, Ib
}, 0 },
3493 { "shrA", { Eb
, Ib
}, 0 },
3494 { "shlA", { Eb
, Ib
}, 0 },
3495 { "sarA", { Eb
, Ib
}, 0 },
3499 { "rolQ", { Ev
, Ib
}, 0 },
3500 { "rorQ", { Ev
, Ib
}, 0 },
3501 { "rclQ", { Ev
, Ib
}, 0 },
3502 { "rcrQ", { Ev
, Ib
}, 0 },
3503 { "shlQ", { Ev
, Ib
}, 0 },
3504 { "shrQ", { Ev
, Ib
}, 0 },
3505 { "shlQ", { Ev
, Ib
}, 0 },
3506 { "sarQ", { Ev
, Ib
}, 0 },
3510 { "movA", { Ebh3
, Ib
}, 0 },
3517 { MOD_TABLE (MOD_C6_REG_7
) },
3521 { "movQ", { Evh3
, Iv
}, 0 },
3528 { MOD_TABLE (MOD_C7_REG_7
) },
3532 { "rolA", { Eb
, I1
}, 0 },
3533 { "rorA", { Eb
, I1
}, 0 },
3534 { "rclA", { Eb
, I1
}, 0 },
3535 { "rcrA", { Eb
, I1
}, 0 },
3536 { "shlA", { Eb
, I1
}, 0 },
3537 { "shrA", { Eb
, I1
}, 0 },
3538 { "shlA", { Eb
, I1
}, 0 },
3539 { "sarA", { Eb
, I1
}, 0 },
3543 { "rolQ", { Ev
, I1
}, 0 },
3544 { "rorQ", { Ev
, I1
}, 0 },
3545 { "rclQ", { Ev
, I1
}, 0 },
3546 { "rcrQ", { Ev
, I1
}, 0 },
3547 { "shlQ", { Ev
, I1
}, 0 },
3548 { "shrQ", { Ev
, I1
}, 0 },
3549 { "shlQ", { Ev
, I1
}, 0 },
3550 { "sarQ", { Ev
, I1
}, 0 },
3554 { "rolA", { Eb
, CL
}, 0 },
3555 { "rorA", { Eb
, CL
}, 0 },
3556 { "rclA", { Eb
, CL
}, 0 },
3557 { "rcrA", { Eb
, CL
}, 0 },
3558 { "shlA", { Eb
, CL
}, 0 },
3559 { "shrA", { Eb
, CL
}, 0 },
3560 { "shlA", { Eb
, CL
}, 0 },
3561 { "sarA", { Eb
, CL
}, 0 },
3565 { "rolQ", { Ev
, CL
}, 0 },
3566 { "rorQ", { Ev
, CL
}, 0 },
3567 { "rclQ", { Ev
, CL
}, 0 },
3568 { "rcrQ", { Ev
, CL
}, 0 },
3569 { "shlQ", { Ev
, CL
}, 0 },
3570 { "shrQ", { Ev
, CL
}, 0 },
3571 { "shlQ", { Ev
, CL
}, 0 },
3572 { "sarQ", { Ev
, CL
}, 0 },
3576 { "testA", { Eb
, Ib
}, 0 },
3577 { "testA", { Eb
, Ib
}, 0 },
3578 { "notA", { Ebh1
}, 0 },
3579 { "negA", { Ebh1
}, 0 },
3580 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3581 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3582 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3583 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3587 { "testQ", { Ev
, Iv
}, 0 },
3588 { "testQ", { Ev
, Iv
}, 0 },
3589 { "notQ", { Evh1
}, 0 },
3590 { "negQ", { Evh1
}, 0 },
3591 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3592 { "imulQ", { Ev
}, 0 },
3593 { "divQ", { Ev
}, 0 },
3594 { "idivQ", { Ev
}, 0 },
3598 { "incA", { Ebh1
}, 0 },
3599 { "decA", { Ebh1
}, 0 },
3603 { "incQ", { Evh1
}, 0 },
3604 { "decQ", { Evh1
}, 0 },
3605 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3606 { MOD_TABLE (MOD_FF_REG_3
) },
3607 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3608 { MOD_TABLE (MOD_FF_REG_5
) },
3609 { "pushU", { stackEv
}, 0 },
3614 { "sldtD", { Sv
}, 0 },
3615 { "strD", { Sv
}, 0 },
3616 { "lldt", { Ew
}, 0 },
3617 { "ltr", { Ew
}, 0 },
3618 { "verr", { Ew
}, 0 },
3619 { "verw", { Ew
}, 0 },
3625 { MOD_TABLE (MOD_0F01_REG_0
) },
3626 { MOD_TABLE (MOD_0F01_REG_1
) },
3627 { MOD_TABLE (MOD_0F01_REG_2
) },
3628 { MOD_TABLE (MOD_0F01_REG_3
) },
3629 { "smswD", { Sv
}, 0 },
3630 { MOD_TABLE (MOD_0F01_REG_5
) },
3631 { "lmsw", { Ew
}, 0 },
3632 { MOD_TABLE (MOD_0F01_REG_7
) },
3636 { "prefetch", { Mb
}, 0 },
3637 { "prefetchw", { Mb
}, 0 },
3638 { "prefetchwt1", { Mb
}, 0 },
3639 { "prefetch", { Mb
}, 0 },
3640 { "prefetch", { Mb
}, 0 },
3641 { "prefetch", { Mb
}, 0 },
3642 { "prefetch", { Mb
}, 0 },
3643 { "prefetch", { Mb
}, 0 },
3647 { MOD_TABLE (MOD_0F18_REG_0
) },
3648 { MOD_TABLE (MOD_0F18_REG_1
) },
3649 { MOD_TABLE (MOD_0F18_REG_2
) },
3650 { MOD_TABLE (MOD_0F18_REG_3
) },
3651 { MOD_TABLE (MOD_0F18_REG_4
) },
3652 { MOD_TABLE (MOD_0F18_REG_5
) },
3653 { MOD_TABLE (MOD_0F18_REG_6
) },
3654 { MOD_TABLE (MOD_0F18_REG_7
) },
3656 /* REG_0F1C_MOD_0 */
3658 { "cldemote", { Mb
}, 0 },
3659 { "nopQ", { Ev
}, 0 },
3660 { "nopQ", { Ev
}, 0 },
3661 { "nopQ", { Ev
}, 0 },
3662 { "nopQ", { Ev
}, 0 },
3663 { "nopQ", { Ev
}, 0 },
3664 { "nopQ", { Ev
}, 0 },
3665 { "nopQ", { Ev
}, 0 },
3667 /* REG_0F1E_MOD_3 */
3669 { "nopQ", { Ev
}, 0 },
3670 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3671 { "nopQ", { Ev
}, 0 },
3672 { "nopQ", { Ev
}, 0 },
3673 { "nopQ", { Ev
}, 0 },
3674 { "nopQ", { Ev
}, 0 },
3675 { "nopQ", { Ev
}, 0 },
3676 { RM_TABLE (RM_0F1E_MOD_3_REG_7
) },
3682 { MOD_TABLE (MOD_0F71_REG_2
) },
3684 { MOD_TABLE (MOD_0F71_REG_4
) },
3686 { MOD_TABLE (MOD_0F71_REG_6
) },
3692 { MOD_TABLE (MOD_0F72_REG_2
) },
3694 { MOD_TABLE (MOD_0F72_REG_4
) },
3696 { MOD_TABLE (MOD_0F72_REG_6
) },
3702 { MOD_TABLE (MOD_0F73_REG_2
) },
3703 { MOD_TABLE (MOD_0F73_REG_3
) },
3706 { MOD_TABLE (MOD_0F73_REG_6
) },
3707 { MOD_TABLE (MOD_0F73_REG_7
) },
3711 { "montmul", { { OP_0f07
, 0 } }, 0 },
3712 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3713 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3717 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3718 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3719 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3720 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3721 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3722 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3726 { MOD_TABLE (MOD_0FAE_REG_0
) },
3727 { MOD_TABLE (MOD_0FAE_REG_1
) },
3728 { MOD_TABLE (MOD_0FAE_REG_2
) },
3729 { MOD_TABLE (MOD_0FAE_REG_3
) },
3730 { MOD_TABLE (MOD_0FAE_REG_4
) },
3731 { MOD_TABLE (MOD_0FAE_REG_5
) },
3732 { MOD_TABLE (MOD_0FAE_REG_6
) },
3733 { MOD_TABLE (MOD_0FAE_REG_7
) },
3741 { "btQ", { Ev
, Ib
}, 0 },
3742 { "btsQ", { Evh1
, Ib
}, 0 },
3743 { "btrQ", { Evh1
, Ib
}, 0 },
3744 { "btcQ", { Evh1
, Ib
}, 0 },
3749 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3751 { MOD_TABLE (MOD_0FC7_REG_3
) },
3752 { MOD_TABLE (MOD_0FC7_REG_4
) },
3753 { MOD_TABLE (MOD_0FC7_REG_5
) },
3754 { MOD_TABLE (MOD_0FC7_REG_6
) },
3755 { MOD_TABLE (MOD_0FC7_REG_7
) },
3761 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3763 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3765 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3771 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3773 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3775 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3781 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3782 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3785 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3786 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3792 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3793 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3795 /* REG_VEX_0F38F3 */
3798 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3799 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3800 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3804 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3805 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3809 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3810 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3812 /* REG_XOP_TBM_01 */
3815 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3816 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3817 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3818 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3819 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3820 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3821 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3823 /* REG_XOP_TBM_02 */
3826 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3831 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3833 #define NEED_REG_TABLE
3834 #include "i386-dis-evex.h"
3835 #undef NEED_REG_TABLE
3838 static const struct dis386 prefix_table
[][4] = {
3841 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3842 { "pause", { XX
}, 0 },
3843 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3844 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3847 /* PREFIX_MOD_0_0F01_REG_5 */
3850 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3853 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3856 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3859 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3862 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3867 { "wbinvd", { XX
}, 0 },
3868 { "wbnoinvd", { XX
}, 0 },
3873 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3874 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3875 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3876 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3881 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3882 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3883 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3884 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3889 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3890 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3891 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3892 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3897 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3898 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3899 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3904 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3905 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3906 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3907 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3912 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3913 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3914 { "bndmov", { EbndS
, Gbnd
}, 0 },
3915 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3920 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3921 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3922 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3923 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3928 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3929 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3930 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3931 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3936 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3937 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_OPCODE
},
3938 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3939 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3944 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3945 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3946 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3947 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3952 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3953 { "cvttss2si", { Gv
, EXd
}, PREFIX_OPCODE
},
3954 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3955 { "cvttsd2si", { Gv
, EXq
}, PREFIX_OPCODE
},
3960 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3961 { "cvtss2si", { Gv
, EXd
}, PREFIX_OPCODE
},
3962 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3963 { "cvtsd2si", { Gv
, EXq
}, PREFIX_OPCODE
},
3968 { "ucomiss",{ XM
, EXd
}, 0 },
3970 { "ucomisd",{ XM
, EXq
}, 0 },
3975 { "comiss", { XM
, EXd
}, 0 },
3977 { "comisd", { XM
, EXq
}, 0 },
3982 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3983 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3984 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3985 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3990 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3991 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3996 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3997 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
4002 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
4003 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
4004 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
4005 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
4010 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
4011 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
4012 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
4013 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
4018 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4019 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
4020 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
4021 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
4026 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
4027 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4028 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4033 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
4034 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
4035 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
4036 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
4041 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
4042 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
4043 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
4044 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
4049 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
4050 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
4051 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
4052 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
4057 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
4058 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
4059 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
4060 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
4065 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
4067 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
4072 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
4074 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
4079 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
4081 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
4088 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
4095 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
4100 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
4101 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
4102 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
4107 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
4108 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4109 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4110 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4113 /* PREFIX_0F73_REG_3 */
4117 { "psrldq", { XS
, Ib
}, 0 },
4120 /* PREFIX_0F73_REG_7 */
4124 { "pslldq", { XS
, Ib
}, 0 },
4129 {"vmread", { Em
, Gm
}, 0 },
4131 {"extrq", { XS
, Ib
, Ib
}, 0 },
4132 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
4137 {"vmwrite", { Gm
, Em
}, 0 },
4139 {"extrq", { XM
, XS
}, 0 },
4140 {"insertq", { XM
, XS
}, 0 },
4147 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
4148 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
4155 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
4156 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
4161 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
4162 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
4163 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
4168 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
4169 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
4170 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
4173 /* PREFIX_0FAE_REG_0 */
4176 { "rdfsbase", { Ev
}, 0 },
4179 /* PREFIX_0FAE_REG_1 */
4182 { "rdgsbase", { Ev
}, 0 },
4185 /* PREFIX_0FAE_REG_2 */
4188 { "wrfsbase", { Ev
}, 0 },
4191 /* PREFIX_0FAE_REG_3 */
4194 { "wrgsbase", { Ev
}, 0 },
4197 /* PREFIX_MOD_0_0FAE_REG_4 */
4199 { "xsave", { FXSAVE
}, 0 },
4200 { "ptwrite%LQ", { Edq
}, 0 },
4203 /* PREFIX_MOD_3_0FAE_REG_4 */
4206 { "ptwrite%LQ", { Edq
}, 0 },
4209 /* PREFIX_MOD_0_0FAE_REG_5 */
4211 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
4214 /* PREFIX_MOD_3_0FAE_REG_5 */
4216 { "lfence", { Skip_MODRM
}, 0 },
4217 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
4220 /* PREFIX_MOD_0_0FAE_REG_6 */
4222 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
4223 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
4224 { "clwb", { Mb
}, PREFIX_OPCODE
},
4227 /* PREFIX_MOD_1_0FAE_REG_6 */
4229 { RM_TABLE (RM_0FAE_REG_6
) },
4230 { "umonitor", { Eva
}, PREFIX_OPCODE
},
4231 { "tpause", { Edq
}, PREFIX_OPCODE
},
4232 { "umwait", { Edq
}, PREFIX_OPCODE
},
4235 /* PREFIX_0FAE_REG_7 */
4237 { "clflush", { Mb
}, 0 },
4239 { "clflushopt", { Mb
}, 0 },
4245 { "popcntS", { Gv
, Ev
}, 0 },
4250 { "bsfS", { Gv
, Ev
}, 0 },
4251 { "tzcntS", { Gv
, Ev
}, 0 },
4252 { "bsfS", { Gv
, Ev
}, 0 },
4257 { "bsrS", { Gv
, Ev
}, 0 },
4258 { "lzcntS", { Gv
, Ev
}, 0 },
4259 { "bsrS", { Gv
, Ev
}, 0 },
4264 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4265 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4266 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4267 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4270 /* PREFIX_MOD_0_0FC3 */
4272 { "movntiS", { Ev
, Gv
}, PREFIX_OPCODE
},
4275 /* PREFIX_MOD_0_0FC7_REG_6 */
4277 { "vmptrld",{ Mq
}, 0 },
4278 { "vmxon", { Mq
}, 0 },
4279 { "vmclear",{ Mq
}, 0 },
4282 /* PREFIX_MOD_3_0FC7_REG_6 */
4284 { "rdrand", { Ev
}, 0 },
4286 { "rdrand", { Ev
}, 0 }
4289 /* PREFIX_MOD_3_0FC7_REG_7 */
4291 { "rdseed", { Ev
}, 0 },
4292 { "rdpid", { Em
}, 0 },
4293 { "rdseed", { Ev
}, 0 },
4300 { "addsubpd", { XM
, EXx
}, 0 },
4301 { "addsubps", { XM
, EXx
}, 0 },
4307 { "movq2dq",{ XM
, MS
}, 0 },
4308 { "movq", { EXqS
, XM
}, 0 },
4309 { "movdq2q",{ MX
, XS
}, 0 },
4315 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4316 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4317 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4322 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4324 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4332 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4337 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4339 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4346 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4353 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4360 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4367 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4374 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4381 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4388 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4395 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4402 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4409 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4416 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4423 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4430 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4437 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4444 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4451 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4458 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4465 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4472 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4479 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4486 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4493 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4500 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4507 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4514 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4521 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4528 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4535 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4542 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4549 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4556 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4563 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4570 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4577 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4582 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4587 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4592 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4597 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4602 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4607 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4614 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4621 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4628 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4635 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4642 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4649 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4654 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4656 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4657 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4662 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4664 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4665 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4672 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4677 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4678 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4679 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4687 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4694 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4701 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4708 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4715 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4722 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4729 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4736 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4743 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4750 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4757 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4764 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4771 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4778 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4785 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4792 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4799 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4806 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4813 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4820 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4827 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4834 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4839 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4846 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4853 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4860 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4863 /* PREFIX_VEX_0F10 */
4865 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4866 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4867 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4868 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4871 /* PREFIX_VEX_0F11 */
4873 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4874 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4875 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4876 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4879 /* PREFIX_VEX_0F12 */
4881 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4882 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4883 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4884 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4887 /* PREFIX_VEX_0F16 */
4889 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4890 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4891 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4894 /* PREFIX_VEX_0F2A */
4897 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4899 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4902 /* PREFIX_VEX_0F2C */
4905 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4907 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4910 /* PREFIX_VEX_0F2D */
4913 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4915 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4918 /* PREFIX_VEX_0F2E */
4920 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4922 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4925 /* PREFIX_VEX_0F2F */
4927 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4929 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4932 /* PREFIX_VEX_0F41 */
4934 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4936 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4939 /* PREFIX_VEX_0F42 */
4941 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4943 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4946 /* PREFIX_VEX_0F44 */
4948 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4950 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4953 /* PREFIX_VEX_0F45 */
4955 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4957 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4960 /* PREFIX_VEX_0F46 */
4962 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4964 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4967 /* PREFIX_VEX_0F47 */
4969 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4971 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4974 /* PREFIX_VEX_0F4A */
4976 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4978 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4981 /* PREFIX_VEX_0F4B */
4983 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4985 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4988 /* PREFIX_VEX_0F51 */
4990 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4991 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4992 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4993 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4996 /* PREFIX_VEX_0F52 */
4998 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4999 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
5002 /* PREFIX_VEX_0F53 */
5004 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
5005 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
5008 /* PREFIX_VEX_0F58 */
5010 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
5011 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
5012 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
5013 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
5016 /* PREFIX_VEX_0F59 */
5018 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
5019 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
5020 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
5021 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
5024 /* PREFIX_VEX_0F5A */
5026 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
5027 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
5028 { "vcvtpd2ps%XY", { XMM
, EXx
}, 0 },
5029 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
5032 /* PREFIX_VEX_0F5B */
5034 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
5035 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
5036 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
5039 /* PREFIX_VEX_0F5C */
5041 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
5042 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
5043 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
5044 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
5047 /* PREFIX_VEX_0F5D */
5049 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
5050 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
5051 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
5052 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
5055 /* PREFIX_VEX_0F5E */
5057 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
5058 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
5059 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
5060 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
5063 /* PREFIX_VEX_0F5F */
5065 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
5066 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
5067 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
5068 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
5071 /* PREFIX_VEX_0F60 */
5075 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
5078 /* PREFIX_VEX_0F61 */
5082 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
5085 /* PREFIX_VEX_0F62 */
5089 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
5092 /* PREFIX_VEX_0F63 */
5096 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
5099 /* PREFIX_VEX_0F64 */
5103 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
5106 /* PREFIX_VEX_0F65 */
5110 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
5113 /* PREFIX_VEX_0F66 */
5117 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
5120 /* PREFIX_VEX_0F67 */
5124 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
5127 /* PREFIX_VEX_0F68 */
5131 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
5134 /* PREFIX_VEX_0F69 */
5138 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
5141 /* PREFIX_VEX_0F6A */
5145 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
5148 /* PREFIX_VEX_0F6B */
5152 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
5155 /* PREFIX_VEX_0F6C */
5159 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
5162 /* PREFIX_VEX_0F6D */
5166 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
5169 /* PREFIX_VEX_0F6E */
5173 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
5176 /* PREFIX_VEX_0F6F */
5179 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
5180 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
5183 /* PREFIX_VEX_0F70 */
5186 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
5187 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
5188 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
5191 /* PREFIX_VEX_0F71_REG_2 */
5195 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
5198 /* PREFIX_VEX_0F71_REG_4 */
5202 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
5205 /* PREFIX_VEX_0F71_REG_6 */
5209 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
5212 /* PREFIX_VEX_0F72_REG_2 */
5216 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
5219 /* PREFIX_VEX_0F72_REG_4 */
5223 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
5226 /* PREFIX_VEX_0F72_REG_6 */
5230 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
5233 /* PREFIX_VEX_0F73_REG_2 */
5237 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
5240 /* PREFIX_VEX_0F73_REG_3 */
5244 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
5247 /* PREFIX_VEX_0F73_REG_6 */
5251 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
5254 /* PREFIX_VEX_0F73_REG_7 */
5258 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
5261 /* PREFIX_VEX_0F74 */
5265 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
5268 /* PREFIX_VEX_0F75 */
5272 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
5275 /* PREFIX_VEX_0F76 */
5279 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
5282 /* PREFIX_VEX_0F77 */
5284 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
5287 /* PREFIX_VEX_0F7C */
5291 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
5292 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
5295 /* PREFIX_VEX_0F7D */
5299 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
5300 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
5303 /* PREFIX_VEX_0F7E */
5306 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5307 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5310 /* PREFIX_VEX_0F7F */
5313 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
5314 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
5317 /* PREFIX_VEX_0F90 */
5319 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5321 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5324 /* PREFIX_VEX_0F91 */
5326 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5328 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5331 /* PREFIX_VEX_0F92 */
5333 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5335 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5336 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5339 /* PREFIX_VEX_0F93 */
5341 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5343 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5344 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5347 /* PREFIX_VEX_0F98 */
5349 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5351 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5354 /* PREFIX_VEX_0F99 */
5356 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5358 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5361 /* PREFIX_VEX_0FC2 */
5363 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
5364 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
5365 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
5366 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
5369 /* PREFIX_VEX_0FC4 */
5373 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5376 /* PREFIX_VEX_0FC5 */
5380 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5383 /* PREFIX_VEX_0FD0 */
5387 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
5388 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
5391 /* PREFIX_VEX_0FD1 */
5395 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
5398 /* PREFIX_VEX_0FD2 */
5402 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
5405 /* PREFIX_VEX_0FD3 */
5409 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
5412 /* PREFIX_VEX_0FD4 */
5416 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
5419 /* PREFIX_VEX_0FD5 */
5423 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
5426 /* PREFIX_VEX_0FD6 */
5430 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5433 /* PREFIX_VEX_0FD7 */
5437 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5440 /* PREFIX_VEX_0FD8 */
5444 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
5447 /* PREFIX_VEX_0FD9 */
5451 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
5454 /* PREFIX_VEX_0FDA */
5458 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
5461 /* PREFIX_VEX_0FDB */
5465 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
5468 /* PREFIX_VEX_0FDC */
5472 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
5475 /* PREFIX_VEX_0FDD */
5479 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
5482 /* PREFIX_VEX_0FDE */
5486 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
5489 /* PREFIX_VEX_0FDF */
5493 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
5496 /* PREFIX_VEX_0FE0 */
5500 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
5503 /* PREFIX_VEX_0FE1 */
5507 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
5510 /* PREFIX_VEX_0FE2 */
5514 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
5517 /* PREFIX_VEX_0FE3 */
5521 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
5524 /* PREFIX_VEX_0FE4 */
5528 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
5531 /* PREFIX_VEX_0FE5 */
5535 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
5538 /* PREFIX_VEX_0FE6 */
5541 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
5542 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
5543 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5546 /* PREFIX_VEX_0FE7 */
5550 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5553 /* PREFIX_VEX_0FE8 */
5557 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5560 /* PREFIX_VEX_0FE9 */
5564 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5567 /* PREFIX_VEX_0FEA */
5571 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5574 /* PREFIX_VEX_0FEB */
5578 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5581 /* PREFIX_VEX_0FEC */
5585 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5588 /* PREFIX_VEX_0FED */
5592 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5595 /* PREFIX_VEX_0FEE */
5599 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5602 /* PREFIX_VEX_0FEF */
5606 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5609 /* PREFIX_VEX_0FF0 */
5614 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5617 /* PREFIX_VEX_0FF1 */
5621 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5624 /* PREFIX_VEX_0FF2 */
5628 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5631 /* PREFIX_VEX_0FF3 */
5635 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5638 /* PREFIX_VEX_0FF4 */
5642 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5645 /* PREFIX_VEX_0FF5 */
5649 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5652 /* PREFIX_VEX_0FF6 */
5656 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5659 /* PREFIX_VEX_0FF7 */
5663 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5666 /* PREFIX_VEX_0FF8 */
5670 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5673 /* PREFIX_VEX_0FF9 */
5677 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5680 /* PREFIX_VEX_0FFA */
5684 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5687 /* PREFIX_VEX_0FFB */
5691 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5694 /* PREFIX_VEX_0FFC */
5698 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5701 /* PREFIX_VEX_0FFD */
5705 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5708 /* PREFIX_VEX_0FFE */
5712 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5715 /* PREFIX_VEX_0F3800 */
5719 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5722 /* PREFIX_VEX_0F3801 */
5726 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5729 /* PREFIX_VEX_0F3802 */
5733 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5736 /* PREFIX_VEX_0F3803 */
5740 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5743 /* PREFIX_VEX_0F3804 */
5747 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5750 /* PREFIX_VEX_0F3805 */
5754 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5757 /* PREFIX_VEX_0F3806 */
5761 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5764 /* PREFIX_VEX_0F3807 */
5768 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5771 /* PREFIX_VEX_0F3808 */
5775 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5778 /* PREFIX_VEX_0F3809 */
5782 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5785 /* PREFIX_VEX_0F380A */
5789 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5792 /* PREFIX_VEX_0F380B */
5796 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5799 /* PREFIX_VEX_0F380C */
5803 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5806 /* PREFIX_VEX_0F380D */
5810 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5813 /* PREFIX_VEX_0F380E */
5817 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5820 /* PREFIX_VEX_0F380F */
5824 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5827 /* PREFIX_VEX_0F3813 */
5831 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5834 /* PREFIX_VEX_0F3816 */
5838 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5841 /* PREFIX_VEX_0F3817 */
5845 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5848 /* PREFIX_VEX_0F3818 */
5852 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5855 /* PREFIX_VEX_0F3819 */
5859 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5862 /* PREFIX_VEX_0F381A */
5866 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5869 /* PREFIX_VEX_0F381C */
5873 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5876 /* PREFIX_VEX_0F381D */
5880 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5883 /* PREFIX_VEX_0F381E */
5887 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5890 /* PREFIX_VEX_0F3820 */
5894 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5897 /* PREFIX_VEX_0F3821 */
5901 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5904 /* PREFIX_VEX_0F3822 */
5908 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5911 /* PREFIX_VEX_0F3823 */
5915 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5918 /* PREFIX_VEX_0F3824 */
5922 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5925 /* PREFIX_VEX_0F3825 */
5929 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5932 /* PREFIX_VEX_0F3828 */
5936 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5939 /* PREFIX_VEX_0F3829 */
5943 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5946 /* PREFIX_VEX_0F382A */
5950 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5953 /* PREFIX_VEX_0F382B */
5957 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5960 /* PREFIX_VEX_0F382C */
5964 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5967 /* PREFIX_VEX_0F382D */
5971 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5974 /* PREFIX_VEX_0F382E */
5978 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5981 /* PREFIX_VEX_0F382F */
5985 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5988 /* PREFIX_VEX_0F3830 */
5992 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5995 /* PREFIX_VEX_0F3831 */
5999 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
6002 /* PREFIX_VEX_0F3832 */
6006 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
6009 /* PREFIX_VEX_0F3833 */
6013 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
6016 /* PREFIX_VEX_0F3834 */
6020 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
6023 /* PREFIX_VEX_0F3835 */
6027 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
6030 /* PREFIX_VEX_0F3836 */
6034 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
6037 /* PREFIX_VEX_0F3837 */
6041 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
6044 /* PREFIX_VEX_0F3838 */
6048 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
6051 /* PREFIX_VEX_0F3839 */
6055 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
6058 /* PREFIX_VEX_0F383A */
6062 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
6065 /* PREFIX_VEX_0F383B */
6069 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
6072 /* PREFIX_VEX_0F383C */
6076 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
6079 /* PREFIX_VEX_0F383D */
6083 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
6086 /* PREFIX_VEX_0F383E */
6090 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
6093 /* PREFIX_VEX_0F383F */
6097 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
6100 /* PREFIX_VEX_0F3840 */
6104 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
6107 /* PREFIX_VEX_0F3841 */
6111 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
6114 /* PREFIX_VEX_0F3845 */
6118 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
6121 /* PREFIX_VEX_0F3846 */
6125 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
6128 /* PREFIX_VEX_0F3847 */
6132 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
6135 /* PREFIX_VEX_0F3858 */
6139 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
6142 /* PREFIX_VEX_0F3859 */
6146 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
6149 /* PREFIX_VEX_0F385A */
6153 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
6156 /* PREFIX_VEX_0F3878 */
6160 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
6163 /* PREFIX_VEX_0F3879 */
6167 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
6170 /* PREFIX_VEX_0F388C */
6174 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
6177 /* PREFIX_VEX_0F388E */
6181 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
6184 /* PREFIX_VEX_0F3890 */
6188 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6191 /* PREFIX_VEX_0F3891 */
6195 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6198 /* PREFIX_VEX_0F3892 */
6202 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6205 /* PREFIX_VEX_0F3893 */
6209 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6212 /* PREFIX_VEX_0F3896 */
6216 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6219 /* PREFIX_VEX_0F3897 */
6223 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6226 /* PREFIX_VEX_0F3898 */
6230 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6233 /* PREFIX_VEX_0F3899 */
6237 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6240 /* PREFIX_VEX_0F389A */
6244 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6247 /* PREFIX_VEX_0F389B */
6251 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6254 /* PREFIX_VEX_0F389C */
6258 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6261 /* PREFIX_VEX_0F389D */
6265 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6268 /* PREFIX_VEX_0F389E */
6272 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6275 /* PREFIX_VEX_0F389F */
6279 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6282 /* PREFIX_VEX_0F38A6 */
6286 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6290 /* PREFIX_VEX_0F38A7 */
6294 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6297 /* PREFIX_VEX_0F38A8 */
6301 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6304 /* PREFIX_VEX_0F38A9 */
6308 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6311 /* PREFIX_VEX_0F38AA */
6315 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6318 /* PREFIX_VEX_0F38AB */
6322 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6325 /* PREFIX_VEX_0F38AC */
6329 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6332 /* PREFIX_VEX_0F38AD */
6336 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6339 /* PREFIX_VEX_0F38AE */
6343 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6346 /* PREFIX_VEX_0F38AF */
6350 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6353 /* PREFIX_VEX_0F38B6 */
6357 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6360 /* PREFIX_VEX_0F38B7 */
6364 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6367 /* PREFIX_VEX_0F38B8 */
6371 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6374 /* PREFIX_VEX_0F38B9 */
6378 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6381 /* PREFIX_VEX_0F38BA */
6385 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6388 /* PREFIX_VEX_0F38BB */
6392 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6395 /* PREFIX_VEX_0F38BC */
6399 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6402 /* PREFIX_VEX_0F38BD */
6406 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6409 /* PREFIX_VEX_0F38BE */
6413 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6416 /* PREFIX_VEX_0F38BF */
6420 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6423 /* PREFIX_VEX_0F38CF */
6427 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6430 /* PREFIX_VEX_0F38DB */
6434 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6437 /* PREFIX_VEX_0F38DC */
6441 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6444 /* PREFIX_VEX_0F38DD */
6448 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6451 /* PREFIX_VEX_0F38DE */
6455 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6458 /* PREFIX_VEX_0F38DF */
6462 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6465 /* PREFIX_VEX_0F38F2 */
6467 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6470 /* PREFIX_VEX_0F38F3_REG_1 */
6472 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6475 /* PREFIX_VEX_0F38F3_REG_2 */
6477 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6480 /* PREFIX_VEX_0F38F3_REG_3 */
6482 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6485 /* PREFIX_VEX_0F38F5 */
6487 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6488 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6490 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6493 /* PREFIX_VEX_0F38F6 */
6498 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6501 /* PREFIX_VEX_0F38F7 */
6503 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6504 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6505 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6506 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6509 /* PREFIX_VEX_0F3A00 */
6513 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6516 /* PREFIX_VEX_0F3A01 */
6520 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6523 /* PREFIX_VEX_0F3A02 */
6527 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6530 /* PREFIX_VEX_0F3A04 */
6534 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6537 /* PREFIX_VEX_0F3A05 */
6541 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6544 /* PREFIX_VEX_0F3A06 */
6548 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6551 /* PREFIX_VEX_0F3A08 */
6555 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6558 /* PREFIX_VEX_0F3A09 */
6562 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6565 /* PREFIX_VEX_0F3A0A */
6569 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6572 /* PREFIX_VEX_0F3A0B */
6576 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6579 /* PREFIX_VEX_0F3A0C */
6583 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6586 /* PREFIX_VEX_0F3A0D */
6590 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6593 /* PREFIX_VEX_0F3A0E */
6597 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6600 /* PREFIX_VEX_0F3A0F */
6604 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6607 /* PREFIX_VEX_0F3A14 */
6611 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6614 /* PREFIX_VEX_0F3A15 */
6618 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6621 /* PREFIX_VEX_0F3A16 */
6625 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6628 /* PREFIX_VEX_0F3A17 */
6632 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6635 /* PREFIX_VEX_0F3A18 */
6639 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6642 /* PREFIX_VEX_0F3A19 */
6646 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6649 /* PREFIX_VEX_0F3A1D */
6653 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6656 /* PREFIX_VEX_0F3A20 */
6660 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6663 /* PREFIX_VEX_0F3A21 */
6667 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6670 /* PREFIX_VEX_0F3A22 */
6674 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6677 /* PREFIX_VEX_0F3A30 */
6681 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6684 /* PREFIX_VEX_0F3A31 */
6688 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6691 /* PREFIX_VEX_0F3A32 */
6695 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6698 /* PREFIX_VEX_0F3A33 */
6702 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6705 /* PREFIX_VEX_0F3A38 */
6709 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6712 /* PREFIX_VEX_0F3A39 */
6716 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6719 /* PREFIX_VEX_0F3A40 */
6723 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6726 /* PREFIX_VEX_0F3A41 */
6730 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6733 /* PREFIX_VEX_0F3A42 */
6737 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6740 /* PREFIX_VEX_0F3A44 */
6744 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6747 /* PREFIX_VEX_0F3A46 */
6751 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6754 /* PREFIX_VEX_0F3A48 */
6758 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6761 /* PREFIX_VEX_0F3A49 */
6765 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6768 /* PREFIX_VEX_0F3A4A */
6772 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6775 /* PREFIX_VEX_0F3A4B */
6779 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6782 /* PREFIX_VEX_0F3A4C */
6786 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6789 /* PREFIX_VEX_0F3A5C */
6793 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6796 /* PREFIX_VEX_0F3A5D */
6800 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6803 /* PREFIX_VEX_0F3A5E */
6807 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6810 /* PREFIX_VEX_0F3A5F */
6814 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6817 /* PREFIX_VEX_0F3A60 */
6821 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6825 /* PREFIX_VEX_0F3A61 */
6829 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6832 /* PREFIX_VEX_0F3A62 */
6836 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6839 /* PREFIX_VEX_0F3A63 */
6843 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6846 /* PREFIX_VEX_0F3A68 */
6850 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6853 /* PREFIX_VEX_0F3A69 */
6857 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6860 /* PREFIX_VEX_0F3A6A */
6864 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6867 /* PREFIX_VEX_0F3A6B */
6871 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6874 /* PREFIX_VEX_0F3A6C */
6878 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6881 /* PREFIX_VEX_0F3A6D */
6885 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6888 /* PREFIX_VEX_0F3A6E */
6892 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6895 /* PREFIX_VEX_0F3A6F */
6899 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6902 /* PREFIX_VEX_0F3A78 */
6906 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6909 /* PREFIX_VEX_0F3A79 */
6913 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6916 /* PREFIX_VEX_0F3A7A */
6920 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6923 /* PREFIX_VEX_0F3A7B */
6927 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6930 /* PREFIX_VEX_0F3A7C */
6934 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6938 /* PREFIX_VEX_0F3A7D */
6942 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6945 /* PREFIX_VEX_0F3A7E */
6949 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6952 /* PREFIX_VEX_0F3A7F */
6956 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6959 /* PREFIX_VEX_0F3ACE */
6963 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6966 /* PREFIX_VEX_0F3ACF */
6970 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6973 /* PREFIX_VEX_0F3ADF */
6977 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6980 /* PREFIX_VEX_0F3AF0 */
6985 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6988 #define NEED_PREFIX_TABLE
6989 #include "i386-dis-evex.h"
6990 #undef NEED_PREFIX_TABLE
6993 static const struct dis386 x86_64_table
[][2] = {
6996 { "pushP", { es
}, 0 },
7001 { "popP", { es
}, 0 },
7006 { "pushP", { cs
}, 0 },
7011 { "pushP", { ss
}, 0 },
7016 { "popP", { ss
}, 0 },
7021 { "pushP", { ds
}, 0 },
7026 { "popP", { ds
}, 0 },
7031 { "daa", { XX
}, 0 },
7036 { "das", { XX
}, 0 },
7041 { "aaa", { XX
}, 0 },
7046 { "aas", { XX
}, 0 },
7051 { "pushaP", { XX
}, 0 },
7056 { "popaP", { XX
}, 0 },
7061 { MOD_TABLE (MOD_62_32BIT
) },
7062 { EVEX_TABLE (EVEX_0F
) },
7067 { "arpl", { Ew
, Gw
}, 0 },
7068 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
7073 { "ins{R|}", { Yzr
, indirDX
}, 0 },
7074 { "ins{G|}", { Yzr
, indirDX
}, 0 },
7079 { "outs{R|}", { indirDXr
, Xz
}, 0 },
7080 { "outs{G|}", { indirDXr
, Xz
}, 0 },
7085 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
7086 { REG_TABLE (REG_80
) },
7091 { "Jcall{T|}", { Ap
}, 0 },
7096 { MOD_TABLE (MOD_C4_32BIT
) },
7097 { VEX_C4_TABLE (VEX_0F
) },
7102 { MOD_TABLE (MOD_C5_32BIT
) },
7103 { VEX_C5_TABLE (VEX_0F
) },
7108 { "into", { XX
}, 0 },
7113 { "aam", { Ib
}, 0 },
7118 { "aad", { Ib
}, 0 },
7123 { "callP", { Jv
, BND
}, 0 },
7124 { "call@", { Jv
, BND
}, 0 }
7129 { "jmpP", { Jv
, BND
}, 0 },
7130 { "jmp@", { Jv
, BND
}, 0 }
7135 { "Jjmp{T|}", { Ap
}, 0 },
7138 /* X86_64_0F01_REG_0 */
7140 { "sgdt{Q|IQ}", { M
}, 0 },
7141 { "sgdt", { M
}, 0 },
7144 /* X86_64_0F01_REG_1 */
7146 { "sidt{Q|IQ}", { M
}, 0 },
7147 { "sidt", { M
}, 0 },
7150 /* X86_64_0F01_REG_2 */
7152 { "lgdt{Q|Q}", { M
}, 0 },
7153 { "lgdt", { M
}, 0 },
7156 /* X86_64_0F01_REG_3 */
7158 { "lidt{Q|Q}", { M
}, 0 },
7159 { "lidt", { M
}, 0 },
7163 static const struct dis386 three_byte_table
[][256] = {
7165 /* THREE_BYTE_0F38 */
7168 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
7169 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
7170 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
7171 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
7172 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
7173 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
7174 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
7175 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
7177 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
7178 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
7179 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
7180 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
7186 { PREFIX_TABLE (PREFIX_0F3810
) },
7190 { PREFIX_TABLE (PREFIX_0F3814
) },
7191 { PREFIX_TABLE (PREFIX_0F3815
) },
7193 { PREFIX_TABLE (PREFIX_0F3817
) },
7199 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7200 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7201 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7204 { PREFIX_TABLE (PREFIX_0F3820
) },
7205 { PREFIX_TABLE (PREFIX_0F3821
) },
7206 { PREFIX_TABLE (PREFIX_0F3822
) },
7207 { PREFIX_TABLE (PREFIX_0F3823
) },
7208 { PREFIX_TABLE (PREFIX_0F3824
) },
7209 { PREFIX_TABLE (PREFIX_0F3825
) },
7213 { PREFIX_TABLE (PREFIX_0F3828
) },
7214 { PREFIX_TABLE (PREFIX_0F3829
) },
7215 { PREFIX_TABLE (PREFIX_0F382A
) },
7216 { PREFIX_TABLE (PREFIX_0F382B
) },
7222 { PREFIX_TABLE (PREFIX_0F3830
) },
7223 { PREFIX_TABLE (PREFIX_0F3831
) },
7224 { PREFIX_TABLE (PREFIX_0F3832
) },
7225 { PREFIX_TABLE (PREFIX_0F3833
) },
7226 { PREFIX_TABLE (PREFIX_0F3834
) },
7227 { PREFIX_TABLE (PREFIX_0F3835
) },
7229 { PREFIX_TABLE (PREFIX_0F3837
) },
7231 { PREFIX_TABLE (PREFIX_0F3838
) },
7232 { PREFIX_TABLE (PREFIX_0F3839
) },
7233 { PREFIX_TABLE (PREFIX_0F383A
) },
7234 { PREFIX_TABLE (PREFIX_0F383B
) },
7235 { PREFIX_TABLE (PREFIX_0F383C
) },
7236 { PREFIX_TABLE (PREFIX_0F383D
) },
7237 { PREFIX_TABLE (PREFIX_0F383E
) },
7238 { PREFIX_TABLE (PREFIX_0F383F
) },
7240 { PREFIX_TABLE (PREFIX_0F3840
) },
7241 { PREFIX_TABLE (PREFIX_0F3841
) },
7312 { PREFIX_TABLE (PREFIX_0F3880
) },
7313 { PREFIX_TABLE (PREFIX_0F3881
) },
7314 { PREFIX_TABLE (PREFIX_0F3882
) },
7393 { PREFIX_TABLE (PREFIX_0F38C8
) },
7394 { PREFIX_TABLE (PREFIX_0F38C9
) },
7395 { PREFIX_TABLE (PREFIX_0F38CA
) },
7396 { PREFIX_TABLE (PREFIX_0F38CB
) },
7397 { PREFIX_TABLE (PREFIX_0F38CC
) },
7398 { PREFIX_TABLE (PREFIX_0F38CD
) },
7400 { PREFIX_TABLE (PREFIX_0F38CF
) },
7414 { PREFIX_TABLE (PREFIX_0F38DB
) },
7415 { PREFIX_TABLE (PREFIX_0F38DC
) },
7416 { PREFIX_TABLE (PREFIX_0F38DD
) },
7417 { PREFIX_TABLE (PREFIX_0F38DE
) },
7418 { PREFIX_TABLE (PREFIX_0F38DF
) },
7438 { PREFIX_TABLE (PREFIX_0F38F0
) },
7439 { PREFIX_TABLE (PREFIX_0F38F1
) },
7443 { PREFIX_TABLE (PREFIX_0F38F5
) },
7444 { PREFIX_TABLE (PREFIX_0F38F6
) },
7456 /* THREE_BYTE_0F3A */
7468 { PREFIX_TABLE (PREFIX_0F3A08
) },
7469 { PREFIX_TABLE (PREFIX_0F3A09
) },
7470 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7471 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7472 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7473 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7474 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7475 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7481 { PREFIX_TABLE (PREFIX_0F3A14
) },
7482 { PREFIX_TABLE (PREFIX_0F3A15
) },
7483 { PREFIX_TABLE (PREFIX_0F3A16
) },
7484 { PREFIX_TABLE (PREFIX_0F3A17
) },
7495 { PREFIX_TABLE (PREFIX_0F3A20
) },
7496 { PREFIX_TABLE (PREFIX_0F3A21
) },
7497 { PREFIX_TABLE (PREFIX_0F3A22
) },
7531 { PREFIX_TABLE (PREFIX_0F3A40
) },
7532 { PREFIX_TABLE (PREFIX_0F3A41
) },
7533 { PREFIX_TABLE (PREFIX_0F3A42
) },
7535 { PREFIX_TABLE (PREFIX_0F3A44
) },
7567 { PREFIX_TABLE (PREFIX_0F3A60
) },
7568 { PREFIX_TABLE (PREFIX_0F3A61
) },
7569 { PREFIX_TABLE (PREFIX_0F3A62
) },
7570 { PREFIX_TABLE (PREFIX_0F3A63
) },
7688 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7690 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7691 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7709 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7749 static const struct dis386 xop_table
[][256] = {
7902 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7903 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7904 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7912 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7913 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7920 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7921 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7922 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7930 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7931 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7935 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7936 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7939 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7957 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7969 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7970 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7971 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7972 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7982 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7983 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7984 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7985 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
8018 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
8019 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
8020 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
8021 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
8045 { REG_TABLE (REG_XOP_TBM_01
) },
8046 { REG_TABLE (REG_XOP_TBM_02
) },
8064 { REG_TABLE (REG_XOP_LWPCB
) },
8188 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8189 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8190 { "vfrczss", { XM
, EXd
}, 0 },
8191 { "vfrczsd", { XM
, EXq
}, 0 },
8206 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8207 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8208 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8209 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8210 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8211 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8212 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8213 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8215 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8216 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8217 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8218 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8261 { "vphaddbw", { XM
, EXxmm
}, 0 },
8262 { "vphaddbd", { XM
, EXxmm
}, 0 },
8263 { "vphaddbq", { XM
, EXxmm
}, 0 },
8266 { "vphaddwd", { XM
, EXxmm
}, 0 },
8267 { "vphaddwq", { XM
, EXxmm
}, 0 },
8272 { "vphadddq", { XM
, EXxmm
}, 0 },
8279 { "vphaddubw", { XM
, EXxmm
}, 0 },
8280 { "vphaddubd", { XM
, EXxmm
}, 0 },
8281 { "vphaddubq", { XM
, EXxmm
}, 0 },
8284 { "vphadduwd", { XM
, EXxmm
}, 0 },
8285 { "vphadduwq", { XM
, EXxmm
}, 0 },
8290 { "vphaddudq", { XM
, EXxmm
}, 0 },
8297 { "vphsubbw", { XM
, EXxmm
}, 0 },
8298 { "vphsubwd", { XM
, EXxmm
}, 0 },
8299 { "vphsubdq", { XM
, EXxmm
}, 0 },
8353 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8355 { REG_TABLE (REG_XOP_LWP
) },
8625 static const struct dis386 vex_table
[][256] = {
8647 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8648 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8649 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8650 { MOD_TABLE (MOD_VEX_0F13
) },
8651 { VEX_W_TABLE (VEX_W_0F14
) },
8652 { VEX_W_TABLE (VEX_W_0F15
) },
8653 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8654 { MOD_TABLE (MOD_VEX_0F17
) },
8674 { VEX_W_TABLE (VEX_W_0F28
) },
8675 { VEX_W_TABLE (VEX_W_0F29
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8677 { MOD_TABLE (MOD_VEX_0F2B
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8719 { MOD_TABLE (MOD_VEX_0F50
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8723 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8724 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8725 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8726 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8728 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8743 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8756 { REG_TABLE (REG_VEX_0F71
) },
8757 { REG_TABLE (REG_VEX_0F72
) },
8758 { REG_TABLE (REG_VEX_0F73
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8824 { REG_TABLE (REG_VEX_0FAE
) },
8847 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8849 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8850 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8851 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8863 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8864 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8865 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8866 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8867 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8870 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8872 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8873 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8874 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8875 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8876 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8877 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8878 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8879 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8881 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8882 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8884 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8895 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8896 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8927 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8979 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8980 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8981 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8983 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8984 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8985 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8988 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8989 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8990 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8992 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
9020 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
9082 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
9083 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
9107 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
9112 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
9113 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
9114 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
9115 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
9116 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
9127 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
9128 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
9129 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
9130 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
9131 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
9152 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
9166 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9167 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9168 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9169 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9170 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9193 { REG_TABLE (REG_VEX_0F38F3
) },
9195 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9196 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9197 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9211 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9212 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9213 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9215 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9216 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9217 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9220 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9221 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9222 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9223 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9224 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9225 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9226 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9227 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9233 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9234 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9235 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9236 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9238 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9239 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9243 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9247 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9248 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9249 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9265 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9266 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9267 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9268 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9274 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9275 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9283 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9284 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9285 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9287 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9289 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9292 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9293 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9294 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9295 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9296 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9314 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9315 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9316 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9317 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9319 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9320 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9321 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9322 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9328 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9329 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9330 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9331 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9332 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9333 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9334 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9335 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9346 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9347 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9348 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9349 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9350 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9351 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9352 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9353 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9442 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9443 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9461 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9481 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9501 #define NEED_OPCODE_TABLE
9502 #include "i386-dis-evex.h"
9503 #undef NEED_OPCODE_TABLE
9504 static const struct dis386 vex_len_table
[][2] = {
9505 /* VEX_LEN_0F10_P_1 */
9507 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9508 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9511 /* VEX_LEN_0F10_P_3 */
9513 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9514 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9517 /* VEX_LEN_0F11_P_1 */
9519 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9520 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9523 /* VEX_LEN_0F11_P_3 */
9525 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9526 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9529 /* VEX_LEN_0F12_P_0_M_0 */
9531 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9534 /* VEX_LEN_0F12_P_0_M_1 */
9536 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9539 /* VEX_LEN_0F12_P_2 */
9541 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9544 /* VEX_LEN_0F13_M_0 */
9546 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9549 /* VEX_LEN_0F16_P_0_M_0 */
9551 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9554 /* VEX_LEN_0F16_P_0_M_1 */
9556 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9559 /* VEX_LEN_0F16_P_2 */
9561 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9564 /* VEX_LEN_0F17_M_0 */
9566 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9569 /* VEX_LEN_0F2A_P_1 */
9571 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9572 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9575 /* VEX_LEN_0F2A_P_3 */
9577 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9578 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9581 /* VEX_LEN_0F2C_P_1 */
9583 { "vcvttss2si", { Gv
, EXdScalar
}, 0 },
9584 { "vcvttss2si", { Gv
, EXdScalar
}, 0 },
9587 /* VEX_LEN_0F2C_P_3 */
9589 { "vcvttsd2si", { Gv
, EXqScalar
}, 0 },
9590 { "vcvttsd2si", { Gv
, EXqScalar
}, 0 },
9593 /* VEX_LEN_0F2D_P_1 */
9595 { "vcvtss2si", { Gv
, EXdScalar
}, 0 },
9596 { "vcvtss2si", { Gv
, EXdScalar
}, 0 },
9599 /* VEX_LEN_0F2D_P_3 */
9601 { "vcvtsd2si", { Gv
, EXqScalar
}, 0 },
9602 { "vcvtsd2si", { Gv
, EXqScalar
}, 0 },
9605 /* VEX_LEN_0F2E_P_0 */
9607 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9608 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9611 /* VEX_LEN_0F2E_P_2 */
9613 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9614 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9617 /* VEX_LEN_0F2F_P_0 */
9619 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9620 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9623 /* VEX_LEN_0F2F_P_2 */
9625 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9626 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9629 /* VEX_LEN_0F41_P_0 */
9632 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9634 /* VEX_LEN_0F41_P_2 */
9637 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9639 /* VEX_LEN_0F42_P_0 */
9642 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9644 /* VEX_LEN_0F42_P_2 */
9647 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9649 /* VEX_LEN_0F44_P_0 */
9651 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9653 /* VEX_LEN_0F44_P_2 */
9655 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9657 /* VEX_LEN_0F45_P_0 */
9660 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9662 /* VEX_LEN_0F45_P_2 */
9665 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9667 /* VEX_LEN_0F46_P_0 */
9670 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9672 /* VEX_LEN_0F46_P_2 */
9675 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9677 /* VEX_LEN_0F47_P_0 */
9680 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9682 /* VEX_LEN_0F47_P_2 */
9685 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9687 /* VEX_LEN_0F4A_P_0 */
9690 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9692 /* VEX_LEN_0F4A_P_2 */
9695 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9697 /* VEX_LEN_0F4B_P_0 */
9700 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9702 /* VEX_LEN_0F4B_P_2 */
9705 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9708 /* VEX_LEN_0F51_P_1 */
9710 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9711 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9714 /* VEX_LEN_0F51_P_3 */
9716 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9717 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9720 /* VEX_LEN_0F52_P_1 */
9722 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9723 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9726 /* VEX_LEN_0F53_P_1 */
9728 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9729 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9732 /* VEX_LEN_0F58_P_1 */
9734 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9735 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9738 /* VEX_LEN_0F58_P_3 */
9740 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9741 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9744 /* VEX_LEN_0F59_P_1 */
9746 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9747 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9750 /* VEX_LEN_0F59_P_3 */
9752 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9753 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9756 /* VEX_LEN_0F5A_P_1 */
9758 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9759 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9762 /* VEX_LEN_0F5A_P_3 */
9764 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9765 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9768 /* VEX_LEN_0F5C_P_1 */
9770 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9771 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9774 /* VEX_LEN_0F5C_P_3 */
9776 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9777 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9780 /* VEX_LEN_0F5D_P_1 */
9782 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9783 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9786 /* VEX_LEN_0F5D_P_3 */
9788 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9789 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9792 /* VEX_LEN_0F5E_P_1 */
9794 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9795 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9798 /* VEX_LEN_0F5E_P_3 */
9800 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9801 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9804 /* VEX_LEN_0F5F_P_1 */
9806 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9807 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9810 /* VEX_LEN_0F5F_P_3 */
9812 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9813 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9816 /* VEX_LEN_0F6E_P_2 */
9818 { "vmovK", { XMScalar
, Edq
}, 0 },
9819 { "vmovK", { XMScalar
, Edq
}, 0 },
9822 /* VEX_LEN_0F7E_P_1 */
9824 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9825 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9828 /* VEX_LEN_0F7E_P_2 */
9830 { "vmovK", { Edq
, XMScalar
}, 0 },
9831 { "vmovK", { Edq
, XMScalar
}, 0 },
9834 /* VEX_LEN_0F90_P_0 */
9836 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9839 /* VEX_LEN_0F90_P_2 */
9841 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9844 /* VEX_LEN_0F91_P_0 */
9846 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9849 /* VEX_LEN_0F91_P_2 */
9851 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9854 /* VEX_LEN_0F92_P_0 */
9856 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9859 /* VEX_LEN_0F92_P_2 */
9861 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9864 /* VEX_LEN_0F92_P_3 */
9866 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9869 /* VEX_LEN_0F93_P_0 */
9871 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9874 /* VEX_LEN_0F93_P_2 */
9876 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9879 /* VEX_LEN_0F93_P_3 */
9881 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9884 /* VEX_LEN_0F98_P_0 */
9886 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9889 /* VEX_LEN_0F98_P_2 */
9891 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9894 /* VEX_LEN_0F99_P_0 */
9896 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9899 /* VEX_LEN_0F99_P_2 */
9901 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9904 /* VEX_LEN_0FAE_R_2_M_0 */
9906 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
9909 /* VEX_LEN_0FAE_R_3_M_0 */
9911 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
9914 /* VEX_LEN_0FC2_P_1 */
9916 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9917 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9920 /* VEX_LEN_0FC2_P_3 */
9922 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9923 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9926 /* VEX_LEN_0FC4_P_2 */
9928 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
9931 /* VEX_LEN_0FC5_P_2 */
9933 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
9936 /* VEX_LEN_0FD6_P_2 */
9938 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9939 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9942 /* VEX_LEN_0FF7_P_2 */
9944 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
9947 /* VEX_LEN_0F3816_P_2 */
9950 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9953 /* VEX_LEN_0F3819_P_2 */
9956 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9959 /* VEX_LEN_0F381A_P_2_M_0 */
9962 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9965 /* VEX_LEN_0F3836_P_2 */
9968 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9971 /* VEX_LEN_0F3841_P_2 */
9973 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
9976 /* VEX_LEN_0F385A_P_2_M_0 */
9979 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9982 /* VEX_LEN_0F38DB_P_2 */
9984 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
9987 /* VEX_LEN_0F38F2_P_0 */
9989 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9992 /* VEX_LEN_0F38F3_R_1_P_0 */
9994 { "blsrS", { VexGdq
, Edq
}, 0 },
9997 /* VEX_LEN_0F38F3_R_2_P_0 */
9999 { "blsmskS", { VexGdq
, Edq
}, 0 },
10002 /* VEX_LEN_0F38F3_R_3_P_0 */
10004 { "blsiS", { VexGdq
, Edq
}, 0 },
10007 /* VEX_LEN_0F38F5_P_0 */
10009 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
10012 /* VEX_LEN_0F38F5_P_1 */
10014 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
10017 /* VEX_LEN_0F38F5_P_3 */
10019 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
10022 /* VEX_LEN_0F38F6_P_3 */
10024 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
10027 /* VEX_LEN_0F38F7_P_0 */
10029 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
10032 /* VEX_LEN_0F38F7_P_1 */
10034 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
10037 /* VEX_LEN_0F38F7_P_2 */
10039 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
10042 /* VEX_LEN_0F38F7_P_3 */
10044 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
10047 /* VEX_LEN_0F3A00_P_2 */
10050 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
10053 /* VEX_LEN_0F3A01_P_2 */
10056 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
10059 /* VEX_LEN_0F3A06_P_2 */
10062 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
10065 /* VEX_LEN_0F3A0A_P_2 */
10067 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10068 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10071 /* VEX_LEN_0F3A0B_P_2 */
10073 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10074 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10077 /* VEX_LEN_0F3A14_P_2 */
10079 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
10082 /* VEX_LEN_0F3A15_P_2 */
10084 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
10087 /* VEX_LEN_0F3A16_P_2 */
10089 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
10092 /* VEX_LEN_0F3A17_P_2 */
10094 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
10097 /* VEX_LEN_0F3A18_P_2 */
10100 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
10103 /* VEX_LEN_0F3A19_P_2 */
10106 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
10109 /* VEX_LEN_0F3A20_P_2 */
10111 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
10114 /* VEX_LEN_0F3A21_P_2 */
10116 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
10119 /* VEX_LEN_0F3A22_P_2 */
10121 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
10124 /* VEX_LEN_0F3A30_P_2 */
10126 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
10129 /* VEX_LEN_0F3A31_P_2 */
10131 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
10134 /* VEX_LEN_0F3A32_P_2 */
10136 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
10139 /* VEX_LEN_0F3A33_P_2 */
10141 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
10144 /* VEX_LEN_0F3A38_P_2 */
10147 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
10150 /* VEX_LEN_0F3A39_P_2 */
10153 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
10156 /* VEX_LEN_0F3A41_P_2 */
10158 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
10161 /* VEX_LEN_0F3A46_P_2 */
10164 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
10167 /* VEX_LEN_0F3A60_P_2 */
10169 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
10172 /* VEX_LEN_0F3A61_P_2 */
10174 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
10177 /* VEX_LEN_0F3A62_P_2 */
10179 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
10182 /* VEX_LEN_0F3A63_P_2 */
10184 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
10187 /* VEX_LEN_0F3A6A_P_2 */
10189 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
10192 /* VEX_LEN_0F3A6B_P_2 */
10194 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
10197 /* VEX_LEN_0F3A6E_P_2 */
10199 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
10202 /* VEX_LEN_0F3A6F_P_2 */
10204 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
10207 /* VEX_LEN_0F3A7A_P_2 */
10209 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
10212 /* VEX_LEN_0F3A7B_P_2 */
10214 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
10217 /* VEX_LEN_0F3A7E_P_2 */
10219 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
10222 /* VEX_LEN_0F3A7F_P_2 */
10224 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
10227 /* VEX_LEN_0F3ADF_P_2 */
10229 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
10232 /* VEX_LEN_0F3AF0_P_3 */
10234 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
10237 /* VEX_LEN_0FXOP_08_CC */
10239 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10242 /* VEX_LEN_0FXOP_08_CD */
10244 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10247 /* VEX_LEN_0FXOP_08_CE */
10249 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10252 /* VEX_LEN_0FXOP_08_CF */
10254 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10257 /* VEX_LEN_0FXOP_08_EC */
10259 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10262 /* VEX_LEN_0FXOP_08_ED */
10264 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10267 /* VEX_LEN_0FXOP_08_EE */
10269 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10272 /* VEX_LEN_0FXOP_08_EF */
10274 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10277 /* VEX_LEN_0FXOP_09_80 */
10279 { "vfrczps", { XM
, EXxmm
}, 0 },
10280 { "vfrczps", { XM
, EXymmq
}, 0 },
10283 /* VEX_LEN_0FXOP_09_81 */
10285 { "vfrczpd", { XM
, EXxmm
}, 0 },
10286 { "vfrczpd", { XM
, EXymmq
}, 0 },
10290 static const struct dis386 vex_w_table
[][2] = {
10292 /* VEX_W_0F10_P_0 */
10293 { "vmovups", { XM
, EXx
}, 0 },
10296 /* VEX_W_0F10_P_1 */
10297 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
10300 /* VEX_W_0F10_P_2 */
10301 { "vmovupd", { XM
, EXx
}, 0 },
10304 /* VEX_W_0F10_P_3 */
10305 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
10308 /* VEX_W_0F11_P_0 */
10309 { "vmovups", { EXxS
, XM
}, 0 },
10312 /* VEX_W_0F11_P_1 */
10313 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
10316 /* VEX_W_0F11_P_2 */
10317 { "vmovupd", { EXxS
, XM
}, 0 },
10320 /* VEX_W_0F11_P_3 */
10321 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
10324 /* VEX_W_0F12_P_0_M_0 */
10325 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
10328 /* VEX_W_0F12_P_0_M_1 */
10329 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
10332 /* VEX_W_0F12_P_1 */
10333 { "vmovsldup", { XM
, EXx
}, 0 },
10336 /* VEX_W_0F12_P_2 */
10337 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
10340 /* VEX_W_0F12_P_3 */
10341 { "vmovddup", { XM
, EXymmq
}, 0 },
10344 /* VEX_W_0F13_M_0 */
10345 { "vmovlpX", { EXq
, XM
}, 0 },
10349 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
10353 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
10356 /* VEX_W_0F16_P_0_M_0 */
10357 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
10360 /* VEX_W_0F16_P_0_M_1 */
10361 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
10364 /* VEX_W_0F16_P_1 */
10365 { "vmovshdup", { XM
, EXx
}, 0 },
10368 /* VEX_W_0F16_P_2 */
10369 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
10372 /* VEX_W_0F17_M_0 */
10373 { "vmovhpX", { EXq
, XM
}, 0 },
10377 { "vmovapX", { XM
, EXx
}, 0 },
10381 { "vmovapX", { EXxS
, XM
}, 0 },
10384 /* VEX_W_0F2B_M_0 */
10385 { "vmovntpX", { Mx
, XM
}, 0 },
10388 /* VEX_W_0F2E_P_0 */
10389 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
10392 /* VEX_W_0F2E_P_2 */
10393 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
10396 /* VEX_W_0F2F_P_0 */
10397 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
10400 /* VEX_W_0F2F_P_2 */
10401 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
10404 /* VEX_W_0F41_P_0_LEN_1 */
10405 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
10406 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
10409 /* VEX_W_0F41_P_2_LEN_1 */
10410 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
10411 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
10414 /* VEX_W_0F42_P_0_LEN_1 */
10415 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
10416 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
10419 /* VEX_W_0F42_P_2_LEN_1 */
10420 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
10421 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
10424 /* VEX_W_0F44_P_0_LEN_0 */
10425 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
10426 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
10429 /* VEX_W_0F44_P_2_LEN_0 */
10430 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
10431 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
10434 /* VEX_W_0F45_P_0_LEN_1 */
10435 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
10436 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
10439 /* VEX_W_0F45_P_2_LEN_1 */
10440 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
10441 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
10444 /* VEX_W_0F46_P_0_LEN_1 */
10445 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
10446 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
10449 /* VEX_W_0F46_P_2_LEN_1 */
10450 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
10451 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
10454 /* VEX_W_0F47_P_0_LEN_1 */
10455 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
10456 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
10459 /* VEX_W_0F47_P_2_LEN_1 */
10460 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
10461 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
10464 /* VEX_W_0F4A_P_0_LEN_1 */
10465 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
10466 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
10469 /* VEX_W_0F4A_P_2_LEN_1 */
10470 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
10471 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
10474 /* VEX_W_0F4B_P_0_LEN_1 */
10475 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
10476 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
10479 /* VEX_W_0F4B_P_2_LEN_1 */
10480 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
10483 /* VEX_W_0F50_M_0 */
10484 { "vmovmskpX", { Gdq
, XS
}, 0 },
10487 /* VEX_W_0F51_P_0 */
10488 { "vsqrtps", { XM
, EXx
}, 0 },
10491 /* VEX_W_0F51_P_1 */
10492 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10495 /* VEX_W_0F51_P_2 */
10496 { "vsqrtpd", { XM
, EXx
}, 0 },
10499 /* VEX_W_0F51_P_3 */
10500 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10503 /* VEX_W_0F52_P_0 */
10504 { "vrsqrtps", { XM
, EXx
}, 0 },
10507 /* VEX_W_0F52_P_1 */
10508 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10511 /* VEX_W_0F53_P_0 */
10512 { "vrcpps", { XM
, EXx
}, 0 },
10515 /* VEX_W_0F53_P_1 */
10516 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10519 /* VEX_W_0F58_P_0 */
10520 { "vaddps", { XM
, Vex
, EXx
}, 0 },
10523 /* VEX_W_0F58_P_1 */
10524 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10527 /* VEX_W_0F58_P_2 */
10528 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
10531 /* VEX_W_0F58_P_3 */
10532 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10535 /* VEX_W_0F59_P_0 */
10536 { "vmulps", { XM
, Vex
, EXx
}, 0 },
10539 /* VEX_W_0F59_P_1 */
10540 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10543 /* VEX_W_0F59_P_2 */
10544 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
10547 /* VEX_W_0F59_P_3 */
10548 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10551 /* VEX_W_0F5A_P_0 */
10552 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
10555 /* VEX_W_0F5A_P_1 */
10556 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10559 /* VEX_W_0F5A_P_3 */
10560 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10563 /* VEX_W_0F5B_P_0 */
10564 { "vcvtdq2ps", { XM
, EXx
}, 0 },
10567 /* VEX_W_0F5B_P_1 */
10568 { "vcvttps2dq", { XM
, EXx
}, 0 },
10571 /* VEX_W_0F5B_P_2 */
10572 { "vcvtps2dq", { XM
, EXx
}, 0 },
10575 /* VEX_W_0F5C_P_0 */
10576 { "vsubps", { XM
, Vex
, EXx
}, 0 },
10579 /* VEX_W_0F5C_P_1 */
10580 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10583 /* VEX_W_0F5C_P_2 */
10584 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
10587 /* VEX_W_0F5C_P_3 */
10588 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10591 /* VEX_W_0F5D_P_0 */
10592 { "vminps", { XM
, Vex
, EXx
}, 0 },
10595 /* VEX_W_0F5D_P_1 */
10596 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10599 /* VEX_W_0F5D_P_2 */
10600 { "vminpd", { XM
, Vex
, EXx
}, 0 },
10603 /* VEX_W_0F5D_P_3 */
10604 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10607 /* VEX_W_0F5E_P_0 */
10608 { "vdivps", { XM
, Vex
, EXx
}, 0 },
10611 /* VEX_W_0F5E_P_1 */
10612 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10615 /* VEX_W_0F5E_P_2 */
10616 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
10619 /* VEX_W_0F5E_P_3 */
10620 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10623 /* VEX_W_0F5F_P_0 */
10624 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
10627 /* VEX_W_0F5F_P_1 */
10628 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10631 /* VEX_W_0F5F_P_2 */
10632 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
10635 /* VEX_W_0F5F_P_3 */
10636 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10639 /* VEX_W_0F60_P_2 */
10640 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
10643 /* VEX_W_0F61_P_2 */
10644 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
10647 /* VEX_W_0F62_P_2 */
10648 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
10651 /* VEX_W_0F63_P_2 */
10652 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
10655 /* VEX_W_0F64_P_2 */
10656 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
10659 /* VEX_W_0F65_P_2 */
10660 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
10663 /* VEX_W_0F66_P_2 */
10664 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
10667 /* VEX_W_0F67_P_2 */
10668 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
10671 /* VEX_W_0F68_P_2 */
10672 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
10675 /* VEX_W_0F69_P_2 */
10676 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
10679 /* VEX_W_0F6A_P_2 */
10680 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
10683 /* VEX_W_0F6B_P_2 */
10684 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
10687 /* VEX_W_0F6C_P_2 */
10688 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
10691 /* VEX_W_0F6D_P_2 */
10692 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
10695 /* VEX_W_0F6F_P_1 */
10696 { "vmovdqu", { XM
, EXx
}, 0 },
10699 /* VEX_W_0F6F_P_2 */
10700 { "vmovdqa", { XM
, EXx
}, 0 },
10703 /* VEX_W_0F70_P_1 */
10704 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
10707 /* VEX_W_0F70_P_2 */
10708 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
10711 /* VEX_W_0F70_P_3 */
10712 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
10715 /* VEX_W_0F71_R_2_P_2 */
10716 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
10719 /* VEX_W_0F71_R_4_P_2 */
10720 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
10723 /* VEX_W_0F71_R_6_P_2 */
10724 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
10727 /* VEX_W_0F72_R_2_P_2 */
10728 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
10731 /* VEX_W_0F72_R_4_P_2 */
10732 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
10735 /* VEX_W_0F72_R_6_P_2 */
10736 { "vpslld", { Vex
, XS
, Ib
}, 0 },
10739 /* VEX_W_0F73_R_2_P_2 */
10740 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
10743 /* VEX_W_0F73_R_3_P_2 */
10744 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
10747 /* VEX_W_0F73_R_6_P_2 */
10748 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
10751 /* VEX_W_0F73_R_7_P_2 */
10752 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
10755 /* VEX_W_0F74_P_2 */
10756 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
10759 /* VEX_W_0F75_P_2 */
10760 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
10763 /* VEX_W_0F76_P_2 */
10764 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
10767 /* VEX_W_0F77_P_0 */
10768 { "", { VZERO
}, 0 },
10771 /* VEX_W_0F7C_P_2 */
10772 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
10775 /* VEX_W_0F7C_P_3 */
10776 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
10779 /* VEX_W_0F7D_P_2 */
10780 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
10783 /* VEX_W_0F7D_P_3 */
10784 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
10787 /* VEX_W_0F7E_P_1 */
10788 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
10791 /* VEX_W_0F7F_P_1 */
10792 { "vmovdqu", { EXxS
, XM
}, 0 },
10795 /* VEX_W_0F7F_P_2 */
10796 { "vmovdqa", { EXxS
, XM
}, 0 },
10799 /* VEX_W_0F90_P_0_LEN_0 */
10800 { "kmovw", { MaskG
, MaskE
}, 0 },
10801 { "kmovq", { MaskG
, MaskE
}, 0 },
10804 /* VEX_W_0F90_P_2_LEN_0 */
10805 { "kmovb", { MaskG
, MaskBDE
}, 0 },
10806 { "kmovd", { MaskG
, MaskBDE
}, 0 },
10809 /* VEX_W_0F91_P_0_LEN_0 */
10810 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
10811 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
10814 /* VEX_W_0F91_P_2_LEN_0 */
10815 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
10816 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
10819 /* VEX_W_0F92_P_0_LEN_0 */
10820 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10823 /* VEX_W_0F92_P_2_LEN_0 */
10824 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10827 /* VEX_W_0F92_P_3_LEN_0 */
10828 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0
) },
10829 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0
) },
10832 /* VEX_W_0F93_P_0_LEN_0 */
10833 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10836 /* VEX_W_0F93_P_2_LEN_0 */
10837 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10840 /* VEX_W_0F93_P_3_LEN_0 */
10841 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0
) },
10842 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0
) },
10845 /* VEX_W_0F98_P_0_LEN_0 */
10846 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10847 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10850 /* VEX_W_0F98_P_2_LEN_0 */
10851 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10852 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10855 /* VEX_W_0F99_P_0_LEN_0 */
10856 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10857 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10860 /* VEX_W_0F99_P_2_LEN_0 */
10861 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10862 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10865 /* VEX_W_0FAE_R_2_M_0 */
10866 { "vldmxcsr", { Md
}, 0 },
10869 /* VEX_W_0FAE_R_3_M_0 */
10870 { "vstmxcsr", { Md
}, 0 },
10873 /* VEX_W_0FC2_P_0 */
10874 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
10877 /* VEX_W_0FC2_P_1 */
10878 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
10881 /* VEX_W_0FC2_P_2 */
10882 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
10885 /* VEX_W_0FC2_P_3 */
10886 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
10889 /* VEX_W_0FC4_P_2 */
10890 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
10893 /* VEX_W_0FC5_P_2 */
10894 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
10897 /* VEX_W_0FD0_P_2 */
10898 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
10901 /* VEX_W_0FD0_P_3 */
10902 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
10905 /* VEX_W_0FD1_P_2 */
10906 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
10909 /* VEX_W_0FD2_P_2 */
10910 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
10913 /* VEX_W_0FD3_P_2 */
10914 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
10917 /* VEX_W_0FD4_P_2 */
10918 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
10921 /* VEX_W_0FD5_P_2 */
10922 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
10925 /* VEX_W_0FD6_P_2 */
10926 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
10929 /* VEX_W_0FD7_P_2_M_1 */
10930 { "vpmovmskb", { Gdq
, XS
}, 0 },
10933 /* VEX_W_0FD8_P_2 */
10934 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
10937 /* VEX_W_0FD9_P_2 */
10938 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
10941 /* VEX_W_0FDA_P_2 */
10942 { "vpminub", { XM
, Vex
, EXx
}, 0 },
10945 /* VEX_W_0FDB_P_2 */
10946 { "vpand", { XM
, Vex
, EXx
}, 0 },
10949 /* VEX_W_0FDC_P_2 */
10950 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
10953 /* VEX_W_0FDD_P_2 */
10954 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
10957 /* VEX_W_0FDE_P_2 */
10958 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
10961 /* VEX_W_0FDF_P_2 */
10962 { "vpandn", { XM
, Vex
, EXx
}, 0 },
10965 /* VEX_W_0FE0_P_2 */
10966 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
10969 /* VEX_W_0FE1_P_2 */
10970 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
10973 /* VEX_W_0FE2_P_2 */
10974 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
10977 /* VEX_W_0FE3_P_2 */
10978 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
10981 /* VEX_W_0FE4_P_2 */
10982 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
10985 /* VEX_W_0FE5_P_2 */
10986 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
10989 /* VEX_W_0FE6_P_1 */
10990 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
10993 /* VEX_W_0FE6_P_2 */
10994 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
10997 /* VEX_W_0FE6_P_3 */
10998 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
11001 /* VEX_W_0FE7_P_2_M_0 */
11002 { "vmovntdq", { Mx
, XM
}, 0 },
11005 /* VEX_W_0FE8_P_2 */
11006 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
11009 /* VEX_W_0FE9_P_2 */
11010 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
11013 /* VEX_W_0FEA_P_2 */
11014 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
11017 /* VEX_W_0FEB_P_2 */
11018 { "vpor", { XM
, Vex
, EXx
}, 0 },
11021 /* VEX_W_0FEC_P_2 */
11022 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
11025 /* VEX_W_0FED_P_2 */
11026 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
11029 /* VEX_W_0FEE_P_2 */
11030 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
11033 /* VEX_W_0FEF_P_2 */
11034 { "vpxor", { XM
, Vex
, EXx
}, 0 },
11037 /* VEX_W_0FF0_P_3_M_0 */
11038 { "vlddqu", { XM
, M
}, 0 },
11041 /* VEX_W_0FF1_P_2 */
11042 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
11045 /* VEX_W_0FF2_P_2 */
11046 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
11049 /* VEX_W_0FF3_P_2 */
11050 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
11053 /* VEX_W_0FF4_P_2 */
11054 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
11057 /* VEX_W_0FF5_P_2 */
11058 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
11061 /* VEX_W_0FF6_P_2 */
11062 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
11065 /* VEX_W_0FF7_P_2 */
11066 { "vmaskmovdqu", { XM
, XS
}, 0 },
11069 /* VEX_W_0FF8_P_2 */
11070 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
11073 /* VEX_W_0FF9_P_2 */
11074 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
11077 /* VEX_W_0FFA_P_2 */
11078 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
11081 /* VEX_W_0FFB_P_2 */
11082 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
11085 /* VEX_W_0FFC_P_2 */
11086 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
11089 /* VEX_W_0FFD_P_2 */
11090 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
11093 /* VEX_W_0FFE_P_2 */
11094 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
11097 /* VEX_W_0F3800_P_2 */
11098 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
11101 /* VEX_W_0F3801_P_2 */
11102 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
11105 /* VEX_W_0F3802_P_2 */
11106 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
11109 /* VEX_W_0F3803_P_2 */
11110 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
11113 /* VEX_W_0F3804_P_2 */
11114 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
11117 /* VEX_W_0F3805_P_2 */
11118 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
11121 /* VEX_W_0F3806_P_2 */
11122 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
11125 /* VEX_W_0F3807_P_2 */
11126 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
11129 /* VEX_W_0F3808_P_2 */
11130 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
11133 /* VEX_W_0F3809_P_2 */
11134 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
11137 /* VEX_W_0F380A_P_2 */
11138 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
11141 /* VEX_W_0F380B_P_2 */
11142 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
11145 /* VEX_W_0F380C_P_2 */
11146 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
11149 /* VEX_W_0F380D_P_2 */
11150 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
11153 /* VEX_W_0F380E_P_2 */
11154 { "vtestps", { XM
, EXx
}, 0 },
11157 /* VEX_W_0F380F_P_2 */
11158 { "vtestpd", { XM
, EXx
}, 0 },
11161 /* VEX_W_0F3816_P_2 */
11162 { "vpermps", { XM
, Vex
, EXx
}, 0 },
11165 /* VEX_W_0F3817_P_2 */
11166 { "vptest", { XM
, EXx
}, 0 },
11169 /* VEX_W_0F3818_P_2 */
11170 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
11173 /* VEX_W_0F3819_P_2 */
11174 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
11177 /* VEX_W_0F381A_P_2_M_0 */
11178 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
11181 /* VEX_W_0F381C_P_2 */
11182 { "vpabsb", { XM
, EXx
}, 0 },
11185 /* VEX_W_0F381D_P_2 */
11186 { "vpabsw", { XM
, EXx
}, 0 },
11189 /* VEX_W_0F381E_P_2 */
11190 { "vpabsd", { XM
, EXx
}, 0 },
11193 /* VEX_W_0F3820_P_2 */
11194 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
11197 /* VEX_W_0F3821_P_2 */
11198 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
11201 /* VEX_W_0F3822_P_2 */
11202 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
11205 /* VEX_W_0F3823_P_2 */
11206 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
11209 /* VEX_W_0F3824_P_2 */
11210 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
11213 /* VEX_W_0F3825_P_2 */
11214 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
11217 /* VEX_W_0F3828_P_2 */
11218 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
11221 /* VEX_W_0F3829_P_2 */
11222 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
11225 /* VEX_W_0F382A_P_2_M_0 */
11226 { "vmovntdqa", { XM
, Mx
}, 0 },
11229 /* VEX_W_0F382B_P_2 */
11230 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
11233 /* VEX_W_0F382C_P_2_M_0 */
11234 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
11237 /* VEX_W_0F382D_P_2_M_0 */
11238 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
11241 /* VEX_W_0F382E_P_2_M_0 */
11242 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
11245 /* VEX_W_0F382F_P_2_M_0 */
11246 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
11249 /* VEX_W_0F3830_P_2 */
11250 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
11253 /* VEX_W_0F3831_P_2 */
11254 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
11257 /* VEX_W_0F3832_P_2 */
11258 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
11261 /* VEX_W_0F3833_P_2 */
11262 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
11265 /* VEX_W_0F3834_P_2 */
11266 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
11269 /* VEX_W_0F3835_P_2 */
11270 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
11273 /* VEX_W_0F3836_P_2 */
11274 { "vpermd", { XM
, Vex
, EXx
}, 0 },
11277 /* VEX_W_0F3837_P_2 */
11278 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
11281 /* VEX_W_0F3838_P_2 */
11282 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
11285 /* VEX_W_0F3839_P_2 */
11286 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
11289 /* VEX_W_0F383A_P_2 */
11290 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
11293 /* VEX_W_0F383B_P_2 */
11294 { "vpminud", { XM
, Vex
, EXx
}, 0 },
11297 /* VEX_W_0F383C_P_2 */
11298 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
11301 /* VEX_W_0F383D_P_2 */
11302 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
11305 /* VEX_W_0F383E_P_2 */
11306 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
11309 /* VEX_W_0F383F_P_2 */
11310 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
11313 /* VEX_W_0F3840_P_2 */
11314 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
11317 /* VEX_W_0F3841_P_2 */
11318 { "vphminposuw", { XM
, EXx
}, 0 },
11321 /* VEX_W_0F3846_P_2 */
11322 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
11325 /* VEX_W_0F3858_P_2 */
11326 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
11329 /* VEX_W_0F3859_P_2 */
11330 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
11333 /* VEX_W_0F385A_P_2_M_0 */
11334 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
11337 /* VEX_W_0F3878_P_2 */
11338 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
11341 /* VEX_W_0F3879_P_2 */
11342 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
11345 /* VEX_W_0F38CF_P_2 */
11346 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
11349 /* VEX_W_0F38DB_P_2 */
11350 { "vaesimc", { XM
, EXx
}, 0 },
11353 /* VEX_W_0F3A00_P_2 */
11355 { "vpermq", { XM
, EXx
, Ib
}, 0 },
11358 /* VEX_W_0F3A01_P_2 */
11360 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
11363 /* VEX_W_0F3A02_P_2 */
11364 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
11367 /* VEX_W_0F3A04_P_2 */
11368 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
11371 /* VEX_W_0F3A05_P_2 */
11372 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
11375 /* VEX_W_0F3A06_P_2 */
11376 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11379 /* VEX_W_0F3A08_P_2 */
11380 { "vroundps", { XM
, EXx
, Ib
}, 0 },
11383 /* VEX_W_0F3A09_P_2 */
11384 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
11387 /* VEX_W_0F3A0A_P_2 */
11388 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
11391 /* VEX_W_0F3A0B_P_2 */
11392 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
11395 /* VEX_W_0F3A0C_P_2 */
11396 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
11399 /* VEX_W_0F3A0D_P_2 */
11400 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
11403 /* VEX_W_0F3A0E_P_2 */
11404 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
11407 /* VEX_W_0F3A0F_P_2 */
11408 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
11411 /* VEX_W_0F3A14_P_2 */
11412 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
11415 /* VEX_W_0F3A15_P_2 */
11416 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
11419 /* VEX_W_0F3A18_P_2 */
11420 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11423 /* VEX_W_0F3A19_P_2 */
11424 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
11427 /* VEX_W_0F3A20_P_2 */
11428 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
11431 /* VEX_W_0F3A21_P_2 */
11432 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
11435 /* VEX_W_0F3A30_P_2_LEN_0 */
11436 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
11437 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
11440 /* VEX_W_0F3A31_P_2_LEN_0 */
11441 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
11442 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
11445 /* VEX_W_0F3A32_P_2_LEN_0 */
11446 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
11447 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
11450 /* VEX_W_0F3A33_P_2_LEN_0 */
11451 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
11452 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
11455 /* VEX_W_0F3A38_P_2 */
11456 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11459 /* VEX_W_0F3A39_P_2 */
11460 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
11463 /* VEX_W_0F3A40_P_2 */
11464 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
11467 /* VEX_W_0F3A41_P_2 */
11468 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
11471 /* VEX_W_0F3A42_P_2 */
11472 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
11475 /* VEX_W_0F3A46_P_2 */
11476 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11479 /* VEX_W_0F3A48_P_2 */
11480 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11481 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11484 /* VEX_W_0F3A49_P_2 */
11485 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11486 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11489 /* VEX_W_0F3A4A_P_2 */
11490 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11493 /* VEX_W_0F3A4B_P_2 */
11494 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11497 /* VEX_W_0F3A4C_P_2 */
11498 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11501 /* VEX_W_0F3A62_P_2 */
11502 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
11505 /* VEX_W_0F3A63_P_2 */
11506 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
11509 /* VEX_W_0F3ACE_P_2 */
11511 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
11514 /* VEX_W_0F3ACF_P_2 */
11516 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
11519 /* VEX_W_0F3ADF_P_2 */
11520 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
11522 #define NEED_VEX_W_TABLE
11523 #include "i386-dis-evex.h"
11524 #undef NEED_VEX_W_TABLE
11527 static const struct dis386 mod_table
[][2] = {
11530 { "leaS", { Gv
, M
}, 0 },
11535 { RM_TABLE (RM_C6_REG_7
) },
11540 { RM_TABLE (RM_C7_REG_7
) },
11544 { "Jcall^", { indirEp
}, 0 },
11548 { "Jjmp^", { indirEp
}, 0 },
11551 /* MOD_0F01_REG_0 */
11552 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11553 { RM_TABLE (RM_0F01_REG_0
) },
11556 /* MOD_0F01_REG_1 */
11557 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11558 { RM_TABLE (RM_0F01_REG_1
) },
11561 /* MOD_0F01_REG_2 */
11562 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11563 { RM_TABLE (RM_0F01_REG_2
) },
11566 /* MOD_0F01_REG_3 */
11567 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11568 { RM_TABLE (RM_0F01_REG_3
) },
11571 /* MOD_0F01_REG_5 */
11572 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5
) },
11573 { RM_TABLE (RM_0F01_REG_5
) },
11576 /* MOD_0F01_REG_7 */
11577 { "invlpg", { Mb
}, 0 },
11578 { RM_TABLE (RM_0F01_REG_7
) },
11581 /* MOD_0F12_PREFIX_0 */
11582 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
11583 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
11587 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
11590 /* MOD_0F16_PREFIX_0 */
11591 { "movhps", { XM
, EXq
}, 0 },
11592 { "movlhps", { XM
, EXq
}, 0 },
11596 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
11599 /* MOD_0F18_REG_0 */
11600 { "prefetchnta", { Mb
}, 0 },
11603 /* MOD_0F18_REG_1 */
11604 { "prefetcht0", { Mb
}, 0 },
11607 /* MOD_0F18_REG_2 */
11608 { "prefetcht1", { Mb
}, 0 },
11611 /* MOD_0F18_REG_3 */
11612 { "prefetcht2", { Mb
}, 0 },
11615 /* MOD_0F18_REG_4 */
11616 { "nop/reserved", { Mb
}, 0 },
11619 /* MOD_0F18_REG_5 */
11620 { "nop/reserved", { Mb
}, 0 },
11623 /* MOD_0F18_REG_6 */
11624 { "nop/reserved", { Mb
}, 0 },
11627 /* MOD_0F18_REG_7 */
11628 { "nop/reserved", { Mb
}, 0 },
11631 /* MOD_0F1A_PREFIX_0 */
11632 { "bndldx", { Gbnd
, Ev_bnd
}, 0 },
11633 { "nopQ", { Ev
}, 0 },
11636 /* MOD_0F1B_PREFIX_0 */
11637 { "bndstx", { Ev_bnd
, Gbnd
}, 0 },
11638 { "nopQ", { Ev
}, 0 },
11641 /* MOD_0F1B_PREFIX_1 */
11642 { "bndmk", { Gbnd
, Ev_bnd
}, 0 },
11643 { "nopQ", { Ev
}, 0 },
11646 /* MOD_0F1C_PREFIX_0 */
11647 { REG_TABLE (REG_0F1C_MOD_0
) },
11648 { "nopQ", { Ev
}, 0 },
11651 /* MOD_0F1E_PREFIX_1 */
11652 { "nopQ", { Ev
}, 0 },
11653 { REG_TABLE (REG_0F1E_MOD_3
) },
11658 { "movL", { Rd
, Td
}, 0 },
11663 { "movL", { Td
, Rd
}, 0 },
11666 /* MOD_0F2B_PREFIX_0 */
11667 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
11670 /* MOD_0F2B_PREFIX_1 */
11671 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
11674 /* MOD_0F2B_PREFIX_2 */
11675 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
11678 /* MOD_0F2B_PREFIX_3 */
11679 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
11684 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
11687 /* MOD_0F71_REG_2 */
11689 { "psrlw", { MS
, Ib
}, 0 },
11692 /* MOD_0F71_REG_4 */
11694 { "psraw", { MS
, Ib
}, 0 },
11697 /* MOD_0F71_REG_6 */
11699 { "psllw", { MS
, Ib
}, 0 },
11702 /* MOD_0F72_REG_2 */
11704 { "psrld", { MS
, Ib
}, 0 },
11707 /* MOD_0F72_REG_4 */
11709 { "psrad", { MS
, Ib
}, 0 },
11712 /* MOD_0F72_REG_6 */
11714 { "pslld", { MS
, Ib
}, 0 },
11717 /* MOD_0F73_REG_2 */
11719 { "psrlq", { MS
, Ib
}, 0 },
11722 /* MOD_0F73_REG_3 */
11724 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11727 /* MOD_0F73_REG_6 */
11729 { "psllq", { MS
, Ib
}, 0 },
11732 /* MOD_0F73_REG_7 */
11734 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11737 /* MOD_0FAE_REG_0 */
11738 { "fxsave", { FXSAVE
}, 0 },
11739 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11742 /* MOD_0FAE_REG_1 */
11743 { "fxrstor", { FXSAVE
}, 0 },
11744 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11747 /* MOD_0FAE_REG_2 */
11748 { "ldmxcsr", { Md
}, 0 },
11749 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11752 /* MOD_0FAE_REG_3 */
11753 { "stmxcsr", { Md
}, 0 },
11754 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11757 /* MOD_0FAE_REG_4 */
11758 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4
) },
11759 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4
) },
11762 /* MOD_0FAE_REG_5 */
11763 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5
) },
11764 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5
) },
11767 /* MOD_0FAE_REG_6 */
11768 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6
) },
11769 { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6
) },
11772 /* MOD_0FAE_REG_7 */
11773 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11774 { RM_TABLE (RM_0FAE_REG_7
) },
11778 { "lssS", { Gv
, Mp
}, 0 },
11782 { "lfsS", { Gv
, Mp
}, 0 },
11786 { "lgsS", { Gv
, Mp
}, 0 },
11790 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
11793 /* MOD_0FC7_REG_3 */
11794 { "xrstors", { FXSAVE
}, 0 },
11797 /* MOD_0FC7_REG_4 */
11798 { "xsavec", { FXSAVE
}, 0 },
11801 /* MOD_0FC7_REG_5 */
11802 { "xsaves", { FXSAVE
}, 0 },
11805 /* MOD_0FC7_REG_6 */
11806 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
11807 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
11810 /* MOD_0FC7_REG_7 */
11811 { "vmptrst", { Mq
}, 0 },
11812 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
11817 { "pmovmskb", { Gdq
, MS
}, 0 },
11820 /* MOD_0FE7_PREFIX_2 */
11821 { "movntdq", { Mx
, XM
}, 0 },
11824 /* MOD_0FF0_PREFIX_3 */
11825 { "lddqu", { XM
, M
}, 0 },
11828 /* MOD_0F382A_PREFIX_2 */
11829 { "movntdqa", { XM
, Mx
}, 0 },
11832 /* MOD_0F38F5_PREFIX_2 */
11833 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
11836 /* MOD_0F38F6_PREFIX_0 */
11837 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
11841 { "bound{S|}", { Gv
, Ma
}, 0 },
11842 { EVEX_TABLE (EVEX_0F
) },
11846 { "lesS", { Gv
, Mp
}, 0 },
11847 { VEX_C4_TABLE (VEX_0F
) },
11851 { "ldsS", { Gv
, Mp
}, 0 },
11852 { VEX_C5_TABLE (VEX_0F
) },
11855 /* MOD_VEX_0F12_PREFIX_0 */
11856 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11857 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11861 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11864 /* MOD_VEX_0F16_PREFIX_0 */
11865 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11866 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11870 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11874 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11877 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11879 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
11882 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11884 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
11887 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11889 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
11892 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11894 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
11897 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11899 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
11902 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11904 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
11907 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11909 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
11912 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11914 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
11917 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11919 { "knotw", { MaskG
, MaskR
}, 0 },
11922 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11924 { "knotq", { MaskG
, MaskR
}, 0 },
11927 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11929 { "knotb", { MaskG
, MaskR
}, 0 },
11932 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11934 { "knotd", { MaskG
, MaskR
}, 0 },
11937 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11939 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
11942 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11944 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
11947 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11949 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
11952 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11954 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
11957 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11959 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
11962 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11964 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
11967 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11969 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
11972 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11974 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
11977 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11979 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
11982 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11984 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
11987 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11989 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
11992 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11994 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
11997 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11999 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
12002 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12004 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
12007 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12009 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
12012 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12014 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
12017 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12019 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
12022 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12024 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
12027 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12029 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
12034 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
12037 /* MOD_VEX_0F71_REG_2 */
12039 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
12042 /* MOD_VEX_0F71_REG_4 */
12044 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
12047 /* MOD_VEX_0F71_REG_6 */
12049 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
12052 /* MOD_VEX_0F72_REG_2 */
12054 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
12057 /* MOD_VEX_0F72_REG_4 */
12059 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
12062 /* MOD_VEX_0F72_REG_6 */
12064 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
12067 /* MOD_VEX_0F73_REG_2 */
12069 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
12072 /* MOD_VEX_0F73_REG_3 */
12074 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
12077 /* MOD_VEX_0F73_REG_6 */
12079 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
12082 /* MOD_VEX_0F73_REG_7 */
12084 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
12087 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12088 { "kmovw", { Ew
, MaskG
}, 0 },
12092 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12093 { "kmovq", { Eq
, MaskG
}, 0 },
12097 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12098 { "kmovb", { Eb
, MaskG
}, 0 },
12102 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12103 { "kmovd", { Ed
, MaskG
}, 0 },
12107 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12109 { "kmovw", { MaskG
, Rdq
}, 0 },
12112 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12114 { "kmovb", { MaskG
, Rdq
}, 0 },
12117 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12119 { "kmovd", { MaskG
, Rdq
}, 0 },
12122 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12124 { "kmovq", { MaskG
, Rdq
}, 0 },
12127 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12129 { "kmovw", { Gdq
, MaskR
}, 0 },
12132 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12134 { "kmovb", { Gdq
, MaskR
}, 0 },
12137 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12139 { "kmovd", { Gdq
, MaskR
}, 0 },
12142 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12144 { "kmovq", { Gdq
, MaskR
}, 0 },
12147 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12149 { "kortestw", { MaskG
, MaskR
}, 0 },
12152 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12154 { "kortestq", { MaskG
, MaskR
}, 0 },
12157 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12159 { "kortestb", { MaskG
, MaskR
}, 0 },
12162 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12164 { "kortestd", { MaskG
, MaskR
}, 0 },
12167 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12169 { "ktestw", { MaskG
, MaskR
}, 0 },
12172 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12174 { "ktestq", { MaskG
, MaskR
}, 0 },
12177 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12179 { "ktestb", { MaskG
, MaskR
}, 0 },
12182 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12184 { "ktestd", { MaskG
, MaskR
}, 0 },
12187 /* MOD_VEX_0FAE_REG_2 */
12188 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
12191 /* MOD_VEX_0FAE_REG_3 */
12192 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
12195 /* MOD_VEX_0FD7_PREFIX_2 */
12197 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
12200 /* MOD_VEX_0FE7_PREFIX_2 */
12201 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
12204 /* MOD_VEX_0FF0_PREFIX_3 */
12205 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
12208 /* MOD_VEX_0F381A_PREFIX_2 */
12209 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
12212 /* MOD_VEX_0F382A_PREFIX_2 */
12213 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
12216 /* MOD_VEX_0F382C_PREFIX_2 */
12217 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
12220 /* MOD_VEX_0F382D_PREFIX_2 */
12221 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
12224 /* MOD_VEX_0F382E_PREFIX_2 */
12225 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
12228 /* MOD_VEX_0F382F_PREFIX_2 */
12229 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
12232 /* MOD_VEX_0F385A_PREFIX_2 */
12233 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
12236 /* MOD_VEX_0F388C_PREFIX_2 */
12237 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
12240 /* MOD_VEX_0F388E_PREFIX_2 */
12241 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
12244 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12246 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
12249 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12251 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
12254 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12256 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
12259 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12261 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
12264 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12266 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
12269 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12271 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
12274 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12276 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
12279 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12281 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
12283 #define NEED_MOD_TABLE
12284 #include "i386-dis-evex.h"
12285 #undef NEED_MOD_TABLE
12288 static const struct dis386 rm_table
[][8] = {
12291 { "xabort", { Skip_MODRM
, Ib
}, 0 },
12295 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
12298 /* RM_0F01_REG_0 */
12300 { "vmcall", { Skip_MODRM
}, 0 },
12301 { "vmlaunch", { Skip_MODRM
}, 0 },
12302 { "vmresume", { Skip_MODRM
}, 0 },
12303 { "vmxoff", { Skip_MODRM
}, 0 },
12304 { "pconfig", { Skip_MODRM
}, 0 },
12307 /* RM_0F01_REG_1 */
12308 { "monitor", { { OP_Monitor
, 0 } }, 0 },
12309 { "mwait", { { OP_Mwait
, 0 } }, 0 },
12310 { "clac", { Skip_MODRM
}, 0 },
12311 { "stac", { Skip_MODRM
}, 0 },
12315 { "encls", { Skip_MODRM
}, 0 },
12318 /* RM_0F01_REG_2 */
12319 { "xgetbv", { Skip_MODRM
}, 0 },
12320 { "xsetbv", { Skip_MODRM
}, 0 },
12323 { "vmfunc", { Skip_MODRM
}, 0 },
12324 { "xend", { Skip_MODRM
}, 0 },
12325 { "xtest", { Skip_MODRM
}, 0 },
12326 { "enclu", { Skip_MODRM
}, 0 },
12329 /* RM_0F01_REG_3 */
12330 { "vmrun", { Skip_MODRM
}, 0 },
12331 { "vmmcall", { Skip_MODRM
}, 0 },
12332 { "vmload", { Skip_MODRM
}, 0 },
12333 { "vmsave", { Skip_MODRM
}, 0 },
12334 { "stgi", { Skip_MODRM
}, 0 },
12335 { "clgi", { Skip_MODRM
}, 0 },
12336 { "skinit", { Skip_MODRM
}, 0 },
12337 { "invlpga", { Skip_MODRM
}, 0 },
12340 /* RM_0F01_REG_5 */
12341 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0
) },
12343 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2
) },
12347 { "rdpkru", { Skip_MODRM
}, 0 },
12348 { "wrpkru", { Skip_MODRM
}, 0 },
12351 /* RM_0F01_REG_7 */
12352 { "swapgs", { Skip_MODRM
}, 0 },
12353 { "rdtscp", { Skip_MODRM
}, 0 },
12354 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
12355 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
12356 { "clzero", { Skip_MODRM
}, 0 },
12359 /* RM_0F1E_MOD_3_REG_7 */
12360 { "nopQ", { Ev
}, 0 },
12361 { "nopQ", { Ev
}, 0 },
12362 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
12363 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
12364 { "nopQ", { Ev
}, 0 },
12365 { "nopQ", { Ev
}, 0 },
12366 { "nopQ", { Ev
}, 0 },
12367 { "nopQ", { Ev
}, 0 },
12370 /* RM_0FAE_REG_6 */
12371 { "mfence", { Skip_MODRM
}, 0 },
12374 /* RM_0FAE_REG_7 */
12375 { "sfence", { Skip_MODRM
}, 0 },
12380 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12382 /* We use the high bit to indicate different name for the same
12384 #define REP_PREFIX (0xf3 | 0x100)
12385 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12386 #define XRELEASE_PREFIX (0xf3 | 0x400)
12387 #define BND_PREFIX (0xf2 | 0x400)
12388 #define NOTRACK_PREFIX (0x3e | 0x100)
12393 int newrex
, i
, length
;
12399 last_lock_prefix
= -1;
12400 last_repz_prefix
= -1;
12401 last_repnz_prefix
= -1;
12402 last_data_prefix
= -1;
12403 last_addr_prefix
= -1;
12404 last_rex_prefix
= -1;
12405 last_seg_prefix
= -1;
12407 active_seg_prefix
= 0;
12408 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12409 all_prefixes
[i
] = 0;
12412 /* The maximum instruction length is 15bytes. */
12413 while (length
< MAX_CODE_LENGTH
- 1)
12415 FETCH_DATA (the_info
, codep
+ 1);
12419 /* REX prefixes family. */
12436 if (address_mode
== mode_64bit
)
12440 last_rex_prefix
= i
;
12443 prefixes
|= PREFIX_REPZ
;
12444 last_repz_prefix
= i
;
12447 prefixes
|= PREFIX_REPNZ
;
12448 last_repnz_prefix
= i
;
12451 prefixes
|= PREFIX_LOCK
;
12452 last_lock_prefix
= i
;
12455 prefixes
|= PREFIX_CS
;
12456 last_seg_prefix
= i
;
12457 active_seg_prefix
= PREFIX_CS
;
12460 prefixes
|= PREFIX_SS
;
12461 last_seg_prefix
= i
;
12462 active_seg_prefix
= PREFIX_SS
;
12465 prefixes
|= PREFIX_DS
;
12466 last_seg_prefix
= i
;
12467 active_seg_prefix
= PREFIX_DS
;
12470 prefixes
|= PREFIX_ES
;
12471 last_seg_prefix
= i
;
12472 active_seg_prefix
= PREFIX_ES
;
12475 prefixes
|= PREFIX_FS
;
12476 last_seg_prefix
= i
;
12477 active_seg_prefix
= PREFIX_FS
;
12480 prefixes
|= PREFIX_GS
;
12481 last_seg_prefix
= i
;
12482 active_seg_prefix
= PREFIX_GS
;
12485 prefixes
|= PREFIX_DATA
;
12486 last_data_prefix
= i
;
12489 prefixes
|= PREFIX_ADDR
;
12490 last_addr_prefix
= i
;
12493 /* fwait is really an instruction. If there are prefixes
12494 before the fwait, they belong to the fwait, *not* to the
12495 following instruction. */
12497 if (prefixes
|| rex
)
12499 prefixes
|= PREFIX_FWAIT
;
12501 /* This ensures that the previous REX prefixes are noticed
12502 as unused prefixes, as in the return case below. */
12506 prefixes
= PREFIX_FWAIT
;
12511 /* Rex is ignored when followed by another prefix. */
12517 if (*codep
!= FWAIT_OPCODE
)
12518 all_prefixes
[i
++] = *codep
;
12526 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12529 static const char *
12530 prefix_name (int pref
, int sizeflag
)
12532 static const char *rexes
[16] =
12535 "rex.B", /* 0x41 */
12536 "rex.X", /* 0x42 */
12537 "rex.XB", /* 0x43 */
12538 "rex.R", /* 0x44 */
12539 "rex.RB", /* 0x45 */
12540 "rex.RX", /* 0x46 */
12541 "rex.RXB", /* 0x47 */
12542 "rex.W", /* 0x48 */
12543 "rex.WB", /* 0x49 */
12544 "rex.WX", /* 0x4a */
12545 "rex.WXB", /* 0x4b */
12546 "rex.WR", /* 0x4c */
12547 "rex.WRB", /* 0x4d */
12548 "rex.WRX", /* 0x4e */
12549 "rex.WRXB", /* 0x4f */
12554 /* REX prefixes family. */
12571 return rexes
[pref
- 0x40];
12591 return (sizeflag
& DFLAG
) ? "data16" : "data32";
12593 if (address_mode
== mode_64bit
)
12594 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
12596 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
12601 case XACQUIRE_PREFIX
:
12603 case XRELEASE_PREFIX
:
12607 case NOTRACK_PREFIX
:
12614 static char op_out
[MAX_OPERANDS
][100];
12615 static int op_ad
, op_index
[MAX_OPERANDS
];
12616 static int two_source_ops
;
12617 static bfd_vma op_address
[MAX_OPERANDS
];
12618 static bfd_vma op_riprel
[MAX_OPERANDS
];
12619 static bfd_vma start_pc
;
12622 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12623 * (see topic "Redundant prefixes" in the "Differences from 8086"
12624 * section of the "Virtual 8086 Mode" chapter.)
12625 * 'pc' should be the address of this instruction, it will
12626 * be used to print the target address if this is a relative jump or call
12627 * The function returns the length of this instruction in bytes.
12630 static char intel_syntax
;
12631 static char intel_mnemonic
= !SYSV386_COMPAT
;
12632 static char open_char
;
12633 static char close_char
;
12634 static char separator_char
;
12635 static char scale_char
;
12643 static enum x86_64_isa isa64
;
12645 /* Here for backwards compatibility. When gdb stops using
12646 print_insn_i386_att and print_insn_i386_intel these functions can
12647 disappear, and print_insn_i386 be merged into print_insn. */
12649 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
12653 return print_insn (pc
, info
);
12657 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
12661 return print_insn (pc
, info
);
12665 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
12669 return print_insn (pc
, info
);
12673 print_i386_disassembler_options (FILE *stream
)
12675 fprintf (stream
, _("\n\
12676 The following i386/x86-64 specific disassembler options are supported for use\n\
12677 with the -M switch (multiple options should be separated by commas):\n"));
12679 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
12680 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
12681 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
12682 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
12683 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
12684 fprintf (stream
, _(" att-mnemonic\n"
12685 " Display instruction in AT&T mnemonic\n"));
12686 fprintf (stream
, _(" intel-mnemonic\n"
12687 " Display instruction in Intel mnemonic\n"));
12688 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
12689 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
12690 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
12691 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
12692 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
12693 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12694 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
12695 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
12699 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
12701 /* Get a pointer to struct dis386 with a valid name. */
12703 static const struct dis386
*
12704 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
12706 int vindex
, vex_table_index
;
12708 if (dp
->name
!= NULL
)
12711 switch (dp
->op
[0].bytemode
)
12713 case USE_REG_TABLE
:
12714 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
12717 case USE_MOD_TABLE
:
12718 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
12719 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
12723 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
12726 case USE_PREFIX_TABLE
:
12729 /* The prefix in VEX is implicit. */
12730 switch (vex
.prefix
)
12735 case REPE_PREFIX_OPCODE
:
12738 case DATA_PREFIX_OPCODE
:
12741 case REPNE_PREFIX_OPCODE
:
12751 int last_prefix
= -1;
12754 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12755 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12757 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12759 if (last_repz_prefix
> last_repnz_prefix
)
12762 prefix
= PREFIX_REPZ
;
12763 last_prefix
= last_repz_prefix
;
12768 prefix
= PREFIX_REPNZ
;
12769 last_prefix
= last_repnz_prefix
;
12772 /* Check if prefix should be ignored. */
12773 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
12774 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
12779 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12782 prefix
= PREFIX_DATA
;
12783 last_prefix
= last_data_prefix
;
12788 used_prefixes
|= prefix
;
12789 all_prefixes
[last_prefix
] = 0;
12792 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12795 case USE_X86_64_TABLE
:
12796 vindex
= address_mode
== mode_64bit
? 1 : 0;
12797 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12800 case USE_3BYTE_TABLE
:
12801 FETCH_DATA (info
, codep
+ 2);
12803 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12805 modrm
.mod
= (*codep
>> 6) & 3;
12806 modrm
.reg
= (*codep
>> 3) & 7;
12807 modrm
.rm
= *codep
& 7;
12810 case USE_VEX_LEN_TABLE
:
12814 switch (vex
.length
)
12827 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12830 case USE_XOP_8F_TABLE
:
12831 FETCH_DATA (info
, codep
+ 3);
12832 /* All bits in the REX prefix are ignored. */
12834 rex
= ~(*codep
>> 5) & 0x7;
12836 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12837 switch ((*codep
& 0x1f))
12843 vex_table_index
= XOP_08
;
12846 vex_table_index
= XOP_09
;
12849 vex_table_index
= XOP_0A
;
12853 vex
.w
= *codep
& 0x80;
12854 if (vex
.w
&& address_mode
== mode_64bit
)
12857 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12858 if (address_mode
!= mode_64bit
)
12860 /* In 16/32-bit mode REX_B is silently ignored. */
12864 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12865 switch ((*codep
& 0x3))
12870 vex
.prefix
= DATA_PREFIX_OPCODE
;
12873 vex
.prefix
= REPE_PREFIX_OPCODE
;
12876 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12883 dp
= &xop_table
[vex_table_index
][vindex
];
12886 FETCH_DATA (info
, codep
+ 1);
12887 modrm
.mod
= (*codep
>> 6) & 3;
12888 modrm
.reg
= (*codep
>> 3) & 7;
12889 modrm
.rm
= *codep
& 7;
12892 case USE_VEX_C4_TABLE
:
12894 FETCH_DATA (info
, codep
+ 3);
12895 /* All bits in the REX prefix are ignored. */
12897 rex
= ~(*codep
>> 5) & 0x7;
12898 switch ((*codep
& 0x1f))
12904 vex_table_index
= VEX_0F
;
12907 vex_table_index
= VEX_0F38
;
12910 vex_table_index
= VEX_0F3A
;
12914 vex
.w
= *codep
& 0x80;
12915 if (address_mode
== mode_64bit
)
12922 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12923 is ignored, other REX bits are 0 and the highest bit in
12924 VEX.vvvv is also ignored (but we mustn't clear it here). */
12927 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12928 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12929 switch ((*codep
& 0x3))
12934 vex
.prefix
= DATA_PREFIX_OPCODE
;
12937 vex
.prefix
= REPE_PREFIX_OPCODE
;
12940 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12947 dp
= &vex_table
[vex_table_index
][vindex
];
12949 /* There is no MODRM byte for VEX0F 77. */
12950 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
12952 FETCH_DATA (info
, codep
+ 1);
12953 modrm
.mod
= (*codep
>> 6) & 3;
12954 modrm
.reg
= (*codep
>> 3) & 7;
12955 modrm
.rm
= *codep
& 7;
12959 case USE_VEX_C5_TABLE
:
12961 FETCH_DATA (info
, codep
+ 2);
12962 /* All bits in the REX prefix are ignored. */
12964 rex
= (*codep
& 0x80) ? 0 : REX_R
;
12966 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12968 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12969 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12970 switch ((*codep
& 0x3))
12975 vex
.prefix
= DATA_PREFIX_OPCODE
;
12978 vex
.prefix
= REPE_PREFIX_OPCODE
;
12981 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12988 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
12990 /* There is no MODRM byte for VEX 77. */
12991 if (vindex
!= 0x77)
12993 FETCH_DATA (info
, codep
+ 1);
12994 modrm
.mod
= (*codep
>> 6) & 3;
12995 modrm
.reg
= (*codep
>> 3) & 7;
12996 modrm
.rm
= *codep
& 7;
13000 case USE_VEX_W_TABLE
:
13004 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
13007 case USE_EVEX_TABLE
:
13008 two_source_ops
= 0;
13011 FETCH_DATA (info
, codep
+ 4);
13012 /* All bits in the REX prefix are ignored. */
13014 /* The first byte after 0x62. */
13015 rex
= ~(*codep
>> 5) & 0x7;
13016 vex
.r
= *codep
& 0x10;
13017 switch ((*codep
& 0xf))
13020 return &bad_opcode
;
13022 vex_table_index
= EVEX_0F
;
13025 vex_table_index
= EVEX_0F38
;
13028 vex_table_index
= EVEX_0F3A
;
13032 /* The second byte after 0x62. */
13034 vex
.w
= *codep
& 0x80;
13035 if (vex
.w
&& address_mode
== mode_64bit
)
13038 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
13041 if (!(*codep
& 0x4))
13042 return &bad_opcode
;
13044 switch ((*codep
& 0x3))
13049 vex
.prefix
= DATA_PREFIX_OPCODE
;
13052 vex
.prefix
= REPE_PREFIX_OPCODE
;
13055 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13059 /* The third byte after 0x62. */
13062 /* Remember the static rounding bits. */
13063 vex
.ll
= (*codep
>> 5) & 3;
13064 vex
.b
= (*codep
& 0x10) != 0;
13066 vex
.v
= *codep
& 0x8;
13067 vex
.mask_register_specifier
= *codep
& 0x7;
13068 vex
.zeroing
= *codep
& 0x80;
13070 if (address_mode
!= mode_64bit
)
13072 /* In 16/32-bit mode silently ignore following bits. */
13082 dp
= &evex_table
[vex_table_index
][vindex
];
13084 FETCH_DATA (info
, codep
+ 1);
13085 modrm
.mod
= (*codep
>> 6) & 3;
13086 modrm
.reg
= (*codep
>> 3) & 7;
13087 modrm
.rm
= *codep
& 7;
13089 /* Set vector length. */
13090 if (modrm
.mod
== 3 && vex
.b
)
13106 return &bad_opcode
;
13119 if (dp
->name
!= NULL
)
13122 return get_valid_dis386 (dp
, info
);
13126 get_sib (disassemble_info
*info
, int sizeflag
)
13128 /* If modrm.mod == 3, operand must be register. */
13130 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13134 FETCH_DATA (info
, codep
+ 2);
13135 sib
.index
= (codep
[1] >> 3) & 7;
13136 sib
.scale
= (codep
[1] >> 6) & 3;
13137 sib
.base
= codep
[1] & 7;
13142 print_insn (bfd_vma pc
, disassemble_info
*info
)
13144 const struct dis386
*dp
;
13146 char *op_txt
[MAX_OPERANDS
];
13148 int sizeflag
, orig_sizeflag
;
13150 struct dis_private priv
;
13153 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13154 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
13155 address_mode
= mode_32bit
;
13156 else if (info
->mach
== bfd_mach_i386_i8086
)
13158 address_mode
= mode_16bit
;
13159 priv
.orig_sizeflag
= 0;
13162 address_mode
= mode_64bit
;
13164 if (intel_syntax
== (char) -1)
13165 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
13167 for (p
= info
->disassembler_options
; p
!= NULL
; )
13169 if (CONST_STRNEQ (p
, "amd64"))
13171 else if (CONST_STRNEQ (p
, "intel64"))
13173 else if (CONST_STRNEQ (p
, "x86-64"))
13175 address_mode
= mode_64bit
;
13176 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13178 else if (CONST_STRNEQ (p
, "i386"))
13180 address_mode
= mode_32bit
;
13181 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13183 else if (CONST_STRNEQ (p
, "i8086"))
13185 address_mode
= mode_16bit
;
13186 priv
.orig_sizeflag
= 0;
13188 else if (CONST_STRNEQ (p
, "intel"))
13191 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
13192 intel_mnemonic
= 1;
13194 else if (CONST_STRNEQ (p
, "att"))
13197 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
13198 intel_mnemonic
= 0;
13200 else if (CONST_STRNEQ (p
, "addr"))
13202 if (address_mode
== mode_64bit
)
13204 if (p
[4] == '3' && p
[5] == '2')
13205 priv
.orig_sizeflag
&= ~AFLAG
;
13206 else if (p
[4] == '6' && p
[5] == '4')
13207 priv
.orig_sizeflag
|= AFLAG
;
13211 if (p
[4] == '1' && p
[5] == '6')
13212 priv
.orig_sizeflag
&= ~AFLAG
;
13213 else if (p
[4] == '3' && p
[5] == '2')
13214 priv
.orig_sizeflag
|= AFLAG
;
13217 else if (CONST_STRNEQ (p
, "data"))
13219 if (p
[4] == '1' && p
[5] == '6')
13220 priv
.orig_sizeflag
&= ~DFLAG
;
13221 else if (p
[4] == '3' && p
[5] == '2')
13222 priv
.orig_sizeflag
|= DFLAG
;
13224 else if (CONST_STRNEQ (p
, "suffix"))
13225 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
13227 p
= strchr (p
, ',');
13232 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
13234 (*info
->fprintf_func
) (info
->stream
,
13235 _("64-bit address is disabled"));
13241 names64
= intel_names64
;
13242 names32
= intel_names32
;
13243 names16
= intel_names16
;
13244 names8
= intel_names8
;
13245 names8rex
= intel_names8rex
;
13246 names_seg
= intel_names_seg
;
13247 names_mm
= intel_names_mm
;
13248 names_bnd
= intel_names_bnd
;
13249 names_xmm
= intel_names_xmm
;
13250 names_ymm
= intel_names_ymm
;
13251 names_zmm
= intel_names_zmm
;
13252 index64
= intel_index64
;
13253 index32
= intel_index32
;
13254 names_mask
= intel_names_mask
;
13255 index16
= intel_index16
;
13258 separator_char
= '+';
13263 names64
= att_names64
;
13264 names32
= att_names32
;
13265 names16
= att_names16
;
13266 names8
= att_names8
;
13267 names8rex
= att_names8rex
;
13268 names_seg
= att_names_seg
;
13269 names_mm
= att_names_mm
;
13270 names_bnd
= att_names_bnd
;
13271 names_xmm
= att_names_xmm
;
13272 names_ymm
= att_names_ymm
;
13273 names_zmm
= att_names_zmm
;
13274 index64
= att_index64
;
13275 index32
= att_index32
;
13276 names_mask
= att_names_mask
;
13277 index16
= att_index16
;
13280 separator_char
= ',';
13284 /* The output looks better if we put 7 bytes on a line, since that
13285 puts most long word instructions on a single line. Use 8 bytes
13287 if ((info
->mach
& bfd_mach_l1om
) != 0)
13288 info
->bytes_per_line
= 8;
13290 info
->bytes_per_line
= 7;
13292 info
->private_data
= &priv
;
13293 priv
.max_fetched
= priv
.the_buffer
;
13294 priv
.insn_start
= pc
;
13297 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13305 start_codep
= priv
.the_buffer
;
13306 codep
= priv
.the_buffer
;
13308 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
13312 /* Getting here means we tried for data but didn't get it. That
13313 means we have an incomplete instruction of some sort. Just
13314 print the first byte as a prefix or a .byte pseudo-op. */
13315 if (codep
> priv
.the_buffer
)
13317 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
13319 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
13322 /* Just print the first byte as a .byte instruction. */
13323 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
13324 (unsigned int) priv
.the_buffer
[0]);
13334 sizeflag
= priv
.orig_sizeflag
;
13336 if (!ckprefix () || rex_used
)
13338 /* Too many prefixes or unused REX prefixes. */
13340 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
13342 (*info
->fprintf_func
) (info
->stream
, "%s%s",
13344 prefix_name (all_prefixes
[i
], sizeflag
));
13348 insn_codep
= codep
;
13350 FETCH_DATA (info
, codep
+ 1);
13351 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
13353 if (((prefixes
& PREFIX_FWAIT
)
13354 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
13356 /* Handle prefixes before fwait. */
13357 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
13359 (*info
->fprintf_func
) (info
->stream
, "%s ",
13360 prefix_name (all_prefixes
[i
], sizeflag
));
13361 (*info
->fprintf_func
) (info
->stream
, "fwait");
13365 if (*codep
== 0x0f)
13367 unsigned char threebyte
;
13370 FETCH_DATA (info
, codep
+ 1);
13371 threebyte
= *codep
;
13372 dp
= &dis386_twobyte
[threebyte
];
13373 need_modrm
= twobyte_has_modrm
[*codep
];
13378 dp
= &dis386
[*codep
];
13379 need_modrm
= onebyte_has_modrm
[*codep
];
13383 /* Save sizeflag for printing the extra prefixes later before updating
13384 it for mnemonic and operand processing. The prefix names depend
13385 only on the address mode. */
13386 orig_sizeflag
= sizeflag
;
13387 if (prefixes
& PREFIX_ADDR
)
13389 if ((prefixes
& PREFIX_DATA
))
13395 FETCH_DATA (info
, codep
+ 1);
13396 modrm
.mod
= (*codep
>> 6) & 3;
13397 modrm
.reg
= (*codep
>> 3) & 7;
13398 modrm
.rm
= *codep
& 7;
13404 memset (&vex
, 0, sizeof (vex
));
13406 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
13408 get_sib (info
, sizeflag
);
13409 dofloat (sizeflag
);
13413 dp
= get_valid_dis386 (dp
, info
);
13414 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
13416 get_sib (info
, sizeflag
);
13417 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13420 op_ad
= MAX_OPERANDS
- 1 - i
;
13422 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
13423 /* For EVEX instruction after the last operand masking
13424 should be printed. */
13425 if (i
== 0 && vex
.evex
)
13427 /* Don't print {%k0}. */
13428 if (vex
.mask_register_specifier
)
13431 oappend (names_mask
[vex
.mask_register_specifier
]);
13441 /* Check if the REX prefix is used. */
13442 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
13443 all_prefixes
[last_rex_prefix
] = 0;
13445 /* Check if the SEG prefix is used. */
13446 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
13447 | PREFIX_FS
| PREFIX_GS
)) != 0
13448 && (used_prefixes
& active_seg_prefix
) != 0)
13449 all_prefixes
[last_seg_prefix
] = 0;
13451 /* Check if the ADDR prefix is used. */
13452 if ((prefixes
& PREFIX_ADDR
) != 0
13453 && (used_prefixes
& PREFIX_ADDR
) != 0)
13454 all_prefixes
[last_addr_prefix
] = 0;
13456 /* Check if the DATA prefix is used. */
13457 if ((prefixes
& PREFIX_DATA
) != 0
13458 && (used_prefixes
& PREFIX_DATA
) != 0)
13459 all_prefixes
[last_data_prefix
] = 0;
13461 /* Print the extra prefixes. */
13463 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
13464 if (all_prefixes
[i
])
13467 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
13470 prefix_length
+= strlen (name
) + 1;
13471 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
13474 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13475 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13476 used by putop and MMX/SSE operand and may be overriden by the
13477 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13479 if (dp
->prefix_requirement
== PREFIX_OPCODE
13480 && dp
!= &bad_opcode
13482 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
13484 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
13486 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
13488 && (used_prefixes
& PREFIX_DATA
) == 0))))
13490 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13491 return end_codep
- priv
.the_buffer
;
13494 /* Check maximum code length. */
13495 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
13497 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13498 return MAX_CODE_LENGTH
;
13501 obufp
= mnemonicendp
;
13502 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
13505 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
13507 /* The enter and bound instructions are printed with operands in the same
13508 order as the intel book; everything else is printed in reverse order. */
13509 if (intel_syntax
|| two_source_ops
)
13513 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13514 op_txt
[i
] = op_out
[i
];
13516 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
13517 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
13519 op_txt
[2] = op_out
[3];
13520 op_txt
[3] = op_out
[2];
13523 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
13525 op_ad
= op_index
[i
];
13526 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
13527 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
13528 riprel
= op_riprel
[i
];
13529 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
13530 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
13535 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13536 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
13540 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13544 (*info
->fprintf_func
) (info
->stream
, ",");
13545 if (op_index
[i
] != -1 && !op_riprel
[i
])
13546 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
13548 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
13552 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13553 if (op_index
[i
] != -1 && op_riprel
[i
])
13555 (*info
->fprintf_func
) (info
->stream
, " # ");
13556 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
13557 + op_address
[op_index
[i
]]), info
);
13560 return codep
- priv
.the_buffer
;
13563 static const char *float_mem
[] = {
13638 static const unsigned char float_mem_mode
[] = {
13713 #define ST { OP_ST, 0 }
13714 #define STi { OP_STi, 0 }
13716 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13717 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13718 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13719 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13720 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13721 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13722 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13723 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13724 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13726 static const struct dis386 float_reg
[][8] = {
13729 { "fadd", { ST
, STi
}, 0 },
13730 { "fmul", { ST
, STi
}, 0 },
13731 { "fcom", { STi
}, 0 },
13732 { "fcomp", { STi
}, 0 },
13733 { "fsub", { ST
, STi
}, 0 },
13734 { "fsubr", { ST
, STi
}, 0 },
13735 { "fdiv", { ST
, STi
}, 0 },
13736 { "fdivr", { ST
, STi
}, 0 },
13740 { "fld", { STi
}, 0 },
13741 { "fxch", { STi
}, 0 },
13751 { "fcmovb", { ST
, STi
}, 0 },
13752 { "fcmove", { ST
, STi
}, 0 },
13753 { "fcmovbe",{ ST
, STi
}, 0 },
13754 { "fcmovu", { ST
, STi
}, 0 },
13762 { "fcmovnb",{ ST
, STi
}, 0 },
13763 { "fcmovne",{ ST
, STi
}, 0 },
13764 { "fcmovnbe",{ ST
, STi
}, 0 },
13765 { "fcmovnu",{ ST
, STi
}, 0 },
13767 { "fucomi", { ST
, STi
}, 0 },
13768 { "fcomi", { ST
, STi
}, 0 },
13773 { "fadd", { STi
, ST
}, 0 },
13774 { "fmul", { STi
, ST
}, 0 },
13777 { "fsub{!M|r}", { STi
, ST
}, 0 },
13778 { "fsub{M|}", { STi
, ST
}, 0 },
13779 { "fdiv{!M|r}", { STi
, ST
}, 0 },
13780 { "fdiv{M|}", { STi
, ST
}, 0 },
13784 { "ffree", { STi
}, 0 },
13786 { "fst", { STi
}, 0 },
13787 { "fstp", { STi
}, 0 },
13788 { "fucom", { STi
}, 0 },
13789 { "fucomp", { STi
}, 0 },
13795 { "faddp", { STi
, ST
}, 0 },
13796 { "fmulp", { STi
, ST
}, 0 },
13799 { "fsub{!M|r}p", { STi
, ST
}, 0 },
13800 { "fsub{M|}p", { STi
, ST
}, 0 },
13801 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
13802 { "fdiv{M|}p", { STi
, ST
}, 0 },
13806 { "ffreep", { STi
}, 0 },
13811 { "fucomip", { ST
, STi
}, 0 },
13812 { "fcomip", { ST
, STi
}, 0 },
13817 static char *fgrps
[][8] = {
13820 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13825 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13830 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13835 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13840 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13845 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13850 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13855 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13856 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13861 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13866 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13871 swap_operand (void)
13873 mnemonicendp
[0] = '.';
13874 mnemonicendp
[1] = 's';
13879 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13880 int sizeflag ATTRIBUTE_UNUSED
)
13882 /* Skip mod/rm byte. */
13888 dofloat (int sizeflag
)
13890 const struct dis386
*dp
;
13891 unsigned char floatop
;
13893 floatop
= codep
[-1];
13895 if (modrm
.mod
!= 3)
13897 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13899 putop (float_mem
[fp_indx
], sizeflag
);
13902 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13905 /* Skip mod/rm byte. */
13909 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13910 if (dp
->name
== NULL
)
13912 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13914 /* Instruction fnstsw is only one with strange arg. */
13915 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13916 strcpy (op_out
[0], names16
[0]);
13920 putop (dp
->name
, sizeflag
);
13925 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13930 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
13934 /* Like oappend (below), but S is a string starting with '%'.
13935 In Intel syntax, the '%' is elided. */
13937 oappend_maybe_intel (const char *s
)
13939 oappend (s
+ intel_syntax
);
13943 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13945 oappend_maybe_intel ("%st");
13949 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13951 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
13952 oappend_maybe_intel (scratchbuf
);
13955 /* Capital letters in template are macros. */
13957 putop (const char *in_template
, int sizeflag
)
13962 unsigned int l
= 0, len
= 1;
13965 #define SAVE_LAST(c) \
13966 if (l < len && l < sizeof (last)) \
13971 for (p
= in_template
; *p
; p
++)
13987 while (*++p
!= '|')
13988 if (*p
== '}' || *p
== '\0')
13991 /* Fall through. */
13996 while (*++p
!= '}')
14007 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14011 if (l
== 0 && len
== 1)
14016 if (sizeflag
& SUFFIX_ALWAYS
)
14029 if (address_mode
== mode_64bit
14030 && !(prefixes
& PREFIX_ADDR
))
14041 if (intel_syntax
&& !alt
)
14043 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14045 if (sizeflag
& DFLAG
)
14046 *obufp
++ = intel_syntax
? 'd' : 'l';
14048 *obufp
++ = intel_syntax
? 'w' : 's';
14049 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14053 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14056 if (modrm
.mod
== 3)
14062 if (sizeflag
& DFLAG
)
14063 *obufp
++ = intel_syntax
? 'd' : 'l';
14066 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14072 case 'E': /* For jcxz/jecxz */
14073 if (address_mode
== mode_64bit
)
14075 if (sizeflag
& AFLAG
)
14081 if (sizeflag
& AFLAG
)
14083 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14088 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
14090 if (sizeflag
& AFLAG
)
14091 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
14093 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
14094 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14098 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
14100 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14104 if (!(rex
& REX_W
))
14105 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14110 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
14111 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
14113 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
14116 if (prefixes
& PREFIX_DS
)
14135 if (l
!= 0 || len
!= 1)
14137 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14142 if (!need_vex
|| !vex
.evex
)
14145 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14147 switch (vex
.length
)
14165 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
14170 /* Fall through. */
14173 if (l
!= 0 || len
!= 1)
14181 if (sizeflag
& SUFFIX_ALWAYS
)
14185 if (intel_mnemonic
!= cond
)
14189 if ((prefixes
& PREFIX_FWAIT
) == 0)
14192 used_prefixes
|= PREFIX_FWAIT
;
14198 else if (intel_syntax
&& (sizeflag
& DFLAG
))
14202 if (!(rex
& REX_W
))
14203 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14207 && address_mode
== mode_64bit
14208 && isa64
== intel64
)
14213 /* Fall through. */
14216 && address_mode
== mode_64bit
14217 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14222 /* Fall through. */
14225 if (l
== 0 && len
== 1)
14230 if ((rex
& REX_W
) == 0
14231 && (prefixes
& PREFIX_DATA
))
14233 if ((sizeflag
& DFLAG
) == 0)
14235 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14239 if ((prefixes
& PREFIX_DATA
)
14241 || (sizeflag
& SUFFIX_ALWAYS
))
14248 if (sizeflag
& DFLAG
)
14252 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14258 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14264 if ((prefixes
& PREFIX_DATA
)
14266 || (sizeflag
& SUFFIX_ALWAYS
))
14273 if (sizeflag
& DFLAG
)
14274 *obufp
++ = intel_syntax
? 'd' : 'l';
14277 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14285 if (address_mode
== mode_64bit
14286 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14288 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14292 /* Fall through. */
14295 if (l
== 0 && len
== 1)
14298 if (intel_syntax
&& !alt
)
14301 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14307 if (sizeflag
& DFLAG
)
14308 *obufp
++ = intel_syntax
? 'd' : 'l';
14311 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14317 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14323 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
14338 else if (sizeflag
& DFLAG
)
14347 if (intel_syntax
&& !p
[1]
14348 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
14350 if (!(rex
& REX_W
))
14351 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14354 if (l
== 0 && len
== 1)
14358 if (address_mode
== mode_64bit
14359 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14361 if (sizeflag
& SUFFIX_ALWAYS
)
14383 /* Fall through. */
14386 if (l
== 0 && len
== 1)
14391 if (sizeflag
& SUFFIX_ALWAYS
)
14397 if (sizeflag
& DFLAG
)
14401 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14415 if (address_mode
== mode_64bit
14416 && !(prefixes
& PREFIX_ADDR
))
14427 if (l
!= 0 || len
!= 1)
14432 if (need_vex
&& vex
.prefix
)
14434 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
14441 if (prefixes
& PREFIX_DATA
)
14445 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14449 if (l
== 0 && len
== 1)
14453 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14461 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14463 switch (vex
.length
)
14479 if (l
== 0 && len
== 1)
14481 /* operand size flag for cwtl, cbtw */
14490 else if (sizeflag
& DFLAG
)
14494 if (!(rex
& REX_W
))
14495 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14502 && last
[0] != 'L'))
14509 if (last
[0] == 'X')
14510 *obufp
++ = vex
.w
? 'd': 's';
14512 *obufp
++ = vex
.w
? 'q': 'd';
14518 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14520 if (sizeflag
& DFLAG
)
14524 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14530 if (address_mode
== mode_64bit
14531 && (isa64
== intel64
14532 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
14534 else if ((prefixes
& PREFIX_DATA
))
14536 if (!(sizeflag
& DFLAG
))
14538 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14545 mnemonicendp
= obufp
;
14550 oappend (const char *s
)
14552 obufp
= stpcpy (obufp
, s
);
14558 /* Only print the active segment register. */
14559 if (!active_seg_prefix
)
14562 used_prefixes
|= active_seg_prefix
;
14563 switch (active_seg_prefix
)
14566 oappend_maybe_intel ("%cs:");
14569 oappend_maybe_intel ("%ds:");
14572 oappend_maybe_intel ("%ss:");
14575 oappend_maybe_intel ("%es:");
14578 oappend_maybe_intel ("%fs:");
14581 oappend_maybe_intel ("%gs:");
14589 OP_indirE (int bytemode
, int sizeflag
)
14593 OP_E (bytemode
, sizeflag
);
14597 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
14599 if (address_mode
== mode_64bit
)
14607 sprintf_vma (tmp
, disp
);
14608 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
14609 strcpy (buf
+ 2, tmp
+ i
);
14613 bfd_signed_vma v
= disp
;
14620 /* Check for possible overflow on 0x8000000000000000. */
14623 strcpy (buf
, "9223372036854775808");
14637 tmp
[28 - i
] = (v
% 10) + '0';
14641 strcpy (buf
, tmp
+ 29 - i
);
14647 sprintf (buf
, "0x%x", (unsigned int) disp
);
14649 sprintf (buf
, "%d", (int) disp
);
14653 /* Put DISP in BUF as signed hex number. */
14656 print_displacement (char *buf
, bfd_vma disp
)
14658 bfd_signed_vma val
= disp
;
14667 /* Check for possible overflow. */
14670 switch (address_mode
)
14673 strcpy (buf
+ j
, "0x8000000000000000");
14676 strcpy (buf
+ j
, "0x80000000");
14679 strcpy (buf
+ j
, "0x8000");
14689 sprintf_vma (tmp
, (bfd_vma
) val
);
14690 for (i
= 0; tmp
[i
] == '0'; i
++)
14692 if (tmp
[i
] == '\0')
14694 strcpy (buf
+ j
, tmp
+ i
);
14698 intel_operand_size (int bytemode
, int sizeflag
)
14702 && (bytemode
== x_mode
14703 || bytemode
== evex_half_bcst_xmmq_mode
))
14706 oappend ("QWORD PTR ");
14708 oappend ("DWORD PTR ");
14717 oappend ("BYTE PTR ");
14722 oappend ("WORD PTR ");
14725 if (address_mode
== mode_64bit
&& isa64
== intel64
)
14727 oappend ("QWORD PTR ");
14730 /* Fall through. */
14732 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14734 oappend ("QWORD PTR ");
14737 /* Fall through. */
14743 oappend ("QWORD PTR ");
14746 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14747 oappend ("DWORD PTR ");
14749 oappend ("WORD PTR ");
14750 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14754 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14756 oappend ("WORD PTR ");
14757 if (!(rex
& REX_W
))
14758 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14761 if (sizeflag
& DFLAG
)
14762 oappend ("QWORD PTR ");
14764 oappend ("DWORD PTR ");
14765 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14768 case d_scalar_mode
:
14769 case d_scalar_swap_mode
:
14772 oappend ("DWORD PTR ");
14775 case q_scalar_mode
:
14776 case q_scalar_swap_mode
:
14778 oappend ("QWORD PTR ");
14781 if (address_mode
== mode_64bit
)
14782 oappend ("QWORD PTR ");
14784 oappend ("DWORD PTR ");
14787 if (sizeflag
& DFLAG
)
14788 oappend ("FWORD PTR ");
14790 oappend ("DWORD PTR ");
14791 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14794 oappend ("TBYTE PTR ");
14798 case evex_x_gscat_mode
:
14799 case evex_x_nobcst_mode
:
14800 case b_scalar_mode
:
14801 case w_scalar_mode
:
14804 switch (vex
.length
)
14807 oappend ("XMMWORD PTR ");
14810 oappend ("YMMWORD PTR ");
14813 oappend ("ZMMWORD PTR ");
14820 oappend ("XMMWORD PTR ");
14823 oappend ("XMMWORD PTR ");
14826 oappend ("YMMWORD PTR ");
14829 case evex_half_bcst_xmmq_mode
:
14833 switch (vex
.length
)
14836 oappend ("QWORD PTR ");
14839 oappend ("XMMWORD PTR ");
14842 oappend ("YMMWORD PTR ");
14852 switch (vex
.length
)
14857 oappend ("BYTE PTR ");
14867 switch (vex
.length
)
14872 oappend ("WORD PTR ");
14882 switch (vex
.length
)
14887 oappend ("DWORD PTR ");
14897 switch (vex
.length
)
14902 oappend ("QWORD PTR ");
14912 switch (vex
.length
)
14915 oappend ("WORD PTR ");
14918 oappend ("DWORD PTR ");
14921 oappend ("QWORD PTR ");
14931 switch (vex
.length
)
14934 oappend ("DWORD PTR ");
14937 oappend ("QWORD PTR ");
14940 oappend ("XMMWORD PTR ");
14950 switch (vex
.length
)
14953 oappend ("QWORD PTR ");
14956 oappend ("YMMWORD PTR ");
14959 oappend ("ZMMWORD PTR ");
14969 switch (vex
.length
)
14973 oappend ("XMMWORD PTR ");
14980 oappend ("OWORD PTR ");
14983 case vex_w_dq_mode
:
14984 case vex_scalar_w_dq_mode
:
14989 oappend ("QWORD PTR ");
14991 oappend ("DWORD PTR ");
14993 case vex_vsib_d_w_dq_mode
:
14994 case vex_vsib_q_w_dq_mode
:
15001 oappend ("QWORD PTR ");
15003 oappend ("DWORD PTR ");
15007 switch (vex
.length
)
15010 oappend ("XMMWORD PTR ");
15013 oappend ("YMMWORD PTR ");
15016 oappend ("ZMMWORD PTR ");
15023 case vex_vsib_q_w_d_mode
:
15024 case vex_vsib_d_w_d_mode
:
15025 if (!need_vex
|| !vex
.evex
)
15028 switch (vex
.length
)
15031 oappend ("QWORD PTR ");
15034 oappend ("XMMWORD PTR ");
15037 oappend ("YMMWORD PTR ");
15045 if (!need_vex
|| vex
.length
!= 128)
15048 oappend ("DWORD PTR ");
15050 oappend ("BYTE PTR ");
15056 oappend ("QWORD PTR ");
15058 oappend ("WORD PTR ");
15067 OP_E_register (int bytemode
, int sizeflag
)
15069 int reg
= modrm
.rm
;
15070 const char **names
;
15076 if ((sizeflag
& SUFFIX_ALWAYS
)
15077 && (bytemode
== b_swap_mode
15078 || bytemode
== bnd_swap_mode
15079 || bytemode
== v_swap_mode
))
15105 names
= address_mode
== mode_64bit
? names64
: names32
;
15108 case bnd_swap_mode
:
15117 if (address_mode
== mode_64bit
&& isa64
== intel64
)
15122 /* Fall through. */
15124 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15130 /* Fall through. */
15142 if ((sizeflag
& DFLAG
)
15143 || (bytemode
!= v_mode
15144 && bytemode
!= v_swap_mode
))
15148 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15152 names
= (address_mode
== mode_64bit
15153 ? names64
: names32
);
15154 if (!(prefixes
& PREFIX_ADDR
))
15155 names
= (address_mode
== mode_16bit
15156 ? names16
: names
);
15159 /* Remove "addr16/addr32". */
15160 all_prefixes
[last_addr_prefix
] = 0;
15161 names
= (address_mode
!= mode_32bit
15162 ? names32
: names16
);
15163 used_prefixes
|= PREFIX_ADDR
;
15173 names
= names_mask
;
15178 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15181 oappend (names
[reg
]);
15185 OP_E_memory (int bytemode
, int sizeflag
)
15188 int add
= (rex
& REX_B
) ? 8 : 0;
15194 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15196 && bytemode
!= x_mode
15197 && bytemode
!= xmmq_mode
15198 && bytemode
!= evex_half_bcst_xmmq_mode
)
15213 case vex_vsib_d_w_dq_mode
:
15214 case vex_vsib_d_w_d_mode
:
15215 case vex_vsib_q_w_dq_mode
:
15216 case vex_vsib_q_w_d_mode
:
15217 case evex_x_gscat_mode
:
15219 shift
= vex
.w
? 3 : 2;
15222 case evex_half_bcst_xmmq_mode
:
15226 shift
= vex
.w
? 3 : 2;
15229 /* Fall through. */
15233 case evex_x_nobcst_mode
:
15235 switch (vex
.length
)
15258 case q_scalar_mode
:
15260 case q_scalar_swap_mode
:
15266 case d_scalar_mode
:
15268 case d_scalar_swap_mode
:
15271 case w_scalar_mode
:
15275 case b_scalar_mode
:
15282 /* Make necessary corrections to shift for modes that need it.
15283 For these modes we currently have shift 4, 5 or 6 depending on
15284 vex.length (it corresponds to xmmword, ymmword or zmmword
15285 operand). We might want to make it 3, 4 or 5 (e.g. for
15286 xmmq_mode). In case of broadcast enabled the corrections
15287 aren't needed, as element size is always 32 or 64 bits. */
15289 && (bytemode
== xmmq_mode
15290 || bytemode
== evex_half_bcst_xmmq_mode
))
15292 else if (bytemode
== xmmqd_mode
)
15294 else if (bytemode
== xmmdw_mode
)
15296 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
15304 intel_operand_size (bytemode
, sizeflag
);
15307 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15309 /* 32/64 bit address mode */
15318 int addr32flag
= !((sizeflag
& AFLAG
)
15319 || bytemode
== v_bnd_mode
15320 || bytemode
== bnd_mode
15321 || bytemode
== bnd_swap_mode
);
15322 const char **indexes64
= names64
;
15323 const char **indexes32
= names32
;
15333 vindex
= sib
.index
;
15339 case vex_vsib_d_w_dq_mode
:
15340 case vex_vsib_d_w_d_mode
:
15341 case vex_vsib_q_w_dq_mode
:
15342 case vex_vsib_q_w_d_mode
:
15352 switch (vex
.length
)
15355 indexes64
= indexes32
= names_xmm
;
15359 || bytemode
== vex_vsib_q_w_dq_mode
15360 || bytemode
== vex_vsib_q_w_d_mode
)
15361 indexes64
= indexes32
= names_ymm
;
15363 indexes64
= indexes32
= names_xmm
;
15367 || bytemode
== vex_vsib_q_w_dq_mode
15368 || bytemode
== vex_vsib_q_w_d_mode
)
15369 indexes64
= indexes32
= names_zmm
;
15371 indexes64
= indexes32
= names_ymm
;
15378 haveindex
= vindex
!= 4;
15385 rbase
= base
+ add
;
15393 if (address_mode
== mode_64bit
&& !havesib
)
15399 FETCH_DATA (the_info
, codep
+ 1);
15401 if ((disp
& 0x80) != 0)
15403 if (vex
.evex
&& shift
> 0)
15411 /* In 32bit mode, we need index register to tell [offset] from
15412 [eiz*1 + offset]. */
15413 needindex
= (havesib
15416 && address_mode
== mode_32bit
);
15417 havedisp
= (havebase
15419 || (havesib
&& (haveindex
|| scale
!= 0)));
15422 if (modrm
.mod
!= 0 || base
== 5)
15424 if (havedisp
|| riprel
)
15425 print_displacement (scratchbuf
, disp
);
15427 print_operand_value (scratchbuf
, 1, disp
);
15428 oappend (scratchbuf
);
15432 oappend (!addr32flag
? "(%rip)" : "(%eip)");
15436 if ((havebase
|| haveindex
|| riprel
)
15437 && (bytemode
!= v_bnd_mode
)
15438 && (bytemode
!= bnd_mode
)
15439 && (bytemode
!= bnd_swap_mode
))
15440 used_prefixes
|= PREFIX_ADDR
;
15442 if (havedisp
|| (intel_syntax
&& riprel
))
15444 *obufp
++ = open_char
;
15445 if (intel_syntax
&& riprel
)
15448 oappend (!addr32flag
? "rip" : "eip");
15452 oappend (address_mode
== mode_64bit
&& !addr32flag
15453 ? names64
[rbase
] : names32
[rbase
]);
15456 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15457 print index to tell base + index from base. */
15461 || (havebase
&& base
!= ESP_REG_NUM
))
15463 if (!intel_syntax
|| havebase
)
15465 *obufp
++ = separator_char
;
15469 oappend (address_mode
== mode_64bit
&& !addr32flag
15470 ? indexes64
[vindex
] : indexes32
[vindex
]);
15472 oappend (address_mode
== mode_64bit
&& !addr32flag
15473 ? index64
: index32
);
15475 *obufp
++ = scale_char
;
15477 sprintf (scratchbuf
, "%d", 1 << scale
);
15478 oappend (scratchbuf
);
15482 && (disp
|| modrm
.mod
!= 0 || base
== 5))
15484 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
15489 else if (modrm
.mod
!= 1 && disp
!= -disp
)
15493 disp
= - (bfd_signed_vma
) disp
;
15497 print_displacement (scratchbuf
, disp
);
15499 print_operand_value (scratchbuf
, 1, disp
);
15500 oappend (scratchbuf
);
15503 *obufp
++ = close_char
;
15506 else if (intel_syntax
)
15508 if (modrm
.mod
!= 0 || base
== 5)
15510 if (!active_seg_prefix
)
15512 oappend (names_seg
[ds_reg
- es_reg
]);
15515 print_operand_value (scratchbuf
, 1, disp
);
15516 oappend (scratchbuf
);
15522 /* 16 bit address mode */
15523 used_prefixes
|= prefixes
& PREFIX_ADDR
;
15530 if ((disp
& 0x8000) != 0)
15535 FETCH_DATA (the_info
, codep
+ 1);
15537 if ((disp
& 0x80) != 0)
15539 if (vex
.evex
&& shift
> 0)
15544 if ((disp
& 0x8000) != 0)
15550 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
15552 print_displacement (scratchbuf
, disp
);
15553 oappend (scratchbuf
);
15556 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
15558 *obufp
++ = open_char
;
15560 oappend (index16
[modrm
.rm
]);
15562 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
15564 if ((bfd_signed_vma
) disp
>= 0)
15569 else if (modrm
.mod
!= 1)
15573 disp
= - (bfd_signed_vma
) disp
;
15576 print_displacement (scratchbuf
, disp
);
15577 oappend (scratchbuf
);
15580 *obufp
++ = close_char
;
15583 else if (intel_syntax
)
15585 if (!active_seg_prefix
)
15587 oappend (names_seg
[ds_reg
- es_reg
]);
15590 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
15591 oappend (scratchbuf
);
15594 if (vex
.evex
&& vex
.b
15595 && (bytemode
== x_mode
15596 || bytemode
== xmmq_mode
15597 || bytemode
== evex_half_bcst_xmmq_mode
))
15600 || bytemode
== xmmq_mode
15601 || bytemode
== evex_half_bcst_xmmq_mode
)
15603 switch (vex
.length
)
15606 oappend ("{1to2}");
15609 oappend ("{1to4}");
15612 oappend ("{1to8}");
15620 switch (vex
.length
)
15623 oappend ("{1to4}");
15626 oappend ("{1to8}");
15629 oappend ("{1to16}");
15639 OP_E (int bytemode
, int sizeflag
)
15641 /* Skip mod/rm byte. */
15645 if (modrm
.mod
== 3)
15646 OP_E_register (bytemode
, sizeflag
);
15648 OP_E_memory (bytemode
, sizeflag
);
15652 OP_G (int bytemode
, int sizeflag
)
15663 oappend (names8rex
[modrm
.reg
+ add
]);
15665 oappend (names8
[modrm
.reg
+ add
]);
15668 oappend (names16
[modrm
.reg
+ add
]);
15673 oappend (names32
[modrm
.reg
+ add
]);
15676 oappend (names64
[modrm
.reg
+ add
]);
15679 if (modrm
.reg
> 0x3)
15684 oappend (names_bnd
[modrm
.reg
]);
15693 oappend (names64
[modrm
.reg
+ add
]);
15696 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
15697 oappend (names32
[modrm
.reg
+ add
]);
15699 oappend (names16
[modrm
.reg
+ add
]);
15700 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15704 if (address_mode
== mode_64bit
)
15705 oappend (names64
[modrm
.reg
+ add
]);
15707 oappend (names32
[modrm
.reg
+ add
]);
15711 if ((modrm
.reg
+ add
) > 0x7)
15716 oappend (names_mask
[modrm
.reg
+ add
]);
15719 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15732 FETCH_DATA (the_info
, codep
+ 8);
15733 a
= *codep
++ & 0xff;
15734 a
|= (*codep
++ & 0xff) << 8;
15735 a
|= (*codep
++ & 0xff) << 16;
15736 a
|= (*codep
++ & 0xffu
) << 24;
15737 b
= *codep
++ & 0xff;
15738 b
|= (*codep
++ & 0xff) << 8;
15739 b
|= (*codep
++ & 0xff) << 16;
15740 b
|= (*codep
++ & 0xffu
) << 24;
15741 x
= a
+ ((bfd_vma
) b
<< 32);
15749 static bfd_signed_vma
15752 bfd_signed_vma x
= 0;
15754 FETCH_DATA (the_info
, codep
+ 4);
15755 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15756 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15757 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15758 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15762 static bfd_signed_vma
15765 bfd_signed_vma x
= 0;
15767 FETCH_DATA (the_info
, codep
+ 4);
15768 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15769 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15770 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15771 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15773 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15783 FETCH_DATA (the_info
, codep
+ 2);
15784 x
= *codep
++ & 0xff;
15785 x
|= (*codep
++ & 0xff) << 8;
15790 set_op (bfd_vma op
, int riprel
)
15792 op_index
[op_ad
] = op_ad
;
15793 if (address_mode
== mode_64bit
)
15795 op_address
[op_ad
] = op
;
15796 op_riprel
[op_ad
] = riprel
;
15800 /* Mask to get a 32-bit address. */
15801 op_address
[op_ad
] = op
& 0xffffffff;
15802 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15807 OP_REG (int code
, int sizeflag
)
15814 case es_reg
: case ss_reg
: case cs_reg
:
15815 case ds_reg
: case fs_reg
: case gs_reg
:
15816 oappend (names_seg
[code
- es_reg
]);
15828 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15829 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15830 s
= names16
[code
- ax_reg
+ add
];
15832 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15833 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15836 s
= names8rex
[code
- al_reg
+ add
];
15838 s
= names8
[code
- al_reg
];
15840 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15841 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15842 if (address_mode
== mode_64bit
15843 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15845 s
= names64
[code
- rAX_reg
+ add
];
15848 code
+= eAX_reg
- rAX_reg
;
15849 /* Fall through. */
15850 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15851 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15854 s
= names64
[code
- eAX_reg
+ add
];
15857 if (sizeflag
& DFLAG
)
15858 s
= names32
[code
- eAX_reg
+ add
];
15860 s
= names16
[code
- eAX_reg
+ add
];
15861 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15865 s
= INTERNAL_DISASSEMBLER_ERROR
;
15872 OP_IMREG (int code
, int sizeflag
)
15884 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15885 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15886 s
= names16
[code
- ax_reg
];
15888 case es_reg
: case ss_reg
: case cs_reg
:
15889 case ds_reg
: case fs_reg
: case gs_reg
:
15890 s
= names_seg
[code
- es_reg
];
15892 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15893 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15896 s
= names8rex
[code
- al_reg
];
15898 s
= names8
[code
- al_reg
];
15900 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15901 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15904 s
= names64
[code
- eAX_reg
];
15907 if (sizeflag
& DFLAG
)
15908 s
= names32
[code
- eAX_reg
];
15910 s
= names16
[code
- eAX_reg
];
15911 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15914 case z_mode_ax_reg
:
15915 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
15919 if (!(rex
& REX_W
))
15920 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15923 s
= INTERNAL_DISASSEMBLER_ERROR
;
15930 OP_I (int bytemode
, int sizeflag
)
15933 bfd_signed_vma mask
= -1;
15938 FETCH_DATA (the_info
, codep
+ 1);
15943 if (address_mode
== mode_64bit
)
15948 /* Fall through. */
15955 if (sizeflag
& DFLAG
)
15965 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15977 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15982 scratchbuf
[0] = '$';
15983 print_operand_value (scratchbuf
+ 1, 1, op
);
15984 oappend_maybe_intel (scratchbuf
);
15985 scratchbuf
[0] = '\0';
15989 OP_I64 (int bytemode
, int sizeflag
)
15992 bfd_signed_vma mask
= -1;
15994 if (address_mode
!= mode_64bit
)
15996 OP_I (bytemode
, sizeflag
);
16003 FETCH_DATA (the_info
, codep
+ 1);
16013 if (sizeflag
& DFLAG
)
16023 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16031 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16036 scratchbuf
[0] = '$';
16037 print_operand_value (scratchbuf
+ 1, 1, op
);
16038 oappend_maybe_intel (scratchbuf
);
16039 scratchbuf
[0] = '\0';
16043 OP_sI (int bytemode
, int sizeflag
)
16051 FETCH_DATA (the_info
, codep
+ 1);
16053 if ((op
& 0x80) != 0)
16055 if (bytemode
== b_T_mode
)
16057 if (address_mode
!= mode_64bit
16058 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
16060 /* The operand-size prefix is overridden by a REX prefix. */
16061 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16069 if (!(rex
& REX_W
))
16071 if (sizeflag
& DFLAG
)
16079 /* The operand-size prefix is overridden by a REX prefix. */
16080 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16086 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16090 scratchbuf
[0] = '$';
16091 print_operand_value (scratchbuf
+ 1, 1, op
);
16092 oappend_maybe_intel (scratchbuf
);
16096 OP_J (int bytemode
, int sizeflag
)
16100 bfd_vma segment
= 0;
16105 FETCH_DATA (the_info
, codep
+ 1);
16107 if ((disp
& 0x80) != 0)
16111 if (isa64
== amd64
)
16113 if ((sizeflag
& DFLAG
)
16114 || (address_mode
== mode_64bit
16115 && (isa64
!= amd64
|| (rex
& REX_W
))))
16120 if ((disp
& 0x8000) != 0)
16122 /* In 16bit mode, address is wrapped around at 64k within
16123 the same segment. Otherwise, a data16 prefix on a jump
16124 instruction means that the pc is masked to 16 bits after
16125 the displacement is added! */
16127 if ((prefixes
& PREFIX_DATA
) == 0)
16128 segment
= ((start_pc
+ (codep
- start_codep
))
16129 & ~((bfd_vma
) 0xffff));
16131 if (address_mode
!= mode_64bit
16132 || (isa64
== amd64
&& !(rex
& REX_W
)))
16133 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16136 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16139 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
16141 print_operand_value (scratchbuf
, 1, disp
);
16142 oappend (scratchbuf
);
16146 OP_SEG (int bytemode
, int sizeflag
)
16148 if (bytemode
== w_mode
)
16149 oappend (names_seg
[modrm
.reg
]);
16151 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
16155 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
16159 if (sizeflag
& DFLAG
)
16169 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16171 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
16173 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
16174 oappend (scratchbuf
);
16178 OP_OFF (int bytemode
, int sizeflag
)
16182 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16183 intel_operand_size (bytemode
, sizeflag
);
16186 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16193 if (!active_seg_prefix
)
16195 oappend (names_seg
[ds_reg
- es_reg
]);
16199 print_operand_value (scratchbuf
, 1, off
);
16200 oappend (scratchbuf
);
16204 OP_OFF64 (int bytemode
, int sizeflag
)
16208 if (address_mode
!= mode_64bit
16209 || (prefixes
& PREFIX_ADDR
))
16211 OP_OFF (bytemode
, sizeflag
);
16215 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16216 intel_operand_size (bytemode
, sizeflag
);
16223 if (!active_seg_prefix
)
16225 oappend (names_seg
[ds_reg
- es_reg
]);
16229 print_operand_value (scratchbuf
, 1, off
);
16230 oappend (scratchbuf
);
16234 ptr_reg (int code
, int sizeflag
)
16238 *obufp
++ = open_char
;
16239 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
16240 if (address_mode
== mode_64bit
)
16242 if (!(sizeflag
& AFLAG
))
16243 s
= names32
[code
- eAX_reg
];
16245 s
= names64
[code
- eAX_reg
];
16247 else if (sizeflag
& AFLAG
)
16248 s
= names32
[code
- eAX_reg
];
16250 s
= names16
[code
- eAX_reg
];
16252 *obufp
++ = close_char
;
16257 OP_ESreg (int code
, int sizeflag
)
16263 case 0x6d: /* insw/insl */
16264 intel_operand_size (z_mode
, sizeflag
);
16266 case 0xa5: /* movsw/movsl/movsq */
16267 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16268 case 0xab: /* stosw/stosl */
16269 case 0xaf: /* scasw/scasl */
16270 intel_operand_size (v_mode
, sizeflag
);
16273 intel_operand_size (b_mode
, sizeflag
);
16276 oappend_maybe_intel ("%es:");
16277 ptr_reg (code
, sizeflag
);
16281 OP_DSreg (int code
, int sizeflag
)
16287 case 0x6f: /* outsw/outsl */
16288 intel_operand_size (z_mode
, sizeflag
);
16290 case 0xa5: /* movsw/movsl/movsq */
16291 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16292 case 0xad: /* lodsw/lodsl/lodsq */
16293 intel_operand_size (v_mode
, sizeflag
);
16296 intel_operand_size (b_mode
, sizeflag
);
16299 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16300 default segment register DS is printed. */
16301 if (!active_seg_prefix
)
16302 active_seg_prefix
= PREFIX_DS
;
16304 ptr_reg (code
, sizeflag
);
16308 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16316 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
16318 all_prefixes
[last_lock_prefix
] = 0;
16319 used_prefixes
|= PREFIX_LOCK
;
16324 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
16325 oappend_maybe_intel (scratchbuf
);
16329 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16338 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
16340 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
16341 oappend (scratchbuf
);
16345 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16347 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
16348 oappend_maybe_intel (scratchbuf
);
16352 OP_R (int bytemode
, int sizeflag
)
16354 /* Skip mod/rm byte. */
16357 OP_E_register (bytemode
, sizeflag
);
16361 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16363 int reg
= modrm
.reg
;
16364 const char **names
;
16366 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16367 if (prefixes
& PREFIX_DATA
)
16376 oappend (names
[reg
]);
16380 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16382 int reg
= modrm
.reg
;
16383 const char **names
;
16395 && bytemode
!= xmm_mode
16396 && bytemode
!= xmmq_mode
16397 && bytemode
!= evex_half_bcst_xmmq_mode
16398 && bytemode
!= ymm_mode
16399 && bytemode
!= scalar_mode
)
16401 switch (vex
.length
)
16408 || (bytemode
!= vex_vsib_q_w_dq_mode
16409 && bytemode
!= vex_vsib_q_w_d_mode
))
16421 else if (bytemode
== xmmq_mode
16422 || bytemode
== evex_half_bcst_xmmq_mode
)
16424 switch (vex
.length
)
16437 else if (bytemode
== ymm_mode
)
16441 oappend (names
[reg
]);
16445 OP_EM (int bytemode
, int sizeflag
)
16448 const char **names
;
16450 if (modrm
.mod
!= 3)
16453 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16455 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16456 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16458 OP_E (bytemode
, sizeflag
);
16462 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
16465 /* Skip mod/rm byte. */
16468 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16470 if (prefixes
& PREFIX_DATA
)
16479 oappend (names
[reg
]);
16482 /* cvt* are the only instructions in sse2 which have
16483 both SSE and MMX operands and also have 0x66 prefix
16484 in their opcode. 0x66 was originally used to differentiate
16485 between SSE and MMX instruction(operands). So we have to handle the
16486 cvt* separately using OP_EMC and OP_MXC */
16488 OP_EMC (int bytemode
, int sizeflag
)
16490 if (modrm
.mod
!= 3)
16492 if (intel_syntax
&& bytemode
== v_mode
)
16494 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16495 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16497 OP_E (bytemode
, sizeflag
);
16501 /* Skip mod/rm byte. */
16504 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16505 oappend (names_mm
[modrm
.rm
]);
16509 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16511 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16512 oappend (names_mm
[modrm
.reg
]);
16516 OP_EX (int bytemode
, int sizeflag
)
16519 const char **names
;
16521 /* Skip mod/rm byte. */
16525 if (modrm
.mod
!= 3)
16527 OP_E_memory (bytemode
, sizeflag
);
16542 if ((sizeflag
& SUFFIX_ALWAYS
)
16543 && (bytemode
== x_swap_mode
16544 || bytemode
== d_swap_mode
16545 || bytemode
== d_scalar_swap_mode
16546 || bytemode
== q_swap_mode
16547 || bytemode
== q_scalar_swap_mode
))
16551 && bytemode
!= xmm_mode
16552 && bytemode
!= xmmdw_mode
16553 && bytemode
!= xmmqd_mode
16554 && bytemode
!= xmm_mb_mode
16555 && bytemode
!= xmm_mw_mode
16556 && bytemode
!= xmm_md_mode
16557 && bytemode
!= xmm_mq_mode
16558 && bytemode
!= xmm_mdq_mode
16559 && bytemode
!= xmmq_mode
16560 && bytemode
!= evex_half_bcst_xmmq_mode
16561 && bytemode
!= ymm_mode
16562 && bytemode
!= d_scalar_mode
16563 && bytemode
!= d_scalar_swap_mode
16564 && bytemode
!= q_scalar_mode
16565 && bytemode
!= q_scalar_swap_mode
16566 && bytemode
!= vex_scalar_w_dq_mode
)
16568 switch (vex
.length
)
16583 else if (bytemode
== xmmq_mode
16584 || bytemode
== evex_half_bcst_xmmq_mode
)
16586 switch (vex
.length
)
16599 else if (bytemode
== ymm_mode
)
16603 oappend (names
[reg
]);
16607 OP_MS (int bytemode
, int sizeflag
)
16609 if (modrm
.mod
== 3)
16610 OP_EM (bytemode
, sizeflag
);
16616 OP_XS (int bytemode
, int sizeflag
)
16618 if (modrm
.mod
== 3)
16619 OP_EX (bytemode
, sizeflag
);
16625 OP_M (int bytemode
, int sizeflag
)
16627 if (modrm
.mod
== 3)
16628 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16631 OP_E (bytemode
, sizeflag
);
16635 OP_0f07 (int bytemode
, int sizeflag
)
16637 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
16640 OP_E (bytemode
, sizeflag
);
16643 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16644 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16647 NOP_Fixup1 (int bytemode
, int sizeflag
)
16649 if ((prefixes
& PREFIX_DATA
) != 0
16652 && address_mode
== mode_64bit
))
16653 OP_REG (bytemode
, sizeflag
);
16655 strcpy (obuf
, "nop");
16659 NOP_Fixup2 (int bytemode
, int sizeflag
)
16661 if ((prefixes
& PREFIX_DATA
) != 0
16664 && address_mode
== mode_64bit
))
16665 OP_IMREG (bytemode
, sizeflag
);
16668 static const char *const Suffix3DNow
[] = {
16669 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16670 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16671 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16672 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16673 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16674 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16675 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16676 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16677 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16678 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16679 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16680 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16681 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16682 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16683 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16684 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16685 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16686 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16687 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16688 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16689 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16690 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16691 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16692 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16693 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16694 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16695 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16696 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16697 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16698 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16699 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16700 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16701 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16702 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16703 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16704 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16705 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16706 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16707 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16708 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16709 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16710 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16711 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16712 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16713 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16714 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16715 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16716 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16717 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16718 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16719 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16720 /* CC */ NULL
, NULL
, NULL
, NULL
,
16721 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16722 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16723 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16724 /* DC */ NULL
, NULL
, NULL
, NULL
,
16725 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16726 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16727 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16728 /* EC */ NULL
, NULL
, NULL
, NULL
,
16729 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16730 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16731 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16732 /* FC */ NULL
, NULL
, NULL
, NULL
,
16736 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16738 const char *mnemonic
;
16740 FETCH_DATA (the_info
, codep
+ 1);
16741 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16742 place where an 8-bit immediate would normally go. ie. the last
16743 byte of the instruction. */
16744 obufp
= mnemonicendp
;
16745 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16747 oappend (mnemonic
);
16750 /* Since a variable sized modrm/sib chunk is between the start
16751 of the opcode (0x0f0f) and the opcode suffix, we need to do
16752 all the modrm processing first, and don't know until now that
16753 we have a bad opcode. This necessitates some cleaning up. */
16754 op_out
[0][0] = '\0';
16755 op_out
[1][0] = '\0';
16758 mnemonicendp
= obufp
;
16761 static struct op simd_cmp_op
[] =
16763 { STRING_COMMA_LEN ("eq") },
16764 { STRING_COMMA_LEN ("lt") },
16765 { STRING_COMMA_LEN ("le") },
16766 { STRING_COMMA_LEN ("unord") },
16767 { STRING_COMMA_LEN ("neq") },
16768 { STRING_COMMA_LEN ("nlt") },
16769 { STRING_COMMA_LEN ("nle") },
16770 { STRING_COMMA_LEN ("ord") }
16774 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16776 unsigned int cmp_type
;
16778 FETCH_DATA (the_info
, codep
+ 1);
16779 cmp_type
= *codep
++ & 0xff;
16780 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16783 char *p
= mnemonicendp
- 2;
16787 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16788 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16792 /* We have a reserved extension byte. Output it directly. */
16793 scratchbuf
[0] = '$';
16794 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16795 oappend_maybe_intel (scratchbuf
);
16796 scratchbuf
[0] = '\0';
16801 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
16802 int sizeflag ATTRIBUTE_UNUSED
)
16804 /* mwaitx %eax,%ecx,%ebx */
16807 const char **names
= (address_mode
== mode_64bit
16808 ? names64
: names32
);
16809 strcpy (op_out
[0], names
[0]);
16810 strcpy (op_out
[1], names
[1]);
16811 strcpy (op_out
[2], names
[3]);
16812 two_source_ops
= 1;
16814 /* Skip mod/rm byte. */
16820 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
16821 int sizeflag ATTRIBUTE_UNUSED
)
16823 /* mwait %eax,%ecx */
16826 const char **names
= (address_mode
== mode_64bit
16827 ? names64
: names32
);
16828 strcpy (op_out
[0], names
[0]);
16829 strcpy (op_out
[1], names
[1]);
16830 two_source_ops
= 1;
16832 /* Skip mod/rm byte. */
16838 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16839 int sizeflag ATTRIBUTE_UNUSED
)
16841 /* monitor %eax,%ecx,%edx" */
16844 const char **op1_names
;
16845 const char **names
= (address_mode
== mode_64bit
16846 ? names64
: names32
);
16848 if (!(prefixes
& PREFIX_ADDR
))
16849 op1_names
= (address_mode
== mode_16bit
16850 ? names16
: names
);
16853 /* Remove "addr16/addr32". */
16854 all_prefixes
[last_addr_prefix
] = 0;
16855 op1_names
= (address_mode
!= mode_32bit
16856 ? names32
: names16
);
16857 used_prefixes
|= PREFIX_ADDR
;
16859 strcpy (op_out
[0], op1_names
[0]);
16860 strcpy (op_out
[1], names
[1]);
16861 strcpy (op_out
[2], names
[2]);
16862 two_source_ops
= 1;
16864 /* Skip mod/rm byte. */
16872 /* Throw away prefixes and 1st. opcode byte. */
16873 codep
= insn_codep
+ 1;
16878 REP_Fixup (int bytemode
, int sizeflag
)
16880 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16882 if (prefixes
& PREFIX_REPZ
)
16883 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16890 OP_IMREG (bytemode
, sizeflag
);
16893 OP_ESreg (bytemode
, sizeflag
);
16896 OP_DSreg (bytemode
, sizeflag
);
16904 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16908 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16910 if (prefixes
& PREFIX_REPNZ
)
16911 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16914 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16918 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16919 int sizeflag ATTRIBUTE_UNUSED
)
16921 if (active_seg_prefix
== PREFIX_DS
16922 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
16924 /* NOTRACK prefix is only valid on indirect branch instructions.
16925 NB: DATA prefix is unsupported for Intel64. */
16926 active_seg_prefix
= 0;
16927 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
16931 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16932 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16936 HLE_Fixup1 (int bytemode
, int sizeflag
)
16939 && (prefixes
& PREFIX_LOCK
) != 0)
16941 if (prefixes
& PREFIX_REPZ
)
16942 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16943 if (prefixes
& PREFIX_REPNZ
)
16944 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16947 OP_E (bytemode
, sizeflag
);
16950 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16951 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16955 HLE_Fixup2 (int bytemode
, int sizeflag
)
16957 if (modrm
.mod
!= 3)
16959 if (prefixes
& PREFIX_REPZ
)
16960 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16961 if (prefixes
& PREFIX_REPNZ
)
16962 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16965 OP_E (bytemode
, sizeflag
);
16968 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16969 "xrelease" for memory operand. No check for LOCK prefix. */
16972 HLE_Fixup3 (int bytemode
, int sizeflag
)
16975 && last_repz_prefix
> last_repnz_prefix
16976 && (prefixes
& PREFIX_REPZ
) != 0)
16977 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16979 OP_E (bytemode
, sizeflag
);
16983 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
16988 /* Change cmpxchg8b to cmpxchg16b. */
16989 char *p
= mnemonicendp
- 2;
16990 mnemonicendp
= stpcpy (p
, "16b");
16993 else if ((prefixes
& PREFIX_LOCK
) != 0)
16995 if (prefixes
& PREFIX_REPZ
)
16996 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16997 if (prefixes
& PREFIX_REPNZ
)
16998 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
17001 OP_M (bytemode
, sizeflag
);
17005 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
17007 const char **names
;
17011 switch (vex
.length
)
17025 oappend (names
[reg
]);
17029 CRC32_Fixup (int bytemode
, int sizeflag
)
17031 /* Add proper suffix to "crc32". */
17032 char *p
= mnemonicendp
;
17051 if (sizeflag
& DFLAG
)
17055 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17059 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17066 if (modrm
.mod
== 3)
17070 /* Skip mod/rm byte. */
17075 add
= (rex
& REX_B
) ? 8 : 0;
17076 if (bytemode
== b_mode
)
17080 oappend (names8rex
[modrm
.rm
+ add
]);
17082 oappend (names8
[modrm
.rm
+ add
]);
17088 oappend (names64
[modrm
.rm
+ add
]);
17089 else if ((prefixes
& PREFIX_DATA
))
17090 oappend (names16
[modrm
.rm
+ add
]);
17092 oappend (names32
[modrm
.rm
+ add
]);
17096 OP_E (bytemode
, sizeflag
);
17100 FXSAVE_Fixup (int bytemode
, int sizeflag
)
17102 /* Add proper suffix to "fxsave" and "fxrstor". */
17106 char *p
= mnemonicendp
;
17112 OP_M (bytemode
, sizeflag
);
17116 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
17118 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
17121 char *p
= mnemonicendp
;
17126 else if (sizeflag
& SUFFIX_ALWAYS
)
17133 OP_EX (bytemode
, sizeflag
);
17136 /* Display the destination register operand for instructions with
17140 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17143 const char **names
;
17151 reg
= vex
.register_specifier
;
17152 if (address_mode
!= mode_64bit
)
17154 else if (vex
.evex
&& !vex
.v
)
17157 if (bytemode
== vex_scalar_mode
)
17159 oappend (names_xmm
[reg
]);
17163 switch (vex
.length
)
17170 case vex_vsib_q_w_dq_mode
:
17171 case vex_vsib_q_w_d_mode
:
17187 names
= names_mask
;
17201 case vex_vsib_q_w_dq_mode
:
17202 case vex_vsib_q_w_d_mode
:
17203 names
= vex
.w
? names_ymm
: names_xmm
;
17212 names
= names_mask
;
17215 /* See PR binutils/20893 for a reproducer. */
17227 oappend (names
[reg
]);
17230 /* Get the VEX immediate byte without moving codep. */
17232 static unsigned char
17233 get_vex_imm8 (int sizeflag
, int opnum
)
17235 int bytes_before_imm
= 0;
17237 if (modrm
.mod
!= 3)
17239 /* There are SIB/displacement bytes. */
17240 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
17242 /* 32/64 bit address mode */
17243 int base
= modrm
.rm
;
17245 /* Check SIB byte. */
17248 FETCH_DATA (the_info
, codep
+ 1);
17250 /* When decoding the third source, don't increase
17251 bytes_before_imm as this has already been incremented
17252 by one in OP_E_memory while decoding the second
17255 bytes_before_imm
++;
17258 /* Don't increase bytes_before_imm when decoding the third source,
17259 it has already been incremented by OP_E_memory while decoding
17260 the second source operand. */
17266 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17267 SIB == 5, there is a 4 byte displacement. */
17269 /* No displacement. */
17271 /* Fall through. */
17273 /* 4 byte displacement. */
17274 bytes_before_imm
+= 4;
17277 /* 1 byte displacement. */
17278 bytes_before_imm
++;
17285 /* 16 bit address mode */
17286 /* Don't increase bytes_before_imm when decoding the third source,
17287 it has already been incremented by OP_E_memory while decoding
17288 the second source operand. */
17294 /* When modrm.rm == 6, there is a 2 byte displacement. */
17296 /* No displacement. */
17298 /* Fall through. */
17300 /* 2 byte displacement. */
17301 bytes_before_imm
+= 2;
17304 /* 1 byte displacement: when decoding the third source,
17305 don't increase bytes_before_imm as this has already
17306 been incremented by one in OP_E_memory while decoding
17307 the second source operand. */
17309 bytes_before_imm
++;
17317 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
17318 return codep
[bytes_before_imm
];
17322 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
17324 const char **names
;
17326 if (reg
== -1 && modrm
.mod
!= 3)
17328 OP_E_memory (bytemode
, sizeflag
);
17340 if (address_mode
!= mode_64bit
)
17344 switch (vex
.length
)
17355 oappend (names
[reg
]);
17359 OP_EX_VexImmW (int bytemode
, int sizeflag
)
17362 static unsigned char vex_imm8
;
17364 if (vex_w_done
== 0)
17368 /* Skip mod/rm byte. */
17372 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
17375 reg
= vex_imm8
>> 4;
17377 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17379 else if (vex_w_done
== 1)
17384 reg
= vex_imm8
>> 4;
17386 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17390 /* Output the imm8 directly. */
17391 scratchbuf
[0] = '$';
17392 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
17393 oappend_maybe_intel (scratchbuf
);
17394 scratchbuf
[0] = '\0';
17400 OP_Vex_2src (int bytemode
, int sizeflag
)
17402 if (modrm
.mod
== 3)
17404 int reg
= modrm
.rm
;
17408 oappend (names_xmm
[reg
]);
17413 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
17415 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
17416 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17418 OP_E (bytemode
, sizeflag
);
17423 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
17425 if (modrm
.mod
== 3)
17427 /* Skip mod/rm byte. */
17434 unsigned int reg
= vex
.register_specifier
;
17436 if (address_mode
!= mode_64bit
)
17438 oappend (names_xmm
[reg
]);
17441 OP_Vex_2src (bytemode
, sizeflag
);
17445 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
17448 OP_Vex_2src (bytemode
, sizeflag
);
17451 unsigned int reg
= vex
.register_specifier
;
17453 if (address_mode
!= mode_64bit
)
17455 oappend (names_xmm
[reg
]);
17460 OP_EX_VexW (int bytemode
, int sizeflag
)
17466 /* Skip mod/rm byte. */
17471 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
17476 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
17479 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17487 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17490 const char **names
;
17492 FETCH_DATA (the_info
, codep
+ 1);
17495 if (bytemode
!= x_mode
)
17499 if (address_mode
!= mode_64bit
)
17502 switch (vex
.length
)
17513 oappend (names
[reg
]);
17517 OP_XMM_VexW (int bytemode
, int sizeflag
)
17519 /* Turn off the REX.W bit since it is used for swapping operands
17522 OP_XMM (bytemode
, sizeflag
);
17526 OP_EX_Vex (int bytemode
, int sizeflag
)
17528 if (modrm
.mod
!= 3)
17530 if (vex
.register_specifier
!= 0)
17534 OP_EX (bytemode
, sizeflag
);
17538 OP_XMM_Vex (int bytemode
, int sizeflag
)
17540 if (modrm
.mod
!= 3)
17542 if (vex
.register_specifier
!= 0)
17546 OP_XMM (bytemode
, sizeflag
);
17550 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17552 switch (vex
.length
)
17555 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
17558 mnemonicendp
= stpcpy (obuf
, "vzeroall");
17565 static struct op vex_cmp_op
[] =
17567 { STRING_COMMA_LEN ("eq") },
17568 { STRING_COMMA_LEN ("lt") },
17569 { STRING_COMMA_LEN ("le") },
17570 { STRING_COMMA_LEN ("unord") },
17571 { STRING_COMMA_LEN ("neq") },
17572 { STRING_COMMA_LEN ("nlt") },
17573 { STRING_COMMA_LEN ("nle") },
17574 { STRING_COMMA_LEN ("ord") },
17575 { STRING_COMMA_LEN ("eq_uq") },
17576 { STRING_COMMA_LEN ("nge") },
17577 { STRING_COMMA_LEN ("ngt") },
17578 { STRING_COMMA_LEN ("false") },
17579 { STRING_COMMA_LEN ("neq_oq") },
17580 { STRING_COMMA_LEN ("ge") },
17581 { STRING_COMMA_LEN ("gt") },
17582 { STRING_COMMA_LEN ("true") },
17583 { STRING_COMMA_LEN ("eq_os") },
17584 { STRING_COMMA_LEN ("lt_oq") },
17585 { STRING_COMMA_LEN ("le_oq") },
17586 { STRING_COMMA_LEN ("unord_s") },
17587 { STRING_COMMA_LEN ("neq_us") },
17588 { STRING_COMMA_LEN ("nlt_uq") },
17589 { STRING_COMMA_LEN ("nle_uq") },
17590 { STRING_COMMA_LEN ("ord_s") },
17591 { STRING_COMMA_LEN ("eq_us") },
17592 { STRING_COMMA_LEN ("nge_uq") },
17593 { STRING_COMMA_LEN ("ngt_uq") },
17594 { STRING_COMMA_LEN ("false_os") },
17595 { STRING_COMMA_LEN ("neq_os") },
17596 { STRING_COMMA_LEN ("ge_oq") },
17597 { STRING_COMMA_LEN ("gt_oq") },
17598 { STRING_COMMA_LEN ("true_us") },
17602 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17604 unsigned int cmp_type
;
17606 FETCH_DATA (the_info
, codep
+ 1);
17607 cmp_type
= *codep
++ & 0xff;
17608 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
17611 char *p
= mnemonicendp
- 2;
17615 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
17616 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
17620 /* We have a reserved extension byte. Output it directly. */
17621 scratchbuf
[0] = '$';
17622 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17623 oappend_maybe_intel (scratchbuf
);
17624 scratchbuf
[0] = '\0';
17629 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17630 int sizeflag ATTRIBUTE_UNUSED
)
17632 unsigned int cmp_type
;
17637 FETCH_DATA (the_info
, codep
+ 1);
17638 cmp_type
= *codep
++ & 0xff;
17639 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17640 If it's the case, print suffix, otherwise - print the immediate. */
17641 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
17646 char *p
= mnemonicendp
- 2;
17648 /* vpcmp* can have both one- and two-lettered suffix. */
17662 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
17663 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
17667 /* We have a reserved extension byte. Output it directly. */
17668 scratchbuf
[0] = '$';
17669 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17670 oappend_maybe_intel (scratchbuf
);
17671 scratchbuf
[0] = '\0';
17675 static const struct op xop_cmp_op
[] =
17677 { STRING_COMMA_LEN ("lt") },
17678 { STRING_COMMA_LEN ("le") },
17679 { STRING_COMMA_LEN ("gt") },
17680 { STRING_COMMA_LEN ("ge") },
17681 { STRING_COMMA_LEN ("eq") },
17682 { STRING_COMMA_LEN ("neq") },
17683 { STRING_COMMA_LEN ("false") },
17684 { STRING_COMMA_LEN ("true") }
17688 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17689 int sizeflag ATTRIBUTE_UNUSED
)
17691 unsigned int cmp_type
;
17693 FETCH_DATA (the_info
, codep
+ 1);
17694 cmp_type
= *codep
++ & 0xff;
17695 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
17698 char *p
= mnemonicendp
- 2;
17700 /* vpcom* can have both one- and two-lettered suffix. */
17714 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
17715 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
17719 /* We have a reserved extension byte. Output it directly. */
17720 scratchbuf
[0] = '$';
17721 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17722 oappend_maybe_intel (scratchbuf
);
17723 scratchbuf
[0] = '\0';
17727 static const struct op pclmul_op
[] =
17729 { STRING_COMMA_LEN ("lql") },
17730 { STRING_COMMA_LEN ("hql") },
17731 { STRING_COMMA_LEN ("lqh") },
17732 { STRING_COMMA_LEN ("hqh") }
17736 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17737 int sizeflag ATTRIBUTE_UNUSED
)
17739 unsigned int pclmul_type
;
17741 FETCH_DATA (the_info
, codep
+ 1);
17742 pclmul_type
= *codep
++ & 0xff;
17743 switch (pclmul_type
)
17754 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
17757 char *p
= mnemonicendp
- 3;
17762 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
17763 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
17767 /* We have a reserved extension byte. Output it directly. */
17768 scratchbuf
[0] = '$';
17769 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
17770 oappend_maybe_intel (scratchbuf
);
17771 scratchbuf
[0] = '\0';
17776 MOVBE_Fixup (int bytemode
, int sizeflag
)
17778 /* Add proper suffix to "movbe". */
17779 char *p
= mnemonicendp
;
17788 if (sizeflag
& SUFFIX_ALWAYS
)
17794 if (sizeflag
& DFLAG
)
17798 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17803 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17810 OP_M (bytemode
, sizeflag
);
17814 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17817 const char **names
;
17819 /* Skip mod/rm byte. */
17833 oappend (names
[reg
]);
17837 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17839 const char **names
;
17840 unsigned int reg
= vex
.register_specifier
;
17847 if (address_mode
!= mode_64bit
)
17849 oappend (names
[reg
]);
17853 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17856 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
17860 if ((rex
& REX_R
) != 0 || !vex
.r
)
17866 oappend (names_mask
[modrm
.reg
]);
17870 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17873 || (bytemode
!= evex_rounding_mode
17874 && bytemode
!= evex_sae_mode
))
17876 if (modrm
.mod
== 3 && vex
.b
)
17879 case evex_rounding_mode
:
17880 oappend (names_rounding
[vex
.ll
]);
17882 case evex_sae_mode
: