1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void OP_LWPCB_E (int, int);
121 static void OP_LWP_E (int, int);
122 static void OP_Vex_2src_1 (int, int);
123 static void OP_Vex_2src_2 (int, int);
125 static void MOVBE_Fixup (int, int);
127 static void OP_Mask (int, int);
130 /* Points to first byte not fetched. */
131 bfd_byte
*max_fetched
;
132 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
135 OPCODES_SIGJMP_BUF bailout
;
145 enum address_mode address_mode
;
147 /* Flags for the prefixes for the current instruction. See below. */
150 /* REX prefix the current instruction. See below. */
152 /* Bits of REX we've already used. */
154 /* REX bits in original REX prefix ignored. */
155 static int rex_ignored
;
156 /* Mark parts used in the REX prefix. When we are testing for
157 empty prefix (for 8bit register REX extension), just mask it
158 out. Otherwise test for REX bit is excuse for existence of REX
159 only in case value is nonzero. */
160 #define USED_REX(value) \
165 rex_used |= (value) | REX_OPCODE; \
168 rex_used |= REX_OPCODE; \
171 /* Flags for prefixes which we somehow handled when printing the
172 current instruction. */
173 static int used_prefixes
;
175 /* Flags stored in PREFIXES. */
176 #define PREFIX_REPZ 1
177 #define PREFIX_REPNZ 2
178 #define PREFIX_LOCK 4
180 #define PREFIX_SS 0x10
181 #define PREFIX_DS 0x20
182 #define PREFIX_ES 0x40
183 #define PREFIX_FS 0x80
184 #define PREFIX_GS 0x100
185 #define PREFIX_DATA 0x200
186 #define PREFIX_ADDR 0x400
187 #define PREFIX_FWAIT 0x800
189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
190 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
192 #define FETCH_DATA(info, addr) \
193 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
194 ? 1 : fetch_data ((info), (addr)))
197 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
200 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
201 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
203 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
204 status
= (*info
->read_memory_func
) (start
,
206 addr
- priv
->max_fetched
,
212 /* If we did manage to read at least one byte, then
213 print_insn_i386 will do something sensible. Otherwise, print
214 an error. We do that here because this is where we know
216 if (priv
->max_fetched
== priv
->the_buffer
)
217 (*info
->memory_error_func
) (status
, start
, info
);
218 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
221 priv
->max_fetched
= addr
;
225 /* Possible values for prefix requirement. */
226 #define PREFIX_IGNORED_SHIFT 16
227 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
228 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
233 /* Opcode prefixes. */
234 #define PREFIX_OPCODE (PREFIX_REPZ \
238 /* Prefixes ignored. */
239 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
240 | PREFIX_IGNORED_REPNZ \
241 | PREFIX_IGNORED_DATA)
243 #define XX { NULL, 0 }
244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
246 #define Eb { OP_E, b_mode }
247 #define Ebnd { OP_E, bnd_mode }
248 #define EbS { OP_E, b_swap_mode }
249 #define Ev { OP_E, v_mode }
250 #define Ev_bnd { OP_E, v_bnd_mode }
251 #define EvS { OP_E, v_swap_mode }
252 #define Ed { OP_E, d_mode }
253 #define Edq { OP_E, dq_mode }
254 #define Edqw { OP_E, dqw_mode }
255 #define EdqwS { OP_E, dqw_swap_mode }
256 #define Edqb { OP_E, dqb_mode }
257 #define Edb { OP_E, db_mode }
258 #define Edw { OP_E, dw_mode }
259 #define Edqd { OP_E, dqd_mode }
260 #define Eq { OP_E, q_mode }
261 #define indirEv { OP_indirE, stack_v_mode }
262 #define indirEp { OP_indirE, f_mode }
263 #define stackEv { OP_E, stack_v_mode }
264 #define Em { OP_E, m_mode }
265 #define Ew { OP_E, w_mode }
266 #define M { OP_M, 0 } /* lea, lgdt, etc. */
267 #define Ma { OP_M, a_mode }
268 #define Mb { OP_M, b_mode }
269 #define Md { OP_M, d_mode }
270 #define Mo { OP_M, o_mode }
271 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
272 #define Mq { OP_M, q_mode }
273 #define Mx { OP_M, x_mode }
274 #define Mxmm { OP_M, xmm_mode }
275 #define Gb { OP_G, b_mode }
276 #define Gbnd { OP_G, bnd_mode }
277 #define Gv { OP_G, v_mode }
278 #define Gd { OP_G, d_mode }
279 #define Gdq { OP_G, dq_mode }
280 #define Gm { OP_G, m_mode }
281 #define Gw { OP_G, w_mode }
282 #define Rd { OP_R, d_mode }
283 #define Rdq { OP_R, dq_mode }
284 #define Rm { OP_R, m_mode }
285 #define Ib { OP_I, b_mode }
286 #define sIb { OP_sI, b_mode } /* sign extened byte */
287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
288 #define Iv { OP_I, v_mode }
289 #define sIv { OP_sI, v_mode }
290 #define Iq { OP_I, q_mode }
291 #define Iv64 { OP_I64, v_mode }
292 #define Iw { OP_I, w_mode }
293 #define I1 { OP_I, const_1_mode }
294 #define Jb { OP_J, b_mode }
295 #define Jv { OP_J, v_mode }
296 #define Cm { OP_C, m_mode }
297 #define Dm { OP_D, m_mode }
298 #define Td { OP_T, d_mode }
299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
301 #define RMeAX { OP_REG, eAX_reg }
302 #define RMeBX { OP_REG, eBX_reg }
303 #define RMeCX { OP_REG, eCX_reg }
304 #define RMeDX { OP_REG, eDX_reg }
305 #define RMeSP { OP_REG, eSP_reg }
306 #define RMeBP { OP_REG, eBP_reg }
307 #define RMeSI { OP_REG, eSI_reg }
308 #define RMeDI { OP_REG, eDI_reg }
309 #define RMrAX { OP_REG, rAX_reg }
310 #define RMrBX { OP_REG, rBX_reg }
311 #define RMrCX { OP_REG, rCX_reg }
312 #define RMrDX { OP_REG, rDX_reg }
313 #define RMrSP { OP_REG, rSP_reg }
314 #define RMrBP { OP_REG, rBP_reg }
315 #define RMrSI { OP_REG, rSI_reg }
316 #define RMrDI { OP_REG, rDI_reg }
317 #define RMAL { OP_REG, al_reg }
318 #define RMCL { OP_REG, cl_reg }
319 #define RMDL { OP_REG, dl_reg }
320 #define RMBL { OP_REG, bl_reg }
321 #define RMAH { OP_REG, ah_reg }
322 #define RMCH { OP_REG, ch_reg }
323 #define RMDH { OP_REG, dh_reg }
324 #define RMBH { OP_REG, bh_reg }
325 #define RMAX { OP_REG, ax_reg }
326 #define RMDX { OP_REG, dx_reg }
328 #define eAX { OP_IMREG, eAX_reg }
329 #define eBX { OP_IMREG, eBX_reg }
330 #define eCX { OP_IMREG, eCX_reg }
331 #define eDX { OP_IMREG, eDX_reg }
332 #define eSP { OP_IMREG, eSP_reg }
333 #define eBP { OP_IMREG, eBP_reg }
334 #define eSI { OP_IMREG, eSI_reg }
335 #define eDI { OP_IMREG, eDI_reg }
336 #define AL { OP_IMREG, al_reg }
337 #define CL { OP_IMREG, cl_reg }
338 #define DL { OP_IMREG, dl_reg }
339 #define BL { OP_IMREG, bl_reg }
340 #define AH { OP_IMREG, ah_reg }
341 #define CH { OP_IMREG, ch_reg }
342 #define DH { OP_IMREG, dh_reg }
343 #define BH { OP_IMREG, bh_reg }
344 #define AX { OP_IMREG, ax_reg }
345 #define DX { OP_IMREG, dx_reg }
346 #define zAX { OP_IMREG, z_mode_ax_reg }
347 #define indirDX { OP_IMREG, indir_dx_reg }
349 #define Sw { OP_SEG, w_mode }
350 #define Sv { OP_SEG, v_mode }
351 #define Ap { OP_DIR, 0 }
352 #define Ob { OP_OFF64, b_mode }
353 #define Ov { OP_OFF64, v_mode }
354 #define Xb { OP_DSreg, eSI_reg }
355 #define Xv { OP_DSreg, eSI_reg }
356 #define Xz { OP_DSreg, eSI_reg }
357 #define Yb { OP_ESreg, eDI_reg }
358 #define Yv { OP_ESreg, eDI_reg }
359 #define DSBX { OP_DSreg, eBX_reg }
361 #define es { OP_REG, es_reg }
362 #define ss { OP_REG, ss_reg }
363 #define cs { OP_REG, cs_reg }
364 #define ds { OP_REG, ds_reg }
365 #define fs { OP_REG, fs_reg }
366 #define gs { OP_REG, gs_reg }
368 #define MX { OP_MMX, 0 }
369 #define XM { OP_XMM, 0 }
370 #define XMScalar { OP_XMM, scalar_mode }
371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
372 #define XMM { OP_XMM, xmm_mode }
373 #define XMxmmq { OP_XMM, xmmq_mode }
374 #define EM { OP_EM, v_mode }
375 #define EMS { OP_EM, v_swap_mode }
376 #define EMd { OP_EM, d_mode }
377 #define EMx { OP_EM, x_mode }
378 #define EXw { OP_EX, w_mode }
379 #define EXd { OP_EX, d_mode }
380 #define EXdScalar { OP_EX, d_scalar_mode }
381 #define EXdS { OP_EX, d_swap_mode }
382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
383 #define EXq { OP_EX, q_mode }
384 #define EXqScalar { OP_EX, q_scalar_mode }
385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
386 #define EXqS { OP_EX, q_swap_mode }
387 #define EXx { OP_EX, x_mode }
388 #define EXxS { OP_EX, x_swap_mode }
389 #define EXxmm { OP_EX, xmm_mode }
390 #define EXymm { OP_EX, ymm_mode }
391 #define EXxmmq { OP_EX, xmmq_mode }
392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
395 #define EXxmm_md { OP_EX, xmm_md_mode }
396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
398 #define EXxmmdw { OP_EX, xmmdw_mode }
399 #define EXxmmqd { OP_EX, xmmqd_mode }
400 #define EXymmq { OP_EX, ymmq_mode }
401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
405 #define MS { OP_MS, v_mode }
406 #define XS { OP_XS, v_mode }
407 #define EMCq { OP_EMC, q_mode }
408 #define MXC { OP_MXC, 0 }
409 #define OPSUF { OP_3DNowSuffix, 0 }
410 #define CMP { CMP_Fixup, 0 }
411 #define XMM0 { XMM_Fixup, 0 }
412 #define FXSAVE { FXSAVE_Fixup, 0 }
413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
416 #define Vex { OP_VEX, vex_mode }
417 #define VexScalar { OP_VEX, vex_scalar_mode }
418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
419 #define Vex128 { OP_VEX, vex128_mode }
420 #define Vex256 { OP_VEX, vex256_mode }
421 #define VexGdq { OP_VEX, dq_mode }
422 #define VexI4 { VEXI4_Fixup, 0}
423 #define EXdVex { OP_EX_Vex, d_mode }
424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
426 #define EXqVex { OP_EX_Vex, q_mode }
427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
429 #define EXVexW { OP_EX_VexW, x_mode }
430 #define EXdVexW { OP_EX_VexW, d_mode }
431 #define EXqVexW { OP_EX_VexW, q_mode }
432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
433 #define XMVex { OP_XMM_Vex, 0 }
434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
435 #define XMVexW { OP_XMM_VexW, 0 }
436 #define XMVexI4 { OP_REG_VexI4, x_mode }
437 #define PCLMUL { PCLMUL_Fixup, 0 }
438 #define VZERO { VZERO_Fixup, 0 }
439 #define VCMP { VCMP_Fixup, 0 }
440 #define VPCMP { VPCMP_Fixup, 0 }
442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
445 #define XMask { OP_Mask, mask_mode }
446 #define MaskG { OP_G, mask_mode }
447 #define MaskE { OP_E, mask_mode }
448 #define MaskBDE { OP_E, mask_bd_mode }
449 #define MaskR { OP_R, mask_mode }
450 #define MaskVex { OP_VEX, mask_mode }
452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
457 /* Used handle "rep" prefix for string instructions. */
458 #define Xbr { REP_Fixup, eSI_reg }
459 #define Xvr { REP_Fixup, eSI_reg }
460 #define Ybr { REP_Fixup, eDI_reg }
461 #define Yvr { REP_Fixup, eDI_reg }
462 #define Yzr { REP_Fixup, eDI_reg }
463 #define indirDXr { REP_Fixup, indir_dx_reg }
464 #define ALr { REP_Fixup, al_reg }
465 #define eAXr { REP_Fixup, eAX_reg }
467 /* Used handle HLE prefix for lockable instructions. */
468 #define Ebh1 { HLE_Fixup1, b_mode }
469 #define Evh1 { HLE_Fixup1, v_mode }
470 #define Ebh2 { HLE_Fixup2, b_mode }
471 #define Evh2 { HLE_Fixup2, v_mode }
472 #define Ebh3 { HLE_Fixup3, b_mode }
473 #define Evh3 { HLE_Fixup3, v_mode }
475 #define BND { BND_Fixup, 0 }
477 #define cond_jump_flag { NULL, cond_jump_mode }
478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
480 /* bits in sizeflag */
481 #define SUFFIX_ALWAYS 4
489 /* byte operand with operand swapped */
491 /* byte operand, sign extend like 'T' suffix */
493 /* operand size depends on prefixes */
495 /* operand size depends on prefixes with operand swapped */
499 /* double word operand */
501 /* double word operand with operand swapped */
503 /* quad word operand */
505 /* quad word operand with operand swapped */
507 /* ten-byte operand */
509 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
510 broadcast enabled. */
512 /* Similar to x_mode, but with different EVEX mem shifts. */
514 /* Similar to x_mode, but with disabled broadcast. */
516 /* Similar to x_mode, but with operands swapped and disabled broadcast
519 /* 16-byte XMM operand */
521 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
522 memory operand (depending on vector length). Broadcast isn't
525 /* Same as xmmq_mode, but broadcast is allowed. */
526 evex_half_bcst_xmmq_mode
,
527 /* XMM register or byte memory operand */
529 /* XMM register or word memory operand */
531 /* XMM register or double word memory operand */
533 /* XMM register or quad word memory operand */
535 /* XMM register or double/quad word memory operand, depending on
538 /* 16-byte XMM, word, double word or quad word operand. */
540 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
542 /* 32-byte YMM operand */
544 /* quad word, ymmword or zmmword memory operand. */
546 /* 32-byte YMM or 16-byte word operand */
548 /* d_mode in 32bit, q_mode in 64bit mode. */
550 /* pair of v_mode operands */
555 /* operand size depends on REX prefixes. */
557 /* registers like dq_mode, memory like w_mode. */
561 /* 4- or 6-byte pointer operand */
564 /* v_mode for stack-related opcodes. */
566 /* non-quad operand size depends on prefixes */
568 /* 16-byte operand */
570 /* registers like dq_mode, memory like b_mode. */
572 /* registers like d_mode, memory like b_mode. */
574 /* registers like d_mode, memory like w_mode. */
576 /* registers like dq_mode, memory like d_mode. */
578 /* normal vex mode */
580 /* 128bit vex mode */
582 /* 256bit vex mode */
584 /* operand size depends on the VEX.W bit. */
587 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
588 vex_vsib_d_w_dq_mode
,
589 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
591 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
592 vex_vsib_q_w_dq_mode
,
593 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
596 /* scalar, ignore vector length. */
598 /* like d_mode, ignore vector length. */
600 /* like d_swap_mode, ignore vector length. */
602 /* like q_mode, ignore vector length. */
604 /* like q_swap_mode, ignore vector length. */
606 /* like vex_mode, ignore vector length. */
608 /* like vex_w_dq_mode, ignore vector length. */
609 vex_scalar_w_dq_mode
,
611 /* Static rounding. */
613 /* Supress all exceptions. */
616 /* Mask register operand. */
618 /* Mask register operand. */
685 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
687 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
688 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
689 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
690 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
691 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
692 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
693 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
694 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
695 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
696 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
697 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
698 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
699 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
700 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
701 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
818 MOD_VEX_0F12_PREFIX_0
,
820 MOD_VEX_0F16_PREFIX_0
,
823 MOD_VEX_W_0_0F41_P_0_LEN_1
,
824 MOD_VEX_W_1_0F41_P_0_LEN_1
,
825 MOD_VEX_W_0_0F41_P_2_LEN_1
,
826 MOD_VEX_W_1_0F41_P_2_LEN_1
,
827 MOD_VEX_W_0_0F42_P_0_LEN_1
,
828 MOD_VEX_W_1_0F42_P_0_LEN_1
,
829 MOD_VEX_W_0_0F42_P_2_LEN_1
,
830 MOD_VEX_W_1_0F42_P_2_LEN_1
,
831 MOD_VEX_W_0_0F44_P_0_LEN_1
,
832 MOD_VEX_W_1_0F44_P_0_LEN_1
,
833 MOD_VEX_W_0_0F44_P_2_LEN_1
,
834 MOD_VEX_W_1_0F44_P_2_LEN_1
,
835 MOD_VEX_W_0_0F45_P_0_LEN_1
,
836 MOD_VEX_W_1_0F45_P_0_LEN_1
,
837 MOD_VEX_W_0_0F45_P_2_LEN_1
,
838 MOD_VEX_W_1_0F45_P_2_LEN_1
,
839 MOD_VEX_W_0_0F46_P_0_LEN_1
,
840 MOD_VEX_W_1_0F46_P_0_LEN_1
,
841 MOD_VEX_W_0_0F46_P_2_LEN_1
,
842 MOD_VEX_W_1_0F46_P_2_LEN_1
,
843 MOD_VEX_W_0_0F47_P_0_LEN_1
,
844 MOD_VEX_W_1_0F47_P_0_LEN_1
,
845 MOD_VEX_W_0_0F47_P_2_LEN_1
,
846 MOD_VEX_W_1_0F47_P_2_LEN_1
,
847 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
848 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
849 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
850 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
851 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
852 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
853 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
865 MOD_VEX_W_0_0F91_P_0_LEN_0
,
866 MOD_VEX_W_1_0F91_P_0_LEN_0
,
867 MOD_VEX_W_0_0F91_P_2_LEN_0
,
868 MOD_VEX_W_1_0F91_P_2_LEN_0
,
869 MOD_VEX_W_0_0F92_P_0_LEN_0
,
870 MOD_VEX_W_0_0F92_P_2_LEN_0
,
871 MOD_VEX_W_0_0F92_P_3_LEN_0
,
872 MOD_VEX_W_1_0F92_P_3_LEN_0
,
873 MOD_VEX_W_0_0F93_P_0_LEN_0
,
874 MOD_VEX_W_0_0F93_P_2_LEN_0
,
875 MOD_VEX_W_0_0F93_P_3_LEN_0
,
876 MOD_VEX_W_1_0F93_P_3_LEN_0
,
877 MOD_VEX_W_0_0F98_P_0_LEN_0
,
878 MOD_VEX_W_1_0F98_P_0_LEN_0
,
879 MOD_VEX_W_0_0F98_P_2_LEN_0
,
880 MOD_VEX_W_1_0F98_P_2_LEN_0
,
881 MOD_VEX_W_0_0F99_P_0_LEN_0
,
882 MOD_VEX_W_1_0F99_P_0_LEN_0
,
883 MOD_VEX_W_0_0F99_P_2_LEN_0
,
884 MOD_VEX_W_1_0F99_P_2_LEN_0
,
887 MOD_VEX_0FD7_PREFIX_2
,
888 MOD_VEX_0FE7_PREFIX_2
,
889 MOD_VEX_0FF0_PREFIX_3
,
890 MOD_VEX_0F381A_PREFIX_2
,
891 MOD_VEX_0F382A_PREFIX_2
,
892 MOD_VEX_0F382C_PREFIX_2
,
893 MOD_VEX_0F382D_PREFIX_2
,
894 MOD_VEX_0F382E_PREFIX_2
,
895 MOD_VEX_0F382F_PREFIX_2
,
896 MOD_VEX_0F385A_PREFIX_2
,
897 MOD_VEX_0F388C_PREFIX_2
,
898 MOD_VEX_0F388E_PREFIX_2
,
899 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
900 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
901 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
902 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
903 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
904 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
905 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
906 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
908 MOD_EVEX_0F10_PREFIX_1
,
909 MOD_EVEX_0F10_PREFIX_3
,
910 MOD_EVEX_0F11_PREFIX_1
,
911 MOD_EVEX_0F11_PREFIX_3
,
912 MOD_EVEX_0F12_PREFIX_0
,
913 MOD_EVEX_0F16_PREFIX_0
,
914 MOD_EVEX_0F38C6_REG_1
,
915 MOD_EVEX_0F38C6_REG_2
,
916 MOD_EVEX_0F38C6_REG_5
,
917 MOD_EVEX_0F38C6_REG_6
,
918 MOD_EVEX_0F38C7_REG_1
,
919 MOD_EVEX_0F38C7_REG_2
,
920 MOD_EVEX_0F38C7_REG_5
,
921 MOD_EVEX_0F38C7_REG_6
985 PREFIX_RM_0_0FAE_REG_7
,
991 PREFIX_MOD_0_0FC7_REG_6
,
992 PREFIX_MOD_3_0FC7_REG_6
,
993 PREFIX_MOD_3_0FC7_REG_7
,
1117 PREFIX_VEX_0F71_REG_2
,
1118 PREFIX_VEX_0F71_REG_4
,
1119 PREFIX_VEX_0F71_REG_6
,
1120 PREFIX_VEX_0F72_REG_2
,
1121 PREFIX_VEX_0F72_REG_4
,
1122 PREFIX_VEX_0F72_REG_6
,
1123 PREFIX_VEX_0F73_REG_2
,
1124 PREFIX_VEX_0F73_REG_3
,
1125 PREFIX_VEX_0F73_REG_6
,
1126 PREFIX_VEX_0F73_REG_7
,
1298 PREFIX_VEX_0F38F3_REG_1
,
1299 PREFIX_VEX_0F38F3_REG_2
,
1300 PREFIX_VEX_0F38F3_REG_3
,
1417 PREFIX_EVEX_0F71_REG_2
,
1418 PREFIX_EVEX_0F71_REG_4
,
1419 PREFIX_EVEX_0F71_REG_6
,
1420 PREFIX_EVEX_0F72_REG_0
,
1421 PREFIX_EVEX_0F72_REG_1
,
1422 PREFIX_EVEX_0F72_REG_2
,
1423 PREFIX_EVEX_0F72_REG_4
,
1424 PREFIX_EVEX_0F72_REG_6
,
1425 PREFIX_EVEX_0F73_REG_2
,
1426 PREFIX_EVEX_0F73_REG_3
,
1427 PREFIX_EVEX_0F73_REG_6
,
1428 PREFIX_EVEX_0F73_REG_7
,
1611 PREFIX_EVEX_0F38C6_REG_1
,
1612 PREFIX_EVEX_0F38C6_REG_2
,
1613 PREFIX_EVEX_0F38C6_REG_5
,
1614 PREFIX_EVEX_0F38C6_REG_6
,
1615 PREFIX_EVEX_0F38C7_REG_1
,
1616 PREFIX_EVEX_0F38C7_REG_2
,
1617 PREFIX_EVEX_0F38C7_REG_5
,
1618 PREFIX_EVEX_0F38C7_REG_6
,
1707 THREE_BYTE_0F38
= 0,
1735 VEX_LEN_0F10_P_1
= 0,
1739 VEX_LEN_0F12_P_0_M_0
,
1740 VEX_LEN_0F12_P_0_M_1
,
1743 VEX_LEN_0F16_P_0_M_0
,
1744 VEX_LEN_0F16_P_0_M_1
,
1808 VEX_LEN_0FAE_R_2_M_0
,
1809 VEX_LEN_0FAE_R_3_M_0
,
1818 VEX_LEN_0F381A_P_2_M_0
,
1821 VEX_LEN_0F385A_P_2_M_0
,
1828 VEX_LEN_0F38F3_R_1_P_0
,
1829 VEX_LEN_0F38F3_R_2_P_0
,
1830 VEX_LEN_0F38F3_R_3_P_0
,
1876 VEX_LEN_0FXOP_08_CC
,
1877 VEX_LEN_0FXOP_08_CD
,
1878 VEX_LEN_0FXOP_08_CE
,
1879 VEX_LEN_0FXOP_08_CF
,
1880 VEX_LEN_0FXOP_08_EC
,
1881 VEX_LEN_0FXOP_08_ED
,
1882 VEX_LEN_0FXOP_08_EE
,
1883 VEX_LEN_0FXOP_08_EF
,
1884 VEX_LEN_0FXOP_09_80
,
1918 VEX_W_0F41_P_0_LEN_1
,
1919 VEX_W_0F41_P_2_LEN_1
,
1920 VEX_W_0F42_P_0_LEN_1
,
1921 VEX_W_0F42_P_2_LEN_1
,
1922 VEX_W_0F44_P_0_LEN_0
,
1923 VEX_W_0F44_P_2_LEN_0
,
1924 VEX_W_0F45_P_0_LEN_1
,
1925 VEX_W_0F45_P_2_LEN_1
,
1926 VEX_W_0F46_P_0_LEN_1
,
1927 VEX_W_0F46_P_2_LEN_1
,
1928 VEX_W_0F47_P_0_LEN_1
,
1929 VEX_W_0F47_P_2_LEN_1
,
1930 VEX_W_0F4A_P_0_LEN_1
,
1931 VEX_W_0F4A_P_2_LEN_1
,
1932 VEX_W_0F4B_P_0_LEN_1
,
1933 VEX_W_0F4B_P_2_LEN_1
,
2013 VEX_W_0F90_P_0_LEN_0
,
2014 VEX_W_0F90_P_2_LEN_0
,
2015 VEX_W_0F91_P_0_LEN_0
,
2016 VEX_W_0F91_P_2_LEN_0
,
2017 VEX_W_0F92_P_0_LEN_0
,
2018 VEX_W_0F92_P_2_LEN_0
,
2019 VEX_W_0F92_P_3_LEN_0
,
2020 VEX_W_0F93_P_0_LEN_0
,
2021 VEX_W_0F93_P_2_LEN_0
,
2022 VEX_W_0F93_P_3_LEN_0
,
2023 VEX_W_0F98_P_0_LEN_0
,
2024 VEX_W_0F98_P_2_LEN_0
,
2025 VEX_W_0F99_P_0_LEN_0
,
2026 VEX_W_0F99_P_2_LEN_0
,
2105 VEX_W_0F381A_P_2_M_0
,
2117 VEX_W_0F382A_P_2_M_0
,
2119 VEX_W_0F382C_P_2_M_0
,
2120 VEX_W_0F382D_P_2_M_0
,
2121 VEX_W_0F382E_P_2_M_0
,
2122 VEX_W_0F382F_P_2_M_0
,
2144 VEX_W_0F385A_P_2_M_0
,
2172 VEX_W_0F3A30_P_2_LEN_0
,
2173 VEX_W_0F3A31_P_2_LEN_0
,
2174 VEX_W_0F3A32_P_2_LEN_0
,
2175 VEX_W_0F3A33_P_2_LEN_0
,
2195 EVEX_W_0F10_P_1_M_0
,
2196 EVEX_W_0F10_P_1_M_1
,
2198 EVEX_W_0F10_P_3_M_0
,
2199 EVEX_W_0F10_P_3_M_1
,
2201 EVEX_W_0F11_P_1_M_0
,
2202 EVEX_W_0F11_P_1_M_1
,
2204 EVEX_W_0F11_P_3_M_0
,
2205 EVEX_W_0F11_P_3_M_1
,
2206 EVEX_W_0F12_P_0_M_0
,
2207 EVEX_W_0F12_P_0_M_1
,
2217 EVEX_W_0F16_P_0_M_0
,
2218 EVEX_W_0F16_P_0_M_1
,
2289 EVEX_W_0F72_R_2_P_2
,
2290 EVEX_W_0F72_R_6_P_2
,
2291 EVEX_W_0F73_R_2_P_2
,
2292 EVEX_W_0F73_R_6_P_2
,
2392 EVEX_W_0F38C7_R_1_P_2
,
2393 EVEX_W_0F38C7_R_2_P_2
,
2394 EVEX_W_0F38C7_R_5_P_2
,
2395 EVEX_W_0F38C7_R_6_P_2
,
2430 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2439 unsigned int prefix_requirement
;
2442 /* Upper case letters in the instruction names here are macros.
2443 'A' => print 'b' if no register operands or suffix_always is true
2444 'B' => print 'b' if suffix_always is true
2445 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2447 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2448 suffix_always is true
2449 'E' => print 'e' if 32-bit form of jcxz
2450 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2451 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2452 'H' => print ",pt" or ",pn" branch hint
2453 'I' => honor following macro letter even in Intel mode (implemented only
2454 for some of the macro letters)
2456 'K' => print 'd' or 'q' if rex prefix is present.
2457 'L' => print 'l' if suffix_always is true
2458 'M' => print 'r' if intel_mnemonic is false.
2459 'N' => print 'n' if instruction has no wait "prefix"
2460 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2461 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2462 or suffix_always is true. print 'q' if rex prefix is present.
2463 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2465 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2466 'S' => print 'w', 'l' or 'q' if suffix_always is true
2467 'T' => print 'q' in 64bit mode if instruction has no operand size
2468 prefix and behave as 'P' otherwise
2469 'U' => print 'q' in 64bit mode if instruction has no operand size
2470 prefix and behave as 'Q' otherwise
2471 'V' => print 'q' in 64bit mode if instruction has no operand size
2472 prefix and behave as 'S' otherwise
2473 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2474 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2475 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2476 suffix_always is true.
2477 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2478 '!' => change condition from true to false or from false to true.
2479 '%' => add 1 upper case letter to the macro.
2480 '^' => print 'w' or 'l' depending on operand size prefix or
2481 suffix_always is true (lcall/ljmp).
2482 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2483 on operand size prefix.
2485 2 upper case letter macros:
2486 "XY" => print 'x' or 'y' if suffix_always is true or no register
2487 operands and no broadcast.
2488 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2489 register operands and no broadcast.
2490 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2491 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2492 or suffix_always is true
2493 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2494 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2495 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2496 "LW" => print 'd', 'q' depending on the VEX.W bit
2497 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2498 an operand size prefix, or suffix_always is true. print
2499 'q' if rex prefix is present.
2501 Many of the above letters print nothing in Intel mode. See "putop"
2504 Braces '{' and '}', and vertical bars '|', indicate alternative
2505 mnemonic strings for AT&T and Intel. */
2507 static const struct dis386 dis386
[] = {
2509 { "addB", { Ebh1
, Gb
}, 0 },
2510 { "addS", { Evh1
, Gv
}, 0 },
2511 { "addB", { Gb
, EbS
}, 0 },
2512 { "addS", { Gv
, EvS
}, 0 },
2513 { "addB", { AL
, Ib
}, 0 },
2514 { "addS", { eAX
, Iv
}, 0 },
2515 { X86_64_TABLE (X86_64_06
) },
2516 { X86_64_TABLE (X86_64_07
) },
2518 { "orB", { Ebh1
, Gb
}, 0 },
2519 { "orS", { Evh1
, Gv
}, 0 },
2520 { "orB", { Gb
, EbS
}, 0 },
2521 { "orS", { Gv
, EvS
}, 0 },
2522 { "orB", { AL
, Ib
}, 0 },
2523 { "orS", { eAX
, Iv
}, 0 },
2524 { X86_64_TABLE (X86_64_0D
) },
2525 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2527 { "adcB", { Ebh1
, Gb
}, 0 },
2528 { "adcS", { Evh1
, Gv
}, 0 },
2529 { "adcB", { Gb
, EbS
}, 0 },
2530 { "adcS", { Gv
, EvS
}, 0 },
2531 { "adcB", { AL
, Ib
}, 0 },
2532 { "adcS", { eAX
, Iv
}, 0 },
2533 { X86_64_TABLE (X86_64_16
) },
2534 { X86_64_TABLE (X86_64_17
) },
2536 { "sbbB", { Ebh1
, Gb
}, 0 },
2537 { "sbbS", { Evh1
, Gv
}, 0 },
2538 { "sbbB", { Gb
, EbS
}, 0 },
2539 { "sbbS", { Gv
, EvS
}, 0 },
2540 { "sbbB", { AL
, Ib
}, 0 },
2541 { "sbbS", { eAX
, Iv
}, 0 },
2542 { X86_64_TABLE (X86_64_1E
) },
2543 { X86_64_TABLE (X86_64_1F
) },
2545 { "andB", { Ebh1
, Gb
}, 0 },
2546 { "andS", { Evh1
, Gv
}, 0 },
2547 { "andB", { Gb
, EbS
}, 0 },
2548 { "andS", { Gv
, EvS
}, 0 },
2549 { "andB", { AL
, Ib
}, 0 },
2550 { "andS", { eAX
, Iv
}, 0 },
2551 { Bad_Opcode
}, /* SEG ES prefix */
2552 { X86_64_TABLE (X86_64_27
) },
2554 { "subB", { Ebh1
, Gb
}, 0 },
2555 { "subS", { Evh1
, Gv
}, 0 },
2556 { "subB", { Gb
, EbS
}, 0 },
2557 { "subS", { Gv
, EvS
}, 0 },
2558 { "subB", { AL
, Ib
}, 0 },
2559 { "subS", { eAX
, Iv
}, 0 },
2560 { Bad_Opcode
}, /* SEG CS prefix */
2561 { X86_64_TABLE (X86_64_2F
) },
2563 { "xorB", { Ebh1
, Gb
}, 0 },
2564 { "xorS", { Evh1
, Gv
}, 0 },
2565 { "xorB", { Gb
, EbS
}, 0 },
2566 { "xorS", { Gv
, EvS
}, 0 },
2567 { "xorB", { AL
, Ib
}, 0 },
2568 { "xorS", { eAX
, Iv
}, 0 },
2569 { Bad_Opcode
}, /* SEG SS prefix */
2570 { X86_64_TABLE (X86_64_37
) },
2572 { "cmpB", { Eb
, Gb
}, 0 },
2573 { "cmpS", { Ev
, Gv
}, 0 },
2574 { "cmpB", { Gb
, EbS
}, 0 },
2575 { "cmpS", { Gv
, EvS
}, 0 },
2576 { "cmpB", { AL
, Ib
}, 0 },
2577 { "cmpS", { eAX
, Iv
}, 0 },
2578 { Bad_Opcode
}, /* SEG DS prefix */
2579 { X86_64_TABLE (X86_64_3F
) },
2581 { "inc{S|}", { RMeAX
}, 0 },
2582 { "inc{S|}", { RMeCX
}, 0 },
2583 { "inc{S|}", { RMeDX
}, 0 },
2584 { "inc{S|}", { RMeBX
}, 0 },
2585 { "inc{S|}", { RMeSP
}, 0 },
2586 { "inc{S|}", { RMeBP
}, 0 },
2587 { "inc{S|}", { RMeSI
}, 0 },
2588 { "inc{S|}", { RMeDI
}, 0 },
2590 { "dec{S|}", { RMeAX
}, 0 },
2591 { "dec{S|}", { RMeCX
}, 0 },
2592 { "dec{S|}", { RMeDX
}, 0 },
2593 { "dec{S|}", { RMeBX
}, 0 },
2594 { "dec{S|}", { RMeSP
}, 0 },
2595 { "dec{S|}", { RMeBP
}, 0 },
2596 { "dec{S|}", { RMeSI
}, 0 },
2597 { "dec{S|}", { RMeDI
}, 0 },
2599 { "pushV", { RMrAX
}, 0 },
2600 { "pushV", { RMrCX
}, 0 },
2601 { "pushV", { RMrDX
}, 0 },
2602 { "pushV", { RMrBX
}, 0 },
2603 { "pushV", { RMrSP
}, 0 },
2604 { "pushV", { RMrBP
}, 0 },
2605 { "pushV", { RMrSI
}, 0 },
2606 { "pushV", { RMrDI
}, 0 },
2608 { "popV", { RMrAX
}, 0 },
2609 { "popV", { RMrCX
}, 0 },
2610 { "popV", { RMrDX
}, 0 },
2611 { "popV", { RMrBX
}, 0 },
2612 { "popV", { RMrSP
}, 0 },
2613 { "popV", { RMrBP
}, 0 },
2614 { "popV", { RMrSI
}, 0 },
2615 { "popV", { RMrDI
}, 0 },
2617 { X86_64_TABLE (X86_64_60
) },
2618 { X86_64_TABLE (X86_64_61
) },
2619 { X86_64_TABLE (X86_64_62
) },
2620 { X86_64_TABLE (X86_64_63
) },
2621 { Bad_Opcode
}, /* seg fs */
2622 { Bad_Opcode
}, /* seg gs */
2623 { Bad_Opcode
}, /* op size prefix */
2624 { Bad_Opcode
}, /* adr size prefix */
2626 { "pushT", { sIv
}, 0 },
2627 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2628 { "pushT", { sIbT
}, 0 },
2629 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2630 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2631 { X86_64_TABLE (X86_64_6D
) },
2632 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2633 { X86_64_TABLE (X86_64_6F
) },
2635 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2636 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2637 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2638 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2639 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2640 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2641 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2642 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2644 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2645 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2646 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2647 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2648 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2649 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2650 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2651 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2653 { REG_TABLE (REG_80
) },
2654 { REG_TABLE (REG_81
) },
2656 { REG_TABLE (REG_82
) },
2657 { "testB", { Eb
, Gb
}, 0 },
2658 { "testS", { Ev
, Gv
}, 0 },
2659 { "xchgB", { Ebh2
, Gb
}, 0 },
2660 { "xchgS", { Evh2
, Gv
}, 0 },
2662 { "movB", { Ebh3
, Gb
}, 0 },
2663 { "movS", { Evh3
, Gv
}, 0 },
2664 { "movB", { Gb
, EbS
}, 0 },
2665 { "movS", { Gv
, EvS
}, 0 },
2666 { "movD", { Sv
, Sw
}, 0 },
2667 { MOD_TABLE (MOD_8D
) },
2668 { "movD", { Sw
, Sv
}, 0 },
2669 { REG_TABLE (REG_8F
) },
2671 { PREFIX_TABLE (PREFIX_90
) },
2672 { "xchgS", { RMeCX
, eAX
}, 0 },
2673 { "xchgS", { RMeDX
, eAX
}, 0 },
2674 { "xchgS", { RMeBX
, eAX
}, 0 },
2675 { "xchgS", { RMeSP
, eAX
}, 0 },
2676 { "xchgS", { RMeBP
, eAX
}, 0 },
2677 { "xchgS", { RMeSI
, eAX
}, 0 },
2678 { "xchgS", { RMeDI
, eAX
}, 0 },
2680 { "cW{t|}R", { XX
}, 0 },
2681 { "cR{t|}O", { XX
}, 0 },
2682 { X86_64_TABLE (X86_64_9A
) },
2683 { Bad_Opcode
}, /* fwait */
2684 { "pushfT", { XX
}, 0 },
2685 { "popfT", { XX
}, 0 },
2686 { "sahf", { XX
}, 0 },
2687 { "lahf", { XX
}, 0 },
2689 { "mov%LB", { AL
, Ob
}, 0 },
2690 { "mov%LS", { eAX
, Ov
}, 0 },
2691 { "mov%LB", { Ob
, AL
}, 0 },
2692 { "mov%LS", { Ov
, eAX
}, 0 },
2693 { "movs{b|}", { Ybr
, Xb
}, 0 },
2694 { "movs{R|}", { Yvr
, Xv
}, 0 },
2695 { "cmps{b|}", { Xb
, Yb
}, 0 },
2696 { "cmps{R|}", { Xv
, Yv
}, 0 },
2698 { "testB", { AL
, Ib
}, 0 },
2699 { "testS", { eAX
, Iv
}, 0 },
2700 { "stosB", { Ybr
, AL
}, 0 },
2701 { "stosS", { Yvr
, eAX
}, 0 },
2702 { "lodsB", { ALr
, Xb
}, 0 },
2703 { "lodsS", { eAXr
, Xv
}, 0 },
2704 { "scasB", { AL
, Yb
}, 0 },
2705 { "scasS", { eAX
, Yv
}, 0 },
2707 { "movB", { RMAL
, Ib
}, 0 },
2708 { "movB", { RMCL
, Ib
}, 0 },
2709 { "movB", { RMDL
, Ib
}, 0 },
2710 { "movB", { RMBL
, Ib
}, 0 },
2711 { "movB", { RMAH
, Ib
}, 0 },
2712 { "movB", { RMCH
, Ib
}, 0 },
2713 { "movB", { RMDH
, Ib
}, 0 },
2714 { "movB", { RMBH
, Ib
}, 0 },
2716 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2717 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2718 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2719 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2720 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2721 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2722 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2723 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2725 { REG_TABLE (REG_C0
) },
2726 { REG_TABLE (REG_C1
) },
2727 { "retT", { Iw
, BND
}, 0 },
2728 { "retT", { BND
}, 0 },
2729 { X86_64_TABLE (X86_64_C4
) },
2730 { X86_64_TABLE (X86_64_C5
) },
2731 { REG_TABLE (REG_C6
) },
2732 { REG_TABLE (REG_C7
) },
2734 { "enterT", { Iw
, Ib
}, 0 },
2735 { "leaveT", { XX
}, 0 },
2736 { "Jret{|f}P", { Iw
}, 0 },
2737 { "Jret{|f}P", { XX
}, 0 },
2738 { "int3", { XX
}, 0 },
2739 { "int", { Ib
}, 0 },
2740 { X86_64_TABLE (X86_64_CE
) },
2741 { "iret%LP", { XX
}, 0 },
2743 { REG_TABLE (REG_D0
) },
2744 { REG_TABLE (REG_D1
) },
2745 { REG_TABLE (REG_D2
) },
2746 { REG_TABLE (REG_D3
) },
2747 { X86_64_TABLE (X86_64_D4
) },
2748 { X86_64_TABLE (X86_64_D5
) },
2750 { "xlat", { DSBX
}, 0 },
2761 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2762 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2763 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2764 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2765 { "inB", { AL
, Ib
}, 0 },
2766 { "inG", { zAX
, Ib
}, 0 },
2767 { "outB", { Ib
, AL
}, 0 },
2768 { "outG", { Ib
, zAX
}, 0 },
2770 { X86_64_TABLE (X86_64_E8
) },
2771 { X86_64_TABLE (X86_64_E9
) },
2772 { X86_64_TABLE (X86_64_EA
) },
2773 { "jmp", { Jb
, BND
}, 0 },
2774 { "inB", { AL
, indirDX
}, 0 },
2775 { "inG", { zAX
, indirDX
}, 0 },
2776 { "outB", { indirDX
, AL
}, 0 },
2777 { "outG", { indirDX
, zAX
}, 0 },
2779 { Bad_Opcode
}, /* lock prefix */
2780 { "icebp", { XX
}, 0 },
2781 { Bad_Opcode
}, /* repne */
2782 { Bad_Opcode
}, /* repz */
2783 { "hlt", { XX
}, 0 },
2784 { "cmc", { XX
}, 0 },
2785 { REG_TABLE (REG_F6
) },
2786 { REG_TABLE (REG_F7
) },
2788 { "clc", { XX
}, 0 },
2789 { "stc", { XX
}, 0 },
2790 { "cli", { XX
}, 0 },
2791 { "sti", { XX
}, 0 },
2792 { "cld", { XX
}, 0 },
2793 { "std", { XX
}, 0 },
2794 { REG_TABLE (REG_FE
) },
2795 { REG_TABLE (REG_FF
) },
2798 static const struct dis386 dis386_twobyte
[] = {
2800 { REG_TABLE (REG_0F00
) },
2801 { REG_TABLE (REG_0F01
) },
2802 { "larS", { Gv
, Ew
}, 0 },
2803 { "lslS", { Gv
, Ew
}, 0 },
2805 { "syscall", { XX
}, 0 },
2806 { "clts", { XX
}, 0 },
2807 { "sysret%LP", { XX
}, 0 },
2809 { "invd", { XX
}, 0 },
2810 { "wbinvd", { XX
}, 0 },
2812 { "ud2", { XX
}, 0 },
2814 { REG_TABLE (REG_0F0D
) },
2815 { "femms", { XX
}, 0 },
2816 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2818 { PREFIX_TABLE (PREFIX_0F10
) },
2819 { PREFIX_TABLE (PREFIX_0F11
) },
2820 { PREFIX_TABLE (PREFIX_0F12
) },
2821 { MOD_TABLE (MOD_0F13
) },
2822 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2823 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2824 { PREFIX_TABLE (PREFIX_0F16
) },
2825 { MOD_TABLE (MOD_0F17
) },
2827 { REG_TABLE (REG_0F18
) },
2828 { "nopQ", { Ev
}, 0 },
2829 { PREFIX_TABLE (PREFIX_0F1A
) },
2830 { PREFIX_TABLE (PREFIX_0F1B
) },
2831 { "nopQ", { Ev
}, 0 },
2832 { "nopQ", { Ev
}, 0 },
2833 { "nopQ", { Ev
}, 0 },
2834 { "nopQ", { Ev
}, 0 },
2836 { "movZ", { Rm
, Cm
}, 0 },
2837 { "movZ", { Rm
, Dm
}, 0 },
2838 { "movZ", { Cm
, Rm
}, 0 },
2839 { "movZ", { Dm
, Rm
}, 0 },
2840 { MOD_TABLE (MOD_0F24
) },
2842 { MOD_TABLE (MOD_0F26
) },
2845 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2846 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2847 { PREFIX_TABLE (PREFIX_0F2A
) },
2848 { PREFIX_TABLE (PREFIX_0F2B
) },
2849 { PREFIX_TABLE (PREFIX_0F2C
) },
2850 { PREFIX_TABLE (PREFIX_0F2D
) },
2851 { PREFIX_TABLE (PREFIX_0F2E
) },
2852 { PREFIX_TABLE (PREFIX_0F2F
) },
2854 { "wrmsr", { XX
}, 0 },
2855 { "rdtsc", { XX
}, 0 },
2856 { "rdmsr", { XX
}, 0 },
2857 { "rdpmc", { XX
}, 0 },
2858 { "sysenter", { XX
}, 0 },
2859 { "sysexit", { XX
}, 0 },
2861 { "getsec", { XX
}, 0 },
2863 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2865 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2872 { "cmovoS", { Gv
, Ev
}, 0 },
2873 { "cmovnoS", { Gv
, Ev
}, 0 },
2874 { "cmovbS", { Gv
, Ev
}, 0 },
2875 { "cmovaeS", { Gv
, Ev
}, 0 },
2876 { "cmoveS", { Gv
, Ev
}, 0 },
2877 { "cmovneS", { Gv
, Ev
}, 0 },
2878 { "cmovbeS", { Gv
, Ev
}, 0 },
2879 { "cmovaS", { Gv
, Ev
}, 0 },
2881 { "cmovsS", { Gv
, Ev
}, 0 },
2882 { "cmovnsS", { Gv
, Ev
}, 0 },
2883 { "cmovpS", { Gv
, Ev
}, 0 },
2884 { "cmovnpS", { Gv
, Ev
}, 0 },
2885 { "cmovlS", { Gv
, Ev
}, 0 },
2886 { "cmovgeS", { Gv
, Ev
}, 0 },
2887 { "cmovleS", { Gv
, Ev
}, 0 },
2888 { "cmovgS", { Gv
, Ev
}, 0 },
2890 { MOD_TABLE (MOD_0F51
) },
2891 { PREFIX_TABLE (PREFIX_0F51
) },
2892 { PREFIX_TABLE (PREFIX_0F52
) },
2893 { PREFIX_TABLE (PREFIX_0F53
) },
2894 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2895 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2896 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2897 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2899 { PREFIX_TABLE (PREFIX_0F58
) },
2900 { PREFIX_TABLE (PREFIX_0F59
) },
2901 { PREFIX_TABLE (PREFIX_0F5A
) },
2902 { PREFIX_TABLE (PREFIX_0F5B
) },
2903 { PREFIX_TABLE (PREFIX_0F5C
) },
2904 { PREFIX_TABLE (PREFIX_0F5D
) },
2905 { PREFIX_TABLE (PREFIX_0F5E
) },
2906 { PREFIX_TABLE (PREFIX_0F5F
) },
2908 { PREFIX_TABLE (PREFIX_0F60
) },
2909 { PREFIX_TABLE (PREFIX_0F61
) },
2910 { PREFIX_TABLE (PREFIX_0F62
) },
2911 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2912 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2913 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2914 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2915 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2917 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2918 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2919 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2920 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2921 { PREFIX_TABLE (PREFIX_0F6C
) },
2922 { PREFIX_TABLE (PREFIX_0F6D
) },
2923 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2924 { PREFIX_TABLE (PREFIX_0F6F
) },
2926 { PREFIX_TABLE (PREFIX_0F70
) },
2927 { REG_TABLE (REG_0F71
) },
2928 { REG_TABLE (REG_0F72
) },
2929 { REG_TABLE (REG_0F73
) },
2930 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2931 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2932 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2933 { "emms", { XX
}, PREFIX_OPCODE
},
2935 { PREFIX_TABLE (PREFIX_0F78
) },
2936 { PREFIX_TABLE (PREFIX_0F79
) },
2937 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2939 { PREFIX_TABLE (PREFIX_0F7C
) },
2940 { PREFIX_TABLE (PREFIX_0F7D
) },
2941 { PREFIX_TABLE (PREFIX_0F7E
) },
2942 { PREFIX_TABLE (PREFIX_0F7F
) },
2944 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2945 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2946 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2947 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2948 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2949 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2950 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2951 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2953 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2954 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2955 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2956 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2957 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2958 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2959 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2960 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2962 { "seto", { Eb
}, 0 },
2963 { "setno", { Eb
}, 0 },
2964 { "setb", { Eb
}, 0 },
2965 { "setae", { Eb
}, 0 },
2966 { "sete", { Eb
}, 0 },
2967 { "setne", { Eb
}, 0 },
2968 { "setbe", { Eb
}, 0 },
2969 { "seta", { Eb
}, 0 },
2971 { "sets", { Eb
}, 0 },
2972 { "setns", { Eb
}, 0 },
2973 { "setp", { Eb
}, 0 },
2974 { "setnp", { Eb
}, 0 },
2975 { "setl", { Eb
}, 0 },
2976 { "setge", { Eb
}, 0 },
2977 { "setle", { Eb
}, 0 },
2978 { "setg", { Eb
}, 0 },
2980 { "pushT", { fs
}, 0 },
2981 { "popT", { fs
}, 0 },
2982 { "cpuid", { XX
}, 0 },
2983 { "btS", { Ev
, Gv
}, 0 },
2984 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2985 { "shldS", { Ev
, Gv
, CL
}, 0 },
2986 { REG_TABLE (REG_0FA6
) },
2987 { REG_TABLE (REG_0FA7
) },
2989 { "pushT", { gs
}, 0 },
2990 { "popT", { gs
}, 0 },
2991 { "rsm", { XX
}, 0 },
2992 { "btsS", { Evh1
, Gv
}, 0 },
2993 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2994 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2995 { REG_TABLE (REG_0FAE
) },
2996 { "imulS", { Gv
, Ev
}, 0 },
2998 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2999 { "cmpxchgS", { Evh1
, Gv
}, 0 },
3000 { MOD_TABLE (MOD_0FB2
) },
3001 { "btrS", { Evh1
, Gv
}, 0 },
3002 { MOD_TABLE (MOD_0FB4
) },
3003 { MOD_TABLE (MOD_0FB5
) },
3004 { "movz{bR|x}", { Gv
, Eb
}, 0 },
3005 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
3007 { PREFIX_TABLE (PREFIX_0FB8
) },
3008 { "ud1", { XX
}, 0 },
3009 { REG_TABLE (REG_0FBA
) },
3010 { "btcS", { Evh1
, Gv
}, 0 },
3011 { PREFIX_TABLE (PREFIX_0FBC
) },
3012 { PREFIX_TABLE (PREFIX_0FBD
) },
3013 { "movs{bR|x}", { Gv
, Eb
}, 0 },
3014 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
3016 { "xaddB", { Ebh1
, Gb
}, 0 },
3017 { "xaddS", { Evh1
, Gv
}, 0 },
3018 { PREFIX_TABLE (PREFIX_0FC2
) },
3019 { MOD_TABLE (MOD_0FC3
) },
3020 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
3021 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
3022 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3023 { REG_TABLE (REG_0FC7
) },
3025 { "bswap", { RMeAX
}, 0 },
3026 { "bswap", { RMeCX
}, 0 },
3027 { "bswap", { RMeDX
}, 0 },
3028 { "bswap", { RMeBX
}, 0 },
3029 { "bswap", { RMeSP
}, 0 },
3030 { "bswap", { RMeBP
}, 0 },
3031 { "bswap", { RMeSI
}, 0 },
3032 { "bswap", { RMeDI
}, 0 },
3034 { PREFIX_TABLE (PREFIX_0FD0
) },
3035 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
3036 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
3037 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
3038 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
3039 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
3040 { PREFIX_TABLE (PREFIX_0FD6
) },
3041 { MOD_TABLE (MOD_0FD7
) },
3043 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
3044 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
3045 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
3046 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
3047 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
3048 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
3049 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
3050 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
3052 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
3053 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
3054 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
3055 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
3056 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
3057 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
3058 { PREFIX_TABLE (PREFIX_0FE6
) },
3059 { PREFIX_TABLE (PREFIX_0FE7
) },
3061 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
3062 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
3063 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
3064 { "por", { MX
, EM
}, PREFIX_OPCODE
},
3065 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
3066 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
3067 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
3068 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
3070 { PREFIX_TABLE (PREFIX_0FF0
) },
3071 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
3072 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
3073 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
3074 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
3075 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
3076 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
3077 { PREFIX_TABLE (PREFIX_0FF7
) },
3079 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
3080 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
3081 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
3082 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
3083 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
3084 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
3085 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
3089 static const unsigned char onebyte_has_modrm
[256] = {
3090 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3091 /* ------------------------------- */
3092 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3093 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3094 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3095 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3096 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3097 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3098 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3099 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3100 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3101 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3102 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3103 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3104 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3105 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3106 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3107 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3108 /* ------------------------------- */
3109 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3112 static const unsigned char twobyte_has_modrm
[256] = {
3113 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3114 /* ------------------------------- */
3115 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3116 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3117 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3118 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3119 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3120 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3121 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3122 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3123 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3124 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3125 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3126 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3127 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3128 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3129 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3130 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3131 /* ------------------------------- */
3132 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3135 static char obuf
[100];
3137 static char *mnemonicendp
;
3138 static char scratchbuf
[100];
3139 static unsigned char *start_codep
;
3140 static unsigned char *insn_codep
;
3141 static unsigned char *codep
;
3142 static unsigned char *end_codep
;
3143 static int last_lock_prefix
;
3144 static int last_repz_prefix
;
3145 static int last_repnz_prefix
;
3146 static int last_data_prefix
;
3147 static int last_addr_prefix
;
3148 static int last_rex_prefix
;
3149 static int last_seg_prefix
;
3150 static int fwait_prefix
;
3151 /* The active segment register prefix. */
3152 static int active_seg_prefix
;
3153 #define MAX_CODE_LENGTH 15
3154 /* We can up to 14 prefixes since the maximum instruction length is
3156 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3157 static disassemble_info
*the_info
;
3165 static unsigned char need_modrm
;
3175 int register_specifier
;
3182 int mask_register_specifier
;
3188 static unsigned char need_vex
;
3189 static unsigned char need_vex_reg
;
3190 static unsigned char vex_w_done
;
3198 /* If we are accessing mod/rm/reg without need_modrm set, then the
3199 values are stale. Hitting this abort likely indicates that you
3200 need to update onebyte_has_modrm or twobyte_has_modrm. */
3201 #define MODRM_CHECK if (!need_modrm) abort ()
3203 static const char **names64
;
3204 static const char **names32
;
3205 static const char **names16
;
3206 static const char **names8
;
3207 static const char **names8rex
;
3208 static const char **names_seg
;
3209 static const char *index64
;
3210 static const char *index32
;
3211 static const char **index16
;
3212 static const char **names_bnd
;
3214 static const char *intel_names64
[] = {
3215 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3216 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3218 static const char *intel_names32
[] = {
3219 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3220 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3222 static const char *intel_names16
[] = {
3223 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3224 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3226 static const char *intel_names8
[] = {
3227 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3229 static const char *intel_names8rex
[] = {
3230 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3231 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3233 static const char *intel_names_seg
[] = {
3234 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3236 static const char *intel_index64
= "riz";
3237 static const char *intel_index32
= "eiz";
3238 static const char *intel_index16
[] = {
3239 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3242 static const char *att_names64
[] = {
3243 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3244 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3246 static const char *att_names32
[] = {
3247 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3248 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3250 static const char *att_names16
[] = {
3251 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3252 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3254 static const char *att_names8
[] = {
3255 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3257 static const char *att_names8rex
[] = {
3258 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3259 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3261 static const char *att_names_seg
[] = {
3262 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3264 static const char *att_index64
= "%riz";
3265 static const char *att_index32
= "%eiz";
3266 static const char *att_index16
[] = {
3267 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3270 static const char **names_mm
;
3271 static const char *intel_names_mm
[] = {
3272 "mm0", "mm1", "mm2", "mm3",
3273 "mm4", "mm5", "mm6", "mm7"
3275 static const char *att_names_mm
[] = {
3276 "%mm0", "%mm1", "%mm2", "%mm3",
3277 "%mm4", "%mm5", "%mm6", "%mm7"
3280 static const char *intel_names_bnd
[] = {
3281 "bnd0", "bnd1", "bnd2", "bnd3"
3284 static const char *att_names_bnd
[] = {
3285 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3288 static const char **names_xmm
;
3289 static const char *intel_names_xmm
[] = {
3290 "xmm0", "xmm1", "xmm2", "xmm3",
3291 "xmm4", "xmm5", "xmm6", "xmm7",
3292 "xmm8", "xmm9", "xmm10", "xmm11",
3293 "xmm12", "xmm13", "xmm14", "xmm15",
3294 "xmm16", "xmm17", "xmm18", "xmm19",
3295 "xmm20", "xmm21", "xmm22", "xmm23",
3296 "xmm24", "xmm25", "xmm26", "xmm27",
3297 "xmm28", "xmm29", "xmm30", "xmm31"
3299 static const char *att_names_xmm
[] = {
3300 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3301 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3302 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3303 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3304 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3305 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3306 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3307 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3310 static const char **names_ymm
;
3311 static const char *intel_names_ymm
[] = {
3312 "ymm0", "ymm1", "ymm2", "ymm3",
3313 "ymm4", "ymm5", "ymm6", "ymm7",
3314 "ymm8", "ymm9", "ymm10", "ymm11",
3315 "ymm12", "ymm13", "ymm14", "ymm15",
3316 "ymm16", "ymm17", "ymm18", "ymm19",
3317 "ymm20", "ymm21", "ymm22", "ymm23",
3318 "ymm24", "ymm25", "ymm26", "ymm27",
3319 "ymm28", "ymm29", "ymm30", "ymm31"
3321 static const char *att_names_ymm
[] = {
3322 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3323 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3324 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3325 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3326 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3327 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3328 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3329 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3332 static const char **names_zmm
;
3333 static const char *intel_names_zmm
[] = {
3334 "zmm0", "zmm1", "zmm2", "zmm3",
3335 "zmm4", "zmm5", "zmm6", "zmm7",
3336 "zmm8", "zmm9", "zmm10", "zmm11",
3337 "zmm12", "zmm13", "zmm14", "zmm15",
3338 "zmm16", "zmm17", "zmm18", "zmm19",
3339 "zmm20", "zmm21", "zmm22", "zmm23",
3340 "zmm24", "zmm25", "zmm26", "zmm27",
3341 "zmm28", "zmm29", "zmm30", "zmm31"
3343 static const char *att_names_zmm
[] = {
3344 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3345 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3346 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3347 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3348 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3349 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3350 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3351 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3354 static const char **names_mask
;
3355 static const char *intel_names_mask
[] = {
3356 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3358 static const char *att_names_mask
[] = {
3359 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3362 static const char *names_rounding
[] =
3370 static const struct dis386 reg_table
[][8] = {
3373 { "addA", { Ebh1
, Ib
}, 0 },
3374 { "orA", { Ebh1
, Ib
}, 0 },
3375 { "adcA", { Ebh1
, Ib
}, 0 },
3376 { "sbbA", { Ebh1
, Ib
}, 0 },
3377 { "andA", { Ebh1
, Ib
}, 0 },
3378 { "subA", { Ebh1
, Ib
}, 0 },
3379 { "xorA", { Ebh1
, Ib
}, 0 },
3380 { "cmpA", { Eb
, Ib
}, 0 },
3384 { "addQ", { Evh1
, Iv
}, 0 },
3385 { "orQ", { Evh1
, Iv
}, 0 },
3386 { "adcQ", { Evh1
, Iv
}, 0 },
3387 { "sbbQ", { Evh1
, Iv
}, 0 },
3388 { "andQ", { Evh1
, Iv
}, 0 },
3389 { "subQ", { Evh1
, Iv
}, 0 },
3390 { "xorQ", { Evh1
, Iv
}, 0 },
3391 { "cmpQ", { Ev
, Iv
}, 0 },
3395 { "addQ", { Evh1
, sIb
}, 0 },
3396 { "orQ", { Evh1
, sIb
}, 0 },
3397 { "adcQ", { Evh1
, sIb
}, 0 },
3398 { "sbbQ", { Evh1
, sIb
}, 0 },
3399 { "andQ", { Evh1
, sIb
}, 0 },
3400 { "subQ", { Evh1
, sIb
}, 0 },
3401 { "xorQ", { Evh1
, sIb
}, 0 },
3402 { "cmpQ", { Ev
, sIb
}, 0 },
3406 { "popU", { stackEv
}, 0 },
3407 { XOP_8F_TABLE (XOP_09
) },
3411 { XOP_8F_TABLE (XOP_09
) },
3415 { "rolA", { Eb
, Ib
}, 0 },
3416 { "rorA", { Eb
, Ib
}, 0 },
3417 { "rclA", { Eb
, Ib
}, 0 },
3418 { "rcrA", { Eb
, Ib
}, 0 },
3419 { "shlA", { Eb
, Ib
}, 0 },
3420 { "shrA", { Eb
, Ib
}, 0 },
3422 { "sarA", { Eb
, Ib
}, 0 },
3426 { "rolQ", { Ev
, Ib
}, 0 },
3427 { "rorQ", { Ev
, Ib
}, 0 },
3428 { "rclQ", { Ev
, Ib
}, 0 },
3429 { "rcrQ", { Ev
, Ib
}, 0 },
3430 { "shlQ", { Ev
, Ib
}, 0 },
3431 { "shrQ", { Ev
, Ib
}, 0 },
3433 { "sarQ", { Ev
, Ib
}, 0 },
3437 { "movA", { Ebh3
, Ib
}, 0 },
3444 { MOD_TABLE (MOD_C6_REG_7
) },
3448 { "movQ", { Evh3
, Iv
}, 0 },
3455 { MOD_TABLE (MOD_C7_REG_7
) },
3459 { "rolA", { Eb
, I1
}, 0 },
3460 { "rorA", { Eb
, I1
}, 0 },
3461 { "rclA", { Eb
, I1
}, 0 },
3462 { "rcrA", { Eb
, I1
}, 0 },
3463 { "shlA", { Eb
, I1
}, 0 },
3464 { "shrA", { Eb
, I1
}, 0 },
3466 { "sarA", { Eb
, I1
}, 0 },
3470 { "rolQ", { Ev
, I1
}, 0 },
3471 { "rorQ", { Ev
, I1
}, 0 },
3472 { "rclQ", { Ev
, I1
}, 0 },
3473 { "rcrQ", { Ev
, I1
}, 0 },
3474 { "shlQ", { Ev
, I1
}, 0 },
3475 { "shrQ", { Ev
, I1
}, 0 },
3477 { "sarQ", { Ev
, I1
}, 0 },
3481 { "rolA", { Eb
, CL
}, 0 },
3482 { "rorA", { Eb
, CL
}, 0 },
3483 { "rclA", { Eb
, CL
}, 0 },
3484 { "rcrA", { Eb
, CL
}, 0 },
3485 { "shlA", { Eb
, CL
}, 0 },
3486 { "shrA", { Eb
, CL
}, 0 },
3488 { "sarA", { Eb
, CL
}, 0 },
3492 { "rolQ", { Ev
, CL
}, 0 },
3493 { "rorQ", { Ev
, CL
}, 0 },
3494 { "rclQ", { Ev
, CL
}, 0 },
3495 { "rcrQ", { Ev
, CL
}, 0 },
3496 { "shlQ", { Ev
, CL
}, 0 },
3497 { "shrQ", { Ev
, CL
}, 0 },
3499 { "sarQ", { Ev
, CL
}, 0 },
3503 { "testA", { Eb
, Ib
}, 0 },
3505 { "notA", { Ebh1
}, 0 },
3506 { "negA", { Ebh1
}, 0 },
3507 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3508 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3509 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3510 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3514 { "testQ", { Ev
, Iv
}, 0 },
3516 { "notQ", { Evh1
}, 0 },
3517 { "negQ", { Evh1
}, 0 },
3518 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3519 { "imulQ", { Ev
}, 0 },
3520 { "divQ", { Ev
}, 0 },
3521 { "idivQ", { Ev
}, 0 },
3525 { "incA", { Ebh1
}, 0 },
3526 { "decA", { Ebh1
}, 0 },
3530 { "incQ", { Evh1
}, 0 },
3531 { "decQ", { Evh1
}, 0 },
3532 { "call{T|}", { indirEv
, BND
}, 0 },
3533 { MOD_TABLE (MOD_FF_REG_3
) },
3534 { "jmp{T|}", { indirEv
, BND
}, 0 },
3535 { MOD_TABLE (MOD_FF_REG_5
) },
3536 { "pushU", { stackEv
}, 0 },
3541 { "sldtD", { Sv
}, 0 },
3542 { "strD", { Sv
}, 0 },
3543 { "lldt", { Ew
}, 0 },
3544 { "ltr", { Ew
}, 0 },
3545 { "verr", { Ew
}, 0 },
3546 { "verw", { Ew
}, 0 },
3552 { MOD_TABLE (MOD_0F01_REG_0
) },
3553 { MOD_TABLE (MOD_0F01_REG_1
) },
3554 { MOD_TABLE (MOD_0F01_REG_2
) },
3555 { MOD_TABLE (MOD_0F01_REG_3
) },
3556 { "smswD", { Sv
}, 0 },
3558 { "lmsw", { Ew
}, 0 },
3559 { MOD_TABLE (MOD_0F01_REG_7
) },
3563 { "prefetch", { Mb
}, 0 },
3564 { "prefetchw", { Mb
}, 0 },
3565 { "prefetchwt1", { Mb
}, 0 },
3566 { "prefetch", { Mb
}, 0 },
3567 { "prefetch", { Mb
}, 0 },
3568 { "prefetch", { Mb
}, 0 },
3569 { "prefetch", { Mb
}, 0 },
3570 { "prefetch", { Mb
}, 0 },
3574 { MOD_TABLE (MOD_0F18_REG_0
) },
3575 { MOD_TABLE (MOD_0F18_REG_1
) },
3576 { MOD_TABLE (MOD_0F18_REG_2
) },
3577 { MOD_TABLE (MOD_0F18_REG_3
) },
3578 { MOD_TABLE (MOD_0F18_REG_4
) },
3579 { MOD_TABLE (MOD_0F18_REG_5
) },
3580 { MOD_TABLE (MOD_0F18_REG_6
) },
3581 { MOD_TABLE (MOD_0F18_REG_7
) },
3587 { MOD_TABLE (MOD_0F71_REG_2
) },
3589 { MOD_TABLE (MOD_0F71_REG_4
) },
3591 { MOD_TABLE (MOD_0F71_REG_6
) },
3597 { MOD_TABLE (MOD_0F72_REG_2
) },
3599 { MOD_TABLE (MOD_0F72_REG_4
) },
3601 { MOD_TABLE (MOD_0F72_REG_6
) },
3607 { MOD_TABLE (MOD_0F73_REG_2
) },
3608 { MOD_TABLE (MOD_0F73_REG_3
) },
3611 { MOD_TABLE (MOD_0F73_REG_6
) },
3612 { MOD_TABLE (MOD_0F73_REG_7
) },
3616 { "montmul", { { OP_0f07
, 0 } }, 0 },
3617 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3618 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3622 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3623 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3624 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3625 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3626 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3627 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3631 { MOD_TABLE (MOD_0FAE_REG_0
) },
3632 { MOD_TABLE (MOD_0FAE_REG_1
) },
3633 { MOD_TABLE (MOD_0FAE_REG_2
) },
3634 { MOD_TABLE (MOD_0FAE_REG_3
) },
3635 { MOD_TABLE (MOD_0FAE_REG_4
) },
3636 { MOD_TABLE (MOD_0FAE_REG_5
) },
3637 { MOD_TABLE (MOD_0FAE_REG_6
) },
3638 { MOD_TABLE (MOD_0FAE_REG_7
) },
3646 { "btQ", { Ev
, Ib
}, 0 },
3647 { "btsQ", { Evh1
, Ib
}, 0 },
3648 { "btrQ", { Evh1
, Ib
}, 0 },
3649 { "btcQ", { Evh1
, Ib
}, 0 },
3654 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3656 { MOD_TABLE (MOD_0FC7_REG_3
) },
3657 { MOD_TABLE (MOD_0FC7_REG_4
) },
3658 { MOD_TABLE (MOD_0FC7_REG_5
) },
3659 { MOD_TABLE (MOD_0FC7_REG_6
) },
3660 { MOD_TABLE (MOD_0FC7_REG_7
) },
3666 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3668 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3670 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3676 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3678 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3680 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3686 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3687 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3690 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3691 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3697 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3698 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3700 /* REG_VEX_0F38F3 */
3703 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3704 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3705 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3709 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3710 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3714 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3715 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3717 /* REG_XOP_TBM_01 */
3720 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3721 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3722 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3723 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3724 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3725 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3726 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3728 /* REG_XOP_TBM_02 */
3731 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3736 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3738 #define NEED_REG_TABLE
3739 #include "i386-dis-evex.h"
3740 #undef NEED_REG_TABLE
3743 static const struct dis386 prefix_table
[][4] = {
3746 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3747 { "pause", { XX
}, 0 },
3748 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3749 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3754 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3755 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3756 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3757 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3762 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3763 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3764 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3765 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3770 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3771 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3772 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3773 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3778 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3779 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3780 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3785 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3786 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3787 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3788 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3793 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3794 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3795 { "bndmov", { Ebnd
, Gbnd
}, 0 },
3796 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3801 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3802 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_OPCODE
},
3803 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3804 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3809 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3810 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3811 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3812 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3817 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3818 { "cvttss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3819 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3820 { "cvttsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3825 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3826 { "cvtss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3827 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3828 { "cvtsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3833 { "ucomiss",{ XM
, EXd
}, 0 },
3835 { "ucomisd",{ XM
, EXq
}, 0 },
3840 { "comiss", { XM
, EXd
}, 0 },
3842 { "comisd", { XM
, EXq
}, 0 },
3847 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3848 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3849 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3850 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3855 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3856 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3861 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3862 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3867 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3868 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3869 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3870 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3875 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3876 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3877 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3878 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3883 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3884 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3885 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3886 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3891 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3892 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3893 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3898 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3899 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3900 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3901 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3906 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3907 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3908 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3909 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3914 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3915 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3916 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3917 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3922 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3923 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3924 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3925 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3930 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3932 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3937 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3939 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3944 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3946 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3953 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3960 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3965 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3966 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3967 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3972 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3973 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3974 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3975 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3978 /* PREFIX_0F73_REG_3 */
3982 { "psrldq", { XS
, Ib
}, 0 },
3985 /* PREFIX_0F73_REG_7 */
3989 { "pslldq", { XS
, Ib
}, 0 },
3994 {"vmread", { Em
, Gm
}, 0 },
3996 {"extrq", { XS
, Ib
, Ib
}, 0 },
3997 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
4002 {"vmwrite", { Gm
, Em
}, 0 },
4004 {"extrq", { XM
, XS
}, 0 },
4005 {"insertq", { XM
, XS
}, 0 },
4012 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
4013 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
4020 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
4021 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
4026 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
4027 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
4028 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
4033 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
4034 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
4035 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
4038 /* PREFIX_0FAE_REG_0 */
4041 { "rdfsbase", { Ev
}, 0 },
4044 /* PREFIX_0FAE_REG_1 */
4047 { "rdgsbase", { Ev
}, 0 },
4050 /* PREFIX_0FAE_REG_2 */
4053 { "wrfsbase", { Ev
}, 0 },
4056 /* PREFIX_0FAE_REG_3 */
4059 { "wrgsbase", { Ev
}, 0 },
4062 /* PREFIX_0FAE_REG_6 */
4064 { "xsaveopt", { FXSAVE
}, 0 },
4066 { "clwb", { Mb
}, 0 },
4069 /* PREFIX_0FAE_REG_7 */
4071 { "clflush", { Mb
}, 0 },
4073 { "clflushopt", { Mb
}, 0 },
4076 /* PREFIX_RM_0_0FAE_REG_7 */
4078 { "sfence", { Skip_MODRM
}, 0 },
4080 { "pcommit", { Skip_MODRM
}, 0 },
4086 { "popcntS", { Gv
, Ev
}, 0 },
4091 { "bsfS", { Gv
, Ev
}, 0 },
4092 { "tzcntS", { Gv
, Ev
}, 0 },
4093 { "bsfS", { Gv
, Ev
}, 0 },
4098 { "bsrS", { Gv
, Ev
}, 0 },
4099 { "lzcntS", { Gv
, Ev
}, 0 },
4100 { "bsrS", { Gv
, Ev
}, 0 },
4105 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4106 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4107 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4108 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4111 /* PREFIX_MOD_0_0FC3 */
4113 { "movntiS", { Ev
, Gv
}, PREFIX_OPCODE
},
4116 /* PREFIX_MOD_0_0FC7_REG_6 */
4118 { "vmptrld",{ Mq
}, 0 },
4119 { "vmxon", { Mq
}, 0 },
4120 { "vmclear",{ Mq
}, 0 },
4123 /* PREFIX_MOD_3_0FC7_REG_6 */
4125 { "rdrand", { Ev
}, 0 },
4127 { "rdrand", { Ev
}, 0 }
4130 /* PREFIX_MOD_3_0FC7_REG_7 */
4132 { "rdseed", { Ev
}, 0 },
4134 { "rdseed", { Ev
}, 0 },
4141 { "addsubpd", { XM
, EXx
}, 0 },
4142 { "addsubps", { XM
, EXx
}, 0 },
4148 { "movq2dq",{ XM
, MS
}, 0 },
4149 { "movq", { EXqS
, XM
}, 0 },
4150 { "movdq2q",{ MX
, XS
}, 0 },
4156 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4157 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4158 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4163 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4165 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4173 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4178 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4180 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4187 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4194 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4201 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4208 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4215 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4222 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4229 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4236 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4243 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4250 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4257 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4264 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4271 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4278 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4285 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4292 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4299 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4306 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4313 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4320 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4327 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4334 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4341 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4348 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4355 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4362 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4369 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4376 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4383 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4390 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4397 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4404 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4411 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4418 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4423 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4428 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4433 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4438 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4443 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4448 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4455 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4462 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4469 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4476 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4483 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4488 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4490 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4491 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4496 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4498 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4499 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4505 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4506 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4514 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4521 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4528 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4535 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4542 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4549 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4556 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4563 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4570 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4577 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4584 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4591 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4598 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4605 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4612 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4619 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4626 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4633 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4640 { "pcmpestrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4647 { "pcmpestri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4654 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4661 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4666 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4673 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4676 /* PREFIX_VEX_0F10 */
4678 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4679 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4680 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4681 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4684 /* PREFIX_VEX_0F11 */
4686 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4687 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4688 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4689 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4692 /* PREFIX_VEX_0F12 */
4694 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4695 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4696 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4697 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4700 /* PREFIX_VEX_0F16 */
4702 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4703 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4704 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4707 /* PREFIX_VEX_0F2A */
4710 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4712 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4715 /* PREFIX_VEX_0F2C */
4718 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4720 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4723 /* PREFIX_VEX_0F2D */
4726 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4728 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4731 /* PREFIX_VEX_0F2E */
4733 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4735 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4738 /* PREFIX_VEX_0F2F */
4740 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4742 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4745 /* PREFIX_VEX_0F41 */
4747 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4749 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4752 /* PREFIX_VEX_0F42 */
4754 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4756 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4759 /* PREFIX_VEX_0F44 */
4761 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4763 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4766 /* PREFIX_VEX_0F45 */
4768 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4770 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4773 /* PREFIX_VEX_0F46 */
4775 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4777 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4780 /* PREFIX_VEX_0F47 */
4782 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4784 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4787 /* PREFIX_VEX_0F4A */
4789 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4791 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4794 /* PREFIX_VEX_0F4B */
4796 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4798 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4801 /* PREFIX_VEX_0F51 */
4803 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4804 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4805 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4806 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4809 /* PREFIX_VEX_0F52 */
4811 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4812 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
4815 /* PREFIX_VEX_0F53 */
4817 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
4818 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
4821 /* PREFIX_VEX_0F58 */
4823 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
4824 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
4825 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
4826 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
4829 /* PREFIX_VEX_0F59 */
4831 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
4832 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
4833 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
4834 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
4837 /* PREFIX_VEX_0F5A */
4839 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
4840 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
4841 { "vcvtpd2ps%XY", { XMM
, EXx
}, 0 },
4842 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
4845 /* PREFIX_VEX_0F5B */
4847 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
4848 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
4849 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
4852 /* PREFIX_VEX_0F5C */
4854 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
4855 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
4856 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
4857 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
4860 /* PREFIX_VEX_0F5D */
4862 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
4863 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
4864 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
4865 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
4868 /* PREFIX_VEX_0F5E */
4870 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
4871 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
4872 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
4873 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
4876 /* PREFIX_VEX_0F5F */
4878 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
4879 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
4880 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
4881 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
4884 /* PREFIX_VEX_0F60 */
4888 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
4891 /* PREFIX_VEX_0F61 */
4895 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
4898 /* PREFIX_VEX_0F62 */
4902 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
4905 /* PREFIX_VEX_0F63 */
4909 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
4912 /* PREFIX_VEX_0F64 */
4916 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
4919 /* PREFIX_VEX_0F65 */
4923 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
4926 /* PREFIX_VEX_0F66 */
4930 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
4933 /* PREFIX_VEX_0F67 */
4937 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
4940 /* PREFIX_VEX_0F68 */
4944 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
4947 /* PREFIX_VEX_0F69 */
4951 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
4954 /* PREFIX_VEX_0F6A */
4958 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
4961 /* PREFIX_VEX_0F6B */
4965 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
4968 /* PREFIX_VEX_0F6C */
4972 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
4975 /* PREFIX_VEX_0F6D */
4979 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
4982 /* PREFIX_VEX_0F6E */
4986 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4989 /* PREFIX_VEX_0F6F */
4992 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
4993 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
4996 /* PREFIX_VEX_0F70 */
4999 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
5000 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
5001 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
5004 /* PREFIX_VEX_0F71_REG_2 */
5008 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
5011 /* PREFIX_VEX_0F71_REG_4 */
5015 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
5018 /* PREFIX_VEX_0F71_REG_6 */
5022 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
5025 /* PREFIX_VEX_0F72_REG_2 */
5029 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
5032 /* PREFIX_VEX_0F72_REG_4 */
5036 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
5039 /* PREFIX_VEX_0F72_REG_6 */
5043 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
5046 /* PREFIX_VEX_0F73_REG_2 */
5050 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
5053 /* PREFIX_VEX_0F73_REG_3 */
5057 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
5060 /* PREFIX_VEX_0F73_REG_6 */
5064 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
5067 /* PREFIX_VEX_0F73_REG_7 */
5071 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
5074 /* PREFIX_VEX_0F74 */
5078 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
5081 /* PREFIX_VEX_0F75 */
5085 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
5088 /* PREFIX_VEX_0F76 */
5092 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
5095 /* PREFIX_VEX_0F77 */
5097 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
5100 /* PREFIX_VEX_0F7C */
5104 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
5105 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
5108 /* PREFIX_VEX_0F7D */
5112 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
5113 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
5116 /* PREFIX_VEX_0F7E */
5119 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5120 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5123 /* PREFIX_VEX_0F7F */
5126 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
5127 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
5130 /* PREFIX_VEX_0F90 */
5132 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5134 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5137 /* PREFIX_VEX_0F91 */
5139 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5141 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5144 /* PREFIX_VEX_0F92 */
5146 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5148 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5149 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5152 /* PREFIX_VEX_0F93 */
5154 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5156 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5157 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5160 /* PREFIX_VEX_0F98 */
5162 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5164 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5167 /* PREFIX_VEX_0F99 */
5169 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5171 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5174 /* PREFIX_VEX_0FC2 */
5176 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
5177 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
5178 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
5179 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
5182 /* PREFIX_VEX_0FC4 */
5186 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5189 /* PREFIX_VEX_0FC5 */
5193 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5196 /* PREFIX_VEX_0FD0 */
5200 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
5201 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
5204 /* PREFIX_VEX_0FD1 */
5208 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
5211 /* PREFIX_VEX_0FD2 */
5215 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
5218 /* PREFIX_VEX_0FD3 */
5222 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
5225 /* PREFIX_VEX_0FD4 */
5229 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
5232 /* PREFIX_VEX_0FD5 */
5236 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
5239 /* PREFIX_VEX_0FD6 */
5243 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5246 /* PREFIX_VEX_0FD7 */
5250 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5253 /* PREFIX_VEX_0FD8 */
5257 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
5260 /* PREFIX_VEX_0FD9 */
5264 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
5267 /* PREFIX_VEX_0FDA */
5271 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
5274 /* PREFIX_VEX_0FDB */
5278 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
5281 /* PREFIX_VEX_0FDC */
5285 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
5288 /* PREFIX_VEX_0FDD */
5292 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
5295 /* PREFIX_VEX_0FDE */
5299 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
5302 /* PREFIX_VEX_0FDF */
5306 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
5309 /* PREFIX_VEX_0FE0 */
5313 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
5316 /* PREFIX_VEX_0FE1 */
5320 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
5323 /* PREFIX_VEX_0FE2 */
5327 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
5330 /* PREFIX_VEX_0FE3 */
5334 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
5337 /* PREFIX_VEX_0FE4 */
5341 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
5344 /* PREFIX_VEX_0FE5 */
5348 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
5351 /* PREFIX_VEX_0FE6 */
5354 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
5355 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
5356 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5359 /* PREFIX_VEX_0FE7 */
5363 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5366 /* PREFIX_VEX_0FE8 */
5370 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5373 /* PREFIX_VEX_0FE9 */
5377 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5380 /* PREFIX_VEX_0FEA */
5384 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5387 /* PREFIX_VEX_0FEB */
5391 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5394 /* PREFIX_VEX_0FEC */
5398 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5401 /* PREFIX_VEX_0FED */
5405 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5408 /* PREFIX_VEX_0FEE */
5412 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5415 /* PREFIX_VEX_0FEF */
5419 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5422 /* PREFIX_VEX_0FF0 */
5427 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5430 /* PREFIX_VEX_0FF1 */
5434 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5437 /* PREFIX_VEX_0FF2 */
5441 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5444 /* PREFIX_VEX_0FF3 */
5448 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5451 /* PREFIX_VEX_0FF4 */
5455 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5458 /* PREFIX_VEX_0FF5 */
5462 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5465 /* PREFIX_VEX_0FF6 */
5469 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5472 /* PREFIX_VEX_0FF7 */
5476 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5479 /* PREFIX_VEX_0FF8 */
5483 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5486 /* PREFIX_VEX_0FF9 */
5490 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5493 /* PREFIX_VEX_0FFA */
5497 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5500 /* PREFIX_VEX_0FFB */
5504 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5507 /* PREFIX_VEX_0FFC */
5511 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5514 /* PREFIX_VEX_0FFD */
5518 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5521 /* PREFIX_VEX_0FFE */
5525 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5528 /* PREFIX_VEX_0F3800 */
5532 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5535 /* PREFIX_VEX_0F3801 */
5539 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5542 /* PREFIX_VEX_0F3802 */
5546 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5549 /* PREFIX_VEX_0F3803 */
5553 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5556 /* PREFIX_VEX_0F3804 */
5560 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5563 /* PREFIX_VEX_0F3805 */
5567 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5570 /* PREFIX_VEX_0F3806 */
5574 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5577 /* PREFIX_VEX_0F3807 */
5581 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5584 /* PREFIX_VEX_0F3808 */
5588 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5591 /* PREFIX_VEX_0F3809 */
5595 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5598 /* PREFIX_VEX_0F380A */
5602 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5605 /* PREFIX_VEX_0F380B */
5609 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5612 /* PREFIX_VEX_0F380C */
5616 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5619 /* PREFIX_VEX_0F380D */
5623 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5626 /* PREFIX_VEX_0F380E */
5630 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5633 /* PREFIX_VEX_0F380F */
5637 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5640 /* PREFIX_VEX_0F3813 */
5644 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5647 /* PREFIX_VEX_0F3816 */
5651 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5654 /* PREFIX_VEX_0F3817 */
5658 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5661 /* PREFIX_VEX_0F3818 */
5665 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5668 /* PREFIX_VEX_0F3819 */
5672 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5675 /* PREFIX_VEX_0F381A */
5679 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5682 /* PREFIX_VEX_0F381C */
5686 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5689 /* PREFIX_VEX_0F381D */
5693 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5696 /* PREFIX_VEX_0F381E */
5700 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5703 /* PREFIX_VEX_0F3820 */
5707 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5710 /* PREFIX_VEX_0F3821 */
5714 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5717 /* PREFIX_VEX_0F3822 */
5721 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5724 /* PREFIX_VEX_0F3823 */
5728 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5731 /* PREFIX_VEX_0F3824 */
5735 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5738 /* PREFIX_VEX_0F3825 */
5742 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5745 /* PREFIX_VEX_0F3828 */
5749 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5752 /* PREFIX_VEX_0F3829 */
5756 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5759 /* PREFIX_VEX_0F382A */
5763 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5766 /* PREFIX_VEX_0F382B */
5770 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5773 /* PREFIX_VEX_0F382C */
5777 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5780 /* PREFIX_VEX_0F382D */
5784 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5787 /* PREFIX_VEX_0F382E */
5791 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5794 /* PREFIX_VEX_0F382F */
5798 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5801 /* PREFIX_VEX_0F3830 */
5805 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5808 /* PREFIX_VEX_0F3831 */
5812 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
5815 /* PREFIX_VEX_0F3832 */
5819 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
5822 /* PREFIX_VEX_0F3833 */
5826 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
5829 /* PREFIX_VEX_0F3834 */
5833 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
5836 /* PREFIX_VEX_0F3835 */
5840 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
5843 /* PREFIX_VEX_0F3836 */
5847 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5850 /* PREFIX_VEX_0F3837 */
5854 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
5857 /* PREFIX_VEX_0F3838 */
5861 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
5864 /* PREFIX_VEX_0F3839 */
5868 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
5871 /* PREFIX_VEX_0F383A */
5875 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
5878 /* PREFIX_VEX_0F383B */
5882 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
5885 /* PREFIX_VEX_0F383C */
5889 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
5892 /* PREFIX_VEX_0F383D */
5896 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
5899 /* PREFIX_VEX_0F383E */
5903 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
5906 /* PREFIX_VEX_0F383F */
5910 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
5913 /* PREFIX_VEX_0F3840 */
5917 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
5920 /* PREFIX_VEX_0F3841 */
5924 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5927 /* PREFIX_VEX_0F3845 */
5931 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5934 /* PREFIX_VEX_0F3846 */
5938 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5941 /* PREFIX_VEX_0F3847 */
5945 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5948 /* PREFIX_VEX_0F3858 */
5952 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5955 /* PREFIX_VEX_0F3859 */
5959 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5962 /* PREFIX_VEX_0F385A */
5966 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5969 /* PREFIX_VEX_0F3878 */
5973 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5976 /* PREFIX_VEX_0F3879 */
5980 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5983 /* PREFIX_VEX_0F388C */
5987 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5990 /* PREFIX_VEX_0F388E */
5994 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5997 /* PREFIX_VEX_0F3890 */
6001 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6004 /* PREFIX_VEX_0F3891 */
6008 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6011 /* PREFIX_VEX_0F3892 */
6015 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6018 /* PREFIX_VEX_0F3893 */
6022 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6025 /* PREFIX_VEX_0F3896 */
6029 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6032 /* PREFIX_VEX_0F3897 */
6036 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6039 /* PREFIX_VEX_0F3898 */
6043 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6046 /* PREFIX_VEX_0F3899 */
6050 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6053 /* PREFIX_VEX_0F389A */
6057 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6060 /* PREFIX_VEX_0F389B */
6064 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6067 /* PREFIX_VEX_0F389C */
6071 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6074 /* PREFIX_VEX_0F389D */
6078 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6081 /* PREFIX_VEX_0F389E */
6085 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6088 /* PREFIX_VEX_0F389F */
6092 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6095 /* PREFIX_VEX_0F38A6 */
6099 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6103 /* PREFIX_VEX_0F38A7 */
6107 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6110 /* PREFIX_VEX_0F38A8 */
6114 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6117 /* PREFIX_VEX_0F38A9 */
6121 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6124 /* PREFIX_VEX_0F38AA */
6128 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6131 /* PREFIX_VEX_0F38AB */
6135 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6138 /* PREFIX_VEX_0F38AC */
6142 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6145 /* PREFIX_VEX_0F38AD */
6149 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6152 /* PREFIX_VEX_0F38AE */
6156 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6159 /* PREFIX_VEX_0F38AF */
6163 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6166 /* PREFIX_VEX_0F38B6 */
6170 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6173 /* PREFIX_VEX_0F38B7 */
6177 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6180 /* PREFIX_VEX_0F38B8 */
6184 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6187 /* PREFIX_VEX_0F38B9 */
6191 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6194 /* PREFIX_VEX_0F38BA */
6198 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6201 /* PREFIX_VEX_0F38BB */
6205 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6208 /* PREFIX_VEX_0F38BC */
6212 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6215 /* PREFIX_VEX_0F38BD */
6219 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6222 /* PREFIX_VEX_0F38BE */
6226 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6229 /* PREFIX_VEX_0F38BF */
6233 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6236 /* PREFIX_VEX_0F38DB */
6240 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6243 /* PREFIX_VEX_0F38DC */
6247 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
6250 /* PREFIX_VEX_0F38DD */
6254 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
6257 /* PREFIX_VEX_0F38DE */
6261 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
6264 /* PREFIX_VEX_0F38DF */
6268 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
6271 /* PREFIX_VEX_0F38F2 */
6273 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6276 /* PREFIX_VEX_0F38F3_REG_1 */
6278 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6281 /* PREFIX_VEX_0F38F3_REG_2 */
6283 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6286 /* PREFIX_VEX_0F38F3_REG_3 */
6288 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6291 /* PREFIX_VEX_0F38F5 */
6293 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6294 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6296 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6299 /* PREFIX_VEX_0F38F6 */
6304 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6307 /* PREFIX_VEX_0F38F7 */
6309 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6310 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6311 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6312 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6315 /* PREFIX_VEX_0F3A00 */
6319 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6322 /* PREFIX_VEX_0F3A01 */
6326 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6329 /* PREFIX_VEX_0F3A02 */
6333 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6336 /* PREFIX_VEX_0F3A04 */
6340 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6343 /* PREFIX_VEX_0F3A05 */
6347 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6350 /* PREFIX_VEX_0F3A06 */
6354 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6357 /* PREFIX_VEX_0F3A08 */
6361 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6364 /* PREFIX_VEX_0F3A09 */
6368 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6371 /* PREFIX_VEX_0F3A0A */
6375 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6378 /* PREFIX_VEX_0F3A0B */
6382 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6385 /* PREFIX_VEX_0F3A0C */
6389 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6392 /* PREFIX_VEX_0F3A0D */
6396 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6399 /* PREFIX_VEX_0F3A0E */
6403 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6406 /* PREFIX_VEX_0F3A0F */
6410 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6413 /* PREFIX_VEX_0F3A14 */
6417 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6420 /* PREFIX_VEX_0F3A15 */
6424 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6427 /* PREFIX_VEX_0F3A16 */
6431 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6434 /* PREFIX_VEX_0F3A17 */
6438 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6441 /* PREFIX_VEX_0F3A18 */
6445 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6448 /* PREFIX_VEX_0F3A19 */
6452 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6455 /* PREFIX_VEX_0F3A1D */
6459 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6462 /* PREFIX_VEX_0F3A20 */
6466 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6469 /* PREFIX_VEX_0F3A21 */
6473 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6476 /* PREFIX_VEX_0F3A22 */
6480 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6483 /* PREFIX_VEX_0F3A30 */
6487 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6490 /* PREFIX_VEX_0F3A31 */
6494 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6497 /* PREFIX_VEX_0F3A32 */
6501 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6504 /* PREFIX_VEX_0F3A33 */
6508 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6511 /* PREFIX_VEX_0F3A38 */
6515 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6518 /* PREFIX_VEX_0F3A39 */
6522 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6525 /* PREFIX_VEX_0F3A40 */
6529 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6532 /* PREFIX_VEX_0F3A41 */
6536 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6539 /* PREFIX_VEX_0F3A42 */
6543 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6546 /* PREFIX_VEX_0F3A44 */
6550 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
6553 /* PREFIX_VEX_0F3A46 */
6557 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6560 /* PREFIX_VEX_0F3A48 */
6564 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6567 /* PREFIX_VEX_0F3A49 */
6571 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6574 /* PREFIX_VEX_0F3A4A */
6578 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6581 /* PREFIX_VEX_0F3A4B */
6585 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6588 /* PREFIX_VEX_0F3A4C */
6592 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6595 /* PREFIX_VEX_0F3A5C */
6599 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6602 /* PREFIX_VEX_0F3A5D */
6606 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6609 /* PREFIX_VEX_0F3A5E */
6613 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6616 /* PREFIX_VEX_0F3A5F */
6620 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6623 /* PREFIX_VEX_0F3A60 */
6627 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6631 /* PREFIX_VEX_0F3A61 */
6635 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6638 /* PREFIX_VEX_0F3A62 */
6642 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6645 /* PREFIX_VEX_0F3A63 */
6649 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6652 /* PREFIX_VEX_0F3A68 */
6656 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6659 /* PREFIX_VEX_0F3A69 */
6663 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6666 /* PREFIX_VEX_0F3A6A */
6670 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6673 /* PREFIX_VEX_0F3A6B */
6677 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6680 /* PREFIX_VEX_0F3A6C */
6684 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6687 /* PREFIX_VEX_0F3A6D */
6691 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6694 /* PREFIX_VEX_0F3A6E */
6698 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6701 /* PREFIX_VEX_0F3A6F */
6705 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6708 /* PREFIX_VEX_0F3A78 */
6712 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6715 /* PREFIX_VEX_0F3A79 */
6719 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6722 /* PREFIX_VEX_0F3A7A */
6726 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6729 /* PREFIX_VEX_0F3A7B */
6733 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6736 /* PREFIX_VEX_0F3A7C */
6740 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6744 /* PREFIX_VEX_0F3A7D */
6748 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6751 /* PREFIX_VEX_0F3A7E */
6755 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6758 /* PREFIX_VEX_0F3A7F */
6762 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6765 /* PREFIX_VEX_0F3ADF */
6769 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6772 /* PREFIX_VEX_0F3AF0 */
6777 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6780 #define NEED_PREFIX_TABLE
6781 #include "i386-dis-evex.h"
6782 #undef NEED_PREFIX_TABLE
6785 static const struct dis386 x86_64_table
[][2] = {
6788 { "pushP", { es
}, 0 },
6793 { "popP", { es
}, 0 },
6798 { "pushP", { cs
}, 0 },
6803 { "pushP", { ss
}, 0 },
6808 { "popP", { ss
}, 0 },
6813 { "pushP", { ds
}, 0 },
6818 { "popP", { ds
}, 0 },
6823 { "daa", { XX
}, 0 },
6828 { "das", { XX
}, 0 },
6833 { "aaa", { XX
}, 0 },
6838 { "aas", { XX
}, 0 },
6843 { "pushaP", { XX
}, 0 },
6848 { "popaP", { XX
}, 0 },
6853 { MOD_TABLE (MOD_62_32BIT
) },
6854 { EVEX_TABLE (EVEX_0F
) },
6859 { "arpl", { Ew
, Gw
}, 0 },
6860 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6865 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6866 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6871 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6872 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6877 { "Jcall{T|}", { Ap
}, 0 },
6882 { MOD_TABLE (MOD_C4_32BIT
) },
6883 { VEX_C4_TABLE (VEX_0F
) },
6888 { MOD_TABLE (MOD_C5_32BIT
) },
6889 { VEX_C5_TABLE (VEX_0F
) },
6894 { "into", { XX
}, 0 },
6899 { "aam", { Ib
}, 0 },
6904 { "aad", { Ib
}, 0 },
6909 { "callP", { Jv
, BND
}, 0 },
6910 { "call@", { Jv
, BND
}, 0 }
6915 { "jmpP", { Jv
, BND
}, 0 },
6916 { "jmp@", { Jv
, BND
}, 0 }
6921 { "Jjmp{T|}", { Ap
}, 0 },
6924 /* X86_64_0F01_REG_0 */
6926 { "sgdt{Q|IQ}", { M
}, 0 },
6927 { "sgdt", { M
}, 0 },
6930 /* X86_64_0F01_REG_1 */
6932 { "sidt{Q|IQ}", { M
}, 0 },
6933 { "sidt", { M
}, 0 },
6936 /* X86_64_0F01_REG_2 */
6938 { "lgdt{Q|Q}", { M
}, 0 },
6939 { "lgdt", { M
}, 0 },
6942 /* X86_64_0F01_REG_3 */
6944 { "lidt{Q|Q}", { M
}, 0 },
6945 { "lidt", { M
}, 0 },
6949 static const struct dis386 three_byte_table
[][256] = {
6951 /* THREE_BYTE_0F38 */
6954 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6955 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6956 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6957 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6958 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6959 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6960 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6961 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6963 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6964 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6965 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6966 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6972 { PREFIX_TABLE (PREFIX_0F3810
) },
6976 { PREFIX_TABLE (PREFIX_0F3814
) },
6977 { PREFIX_TABLE (PREFIX_0F3815
) },
6979 { PREFIX_TABLE (PREFIX_0F3817
) },
6985 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
6986 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
6987 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
6990 { PREFIX_TABLE (PREFIX_0F3820
) },
6991 { PREFIX_TABLE (PREFIX_0F3821
) },
6992 { PREFIX_TABLE (PREFIX_0F3822
) },
6993 { PREFIX_TABLE (PREFIX_0F3823
) },
6994 { PREFIX_TABLE (PREFIX_0F3824
) },
6995 { PREFIX_TABLE (PREFIX_0F3825
) },
6999 { PREFIX_TABLE (PREFIX_0F3828
) },
7000 { PREFIX_TABLE (PREFIX_0F3829
) },
7001 { PREFIX_TABLE (PREFIX_0F382A
) },
7002 { PREFIX_TABLE (PREFIX_0F382B
) },
7008 { PREFIX_TABLE (PREFIX_0F3830
) },
7009 { PREFIX_TABLE (PREFIX_0F3831
) },
7010 { PREFIX_TABLE (PREFIX_0F3832
) },
7011 { PREFIX_TABLE (PREFIX_0F3833
) },
7012 { PREFIX_TABLE (PREFIX_0F3834
) },
7013 { PREFIX_TABLE (PREFIX_0F3835
) },
7015 { PREFIX_TABLE (PREFIX_0F3837
) },
7017 { PREFIX_TABLE (PREFIX_0F3838
) },
7018 { PREFIX_TABLE (PREFIX_0F3839
) },
7019 { PREFIX_TABLE (PREFIX_0F383A
) },
7020 { PREFIX_TABLE (PREFIX_0F383B
) },
7021 { PREFIX_TABLE (PREFIX_0F383C
) },
7022 { PREFIX_TABLE (PREFIX_0F383D
) },
7023 { PREFIX_TABLE (PREFIX_0F383E
) },
7024 { PREFIX_TABLE (PREFIX_0F383F
) },
7026 { PREFIX_TABLE (PREFIX_0F3840
) },
7027 { PREFIX_TABLE (PREFIX_0F3841
) },
7098 { PREFIX_TABLE (PREFIX_0F3880
) },
7099 { PREFIX_TABLE (PREFIX_0F3881
) },
7100 { PREFIX_TABLE (PREFIX_0F3882
) },
7179 { PREFIX_TABLE (PREFIX_0F38C8
) },
7180 { PREFIX_TABLE (PREFIX_0F38C9
) },
7181 { PREFIX_TABLE (PREFIX_0F38CA
) },
7182 { PREFIX_TABLE (PREFIX_0F38CB
) },
7183 { PREFIX_TABLE (PREFIX_0F38CC
) },
7184 { PREFIX_TABLE (PREFIX_0F38CD
) },
7200 { PREFIX_TABLE (PREFIX_0F38DB
) },
7201 { PREFIX_TABLE (PREFIX_0F38DC
) },
7202 { PREFIX_TABLE (PREFIX_0F38DD
) },
7203 { PREFIX_TABLE (PREFIX_0F38DE
) },
7204 { PREFIX_TABLE (PREFIX_0F38DF
) },
7224 { PREFIX_TABLE (PREFIX_0F38F0
) },
7225 { PREFIX_TABLE (PREFIX_0F38F1
) },
7230 { PREFIX_TABLE (PREFIX_0F38F6
) },
7242 /* THREE_BYTE_0F3A */
7254 { PREFIX_TABLE (PREFIX_0F3A08
) },
7255 { PREFIX_TABLE (PREFIX_0F3A09
) },
7256 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7257 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7258 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7259 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7260 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7261 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7267 { PREFIX_TABLE (PREFIX_0F3A14
) },
7268 { PREFIX_TABLE (PREFIX_0F3A15
) },
7269 { PREFIX_TABLE (PREFIX_0F3A16
) },
7270 { PREFIX_TABLE (PREFIX_0F3A17
) },
7281 { PREFIX_TABLE (PREFIX_0F3A20
) },
7282 { PREFIX_TABLE (PREFIX_0F3A21
) },
7283 { PREFIX_TABLE (PREFIX_0F3A22
) },
7317 { PREFIX_TABLE (PREFIX_0F3A40
) },
7318 { PREFIX_TABLE (PREFIX_0F3A41
) },
7319 { PREFIX_TABLE (PREFIX_0F3A42
) },
7321 { PREFIX_TABLE (PREFIX_0F3A44
) },
7353 { PREFIX_TABLE (PREFIX_0F3A60
) },
7354 { PREFIX_TABLE (PREFIX_0F3A61
) },
7355 { PREFIX_TABLE (PREFIX_0F3A62
) },
7356 { PREFIX_TABLE (PREFIX_0F3A63
) },
7474 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7495 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7534 /* THREE_BYTE_0F7A */
7573 { "ptest", { XX
}, PREFIX_OPCODE
},
7610 { "phaddbw", { XM
, EXq
}, PREFIX_OPCODE
},
7611 { "phaddbd", { XM
, EXq
}, PREFIX_OPCODE
},
7612 { "phaddbq", { XM
, EXq
}, PREFIX_OPCODE
},
7615 { "phaddwd", { XM
, EXq
}, PREFIX_OPCODE
},
7616 { "phaddwq", { XM
, EXq
}, PREFIX_OPCODE
},
7621 { "phadddq", { XM
, EXq
}, PREFIX_OPCODE
},
7628 { "phaddubw", { XM
, EXq
}, PREFIX_OPCODE
},
7629 { "phaddubd", { XM
, EXq
}, PREFIX_OPCODE
},
7630 { "phaddubq", { XM
, EXq
}, PREFIX_OPCODE
},
7633 { "phadduwd", { XM
, EXq
}, PREFIX_OPCODE
},
7634 { "phadduwq", { XM
, EXq
}, PREFIX_OPCODE
},
7639 { "phaddudq", { XM
, EXq
}, PREFIX_OPCODE
},
7646 { "phsubbw", { XM
, EXq
}, PREFIX_OPCODE
},
7647 { "phsubbd", { XM
, EXq
}, PREFIX_OPCODE
},
7648 { "phsubbq", { XM
, EXq
}, PREFIX_OPCODE
},
7827 static const struct dis386 xop_table
[][256] = {
7980 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7981 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7982 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7990 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7991 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7998 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7999 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8000 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8008 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8009 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8013 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8014 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8017 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8035 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8047 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
8048 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
8049 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
8050 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
8060 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
8061 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
8062 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
8063 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
8096 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
8097 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
8098 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
8099 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
8123 { REG_TABLE (REG_XOP_TBM_01
) },
8124 { REG_TABLE (REG_XOP_TBM_02
) },
8142 { REG_TABLE (REG_XOP_LWPCB
) },
8266 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8267 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8268 { "vfrczss", { XM
, EXd
}, 0 },
8269 { "vfrczsd", { XM
, EXq
}, 0 },
8284 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8285 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8286 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8287 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8288 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8289 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8290 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8291 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8293 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8294 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8295 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8296 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8339 { "vphaddbw", { XM
, EXxmm
}, 0 },
8340 { "vphaddbd", { XM
, EXxmm
}, 0 },
8341 { "vphaddbq", { XM
, EXxmm
}, 0 },
8344 { "vphaddwd", { XM
, EXxmm
}, 0 },
8345 { "vphaddwq", { XM
, EXxmm
}, 0 },
8350 { "vphadddq", { XM
, EXxmm
}, 0 },
8357 { "vphaddubw", { XM
, EXxmm
}, 0 },
8358 { "vphaddubd", { XM
, EXxmm
}, 0 },
8359 { "vphaddubq", { XM
, EXxmm
}, 0 },
8362 { "vphadduwd", { XM
, EXxmm
}, 0 },
8363 { "vphadduwq", { XM
, EXxmm
}, 0 },
8368 { "vphaddudq", { XM
, EXxmm
}, 0 },
8375 { "vphsubbw", { XM
, EXxmm
}, 0 },
8376 { "vphsubwd", { XM
, EXxmm
}, 0 },
8377 { "vphsubdq", { XM
, EXxmm
}, 0 },
8431 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8433 { REG_TABLE (REG_XOP_LWP
) },
8703 static const struct dis386 vex_table
[][256] = {
8725 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8728 { MOD_TABLE (MOD_VEX_0F13
) },
8729 { VEX_W_TABLE (VEX_W_0F14
) },
8730 { VEX_W_TABLE (VEX_W_0F15
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8732 { MOD_TABLE (MOD_VEX_0F17
) },
8752 { VEX_W_TABLE (VEX_W_0F28
) },
8753 { VEX_W_TABLE (VEX_W_0F29
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8755 { MOD_TABLE (MOD_VEX_0F2B
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8797 { MOD_TABLE (MOD_VEX_0F50
) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8801 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8802 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8803 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8804 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8806 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8808 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8809 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8810 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8812 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8813 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8815 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8816 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8817 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8818 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8819 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8820 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8821 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8822 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8824 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8825 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8827 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8828 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8830 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8831 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8833 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8834 { REG_TABLE (REG_VEX_0F71
) },
8835 { REG_TABLE (REG_VEX_0F72
) },
8836 { REG_TABLE (REG_VEX_0F73
) },
8837 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8838 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8839 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8840 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8846 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8847 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8848 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8849 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8870 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8871 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8872 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8878 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8879 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8902 { REG_TABLE (REG_VEX_0FAE
) },
8925 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8927 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8928 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8929 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8941 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8945 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8950 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8951 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8952 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8953 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8954 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8956 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8957 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8959 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8960 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8961 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8962 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8963 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8964 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8965 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8966 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8968 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8969 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8971 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8972 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8973 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8974 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8975 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8978 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8979 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8980 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8981 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8982 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8983 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8984 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8986 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8987 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8988 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8989 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8990 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8991 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8992 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
9008 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
9010 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
9013 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
9031 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
9034 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
9035 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
9036 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
9064 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
9160 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
9161 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
9162 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
9163 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
9166 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
9167 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
9169 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
9170 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
9171 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
9172 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
9173 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
9174 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
9175 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
9176 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
9184 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
9185 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
9187 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
9188 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
9191 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
9193 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
9194 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
9202 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
9203 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
9205 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
9206 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
9207 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
9208 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
9209 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
9210 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
9211 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
9212 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
9244 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9245 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9246 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9247 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9248 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9270 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9271 { REG_TABLE (REG_VEX_0F38F3
) },
9273 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9274 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9275 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9289 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9290 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9291 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9293 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9294 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9295 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9298 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9299 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9300 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9301 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9302 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9303 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9304 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9305 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9311 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9312 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9314 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9316 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9317 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9321 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9325 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9326 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9327 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9343 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9344 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9345 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9346 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9352 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9353 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9361 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9362 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9363 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9365 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9367 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9370 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9371 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9372 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9373 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9374 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9392 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9393 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9394 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9395 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9397 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9398 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9399 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9400 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9406 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9407 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9408 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9409 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9410 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9411 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9412 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9413 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9424 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9425 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9426 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9427 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9428 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9429 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9430 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9431 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9539 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9559 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9579 #define NEED_OPCODE_TABLE
9580 #include "i386-dis-evex.h"
9581 #undef NEED_OPCODE_TABLE
9582 static const struct dis386 vex_len_table
[][2] = {
9583 /* VEX_LEN_0F10_P_1 */
9585 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9586 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9589 /* VEX_LEN_0F10_P_3 */
9591 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9592 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9595 /* VEX_LEN_0F11_P_1 */
9597 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9598 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9601 /* VEX_LEN_0F11_P_3 */
9603 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9604 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9607 /* VEX_LEN_0F12_P_0_M_0 */
9609 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9612 /* VEX_LEN_0F12_P_0_M_1 */
9614 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9617 /* VEX_LEN_0F12_P_2 */
9619 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9622 /* VEX_LEN_0F13_M_0 */
9624 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9627 /* VEX_LEN_0F16_P_0_M_0 */
9629 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9632 /* VEX_LEN_0F16_P_0_M_1 */
9634 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9637 /* VEX_LEN_0F16_P_2 */
9639 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9642 /* VEX_LEN_0F17_M_0 */
9644 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9647 /* VEX_LEN_0F2A_P_1 */
9649 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9650 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9653 /* VEX_LEN_0F2A_P_3 */
9655 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9656 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9659 /* VEX_LEN_0F2C_P_1 */
9661 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9662 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9665 /* VEX_LEN_0F2C_P_3 */
9667 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9668 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9671 /* VEX_LEN_0F2D_P_1 */
9673 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9674 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9677 /* VEX_LEN_0F2D_P_3 */
9679 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9680 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9683 /* VEX_LEN_0F2E_P_0 */
9685 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9686 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9689 /* VEX_LEN_0F2E_P_2 */
9691 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9692 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9695 /* VEX_LEN_0F2F_P_0 */
9697 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9698 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9701 /* VEX_LEN_0F2F_P_2 */
9703 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9704 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9707 /* VEX_LEN_0F41_P_0 */
9710 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9712 /* VEX_LEN_0F41_P_2 */
9715 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9717 /* VEX_LEN_0F42_P_0 */
9720 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9722 /* VEX_LEN_0F42_P_2 */
9725 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9727 /* VEX_LEN_0F44_P_0 */
9729 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9731 /* VEX_LEN_0F44_P_2 */
9733 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9735 /* VEX_LEN_0F45_P_0 */
9738 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9740 /* VEX_LEN_0F45_P_2 */
9743 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9745 /* VEX_LEN_0F46_P_0 */
9748 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9750 /* VEX_LEN_0F46_P_2 */
9753 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9755 /* VEX_LEN_0F47_P_0 */
9758 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9760 /* VEX_LEN_0F47_P_2 */
9763 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9765 /* VEX_LEN_0F4A_P_0 */
9768 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9770 /* VEX_LEN_0F4A_P_2 */
9773 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9775 /* VEX_LEN_0F4B_P_0 */
9778 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9780 /* VEX_LEN_0F4B_P_2 */
9783 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9786 /* VEX_LEN_0F51_P_1 */
9788 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9789 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9792 /* VEX_LEN_0F51_P_3 */
9794 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9795 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9798 /* VEX_LEN_0F52_P_1 */
9800 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9801 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9804 /* VEX_LEN_0F53_P_1 */
9806 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9807 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9810 /* VEX_LEN_0F58_P_1 */
9812 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9813 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9816 /* VEX_LEN_0F58_P_3 */
9818 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9819 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9822 /* VEX_LEN_0F59_P_1 */
9824 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9825 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9828 /* VEX_LEN_0F59_P_3 */
9830 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9831 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9834 /* VEX_LEN_0F5A_P_1 */
9836 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9837 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9840 /* VEX_LEN_0F5A_P_3 */
9842 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9843 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9846 /* VEX_LEN_0F5C_P_1 */
9848 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9849 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9852 /* VEX_LEN_0F5C_P_3 */
9854 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9855 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9858 /* VEX_LEN_0F5D_P_1 */
9860 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9861 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9864 /* VEX_LEN_0F5D_P_3 */
9866 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9867 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9870 /* VEX_LEN_0F5E_P_1 */
9872 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9873 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9876 /* VEX_LEN_0F5E_P_3 */
9878 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9879 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9882 /* VEX_LEN_0F5F_P_1 */
9884 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9885 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9888 /* VEX_LEN_0F5F_P_3 */
9890 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9891 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9894 /* VEX_LEN_0F6E_P_2 */
9896 { "vmovK", { XMScalar
, Edq
}, 0 },
9897 { "vmovK", { XMScalar
, Edq
}, 0 },
9900 /* VEX_LEN_0F7E_P_1 */
9902 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9903 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9906 /* VEX_LEN_0F7E_P_2 */
9908 { "vmovK", { Edq
, XMScalar
}, 0 },
9909 { "vmovK", { Edq
, XMScalar
}, 0 },
9912 /* VEX_LEN_0F90_P_0 */
9914 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9917 /* VEX_LEN_0F90_P_2 */
9919 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9922 /* VEX_LEN_0F91_P_0 */
9924 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9927 /* VEX_LEN_0F91_P_2 */
9929 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9932 /* VEX_LEN_0F92_P_0 */
9934 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9937 /* VEX_LEN_0F92_P_2 */
9939 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9942 /* VEX_LEN_0F92_P_3 */
9944 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9947 /* VEX_LEN_0F93_P_0 */
9949 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9952 /* VEX_LEN_0F93_P_2 */
9954 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9957 /* VEX_LEN_0F93_P_3 */
9959 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9962 /* VEX_LEN_0F98_P_0 */
9964 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9967 /* VEX_LEN_0F98_P_2 */
9969 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9972 /* VEX_LEN_0F99_P_0 */
9974 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9977 /* VEX_LEN_0F99_P_2 */
9979 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9982 /* VEX_LEN_0FAE_R_2_M_0 */
9984 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
9987 /* VEX_LEN_0FAE_R_3_M_0 */
9989 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
9992 /* VEX_LEN_0FC2_P_1 */
9994 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9995 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9998 /* VEX_LEN_0FC2_P_3 */
10000 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
10001 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
10004 /* VEX_LEN_0FC4_P_2 */
10006 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
10009 /* VEX_LEN_0FC5_P_2 */
10011 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
10014 /* VEX_LEN_0FD6_P_2 */
10016 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
10017 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
10020 /* VEX_LEN_0FF7_P_2 */
10022 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
10025 /* VEX_LEN_0F3816_P_2 */
10028 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
10031 /* VEX_LEN_0F3819_P_2 */
10034 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
10037 /* VEX_LEN_0F381A_P_2_M_0 */
10040 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
10043 /* VEX_LEN_0F3836_P_2 */
10046 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
10049 /* VEX_LEN_0F3841_P_2 */
10051 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
10054 /* VEX_LEN_0F385A_P_2_M_0 */
10057 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
10060 /* VEX_LEN_0F38DB_P_2 */
10062 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
10065 /* VEX_LEN_0F38DC_P_2 */
10067 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
10070 /* VEX_LEN_0F38DD_P_2 */
10072 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
10075 /* VEX_LEN_0F38DE_P_2 */
10077 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
10080 /* VEX_LEN_0F38DF_P_2 */
10082 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
10085 /* VEX_LEN_0F38F2_P_0 */
10087 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
10090 /* VEX_LEN_0F38F3_R_1_P_0 */
10092 { "blsrS", { VexGdq
, Edq
}, 0 },
10095 /* VEX_LEN_0F38F3_R_2_P_0 */
10097 { "blsmskS", { VexGdq
, Edq
}, 0 },
10100 /* VEX_LEN_0F38F3_R_3_P_0 */
10102 { "blsiS", { VexGdq
, Edq
}, 0 },
10105 /* VEX_LEN_0F38F5_P_0 */
10107 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
10110 /* VEX_LEN_0F38F5_P_1 */
10112 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
10115 /* VEX_LEN_0F38F5_P_3 */
10117 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
10120 /* VEX_LEN_0F38F6_P_3 */
10122 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
10125 /* VEX_LEN_0F38F7_P_0 */
10127 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
10130 /* VEX_LEN_0F38F7_P_1 */
10132 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
10135 /* VEX_LEN_0F38F7_P_2 */
10137 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
10140 /* VEX_LEN_0F38F7_P_3 */
10142 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
10145 /* VEX_LEN_0F3A00_P_2 */
10148 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
10151 /* VEX_LEN_0F3A01_P_2 */
10154 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
10157 /* VEX_LEN_0F3A06_P_2 */
10160 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
10163 /* VEX_LEN_0F3A0A_P_2 */
10165 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10166 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10169 /* VEX_LEN_0F3A0B_P_2 */
10171 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10172 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10175 /* VEX_LEN_0F3A14_P_2 */
10177 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
10180 /* VEX_LEN_0F3A15_P_2 */
10182 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
10185 /* VEX_LEN_0F3A16_P_2 */
10187 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
10190 /* VEX_LEN_0F3A17_P_2 */
10192 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
10195 /* VEX_LEN_0F3A18_P_2 */
10198 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
10201 /* VEX_LEN_0F3A19_P_2 */
10204 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
10207 /* VEX_LEN_0F3A20_P_2 */
10209 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
10212 /* VEX_LEN_0F3A21_P_2 */
10214 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
10217 /* VEX_LEN_0F3A22_P_2 */
10219 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
10222 /* VEX_LEN_0F3A30_P_2 */
10224 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
10227 /* VEX_LEN_0F3A31_P_2 */
10229 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
10232 /* VEX_LEN_0F3A32_P_2 */
10234 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
10237 /* VEX_LEN_0F3A33_P_2 */
10239 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
10242 /* VEX_LEN_0F3A38_P_2 */
10245 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
10248 /* VEX_LEN_0F3A39_P_2 */
10251 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
10254 /* VEX_LEN_0F3A41_P_2 */
10256 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
10259 /* VEX_LEN_0F3A44_P_2 */
10261 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
10264 /* VEX_LEN_0F3A46_P_2 */
10267 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
10270 /* VEX_LEN_0F3A60_P_2 */
10272 { VEX_W_TABLE (VEX_W_0F3A60_P_2
) },
10275 /* VEX_LEN_0F3A61_P_2 */
10277 { VEX_W_TABLE (VEX_W_0F3A61_P_2
) },
10280 /* VEX_LEN_0F3A62_P_2 */
10282 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
10285 /* VEX_LEN_0F3A63_P_2 */
10287 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
10290 /* VEX_LEN_0F3A6A_P_2 */
10292 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10295 /* VEX_LEN_0F3A6B_P_2 */
10297 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10300 /* VEX_LEN_0F3A6E_P_2 */
10302 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10305 /* VEX_LEN_0F3A6F_P_2 */
10307 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10310 /* VEX_LEN_0F3A7A_P_2 */
10312 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10315 /* VEX_LEN_0F3A7B_P_2 */
10317 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10320 /* VEX_LEN_0F3A7E_P_2 */
10322 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10325 /* VEX_LEN_0F3A7F_P_2 */
10327 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10330 /* VEX_LEN_0F3ADF_P_2 */
10332 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
10335 /* VEX_LEN_0F3AF0_P_3 */
10337 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
10340 /* VEX_LEN_0FXOP_08_CC */
10342 { "vpcomb", { XM
, Vex128
, EXx
, Ib
}, 0 },
10345 /* VEX_LEN_0FXOP_08_CD */
10347 { "vpcomw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10350 /* VEX_LEN_0FXOP_08_CE */
10352 { "vpcomd", { XM
, Vex128
, EXx
, Ib
}, 0 },
10355 /* VEX_LEN_0FXOP_08_CF */
10357 { "vpcomq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10360 /* VEX_LEN_0FXOP_08_EC */
10362 { "vpcomub", { XM
, Vex128
, EXx
, Ib
}, 0 },
10365 /* VEX_LEN_0FXOP_08_ED */
10367 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10370 /* VEX_LEN_0FXOP_08_EE */
10372 { "vpcomud", { XM
, Vex128
, EXx
, Ib
}, 0 },
10375 /* VEX_LEN_0FXOP_08_EF */
10377 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10380 /* VEX_LEN_0FXOP_09_80 */
10382 { "vfrczps", { XM
, EXxmm
}, 0 },
10383 { "vfrczps", { XM
, EXymmq
}, 0 },
10386 /* VEX_LEN_0FXOP_09_81 */
10388 { "vfrczpd", { XM
, EXxmm
}, 0 },
10389 { "vfrczpd", { XM
, EXymmq
}, 0 },
10393 static const struct dis386 vex_w_table
[][2] = {
10395 /* VEX_W_0F10_P_0 */
10396 { "vmovups", { XM
, EXx
}, 0 },
10399 /* VEX_W_0F10_P_1 */
10400 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
10403 /* VEX_W_0F10_P_2 */
10404 { "vmovupd", { XM
, EXx
}, 0 },
10407 /* VEX_W_0F10_P_3 */
10408 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
10411 /* VEX_W_0F11_P_0 */
10412 { "vmovups", { EXxS
, XM
}, 0 },
10415 /* VEX_W_0F11_P_1 */
10416 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
10419 /* VEX_W_0F11_P_2 */
10420 { "vmovupd", { EXxS
, XM
}, 0 },
10423 /* VEX_W_0F11_P_3 */
10424 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
10427 /* VEX_W_0F12_P_0_M_0 */
10428 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
10431 /* VEX_W_0F12_P_0_M_1 */
10432 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
10435 /* VEX_W_0F12_P_1 */
10436 { "vmovsldup", { XM
, EXx
}, 0 },
10439 /* VEX_W_0F12_P_2 */
10440 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
10443 /* VEX_W_0F12_P_3 */
10444 { "vmovddup", { XM
, EXymmq
}, 0 },
10447 /* VEX_W_0F13_M_0 */
10448 { "vmovlpX", { EXq
, XM
}, 0 },
10452 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
10456 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
10459 /* VEX_W_0F16_P_0_M_0 */
10460 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
10463 /* VEX_W_0F16_P_0_M_1 */
10464 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
10467 /* VEX_W_0F16_P_1 */
10468 { "vmovshdup", { XM
, EXx
}, 0 },
10471 /* VEX_W_0F16_P_2 */
10472 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
10475 /* VEX_W_0F17_M_0 */
10476 { "vmovhpX", { EXq
, XM
}, 0 },
10480 { "vmovapX", { XM
, EXx
}, 0 },
10484 { "vmovapX", { EXxS
, XM
}, 0 },
10487 /* VEX_W_0F2B_M_0 */
10488 { "vmovntpX", { Mx
, XM
}, 0 },
10491 /* VEX_W_0F2E_P_0 */
10492 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
10495 /* VEX_W_0F2E_P_2 */
10496 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
10499 /* VEX_W_0F2F_P_0 */
10500 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
10503 /* VEX_W_0F2F_P_2 */
10504 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
10507 /* VEX_W_0F41_P_0_LEN_1 */
10508 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
10509 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
10512 /* VEX_W_0F41_P_2_LEN_1 */
10513 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
10514 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
10517 /* VEX_W_0F42_P_0_LEN_1 */
10518 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
10519 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
10522 /* VEX_W_0F42_P_2_LEN_1 */
10523 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
10524 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
10527 /* VEX_W_0F44_P_0_LEN_0 */
10528 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
10529 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
10532 /* VEX_W_0F44_P_2_LEN_0 */
10533 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
10534 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
10537 /* VEX_W_0F45_P_0_LEN_1 */
10538 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
10539 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
10542 /* VEX_W_0F45_P_2_LEN_1 */
10543 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
10544 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
10547 /* VEX_W_0F46_P_0_LEN_1 */
10548 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
10549 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
10552 /* VEX_W_0F46_P_2_LEN_1 */
10553 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
10554 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
10557 /* VEX_W_0F47_P_0_LEN_1 */
10558 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
10559 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
10562 /* VEX_W_0F47_P_2_LEN_1 */
10563 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
10564 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
10567 /* VEX_W_0F4A_P_0_LEN_1 */
10568 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
10569 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
10572 /* VEX_W_0F4A_P_2_LEN_1 */
10573 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
10574 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
10577 /* VEX_W_0F4B_P_0_LEN_1 */
10578 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
10579 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
10582 /* VEX_W_0F4B_P_2_LEN_1 */
10583 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
10586 /* VEX_W_0F50_M_0 */
10587 { "vmovmskpX", { Gdq
, XS
}, 0 },
10590 /* VEX_W_0F51_P_0 */
10591 { "vsqrtps", { XM
, EXx
}, 0 },
10594 /* VEX_W_0F51_P_1 */
10595 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10598 /* VEX_W_0F51_P_2 */
10599 { "vsqrtpd", { XM
, EXx
}, 0 },
10602 /* VEX_W_0F51_P_3 */
10603 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10606 /* VEX_W_0F52_P_0 */
10607 { "vrsqrtps", { XM
, EXx
}, 0 },
10610 /* VEX_W_0F52_P_1 */
10611 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10614 /* VEX_W_0F53_P_0 */
10615 { "vrcpps", { XM
, EXx
}, 0 },
10618 /* VEX_W_0F53_P_1 */
10619 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10622 /* VEX_W_0F58_P_0 */
10623 { "vaddps", { XM
, Vex
, EXx
}, 0 },
10626 /* VEX_W_0F58_P_1 */
10627 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10630 /* VEX_W_0F58_P_2 */
10631 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
10634 /* VEX_W_0F58_P_3 */
10635 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10638 /* VEX_W_0F59_P_0 */
10639 { "vmulps", { XM
, Vex
, EXx
}, 0 },
10642 /* VEX_W_0F59_P_1 */
10643 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10646 /* VEX_W_0F59_P_2 */
10647 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
10650 /* VEX_W_0F59_P_3 */
10651 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10654 /* VEX_W_0F5A_P_0 */
10655 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
10658 /* VEX_W_0F5A_P_1 */
10659 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10662 /* VEX_W_0F5A_P_3 */
10663 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10666 /* VEX_W_0F5B_P_0 */
10667 { "vcvtdq2ps", { XM
, EXx
}, 0 },
10670 /* VEX_W_0F5B_P_1 */
10671 { "vcvttps2dq", { XM
, EXx
}, 0 },
10674 /* VEX_W_0F5B_P_2 */
10675 { "vcvtps2dq", { XM
, EXx
}, 0 },
10678 /* VEX_W_0F5C_P_0 */
10679 { "vsubps", { XM
, Vex
, EXx
}, 0 },
10682 /* VEX_W_0F5C_P_1 */
10683 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10686 /* VEX_W_0F5C_P_2 */
10687 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
10690 /* VEX_W_0F5C_P_3 */
10691 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10694 /* VEX_W_0F5D_P_0 */
10695 { "vminps", { XM
, Vex
, EXx
}, 0 },
10698 /* VEX_W_0F5D_P_1 */
10699 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10702 /* VEX_W_0F5D_P_2 */
10703 { "vminpd", { XM
, Vex
, EXx
}, 0 },
10706 /* VEX_W_0F5D_P_3 */
10707 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10710 /* VEX_W_0F5E_P_0 */
10711 { "vdivps", { XM
, Vex
, EXx
}, 0 },
10714 /* VEX_W_0F5E_P_1 */
10715 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10718 /* VEX_W_0F5E_P_2 */
10719 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
10722 /* VEX_W_0F5E_P_3 */
10723 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10726 /* VEX_W_0F5F_P_0 */
10727 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
10730 /* VEX_W_0F5F_P_1 */
10731 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10734 /* VEX_W_0F5F_P_2 */
10735 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
10738 /* VEX_W_0F5F_P_3 */
10739 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10742 /* VEX_W_0F60_P_2 */
10743 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
10746 /* VEX_W_0F61_P_2 */
10747 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
10750 /* VEX_W_0F62_P_2 */
10751 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
10754 /* VEX_W_0F63_P_2 */
10755 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
10758 /* VEX_W_0F64_P_2 */
10759 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
10762 /* VEX_W_0F65_P_2 */
10763 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
10766 /* VEX_W_0F66_P_2 */
10767 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
10770 /* VEX_W_0F67_P_2 */
10771 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
10774 /* VEX_W_0F68_P_2 */
10775 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
10778 /* VEX_W_0F69_P_2 */
10779 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
10782 /* VEX_W_0F6A_P_2 */
10783 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
10786 /* VEX_W_0F6B_P_2 */
10787 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
10790 /* VEX_W_0F6C_P_2 */
10791 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
10794 /* VEX_W_0F6D_P_2 */
10795 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
10798 /* VEX_W_0F6F_P_1 */
10799 { "vmovdqu", { XM
, EXx
}, 0 },
10802 /* VEX_W_0F6F_P_2 */
10803 { "vmovdqa", { XM
, EXx
}, 0 },
10806 /* VEX_W_0F70_P_1 */
10807 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
10810 /* VEX_W_0F70_P_2 */
10811 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
10814 /* VEX_W_0F70_P_3 */
10815 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
10818 /* VEX_W_0F71_R_2_P_2 */
10819 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
10822 /* VEX_W_0F71_R_4_P_2 */
10823 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
10826 /* VEX_W_0F71_R_6_P_2 */
10827 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
10830 /* VEX_W_0F72_R_2_P_2 */
10831 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
10834 /* VEX_W_0F72_R_4_P_2 */
10835 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
10838 /* VEX_W_0F72_R_6_P_2 */
10839 { "vpslld", { Vex
, XS
, Ib
}, 0 },
10842 /* VEX_W_0F73_R_2_P_2 */
10843 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
10846 /* VEX_W_0F73_R_3_P_2 */
10847 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
10850 /* VEX_W_0F73_R_6_P_2 */
10851 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
10854 /* VEX_W_0F73_R_7_P_2 */
10855 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
10858 /* VEX_W_0F74_P_2 */
10859 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
10862 /* VEX_W_0F75_P_2 */
10863 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
10866 /* VEX_W_0F76_P_2 */
10867 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
10870 /* VEX_W_0F77_P_0 */
10871 { "", { VZERO
}, 0 },
10874 /* VEX_W_0F7C_P_2 */
10875 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
10878 /* VEX_W_0F7C_P_3 */
10879 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
10882 /* VEX_W_0F7D_P_2 */
10883 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
10886 /* VEX_W_0F7D_P_3 */
10887 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
10890 /* VEX_W_0F7E_P_1 */
10891 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
10894 /* VEX_W_0F7F_P_1 */
10895 { "vmovdqu", { EXxS
, XM
}, 0 },
10898 /* VEX_W_0F7F_P_2 */
10899 { "vmovdqa", { EXxS
, XM
}, 0 },
10902 /* VEX_W_0F90_P_0_LEN_0 */
10903 { "kmovw", { MaskG
, MaskE
}, 0 },
10904 { "kmovq", { MaskG
, MaskE
}, 0 },
10907 /* VEX_W_0F90_P_2_LEN_0 */
10908 { "kmovb", { MaskG
, MaskBDE
}, 0 },
10909 { "kmovd", { MaskG
, MaskBDE
}, 0 },
10912 /* VEX_W_0F91_P_0_LEN_0 */
10913 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
10914 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
10917 /* VEX_W_0F91_P_2_LEN_0 */
10918 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
10919 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
10922 /* VEX_W_0F92_P_0_LEN_0 */
10923 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10926 /* VEX_W_0F92_P_2_LEN_0 */
10927 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10930 /* VEX_W_0F92_P_3_LEN_0 */
10931 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0
) },
10932 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0
) },
10935 /* VEX_W_0F93_P_0_LEN_0 */
10936 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10939 /* VEX_W_0F93_P_2_LEN_0 */
10940 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10943 /* VEX_W_0F93_P_3_LEN_0 */
10944 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0
) },
10945 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0
) },
10948 /* VEX_W_0F98_P_0_LEN_0 */
10949 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10950 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10953 /* VEX_W_0F98_P_2_LEN_0 */
10954 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10955 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10958 /* VEX_W_0F99_P_0_LEN_0 */
10959 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10960 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10963 /* VEX_W_0F99_P_2_LEN_0 */
10964 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10965 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10968 /* VEX_W_0FAE_R_2_M_0 */
10969 { "vldmxcsr", { Md
}, 0 },
10972 /* VEX_W_0FAE_R_3_M_0 */
10973 { "vstmxcsr", { Md
}, 0 },
10976 /* VEX_W_0FC2_P_0 */
10977 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
10980 /* VEX_W_0FC2_P_1 */
10981 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
10984 /* VEX_W_0FC2_P_2 */
10985 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
10988 /* VEX_W_0FC2_P_3 */
10989 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
10992 /* VEX_W_0FC4_P_2 */
10993 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
10996 /* VEX_W_0FC5_P_2 */
10997 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
11000 /* VEX_W_0FD0_P_2 */
11001 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
11004 /* VEX_W_0FD0_P_3 */
11005 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
11008 /* VEX_W_0FD1_P_2 */
11009 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
11012 /* VEX_W_0FD2_P_2 */
11013 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
11016 /* VEX_W_0FD3_P_2 */
11017 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
11020 /* VEX_W_0FD4_P_2 */
11021 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
11024 /* VEX_W_0FD5_P_2 */
11025 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
11028 /* VEX_W_0FD6_P_2 */
11029 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
11032 /* VEX_W_0FD7_P_2_M_1 */
11033 { "vpmovmskb", { Gdq
, XS
}, 0 },
11036 /* VEX_W_0FD8_P_2 */
11037 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
11040 /* VEX_W_0FD9_P_2 */
11041 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
11044 /* VEX_W_0FDA_P_2 */
11045 { "vpminub", { XM
, Vex
, EXx
}, 0 },
11048 /* VEX_W_0FDB_P_2 */
11049 { "vpand", { XM
, Vex
, EXx
}, 0 },
11052 /* VEX_W_0FDC_P_2 */
11053 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
11056 /* VEX_W_0FDD_P_2 */
11057 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
11060 /* VEX_W_0FDE_P_2 */
11061 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
11064 /* VEX_W_0FDF_P_2 */
11065 { "vpandn", { XM
, Vex
, EXx
}, 0 },
11068 /* VEX_W_0FE0_P_2 */
11069 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
11072 /* VEX_W_0FE1_P_2 */
11073 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
11076 /* VEX_W_0FE2_P_2 */
11077 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
11080 /* VEX_W_0FE3_P_2 */
11081 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
11084 /* VEX_W_0FE4_P_2 */
11085 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
11088 /* VEX_W_0FE5_P_2 */
11089 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
11092 /* VEX_W_0FE6_P_1 */
11093 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
11096 /* VEX_W_0FE6_P_2 */
11097 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
11100 /* VEX_W_0FE6_P_3 */
11101 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
11104 /* VEX_W_0FE7_P_2_M_0 */
11105 { "vmovntdq", { Mx
, XM
}, 0 },
11108 /* VEX_W_0FE8_P_2 */
11109 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
11112 /* VEX_W_0FE9_P_2 */
11113 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
11116 /* VEX_W_0FEA_P_2 */
11117 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
11120 /* VEX_W_0FEB_P_2 */
11121 { "vpor", { XM
, Vex
, EXx
}, 0 },
11124 /* VEX_W_0FEC_P_2 */
11125 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
11128 /* VEX_W_0FED_P_2 */
11129 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
11132 /* VEX_W_0FEE_P_2 */
11133 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
11136 /* VEX_W_0FEF_P_2 */
11137 { "vpxor", { XM
, Vex
, EXx
}, 0 },
11140 /* VEX_W_0FF0_P_3_M_0 */
11141 { "vlddqu", { XM
, M
}, 0 },
11144 /* VEX_W_0FF1_P_2 */
11145 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
11148 /* VEX_W_0FF2_P_2 */
11149 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
11152 /* VEX_W_0FF3_P_2 */
11153 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
11156 /* VEX_W_0FF4_P_2 */
11157 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
11160 /* VEX_W_0FF5_P_2 */
11161 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
11164 /* VEX_W_0FF6_P_2 */
11165 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
11168 /* VEX_W_0FF7_P_2 */
11169 { "vmaskmovdqu", { XM
, XS
}, 0 },
11172 /* VEX_W_0FF8_P_2 */
11173 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
11176 /* VEX_W_0FF9_P_2 */
11177 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
11180 /* VEX_W_0FFA_P_2 */
11181 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
11184 /* VEX_W_0FFB_P_2 */
11185 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
11188 /* VEX_W_0FFC_P_2 */
11189 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
11192 /* VEX_W_0FFD_P_2 */
11193 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
11196 /* VEX_W_0FFE_P_2 */
11197 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
11200 /* VEX_W_0F3800_P_2 */
11201 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
11204 /* VEX_W_0F3801_P_2 */
11205 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
11208 /* VEX_W_0F3802_P_2 */
11209 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
11212 /* VEX_W_0F3803_P_2 */
11213 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
11216 /* VEX_W_0F3804_P_2 */
11217 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
11220 /* VEX_W_0F3805_P_2 */
11221 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
11224 /* VEX_W_0F3806_P_2 */
11225 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
11228 /* VEX_W_0F3807_P_2 */
11229 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
11232 /* VEX_W_0F3808_P_2 */
11233 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
11236 /* VEX_W_0F3809_P_2 */
11237 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
11240 /* VEX_W_0F380A_P_2 */
11241 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
11244 /* VEX_W_0F380B_P_2 */
11245 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
11248 /* VEX_W_0F380C_P_2 */
11249 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
11252 /* VEX_W_0F380D_P_2 */
11253 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
11256 /* VEX_W_0F380E_P_2 */
11257 { "vtestps", { XM
, EXx
}, 0 },
11260 /* VEX_W_0F380F_P_2 */
11261 { "vtestpd", { XM
, EXx
}, 0 },
11264 /* VEX_W_0F3816_P_2 */
11265 { "vpermps", { XM
, Vex
, EXx
}, 0 },
11268 /* VEX_W_0F3817_P_2 */
11269 { "vptest", { XM
, EXx
}, 0 },
11272 /* VEX_W_0F3818_P_2 */
11273 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
11276 /* VEX_W_0F3819_P_2 */
11277 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
11280 /* VEX_W_0F381A_P_2_M_0 */
11281 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
11284 /* VEX_W_0F381C_P_2 */
11285 { "vpabsb", { XM
, EXx
}, 0 },
11288 /* VEX_W_0F381D_P_2 */
11289 { "vpabsw", { XM
, EXx
}, 0 },
11292 /* VEX_W_0F381E_P_2 */
11293 { "vpabsd", { XM
, EXx
}, 0 },
11296 /* VEX_W_0F3820_P_2 */
11297 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
11300 /* VEX_W_0F3821_P_2 */
11301 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
11304 /* VEX_W_0F3822_P_2 */
11305 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
11308 /* VEX_W_0F3823_P_2 */
11309 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
11312 /* VEX_W_0F3824_P_2 */
11313 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
11316 /* VEX_W_0F3825_P_2 */
11317 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
11320 /* VEX_W_0F3828_P_2 */
11321 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
11324 /* VEX_W_0F3829_P_2 */
11325 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
11328 /* VEX_W_0F382A_P_2_M_0 */
11329 { "vmovntdqa", { XM
, Mx
}, 0 },
11332 /* VEX_W_0F382B_P_2 */
11333 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
11336 /* VEX_W_0F382C_P_2_M_0 */
11337 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
11340 /* VEX_W_0F382D_P_2_M_0 */
11341 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
11344 /* VEX_W_0F382E_P_2_M_0 */
11345 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
11348 /* VEX_W_0F382F_P_2_M_0 */
11349 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
11352 /* VEX_W_0F3830_P_2 */
11353 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
11356 /* VEX_W_0F3831_P_2 */
11357 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
11360 /* VEX_W_0F3832_P_2 */
11361 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
11364 /* VEX_W_0F3833_P_2 */
11365 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
11368 /* VEX_W_0F3834_P_2 */
11369 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
11372 /* VEX_W_0F3835_P_2 */
11373 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
11376 /* VEX_W_0F3836_P_2 */
11377 { "vpermd", { XM
, Vex
, EXx
}, 0 },
11380 /* VEX_W_0F3837_P_2 */
11381 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
11384 /* VEX_W_0F3838_P_2 */
11385 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
11388 /* VEX_W_0F3839_P_2 */
11389 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
11392 /* VEX_W_0F383A_P_2 */
11393 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
11396 /* VEX_W_0F383B_P_2 */
11397 { "vpminud", { XM
, Vex
, EXx
}, 0 },
11400 /* VEX_W_0F383C_P_2 */
11401 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
11404 /* VEX_W_0F383D_P_2 */
11405 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
11408 /* VEX_W_0F383E_P_2 */
11409 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
11412 /* VEX_W_0F383F_P_2 */
11413 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
11416 /* VEX_W_0F3840_P_2 */
11417 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
11420 /* VEX_W_0F3841_P_2 */
11421 { "vphminposuw", { XM
, EXx
}, 0 },
11424 /* VEX_W_0F3846_P_2 */
11425 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
11428 /* VEX_W_0F3858_P_2 */
11429 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
11432 /* VEX_W_0F3859_P_2 */
11433 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
11436 /* VEX_W_0F385A_P_2_M_0 */
11437 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
11440 /* VEX_W_0F3878_P_2 */
11441 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
11444 /* VEX_W_0F3879_P_2 */
11445 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
11448 /* VEX_W_0F38DB_P_2 */
11449 { "vaesimc", { XM
, EXx
}, 0 },
11452 /* VEX_W_0F38DC_P_2 */
11453 { "vaesenc", { XM
, Vex128
, EXx
}, 0 },
11456 /* VEX_W_0F38DD_P_2 */
11457 { "vaesenclast", { XM
, Vex128
, EXx
}, 0 },
11460 /* VEX_W_0F38DE_P_2 */
11461 { "vaesdec", { XM
, Vex128
, EXx
}, 0 },
11464 /* VEX_W_0F38DF_P_2 */
11465 { "vaesdeclast", { XM
, Vex128
, EXx
}, 0 },
11468 /* VEX_W_0F3A00_P_2 */
11470 { "vpermq", { XM
, EXx
, Ib
}, 0 },
11473 /* VEX_W_0F3A01_P_2 */
11475 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
11478 /* VEX_W_0F3A02_P_2 */
11479 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
11482 /* VEX_W_0F3A04_P_2 */
11483 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
11486 /* VEX_W_0F3A05_P_2 */
11487 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
11490 /* VEX_W_0F3A06_P_2 */
11491 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11494 /* VEX_W_0F3A08_P_2 */
11495 { "vroundps", { XM
, EXx
, Ib
}, 0 },
11498 /* VEX_W_0F3A09_P_2 */
11499 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
11502 /* VEX_W_0F3A0A_P_2 */
11503 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
11506 /* VEX_W_0F3A0B_P_2 */
11507 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
11510 /* VEX_W_0F3A0C_P_2 */
11511 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
11514 /* VEX_W_0F3A0D_P_2 */
11515 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
11518 /* VEX_W_0F3A0E_P_2 */
11519 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
11522 /* VEX_W_0F3A0F_P_2 */
11523 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
11526 /* VEX_W_0F3A14_P_2 */
11527 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
11530 /* VEX_W_0F3A15_P_2 */
11531 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
11534 /* VEX_W_0F3A18_P_2 */
11535 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11538 /* VEX_W_0F3A19_P_2 */
11539 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
11542 /* VEX_W_0F3A20_P_2 */
11543 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
11546 /* VEX_W_0F3A21_P_2 */
11547 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
11550 /* VEX_W_0F3A30_P_2_LEN_0 */
11551 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
11552 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
11555 /* VEX_W_0F3A31_P_2_LEN_0 */
11556 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
11557 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
11560 /* VEX_W_0F3A32_P_2_LEN_0 */
11561 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
11562 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
11565 /* VEX_W_0F3A33_P_2_LEN_0 */
11566 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
11567 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
11570 /* VEX_W_0F3A38_P_2 */
11571 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11574 /* VEX_W_0F3A39_P_2 */
11575 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
11578 /* VEX_W_0F3A40_P_2 */
11579 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
11582 /* VEX_W_0F3A41_P_2 */
11583 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
11586 /* VEX_W_0F3A42_P_2 */
11587 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
11590 /* VEX_W_0F3A44_P_2 */
11591 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
}, 0 },
11594 /* VEX_W_0F3A46_P_2 */
11595 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11598 /* VEX_W_0F3A48_P_2 */
11599 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11600 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11603 /* VEX_W_0F3A49_P_2 */
11604 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11605 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11608 /* VEX_W_0F3A4A_P_2 */
11609 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11612 /* VEX_W_0F3A4B_P_2 */
11613 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11616 /* VEX_W_0F3A4C_P_2 */
11617 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11620 /* VEX_W_0F3A60_P_2 */
11621 { "vpcmpestrm", { XM
, EXx
, Ib
}, 0 },
11624 /* VEX_W_0F3A61_P_2 */
11625 { "vpcmpestri", { XM
, EXx
, Ib
}, 0 },
11628 /* VEX_W_0F3A62_P_2 */
11629 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
11632 /* VEX_W_0F3A63_P_2 */
11633 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
11636 /* VEX_W_0F3ADF_P_2 */
11637 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
11639 #define NEED_VEX_W_TABLE
11640 #include "i386-dis-evex.h"
11641 #undef NEED_VEX_W_TABLE
11644 static const struct dis386 mod_table
[][2] = {
11647 { "leaS", { Gv
, M
}, 0 },
11652 { RM_TABLE (RM_C6_REG_7
) },
11657 { RM_TABLE (RM_C7_REG_7
) },
11661 { "Jcall^", { indirEp
}, 0 },
11665 { "Jjmp^", { indirEp
}, 0 },
11668 /* MOD_0F01_REG_0 */
11669 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11670 { RM_TABLE (RM_0F01_REG_0
) },
11673 /* MOD_0F01_REG_1 */
11674 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11675 { RM_TABLE (RM_0F01_REG_1
) },
11678 /* MOD_0F01_REG_2 */
11679 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11680 { RM_TABLE (RM_0F01_REG_2
) },
11683 /* MOD_0F01_REG_3 */
11684 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11685 { RM_TABLE (RM_0F01_REG_3
) },
11688 /* MOD_0F01_REG_7 */
11689 { "invlpg", { Mb
}, 0 },
11690 { RM_TABLE (RM_0F01_REG_7
) },
11693 /* MOD_0F12_PREFIX_0 */
11694 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
11695 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
11699 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
11702 /* MOD_0F16_PREFIX_0 */
11703 { "movhps", { XM
, EXq
}, 0 },
11704 { "movlhps", { XM
, EXq
}, 0 },
11708 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
11711 /* MOD_0F18_REG_0 */
11712 { "prefetchnta", { Mb
}, 0 },
11715 /* MOD_0F18_REG_1 */
11716 { "prefetcht0", { Mb
}, 0 },
11719 /* MOD_0F18_REG_2 */
11720 { "prefetcht1", { Mb
}, 0 },
11723 /* MOD_0F18_REG_3 */
11724 { "prefetcht2", { Mb
}, 0 },
11727 /* MOD_0F18_REG_4 */
11728 { "nop/reserved", { Mb
}, 0 },
11731 /* MOD_0F18_REG_5 */
11732 { "nop/reserved", { Mb
}, 0 },
11735 /* MOD_0F18_REG_6 */
11736 { "nop/reserved", { Mb
}, 0 },
11739 /* MOD_0F18_REG_7 */
11740 { "nop/reserved", { Mb
}, 0 },
11743 /* MOD_0F1A_PREFIX_0 */
11744 { "bndldx", { Gbnd
, Ev_bnd
}, 0 },
11745 { "nopQ", { Ev
}, 0 },
11748 /* MOD_0F1B_PREFIX_0 */
11749 { "bndstx", { Ev_bnd
, Gbnd
}, 0 },
11750 { "nopQ", { Ev
}, 0 },
11753 /* MOD_0F1B_PREFIX_1 */
11754 { "bndmk", { Gbnd
, Ev_bnd
}, 0 },
11755 { "nopQ", { Ev
}, 0 },
11760 { "movL", { Rd
, Td
}, 0 },
11765 { "movL", { Td
, Rd
}, 0 },
11768 /* MOD_0F2B_PREFIX_0 */
11769 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
11772 /* MOD_0F2B_PREFIX_1 */
11773 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
11776 /* MOD_0F2B_PREFIX_2 */
11777 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
11780 /* MOD_0F2B_PREFIX_3 */
11781 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
11786 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
11789 /* MOD_0F71_REG_2 */
11791 { "psrlw", { MS
, Ib
}, 0 },
11794 /* MOD_0F71_REG_4 */
11796 { "psraw", { MS
, Ib
}, 0 },
11799 /* MOD_0F71_REG_6 */
11801 { "psllw", { MS
, Ib
}, 0 },
11804 /* MOD_0F72_REG_2 */
11806 { "psrld", { MS
, Ib
}, 0 },
11809 /* MOD_0F72_REG_4 */
11811 { "psrad", { MS
, Ib
}, 0 },
11814 /* MOD_0F72_REG_6 */
11816 { "pslld", { MS
, Ib
}, 0 },
11819 /* MOD_0F73_REG_2 */
11821 { "psrlq", { MS
, Ib
}, 0 },
11824 /* MOD_0F73_REG_3 */
11826 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11829 /* MOD_0F73_REG_6 */
11831 { "psllq", { MS
, Ib
}, 0 },
11834 /* MOD_0F73_REG_7 */
11836 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11839 /* MOD_0FAE_REG_0 */
11840 { "fxsave", { FXSAVE
}, 0 },
11841 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11844 /* MOD_0FAE_REG_1 */
11845 { "fxrstor", { FXSAVE
}, 0 },
11846 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11849 /* MOD_0FAE_REG_2 */
11850 { "ldmxcsr", { Md
}, 0 },
11851 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11854 /* MOD_0FAE_REG_3 */
11855 { "stmxcsr", { Md
}, 0 },
11856 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11859 /* MOD_0FAE_REG_4 */
11860 { "xsave", { FXSAVE
}, 0 },
11863 /* MOD_0FAE_REG_5 */
11864 { "xrstor", { FXSAVE
}, 0 },
11865 { RM_TABLE (RM_0FAE_REG_5
) },
11868 /* MOD_0FAE_REG_6 */
11869 { PREFIX_TABLE (PREFIX_0FAE_REG_6
) },
11870 { RM_TABLE (RM_0FAE_REG_6
) },
11873 /* MOD_0FAE_REG_7 */
11874 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11875 { RM_TABLE (RM_0FAE_REG_7
) },
11879 { "lssS", { Gv
, Mp
}, 0 },
11883 { "lfsS", { Gv
, Mp
}, 0 },
11887 { "lgsS", { Gv
, Mp
}, 0 },
11891 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
11894 /* MOD_0FC7_REG_3 */
11895 { "xrstors", { FXSAVE
}, 0 },
11898 /* MOD_0FC7_REG_4 */
11899 { "xsavec", { FXSAVE
}, 0 },
11902 /* MOD_0FC7_REG_5 */
11903 { "xsaves", { FXSAVE
}, 0 },
11906 /* MOD_0FC7_REG_6 */
11907 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
11908 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
11911 /* MOD_0FC7_REG_7 */
11912 { "vmptrst", { Mq
}, 0 },
11913 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
11918 { "pmovmskb", { Gdq
, MS
}, 0 },
11921 /* MOD_0FE7_PREFIX_2 */
11922 { "movntdq", { Mx
, XM
}, 0 },
11925 /* MOD_0FF0_PREFIX_3 */
11926 { "lddqu", { XM
, M
}, 0 },
11929 /* MOD_0F382A_PREFIX_2 */
11930 { "movntdqa", { XM
, Mx
}, 0 },
11934 { "bound{S|}", { Gv
, Ma
}, 0 },
11935 { EVEX_TABLE (EVEX_0F
) },
11939 { "lesS", { Gv
, Mp
}, 0 },
11940 { VEX_C4_TABLE (VEX_0F
) },
11944 { "ldsS", { Gv
, Mp
}, 0 },
11945 { VEX_C5_TABLE (VEX_0F
) },
11948 /* MOD_VEX_0F12_PREFIX_0 */
11949 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11950 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11954 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11957 /* MOD_VEX_0F16_PREFIX_0 */
11958 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11959 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11963 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11967 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11970 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11972 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
11975 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11977 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
11980 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11982 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
11985 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11987 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
11990 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11992 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
11995 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11997 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
12000 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
12002 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
12005 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
12007 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
12010 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
12012 { "knotw", { MaskG
, MaskR
}, 0 },
12015 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
12017 { "knotq", { MaskG
, MaskR
}, 0 },
12020 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
12022 { "knotb", { MaskG
, MaskR
}, 0 },
12025 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
12027 { "knotd", { MaskG
, MaskR
}, 0 },
12030 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
12032 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
12035 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
12037 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
12040 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
12042 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
12045 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
12047 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
12050 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
12052 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
12055 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
12057 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
12060 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
12062 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
12065 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
12067 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
12070 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12072 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
12075 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12077 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
12080 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12082 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
12085 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12087 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
12090 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12092 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
12095 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12097 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
12100 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12102 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
12105 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12107 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
12110 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12112 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
12115 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12117 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
12120 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12122 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
12127 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
12130 /* MOD_VEX_0F71_REG_2 */
12132 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
12135 /* MOD_VEX_0F71_REG_4 */
12137 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
12140 /* MOD_VEX_0F71_REG_6 */
12142 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
12145 /* MOD_VEX_0F72_REG_2 */
12147 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
12150 /* MOD_VEX_0F72_REG_4 */
12152 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
12155 /* MOD_VEX_0F72_REG_6 */
12157 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
12160 /* MOD_VEX_0F73_REG_2 */
12162 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
12165 /* MOD_VEX_0F73_REG_3 */
12167 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
12170 /* MOD_VEX_0F73_REG_6 */
12172 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
12175 /* MOD_VEX_0F73_REG_7 */
12177 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
12180 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12181 { "kmovw", { Ew
, MaskG
}, 0 },
12185 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12186 { "kmovq", { Eq
, MaskG
}, 0 },
12190 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12191 { "kmovb", { Eb
, MaskG
}, 0 },
12195 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12196 { "kmovd", { Ed
, MaskG
}, 0 },
12200 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12202 { "kmovw", { MaskG
, Rdq
}, 0 },
12205 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12207 { "kmovb", { MaskG
, Rdq
}, 0 },
12210 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12212 { "kmovd", { MaskG
, Rdq
}, 0 },
12215 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12217 { "kmovq", { MaskG
, Rdq
}, 0 },
12220 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12222 { "kmovw", { Gdq
, MaskR
}, 0 },
12225 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12227 { "kmovb", { Gdq
, MaskR
}, 0 },
12230 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12232 { "kmovd", { Gdq
, MaskR
}, 0 },
12235 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12237 { "kmovq", { Gdq
, MaskR
}, 0 },
12240 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12242 { "kortestw", { MaskG
, MaskR
}, 0 },
12245 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12247 { "kortestq", { MaskG
, MaskR
}, 0 },
12250 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12252 { "kortestb", { MaskG
, MaskR
}, 0 },
12255 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12257 { "kortestd", { MaskG
, MaskR
}, 0 },
12260 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12262 { "ktestw", { MaskG
, MaskR
}, 0 },
12265 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12267 { "ktestq", { MaskG
, MaskR
}, 0 },
12270 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12272 { "ktestb", { MaskG
, MaskR
}, 0 },
12275 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12277 { "ktestd", { MaskG
, MaskR
}, 0 },
12280 /* MOD_VEX_0FAE_REG_2 */
12281 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
12284 /* MOD_VEX_0FAE_REG_3 */
12285 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
12288 /* MOD_VEX_0FD7_PREFIX_2 */
12290 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
12293 /* MOD_VEX_0FE7_PREFIX_2 */
12294 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
12297 /* MOD_VEX_0FF0_PREFIX_3 */
12298 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
12301 /* MOD_VEX_0F381A_PREFIX_2 */
12302 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
12305 /* MOD_VEX_0F382A_PREFIX_2 */
12306 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
12309 /* MOD_VEX_0F382C_PREFIX_2 */
12310 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
12313 /* MOD_VEX_0F382D_PREFIX_2 */
12314 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
12317 /* MOD_VEX_0F382E_PREFIX_2 */
12318 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
12321 /* MOD_VEX_0F382F_PREFIX_2 */
12322 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
12325 /* MOD_VEX_0F385A_PREFIX_2 */
12326 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
12329 /* MOD_VEX_0F388C_PREFIX_2 */
12330 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
12333 /* MOD_VEX_0F388E_PREFIX_2 */
12334 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
12337 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12339 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
12342 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12344 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
12347 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12349 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
12352 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12354 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
12357 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12359 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
12362 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12364 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
12367 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12369 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
12372 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12374 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
12376 #define NEED_MOD_TABLE
12377 #include "i386-dis-evex.h"
12378 #undef NEED_MOD_TABLE
12381 static const struct dis386 rm_table
[][8] = {
12384 { "xabort", { Skip_MODRM
, Ib
}, 0 },
12388 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
12391 /* RM_0F01_REG_0 */
12393 { "vmcall", { Skip_MODRM
}, 0 },
12394 { "vmlaunch", { Skip_MODRM
}, 0 },
12395 { "vmresume", { Skip_MODRM
}, 0 },
12396 { "vmxoff", { Skip_MODRM
}, 0 },
12399 /* RM_0F01_REG_1 */
12400 { "monitor", { { OP_Monitor
, 0 } }, 0 },
12401 { "mwait", { { OP_Mwait
, 0 } }, 0 },
12402 { "clac", { Skip_MODRM
}, 0 },
12403 { "stac", { Skip_MODRM
}, 0 },
12407 { "encls", { Skip_MODRM
}, 0 },
12410 /* RM_0F01_REG_2 */
12411 { "xgetbv", { Skip_MODRM
}, 0 },
12412 { "xsetbv", { Skip_MODRM
}, 0 },
12415 { "vmfunc", { Skip_MODRM
}, 0 },
12416 { "xend", { Skip_MODRM
}, 0 },
12417 { "xtest", { Skip_MODRM
}, 0 },
12418 { "enclu", { Skip_MODRM
}, 0 },
12421 /* RM_0F01_REG_3 */
12422 { "vmrun", { Skip_MODRM
}, 0 },
12423 { "vmmcall", { Skip_MODRM
}, 0 },
12424 { "vmload", { Skip_MODRM
}, 0 },
12425 { "vmsave", { Skip_MODRM
}, 0 },
12426 { "stgi", { Skip_MODRM
}, 0 },
12427 { "clgi", { Skip_MODRM
}, 0 },
12428 { "skinit", { Skip_MODRM
}, 0 },
12429 { "invlpga", { Skip_MODRM
}, 0 },
12432 /* RM_0F01_REG_7 */
12433 { "swapgs", { Skip_MODRM
}, 0 },
12434 { "rdtscp", { Skip_MODRM
}, 0 },
12435 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
12436 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
12437 { "clzero", { Skip_MODRM
}, 0 },
12440 /* RM_0FAE_REG_5 */
12441 { "lfence", { Skip_MODRM
}, 0 },
12444 /* RM_0FAE_REG_6 */
12445 { "mfence", { Skip_MODRM
}, 0 },
12448 /* RM_0FAE_REG_7 */
12449 { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7
) },
12453 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12455 /* We use the high bit to indicate different name for the same
12457 #define REP_PREFIX (0xf3 | 0x100)
12458 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12459 #define XRELEASE_PREFIX (0xf3 | 0x400)
12460 #define BND_PREFIX (0xf2 | 0x400)
12465 int newrex
, i
, length
;
12471 last_lock_prefix
= -1;
12472 last_repz_prefix
= -1;
12473 last_repnz_prefix
= -1;
12474 last_data_prefix
= -1;
12475 last_addr_prefix
= -1;
12476 last_rex_prefix
= -1;
12477 last_seg_prefix
= -1;
12479 active_seg_prefix
= 0;
12480 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12481 all_prefixes
[i
] = 0;
12484 /* The maximum instruction length is 15bytes. */
12485 while (length
< MAX_CODE_LENGTH
- 1)
12487 FETCH_DATA (the_info
, codep
+ 1);
12491 /* REX prefixes family. */
12508 if (address_mode
== mode_64bit
)
12512 last_rex_prefix
= i
;
12515 prefixes
|= PREFIX_REPZ
;
12516 last_repz_prefix
= i
;
12519 prefixes
|= PREFIX_REPNZ
;
12520 last_repnz_prefix
= i
;
12523 prefixes
|= PREFIX_LOCK
;
12524 last_lock_prefix
= i
;
12527 prefixes
|= PREFIX_CS
;
12528 last_seg_prefix
= i
;
12529 active_seg_prefix
= PREFIX_CS
;
12532 prefixes
|= PREFIX_SS
;
12533 last_seg_prefix
= i
;
12534 active_seg_prefix
= PREFIX_SS
;
12537 prefixes
|= PREFIX_DS
;
12538 last_seg_prefix
= i
;
12539 active_seg_prefix
= PREFIX_DS
;
12542 prefixes
|= PREFIX_ES
;
12543 last_seg_prefix
= i
;
12544 active_seg_prefix
= PREFIX_ES
;
12547 prefixes
|= PREFIX_FS
;
12548 last_seg_prefix
= i
;
12549 active_seg_prefix
= PREFIX_FS
;
12552 prefixes
|= PREFIX_GS
;
12553 last_seg_prefix
= i
;
12554 active_seg_prefix
= PREFIX_GS
;
12557 prefixes
|= PREFIX_DATA
;
12558 last_data_prefix
= i
;
12561 prefixes
|= PREFIX_ADDR
;
12562 last_addr_prefix
= i
;
12565 /* fwait is really an instruction. If there are prefixes
12566 before the fwait, they belong to the fwait, *not* to the
12567 following instruction. */
12569 if (prefixes
|| rex
)
12571 prefixes
|= PREFIX_FWAIT
;
12573 /* This ensures that the previous REX prefixes are noticed
12574 as unused prefixes, as in the return case below. */
12578 prefixes
= PREFIX_FWAIT
;
12583 /* Rex is ignored when followed by another prefix. */
12589 if (*codep
!= FWAIT_OPCODE
)
12590 all_prefixes
[i
++] = *codep
;
12598 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12601 static const char *
12602 prefix_name (int pref
, int sizeflag
)
12604 static const char *rexes
[16] =
12607 "rex.B", /* 0x41 */
12608 "rex.X", /* 0x42 */
12609 "rex.XB", /* 0x43 */
12610 "rex.R", /* 0x44 */
12611 "rex.RB", /* 0x45 */
12612 "rex.RX", /* 0x46 */
12613 "rex.RXB", /* 0x47 */
12614 "rex.W", /* 0x48 */
12615 "rex.WB", /* 0x49 */
12616 "rex.WX", /* 0x4a */
12617 "rex.WXB", /* 0x4b */
12618 "rex.WR", /* 0x4c */
12619 "rex.WRB", /* 0x4d */
12620 "rex.WRX", /* 0x4e */
12621 "rex.WRXB", /* 0x4f */
12626 /* REX prefixes family. */
12643 return rexes
[pref
- 0x40];
12663 return (sizeflag
& DFLAG
) ? "data16" : "data32";
12665 if (address_mode
== mode_64bit
)
12666 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
12668 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
12673 case XACQUIRE_PREFIX
:
12675 case XRELEASE_PREFIX
:
12684 static char op_out
[MAX_OPERANDS
][100];
12685 static int op_ad
, op_index
[MAX_OPERANDS
];
12686 static int two_source_ops
;
12687 static bfd_vma op_address
[MAX_OPERANDS
];
12688 static bfd_vma op_riprel
[MAX_OPERANDS
];
12689 static bfd_vma start_pc
;
12692 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12693 * (see topic "Redundant prefixes" in the "Differences from 8086"
12694 * section of the "Virtual 8086 Mode" chapter.)
12695 * 'pc' should be the address of this instruction, it will
12696 * be used to print the target address if this is a relative jump or call
12697 * The function returns the length of this instruction in bytes.
12700 static char intel_syntax
;
12701 static char intel_mnemonic
= !SYSV386_COMPAT
;
12702 static char open_char
;
12703 static char close_char
;
12704 static char separator_char
;
12705 static char scale_char
;
12713 static enum x86_64_isa isa64
;
12715 /* Here for backwards compatibility. When gdb stops using
12716 print_insn_i386_att and print_insn_i386_intel these functions can
12717 disappear, and print_insn_i386 be merged into print_insn. */
12719 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
12723 return print_insn (pc
, info
);
12727 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
12731 return print_insn (pc
, info
);
12735 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
12739 return print_insn (pc
, info
);
12743 print_i386_disassembler_options (FILE *stream
)
12745 fprintf (stream
, _("\n\
12746 The following i386/x86-64 specific disassembler options are supported for use\n\
12747 with the -M switch (multiple options should be separated by commas):\n"));
12749 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
12750 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
12751 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
12752 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
12753 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
12754 fprintf (stream
, _(" att-mnemonic\n"
12755 " Display instruction in AT&T mnemonic\n"));
12756 fprintf (stream
, _(" intel-mnemonic\n"
12757 " Display instruction in Intel mnemonic\n"));
12758 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
12759 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
12760 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
12761 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
12762 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
12763 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12764 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
12765 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
12769 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
12771 /* Get a pointer to struct dis386 with a valid name. */
12773 static const struct dis386
*
12774 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
12776 int vindex
, vex_table_index
;
12778 if (dp
->name
!= NULL
)
12781 switch (dp
->op
[0].bytemode
)
12783 case USE_REG_TABLE
:
12784 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
12787 case USE_MOD_TABLE
:
12788 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
12789 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
12793 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
12796 case USE_PREFIX_TABLE
:
12799 /* The prefix in VEX is implicit. */
12800 switch (vex
.prefix
)
12805 case REPE_PREFIX_OPCODE
:
12808 case DATA_PREFIX_OPCODE
:
12811 case REPNE_PREFIX_OPCODE
:
12821 int last_prefix
= -1;
12824 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12825 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12827 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12829 if (last_repz_prefix
> last_repnz_prefix
)
12832 prefix
= PREFIX_REPZ
;
12833 last_prefix
= last_repz_prefix
;
12838 prefix
= PREFIX_REPNZ
;
12839 last_prefix
= last_repnz_prefix
;
12842 /* Check if prefix should be ignored. */
12843 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
12844 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
12849 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12852 prefix
= PREFIX_DATA
;
12853 last_prefix
= last_data_prefix
;
12858 used_prefixes
|= prefix
;
12859 all_prefixes
[last_prefix
] = 0;
12862 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12865 case USE_X86_64_TABLE
:
12866 vindex
= address_mode
== mode_64bit
? 1 : 0;
12867 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12870 case USE_3BYTE_TABLE
:
12871 FETCH_DATA (info
, codep
+ 2);
12873 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12875 modrm
.mod
= (*codep
>> 6) & 3;
12876 modrm
.reg
= (*codep
>> 3) & 7;
12877 modrm
.rm
= *codep
& 7;
12880 case USE_VEX_LEN_TABLE
:
12884 switch (vex
.length
)
12897 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12900 case USE_XOP_8F_TABLE
:
12901 FETCH_DATA (info
, codep
+ 3);
12902 /* All bits in the REX prefix are ignored. */
12904 rex
= ~(*codep
>> 5) & 0x7;
12906 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12907 switch ((*codep
& 0x1f))
12913 vex_table_index
= XOP_08
;
12916 vex_table_index
= XOP_09
;
12919 vex_table_index
= XOP_0A
;
12923 vex
.w
= *codep
& 0x80;
12924 if (vex
.w
&& address_mode
== mode_64bit
)
12927 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12928 if (address_mode
!= mode_64bit
12929 && vex
.register_specifier
> 0x7)
12935 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12936 switch ((*codep
& 0x3))
12942 vex
.prefix
= DATA_PREFIX_OPCODE
;
12945 vex
.prefix
= REPE_PREFIX_OPCODE
;
12948 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12955 dp
= &xop_table
[vex_table_index
][vindex
];
12958 FETCH_DATA (info
, codep
+ 1);
12959 modrm
.mod
= (*codep
>> 6) & 3;
12960 modrm
.reg
= (*codep
>> 3) & 7;
12961 modrm
.rm
= *codep
& 7;
12964 case USE_VEX_C4_TABLE
:
12966 FETCH_DATA (info
, codep
+ 3);
12967 /* All bits in the REX prefix are ignored. */
12969 rex
= ~(*codep
>> 5) & 0x7;
12970 switch ((*codep
& 0x1f))
12976 vex_table_index
= VEX_0F
;
12979 vex_table_index
= VEX_0F38
;
12982 vex_table_index
= VEX_0F3A
;
12986 vex
.w
= *codep
& 0x80;
12987 if (vex
.w
&& address_mode
== mode_64bit
)
12990 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12991 if (address_mode
!= mode_64bit
12992 && vex
.register_specifier
> 0x7)
12998 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12999 switch ((*codep
& 0x3))
13005 vex
.prefix
= DATA_PREFIX_OPCODE
;
13008 vex
.prefix
= REPE_PREFIX_OPCODE
;
13011 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13018 dp
= &vex_table
[vex_table_index
][vindex
];
13020 /* There is no MODRM byte for VEX [82|77]. */
13021 if (vindex
!= 0x77 && vindex
!= 0x82)
13023 FETCH_DATA (info
, codep
+ 1);
13024 modrm
.mod
= (*codep
>> 6) & 3;
13025 modrm
.reg
= (*codep
>> 3) & 7;
13026 modrm
.rm
= *codep
& 7;
13030 case USE_VEX_C5_TABLE
:
13032 FETCH_DATA (info
, codep
+ 2);
13033 /* All bits in the REX prefix are ignored. */
13035 rex
= (*codep
& 0x80) ? 0 : REX_R
;
13037 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
13038 if (address_mode
!= mode_64bit
13039 && vex
.register_specifier
> 0x7)
13047 vex
.length
= (*codep
& 0x4) ? 256 : 128;
13048 switch ((*codep
& 0x3))
13054 vex
.prefix
= DATA_PREFIX_OPCODE
;
13057 vex
.prefix
= REPE_PREFIX_OPCODE
;
13060 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13067 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
13069 /* There is no MODRM byte for VEX [82|77]. */
13070 if (vindex
!= 0x77 && vindex
!= 0x82)
13072 FETCH_DATA (info
, codep
+ 1);
13073 modrm
.mod
= (*codep
>> 6) & 3;
13074 modrm
.reg
= (*codep
>> 3) & 7;
13075 modrm
.rm
= *codep
& 7;
13079 case USE_VEX_W_TABLE
:
13083 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
13086 case USE_EVEX_TABLE
:
13087 two_source_ops
= 0;
13090 FETCH_DATA (info
, codep
+ 4);
13091 /* All bits in the REX prefix are ignored. */
13093 /* The first byte after 0x62. */
13094 rex
= ~(*codep
>> 5) & 0x7;
13095 vex
.r
= *codep
& 0x10;
13096 switch ((*codep
& 0xf))
13099 return &bad_opcode
;
13101 vex_table_index
= EVEX_0F
;
13104 vex_table_index
= EVEX_0F38
;
13107 vex_table_index
= EVEX_0F3A
;
13111 /* The second byte after 0x62. */
13113 vex
.w
= *codep
& 0x80;
13114 if (vex
.w
&& address_mode
== mode_64bit
)
13117 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
13118 if (address_mode
!= mode_64bit
)
13120 /* In 16/32-bit mode silently ignore following bits. */
13124 vex
.register_specifier
&= 0x7;
13128 if (!(*codep
& 0x4))
13129 return &bad_opcode
;
13131 switch ((*codep
& 0x3))
13137 vex
.prefix
= DATA_PREFIX_OPCODE
;
13140 vex
.prefix
= REPE_PREFIX_OPCODE
;
13143 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13147 /* The third byte after 0x62. */
13150 /* Remember the static rounding bits. */
13151 vex
.ll
= (*codep
>> 5) & 3;
13152 vex
.b
= (*codep
& 0x10) != 0;
13154 vex
.v
= *codep
& 0x8;
13155 vex
.mask_register_specifier
= *codep
& 0x7;
13156 vex
.zeroing
= *codep
& 0x80;
13162 dp
= &evex_table
[vex_table_index
][vindex
];
13164 FETCH_DATA (info
, codep
+ 1);
13165 modrm
.mod
= (*codep
>> 6) & 3;
13166 modrm
.reg
= (*codep
>> 3) & 7;
13167 modrm
.rm
= *codep
& 7;
13169 /* Set vector length. */
13170 if (modrm
.mod
== 3 && vex
.b
)
13186 return &bad_opcode
;
13199 if (dp
->name
!= NULL
)
13202 return get_valid_dis386 (dp
, info
);
13206 get_sib (disassemble_info
*info
, int sizeflag
)
13208 /* If modrm.mod == 3, operand must be register. */
13210 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13214 FETCH_DATA (info
, codep
+ 2);
13215 sib
.index
= (codep
[1] >> 3) & 7;
13216 sib
.scale
= (codep
[1] >> 6) & 3;
13217 sib
.base
= codep
[1] & 7;
13222 print_insn (bfd_vma pc
, disassemble_info
*info
)
13224 const struct dis386
*dp
;
13226 char *op_txt
[MAX_OPERANDS
];
13228 int sizeflag
, orig_sizeflag
;
13230 struct dis_private priv
;
13233 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13234 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
13235 address_mode
= mode_32bit
;
13236 else if (info
->mach
== bfd_mach_i386_i8086
)
13238 address_mode
= mode_16bit
;
13239 priv
.orig_sizeflag
= 0;
13242 address_mode
= mode_64bit
;
13244 if (intel_syntax
== (char) -1)
13245 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
13247 for (p
= info
->disassembler_options
; p
!= NULL
; )
13249 if (CONST_STRNEQ (p
, "amd64"))
13251 else if (CONST_STRNEQ (p
, "intel64"))
13253 else if (CONST_STRNEQ (p
, "x86-64"))
13255 address_mode
= mode_64bit
;
13256 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13258 else if (CONST_STRNEQ (p
, "i386"))
13260 address_mode
= mode_32bit
;
13261 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13263 else if (CONST_STRNEQ (p
, "i8086"))
13265 address_mode
= mode_16bit
;
13266 priv
.orig_sizeflag
= 0;
13268 else if (CONST_STRNEQ (p
, "intel"))
13271 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
13272 intel_mnemonic
= 1;
13274 else if (CONST_STRNEQ (p
, "att"))
13277 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
13278 intel_mnemonic
= 0;
13280 else if (CONST_STRNEQ (p
, "addr"))
13282 if (address_mode
== mode_64bit
)
13284 if (p
[4] == '3' && p
[5] == '2')
13285 priv
.orig_sizeflag
&= ~AFLAG
;
13286 else if (p
[4] == '6' && p
[5] == '4')
13287 priv
.orig_sizeflag
|= AFLAG
;
13291 if (p
[4] == '1' && p
[5] == '6')
13292 priv
.orig_sizeflag
&= ~AFLAG
;
13293 else if (p
[4] == '3' && p
[5] == '2')
13294 priv
.orig_sizeflag
|= AFLAG
;
13297 else if (CONST_STRNEQ (p
, "data"))
13299 if (p
[4] == '1' && p
[5] == '6')
13300 priv
.orig_sizeflag
&= ~DFLAG
;
13301 else if (p
[4] == '3' && p
[5] == '2')
13302 priv
.orig_sizeflag
|= DFLAG
;
13304 else if (CONST_STRNEQ (p
, "suffix"))
13305 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
13307 p
= strchr (p
, ',');
13314 names64
= intel_names64
;
13315 names32
= intel_names32
;
13316 names16
= intel_names16
;
13317 names8
= intel_names8
;
13318 names8rex
= intel_names8rex
;
13319 names_seg
= intel_names_seg
;
13320 names_mm
= intel_names_mm
;
13321 names_bnd
= intel_names_bnd
;
13322 names_xmm
= intel_names_xmm
;
13323 names_ymm
= intel_names_ymm
;
13324 names_zmm
= intel_names_zmm
;
13325 index64
= intel_index64
;
13326 index32
= intel_index32
;
13327 names_mask
= intel_names_mask
;
13328 index16
= intel_index16
;
13331 separator_char
= '+';
13336 names64
= att_names64
;
13337 names32
= att_names32
;
13338 names16
= att_names16
;
13339 names8
= att_names8
;
13340 names8rex
= att_names8rex
;
13341 names_seg
= att_names_seg
;
13342 names_mm
= att_names_mm
;
13343 names_bnd
= att_names_bnd
;
13344 names_xmm
= att_names_xmm
;
13345 names_ymm
= att_names_ymm
;
13346 names_zmm
= att_names_zmm
;
13347 index64
= att_index64
;
13348 index32
= att_index32
;
13349 names_mask
= att_names_mask
;
13350 index16
= att_index16
;
13353 separator_char
= ',';
13357 /* The output looks better if we put 7 bytes on a line, since that
13358 puts most long word instructions on a single line. Use 8 bytes
13360 if ((info
->mach
& bfd_mach_l1om
) != 0)
13361 info
->bytes_per_line
= 8;
13363 info
->bytes_per_line
= 7;
13365 info
->private_data
= &priv
;
13366 priv
.max_fetched
= priv
.the_buffer
;
13367 priv
.insn_start
= pc
;
13370 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13378 start_codep
= priv
.the_buffer
;
13379 codep
= priv
.the_buffer
;
13381 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
13385 /* Getting here means we tried for data but didn't get it. That
13386 means we have an incomplete instruction of some sort. Just
13387 print the first byte as a prefix or a .byte pseudo-op. */
13388 if (codep
> priv
.the_buffer
)
13390 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
13392 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
13395 /* Just print the first byte as a .byte instruction. */
13396 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
13397 (unsigned int) priv
.the_buffer
[0]);
13407 sizeflag
= priv
.orig_sizeflag
;
13409 if (!ckprefix () || rex_used
)
13411 /* Too many prefixes or unused REX prefixes. */
13413 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
13415 (*info
->fprintf_func
) (info
->stream
, "%s%s",
13417 prefix_name (all_prefixes
[i
], sizeflag
));
13421 insn_codep
= codep
;
13423 FETCH_DATA (info
, codep
+ 1);
13424 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
13426 if (((prefixes
& PREFIX_FWAIT
)
13427 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
13429 /* Handle prefixes before fwait. */
13430 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
13432 (*info
->fprintf_func
) (info
->stream
, "%s ",
13433 prefix_name (all_prefixes
[i
], sizeflag
));
13434 (*info
->fprintf_func
) (info
->stream
, "fwait");
13438 if (*codep
== 0x0f)
13440 unsigned char threebyte
;
13443 FETCH_DATA (info
, codep
+ 1);
13444 threebyte
= *codep
;
13445 dp
= &dis386_twobyte
[threebyte
];
13446 need_modrm
= twobyte_has_modrm
[*codep
];
13451 dp
= &dis386
[*codep
];
13452 need_modrm
= onebyte_has_modrm
[*codep
];
13456 /* Save sizeflag for printing the extra prefixes later before updating
13457 it for mnemonic and operand processing. The prefix names depend
13458 only on the address mode. */
13459 orig_sizeflag
= sizeflag
;
13460 if (prefixes
& PREFIX_ADDR
)
13462 if ((prefixes
& PREFIX_DATA
))
13468 FETCH_DATA (info
, codep
+ 1);
13469 modrm
.mod
= (*codep
>> 6) & 3;
13470 modrm
.reg
= (*codep
>> 3) & 7;
13471 modrm
.rm
= *codep
& 7;
13479 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
13481 get_sib (info
, sizeflag
);
13482 dofloat (sizeflag
);
13486 dp
= get_valid_dis386 (dp
, info
);
13487 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
13489 get_sib (info
, sizeflag
);
13490 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13493 op_ad
= MAX_OPERANDS
- 1 - i
;
13495 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
13496 /* For EVEX instruction after the last operand masking
13497 should be printed. */
13498 if (i
== 0 && vex
.evex
)
13500 /* Don't print {%k0}. */
13501 if (vex
.mask_register_specifier
)
13504 oappend (names_mask
[vex
.mask_register_specifier
]);
13514 /* Check if the REX prefix is used. */
13515 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
13516 all_prefixes
[last_rex_prefix
] = 0;
13518 /* Check if the SEG prefix is used. */
13519 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
13520 | PREFIX_FS
| PREFIX_GS
)) != 0
13521 && (used_prefixes
& active_seg_prefix
) != 0)
13522 all_prefixes
[last_seg_prefix
] = 0;
13524 /* Check if the ADDR prefix is used. */
13525 if ((prefixes
& PREFIX_ADDR
) != 0
13526 && (used_prefixes
& PREFIX_ADDR
) != 0)
13527 all_prefixes
[last_addr_prefix
] = 0;
13529 /* Check if the DATA prefix is used. */
13530 if ((prefixes
& PREFIX_DATA
) != 0
13531 && (used_prefixes
& PREFIX_DATA
) != 0)
13532 all_prefixes
[last_data_prefix
] = 0;
13534 /* Print the extra prefixes. */
13536 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
13537 if (all_prefixes
[i
])
13540 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
13543 prefix_length
+= strlen (name
) + 1;
13544 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
13547 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13548 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13549 used by putop and MMX/SSE operand and may be overriden by the
13550 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13552 if (dp
->prefix_requirement
== PREFIX_OPCODE
13553 && dp
!= &bad_opcode
13555 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
13557 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
13559 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
13561 && (used_prefixes
& PREFIX_DATA
) == 0))))
13563 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13564 return end_codep
- priv
.the_buffer
;
13567 /* Check maximum code length. */
13568 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
13570 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13571 return MAX_CODE_LENGTH
;
13574 obufp
= mnemonicendp
;
13575 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
13578 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
13580 /* The enter and bound instructions are printed with operands in the same
13581 order as the intel book; everything else is printed in reverse order. */
13582 if (intel_syntax
|| two_source_ops
)
13586 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13587 op_txt
[i
] = op_out
[i
];
13589 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
13590 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
13592 op_txt
[2] = op_out
[3];
13593 op_txt
[3] = op_out
[2];
13596 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
13598 op_ad
= op_index
[i
];
13599 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
13600 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
13601 riprel
= op_riprel
[i
];
13602 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
13603 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
13608 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13609 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
13613 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13617 (*info
->fprintf_func
) (info
->stream
, ",");
13618 if (op_index
[i
] != -1 && !op_riprel
[i
])
13619 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
13621 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
13625 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13626 if (op_index
[i
] != -1 && op_riprel
[i
])
13628 (*info
->fprintf_func
) (info
->stream
, " # ");
13629 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ codep
- start_codep
13630 + op_address
[op_index
[i
]]), info
);
13633 return codep
- priv
.the_buffer
;
13636 static const char *float_mem
[] = {
13711 static const unsigned char float_mem_mode
[] = {
13786 #define ST { OP_ST, 0 }
13787 #define STi { OP_STi, 0 }
13789 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13790 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13791 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13792 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13793 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13794 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13795 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13796 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13797 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13799 static const struct dis386 float_reg
[][8] = {
13802 { "fadd", { ST
, STi
}, 0 },
13803 { "fmul", { ST
, STi
}, 0 },
13804 { "fcom", { STi
}, 0 },
13805 { "fcomp", { STi
}, 0 },
13806 { "fsub", { ST
, STi
}, 0 },
13807 { "fsubr", { ST
, STi
}, 0 },
13808 { "fdiv", { ST
, STi
}, 0 },
13809 { "fdivr", { ST
, STi
}, 0 },
13813 { "fld", { STi
}, 0 },
13814 { "fxch", { STi
}, 0 },
13824 { "fcmovb", { ST
, STi
}, 0 },
13825 { "fcmove", { ST
, STi
}, 0 },
13826 { "fcmovbe",{ ST
, STi
}, 0 },
13827 { "fcmovu", { ST
, STi
}, 0 },
13835 { "fcmovnb",{ ST
, STi
}, 0 },
13836 { "fcmovne",{ ST
, STi
}, 0 },
13837 { "fcmovnbe",{ ST
, STi
}, 0 },
13838 { "fcmovnu",{ ST
, STi
}, 0 },
13840 { "fucomi", { ST
, STi
}, 0 },
13841 { "fcomi", { ST
, STi
}, 0 },
13846 { "fadd", { STi
, ST
}, 0 },
13847 { "fmul", { STi
, ST
}, 0 },
13850 { "fsub!M", { STi
, ST
}, 0 },
13851 { "fsubM", { STi
, ST
}, 0 },
13852 { "fdiv!M", { STi
, ST
}, 0 },
13853 { "fdivM", { STi
, ST
}, 0 },
13857 { "ffree", { STi
}, 0 },
13859 { "fst", { STi
}, 0 },
13860 { "fstp", { STi
}, 0 },
13861 { "fucom", { STi
}, 0 },
13862 { "fucomp", { STi
}, 0 },
13868 { "faddp", { STi
, ST
}, 0 },
13869 { "fmulp", { STi
, ST
}, 0 },
13872 { "fsub!Mp", { STi
, ST
}, 0 },
13873 { "fsubMp", { STi
, ST
}, 0 },
13874 { "fdiv!Mp", { STi
, ST
}, 0 },
13875 { "fdivMp", { STi
, ST
}, 0 },
13879 { "ffreep", { STi
}, 0 },
13884 { "fucomip", { ST
, STi
}, 0 },
13885 { "fcomip", { ST
, STi
}, 0 },
13890 static char *fgrps
[][8] = {
13893 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13898 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13903 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13908 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13913 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13918 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13923 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13924 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13929 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13934 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13939 swap_operand (void)
13941 mnemonicendp
[0] = '.';
13942 mnemonicendp
[1] = 's';
13947 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13948 int sizeflag ATTRIBUTE_UNUSED
)
13950 /* Skip mod/rm byte. */
13956 dofloat (int sizeflag
)
13958 const struct dis386
*dp
;
13959 unsigned char floatop
;
13961 floatop
= codep
[-1];
13963 if (modrm
.mod
!= 3)
13965 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13967 putop (float_mem
[fp_indx
], sizeflag
);
13970 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13973 /* Skip mod/rm byte. */
13977 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13978 if (dp
->name
== NULL
)
13980 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13982 /* Instruction fnstsw is only one with strange arg. */
13983 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13984 strcpy (op_out
[0], names16
[0]);
13988 putop (dp
->name
, sizeflag
);
13993 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13998 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
14002 /* Like oappend (below), but S is a string starting with '%'.
14003 In Intel syntax, the '%' is elided. */
14005 oappend_maybe_intel (const char *s
)
14007 oappend (s
+ intel_syntax
);
14011 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14013 oappend_maybe_intel ("%st");
14017 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14019 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
14020 oappend_maybe_intel (scratchbuf
);
14023 /* Capital letters in template are macros. */
14025 putop (const char *in_template
, int sizeflag
)
14030 unsigned int l
= 0, len
= 1;
14033 #define SAVE_LAST(c) \
14034 if (l < len && l < sizeof (last)) \
14039 for (p
= in_template
; *p
; p
++)
14056 while (*++p
!= '|')
14057 if (*p
== '}' || *p
== '\0')
14060 /* Fall through. */
14065 while (*++p
!= '}')
14076 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14080 if (l
== 0 && len
== 1)
14085 if (sizeflag
& SUFFIX_ALWAYS
)
14098 if (address_mode
== mode_64bit
14099 && !(prefixes
& PREFIX_ADDR
))
14110 if (intel_syntax
&& !alt
)
14112 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14114 if (sizeflag
& DFLAG
)
14115 *obufp
++ = intel_syntax
? 'd' : 'l';
14117 *obufp
++ = intel_syntax
? 'w' : 's';
14118 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14122 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14125 if (modrm
.mod
== 3)
14131 if (sizeflag
& DFLAG
)
14132 *obufp
++ = intel_syntax
? 'd' : 'l';
14135 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14141 case 'E': /* For jcxz/jecxz */
14142 if (address_mode
== mode_64bit
)
14144 if (sizeflag
& AFLAG
)
14150 if (sizeflag
& AFLAG
)
14152 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14157 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
14159 if (sizeflag
& AFLAG
)
14160 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
14162 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
14163 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14167 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
14169 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14173 if (!(rex
& REX_W
))
14174 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14179 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
14180 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
14182 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
14185 if (prefixes
& PREFIX_DS
)
14204 if (l
!= 0 || len
!= 1)
14206 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14211 if (!need_vex
|| !vex
.evex
)
14214 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14216 switch (vex
.length
)
14234 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
14239 /* Fall through. */
14242 if (l
!= 0 || len
!= 1)
14250 if (sizeflag
& SUFFIX_ALWAYS
)
14254 if (intel_mnemonic
!= cond
)
14258 if ((prefixes
& PREFIX_FWAIT
) == 0)
14261 used_prefixes
|= PREFIX_FWAIT
;
14267 else if (intel_syntax
&& (sizeflag
& DFLAG
))
14271 if (!(rex
& REX_W
))
14272 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14276 && address_mode
== mode_64bit
14277 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14282 /* Fall through. */
14285 if (l
== 0 && len
== 1)
14290 if ((rex
& REX_W
) == 0
14291 && (prefixes
& PREFIX_DATA
))
14293 if ((sizeflag
& DFLAG
) == 0)
14295 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14299 if ((prefixes
& PREFIX_DATA
)
14301 || (sizeflag
& SUFFIX_ALWAYS
))
14308 if (sizeflag
& DFLAG
)
14312 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14318 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14324 if ((prefixes
& PREFIX_DATA
)
14326 || (sizeflag
& SUFFIX_ALWAYS
))
14333 if (sizeflag
& DFLAG
)
14334 *obufp
++ = intel_syntax
? 'd' : 'l';
14337 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14345 if (address_mode
== mode_64bit
14346 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14348 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14352 /* Fall through. */
14355 if (l
== 0 && len
== 1)
14358 if (intel_syntax
&& !alt
)
14361 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14367 if (sizeflag
& DFLAG
)
14368 *obufp
++ = intel_syntax
? 'd' : 'l';
14371 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14377 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14383 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
14398 else if (sizeflag
& DFLAG
)
14407 if (intel_syntax
&& !p
[1]
14408 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
14410 if (!(rex
& REX_W
))
14411 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14414 if (l
== 0 && len
== 1)
14418 if (address_mode
== mode_64bit
14419 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14421 if (sizeflag
& SUFFIX_ALWAYS
)
14443 /* Fall through. */
14446 if (l
== 0 && len
== 1)
14451 if (sizeflag
& SUFFIX_ALWAYS
)
14457 if (sizeflag
& DFLAG
)
14461 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14475 if (address_mode
== mode_64bit
14476 && !(prefixes
& PREFIX_ADDR
))
14487 if (l
!= 0 || len
!= 1)
14492 if (need_vex
&& vex
.prefix
)
14494 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
14501 if (prefixes
& PREFIX_DATA
)
14505 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14509 if (l
== 0 && len
== 1)
14511 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14522 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14530 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14532 switch (vex
.length
)
14548 if (l
== 0 && len
== 1)
14550 /* operand size flag for cwtl, cbtw */
14559 else if (sizeflag
& DFLAG
)
14563 if (!(rex
& REX_W
))
14564 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14571 && last
[0] != 'L'))
14578 if (last
[0] == 'X')
14579 *obufp
++ = vex
.w
? 'd': 's';
14581 *obufp
++ = vex
.w
? 'q': 'd';
14587 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14589 if (sizeflag
& DFLAG
)
14593 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14599 if (address_mode
== mode_64bit
14600 && (isa64
== intel64
14601 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
14603 else if ((prefixes
& PREFIX_DATA
))
14605 if (!(sizeflag
& DFLAG
))
14607 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14614 mnemonicendp
= obufp
;
14619 oappend (const char *s
)
14621 obufp
= stpcpy (obufp
, s
);
14627 /* Only print the active segment register. */
14628 if (!active_seg_prefix
)
14631 used_prefixes
|= active_seg_prefix
;
14632 switch (active_seg_prefix
)
14635 oappend_maybe_intel ("%cs:");
14638 oappend_maybe_intel ("%ds:");
14641 oappend_maybe_intel ("%ss:");
14644 oappend_maybe_intel ("%es:");
14647 oappend_maybe_intel ("%fs:");
14650 oappend_maybe_intel ("%gs:");
14658 OP_indirE (int bytemode
, int sizeflag
)
14662 OP_E (bytemode
, sizeflag
);
14666 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
14668 if (address_mode
== mode_64bit
)
14676 sprintf_vma (tmp
, disp
);
14677 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
14678 strcpy (buf
+ 2, tmp
+ i
);
14682 bfd_signed_vma v
= disp
;
14689 /* Check for possible overflow on 0x8000000000000000. */
14692 strcpy (buf
, "9223372036854775808");
14706 tmp
[28 - i
] = (v
% 10) + '0';
14710 strcpy (buf
, tmp
+ 29 - i
);
14716 sprintf (buf
, "0x%x", (unsigned int) disp
);
14718 sprintf (buf
, "%d", (int) disp
);
14722 /* Put DISP in BUF as signed hex number. */
14725 print_displacement (char *buf
, bfd_vma disp
)
14727 bfd_signed_vma val
= disp
;
14736 /* Check for possible overflow. */
14739 switch (address_mode
)
14742 strcpy (buf
+ j
, "0x8000000000000000");
14745 strcpy (buf
+ j
, "0x80000000");
14748 strcpy (buf
+ j
, "0x8000");
14758 sprintf_vma (tmp
, (bfd_vma
) val
);
14759 for (i
= 0; tmp
[i
] == '0'; i
++)
14761 if (tmp
[i
] == '\0')
14763 strcpy (buf
+ j
, tmp
+ i
);
14767 intel_operand_size (int bytemode
, int sizeflag
)
14771 && (bytemode
== x_mode
14772 || bytemode
== evex_half_bcst_xmmq_mode
))
14775 oappend ("QWORD PTR ");
14777 oappend ("DWORD PTR ");
14786 oappend ("BYTE PTR ");
14791 case dqw_swap_mode
:
14792 oappend ("WORD PTR ");
14795 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14797 oappend ("QWORD PTR ");
14806 oappend ("QWORD PTR ");
14809 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14810 oappend ("DWORD PTR ");
14812 oappend ("WORD PTR ");
14813 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14817 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14819 oappend ("WORD PTR ");
14820 if (!(rex
& REX_W
))
14821 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14824 if (sizeflag
& DFLAG
)
14825 oappend ("QWORD PTR ");
14827 oappend ("DWORD PTR ");
14828 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14831 case d_scalar_mode
:
14832 case d_scalar_swap_mode
:
14835 oappend ("DWORD PTR ");
14838 case q_scalar_mode
:
14839 case q_scalar_swap_mode
:
14841 oappend ("QWORD PTR ");
14844 if (address_mode
== mode_64bit
)
14845 oappend ("QWORD PTR ");
14847 oappend ("DWORD PTR ");
14850 if (sizeflag
& DFLAG
)
14851 oappend ("FWORD PTR ");
14853 oappend ("DWORD PTR ");
14854 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14857 oappend ("TBYTE PTR ");
14861 case evex_x_gscat_mode
:
14862 case evex_x_nobcst_mode
:
14865 switch (vex
.length
)
14868 oappend ("XMMWORD PTR ");
14871 oappend ("YMMWORD PTR ");
14874 oappend ("ZMMWORD PTR ");
14881 oappend ("XMMWORD PTR ");
14884 oappend ("XMMWORD PTR ");
14887 oappend ("YMMWORD PTR ");
14890 case evex_half_bcst_xmmq_mode
:
14894 switch (vex
.length
)
14897 oappend ("QWORD PTR ");
14900 oappend ("XMMWORD PTR ");
14903 oappend ("YMMWORD PTR ");
14913 switch (vex
.length
)
14918 oappend ("BYTE PTR ");
14928 switch (vex
.length
)
14933 oappend ("WORD PTR ");
14943 switch (vex
.length
)
14948 oappend ("DWORD PTR ");
14958 switch (vex
.length
)
14963 oappend ("QWORD PTR ");
14973 switch (vex
.length
)
14976 oappend ("WORD PTR ");
14979 oappend ("DWORD PTR ");
14982 oappend ("QWORD PTR ");
14992 switch (vex
.length
)
14995 oappend ("DWORD PTR ");
14998 oappend ("QWORD PTR ");
15001 oappend ("XMMWORD PTR ");
15011 switch (vex
.length
)
15014 oappend ("QWORD PTR ");
15017 oappend ("YMMWORD PTR ");
15020 oappend ("ZMMWORD PTR ");
15030 switch (vex
.length
)
15034 oappend ("XMMWORD PTR ");
15041 oappend ("OWORD PTR ");
15044 case vex_w_dq_mode
:
15045 case vex_scalar_w_dq_mode
:
15050 oappend ("QWORD PTR ");
15052 oappend ("DWORD PTR ");
15054 case vex_vsib_d_w_dq_mode
:
15055 case vex_vsib_q_w_dq_mode
:
15062 oappend ("QWORD PTR ");
15064 oappend ("DWORD PTR ");
15068 switch (vex
.length
)
15071 oappend ("XMMWORD PTR ");
15074 oappend ("YMMWORD PTR ");
15077 oappend ("ZMMWORD PTR ");
15084 case vex_vsib_q_w_d_mode
:
15085 case vex_vsib_d_w_d_mode
:
15086 if (!need_vex
|| !vex
.evex
)
15089 switch (vex
.length
)
15092 oappend ("QWORD PTR ");
15095 oappend ("XMMWORD PTR ");
15098 oappend ("YMMWORD PTR ");
15106 if (!need_vex
|| vex
.length
!= 128)
15109 oappend ("DWORD PTR ");
15111 oappend ("BYTE PTR ");
15117 oappend ("QWORD PTR ");
15119 oappend ("WORD PTR ");
15128 OP_E_register (int bytemode
, int sizeflag
)
15130 int reg
= modrm
.rm
;
15131 const char **names
;
15137 if ((sizeflag
& SUFFIX_ALWAYS
)
15138 && (bytemode
== b_swap_mode
15139 || bytemode
== v_swap_mode
15140 || bytemode
== dqw_swap_mode
))
15166 names
= address_mode
== mode_64bit
? names64
: names32
;
15172 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15185 case dqw_swap_mode
:
15191 if ((sizeflag
& DFLAG
)
15192 || (bytemode
!= v_mode
15193 && bytemode
!= v_swap_mode
))
15197 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15202 names
= names_mask
;
15207 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15210 oappend (names
[reg
]);
15214 OP_E_memory (int bytemode
, int sizeflag
)
15217 int add
= (rex
& REX_B
) ? 8 : 0;
15223 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15225 && bytemode
!= x_mode
15226 && bytemode
!= xmmq_mode
15227 && bytemode
!= evex_half_bcst_xmmq_mode
)
15236 case dqw_swap_mode
:
15243 case vex_vsib_d_w_dq_mode
:
15244 case vex_vsib_d_w_d_mode
:
15245 case vex_vsib_q_w_dq_mode
:
15246 case vex_vsib_q_w_d_mode
:
15247 case evex_x_gscat_mode
:
15249 shift
= vex
.w
? 3 : 2;
15252 case evex_half_bcst_xmmq_mode
:
15256 shift
= vex
.w
? 3 : 2;
15259 /* Fall through if vex.b == 0. */
15263 case evex_x_nobcst_mode
:
15265 switch (vex
.length
)
15288 case q_scalar_mode
:
15290 case q_scalar_swap_mode
:
15296 case d_scalar_mode
:
15298 case d_scalar_swap_mode
:
15310 /* Make necessary corrections to shift for modes that need it.
15311 For these modes we currently have shift 4, 5 or 6 depending on
15312 vex.length (it corresponds to xmmword, ymmword or zmmword
15313 operand). We might want to make it 3, 4 or 5 (e.g. for
15314 xmmq_mode). In case of broadcast enabled the corrections
15315 aren't needed, as element size is always 32 or 64 bits. */
15317 && (bytemode
== xmmq_mode
15318 || bytemode
== evex_half_bcst_xmmq_mode
))
15320 else if (bytemode
== xmmqd_mode
)
15322 else if (bytemode
== xmmdw_mode
)
15324 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
15332 intel_operand_size (bytemode
, sizeflag
);
15335 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15337 /* 32/64 bit address mode */
15346 int addr32flag
= !((sizeflag
& AFLAG
)
15347 || bytemode
== v_bnd_mode
15348 || bytemode
== bnd_mode
);
15349 const char **indexes64
= names64
;
15350 const char **indexes32
= names32
;
15360 vindex
= sib
.index
;
15366 case vex_vsib_d_w_dq_mode
:
15367 case vex_vsib_d_w_d_mode
:
15368 case vex_vsib_q_w_dq_mode
:
15369 case vex_vsib_q_w_d_mode
:
15379 switch (vex
.length
)
15382 indexes64
= indexes32
= names_xmm
;
15386 || bytemode
== vex_vsib_q_w_dq_mode
15387 || bytemode
== vex_vsib_q_w_d_mode
)
15388 indexes64
= indexes32
= names_ymm
;
15390 indexes64
= indexes32
= names_xmm
;
15394 || bytemode
== vex_vsib_q_w_dq_mode
15395 || bytemode
== vex_vsib_q_w_d_mode
)
15396 indexes64
= indexes32
= names_zmm
;
15398 indexes64
= indexes32
= names_ymm
;
15405 haveindex
= vindex
!= 4;
15412 rbase
= base
+ add
;
15420 if (address_mode
== mode_64bit
&& !havesib
)
15426 FETCH_DATA (the_info
, codep
+ 1);
15428 if ((disp
& 0x80) != 0)
15430 if (vex
.evex
&& shift
> 0)
15438 /* In 32bit mode, we need index register to tell [offset] from
15439 [eiz*1 + offset]. */
15440 needindex
= (havesib
15443 && address_mode
== mode_32bit
);
15444 havedisp
= (havebase
15446 || (havesib
&& (haveindex
|| scale
!= 0)));
15449 if (modrm
.mod
!= 0 || base
== 5)
15451 if (havedisp
|| riprel
)
15452 print_displacement (scratchbuf
, disp
);
15454 print_operand_value (scratchbuf
, 1, disp
);
15455 oappend (scratchbuf
);
15459 oappend (sizeflag
& AFLAG
? "(%rip)" : "(%eip)");
15463 if ((havebase
|| haveindex
|| riprel
)
15464 && (bytemode
!= v_bnd_mode
)
15465 && (bytemode
!= bnd_mode
))
15466 used_prefixes
|= PREFIX_ADDR
;
15468 if (havedisp
|| (intel_syntax
&& riprel
))
15470 *obufp
++ = open_char
;
15471 if (intel_syntax
&& riprel
)
15474 oappend (sizeflag
& AFLAG
? "rip" : "eip");
15478 oappend (address_mode
== mode_64bit
&& !addr32flag
15479 ? names64
[rbase
] : names32
[rbase
]);
15482 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15483 print index to tell base + index from base. */
15487 || (havebase
&& base
!= ESP_REG_NUM
))
15489 if (!intel_syntax
|| havebase
)
15491 *obufp
++ = separator_char
;
15495 oappend (address_mode
== mode_64bit
&& !addr32flag
15496 ? indexes64
[vindex
] : indexes32
[vindex
]);
15498 oappend (address_mode
== mode_64bit
&& !addr32flag
15499 ? index64
: index32
);
15501 *obufp
++ = scale_char
;
15503 sprintf (scratchbuf
, "%d", 1 << scale
);
15504 oappend (scratchbuf
);
15508 && (disp
|| modrm
.mod
!= 0 || base
== 5))
15510 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
15515 else if (modrm
.mod
!= 1 && disp
!= -disp
)
15519 disp
= - (bfd_signed_vma
) disp
;
15523 print_displacement (scratchbuf
, disp
);
15525 print_operand_value (scratchbuf
, 1, disp
);
15526 oappend (scratchbuf
);
15529 *obufp
++ = close_char
;
15532 else if (intel_syntax
)
15534 if (modrm
.mod
!= 0 || base
== 5)
15536 if (!active_seg_prefix
)
15538 oappend (names_seg
[ds_reg
- es_reg
]);
15541 print_operand_value (scratchbuf
, 1, disp
);
15542 oappend (scratchbuf
);
15548 /* 16 bit address mode */
15549 used_prefixes
|= prefixes
& PREFIX_ADDR
;
15556 if ((disp
& 0x8000) != 0)
15561 FETCH_DATA (the_info
, codep
+ 1);
15563 if ((disp
& 0x80) != 0)
15568 if ((disp
& 0x8000) != 0)
15574 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
15576 print_displacement (scratchbuf
, disp
);
15577 oappend (scratchbuf
);
15580 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
15582 *obufp
++ = open_char
;
15584 oappend (index16
[modrm
.rm
]);
15586 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
15588 if ((bfd_signed_vma
) disp
>= 0)
15593 else if (modrm
.mod
!= 1)
15597 disp
= - (bfd_signed_vma
) disp
;
15600 print_displacement (scratchbuf
, disp
);
15601 oappend (scratchbuf
);
15604 *obufp
++ = close_char
;
15607 else if (intel_syntax
)
15609 if (!active_seg_prefix
)
15611 oappend (names_seg
[ds_reg
- es_reg
]);
15614 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
15615 oappend (scratchbuf
);
15618 if (vex
.evex
&& vex
.b
15619 && (bytemode
== x_mode
15620 || bytemode
== xmmq_mode
15621 || bytemode
== evex_half_bcst_xmmq_mode
))
15624 || bytemode
== xmmq_mode
15625 || bytemode
== evex_half_bcst_xmmq_mode
)
15627 switch (vex
.length
)
15630 oappend ("{1to2}");
15633 oappend ("{1to4}");
15636 oappend ("{1to8}");
15644 switch (vex
.length
)
15647 oappend ("{1to4}");
15650 oappend ("{1to8}");
15653 oappend ("{1to16}");
15663 OP_E (int bytemode
, int sizeflag
)
15665 /* Skip mod/rm byte. */
15669 if (modrm
.mod
== 3)
15670 OP_E_register (bytemode
, sizeflag
);
15672 OP_E_memory (bytemode
, sizeflag
);
15676 OP_G (int bytemode
, int sizeflag
)
15687 oappend (names8rex
[modrm
.reg
+ add
]);
15689 oappend (names8
[modrm
.reg
+ add
]);
15692 oappend (names16
[modrm
.reg
+ add
]);
15697 oappend (names32
[modrm
.reg
+ add
]);
15700 oappend (names64
[modrm
.reg
+ add
]);
15703 oappend (names_bnd
[modrm
.reg
]);
15710 case dqw_swap_mode
:
15713 oappend (names64
[modrm
.reg
+ add
]);
15716 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
15717 oappend (names32
[modrm
.reg
+ add
]);
15719 oappend (names16
[modrm
.reg
+ add
]);
15720 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15724 if (address_mode
== mode_64bit
)
15725 oappend (names64
[modrm
.reg
+ add
]);
15727 oappend (names32
[modrm
.reg
+ add
]);
15731 oappend (names_mask
[modrm
.reg
+ add
]);
15734 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15747 FETCH_DATA (the_info
, codep
+ 8);
15748 a
= *codep
++ & 0xff;
15749 a
|= (*codep
++ & 0xff) << 8;
15750 a
|= (*codep
++ & 0xff) << 16;
15751 a
|= (*codep
++ & 0xffu
) << 24;
15752 b
= *codep
++ & 0xff;
15753 b
|= (*codep
++ & 0xff) << 8;
15754 b
|= (*codep
++ & 0xff) << 16;
15755 b
|= (*codep
++ & 0xffu
) << 24;
15756 x
= a
+ ((bfd_vma
) b
<< 32);
15764 static bfd_signed_vma
15767 bfd_signed_vma x
= 0;
15769 FETCH_DATA (the_info
, codep
+ 4);
15770 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15771 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15772 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15773 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15777 static bfd_signed_vma
15780 bfd_signed_vma x
= 0;
15782 FETCH_DATA (the_info
, codep
+ 4);
15783 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15784 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15785 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15786 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15788 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15798 FETCH_DATA (the_info
, codep
+ 2);
15799 x
= *codep
++ & 0xff;
15800 x
|= (*codep
++ & 0xff) << 8;
15805 set_op (bfd_vma op
, int riprel
)
15807 op_index
[op_ad
] = op_ad
;
15808 if (address_mode
== mode_64bit
)
15810 op_address
[op_ad
] = op
;
15811 op_riprel
[op_ad
] = riprel
;
15815 /* Mask to get a 32-bit address. */
15816 op_address
[op_ad
] = op
& 0xffffffff;
15817 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15822 OP_REG (int code
, int sizeflag
)
15829 case es_reg
: case ss_reg
: case cs_reg
:
15830 case ds_reg
: case fs_reg
: case gs_reg
:
15831 oappend (names_seg
[code
- es_reg
]);
15843 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15844 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15845 s
= names16
[code
- ax_reg
+ add
];
15847 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15848 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15851 s
= names8rex
[code
- al_reg
+ add
];
15853 s
= names8
[code
- al_reg
];
15855 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15856 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15857 if (address_mode
== mode_64bit
15858 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15860 s
= names64
[code
- rAX_reg
+ add
];
15863 code
+= eAX_reg
- rAX_reg
;
15864 /* Fall through. */
15865 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15866 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15869 s
= names64
[code
- eAX_reg
+ add
];
15872 if (sizeflag
& DFLAG
)
15873 s
= names32
[code
- eAX_reg
+ add
];
15875 s
= names16
[code
- eAX_reg
+ add
];
15876 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15880 s
= INTERNAL_DISASSEMBLER_ERROR
;
15887 OP_IMREG (int code
, int sizeflag
)
15899 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15900 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15901 s
= names16
[code
- ax_reg
];
15903 case es_reg
: case ss_reg
: case cs_reg
:
15904 case ds_reg
: case fs_reg
: case gs_reg
:
15905 s
= names_seg
[code
- es_reg
];
15907 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15908 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15911 s
= names8rex
[code
- al_reg
];
15913 s
= names8
[code
- al_reg
];
15915 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15916 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15919 s
= names64
[code
- eAX_reg
];
15922 if (sizeflag
& DFLAG
)
15923 s
= names32
[code
- eAX_reg
];
15925 s
= names16
[code
- eAX_reg
];
15926 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15929 case z_mode_ax_reg
:
15930 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
15934 if (!(rex
& REX_W
))
15935 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15938 s
= INTERNAL_DISASSEMBLER_ERROR
;
15945 OP_I (int bytemode
, int sizeflag
)
15948 bfd_signed_vma mask
= -1;
15953 FETCH_DATA (the_info
, codep
+ 1);
15958 if (address_mode
== mode_64bit
)
15963 /* Fall through. */
15970 if (sizeflag
& DFLAG
)
15980 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15992 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15997 scratchbuf
[0] = '$';
15998 print_operand_value (scratchbuf
+ 1, 1, op
);
15999 oappend_maybe_intel (scratchbuf
);
16000 scratchbuf
[0] = '\0';
16004 OP_I64 (int bytemode
, int sizeflag
)
16007 bfd_signed_vma mask
= -1;
16009 if (address_mode
!= mode_64bit
)
16011 OP_I (bytemode
, sizeflag
);
16018 FETCH_DATA (the_info
, codep
+ 1);
16028 if (sizeflag
& DFLAG
)
16038 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16046 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16051 scratchbuf
[0] = '$';
16052 print_operand_value (scratchbuf
+ 1, 1, op
);
16053 oappend_maybe_intel (scratchbuf
);
16054 scratchbuf
[0] = '\0';
16058 OP_sI (int bytemode
, int sizeflag
)
16066 FETCH_DATA (the_info
, codep
+ 1);
16068 if ((op
& 0x80) != 0)
16070 if (bytemode
== b_T_mode
)
16072 if (address_mode
!= mode_64bit
16073 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
16075 /* The operand-size prefix is overridden by a REX prefix. */
16076 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16084 if (!(rex
& REX_W
))
16086 if (sizeflag
& DFLAG
)
16094 /* The operand-size prefix is overridden by a REX prefix. */
16095 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16101 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16105 scratchbuf
[0] = '$';
16106 print_operand_value (scratchbuf
+ 1, 1, op
);
16107 oappend_maybe_intel (scratchbuf
);
16111 OP_J (int bytemode
, int sizeflag
)
16115 bfd_vma segment
= 0;
16120 FETCH_DATA (the_info
, codep
+ 1);
16122 if ((disp
& 0x80) != 0)
16126 if (isa64
== amd64
)
16128 if ((sizeflag
& DFLAG
)
16129 || (address_mode
== mode_64bit
16130 && (isa64
!= amd64
|| (rex
& REX_W
))))
16135 if ((disp
& 0x8000) != 0)
16137 /* In 16bit mode, address is wrapped around at 64k within
16138 the same segment. Otherwise, a data16 prefix on a jump
16139 instruction means that the pc is masked to 16 bits after
16140 the displacement is added! */
16142 if ((prefixes
& PREFIX_DATA
) == 0)
16143 segment
= ((start_pc
+ codep
- start_codep
)
16144 & ~((bfd_vma
) 0xffff));
16146 if (address_mode
!= mode_64bit
16147 || (isa64
== amd64
&& !(rex
& REX_W
)))
16148 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16151 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16154 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
16156 print_operand_value (scratchbuf
, 1, disp
);
16157 oappend (scratchbuf
);
16161 OP_SEG (int bytemode
, int sizeflag
)
16163 if (bytemode
== w_mode
)
16164 oappend (names_seg
[modrm
.reg
]);
16166 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
16170 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
16174 if (sizeflag
& DFLAG
)
16184 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16186 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
16188 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
16189 oappend (scratchbuf
);
16193 OP_OFF (int bytemode
, int sizeflag
)
16197 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16198 intel_operand_size (bytemode
, sizeflag
);
16201 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16208 if (!active_seg_prefix
)
16210 oappend (names_seg
[ds_reg
- es_reg
]);
16214 print_operand_value (scratchbuf
, 1, off
);
16215 oappend (scratchbuf
);
16219 OP_OFF64 (int bytemode
, int sizeflag
)
16223 if (address_mode
!= mode_64bit
16224 || (prefixes
& PREFIX_ADDR
))
16226 OP_OFF (bytemode
, sizeflag
);
16230 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16231 intel_operand_size (bytemode
, sizeflag
);
16238 if (!active_seg_prefix
)
16240 oappend (names_seg
[ds_reg
- es_reg
]);
16244 print_operand_value (scratchbuf
, 1, off
);
16245 oappend (scratchbuf
);
16249 ptr_reg (int code
, int sizeflag
)
16253 *obufp
++ = open_char
;
16254 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
16255 if (address_mode
== mode_64bit
)
16257 if (!(sizeflag
& AFLAG
))
16258 s
= names32
[code
- eAX_reg
];
16260 s
= names64
[code
- eAX_reg
];
16262 else if (sizeflag
& AFLAG
)
16263 s
= names32
[code
- eAX_reg
];
16265 s
= names16
[code
- eAX_reg
];
16267 *obufp
++ = close_char
;
16272 OP_ESreg (int code
, int sizeflag
)
16278 case 0x6d: /* insw/insl */
16279 intel_operand_size (z_mode
, sizeflag
);
16281 case 0xa5: /* movsw/movsl/movsq */
16282 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16283 case 0xab: /* stosw/stosl */
16284 case 0xaf: /* scasw/scasl */
16285 intel_operand_size (v_mode
, sizeflag
);
16288 intel_operand_size (b_mode
, sizeflag
);
16291 oappend_maybe_intel ("%es:");
16292 ptr_reg (code
, sizeflag
);
16296 OP_DSreg (int code
, int sizeflag
)
16302 case 0x6f: /* outsw/outsl */
16303 intel_operand_size (z_mode
, sizeflag
);
16305 case 0xa5: /* movsw/movsl/movsq */
16306 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16307 case 0xad: /* lodsw/lodsl/lodsq */
16308 intel_operand_size (v_mode
, sizeflag
);
16311 intel_operand_size (b_mode
, sizeflag
);
16314 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16315 default segment register DS is printed. */
16316 if (!active_seg_prefix
)
16317 active_seg_prefix
= PREFIX_DS
;
16319 ptr_reg (code
, sizeflag
);
16323 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16331 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
16333 all_prefixes
[last_lock_prefix
] = 0;
16334 used_prefixes
|= PREFIX_LOCK
;
16339 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
16340 oappend_maybe_intel (scratchbuf
);
16344 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16353 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
16355 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
16356 oappend (scratchbuf
);
16360 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16362 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
16363 oappend_maybe_intel (scratchbuf
);
16367 OP_R (int bytemode
, int sizeflag
)
16369 /* Skip mod/rm byte. */
16372 OP_E_register (bytemode
, sizeflag
);
16376 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16378 int reg
= modrm
.reg
;
16379 const char **names
;
16381 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16382 if (prefixes
& PREFIX_DATA
)
16391 oappend (names
[reg
]);
16395 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16397 int reg
= modrm
.reg
;
16398 const char **names
;
16410 && bytemode
!= xmm_mode
16411 && bytemode
!= xmmq_mode
16412 && bytemode
!= evex_half_bcst_xmmq_mode
16413 && bytemode
!= ymm_mode
16414 && bytemode
!= scalar_mode
)
16416 switch (vex
.length
)
16423 || (bytemode
!= vex_vsib_q_w_dq_mode
16424 && bytemode
!= vex_vsib_q_w_d_mode
))
16436 else if (bytemode
== xmmq_mode
16437 || bytemode
== evex_half_bcst_xmmq_mode
)
16439 switch (vex
.length
)
16452 else if (bytemode
== ymm_mode
)
16456 oappend (names
[reg
]);
16460 OP_EM (int bytemode
, int sizeflag
)
16463 const char **names
;
16465 if (modrm
.mod
!= 3)
16468 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16470 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16471 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16473 OP_E (bytemode
, sizeflag
);
16477 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
16480 /* Skip mod/rm byte. */
16483 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16485 if (prefixes
& PREFIX_DATA
)
16494 oappend (names
[reg
]);
16497 /* cvt* are the only instructions in sse2 which have
16498 both SSE and MMX operands and also have 0x66 prefix
16499 in their opcode. 0x66 was originally used to differentiate
16500 between SSE and MMX instruction(operands). So we have to handle the
16501 cvt* separately using OP_EMC and OP_MXC */
16503 OP_EMC (int bytemode
, int sizeflag
)
16505 if (modrm
.mod
!= 3)
16507 if (intel_syntax
&& bytemode
== v_mode
)
16509 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16510 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16512 OP_E (bytemode
, sizeflag
);
16516 /* Skip mod/rm byte. */
16519 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16520 oappend (names_mm
[modrm
.rm
]);
16524 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16526 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16527 oappend (names_mm
[modrm
.reg
]);
16531 OP_EX (int bytemode
, int sizeflag
)
16534 const char **names
;
16536 /* Skip mod/rm byte. */
16540 if (modrm
.mod
!= 3)
16542 OP_E_memory (bytemode
, sizeflag
);
16557 if ((sizeflag
& SUFFIX_ALWAYS
)
16558 && (bytemode
== x_swap_mode
16559 || bytemode
== d_swap_mode
16560 || bytemode
== dqw_swap_mode
16561 || bytemode
== d_scalar_swap_mode
16562 || bytemode
== q_swap_mode
16563 || bytemode
== q_scalar_swap_mode
))
16567 && bytemode
!= xmm_mode
16568 && bytemode
!= xmmdw_mode
16569 && bytemode
!= xmmqd_mode
16570 && bytemode
!= xmm_mb_mode
16571 && bytemode
!= xmm_mw_mode
16572 && bytemode
!= xmm_md_mode
16573 && bytemode
!= xmm_mq_mode
16574 && bytemode
!= xmm_mdq_mode
16575 && bytemode
!= xmmq_mode
16576 && bytemode
!= evex_half_bcst_xmmq_mode
16577 && bytemode
!= ymm_mode
16578 && bytemode
!= d_scalar_mode
16579 && bytemode
!= d_scalar_swap_mode
16580 && bytemode
!= q_scalar_mode
16581 && bytemode
!= q_scalar_swap_mode
16582 && bytemode
!= vex_scalar_w_dq_mode
)
16584 switch (vex
.length
)
16599 else if (bytemode
== xmmq_mode
16600 || bytemode
== evex_half_bcst_xmmq_mode
)
16602 switch (vex
.length
)
16615 else if (bytemode
== ymm_mode
)
16619 oappend (names
[reg
]);
16623 OP_MS (int bytemode
, int sizeflag
)
16625 if (modrm
.mod
== 3)
16626 OP_EM (bytemode
, sizeflag
);
16632 OP_XS (int bytemode
, int sizeflag
)
16634 if (modrm
.mod
== 3)
16635 OP_EX (bytemode
, sizeflag
);
16641 OP_M (int bytemode
, int sizeflag
)
16643 if (modrm
.mod
== 3)
16644 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16647 OP_E (bytemode
, sizeflag
);
16651 OP_0f07 (int bytemode
, int sizeflag
)
16653 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
16656 OP_E (bytemode
, sizeflag
);
16659 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16660 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16663 NOP_Fixup1 (int bytemode
, int sizeflag
)
16665 if ((prefixes
& PREFIX_DATA
) != 0
16668 && address_mode
== mode_64bit
))
16669 OP_REG (bytemode
, sizeflag
);
16671 strcpy (obuf
, "nop");
16675 NOP_Fixup2 (int bytemode
, int sizeflag
)
16677 if ((prefixes
& PREFIX_DATA
) != 0
16680 && address_mode
== mode_64bit
))
16681 OP_IMREG (bytemode
, sizeflag
);
16684 static const char *const Suffix3DNow
[] = {
16685 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16686 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16687 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16688 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16689 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16690 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16691 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16692 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16693 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16694 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16695 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16696 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16697 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16698 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16699 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16700 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16701 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16702 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16703 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16704 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16705 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16706 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16707 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16708 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16709 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16710 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16711 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16712 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16713 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16714 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16715 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16716 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16717 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16718 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16719 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16720 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16721 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16722 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16723 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16724 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16725 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16726 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16727 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16728 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16729 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16730 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16731 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16732 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16733 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16734 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16735 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16736 /* CC */ NULL
, NULL
, NULL
, NULL
,
16737 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16738 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16739 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16740 /* DC */ NULL
, NULL
, NULL
, NULL
,
16741 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16742 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16743 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16744 /* EC */ NULL
, NULL
, NULL
, NULL
,
16745 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16746 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16747 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16748 /* FC */ NULL
, NULL
, NULL
, NULL
,
16752 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16754 const char *mnemonic
;
16756 FETCH_DATA (the_info
, codep
+ 1);
16757 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16758 place where an 8-bit immediate would normally go. ie. the last
16759 byte of the instruction. */
16760 obufp
= mnemonicendp
;
16761 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16763 oappend (mnemonic
);
16766 /* Since a variable sized modrm/sib chunk is between the start
16767 of the opcode (0x0f0f) and the opcode suffix, we need to do
16768 all the modrm processing first, and don't know until now that
16769 we have a bad opcode. This necessitates some cleaning up. */
16770 op_out
[0][0] = '\0';
16771 op_out
[1][0] = '\0';
16774 mnemonicendp
= obufp
;
16777 static struct op simd_cmp_op
[] =
16779 { STRING_COMMA_LEN ("eq") },
16780 { STRING_COMMA_LEN ("lt") },
16781 { STRING_COMMA_LEN ("le") },
16782 { STRING_COMMA_LEN ("unord") },
16783 { STRING_COMMA_LEN ("neq") },
16784 { STRING_COMMA_LEN ("nlt") },
16785 { STRING_COMMA_LEN ("nle") },
16786 { STRING_COMMA_LEN ("ord") }
16790 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16792 unsigned int cmp_type
;
16794 FETCH_DATA (the_info
, codep
+ 1);
16795 cmp_type
= *codep
++ & 0xff;
16796 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16799 char *p
= mnemonicendp
- 2;
16803 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16804 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16808 /* We have a reserved extension byte. Output it directly. */
16809 scratchbuf
[0] = '$';
16810 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16811 oappend_maybe_intel (scratchbuf
);
16812 scratchbuf
[0] = '\0';
16817 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
16818 int sizeflag ATTRIBUTE_UNUSED
)
16820 /* mwaitx %eax,%ecx,%ebx */
16823 const char **names
= (address_mode
== mode_64bit
16824 ? names64
: names32
);
16825 strcpy (op_out
[0], names
[0]);
16826 strcpy (op_out
[1], names
[1]);
16827 strcpy (op_out
[2], names
[3]);
16828 two_source_ops
= 1;
16830 /* Skip mod/rm byte. */
16836 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
16837 int sizeflag ATTRIBUTE_UNUSED
)
16839 /* mwait %eax,%ecx */
16842 const char **names
= (address_mode
== mode_64bit
16843 ? names64
: names32
);
16844 strcpy (op_out
[0], names
[0]);
16845 strcpy (op_out
[1], names
[1]);
16846 two_source_ops
= 1;
16848 /* Skip mod/rm byte. */
16854 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16855 int sizeflag ATTRIBUTE_UNUSED
)
16857 /* monitor %eax,%ecx,%edx" */
16860 const char **op1_names
;
16861 const char **names
= (address_mode
== mode_64bit
16862 ? names64
: names32
);
16864 if (!(prefixes
& PREFIX_ADDR
))
16865 op1_names
= (address_mode
== mode_16bit
16866 ? names16
: names
);
16869 /* Remove "addr16/addr32". */
16870 all_prefixes
[last_addr_prefix
] = 0;
16871 op1_names
= (address_mode
!= mode_32bit
16872 ? names32
: names16
);
16873 used_prefixes
|= PREFIX_ADDR
;
16875 strcpy (op_out
[0], op1_names
[0]);
16876 strcpy (op_out
[1], names
[1]);
16877 strcpy (op_out
[2], names
[2]);
16878 two_source_ops
= 1;
16880 /* Skip mod/rm byte. */
16888 /* Throw away prefixes and 1st. opcode byte. */
16889 codep
= insn_codep
+ 1;
16894 REP_Fixup (int bytemode
, int sizeflag
)
16896 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16898 if (prefixes
& PREFIX_REPZ
)
16899 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16906 OP_IMREG (bytemode
, sizeflag
);
16909 OP_ESreg (bytemode
, sizeflag
);
16912 OP_DSreg (bytemode
, sizeflag
);
16920 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16924 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16926 if (prefixes
& PREFIX_REPNZ
)
16927 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16930 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16931 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16935 HLE_Fixup1 (int bytemode
, int sizeflag
)
16938 && (prefixes
& PREFIX_LOCK
) != 0)
16940 if (prefixes
& PREFIX_REPZ
)
16941 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16942 if (prefixes
& PREFIX_REPNZ
)
16943 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16946 OP_E (bytemode
, sizeflag
);
16949 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16950 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16954 HLE_Fixup2 (int bytemode
, int sizeflag
)
16956 if (modrm
.mod
!= 3)
16958 if (prefixes
& PREFIX_REPZ
)
16959 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16960 if (prefixes
& PREFIX_REPNZ
)
16961 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16964 OP_E (bytemode
, sizeflag
);
16967 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16968 "xrelease" for memory operand. No check for LOCK prefix. */
16971 HLE_Fixup3 (int bytemode
, int sizeflag
)
16974 && last_repz_prefix
> last_repnz_prefix
16975 && (prefixes
& PREFIX_REPZ
) != 0)
16976 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16978 OP_E (bytemode
, sizeflag
);
16982 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
16987 /* Change cmpxchg8b to cmpxchg16b. */
16988 char *p
= mnemonicendp
- 2;
16989 mnemonicendp
= stpcpy (p
, "16b");
16992 else if ((prefixes
& PREFIX_LOCK
) != 0)
16994 if (prefixes
& PREFIX_REPZ
)
16995 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16996 if (prefixes
& PREFIX_REPNZ
)
16997 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
17000 OP_M (bytemode
, sizeflag
);
17004 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
17006 const char **names
;
17010 switch (vex
.length
)
17024 oappend (names
[reg
]);
17028 CRC32_Fixup (int bytemode
, int sizeflag
)
17030 /* Add proper suffix to "crc32". */
17031 char *p
= mnemonicendp
;
17050 if (sizeflag
& DFLAG
)
17054 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17058 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17065 if (modrm
.mod
== 3)
17069 /* Skip mod/rm byte. */
17074 add
= (rex
& REX_B
) ? 8 : 0;
17075 if (bytemode
== b_mode
)
17079 oappend (names8rex
[modrm
.rm
+ add
]);
17081 oappend (names8
[modrm
.rm
+ add
]);
17087 oappend (names64
[modrm
.rm
+ add
]);
17088 else if ((prefixes
& PREFIX_DATA
))
17089 oappend (names16
[modrm
.rm
+ add
]);
17091 oappend (names32
[modrm
.rm
+ add
]);
17095 OP_E (bytemode
, sizeflag
);
17099 FXSAVE_Fixup (int bytemode
, int sizeflag
)
17101 /* Add proper suffix to "fxsave" and "fxrstor". */
17105 char *p
= mnemonicendp
;
17111 OP_M (bytemode
, sizeflag
);
17114 /* Display the destination register operand for instructions with
17118 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17121 const char **names
;
17129 reg
= vex
.register_specifier
;
17136 if (bytemode
== vex_scalar_mode
)
17138 oappend (names_xmm
[reg
]);
17142 switch (vex
.length
)
17149 case vex_vsib_q_w_dq_mode
:
17150 case vex_vsib_q_w_d_mode
:
17161 names
= names_mask
;
17175 case vex_vsib_q_w_dq_mode
:
17176 case vex_vsib_q_w_d_mode
:
17177 names
= vex
.w
? names_ymm
: names_xmm
;
17181 names
= names_mask
;
17195 oappend (names
[reg
]);
17198 /* Get the VEX immediate byte without moving codep. */
17200 static unsigned char
17201 get_vex_imm8 (int sizeflag
, int opnum
)
17203 int bytes_before_imm
= 0;
17205 if (modrm
.mod
!= 3)
17207 /* There are SIB/displacement bytes. */
17208 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
17210 /* 32/64 bit address mode */
17211 int base
= modrm
.rm
;
17213 /* Check SIB byte. */
17216 FETCH_DATA (the_info
, codep
+ 1);
17218 /* When decoding the third source, don't increase
17219 bytes_before_imm as this has already been incremented
17220 by one in OP_E_memory while decoding the second
17223 bytes_before_imm
++;
17226 /* Don't increase bytes_before_imm when decoding the third source,
17227 it has already been incremented by OP_E_memory while decoding
17228 the second source operand. */
17234 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17235 SIB == 5, there is a 4 byte displacement. */
17237 /* No displacement. */
17240 /* 4 byte displacement. */
17241 bytes_before_imm
+= 4;
17244 /* 1 byte displacement. */
17245 bytes_before_imm
++;
17252 /* 16 bit address mode */
17253 /* Don't increase bytes_before_imm when decoding the third source,
17254 it has already been incremented by OP_E_memory while decoding
17255 the second source operand. */
17261 /* When modrm.rm == 6, there is a 2 byte displacement. */
17263 /* No displacement. */
17266 /* 2 byte displacement. */
17267 bytes_before_imm
+= 2;
17270 /* 1 byte displacement: when decoding the third source,
17271 don't increase bytes_before_imm as this has already
17272 been incremented by one in OP_E_memory while decoding
17273 the second source operand. */
17275 bytes_before_imm
++;
17283 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
17284 return codep
[bytes_before_imm
];
17288 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
17290 const char **names
;
17292 if (reg
== -1 && modrm
.mod
!= 3)
17294 OP_E_memory (bytemode
, sizeflag
);
17306 else if (reg
> 7 && address_mode
!= mode_64bit
)
17310 switch (vex
.length
)
17321 oappend (names
[reg
]);
17325 OP_EX_VexImmW (int bytemode
, int sizeflag
)
17328 static unsigned char vex_imm8
;
17330 if (vex_w_done
== 0)
17334 /* Skip mod/rm byte. */
17338 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
17341 reg
= vex_imm8
>> 4;
17343 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17345 else if (vex_w_done
== 1)
17350 reg
= vex_imm8
>> 4;
17352 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17356 /* Output the imm8 directly. */
17357 scratchbuf
[0] = '$';
17358 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
17359 oappend_maybe_intel (scratchbuf
);
17360 scratchbuf
[0] = '\0';
17366 OP_Vex_2src (int bytemode
, int sizeflag
)
17368 if (modrm
.mod
== 3)
17370 int reg
= modrm
.rm
;
17374 oappend (names_xmm
[reg
]);
17379 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
17381 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
17382 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17384 OP_E (bytemode
, sizeflag
);
17389 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
17391 if (modrm
.mod
== 3)
17393 /* Skip mod/rm byte. */
17399 oappend (names_xmm
[vex
.register_specifier
]);
17401 OP_Vex_2src (bytemode
, sizeflag
);
17405 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
17408 OP_Vex_2src (bytemode
, sizeflag
);
17410 oappend (names_xmm
[vex
.register_specifier
]);
17414 OP_EX_VexW (int bytemode
, int sizeflag
)
17422 /* Skip mod/rm byte. */
17427 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
17432 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
17435 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17439 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17440 int sizeflag ATTRIBUTE_UNUSED
)
17442 /* Skip the immediate byte and check for invalid bits. */
17443 FETCH_DATA (the_info
, codep
+ 1);
17444 if (*codep
++ & 0xf)
17449 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17452 const char **names
;
17454 FETCH_DATA (the_info
, codep
+ 1);
17457 if (bytemode
!= x_mode
)
17464 if (reg
> 7 && address_mode
!= mode_64bit
)
17467 switch (vex
.length
)
17478 oappend (names
[reg
]);
17482 OP_XMM_VexW (int bytemode
, int sizeflag
)
17484 /* Turn off the REX.W bit since it is used for swapping operands
17487 OP_XMM (bytemode
, sizeflag
);
17491 OP_EX_Vex (int bytemode
, int sizeflag
)
17493 if (modrm
.mod
!= 3)
17495 if (vex
.register_specifier
!= 0)
17499 OP_EX (bytemode
, sizeflag
);
17503 OP_XMM_Vex (int bytemode
, int sizeflag
)
17505 if (modrm
.mod
!= 3)
17507 if (vex
.register_specifier
!= 0)
17511 OP_XMM (bytemode
, sizeflag
);
17515 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17517 switch (vex
.length
)
17520 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
17523 mnemonicendp
= stpcpy (obuf
, "vzeroall");
17530 static struct op vex_cmp_op
[] =
17532 { STRING_COMMA_LEN ("eq") },
17533 { STRING_COMMA_LEN ("lt") },
17534 { STRING_COMMA_LEN ("le") },
17535 { STRING_COMMA_LEN ("unord") },
17536 { STRING_COMMA_LEN ("neq") },
17537 { STRING_COMMA_LEN ("nlt") },
17538 { STRING_COMMA_LEN ("nle") },
17539 { STRING_COMMA_LEN ("ord") },
17540 { STRING_COMMA_LEN ("eq_uq") },
17541 { STRING_COMMA_LEN ("nge") },
17542 { STRING_COMMA_LEN ("ngt") },
17543 { STRING_COMMA_LEN ("false") },
17544 { STRING_COMMA_LEN ("neq_oq") },
17545 { STRING_COMMA_LEN ("ge") },
17546 { STRING_COMMA_LEN ("gt") },
17547 { STRING_COMMA_LEN ("true") },
17548 { STRING_COMMA_LEN ("eq_os") },
17549 { STRING_COMMA_LEN ("lt_oq") },
17550 { STRING_COMMA_LEN ("le_oq") },
17551 { STRING_COMMA_LEN ("unord_s") },
17552 { STRING_COMMA_LEN ("neq_us") },
17553 { STRING_COMMA_LEN ("nlt_uq") },
17554 { STRING_COMMA_LEN ("nle_uq") },
17555 { STRING_COMMA_LEN ("ord_s") },
17556 { STRING_COMMA_LEN ("eq_us") },
17557 { STRING_COMMA_LEN ("nge_uq") },
17558 { STRING_COMMA_LEN ("ngt_uq") },
17559 { STRING_COMMA_LEN ("false_os") },
17560 { STRING_COMMA_LEN ("neq_os") },
17561 { STRING_COMMA_LEN ("ge_oq") },
17562 { STRING_COMMA_LEN ("gt_oq") },
17563 { STRING_COMMA_LEN ("true_us") },
17567 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17569 unsigned int cmp_type
;
17571 FETCH_DATA (the_info
, codep
+ 1);
17572 cmp_type
= *codep
++ & 0xff;
17573 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
17576 char *p
= mnemonicendp
- 2;
17580 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
17581 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
17585 /* We have a reserved extension byte. Output it directly. */
17586 scratchbuf
[0] = '$';
17587 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17588 oappend_maybe_intel (scratchbuf
);
17589 scratchbuf
[0] = '\0';
17594 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17595 int sizeflag ATTRIBUTE_UNUSED
)
17597 unsigned int cmp_type
;
17602 FETCH_DATA (the_info
, codep
+ 1);
17603 cmp_type
= *codep
++ & 0xff;
17604 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17605 If it's the case, print suffix, otherwise - print the immediate. */
17606 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
17611 char *p
= mnemonicendp
- 2;
17613 /* vpcmp* can have both one- and two-lettered suffix. */
17627 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
17628 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
17632 /* We have a reserved extension byte. Output it directly. */
17633 scratchbuf
[0] = '$';
17634 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17635 oappend_maybe_intel (scratchbuf
);
17636 scratchbuf
[0] = '\0';
17640 static const struct op pclmul_op
[] =
17642 { STRING_COMMA_LEN ("lql") },
17643 { STRING_COMMA_LEN ("hql") },
17644 { STRING_COMMA_LEN ("lqh") },
17645 { STRING_COMMA_LEN ("hqh") }
17649 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17650 int sizeflag ATTRIBUTE_UNUSED
)
17652 unsigned int pclmul_type
;
17654 FETCH_DATA (the_info
, codep
+ 1);
17655 pclmul_type
= *codep
++ & 0xff;
17656 switch (pclmul_type
)
17667 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
17670 char *p
= mnemonicendp
- 3;
17675 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
17676 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
17680 /* We have a reserved extension byte. Output it directly. */
17681 scratchbuf
[0] = '$';
17682 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
17683 oappend_maybe_intel (scratchbuf
);
17684 scratchbuf
[0] = '\0';
17689 MOVBE_Fixup (int bytemode
, int sizeflag
)
17691 /* Add proper suffix to "movbe". */
17692 char *p
= mnemonicendp
;
17701 if (sizeflag
& SUFFIX_ALWAYS
)
17707 if (sizeflag
& DFLAG
)
17711 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17716 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17723 OP_M (bytemode
, sizeflag
);
17727 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17730 const char **names
;
17732 /* Skip mod/rm byte. */
17746 oappend (names
[reg
]);
17750 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17752 const char **names
;
17759 oappend (names
[vex
.register_specifier
]);
17763 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17766 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
17770 if ((rex
& REX_R
) != 0 || !vex
.r
)
17776 oappend (names_mask
[modrm
.reg
]);
17780 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17783 || (bytemode
!= evex_rounding_mode
17784 && bytemode
!= evex_sae_mode
))
17786 if (modrm
.mod
== 3 && vex
.b
)
17789 case evex_rounding_mode
:
17790 oappend (names_rounding
[vex
.ll
]);
17792 case evex_sae_mode
: