1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2016 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void OP_LWPCB_E (int, int);
121 static void OP_LWP_E (int, int);
122 static void OP_Vex_2src_1 (int, int);
123 static void OP_Vex_2src_2 (int, int);
125 static void MOVBE_Fixup (int, int);
127 static void OP_Mask (int, int);
130 /* Points to first byte not fetched. */
131 bfd_byte
*max_fetched
;
132 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
135 OPCODES_SIGJMP_BUF bailout
;
145 enum address_mode address_mode
;
147 /* Flags for the prefixes for the current instruction. See below. */
150 /* REX prefix the current instruction. See below. */
152 /* Bits of REX we've already used. */
154 /* REX bits in original REX prefix ignored. */
155 static int rex_ignored
;
156 /* Mark parts used in the REX prefix. When we are testing for
157 empty prefix (for 8bit register REX extension), just mask it
158 out. Otherwise test for REX bit is excuse for existence of REX
159 only in case value is nonzero. */
160 #define USED_REX(value) \
165 rex_used |= (value) | REX_OPCODE; \
168 rex_used |= REX_OPCODE; \
171 /* Flags for prefixes which we somehow handled when printing the
172 current instruction. */
173 static int used_prefixes
;
175 /* Flags stored in PREFIXES. */
176 #define PREFIX_REPZ 1
177 #define PREFIX_REPNZ 2
178 #define PREFIX_LOCK 4
180 #define PREFIX_SS 0x10
181 #define PREFIX_DS 0x20
182 #define PREFIX_ES 0x40
183 #define PREFIX_FS 0x80
184 #define PREFIX_GS 0x100
185 #define PREFIX_DATA 0x200
186 #define PREFIX_ADDR 0x400
187 #define PREFIX_FWAIT 0x800
189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
190 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
192 #define FETCH_DATA(info, addr) \
193 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
194 ? 1 : fetch_data ((info), (addr)))
197 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
200 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
201 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
203 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
204 status
= (*info
->read_memory_func
) (start
,
206 addr
- priv
->max_fetched
,
212 /* If we did manage to read at least one byte, then
213 print_insn_i386 will do something sensible. Otherwise, print
214 an error. We do that here because this is where we know
216 if (priv
->max_fetched
== priv
->the_buffer
)
217 (*info
->memory_error_func
) (status
, start
, info
);
218 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
221 priv
->max_fetched
= addr
;
225 /* Possible values for prefix requirement. */
226 #define PREFIX_IGNORED_SHIFT 16
227 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
228 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
233 /* Opcode prefixes. */
234 #define PREFIX_OPCODE (PREFIX_REPZ \
238 /* Prefixes ignored. */
239 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
240 | PREFIX_IGNORED_REPNZ \
241 | PREFIX_IGNORED_DATA)
243 #define XX { NULL, 0 }
244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
246 #define Eb { OP_E, b_mode }
247 #define Ebnd { OP_E, bnd_mode }
248 #define EbS { OP_E, b_swap_mode }
249 #define Ev { OP_E, v_mode }
250 #define Ev_bnd { OP_E, v_bnd_mode }
251 #define EvS { OP_E, v_swap_mode }
252 #define Ed { OP_E, d_mode }
253 #define Edq { OP_E, dq_mode }
254 #define Edqw { OP_E, dqw_mode }
255 #define EdqwS { OP_E, dqw_swap_mode }
256 #define Edqb { OP_E, dqb_mode }
257 #define Edb { OP_E, db_mode }
258 #define Edw { OP_E, dw_mode }
259 #define Edqd { OP_E, dqd_mode }
260 #define Eq { OP_E, q_mode }
261 #define indirEv { OP_indirE, stack_v_mode }
262 #define indirEp { OP_indirE, f_mode }
263 #define stackEv { OP_E, stack_v_mode }
264 #define Em { OP_E, m_mode }
265 #define Ew { OP_E, w_mode }
266 #define M { OP_M, 0 } /* lea, lgdt, etc. */
267 #define Ma { OP_M, a_mode }
268 #define Mb { OP_M, b_mode }
269 #define Md { OP_M, d_mode }
270 #define Mo { OP_M, o_mode }
271 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
272 #define Mq { OP_M, q_mode }
273 #define Mx { OP_M, x_mode }
274 #define Mxmm { OP_M, xmm_mode }
275 #define Gb { OP_G, b_mode }
276 #define Gbnd { OP_G, bnd_mode }
277 #define Gv { OP_G, v_mode }
278 #define Gd { OP_G, d_mode }
279 #define Gdq { OP_G, dq_mode }
280 #define Gm { OP_G, m_mode }
281 #define Gw { OP_G, w_mode }
282 #define Rd { OP_R, d_mode }
283 #define Rdq { OP_R, dq_mode }
284 #define Rm { OP_R, m_mode }
285 #define Ib { OP_I, b_mode }
286 #define sIb { OP_sI, b_mode } /* sign extened byte */
287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
288 #define Iv { OP_I, v_mode }
289 #define sIv { OP_sI, v_mode }
290 #define Iq { OP_I, q_mode }
291 #define Iv64 { OP_I64, v_mode }
292 #define Iw { OP_I, w_mode }
293 #define I1 { OP_I, const_1_mode }
294 #define Jb { OP_J, b_mode }
295 #define Jv { OP_J, v_mode }
296 #define Cm { OP_C, m_mode }
297 #define Dm { OP_D, m_mode }
298 #define Td { OP_T, d_mode }
299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
301 #define RMeAX { OP_REG, eAX_reg }
302 #define RMeBX { OP_REG, eBX_reg }
303 #define RMeCX { OP_REG, eCX_reg }
304 #define RMeDX { OP_REG, eDX_reg }
305 #define RMeSP { OP_REG, eSP_reg }
306 #define RMeBP { OP_REG, eBP_reg }
307 #define RMeSI { OP_REG, eSI_reg }
308 #define RMeDI { OP_REG, eDI_reg }
309 #define RMrAX { OP_REG, rAX_reg }
310 #define RMrBX { OP_REG, rBX_reg }
311 #define RMrCX { OP_REG, rCX_reg }
312 #define RMrDX { OP_REG, rDX_reg }
313 #define RMrSP { OP_REG, rSP_reg }
314 #define RMrBP { OP_REG, rBP_reg }
315 #define RMrSI { OP_REG, rSI_reg }
316 #define RMrDI { OP_REG, rDI_reg }
317 #define RMAL { OP_REG, al_reg }
318 #define RMCL { OP_REG, cl_reg }
319 #define RMDL { OP_REG, dl_reg }
320 #define RMBL { OP_REG, bl_reg }
321 #define RMAH { OP_REG, ah_reg }
322 #define RMCH { OP_REG, ch_reg }
323 #define RMDH { OP_REG, dh_reg }
324 #define RMBH { OP_REG, bh_reg }
325 #define RMAX { OP_REG, ax_reg }
326 #define RMDX { OP_REG, dx_reg }
328 #define eAX { OP_IMREG, eAX_reg }
329 #define eBX { OP_IMREG, eBX_reg }
330 #define eCX { OP_IMREG, eCX_reg }
331 #define eDX { OP_IMREG, eDX_reg }
332 #define eSP { OP_IMREG, eSP_reg }
333 #define eBP { OP_IMREG, eBP_reg }
334 #define eSI { OP_IMREG, eSI_reg }
335 #define eDI { OP_IMREG, eDI_reg }
336 #define AL { OP_IMREG, al_reg }
337 #define CL { OP_IMREG, cl_reg }
338 #define DL { OP_IMREG, dl_reg }
339 #define BL { OP_IMREG, bl_reg }
340 #define AH { OP_IMREG, ah_reg }
341 #define CH { OP_IMREG, ch_reg }
342 #define DH { OP_IMREG, dh_reg }
343 #define BH { OP_IMREG, bh_reg }
344 #define AX { OP_IMREG, ax_reg }
345 #define DX { OP_IMREG, dx_reg }
346 #define zAX { OP_IMREG, z_mode_ax_reg }
347 #define indirDX { OP_IMREG, indir_dx_reg }
349 #define Sw { OP_SEG, w_mode }
350 #define Sv { OP_SEG, v_mode }
351 #define Ap { OP_DIR, 0 }
352 #define Ob { OP_OFF64, b_mode }
353 #define Ov { OP_OFF64, v_mode }
354 #define Xb { OP_DSreg, eSI_reg }
355 #define Xv { OP_DSreg, eSI_reg }
356 #define Xz { OP_DSreg, eSI_reg }
357 #define Yb { OP_ESreg, eDI_reg }
358 #define Yv { OP_ESreg, eDI_reg }
359 #define DSBX { OP_DSreg, eBX_reg }
361 #define es { OP_REG, es_reg }
362 #define ss { OP_REG, ss_reg }
363 #define cs { OP_REG, cs_reg }
364 #define ds { OP_REG, ds_reg }
365 #define fs { OP_REG, fs_reg }
366 #define gs { OP_REG, gs_reg }
368 #define MX { OP_MMX, 0 }
369 #define XM { OP_XMM, 0 }
370 #define XMScalar { OP_XMM, scalar_mode }
371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
372 #define XMM { OP_XMM, xmm_mode }
373 #define XMxmmq { OP_XMM, xmmq_mode }
374 #define EM { OP_EM, v_mode }
375 #define EMS { OP_EM, v_swap_mode }
376 #define EMd { OP_EM, d_mode }
377 #define EMx { OP_EM, x_mode }
378 #define EXw { OP_EX, w_mode }
379 #define EXd { OP_EX, d_mode }
380 #define EXdScalar { OP_EX, d_scalar_mode }
381 #define EXdS { OP_EX, d_swap_mode }
382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
383 #define EXq { OP_EX, q_mode }
384 #define EXqScalar { OP_EX, q_scalar_mode }
385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
386 #define EXqS { OP_EX, q_swap_mode }
387 #define EXx { OP_EX, x_mode }
388 #define EXxS { OP_EX, x_swap_mode }
389 #define EXxmm { OP_EX, xmm_mode }
390 #define EXymm { OP_EX, ymm_mode }
391 #define EXxmmq { OP_EX, xmmq_mode }
392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
395 #define EXxmm_md { OP_EX, xmm_md_mode }
396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
398 #define EXxmmdw { OP_EX, xmmdw_mode }
399 #define EXxmmqd { OP_EX, xmmqd_mode }
400 #define EXymmq { OP_EX, ymmq_mode }
401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
405 #define MS { OP_MS, v_mode }
406 #define XS { OP_XS, v_mode }
407 #define EMCq { OP_EMC, q_mode }
408 #define MXC { OP_MXC, 0 }
409 #define OPSUF { OP_3DNowSuffix, 0 }
410 #define CMP { CMP_Fixup, 0 }
411 #define XMM0 { XMM_Fixup, 0 }
412 #define FXSAVE { FXSAVE_Fixup, 0 }
413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
416 #define Vex { OP_VEX, vex_mode }
417 #define VexScalar { OP_VEX, vex_scalar_mode }
418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
419 #define Vex128 { OP_VEX, vex128_mode }
420 #define Vex256 { OP_VEX, vex256_mode }
421 #define VexGdq { OP_VEX, dq_mode }
422 #define VexI4 { VEXI4_Fixup, 0}
423 #define EXdVex { OP_EX_Vex, d_mode }
424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
426 #define EXqVex { OP_EX_Vex, q_mode }
427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
429 #define EXVexW { OP_EX_VexW, x_mode }
430 #define EXdVexW { OP_EX_VexW, d_mode }
431 #define EXqVexW { OP_EX_VexW, q_mode }
432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
433 #define XMVex { OP_XMM_Vex, 0 }
434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
435 #define XMVexW { OP_XMM_VexW, 0 }
436 #define XMVexI4 { OP_REG_VexI4, x_mode }
437 #define PCLMUL { PCLMUL_Fixup, 0 }
438 #define VZERO { VZERO_Fixup, 0 }
439 #define VCMP { VCMP_Fixup, 0 }
440 #define VPCMP { VPCMP_Fixup, 0 }
442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
445 #define XMask { OP_Mask, mask_mode }
446 #define MaskG { OP_G, mask_mode }
447 #define MaskE { OP_E, mask_mode }
448 #define MaskBDE { OP_E, mask_bd_mode }
449 #define MaskR { OP_R, mask_mode }
450 #define MaskVex { OP_VEX, mask_mode }
452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
457 /* Used handle "rep" prefix for string instructions. */
458 #define Xbr { REP_Fixup, eSI_reg }
459 #define Xvr { REP_Fixup, eSI_reg }
460 #define Ybr { REP_Fixup, eDI_reg }
461 #define Yvr { REP_Fixup, eDI_reg }
462 #define Yzr { REP_Fixup, eDI_reg }
463 #define indirDXr { REP_Fixup, indir_dx_reg }
464 #define ALr { REP_Fixup, al_reg }
465 #define eAXr { REP_Fixup, eAX_reg }
467 /* Used handle HLE prefix for lockable instructions. */
468 #define Ebh1 { HLE_Fixup1, b_mode }
469 #define Evh1 { HLE_Fixup1, v_mode }
470 #define Ebh2 { HLE_Fixup2, b_mode }
471 #define Evh2 { HLE_Fixup2, v_mode }
472 #define Ebh3 { HLE_Fixup3, b_mode }
473 #define Evh3 { HLE_Fixup3, v_mode }
475 #define BND { BND_Fixup, 0 }
477 #define cond_jump_flag { NULL, cond_jump_mode }
478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
480 /* bits in sizeflag */
481 #define SUFFIX_ALWAYS 4
489 /* byte operand with operand swapped */
491 /* byte operand, sign extend like 'T' suffix */
493 /* operand size depends on prefixes */
495 /* operand size depends on prefixes with operand swapped */
499 /* double word operand */
501 /* double word operand with operand swapped */
503 /* quad word operand */
505 /* quad word operand with operand swapped */
507 /* ten-byte operand */
509 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
510 broadcast enabled. */
512 /* Similar to x_mode, but with different EVEX mem shifts. */
514 /* Similar to x_mode, but with disabled broadcast. */
516 /* Similar to x_mode, but with operands swapped and disabled broadcast
519 /* 16-byte XMM operand */
521 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
522 memory operand (depending on vector length). Broadcast isn't
525 /* Same as xmmq_mode, but broadcast is allowed. */
526 evex_half_bcst_xmmq_mode
,
527 /* XMM register or byte memory operand */
529 /* XMM register or word memory operand */
531 /* XMM register or double word memory operand */
533 /* XMM register or quad word memory operand */
535 /* XMM register or double/quad word memory operand, depending on
538 /* 16-byte XMM, word, double word or quad word operand. */
540 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
542 /* 32-byte YMM operand */
544 /* quad word, ymmword or zmmword memory operand. */
546 /* 32-byte YMM or 16-byte word operand */
548 /* d_mode in 32bit, q_mode in 64bit mode. */
550 /* pair of v_mode operands */
555 /* operand size depends on REX prefixes. */
557 /* registers like dq_mode, memory like w_mode. */
561 /* 4- or 6-byte pointer operand */
564 /* v_mode for stack-related opcodes. */
566 /* non-quad operand size depends on prefixes */
568 /* 16-byte operand */
570 /* registers like dq_mode, memory like b_mode. */
572 /* registers like d_mode, memory like b_mode. */
574 /* registers like d_mode, memory like w_mode. */
576 /* registers like dq_mode, memory like d_mode. */
578 /* normal vex mode */
580 /* 128bit vex mode */
582 /* 256bit vex mode */
584 /* operand size depends on the VEX.W bit. */
587 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
588 vex_vsib_d_w_dq_mode
,
589 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
591 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
592 vex_vsib_q_w_dq_mode
,
593 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
596 /* scalar, ignore vector length. */
598 /* like d_mode, ignore vector length. */
600 /* like d_swap_mode, ignore vector length. */
602 /* like q_mode, ignore vector length. */
604 /* like q_swap_mode, ignore vector length. */
606 /* like vex_mode, ignore vector length. */
608 /* like vex_w_dq_mode, ignore vector length. */
609 vex_scalar_w_dq_mode
,
611 /* Static rounding. */
613 /* Supress all exceptions. */
616 /* Mask register operand. */
618 /* Mask register operand. */
685 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
687 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
688 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
689 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
690 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
691 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
692 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
693 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
694 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
695 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
696 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
697 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
698 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
699 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
700 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
701 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
819 MOD_VEX_0F12_PREFIX_0
,
821 MOD_VEX_0F16_PREFIX_0
,
824 MOD_VEX_W_0_0F41_P_0_LEN_1
,
825 MOD_VEX_W_1_0F41_P_0_LEN_1
,
826 MOD_VEX_W_0_0F41_P_2_LEN_1
,
827 MOD_VEX_W_1_0F41_P_2_LEN_1
,
828 MOD_VEX_W_0_0F42_P_0_LEN_1
,
829 MOD_VEX_W_1_0F42_P_0_LEN_1
,
830 MOD_VEX_W_0_0F42_P_2_LEN_1
,
831 MOD_VEX_W_1_0F42_P_2_LEN_1
,
832 MOD_VEX_W_0_0F44_P_0_LEN_1
,
833 MOD_VEX_W_1_0F44_P_0_LEN_1
,
834 MOD_VEX_W_0_0F44_P_2_LEN_1
,
835 MOD_VEX_W_1_0F44_P_2_LEN_1
,
836 MOD_VEX_W_0_0F45_P_0_LEN_1
,
837 MOD_VEX_W_1_0F45_P_0_LEN_1
,
838 MOD_VEX_W_0_0F45_P_2_LEN_1
,
839 MOD_VEX_W_1_0F45_P_2_LEN_1
,
840 MOD_VEX_W_0_0F46_P_0_LEN_1
,
841 MOD_VEX_W_1_0F46_P_0_LEN_1
,
842 MOD_VEX_W_0_0F46_P_2_LEN_1
,
843 MOD_VEX_W_1_0F46_P_2_LEN_1
,
844 MOD_VEX_W_0_0F47_P_0_LEN_1
,
845 MOD_VEX_W_1_0F47_P_0_LEN_1
,
846 MOD_VEX_W_0_0F47_P_2_LEN_1
,
847 MOD_VEX_W_1_0F47_P_2_LEN_1
,
848 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
849 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
850 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
851 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
852 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
853 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
854 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
866 MOD_VEX_W_0_0F91_P_0_LEN_0
,
867 MOD_VEX_W_1_0F91_P_0_LEN_0
,
868 MOD_VEX_W_0_0F91_P_2_LEN_0
,
869 MOD_VEX_W_1_0F91_P_2_LEN_0
,
870 MOD_VEX_W_0_0F92_P_0_LEN_0
,
871 MOD_VEX_W_0_0F92_P_2_LEN_0
,
872 MOD_VEX_W_0_0F92_P_3_LEN_0
,
873 MOD_VEX_W_1_0F92_P_3_LEN_0
,
874 MOD_VEX_W_0_0F93_P_0_LEN_0
,
875 MOD_VEX_W_0_0F93_P_2_LEN_0
,
876 MOD_VEX_W_0_0F93_P_3_LEN_0
,
877 MOD_VEX_W_1_0F93_P_3_LEN_0
,
878 MOD_VEX_W_0_0F98_P_0_LEN_0
,
879 MOD_VEX_W_1_0F98_P_0_LEN_0
,
880 MOD_VEX_W_0_0F98_P_2_LEN_0
,
881 MOD_VEX_W_1_0F98_P_2_LEN_0
,
882 MOD_VEX_W_0_0F99_P_0_LEN_0
,
883 MOD_VEX_W_1_0F99_P_0_LEN_0
,
884 MOD_VEX_W_0_0F99_P_2_LEN_0
,
885 MOD_VEX_W_1_0F99_P_2_LEN_0
,
888 MOD_VEX_0FD7_PREFIX_2
,
889 MOD_VEX_0FE7_PREFIX_2
,
890 MOD_VEX_0FF0_PREFIX_3
,
891 MOD_VEX_0F381A_PREFIX_2
,
892 MOD_VEX_0F382A_PREFIX_2
,
893 MOD_VEX_0F382C_PREFIX_2
,
894 MOD_VEX_0F382D_PREFIX_2
,
895 MOD_VEX_0F382E_PREFIX_2
,
896 MOD_VEX_0F382F_PREFIX_2
,
897 MOD_VEX_0F385A_PREFIX_2
,
898 MOD_VEX_0F388C_PREFIX_2
,
899 MOD_VEX_0F388E_PREFIX_2
,
900 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
901 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
902 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
903 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
904 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
905 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
906 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
907 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
909 MOD_EVEX_0F10_PREFIX_1
,
910 MOD_EVEX_0F10_PREFIX_3
,
911 MOD_EVEX_0F11_PREFIX_1
,
912 MOD_EVEX_0F11_PREFIX_3
,
913 MOD_EVEX_0F12_PREFIX_0
,
914 MOD_EVEX_0F16_PREFIX_0
,
915 MOD_EVEX_0F38C6_REG_1
,
916 MOD_EVEX_0F38C6_REG_2
,
917 MOD_EVEX_0F38C6_REG_5
,
918 MOD_EVEX_0F38C6_REG_6
,
919 MOD_EVEX_0F38C7_REG_1
,
920 MOD_EVEX_0F38C7_REG_2
,
921 MOD_EVEX_0F38C7_REG_5
,
922 MOD_EVEX_0F38C7_REG_6
987 PREFIX_RM_0_0FAE_REG_7
,
993 PREFIX_MOD_0_0FC7_REG_6
,
994 PREFIX_MOD_3_0FC7_REG_6
,
995 PREFIX_MOD_3_0FC7_REG_7
,
1119 PREFIX_VEX_0F71_REG_2
,
1120 PREFIX_VEX_0F71_REG_4
,
1121 PREFIX_VEX_0F71_REG_6
,
1122 PREFIX_VEX_0F72_REG_2
,
1123 PREFIX_VEX_0F72_REG_4
,
1124 PREFIX_VEX_0F72_REG_6
,
1125 PREFIX_VEX_0F73_REG_2
,
1126 PREFIX_VEX_0F73_REG_3
,
1127 PREFIX_VEX_0F73_REG_6
,
1128 PREFIX_VEX_0F73_REG_7
,
1300 PREFIX_VEX_0F38F3_REG_1
,
1301 PREFIX_VEX_0F38F3_REG_2
,
1302 PREFIX_VEX_0F38F3_REG_3
,
1419 PREFIX_EVEX_0F71_REG_2
,
1420 PREFIX_EVEX_0F71_REG_4
,
1421 PREFIX_EVEX_0F71_REG_6
,
1422 PREFIX_EVEX_0F72_REG_0
,
1423 PREFIX_EVEX_0F72_REG_1
,
1424 PREFIX_EVEX_0F72_REG_2
,
1425 PREFIX_EVEX_0F72_REG_4
,
1426 PREFIX_EVEX_0F72_REG_6
,
1427 PREFIX_EVEX_0F73_REG_2
,
1428 PREFIX_EVEX_0F73_REG_3
,
1429 PREFIX_EVEX_0F73_REG_6
,
1430 PREFIX_EVEX_0F73_REG_7
,
1613 PREFIX_EVEX_0F38C6_REG_1
,
1614 PREFIX_EVEX_0F38C6_REG_2
,
1615 PREFIX_EVEX_0F38C6_REG_5
,
1616 PREFIX_EVEX_0F38C6_REG_6
,
1617 PREFIX_EVEX_0F38C7_REG_1
,
1618 PREFIX_EVEX_0F38C7_REG_2
,
1619 PREFIX_EVEX_0F38C7_REG_5
,
1620 PREFIX_EVEX_0F38C7_REG_6
,
1709 THREE_BYTE_0F38
= 0,
1737 VEX_LEN_0F10_P_1
= 0,
1741 VEX_LEN_0F12_P_0_M_0
,
1742 VEX_LEN_0F12_P_0_M_1
,
1745 VEX_LEN_0F16_P_0_M_0
,
1746 VEX_LEN_0F16_P_0_M_1
,
1810 VEX_LEN_0FAE_R_2_M_0
,
1811 VEX_LEN_0FAE_R_3_M_0
,
1820 VEX_LEN_0F381A_P_2_M_0
,
1823 VEX_LEN_0F385A_P_2_M_0
,
1830 VEX_LEN_0F38F3_R_1_P_0
,
1831 VEX_LEN_0F38F3_R_2_P_0
,
1832 VEX_LEN_0F38F3_R_3_P_0
,
1878 VEX_LEN_0FXOP_08_CC
,
1879 VEX_LEN_0FXOP_08_CD
,
1880 VEX_LEN_0FXOP_08_CE
,
1881 VEX_LEN_0FXOP_08_CF
,
1882 VEX_LEN_0FXOP_08_EC
,
1883 VEX_LEN_0FXOP_08_ED
,
1884 VEX_LEN_0FXOP_08_EE
,
1885 VEX_LEN_0FXOP_08_EF
,
1886 VEX_LEN_0FXOP_09_80
,
1920 VEX_W_0F41_P_0_LEN_1
,
1921 VEX_W_0F41_P_2_LEN_1
,
1922 VEX_W_0F42_P_0_LEN_1
,
1923 VEX_W_0F42_P_2_LEN_1
,
1924 VEX_W_0F44_P_0_LEN_0
,
1925 VEX_W_0F44_P_2_LEN_0
,
1926 VEX_W_0F45_P_0_LEN_1
,
1927 VEX_W_0F45_P_2_LEN_1
,
1928 VEX_W_0F46_P_0_LEN_1
,
1929 VEX_W_0F46_P_2_LEN_1
,
1930 VEX_W_0F47_P_0_LEN_1
,
1931 VEX_W_0F47_P_2_LEN_1
,
1932 VEX_W_0F4A_P_0_LEN_1
,
1933 VEX_W_0F4A_P_2_LEN_1
,
1934 VEX_W_0F4B_P_0_LEN_1
,
1935 VEX_W_0F4B_P_2_LEN_1
,
2015 VEX_W_0F90_P_0_LEN_0
,
2016 VEX_W_0F90_P_2_LEN_0
,
2017 VEX_W_0F91_P_0_LEN_0
,
2018 VEX_W_0F91_P_2_LEN_0
,
2019 VEX_W_0F92_P_0_LEN_0
,
2020 VEX_W_0F92_P_2_LEN_0
,
2021 VEX_W_0F92_P_3_LEN_0
,
2022 VEX_W_0F93_P_0_LEN_0
,
2023 VEX_W_0F93_P_2_LEN_0
,
2024 VEX_W_0F93_P_3_LEN_0
,
2025 VEX_W_0F98_P_0_LEN_0
,
2026 VEX_W_0F98_P_2_LEN_0
,
2027 VEX_W_0F99_P_0_LEN_0
,
2028 VEX_W_0F99_P_2_LEN_0
,
2107 VEX_W_0F381A_P_2_M_0
,
2119 VEX_W_0F382A_P_2_M_0
,
2121 VEX_W_0F382C_P_2_M_0
,
2122 VEX_W_0F382D_P_2_M_0
,
2123 VEX_W_0F382E_P_2_M_0
,
2124 VEX_W_0F382F_P_2_M_0
,
2146 VEX_W_0F385A_P_2_M_0
,
2174 VEX_W_0F3A30_P_2_LEN_0
,
2175 VEX_W_0F3A31_P_2_LEN_0
,
2176 VEX_W_0F3A32_P_2_LEN_0
,
2177 VEX_W_0F3A33_P_2_LEN_0
,
2197 EVEX_W_0F10_P_1_M_0
,
2198 EVEX_W_0F10_P_1_M_1
,
2200 EVEX_W_0F10_P_3_M_0
,
2201 EVEX_W_0F10_P_3_M_1
,
2203 EVEX_W_0F11_P_1_M_0
,
2204 EVEX_W_0F11_P_1_M_1
,
2206 EVEX_W_0F11_P_3_M_0
,
2207 EVEX_W_0F11_P_3_M_1
,
2208 EVEX_W_0F12_P_0_M_0
,
2209 EVEX_W_0F12_P_0_M_1
,
2219 EVEX_W_0F16_P_0_M_0
,
2220 EVEX_W_0F16_P_0_M_1
,
2291 EVEX_W_0F72_R_2_P_2
,
2292 EVEX_W_0F72_R_6_P_2
,
2293 EVEX_W_0F73_R_2_P_2
,
2294 EVEX_W_0F73_R_6_P_2
,
2394 EVEX_W_0F38C7_R_1_P_2
,
2395 EVEX_W_0F38C7_R_2_P_2
,
2396 EVEX_W_0F38C7_R_5_P_2
,
2397 EVEX_W_0F38C7_R_6_P_2
,
2432 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2441 unsigned int prefix_requirement
;
2444 /* Upper case letters in the instruction names here are macros.
2445 'A' => print 'b' if no register operands or suffix_always is true
2446 'B' => print 'b' if suffix_always is true
2447 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2449 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2450 suffix_always is true
2451 'E' => print 'e' if 32-bit form of jcxz
2452 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2453 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2454 'H' => print ",pt" or ",pn" branch hint
2455 'I' => honor following macro letter even in Intel mode (implemented only
2456 for some of the macro letters)
2458 'K' => print 'd' or 'q' if rex prefix is present.
2459 'L' => print 'l' if suffix_always is true
2460 'M' => print 'r' if intel_mnemonic is false.
2461 'N' => print 'n' if instruction has no wait "prefix"
2462 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2463 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2464 or suffix_always is true. print 'q' if rex prefix is present.
2465 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2467 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2468 'S' => print 'w', 'l' or 'q' if suffix_always is true
2469 'T' => print 'q' in 64bit mode if instruction has no operand size
2470 prefix and behave as 'P' otherwise
2471 'U' => print 'q' in 64bit mode if instruction has no operand size
2472 prefix and behave as 'Q' otherwise
2473 'V' => print 'q' in 64bit mode if instruction has no operand size
2474 prefix and behave as 'S' otherwise
2475 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2476 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2477 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2478 suffix_always is true.
2479 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2480 '!' => change condition from true to false or from false to true.
2481 '%' => add 1 upper case letter to the macro.
2482 '^' => print 'w' or 'l' depending on operand size prefix or
2483 suffix_always is true (lcall/ljmp).
2484 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2485 on operand size prefix.
2487 2 upper case letter macros:
2488 "XY" => print 'x' or 'y' if suffix_always is true or no register
2489 operands and no broadcast.
2490 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2491 register operands and no broadcast.
2492 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2493 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2494 or suffix_always is true
2495 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2496 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2497 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2498 "LW" => print 'd', 'q' depending on the VEX.W bit
2499 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2500 an operand size prefix, or suffix_always is true. print
2501 'q' if rex prefix is present.
2503 Many of the above letters print nothing in Intel mode. See "putop"
2506 Braces '{' and '}', and vertical bars '|', indicate alternative
2507 mnemonic strings for AT&T and Intel. */
2509 static const struct dis386 dis386
[] = {
2511 { "addB", { Ebh1
, Gb
}, 0 },
2512 { "addS", { Evh1
, Gv
}, 0 },
2513 { "addB", { Gb
, EbS
}, 0 },
2514 { "addS", { Gv
, EvS
}, 0 },
2515 { "addB", { AL
, Ib
}, 0 },
2516 { "addS", { eAX
, Iv
}, 0 },
2517 { X86_64_TABLE (X86_64_06
) },
2518 { X86_64_TABLE (X86_64_07
) },
2520 { "orB", { Ebh1
, Gb
}, 0 },
2521 { "orS", { Evh1
, Gv
}, 0 },
2522 { "orB", { Gb
, EbS
}, 0 },
2523 { "orS", { Gv
, EvS
}, 0 },
2524 { "orB", { AL
, Ib
}, 0 },
2525 { "orS", { eAX
, Iv
}, 0 },
2526 { X86_64_TABLE (X86_64_0D
) },
2527 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2529 { "adcB", { Ebh1
, Gb
}, 0 },
2530 { "adcS", { Evh1
, Gv
}, 0 },
2531 { "adcB", { Gb
, EbS
}, 0 },
2532 { "adcS", { Gv
, EvS
}, 0 },
2533 { "adcB", { AL
, Ib
}, 0 },
2534 { "adcS", { eAX
, Iv
}, 0 },
2535 { X86_64_TABLE (X86_64_16
) },
2536 { X86_64_TABLE (X86_64_17
) },
2538 { "sbbB", { Ebh1
, Gb
}, 0 },
2539 { "sbbS", { Evh1
, Gv
}, 0 },
2540 { "sbbB", { Gb
, EbS
}, 0 },
2541 { "sbbS", { Gv
, EvS
}, 0 },
2542 { "sbbB", { AL
, Ib
}, 0 },
2543 { "sbbS", { eAX
, Iv
}, 0 },
2544 { X86_64_TABLE (X86_64_1E
) },
2545 { X86_64_TABLE (X86_64_1F
) },
2547 { "andB", { Ebh1
, Gb
}, 0 },
2548 { "andS", { Evh1
, Gv
}, 0 },
2549 { "andB", { Gb
, EbS
}, 0 },
2550 { "andS", { Gv
, EvS
}, 0 },
2551 { "andB", { AL
, Ib
}, 0 },
2552 { "andS", { eAX
, Iv
}, 0 },
2553 { Bad_Opcode
}, /* SEG ES prefix */
2554 { X86_64_TABLE (X86_64_27
) },
2556 { "subB", { Ebh1
, Gb
}, 0 },
2557 { "subS", { Evh1
, Gv
}, 0 },
2558 { "subB", { Gb
, EbS
}, 0 },
2559 { "subS", { Gv
, EvS
}, 0 },
2560 { "subB", { AL
, Ib
}, 0 },
2561 { "subS", { eAX
, Iv
}, 0 },
2562 { Bad_Opcode
}, /* SEG CS prefix */
2563 { X86_64_TABLE (X86_64_2F
) },
2565 { "xorB", { Ebh1
, Gb
}, 0 },
2566 { "xorS", { Evh1
, Gv
}, 0 },
2567 { "xorB", { Gb
, EbS
}, 0 },
2568 { "xorS", { Gv
, EvS
}, 0 },
2569 { "xorB", { AL
, Ib
}, 0 },
2570 { "xorS", { eAX
, Iv
}, 0 },
2571 { Bad_Opcode
}, /* SEG SS prefix */
2572 { X86_64_TABLE (X86_64_37
) },
2574 { "cmpB", { Eb
, Gb
}, 0 },
2575 { "cmpS", { Ev
, Gv
}, 0 },
2576 { "cmpB", { Gb
, EbS
}, 0 },
2577 { "cmpS", { Gv
, EvS
}, 0 },
2578 { "cmpB", { AL
, Ib
}, 0 },
2579 { "cmpS", { eAX
, Iv
}, 0 },
2580 { Bad_Opcode
}, /* SEG DS prefix */
2581 { X86_64_TABLE (X86_64_3F
) },
2583 { "inc{S|}", { RMeAX
}, 0 },
2584 { "inc{S|}", { RMeCX
}, 0 },
2585 { "inc{S|}", { RMeDX
}, 0 },
2586 { "inc{S|}", { RMeBX
}, 0 },
2587 { "inc{S|}", { RMeSP
}, 0 },
2588 { "inc{S|}", { RMeBP
}, 0 },
2589 { "inc{S|}", { RMeSI
}, 0 },
2590 { "inc{S|}", { RMeDI
}, 0 },
2592 { "dec{S|}", { RMeAX
}, 0 },
2593 { "dec{S|}", { RMeCX
}, 0 },
2594 { "dec{S|}", { RMeDX
}, 0 },
2595 { "dec{S|}", { RMeBX
}, 0 },
2596 { "dec{S|}", { RMeSP
}, 0 },
2597 { "dec{S|}", { RMeBP
}, 0 },
2598 { "dec{S|}", { RMeSI
}, 0 },
2599 { "dec{S|}", { RMeDI
}, 0 },
2601 { "pushV", { RMrAX
}, 0 },
2602 { "pushV", { RMrCX
}, 0 },
2603 { "pushV", { RMrDX
}, 0 },
2604 { "pushV", { RMrBX
}, 0 },
2605 { "pushV", { RMrSP
}, 0 },
2606 { "pushV", { RMrBP
}, 0 },
2607 { "pushV", { RMrSI
}, 0 },
2608 { "pushV", { RMrDI
}, 0 },
2610 { "popV", { RMrAX
}, 0 },
2611 { "popV", { RMrCX
}, 0 },
2612 { "popV", { RMrDX
}, 0 },
2613 { "popV", { RMrBX
}, 0 },
2614 { "popV", { RMrSP
}, 0 },
2615 { "popV", { RMrBP
}, 0 },
2616 { "popV", { RMrSI
}, 0 },
2617 { "popV", { RMrDI
}, 0 },
2619 { X86_64_TABLE (X86_64_60
) },
2620 { X86_64_TABLE (X86_64_61
) },
2621 { X86_64_TABLE (X86_64_62
) },
2622 { X86_64_TABLE (X86_64_63
) },
2623 { Bad_Opcode
}, /* seg fs */
2624 { Bad_Opcode
}, /* seg gs */
2625 { Bad_Opcode
}, /* op size prefix */
2626 { Bad_Opcode
}, /* adr size prefix */
2628 { "pushT", { sIv
}, 0 },
2629 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2630 { "pushT", { sIbT
}, 0 },
2631 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2632 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2633 { X86_64_TABLE (X86_64_6D
) },
2634 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2635 { X86_64_TABLE (X86_64_6F
) },
2637 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2638 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2639 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2640 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2641 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2642 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2643 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2644 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2646 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2647 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2648 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2649 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2650 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2651 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2652 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2653 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2655 { REG_TABLE (REG_80
) },
2656 { REG_TABLE (REG_81
) },
2658 { REG_TABLE (REG_82
) },
2659 { "testB", { Eb
, Gb
}, 0 },
2660 { "testS", { Ev
, Gv
}, 0 },
2661 { "xchgB", { Ebh2
, Gb
}, 0 },
2662 { "xchgS", { Evh2
, Gv
}, 0 },
2664 { "movB", { Ebh3
, Gb
}, 0 },
2665 { "movS", { Evh3
, Gv
}, 0 },
2666 { "movB", { Gb
, EbS
}, 0 },
2667 { "movS", { Gv
, EvS
}, 0 },
2668 { "movD", { Sv
, Sw
}, 0 },
2669 { MOD_TABLE (MOD_8D
) },
2670 { "movD", { Sw
, Sv
}, 0 },
2671 { REG_TABLE (REG_8F
) },
2673 { PREFIX_TABLE (PREFIX_90
) },
2674 { "xchgS", { RMeCX
, eAX
}, 0 },
2675 { "xchgS", { RMeDX
, eAX
}, 0 },
2676 { "xchgS", { RMeBX
, eAX
}, 0 },
2677 { "xchgS", { RMeSP
, eAX
}, 0 },
2678 { "xchgS", { RMeBP
, eAX
}, 0 },
2679 { "xchgS", { RMeSI
, eAX
}, 0 },
2680 { "xchgS", { RMeDI
, eAX
}, 0 },
2682 { "cW{t|}R", { XX
}, 0 },
2683 { "cR{t|}O", { XX
}, 0 },
2684 { X86_64_TABLE (X86_64_9A
) },
2685 { Bad_Opcode
}, /* fwait */
2686 { "pushfT", { XX
}, 0 },
2687 { "popfT", { XX
}, 0 },
2688 { "sahf", { XX
}, 0 },
2689 { "lahf", { XX
}, 0 },
2691 { "mov%LB", { AL
, Ob
}, 0 },
2692 { "mov%LS", { eAX
, Ov
}, 0 },
2693 { "mov%LB", { Ob
, AL
}, 0 },
2694 { "mov%LS", { Ov
, eAX
}, 0 },
2695 { "movs{b|}", { Ybr
, Xb
}, 0 },
2696 { "movs{R|}", { Yvr
, Xv
}, 0 },
2697 { "cmps{b|}", { Xb
, Yb
}, 0 },
2698 { "cmps{R|}", { Xv
, Yv
}, 0 },
2700 { "testB", { AL
, Ib
}, 0 },
2701 { "testS", { eAX
, Iv
}, 0 },
2702 { "stosB", { Ybr
, AL
}, 0 },
2703 { "stosS", { Yvr
, eAX
}, 0 },
2704 { "lodsB", { ALr
, Xb
}, 0 },
2705 { "lodsS", { eAXr
, Xv
}, 0 },
2706 { "scasB", { AL
, Yb
}, 0 },
2707 { "scasS", { eAX
, Yv
}, 0 },
2709 { "movB", { RMAL
, Ib
}, 0 },
2710 { "movB", { RMCL
, Ib
}, 0 },
2711 { "movB", { RMDL
, Ib
}, 0 },
2712 { "movB", { RMBL
, Ib
}, 0 },
2713 { "movB", { RMAH
, Ib
}, 0 },
2714 { "movB", { RMCH
, Ib
}, 0 },
2715 { "movB", { RMDH
, Ib
}, 0 },
2716 { "movB", { RMBH
, Ib
}, 0 },
2718 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2719 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2720 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2721 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2722 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2723 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2724 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2725 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2727 { REG_TABLE (REG_C0
) },
2728 { REG_TABLE (REG_C1
) },
2729 { "retT", { Iw
, BND
}, 0 },
2730 { "retT", { BND
}, 0 },
2731 { X86_64_TABLE (X86_64_C4
) },
2732 { X86_64_TABLE (X86_64_C5
) },
2733 { REG_TABLE (REG_C6
) },
2734 { REG_TABLE (REG_C7
) },
2736 { "enterT", { Iw
, Ib
}, 0 },
2737 { "leaveT", { XX
}, 0 },
2738 { "Jret{|f}P", { Iw
}, 0 },
2739 { "Jret{|f}P", { XX
}, 0 },
2740 { "int3", { XX
}, 0 },
2741 { "int", { Ib
}, 0 },
2742 { X86_64_TABLE (X86_64_CE
) },
2743 { "iret%LP", { XX
}, 0 },
2745 { REG_TABLE (REG_D0
) },
2746 { REG_TABLE (REG_D1
) },
2747 { REG_TABLE (REG_D2
) },
2748 { REG_TABLE (REG_D3
) },
2749 { X86_64_TABLE (X86_64_D4
) },
2750 { X86_64_TABLE (X86_64_D5
) },
2752 { "xlat", { DSBX
}, 0 },
2763 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2764 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2765 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2766 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2767 { "inB", { AL
, Ib
}, 0 },
2768 { "inG", { zAX
, Ib
}, 0 },
2769 { "outB", { Ib
, AL
}, 0 },
2770 { "outG", { Ib
, zAX
}, 0 },
2772 { X86_64_TABLE (X86_64_E8
) },
2773 { X86_64_TABLE (X86_64_E9
) },
2774 { X86_64_TABLE (X86_64_EA
) },
2775 { "jmp", { Jb
, BND
}, 0 },
2776 { "inB", { AL
, indirDX
}, 0 },
2777 { "inG", { zAX
, indirDX
}, 0 },
2778 { "outB", { indirDX
, AL
}, 0 },
2779 { "outG", { indirDX
, zAX
}, 0 },
2781 { Bad_Opcode
}, /* lock prefix */
2782 { "icebp", { XX
}, 0 },
2783 { Bad_Opcode
}, /* repne */
2784 { Bad_Opcode
}, /* repz */
2785 { "hlt", { XX
}, 0 },
2786 { "cmc", { XX
}, 0 },
2787 { REG_TABLE (REG_F6
) },
2788 { REG_TABLE (REG_F7
) },
2790 { "clc", { XX
}, 0 },
2791 { "stc", { XX
}, 0 },
2792 { "cli", { XX
}, 0 },
2793 { "sti", { XX
}, 0 },
2794 { "cld", { XX
}, 0 },
2795 { "std", { XX
}, 0 },
2796 { REG_TABLE (REG_FE
) },
2797 { REG_TABLE (REG_FF
) },
2800 static const struct dis386 dis386_twobyte
[] = {
2802 { REG_TABLE (REG_0F00
) },
2803 { REG_TABLE (REG_0F01
) },
2804 { "larS", { Gv
, Ew
}, 0 },
2805 { "lslS", { Gv
, Ew
}, 0 },
2807 { "syscall", { XX
}, 0 },
2808 { "clts", { XX
}, 0 },
2809 { "sysret%LP", { XX
}, 0 },
2811 { "invd", { XX
}, 0 },
2812 { "wbinvd", { XX
}, 0 },
2814 { "ud2", { XX
}, 0 },
2816 { REG_TABLE (REG_0F0D
) },
2817 { "femms", { XX
}, 0 },
2818 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2820 { PREFIX_TABLE (PREFIX_0F10
) },
2821 { PREFIX_TABLE (PREFIX_0F11
) },
2822 { PREFIX_TABLE (PREFIX_0F12
) },
2823 { MOD_TABLE (MOD_0F13
) },
2824 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2825 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2826 { PREFIX_TABLE (PREFIX_0F16
) },
2827 { MOD_TABLE (MOD_0F17
) },
2829 { REG_TABLE (REG_0F18
) },
2830 { "nopQ", { Ev
}, 0 },
2831 { PREFIX_TABLE (PREFIX_0F1A
) },
2832 { PREFIX_TABLE (PREFIX_0F1B
) },
2833 { "nopQ", { Ev
}, 0 },
2834 { "nopQ", { Ev
}, 0 },
2835 { "nopQ", { Ev
}, 0 },
2836 { "nopQ", { Ev
}, 0 },
2838 { "movZ", { Rm
, Cm
}, 0 },
2839 { "movZ", { Rm
, Dm
}, 0 },
2840 { "movZ", { Cm
, Rm
}, 0 },
2841 { "movZ", { Dm
, Rm
}, 0 },
2842 { MOD_TABLE (MOD_0F24
) },
2844 { MOD_TABLE (MOD_0F26
) },
2847 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2848 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2849 { PREFIX_TABLE (PREFIX_0F2A
) },
2850 { PREFIX_TABLE (PREFIX_0F2B
) },
2851 { PREFIX_TABLE (PREFIX_0F2C
) },
2852 { PREFIX_TABLE (PREFIX_0F2D
) },
2853 { PREFIX_TABLE (PREFIX_0F2E
) },
2854 { PREFIX_TABLE (PREFIX_0F2F
) },
2856 { "wrmsr", { XX
}, 0 },
2857 { "rdtsc", { XX
}, 0 },
2858 { "rdmsr", { XX
}, 0 },
2859 { "rdpmc", { XX
}, 0 },
2860 { "sysenter", { XX
}, 0 },
2861 { "sysexit", { XX
}, 0 },
2863 { "getsec", { XX
}, 0 },
2865 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2867 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2874 { "cmovoS", { Gv
, Ev
}, 0 },
2875 { "cmovnoS", { Gv
, Ev
}, 0 },
2876 { "cmovbS", { Gv
, Ev
}, 0 },
2877 { "cmovaeS", { Gv
, Ev
}, 0 },
2878 { "cmoveS", { Gv
, Ev
}, 0 },
2879 { "cmovneS", { Gv
, Ev
}, 0 },
2880 { "cmovbeS", { Gv
, Ev
}, 0 },
2881 { "cmovaS", { Gv
, Ev
}, 0 },
2883 { "cmovsS", { Gv
, Ev
}, 0 },
2884 { "cmovnsS", { Gv
, Ev
}, 0 },
2885 { "cmovpS", { Gv
, Ev
}, 0 },
2886 { "cmovnpS", { Gv
, Ev
}, 0 },
2887 { "cmovlS", { Gv
, Ev
}, 0 },
2888 { "cmovgeS", { Gv
, Ev
}, 0 },
2889 { "cmovleS", { Gv
, Ev
}, 0 },
2890 { "cmovgS", { Gv
, Ev
}, 0 },
2892 { MOD_TABLE (MOD_0F51
) },
2893 { PREFIX_TABLE (PREFIX_0F51
) },
2894 { PREFIX_TABLE (PREFIX_0F52
) },
2895 { PREFIX_TABLE (PREFIX_0F53
) },
2896 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2897 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2898 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2899 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2901 { PREFIX_TABLE (PREFIX_0F58
) },
2902 { PREFIX_TABLE (PREFIX_0F59
) },
2903 { PREFIX_TABLE (PREFIX_0F5A
) },
2904 { PREFIX_TABLE (PREFIX_0F5B
) },
2905 { PREFIX_TABLE (PREFIX_0F5C
) },
2906 { PREFIX_TABLE (PREFIX_0F5D
) },
2907 { PREFIX_TABLE (PREFIX_0F5E
) },
2908 { PREFIX_TABLE (PREFIX_0F5F
) },
2910 { PREFIX_TABLE (PREFIX_0F60
) },
2911 { PREFIX_TABLE (PREFIX_0F61
) },
2912 { PREFIX_TABLE (PREFIX_0F62
) },
2913 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2914 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2915 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2916 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2917 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2919 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2920 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2921 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2922 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2923 { PREFIX_TABLE (PREFIX_0F6C
) },
2924 { PREFIX_TABLE (PREFIX_0F6D
) },
2925 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2926 { PREFIX_TABLE (PREFIX_0F6F
) },
2928 { PREFIX_TABLE (PREFIX_0F70
) },
2929 { REG_TABLE (REG_0F71
) },
2930 { REG_TABLE (REG_0F72
) },
2931 { REG_TABLE (REG_0F73
) },
2932 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2933 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2934 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2935 { "emms", { XX
}, PREFIX_OPCODE
},
2937 { PREFIX_TABLE (PREFIX_0F78
) },
2938 { PREFIX_TABLE (PREFIX_0F79
) },
2939 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2941 { PREFIX_TABLE (PREFIX_0F7C
) },
2942 { PREFIX_TABLE (PREFIX_0F7D
) },
2943 { PREFIX_TABLE (PREFIX_0F7E
) },
2944 { PREFIX_TABLE (PREFIX_0F7F
) },
2946 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2947 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2948 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2949 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2950 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2951 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2952 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2953 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2955 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2956 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2957 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2958 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2959 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2960 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2961 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2962 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2964 { "seto", { Eb
}, 0 },
2965 { "setno", { Eb
}, 0 },
2966 { "setb", { Eb
}, 0 },
2967 { "setae", { Eb
}, 0 },
2968 { "sete", { Eb
}, 0 },
2969 { "setne", { Eb
}, 0 },
2970 { "setbe", { Eb
}, 0 },
2971 { "seta", { Eb
}, 0 },
2973 { "sets", { Eb
}, 0 },
2974 { "setns", { Eb
}, 0 },
2975 { "setp", { Eb
}, 0 },
2976 { "setnp", { Eb
}, 0 },
2977 { "setl", { Eb
}, 0 },
2978 { "setge", { Eb
}, 0 },
2979 { "setle", { Eb
}, 0 },
2980 { "setg", { Eb
}, 0 },
2982 { "pushT", { fs
}, 0 },
2983 { "popT", { fs
}, 0 },
2984 { "cpuid", { XX
}, 0 },
2985 { "btS", { Ev
, Gv
}, 0 },
2986 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2987 { "shldS", { Ev
, Gv
, CL
}, 0 },
2988 { REG_TABLE (REG_0FA6
) },
2989 { REG_TABLE (REG_0FA7
) },
2991 { "pushT", { gs
}, 0 },
2992 { "popT", { gs
}, 0 },
2993 { "rsm", { XX
}, 0 },
2994 { "btsS", { Evh1
, Gv
}, 0 },
2995 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2996 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2997 { REG_TABLE (REG_0FAE
) },
2998 { "imulS", { Gv
, Ev
}, 0 },
3000 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
3001 { "cmpxchgS", { Evh1
, Gv
}, 0 },
3002 { MOD_TABLE (MOD_0FB2
) },
3003 { "btrS", { Evh1
, Gv
}, 0 },
3004 { MOD_TABLE (MOD_0FB4
) },
3005 { MOD_TABLE (MOD_0FB5
) },
3006 { "movz{bR|x}", { Gv
, Eb
}, 0 },
3007 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
3009 { PREFIX_TABLE (PREFIX_0FB8
) },
3010 { "ud1", { XX
}, 0 },
3011 { REG_TABLE (REG_0FBA
) },
3012 { "btcS", { Evh1
, Gv
}, 0 },
3013 { PREFIX_TABLE (PREFIX_0FBC
) },
3014 { PREFIX_TABLE (PREFIX_0FBD
) },
3015 { "movs{bR|x}", { Gv
, Eb
}, 0 },
3016 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
3018 { "xaddB", { Ebh1
, Gb
}, 0 },
3019 { "xaddS", { Evh1
, Gv
}, 0 },
3020 { PREFIX_TABLE (PREFIX_0FC2
) },
3021 { MOD_TABLE (MOD_0FC3
) },
3022 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
3023 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
3024 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3025 { REG_TABLE (REG_0FC7
) },
3027 { "bswap", { RMeAX
}, 0 },
3028 { "bswap", { RMeCX
}, 0 },
3029 { "bswap", { RMeDX
}, 0 },
3030 { "bswap", { RMeBX
}, 0 },
3031 { "bswap", { RMeSP
}, 0 },
3032 { "bswap", { RMeBP
}, 0 },
3033 { "bswap", { RMeSI
}, 0 },
3034 { "bswap", { RMeDI
}, 0 },
3036 { PREFIX_TABLE (PREFIX_0FD0
) },
3037 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
3038 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
3039 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
3040 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
3041 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
3042 { PREFIX_TABLE (PREFIX_0FD6
) },
3043 { MOD_TABLE (MOD_0FD7
) },
3045 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
3046 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
3047 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
3048 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
3049 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
3050 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
3051 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
3052 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
3054 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
3055 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
3056 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
3057 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
3058 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
3059 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
3060 { PREFIX_TABLE (PREFIX_0FE6
) },
3061 { PREFIX_TABLE (PREFIX_0FE7
) },
3063 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
3064 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
3065 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
3066 { "por", { MX
, EM
}, PREFIX_OPCODE
},
3067 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
3068 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
3069 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
3070 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
3072 { PREFIX_TABLE (PREFIX_0FF0
) },
3073 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
3074 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
3075 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
3076 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
3077 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
3078 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
3079 { PREFIX_TABLE (PREFIX_0FF7
) },
3081 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
3082 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
3083 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
3084 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
3085 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
3086 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
3087 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
3091 static const unsigned char onebyte_has_modrm
[256] = {
3092 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3093 /* ------------------------------- */
3094 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3095 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3096 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3097 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3098 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3099 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3100 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3101 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3102 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3103 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3104 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3105 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3106 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3107 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3108 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3109 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3110 /* ------------------------------- */
3111 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3114 static const unsigned char twobyte_has_modrm
[256] = {
3115 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3116 /* ------------------------------- */
3117 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3118 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3119 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3120 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3121 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3122 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3123 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3124 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3125 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3126 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3127 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3128 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3129 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3130 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3131 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3132 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3133 /* ------------------------------- */
3134 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3137 static char obuf
[100];
3139 static char *mnemonicendp
;
3140 static char scratchbuf
[100];
3141 static unsigned char *start_codep
;
3142 static unsigned char *insn_codep
;
3143 static unsigned char *codep
;
3144 static unsigned char *end_codep
;
3145 static int last_lock_prefix
;
3146 static int last_repz_prefix
;
3147 static int last_repnz_prefix
;
3148 static int last_data_prefix
;
3149 static int last_addr_prefix
;
3150 static int last_rex_prefix
;
3151 static int last_seg_prefix
;
3152 static int fwait_prefix
;
3153 /* The active segment register prefix. */
3154 static int active_seg_prefix
;
3155 #define MAX_CODE_LENGTH 15
3156 /* We can up to 14 prefixes since the maximum instruction length is
3158 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3159 static disassemble_info
*the_info
;
3167 static unsigned char need_modrm
;
3177 int register_specifier
;
3184 int mask_register_specifier
;
3190 static unsigned char need_vex
;
3191 static unsigned char need_vex_reg
;
3192 static unsigned char vex_w_done
;
3200 /* If we are accessing mod/rm/reg without need_modrm set, then the
3201 values are stale. Hitting this abort likely indicates that you
3202 need to update onebyte_has_modrm or twobyte_has_modrm. */
3203 #define MODRM_CHECK if (!need_modrm) abort ()
3205 static const char **names64
;
3206 static const char **names32
;
3207 static const char **names16
;
3208 static const char **names8
;
3209 static const char **names8rex
;
3210 static const char **names_seg
;
3211 static const char *index64
;
3212 static const char *index32
;
3213 static const char **index16
;
3214 static const char **names_bnd
;
3216 static const char *intel_names64
[] = {
3217 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3218 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3220 static const char *intel_names32
[] = {
3221 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3222 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3224 static const char *intel_names16
[] = {
3225 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3226 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3228 static const char *intel_names8
[] = {
3229 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3231 static const char *intel_names8rex
[] = {
3232 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3233 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3235 static const char *intel_names_seg
[] = {
3236 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3238 static const char *intel_index64
= "riz";
3239 static const char *intel_index32
= "eiz";
3240 static const char *intel_index16
[] = {
3241 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3244 static const char *att_names64
[] = {
3245 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3246 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3248 static const char *att_names32
[] = {
3249 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3250 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3252 static const char *att_names16
[] = {
3253 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3254 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3256 static const char *att_names8
[] = {
3257 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3259 static const char *att_names8rex
[] = {
3260 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3261 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3263 static const char *att_names_seg
[] = {
3264 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3266 static const char *att_index64
= "%riz";
3267 static const char *att_index32
= "%eiz";
3268 static const char *att_index16
[] = {
3269 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3272 static const char **names_mm
;
3273 static const char *intel_names_mm
[] = {
3274 "mm0", "mm1", "mm2", "mm3",
3275 "mm4", "mm5", "mm6", "mm7"
3277 static const char *att_names_mm
[] = {
3278 "%mm0", "%mm1", "%mm2", "%mm3",
3279 "%mm4", "%mm5", "%mm6", "%mm7"
3282 static const char *intel_names_bnd
[] = {
3283 "bnd0", "bnd1", "bnd2", "bnd3"
3286 static const char *att_names_bnd
[] = {
3287 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3290 static const char **names_xmm
;
3291 static const char *intel_names_xmm
[] = {
3292 "xmm0", "xmm1", "xmm2", "xmm3",
3293 "xmm4", "xmm5", "xmm6", "xmm7",
3294 "xmm8", "xmm9", "xmm10", "xmm11",
3295 "xmm12", "xmm13", "xmm14", "xmm15",
3296 "xmm16", "xmm17", "xmm18", "xmm19",
3297 "xmm20", "xmm21", "xmm22", "xmm23",
3298 "xmm24", "xmm25", "xmm26", "xmm27",
3299 "xmm28", "xmm29", "xmm30", "xmm31"
3301 static const char *att_names_xmm
[] = {
3302 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3303 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3304 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3305 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3306 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3307 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3308 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3309 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3312 static const char **names_ymm
;
3313 static const char *intel_names_ymm
[] = {
3314 "ymm0", "ymm1", "ymm2", "ymm3",
3315 "ymm4", "ymm5", "ymm6", "ymm7",
3316 "ymm8", "ymm9", "ymm10", "ymm11",
3317 "ymm12", "ymm13", "ymm14", "ymm15",
3318 "ymm16", "ymm17", "ymm18", "ymm19",
3319 "ymm20", "ymm21", "ymm22", "ymm23",
3320 "ymm24", "ymm25", "ymm26", "ymm27",
3321 "ymm28", "ymm29", "ymm30", "ymm31"
3323 static const char *att_names_ymm
[] = {
3324 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3325 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3326 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3327 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3328 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3329 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3330 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3331 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3334 static const char **names_zmm
;
3335 static const char *intel_names_zmm
[] = {
3336 "zmm0", "zmm1", "zmm2", "zmm3",
3337 "zmm4", "zmm5", "zmm6", "zmm7",
3338 "zmm8", "zmm9", "zmm10", "zmm11",
3339 "zmm12", "zmm13", "zmm14", "zmm15",
3340 "zmm16", "zmm17", "zmm18", "zmm19",
3341 "zmm20", "zmm21", "zmm22", "zmm23",
3342 "zmm24", "zmm25", "zmm26", "zmm27",
3343 "zmm28", "zmm29", "zmm30", "zmm31"
3345 static const char *att_names_zmm
[] = {
3346 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3347 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3348 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3349 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3350 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3351 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3352 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3353 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3356 static const char **names_mask
;
3357 static const char *intel_names_mask
[] = {
3358 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3360 static const char *att_names_mask
[] = {
3361 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3364 static const char *names_rounding
[] =
3372 static const struct dis386 reg_table
[][8] = {
3375 { "addA", { Ebh1
, Ib
}, 0 },
3376 { "orA", { Ebh1
, Ib
}, 0 },
3377 { "adcA", { Ebh1
, Ib
}, 0 },
3378 { "sbbA", { Ebh1
, Ib
}, 0 },
3379 { "andA", { Ebh1
, Ib
}, 0 },
3380 { "subA", { Ebh1
, Ib
}, 0 },
3381 { "xorA", { Ebh1
, Ib
}, 0 },
3382 { "cmpA", { Eb
, Ib
}, 0 },
3386 { "addQ", { Evh1
, Iv
}, 0 },
3387 { "orQ", { Evh1
, Iv
}, 0 },
3388 { "adcQ", { Evh1
, Iv
}, 0 },
3389 { "sbbQ", { Evh1
, Iv
}, 0 },
3390 { "andQ", { Evh1
, Iv
}, 0 },
3391 { "subQ", { Evh1
, Iv
}, 0 },
3392 { "xorQ", { Evh1
, Iv
}, 0 },
3393 { "cmpQ", { Ev
, Iv
}, 0 },
3397 { "addQ", { Evh1
, sIb
}, 0 },
3398 { "orQ", { Evh1
, sIb
}, 0 },
3399 { "adcQ", { Evh1
, sIb
}, 0 },
3400 { "sbbQ", { Evh1
, sIb
}, 0 },
3401 { "andQ", { Evh1
, sIb
}, 0 },
3402 { "subQ", { Evh1
, sIb
}, 0 },
3403 { "xorQ", { Evh1
, sIb
}, 0 },
3404 { "cmpQ", { Ev
, sIb
}, 0 },
3408 { "popU", { stackEv
}, 0 },
3409 { XOP_8F_TABLE (XOP_09
) },
3413 { XOP_8F_TABLE (XOP_09
) },
3417 { "rolA", { Eb
, Ib
}, 0 },
3418 { "rorA", { Eb
, Ib
}, 0 },
3419 { "rclA", { Eb
, Ib
}, 0 },
3420 { "rcrA", { Eb
, Ib
}, 0 },
3421 { "shlA", { Eb
, Ib
}, 0 },
3422 { "shrA", { Eb
, Ib
}, 0 },
3424 { "sarA", { Eb
, Ib
}, 0 },
3428 { "rolQ", { Ev
, Ib
}, 0 },
3429 { "rorQ", { Ev
, Ib
}, 0 },
3430 { "rclQ", { Ev
, Ib
}, 0 },
3431 { "rcrQ", { Ev
, Ib
}, 0 },
3432 { "shlQ", { Ev
, Ib
}, 0 },
3433 { "shrQ", { Ev
, Ib
}, 0 },
3435 { "sarQ", { Ev
, Ib
}, 0 },
3439 { "movA", { Ebh3
, Ib
}, 0 },
3446 { MOD_TABLE (MOD_C6_REG_7
) },
3450 { "movQ", { Evh3
, Iv
}, 0 },
3457 { MOD_TABLE (MOD_C7_REG_7
) },
3461 { "rolA", { Eb
, I1
}, 0 },
3462 { "rorA", { Eb
, I1
}, 0 },
3463 { "rclA", { Eb
, I1
}, 0 },
3464 { "rcrA", { Eb
, I1
}, 0 },
3465 { "shlA", { Eb
, I1
}, 0 },
3466 { "shrA", { Eb
, I1
}, 0 },
3468 { "sarA", { Eb
, I1
}, 0 },
3472 { "rolQ", { Ev
, I1
}, 0 },
3473 { "rorQ", { Ev
, I1
}, 0 },
3474 { "rclQ", { Ev
, I1
}, 0 },
3475 { "rcrQ", { Ev
, I1
}, 0 },
3476 { "shlQ", { Ev
, I1
}, 0 },
3477 { "shrQ", { Ev
, I1
}, 0 },
3479 { "sarQ", { Ev
, I1
}, 0 },
3483 { "rolA", { Eb
, CL
}, 0 },
3484 { "rorA", { Eb
, CL
}, 0 },
3485 { "rclA", { Eb
, CL
}, 0 },
3486 { "rcrA", { Eb
, CL
}, 0 },
3487 { "shlA", { Eb
, CL
}, 0 },
3488 { "shrA", { Eb
, CL
}, 0 },
3490 { "sarA", { Eb
, CL
}, 0 },
3494 { "rolQ", { Ev
, CL
}, 0 },
3495 { "rorQ", { Ev
, CL
}, 0 },
3496 { "rclQ", { Ev
, CL
}, 0 },
3497 { "rcrQ", { Ev
, CL
}, 0 },
3498 { "shlQ", { Ev
, CL
}, 0 },
3499 { "shrQ", { Ev
, CL
}, 0 },
3501 { "sarQ", { Ev
, CL
}, 0 },
3505 { "testA", { Eb
, Ib
}, 0 },
3507 { "notA", { Ebh1
}, 0 },
3508 { "negA", { Ebh1
}, 0 },
3509 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3510 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3511 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3512 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3516 { "testQ", { Ev
, Iv
}, 0 },
3518 { "notQ", { Evh1
}, 0 },
3519 { "negQ", { Evh1
}, 0 },
3520 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3521 { "imulQ", { Ev
}, 0 },
3522 { "divQ", { Ev
}, 0 },
3523 { "idivQ", { Ev
}, 0 },
3527 { "incA", { Ebh1
}, 0 },
3528 { "decA", { Ebh1
}, 0 },
3532 { "incQ", { Evh1
}, 0 },
3533 { "decQ", { Evh1
}, 0 },
3534 { "call{T|}", { indirEv
, BND
}, 0 },
3535 { MOD_TABLE (MOD_FF_REG_3
) },
3536 { "jmp{T|}", { indirEv
, BND
}, 0 },
3537 { MOD_TABLE (MOD_FF_REG_5
) },
3538 { "pushU", { stackEv
}, 0 },
3543 { "sldtD", { Sv
}, 0 },
3544 { "strD", { Sv
}, 0 },
3545 { "lldt", { Ew
}, 0 },
3546 { "ltr", { Ew
}, 0 },
3547 { "verr", { Ew
}, 0 },
3548 { "verw", { Ew
}, 0 },
3554 { MOD_TABLE (MOD_0F01_REG_0
) },
3555 { MOD_TABLE (MOD_0F01_REG_1
) },
3556 { MOD_TABLE (MOD_0F01_REG_2
) },
3557 { MOD_TABLE (MOD_0F01_REG_3
) },
3558 { "smswD", { Sv
}, 0 },
3559 { MOD_TABLE (MOD_0F01_REG_5
) },
3560 { "lmsw", { Ew
}, 0 },
3561 { MOD_TABLE (MOD_0F01_REG_7
) },
3565 { "prefetch", { Mb
}, 0 },
3566 { "prefetchw", { Mb
}, 0 },
3567 { "prefetchwt1", { Mb
}, 0 },
3568 { "prefetch", { Mb
}, 0 },
3569 { "prefetch", { Mb
}, 0 },
3570 { "prefetch", { Mb
}, 0 },
3571 { "prefetch", { Mb
}, 0 },
3572 { "prefetch", { Mb
}, 0 },
3576 { MOD_TABLE (MOD_0F18_REG_0
) },
3577 { MOD_TABLE (MOD_0F18_REG_1
) },
3578 { MOD_TABLE (MOD_0F18_REG_2
) },
3579 { MOD_TABLE (MOD_0F18_REG_3
) },
3580 { MOD_TABLE (MOD_0F18_REG_4
) },
3581 { MOD_TABLE (MOD_0F18_REG_5
) },
3582 { MOD_TABLE (MOD_0F18_REG_6
) },
3583 { MOD_TABLE (MOD_0F18_REG_7
) },
3589 { MOD_TABLE (MOD_0F71_REG_2
) },
3591 { MOD_TABLE (MOD_0F71_REG_4
) },
3593 { MOD_TABLE (MOD_0F71_REG_6
) },
3599 { MOD_TABLE (MOD_0F72_REG_2
) },
3601 { MOD_TABLE (MOD_0F72_REG_4
) },
3603 { MOD_TABLE (MOD_0F72_REG_6
) },
3609 { MOD_TABLE (MOD_0F73_REG_2
) },
3610 { MOD_TABLE (MOD_0F73_REG_3
) },
3613 { MOD_TABLE (MOD_0F73_REG_6
) },
3614 { MOD_TABLE (MOD_0F73_REG_7
) },
3618 { "montmul", { { OP_0f07
, 0 } }, 0 },
3619 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3620 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3624 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3625 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3626 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3627 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3628 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3629 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3633 { MOD_TABLE (MOD_0FAE_REG_0
) },
3634 { MOD_TABLE (MOD_0FAE_REG_1
) },
3635 { MOD_TABLE (MOD_0FAE_REG_2
) },
3636 { MOD_TABLE (MOD_0FAE_REG_3
) },
3637 { MOD_TABLE (MOD_0FAE_REG_4
) },
3638 { MOD_TABLE (MOD_0FAE_REG_5
) },
3639 { MOD_TABLE (MOD_0FAE_REG_6
) },
3640 { MOD_TABLE (MOD_0FAE_REG_7
) },
3648 { "btQ", { Ev
, Ib
}, 0 },
3649 { "btsQ", { Evh1
, Ib
}, 0 },
3650 { "btrQ", { Evh1
, Ib
}, 0 },
3651 { "btcQ", { Evh1
, Ib
}, 0 },
3656 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3658 { MOD_TABLE (MOD_0FC7_REG_3
) },
3659 { MOD_TABLE (MOD_0FC7_REG_4
) },
3660 { MOD_TABLE (MOD_0FC7_REG_5
) },
3661 { MOD_TABLE (MOD_0FC7_REG_6
) },
3662 { MOD_TABLE (MOD_0FC7_REG_7
) },
3668 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3670 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3672 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3678 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3680 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3682 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3688 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3689 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3692 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3693 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3699 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3700 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3702 /* REG_VEX_0F38F3 */
3705 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3706 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3707 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3711 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3712 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3716 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3717 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3719 /* REG_XOP_TBM_01 */
3722 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3723 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3724 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3725 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3726 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3727 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3728 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3730 /* REG_XOP_TBM_02 */
3733 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3738 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3740 #define NEED_REG_TABLE
3741 #include "i386-dis-evex.h"
3742 #undef NEED_REG_TABLE
3745 static const struct dis386 prefix_table
[][4] = {
3748 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3749 { "pause", { XX
}, 0 },
3750 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3751 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3756 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3757 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3758 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3759 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3764 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3765 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3766 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3767 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3772 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3773 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3774 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3775 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3780 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3781 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3782 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3787 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3788 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3789 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3790 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3795 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3796 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3797 { "bndmov", { Ebnd
, Gbnd
}, 0 },
3798 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3803 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3804 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_OPCODE
},
3805 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3806 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3811 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3812 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3813 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3814 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3819 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3820 { "cvttss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3821 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3822 { "cvttsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3827 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3828 { "cvtss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3829 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3830 { "cvtsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3835 { "ucomiss",{ XM
, EXd
}, 0 },
3837 { "ucomisd",{ XM
, EXq
}, 0 },
3842 { "comiss", { XM
, EXd
}, 0 },
3844 { "comisd", { XM
, EXq
}, 0 },
3849 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3850 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3851 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3852 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3857 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3858 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3863 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3864 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3869 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3870 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3871 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3872 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3877 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3878 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3879 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3880 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3885 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3886 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3887 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3888 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3893 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3894 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3895 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3900 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3901 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3902 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3903 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3908 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3909 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3910 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3911 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3916 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3917 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3918 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3919 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3924 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3925 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3926 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3927 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3932 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3934 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3939 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3941 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3946 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3948 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3955 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3962 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3967 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3968 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3969 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3974 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3975 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3976 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3977 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3980 /* PREFIX_0F73_REG_3 */
3984 { "psrldq", { XS
, Ib
}, 0 },
3987 /* PREFIX_0F73_REG_7 */
3991 { "pslldq", { XS
, Ib
}, 0 },
3996 {"vmread", { Em
, Gm
}, 0 },
3998 {"extrq", { XS
, Ib
, Ib
}, 0 },
3999 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
4004 {"vmwrite", { Gm
, Em
}, 0 },
4006 {"extrq", { XM
, XS
}, 0 },
4007 {"insertq", { XM
, XS
}, 0 },
4014 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
4015 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
4022 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
4023 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
4028 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
4029 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
4030 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
4035 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
4036 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
4037 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
4040 /* PREFIX_0FAE_REG_0 */
4043 { "rdfsbase", { Ev
}, 0 },
4046 /* PREFIX_0FAE_REG_1 */
4049 { "rdgsbase", { Ev
}, 0 },
4052 /* PREFIX_0FAE_REG_2 */
4055 { "wrfsbase", { Ev
}, 0 },
4058 /* PREFIX_0FAE_REG_3 */
4061 { "wrgsbase", { Ev
}, 0 },
4064 /* PREFIX_0FAE_REG_6 */
4066 { "xsaveopt", { FXSAVE
}, 0 },
4068 { "clwb", { Mb
}, 0 },
4071 /* PREFIX_0FAE_REG_7 */
4073 { "clflush", { Mb
}, 0 },
4075 { "clflushopt", { Mb
}, 0 },
4078 /* PREFIX_RM_0_0FAE_REG_7 */
4080 { "sfence", { Skip_MODRM
}, 0 },
4082 { "pcommit", { Skip_MODRM
}, 0 },
4088 { "popcntS", { Gv
, Ev
}, 0 },
4093 { "bsfS", { Gv
, Ev
}, 0 },
4094 { "tzcntS", { Gv
, Ev
}, 0 },
4095 { "bsfS", { Gv
, Ev
}, 0 },
4100 { "bsrS", { Gv
, Ev
}, 0 },
4101 { "lzcntS", { Gv
, Ev
}, 0 },
4102 { "bsrS", { Gv
, Ev
}, 0 },
4107 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4108 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4109 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4110 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4113 /* PREFIX_MOD_0_0FC3 */
4115 { "movntiS", { Ev
, Gv
}, PREFIX_OPCODE
},
4118 /* PREFIX_MOD_0_0FC7_REG_6 */
4120 { "vmptrld",{ Mq
}, 0 },
4121 { "vmxon", { Mq
}, 0 },
4122 { "vmclear",{ Mq
}, 0 },
4125 /* PREFIX_MOD_3_0FC7_REG_6 */
4127 { "rdrand", { Ev
}, 0 },
4129 { "rdrand", { Ev
}, 0 }
4132 /* PREFIX_MOD_3_0FC7_REG_7 */
4134 { "rdseed", { Ev
}, 0 },
4135 { "rdpid", { Em
}, 0 },
4136 { "rdseed", { Ev
}, 0 },
4143 { "addsubpd", { XM
, EXx
}, 0 },
4144 { "addsubps", { XM
, EXx
}, 0 },
4150 { "movq2dq",{ XM
, MS
}, 0 },
4151 { "movq", { EXqS
, XM
}, 0 },
4152 { "movdq2q",{ MX
, XS
}, 0 },
4158 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4159 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4160 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4165 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4167 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4175 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4180 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4182 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4189 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4196 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4203 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4210 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4217 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4224 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4231 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4238 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4245 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4252 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4259 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4266 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4273 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4280 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4287 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4294 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4301 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4308 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4315 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4322 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4329 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4336 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4343 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4350 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4357 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4364 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4371 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4378 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4385 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4392 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4399 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4406 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4413 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4420 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4425 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4430 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4435 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4440 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4445 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4450 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4457 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4464 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4471 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4478 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4485 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4490 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4492 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4493 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4498 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4500 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4501 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4507 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4508 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4516 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4523 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4530 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4537 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4544 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4551 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4558 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4565 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4572 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4579 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4586 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4593 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4600 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4607 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4614 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4621 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4628 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4635 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4642 { "pcmpestrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4649 { "pcmpestri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4656 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4663 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4668 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4675 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4678 /* PREFIX_VEX_0F10 */
4680 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4681 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4682 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4683 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4686 /* PREFIX_VEX_0F11 */
4688 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4689 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4690 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4691 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4694 /* PREFIX_VEX_0F12 */
4696 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4697 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4698 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4699 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4702 /* PREFIX_VEX_0F16 */
4704 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4705 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4706 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4709 /* PREFIX_VEX_0F2A */
4712 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4714 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4717 /* PREFIX_VEX_0F2C */
4720 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4722 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4725 /* PREFIX_VEX_0F2D */
4728 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4730 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4733 /* PREFIX_VEX_0F2E */
4735 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4737 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4740 /* PREFIX_VEX_0F2F */
4742 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4744 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4747 /* PREFIX_VEX_0F41 */
4749 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4751 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4754 /* PREFIX_VEX_0F42 */
4756 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4758 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4761 /* PREFIX_VEX_0F44 */
4763 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4765 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4768 /* PREFIX_VEX_0F45 */
4770 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4772 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4775 /* PREFIX_VEX_0F46 */
4777 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4779 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4782 /* PREFIX_VEX_0F47 */
4784 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4786 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4789 /* PREFIX_VEX_0F4A */
4791 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4793 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4796 /* PREFIX_VEX_0F4B */
4798 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4800 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4803 /* PREFIX_VEX_0F51 */
4805 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4806 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4807 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4808 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4811 /* PREFIX_VEX_0F52 */
4813 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4814 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
4817 /* PREFIX_VEX_0F53 */
4819 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
4820 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
4823 /* PREFIX_VEX_0F58 */
4825 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
4826 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
4827 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
4828 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
4831 /* PREFIX_VEX_0F59 */
4833 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
4834 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
4835 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
4836 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
4839 /* PREFIX_VEX_0F5A */
4841 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
4842 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
4843 { "vcvtpd2ps%XY", { XMM
, EXx
}, 0 },
4844 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
4847 /* PREFIX_VEX_0F5B */
4849 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
4850 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
4851 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
4854 /* PREFIX_VEX_0F5C */
4856 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
4857 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
4858 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
4859 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
4862 /* PREFIX_VEX_0F5D */
4864 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
4865 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
4866 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
4867 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
4870 /* PREFIX_VEX_0F5E */
4872 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
4873 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
4874 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
4875 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
4878 /* PREFIX_VEX_0F5F */
4880 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
4881 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
4882 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
4883 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
4886 /* PREFIX_VEX_0F60 */
4890 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
4893 /* PREFIX_VEX_0F61 */
4897 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
4900 /* PREFIX_VEX_0F62 */
4904 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
4907 /* PREFIX_VEX_0F63 */
4911 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
4914 /* PREFIX_VEX_0F64 */
4918 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
4921 /* PREFIX_VEX_0F65 */
4925 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
4928 /* PREFIX_VEX_0F66 */
4932 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
4935 /* PREFIX_VEX_0F67 */
4939 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
4942 /* PREFIX_VEX_0F68 */
4946 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
4949 /* PREFIX_VEX_0F69 */
4953 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
4956 /* PREFIX_VEX_0F6A */
4960 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
4963 /* PREFIX_VEX_0F6B */
4967 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
4970 /* PREFIX_VEX_0F6C */
4974 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
4977 /* PREFIX_VEX_0F6D */
4981 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
4984 /* PREFIX_VEX_0F6E */
4988 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4991 /* PREFIX_VEX_0F6F */
4994 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
4995 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
4998 /* PREFIX_VEX_0F70 */
5001 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
5002 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
5003 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
5006 /* PREFIX_VEX_0F71_REG_2 */
5010 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
5013 /* PREFIX_VEX_0F71_REG_4 */
5017 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
5020 /* PREFIX_VEX_0F71_REG_6 */
5024 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
5027 /* PREFIX_VEX_0F72_REG_2 */
5031 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
5034 /* PREFIX_VEX_0F72_REG_4 */
5038 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
5041 /* PREFIX_VEX_0F72_REG_6 */
5045 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
5048 /* PREFIX_VEX_0F73_REG_2 */
5052 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
5055 /* PREFIX_VEX_0F73_REG_3 */
5059 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
5062 /* PREFIX_VEX_0F73_REG_6 */
5066 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
5069 /* PREFIX_VEX_0F73_REG_7 */
5073 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
5076 /* PREFIX_VEX_0F74 */
5080 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
5083 /* PREFIX_VEX_0F75 */
5087 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
5090 /* PREFIX_VEX_0F76 */
5094 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
5097 /* PREFIX_VEX_0F77 */
5099 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
5102 /* PREFIX_VEX_0F7C */
5106 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
5107 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
5110 /* PREFIX_VEX_0F7D */
5114 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
5115 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
5118 /* PREFIX_VEX_0F7E */
5121 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5122 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5125 /* PREFIX_VEX_0F7F */
5128 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
5129 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
5132 /* PREFIX_VEX_0F90 */
5134 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5136 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5139 /* PREFIX_VEX_0F91 */
5141 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5143 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5146 /* PREFIX_VEX_0F92 */
5148 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5150 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5151 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5154 /* PREFIX_VEX_0F93 */
5156 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5158 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5159 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5162 /* PREFIX_VEX_0F98 */
5164 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5166 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5169 /* PREFIX_VEX_0F99 */
5171 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5173 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5176 /* PREFIX_VEX_0FC2 */
5178 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
5179 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
5180 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
5181 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
5184 /* PREFIX_VEX_0FC4 */
5188 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5191 /* PREFIX_VEX_0FC5 */
5195 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5198 /* PREFIX_VEX_0FD0 */
5202 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
5203 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
5206 /* PREFIX_VEX_0FD1 */
5210 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
5213 /* PREFIX_VEX_0FD2 */
5217 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
5220 /* PREFIX_VEX_0FD3 */
5224 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
5227 /* PREFIX_VEX_0FD4 */
5231 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
5234 /* PREFIX_VEX_0FD5 */
5238 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
5241 /* PREFIX_VEX_0FD6 */
5245 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5248 /* PREFIX_VEX_0FD7 */
5252 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5255 /* PREFIX_VEX_0FD8 */
5259 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
5262 /* PREFIX_VEX_0FD9 */
5266 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
5269 /* PREFIX_VEX_0FDA */
5273 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
5276 /* PREFIX_VEX_0FDB */
5280 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
5283 /* PREFIX_VEX_0FDC */
5287 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
5290 /* PREFIX_VEX_0FDD */
5294 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
5297 /* PREFIX_VEX_0FDE */
5301 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
5304 /* PREFIX_VEX_0FDF */
5308 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
5311 /* PREFIX_VEX_0FE0 */
5315 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
5318 /* PREFIX_VEX_0FE1 */
5322 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
5325 /* PREFIX_VEX_0FE2 */
5329 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
5332 /* PREFIX_VEX_0FE3 */
5336 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
5339 /* PREFIX_VEX_0FE4 */
5343 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
5346 /* PREFIX_VEX_0FE5 */
5350 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
5353 /* PREFIX_VEX_0FE6 */
5356 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
5357 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
5358 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5361 /* PREFIX_VEX_0FE7 */
5365 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5368 /* PREFIX_VEX_0FE8 */
5372 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5375 /* PREFIX_VEX_0FE9 */
5379 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5382 /* PREFIX_VEX_0FEA */
5386 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5389 /* PREFIX_VEX_0FEB */
5393 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5396 /* PREFIX_VEX_0FEC */
5400 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5403 /* PREFIX_VEX_0FED */
5407 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5410 /* PREFIX_VEX_0FEE */
5414 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5417 /* PREFIX_VEX_0FEF */
5421 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5424 /* PREFIX_VEX_0FF0 */
5429 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5432 /* PREFIX_VEX_0FF1 */
5436 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5439 /* PREFIX_VEX_0FF2 */
5443 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5446 /* PREFIX_VEX_0FF3 */
5450 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5453 /* PREFIX_VEX_0FF4 */
5457 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5460 /* PREFIX_VEX_0FF5 */
5464 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5467 /* PREFIX_VEX_0FF6 */
5471 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5474 /* PREFIX_VEX_0FF7 */
5478 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5481 /* PREFIX_VEX_0FF8 */
5485 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5488 /* PREFIX_VEX_0FF9 */
5492 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5495 /* PREFIX_VEX_0FFA */
5499 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5502 /* PREFIX_VEX_0FFB */
5506 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5509 /* PREFIX_VEX_0FFC */
5513 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5516 /* PREFIX_VEX_0FFD */
5520 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5523 /* PREFIX_VEX_0FFE */
5527 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5530 /* PREFIX_VEX_0F3800 */
5534 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5537 /* PREFIX_VEX_0F3801 */
5541 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5544 /* PREFIX_VEX_0F3802 */
5548 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5551 /* PREFIX_VEX_0F3803 */
5555 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5558 /* PREFIX_VEX_0F3804 */
5562 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5565 /* PREFIX_VEX_0F3805 */
5569 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5572 /* PREFIX_VEX_0F3806 */
5576 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5579 /* PREFIX_VEX_0F3807 */
5583 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5586 /* PREFIX_VEX_0F3808 */
5590 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5593 /* PREFIX_VEX_0F3809 */
5597 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5600 /* PREFIX_VEX_0F380A */
5604 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5607 /* PREFIX_VEX_0F380B */
5611 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5614 /* PREFIX_VEX_0F380C */
5618 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5621 /* PREFIX_VEX_0F380D */
5625 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5628 /* PREFIX_VEX_0F380E */
5632 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5635 /* PREFIX_VEX_0F380F */
5639 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5642 /* PREFIX_VEX_0F3813 */
5646 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5649 /* PREFIX_VEX_0F3816 */
5653 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5656 /* PREFIX_VEX_0F3817 */
5660 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5663 /* PREFIX_VEX_0F3818 */
5667 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5670 /* PREFIX_VEX_0F3819 */
5674 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5677 /* PREFIX_VEX_0F381A */
5681 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5684 /* PREFIX_VEX_0F381C */
5688 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5691 /* PREFIX_VEX_0F381D */
5695 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5698 /* PREFIX_VEX_0F381E */
5702 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5705 /* PREFIX_VEX_0F3820 */
5709 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5712 /* PREFIX_VEX_0F3821 */
5716 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5719 /* PREFIX_VEX_0F3822 */
5723 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5726 /* PREFIX_VEX_0F3823 */
5730 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5733 /* PREFIX_VEX_0F3824 */
5737 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5740 /* PREFIX_VEX_0F3825 */
5744 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5747 /* PREFIX_VEX_0F3828 */
5751 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5754 /* PREFIX_VEX_0F3829 */
5758 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5761 /* PREFIX_VEX_0F382A */
5765 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5768 /* PREFIX_VEX_0F382B */
5772 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5775 /* PREFIX_VEX_0F382C */
5779 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5782 /* PREFIX_VEX_0F382D */
5786 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5789 /* PREFIX_VEX_0F382E */
5793 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5796 /* PREFIX_VEX_0F382F */
5800 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5803 /* PREFIX_VEX_0F3830 */
5807 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5810 /* PREFIX_VEX_0F3831 */
5814 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
5817 /* PREFIX_VEX_0F3832 */
5821 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
5824 /* PREFIX_VEX_0F3833 */
5828 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
5831 /* PREFIX_VEX_0F3834 */
5835 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
5838 /* PREFIX_VEX_0F3835 */
5842 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
5845 /* PREFIX_VEX_0F3836 */
5849 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5852 /* PREFIX_VEX_0F3837 */
5856 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
5859 /* PREFIX_VEX_0F3838 */
5863 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
5866 /* PREFIX_VEX_0F3839 */
5870 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
5873 /* PREFIX_VEX_0F383A */
5877 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
5880 /* PREFIX_VEX_0F383B */
5884 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
5887 /* PREFIX_VEX_0F383C */
5891 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
5894 /* PREFIX_VEX_0F383D */
5898 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
5901 /* PREFIX_VEX_0F383E */
5905 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
5908 /* PREFIX_VEX_0F383F */
5912 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
5915 /* PREFIX_VEX_0F3840 */
5919 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
5922 /* PREFIX_VEX_0F3841 */
5926 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5929 /* PREFIX_VEX_0F3845 */
5933 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5936 /* PREFIX_VEX_0F3846 */
5940 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5943 /* PREFIX_VEX_0F3847 */
5947 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5950 /* PREFIX_VEX_0F3858 */
5954 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5957 /* PREFIX_VEX_0F3859 */
5961 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5964 /* PREFIX_VEX_0F385A */
5968 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5971 /* PREFIX_VEX_0F3878 */
5975 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5978 /* PREFIX_VEX_0F3879 */
5982 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5985 /* PREFIX_VEX_0F388C */
5989 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5992 /* PREFIX_VEX_0F388E */
5996 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5999 /* PREFIX_VEX_0F3890 */
6003 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6006 /* PREFIX_VEX_0F3891 */
6010 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6013 /* PREFIX_VEX_0F3892 */
6017 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6020 /* PREFIX_VEX_0F3893 */
6024 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6027 /* PREFIX_VEX_0F3896 */
6031 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6034 /* PREFIX_VEX_0F3897 */
6038 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6041 /* PREFIX_VEX_0F3898 */
6045 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6048 /* PREFIX_VEX_0F3899 */
6052 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6055 /* PREFIX_VEX_0F389A */
6059 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6062 /* PREFIX_VEX_0F389B */
6066 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6069 /* PREFIX_VEX_0F389C */
6073 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6076 /* PREFIX_VEX_0F389D */
6080 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6083 /* PREFIX_VEX_0F389E */
6087 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6090 /* PREFIX_VEX_0F389F */
6094 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6097 /* PREFIX_VEX_0F38A6 */
6101 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6105 /* PREFIX_VEX_0F38A7 */
6109 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6112 /* PREFIX_VEX_0F38A8 */
6116 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6119 /* PREFIX_VEX_0F38A9 */
6123 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6126 /* PREFIX_VEX_0F38AA */
6130 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6133 /* PREFIX_VEX_0F38AB */
6137 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6140 /* PREFIX_VEX_0F38AC */
6144 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6147 /* PREFIX_VEX_0F38AD */
6151 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6154 /* PREFIX_VEX_0F38AE */
6158 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6161 /* PREFIX_VEX_0F38AF */
6165 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6168 /* PREFIX_VEX_0F38B6 */
6172 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6175 /* PREFIX_VEX_0F38B7 */
6179 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6182 /* PREFIX_VEX_0F38B8 */
6186 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6189 /* PREFIX_VEX_0F38B9 */
6193 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6196 /* PREFIX_VEX_0F38BA */
6200 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6203 /* PREFIX_VEX_0F38BB */
6207 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6210 /* PREFIX_VEX_0F38BC */
6214 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6217 /* PREFIX_VEX_0F38BD */
6221 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6224 /* PREFIX_VEX_0F38BE */
6228 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6231 /* PREFIX_VEX_0F38BF */
6235 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6238 /* PREFIX_VEX_0F38DB */
6242 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6245 /* PREFIX_VEX_0F38DC */
6249 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
6252 /* PREFIX_VEX_0F38DD */
6256 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
6259 /* PREFIX_VEX_0F38DE */
6263 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
6266 /* PREFIX_VEX_0F38DF */
6270 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
6273 /* PREFIX_VEX_0F38F2 */
6275 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6278 /* PREFIX_VEX_0F38F3_REG_1 */
6280 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6283 /* PREFIX_VEX_0F38F3_REG_2 */
6285 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6288 /* PREFIX_VEX_0F38F3_REG_3 */
6290 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6293 /* PREFIX_VEX_0F38F5 */
6295 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6296 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6298 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6301 /* PREFIX_VEX_0F38F6 */
6306 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6309 /* PREFIX_VEX_0F38F7 */
6311 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6312 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6313 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6314 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6317 /* PREFIX_VEX_0F3A00 */
6321 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6324 /* PREFIX_VEX_0F3A01 */
6328 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6331 /* PREFIX_VEX_0F3A02 */
6335 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6338 /* PREFIX_VEX_0F3A04 */
6342 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6345 /* PREFIX_VEX_0F3A05 */
6349 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6352 /* PREFIX_VEX_0F3A06 */
6356 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6359 /* PREFIX_VEX_0F3A08 */
6363 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6366 /* PREFIX_VEX_0F3A09 */
6370 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6373 /* PREFIX_VEX_0F3A0A */
6377 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6380 /* PREFIX_VEX_0F3A0B */
6384 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6387 /* PREFIX_VEX_0F3A0C */
6391 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6394 /* PREFIX_VEX_0F3A0D */
6398 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6401 /* PREFIX_VEX_0F3A0E */
6405 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6408 /* PREFIX_VEX_0F3A0F */
6412 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6415 /* PREFIX_VEX_0F3A14 */
6419 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6422 /* PREFIX_VEX_0F3A15 */
6426 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6429 /* PREFIX_VEX_0F3A16 */
6433 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6436 /* PREFIX_VEX_0F3A17 */
6440 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6443 /* PREFIX_VEX_0F3A18 */
6447 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6450 /* PREFIX_VEX_0F3A19 */
6454 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6457 /* PREFIX_VEX_0F3A1D */
6461 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6464 /* PREFIX_VEX_0F3A20 */
6468 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6471 /* PREFIX_VEX_0F3A21 */
6475 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6478 /* PREFIX_VEX_0F3A22 */
6482 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6485 /* PREFIX_VEX_0F3A30 */
6489 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6492 /* PREFIX_VEX_0F3A31 */
6496 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6499 /* PREFIX_VEX_0F3A32 */
6503 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6506 /* PREFIX_VEX_0F3A33 */
6510 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6513 /* PREFIX_VEX_0F3A38 */
6517 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6520 /* PREFIX_VEX_0F3A39 */
6524 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6527 /* PREFIX_VEX_0F3A40 */
6531 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6534 /* PREFIX_VEX_0F3A41 */
6538 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6541 /* PREFIX_VEX_0F3A42 */
6545 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6548 /* PREFIX_VEX_0F3A44 */
6552 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
6555 /* PREFIX_VEX_0F3A46 */
6559 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6562 /* PREFIX_VEX_0F3A48 */
6566 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6569 /* PREFIX_VEX_0F3A49 */
6573 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6576 /* PREFIX_VEX_0F3A4A */
6580 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6583 /* PREFIX_VEX_0F3A4B */
6587 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6590 /* PREFIX_VEX_0F3A4C */
6594 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6597 /* PREFIX_VEX_0F3A5C */
6601 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6604 /* PREFIX_VEX_0F3A5D */
6608 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6611 /* PREFIX_VEX_0F3A5E */
6615 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6618 /* PREFIX_VEX_0F3A5F */
6622 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6625 /* PREFIX_VEX_0F3A60 */
6629 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6633 /* PREFIX_VEX_0F3A61 */
6637 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6640 /* PREFIX_VEX_0F3A62 */
6644 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6647 /* PREFIX_VEX_0F3A63 */
6651 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6654 /* PREFIX_VEX_0F3A68 */
6658 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6661 /* PREFIX_VEX_0F3A69 */
6665 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6668 /* PREFIX_VEX_0F3A6A */
6672 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6675 /* PREFIX_VEX_0F3A6B */
6679 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6682 /* PREFIX_VEX_0F3A6C */
6686 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6689 /* PREFIX_VEX_0F3A6D */
6693 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6696 /* PREFIX_VEX_0F3A6E */
6700 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6703 /* PREFIX_VEX_0F3A6F */
6707 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6710 /* PREFIX_VEX_0F3A78 */
6714 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6717 /* PREFIX_VEX_0F3A79 */
6721 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6724 /* PREFIX_VEX_0F3A7A */
6728 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6731 /* PREFIX_VEX_0F3A7B */
6735 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6738 /* PREFIX_VEX_0F3A7C */
6742 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6746 /* PREFIX_VEX_0F3A7D */
6750 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6753 /* PREFIX_VEX_0F3A7E */
6757 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6760 /* PREFIX_VEX_0F3A7F */
6764 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6767 /* PREFIX_VEX_0F3ADF */
6771 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6774 /* PREFIX_VEX_0F3AF0 */
6779 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6782 #define NEED_PREFIX_TABLE
6783 #include "i386-dis-evex.h"
6784 #undef NEED_PREFIX_TABLE
6787 static const struct dis386 x86_64_table
[][2] = {
6790 { "pushP", { es
}, 0 },
6795 { "popP", { es
}, 0 },
6800 { "pushP", { cs
}, 0 },
6805 { "pushP", { ss
}, 0 },
6810 { "popP", { ss
}, 0 },
6815 { "pushP", { ds
}, 0 },
6820 { "popP", { ds
}, 0 },
6825 { "daa", { XX
}, 0 },
6830 { "das", { XX
}, 0 },
6835 { "aaa", { XX
}, 0 },
6840 { "aas", { XX
}, 0 },
6845 { "pushaP", { XX
}, 0 },
6850 { "popaP", { XX
}, 0 },
6855 { MOD_TABLE (MOD_62_32BIT
) },
6856 { EVEX_TABLE (EVEX_0F
) },
6861 { "arpl", { Ew
, Gw
}, 0 },
6862 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6867 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6868 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6873 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6874 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6879 { "Jcall{T|}", { Ap
}, 0 },
6884 { MOD_TABLE (MOD_C4_32BIT
) },
6885 { VEX_C4_TABLE (VEX_0F
) },
6890 { MOD_TABLE (MOD_C5_32BIT
) },
6891 { VEX_C5_TABLE (VEX_0F
) },
6896 { "into", { XX
}, 0 },
6901 { "aam", { Ib
}, 0 },
6906 { "aad", { Ib
}, 0 },
6911 { "callP", { Jv
, BND
}, 0 },
6912 { "call@", { Jv
, BND
}, 0 }
6917 { "jmpP", { Jv
, BND
}, 0 },
6918 { "jmp@", { Jv
, BND
}, 0 }
6923 { "Jjmp{T|}", { Ap
}, 0 },
6926 /* X86_64_0F01_REG_0 */
6928 { "sgdt{Q|IQ}", { M
}, 0 },
6929 { "sgdt", { M
}, 0 },
6932 /* X86_64_0F01_REG_1 */
6934 { "sidt{Q|IQ}", { M
}, 0 },
6935 { "sidt", { M
}, 0 },
6938 /* X86_64_0F01_REG_2 */
6940 { "lgdt{Q|Q}", { M
}, 0 },
6941 { "lgdt", { M
}, 0 },
6944 /* X86_64_0F01_REG_3 */
6946 { "lidt{Q|Q}", { M
}, 0 },
6947 { "lidt", { M
}, 0 },
6951 static const struct dis386 three_byte_table
[][256] = {
6953 /* THREE_BYTE_0F38 */
6956 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6957 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6958 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6959 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6960 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6961 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6962 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6963 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6965 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6966 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6967 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6968 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6974 { PREFIX_TABLE (PREFIX_0F3810
) },
6978 { PREFIX_TABLE (PREFIX_0F3814
) },
6979 { PREFIX_TABLE (PREFIX_0F3815
) },
6981 { PREFIX_TABLE (PREFIX_0F3817
) },
6987 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
6988 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
6989 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
6992 { PREFIX_TABLE (PREFIX_0F3820
) },
6993 { PREFIX_TABLE (PREFIX_0F3821
) },
6994 { PREFIX_TABLE (PREFIX_0F3822
) },
6995 { PREFIX_TABLE (PREFIX_0F3823
) },
6996 { PREFIX_TABLE (PREFIX_0F3824
) },
6997 { PREFIX_TABLE (PREFIX_0F3825
) },
7001 { PREFIX_TABLE (PREFIX_0F3828
) },
7002 { PREFIX_TABLE (PREFIX_0F3829
) },
7003 { PREFIX_TABLE (PREFIX_0F382A
) },
7004 { PREFIX_TABLE (PREFIX_0F382B
) },
7010 { PREFIX_TABLE (PREFIX_0F3830
) },
7011 { PREFIX_TABLE (PREFIX_0F3831
) },
7012 { PREFIX_TABLE (PREFIX_0F3832
) },
7013 { PREFIX_TABLE (PREFIX_0F3833
) },
7014 { PREFIX_TABLE (PREFIX_0F3834
) },
7015 { PREFIX_TABLE (PREFIX_0F3835
) },
7017 { PREFIX_TABLE (PREFIX_0F3837
) },
7019 { PREFIX_TABLE (PREFIX_0F3838
) },
7020 { PREFIX_TABLE (PREFIX_0F3839
) },
7021 { PREFIX_TABLE (PREFIX_0F383A
) },
7022 { PREFIX_TABLE (PREFIX_0F383B
) },
7023 { PREFIX_TABLE (PREFIX_0F383C
) },
7024 { PREFIX_TABLE (PREFIX_0F383D
) },
7025 { PREFIX_TABLE (PREFIX_0F383E
) },
7026 { PREFIX_TABLE (PREFIX_0F383F
) },
7028 { PREFIX_TABLE (PREFIX_0F3840
) },
7029 { PREFIX_TABLE (PREFIX_0F3841
) },
7100 { PREFIX_TABLE (PREFIX_0F3880
) },
7101 { PREFIX_TABLE (PREFIX_0F3881
) },
7102 { PREFIX_TABLE (PREFIX_0F3882
) },
7181 { PREFIX_TABLE (PREFIX_0F38C8
) },
7182 { PREFIX_TABLE (PREFIX_0F38C9
) },
7183 { PREFIX_TABLE (PREFIX_0F38CA
) },
7184 { PREFIX_TABLE (PREFIX_0F38CB
) },
7185 { PREFIX_TABLE (PREFIX_0F38CC
) },
7186 { PREFIX_TABLE (PREFIX_0F38CD
) },
7202 { PREFIX_TABLE (PREFIX_0F38DB
) },
7203 { PREFIX_TABLE (PREFIX_0F38DC
) },
7204 { PREFIX_TABLE (PREFIX_0F38DD
) },
7205 { PREFIX_TABLE (PREFIX_0F38DE
) },
7206 { PREFIX_TABLE (PREFIX_0F38DF
) },
7226 { PREFIX_TABLE (PREFIX_0F38F0
) },
7227 { PREFIX_TABLE (PREFIX_0F38F1
) },
7232 { PREFIX_TABLE (PREFIX_0F38F6
) },
7244 /* THREE_BYTE_0F3A */
7256 { PREFIX_TABLE (PREFIX_0F3A08
) },
7257 { PREFIX_TABLE (PREFIX_0F3A09
) },
7258 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7259 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7260 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7261 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7262 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7263 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7269 { PREFIX_TABLE (PREFIX_0F3A14
) },
7270 { PREFIX_TABLE (PREFIX_0F3A15
) },
7271 { PREFIX_TABLE (PREFIX_0F3A16
) },
7272 { PREFIX_TABLE (PREFIX_0F3A17
) },
7283 { PREFIX_TABLE (PREFIX_0F3A20
) },
7284 { PREFIX_TABLE (PREFIX_0F3A21
) },
7285 { PREFIX_TABLE (PREFIX_0F3A22
) },
7319 { PREFIX_TABLE (PREFIX_0F3A40
) },
7320 { PREFIX_TABLE (PREFIX_0F3A41
) },
7321 { PREFIX_TABLE (PREFIX_0F3A42
) },
7323 { PREFIX_TABLE (PREFIX_0F3A44
) },
7355 { PREFIX_TABLE (PREFIX_0F3A60
) },
7356 { PREFIX_TABLE (PREFIX_0F3A61
) },
7357 { PREFIX_TABLE (PREFIX_0F3A62
) },
7358 { PREFIX_TABLE (PREFIX_0F3A63
) },
7476 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7497 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7536 /* THREE_BYTE_0F7A */
7575 { "ptest", { XX
}, PREFIX_OPCODE
},
7612 { "phaddbw", { XM
, EXq
}, PREFIX_OPCODE
},
7613 { "phaddbd", { XM
, EXq
}, PREFIX_OPCODE
},
7614 { "phaddbq", { XM
, EXq
}, PREFIX_OPCODE
},
7617 { "phaddwd", { XM
, EXq
}, PREFIX_OPCODE
},
7618 { "phaddwq", { XM
, EXq
}, PREFIX_OPCODE
},
7623 { "phadddq", { XM
, EXq
}, PREFIX_OPCODE
},
7630 { "phaddubw", { XM
, EXq
}, PREFIX_OPCODE
},
7631 { "phaddubd", { XM
, EXq
}, PREFIX_OPCODE
},
7632 { "phaddubq", { XM
, EXq
}, PREFIX_OPCODE
},
7635 { "phadduwd", { XM
, EXq
}, PREFIX_OPCODE
},
7636 { "phadduwq", { XM
, EXq
}, PREFIX_OPCODE
},
7641 { "phaddudq", { XM
, EXq
}, PREFIX_OPCODE
},
7648 { "phsubbw", { XM
, EXq
}, PREFIX_OPCODE
},
7649 { "phsubbd", { XM
, EXq
}, PREFIX_OPCODE
},
7650 { "phsubbq", { XM
, EXq
}, PREFIX_OPCODE
},
7829 static const struct dis386 xop_table
[][256] = {
7982 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7983 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7984 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7992 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7993 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8000 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8001 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8002 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8010 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8011 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8015 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8016 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8019 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8037 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8049 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
8050 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
8051 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
8052 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
8062 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
8063 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
8064 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
8065 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
8098 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
8099 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
8100 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
8101 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
8125 { REG_TABLE (REG_XOP_TBM_01
) },
8126 { REG_TABLE (REG_XOP_TBM_02
) },
8144 { REG_TABLE (REG_XOP_LWPCB
) },
8268 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8269 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8270 { "vfrczss", { XM
, EXd
}, 0 },
8271 { "vfrczsd", { XM
, EXq
}, 0 },
8286 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8287 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8288 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8289 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8290 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8291 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8292 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8293 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8295 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8296 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8297 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8298 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8341 { "vphaddbw", { XM
, EXxmm
}, 0 },
8342 { "vphaddbd", { XM
, EXxmm
}, 0 },
8343 { "vphaddbq", { XM
, EXxmm
}, 0 },
8346 { "vphaddwd", { XM
, EXxmm
}, 0 },
8347 { "vphaddwq", { XM
, EXxmm
}, 0 },
8352 { "vphadddq", { XM
, EXxmm
}, 0 },
8359 { "vphaddubw", { XM
, EXxmm
}, 0 },
8360 { "vphaddubd", { XM
, EXxmm
}, 0 },
8361 { "vphaddubq", { XM
, EXxmm
}, 0 },
8364 { "vphadduwd", { XM
, EXxmm
}, 0 },
8365 { "vphadduwq", { XM
, EXxmm
}, 0 },
8370 { "vphaddudq", { XM
, EXxmm
}, 0 },
8377 { "vphsubbw", { XM
, EXxmm
}, 0 },
8378 { "vphsubwd", { XM
, EXxmm
}, 0 },
8379 { "vphsubdq", { XM
, EXxmm
}, 0 },
8433 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8435 { REG_TABLE (REG_XOP_LWP
) },
8705 static const struct dis386 vex_table
[][256] = {
8727 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8730 { MOD_TABLE (MOD_VEX_0F13
) },
8731 { VEX_W_TABLE (VEX_W_0F14
) },
8732 { VEX_W_TABLE (VEX_W_0F15
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8734 { MOD_TABLE (MOD_VEX_0F17
) },
8754 { VEX_W_TABLE (VEX_W_0F28
) },
8755 { VEX_W_TABLE (VEX_W_0F29
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8757 { MOD_TABLE (MOD_VEX_0F2B
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8799 { MOD_TABLE (MOD_VEX_0F50
) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8803 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8804 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8805 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8806 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8808 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8809 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8810 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8812 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8813 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8814 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8815 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8817 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8818 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8819 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8820 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8821 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8822 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8823 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8824 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8827 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8828 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8830 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8831 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8832 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8833 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8835 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8836 { REG_TABLE (REG_VEX_0F71
) },
8837 { REG_TABLE (REG_VEX_0F72
) },
8838 { REG_TABLE (REG_VEX_0F73
) },
8839 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8840 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8841 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8842 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8848 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8849 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8850 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8851 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8871 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8872 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8873 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8874 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8880 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8881 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8904 { REG_TABLE (REG_VEX_0FAE
) },
8927 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8929 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8931 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8943 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8945 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8950 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8952 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8953 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8954 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8956 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8957 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8958 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8959 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8961 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8962 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8963 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8964 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8965 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8966 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8967 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8968 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8971 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8972 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8973 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8974 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8975 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8979 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8980 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8981 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8982 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8983 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8984 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8985 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8986 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8988 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8989 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8990 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8991 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8992 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8994 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
9010 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
9013 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
9031 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
9032 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
9033 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
9036 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
9064 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
9159 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
9162 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
9163 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
9164 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
9165 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
9168 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
9169 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
9171 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
9172 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
9173 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
9174 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
9175 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
9176 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
9177 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
9186 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
9187 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
9191 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
9193 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
9194 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
9195 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
9196 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
9204 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
9205 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
9207 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
9208 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
9209 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
9210 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
9211 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
9212 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
9213 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
9214 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
9246 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9247 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9248 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9249 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9250 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9272 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9273 { REG_TABLE (REG_VEX_0F38F3
) },
9275 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9276 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9277 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9291 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9292 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9293 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9295 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9296 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9297 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9300 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9301 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9302 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9303 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9304 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9305 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9306 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9307 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9314 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9315 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9316 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9318 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9319 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9323 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9327 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9328 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9329 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9345 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9346 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9347 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9348 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9354 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9355 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9363 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9364 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9365 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9367 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9369 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9372 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9373 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9374 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9375 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9376 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9394 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9395 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9396 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9397 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9399 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9400 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9401 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9402 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9408 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9409 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9410 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9411 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9412 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9413 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9414 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9415 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9426 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9427 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9428 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9429 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9430 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9431 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9432 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9433 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9541 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9561 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9581 #define NEED_OPCODE_TABLE
9582 #include "i386-dis-evex.h"
9583 #undef NEED_OPCODE_TABLE
9584 static const struct dis386 vex_len_table
[][2] = {
9585 /* VEX_LEN_0F10_P_1 */
9587 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9588 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9591 /* VEX_LEN_0F10_P_3 */
9593 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9594 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9597 /* VEX_LEN_0F11_P_1 */
9599 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9600 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9603 /* VEX_LEN_0F11_P_3 */
9605 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9606 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9609 /* VEX_LEN_0F12_P_0_M_0 */
9611 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9614 /* VEX_LEN_0F12_P_0_M_1 */
9616 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9619 /* VEX_LEN_0F12_P_2 */
9621 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9624 /* VEX_LEN_0F13_M_0 */
9626 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9629 /* VEX_LEN_0F16_P_0_M_0 */
9631 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9634 /* VEX_LEN_0F16_P_0_M_1 */
9636 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9639 /* VEX_LEN_0F16_P_2 */
9641 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9644 /* VEX_LEN_0F17_M_0 */
9646 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9649 /* VEX_LEN_0F2A_P_1 */
9651 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9652 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9655 /* VEX_LEN_0F2A_P_3 */
9657 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9658 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9661 /* VEX_LEN_0F2C_P_1 */
9663 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9664 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9667 /* VEX_LEN_0F2C_P_3 */
9669 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9670 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9673 /* VEX_LEN_0F2D_P_1 */
9675 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9676 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9679 /* VEX_LEN_0F2D_P_3 */
9681 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9682 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9685 /* VEX_LEN_0F2E_P_0 */
9687 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9688 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9691 /* VEX_LEN_0F2E_P_2 */
9693 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9694 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9697 /* VEX_LEN_0F2F_P_0 */
9699 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9700 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9703 /* VEX_LEN_0F2F_P_2 */
9705 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9706 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9709 /* VEX_LEN_0F41_P_0 */
9712 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9714 /* VEX_LEN_0F41_P_2 */
9717 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9719 /* VEX_LEN_0F42_P_0 */
9722 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9724 /* VEX_LEN_0F42_P_2 */
9727 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9729 /* VEX_LEN_0F44_P_0 */
9731 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9733 /* VEX_LEN_0F44_P_2 */
9735 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9737 /* VEX_LEN_0F45_P_0 */
9740 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9742 /* VEX_LEN_0F45_P_2 */
9745 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9747 /* VEX_LEN_0F46_P_0 */
9750 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9752 /* VEX_LEN_0F46_P_2 */
9755 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9757 /* VEX_LEN_0F47_P_0 */
9760 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9762 /* VEX_LEN_0F47_P_2 */
9765 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9767 /* VEX_LEN_0F4A_P_0 */
9770 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9772 /* VEX_LEN_0F4A_P_2 */
9775 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9777 /* VEX_LEN_0F4B_P_0 */
9780 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9782 /* VEX_LEN_0F4B_P_2 */
9785 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9788 /* VEX_LEN_0F51_P_1 */
9790 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9791 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9794 /* VEX_LEN_0F51_P_3 */
9796 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9797 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9800 /* VEX_LEN_0F52_P_1 */
9802 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9803 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9806 /* VEX_LEN_0F53_P_1 */
9808 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9809 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9812 /* VEX_LEN_0F58_P_1 */
9814 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9815 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9818 /* VEX_LEN_0F58_P_3 */
9820 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9821 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9824 /* VEX_LEN_0F59_P_1 */
9826 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9827 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9830 /* VEX_LEN_0F59_P_3 */
9832 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9833 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9836 /* VEX_LEN_0F5A_P_1 */
9838 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9839 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9842 /* VEX_LEN_0F5A_P_3 */
9844 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9845 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9848 /* VEX_LEN_0F5C_P_1 */
9850 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9851 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9854 /* VEX_LEN_0F5C_P_3 */
9856 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9857 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9860 /* VEX_LEN_0F5D_P_1 */
9862 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9863 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9866 /* VEX_LEN_0F5D_P_3 */
9868 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9869 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9872 /* VEX_LEN_0F5E_P_1 */
9874 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9875 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9878 /* VEX_LEN_0F5E_P_3 */
9880 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9881 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9884 /* VEX_LEN_0F5F_P_1 */
9886 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9887 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9890 /* VEX_LEN_0F5F_P_3 */
9892 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9893 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9896 /* VEX_LEN_0F6E_P_2 */
9898 { "vmovK", { XMScalar
, Edq
}, 0 },
9899 { "vmovK", { XMScalar
, Edq
}, 0 },
9902 /* VEX_LEN_0F7E_P_1 */
9904 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9905 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9908 /* VEX_LEN_0F7E_P_2 */
9910 { "vmovK", { Edq
, XMScalar
}, 0 },
9911 { "vmovK", { Edq
, XMScalar
}, 0 },
9914 /* VEX_LEN_0F90_P_0 */
9916 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9919 /* VEX_LEN_0F90_P_2 */
9921 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9924 /* VEX_LEN_0F91_P_0 */
9926 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9929 /* VEX_LEN_0F91_P_2 */
9931 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9934 /* VEX_LEN_0F92_P_0 */
9936 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9939 /* VEX_LEN_0F92_P_2 */
9941 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9944 /* VEX_LEN_0F92_P_3 */
9946 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9949 /* VEX_LEN_0F93_P_0 */
9951 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9954 /* VEX_LEN_0F93_P_2 */
9956 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9959 /* VEX_LEN_0F93_P_3 */
9961 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9964 /* VEX_LEN_0F98_P_0 */
9966 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9969 /* VEX_LEN_0F98_P_2 */
9971 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9974 /* VEX_LEN_0F99_P_0 */
9976 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9979 /* VEX_LEN_0F99_P_2 */
9981 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9984 /* VEX_LEN_0FAE_R_2_M_0 */
9986 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
9989 /* VEX_LEN_0FAE_R_3_M_0 */
9991 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
9994 /* VEX_LEN_0FC2_P_1 */
9996 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9997 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
10000 /* VEX_LEN_0FC2_P_3 */
10002 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
10003 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
10006 /* VEX_LEN_0FC4_P_2 */
10008 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
10011 /* VEX_LEN_0FC5_P_2 */
10013 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
10016 /* VEX_LEN_0FD6_P_2 */
10018 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
10019 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
10022 /* VEX_LEN_0FF7_P_2 */
10024 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
10027 /* VEX_LEN_0F3816_P_2 */
10030 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
10033 /* VEX_LEN_0F3819_P_2 */
10036 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
10039 /* VEX_LEN_0F381A_P_2_M_0 */
10042 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
10045 /* VEX_LEN_0F3836_P_2 */
10048 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
10051 /* VEX_LEN_0F3841_P_2 */
10053 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
10056 /* VEX_LEN_0F385A_P_2_M_0 */
10059 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
10062 /* VEX_LEN_0F38DB_P_2 */
10064 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
10067 /* VEX_LEN_0F38DC_P_2 */
10069 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
10072 /* VEX_LEN_0F38DD_P_2 */
10074 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
10077 /* VEX_LEN_0F38DE_P_2 */
10079 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
10082 /* VEX_LEN_0F38DF_P_2 */
10084 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
10087 /* VEX_LEN_0F38F2_P_0 */
10089 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
10092 /* VEX_LEN_0F38F3_R_1_P_0 */
10094 { "blsrS", { VexGdq
, Edq
}, 0 },
10097 /* VEX_LEN_0F38F3_R_2_P_0 */
10099 { "blsmskS", { VexGdq
, Edq
}, 0 },
10102 /* VEX_LEN_0F38F3_R_3_P_0 */
10104 { "blsiS", { VexGdq
, Edq
}, 0 },
10107 /* VEX_LEN_0F38F5_P_0 */
10109 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
10112 /* VEX_LEN_0F38F5_P_1 */
10114 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
10117 /* VEX_LEN_0F38F5_P_3 */
10119 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
10122 /* VEX_LEN_0F38F6_P_3 */
10124 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
10127 /* VEX_LEN_0F38F7_P_0 */
10129 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
10132 /* VEX_LEN_0F38F7_P_1 */
10134 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
10137 /* VEX_LEN_0F38F7_P_2 */
10139 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
10142 /* VEX_LEN_0F38F7_P_3 */
10144 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
10147 /* VEX_LEN_0F3A00_P_2 */
10150 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
10153 /* VEX_LEN_0F3A01_P_2 */
10156 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
10159 /* VEX_LEN_0F3A06_P_2 */
10162 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
10165 /* VEX_LEN_0F3A0A_P_2 */
10167 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10168 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10171 /* VEX_LEN_0F3A0B_P_2 */
10173 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10174 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10177 /* VEX_LEN_0F3A14_P_2 */
10179 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
10182 /* VEX_LEN_0F3A15_P_2 */
10184 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
10187 /* VEX_LEN_0F3A16_P_2 */
10189 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
10192 /* VEX_LEN_0F3A17_P_2 */
10194 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
10197 /* VEX_LEN_0F3A18_P_2 */
10200 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
10203 /* VEX_LEN_0F3A19_P_2 */
10206 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
10209 /* VEX_LEN_0F3A20_P_2 */
10211 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
10214 /* VEX_LEN_0F3A21_P_2 */
10216 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
10219 /* VEX_LEN_0F3A22_P_2 */
10221 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
10224 /* VEX_LEN_0F3A30_P_2 */
10226 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
10229 /* VEX_LEN_0F3A31_P_2 */
10231 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
10234 /* VEX_LEN_0F3A32_P_2 */
10236 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
10239 /* VEX_LEN_0F3A33_P_2 */
10241 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
10244 /* VEX_LEN_0F3A38_P_2 */
10247 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
10250 /* VEX_LEN_0F3A39_P_2 */
10253 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
10256 /* VEX_LEN_0F3A41_P_2 */
10258 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
10261 /* VEX_LEN_0F3A44_P_2 */
10263 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
10266 /* VEX_LEN_0F3A46_P_2 */
10269 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
10272 /* VEX_LEN_0F3A60_P_2 */
10274 { VEX_W_TABLE (VEX_W_0F3A60_P_2
) },
10277 /* VEX_LEN_0F3A61_P_2 */
10279 { VEX_W_TABLE (VEX_W_0F3A61_P_2
) },
10282 /* VEX_LEN_0F3A62_P_2 */
10284 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
10287 /* VEX_LEN_0F3A63_P_2 */
10289 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
10292 /* VEX_LEN_0F3A6A_P_2 */
10294 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10297 /* VEX_LEN_0F3A6B_P_2 */
10299 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10302 /* VEX_LEN_0F3A6E_P_2 */
10304 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10307 /* VEX_LEN_0F3A6F_P_2 */
10309 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10312 /* VEX_LEN_0F3A7A_P_2 */
10314 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10317 /* VEX_LEN_0F3A7B_P_2 */
10319 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10322 /* VEX_LEN_0F3A7E_P_2 */
10324 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10327 /* VEX_LEN_0F3A7F_P_2 */
10329 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10332 /* VEX_LEN_0F3ADF_P_2 */
10334 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
10337 /* VEX_LEN_0F3AF0_P_3 */
10339 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
10342 /* VEX_LEN_0FXOP_08_CC */
10344 { "vpcomb", { XM
, Vex128
, EXx
, Ib
}, 0 },
10347 /* VEX_LEN_0FXOP_08_CD */
10349 { "vpcomw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10352 /* VEX_LEN_0FXOP_08_CE */
10354 { "vpcomd", { XM
, Vex128
, EXx
, Ib
}, 0 },
10357 /* VEX_LEN_0FXOP_08_CF */
10359 { "vpcomq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10362 /* VEX_LEN_0FXOP_08_EC */
10364 { "vpcomub", { XM
, Vex128
, EXx
, Ib
}, 0 },
10367 /* VEX_LEN_0FXOP_08_ED */
10369 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10372 /* VEX_LEN_0FXOP_08_EE */
10374 { "vpcomud", { XM
, Vex128
, EXx
, Ib
}, 0 },
10377 /* VEX_LEN_0FXOP_08_EF */
10379 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10382 /* VEX_LEN_0FXOP_09_80 */
10384 { "vfrczps", { XM
, EXxmm
}, 0 },
10385 { "vfrczps", { XM
, EXymmq
}, 0 },
10388 /* VEX_LEN_0FXOP_09_81 */
10390 { "vfrczpd", { XM
, EXxmm
}, 0 },
10391 { "vfrczpd", { XM
, EXymmq
}, 0 },
10395 static const struct dis386 vex_w_table
[][2] = {
10397 /* VEX_W_0F10_P_0 */
10398 { "vmovups", { XM
, EXx
}, 0 },
10401 /* VEX_W_0F10_P_1 */
10402 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
10405 /* VEX_W_0F10_P_2 */
10406 { "vmovupd", { XM
, EXx
}, 0 },
10409 /* VEX_W_0F10_P_3 */
10410 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
10413 /* VEX_W_0F11_P_0 */
10414 { "vmovups", { EXxS
, XM
}, 0 },
10417 /* VEX_W_0F11_P_1 */
10418 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
10421 /* VEX_W_0F11_P_2 */
10422 { "vmovupd", { EXxS
, XM
}, 0 },
10425 /* VEX_W_0F11_P_3 */
10426 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
10429 /* VEX_W_0F12_P_0_M_0 */
10430 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
10433 /* VEX_W_0F12_P_0_M_1 */
10434 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
10437 /* VEX_W_0F12_P_1 */
10438 { "vmovsldup", { XM
, EXx
}, 0 },
10441 /* VEX_W_0F12_P_2 */
10442 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
10445 /* VEX_W_0F12_P_3 */
10446 { "vmovddup", { XM
, EXymmq
}, 0 },
10449 /* VEX_W_0F13_M_0 */
10450 { "vmovlpX", { EXq
, XM
}, 0 },
10454 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
10458 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
10461 /* VEX_W_0F16_P_0_M_0 */
10462 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
10465 /* VEX_W_0F16_P_0_M_1 */
10466 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
10469 /* VEX_W_0F16_P_1 */
10470 { "vmovshdup", { XM
, EXx
}, 0 },
10473 /* VEX_W_0F16_P_2 */
10474 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
10477 /* VEX_W_0F17_M_0 */
10478 { "vmovhpX", { EXq
, XM
}, 0 },
10482 { "vmovapX", { XM
, EXx
}, 0 },
10486 { "vmovapX", { EXxS
, XM
}, 0 },
10489 /* VEX_W_0F2B_M_0 */
10490 { "vmovntpX", { Mx
, XM
}, 0 },
10493 /* VEX_W_0F2E_P_0 */
10494 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
10497 /* VEX_W_0F2E_P_2 */
10498 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
10501 /* VEX_W_0F2F_P_0 */
10502 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
10505 /* VEX_W_0F2F_P_2 */
10506 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
10509 /* VEX_W_0F41_P_0_LEN_1 */
10510 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
10511 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
10514 /* VEX_W_0F41_P_2_LEN_1 */
10515 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
10516 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
10519 /* VEX_W_0F42_P_0_LEN_1 */
10520 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
10521 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
10524 /* VEX_W_0F42_P_2_LEN_1 */
10525 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
10526 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
10529 /* VEX_W_0F44_P_0_LEN_0 */
10530 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
10531 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
10534 /* VEX_W_0F44_P_2_LEN_0 */
10535 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
10536 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
10539 /* VEX_W_0F45_P_0_LEN_1 */
10540 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
10541 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
10544 /* VEX_W_0F45_P_2_LEN_1 */
10545 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
10546 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
10549 /* VEX_W_0F46_P_0_LEN_1 */
10550 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
10551 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
10554 /* VEX_W_0F46_P_2_LEN_1 */
10555 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
10556 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
10559 /* VEX_W_0F47_P_0_LEN_1 */
10560 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
10561 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
10564 /* VEX_W_0F47_P_2_LEN_1 */
10565 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
10566 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
10569 /* VEX_W_0F4A_P_0_LEN_1 */
10570 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
10571 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
10574 /* VEX_W_0F4A_P_2_LEN_1 */
10575 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
10576 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
10579 /* VEX_W_0F4B_P_0_LEN_1 */
10580 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
10581 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
10584 /* VEX_W_0F4B_P_2_LEN_1 */
10585 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
10588 /* VEX_W_0F50_M_0 */
10589 { "vmovmskpX", { Gdq
, XS
}, 0 },
10592 /* VEX_W_0F51_P_0 */
10593 { "vsqrtps", { XM
, EXx
}, 0 },
10596 /* VEX_W_0F51_P_1 */
10597 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10600 /* VEX_W_0F51_P_2 */
10601 { "vsqrtpd", { XM
, EXx
}, 0 },
10604 /* VEX_W_0F51_P_3 */
10605 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10608 /* VEX_W_0F52_P_0 */
10609 { "vrsqrtps", { XM
, EXx
}, 0 },
10612 /* VEX_W_0F52_P_1 */
10613 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10616 /* VEX_W_0F53_P_0 */
10617 { "vrcpps", { XM
, EXx
}, 0 },
10620 /* VEX_W_0F53_P_1 */
10621 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10624 /* VEX_W_0F58_P_0 */
10625 { "vaddps", { XM
, Vex
, EXx
}, 0 },
10628 /* VEX_W_0F58_P_1 */
10629 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10632 /* VEX_W_0F58_P_2 */
10633 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
10636 /* VEX_W_0F58_P_3 */
10637 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10640 /* VEX_W_0F59_P_0 */
10641 { "vmulps", { XM
, Vex
, EXx
}, 0 },
10644 /* VEX_W_0F59_P_1 */
10645 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10648 /* VEX_W_0F59_P_2 */
10649 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
10652 /* VEX_W_0F59_P_3 */
10653 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10656 /* VEX_W_0F5A_P_0 */
10657 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
10660 /* VEX_W_0F5A_P_1 */
10661 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10664 /* VEX_W_0F5A_P_3 */
10665 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10668 /* VEX_W_0F5B_P_0 */
10669 { "vcvtdq2ps", { XM
, EXx
}, 0 },
10672 /* VEX_W_0F5B_P_1 */
10673 { "vcvttps2dq", { XM
, EXx
}, 0 },
10676 /* VEX_W_0F5B_P_2 */
10677 { "vcvtps2dq", { XM
, EXx
}, 0 },
10680 /* VEX_W_0F5C_P_0 */
10681 { "vsubps", { XM
, Vex
, EXx
}, 0 },
10684 /* VEX_W_0F5C_P_1 */
10685 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10688 /* VEX_W_0F5C_P_2 */
10689 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
10692 /* VEX_W_0F5C_P_3 */
10693 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10696 /* VEX_W_0F5D_P_0 */
10697 { "vminps", { XM
, Vex
, EXx
}, 0 },
10700 /* VEX_W_0F5D_P_1 */
10701 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10704 /* VEX_W_0F5D_P_2 */
10705 { "vminpd", { XM
, Vex
, EXx
}, 0 },
10708 /* VEX_W_0F5D_P_3 */
10709 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10712 /* VEX_W_0F5E_P_0 */
10713 { "vdivps", { XM
, Vex
, EXx
}, 0 },
10716 /* VEX_W_0F5E_P_1 */
10717 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10720 /* VEX_W_0F5E_P_2 */
10721 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
10724 /* VEX_W_0F5E_P_3 */
10725 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10728 /* VEX_W_0F5F_P_0 */
10729 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
10732 /* VEX_W_0F5F_P_1 */
10733 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10736 /* VEX_W_0F5F_P_2 */
10737 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
10740 /* VEX_W_0F5F_P_3 */
10741 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10744 /* VEX_W_0F60_P_2 */
10745 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
10748 /* VEX_W_0F61_P_2 */
10749 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
10752 /* VEX_W_0F62_P_2 */
10753 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
10756 /* VEX_W_0F63_P_2 */
10757 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
10760 /* VEX_W_0F64_P_2 */
10761 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
10764 /* VEX_W_0F65_P_2 */
10765 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
10768 /* VEX_W_0F66_P_2 */
10769 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
10772 /* VEX_W_0F67_P_2 */
10773 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
10776 /* VEX_W_0F68_P_2 */
10777 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
10780 /* VEX_W_0F69_P_2 */
10781 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
10784 /* VEX_W_0F6A_P_2 */
10785 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
10788 /* VEX_W_0F6B_P_2 */
10789 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
10792 /* VEX_W_0F6C_P_2 */
10793 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
10796 /* VEX_W_0F6D_P_2 */
10797 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
10800 /* VEX_W_0F6F_P_1 */
10801 { "vmovdqu", { XM
, EXx
}, 0 },
10804 /* VEX_W_0F6F_P_2 */
10805 { "vmovdqa", { XM
, EXx
}, 0 },
10808 /* VEX_W_0F70_P_1 */
10809 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
10812 /* VEX_W_0F70_P_2 */
10813 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
10816 /* VEX_W_0F70_P_3 */
10817 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
10820 /* VEX_W_0F71_R_2_P_2 */
10821 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
10824 /* VEX_W_0F71_R_4_P_2 */
10825 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
10828 /* VEX_W_0F71_R_6_P_2 */
10829 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
10832 /* VEX_W_0F72_R_2_P_2 */
10833 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
10836 /* VEX_W_0F72_R_4_P_2 */
10837 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
10840 /* VEX_W_0F72_R_6_P_2 */
10841 { "vpslld", { Vex
, XS
, Ib
}, 0 },
10844 /* VEX_W_0F73_R_2_P_2 */
10845 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
10848 /* VEX_W_0F73_R_3_P_2 */
10849 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
10852 /* VEX_W_0F73_R_6_P_2 */
10853 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
10856 /* VEX_W_0F73_R_7_P_2 */
10857 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
10860 /* VEX_W_0F74_P_2 */
10861 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
10864 /* VEX_W_0F75_P_2 */
10865 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
10868 /* VEX_W_0F76_P_2 */
10869 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
10872 /* VEX_W_0F77_P_0 */
10873 { "", { VZERO
}, 0 },
10876 /* VEX_W_0F7C_P_2 */
10877 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
10880 /* VEX_W_0F7C_P_3 */
10881 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
10884 /* VEX_W_0F7D_P_2 */
10885 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
10888 /* VEX_W_0F7D_P_3 */
10889 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
10892 /* VEX_W_0F7E_P_1 */
10893 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
10896 /* VEX_W_0F7F_P_1 */
10897 { "vmovdqu", { EXxS
, XM
}, 0 },
10900 /* VEX_W_0F7F_P_2 */
10901 { "vmovdqa", { EXxS
, XM
}, 0 },
10904 /* VEX_W_0F90_P_0_LEN_0 */
10905 { "kmovw", { MaskG
, MaskE
}, 0 },
10906 { "kmovq", { MaskG
, MaskE
}, 0 },
10909 /* VEX_W_0F90_P_2_LEN_0 */
10910 { "kmovb", { MaskG
, MaskBDE
}, 0 },
10911 { "kmovd", { MaskG
, MaskBDE
}, 0 },
10914 /* VEX_W_0F91_P_0_LEN_0 */
10915 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
10916 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
10919 /* VEX_W_0F91_P_2_LEN_0 */
10920 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
10921 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
10924 /* VEX_W_0F92_P_0_LEN_0 */
10925 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10928 /* VEX_W_0F92_P_2_LEN_0 */
10929 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10932 /* VEX_W_0F92_P_3_LEN_0 */
10933 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0
) },
10934 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0
) },
10937 /* VEX_W_0F93_P_0_LEN_0 */
10938 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10941 /* VEX_W_0F93_P_2_LEN_0 */
10942 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10945 /* VEX_W_0F93_P_3_LEN_0 */
10946 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0
) },
10947 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0
) },
10950 /* VEX_W_0F98_P_0_LEN_0 */
10951 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10952 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10955 /* VEX_W_0F98_P_2_LEN_0 */
10956 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10957 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10960 /* VEX_W_0F99_P_0_LEN_0 */
10961 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10962 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10965 /* VEX_W_0F99_P_2_LEN_0 */
10966 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10967 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10970 /* VEX_W_0FAE_R_2_M_0 */
10971 { "vldmxcsr", { Md
}, 0 },
10974 /* VEX_W_0FAE_R_3_M_0 */
10975 { "vstmxcsr", { Md
}, 0 },
10978 /* VEX_W_0FC2_P_0 */
10979 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
10982 /* VEX_W_0FC2_P_1 */
10983 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
10986 /* VEX_W_0FC2_P_2 */
10987 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
10990 /* VEX_W_0FC2_P_3 */
10991 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
10994 /* VEX_W_0FC4_P_2 */
10995 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
10998 /* VEX_W_0FC5_P_2 */
10999 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
11002 /* VEX_W_0FD0_P_2 */
11003 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
11006 /* VEX_W_0FD0_P_3 */
11007 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
11010 /* VEX_W_0FD1_P_2 */
11011 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
11014 /* VEX_W_0FD2_P_2 */
11015 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
11018 /* VEX_W_0FD3_P_2 */
11019 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
11022 /* VEX_W_0FD4_P_2 */
11023 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
11026 /* VEX_W_0FD5_P_2 */
11027 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
11030 /* VEX_W_0FD6_P_2 */
11031 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
11034 /* VEX_W_0FD7_P_2_M_1 */
11035 { "vpmovmskb", { Gdq
, XS
}, 0 },
11038 /* VEX_W_0FD8_P_2 */
11039 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
11042 /* VEX_W_0FD9_P_2 */
11043 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
11046 /* VEX_W_0FDA_P_2 */
11047 { "vpminub", { XM
, Vex
, EXx
}, 0 },
11050 /* VEX_W_0FDB_P_2 */
11051 { "vpand", { XM
, Vex
, EXx
}, 0 },
11054 /* VEX_W_0FDC_P_2 */
11055 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
11058 /* VEX_W_0FDD_P_2 */
11059 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
11062 /* VEX_W_0FDE_P_2 */
11063 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
11066 /* VEX_W_0FDF_P_2 */
11067 { "vpandn", { XM
, Vex
, EXx
}, 0 },
11070 /* VEX_W_0FE0_P_2 */
11071 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
11074 /* VEX_W_0FE1_P_2 */
11075 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
11078 /* VEX_W_0FE2_P_2 */
11079 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
11082 /* VEX_W_0FE3_P_2 */
11083 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
11086 /* VEX_W_0FE4_P_2 */
11087 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
11090 /* VEX_W_0FE5_P_2 */
11091 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
11094 /* VEX_W_0FE6_P_1 */
11095 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
11098 /* VEX_W_0FE6_P_2 */
11099 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
11102 /* VEX_W_0FE6_P_3 */
11103 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
11106 /* VEX_W_0FE7_P_2_M_0 */
11107 { "vmovntdq", { Mx
, XM
}, 0 },
11110 /* VEX_W_0FE8_P_2 */
11111 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
11114 /* VEX_W_0FE9_P_2 */
11115 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
11118 /* VEX_W_0FEA_P_2 */
11119 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
11122 /* VEX_W_0FEB_P_2 */
11123 { "vpor", { XM
, Vex
, EXx
}, 0 },
11126 /* VEX_W_0FEC_P_2 */
11127 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
11130 /* VEX_W_0FED_P_2 */
11131 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
11134 /* VEX_W_0FEE_P_2 */
11135 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
11138 /* VEX_W_0FEF_P_2 */
11139 { "vpxor", { XM
, Vex
, EXx
}, 0 },
11142 /* VEX_W_0FF0_P_3_M_0 */
11143 { "vlddqu", { XM
, M
}, 0 },
11146 /* VEX_W_0FF1_P_2 */
11147 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
11150 /* VEX_W_0FF2_P_2 */
11151 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
11154 /* VEX_W_0FF3_P_2 */
11155 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
11158 /* VEX_W_0FF4_P_2 */
11159 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
11162 /* VEX_W_0FF5_P_2 */
11163 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
11166 /* VEX_W_0FF6_P_2 */
11167 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
11170 /* VEX_W_0FF7_P_2 */
11171 { "vmaskmovdqu", { XM
, XS
}, 0 },
11174 /* VEX_W_0FF8_P_2 */
11175 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
11178 /* VEX_W_0FF9_P_2 */
11179 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
11182 /* VEX_W_0FFA_P_2 */
11183 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
11186 /* VEX_W_0FFB_P_2 */
11187 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
11190 /* VEX_W_0FFC_P_2 */
11191 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
11194 /* VEX_W_0FFD_P_2 */
11195 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
11198 /* VEX_W_0FFE_P_2 */
11199 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
11202 /* VEX_W_0F3800_P_2 */
11203 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
11206 /* VEX_W_0F3801_P_2 */
11207 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
11210 /* VEX_W_0F3802_P_2 */
11211 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
11214 /* VEX_W_0F3803_P_2 */
11215 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
11218 /* VEX_W_0F3804_P_2 */
11219 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
11222 /* VEX_W_0F3805_P_2 */
11223 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
11226 /* VEX_W_0F3806_P_2 */
11227 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
11230 /* VEX_W_0F3807_P_2 */
11231 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
11234 /* VEX_W_0F3808_P_2 */
11235 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
11238 /* VEX_W_0F3809_P_2 */
11239 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
11242 /* VEX_W_0F380A_P_2 */
11243 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
11246 /* VEX_W_0F380B_P_2 */
11247 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
11250 /* VEX_W_0F380C_P_2 */
11251 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
11254 /* VEX_W_0F380D_P_2 */
11255 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
11258 /* VEX_W_0F380E_P_2 */
11259 { "vtestps", { XM
, EXx
}, 0 },
11262 /* VEX_W_0F380F_P_2 */
11263 { "vtestpd", { XM
, EXx
}, 0 },
11266 /* VEX_W_0F3816_P_2 */
11267 { "vpermps", { XM
, Vex
, EXx
}, 0 },
11270 /* VEX_W_0F3817_P_2 */
11271 { "vptest", { XM
, EXx
}, 0 },
11274 /* VEX_W_0F3818_P_2 */
11275 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
11278 /* VEX_W_0F3819_P_2 */
11279 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
11282 /* VEX_W_0F381A_P_2_M_0 */
11283 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
11286 /* VEX_W_0F381C_P_2 */
11287 { "vpabsb", { XM
, EXx
}, 0 },
11290 /* VEX_W_0F381D_P_2 */
11291 { "vpabsw", { XM
, EXx
}, 0 },
11294 /* VEX_W_0F381E_P_2 */
11295 { "vpabsd", { XM
, EXx
}, 0 },
11298 /* VEX_W_0F3820_P_2 */
11299 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
11302 /* VEX_W_0F3821_P_2 */
11303 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
11306 /* VEX_W_0F3822_P_2 */
11307 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
11310 /* VEX_W_0F3823_P_2 */
11311 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
11314 /* VEX_W_0F3824_P_2 */
11315 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
11318 /* VEX_W_0F3825_P_2 */
11319 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
11322 /* VEX_W_0F3828_P_2 */
11323 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
11326 /* VEX_W_0F3829_P_2 */
11327 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
11330 /* VEX_W_0F382A_P_2_M_0 */
11331 { "vmovntdqa", { XM
, Mx
}, 0 },
11334 /* VEX_W_0F382B_P_2 */
11335 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
11338 /* VEX_W_0F382C_P_2_M_0 */
11339 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
11342 /* VEX_W_0F382D_P_2_M_0 */
11343 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
11346 /* VEX_W_0F382E_P_2_M_0 */
11347 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
11350 /* VEX_W_0F382F_P_2_M_0 */
11351 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
11354 /* VEX_W_0F3830_P_2 */
11355 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
11358 /* VEX_W_0F3831_P_2 */
11359 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
11362 /* VEX_W_0F3832_P_2 */
11363 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
11366 /* VEX_W_0F3833_P_2 */
11367 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
11370 /* VEX_W_0F3834_P_2 */
11371 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
11374 /* VEX_W_0F3835_P_2 */
11375 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
11378 /* VEX_W_0F3836_P_2 */
11379 { "vpermd", { XM
, Vex
, EXx
}, 0 },
11382 /* VEX_W_0F3837_P_2 */
11383 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
11386 /* VEX_W_0F3838_P_2 */
11387 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
11390 /* VEX_W_0F3839_P_2 */
11391 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
11394 /* VEX_W_0F383A_P_2 */
11395 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
11398 /* VEX_W_0F383B_P_2 */
11399 { "vpminud", { XM
, Vex
, EXx
}, 0 },
11402 /* VEX_W_0F383C_P_2 */
11403 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
11406 /* VEX_W_0F383D_P_2 */
11407 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
11410 /* VEX_W_0F383E_P_2 */
11411 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
11414 /* VEX_W_0F383F_P_2 */
11415 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
11418 /* VEX_W_0F3840_P_2 */
11419 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
11422 /* VEX_W_0F3841_P_2 */
11423 { "vphminposuw", { XM
, EXx
}, 0 },
11426 /* VEX_W_0F3846_P_2 */
11427 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
11430 /* VEX_W_0F3858_P_2 */
11431 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
11434 /* VEX_W_0F3859_P_2 */
11435 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
11438 /* VEX_W_0F385A_P_2_M_0 */
11439 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
11442 /* VEX_W_0F3878_P_2 */
11443 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
11446 /* VEX_W_0F3879_P_2 */
11447 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
11450 /* VEX_W_0F38DB_P_2 */
11451 { "vaesimc", { XM
, EXx
}, 0 },
11454 /* VEX_W_0F38DC_P_2 */
11455 { "vaesenc", { XM
, Vex128
, EXx
}, 0 },
11458 /* VEX_W_0F38DD_P_2 */
11459 { "vaesenclast", { XM
, Vex128
, EXx
}, 0 },
11462 /* VEX_W_0F38DE_P_2 */
11463 { "vaesdec", { XM
, Vex128
, EXx
}, 0 },
11466 /* VEX_W_0F38DF_P_2 */
11467 { "vaesdeclast", { XM
, Vex128
, EXx
}, 0 },
11470 /* VEX_W_0F3A00_P_2 */
11472 { "vpermq", { XM
, EXx
, Ib
}, 0 },
11475 /* VEX_W_0F3A01_P_2 */
11477 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
11480 /* VEX_W_0F3A02_P_2 */
11481 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
11484 /* VEX_W_0F3A04_P_2 */
11485 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
11488 /* VEX_W_0F3A05_P_2 */
11489 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
11492 /* VEX_W_0F3A06_P_2 */
11493 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11496 /* VEX_W_0F3A08_P_2 */
11497 { "vroundps", { XM
, EXx
, Ib
}, 0 },
11500 /* VEX_W_0F3A09_P_2 */
11501 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
11504 /* VEX_W_0F3A0A_P_2 */
11505 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
11508 /* VEX_W_0F3A0B_P_2 */
11509 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
11512 /* VEX_W_0F3A0C_P_2 */
11513 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
11516 /* VEX_W_0F3A0D_P_2 */
11517 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
11520 /* VEX_W_0F3A0E_P_2 */
11521 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
11524 /* VEX_W_0F3A0F_P_2 */
11525 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
11528 /* VEX_W_0F3A14_P_2 */
11529 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
11532 /* VEX_W_0F3A15_P_2 */
11533 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
11536 /* VEX_W_0F3A18_P_2 */
11537 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11540 /* VEX_W_0F3A19_P_2 */
11541 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
11544 /* VEX_W_0F3A20_P_2 */
11545 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
11548 /* VEX_W_0F3A21_P_2 */
11549 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
11552 /* VEX_W_0F3A30_P_2_LEN_0 */
11553 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
11554 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
11557 /* VEX_W_0F3A31_P_2_LEN_0 */
11558 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
11559 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
11562 /* VEX_W_0F3A32_P_2_LEN_0 */
11563 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
11564 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
11567 /* VEX_W_0F3A33_P_2_LEN_0 */
11568 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
11569 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
11572 /* VEX_W_0F3A38_P_2 */
11573 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11576 /* VEX_W_0F3A39_P_2 */
11577 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
11580 /* VEX_W_0F3A40_P_2 */
11581 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
11584 /* VEX_W_0F3A41_P_2 */
11585 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
11588 /* VEX_W_0F3A42_P_2 */
11589 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
11592 /* VEX_W_0F3A44_P_2 */
11593 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
}, 0 },
11596 /* VEX_W_0F3A46_P_2 */
11597 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11600 /* VEX_W_0F3A48_P_2 */
11601 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11602 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11605 /* VEX_W_0F3A49_P_2 */
11606 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11607 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11610 /* VEX_W_0F3A4A_P_2 */
11611 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11614 /* VEX_W_0F3A4B_P_2 */
11615 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11618 /* VEX_W_0F3A4C_P_2 */
11619 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11622 /* VEX_W_0F3A60_P_2 */
11623 { "vpcmpestrm", { XM
, EXx
, Ib
}, 0 },
11626 /* VEX_W_0F3A61_P_2 */
11627 { "vpcmpestri", { XM
, EXx
, Ib
}, 0 },
11630 /* VEX_W_0F3A62_P_2 */
11631 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
11634 /* VEX_W_0F3A63_P_2 */
11635 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
11638 /* VEX_W_0F3ADF_P_2 */
11639 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
11641 #define NEED_VEX_W_TABLE
11642 #include "i386-dis-evex.h"
11643 #undef NEED_VEX_W_TABLE
11646 static const struct dis386 mod_table
[][2] = {
11649 { "leaS", { Gv
, M
}, 0 },
11654 { RM_TABLE (RM_C6_REG_7
) },
11659 { RM_TABLE (RM_C7_REG_7
) },
11663 { "Jcall^", { indirEp
}, 0 },
11667 { "Jjmp^", { indirEp
}, 0 },
11670 /* MOD_0F01_REG_0 */
11671 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11672 { RM_TABLE (RM_0F01_REG_0
) },
11675 /* MOD_0F01_REG_1 */
11676 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11677 { RM_TABLE (RM_0F01_REG_1
) },
11680 /* MOD_0F01_REG_2 */
11681 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11682 { RM_TABLE (RM_0F01_REG_2
) },
11685 /* MOD_0F01_REG_3 */
11686 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11687 { RM_TABLE (RM_0F01_REG_3
) },
11690 /* MOD_0F01_REG_5 */
11692 { RM_TABLE (RM_0F01_REG_5
) },
11695 /* MOD_0F01_REG_7 */
11696 { "invlpg", { Mb
}, 0 },
11697 { RM_TABLE (RM_0F01_REG_7
) },
11700 /* MOD_0F12_PREFIX_0 */
11701 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
11702 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
11706 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
11709 /* MOD_0F16_PREFIX_0 */
11710 { "movhps", { XM
, EXq
}, 0 },
11711 { "movlhps", { XM
, EXq
}, 0 },
11715 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
11718 /* MOD_0F18_REG_0 */
11719 { "prefetchnta", { Mb
}, 0 },
11722 /* MOD_0F18_REG_1 */
11723 { "prefetcht0", { Mb
}, 0 },
11726 /* MOD_0F18_REG_2 */
11727 { "prefetcht1", { Mb
}, 0 },
11730 /* MOD_0F18_REG_3 */
11731 { "prefetcht2", { Mb
}, 0 },
11734 /* MOD_0F18_REG_4 */
11735 { "nop/reserved", { Mb
}, 0 },
11738 /* MOD_0F18_REG_5 */
11739 { "nop/reserved", { Mb
}, 0 },
11742 /* MOD_0F18_REG_6 */
11743 { "nop/reserved", { Mb
}, 0 },
11746 /* MOD_0F18_REG_7 */
11747 { "nop/reserved", { Mb
}, 0 },
11750 /* MOD_0F1A_PREFIX_0 */
11751 { "bndldx", { Gbnd
, Ev_bnd
}, 0 },
11752 { "nopQ", { Ev
}, 0 },
11755 /* MOD_0F1B_PREFIX_0 */
11756 { "bndstx", { Ev_bnd
, Gbnd
}, 0 },
11757 { "nopQ", { Ev
}, 0 },
11760 /* MOD_0F1B_PREFIX_1 */
11761 { "bndmk", { Gbnd
, Ev_bnd
}, 0 },
11762 { "nopQ", { Ev
}, 0 },
11767 { "movL", { Rd
, Td
}, 0 },
11772 { "movL", { Td
, Rd
}, 0 },
11775 /* MOD_0F2B_PREFIX_0 */
11776 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
11779 /* MOD_0F2B_PREFIX_1 */
11780 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
11783 /* MOD_0F2B_PREFIX_2 */
11784 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
11787 /* MOD_0F2B_PREFIX_3 */
11788 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
11793 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
11796 /* MOD_0F71_REG_2 */
11798 { "psrlw", { MS
, Ib
}, 0 },
11801 /* MOD_0F71_REG_4 */
11803 { "psraw", { MS
, Ib
}, 0 },
11806 /* MOD_0F71_REG_6 */
11808 { "psllw", { MS
, Ib
}, 0 },
11811 /* MOD_0F72_REG_2 */
11813 { "psrld", { MS
, Ib
}, 0 },
11816 /* MOD_0F72_REG_4 */
11818 { "psrad", { MS
, Ib
}, 0 },
11821 /* MOD_0F72_REG_6 */
11823 { "pslld", { MS
, Ib
}, 0 },
11826 /* MOD_0F73_REG_2 */
11828 { "psrlq", { MS
, Ib
}, 0 },
11831 /* MOD_0F73_REG_3 */
11833 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11836 /* MOD_0F73_REG_6 */
11838 { "psllq", { MS
, Ib
}, 0 },
11841 /* MOD_0F73_REG_7 */
11843 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11846 /* MOD_0FAE_REG_0 */
11847 { "fxsave", { FXSAVE
}, 0 },
11848 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11851 /* MOD_0FAE_REG_1 */
11852 { "fxrstor", { FXSAVE
}, 0 },
11853 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11856 /* MOD_0FAE_REG_2 */
11857 { "ldmxcsr", { Md
}, 0 },
11858 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11861 /* MOD_0FAE_REG_3 */
11862 { "stmxcsr", { Md
}, 0 },
11863 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11866 /* MOD_0FAE_REG_4 */
11867 { "xsave", { FXSAVE
}, 0 },
11870 /* MOD_0FAE_REG_5 */
11871 { "xrstor", { FXSAVE
}, 0 },
11872 { RM_TABLE (RM_0FAE_REG_5
) },
11875 /* MOD_0FAE_REG_6 */
11876 { PREFIX_TABLE (PREFIX_0FAE_REG_6
) },
11877 { RM_TABLE (RM_0FAE_REG_6
) },
11880 /* MOD_0FAE_REG_7 */
11881 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11882 { RM_TABLE (RM_0FAE_REG_7
) },
11886 { "lssS", { Gv
, Mp
}, 0 },
11890 { "lfsS", { Gv
, Mp
}, 0 },
11894 { "lgsS", { Gv
, Mp
}, 0 },
11898 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
11901 /* MOD_0FC7_REG_3 */
11902 { "xrstors", { FXSAVE
}, 0 },
11905 /* MOD_0FC7_REG_4 */
11906 { "xsavec", { FXSAVE
}, 0 },
11909 /* MOD_0FC7_REG_5 */
11910 { "xsaves", { FXSAVE
}, 0 },
11913 /* MOD_0FC7_REG_6 */
11914 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
11915 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
11918 /* MOD_0FC7_REG_7 */
11919 { "vmptrst", { Mq
}, 0 },
11920 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
11925 { "pmovmskb", { Gdq
, MS
}, 0 },
11928 /* MOD_0FE7_PREFIX_2 */
11929 { "movntdq", { Mx
, XM
}, 0 },
11932 /* MOD_0FF0_PREFIX_3 */
11933 { "lddqu", { XM
, M
}, 0 },
11936 /* MOD_0F382A_PREFIX_2 */
11937 { "movntdqa", { XM
, Mx
}, 0 },
11941 { "bound{S|}", { Gv
, Ma
}, 0 },
11942 { EVEX_TABLE (EVEX_0F
) },
11946 { "lesS", { Gv
, Mp
}, 0 },
11947 { VEX_C4_TABLE (VEX_0F
) },
11951 { "ldsS", { Gv
, Mp
}, 0 },
11952 { VEX_C5_TABLE (VEX_0F
) },
11955 /* MOD_VEX_0F12_PREFIX_0 */
11956 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11957 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11961 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11964 /* MOD_VEX_0F16_PREFIX_0 */
11965 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11966 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11970 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11974 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11977 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11979 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
11982 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11984 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
11987 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11989 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
11992 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11994 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
11997 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11999 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
12002 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
12004 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
12007 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
12009 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
12012 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
12014 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
12017 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
12019 { "knotw", { MaskG
, MaskR
}, 0 },
12022 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
12024 { "knotq", { MaskG
, MaskR
}, 0 },
12027 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
12029 { "knotb", { MaskG
, MaskR
}, 0 },
12032 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
12034 { "knotd", { MaskG
, MaskR
}, 0 },
12037 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
12039 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
12042 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
12044 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
12047 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
12049 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
12052 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
12054 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
12057 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
12059 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
12062 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
12064 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
12067 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
12069 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
12072 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
12074 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
12077 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12079 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
12082 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12084 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
12087 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12089 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
12092 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12094 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
12097 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12099 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
12102 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12104 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
12107 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12109 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
12112 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12114 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
12117 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12119 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
12122 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12124 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
12127 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12129 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
12134 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
12137 /* MOD_VEX_0F71_REG_2 */
12139 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
12142 /* MOD_VEX_0F71_REG_4 */
12144 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
12147 /* MOD_VEX_0F71_REG_6 */
12149 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
12152 /* MOD_VEX_0F72_REG_2 */
12154 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
12157 /* MOD_VEX_0F72_REG_4 */
12159 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
12162 /* MOD_VEX_0F72_REG_6 */
12164 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
12167 /* MOD_VEX_0F73_REG_2 */
12169 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
12172 /* MOD_VEX_0F73_REG_3 */
12174 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
12177 /* MOD_VEX_0F73_REG_6 */
12179 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
12182 /* MOD_VEX_0F73_REG_7 */
12184 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
12187 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12188 { "kmovw", { Ew
, MaskG
}, 0 },
12192 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12193 { "kmovq", { Eq
, MaskG
}, 0 },
12197 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12198 { "kmovb", { Eb
, MaskG
}, 0 },
12202 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12203 { "kmovd", { Ed
, MaskG
}, 0 },
12207 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12209 { "kmovw", { MaskG
, Rdq
}, 0 },
12212 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12214 { "kmovb", { MaskG
, Rdq
}, 0 },
12217 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12219 { "kmovd", { MaskG
, Rdq
}, 0 },
12222 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12224 { "kmovq", { MaskG
, Rdq
}, 0 },
12227 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12229 { "kmovw", { Gdq
, MaskR
}, 0 },
12232 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12234 { "kmovb", { Gdq
, MaskR
}, 0 },
12237 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12239 { "kmovd", { Gdq
, MaskR
}, 0 },
12242 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12244 { "kmovq", { Gdq
, MaskR
}, 0 },
12247 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12249 { "kortestw", { MaskG
, MaskR
}, 0 },
12252 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12254 { "kortestq", { MaskG
, MaskR
}, 0 },
12257 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12259 { "kortestb", { MaskG
, MaskR
}, 0 },
12262 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12264 { "kortestd", { MaskG
, MaskR
}, 0 },
12267 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12269 { "ktestw", { MaskG
, MaskR
}, 0 },
12272 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12274 { "ktestq", { MaskG
, MaskR
}, 0 },
12277 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12279 { "ktestb", { MaskG
, MaskR
}, 0 },
12282 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12284 { "ktestd", { MaskG
, MaskR
}, 0 },
12287 /* MOD_VEX_0FAE_REG_2 */
12288 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
12291 /* MOD_VEX_0FAE_REG_3 */
12292 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
12295 /* MOD_VEX_0FD7_PREFIX_2 */
12297 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
12300 /* MOD_VEX_0FE7_PREFIX_2 */
12301 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
12304 /* MOD_VEX_0FF0_PREFIX_3 */
12305 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
12308 /* MOD_VEX_0F381A_PREFIX_2 */
12309 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
12312 /* MOD_VEX_0F382A_PREFIX_2 */
12313 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
12316 /* MOD_VEX_0F382C_PREFIX_2 */
12317 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
12320 /* MOD_VEX_0F382D_PREFIX_2 */
12321 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
12324 /* MOD_VEX_0F382E_PREFIX_2 */
12325 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
12328 /* MOD_VEX_0F382F_PREFIX_2 */
12329 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
12332 /* MOD_VEX_0F385A_PREFIX_2 */
12333 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
12336 /* MOD_VEX_0F388C_PREFIX_2 */
12337 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
12340 /* MOD_VEX_0F388E_PREFIX_2 */
12341 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
12344 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12346 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
12349 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12351 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
12354 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12356 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
12359 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12361 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
12364 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12366 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
12369 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12371 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
12374 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12376 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
12379 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12381 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
12383 #define NEED_MOD_TABLE
12384 #include "i386-dis-evex.h"
12385 #undef NEED_MOD_TABLE
12388 static const struct dis386 rm_table
[][8] = {
12391 { "xabort", { Skip_MODRM
, Ib
}, 0 },
12395 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
12398 /* RM_0F01_REG_0 */
12400 { "vmcall", { Skip_MODRM
}, 0 },
12401 { "vmlaunch", { Skip_MODRM
}, 0 },
12402 { "vmresume", { Skip_MODRM
}, 0 },
12403 { "vmxoff", { Skip_MODRM
}, 0 },
12406 /* RM_0F01_REG_1 */
12407 { "monitor", { { OP_Monitor
, 0 } }, 0 },
12408 { "mwait", { { OP_Mwait
, 0 } }, 0 },
12409 { "clac", { Skip_MODRM
}, 0 },
12410 { "stac", { Skip_MODRM
}, 0 },
12414 { "encls", { Skip_MODRM
}, 0 },
12417 /* RM_0F01_REG_2 */
12418 { "xgetbv", { Skip_MODRM
}, 0 },
12419 { "xsetbv", { Skip_MODRM
}, 0 },
12422 { "vmfunc", { Skip_MODRM
}, 0 },
12423 { "xend", { Skip_MODRM
}, 0 },
12424 { "xtest", { Skip_MODRM
}, 0 },
12425 { "enclu", { Skip_MODRM
}, 0 },
12428 /* RM_0F01_REG_3 */
12429 { "vmrun", { Skip_MODRM
}, 0 },
12430 { "vmmcall", { Skip_MODRM
}, 0 },
12431 { "vmload", { Skip_MODRM
}, 0 },
12432 { "vmsave", { Skip_MODRM
}, 0 },
12433 { "stgi", { Skip_MODRM
}, 0 },
12434 { "clgi", { Skip_MODRM
}, 0 },
12435 { "skinit", { Skip_MODRM
}, 0 },
12436 { "invlpga", { Skip_MODRM
}, 0 },
12439 /* RM_0F01_REG_5 */
12446 { "rdpkru", { Skip_MODRM
}, 0 },
12447 { "wrpkru", { Skip_MODRM
}, 0 },
12450 /* RM_0F01_REG_7 */
12451 { "swapgs", { Skip_MODRM
}, 0 },
12452 { "rdtscp", { Skip_MODRM
}, 0 },
12453 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
12454 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
12455 { "clzero", { Skip_MODRM
}, 0 },
12458 /* RM_0FAE_REG_5 */
12459 { "lfence", { Skip_MODRM
}, 0 },
12462 /* RM_0FAE_REG_6 */
12463 { "mfence", { Skip_MODRM
}, 0 },
12466 /* RM_0FAE_REG_7 */
12467 { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7
) },
12471 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12473 /* We use the high bit to indicate different name for the same
12475 #define REP_PREFIX (0xf3 | 0x100)
12476 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12477 #define XRELEASE_PREFIX (0xf3 | 0x400)
12478 #define BND_PREFIX (0xf2 | 0x400)
12483 int newrex
, i
, length
;
12489 last_lock_prefix
= -1;
12490 last_repz_prefix
= -1;
12491 last_repnz_prefix
= -1;
12492 last_data_prefix
= -1;
12493 last_addr_prefix
= -1;
12494 last_rex_prefix
= -1;
12495 last_seg_prefix
= -1;
12497 active_seg_prefix
= 0;
12498 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12499 all_prefixes
[i
] = 0;
12502 /* The maximum instruction length is 15bytes. */
12503 while (length
< MAX_CODE_LENGTH
- 1)
12505 FETCH_DATA (the_info
, codep
+ 1);
12509 /* REX prefixes family. */
12526 if (address_mode
== mode_64bit
)
12530 last_rex_prefix
= i
;
12533 prefixes
|= PREFIX_REPZ
;
12534 last_repz_prefix
= i
;
12537 prefixes
|= PREFIX_REPNZ
;
12538 last_repnz_prefix
= i
;
12541 prefixes
|= PREFIX_LOCK
;
12542 last_lock_prefix
= i
;
12545 prefixes
|= PREFIX_CS
;
12546 last_seg_prefix
= i
;
12547 active_seg_prefix
= PREFIX_CS
;
12550 prefixes
|= PREFIX_SS
;
12551 last_seg_prefix
= i
;
12552 active_seg_prefix
= PREFIX_SS
;
12555 prefixes
|= PREFIX_DS
;
12556 last_seg_prefix
= i
;
12557 active_seg_prefix
= PREFIX_DS
;
12560 prefixes
|= PREFIX_ES
;
12561 last_seg_prefix
= i
;
12562 active_seg_prefix
= PREFIX_ES
;
12565 prefixes
|= PREFIX_FS
;
12566 last_seg_prefix
= i
;
12567 active_seg_prefix
= PREFIX_FS
;
12570 prefixes
|= PREFIX_GS
;
12571 last_seg_prefix
= i
;
12572 active_seg_prefix
= PREFIX_GS
;
12575 prefixes
|= PREFIX_DATA
;
12576 last_data_prefix
= i
;
12579 prefixes
|= PREFIX_ADDR
;
12580 last_addr_prefix
= i
;
12583 /* fwait is really an instruction. If there are prefixes
12584 before the fwait, they belong to the fwait, *not* to the
12585 following instruction. */
12587 if (prefixes
|| rex
)
12589 prefixes
|= PREFIX_FWAIT
;
12591 /* This ensures that the previous REX prefixes are noticed
12592 as unused prefixes, as in the return case below. */
12596 prefixes
= PREFIX_FWAIT
;
12601 /* Rex is ignored when followed by another prefix. */
12607 if (*codep
!= FWAIT_OPCODE
)
12608 all_prefixes
[i
++] = *codep
;
12616 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12619 static const char *
12620 prefix_name (int pref
, int sizeflag
)
12622 static const char *rexes
[16] =
12625 "rex.B", /* 0x41 */
12626 "rex.X", /* 0x42 */
12627 "rex.XB", /* 0x43 */
12628 "rex.R", /* 0x44 */
12629 "rex.RB", /* 0x45 */
12630 "rex.RX", /* 0x46 */
12631 "rex.RXB", /* 0x47 */
12632 "rex.W", /* 0x48 */
12633 "rex.WB", /* 0x49 */
12634 "rex.WX", /* 0x4a */
12635 "rex.WXB", /* 0x4b */
12636 "rex.WR", /* 0x4c */
12637 "rex.WRB", /* 0x4d */
12638 "rex.WRX", /* 0x4e */
12639 "rex.WRXB", /* 0x4f */
12644 /* REX prefixes family. */
12661 return rexes
[pref
- 0x40];
12681 return (sizeflag
& DFLAG
) ? "data16" : "data32";
12683 if (address_mode
== mode_64bit
)
12684 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
12686 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
12691 case XACQUIRE_PREFIX
:
12693 case XRELEASE_PREFIX
:
12702 static char op_out
[MAX_OPERANDS
][100];
12703 static int op_ad
, op_index
[MAX_OPERANDS
];
12704 static int two_source_ops
;
12705 static bfd_vma op_address
[MAX_OPERANDS
];
12706 static bfd_vma op_riprel
[MAX_OPERANDS
];
12707 static bfd_vma start_pc
;
12710 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12711 * (see topic "Redundant prefixes" in the "Differences from 8086"
12712 * section of the "Virtual 8086 Mode" chapter.)
12713 * 'pc' should be the address of this instruction, it will
12714 * be used to print the target address if this is a relative jump or call
12715 * The function returns the length of this instruction in bytes.
12718 static char intel_syntax
;
12719 static char intel_mnemonic
= !SYSV386_COMPAT
;
12720 static char open_char
;
12721 static char close_char
;
12722 static char separator_char
;
12723 static char scale_char
;
12731 static enum x86_64_isa isa64
;
12733 /* Here for backwards compatibility. When gdb stops using
12734 print_insn_i386_att and print_insn_i386_intel these functions can
12735 disappear, and print_insn_i386 be merged into print_insn. */
12737 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
12741 return print_insn (pc
, info
);
12745 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
12749 return print_insn (pc
, info
);
12753 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
12757 return print_insn (pc
, info
);
12761 print_i386_disassembler_options (FILE *stream
)
12763 fprintf (stream
, _("\n\
12764 The following i386/x86-64 specific disassembler options are supported for use\n\
12765 with the -M switch (multiple options should be separated by commas):\n"));
12767 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
12768 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
12769 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
12770 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
12771 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
12772 fprintf (stream
, _(" att-mnemonic\n"
12773 " Display instruction in AT&T mnemonic\n"));
12774 fprintf (stream
, _(" intel-mnemonic\n"
12775 " Display instruction in Intel mnemonic\n"));
12776 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
12777 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
12778 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
12779 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
12780 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
12781 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12782 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
12783 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
12787 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
12789 /* Get a pointer to struct dis386 with a valid name. */
12791 static const struct dis386
*
12792 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
12794 int vindex
, vex_table_index
;
12796 if (dp
->name
!= NULL
)
12799 switch (dp
->op
[0].bytemode
)
12801 case USE_REG_TABLE
:
12802 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
12805 case USE_MOD_TABLE
:
12806 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
12807 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
12811 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
12814 case USE_PREFIX_TABLE
:
12817 /* The prefix in VEX is implicit. */
12818 switch (vex
.prefix
)
12823 case REPE_PREFIX_OPCODE
:
12826 case DATA_PREFIX_OPCODE
:
12829 case REPNE_PREFIX_OPCODE
:
12839 int last_prefix
= -1;
12842 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12843 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12845 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12847 if (last_repz_prefix
> last_repnz_prefix
)
12850 prefix
= PREFIX_REPZ
;
12851 last_prefix
= last_repz_prefix
;
12856 prefix
= PREFIX_REPNZ
;
12857 last_prefix
= last_repnz_prefix
;
12860 /* Check if prefix should be ignored. */
12861 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
12862 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
12867 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12870 prefix
= PREFIX_DATA
;
12871 last_prefix
= last_data_prefix
;
12876 used_prefixes
|= prefix
;
12877 all_prefixes
[last_prefix
] = 0;
12880 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12883 case USE_X86_64_TABLE
:
12884 vindex
= address_mode
== mode_64bit
? 1 : 0;
12885 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12888 case USE_3BYTE_TABLE
:
12889 FETCH_DATA (info
, codep
+ 2);
12891 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12893 modrm
.mod
= (*codep
>> 6) & 3;
12894 modrm
.reg
= (*codep
>> 3) & 7;
12895 modrm
.rm
= *codep
& 7;
12898 case USE_VEX_LEN_TABLE
:
12902 switch (vex
.length
)
12915 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12918 case USE_XOP_8F_TABLE
:
12919 FETCH_DATA (info
, codep
+ 3);
12920 /* All bits in the REX prefix are ignored. */
12922 rex
= ~(*codep
>> 5) & 0x7;
12924 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12925 switch ((*codep
& 0x1f))
12931 vex_table_index
= XOP_08
;
12934 vex_table_index
= XOP_09
;
12937 vex_table_index
= XOP_0A
;
12941 vex
.w
= *codep
& 0x80;
12942 if (vex
.w
&& address_mode
== mode_64bit
)
12945 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12946 if (address_mode
!= mode_64bit
12947 && vex
.register_specifier
> 0x7)
12953 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12954 switch ((*codep
& 0x3))
12960 vex
.prefix
= DATA_PREFIX_OPCODE
;
12963 vex
.prefix
= REPE_PREFIX_OPCODE
;
12966 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12973 dp
= &xop_table
[vex_table_index
][vindex
];
12976 FETCH_DATA (info
, codep
+ 1);
12977 modrm
.mod
= (*codep
>> 6) & 3;
12978 modrm
.reg
= (*codep
>> 3) & 7;
12979 modrm
.rm
= *codep
& 7;
12982 case USE_VEX_C4_TABLE
:
12984 FETCH_DATA (info
, codep
+ 3);
12985 /* All bits in the REX prefix are ignored. */
12987 rex
= ~(*codep
>> 5) & 0x7;
12988 switch ((*codep
& 0x1f))
12994 vex_table_index
= VEX_0F
;
12997 vex_table_index
= VEX_0F38
;
13000 vex_table_index
= VEX_0F3A
;
13004 vex
.w
= *codep
& 0x80;
13005 if (vex
.w
&& address_mode
== mode_64bit
)
13008 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
13009 if (address_mode
!= mode_64bit
13010 && vex
.register_specifier
> 0x7)
13016 vex
.length
= (*codep
& 0x4) ? 256 : 128;
13017 switch ((*codep
& 0x3))
13023 vex
.prefix
= DATA_PREFIX_OPCODE
;
13026 vex
.prefix
= REPE_PREFIX_OPCODE
;
13029 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13036 dp
= &vex_table
[vex_table_index
][vindex
];
13038 /* There is no MODRM byte for VEX [82|77]. */
13039 if (vindex
!= 0x77 && vindex
!= 0x82)
13041 FETCH_DATA (info
, codep
+ 1);
13042 modrm
.mod
= (*codep
>> 6) & 3;
13043 modrm
.reg
= (*codep
>> 3) & 7;
13044 modrm
.rm
= *codep
& 7;
13048 case USE_VEX_C5_TABLE
:
13050 FETCH_DATA (info
, codep
+ 2);
13051 /* All bits in the REX prefix are ignored. */
13053 rex
= (*codep
& 0x80) ? 0 : REX_R
;
13055 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
13056 if (address_mode
!= mode_64bit
13057 && vex
.register_specifier
> 0x7)
13065 vex
.length
= (*codep
& 0x4) ? 256 : 128;
13066 switch ((*codep
& 0x3))
13072 vex
.prefix
= DATA_PREFIX_OPCODE
;
13075 vex
.prefix
= REPE_PREFIX_OPCODE
;
13078 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13085 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
13087 /* There is no MODRM byte for VEX [82|77]. */
13088 if (vindex
!= 0x77 && vindex
!= 0x82)
13090 FETCH_DATA (info
, codep
+ 1);
13091 modrm
.mod
= (*codep
>> 6) & 3;
13092 modrm
.reg
= (*codep
>> 3) & 7;
13093 modrm
.rm
= *codep
& 7;
13097 case USE_VEX_W_TABLE
:
13101 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
13104 case USE_EVEX_TABLE
:
13105 two_source_ops
= 0;
13108 FETCH_DATA (info
, codep
+ 4);
13109 /* All bits in the REX prefix are ignored. */
13111 /* The first byte after 0x62. */
13112 rex
= ~(*codep
>> 5) & 0x7;
13113 vex
.r
= *codep
& 0x10;
13114 switch ((*codep
& 0xf))
13117 return &bad_opcode
;
13119 vex_table_index
= EVEX_0F
;
13122 vex_table_index
= EVEX_0F38
;
13125 vex_table_index
= EVEX_0F3A
;
13129 /* The second byte after 0x62. */
13131 vex
.w
= *codep
& 0x80;
13132 if (vex
.w
&& address_mode
== mode_64bit
)
13135 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
13136 if (address_mode
!= mode_64bit
)
13138 /* In 16/32-bit mode silently ignore following bits. */
13142 vex
.register_specifier
&= 0x7;
13146 if (!(*codep
& 0x4))
13147 return &bad_opcode
;
13149 switch ((*codep
& 0x3))
13155 vex
.prefix
= DATA_PREFIX_OPCODE
;
13158 vex
.prefix
= REPE_PREFIX_OPCODE
;
13161 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13165 /* The third byte after 0x62. */
13168 /* Remember the static rounding bits. */
13169 vex
.ll
= (*codep
>> 5) & 3;
13170 vex
.b
= (*codep
& 0x10) != 0;
13172 vex
.v
= *codep
& 0x8;
13173 vex
.mask_register_specifier
= *codep
& 0x7;
13174 vex
.zeroing
= *codep
& 0x80;
13180 dp
= &evex_table
[vex_table_index
][vindex
];
13182 FETCH_DATA (info
, codep
+ 1);
13183 modrm
.mod
= (*codep
>> 6) & 3;
13184 modrm
.reg
= (*codep
>> 3) & 7;
13185 modrm
.rm
= *codep
& 7;
13187 /* Set vector length. */
13188 if (modrm
.mod
== 3 && vex
.b
)
13204 return &bad_opcode
;
13217 if (dp
->name
!= NULL
)
13220 return get_valid_dis386 (dp
, info
);
13224 get_sib (disassemble_info
*info
, int sizeflag
)
13226 /* If modrm.mod == 3, operand must be register. */
13228 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13232 FETCH_DATA (info
, codep
+ 2);
13233 sib
.index
= (codep
[1] >> 3) & 7;
13234 sib
.scale
= (codep
[1] >> 6) & 3;
13235 sib
.base
= codep
[1] & 7;
13240 print_insn (bfd_vma pc
, disassemble_info
*info
)
13242 const struct dis386
*dp
;
13244 char *op_txt
[MAX_OPERANDS
];
13246 int sizeflag
, orig_sizeflag
;
13248 struct dis_private priv
;
13251 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13252 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
13253 address_mode
= mode_32bit
;
13254 else if (info
->mach
== bfd_mach_i386_i8086
)
13256 address_mode
= mode_16bit
;
13257 priv
.orig_sizeflag
= 0;
13260 address_mode
= mode_64bit
;
13262 if (intel_syntax
== (char) -1)
13263 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
13265 for (p
= info
->disassembler_options
; p
!= NULL
; )
13267 if (CONST_STRNEQ (p
, "amd64"))
13269 else if (CONST_STRNEQ (p
, "intel64"))
13271 else if (CONST_STRNEQ (p
, "x86-64"))
13273 address_mode
= mode_64bit
;
13274 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13276 else if (CONST_STRNEQ (p
, "i386"))
13278 address_mode
= mode_32bit
;
13279 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13281 else if (CONST_STRNEQ (p
, "i8086"))
13283 address_mode
= mode_16bit
;
13284 priv
.orig_sizeflag
= 0;
13286 else if (CONST_STRNEQ (p
, "intel"))
13289 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
13290 intel_mnemonic
= 1;
13292 else if (CONST_STRNEQ (p
, "att"))
13295 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
13296 intel_mnemonic
= 0;
13298 else if (CONST_STRNEQ (p
, "addr"))
13300 if (address_mode
== mode_64bit
)
13302 if (p
[4] == '3' && p
[5] == '2')
13303 priv
.orig_sizeflag
&= ~AFLAG
;
13304 else if (p
[4] == '6' && p
[5] == '4')
13305 priv
.orig_sizeflag
|= AFLAG
;
13309 if (p
[4] == '1' && p
[5] == '6')
13310 priv
.orig_sizeflag
&= ~AFLAG
;
13311 else if (p
[4] == '3' && p
[5] == '2')
13312 priv
.orig_sizeflag
|= AFLAG
;
13315 else if (CONST_STRNEQ (p
, "data"))
13317 if (p
[4] == '1' && p
[5] == '6')
13318 priv
.orig_sizeflag
&= ~DFLAG
;
13319 else if (p
[4] == '3' && p
[5] == '2')
13320 priv
.orig_sizeflag
|= DFLAG
;
13322 else if (CONST_STRNEQ (p
, "suffix"))
13323 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
13325 p
= strchr (p
, ',');
13330 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
13332 (*info
->fprintf_func
) (info
->stream
,
13333 _("64-bit address is disabled"));
13339 names64
= intel_names64
;
13340 names32
= intel_names32
;
13341 names16
= intel_names16
;
13342 names8
= intel_names8
;
13343 names8rex
= intel_names8rex
;
13344 names_seg
= intel_names_seg
;
13345 names_mm
= intel_names_mm
;
13346 names_bnd
= intel_names_bnd
;
13347 names_xmm
= intel_names_xmm
;
13348 names_ymm
= intel_names_ymm
;
13349 names_zmm
= intel_names_zmm
;
13350 index64
= intel_index64
;
13351 index32
= intel_index32
;
13352 names_mask
= intel_names_mask
;
13353 index16
= intel_index16
;
13356 separator_char
= '+';
13361 names64
= att_names64
;
13362 names32
= att_names32
;
13363 names16
= att_names16
;
13364 names8
= att_names8
;
13365 names8rex
= att_names8rex
;
13366 names_seg
= att_names_seg
;
13367 names_mm
= att_names_mm
;
13368 names_bnd
= att_names_bnd
;
13369 names_xmm
= att_names_xmm
;
13370 names_ymm
= att_names_ymm
;
13371 names_zmm
= att_names_zmm
;
13372 index64
= att_index64
;
13373 index32
= att_index32
;
13374 names_mask
= att_names_mask
;
13375 index16
= att_index16
;
13378 separator_char
= ',';
13382 /* The output looks better if we put 7 bytes on a line, since that
13383 puts most long word instructions on a single line. Use 8 bytes
13385 if ((info
->mach
& bfd_mach_l1om
) != 0)
13386 info
->bytes_per_line
= 8;
13388 info
->bytes_per_line
= 7;
13390 info
->private_data
= &priv
;
13391 priv
.max_fetched
= priv
.the_buffer
;
13392 priv
.insn_start
= pc
;
13395 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13403 start_codep
= priv
.the_buffer
;
13404 codep
= priv
.the_buffer
;
13406 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
13410 /* Getting here means we tried for data but didn't get it. That
13411 means we have an incomplete instruction of some sort. Just
13412 print the first byte as a prefix or a .byte pseudo-op. */
13413 if (codep
> priv
.the_buffer
)
13415 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
13417 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
13420 /* Just print the first byte as a .byte instruction. */
13421 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
13422 (unsigned int) priv
.the_buffer
[0]);
13432 sizeflag
= priv
.orig_sizeflag
;
13434 if (!ckprefix () || rex_used
)
13436 /* Too many prefixes or unused REX prefixes. */
13438 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
13440 (*info
->fprintf_func
) (info
->stream
, "%s%s",
13442 prefix_name (all_prefixes
[i
], sizeflag
));
13446 insn_codep
= codep
;
13448 FETCH_DATA (info
, codep
+ 1);
13449 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
13451 if (((prefixes
& PREFIX_FWAIT
)
13452 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
13454 /* Handle prefixes before fwait. */
13455 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
13457 (*info
->fprintf_func
) (info
->stream
, "%s ",
13458 prefix_name (all_prefixes
[i
], sizeflag
));
13459 (*info
->fprintf_func
) (info
->stream
, "fwait");
13463 if (*codep
== 0x0f)
13465 unsigned char threebyte
;
13468 FETCH_DATA (info
, codep
+ 1);
13469 threebyte
= *codep
;
13470 dp
= &dis386_twobyte
[threebyte
];
13471 need_modrm
= twobyte_has_modrm
[*codep
];
13476 dp
= &dis386
[*codep
];
13477 need_modrm
= onebyte_has_modrm
[*codep
];
13481 /* Save sizeflag for printing the extra prefixes later before updating
13482 it for mnemonic and operand processing. The prefix names depend
13483 only on the address mode. */
13484 orig_sizeflag
= sizeflag
;
13485 if (prefixes
& PREFIX_ADDR
)
13487 if ((prefixes
& PREFIX_DATA
))
13493 FETCH_DATA (info
, codep
+ 1);
13494 modrm
.mod
= (*codep
>> 6) & 3;
13495 modrm
.reg
= (*codep
>> 3) & 7;
13496 modrm
.rm
= *codep
& 7;
13504 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
13506 get_sib (info
, sizeflag
);
13507 dofloat (sizeflag
);
13511 dp
= get_valid_dis386 (dp
, info
);
13512 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
13514 get_sib (info
, sizeflag
);
13515 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13518 op_ad
= MAX_OPERANDS
- 1 - i
;
13520 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
13521 /* For EVEX instruction after the last operand masking
13522 should be printed. */
13523 if (i
== 0 && vex
.evex
)
13525 /* Don't print {%k0}. */
13526 if (vex
.mask_register_specifier
)
13529 oappend (names_mask
[vex
.mask_register_specifier
]);
13539 /* Check if the REX prefix is used. */
13540 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
13541 all_prefixes
[last_rex_prefix
] = 0;
13543 /* Check if the SEG prefix is used. */
13544 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
13545 | PREFIX_FS
| PREFIX_GS
)) != 0
13546 && (used_prefixes
& active_seg_prefix
) != 0)
13547 all_prefixes
[last_seg_prefix
] = 0;
13549 /* Check if the ADDR prefix is used. */
13550 if ((prefixes
& PREFIX_ADDR
) != 0
13551 && (used_prefixes
& PREFIX_ADDR
) != 0)
13552 all_prefixes
[last_addr_prefix
] = 0;
13554 /* Check if the DATA prefix is used. */
13555 if ((prefixes
& PREFIX_DATA
) != 0
13556 && (used_prefixes
& PREFIX_DATA
) != 0)
13557 all_prefixes
[last_data_prefix
] = 0;
13559 /* Print the extra prefixes. */
13561 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
13562 if (all_prefixes
[i
])
13565 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
13568 prefix_length
+= strlen (name
) + 1;
13569 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
13572 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13573 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13574 used by putop and MMX/SSE operand and may be overriden by the
13575 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13577 if (dp
->prefix_requirement
== PREFIX_OPCODE
13578 && dp
!= &bad_opcode
13580 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
13582 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
13584 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
13586 && (used_prefixes
& PREFIX_DATA
) == 0))))
13588 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13589 return end_codep
- priv
.the_buffer
;
13592 /* Check maximum code length. */
13593 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
13595 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13596 return MAX_CODE_LENGTH
;
13599 obufp
= mnemonicendp
;
13600 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
13603 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
13605 /* The enter and bound instructions are printed with operands in the same
13606 order as the intel book; everything else is printed in reverse order. */
13607 if (intel_syntax
|| two_source_ops
)
13611 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13612 op_txt
[i
] = op_out
[i
];
13614 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
13615 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
13617 op_txt
[2] = op_out
[3];
13618 op_txt
[3] = op_out
[2];
13621 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
13623 op_ad
= op_index
[i
];
13624 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
13625 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
13626 riprel
= op_riprel
[i
];
13627 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
13628 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
13633 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13634 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
13638 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13642 (*info
->fprintf_func
) (info
->stream
, ",");
13643 if (op_index
[i
] != -1 && !op_riprel
[i
])
13644 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
13646 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
13650 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13651 if (op_index
[i
] != -1 && op_riprel
[i
])
13653 (*info
->fprintf_func
) (info
->stream
, " # ");
13654 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
13655 + op_address
[op_index
[i
]]), info
);
13658 return codep
- priv
.the_buffer
;
13661 static const char *float_mem
[] = {
13736 static const unsigned char float_mem_mode
[] = {
13811 #define ST { OP_ST, 0 }
13812 #define STi { OP_STi, 0 }
13814 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13815 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13816 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13817 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13818 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13819 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13820 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13821 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13822 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13824 static const struct dis386 float_reg
[][8] = {
13827 { "fadd", { ST
, STi
}, 0 },
13828 { "fmul", { ST
, STi
}, 0 },
13829 { "fcom", { STi
}, 0 },
13830 { "fcomp", { STi
}, 0 },
13831 { "fsub", { ST
, STi
}, 0 },
13832 { "fsubr", { ST
, STi
}, 0 },
13833 { "fdiv", { ST
, STi
}, 0 },
13834 { "fdivr", { ST
, STi
}, 0 },
13838 { "fld", { STi
}, 0 },
13839 { "fxch", { STi
}, 0 },
13849 { "fcmovb", { ST
, STi
}, 0 },
13850 { "fcmove", { ST
, STi
}, 0 },
13851 { "fcmovbe",{ ST
, STi
}, 0 },
13852 { "fcmovu", { ST
, STi
}, 0 },
13860 { "fcmovnb",{ ST
, STi
}, 0 },
13861 { "fcmovne",{ ST
, STi
}, 0 },
13862 { "fcmovnbe",{ ST
, STi
}, 0 },
13863 { "fcmovnu",{ ST
, STi
}, 0 },
13865 { "fucomi", { ST
, STi
}, 0 },
13866 { "fcomi", { ST
, STi
}, 0 },
13871 { "fadd", { STi
, ST
}, 0 },
13872 { "fmul", { STi
, ST
}, 0 },
13875 { "fsub!M", { STi
, ST
}, 0 },
13876 { "fsubM", { STi
, ST
}, 0 },
13877 { "fdiv!M", { STi
, ST
}, 0 },
13878 { "fdivM", { STi
, ST
}, 0 },
13882 { "ffree", { STi
}, 0 },
13884 { "fst", { STi
}, 0 },
13885 { "fstp", { STi
}, 0 },
13886 { "fucom", { STi
}, 0 },
13887 { "fucomp", { STi
}, 0 },
13893 { "faddp", { STi
, ST
}, 0 },
13894 { "fmulp", { STi
, ST
}, 0 },
13897 { "fsub!Mp", { STi
, ST
}, 0 },
13898 { "fsubMp", { STi
, ST
}, 0 },
13899 { "fdiv!Mp", { STi
, ST
}, 0 },
13900 { "fdivMp", { STi
, ST
}, 0 },
13904 { "ffreep", { STi
}, 0 },
13909 { "fucomip", { ST
, STi
}, 0 },
13910 { "fcomip", { ST
, STi
}, 0 },
13915 static char *fgrps
[][8] = {
13918 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13923 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13928 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13933 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13938 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13943 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13948 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13949 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13954 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13959 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13964 swap_operand (void)
13966 mnemonicendp
[0] = '.';
13967 mnemonicendp
[1] = 's';
13972 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13973 int sizeflag ATTRIBUTE_UNUSED
)
13975 /* Skip mod/rm byte. */
13981 dofloat (int sizeflag
)
13983 const struct dis386
*dp
;
13984 unsigned char floatop
;
13986 floatop
= codep
[-1];
13988 if (modrm
.mod
!= 3)
13990 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13992 putop (float_mem
[fp_indx
], sizeflag
);
13995 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13998 /* Skip mod/rm byte. */
14002 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
14003 if (dp
->name
== NULL
)
14005 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
14007 /* Instruction fnstsw is only one with strange arg. */
14008 if (floatop
== 0xdf && codep
[-1] == 0xe0)
14009 strcpy (op_out
[0], names16
[0]);
14013 putop (dp
->name
, sizeflag
);
14018 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
14023 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
14027 /* Like oappend (below), but S is a string starting with '%'.
14028 In Intel syntax, the '%' is elided. */
14030 oappend_maybe_intel (const char *s
)
14032 oappend (s
+ intel_syntax
);
14036 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14038 oappend_maybe_intel ("%st");
14042 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14044 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
14045 oappend_maybe_intel (scratchbuf
);
14048 /* Capital letters in template are macros. */
14050 putop (const char *in_template
, int sizeflag
)
14055 unsigned int l
= 0, len
= 1;
14058 #define SAVE_LAST(c) \
14059 if (l < len && l < sizeof (last)) \
14064 for (p
= in_template
; *p
; p
++)
14081 while (*++p
!= '|')
14082 if (*p
== '}' || *p
== '\0')
14085 /* Fall through. */
14090 while (*++p
!= '}')
14101 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14105 if (l
== 0 && len
== 1)
14110 if (sizeflag
& SUFFIX_ALWAYS
)
14123 if (address_mode
== mode_64bit
14124 && !(prefixes
& PREFIX_ADDR
))
14135 if (intel_syntax
&& !alt
)
14137 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14139 if (sizeflag
& DFLAG
)
14140 *obufp
++ = intel_syntax
? 'd' : 'l';
14142 *obufp
++ = intel_syntax
? 'w' : 's';
14143 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14147 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14150 if (modrm
.mod
== 3)
14156 if (sizeflag
& DFLAG
)
14157 *obufp
++ = intel_syntax
? 'd' : 'l';
14160 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14166 case 'E': /* For jcxz/jecxz */
14167 if (address_mode
== mode_64bit
)
14169 if (sizeflag
& AFLAG
)
14175 if (sizeflag
& AFLAG
)
14177 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14182 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
14184 if (sizeflag
& AFLAG
)
14185 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
14187 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
14188 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14192 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
14194 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14198 if (!(rex
& REX_W
))
14199 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14204 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
14205 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
14207 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
14210 if (prefixes
& PREFIX_DS
)
14229 if (l
!= 0 || len
!= 1)
14231 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14236 if (!need_vex
|| !vex
.evex
)
14239 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14241 switch (vex
.length
)
14259 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
14264 /* Fall through. */
14267 if (l
!= 0 || len
!= 1)
14275 if (sizeflag
& SUFFIX_ALWAYS
)
14279 if (intel_mnemonic
!= cond
)
14283 if ((prefixes
& PREFIX_FWAIT
) == 0)
14286 used_prefixes
|= PREFIX_FWAIT
;
14292 else if (intel_syntax
&& (sizeflag
& DFLAG
))
14296 if (!(rex
& REX_W
))
14297 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14301 && address_mode
== mode_64bit
14302 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14307 /* Fall through. */
14310 if (l
== 0 && len
== 1)
14315 if ((rex
& REX_W
) == 0
14316 && (prefixes
& PREFIX_DATA
))
14318 if ((sizeflag
& DFLAG
) == 0)
14320 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14324 if ((prefixes
& PREFIX_DATA
)
14326 || (sizeflag
& SUFFIX_ALWAYS
))
14333 if (sizeflag
& DFLAG
)
14337 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14343 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14349 if ((prefixes
& PREFIX_DATA
)
14351 || (sizeflag
& SUFFIX_ALWAYS
))
14358 if (sizeflag
& DFLAG
)
14359 *obufp
++ = intel_syntax
? 'd' : 'l';
14362 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14370 if (address_mode
== mode_64bit
14371 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14373 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14377 /* Fall through. */
14380 if (l
== 0 && len
== 1)
14383 if (intel_syntax
&& !alt
)
14386 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14392 if (sizeflag
& DFLAG
)
14393 *obufp
++ = intel_syntax
? 'd' : 'l';
14396 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14402 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14408 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
14423 else if (sizeflag
& DFLAG
)
14432 if (intel_syntax
&& !p
[1]
14433 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
14435 if (!(rex
& REX_W
))
14436 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14439 if (l
== 0 && len
== 1)
14443 if (address_mode
== mode_64bit
14444 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14446 if (sizeflag
& SUFFIX_ALWAYS
)
14468 /* Fall through. */
14471 if (l
== 0 && len
== 1)
14476 if (sizeflag
& SUFFIX_ALWAYS
)
14482 if (sizeflag
& DFLAG
)
14486 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14500 if (address_mode
== mode_64bit
14501 && !(prefixes
& PREFIX_ADDR
))
14512 if (l
!= 0 || len
!= 1)
14517 if (need_vex
&& vex
.prefix
)
14519 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
14526 if (prefixes
& PREFIX_DATA
)
14530 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14534 if (l
== 0 && len
== 1)
14536 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14547 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14555 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14557 switch (vex
.length
)
14573 if (l
== 0 && len
== 1)
14575 /* operand size flag for cwtl, cbtw */
14584 else if (sizeflag
& DFLAG
)
14588 if (!(rex
& REX_W
))
14589 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14596 && last
[0] != 'L'))
14603 if (last
[0] == 'X')
14604 *obufp
++ = vex
.w
? 'd': 's';
14606 *obufp
++ = vex
.w
? 'q': 'd';
14612 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14614 if (sizeflag
& DFLAG
)
14618 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14624 if (address_mode
== mode_64bit
14625 && (isa64
== intel64
14626 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
14628 else if ((prefixes
& PREFIX_DATA
))
14630 if (!(sizeflag
& DFLAG
))
14632 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14639 mnemonicendp
= obufp
;
14644 oappend (const char *s
)
14646 obufp
= stpcpy (obufp
, s
);
14652 /* Only print the active segment register. */
14653 if (!active_seg_prefix
)
14656 used_prefixes
|= active_seg_prefix
;
14657 switch (active_seg_prefix
)
14660 oappend_maybe_intel ("%cs:");
14663 oappend_maybe_intel ("%ds:");
14666 oappend_maybe_intel ("%ss:");
14669 oappend_maybe_intel ("%es:");
14672 oappend_maybe_intel ("%fs:");
14675 oappend_maybe_intel ("%gs:");
14683 OP_indirE (int bytemode
, int sizeflag
)
14687 OP_E (bytemode
, sizeflag
);
14691 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
14693 if (address_mode
== mode_64bit
)
14701 sprintf_vma (tmp
, disp
);
14702 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
14703 strcpy (buf
+ 2, tmp
+ i
);
14707 bfd_signed_vma v
= disp
;
14714 /* Check for possible overflow on 0x8000000000000000. */
14717 strcpy (buf
, "9223372036854775808");
14731 tmp
[28 - i
] = (v
% 10) + '0';
14735 strcpy (buf
, tmp
+ 29 - i
);
14741 sprintf (buf
, "0x%x", (unsigned int) disp
);
14743 sprintf (buf
, "%d", (int) disp
);
14747 /* Put DISP in BUF as signed hex number. */
14750 print_displacement (char *buf
, bfd_vma disp
)
14752 bfd_signed_vma val
= disp
;
14761 /* Check for possible overflow. */
14764 switch (address_mode
)
14767 strcpy (buf
+ j
, "0x8000000000000000");
14770 strcpy (buf
+ j
, "0x80000000");
14773 strcpy (buf
+ j
, "0x8000");
14783 sprintf_vma (tmp
, (bfd_vma
) val
);
14784 for (i
= 0; tmp
[i
] == '0'; i
++)
14786 if (tmp
[i
] == '\0')
14788 strcpy (buf
+ j
, tmp
+ i
);
14792 intel_operand_size (int bytemode
, int sizeflag
)
14796 && (bytemode
== x_mode
14797 || bytemode
== evex_half_bcst_xmmq_mode
))
14800 oappend ("QWORD PTR ");
14802 oappend ("DWORD PTR ");
14811 oappend ("BYTE PTR ");
14816 case dqw_swap_mode
:
14817 oappend ("WORD PTR ");
14820 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14822 oappend ("QWORD PTR ");
14831 oappend ("QWORD PTR ");
14834 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14835 oappend ("DWORD PTR ");
14837 oappend ("WORD PTR ");
14838 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14842 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14844 oappend ("WORD PTR ");
14845 if (!(rex
& REX_W
))
14846 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14849 if (sizeflag
& DFLAG
)
14850 oappend ("QWORD PTR ");
14852 oappend ("DWORD PTR ");
14853 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14856 case d_scalar_mode
:
14857 case d_scalar_swap_mode
:
14860 oappend ("DWORD PTR ");
14863 case q_scalar_mode
:
14864 case q_scalar_swap_mode
:
14866 oappend ("QWORD PTR ");
14869 if (address_mode
== mode_64bit
)
14870 oappend ("QWORD PTR ");
14872 oappend ("DWORD PTR ");
14875 if (sizeflag
& DFLAG
)
14876 oappend ("FWORD PTR ");
14878 oappend ("DWORD PTR ");
14879 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14882 oappend ("TBYTE PTR ");
14886 case evex_x_gscat_mode
:
14887 case evex_x_nobcst_mode
:
14890 switch (vex
.length
)
14893 oappend ("XMMWORD PTR ");
14896 oappend ("YMMWORD PTR ");
14899 oappend ("ZMMWORD PTR ");
14906 oappend ("XMMWORD PTR ");
14909 oappend ("XMMWORD PTR ");
14912 oappend ("YMMWORD PTR ");
14915 case evex_half_bcst_xmmq_mode
:
14919 switch (vex
.length
)
14922 oappend ("QWORD PTR ");
14925 oappend ("XMMWORD PTR ");
14928 oappend ("YMMWORD PTR ");
14938 switch (vex
.length
)
14943 oappend ("BYTE PTR ");
14953 switch (vex
.length
)
14958 oappend ("WORD PTR ");
14968 switch (vex
.length
)
14973 oappend ("DWORD PTR ");
14983 switch (vex
.length
)
14988 oappend ("QWORD PTR ");
14998 switch (vex
.length
)
15001 oappend ("WORD PTR ");
15004 oappend ("DWORD PTR ");
15007 oappend ("QWORD PTR ");
15017 switch (vex
.length
)
15020 oappend ("DWORD PTR ");
15023 oappend ("QWORD PTR ");
15026 oappend ("XMMWORD PTR ");
15036 switch (vex
.length
)
15039 oappend ("QWORD PTR ");
15042 oappend ("YMMWORD PTR ");
15045 oappend ("ZMMWORD PTR ");
15055 switch (vex
.length
)
15059 oappend ("XMMWORD PTR ");
15066 oappend ("OWORD PTR ");
15069 case vex_w_dq_mode
:
15070 case vex_scalar_w_dq_mode
:
15075 oappend ("QWORD PTR ");
15077 oappend ("DWORD PTR ");
15079 case vex_vsib_d_w_dq_mode
:
15080 case vex_vsib_q_w_dq_mode
:
15087 oappend ("QWORD PTR ");
15089 oappend ("DWORD PTR ");
15093 switch (vex
.length
)
15096 oappend ("XMMWORD PTR ");
15099 oappend ("YMMWORD PTR ");
15102 oappend ("ZMMWORD PTR ");
15109 case vex_vsib_q_w_d_mode
:
15110 case vex_vsib_d_w_d_mode
:
15111 if (!need_vex
|| !vex
.evex
)
15114 switch (vex
.length
)
15117 oappend ("QWORD PTR ");
15120 oappend ("XMMWORD PTR ");
15123 oappend ("YMMWORD PTR ");
15131 if (!need_vex
|| vex
.length
!= 128)
15134 oappend ("DWORD PTR ");
15136 oappend ("BYTE PTR ");
15142 oappend ("QWORD PTR ");
15144 oappend ("WORD PTR ");
15153 OP_E_register (int bytemode
, int sizeflag
)
15155 int reg
= modrm
.rm
;
15156 const char **names
;
15162 if ((sizeflag
& SUFFIX_ALWAYS
)
15163 && (bytemode
== b_swap_mode
15164 || bytemode
== v_swap_mode
15165 || bytemode
== dqw_swap_mode
))
15191 names
= address_mode
== mode_64bit
? names64
: names32
;
15197 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15210 case dqw_swap_mode
:
15216 if ((sizeflag
& DFLAG
)
15217 || (bytemode
!= v_mode
15218 && bytemode
!= v_swap_mode
))
15222 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15227 names
= names_mask
;
15232 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15235 oappend (names
[reg
]);
15239 OP_E_memory (int bytemode
, int sizeflag
)
15242 int add
= (rex
& REX_B
) ? 8 : 0;
15248 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15250 && bytemode
!= x_mode
15251 && bytemode
!= xmmq_mode
15252 && bytemode
!= evex_half_bcst_xmmq_mode
)
15261 case dqw_swap_mode
:
15268 case vex_vsib_d_w_dq_mode
:
15269 case vex_vsib_d_w_d_mode
:
15270 case vex_vsib_q_w_dq_mode
:
15271 case vex_vsib_q_w_d_mode
:
15272 case evex_x_gscat_mode
:
15274 shift
= vex
.w
? 3 : 2;
15277 case evex_half_bcst_xmmq_mode
:
15281 shift
= vex
.w
? 3 : 2;
15284 /* Fall through if vex.b == 0. */
15288 case evex_x_nobcst_mode
:
15290 switch (vex
.length
)
15313 case q_scalar_mode
:
15315 case q_scalar_swap_mode
:
15321 case d_scalar_mode
:
15323 case d_scalar_swap_mode
:
15335 /* Make necessary corrections to shift for modes that need it.
15336 For these modes we currently have shift 4, 5 or 6 depending on
15337 vex.length (it corresponds to xmmword, ymmword or zmmword
15338 operand). We might want to make it 3, 4 or 5 (e.g. for
15339 xmmq_mode). In case of broadcast enabled the corrections
15340 aren't needed, as element size is always 32 or 64 bits. */
15342 && (bytemode
== xmmq_mode
15343 || bytemode
== evex_half_bcst_xmmq_mode
))
15345 else if (bytemode
== xmmqd_mode
)
15347 else if (bytemode
== xmmdw_mode
)
15349 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
15357 intel_operand_size (bytemode
, sizeflag
);
15360 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15362 /* 32/64 bit address mode */
15371 int addr32flag
= !((sizeflag
& AFLAG
)
15372 || bytemode
== v_bnd_mode
15373 || bytemode
== bnd_mode
);
15374 const char **indexes64
= names64
;
15375 const char **indexes32
= names32
;
15385 vindex
= sib
.index
;
15391 case vex_vsib_d_w_dq_mode
:
15392 case vex_vsib_d_w_d_mode
:
15393 case vex_vsib_q_w_dq_mode
:
15394 case vex_vsib_q_w_d_mode
:
15404 switch (vex
.length
)
15407 indexes64
= indexes32
= names_xmm
;
15411 || bytemode
== vex_vsib_q_w_dq_mode
15412 || bytemode
== vex_vsib_q_w_d_mode
)
15413 indexes64
= indexes32
= names_ymm
;
15415 indexes64
= indexes32
= names_xmm
;
15419 || bytemode
== vex_vsib_q_w_dq_mode
15420 || bytemode
== vex_vsib_q_w_d_mode
)
15421 indexes64
= indexes32
= names_zmm
;
15423 indexes64
= indexes32
= names_ymm
;
15430 haveindex
= vindex
!= 4;
15437 rbase
= base
+ add
;
15445 if (address_mode
== mode_64bit
&& !havesib
)
15451 FETCH_DATA (the_info
, codep
+ 1);
15453 if ((disp
& 0x80) != 0)
15455 if (vex
.evex
&& shift
> 0)
15463 /* In 32bit mode, we need index register to tell [offset] from
15464 [eiz*1 + offset]. */
15465 needindex
= (havesib
15468 && address_mode
== mode_32bit
);
15469 havedisp
= (havebase
15471 || (havesib
&& (haveindex
|| scale
!= 0)));
15474 if (modrm
.mod
!= 0 || base
== 5)
15476 if (havedisp
|| riprel
)
15477 print_displacement (scratchbuf
, disp
);
15479 print_operand_value (scratchbuf
, 1, disp
);
15480 oappend (scratchbuf
);
15484 oappend (sizeflag
& AFLAG
? "(%rip)" : "(%eip)");
15488 if ((havebase
|| haveindex
|| riprel
)
15489 && (bytemode
!= v_bnd_mode
)
15490 && (bytemode
!= bnd_mode
))
15491 used_prefixes
|= PREFIX_ADDR
;
15493 if (havedisp
|| (intel_syntax
&& riprel
))
15495 *obufp
++ = open_char
;
15496 if (intel_syntax
&& riprel
)
15499 oappend (sizeflag
& AFLAG
? "rip" : "eip");
15503 oappend (address_mode
== mode_64bit
&& !addr32flag
15504 ? names64
[rbase
] : names32
[rbase
]);
15507 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15508 print index to tell base + index from base. */
15512 || (havebase
&& base
!= ESP_REG_NUM
))
15514 if (!intel_syntax
|| havebase
)
15516 *obufp
++ = separator_char
;
15520 oappend (address_mode
== mode_64bit
&& !addr32flag
15521 ? indexes64
[vindex
] : indexes32
[vindex
]);
15523 oappend (address_mode
== mode_64bit
&& !addr32flag
15524 ? index64
: index32
);
15526 *obufp
++ = scale_char
;
15528 sprintf (scratchbuf
, "%d", 1 << scale
);
15529 oappend (scratchbuf
);
15533 && (disp
|| modrm
.mod
!= 0 || base
== 5))
15535 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
15540 else if (modrm
.mod
!= 1 && disp
!= -disp
)
15544 disp
= - (bfd_signed_vma
) disp
;
15548 print_displacement (scratchbuf
, disp
);
15550 print_operand_value (scratchbuf
, 1, disp
);
15551 oappend (scratchbuf
);
15554 *obufp
++ = close_char
;
15557 else if (intel_syntax
)
15559 if (modrm
.mod
!= 0 || base
== 5)
15561 if (!active_seg_prefix
)
15563 oappend (names_seg
[ds_reg
- es_reg
]);
15566 print_operand_value (scratchbuf
, 1, disp
);
15567 oappend (scratchbuf
);
15573 /* 16 bit address mode */
15574 used_prefixes
|= prefixes
& PREFIX_ADDR
;
15581 if ((disp
& 0x8000) != 0)
15586 FETCH_DATA (the_info
, codep
+ 1);
15588 if ((disp
& 0x80) != 0)
15593 if ((disp
& 0x8000) != 0)
15599 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
15601 print_displacement (scratchbuf
, disp
);
15602 oappend (scratchbuf
);
15605 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
15607 *obufp
++ = open_char
;
15609 oappend (index16
[modrm
.rm
]);
15611 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
15613 if ((bfd_signed_vma
) disp
>= 0)
15618 else if (modrm
.mod
!= 1)
15622 disp
= - (bfd_signed_vma
) disp
;
15625 print_displacement (scratchbuf
, disp
);
15626 oappend (scratchbuf
);
15629 *obufp
++ = close_char
;
15632 else if (intel_syntax
)
15634 if (!active_seg_prefix
)
15636 oappend (names_seg
[ds_reg
- es_reg
]);
15639 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
15640 oappend (scratchbuf
);
15643 if (vex
.evex
&& vex
.b
15644 && (bytemode
== x_mode
15645 || bytemode
== xmmq_mode
15646 || bytemode
== evex_half_bcst_xmmq_mode
))
15649 || bytemode
== xmmq_mode
15650 || bytemode
== evex_half_bcst_xmmq_mode
)
15652 switch (vex
.length
)
15655 oappend ("{1to2}");
15658 oappend ("{1to4}");
15661 oappend ("{1to8}");
15669 switch (vex
.length
)
15672 oappend ("{1to4}");
15675 oappend ("{1to8}");
15678 oappend ("{1to16}");
15688 OP_E (int bytemode
, int sizeflag
)
15690 /* Skip mod/rm byte. */
15694 if (modrm
.mod
== 3)
15695 OP_E_register (bytemode
, sizeflag
);
15697 OP_E_memory (bytemode
, sizeflag
);
15701 OP_G (int bytemode
, int sizeflag
)
15712 oappend (names8rex
[modrm
.reg
+ add
]);
15714 oappend (names8
[modrm
.reg
+ add
]);
15717 oappend (names16
[modrm
.reg
+ add
]);
15722 oappend (names32
[modrm
.reg
+ add
]);
15725 oappend (names64
[modrm
.reg
+ add
]);
15728 oappend (names_bnd
[modrm
.reg
]);
15735 case dqw_swap_mode
:
15738 oappend (names64
[modrm
.reg
+ add
]);
15741 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
15742 oappend (names32
[modrm
.reg
+ add
]);
15744 oappend (names16
[modrm
.reg
+ add
]);
15745 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15749 if (address_mode
== mode_64bit
)
15750 oappend (names64
[modrm
.reg
+ add
]);
15752 oappend (names32
[modrm
.reg
+ add
]);
15756 oappend (names_mask
[modrm
.reg
+ add
]);
15759 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15772 FETCH_DATA (the_info
, codep
+ 8);
15773 a
= *codep
++ & 0xff;
15774 a
|= (*codep
++ & 0xff) << 8;
15775 a
|= (*codep
++ & 0xff) << 16;
15776 a
|= (*codep
++ & 0xffu
) << 24;
15777 b
= *codep
++ & 0xff;
15778 b
|= (*codep
++ & 0xff) << 8;
15779 b
|= (*codep
++ & 0xff) << 16;
15780 b
|= (*codep
++ & 0xffu
) << 24;
15781 x
= a
+ ((bfd_vma
) b
<< 32);
15789 static bfd_signed_vma
15792 bfd_signed_vma x
= 0;
15794 FETCH_DATA (the_info
, codep
+ 4);
15795 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15796 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15797 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15798 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15802 static bfd_signed_vma
15805 bfd_signed_vma x
= 0;
15807 FETCH_DATA (the_info
, codep
+ 4);
15808 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15809 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15810 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15811 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15813 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15823 FETCH_DATA (the_info
, codep
+ 2);
15824 x
= *codep
++ & 0xff;
15825 x
|= (*codep
++ & 0xff) << 8;
15830 set_op (bfd_vma op
, int riprel
)
15832 op_index
[op_ad
] = op_ad
;
15833 if (address_mode
== mode_64bit
)
15835 op_address
[op_ad
] = op
;
15836 op_riprel
[op_ad
] = riprel
;
15840 /* Mask to get a 32-bit address. */
15841 op_address
[op_ad
] = op
& 0xffffffff;
15842 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15847 OP_REG (int code
, int sizeflag
)
15854 case es_reg
: case ss_reg
: case cs_reg
:
15855 case ds_reg
: case fs_reg
: case gs_reg
:
15856 oappend (names_seg
[code
- es_reg
]);
15868 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15869 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15870 s
= names16
[code
- ax_reg
+ add
];
15872 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15873 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15876 s
= names8rex
[code
- al_reg
+ add
];
15878 s
= names8
[code
- al_reg
];
15880 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15881 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15882 if (address_mode
== mode_64bit
15883 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15885 s
= names64
[code
- rAX_reg
+ add
];
15888 code
+= eAX_reg
- rAX_reg
;
15889 /* Fall through. */
15890 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15891 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15894 s
= names64
[code
- eAX_reg
+ add
];
15897 if (sizeflag
& DFLAG
)
15898 s
= names32
[code
- eAX_reg
+ add
];
15900 s
= names16
[code
- eAX_reg
+ add
];
15901 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15905 s
= INTERNAL_DISASSEMBLER_ERROR
;
15912 OP_IMREG (int code
, int sizeflag
)
15924 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15925 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15926 s
= names16
[code
- ax_reg
];
15928 case es_reg
: case ss_reg
: case cs_reg
:
15929 case ds_reg
: case fs_reg
: case gs_reg
:
15930 s
= names_seg
[code
- es_reg
];
15932 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15933 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15936 s
= names8rex
[code
- al_reg
];
15938 s
= names8
[code
- al_reg
];
15940 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15941 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15944 s
= names64
[code
- eAX_reg
];
15947 if (sizeflag
& DFLAG
)
15948 s
= names32
[code
- eAX_reg
];
15950 s
= names16
[code
- eAX_reg
];
15951 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15954 case z_mode_ax_reg
:
15955 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
15959 if (!(rex
& REX_W
))
15960 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15963 s
= INTERNAL_DISASSEMBLER_ERROR
;
15970 OP_I (int bytemode
, int sizeflag
)
15973 bfd_signed_vma mask
= -1;
15978 FETCH_DATA (the_info
, codep
+ 1);
15983 if (address_mode
== mode_64bit
)
15988 /* Fall through. */
15995 if (sizeflag
& DFLAG
)
16005 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16017 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16022 scratchbuf
[0] = '$';
16023 print_operand_value (scratchbuf
+ 1, 1, op
);
16024 oappend_maybe_intel (scratchbuf
);
16025 scratchbuf
[0] = '\0';
16029 OP_I64 (int bytemode
, int sizeflag
)
16032 bfd_signed_vma mask
= -1;
16034 if (address_mode
!= mode_64bit
)
16036 OP_I (bytemode
, sizeflag
);
16043 FETCH_DATA (the_info
, codep
+ 1);
16053 if (sizeflag
& DFLAG
)
16063 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16071 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16076 scratchbuf
[0] = '$';
16077 print_operand_value (scratchbuf
+ 1, 1, op
);
16078 oappend_maybe_intel (scratchbuf
);
16079 scratchbuf
[0] = '\0';
16083 OP_sI (int bytemode
, int sizeflag
)
16091 FETCH_DATA (the_info
, codep
+ 1);
16093 if ((op
& 0x80) != 0)
16095 if (bytemode
== b_T_mode
)
16097 if (address_mode
!= mode_64bit
16098 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
16100 /* The operand-size prefix is overridden by a REX prefix. */
16101 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16109 if (!(rex
& REX_W
))
16111 if (sizeflag
& DFLAG
)
16119 /* The operand-size prefix is overridden by a REX prefix. */
16120 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16126 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16130 scratchbuf
[0] = '$';
16131 print_operand_value (scratchbuf
+ 1, 1, op
);
16132 oappend_maybe_intel (scratchbuf
);
16136 OP_J (int bytemode
, int sizeflag
)
16140 bfd_vma segment
= 0;
16145 FETCH_DATA (the_info
, codep
+ 1);
16147 if ((disp
& 0x80) != 0)
16151 if (isa64
== amd64
)
16153 if ((sizeflag
& DFLAG
)
16154 || (address_mode
== mode_64bit
16155 && (isa64
!= amd64
|| (rex
& REX_W
))))
16160 if ((disp
& 0x8000) != 0)
16162 /* In 16bit mode, address is wrapped around at 64k within
16163 the same segment. Otherwise, a data16 prefix on a jump
16164 instruction means that the pc is masked to 16 bits after
16165 the displacement is added! */
16167 if ((prefixes
& PREFIX_DATA
) == 0)
16168 segment
= ((start_pc
+ (codep
- start_codep
))
16169 & ~((bfd_vma
) 0xffff));
16171 if (address_mode
!= mode_64bit
16172 || (isa64
== amd64
&& !(rex
& REX_W
)))
16173 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16176 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16179 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
16181 print_operand_value (scratchbuf
, 1, disp
);
16182 oappend (scratchbuf
);
16186 OP_SEG (int bytemode
, int sizeflag
)
16188 if (bytemode
== w_mode
)
16189 oappend (names_seg
[modrm
.reg
]);
16191 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
16195 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
16199 if (sizeflag
& DFLAG
)
16209 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16211 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
16213 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
16214 oappend (scratchbuf
);
16218 OP_OFF (int bytemode
, int sizeflag
)
16222 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16223 intel_operand_size (bytemode
, sizeflag
);
16226 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16233 if (!active_seg_prefix
)
16235 oappend (names_seg
[ds_reg
- es_reg
]);
16239 print_operand_value (scratchbuf
, 1, off
);
16240 oappend (scratchbuf
);
16244 OP_OFF64 (int bytemode
, int sizeflag
)
16248 if (address_mode
!= mode_64bit
16249 || (prefixes
& PREFIX_ADDR
))
16251 OP_OFF (bytemode
, sizeflag
);
16255 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16256 intel_operand_size (bytemode
, sizeflag
);
16263 if (!active_seg_prefix
)
16265 oappend (names_seg
[ds_reg
- es_reg
]);
16269 print_operand_value (scratchbuf
, 1, off
);
16270 oappend (scratchbuf
);
16274 ptr_reg (int code
, int sizeflag
)
16278 *obufp
++ = open_char
;
16279 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
16280 if (address_mode
== mode_64bit
)
16282 if (!(sizeflag
& AFLAG
))
16283 s
= names32
[code
- eAX_reg
];
16285 s
= names64
[code
- eAX_reg
];
16287 else if (sizeflag
& AFLAG
)
16288 s
= names32
[code
- eAX_reg
];
16290 s
= names16
[code
- eAX_reg
];
16292 *obufp
++ = close_char
;
16297 OP_ESreg (int code
, int sizeflag
)
16303 case 0x6d: /* insw/insl */
16304 intel_operand_size (z_mode
, sizeflag
);
16306 case 0xa5: /* movsw/movsl/movsq */
16307 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16308 case 0xab: /* stosw/stosl */
16309 case 0xaf: /* scasw/scasl */
16310 intel_operand_size (v_mode
, sizeflag
);
16313 intel_operand_size (b_mode
, sizeflag
);
16316 oappend_maybe_intel ("%es:");
16317 ptr_reg (code
, sizeflag
);
16321 OP_DSreg (int code
, int sizeflag
)
16327 case 0x6f: /* outsw/outsl */
16328 intel_operand_size (z_mode
, sizeflag
);
16330 case 0xa5: /* movsw/movsl/movsq */
16331 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16332 case 0xad: /* lodsw/lodsl/lodsq */
16333 intel_operand_size (v_mode
, sizeflag
);
16336 intel_operand_size (b_mode
, sizeflag
);
16339 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16340 default segment register DS is printed. */
16341 if (!active_seg_prefix
)
16342 active_seg_prefix
= PREFIX_DS
;
16344 ptr_reg (code
, sizeflag
);
16348 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16356 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
16358 all_prefixes
[last_lock_prefix
] = 0;
16359 used_prefixes
|= PREFIX_LOCK
;
16364 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
16365 oappend_maybe_intel (scratchbuf
);
16369 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16378 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
16380 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
16381 oappend (scratchbuf
);
16385 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16387 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
16388 oappend_maybe_intel (scratchbuf
);
16392 OP_R (int bytemode
, int sizeflag
)
16394 /* Skip mod/rm byte. */
16397 OP_E_register (bytemode
, sizeflag
);
16401 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16403 int reg
= modrm
.reg
;
16404 const char **names
;
16406 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16407 if (prefixes
& PREFIX_DATA
)
16416 oappend (names
[reg
]);
16420 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16422 int reg
= modrm
.reg
;
16423 const char **names
;
16435 && bytemode
!= xmm_mode
16436 && bytemode
!= xmmq_mode
16437 && bytemode
!= evex_half_bcst_xmmq_mode
16438 && bytemode
!= ymm_mode
16439 && bytemode
!= scalar_mode
)
16441 switch (vex
.length
)
16448 || (bytemode
!= vex_vsib_q_w_dq_mode
16449 && bytemode
!= vex_vsib_q_w_d_mode
))
16461 else if (bytemode
== xmmq_mode
16462 || bytemode
== evex_half_bcst_xmmq_mode
)
16464 switch (vex
.length
)
16477 else if (bytemode
== ymm_mode
)
16481 oappend (names
[reg
]);
16485 OP_EM (int bytemode
, int sizeflag
)
16488 const char **names
;
16490 if (modrm
.mod
!= 3)
16493 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16495 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16496 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16498 OP_E (bytemode
, sizeflag
);
16502 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
16505 /* Skip mod/rm byte. */
16508 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16510 if (prefixes
& PREFIX_DATA
)
16519 oappend (names
[reg
]);
16522 /* cvt* are the only instructions in sse2 which have
16523 both SSE and MMX operands and also have 0x66 prefix
16524 in their opcode. 0x66 was originally used to differentiate
16525 between SSE and MMX instruction(operands). So we have to handle the
16526 cvt* separately using OP_EMC and OP_MXC */
16528 OP_EMC (int bytemode
, int sizeflag
)
16530 if (modrm
.mod
!= 3)
16532 if (intel_syntax
&& bytemode
== v_mode
)
16534 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16535 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16537 OP_E (bytemode
, sizeflag
);
16541 /* Skip mod/rm byte. */
16544 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16545 oappend (names_mm
[modrm
.rm
]);
16549 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16551 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16552 oappend (names_mm
[modrm
.reg
]);
16556 OP_EX (int bytemode
, int sizeflag
)
16559 const char **names
;
16561 /* Skip mod/rm byte. */
16565 if (modrm
.mod
!= 3)
16567 OP_E_memory (bytemode
, sizeflag
);
16582 if ((sizeflag
& SUFFIX_ALWAYS
)
16583 && (bytemode
== x_swap_mode
16584 || bytemode
== d_swap_mode
16585 || bytemode
== dqw_swap_mode
16586 || bytemode
== d_scalar_swap_mode
16587 || bytemode
== q_swap_mode
16588 || bytemode
== q_scalar_swap_mode
))
16592 && bytemode
!= xmm_mode
16593 && bytemode
!= xmmdw_mode
16594 && bytemode
!= xmmqd_mode
16595 && bytemode
!= xmm_mb_mode
16596 && bytemode
!= xmm_mw_mode
16597 && bytemode
!= xmm_md_mode
16598 && bytemode
!= xmm_mq_mode
16599 && bytemode
!= xmm_mdq_mode
16600 && bytemode
!= xmmq_mode
16601 && bytemode
!= evex_half_bcst_xmmq_mode
16602 && bytemode
!= ymm_mode
16603 && bytemode
!= d_scalar_mode
16604 && bytemode
!= d_scalar_swap_mode
16605 && bytemode
!= q_scalar_mode
16606 && bytemode
!= q_scalar_swap_mode
16607 && bytemode
!= vex_scalar_w_dq_mode
)
16609 switch (vex
.length
)
16624 else if (bytemode
== xmmq_mode
16625 || bytemode
== evex_half_bcst_xmmq_mode
)
16627 switch (vex
.length
)
16640 else if (bytemode
== ymm_mode
)
16644 oappend (names
[reg
]);
16648 OP_MS (int bytemode
, int sizeflag
)
16650 if (modrm
.mod
== 3)
16651 OP_EM (bytemode
, sizeflag
);
16657 OP_XS (int bytemode
, int sizeflag
)
16659 if (modrm
.mod
== 3)
16660 OP_EX (bytemode
, sizeflag
);
16666 OP_M (int bytemode
, int sizeflag
)
16668 if (modrm
.mod
== 3)
16669 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16672 OP_E (bytemode
, sizeflag
);
16676 OP_0f07 (int bytemode
, int sizeflag
)
16678 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
16681 OP_E (bytemode
, sizeflag
);
16684 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16685 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16688 NOP_Fixup1 (int bytemode
, int sizeflag
)
16690 if ((prefixes
& PREFIX_DATA
) != 0
16693 && address_mode
== mode_64bit
))
16694 OP_REG (bytemode
, sizeflag
);
16696 strcpy (obuf
, "nop");
16700 NOP_Fixup2 (int bytemode
, int sizeflag
)
16702 if ((prefixes
& PREFIX_DATA
) != 0
16705 && address_mode
== mode_64bit
))
16706 OP_IMREG (bytemode
, sizeflag
);
16709 static const char *const Suffix3DNow
[] = {
16710 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16711 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16712 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16713 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16714 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16715 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16716 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16717 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16718 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16719 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16720 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16721 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16722 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16723 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16724 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16725 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16726 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16727 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16728 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16729 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16730 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16731 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16732 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16733 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16734 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16735 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16736 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16737 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16738 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16739 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16740 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16741 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16742 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16743 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16744 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16745 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16746 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16747 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16748 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16749 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16750 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16751 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16752 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16753 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16754 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16755 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16756 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16757 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16758 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16759 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16760 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16761 /* CC */ NULL
, NULL
, NULL
, NULL
,
16762 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16763 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16764 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16765 /* DC */ NULL
, NULL
, NULL
, NULL
,
16766 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16767 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16768 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16769 /* EC */ NULL
, NULL
, NULL
, NULL
,
16770 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16771 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16772 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16773 /* FC */ NULL
, NULL
, NULL
, NULL
,
16777 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16779 const char *mnemonic
;
16781 FETCH_DATA (the_info
, codep
+ 1);
16782 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16783 place where an 8-bit immediate would normally go. ie. the last
16784 byte of the instruction. */
16785 obufp
= mnemonicendp
;
16786 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16788 oappend (mnemonic
);
16791 /* Since a variable sized modrm/sib chunk is between the start
16792 of the opcode (0x0f0f) and the opcode suffix, we need to do
16793 all the modrm processing first, and don't know until now that
16794 we have a bad opcode. This necessitates some cleaning up. */
16795 op_out
[0][0] = '\0';
16796 op_out
[1][0] = '\0';
16799 mnemonicendp
= obufp
;
16802 static struct op simd_cmp_op
[] =
16804 { STRING_COMMA_LEN ("eq") },
16805 { STRING_COMMA_LEN ("lt") },
16806 { STRING_COMMA_LEN ("le") },
16807 { STRING_COMMA_LEN ("unord") },
16808 { STRING_COMMA_LEN ("neq") },
16809 { STRING_COMMA_LEN ("nlt") },
16810 { STRING_COMMA_LEN ("nle") },
16811 { STRING_COMMA_LEN ("ord") }
16815 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16817 unsigned int cmp_type
;
16819 FETCH_DATA (the_info
, codep
+ 1);
16820 cmp_type
= *codep
++ & 0xff;
16821 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16824 char *p
= mnemonicendp
- 2;
16828 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16829 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16833 /* We have a reserved extension byte. Output it directly. */
16834 scratchbuf
[0] = '$';
16835 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16836 oappend_maybe_intel (scratchbuf
);
16837 scratchbuf
[0] = '\0';
16842 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
16843 int sizeflag ATTRIBUTE_UNUSED
)
16845 /* mwaitx %eax,%ecx,%ebx */
16848 const char **names
= (address_mode
== mode_64bit
16849 ? names64
: names32
);
16850 strcpy (op_out
[0], names
[0]);
16851 strcpy (op_out
[1], names
[1]);
16852 strcpy (op_out
[2], names
[3]);
16853 two_source_ops
= 1;
16855 /* Skip mod/rm byte. */
16861 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
16862 int sizeflag ATTRIBUTE_UNUSED
)
16864 /* mwait %eax,%ecx */
16867 const char **names
= (address_mode
== mode_64bit
16868 ? names64
: names32
);
16869 strcpy (op_out
[0], names
[0]);
16870 strcpy (op_out
[1], names
[1]);
16871 two_source_ops
= 1;
16873 /* Skip mod/rm byte. */
16879 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16880 int sizeflag ATTRIBUTE_UNUSED
)
16882 /* monitor %eax,%ecx,%edx" */
16885 const char **op1_names
;
16886 const char **names
= (address_mode
== mode_64bit
16887 ? names64
: names32
);
16889 if (!(prefixes
& PREFIX_ADDR
))
16890 op1_names
= (address_mode
== mode_16bit
16891 ? names16
: names
);
16894 /* Remove "addr16/addr32". */
16895 all_prefixes
[last_addr_prefix
] = 0;
16896 op1_names
= (address_mode
!= mode_32bit
16897 ? names32
: names16
);
16898 used_prefixes
|= PREFIX_ADDR
;
16900 strcpy (op_out
[0], op1_names
[0]);
16901 strcpy (op_out
[1], names
[1]);
16902 strcpy (op_out
[2], names
[2]);
16903 two_source_ops
= 1;
16905 /* Skip mod/rm byte. */
16913 /* Throw away prefixes and 1st. opcode byte. */
16914 codep
= insn_codep
+ 1;
16919 REP_Fixup (int bytemode
, int sizeflag
)
16921 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16923 if (prefixes
& PREFIX_REPZ
)
16924 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16931 OP_IMREG (bytemode
, sizeflag
);
16934 OP_ESreg (bytemode
, sizeflag
);
16937 OP_DSreg (bytemode
, sizeflag
);
16945 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16949 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16951 if (prefixes
& PREFIX_REPNZ
)
16952 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16955 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16956 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16960 HLE_Fixup1 (int bytemode
, int sizeflag
)
16963 && (prefixes
& PREFIX_LOCK
) != 0)
16965 if (prefixes
& PREFIX_REPZ
)
16966 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16967 if (prefixes
& PREFIX_REPNZ
)
16968 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16971 OP_E (bytemode
, sizeflag
);
16974 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16975 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16979 HLE_Fixup2 (int bytemode
, int sizeflag
)
16981 if (modrm
.mod
!= 3)
16983 if (prefixes
& PREFIX_REPZ
)
16984 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16985 if (prefixes
& PREFIX_REPNZ
)
16986 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16989 OP_E (bytemode
, sizeflag
);
16992 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16993 "xrelease" for memory operand. No check for LOCK prefix. */
16996 HLE_Fixup3 (int bytemode
, int sizeflag
)
16999 && last_repz_prefix
> last_repnz_prefix
17000 && (prefixes
& PREFIX_REPZ
) != 0)
17001 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
17003 OP_E (bytemode
, sizeflag
);
17007 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
17012 /* Change cmpxchg8b to cmpxchg16b. */
17013 char *p
= mnemonicendp
- 2;
17014 mnemonicendp
= stpcpy (p
, "16b");
17017 else if ((prefixes
& PREFIX_LOCK
) != 0)
17019 if (prefixes
& PREFIX_REPZ
)
17020 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
17021 if (prefixes
& PREFIX_REPNZ
)
17022 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
17025 OP_M (bytemode
, sizeflag
);
17029 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
17031 const char **names
;
17035 switch (vex
.length
)
17049 oappend (names
[reg
]);
17053 CRC32_Fixup (int bytemode
, int sizeflag
)
17055 /* Add proper suffix to "crc32". */
17056 char *p
= mnemonicendp
;
17075 if (sizeflag
& DFLAG
)
17079 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17083 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17090 if (modrm
.mod
== 3)
17094 /* Skip mod/rm byte. */
17099 add
= (rex
& REX_B
) ? 8 : 0;
17100 if (bytemode
== b_mode
)
17104 oappend (names8rex
[modrm
.rm
+ add
]);
17106 oappend (names8
[modrm
.rm
+ add
]);
17112 oappend (names64
[modrm
.rm
+ add
]);
17113 else if ((prefixes
& PREFIX_DATA
))
17114 oappend (names16
[modrm
.rm
+ add
]);
17116 oappend (names32
[modrm
.rm
+ add
]);
17120 OP_E (bytemode
, sizeflag
);
17124 FXSAVE_Fixup (int bytemode
, int sizeflag
)
17126 /* Add proper suffix to "fxsave" and "fxrstor". */
17130 char *p
= mnemonicendp
;
17136 OP_M (bytemode
, sizeflag
);
17139 /* Display the destination register operand for instructions with
17143 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17146 const char **names
;
17154 reg
= vex
.register_specifier
;
17161 if (bytemode
== vex_scalar_mode
)
17163 oappend (names_xmm
[reg
]);
17167 switch (vex
.length
)
17174 case vex_vsib_q_w_dq_mode
:
17175 case vex_vsib_q_w_d_mode
:
17186 names
= names_mask
;
17200 case vex_vsib_q_w_dq_mode
:
17201 case vex_vsib_q_w_d_mode
:
17202 names
= vex
.w
? names_ymm
: names_xmm
;
17206 names
= names_mask
;
17220 oappend (names
[reg
]);
17223 /* Get the VEX immediate byte without moving codep. */
17225 static unsigned char
17226 get_vex_imm8 (int sizeflag
, int opnum
)
17228 int bytes_before_imm
= 0;
17230 if (modrm
.mod
!= 3)
17232 /* There are SIB/displacement bytes. */
17233 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
17235 /* 32/64 bit address mode */
17236 int base
= modrm
.rm
;
17238 /* Check SIB byte. */
17241 FETCH_DATA (the_info
, codep
+ 1);
17243 /* When decoding the third source, don't increase
17244 bytes_before_imm as this has already been incremented
17245 by one in OP_E_memory while decoding the second
17248 bytes_before_imm
++;
17251 /* Don't increase bytes_before_imm when decoding the third source,
17252 it has already been incremented by OP_E_memory while decoding
17253 the second source operand. */
17259 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17260 SIB == 5, there is a 4 byte displacement. */
17262 /* No displacement. */
17265 /* 4 byte displacement. */
17266 bytes_before_imm
+= 4;
17269 /* 1 byte displacement. */
17270 bytes_before_imm
++;
17277 /* 16 bit address mode */
17278 /* Don't increase bytes_before_imm when decoding the third source,
17279 it has already been incremented by OP_E_memory while decoding
17280 the second source operand. */
17286 /* When modrm.rm == 6, there is a 2 byte displacement. */
17288 /* No displacement. */
17291 /* 2 byte displacement. */
17292 bytes_before_imm
+= 2;
17295 /* 1 byte displacement: when decoding the third source,
17296 don't increase bytes_before_imm as this has already
17297 been incremented by one in OP_E_memory while decoding
17298 the second source operand. */
17300 bytes_before_imm
++;
17308 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
17309 return codep
[bytes_before_imm
];
17313 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
17315 const char **names
;
17317 if (reg
== -1 && modrm
.mod
!= 3)
17319 OP_E_memory (bytemode
, sizeflag
);
17331 else if (reg
> 7 && address_mode
!= mode_64bit
)
17335 switch (vex
.length
)
17346 oappend (names
[reg
]);
17350 OP_EX_VexImmW (int bytemode
, int sizeflag
)
17353 static unsigned char vex_imm8
;
17355 if (vex_w_done
== 0)
17359 /* Skip mod/rm byte. */
17363 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
17366 reg
= vex_imm8
>> 4;
17368 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17370 else if (vex_w_done
== 1)
17375 reg
= vex_imm8
>> 4;
17377 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17381 /* Output the imm8 directly. */
17382 scratchbuf
[0] = '$';
17383 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
17384 oappend_maybe_intel (scratchbuf
);
17385 scratchbuf
[0] = '\0';
17391 OP_Vex_2src (int bytemode
, int sizeflag
)
17393 if (modrm
.mod
== 3)
17395 int reg
= modrm
.rm
;
17399 oappend (names_xmm
[reg
]);
17404 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
17406 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
17407 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17409 OP_E (bytemode
, sizeflag
);
17414 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
17416 if (modrm
.mod
== 3)
17418 /* Skip mod/rm byte. */
17424 oappend (names_xmm
[vex
.register_specifier
]);
17426 OP_Vex_2src (bytemode
, sizeflag
);
17430 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
17433 OP_Vex_2src (bytemode
, sizeflag
);
17435 oappend (names_xmm
[vex
.register_specifier
]);
17439 OP_EX_VexW (int bytemode
, int sizeflag
)
17447 /* Skip mod/rm byte. */
17452 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
17457 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
17460 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17464 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17465 int sizeflag ATTRIBUTE_UNUSED
)
17467 /* Skip the immediate byte and check for invalid bits. */
17468 FETCH_DATA (the_info
, codep
+ 1);
17469 if (*codep
++ & 0xf)
17474 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17477 const char **names
;
17479 FETCH_DATA (the_info
, codep
+ 1);
17482 if (bytemode
!= x_mode
)
17489 if (reg
> 7 && address_mode
!= mode_64bit
)
17492 switch (vex
.length
)
17503 oappend (names
[reg
]);
17507 OP_XMM_VexW (int bytemode
, int sizeflag
)
17509 /* Turn off the REX.W bit since it is used for swapping operands
17512 OP_XMM (bytemode
, sizeflag
);
17516 OP_EX_Vex (int bytemode
, int sizeflag
)
17518 if (modrm
.mod
!= 3)
17520 if (vex
.register_specifier
!= 0)
17524 OP_EX (bytemode
, sizeflag
);
17528 OP_XMM_Vex (int bytemode
, int sizeflag
)
17530 if (modrm
.mod
!= 3)
17532 if (vex
.register_specifier
!= 0)
17536 OP_XMM (bytemode
, sizeflag
);
17540 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17542 switch (vex
.length
)
17545 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
17548 mnemonicendp
= stpcpy (obuf
, "vzeroall");
17555 static struct op vex_cmp_op
[] =
17557 { STRING_COMMA_LEN ("eq") },
17558 { STRING_COMMA_LEN ("lt") },
17559 { STRING_COMMA_LEN ("le") },
17560 { STRING_COMMA_LEN ("unord") },
17561 { STRING_COMMA_LEN ("neq") },
17562 { STRING_COMMA_LEN ("nlt") },
17563 { STRING_COMMA_LEN ("nle") },
17564 { STRING_COMMA_LEN ("ord") },
17565 { STRING_COMMA_LEN ("eq_uq") },
17566 { STRING_COMMA_LEN ("nge") },
17567 { STRING_COMMA_LEN ("ngt") },
17568 { STRING_COMMA_LEN ("false") },
17569 { STRING_COMMA_LEN ("neq_oq") },
17570 { STRING_COMMA_LEN ("ge") },
17571 { STRING_COMMA_LEN ("gt") },
17572 { STRING_COMMA_LEN ("true") },
17573 { STRING_COMMA_LEN ("eq_os") },
17574 { STRING_COMMA_LEN ("lt_oq") },
17575 { STRING_COMMA_LEN ("le_oq") },
17576 { STRING_COMMA_LEN ("unord_s") },
17577 { STRING_COMMA_LEN ("neq_us") },
17578 { STRING_COMMA_LEN ("nlt_uq") },
17579 { STRING_COMMA_LEN ("nle_uq") },
17580 { STRING_COMMA_LEN ("ord_s") },
17581 { STRING_COMMA_LEN ("eq_us") },
17582 { STRING_COMMA_LEN ("nge_uq") },
17583 { STRING_COMMA_LEN ("ngt_uq") },
17584 { STRING_COMMA_LEN ("false_os") },
17585 { STRING_COMMA_LEN ("neq_os") },
17586 { STRING_COMMA_LEN ("ge_oq") },
17587 { STRING_COMMA_LEN ("gt_oq") },
17588 { STRING_COMMA_LEN ("true_us") },
17592 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17594 unsigned int cmp_type
;
17596 FETCH_DATA (the_info
, codep
+ 1);
17597 cmp_type
= *codep
++ & 0xff;
17598 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
17601 char *p
= mnemonicendp
- 2;
17605 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
17606 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
17610 /* We have a reserved extension byte. Output it directly. */
17611 scratchbuf
[0] = '$';
17612 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17613 oappend_maybe_intel (scratchbuf
);
17614 scratchbuf
[0] = '\0';
17619 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17620 int sizeflag ATTRIBUTE_UNUSED
)
17622 unsigned int cmp_type
;
17627 FETCH_DATA (the_info
, codep
+ 1);
17628 cmp_type
= *codep
++ & 0xff;
17629 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17630 If it's the case, print suffix, otherwise - print the immediate. */
17631 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
17636 char *p
= mnemonicendp
- 2;
17638 /* vpcmp* can have both one- and two-lettered suffix. */
17652 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
17653 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
17657 /* We have a reserved extension byte. Output it directly. */
17658 scratchbuf
[0] = '$';
17659 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17660 oappend_maybe_intel (scratchbuf
);
17661 scratchbuf
[0] = '\0';
17665 static const struct op pclmul_op
[] =
17667 { STRING_COMMA_LEN ("lql") },
17668 { STRING_COMMA_LEN ("hql") },
17669 { STRING_COMMA_LEN ("lqh") },
17670 { STRING_COMMA_LEN ("hqh") }
17674 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17675 int sizeflag ATTRIBUTE_UNUSED
)
17677 unsigned int pclmul_type
;
17679 FETCH_DATA (the_info
, codep
+ 1);
17680 pclmul_type
= *codep
++ & 0xff;
17681 switch (pclmul_type
)
17692 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
17695 char *p
= mnemonicendp
- 3;
17700 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
17701 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
17705 /* We have a reserved extension byte. Output it directly. */
17706 scratchbuf
[0] = '$';
17707 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
17708 oappend_maybe_intel (scratchbuf
);
17709 scratchbuf
[0] = '\0';
17714 MOVBE_Fixup (int bytemode
, int sizeflag
)
17716 /* Add proper suffix to "movbe". */
17717 char *p
= mnemonicendp
;
17726 if (sizeflag
& SUFFIX_ALWAYS
)
17732 if (sizeflag
& DFLAG
)
17736 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17741 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17748 OP_M (bytemode
, sizeflag
);
17752 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17755 const char **names
;
17757 /* Skip mod/rm byte. */
17771 oappend (names
[reg
]);
17775 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17777 const char **names
;
17784 oappend (names
[vex
.register_specifier
]);
17788 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17791 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
17795 if ((rex
& REX_R
) != 0 || !vex
.r
)
17801 oappend (names_mask
[modrm
.reg
]);
17805 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17808 || (bytemode
!= evex_rounding_mode
17809 && bytemode
!= evex_sae_mode
))
17811 if (modrm
.mod
== 3 && vex
.b
)
17814 case evex_rounding_mode
:
17815 oappend (names_rounding
[vex
.ll
]);
17817 case evex_sae_mode
: