1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2017 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void NOTRACK_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void PCMPESTR_Fixup (int, int);
122 static void OP_LWPCB_E (int, int);
123 static void OP_LWP_E (int, int);
124 static void OP_Vex_2src_1 (int, int);
125 static void OP_Vex_2src_2 (int, int);
127 static void MOVBE_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte
*max_fetched
;
134 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
137 OPCODES_SIGJMP_BUF bailout
;
147 enum address_mode address_mode
;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* REX bits in original REX prefix ignored. */
157 static int rex_ignored
;
158 /* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162 #define USED_REX(value) \
167 rex_used |= (value) | REX_OPCODE; \
170 rex_used |= REX_OPCODE; \
173 /* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175 static int used_prefixes
;
177 /* Flags stored in PREFIXES. */
178 #define PREFIX_REPZ 1
179 #define PREFIX_REPNZ 2
180 #define PREFIX_LOCK 4
182 #define PREFIX_SS 0x10
183 #define PREFIX_DS 0x20
184 #define PREFIX_ES 0x40
185 #define PREFIX_FS 0x80
186 #define PREFIX_GS 0x100
187 #define PREFIX_DATA 0x200
188 #define PREFIX_ADDR 0x400
189 #define PREFIX_FWAIT 0x800
191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
194 #define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
199 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
202 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
203 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
205 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
206 status
= (*info
->read_memory_func
) (start
,
208 addr
- priv
->max_fetched
,
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
218 if (priv
->max_fetched
== priv
->the_buffer
)
219 (*info
->memory_error_func
) (status
, start
, info
);
220 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
223 priv
->max_fetched
= addr
;
227 /* Possible values for prefix requirement. */
228 #define PREFIX_IGNORED_SHIFT 16
229 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
235 /* Opcode prefixes. */
236 #define PREFIX_OPCODE (PREFIX_REPZ \
240 /* Prefixes ignored. */
241 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
245 #define XX { NULL, 0 }
246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
248 #define Eb { OP_E, b_mode }
249 #define Ebnd { OP_E, bnd_mode }
250 #define EbS { OP_E, b_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Ev_bnd { OP_E, v_bnd_mode }
253 #define EvS { OP_E, v_swap_mode }
254 #define Ed { OP_E, d_mode }
255 #define Edq { OP_E, dq_mode }
256 #define Edqw { OP_E, dqw_mode }
257 #define Edqb { OP_E, dqb_mode }
258 #define Edb { OP_E, db_mode }
259 #define Edw { OP_E, dw_mode }
260 #define Edqd { OP_E, dqd_mode }
261 #define Eq { OP_E, q_mode }
262 #define indirEv { OP_indirE, indir_v_mode }
263 #define indirEp { OP_indirE, f_mode }
264 #define stackEv { OP_E, stack_v_mode }
265 #define Em { OP_E, m_mode }
266 #define Ew { OP_E, w_mode }
267 #define M { OP_M, 0 } /* lea, lgdt, etc. */
268 #define Ma { OP_M, a_mode }
269 #define Mb { OP_M, b_mode }
270 #define Md { OP_M, d_mode }
271 #define Mo { OP_M, o_mode }
272 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
273 #define Mq { OP_M, q_mode }
274 #define Mx { OP_M, x_mode }
275 #define Mxmm { OP_M, xmm_mode }
276 #define Gb { OP_G, b_mode }
277 #define Gbnd { OP_G, bnd_mode }
278 #define Gv { OP_G, v_mode }
279 #define Gd { OP_G, d_mode }
280 #define Gdq { OP_G, dq_mode }
281 #define Gm { OP_G, m_mode }
282 #define Gw { OP_G, w_mode }
283 #define Rd { OP_R, d_mode }
284 #define Rdq { OP_R, dq_mode }
285 #define Rm { OP_R, m_mode }
286 #define Ib { OP_I, b_mode }
287 #define sIb { OP_sI, b_mode } /* sign extened byte */
288 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
289 #define Iv { OP_I, v_mode }
290 #define sIv { OP_sI, v_mode }
291 #define Iq { OP_I, q_mode }
292 #define Iv64 { OP_I64, v_mode }
293 #define Iw { OP_I, w_mode }
294 #define I1 { OP_I, const_1_mode }
295 #define Jb { OP_J, b_mode }
296 #define Jv { OP_J, v_mode }
297 #define Cm { OP_C, m_mode }
298 #define Dm { OP_D, m_mode }
299 #define Td { OP_T, d_mode }
300 #define Skip_MODRM { OP_Skip_MODRM, 0 }
302 #define RMeAX { OP_REG, eAX_reg }
303 #define RMeBX { OP_REG, eBX_reg }
304 #define RMeCX { OP_REG, eCX_reg }
305 #define RMeDX { OP_REG, eDX_reg }
306 #define RMeSP { OP_REG, eSP_reg }
307 #define RMeBP { OP_REG, eBP_reg }
308 #define RMeSI { OP_REG, eSI_reg }
309 #define RMeDI { OP_REG, eDI_reg }
310 #define RMrAX { OP_REG, rAX_reg }
311 #define RMrBX { OP_REG, rBX_reg }
312 #define RMrCX { OP_REG, rCX_reg }
313 #define RMrDX { OP_REG, rDX_reg }
314 #define RMrSP { OP_REG, rSP_reg }
315 #define RMrBP { OP_REG, rBP_reg }
316 #define RMrSI { OP_REG, rSI_reg }
317 #define RMrDI { OP_REG, rDI_reg }
318 #define RMAL { OP_REG, al_reg }
319 #define RMCL { OP_REG, cl_reg }
320 #define RMDL { OP_REG, dl_reg }
321 #define RMBL { OP_REG, bl_reg }
322 #define RMAH { OP_REG, ah_reg }
323 #define RMCH { OP_REG, ch_reg }
324 #define RMDH { OP_REG, dh_reg }
325 #define RMBH { OP_REG, bh_reg }
326 #define RMAX { OP_REG, ax_reg }
327 #define RMDX { OP_REG, dx_reg }
329 #define eAX { OP_IMREG, eAX_reg }
330 #define eBX { OP_IMREG, eBX_reg }
331 #define eCX { OP_IMREG, eCX_reg }
332 #define eDX { OP_IMREG, eDX_reg }
333 #define eSP { OP_IMREG, eSP_reg }
334 #define eBP { OP_IMREG, eBP_reg }
335 #define eSI { OP_IMREG, eSI_reg }
336 #define eDI { OP_IMREG, eDI_reg }
337 #define AL { OP_IMREG, al_reg }
338 #define CL { OP_IMREG, cl_reg }
339 #define DL { OP_IMREG, dl_reg }
340 #define BL { OP_IMREG, bl_reg }
341 #define AH { OP_IMREG, ah_reg }
342 #define CH { OP_IMREG, ch_reg }
343 #define DH { OP_IMREG, dh_reg }
344 #define BH { OP_IMREG, bh_reg }
345 #define AX { OP_IMREG, ax_reg }
346 #define DX { OP_IMREG, dx_reg }
347 #define zAX { OP_IMREG, z_mode_ax_reg }
348 #define indirDX { OP_IMREG, indir_dx_reg }
350 #define Sw { OP_SEG, w_mode }
351 #define Sv { OP_SEG, v_mode }
352 #define Ap { OP_DIR, 0 }
353 #define Ob { OP_OFF64, b_mode }
354 #define Ov { OP_OFF64, v_mode }
355 #define Xb { OP_DSreg, eSI_reg }
356 #define Xv { OP_DSreg, eSI_reg }
357 #define Xz { OP_DSreg, eSI_reg }
358 #define Yb { OP_ESreg, eDI_reg }
359 #define Yv { OP_ESreg, eDI_reg }
360 #define DSBX { OP_DSreg, eBX_reg }
362 #define es { OP_REG, es_reg }
363 #define ss { OP_REG, ss_reg }
364 #define cs { OP_REG, cs_reg }
365 #define ds { OP_REG, ds_reg }
366 #define fs { OP_REG, fs_reg }
367 #define gs { OP_REG, gs_reg }
369 #define MX { OP_MMX, 0 }
370 #define XM { OP_XMM, 0 }
371 #define XMScalar { OP_XMM, scalar_mode }
372 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
373 #define XMM { OP_XMM, xmm_mode }
374 #define XMxmmq { OP_XMM, xmmq_mode }
375 #define EM { OP_EM, v_mode }
376 #define EMS { OP_EM, v_swap_mode }
377 #define EMd { OP_EM, d_mode }
378 #define EMx { OP_EM, x_mode }
379 #define EXw { OP_EX, w_mode }
380 #define EXd { OP_EX, d_mode }
381 #define EXdScalar { OP_EX, d_scalar_mode }
382 #define EXdS { OP_EX, d_swap_mode }
383 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
384 #define EXq { OP_EX, q_mode }
385 #define EXqScalar { OP_EX, q_scalar_mode }
386 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
387 #define EXqS { OP_EX, q_swap_mode }
388 #define EXx { OP_EX, x_mode }
389 #define EXxS { OP_EX, x_swap_mode }
390 #define EXxmm { OP_EX, xmm_mode }
391 #define EXymm { OP_EX, ymm_mode }
392 #define EXxmmq { OP_EX, xmmq_mode }
393 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
394 #define EXxmm_mb { OP_EX, xmm_mb_mode }
395 #define EXxmm_mw { OP_EX, xmm_mw_mode }
396 #define EXxmm_md { OP_EX, xmm_md_mode }
397 #define EXxmm_mq { OP_EX, xmm_mq_mode }
398 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
399 #define EXxmmdw { OP_EX, xmmdw_mode }
400 #define EXxmmqd { OP_EX, xmmqd_mode }
401 #define EXymmq { OP_EX, ymmq_mode }
402 #define EXVexWdq { OP_EX, vex_w_dq_mode }
403 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
404 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
405 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
406 #define MS { OP_MS, v_mode }
407 #define XS { OP_XS, v_mode }
408 #define EMCq { OP_EMC, q_mode }
409 #define MXC { OP_MXC, 0 }
410 #define OPSUF { OP_3DNowSuffix, 0 }
411 #define CMP { CMP_Fixup, 0 }
412 #define XMM0 { XMM_Fixup, 0 }
413 #define FXSAVE { FXSAVE_Fixup, 0 }
414 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
415 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
417 #define Vex { OP_VEX, vex_mode }
418 #define VexScalar { OP_VEX, vex_scalar_mode }
419 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
420 #define Vex128 { OP_VEX, vex128_mode }
421 #define Vex256 { OP_VEX, vex256_mode }
422 #define VexGdq { OP_VEX, dq_mode }
423 #define VexI4 { VEXI4_Fixup, 0}
424 #define EXdVex { OP_EX_Vex, d_mode }
425 #define EXdVexS { OP_EX_Vex, d_swap_mode }
426 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
427 #define EXqVex { OP_EX_Vex, q_mode }
428 #define EXqVexS { OP_EX_Vex, q_swap_mode }
429 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
430 #define EXVexW { OP_EX_VexW, x_mode }
431 #define EXdVexW { OP_EX_VexW, d_mode }
432 #define EXqVexW { OP_EX_VexW, q_mode }
433 #define EXVexImmW { OP_EX_VexImmW, x_mode }
434 #define XMVex { OP_XMM_Vex, 0 }
435 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
436 #define XMVexW { OP_XMM_VexW, 0 }
437 #define XMVexI4 { OP_REG_VexI4, x_mode }
438 #define PCLMUL { PCLMUL_Fixup, 0 }
439 #define VZERO { VZERO_Fixup, 0 }
440 #define VCMP { VCMP_Fixup, 0 }
441 #define VPCMP { VPCMP_Fixup, 0 }
443 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
444 #define EXxEVexS { OP_Rounding, evex_sae_mode }
446 #define XMask { OP_Mask, mask_mode }
447 #define MaskG { OP_G, mask_mode }
448 #define MaskE { OP_E, mask_mode }
449 #define MaskBDE { OP_E, mask_bd_mode }
450 #define MaskR { OP_R, mask_mode }
451 #define MaskVex { OP_VEX, mask_mode }
453 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
454 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
455 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
456 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
458 /* Used handle "rep" prefix for string instructions. */
459 #define Xbr { REP_Fixup, eSI_reg }
460 #define Xvr { REP_Fixup, eSI_reg }
461 #define Ybr { REP_Fixup, eDI_reg }
462 #define Yvr { REP_Fixup, eDI_reg }
463 #define Yzr { REP_Fixup, eDI_reg }
464 #define indirDXr { REP_Fixup, indir_dx_reg }
465 #define ALr { REP_Fixup, al_reg }
466 #define eAXr { REP_Fixup, eAX_reg }
468 /* Used handle HLE prefix for lockable instructions. */
469 #define Ebh1 { HLE_Fixup1, b_mode }
470 #define Evh1 { HLE_Fixup1, v_mode }
471 #define Ebh2 { HLE_Fixup2, b_mode }
472 #define Evh2 { HLE_Fixup2, v_mode }
473 #define Ebh3 { HLE_Fixup3, b_mode }
474 #define Evh3 { HLE_Fixup3, v_mode }
476 #define BND { BND_Fixup, 0 }
477 #define NOTRACK { NOTRACK_Fixup, 0 }
479 #define cond_jump_flag { NULL, cond_jump_mode }
480 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
482 /* bits in sizeflag */
483 #define SUFFIX_ALWAYS 4
491 /* byte operand with operand swapped */
493 /* byte operand, sign extend like 'T' suffix */
495 /* operand size depends on prefixes */
497 /* operand size depends on prefixes with operand swapped */
501 /* double word operand */
503 /* double word operand with operand swapped */
505 /* quad word operand */
507 /* quad word operand with operand swapped */
509 /* ten-byte operand */
511 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
512 broadcast enabled. */
514 /* Similar to x_mode, but with different EVEX mem shifts. */
516 /* Similar to x_mode, but with disabled broadcast. */
518 /* Similar to x_mode, but with operands swapped and disabled broadcast
521 /* 16-byte XMM operand */
523 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
524 memory operand (depending on vector length). Broadcast isn't
527 /* Same as xmmq_mode, but broadcast is allowed. */
528 evex_half_bcst_xmmq_mode
,
529 /* XMM register or byte memory operand */
531 /* XMM register or word memory operand */
533 /* XMM register or double word memory operand */
535 /* XMM register or quad word memory operand */
537 /* XMM register or double/quad word memory operand, depending on
540 /* 16-byte XMM, word, double word or quad word operand. */
542 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
544 /* 32-byte YMM operand */
546 /* quad word, ymmword or zmmword memory operand. */
548 /* 32-byte YMM or 16-byte word operand */
550 /* d_mode in 32bit, q_mode in 64bit mode. */
552 /* pair of v_mode operands */
557 /* operand size depends on REX prefixes. */
559 /* registers like dq_mode, memory like w_mode. */
562 /* 4- or 6-byte pointer operand */
565 /* v_mode for indirect branch opcodes. */
567 /* v_mode for stack-related opcodes. */
569 /* non-quad operand size depends on prefixes */
571 /* 16-byte operand */
573 /* registers like dq_mode, memory like b_mode. */
575 /* registers like d_mode, memory like b_mode. */
577 /* registers like d_mode, memory like w_mode. */
579 /* registers like dq_mode, memory like d_mode. */
581 /* normal vex mode */
583 /* 128bit vex mode */
585 /* 256bit vex mode */
587 /* operand size depends on the VEX.W bit. */
590 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
591 vex_vsib_d_w_dq_mode
,
592 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
594 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
595 vex_vsib_q_w_dq_mode
,
596 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
599 /* scalar, ignore vector length. */
601 /* like d_mode, ignore vector length. */
603 /* like d_swap_mode, ignore vector length. */
605 /* like q_mode, ignore vector length. */
607 /* like q_swap_mode, ignore vector length. */
609 /* like vex_mode, ignore vector length. */
611 /* like vex_w_dq_mode, ignore vector length. */
612 vex_scalar_w_dq_mode
,
614 /* Static rounding. */
616 /* Supress all exceptions. */
619 /* Mask register operand. */
621 /* Mask register operand. */
688 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
690 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
691 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
692 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
693 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
694 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
695 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
696 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
697 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
698 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
699 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
700 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
701 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
702 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
703 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
704 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
826 MOD_VEX_0F12_PREFIX_0
,
828 MOD_VEX_0F16_PREFIX_0
,
831 MOD_VEX_W_0_0F41_P_0_LEN_1
,
832 MOD_VEX_W_1_0F41_P_0_LEN_1
,
833 MOD_VEX_W_0_0F41_P_2_LEN_1
,
834 MOD_VEX_W_1_0F41_P_2_LEN_1
,
835 MOD_VEX_W_0_0F42_P_0_LEN_1
,
836 MOD_VEX_W_1_0F42_P_0_LEN_1
,
837 MOD_VEX_W_0_0F42_P_2_LEN_1
,
838 MOD_VEX_W_1_0F42_P_2_LEN_1
,
839 MOD_VEX_W_0_0F44_P_0_LEN_1
,
840 MOD_VEX_W_1_0F44_P_0_LEN_1
,
841 MOD_VEX_W_0_0F44_P_2_LEN_1
,
842 MOD_VEX_W_1_0F44_P_2_LEN_1
,
843 MOD_VEX_W_0_0F45_P_0_LEN_1
,
844 MOD_VEX_W_1_0F45_P_0_LEN_1
,
845 MOD_VEX_W_0_0F45_P_2_LEN_1
,
846 MOD_VEX_W_1_0F45_P_2_LEN_1
,
847 MOD_VEX_W_0_0F46_P_0_LEN_1
,
848 MOD_VEX_W_1_0F46_P_0_LEN_1
,
849 MOD_VEX_W_0_0F46_P_2_LEN_1
,
850 MOD_VEX_W_1_0F46_P_2_LEN_1
,
851 MOD_VEX_W_0_0F47_P_0_LEN_1
,
852 MOD_VEX_W_1_0F47_P_0_LEN_1
,
853 MOD_VEX_W_0_0F47_P_2_LEN_1
,
854 MOD_VEX_W_1_0F47_P_2_LEN_1
,
855 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
856 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
857 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
858 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
859 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
860 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
861 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
873 MOD_VEX_W_0_0F91_P_0_LEN_0
,
874 MOD_VEX_W_1_0F91_P_0_LEN_0
,
875 MOD_VEX_W_0_0F91_P_2_LEN_0
,
876 MOD_VEX_W_1_0F91_P_2_LEN_0
,
877 MOD_VEX_W_0_0F92_P_0_LEN_0
,
878 MOD_VEX_W_0_0F92_P_2_LEN_0
,
879 MOD_VEX_W_0_0F92_P_3_LEN_0
,
880 MOD_VEX_W_1_0F92_P_3_LEN_0
,
881 MOD_VEX_W_0_0F93_P_0_LEN_0
,
882 MOD_VEX_W_0_0F93_P_2_LEN_0
,
883 MOD_VEX_W_0_0F93_P_3_LEN_0
,
884 MOD_VEX_W_1_0F93_P_3_LEN_0
,
885 MOD_VEX_W_0_0F98_P_0_LEN_0
,
886 MOD_VEX_W_1_0F98_P_0_LEN_0
,
887 MOD_VEX_W_0_0F98_P_2_LEN_0
,
888 MOD_VEX_W_1_0F98_P_2_LEN_0
,
889 MOD_VEX_W_0_0F99_P_0_LEN_0
,
890 MOD_VEX_W_1_0F99_P_0_LEN_0
,
891 MOD_VEX_W_0_0F99_P_2_LEN_0
,
892 MOD_VEX_W_1_0F99_P_2_LEN_0
,
895 MOD_VEX_0FD7_PREFIX_2
,
896 MOD_VEX_0FE7_PREFIX_2
,
897 MOD_VEX_0FF0_PREFIX_3
,
898 MOD_VEX_0F381A_PREFIX_2
,
899 MOD_VEX_0F382A_PREFIX_2
,
900 MOD_VEX_0F382C_PREFIX_2
,
901 MOD_VEX_0F382D_PREFIX_2
,
902 MOD_VEX_0F382E_PREFIX_2
,
903 MOD_VEX_0F382F_PREFIX_2
,
904 MOD_VEX_0F385A_PREFIX_2
,
905 MOD_VEX_0F388C_PREFIX_2
,
906 MOD_VEX_0F388E_PREFIX_2
,
907 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
908 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
909 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
910 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
911 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
912 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
913 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
914 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
916 MOD_EVEX_0F10_PREFIX_1
,
917 MOD_EVEX_0F10_PREFIX_3
,
918 MOD_EVEX_0F11_PREFIX_1
,
919 MOD_EVEX_0F11_PREFIX_3
,
920 MOD_EVEX_0F12_PREFIX_0
,
921 MOD_EVEX_0F16_PREFIX_0
,
922 MOD_EVEX_0F38C6_REG_1
,
923 MOD_EVEX_0F38C6_REG_2
,
924 MOD_EVEX_0F38C6_REG_5
,
925 MOD_EVEX_0F38C6_REG_6
,
926 MOD_EVEX_0F38C7_REG_1
,
927 MOD_EVEX_0F38C7_REG_2
,
928 MOD_EVEX_0F38C7_REG_5
,
929 MOD_EVEX_0F38C7_REG_6
951 PREFIX_MOD_0_0F01_REG_5
,
952 PREFIX_MOD_3_0F01_REG_5_RM_1
,
953 PREFIX_MOD_3_0F01_REG_5_RM_2
,
997 PREFIX_MOD_0_0FAE_REG_4
,
998 PREFIX_MOD_3_0FAE_REG_4
,
999 PREFIX_MOD_0_0FAE_REG_5
,
1007 PREFIX_MOD_0_0FC7_REG_6
,
1008 PREFIX_MOD_3_0FC7_REG_6
,
1009 PREFIX_MOD_3_0FC7_REG_7
,
1134 PREFIX_VEX_0F71_REG_2
,
1135 PREFIX_VEX_0F71_REG_4
,
1136 PREFIX_VEX_0F71_REG_6
,
1137 PREFIX_VEX_0F72_REG_2
,
1138 PREFIX_VEX_0F72_REG_4
,
1139 PREFIX_VEX_0F72_REG_6
,
1140 PREFIX_VEX_0F73_REG_2
,
1141 PREFIX_VEX_0F73_REG_3
,
1142 PREFIX_VEX_0F73_REG_6
,
1143 PREFIX_VEX_0F73_REG_7
,
1315 PREFIX_VEX_0F38F3_REG_1
,
1316 PREFIX_VEX_0F38F3_REG_2
,
1317 PREFIX_VEX_0F38F3_REG_3
,
1434 PREFIX_EVEX_0F71_REG_2
,
1435 PREFIX_EVEX_0F71_REG_4
,
1436 PREFIX_EVEX_0F71_REG_6
,
1437 PREFIX_EVEX_0F72_REG_0
,
1438 PREFIX_EVEX_0F72_REG_1
,
1439 PREFIX_EVEX_0F72_REG_2
,
1440 PREFIX_EVEX_0F72_REG_4
,
1441 PREFIX_EVEX_0F72_REG_6
,
1442 PREFIX_EVEX_0F73_REG_2
,
1443 PREFIX_EVEX_0F73_REG_3
,
1444 PREFIX_EVEX_0F73_REG_6
,
1445 PREFIX_EVEX_0F73_REG_7
,
1631 PREFIX_EVEX_0F38C6_REG_1
,
1632 PREFIX_EVEX_0F38C6_REG_2
,
1633 PREFIX_EVEX_0F38C6_REG_5
,
1634 PREFIX_EVEX_0F38C6_REG_6
,
1635 PREFIX_EVEX_0F38C7_REG_1
,
1636 PREFIX_EVEX_0F38C7_REG_2
,
1637 PREFIX_EVEX_0F38C7_REG_5
,
1638 PREFIX_EVEX_0F38C7_REG_6
,
1728 THREE_BYTE_0F38
= 0,
1755 VEX_LEN_0F10_P_1
= 0,
1759 VEX_LEN_0F12_P_0_M_0
,
1760 VEX_LEN_0F12_P_0_M_1
,
1763 VEX_LEN_0F16_P_0_M_0
,
1764 VEX_LEN_0F16_P_0_M_1
,
1828 VEX_LEN_0FAE_R_2_M_0
,
1829 VEX_LEN_0FAE_R_3_M_0
,
1838 VEX_LEN_0F381A_P_2_M_0
,
1841 VEX_LEN_0F385A_P_2_M_0
,
1848 VEX_LEN_0F38F3_R_1_P_0
,
1849 VEX_LEN_0F38F3_R_2_P_0
,
1850 VEX_LEN_0F38F3_R_3_P_0
,
1896 VEX_LEN_0FXOP_08_CC
,
1897 VEX_LEN_0FXOP_08_CD
,
1898 VEX_LEN_0FXOP_08_CE
,
1899 VEX_LEN_0FXOP_08_CF
,
1900 VEX_LEN_0FXOP_08_EC
,
1901 VEX_LEN_0FXOP_08_ED
,
1902 VEX_LEN_0FXOP_08_EE
,
1903 VEX_LEN_0FXOP_08_EF
,
1904 VEX_LEN_0FXOP_09_80
,
1938 VEX_W_0F41_P_0_LEN_1
,
1939 VEX_W_0F41_P_2_LEN_1
,
1940 VEX_W_0F42_P_0_LEN_1
,
1941 VEX_W_0F42_P_2_LEN_1
,
1942 VEX_W_0F44_P_0_LEN_0
,
1943 VEX_W_0F44_P_2_LEN_0
,
1944 VEX_W_0F45_P_0_LEN_1
,
1945 VEX_W_0F45_P_2_LEN_1
,
1946 VEX_W_0F46_P_0_LEN_1
,
1947 VEX_W_0F46_P_2_LEN_1
,
1948 VEX_W_0F47_P_0_LEN_1
,
1949 VEX_W_0F47_P_2_LEN_1
,
1950 VEX_W_0F4A_P_0_LEN_1
,
1951 VEX_W_0F4A_P_2_LEN_1
,
1952 VEX_W_0F4B_P_0_LEN_1
,
1953 VEX_W_0F4B_P_2_LEN_1
,
2033 VEX_W_0F90_P_0_LEN_0
,
2034 VEX_W_0F90_P_2_LEN_0
,
2035 VEX_W_0F91_P_0_LEN_0
,
2036 VEX_W_0F91_P_2_LEN_0
,
2037 VEX_W_0F92_P_0_LEN_0
,
2038 VEX_W_0F92_P_2_LEN_0
,
2039 VEX_W_0F92_P_3_LEN_0
,
2040 VEX_W_0F93_P_0_LEN_0
,
2041 VEX_W_0F93_P_2_LEN_0
,
2042 VEX_W_0F93_P_3_LEN_0
,
2043 VEX_W_0F98_P_0_LEN_0
,
2044 VEX_W_0F98_P_2_LEN_0
,
2045 VEX_W_0F99_P_0_LEN_0
,
2046 VEX_W_0F99_P_2_LEN_0
,
2125 VEX_W_0F381A_P_2_M_0
,
2137 VEX_W_0F382A_P_2_M_0
,
2139 VEX_W_0F382C_P_2_M_0
,
2140 VEX_W_0F382D_P_2_M_0
,
2141 VEX_W_0F382E_P_2_M_0
,
2142 VEX_W_0F382F_P_2_M_0
,
2164 VEX_W_0F385A_P_2_M_0
,
2192 VEX_W_0F3A30_P_2_LEN_0
,
2193 VEX_W_0F3A31_P_2_LEN_0
,
2194 VEX_W_0F3A32_P_2_LEN_0
,
2195 VEX_W_0F3A33_P_2_LEN_0
,
2213 EVEX_W_0F10_P_1_M_0
,
2214 EVEX_W_0F10_P_1_M_1
,
2216 EVEX_W_0F10_P_3_M_0
,
2217 EVEX_W_0F10_P_3_M_1
,
2219 EVEX_W_0F11_P_1_M_0
,
2220 EVEX_W_0F11_P_1_M_1
,
2222 EVEX_W_0F11_P_3_M_0
,
2223 EVEX_W_0F11_P_3_M_1
,
2224 EVEX_W_0F12_P_0_M_0
,
2225 EVEX_W_0F12_P_0_M_1
,
2235 EVEX_W_0F16_P_0_M_0
,
2236 EVEX_W_0F16_P_0_M_1
,
2307 EVEX_W_0F72_R_2_P_2
,
2308 EVEX_W_0F72_R_6_P_2
,
2309 EVEX_W_0F73_R_2_P_2
,
2310 EVEX_W_0F73_R_6_P_2
,
2411 EVEX_W_0F38C7_R_1_P_2
,
2412 EVEX_W_0F38C7_R_2_P_2
,
2413 EVEX_W_0F38C7_R_5_P_2
,
2414 EVEX_W_0F38C7_R_6_P_2
,
2449 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2458 unsigned int prefix_requirement
;
2461 /* Upper case letters in the instruction names here are macros.
2462 'A' => print 'b' if no register operands or suffix_always is true
2463 'B' => print 'b' if suffix_always is true
2464 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2466 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2467 suffix_always is true
2468 'E' => print 'e' if 32-bit form of jcxz
2469 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2470 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2471 'H' => print ",pt" or ",pn" branch hint
2472 'I' => honor following macro letter even in Intel mode (implemented only
2473 for some of the macro letters)
2475 'K' => print 'd' or 'q' if rex prefix is present.
2476 'L' => print 'l' if suffix_always is true
2477 'M' => print 'r' if intel_mnemonic is false.
2478 'N' => print 'n' if instruction has no wait "prefix"
2479 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2480 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2481 or suffix_always is true. print 'q' if rex prefix is present.
2482 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2484 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2485 'S' => print 'w', 'l' or 'q' if suffix_always is true
2486 'T' => print 'q' in 64bit mode if instruction has no operand size
2487 prefix and behave as 'P' otherwise
2488 'U' => print 'q' in 64bit mode if instruction has no operand size
2489 prefix and behave as 'Q' otherwise
2490 'V' => print 'q' in 64bit mode if instruction has no operand size
2491 prefix and behave as 'S' otherwise
2492 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2493 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2494 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2495 suffix_always is true.
2496 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2497 '!' => change condition from true to false or from false to true.
2498 '%' => add 1 upper case letter to the macro.
2499 '^' => print 'w' or 'l' depending on operand size prefix or
2500 suffix_always is true (lcall/ljmp).
2501 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2502 on operand size prefix.
2503 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2504 has no operand size prefix for AMD64 ISA, behave as 'P'
2507 2 upper case letter macros:
2508 "XY" => print 'x' or 'y' if suffix_always is true or no register
2509 operands and no broadcast.
2510 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2511 register operands and no broadcast.
2512 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2513 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2514 or suffix_always is true
2515 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2516 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2517 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2518 "LW" => print 'd', 'q' depending on the VEX.W bit
2519 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2520 an operand size prefix, or suffix_always is true. print
2521 'q' if rex prefix is present.
2523 Many of the above letters print nothing in Intel mode. See "putop"
2526 Braces '{' and '}', and vertical bars '|', indicate alternative
2527 mnemonic strings for AT&T and Intel. */
2529 static const struct dis386 dis386
[] = {
2531 { "addB", { Ebh1
, Gb
}, 0 },
2532 { "addS", { Evh1
, Gv
}, 0 },
2533 { "addB", { Gb
, EbS
}, 0 },
2534 { "addS", { Gv
, EvS
}, 0 },
2535 { "addB", { AL
, Ib
}, 0 },
2536 { "addS", { eAX
, Iv
}, 0 },
2537 { X86_64_TABLE (X86_64_06
) },
2538 { X86_64_TABLE (X86_64_07
) },
2540 { "orB", { Ebh1
, Gb
}, 0 },
2541 { "orS", { Evh1
, Gv
}, 0 },
2542 { "orB", { Gb
, EbS
}, 0 },
2543 { "orS", { Gv
, EvS
}, 0 },
2544 { "orB", { AL
, Ib
}, 0 },
2545 { "orS", { eAX
, Iv
}, 0 },
2546 { X86_64_TABLE (X86_64_0D
) },
2547 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2549 { "adcB", { Ebh1
, Gb
}, 0 },
2550 { "adcS", { Evh1
, Gv
}, 0 },
2551 { "adcB", { Gb
, EbS
}, 0 },
2552 { "adcS", { Gv
, EvS
}, 0 },
2553 { "adcB", { AL
, Ib
}, 0 },
2554 { "adcS", { eAX
, Iv
}, 0 },
2555 { X86_64_TABLE (X86_64_16
) },
2556 { X86_64_TABLE (X86_64_17
) },
2558 { "sbbB", { Ebh1
, Gb
}, 0 },
2559 { "sbbS", { Evh1
, Gv
}, 0 },
2560 { "sbbB", { Gb
, EbS
}, 0 },
2561 { "sbbS", { Gv
, EvS
}, 0 },
2562 { "sbbB", { AL
, Ib
}, 0 },
2563 { "sbbS", { eAX
, Iv
}, 0 },
2564 { X86_64_TABLE (X86_64_1E
) },
2565 { X86_64_TABLE (X86_64_1F
) },
2567 { "andB", { Ebh1
, Gb
}, 0 },
2568 { "andS", { Evh1
, Gv
}, 0 },
2569 { "andB", { Gb
, EbS
}, 0 },
2570 { "andS", { Gv
, EvS
}, 0 },
2571 { "andB", { AL
, Ib
}, 0 },
2572 { "andS", { eAX
, Iv
}, 0 },
2573 { Bad_Opcode
}, /* SEG ES prefix */
2574 { X86_64_TABLE (X86_64_27
) },
2576 { "subB", { Ebh1
, Gb
}, 0 },
2577 { "subS", { Evh1
, Gv
}, 0 },
2578 { "subB", { Gb
, EbS
}, 0 },
2579 { "subS", { Gv
, EvS
}, 0 },
2580 { "subB", { AL
, Ib
}, 0 },
2581 { "subS", { eAX
, Iv
}, 0 },
2582 { Bad_Opcode
}, /* SEG CS prefix */
2583 { X86_64_TABLE (X86_64_2F
) },
2585 { "xorB", { Ebh1
, Gb
}, 0 },
2586 { "xorS", { Evh1
, Gv
}, 0 },
2587 { "xorB", { Gb
, EbS
}, 0 },
2588 { "xorS", { Gv
, EvS
}, 0 },
2589 { "xorB", { AL
, Ib
}, 0 },
2590 { "xorS", { eAX
, Iv
}, 0 },
2591 { Bad_Opcode
}, /* SEG SS prefix */
2592 { X86_64_TABLE (X86_64_37
) },
2594 { "cmpB", { Eb
, Gb
}, 0 },
2595 { "cmpS", { Ev
, Gv
}, 0 },
2596 { "cmpB", { Gb
, EbS
}, 0 },
2597 { "cmpS", { Gv
, EvS
}, 0 },
2598 { "cmpB", { AL
, Ib
}, 0 },
2599 { "cmpS", { eAX
, Iv
}, 0 },
2600 { Bad_Opcode
}, /* SEG DS prefix */
2601 { X86_64_TABLE (X86_64_3F
) },
2603 { "inc{S|}", { RMeAX
}, 0 },
2604 { "inc{S|}", { RMeCX
}, 0 },
2605 { "inc{S|}", { RMeDX
}, 0 },
2606 { "inc{S|}", { RMeBX
}, 0 },
2607 { "inc{S|}", { RMeSP
}, 0 },
2608 { "inc{S|}", { RMeBP
}, 0 },
2609 { "inc{S|}", { RMeSI
}, 0 },
2610 { "inc{S|}", { RMeDI
}, 0 },
2612 { "dec{S|}", { RMeAX
}, 0 },
2613 { "dec{S|}", { RMeCX
}, 0 },
2614 { "dec{S|}", { RMeDX
}, 0 },
2615 { "dec{S|}", { RMeBX
}, 0 },
2616 { "dec{S|}", { RMeSP
}, 0 },
2617 { "dec{S|}", { RMeBP
}, 0 },
2618 { "dec{S|}", { RMeSI
}, 0 },
2619 { "dec{S|}", { RMeDI
}, 0 },
2621 { "pushV", { RMrAX
}, 0 },
2622 { "pushV", { RMrCX
}, 0 },
2623 { "pushV", { RMrDX
}, 0 },
2624 { "pushV", { RMrBX
}, 0 },
2625 { "pushV", { RMrSP
}, 0 },
2626 { "pushV", { RMrBP
}, 0 },
2627 { "pushV", { RMrSI
}, 0 },
2628 { "pushV", { RMrDI
}, 0 },
2630 { "popV", { RMrAX
}, 0 },
2631 { "popV", { RMrCX
}, 0 },
2632 { "popV", { RMrDX
}, 0 },
2633 { "popV", { RMrBX
}, 0 },
2634 { "popV", { RMrSP
}, 0 },
2635 { "popV", { RMrBP
}, 0 },
2636 { "popV", { RMrSI
}, 0 },
2637 { "popV", { RMrDI
}, 0 },
2639 { X86_64_TABLE (X86_64_60
) },
2640 { X86_64_TABLE (X86_64_61
) },
2641 { X86_64_TABLE (X86_64_62
) },
2642 { X86_64_TABLE (X86_64_63
) },
2643 { Bad_Opcode
}, /* seg fs */
2644 { Bad_Opcode
}, /* seg gs */
2645 { Bad_Opcode
}, /* op size prefix */
2646 { Bad_Opcode
}, /* adr size prefix */
2648 { "pushT", { sIv
}, 0 },
2649 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2650 { "pushT", { sIbT
}, 0 },
2651 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2652 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2653 { X86_64_TABLE (X86_64_6D
) },
2654 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2655 { X86_64_TABLE (X86_64_6F
) },
2657 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2658 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2659 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2660 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2661 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2662 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2663 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2664 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2666 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2667 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2668 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2669 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2670 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2671 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2672 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2673 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2675 { REG_TABLE (REG_80
) },
2676 { REG_TABLE (REG_81
) },
2677 { X86_64_TABLE (X86_64_82
) },
2678 { REG_TABLE (REG_83
) },
2679 { "testB", { Eb
, Gb
}, 0 },
2680 { "testS", { Ev
, Gv
}, 0 },
2681 { "xchgB", { Ebh2
, Gb
}, 0 },
2682 { "xchgS", { Evh2
, Gv
}, 0 },
2684 { "movB", { Ebh3
, Gb
}, 0 },
2685 { "movS", { Evh3
, Gv
}, 0 },
2686 { "movB", { Gb
, EbS
}, 0 },
2687 { "movS", { Gv
, EvS
}, 0 },
2688 { "movD", { Sv
, Sw
}, 0 },
2689 { MOD_TABLE (MOD_8D
) },
2690 { "movD", { Sw
, Sv
}, 0 },
2691 { REG_TABLE (REG_8F
) },
2693 { PREFIX_TABLE (PREFIX_90
) },
2694 { "xchgS", { RMeCX
, eAX
}, 0 },
2695 { "xchgS", { RMeDX
, eAX
}, 0 },
2696 { "xchgS", { RMeBX
, eAX
}, 0 },
2697 { "xchgS", { RMeSP
, eAX
}, 0 },
2698 { "xchgS", { RMeBP
, eAX
}, 0 },
2699 { "xchgS", { RMeSI
, eAX
}, 0 },
2700 { "xchgS", { RMeDI
, eAX
}, 0 },
2702 { "cW{t|}R", { XX
}, 0 },
2703 { "cR{t|}O", { XX
}, 0 },
2704 { X86_64_TABLE (X86_64_9A
) },
2705 { Bad_Opcode
}, /* fwait */
2706 { "pushfT", { XX
}, 0 },
2707 { "popfT", { XX
}, 0 },
2708 { "sahf", { XX
}, 0 },
2709 { "lahf", { XX
}, 0 },
2711 { "mov%LB", { AL
, Ob
}, 0 },
2712 { "mov%LS", { eAX
, Ov
}, 0 },
2713 { "mov%LB", { Ob
, AL
}, 0 },
2714 { "mov%LS", { Ov
, eAX
}, 0 },
2715 { "movs{b|}", { Ybr
, Xb
}, 0 },
2716 { "movs{R|}", { Yvr
, Xv
}, 0 },
2717 { "cmps{b|}", { Xb
, Yb
}, 0 },
2718 { "cmps{R|}", { Xv
, Yv
}, 0 },
2720 { "testB", { AL
, Ib
}, 0 },
2721 { "testS", { eAX
, Iv
}, 0 },
2722 { "stosB", { Ybr
, AL
}, 0 },
2723 { "stosS", { Yvr
, eAX
}, 0 },
2724 { "lodsB", { ALr
, Xb
}, 0 },
2725 { "lodsS", { eAXr
, Xv
}, 0 },
2726 { "scasB", { AL
, Yb
}, 0 },
2727 { "scasS", { eAX
, Yv
}, 0 },
2729 { "movB", { RMAL
, Ib
}, 0 },
2730 { "movB", { RMCL
, Ib
}, 0 },
2731 { "movB", { RMDL
, Ib
}, 0 },
2732 { "movB", { RMBL
, Ib
}, 0 },
2733 { "movB", { RMAH
, Ib
}, 0 },
2734 { "movB", { RMCH
, Ib
}, 0 },
2735 { "movB", { RMDH
, Ib
}, 0 },
2736 { "movB", { RMBH
, Ib
}, 0 },
2738 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2739 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2740 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2741 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2742 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2743 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2744 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2745 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2747 { REG_TABLE (REG_C0
) },
2748 { REG_TABLE (REG_C1
) },
2749 { "retT", { Iw
, BND
}, 0 },
2750 { "retT", { BND
}, 0 },
2751 { X86_64_TABLE (X86_64_C4
) },
2752 { X86_64_TABLE (X86_64_C5
) },
2753 { REG_TABLE (REG_C6
) },
2754 { REG_TABLE (REG_C7
) },
2756 { "enterT", { Iw
, Ib
}, 0 },
2757 { "leaveT", { XX
}, 0 },
2758 { "Jret{|f}P", { Iw
}, 0 },
2759 { "Jret{|f}P", { XX
}, 0 },
2760 { "int3", { XX
}, 0 },
2761 { "int", { Ib
}, 0 },
2762 { X86_64_TABLE (X86_64_CE
) },
2763 { "iret%LP", { XX
}, 0 },
2765 { REG_TABLE (REG_D0
) },
2766 { REG_TABLE (REG_D1
) },
2767 { REG_TABLE (REG_D2
) },
2768 { REG_TABLE (REG_D3
) },
2769 { X86_64_TABLE (X86_64_D4
) },
2770 { X86_64_TABLE (X86_64_D5
) },
2772 { "xlat", { DSBX
}, 0 },
2783 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2784 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2785 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2786 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2787 { "inB", { AL
, Ib
}, 0 },
2788 { "inG", { zAX
, Ib
}, 0 },
2789 { "outB", { Ib
, AL
}, 0 },
2790 { "outG", { Ib
, zAX
}, 0 },
2792 { X86_64_TABLE (X86_64_E8
) },
2793 { X86_64_TABLE (X86_64_E9
) },
2794 { X86_64_TABLE (X86_64_EA
) },
2795 { "jmp", { Jb
, BND
}, 0 },
2796 { "inB", { AL
, indirDX
}, 0 },
2797 { "inG", { zAX
, indirDX
}, 0 },
2798 { "outB", { indirDX
, AL
}, 0 },
2799 { "outG", { indirDX
, zAX
}, 0 },
2801 { Bad_Opcode
}, /* lock prefix */
2802 { "icebp", { XX
}, 0 },
2803 { Bad_Opcode
}, /* repne */
2804 { Bad_Opcode
}, /* repz */
2805 { "hlt", { XX
}, 0 },
2806 { "cmc", { XX
}, 0 },
2807 { REG_TABLE (REG_F6
) },
2808 { REG_TABLE (REG_F7
) },
2810 { "clc", { XX
}, 0 },
2811 { "stc", { XX
}, 0 },
2812 { "cli", { XX
}, 0 },
2813 { "sti", { XX
}, 0 },
2814 { "cld", { XX
}, 0 },
2815 { "std", { XX
}, 0 },
2816 { REG_TABLE (REG_FE
) },
2817 { REG_TABLE (REG_FF
) },
2820 static const struct dis386 dis386_twobyte
[] = {
2822 { REG_TABLE (REG_0F00
) },
2823 { REG_TABLE (REG_0F01
) },
2824 { "larS", { Gv
, Ew
}, 0 },
2825 { "lslS", { Gv
, Ew
}, 0 },
2827 { "syscall", { XX
}, 0 },
2828 { "clts", { XX
}, 0 },
2829 { "sysret%LP", { XX
}, 0 },
2831 { "invd", { XX
}, 0 },
2832 { "wbinvd", { XX
}, 0 },
2834 { "ud2", { XX
}, 0 },
2836 { REG_TABLE (REG_0F0D
) },
2837 { "femms", { XX
}, 0 },
2838 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2840 { PREFIX_TABLE (PREFIX_0F10
) },
2841 { PREFIX_TABLE (PREFIX_0F11
) },
2842 { PREFIX_TABLE (PREFIX_0F12
) },
2843 { MOD_TABLE (MOD_0F13
) },
2844 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2845 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2846 { PREFIX_TABLE (PREFIX_0F16
) },
2847 { MOD_TABLE (MOD_0F17
) },
2849 { REG_TABLE (REG_0F18
) },
2850 { "nopQ", { Ev
}, 0 },
2851 { PREFIX_TABLE (PREFIX_0F1A
) },
2852 { PREFIX_TABLE (PREFIX_0F1B
) },
2853 { "nopQ", { Ev
}, 0 },
2854 { "nopQ", { Ev
}, 0 },
2855 { PREFIX_TABLE (PREFIX_0F1E
) },
2856 { "nopQ", { Ev
}, 0 },
2858 { "movZ", { Rm
, Cm
}, 0 },
2859 { "movZ", { Rm
, Dm
}, 0 },
2860 { "movZ", { Cm
, Rm
}, 0 },
2861 { "movZ", { Dm
, Rm
}, 0 },
2862 { MOD_TABLE (MOD_0F24
) },
2864 { MOD_TABLE (MOD_0F26
) },
2867 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2868 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2869 { PREFIX_TABLE (PREFIX_0F2A
) },
2870 { PREFIX_TABLE (PREFIX_0F2B
) },
2871 { PREFIX_TABLE (PREFIX_0F2C
) },
2872 { PREFIX_TABLE (PREFIX_0F2D
) },
2873 { PREFIX_TABLE (PREFIX_0F2E
) },
2874 { PREFIX_TABLE (PREFIX_0F2F
) },
2876 { "wrmsr", { XX
}, 0 },
2877 { "rdtsc", { XX
}, 0 },
2878 { "rdmsr", { XX
}, 0 },
2879 { "rdpmc", { XX
}, 0 },
2880 { "sysenter", { XX
}, 0 },
2881 { "sysexit", { XX
}, 0 },
2883 { "getsec", { XX
}, 0 },
2885 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2887 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2894 { "cmovoS", { Gv
, Ev
}, 0 },
2895 { "cmovnoS", { Gv
, Ev
}, 0 },
2896 { "cmovbS", { Gv
, Ev
}, 0 },
2897 { "cmovaeS", { Gv
, Ev
}, 0 },
2898 { "cmoveS", { Gv
, Ev
}, 0 },
2899 { "cmovneS", { Gv
, Ev
}, 0 },
2900 { "cmovbeS", { Gv
, Ev
}, 0 },
2901 { "cmovaS", { Gv
, Ev
}, 0 },
2903 { "cmovsS", { Gv
, Ev
}, 0 },
2904 { "cmovnsS", { Gv
, Ev
}, 0 },
2905 { "cmovpS", { Gv
, Ev
}, 0 },
2906 { "cmovnpS", { Gv
, Ev
}, 0 },
2907 { "cmovlS", { Gv
, Ev
}, 0 },
2908 { "cmovgeS", { Gv
, Ev
}, 0 },
2909 { "cmovleS", { Gv
, Ev
}, 0 },
2910 { "cmovgS", { Gv
, Ev
}, 0 },
2912 { MOD_TABLE (MOD_0F51
) },
2913 { PREFIX_TABLE (PREFIX_0F51
) },
2914 { PREFIX_TABLE (PREFIX_0F52
) },
2915 { PREFIX_TABLE (PREFIX_0F53
) },
2916 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2917 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2918 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2919 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2921 { PREFIX_TABLE (PREFIX_0F58
) },
2922 { PREFIX_TABLE (PREFIX_0F59
) },
2923 { PREFIX_TABLE (PREFIX_0F5A
) },
2924 { PREFIX_TABLE (PREFIX_0F5B
) },
2925 { PREFIX_TABLE (PREFIX_0F5C
) },
2926 { PREFIX_TABLE (PREFIX_0F5D
) },
2927 { PREFIX_TABLE (PREFIX_0F5E
) },
2928 { PREFIX_TABLE (PREFIX_0F5F
) },
2930 { PREFIX_TABLE (PREFIX_0F60
) },
2931 { PREFIX_TABLE (PREFIX_0F61
) },
2932 { PREFIX_TABLE (PREFIX_0F62
) },
2933 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2934 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2935 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2936 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2937 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2939 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2940 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2941 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2942 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2943 { PREFIX_TABLE (PREFIX_0F6C
) },
2944 { PREFIX_TABLE (PREFIX_0F6D
) },
2945 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2946 { PREFIX_TABLE (PREFIX_0F6F
) },
2948 { PREFIX_TABLE (PREFIX_0F70
) },
2949 { REG_TABLE (REG_0F71
) },
2950 { REG_TABLE (REG_0F72
) },
2951 { REG_TABLE (REG_0F73
) },
2952 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2953 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2954 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2955 { "emms", { XX
}, PREFIX_OPCODE
},
2957 { PREFIX_TABLE (PREFIX_0F78
) },
2958 { PREFIX_TABLE (PREFIX_0F79
) },
2961 { PREFIX_TABLE (PREFIX_0F7C
) },
2962 { PREFIX_TABLE (PREFIX_0F7D
) },
2963 { PREFIX_TABLE (PREFIX_0F7E
) },
2964 { PREFIX_TABLE (PREFIX_0F7F
) },
2966 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2967 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2968 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2969 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2970 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2971 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2972 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2973 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2975 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2976 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2977 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2978 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2979 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2980 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2981 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2982 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2984 { "seto", { Eb
}, 0 },
2985 { "setno", { Eb
}, 0 },
2986 { "setb", { Eb
}, 0 },
2987 { "setae", { Eb
}, 0 },
2988 { "sete", { Eb
}, 0 },
2989 { "setne", { Eb
}, 0 },
2990 { "setbe", { Eb
}, 0 },
2991 { "seta", { Eb
}, 0 },
2993 { "sets", { Eb
}, 0 },
2994 { "setns", { Eb
}, 0 },
2995 { "setp", { Eb
}, 0 },
2996 { "setnp", { Eb
}, 0 },
2997 { "setl", { Eb
}, 0 },
2998 { "setge", { Eb
}, 0 },
2999 { "setle", { Eb
}, 0 },
3000 { "setg", { Eb
}, 0 },
3002 { "pushT", { fs
}, 0 },
3003 { "popT", { fs
}, 0 },
3004 { "cpuid", { XX
}, 0 },
3005 { "btS", { Ev
, Gv
}, 0 },
3006 { "shldS", { Ev
, Gv
, Ib
}, 0 },
3007 { "shldS", { Ev
, Gv
, CL
}, 0 },
3008 { REG_TABLE (REG_0FA6
) },
3009 { REG_TABLE (REG_0FA7
) },
3011 { "pushT", { gs
}, 0 },
3012 { "popT", { gs
}, 0 },
3013 { "rsm", { XX
}, 0 },
3014 { "btsS", { Evh1
, Gv
}, 0 },
3015 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
3016 { "shrdS", { Ev
, Gv
, CL
}, 0 },
3017 { REG_TABLE (REG_0FAE
) },
3018 { "imulS", { Gv
, Ev
}, 0 },
3020 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
3021 { "cmpxchgS", { Evh1
, Gv
}, 0 },
3022 { MOD_TABLE (MOD_0FB2
) },
3023 { "btrS", { Evh1
, Gv
}, 0 },
3024 { MOD_TABLE (MOD_0FB4
) },
3025 { MOD_TABLE (MOD_0FB5
) },
3026 { "movz{bR|x}", { Gv
, Eb
}, 0 },
3027 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
3029 { PREFIX_TABLE (PREFIX_0FB8
) },
3030 { "ud1", { XX
}, 0 },
3031 { REG_TABLE (REG_0FBA
) },
3032 { "btcS", { Evh1
, Gv
}, 0 },
3033 { PREFIX_TABLE (PREFIX_0FBC
) },
3034 { PREFIX_TABLE (PREFIX_0FBD
) },
3035 { "movs{bR|x}", { Gv
, Eb
}, 0 },
3036 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
3038 { "xaddB", { Ebh1
, Gb
}, 0 },
3039 { "xaddS", { Evh1
, Gv
}, 0 },
3040 { PREFIX_TABLE (PREFIX_0FC2
) },
3041 { MOD_TABLE (MOD_0FC3
) },
3042 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
3043 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
3044 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3045 { REG_TABLE (REG_0FC7
) },
3047 { "bswap", { RMeAX
}, 0 },
3048 { "bswap", { RMeCX
}, 0 },
3049 { "bswap", { RMeDX
}, 0 },
3050 { "bswap", { RMeBX
}, 0 },
3051 { "bswap", { RMeSP
}, 0 },
3052 { "bswap", { RMeBP
}, 0 },
3053 { "bswap", { RMeSI
}, 0 },
3054 { "bswap", { RMeDI
}, 0 },
3056 { PREFIX_TABLE (PREFIX_0FD0
) },
3057 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
3058 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
3059 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
3060 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
3061 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
3062 { PREFIX_TABLE (PREFIX_0FD6
) },
3063 { MOD_TABLE (MOD_0FD7
) },
3065 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
3066 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
3067 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
3068 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
3069 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
3070 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
3071 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
3072 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
3074 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
3075 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
3076 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
3077 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
3078 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
3079 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
3080 { PREFIX_TABLE (PREFIX_0FE6
) },
3081 { PREFIX_TABLE (PREFIX_0FE7
) },
3083 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
3084 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
3085 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
3086 { "por", { MX
, EM
}, PREFIX_OPCODE
},
3087 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
3088 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
3089 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
3090 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
3092 { PREFIX_TABLE (PREFIX_0FF0
) },
3093 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
3094 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
3095 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
3096 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
3097 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
3098 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
3099 { PREFIX_TABLE (PREFIX_0FF7
) },
3101 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
3102 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
3103 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
3104 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
3105 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
3106 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
3107 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
3111 static const unsigned char onebyte_has_modrm
[256] = {
3112 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3113 /* ------------------------------- */
3114 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3115 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3116 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3117 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3118 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3119 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3120 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3121 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3122 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3123 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3124 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3125 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3126 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3127 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3128 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3129 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3130 /* ------------------------------- */
3131 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3134 static const unsigned char twobyte_has_modrm
[256] = {
3135 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3136 /* ------------------------------- */
3137 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3138 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3139 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3140 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3141 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3142 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3143 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3144 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3145 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3146 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3147 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3148 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3149 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3150 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3151 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3152 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3153 /* ------------------------------- */
3154 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3157 static char obuf
[100];
3159 static char *mnemonicendp
;
3160 static char scratchbuf
[100];
3161 static unsigned char *start_codep
;
3162 static unsigned char *insn_codep
;
3163 static unsigned char *codep
;
3164 static unsigned char *end_codep
;
3165 static int last_lock_prefix
;
3166 static int last_repz_prefix
;
3167 static int last_repnz_prefix
;
3168 static int last_data_prefix
;
3169 static int last_addr_prefix
;
3170 static int last_rex_prefix
;
3171 static int last_seg_prefix
;
3172 static int last_active_prefix
;
3173 static int fwait_prefix
;
3174 /* The active segment register prefix. */
3175 static int active_seg_prefix
;
3176 #define MAX_CODE_LENGTH 15
3177 /* We can up to 14 prefixes since the maximum instruction length is
3179 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3180 static disassemble_info
*the_info
;
3188 static unsigned char need_modrm
;
3198 int register_specifier
;
3205 int mask_register_specifier
;
3211 static unsigned char need_vex
;
3212 static unsigned char need_vex_reg
;
3213 static unsigned char vex_w_done
;
3221 /* If we are accessing mod/rm/reg without need_modrm set, then the
3222 values are stale. Hitting this abort likely indicates that you
3223 need to update onebyte_has_modrm or twobyte_has_modrm. */
3224 #define MODRM_CHECK if (!need_modrm) abort ()
3226 static const char **names64
;
3227 static const char **names32
;
3228 static const char **names16
;
3229 static const char **names8
;
3230 static const char **names8rex
;
3231 static const char **names_seg
;
3232 static const char *index64
;
3233 static const char *index32
;
3234 static const char **index16
;
3235 static const char **names_bnd
;
3237 static const char *intel_names64
[] = {
3238 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3239 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3241 static const char *intel_names32
[] = {
3242 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3243 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3245 static const char *intel_names16
[] = {
3246 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3247 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3249 static const char *intel_names8
[] = {
3250 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3252 static const char *intel_names8rex
[] = {
3253 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3254 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3256 static const char *intel_names_seg
[] = {
3257 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3259 static const char *intel_index64
= "riz";
3260 static const char *intel_index32
= "eiz";
3261 static const char *intel_index16
[] = {
3262 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3265 static const char *att_names64
[] = {
3266 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3267 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3269 static const char *att_names32
[] = {
3270 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3271 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3273 static const char *att_names16
[] = {
3274 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3275 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3277 static const char *att_names8
[] = {
3278 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3280 static const char *att_names8rex
[] = {
3281 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3282 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3284 static const char *att_names_seg
[] = {
3285 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3287 static const char *att_index64
= "%riz";
3288 static const char *att_index32
= "%eiz";
3289 static const char *att_index16
[] = {
3290 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3293 static const char **names_mm
;
3294 static const char *intel_names_mm
[] = {
3295 "mm0", "mm1", "mm2", "mm3",
3296 "mm4", "mm5", "mm6", "mm7"
3298 static const char *att_names_mm
[] = {
3299 "%mm0", "%mm1", "%mm2", "%mm3",
3300 "%mm4", "%mm5", "%mm6", "%mm7"
3303 static const char *intel_names_bnd
[] = {
3304 "bnd0", "bnd1", "bnd2", "bnd3"
3307 static const char *att_names_bnd
[] = {
3308 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3311 static const char **names_xmm
;
3312 static const char *intel_names_xmm
[] = {
3313 "xmm0", "xmm1", "xmm2", "xmm3",
3314 "xmm4", "xmm5", "xmm6", "xmm7",
3315 "xmm8", "xmm9", "xmm10", "xmm11",
3316 "xmm12", "xmm13", "xmm14", "xmm15",
3317 "xmm16", "xmm17", "xmm18", "xmm19",
3318 "xmm20", "xmm21", "xmm22", "xmm23",
3319 "xmm24", "xmm25", "xmm26", "xmm27",
3320 "xmm28", "xmm29", "xmm30", "xmm31"
3322 static const char *att_names_xmm
[] = {
3323 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3324 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3325 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3326 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3327 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3328 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3329 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3330 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3333 static const char **names_ymm
;
3334 static const char *intel_names_ymm
[] = {
3335 "ymm0", "ymm1", "ymm2", "ymm3",
3336 "ymm4", "ymm5", "ymm6", "ymm7",
3337 "ymm8", "ymm9", "ymm10", "ymm11",
3338 "ymm12", "ymm13", "ymm14", "ymm15",
3339 "ymm16", "ymm17", "ymm18", "ymm19",
3340 "ymm20", "ymm21", "ymm22", "ymm23",
3341 "ymm24", "ymm25", "ymm26", "ymm27",
3342 "ymm28", "ymm29", "ymm30", "ymm31"
3344 static const char *att_names_ymm
[] = {
3345 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3346 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3347 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3348 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3349 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3350 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3351 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3352 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3355 static const char **names_zmm
;
3356 static const char *intel_names_zmm
[] = {
3357 "zmm0", "zmm1", "zmm2", "zmm3",
3358 "zmm4", "zmm5", "zmm6", "zmm7",
3359 "zmm8", "zmm9", "zmm10", "zmm11",
3360 "zmm12", "zmm13", "zmm14", "zmm15",
3361 "zmm16", "zmm17", "zmm18", "zmm19",
3362 "zmm20", "zmm21", "zmm22", "zmm23",
3363 "zmm24", "zmm25", "zmm26", "zmm27",
3364 "zmm28", "zmm29", "zmm30", "zmm31"
3366 static const char *att_names_zmm
[] = {
3367 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3368 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3369 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3370 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3371 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3372 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3373 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3374 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3377 static const char **names_mask
;
3378 static const char *intel_names_mask
[] = {
3379 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3381 static const char *att_names_mask
[] = {
3382 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3385 static const char *names_rounding
[] =
3393 static const struct dis386 reg_table
[][8] = {
3396 { "addA", { Ebh1
, Ib
}, 0 },
3397 { "orA", { Ebh1
, Ib
}, 0 },
3398 { "adcA", { Ebh1
, Ib
}, 0 },
3399 { "sbbA", { Ebh1
, Ib
}, 0 },
3400 { "andA", { Ebh1
, Ib
}, 0 },
3401 { "subA", { Ebh1
, Ib
}, 0 },
3402 { "xorA", { Ebh1
, Ib
}, 0 },
3403 { "cmpA", { Eb
, Ib
}, 0 },
3407 { "addQ", { Evh1
, Iv
}, 0 },
3408 { "orQ", { Evh1
, Iv
}, 0 },
3409 { "adcQ", { Evh1
, Iv
}, 0 },
3410 { "sbbQ", { Evh1
, Iv
}, 0 },
3411 { "andQ", { Evh1
, Iv
}, 0 },
3412 { "subQ", { Evh1
, Iv
}, 0 },
3413 { "xorQ", { Evh1
, Iv
}, 0 },
3414 { "cmpQ", { Ev
, Iv
}, 0 },
3418 { "addQ", { Evh1
, sIb
}, 0 },
3419 { "orQ", { Evh1
, sIb
}, 0 },
3420 { "adcQ", { Evh1
, sIb
}, 0 },
3421 { "sbbQ", { Evh1
, sIb
}, 0 },
3422 { "andQ", { Evh1
, sIb
}, 0 },
3423 { "subQ", { Evh1
, sIb
}, 0 },
3424 { "xorQ", { Evh1
, sIb
}, 0 },
3425 { "cmpQ", { Ev
, sIb
}, 0 },
3429 { "popU", { stackEv
}, 0 },
3430 { XOP_8F_TABLE (XOP_09
) },
3434 { XOP_8F_TABLE (XOP_09
) },
3438 { "rolA", { Eb
, Ib
}, 0 },
3439 { "rorA", { Eb
, Ib
}, 0 },
3440 { "rclA", { Eb
, Ib
}, 0 },
3441 { "rcrA", { Eb
, Ib
}, 0 },
3442 { "shlA", { Eb
, Ib
}, 0 },
3443 { "shrA", { Eb
, Ib
}, 0 },
3445 { "sarA", { Eb
, Ib
}, 0 },
3449 { "rolQ", { Ev
, Ib
}, 0 },
3450 { "rorQ", { Ev
, Ib
}, 0 },
3451 { "rclQ", { Ev
, Ib
}, 0 },
3452 { "rcrQ", { Ev
, Ib
}, 0 },
3453 { "shlQ", { Ev
, Ib
}, 0 },
3454 { "shrQ", { Ev
, Ib
}, 0 },
3456 { "sarQ", { Ev
, Ib
}, 0 },
3460 { "movA", { Ebh3
, Ib
}, 0 },
3467 { MOD_TABLE (MOD_C6_REG_7
) },
3471 { "movQ", { Evh3
, Iv
}, 0 },
3478 { MOD_TABLE (MOD_C7_REG_7
) },
3482 { "rolA", { Eb
, I1
}, 0 },
3483 { "rorA", { Eb
, I1
}, 0 },
3484 { "rclA", { Eb
, I1
}, 0 },
3485 { "rcrA", { Eb
, I1
}, 0 },
3486 { "shlA", { Eb
, I1
}, 0 },
3487 { "shrA", { Eb
, I1
}, 0 },
3489 { "sarA", { Eb
, I1
}, 0 },
3493 { "rolQ", { Ev
, I1
}, 0 },
3494 { "rorQ", { Ev
, I1
}, 0 },
3495 { "rclQ", { Ev
, I1
}, 0 },
3496 { "rcrQ", { Ev
, I1
}, 0 },
3497 { "shlQ", { Ev
, I1
}, 0 },
3498 { "shrQ", { Ev
, I1
}, 0 },
3500 { "sarQ", { Ev
, I1
}, 0 },
3504 { "rolA", { Eb
, CL
}, 0 },
3505 { "rorA", { Eb
, CL
}, 0 },
3506 { "rclA", { Eb
, CL
}, 0 },
3507 { "rcrA", { Eb
, CL
}, 0 },
3508 { "shlA", { Eb
, CL
}, 0 },
3509 { "shrA", { Eb
, CL
}, 0 },
3511 { "sarA", { Eb
, CL
}, 0 },
3515 { "rolQ", { Ev
, CL
}, 0 },
3516 { "rorQ", { Ev
, CL
}, 0 },
3517 { "rclQ", { Ev
, CL
}, 0 },
3518 { "rcrQ", { Ev
, CL
}, 0 },
3519 { "shlQ", { Ev
, CL
}, 0 },
3520 { "shrQ", { Ev
, CL
}, 0 },
3522 { "sarQ", { Ev
, CL
}, 0 },
3526 { "testA", { Eb
, Ib
}, 0 },
3527 { "testA", { Eb
, Ib
}, 0 },
3528 { "notA", { Ebh1
}, 0 },
3529 { "negA", { Ebh1
}, 0 },
3530 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3531 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3532 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3533 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3537 { "testQ", { Ev
, Iv
}, 0 },
3538 { "testQ", { Ev
, Iv
}, 0 },
3539 { "notQ", { Evh1
}, 0 },
3540 { "negQ", { Evh1
}, 0 },
3541 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3542 { "imulQ", { Ev
}, 0 },
3543 { "divQ", { Ev
}, 0 },
3544 { "idivQ", { Ev
}, 0 },
3548 { "incA", { Ebh1
}, 0 },
3549 { "decA", { Ebh1
}, 0 },
3553 { "incQ", { Evh1
}, 0 },
3554 { "decQ", { Evh1
}, 0 },
3555 { "call{&|}", { indirEv
, NOTRACK
, BND
}, 0 },
3556 { MOD_TABLE (MOD_FF_REG_3
) },
3557 { "jmp{&|}", { indirEv
, NOTRACK
, BND
}, 0 },
3558 { MOD_TABLE (MOD_FF_REG_5
) },
3559 { "pushU", { stackEv
}, 0 },
3564 { "sldtD", { Sv
}, 0 },
3565 { "strD", { Sv
}, 0 },
3566 { "lldt", { Ew
}, 0 },
3567 { "ltr", { Ew
}, 0 },
3568 { "verr", { Ew
}, 0 },
3569 { "verw", { Ew
}, 0 },
3575 { MOD_TABLE (MOD_0F01_REG_0
) },
3576 { MOD_TABLE (MOD_0F01_REG_1
) },
3577 { MOD_TABLE (MOD_0F01_REG_2
) },
3578 { MOD_TABLE (MOD_0F01_REG_3
) },
3579 { "smswD", { Sv
}, 0 },
3580 { MOD_TABLE (MOD_0F01_REG_5
) },
3581 { "lmsw", { Ew
}, 0 },
3582 { MOD_TABLE (MOD_0F01_REG_7
) },
3586 { "prefetch", { Mb
}, 0 },
3587 { "prefetchw", { Mb
}, 0 },
3588 { "prefetchwt1", { Mb
}, 0 },
3589 { "prefetch", { Mb
}, 0 },
3590 { "prefetch", { Mb
}, 0 },
3591 { "prefetch", { Mb
}, 0 },
3592 { "prefetch", { Mb
}, 0 },
3593 { "prefetch", { Mb
}, 0 },
3597 { MOD_TABLE (MOD_0F18_REG_0
) },
3598 { MOD_TABLE (MOD_0F18_REG_1
) },
3599 { MOD_TABLE (MOD_0F18_REG_2
) },
3600 { MOD_TABLE (MOD_0F18_REG_3
) },
3601 { MOD_TABLE (MOD_0F18_REG_4
) },
3602 { MOD_TABLE (MOD_0F18_REG_5
) },
3603 { MOD_TABLE (MOD_0F18_REG_6
) },
3604 { MOD_TABLE (MOD_0F18_REG_7
) },
3606 /* REG_0F1E_MOD_3 */
3608 { "nopQ", { Ev
}, 0 },
3609 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3610 { "nopQ", { Ev
}, 0 },
3611 { "nopQ", { Ev
}, 0 },
3612 { "nopQ", { Ev
}, 0 },
3613 { "nopQ", { Ev
}, 0 },
3614 { "nopQ", { Ev
}, 0 },
3615 { RM_TABLE (RM_0F1E_MOD_3_REG_7
) },
3621 { MOD_TABLE (MOD_0F71_REG_2
) },
3623 { MOD_TABLE (MOD_0F71_REG_4
) },
3625 { MOD_TABLE (MOD_0F71_REG_6
) },
3631 { MOD_TABLE (MOD_0F72_REG_2
) },
3633 { MOD_TABLE (MOD_0F72_REG_4
) },
3635 { MOD_TABLE (MOD_0F72_REG_6
) },
3641 { MOD_TABLE (MOD_0F73_REG_2
) },
3642 { MOD_TABLE (MOD_0F73_REG_3
) },
3645 { MOD_TABLE (MOD_0F73_REG_6
) },
3646 { MOD_TABLE (MOD_0F73_REG_7
) },
3650 { "montmul", { { OP_0f07
, 0 } }, 0 },
3651 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3652 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3656 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3657 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3658 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3659 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3660 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3661 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3665 { MOD_TABLE (MOD_0FAE_REG_0
) },
3666 { MOD_TABLE (MOD_0FAE_REG_1
) },
3667 { MOD_TABLE (MOD_0FAE_REG_2
) },
3668 { MOD_TABLE (MOD_0FAE_REG_3
) },
3669 { MOD_TABLE (MOD_0FAE_REG_4
) },
3670 { MOD_TABLE (MOD_0FAE_REG_5
) },
3671 { MOD_TABLE (MOD_0FAE_REG_6
) },
3672 { MOD_TABLE (MOD_0FAE_REG_7
) },
3680 { "btQ", { Ev
, Ib
}, 0 },
3681 { "btsQ", { Evh1
, Ib
}, 0 },
3682 { "btrQ", { Evh1
, Ib
}, 0 },
3683 { "btcQ", { Evh1
, Ib
}, 0 },
3688 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3690 { MOD_TABLE (MOD_0FC7_REG_3
) },
3691 { MOD_TABLE (MOD_0FC7_REG_4
) },
3692 { MOD_TABLE (MOD_0FC7_REG_5
) },
3693 { MOD_TABLE (MOD_0FC7_REG_6
) },
3694 { MOD_TABLE (MOD_0FC7_REG_7
) },
3700 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3702 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3704 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3710 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3712 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3714 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3720 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3721 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3724 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3725 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3731 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3732 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3734 /* REG_VEX_0F38F3 */
3737 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3738 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3739 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3743 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3744 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3748 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3749 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3751 /* REG_XOP_TBM_01 */
3754 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3755 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3756 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3757 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3758 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3759 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3760 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3762 /* REG_XOP_TBM_02 */
3765 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3770 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3772 #define NEED_REG_TABLE
3773 #include "i386-dis-evex.h"
3774 #undef NEED_REG_TABLE
3777 static const struct dis386 prefix_table
[][4] = {
3780 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3781 { "pause", { XX
}, 0 },
3782 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3783 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3786 /* PREFIX_MOD_0_0F01_REG_5 */
3789 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3792 /* PREFIX_MOD_3_0F01_REG_5_RM_1 */
3795 { "incsspK", { Skip_MODRM
}, PREFIX_OPCODE
},
3798 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3801 { "savessp", { Skip_MODRM
}, PREFIX_OPCODE
},
3806 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3807 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3808 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3809 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3814 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3815 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3816 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3817 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3822 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3823 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3824 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3825 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3830 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3831 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3832 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3837 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3838 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3839 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3840 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3845 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3846 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3847 { "bndmov", { Ebnd
, Gbnd
}, 0 },
3848 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3853 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3854 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3855 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3856 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3861 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3862 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_OPCODE
},
3863 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3864 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3869 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3870 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3871 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3872 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3877 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3878 { "cvttss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3879 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3880 { "cvttsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3885 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3886 { "cvtss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3887 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3888 { "cvtsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3893 { "ucomiss",{ XM
, EXd
}, 0 },
3895 { "ucomisd",{ XM
, EXq
}, 0 },
3900 { "comiss", { XM
, EXd
}, 0 },
3902 { "comisd", { XM
, EXq
}, 0 },
3907 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3908 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3909 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3910 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3915 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3916 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3921 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3922 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3927 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3928 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3929 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3930 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3935 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3936 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3937 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3938 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3943 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3944 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3945 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3946 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3951 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3952 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3953 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3958 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3959 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3960 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3961 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3966 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3967 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3968 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3969 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3974 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3975 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3976 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3977 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3982 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3983 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3984 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3985 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3990 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3992 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3997 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3999 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
4004 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
4006 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
4013 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
4020 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
4025 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
4026 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
4027 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
4032 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
4033 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4034 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4035 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4038 /* PREFIX_0F73_REG_3 */
4042 { "psrldq", { XS
, Ib
}, 0 },
4045 /* PREFIX_0F73_REG_7 */
4049 { "pslldq", { XS
, Ib
}, 0 },
4054 {"vmread", { Em
, Gm
}, 0 },
4056 {"extrq", { XS
, Ib
, Ib
}, 0 },
4057 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
4062 {"vmwrite", { Gm
, Em
}, 0 },
4064 {"extrq", { XM
, XS
}, 0 },
4065 {"insertq", { XM
, XS
}, 0 },
4072 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
4073 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
4080 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
4081 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
4086 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
4087 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
4088 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
4093 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
4094 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
4095 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
4098 /* PREFIX_0FAE_REG_0 */
4101 { "rdfsbase", { Ev
}, 0 },
4104 /* PREFIX_0FAE_REG_1 */
4107 { "rdgsbase", { Ev
}, 0 },
4110 /* PREFIX_0FAE_REG_2 */
4113 { "wrfsbase", { Ev
}, 0 },
4116 /* PREFIX_0FAE_REG_3 */
4119 { "wrgsbase", { Ev
}, 0 },
4122 /* PREFIX_MOD_0_0FAE_REG_4 */
4124 { "xsave", { FXSAVE
}, 0 },
4125 { "ptwrite%LQ", { Edq
}, 0 },
4128 /* PREFIX_MOD_3_0FAE_REG_4 */
4131 { "ptwrite%LQ", { Edq
}, 0 },
4134 /* PREFIX_MOD_0_0FAE_REG_5 */
4136 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
4137 { "setssbsy", { Mq
}, PREFIX_OPCODE
},
4140 /* PREFIX_0FAE_REG_6 */
4142 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
4143 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
4144 { "clwb", { Mb
}, PREFIX_OPCODE
},
4147 /* PREFIX_0FAE_REG_7 */
4149 { "clflush", { Mb
}, 0 },
4151 { "clflushopt", { Mb
}, 0 },
4157 { "popcntS", { Gv
, Ev
}, 0 },
4162 { "bsfS", { Gv
, Ev
}, 0 },
4163 { "tzcntS", { Gv
, Ev
}, 0 },
4164 { "bsfS", { Gv
, Ev
}, 0 },
4169 { "bsrS", { Gv
, Ev
}, 0 },
4170 { "lzcntS", { Gv
, Ev
}, 0 },
4171 { "bsrS", { Gv
, Ev
}, 0 },
4176 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4177 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4178 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4179 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4182 /* PREFIX_MOD_0_0FC3 */
4184 { "movntiS", { Ev
, Gv
}, PREFIX_OPCODE
},
4187 /* PREFIX_MOD_0_0FC7_REG_6 */
4189 { "vmptrld",{ Mq
}, 0 },
4190 { "vmxon", { Mq
}, 0 },
4191 { "vmclear",{ Mq
}, 0 },
4194 /* PREFIX_MOD_3_0FC7_REG_6 */
4196 { "rdrand", { Ev
}, 0 },
4198 { "rdrand", { Ev
}, 0 }
4201 /* PREFIX_MOD_3_0FC7_REG_7 */
4203 { "rdseed", { Ev
}, 0 },
4204 { "rdpid", { Em
}, 0 },
4205 { "rdseed", { Ev
}, 0 },
4212 { "addsubpd", { XM
, EXx
}, 0 },
4213 { "addsubps", { XM
, EXx
}, 0 },
4219 { "movq2dq",{ XM
, MS
}, 0 },
4220 { "movq", { EXqS
, XM
}, 0 },
4221 { "movdq2q",{ MX
, XS
}, 0 },
4227 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4228 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4229 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4234 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4236 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4244 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4249 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4251 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4258 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4265 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4272 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4279 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4286 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4293 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4300 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4307 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4314 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4321 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4328 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4335 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4342 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4349 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4356 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4363 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4370 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4377 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4384 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4391 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4398 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4405 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4412 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4419 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4426 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4433 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4440 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4447 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4454 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4461 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4468 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4475 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4482 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4489 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4494 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4499 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4504 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4509 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4514 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4519 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4526 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4533 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4540 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4547 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4554 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4559 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4561 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4562 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4567 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4569 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4570 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4577 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4582 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4583 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4584 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4592 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4599 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4606 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4613 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4620 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4627 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4634 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4641 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4648 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4655 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4662 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4669 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4676 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4683 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4690 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4697 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4704 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4711 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4718 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4725 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4732 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4739 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4744 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4751 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4754 /* PREFIX_VEX_0F10 */
4756 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4757 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4758 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4759 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4762 /* PREFIX_VEX_0F11 */
4764 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4765 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4766 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4767 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4770 /* PREFIX_VEX_0F12 */
4772 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4773 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4774 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4775 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4778 /* PREFIX_VEX_0F16 */
4780 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4781 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4782 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4785 /* PREFIX_VEX_0F2A */
4788 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4790 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4793 /* PREFIX_VEX_0F2C */
4796 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4798 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4801 /* PREFIX_VEX_0F2D */
4804 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4806 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4809 /* PREFIX_VEX_0F2E */
4811 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4813 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4816 /* PREFIX_VEX_0F2F */
4818 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4820 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4823 /* PREFIX_VEX_0F41 */
4825 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4827 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4830 /* PREFIX_VEX_0F42 */
4832 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4834 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4837 /* PREFIX_VEX_0F44 */
4839 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4841 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4844 /* PREFIX_VEX_0F45 */
4846 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4848 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4851 /* PREFIX_VEX_0F46 */
4853 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4855 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4858 /* PREFIX_VEX_0F47 */
4860 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4862 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4865 /* PREFIX_VEX_0F4A */
4867 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4869 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4872 /* PREFIX_VEX_0F4B */
4874 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4876 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4879 /* PREFIX_VEX_0F51 */
4881 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4882 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4883 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4884 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4887 /* PREFIX_VEX_0F52 */
4889 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4890 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
4893 /* PREFIX_VEX_0F53 */
4895 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
4896 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
4899 /* PREFIX_VEX_0F58 */
4901 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
4902 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
4903 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
4904 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
4907 /* PREFIX_VEX_0F59 */
4909 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
4910 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
4911 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
4912 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
4915 /* PREFIX_VEX_0F5A */
4917 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
4918 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
4919 { "vcvtpd2ps%XY", { XMM
, EXx
}, 0 },
4920 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
4923 /* PREFIX_VEX_0F5B */
4925 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
4926 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
4927 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
4930 /* PREFIX_VEX_0F5C */
4932 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
4933 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
4934 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
4935 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
4938 /* PREFIX_VEX_0F5D */
4940 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
4941 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
4942 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
4943 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
4946 /* PREFIX_VEX_0F5E */
4948 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
4949 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
4950 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
4951 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
4954 /* PREFIX_VEX_0F5F */
4956 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
4957 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
4958 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
4959 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
4962 /* PREFIX_VEX_0F60 */
4966 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
4969 /* PREFIX_VEX_0F61 */
4973 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
4976 /* PREFIX_VEX_0F62 */
4980 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
4983 /* PREFIX_VEX_0F63 */
4987 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
4990 /* PREFIX_VEX_0F64 */
4994 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
4997 /* PREFIX_VEX_0F65 */
5001 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
5004 /* PREFIX_VEX_0F66 */
5008 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
5011 /* PREFIX_VEX_0F67 */
5015 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
5018 /* PREFIX_VEX_0F68 */
5022 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
5025 /* PREFIX_VEX_0F69 */
5029 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
5032 /* PREFIX_VEX_0F6A */
5036 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
5039 /* PREFIX_VEX_0F6B */
5043 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
5046 /* PREFIX_VEX_0F6C */
5050 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
5053 /* PREFIX_VEX_0F6D */
5057 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
5060 /* PREFIX_VEX_0F6E */
5064 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
5067 /* PREFIX_VEX_0F6F */
5070 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
5071 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
5074 /* PREFIX_VEX_0F70 */
5077 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
5078 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
5079 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
5082 /* PREFIX_VEX_0F71_REG_2 */
5086 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
5089 /* PREFIX_VEX_0F71_REG_4 */
5093 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
5096 /* PREFIX_VEX_0F71_REG_6 */
5100 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
5103 /* PREFIX_VEX_0F72_REG_2 */
5107 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
5110 /* PREFIX_VEX_0F72_REG_4 */
5114 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
5117 /* PREFIX_VEX_0F72_REG_6 */
5121 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
5124 /* PREFIX_VEX_0F73_REG_2 */
5128 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
5131 /* PREFIX_VEX_0F73_REG_3 */
5135 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
5138 /* PREFIX_VEX_0F73_REG_6 */
5142 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
5145 /* PREFIX_VEX_0F73_REG_7 */
5149 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
5152 /* PREFIX_VEX_0F74 */
5156 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
5159 /* PREFIX_VEX_0F75 */
5163 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
5166 /* PREFIX_VEX_0F76 */
5170 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
5173 /* PREFIX_VEX_0F77 */
5175 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
5178 /* PREFIX_VEX_0F7C */
5182 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
5183 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
5186 /* PREFIX_VEX_0F7D */
5190 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
5191 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
5194 /* PREFIX_VEX_0F7E */
5197 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5198 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5201 /* PREFIX_VEX_0F7F */
5204 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
5205 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
5208 /* PREFIX_VEX_0F90 */
5210 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5212 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5215 /* PREFIX_VEX_0F91 */
5217 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5219 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5222 /* PREFIX_VEX_0F92 */
5224 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5226 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5227 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5230 /* PREFIX_VEX_0F93 */
5232 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5234 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5235 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5238 /* PREFIX_VEX_0F98 */
5240 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5242 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5245 /* PREFIX_VEX_0F99 */
5247 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5249 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5252 /* PREFIX_VEX_0FC2 */
5254 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
5255 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
5256 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
5257 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
5260 /* PREFIX_VEX_0FC4 */
5264 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5267 /* PREFIX_VEX_0FC5 */
5271 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5274 /* PREFIX_VEX_0FD0 */
5278 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
5279 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
5282 /* PREFIX_VEX_0FD1 */
5286 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
5289 /* PREFIX_VEX_0FD2 */
5293 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
5296 /* PREFIX_VEX_0FD3 */
5300 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
5303 /* PREFIX_VEX_0FD4 */
5307 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
5310 /* PREFIX_VEX_0FD5 */
5314 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
5317 /* PREFIX_VEX_0FD6 */
5321 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5324 /* PREFIX_VEX_0FD7 */
5328 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5331 /* PREFIX_VEX_0FD8 */
5335 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
5338 /* PREFIX_VEX_0FD9 */
5342 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
5345 /* PREFIX_VEX_0FDA */
5349 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
5352 /* PREFIX_VEX_0FDB */
5356 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
5359 /* PREFIX_VEX_0FDC */
5363 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
5366 /* PREFIX_VEX_0FDD */
5370 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
5373 /* PREFIX_VEX_0FDE */
5377 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
5380 /* PREFIX_VEX_0FDF */
5384 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
5387 /* PREFIX_VEX_0FE0 */
5391 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
5394 /* PREFIX_VEX_0FE1 */
5398 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
5401 /* PREFIX_VEX_0FE2 */
5405 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
5408 /* PREFIX_VEX_0FE3 */
5412 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
5415 /* PREFIX_VEX_0FE4 */
5419 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
5422 /* PREFIX_VEX_0FE5 */
5426 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
5429 /* PREFIX_VEX_0FE6 */
5432 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
5433 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
5434 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5437 /* PREFIX_VEX_0FE7 */
5441 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5444 /* PREFIX_VEX_0FE8 */
5448 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5451 /* PREFIX_VEX_0FE9 */
5455 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5458 /* PREFIX_VEX_0FEA */
5462 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5465 /* PREFIX_VEX_0FEB */
5469 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5472 /* PREFIX_VEX_0FEC */
5476 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5479 /* PREFIX_VEX_0FED */
5483 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5486 /* PREFIX_VEX_0FEE */
5490 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5493 /* PREFIX_VEX_0FEF */
5497 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5500 /* PREFIX_VEX_0FF0 */
5505 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5508 /* PREFIX_VEX_0FF1 */
5512 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5515 /* PREFIX_VEX_0FF2 */
5519 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5522 /* PREFIX_VEX_0FF3 */
5526 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5529 /* PREFIX_VEX_0FF4 */
5533 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5536 /* PREFIX_VEX_0FF5 */
5540 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5543 /* PREFIX_VEX_0FF6 */
5547 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5550 /* PREFIX_VEX_0FF7 */
5554 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5557 /* PREFIX_VEX_0FF8 */
5561 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5564 /* PREFIX_VEX_0FF9 */
5568 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5571 /* PREFIX_VEX_0FFA */
5575 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5578 /* PREFIX_VEX_0FFB */
5582 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5585 /* PREFIX_VEX_0FFC */
5589 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5592 /* PREFIX_VEX_0FFD */
5596 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5599 /* PREFIX_VEX_0FFE */
5603 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5606 /* PREFIX_VEX_0F3800 */
5610 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5613 /* PREFIX_VEX_0F3801 */
5617 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5620 /* PREFIX_VEX_0F3802 */
5624 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5627 /* PREFIX_VEX_0F3803 */
5631 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5634 /* PREFIX_VEX_0F3804 */
5638 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5641 /* PREFIX_VEX_0F3805 */
5645 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5648 /* PREFIX_VEX_0F3806 */
5652 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5655 /* PREFIX_VEX_0F3807 */
5659 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5662 /* PREFIX_VEX_0F3808 */
5666 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5669 /* PREFIX_VEX_0F3809 */
5673 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5676 /* PREFIX_VEX_0F380A */
5680 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5683 /* PREFIX_VEX_0F380B */
5687 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5690 /* PREFIX_VEX_0F380C */
5694 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5697 /* PREFIX_VEX_0F380D */
5701 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5704 /* PREFIX_VEX_0F380E */
5708 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5711 /* PREFIX_VEX_0F380F */
5715 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5718 /* PREFIX_VEX_0F3813 */
5722 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5725 /* PREFIX_VEX_0F3816 */
5729 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5732 /* PREFIX_VEX_0F3817 */
5736 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5739 /* PREFIX_VEX_0F3818 */
5743 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5746 /* PREFIX_VEX_0F3819 */
5750 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5753 /* PREFIX_VEX_0F381A */
5757 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5760 /* PREFIX_VEX_0F381C */
5764 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5767 /* PREFIX_VEX_0F381D */
5771 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5774 /* PREFIX_VEX_0F381E */
5778 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5781 /* PREFIX_VEX_0F3820 */
5785 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5788 /* PREFIX_VEX_0F3821 */
5792 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5795 /* PREFIX_VEX_0F3822 */
5799 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5802 /* PREFIX_VEX_0F3823 */
5806 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5809 /* PREFIX_VEX_0F3824 */
5813 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5816 /* PREFIX_VEX_0F3825 */
5820 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5823 /* PREFIX_VEX_0F3828 */
5827 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5830 /* PREFIX_VEX_0F3829 */
5834 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5837 /* PREFIX_VEX_0F382A */
5841 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5844 /* PREFIX_VEX_0F382B */
5848 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5851 /* PREFIX_VEX_0F382C */
5855 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5858 /* PREFIX_VEX_0F382D */
5862 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5865 /* PREFIX_VEX_0F382E */
5869 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5872 /* PREFIX_VEX_0F382F */
5876 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5879 /* PREFIX_VEX_0F3830 */
5883 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5886 /* PREFIX_VEX_0F3831 */
5890 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
5893 /* PREFIX_VEX_0F3832 */
5897 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
5900 /* PREFIX_VEX_0F3833 */
5904 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
5907 /* PREFIX_VEX_0F3834 */
5911 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
5914 /* PREFIX_VEX_0F3835 */
5918 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
5921 /* PREFIX_VEX_0F3836 */
5925 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5928 /* PREFIX_VEX_0F3837 */
5932 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
5935 /* PREFIX_VEX_0F3838 */
5939 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
5942 /* PREFIX_VEX_0F3839 */
5946 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
5949 /* PREFIX_VEX_0F383A */
5953 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
5956 /* PREFIX_VEX_0F383B */
5960 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
5963 /* PREFIX_VEX_0F383C */
5967 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
5970 /* PREFIX_VEX_0F383D */
5974 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
5977 /* PREFIX_VEX_0F383E */
5981 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
5984 /* PREFIX_VEX_0F383F */
5988 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
5991 /* PREFIX_VEX_0F3840 */
5995 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
5998 /* PREFIX_VEX_0F3841 */
6002 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
6005 /* PREFIX_VEX_0F3845 */
6009 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
6012 /* PREFIX_VEX_0F3846 */
6016 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
6019 /* PREFIX_VEX_0F3847 */
6023 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
6026 /* PREFIX_VEX_0F3858 */
6030 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
6033 /* PREFIX_VEX_0F3859 */
6037 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
6040 /* PREFIX_VEX_0F385A */
6044 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
6047 /* PREFIX_VEX_0F3878 */
6051 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
6054 /* PREFIX_VEX_0F3879 */
6058 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
6061 /* PREFIX_VEX_0F388C */
6065 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
6068 /* PREFIX_VEX_0F388E */
6072 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
6075 /* PREFIX_VEX_0F3890 */
6079 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6082 /* PREFIX_VEX_0F3891 */
6086 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6089 /* PREFIX_VEX_0F3892 */
6093 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6096 /* PREFIX_VEX_0F3893 */
6100 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6103 /* PREFIX_VEX_0F3896 */
6107 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6110 /* PREFIX_VEX_0F3897 */
6114 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6117 /* PREFIX_VEX_0F3898 */
6121 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6124 /* PREFIX_VEX_0F3899 */
6128 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6131 /* PREFIX_VEX_0F389A */
6135 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6138 /* PREFIX_VEX_0F389B */
6142 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6145 /* PREFIX_VEX_0F389C */
6149 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6152 /* PREFIX_VEX_0F389D */
6156 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6159 /* PREFIX_VEX_0F389E */
6163 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6166 /* PREFIX_VEX_0F389F */
6170 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6173 /* PREFIX_VEX_0F38A6 */
6177 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6181 /* PREFIX_VEX_0F38A7 */
6185 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6188 /* PREFIX_VEX_0F38A8 */
6192 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6195 /* PREFIX_VEX_0F38A9 */
6199 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6202 /* PREFIX_VEX_0F38AA */
6206 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6209 /* PREFIX_VEX_0F38AB */
6213 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6216 /* PREFIX_VEX_0F38AC */
6220 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6223 /* PREFIX_VEX_0F38AD */
6227 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6230 /* PREFIX_VEX_0F38AE */
6234 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6237 /* PREFIX_VEX_0F38AF */
6241 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6244 /* PREFIX_VEX_0F38B6 */
6248 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6251 /* PREFIX_VEX_0F38B7 */
6255 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6258 /* PREFIX_VEX_0F38B8 */
6262 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6265 /* PREFIX_VEX_0F38B9 */
6269 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6272 /* PREFIX_VEX_0F38BA */
6276 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6279 /* PREFIX_VEX_0F38BB */
6283 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6286 /* PREFIX_VEX_0F38BC */
6290 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6293 /* PREFIX_VEX_0F38BD */
6297 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6300 /* PREFIX_VEX_0F38BE */
6304 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6307 /* PREFIX_VEX_0F38BF */
6311 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6314 /* PREFIX_VEX_0F38DB */
6318 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6321 /* PREFIX_VEX_0F38DC */
6325 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
6328 /* PREFIX_VEX_0F38DD */
6332 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
6335 /* PREFIX_VEX_0F38DE */
6339 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
6342 /* PREFIX_VEX_0F38DF */
6346 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
6349 /* PREFIX_VEX_0F38F2 */
6351 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6354 /* PREFIX_VEX_0F38F3_REG_1 */
6356 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6359 /* PREFIX_VEX_0F38F3_REG_2 */
6361 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6364 /* PREFIX_VEX_0F38F3_REG_3 */
6366 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6369 /* PREFIX_VEX_0F38F5 */
6371 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6372 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6374 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6377 /* PREFIX_VEX_0F38F6 */
6382 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6385 /* PREFIX_VEX_0F38F7 */
6387 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6388 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6389 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6390 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6393 /* PREFIX_VEX_0F3A00 */
6397 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6400 /* PREFIX_VEX_0F3A01 */
6404 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6407 /* PREFIX_VEX_0F3A02 */
6411 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6414 /* PREFIX_VEX_0F3A04 */
6418 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6421 /* PREFIX_VEX_0F3A05 */
6425 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6428 /* PREFIX_VEX_0F3A06 */
6432 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6435 /* PREFIX_VEX_0F3A08 */
6439 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6442 /* PREFIX_VEX_0F3A09 */
6446 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6449 /* PREFIX_VEX_0F3A0A */
6453 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6456 /* PREFIX_VEX_0F3A0B */
6460 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6463 /* PREFIX_VEX_0F3A0C */
6467 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6470 /* PREFIX_VEX_0F3A0D */
6474 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6477 /* PREFIX_VEX_0F3A0E */
6481 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6484 /* PREFIX_VEX_0F3A0F */
6488 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6491 /* PREFIX_VEX_0F3A14 */
6495 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6498 /* PREFIX_VEX_0F3A15 */
6502 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6505 /* PREFIX_VEX_0F3A16 */
6509 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6512 /* PREFIX_VEX_0F3A17 */
6516 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6519 /* PREFIX_VEX_0F3A18 */
6523 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6526 /* PREFIX_VEX_0F3A19 */
6530 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6533 /* PREFIX_VEX_0F3A1D */
6537 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6540 /* PREFIX_VEX_0F3A20 */
6544 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6547 /* PREFIX_VEX_0F3A21 */
6551 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6554 /* PREFIX_VEX_0F3A22 */
6558 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6561 /* PREFIX_VEX_0F3A30 */
6565 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6568 /* PREFIX_VEX_0F3A31 */
6572 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6575 /* PREFIX_VEX_0F3A32 */
6579 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6582 /* PREFIX_VEX_0F3A33 */
6586 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6589 /* PREFIX_VEX_0F3A38 */
6593 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6596 /* PREFIX_VEX_0F3A39 */
6600 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6603 /* PREFIX_VEX_0F3A40 */
6607 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6610 /* PREFIX_VEX_0F3A41 */
6614 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6617 /* PREFIX_VEX_0F3A42 */
6621 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6624 /* PREFIX_VEX_0F3A44 */
6628 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
6631 /* PREFIX_VEX_0F3A46 */
6635 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6638 /* PREFIX_VEX_0F3A48 */
6642 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6645 /* PREFIX_VEX_0F3A49 */
6649 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6652 /* PREFIX_VEX_0F3A4A */
6656 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6659 /* PREFIX_VEX_0F3A4B */
6663 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6666 /* PREFIX_VEX_0F3A4C */
6670 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6673 /* PREFIX_VEX_0F3A5C */
6677 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6680 /* PREFIX_VEX_0F3A5D */
6684 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6687 /* PREFIX_VEX_0F3A5E */
6691 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6694 /* PREFIX_VEX_0F3A5F */
6698 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6701 /* PREFIX_VEX_0F3A60 */
6705 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6709 /* PREFIX_VEX_0F3A61 */
6713 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6716 /* PREFIX_VEX_0F3A62 */
6720 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6723 /* PREFIX_VEX_0F3A63 */
6727 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6730 /* PREFIX_VEX_0F3A68 */
6734 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6737 /* PREFIX_VEX_0F3A69 */
6741 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6744 /* PREFIX_VEX_0F3A6A */
6748 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6751 /* PREFIX_VEX_0F3A6B */
6755 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6758 /* PREFIX_VEX_0F3A6C */
6762 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6765 /* PREFIX_VEX_0F3A6D */
6769 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6772 /* PREFIX_VEX_0F3A6E */
6776 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6779 /* PREFIX_VEX_0F3A6F */
6783 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6786 /* PREFIX_VEX_0F3A78 */
6790 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6793 /* PREFIX_VEX_0F3A79 */
6797 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6800 /* PREFIX_VEX_0F3A7A */
6804 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6807 /* PREFIX_VEX_0F3A7B */
6811 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6814 /* PREFIX_VEX_0F3A7C */
6818 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6822 /* PREFIX_VEX_0F3A7D */
6826 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6829 /* PREFIX_VEX_0F3A7E */
6833 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6836 /* PREFIX_VEX_0F3A7F */
6840 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6843 /* PREFIX_VEX_0F3ADF */
6847 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6850 /* PREFIX_VEX_0F3AF0 */
6855 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6858 #define NEED_PREFIX_TABLE
6859 #include "i386-dis-evex.h"
6860 #undef NEED_PREFIX_TABLE
6863 static const struct dis386 x86_64_table
[][2] = {
6866 { "pushP", { es
}, 0 },
6871 { "popP", { es
}, 0 },
6876 { "pushP", { cs
}, 0 },
6881 { "pushP", { ss
}, 0 },
6886 { "popP", { ss
}, 0 },
6891 { "pushP", { ds
}, 0 },
6896 { "popP", { ds
}, 0 },
6901 { "daa", { XX
}, 0 },
6906 { "das", { XX
}, 0 },
6911 { "aaa", { XX
}, 0 },
6916 { "aas", { XX
}, 0 },
6921 { "pushaP", { XX
}, 0 },
6926 { "popaP", { XX
}, 0 },
6931 { MOD_TABLE (MOD_62_32BIT
) },
6932 { EVEX_TABLE (EVEX_0F
) },
6937 { "arpl", { Ew
, Gw
}, 0 },
6938 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6943 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6944 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6949 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6950 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6955 /* Opcode 0x82 is an alias of of opcode 0x80 in 32-bit mode. */
6956 { REG_TABLE (REG_80
) },
6961 { "Jcall{T|}", { Ap
}, 0 },
6966 { MOD_TABLE (MOD_C4_32BIT
) },
6967 { VEX_C4_TABLE (VEX_0F
) },
6972 { MOD_TABLE (MOD_C5_32BIT
) },
6973 { VEX_C5_TABLE (VEX_0F
) },
6978 { "into", { XX
}, 0 },
6983 { "aam", { Ib
}, 0 },
6988 { "aad", { Ib
}, 0 },
6993 { "callP", { Jv
, BND
}, 0 },
6994 { "call@", { Jv
, BND
}, 0 }
6999 { "jmpP", { Jv
, BND
}, 0 },
7000 { "jmp@", { Jv
, BND
}, 0 }
7005 { "Jjmp{T|}", { Ap
}, 0 },
7008 /* X86_64_0F01_REG_0 */
7010 { "sgdt{Q|IQ}", { M
}, 0 },
7011 { "sgdt", { M
}, 0 },
7014 /* X86_64_0F01_REG_1 */
7016 { "sidt{Q|IQ}", { M
}, 0 },
7017 { "sidt", { M
}, 0 },
7020 /* X86_64_0F01_REG_2 */
7022 { "lgdt{Q|Q}", { M
}, 0 },
7023 { "lgdt", { M
}, 0 },
7026 /* X86_64_0F01_REG_3 */
7028 { "lidt{Q|Q}", { M
}, 0 },
7029 { "lidt", { M
}, 0 },
7033 static const struct dis386 three_byte_table
[][256] = {
7035 /* THREE_BYTE_0F38 */
7038 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
7039 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
7040 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
7041 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
7042 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
7043 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
7044 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
7045 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
7047 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
7048 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
7049 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
7050 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
7056 { PREFIX_TABLE (PREFIX_0F3810
) },
7060 { PREFIX_TABLE (PREFIX_0F3814
) },
7061 { PREFIX_TABLE (PREFIX_0F3815
) },
7063 { PREFIX_TABLE (PREFIX_0F3817
) },
7069 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7070 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7071 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7074 { PREFIX_TABLE (PREFIX_0F3820
) },
7075 { PREFIX_TABLE (PREFIX_0F3821
) },
7076 { PREFIX_TABLE (PREFIX_0F3822
) },
7077 { PREFIX_TABLE (PREFIX_0F3823
) },
7078 { PREFIX_TABLE (PREFIX_0F3824
) },
7079 { PREFIX_TABLE (PREFIX_0F3825
) },
7083 { PREFIX_TABLE (PREFIX_0F3828
) },
7084 { PREFIX_TABLE (PREFIX_0F3829
) },
7085 { PREFIX_TABLE (PREFIX_0F382A
) },
7086 { PREFIX_TABLE (PREFIX_0F382B
) },
7092 { PREFIX_TABLE (PREFIX_0F3830
) },
7093 { PREFIX_TABLE (PREFIX_0F3831
) },
7094 { PREFIX_TABLE (PREFIX_0F3832
) },
7095 { PREFIX_TABLE (PREFIX_0F3833
) },
7096 { PREFIX_TABLE (PREFIX_0F3834
) },
7097 { PREFIX_TABLE (PREFIX_0F3835
) },
7099 { PREFIX_TABLE (PREFIX_0F3837
) },
7101 { PREFIX_TABLE (PREFIX_0F3838
) },
7102 { PREFIX_TABLE (PREFIX_0F3839
) },
7103 { PREFIX_TABLE (PREFIX_0F383A
) },
7104 { PREFIX_TABLE (PREFIX_0F383B
) },
7105 { PREFIX_TABLE (PREFIX_0F383C
) },
7106 { PREFIX_TABLE (PREFIX_0F383D
) },
7107 { PREFIX_TABLE (PREFIX_0F383E
) },
7108 { PREFIX_TABLE (PREFIX_0F383F
) },
7110 { PREFIX_TABLE (PREFIX_0F3840
) },
7111 { PREFIX_TABLE (PREFIX_0F3841
) },
7182 { PREFIX_TABLE (PREFIX_0F3880
) },
7183 { PREFIX_TABLE (PREFIX_0F3881
) },
7184 { PREFIX_TABLE (PREFIX_0F3882
) },
7263 { PREFIX_TABLE (PREFIX_0F38C8
) },
7264 { PREFIX_TABLE (PREFIX_0F38C9
) },
7265 { PREFIX_TABLE (PREFIX_0F38CA
) },
7266 { PREFIX_TABLE (PREFIX_0F38CB
) },
7267 { PREFIX_TABLE (PREFIX_0F38CC
) },
7268 { PREFIX_TABLE (PREFIX_0F38CD
) },
7284 { PREFIX_TABLE (PREFIX_0F38DB
) },
7285 { PREFIX_TABLE (PREFIX_0F38DC
) },
7286 { PREFIX_TABLE (PREFIX_0F38DD
) },
7287 { PREFIX_TABLE (PREFIX_0F38DE
) },
7288 { PREFIX_TABLE (PREFIX_0F38DF
) },
7308 { PREFIX_TABLE (PREFIX_0F38F0
) },
7309 { PREFIX_TABLE (PREFIX_0F38F1
) },
7313 { PREFIX_TABLE (PREFIX_0F38F5
) },
7314 { PREFIX_TABLE (PREFIX_0F38F6
) },
7326 /* THREE_BYTE_0F3A */
7338 { PREFIX_TABLE (PREFIX_0F3A08
) },
7339 { PREFIX_TABLE (PREFIX_0F3A09
) },
7340 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7341 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7342 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7343 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7344 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7345 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7351 { PREFIX_TABLE (PREFIX_0F3A14
) },
7352 { PREFIX_TABLE (PREFIX_0F3A15
) },
7353 { PREFIX_TABLE (PREFIX_0F3A16
) },
7354 { PREFIX_TABLE (PREFIX_0F3A17
) },
7365 { PREFIX_TABLE (PREFIX_0F3A20
) },
7366 { PREFIX_TABLE (PREFIX_0F3A21
) },
7367 { PREFIX_TABLE (PREFIX_0F3A22
) },
7401 { PREFIX_TABLE (PREFIX_0F3A40
) },
7402 { PREFIX_TABLE (PREFIX_0F3A41
) },
7403 { PREFIX_TABLE (PREFIX_0F3A42
) },
7405 { PREFIX_TABLE (PREFIX_0F3A44
) },
7437 { PREFIX_TABLE (PREFIX_0F3A60
) },
7438 { PREFIX_TABLE (PREFIX_0F3A61
) },
7439 { PREFIX_TABLE (PREFIX_0F3A62
) },
7440 { PREFIX_TABLE (PREFIX_0F3A63
) },
7558 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7579 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7619 static const struct dis386 xop_table
[][256] = {
7772 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7773 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7774 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7782 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7783 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7790 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7791 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7792 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7800 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7801 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7805 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7806 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7809 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7827 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7839 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7840 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7841 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7842 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7852 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7853 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7854 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7855 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7888 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7889 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7890 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7891 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7915 { REG_TABLE (REG_XOP_TBM_01
) },
7916 { REG_TABLE (REG_XOP_TBM_02
) },
7934 { REG_TABLE (REG_XOP_LWPCB
) },
8058 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8059 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8060 { "vfrczss", { XM
, EXd
}, 0 },
8061 { "vfrczsd", { XM
, EXq
}, 0 },
8076 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8077 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8078 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8079 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8080 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8081 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8082 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8083 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8085 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8086 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8087 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8088 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8131 { "vphaddbw", { XM
, EXxmm
}, 0 },
8132 { "vphaddbd", { XM
, EXxmm
}, 0 },
8133 { "vphaddbq", { XM
, EXxmm
}, 0 },
8136 { "vphaddwd", { XM
, EXxmm
}, 0 },
8137 { "vphaddwq", { XM
, EXxmm
}, 0 },
8142 { "vphadddq", { XM
, EXxmm
}, 0 },
8149 { "vphaddubw", { XM
, EXxmm
}, 0 },
8150 { "vphaddubd", { XM
, EXxmm
}, 0 },
8151 { "vphaddubq", { XM
, EXxmm
}, 0 },
8154 { "vphadduwd", { XM
, EXxmm
}, 0 },
8155 { "vphadduwq", { XM
, EXxmm
}, 0 },
8160 { "vphaddudq", { XM
, EXxmm
}, 0 },
8167 { "vphsubbw", { XM
, EXxmm
}, 0 },
8168 { "vphsubwd", { XM
, EXxmm
}, 0 },
8169 { "vphsubdq", { XM
, EXxmm
}, 0 },
8223 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8225 { REG_TABLE (REG_XOP_LWP
) },
8495 static const struct dis386 vex_table
[][256] = {
8517 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8518 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8519 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8520 { MOD_TABLE (MOD_VEX_0F13
) },
8521 { VEX_W_TABLE (VEX_W_0F14
) },
8522 { VEX_W_TABLE (VEX_W_0F15
) },
8523 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8524 { MOD_TABLE (MOD_VEX_0F17
) },
8544 { VEX_W_TABLE (VEX_W_0F28
) },
8545 { VEX_W_TABLE (VEX_W_0F29
) },
8546 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8547 { MOD_TABLE (MOD_VEX_0F2B
) },
8548 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8549 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8550 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8551 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8572 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8573 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8575 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8576 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8577 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8578 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8582 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8583 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8589 { MOD_TABLE (MOD_VEX_0F50
) },
8590 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8591 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8592 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8593 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8594 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8595 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8596 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8598 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8599 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8600 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8601 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8602 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8603 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8604 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8605 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8607 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8608 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8609 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8610 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8611 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8612 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8613 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8614 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8616 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8617 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8618 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8619 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8620 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8621 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8622 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8623 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8625 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8626 { REG_TABLE (REG_VEX_0F71
) },
8627 { REG_TABLE (REG_VEX_0F72
) },
8628 { REG_TABLE (REG_VEX_0F73
) },
8629 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8630 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8631 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8632 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8638 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8639 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8640 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8641 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8661 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8662 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8663 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8664 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8694 { REG_TABLE (REG_VEX_0FAE
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8721 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8733 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8742 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8743 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8744 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8745 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8746 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8764 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8774 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8776 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8781 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8783 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8814 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8815 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8817 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8818 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8819 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8821 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8822 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8823 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8827 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8828 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8830 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8831 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8835 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8836 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8837 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8838 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8839 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8840 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8841 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8842 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8844 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8845 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8846 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8847 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8848 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8849 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8850 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8851 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8853 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8854 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8855 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8856 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8857 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8858 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8859 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8860 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8862 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8863 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8867 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8963 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8979 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8980 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8981 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8982 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8983 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8984 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8985 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8994 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8995 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
9036 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9063 { REG_TABLE (REG_VEX_0F38F3
) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9081 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9082 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9083 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9103 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9104 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9105 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9113 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9117 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9118 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9137 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9144 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9145 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9159 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9162 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9163 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9164 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9165 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9166 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9184 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9185 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9186 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9187 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9191 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9198 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9199 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9200 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9201 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9202 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9203 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9204 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9205 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9216 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9217 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9218 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9219 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9220 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9221 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9222 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9223 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9331 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9351 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9371 #define NEED_OPCODE_TABLE
9372 #include "i386-dis-evex.h"
9373 #undef NEED_OPCODE_TABLE
9374 static const struct dis386 vex_len_table
[][2] = {
9375 /* VEX_LEN_0F10_P_1 */
9377 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9378 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9381 /* VEX_LEN_0F10_P_3 */
9383 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9384 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9387 /* VEX_LEN_0F11_P_1 */
9389 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9390 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9393 /* VEX_LEN_0F11_P_3 */
9395 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9396 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9399 /* VEX_LEN_0F12_P_0_M_0 */
9401 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9404 /* VEX_LEN_0F12_P_0_M_1 */
9406 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9409 /* VEX_LEN_0F12_P_2 */
9411 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9414 /* VEX_LEN_0F13_M_0 */
9416 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9419 /* VEX_LEN_0F16_P_0_M_0 */
9421 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9424 /* VEX_LEN_0F16_P_0_M_1 */
9426 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9429 /* VEX_LEN_0F16_P_2 */
9431 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9434 /* VEX_LEN_0F17_M_0 */
9436 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9439 /* VEX_LEN_0F2A_P_1 */
9441 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9442 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9445 /* VEX_LEN_0F2A_P_3 */
9447 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9448 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9451 /* VEX_LEN_0F2C_P_1 */
9453 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9454 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9457 /* VEX_LEN_0F2C_P_3 */
9459 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9460 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9463 /* VEX_LEN_0F2D_P_1 */
9465 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9466 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9469 /* VEX_LEN_0F2D_P_3 */
9471 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9472 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9475 /* VEX_LEN_0F2E_P_0 */
9477 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9478 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9481 /* VEX_LEN_0F2E_P_2 */
9483 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9484 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9487 /* VEX_LEN_0F2F_P_0 */
9489 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9490 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9493 /* VEX_LEN_0F2F_P_2 */
9495 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9496 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9499 /* VEX_LEN_0F41_P_0 */
9502 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9504 /* VEX_LEN_0F41_P_2 */
9507 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9509 /* VEX_LEN_0F42_P_0 */
9512 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9514 /* VEX_LEN_0F42_P_2 */
9517 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9519 /* VEX_LEN_0F44_P_0 */
9521 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9523 /* VEX_LEN_0F44_P_2 */
9525 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9527 /* VEX_LEN_0F45_P_0 */
9530 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9532 /* VEX_LEN_0F45_P_2 */
9535 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9537 /* VEX_LEN_0F46_P_0 */
9540 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9542 /* VEX_LEN_0F46_P_2 */
9545 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9547 /* VEX_LEN_0F47_P_0 */
9550 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9552 /* VEX_LEN_0F47_P_2 */
9555 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9557 /* VEX_LEN_0F4A_P_0 */
9560 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9562 /* VEX_LEN_0F4A_P_2 */
9565 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9567 /* VEX_LEN_0F4B_P_0 */
9570 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9572 /* VEX_LEN_0F4B_P_2 */
9575 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9578 /* VEX_LEN_0F51_P_1 */
9580 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9581 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9584 /* VEX_LEN_0F51_P_3 */
9586 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9587 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9590 /* VEX_LEN_0F52_P_1 */
9592 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9593 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9596 /* VEX_LEN_0F53_P_1 */
9598 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9599 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9602 /* VEX_LEN_0F58_P_1 */
9604 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9605 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9608 /* VEX_LEN_0F58_P_3 */
9610 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9611 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9614 /* VEX_LEN_0F59_P_1 */
9616 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9617 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9620 /* VEX_LEN_0F59_P_3 */
9622 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9623 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9626 /* VEX_LEN_0F5A_P_1 */
9628 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9629 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9632 /* VEX_LEN_0F5A_P_3 */
9634 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9635 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9638 /* VEX_LEN_0F5C_P_1 */
9640 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9641 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9644 /* VEX_LEN_0F5C_P_3 */
9646 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9647 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9650 /* VEX_LEN_0F5D_P_1 */
9652 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9653 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9656 /* VEX_LEN_0F5D_P_3 */
9658 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9659 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9662 /* VEX_LEN_0F5E_P_1 */
9664 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9665 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9668 /* VEX_LEN_0F5E_P_3 */
9670 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9671 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9674 /* VEX_LEN_0F5F_P_1 */
9676 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9677 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9680 /* VEX_LEN_0F5F_P_3 */
9682 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9683 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9686 /* VEX_LEN_0F6E_P_2 */
9688 { "vmovK", { XMScalar
, Edq
}, 0 },
9689 { "vmovK", { XMScalar
, Edq
}, 0 },
9692 /* VEX_LEN_0F7E_P_1 */
9694 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9695 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9698 /* VEX_LEN_0F7E_P_2 */
9700 { "vmovK", { Edq
, XMScalar
}, 0 },
9701 { "vmovK", { Edq
, XMScalar
}, 0 },
9704 /* VEX_LEN_0F90_P_0 */
9706 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9709 /* VEX_LEN_0F90_P_2 */
9711 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9714 /* VEX_LEN_0F91_P_0 */
9716 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9719 /* VEX_LEN_0F91_P_2 */
9721 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9724 /* VEX_LEN_0F92_P_0 */
9726 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9729 /* VEX_LEN_0F92_P_2 */
9731 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9734 /* VEX_LEN_0F92_P_3 */
9736 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9739 /* VEX_LEN_0F93_P_0 */
9741 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9744 /* VEX_LEN_0F93_P_2 */
9746 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9749 /* VEX_LEN_0F93_P_3 */
9751 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9754 /* VEX_LEN_0F98_P_0 */
9756 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9759 /* VEX_LEN_0F98_P_2 */
9761 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9764 /* VEX_LEN_0F99_P_0 */
9766 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9769 /* VEX_LEN_0F99_P_2 */
9771 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9774 /* VEX_LEN_0FAE_R_2_M_0 */
9776 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
9779 /* VEX_LEN_0FAE_R_3_M_0 */
9781 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
9784 /* VEX_LEN_0FC2_P_1 */
9786 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9787 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9790 /* VEX_LEN_0FC2_P_3 */
9792 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9793 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9796 /* VEX_LEN_0FC4_P_2 */
9798 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
9801 /* VEX_LEN_0FC5_P_2 */
9803 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
9806 /* VEX_LEN_0FD6_P_2 */
9808 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9809 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9812 /* VEX_LEN_0FF7_P_2 */
9814 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
9817 /* VEX_LEN_0F3816_P_2 */
9820 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9823 /* VEX_LEN_0F3819_P_2 */
9826 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9829 /* VEX_LEN_0F381A_P_2_M_0 */
9832 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9835 /* VEX_LEN_0F3836_P_2 */
9838 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9841 /* VEX_LEN_0F3841_P_2 */
9843 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
9846 /* VEX_LEN_0F385A_P_2_M_0 */
9849 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9852 /* VEX_LEN_0F38DB_P_2 */
9854 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
9857 /* VEX_LEN_0F38DC_P_2 */
9859 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
9862 /* VEX_LEN_0F38DD_P_2 */
9864 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
9867 /* VEX_LEN_0F38DE_P_2 */
9869 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
9872 /* VEX_LEN_0F38DF_P_2 */
9874 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
9877 /* VEX_LEN_0F38F2_P_0 */
9879 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9882 /* VEX_LEN_0F38F3_R_1_P_0 */
9884 { "blsrS", { VexGdq
, Edq
}, 0 },
9887 /* VEX_LEN_0F38F3_R_2_P_0 */
9889 { "blsmskS", { VexGdq
, Edq
}, 0 },
9892 /* VEX_LEN_0F38F3_R_3_P_0 */
9894 { "blsiS", { VexGdq
, Edq
}, 0 },
9897 /* VEX_LEN_0F38F5_P_0 */
9899 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9902 /* VEX_LEN_0F38F5_P_1 */
9904 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9907 /* VEX_LEN_0F38F5_P_3 */
9909 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9912 /* VEX_LEN_0F38F6_P_3 */
9914 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9917 /* VEX_LEN_0F38F7_P_0 */
9919 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9922 /* VEX_LEN_0F38F7_P_1 */
9924 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9927 /* VEX_LEN_0F38F7_P_2 */
9929 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9932 /* VEX_LEN_0F38F7_P_3 */
9934 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9937 /* VEX_LEN_0F3A00_P_2 */
9940 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9943 /* VEX_LEN_0F3A01_P_2 */
9946 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9949 /* VEX_LEN_0F3A06_P_2 */
9952 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9955 /* VEX_LEN_0F3A0A_P_2 */
9957 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
9958 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
9961 /* VEX_LEN_0F3A0B_P_2 */
9963 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
9964 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
9967 /* VEX_LEN_0F3A14_P_2 */
9969 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
9972 /* VEX_LEN_0F3A15_P_2 */
9974 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
9977 /* VEX_LEN_0F3A16_P_2 */
9979 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9982 /* VEX_LEN_0F3A17_P_2 */
9984 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9987 /* VEX_LEN_0F3A18_P_2 */
9990 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9993 /* VEX_LEN_0F3A19_P_2 */
9996 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9999 /* VEX_LEN_0F3A20_P_2 */
10001 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
10004 /* VEX_LEN_0F3A21_P_2 */
10006 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
10009 /* VEX_LEN_0F3A22_P_2 */
10011 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
10014 /* VEX_LEN_0F3A30_P_2 */
10016 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
10019 /* VEX_LEN_0F3A31_P_2 */
10021 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
10024 /* VEX_LEN_0F3A32_P_2 */
10026 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
10029 /* VEX_LEN_0F3A33_P_2 */
10031 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
10034 /* VEX_LEN_0F3A38_P_2 */
10037 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
10040 /* VEX_LEN_0F3A39_P_2 */
10043 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
10046 /* VEX_LEN_0F3A41_P_2 */
10048 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
10051 /* VEX_LEN_0F3A44_P_2 */
10053 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
10056 /* VEX_LEN_0F3A46_P_2 */
10059 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
10062 /* VEX_LEN_0F3A60_P_2 */
10064 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
10067 /* VEX_LEN_0F3A61_P_2 */
10069 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
10072 /* VEX_LEN_0F3A62_P_2 */
10074 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
10077 /* VEX_LEN_0F3A63_P_2 */
10079 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
10082 /* VEX_LEN_0F3A6A_P_2 */
10084 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10087 /* VEX_LEN_0F3A6B_P_2 */
10089 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10092 /* VEX_LEN_0F3A6E_P_2 */
10094 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10097 /* VEX_LEN_0F3A6F_P_2 */
10099 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10102 /* VEX_LEN_0F3A7A_P_2 */
10104 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10107 /* VEX_LEN_0F3A7B_P_2 */
10109 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10112 /* VEX_LEN_0F3A7E_P_2 */
10114 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10117 /* VEX_LEN_0F3A7F_P_2 */
10119 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10122 /* VEX_LEN_0F3ADF_P_2 */
10124 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
10127 /* VEX_LEN_0F3AF0_P_3 */
10129 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
10132 /* VEX_LEN_0FXOP_08_CC */
10134 { "vpcomb", { XM
, Vex128
, EXx
, Ib
}, 0 },
10137 /* VEX_LEN_0FXOP_08_CD */
10139 { "vpcomw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10142 /* VEX_LEN_0FXOP_08_CE */
10144 { "vpcomd", { XM
, Vex128
, EXx
, Ib
}, 0 },
10147 /* VEX_LEN_0FXOP_08_CF */
10149 { "vpcomq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10152 /* VEX_LEN_0FXOP_08_EC */
10154 { "vpcomub", { XM
, Vex128
, EXx
, Ib
}, 0 },
10157 /* VEX_LEN_0FXOP_08_ED */
10159 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10162 /* VEX_LEN_0FXOP_08_EE */
10164 { "vpcomud", { XM
, Vex128
, EXx
, Ib
}, 0 },
10167 /* VEX_LEN_0FXOP_08_EF */
10169 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10172 /* VEX_LEN_0FXOP_09_80 */
10174 { "vfrczps", { XM
, EXxmm
}, 0 },
10175 { "vfrczps", { XM
, EXymmq
}, 0 },
10178 /* VEX_LEN_0FXOP_09_81 */
10180 { "vfrczpd", { XM
, EXxmm
}, 0 },
10181 { "vfrczpd", { XM
, EXymmq
}, 0 },
10185 static const struct dis386 vex_w_table
[][2] = {
10187 /* VEX_W_0F10_P_0 */
10188 { "vmovups", { XM
, EXx
}, 0 },
10191 /* VEX_W_0F10_P_1 */
10192 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
10195 /* VEX_W_0F10_P_2 */
10196 { "vmovupd", { XM
, EXx
}, 0 },
10199 /* VEX_W_0F10_P_3 */
10200 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
10203 /* VEX_W_0F11_P_0 */
10204 { "vmovups", { EXxS
, XM
}, 0 },
10207 /* VEX_W_0F11_P_1 */
10208 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
10211 /* VEX_W_0F11_P_2 */
10212 { "vmovupd", { EXxS
, XM
}, 0 },
10215 /* VEX_W_0F11_P_3 */
10216 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
10219 /* VEX_W_0F12_P_0_M_0 */
10220 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
10223 /* VEX_W_0F12_P_0_M_1 */
10224 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
10227 /* VEX_W_0F12_P_1 */
10228 { "vmovsldup", { XM
, EXx
}, 0 },
10231 /* VEX_W_0F12_P_2 */
10232 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
10235 /* VEX_W_0F12_P_3 */
10236 { "vmovddup", { XM
, EXymmq
}, 0 },
10239 /* VEX_W_0F13_M_0 */
10240 { "vmovlpX", { EXq
, XM
}, 0 },
10244 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
10248 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
10251 /* VEX_W_0F16_P_0_M_0 */
10252 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
10255 /* VEX_W_0F16_P_0_M_1 */
10256 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
10259 /* VEX_W_0F16_P_1 */
10260 { "vmovshdup", { XM
, EXx
}, 0 },
10263 /* VEX_W_0F16_P_2 */
10264 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
10267 /* VEX_W_0F17_M_0 */
10268 { "vmovhpX", { EXq
, XM
}, 0 },
10272 { "vmovapX", { XM
, EXx
}, 0 },
10276 { "vmovapX", { EXxS
, XM
}, 0 },
10279 /* VEX_W_0F2B_M_0 */
10280 { "vmovntpX", { Mx
, XM
}, 0 },
10283 /* VEX_W_0F2E_P_0 */
10284 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
10287 /* VEX_W_0F2E_P_2 */
10288 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
10291 /* VEX_W_0F2F_P_0 */
10292 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
10295 /* VEX_W_0F2F_P_2 */
10296 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
10299 /* VEX_W_0F41_P_0_LEN_1 */
10300 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
10301 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
10304 /* VEX_W_0F41_P_2_LEN_1 */
10305 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
10306 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
10309 /* VEX_W_0F42_P_0_LEN_1 */
10310 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
10311 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
10314 /* VEX_W_0F42_P_2_LEN_1 */
10315 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
10316 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
10319 /* VEX_W_0F44_P_0_LEN_0 */
10320 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
10321 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
10324 /* VEX_W_0F44_P_2_LEN_0 */
10325 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
10326 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
10329 /* VEX_W_0F45_P_0_LEN_1 */
10330 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
10331 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
10334 /* VEX_W_0F45_P_2_LEN_1 */
10335 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
10336 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
10339 /* VEX_W_0F46_P_0_LEN_1 */
10340 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
10341 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
10344 /* VEX_W_0F46_P_2_LEN_1 */
10345 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
10346 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
10349 /* VEX_W_0F47_P_0_LEN_1 */
10350 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
10351 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
10354 /* VEX_W_0F47_P_2_LEN_1 */
10355 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
10356 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
10359 /* VEX_W_0F4A_P_0_LEN_1 */
10360 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
10361 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
10364 /* VEX_W_0F4A_P_2_LEN_1 */
10365 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
10366 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
10369 /* VEX_W_0F4B_P_0_LEN_1 */
10370 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
10371 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
10374 /* VEX_W_0F4B_P_2_LEN_1 */
10375 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
10378 /* VEX_W_0F50_M_0 */
10379 { "vmovmskpX", { Gdq
, XS
}, 0 },
10382 /* VEX_W_0F51_P_0 */
10383 { "vsqrtps", { XM
, EXx
}, 0 },
10386 /* VEX_W_0F51_P_1 */
10387 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10390 /* VEX_W_0F51_P_2 */
10391 { "vsqrtpd", { XM
, EXx
}, 0 },
10394 /* VEX_W_0F51_P_3 */
10395 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10398 /* VEX_W_0F52_P_0 */
10399 { "vrsqrtps", { XM
, EXx
}, 0 },
10402 /* VEX_W_0F52_P_1 */
10403 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10406 /* VEX_W_0F53_P_0 */
10407 { "vrcpps", { XM
, EXx
}, 0 },
10410 /* VEX_W_0F53_P_1 */
10411 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10414 /* VEX_W_0F58_P_0 */
10415 { "vaddps", { XM
, Vex
, EXx
}, 0 },
10418 /* VEX_W_0F58_P_1 */
10419 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10422 /* VEX_W_0F58_P_2 */
10423 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
10426 /* VEX_W_0F58_P_3 */
10427 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10430 /* VEX_W_0F59_P_0 */
10431 { "vmulps", { XM
, Vex
, EXx
}, 0 },
10434 /* VEX_W_0F59_P_1 */
10435 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10438 /* VEX_W_0F59_P_2 */
10439 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
10442 /* VEX_W_0F59_P_3 */
10443 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10446 /* VEX_W_0F5A_P_0 */
10447 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
10450 /* VEX_W_0F5A_P_1 */
10451 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10454 /* VEX_W_0F5A_P_3 */
10455 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10458 /* VEX_W_0F5B_P_0 */
10459 { "vcvtdq2ps", { XM
, EXx
}, 0 },
10462 /* VEX_W_0F5B_P_1 */
10463 { "vcvttps2dq", { XM
, EXx
}, 0 },
10466 /* VEX_W_0F5B_P_2 */
10467 { "vcvtps2dq", { XM
, EXx
}, 0 },
10470 /* VEX_W_0F5C_P_0 */
10471 { "vsubps", { XM
, Vex
, EXx
}, 0 },
10474 /* VEX_W_0F5C_P_1 */
10475 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10478 /* VEX_W_0F5C_P_2 */
10479 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
10482 /* VEX_W_0F5C_P_3 */
10483 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10486 /* VEX_W_0F5D_P_0 */
10487 { "vminps", { XM
, Vex
, EXx
}, 0 },
10490 /* VEX_W_0F5D_P_1 */
10491 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10494 /* VEX_W_0F5D_P_2 */
10495 { "vminpd", { XM
, Vex
, EXx
}, 0 },
10498 /* VEX_W_0F5D_P_3 */
10499 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10502 /* VEX_W_0F5E_P_0 */
10503 { "vdivps", { XM
, Vex
, EXx
}, 0 },
10506 /* VEX_W_0F5E_P_1 */
10507 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10510 /* VEX_W_0F5E_P_2 */
10511 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
10514 /* VEX_W_0F5E_P_3 */
10515 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10518 /* VEX_W_0F5F_P_0 */
10519 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
10522 /* VEX_W_0F5F_P_1 */
10523 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10526 /* VEX_W_0F5F_P_2 */
10527 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
10530 /* VEX_W_0F5F_P_3 */
10531 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10534 /* VEX_W_0F60_P_2 */
10535 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
10538 /* VEX_W_0F61_P_2 */
10539 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
10542 /* VEX_W_0F62_P_2 */
10543 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
10546 /* VEX_W_0F63_P_2 */
10547 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
10550 /* VEX_W_0F64_P_2 */
10551 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
10554 /* VEX_W_0F65_P_2 */
10555 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
10558 /* VEX_W_0F66_P_2 */
10559 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
10562 /* VEX_W_0F67_P_2 */
10563 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
10566 /* VEX_W_0F68_P_2 */
10567 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
10570 /* VEX_W_0F69_P_2 */
10571 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
10574 /* VEX_W_0F6A_P_2 */
10575 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
10578 /* VEX_W_0F6B_P_2 */
10579 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
10582 /* VEX_W_0F6C_P_2 */
10583 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
10586 /* VEX_W_0F6D_P_2 */
10587 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
10590 /* VEX_W_0F6F_P_1 */
10591 { "vmovdqu", { XM
, EXx
}, 0 },
10594 /* VEX_W_0F6F_P_2 */
10595 { "vmovdqa", { XM
, EXx
}, 0 },
10598 /* VEX_W_0F70_P_1 */
10599 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
10602 /* VEX_W_0F70_P_2 */
10603 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
10606 /* VEX_W_0F70_P_3 */
10607 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
10610 /* VEX_W_0F71_R_2_P_2 */
10611 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
10614 /* VEX_W_0F71_R_4_P_2 */
10615 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
10618 /* VEX_W_0F71_R_6_P_2 */
10619 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
10622 /* VEX_W_0F72_R_2_P_2 */
10623 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
10626 /* VEX_W_0F72_R_4_P_2 */
10627 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
10630 /* VEX_W_0F72_R_6_P_2 */
10631 { "vpslld", { Vex
, XS
, Ib
}, 0 },
10634 /* VEX_W_0F73_R_2_P_2 */
10635 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
10638 /* VEX_W_0F73_R_3_P_2 */
10639 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
10642 /* VEX_W_0F73_R_6_P_2 */
10643 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
10646 /* VEX_W_0F73_R_7_P_2 */
10647 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
10650 /* VEX_W_0F74_P_2 */
10651 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
10654 /* VEX_W_0F75_P_2 */
10655 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
10658 /* VEX_W_0F76_P_2 */
10659 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
10662 /* VEX_W_0F77_P_0 */
10663 { "", { VZERO
}, 0 },
10666 /* VEX_W_0F7C_P_2 */
10667 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
10670 /* VEX_W_0F7C_P_3 */
10671 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
10674 /* VEX_W_0F7D_P_2 */
10675 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
10678 /* VEX_W_0F7D_P_3 */
10679 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
10682 /* VEX_W_0F7E_P_1 */
10683 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
10686 /* VEX_W_0F7F_P_1 */
10687 { "vmovdqu", { EXxS
, XM
}, 0 },
10690 /* VEX_W_0F7F_P_2 */
10691 { "vmovdqa", { EXxS
, XM
}, 0 },
10694 /* VEX_W_0F90_P_0_LEN_0 */
10695 { "kmovw", { MaskG
, MaskE
}, 0 },
10696 { "kmovq", { MaskG
, MaskE
}, 0 },
10699 /* VEX_W_0F90_P_2_LEN_0 */
10700 { "kmovb", { MaskG
, MaskBDE
}, 0 },
10701 { "kmovd", { MaskG
, MaskBDE
}, 0 },
10704 /* VEX_W_0F91_P_0_LEN_0 */
10705 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
10706 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
10709 /* VEX_W_0F91_P_2_LEN_0 */
10710 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
10711 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
10714 /* VEX_W_0F92_P_0_LEN_0 */
10715 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10718 /* VEX_W_0F92_P_2_LEN_0 */
10719 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10722 /* VEX_W_0F92_P_3_LEN_0 */
10723 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0
) },
10724 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0
) },
10727 /* VEX_W_0F93_P_0_LEN_0 */
10728 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10731 /* VEX_W_0F93_P_2_LEN_0 */
10732 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10735 /* VEX_W_0F93_P_3_LEN_0 */
10736 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0
) },
10737 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0
) },
10740 /* VEX_W_0F98_P_0_LEN_0 */
10741 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10742 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10745 /* VEX_W_0F98_P_2_LEN_0 */
10746 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10747 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10750 /* VEX_W_0F99_P_0_LEN_0 */
10751 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10752 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10755 /* VEX_W_0F99_P_2_LEN_0 */
10756 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10757 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10760 /* VEX_W_0FAE_R_2_M_0 */
10761 { "vldmxcsr", { Md
}, 0 },
10764 /* VEX_W_0FAE_R_3_M_0 */
10765 { "vstmxcsr", { Md
}, 0 },
10768 /* VEX_W_0FC2_P_0 */
10769 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
10772 /* VEX_W_0FC2_P_1 */
10773 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
10776 /* VEX_W_0FC2_P_2 */
10777 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
10780 /* VEX_W_0FC2_P_3 */
10781 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
10784 /* VEX_W_0FC4_P_2 */
10785 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
10788 /* VEX_W_0FC5_P_2 */
10789 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
10792 /* VEX_W_0FD0_P_2 */
10793 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
10796 /* VEX_W_0FD0_P_3 */
10797 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
10800 /* VEX_W_0FD1_P_2 */
10801 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
10804 /* VEX_W_0FD2_P_2 */
10805 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
10808 /* VEX_W_0FD3_P_2 */
10809 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
10812 /* VEX_W_0FD4_P_2 */
10813 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
10816 /* VEX_W_0FD5_P_2 */
10817 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
10820 /* VEX_W_0FD6_P_2 */
10821 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
10824 /* VEX_W_0FD7_P_2_M_1 */
10825 { "vpmovmskb", { Gdq
, XS
}, 0 },
10828 /* VEX_W_0FD8_P_2 */
10829 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
10832 /* VEX_W_0FD9_P_2 */
10833 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
10836 /* VEX_W_0FDA_P_2 */
10837 { "vpminub", { XM
, Vex
, EXx
}, 0 },
10840 /* VEX_W_0FDB_P_2 */
10841 { "vpand", { XM
, Vex
, EXx
}, 0 },
10844 /* VEX_W_0FDC_P_2 */
10845 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
10848 /* VEX_W_0FDD_P_2 */
10849 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
10852 /* VEX_W_0FDE_P_2 */
10853 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
10856 /* VEX_W_0FDF_P_2 */
10857 { "vpandn", { XM
, Vex
, EXx
}, 0 },
10860 /* VEX_W_0FE0_P_2 */
10861 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
10864 /* VEX_W_0FE1_P_2 */
10865 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
10868 /* VEX_W_0FE2_P_2 */
10869 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
10872 /* VEX_W_0FE3_P_2 */
10873 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
10876 /* VEX_W_0FE4_P_2 */
10877 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
10880 /* VEX_W_0FE5_P_2 */
10881 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
10884 /* VEX_W_0FE6_P_1 */
10885 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
10888 /* VEX_W_0FE6_P_2 */
10889 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
10892 /* VEX_W_0FE6_P_3 */
10893 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
10896 /* VEX_W_0FE7_P_2_M_0 */
10897 { "vmovntdq", { Mx
, XM
}, 0 },
10900 /* VEX_W_0FE8_P_2 */
10901 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
10904 /* VEX_W_0FE9_P_2 */
10905 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
10908 /* VEX_W_0FEA_P_2 */
10909 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
10912 /* VEX_W_0FEB_P_2 */
10913 { "vpor", { XM
, Vex
, EXx
}, 0 },
10916 /* VEX_W_0FEC_P_2 */
10917 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
10920 /* VEX_W_0FED_P_2 */
10921 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
10924 /* VEX_W_0FEE_P_2 */
10925 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
10928 /* VEX_W_0FEF_P_2 */
10929 { "vpxor", { XM
, Vex
, EXx
}, 0 },
10932 /* VEX_W_0FF0_P_3_M_0 */
10933 { "vlddqu", { XM
, M
}, 0 },
10936 /* VEX_W_0FF1_P_2 */
10937 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
10940 /* VEX_W_0FF2_P_2 */
10941 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
10944 /* VEX_W_0FF3_P_2 */
10945 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
10948 /* VEX_W_0FF4_P_2 */
10949 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
10952 /* VEX_W_0FF5_P_2 */
10953 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
10956 /* VEX_W_0FF6_P_2 */
10957 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
10960 /* VEX_W_0FF7_P_2 */
10961 { "vmaskmovdqu", { XM
, XS
}, 0 },
10964 /* VEX_W_0FF8_P_2 */
10965 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
10968 /* VEX_W_0FF9_P_2 */
10969 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
10972 /* VEX_W_0FFA_P_2 */
10973 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
10976 /* VEX_W_0FFB_P_2 */
10977 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
10980 /* VEX_W_0FFC_P_2 */
10981 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
10984 /* VEX_W_0FFD_P_2 */
10985 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
10988 /* VEX_W_0FFE_P_2 */
10989 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
10992 /* VEX_W_0F3800_P_2 */
10993 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
10996 /* VEX_W_0F3801_P_2 */
10997 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
11000 /* VEX_W_0F3802_P_2 */
11001 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
11004 /* VEX_W_0F3803_P_2 */
11005 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
11008 /* VEX_W_0F3804_P_2 */
11009 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
11012 /* VEX_W_0F3805_P_2 */
11013 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
11016 /* VEX_W_0F3806_P_2 */
11017 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
11020 /* VEX_W_0F3807_P_2 */
11021 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
11024 /* VEX_W_0F3808_P_2 */
11025 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
11028 /* VEX_W_0F3809_P_2 */
11029 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
11032 /* VEX_W_0F380A_P_2 */
11033 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
11036 /* VEX_W_0F380B_P_2 */
11037 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
11040 /* VEX_W_0F380C_P_2 */
11041 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
11044 /* VEX_W_0F380D_P_2 */
11045 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
11048 /* VEX_W_0F380E_P_2 */
11049 { "vtestps", { XM
, EXx
}, 0 },
11052 /* VEX_W_0F380F_P_2 */
11053 { "vtestpd", { XM
, EXx
}, 0 },
11056 /* VEX_W_0F3816_P_2 */
11057 { "vpermps", { XM
, Vex
, EXx
}, 0 },
11060 /* VEX_W_0F3817_P_2 */
11061 { "vptest", { XM
, EXx
}, 0 },
11064 /* VEX_W_0F3818_P_2 */
11065 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
11068 /* VEX_W_0F3819_P_2 */
11069 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
11072 /* VEX_W_0F381A_P_2_M_0 */
11073 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
11076 /* VEX_W_0F381C_P_2 */
11077 { "vpabsb", { XM
, EXx
}, 0 },
11080 /* VEX_W_0F381D_P_2 */
11081 { "vpabsw", { XM
, EXx
}, 0 },
11084 /* VEX_W_0F381E_P_2 */
11085 { "vpabsd", { XM
, EXx
}, 0 },
11088 /* VEX_W_0F3820_P_2 */
11089 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
11092 /* VEX_W_0F3821_P_2 */
11093 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
11096 /* VEX_W_0F3822_P_2 */
11097 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
11100 /* VEX_W_0F3823_P_2 */
11101 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
11104 /* VEX_W_0F3824_P_2 */
11105 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
11108 /* VEX_W_0F3825_P_2 */
11109 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
11112 /* VEX_W_0F3828_P_2 */
11113 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
11116 /* VEX_W_0F3829_P_2 */
11117 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
11120 /* VEX_W_0F382A_P_2_M_0 */
11121 { "vmovntdqa", { XM
, Mx
}, 0 },
11124 /* VEX_W_0F382B_P_2 */
11125 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
11128 /* VEX_W_0F382C_P_2_M_0 */
11129 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
11132 /* VEX_W_0F382D_P_2_M_0 */
11133 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
11136 /* VEX_W_0F382E_P_2_M_0 */
11137 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
11140 /* VEX_W_0F382F_P_2_M_0 */
11141 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
11144 /* VEX_W_0F3830_P_2 */
11145 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
11148 /* VEX_W_0F3831_P_2 */
11149 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
11152 /* VEX_W_0F3832_P_2 */
11153 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
11156 /* VEX_W_0F3833_P_2 */
11157 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
11160 /* VEX_W_0F3834_P_2 */
11161 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
11164 /* VEX_W_0F3835_P_2 */
11165 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
11168 /* VEX_W_0F3836_P_2 */
11169 { "vpermd", { XM
, Vex
, EXx
}, 0 },
11172 /* VEX_W_0F3837_P_2 */
11173 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
11176 /* VEX_W_0F3838_P_2 */
11177 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
11180 /* VEX_W_0F3839_P_2 */
11181 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
11184 /* VEX_W_0F383A_P_2 */
11185 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
11188 /* VEX_W_0F383B_P_2 */
11189 { "vpminud", { XM
, Vex
, EXx
}, 0 },
11192 /* VEX_W_0F383C_P_2 */
11193 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
11196 /* VEX_W_0F383D_P_2 */
11197 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
11200 /* VEX_W_0F383E_P_2 */
11201 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
11204 /* VEX_W_0F383F_P_2 */
11205 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
11208 /* VEX_W_0F3840_P_2 */
11209 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
11212 /* VEX_W_0F3841_P_2 */
11213 { "vphminposuw", { XM
, EXx
}, 0 },
11216 /* VEX_W_0F3846_P_2 */
11217 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
11220 /* VEX_W_0F3858_P_2 */
11221 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
11224 /* VEX_W_0F3859_P_2 */
11225 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
11228 /* VEX_W_0F385A_P_2_M_0 */
11229 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
11232 /* VEX_W_0F3878_P_2 */
11233 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
11236 /* VEX_W_0F3879_P_2 */
11237 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
11240 /* VEX_W_0F38DB_P_2 */
11241 { "vaesimc", { XM
, EXx
}, 0 },
11244 /* VEX_W_0F38DC_P_2 */
11245 { "vaesenc", { XM
, Vex128
, EXx
}, 0 },
11248 /* VEX_W_0F38DD_P_2 */
11249 { "vaesenclast", { XM
, Vex128
, EXx
}, 0 },
11252 /* VEX_W_0F38DE_P_2 */
11253 { "vaesdec", { XM
, Vex128
, EXx
}, 0 },
11256 /* VEX_W_0F38DF_P_2 */
11257 { "vaesdeclast", { XM
, Vex128
, EXx
}, 0 },
11260 /* VEX_W_0F3A00_P_2 */
11262 { "vpermq", { XM
, EXx
, Ib
}, 0 },
11265 /* VEX_W_0F3A01_P_2 */
11267 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
11270 /* VEX_W_0F3A02_P_2 */
11271 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
11274 /* VEX_W_0F3A04_P_2 */
11275 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
11278 /* VEX_W_0F3A05_P_2 */
11279 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
11282 /* VEX_W_0F3A06_P_2 */
11283 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11286 /* VEX_W_0F3A08_P_2 */
11287 { "vroundps", { XM
, EXx
, Ib
}, 0 },
11290 /* VEX_W_0F3A09_P_2 */
11291 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
11294 /* VEX_W_0F3A0A_P_2 */
11295 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
11298 /* VEX_W_0F3A0B_P_2 */
11299 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
11302 /* VEX_W_0F3A0C_P_2 */
11303 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
11306 /* VEX_W_0F3A0D_P_2 */
11307 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
11310 /* VEX_W_0F3A0E_P_2 */
11311 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
11314 /* VEX_W_0F3A0F_P_2 */
11315 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
11318 /* VEX_W_0F3A14_P_2 */
11319 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
11322 /* VEX_W_0F3A15_P_2 */
11323 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
11326 /* VEX_W_0F3A18_P_2 */
11327 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11330 /* VEX_W_0F3A19_P_2 */
11331 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
11334 /* VEX_W_0F3A20_P_2 */
11335 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
11338 /* VEX_W_0F3A21_P_2 */
11339 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
11342 /* VEX_W_0F3A30_P_2_LEN_0 */
11343 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
11344 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
11347 /* VEX_W_0F3A31_P_2_LEN_0 */
11348 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
11349 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
11352 /* VEX_W_0F3A32_P_2_LEN_0 */
11353 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
11354 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
11357 /* VEX_W_0F3A33_P_2_LEN_0 */
11358 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
11359 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
11362 /* VEX_W_0F3A38_P_2 */
11363 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11366 /* VEX_W_0F3A39_P_2 */
11367 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
11370 /* VEX_W_0F3A40_P_2 */
11371 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
11374 /* VEX_W_0F3A41_P_2 */
11375 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
11378 /* VEX_W_0F3A42_P_2 */
11379 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
11382 /* VEX_W_0F3A44_P_2 */
11383 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
}, 0 },
11386 /* VEX_W_0F3A46_P_2 */
11387 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11390 /* VEX_W_0F3A48_P_2 */
11391 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11392 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11395 /* VEX_W_0F3A49_P_2 */
11396 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11397 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11400 /* VEX_W_0F3A4A_P_2 */
11401 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11404 /* VEX_W_0F3A4B_P_2 */
11405 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11408 /* VEX_W_0F3A4C_P_2 */
11409 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11412 /* VEX_W_0F3A62_P_2 */
11413 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
11416 /* VEX_W_0F3A63_P_2 */
11417 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
11420 /* VEX_W_0F3ADF_P_2 */
11421 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
11423 #define NEED_VEX_W_TABLE
11424 #include "i386-dis-evex.h"
11425 #undef NEED_VEX_W_TABLE
11428 static const struct dis386 mod_table
[][2] = {
11431 { "leaS", { Gv
, M
}, 0 },
11436 { RM_TABLE (RM_C6_REG_7
) },
11441 { RM_TABLE (RM_C7_REG_7
) },
11445 { "Jcall^", { indirEp
}, 0 },
11449 { "Jjmp^", { indirEp
}, 0 },
11452 /* MOD_0F01_REG_0 */
11453 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11454 { RM_TABLE (RM_0F01_REG_0
) },
11457 /* MOD_0F01_REG_1 */
11458 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11459 { RM_TABLE (RM_0F01_REG_1
) },
11462 /* MOD_0F01_REG_2 */
11463 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11464 { RM_TABLE (RM_0F01_REG_2
) },
11467 /* MOD_0F01_REG_3 */
11468 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11469 { RM_TABLE (RM_0F01_REG_3
) },
11472 /* MOD_0F01_REG_5 */
11473 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5
) },
11474 { RM_TABLE (RM_0F01_REG_5
) },
11477 /* MOD_0F01_REG_7 */
11478 { "invlpg", { Mb
}, 0 },
11479 { RM_TABLE (RM_0F01_REG_7
) },
11482 /* MOD_0F12_PREFIX_0 */
11483 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
11484 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
11488 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
11491 /* MOD_0F16_PREFIX_0 */
11492 { "movhps", { XM
, EXq
}, 0 },
11493 { "movlhps", { XM
, EXq
}, 0 },
11497 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
11500 /* MOD_0F18_REG_0 */
11501 { "prefetchnta", { Mb
}, 0 },
11504 /* MOD_0F18_REG_1 */
11505 { "prefetcht0", { Mb
}, 0 },
11508 /* MOD_0F18_REG_2 */
11509 { "prefetcht1", { Mb
}, 0 },
11512 /* MOD_0F18_REG_3 */
11513 { "prefetcht2", { Mb
}, 0 },
11516 /* MOD_0F18_REG_4 */
11517 { "nop/reserved", { Mb
}, 0 },
11520 /* MOD_0F18_REG_5 */
11521 { "nop/reserved", { Mb
}, 0 },
11524 /* MOD_0F18_REG_6 */
11525 { "nop/reserved", { Mb
}, 0 },
11528 /* MOD_0F18_REG_7 */
11529 { "nop/reserved", { Mb
}, 0 },
11532 /* MOD_0F1A_PREFIX_0 */
11533 { "bndldx", { Gbnd
, Ev_bnd
}, 0 },
11534 { "nopQ", { Ev
}, 0 },
11537 /* MOD_0F1B_PREFIX_0 */
11538 { "bndstx", { Ev_bnd
, Gbnd
}, 0 },
11539 { "nopQ", { Ev
}, 0 },
11542 /* MOD_0F1B_PREFIX_1 */
11543 { "bndmk", { Gbnd
, Ev_bnd
}, 0 },
11544 { "nopQ", { Ev
}, 0 },
11547 /* MOD_0F1E_PREFIX_1 */
11548 { "nopQ", { Ev
}, 0 },
11549 { REG_TABLE (REG_0F1E_MOD_3
) },
11554 { "movL", { Rd
, Td
}, 0 },
11559 { "movL", { Td
, Rd
}, 0 },
11562 /* MOD_0F2B_PREFIX_0 */
11563 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
11566 /* MOD_0F2B_PREFIX_1 */
11567 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
11570 /* MOD_0F2B_PREFIX_2 */
11571 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
11574 /* MOD_0F2B_PREFIX_3 */
11575 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
11580 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
11583 /* MOD_0F71_REG_2 */
11585 { "psrlw", { MS
, Ib
}, 0 },
11588 /* MOD_0F71_REG_4 */
11590 { "psraw", { MS
, Ib
}, 0 },
11593 /* MOD_0F71_REG_6 */
11595 { "psllw", { MS
, Ib
}, 0 },
11598 /* MOD_0F72_REG_2 */
11600 { "psrld", { MS
, Ib
}, 0 },
11603 /* MOD_0F72_REG_4 */
11605 { "psrad", { MS
, Ib
}, 0 },
11608 /* MOD_0F72_REG_6 */
11610 { "pslld", { MS
, Ib
}, 0 },
11613 /* MOD_0F73_REG_2 */
11615 { "psrlq", { MS
, Ib
}, 0 },
11618 /* MOD_0F73_REG_3 */
11620 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11623 /* MOD_0F73_REG_6 */
11625 { "psllq", { MS
, Ib
}, 0 },
11628 /* MOD_0F73_REG_7 */
11630 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11633 /* MOD_0FAE_REG_0 */
11634 { "fxsave", { FXSAVE
}, 0 },
11635 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11638 /* MOD_0FAE_REG_1 */
11639 { "fxrstor", { FXSAVE
}, 0 },
11640 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11643 /* MOD_0FAE_REG_2 */
11644 { "ldmxcsr", { Md
}, 0 },
11645 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11648 /* MOD_0FAE_REG_3 */
11649 { "stmxcsr", { Md
}, 0 },
11650 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11653 /* MOD_0FAE_REG_4 */
11654 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4
) },
11655 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4
) },
11658 /* MOD_0FAE_REG_5 */
11659 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5
) },
11660 { RM_TABLE (RM_0FAE_REG_5
) },
11663 /* MOD_0FAE_REG_6 */
11664 { PREFIX_TABLE (PREFIX_0FAE_REG_6
) },
11665 { RM_TABLE (RM_0FAE_REG_6
) },
11668 /* MOD_0FAE_REG_7 */
11669 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11670 { RM_TABLE (RM_0FAE_REG_7
) },
11674 { "lssS", { Gv
, Mp
}, 0 },
11678 { "lfsS", { Gv
, Mp
}, 0 },
11682 { "lgsS", { Gv
, Mp
}, 0 },
11686 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
11689 /* MOD_0FC7_REG_3 */
11690 { "xrstors", { FXSAVE
}, 0 },
11693 /* MOD_0FC7_REG_4 */
11694 { "xsavec", { FXSAVE
}, 0 },
11697 /* MOD_0FC7_REG_5 */
11698 { "xsaves", { FXSAVE
}, 0 },
11701 /* MOD_0FC7_REG_6 */
11702 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
11703 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
11706 /* MOD_0FC7_REG_7 */
11707 { "vmptrst", { Mq
}, 0 },
11708 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
11713 { "pmovmskb", { Gdq
, MS
}, 0 },
11716 /* MOD_0FE7_PREFIX_2 */
11717 { "movntdq", { Mx
, XM
}, 0 },
11720 /* MOD_0FF0_PREFIX_3 */
11721 { "lddqu", { XM
, M
}, 0 },
11724 /* MOD_0F382A_PREFIX_2 */
11725 { "movntdqa", { XM
, Mx
}, 0 },
11728 /* MOD_0F38F5_PREFIX_2 */
11729 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
11732 /* MOD_0F38F6_PREFIX_0 */
11733 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
11737 { "bound{S|}", { Gv
, Ma
}, 0 },
11738 { EVEX_TABLE (EVEX_0F
) },
11742 { "lesS", { Gv
, Mp
}, 0 },
11743 { VEX_C4_TABLE (VEX_0F
) },
11747 { "ldsS", { Gv
, Mp
}, 0 },
11748 { VEX_C5_TABLE (VEX_0F
) },
11751 /* MOD_VEX_0F12_PREFIX_0 */
11752 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11753 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11757 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11760 /* MOD_VEX_0F16_PREFIX_0 */
11761 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11762 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11766 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11770 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11773 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11775 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
11778 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11780 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
11783 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11785 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
11788 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11790 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
11793 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11795 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
11798 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11800 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
11803 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11805 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
11808 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11810 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
11813 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11815 { "knotw", { MaskG
, MaskR
}, 0 },
11818 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11820 { "knotq", { MaskG
, MaskR
}, 0 },
11823 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11825 { "knotb", { MaskG
, MaskR
}, 0 },
11828 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11830 { "knotd", { MaskG
, MaskR
}, 0 },
11833 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11835 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
11838 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11840 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
11843 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11845 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
11848 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11850 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
11853 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11855 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
11858 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11860 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
11863 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11865 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
11868 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11870 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
11873 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11875 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
11878 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11880 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
11883 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11885 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
11888 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11890 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
11893 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11895 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
11898 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11900 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
11903 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11905 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
11908 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11910 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
11913 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11915 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
11918 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11920 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
11923 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11925 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
11930 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
11933 /* MOD_VEX_0F71_REG_2 */
11935 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
11938 /* MOD_VEX_0F71_REG_4 */
11940 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
11943 /* MOD_VEX_0F71_REG_6 */
11945 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
11948 /* MOD_VEX_0F72_REG_2 */
11950 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
11953 /* MOD_VEX_0F72_REG_4 */
11955 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
11958 /* MOD_VEX_0F72_REG_6 */
11960 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
11963 /* MOD_VEX_0F73_REG_2 */
11965 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
11968 /* MOD_VEX_0F73_REG_3 */
11970 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
11973 /* MOD_VEX_0F73_REG_6 */
11975 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
11978 /* MOD_VEX_0F73_REG_7 */
11980 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
11983 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11984 { "kmovw", { Ew
, MaskG
}, 0 },
11988 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11989 { "kmovq", { Eq
, MaskG
}, 0 },
11993 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11994 { "kmovb", { Eb
, MaskG
}, 0 },
11998 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11999 { "kmovd", { Ed
, MaskG
}, 0 },
12003 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12005 { "kmovw", { MaskG
, Rdq
}, 0 },
12008 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12010 { "kmovb", { MaskG
, Rdq
}, 0 },
12013 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12015 { "kmovd", { MaskG
, Rdq
}, 0 },
12018 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12020 { "kmovq", { MaskG
, Rdq
}, 0 },
12023 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12025 { "kmovw", { Gdq
, MaskR
}, 0 },
12028 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12030 { "kmovb", { Gdq
, MaskR
}, 0 },
12033 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12035 { "kmovd", { Gdq
, MaskR
}, 0 },
12038 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12040 { "kmovq", { Gdq
, MaskR
}, 0 },
12043 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12045 { "kortestw", { MaskG
, MaskR
}, 0 },
12048 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12050 { "kortestq", { MaskG
, MaskR
}, 0 },
12053 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12055 { "kortestb", { MaskG
, MaskR
}, 0 },
12058 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12060 { "kortestd", { MaskG
, MaskR
}, 0 },
12063 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12065 { "ktestw", { MaskG
, MaskR
}, 0 },
12068 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12070 { "ktestq", { MaskG
, MaskR
}, 0 },
12073 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12075 { "ktestb", { MaskG
, MaskR
}, 0 },
12078 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12080 { "ktestd", { MaskG
, MaskR
}, 0 },
12083 /* MOD_VEX_0FAE_REG_2 */
12084 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
12087 /* MOD_VEX_0FAE_REG_3 */
12088 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
12091 /* MOD_VEX_0FD7_PREFIX_2 */
12093 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
12096 /* MOD_VEX_0FE7_PREFIX_2 */
12097 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
12100 /* MOD_VEX_0FF0_PREFIX_3 */
12101 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
12104 /* MOD_VEX_0F381A_PREFIX_2 */
12105 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
12108 /* MOD_VEX_0F382A_PREFIX_2 */
12109 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
12112 /* MOD_VEX_0F382C_PREFIX_2 */
12113 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
12116 /* MOD_VEX_0F382D_PREFIX_2 */
12117 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
12120 /* MOD_VEX_0F382E_PREFIX_2 */
12121 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
12124 /* MOD_VEX_0F382F_PREFIX_2 */
12125 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
12128 /* MOD_VEX_0F385A_PREFIX_2 */
12129 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
12132 /* MOD_VEX_0F388C_PREFIX_2 */
12133 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
12136 /* MOD_VEX_0F388E_PREFIX_2 */
12137 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
12140 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12142 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
12145 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12147 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
12150 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12152 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
12155 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12157 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
12160 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12162 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
12165 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12167 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
12170 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12172 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
12175 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12177 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
12179 #define NEED_MOD_TABLE
12180 #include "i386-dis-evex.h"
12181 #undef NEED_MOD_TABLE
12184 static const struct dis386 rm_table
[][8] = {
12187 { "xabort", { Skip_MODRM
, Ib
}, 0 },
12191 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
12194 /* RM_0F01_REG_0 */
12196 { "vmcall", { Skip_MODRM
}, 0 },
12197 { "vmlaunch", { Skip_MODRM
}, 0 },
12198 { "vmresume", { Skip_MODRM
}, 0 },
12199 { "vmxoff", { Skip_MODRM
}, 0 },
12202 /* RM_0F01_REG_1 */
12203 { "monitor", { { OP_Monitor
, 0 } }, 0 },
12204 { "mwait", { { OP_Mwait
, 0 } }, 0 },
12205 { "clac", { Skip_MODRM
}, 0 },
12206 { "stac", { Skip_MODRM
}, 0 },
12210 { "encls", { Skip_MODRM
}, 0 },
12213 /* RM_0F01_REG_2 */
12214 { "xgetbv", { Skip_MODRM
}, 0 },
12215 { "xsetbv", { Skip_MODRM
}, 0 },
12218 { "vmfunc", { Skip_MODRM
}, 0 },
12219 { "xend", { Skip_MODRM
}, 0 },
12220 { "xtest", { Skip_MODRM
}, 0 },
12221 { "enclu", { Skip_MODRM
}, 0 },
12224 /* RM_0F01_REG_3 */
12225 { "vmrun", { Skip_MODRM
}, 0 },
12226 { "vmmcall", { Skip_MODRM
}, 0 },
12227 { "vmload", { Skip_MODRM
}, 0 },
12228 { "vmsave", { Skip_MODRM
}, 0 },
12229 { "stgi", { Skip_MODRM
}, 0 },
12230 { "clgi", { Skip_MODRM
}, 0 },
12231 { "skinit", { Skip_MODRM
}, 0 },
12232 { "invlpga", { Skip_MODRM
}, 0 },
12235 /* RM_0F01_REG_5 */
12237 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_1
) },
12238 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2
) },
12242 { "rdpkru", { Skip_MODRM
}, 0 },
12243 { "wrpkru", { Skip_MODRM
}, 0 },
12246 /* RM_0F01_REG_7 */
12247 { "swapgs", { Skip_MODRM
}, 0 },
12248 { "rdtscp", { Skip_MODRM
}, 0 },
12249 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
12250 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
12251 { "clzero", { Skip_MODRM
}, 0 },
12254 /* RM_0F1E_MOD_3_REG_7 */
12255 { "nopQ", { Ev
}, 0 },
12256 { "nopQ", { Ev
}, 0 },
12257 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
12258 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
12259 { "nopQ", { Ev
}, 0 },
12260 { "nopQ", { Ev
}, 0 },
12261 { "nopQ", { Ev
}, 0 },
12262 { "nopQ", { Ev
}, 0 },
12265 /* RM_0FAE_REG_5 */
12266 { "lfence", { Skip_MODRM
}, 0 },
12269 /* RM_0FAE_REG_6 */
12270 { "mfence", { Skip_MODRM
}, 0 },
12273 /* RM_0FAE_REG_7 */
12274 { "sfence", { Skip_MODRM
}, 0 },
12279 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12281 /* We use the high bit to indicate different name for the same
12283 #define REP_PREFIX (0xf3 | 0x100)
12284 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12285 #define XRELEASE_PREFIX (0xf3 | 0x400)
12286 #define BND_PREFIX (0xf2 | 0x400)
12287 #define NOTRACK_PREFIX (0x3e | 0x100)
12292 int newrex
, i
, length
;
12298 last_lock_prefix
= -1;
12299 last_repz_prefix
= -1;
12300 last_repnz_prefix
= -1;
12301 last_data_prefix
= -1;
12302 last_addr_prefix
= -1;
12303 last_rex_prefix
= -1;
12304 last_seg_prefix
= -1;
12305 last_active_prefix
= -1;
12307 active_seg_prefix
= 0;
12308 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12309 all_prefixes
[i
] = 0;
12312 /* The maximum instruction length is 15bytes. */
12313 while (length
< MAX_CODE_LENGTH
- 1)
12315 FETCH_DATA (the_info
, codep
+ 1);
12319 /* REX prefixes family. */
12336 if (address_mode
== mode_64bit
)
12340 last_rex_prefix
= i
;
12343 prefixes
|= PREFIX_REPZ
;
12344 last_repz_prefix
= i
;
12347 prefixes
|= PREFIX_REPNZ
;
12348 last_repnz_prefix
= i
;
12351 prefixes
|= PREFIX_LOCK
;
12352 last_lock_prefix
= i
;
12355 prefixes
|= PREFIX_CS
;
12356 last_seg_prefix
= i
;
12357 active_seg_prefix
= PREFIX_CS
;
12360 prefixes
|= PREFIX_SS
;
12361 last_seg_prefix
= i
;
12362 active_seg_prefix
= PREFIX_SS
;
12365 prefixes
|= PREFIX_DS
;
12366 last_seg_prefix
= i
;
12367 active_seg_prefix
= PREFIX_DS
;
12370 prefixes
|= PREFIX_ES
;
12371 last_seg_prefix
= i
;
12372 active_seg_prefix
= PREFIX_ES
;
12375 prefixes
|= PREFIX_FS
;
12376 last_seg_prefix
= i
;
12377 active_seg_prefix
= PREFIX_FS
;
12380 prefixes
|= PREFIX_GS
;
12381 last_seg_prefix
= i
;
12382 active_seg_prefix
= PREFIX_GS
;
12385 prefixes
|= PREFIX_DATA
;
12386 last_data_prefix
= i
;
12389 prefixes
|= PREFIX_ADDR
;
12390 last_addr_prefix
= i
;
12393 /* fwait is really an instruction. If there are prefixes
12394 before the fwait, they belong to the fwait, *not* to the
12395 following instruction. */
12397 if (prefixes
|| rex
)
12399 prefixes
|= PREFIX_FWAIT
;
12401 /* This ensures that the previous REX prefixes are noticed
12402 as unused prefixes, as in the return case below. */
12406 prefixes
= PREFIX_FWAIT
;
12411 /* Rex is ignored when followed by another prefix. */
12417 if (*codep
!= FWAIT_OPCODE
)
12419 last_active_prefix
= i
;
12420 all_prefixes
[i
++] = *codep
;
12429 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12432 static const char *
12433 prefix_name (int pref
, int sizeflag
)
12435 static const char *rexes
[16] =
12438 "rex.B", /* 0x41 */
12439 "rex.X", /* 0x42 */
12440 "rex.XB", /* 0x43 */
12441 "rex.R", /* 0x44 */
12442 "rex.RB", /* 0x45 */
12443 "rex.RX", /* 0x46 */
12444 "rex.RXB", /* 0x47 */
12445 "rex.W", /* 0x48 */
12446 "rex.WB", /* 0x49 */
12447 "rex.WX", /* 0x4a */
12448 "rex.WXB", /* 0x4b */
12449 "rex.WR", /* 0x4c */
12450 "rex.WRB", /* 0x4d */
12451 "rex.WRX", /* 0x4e */
12452 "rex.WRXB", /* 0x4f */
12457 /* REX prefixes family. */
12474 return rexes
[pref
- 0x40];
12494 return (sizeflag
& DFLAG
) ? "data16" : "data32";
12496 if (address_mode
== mode_64bit
)
12497 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
12499 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
12504 case XACQUIRE_PREFIX
:
12506 case XRELEASE_PREFIX
:
12510 case NOTRACK_PREFIX
:
12517 static char op_out
[MAX_OPERANDS
][100];
12518 static int op_ad
, op_index
[MAX_OPERANDS
];
12519 static int two_source_ops
;
12520 static bfd_vma op_address
[MAX_OPERANDS
];
12521 static bfd_vma op_riprel
[MAX_OPERANDS
];
12522 static bfd_vma start_pc
;
12525 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12526 * (see topic "Redundant prefixes" in the "Differences from 8086"
12527 * section of the "Virtual 8086 Mode" chapter.)
12528 * 'pc' should be the address of this instruction, it will
12529 * be used to print the target address if this is a relative jump or call
12530 * The function returns the length of this instruction in bytes.
12533 static char intel_syntax
;
12534 static char intel_mnemonic
= !SYSV386_COMPAT
;
12535 static char open_char
;
12536 static char close_char
;
12537 static char separator_char
;
12538 static char scale_char
;
12546 static enum x86_64_isa isa64
;
12548 /* Here for backwards compatibility. When gdb stops using
12549 print_insn_i386_att and print_insn_i386_intel these functions can
12550 disappear, and print_insn_i386 be merged into print_insn. */
12552 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
12556 return print_insn (pc
, info
);
12560 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
12564 return print_insn (pc
, info
);
12568 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
12572 return print_insn (pc
, info
);
12576 print_i386_disassembler_options (FILE *stream
)
12578 fprintf (stream
, _("\n\
12579 The following i386/x86-64 specific disassembler options are supported for use\n\
12580 with the -M switch (multiple options should be separated by commas):\n"));
12582 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
12583 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
12584 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
12585 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
12586 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
12587 fprintf (stream
, _(" att-mnemonic\n"
12588 " Display instruction in AT&T mnemonic\n"));
12589 fprintf (stream
, _(" intel-mnemonic\n"
12590 " Display instruction in Intel mnemonic\n"));
12591 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
12592 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
12593 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
12594 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
12595 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
12596 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12597 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
12598 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
12602 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
12604 /* Get a pointer to struct dis386 with a valid name. */
12606 static const struct dis386
*
12607 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
12609 int vindex
, vex_table_index
;
12611 if (dp
->name
!= NULL
)
12614 switch (dp
->op
[0].bytemode
)
12616 case USE_REG_TABLE
:
12617 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
12620 case USE_MOD_TABLE
:
12621 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
12622 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
12626 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
12629 case USE_PREFIX_TABLE
:
12632 /* The prefix in VEX is implicit. */
12633 switch (vex
.prefix
)
12638 case REPE_PREFIX_OPCODE
:
12641 case DATA_PREFIX_OPCODE
:
12644 case REPNE_PREFIX_OPCODE
:
12654 int last_prefix
= -1;
12657 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12658 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12660 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12662 if (last_repz_prefix
> last_repnz_prefix
)
12665 prefix
= PREFIX_REPZ
;
12666 last_prefix
= last_repz_prefix
;
12671 prefix
= PREFIX_REPNZ
;
12672 last_prefix
= last_repnz_prefix
;
12675 /* Check if prefix should be ignored. */
12676 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
12677 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
12682 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12685 prefix
= PREFIX_DATA
;
12686 last_prefix
= last_data_prefix
;
12691 used_prefixes
|= prefix
;
12692 all_prefixes
[last_prefix
] = 0;
12695 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12698 case USE_X86_64_TABLE
:
12699 vindex
= address_mode
== mode_64bit
? 1 : 0;
12700 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12703 case USE_3BYTE_TABLE
:
12704 FETCH_DATA (info
, codep
+ 2);
12706 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12708 modrm
.mod
= (*codep
>> 6) & 3;
12709 modrm
.reg
= (*codep
>> 3) & 7;
12710 modrm
.rm
= *codep
& 7;
12713 case USE_VEX_LEN_TABLE
:
12717 switch (vex
.length
)
12730 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12733 case USE_XOP_8F_TABLE
:
12734 FETCH_DATA (info
, codep
+ 3);
12735 /* All bits in the REX prefix are ignored. */
12737 rex
= ~(*codep
>> 5) & 0x7;
12739 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12740 switch ((*codep
& 0x1f))
12746 vex_table_index
= XOP_08
;
12749 vex_table_index
= XOP_09
;
12752 vex_table_index
= XOP_0A
;
12756 vex
.w
= *codep
& 0x80;
12757 if (vex
.w
&& address_mode
== mode_64bit
)
12760 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12761 if (address_mode
!= mode_64bit
)
12763 /* In 16/32-bit mode REX_B is silently ignored. */
12765 if (vex
.register_specifier
> 0x7)
12772 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12773 switch ((*codep
& 0x3))
12779 vex
.prefix
= DATA_PREFIX_OPCODE
;
12782 vex
.prefix
= REPE_PREFIX_OPCODE
;
12785 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12792 dp
= &xop_table
[vex_table_index
][vindex
];
12795 FETCH_DATA (info
, codep
+ 1);
12796 modrm
.mod
= (*codep
>> 6) & 3;
12797 modrm
.reg
= (*codep
>> 3) & 7;
12798 modrm
.rm
= *codep
& 7;
12801 case USE_VEX_C4_TABLE
:
12803 FETCH_DATA (info
, codep
+ 3);
12804 /* All bits in the REX prefix are ignored. */
12806 rex
= ~(*codep
>> 5) & 0x7;
12807 switch ((*codep
& 0x1f))
12813 vex_table_index
= VEX_0F
;
12816 vex_table_index
= VEX_0F38
;
12819 vex_table_index
= VEX_0F3A
;
12823 vex
.w
= *codep
& 0x80;
12824 if (address_mode
== mode_64bit
)
12828 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12832 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12833 is ignored, other REX bits are 0 and the highest bit in
12834 VEX.vvvv is also ignored. */
12836 vex
.register_specifier
= (~(*codep
>> 3)) & 0x7;
12838 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12839 switch ((*codep
& 0x3))
12845 vex
.prefix
= DATA_PREFIX_OPCODE
;
12848 vex
.prefix
= REPE_PREFIX_OPCODE
;
12851 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12858 dp
= &vex_table
[vex_table_index
][vindex
];
12860 /* There is no MODRM byte for VEX0F 77. */
12861 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
12863 FETCH_DATA (info
, codep
+ 1);
12864 modrm
.mod
= (*codep
>> 6) & 3;
12865 modrm
.reg
= (*codep
>> 3) & 7;
12866 modrm
.rm
= *codep
& 7;
12870 case USE_VEX_C5_TABLE
:
12872 FETCH_DATA (info
, codep
+ 2);
12873 /* All bits in the REX prefix are ignored. */
12875 rex
= (*codep
& 0x80) ? 0 : REX_R
;
12877 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12879 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12881 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12882 switch ((*codep
& 0x3))
12888 vex
.prefix
= DATA_PREFIX_OPCODE
;
12891 vex
.prefix
= REPE_PREFIX_OPCODE
;
12894 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12901 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
12903 /* There is no MODRM byte for VEX 77. */
12904 if (vindex
!= 0x77)
12906 FETCH_DATA (info
, codep
+ 1);
12907 modrm
.mod
= (*codep
>> 6) & 3;
12908 modrm
.reg
= (*codep
>> 3) & 7;
12909 modrm
.rm
= *codep
& 7;
12913 case USE_VEX_W_TABLE
:
12917 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
12920 case USE_EVEX_TABLE
:
12921 two_source_ops
= 0;
12924 FETCH_DATA (info
, codep
+ 4);
12925 /* All bits in the REX prefix are ignored. */
12927 /* The first byte after 0x62. */
12928 rex
= ~(*codep
>> 5) & 0x7;
12929 vex
.r
= *codep
& 0x10;
12930 switch ((*codep
& 0xf))
12933 return &bad_opcode
;
12935 vex_table_index
= EVEX_0F
;
12938 vex_table_index
= EVEX_0F38
;
12941 vex_table_index
= EVEX_0F3A
;
12945 /* The second byte after 0x62. */
12947 vex
.w
= *codep
& 0x80;
12948 if (vex
.w
&& address_mode
== mode_64bit
)
12951 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12952 if (address_mode
!= mode_64bit
)
12954 /* In 16/32-bit mode silently ignore following bits. */
12958 vex
.register_specifier
&= 0x7;
12962 if (!(*codep
& 0x4))
12963 return &bad_opcode
;
12965 switch ((*codep
& 0x3))
12971 vex
.prefix
= DATA_PREFIX_OPCODE
;
12974 vex
.prefix
= REPE_PREFIX_OPCODE
;
12977 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12981 /* The third byte after 0x62. */
12984 /* Remember the static rounding bits. */
12985 vex
.ll
= (*codep
>> 5) & 3;
12986 vex
.b
= (*codep
& 0x10) != 0;
12988 vex
.v
= *codep
& 0x8;
12989 vex
.mask_register_specifier
= *codep
& 0x7;
12990 vex
.zeroing
= *codep
& 0x80;
12996 dp
= &evex_table
[vex_table_index
][vindex
];
12998 FETCH_DATA (info
, codep
+ 1);
12999 modrm
.mod
= (*codep
>> 6) & 3;
13000 modrm
.reg
= (*codep
>> 3) & 7;
13001 modrm
.rm
= *codep
& 7;
13003 /* Set vector length. */
13004 if (modrm
.mod
== 3 && vex
.b
)
13020 return &bad_opcode
;
13033 if (dp
->name
!= NULL
)
13036 return get_valid_dis386 (dp
, info
);
13040 get_sib (disassemble_info
*info
, int sizeflag
)
13042 /* If modrm.mod == 3, operand must be register. */
13044 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13048 FETCH_DATA (info
, codep
+ 2);
13049 sib
.index
= (codep
[1] >> 3) & 7;
13050 sib
.scale
= (codep
[1] >> 6) & 3;
13051 sib
.base
= codep
[1] & 7;
13056 print_insn (bfd_vma pc
, disassemble_info
*info
)
13058 const struct dis386
*dp
;
13060 char *op_txt
[MAX_OPERANDS
];
13062 int sizeflag
, orig_sizeflag
;
13064 struct dis_private priv
;
13067 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13068 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
13069 address_mode
= mode_32bit
;
13070 else if (info
->mach
== bfd_mach_i386_i8086
)
13072 address_mode
= mode_16bit
;
13073 priv
.orig_sizeflag
= 0;
13076 address_mode
= mode_64bit
;
13078 if (intel_syntax
== (char) -1)
13079 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
13081 for (p
= info
->disassembler_options
; p
!= NULL
; )
13083 if (CONST_STRNEQ (p
, "amd64"))
13085 else if (CONST_STRNEQ (p
, "intel64"))
13087 else if (CONST_STRNEQ (p
, "x86-64"))
13089 address_mode
= mode_64bit
;
13090 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13092 else if (CONST_STRNEQ (p
, "i386"))
13094 address_mode
= mode_32bit
;
13095 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13097 else if (CONST_STRNEQ (p
, "i8086"))
13099 address_mode
= mode_16bit
;
13100 priv
.orig_sizeflag
= 0;
13102 else if (CONST_STRNEQ (p
, "intel"))
13105 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
13106 intel_mnemonic
= 1;
13108 else if (CONST_STRNEQ (p
, "att"))
13111 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
13112 intel_mnemonic
= 0;
13114 else if (CONST_STRNEQ (p
, "addr"))
13116 if (address_mode
== mode_64bit
)
13118 if (p
[4] == '3' && p
[5] == '2')
13119 priv
.orig_sizeflag
&= ~AFLAG
;
13120 else if (p
[4] == '6' && p
[5] == '4')
13121 priv
.orig_sizeflag
|= AFLAG
;
13125 if (p
[4] == '1' && p
[5] == '6')
13126 priv
.orig_sizeflag
&= ~AFLAG
;
13127 else if (p
[4] == '3' && p
[5] == '2')
13128 priv
.orig_sizeflag
|= AFLAG
;
13131 else if (CONST_STRNEQ (p
, "data"))
13133 if (p
[4] == '1' && p
[5] == '6')
13134 priv
.orig_sizeflag
&= ~DFLAG
;
13135 else if (p
[4] == '3' && p
[5] == '2')
13136 priv
.orig_sizeflag
|= DFLAG
;
13138 else if (CONST_STRNEQ (p
, "suffix"))
13139 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
13141 p
= strchr (p
, ',');
13146 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
13148 (*info
->fprintf_func
) (info
->stream
,
13149 _("64-bit address is disabled"));
13155 names64
= intel_names64
;
13156 names32
= intel_names32
;
13157 names16
= intel_names16
;
13158 names8
= intel_names8
;
13159 names8rex
= intel_names8rex
;
13160 names_seg
= intel_names_seg
;
13161 names_mm
= intel_names_mm
;
13162 names_bnd
= intel_names_bnd
;
13163 names_xmm
= intel_names_xmm
;
13164 names_ymm
= intel_names_ymm
;
13165 names_zmm
= intel_names_zmm
;
13166 index64
= intel_index64
;
13167 index32
= intel_index32
;
13168 names_mask
= intel_names_mask
;
13169 index16
= intel_index16
;
13172 separator_char
= '+';
13177 names64
= att_names64
;
13178 names32
= att_names32
;
13179 names16
= att_names16
;
13180 names8
= att_names8
;
13181 names8rex
= att_names8rex
;
13182 names_seg
= att_names_seg
;
13183 names_mm
= att_names_mm
;
13184 names_bnd
= att_names_bnd
;
13185 names_xmm
= att_names_xmm
;
13186 names_ymm
= att_names_ymm
;
13187 names_zmm
= att_names_zmm
;
13188 index64
= att_index64
;
13189 index32
= att_index32
;
13190 names_mask
= att_names_mask
;
13191 index16
= att_index16
;
13194 separator_char
= ',';
13198 /* The output looks better if we put 7 bytes on a line, since that
13199 puts most long word instructions on a single line. Use 8 bytes
13201 if ((info
->mach
& bfd_mach_l1om
) != 0)
13202 info
->bytes_per_line
= 8;
13204 info
->bytes_per_line
= 7;
13206 info
->private_data
= &priv
;
13207 priv
.max_fetched
= priv
.the_buffer
;
13208 priv
.insn_start
= pc
;
13211 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13219 start_codep
= priv
.the_buffer
;
13220 codep
= priv
.the_buffer
;
13222 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
13226 /* Getting here means we tried for data but didn't get it. That
13227 means we have an incomplete instruction of some sort. Just
13228 print the first byte as a prefix or a .byte pseudo-op. */
13229 if (codep
> priv
.the_buffer
)
13231 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
13233 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
13236 /* Just print the first byte as a .byte instruction. */
13237 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
13238 (unsigned int) priv
.the_buffer
[0]);
13248 sizeflag
= priv
.orig_sizeflag
;
13250 if (!ckprefix () || rex_used
)
13252 /* Too many prefixes or unused REX prefixes. */
13254 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
13256 (*info
->fprintf_func
) (info
->stream
, "%s%s",
13258 prefix_name (all_prefixes
[i
], sizeflag
));
13262 insn_codep
= codep
;
13264 FETCH_DATA (info
, codep
+ 1);
13265 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
13267 if (((prefixes
& PREFIX_FWAIT
)
13268 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
13270 /* Handle prefixes before fwait. */
13271 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
13273 (*info
->fprintf_func
) (info
->stream
, "%s ",
13274 prefix_name (all_prefixes
[i
], sizeflag
));
13275 (*info
->fprintf_func
) (info
->stream
, "fwait");
13279 if (*codep
== 0x0f)
13281 unsigned char threebyte
;
13284 FETCH_DATA (info
, codep
+ 1);
13285 threebyte
= *codep
;
13286 dp
= &dis386_twobyte
[threebyte
];
13287 need_modrm
= twobyte_has_modrm
[*codep
];
13292 dp
= &dis386
[*codep
];
13293 need_modrm
= onebyte_has_modrm
[*codep
];
13297 /* Save sizeflag for printing the extra prefixes later before updating
13298 it for mnemonic and operand processing. The prefix names depend
13299 only on the address mode. */
13300 orig_sizeflag
= sizeflag
;
13301 if (prefixes
& PREFIX_ADDR
)
13303 if ((prefixes
& PREFIX_DATA
))
13309 FETCH_DATA (info
, codep
+ 1);
13310 modrm
.mod
= (*codep
>> 6) & 3;
13311 modrm
.reg
= (*codep
>> 3) & 7;
13312 modrm
.rm
= *codep
& 7;
13320 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
13322 get_sib (info
, sizeflag
);
13323 dofloat (sizeflag
);
13327 dp
= get_valid_dis386 (dp
, info
);
13328 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
13330 get_sib (info
, sizeflag
);
13331 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13334 op_ad
= MAX_OPERANDS
- 1 - i
;
13336 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
13337 /* For EVEX instruction after the last operand masking
13338 should be printed. */
13339 if (i
== 0 && vex
.evex
)
13341 /* Don't print {%k0}. */
13342 if (vex
.mask_register_specifier
)
13345 oappend (names_mask
[vex
.mask_register_specifier
]);
13355 /* Check if the REX prefix is used. */
13356 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
13357 all_prefixes
[last_rex_prefix
] = 0;
13359 /* Check if the SEG prefix is used. */
13360 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
13361 | PREFIX_FS
| PREFIX_GS
)) != 0
13362 && (used_prefixes
& active_seg_prefix
) != 0)
13363 all_prefixes
[last_seg_prefix
] = 0;
13365 /* Check if the ADDR prefix is used. */
13366 if ((prefixes
& PREFIX_ADDR
) != 0
13367 && (used_prefixes
& PREFIX_ADDR
) != 0)
13368 all_prefixes
[last_addr_prefix
] = 0;
13370 /* Check if the DATA prefix is used. */
13371 if ((prefixes
& PREFIX_DATA
) != 0
13372 && (used_prefixes
& PREFIX_DATA
) != 0)
13373 all_prefixes
[last_data_prefix
] = 0;
13375 /* Print the extra prefixes. */
13377 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
13378 if (all_prefixes
[i
])
13381 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
13384 prefix_length
+= strlen (name
) + 1;
13385 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
13388 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13389 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13390 used by putop and MMX/SSE operand and may be overriden by the
13391 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13393 if (dp
->prefix_requirement
== PREFIX_OPCODE
13394 && dp
!= &bad_opcode
13396 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
13398 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
13400 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
13402 && (used_prefixes
& PREFIX_DATA
) == 0))))
13404 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13405 return end_codep
- priv
.the_buffer
;
13408 /* Check maximum code length. */
13409 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
13411 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13412 return MAX_CODE_LENGTH
;
13415 obufp
= mnemonicendp
;
13416 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
13419 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
13421 /* The enter and bound instructions are printed with operands in the same
13422 order as the intel book; everything else is printed in reverse order. */
13423 if (intel_syntax
|| two_source_ops
)
13427 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13428 op_txt
[i
] = op_out
[i
];
13430 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
13431 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
13433 op_txt
[2] = op_out
[3];
13434 op_txt
[3] = op_out
[2];
13437 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
13439 op_ad
= op_index
[i
];
13440 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
13441 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
13442 riprel
= op_riprel
[i
];
13443 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
13444 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
13449 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13450 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
13454 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13458 (*info
->fprintf_func
) (info
->stream
, ",");
13459 if (op_index
[i
] != -1 && !op_riprel
[i
])
13460 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
13462 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
13466 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13467 if (op_index
[i
] != -1 && op_riprel
[i
])
13469 (*info
->fprintf_func
) (info
->stream
, " # ");
13470 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
13471 + op_address
[op_index
[i
]]), info
);
13474 return codep
- priv
.the_buffer
;
13477 static const char *float_mem
[] = {
13552 static const unsigned char float_mem_mode
[] = {
13627 #define ST { OP_ST, 0 }
13628 #define STi { OP_STi, 0 }
13630 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13631 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13632 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13633 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13634 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13635 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13636 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13637 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13638 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13640 static const struct dis386 float_reg
[][8] = {
13643 { "fadd", { ST
, STi
}, 0 },
13644 { "fmul", { ST
, STi
}, 0 },
13645 { "fcom", { STi
}, 0 },
13646 { "fcomp", { STi
}, 0 },
13647 { "fsub", { ST
, STi
}, 0 },
13648 { "fsubr", { ST
, STi
}, 0 },
13649 { "fdiv", { ST
, STi
}, 0 },
13650 { "fdivr", { ST
, STi
}, 0 },
13654 { "fld", { STi
}, 0 },
13655 { "fxch", { STi
}, 0 },
13665 { "fcmovb", { ST
, STi
}, 0 },
13666 { "fcmove", { ST
, STi
}, 0 },
13667 { "fcmovbe",{ ST
, STi
}, 0 },
13668 { "fcmovu", { ST
, STi
}, 0 },
13676 { "fcmovnb",{ ST
, STi
}, 0 },
13677 { "fcmovne",{ ST
, STi
}, 0 },
13678 { "fcmovnbe",{ ST
, STi
}, 0 },
13679 { "fcmovnu",{ ST
, STi
}, 0 },
13681 { "fucomi", { ST
, STi
}, 0 },
13682 { "fcomi", { ST
, STi
}, 0 },
13687 { "fadd", { STi
, ST
}, 0 },
13688 { "fmul", { STi
, ST
}, 0 },
13691 { "fsub!M", { STi
, ST
}, 0 },
13692 { "fsubM", { STi
, ST
}, 0 },
13693 { "fdiv!M", { STi
, ST
}, 0 },
13694 { "fdivM", { STi
, ST
}, 0 },
13698 { "ffree", { STi
}, 0 },
13700 { "fst", { STi
}, 0 },
13701 { "fstp", { STi
}, 0 },
13702 { "fucom", { STi
}, 0 },
13703 { "fucomp", { STi
}, 0 },
13709 { "faddp", { STi
, ST
}, 0 },
13710 { "fmulp", { STi
, ST
}, 0 },
13713 { "fsub!Mp", { STi
, ST
}, 0 },
13714 { "fsubMp", { STi
, ST
}, 0 },
13715 { "fdiv!Mp", { STi
, ST
}, 0 },
13716 { "fdivMp", { STi
, ST
}, 0 },
13720 { "ffreep", { STi
}, 0 },
13725 { "fucomip", { ST
, STi
}, 0 },
13726 { "fcomip", { ST
, STi
}, 0 },
13731 static char *fgrps
[][8] = {
13734 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13739 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13744 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13749 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13754 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13759 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13764 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13769 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13770 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13775 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13780 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13785 swap_operand (void)
13787 mnemonicendp
[0] = '.';
13788 mnemonicendp
[1] = 's';
13793 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13794 int sizeflag ATTRIBUTE_UNUSED
)
13796 /* Skip mod/rm byte. */
13802 dofloat (int sizeflag
)
13804 const struct dis386
*dp
;
13805 unsigned char floatop
;
13807 floatop
= codep
[-1];
13809 if (modrm
.mod
!= 3)
13811 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13813 putop (float_mem
[fp_indx
], sizeflag
);
13816 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13819 /* Skip mod/rm byte. */
13823 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13824 if (dp
->name
== NULL
)
13826 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13828 /* Instruction fnstsw is only one with strange arg. */
13829 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13830 strcpy (op_out
[0], names16
[0]);
13834 putop (dp
->name
, sizeflag
);
13839 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13844 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
13848 /* Like oappend (below), but S is a string starting with '%'.
13849 In Intel syntax, the '%' is elided. */
13851 oappend_maybe_intel (const char *s
)
13853 oappend (s
+ intel_syntax
);
13857 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13859 oappend_maybe_intel ("%st");
13863 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13865 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
13866 oappend_maybe_intel (scratchbuf
);
13869 /* Capital letters in template are macros. */
13871 putop (const char *in_template
, int sizeflag
)
13876 unsigned int l
= 0, len
= 1;
13879 #define SAVE_LAST(c) \
13880 if (l < len && l < sizeof (last)) \
13885 for (p
= in_template
; *p
; p
++)
13901 while (*++p
!= '|')
13902 if (*p
== '}' || *p
== '\0')
13905 /* Fall through. */
13910 while (*++p
!= '}')
13921 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13925 if (l
== 0 && len
== 1)
13930 if (sizeflag
& SUFFIX_ALWAYS
)
13943 if (address_mode
== mode_64bit
13944 && !(prefixes
& PREFIX_ADDR
))
13955 if (intel_syntax
&& !alt
)
13957 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13959 if (sizeflag
& DFLAG
)
13960 *obufp
++ = intel_syntax
? 'd' : 'l';
13962 *obufp
++ = intel_syntax
? 'w' : 's';
13963 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13967 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
13970 if (modrm
.mod
== 3)
13976 if (sizeflag
& DFLAG
)
13977 *obufp
++ = intel_syntax
? 'd' : 'l';
13980 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13986 case 'E': /* For jcxz/jecxz */
13987 if (address_mode
== mode_64bit
)
13989 if (sizeflag
& AFLAG
)
13995 if (sizeflag
& AFLAG
)
13997 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14002 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
14004 if (sizeflag
& AFLAG
)
14005 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
14007 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
14008 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14012 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
14014 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14018 if (!(rex
& REX_W
))
14019 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14024 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
14025 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
14027 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
14030 if (prefixes
& PREFIX_DS
)
14049 if (l
!= 0 || len
!= 1)
14051 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14056 if (!need_vex
|| !vex
.evex
)
14059 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14061 switch (vex
.length
)
14079 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
14084 /* Fall through. */
14087 if (l
!= 0 || len
!= 1)
14095 if (sizeflag
& SUFFIX_ALWAYS
)
14099 if (intel_mnemonic
!= cond
)
14103 if ((prefixes
& PREFIX_FWAIT
) == 0)
14106 used_prefixes
|= PREFIX_FWAIT
;
14112 else if (intel_syntax
&& (sizeflag
& DFLAG
))
14116 if (!(rex
& REX_W
))
14117 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14121 && address_mode
== mode_64bit
14122 && isa64
== intel64
)
14127 /* Fall through. */
14130 && address_mode
== mode_64bit
14131 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14136 /* Fall through. */
14139 if (l
== 0 && len
== 1)
14144 if ((rex
& REX_W
) == 0
14145 && (prefixes
& PREFIX_DATA
))
14147 if ((sizeflag
& DFLAG
) == 0)
14149 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14153 if ((prefixes
& PREFIX_DATA
)
14155 || (sizeflag
& SUFFIX_ALWAYS
))
14162 if (sizeflag
& DFLAG
)
14166 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14172 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14178 if ((prefixes
& PREFIX_DATA
)
14180 || (sizeflag
& SUFFIX_ALWAYS
))
14187 if (sizeflag
& DFLAG
)
14188 *obufp
++ = intel_syntax
? 'd' : 'l';
14191 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14199 if (address_mode
== mode_64bit
14200 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14202 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14206 /* Fall through. */
14209 if (l
== 0 && len
== 1)
14212 if (intel_syntax
&& !alt
)
14215 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14221 if (sizeflag
& DFLAG
)
14222 *obufp
++ = intel_syntax
? 'd' : 'l';
14225 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14231 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14237 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
14252 else if (sizeflag
& DFLAG
)
14261 if (intel_syntax
&& !p
[1]
14262 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
14264 if (!(rex
& REX_W
))
14265 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14268 if (l
== 0 && len
== 1)
14272 if (address_mode
== mode_64bit
14273 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14275 if (sizeflag
& SUFFIX_ALWAYS
)
14297 /* Fall through. */
14300 if (l
== 0 && len
== 1)
14305 if (sizeflag
& SUFFIX_ALWAYS
)
14311 if (sizeflag
& DFLAG
)
14315 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14329 if (address_mode
== mode_64bit
14330 && !(prefixes
& PREFIX_ADDR
))
14341 if (l
!= 0 || len
!= 1)
14346 if (need_vex
&& vex
.prefix
)
14348 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
14355 if (prefixes
& PREFIX_DATA
)
14359 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14363 if (l
== 0 && len
== 1)
14365 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14376 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14384 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14386 switch (vex
.length
)
14402 if (l
== 0 && len
== 1)
14404 /* operand size flag for cwtl, cbtw */
14413 else if (sizeflag
& DFLAG
)
14417 if (!(rex
& REX_W
))
14418 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14425 && last
[0] != 'L'))
14432 if (last
[0] == 'X')
14433 *obufp
++ = vex
.w
? 'd': 's';
14435 *obufp
++ = vex
.w
? 'q': 'd';
14441 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14443 if (sizeflag
& DFLAG
)
14447 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14453 if (address_mode
== mode_64bit
14454 && (isa64
== intel64
14455 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
14457 else if ((prefixes
& PREFIX_DATA
))
14459 if (!(sizeflag
& DFLAG
))
14461 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14468 mnemonicendp
= obufp
;
14473 oappend (const char *s
)
14475 obufp
= stpcpy (obufp
, s
);
14481 /* Only print the active segment register. */
14482 if (!active_seg_prefix
)
14485 used_prefixes
|= active_seg_prefix
;
14486 switch (active_seg_prefix
)
14489 oappend_maybe_intel ("%cs:");
14492 oappend_maybe_intel ("%ds:");
14495 oappend_maybe_intel ("%ss:");
14498 oappend_maybe_intel ("%es:");
14501 oappend_maybe_intel ("%fs:");
14504 oappend_maybe_intel ("%gs:");
14512 OP_indirE (int bytemode
, int sizeflag
)
14516 OP_E (bytemode
, sizeflag
);
14520 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
14522 if (address_mode
== mode_64bit
)
14530 sprintf_vma (tmp
, disp
);
14531 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
14532 strcpy (buf
+ 2, tmp
+ i
);
14536 bfd_signed_vma v
= disp
;
14543 /* Check for possible overflow on 0x8000000000000000. */
14546 strcpy (buf
, "9223372036854775808");
14560 tmp
[28 - i
] = (v
% 10) + '0';
14564 strcpy (buf
, tmp
+ 29 - i
);
14570 sprintf (buf
, "0x%x", (unsigned int) disp
);
14572 sprintf (buf
, "%d", (int) disp
);
14576 /* Put DISP in BUF as signed hex number. */
14579 print_displacement (char *buf
, bfd_vma disp
)
14581 bfd_signed_vma val
= disp
;
14590 /* Check for possible overflow. */
14593 switch (address_mode
)
14596 strcpy (buf
+ j
, "0x8000000000000000");
14599 strcpy (buf
+ j
, "0x80000000");
14602 strcpy (buf
+ j
, "0x8000");
14612 sprintf_vma (tmp
, (bfd_vma
) val
);
14613 for (i
= 0; tmp
[i
] == '0'; i
++)
14615 if (tmp
[i
] == '\0')
14617 strcpy (buf
+ j
, tmp
+ i
);
14621 intel_operand_size (int bytemode
, int sizeflag
)
14625 && (bytemode
== x_mode
14626 || bytemode
== evex_half_bcst_xmmq_mode
))
14629 oappend ("QWORD PTR ");
14631 oappend ("DWORD PTR ");
14640 oappend ("BYTE PTR ");
14645 oappend ("WORD PTR ");
14648 if (address_mode
== mode_64bit
&& isa64
== intel64
)
14650 oappend ("QWORD PTR ");
14653 /* Fall through. */
14655 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14657 oappend ("QWORD PTR ");
14660 /* Fall through. */
14666 oappend ("QWORD PTR ");
14669 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14670 oappend ("DWORD PTR ");
14672 oappend ("WORD PTR ");
14673 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14677 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14679 oappend ("WORD PTR ");
14680 if (!(rex
& REX_W
))
14681 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14684 if (sizeflag
& DFLAG
)
14685 oappend ("QWORD PTR ");
14687 oappend ("DWORD PTR ");
14688 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14691 case d_scalar_mode
:
14692 case d_scalar_swap_mode
:
14695 oappend ("DWORD PTR ");
14698 case q_scalar_mode
:
14699 case q_scalar_swap_mode
:
14701 oappend ("QWORD PTR ");
14704 if (address_mode
== mode_64bit
)
14705 oappend ("QWORD PTR ");
14707 oappend ("DWORD PTR ");
14710 if (sizeflag
& DFLAG
)
14711 oappend ("FWORD PTR ");
14713 oappend ("DWORD PTR ");
14714 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14717 oappend ("TBYTE PTR ");
14721 case evex_x_gscat_mode
:
14722 case evex_x_nobcst_mode
:
14725 switch (vex
.length
)
14728 oappend ("XMMWORD PTR ");
14731 oappend ("YMMWORD PTR ");
14734 oappend ("ZMMWORD PTR ");
14741 oappend ("XMMWORD PTR ");
14744 oappend ("XMMWORD PTR ");
14747 oappend ("YMMWORD PTR ");
14750 case evex_half_bcst_xmmq_mode
:
14754 switch (vex
.length
)
14757 oappend ("QWORD PTR ");
14760 oappend ("XMMWORD PTR ");
14763 oappend ("YMMWORD PTR ");
14773 switch (vex
.length
)
14778 oappend ("BYTE PTR ");
14788 switch (vex
.length
)
14793 oappend ("WORD PTR ");
14803 switch (vex
.length
)
14808 oappend ("DWORD PTR ");
14818 switch (vex
.length
)
14823 oappend ("QWORD PTR ");
14833 switch (vex
.length
)
14836 oappend ("WORD PTR ");
14839 oappend ("DWORD PTR ");
14842 oappend ("QWORD PTR ");
14852 switch (vex
.length
)
14855 oappend ("DWORD PTR ");
14858 oappend ("QWORD PTR ");
14861 oappend ("XMMWORD PTR ");
14871 switch (vex
.length
)
14874 oappend ("QWORD PTR ");
14877 oappend ("YMMWORD PTR ");
14880 oappend ("ZMMWORD PTR ");
14890 switch (vex
.length
)
14894 oappend ("XMMWORD PTR ");
14901 oappend ("OWORD PTR ");
14904 case vex_w_dq_mode
:
14905 case vex_scalar_w_dq_mode
:
14910 oappend ("QWORD PTR ");
14912 oappend ("DWORD PTR ");
14914 case vex_vsib_d_w_dq_mode
:
14915 case vex_vsib_q_w_dq_mode
:
14922 oappend ("QWORD PTR ");
14924 oappend ("DWORD PTR ");
14928 switch (vex
.length
)
14931 oappend ("XMMWORD PTR ");
14934 oappend ("YMMWORD PTR ");
14937 oappend ("ZMMWORD PTR ");
14944 case vex_vsib_q_w_d_mode
:
14945 case vex_vsib_d_w_d_mode
:
14946 if (!need_vex
|| !vex
.evex
)
14949 switch (vex
.length
)
14952 oappend ("QWORD PTR ");
14955 oappend ("XMMWORD PTR ");
14958 oappend ("YMMWORD PTR ");
14966 if (!need_vex
|| vex
.length
!= 128)
14969 oappend ("DWORD PTR ");
14971 oappend ("BYTE PTR ");
14977 oappend ("QWORD PTR ");
14979 oappend ("WORD PTR ");
14988 OP_E_register (int bytemode
, int sizeflag
)
14990 int reg
= modrm
.rm
;
14991 const char **names
;
14997 if ((sizeflag
& SUFFIX_ALWAYS
)
14998 && (bytemode
== b_swap_mode
14999 || bytemode
== v_swap_mode
))
15025 names
= address_mode
== mode_64bit
? names64
: names32
;
15031 if (address_mode
== mode_64bit
&& isa64
== intel64
)
15036 /* Fall through. */
15038 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15044 /* Fall through. */
15056 if ((sizeflag
& DFLAG
)
15057 || (bytemode
!= v_mode
15058 && bytemode
!= v_swap_mode
))
15062 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15072 names
= names_mask
;
15077 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15080 oappend (names
[reg
]);
15084 OP_E_memory (int bytemode
, int sizeflag
)
15087 int add
= (rex
& REX_B
) ? 8 : 0;
15093 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15095 && bytemode
!= x_mode
15096 && bytemode
!= xmmq_mode
15097 && bytemode
!= evex_half_bcst_xmmq_mode
)
15112 case vex_vsib_d_w_dq_mode
:
15113 case vex_vsib_d_w_d_mode
:
15114 case vex_vsib_q_w_dq_mode
:
15115 case vex_vsib_q_w_d_mode
:
15116 case evex_x_gscat_mode
:
15118 shift
= vex
.w
? 3 : 2;
15121 case evex_half_bcst_xmmq_mode
:
15125 shift
= vex
.w
? 3 : 2;
15128 /* Fall through. */
15132 case evex_x_nobcst_mode
:
15134 switch (vex
.length
)
15157 case q_scalar_mode
:
15159 case q_scalar_swap_mode
:
15165 case d_scalar_mode
:
15167 case d_scalar_swap_mode
:
15179 /* Make necessary corrections to shift for modes that need it.
15180 For these modes we currently have shift 4, 5 or 6 depending on
15181 vex.length (it corresponds to xmmword, ymmword or zmmword
15182 operand). We might want to make it 3, 4 or 5 (e.g. for
15183 xmmq_mode). In case of broadcast enabled the corrections
15184 aren't needed, as element size is always 32 or 64 bits. */
15186 && (bytemode
== xmmq_mode
15187 || bytemode
== evex_half_bcst_xmmq_mode
))
15189 else if (bytemode
== xmmqd_mode
)
15191 else if (bytemode
== xmmdw_mode
)
15193 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
15201 intel_operand_size (bytemode
, sizeflag
);
15204 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15206 /* 32/64 bit address mode */
15215 int addr32flag
= !((sizeflag
& AFLAG
)
15216 || bytemode
== v_bnd_mode
15217 || bytemode
== bnd_mode
);
15218 const char **indexes64
= names64
;
15219 const char **indexes32
= names32
;
15229 vindex
= sib
.index
;
15235 case vex_vsib_d_w_dq_mode
:
15236 case vex_vsib_d_w_d_mode
:
15237 case vex_vsib_q_w_dq_mode
:
15238 case vex_vsib_q_w_d_mode
:
15248 switch (vex
.length
)
15251 indexes64
= indexes32
= names_xmm
;
15255 || bytemode
== vex_vsib_q_w_dq_mode
15256 || bytemode
== vex_vsib_q_w_d_mode
)
15257 indexes64
= indexes32
= names_ymm
;
15259 indexes64
= indexes32
= names_xmm
;
15263 || bytemode
== vex_vsib_q_w_dq_mode
15264 || bytemode
== vex_vsib_q_w_d_mode
)
15265 indexes64
= indexes32
= names_zmm
;
15267 indexes64
= indexes32
= names_ymm
;
15274 haveindex
= vindex
!= 4;
15281 rbase
= base
+ add
;
15289 if (address_mode
== mode_64bit
&& !havesib
)
15295 FETCH_DATA (the_info
, codep
+ 1);
15297 if ((disp
& 0x80) != 0)
15299 if (vex
.evex
&& shift
> 0)
15307 /* In 32bit mode, we need index register to tell [offset] from
15308 [eiz*1 + offset]. */
15309 needindex
= (havesib
15312 && address_mode
== mode_32bit
);
15313 havedisp
= (havebase
15315 || (havesib
&& (haveindex
|| scale
!= 0)));
15318 if (modrm
.mod
!= 0 || base
== 5)
15320 if (havedisp
|| riprel
)
15321 print_displacement (scratchbuf
, disp
);
15323 print_operand_value (scratchbuf
, 1, disp
);
15324 oappend (scratchbuf
);
15328 oappend (!addr32flag
? "(%rip)" : "(%eip)");
15332 if ((havebase
|| haveindex
|| riprel
)
15333 && (bytemode
!= v_bnd_mode
)
15334 && (bytemode
!= bnd_mode
))
15335 used_prefixes
|= PREFIX_ADDR
;
15337 if (havedisp
|| (intel_syntax
&& riprel
))
15339 *obufp
++ = open_char
;
15340 if (intel_syntax
&& riprel
)
15343 oappend (!addr32flag
? "rip" : "eip");
15347 oappend (address_mode
== mode_64bit
&& !addr32flag
15348 ? names64
[rbase
] : names32
[rbase
]);
15351 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15352 print index to tell base + index from base. */
15356 || (havebase
&& base
!= ESP_REG_NUM
))
15358 if (!intel_syntax
|| havebase
)
15360 *obufp
++ = separator_char
;
15364 oappend (address_mode
== mode_64bit
&& !addr32flag
15365 ? indexes64
[vindex
] : indexes32
[vindex
]);
15367 oappend (address_mode
== mode_64bit
&& !addr32flag
15368 ? index64
: index32
);
15370 *obufp
++ = scale_char
;
15372 sprintf (scratchbuf
, "%d", 1 << scale
);
15373 oappend (scratchbuf
);
15377 && (disp
|| modrm
.mod
!= 0 || base
== 5))
15379 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
15384 else if (modrm
.mod
!= 1 && disp
!= -disp
)
15388 disp
= - (bfd_signed_vma
) disp
;
15392 print_displacement (scratchbuf
, disp
);
15394 print_operand_value (scratchbuf
, 1, disp
);
15395 oappend (scratchbuf
);
15398 *obufp
++ = close_char
;
15401 else if (intel_syntax
)
15403 if (modrm
.mod
!= 0 || base
== 5)
15405 if (!active_seg_prefix
)
15407 oappend (names_seg
[ds_reg
- es_reg
]);
15410 print_operand_value (scratchbuf
, 1, disp
);
15411 oappend (scratchbuf
);
15417 /* 16 bit address mode */
15418 used_prefixes
|= prefixes
& PREFIX_ADDR
;
15425 if ((disp
& 0x8000) != 0)
15430 FETCH_DATA (the_info
, codep
+ 1);
15432 if ((disp
& 0x80) != 0)
15437 if ((disp
& 0x8000) != 0)
15443 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
15445 print_displacement (scratchbuf
, disp
);
15446 oappend (scratchbuf
);
15449 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
15451 *obufp
++ = open_char
;
15453 oappend (index16
[modrm
.rm
]);
15455 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
15457 if ((bfd_signed_vma
) disp
>= 0)
15462 else if (modrm
.mod
!= 1)
15466 disp
= - (bfd_signed_vma
) disp
;
15469 print_displacement (scratchbuf
, disp
);
15470 oappend (scratchbuf
);
15473 *obufp
++ = close_char
;
15476 else if (intel_syntax
)
15478 if (!active_seg_prefix
)
15480 oappend (names_seg
[ds_reg
- es_reg
]);
15483 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
15484 oappend (scratchbuf
);
15487 if (vex
.evex
&& vex
.b
15488 && (bytemode
== x_mode
15489 || bytemode
== xmmq_mode
15490 || bytemode
== evex_half_bcst_xmmq_mode
))
15493 || bytemode
== xmmq_mode
15494 || bytemode
== evex_half_bcst_xmmq_mode
)
15496 switch (vex
.length
)
15499 oappend ("{1to2}");
15502 oappend ("{1to4}");
15505 oappend ("{1to8}");
15513 switch (vex
.length
)
15516 oappend ("{1to4}");
15519 oappend ("{1to8}");
15522 oappend ("{1to16}");
15532 OP_E (int bytemode
, int sizeflag
)
15534 /* Skip mod/rm byte. */
15538 if (modrm
.mod
== 3)
15539 OP_E_register (bytemode
, sizeflag
);
15541 OP_E_memory (bytemode
, sizeflag
);
15545 OP_G (int bytemode
, int sizeflag
)
15556 oappend (names8rex
[modrm
.reg
+ add
]);
15558 oappend (names8
[modrm
.reg
+ add
]);
15561 oappend (names16
[modrm
.reg
+ add
]);
15566 oappend (names32
[modrm
.reg
+ add
]);
15569 oappend (names64
[modrm
.reg
+ add
]);
15572 oappend (names_bnd
[modrm
.reg
]);
15581 oappend (names64
[modrm
.reg
+ add
]);
15584 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
15585 oappend (names32
[modrm
.reg
+ add
]);
15587 oappend (names16
[modrm
.reg
+ add
]);
15588 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15592 if (address_mode
== mode_64bit
)
15593 oappend (names64
[modrm
.reg
+ add
]);
15595 oappend (names32
[modrm
.reg
+ add
]);
15599 if ((modrm
.reg
+ add
) > 0x7)
15604 oappend (names_mask
[modrm
.reg
+ add
]);
15607 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15620 FETCH_DATA (the_info
, codep
+ 8);
15621 a
= *codep
++ & 0xff;
15622 a
|= (*codep
++ & 0xff) << 8;
15623 a
|= (*codep
++ & 0xff) << 16;
15624 a
|= (*codep
++ & 0xffu
) << 24;
15625 b
= *codep
++ & 0xff;
15626 b
|= (*codep
++ & 0xff) << 8;
15627 b
|= (*codep
++ & 0xff) << 16;
15628 b
|= (*codep
++ & 0xffu
) << 24;
15629 x
= a
+ ((bfd_vma
) b
<< 32);
15637 static bfd_signed_vma
15640 bfd_signed_vma x
= 0;
15642 FETCH_DATA (the_info
, codep
+ 4);
15643 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15644 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15645 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15646 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15650 static bfd_signed_vma
15653 bfd_signed_vma x
= 0;
15655 FETCH_DATA (the_info
, codep
+ 4);
15656 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15657 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15658 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15659 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15661 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15671 FETCH_DATA (the_info
, codep
+ 2);
15672 x
= *codep
++ & 0xff;
15673 x
|= (*codep
++ & 0xff) << 8;
15678 set_op (bfd_vma op
, int riprel
)
15680 op_index
[op_ad
] = op_ad
;
15681 if (address_mode
== mode_64bit
)
15683 op_address
[op_ad
] = op
;
15684 op_riprel
[op_ad
] = riprel
;
15688 /* Mask to get a 32-bit address. */
15689 op_address
[op_ad
] = op
& 0xffffffff;
15690 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15695 OP_REG (int code
, int sizeflag
)
15702 case es_reg
: case ss_reg
: case cs_reg
:
15703 case ds_reg
: case fs_reg
: case gs_reg
:
15704 oappend (names_seg
[code
- es_reg
]);
15716 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15717 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15718 s
= names16
[code
- ax_reg
+ add
];
15720 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15721 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15724 s
= names8rex
[code
- al_reg
+ add
];
15726 s
= names8
[code
- al_reg
];
15728 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15729 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15730 if (address_mode
== mode_64bit
15731 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15733 s
= names64
[code
- rAX_reg
+ add
];
15736 code
+= eAX_reg
- rAX_reg
;
15737 /* Fall through. */
15738 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15739 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15742 s
= names64
[code
- eAX_reg
+ add
];
15745 if (sizeflag
& DFLAG
)
15746 s
= names32
[code
- eAX_reg
+ add
];
15748 s
= names16
[code
- eAX_reg
+ add
];
15749 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15753 s
= INTERNAL_DISASSEMBLER_ERROR
;
15760 OP_IMREG (int code
, int sizeflag
)
15772 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15773 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15774 s
= names16
[code
- ax_reg
];
15776 case es_reg
: case ss_reg
: case cs_reg
:
15777 case ds_reg
: case fs_reg
: case gs_reg
:
15778 s
= names_seg
[code
- es_reg
];
15780 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15781 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15784 s
= names8rex
[code
- al_reg
];
15786 s
= names8
[code
- al_reg
];
15788 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15789 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15792 s
= names64
[code
- eAX_reg
];
15795 if (sizeflag
& DFLAG
)
15796 s
= names32
[code
- eAX_reg
];
15798 s
= names16
[code
- eAX_reg
];
15799 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15802 case z_mode_ax_reg
:
15803 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
15807 if (!(rex
& REX_W
))
15808 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15811 s
= INTERNAL_DISASSEMBLER_ERROR
;
15818 OP_I (int bytemode
, int sizeflag
)
15821 bfd_signed_vma mask
= -1;
15826 FETCH_DATA (the_info
, codep
+ 1);
15831 if (address_mode
== mode_64bit
)
15836 /* Fall through. */
15843 if (sizeflag
& DFLAG
)
15853 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15865 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15870 scratchbuf
[0] = '$';
15871 print_operand_value (scratchbuf
+ 1, 1, op
);
15872 oappend_maybe_intel (scratchbuf
);
15873 scratchbuf
[0] = '\0';
15877 OP_I64 (int bytemode
, int sizeflag
)
15880 bfd_signed_vma mask
= -1;
15882 if (address_mode
!= mode_64bit
)
15884 OP_I (bytemode
, sizeflag
);
15891 FETCH_DATA (the_info
, codep
+ 1);
15901 if (sizeflag
& DFLAG
)
15911 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15919 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15924 scratchbuf
[0] = '$';
15925 print_operand_value (scratchbuf
+ 1, 1, op
);
15926 oappend_maybe_intel (scratchbuf
);
15927 scratchbuf
[0] = '\0';
15931 OP_sI (int bytemode
, int sizeflag
)
15939 FETCH_DATA (the_info
, codep
+ 1);
15941 if ((op
& 0x80) != 0)
15943 if (bytemode
== b_T_mode
)
15945 if (address_mode
!= mode_64bit
15946 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15948 /* The operand-size prefix is overridden by a REX prefix. */
15949 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15957 if (!(rex
& REX_W
))
15959 if (sizeflag
& DFLAG
)
15967 /* The operand-size prefix is overridden by a REX prefix. */
15968 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15974 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15978 scratchbuf
[0] = '$';
15979 print_operand_value (scratchbuf
+ 1, 1, op
);
15980 oappend_maybe_intel (scratchbuf
);
15984 OP_J (int bytemode
, int sizeflag
)
15988 bfd_vma segment
= 0;
15993 FETCH_DATA (the_info
, codep
+ 1);
15995 if ((disp
& 0x80) != 0)
15999 if (isa64
== amd64
)
16001 if ((sizeflag
& DFLAG
)
16002 || (address_mode
== mode_64bit
16003 && (isa64
!= amd64
|| (rex
& REX_W
))))
16008 if ((disp
& 0x8000) != 0)
16010 /* In 16bit mode, address is wrapped around at 64k within
16011 the same segment. Otherwise, a data16 prefix on a jump
16012 instruction means that the pc is masked to 16 bits after
16013 the displacement is added! */
16015 if ((prefixes
& PREFIX_DATA
) == 0)
16016 segment
= ((start_pc
+ (codep
- start_codep
))
16017 & ~((bfd_vma
) 0xffff));
16019 if (address_mode
!= mode_64bit
16020 || (isa64
== amd64
&& !(rex
& REX_W
)))
16021 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16024 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16027 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
16029 print_operand_value (scratchbuf
, 1, disp
);
16030 oappend (scratchbuf
);
16034 OP_SEG (int bytemode
, int sizeflag
)
16036 if (bytemode
== w_mode
)
16037 oappend (names_seg
[modrm
.reg
]);
16039 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
16043 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
16047 if (sizeflag
& DFLAG
)
16057 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16059 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
16061 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
16062 oappend (scratchbuf
);
16066 OP_OFF (int bytemode
, int sizeflag
)
16070 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16071 intel_operand_size (bytemode
, sizeflag
);
16074 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16081 if (!active_seg_prefix
)
16083 oappend (names_seg
[ds_reg
- es_reg
]);
16087 print_operand_value (scratchbuf
, 1, off
);
16088 oappend (scratchbuf
);
16092 OP_OFF64 (int bytemode
, int sizeflag
)
16096 if (address_mode
!= mode_64bit
16097 || (prefixes
& PREFIX_ADDR
))
16099 OP_OFF (bytemode
, sizeflag
);
16103 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16104 intel_operand_size (bytemode
, sizeflag
);
16111 if (!active_seg_prefix
)
16113 oappend (names_seg
[ds_reg
- es_reg
]);
16117 print_operand_value (scratchbuf
, 1, off
);
16118 oappend (scratchbuf
);
16122 ptr_reg (int code
, int sizeflag
)
16126 *obufp
++ = open_char
;
16127 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
16128 if (address_mode
== mode_64bit
)
16130 if (!(sizeflag
& AFLAG
))
16131 s
= names32
[code
- eAX_reg
];
16133 s
= names64
[code
- eAX_reg
];
16135 else if (sizeflag
& AFLAG
)
16136 s
= names32
[code
- eAX_reg
];
16138 s
= names16
[code
- eAX_reg
];
16140 *obufp
++ = close_char
;
16145 OP_ESreg (int code
, int sizeflag
)
16151 case 0x6d: /* insw/insl */
16152 intel_operand_size (z_mode
, sizeflag
);
16154 case 0xa5: /* movsw/movsl/movsq */
16155 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16156 case 0xab: /* stosw/stosl */
16157 case 0xaf: /* scasw/scasl */
16158 intel_operand_size (v_mode
, sizeflag
);
16161 intel_operand_size (b_mode
, sizeflag
);
16164 oappend_maybe_intel ("%es:");
16165 ptr_reg (code
, sizeflag
);
16169 OP_DSreg (int code
, int sizeflag
)
16175 case 0x6f: /* outsw/outsl */
16176 intel_operand_size (z_mode
, sizeflag
);
16178 case 0xa5: /* movsw/movsl/movsq */
16179 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16180 case 0xad: /* lodsw/lodsl/lodsq */
16181 intel_operand_size (v_mode
, sizeflag
);
16184 intel_operand_size (b_mode
, sizeflag
);
16187 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16188 default segment register DS is printed. */
16189 if (!active_seg_prefix
)
16190 active_seg_prefix
= PREFIX_DS
;
16192 ptr_reg (code
, sizeflag
);
16196 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16204 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
16206 all_prefixes
[last_lock_prefix
] = 0;
16207 used_prefixes
|= PREFIX_LOCK
;
16212 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
16213 oappend_maybe_intel (scratchbuf
);
16217 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16226 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
16228 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
16229 oappend (scratchbuf
);
16233 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16235 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
16236 oappend_maybe_intel (scratchbuf
);
16240 OP_R (int bytemode
, int sizeflag
)
16242 /* Skip mod/rm byte. */
16245 OP_E_register (bytemode
, sizeflag
);
16249 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16251 int reg
= modrm
.reg
;
16252 const char **names
;
16254 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16255 if (prefixes
& PREFIX_DATA
)
16264 oappend (names
[reg
]);
16268 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16270 int reg
= modrm
.reg
;
16271 const char **names
;
16283 && bytemode
!= xmm_mode
16284 && bytemode
!= xmmq_mode
16285 && bytemode
!= evex_half_bcst_xmmq_mode
16286 && bytemode
!= ymm_mode
16287 && bytemode
!= scalar_mode
)
16289 switch (vex
.length
)
16296 || (bytemode
!= vex_vsib_q_w_dq_mode
16297 && bytemode
!= vex_vsib_q_w_d_mode
))
16309 else if (bytemode
== xmmq_mode
16310 || bytemode
== evex_half_bcst_xmmq_mode
)
16312 switch (vex
.length
)
16325 else if (bytemode
== ymm_mode
)
16329 oappend (names
[reg
]);
16333 OP_EM (int bytemode
, int sizeflag
)
16336 const char **names
;
16338 if (modrm
.mod
!= 3)
16341 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16343 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16344 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16346 OP_E (bytemode
, sizeflag
);
16350 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
16353 /* Skip mod/rm byte. */
16356 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16358 if (prefixes
& PREFIX_DATA
)
16367 oappend (names
[reg
]);
16370 /* cvt* are the only instructions in sse2 which have
16371 both SSE and MMX operands and also have 0x66 prefix
16372 in their opcode. 0x66 was originally used to differentiate
16373 between SSE and MMX instruction(operands). So we have to handle the
16374 cvt* separately using OP_EMC and OP_MXC */
16376 OP_EMC (int bytemode
, int sizeflag
)
16378 if (modrm
.mod
!= 3)
16380 if (intel_syntax
&& bytemode
== v_mode
)
16382 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16383 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16385 OP_E (bytemode
, sizeflag
);
16389 /* Skip mod/rm byte. */
16392 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16393 oappend (names_mm
[modrm
.rm
]);
16397 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16399 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16400 oappend (names_mm
[modrm
.reg
]);
16404 OP_EX (int bytemode
, int sizeflag
)
16407 const char **names
;
16409 /* Skip mod/rm byte. */
16413 if (modrm
.mod
!= 3)
16415 OP_E_memory (bytemode
, sizeflag
);
16430 if ((sizeflag
& SUFFIX_ALWAYS
)
16431 && (bytemode
== x_swap_mode
16432 || bytemode
== d_swap_mode
16433 || bytemode
== d_scalar_swap_mode
16434 || bytemode
== q_swap_mode
16435 || bytemode
== q_scalar_swap_mode
))
16439 && bytemode
!= xmm_mode
16440 && bytemode
!= xmmdw_mode
16441 && bytemode
!= xmmqd_mode
16442 && bytemode
!= xmm_mb_mode
16443 && bytemode
!= xmm_mw_mode
16444 && bytemode
!= xmm_md_mode
16445 && bytemode
!= xmm_mq_mode
16446 && bytemode
!= xmm_mdq_mode
16447 && bytemode
!= xmmq_mode
16448 && bytemode
!= evex_half_bcst_xmmq_mode
16449 && bytemode
!= ymm_mode
16450 && bytemode
!= d_scalar_mode
16451 && bytemode
!= d_scalar_swap_mode
16452 && bytemode
!= q_scalar_mode
16453 && bytemode
!= q_scalar_swap_mode
16454 && bytemode
!= vex_scalar_w_dq_mode
)
16456 switch (vex
.length
)
16471 else if (bytemode
== xmmq_mode
16472 || bytemode
== evex_half_bcst_xmmq_mode
)
16474 switch (vex
.length
)
16487 else if (bytemode
== ymm_mode
)
16491 oappend (names
[reg
]);
16495 OP_MS (int bytemode
, int sizeflag
)
16497 if (modrm
.mod
== 3)
16498 OP_EM (bytemode
, sizeflag
);
16504 OP_XS (int bytemode
, int sizeflag
)
16506 if (modrm
.mod
== 3)
16507 OP_EX (bytemode
, sizeflag
);
16513 OP_M (int bytemode
, int sizeflag
)
16515 if (modrm
.mod
== 3)
16516 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16519 OP_E (bytemode
, sizeflag
);
16523 OP_0f07 (int bytemode
, int sizeflag
)
16525 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
16528 OP_E (bytemode
, sizeflag
);
16531 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16532 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16535 NOP_Fixup1 (int bytemode
, int sizeflag
)
16537 if ((prefixes
& PREFIX_DATA
) != 0
16540 && address_mode
== mode_64bit
))
16541 OP_REG (bytemode
, sizeflag
);
16543 strcpy (obuf
, "nop");
16547 NOP_Fixup2 (int bytemode
, int sizeflag
)
16549 if ((prefixes
& PREFIX_DATA
) != 0
16552 && address_mode
== mode_64bit
))
16553 OP_IMREG (bytemode
, sizeflag
);
16556 static const char *const Suffix3DNow
[] = {
16557 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16558 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16559 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16560 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16561 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16562 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16563 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16564 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16565 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16566 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16567 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16568 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16569 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16570 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16571 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16572 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16573 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16574 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16575 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16576 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16577 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16578 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16579 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16580 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16581 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16582 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16583 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16584 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16585 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16586 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16587 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16588 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16589 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16590 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16591 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16592 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16593 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16594 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16595 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16596 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16597 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16598 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16599 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16600 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16601 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16602 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16603 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16604 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16605 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16606 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16607 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16608 /* CC */ NULL
, NULL
, NULL
, NULL
,
16609 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16610 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16611 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16612 /* DC */ NULL
, NULL
, NULL
, NULL
,
16613 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16614 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16615 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16616 /* EC */ NULL
, NULL
, NULL
, NULL
,
16617 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16618 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16619 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16620 /* FC */ NULL
, NULL
, NULL
, NULL
,
16624 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16626 const char *mnemonic
;
16628 FETCH_DATA (the_info
, codep
+ 1);
16629 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16630 place where an 8-bit immediate would normally go. ie. the last
16631 byte of the instruction. */
16632 obufp
= mnemonicendp
;
16633 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16635 oappend (mnemonic
);
16638 /* Since a variable sized modrm/sib chunk is between the start
16639 of the opcode (0x0f0f) and the opcode suffix, we need to do
16640 all the modrm processing first, and don't know until now that
16641 we have a bad opcode. This necessitates some cleaning up. */
16642 op_out
[0][0] = '\0';
16643 op_out
[1][0] = '\0';
16646 mnemonicendp
= obufp
;
16649 static struct op simd_cmp_op
[] =
16651 { STRING_COMMA_LEN ("eq") },
16652 { STRING_COMMA_LEN ("lt") },
16653 { STRING_COMMA_LEN ("le") },
16654 { STRING_COMMA_LEN ("unord") },
16655 { STRING_COMMA_LEN ("neq") },
16656 { STRING_COMMA_LEN ("nlt") },
16657 { STRING_COMMA_LEN ("nle") },
16658 { STRING_COMMA_LEN ("ord") }
16662 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16664 unsigned int cmp_type
;
16666 FETCH_DATA (the_info
, codep
+ 1);
16667 cmp_type
= *codep
++ & 0xff;
16668 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16671 char *p
= mnemonicendp
- 2;
16675 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16676 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16680 /* We have a reserved extension byte. Output it directly. */
16681 scratchbuf
[0] = '$';
16682 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16683 oappend_maybe_intel (scratchbuf
);
16684 scratchbuf
[0] = '\0';
16689 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
16690 int sizeflag ATTRIBUTE_UNUSED
)
16692 /* mwaitx %eax,%ecx,%ebx */
16695 const char **names
= (address_mode
== mode_64bit
16696 ? names64
: names32
);
16697 strcpy (op_out
[0], names
[0]);
16698 strcpy (op_out
[1], names
[1]);
16699 strcpy (op_out
[2], names
[3]);
16700 two_source_ops
= 1;
16702 /* Skip mod/rm byte. */
16708 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
16709 int sizeflag ATTRIBUTE_UNUSED
)
16711 /* mwait %eax,%ecx */
16714 const char **names
= (address_mode
== mode_64bit
16715 ? names64
: names32
);
16716 strcpy (op_out
[0], names
[0]);
16717 strcpy (op_out
[1], names
[1]);
16718 two_source_ops
= 1;
16720 /* Skip mod/rm byte. */
16726 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16727 int sizeflag ATTRIBUTE_UNUSED
)
16729 /* monitor %eax,%ecx,%edx" */
16732 const char **op1_names
;
16733 const char **names
= (address_mode
== mode_64bit
16734 ? names64
: names32
);
16736 if (!(prefixes
& PREFIX_ADDR
))
16737 op1_names
= (address_mode
== mode_16bit
16738 ? names16
: names
);
16741 /* Remove "addr16/addr32". */
16742 all_prefixes
[last_addr_prefix
] = 0;
16743 op1_names
= (address_mode
!= mode_32bit
16744 ? names32
: names16
);
16745 used_prefixes
|= PREFIX_ADDR
;
16747 strcpy (op_out
[0], op1_names
[0]);
16748 strcpy (op_out
[1], names
[1]);
16749 strcpy (op_out
[2], names
[2]);
16750 two_source_ops
= 1;
16752 /* Skip mod/rm byte. */
16760 /* Throw away prefixes and 1st. opcode byte. */
16761 codep
= insn_codep
+ 1;
16766 REP_Fixup (int bytemode
, int sizeflag
)
16768 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16770 if (prefixes
& PREFIX_REPZ
)
16771 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16778 OP_IMREG (bytemode
, sizeflag
);
16781 OP_ESreg (bytemode
, sizeflag
);
16784 OP_DSreg (bytemode
, sizeflag
);
16792 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16796 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16798 if (prefixes
& PREFIX_REPNZ
)
16799 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16802 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16806 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16807 int sizeflag ATTRIBUTE_UNUSED
)
16810 && active_seg_prefix
== PREFIX_DS
16811 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
16813 /* NOTRACK prefix is only valid on register indirect branch
16814 instructions and it must be the last prefix before REX
16815 prefix and opcode. NB: DATA prefix is unsupported for
16817 if (last_active_prefix
>= 0)
16819 int notrack_prefix
= last_active_prefix
;
16820 if (last_rex_prefix
== last_active_prefix
)
16822 if (all_prefixes
[notrack_prefix
] != NOTRACK_PREFIX_OPCODE
)
16825 active_seg_prefix
= 0;
16826 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
16830 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16831 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16835 HLE_Fixup1 (int bytemode
, int sizeflag
)
16838 && (prefixes
& PREFIX_LOCK
) != 0)
16840 if (prefixes
& PREFIX_REPZ
)
16841 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16842 if (prefixes
& PREFIX_REPNZ
)
16843 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16846 OP_E (bytemode
, sizeflag
);
16849 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16850 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16854 HLE_Fixup2 (int bytemode
, int sizeflag
)
16856 if (modrm
.mod
!= 3)
16858 if (prefixes
& PREFIX_REPZ
)
16859 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16860 if (prefixes
& PREFIX_REPNZ
)
16861 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16864 OP_E (bytemode
, sizeflag
);
16867 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16868 "xrelease" for memory operand. No check for LOCK prefix. */
16871 HLE_Fixup3 (int bytemode
, int sizeflag
)
16874 && last_repz_prefix
> last_repnz_prefix
16875 && (prefixes
& PREFIX_REPZ
) != 0)
16876 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16878 OP_E (bytemode
, sizeflag
);
16882 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
16887 /* Change cmpxchg8b to cmpxchg16b. */
16888 char *p
= mnemonicendp
- 2;
16889 mnemonicendp
= stpcpy (p
, "16b");
16892 else if ((prefixes
& PREFIX_LOCK
) != 0)
16894 if (prefixes
& PREFIX_REPZ
)
16895 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16896 if (prefixes
& PREFIX_REPNZ
)
16897 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16900 OP_M (bytemode
, sizeflag
);
16904 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
16906 const char **names
;
16910 switch (vex
.length
)
16924 oappend (names
[reg
]);
16928 CRC32_Fixup (int bytemode
, int sizeflag
)
16930 /* Add proper suffix to "crc32". */
16931 char *p
= mnemonicendp
;
16950 if (sizeflag
& DFLAG
)
16954 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16958 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16965 if (modrm
.mod
== 3)
16969 /* Skip mod/rm byte. */
16974 add
= (rex
& REX_B
) ? 8 : 0;
16975 if (bytemode
== b_mode
)
16979 oappend (names8rex
[modrm
.rm
+ add
]);
16981 oappend (names8
[modrm
.rm
+ add
]);
16987 oappend (names64
[modrm
.rm
+ add
]);
16988 else if ((prefixes
& PREFIX_DATA
))
16989 oappend (names16
[modrm
.rm
+ add
]);
16991 oappend (names32
[modrm
.rm
+ add
]);
16995 OP_E (bytemode
, sizeflag
);
16999 FXSAVE_Fixup (int bytemode
, int sizeflag
)
17001 /* Add proper suffix to "fxsave" and "fxrstor". */
17005 char *p
= mnemonicendp
;
17011 OP_M (bytemode
, sizeflag
);
17015 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
17017 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
17020 char *p
= mnemonicendp
;
17025 else if (sizeflag
& SUFFIX_ALWAYS
)
17032 OP_EX (bytemode
, sizeflag
);
17035 /* Display the destination register operand for instructions with
17039 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17042 const char **names
;
17050 reg
= vex
.register_specifier
;
17057 if (bytemode
== vex_scalar_mode
)
17059 oappend (names_xmm
[reg
]);
17063 switch (vex
.length
)
17070 case vex_vsib_q_w_dq_mode
:
17071 case vex_vsib_q_w_d_mode
:
17087 names
= names_mask
;
17101 case vex_vsib_q_w_dq_mode
:
17102 case vex_vsib_q_w_d_mode
:
17103 names
= vex
.w
? names_ymm
: names_xmm
;
17112 names
= names_mask
;
17115 /* See PR binutils/20893 for a reproducer. */
17127 oappend (names
[reg
]);
17130 /* Get the VEX immediate byte without moving codep. */
17132 static unsigned char
17133 get_vex_imm8 (int sizeflag
, int opnum
)
17135 int bytes_before_imm
= 0;
17137 if (modrm
.mod
!= 3)
17139 /* There are SIB/displacement bytes. */
17140 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
17142 /* 32/64 bit address mode */
17143 int base
= modrm
.rm
;
17145 /* Check SIB byte. */
17148 FETCH_DATA (the_info
, codep
+ 1);
17150 /* When decoding the third source, don't increase
17151 bytes_before_imm as this has already been incremented
17152 by one in OP_E_memory while decoding the second
17155 bytes_before_imm
++;
17158 /* Don't increase bytes_before_imm when decoding the third source,
17159 it has already been incremented by OP_E_memory while decoding
17160 the second source operand. */
17166 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17167 SIB == 5, there is a 4 byte displacement. */
17169 /* No displacement. */
17171 /* Fall through. */
17173 /* 4 byte displacement. */
17174 bytes_before_imm
+= 4;
17177 /* 1 byte displacement. */
17178 bytes_before_imm
++;
17185 /* 16 bit address mode */
17186 /* Don't increase bytes_before_imm when decoding the third source,
17187 it has already been incremented by OP_E_memory while decoding
17188 the second source operand. */
17194 /* When modrm.rm == 6, there is a 2 byte displacement. */
17196 /* No displacement. */
17198 /* Fall through. */
17200 /* 2 byte displacement. */
17201 bytes_before_imm
+= 2;
17204 /* 1 byte displacement: when decoding the third source,
17205 don't increase bytes_before_imm as this has already
17206 been incremented by one in OP_E_memory while decoding
17207 the second source operand. */
17209 bytes_before_imm
++;
17217 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
17218 return codep
[bytes_before_imm
];
17222 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
17224 const char **names
;
17226 if (reg
== -1 && modrm
.mod
!= 3)
17228 OP_E_memory (bytemode
, sizeflag
);
17240 else if (reg
> 7 && address_mode
!= mode_64bit
)
17244 switch (vex
.length
)
17255 oappend (names
[reg
]);
17259 OP_EX_VexImmW (int bytemode
, int sizeflag
)
17262 static unsigned char vex_imm8
;
17264 if (vex_w_done
== 0)
17268 /* Skip mod/rm byte. */
17272 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
17275 reg
= vex_imm8
>> 4;
17277 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17279 else if (vex_w_done
== 1)
17284 reg
= vex_imm8
>> 4;
17286 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17290 /* Output the imm8 directly. */
17291 scratchbuf
[0] = '$';
17292 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
17293 oappend_maybe_intel (scratchbuf
);
17294 scratchbuf
[0] = '\0';
17300 OP_Vex_2src (int bytemode
, int sizeflag
)
17302 if (modrm
.mod
== 3)
17304 int reg
= modrm
.rm
;
17308 oappend (names_xmm
[reg
]);
17313 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
17315 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
17316 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17318 OP_E (bytemode
, sizeflag
);
17323 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
17325 if (modrm
.mod
== 3)
17327 /* Skip mod/rm byte. */
17333 oappend (names_xmm
[vex
.register_specifier
]);
17335 OP_Vex_2src (bytemode
, sizeflag
);
17339 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
17342 OP_Vex_2src (bytemode
, sizeflag
);
17344 oappend (names_xmm
[vex
.register_specifier
]);
17348 OP_EX_VexW (int bytemode
, int sizeflag
)
17356 /* Skip mod/rm byte. */
17361 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
17366 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
17369 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17373 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17374 int sizeflag ATTRIBUTE_UNUSED
)
17376 /* Skip the immediate byte and check for invalid bits. */
17377 FETCH_DATA (the_info
, codep
+ 1);
17378 if (*codep
++ & 0xf)
17383 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17386 const char **names
;
17388 FETCH_DATA (the_info
, codep
+ 1);
17391 if (bytemode
!= x_mode
)
17398 if (reg
> 7 && address_mode
!= mode_64bit
)
17401 switch (vex
.length
)
17412 oappend (names
[reg
]);
17416 OP_XMM_VexW (int bytemode
, int sizeflag
)
17418 /* Turn off the REX.W bit since it is used for swapping operands
17421 OP_XMM (bytemode
, sizeflag
);
17425 OP_EX_Vex (int bytemode
, int sizeflag
)
17427 if (modrm
.mod
!= 3)
17429 if (vex
.register_specifier
!= 0)
17433 OP_EX (bytemode
, sizeflag
);
17437 OP_XMM_Vex (int bytemode
, int sizeflag
)
17439 if (modrm
.mod
!= 3)
17441 if (vex
.register_specifier
!= 0)
17445 OP_XMM (bytemode
, sizeflag
);
17449 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17451 switch (vex
.length
)
17454 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
17457 mnemonicendp
= stpcpy (obuf
, "vzeroall");
17464 static struct op vex_cmp_op
[] =
17466 { STRING_COMMA_LEN ("eq") },
17467 { STRING_COMMA_LEN ("lt") },
17468 { STRING_COMMA_LEN ("le") },
17469 { STRING_COMMA_LEN ("unord") },
17470 { STRING_COMMA_LEN ("neq") },
17471 { STRING_COMMA_LEN ("nlt") },
17472 { STRING_COMMA_LEN ("nle") },
17473 { STRING_COMMA_LEN ("ord") },
17474 { STRING_COMMA_LEN ("eq_uq") },
17475 { STRING_COMMA_LEN ("nge") },
17476 { STRING_COMMA_LEN ("ngt") },
17477 { STRING_COMMA_LEN ("false") },
17478 { STRING_COMMA_LEN ("neq_oq") },
17479 { STRING_COMMA_LEN ("ge") },
17480 { STRING_COMMA_LEN ("gt") },
17481 { STRING_COMMA_LEN ("true") },
17482 { STRING_COMMA_LEN ("eq_os") },
17483 { STRING_COMMA_LEN ("lt_oq") },
17484 { STRING_COMMA_LEN ("le_oq") },
17485 { STRING_COMMA_LEN ("unord_s") },
17486 { STRING_COMMA_LEN ("neq_us") },
17487 { STRING_COMMA_LEN ("nlt_uq") },
17488 { STRING_COMMA_LEN ("nle_uq") },
17489 { STRING_COMMA_LEN ("ord_s") },
17490 { STRING_COMMA_LEN ("eq_us") },
17491 { STRING_COMMA_LEN ("nge_uq") },
17492 { STRING_COMMA_LEN ("ngt_uq") },
17493 { STRING_COMMA_LEN ("false_os") },
17494 { STRING_COMMA_LEN ("neq_os") },
17495 { STRING_COMMA_LEN ("ge_oq") },
17496 { STRING_COMMA_LEN ("gt_oq") },
17497 { STRING_COMMA_LEN ("true_us") },
17501 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17503 unsigned int cmp_type
;
17505 FETCH_DATA (the_info
, codep
+ 1);
17506 cmp_type
= *codep
++ & 0xff;
17507 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
17510 char *p
= mnemonicendp
- 2;
17514 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
17515 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
17519 /* We have a reserved extension byte. Output it directly. */
17520 scratchbuf
[0] = '$';
17521 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17522 oappend_maybe_intel (scratchbuf
);
17523 scratchbuf
[0] = '\0';
17528 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17529 int sizeflag ATTRIBUTE_UNUSED
)
17531 unsigned int cmp_type
;
17536 FETCH_DATA (the_info
, codep
+ 1);
17537 cmp_type
= *codep
++ & 0xff;
17538 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17539 If it's the case, print suffix, otherwise - print the immediate. */
17540 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
17545 char *p
= mnemonicendp
- 2;
17547 /* vpcmp* can have both one- and two-lettered suffix. */
17561 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
17562 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
17566 /* We have a reserved extension byte. Output it directly. */
17567 scratchbuf
[0] = '$';
17568 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17569 oappend_maybe_intel (scratchbuf
);
17570 scratchbuf
[0] = '\0';
17574 static const struct op pclmul_op
[] =
17576 { STRING_COMMA_LEN ("lql") },
17577 { STRING_COMMA_LEN ("hql") },
17578 { STRING_COMMA_LEN ("lqh") },
17579 { STRING_COMMA_LEN ("hqh") }
17583 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17584 int sizeflag ATTRIBUTE_UNUSED
)
17586 unsigned int pclmul_type
;
17588 FETCH_DATA (the_info
, codep
+ 1);
17589 pclmul_type
= *codep
++ & 0xff;
17590 switch (pclmul_type
)
17601 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
17604 char *p
= mnemonicendp
- 3;
17609 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
17610 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
17614 /* We have a reserved extension byte. Output it directly. */
17615 scratchbuf
[0] = '$';
17616 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
17617 oappend_maybe_intel (scratchbuf
);
17618 scratchbuf
[0] = '\0';
17623 MOVBE_Fixup (int bytemode
, int sizeflag
)
17625 /* Add proper suffix to "movbe". */
17626 char *p
= mnemonicendp
;
17635 if (sizeflag
& SUFFIX_ALWAYS
)
17641 if (sizeflag
& DFLAG
)
17645 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17650 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17657 OP_M (bytemode
, sizeflag
);
17661 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17664 const char **names
;
17666 /* Skip mod/rm byte. */
17680 oappend (names
[reg
]);
17684 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17686 const char **names
;
17693 oappend (names
[vex
.register_specifier
]);
17697 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17700 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
17704 if ((rex
& REX_R
) != 0 || !vex
.r
)
17710 oappend (names_mask
[modrm
.reg
]);
17714 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17717 || (bytemode
!= evex_rounding_mode
17718 && bytemode
!= evex_sae_mode
))
17720 if (modrm
.mod
== 3 && vex
.b
)
17723 case evex_rounding_mode
:
17724 oappend (names_rounding
[vex
.ll
]);
17726 case evex_sae_mode
: