opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2016 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void OP_LWPCB_E (int, int);
 121 static void OP_LWP_E (int, int);
 122 static void OP_Vex_2src_1 (int, int);
 123 static void OP_Vex_2src_2 (int, int);
 124
 125 static void MOVBE_Fixup (int, int);
 126
 127 static void OP_Mask (int, int);
 128
 129 struct dis_private {
 130   /* Points to first byte not fetched.  */
 131   bfd_byte *max_fetched;
 132   bfd_byte the_buffer[MAX_MNEM_SIZE];
 133   bfd_vma insn_start;
 134   int orig_sizeflag;
 135   OPCODES_SIGJMP_BUF bailout;
 136 };
 137
 138 enum address_mode
 139 {
 140   mode_16bit,
 141   mode_32bit,
 142   mode_64bit
 143 };
 144
 145 enum address_mode address_mode;
 146
 147 /* Flags for the prefixes for the current instruction.  See below.  */
 148 static int prefixes;
 149
 150 /* REX prefix the current instruction.  See below.  */
 151 static int rex;
 152 /* Bits of REX we've already used.  */
 153 static int rex_used;
 154 /* REX bits in original REX prefix ignored.  */
 155 static int rex_ignored;
 156 /* Mark parts used in the REX prefix.  When we are testing for
 157    empty prefix (for 8bit register REX extension), just mask it
 158    out.  Otherwise test for REX bit is excuse for existence of REX
 159    only in case value is nonzero.  */
 160 #define USED_REX(value)                                 \
 161   {                                                     \
 162     if (value)                                          \
 163       {                                                 \
 164         if ((rex & value))                              \
 165           rex_used |= (value) | REX_OPCODE;             \
 166       }                                                 \
 167     else                                                \
 168       rex_used |= REX_OPCODE;                           \
 169   }
 170
 171 /* Flags for prefixes which we somehow handled when printing the
 172    current instruction.  */
 173 static int used_prefixes;
 174
 175 /* Flags stored in PREFIXES.  */
 176 #define PREFIX_REPZ 1
 177 #define PREFIX_REPNZ 2
 178 #define PREFIX_LOCK 4
 179 #define PREFIX_CS 8
 180 #define PREFIX_SS 0x10
 181 #define PREFIX_DS 0x20
 182 #define PREFIX_ES 0x40
 183 #define PREFIX_FS 0x80
 184 #define PREFIX_GS 0x100
 185 #define PREFIX_DATA 0x200
 186 #define PREFIX_ADDR 0x400
 187 #define PREFIX_FWAIT 0x800
 188
 189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 190    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 191    on error.  */
 192 #define FETCH_DATA(info, addr) \
 193   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 194    ? 1 : fetch_data ((info), (addr)))
 195
 196 static int
 197 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 198 {
 199   int status;
 200   struct dis_private *priv = (struct dis_private *) info->private_data;
 201   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 202
 203   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 204     status = (*info->read_memory_func) (start,
 205                                         priv->max_fetched,
 206                                         addr - priv->max_fetched,
 207                                         info);
 208   else
 209     status = -1;
 210   if (status != 0)
 211     {
 212       /* If we did manage to read at least one byte, then
 213          print_insn_i386 will do something sensible.  Otherwise, print
 214          an error.  We do that here because this is where we know
 215          STATUS.  */
 216       if (priv->max_fetched == priv->the_buffer)
 217         (*info->memory_error_func) (status, start, info);
 218       OPCODES_SIGLONGJMP (priv->bailout, 1);
 219     }
 220   else
 221     priv->max_fetched = addr;
 222   return 1;
 223 }
 224
 225 /* Possible values for prefix requirement.  */
 226 #define PREFIX_IGNORED_SHIFT    16
 227 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 232
 233 /* Opcode prefixes.  */
 234 #define PREFIX_OPCODE           (PREFIX_REPZ \
 235                                  | PREFIX_REPNZ \
 236                                  | PREFIX_DATA)
 237
 238 /* Prefixes ignored.  */
 239 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 240                                  | PREFIX_IGNORED_REPNZ \
 241                                  | PREFIX_IGNORED_DATA)
 242
 243 #define XX { NULL, 0 }
 244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 245
 246 #define Eb { OP_E, b_mode }
 247 #define Ebnd { OP_E, bnd_mode }
 248 #define EbS { OP_E, b_swap_mode }
 249 #define Ev { OP_E, v_mode }
 250 #define Ev_bnd { OP_E, v_bnd_mode }
 251 #define EvS { OP_E, v_swap_mode }
 252 #define Ed { OP_E, d_mode }
 253 #define Edq { OP_E, dq_mode }
 254 #define Edqw { OP_E, dqw_mode }
 255 #define EdqwS { OP_E, dqw_swap_mode }
 256 #define Edqb { OP_E, dqb_mode }
 257 #define Edb { OP_E, db_mode }
 258 #define Edw { OP_E, dw_mode }
 259 #define Edqd { OP_E, dqd_mode }
 260 #define Eq { OP_E, q_mode }
 261 #define indirEv { OP_indirE, indir_v_mode }
 262 #define indirEp { OP_indirE, f_mode }
 263 #define stackEv { OP_E, stack_v_mode }
 264 #define Em { OP_E, m_mode }
 265 #define Ew { OP_E, w_mode }
 266 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 267 #define Ma { OP_M, a_mode }
 268 #define Mb { OP_M, b_mode }
 269 #define Md { OP_M, d_mode }
 270 #define Mo { OP_M, o_mode }
 271 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 272 #define Mq { OP_M, q_mode }
 273 #define Mx { OP_M, x_mode }
 274 #define Mxmm { OP_M, xmm_mode }
 275 #define Gb { OP_G, b_mode }
 276 #define Gbnd { OP_G, bnd_mode }
 277 #define Gv { OP_G, v_mode }
 278 #define Gd { OP_G, d_mode }
 279 #define Gdq { OP_G, dq_mode }
 280 #define Gm { OP_G, m_mode }
 281 #define Gw { OP_G, w_mode }
 282 #define Rd { OP_R, d_mode }
 283 #define Rdq { OP_R, dq_mode }
 284 #define Rm { OP_R, m_mode }
 285 #define Ib { OP_I, b_mode }
 286 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 288 #define Iv { OP_I, v_mode }
 289 #define sIv { OP_sI, v_mode }
 290 #define Iq { OP_I, q_mode }
 291 #define Iv64 { OP_I64, v_mode }
 292 #define Iw { OP_I, w_mode }
 293 #define I1 { OP_I, const_1_mode }
 294 #define Jb { OP_J, b_mode }
 295 #define Jv { OP_J, v_mode }
 296 #define Cm { OP_C, m_mode }
 297 #define Dm { OP_D, m_mode }
 298 #define Td { OP_T, d_mode }
 299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 300
 301 #define RMeAX { OP_REG, eAX_reg }
 302 #define RMeBX { OP_REG, eBX_reg }
 303 #define RMeCX { OP_REG, eCX_reg }
 304 #define RMeDX { OP_REG, eDX_reg }
 305 #define RMeSP { OP_REG, eSP_reg }
 306 #define RMeBP { OP_REG, eBP_reg }
 307 #define RMeSI { OP_REG, eSI_reg }
 308 #define RMeDI { OP_REG, eDI_reg }
 309 #define RMrAX { OP_REG, rAX_reg }
 310 #define RMrBX { OP_REG, rBX_reg }
 311 #define RMrCX { OP_REG, rCX_reg }
 312 #define RMrDX { OP_REG, rDX_reg }
 313 #define RMrSP { OP_REG, rSP_reg }
 314 #define RMrBP { OP_REG, rBP_reg }
 315 #define RMrSI { OP_REG, rSI_reg }
 316 #define RMrDI { OP_REG, rDI_reg }
 317 #define RMAL { OP_REG, al_reg }
 318 #define RMCL { OP_REG, cl_reg }
 319 #define RMDL { OP_REG, dl_reg }
 320 #define RMBL { OP_REG, bl_reg }
 321 #define RMAH { OP_REG, ah_reg }
 322 #define RMCH { OP_REG, ch_reg }
 323 #define RMDH { OP_REG, dh_reg }
 324 #define RMBH { OP_REG, bh_reg }
 325 #define RMAX { OP_REG, ax_reg }
 326 #define RMDX { OP_REG, dx_reg }
 327
 328 #define eAX { OP_IMREG, eAX_reg }
 329 #define eBX { OP_IMREG, eBX_reg }
 330 #define eCX { OP_IMREG, eCX_reg }
 331 #define eDX { OP_IMREG, eDX_reg }
 332 #define eSP { OP_IMREG, eSP_reg }
 333 #define eBP { OP_IMREG, eBP_reg }
 334 #define eSI { OP_IMREG, eSI_reg }
 335 #define eDI { OP_IMREG, eDI_reg }
 336 #define AL { OP_IMREG, al_reg }
 337 #define CL { OP_IMREG, cl_reg }
 338 #define DL { OP_IMREG, dl_reg }
 339 #define BL { OP_IMREG, bl_reg }
 340 #define AH { OP_IMREG, ah_reg }
 341 #define CH { OP_IMREG, ch_reg }
 342 #define DH { OP_IMREG, dh_reg }
 343 #define BH { OP_IMREG, bh_reg }
 344 #define AX { OP_IMREG, ax_reg }
 345 #define DX { OP_IMREG, dx_reg }
 346 #define zAX { OP_IMREG, z_mode_ax_reg }
 347 #define indirDX { OP_IMREG, indir_dx_reg }
 348
 349 #define Sw { OP_SEG, w_mode }
 350 #define Sv { OP_SEG, v_mode }
 351 #define Ap { OP_DIR, 0 }
 352 #define Ob { OP_OFF64, b_mode }
 353 #define Ov { OP_OFF64, v_mode }
 354 #define Xb { OP_DSreg, eSI_reg }
 355 #define Xv { OP_DSreg, eSI_reg }
 356 #define Xz { OP_DSreg, eSI_reg }
 357 #define Yb { OP_ESreg, eDI_reg }
 358 #define Yv { OP_ESreg, eDI_reg }
 359 #define DSBX { OP_DSreg, eBX_reg }
 360
 361 #define es { OP_REG, es_reg }
 362 #define ss { OP_REG, ss_reg }
 363 #define cs { OP_REG, cs_reg }
 364 #define ds { OP_REG, ds_reg }
 365 #define fs { OP_REG, fs_reg }
 366 #define gs { OP_REG, gs_reg }
 367
 368 #define MX { OP_MMX, 0 }
 369 #define XM { OP_XMM, 0 }
 370 #define XMScalar { OP_XMM, scalar_mode }
 371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 372 #define XMM { OP_XMM, xmm_mode }
 373 #define XMxmmq { OP_XMM, xmmq_mode }
 374 #define EM { OP_EM, v_mode }
 375 #define EMS { OP_EM, v_swap_mode }
 376 #define EMd { OP_EM, d_mode }
 377 #define EMx { OP_EM, x_mode }
 378 #define EXw { OP_EX, w_mode }
 379 #define EXd { OP_EX, d_mode }
 380 #define EXdScalar { OP_EX, d_scalar_mode }
 381 #define EXdS { OP_EX, d_swap_mode }
 382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 383 #define EXq { OP_EX, q_mode }
 384 #define EXqScalar { OP_EX, q_scalar_mode }
 385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 386 #define EXqS { OP_EX, q_swap_mode }
 387 #define EXx { OP_EX, x_mode }
 388 #define EXxS { OP_EX, x_swap_mode }
 389 #define EXxmm { OP_EX, xmm_mode }
 390 #define EXymm { OP_EX, ymm_mode }
 391 #define EXxmmq { OP_EX, xmmq_mode }
 392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 395 #define EXxmm_md { OP_EX, xmm_md_mode }
 396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 398 #define EXxmmdw { OP_EX, xmmdw_mode }
 399 #define EXxmmqd { OP_EX, xmmqd_mode }
 400 #define EXymmq { OP_EX, ymmq_mode }
 401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 405 #define MS { OP_MS, v_mode }
 406 #define XS { OP_XS, v_mode }
 407 #define EMCq { OP_EMC, q_mode }
 408 #define MXC { OP_MXC, 0 }
 409 #define OPSUF { OP_3DNowSuffix, 0 }
 410 #define CMP { CMP_Fixup, 0 }
 411 #define XMM0 { XMM_Fixup, 0 }
 412 #define FXSAVE { FXSAVE_Fixup, 0 }
 413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 415
 416 #define Vex { OP_VEX, vex_mode }
 417 #define VexScalar { OP_VEX, vex_scalar_mode }
 418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 419 #define Vex128 { OP_VEX, vex128_mode }
 420 #define Vex256 { OP_VEX, vex256_mode }
 421 #define VexGdq { OP_VEX, dq_mode }
 422 #define VexI4 { VEXI4_Fixup, 0}
 423 #define EXdVex { OP_EX_Vex, d_mode }
 424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 426 #define EXqVex { OP_EX_Vex, q_mode }
 427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 429 #define EXVexW { OP_EX_VexW, x_mode }
 430 #define EXdVexW { OP_EX_VexW, d_mode }
 431 #define EXqVexW { OP_EX_VexW, q_mode }
 432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 433 #define XMVex { OP_XMM_Vex, 0 }
 434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 435 #define XMVexW { OP_XMM_VexW, 0 }
 436 #define XMVexI4 { OP_REG_VexI4, x_mode }
 437 #define PCLMUL { PCLMUL_Fixup, 0 }
 438 #define VZERO { VZERO_Fixup, 0 }
 439 #define VCMP { VCMP_Fixup, 0 }
 440 #define VPCMP { VPCMP_Fixup, 0 }
 441
 442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 444
 445 #define XMask { OP_Mask, mask_mode }
 446 #define MaskG { OP_G, mask_mode }
 447 #define MaskE { OP_E, mask_mode }
 448 #define MaskBDE { OP_E, mask_bd_mode }
 449 #define MaskR { OP_R, mask_mode }
 450 #define MaskVex { OP_VEX, mask_mode }
 451
 452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 456
 457 /* Used handle "rep" prefix for string instructions.  */
 458 #define Xbr { REP_Fixup, eSI_reg }
 459 #define Xvr { REP_Fixup, eSI_reg }
 460 #define Ybr { REP_Fixup, eDI_reg }
 461 #define Yvr { REP_Fixup, eDI_reg }
 462 #define Yzr { REP_Fixup, eDI_reg }
 463 #define indirDXr { REP_Fixup, indir_dx_reg }
 464 #define ALr { REP_Fixup, al_reg }
 465 #define eAXr { REP_Fixup, eAX_reg }
 466
 467 /* Used handle HLE prefix for lockable instructions.  */
 468 #define Ebh1 { HLE_Fixup1, b_mode }
 469 #define Evh1 { HLE_Fixup1, v_mode }
 470 #define Ebh2 { HLE_Fixup2, b_mode }
 471 #define Evh2 { HLE_Fixup2, v_mode }
 472 #define Ebh3 { HLE_Fixup3, b_mode }
 473 #define Evh3 { HLE_Fixup3, v_mode }
 474
 475 #define BND { BND_Fixup, 0 }
 476
 477 #define cond_jump_flag { NULL, cond_jump_mode }
 478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 479
 480 /* bits in sizeflag */
 481 #define SUFFIX_ALWAYS 4
 482 #define AFLAG 2
 483 #define DFLAG 1
 484
 485 enum
 486 {
 487   /* byte operand */
 488   b_mode = 1,
 489   /* byte operand with operand swapped */
 490   b_swap_mode,
 491   /* byte operand, sign extend like 'T' suffix */
 492   b_T_mode,
 493   /* operand size depends on prefixes */
 494   v_mode,
 495   /* operand size depends on prefixes with operand swapped */
 496   v_swap_mode,
 497   /* word operand */
 498   w_mode,
 499   /* double word operand  */
 500   d_mode,
 501   /* double word operand with operand swapped */
 502   d_swap_mode,
 503   /* quad word operand */
 504   q_mode,
 505   /* quad word operand with operand swapped */
 506   q_swap_mode,
 507   /* ten-byte operand */
 508   t_mode,
 509   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 510      broadcast enabled.  */
 511   x_mode,
 512   /* Similar to x_mode, but with different EVEX mem shifts.  */
 513   evex_x_gscat_mode,
 514   /* Similar to x_mode, but with disabled broadcast.  */
 515   evex_x_nobcst_mode,
 516   /* Similar to x_mode, but with operands swapped and disabled broadcast
 517      in EVEX.  */
 518   x_swap_mode,
 519   /* 16-byte XMM operand */
 520   xmm_mode,
 521   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 522      memory operand (depending on vector length).  Broadcast isn't
 523      allowed.  */
 524   xmmq_mode,
 525   /* Same as xmmq_mode, but broadcast is allowed.  */
 526   evex_half_bcst_xmmq_mode,
 527   /* XMM register or byte memory operand */
 528   xmm_mb_mode,
 529   /* XMM register or word memory operand */
 530   xmm_mw_mode,
 531   /* XMM register or double word memory operand */
 532   xmm_md_mode,
 533   /* XMM register or quad word memory operand */
 534   xmm_mq_mode,
 535   /* XMM register or double/quad word memory operand, depending on
 536      VEX.W.  */
 537   xmm_mdq_mode,
 538   /* 16-byte XMM, word, double word or quad word operand.  */
 539   xmmdw_mode,
 540   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 541   xmmqd_mode,
 542   /* 32-byte YMM operand */
 543   ymm_mode,
 544   /* quad word, ymmword or zmmword memory operand.  */
 545   ymmq_mode,
 546   /* 32-byte YMM or 16-byte word operand */
 547   ymmxmm_mode,
 548   /* d_mode in 32bit, q_mode in 64bit mode.  */
 549   m_mode,
 550   /* pair of v_mode operands */
 551   a_mode,
 552   cond_jump_mode,
 553   loop_jcxz_mode,
 554   v_bnd_mode,
 555   /* operand size depends on REX prefixes.  */
 556   dq_mode,
 557   /* registers like dq_mode, memory like w_mode.  */
 558   dqw_mode,
 559   dqw_swap_mode,
 560   bnd_mode,
 561   /* 4- or 6-byte pointer operand */
 562   f_mode,
 563   const_1_mode,
 564   /* v_mode for indirect branch opcodes.  */
 565   indir_v_mode,
 566   /* v_mode for stack-related opcodes.  */
 567   stack_v_mode,
 568   /* non-quad operand size depends on prefixes */
 569   z_mode,
 570   /* 16-byte operand */
 571   o_mode,
 572   /* registers like dq_mode, memory like b_mode.  */
 573   dqb_mode,
 574   /* registers like d_mode, memory like b_mode.  */
 575   db_mode,
 576   /* registers like d_mode, memory like w_mode.  */
 577   dw_mode,
 578   /* registers like dq_mode, memory like d_mode.  */
 579   dqd_mode,
 580   /* normal vex mode */
 581   vex_mode,
 582   /* 128bit vex mode */
 583   vex128_mode,
 584   /* 256bit vex mode */
 585   vex256_mode,
 586   /* operand size depends on the VEX.W bit.  */
 587   vex_w_dq_mode,
 588
 589   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 590   vex_vsib_d_w_dq_mode,
 591   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 592   vex_vsib_d_w_d_mode,
 593   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 594   vex_vsib_q_w_dq_mode,
 595   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 596   vex_vsib_q_w_d_mode,
 597
 598   /* scalar, ignore vector length.  */
 599   scalar_mode,
 600   /* like d_mode, ignore vector length.  */
 601   d_scalar_mode,
 602   /* like d_swap_mode, ignore vector length.  */
 603   d_scalar_swap_mode,
 604   /* like q_mode, ignore vector length.  */
 605   q_scalar_mode,
 606   /* like q_swap_mode, ignore vector length.  */
 607   q_scalar_swap_mode,
 608   /* like vex_mode, ignore vector length.  */
 609   vex_scalar_mode,
 610   /* like vex_w_dq_mode, ignore vector length.  */
 611   vex_scalar_w_dq_mode,
 612
 613   /* Static rounding.  */
 614   evex_rounding_mode,
 615   /* Supress all exceptions.  */
 616   evex_sae_mode,
 617
 618   /* Mask register operand.  */
 619   mask_mode,
 620   /* Mask register operand.  */
 621   mask_bd_mode,
 622
 623   es_reg,
 624   cs_reg,
 625   ss_reg,
 626   ds_reg,
 627   fs_reg,
 628   gs_reg,
 629
 630   eAX_reg,
 631   eCX_reg,
 632   eDX_reg,
 633   eBX_reg,
 634   eSP_reg,
 635   eBP_reg,
 636   eSI_reg,
 637   eDI_reg,
 638
 639   al_reg,
 640   cl_reg,
 641   dl_reg,
 642   bl_reg,
 643   ah_reg,
 644   ch_reg,
 645   dh_reg,
 646   bh_reg,
 647
 648   ax_reg,
 649   cx_reg,
 650   dx_reg,
 651   bx_reg,
 652   sp_reg,
 653   bp_reg,
 654   si_reg,
 655   di_reg,
 656
 657   rAX_reg,
 658   rCX_reg,
 659   rDX_reg,
 660   rBX_reg,
 661   rSP_reg,
 662   rBP_reg,
 663   rSI_reg,
 664   rDI_reg,
 665
 666   z_mode_ax_reg,
 667   indir_dx_reg
 668 };
 669
 670 enum
 671 {
 672   FLOATCODE = 1,
 673   USE_REG_TABLE,
 674   USE_MOD_TABLE,
 675   USE_RM_TABLE,
 676   USE_PREFIX_TABLE,
 677   USE_X86_64_TABLE,
 678   USE_3BYTE_TABLE,
 679   USE_XOP_8F_TABLE,
 680   USE_VEX_C4_TABLE,
 681   USE_VEX_C5_TABLE,
 682   USE_VEX_LEN_TABLE,
 683   USE_VEX_W_TABLE,
 684   USE_EVEX_TABLE
 685 };
 686
 687 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 688
 689 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 690 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 691 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 692 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 693 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 694 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 695 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 696 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 697 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 698 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 699 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 700 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 701 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 702 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 703 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 704
 705 enum
 706 {
 707   REG_80 = 0,
 708   REG_81,
 709   REG_82,
 710   REG_8F,
 711   REG_C0,
 712   REG_C1,
 713   REG_C6,
 714   REG_C7,
 715   REG_D0,
 716   REG_D1,
 717   REG_D2,
 718   REG_D3,
 719   REG_F6,
 720   REG_F7,
 721   REG_FE,
 722   REG_FF,
 723   REG_0F00,
 724   REG_0F01,
 725   REG_0F0D,
 726   REG_0F18,
 727   REG_0F71,
 728   REG_0F72,
 729   REG_0F73,
 730   REG_0FA6,
 731   REG_0FA7,
 732   REG_0FAE,
 733   REG_0FBA,
 734   REG_0FC7,
 735   REG_VEX_0F71,
 736   REG_VEX_0F72,
 737   REG_VEX_0F73,
 738   REG_VEX_0FAE,
 739   REG_VEX_0F38F3,
 740   REG_XOP_LWPCB,
 741   REG_XOP_LWP,
 742   REG_XOP_TBM_01,
 743   REG_XOP_TBM_02,
 744
 745   REG_EVEX_0F71,
 746   REG_EVEX_0F72,
 747   REG_EVEX_0F73,
 748   REG_EVEX_0F38C6,
 749   REG_EVEX_0F38C7
 750 };
 751
 752 enum
 753 {
 754   MOD_8D = 0,
 755   MOD_C6_REG_7,
 756   MOD_C7_REG_7,
 757   MOD_FF_REG_3,
 758   MOD_FF_REG_5,
 759   MOD_0F01_REG_0,
 760   MOD_0F01_REG_1,
 761   MOD_0F01_REG_2,
 762   MOD_0F01_REG_3,
 763   MOD_0F01_REG_5,
 764   MOD_0F01_REG_7,
 765   MOD_0F12_PREFIX_0,
 766   MOD_0F13,
 767   MOD_0F16_PREFIX_0,
 768   MOD_0F17,
 769   MOD_0F18_REG_0,
 770   MOD_0F18_REG_1,
 771   MOD_0F18_REG_2,
 772   MOD_0F18_REG_3,
 773   MOD_0F18_REG_4,
 774   MOD_0F18_REG_5,
 775   MOD_0F18_REG_6,
 776   MOD_0F18_REG_7,
 777   MOD_0F1A_PREFIX_0,
 778   MOD_0F1B_PREFIX_0,
 779   MOD_0F1B_PREFIX_1,
 780   MOD_0F24,
 781   MOD_0F26,
 782   MOD_0F2B_PREFIX_0,
 783   MOD_0F2B_PREFIX_1,
 784   MOD_0F2B_PREFIX_2,
 785   MOD_0F2B_PREFIX_3,
 786   MOD_0F51,
 787   MOD_0F71_REG_2,
 788   MOD_0F71_REG_4,
 789   MOD_0F71_REG_6,
 790   MOD_0F72_REG_2,
 791   MOD_0F72_REG_4,
 792   MOD_0F72_REG_6,
 793   MOD_0F73_REG_2,
 794   MOD_0F73_REG_3,
 795   MOD_0F73_REG_6,
 796   MOD_0F73_REG_7,
 797   MOD_0FAE_REG_0,
 798   MOD_0FAE_REG_1,
 799   MOD_0FAE_REG_2,
 800   MOD_0FAE_REG_3,
 801   MOD_0FAE_REG_4,
 802   MOD_0FAE_REG_5,
 803   MOD_0FAE_REG_6,
 804   MOD_0FAE_REG_7,
 805   MOD_0FB2,
 806   MOD_0FB4,
 807   MOD_0FB5,
 808   MOD_0FC3,
 809   MOD_0FC7_REG_3,
 810   MOD_0FC7_REG_4,
 811   MOD_0FC7_REG_5,
 812   MOD_0FC7_REG_6,
 813   MOD_0FC7_REG_7,
 814   MOD_0FD7,
 815   MOD_0FE7_PREFIX_2,
 816   MOD_0FF0_PREFIX_3,
 817   MOD_0F382A_PREFIX_2,
 818   MOD_62_32BIT,
 819   MOD_C4_32BIT,
 820   MOD_C5_32BIT,
 821   MOD_VEX_0F12_PREFIX_0,
 822   MOD_VEX_0F13,
 823   MOD_VEX_0F16_PREFIX_0,
 824   MOD_VEX_0F17,
 825   MOD_VEX_0F2B,
 826   MOD_VEX_W_0_0F41_P_0_LEN_1,
 827   MOD_VEX_W_1_0F41_P_0_LEN_1,
 828   MOD_VEX_W_0_0F41_P_2_LEN_1,
 829   MOD_VEX_W_1_0F41_P_2_LEN_1,
 830   MOD_VEX_W_0_0F42_P_0_LEN_1,
 831   MOD_VEX_W_1_0F42_P_0_LEN_1,
 832   MOD_VEX_W_0_0F42_P_2_LEN_1,
 833   MOD_VEX_W_1_0F42_P_2_LEN_1,
 834   MOD_VEX_W_0_0F44_P_0_LEN_1,
 835   MOD_VEX_W_1_0F44_P_0_LEN_1,
 836   MOD_VEX_W_0_0F44_P_2_LEN_1,
 837   MOD_VEX_W_1_0F44_P_2_LEN_1,
 838   MOD_VEX_W_0_0F45_P_0_LEN_1,
 839   MOD_VEX_W_1_0F45_P_0_LEN_1,
 840   MOD_VEX_W_0_0F45_P_2_LEN_1,
 841   MOD_VEX_W_1_0F45_P_2_LEN_1,
 842   MOD_VEX_W_0_0F46_P_0_LEN_1,
 843   MOD_VEX_W_1_0F46_P_0_LEN_1,
 844   MOD_VEX_W_0_0F46_P_2_LEN_1,
 845   MOD_VEX_W_1_0F46_P_2_LEN_1,
 846   MOD_VEX_W_0_0F47_P_0_LEN_1,
 847   MOD_VEX_W_1_0F47_P_0_LEN_1,
 848   MOD_VEX_W_0_0F47_P_2_LEN_1,
 849   MOD_VEX_W_1_0F47_P_2_LEN_1,
 850   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 851   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 852   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 853   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 854   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 855   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 856   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 857   MOD_VEX_0F50,
 858   MOD_VEX_0F71_REG_2,
 859   MOD_VEX_0F71_REG_4,
 860   MOD_VEX_0F71_REG_6,
 861   MOD_VEX_0F72_REG_2,
 862   MOD_VEX_0F72_REG_4,
 863   MOD_VEX_0F72_REG_6,
 864   MOD_VEX_0F73_REG_2,
 865   MOD_VEX_0F73_REG_3,
 866   MOD_VEX_0F73_REG_6,
 867   MOD_VEX_0F73_REG_7,
 868   MOD_VEX_W_0_0F91_P_0_LEN_0,
 869   MOD_VEX_W_1_0F91_P_0_LEN_0,
 870   MOD_VEX_W_0_0F91_P_2_LEN_0,
 871   MOD_VEX_W_1_0F91_P_2_LEN_0,
 872   MOD_VEX_W_0_0F92_P_0_LEN_0,
 873   MOD_VEX_W_0_0F92_P_2_LEN_0,
 874   MOD_VEX_W_0_0F92_P_3_LEN_0,
 875   MOD_VEX_W_1_0F92_P_3_LEN_0,
 876   MOD_VEX_W_0_0F93_P_0_LEN_0,
 877   MOD_VEX_W_0_0F93_P_2_LEN_0,
 878   MOD_VEX_W_0_0F93_P_3_LEN_0,
 879   MOD_VEX_W_1_0F93_P_3_LEN_0,
 880   MOD_VEX_W_0_0F98_P_0_LEN_0,
 881   MOD_VEX_W_1_0F98_P_0_LEN_0,
 882   MOD_VEX_W_0_0F98_P_2_LEN_0,
 883   MOD_VEX_W_1_0F98_P_2_LEN_0,
 884   MOD_VEX_W_0_0F99_P_0_LEN_0,
 885   MOD_VEX_W_1_0F99_P_0_LEN_0,
 886   MOD_VEX_W_0_0F99_P_2_LEN_0,
 887   MOD_VEX_W_1_0F99_P_2_LEN_0,
 888   MOD_VEX_0FAE_REG_2,
 889   MOD_VEX_0FAE_REG_3,
 890   MOD_VEX_0FD7_PREFIX_2,
 891   MOD_VEX_0FE7_PREFIX_2,
 892   MOD_VEX_0FF0_PREFIX_3,
 893   MOD_VEX_0F381A_PREFIX_2,
 894   MOD_VEX_0F382A_PREFIX_2,
 895   MOD_VEX_0F382C_PREFIX_2,
 896   MOD_VEX_0F382D_PREFIX_2,
 897   MOD_VEX_0F382E_PREFIX_2,
 898   MOD_VEX_0F382F_PREFIX_2,
 899   MOD_VEX_0F385A_PREFIX_2,
 900   MOD_VEX_0F388C_PREFIX_2,
 901   MOD_VEX_0F388E_PREFIX_2,
 902   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 903   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 904   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 905   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 906   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 907   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 908   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 909   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 910
 911   MOD_EVEX_0F10_PREFIX_1,
 912   MOD_EVEX_0F10_PREFIX_3,
 913   MOD_EVEX_0F11_PREFIX_1,
 914   MOD_EVEX_0F11_PREFIX_3,
 915   MOD_EVEX_0F12_PREFIX_0,
 916   MOD_EVEX_0F16_PREFIX_0,
 917   MOD_EVEX_0F38C6_REG_1,
 918   MOD_EVEX_0F38C6_REG_2,
 919   MOD_EVEX_0F38C6_REG_5,
 920   MOD_EVEX_0F38C6_REG_6,
 921   MOD_EVEX_0F38C7_REG_1,
 922   MOD_EVEX_0F38C7_REG_2,
 923   MOD_EVEX_0F38C7_REG_5,
 924   MOD_EVEX_0F38C7_REG_6
 925 };
 926
 927 enum
 928 {
 929   RM_C6_REG_7 = 0,
 930   RM_C7_REG_7,
 931   RM_0F01_REG_0,
 932   RM_0F01_REG_1,
 933   RM_0F01_REG_2,
 934   RM_0F01_REG_3,
 935   RM_0F01_REG_5,
 936   RM_0F01_REG_7,
 937   RM_0FAE_REG_5,
 938   RM_0FAE_REG_6,
 939   RM_0FAE_REG_7
 940 };
 941
 942 enum
 943 {
 944   PREFIX_90 = 0,
 945   PREFIX_0F10,
 946   PREFIX_0F11,
 947   PREFIX_0F12,
 948   PREFIX_0F16,
 949   PREFIX_0F1A,
 950   PREFIX_0F1B,
 951   PREFIX_0F2A,
 952   PREFIX_0F2B,
 953   PREFIX_0F2C,
 954   PREFIX_0F2D,
 955   PREFIX_0F2E,
 956   PREFIX_0F2F,
 957   PREFIX_0F51,
 958   PREFIX_0F52,
 959   PREFIX_0F53,
 960   PREFIX_0F58,
 961   PREFIX_0F59,
 962   PREFIX_0F5A,
 963   PREFIX_0F5B,
 964   PREFIX_0F5C,
 965   PREFIX_0F5D,
 966   PREFIX_0F5E,
 967   PREFIX_0F5F,
 968   PREFIX_0F60,
 969   PREFIX_0F61,
 970   PREFIX_0F62,
 971   PREFIX_0F6C,
 972   PREFIX_0F6D,
 973   PREFIX_0F6F,
 974   PREFIX_0F70,
 975   PREFIX_0F73_REG_3,
 976   PREFIX_0F73_REG_7,
 977   PREFIX_0F78,
 978   PREFIX_0F79,
 979   PREFIX_0F7C,
 980   PREFIX_0F7D,
 981   PREFIX_0F7E,
 982   PREFIX_0F7F,
 983   PREFIX_0FAE_REG_0,
 984   PREFIX_0FAE_REG_1,
 985   PREFIX_0FAE_REG_2,
 986   PREFIX_0FAE_REG_3,
 987   PREFIX_MOD_0_0FAE_REG_4,
 988   PREFIX_MOD_3_0FAE_REG_4,
 989   PREFIX_0FAE_REG_6,
 990   PREFIX_0FAE_REG_7,
 991   PREFIX_0FB8,
 992   PREFIX_0FBC,
 993   PREFIX_0FBD,
 994   PREFIX_0FC2,
 995   PREFIX_MOD_0_0FC3,
 996   PREFIX_MOD_0_0FC7_REG_6,
 997   PREFIX_MOD_3_0FC7_REG_6,
 998   PREFIX_MOD_3_0FC7_REG_7,
 999   PREFIX_0FD0,
1000   PREFIX_0FD6,
1001   PREFIX_0FE6,
1002   PREFIX_0FE7,
1003   PREFIX_0FF0,
1004   PREFIX_0FF7,
1005   PREFIX_0F3810,
1006   PREFIX_0F3814,
1007   PREFIX_0F3815,
1008   PREFIX_0F3817,
1009   PREFIX_0F3820,
1010   PREFIX_0F3821,
1011   PREFIX_0F3822,
1012   PREFIX_0F3823,
1013   PREFIX_0F3824,
1014   PREFIX_0F3825,
1015   PREFIX_0F3828,
1016   PREFIX_0F3829,
1017   PREFIX_0F382A,
1018   PREFIX_0F382B,
1019   PREFIX_0F3830,
1020   PREFIX_0F3831,
1021   PREFIX_0F3832,
1022   PREFIX_0F3833,
1023   PREFIX_0F3834,
1024   PREFIX_0F3835,
1025   PREFIX_0F3837,
1026   PREFIX_0F3838,
1027   PREFIX_0F3839,
1028   PREFIX_0F383A,
1029   PREFIX_0F383B,
1030   PREFIX_0F383C,
1031   PREFIX_0F383D,
1032   PREFIX_0F383E,
1033   PREFIX_0F383F,
1034   PREFIX_0F3840,
1035   PREFIX_0F3841,
1036   PREFIX_0F3880,
1037   PREFIX_0F3881,
1038   PREFIX_0F3882,
1039   PREFIX_0F38C8,
1040   PREFIX_0F38C9,
1041   PREFIX_0F38CA,
1042   PREFIX_0F38CB,
1043   PREFIX_0F38CC,
1044   PREFIX_0F38CD,
1045   PREFIX_0F38DB,
1046   PREFIX_0F38DC,
1047   PREFIX_0F38DD,
1048   PREFIX_0F38DE,
1049   PREFIX_0F38DF,
1050   PREFIX_0F38F0,
1051   PREFIX_0F38F1,
1052   PREFIX_0F38F6,
1053   PREFIX_0F3A08,
1054   PREFIX_0F3A09,
1055   PREFIX_0F3A0A,
1056   PREFIX_0F3A0B,
1057   PREFIX_0F3A0C,
1058   PREFIX_0F3A0D,
1059   PREFIX_0F3A0E,
1060   PREFIX_0F3A14,
1061   PREFIX_0F3A15,
1062   PREFIX_0F3A16,
1063   PREFIX_0F3A17,
1064   PREFIX_0F3A20,
1065   PREFIX_0F3A21,
1066   PREFIX_0F3A22,
1067   PREFIX_0F3A40,
1068   PREFIX_0F3A41,
1069   PREFIX_0F3A42,
1070   PREFIX_0F3A44,
1071   PREFIX_0F3A60,
1072   PREFIX_0F3A61,
1073   PREFIX_0F3A62,
1074   PREFIX_0F3A63,
1075   PREFIX_0F3ACC,
1076   PREFIX_0F3ADF,
1077   PREFIX_VEX_0F10,
1078   PREFIX_VEX_0F11,
1079   PREFIX_VEX_0F12,
1080   PREFIX_VEX_0F16,
1081   PREFIX_VEX_0F2A,
1082   PREFIX_VEX_0F2C,
1083   PREFIX_VEX_0F2D,
1084   PREFIX_VEX_0F2E,
1085   PREFIX_VEX_0F2F,
1086   PREFIX_VEX_0F41,
1087   PREFIX_VEX_0F42,
1088   PREFIX_VEX_0F44,
1089   PREFIX_VEX_0F45,
1090   PREFIX_VEX_0F46,
1091   PREFIX_VEX_0F47,
1092   PREFIX_VEX_0F4A,
1093   PREFIX_VEX_0F4B,
1094   PREFIX_VEX_0F51,
1095   PREFIX_VEX_0F52,
1096   PREFIX_VEX_0F53,
1097   PREFIX_VEX_0F58,
1098   PREFIX_VEX_0F59,
1099   PREFIX_VEX_0F5A,
1100   PREFIX_VEX_0F5B,
1101   PREFIX_VEX_0F5C,
1102   PREFIX_VEX_0F5D,
1103   PREFIX_VEX_0F5E,
1104   PREFIX_VEX_0F5F,
1105   PREFIX_VEX_0F60,
1106   PREFIX_VEX_0F61,
1107   PREFIX_VEX_0F62,
1108   PREFIX_VEX_0F63,
1109   PREFIX_VEX_0F64,
1110   PREFIX_VEX_0F65,
1111   PREFIX_VEX_0F66,
1112   PREFIX_VEX_0F67,
1113   PREFIX_VEX_0F68,
1114   PREFIX_VEX_0F69,
1115   PREFIX_VEX_0F6A,
1116   PREFIX_VEX_0F6B,
1117   PREFIX_VEX_0F6C,
1118   PREFIX_VEX_0F6D,
1119   PREFIX_VEX_0F6E,
1120   PREFIX_VEX_0F6F,
1121   PREFIX_VEX_0F70,
1122   PREFIX_VEX_0F71_REG_2,
1123   PREFIX_VEX_0F71_REG_4,
1124   PREFIX_VEX_0F71_REG_6,
1125   PREFIX_VEX_0F72_REG_2,
1126   PREFIX_VEX_0F72_REG_4,
1127   PREFIX_VEX_0F72_REG_6,
1128   PREFIX_VEX_0F73_REG_2,
1129   PREFIX_VEX_0F73_REG_3,
1130   PREFIX_VEX_0F73_REG_6,
1131   PREFIX_VEX_0F73_REG_7,
1132   PREFIX_VEX_0F74,
1133   PREFIX_VEX_0F75,
1134   PREFIX_VEX_0F76,
1135   PREFIX_VEX_0F77,
1136   PREFIX_VEX_0F7C,
1137   PREFIX_VEX_0F7D,
1138   PREFIX_VEX_0F7E,
1139   PREFIX_VEX_0F7F,
1140   PREFIX_VEX_0F90,
1141   PREFIX_VEX_0F91,
1142   PREFIX_VEX_0F92,
1143   PREFIX_VEX_0F93,
1144   PREFIX_VEX_0F98,
1145   PREFIX_VEX_0F99,
1146   PREFIX_VEX_0FC2,
1147   PREFIX_VEX_0FC4,
1148   PREFIX_VEX_0FC5,
1149   PREFIX_VEX_0FD0,
1150   PREFIX_VEX_0FD1,
1151   PREFIX_VEX_0FD2,
1152   PREFIX_VEX_0FD3,
1153   PREFIX_VEX_0FD4,
1154   PREFIX_VEX_0FD5,
1155   PREFIX_VEX_0FD6,
1156   PREFIX_VEX_0FD7,
1157   PREFIX_VEX_0FD8,
1158   PREFIX_VEX_0FD9,
1159   PREFIX_VEX_0FDA,
1160   PREFIX_VEX_0FDB,
1161   PREFIX_VEX_0FDC,
1162   PREFIX_VEX_0FDD,
1163   PREFIX_VEX_0FDE,
1164   PREFIX_VEX_0FDF,
1165   PREFIX_VEX_0FE0,
1166   PREFIX_VEX_0FE1,
1167   PREFIX_VEX_0FE2,
1168   PREFIX_VEX_0FE3,
1169   PREFIX_VEX_0FE4,
1170   PREFIX_VEX_0FE5,
1171   PREFIX_VEX_0FE6,
1172   PREFIX_VEX_0FE7,
1173   PREFIX_VEX_0FE8,
1174   PREFIX_VEX_0FE9,
1175   PREFIX_VEX_0FEA,
1176   PREFIX_VEX_0FEB,
1177   PREFIX_VEX_0FEC,
1178   PREFIX_VEX_0FED,
1179   PREFIX_VEX_0FEE,
1180   PREFIX_VEX_0FEF,
1181   PREFIX_VEX_0FF0,
1182   PREFIX_VEX_0FF1,
1183   PREFIX_VEX_0FF2,
1184   PREFIX_VEX_0FF3,
1185   PREFIX_VEX_0FF4,
1186   PREFIX_VEX_0FF5,
1187   PREFIX_VEX_0FF6,
1188   PREFIX_VEX_0FF7,
1189   PREFIX_VEX_0FF8,
1190   PREFIX_VEX_0FF9,
1191   PREFIX_VEX_0FFA,
1192   PREFIX_VEX_0FFB,
1193   PREFIX_VEX_0FFC,
1194   PREFIX_VEX_0FFD,
1195   PREFIX_VEX_0FFE,
1196   PREFIX_VEX_0F3800,
1197   PREFIX_VEX_0F3801,
1198   PREFIX_VEX_0F3802,
1199   PREFIX_VEX_0F3803,
1200   PREFIX_VEX_0F3804,
1201   PREFIX_VEX_0F3805,
1202   PREFIX_VEX_0F3806,
1203   PREFIX_VEX_0F3807,
1204   PREFIX_VEX_0F3808,
1205   PREFIX_VEX_0F3809,
1206   PREFIX_VEX_0F380A,
1207   PREFIX_VEX_0F380B,
1208   PREFIX_VEX_0F380C,
1209   PREFIX_VEX_0F380D,
1210   PREFIX_VEX_0F380E,
1211   PREFIX_VEX_0F380F,
1212   PREFIX_VEX_0F3813,
1213   PREFIX_VEX_0F3816,
1214   PREFIX_VEX_0F3817,
1215   PREFIX_VEX_0F3818,
1216   PREFIX_VEX_0F3819,
1217   PREFIX_VEX_0F381A,
1218   PREFIX_VEX_0F381C,
1219   PREFIX_VEX_0F381D,
1220   PREFIX_VEX_0F381E,
1221   PREFIX_VEX_0F3820,
1222   PREFIX_VEX_0F3821,
1223   PREFIX_VEX_0F3822,
1224   PREFIX_VEX_0F3823,
1225   PREFIX_VEX_0F3824,
1226   PREFIX_VEX_0F3825,
1227   PREFIX_VEX_0F3828,
1228   PREFIX_VEX_0F3829,
1229   PREFIX_VEX_0F382A,
1230   PREFIX_VEX_0F382B,
1231   PREFIX_VEX_0F382C,
1232   PREFIX_VEX_0F382D,
1233   PREFIX_VEX_0F382E,
1234   PREFIX_VEX_0F382F,
1235   PREFIX_VEX_0F3830,
1236   PREFIX_VEX_0F3831,
1237   PREFIX_VEX_0F3832,
1238   PREFIX_VEX_0F3833,
1239   PREFIX_VEX_0F3834,
1240   PREFIX_VEX_0F3835,
1241   PREFIX_VEX_0F3836,
1242   PREFIX_VEX_0F3837,
1243   PREFIX_VEX_0F3838,
1244   PREFIX_VEX_0F3839,
1245   PREFIX_VEX_0F383A,
1246   PREFIX_VEX_0F383B,
1247   PREFIX_VEX_0F383C,
1248   PREFIX_VEX_0F383D,
1249   PREFIX_VEX_0F383E,
1250   PREFIX_VEX_0F383F,
1251   PREFIX_VEX_0F3840,
1252   PREFIX_VEX_0F3841,
1253   PREFIX_VEX_0F3845,
1254   PREFIX_VEX_0F3846,
1255   PREFIX_VEX_0F3847,
1256   PREFIX_VEX_0F3858,
1257   PREFIX_VEX_0F3859,
1258   PREFIX_VEX_0F385A,
1259   PREFIX_VEX_0F3878,
1260   PREFIX_VEX_0F3879,
1261   PREFIX_VEX_0F388C,
1262   PREFIX_VEX_0F388E,
1263   PREFIX_VEX_0F3890,
1264   PREFIX_VEX_0F3891,
1265   PREFIX_VEX_0F3892,
1266   PREFIX_VEX_0F3893,
1267   PREFIX_VEX_0F3896,
1268   PREFIX_VEX_0F3897,
1269   PREFIX_VEX_0F3898,
1270   PREFIX_VEX_0F3899,
1271   PREFIX_VEX_0F389A,
1272   PREFIX_VEX_0F389B,
1273   PREFIX_VEX_0F389C,
1274   PREFIX_VEX_0F389D,
1275   PREFIX_VEX_0F389E,
1276   PREFIX_VEX_0F389F,
1277   PREFIX_VEX_0F38A6,
1278   PREFIX_VEX_0F38A7,
1279   PREFIX_VEX_0F38A8,
1280   PREFIX_VEX_0F38A9,
1281   PREFIX_VEX_0F38AA,
1282   PREFIX_VEX_0F38AB,
1283   PREFIX_VEX_0F38AC,
1284   PREFIX_VEX_0F38AD,
1285   PREFIX_VEX_0F38AE,
1286   PREFIX_VEX_0F38AF,
1287   PREFIX_VEX_0F38B6,
1288   PREFIX_VEX_0F38B7,
1289   PREFIX_VEX_0F38B8,
1290   PREFIX_VEX_0F38B9,
1291   PREFIX_VEX_0F38BA,
1292   PREFIX_VEX_0F38BB,
1293   PREFIX_VEX_0F38BC,
1294   PREFIX_VEX_0F38BD,
1295   PREFIX_VEX_0F38BE,
1296   PREFIX_VEX_0F38BF,
1297   PREFIX_VEX_0F38DB,
1298   PREFIX_VEX_0F38DC,
1299   PREFIX_VEX_0F38DD,
1300   PREFIX_VEX_0F38DE,
1301   PREFIX_VEX_0F38DF,
1302   PREFIX_VEX_0F38F2,
1303   PREFIX_VEX_0F38F3_REG_1,
1304   PREFIX_VEX_0F38F3_REG_2,
1305   PREFIX_VEX_0F38F3_REG_3,
1306   PREFIX_VEX_0F38F5,
1307   PREFIX_VEX_0F38F6,
1308   PREFIX_VEX_0F38F7,
1309   PREFIX_VEX_0F3A00,
1310   PREFIX_VEX_0F3A01,
1311   PREFIX_VEX_0F3A02,
1312   PREFIX_VEX_0F3A04,
1313   PREFIX_VEX_0F3A05,
1314   PREFIX_VEX_0F3A06,
1315   PREFIX_VEX_0F3A08,
1316   PREFIX_VEX_0F3A09,
1317   PREFIX_VEX_0F3A0A,
1318   PREFIX_VEX_0F3A0B,
1319   PREFIX_VEX_0F3A0C,
1320   PREFIX_VEX_0F3A0D,
1321   PREFIX_VEX_0F3A0E,
1322   PREFIX_VEX_0F3A0F,
1323   PREFIX_VEX_0F3A14,
1324   PREFIX_VEX_0F3A15,
1325   PREFIX_VEX_0F3A16,
1326   PREFIX_VEX_0F3A17,
1327   PREFIX_VEX_0F3A18,
1328   PREFIX_VEX_0F3A19,
1329   PREFIX_VEX_0F3A1D,
1330   PREFIX_VEX_0F3A20,
1331   PREFIX_VEX_0F3A21,
1332   PREFIX_VEX_0F3A22,
1333   PREFIX_VEX_0F3A30,
1334   PREFIX_VEX_0F3A31,
1335   PREFIX_VEX_0F3A32,
1336   PREFIX_VEX_0F3A33,
1337   PREFIX_VEX_0F3A38,
1338   PREFIX_VEX_0F3A39,
1339   PREFIX_VEX_0F3A40,
1340   PREFIX_VEX_0F3A41,
1341   PREFIX_VEX_0F3A42,
1342   PREFIX_VEX_0F3A44,
1343   PREFIX_VEX_0F3A46,
1344   PREFIX_VEX_0F3A48,
1345   PREFIX_VEX_0F3A49,
1346   PREFIX_VEX_0F3A4A,
1347   PREFIX_VEX_0F3A4B,
1348   PREFIX_VEX_0F3A4C,
1349   PREFIX_VEX_0F3A5C,
1350   PREFIX_VEX_0F3A5D,
1351   PREFIX_VEX_0F3A5E,
1352   PREFIX_VEX_0F3A5F,
1353   PREFIX_VEX_0F3A60,
1354   PREFIX_VEX_0F3A61,
1355   PREFIX_VEX_0F3A62,
1356   PREFIX_VEX_0F3A63,
1357   PREFIX_VEX_0F3A68,
1358   PREFIX_VEX_0F3A69,
1359   PREFIX_VEX_0F3A6A,
1360   PREFIX_VEX_0F3A6B,
1361   PREFIX_VEX_0F3A6C,
1362   PREFIX_VEX_0F3A6D,
1363   PREFIX_VEX_0F3A6E,
1364   PREFIX_VEX_0F3A6F,
1365   PREFIX_VEX_0F3A78,
1366   PREFIX_VEX_0F3A79,
1367   PREFIX_VEX_0F3A7A,
1368   PREFIX_VEX_0F3A7B,
1369   PREFIX_VEX_0F3A7C,
1370   PREFIX_VEX_0F3A7D,
1371   PREFIX_VEX_0F3A7E,
1372   PREFIX_VEX_0F3A7F,
1373   PREFIX_VEX_0F3ADF,
1374   PREFIX_VEX_0F3AF0,
1375
1376   PREFIX_EVEX_0F10,
1377   PREFIX_EVEX_0F11,
1378   PREFIX_EVEX_0F12,
1379   PREFIX_EVEX_0F13,
1380   PREFIX_EVEX_0F14,
1381   PREFIX_EVEX_0F15,
1382   PREFIX_EVEX_0F16,
1383   PREFIX_EVEX_0F17,
1384   PREFIX_EVEX_0F28,
1385   PREFIX_EVEX_0F29,
1386   PREFIX_EVEX_0F2A,
1387   PREFIX_EVEX_0F2B,
1388   PREFIX_EVEX_0F2C,
1389   PREFIX_EVEX_0F2D,
1390   PREFIX_EVEX_0F2E,
1391   PREFIX_EVEX_0F2F,
1392   PREFIX_EVEX_0F51,
1393   PREFIX_EVEX_0F54,
1394   PREFIX_EVEX_0F55,
1395   PREFIX_EVEX_0F56,
1396   PREFIX_EVEX_0F57,
1397   PREFIX_EVEX_0F58,
1398   PREFIX_EVEX_0F59,
1399   PREFIX_EVEX_0F5A,
1400   PREFIX_EVEX_0F5B,
1401   PREFIX_EVEX_0F5C,
1402   PREFIX_EVEX_0F5D,
1403   PREFIX_EVEX_0F5E,
1404   PREFIX_EVEX_0F5F,
1405   PREFIX_EVEX_0F60,
1406   PREFIX_EVEX_0F61,
1407   PREFIX_EVEX_0F62,
1408   PREFIX_EVEX_0F63,
1409   PREFIX_EVEX_0F64,
1410   PREFIX_EVEX_0F65,
1411   PREFIX_EVEX_0F66,
1412   PREFIX_EVEX_0F67,
1413   PREFIX_EVEX_0F68,
1414   PREFIX_EVEX_0F69,
1415   PREFIX_EVEX_0F6A,
1416   PREFIX_EVEX_0F6B,
1417   PREFIX_EVEX_0F6C,
1418   PREFIX_EVEX_0F6D,
1419   PREFIX_EVEX_0F6E,
1420   PREFIX_EVEX_0F6F,
1421   PREFIX_EVEX_0F70,
1422   PREFIX_EVEX_0F71_REG_2,
1423   PREFIX_EVEX_0F71_REG_4,
1424   PREFIX_EVEX_0F71_REG_6,
1425   PREFIX_EVEX_0F72_REG_0,
1426   PREFIX_EVEX_0F72_REG_1,
1427   PREFIX_EVEX_0F72_REG_2,
1428   PREFIX_EVEX_0F72_REG_4,
1429   PREFIX_EVEX_0F72_REG_6,
1430   PREFIX_EVEX_0F73_REG_2,
1431   PREFIX_EVEX_0F73_REG_3,
1432   PREFIX_EVEX_0F73_REG_6,
1433   PREFIX_EVEX_0F73_REG_7,
1434   PREFIX_EVEX_0F74,
1435   PREFIX_EVEX_0F75,
1436   PREFIX_EVEX_0F76,
1437   PREFIX_EVEX_0F78,
1438   PREFIX_EVEX_0F79,
1439   PREFIX_EVEX_0F7A,
1440   PREFIX_EVEX_0F7B,
1441   PREFIX_EVEX_0F7E,
1442   PREFIX_EVEX_0F7F,
1443   PREFIX_EVEX_0FC2,
1444   PREFIX_EVEX_0FC4,
1445   PREFIX_EVEX_0FC5,
1446   PREFIX_EVEX_0FC6,
1447   PREFIX_EVEX_0FD1,
1448   PREFIX_EVEX_0FD2,
1449   PREFIX_EVEX_0FD3,
1450   PREFIX_EVEX_0FD4,
1451   PREFIX_EVEX_0FD5,
1452   PREFIX_EVEX_0FD6,
1453   PREFIX_EVEX_0FD8,
1454   PREFIX_EVEX_0FD9,
1455   PREFIX_EVEX_0FDA,
1456   PREFIX_EVEX_0FDB,
1457   PREFIX_EVEX_0FDC,
1458   PREFIX_EVEX_0FDD,
1459   PREFIX_EVEX_0FDE,
1460   PREFIX_EVEX_0FDF,
1461   PREFIX_EVEX_0FE0,
1462   PREFIX_EVEX_0FE1,
1463   PREFIX_EVEX_0FE2,
1464   PREFIX_EVEX_0FE3,
1465   PREFIX_EVEX_0FE4,
1466   PREFIX_EVEX_0FE5,
1467   PREFIX_EVEX_0FE6,
1468   PREFIX_EVEX_0FE7,
1469   PREFIX_EVEX_0FE8,
1470   PREFIX_EVEX_0FE9,
1471   PREFIX_EVEX_0FEA,
1472   PREFIX_EVEX_0FEB,
1473   PREFIX_EVEX_0FEC,
1474   PREFIX_EVEX_0FED,
1475   PREFIX_EVEX_0FEE,
1476   PREFIX_EVEX_0FEF,
1477   PREFIX_EVEX_0FF1,
1478   PREFIX_EVEX_0FF2,
1479   PREFIX_EVEX_0FF3,
1480   PREFIX_EVEX_0FF4,
1481   PREFIX_EVEX_0FF5,
1482   PREFIX_EVEX_0FF6,
1483   PREFIX_EVEX_0FF8,
1484   PREFIX_EVEX_0FF9,
1485   PREFIX_EVEX_0FFA,
1486   PREFIX_EVEX_0FFB,
1487   PREFIX_EVEX_0FFC,
1488   PREFIX_EVEX_0FFD,
1489   PREFIX_EVEX_0FFE,
1490   PREFIX_EVEX_0F3800,
1491   PREFIX_EVEX_0F3804,
1492   PREFIX_EVEX_0F380B,
1493   PREFIX_EVEX_0F380C,
1494   PREFIX_EVEX_0F380D,
1495   PREFIX_EVEX_0F3810,
1496   PREFIX_EVEX_0F3811,
1497   PREFIX_EVEX_0F3812,
1498   PREFIX_EVEX_0F3813,
1499   PREFIX_EVEX_0F3814,
1500   PREFIX_EVEX_0F3815,
1501   PREFIX_EVEX_0F3816,
1502   PREFIX_EVEX_0F3818,
1503   PREFIX_EVEX_0F3819,
1504   PREFIX_EVEX_0F381A,
1505   PREFIX_EVEX_0F381B,
1506   PREFIX_EVEX_0F381C,
1507   PREFIX_EVEX_0F381D,
1508   PREFIX_EVEX_0F381E,
1509   PREFIX_EVEX_0F381F,
1510   PREFIX_EVEX_0F3820,
1511   PREFIX_EVEX_0F3821,
1512   PREFIX_EVEX_0F3822,
1513   PREFIX_EVEX_0F3823,
1514   PREFIX_EVEX_0F3824,
1515   PREFIX_EVEX_0F3825,
1516   PREFIX_EVEX_0F3826,
1517   PREFIX_EVEX_0F3827,
1518   PREFIX_EVEX_0F3828,
1519   PREFIX_EVEX_0F3829,
1520   PREFIX_EVEX_0F382A,
1521   PREFIX_EVEX_0F382B,
1522   PREFIX_EVEX_0F382C,
1523   PREFIX_EVEX_0F382D,
1524   PREFIX_EVEX_0F3830,
1525   PREFIX_EVEX_0F3831,
1526   PREFIX_EVEX_0F3832,
1527   PREFIX_EVEX_0F3833,
1528   PREFIX_EVEX_0F3834,
1529   PREFIX_EVEX_0F3835,
1530   PREFIX_EVEX_0F3836,
1531   PREFIX_EVEX_0F3837,
1532   PREFIX_EVEX_0F3838,
1533   PREFIX_EVEX_0F3839,
1534   PREFIX_EVEX_0F383A,
1535   PREFIX_EVEX_0F383B,
1536   PREFIX_EVEX_0F383C,
1537   PREFIX_EVEX_0F383D,
1538   PREFIX_EVEX_0F383E,
1539   PREFIX_EVEX_0F383F,
1540   PREFIX_EVEX_0F3840,
1541   PREFIX_EVEX_0F3842,
1542   PREFIX_EVEX_0F3843,
1543   PREFIX_EVEX_0F3844,
1544   PREFIX_EVEX_0F3845,
1545   PREFIX_EVEX_0F3846,
1546   PREFIX_EVEX_0F3847,
1547   PREFIX_EVEX_0F384C,
1548   PREFIX_EVEX_0F384D,
1549   PREFIX_EVEX_0F384E,
1550   PREFIX_EVEX_0F384F,
1551   PREFIX_EVEX_0F3858,
1552   PREFIX_EVEX_0F3859,
1553   PREFIX_EVEX_0F385A,
1554   PREFIX_EVEX_0F385B,
1555   PREFIX_EVEX_0F3864,
1556   PREFIX_EVEX_0F3865,
1557   PREFIX_EVEX_0F3866,
1558   PREFIX_EVEX_0F3875,
1559   PREFIX_EVEX_0F3876,
1560   PREFIX_EVEX_0F3877,
1561   PREFIX_EVEX_0F3878,
1562   PREFIX_EVEX_0F3879,
1563   PREFIX_EVEX_0F387A,
1564   PREFIX_EVEX_0F387B,
1565   PREFIX_EVEX_0F387C,
1566   PREFIX_EVEX_0F387D,
1567   PREFIX_EVEX_0F387E,
1568   PREFIX_EVEX_0F387F,
1569   PREFIX_EVEX_0F3883,
1570   PREFIX_EVEX_0F3888,
1571   PREFIX_EVEX_0F3889,
1572   PREFIX_EVEX_0F388A,
1573   PREFIX_EVEX_0F388B,
1574   PREFIX_EVEX_0F388D,
1575   PREFIX_EVEX_0F3890,
1576   PREFIX_EVEX_0F3891,
1577   PREFIX_EVEX_0F3892,
1578   PREFIX_EVEX_0F3893,
1579   PREFIX_EVEX_0F3896,
1580   PREFIX_EVEX_0F3897,
1581   PREFIX_EVEX_0F3898,
1582   PREFIX_EVEX_0F3899,
1583   PREFIX_EVEX_0F389A,
1584   PREFIX_EVEX_0F389B,
1585   PREFIX_EVEX_0F389C,
1586   PREFIX_EVEX_0F389D,
1587   PREFIX_EVEX_0F389E,
1588   PREFIX_EVEX_0F389F,
1589   PREFIX_EVEX_0F38A0,
1590   PREFIX_EVEX_0F38A1,
1591   PREFIX_EVEX_0F38A2,
1592   PREFIX_EVEX_0F38A3,
1593   PREFIX_EVEX_0F38A6,
1594   PREFIX_EVEX_0F38A7,
1595   PREFIX_EVEX_0F38A8,
1596   PREFIX_EVEX_0F38A9,
1597   PREFIX_EVEX_0F38AA,
1598   PREFIX_EVEX_0F38AB,
1599   PREFIX_EVEX_0F38AC,
1600   PREFIX_EVEX_0F38AD,
1601   PREFIX_EVEX_0F38AE,
1602   PREFIX_EVEX_0F38AF,
1603   PREFIX_EVEX_0F38B4,
1604   PREFIX_EVEX_0F38B5,
1605   PREFIX_EVEX_0F38B6,
1606   PREFIX_EVEX_0F38B7,
1607   PREFIX_EVEX_0F38B8,
1608   PREFIX_EVEX_0F38B9,
1609   PREFIX_EVEX_0F38BA,
1610   PREFIX_EVEX_0F38BB,
1611   PREFIX_EVEX_0F38BC,
1612   PREFIX_EVEX_0F38BD,
1613   PREFIX_EVEX_0F38BE,
1614   PREFIX_EVEX_0F38BF,
1615   PREFIX_EVEX_0F38C4,
1616   PREFIX_EVEX_0F38C6_REG_1,
1617   PREFIX_EVEX_0F38C6_REG_2,
1618   PREFIX_EVEX_0F38C6_REG_5,
1619   PREFIX_EVEX_0F38C6_REG_6,
1620   PREFIX_EVEX_0F38C7_REG_1,
1621   PREFIX_EVEX_0F38C7_REG_2,
1622   PREFIX_EVEX_0F38C7_REG_5,
1623   PREFIX_EVEX_0F38C7_REG_6,
1624   PREFIX_EVEX_0F38C8,
1625   PREFIX_EVEX_0F38CA,
1626   PREFIX_EVEX_0F38CB,
1627   PREFIX_EVEX_0F38CC,
1628   PREFIX_EVEX_0F38CD,
1629
1630   PREFIX_EVEX_0F3A00,
1631   PREFIX_EVEX_0F3A01,
1632   PREFIX_EVEX_0F3A03,
1633   PREFIX_EVEX_0F3A04,
1634   PREFIX_EVEX_0F3A05,
1635   PREFIX_EVEX_0F3A08,
1636   PREFIX_EVEX_0F3A09,
1637   PREFIX_EVEX_0F3A0A,
1638   PREFIX_EVEX_0F3A0B,
1639   PREFIX_EVEX_0F3A0F,
1640   PREFIX_EVEX_0F3A14,
1641   PREFIX_EVEX_0F3A15,
1642   PREFIX_EVEX_0F3A16,
1643   PREFIX_EVEX_0F3A17,
1644   PREFIX_EVEX_0F3A18,
1645   PREFIX_EVEX_0F3A19,
1646   PREFIX_EVEX_0F3A1A,
1647   PREFIX_EVEX_0F3A1B,
1648   PREFIX_EVEX_0F3A1D,
1649   PREFIX_EVEX_0F3A1E,
1650   PREFIX_EVEX_0F3A1F,
1651   PREFIX_EVEX_0F3A20,
1652   PREFIX_EVEX_0F3A21,
1653   PREFIX_EVEX_0F3A22,
1654   PREFIX_EVEX_0F3A23,
1655   PREFIX_EVEX_0F3A25,
1656   PREFIX_EVEX_0F3A26,
1657   PREFIX_EVEX_0F3A27,
1658   PREFIX_EVEX_0F3A38,
1659   PREFIX_EVEX_0F3A39,
1660   PREFIX_EVEX_0F3A3A,
1661   PREFIX_EVEX_0F3A3B,
1662   PREFIX_EVEX_0F3A3E,
1663   PREFIX_EVEX_0F3A3F,
1664   PREFIX_EVEX_0F3A42,
1665   PREFIX_EVEX_0F3A43,
1666   PREFIX_EVEX_0F3A50,
1667   PREFIX_EVEX_0F3A51,
1668   PREFIX_EVEX_0F3A54,
1669   PREFIX_EVEX_0F3A55,
1670   PREFIX_EVEX_0F3A56,
1671   PREFIX_EVEX_0F3A57,
1672   PREFIX_EVEX_0F3A66,
1673   PREFIX_EVEX_0F3A67
1674 };
1675
1676 enum
1677 {
1678   X86_64_06 = 0,
1679   X86_64_07,
1680   X86_64_0D,
1681   X86_64_16,
1682   X86_64_17,
1683   X86_64_1E,
1684   X86_64_1F,
1685   X86_64_27,
1686   X86_64_2F,
1687   X86_64_37,
1688   X86_64_3F,
1689   X86_64_60,
1690   X86_64_61,
1691   X86_64_62,
1692   X86_64_63,
1693   X86_64_6D,
1694   X86_64_6F,
1695   X86_64_9A,
1696   X86_64_C4,
1697   X86_64_C5,
1698   X86_64_CE,
1699   X86_64_D4,
1700   X86_64_D5,
1701   X86_64_E8,
1702   X86_64_E9,
1703   X86_64_EA,
1704   X86_64_0F01_REG_0,
1705   X86_64_0F01_REG_1,
1706   X86_64_0F01_REG_2,
1707   X86_64_0F01_REG_3
1708 };
1709
1710 enum
1711 {
1712   THREE_BYTE_0F38 = 0,
1713   THREE_BYTE_0F3A,
1714   THREE_BYTE_0F7A
1715 };
1716
1717 enum
1718 {
1719   XOP_08 = 0,
1720   XOP_09,
1721   XOP_0A
1722 };
1723
1724 enum
1725 {
1726   VEX_0F = 0,
1727   VEX_0F38,
1728   VEX_0F3A
1729 };
1730
1731 enum
1732 {
1733   EVEX_0F = 0,
1734   EVEX_0F38,
1735   EVEX_0F3A
1736 };
1737
1738 enum
1739 {
1740   VEX_LEN_0F10_P_1 = 0,
1741   VEX_LEN_0F10_P_3,
1742   VEX_LEN_0F11_P_1,
1743   VEX_LEN_0F11_P_3,
1744   VEX_LEN_0F12_P_0_M_0,
1745   VEX_LEN_0F12_P_0_M_1,
1746   VEX_LEN_0F12_P_2,
1747   VEX_LEN_0F13_M_0,
1748   VEX_LEN_0F16_P_0_M_0,
1749   VEX_LEN_0F16_P_0_M_1,
1750   VEX_LEN_0F16_P_2,
1751   VEX_LEN_0F17_M_0,
1752   VEX_LEN_0F2A_P_1,
1753   VEX_LEN_0F2A_P_3,
1754   VEX_LEN_0F2C_P_1,
1755   VEX_LEN_0F2C_P_3,
1756   VEX_LEN_0F2D_P_1,
1757   VEX_LEN_0F2D_P_3,
1758   VEX_LEN_0F2E_P_0,
1759   VEX_LEN_0F2E_P_2,
1760   VEX_LEN_0F2F_P_0,
1761   VEX_LEN_0F2F_P_2,
1762   VEX_LEN_0F41_P_0,
1763   VEX_LEN_0F41_P_2,
1764   VEX_LEN_0F42_P_0,
1765   VEX_LEN_0F42_P_2,
1766   VEX_LEN_0F44_P_0,
1767   VEX_LEN_0F44_P_2,
1768   VEX_LEN_0F45_P_0,
1769   VEX_LEN_0F45_P_2,
1770   VEX_LEN_0F46_P_0,
1771   VEX_LEN_0F46_P_2,
1772   VEX_LEN_0F47_P_0,
1773   VEX_LEN_0F47_P_2,
1774   VEX_LEN_0F4A_P_0,
1775   VEX_LEN_0F4A_P_2,
1776   VEX_LEN_0F4B_P_0,
1777   VEX_LEN_0F4B_P_2,
1778   VEX_LEN_0F51_P_1,
1779   VEX_LEN_0F51_P_3,
1780   VEX_LEN_0F52_P_1,
1781   VEX_LEN_0F53_P_1,
1782   VEX_LEN_0F58_P_1,
1783   VEX_LEN_0F58_P_3,
1784   VEX_LEN_0F59_P_1,
1785   VEX_LEN_0F59_P_3,
1786   VEX_LEN_0F5A_P_1,
1787   VEX_LEN_0F5A_P_3,
1788   VEX_LEN_0F5C_P_1,
1789   VEX_LEN_0F5C_P_3,
1790   VEX_LEN_0F5D_P_1,
1791   VEX_LEN_0F5D_P_3,
1792   VEX_LEN_0F5E_P_1,
1793   VEX_LEN_0F5E_P_3,
1794   VEX_LEN_0F5F_P_1,
1795   VEX_LEN_0F5F_P_3,
1796   VEX_LEN_0F6E_P_2,
1797   VEX_LEN_0F7E_P_1,
1798   VEX_LEN_0F7E_P_2,
1799   VEX_LEN_0F90_P_0,
1800   VEX_LEN_0F90_P_2,
1801   VEX_LEN_0F91_P_0,
1802   VEX_LEN_0F91_P_2,
1803   VEX_LEN_0F92_P_0,
1804   VEX_LEN_0F92_P_2,
1805   VEX_LEN_0F92_P_3,
1806   VEX_LEN_0F93_P_0,
1807   VEX_LEN_0F93_P_2,
1808   VEX_LEN_0F93_P_3,
1809   VEX_LEN_0F98_P_0,
1810   VEX_LEN_0F98_P_2,
1811   VEX_LEN_0F99_P_0,
1812   VEX_LEN_0F99_P_2,
1813   VEX_LEN_0FAE_R_2_M_0,
1814   VEX_LEN_0FAE_R_3_M_0,
1815   VEX_LEN_0FC2_P_1,
1816   VEX_LEN_0FC2_P_3,
1817   VEX_LEN_0FC4_P_2,
1818   VEX_LEN_0FC5_P_2,
1819   VEX_LEN_0FD6_P_2,
1820   VEX_LEN_0FF7_P_2,
1821   VEX_LEN_0F3816_P_2,
1822   VEX_LEN_0F3819_P_2,
1823   VEX_LEN_0F381A_P_2_M_0,
1824   VEX_LEN_0F3836_P_2,
1825   VEX_LEN_0F3841_P_2,
1826   VEX_LEN_0F385A_P_2_M_0,
1827   VEX_LEN_0F38DB_P_2,
1828   VEX_LEN_0F38DC_P_2,
1829   VEX_LEN_0F38DD_P_2,
1830   VEX_LEN_0F38DE_P_2,
1831   VEX_LEN_0F38DF_P_2,
1832   VEX_LEN_0F38F2_P_0,
1833   VEX_LEN_0F38F3_R_1_P_0,
1834   VEX_LEN_0F38F3_R_2_P_0,
1835   VEX_LEN_0F38F3_R_3_P_0,
1836   VEX_LEN_0F38F5_P_0,
1837   VEX_LEN_0F38F5_P_1,
1838   VEX_LEN_0F38F5_P_3,
1839   VEX_LEN_0F38F6_P_3,
1840   VEX_LEN_0F38F7_P_0,
1841   VEX_LEN_0F38F7_P_1,
1842   VEX_LEN_0F38F7_P_2,
1843   VEX_LEN_0F38F7_P_3,
1844   VEX_LEN_0F3A00_P_2,
1845   VEX_LEN_0F3A01_P_2,
1846   VEX_LEN_0F3A06_P_2,
1847   VEX_LEN_0F3A0A_P_2,
1848   VEX_LEN_0F3A0B_P_2,
1849   VEX_LEN_0F3A14_P_2,
1850   VEX_LEN_0F3A15_P_2,
1851   VEX_LEN_0F3A16_P_2,
1852   VEX_LEN_0F3A17_P_2,
1853   VEX_LEN_0F3A18_P_2,
1854   VEX_LEN_0F3A19_P_2,
1855   VEX_LEN_0F3A20_P_2,
1856   VEX_LEN_0F3A21_P_2,
1857   VEX_LEN_0F3A22_P_2,
1858   VEX_LEN_0F3A30_P_2,
1859   VEX_LEN_0F3A31_P_2,
1860   VEX_LEN_0F3A32_P_2,
1861   VEX_LEN_0F3A33_P_2,
1862   VEX_LEN_0F3A38_P_2,
1863   VEX_LEN_0F3A39_P_2,
1864   VEX_LEN_0F3A41_P_2,
1865   VEX_LEN_0F3A44_P_2,
1866   VEX_LEN_0F3A46_P_2,
1867   VEX_LEN_0F3A60_P_2,
1868   VEX_LEN_0F3A61_P_2,
1869   VEX_LEN_0F3A62_P_2,
1870   VEX_LEN_0F3A63_P_2,
1871   VEX_LEN_0F3A6A_P_2,
1872   VEX_LEN_0F3A6B_P_2,
1873   VEX_LEN_0F3A6E_P_2,
1874   VEX_LEN_0F3A6F_P_2,
1875   VEX_LEN_0F3A7A_P_2,
1876   VEX_LEN_0F3A7B_P_2,
1877   VEX_LEN_0F3A7E_P_2,
1878   VEX_LEN_0F3A7F_P_2,
1879   VEX_LEN_0F3ADF_P_2,
1880   VEX_LEN_0F3AF0_P_3,
1881   VEX_LEN_0FXOP_08_CC,
1882   VEX_LEN_0FXOP_08_CD,
1883   VEX_LEN_0FXOP_08_CE,
1884   VEX_LEN_0FXOP_08_CF,
1885   VEX_LEN_0FXOP_08_EC,
1886   VEX_LEN_0FXOP_08_ED,
1887   VEX_LEN_0FXOP_08_EE,
1888   VEX_LEN_0FXOP_08_EF,
1889   VEX_LEN_0FXOP_09_80,
1890   VEX_LEN_0FXOP_09_81
1891 };
1892
1893 enum
1894 {
1895   VEX_W_0F10_P_0 = 0,
1896   VEX_W_0F10_P_1,
1897   VEX_W_0F10_P_2,
1898   VEX_W_0F10_P_3,
1899   VEX_W_0F11_P_0,
1900   VEX_W_0F11_P_1,
1901   VEX_W_0F11_P_2,
1902   VEX_W_0F11_P_3,
1903   VEX_W_0F12_P_0_M_0,
1904   VEX_W_0F12_P_0_M_1,
1905   VEX_W_0F12_P_1,
1906   VEX_W_0F12_P_2,
1907   VEX_W_0F12_P_3,
1908   VEX_W_0F13_M_0,
1909   VEX_W_0F14,
1910   VEX_W_0F15,
1911   VEX_W_0F16_P_0_M_0,
1912   VEX_W_0F16_P_0_M_1,
1913   VEX_W_0F16_P_1,
1914   VEX_W_0F16_P_2,
1915   VEX_W_0F17_M_0,
1916   VEX_W_0F28,
1917   VEX_W_0F29,
1918   VEX_W_0F2B_M_0,
1919   VEX_W_0F2E_P_0,
1920   VEX_W_0F2E_P_2,
1921   VEX_W_0F2F_P_0,
1922   VEX_W_0F2F_P_2,
1923   VEX_W_0F41_P_0_LEN_1,
1924   VEX_W_0F41_P_2_LEN_1,
1925   VEX_W_0F42_P_0_LEN_1,
1926   VEX_W_0F42_P_2_LEN_1,
1927   VEX_W_0F44_P_0_LEN_0,
1928   VEX_W_0F44_P_2_LEN_0,
1929   VEX_W_0F45_P_0_LEN_1,
1930   VEX_W_0F45_P_2_LEN_1,
1931   VEX_W_0F46_P_0_LEN_1,
1932   VEX_W_0F46_P_2_LEN_1,
1933   VEX_W_0F47_P_0_LEN_1,
1934   VEX_W_0F47_P_2_LEN_1,
1935   VEX_W_0F4A_P_0_LEN_1,
1936   VEX_W_0F4A_P_2_LEN_1,
1937   VEX_W_0F4B_P_0_LEN_1,
1938   VEX_W_0F4B_P_2_LEN_1,
1939   VEX_W_0F50_M_0,
1940   VEX_W_0F51_P_0,
1941   VEX_W_0F51_P_1,
1942   VEX_W_0F51_P_2,
1943   VEX_W_0F51_P_3,
1944   VEX_W_0F52_P_0,
1945   VEX_W_0F52_P_1,
1946   VEX_W_0F53_P_0,
1947   VEX_W_0F53_P_1,
1948   VEX_W_0F58_P_0,
1949   VEX_W_0F58_P_1,
1950   VEX_W_0F58_P_2,
1951   VEX_W_0F58_P_3,
1952   VEX_W_0F59_P_0,
1953   VEX_W_0F59_P_1,
1954   VEX_W_0F59_P_2,
1955   VEX_W_0F59_P_3,
1956   VEX_W_0F5A_P_0,
1957   VEX_W_0F5A_P_1,
1958   VEX_W_0F5A_P_3,
1959   VEX_W_0F5B_P_0,
1960   VEX_W_0F5B_P_1,
1961   VEX_W_0F5B_P_2,
1962   VEX_W_0F5C_P_0,
1963   VEX_W_0F5C_P_1,
1964   VEX_W_0F5C_P_2,
1965   VEX_W_0F5C_P_3,
1966   VEX_W_0F5D_P_0,
1967   VEX_W_0F5D_P_1,
1968   VEX_W_0F5D_P_2,
1969   VEX_W_0F5D_P_3,
1970   VEX_W_0F5E_P_0,
1971   VEX_W_0F5E_P_1,
1972   VEX_W_0F5E_P_2,
1973   VEX_W_0F5E_P_3,
1974   VEX_W_0F5F_P_0,
1975   VEX_W_0F5F_P_1,
1976   VEX_W_0F5F_P_2,
1977   VEX_W_0F5F_P_3,
1978   VEX_W_0F60_P_2,
1979   VEX_W_0F61_P_2,
1980   VEX_W_0F62_P_2,
1981   VEX_W_0F63_P_2,
1982   VEX_W_0F64_P_2,
1983   VEX_W_0F65_P_2,
1984   VEX_W_0F66_P_2,
1985   VEX_W_0F67_P_2,
1986   VEX_W_0F68_P_2,
1987   VEX_W_0F69_P_2,
1988   VEX_W_0F6A_P_2,
1989   VEX_W_0F6B_P_2,
1990   VEX_W_0F6C_P_2,
1991   VEX_W_0F6D_P_2,
1992   VEX_W_0F6F_P_1,
1993   VEX_W_0F6F_P_2,
1994   VEX_W_0F70_P_1,
1995   VEX_W_0F70_P_2,
1996   VEX_W_0F70_P_3,
1997   VEX_W_0F71_R_2_P_2,
1998   VEX_W_0F71_R_4_P_2,
1999   VEX_W_0F71_R_6_P_2,
2000   VEX_W_0F72_R_2_P_2,
2001   VEX_W_0F72_R_4_P_2,
2002   VEX_W_0F72_R_6_P_2,
2003   VEX_W_0F73_R_2_P_2,
2004   VEX_W_0F73_R_3_P_2,
2005   VEX_W_0F73_R_6_P_2,
2006   VEX_W_0F73_R_7_P_2,
2007   VEX_W_0F74_P_2,
2008   VEX_W_0F75_P_2,
2009   VEX_W_0F76_P_2,
2010   VEX_W_0F77_P_0,
2011   VEX_W_0F7C_P_2,
2012   VEX_W_0F7C_P_3,
2013   VEX_W_0F7D_P_2,
2014   VEX_W_0F7D_P_3,
2015   VEX_W_0F7E_P_1,
2016   VEX_W_0F7F_P_1,
2017   VEX_W_0F7F_P_2,
2018   VEX_W_0F90_P_0_LEN_0,
2019   VEX_W_0F90_P_2_LEN_0,
2020   VEX_W_0F91_P_0_LEN_0,
2021   VEX_W_0F91_P_2_LEN_0,
2022   VEX_W_0F92_P_0_LEN_0,
2023   VEX_W_0F92_P_2_LEN_0,
2024   VEX_W_0F92_P_3_LEN_0,
2025   VEX_W_0F93_P_0_LEN_0,
2026   VEX_W_0F93_P_2_LEN_0,
2027   VEX_W_0F93_P_3_LEN_0,
2028   VEX_W_0F98_P_0_LEN_0,
2029   VEX_W_0F98_P_2_LEN_0,
2030   VEX_W_0F99_P_0_LEN_0,
2031   VEX_W_0F99_P_2_LEN_0,
2032   VEX_W_0FAE_R_2_M_0,
2033   VEX_W_0FAE_R_3_M_0,
2034   VEX_W_0FC2_P_0,
2035   VEX_W_0FC2_P_1,
2036   VEX_W_0FC2_P_2,
2037   VEX_W_0FC2_P_3,
2038   VEX_W_0FC4_P_2,
2039   VEX_W_0FC5_P_2,
2040   VEX_W_0FD0_P_2,
2041   VEX_W_0FD0_P_3,
2042   VEX_W_0FD1_P_2,
2043   VEX_W_0FD2_P_2,
2044   VEX_W_0FD3_P_2,
2045   VEX_W_0FD4_P_2,
2046   VEX_W_0FD5_P_2,
2047   VEX_W_0FD6_P_2,
2048   VEX_W_0FD7_P_2_M_1,
2049   VEX_W_0FD8_P_2,
2050   VEX_W_0FD9_P_2,
2051   VEX_W_0FDA_P_2,
2052   VEX_W_0FDB_P_2,
2053   VEX_W_0FDC_P_2,
2054   VEX_W_0FDD_P_2,
2055   VEX_W_0FDE_P_2,
2056   VEX_W_0FDF_P_2,
2057   VEX_W_0FE0_P_2,
2058   VEX_W_0FE1_P_2,
2059   VEX_W_0FE2_P_2,
2060   VEX_W_0FE3_P_2,
2061   VEX_W_0FE4_P_2,
2062   VEX_W_0FE5_P_2,
2063   VEX_W_0FE6_P_1,
2064   VEX_W_0FE6_P_2,
2065   VEX_W_0FE6_P_3,
2066   VEX_W_0FE7_P_2_M_0,
2067   VEX_W_0FE8_P_2,
2068   VEX_W_0FE9_P_2,
2069   VEX_W_0FEA_P_2,
2070   VEX_W_0FEB_P_2,
2071   VEX_W_0FEC_P_2,
2072   VEX_W_0FED_P_2,
2073   VEX_W_0FEE_P_2,
2074   VEX_W_0FEF_P_2,
2075   VEX_W_0FF0_P_3_M_0,
2076   VEX_W_0FF1_P_2,
2077   VEX_W_0FF2_P_2,
2078   VEX_W_0FF3_P_2,
2079   VEX_W_0FF4_P_2,
2080   VEX_W_0FF5_P_2,
2081   VEX_W_0FF6_P_2,
2082   VEX_W_0FF7_P_2,
2083   VEX_W_0FF8_P_2,
2084   VEX_W_0FF9_P_2,
2085   VEX_W_0FFA_P_2,
2086   VEX_W_0FFB_P_2,
2087   VEX_W_0FFC_P_2,
2088   VEX_W_0FFD_P_2,
2089   VEX_W_0FFE_P_2,
2090   VEX_W_0F3800_P_2,
2091   VEX_W_0F3801_P_2,
2092   VEX_W_0F3802_P_2,
2093   VEX_W_0F3803_P_2,
2094   VEX_W_0F3804_P_2,
2095   VEX_W_0F3805_P_2,
2096   VEX_W_0F3806_P_2,
2097   VEX_W_0F3807_P_2,
2098   VEX_W_0F3808_P_2,
2099   VEX_W_0F3809_P_2,
2100   VEX_W_0F380A_P_2,
2101   VEX_W_0F380B_P_2,
2102   VEX_W_0F380C_P_2,
2103   VEX_W_0F380D_P_2,
2104   VEX_W_0F380E_P_2,
2105   VEX_W_0F380F_P_2,
2106   VEX_W_0F3816_P_2,
2107   VEX_W_0F3817_P_2,
2108   VEX_W_0F3818_P_2,
2109   VEX_W_0F3819_P_2,
2110   VEX_W_0F381A_P_2_M_0,
2111   VEX_W_0F381C_P_2,
2112   VEX_W_0F381D_P_2,
2113   VEX_W_0F381E_P_2,
2114   VEX_W_0F3820_P_2,
2115   VEX_W_0F3821_P_2,
2116   VEX_W_0F3822_P_2,
2117   VEX_W_0F3823_P_2,
2118   VEX_W_0F3824_P_2,
2119   VEX_W_0F3825_P_2,
2120   VEX_W_0F3828_P_2,
2121   VEX_W_0F3829_P_2,
2122   VEX_W_0F382A_P_2_M_0,
2123   VEX_W_0F382B_P_2,
2124   VEX_W_0F382C_P_2_M_0,
2125   VEX_W_0F382D_P_2_M_0,
2126   VEX_W_0F382E_P_2_M_0,
2127   VEX_W_0F382F_P_2_M_0,
2128   VEX_W_0F3830_P_2,
2129   VEX_W_0F3831_P_2,
2130   VEX_W_0F3832_P_2,
2131   VEX_W_0F3833_P_2,
2132   VEX_W_0F3834_P_2,
2133   VEX_W_0F3835_P_2,
2134   VEX_W_0F3836_P_2,
2135   VEX_W_0F3837_P_2,
2136   VEX_W_0F3838_P_2,
2137   VEX_W_0F3839_P_2,
2138   VEX_W_0F383A_P_2,
2139   VEX_W_0F383B_P_2,
2140   VEX_W_0F383C_P_2,
2141   VEX_W_0F383D_P_2,
2142   VEX_W_0F383E_P_2,
2143   VEX_W_0F383F_P_2,
2144   VEX_W_0F3840_P_2,
2145   VEX_W_0F3841_P_2,
2146   VEX_W_0F3846_P_2,
2147   VEX_W_0F3858_P_2,
2148   VEX_W_0F3859_P_2,
2149   VEX_W_0F385A_P_2_M_0,
2150   VEX_W_0F3878_P_2,
2151   VEX_W_0F3879_P_2,
2152   VEX_W_0F38DB_P_2,
2153   VEX_W_0F38DC_P_2,
2154   VEX_W_0F38DD_P_2,
2155   VEX_W_0F38DE_P_2,
2156   VEX_W_0F38DF_P_2,
2157   VEX_W_0F3A00_P_2,
2158   VEX_W_0F3A01_P_2,
2159   VEX_W_0F3A02_P_2,
2160   VEX_W_0F3A04_P_2,
2161   VEX_W_0F3A05_P_2,
2162   VEX_W_0F3A06_P_2,
2163   VEX_W_0F3A08_P_2,
2164   VEX_W_0F3A09_P_2,
2165   VEX_W_0F3A0A_P_2,
2166   VEX_W_0F3A0B_P_2,
2167   VEX_W_0F3A0C_P_2,
2168   VEX_W_0F3A0D_P_2,
2169   VEX_W_0F3A0E_P_2,
2170   VEX_W_0F3A0F_P_2,
2171   VEX_W_0F3A14_P_2,
2172   VEX_W_0F3A15_P_2,
2173   VEX_W_0F3A18_P_2,
2174   VEX_W_0F3A19_P_2,
2175   VEX_W_0F3A20_P_2,
2176   VEX_W_0F3A21_P_2,
2177   VEX_W_0F3A30_P_2_LEN_0,
2178   VEX_W_0F3A31_P_2_LEN_0,
2179   VEX_W_0F3A32_P_2_LEN_0,
2180   VEX_W_0F3A33_P_2_LEN_0,
2181   VEX_W_0F3A38_P_2,
2182   VEX_W_0F3A39_P_2,
2183   VEX_W_0F3A40_P_2,
2184   VEX_W_0F3A41_P_2,
2185   VEX_W_0F3A42_P_2,
2186   VEX_W_0F3A44_P_2,
2187   VEX_W_0F3A46_P_2,
2188   VEX_W_0F3A48_P_2,
2189   VEX_W_0F3A49_P_2,
2190   VEX_W_0F3A4A_P_2,
2191   VEX_W_0F3A4B_P_2,
2192   VEX_W_0F3A4C_P_2,
2193   VEX_W_0F3A60_P_2,
2194   VEX_W_0F3A61_P_2,
2195   VEX_W_0F3A62_P_2,
2196   VEX_W_0F3A63_P_2,
2197   VEX_W_0F3ADF_P_2,
2198
2199   EVEX_W_0F10_P_0,
2200   EVEX_W_0F10_P_1_M_0,
2201   EVEX_W_0F10_P_1_M_1,
2202   EVEX_W_0F10_P_2,
2203   EVEX_W_0F10_P_3_M_0,
2204   EVEX_W_0F10_P_3_M_1,
2205   EVEX_W_0F11_P_0,
2206   EVEX_W_0F11_P_1_M_0,
2207   EVEX_W_0F11_P_1_M_1,
2208   EVEX_W_0F11_P_2,
2209   EVEX_W_0F11_P_3_M_0,
2210   EVEX_W_0F11_P_3_M_1,
2211   EVEX_W_0F12_P_0_M_0,
2212   EVEX_W_0F12_P_0_M_1,
2213   EVEX_W_0F12_P_1,
2214   EVEX_W_0F12_P_2,
2215   EVEX_W_0F12_P_3,
2216   EVEX_W_0F13_P_0,
2217   EVEX_W_0F13_P_2,
2218   EVEX_W_0F14_P_0,
2219   EVEX_W_0F14_P_2,
2220   EVEX_W_0F15_P_0,
2221   EVEX_W_0F15_P_2,
2222   EVEX_W_0F16_P_0_M_0,
2223   EVEX_W_0F16_P_0_M_1,
2224   EVEX_W_0F16_P_1,
2225   EVEX_W_0F16_P_2,
2226   EVEX_W_0F17_P_0,
2227   EVEX_W_0F17_P_2,
2228   EVEX_W_0F28_P_0,
2229   EVEX_W_0F28_P_2,
2230   EVEX_W_0F29_P_0,
2231   EVEX_W_0F29_P_2,
2232   EVEX_W_0F2A_P_1,
2233   EVEX_W_0F2A_P_3,
2234   EVEX_W_0F2B_P_0,
2235   EVEX_W_0F2B_P_2,
2236   EVEX_W_0F2E_P_0,
2237   EVEX_W_0F2E_P_2,
2238   EVEX_W_0F2F_P_0,
2239   EVEX_W_0F2F_P_2,
2240   EVEX_W_0F51_P_0,
2241   EVEX_W_0F51_P_1,
2242   EVEX_W_0F51_P_2,
2243   EVEX_W_0F51_P_3,
2244   EVEX_W_0F54_P_0,
2245   EVEX_W_0F54_P_2,
2246   EVEX_W_0F55_P_0,
2247   EVEX_W_0F55_P_2,
2248   EVEX_W_0F56_P_0,
2249   EVEX_W_0F56_P_2,
2250   EVEX_W_0F57_P_0,
2251   EVEX_W_0F57_P_2,
2252   EVEX_W_0F58_P_0,
2253   EVEX_W_0F58_P_1,
2254   EVEX_W_0F58_P_2,
2255   EVEX_W_0F58_P_3,
2256   EVEX_W_0F59_P_0,
2257   EVEX_W_0F59_P_1,
2258   EVEX_W_0F59_P_2,
2259   EVEX_W_0F59_P_3,
2260   EVEX_W_0F5A_P_0,
2261   EVEX_W_0F5A_P_1,
2262   EVEX_W_0F5A_P_2,
2263   EVEX_W_0F5A_P_3,
2264   EVEX_W_0F5B_P_0,
2265   EVEX_W_0F5B_P_1,
2266   EVEX_W_0F5B_P_2,
2267   EVEX_W_0F5C_P_0,
2268   EVEX_W_0F5C_P_1,
2269   EVEX_W_0F5C_P_2,
2270   EVEX_W_0F5C_P_3,
2271   EVEX_W_0F5D_P_0,
2272   EVEX_W_0F5D_P_1,
2273   EVEX_W_0F5D_P_2,
2274   EVEX_W_0F5D_P_3,
2275   EVEX_W_0F5E_P_0,
2276   EVEX_W_0F5E_P_1,
2277   EVEX_W_0F5E_P_2,
2278   EVEX_W_0F5E_P_3,
2279   EVEX_W_0F5F_P_0,
2280   EVEX_W_0F5F_P_1,
2281   EVEX_W_0F5F_P_2,
2282   EVEX_W_0F5F_P_3,
2283   EVEX_W_0F62_P_2,
2284   EVEX_W_0F66_P_2,
2285   EVEX_W_0F6A_P_2,
2286   EVEX_W_0F6B_P_2,
2287   EVEX_W_0F6C_P_2,
2288   EVEX_W_0F6D_P_2,
2289   EVEX_W_0F6E_P_2,
2290   EVEX_W_0F6F_P_1,
2291   EVEX_W_0F6F_P_2,
2292   EVEX_W_0F6F_P_3,
2293   EVEX_W_0F70_P_2,
2294   EVEX_W_0F72_R_2_P_2,
2295   EVEX_W_0F72_R_6_P_2,
2296   EVEX_W_0F73_R_2_P_2,
2297   EVEX_W_0F73_R_6_P_2,
2298   EVEX_W_0F76_P_2,
2299   EVEX_W_0F78_P_0,
2300   EVEX_W_0F78_P_2,
2301   EVEX_W_0F79_P_0,
2302   EVEX_W_0F79_P_2,
2303   EVEX_W_0F7A_P_1,
2304   EVEX_W_0F7A_P_2,
2305   EVEX_W_0F7A_P_3,
2306   EVEX_W_0F7B_P_1,
2307   EVEX_W_0F7B_P_2,
2308   EVEX_W_0F7B_P_3,
2309   EVEX_W_0F7E_P_1,
2310   EVEX_W_0F7E_P_2,
2311   EVEX_W_0F7F_P_1,
2312   EVEX_W_0F7F_P_2,
2313   EVEX_W_0F7F_P_3,
2314   EVEX_W_0FC2_P_0,
2315   EVEX_W_0FC2_P_1,
2316   EVEX_W_0FC2_P_2,
2317   EVEX_W_0FC2_P_3,
2318   EVEX_W_0FC6_P_0,
2319   EVEX_W_0FC6_P_2,
2320   EVEX_W_0FD2_P_2,
2321   EVEX_W_0FD3_P_2,
2322   EVEX_W_0FD4_P_2,
2323   EVEX_W_0FD6_P_2,
2324   EVEX_W_0FE6_P_1,
2325   EVEX_W_0FE6_P_2,
2326   EVEX_W_0FE6_P_3,
2327   EVEX_W_0FE7_P_2,
2328   EVEX_W_0FF2_P_2,
2329   EVEX_W_0FF3_P_2,
2330   EVEX_W_0FF4_P_2,
2331   EVEX_W_0FFA_P_2,
2332   EVEX_W_0FFB_P_2,
2333   EVEX_W_0FFE_P_2,
2334   EVEX_W_0F380C_P_2,
2335   EVEX_W_0F380D_P_2,
2336   EVEX_W_0F3810_P_1,
2337   EVEX_W_0F3810_P_2,
2338   EVEX_W_0F3811_P_1,
2339   EVEX_W_0F3811_P_2,
2340   EVEX_W_0F3812_P_1,
2341   EVEX_W_0F3812_P_2,
2342   EVEX_W_0F3813_P_1,
2343   EVEX_W_0F3813_P_2,
2344   EVEX_W_0F3814_P_1,
2345   EVEX_W_0F3815_P_1,
2346   EVEX_W_0F3818_P_2,
2347   EVEX_W_0F3819_P_2,
2348   EVEX_W_0F381A_P_2,
2349   EVEX_W_0F381B_P_2,
2350   EVEX_W_0F381E_P_2,
2351   EVEX_W_0F381F_P_2,
2352   EVEX_W_0F3820_P_1,
2353   EVEX_W_0F3821_P_1,
2354   EVEX_W_0F3822_P_1,
2355   EVEX_W_0F3823_P_1,
2356   EVEX_W_0F3824_P_1,
2357   EVEX_W_0F3825_P_1,
2358   EVEX_W_0F3825_P_2,
2359   EVEX_W_0F3826_P_1,
2360   EVEX_W_0F3826_P_2,
2361   EVEX_W_0F3828_P_1,
2362   EVEX_W_0F3828_P_2,
2363   EVEX_W_0F3829_P_1,
2364   EVEX_W_0F3829_P_2,
2365   EVEX_W_0F382A_P_1,
2366   EVEX_W_0F382A_P_2,
2367   EVEX_W_0F382B_P_2,
2368   EVEX_W_0F3830_P_1,
2369   EVEX_W_0F3831_P_1,
2370   EVEX_W_0F3832_P_1,
2371   EVEX_W_0F3833_P_1,
2372   EVEX_W_0F3834_P_1,
2373   EVEX_W_0F3835_P_1,
2374   EVEX_W_0F3835_P_2,
2375   EVEX_W_0F3837_P_2,
2376   EVEX_W_0F3838_P_1,
2377   EVEX_W_0F3839_P_1,
2378   EVEX_W_0F383A_P_1,
2379   EVEX_W_0F3840_P_2,
2380   EVEX_W_0F3858_P_2,
2381   EVEX_W_0F3859_P_2,
2382   EVEX_W_0F385A_P_2,
2383   EVEX_W_0F385B_P_2,
2384   EVEX_W_0F3866_P_2,
2385   EVEX_W_0F3875_P_2,
2386   EVEX_W_0F3878_P_2,
2387   EVEX_W_0F3879_P_2,
2388   EVEX_W_0F387A_P_2,
2389   EVEX_W_0F387B_P_2,
2390   EVEX_W_0F387D_P_2,
2391   EVEX_W_0F3883_P_2,
2392   EVEX_W_0F388D_P_2,
2393   EVEX_W_0F3891_P_2,
2394   EVEX_W_0F3893_P_2,
2395   EVEX_W_0F38A1_P_2,
2396   EVEX_W_0F38A3_P_2,
2397   EVEX_W_0F38C7_R_1_P_2,
2398   EVEX_W_0F38C7_R_2_P_2,
2399   EVEX_W_0F38C7_R_5_P_2,
2400   EVEX_W_0F38C7_R_6_P_2,
2401
2402   EVEX_W_0F3A00_P_2,
2403   EVEX_W_0F3A01_P_2,
2404   EVEX_W_0F3A04_P_2,
2405   EVEX_W_0F3A05_P_2,
2406   EVEX_W_0F3A08_P_2,
2407   EVEX_W_0F3A09_P_2,
2408   EVEX_W_0F3A0A_P_2,
2409   EVEX_W_0F3A0B_P_2,
2410   EVEX_W_0F3A16_P_2,
2411   EVEX_W_0F3A18_P_2,
2412   EVEX_W_0F3A19_P_2,
2413   EVEX_W_0F3A1A_P_2,
2414   EVEX_W_0F3A1B_P_2,
2415   EVEX_W_0F3A1D_P_2,
2416   EVEX_W_0F3A21_P_2,
2417   EVEX_W_0F3A22_P_2,
2418   EVEX_W_0F3A23_P_2,
2419   EVEX_W_0F3A38_P_2,
2420   EVEX_W_0F3A39_P_2,
2421   EVEX_W_0F3A3A_P_2,
2422   EVEX_W_0F3A3B_P_2,
2423   EVEX_W_0F3A3E_P_2,
2424   EVEX_W_0F3A3F_P_2,
2425   EVEX_W_0F3A42_P_2,
2426   EVEX_W_0F3A43_P_2,
2427   EVEX_W_0F3A50_P_2,
2428   EVEX_W_0F3A51_P_2,
2429   EVEX_W_0F3A56_P_2,
2430   EVEX_W_0F3A57_P_2,
2431   EVEX_W_0F3A66_P_2,
2432   EVEX_W_0F3A67_P_2
2433 };
2434
2435 typedef void (*op_rtn) (int bytemode, int sizeflag);
2436
2437 struct dis386 {
2438   const char *name;
2439   struct
2440     {
2441       op_rtn rtn;
2442       int bytemode;
2443     } op[MAX_OPERANDS];
2444   unsigned int prefix_requirement;
2445 };
2446
2447 /* Upper case letters in the instruction names here are macros.
2448    'A' => print 'b' if no register operands or suffix_always is true
2449    'B' => print 'b' if suffix_always is true
2450    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2451           size prefix
2452    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2453           suffix_always is true
2454    'E' => print 'e' if 32-bit form of jcxz
2455    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2456    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2457    'H' => print ",pt" or ",pn" branch hint
2458    'I' => honor following macro letter even in Intel mode (implemented only
2459           for some of the macro letters)
2460    'J' => print 'l'
2461    'K' => print 'd' or 'q' if rex prefix is present.
2462    'L' => print 'l' if suffix_always is true
2463    'M' => print 'r' if intel_mnemonic is false.
2464    'N' => print 'n' if instruction has no wait "prefix"
2465    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2466    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2467           or suffix_always is true.  print 'q' if rex prefix is present.
2468    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2469           is true
2470    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2471    'S' => print 'w', 'l' or 'q' if suffix_always is true
2472    'T' => print 'q' in 64bit mode if instruction has no operand size
2473           prefix and behave as 'P' otherwise
2474    'U' => print 'q' in 64bit mode if instruction has no operand size
2475           prefix and behave as 'Q' otherwise
2476    'V' => print 'q' in 64bit mode if instruction has no operand size
2477           prefix and behave as 'S' otherwise
2478    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2479    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2480    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2481           suffix_always is true.
2482    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2483    '!' => change condition from true to false or from false to true.
2484    '%' => add 1 upper case letter to the macro.
2485    '^' => print 'w' or 'l' depending on operand size prefix or
2486           suffix_always is true (lcall/ljmp).
2487    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2488           on operand size prefix.
2489    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2490           has no operand size prefix for AMD64 ISA, behave as 'P'
2491           otherwise
2492
2493    2 upper case letter macros:
2494    "XY" => print 'x' or 'y' if suffix_always is true or no register
2495            operands and no broadcast.
2496    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2497            register operands and no broadcast.
2498    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2499    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2500            or suffix_always is true
2501    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2502    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2503    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2504    "LW" => print 'd', 'q' depending on the VEX.W bit
2505    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2506            an operand size prefix, or suffix_always is true.  print
2507            'q' if rex prefix is present.
2508
2509    Many of the above letters print nothing in Intel mode.  See "putop"
2510    for the details.
2511
2512    Braces '{' and '}', and vertical bars '|', indicate alternative
2513    mnemonic strings for AT&T and Intel.  */
2514
2515 static const struct dis386 dis386[] = {
2516   /* 00 */
2517   { "addB",             { Ebh1, Gb }, 0 },
2518   { "addS",             { Evh1, Gv }, 0 },
2519   { "addB",             { Gb, EbS }, 0 },
2520   { "addS",             { Gv, EvS }, 0 },
2521   { "addB",             { AL, Ib }, 0 },
2522   { "addS",             { eAX, Iv }, 0 },
2523   { X86_64_TABLE (X86_64_06) },
2524   { X86_64_TABLE (X86_64_07) },
2525   /* 08 */
2526   { "orB",              { Ebh1, Gb }, 0 },
2527   { "orS",              { Evh1, Gv }, 0 },
2528   { "orB",              { Gb, EbS }, 0 },
2529   { "orS",              { Gv, EvS }, 0 },
2530   { "orB",              { AL, Ib }, 0 },
2531   { "orS",              { eAX, Iv }, 0 },
2532   { X86_64_TABLE (X86_64_0D) },
2533   { Bad_Opcode },       /* 0x0f extended opcode escape */
2534   /* 10 */
2535   { "adcB",             { Ebh1, Gb }, 0 },
2536   { "adcS",             { Evh1, Gv }, 0 },
2537   { "adcB",             { Gb, EbS }, 0 },
2538   { "adcS",             { Gv, EvS }, 0 },
2539   { "adcB",             { AL, Ib }, 0 },
2540   { "adcS",             { eAX, Iv }, 0 },
2541   { X86_64_TABLE (X86_64_16) },
2542   { X86_64_TABLE (X86_64_17) },
2543   /* 18 */
2544   { "sbbB",             { Ebh1, Gb }, 0 },
2545   { "sbbS",             { Evh1, Gv }, 0 },
2546   { "sbbB",             { Gb, EbS }, 0 },
2547   { "sbbS",             { Gv, EvS }, 0 },
2548   { "sbbB",             { AL, Ib }, 0 },
2549   { "sbbS",             { eAX, Iv }, 0 },
2550   { X86_64_TABLE (X86_64_1E) },
2551   { X86_64_TABLE (X86_64_1F) },
2552   /* 20 */
2553   { "andB",             { Ebh1, Gb }, 0 },
2554   { "andS",             { Evh1, Gv }, 0 },
2555   { "andB",             { Gb, EbS }, 0 },
2556   { "andS",             { Gv, EvS }, 0 },
2557   { "andB",             { AL, Ib }, 0 },
2558   { "andS",             { eAX, Iv }, 0 },
2559   { Bad_Opcode },       /* SEG ES prefix */
2560   { X86_64_TABLE (X86_64_27) },
2561   /* 28 */
2562   { "subB",             { Ebh1, Gb }, 0 },
2563   { "subS",             { Evh1, Gv }, 0 },
2564   { "subB",             { Gb, EbS }, 0 },
2565   { "subS",             { Gv, EvS }, 0 },
2566   { "subB",             { AL, Ib }, 0 },
2567   { "subS",             { eAX, Iv }, 0 },
2568   { Bad_Opcode },       /* SEG CS prefix */
2569   { X86_64_TABLE (X86_64_2F) },
2570   /* 30 */
2571   { "xorB",             { Ebh1, Gb }, 0 },
2572   { "xorS",             { Evh1, Gv }, 0 },
2573   { "xorB",             { Gb, EbS }, 0 },
2574   { "xorS",             { Gv, EvS }, 0 },
2575   { "xorB",             { AL, Ib }, 0 },
2576   { "xorS",             { eAX, Iv }, 0 },
2577   { Bad_Opcode },       /* SEG SS prefix */
2578   { X86_64_TABLE (X86_64_37) },
2579   /* 38 */
2580   { "cmpB",             { Eb, Gb }, 0 },
2581   { "cmpS",             { Ev, Gv }, 0 },
2582   { "cmpB",             { Gb, EbS }, 0 },
2583   { "cmpS",             { Gv, EvS }, 0 },
2584   { "cmpB",             { AL, Ib }, 0 },
2585   { "cmpS",             { eAX, Iv }, 0 },
2586   { Bad_Opcode },       /* SEG DS prefix */
2587   { X86_64_TABLE (X86_64_3F) },
2588   /* 40 */
2589   { "inc{S|}",          { RMeAX }, 0 },
2590   { "inc{S|}",          { RMeCX }, 0 },
2591   { "inc{S|}",          { RMeDX }, 0 },
2592   { "inc{S|}",          { RMeBX }, 0 },
2593   { "inc{S|}",          { RMeSP }, 0 },
2594   { "inc{S|}",          { RMeBP }, 0 },
2595   { "inc{S|}",          { RMeSI }, 0 },
2596   { "inc{S|}",          { RMeDI }, 0 },
2597   /* 48 */
2598   { "dec{S|}",          { RMeAX }, 0 },
2599   { "dec{S|}",          { RMeCX }, 0 },
2600   { "dec{S|}",          { RMeDX }, 0 },
2601   { "dec{S|}",          { RMeBX }, 0 },
2602   { "dec{S|}",          { RMeSP }, 0 },
2603   { "dec{S|}",          { RMeBP }, 0 },
2604   { "dec{S|}",          { RMeSI }, 0 },
2605   { "dec{S|}",          { RMeDI }, 0 },
2606   /* 50 */
2607   { "pushV",            { RMrAX }, 0 },
2608   { "pushV",            { RMrCX }, 0 },
2609   { "pushV",            { RMrDX }, 0 },
2610   { "pushV",            { RMrBX }, 0 },
2611   { "pushV",            { RMrSP }, 0 },
2612   { "pushV",            { RMrBP }, 0 },
2613   { "pushV",            { RMrSI }, 0 },
2614   { "pushV",            { RMrDI }, 0 },
2615   /* 58 */
2616   { "popV",             { RMrAX }, 0 },
2617   { "popV",             { RMrCX }, 0 },
2618   { "popV",             { RMrDX }, 0 },
2619   { "popV",             { RMrBX }, 0 },
2620   { "popV",             { RMrSP }, 0 },
2621   { "popV",             { RMrBP }, 0 },
2622   { "popV",             { RMrSI }, 0 },
2623   { "popV",             { RMrDI }, 0 },
2624   /* 60 */
2625   { X86_64_TABLE (X86_64_60) },
2626   { X86_64_TABLE (X86_64_61) },
2627   { X86_64_TABLE (X86_64_62) },
2628   { X86_64_TABLE (X86_64_63) },
2629   { Bad_Opcode },       /* seg fs */
2630   { Bad_Opcode },       /* seg gs */
2631   { Bad_Opcode },       /* op size prefix */
2632   { Bad_Opcode },       /* adr size prefix */
2633   /* 68 */
2634   { "pushT",            { sIv }, 0 },
2635   { "imulS",            { Gv, Ev, Iv }, 0 },
2636   { "pushT",            { sIbT }, 0 },
2637   { "imulS",            { Gv, Ev, sIb }, 0 },
2638   { "ins{b|}",          { Ybr, indirDX }, 0 },
2639   { X86_64_TABLE (X86_64_6D) },
2640   { "outs{b|}",         { indirDXr, Xb }, 0 },
2641   { X86_64_TABLE (X86_64_6F) },
2642   /* 70 */
2643   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2644   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2645   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2646   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2647   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2648   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2649   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2650   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2651   /* 78 */
2652   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2653   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2654   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2655   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2656   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2657   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2658   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2659   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2660   /* 80 */
2661   { REG_TABLE (REG_80) },
2662   { REG_TABLE (REG_81) },
2663   { Bad_Opcode },
2664   { REG_TABLE (REG_82) },
2665   { "testB",            { Eb, Gb }, 0 },
2666   { "testS",            { Ev, Gv }, 0 },
2667   { "xchgB",            { Ebh2, Gb }, 0 },
2668   { "xchgS",            { Evh2, Gv }, 0 },
2669   /* 88 */
2670   { "movB",             { Ebh3, Gb }, 0 },
2671   { "movS",             { Evh3, Gv }, 0 },
2672   { "movB",             { Gb, EbS }, 0 },
2673   { "movS",             { Gv, EvS }, 0 },
2674   { "movD",             { Sv, Sw }, 0 },
2675   { MOD_TABLE (MOD_8D) },
2676   { "movD",             { Sw, Sv }, 0 },
2677   { REG_TABLE (REG_8F) },
2678   /* 90 */
2679   { PREFIX_TABLE (PREFIX_90) },
2680   { "xchgS",            { RMeCX, eAX }, 0 },
2681   { "xchgS",            { RMeDX, eAX }, 0 },
2682   { "xchgS",            { RMeBX, eAX }, 0 },
2683   { "xchgS",            { RMeSP, eAX }, 0 },
2684   { "xchgS",            { RMeBP, eAX }, 0 },
2685   { "xchgS",            { RMeSI, eAX }, 0 },
2686   { "xchgS",            { RMeDI, eAX }, 0 },
2687   /* 98 */
2688   { "cW{t|}R",          { XX }, 0 },
2689   { "cR{t|}O",          { XX }, 0 },
2690   { X86_64_TABLE (X86_64_9A) },
2691   { Bad_Opcode },       /* fwait */
2692   { "pushfT",           { XX }, 0 },
2693   { "popfT",            { XX }, 0 },
2694   { "sahf",             { XX }, 0 },
2695   { "lahf",             { XX }, 0 },
2696   /* a0 */
2697   { "mov%LB",           { AL, Ob }, 0 },
2698   { "mov%LS",           { eAX, Ov }, 0 },
2699   { "mov%LB",           { Ob, AL }, 0 },
2700   { "mov%LS",           { Ov, eAX }, 0 },
2701   { "movs{b|}",         { Ybr, Xb }, 0 },
2702   { "movs{R|}",         { Yvr, Xv }, 0 },
2703   { "cmps{b|}",         { Xb, Yb }, 0 },
2704   { "cmps{R|}",         { Xv, Yv }, 0 },
2705   /* a8 */
2706   { "testB",            { AL, Ib }, 0 },
2707   { "testS",            { eAX, Iv }, 0 },
2708   { "stosB",            { Ybr, AL }, 0 },
2709   { "stosS",            { Yvr, eAX }, 0 },
2710   { "lodsB",            { ALr, Xb }, 0 },
2711   { "lodsS",            { eAXr, Xv }, 0 },
2712   { "scasB",            { AL, Yb }, 0 },
2713   { "scasS",            { eAX, Yv }, 0 },
2714   /* b0 */
2715   { "movB",             { RMAL, Ib }, 0 },
2716   { "movB",             { RMCL, Ib }, 0 },
2717   { "movB",             { RMDL, Ib }, 0 },
2718   { "movB",             { RMBL, Ib }, 0 },
2719   { "movB",             { RMAH, Ib }, 0 },
2720   { "movB",             { RMCH, Ib }, 0 },
2721   { "movB",             { RMDH, Ib }, 0 },
2722   { "movB",             { RMBH, Ib }, 0 },
2723   /* b8 */
2724   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2725   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2726   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2727   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2728   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2729   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2730   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2731   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2732   /* c0 */
2733   { REG_TABLE (REG_C0) },
2734   { REG_TABLE (REG_C1) },
2735   { "retT",             { Iw, BND }, 0 },
2736   { "retT",             { BND }, 0 },
2737   { X86_64_TABLE (X86_64_C4) },
2738   { X86_64_TABLE (X86_64_C5) },
2739   { REG_TABLE (REG_C6) },
2740   { REG_TABLE (REG_C7) },
2741   /* c8 */
2742   { "enterT",           { Iw, Ib }, 0 },
2743   { "leaveT",           { XX }, 0 },
2744   { "Jret{|f}P",        { Iw }, 0 },
2745   { "Jret{|f}P",        { XX }, 0 },
2746   { "int3",             { XX }, 0 },
2747   { "int",              { Ib }, 0 },
2748   { X86_64_TABLE (X86_64_CE) },
2749   { "iret%LP",          { XX }, 0 },
2750   /* d0 */
2751   { REG_TABLE (REG_D0) },
2752   { REG_TABLE (REG_D1) },
2753   { REG_TABLE (REG_D2) },
2754   { REG_TABLE (REG_D3) },
2755   { X86_64_TABLE (X86_64_D4) },
2756   { X86_64_TABLE (X86_64_D5) },
2757   { Bad_Opcode },
2758   { "xlat",             { DSBX }, 0 },
2759   /* d8 */
2760   { FLOAT },
2761   { FLOAT },
2762   { FLOAT },
2763   { FLOAT },
2764   { FLOAT },
2765   { FLOAT },
2766   { FLOAT },
2767   { FLOAT },
2768   /* e0 */
2769   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2770   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2771   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2772   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2773   { "inB",              { AL, Ib }, 0 },
2774   { "inG",              { zAX, Ib }, 0 },
2775   { "outB",             { Ib, AL }, 0 },
2776   { "outG",             { Ib, zAX }, 0 },
2777   /* e8 */
2778   { X86_64_TABLE (X86_64_E8) },
2779   { X86_64_TABLE (X86_64_E9) },
2780   { X86_64_TABLE (X86_64_EA) },
2781   { "jmp",              { Jb, BND }, 0 },
2782   { "inB",              { AL, indirDX }, 0 },
2783   { "inG",              { zAX, indirDX }, 0 },
2784   { "outB",             { indirDX, AL }, 0 },
2785   { "outG",             { indirDX, zAX }, 0 },
2786   /* f0 */
2787   { Bad_Opcode },       /* lock prefix */
2788   { "icebp",            { XX }, 0 },
2789   { Bad_Opcode },       /* repne */
2790   { Bad_Opcode },       /* repz */
2791   { "hlt",              { XX }, 0 },
2792   { "cmc",              { XX }, 0 },
2793   { REG_TABLE (REG_F6) },
2794   { REG_TABLE (REG_F7) },
2795   /* f8 */
2796   { "clc",              { XX }, 0 },
2797   { "stc",              { XX }, 0 },
2798   { "cli",              { XX }, 0 },
2799   { "sti",              { XX }, 0 },
2800   { "cld",              { XX }, 0 },
2801   { "std",              { XX }, 0 },
2802   { REG_TABLE (REG_FE) },
2803   { REG_TABLE (REG_FF) },
2804 };
2805
2806 static const struct dis386 dis386_twobyte[] = {
2807   /* 00 */
2808   { REG_TABLE (REG_0F00 ) },
2809   { REG_TABLE (REG_0F01 ) },
2810   { "larS",             { Gv, Ew }, 0 },
2811   { "lslS",             { Gv, Ew }, 0 },
2812   { Bad_Opcode },
2813   { "syscall",          { XX }, 0 },
2814   { "clts",             { XX }, 0 },
2815   { "sysret%LP",                { XX }, 0 },
2816   /* 08 */
2817   { "invd",             { XX }, 0 },
2818   { "wbinvd",           { XX }, 0 },
2819   { Bad_Opcode },
2820   { "ud2",              { XX }, 0 },
2821   { Bad_Opcode },
2822   { REG_TABLE (REG_0F0D) },
2823   { "femms",            { XX }, 0 },
2824   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2825   /* 10 */
2826   { PREFIX_TABLE (PREFIX_0F10) },
2827   { PREFIX_TABLE (PREFIX_0F11) },
2828   { PREFIX_TABLE (PREFIX_0F12) },
2829   { MOD_TABLE (MOD_0F13) },
2830   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2831   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2832   { PREFIX_TABLE (PREFIX_0F16) },
2833   { MOD_TABLE (MOD_0F17) },
2834   /* 18 */
2835   { REG_TABLE (REG_0F18) },
2836   { "nopQ",             { Ev }, 0 },
2837   { PREFIX_TABLE (PREFIX_0F1A) },
2838   { PREFIX_TABLE (PREFIX_0F1B) },
2839   { "nopQ",             { Ev }, 0 },
2840   { "nopQ",             { Ev }, 0 },
2841   { "nopQ",             { Ev }, 0 },
2842   { "nopQ",             { Ev }, 0 },
2843   /* 20 */
2844   { "movZ",             { Rm, Cm }, 0 },
2845   { "movZ",             { Rm, Dm }, 0 },
2846   { "movZ",             { Cm, Rm }, 0 },
2847   { "movZ",             { Dm, Rm }, 0 },
2848   { MOD_TABLE (MOD_0F24) },
2849   { Bad_Opcode },
2850   { MOD_TABLE (MOD_0F26) },
2851   { Bad_Opcode },
2852   /* 28 */
2853   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2854   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2855   { PREFIX_TABLE (PREFIX_0F2A) },
2856   { PREFIX_TABLE (PREFIX_0F2B) },
2857   { PREFIX_TABLE (PREFIX_0F2C) },
2858   { PREFIX_TABLE (PREFIX_0F2D) },
2859   { PREFIX_TABLE (PREFIX_0F2E) },
2860   { PREFIX_TABLE (PREFIX_0F2F) },
2861   /* 30 */
2862   { "wrmsr",            { XX }, 0 },
2863   { "rdtsc",            { XX }, 0 },
2864   { "rdmsr",            { XX }, 0 },
2865   { "rdpmc",            { XX }, 0 },
2866   { "sysenter",         { XX }, 0 },
2867   { "sysexit",          { XX }, 0 },
2868   { Bad_Opcode },
2869   { "getsec",           { XX }, 0 },
2870   /* 38 */
2871   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2872   { Bad_Opcode },
2873   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2874   { Bad_Opcode },
2875   { Bad_Opcode },
2876   { Bad_Opcode },
2877   { Bad_Opcode },
2878   { Bad_Opcode },
2879   /* 40 */
2880   { "cmovoS",           { Gv, Ev }, 0 },
2881   { "cmovnoS",          { Gv, Ev }, 0 },
2882   { "cmovbS",           { Gv, Ev }, 0 },
2883   { "cmovaeS",          { Gv, Ev }, 0 },
2884   { "cmoveS",           { Gv, Ev }, 0 },
2885   { "cmovneS",          { Gv, Ev }, 0 },
2886   { "cmovbeS",          { Gv, Ev }, 0 },
2887   { "cmovaS",           { Gv, Ev }, 0 },
2888   /* 48 */
2889   { "cmovsS",           { Gv, Ev }, 0 },
2890   { "cmovnsS",          { Gv, Ev }, 0 },
2891   { "cmovpS",           { Gv, Ev }, 0 },
2892   { "cmovnpS",          { Gv, Ev }, 0 },
2893   { "cmovlS",           { Gv, Ev }, 0 },
2894   { "cmovgeS",          { Gv, Ev }, 0 },
2895   { "cmovleS",          { Gv, Ev }, 0 },
2896   { "cmovgS",           { Gv, Ev }, 0 },
2897   /* 50 */
2898   { MOD_TABLE (MOD_0F51) },
2899   { PREFIX_TABLE (PREFIX_0F51) },
2900   { PREFIX_TABLE (PREFIX_0F52) },
2901   { PREFIX_TABLE (PREFIX_0F53) },
2902   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2903   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2904   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2905   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2906   /* 58 */
2907   { PREFIX_TABLE (PREFIX_0F58) },
2908   { PREFIX_TABLE (PREFIX_0F59) },
2909   { PREFIX_TABLE (PREFIX_0F5A) },
2910   { PREFIX_TABLE (PREFIX_0F5B) },
2911   { PREFIX_TABLE (PREFIX_0F5C) },
2912   { PREFIX_TABLE (PREFIX_0F5D) },
2913   { PREFIX_TABLE (PREFIX_0F5E) },
2914   { PREFIX_TABLE (PREFIX_0F5F) },
2915   /* 60 */
2916   { PREFIX_TABLE (PREFIX_0F60) },
2917   { PREFIX_TABLE (PREFIX_0F61) },
2918   { PREFIX_TABLE (PREFIX_0F62) },
2919   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2920   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2921   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2922   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2923   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2924   /* 68 */
2925   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2926   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2927   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2928   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2929   { PREFIX_TABLE (PREFIX_0F6C) },
2930   { PREFIX_TABLE (PREFIX_0F6D) },
2931   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2932   { PREFIX_TABLE (PREFIX_0F6F) },
2933   /* 70 */
2934   { PREFIX_TABLE (PREFIX_0F70) },
2935   { REG_TABLE (REG_0F71) },
2936   { REG_TABLE (REG_0F72) },
2937   { REG_TABLE (REG_0F73) },
2938   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2939   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2940   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2941   { "emms",             { XX }, PREFIX_OPCODE },
2942   /* 78 */
2943   { PREFIX_TABLE (PREFIX_0F78) },
2944   { PREFIX_TABLE (PREFIX_0F79) },
2945   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2946   { Bad_Opcode },
2947   { PREFIX_TABLE (PREFIX_0F7C) },
2948   { PREFIX_TABLE (PREFIX_0F7D) },
2949   { PREFIX_TABLE (PREFIX_0F7E) },
2950   { PREFIX_TABLE (PREFIX_0F7F) },
2951   /* 80 */
2952   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2953   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2954   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2955   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2956   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2957   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2958   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2959   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2960   /* 88 */
2961   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2962   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2963   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2964   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2965   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2966   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2967   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2968   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2969   /* 90 */
2970   { "seto",             { Eb }, 0 },
2971   { "setno",            { Eb }, 0 },
2972   { "setb",             { Eb }, 0 },
2973   { "setae",            { Eb }, 0 },
2974   { "sete",             { Eb }, 0 },
2975   { "setne",            { Eb }, 0 },
2976   { "setbe",            { Eb }, 0 },
2977   { "seta",             { Eb }, 0 },
2978   /* 98 */
2979   { "sets",             { Eb }, 0 },
2980   { "setns",            { Eb }, 0 },
2981   { "setp",             { Eb }, 0 },
2982   { "setnp",            { Eb }, 0 },
2983   { "setl",             { Eb }, 0 },
2984   { "setge",            { Eb }, 0 },
2985   { "setle",            { Eb }, 0 },
2986   { "setg",             { Eb }, 0 },
2987   /* a0 */
2988   { "pushT",            { fs }, 0 },
2989   { "popT",             { fs }, 0 },
2990   { "cpuid",            { XX }, 0 },
2991   { "btS",              { Ev, Gv }, 0 },
2992   { "shldS",            { Ev, Gv, Ib }, 0 },
2993   { "shldS",            { Ev, Gv, CL }, 0 },
2994   { REG_TABLE (REG_0FA6) },
2995   { REG_TABLE (REG_0FA7) },
2996   /* a8 */
2997   { "pushT",            { gs }, 0 },
2998   { "popT",             { gs }, 0 },
2999   { "rsm",              { XX }, 0 },
3000   { "btsS",             { Evh1, Gv }, 0 },
3001   { "shrdS",            { Ev, Gv, Ib }, 0 },
3002   { "shrdS",            { Ev, Gv, CL }, 0 },
3003   { REG_TABLE (REG_0FAE) },
3004   { "imulS",            { Gv, Ev }, 0 },
3005   /* b0 */
3006   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3007   { "cmpxchgS",         { Evh1, Gv }, 0 },
3008   { MOD_TABLE (MOD_0FB2) },
3009   { "btrS",             { Evh1, Gv }, 0 },
3010   { MOD_TABLE (MOD_0FB4) },
3011   { MOD_TABLE (MOD_0FB5) },
3012   { "movz{bR|x}",       { Gv, Eb }, 0 },
3013   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3014   /* b8 */
3015   { PREFIX_TABLE (PREFIX_0FB8) },
3016   { "ud1",              { XX }, 0 },
3017   { REG_TABLE (REG_0FBA) },
3018   { "btcS",             { Evh1, Gv }, 0 },
3019   { PREFIX_TABLE (PREFIX_0FBC) },
3020   { PREFIX_TABLE (PREFIX_0FBD) },
3021   { "movs{bR|x}",       { Gv, Eb }, 0 },
3022   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3023   /* c0 */
3024   { "xaddB",            { Ebh1, Gb }, 0 },
3025   { "xaddS",            { Evh1, Gv }, 0 },
3026   { PREFIX_TABLE (PREFIX_0FC2) },
3027   { MOD_TABLE (MOD_0FC3) },
3028   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3029   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3030   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3031   { REG_TABLE (REG_0FC7) },
3032   /* c8 */
3033   { "bswap",            { RMeAX }, 0 },
3034   { "bswap",            { RMeCX }, 0 },
3035   { "bswap",            { RMeDX }, 0 },
3036   { "bswap",            { RMeBX }, 0 },
3037   { "bswap",            { RMeSP }, 0 },
3038   { "bswap",            { RMeBP }, 0 },
3039   { "bswap",            { RMeSI }, 0 },
3040   { "bswap",            { RMeDI }, 0 },
3041   /* d0 */
3042   { PREFIX_TABLE (PREFIX_0FD0) },
3043   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3044   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3045   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3046   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3047   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3048   { PREFIX_TABLE (PREFIX_0FD6) },
3049   { MOD_TABLE (MOD_0FD7) },
3050   /* d8 */
3051   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3052   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3053   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3054   { "pand",             { MX, EM }, PREFIX_OPCODE },
3055   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3056   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3057   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3058   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3059   /* e0 */
3060   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3061   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3062   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3063   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3064   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3065   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3066   { PREFIX_TABLE (PREFIX_0FE6) },
3067   { PREFIX_TABLE (PREFIX_0FE7) },
3068   /* e8 */
3069   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3070   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3071   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3072   { "por",              { MX, EM }, PREFIX_OPCODE },
3073   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3074   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3075   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3076   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3077   /* f0 */
3078   { PREFIX_TABLE (PREFIX_0FF0) },
3079   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3080   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3081   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3082   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3083   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3084   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3085   { PREFIX_TABLE (PREFIX_0FF7) },
3086   /* f8 */
3087   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3088   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3089   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3090   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3091   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3092   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3093   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3094   { Bad_Opcode },
3095 };
3096
3097 static const unsigned char onebyte_has_modrm[256] = {
3098   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3099   /*       -------------------------------        */
3100   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3101   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3102   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3103   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3104   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3105   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3106   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3107   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3108   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3109   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3110   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3111   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3112   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3113   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3114   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3115   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3116   /*       -------------------------------        */
3117   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3118 };
3119
3120 static const unsigned char twobyte_has_modrm[256] = {
3121   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3122   /*       -------------------------------        */
3123   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3124   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3125   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3126   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3127   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3128   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3129   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3130   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3131   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3132   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3133   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3134   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3135   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3136   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3137   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3138   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3139   /*       -------------------------------        */
3140   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3141 };
3142
3143 static char obuf[100];
3144 static char *obufp;
3145 static char *mnemonicendp;
3146 static char scratchbuf[100];
3147 static unsigned char *start_codep;
3148 static unsigned char *insn_codep;
3149 static unsigned char *codep;
3150 static unsigned char *end_codep;
3151 static int last_lock_prefix;
3152 static int last_repz_prefix;
3153 static int last_repnz_prefix;
3154 static int last_data_prefix;
3155 static int last_addr_prefix;
3156 static int last_rex_prefix;
3157 static int last_seg_prefix;
3158 static int fwait_prefix;
3159 /* The active segment register prefix.  */
3160 static int active_seg_prefix;
3161 #define MAX_CODE_LENGTH 15
3162 /* We can up to 14 prefixes since the maximum instruction length is
3163    15bytes.  */
3164 static int all_prefixes[MAX_CODE_LENGTH - 1];
3165 static disassemble_info *the_info;
3166 static struct
3167   {
3168     int mod;
3169     int reg;
3170     int rm;
3171   }
3172 modrm;
3173 static unsigned char need_modrm;
3174 static struct
3175   {
3176     int scale;
3177     int index;
3178     int base;
3179   }
3180 sib;
3181 static struct
3182   {
3183     int register_specifier;
3184     int length;
3185     int prefix;
3186     int w;
3187     int evex;
3188     int r;
3189     int v;
3190     int mask_register_specifier;
3191     int zeroing;
3192     int ll;
3193     int b;
3194   }
3195 vex;
3196 static unsigned char need_vex;
3197 static unsigned char need_vex_reg;
3198 static unsigned char vex_w_done;
3199
3200 struct op
3201   {
3202     const char *name;
3203     unsigned int len;
3204   };
3205
3206 /* If we are accessing mod/rm/reg without need_modrm set, then the
3207    values are stale.  Hitting this abort likely indicates that you
3208    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3209 #define MODRM_CHECK  if (!need_modrm) abort ()
3210
3211 static const char **names64;
3212 static const char **names32;
3213 static const char **names16;
3214 static const char **names8;
3215 static const char **names8rex;
3216 static const char **names_seg;
3217 static const char *index64;
3218 static const char *index32;
3219 static const char **index16;
3220 static const char **names_bnd;
3221
3222 static const char *intel_names64[] = {
3223   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3224   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3225 };
3226 static const char *intel_names32[] = {
3227   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3228   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3229 };
3230 static const char *intel_names16[] = {
3231   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3232   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3233 };
3234 static const char *intel_names8[] = {
3235   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3236 };
3237 static const char *intel_names8rex[] = {
3238   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3239   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3240 };
3241 static const char *intel_names_seg[] = {
3242   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3243 };
3244 static const char *intel_index64 = "riz";
3245 static const char *intel_index32 = "eiz";
3246 static const char *intel_index16[] = {
3247   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3248 };
3249
3250 static const char *att_names64[] = {
3251   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3252   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3253 };
3254 static const char *att_names32[] = {
3255   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3256   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3257 };
3258 static const char *att_names16[] = {
3259   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3260   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3261 };
3262 static const char *att_names8[] = {
3263   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3264 };
3265 static const char *att_names8rex[] = {
3266   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3267   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3268 };
3269 static const char *att_names_seg[] = {
3270   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3271 };
3272 static const char *att_index64 = "%riz";
3273 static const char *att_index32 = "%eiz";
3274 static const char *att_index16[] = {
3275   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3276 };
3277
3278 static const char **names_mm;
3279 static const char *intel_names_mm[] = {
3280   "mm0", "mm1", "mm2", "mm3",
3281   "mm4", "mm5", "mm6", "mm7"
3282 };
3283 static const char *att_names_mm[] = {
3284   "%mm0", "%mm1", "%mm2", "%mm3",
3285   "%mm4", "%mm5", "%mm6", "%mm7"
3286 };
3287
3288 static const char *intel_names_bnd[] = {
3289   "bnd0", "bnd1", "bnd2", "bnd3"
3290 };
3291
3292 static const char *att_names_bnd[] = {
3293   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3294 };
3295
3296 static const char **names_xmm;
3297 static const char *intel_names_xmm[] = {
3298   "xmm0", "xmm1", "xmm2", "xmm3",
3299   "xmm4", "xmm5", "xmm6", "xmm7",
3300   "xmm8", "xmm9", "xmm10", "xmm11",
3301   "xmm12", "xmm13", "xmm14", "xmm15",
3302   "xmm16", "xmm17", "xmm18", "xmm19",
3303   "xmm20", "xmm21", "xmm22", "xmm23",
3304   "xmm24", "xmm25", "xmm26", "xmm27",
3305   "xmm28", "xmm29", "xmm30", "xmm31"
3306 };
3307 static const char *att_names_xmm[] = {
3308   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3309   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3310   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3311   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3312   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3313   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3314   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3315   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3316 };
3317
3318 static const char **names_ymm;
3319 static const char *intel_names_ymm[] = {
3320   "ymm0", "ymm1", "ymm2", "ymm3",
3321   "ymm4", "ymm5", "ymm6", "ymm7",
3322   "ymm8", "ymm9", "ymm10", "ymm11",
3323   "ymm12", "ymm13", "ymm14", "ymm15",
3324   "ymm16", "ymm17", "ymm18", "ymm19",
3325   "ymm20", "ymm21", "ymm22", "ymm23",
3326   "ymm24", "ymm25", "ymm26", "ymm27",
3327   "ymm28", "ymm29", "ymm30", "ymm31"
3328 };
3329 static const char *att_names_ymm[] = {
3330   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3331   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3332   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3333   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3334   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3335   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3336   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3337   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3338 };
3339
3340 static const char **names_zmm;
3341 static const char *intel_names_zmm[] = {
3342   "zmm0", "zmm1", "zmm2", "zmm3",
3343   "zmm4", "zmm5", "zmm6", "zmm7",
3344   "zmm8", "zmm9", "zmm10", "zmm11",
3345   "zmm12", "zmm13", "zmm14", "zmm15",
3346   "zmm16", "zmm17", "zmm18", "zmm19",
3347   "zmm20", "zmm21", "zmm22", "zmm23",
3348   "zmm24", "zmm25", "zmm26", "zmm27",
3349   "zmm28", "zmm29", "zmm30", "zmm31"
3350 };
3351 static const char *att_names_zmm[] = {
3352   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3353   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3354   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3355   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3356   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3357   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3358   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3359   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3360 };
3361
3362 static const char **names_mask;
3363 static const char *intel_names_mask[] = {
3364   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3365 };
3366 static const char *att_names_mask[] = {
3367   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3368 };
3369
3370 static const char *names_rounding[] =
3371 {
3372   "{rn-sae}",
3373   "{rd-sae}",
3374   "{ru-sae}",
3375   "{rz-sae}"
3376 };
3377
3378 static const struct dis386 reg_table[][8] = {
3379   /* REG_80 */
3380   {
3381     { "addA",   { Ebh1, Ib }, 0 },
3382     { "orA",    { Ebh1, Ib }, 0 },
3383     { "adcA",   { Ebh1, Ib }, 0 },
3384     { "sbbA",   { Ebh1, Ib }, 0 },
3385     { "andA",   { Ebh1, Ib }, 0 },
3386     { "subA",   { Ebh1, Ib }, 0 },
3387     { "xorA",   { Ebh1, Ib }, 0 },
3388     { "cmpA",   { Eb, Ib }, 0 },
3389   },
3390   /* REG_81 */
3391   {
3392     { "addQ",   { Evh1, Iv }, 0 },
3393     { "orQ",    { Evh1, Iv }, 0 },
3394     { "adcQ",   { Evh1, Iv }, 0 },
3395     { "sbbQ",   { Evh1, Iv }, 0 },
3396     { "andQ",   { Evh1, Iv }, 0 },
3397     { "subQ",   { Evh1, Iv }, 0 },
3398     { "xorQ",   { Evh1, Iv }, 0 },
3399     { "cmpQ",   { Ev, Iv }, 0 },
3400   },
3401   /* REG_82 */
3402   {
3403     { "addQ",   { Evh1, sIb }, 0 },
3404     { "orQ",    { Evh1, sIb }, 0 },
3405     { "adcQ",   { Evh1, sIb }, 0 },
3406     { "sbbQ",   { Evh1, sIb }, 0 },
3407     { "andQ",   { Evh1, sIb }, 0 },
3408     { "subQ",   { Evh1, sIb }, 0 },
3409     { "xorQ",   { Evh1, sIb }, 0 },
3410     { "cmpQ",   { Ev, sIb }, 0 },
3411   },
3412   /* REG_8F */
3413   {
3414     { "popU",   { stackEv }, 0 },
3415     { XOP_8F_TABLE (XOP_09) },
3416     { Bad_Opcode },
3417     { Bad_Opcode },
3418     { Bad_Opcode },
3419     { XOP_8F_TABLE (XOP_09) },
3420   },
3421   /* REG_C0 */
3422   {
3423     { "rolA",   { Eb, Ib }, 0 },
3424     { "rorA",   { Eb, Ib }, 0 },
3425     { "rclA",   { Eb, Ib }, 0 },
3426     { "rcrA",   { Eb, Ib }, 0 },
3427     { "shlA",   { Eb, Ib }, 0 },
3428     { "shrA",   { Eb, Ib }, 0 },
3429     { Bad_Opcode },
3430     { "sarA",   { Eb, Ib }, 0 },
3431   },
3432   /* REG_C1 */
3433   {
3434     { "rolQ",   { Ev, Ib }, 0 },
3435     { "rorQ",   { Ev, Ib }, 0 },
3436     { "rclQ",   { Ev, Ib }, 0 },
3437     { "rcrQ",   { Ev, Ib }, 0 },
3438     { "shlQ",   { Ev, Ib }, 0 },
3439     { "shrQ",   { Ev, Ib }, 0 },
3440     { Bad_Opcode },
3441     { "sarQ",   { Ev, Ib }, 0 },
3442   },
3443   /* REG_C6 */
3444   {
3445     { "movA",   { Ebh3, Ib }, 0 },
3446     { Bad_Opcode },
3447     { Bad_Opcode },
3448     { Bad_Opcode },
3449     { Bad_Opcode },
3450     { Bad_Opcode },
3451     { Bad_Opcode },
3452     { MOD_TABLE (MOD_C6_REG_7) },
3453   },
3454   /* REG_C7 */
3455   {
3456     { "movQ",   { Evh3, Iv }, 0 },
3457     { Bad_Opcode },
3458     { Bad_Opcode },
3459     { Bad_Opcode },
3460     { Bad_Opcode },
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { MOD_TABLE (MOD_C7_REG_7) },
3464   },
3465   /* REG_D0 */
3466   {
3467     { "rolA",   { Eb, I1 }, 0 },
3468     { "rorA",   { Eb, I1 }, 0 },
3469     { "rclA",   { Eb, I1 }, 0 },
3470     { "rcrA",   { Eb, I1 }, 0 },
3471     { "shlA",   { Eb, I1 }, 0 },
3472     { "shrA",   { Eb, I1 }, 0 },
3473     { Bad_Opcode },
3474     { "sarA",   { Eb, I1 }, 0 },
3475   },
3476   /* REG_D1 */
3477   {
3478     { "rolQ",   { Ev, I1 }, 0 },
3479     { "rorQ",   { Ev, I1 }, 0 },
3480     { "rclQ",   { Ev, I1 }, 0 },
3481     { "rcrQ",   { Ev, I1 }, 0 },
3482     { "shlQ",   { Ev, I1 }, 0 },
3483     { "shrQ",   { Ev, I1 }, 0 },
3484     { Bad_Opcode },
3485     { "sarQ",   { Ev, I1 }, 0 },
3486   },
3487   /* REG_D2 */
3488   {
3489     { "rolA",   { Eb, CL }, 0 },
3490     { "rorA",   { Eb, CL }, 0 },
3491     { "rclA",   { Eb, CL }, 0 },
3492     { "rcrA",   { Eb, CL }, 0 },
3493     { "shlA",   { Eb, CL }, 0 },
3494     { "shrA",   { Eb, CL }, 0 },
3495     { Bad_Opcode },
3496     { "sarA",   { Eb, CL }, 0 },
3497   },
3498   /* REG_D3 */
3499   {
3500     { "rolQ",   { Ev, CL }, 0 },
3501     { "rorQ",   { Ev, CL }, 0 },
3502     { "rclQ",   { Ev, CL }, 0 },
3503     { "rcrQ",   { Ev, CL }, 0 },
3504     { "shlQ",   { Ev, CL }, 0 },
3505     { "shrQ",   { Ev, CL }, 0 },
3506     { Bad_Opcode },
3507     { "sarQ",   { Ev, CL }, 0 },
3508   },
3509   /* REG_F6 */
3510   {
3511     { "testA",  { Eb, Ib }, 0 },
3512     { Bad_Opcode },
3513     { "notA",   { Ebh1 }, 0 },
3514     { "negA",   { Ebh1 }, 0 },
3515     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3516     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3517     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3518     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3519   },
3520   /* REG_F7 */
3521   {
3522     { "testQ",  { Ev, Iv }, 0 },
3523     { Bad_Opcode },
3524     { "notQ",   { Evh1 }, 0 },
3525     { "negQ",   { Evh1 }, 0 },
3526     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3527     { "imulQ",  { Ev }, 0 },
3528     { "divQ",   { Ev }, 0 },
3529     { "idivQ",  { Ev }, 0 },
3530   },
3531   /* REG_FE */
3532   {
3533     { "incA",   { Ebh1 }, 0 },
3534     { "decA",   { Ebh1 }, 0 },
3535   },
3536   /* REG_FF */
3537   {
3538     { "incQ",   { Evh1 }, 0 },
3539     { "decQ",   { Evh1 }, 0 },
3540     { "call{&|}", { indirEv, BND }, 0 },
3541     { MOD_TABLE (MOD_FF_REG_3) },
3542     { "jmp{&|}", { indirEv, BND }, 0 },
3543     { MOD_TABLE (MOD_FF_REG_5) },
3544     { "pushU",  { stackEv }, 0 },
3545     { Bad_Opcode },
3546   },
3547   /* REG_0F00 */
3548   {
3549     { "sldtD",  { Sv }, 0 },
3550     { "strD",   { Sv }, 0 },
3551     { "lldt",   { Ew }, 0 },
3552     { "ltr",    { Ew }, 0 },
3553     { "verr",   { Ew }, 0 },
3554     { "verw",   { Ew }, 0 },
3555     { Bad_Opcode },
3556     { Bad_Opcode },
3557   },
3558   /* REG_0F01 */
3559   {
3560     { MOD_TABLE (MOD_0F01_REG_0) },
3561     { MOD_TABLE (MOD_0F01_REG_1) },
3562     { MOD_TABLE (MOD_0F01_REG_2) },
3563     { MOD_TABLE (MOD_0F01_REG_3) },
3564     { "smswD",  { Sv }, 0 },
3565     { MOD_TABLE (MOD_0F01_REG_5) },
3566     { "lmsw",   { Ew }, 0 },
3567     { MOD_TABLE (MOD_0F01_REG_7) },
3568   },
3569   /* REG_0F0D */
3570   {
3571     { "prefetch",       { Mb }, 0 },
3572     { "prefetchw",      { Mb }, 0 },
3573     { "prefetchwt1",    { Mb }, 0 },
3574     { "prefetch",       { Mb }, 0 },
3575     { "prefetch",       { Mb }, 0 },
3576     { "prefetch",       { Mb }, 0 },
3577     { "prefetch",       { Mb }, 0 },
3578     { "prefetch",       { Mb }, 0 },
3579   },
3580   /* REG_0F18 */
3581   {
3582     { MOD_TABLE (MOD_0F18_REG_0) },
3583     { MOD_TABLE (MOD_0F18_REG_1) },
3584     { MOD_TABLE (MOD_0F18_REG_2) },
3585     { MOD_TABLE (MOD_0F18_REG_3) },
3586     { MOD_TABLE (MOD_0F18_REG_4) },
3587     { MOD_TABLE (MOD_0F18_REG_5) },
3588     { MOD_TABLE (MOD_0F18_REG_6) },
3589     { MOD_TABLE (MOD_0F18_REG_7) },
3590   },
3591   /* REG_0F71 */
3592   {
3593     { Bad_Opcode },
3594     { Bad_Opcode },
3595     { MOD_TABLE (MOD_0F71_REG_2) },
3596     { Bad_Opcode },
3597     { MOD_TABLE (MOD_0F71_REG_4) },
3598     { Bad_Opcode },
3599     { MOD_TABLE (MOD_0F71_REG_6) },
3600   },
3601   /* REG_0F72 */
3602   {
3603     { Bad_Opcode },
3604     { Bad_Opcode },
3605     { MOD_TABLE (MOD_0F72_REG_2) },
3606     { Bad_Opcode },
3607     { MOD_TABLE (MOD_0F72_REG_4) },
3608     { Bad_Opcode },
3609     { MOD_TABLE (MOD_0F72_REG_6) },
3610   },
3611   /* REG_0F73 */
3612   {
3613     { Bad_Opcode },
3614     { Bad_Opcode },
3615     { MOD_TABLE (MOD_0F73_REG_2) },
3616     { MOD_TABLE (MOD_0F73_REG_3) },
3617     { Bad_Opcode },
3618     { Bad_Opcode },
3619     { MOD_TABLE (MOD_0F73_REG_6) },
3620     { MOD_TABLE (MOD_0F73_REG_7) },
3621   },
3622   /* REG_0FA6 */
3623   {
3624     { "montmul",        { { OP_0f07, 0 } }, 0 },
3625     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3626     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3627   },
3628   /* REG_0FA7 */
3629   {
3630     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3631     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3632     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3633     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3634     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3635     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3636   },
3637   /* REG_0FAE */
3638   {
3639     { MOD_TABLE (MOD_0FAE_REG_0) },
3640     { MOD_TABLE (MOD_0FAE_REG_1) },
3641     { MOD_TABLE (MOD_0FAE_REG_2) },
3642     { MOD_TABLE (MOD_0FAE_REG_3) },
3643     { MOD_TABLE (MOD_0FAE_REG_4) },
3644     { MOD_TABLE (MOD_0FAE_REG_5) },
3645     { MOD_TABLE (MOD_0FAE_REG_6) },
3646     { MOD_TABLE (MOD_0FAE_REG_7) },
3647   },
3648   /* REG_0FBA */
3649   {
3650     { Bad_Opcode },
3651     { Bad_Opcode },
3652     { Bad_Opcode },
3653     { Bad_Opcode },
3654     { "btQ",    { Ev, Ib }, 0 },
3655     { "btsQ",   { Evh1, Ib }, 0 },
3656     { "btrQ",   { Evh1, Ib }, 0 },
3657     { "btcQ",   { Evh1, Ib }, 0 },
3658   },
3659   /* REG_0FC7 */
3660   {
3661     { Bad_Opcode },
3662     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3663     { Bad_Opcode },
3664     { MOD_TABLE (MOD_0FC7_REG_3) },
3665     { MOD_TABLE (MOD_0FC7_REG_4) },
3666     { MOD_TABLE (MOD_0FC7_REG_5) },
3667     { MOD_TABLE (MOD_0FC7_REG_6) },
3668     { MOD_TABLE (MOD_0FC7_REG_7) },
3669   },
3670   /* REG_VEX_0F71 */
3671   {
3672     { Bad_Opcode },
3673     { Bad_Opcode },
3674     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3675     { Bad_Opcode },
3676     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3677     { Bad_Opcode },
3678     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3679   },
3680   /* REG_VEX_0F72 */
3681   {
3682     { Bad_Opcode },
3683     { Bad_Opcode },
3684     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3685     { Bad_Opcode },
3686     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3687     { Bad_Opcode },
3688     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3689   },
3690   /* REG_VEX_0F73 */
3691   {
3692     { Bad_Opcode },
3693     { Bad_Opcode },
3694     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3695     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3696     { Bad_Opcode },
3697     { Bad_Opcode },
3698     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3699     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3700   },
3701   /* REG_VEX_0FAE */
3702   {
3703     { Bad_Opcode },
3704     { Bad_Opcode },
3705     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3706     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3707   },
3708   /* REG_VEX_0F38F3 */
3709   {
3710     { Bad_Opcode },
3711     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3712     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3713     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3714   },
3715   /* REG_XOP_LWPCB */
3716   {
3717     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3718     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3719   },
3720   /* REG_XOP_LWP */
3721   {
3722     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3723     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3724   },
3725   /* REG_XOP_TBM_01 */
3726   {
3727     { Bad_Opcode },
3728     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3729     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3730     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3731     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3732     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3733     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3734     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3735   },
3736   /* REG_XOP_TBM_02 */
3737   {
3738     { Bad_Opcode },
3739     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3740     { Bad_Opcode },
3741     { Bad_Opcode },
3742     { Bad_Opcode },
3743     { Bad_Opcode },
3744     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3745   },
3746 #define NEED_REG_TABLE
3747 #include "i386-dis-evex.h"
3748 #undef NEED_REG_TABLE
3749 };
3750
3751 static const struct dis386 prefix_table[][4] = {
3752   /* PREFIX_90 */
3753   {
3754     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3755     { "pause", { XX }, 0 },
3756     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3757     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3758   },
3759
3760   /* PREFIX_0F10 */
3761   {
3762     { "movups", { XM, EXx }, PREFIX_OPCODE },
3763     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3764     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3765     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3766   },
3767
3768   /* PREFIX_0F11 */
3769   {
3770     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3771     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3772     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3773     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3774   },
3775
3776   /* PREFIX_0F12 */
3777   {
3778     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3779     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3780     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3781     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3782   },
3783
3784   /* PREFIX_0F16 */
3785   {
3786     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3787     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3788     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3789   },
3790
3791   /* PREFIX_0F1A */
3792   {
3793     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3794     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3795     { "bndmov", { Gbnd, Ebnd }, 0 },
3796     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3797   },
3798
3799   /* PREFIX_0F1B */
3800   {
3801     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3802     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3803     { "bndmov", { Ebnd, Gbnd }, 0 },
3804     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3805   },
3806
3807   /* PREFIX_0F2A */
3808   {
3809     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3810     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3811     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3812     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3813   },
3814
3815   /* PREFIX_0F2B */
3816   {
3817     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3818     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3819     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3820     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3821   },
3822
3823   /* PREFIX_0F2C */
3824   {
3825     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3826     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3827     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3828     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3829   },
3830
3831   /* PREFIX_0F2D */
3832   {
3833     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3834     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3835     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3836     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3837   },
3838
3839   /* PREFIX_0F2E */
3840   {
3841     { "ucomiss",{ XM, EXd }, 0 },
3842     { Bad_Opcode },
3843     { "ucomisd",{ XM, EXq }, 0 },
3844   },
3845
3846   /* PREFIX_0F2F */
3847   {
3848     { "comiss", { XM, EXd }, 0 },
3849     { Bad_Opcode },
3850     { "comisd", { XM, EXq }, 0 },
3851   },
3852
3853   /* PREFIX_0F51 */
3854   {
3855     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3856     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3857     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3858     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3859   },
3860
3861   /* PREFIX_0F52 */
3862   {
3863     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3864     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3865   },
3866
3867   /* PREFIX_0F53 */
3868   {
3869     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3870     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3871   },
3872
3873   /* PREFIX_0F58 */
3874   {
3875     { "addps", { XM, EXx }, PREFIX_OPCODE },
3876     { "addss", { XM, EXd }, PREFIX_OPCODE },
3877     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3878     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3879   },
3880
3881   /* PREFIX_0F59 */
3882   {
3883     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3884     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3885     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3886     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3887   },
3888
3889   /* PREFIX_0F5A */
3890   {
3891     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3892     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3893     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3894     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3895   },
3896
3897   /* PREFIX_0F5B */
3898   {
3899     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3900     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3901     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3902   },
3903
3904   /* PREFIX_0F5C */
3905   {
3906     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3907     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3908     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3909     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3910   },
3911
3912   /* PREFIX_0F5D */
3913   {
3914     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3915     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3916     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3917     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3918   },
3919
3920   /* PREFIX_0F5E */
3921   {
3922     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3923     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3924     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3925     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3926   },
3927
3928   /* PREFIX_0F5F */
3929   {
3930     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3931     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3932     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3933     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3934   },
3935
3936   /* PREFIX_0F60 */
3937   {
3938     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3939     { Bad_Opcode },
3940     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3941   },
3942
3943   /* PREFIX_0F61 */
3944   {
3945     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3946     { Bad_Opcode },
3947     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3948   },
3949
3950   /* PREFIX_0F62 */
3951   {
3952     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3953     { Bad_Opcode },
3954     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3955   },
3956
3957   /* PREFIX_0F6C */
3958   {
3959     { Bad_Opcode },
3960     { Bad_Opcode },
3961     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3962   },
3963
3964   /* PREFIX_0F6D */
3965   {
3966     { Bad_Opcode },
3967     { Bad_Opcode },
3968     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3969   },
3970
3971   /* PREFIX_0F6F */
3972   {
3973     { "movq",   { MX, EM }, PREFIX_OPCODE },
3974     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3975     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3976   },
3977
3978   /* PREFIX_0F70 */
3979   {
3980     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3981     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3982     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3983     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3984   },
3985
3986   /* PREFIX_0F73_REG_3 */
3987   {
3988     { Bad_Opcode },
3989     { Bad_Opcode },
3990     { "psrldq", { XS, Ib }, 0 },
3991   },
3992
3993   /* PREFIX_0F73_REG_7 */
3994   {
3995     { Bad_Opcode },
3996     { Bad_Opcode },
3997     { "pslldq", { XS, Ib }, 0 },
3998   },
3999
4000   /* PREFIX_0F78 */
4001   {
4002     {"vmread",  { Em, Gm }, 0 },
4003     { Bad_Opcode },
4004     {"extrq",   { XS, Ib, Ib }, 0 },
4005     {"insertq", { XM, XS, Ib, Ib }, 0 },
4006   },
4007
4008   /* PREFIX_0F79 */
4009   {
4010     {"vmwrite", { Gm, Em }, 0 },
4011     { Bad_Opcode },
4012     {"extrq",   { XM, XS }, 0 },
4013     {"insertq", { XM, XS }, 0 },
4014   },
4015
4016   /* PREFIX_0F7C */
4017   {
4018     { Bad_Opcode },
4019     { Bad_Opcode },
4020     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4021     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4022   },
4023
4024   /* PREFIX_0F7D */
4025   {
4026     { Bad_Opcode },
4027     { Bad_Opcode },
4028     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4029     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4030   },
4031
4032   /* PREFIX_0F7E */
4033   {
4034     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4035     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4036     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4037   },
4038
4039   /* PREFIX_0F7F */
4040   {
4041     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4042     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4043     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4044   },
4045
4046   /* PREFIX_0FAE_REG_0 */
4047   {
4048     { Bad_Opcode },
4049     { "rdfsbase", { Ev }, 0 },
4050   },
4051
4052   /* PREFIX_0FAE_REG_1 */
4053   {
4054     { Bad_Opcode },
4055     { "rdgsbase", { Ev }, 0 },
4056   },
4057
4058   /* PREFIX_0FAE_REG_2 */
4059   {
4060     { Bad_Opcode },
4061     { "wrfsbase", { Ev }, 0 },
4062   },
4063
4064   /* PREFIX_0FAE_REG_3 */
4065   {
4066     { Bad_Opcode },
4067     { "wrgsbase", { Ev }, 0 },
4068   },
4069
4070   /* PREFIX_MOD_0_0FAE_REG_4 */
4071   {
4072     { "xsave",  { FXSAVE }, 0 },
4073     { "ptwrite%LQ", { Edq }, 0 },
4074   },
4075
4076   /* PREFIX_MOD_3_0FAE_REG_4 */
4077   {
4078     { Bad_Opcode },
4079     { "ptwrite%LQ", { Edq }, 0 },
4080   },
4081
4082   /* PREFIX_0FAE_REG_6 */
4083   {
4084     { "xsaveopt",      { FXSAVE }, 0 },
4085     { Bad_Opcode },
4086     { "clwb",   { Mb }, 0 },
4087   },
4088
4089   /* PREFIX_0FAE_REG_7 */
4090   {
4091     { "clflush",        { Mb }, 0 },
4092     { Bad_Opcode },
4093     { "clflushopt",     { Mb }, 0 },
4094   },
4095
4096   /* PREFIX_0FB8 */
4097   {
4098     { Bad_Opcode },
4099     { "popcntS", { Gv, Ev }, 0 },
4100   },
4101
4102   /* PREFIX_0FBC */
4103   {
4104     { "bsfS",   { Gv, Ev }, 0 },
4105     { "tzcntS", { Gv, Ev }, 0 },
4106     { "bsfS",   { Gv, Ev }, 0 },
4107   },
4108
4109   /* PREFIX_0FBD */
4110   {
4111     { "bsrS",   { Gv, Ev }, 0 },
4112     { "lzcntS", { Gv, Ev }, 0 },
4113     { "bsrS",   { Gv, Ev }, 0 },
4114   },
4115
4116   /* PREFIX_0FC2 */
4117   {
4118     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4119     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4120     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4121     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4122   },
4123
4124   /* PREFIX_MOD_0_0FC3 */
4125   {
4126     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4127   },
4128
4129   /* PREFIX_MOD_0_0FC7_REG_6 */
4130   {
4131     { "vmptrld",{ Mq }, 0 },
4132     { "vmxon",  { Mq }, 0 },
4133     { "vmclear",{ Mq }, 0 },
4134   },
4135
4136   /* PREFIX_MOD_3_0FC7_REG_6 */
4137   {
4138     { "rdrand", { Ev }, 0 },
4139     { Bad_Opcode },
4140     { "rdrand", { Ev }, 0 }
4141   },
4142
4143   /* PREFIX_MOD_3_0FC7_REG_7 */
4144   {
4145     { "rdseed", { Ev }, 0 },
4146     { "rdpid",  { Em }, 0 },
4147     { "rdseed", { Ev }, 0 },
4148   },
4149
4150   /* PREFIX_0FD0 */
4151   {
4152     { Bad_Opcode },
4153     { Bad_Opcode },
4154     { "addsubpd", { XM, EXx }, 0 },
4155     { "addsubps", { XM, EXx }, 0 },
4156   },
4157
4158   /* PREFIX_0FD6 */
4159   {
4160     { Bad_Opcode },
4161     { "movq2dq",{ XM, MS }, 0 },
4162     { "movq",   { EXqS, XM }, 0 },
4163     { "movdq2q",{ MX, XS }, 0 },
4164   },
4165
4166   /* PREFIX_0FE6 */
4167   {
4168     { Bad_Opcode },
4169     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4170     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4171     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4172   },
4173
4174   /* PREFIX_0FE7 */
4175   {
4176     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4177     { Bad_Opcode },
4178     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4179   },
4180
4181   /* PREFIX_0FF0 */
4182   {
4183     { Bad_Opcode },
4184     { Bad_Opcode },
4185     { Bad_Opcode },
4186     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4187   },
4188
4189   /* PREFIX_0FF7 */
4190   {
4191     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4192     { Bad_Opcode },
4193     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4194   },
4195
4196   /* PREFIX_0F3810 */
4197   {
4198     { Bad_Opcode },
4199     { Bad_Opcode },
4200     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4201   },
4202
4203   /* PREFIX_0F3814 */
4204   {
4205     { Bad_Opcode },
4206     { Bad_Opcode },
4207     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4208   },
4209
4210   /* PREFIX_0F3815 */
4211   {
4212     { Bad_Opcode },
4213     { Bad_Opcode },
4214     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4215   },
4216
4217   /* PREFIX_0F3817 */
4218   {
4219     { Bad_Opcode },
4220     { Bad_Opcode },
4221     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4222   },
4223
4224   /* PREFIX_0F3820 */
4225   {
4226     { Bad_Opcode },
4227     { Bad_Opcode },
4228     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4229   },
4230
4231   /* PREFIX_0F3821 */
4232   {
4233     { Bad_Opcode },
4234     { Bad_Opcode },
4235     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4236   },
4237
4238   /* PREFIX_0F3822 */
4239   {
4240     { Bad_Opcode },
4241     { Bad_Opcode },
4242     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4243   },
4244
4245   /* PREFIX_0F3823 */
4246   {
4247     { Bad_Opcode },
4248     { Bad_Opcode },
4249     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4250   },
4251
4252   /* PREFIX_0F3824 */
4253   {
4254     { Bad_Opcode },
4255     { Bad_Opcode },
4256     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4257   },
4258
4259   /* PREFIX_0F3825 */
4260   {
4261     { Bad_Opcode },
4262     { Bad_Opcode },
4263     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4264   },
4265
4266   /* PREFIX_0F3828 */
4267   {
4268     { Bad_Opcode },
4269     { Bad_Opcode },
4270     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4271   },
4272
4273   /* PREFIX_0F3829 */
4274   {
4275     { Bad_Opcode },
4276     { Bad_Opcode },
4277     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4278   },
4279
4280   /* PREFIX_0F382A */
4281   {
4282     { Bad_Opcode },
4283     { Bad_Opcode },
4284     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4285   },
4286
4287   /* PREFIX_0F382B */
4288   {
4289     { Bad_Opcode },
4290     { Bad_Opcode },
4291     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4292   },
4293
4294   /* PREFIX_0F3830 */
4295   {
4296     { Bad_Opcode },
4297     { Bad_Opcode },
4298     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4299   },
4300
4301   /* PREFIX_0F3831 */
4302   {
4303     { Bad_Opcode },
4304     { Bad_Opcode },
4305     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4306   },
4307
4308   /* PREFIX_0F3832 */
4309   {
4310     { Bad_Opcode },
4311     { Bad_Opcode },
4312     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4313   },
4314
4315   /* PREFIX_0F3833 */
4316   {
4317     { Bad_Opcode },
4318     { Bad_Opcode },
4319     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4320   },
4321
4322   /* PREFIX_0F3834 */
4323   {
4324     { Bad_Opcode },
4325     { Bad_Opcode },
4326     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4327   },
4328
4329   /* PREFIX_0F3835 */
4330   {
4331     { Bad_Opcode },
4332     { Bad_Opcode },
4333     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4334   },
4335
4336   /* PREFIX_0F3837 */
4337   {
4338     { Bad_Opcode },
4339     { Bad_Opcode },
4340     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4341   },
4342
4343   /* PREFIX_0F3838 */
4344   {
4345     { Bad_Opcode },
4346     { Bad_Opcode },
4347     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4348   },
4349
4350   /* PREFIX_0F3839 */
4351   {
4352     { Bad_Opcode },
4353     { Bad_Opcode },
4354     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4355   },
4356
4357   /* PREFIX_0F383A */
4358   {
4359     { Bad_Opcode },
4360     { Bad_Opcode },
4361     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4362   },
4363
4364   /* PREFIX_0F383B */
4365   {
4366     { Bad_Opcode },
4367     { Bad_Opcode },
4368     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4369   },
4370
4371   /* PREFIX_0F383C */
4372   {
4373     { Bad_Opcode },
4374     { Bad_Opcode },
4375     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4376   },
4377
4378   /* PREFIX_0F383D */
4379   {
4380     { Bad_Opcode },
4381     { Bad_Opcode },
4382     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4383   },
4384
4385   /* PREFIX_0F383E */
4386   {
4387     { Bad_Opcode },
4388     { Bad_Opcode },
4389     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4390   },
4391
4392   /* PREFIX_0F383F */
4393   {
4394     { Bad_Opcode },
4395     { Bad_Opcode },
4396     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4397   },
4398
4399   /* PREFIX_0F3840 */
4400   {
4401     { Bad_Opcode },
4402     { Bad_Opcode },
4403     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4404   },
4405
4406   /* PREFIX_0F3841 */
4407   {
4408     { Bad_Opcode },
4409     { Bad_Opcode },
4410     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4411   },
4412
4413   /* PREFIX_0F3880 */
4414   {
4415     { Bad_Opcode },
4416     { Bad_Opcode },
4417     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4418   },
4419
4420   /* PREFIX_0F3881 */
4421   {
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4425   },
4426
4427   /* PREFIX_0F3882 */
4428   {
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4432   },
4433
4434   /* PREFIX_0F38C8 */
4435   {
4436     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4437   },
4438
4439   /* PREFIX_0F38C9 */
4440   {
4441     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4442   },
4443
4444   /* PREFIX_0F38CA */
4445   {
4446     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4447   },
4448
4449   /* PREFIX_0F38CB */
4450   {
4451     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4452   },
4453
4454   /* PREFIX_0F38CC */
4455   {
4456     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4457   },
4458
4459   /* PREFIX_0F38CD */
4460   {
4461     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4462   },
4463
4464   /* PREFIX_0F38DB */
4465   {
4466     { Bad_Opcode },
4467     { Bad_Opcode },
4468     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4469   },
4470
4471   /* PREFIX_0F38DC */
4472   {
4473     { Bad_Opcode },
4474     { Bad_Opcode },
4475     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4476   },
4477
4478   /* PREFIX_0F38DD */
4479   {
4480     { Bad_Opcode },
4481     { Bad_Opcode },
4482     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4483   },
4484
4485   /* PREFIX_0F38DE */
4486   {
4487     { Bad_Opcode },
4488     { Bad_Opcode },
4489     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4490   },
4491
4492   /* PREFIX_0F38DF */
4493   {
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4497   },
4498
4499   /* PREFIX_0F38F0 */
4500   {
4501     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4502     { Bad_Opcode },
4503     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4504     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4505   },
4506
4507   /* PREFIX_0F38F1 */
4508   {
4509     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4510     { Bad_Opcode },
4511     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4512     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4513   },
4514
4515   /* PREFIX_0F38F6 */
4516   {
4517     { Bad_Opcode },
4518     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4519     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4520     { Bad_Opcode },
4521   },
4522
4523   /* PREFIX_0F3A08 */
4524   {
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4528   },
4529
4530   /* PREFIX_0F3A09 */
4531   {
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4535   },
4536
4537   /* PREFIX_0F3A0A */
4538   {
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4542   },
4543
4544   /* PREFIX_0F3A0B */
4545   {
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4549   },
4550
4551   /* PREFIX_0F3A0C */
4552   {
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4556   },
4557
4558   /* PREFIX_0F3A0D */
4559   {
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4563   },
4564
4565   /* PREFIX_0F3A0E */
4566   {
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4570   },
4571
4572   /* PREFIX_0F3A14 */
4573   {
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4577   },
4578
4579   /* PREFIX_0F3A15 */
4580   {
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4584   },
4585
4586   /* PREFIX_0F3A16 */
4587   {
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4591   },
4592
4593   /* PREFIX_0F3A17 */
4594   {
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4598   },
4599
4600   /* PREFIX_0F3A20 */
4601   {
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4605   },
4606
4607   /* PREFIX_0F3A21 */
4608   {
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4612   },
4613
4614   /* PREFIX_0F3A22 */
4615   {
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4619   },
4620
4621   /* PREFIX_0F3A40 */
4622   {
4623     { Bad_Opcode },
4624     { Bad_Opcode },
4625     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4626   },
4627
4628   /* PREFIX_0F3A41 */
4629   {
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4633   },
4634
4635   /* PREFIX_0F3A42 */
4636   {
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4640   },
4641
4642   /* PREFIX_0F3A44 */
4643   {
4644     { Bad_Opcode },
4645     { Bad_Opcode },
4646     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4647   },
4648
4649   /* PREFIX_0F3A60 */
4650   {
4651     { Bad_Opcode },
4652     { Bad_Opcode },
4653     { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4654   },
4655
4656   /* PREFIX_0F3A61 */
4657   {
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4661   },
4662
4663   /* PREFIX_0F3A62 */
4664   {
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4668   },
4669
4670   /* PREFIX_0F3A63 */
4671   {
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4675   },
4676
4677   /* PREFIX_0F3ACC */
4678   {
4679     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4680   },
4681
4682   /* PREFIX_0F3ADF */
4683   {
4684     { Bad_Opcode },
4685     { Bad_Opcode },
4686     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4687   },
4688
4689   /* PREFIX_VEX_0F10 */
4690   {
4691     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4692     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4693     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4694     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4695   },
4696
4697   /* PREFIX_VEX_0F11 */
4698   {
4699     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4700     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4701     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4702     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4703   },
4704
4705   /* PREFIX_VEX_0F12 */
4706   {
4707     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4708     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4709     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4710     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4711   },
4712
4713   /* PREFIX_VEX_0F16 */
4714   {
4715     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4716     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4717     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4718   },
4719
4720   /* PREFIX_VEX_0F2A */
4721   {
4722     { Bad_Opcode },
4723     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4724     { Bad_Opcode },
4725     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4726   },
4727
4728   /* PREFIX_VEX_0F2C */
4729   {
4730     { Bad_Opcode },
4731     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4732     { Bad_Opcode },
4733     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4734   },
4735
4736   /* PREFIX_VEX_0F2D */
4737   {
4738     { Bad_Opcode },
4739     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4740     { Bad_Opcode },
4741     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4742   },
4743
4744   /* PREFIX_VEX_0F2E */
4745   {
4746     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4747     { Bad_Opcode },
4748     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4749   },
4750
4751   /* PREFIX_VEX_0F2F */
4752   {
4753     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4754     { Bad_Opcode },
4755     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4756   },
4757
4758   /* PREFIX_VEX_0F41 */
4759   {
4760     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4761     { Bad_Opcode },
4762     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4763   },
4764
4765   /* PREFIX_VEX_0F42 */
4766   {
4767     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4768     { Bad_Opcode },
4769     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4770   },
4771
4772   /* PREFIX_VEX_0F44 */
4773   {
4774     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4775     { Bad_Opcode },
4776     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4777   },
4778
4779   /* PREFIX_VEX_0F45 */
4780   {
4781     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4782     { Bad_Opcode },
4783     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4784   },
4785
4786   /* PREFIX_VEX_0F46 */
4787   {
4788     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4789     { Bad_Opcode },
4790     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4791   },
4792
4793   /* PREFIX_VEX_0F47 */
4794   {
4795     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4796     { Bad_Opcode },
4797     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4798   },
4799
4800   /* PREFIX_VEX_0F4A */
4801   {
4802     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4803     { Bad_Opcode },
4804     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4805   },
4806
4807   /* PREFIX_VEX_0F4B */
4808   {
4809     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4810     { Bad_Opcode },
4811     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4812   },
4813
4814   /* PREFIX_VEX_0F51 */
4815   {
4816     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4817     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4818     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4819     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4820   },
4821
4822   /* PREFIX_VEX_0F52 */
4823   {
4824     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4825     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4826   },
4827
4828   /* PREFIX_VEX_0F53 */
4829   {
4830     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4831     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4832   },
4833
4834   /* PREFIX_VEX_0F58 */
4835   {
4836     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4837     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4838     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4839     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4840   },
4841
4842   /* PREFIX_VEX_0F59 */
4843   {
4844     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4845     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4846     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4847     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4848   },
4849
4850   /* PREFIX_VEX_0F5A */
4851   {
4852     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4853     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4854     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4855     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4856   },
4857
4858   /* PREFIX_VEX_0F5B */
4859   {
4860     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4861     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4862     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4863   },
4864
4865   /* PREFIX_VEX_0F5C */
4866   {
4867     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4868     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4869     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4870     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4871   },
4872
4873   /* PREFIX_VEX_0F5D */
4874   {
4875     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4876     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4877     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4878     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4879   },
4880
4881   /* PREFIX_VEX_0F5E */
4882   {
4883     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4884     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4885     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4886     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4887   },
4888
4889   /* PREFIX_VEX_0F5F */
4890   {
4891     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4892     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4893     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4894     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4895   },
4896
4897   /* PREFIX_VEX_0F60 */
4898   {
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4902   },
4903
4904   /* PREFIX_VEX_0F61 */
4905   {
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4909   },
4910
4911   /* PREFIX_VEX_0F62 */
4912   {
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4916   },
4917
4918   /* PREFIX_VEX_0F63 */
4919   {
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4923   },
4924
4925   /* PREFIX_VEX_0F64 */
4926   {
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4930   },
4931
4932   /* PREFIX_VEX_0F65 */
4933   {
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4937   },
4938
4939   /* PREFIX_VEX_0F66 */
4940   {
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4944   },
4945
4946   /* PREFIX_VEX_0F67 */
4947   {
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4951   },
4952
4953   /* PREFIX_VEX_0F68 */
4954   {
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4958   },
4959
4960   /* PREFIX_VEX_0F69 */
4961   {
4962     { Bad_Opcode },
4963     { Bad_Opcode },
4964     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4965   },
4966
4967   /* PREFIX_VEX_0F6A */
4968   {
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4972   },
4973
4974   /* PREFIX_VEX_0F6B */
4975   {
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4979   },
4980
4981   /* PREFIX_VEX_0F6C */
4982   {
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4986   },
4987
4988   /* PREFIX_VEX_0F6D */
4989   {
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4993   },
4994
4995   /* PREFIX_VEX_0F6E */
4996   {
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5000   },
5001
5002   /* PREFIX_VEX_0F6F */
5003   {
5004     { Bad_Opcode },
5005     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5006     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5007   },
5008
5009   /* PREFIX_VEX_0F70 */
5010   {
5011     { Bad_Opcode },
5012     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5013     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5014     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5015   },
5016
5017   /* PREFIX_VEX_0F71_REG_2 */
5018   {
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5022   },
5023
5024   /* PREFIX_VEX_0F71_REG_4 */
5025   {
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5029   },
5030
5031   /* PREFIX_VEX_0F71_REG_6 */
5032   {
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5036   },
5037
5038   /* PREFIX_VEX_0F72_REG_2 */
5039   {
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5043   },
5044
5045   /* PREFIX_VEX_0F72_REG_4 */
5046   {
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5050   },
5051
5052   /* PREFIX_VEX_0F72_REG_6 */
5053   {
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5057   },
5058
5059   /* PREFIX_VEX_0F73_REG_2 */
5060   {
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5064   },
5065
5066   /* PREFIX_VEX_0F73_REG_3 */
5067   {
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5071   },
5072
5073   /* PREFIX_VEX_0F73_REG_6 */
5074   {
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5078   },
5079
5080   /* PREFIX_VEX_0F73_REG_7 */
5081   {
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5085   },
5086
5087   /* PREFIX_VEX_0F74 */
5088   {
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5092   },
5093
5094   /* PREFIX_VEX_0F75 */
5095   {
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5099   },
5100
5101   /* PREFIX_VEX_0F76 */
5102   {
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5106   },
5107
5108   /* PREFIX_VEX_0F77 */
5109   {
5110     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5111   },
5112
5113   /* PREFIX_VEX_0F7C */
5114   {
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5118     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5119   },
5120
5121   /* PREFIX_VEX_0F7D */
5122   {
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5126     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5127   },
5128
5129   /* PREFIX_VEX_0F7E */
5130   {
5131     { Bad_Opcode },
5132     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5133     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5134   },
5135
5136   /* PREFIX_VEX_0F7F */
5137   {
5138     { Bad_Opcode },
5139     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5140     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5141   },
5142
5143   /* PREFIX_VEX_0F90 */
5144   {
5145     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5146     { Bad_Opcode },
5147     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5148   },
5149
5150   /* PREFIX_VEX_0F91 */
5151   {
5152     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5153     { Bad_Opcode },
5154     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5155   },
5156
5157   /* PREFIX_VEX_0F92 */
5158   {
5159     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5160     { Bad_Opcode },
5161     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5162     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5163   },
5164
5165   /* PREFIX_VEX_0F93 */
5166   {
5167     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5168     { Bad_Opcode },
5169     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5170     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5171   },
5172
5173   /* PREFIX_VEX_0F98 */
5174   {
5175     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5176     { Bad_Opcode },
5177     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5178   },
5179
5180   /* PREFIX_VEX_0F99 */
5181   {
5182     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5183     { Bad_Opcode },
5184     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5185   },
5186
5187   /* PREFIX_VEX_0FC2 */
5188   {
5189     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5190     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5191     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5192     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5193   },
5194
5195   /* PREFIX_VEX_0FC4 */
5196   {
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5200   },
5201
5202   /* PREFIX_VEX_0FC5 */
5203   {
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5207   },
5208
5209   /* PREFIX_VEX_0FD0 */
5210   {
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5214     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5215   },
5216
5217   /* PREFIX_VEX_0FD1 */
5218   {
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5222   },
5223
5224   /* PREFIX_VEX_0FD2 */
5225   {
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5229   },
5230
5231   /* PREFIX_VEX_0FD3 */
5232   {
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5236   },
5237
5238   /* PREFIX_VEX_0FD4 */
5239   {
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5243   },
5244
5245   /* PREFIX_VEX_0FD5 */
5246   {
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5250   },
5251
5252   /* PREFIX_VEX_0FD6 */
5253   {
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5257   },
5258
5259   /* PREFIX_VEX_0FD7 */
5260   {
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5264   },
5265
5266   /* PREFIX_VEX_0FD8 */
5267   {
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5271   },
5272
5273   /* PREFIX_VEX_0FD9 */
5274   {
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5278   },
5279
5280   /* PREFIX_VEX_0FDA */
5281   {
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5285   },
5286
5287   /* PREFIX_VEX_0FDB */
5288   {
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5292   },
5293
5294   /* PREFIX_VEX_0FDC */
5295   {
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5299   },
5300
5301   /* PREFIX_VEX_0FDD */
5302   {
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5306   },
5307
5308   /* PREFIX_VEX_0FDE */
5309   {
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5313   },
5314
5315   /* PREFIX_VEX_0FDF */
5316   {
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5320   },
5321
5322   /* PREFIX_VEX_0FE0 */
5323   {
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5327   },
5328
5329   /* PREFIX_VEX_0FE1 */
5330   {
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5334   },
5335
5336   /* PREFIX_VEX_0FE2 */
5337   {
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5341   },
5342
5343   /* PREFIX_VEX_0FE3 */
5344   {
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5348   },
5349
5350   /* PREFIX_VEX_0FE4 */
5351   {
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5355   },
5356
5357   /* PREFIX_VEX_0FE5 */
5358   {
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5362   },
5363
5364   /* PREFIX_VEX_0FE6 */
5365   {
5366     { Bad_Opcode },
5367     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5368     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5369     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5370   },
5371
5372   /* PREFIX_VEX_0FE7 */
5373   {
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5377   },
5378
5379   /* PREFIX_VEX_0FE8 */
5380   {
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5384   },
5385
5386   /* PREFIX_VEX_0FE9 */
5387   {
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5391   },
5392
5393   /* PREFIX_VEX_0FEA */
5394   {
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5398   },
5399
5400   /* PREFIX_VEX_0FEB */
5401   {
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5405   },
5406
5407   /* PREFIX_VEX_0FEC */
5408   {
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5412   },
5413
5414   /* PREFIX_VEX_0FED */
5415   {
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5419   },
5420
5421   /* PREFIX_VEX_0FEE */
5422   {
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5426   },
5427
5428   /* PREFIX_VEX_0FEF */
5429   {
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5433   },
5434
5435   /* PREFIX_VEX_0FF0 */
5436   {
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5441   },
5442
5443   /* PREFIX_VEX_0FF1 */
5444   {
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5448   },
5449
5450   /* PREFIX_VEX_0FF2 */
5451   {
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5455   },
5456
5457   /* PREFIX_VEX_0FF3 */
5458   {
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5462   },
5463
5464   /* PREFIX_VEX_0FF4 */
5465   {
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5469   },
5470
5471   /* PREFIX_VEX_0FF5 */
5472   {
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5476   },
5477
5478   /* PREFIX_VEX_0FF6 */
5479   {
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5483   },
5484
5485   /* PREFIX_VEX_0FF7 */
5486   {
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5490   },
5491
5492   /* PREFIX_VEX_0FF8 */
5493   {
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5497   },
5498
5499   /* PREFIX_VEX_0FF9 */
5500   {
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5504   },
5505
5506   /* PREFIX_VEX_0FFA */
5507   {
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5511   },
5512
5513   /* PREFIX_VEX_0FFB */
5514   {
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5518   },
5519
5520   /* PREFIX_VEX_0FFC */
5521   {
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5525   },
5526
5527   /* PREFIX_VEX_0FFD */
5528   {
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5532   },
5533
5534   /* PREFIX_VEX_0FFE */
5535   {
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5539   },
5540
5541   /* PREFIX_VEX_0F3800 */
5542   {
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5546   },
5547
5548   /* PREFIX_VEX_0F3801 */
5549   {
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5553   },
5554
5555   /* PREFIX_VEX_0F3802 */
5556   {
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5560   },
5561
5562   /* PREFIX_VEX_0F3803 */
5563   {
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5567   },
5568
5569   /* PREFIX_VEX_0F3804 */
5570   {
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5574   },
5575
5576   /* PREFIX_VEX_0F3805 */
5577   {
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5581   },
5582
5583   /* PREFIX_VEX_0F3806 */
5584   {
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5588   },
5589
5590   /* PREFIX_VEX_0F3807 */
5591   {
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5595   },
5596
5597   /* PREFIX_VEX_0F3808 */
5598   {
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5602   },
5603
5604   /* PREFIX_VEX_0F3809 */
5605   {
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5609   },
5610
5611   /* PREFIX_VEX_0F380A */
5612   {
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5616   },
5617
5618   /* PREFIX_VEX_0F380B */
5619   {
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5623   },
5624
5625   /* PREFIX_VEX_0F380C */
5626   {
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5630   },
5631
5632   /* PREFIX_VEX_0F380D */
5633   {
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5637   },
5638
5639   /* PREFIX_VEX_0F380E */
5640   {
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5644   },
5645
5646   /* PREFIX_VEX_0F380F */
5647   {
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5651   },
5652
5653   /* PREFIX_VEX_0F3813 */
5654   {
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5658   },
5659
5660   /* PREFIX_VEX_0F3816 */
5661   {
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5665   },
5666
5667   /* PREFIX_VEX_0F3817 */
5668   {
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5672   },
5673
5674   /* PREFIX_VEX_0F3818 */
5675   {
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5679   },
5680
5681   /* PREFIX_VEX_0F3819 */
5682   {
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5686   },
5687
5688   /* PREFIX_VEX_0F381A */
5689   {
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5693   },
5694
5695   /* PREFIX_VEX_0F381C */
5696   {
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5700   },
5701
5702   /* PREFIX_VEX_0F381D */
5703   {
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5707   },
5708
5709   /* PREFIX_VEX_0F381E */
5710   {
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5714   },
5715
5716   /* PREFIX_VEX_0F3820 */
5717   {
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5721   },
5722
5723   /* PREFIX_VEX_0F3821 */
5724   {
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5728   },
5729
5730   /* PREFIX_VEX_0F3822 */
5731   {
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5735   },
5736
5737   /* PREFIX_VEX_0F3823 */
5738   {
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5742   },
5743
5744   /* PREFIX_VEX_0F3824 */
5745   {
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5749   },
5750
5751   /* PREFIX_VEX_0F3825 */
5752   {
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5756   },
5757
5758   /* PREFIX_VEX_0F3828 */
5759   {
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5763   },
5764
5765   /* PREFIX_VEX_0F3829 */
5766   {
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5770   },
5771
5772   /* PREFIX_VEX_0F382A */
5773   {
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5777   },
5778
5779   /* PREFIX_VEX_0F382B */
5780   {
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5784   },
5785
5786   /* PREFIX_VEX_0F382C */
5787   {
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5791   },
5792
5793   /* PREFIX_VEX_0F382D */
5794   {
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5798   },
5799
5800   /* PREFIX_VEX_0F382E */
5801   {
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5805   },
5806
5807   /* PREFIX_VEX_0F382F */
5808   {
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5812   },
5813
5814   /* PREFIX_VEX_0F3830 */
5815   {
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5819   },
5820
5821   /* PREFIX_VEX_0F3831 */
5822   {
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5826   },
5827
5828   /* PREFIX_VEX_0F3832 */
5829   {
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5833   },
5834
5835   /* PREFIX_VEX_0F3833 */
5836   {
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5840   },
5841
5842   /* PREFIX_VEX_0F3834 */
5843   {
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5847   },
5848
5849   /* PREFIX_VEX_0F3835 */
5850   {
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5854   },
5855
5856   /* PREFIX_VEX_0F3836 */
5857   {
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5861   },
5862
5863   /* PREFIX_VEX_0F3837 */
5864   {
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5868   },
5869
5870   /* PREFIX_VEX_0F3838 */
5871   {
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5875   },
5876
5877   /* PREFIX_VEX_0F3839 */
5878   {
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5882   },
5883
5884   /* PREFIX_VEX_0F383A */
5885   {
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5889   },
5890
5891   /* PREFIX_VEX_0F383B */
5892   {
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5896   },
5897
5898   /* PREFIX_VEX_0F383C */
5899   {
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5903   },
5904
5905   /* PREFIX_VEX_0F383D */
5906   {
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5910   },
5911
5912   /* PREFIX_VEX_0F383E */
5913   {
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5917   },
5918
5919   /* PREFIX_VEX_0F383F */
5920   {
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5924   },
5925
5926   /* PREFIX_VEX_0F3840 */
5927   {
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5931   },
5932
5933   /* PREFIX_VEX_0F3841 */
5934   {
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5938   },
5939
5940   /* PREFIX_VEX_0F3845 */
5941   {
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5945   },
5946
5947   /* PREFIX_VEX_0F3846 */
5948   {
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5952   },
5953
5954   /* PREFIX_VEX_0F3847 */
5955   {
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5959   },
5960
5961   /* PREFIX_VEX_0F3858 */
5962   {
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5966   },
5967
5968   /* PREFIX_VEX_0F3859 */
5969   {
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5973   },
5974
5975   /* PREFIX_VEX_0F385A */
5976   {
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5980   },
5981
5982   /* PREFIX_VEX_0F3878 */
5983   {
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5987   },
5988
5989   /* PREFIX_VEX_0F3879 */
5990   {
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5994   },
5995
5996   /* PREFIX_VEX_0F388C */
5997   {
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6001   },
6002
6003   /* PREFIX_VEX_0F388E */
6004   {
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6008   },
6009
6010   /* PREFIX_VEX_0F3890 */
6011   {
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6015   },
6016
6017   /* PREFIX_VEX_0F3891 */
6018   {
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6022   },
6023
6024   /* PREFIX_VEX_0F3892 */
6025   {
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6029   },
6030
6031   /* PREFIX_VEX_0F3893 */
6032   {
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6036   },
6037
6038   /* PREFIX_VEX_0F3896 */
6039   {
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6043   },
6044
6045   /* PREFIX_VEX_0F3897 */
6046   {
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6050   },
6051
6052   /* PREFIX_VEX_0F3898 */
6053   {
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6057   },
6058
6059   /* PREFIX_VEX_0F3899 */
6060   {
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6064   },
6065
6066   /* PREFIX_VEX_0F389A */
6067   {
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6071   },
6072
6073   /* PREFIX_VEX_0F389B */
6074   {
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6078   },
6079
6080   /* PREFIX_VEX_0F389C */
6081   {
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6085   },
6086
6087   /* PREFIX_VEX_0F389D */
6088   {
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6092   },
6093
6094   /* PREFIX_VEX_0F389E */
6095   {
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6099   },
6100
6101   /* PREFIX_VEX_0F389F */
6102   {
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6106   },
6107
6108   /* PREFIX_VEX_0F38A6 */
6109   {
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6113     { Bad_Opcode },
6114   },
6115
6116   /* PREFIX_VEX_0F38A7 */
6117   {
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6121   },
6122
6123   /* PREFIX_VEX_0F38A8 */
6124   {
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6128   },
6129
6130   /* PREFIX_VEX_0F38A9 */
6131   {
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6135   },
6136
6137   /* PREFIX_VEX_0F38AA */
6138   {
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6142   },
6143
6144   /* PREFIX_VEX_0F38AB */
6145   {
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6149   },
6150
6151   /* PREFIX_VEX_0F38AC */
6152   {
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6156   },
6157
6158   /* PREFIX_VEX_0F38AD */
6159   {
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6163   },
6164
6165   /* PREFIX_VEX_0F38AE */
6166   {
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6170   },
6171
6172   /* PREFIX_VEX_0F38AF */
6173   {
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6177   },
6178
6179   /* PREFIX_VEX_0F38B6 */
6180   {
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6184   },
6185
6186   /* PREFIX_VEX_0F38B7 */
6187   {
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6191   },
6192
6193   /* PREFIX_VEX_0F38B8 */
6194   {
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6198   },
6199
6200   /* PREFIX_VEX_0F38B9 */
6201   {
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6205   },
6206
6207   /* PREFIX_VEX_0F38BA */
6208   {
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6212   },
6213
6214   /* PREFIX_VEX_0F38BB */
6215   {
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6219   },
6220
6221   /* PREFIX_VEX_0F38BC */
6222   {
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6226   },
6227
6228   /* PREFIX_VEX_0F38BD */
6229   {
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6233   },
6234
6235   /* PREFIX_VEX_0F38BE */
6236   {
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6240   },
6241
6242   /* PREFIX_VEX_0F38BF */
6243   {
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6247   },
6248
6249   /* PREFIX_VEX_0F38DB */
6250   {
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6254   },
6255
6256   /* PREFIX_VEX_0F38DC */
6257   {
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6261   },
6262
6263   /* PREFIX_VEX_0F38DD */
6264   {
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6268   },
6269
6270   /* PREFIX_VEX_0F38DE */
6271   {
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6275   },
6276
6277   /* PREFIX_VEX_0F38DF */
6278   {
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6282   },
6283
6284   /* PREFIX_VEX_0F38F2 */
6285   {
6286     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6287   },
6288
6289   /* PREFIX_VEX_0F38F3_REG_1 */
6290   {
6291     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6292   },
6293
6294   /* PREFIX_VEX_0F38F3_REG_2 */
6295   {
6296     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6297   },
6298
6299   /* PREFIX_VEX_0F38F3_REG_3 */
6300   {
6301     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6302   },
6303
6304   /* PREFIX_VEX_0F38F5 */
6305   {
6306     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6307     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6308     { Bad_Opcode },
6309     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6310   },
6311
6312   /* PREFIX_VEX_0F38F6 */
6313   {
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6318   },
6319
6320   /* PREFIX_VEX_0F38F7 */
6321   {
6322     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6323     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6324     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6325     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6326   },
6327
6328   /* PREFIX_VEX_0F3A00 */
6329   {
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6333   },
6334
6335   /* PREFIX_VEX_0F3A01 */
6336   {
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6340   },
6341
6342   /* PREFIX_VEX_0F3A02 */
6343   {
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6347   },
6348
6349   /* PREFIX_VEX_0F3A04 */
6350   {
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6354   },
6355
6356   /* PREFIX_VEX_0F3A05 */
6357   {
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6361   },
6362
6363   /* PREFIX_VEX_0F3A06 */
6364   {
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6368   },
6369
6370   /* PREFIX_VEX_0F3A08 */
6371   {
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6375   },
6376
6377   /* PREFIX_VEX_0F3A09 */
6378   {
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6382   },
6383
6384   /* PREFIX_VEX_0F3A0A */
6385   {
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6389   },
6390
6391   /* PREFIX_VEX_0F3A0B */
6392   {
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6396   },
6397
6398   /* PREFIX_VEX_0F3A0C */
6399   {
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6403   },
6404
6405   /* PREFIX_VEX_0F3A0D */
6406   {
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6410   },
6411
6412   /* PREFIX_VEX_0F3A0E */
6413   {
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6417   },
6418
6419   /* PREFIX_VEX_0F3A0F */
6420   {
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6424   },
6425
6426   /* PREFIX_VEX_0F3A14 */
6427   {
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6431   },
6432
6433   /* PREFIX_VEX_0F3A15 */
6434   {
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6438   },
6439
6440   /* PREFIX_VEX_0F3A16 */
6441   {
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6445   },
6446
6447   /* PREFIX_VEX_0F3A17 */
6448   {
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6452   },
6453
6454   /* PREFIX_VEX_0F3A18 */
6455   {
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6459   },
6460
6461   /* PREFIX_VEX_0F3A19 */
6462   {
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6466   },
6467
6468   /* PREFIX_VEX_0F3A1D */
6469   {
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6473   },
6474
6475   /* PREFIX_VEX_0F3A20 */
6476   {
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6480   },
6481
6482   /* PREFIX_VEX_0F3A21 */
6483   {
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6487   },
6488
6489   /* PREFIX_VEX_0F3A22 */
6490   {
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6494   },
6495
6496   /* PREFIX_VEX_0F3A30 */
6497   {
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6501   },
6502
6503   /* PREFIX_VEX_0F3A31 */
6504   {
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6508   },
6509
6510   /* PREFIX_VEX_0F3A32 */
6511   {
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6515   },
6516
6517   /* PREFIX_VEX_0F3A33 */
6518   {
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6522   },
6523
6524   /* PREFIX_VEX_0F3A38 */
6525   {
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6529   },
6530
6531   /* PREFIX_VEX_0F3A39 */
6532   {
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6536   },
6537
6538   /* PREFIX_VEX_0F3A40 */
6539   {
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6543   },
6544
6545   /* PREFIX_VEX_0F3A41 */
6546   {
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6550   },
6551
6552   /* PREFIX_VEX_0F3A42 */
6553   {
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6557   },
6558
6559   /* PREFIX_VEX_0F3A44 */
6560   {
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6564   },
6565
6566   /* PREFIX_VEX_0F3A46 */
6567   {
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6571   },
6572
6573   /* PREFIX_VEX_0F3A48 */
6574   {
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6578   },
6579
6580   /* PREFIX_VEX_0F3A49 */
6581   {
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6585   },
6586
6587   /* PREFIX_VEX_0F3A4A */
6588   {
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6592   },
6593
6594   /* PREFIX_VEX_0F3A4B */
6595   {
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6599   },
6600
6601   /* PREFIX_VEX_0F3A4C */
6602   {
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6606   },
6607
6608   /* PREFIX_VEX_0F3A5C */
6609   {
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6613   },
6614
6615   /* PREFIX_VEX_0F3A5D */
6616   {
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6620   },
6621
6622   /* PREFIX_VEX_0F3A5E */
6623   {
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6627   },
6628
6629   /* PREFIX_VEX_0F3A5F */
6630   {
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6634   },
6635
6636   /* PREFIX_VEX_0F3A60 */
6637   {
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6641     { Bad_Opcode },
6642   },
6643
6644   /* PREFIX_VEX_0F3A61 */
6645   {
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6649   },
6650
6651   /* PREFIX_VEX_0F3A62 */
6652   {
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6656   },
6657
6658   /* PREFIX_VEX_0F3A63 */
6659   {
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6663   },
6664
6665   /* PREFIX_VEX_0F3A68 */
6666   {
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6670   },
6671
6672   /* PREFIX_VEX_0F3A69 */
6673   {
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6677   },
6678
6679   /* PREFIX_VEX_0F3A6A */
6680   {
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6684   },
6685
6686   /* PREFIX_VEX_0F3A6B */
6687   {
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6691   },
6692
6693   /* PREFIX_VEX_0F3A6C */
6694   {
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6698   },
6699
6700   /* PREFIX_VEX_0F3A6D */
6701   {
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6705   },
6706
6707   /* PREFIX_VEX_0F3A6E */
6708   {
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6712   },
6713
6714   /* PREFIX_VEX_0F3A6F */
6715   {
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6719   },
6720
6721   /* PREFIX_VEX_0F3A78 */
6722   {
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6726   },
6727
6728   /* PREFIX_VEX_0F3A79 */
6729   {
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6733   },
6734
6735   /* PREFIX_VEX_0F3A7A */
6736   {
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6740   },
6741
6742   /* PREFIX_VEX_0F3A7B */
6743   {
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6747   },
6748
6749   /* PREFIX_VEX_0F3A7C */
6750   {
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6754     { Bad_Opcode },
6755   },
6756
6757   /* PREFIX_VEX_0F3A7D */
6758   {
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6762   },
6763
6764   /* PREFIX_VEX_0F3A7E */
6765   {
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6769   },
6770
6771   /* PREFIX_VEX_0F3A7F */
6772   {
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6776   },
6777
6778   /* PREFIX_VEX_0F3ADF */
6779   {
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6783   },
6784
6785   /* PREFIX_VEX_0F3AF0 */
6786   {
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6791   },
6792
6793 #define NEED_PREFIX_TABLE
6794 #include "i386-dis-evex.h"
6795 #undef NEED_PREFIX_TABLE
6796 };
6797
6798 static const struct dis386 x86_64_table[][2] = {
6799   /* X86_64_06 */
6800   {
6801     { "pushP", { es }, 0 },
6802   },
6803
6804   /* X86_64_07 */
6805   {
6806     { "popP", { es }, 0 },
6807   },
6808
6809   /* X86_64_0D */
6810   {
6811     { "pushP", { cs }, 0 },
6812   },
6813
6814   /* X86_64_16 */
6815   {
6816     { "pushP", { ss }, 0 },
6817   },
6818
6819   /* X86_64_17 */
6820   {
6821     { "popP", { ss }, 0 },
6822   },
6823
6824   /* X86_64_1E */
6825   {
6826     { "pushP", { ds }, 0 },
6827   },
6828
6829   /* X86_64_1F */
6830   {
6831     { "popP", { ds }, 0 },
6832   },
6833
6834   /* X86_64_27 */
6835   {
6836     { "daa", { XX }, 0 },
6837   },
6838
6839   /* X86_64_2F */
6840   {
6841     { "das", { XX }, 0 },
6842   },
6843
6844   /* X86_64_37 */
6845   {
6846     { "aaa", { XX }, 0 },
6847   },
6848
6849   /* X86_64_3F */
6850   {
6851     { "aas", { XX }, 0 },
6852   },
6853
6854   /* X86_64_60 */
6855   {
6856     { "pushaP", { XX }, 0 },
6857   },
6858
6859   /* X86_64_61 */
6860   {
6861     { "popaP", { XX }, 0 },
6862   },
6863
6864   /* X86_64_62 */
6865   {
6866     { MOD_TABLE (MOD_62_32BIT) },
6867     { EVEX_TABLE (EVEX_0F) },
6868   },
6869
6870   /* X86_64_63 */
6871   {
6872     { "arpl", { Ew, Gw }, 0 },
6873     { "movs{lq|xd}", { Gv, Ed }, 0 },
6874   },
6875
6876   /* X86_64_6D */
6877   {
6878     { "ins{R|}", { Yzr, indirDX }, 0 },
6879     { "ins{G|}", { Yzr, indirDX }, 0 },
6880   },
6881
6882   /* X86_64_6F */
6883   {
6884     { "outs{R|}", { indirDXr, Xz }, 0 },
6885     { "outs{G|}", { indirDXr, Xz }, 0 },
6886   },
6887
6888   /* X86_64_9A */
6889   {
6890     { "Jcall{T|}", { Ap }, 0 },
6891   },
6892
6893   /* X86_64_C4 */
6894   {
6895     { MOD_TABLE (MOD_C4_32BIT) },
6896     { VEX_C4_TABLE (VEX_0F) },
6897   },
6898
6899   /* X86_64_C5 */
6900   {
6901     { MOD_TABLE (MOD_C5_32BIT) },
6902     { VEX_C5_TABLE (VEX_0F) },
6903   },
6904
6905   /* X86_64_CE */
6906   {
6907     { "into", { XX }, 0 },
6908   },
6909
6910   /* X86_64_D4 */
6911   {
6912     { "aam", { Ib }, 0 },
6913   },
6914
6915   /* X86_64_D5 */
6916   {
6917     { "aad", { Ib }, 0 },
6918   },
6919
6920   /* X86_64_E8 */
6921   {
6922     { "callP",          { Jv, BND }, 0 },
6923     { "call@",          { Jv, BND }, 0 }
6924   },
6925
6926   /* X86_64_E9 */
6927   {
6928     { "jmpP",           { Jv, BND }, 0 },
6929     { "jmp@",           { Jv, BND }, 0 }
6930   },
6931
6932   /* X86_64_EA */
6933   {
6934     { "Jjmp{T|}", { Ap }, 0 },
6935   },
6936
6937   /* X86_64_0F01_REG_0 */
6938   {
6939     { "sgdt{Q|IQ}", { M }, 0 },
6940     { "sgdt", { M }, 0 },
6941   },
6942
6943   /* X86_64_0F01_REG_1 */
6944   {
6945     { "sidt{Q|IQ}", { M }, 0 },
6946     { "sidt", { M }, 0 },
6947   },
6948
6949   /* X86_64_0F01_REG_2 */
6950   {
6951     { "lgdt{Q|Q}", { M }, 0 },
6952     { "lgdt", { M }, 0 },
6953   },
6954
6955   /* X86_64_0F01_REG_3 */
6956   {
6957     { "lidt{Q|Q}", { M }, 0 },
6958     { "lidt", { M }, 0 },
6959   },
6960 };
6961
6962 static const struct dis386 three_byte_table[][256] = {
6963
6964   /* THREE_BYTE_0F38 */
6965   {
6966     /* 00 */
6967     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6968     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6969     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6970     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6971     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6972     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6973     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6974     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6975     /* 08 */
6976     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6977     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6978     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6979     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     /* 10 */
6985     { PREFIX_TABLE (PREFIX_0F3810) },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { PREFIX_TABLE (PREFIX_0F3814) },
6990     { PREFIX_TABLE (PREFIX_0F3815) },
6991     { Bad_Opcode },
6992     { PREFIX_TABLE (PREFIX_0F3817) },
6993     /* 18 */
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6999     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7000     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7001     { Bad_Opcode },
7002     /* 20 */
7003     { PREFIX_TABLE (PREFIX_0F3820) },
7004     { PREFIX_TABLE (PREFIX_0F3821) },
7005     { PREFIX_TABLE (PREFIX_0F3822) },
7006     { PREFIX_TABLE (PREFIX_0F3823) },
7007     { PREFIX_TABLE (PREFIX_0F3824) },
7008     { PREFIX_TABLE (PREFIX_0F3825) },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     /* 28 */
7012     { PREFIX_TABLE (PREFIX_0F3828) },
7013     { PREFIX_TABLE (PREFIX_0F3829) },
7014     { PREFIX_TABLE (PREFIX_0F382A) },
7015     { PREFIX_TABLE (PREFIX_0F382B) },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     /* 30 */
7021     { PREFIX_TABLE (PREFIX_0F3830) },
7022     { PREFIX_TABLE (PREFIX_0F3831) },
7023     { PREFIX_TABLE (PREFIX_0F3832) },
7024     { PREFIX_TABLE (PREFIX_0F3833) },
7025     { PREFIX_TABLE (PREFIX_0F3834) },
7026     { PREFIX_TABLE (PREFIX_0F3835) },
7027     { Bad_Opcode },
7028     { PREFIX_TABLE (PREFIX_0F3837) },
7029     /* 38 */
7030     { PREFIX_TABLE (PREFIX_0F3838) },
7031     { PREFIX_TABLE (PREFIX_0F3839) },
7032     { PREFIX_TABLE (PREFIX_0F383A) },
7033     { PREFIX_TABLE (PREFIX_0F383B) },
7034     { PREFIX_TABLE (PREFIX_0F383C) },
7035     { PREFIX_TABLE (PREFIX_0F383D) },
7036     { PREFIX_TABLE (PREFIX_0F383E) },
7037     { PREFIX_TABLE (PREFIX_0F383F) },
7038     /* 40 */
7039     { PREFIX_TABLE (PREFIX_0F3840) },
7040     { PREFIX_TABLE (PREFIX_0F3841) },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     /* 48 */
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     /* 50 */
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     /* 58 */
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     /* 60 */
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     /* 68 */
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     /* 70 */
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     /* 78 */
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     /* 80 */
7111     { PREFIX_TABLE (PREFIX_0F3880) },
7112     { PREFIX_TABLE (PREFIX_0F3881) },
7113     { PREFIX_TABLE (PREFIX_0F3882) },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     /* 88 */
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     /* 90 */
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     /* 98 */
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     /* a0 */
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     /* a8 */
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     /* b0 */
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     /* b8 */
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     /* c0 */
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     /* c8 */
7192     { PREFIX_TABLE (PREFIX_0F38C8) },
7193     { PREFIX_TABLE (PREFIX_0F38C9) },
7194     { PREFIX_TABLE (PREFIX_0F38CA) },
7195     { PREFIX_TABLE (PREFIX_0F38CB) },
7196     { PREFIX_TABLE (PREFIX_0F38CC) },
7197     { PREFIX_TABLE (PREFIX_0F38CD) },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     /* d0 */
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     /* d8 */
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { PREFIX_TABLE (PREFIX_0F38DB) },
7214     { PREFIX_TABLE (PREFIX_0F38DC) },
7215     { PREFIX_TABLE (PREFIX_0F38DD) },
7216     { PREFIX_TABLE (PREFIX_0F38DE) },
7217     { PREFIX_TABLE (PREFIX_0F38DF) },
7218     /* e0 */
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     /* e8 */
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     /* f0 */
7237     { PREFIX_TABLE (PREFIX_0F38F0) },
7238     { PREFIX_TABLE (PREFIX_0F38F1) },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { PREFIX_TABLE (PREFIX_0F38F6) },
7244     { Bad_Opcode },
7245     /* f8 */
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254   },
7255   /* THREE_BYTE_0F3A */
7256   {
7257     /* 00 */
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     /* 08 */
7267     { PREFIX_TABLE (PREFIX_0F3A08) },
7268     { PREFIX_TABLE (PREFIX_0F3A09) },
7269     { PREFIX_TABLE (PREFIX_0F3A0A) },
7270     { PREFIX_TABLE (PREFIX_0F3A0B) },
7271     { PREFIX_TABLE (PREFIX_0F3A0C) },
7272     { PREFIX_TABLE (PREFIX_0F3A0D) },
7273     { PREFIX_TABLE (PREFIX_0F3A0E) },
7274     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7275     /* 10 */
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { PREFIX_TABLE (PREFIX_0F3A14) },
7281     { PREFIX_TABLE (PREFIX_0F3A15) },
7282     { PREFIX_TABLE (PREFIX_0F3A16) },
7283     { PREFIX_TABLE (PREFIX_0F3A17) },
7284     /* 18 */
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     /* 20 */
7294     { PREFIX_TABLE (PREFIX_0F3A20) },
7295     { PREFIX_TABLE (PREFIX_0F3A21) },
7296     { PREFIX_TABLE (PREFIX_0F3A22) },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     /* 28 */
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     /* 30 */
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     /* 38 */
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     /* 40 */
7330     { PREFIX_TABLE (PREFIX_0F3A40) },
7331     { PREFIX_TABLE (PREFIX_0F3A41) },
7332     { PREFIX_TABLE (PREFIX_0F3A42) },
7333     { Bad_Opcode },
7334     { PREFIX_TABLE (PREFIX_0F3A44) },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     /* 48 */
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     /* 50 */
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     /* 58 */
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     /* 60 */
7366     { PREFIX_TABLE (PREFIX_0F3A60) },
7367     { PREFIX_TABLE (PREFIX_0F3A61) },
7368     { PREFIX_TABLE (PREFIX_0F3A62) },
7369     { PREFIX_TABLE (PREFIX_0F3A63) },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     /* 68 */
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     /* 70 */
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     /* 78 */
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     /* 80 */
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     /* 88 */
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     /* 90 */
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     /* 98 */
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     /* a0 */
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     /* a8 */
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     /* b0 */
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     /* b8 */
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     /* c0 */
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     /* c8 */
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { PREFIX_TABLE (PREFIX_0F3ACC) },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     /* d0 */
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     /* d8 */
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { PREFIX_TABLE (PREFIX_0F3ADF) },
7509     /* e0 */
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     /* e8 */
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     /* f0 */
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     /* f8 */
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545   },
7546
7547   /* THREE_BYTE_0F7A */
7548   {
7549     /* 00 */
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     /* 08 */
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     /* 10 */
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     /* 18 */
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     /* 20 */
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     /* 28 */
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     /* 30 */
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     /* 38 */
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     /* 40 */
7622     { Bad_Opcode },
7623     { "phaddbw",        { XM, EXq }, PREFIX_OPCODE },
7624     { "phaddbd",        { XM, EXq }, PREFIX_OPCODE },
7625     { "phaddbq",        { XM, EXq }, PREFIX_OPCODE },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { "phaddwd",        { XM, EXq }, PREFIX_OPCODE },
7629     { "phaddwq",        { XM, EXq }, PREFIX_OPCODE },
7630     /* 48 */
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { "phadddq",        { XM, EXq }, PREFIX_OPCODE },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     /* 50 */
7640     { Bad_Opcode },
7641     { "phaddubw",       { XM, EXq }, PREFIX_OPCODE },
7642     { "phaddubd",       { XM, EXq }, PREFIX_OPCODE },
7643     { "phaddubq",       { XM, EXq }, PREFIX_OPCODE },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { "phadduwd",       { XM, EXq }, PREFIX_OPCODE },
7647     { "phadduwq",       { XM, EXq }, PREFIX_OPCODE },
7648     /* 58 */
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { "phaddudq",       { XM, EXq }, PREFIX_OPCODE },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     /* 60 */
7658     { Bad_Opcode },
7659     { "phsubbw",        { XM, EXq }, PREFIX_OPCODE },
7660     { "phsubbd",        { XM, EXq }, PREFIX_OPCODE },
7661     { "phsubbq",        { XM, EXq }, PREFIX_OPCODE },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     /* 68 */
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     /* 70 */
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     /* 78 */
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     /* 80 */
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     /* 88 */
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     /* 90 */
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     /* 98 */
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     /* a0 */
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     /* a8 */
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     /* b0 */
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     /* b8 */
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     /* c0 */
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     /* c8 */
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     /* d0 */
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     /* d8 */
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     /* e0 */
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     /* e8 */
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     /* f0 */
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     /* f8 */
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837   },
7838 };
7839
7840 static const struct dis386 xop_table[][256] = {
7841   /* XOP_08 */
7842   {
7843     /* 00 */
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     /* 08 */
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     /* 10 */
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     /* 18 */
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     /* 20 */
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     /* 28 */
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     /* 30 */
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     /* 38 */
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     /* 40 */
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     /* 48 */
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     /* 50 */
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     /* 58 */
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     /* 60 */
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     /* 68 */
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     /* 70 */
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     /* 78 */
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     /* 80 */
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7994     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7995     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7996     /* 88 */
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8004     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8005     /* 90 */
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8012     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8013     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8014     /* 98 */
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8022     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8023     /* a0 */
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8027     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8031     { Bad_Opcode },
8032     /* a8 */
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     /* b0 */
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8049     { Bad_Opcode },
8050     /* b8 */
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     /* c0 */
8060     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
8061     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
8062     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
8063     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     /* c8 */
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
8074     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
8075     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
8076     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
8077     /* d0 */
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     /* d8 */
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     /* e0 */
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     /* e8 */
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8110     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8111     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8112     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8113     /* f0 */
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     /* f8 */
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131   },
8132   /* XOP_09 */
8133   {
8134     /* 00 */
8135     { Bad_Opcode },
8136     { REG_TABLE (REG_XOP_TBM_01) },
8137     { REG_TABLE (REG_XOP_TBM_02) },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     /* 08 */
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     /* 10 */
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { REG_TABLE (REG_XOP_LWPCB) },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     /* 18 */
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     /* 20 */
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     /* 28 */
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     /* 30 */
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     /* 38 */
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     /* 40 */
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     /* 48 */
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     /* 50 */
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     /* 58 */
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     /* 60 */
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     /* 68 */
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     /* 70 */
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     /* 78 */
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     /* 80 */
8279     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8280     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8281     { "vfrczss",        { XM, EXd }, 0 },
8282     { "vfrczsd",        { XM, EXq }, 0 },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     /* 88 */
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     /* 90 */
8297     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8298     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8299     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8300     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8301     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8302     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8303     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8304     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8305     /* 98 */
8306     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8307     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8308     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8309     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     /* a0 */
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     /* a8 */
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     /* b0 */
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     /* b8 */
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     /* c0 */
8351     { Bad_Opcode },
8352     { "vphaddbw",       { XM, EXxmm }, 0 },
8353     { "vphaddbd",       { XM, EXxmm }, 0 },
8354     { "vphaddbq",       { XM, EXxmm }, 0 },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { "vphaddwd",       { XM, EXxmm }, 0 },
8358     { "vphaddwq",       { XM, EXxmm }, 0 },
8359     /* c8 */
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { "vphadddq",       { XM, EXxmm }, 0 },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     /* d0 */
8369     { Bad_Opcode },
8370     { "vphaddubw",      { XM, EXxmm }, 0 },
8371     { "vphaddubd",      { XM, EXxmm }, 0 },
8372     { "vphaddubq",      { XM, EXxmm }, 0 },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { "vphadduwd",      { XM, EXxmm }, 0 },
8376     { "vphadduwq",      { XM, EXxmm }, 0 },
8377     /* d8 */
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { "vphaddudq",      { XM, EXxmm }, 0 },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     /* e0 */
8387     { Bad_Opcode },
8388     { "vphsubbw",       { XM, EXxmm }, 0 },
8389     { "vphsubwd",       { XM, EXxmm }, 0 },
8390     { "vphsubdq",       { XM, EXxmm }, 0 },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     /* e8 */
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     /* f0 */
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     /* f8 */
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422   },
8423   /* XOP_0A */
8424   {
8425     /* 00 */
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     /* 08 */
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     /* 10 */
8444     { "bextr",  { Gv, Ev, Iq }, 0 },
8445     { Bad_Opcode },
8446     { REG_TABLE (REG_XOP_LWP) },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     /* 18 */
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     /* 20 */
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     /* 28 */
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     /* 30 */
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     /* 38 */
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     /* 40 */
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     /* 48 */
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     /* 50 */
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     /* 58 */
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     /* 60 */
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     /* 68 */
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     /* 70 */
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     /* 78 */
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     /* 80 */
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     /* 88 */
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     /* 90 */
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     /* 98 */
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     /* a0 */
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     /* a8 */
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     /* b0 */
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     /* b8 */
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     /* c0 */
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     /* c8 */
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     /* d0 */
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     /* d8 */
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     { Bad_Opcode },
8677     /* e0 */
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     /* e8 */
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     /* f0 */
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     /* f8 */
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713   },
8714 };
8715
8716 static const struct dis386 vex_table[][256] = {
8717   /* VEX_0F */
8718   {
8719     /* 00 */
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { Bad_Opcode },
8728     /* 08 */
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     /* 10 */
8738     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8741     { MOD_TABLE (MOD_VEX_0F13) },
8742     { VEX_W_TABLE (VEX_W_0F14) },
8743     { VEX_W_TABLE (VEX_W_0F15) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8745     { MOD_TABLE (MOD_VEX_0F17) },
8746     /* 18 */
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     /* 20 */
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     /* 28 */
8765     { VEX_W_TABLE (VEX_W_0F28) },
8766     { VEX_W_TABLE (VEX_W_0F29) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8768     { MOD_TABLE (MOD_VEX_0F2B) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8773     /* 30 */
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     /* 38 */
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     /* 40 */
8792     { Bad_Opcode },
8793     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8795     { Bad_Opcode },
8796     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8800     /* 48 */
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     /* 50 */
8810     { MOD_TABLE (MOD_VEX_0F50) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8813     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8814     { "vandpX",         { XM, Vex, EXx }, 0 },
8815     { "vandnpX",        { XM, Vex, EXx }, 0 },
8816     { "vorpX",          { XM, Vex, EXx }, 0 },
8817     { "vxorpX",         { XM, Vex, EXx }, 0 },
8818     /* 58 */
8819     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8821     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8822     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8823     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8824     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8825     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8826     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8827     /* 60 */
8828     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8829     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8830     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8831     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8832     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8833     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8834     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8835     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8836     /* 68 */
8837     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8838     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8839     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8840     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8841     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8842     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8843     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8844     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8845     /* 70 */
8846     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8847     { REG_TABLE (REG_VEX_0F71) },
8848     { REG_TABLE (REG_VEX_0F72) },
8849     { REG_TABLE (REG_VEX_0F73) },
8850     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8851     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8852     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8853     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8854     /* 78 */
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8860     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8861     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8862     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8863     /* 80 */
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     /* 88 */
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     /* 90 */
8882     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8883     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     { Bad_Opcode },
8890     /* 98 */
8891     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     /* a0 */
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     /* a8 */
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { REG_TABLE (REG_VEX_0FAE) },
8916     { Bad_Opcode },
8917     /* b0 */
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     /* b8 */
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     /* c0 */
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8939     { Bad_Opcode },
8940     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8941     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8942     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8943     { Bad_Opcode },
8944     /* c8 */
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     /* d0 */
8954     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8955     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8956     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8957     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8958     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8959     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8960     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8961     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8962     /* d8 */
8963     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8964     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8965     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8966     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8967     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8968     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8969     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8970     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8971     /* e0 */
8972     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8973     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8974     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8975     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8976     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8977     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8978     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8979     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8980     /* e8 */
8981     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8982     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8983     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8984     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8985     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8986     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8987     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8988     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8989     /* f0 */
8990     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8991     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8992     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8993     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8994     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8995     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8996     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8997     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8998     /* f8 */
8999     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
9000     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
9001     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
9002     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
9003     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
9004     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
9005     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
9006     { Bad_Opcode },
9007   },
9008   /* VEX_0F38 */
9009   {
9010     /* 00 */
9011     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
9015     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
9019     /* 08 */
9020     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
9024     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
9026     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
9028     /* 10 */
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
9036     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
9037     /* 18 */
9038     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
9041     { Bad_Opcode },
9042     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
9045     { Bad_Opcode },
9046     /* 20 */
9047     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
9051     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     /* 28 */
9056     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
9061     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
9062     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
9063     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
9064     /* 30 */
9065     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
9068     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
9069     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
9073     /* 38 */
9074     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
9078     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
9079     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
9080     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
9081     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
9082     /* 40 */
9083     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
9084     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9091     /* 48 */
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     /* 50 */
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     /* 58 */
9110     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     /* 60 */
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     /* 68 */
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     /* 70 */
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     /* 78 */
9146     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9147     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     /* 80 */
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     /* 88 */
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9169     { Bad_Opcode },
9170     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9171     { Bad_Opcode },
9172     /* 90 */
9173     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9174     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9175     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9176     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9180     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9181     /* 98 */
9182     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9183     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9184     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9185     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9186     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9187     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9188     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9189     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9190     /* a0 */
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9198     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9199     /* a8 */
9200     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9201     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9202     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9203     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9204     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9205     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9206     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9207     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9208     /* b0 */
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9216     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9217     /* b8 */
9218     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9219     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9220     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9221     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9222     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9223     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9224     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9225     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9226     /* c0 */
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     /* c8 */
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     /* d0 */
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     /* d8 */
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9258     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9259     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9260     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9261     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9262     /* e0 */
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     /* e8 */
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     /* f0 */
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9284     { REG_TABLE (REG_VEX_0F38F3) },
9285     { Bad_Opcode },
9286     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9287     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9288     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9289     /* f8 */
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298   },
9299   /* VEX_0F3A */
9300   {
9301     /* 00 */
9302     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9303     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9304     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9305     { Bad_Opcode },
9306     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9307     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9308     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9309     { Bad_Opcode },
9310     /* 08 */
9311     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9312     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9313     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9314     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9315     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9316     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9317     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9318     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9319     /* 10 */
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9325     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9326     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9327     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9328     /* 18 */
9329     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9330     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     /* 20 */
9338     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9339     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9340     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     /* 28 */
9347     { Bad_Opcode },
9348     { Bad_Opcode },
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     /* 30 */
9356     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9357     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9358     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9359     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     /* 38 */
9365     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9366     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9367     { Bad_Opcode },
9368     { Bad_Opcode },
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     { Bad_Opcode },
9373     /* 40 */
9374     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9375     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9376     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9377     { Bad_Opcode },
9378     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9379     { Bad_Opcode },
9380     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9381     { Bad_Opcode },
9382     /* 48 */
9383     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9384     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9385     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9386     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9387     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     /* 50 */
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     /* 58 */
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9406     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9407     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9408     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9409     /* 60 */
9410     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9411     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9412     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9413     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     /* 68 */
9419     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9420     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9421     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9422     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9423     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9424     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9425     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9426     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9427     /* 70 */
9428     { Bad_Opcode },
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     /* 78 */
9437     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9438     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9439     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9440     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9441     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9442     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9443     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9444     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9445     /* 80 */
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     { Bad_Opcode },
9454     /* 88 */
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461     { Bad_Opcode },
9462     { Bad_Opcode },
9463     /* 90 */
9464     { Bad_Opcode },
9465     { Bad_Opcode },
9466     { Bad_Opcode },
9467     { Bad_Opcode },
9468     { Bad_Opcode },
9469     { Bad_Opcode },
9470     { Bad_Opcode },
9471     { Bad_Opcode },
9472     /* 98 */
9473     { Bad_Opcode },
9474     { Bad_Opcode },
9475     { Bad_Opcode },
9476     { Bad_Opcode },
9477     { Bad_Opcode },
9478     { Bad_Opcode },
9479     { Bad_Opcode },
9480     { Bad_Opcode },
9481     /* a0 */
9482     { Bad_Opcode },
9483     { Bad_Opcode },
9484     { Bad_Opcode },
9485     { Bad_Opcode },
9486     { Bad_Opcode },
9487     { Bad_Opcode },
9488     { Bad_Opcode },
9489     { Bad_Opcode },
9490     /* a8 */
9491     { Bad_Opcode },
9492     { Bad_Opcode },
9493     { Bad_Opcode },
9494     { Bad_Opcode },
9495     { Bad_Opcode },
9496     { Bad_Opcode },
9497     { Bad_Opcode },
9498     { Bad_Opcode },
9499     /* b0 */
9500     { Bad_Opcode },
9501     { Bad_Opcode },
9502     { Bad_Opcode },
9503     { Bad_Opcode },
9504     { Bad_Opcode },
9505     { Bad_Opcode },
9506     { Bad_Opcode },
9507     { Bad_Opcode },
9508     /* b8 */
9509     { Bad_Opcode },
9510     { Bad_Opcode },
9511     { Bad_Opcode },
9512     { Bad_Opcode },
9513     { Bad_Opcode },
9514     { Bad_Opcode },
9515     { Bad_Opcode },
9516     { Bad_Opcode },
9517     /* c0 */
9518     { Bad_Opcode },
9519     { Bad_Opcode },
9520     { Bad_Opcode },
9521     { Bad_Opcode },
9522     { Bad_Opcode },
9523     { Bad_Opcode },
9524     { Bad_Opcode },
9525     { Bad_Opcode },
9526     /* c8 */
9527     { Bad_Opcode },
9528     { Bad_Opcode },
9529     { Bad_Opcode },
9530     { Bad_Opcode },
9531     { Bad_Opcode },
9532     { Bad_Opcode },
9533     { Bad_Opcode },
9534     { Bad_Opcode },
9535     /* d0 */
9536     { Bad_Opcode },
9537     { Bad_Opcode },
9538     { Bad_Opcode },
9539     { Bad_Opcode },
9540     { Bad_Opcode },
9541     { Bad_Opcode },
9542     { Bad_Opcode },
9543     { Bad_Opcode },
9544     /* d8 */
9545     { Bad_Opcode },
9546     { Bad_Opcode },
9547     { Bad_Opcode },
9548     { Bad_Opcode },
9549     { Bad_Opcode },
9550     { Bad_Opcode },
9551     { Bad_Opcode },
9552     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9553     /* e0 */
9554     { Bad_Opcode },
9555     { Bad_Opcode },
9556     { Bad_Opcode },
9557     { Bad_Opcode },
9558     { Bad_Opcode },
9559     { Bad_Opcode },
9560     { Bad_Opcode },
9561     { Bad_Opcode },
9562     /* e8 */
9563     { Bad_Opcode },
9564     { Bad_Opcode },
9565     { Bad_Opcode },
9566     { Bad_Opcode },
9567     { Bad_Opcode },
9568     { Bad_Opcode },
9569     { Bad_Opcode },
9570     { Bad_Opcode },
9571     /* f0 */
9572     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9573     { Bad_Opcode },
9574     { Bad_Opcode },
9575     { Bad_Opcode },
9576     { Bad_Opcode },
9577     { Bad_Opcode },
9578     { Bad_Opcode },
9579     { Bad_Opcode },
9580     /* f8 */
9581     { Bad_Opcode },
9582     { Bad_Opcode },
9583     { Bad_Opcode },
9584     { Bad_Opcode },
9585     { Bad_Opcode },
9586     { Bad_Opcode },
9587     { Bad_Opcode },
9588     { Bad_Opcode },
9589   },
9590 };
9591
9592 #define NEED_OPCODE_TABLE
9593 #include "i386-dis-evex.h"
9594 #undef NEED_OPCODE_TABLE
9595 static const struct dis386 vex_len_table[][2] = {
9596   /* VEX_LEN_0F10_P_1 */
9597   {
9598     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9599     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9600   },
9601
9602   /* VEX_LEN_0F10_P_3 */
9603   {
9604     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9605     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9606   },
9607
9608   /* VEX_LEN_0F11_P_1 */
9609   {
9610     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9611     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9612   },
9613
9614   /* VEX_LEN_0F11_P_3 */
9615   {
9616     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9617     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9618   },
9619
9620   /* VEX_LEN_0F12_P_0_M_0 */
9621   {
9622     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9623   },
9624
9625   /* VEX_LEN_0F12_P_0_M_1 */
9626   {
9627     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9628   },
9629
9630   /* VEX_LEN_0F12_P_2 */
9631   {
9632     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9633   },
9634
9635   /* VEX_LEN_0F13_M_0 */
9636   {
9637     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9638   },
9639
9640   /* VEX_LEN_0F16_P_0_M_0 */
9641   {
9642     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9643   },
9644
9645   /* VEX_LEN_0F16_P_0_M_1 */
9646   {
9647     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9648   },
9649
9650   /* VEX_LEN_0F16_P_2 */
9651   {
9652     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9653   },
9654
9655   /* VEX_LEN_0F17_M_0 */
9656   {
9657     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9658   },
9659
9660   /* VEX_LEN_0F2A_P_1 */
9661   {
9662     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9663     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9664   },
9665
9666   /* VEX_LEN_0F2A_P_3 */
9667   {
9668     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9669     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9670   },
9671
9672   /* VEX_LEN_0F2C_P_1 */
9673   {
9674     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9675     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9676   },
9677
9678   /* VEX_LEN_0F2C_P_3 */
9679   {
9680     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9681     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9682   },
9683
9684   /* VEX_LEN_0F2D_P_1 */
9685   {
9686     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9687     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9688   },
9689
9690   /* VEX_LEN_0F2D_P_3 */
9691   {
9692     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9693     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9694   },
9695
9696   /* VEX_LEN_0F2E_P_0 */
9697   {
9698     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9699     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9700   },
9701
9702   /* VEX_LEN_0F2E_P_2 */
9703   {
9704     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9705     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9706   },
9707
9708   /* VEX_LEN_0F2F_P_0 */
9709   {
9710     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9711     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9712   },
9713
9714   /* VEX_LEN_0F2F_P_2 */
9715   {
9716     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9717     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9718   },
9719
9720   /* VEX_LEN_0F41_P_0 */
9721   {
9722     { Bad_Opcode },
9723     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9724   },
9725   /* VEX_LEN_0F41_P_2 */
9726   {
9727     { Bad_Opcode },
9728     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9729   },
9730   /* VEX_LEN_0F42_P_0 */
9731   {
9732     { Bad_Opcode },
9733     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9734   },
9735   /* VEX_LEN_0F42_P_2 */
9736   {
9737     { Bad_Opcode },
9738     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9739   },
9740   /* VEX_LEN_0F44_P_0 */
9741   {
9742     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9743   },
9744   /* VEX_LEN_0F44_P_2 */
9745   {
9746     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9747   },
9748   /* VEX_LEN_0F45_P_0 */
9749   {
9750     { Bad_Opcode },
9751     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9752   },
9753   /* VEX_LEN_0F45_P_2 */
9754   {
9755     { Bad_Opcode },
9756     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9757   },
9758   /* VEX_LEN_0F46_P_0 */
9759   {
9760     { Bad_Opcode },
9761     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9762   },
9763   /* VEX_LEN_0F46_P_2 */
9764   {
9765     { Bad_Opcode },
9766     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9767   },
9768   /* VEX_LEN_0F47_P_0 */
9769   {
9770     { Bad_Opcode },
9771     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9772   },
9773   /* VEX_LEN_0F47_P_2 */
9774   {
9775     { Bad_Opcode },
9776     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9777   },
9778   /* VEX_LEN_0F4A_P_0 */
9779   {
9780     { Bad_Opcode },
9781     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9782   },
9783   /* VEX_LEN_0F4A_P_2 */
9784   {
9785     { Bad_Opcode },
9786     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9787   },
9788   /* VEX_LEN_0F4B_P_0 */
9789   {
9790     { Bad_Opcode },
9791     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9792   },
9793   /* VEX_LEN_0F4B_P_2 */
9794   {
9795     { Bad_Opcode },
9796     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9797   },
9798
9799   /* VEX_LEN_0F51_P_1 */
9800   {
9801     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9802     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9803   },
9804
9805   /* VEX_LEN_0F51_P_3 */
9806   {
9807     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9808     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9809   },
9810
9811   /* VEX_LEN_0F52_P_1 */
9812   {
9813     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9814     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9815   },
9816
9817   /* VEX_LEN_0F53_P_1 */
9818   {
9819     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9820     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9821   },
9822
9823   /* VEX_LEN_0F58_P_1 */
9824   {
9825     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9826     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9827   },
9828
9829   /* VEX_LEN_0F58_P_3 */
9830   {
9831     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9832     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9833   },
9834
9835   /* VEX_LEN_0F59_P_1 */
9836   {
9837     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9838     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9839   },
9840
9841   /* VEX_LEN_0F59_P_3 */
9842   {
9843     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9844     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9845   },
9846
9847   /* VEX_LEN_0F5A_P_1 */
9848   {
9849     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9850     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9851   },
9852
9853   /* VEX_LEN_0F5A_P_3 */
9854   {
9855     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9856     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9857   },
9858
9859   /* VEX_LEN_0F5C_P_1 */
9860   {
9861     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9862     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9863   },
9864
9865   /* VEX_LEN_0F5C_P_3 */
9866   {
9867     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9868     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9869   },
9870
9871   /* VEX_LEN_0F5D_P_1 */
9872   {
9873     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9874     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9875   },
9876
9877   /* VEX_LEN_0F5D_P_3 */
9878   {
9879     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9880     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9881   },
9882
9883   /* VEX_LEN_0F5E_P_1 */
9884   {
9885     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9886     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9887   },
9888
9889   /* VEX_LEN_0F5E_P_3 */
9890   {
9891     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9892     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9893   },
9894
9895   /* VEX_LEN_0F5F_P_1 */
9896   {
9897     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9898     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9899   },
9900
9901   /* VEX_LEN_0F5F_P_3 */
9902   {
9903     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9904     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9905   },
9906
9907   /* VEX_LEN_0F6E_P_2 */
9908   {
9909     { "vmovK",          { XMScalar, Edq }, 0 },
9910     { "vmovK",          { XMScalar, Edq }, 0 },
9911   },
9912
9913   /* VEX_LEN_0F7E_P_1 */
9914   {
9915     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9916     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9917   },
9918
9919   /* VEX_LEN_0F7E_P_2 */
9920   {
9921     { "vmovK",          { Edq, XMScalar }, 0 },
9922     { "vmovK",          { Edq, XMScalar }, 0 },
9923   },
9924
9925   /* VEX_LEN_0F90_P_0 */
9926   {
9927     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9928   },
9929
9930   /* VEX_LEN_0F90_P_2 */
9931   {
9932     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9933   },
9934
9935   /* VEX_LEN_0F91_P_0 */
9936   {
9937     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9938   },
9939
9940   /* VEX_LEN_0F91_P_2 */
9941   {
9942     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9943   },
9944
9945   /* VEX_LEN_0F92_P_0 */
9946   {
9947     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9948   },
9949
9950   /* VEX_LEN_0F92_P_2 */
9951   {
9952     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9953   },
9954
9955   /* VEX_LEN_0F92_P_3 */
9956   {
9957     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9958   },
9959
9960   /* VEX_LEN_0F93_P_0 */
9961   {
9962     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9963   },
9964
9965   /* VEX_LEN_0F93_P_2 */
9966   {
9967     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9968   },
9969
9970   /* VEX_LEN_0F93_P_3 */
9971   {
9972     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9973   },
9974
9975   /* VEX_LEN_0F98_P_0 */
9976   {
9977     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9978   },
9979
9980   /* VEX_LEN_0F98_P_2 */
9981   {
9982     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9983   },
9984
9985   /* VEX_LEN_0F99_P_0 */
9986   {
9987     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9988   },
9989
9990   /* VEX_LEN_0F99_P_2 */
9991   {
9992     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9993   },
9994
9995   /* VEX_LEN_0FAE_R_2_M_0 */
9996   {
9997     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9998   },
9999
10000   /* VEX_LEN_0FAE_R_3_M_0 */
10001   {
10002     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
10003   },
10004
10005   /* VEX_LEN_0FC2_P_1 */
10006   {
10007     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
10008     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
10009   },
10010
10011   /* VEX_LEN_0FC2_P_3 */
10012   {
10013     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
10014     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
10015   },
10016
10017   /* VEX_LEN_0FC4_P_2 */
10018   {
10019     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
10020   },
10021
10022   /* VEX_LEN_0FC5_P_2 */
10023   {
10024     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
10025   },
10026
10027   /* VEX_LEN_0FD6_P_2 */
10028   {
10029     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
10030     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
10031   },
10032
10033   /* VEX_LEN_0FF7_P_2 */
10034   {
10035     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
10036   },
10037
10038   /* VEX_LEN_0F3816_P_2 */
10039   {
10040     { Bad_Opcode },
10041     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
10042   },
10043
10044   /* VEX_LEN_0F3819_P_2 */
10045   {
10046     { Bad_Opcode },
10047     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
10048   },
10049
10050   /* VEX_LEN_0F381A_P_2_M_0 */
10051   {
10052     { Bad_Opcode },
10053     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
10054   },
10055
10056   /* VEX_LEN_0F3836_P_2 */
10057   {
10058     { Bad_Opcode },
10059     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
10060   },
10061
10062   /* VEX_LEN_0F3841_P_2 */
10063   {
10064     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
10065   },
10066
10067   /* VEX_LEN_0F385A_P_2_M_0 */
10068   {
10069     { Bad_Opcode },
10070     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
10071   },
10072
10073   /* VEX_LEN_0F38DB_P_2 */
10074   {
10075     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
10076   },
10077
10078   /* VEX_LEN_0F38DC_P_2 */
10079   {
10080     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
10081   },
10082
10083   /* VEX_LEN_0F38DD_P_2 */
10084   {
10085     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
10086   },
10087
10088   /* VEX_LEN_0F38DE_P_2 */
10089   {
10090     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
10091   },
10092
10093   /* VEX_LEN_0F38DF_P_2 */
10094   {
10095     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
10096   },
10097
10098   /* VEX_LEN_0F38F2_P_0 */
10099   {
10100     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
10101   },
10102
10103   /* VEX_LEN_0F38F3_R_1_P_0 */
10104   {
10105     { "blsrS",          { VexGdq, Edq }, 0 },
10106   },
10107
10108   /* VEX_LEN_0F38F3_R_2_P_0 */
10109   {
10110     { "blsmskS",        { VexGdq, Edq }, 0 },
10111   },
10112
10113   /* VEX_LEN_0F38F3_R_3_P_0 */
10114   {
10115     { "blsiS",          { VexGdq, Edq }, 0 },
10116   },
10117
10118   /* VEX_LEN_0F38F5_P_0 */
10119   {
10120     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
10121   },
10122
10123   /* VEX_LEN_0F38F5_P_1 */
10124   {
10125     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
10126   },
10127
10128   /* VEX_LEN_0F38F5_P_3 */
10129   {
10130     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
10131   },
10132
10133   /* VEX_LEN_0F38F6_P_3 */
10134   {
10135     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
10136   },
10137
10138   /* VEX_LEN_0F38F7_P_0 */
10139   {
10140     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
10141   },
10142
10143   /* VEX_LEN_0F38F7_P_1 */
10144   {
10145     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10146   },
10147
10148   /* VEX_LEN_0F38F7_P_2 */
10149   {
10150     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10151   },
10152
10153   /* VEX_LEN_0F38F7_P_3 */
10154   {
10155     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10156   },
10157
10158   /* VEX_LEN_0F3A00_P_2 */
10159   {
10160     { Bad_Opcode },
10161     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10162   },
10163
10164   /* VEX_LEN_0F3A01_P_2 */
10165   {
10166     { Bad_Opcode },
10167     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10168   },
10169
10170   /* VEX_LEN_0F3A06_P_2 */
10171   {
10172     { Bad_Opcode },
10173     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10174   },
10175
10176   /* VEX_LEN_0F3A0A_P_2 */
10177   {
10178     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10179     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10180   },
10181
10182   /* VEX_LEN_0F3A0B_P_2 */
10183   {
10184     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10185     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10186   },
10187
10188   /* VEX_LEN_0F3A14_P_2 */
10189   {
10190     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10191   },
10192
10193   /* VEX_LEN_0F3A15_P_2 */
10194   {
10195     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10196   },
10197
10198   /* VEX_LEN_0F3A16_P_2  */
10199   {
10200     { "vpextrK",        { Edq, XM, Ib }, 0 },
10201   },
10202
10203   /* VEX_LEN_0F3A17_P_2 */
10204   {
10205     { "vextractps",     { Edqd, XM, Ib }, 0 },
10206   },
10207
10208   /* VEX_LEN_0F3A18_P_2 */
10209   {
10210     { Bad_Opcode },
10211     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10212   },
10213
10214   /* VEX_LEN_0F3A19_P_2 */
10215   {
10216     { Bad_Opcode },
10217     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10218   },
10219
10220   /* VEX_LEN_0F3A20_P_2 */
10221   {
10222     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10223   },
10224
10225   /* VEX_LEN_0F3A21_P_2 */
10226   {
10227     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10228   },
10229
10230   /* VEX_LEN_0F3A22_P_2 */
10231   {
10232     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10233   },
10234
10235   /* VEX_LEN_0F3A30_P_2 */
10236   {
10237     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10238   },
10239
10240   /* VEX_LEN_0F3A31_P_2 */
10241   {
10242     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10243   },
10244
10245   /* VEX_LEN_0F3A32_P_2 */
10246   {
10247     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10248   },
10249
10250   /* VEX_LEN_0F3A33_P_2 */
10251   {
10252     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10253   },
10254
10255   /* VEX_LEN_0F3A38_P_2 */
10256   {
10257     { Bad_Opcode },
10258     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10259   },
10260
10261   /* VEX_LEN_0F3A39_P_2 */
10262   {
10263     { Bad_Opcode },
10264     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10265   },
10266
10267   /* VEX_LEN_0F3A41_P_2 */
10268   {
10269     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10270   },
10271
10272   /* VEX_LEN_0F3A44_P_2 */
10273   {
10274     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10275   },
10276
10277   /* VEX_LEN_0F3A46_P_2 */
10278   {
10279     { Bad_Opcode },
10280     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10281   },
10282
10283   /* VEX_LEN_0F3A60_P_2 */
10284   {
10285     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10286   },
10287
10288   /* VEX_LEN_0F3A61_P_2 */
10289   {
10290     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10291   },
10292
10293   /* VEX_LEN_0F3A62_P_2 */
10294   {
10295     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10296   },
10297
10298   /* VEX_LEN_0F3A63_P_2 */
10299   {
10300     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10301   },
10302
10303   /* VEX_LEN_0F3A6A_P_2 */
10304   {
10305     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10306   },
10307
10308   /* VEX_LEN_0F3A6B_P_2 */
10309   {
10310     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10311   },
10312
10313   /* VEX_LEN_0F3A6E_P_2 */
10314   {
10315     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10316   },
10317
10318   /* VEX_LEN_0F3A6F_P_2 */
10319   {
10320     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10321   },
10322
10323   /* VEX_LEN_0F3A7A_P_2 */
10324   {
10325     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10326   },
10327
10328   /* VEX_LEN_0F3A7B_P_2 */
10329   {
10330     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10331   },
10332
10333   /* VEX_LEN_0F3A7E_P_2 */
10334   {
10335     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10336   },
10337
10338   /* VEX_LEN_0F3A7F_P_2 */
10339   {
10340     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10341   },
10342
10343   /* VEX_LEN_0F3ADF_P_2 */
10344   {
10345     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10346   },
10347
10348   /* VEX_LEN_0F3AF0_P_3 */
10349   {
10350     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10351   },
10352
10353   /* VEX_LEN_0FXOP_08_CC */
10354   {
10355      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10356   },
10357
10358   /* VEX_LEN_0FXOP_08_CD */
10359   {
10360      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10361   },
10362
10363   /* VEX_LEN_0FXOP_08_CE */
10364   {
10365      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10366   },
10367
10368   /* VEX_LEN_0FXOP_08_CF */
10369   {
10370      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10371   },
10372
10373   /* VEX_LEN_0FXOP_08_EC */
10374   {
10375      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10376   },
10377
10378   /* VEX_LEN_0FXOP_08_ED */
10379   {
10380      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10381   },
10382
10383   /* VEX_LEN_0FXOP_08_EE */
10384   {
10385      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10386   },
10387
10388   /* VEX_LEN_0FXOP_08_EF */
10389   {
10390      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10391   },
10392
10393   /* VEX_LEN_0FXOP_09_80 */
10394   {
10395     { "vfrczps",        { XM, EXxmm }, 0 },
10396     { "vfrczps",        { XM, EXymmq }, 0 },
10397   },
10398
10399   /* VEX_LEN_0FXOP_09_81 */
10400   {
10401     { "vfrczpd",        { XM, EXxmm }, 0 },
10402     { "vfrczpd",        { XM, EXymmq }, 0 },
10403   },
10404 };
10405
10406 static const struct dis386 vex_w_table[][2] = {
10407   {
10408     /* VEX_W_0F10_P_0 */
10409     { "vmovups",        { XM, EXx }, 0 },
10410   },
10411   {
10412     /* VEX_W_0F10_P_1 */
10413     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10414   },
10415   {
10416     /* VEX_W_0F10_P_2 */
10417     { "vmovupd",        { XM, EXx }, 0 },
10418   },
10419   {
10420     /* VEX_W_0F10_P_3 */
10421     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10422   },
10423   {
10424     /* VEX_W_0F11_P_0 */
10425     { "vmovups",        { EXxS, XM }, 0 },
10426   },
10427   {
10428     /* VEX_W_0F11_P_1 */
10429     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10430   },
10431   {
10432     /* VEX_W_0F11_P_2 */
10433     { "vmovupd",        { EXxS, XM }, 0 },
10434   },
10435   {
10436     /* VEX_W_0F11_P_3 */
10437     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10438   },
10439   {
10440     /* VEX_W_0F12_P_0_M_0 */
10441     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10442   },
10443   {
10444     /* VEX_W_0F12_P_0_M_1 */
10445     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10446   },
10447   {
10448     /* VEX_W_0F12_P_1 */
10449     { "vmovsldup",      { XM, EXx }, 0 },
10450   },
10451   {
10452     /* VEX_W_0F12_P_2 */
10453     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10454   },
10455   {
10456     /* VEX_W_0F12_P_3 */
10457     { "vmovddup",       { XM, EXymmq }, 0 },
10458   },
10459   {
10460     /* VEX_W_0F13_M_0 */
10461     { "vmovlpX",        { EXq, XM }, 0 },
10462   },
10463   {
10464     /* VEX_W_0F14 */
10465     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10466   },
10467   {
10468     /* VEX_W_0F15 */
10469     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10470   },
10471   {
10472     /* VEX_W_0F16_P_0_M_0 */
10473     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10474   },
10475   {
10476     /* VEX_W_0F16_P_0_M_1 */
10477     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10478   },
10479   {
10480     /* VEX_W_0F16_P_1 */
10481     { "vmovshdup",      { XM, EXx }, 0 },
10482   },
10483   {
10484     /* VEX_W_0F16_P_2 */
10485     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10486   },
10487   {
10488     /* VEX_W_0F17_M_0 */
10489     { "vmovhpX",        { EXq, XM }, 0 },
10490   },
10491   {
10492     /* VEX_W_0F28 */
10493     { "vmovapX",        { XM, EXx }, 0 },
10494   },
10495   {
10496     /* VEX_W_0F29 */
10497     { "vmovapX",        { EXxS, XM }, 0 },
10498   },
10499   {
10500     /* VEX_W_0F2B_M_0 */
10501     { "vmovntpX",       { Mx, XM }, 0 },
10502   },
10503   {
10504     /* VEX_W_0F2E_P_0 */
10505     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10506   },
10507   {
10508     /* VEX_W_0F2E_P_2 */
10509     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10510   },
10511   {
10512     /* VEX_W_0F2F_P_0 */
10513     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10514   },
10515   {
10516     /* VEX_W_0F2F_P_2 */
10517     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10518   },
10519   {
10520     /* VEX_W_0F41_P_0_LEN_1 */
10521     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10522     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10523   },
10524   {
10525     /* VEX_W_0F41_P_2_LEN_1 */
10526     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10527     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10528   },
10529   {
10530     /* VEX_W_0F42_P_0_LEN_1 */
10531     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10532     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10533   },
10534   {
10535     /* VEX_W_0F42_P_2_LEN_1 */
10536     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10537     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10538   },
10539   {
10540     /* VEX_W_0F44_P_0_LEN_0 */
10541     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10542     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10543   },
10544   {
10545     /* VEX_W_0F44_P_2_LEN_0 */
10546     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10547     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10548   },
10549   {
10550     /* VEX_W_0F45_P_0_LEN_1 */
10551     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10552     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10553   },
10554   {
10555     /* VEX_W_0F45_P_2_LEN_1 */
10556     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10557     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10558   },
10559   {
10560     /* VEX_W_0F46_P_0_LEN_1 */
10561     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10562     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10563   },
10564   {
10565     /* VEX_W_0F46_P_2_LEN_1 */
10566     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10567     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10568   },
10569   {
10570     /* VEX_W_0F47_P_0_LEN_1 */
10571     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10572     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10573   },
10574   {
10575     /* VEX_W_0F47_P_2_LEN_1 */
10576     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10577     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10578   },
10579   {
10580     /* VEX_W_0F4A_P_0_LEN_1 */
10581     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10582     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10583   },
10584   {
10585     /* VEX_W_0F4A_P_2_LEN_1 */
10586     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10587     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10588   },
10589   {
10590     /* VEX_W_0F4B_P_0_LEN_1 */
10591     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10592     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10593   },
10594   {
10595     /* VEX_W_0F4B_P_2_LEN_1 */
10596     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10597   },
10598   {
10599     /* VEX_W_0F50_M_0 */
10600     { "vmovmskpX",      { Gdq, XS }, 0 },
10601   },
10602   {
10603     /* VEX_W_0F51_P_0 */
10604     { "vsqrtps",        { XM, EXx }, 0 },
10605   },
10606   {
10607     /* VEX_W_0F51_P_1 */
10608     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10609   },
10610   {
10611     /* VEX_W_0F51_P_2  */
10612     { "vsqrtpd",        { XM, EXx }, 0 },
10613   },
10614   {
10615     /* VEX_W_0F51_P_3 */
10616     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10617   },
10618   {
10619     /* VEX_W_0F52_P_0 */
10620     { "vrsqrtps",       { XM, EXx }, 0 },
10621   },
10622   {
10623     /* VEX_W_0F52_P_1 */
10624     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10625   },
10626   {
10627     /* VEX_W_0F53_P_0  */
10628     { "vrcpps",         { XM, EXx }, 0 },
10629   },
10630   {
10631     /* VEX_W_0F53_P_1  */
10632     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10633   },
10634   {
10635     /* VEX_W_0F58_P_0  */
10636     { "vaddps",         { XM, Vex, EXx }, 0 },
10637   },
10638   {
10639     /* VEX_W_0F58_P_1  */
10640     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10641   },
10642   {
10643     /* VEX_W_0F58_P_2  */
10644     { "vaddpd",         { XM, Vex, EXx }, 0 },
10645   },
10646   {
10647     /* VEX_W_0F58_P_3  */
10648     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10649   },
10650   {
10651     /* VEX_W_0F59_P_0  */
10652     { "vmulps",         { XM, Vex, EXx }, 0 },
10653   },
10654   {
10655     /* VEX_W_0F59_P_1  */
10656     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10657   },
10658   {
10659     /* VEX_W_0F59_P_2  */
10660     { "vmulpd",         { XM, Vex, EXx }, 0 },
10661   },
10662   {
10663     /* VEX_W_0F59_P_3  */
10664     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10665   },
10666   {
10667     /* VEX_W_0F5A_P_0  */
10668     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10669   },
10670   {
10671     /* VEX_W_0F5A_P_1  */
10672     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10673   },
10674   {
10675     /* VEX_W_0F5A_P_3  */
10676     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10677   },
10678   {
10679     /* VEX_W_0F5B_P_0  */
10680     { "vcvtdq2ps",      { XM, EXx }, 0 },
10681   },
10682   {
10683     /* VEX_W_0F5B_P_1  */
10684     { "vcvttps2dq",     { XM, EXx }, 0 },
10685   },
10686   {
10687     /* VEX_W_0F5B_P_2  */
10688     { "vcvtps2dq",      { XM, EXx }, 0 },
10689   },
10690   {
10691     /* VEX_W_0F5C_P_0  */
10692     { "vsubps",         { XM, Vex, EXx }, 0 },
10693   },
10694   {
10695     /* VEX_W_0F5C_P_1  */
10696     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10697   },
10698   {
10699     /* VEX_W_0F5C_P_2  */
10700     { "vsubpd",         { XM, Vex, EXx }, 0 },
10701   },
10702   {
10703     /* VEX_W_0F5C_P_3  */
10704     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10705   },
10706   {
10707     /* VEX_W_0F5D_P_0  */
10708     { "vminps",         { XM, Vex, EXx }, 0 },
10709   },
10710   {
10711     /* VEX_W_0F5D_P_1  */
10712     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10713   },
10714   {
10715     /* VEX_W_0F5D_P_2  */
10716     { "vminpd",         { XM, Vex, EXx }, 0 },
10717   },
10718   {
10719     /* VEX_W_0F5D_P_3  */
10720     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10721   },
10722   {
10723     /* VEX_W_0F5E_P_0  */
10724     { "vdivps",         { XM, Vex, EXx }, 0 },
10725   },
10726   {
10727     /* VEX_W_0F5E_P_1  */
10728     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10729   },
10730   {
10731     /* VEX_W_0F5E_P_2  */
10732     { "vdivpd",         { XM, Vex, EXx }, 0 },
10733   },
10734   {
10735     /* VEX_W_0F5E_P_3  */
10736     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10737   },
10738   {
10739     /* VEX_W_0F5F_P_0  */
10740     { "vmaxps",         { XM, Vex, EXx }, 0 },
10741   },
10742   {
10743     /* VEX_W_0F5F_P_1  */
10744     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10745   },
10746   {
10747     /* VEX_W_0F5F_P_2  */
10748     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10749   },
10750   {
10751     /* VEX_W_0F5F_P_3  */
10752     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10753   },
10754   {
10755     /* VEX_W_0F60_P_2  */
10756     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10757   },
10758   {
10759     /* VEX_W_0F61_P_2  */
10760     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10761   },
10762   {
10763     /* VEX_W_0F62_P_2  */
10764     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10765   },
10766   {
10767     /* VEX_W_0F63_P_2  */
10768     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10769   },
10770   {
10771     /* VEX_W_0F64_P_2  */
10772     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10773   },
10774   {
10775     /* VEX_W_0F65_P_2  */
10776     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10777   },
10778   {
10779     /* VEX_W_0F66_P_2  */
10780     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10781   },
10782   {
10783     /* VEX_W_0F67_P_2  */
10784     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10785   },
10786   {
10787     /* VEX_W_0F68_P_2  */
10788     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10789   },
10790   {
10791     /* VEX_W_0F69_P_2  */
10792     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10793   },
10794   {
10795     /* VEX_W_0F6A_P_2  */
10796     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10797   },
10798   {
10799     /* VEX_W_0F6B_P_2  */
10800     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10801   },
10802   {
10803     /* VEX_W_0F6C_P_2  */
10804     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10805   },
10806   {
10807     /* VEX_W_0F6D_P_2  */
10808     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10809   },
10810   {
10811     /* VEX_W_0F6F_P_1  */
10812     { "vmovdqu",        { XM, EXx }, 0 },
10813   },
10814   {
10815     /* VEX_W_0F6F_P_2  */
10816     { "vmovdqa",        { XM, EXx }, 0 },
10817   },
10818   {
10819     /* VEX_W_0F70_P_1 */
10820     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10821   },
10822   {
10823     /* VEX_W_0F70_P_2 */
10824     { "vpshufd",        { XM, EXx, Ib }, 0 },
10825   },
10826   {
10827     /* VEX_W_0F70_P_3 */
10828     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10829   },
10830   {
10831     /* VEX_W_0F71_R_2_P_2  */
10832     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10833   },
10834   {
10835     /* VEX_W_0F71_R_4_P_2  */
10836     { "vpsraw",         { Vex, XS, Ib }, 0 },
10837   },
10838   {
10839     /* VEX_W_0F71_R_6_P_2  */
10840     { "vpsllw",         { Vex, XS, Ib }, 0 },
10841   },
10842   {
10843     /* VEX_W_0F72_R_2_P_2  */
10844     { "vpsrld",         { Vex, XS, Ib }, 0 },
10845   },
10846   {
10847     /* VEX_W_0F72_R_4_P_2  */
10848     { "vpsrad",         { Vex, XS, Ib }, 0 },
10849   },
10850   {
10851     /* VEX_W_0F72_R_6_P_2  */
10852     { "vpslld",         { Vex, XS, Ib }, 0 },
10853   },
10854   {
10855     /* VEX_W_0F73_R_2_P_2  */
10856     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10857   },
10858   {
10859     /* VEX_W_0F73_R_3_P_2  */
10860     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10861   },
10862   {
10863     /* VEX_W_0F73_R_6_P_2  */
10864     { "vpsllq",         { Vex, XS, Ib }, 0 },
10865   },
10866   {
10867     /* VEX_W_0F73_R_7_P_2  */
10868     { "vpslldq",        { Vex, XS, Ib }, 0 },
10869   },
10870   {
10871     /* VEX_W_0F74_P_2 */
10872     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10873   },
10874   {
10875     /* VEX_W_0F75_P_2 */
10876     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10877   },
10878   {
10879     /* VEX_W_0F76_P_2 */
10880     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10881   },
10882   {
10883     /* VEX_W_0F77_P_0 */
10884     { "",               { VZERO }, 0 },
10885   },
10886   {
10887     /* VEX_W_0F7C_P_2 */
10888     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10889   },
10890   {
10891     /* VEX_W_0F7C_P_3 */
10892     { "vhaddps",        { XM, Vex, EXx }, 0 },
10893   },
10894   {
10895     /* VEX_W_0F7D_P_2 */
10896     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10897   },
10898   {
10899     /* VEX_W_0F7D_P_3 */
10900     { "vhsubps",        { XM, Vex, EXx }, 0 },
10901   },
10902   {
10903     /* VEX_W_0F7E_P_1 */
10904     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10905   },
10906   {
10907     /* VEX_W_0F7F_P_1 */
10908     { "vmovdqu",        { EXxS, XM }, 0 },
10909   },
10910   {
10911     /* VEX_W_0F7F_P_2 */
10912     { "vmovdqa",        { EXxS, XM }, 0 },
10913   },
10914   {
10915     /* VEX_W_0F90_P_0_LEN_0 */
10916     { "kmovw",          { MaskG, MaskE }, 0 },
10917     { "kmovq",          { MaskG, MaskE }, 0 },
10918   },
10919   {
10920     /* VEX_W_0F90_P_2_LEN_0 */
10921     { "kmovb",          { MaskG, MaskBDE }, 0 },
10922     { "kmovd",          { MaskG, MaskBDE }, 0 },
10923   },
10924   {
10925     /* VEX_W_0F91_P_0_LEN_0 */
10926     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10927     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10928   },
10929   {
10930     /* VEX_W_0F91_P_2_LEN_0 */
10931     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10932     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10933   },
10934   {
10935     /* VEX_W_0F92_P_0_LEN_0 */
10936     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10937   },
10938   {
10939     /* VEX_W_0F92_P_2_LEN_0 */
10940     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10941   },
10942   {
10943     /* VEX_W_0F92_P_3_LEN_0 */
10944     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10945     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10946   },
10947   {
10948     /* VEX_W_0F93_P_0_LEN_0 */
10949     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10950   },
10951   {
10952     /* VEX_W_0F93_P_2_LEN_0 */
10953     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10954   },
10955   {
10956     /* VEX_W_0F93_P_3_LEN_0 */
10957     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10958     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10959   },
10960   {
10961     /* VEX_W_0F98_P_0_LEN_0 */
10962     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10963     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10964   },
10965   {
10966     /* VEX_W_0F98_P_2_LEN_0 */
10967     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10968     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10969   },
10970   {
10971     /* VEX_W_0F99_P_0_LEN_0 */
10972     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10973     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10974   },
10975   {
10976     /* VEX_W_0F99_P_2_LEN_0 */
10977     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10978     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10979   },
10980   {
10981     /* VEX_W_0FAE_R_2_M_0 */
10982     { "vldmxcsr",       { Md }, 0 },
10983   },
10984   {
10985     /* VEX_W_0FAE_R_3_M_0 */
10986     { "vstmxcsr",       { Md }, 0 },
10987   },
10988   {
10989     /* VEX_W_0FC2_P_0 */
10990     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10991   },
10992   {
10993     /* VEX_W_0FC2_P_1 */
10994     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10995   },
10996   {
10997     /* VEX_W_0FC2_P_2 */
10998     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10999   },
11000   {
11001     /* VEX_W_0FC2_P_3 */
11002     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
11003   },
11004   {
11005     /* VEX_W_0FC4_P_2 */
11006     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
11007   },
11008   {
11009     /* VEX_W_0FC5_P_2 */
11010     { "vpextrw",        { Gdq, XS, Ib }, 0 },
11011   },
11012   {
11013     /* VEX_W_0FD0_P_2 */
11014     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
11015   },
11016   {
11017     /* VEX_W_0FD0_P_3 */
11018     { "vaddsubps",      { XM, Vex, EXx }, 0 },
11019   },
11020   {
11021     /* VEX_W_0FD1_P_2 */
11022     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
11023   },
11024   {
11025     /* VEX_W_0FD2_P_2 */
11026     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
11027   },
11028   {
11029     /* VEX_W_0FD3_P_2 */
11030     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
11031   },
11032   {
11033     /* VEX_W_0FD4_P_2 */
11034     { "vpaddq",         { XM, Vex, EXx }, 0 },
11035   },
11036   {
11037     /* VEX_W_0FD5_P_2 */
11038     { "vpmullw",        { XM, Vex, EXx }, 0 },
11039   },
11040   {
11041     /* VEX_W_0FD6_P_2 */
11042     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
11043   },
11044   {
11045     /* VEX_W_0FD7_P_2_M_1 */
11046     { "vpmovmskb",      { Gdq, XS }, 0 },
11047   },
11048   {
11049     /* VEX_W_0FD8_P_2 */
11050     { "vpsubusb",       { XM, Vex, EXx }, 0 },
11051   },
11052   {
11053     /* VEX_W_0FD9_P_2 */
11054     { "vpsubusw",       { XM, Vex, EXx }, 0 },
11055   },
11056   {
11057     /* VEX_W_0FDA_P_2 */
11058     { "vpminub",        { XM, Vex, EXx }, 0 },
11059   },
11060   {
11061     /* VEX_W_0FDB_P_2 */
11062     { "vpand",          { XM, Vex, EXx }, 0 },
11063   },
11064   {
11065     /* VEX_W_0FDC_P_2 */
11066     { "vpaddusb",       { XM, Vex, EXx }, 0 },
11067   },
11068   {
11069     /* VEX_W_0FDD_P_2 */
11070     { "vpaddusw",       { XM, Vex, EXx }, 0 },
11071   },
11072   {
11073     /* VEX_W_0FDE_P_2 */
11074     { "vpmaxub",        { XM, Vex, EXx }, 0 },
11075   },
11076   {
11077     /* VEX_W_0FDF_P_2 */
11078     { "vpandn",         { XM, Vex, EXx }, 0 },
11079   },
11080   {
11081     /* VEX_W_0FE0_P_2  */
11082     { "vpavgb",         { XM, Vex, EXx }, 0 },
11083   },
11084   {
11085     /* VEX_W_0FE1_P_2  */
11086     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
11087   },
11088   {
11089     /* VEX_W_0FE2_P_2  */
11090     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
11091   },
11092   {
11093     /* VEX_W_0FE3_P_2  */
11094     { "vpavgw",         { XM, Vex, EXx }, 0 },
11095   },
11096   {
11097     /* VEX_W_0FE4_P_2  */
11098     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
11099   },
11100   {
11101     /* VEX_W_0FE5_P_2  */
11102     { "vpmulhw",        { XM, Vex, EXx }, 0 },
11103   },
11104   {
11105     /* VEX_W_0FE6_P_1  */
11106     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
11107   },
11108   {
11109     /* VEX_W_0FE6_P_2  */
11110     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
11111   },
11112   {
11113     /* VEX_W_0FE6_P_3  */
11114     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
11115   },
11116   {
11117     /* VEX_W_0FE7_P_2_M_0 */
11118     { "vmovntdq",       { Mx, XM }, 0 },
11119   },
11120   {
11121     /* VEX_W_0FE8_P_2  */
11122     { "vpsubsb",        { XM, Vex, EXx }, 0 },
11123   },
11124   {
11125     /* VEX_W_0FE9_P_2  */
11126     { "vpsubsw",        { XM, Vex, EXx }, 0 },
11127   },
11128   {
11129     /* VEX_W_0FEA_P_2  */
11130     { "vpminsw",        { XM, Vex, EXx }, 0 },
11131   },
11132   {
11133     /* VEX_W_0FEB_P_2  */
11134     { "vpor",           { XM, Vex, EXx }, 0 },
11135   },
11136   {
11137     /* VEX_W_0FEC_P_2  */
11138     { "vpaddsb",        { XM, Vex, EXx }, 0 },
11139   },
11140   {
11141     /* VEX_W_0FED_P_2  */
11142     { "vpaddsw",        { XM, Vex, EXx }, 0 },
11143   },
11144   {
11145     /* VEX_W_0FEE_P_2  */
11146     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
11147   },
11148   {
11149     /* VEX_W_0FEF_P_2  */
11150     { "vpxor",          { XM, Vex, EXx }, 0 },
11151   },
11152   {
11153     /* VEX_W_0FF0_P_3_M_0 */
11154     { "vlddqu",         { XM, M }, 0 },
11155   },
11156   {
11157     /* VEX_W_0FF1_P_2 */
11158     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11159   },
11160   {
11161     /* VEX_W_0FF2_P_2 */
11162     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11163   },
11164   {
11165     /* VEX_W_0FF3_P_2 */
11166     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11167   },
11168   {
11169     /* VEX_W_0FF4_P_2 */
11170     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11171   },
11172   {
11173     /* VEX_W_0FF5_P_2 */
11174     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11175   },
11176   {
11177     /* VEX_W_0FF6_P_2 */
11178     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11179   },
11180   {
11181     /* VEX_W_0FF7_P_2 */
11182     { "vmaskmovdqu",    { XM, XS }, 0 },
11183   },
11184   {
11185     /* VEX_W_0FF8_P_2 */
11186     { "vpsubb",         { XM, Vex, EXx }, 0 },
11187   },
11188   {
11189     /* VEX_W_0FF9_P_2 */
11190     { "vpsubw",         { XM, Vex, EXx }, 0 },
11191   },
11192   {
11193     /* VEX_W_0FFA_P_2 */
11194     { "vpsubd",         { XM, Vex, EXx }, 0 },
11195   },
11196   {
11197     /* VEX_W_0FFB_P_2 */
11198     { "vpsubq",         { XM, Vex, EXx }, 0 },
11199   },
11200   {
11201     /* VEX_W_0FFC_P_2 */
11202     { "vpaddb",         { XM, Vex, EXx }, 0 },
11203   },
11204   {
11205     /* VEX_W_0FFD_P_2 */
11206     { "vpaddw",         { XM, Vex, EXx }, 0 },
11207   },
11208   {
11209     /* VEX_W_0FFE_P_2 */
11210     { "vpaddd",         { XM, Vex, EXx }, 0 },
11211   },
11212   {
11213     /* VEX_W_0F3800_P_2  */
11214     { "vpshufb",        { XM, Vex, EXx }, 0 },
11215   },
11216   {
11217     /* VEX_W_0F3801_P_2  */
11218     { "vphaddw",        { XM, Vex, EXx }, 0 },
11219   },
11220   {
11221     /* VEX_W_0F3802_P_2  */
11222     { "vphaddd",        { XM, Vex, EXx }, 0 },
11223   },
11224   {
11225     /* VEX_W_0F3803_P_2  */
11226     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11227   },
11228   {
11229     /* VEX_W_0F3804_P_2  */
11230     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11231   },
11232   {
11233     /* VEX_W_0F3805_P_2  */
11234     { "vphsubw",        { XM, Vex, EXx }, 0 },
11235   },
11236   {
11237     /* VEX_W_0F3806_P_2  */
11238     { "vphsubd",        { XM, Vex, EXx }, 0 },
11239   },
11240   {
11241     /* VEX_W_0F3807_P_2  */
11242     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11243   },
11244   {
11245     /* VEX_W_0F3808_P_2  */
11246     { "vpsignb",        { XM, Vex, EXx }, 0 },
11247   },
11248   {
11249     /* VEX_W_0F3809_P_2  */
11250     { "vpsignw",        { XM, Vex, EXx }, 0 },
11251   },
11252   {
11253     /* VEX_W_0F380A_P_2  */
11254     { "vpsignd",        { XM, Vex, EXx }, 0 },
11255   },
11256   {
11257     /* VEX_W_0F380B_P_2  */
11258     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11259   },
11260   {
11261     /* VEX_W_0F380C_P_2  */
11262     { "vpermilps",      { XM, Vex, EXx }, 0 },
11263   },
11264   {
11265     /* VEX_W_0F380D_P_2  */
11266     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11267   },
11268   {
11269     /* VEX_W_0F380E_P_2  */
11270     { "vtestps",        { XM, EXx }, 0 },
11271   },
11272   {
11273     /* VEX_W_0F380F_P_2  */
11274     { "vtestpd",        { XM, EXx }, 0 },
11275   },
11276   {
11277     /* VEX_W_0F3816_P_2  */
11278     { "vpermps",        { XM, Vex, EXx }, 0 },
11279   },
11280   {
11281     /* VEX_W_0F3817_P_2 */
11282     { "vptest",         { XM, EXx }, 0 },
11283   },
11284   {
11285     /* VEX_W_0F3818_P_2 */
11286     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11287   },
11288   {
11289     /* VEX_W_0F3819_P_2 */
11290     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11291   },
11292   {
11293     /* VEX_W_0F381A_P_2_M_0 */
11294     { "vbroadcastf128", { XM, Mxmm }, 0 },
11295   },
11296   {
11297     /* VEX_W_0F381C_P_2 */
11298     { "vpabsb",         { XM, EXx }, 0 },
11299   },
11300   {
11301     /* VEX_W_0F381D_P_2 */
11302     { "vpabsw",         { XM, EXx }, 0 },
11303   },
11304   {
11305     /* VEX_W_0F381E_P_2 */
11306     { "vpabsd",         { XM, EXx }, 0 },
11307   },
11308   {
11309     /* VEX_W_0F3820_P_2 */
11310     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11311   },
11312   {
11313     /* VEX_W_0F3821_P_2 */
11314     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11315   },
11316   {
11317     /* VEX_W_0F3822_P_2 */
11318     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11319   },
11320   {
11321     /* VEX_W_0F3823_P_2 */
11322     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11323   },
11324   {
11325     /* VEX_W_0F3824_P_2 */
11326     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11327   },
11328   {
11329     /* VEX_W_0F3825_P_2 */
11330     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11331   },
11332   {
11333     /* VEX_W_0F3828_P_2 */
11334     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11335   },
11336   {
11337     /* VEX_W_0F3829_P_2 */
11338     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11339   },
11340   {
11341     /* VEX_W_0F382A_P_2_M_0 */
11342     { "vmovntdqa",      { XM, Mx }, 0 },
11343   },
11344   {
11345     /* VEX_W_0F382B_P_2 */
11346     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11347   },
11348   {
11349     /* VEX_W_0F382C_P_2_M_0 */
11350     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11351   },
11352   {
11353     /* VEX_W_0F382D_P_2_M_0 */
11354     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11355   },
11356   {
11357     /* VEX_W_0F382E_P_2_M_0 */
11358     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11359   },
11360   {
11361     /* VEX_W_0F382F_P_2_M_0 */
11362     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11363   },
11364   {
11365     /* VEX_W_0F3830_P_2 */
11366     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11367   },
11368   {
11369     /* VEX_W_0F3831_P_2 */
11370     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11371   },
11372   {
11373     /* VEX_W_0F3832_P_2 */
11374     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11375   },
11376   {
11377     /* VEX_W_0F3833_P_2 */
11378     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11379   },
11380   {
11381     /* VEX_W_0F3834_P_2 */
11382     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11383   },
11384   {
11385     /* VEX_W_0F3835_P_2 */
11386     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11387   },
11388   {
11389     /* VEX_W_0F3836_P_2  */
11390     { "vpermd",         { XM, Vex, EXx }, 0 },
11391   },
11392   {
11393     /* VEX_W_0F3837_P_2 */
11394     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11395   },
11396   {
11397     /* VEX_W_0F3838_P_2 */
11398     { "vpminsb",        { XM, Vex, EXx }, 0 },
11399   },
11400   {
11401     /* VEX_W_0F3839_P_2 */
11402     { "vpminsd",        { XM, Vex, EXx }, 0 },
11403   },
11404   {
11405     /* VEX_W_0F383A_P_2 */
11406     { "vpminuw",        { XM, Vex, EXx }, 0 },
11407   },
11408   {
11409     /* VEX_W_0F383B_P_2 */
11410     { "vpminud",        { XM, Vex, EXx }, 0 },
11411   },
11412   {
11413     /* VEX_W_0F383C_P_2 */
11414     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11415   },
11416   {
11417     /* VEX_W_0F383D_P_2 */
11418     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11419   },
11420   {
11421     /* VEX_W_0F383E_P_2 */
11422     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11423   },
11424   {
11425     /* VEX_W_0F383F_P_2 */
11426     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11427   },
11428   {
11429     /* VEX_W_0F3840_P_2 */
11430     { "vpmulld",        { XM, Vex, EXx }, 0 },
11431   },
11432   {
11433     /* VEX_W_0F3841_P_2 */
11434     { "vphminposuw",    { XM, EXx }, 0 },
11435   },
11436   {
11437     /* VEX_W_0F3846_P_2 */
11438     { "vpsravd",        { XM, Vex, EXx }, 0 },
11439   },
11440   {
11441     /* VEX_W_0F3858_P_2 */
11442     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11443   },
11444   {
11445     /* VEX_W_0F3859_P_2 */
11446     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11447   },
11448   {
11449     /* VEX_W_0F385A_P_2_M_0 */
11450     { "vbroadcasti128", { XM, Mxmm }, 0 },
11451   },
11452   {
11453     /* VEX_W_0F3878_P_2 */
11454     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11455   },
11456   {
11457     /* VEX_W_0F3879_P_2 */
11458     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11459   },
11460   {
11461     /* VEX_W_0F38DB_P_2 */
11462     { "vaesimc",        { XM, EXx }, 0 },
11463   },
11464   {
11465     /* VEX_W_0F38DC_P_2 */
11466     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11467   },
11468   {
11469     /* VEX_W_0F38DD_P_2 */
11470     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11471   },
11472   {
11473     /* VEX_W_0F38DE_P_2 */
11474     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11475   },
11476   {
11477     /* VEX_W_0F38DF_P_2 */
11478     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11479   },
11480   {
11481     /* VEX_W_0F3A00_P_2 */
11482     { Bad_Opcode },
11483     { "vpermq",         { XM, EXx, Ib }, 0 },
11484   },
11485   {
11486     /* VEX_W_0F3A01_P_2 */
11487     { Bad_Opcode },
11488     { "vpermpd",        { XM, EXx, Ib }, 0 },
11489   },
11490   {
11491     /* VEX_W_0F3A02_P_2 */
11492     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11493   },
11494   {
11495     /* VEX_W_0F3A04_P_2 */
11496     { "vpermilps",      { XM, EXx, Ib }, 0 },
11497   },
11498   {
11499     /* VEX_W_0F3A05_P_2 */
11500     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11501   },
11502   {
11503     /* VEX_W_0F3A06_P_2 */
11504     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11505   },
11506   {
11507     /* VEX_W_0F3A08_P_2 */
11508     { "vroundps",       { XM, EXx, Ib }, 0 },
11509   },
11510   {
11511     /* VEX_W_0F3A09_P_2 */
11512     { "vroundpd",       { XM, EXx, Ib }, 0 },
11513   },
11514   {
11515     /* VEX_W_0F3A0A_P_2 */
11516     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11517   },
11518   {
11519     /* VEX_W_0F3A0B_P_2 */
11520     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11521   },
11522   {
11523     /* VEX_W_0F3A0C_P_2 */
11524     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11525   },
11526   {
11527     /* VEX_W_0F3A0D_P_2 */
11528     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11529   },
11530   {
11531     /* VEX_W_0F3A0E_P_2 */
11532     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11533   },
11534   {
11535     /* VEX_W_0F3A0F_P_2 */
11536     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11537   },
11538   {
11539     /* VEX_W_0F3A14_P_2 */
11540     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11541   },
11542   {
11543     /* VEX_W_0F3A15_P_2 */
11544     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11545   },
11546   {
11547     /* VEX_W_0F3A18_P_2 */
11548     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11549   },
11550   {
11551     /* VEX_W_0F3A19_P_2 */
11552     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11553   },
11554   {
11555     /* VEX_W_0F3A20_P_2 */
11556     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11557   },
11558   {
11559     /* VEX_W_0F3A21_P_2 */
11560     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11561   },
11562   {
11563     /* VEX_W_0F3A30_P_2_LEN_0 */
11564     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11565     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11566   },
11567   {
11568     /* VEX_W_0F3A31_P_2_LEN_0 */
11569     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11570     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11571   },
11572   {
11573     /* VEX_W_0F3A32_P_2_LEN_0 */
11574     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11575     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11576   },
11577   {
11578     /* VEX_W_0F3A33_P_2_LEN_0 */
11579     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11580     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11581   },
11582   {
11583     /* VEX_W_0F3A38_P_2 */
11584     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11585   },
11586   {
11587     /* VEX_W_0F3A39_P_2 */
11588     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11589   },
11590   {
11591     /* VEX_W_0F3A40_P_2 */
11592     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11593   },
11594   {
11595     /* VEX_W_0F3A41_P_2 */
11596     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11597   },
11598   {
11599     /* VEX_W_0F3A42_P_2 */
11600     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11601   },
11602   {
11603     /* VEX_W_0F3A44_P_2 */
11604     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11605   },
11606   {
11607     /* VEX_W_0F3A46_P_2 */
11608     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11609   },
11610   {
11611     /* VEX_W_0F3A48_P_2 */
11612     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11613     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11614   },
11615   {
11616     /* VEX_W_0F3A49_P_2 */
11617     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11618     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11619   },
11620   {
11621     /* VEX_W_0F3A4A_P_2 */
11622     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11623   },
11624   {
11625     /* VEX_W_0F3A4B_P_2 */
11626     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11627   },
11628   {
11629     /* VEX_W_0F3A4C_P_2 */
11630     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11631   },
11632   {
11633     /* VEX_W_0F3A60_P_2 */
11634     { "vpcmpestrm",     { XM, EXx, Ib }, 0 },
11635   },
11636   {
11637     /* VEX_W_0F3A61_P_2 */
11638     { "vpcmpestri",     { XM, EXx, Ib }, 0 },
11639   },
11640   {
11641     /* VEX_W_0F3A62_P_2 */
11642     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11643   },
11644   {
11645     /* VEX_W_0F3A63_P_2 */
11646     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11647   },
11648   {
11649     /* VEX_W_0F3ADF_P_2 */
11650     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11651   },
11652 #define NEED_VEX_W_TABLE
11653 #include "i386-dis-evex.h"
11654 #undef NEED_VEX_W_TABLE
11655 };
11656
11657 static const struct dis386 mod_table[][2] = {
11658   {
11659     /* MOD_8D */
11660     { "leaS",           { Gv, M }, 0 },
11661   },
11662   {
11663     /* MOD_C6_REG_7 */
11664     { Bad_Opcode },
11665     { RM_TABLE (RM_C6_REG_7) },
11666   },
11667   {
11668     /* MOD_C7_REG_7 */
11669     { Bad_Opcode },
11670     { RM_TABLE (RM_C7_REG_7) },
11671   },
11672   {
11673     /* MOD_FF_REG_3 */
11674     { "Jcall^", { indirEp }, 0 },
11675   },
11676   {
11677     /* MOD_FF_REG_5 */
11678     { "Jjmp^", { indirEp }, 0 },
11679   },
11680   {
11681     /* MOD_0F01_REG_0 */
11682     { X86_64_TABLE (X86_64_0F01_REG_0) },
11683     { RM_TABLE (RM_0F01_REG_0) },
11684   },
11685   {
11686     /* MOD_0F01_REG_1 */
11687     { X86_64_TABLE (X86_64_0F01_REG_1) },
11688     { RM_TABLE (RM_0F01_REG_1) },
11689   },
11690   {
11691     /* MOD_0F01_REG_2 */
11692     { X86_64_TABLE (X86_64_0F01_REG_2) },
11693     { RM_TABLE (RM_0F01_REG_2) },
11694   },
11695   {
11696     /* MOD_0F01_REG_3 */
11697     { X86_64_TABLE (X86_64_0F01_REG_3) },
11698     { RM_TABLE (RM_0F01_REG_3) },
11699   },
11700   {
11701     /* MOD_0F01_REG_5 */
11702     { Bad_Opcode },
11703     { RM_TABLE (RM_0F01_REG_5) },
11704   },
11705   {
11706     /* MOD_0F01_REG_7 */
11707     { "invlpg",         { Mb }, 0 },
11708     { RM_TABLE (RM_0F01_REG_7) },
11709   },
11710   {
11711     /* MOD_0F12_PREFIX_0 */
11712     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11713     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11714   },
11715   {
11716     /* MOD_0F13 */
11717     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11718   },
11719   {
11720     /* MOD_0F16_PREFIX_0 */
11721     { "movhps",         { XM, EXq }, 0 },
11722     { "movlhps",        { XM, EXq }, 0 },
11723   },
11724   {
11725     /* MOD_0F17 */
11726     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11727   },
11728   {
11729     /* MOD_0F18_REG_0 */
11730     { "prefetchnta",    { Mb }, 0 },
11731   },
11732   {
11733     /* MOD_0F18_REG_1 */
11734     { "prefetcht0",     { Mb }, 0 },
11735   },
11736   {
11737     /* MOD_0F18_REG_2 */
11738     { "prefetcht1",     { Mb }, 0 },
11739   },
11740   {
11741     /* MOD_0F18_REG_3 */
11742     { "prefetcht2",     { Mb }, 0 },
11743   },
11744   {
11745     /* MOD_0F18_REG_4 */
11746     { "nop/reserved",   { Mb }, 0 },
11747   },
11748   {
11749     /* MOD_0F18_REG_5 */
11750     { "nop/reserved",   { Mb }, 0 },
11751   },
11752   {
11753     /* MOD_0F18_REG_6 */
11754     { "nop/reserved",   { Mb }, 0 },
11755   },
11756   {
11757     /* MOD_0F18_REG_7 */
11758     { "nop/reserved",   { Mb }, 0 },
11759   },
11760   {
11761     /* MOD_0F1A_PREFIX_0 */
11762     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11763     { "nopQ",           { Ev }, 0 },
11764   },
11765   {
11766     /* MOD_0F1B_PREFIX_0 */
11767     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11768     { "nopQ",           { Ev }, 0 },
11769   },
11770   {
11771     /* MOD_0F1B_PREFIX_1 */
11772     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11773     { "nopQ",           { Ev }, 0 },
11774   },
11775   {
11776     /* MOD_0F24 */
11777     { Bad_Opcode },
11778     { "movL",           { Rd, Td }, 0 },
11779   },
11780   {
11781     /* MOD_0F26 */
11782     { Bad_Opcode },
11783     { "movL",           { Td, Rd }, 0 },
11784   },
11785   {
11786     /* MOD_0F2B_PREFIX_0 */
11787     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11788   },
11789   {
11790     /* MOD_0F2B_PREFIX_1 */
11791     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11792   },
11793   {
11794     /* MOD_0F2B_PREFIX_2 */
11795     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11796   },
11797   {
11798     /* MOD_0F2B_PREFIX_3 */
11799     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11800   },
11801   {
11802     /* MOD_0F51 */
11803     { Bad_Opcode },
11804     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11805   },
11806   {
11807     /* MOD_0F71_REG_2 */
11808     { Bad_Opcode },
11809     { "psrlw",          { MS, Ib }, 0 },
11810   },
11811   {
11812     /* MOD_0F71_REG_4 */
11813     { Bad_Opcode },
11814     { "psraw",          { MS, Ib }, 0 },
11815   },
11816   {
11817     /* MOD_0F71_REG_6 */
11818     { Bad_Opcode },
11819     { "psllw",          { MS, Ib }, 0 },
11820   },
11821   {
11822     /* MOD_0F72_REG_2 */
11823     { Bad_Opcode },
11824     { "psrld",          { MS, Ib }, 0 },
11825   },
11826   {
11827     /* MOD_0F72_REG_4 */
11828     { Bad_Opcode },
11829     { "psrad",          { MS, Ib }, 0 },
11830   },
11831   {
11832     /* MOD_0F72_REG_6 */
11833     { Bad_Opcode },
11834     { "pslld",          { MS, Ib }, 0 },
11835   },
11836   {
11837     /* MOD_0F73_REG_2 */
11838     { Bad_Opcode },
11839     { "psrlq",          { MS, Ib }, 0 },
11840   },
11841   {
11842     /* MOD_0F73_REG_3 */
11843     { Bad_Opcode },
11844     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11845   },
11846   {
11847     /* MOD_0F73_REG_6 */
11848     { Bad_Opcode },
11849     { "psllq",          { MS, Ib }, 0 },
11850   },
11851   {
11852     /* MOD_0F73_REG_7 */
11853     { Bad_Opcode },
11854     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11855   },
11856   {
11857     /* MOD_0FAE_REG_0 */
11858     { "fxsave",         { FXSAVE }, 0 },
11859     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11860   },
11861   {
11862     /* MOD_0FAE_REG_1 */
11863     { "fxrstor",        { FXSAVE }, 0 },
11864     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11865   },
11866   {
11867     /* MOD_0FAE_REG_2 */
11868     { "ldmxcsr",        { Md }, 0 },
11869     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11870   },
11871   {
11872     /* MOD_0FAE_REG_3 */
11873     { "stmxcsr",        { Md }, 0 },
11874     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11875   },
11876   {
11877     /* MOD_0FAE_REG_4 */
11878     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11879     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11880   },
11881   {
11882     /* MOD_0FAE_REG_5 */
11883     { "xrstor",         { FXSAVE }, 0 },
11884     { RM_TABLE (RM_0FAE_REG_5) },
11885   },
11886   {
11887     /* MOD_0FAE_REG_6 */
11888     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11889     { RM_TABLE (RM_0FAE_REG_6) },
11890   },
11891   {
11892     /* MOD_0FAE_REG_7 */
11893     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11894     { RM_TABLE (RM_0FAE_REG_7) },
11895   },
11896   {
11897     /* MOD_0FB2 */
11898     { "lssS",           { Gv, Mp }, 0 },
11899   },
11900   {
11901     /* MOD_0FB4 */
11902     { "lfsS",           { Gv, Mp }, 0 },
11903   },
11904   {
11905     /* MOD_0FB5 */
11906     { "lgsS",           { Gv, Mp }, 0 },
11907   },
11908   {
11909     /* MOD_0FC3 */
11910     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11911   },
11912   {
11913     /* MOD_0FC7_REG_3 */
11914     { "xrstors",        { FXSAVE }, 0 },
11915   },
11916   {
11917     /* MOD_0FC7_REG_4 */
11918     { "xsavec",         { FXSAVE }, 0 },
11919   },
11920   {
11921     /* MOD_0FC7_REG_5 */
11922     { "xsaves",         { FXSAVE }, 0 },
11923   },
11924   {
11925     /* MOD_0FC7_REG_6 */
11926     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11927     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11928   },
11929   {
11930     /* MOD_0FC7_REG_7 */
11931     { "vmptrst",        { Mq }, 0 },
11932     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11933   },
11934   {
11935     /* MOD_0FD7 */
11936     { Bad_Opcode },
11937     { "pmovmskb",       { Gdq, MS }, 0 },
11938   },
11939   {
11940     /* MOD_0FE7_PREFIX_2 */
11941     { "movntdq",        { Mx, XM }, 0 },
11942   },
11943   {
11944     /* MOD_0FF0_PREFIX_3 */
11945     { "lddqu",          { XM, M }, 0 },
11946   },
11947   {
11948     /* MOD_0F382A_PREFIX_2 */
11949     { "movntdqa",       { XM, Mx }, 0 },
11950   },
11951   {
11952     /* MOD_62_32BIT */
11953     { "bound{S|}",      { Gv, Ma }, 0 },
11954     { EVEX_TABLE (EVEX_0F) },
11955   },
11956   {
11957     /* MOD_C4_32BIT */
11958     { "lesS",           { Gv, Mp }, 0 },
11959     { VEX_C4_TABLE (VEX_0F) },
11960   },
11961   {
11962     /* MOD_C5_32BIT */
11963     { "ldsS",           { Gv, Mp }, 0 },
11964     { VEX_C5_TABLE (VEX_0F) },
11965   },
11966   {
11967     /* MOD_VEX_0F12_PREFIX_0 */
11968     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11969     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11970   },
11971   {
11972     /* MOD_VEX_0F13 */
11973     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11974   },
11975   {
11976     /* MOD_VEX_0F16_PREFIX_0 */
11977     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11978     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11979   },
11980   {
11981     /* MOD_VEX_0F17 */
11982     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11983   },
11984   {
11985     /* MOD_VEX_0F2B */
11986     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11987   },
11988   {
11989     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11990     { Bad_Opcode },
11991     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11992   },
11993   {
11994     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11995     { Bad_Opcode },
11996     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11997   },
11998   {
11999     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
12000     { Bad_Opcode },
12001     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
12002   },
12003   {
12004     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
12005     { Bad_Opcode },
12006     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
12007   },
12008   {
12009     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
12010     { Bad_Opcode },
12011     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
12012   },
12013   {
12014     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
12015     { Bad_Opcode },
12016     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
12017   },
12018   {
12019     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
12020     { Bad_Opcode },
12021     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
12022   },
12023   {
12024     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
12025     { Bad_Opcode },
12026     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
12027   },
12028   {
12029     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
12030     { Bad_Opcode },
12031     { "knotw",          { MaskG, MaskR }, 0 },
12032   },
12033   {
12034     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
12035     { Bad_Opcode },
12036     { "knotq",          { MaskG, MaskR }, 0 },
12037   },
12038   {
12039     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
12040     { Bad_Opcode },
12041     { "knotb",          { MaskG, MaskR }, 0 },
12042   },
12043   {
12044     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
12045     { Bad_Opcode },
12046     { "knotd",          { MaskG, MaskR }, 0 },
12047   },
12048   {
12049     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
12050     { Bad_Opcode },
12051     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
12052   },
12053   {
12054     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
12055     { Bad_Opcode },
12056     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
12057   },
12058   {
12059     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
12060     { Bad_Opcode },
12061     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
12062   },
12063   {
12064     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
12065     { Bad_Opcode },
12066     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
12067   },
12068  {
12069     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
12070     { Bad_Opcode },
12071     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
12072   },
12073   {
12074     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
12075     { Bad_Opcode },
12076     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
12077   },
12078   {
12079     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
12080     { Bad_Opcode },
12081     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
12082   },
12083   {
12084     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
12085     { Bad_Opcode },
12086     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
12087   },
12088   {
12089     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12090     { Bad_Opcode },
12091     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
12092   },
12093   {
12094     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12095     { Bad_Opcode },
12096     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
12097   },
12098   {
12099     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12100     { Bad_Opcode },
12101     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
12102   },
12103   {
12104     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12105     { Bad_Opcode },
12106     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
12107   },
12108   {
12109     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12110     { Bad_Opcode },
12111     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
12112   },
12113   {
12114     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12115     { Bad_Opcode },
12116     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
12117   },
12118   {
12119     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12120     { Bad_Opcode },
12121     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
12122   },
12123   {
12124     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12125     { Bad_Opcode },
12126     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
12127   },
12128   {
12129     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12130     { Bad_Opcode },
12131     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
12132   },
12133   {
12134     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12135     { Bad_Opcode },
12136     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
12137   },
12138   {
12139     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12140     { Bad_Opcode },
12141     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
12142   },
12143   {
12144     /* MOD_VEX_0F50 */
12145     { Bad_Opcode },
12146     { VEX_W_TABLE (VEX_W_0F50_M_0) },
12147   },
12148   {
12149     /* MOD_VEX_0F71_REG_2 */
12150     { Bad_Opcode },
12151     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
12152   },
12153   {
12154     /* MOD_VEX_0F71_REG_4 */
12155     { Bad_Opcode },
12156     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12157   },
12158   {
12159     /* MOD_VEX_0F71_REG_6 */
12160     { Bad_Opcode },
12161     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12162   },
12163   {
12164     /* MOD_VEX_0F72_REG_2 */
12165     { Bad_Opcode },
12166     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12167   },
12168   {
12169     /* MOD_VEX_0F72_REG_4 */
12170     { Bad_Opcode },
12171     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12172   },
12173   {
12174     /* MOD_VEX_0F72_REG_6 */
12175     { Bad_Opcode },
12176     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12177   },
12178   {
12179     /* MOD_VEX_0F73_REG_2 */
12180     { Bad_Opcode },
12181     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12182   },
12183   {
12184     /* MOD_VEX_0F73_REG_3 */
12185     { Bad_Opcode },
12186     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12187   },
12188   {
12189     /* MOD_VEX_0F73_REG_6 */
12190     { Bad_Opcode },
12191     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12192   },
12193   {
12194     /* MOD_VEX_0F73_REG_7 */
12195     { Bad_Opcode },
12196     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12197   },
12198   {
12199     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12200     { "kmovw",          { Ew, MaskG }, 0 },
12201     { Bad_Opcode },
12202   },
12203   {
12204     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12205     { "kmovq",          { Eq, MaskG }, 0 },
12206     { Bad_Opcode },
12207   },
12208   {
12209     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12210     { "kmovb",          { Eb, MaskG }, 0 },
12211     { Bad_Opcode },
12212   },
12213   {
12214     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12215     { "kmovd",          { Ed, MaskG }, 0 },
12216     { Bad_Opcode },
12217   },
12218   {
12219     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12220     { Bad_Opcode },
12221     { "kmovw",          { MaskG, Rdq }, 0 },
12222   },
12223   {
12224     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12225     { Bad_Opcode },
12226     { "kmovb",          { MaskG, Rdq }, 0 },
12227   },
12228   {
12229     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12230     { Bad_Opcode },
12231     { "kmovd",          { MaskG, Rdq }, 0 },
12232   },
12233   {
12234     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12235     { Bad_Opcode },
12236     { "kmovq",          { MaskG, Rdq }, 0 },
12237   },
12238   {
12239     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12240     { Bad_Opcode },
12241     { "kmovw",          { Gdq, MaskR }, 0 },
12242   },
12243   {
12244     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12245     { Bad_Opcode },
12246     { "kmovb",          { Gdq, MaskR }, 0 },
12247   },
12248   {
12249     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12250     { Bad_Opcode },
12251     { "kmovd",          { Gdq, MaskR }, 0 },
12252   },
12253   {
12254     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12255     { Bad_Opcode },
12256     { "kmovq",          { Gdq, MaskR }, 0 },
12257   },
12258   {
12259     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12260     { Bad_Opcode },
12261     { "kortestw", { MaskG, MaskR }, 0 },
12262   },
12263   {
12264     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12265     { Bad_Opcode },
12266     { "kortestq", { MaskG, MaskR }, 0 },
12267   },
12268   {
12269     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12270     { Bad_Opcode },
12271     { "kortestb", { MaskG, MaskR }, 0 },
12272   },
12273   {
12274     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12275     { Bad_Opcode },
12276     { "kortestd", { MaskG, MaskR }, 0 },
12277   },
12278   {
12279     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12280     { Bad_Opcode },
12281     { "ktestw", { MaskG, MaskR }, 0 },
12282   },
12283   {
12284     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12285     { Bad_Opcode },
12286     { "ktestq", { MaskG, MaskR }, 0 },
12287   },
12288   {
12289     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12290     { Bad_Opcode },
12291     { "ktestb", { MaskG, MaskR }, 0 },
12292   },
12293   {
12294     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12295     { Bad_Opcode },
12296     { "ktestd", { MaskG, MaskR }, 0 },
12297   },
12298   {
12299     /* MOD_VEX_0FAE_REG_2 */
12300     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12301   },
12302   {
12303     /* MOD_VEX_0FAE_REG_3 */
12304     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12305   },
12306   {
12307     /* MOD_VEX_0FD7_PREFIX_2 */
12308     { Bad_Opcode },
12309     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12310   },
12311   {
12312     /* MOD_VEX_0FE7_PREFIX_2 */
12313     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12314   },
12315   {
12316     /* MOD_VEX_0FF0_PREFIX_3 */
12317     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12318   },
12319   {
12320     /* MOD_VEX_0F381A_PREFIX_2 */
12321     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12322   },
12323   {
12324     /* MOD_VEX_0F382A_PREFIX_2 */
12325     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12326   },
12327   {
12328     /* MOD_VEX_0F382C_PREFIX_2 */
12329     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12330   },
12331   {
12332     /* MOD_VEX_0F382D_PREFIX_2 */
12333     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12334   },
12335   {
12336     /* MOD_VEX_0F382E_PREFIX_2 */
12337     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12338   },
12339   {
12340     /* MOD_VEX_0F382F_PREFIX_2 */
12341     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12342   },
12343   {
12344     /* MOD_VEX_0F385A_PREFIX_2 */
12345     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12346   },
12347   {
12348     /* MOD_VEX_0F388C_PREFIX_2 */
12349     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12350   },
12351   {
12352     /* MOD_VEX_0F388E_PREFIX_2 */
12353     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12354   },
12355   {
12356     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12357     { Bad_Opcode },
12358     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12359   },
12360   {
12361     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12362     { Bad_Opcode },
12363     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12364   },
12365   {
12366     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12367     { Bad_Opcode },
12368     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12369   },
12370   {
12371     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12372     { Bad_Opcode },
12373     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12374   },
12375   {
12376     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12377     { Bad_Opcode },
12378     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12379   },
12380   {
12381     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12382     { Bad_Opcode },
12383     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12384   },
12385   {
12386     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12387     { Bad_Opcode },
12388     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12389   },
12390   {
12391     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12392     { Bad_Opcode },
12393     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12394   },
12395 #define NEED_MOD_TABLE
12396 #include "i386-dis-evex.h"
12397 #undef NEED_MOD_TABLE
12398 };
12399
12400 static const struct dis386 rm_table[][8] = {
12401   {
12402     /* RM_C6_REG_7 */
12403     { "xabort",         { Skip_MODRM, Ib }, 0 },
12404   },
12405   {
12406     /* RM_C7_REG_7 */
12407     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12408   },
12409   {
12410     /* RM_0F01_REG_0 */
12411     { Bad_Opcode },
12412     { "vmcall",         { Skip_MODRM }, 0 },
12413     { "vmlaunch",       { Skip_MODRM }, 0 },
12414     { "vmresume",       { Skip_MODRM }, 0 },
12415     { "vmxoff",         { Skip_MODRM }, 0 },
12416   },
12417   {
12418     /* RM_0F01_REG_1 */
12419     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12420     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12421     { "clac",           { Skip_MODRM }, 0 },
12422     { "stac",           { Skip_MODRM }, 0 },
12423     { Bad_Opcode },
12424     { Bad_Opcode },
12425     { Bad_Opcode },
12426     { "encls",          { Skip_MODRM }, 0 },
12427   },
12428   {
12429     /* RM_0F01_REG_2 */
12430     { "xgetbv",         { Skip_MODRM }, 0 },
12431     { "xsetbv",         { Skip_MODRM }, 0 },
12432     { Bad_Opcode },
12433     { Bad_Opcode },
12434     { "vmfunc",         { Skip_MODRM }, 0 },
12435     { "xend",           { Skip_MODRM }, 0 },
12436     { "xtest",          { Skip_MODRM }, 0 },
12437     { "enclu",          { Skip_MODRM }, 0 },
12438   },
12439   {
12440     /* RM_0F01_REG_3 */
12441     { "vmrun",          { Skip_MODRM }, 0 },
12442     { "vmmcall",        { Skip_MODRM }, 0 },
12443     { "vmload",         { Skip_MODRM }, 0 },
12444     { "vmsave",         { Skip_MODRM }, 0 },
12445     { "stgi",           { Skip_MODRM }, 0 },
12446     { "clgi",           { Skip_MODRM }, 0 },
12447     { "skinit",         { Skip_MODRM }, 0 },
12448     { "invlpga",        { Skip_MODRM }, 0 },
12449   },
12450   {
12451     /* RM_0F01_REG_5 */
12452     { Bad_Opcode },
12453     { Bad_Opcode },
12454     { Bad_Opcode },
12455     { Bad_Opcode },
12456     { Bad_Opcode },
12457     { Bad_Opcode },
12458     { "rdpkru",         { Skip_MODRM }, 0 },
12459     { "wrpkru",         { Skip_MODRM }, 0 },
12460   },
12461   {
12462     /* RM_0F01_REG_7 */
12463     { "swapgs",         { Skip_MODRM }, 0  },
12464     { "rdtscp",         { Skip_MODRM }, 0  },
12465     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12466     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12467     { "clzero",         { Skip_MODRM }, 0  },
12468   },
12469   {
12470     /* RM_0FAE_REG_5 */
12471     { "lfence",         { Skip_MODRM }, 0 },
12472   },
12473   {
12474     /* RM_0FAE_REG_6 */
12475     { "mfence",         { Skip_MODRM }, 0 },
12476   },
12477   {
12478     /* RM_0FAE_REG_7 */
12479     { "sfence",         { Skip_MODRM }, 0 },
12480
12481   },
12482 };
12483
12484 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12485
12486 /* We use the high bit to indicate different name for the same
12487    prefix.  */
12488 #define REP_PREFIX      (0xf3 | 0x100)
12489 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12490 #define XRELEASE_PREFIX (0xf3 | 0x400)
12491 #define BND_PREFIX      (0xf2 | 0x400)
12492
12493 static int
12494 ckprefix (void)
12495 {
12496   int newrex, i, length;
12497   rex = 0;
12498   rex_ignored = 0;
12499   prefixes = 0;
12500   used_prefixes = 0;
12501   rex_used = 0;
12502   last_lock_prefix = -1;
12503   last_repz_prefix = -1;
12504   last_repnz_prefix = -1;
12505   last_data_prefix = -1;
12506   last_addr_prefix = -1;
12507   last_rex_prefix = -1;
12508   last_seg_prefix = -1;
12509   fwait_prefix = -1;
12510   active_seg_prefix = 0;
12511   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12512     all_prefixes[i] = 0;
12513   i = 0;
12514   length = 0;
12515   /* The maximum instruction length is 15bytes.  */
12516   while (length < MAX_CODE_LENGTH - 1)
12517     {
12518       FETCH_DATA (the_info, codep + 1);
12519       newrex = 0;
12520       switch (*codep)
12521         {
12522         /* REX prefixes family.  */
12523         case 0x40:
12524         case 0x41:
12525         case 0x42:
12526         case 0x43:
12527         case 0x44:
12528         case 0x45:
12529         case 0x46:
12530         case 0x47:
12531         case 0x48:
12532         case 0x49:
12533         case 0x4a:
12534         case 0x4b:
12535         case 0x4c:
12536         case 0x4d:
12537         case 0x4e:
12538         case 0x4f:
12539           if (address_mode == mode_64bit)
12540             newrex = *codep;
12541           else
12542             return 1;
12543           last_rex_prefix = i;
12544           break;
12545         case 0xf3:
12546           prefixes |= PREFIX_REPZ;
12547           last_repz_prefix = i;
12548           break;
12549         case 0xf2:
12550           prefixes |= PREFIX_REPNZ;
12551           last_repnz_prefix = i;
12552           break;
12553         case 0xf0:
12554           prefixes |= PREFIX_LOCK;
12555           last_lock_prefix = i;
12556           break;
12557         case 0x2e:
12558           prefixes |= PREFIX_CS;
12559           last_seg_prefix = i;
12560           active_seg_prefix = PREFIX_CS;
12561           break;
12562         case 0x36:
12563           prefixes |= PREFIX_SS;
12564           last_seg_prefix = i;
12565           active_seg_prefix = PREFIX_SS;
12566           break;
12567         case 0x3e:
12568           prefixes |= PREFIX_DS;
12569           last_seg_prefix = i;
12570           active_seg_prefix = PREFIX_DS;
12571           break;
12572         case 0x26:
12573           prefixes |= PREFIX_ES;
12574           last_seg_prefix = i;
12575           active_seg_prefix = PREFIX_ES;
12576           break;
12577         case 0x64:
12578           prefixes |= PREFIX_FS;
12579           last_seg_prefix = i;
12580           active_seg_prefix = PREFIX_FS;
12581           break;
12582         case 0x65:
12583           prefixes |= PREFIX_GS;
12584           last_seg_prefix = i;
12585           active_seg_prefix = PREFIX_GS;
12586           break;
12587         case 0x66:
12588           prefixes |= PREFIX_DATA;
12589           last_data_prefix = i;
12590           break;
12591         case 0x67:
12592           prefixes |= PREFIX_ADDR;
12593           last_addr_prefix = i;
12594           break;
12595         case FWAIT_OPCODE:
12596           /* fwait is really an instruction.  If there are prefixes
12597              before the fwait, they belong to the fwait, *not* to the
12598              following instruction.  */
12599           fwait_prefix = i;
12600           if (prefixes || rex)
12601             {
12602               prefixes |= PREFIX_FWAIT;
12603               codep++;
12604               /* This ensures that the previous REX prefixes are noticed
12605                  as unused prefixes, as in the return case below.  */
12606               rex_used = rex;
12607               return 1;
12608             }
12609           prefixes = PREFIX_FWAIT;
12610           break;
12611         default:
12612           return 1;
12613         }
12614       /* Rex is ignored when followed by another prefix.  */
12615       if (rex)
12616         {
12617           rex_used = rex;
12618           return 1;
12619         }
12620       if (*codep != FWAIT_OPCODE)
12621         all_prefixes[i++] = *codep;
12622       rex = newrex;
12623       codep++;
12624       length++;
12625     }
12626   return 0;
12627 }
12628
12629 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12630    prefix byte.  */
12631
12632 static const char *
12633 prefix_name (int pref, int sizeflag)
12634 {
12635   static const char *rexes [16] =
12636     {
12637       "rex",            /* 0x40 */
12638       "rex.B",          /* 0x41 */
12639       "rex.X",          /* 0x42 */
12640       "rex.XB",         /* 0x43 */
12641       "rex.R",          /* 0x44 */
12642       "rex.RB",         /* 0x45 */
12643       "rex.RX",         /* 0x46 */
12644       "rex.RXB",        /* 0x47 */
12645       "rex.W",          /* 0x48 */
12646       "rex.WB",         /* 0x49 */
12647       "rex.WX",         /* 0x4a */
12648       "rex.WXB",        /* 0x4b */
12649       "rex.WR",         /* 0x4c */
12650       "rex.WRB",        /* 0x4d */
12651       "rex.WRX",        /* 0x4e */
12652       "rex.WRXB",       /* 0x4f */
12653     };
12654
12655   switch (pref)
12656     {
12657     /* REX prefixes family.  */
12658     case 0x40:
12659     case 0x41:
12660     case 0x42:
12661     case 0x43:
12662     case 0x44:
12663     case 0x45:
12664     case 0x46:
12665     case 0x47:
12666     case 0x48:
12667     case 0x49:
12668     case 0x4a:
12669     case 0x4b:
12670     case 0x4c:
12671     case 0x4d:
12672     case 0x4e:
12673     case 0x4f:
12674       return rexes [pref - 0x40];
12675     case 0xf3:
12676       return "repz";
12677     case 0xf2:
12678       return "repnz";
12679     case 0xf0:
12680       return "lock";
12681     case 0x2e:
12682       return "cs";
12683     case 0x36:
12684       return "ss";
12685     case 0x3e:
12686       return "ds";
12687     case 0x26:
12688       return "es";
12689     case 0x64:
12690       return "fs";
12691     case 0x65:
12692       return "gs";
12693     case 0x66:
12694       return (sizeflag & DFLAG) ? "data16" : "data32";
12695     case 0x67:
12696       if (address_mode == mode_64bit)
12697         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12698       else
12699         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12700     case FWAIT_OPCODE:
12701       return "fwait";
12702     case REP_PREFIX:
12703       return "rep";
12704     case XACQUIRE_PREFIX:
12705       return "xacquire";
12706     case XRELEASE_PREFIX:
12707       return "xrelease";
12708     case BND_PREFIX:
12709       return "bnd";
12710     default:
12711       return NULL;
12712     }
12713 }
12714
12715 static char op_out[MAX_OPERANDS][100];
12716 static int op_ad, op_index[MAX_OPERANDS];
12717 static int two_source_ops;
12718 static bfd_vma op_address[MAX_OPERANDS];
12719 static bfd_vma op_riprel[MAX_OPERANDS];
12720 static bfd_vma start_pc;
12721
12722 /*
12723  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12724  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12725  *   section of the "Virtual 8086 Mode" chapter.)
12726  * 'pc' should be the address of this instruction, it will
12727  *   be used to print the target address if this is a relative jump or call
12728  * The function returns the length of this instruction in bytes.
12729  */
12730
12731 static char intel_syntax;
12732 static char intel_mnemonic = !SYSV386_COMPAT;
12733 static char open_char;
12734 static char close_char;
12735 static char separator_char;
12736 static char scale_char;
12737
12738 enum x86_64_isa
12739 {
12740   amd64 = 0,
12741   intel64
12742 };
12743
12744 static enum x86_64_isa isa64;
12745
12746 /* Here for backwards compatibility.  When gdb stops using
12747    print_insn_i386_att and print_insn_i386_intel these functions can
12748    disappear, and print_insn_i386 be merged into print_insn.  */
12749 int
12750 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12751 {
12752   intel_syntax = 0;
12753
12754   return print_insn (pc, info);
12755 }
12756
12757 int
12758 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12759 {
12760   intel_syntax = 1;
12761
12762   return print_insn (pc, info);
12763 }
12764
12765 int
12766 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12767 {
12768   intel_syntax = -1;
12769
12770   return print_insn (pc, info);
12771 }
12772
12773 void
12774 print_i386_disassembler_options (FILE *stream)
12775 {
12776   fprintf (stream, _("\n\
12777 The following i386/x86-64 specific disassembler options are supported for use\n\
12778 with the -M switch (multiple options should be separated by commas):\n"));
12779
12780   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12781   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12782   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12783   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12784   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12785   fprintf (stream, _("  att-mnemonic\n"
12786                      "              Display instruction in AT&T mnemonic\n"));
12787   fprintf (stream, _("  intel-mnemonic\n"
12788                      "              Display instruction in Intel mnemonic\n"));
12789   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12790   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12791   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12792   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12793   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12794   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12795   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12796   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12797 }
12798
12799 /* Bad opcode.  */
12800 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12801
12802 /* Get a pointer to struct dis386 with a valid name.  */
12803
12804 static const struct dis386 *
12805 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12806 {
12807   int vindex, vex_table_index;
12808
12809   if (dp->name != NULL)
12810     return dp;
12811
12812   switch (dp->op[0].bytemode)
12813     {
12814     case USE_REG_TABLE:
12815       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12816       break;
12817
12818     case USE_MOD_TABLE:
12819       vindex = modrm.mod == 0x3 ? 1 : 0;
12820       dp = &mod_table[dp->op[1].bytemode][vindex];
12821       break;
12822
12823     case USE_RM_TABLE:
12824       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12825       break;
12826
12827     case USE_PREFIX_TABLE:
12828       if (need_vex)
12829         {
12830           /* The prefix in VEX is implicit.  */
12831           switch (vex.prefix)
12832             {
12833             case 0:
12834               vindex = 0;
12835               break;
12836             case REPE_PREFIX_OPCODE:
12837               vindex = 1;
12838               break;
12839             case DATA_PREFIX_OPCODE:
12840               vindex = 2;
12841               break;
12842             case REPNE_PREFIX_OPCODE:
12843               vindex = 3;
12844               break;
12845             default:
12846               abort ();
12847               break;
12848             }
12849         }
12850       else
12851         {
12852           int last_prefix = -1;
12853           int prefix = 0;
12854           vindex = 0;
12855           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12856              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12857              last one wins.  */
12858           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12859             {
12860               if (last_repz_prefix > last_repnz_prefix)
12861                 {
12862                   vindex = 1;
12863                   prefix = PREFIX_REPZ;
12864                   last_prefix = last_repz_prefix;
12865                 }
12866               else
12867                 {
12868                   vindex = 3;
12869                   prefix = PREFIX_REPNZ;
12870                   last_prefix = last_repnz_prefix;
12871                 }
12872
12873               /* Check if prefix should be ignored.  */
12874               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12875                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12876                    & prefix) != 0)
12877                 vindex = 0;
12878             }
12879
12880           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12881             {
12882               vindex = 2;
12883               prefix = PREFIX_DATA;
12884               last_prefix = last_data_prefix;
12885             }
12886
12887           if (vindex != 0)
12888             {
12889               used_prefixes |= prefix;
12890               all_prefixes[last_prefix] = 0;
12891             }
12892         }
12893       dp = &prefix_table[dp->op[1].bytemode][vindex];
12894       break;
12895
12896     case USE_X86_64_TABLE:
12897       vindex = address_mode == mode_64bit ? 1 : 0;
12898       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12899       break;
12900
12901     case USE_3BYTE_TABLE:
12902       FETCH_DATA (info, codep + 2);
12903       vindex = *codep++;
12904       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12905       end_codep = codep;
12906       modrm.mod = (*codep >> 6) & 3;
12907       modrm.reg = (*codep >> 3) & 7;
12908       modrm.rm = *codep & 7;
12909       break;
12910
12911     case USE_VEX_LEN_TABLE:
12912       if (!need_vex)
12913         abort ();
12914
12915       switch (vex.length)
12916         {
12917         case 128:
12918           vindex = 0;
12919           break;
12920         case 256:
12921           vindex = 1;
12922           break;
12923         default:
12924           abort ();
12925           break;
12926         }
12927
12928       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12929       break;
12930
12931     case USE_XOP_8F_TABLE:
12932       FETCH_DATA (info, codep + 3);
12933       /* All bits in the REX prefix are ignored.  */
12934       rex_ignored = rex;
12935       rex = ~(*codep >> 5) & 0x7;
12936
12937       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12938       switch ((*codep & 0x1f))
12939         {
12940         default:
12941           dp = &bad_opcode;
12942           return dp;
12943         case 0x8:
12944           vex_table_index = XOP_08;
12945           break;
12946         case 0x9:
12947           vex_table_index = XOP_09;
12948           break;
12949         case 0xa:
12950           vex_table_index = XOP_0A;
12951           break;
12952         }
12953       codep++;
12954       vex.w = *codep & 0x80;
12955       if (vex.w && address_mode == mode_64bit)
12956         rex |= REX_W;
12957
12958       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12959       if (address_mode != mode_64bit
12960           && vex.register_specifier > 0x7)
12961         {
12962           dp = &bad_opcode;
12963           return dp;
12964         }
12965
12966       vex.length = (*codep & 0x4) ? 256 : 128;
12967       switch ((*codep & 0x3))
12968         {
12969         case 0:
12970           vex.prefix = 0;
12971           break;
12972         case 1:
12973           vex.prefix = DATA_PREFIX_OPCODE;
12974           break;
12975         case 2:
12976           vex.prefix = REPE_PREFIX_OPCODE;
12977           break;
12978         case 3:
12979           vex.prefix = REPNE_PREFIX_OPCODE;
12980           break;
12981         }
12982       need_vex = 1;
12983       need_vex_reg = 1;
12984       codep++;
12985       vindex = *codep++;
12986       dp = &xop_table[vex_table_index][vindex];
12987
12988       end_codep = codep;
12989       FETCH_DATA (info, codep + 1);
12990       modrm.mod = (*codep >> 6) & 3;
12991       modrm.reg = (*codep >> 3) & 7;
12992       modrm.rm = *codep & 7;
12993       break;
12994
12995     case USE_VEX_C4_TABLE:
12996       /* VEX prefix.  */
12997       FETCH_DATA (info, codep + 3);
12998       /* All bits in the REX prefix are ignored.  */
12999       rex_ignored = rex;
13000       rex = ~(*codep >> 5) & 0x7;
13001       switch ((*codep & 0x1f))
13002         {
13003         default:
13004           dp = &bad_opcode;
13005           return dp;
13006         case 0x1:
13007           vex_table_index = VEX_0F;
13008           break;
13009         case 0x2:
13010           vex_table_index = VEX_0F38;
13011           break;
13012         case 0x3:
13013           vex_table_index = VEX_0F3A;
13014           break;
13015         }
13016       codep++;
13017       vex.w = *codep & 0x80;
13018       if (address_mode == mode_64bit)
13019         {
13020           if (vex.w)
13021             rex |= REX_W;
13022           vex.register_specifier = (~(*codep >> 3)) & 0xf;
13023         }
13024       else
13025         {
13026           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
13027              is ignored, other REX bits are 0 and the highest bit in
13028              VEX.vvvv is also ignored.  */
13029           rex = 0;
13030           vex.register_specifier = (~(*codep >> 3)) & 0x7;
13031         }
13032       vex.length = (*codep & 0x4) ? 256 : 128;
13033       switch ((*codep & 0x3))
13034         {
13035         case 0:
13036           vex.prefix = 0;
13037           break;
13038         case 1:
13039           vex.prefix = DATA_PREFIX_OPCODE;
13040           break;
13041         case 2:
13042           vex.prefix = REPE_PREFIX_OPCODE;
13043           break;
13044         case 3:
13045           vex.prefix = REPNE_PREFIX_OPCODE;
13046           break;
13047         }
13048       need_vex = 1;
13049       need_vex_reg = 1;
13050       codep++;
13051       vindex = *codep++;
13052       dp = &vex_table[vex_table_index][vindex];
13053       end_codep = codep;
13054       /* There is no MODRM byte for VEX [82|77].  */
13055       if (vindex != 0x77 && vindex != 0x82)
13056         {
13057           FETCH_DATA (info, codep + 1);
13058           modrm.mod = (*codep >> 6) & 3;
13059           modrm.reg = (*codep >> 3) & 7;
13060           modrm.rm = *codep & 7;
13061         }
13062       break;
13063
13064     case USE_VEX_C5_TABLE:
13065       /* VEX prefix.  */
13066       FETCH_DATA (info, codep + 2);
13067       /* All bits in the REX prefix are ignored.  */
13068       rex_ignored = rex;
13069       rex = (*codep & 0x80) ? 0 : REX_R;
13070
13071       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
13072          VEX.vvvv is 1.  */
13073       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13074       vex.w = 0;
13075       vex.length = (*codep & 0x4) ? 256 : 128;
13076       switch ((*codep & 0x3))
13077         {
13078         case 0:
13079           vex.prefix = 0;
13080           break;
13081         case 1:
13082           vex.prefix = DATA_PREFIX_OPCODE;
13083           break;
13084         case 2:
13085           vex.prefix = REPE_PREFIX_OPCODE;
13086           break;
13087         case 3:
13088           vex.prefix = REPNE_PREFIX_OPCODE;
13089           break;
13090         }
13091       need_vex = 1;
13092       need_vex_reg = 1;
13093       codep++;
13094       vindex = *codep++;
13095       dp = &vex_table[dp->op[1].bytemode][vindex];
13096       end_codep = codep;
13097       /* There is no MODRM byte for VEX [82|77].  */
13098       if (vindex != 0x77 && vindex != 0x82)
13099         {
13100           FETCH_DATA (info, codep + 1);
13101           modrm.mod = (*codep >> 6) & 3;
13102           modrm.reg = (*codep >> 3) & 7;
13103           modrm.rm = *codep & 7;
13104         }
13105       break;
13106
13107     case USE_VEX_W_TABLE:
13108       if (!need_vex)
13109         abort ();
13110
13111       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
13112       break;
13113
13114     case USE_EVEX_TABLE:
13115       two_source_ops = 0;
13116       /* EVEX prefix.  */
13117       vex.evex = 1;
13118       FETCH_DATA (info, codep + 4);
13119       /* All bits in the REX prefix are ignored.  */
13120       rex_ignored = rex;
13121       /* The first byte after 0x62.  */
13122       rex = ~(*codep >> 5) & 0x7;
13123       vex.r = *codep & 0x10;
13124       switch ((*codep & 0xf))
13125         {
13126         default:
13127           return &bad_opcode;
13128         case 0x1:
13129           vex_table_index = EVEX_0F;
13130           break;
13131         case 0x2:
13132           vex_table_index = EVEX_0F38;
13133           break;
13134         case 0x3:
13135           vex_table_index = EVEX_0F3A;
13136           break;
13137         }
13138
13139       /* The second byte after 0x62.  */
13140       codep++;
13141       vex.w = *codep & 0x80;
13142       if (vex.w && address_mode == mode_64bit)
13143         rex |= REX_W;
13144
13145       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13146       if (address_mode != mode_64bit)
13147         {
13148           /* In 16/32-bit mode silently ignore following bits.  */
13149           rex &= ~REX_B;
13150           vex.r = 1;
13151           vex.v = 1;
13152           vex.register_specifier &= 0x7;
13153         }
13154
13155       /* The U bit.  */
13156       if (!(*codep & 0x4))
13157         return &bad_opcode;
13158
13159       switch ((*codep & 0x3))
13160         {
13161         case 0:
13162           vex.prefix = 0;
13163           break;
13164         case 1:
13165           vex.prefix = DATA_PREFIX_OPCODE;
13166           break;
13167         case 2:
13168           vex.prefix = REPE_PREFIX_OPCODE;
13169           break;
13170         case 3:
13171           vex.prefix = REPNE_PREFIX_OPCODE;
13172           break;
13173         }
13174
13175       /* The third byte after 0x62.  */
13176       codep++;
13177
13178       /* Remember the static rounding bits.  */
13179       vex.ll = (*codep >> 5) & 3;
13180       vex.b = (*codep & 0x10) != 0;
13181
13182       vex.v = *codep & 0x8;
13183       vex.mask_register_specifier = *codep & 0x7;
13184       vex.zeroing = *codep & 0x80;
13185
13186       need_vex = 1;
13187       need_vex_reg = 1;
13188       codep++;
13189       vindex = *codep++;
13190       dp = &evex_table[vex_table_index][vindex];
13191       end_codep = codep;
13192       FETCH_DATA (info, codep + 1);
13193       modrm.mod = (*codep >> 6) & 3;
13194       modrm.reg = (*codep >> 3) & 7;
13195       modrm.rm = *codep & 7;
13196
13197       /* Set vector length.  */
13198       if (modrm.mod == 3 && vex.b)
13199         vex.length = 512;
13200       else
13201         {
13202           switch (vex.ll)
13203             {
13204             case 0x0:
13205               vex.length = 128;
13206               break;
13207             case 0x1:
13208               vex.length = 256;
13209               break;
13210             case 0x2:
13211               vex.length = 512;
13212               break;
13213             default:
13214               return &bad_opcode;
13215             }
13216         }
13217       break;
13218
13219     case 0:
13220       dp = &bad_opcode;
13221       break;
13222
13223     default:
13224       abort ();
13225     }
13226
13227   if (dp->name != NULL)
13228     return dp;
13229   else
13230     return get_valid_dis386 (dp, info);
13231 }
13232
13233 static void
13234 get_sib (disassemble_info *info, int sizeflag)
13235 {
13236   /* If modrm.mod == 3, operand must be register.  */
13237   if (need_modrm
13238       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13239       && modrm.mod != 3
13240       && modrm.rm == 4)
13241     {
13242       FETCH_DATA (info, codep + 2);
13243       sib.index = (codep [1] >> 3) & 7;
13244       sib.scale = (codep [1] >> 6) & 3;
13245       sib.base = codep [1] & 7;
13246     }
13247 }
13248
13249 static int
13250 print_insn (bfd_vma pc, disassemble_info *info)
13251 {
13252   const struct dis386 *dp;
13253   int i;
13254   char *op_txt[MAX_OPERANDS];
13255   int needcomma;
13256   int sizeflag, orig_sizeflag;
13257   const char *p;
13258   struct dis_private priv;
13259   int prefix_length;
13260
13261   priv.orig_sizeflag = AFLAG | DFLAG;
13262   if ((info->mach & bfd_mach_i386_i386) != 0)
13263     address_mode = mode_32bit;
13264   else if (info->mach == bfd_mach_i386_i8086)
13265     {
13266       address_mode = mode_16bit;
13267       priv.orig_sizeflag = 0;
13268     }
13269   else
13270     address_mode = mode_64bit;
13271
13272   if (intel_syntax == (char) -1)
13273     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13274
13275   for (p = info->disassembler_options; p != NULL; )
13276     {
13277       if (CONST_STRNEQ (p, "amd64"))
13278         isa64 = amd64;
13279       else if (CONST_STRNEQ (p, "intel64"))
13280         isa64 = intel64;
13281       else if (CONST_STRNEQ (p, "x86-64"))
13282         {
13283           address_mode = mode_64bit;
13284           priv.orig_sizeflag = AFLAG | DFLAG;
13285         }
13286       else if (CONST_STRNEQ (p, "i386"))
13287         {
13288           address_mode = mode_32bit;
13289           priv.orig_sizeflag = AFLAG | DFLAG;
13290         }
13291       else if (CONST_STRNEQ (p, "i8086"))
13292         {
13293           address_mode = mode_16bit;
13294           priv.orig_sizeflag = 0;
13295         }
13296       else if (CONST_STRNEQ (p, "intel"))
13297         {
13298           intel_syntax = 1;
13299           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13300             intel_mnemonic = 1;
13301         }
13302       else if (CONST_STRNEQ (p, "att"))
13303         {
13304           intel_syntax = 0;
13305           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13306             intel_mnemonic = 0;
13307         }
13308       else if (CONST_STRNEQ (p, "addr"))
13309         {
13310           if (address_mode == mode_64bit)
13311             {
13312               if (p[4] == '3' && p[5] == '2')
13313                 priv.orig_sizeflag &= ~AFLAG;
13314               else if (p[4] == '6' && p[5] == '4')
13315                 priv.orig_sizeflag |= AFLAG;
13316             }
13317           else
13318             {
13319               if (p[4] == '1' && p[5] == '6')
13320                 priv.orig_sizeflag &= ~AFLAG;
13321               else if (p[4] == '3' && p[5] == '2')
13322                 priv.orig_sizeflag |= AFLAG;
13323             }
13324         }
13325       else if (CONST_STRNEQ (p, "data"))
13326         {
13327           if (p[4] == '1' && p[5] == '6')
13328             priv.orig_sizeflag &= ~DFLAG;
13329           else if (p[4] == '3' && p[5] == '2')
13330             priv.orig_sizeflag |= DFLAG;
13331         }
13332       else if (CONST_STRNEQ (p, "suffix"))
13333         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13334
13335       p = strchr (p, ',');
13336       if (p != NULL)
13337         p++;
13338     }
13339
13340   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13341     {
13342       (*info->fprintf_func) (info->stream,
13343                              _("64-bit address is disabled"));
13344       return -1;
13345     }
13346
13347   if (intel_syntax)
13348     {
13349       names64 = intel_names64;
13350       names32 = intel_names32;
13351       names16 = intel_names16;
13352       names8 = intel_names8;
13353       names8rex = intel_names8rex;
13354       names_seg = intel_names_seg;
13355       names_mm = intel_names_mm;
13356       names_bnd = intel_names_bnd;
13357       names_xmm = intel_names_xmm;
13358       names_ymm = intel_names_ymm;
13359       names_zmm = intel_names_zmm;
13360       index64 = intel_index64;
13361       index32 = intel_index32;
13362       names_mask = intel_names_mask;
13363       index16 = intel_index16;
13364       open_char = '[';
13365       close_char = ']';
13366       separator_char = '+';
13367       scale_char = '*';
13368     }
13369   else
13370     {
13371       names64 = att_names64;
13372       names32 = att_names32;
13373       names16 = att_names16;
13374       names8 = att_names8;
13375       names8rex = att_names8rex;
13376       names_seg = att_names_seg;
13377       names_mm = att_names_mm;
13378       names_bnd = att_names_bnd;
13379       names_xmm = att_names_xmm;
13380       names_ymm = att_names_ymm;
13381       names_zmm = att_names_zmm;
13382       index64 = att_index64;
13383       index32 = att_index32;
13384       names_mask = att_names_mask;
13385       index16 = att_index16;
13386       open_char = '(';
13387       close_char =  ')';
13388       separator_char = ',';
13389       scale_char = ',';
13390     }
13391
13392   /* The output looks better if we put 7 bytes on a line, since that
13393      puts most long word instructions on a single line.  Use 8 bytes
13394      for Intel L1OM.  */
13395   if ((info->mach & bfd_mach_l1om) != 0)
13396     info->bytes_per_line = 8;
13397   else
13398     info->bytes_per_line = 7;
13399
13400   info->private_data = &priv;
13401   priv.max_fetched = priv.the_buffer;
13402   priv.insn_start = pc;
13403
13404   obuf[0] = 0;
13405   for (i = 0; i < MAX_OPERANDS; ++i)
13406     {
13407       op_out[i][0] = 0;
13408       op_index[i] = -1;
13409     }
13410
13411   the_info = info;
13412   start_pc = pc;
13413   start_codep = priv.the_buffer;
13414   codep = priv.the_buffer;
13415
13416   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13417     {
13418       const char *name;
13419
13420       /* Getting here means we tried for data but didn't get it.  That
13421          means we have an incomplete instruction of some sort.  Just
13422          print the first byte as a prefix or a .byte pseudo-op.  */
13423       if (codep > priv.the_buffer)
13424         {
13425           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13426           if (name != NULL)
13427             (*info->fprintf_func) (info->stream, "%s", name);
13428           else
13429             {
13430               /* Just print the first byte as a .byte instruction.  */
13431               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13432                                      (unsigned int) priv.the_buffer[0]);
13433             }
13434
13435           return 1;
13436         }
13437
13438       return -1;
13439     }
13440
13441   obufp = obuf;
13442   sizeflag = priv.orig_sizeflag;
13443
13444   if (!ckprefix () || rex_used)
13445     {
13446       /* Too many prefixes or unused REX prefixes.  */
13447       for (i = 0;
13448            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13449            i++)
13450         (*info->fprintf_func) (info->stream, "%s%s",
13451                                i == 0 ? "" : " ",
13452                                prefix_name (all_prefixes[i], sizeflag));
13453       return i;
13454     }
13455
13456   insn_codep = codep;
13457
13458   FETCH_DATA (info, codep + 1);
13459   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13460
13461   if (((prefixes & PREFIX_FWAIT)
13462        && ((*codep < 0xd8) || (*codep > 0xdf))))
13463     {
13464       /* Handle prefixes before fwait.  */
13465       for (i = 0; i < fwait_prefix && all_prefixes[i];
13466            i++)
13467         (*info->fprintf_func) (info->stream, "%s ",
13468                                prefix_name (all_prefixes[i], sizeflag));
13469       (*info->fprintf_func) (info->stream, "fwait");
13470       return i + 1;
13471     }
13472
13473   if (*codep == 0x0f)
13474     {
13475       unsigned char threebyte;
13476
13477       codep++;
13478       FETCH_DATA (info, codep + 1);
13479       threebyte = *codep;
13480       dp = &dis386_twobyte[threebyte];
13481       need_modrm = twobyte_has_modrm[*codep];
13482       codep++;
13483     }
13484   else
13485     {
13486       dp = &dis386[*codep];
13487       need_modrm = onebyte_has_modrm[*codep];
13488       codep++;
13489     }
13490
13491   /* Save sizeflag for printing the extra prefixes later before updating
13492      it for mnemonic and operand processing.  The prefix names depend
13493      only on the address mode.  */
13494   orig_sizeflag = sizeflag;
13495   if (prefixes & PREFIX_ADDR)
13496     sizeflag ^= AFLAG;
13497   if ((prefixes & PREFIX_DATA))
13498     sizeflag ^= DFLAG;
13499
13500   end_codep = codep;
13501   if (need_modrm)
13502     {
13503       FETCH_DATA (info, codep + 1);
13504       modrm.mod = (*codep >> 6) & 3;
13505       modrm.reg = (*codep >> 3) & 7;
13506       modrm.rm = *codep & 7;
13507     }
13508
13509   need_vex = 0;
13510   need_vex_reg = 0;
13511   vex_w_done = 0;
13512   vex.evex = 0;
13513
13514   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13515     {
13516       get_sib (info, sizeflag);
13517       dofloat (sizeflag);
13518     }
13519   else
13520     {
13521       dp = get_valid_dis386 (dp, info);
13522       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13523         {
13524           get_sib (info, sizeflag);
13525           for (i = 0; i < MAX_OPERANDS; ++i)
13526             {
13527               obufp = op_out[i];
13528               op_ad = MAX_OPERANDS - 1 - i;
13529               if (dp->op[i].rtn)
13530                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13531               /* For EVEX instruction after the last operand masking
13532                  should be printed.  */
13533               if (i == 0 && vex.evex)
13534                 {
13535                   /* Don't print {%k0}.  */
13536                   if (vex.mask_register_specifier)
13537                     {
13538                       oappend ("{");
13539                       oappend (names_mask[vex.mask_register_specifier]);
13540                       oappend ("}");
13541                     }
13542                   if (vex.zeroing)
13543                     oappend ("{z}");
13544                 }
13545             }
13546         }
13547     }
13548
13549   /* Check if the REX prefix is used.  */
13550   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13551     all_prefixes[last_rex_prefix] = 0;
13552
13553   /* Check if the SEG prefix is used.  */
13554   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13555                    | PREFIX_FS | PREFIX_GS)) != 0
13556       && (used_prefixes & active_seg_prefix) != 0)
13557     all_prefixes[last_seg_prefix] = 0;
13558
13559   /* Check if the ADDR prefix is used.  */
13560   if ((prefixes & PREFIX_ADDR) != 0
13561       && (used_prefixes & PREFIX_ADDR) != 0)
13562     all_prefixes[last_addr_prefix] = 0;
13563
13564   /* Check if the DATA prefix is used.  */
13565   if ((prefixes & PREFIX_DATA) != 0
13566       && (used_prefixes & PREFIX_DATA) != 0)
13567     all_prefixes[last_data_prefix] = 0;
13568
13569   /* Print the extra prefixes.  */
13570   prefix_length = 0;
13571   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13572     if (all_prefixes[i])
13573       {
13574         const char *name;
13575         name = prefix_name (all_prefixes[i], orig_sizeflag);
13576         if (name == NULL)
13577           abort ();
13578         prefix_length += strlen (name) + 1;
13579         (*info->fprintf_func) (info->stream, "%s ", name);
13580       }
13581
13582   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13583      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13584      used by putop and MMX/SSE operand and may be overriden by the
13585      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13586      separately.  */
13587   if (dp->prefix_requirement == PREFIX_OPCODE
13588       && dp != &bad_opcode
13589       && (((prefixes
13590             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13591            && (used_prefixes
13592                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13593           || ((((prefixes
13594                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13595                 == PREFIX_DATA)
13596                && (used_prefixes & PREFIX_DATA) == 0))))
13597     {
13598       (*info->fprintf_func) (info->stream, "(bad)");
13599       return end_codep - priv.the_buffer;
13600     }
13601
13602   /* Check maximum code length.  */
13603   if ((codep - start_codep) > MAX_CODE_LENGTH)
13604     {
13605       (*info->fprintf_func) (info->stream, "(bad)");
13606       return MAX_CODE_LENGTH;
13607     }
13608
13609   obufp = mnemonicendp;
13610   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13611     oappend (" ");
13612   oappend (" ");
13613   (*info->fprintf_func) (info->stream, "%s", obuf);
13614
13615   /* The enter and bound instructions are printed with operands in the same
13616      order as the intel book; everything else is printed in reverse order.  */
13617   if (intel_syntax || two_source_ops)
13618     {
13619       bfd_vma riprel;
13620
13621       for (i = 0; i < MAX_OPERANDS; ++i)
13622         op_txt[i] = op_out[i];
13623
13624       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13625           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13626         {
13627           op_txt[2] = op_out[3];
13628           op_txt[3] = op_out[2];
13629         }
13630
13631       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13632         {
13633           op_ad = op_index[i];
13634           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13635           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13636           riprel = op_riprel[i];
13637           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13638           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13639         }
13640     }
13641   else
13642     {
13643       for (i = 0; i < MAX_OPERANDS; ++i)
13644         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13645     }
13646
13647   needcomma = 0;
13648   for (i = 0; i < MAX_OPERANDS; ++i)
13649     if (*op_txt[i])
13650       {
13651         if (needcomma)
13652           (*info->fprintf_func) (info->stream, ",");
13653         if (op_index[i] != -1 && !op_riprel[i])
13654           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13655         else
13656           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13657         needcomma = 1;
13658       }
13659
13660   for (i = 0; i < MAX_OPERANDS; i++)
13661     if (op_index[i] != -1 && op_riprel[i])
13662       {
13663         (*info->fprintf_func) (info->stream, "        # ");
13664         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13665                                                 + op_address[op_index[i]]), info);
13666         break;
13667       }
13668   return codep - priv.the_buffer;
13669 }
13670
13671 static const char *float_mem[] = {
13672   /* d8 */
13673   "fadd{s|}",
13674   "fmul{s|}",
13675   "fcom{s|}",
13676   "fcomp{s|}",
13677   "fsub{s|}",
13678   "fsubr{s|}",
13679   "fdiv{s|}",
13680   "fdivr{s|}",
13681   /* d9 */
13682   "fld{s|}",
13683   "(bad)",
13684   "fst{s|}",
13685   "fstp{s|}",
13686   "fldenvIC",
13687   "fldcw",
13688   "fNstenvIC",
13689   "fNstcw",
13690   /* da */
13691   "fiadd{l|}",
13692   "fimul{l|}",
13693   "ficom{l|}",
13694   "ficomp{l|}",
13695   "fisub{l|}",
13696   "fisubr{l|}",
13697   "fidiv{l|}",
13698   "fidivr{l|}",
13699   /* db */
13700   "fild{l|}",
13701   "fisttp{l|}",
13702   "fist{l|}",
13703   "fistp{l|}",
13704   "(bad)",
13705   "fld{t||t|}",
13706   "(bad)",
13707   "fstp{t||t|}",
13708   /* dc */
13709   "fadd{l|}",
13710   "fmul{l|}",
13711   "fcom{l|}",
13712   "fcomp{l|}",
13713   "fsub{l|}",
13714   "fsubr{l|}",
13715   "fdiv{l|}",
13716   "fdivr{l|}",
13717   /* dd */
13718   "fld{l|}",
13719   "fisttp{ll|}",
13720   "fst{l||}",
13721   "fstp{l|}",
13722   "frstorIC",
13723   "(bad)",
13724   "fNsaveIC",
13725   "fNstsw",
13726   /* de */
13727   "fiadd",
13728   "fimul",
13729   "ficom",
13730   "ficomp",
13731   "fisub",
13732   "fisubr",
13733   "fidiv",
13734   "fidivr",
13735   /* df */
13736   "fild",
13737   "fisttp",
13738   "fist",
13739   "fistp",
13740   "fbld",
13741   "fild{ll|}",
13742   "fbstp",
13743   "fistp{ll|}",
13744 };
13745
13746 static const unsigned char float_mem_mode[] = {
13747   /* d8 */
13748   d_mode,
13749   d_mode,
13750   d_mode,
13751   d_mode,
13752   d_mode,
13753   d_mode,
13754   d_mode,
13755   d_mode,
13756   /* d9 */
13757   d_mode,
13758   0,
13759   d_mode,
13760   d_mode,
13761   0,
13762   w_mode,
13763   0,
13764   w_mode,
13765   /* da */
13766   d_mode,
13767   d_mode,
13768   d_mode,
13769   d_mode,
13770   d_mode,
13771   d_mode,
13772   d_mode,
13773   d_mode,
13774   /* db */
13775   d_mode,
13776   d_mode,
13777   d_mode,
13778   d_mode,
13779   0,
13780   t_mode,
13781   0,
13782   t_mode,
13783   /* dc */
13784   q_mode,
13785   q_mode,
13786   q_mode,
13787   q_mode,
13788   q_mode,
13789   q_mode,
13790   q_mode,
13791   q_mode,
13792   /* dd */
13793   q_mode,
13794   q_mode,
13795   q_mode,
13796   q_mode,
13797   0,
13798   0,
13799   0,
13800   w_mode,
13801   /* de */
13802   w_mode,
13803   w_mode,
13804   w_mode,
13805   w_mode,
13806   w_mode,
13807   w_mode,
13808   w_mode,
13809   w_mode,
13810   /* df */
13811   w_mode,
13812   w_mode,
13813   w_mode,
13814   w_mode,
13815   t_mode,
13816   q_mode,
13817   t_mode,
13818   q_mode
13819 };
13820
13821 #define ST { OP_ST, 0 }
13822 #define STi { OP_STi, 0 }
13823
13824 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13825 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13826 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13827 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13828 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13829 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13830 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13831 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13832 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13833
13834 static const struct dis386 float_reg[][8] = {
13835   /* d8 */
13836   {
13837     { "fadd",   { ST, STi }, 0 },
13838     { "fmul",   { ST, STi }, 0 },
13839     { "fcom",   { STi }, 0 },
13840     { "fcomp",  { STi }, 0 },
13841     { "fsub",   { ST, STi }, 0 },
13842     { "fsubr",  { ST, STi }, 0 },
13843     { "fdiv",   { ST, STi }, 0 },
13844     { "fdivr",  { ST, STi }, 0 },
13845   },
13846   /* d9 */
13847   {
13848     { "fld",    { STi }, 0 },
13849     { "fxch",   { STi }, 0 },
13850     { FGRPd9_2 },
13851     { Bad_Opcode },
13852     { FGRPd9_4 },
13853     { FGRPd9_5 },
13854     { FGRPd9_6 },
13855     { FGRPd9_7 },
13856   },
13857   /* da */
13858   {
13859     { "fcmovb", { ST, STi }, 0 },
13860     { "fcmove", { ST, STi }, 0 },
13861     { "fcmovbe",{ ST, STi }, 0 },
13862     { "fcmovu", { ST, STi }, 0 },
13863     { Bad_Opcode },
13864     { FGRPda_5 },
13865     { Bad_Opcode },
13866     { Bad_Opcode },
13867   },
13868   /* db */
13869   {
13870     { "fcmovnb",{ ST, STi }, 0 },
13871     { "fcmovne",{ ST, STi }, 0 },
13872     { "fcmovnbe",{ ST, STi }, 0 },
13873     { "fcmovnu",{ ST, STi }, 0 },
13874     { FGRPdb_4 },
13875     { "fucomi", { ST, STi }, 0 },
13876     { "fcomi",  { ST, STi }, 0 },
13877     { Bad_Opcode },
13878   },
13879   /* dc */
13880   {
13881     { "fadd",   { STi, ST }, 0 },
13882     { "fmul",   { STi, ST }, 0 },
13883     { Bad_Opcode },
13884     { Bad_Opcode },
13885     { "fsub!M", { STi, ST }, 0 },
13886     { "fsubM",  { STi, ST }, 0 },
13887     { "fdiv!M", { STi, ST }, 0 },
13888     { "fdivM",  { STi, ST }, 0 },
13889   },
13890   /* dd */
13891   {
13892     { "ffree",  { STi }, 0 },
13893     { Bad_Opcode },
13894     { "fst",    { STi }, 0 },
13895     { "fstp",   { STi }, 0 },
13896     { "fucom",  { STi }, 0 },
13897     { "fucomp", { STi }, 0 },
13898     { Bad_Opcode },
13899     { Bad_Opcode },
13900   },
13901   /* de */
13902   {
13903     { "faddp",  { STi, ST }, 0 },
13904     { "fmulp",  { STi, ST }, 0 },
13905     { Bad_Opcode },
13906     { FGRPde_3 },
13907     { "fsub!Mp", { STi, ST }, 0 },
13908     { "fsubMp", { STi, ST }, 0 },
13909     { "fdiv!Mp", { STi, ST }, 0 },
13910     { "fdivMp", { STi, ST }, 0 },
13911   },
13912   /* df */
13913   {
13914     { "ffreep", { STi }, 0 },
13915     { Bad_Opcode },
13916     { Bad_Opcode },
13917     { Bad_Opcode },
13918     { FGRPdf_4 },
13919     { "fucomip", { ST, STi }, 0 },
13920     { "fcomip", { ST, STi }, 0 },
13921     { Bad_Opcode },
13922   },
13923 };
13924
13925 static char *fgrps[][8] = {
13926   /* d9_2  0 */
13927   {
13928     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13929   },
13930
13931   /* d9_4  1 */
13932   {
13933     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13934   },
13935
13936   /* d9_5  2 */
13937   {
13938     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13939   },
13940
13941   /* d9_6  3 */
13942   {
13943     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13944   },
13945
13946   /* d9_7  4 */
13947   {
13948     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13949   },
13950
13951   /* da_5  5 */
13952   {
13953     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13954   },
13955
13956   /* db_4  6 */
13957   {
13958     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13959     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13960   },
13961
13962   /* de_3  7 */
13963   {
13964     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13965   },
13966
13967   /* df_4  8 */
13968   {
13969     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13970   },
13971 };
13972
13973 static void
13974 swap_operand (void)
13975 {
13976   mnemonicendp[0] = '.';
13977   mnemonicendp[1] = 's';
13978   mnemonicendp += 2;
13979 }
13980
13981 static void
13982 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13983                int sizeflag ATTRIBUTE_UNUSED)
13984 {
13985   /* Skip mod/rm byte.  */
13986   MODRM_CHECK;
13987   codep++;
13988 }
13989
13990 static void
13991 dofloat (int sizeflag)
13992 {
13993   const struct dis386 *dp;
13994   unsigned char floatop;
13995
13996   floatop = codep[-1];
13997
13998   if (modrm.mod != 3)
13999     {
14000       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
14001
14002       putop (float_mem[fp_indx], sizeflag);
14003       obufp = op_out[0];
14004       op_ad = 2;
14005       OP_E (float_mem_mode[fp_indx], sizeflag);
14006       return;
14007     }
14008   /* Skip mod/rm byte.  */
14009   MODRM_CHECK;
14010   codep++;
14011
14012   dp = &float_reg[floatop - 0xd8][modrm.reg];
14013   if (dp->name == NULL)
14014     {
14015       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
14016
14017       /* Instruction fnstsw is only one with strange arg.  */
14018       if (floatop == 0xdf && codep[-1] == 0xe0)
14019         strcpy (op_out[0], names16[0]);
14020     }
14021   else
14022     {
14023       putop (dp->name, sizeflag);
14024
14025       obufp = op_out[0];
14026       op_ad = 2;
14027       if (dp->op[0].rtn)
14028         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
14029
14030       obufp = op_out[1];
14031       op_ad = 1;
14032       if (dp->op[1].rtn)
14033         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
14034     }
14035 }
14036
14037 /* Like oappend (below), but S is a string starting with '%'.
14038    In Intel syntax, the '%' is elided.  */
14039 static void
14040 oappend_maybe_intel (const char *s)
14041 {
14042   oappend (s + intel_syntax);
14043 }
14044
14045 static void
14046 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14047 {
14048   oappend_maybe_intel ("%st");
14049 }
14050
14051 static void
14052 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14053 {
14054   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
14055   oappend_maybe_intel (scratchbuf);
14056 }
14057
14058 /* Capital letters in template are macros.  */
14059 static int
14060 putop (const char *in_template, int sizeflag)
14061 {
14062   const char *p;
14063   int alt = 0;
14064   int cond = 1;
14065   unsigned int l = 0, len = 1;
14066   char last[4];
14067
14068 #define SAVE_LAST(c)                    \
14069   if (l < len && l < sizeof (last))     \
14070     last[l++] = c;                      \
14071   else                                  \
14072     abort ();
14073
14074   for (p = in_template; *p; p++)
14075     {
14076       switch (*p)
14077         {
14078         default:
14079           *obufp++ = *p;
14080           break;
14081         case '%':
14082           len++;
14083           break;
14084         case '!':
14085           cond = 0;
14086           break;
14087         case '{':
14088           if (intel_syntax)
14089             {
14090               while (*++p != '|')
14091                 if (*p == '}' || *p == '\0')
14092                   abort ();
14093             }
14094           /* Fall through.  */
14095         case 'I':
14096           alt = 1;
14097           continue;
14098         case '|':
14099           while (*++p != '}')
14100             {
14101               if (*p == '\0')
14102                 abort ();
14103             }
14104           break;
14105         case '}':
14106           break;
14107         case 'A':
14108           if (intel_syntax)
14109             break;
14110           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14111             *obufp++ = 'b';
14112           break;
14113         case 'B':
14114           if (l == 0 && len == 1)
14115             {
14116 case_B:
14117               if (intel_syntax)
14118                 break;
14119               if (sizeflag & SUFFIX_ALWAYS)
14120                 *obufp++ = 'b';
14121             }
14122           else
14123             {
14124               if (l != 1
14125                   || len != 2
14126                   || last[0] != 'L')
14127                 {
14128                   SAVE_LAST (*p);
14129                   break;
14130                 }
14131
14132               if (address_mode == mode_64bit
14133                   && !(prefixes & PREFIX_ADDR))
14134                 {
14135                   *obufp++ = 'a';
14136                   *obufp++ = 'b';
14137                   *obufp++ = 's';
14138                 }
14139
14140               goto case_B;
14141             }
14142           break;
14143         case 'C':
14144           if (intel_syntax && !alt)
14145             break;
14146           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14147             {
14148               if (sizeflag & DFLAG)
14149                 *obufp++ = intel_syntax ? 'd' : 'l';
14150               else
14151                 *obufp++ = intel_syntax ? 'w' : 's';
14152               used_prefixes |= (prefixes & PREFIX_DATA);
14153             }
14154           break;
14155         case 'D':
14156           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14157             break;
14158           USED_REX (REX_W);
14159           if (modrm.mod == 3)
14160             {
14161               if (rex & REX_W)
14162                 *obufp++ = 'q';
14163               else
14164                 {
14165                   if (sizeflag & DFLAG)
14166                     *obufp++ = intel_syntax ? 'd' : 'l';
14167                   else
14168                     *obufp++ = 'w';
14169                   used_prefixes |= (prefixes & PREFIX_DATA);
14170                 }
14171             }
14172           else
14173             *obufp++ = 'w';
14174           break;
14175         case 'E':               /* For jcxz/jecxz */
14176           if (address_mode == mode_64bit)
14177             {
14178               if (sizeflag & AFLAG)
14179                 *obufp++ = 'r';
14180               else
14181                 *obufp++ = 'e';
14182             }
14183           else
14184             if (sizeflag & AFLAG)
14185               *obufp++ = 'e';
14186           used_prefixes |= (prefixes & PREFIX_ADDR);
14187           break;
14188         case 'F':
14189           if (intel_syntax)
14190             break;
14191           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14192             {
14193               if (sizeflag & AFLAG)
14194                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14195               else
14196                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14197               used_prefixes |= (prefixes & PREFIX_ADDR);
14198             }
14199           break;
14200         case 'G':
14201           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14202             break;
14203           if ((rex & REX_W) || (sizeflag & DFLAG))
14204             *obufp++ = 'l';
14205           else
14206             *obufp++ = 'w';
14207           if (!(rex & REX_W))
14208             used_prefixes |= (prefixes & PREFIX_DATA);
14209           break;
14210         case 'H':
14211           if (intel_syntax)
14212             break;
14213           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14214               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14215             {
14216               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14217               *obufp++ = ',';
14218               *obufp++ = 'p';
14219               if (prefixes & PREFIX_DS)
14220                 *obufp++ = 't';
14221               else
14222                 *obufp++ = 'n';
14223             }
14224           break;
14225         case 'J':
14226           if (intel_syntax)
14227             break;
14228           *obufp++ = 'l';
14229           break;
14230         case 'K':
14231           USED_REX (REX_W);
14232           if (rex & REX_W)
14233             *obufp++ = 'q';
14234           else
14235             *obufp++ = 'd';
14236           break;
14237         case 'Z':
14238           if (l != 0 || len != 1)
14239             {
14240               if (l != 1 || len != 2 || last[0] != 'X')
14241                 {
14242                   SAVE_LAST (*p);
14243                   break;
14244                 }
14245               if (!need_vex || !vex.evex)
14246                 abort ();
14247               if (intel_syntax
14248                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14249                 break;
14250               switch (vex.length)
14251                 {
14252                 case 128:
14253                   *obufp++ = 'x';
14254                   break;
14255                 case 256:
14256                   *obufp++ = 'y';
14257                   break;
14258                 case 512:
14259                   *obufp++ = 'z';
14260                   break;
14261                 default:
14262                   abort ();
14263                 }
14264               break;
14265             }
14266           if (intel_syntax)
14267             break;
14268           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14269             {
14270               *obufp++ = 'q';
14271               break;
14272             }
14273           /* Fall through.  */
14274           goto case_L;
14275         case 'L':
14276           if (l != 0 || len != 1)
14277             {
14278               SAVE_LAST (*p);
14279               break;
14280             }
14281 case_L:
14282           if (intel_syntax)
14283             break;
14284           if (sizeflag & SUFFIX_ALWAYS)
14285             *obufp++ = 'l';
14286           break;
14287         case 'M':
14288           if (intel_mnemonic != cond)
14289             *obufp++ = 'r';
14290           break;
14291         case 'N':
14292           if ((prefixes & PREFIX_FWAIT) == 0)
14293             *obufp++ = 'n';
14294           else
14295             used_prefixes |= PREFIX_FWAIT;
14296           break;
14297         case 'O':
14298           USED_REX (REX_W);
14299           if (rex & REX_W)
14300             *obufp++ = 'o';
14301           else if (intel_syntax && (sizeflag & DFLAG))
14302             *obufp++ = 'q';
14303           else
14304             *obufp++ = 'd';
14305           if (!(rex & REX_W))
14306             used_prefixes |= (prefixes & PREFIX_DATA);
14307           break;
14308         case '&':
14309           if (!intel_syntax
14310               && address_mode == mode_64bit
14311               && isa64 == intel64)
14312             {
14313               *obufp++ = 'q';
14314               break;
14315             }
14316           /* Fall through.  */
14317         case 'T':
14318           if (!intel_syntax
14319               && address_mode == mode_64bit
14320               && ((sizeflag & DFLAG) || (rex & REX_W)))
14321             {
14322               *obufp++ = 'q';
14323               break;
14324             }
14325           /* Fall through.  */
14326           goto case_P;
14327         case 'P':
14328           if (l == 0 && len == 1)
14329             {
14330 case_P:
14331               if (intel_syntax)
14332                 {
14333                   if ((rex & REX_W) == 0
14334                       && (prefixes & PREFIX_DATA))
14335                     {
14336                       if ((sizeflag & DFLAG) == 0)
14337                         *obufp++ = 'w';
14338                       used_prefixes |= (prefixes & PREFIX_DATA);
14339                     }
14340                   break;
14341                 }
14342               if ((prefixes & PREFIX_DATA)
14343                   || (rex & REX_W)
14344                   || (sizeflag & SUFFIX_ALWAYS))
14345                 {
14346                   USED_REX (REX_W);
14347                   if (rex & REX_W)
14348                     *obufp++ = 'q';
14349                   else
14350                     {
14351                       if (sizeflag & DFLAG)
14352                         *obufp++ = 'l';
14353                       else
14354                         *obufp++ = 'w';
14355                       used_prefixes |= (prefixes & PREFIX_DATA);
14356                     }
14357                 }
14358             }
14359           else
14360             {
14361               if (l != 1 || len != 2 || last[0] != 'L')
14362                 {
14363                   SAVE_LAST (*p);
14364                   break;
14365                 }
14366
14367               if ((prefixes & PREFIX_DATA)
14368                   || (rex & REX_W)
14369                   || (sizeflag & SUFFIX_ALWAYS))
14370                 {
14371                   USED_REX (REX_W);
14372                   if (rex & REX_W)
14373                     *obufp++ = 'q';
14374                   else
14375                     {
14376                       if (sizeflag & DFLAG)
14377                         *obufp++ = intel_syntax ? 'd' : 'l';
14378                       else
14379                         *obufp++ = 'w';
14380                       used_prefixes |= (prefixes & PREFIX_DATA);
14381                     }
14382                 }
14383             }
14384           break;
14385         case 'U':
14386           if (intel_syntax)
14387             break;
14388           if (address_mode == mode_64bit
14389               && ((sizeflag & DFLAG) || (rex & REX_W)))
14390             {
14391               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14392                 *obufp++ = 'q';
14393               break;
14394             }
14395           /* Fall through.  */
14396           goto case_Q;
14397         case 'Q':
14398           if (l == 0 && len == 1)
14399             {
14400 case_Q:
14401               if (intel_syntax && !alt)
14402                 break;
14403               USED_REX (REX_W);
14404               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14405                 {
14406                   if (rex & REX_W)
14407                     *obufp++ = 'q';
14408                   else
14409                     {
14410                       if (sizeflag & DFLAG)
14411                         *obufp++ = intel_syntax ? 'd' : 'l';
14412                       else
14413                         *obufp++ = 'w';
14414                       used_prefixes |= (prefixes & PREFIX_DATA);
14415                     }
14416                 }
14417             }
14418           else
14419             {
14420               if (l != 1 || len != 2 || last[0] != 'L')
14421                 {
14422                   SAVE_LAST (*p);
14423                   break;
14424                 }
14425               if (intel_syntax
14426                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14427                 break;
14428               if ((rex & REX_W))
14429                 {
14430                   USED_REX (REX_W);
14431                   *obufp++ = 'q';
14432                 }
14433               else
14434                 *obufp++ = 'l';
14435             }
14436           break;
14437         case 'R':
14438           USED_REX (REX_W);
14439           if (rex & REX_W)
14440             *obufp++ = 'q';
14441           else if (sizeflag & DFLAG)
14442             {
14443               if (intel_syntax)
14444                   *obufp++ = 'd';
14445               else
14446                   *obufp++ = 'l';
14447             }
14448           else
14449             *obufp++ = 'w';
14450           if (intel_syntax && !p[1]
14451               && ((rex & REX_W) || (sizeflag & DFLAG)))
14452             *obufp++ = 'e';
14453           if (!(rex & REX_W))
14454             used_prefixes |= (prefixes & PREFIX_DATA);
14455           break;
14456         case 'V':
14457           if (l == 0 && len == 1)
14458             {
14459               if (intel_syntax)
14460                 break;
14461               if (address_mode == mode_64bit
14462                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14463                 {
14464                   if (sizeflag & SUFFIX_ALWAYS)
14465                     *obufp++ = 'q';
14466                   break;
14467                 }
14468             }
14469           else
14470             {
14471               if (l != 1
14472                   || len != 2
14473                   || last[0] != 'L')
14474                 {
14475                   SAVE_LAST (*p);
14476                   break;
14477                 }
14478
14479               if (rex & REX_W)
14480                 {
14481                   *obufp++ = 'a';
14482                   *obufp++ = 'b';
14483                   *obufp++ = 's';
14484                 }
14485             }
14486           /* Fall through.  */
14487           goto case_S;
14488         case 'S':
14489           if (l == 0 && len == 1)
14490             {
14491 case_S:
14492               if (intel_syntax)
14493                 break;
14494               if (sizeflag & SUFFIX_ALWAYS)
14495                 {
14496                   if (rex & REX_W)
14497                     *obufp++ = 'q';
14498                   else
14499                     {
14500                       if (sizeflag & DFLAG)
14501                         *obufp++ = 'l';
14502                       else
14503                         *obufp++ = 'w';
14504                       used_prefixes |= (prefixes & PREFIX_DATA);
14505                     }
14506                 }
14507             }
14508           else
14509             {
14510               if (l != 1
14511                   || len != 2
14512                   || last[0] != 'L')
14513                 {
14514                   SAVE_LAST (*p);
14515                   break;
14516                 }
14517
14518               if (address_mode == mode_64bit
14519                   && !(prefixes & PREFIX_ADDR))
14520                 {
14521                   *obufp++ = 'a';
14522                   *obufp++ = 'b';
14523                   *obufp++ = 's';
14524                 }
14525
14526               goto case_S;
14527             }
14528           break;
14529         case 'X':
14530           if (l != 0 || len != 1)
14531             {
14532               SAVE_LAST (*p);
14533               break;
14534             }
14535           if (need_vex && vex.prefix)
14536             {
14537               if (vex.prefix == DATA_PREFIX_OPCODE)
14538                 *obufp++ = 'd';
14539               else
14540                 *obufp++ = 's';
14541             }
14542           else
14543             {
14544               if (prefixes & PREFIX_DATA)
14545                 *obufp++ = 'd';
14546               else
14547                 *obufp++ = 's';
14548               used_prefixes |= (prefixes & PREFIX_DATA);
14549             }
14550           break;
14551         case 'Y':
14552           if (l == 0 && len == 1)
14553             {
14554               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14555                 break;
14556               if (rex & REX_W)
14557                 {
14558                   USED_REX (REX_W);
14559                   *obufp++ = 'q';
14560                 }
14561               break;
14562             }
14563           else
14564             {
14565               if (l != 1 || len != 2 || last[0] != 'X')
14566                 {
14567                   SAVE_LAST (*p);
14568                   break;
14569                 }
14570               if (!need_vex)
14571                 abort ();
14572               if (intel_syntax
14573                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14574                 break;
14575               switch (vex.length)
14576                 {
14577                 case 128:
14578                   *obufp++ = 'x';
14579                   break;
14580                 case 256:
14581                   *obufp++ = 'y';
14582                   break;
14583                 case 512:
14584                   if (!vex.evex)
14585                 default:
14586                     abort ();
14587                 }
14588             }
14589           break;
14590         case 'W':
14591           if (l == 0 && len == 1)
14592             {
14593               /* operand size flag for cwtl, cbtw */
14594               USED_REX (REX_W);
14595               if (rex & REX_W)
14596                 {
14597                   if (intel_syntax)
14598                     *obufp++ = 'd';
14599                   else
14600                     *obufp++ = 'l';
14601                 }
14602               else if (sizeflag & DFLAG)
14603                 *obufp++ = 'w';
14604               else
14605                 *obufp++ = 'b';
14606               if (!(rex & REX_W))
14607                 used_prefixes |= (prefixes & PREFIX_DATA);
14608             }
14609           else
14610             {
14611               if (l != 1
14612                   || len != 2
14613                   || (last[0] != 'X'
14614                       && last[0] != 'L'))
14615                 {
14616                   SAVE_LAST (*p);
14617                   break;
14618                 }
14619               if (!need_vex)
14620                 abort ();
14621               if (last[0] == 'X')
14622                 *obufp++ = vex.w ? 'd': 's';
14623               else
14624                 *obufp++ = vex.w ? 'q': 'd';
14625             }
14626           break;
14627         case '^':
14628           if (intel_syntax)
14629             break;
14630           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14631             {
14632               if (sizeflag & DFLAG)
14633                 *obufp++ = 'l';
14634               else
14635                 *obufp++ = 'w';
14636               used_prefixes |= (prefixes & PREFIX_DATA);
14637             }
14638           break;
14639         case '@':
14640           if (intel_syntax)
14641             break;
14642           if (address_mode == mode_64bit
14643               && (isa64 == intel64
14644                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14645               *obufp++ = 'q';
14646           else if ((prefixes & PREFIX_DATA))
14647             {
14648               if (!(sizeflag & DFLAG))
14649                 *obufp++ = 'w';
14650               used_prefixes |= (prefixes & PREFIX_DATA);
14651             }
14652           break;
14653         }
14654       alt = 0;
14655     }
14656   *obufp = 0;
14657   mnemonicendp = obufp;
14658   return 0;
14659 }
14660
14661 static void
14662 oappend (const char *s)
14663 {
14664   obufp = stpcpy (obufp, s);
14665 }
14666
14667 static void
14668 append_seg (void)
14669 {
14670   /* Only print the active segment register.  */
14671   if (!active_seg_prefix)
14672     return;
14673
14674   used_prefixes |= active_seg_prefix;
14675   switch (active_seg_prefix)
14676     {
14677     case PREFIX_CS:
14678       oappend_maybe_intel ("%cs:");
14679       break;
14680     case PREFIX_DS:
14681       oappend_maybe_intel ("%ds:");
14682       break;
14683     case PREFIX_SS:
14684       oappend_maybe_intel ("%ss:");
14685       break;
14686     case PREFIX_ES:
14687       oappend_maybe_intel ("%es:");
14688       break;
14689     case PREFIX_FS:
14690       oappend_maybe_intel ("%fs:");
14691       break;
14692     case PREFIX_GS:
14693       oappend_maybe_intel ("%gs:");
14694       break;
14695     default:
14696       break;
14697     }
14698 }
14699
14700 static void
14701 OP_indirE (int bytemode, int sizeflag)
14702 {
14703   if (!intel_syntax)
14704     oappend ("*");
14705   OP_E (bytemode, sizeflag);
14706 }
14707
14708 static void
14709 print_operand_value (char *buf, int hex, bfd_vma disp)
14710 {
14711   if (address_mode == mode_64bit)
14712     {
14713       if (hex)
14714         {
14715           char tmp[30];
14716           int i;
14717           buf[0] = '0';
14718           buf[1] = 'x';
14719           sprintf_vma (tmp, disp);
14720           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14721           strcpy (buf + 2, tmp + i);
14722         }
14723       else
14724         {
14725           bfd_signed_vma v = disp;
14726           char tmp[30];
14727           int i;
14728           if (v < 0)
14729             {
14730               *(buf++) = '-';
14731               v = -disp;
14732               /* Check for possible overflow on 0x8000000000000000.  */
14733               if (v < 0)
14734                 {
14735                   strcpy (buf, "9223372036854775808");
14736                   return;
14737                 }
14738             }
14739           if (!v)
14740             {
14741               strcpy (buf, "0");
14742               return;
14743             }
14744
14745           i = 0;
14746           tmp[29] = 0;
14747           while (v)
14748             {
14749               tmp[28 - i] = (v % 10) + '0';
14750               v /= 10;
14751               i++;
14752             }
14753           strcpy (buf, tmp + 29 - i);
14754         }
14755     }
14756   else
14757     {
14758       if (hex)
14759         sprintf (buf, "0x%x", (unsigned int) disp);
14760       else
14761         sprintf (buf, "%d", (int) disp);
14762     }
14763 }
14764
14765 /* Put DISP in BUF as signed hex number.  */
14766
14767 static void
14768 print_displacement (char *buf, bfd_vma disp)
14769 {
14770   bfd_signed_vma val = disp;
14771   char tmp[30];
14772   int i, j = 0;
14773
14774   if (val < 0)
14775     {
14776       buf[j++] = '-';
14777       val = -disp;
14778
14779       /* Check for possible overflow.  */
14780       if (val < 0)
14781         {
14782           switch (address_mode)
14783             {
14784             case mode_64bit:
14785               strcpy (buf + j, "0x8000000000000000");
14786               break;
14787             case mode_32bit:
14788               strcpy (buf + j, "0x80000000");
14789               break;
14790             case mode_16bit:
14791               strcpy (buf + j, "0x8000");
14792               break;
14793             }
14794           return;
14795         }
14796     }
14797
14798   buf[j++] = '0';
14799   buf[j++] = 'x';
14800
14801   sprintf_vma (tmp, (bfd_vma) val);
14802   for (i = 0; tmp[i] == '0'; i++)
14803     continue;
14804   if (tmp[i] == '\0')
14805     i--;
14806   strcpy (buf + j, tmp + i);
14807 }
14808
14809 static void
14810 intel_operand_size (int bytemode, int sizeflag)
14811 {
14812   if (vex.evex
14813       && vex.b
14814       && (bytemode == x_mode
14815           || bytemode == evex_half_bcst_xmmq_mode))
14816     {
14817       if (vex.w)
14818         oappend ("QWORD PTR ");
14819       else
14820         oappend ("DWORD PTR ");
14821       return;
14822     }
14823   switch (bytemode)
14824     {
14825     case b_mode:
14826     case b_swap_mode:
14827     case dqb_mode:
14828     case db_mode:
14829       oappend ("BYTE PTR ");
14830       break;
14831     case w_mode:
14832     case dw_mode:
14833     case dqw_mode:
14834     case dqw_swap_mode:
14835       oappend ("WORD PTR ");
14836       break;
14837     case indir_v_mode:
14838       if (address_mode == mode_64bit && isa64 == intel64)
14839         {
14840           oappend ("QWORD PTR ");
14841           break;
14842         }
14843       /* Fall through.  */
14844     case stack_v_mode:
14845       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14846         {
14847           oappend ("QWORD PTR ");
14848           break;
14849         }
14850       /* Fall through.  */
14851     case v_mode:
14852     case v_swap_mode:
14853     case dq_mode:
14854       USED_REX (REX_W);
14855       if (rex & REX_W)
14856         oappend ("QWORD PTR ");
14857       else
14858         {
14859           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14860             oappend ("DWORD PTR ");
14861           else
14862             oappend ("WORD PTR ");
14863           used_prefixes |= (prefixes & PREFIX_DATA);
14864         }
14865       break;
14866     case z_mode:
14867       if ((rex & REX_W) || (sizeflag & DFLAG))
14868         *obufp++ = 'D';
14869       oappend ("WORD PTR ");
14870       if (!(rex & REX_W))
14871         used_prefixes |= (prefixes & PREFIX_DATA);
14872       break;
14873     case a_mode:
14874       if (sizeflag & DFLAG)
14875         oappend ("QWORD PTR ");
14876       else
14877         oappend ("DWORD PTR ");
14878       used_prefixes |= (prefixes & PREFIX_DATA);
14879       break;
14880     case d_mode:
14881     case d_scalar_mode:
14882     case d_scalar_swap_mode:
14883     case d_swap_mode:
14884     case dqd_mode:
14885       oappend ("DWORD PTR ");
14886       break;
14887     case q_mode:
14888     case q_scalar_mode:
14889     case q_scalar_swap_mode:
14890     case q_swap_mode:
14891       oappend ("QWORD PTR ");
14892       break;
14893     case m_mode:
14894       if (address_mode == mode_64bit)
14895         oappend ("QWORD PTR ");
14896       else
14897         oappend ("DWORD PTR ");
14898       break;
14899     case f_mode:
14900       if (sizeflag & DFLAG)
14901         oappend ("FWORD PTR ");
14902       else
14903         oappend ("DWORD PTR ");
14904       used_prefixes |= (prefixes & PREFIX_DATA);
14905       break;
14906     case t_mode:
14907       oappend ("TBYTE PTR ");
14908       break;
14909     case x_mode:
14910     case x_swap_mode:
14911     case evex_x_gscat_mode:
14912     case evex_x_nobcst_mode:
14913       if (need_vex)
14914         {
14915           switch (vex.length)
14916             {
14917             case 128:
14918               oappend ("XMMWORD PTR ");
14919               break;
14920             case 256:
14921               oappend ("YMMWORD PTR ");
14922               break;
14923             case 512:
14924               oappend ("ZMMWORD PTR ");
14925               break;
14926             default:
14927               abort ();
14928             }
14929         }
14930       else
14931         oappend ("XMMWORD PTR ");
14932       break;
14933     case xmm_mode:
14934       oappend ("XMMWORD PTR ");
14935       break;
14936     case ymm_mode:
14937       oappend ("YMMWORD PTR ");
14938       break;
14939     case xmmq_mode:
14940     case evex_half_bcst_xmmq_mode:
14941       if (!need_vex)
14942         abort ();
14943
14944       switch (vex.length)
14945         {
14946         case 128:
14947           oappend ("QWORD PTR ");
14948           break;
14949         case 256:
14950           oappend ("XMMWORD PTR ");
14951           break;
14952         case 512:
14953           oappend ("YMMWORD PTR ");
14954           break;
14955         default:
14956           abort ();
14957         }
14958       break;
14959     case xmm_mb_mode:
14960       if (!need_vex)
14961         abort ();
14962
14963       switch (vex.length)
14964         {
14965         case 128:
14966         case 256:
14967         case 512:
14968           oappend ("BYTE PTR ");
14969           break;
14970         default:
14971           abort ();
14972         }
14973       break;
14974     case xmm_mw_mode:
14975       if (!need_vex)
14976         abort ();
14977
14978       switch (vex.length)
14979         {
14980         case 128:
14981         case 256:
14982         case 512:
14983           oappend ("WORD PTR ");
14984           break;
14985         default:
14986           abort ();
14987         }
14988       break;
14989     case xmm_md_mode:
14990       if (!need_vex)
14991         abort ();
14992
14993       switch (vex.length)
14994         {
14995         case 128:
14996         case 256:
14997         case 512:
14998           oappend ("DWORD PTR ");
14999           break;
15000         default:
15001           abort ();
15002         }
15003       break;
15004     case xmm_mq_mode:
15005       if (!need_vex)
15006         abort ();
15007
15008       switch (vex.length)
15009         {
15010         case 128:
15011         case 256:
15012         case 512:
15013           oappend ("QWORD PTR ");
15014           break;
15015         default:
15016           abort ();
15017         }
15018       break;
15019     case xmmdw_mode:
15020       if (!need_vex)
15021         abort ();
15022
15023       switch (vex.length)
15024         {
15025         case 128:
15026           oappend ("WORD PTR ");
15027           break;
15028         case 256:
15029           oappend ("DWORD PTR ");
15030           break;
15031         case 512:
15032           oappend ("QWORD PTR ");
15033           break;
15034         default:
15035           abort ();
15036         }
15037       break;
15038     case xmmqd_mode:
15039       if (!need_vex)
15040         abort ();
15041
15042       switch (vex.length)
15043         {
15044         case 128:
15045           oappend ("DWORD PTR ");
15046           break;
15047         case 256:
15048           oappend ("QWORD PTR ");
15049           break;
15050         case 512:
15051           oappend ("XMMWORD PTR ");
15052           break;
15053         default:
15054           abort ();
15055         }
15056       break;
15057     case ymmq_mode:
15058       if (!need_vex)
15059         abort ();
15060
15061       switch (vex.length)
15062         {
15063         case 128:
15064           oappend ("QWORD PTR ");
15065           break;
15066         case 256:
15067           oappend ("YMMWORD PTR ");
15068           break;
15069         case 512:
15070           oappend ("ZMMWORD PTR ");
15071           break;
15072         default:
15073           abort ();
15074         }
15075       break;
15076     case ymmxmm_mode:
15077       if (!need_vex)
15078         abort ();
15079
15080       switch (vex.length)
15081         {
15082         case 128:
15083         case 256:
15084           oappend ("XMMWORD PTR ");
15085           break;
15086         default:
15087           abort ();
15088         }
15089       break;
15090     case o_mode:
15091       oappend ("OWORD PTR ");
15092       break;
15093     case xmm_mdq_mode:
15094     case vex_w_dq_mode:
15095     case vex_scalar_w_dq_mode:
15096       if (!need_vex)
15097         abort ();
15098
15099       if (vex.w)
15100         oappend ("QWORD PTR ");
15101       else
15102         oappend ("DWORD PTR ");
15103       break;
15104     case vex_vsib_d_w_dq_mode:
15105     case vex_vsib_q_w_dq_mode:
15106       if (!need_vex)
15107         abort ();
15108
15109       if (!vex.evex)
15110         {
15111           if (vex.w)
15112             oappend ("QWORD PTR ");
15113           else
15114             oappend ("DWORD PTR ");
15115         }
15116       else
15117         {
15118           switch (vex.length)
15119             {
15120             case 128:
15121               oappend ("XMMWORD PTR ");
15122               break;
15123             case 256:
15124               oappend ("YMMWORD PTR ");
15125               break;
15126             case 512:
15127               oappend ("ZMMWORD PTR ");
15128               break;
15129             default:
15130               abort ();
15131             }
15132         }
15133       break;
15134     case vex_vsib_q_w_d_mode:
15135     case vex_vsib_d_w_d_mode:
15136       if (!need_vex || !vex.evex)
15137         abort ();
15138
15139       switch (vex.length)
15140         {
15141         case 128:
15142           oappend ("QWORD PTR ");
15143           break;
15144         case 256:
15145           oappend ("XMMWORD PTR ");
15146           break;
15147         case 512:
15148           oappend ("YMMWORD PTR ");
15149           break;
15150         default:
15151           abort ();
15152         }
15153
15154       break;
15155     case mask_bd_mode:
15156       if (!need_vex || vex.length != 128)
15157         abort ();
15158       if (vex.w)
15159         oappend ("DWORD PTR ");
15160       else
15161         oappend ("BYTE PTR ");
15162       break;
15163     case mask_mode:
15164       if (!need_vex)
15165         abort ();
15166       if (vex.w)
15167         oappend ("QWORD PTR ");
15168       else
15169         oappend ("WORD PTR ");
15170       break;
15171     case v_bnd_mode:
15172     default:
15173       break;
15174     }
15175 }
15176
15177 static void
15178 OP_E_register (int bytemode, int sizeflag)
15179 {
15180   int reg = modrm.rm;
15181   const char **names;
15182
15183   USED_REX (REX_B);
15184   if ((rex & REX_B))
15185     reg += 8;
15186
15187   if ((sizeflag & SUFFIX_ALWAYS)
15188       && (bytemode == b_swap_mode
15189           || bytemode == v_swap_mode
15190           || bytemode == dqw_swap_mode))
15191     swap_operand ();
15192
15193   switch (bytemode)
15194     {
15195     case b_mode:
15196     case b_swap_mode:
15197       USED_REX (0);
15198       if (rex)
15199         names = names8rex;
15200       else
15201         names = names8;
15202       break;
15203     case w_mode:
15204       names = names16;
15205       break;
15206     case d_mode:
15207     case dw_mode:
15208     case db_mode:
15209       names = names32;
15210       break;
15211     case q_mode:
15212       names = names64;
15213       break;
15214     case m_mode:
15215     case v_bnd_mode:
15216       names = address_mode == mode_64bit ? names64 : names32;
15217       break;
15218     case bnd_mode:
15219       names = names_bnd;
15220       break;
15221     case indir_v_mode:
15222       if (address_mode == mode_64bit && isa64 == intel64)
15223         {
15224           names = names64;
15225           break;
15226         }
15227       /* Fall through.  */
15228     case stack_v_mode:
15229       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15230         {
15231           names = names64;
15232           break;
15233         }
15234       bytemode = v_mode;
15235       /* Fall through.  */
15236     case v_mode:
15237     case v_swap_mode:
15238     case dq_mode:
15239     case dqb_mode:
15240     case dqd_mode:
15241     case dqw_mode:
15242     case dqw_swap_mode:
15243       USED_REX (REX_W);
15244       if (rex & REX_W)
15245         names = names64;
15246       else
15247         {
15248           if ((sizeflag & DFLAG)
15249               || (bytemode != v_mode
15250                   && bytemode != v_swap_mode))
15251             names = names32;
15252           else
15253             names = names16;
15254           used_prefixes |= (prefixes & PREFIX_DATA);
15255         }
15256       break;
15257     case mask_bd_mode:
15258     case mask_mode:
15259       if (reg > 0x7)
15260         {
15261           oappend ("(bad)");
15262           return;
15263         }
15264       names = names_mask;
15265       break;
15266     case 0:
15267       return;
15268     default:
15269       oappend (INTERNAL_DISASSEMBLER_ERROR);
15270       return;
15271     }
15272   oappend (names[reg]);
15273 }
15274
15275 static void
15276 OP_E_memory (int bytemode, int sizeflag)
15277 {
15278   bfd_vma disp = 0;
15279   int add = (rex & REX_B) ? 8 : 0;
15280   int riprel = 0;
15281   int shift;
15282
15283   if (vex.evex)
15284     {
15285       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15286       if (vex.b
15287           && bytemode != x_mode
15288           && bytemode != xmmq_mode
15289           && bytemode != evex_half_bcst_xmmq_mode)
15290         {
15291           BadOp ();
15292           return;
15293         }
15294       switch (bytemode)
15295         {
15296         case dqw_mode:
15297         case dw_mode:
15298         case dqw_swap_mode:
15299           shift = 1;
15300           break;
15301         case dqb_mode:
15302         case db_mode:
15303           shift = 0;
15304           break;
15305         case vex_vsib_d_w_dq_mode:
15306         case vex_vsib_d_w_d_mode:
15307         case vex_vsib_q_w_dq_mode:
15308         case vex_vsib_q_w_d_mode:
15309         case evex_x_gscat_mode:
15310         case xmm_mdq_mode:
15311           shift = vex.w ? 3 : 2;
15312           break;
15313         case x_mode:
15314         case evex_half_bcst_xmmq_mode:
15315         case xmmq_mode:
15316           if (vex.b)
15317             {
15318               shift = vex.w ? 3 : 2;
15319               break;
15320             }
15321           /* Fall through.  */
15322         case xmmqd_mode:
15323         case xmmdw_mode:
15324         case ymmq_mode:
15325         case evex_x_nobcst_mode:
15326         case x_swap_mode:
15327           switch (vex.length)
15328             {
15329             case 128:
15330               shift = 4;
15331               break;
15332             case 256:
15333               shift = 5;
15334               break;
15335             case 512:
15336               shift = 6;
15337               break;
15338             default:
15339               abort ();
15340             }
15341           break;
15342         case ymm_mode:
15343           shift = 5;
15344           break;
15345         case xmm_mode:
15346           shift = 4;
15347           break;
15348         case xmm_mq_mode:
15349         case q_mode:
15350         case q_scalar_mode:
15351         case q_swap_mode:
15352         case q_scalar_swap_mode:
15353           shift = 3;
15354           break;
15355         case dqd_mode:
15356         case xmm_md_mode:
15357         case d_mode:
15358         case d_scalar_mode:
15359         case d_swap_mode:
15360         case d_scalar_swap_mode:
15361           shift = 2;
15362           break;
15363         case xmm_mw_mode:
15364           shift = 1;
15365           break;
15366         case xmm_mb_mode:
15367           shift = 0;
15368           break;
15369         default:
15370           abort ();
15371         }
15372       /* Make necessary corrections to shift for modes that need it.
15373          For these modes we currently have shift 4, 5 or 6 depending on
15374          vex.length (it corresponds to xmmword, ymmword or zmmword
15375          operand).  We might want to make it 3, 4 or 5 (e.g. for
15376          xmmq_mode).  In case of broadcast enabled the corrections
15377          aren't needed, as element size is always 32 or 64 bits.  */
15378       if (!vex.b
15379           && (bytemode == xmmq_mode
15380               || bytemode == evex_half_bcst_xmmq_mode))
15381         shift -= 1;
15382       else if (bytemode == xmmqd_mode)
15383         shift -= 2;
15384       else if (bytemode == xmmdw_mode)
15385         shift -= 3;
15386       else if (bytemode == ymmq_mode && vex.length == 128)
15387         shift -= 1;
15388     }
15389   else
15390     shift = 0;
15391
15392   USED_REX (REX_B);
15393   if (intel_syntax)
15394     intel_operand_size (bytemode, sizeflag);
15395   append_seg ();
15396
15397   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15398     {
15399       /* 32/64 bit address mode */
15400       int havedisp;
15401       int havesib;
15402       int havebase;
15403       int haveindex;
15404       int needindex;
15405       int base, rbase;
15406       int vindex = 0;
15407       int scale = 0;
15408       int addr32flag = !((sizeflag & AFLAG)
15409                          || bytemode == v_bnd_mode
15410                          || bytemode == bnd_mode);
15411       const char **indexes64 = names64;
15412       const char **indexes32 = names32;
15413
15414       havesib = 0;
15415       havebase = 1;
15416       haveindex = 0;
15417       base = modrm.rm;
15418
15419       if (base == 4)
15420         {
15421           havesib = 1;
15422           vindex = sib.index;
15423           USED_REX (REX_X);
15424           if (rex & REX_X)
15425             vindex += 8;
15426           switch (bytemode)
15427             {
15428             case vex_vsib_d_w_dq_mode:
15429             case vex_vsib_d_w_d_mode:
15430             case vex_vsib_q_w_dq_mode:
15431             case vex_vsib_q_w_d_mode:
15432               if (!need_vex)
15433                 abort ();
15434               if (vex.evex)
15435                 {
15436                   if (!vex.v)
15437                     vindex += 16;
15438                 }
15439
15440               haveindex = 1;
15441               switch (vex.length)
15442                 {
15443                 case 128:
15444                   indexes64 = indexes32 = names_xmm;
15445                   break;
15446                 case 256:
15447                   if (!vex.w
15448                       || bytemode == vex_vsib_q_w_dq_mode
15449                       || bytemode == vex_vsib_q_w_d_mode)
15450                     indexes64 = indexes32 = names_ymm;
15451                   else
15452                     indexes64 = indexes32 = names_xmm;
15453                   break;
15454                 case 512:
15455                   if (!vex.w
15456                       || bytemode == vex_vsib_q_w_dq_mode
15457                       || bytemode == vex_vsib_q_w_d_mode)
15458                     indexes64 = indexes32 = names_zmm;
15459                   else
15460                     indexes64 = indexes32 = names_ymm;
15461                   break;
15462                 default:
15463                   abort ();
15464                 }
15465               break;
15466             default:
15467               haveindex = vindex != 4;
15468               break;
15469             }
15470           scale = sib.scale;
15471           base = sib.base;
15472           codep++;
15473         }
15474       rbase = base + add;
15475
15476       switch (modrm.mod)
15477         {
15478         case 0:
15479           if (base == 5)
15480             {
15481               havebase = 0;
15482               if (address_mode == mode_64bit && !havesib)
15483                 riprel = 1;
15484               disp = get32s ();
15485             }
15486           break;
15487         case 1:
15488           FETCH_DATA (the_info, codep + 1);
15489           disp = *codep++;
15490           if ((disp & 0x80) != 0)
15491             disp -= 0x100;
15492           if (vex.evex && shift > 0)
15493             disp <<= shift;
15494           break;
15495         case 2:
15496           disp = get32s ();
15497           break;
15498         }
15499
15500       /* In 32bit mode, we need index register to tell [offset] from
15501          [eiz*1 + offset].  */
15502       needindex = (havesib
15503                    && !havebase
15504                    && !haveindex
15505                    && address_mode == mode_32bit);
15506       havedisp = (havebase
15507                   || needindex
15508                   || (havesib && (haveindex || scale != 0)));
15509
15510       if (!intel_syntax)
15511         if (modrm.mod != 0 || base == 5)
15512           {
15513             if (havedisp || riprel)
15514               print_displacement (scratchbuf, disp);
15515             else
15516               print_operand_value (scratchbuf, 1, disp);
15517             oappend (scratchbuf);
15518             if (riprel)
15519               {
15520                 set_op (disp, 1);
15521                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15522               }
15523           }
15524
15525       if ((havebase || haveindex || riprel)
15526           && (bytemode != v_bnd_mode)
15527           && (bytemode != bnd_mode))
15528         used_prefixes |= PREFIX_ADDR;
15529
15530       if (havedisp || (intel_syntax && riprel))
15531         {
15532           *obufp++ = open_char;
15533           if (intel_syntax && riprel)
15534             {
15535               set_op (disp, 1);
15536               oappend (!addr32flag ? "rip" : "eip");
15537             }
15538           *obufp = '\0';
15539           if (havebase)
15540             oappend (address_mode == mode_64bit && !addr32flag
15541                      ? names64[rbase] : names32[rbase]);
15542           if (havesib)
15543             {
15544               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15545                  print index to tell base + index from base.  */
15546               if (scale != 0
15547                   || needindex
15548                   || haveindex
15549                   || (havebase && base != ESP_REG_NUM))
15550                 {
15551                   if (!intel_syntax || havebase)
15552                     {
15553                       *obufp++ = separator_char;
15554                       *obufp = '\0';
15555                     }
15556                   if (haveindex)
15557                     oappend (address_mode == mode_64bit && !addr32flag
15558                              ? indexes64[vindex] : indexes32[vindex]);
15559                   else
15560                     oappend (address_mode == mode_64bit && !addr32flag
15561                              ? index64 : index32);
15562
15563                   *obufp++ = scale_char;
15564                   *obufp = '\0';
15565                   sprintf (scratchbuf, "%d", 1 << scale);
15566                   oappend (scratchbuf);
15567                 }
15568             }
15569           if (intel_syntax
15570               && (disp || modrm.mod != 0 || base == 5))
15571             {
15572               if (!havedisp || (bfd_signed_vma) disp >= 0)
15573                 {
15574                   *obufp++ = '+';
15575                   *obufp = '\0';
15576                 }
15577               else if (modrm.mod != 1 && disp != -disp)
15578                 {
15579                   *obufp++ = '-';
15580                   *obufp = '\0';
15581                   disp = - (bfd_signed_vma) disp;
15582                 }
15583
15584               if (havedisp)
15585                 print_displacement (scratchbuf, disp);
15586               else
15587                 print_operand_value (scratchbuf, 1, disp);
15588               oappend (scratchbuf);
15589             }
15590
15591           *obufp++ = close_char;
15592           *obufp = '\0';
15593         }
15594       else if (intel_syntax)
15595         {
15596           if (modrm.mod != 0 || base == 5)
15597             {
15598               if (!active_seg_prefix)
15599                 {
15600                   oappend (names_seg[ds_reg - es_reg]);
15601                   oappend (":");
15602                 }
15603               print_operand_value (scratchbuf, 1, disp);
15604               oappend (scratchbuf);
15605             }
15606         }
15607     }
15608   else
15609     {
15610       /* 16 bit address mode */
15611       used_prefixes |= prefixes & PREFIX_ADDR;
15612       switch (modrm.mod)
15613         {
15614         case 0:
15615           if (modrm.rm == 6)
15616             {
15617               disp = get16 ();
15618               if ((disp & 0x8000) != 0)
15619                 disp -= 0x10000;
15620             }
15621           break;
15622         case 1:
15623           FETCH_DATA (the_info, codep + 1);
15624           disp = *codep++;
15625           if ((disp & 0x80) != 0)
15626             disp -= 0x100;
15627           break;
15628         case 2:
15629           disp = get16 ();
15630           if ((disp & 0x8000) != 0)
15631             disp -= 0x10000;
15632           break;
15633         }
15634
15635       if (!intel_syntax)
15636         if (modrm.mod != 0 || modrm.rm == 6)
15637           {
15638             print_displacement (scratchbuf, disp);
15639             oappend (scratchbuf);
15640           }
15641
15642       if (modrm.mod != 0 || modrm.rm != 6)
15643         {
15644           *obufp++ = open_char;
15645           *obufp = '\0';
15646           oappend (index16[modrm.rm]);
15647           if (intel_syntax
15648               && (disp || modrm.mod != 0 || modrm.rm == 6))
15649             {
15650               if ((bfd_signed_vma) disp >= 0)
15651                 {
15652                   *obufp++ = '+';
15653                   *obufp = '\0';
15654                 }
15655               else if (modrm.mod != 1)
15656                 {
15657                   *obufp++ = '-';
15658                   *obufp = '\0';
15659                   disp = - (bfd_signed_vma) disp;
15660                 }
15661
15662               print_displacement (scratchbuf, disp);
15663               oappend (scratchbuf);
15664             }
15665
15666           *obufp++ = close_char;
15667           *obufp = '\0';
15668         }
15669       else if (intel_syntax)
15670         {
15671           if (!active_seg_prefix)
15672             {
15673               oappend (names_seg[ds_reg - es_reg]);
15674               oappend (":");
15675             }
15676           print_operand_value (scratchbuf, 1, disp & 0xffff);
15677           oappend (scratchbuf);
15678         }
15679     }
15680   if (vex.evex && vex.b
15681       && (bytemode == x_mode
15682           || bytemode == xmmq_mode
15683           || bytemode == evex_half_bcst_xmmq_mode))
15684     {
15685       if (vex.w
15686           || bytemode == xmmq_mode
15687           || bytemode == evex_half_bcst_xmmq_mode)
15688         {
15689           switch (vex.length)
15690             {
15691             case 128:
15692               oappend ("{1to2}");
15693               break;
15694             case 256:
15695               oappend ("{1to4}");
15696               break;
15697             case 512:
15698               oappend ("{1to8}");
15699               break;
15700             default:
15701               abort ();
15702             }
15703         }
15704       else
15705         {
15706           switch (vex.length)
15707             {
15708             case 128:
15709               oappend ("{1to4}");
15710               break;
15711             case 256:
15712               oappend ("{1to8}");
15713               break;
15714             case 512:
15715               oappend ("{1to16}");
15716               break;
15717             default:
15718               abort ();
15719             }
15720         }
15721     }
15722 }
15723
15724 static void
15725 OP_E (int bytemode, int sizeflag)
15726 {
15727   /* Skip mod/rm byte.  */
15728   MODRM_CHECK;
15729   codep++;
15730
15731   if (modrm.mod == 3)
15732     OP_E_register (bytemode, sizeflag);
15733   else
15734     OP_E_memory (bytemode, sizeflag);
15735 }
15736
15737 static void
15738 OP_G (int bytemode, int sizeflag)
15739 {
15740   int add = 0;
15741   USED_REX (REX_R);
15742   if (rex & REX_R)
15743     add += 8;
15744   switch (bytemode)
15745     {
15746     case b_mode:
15747       USED_REX (0);
15748       if (rex)
15749         oappend (names8rex[modrm.reg + add]);
15750       else
15751         oappend (names8[modrm.reg + add]);
15752       break;
15753     case w_mode:
15754       oappend (names16[modrm.reg + add]);
15755       break;
15756     case d_mode:
15757     case db_mode:
15758     case dw_mode:
15759       oappend (names32[modrm.reg + add]);
15760       break;
15761     case q_mode:
15762       oappend (names64[modrm.reg + add]);
15763       break;
15764     case bnd_mode:
15765       oappend (names_bnd[modrm.reg]);
15766       break;
15767     case v_mode:
15768     case dq_mode:
15769     case dqb_mode:
15770     case dqd_mode:
15771     case dqw_mode:
15772     case dqw_swap_mode:
15773       USED_REX (REX_W);
15774       if (rex & REX_W)
15775         oappend (names64[modrm.reg + add]);
15776       else
15777         {
15778           if ((sizeflag & DFLAG) || bytemode != v_mode)
15779             oappend (names32[modrm.reg + add]);
15780           else
15781             oappend (names16[modrm.reg + add]);
15782           used_prefixes |= (prefixes & PREFIX_DATA);
15783         }
15784       break;
15785     case m_mode:
15786       if (address_mode == mode_64bit)
15787         oappend (names64[modrm.reg + add]);
15788       else
15789         oappend (names32[modrm.reg + add]);
15790       break;
15791     case mask_bd_mode:
15792     case mask_mode:
15793       if ((modrm.reg + add) > 0x7)
15794         {
15795           oappend ("(bad)");
15796           return;
15797         }
15798       oappend (names_mask[modrm.reg + add]);
15799       break;
15800     default:
15801       oappend (INTERNAL_DISASSEMBLER_ERROR);
15802       break;
15803     }
15804 }
15805
15806 static bfd_vma
15807 get64 (void)
15808 {
15809   bfd_vma x;
15810 #ifdef BFD64
15811   unsigned int a;
15812   unsigned int b;
15813
15814   FETCH_DATA (the_info, codep + 8);
15815   a = *codep++ & 0xff;
15816   a |= (*codep++ & 0xff) << 8;
15817   a |= (*codep++ & 0xff) << 16;
15818   a |= (*codep++ & 0xffu) << 24;
15819   b = *codep++ & 0xff;
15820   b |= (*codep++ & 0xff) << 8;
15821   b |= (*codep++ & 0xff) << 16;
15822   b |= (*codep++ & 0xffu) << 24;
15823   x = a + ((bfd_vma) b << 32);
15824 #else
15825   abort ();
15826   x = 0;
15827 #endif
15828   return x;
15829 }
15830
15831 static bfd_signed_vma
15832 get32 (void)
15833 {
15834   bfd_signed_vma x = 0;
15835
15836   FETCH_DATA (the_info, codep + 4);
15837   x = *codep++ & (bfd_signed_vma) 0xff;
15838   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15839   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15840   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15841   return x;
15842 }
15843
15844 static bfd_signed_vma
15845 get32s (void)
15846 {
15847   bfd_signed_vma x = 0;
15848
15849   FETCH_DATA (the_info, codep + 4);
15850   x = *codep++ & (bfd_signed_vma) 0xff;
15851   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15852   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15853   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15854
15855   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15856
15857   return x;
15858 }
15859
15860 static int
15861 get16 (void)
15862 {
15863   int x = 0;
15864
15865   FETCH_DATA (the_info, codep + 2);
15866   x = *codep++ & 0xff;
15867   x |= (*codep++ & 0xff) << 8;
15868   return x;
15869 }
15870
15871 static void
15872 set_op (bfd_vma op, int riprel)
15873 {
15874   op_index[op_ad] = op_ad;
15875   if (address_mode == mode_64bit)
15876     {
15877       op_address[op_ad] = op;
15878       op_riprel[op_ad] = riprel;
15879     }
15880   else
15881     {
15882       /* Mask to get a 32-bit address.  */
15883       op_address[op_ad] = op & 0xffffffff;
15884       op_riprel[op_ad] = riprel & 0xffffffff;
15885     }
15886 }
15887
15888 static void
15889 OP_REG (int code, int sizeflag)
15890 {
15891   const char *s;
15892   int add;
15893
15894   switch (code)
15895     {
15896     case es_reg: case ss_reg: case cs_reg:
15897     case ds_reg: case fs_reg: case gs_reg:
15898       oappend (names_seg[code - es_reg]);
15899       return;
15900     }
15901
15902   USED_REX (REX_B);
15903   if (rex & REX_B)
15904     add = 8;
15905   else
15906     add = 0;
15907
15908   switch (code)
15909     {
15910     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15911     case sp_reg: case bp_reg: case si_reg: case di_reg:
15912       s = names16[code - ax_reg + add];
15913       break;
15914     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15915     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15916       USED_REX (0);
15917       if (rex)
15918         s = names8rex[code - al_reg + add];
15919       else
15920         s = names8[code - al_reg];
15921       break;
15922     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15923     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15924       if (address_mode == mode_64bit
15925           && ((sizeflag & DFLAG) || (rex & REX_W)))
15926         {
15927           s = names64[code - rAX_reg + add];
15928           break;
15929         }
15930       code += eAX_reg - rAX_reg;
15931       /* Fall through.  */
15932     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15933     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15934       USED_REX (REX_W);
15935       if (rex & REX_W)
15936         s = names64[code - eAX_reg + add];
15937       else
15938         {
15939           if (sizeflag & DFLAG)
15940             s = names32[code - eAX_reg + add];
15941           else
15942             s = names16[code - eAX_reg + add];
15943           used_prefixes |= (prefixes & PREFIX_DATA);
15944         }
15945       break;
15946     default:
15947       s = INTERNAL_DISASSEMBLER_ERROR;
15948       break;
15949     }
15950   oappend (s);
15951 }
15952
15953 static void
15954 OP_IMREG (int code, int sizeflag)
15955 {
15956   const char *s;
15957
15958   switch (code)
15959     {
15960     case indir_dx_reg:
15961       if (intel_syntax)
15962         s = "dx";
15963       else
15964         s = "(%dx)";
15965       break;
15966     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15967     case sp_reg: case bp_reg: case si_reg: case di_reg:
15968       s = names16[code - ax_reg];
15969       break;
15970     case es_reg: case ss_reg: case cs_reg:
15971     case ds_reg: case fs_reg: case gs_reg:
15972       s = names_seg[code - es_reg];
15973       break;
15974     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15975     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15976       USED_REX (0);
15977       if (rex)
15978         s = names8rex[code - al_reg];
15979       else
15980         s = names8[code - al_reg];
15981       break;
15982     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15983     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15984       USED_REX (REX_W);
15985       if (rex & REX_W)
15986         s = names64[code - eAX_reg];
15987       else
15988         {
15989           if (sizeflag & DFLAG)
15990             s = names32[code - eAX_reg];
15991           else
15992             s = names16[code - eAX_reg];
15993           used_prefixes |= (prefixes & PREFIX_DATA);
15994         }
15995       break;
15996     case z_mode_ax_reg:
15997       if ((rex & REX_W) || (sizeflag & DFLAG))
15998         s = *names32;
15999       else
16000         s = *names16;
16001       if (!(rex & REX_W))
16002         used_prefixes |= (prefixes & PREFIX_DATA);
16003       break;
16004     default:
16005       s = INTERNAL_DISASSEMBLER_ERROR;
16006       break;
16007     }
16008   oappend (s);
16009 }
16010
16011 static void
16012 OP_I (int bytemode, int sizeflag)
16013 {
16014   bfd_signed_vma op;
16015   bfd_signed_vma mask = -1;
16016
16017   switch (bytemode)
16018     {
16019     case b_mode:
16020       FETCH_DATA (the_info, codep + 1);
16021       op = *codep++;
16022       mask = 0xff;
16023       break;
16024     case q_mode:
16025       if (address_mode == mode_64bit)
16026         {
16027           op = get32s ();
16028           break;
16029         }
16030       /* Fall through.  */
16031     case v_mode:
16032       USED_REX (REX_W);
16033       if (rex & REX_W)
16034         op = get32s ();
16035       else
16036         {
16037           if (sizeflag & DFLAG)
16038             {
16039               op = get32 ();
16040               mask = 0xffffffff;
16041             }
16042           else
16043             {
16044               op = get16 ();
16045               mask = 0xfffff;
16046             }
16047           used_prefixes |= (prefixes & PREFIX_DATA);
16048         }
16049       break;
16050     case w_mode:
16051       mask = 0xfffff;
16052       op = get16 ();
16053       break;
16054     case const_1_mode:
16055       if (intel_syntax)
16056         oappend ("1");
16057       return;
16058     default:
16059       oappend (INTERNAL_DISASSEMBLER_ERROR);
16060       return;
16061     }
16062
16063   op &= mask;
16064   scratchbuf[0] = '$';
16065   print_operand_value (scratchbuf + 1, 1, op);
16066   oappend_maybe_intel (scratchbuf);
16067   scratchbuf[0] = '\0';
16068 }
16069
16070 static void
16071 OP_I64 (int bytemode, int sizeflag)
16072 {
16073   bfd_signed_vma op;
16074   bfd_signed_vma mask = -1;
16075
16076   if (address_mode != mode_64bit)
16077     {
16078       OP_I (bytemode, sizeflag);
16079       return;
16080     }
16081
16082   switch (bytemode)
16083     {
16084     case b_mode:
16085       FETCH_DATA (the_info, codep + 1);
16086       op = *codep++;
16087       mask = 0xff;
16088       break;
16089     case v_mode:
16090       USED_REX (REX_W);
16091       if (rex & REX_W)
16092         op = get64 ();
16093       else
16094         {
16095           if (sizeflag & DFLAG)
16096             {
16097               op = get32 ();
16098               mask = 0xffffffff;
16099             }
16100           else
16101             {
16102               op = get16 ();
16103               mask = 0xfffff;
16104             }
16105           used_prefixes |= (prefixes & PREFIX_DATA);
16106         }
16107       break;
16108     case w_mode:
16109       mask = 0xfffff;
16110       op = get16 ();
16111       break;
16112     default:
16113       oappend (INTERNAL_DISASSEMBLER_ERROR);
16114       return;
16115     }
16116
16117   op &= mask;
16118   scratchbuf[0] = '$';
16119   print_operand_value (scratchbuf + 1, 1, op);
16120   oappend_maybe_intel (scratchbuf);
16121   scratchbuf[0] = '\0';
16122 }
16123
16124 static void
16125 OP_sI (int bytemode, int sizeflag)
16126 {
16127   bfd_signed_vma op;
16128
16129   switch (bytemode)
16130     {
16131     case b_mode:
16132     case b_T_mode:
16133       FETCH_DATA (the_info, codep + 1);
16134       op = *codep++;
16135       if ((op & 0x80) != 0)
16136         op -= 0x100;
16137       if (bytemode == b_T_mode)
16138         {
16139           if (address_mode != mode_64bit
16140               || !((sizeflag & DFLAG) || (rex & REX_W)))
16141             {
16142               /* The operand-size prefix is overridden by a REX prefix.  */
16143               if ((sizeflag & DFLAG) || (rex & REX_W))
16144                 op &= 0xffffffff;
16145               else
16146                 op &= 0xffff;
16147           }
16148         }
16149       else
16150         {
16151           if (!(rex & REX_W))
16152             {
16153               if (sizeflag & DFLAG)
16154                 op &= 0xffffffff;
16155               else
16156                 op &= 0xffff;
16157             }
16158         }
16159       break;
16160     case v_mode:
16161       /* The operand-size prefix is overridden by a REX prefix.  */
16162       if ((sizeflag & DFLAG) || (rex & REX_W))
16163         op = get32s ();
16164       else
16165         op = get16 ();
16166       break;
16167     default:
16168       oappend (INTERNAL_DISASSEMBLER_ERROR);
16169       return;
16170     }
16171
16172   scratchbuf[0] = '$';
16173   print_operand_value (scratchbuf + 1, 1, op);
16174   oappend_maybe_intel (scratchbuf);
16175 }
16176
16177 static void
16178 OP_J (int bytemode, int sizeflag)
16179 {
16180   bfd_vma disp;
16181   bfd_vma mask = -1;
16182   bfd_vma segment = 0;
16183
16184   switch (bytemode)
16185     {
16186     case b_mode:
16187       FETCH_DATA (the_info, codep + 1);
16188       disp = *codep++;
16189       if ((disp & 0x80) != 0)
16190         disp -= 0x100;
16191       break;
16192     case v_mode:
16193       if (isa64 == amd64)
16194         USED_REX (REX_W);
16195       if ((sizeflag & DFLAG)
16196           || (address_mode == mode_64bit
16197               && (isa64 != amd64 || (rex & REX_W))))
16198         disp = get32s ();
16199       else
16200         {
16201           disp = get16 ();
16202           if ((disp & 0x8000) != 0)
16203             disp -= 0x10000;
16204           /* In 16bit mode, address is wrapped around at 64k within
16205              the same segment.  Otherwise, a data16 prefix on a jump
16206              instruction means that the pc is masked to 16 bits after
16207              the displacement is added!  */
16208           mask = 0xffff;
16209           if ((prefixes & PREFIX_DATA) == 0)
16210             segment = ((start_pc + (codep - start_codep))
16211                        & ~((bfd_vma) 0xffff));
16212         }
16213       if (address_mode != mode_64bit
16214           || (isa64 == amd64 && !(rex & REX_W)))
16215         used_prefixes |= (prefixes & PREFIX_DATA);
16216       break;
16217     default:
16218       oappend (INTERNAL_DISASSEMBLER_ERROR);
16219       return;
16220     }
16221   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16222   set_op (disp, 0);
16223   print_operand_value (scratchbuf, 1, disp);
16224   oappend (scratchbuf);
16225 }
16226
16227 static void
16228 OP_SEG (int bytemode, int sizeflag)
16229 {
16230   if (bytemode == w_mode)
16231     oappend (names_seg[modrm.reg]);
16232   else
16233     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16234 }
16235
16236 static void
16237 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16238 {
16239   int seg, offset;
16240
16241   if (sizeflag & DFLAG)
16242     {
16243       offset = get32 ();
16244       seg = get16 ();
16245     }
16246   else
16247     {
16248       offset = get16 ();
16249       seg = get16 ();
16250     }
16251   used_prefixes |= (prefixes & PREFIX_DATA);
16252   if (intel_syntax)
16253     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16254   else
16255     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16256   oappend (scratchbuf);
16257 }
16258
16259 static void
16260 OP_OFF (int bytemode, int sizeflag)
16261 {
16262   bfd_vma off;
16263
16264   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16265     intel_operand_size (bytemode, sizeflag);
16266   append_seg ();
16267
16268   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16269     off = get32 ();
16270   else
16271     off = get16 ();
16272
16273   if (intel_syntax)
16274     {
16275       if (!active_seg_prefix)
16276         {
16277           oappend (names_seg[ds_reg - es_reg]);
16278           oappend (":");
16279         }
16280     }
16281   print_operand_value (scratchbuf, 1, off);
16282   oappend (scratchbuf);
16283 }
16284
16285 static void
16286 OP_OFF64 (int bytemode, int sizeflag)
16287 {
16288   bfd_vma off;
16289
16290   if (address_mode != mode_64bit
16291       || (prefixes & PREFIX_ADDR))
16292     {
16293       OP_OFF (bytemode, sizeflag);
16294       return;
16295     }
16296
16297   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16298     intel_operand_size (bytemode, sizeflag);
16299   append_seg ();
16300
16301   off = get64 ();
16302
16303   if (intel_syntax)
16304     {
16305       if (!active_seg_prefix)
16306         {
16307           oappend (names_seg[ds_reg - es_reg]);
16308           oappend (":");
16309         }
16310     }
16311   print_operand_value (scratchbuf, 1, off);
16312   oappend (scratchbuf);
16313 }
16314
16315 static void
16316 ptr_reg (int code, int sizeflag)
16317 {
16318   const char *s;
16319
16320   *obufp++ = open_char;
16321   used_prefixes |= (prefixes & PREFIX_ADDR);
16322   if (address_mode == mode_64bit)
16323     {
16324       if (!(sizeflag & AFLAG))
16325         s = names32[code - eAX_reg];
16326       else
16327         s = names64[code - eAX_reg];
16328     }
16329   else if (sizeflag & AFLAG)
16330     s = names32[code - eAX_reg];
16331   else
16332     s = names16[code - eAX_reg];
16333   oappend (s);
16334   *obufp++ = close_char;
16335   *obufp = 0;
16336 }
16337
16338 static void
16339 OP_ESreg (int code, int sizeflag)
16340 {
16341   if (intel_syntax)
16342     {
16343       switch (codep[-1])
16344         {
16345         case 0x6d:      /* insw/insl */
16346           intel_operand_size (z_mode, sizeflag);
16347           break;
16348         case 0xa5:      /* movsw/movsl/movsq */
16349         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16350         case 0xab:      /* stosw/stosl */
16351         case 0xaf:      /* scasw/scasl */
16352           intel_operand_size (v_mode, sizeflag);
16353           break;
16354         default:
16355           intel_operand_size (b_mode, sizeflag);
16356         }
16357     }
16358   oappend_maybe_intel ("%es:");
16359   ptr_reg (code, sizeflag);
16360 }
16361
16362 static void
16363 OP_DSreg (int code, int sizeflag)
16364 {
16365   if (intel_syntax)
16366     {
16367       switch (codep[-1])
16368         {
16369         case 0x6f:      /* outsw/outsl */
16370           intel_operand_size (z_mode, sizeflag);
16371           break;
16372         case 0xa5:      /* movsw/movsl/movsq */
16373         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16374         case 0xad:      /* lodsw/lodsl/lodsq */
16375           intel_operand_size (v_mode, sizeflag);
16376           break;
16377         default:
16378           intel_operand_size (b_mode, sizeflag);
16379         }
16380     }
16381   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16382      default segment register DS is printed.  */
16383   if (!active_seg_prefix)
16384     active_seg_prefix = PREFIX_DS;
16385   append_seg ();
16386   ptr_reg (code, sizeflag);
16387 }
16388
16389 static void
16390 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16391 {
16392   int add;
16393   if (rex & REX_R)
16394     {
16395       USED_REX (REX_R);
16396       add = 8;
16397     }
16398   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16399     {
16400       all_prefixes[last_lock_prefix] = 0;
16401       used_prefixes |= PREFIX_LOCK;
16402       add = 8;
16403     }
16404   else
16405     add = 0;
16406   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16407   oappend_maybe_intel (scratchbuf);
16408 }
16409
16410 static void
16411 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16412 {
16413   int add;
16414   USED_REX (REX_R);
16415   if (rex & REX_R)
16416     add = 8;
16417   else
16418     add = 0;
16419   if (intel_syntax)
16420     sprintf (scratchbuf, "db%d", modrm.reg + add);
16421   else
16422     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16423   oappend (scratchbuf);
16424 }
16425
16426 static void
16427 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16428 {
16429   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16430   oappend_maybe_intel (scratchbuf);
16431 }
16432
16433 static void
16434 OP_R (int bytemode, int sizeflag)
16435 {
16436   /* Skip mod/rm byte.  */
16437   MODRM_CHECK;
16438   codep++;
16439   OP_E_register (bytemode, sizeflag);
16440 }
16441
16442 static void
16443 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16444 {
16445   int reg = modrm.reg;
16446   const char **names;
16447
16448   used_prefixes |= (prefixes & PREFIX_DATA);
16449   if (prefixes & PREFIX_DATA)
16450     {
16451       names = names_xmm;
16452       USED_REX (REX_R);
16453       if (rex & REX_R)
16454         reg += 8;
16455     }
16456   else
16457     names = names_mm;
16458   oappend (names[reg]);
16459 }
16460
16461 static void
16462 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16463 {
16464   int reg = modrm.reg;
16465   const char **names;
16466
16467   USED_REX (REX_R);
16468   if (rex & REX_R)
16469     reg += 8;
16470   if (vex.evex)
16471     {
16472       if (!vex.r)
16473         reg += 16;
16474     }
16475
16476   if (need_vex
16477       && bytemode != xmm_mode
16478       && bytemode != xmmq_mode
16479       && bytemode != evex_half_bcst_xmmq_mode
16480       && bytemode != ymm_mode
16481       && bytemode != scalar_mode)
16482     {
16483       switch (vex.length)
16484         {
16485         case 128:
16486           names = names_xmm;
16487           break;
16488         case 256:
16489           if (vex.w
16490               || (bytemode != vex_vsib_q_w_dq_mode
16491                   && bytemode != vex_vsib_q_w_d_mode))
16492             names = names_ymm;
16493           else
16494             names = names_xmm;
16495           break;
16496         case 512:
16497           names = names_zmm;
16498           break;
16499         default:
16500           abort ();
16501         }
16502     }
16503   else if (bytemode == xmmq_mode
16504            || bytemode == evex_half_bcst_xmmq_mode)
16505     {
16506       switch (vex.length)
16507         {
16508         case 128:
16509         case 256:
16510           names = names_xmm;
16511           break;
16512         case 512:
16513           names = names_ymm;
16514           break;
16515         default:
16516           abort ();
16517         }
16518     }
16519   else if (bytemode == ymm_mode)
16520     names = names_ymm;
16521   else
16522     names = names_xmm;
16523   oappend (names[reg]);
16524 }
16525
16526 static void
16527 OP_EM (int bytemode, int sizeflag)
16528 {
16529   int reg;
16530   const char **names;
16531
16532   if (modrm.mod != 3)
16533     {
16534       if (intel_syntax
16535           && (bytemode == v_mode || bytemode == v_swap_mode))
16536         {
16537           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16538           used_prefixes |= (prefixes & PREFIX_DATA);
16539         }
16540       OP_E (bytemode, sizeflag);
16541       return;
16542     }
16543
16544   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16545     swap_operand ();
16546
16547   /* Skip mod/rm byte.  */
16548   MODRM_CHECK;
16549   codep++;
16550   used_prefixes |= (prefixes & PREFIX_DATA);
16551   reg = modrm.rm;
16552   if (prefixes & PREFIX_DATA)
16553     {
16554       names = names_xmm;
16555       USED_REX (REX_B);
16556       if (rex & REX_B)
16557         reg += 8;
16558     }
16559   else
16560     names = names_mm;
16561   oappend (names[reg]);
16562 }
16563
16564 /* cvt* are the only instructions in sse2 which have
16565    both SSE and MMX operands and also have 0x66 prefix
16566    in their opcode. 0x66 was originally used to differentiate
16567    between SSE and MMX instruction(operands). So we have to handle the
16568    cvt* separately using OP_EMC and OP_MXC */
16569 static void
16570 OP_EMC (int bytemode, int sizeflag)
16571 {
16572   if (modrm.mod != 3)
16573     {
16574       if (intel_syntax && bytemode == v_mode)
16575         {
16576           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16577           used_prefixes |= (prefixes & PREFIX_DATA);
16578         }
16579       OP_E (bytemode, sizeflag);
16580       return;
16581     }
16582
16583   /* Skip mod/rm byte.  */
16584   MODRM_CHECK;
16585   codep++;
16586   used_prefixes |= (prefixes & PREFIX_DATA);
16587   oappend (names_mm[modrm.rm]);
16588 }
16589
16590 static void
16591 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16592 {
16593   used_prefixes |= (prefixes & PREFIX_DATA);
16594   oappend (names_mm[modrm.reg]);
16595 }
16596
16597 static void
16598 OP_EX (int bytemode, int sizeflag)
16599 {
16600   int reg;
16601   const char **names;
16602
16603   /* Skip mod/rm byte.  */
16604   MODRM_CHECK;
16605   codep++;
16606
16607   if (modrm.mod != 3)
16608     {
16609       OP_E_memory (bytemode, sizeflag);
16610       return;
16611     }
16612
16613   reg = modrm.rm;
16614   USED_REX (REX_B);
16615   if (rex & REX_B)
16616     reg += 8;
16617   if (vex.evex)
16618     {
16619       USED_REX (REX_X);
16620       if ((rex & REX_X))
16621         reg += 16;
16622     }
16623
16624   if ((sizeflag & SUFFIX_ALWAYS)
16625       && (bytemode == x_swap_mode
16626           || bytemode == d_swap_mode
16627           || bytemode == dqw_swap_mode
16628           || bytemode == d_scalar_swap_mode
16629           || bytemode == q_swap_mode
16630           || bytemode == q_scalar_swap_mode))
16631     swap_operand ();
16632
16633   if (need_vex
16634       && bytemode != xmm_mode
16635       && bytemode != xmmdw_mode
16636       && bytemode != xmmqd_mode
16637       && bytemode != xmm_mb_mode
16638       && bytemode != xmm_mw_mode
16639       && bytemode != xmm_md_mode
16640       && bytemode != xmm_mq_mode
16641       && bytemode != xmm_mdq_mode
16642       && bytemode != xmmq_mode
16643       && bytemode != evex_half_bcst_xmmq_mode
16644       && bytemode != ymm_mode
16645       && bytemode != d_scalar_mode
16646       && bytemode != d_scalar_swap_mode
16647       && bytemode != q_scalar_mode
16648       && bytemode != q_scalar_swap_mode
16649       && bytemode != vex_scalar_w_dq_mode)
16650     {
16651       switch (vex.length)
16652         {
16653         case 128:
16654           names = names_xmm;
16655           break;
16656         case 256:
16657           names = names_ymm;
16658           break;
16659         case 512:
16660           names = names_zmm;
16661           break;
16662         default:
16663           abort ();
16664         }
16665     }
16666   else if (bytemode == xmmq_mode
16667            || bytemode == evex_half_bcst_xmmq_mode)
16668     {
16669       switch (vex.length)
16670         {
16671         case 128:
16672         case 256:
16673           names = names_xmm;
16674           break;
16675         case 512:
16676           names = names_ymm;
16677           break;
16678         default:
16679           abort ();
16680         }
16681     }
16682   else if (bytemode == ymm_mode)
16683     names = names_ymm;
16684   else
16685     names = names_xmm;
16686   oappend (names[reg]);
16687 }
16688
16689 static void
16690 OP_MS (int bytemode, int sizeflag)
16691 {
16692   if (modrm.mod == 3)
16693     OP_EM (bytemode, sizeflag);
16694   else
16695     BadOp ();
16696 }
16697
16698 static void
16699 OP_XS (int bytemode, int sizeflag)
16700 {
16701   if (modrm.mod == 3)
16702     OP_EX (bytemode, sizeflag);
16703   else
16704     BadOp ();
16705 }
16706
16707 static void
16708 OP_M (int bytemode, int sizeflag)
16709 {
16710   if (modrm.mod == 3)
16711     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16712     BadOp ();
16713   else
16714     OP_E (bytemode, sizeflag);
16715 }
16716
16717 static void
16718 OP_0f07 (int bytemode, int sizeflag)
16719 {
16720   if (modrm.mod != 3 || modrm.rm != 0)
16721     BadOp ();
16722   else
16723     OP_E (bytemode, sizeflag);
16724 }
16725
16726 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16727    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16728
16729 static void
16730 NOP_Fixup1 (int bytemode, int sizeflag)
16731 {
16732   if ((prefixes & PREFIX_DATA) != 0
16733       || (rex != 0
16734           && rex != 0x48
16735           && address_mode == mode_64bit))
16736     OP_REG (bytemode, sizeflag);
16737   else
16738     strcpy (obuf, "nop");
16739 }
16740
16741 static void
16742 NOP_Fixup2 (int bytemode, int sizeflag)
16743 {
16744   if ((prefixes & PREFIX_DATA) != 0
16745       || (rex != 0
16746           && rex != 0x48
16747           && address_mode == mode_64bit))
16748     OP_IMREG (bytemode, sizeflag);
16749 }
16750
16751 static const char *const Suffix3DNow[] = {
16752 /* 00 */        NULL,           NULL,           NULL,           NULL,
16753 /* 04 */        NULL,           NULL,           NULL,           NULL,
16754 /* 08 */        NULL,           NULL,           NULL,           NULL,
16755 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16756 /* 10 */        NULL,           NULL,           NULL,           NULL,
16757 /* 14 */        NULL,           NULL,           NULL,           NULL,
16758 /* 18 */        NULL,           NULL,           NULL,           NULL,
16759 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16760 /* 20 */        NULL,           NULL,           NULL,           NULL,
16761 /* 24 */        NULL,           NULL,           NULL,           NULL,
16762 /* 28 */        NULL,           NULL,           NULL,           NULL,
16763 /* 2C */        NULL,           NULL,           NULL,           NULL,
16764 /* 30 */        NULL,           NULL,           NULL,           NULL,
16765 /* 34 */        NULL,           NULL,           NULL,           NULL,
16766 /* 38 */        NULL,           NULL,           NULL,           NULL,
16767 /* 3C */        NULL,           NULL,           NULL,           NULL,
16768 /* 40 */        NULL,           NULL,           NULL,           NULL,
16769 /* 44 */        NULL,           NULL,           NULL,           NULL,
16770 /* 48 */        NULL,           NULL,           NULL,           NULL,
16771 /* 4C */        NULL,           NULL,           NULL,           NULL,
16772 /* 50 */        NULL,           NULL,           NULL,           NULL,
16773 /* 54 */        NULL,           NULL,           NULL,           NULL,
16774 /* 58 */        NULL,           NULL,           NULL,           NULL,
16775 /* 5C */        NULL,           NULL,           NULL,           NULL,
16776 /* 60 */        NULL,           NULL,           NULL,           NULL,
16777 /* 64 */        NULL,           NULL,           NULL,           NULL,
16778 /* 68 */        NULL,           NULL,           NULL,           NULL,
16779 /* 6C */        NULL,           NULL,           NULL,           NULL,
16780 /* 70 */        NULL,           NULL,           NULL,           NULL,
16781 /* 74 */        NULL,           NULL,           NULL,           NULL,
16782 /* 78 */        NULL,           NULL,           NULL,           NULL,
16783 /* 7C */        NULL,           NULL,           NULL,           NULL,
16784 /* 80 */        NULL,           NULL,           NULL,           NULL,
16785 /* 84 */        NULL,           NULL,           NULL,           NULL,
16786 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16787 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16788 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16789 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16790 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16791 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16792 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16793 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16794 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16795 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16796 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16797 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16798 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16799 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16800 /* C0 */        NULL,           NULL,           NULL,           NULL,
16801 /* C4 */        NULL,           NULL,           NULL,           NULL,
16802 /* C8 */        NULL,           NULL,           NULL,           NULL,
16803 /* CC */        NULL,           NULL,           NULL,           NULL,
16804 /* D0 */        NULL,           NULL,           NULL,           NULL,
16805 /* D4 */        NULL,           NULL,           NULL,           NULL,
16806 /* D8 */        NULL,           NULL,           NULL,           NULL,
16807 /* DC */        NULL,           NULL,           NULL,           NULL,
16808 /* E0 */        NULL,           NULL,           NULL,           NULL,
16809 /* E4 */        NULL,           NULL,           NULL,           NULL,
16810 /* E8 */        NULL,           NULL,           NULL,           NULL,
16811 /* EC */        NULL,           NULL,           NULL,           NULL,
16812 /* F0 */        NULL,           NULL,           NULL,           NULL,
16813 /* F4 */        NULL,           NULL,           NULL,           NULL,
16814 /* F8 */        NULL,           NULL,           NULL,           NULL,
16815 /* FC */        NULL,           NULL,           NULL,           NULL,
16816 };
16817
16818 static void
16819 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16820 {
16821   const char *mnemonic;
16822
16823   FETCH_DATA (the_info, codep + 1);
16824   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16825      place where an 8-bit immediate would normally go.  ie. the last
16826      byte of the instruction.  */
16827   obufp = mnemonicendp;
16828   mnemonic = Suffix3DNow[*codep++ & 0xff];
16829   if (mnemonic)
16830     oappend (mnemonic);
16831   else
16832     {
16833       /* Since a variable sized modrm/sib chunk is between the start
16834          of the opcode (0x0f0f) and the opcode suffix, we need to do
16835          all the modrm processing first, and don't know until now that
16836          we have a bad opcode.  This necessitates some cleaning up.  */
16837       op_out[0][0] = '\0';
16838       op_out[1][0] = '\0';
16839       BadOp ();
16840     }
16841   mnemonicendp = obufp;
16842 }
16843
16844 static struct op simd_cmp_op[] =
16845 {
16846   { STRING_COMMA_LEN ("eq") },
16847   { STRING_COMMA_LEN ("lt") },
16848   { STRING_COMMA_LEN ("le") },
16849   { STRING_COMMA_LEN ("unord") },
16850   { STRING_COMMA_LEN ("neq") },
16851   { STRING_COMMA_LEN ("nlt") },
16852   { STRING_COMMA_LEN ("nle") },
16853   { STRING_COMMA_LEN ("ord") }
16854 };
16855
16856 static void
16857 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16858 {
16859   unsigned int cmp_type;
16860
16861   FETCH_DATA (the_info, codep + 1);
16862   cmp_type = *codep++ & 0xff;
16863   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16864     {
16865       char suffix [3];
16866       char *p = mnemonicendp - 2;
16867       suffix[0] = p[0];
16868       suffix[1] = p[1];
16869       suffix[2] = '\0';
16870       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16871       mnemonicendp += simd_cmp_op[cmp_type].len;
16872     }
16873   else
16874     {
16875       /* We have a reserved extension byte.  Output it directly.  */
16876       scratchbuf[0] = '$';
16877       print_operand_value (scratchbuf + 1, 1, cmp_type);
16878       oappend_maybe_intel (scratchbuf);
16879       scratchbuf[0] = '\0';
16880     }
16881 }
16882
16883 static void
16884 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16885           int sizeflag ATTRIBUTE_UNUSED)
16886 {
16887   /* mwaitx %eax,%ecx,%ebx */
16888   if (!intel_syntax)
16889     {
16890       const char **names = (address_mode == mode_64bit
16891                             ? names64 : names32);
16892       strcpy (op_out[0], names[0]);
16893       strcpy (op_out[1], names[1]);
16894       strcpy (op_out[2], names[3]);
16895       two_source_ops = 1;
16896     }
16897   /* Skip mod/rm byte.  */
16898   MODRM_CHECK;
16899   codep++;
16900 }
16901
16902 static void
16903 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16904           int sizeflag ATTRIBUTE_UNUSED)
16905 {
16906   /* mwait %eax,%ecx  */
16907   if (!intel_syntax)
16908     {
16909       const char **names = (address_mode == mode_64bit
16910                             ? names64 : names32);
16911       strcpy (op_out[0], names[0]);
16912       strcpy (op_out[1], names[1]);
16913       two_source_ops = 1;
16914     }
16915   /* Skip mod/rm byte.  */
16916   MODRM_CHECK;
16917   codep++;
16918 }
16919
16920 static void
16921 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16922             int sizeflag ATTRIBUTE_UNUSED)
16923 {
16924   /* monitor %eax,%ecx,%edx"  */
16925   if (!intel_syntax)
16926     {
16927       const char **op1_names;
16928       const char **names = (address_mode == mode_64bit
16929                             ? names64 : names32);
16930
16931       if (!(prefixes & PREFIX_ADDR))
16932         op1_names = (address_mode == mode_16bit
16933                      ? names16 : names);
16934       else
16935         {
16936           /* Remove "addr16/addr32".  */
16937           all_prefixes[last_addr_prefix] = 0;
16938           op1_names = (address_mode != mode_32bit
16939                        ? names32 : names16);
16940           used_prefixes |= PREFIX_ADDR;
16941         }
16942       strcpy (op_out[0], op1_names[0]);
16943       strcpy (op_out[1], names[1]);
16944       strcpy (op_out[2], names[2]);
16945       two_source_ops = 1;
16946     }
16947   /* Skip mod/rm byte.  */
16948   MODRM_CHECK;
16949   codep++;
16950 }
16951
16952 static void
16953 BadOp (void)
16954 {
16955   /* Throw away prefixes and 1st. opcode byte.  */
16956   codep = insn_codep + 1;
16957   oappend ("(bad)");
16958 }
16959
16960 static void
16961 REP_Fixup (int bytemode, int sizeflag)
16962 {
16963   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16964      lods and stos.  */
16965   if (prefixes & PREFIX_REPZ)
16966     all_prefixes[last_repz_prefix] = REP_PREFIX;
16967
16968   switch (bytemode)
16969     {
16970     case al_reg:
16971     case eAX_reg:
16972     case indir_dx_reg:
16973       OP_IMREG (bytemode, sizeflag);
16974       break;
16975     case eDI_reg:
16976       OP_ESreg (bytemode, sizeflag);
16977       break;
16978     case eSI_reg:
16979       OP_DSreg (bytemode, sizeflag);
16980       break;
16981     default:
16982       abort ();
16983       break;
16984     }
16985 }
16986
16987 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16988    "bnd".  */
16989
16990 static void
16991 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16992 {
16993   if (prefixes & PREFIX_REPNZ)
16994     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16995 }
16996
16997 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16998    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16999  */
17000
17001 static void
17002 HLE_Fixup1 (int bytemode, int sizeflag)
17003 {
17004   if (modrm.mod != 3
17005       && (prefixes & PREFIX_LOCK) != 0)
17006     {
17007       if (prefixes & PREFIX_REPZ)
17008         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17009       if (prefixes & PREFIX_REPNZ)
17010         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17011     }
17012
17013   OP_E (bytemode, sizeflag);
17014 }
17015
17016 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
17017    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
17018  */
17019
17020 static void
17021 HLE_Fixup2 (int bytemode, int sizeflag)
17022 {
17023   if (modrm.mod != 3)
17024     {
17025       if (prefixes & PREFIX_REPZ)
17026         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17027       if (prefixes & PREFIX_REPNZ)
17028         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17029     }
17030
17031   OP_E (bytemode, sizeflag);
17032 }
17033
17034 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
17035    "xrelease" for memory operand.  No check for LOCK prefix.   */
17036
17037 static void
17038 HLE_Fixup3 (int bytemode, int sizeflag)
17039 {
17040   if (modrm.mod != 3
17041       && last_repz_prefix > last_repnz_prefix
17042       && (prefixes & PREFIX_REPZ) != 0)
17043     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17044
17045   OP_E (bytemode, sizeflag);
17046 }
17047
17048 static void
17049 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
17050 {
17051   USED_REX (REX_W);
17052   if (rex & REX_W)
17053     {
17054       /* Change cmpxchg8b to cmpxchg16b.  */
17055       char *p = mnemonicendp - 2;
17056       mnemonicendp = stpcpy (p, "16b");
17057       bytemode = o_mode;
17058     }
17059   else if ((prefixes & PREFIX_LOCK) != 0)
17060     {
17061       if (prefixes & PREFIX_REPZ)
17062         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17063       if (prefixes & PREFIX_REPNZ)
17064         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17065     }
17066
17067   OP_M (bytemode, sizeflag);
17068 }
17069
17070 static void
17071 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
17072 {
17073   const char **names;
17074
17075   if (need_vex)
17076     {
17077       switch (vex.length)
17078         {
17079         case 128:
17080           names = names_xmm;
17081           break;
17082         case 256:
17083           names = names_ymm;
17084           break;
17085         default:
17086           abort ();
17087         }
17088     }
17089   else
17090     names = names_xmm;
17091   oappend (names[reg]);
17092 }
17093
17094 static void
17095 CRC32_Fixup (int bytemode, int sizeflag)
17096 {
17097   /* Add proper suffix to "crc32".  */
17098   char *p = mnemonicendp;
17099
17100   switch (bytemode)
17101     {
17102     case b_mode:
17103       if (intel_syntax)
17104         goto skip;
17105
17106       *p++ = 'b';
17107       break;
17108     case v_mode:
17109       if (intel_syntax)
17110         goto skip;
17111
17112       USED_REX (REX_W);
17113       if (rex & REX_W)
17114         *p++ = 'q';
17115       else
17116         {
17117           if (sizeflag & DFLAG)
17118             *p++ = 'l';
17119           else
17120             *p++ = 'w';
17121           used_prefixes |= (prefixes & PREFIX_DATA);
17122         }
17123       break;
17124     default:
17125       oappend (INTERNAL_DISASSEMBLER_ERROR);
17126       break;
17127     }
17128   mnemonicendp = p;
17129   *p = '\0';
17130
17131 skip:
17132   if (modrm.mod == 3)
17133     {
17134       int add;
17135
17136       /* Skip mod/rm byte.  */
17137       MODRM_CHECK;
17138       codep++;
17139
17140       USED_REX (REX_B);
17141       add = (rex & REX_B) ? 8 : 0;
17142       if (bytemode == b_mode)
17143         {
17144           USED_REX (0);
17145           if (rex)
17146             oappend (names8rex[modrm.rm + add]);
17147           else
17148             oappend (names8[modrm.rm + add]);
17149         }
17150       else
17151         {
17152           USED_REX (REX_W);
17153           if (rex & REX_W)
17154             oappend (names64[modrm.rm + add]);
17155           else if ((prefixes & PREFIX_DATA))
17156             oappend (names16[modrm.rm + add]);
17157           else
17158             oappend (names32[modrm.rm + add]);
17159         }
17160     }
17161   else
17162     OP_E (bytemode, sizeflag);
17163 }
17164
17165 static void
17166 FXSAVE_Fixup (int bytemode, int sizeflag)
17167 {
17168   /* Add proper suffix to "fxsave" and "fxrstor".  */
17169   USED_REX (REX_W);
17170   if (rex & REX_W)
17171     {
17172       char *p = mnemonicendp;
17173       *p++ = '6';
17174       *p++ = '4';
17175       *p = '\0';
17176       mnemonicendp = p;
17177     }
17178   OP_M (bytemode, sizeflag);
17179 }
17180
17181 /* Display the destination register operand for instructions with
17182    VEX. */
17183
17184 static void
17185 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17186 {
17187   int reg;
17188   const char **names;
17189
17190   if (!need_vex)
17191     abort ();
17192
17193   if (!need_vex_reg)
17194     return;
17195
17196   reg = vex.register_specifier;
17197   if (vex.evex)
17198     {
17199       if (!vex.v)
17200         reg += 16;
17201     }
17202
17203   if (bytemode == vex_scalar_mode)
17204     {
17205       oappend (names_xmm[reg]);
17206       return;
17207     }
17208
17209   switch (vex.length)
17210     {
17211     case 128:
17212       switch (bytemode)
17213         {
17214         case vex_mode:
17215         case vex128_mode:
17216         case vex_vsib_q_w_dq_mode:
17217         case vex_vsib_q_w_d_mode:
17218           names = names_xmm;
17219           break;
17220         case dq_mode:
17221           if (vex.w)
17222             names = names64;
17223           else
17224             names = names32;
17225           break;
17226         case mask_bd_mode:
17227         case mask_mode:
17228           if (reg > 0x7)
17229             {
17230               oappend ("(bad)");
17231               return;
17232             }
17233           names = names_mask;
17234           break;
17235         default:
17236           abort ();
17237           return;
17238         }
17239       break;
17240     case 256:
17241       switch (bytemode)
17242         {
17243         case vex_mode:
17244         case vex256_mode:
17245           names = names_ymm;
17246           break;
17247         case vex_vsib_q_w_dq_mode:
17248         case vex_vsib_q_w_d_mode:
17249           names = vex.w ? names_ymm : names_xmm;
17250           break;
17251         case mask_bd_mode:
17252         case mask_mode:
17253           if (reg > 0x7)
17254             {
17255               oappend ("(bad)");
17256               return;
17257             }
17258           names = names_mask;
17259           break;
17260         default:
17261           abort ();
17262           return;
17263         }
17264       break;
17265     case 512:
17266       names = names_zmm;
17267       break;
17268     default:
17269       abort ();
17270       break;
17271     }
17272   oappend (names[reg]);
17273 }
17274
17275 /* Get the VEX immediate byte without moving codep.  */
17276
17277 static unsigned char
17278 get_vex_imm8 (int sizeflag, int opnum)
17279 {
17280   int bytes_before_imm = 0;
17281
17282   if (modrm.mod != 3)
17283     {
17284       /* There are SIB/displacement bytes.  */
17285       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17286         {
17287           /* 32/64 bit address mode */
17288           int base = modrm.rm;
17289
17290           /* Check SIB byte.  */
17291           if (base == 4)
17292             {
17293               FETCH_DATA (the_info, codep + 1);
17294               base = *codep & 7;
17295               /* When decoding the third source, don't increase
17296                  bytes_before_imm as this has already been incremented
17297                  by one in OP_E_memory while decoding the second
17298                  source operand.  */
17299               if (opnum == 0)
17300                 bytes_before_imm++;
17301             }
17302
17303           /* Don't increase bytes_before_imm when decoding the third source,
17304              it has already been incremented by OP_E_memory while decoding
17305              the second source operand.  */
17306           if (opnum == 0)
17307             {
17308               switch (modrm.mod)
17309                 {
17310                   case 0:
17311                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17312                        SIB == 5, there is a 4 byte displacement.  */
17313                     if (base != 5)
17314                       /* No displacement. */
17315                       break;
17316                     /* Fall through.  */
17317                   case 2:
17318                     /* 4 byte displacement.  */
17319                     bytes_before_imm += 4;
17320                     break;
17321                   case 1:
17322                     /* 1 byte displacement.  */
17323                     bytes_before_imm++;
17324                     break;
17325                 }
17326             }
17327         }
17328       else
17329         {
17330           /* 16 bit address mode */
17331           /* Don't increase bytes_before_imm when decoding the third source,
17332              it has already been incremented by OP_E_memory while decoding
17333              the second source operand.  */
17334           if (opnum == 0)
17335             {
17336               switch (modrm.mod)
17337                 {
17338                 case 0:
17339                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17340                   if (modrm.rm != 6)
17341                     /* No displacement. */
17342                     break;
17343                   /* Fall through.  */
17344                 case 2:
17345                   /* 2 byte displacement.  */
17346                   bytes_before_imm += 2;
17347                   break;
17348                 case 1:
17349                   /* 1 byte displacement: when decoding the third source,
17350                      don't increase bytes_before_imm as this has already
17351                      been incremented by one in OP_E_memory while decoding
17352                      the second source operand.  */
17353                   if (opnum == 0)
17354                     bytes_before_imm++;
17355
17356                   break;
17357                 }
17358             }
17359         }
17360     }
17361
17362   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17363   return codep [bytes_before_imm];
17364 }
17365
17366 static void
17367 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17368 {
17369   const char **names;
17370
17371   if (reg == -1 && modrm.mod != 3)
17372     {
17373       OP_E_memory (bytemode, sizeflag);
17374       return;
17375     }
17376   else
17377     {
17378       if (reg == -1)
17379         {
17380           reg = modrm.rm;
17381           USED_REX (REX_B);
17382           if (rex & REX_B)
17383             reg += 8;
17384         }
17385       else if (reg > 7 && address_mode != mode_64bit)
17386         BadOp ();
17387     }
17388
17389   switch (vex.length)
17390     {
17391     case 128:
17392       names = names_xmm;
17393       break;
17394     case 256:
17395       names = names_ymm;
17396       break;
17397     default:
17398       abort ();
17399     }
17400   oappend (names[reg]);
17401 }
17402
17403 static void
17404 OP_EX_VexImmW (int bytemode, int sizeflag)
17405 {
17406   int reg = -1;
17407   static unsigned char vex_imm8;
17408
17409   if (vex_w_done == 0)
17410     {
17411       vex_w_done = 1;
17412
17413       /* Skip mod/rm byte.  */
17414       MODRM_CHECK;
17415       codep++;
17416
17417       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17418
17419       if (vex.w)
17420           reg = vex_imm8 >> 4;
17421
17422       OP_EX_VexReg (bytemode, sizeflag, reg);
17423     }
17424   else if (vex_w_done == 1)
17425     {
17426       vex_w_done = 2;
17427
17428       if (!vex.w)
17429           reg = vex_imm8 >> 4;
17430
17431       OP_EX_VexReg (bytemode, sizeflag, reg);
17432     }
17433   else
17434     {
17435       /* Output the imm8 directly.  */
17436       scratchbuf[0] = '$';
17437       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17438       oappend_maybe_intel (scratchbuf);
17439       scratchbuf[0] = '\0';
17440       codep++;
17441     }
17442 }
17443
17444 static void
17445 OP_Vex_2src (int bytemode, int sizeflag)
17446 {
17447   if (modrm.mod == 3)
17448     {
17449       int reg = modrm.rm;
17450       USED_REX (REX_B);
17451       if (rex & REX_B)
17452         reg += 8;
17453       oappend (names_xmm[reg]);
17454     }
17455   else
17456     {
17457       if (intel_syntax
17458           && (bytemode == v_mode || bytemode == v_swap_mode))
17459         {
17460           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17461           used_prefixes |= (prefixes & PREFIX_DATA);
17462         }
17463       OP_E (bytemode, sizeflag);
17464     }
17465 }
17466
17467 static void
17468 OP_Vex_2src_1 (int bytemode, int sizeflag)
17469 {
17470   if (modrm.mod == 3)
17471     {
17472       /* Skip mod/rm byte.   */
17473       MODRM_CHECK;
17474       codep++;
17475     }
17476
17477   if (vex.w)
17478     oappend (names_xmm[vex.register_specifier]);
17479   else
17480     OP_Vex_2src (bytemode, sizeflag);
17481 }
17482
17483 static void
17484 OP_Vex_2src_2 (int bytemode, int sizeflag)
17485 {
17486   if (vex.w)
17487     OP_Vex_2src (bytemode, sizeflag);
17488   else
17489     oappend (names_xmm[vex.register_specifier]);
17490 }
17491
17492 static void
17493 OP_EX_VexW (int bytemode, int sizeflag)
17494 {
17495   int reg = -1;
17496
17497   if (!vex_w_done)
17498     {
17499       vex_w_done = 1;
17500
17501       /* Skip mod/rm byte.  */
17502       MODRM_CHECK;
17503       codep++;
17504
17505       if (vex.w)
17506         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17507     }
17508   else
17509     {
17510       if (!vex.w)
17511         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17512     }
17513
17514   OP_EX_VexReg (bytemode, sizeflag, reg);
17515 }
17516
17517 static void
17518 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17519              int sizeflag ATTRIBUTE_UNUSED)
17520 {
17521   /* Skip the immediate byte and check for invalid bits.  */
17522   FETCH_DATA (the_info, codep + 1);
17523   if (*codep++ & 0xf)
17524     BadOp ();
17525 }
17526
17527 static void
17528 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17529 {
17530   int reg;
17531   const char **names;
17532
17533   FETCH_DATA (the_info, codep + 1);
17534   reg = *codep++;
17535
17536   if (bytemode != x_mode)
17537     abort ();
17538
17539   if (reg & 0xf)
17540       BadOp ();
17541
17542   reg >>= 4;
17543   if (reg > 7 && address_mode != mode_64bit)
17544     BadOp ();
17545
17546   switch (vex.length)
17547     {
17548     case 128:
17549       names = names_xmm;
17550       break;
17551     case 256:
17552       names = names_ymm;
17553       break;
17554     default:
17555       abort ();
17556     }
17557   oappend (names[reg]);
17558 }
17559
17560 static void
17561 OP_XMM_VexW (int bytemode, int sizeflag)
17562 {
17563   /* Turn off the REX.W bit since it is used for swapping operands
17564      now.  */
17565   rex &= ~REX_W;
17566   OP_XMM (bytemode, sizeflag);
17567 }
17568
17569 static void
17570 OP_EX_Vex (int bytemode, int sizeflag)
17571 {
17572   if (modrm.mod != 3)
17573     {
17574       if (vex.register_specifier != 0)
17575         BadOp ();
17576       need_vex_reg = 0;
17577     }
17578   OP_EX (bytemode, sizeflag);
17579 }
17580
17581 static void
17582 OP_XMM_Vex (int bytemode, int sizeflag)
17583 {
17584   if (modrm.mod != 3)
17585     {
17586       if (vex.register_specifier != 0)
17587         BadOp ();
17588       need_vex_reg = 0;
17589     }
17590   OP_XMM (bytemode, sizeflag);
17591 }
17592
17593 static void
17594 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17595 {
17596   switch (vex.length)
17597     {
17598     case 128:
17599       mnemonicendp = stpcpy (obuf, "vzeroupper");
17600       break;
17601     case 256:
17602       mnemonicendp = stpcpy (obuf, "vzeroall");
17603       break;
17604     default:
17605       abort ();
17606     }
17607 }
17608
17609 static struct op vex_cmp_op[] =
17610 {
17611   { STRING_COMMA_LEN ("eq") },
17612   { STRING_COMMA_LEN ("lt") },
17613   { STRING_COMMA_LEN ("le") },
17614   { STRING_COMMA_LEN ("unord") },
17615   { STRING_COMMA_LEN ("neq") },
17616   { STRING_COMMA_LEN ("nlt") },
17617   { STRING_COMMA_LEN ("nle") },
17618   { STRING_COMMA_LEN ("ord") },
17619   { STRING_COMMA_LEN ("eq_uq") },
17620   { STRING_COMMA_LEN ("nge") },
17621   { STRING_COMMA_LEN ("ngt") },
17622   { STRING_COMMA_LEN ("false") },
17623   { STRING_COMMA_LEN ("neq_oq") },
17624   { STRING_COMMA_LEN ("ge") },
17625   { STRING_COMMA_LEN ("gt") },
17626   { STRING_COMMA_LEN ("true") },
17627   { STRING_COMMA_LEN ("eq_os") },
17628   { STRING_COMMA_LEN ("lt_oq") },
17629   { STRING_COMMA_LEN ("le_oq") },
17630   { STRING_COMMA_LEN ("unord_s") },
17631   { STRING_COMMA_LEN ("neq_us") },
17632   { STRING_COMMA_LEN ("nlt_uq") },
17633   { STRING_COMMA_LEN ("nle_uq") },
17634   { STRING_COMMA_LEN ("ord_s") },
17635   { STRING_COMMA_LEN ("eq_us") },
17636   { STRING_COMMA_LEN ("nge_uq") },
17637   { STRING_COMMA_LEN ("ngt_uq") },
17638   { STRING_COMMA_LEN ("false_os") },
17639   { STRING_COMMA_LEN ("neq_os") },
17640   { STRING_COMMA_LEN ("ge_oq") },
17641   { STRING_COMMA_LEN ("gt_oq") },
17642   { STRING_COMMA_LEN ("true_us") },
17643 };
17644
17645 static void
17646 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17647 {
17648   unsigned int cmp_type;
17649
17650   FETCH_DATA (the_info, codep + 1);
17651   cmp_type = *codep++ & 0xff;
17652   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17653     {
17654       char suffix [3];
17655       char *p = mnemonicendp - 2;
17656       suffix[0] = p[0];
17657       suffix[1] = p[1];
17658       suffix[2] = '\0';
17659       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17660       mnemonicendp += vex_cmp_op[cmp_type].len;
17661     }
17662   else
17663     {
17664       /* We have a reserved extension byte.  Output it directly.  */
17665       scratchbuf[0] = '$';
17666       print_operand_value (scratchbuf + 1, 1, cmp_type);
17667       oappend_maybe_intel (scratchbuf);
17668       scratchbuf[0] = '\0';
17669     }
17670 }
17671
17672 static void
17673 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17674              int sizeflag ATTRIBUTE_UNUSED)
17675 {
17676   unsigned int cmp_type;
17677
17678   if (!vex.evex)
17679     abort ();
17680
17681   FETCH_DATA (the_info, codep + 1);
17682   cmp_type = *codep++ & 0xff;
17683   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17684      If it's the case, print suffix, otherwise - print the immediate.  */
17685   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17686       && cmp_type != 3
17687       && cmp_type != 7)
17688     {
17689       char suffix [3];
17690       char *p = mnemonicendp - 2;
17691
17692       /* vpcmp* can have both one- and two-lettered suffix.  */
17693       if (p[0] == 'p')
17694         {
17695           p++;
17696           suffix[0] = p[0];
17697           suffix[1] = '\0';
17698         }
17699       else
17700         {
17701           suffix[0] = p[0];
17702           suffix[1] = p[1];
17703           suffix[2] = '\0';
17704         }
17705
17706       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17707       mnemonicendp += simd_cmp_op[cmp_type].len;
17708     }
17709   else
17710     {
17711       /* We have a reserved extension byte.  Output it directly.  */
17712       scratchbuf[0] = '$';
17713       print_operand_value (scratchbuf + 1, 1, cmp_type);
17714       oappend_maybe_intel (scratchbuf);
17715       scratchbuf[0] = '\0';
17716     }
17717 }
17718
17719 static const struct op pclmul_op[] =
17720 {
17721   { STRING_COMMA_LEN ("lql") },
17722   { STRING_COMMA_LEN ("hql") },
17723   { STRING_COMMA_LEN ("lqh") },
17724   { STRING_COMMA_LEN ("hqh") }
17725 };
17726
17727 static void
17728 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17729               int sizeflag ATTRIBUTE_UNUSED)
17730 {
17731   unsigned int pclmul_type;
17732
17733   FETCH_DATA (the_info, codep + 1);
17734   pclmul_type = *codep++ & 0xff;
17735   switch (pclmul_type)
17736     {
17737     case 0x10:
17738       pclmul_type = 2;
17739       break;
17740     case 0x11:
17741       pclmul_type = 3;
17742       break;
17743     default:
17744       break;
17745     }
17746   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17747     {
17748       char suffix [4];
17749       char *p = mnemonicendp - 3;
17750       suffix[0] = p[0];
17751       suffix[1] = p[1];
17752       suffix[2] = p[2];
17753       suffix[3] = '\0';
17754       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17755       mnemonicendp += pclmul_op[pclmul_type].len;
17756     }
17757   else
17758     {
17759       /* We have a reserved extension byte.  Output it directly.  */
17760       scratchbuf[0] = '$';
17761       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17762       oappend_maybe_intel (scratchbuf);
17763       scratchbuf[0] = '\0';
17764     }
17765 }
17766
17767 static void
17768 MOVBE_Fixup (int bytemode, int sizeflag)
17769 {
17770   /* Add proper suffix to "movbe".  */
17771   char *p = mnemonicendp;
17772
17773   switch (bytemode)
17774     {
17775     case v_mode:
17776       if (intel_syntax)
17777         goto skip;
17778
17779       USED_REX (REX_W);
17780       if (sizeflag & SUFFIX_ALWAYS)
17781         {
17782           if (rex & REX_W)
17783             *p++ = 'q';
17784           else
17785             {
17786               if (sizeflag & DFLAG)
17787                 *p++ = 'l';
17788               else
17789                 *p++ = 'w';
17790               used_prefixes |= (prefixes & PREFIX_DATA);
17791             }
17792         }
17793       break;
17794     default:
17795       oappend (INTERNAL_DISASSEMBLER_ERROR);
17796       break;
17797     }
17798   mnemonicendp = p;
17799   *p = '\0';
17800
17801 skip:
17802   OP_M (bytemode, sizeflag);
17803 }
17804
17805 static void
17806 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17807 {
17808   int reg;
17809   const char **names;
17810
17811   /* Skip mod/rm byte.  */
17812   MODRM_CHECK;
17813   codep++;
17814
17815   if (vex.w)
17816     names = names64;
17817   else
17818     names = names32;
17819
17820   reg = modrm.rm;
17821   USED_REX (REX_B);
17822   if (rex & REX_B)
17823     reg += 8;
17824
17825   oappend (names[reg]);
17826 }
17827
17828 static void
17829 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17830 {
17831   const char **names;
17832
17833   if (vex.w)
17834     names = names64;
17835   else
17836     names = names32;
17837
17838   oappend (names[vex.register_specifier]);
17839 }
17840
17841 static void
17842 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17843 {
17844   if (!vex.evex
17845       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17846     abort ();
17847
17848   USED_REX (REX_R);
17849   if ((rex & REX_R) != 0 || !vex.r)
17850     {
17851       BadOp ();
17852       return;
17853     }
17854
17855   oappend (names_mask [modrm.reg]);
17856 }
17857
17858 static void
17859 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17860 {
17861   if (!vex.evex
17862       || (bytemode != evex_rounding_mode
17863           && bytemode != evex_sae_mode))
17864     abort ();
17865   if (modrm.mod == 3 && vex.b)
17866     switch (bytemode)
17867       {
17868       case evex_rounding_mode:
17869         oappend (names_rounding[vex.ll]);
17870         break;
17871       case evex_sae_mode:
17872         oappend ("{sae}");
17873         break;
17874       default:
17875         break;
17876       }
17877 }