1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2016 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void OP_LWPCB_E (int, int);
121 static void OP_LWP_E (int, int);
122 static void OP_Vex_2src_1 (int, int);
123 static void OP_Vex_2src_2 (int, int);
125 static void MOVBE_Fixup (int, int);
127 static void OP_Mask (int, int);
130 /* Points to first byte not fetched. */
131 bfd_byte
*max_fetched
;
132 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
135 OPCODES_SIGJMP_BUF bailout
;
145 enum address_mode address_mode
;
147 /* Flags for the prefixes for the current instruction. See below. */
150 /* REX prefix the current instruction. See below. */
152 /* Bits of REX we've already used. */
154 /* REX bits in original REX prefix ignored. */
155 static int rex_ignored
;
156 /* Mark parts used in the REX prefix. When we are testing for
157 empty prefix (for 8bit register REX extension), just mask it
158 out. Otherwise test for REX bit is excuse for existence of REX
159 only in case value is nonzero. */
160 #define USED_REX(value) \
165 rex_used |= (value) | REX_OPCODE; \
168 rex_used |= REX_OPCODE; \
171 /* Flags for prefixes which we somehow handled when printing the
172 current instruction. */
173 static int used_prefixes
;
175 /* Flags stored in PREFIXES. */
176 #define PREFIX_REPZ 1
177 #define PREFIX_REPNZ 2
178 #define PREFIX_LOCK 4
180 #define PREFIX_SS 0x10
181 #define PREFIX_DS 0x20
182 #define PREFIX_ES 0x40
183 #define PREFIX_FS 0x80
184 #define PREFIX_GS 0x100
185 #define PREFIX_DATA 0x200
186 #define PREFIX_ADDR 0x400
187 #define PREFIX_FWAIT 0x800
189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
190 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
192 #define FETCH_DATA(info, addr) \
193 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
194 ? 1 : fetch_data ((info), (addr)))
197 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
200 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
201 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
203 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
204 status
= (*info
->read_memory_func
) (start
,
206 addr
- priv
->max_fetched
,
212 /* If we did manage to read at least one byte, then
213 print_insn_i386 will do something sensible. Otherwise, print
214 an error. We do that here because this is where we know
216 if (priv
->max_fetched
== priv
->the_buffer
)
217 (*info
->memory_error_func
) (status
, start
, info
);
218 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
221 priv
->max_fetched
= addr
;
225 /* Possible values for prefix requirement. */
226 #define PREFIX_IGNORED_SHIFT 16
227 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
228 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
233 /* Opcode prefixes. */
234 #define PREFIX_OPCODE (PREFIX_REPZ \
238 /* Prefixes ignored. */
239 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
240 | PREFIX_IGNORED_REPNZ \
241 | PREFIX_IGNORED_DATA)
243 #define XX { NULL, 0 }
244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
246 #define Eb { OP_E, b_mode }
247 #define Ebnd { OP_E, bnd_mode }
248 #define EbS { OP_E, b_swap_mode }
249 #define Ev { OP_E, v_mode }
250 #define Ev_bnd { OP_E, v_bnd_mode }
251 #define EvS { OP_E, v_swap_mode }
252 #define Ed { OP_E, d_mode }
253 #define Edq { OP_E, dq_mode }
254 #define Edqw { OP_E, dqw_mode }
255 #define EdqwS { OP_E, dqw_swap_mode }
256 #define Edqb { OP_E, dqb_mode }
257 #define Edb { OP_E, db_mode }
258 #define Edw { OP_E, dw_mode }
259 #define Edqd { OP_E, dqd_mode }
260 #define Eq { OP_E, q_mode }
261 #define indirEv { OP_indirE, indir_v_mode }
262 #define indirEp { OP_indirE, f_mode }
263 #define stackEv { OP_E, stack_v_mode }
264 #define Em { OP_E, m_mode }
265 #define Ew { OP_E, w_mode }
266 #define M { OP_M, 0 } /* lea, lgdt, etc. */
267 #define Ma { OP_M, a_mode }
268 #define Mb { OP_M, b_mode }
269 #define Md { OP_M, d_mode }
270 #define Mo { OP_M, o_mode }
271 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
272 #define Mq { OP_M, q_mode }
273 #define Mx { OP_M, x_mode }
274 #define Mxmm { OP_M, xmm_mode }
275 #define Gb { OP_G, b_mode }
276 #define Gbnd { OP_G, bnd_mode }
277 #define Gv { OP_G, v_mode }
278 #define Gd { OP_G, d_mode }
279 #define Gdq { OP_G, dq_mode }
280 #define Gm { OP_G, m_mode }
281 #define Gw { OP_G, w_mode }
282 #define Rd { OP_R, d_mode }
283 #define Rdq { OP_R, dq_mode }
284 #define Rm { OP_R, m_mode }
285 #define Ib { OP_I, b_mode }
286 #define sIb { OP_sI, b_mode } /* sign extened byte */
287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
288 #define Iv { OP_I, v_mode }
289 #define sIv { OP_sI, v_mode }
290 #define Iq { OP_I, q_mode }
291 #define Iv64 { OP_I64, v_mode }
292 #define Iw { OP_I, w_mode }
293 #define I1 { OP_I, const_1_mode }
294 #define Jb { OP_J, b_mode }
295 #define Jv { OP_J, v_mode }
296 #define Cm { OP_C, m_mode }
297 #define Dm { OP_D, m_mode }
298 #define Td { OP_T, d_mode }
299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
301 #define RMeAX { OP_REG, eAX_reg }
302 #define RMeBX { OP_REG, eBX_reg }
303 #define RMeCX { OP_REG, eCX_reg }
304 #define RMeDX { OP_REG, eDX_reg }
305 #define RMeSP { OP_REG, eSP_reg }
306 #define RMeBP { OP_REG, eBP_reg }
307 #define RMeSI { OP_REG, eSI_reg }
308 #define RMeDI { OP_REG, eDI_reg }
309 #define RMrAX { OP_REG, rAX_reg }
310 #define RMrBX { OP_REG, rBX_reg }
311 #define RMrCX { OP_REG, rCX_reg }
312 #define RMrDX { OP_REG, rDX_reg }
313 #define RMrSP { OP_REG, rSP_reg }
314 #define RMrBP { OP_REG, rBP_reg }
315 #define RMrSI { OP_REG, rSI_reg }
316 #define RMrDI { OP_REG, rDI_reg }
317 #define RMAL { OP_REG, al_reg }
318 #define RMCL { OP_REG, cl_reg }
319 #define RMDL { OP_REG, dl_reg }
320 #define RMBL { OP_REG, bl_reg }
321 #define RMAH { OP_REG, ah_reg }
322 #define RMCH { OP_REG, ch_reg }
323 #define RMDH { OP_REG, dh_reg }
324 #define RMBH { OP_REG, bh_reg }
325 #define RMAX { OP_REG, ax_reg }
326 #define RMDX { OP_REG, dx_reg }
328 #define eAX { OP_IMREG, eAX_reg }
329 #define eBX { OP_IMREG, eBX_reg }
330 #define eCX { OP_IMREG, eCX_reg }
331 #define eDX { OP_IMREG, eDX_reg }
332 #define eSP { OP_IMREG, eSP_reg }
333 #define eBP { OP_IMREG, eBP_reg }
334 #define eSI { OP_IMREG, eSI_reg }
335 #define eDI { OP_IMREG, eDI_reg }
336 #define AL { OP_IMREG, al_reg }
337 #define CL { OP_IMREG, cl_reg }
338 #define DL { OP_IMREG, dl_reg }
339 #define BL { OP_IMREG, bl_reg }
340 #define AH { OP_IMREG, ah_reg }
341 #define CH { OP_IMREG, ch_reg }
342 #define DH { OP_IMREG, dh_reg }
343 #define BH { OP_IMREG, bh_reg }
344 #define AX { OP_IMREG, ax_reg }
345 #define DX { OP_IMREG, dx_reg }
346 #define zAX { OP_IMREG, z_mode_ax_reg }
347 #define indirDX { OP_IMREG, indir_dx_reg }
349 #define Sw { OP_SEG, w_mode }
350 #define Sv { OP_SEG, v_mode }
351 #define Ap { OP_DIR, 0 }
352 #define Ob { OP_OFF64, b_mode }
353 #define Ov { OP_OFF64, v_mode }
354 #define Xb { OP_DSreg, eSI_reg }
355 #define Xv { OP_DSreg, eSI_reg }
356 #define Xz { OP_DSreg, eSI_reg }
357 #define Yb { OP_ESreg, eDI_reg }
358 #define Yv { OP_ESreg, eDI_reg }
359 #define DSBX { OP_DSreg, eBX_reg }
361 #define es { OP_REG, es_reg }
362 #define ss { OP_REG, ss_reg }
363 #define cs { OP_REG, cs_reg }
364 #define ds { OP_REG, ds_reg }
365 #define fs { OP_REG, fs_reg }
366 #define gs { OP_REG, gs_reg }
368 #define MX { OP_MMX, 0 }
369 #define XM { OP_XMM, 0 }
370 #define XMScalar { OP_XMM, scalar_mode }
371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
372 #define XMM { OP_XMM, xmm_mode }
373 #define XMxmmq { OP_XMM, xmmq_mode }
374 #define EM { OP_EM, v_mode }
375 #define EMS { OP_EM, v_swap_mode }
376 #define EMd { OP_EM, d_mode }
377 #define EMx { OP_EM, x_mode }
378 #define EXw { OP_EX, w_mode }
379 #define EXd { OP_EX, d_mode }
380 #define EXdScalar { OP_EX, d_scalar_mode }
381 #define EXdS { OP_EX, d_swap_mode }
382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
383 #define EXq { OP_EX, q_mode }
384 #define EXqScalar { OP_EX, q_scalar_mode }
385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
386 #define EXqS { OP_EX, q_swap_mode }
387 #define EXx { OP_EX, x_mode }
388 #define EXxS { OP_EX, x_swap_mode }
389 #define EXxmm { OP_EX, xmm_mode }
390 #define EXymm { OP_EX, ymm_mode }
391 #define EXxmmq { OP_EX, xmmq_mode }
392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
395 #define EXxmm_md { OP_EX, xmm_md_mode }
396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
398 #define EXxmmdw { OP_EX, xmmdw_mode }
399 #define EXxmmqd { OP_EX, xmmqd_mode }
400 #define EXymmq { OP_EX, ymmq_mode }
401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
405 #define MS { OP_MS, v_mode }
406 #define XS { OP_XS, v_mode }
407 #define EMCq { OP_EMC, q_mode }
408 #define MXC { OP_MXC, 0 }
409 #define OPSUF { OP_3DNowSuffix, 0 }
410 #define CMP { CMP_Fixup, 0 }
411 #define XMM0 { XMM_Fixup, 0 }
412 #define FXSAVE { FXSAVE_Fixup, 0 }
413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
416 #define Vex { OP_VEX, vex_mode }
417 #define VexScalar { OP_VEX, vex_scalar_mode }
418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
419 #define Vex128 { OP_VEX, vex128_mode }
420 #define Vex256 { OP_VEX, vex256_mode }
421 #define VexGdq { OP_VEX, dq_mode }
422 #define VexI4 { VEXI4_Fixup, 0}
423 #define EXdVex { OP_EX_Vex, d_mode }
424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
426 #define EXqVex { OP_EX_Vex, q_mode }
427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
429 #define EXVexW { OP_EX_VexW, x_mode }
430 #define EXdVexW { OP_EX_VexW, d_mode }
431 #define EXqVexW { OP_EX_VexW, q_mode }
432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
433 #define XMVex { OP_XMM_Vex, 0 }
434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
435 #define XMVexW { OP_XMM_VexW, 0 }
436 #define XMVexI4 { OP_REG_VexI4, x_mode }
437 #define PCLMUL { PCLMUL_Fixup, 0 }
438 #define VZERO { VZERO_Fixup, 0 }
439 #define VCMP { VCMP_Fixup, 0 }
440 #define VPCMP { VPCMP_Fixup, 0 }
442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
445 #define XMask { OP_Mask, mask_mode }
446 #define MaskG { OP_G, mask_mode }
447 #define MaskE { OP_E, mask_mode }
448 #define MaskBDE { OP_E, mask_bd_mode }
449 #define MaskR { OP_R, mask_mode }
450 #define MaskVex { OP_VEX, mask_mode }
452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
457 /* Used handle "rep" prefix for string instructions. */
458 #define Xbr { REP_Fixup, eSI_reg }
459 #define Xvr { REP_Fixup, eSI_reg }
460 #define Ybr { REP_Fixup, eDI_reg }
461 #define Yvr { REP_Fixup, eDI_reg }
462 #define Yzr { REP_Fixup, eDI_reg }
463 #define indirDXr { REP_Fixup, indir_dx_reg }
464 #define ALr { REP_Fixup, al_reg }
465 #define eAXr { REP_Fixup, eAX_reg }
467 /* Used handle HLE prefix for lockable instructions. */
468 #define Ebh1 { HLE_Fixup1, b_mode }
469 #define Evh1 { HLE_Fixup1, v_mode }
470 #define Ebh2 { HLE_Fixup2, b_mode }
471 #define Evh2 { HLE_Fixup2, v_mode }
472 #define Ebh3 { HLE_Fixup3, b_mode }
473 #define Evh3 { HLE_Fixup3, v_mode }
475 #define BND { BND_Fixup, 0 }
477 #define cond_jump_flag { NULL, cond_jump_mode }
478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
480 /* bits in sizeflag */
481 #define SUFFIX_ALWAYS 4
489 /* byte operand with operand swapped */
491 /* byte operand, sign extend like 'T' suffix */
493 /* operand size depends on prefixes */
495 /* operand size depends on prefixes with operand swapped */
499 /* double word operand */
501 /* double word operand with operand swapped */
503 /* quad word operand */
505 /* quad word operand with operand swapped */
507 /* ten-byte operand */
509 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
510 broadcast enabled. */
512 /* Similar to x_mode, but with different EVEX mem shifts. */
514 /* Similar to x_mode, but with disabled broadcast. */
516 /* Similar to x_mode, but with operands swapped and disabled broadcast
519 /* 16-byte XMM operand */
521 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
522 memory operand (depending on vector length). Broadcast isn't
525 /* Same as xmmq_mode, but broadcast is allowed. */
526 evex_half_bcst_xmmq_mode
,
527 /* XMM register or byte memory operand */
529 /* XMM register or word memory operand */
531 /* XMM register or double word memory operand */
533 /* XMM register or quad word memory operand */
535 /* XMM register or double/quad word memory operand, depending on
538 /* 16-byte XMM, word, double word or quad word operand. */
540 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
542 /* 32-byte YMM operand */
544 /* quad word, ymmword or zmmword memory operand. */
546 /* 32-byte YMM or 16-byte word operand */
548 /* d_mode in 32bit, q_mode in 64bit mode. */
550 /* pair of v_mode operands */
555 /* operand size depends on REX prefixes. */
557 /* registers like dq_mode, memory like w_mode. */
561 /* 4- or 6-byte pointer operand */
564 /* v_mode for indirect branch opcodes. */
566 /* v_mode for stack-related opcodes. */
568 /* non-quad operand size depends on prefixes */
570 /* 16-byte operand */
572 /* registers like dq_mode, memory like b_mode. */
574 /* registers like d_mode, memory like b_mode. */
576 /* registers like d_mode, memory like w_mode. */
578 /* registers like dq_mode, memory like d_mode. */
580 /* normal vex mode */
582 /* 128bit vex mode */
584 /* 256bit vex mode */
586 /* operand size depends on the VEX.W bit. */
589 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
590 vex_vsib_d_w_dq_mode
,
591 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
593 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
594 vex_vsib_q_w_dq_mode
,
595 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
598 /* scalar, ignore vector length. */
600 /* like d_mode, ignore vector length. */
602 /* like d_swap_mode, ignore vector length. */
604 /* like q_mode, ignore vector length. */
606 /* like q_swap_mode, ignore vector length. */
608 /* like vex_mode, ignore vector length. */
610 /* like vex_w_dq_mode, ignore vector length. */
611 vex_scalar_w_dq_mode
,
613 /* Static rounding. */
615 /* Supress all exceptions. */
618 /* Mask register operand. */
620 /* Mask register operand. */
687 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
689 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
690 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
691 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
692 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
693 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
694 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
695 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
696 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
697 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
698 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
699 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
700 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
701 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
702 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
703 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
821 MOD_VEX_0F12_PREFIX_0
,
823 MOD_VEX_0F16_PREFIX_0
,
826 MOD_VEX_W_0_0F41_P_0_LEN_1
,
827 MOD_VEX_W_1_0F41_P_0_LEN_1
,
828 MOD_VEX_W_0_0F41_P_2_LEN_1
,
829 MOD_VEX_W_1_0F41_P_2_LEN_1
,
830 MOD_VEX_W_0_0F42_P_0_LEN_1
,
831 MOD_VEX_W_1_0F42_P_0_LEN_1
,
832 MOD_VEX_W_0_0F42_P_2_LEN_1
,
833 MOD_VEX_W_1_0F42_P_2_LEN_1
,
834 MOD_VEX_W_0_0F44_P_0_LEN_1
,
835 MOD_VEX_W_1_0F44_P_0_LEN_1
,
836 MOD_VEX_W_0_0F44_P_2_LEN_1
,
837 MOD_VEX_W_1_0F44_P_2_LEN_1
,
838 MOD_VEX_W_0_0F45_P_0_LEN_1
,
839 MOD_VEX_W_1_0F45_P_0_LEN_1
,
840 MOD_VEX_W_0_0F45_P_2_LEN_1
,
841 MOD_VEX_W_1_0F45_P_2_LEN_1
,
842 MOD_VEX_W_0_0F46_P_0_LEN_1
,
843 MOD_VEX_W_1_0F46_P_0_LEN_1
,
844 MOD_VEX_W_0_0F46_P_2_LEN_1
,
845 MOD_VEX_W_1_0F46_P_2_LEN_1
,
846 MOD_VEX_W_0_0F47_P_0_LEN_1
,
847 MOD_VEX_W_1_0F47_P_0_LEN_1
,
848 MOD_VEX_W_0_0F47_P_2_LEN_1
,
849 MOD_VEX_W_1_0F47_P_2_LEN_1
,
850 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
851 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
852 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
853 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
854 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
855 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
856 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
868 MOD_VEX_W_0_0F91_P_0_LEN_0
,
869 MOD_VEX_W_1_0F91_P_0_LEN_0
,
870 MOD_VEX_W_0_0F91_P_2_LEN_0
,
871 MOD_VEX_W_1_0F91_P_2_LEN_0
,
872 MOD_VEX_W_0_0F92_P_0_LEN_0
,
873 MOD_VEX_W_0_0F92_P_2_LEN_0
,
874 MOD_VEX_W_0_0F92_P_3_LEN_0
,
875 MOD_VEX_W_1_0F92_P_3_LEN_0
,
876 MOD_VEX_W_0_0F93_P_0_LEN_0
,
877 MOD_VEX_W_0_0F93_P_2_LEN_0
,
878 MOD_VEX_W_0_0F93_P_3_LEN_0
,
879 MOD_VEX_W_1_0F93_P_3_LEN_0
,
880 MOD_VEX_W_0_0F98_P_0_LEN_0
,
881 MOD_VEX_W_1_0F98_P_0_LEN_0
,
882 MOD_VEX_W_0_0F98_P_2_LEN_0
,
883 MOD_VEX_W_1_0F98_P_2_LEN_0
,
884 MOD_VEX_W_0_0F99_P_0_LEN_0
,
885 MOD_VEX_W_1_0F99_P_0_LEN_0
,
886 MOD_VEX_W_0_0F99_P_2_LEN_0
,
887 MOD_VEX_W_1_0F99_P_2_LEN_0
,
890 MOD_VEX_0FD7_PREFIX_2
,
891 MOD_VEX_0FE7_PREFIX_2
,
892 MOD_VEX_0FF0_PREFIX_3
,
893 MOD_VEX_0F381A_PREFIX_2
,
894 MOD_VEX_0F382A_PREFIX_2
,
895 MOD_VEX_0F382C_PREFIX_2
,
896 MOD_VEX_0F382D_PREFIX_2
,
897 MOD_VEX_0F382E_PREFIX_2
,
898 MOD_VEX_0F382F_PREFIX_2
,
899 MOD_VEX_0F385A_PREFIX_2
,
900 MOD_VEX_0F388C_PREFIX_2
,
901 MOD_VEX_0F388E_PREFIX_2
,
902 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
903 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
904 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
905 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
906 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
907 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
908 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
909 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
911 MOD_EVEX_0F10_PREFIX_1
,
912 MOD_EVEX_0F10_PREFIX_3
,
913 MOD_EVEX_0F11_PREFIX_1
,
914 MOD_EVEX_0F11_PREFIX_3
,
915 MOD_EVEX_0F12_PREFIX_0
,
916 MOD_EVEX_0F16_PREFIX_0
,
917 MOD_EVEX_0F38C6_REG_1
,
918 MOD_EVEX_0F38C6_REG_2
,
919 MOD_EVEX_0F38C6_REG_5
,
920 MOD_EVEX_0F38C6_REG_6
,
921 MOD_EVEX_0F38C7_REG_1
,
922 MOD_EVEX_0F38C7_REG_2
,
923 MOD_EVEX_0F38C7_REG_5
,
924 MOD_EVEX_0F38C7_REG_6
987 PREFIX_MOD_0_0FAE_REG_4
,
988 PREFIX_MOD_3_0FAE_REG_4
,
996 PREFIX_MOD_0_0FC7_REG_6
,
997 PREFIX_MOD_3_0FC7_REG_6
,
998 PREFIX_MOD_3_0FC7_REG_7
,
1122 PREFIX_VEX_0F71_REG_2
,
1123 PREFIX_VEX_0F71_REG_4
,
1124 PREFIX_VEX_0F71_REG_6
,
1125 PREFIX_VEX_0F72_REG_2
,
1126 PREFIX_VEX_0F72_REG_4
,
1127 PREFIX_VEX_0F72_REG_6
,
1128 PREFIX_VEX_0F73_REG_2
,
1129 PREFIX_VEX_0F73_REG_3
,
1130 PREFIX_VEX_0F73_REG_6
,
1131 PREFIX_VEX_0F73_REG_7
,
1303 PREFIX_VEX_0F38F3_REG_1
,
1304 PREFIX_VEX_0F38F3_REG_2
,
1305 PREFIX_VEX_0F38F3_REG_3
,
1422 PREFIX_EVEX_0F71_REG_2
,
1423 PREFIX_EVEX_0F71_REG_4
,
1424 PREFIX_EVEX_0F71_REG_6
,
1425 PREFIX_EVEX_0F72_REG_0
,
1426 PREFIX_EVEX_0F72_REG_1
,
1427 PREFIX_EVEX_0F72_REG_2
,
1428 PREFIX_EVEX_0F72_REG_4
,
1429 PREFIX_EVEX_0F72_REG_6
,
1430 PREFIX_EVEX_0F73_REG_2
,
1431 PREFIX_EVEX_0F73_REG_3
,
1432 PREFIX_EVEX_0F73_REG_6
,
1433 PREFIX_EVEX_0F73_REG_7
,
1616 PREFIX_EVEX_0F38C6_REG_1
,
1617 PREFIX_EVEX_0F38C6_REG_2
,
1618 PREFIX_EVEX_0F38C6_REG_5
,
1619 PREFIX_EVEX_0F38C6_REG_6
,
1620 PREFIX_EVEX_0F38C7_REG_1
,
1621 PREFIX_EVEX_0F38C7_REG_2
,
1622 PREFIX_EVEX_0F38C7_REG_5
,
1623 PREFIX_EVEX_0F38C7_REG_6
,
1712 THREE_BYTE_0F38
= 0,
1740 VEX_LEN_0F10_P_1
= 0,
1744 VEX_LEN_0F12_P_0_M_0
,
1745 VEX_LEN_0F12_P_0_M_1
,
1748 VEX_LEN_0F16_P_0_M_0
,
1749 VEX_LEN_0F16_P_0_M_1
,
1813 VEX_LEN_0FAE_R_2_M_0
,
1814 VEX_LEN_0FAE_R_3_M_0
,
1823 VEX_LEN_0F381A_P_2_M_0
,
1826 VEX_LEN_0F385A_P_2_M_0
,
1833 VEX_LEN_0F38F3_R_1_P_0
,
1834 VEX_LEN_0F38F3_R_2_P_0
,
1835 VEX_LEN_0F38F3_R_3_P_0
,
1881 VEX_LEN_0FXOP_08_CC
,
1882 VEX_LEN_0FXOP_08_CD
,
1883 VEX_LEN_0FXOP_08_CE
,
1884 VEX_LEN_0FXOP_08_CF
,
1885 VEX_LEN_0FXOP_08_EC
,
1886 VEX_LEN_0FXOP_08_ED
,
1887 VEX_LEN_0FXOP_08_EE
,
1888 VEX_LEN_0FXOP_08_EF
,
1889 VEX_LEN_0FXOP_09_80
,
1923 VEX_W_0F41_P_0_LEN_1
,
1924 VEX_W_0F41_P_2_LEN_1
,
1925 VEX_W_0F42_P_0_LEN_1
,
1926 VEX_W_0F42_P_2_LEN_1
,
1927 VEX_W_0F44_P_0_LEN_0
,
1928 VEX_W_0F44_P_2_LEN_0
,
1929 VEX_W_0F45_P_0_LEN_1
,
1930 VEX_W_0F45_P_2_LEN_1
,
1931 VEX_W_0F46_P_0_LEN_1
,
1932 VEX_W_0F46_P_2_LEN_1
,
1933 VEX_W_0F47_P_0_LEN_1
,
1934 VEX_W_0F47_P_2_LEN_1
,
1935 VEX_W_0F4A_P_0_LEN_1
,
1936 VEX_W_0F4A_P_2_LEN_1
,
1937 VEX_W_0F4B_P_0_LEN_1
,
1938 VEX_W_0F4B_P_2_LEN_1
,
2018 VEX_W_0F90_P_0_LEN_0
,
2019 VEX_W_0F90_P_2_LEN_0
,
2020 VEX_W_0F91_P_0_LEN_0
,
2021 VEX_W_0F91_P_2_LEN_0
,
2022 VEX_W_0F92_P_0_LEN_0
,
2023 VEX_W_0F92_P_2_LEN_0
,
2024 VEX_W_0F92_P_3_LEN_0
,
2025 VEX_W_0F93_P_0_LEN_0
,
2026 VEX_W_0F93_P_2_LEN_0
,
2027 VEX_W_0F93_P_3_LEN_0
,
2028 VEX_W_0F98_P_0_LEN_0
,
2029 VEX_W_0F98_P_2_LEN_0
,
2030 VEX_W_0F99_P_0_LEN_0
,
2031 VEX_W_0F99_P_2_LEN_0
,
2110 VEX_W_0F381A_P_2_M_0
,
2122 VEX_W_0F382A_P_2_M_0
,
2124 VEX_W_0F382C_P_2_M_0
,
2125 VEX_W_0F382D_P_2_M_0
,
2126 VEX_W_0F382E_P_2_M_0
,
2127 VEX_W_0F382F_P_2_M_0
,
2149 VEX_W_0F385A_P_2_M_0
,
2177 VEX_W_0F3A30_P_2_LEN_0
,
2178 VEX_W_0F3A31_P_2_LEN_0
,
2179 VEX_W_0F3A32_P_2_LEN_0
,
2180 VEX_W_0F3A33_P_2_LEN_0
,
2200 EVEX_W_0F10_P_1_M_0
,
2201 EVEX_W_0F10_P_1_M_1
,
2203 EVEX_W_0F10_P_3_M_0
,
2204 EVEX_W_0F10_P_3_M_1
,
2206 EVEX_W_0F11_P_1_M_0
,
2207 EVEX_W_0F11_P_1_M_1
,
2209 EVEX_W_0F11_P_3_M_0
,
2210 EVEX_W_0F11_P_3_M_1
,
2211 EVEX_W_0F12_P_0_M_0
,
2212 EVEX_W_0F12_P_0_M_1
,
2222 EVEX_W_0F16_P_0_M_0
,
2223 EVEX_W_0F16_P_0_M_1
,
2294 EVEX_W_0F72_R_2_P_2
,
2295 EVEX_W_0F72_R_6_P_2
,
2296 EVEX_W_0F73_R_2_P_2
,
2297 EVEX_W_0F73_R_6_P_2
,
2397 EVEX_W_0F38C7_R_1_P_2
,
2398 EVEX_W_0F38C7_R_2_P_2
,
2399 EVEX_W_0F38C7_R_5_P_2
,
2400 EVEX_W_0F38C7_R_6_P_2
,
2435 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2444 unsigned int prefix_requirement
;
2447 /* Upper case letters in the instruction names here are macros.
2448 'A' => print 'b' if no register operands or suffix_always is true
2449 'B' => print 'b' if suffix_always is true
2450 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2452 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2453 suffix_always is true
2454 'E' => print 'e' if 32-bit form of jcxz
2455 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2456 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2457 'H' => print ",pt" or ",pn" branch hint
2458 'I' => honor following macro letter even in Intel mode (implemented only
2459 for some of the macro letters)
2461 'K' => print 'd' or 'q' if rex prefix is present.
2462 'L' => print 'l' if suffix_always is true
2463 'M' => print 'r' if intel_mnemonic is false.
2464 'N' => print 'n' if instruction has no wait "prefix"
2465 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2466 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2467 or suffix_always is true. print 'q' if rex prefix is present.
2468 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2470 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2471 'S' => print 'w', 'l' or 'q' if suffix_always is true
2472 'T' => print 'q' in 64bit mode if instruction has no operand size
2473 prefix and behave as 'P' otherwise
2474 'U' => print 'q' in 64bit mode if instruction has no operand size
2475 prefix and behave as 'Q' otherwise
2476 'V' => print 'q' in 64bit mode if instruction has no operand size
2477 prefix and behave as 'S' otherwise
2478 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2479 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2480 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2481 suffix_always is true.
2482 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2483 '!' => change condition from true to false or from false to true.
2484 '%' => add 1 upper case letter to the macro.
2485 '^' => print 'w' or 'l' depending on operand size prefix or
2486 suffix_always is true (lcall/ljmp).
2487 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2488 on operand size prefix.
2489 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2490 has no operand size prefix for AMD64 ISA, behave as 'P'
2493 2 upper case letter macros:
2494 "XY" => print 'x' or 'y' if suffix_always is true or no register
2495 operands and no broadcast.
2496 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2497 register operands and no broadcast.
2498 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2499 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2500 or suffix_always is true
2501 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2502 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2503 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2504 "LW" => print 'd', 'q' depending on the VEX.W bit
2505 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2506 an operand size prefix, or suffix_always is true. print
2507 'q' if rex prefix is present.
2509 Many of the above letters print nothing in Intel mode. See "putop"
2512 Braces '{' and '}', and vertical bars '|', indicate alternative
2513 mnemonic strings for AT&T and Intel. */
2515 static const struct dis386 dis386
[] = {
2517 { "addB", { Ebh1
, Gb
}, 0 },
2518 { "addS", { Evh1
, Gv
}, 0 },
2519 { "addB", { Gb
, EbS
}, 0 },
2520 { "addS", { Gv
, EvS
}, 0 },
2521 { "addB", { AL
, Ib
}, 0 },
2522 { "addS", { eAX
, Iv
}, 0 },
2523 { X86_64_TABLE (X86_64_06
) },
2524 { X86_64_TABLE (X86_64_07
) },
2526 { "orB", { Ebh1
, Gb
}, 0 },
2527 { "orS", { Evh1
, Gv
}, 0 },
2528 { "orB", { Gb
, EbS
}, 0 },
2529 { "orS", { Gv
, EvS
}, 0 },
2530 { "orB", { AL
, Ib
}, 0 },
2531 { "orS", { eAX
, Iv
}, 0 },
2532 { X86_64_TABLE (X86_64_0D
) },
2533 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2535 { "adcB", { Ebh1
, Gb
}, 0 },
2536 { "adcS", { Evh1
, Gv
}, 0 },
2537 { "adcB", { Gb
, EbS
}, 0 },
2538 { "adcS", { Gv
, EvS
}, 0 },
2539 { "adcB", { AL
, Ib
}, 0 },
2540 { "adcS", { eAX
, Iv
}, 0 },
2541 { X86_64_TABLE (X86_64_16
) },
2542 { X86_64_TABLE (X86_64_17
) },
2544 { "sbbB", { Ebh1
, Gb
}, 0 },
2545 { "sbbS", { Evh1
, Gv
}, 0 },
2546 { "sbbB", { Gb
, EbS
}, 0 },
2547 { "sbbS", { Gv
, EvS
}, 0 },
2548 { "sbbB", { AL
, Ib
}, 0 },
2549 { "sbbS", { eAX
, Iv
}, 0 },
2550 { X86_64_TABLE (X86_64_1E
) },
2551 { X86_64_TABLE (X86_64_1F
) },
2553 { "andB", { Ebh1
, Gb
}, 0 },
2554 { "andS", { Evh1
, Gv
}, 0 },
2555 { "andB", { Gb
, EbS
}, 0 },
2556 { "andS", { Gv
, EvS
}, 0 },
2557 { "andB", { AL
, Ib
}, 0 },
2558 { "andS", { eAX
, Iv
}, 0 },
2559 { Bad_Opcode
}, /* SEG ES prefix */
2560 { X86_64_TABLE (X86_64_27
) },
2562 { "subB", { Ebh1
, Gb
}, 0 },
2563 { "subS", { Evh1
, Gv
}, 0 },
2564 { "subB", { Gb
, EbS
}, 0 },
2565 { "subS", { Gv
, EvS
}, 0 },
2566 { "subB", { AL
, Ib
}, 0 },
2567 { "subS", { eAX
, Iv
}, 0 },
2568 { Bad_Opcode
}, /* SEG CS prefix */
2569 { X86_64_TABLE (X86_64_2F
) },
2571 { "xorB", { Ebh1
, Gb
}, 0 },
2572 { "xorS", { Evh1
, Gv
}, 0 },
2573 { "xorB", { Gb
, EbS
}, 0 },
2574 { "xorS", { Gv
, EvS
}, 0 },
2575 { "xorB", { AL
, Ib
}, 0 },
2576 { "xorS", { eAX
, Iv
}, 0 },
2577 { Bad_Opcode
}, /* SEG SS prefix */
2578 { X86_64_TABLE (X86_64_37
) },
2580 { "cmpB", { Eb
, Gb
}, 0 },
2581 { "cmpS", { Ev
, Gv
}, 0 },
2582 { "cmpB", { Gb
, EbS
}, 0 },
2583 { "cmpS", { Gv
, EvS
}, 0 },
2584 { "cmpB", { AL
, Ib
}, 0 },
2585 { "cmpS", { eAX
, Iv
}, 0 },
2586 { Bad_Opcode
}, /* SEG DS prefix */
2587 { X86_64_TABLE (X86_64_3F
) },
2589 { "inc{S|}", { RMeAX
}, 0 },
2590 { "inc{S|}", { RMeCX
}, 0 },
2591 { "inc{S|}", { RMeDX
}, 0 },
2592 { "inc{S|}", { RMeBX
}, 0 },
2593 { "inc{S|}", { RMeSP
}, 0 },
2594 { "inc{S|}", { RMeBP
}, 0 },
2595 { "inc{S|}", { RMeSI
}, 0 },
2596 { "inc{S|}", { RMeDI
}, 0 },
2598 { "dec{S|}", { RMeAX
}, 0 },
2599 { "dec{S|}", { RMeCX
}, 0 },
2600 { "dec{S|}", { RMeDX
}, 0 },
2601 { "dec{S|}", { RMeBX
}, 0 },
2602 { "dec{S|}", { RMeSP
}, 0 },
2603 { "dec{S|}", { RMeBP
}, 0 },
2604 { "dec{S|}", { RMeSI
}, 0 },
2605 { "dec{S|}", { RMeDI
}, 0 },
2607 { "pushV", { RMrAX
}, 0 },
2608 { "pushV", { RMrCX
}, 0 },
2609 { "pushV", { RMrDX
}, 0 },
2610 { "pushV", { RMrBX
}, 0 },
2611 { "pushV", { RMrSP
}, 0 },
2612 { "pushV", { RMrBP
}, 0 },
2613 { "pushV", { RMrSI
}, 0 },
2614 { "pushV", { RMrDI
}, 0 },
2616 { "popV", { RMrAX
}, 0 },
2617 { "popV", { RMrCX
}, 0 },
2618 { "popV", { RMrDX
}, 0 },
2619 { "popV", { RMrBX
}, 0 },
2620 { "popV", { RMrSP
}, 0 },
2621 { "popV", { RMrBP
}, 0 },
2622 { "popV", { RMrSI
}, 0 },
2623 { "popV", { RMrDI
}, 0 },
2625 { X86_64_TABLE (X86_64_60
) },
2626 { X86_64_TABLE (X86_64_61
) },
2627 { X86_64_TABLE (X86_64_62
) },
2628 { X86_64_TABLE (X86_64_63
) },
2629 { Bad_Opcode
}, /* seg fs */
2630 { Bad_Opcode
}, /* seg gs */
2631 { Bad_Opcode
}, /* op size prefix */
2632 { Bad_Opcode
}, /* adr size prefix */
2634 { "pushT", { sIv
}, 0 },
2635 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2636 { "pushT", { sIbT
}, 0 },
2637 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2638 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2639 { X86_64_TABLE (X86_64_6D
) },
2640 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2641 { X86_64_TABLE (X86_64_6F
) },
2643 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2644 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2645 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2646 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2647 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2648 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2649 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2650 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2652 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2653 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2654 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2655 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2656 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2657 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2658 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2659 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2661 { REG_TABLE (REG_80
) },
2662 { REG_TABLE (REG_81
) },
2664 { REG_TABLE (REG_82
) },
2665 { "testB", { Eb
, Gb
}, 0 },
2666 { "testS", { Ev
, Gv
}, 0 },
2667 { "xchgB", { Ebh2
, Gb
}, 0 },
2668 { "xchgS", { Evh2
, Gv
}, 0 },
2670 { "movB", { Ebh3
, Gb
}, 0 },
2671 { "movS", { Evh3
, Gv
}, 0 },
2672 { "movB", { Gb
, EbS
}, 0 },
2673 { "movS", { Gv
, EvS
}, 0 },
2674 { "movD", { Sv
, Sw
}, 0 },
2675 { MOD_TABLE (MOD_8D
) },
2676 { "movD", { Sw
, Sv
}, 0 },
2677 { REG_TABLE (REG_8F
) },
2679 { PREFIX_TABLE (PREFIX_90
) },
2680 { "xchgS", { RMeCX
, eAX
}, 0 },
2681 { "xchgS", { RMeDX
, eAX
}, 0 },
2682 { "xchgS", { RMeBX
, eAX
}, 0 },
2683 { "xchgS", { RMeSP
, eAX
}, 0 },
2684 { "xchgS", { RMeBP
, eAX
}, 0 },
2685 { "xchgS", { RMeSI
, eAX
}, 0 },
2686 { "xchgS", { RMeDI
, eAX
}, 0 },
2688 { "cW{t|}R", { XX
}, 0 },
2689 { "cR{t|}O", { XX
}, 0 },
2690 { X86_64_TABLE (X86_64_9A
) },
2691 { Bad_Opcode
}, /* fwait */
2692 { "pushfT", { XX
}, 0 },
2693 { "popfT", { XX
}, 0 },
2694 { "sahf", { XX
}, 0 },
2695 { "lahf", { XX
}, 0 },
2697 { "mov%LB", { AL
, Ob
}, 0 },
2698 { "mov%LS", { eAX
, Ov
}, 0 },
2699 { "mov%LB", { Ob
, AL
}, 0 },
2700 { "mov%LS", { Ov
, eAX
}, 0 },
2701 { "movs{b|}", { Ybr
, Xb
}, 0 },
2702 { "movs{R|}", { Yvr
, Xv
}, 0 },
2703 { "cmps{b|}", { Xb
, Yb
}, 0 },
2704 { "cmps{R|}", { Xv
, Yv
}, 0 },
2706 { "testB", { AL
, Ib
}, 0 },
2707 { "testS", { eAX
, Iv
}, 0 },
2708 { "stosB", { Ybr
, AL
}, 0 },
2709 { "stosS", { Yvr
, eAX
}, 0 },
2710 { "lodsB", { ALr
, Xb
}, 0 },
2711 { "lodsS", { eAXr
, Xv
}, 0 },
2712 { "scasB", { AL
, Yb
}, 0 },
2713 { "scasS", { eAX
, Yv
}, 0 },
2715 { "movB", { RMAL
, Ib
}, 0 },
2716 { "movB", { RMCL
, Ib
}, 0 },
2717 { "movB", { RMDL
, Ib
}, 0 },
2718 { "movB", { RMBL
, Ib
}, 0 },
2719 { "movB", { RMAH
, Ib
}, 0 },
2720 { "movB", { RMCH
, Ib
}, 0 },
2721 { "movB", { RMDH
, Ib
}, 0 },
2722 { "movB", { RMBH
, Ib
}, 0 },
2724 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2725 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2726 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2727 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2728 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2729 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2730 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2731 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2733 { REG_TABLE (REG_C0
) },
2734 { REG_TABLE (REG_C1
) },
2735 { "retT", { Iw
, BND
}, 0 },
2736 { "retT", { BND
}, 0 },
2737 { X86_64_TABLE (X86_64_C4
) },
2738 { X86_64_TABLE (X86_64_C5
) },
2739 { REG_TABLE (REG_C6
) },
2740 { REG_TABLE (REG_C7
) },
2742 { "enterT", { Iw
, Ib
}, 0 },
2743 { "leaveT", { XX
}, 0 },
2744 { "Jret{|f}P", { Iw
}, 0 },
2745 { "Jret{|f}P", { XX
}, 0 },
2746 { "int3", { XX
}, 0 },
2747 { "int", { Ib
}, 0 },
2748 { X86_64_TABLE (X86_64_CE
) },
2749 { "iret%LP", { XX
}, 0 },
2751 { REG_TABLE (REG_D0
) },
2752 { REG_TABLE (REG_D1
) },
2753 { REG_TABLE (REG_D2
) },
2754 { REG_TABLE (REG_D3
) },
2755 { X86_64_TABLE (X86_64_D4
) },
2756 { X86_64_TABLE (X86_64_D5
) },
2758 { "xlat", { DSBX
}, 0 },
2769 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2770 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2771 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2772 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2773 { "inB", { AL
, Ib
}, 0 },
2774 { "inG", { zAX
, Ib
}, 0 },
2775 { "outB", { Ib
, AL
}, 0 },
2776 { "outG", { Ib
, zAX
}, 0 },
2778 { X86_64_TABLE (X86_64_E8
) },
2779 { X86_64_TABLE (X86_64_E9
) },
2780 { X86_64_TABLE (X86_64_EA
) },
2781 { "jmp", { Jb
, BND
}, 0 },
2782 { "inB", { AL
, indirDX
}, 0 },
2783 { "inG", { zAX
, indirDX
}, 0 },
2784 { "outB", { indirDX
, AL
}, 0 },
2785 { "outG", { indirDX
, zAX
}, 0 },
2787 { Bad_Opcode
}, /* lock prefix */
2788 { "icebp", { XX
}, 0 },
2789 { Bad_Opcode
}, /* repne */
2790 { Bad_Opcode
}, /* repz */
2791 { "hlt", { XX
}, 0 },
2792 { "cmc", { XX
}, 0 },
2793 { REG_TABLE (REG_F6
) },
2794 { REG_TABLE (REG_F7
) },
2796 { "clc", { XX
}, 0 },
2797 { "stc", { XX
}, 0 },
2798 { "cli", { XX
}, 0 },
2799 { "sti", { XX
}, 0 },
2800 { "cld", { XX
}, 0 },
2801 { "std", { XX
}, 0 },
2802 { REG_TABLE (REG_FE
) },
2803 { REG_TABLE (REG_FF
) },
2806 static const struct dis386 dis386_twobyte
[] = {
2808 { REG_TABLE (REG_0F00
) },
2809 { REG_TABLE (REG_0F01
) },
2810 { "larS", { Gv
, Ew
}, 0 },
2811 { "lslS", { Gv
, Ew
}, 0 },
2813 { "syscall", { XX
}, 0 },
2814 { "clts", { XX
}, 0 },
2815 { "sysret%LP", { XX
}, 0 },
2817 { "invd", { XX
}, 0 },
2818 { "wbinvd", { XX
}, 0 },
2820 { "ud2", { XX
}, 0 },
2822 { REG_TABLE (REG_0F0D
) },
2823 { "femms", { XX
}, 0 },
2824 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2826 { PREFIX_TABLE (PREFIX_0F10
) },
2827 { PREFIX_TABLE (PREFIX_0F11
) },
2828 { PREFIX_TABLE (PREFIX_0F12
) },
2829 { MOD_TABLE (MOD_0F13
) },
2830 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2831 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2832 { PREFIX_TABLE (PREFIX_0F16
) },
2833 { MOD_TABLE (MOD_0F17
) },
2835 { REG_TABLE (REG_0F18
) },
2836 { "nopQ", { Ev
}, 0 },
2837 { PREFIX_TABLE (PREFIX_0F1A
) },
2838 { PREFIX_TABLE (PREFIX_0F1B
) },
2839 { "nopQ", { Ev
}, 0 },
2840 { "nopQ", { Ev
}, 0 },
2841 { "nopQ", { Ev
}, 0 },
2842 { "nopQ", { Ev
}, 0 },
2844 { "movZ", { Rm
, Cm
}, 0 },
2845 { "movZ", { Rm
, Dm
}, 0 },
2846 { "movZ", { Cm
, Rm
}, 0 },
2847 { "movZ", { Dm
, Rm
}, 0 },
2848 { MOD_TABLE (MOD_0F24
) },
2850 { MOD_TABLE (MOD_0F26
) },
2853 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2854 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2855 { PREFIX_TABLE (PREFIX_0F2A
) },
2856 { PREFIX_TABLE (PREFIX_0F2B
) },
2857 { PREFIX_TABLE (PREFIX_0F2C
) },
2858 { PREFIX_TABLE (PREFIX_0F2D
) },
2859 { PREFIX_TABLE (PREFIX_0F2E
) },
2860 { PREFIX_TABLE (PREFIX_0F2F
) },
2862 { "wrmsr", { XX
}, 0 },
2863 { "rdtsc", { XX
}, 0 },
2864 { "rdmsr", { XX
}, 0 },
2865 { "rdpmc", { XX
}, 0 },
2866 { "sysenter", { XX
}, 0 },
2867 { "sysexit", { XX
}, 0 },
2869 { "getsec", { XX
}, 0 },
2871 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2873 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2880 { "cmovoS", { Gv
, Ev
}, 0 },
2881 { "cmovnoS", { Gv
, Ev
}, 0 },
2882 { "cmovbS", { Gv
, Ev
}, 0 },
2883 { "cmovaeS", { Gv
, Ev
}, 0 },
2884 { "cmoveS", { Gv
, Ev
}, 0 },
2885 { "cmovneS", { Gv
, Ev
}, 0 },
2886 { "cmovbeS", { Gv
, Ev
}, 0 },
2887 { "cmovaS", { Gv
, Ev
}, 0 },
2889 { "cmovsS", { Gv
, Ev
}, 0 },
2890 { "cmovnsS", { Gv
, Ev
}, 0 },
2891 { "cmovpS", { Gv
, Ev
}, 0 },
2892 { "cmovnpS", { Gv
, Ev
}, 0 },
2893 { "cmovlS", { Gv
, Ev
}, 0 },
2894 { "cmovgeS", { Gv
, Ev
}, 0 },
2895 { "cmovleS", { Gv
, Ev
}, 0 },
2896 { "cmovgS", { Gv
, Ev
}, 0 },
2898 { MOD_TABLE (MOD_0F51
) },
2899 { PREFIX_TABLE (PREFIX_0F51
) },
2900 { PREFIX_TABLE (PREFIX_0F52
) },
2901 { PREFIX_TABLE (PREFIX_0F53
) },
2902 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2903 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2904 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2905 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2907 { PREFIX_TABLE (PREFIX_0F58
) },
2908 { PREFIX_TABLE (PREFIX_0F59
) },
2909 { PREFIX_TABLE (PREFIX_0F5A
) },
2910 { PREFIX_TABLE (PREFIX_0F5B
) },
2911 { PREFIX_TABLE (PREFIX_0F5C
) },
2912 { PREFIX_TABLE (PREFIX_0F5D
) },
2913 { PREFIX_TABLE (PREFIX_0F5E
) },
2914 { PREFIX_TABLE (PREFIX_0F5F
) },
2916 { PREFIX_TABLE (PREFIX_0F60
) },
2917 { PREFIX_TABLE (PREFIX_0F61
) },
2918 { PREFIX_TABLE (PREFIX_0F62
) },
2919 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2920 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2921 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2922 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2923 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2925 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2926 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2927 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2928 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2929 { PREFIX_TABLE (PREFIX_0F6C
) },
2930 { PREFIX_TABLE (PREFIX_0F6D
) },
2931 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2932 { PREFIX_TABLE (PREFIX_0F6F
) },
2934 { PREFIX_TABLE (PREFIX_0F70
) },
2935 { REG_TABLE (REG_0F71
) },
2936 { REG_TABLE (REG_0F72
) },
2937 { REG_TABLE (REG_0F73
) },
2938 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2939 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2940 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2941 { "emms", { XX
}, PREFIX_OPCODE
},
2943 { PREFIX_TABLE (PREFIX_0F78
) },
2944 { PREFIX_TABLE (PREFIX_0F79
) },
2945 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2947 { PREFIX_TABLE (PREFIX_0F7C
) },
2948 { PREFIX_TABLE (PREFIX_0F7D
) },
2949 { PREFIX_TABLE (PREFIX_0F7E
) },
2950 { PREFIX_TABLE (PREFIX_0F7F
) },
2952 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2953 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2954 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2955 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2956 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2957 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2958 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2959 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2961 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2962 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2963 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2964 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2965 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2966 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2967 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2968 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2970 { "seto", { Eb
}, 0 },
2971 { "setno", { Eb
}, 0 },
2972 { "setb", { Eb
}, 0 },
2973 { "setae", { Eb
}, 0 },
2974 { "sete", { Eb
}, 0 },
2975 { "setne", { Eb
}, 0 },
2976 { "setbe", { Eb
}, 0 },
2977 { "seta", { Eb
}, 0 },
2979 { "sets", { Eb
}, 0 },
2980 { "setns", { Eb
}, 0 },
2981 { "setp", { Eb
}, 0 },
2982 { "setnp", { Eb
}, 0 },
2983 { "setl", { Eb
}, 0 },
2984 { "setge", { Eb
}, 0 },
2985 { "setle", { Eb
}, 0 },
2986 { "setg", { Eb
}, 0 },
2988 { "pushT", { fs
}, 0 },
2989 { "popT", { fs
}, 0 },
2990 { "cpuid", { XX
}, 0 },
2991 { "btS", { Ev
, Gv
}, 0 },
2992 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2993 { "shldS", { Ev
, Gv
, CL
}, 0 },
2994 { REG_TABLE (REG_0FA6
) },
2995 { REG_TABLE (REG_0FA7
) },
2997 { "pushT", { gs
}, 0 },
2998 { "popT", { gs
}, 0 },
2999 { "rsm", { XX
}, 0 },
3000 { "btsS", { Evh1
, Gv
}, 0 },
3001 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
3002 { "shrdS", { Ev
, Gv
, CL
}, 0 },
3003 { REG_TABLE (REG_0FAE
) },
3004 { "imulS", { Gv
, Ev
}, 0 },
3006 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
3007 { "cmpxchgS", { Evh1
, Gv
}, 0 },
3008 { MOD_TABLE (MOD_0FB2
) },
3009 { "btrS", { Evh1
, Gv
}, 0 },
3010 { MOD_TABLE (MOD_0FB4
) },
3011 { MOD_TABLE (MOD_0FB5
) },
3012 { "movz{bR|x}", { Gv
, Eb
}, 0 },
3013 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
3015 { PREFIX_TABLE (PREFIX_0FB8
) },
3016 { "ud1", { XX
}, 0 },
3017 { REG_TABLE (REG_0FBA
) },
3018 { "btcS", { Evh1
, Gv
}, 0 },
3019 { PREFIX_TABLE (PREFIX_0FBC
) },
3020 { PREFIX_TABLE (PREFIX_0FBD
) },
3021 { "movs{bR|x}", { Gv
, Eb
}, 0 },
3022 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
3024 { "xaddB", { Ebh1
, Gb
}, 0 },
3025 { "xaddS", { Evh1
, Gv
}, 0 },
3026 { PREFIX_TABLE (PREFIX_0FC2
) },
3027 { MOD_TABLE (MOD_0FC3
) },
3028 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
3029 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
3030 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3031 { REG_TABLE (REG_0FC7
) },
3033 { "bswap", { RMeAX
}, 0 },
3034 { "bswap", { RMeCX
}, 0 },
3035 { "bswap", { RMeDX
}, 0 },
3036 { "bswap", { RMeBX
}, 0 },
3037 { "bswap", { RMeSP
}, 0 },
3038 { "bswap", { RMeBP
}, 0 },
3039 { "bswap", { RMeSI
}, 0 },
3040 { "bswap", { RMeDI
}, 0 },
3042 { PREFIX_TABLE (PREFIX_0FD0
) },
3043 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
3044 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
3045 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
3046 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
3047 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
3048 { PREFIX_TABLE (PREFIX_0FD6
) },
3049 { MOD_TABLE (MOD_0FD7
) },
3051 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
3052 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
3053 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
3054 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
3055 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
3056 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
3057 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
3058 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
3060 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
3061 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
3062 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
3063 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
3064 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
3065 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
3066 { PREFIX_TABLE (PREFIX_0FE6
) },
3067 { PREFIX_TABLE (PREFIX_0FE7
) },
3069 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
3070 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
3071 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
3072 { "por", { MX
, EM
}, PREFIX_OPCODE
},
3073 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
3074 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
3075 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
3076 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
3078 { PREFIX_TABLE (PREFIX_0FF0
) },
3079 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
3080 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
3081 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
3082 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
3083 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
3084 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
3085 { PREFIX_TABLE (PREFIX_0FF7
) },
3087 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
3088 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
3089 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
3090 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
3091 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
3092 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
3093 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
3097 static const unsigned char onebyte_has_modrm
[256] = {
3098 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3099 /* ------------------------------- */
3100 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3101 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3102 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3103 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3104 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3105 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3106 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3107 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3108 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3109 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3110 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3111 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3112 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3113 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3114 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3115 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3116 /* ------------------------------- */
3117 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3120 static const unsigned char twobyte_has_modrm
[256] = {
3121 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3122 /* ------------------------------- */
3123 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3124 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3125 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3126 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3127 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3128 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3129 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3130 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3131 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3132 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3133 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3134 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3135 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3136 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3137 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3138 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3139 /* ------------------------------- */
3140 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3143 static char obuf
[100];
3145 static char *mnemonicendp
;
3146 static char scratchbuf
[100];
3147 static unsigned char *start_codep
;
3148 static unsigned char *insn_codep
;
3149 static unsigned char *codep
;
3150 static unsigned char *end_codep
;
3151 static int last_lock_prefix
;
3152 static int last_repz_prefix
;
3153 static int last_repnz_prefix
;
3154 static int last_data_prefix
;
3155 static int last_addr_prefix
;
3156 static int last_rex_prefix
;
3157 static int last_seg_prefix
;
3158 static int fwait_prefix
;
3159 /* The active segment register prefix. */
3160 static int active_seg_prefix
;
3161 #define MAX_CODE_LENGTH 15
3162 /* We can up to 14 prefixes since the maximum instruction length is
3164 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3165 static disassemble_info
*the_info
;
3173 static unsigned char need_modrm
;
3183 int register_specifier
;
3190 int mask_register_specifier
;
3196 static unsigned char need_vex
;
3197 static unsigned char need_vex_reg
;
3198 static unsigned char vex_w_done
;
3206 /* If we are accessing mod/rm/reg without need_modrm set, then the
3207 values are stale. Hitting this abort likely indicates that you
3208 need to update onebyte_has_modrm or twobyte_has_modrm. */
3209 #define MODRM_CHECK if (!need_modrm) abort ()
3211 static const char **names64
;
3212 static const char **names32
;
3213 static const char **names16
;
3214 static const char **names8
;
3215 static const char **names8rex
;
3216 static const char **names_seg
;
3217 static const char *index64
;
3218 static const char *index32
;
3219 static const char **index16
;
3220 static const char **names_bnd
;
3222 static const char *intel_names64
[] = {
3223 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3224 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3226 static const char *intel_names32
[] = {
3227 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3228 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3230 static const char *intel_names16
[] = {
3231 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3232 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3234 static const char *intel_names8
[] = {
3235 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3237 static const char *intel_names8rex
[] = {
3238 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3239 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3241 static const char *intel_names_seg
[] = {
3242 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3244 static const char *intel_index64
= "riz";
3245 static const char *intel_index32
= "eiz";
3246 static const char *intel_index16
[] = {
3247 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3250 static const char *att_names64
[] = {
3251 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3252 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3254 static const char *att_names32
[] = {
3255 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3256 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3258 static const char *att_names16
[] = {
3259 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3260 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3262 static const char *att_names8
[] = {
3263 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3265 static const char *att_names8rex
[] = {
3266 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3267 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3269 static const char *att_names_seg
[] = {
3270 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3272 static const char *att_index64
= "%riz";
3273 static const char *att_index32
= "%eiz";
3274 static const char *att_index16
[] = {
3275 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3278 static const char **names_mm
;
3279 static const char *intel_names_mm
[] = {
3280 "mm0", "mm1", "mm2", "mm3",
3281 "mm4", "mm5", "mm6", "mm7"
3283 static const char *att_names_mm
[] = {
3284 "%mm0", "%mm1", "%mm2", "%mm3",
3285 "%mm4", "%mm5", "%mm6", "%mm7"
3288 static const char *intel_names_bnd
[] = {
3289 "bnd0", "bnd1", "bnd2", "bnd3"
3292 static const char *att_names_bnd
[] = {
3293 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3296 static const char **names_xmm
;
3297 static const char *intel_names_xmm
[] = {
3298 "xmm0", "xmm1", "xmm2", "xmm3",
3299 "xmm4", "xmm5", "xmm6", "xmm7",
3300 "xmm8", "xmm9", "xmm10", "xmm11",
3301 "xmm12", "xmm13", "xmm14", "xmm15",
3302 "xmm16", "xmm17", "xmm18", "xmm19",
3303 "xmm20", "xmm21", "xmm22", "xmm23",
3304 "xmm24", "xmm25", "xmm26", "xmm27",
3305 "xmm28", "xmm29", "xmm30", "xmm31"
3307 static const char *att_names_xmm
[] = {
3308 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3309 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3310 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3311 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3312 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3313 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3314 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3315 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3318 static const char **names_ymm
;
3319 static const char *intel_names_ymm
[] = {
3320 "ymm0", "ymm1", "ymm2", "ymm3",
3321 "ymm4", "ymm5", "ymm6", "ymm7",
3322 "ymm8", "ymm9", "ymm10", "ymm11",
3323 "ymm12", "ymm13", "ymm14", "ymm15",
3324 "ymm16", "ymm17", "ymm18", "ymm19",
3325 "ymm20", "ymm21", "ymm22", "ymm23",
3326 "ymm24", "ymm25", "ymm26", "ymm27",
3327 "ymm28", "ymm29", "ymm30", "ymm31"
3329 static const char *att_names_ymm
[] = {
3330 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3331 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3332 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3333 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3334 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3335 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3336 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3337 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3340 static const char **names_zmm
;
3341 static const char *intel_names_zmm
[] = {
3342 "zmm0", "zmm1", "zmm2", "zmm3",
3343 "zmm4", "zmm5", "zmm6", "zmm7",
3344 "zmm8", "zmm9", "zmm10", "zmm11",
3345 "zmm12", "zmm13", "zmm14", "zmm15",
3346 "zmm16", "zmm17", "zmm18", "zmm19",
3347 "zmm20", "zmm21", "zmm22", "zmm23",
3348 "zmm24", "zmm25", "zmm26", "zmm27",
3349 "zmm28", "zmm29", "zmm30", "zmm31"
3351 static const char *att_names_zmm
[] = {
3352 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3353 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3354 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3355 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3356 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3357 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3358 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3359 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3362 static const char **names_mask
;
3363 static const char *intel_names_mask
[] = {
3364 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3366 static const char *att_names_mask
[] = {
3367 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3370 static const char *names_rounding
[] =
3378 static const struct dis386 reg_table
[][8] = {
3381 { "addA", { Ebh1
, Ib
}, 0 },
3382 { "orA", { Ebh1
, Ib
}, 0 },
3383 { "adcA", { Ebh1
, Ib
}, 0 },
3384 { "sbbA", { Ebh1
, Ib
}, 0 },
3385 { "andA", { Ebh1
, Ib
}, 0 },
3386 { "subA", { Ebh1
, Ib
}, 0 },
3387 { "xorA", { Ebh1
, Ib
}, 0 },
3388 { "cmpA", { Eb
, Ib
}, 0 },
3392 { "addQ", { Evh1
, Iv
}, 0 },
3393 { "orQ", { Evh1
, Iv
}, 0 },
3394 { "adcQ", { Evh1
, Iv
}, 0 },
3395 { "sbbQ", { Evh1
, Iv
}, 0 },
3396 { "andQ", { Evh1
, Iv
}, 0 },
3397 { "subQ", { Evh1
, Iv
}, 0 },
3398 { "xorQ", { Evh1
, Iv
}, 0 },
3399 { "cmpQ", { Ev
, Iv
}, 0 },
3403 { "addQ", { Evh1
, sIb
}, 0 },
3404 { "orQ", { Evh1
, sIb
}, 0 },
3405 { "adcQ", { Evh1
, sIb
}, 0 },
3406 { "sbbQ", { Evh1
, sIb
}, 0 },
3407 { "andQ", { Evh1
, sIb
}, 0 },
3408 { "subQ", { Evh1
, sIb
}, 0 },
3409 { "xorQ", { Evh1
, sIb
}, 0 },
3410 { "cmpQ", { Ev
, sIb
}, 0 },
3414 { "popU", { stackEv
}, 0 },
3415 { XOP_8F_TABLE (XOP_09
) },
3419 { XOP_8F_TABLE (XOP_09
) },
3423 { "rolA", { Eb
, Ib
}, 0 },
3424 { "rorA", { Eb
, Ib
}, 0 },
3425 { "rclA", { Eb
, Ib
}, 0 },
3426 { "rcrA", { Eb
, Ib
}, 0 },
3427 { "shlA", { Eb
, Ib
}, 0 },
3428 { "shrA", { Eb
, Ib
}, 0 },
3430 { "sarA", { Eb
, Ib
}, 0 },
3434 { "rolQ", { Ev
, Ib
}, 0 },
3435 { "rorQ", { Ev
, Ib
}, 0 },
3436 { "rclQ", { Ev
, Ib
}, 0 },
3437 { "rcrQ", { Ev
, Ib
}, 0 },
3438 { "shlQ", { Ev
, Ib
}, 0 },
3439 { "shrQ", { Ev
, Ib
}, 0 },
3441 { "sarQ", { Ev
, Ib
}, 0 },
3445 { "movA", { Ebh3
, Ib
}, 0 },
3452 { MOD_TABLE (MOD_C6_REG_7
) },
3456 { "movQ", { Evh3
, Iv
}, 0 },
3463 { MOD_TABLE (MOD_C7_REG_7
) },
3467 { "rolA", { Eb
, I1
}, 0 },
3468 { "rorA", { Eb
, I1
}, 0 },
3469 { "rclA", { Eb
, I1
}, 0 },
3470 { "rcrA", { Eb
, I1
}, 0 },
3471 { "shlA", { Eb
, I1
}, 0 },
3472 { "shrA", { Eb
, I1
}, 0 },
3474 { "sarA", { Eb
, I1
}, 0 },
3478 { "rolQ", { Ev
, I1
}, 0 },
3479 { "rorQ", { Ev
, I1
}, 0 },
3480 { "rclQ", { Ev
, I1
}, 0 },
3481 { "rcrQ", { Ev
, I1
}, 0 },
3482 { "shlQ", { Ev
, I1
}, 0 },
3483 { "shrQ", { Ev
, I1
}, 0 },
3485 { "sarQ", { Ev
, I1
}, 0 },
3489 { "rolA", { Eb
, CL
}, 0 },
3490 { "rorA", { Eb
, CL
}, 0 },
3491 { "rclA", { Eb
, CL
}, 0 },
3492 { "rcrA", { Eb
, CL
}, 0 },
3493 { "shlA", { Eb
, CL
}, 0 },
3494 { "shrA", { Eb
, CL
}, 0 },
3496 { "sarA", { Eb
, CL
}, 0 },
3500 { "rolQ", { Ev
, CL
}, 0 },
3501 { "rorQ", { Ev
, CL
}, 0 },
3502 { "rclQ", { Ev
, CL
}, 0 },
3503 { "rcrQ", { Ev
, CL
}, 0 },
3504 { "shlQ", { Ev
, CL
}, 0 },
3505 { "shrQ", { Ev
, CL
}, 0 },
3507 { "sarQ", { Ev
, CL
}, 0 },
3511 { "testA", { Eb
, Ib
}, 0 },
3513 { "notA", { Ebh1
}, 0 },
3514 { "negA", { Ebh1
}, 0 },
3515 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3516 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3517 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3518 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3522 { "testQ", { Ev
, Iv
}, 0 },
3524 { "notQ", { Evh1
}, 0 },
3525 { "negQ", { Evh1
}, 0 },
3526 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3527 { "imulQ", { Ev
}, 0 },
3528 { "divQ", { Ev
}, 0 },
3529 { "idivQ", { Ev
}, 0 },
3533 { "incA", { Ebh1
}, 0 },
3534 { "decA", { Ebh1
}, 0 },
3538 { "incQ", { Evh1
}, 0 },
3539 { "decQ", { Evh1
}, 0 },
3540 { "call{&|}", { indirEv
, BND
}, 0 },
3541 { MOD_TABLE (MOD_FF_REG_3
) },
3542 { "jmp{&|}", { indirEv
, BND
}, 0 },
3543 { MOD_TABLE (MOD_FF_REG_5
) },
3544 { "pushU", { stackEv
}, 0 },
3549 { "sldtD", { Sv
}, 0 },
3550 { "strD", { Sv
}, 0 },
3551 { "lldt", { Ew
}, 0 },
3552 { "ltr", { Ew
}, 0 },
3553 { "verr", { Ew
}, 0 },
3554 { "verw", { Ew
}, 0 },
3560 { MOD_TABLE (MOD_0F01_REG_0
) },
3561 { MOD_TABLE (MOD_0F01_REG_1
) },
3562 { MOD_TABLE (MOD_0F01_REG_2
) },
3563 { MOD_TABLE (MOD_0F01_REG_3
) },
3564 { "smswD", { Sv
}, 0 },
3565 { MOD_TABLE (MOD_0F01_REG_5
) },
3566 { "lmsw", { Ew
}, 0 },
3567 { MOD_TABLE (MOD_0F01_REG_7
) },
3571 { "prefetch", { Mb
}, 0 },
3572 { "prefetchw", { Mb
}, 0 },
3573 { "prefetchwt1", { Mb
}, 0 },
3574 { "prefetch", { Mb
}, 0 },
3575 { "prefetch", { Mb
}, 0 },
3576 { "prefetch", { Mb
}, 0 },
3577 { "prefetch", { Mb
}, 0 },
3578 { "prefetch", { Mb
}, 0 },
3582 { MOD_TABLE (MOD_0F18_REG_0
) },
3583 { MOD_TABLE (MOD_0F18_REG_1
) },
3584 { MOD_TABLE (MOD_0F18_REG_2
) },
3585 { MOD_TABLE (MOD_0F18_REG_3
) },
3586 { MOD_TABLE (MOD_0F18_REG_4
) },
3587 { MOD_TABLE (MOD_0F18_REG_5
) },
3588 { MOD_TABLE (MOD_0F18_REG_6
) },
3589 { MOD_TABLE (MOD_0F18_REG_7
) },
3595 { MOD_TABLE (MOD_0F71_REG_2
) },
3597 { MOD_TABLE (MOD_0F71_REG_4
) },
3599 { MOD_TABLE (MOD_0F71_REG_6
) },
3605 { MOD_TABLE (MOD_0F72_REG_2
) },
3607 { MOD_TABLE (MOD_0F72_REG_4
) },
3609 { MOD_TABLE (MOD_0F72_REG_6
) },
3615 { MOD_TABLE (MOD_0F73_REG_2
) },
3616 { MOD_TABLE (MOD_0F73_REG_3
) },
3619 { MOD_TABLE (MOD_0F73_REG_6
) },
3620 { MOD_TABLE (MOD_0F73_REG_7
) },
3624 { "montmul", { { OP_0f07
, 0 } }, 0 },
3625 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3626 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3630 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3631 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3632 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3633 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3634 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3635 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3639 { MOD_TABLE (MOD_0FAE_REG_0
) },
3640 { MOD_TABLE (MOD_0FAE_REG_1
) },
3641 { MOD_TABLE (MOD_0FAE_REG_2
) },
3642 { MOD_TABLE (MOD_0FAE_REG_3
) },
3643 { MOD_TABLE (MOD_0FAE_REG_4
) },
3644 { MOD_TABLE (MOD_0FAE_REG_5
) },
3645 { MOD_TABLE (MOD_0FAE_REG_6
) },
3646 { MOD_TABLE (MOD_0FAE_REG_7
) },
3654 { "btQ", { Ev
, Ib
}, 0 },
3655 { "btsQ", { Evh1
, Ib
}, 0 },
3656 { "btrQ", { Evh1
, Ib
}, 0 },
3657 { "btcQ", { Evh1
, Ib
}, 0 },
3662 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3664 { MOD_TABLE (MOD_0FC7_REG_3
) },
3665 { MOD_TABLE (MOD_0FC7_REG_4
) },
3666 { MOD_TABLE (MOD_0FC7_REG_5
) },
3667 { MOD_TABLE (MOD_0FC7_REG_6
) },
3668 { MOD_TABLE (MOD_0FC7_REG_7
) },
3674 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3676 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3678 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3684 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3686 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3688 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3694 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3695 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3698 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3699 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3705 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3706 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3708 /* REG_VEX_0F38F3 */
3711 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3712 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3713 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3717 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3718 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3722 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3723 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3725 /* REG_XOP_TBM_01 */
3728 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3729 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3730 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3731 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3732 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3733 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3734 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3736 /* REG_XOP_TBM_02 */
3739 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3744 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3746 #define NEED_REG_TABLE
3747 #include "i386-dis-evex.h"
3748 #undef NEED_REG_TABLE
3751 static const struct dis386 prefix_table
[][4] = {
3754 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3755 { "pause", { XX
}, 0 },
3756 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3757 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3762 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3763 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3764 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3765 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3770 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3771 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3772 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3773 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3778 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3779 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3780 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3781 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3786 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3787 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3788 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3793 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3794 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3795 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3796 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3801 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3802 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3803 { "bndmov", { Ebnd
, Gbnd
}, 0 },
3804 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3809 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3810 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_OPCODE
},
3811 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3812 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3817 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3818 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3819 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3820 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3825 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3826 { "cvttss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3827 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3828 { "cvttsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3833 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3834 { "cvtss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3835 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3836 { "cvtsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3841 { "ucomiss",{ XM
, EXd
}, 0 },
3843 { "ucomisd",{ XM
, EXq
}, 0 },
3848 { "comiss", { XM
, EXd
}, 0 },
3850 { "comisd", { XM
, EXq
}, 0 },
3855 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3856 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3857 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3858 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3863 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3864 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3869 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3870 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3875 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3876 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3877 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3878 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3883 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3884 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3885 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3886 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3891 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3892 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3893 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3894 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3899 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3900 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3901 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3906 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3907 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3908 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3909 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3914 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3915 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3916 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3917 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3922 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3923 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3924 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3925 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3930 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3931 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3932 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3933 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3938 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3940 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3945 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3947 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3952 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3954 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3961 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3968 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3973 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3974 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3975 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3980 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3981 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3982 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3983 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3986 /* PREFIX_0F73_REG_3 */
3990 { "psrldq", { XS
, Ib
}, 0 },
3993 /* PREFIX_0F73_REG_7 */
3997 { "pslldq", { XS
, Ib
}, 0 },
4002 {"vmread", { Em
, Gm
}, 0 },
4004 {"extrq", { XS
, Ib
, Ib
}, 0 },
4005 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
4010 {"vmwrite", { Gm
, Em
}, 0 },
4012 {"extrq", { XM
, XS
}, 0 },
4013 {"insertq", { XM
, XS
}, 0 },
4020 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
4021 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
4028 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
4029 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
4034 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
4035 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
4036 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
4041 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
4042 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
4043 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
4046 /* PREFIX_0FAE_REG_0 */
4049 { "rdfsbase", { Ev
}, 0 },
4052 /* PREFIX_0FAE_REG_1 */
4055 { "rdgsbase", { Ev
}, 0 },
4058 /* PREFIX_0FAE_REG_2 */
4061 { "wrfsbase", { Ev
}, 0 },
4064 /* PREFIX_0FAE_REG_3 */
4067 { "wrgsbase", { Ev
}, 0 },
4070 /* PREFIX_MOD_0_0FAE_REG_4 */
4072 { "xsave", { FXSAVE
}, 0 },
4073 { "ptwrite%LQ", { Edq
}, 0 },
4076 /* PREFIX_MOD_3_0FAE_REG_4 */
4079 { "ptwrite%LQ", { Edq
}, 0 },
4082 /* PREFIX_0FAE_REG_6 */
4084 { "xsaveopt", { FXSAVE
}, 0 },
4086 { "clwb", { Mb
}, 0 },
4089 /* PREFIX_0FAE_REG_7 */
4091 { "clflush", { Mb
}, 0 },
4093 { "clflushopt", { Mb
}, 0 },
4099 { "popcntS", { Gv
, Ev
}, 0 },
4104 { "bsfS", { Gv
, Ev
}, 0 },
4105 { "tzcntS", { Gv
, Ev
}, 0 },
4106 { "bsfS", { Gv
, Ev
}, 0 },
4111 { "bsrS", { Gv
, Ev
}, 0 },
4112 { "lzcntS", { Gv
, Ev
}, 0 },
4113 { "bsrS", { Gv
, Ev
}, 0 },
4118 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4119 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4120 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4121 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4124 /* PREFIX_MOD_0_0FC3 */
4126 { "movntiS", { Ev
, Gv
}, PREFIX_OPCODE
},
4129 /* PREFIX_MOD_0_0FC7_REG_6 */
4131 { "vmptrld",{ Mq
}, 0 },
4132 { "vmxon", { Mq
}, 0 },
4133 { "vmclear",{ Mq
}, 0 },
4136 /* PREFIX_MOD_3_0FC7_REG_6 */
4138 { "rdrand", { Ev
}, 0 },
4140 { "rdrand", { Ev
}, 0 }
4143 /* PREFIX_MOD_3_0FC7_REG_7 */
4145 { "rdseed", { Ev
}, 0 },
4146 { "rdpid", { Em
}, 0 },
4147 { "rdseed", { Ev
}, 0 },
4154 { "addsubpd", { XM
, EXx
}, 0 },
4155 { "addsubps", { XM
, EXx
}, 0 },
4161 { "movq2dq",{ XM
, MS
}, 0 },
4162 { "movq", { EXqS
, XM
}, 0 },
4163 { "movdq2q",{ MX
, XS
}, 0 },
4169 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4170 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4171 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4176 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4178 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4186 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4191 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4193 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4200 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4207 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4214 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4221 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4228 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4235 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4242 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4249 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4256 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4263 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4270 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4277 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4284 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4291 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4298 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4305 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4312 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4319 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4326 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4333 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4340 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4347 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4354 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4361 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4368 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4375 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4382 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4389 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4396 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4403 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4410 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4417 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4424 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4431 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4436 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4441 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4446 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4451 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4456 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4461 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4468 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4475 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4482 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4489 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4496 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4501 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4503 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4504 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4509 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4511 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4512 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4518 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4519 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4527 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4534 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4541 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4548 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4555 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4562 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4569 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4576 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4583 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4590 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4597 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4604 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4611 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4618 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4625 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4632 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4639 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4646 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4653 { "pcmpestrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4660 { "pcmpestri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4667 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4674 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4679 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4686 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4689 /* PREFIX_VEX_0F10 */
4691 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4692 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4693 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4694 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4697 /* PREFIX_VEX_0F11 */
4699 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4700 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4701 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4702 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4705 /* PREFIX_VEX_0F12 */
4707 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4708 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4709 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4710 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4713 /* PREFIX_VEX_0F16 */
4715 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4716 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4717 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4720 /* PREFIX_VEX_0F2A */
4723 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4725 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4728 /* PREFIX_VEX_0F2C */
4731 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4733 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4736 /* PREFIX_VEX_0F2D */
4739 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4741 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4744 /* PREFIX_VEX_0F2E */
4746 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4748 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4751 /* PREFIX_VEX_0F2F */
4753 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4755 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4758 /* PREFIX_VEX_0F41 */
4760 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4762 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4765 /* PREFIX_VEX_0F42 */
4767 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4769 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4772 /* PREFIX_VEX_0F44 */
4774 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4776 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4779 /* PREFIX_VEX_0F45 */
4781 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4783 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4786 /* PREFIX_VEX_0F46 */
4788 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4790 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4793 /* PREFIX_VEX_0F47 */
4795 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4797 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4800 /* PREFIX_VEX_0F4A */
4802 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4804 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4807 /* PREFIX_VEX_0F4B */
4809 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4811 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4814 /* PREFIX_VEX_0F51 */
4816 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4817 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4818 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4819 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4822 /* PREFIX_VEX_0F52 */
4824 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4825 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
4828 /* PREFIX_VEX_0F53 */
4830 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
4831 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
4834 /* PREFIX_VEX_0F58 */
4836 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
4837 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
4838 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
4839 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
4842 /* PREFIX_VEX_0F59 */
4844 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
4845 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
4846 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
4847 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
4850 /* PREFIX_VEX_0F5A */
4852 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
4853 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
4854 { "vcvtpd2ps%XY", { XMM
, EXx
}, 0 },
4855 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
4858 /* PREFIX_VEX_0F5B */
4860 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
4861 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
4862 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
4865 /* PREFIX_VEX_0F5C */
4867 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
4868 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
4869 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
4870 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
4873 /* PREFIX_VEX_0F5D */
4875 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
4876 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
4877 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
4878 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
4881 /* PREFIX_VEX_0F5E */
4883 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
4884 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
4885 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
4886 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
4889 /* PREFIX_VEX_0F5F */
4891 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
4892 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
4893 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
4894 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
4897 /* PREFIX_VEX_0F60 */
4901 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
4904 /* PREFIX_VEX_0F61 */
4908 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
4911 /* PREFIX_VEX_0F62 */
4915 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
4918 /* PREFIX_VEX_0F63 */
4922 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
4925 /* PREFIX_VEX_0F64 */
4929 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
4932 /* PREFIX_VEX_0F65 */
4936 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
4939 /* PREFIX_VEX_0F66 */
4943 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
4946 /* PREFIX_VEX_0F67 */
4950 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
4953 /* PREFIX_VEX_0F68 */
4957 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
4960 /* PREFIX_VEX_0F69 */
4964 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
4967 /* PREFIX_VEX_0F6A */
4971 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
4974 /* PREFIX_VEX_0F6B */
4978 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
4981 /* PREFIX_VEX_0F6C */
4985 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
4988 /* PREFIX_VEX_0F6D */
4992 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
4995 /* PREFIX_VEX_0F6E */
4999 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
5002 /* PREFIX_VEX_0F6F */
5005 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
5006 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
5009 /* PREFIX_VEX_0F70 */
5012 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
5013 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
5014 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
5017 /* PREFIX_VEX_0F71_REG_2 */
5021 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
5024 /* PREFIX_VEX_0F71_REG_4 */
5028 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
5031 /* PREFIX_VEX_0F71_REG_6 */
5035 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
5038 /* PREFIX_VEX_0F72_REG_2 */
5042 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
5045 /* PREFIX_VEX_0F72_REG_4 */
5049 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
5052 /* PREFIX_VEX_0F72_REG_6 */
5056 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
5059 /* PREFIX_VEX_0F73_REG_2 */
5063 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
5066 /* PREFIX_VEX_0F73_REG_3 */
5070 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
5073 /* PREFIX_VEX_0F73_REG_6 */
5077 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
5080 /* PREFIX_VEX_0F73_REG_7 */
5084 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
5087 /* PREFIX_VEX_0F74 */
5091 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
5094 /* PREFIX_VEX_0F75 */
5098 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
5101 /* PREFIX_VEX_0F76 */
5105 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
5108 /* PREFIX_VEX_0F77 */
5110 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
5113 /* PREFIX_VEX_0F7C */
5117 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
5118 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
5121 /* PREFIX_VEX_0F7D */
5125 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
5126 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
5129 /* PREFIX_VEX_0F7E */
5132 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5133 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5136 /* PREFIX_VEX_0F7F */
5139 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
5140 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
5143 /* PREFIX_VEX_0F90 */
5145 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5147 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5150 /* PREFIX_VEX_0F91 */
5152 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5154 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5157 /* PREFIX_VEX_0F92 */
5159 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5161 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5162 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5165 /* PREFIX_VEX_0F93 */
5167 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5169 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5170 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5173 /* PREFIX_VEX_0F98 */
5175 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5177 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5180 /* PREFIX_VEX_0F99 */
5182 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5184 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5187 /* PREFIX_VEX_0FC2 */
5189 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
5190 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
5191 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
5192 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
5195 /* PREFIX_VEX_0FC4 */
5199 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5202 /* PREFIX_VEX_0FC5 */
5206 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5209 /* PREFIX_VEX_0FD0 */
5213 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
5214 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
5217 /* PREFIX_VEX_0FD1 */
5221 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
5224 /* PREFIX_VEX_0FD2 */
5228 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
5231 /* PREFIX_VEX_0FD3 */
5235 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
5238 /* PREFIX_VEX_0FD4 */
5242 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
5245 /* PREFIX_VEX_0FD5 */
5249 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
5252 /* PREFIX_VEX_0FD6 */
5256 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5259 /* PREFIX_VEX_0FD7 */
5263 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5266 /* PREFIX_VEX_0FD8 */
5270 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
5273 /* PREFIX_VEX_0FD9 */
5277 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
5280 /* PREFIX_VEX_0FDA */
5284 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
5287 /* PREFIX_VEX_0FDB */
5291 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
5294 /* PREFIX_VEX_0FDC */
5298 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
5301 /* PREFIX_VEX_0FDD */
5305 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
5308 /* PREFIX_VEX_0FDE */
5312 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
5315 /* PREFIX_VEX_0FDF */
5319 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
5322 /* PREFIX_VEX_0FE0 */
5326 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
5329 /* PREFIX_VEX_0FE1 */
5333 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
5336 /* PREFIX_VEX_0FE2 */
5340 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
5343 /* PREFIX_VEX_0FE3 */
5347 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
5350 /* PREFIX_VEX_0FE4 */
5354 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
5357 /* PREFIX_VEX_0FE5 */
5361 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
5364 /* PREFIX_VEX_0FE6 */
5367 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
5368 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
5369 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5372 /* PREFIX_VEX_0FE7 */
5376 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5379 /* PREFIX_VEX_0FE8 */
5383 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5386 /* PREFIX_VEX_0FE9 */
5390 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5393 /* PREFIX_VEX_0FEA */
5397 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5400 /* PREFIX_VEX_0FEB */
5404 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5407 /* PREFIX_VEX_0FEC */
5411 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5414 /* PREFIX_VEX_0FED */
5418 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5421 /* PREFIX_VEX_0FEE */
5425 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5428 /* PREFIX_VEX_0FEF */
5432 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5435 /* PREFIX_VEX_0FF0 */
5440 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5443 /* PREFIX_VEX_0FF1 */
5447 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5450 /* PREFIX_VEX_0FF2 */
5454 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5457 /* PREFIX_VEX_0FF3 */
5461 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5464 /* PREFIX_VEX_0FF4 */
5468 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5471 /* PREFIX_VEX_0FF5 */
5475 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5478 /* PREFIX_VEX_0FF6 */
5482 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5485 /* PREFIX_VEX_0FF7 */
5489 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5492 /* PREFIX_VEX_0FF8 */
5496 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5499 /* PREFIX_VEX_0FF9 */
5503 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5506 /* PREFIX_VEX_0FFA */
5510 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5513 /* PREFIX_VEX_0FFB */
5517 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5520 /* PREFIX_VEX_0FFC */
5524 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5527 /* PREFIX_VEX_0FFD */
5531 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5534 /* PREFIX_VEX_0FFE */
5538 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5541 /* PREFIX_VEX_0F3800 */
5545 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5548 /* PREFIX_VEX_0F3801 */
5552 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5555 /* PREFIX_VEX_0F3802 */
5559 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5562 /* PREFIX_VEX_0F3803 */
5566 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5569 /* PREFIX_VEX_0F3804 */
5573 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5576 /* PREFIX_VEX_0F3805 */
5580 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5583 /* PREFIX_VEX_0F3806 */
5587 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5590 /* PREFIX_VEX_0F3807 */
5594 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5597 /* PREFIX_VEX_0F3808 */
5601 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5604 /* PREFIX_VEX_0F3809 */
5608 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5611 /* PREFIX_VEX_0F380A */
5615 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5618 /* PREFIX_VEX_0F380B */
5622 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5625 /* PREFIX_VEX_0F380C */
5629 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5632 /* PREFIX_VEX_0F380D */
5636 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5639 /* PREFIX_VEX_0F380E */
5643 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5646 /* PREFIX_VEX_0F380F */
5650 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5653 /* PREFIX_VEX_0F3813 */
5657 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5660 /* PREFIX_VEX_0F3816 */
5664 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5667 /* PREFIX_VEX_0F3817 */
5671 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5674 /* PREFIX_VEX_0F3818 */
5678 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5681 /* PREFIX_VEX_0F3819 */
5685 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5688 /* PREFIX_VEX_0F381A */
5692 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5695 /* PREFIX_VEX_0F381C */
5699 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5702 /* PREFIX_VEX_0F381D */
5706 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5709 /* PREFIX_VEX_0F381E */
5713 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5716 /* PREFIX_VEX_0F3820 */
5720 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5723 /* PREFIX_VEX_0F3821 */
5727 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5730 /* PREFIX_VEX_0F3822 */
5734 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5737 /* PREFIX_VEX_0F3823 */
5741 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5744 /* PREFIX_VEX_0F3824 */
5748 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5751 /* PREFIX_VEX_0F3825 */
5755 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5758 /* PREFIX_VEX_0F3828 */
5762 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5765 /* PREFIX_VEX_0F3829 */
5769 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5772 /* PREFIX_VEX_0F382A */
5776 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5779 /* PREFIX_VEX_0F382B */
5783 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5786 /* PREFIX_VEX_0F382C */
5790 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5793 /* PREFIX_VEX_0F382D */
5797 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5800 /* PREFIX_VEX_0F382E */
5804 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5807 /* PREFIX_VEX_0F382F */
5811 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5814 /* PREFIX_VEX_0F3830 */
5818 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5821 /* PREFIX_VEX_0F3831 */
5825 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
5828 /* PREFIX_VEX_0F3832 */
5832 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
5835 /* PREFIX_VEX_0F3833 */
5839 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
5842 /* PREFIX_VEX_0F3834 */
5846 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
5849 /* PREFIX_VEX_0F3835 */
5853 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
5856 /* PREFIX_VEX_0F3836 */
5860 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5863 /* PREFIX_VEX_0F3837 */
5867 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
5870 /* PREFIX_VEX_0F3838 */
5874 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
5877 /* PREFIX_VEX_0F3839 */
5881 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
5884 /* PREFIX_VEX_0F383A */
5888 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
5891 /* PREFIX_VEX_0F383B */
5895 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
5898 /* PREFIX_VEX_0F383C */
5902 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
5905 /* PREFIX_VEX_0F383D */
5909 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
5912 /* PREFIX_VEX_0F383E */
5916 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
5919 /* PREFIX_VEX_0F383F */
5923 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
5926 /* PREFIX_VEX_0F3840 */
5930 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
5933 /* PREFIX_VEX_0F3841 */
5937 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5940 /* PREFIX_VEX_0F3845 */
5944 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5947 /* PREFIX_VEX_0F3846 */
5951 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5954 /* PREFIX_VEX_0F3847 */
5958 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5961 /* PREFIX_VEX_0F3858 */
5965 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5968 /* PREFIX_VEX_0F3859 */
5972 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5975 /* PREFIX_VEX_0F385A */
5979 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5982 /* PREFIX_VEX_0F3878 */
5986 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5989 /* PREFIX_VEX_0F3879 */
5993 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5996 /* PREFIX_VEX_0F388C */
6000 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
6003 /* PREFIX_VEX_0F388E */
6007 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
6010 /* PREFIX_VEX_0F3890 */
6014 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6017 /* PREFIX_VEX_0F3891 */
6021 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6024 /* PREFIX_VEX_0F3892 */
6028 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6031 /* PREFIX_VEX_0F3893 */
6035 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6038 /* PREFIX_VEX_0F3896 */
6042 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6045 /* PREFIX_VEX_0F3897 */
6049 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6052 /* PREFIX_VEX_0F3898 */
6056 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6059 /* PREFIX_VEX_0F3899 */
6063 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6066 /* PREFIX_VEX_0F389A */
6070 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6073 /* PREFIX_VEX_0F389B */
6077 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6080 /* PREFIX_VEX_0F389C */
6084 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6087 /* PREFIX_VEX_0F389D */
6091 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6094 /* PREFIX_VEX_0F389E */
6098 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6101 /* PREFIX_VEX_0F389F */
6105 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6108 /* PREFIX_VEX_0F38A6 */
6112 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6116 /* PREFIX_VEX_0F38A7 */
6120 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6123 /* PREFIX_VEX_0F38A8 */
6127 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6130 /* PREFIX_VEX_0F38A9 */
6134 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6137 /* PREFIX_VEX_0F38AA */
6141 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6144 /* PREFIX_VEX_0F38AB */
6148 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6151 /* PREFIX_VEX_0F38AC */
6155 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6158 /* PREFIX_VEX_0F38AD */
6162 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6165 /* PREFIX_VEX_0F38AE */
6169 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6172 /* PREFIX_VEX_0F38AF */
6176 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6179 /* PREFIX_VEX_0F38B6 */
6183 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6186 /* PREFIX_VEX_0F38B7 */
6190 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6193 /* PREFIX_VEX_0F38B8 */
6197 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6200 /* PREFIX_VEX_0F38B9 */
6204 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6207 /* PREFIX_VEX_0F38BA */
6211 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6214 /* PREFIX_VEX_0F38BB */
6218 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6221 /* PREFIX_VEX_0F38BC */
6225 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6228 /* PREFIX_VEX_0F38BD */
6232 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6235 /* PREFIX_VEX_0F38BE */
6239 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6242 /* PREFIX_VEX_0F38BF */
6246 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6249 /* PREFIX_VEX_0F38DB */
6253 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6256 /* PREFIX_VEX_0F38DC */
6260 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
6263 /* PREFIX_VEX_0F38DD */
6267 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
6270 /* PREFIX_VEX_0F38DE */
6274 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
6277 /* PREFIX_VEX_0F38DF */
6281 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
6284 /* PREFIX_VEX_0F38F2 */
6286 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6289 /* PREFIX_VEX_0F38F3_REG_1 */
6291 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6294 /* PREFIX_VEX_0F38F3_REG_2 */
6296 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6299 /* PREFIX_VEX_0F38F3_REG_3 */
6301 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6304 /* PREFIX_VEX_0F38F5 */
6306 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6307 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6309 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6312 /* PREFIX_VEX_0F38F6 */
6317 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6320 /* PREFIX_VEX_0F38F7 */
6322 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6323 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6324 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6325 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6328 /* PREFIX_VEX_0F3A00 */
6332 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6335 /* PREFIX_VEX_0F3A01 */
6339 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6342 /* PREFIX_VEX_0F3A02 */
6346 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6349 /* PREFIX_VEX_0F3A04 */
6353 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6356 /* PREFIX_VEX_0F3A05 */
6360 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6363 /* PREFIX_VEX_0F3A06 */
6367 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6370 /* PREFIX_VEX_0F3A08 */
6374 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6377 /* PREFIX_VEX_0F3A09 */
6381 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6384 /* PREFIX_VEX_0F3A0A */
6388 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6391 /* PREFIX_VEX_0F3A0B */
6395 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6398 /* PREFIX_VEX_0F3A0C */
6402 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6405 /* PREFIX_VEX_0F3A0D */
6409 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6412 /* PREFIX_VEX_0F3A0E */
6416 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6419 /* PREFIX_VEX_0F3A0F */
6423 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6426 /* PREFIX_VEX_0F3A14 */
6430 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6433 /* PREFIX_VEX_0F3A15 */
6437 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6440 /* PREFIX_VEX_0F3A16 */
6444 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6447 /* PREFIX_VEX_0F3A17 */
6451 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6454 /* PREFIX_VEX_0F3A18 */
6458 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6461 /* PREFIX_VEX_0F3A19 */
6465 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6468 /* PREFIX_VEX_0F3A1D */
6472 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6475 /* PREFIX_VEX_0F3A20 */
6479 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6482 /* PREFIX_VEX_0F3A21 */
6486 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6489 /* PREFIX_VEX_0F3A22 */
6493 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6496 /* PREFIX_VEX_0F3A30 */
6500 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6503 /* PREFIX_VEX_0F3A31 */
6507 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6510 /* PREFIX_VEX_0F3A32 */
6514 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6517 /* PREFIX_VEX_0F3A33 */
6521 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6524 /* PREFIX_VEX_0F3A38 */
6528 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6531 /* PREFIX_VEX_0F3A39 */
6535 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6538 /* PREFIX_VEX_0F3A40 */
6542 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6545 /* PREFIX_VEX_0F3A41 */
6549 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6552 /* PREFIX_VEX_0F3A42 */
6556 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6559 /* PREFIX_VEX_0F3A44 */
6563 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
6566 /* PREFIX_VEX_0F3A46 */
6570 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6573 /* PREFIX_VEX_0F3A48 */
6577 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6580 /* PREFIX_VEX_0F3A49 */
6584 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6587 /* PREFIX_VEX_0F3A4A */
6591 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6594 /* PREFIX_VEX_0F3A4B */
6598 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6601 /* PREFIX_VEX_0F3A4C */
6605 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6608 /* PREFIX_VEX_0F3A5C */
6612 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6615 /* PREFIX_VEX_0F3A5D */
6619 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6622 /* PREFIX_VEX_0F3A5E */
6626 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6629 /* PREFIX_VEX_0F3A5F */
6633 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6636 /* PREFIX_VEX_0F3A60 */
6640 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6644 /* PREFIX_VEX_0F3A61 */
6648 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6651 /* PREFIX_VEX_0F3A62 */
6655 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6658 /* PREFIX_VEX_0F3A63 */
6662 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6665 /* PREFIX_VEX_0F3A68 */
6669 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6672 /* PREFIX_VEX_0F3A69 */
6676 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6679 /* PREFIX_VEX_0F3A6A */
6683 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6686 /* PREFIX_VEX_0F3A6B */
6690 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6693 /* PREFIX_VEX_0F3A6C */
6697 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6700 /* PREFIX_VEX_0F3A6D */
6704 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6707 /* PREFIX_VEX_0F3A6E */
6711 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6714 /* PREFIX_VEX_0F3A6F */
6718 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6721 /* PREFIX_VEX_0F3A78 */
6725 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6728 /* PREFIX_VEX_0F3A79 */
6732 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6735 /* PREFIX_VEX_0F3A7A */
6739 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6742 /* PREFIX_VEX_0F3A7B */
6746 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6749 /* PREFIX_VEX_0F3A7C */
6753 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6757 /* PREFIX_VEX_0F3A7D */
6761 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6764 /* PREFIX_VEX_0F3A7E */
6768 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6771 /* PREFIX_VEX_0F3A7F */
6775 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6778 /* PREFIX_VEX_0F3ADF */
6782 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6785 /* PREFIX_VEX_0F3AF0 */
6790 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6793 #define NEED_PREFIX_TABLE
6794 #include "i386-dis-evex.h"
6795 #undef NEED_PREFIX_TABLE
6798 static const struct dis386 x86_64_table
[][2] = {
6801 { "pushP", { es
}, 0 },
6806 { "popP", { es
}, 0 },
6811 { "pushP", { cs
}, 0 },
6816 { "pushP", { ss
}, 0 },
6821 { "popP", { ss
}, 0 },
6826 { "pushP", { ds
}, 0 },
6831 { "popP", { ds
}, 0 },
6836 { "daa", { XX
}, 0 },
6841 { "das", { XX
}, 0 },
6846 { "aaa", { XX
}, 0 },
6851 { "aas", { XX
}, 0 },
6856 { "pushaP", { XX
}, 0 },
6861 { "popaP", { XX
}, 0 },
6866 { MOD_TABLE (MOD_62_32BIT
) },
6867 { EVEX_TABLE (EVEX_0F
) },
6872 { "arpl", { Ew
, Gw
}, 0 },
6873 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6878 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6879 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6884 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6885 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6890 { "Jcall{T|}", { Ap
}, 0 },
6895 { MOD_TABLE (MOD_C4_32BIT
) },
6896 { VEX_C4_TABLE (VEX_0F
) },
6901 { MOD_TABLE (MOD_C5_32BIT
) },
6902 { VEX_C5_TABLE (VEX_0F
) },
6907 { "into", { XX
}, 0 },
6912 { "aam", { Ib
}, 0 },
6917 { "aad", { Ib
}, 0 },
6922 { "callP", { Jv
, BND
}, 0 },
6923 { "call@", { Jv
, BND
}, 0 }
6928 { "jmpP", { Jv
, BND
}, 0 },
6929 { "jmp@", { Jv
, BND
}, 0 }
6934 { "Jjmp{T|}", { Ap
}, 0 },
6937 /* X86_64_0F01_REG_0 */
6939 { "sgdt{Q|IQ}", { M
}, 0 },
6940 { "sgdt", { M
}, 0 },
6943 /* X86_64_0F01_REG_1 */
6945 { "sidt{Q|IQ}", { M
}, 0 },
6946 { "sidt", { M
}, 0 },
6949 /* X86_64_0F01_REG_2 */
6951 { "lgdt{Q|Q}", { M
}, 0 },
6952 { "lgdt", { M
}, 0 },
6955 /* X86_64_0F01_REG_3 */
6957 { "lidt{Q|Q}", { M
}, 0 },
6958 { "lidt", { M
}, 0 },
6962 static const struct dis386 three_byte_table
[][256] = {
6964 /* THREE_BYTE_0F38 */
6967 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6968 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6969 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6970 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6971 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6972 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6973 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6974 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6976 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6977 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6978 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6979 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6985 { PREFIX_TABLE (PREFIX_0F3810
) },
6989 { PREFIX_TABLE (PREFIX_0F3814
) },
6990 { PREFIX_TABLE (PREFIX_0F3815
) },
6992 { PREFIX_TABLE (PREFIX_0F3817
) },
6998 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
6999 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7000 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7003 { PREFIX_TABLE (PREFIX_0F3820
) },
7004 { PREFIX_TABLE (PREFIX_0F3821
) },
7005 { PREFIX_TABLE (PREFIX_0F3822
) },
7006 { PREFIX_TABLE (PREFIX_0F3823
) },
7007 { PREFIX_TABLE (PREFIX_0F3824
) },
7008 { PREFIX_TABLE (PREFIX_0F3825
) },
7012 { PREFIX_TABLE (PREFIX_0F3828
) },
7013 { PREFIX_TABLE (PREFIX_0F3829
) },
7014 { PREFIX_TABLE (PREFIX_0F382A
) },
7015 { PREFIX_TABLE (PREFIX_0F382B
) },
7021 { PREFIX_TABLE (PREFIX_0F3830
) },
7022 { PREFIX_TABLE (PREFIX_0F3831
) },
7023 { PREFIX_TABLE (PREFIX_0F3832
) },
7024 { PREFIX_TABLE (PREFIX_0F3833
) },
7025 { PREFIX_TABLE (PREFIX_0F3834
) },
7026 { PREFIX_TABLE (PREFIX_0F3835
) },
7028 { PREFIX_TABLE (PREFIX_0F3837
) },
7030 { PREFIX_TABLE (PREFIX_0F3838
) },
7031 { PREFIX_TABLE (PREFIX_0F3839
) },
7032 { PREFIX_TABLE (PREFIX_0F383A
) },
7033 { PREFIX_TABLE (PREFIX_0F383B
) },
7034 { PREFIX_TABLE (PREFIX_0F383C
) },
7035 { PREFIX_TABLE (PREFIX_0F383D
) },
7036 { PREFIX_TABLE (PREFIX_0F383E
) },
7037 { PREFIX_TABLE (PREFIX_0F383F
) },
7039 { PREFIX_TABLE (PREFIX_0F3840
) },
7040 { PREFIX_TABLE (PREFIX_0F3841
) },
7111 { PREFIX_TABLE (PREFIX_0F3880
) },
7112 { PREFIX_TABLE (PREFIX_0F3881
) },
7113 { PREFIX_TABLE (PREFIX_0F3882
) },
7192 { PREFIX_TABLE (PREFIX_0F38C8
) },
7193 { PREFIX_TABLE (PREFIX_0F38C9
) },
7194 { PREFIX_TABLE (PREFIX_0F38CA
) },
7195 { PREFIX_TABLE (PREFIX_0F38CB
) },
7196 { PREFIX_TABLE (PREFIX_0F38CC
) },
7197 { PREFIX_TABLE (PREFIX_0F38CD
) },
7213 { PREFIX_TABLE (PREFIX_0F38DB
) },
7214 { PREFIX_TABLE (PREFIX_0F38DC
) },
7215 { PREFIX_TABLE (PREFIX_0F38DD
) },
7216 { PREFIX_TABLE (PREFIX_0F38DE
) },
7217 { PREFIX_TABLE (PREFIX_0F38DF
) },
7237 { PREFIX_TABLE (PREFIX_0F38F0
) },
7238 { PREFIX_TABLE (PREFIX_0F38F1
) },
7243 { PREFIX_TABLE (PREFIX_0F38F6
) },
7255 /* THREE_BYTE_0F3A */
7267 { PREFIX_TABLE (PREFIX_0F3A08
) },
7268 { PREFIX_TABLE (PREFIX_0F3A09
) },
7269 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7270 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7271 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7272 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7273 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7274 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7280 { PREFIX_TABLE (PREFIX_0F3A14
) },
7281 { PREFIX_TABLE (PREFIX_0F3A15
) },
7282 { PREFIX_TABLE (PREFIX_0F3A16
) },
7283 { PREFIX_TABLE (PREFIX_0F3A17
) },
7294 { PREFIX_TABLE (PREFIX_0F3A20
) },
7295 { PREFIX_TABLE (PREFIX_0F3A21
) },
7296 { PREFIX_TABLE (PREFIX_0F3A22
) },
7330 { PREFIX_TABLE (PREFIX_0F3A40
) },
7331 { PREFIX_TABLE (PREFIX_0F3A41
) },
7332 { PREFIX_TABLE (PREFIX_0F3A42
) },
7334 { PREFIX_TABLE (PREFIX_0F3A44
) },
7366 { PREFIX_TABLE (PREFIX_0F3A60
) },
7367 { PREFIX_TABLE (PREFIX_0F3A61
) },
7368 { PREFIX_TABLE (PREFIX_0F3A62
) },
7369 { PREFIX_TABLE (PREFIX_0F3A63
) },
7487 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7508 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7547 /* THREE_BYTE_0F7A */
7623 { "phaddbw", { XM
, EXq
}, PREFIX_OPCODE
},
7624 { "phaddbd", { XM
, EXq
}, PREFIX_OPCODE
},
7625 { "phaddbq", { XM
, EXq
}, PREFIX_OPCODE
},
7628 { "phaddwd", { XM
, EXq
}, PREFIX_OPCODE
},
7629 { "phaddwq", { XM
, EXq
}, PREFIX_OPCODE
},
7634 { "phadddq", { XM
, EXq
}, PREFIX_OPCODE
},
7641 { "phaddubw", { XM
, EXq
}, PREFIX_OPCODE
},
7642 { "phaddubd", { XM
, EXq
}, PREFIX_OPCODE
},
7643 { "phaddubq", { XM
, EXq
}, PREFIX_OPCODE
},
7646 { "phadduwd", { XM
, EXq
}, PREFIX_OPCODE
},
7647 { "phadduwq", { XM
, EXq
}, PREFIX_OPCODE
},
7652 { "phaddudq", { XM
, EXq
}, PREFIX_OPCODE
},
7659 { "phsubbw", { XM
, EXq
}, PREFIX_OPCODE
},
7660 { "phsubbd", { XM
, EXq
}, PREFIX_OPCODE
},
7661 { "phsubbq", { XM
, EXq
}, PREFIX_OPCODE
},
7840 static const struct dis386 xop_table
[][256] = {
7993 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7994 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7995 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8003 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8004 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8011 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8012 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8013 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8021 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8022 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8026 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8027 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8030 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8048 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8060 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
8061 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
8062 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
8063 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
8073 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
8074 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
8075 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
8076 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
8109 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
8110 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
8111 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
8112 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
8136 { REG_TABLE (REG_XOP_TBM_01
) },
8137 { REG_TABLE (REG_XOP_TBM_02
) },
8155 { REG_TABLE (REG_XOP_LWPCB
) },
8279 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8280 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8281 { "vfrczss", { XM
, EXd
}, 0 },
8282 { "vfrczsd", { XM
, EXq
}, 0 },
8297 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8298 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8299 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8300 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8301 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8302 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8303 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8304 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8306 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8307 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8308 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8309 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8352 { "vphaddbw", { XM
, EXxmm
}, 0 },
8353 { "vphaddbd", { XM
, EXxmm
}, 0 },
8354 { "vphaddbq", { XM
, EXxmm
}, 0 },
8357 { "vphaddwd", { XM
, EXxmm
}, 0 },
8358 { "vphaddwq", { XM
, EXxmm
}, 0 },
8363 { "vphadddq", { XM
, EXxmm
}, 0 },
8370 { "vphaddubw", { XM
, EXxmm
}, 0 },
8371 { "vphaddubd", { XM
, EXxmm
}, 0 },
8372 { "vphaddubq", { XM
, EXxmm
}, 0 },
8375 { "vphadduwd", { XM
, EXxmm
}, 0 },
8376 { "vphadduwq", { XM
, EXxmm
}, 0 },
8381 { "vphaddudq", { XM
, EXxmm
}, 0 },
8388 { "vphsubbw", { XM
, EXxmm
}, 0 },
8389 { "vphsubwd", { XM
, EXxmm
}, 0 },
8390 { "vphsubdq", { XM
, EXxmm
}, 0 },
8444 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8446 { REG_TABLE (REG_XOP_LWP
) },
8716 static const struct dis386 vex_table
[][256] = {
8738 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8741 { MOD_TABLE (MOD_VEX_0F13
) },
8742 { VEX_W_TABLE (VEX_W_0F14
) },
8743 { VEX_W_TABLE (VEX_W_0F15
) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8745 { MOD_TABLE (MOD_VEX_0F17
) },
8765 { VEX_W_TABLE (VEX_W_0F28
) },
8766 { VEX_W_TABLE (VEX_W_0F29
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8768 { MOD_TABLE (MOD_VEX_0F2B
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8810 { MOD_TABLE (MOD_VEX_0F50
) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8812 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8813 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8814 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8815 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8816 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8817 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8819 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8820 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8821 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8822 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8823 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8824 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8825 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8828 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8830 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8831 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8832 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8833 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8834 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8835 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8837 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8838 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8839 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8840 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8841 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8842 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8843 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8844 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8846 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8847 { REG_TABLE (REG_VEX_0F71
) },
8848 { REG_TABLE (REG_VEX_0F72
) },
8849 { REG_TABLE (REG_VEX_0F73
) },
8850 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8851 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8852 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8853 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8859 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8860 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8861 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8862 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8882 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8884 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8915 { REG_TABLE (REG_VEX_0FAE
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8941 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8942 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8954 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8956 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8957 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8958 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8959 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8960 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8961 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8963 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8964 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8965 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8966 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8967 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8968 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8969 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8972 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8973 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8974 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8975 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8978 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8979 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8981 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8982 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8983 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8984 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8985 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8986 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8987 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8988 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8990 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8991 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8992 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8994 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8995 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8996 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8997 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8999 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
9000 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
9001 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
9002 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
9004 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
9005 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
9013 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
9020 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
9032 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
9035 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
9036 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
9081 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
9083 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
9112 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
9146 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
9147 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
9168 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
9170 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
9173 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
9174 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
9175 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
9176 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
9179 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
9180 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
9182 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
9183 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
9184 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
9185 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
9186 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
9187 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
9188 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
9197 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
9198 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
9200 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
9201 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
9202 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
9203 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
9204 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
9205 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
9206 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
9207 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
9215 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
9216 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
9218 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
9219 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
9220 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
9221 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
9222 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
9223 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
9224 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
9225 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
9257 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9258 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9259 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9260 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9261 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9283 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9284 { REG_TABLE (REG_VEX_0F38F3
) },
9286 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9287 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9288 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9302 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9303 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9304 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9306 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9307 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9308 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9311 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9312 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9314 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9315 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9316 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9317 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9318 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9324 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9325 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9326 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9327 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9329 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9330 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9334 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9338 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9339 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9340 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9356 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9357 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9358 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9359 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9365 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9366 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9374 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9375 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9376 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9378 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9380 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9383 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9384 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9385 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9386 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9387 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9405 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9406 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9407 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9408 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9410 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9411 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9412 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9413 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9419 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9420 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9421 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9422 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9423 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9424 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9425 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9426 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9437 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9438 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9439 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9440 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9441 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9442 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9443 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9444 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9552 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9572 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9592 #define NEED_OPCODE_TABLE
9593 #include "i386-dis-evex.h"
9594 #undef NEED_OPCODE_TABLE
9595 static const struct dis386 vex_len_table
[][2] = {
9596 /* VEX_LEN_0F10_P_1 */
9598 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9599 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9602 /* VEX_LEN_0F10_P_3 */
9604 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9605 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9608 /* VEX_LEN_0F11_P_1 */
9610 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9611 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9614 /* VEX_LEN_0F11_P_3 */
9616 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9617 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9620 /* VEX_LEN_0F12_P_0_M_0 */
9622 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9625 /* VEX_LEN_0F12_P_0_M_1 */
9627 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9630 /* VEX_LEN_0F12_P_2 */
9632 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9635 /* VEX_LEN_0F13_M_0 */
9637 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9640 /* VEX_LEN_0F16_P_0_M_0 */
9642 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9645 /* VEX_LEN_0F16_P_0_M_1 */
9647 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9650 /* VEX_LEN_0F16_P_2 */
9652 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9655 /* VEX_LEN_0F17_M_0 */
9657 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9660 /* VEX_LEN_0F2A_P_1 */
9662 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9663 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9666 /* VEX_LEN_0F2A_P_3 */
9668 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9669 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9672 /* VEX_LEN_0F2C_P_1 */
9674 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9675 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9678 /* VEX_LEN_0F2C_P_3 */
9680 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9681 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9684 /* VEX_LEN_0F2D_P_1 */
9686 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9687 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9690 /* VEX_LEN_0F2D_P_3 */
9692 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9693 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9696 /* VEX_LEN_0F2E_P_0 */
9698 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9699 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9702 /* VEX_LEN_0F2E_P_2 */
9704 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9705 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9708 /* VEX_LEN_0F2F_P_0 */
9710 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9711 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9714 /* VEX_LEN_0F2F_P_2 */
9716 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9717 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9720 /* VEX_LEN_0F41_P_0 */
9723 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9725 /* VEX_LEN_0F41_P_2 */
9728 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9730 /* VEX_LEN_0F42_P_0 */
9733 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9735 /* VEX_LEN_0F42_P_2 */
9738 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9740 /* VEX_LEN_0F44_P_0 */
9742 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9744 /* VEX_LEN_0F44_P_2 */
9746 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9748 /* VEX_LEN_0F45_P_0 */
9751 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9753 /* VEX_LEN_0F45_P_2 */
9756 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9758 /* VEX_LEN_0F46_P_0 */
9761 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9763 /* VEX_LEN_0F46_P_2 */
9766 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9768 /* VEX_LEN_0F47_P_0 */
9771 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9773 /* VEX_LEN_0F47_P_2 */
9776 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9778 /* VEX_LEN_0F4A_P_0 */
9781 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9783 /* VEX_LEN_0F4A_P_2 */
9786 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9788 /* VEX_LEN_0F4B_P_0 */
9791 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9793 /* VEX_LEN_0F4B_P_2 */
9796 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9799 /* VEX_LEN_0F51_P_1 */
9801 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9802 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9805 /* VEX_LEN_0F51_P_3 */
9807 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9808 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9811 /* VEX_LEN_0F52_P_1 */
9813 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9814 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9817 /* VEX_LEN_0F53_P_1 */
9819 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9820 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9823 /* VEX_LEN_0F58_P_1 */
9825 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9826 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9829 /* VEX_LEN_0F58_P_3 */
9831 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9832 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9835 /* VEX_LEN_0F59_P_1 */
9837 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9838 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9841 /* VEX_LEN_0F59_P_3 */
9843 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9844 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9847 /* VEX_LEN_0F5A_P_1 */
9849 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9850 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9853 /* VEX_LEN_0F5A_P_3 */
9855 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9856 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9859 /* VEX_LEN_0F5C_P_1 */
9861 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9862 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9865 /* VEX_LEN_0F5C_P_3 */
9867 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9868 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9871 /* VEX_LEN_0F5D_P_1 */
9873 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9874 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9877 /* VEX_LEN_0F5D_P_3 */
9879 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9880 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9883 /* VEX_LEN_0F5E_P_1 */
9885 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9886 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9889 /* VEX_LEN_0F5E_P_3 */
9891 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9892 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9895 /* VEX_LEN_0F5F_P_1 */
9897 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9898 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9901 /* VEX_LEN_0F5F_P_3 */
9903 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9904 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9907 /* VEX_LEN_0F6E_P_2 */
9909 { "vmovK", { XMScalar
, Edq
}, 0 },
9910 { "vmovK", { XMScalar
, Edq
}, 0 },
9913 /* VEX_LEN_0F7E_P_1 */
9915 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9916 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9919 /* VEX_LEN_0F7E_P_2 */
9921 { "vmovK", { Edq
, XMScalar
}, 0 },
9922 { "vmovK", { Edq
, XMScalar
}, 0 },
9925 /* VEX_LEN_0F90_P_0 */
9927 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9930 /* VEX_LEN_0F90_P_2 */
9932 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9935 /* VEX_LEN_0F91_P_0 */
9937 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9940 /* VEX_LEN_0F91_P_2 */
9942 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9945 /* VEX_LEN_0F92_P_0 */
9947 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9950 /* VEX_LEN_0F92_P_2 */
9952 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9955 /* VEX_LEN_0F92_P_3 */
9957 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9960 /* VEX_LEN_0F93_P_0 */
9962 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9965 /* VEX_LEN_0F93_P_2 */
9967 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9970 /* VEX_LEN_0F93_P_3 */
9972 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9975 /* VEX_LEN_0F98_P_0 */
9977 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9980 /* VEX_LEN_0F98_P_2 */
9982 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9985 /* VEX_LEN_0F99_P_0 */
9987 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9990 /* VEX_LEN_0F99_P_2 */
9992 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9995 /* VEX_LEN_0FAE_R_2_M_0 */
9997 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
10000 /* VEX_LEN_0FAE_R_3_M_0 */
10002 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
10005 /* VEX_LEN_0FC2_P_1 */
10007 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
10008 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
10011 /* VEX_LEN_0FC2_P_3 */
10013 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
10014 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
10017 /* VEX_LEN_0FC4_P_2 */
10019 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
10022 /* VEX_LEN_0FC5_P_2 */
10024 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
10027 /* VEX_LEN_0FD6_P_2 */
10029 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
10030 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
10033 /* VEX_LEN_0FF7_P_2 */
10035 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
10038 /* VEX_LEN_0F3816_P_2 */
10041 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
10044 /* VEX_LEN_0F3819_P_2 */
10047 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
10050 /* VEX_LEN_0F381A_P_2_M_0 */
10053 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
10056 /* VEX_LEN_0F3836_P_2 */
10059 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
10062 /* VEX_LEN_0F3841_P_2 */
10064 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
10067 /* VEX_LEN_0F385A_P_2_M_0 */
10070 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
10073 /* VEX_LEN_0F38DB_P_2 */
10075 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
10078 /* VEX_LEN_0F38DC_P_2 */
10080 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
10083 /* VEX_LEN_0F38DD_P_2 */
10085 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
10088 /* VEX_LEN_0F38DE_P_2 */
10090 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
10093 /* VEX_LEN_0F38DF_P_2 */
10095 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
10098 /* VEX_LEN_0F38F2_P_0 */
10100 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
10103 /* VEX_LEN_0F38F3_R_1_P_0 */
10105 { "blsrS", { VexGdq
, Edq
}, 0 },
10108 /* VEX_LEN_0F38F3_R_2_P_0 */
10110 { "blsmskS", { VexGdq
, Edq
}, 0 },
10113 /* VEX_LEN_0F38F3_R_3_P_0 */
10115 { "blsiS", { VexGdq
, Edq
}, 0 },
10118 /* VEX_LEN_0F38F5_P_0 */
10120 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
10123 /* VEX_LEN_0F38F5_P_1 */
10125 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
10128 /* VEX_LEN_0F38F5_P_3 */
10130 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
10133 /* VEX_LEN_0F38F6_P_3 */
10135 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
10138 /* VEX_LEN_0F38F7_P_0 */
10140 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
10143 /* VEX_LEN_0F38F7_P_1 */
10145 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
10148 /* VEX_LEN_0F38F7_P_2 */
10150 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
10153 /* VEX_LEN_0F38F7_P_3 */
10155 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
10158 /* VEX_LEN_0F3A00_P_2 */
10161 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
10164 /* VEX_LEN_0F3A01_P_2 */
10167 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
10170 /* VEX_LEN_0F3A06_P_2 */
10173 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
10176 /* VEX_LEN_0F3A0A_P_2 */
10178 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10179 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10182 /* VEX_LEN_0F3A0B_P_2 */
10184 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10185 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10188 /* VEX_LEN_0F3A14_P_2 */
10190 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
10193 /* VEX_LEN_0F3A15_P_2 */
10195 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
10198 /* VEX_LEN_0F3A16_P_2 */
10200 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
10203 /* VEX_LEN_0F3A17_P_2 */
10205 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
10208 /* VEX_LEN_0F3A18_P_2 */
10211 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
10214 /* VEX_LEN_0F3A19_P_2 */
10217 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
10220 /* VEX_LEN_0F3A20_P_2 */
10222 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
10225 /* VEX_LEN_0F3A21_P_2 */
10227 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
10230 /* VEX_LEN_0F3A22_P_2 */
10232 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
10235 /* VEX_LEN_0F3A30_P_2 */
10237 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
10240 /* VEX_LEN_0F3A31_P_2 */
10242 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
10245 /* VEX_LEN_0F3A32_P_2 */
10247 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
10250 /* VEX_LEN_0F3A33_P_2 */
10252 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
10255 /* VEX_LEN_0F3A38_P_2 */
10258 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
10261 /* VEX_LEN_0F3A39_P_2 */
10264 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
10267 /* VEX_LEN_0F3A41_P_2 */
10269 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
10272 /* VEX_LEN_0F3A44_P_2 */
10274 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
10277 /* VEX_LEN_0F3A46_P_2 */
10280 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
10283 /* VEX_LEN_0F3A60_P_2 */
10285 { VEX_W_TABLE (VEX_W_0F3A60_P_2
) },
10288 /* VEX_LEN_0F3A61_P_2 */
10290 { VEX_W_TABLE (VEX_W_0F3A61_P_2
) },
10293 /* VEX_LEN_0F3A62_P_2 */
10295 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
10298 /* VEX_LEN_0F3A63_P_2 */
10300 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
10303 /* VEX_LEN_0F3A6A_P_2 */
10305 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10308 /* VEX_LEN_0F3A6B_P_2 */
10310 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10313 /* VEX_LEN_0F3A6E_P_2 */
10315 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10318 /* VEX_LEN_0F3A6F_P_2 */
10320 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10323 /* VEX_LEN_0F3A7A_P_2 */
10325 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10328 /* VEX_LEN_0F3A7B_P_2 */
10330 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10333 /* VEX_LEN_0F3A7E_P_2 */
10335 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10338 /* VEX_LEN_0F3A7F_P_2 */
10340 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10343 /* VEX_LEN_0F3ADF_P_2 */
10345 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
10348 /* VEX_LEN_0F3AF0_P_3 */
10350 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
10353 /* VEX_LEN_0FXOP_08_CC */
10355 { "vpcomb", { XM
, Vex128
, EXx
, Ib
}, 0 },
10358 /* VEX_LEN_0FXOP_08_CD */
10360 { "vpcomw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10363 /* VEX_LEN_0FXOP_08_CE */
10365 { "vpcomd", { XM
, Vex128
, EXx
, Ib
}, 0 },
10368 /* VEX_LEN_0FXOP_08_CF */
10370 { "vpcomq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10373 /* VEX_LEN_0FXOP_08_EC */
10375 { "vpcomub", { XM
, Vex128
, EXx
, Ib
}, 0 },
10378 /* VEX_LEN_0FXOP_08_ED */
10380 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10383 /* VEX_LEN_0FXOP_08_EE */
10385 { "vpcomud", { XM
, Vex128
, EXx
, Ib
}, 0 },
10388 /* VEX_LEN_0FXOP_08_EF */
10390 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10393 /* VEX_LEN_0FXOP_09_80 */
10395 { "vfrczps", { XM
, EXxmm
}, 0 },
10396 { "vfrczps", { XM
, EXymmq
}, 0 },
10399 /* VEX_LEN_0FXOP_09_81 */
10401 { "vfrczpd", { XM
, EXxmm
}, 0 },
10402 { "vfrczpd", { XM
, EXymmq
}, 0 },
10406 static const struct dis386 vex_w_table
[][2] = {
10408 /* VEX_W_0F10_P_0 */
10409 { "vmovups", { XM
, EXx
}, 0 },
10412 /* VEX_W_0F10_P_1 */
10413 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
10416 /* VEX_W_0F10_P_2 */
10417 { "vmovupd", { XM
, EXx
}, 0 },
10420 /* VEX_W_0F10_P_3 */
10421 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
10424 /* VEX_W_0F11_P_0 */
10425 { "vmovups", { EXxS
, XM
}, 0 },
10428 /* VEX_W_0F11_P_1 */
10429 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
10432 /* VEX_W_0F11_P_2 */
10433 { "vmovupd", { EXxS
, XM
}, 0 },
10436 /* VEX_W_0F11_P_3 */
10437 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
10440 /* VEX_W_0F12_P_0_M_0 */
10441 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
10444 /* VEX_W_0F12_P_0_M_1 */
10445 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
10448 /* VEX_W_0F12_P_1 */
10449 { "vmovsldup", { XM
, EXx
}, 0 },
10452 /* VEX_W_0F12_P_2 */
10453 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
10456 /* VEX_W_0F12_P_3 */
10457 { "vmovddup", { XM
, EXymmq
}, 0 },
10460 /* VEX_W_0F13_M_0 */
10461 { "vmovlpX", { EXq
, XM
}, 0 },
10465 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
10469 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
10472 /* VEX_W_0F16_P_0_M_0 */
10473 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
10476 /* VEX_W_0F16_P_0_M_1 */
10477 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
10480 /* VEX_W_0F16_P_1 */
10481 { "vmovshdup", { XM
, EXx
}, 0 },
10484 /* VEX_W_0F16_P_2 */
10485 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
10488 /* VEX_W_0F17_M_0 */
10489 { "vmovhpX", { EXq
, XM
}, 0 },
10493 { "vmovapX", { XM
, EXx
}, 0 },
10497 { "vmovapX", { EXxS
, XM
}, 0 },
10500 /* VEX_W_0F2B_M_0 */
10501 { "vmovntpX", { Mx
, XM
}, 0 },
10504 /* VEX_W_0F2E_P_0 */
10505 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
10508 /* VEX_W_0F2E_P_2 */
10509 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
10512 /* VEX_W_0F2F_P_0 */
10513 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
10516 /* VEX_W_0F2F_P_2 */
10517 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
10520 /* VEX_W_0F41_P_0_LEN_1 */
10521 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
10522 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
10525 /* VEX_W_0F41_P_2_LEN_1 */
10526 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
10527 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
10530 /* VEX_W_0F42_P_0_LEN_1 */
10531 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
10532 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
10535 /* VEX_W_0F42_P_2_LEN_1 */
10536 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
10537 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
10540 /* VEX_W_0F44_P_0_LEN_0 */
10541 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
10542 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
10545 /* VEX_W_0F44_P_2_LEN_0 */
10546 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
10547 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
10550 /* VEX_W_0F45_P_0_LEN_1 */
10551 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
10552 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
10555 /* VEX_W_0F45_P_2_LEN_1 */
10556 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
10557 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
10560 /* VEX_W_0F46_P_0_LEN_1 */
10561 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
10562 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
10565 /* VEX_W_0F46_P_2_LEN_1 */
10566 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
10567 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
10570 /* VEX_W_0F47_P_0_LEN_1 */
10571 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
10572 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
10575 /* VEX_W_0F47_P_2_LEN_1 */
10576 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
10577 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
10580 /* VEX_W_0F4A_P_0_LEN_1 */
10581 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
10582 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
10585 /* VEX_W_0F4A_P_2_LEN_1 */
10586 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
10587 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
10590 /* VEX_W_0F4B_P_0_LEN_1 */
10591 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
10592 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
10595 /* VEX_W_0F4B_P_2_LEN_1 */
10596 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
10599 /* VEX_W_0F50_M_0 */
10600 { "vmovmskpX", { Gdq
, XS
}, 0 },
10603 /* VEX_W_0F51_P_0 */
10604 { "vsqrtps", { XM
, EXx
}, 0 },
10607 /* VEX_W_0F51_P_1 */
10608 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10611 /* VEX_W_0F51_P_2 */
10612 { "vsqrtpd", { XM
, EXx
}, 0 },
10615 /* VEX_W_0F51_P_3 */
10616 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10619 /* VEX_W_0F52_P_0 */
10620 { "vrsqrtps", { XM
, EXx
}, 0 },
10623 /* VEX_W_0F52_P_1 */
10624 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10627 /* VEX_W_0F53_P_0 */
10628 { "vrcpps", { XM
, EXx
}, 0 },
10631 /* VEX_W_0F53_P_1 */
10632 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10635 /* VEX_W_0F58_P_0 */
10636 { "vaddps", { XM
, Vex
, EXx
}, 0 },
10639 /* VEX_W_0F58_P_1 */
10640 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10643 /* VEX_W_0F58_P_2 */
10644 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
10647 /* VEX_W_0F58_P_3 */
10648 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10651 /* VEX_W_0F59_P_0 */
10652 { "vmulps", { XM
, Vex
, EXx
}, 0 },
10655 /* VEX_W_0F59_P_1 */
10656 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10659 /* VEX_W_0F59_P_2 */
10660 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
10663 /* VEX_W_0F59_P_3 */
10664 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10667 /* VEX_W_0F5A_P_0 */
10668 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
10671 /* VEX_W_0F5A_P_1 */
10672 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10675 /* VEX_W_0F5A_P_3 */
10676 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10679 /* VEX_W_0F5B_P_0 */
10680 { "vcvtdq2ps", { XM
, EXx
}, 0 },
10683 /* VEX_W_0F5B_P_1 */
10684 { "vcvttps2dq", { XM
, EXx
}, 0 },
10687 /* VEX_W_0F5B_P_2 */
10688 { "vcvtps2dq", { XM
, EXx
}, 0 },
10691 /* VEX_W_0F5C_P_0 */
10692 { "vsubps", { XM
, Vex
, EXx
}, 0 },
10695 /* VEX_W_0F5C_P_1 */
10696 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10699 /* VEX_W_0F5C_P_2 */
10700 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
10703 /* VEX_W_0F5C_P_3 */
10704 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10707 /* VEX_W_0F5D_P_0 */
10708 { "vminps", { XM
, Vex
, EXx
}, 0 },
10711 /* VEX_W_0F5D_P_1 */
10712 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10715 /* VEX_W_0F5D_P_2 */
10716 { "vminpd", { XM
, Vex
, EXx
}, 0 },
10719 /* VEX_W_0F5D_P_3 */
10720 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10723 /* VEX_W_0F5E_P_0 */
10724 { "vdivps", { XM
, Vex
, EXx
}, 0 },
10727 /* VEX_W_0F5E_P_1 */
10728 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10731 /* VEX_W_0F5E_P_2 */
10732 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
10735 /* VEX_W_0F5E_P_3 */
10736 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10739 /* VEX_W_0F5F_P_0 */
10740 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
10743 /* VEX_W_0F5F_P_1 */
10744 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10747 /* VEX_W_0F5F_P_2 */
10748 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
10751 /* VEX_W_0F5F_P_3 */
10752 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10755 /* VEX_W_0F60_P_2 */
10756 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
10759 /* VEX_W_0F61_P_2 */
10760 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
10763 /* VEX_W_0F62_P_2 */
10764 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
10767 /* VEX_W_0F63_P_2 */
10768 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
10771 /* VEX_W_0F64_P_2 */
10772 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
10775 /* VEX_W_0F65_P_2 */
10776 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
10779 /* VEX_W_0F66_P_2 */
10780 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
10783 /* VEX_W_0F67_P_2 */
10784 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
10787 /* VEX_W_0F68_P_2 */
10788 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
10791 /* VEX_W_0F69_P_2 */
10792 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
10795 /* VEX_W_0F6A_P_2 */
10796 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
10799 /* VEX_W_0F6B_P_2 */
10800 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
10803 /* VEX_W_0F6C_P_2 */
10804 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
10807 /* VEX_W_0F6D_P_2 */
10808 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
10811 /* VEX_W_0F6F_P_1 */
10812 { "vmovdqu", { XM
, EXx
}, 0 },
10815 /* VEX_W_0F6F_P_2 */
10816 { "vmovdqa", { XM
, EXx
}, 0 },
10819 /* VEX_W_0F70_P_1 */
10820 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
10823 /* VEX_W_0F70_P_2 */
10824 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
10827 /* VEX_W_0F70_P_3 */
10828 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
10831 /* VEX_W_0F71_R_2_P_2 */
10832 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
10835 /* VEX_W_0F71_R_4_P_2 */
10836 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
10839 /* VEX_W_0F71_R_6_P_2 */
10840 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
10843 /* VEX_W_0F72_R_2_P_2 */
10844 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
10847 /* VEX_W_0F72_R_4_P_2 */
10848 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
10851 /* VEX_W_0F72_R_6_P_2 */
10852 { "vpslld", { Vex
, XS
, Ib
}, 0 },
10855 /* VEX_W_0F73_R_2_P_2 */
10856 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
10859 /* VEX_W_0F73_R_3_P_2 */
10860 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
10863 /* VEX_W_0F73_R_6_P_2 */
10864 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
10867 /* VEX_W_0F73_R_7_P_2 */
10868 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
10871 /* VEX_W_0F74_P_2 */
10872 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
10875 /* VEX_W_0F75_P_2 */
10876 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
10879 /* VEX_W_0F76_P_2 */
10880 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
10883 /* VEX_W_0F77_P_0 */
10884 { "", { VZERO
}, 0 },
10887 /* VEX_W_0F7C_P_2 */
10888 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
10891 /* VEX_W_0F7C_P_3 */
10892 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
10895 /* VEX_W_0F7D_P_2 */
10896 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
10899 /* VEX_W_0F7D_P_3 */
10900 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
10903 /* VEX_W_0F7E_P_1 */
10904 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
10907 /* VEX_W_0F7F_P_1 */
10908 { "vmovdqu", { EXxS
, XM
}, 0 },
10911 /* VEX_W_0F7F_P_2 */
10912 { "vmovdqa", { EXxS
, XM
}, 0 },
10915 /* VEX_W_0F90_P_0_LEN_0 */
10916 { "kmovw", { MaskG
, MaskE
}, 0 },
10917 { "kmovq", { MaskG
, MaskE
}, 0 },
10920 /* VEX_W_0F90_P_2_LEN_0 */
10921 { "kmovb", { MaskG
, MaskBDE
}, 0 },
10922 { "kmovd", { MaskG
, MaskBDE
}, 0 },
10925 /* VEX_W_0F91_P_0_LEN_0 */
10926 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
10927 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
10930 /* VEX_W_0F91_P_2_LEN_0 */
10931 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
10932 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
10935 /* VEX_W_0F92_P_0_LEN_0 */
10936 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10939 /* VEX_W_0F92_P_2_LEN_0 */
10940 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10943 /* VEX_W_0F92_P_3_LEN_0 */
10944 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0
) },
10945 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0
) },
10948 /* VEX_W_0F93_P_0_LEN_0 */
10949 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10952 /* VEX_W_0F93_P_2_LEN_0 */
10953 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10956 /* VEX_W_0F93_P_3_LEN_0 */
10957 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0
) },
10958 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0
) },
10961 /* VEX_W_0F98_P_0_LEN_0 */
10962 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10963 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10966 /* VEX_W_0F98_P_2_LEN_0 */
10967 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10968 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10971 /* VEX_W_0F99_P_0_LEN_0 */
10972 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10973 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10976 /* VEX_W_0F99_P_2_LEN_0 */
10977 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10978 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10981 /* VEX_W_0FAE_R_2_M_0 */
10982 { "vldmxcsr", { Md
}, 0 },
10985 /* VEX_W_0FAE_R_3_M_0 */
10986 { "vstmxcsr", { Md
}, 0 },
10989 /* VEX_W_0FC2_P_0 */
10990 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
10993 /* VEX_W_0FC2_P_1 */
10994 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
10997 /* VEX_W_0FC2_P_2 */
10998 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
11001 /* VEX_W_0FC2_P_3 */
11002 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
11005 /* VEX_W_0FC4_P_2 */
11006 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
11009 /* VEX_W_0FC5_P_2 */
11010 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
11013 /* VEX_W_0FD0_P_2 */
11014 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
11017 /* VEX_W_0FD0_P_3 */
11018 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
11021 /* VEX_W_0FD1_P_2 */
11022 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
11025 /* VEX_W_0FD2_P_2 */
11026 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
11029 /* VEX_W_0FD3_P_2 */
11030 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
11033 /* VEX_W_0FD4_P_2 */
11034 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
11037 /* VEX_W_0FD5_P_2 */
11038 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
11041 /* VEX_W_0FD6_P_2 */
11042 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
11045 /* VEX_W_0FD7_P_2_M_1 */
11046 { "vpmovmskb", { Gdq
, XS
}, 0 },
11049 /* VEX_W_0FD8_P_2 */
11050 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
11053 /* VEX_W_0FD9_P_2 */
11054 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
11057 /* VEX_W_0FDA_P_2 */
11058 { "vpminub", { XM
, Vex
, EXx
}, 0 },
11061 /* VEX_W_0FDB_P_2 */
11062 { "vpand", { XM
, Vex
, EXx
}, 0 },
11065 /* VEX_W_0FDC_P_2 */
11066 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
11069 /* VEX_W_0FDD_P_2 */
11070 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
11073 /* VEX_W_0FDE_P_2 */
11074 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
11077 /* VEX_W_0FDF_P_2 */
11078 { "vpandn", { XM
, Vex
, EXx
}, 0 },
11081 /* VEX_W_0FE0_P_2 */
11082 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
11085 /* VEX_W_0FE1_P_2 */
11086 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
11089 /* VEX_W_0FE2_P_2 */
11090 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
11093 /* VEX_W_0FE3_P_2 */
11094 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
11097 /* VEX_W_0FE4_P_2 */
11098 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
11101 /* VEX_W_0FE5_P_2 */
11102 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
11105 /* VEX_W_0FE6_P_1 */
11106 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
11109 /* VEX_W_0FE6_P_2 */
11110 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
11113 /* VEX_W_0FE6_P_3 */
11114 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
11117 /* VEX_W_0FE7_P_2_M_0 */
11118 { "vmovntdq", { Mx
, XM
}, 0 },
11121 /* VEX_W_0FE8_P_2 */
11122 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
11125 /* VEX_W_0FE9_P_2 */
11126 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
11129 /* VEX_W_0FEA_P_2 */
11130 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
11133 /* VEX_W_0FEB_P_2 */
11134 { "vpor", { XM
, Vex
, EXx
}, 0 },
11137 /* VEX_W_0FEC_P_2 */
11138 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
11141 /* VEX_W_0FED_P_2 */
11142 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
11145 /* VEX_W_0FEE_P_2 */
11146 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
11149 /* VEX_W_0FEF_P_2 */
11150 { "vpxor", { XM
, Vex
, EXx
}, 0 },
11153 /* VEX_W_0FF0_P_3_M_0 */
11154 { "vlddqu", { XM
, M
}, 0 },
11157 /* VEX_W_0FF1_P_2 */
11158 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
11161 /* VEX_W_0FF2_P_2 */
11162 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
11165 /* VEX_W_0FF3_P_2 */
11166 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
11169 /* VEX_W_0FF4_P_2 */
11170 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
11173 /* VEX_W_0FF5_P_2 */
11174 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
11177 /* VEX_W_0FF6_P_2 */
11178 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
11181 /* VEX_W_0FF7_P_2 */
11182 { "vmaskmovdqu", { XM
, XS
}, 0 },
11185 /* VEX_W_0FF8_P_2 */
11186 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
11189 /* VEX_W_0FF9_P_2 */
11190 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
11193 /* VEX_W_0FFA_P_2 */
11194 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
11197 /* VEX_W_0FFB_P_2 */
11198 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
11201 /* VEX_W_0FFC_P_2 */
11202 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
11205 /* VEX_W_0FFD_P_2 */
11206 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
11209 /* VEX_W_0FFE_P_2 */
11210 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
11213 /* VEX_W_0F3800_P_2 */
11214 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
11217 /* VEX_W_0F3801_P_2 */
11218 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
11221 /* VEX_W_0F3802_P_2 */
11222 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
11225 /* VEX_W_0F3803_P_2 */
11226 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
11229 /* VEX_W_0F3804_P_2 */
11230 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
11233 /* VEX_W_0F3805_P_2 */
11234 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
11237 /* VEX_W_0F3806_P_2 */
11238 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
11241 /* VEX_W_0F3807_P_2 */
11242 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
11245 /* VEX_W_0F3808_P_2 */
11246 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
11249 /* VEX_W_0F3809_P_2 */
11250 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
11253 /* VEX_W_0F380A_P_2 */
11254 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
11257 /* VEX_W_0F380B_P_2 */
11258 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
11261 /* VEX_W_0F380C_P_2 */
11262 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
11265 /* VEX_W_0F380D_P_2 */
11266 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
11269 /* VEX_W_0F380E_P_2 */
11270 { "vtestps", { XM
, EXx
}, 0 },
11273 /* VEX_W_0F380F_P_2 */
11274 { "vtestpd", { XM
, EXx
}, 0 },
11277 /* VEX_W_0F3816_P_2 */
11278 { "vpermps", { XM
, Vex
, EXx
}, 0 },
11281 /* VEX_W_0F3817_P_2 */
11282 { "vptest", { XM
, EXx
}, 0 },
11285 /* VEX_W_0F3818_P_2 */
11286 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
11289 /* VEX_W_0F3819_P_2 */
11290 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
11293 /* VEX_W_0F381A_P_2_M_0 */
11294 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
11297 /* VEX_W_0F381C_P_2 */
11298 { "vpabsb", { XM
, EXx
}, 0 },
11301 /* VEX_W_0F381D_P_2 */
11302 { "vpabsw", { XM
, EXx
}, 0 },
11305 /* VEX_W_0F381E_P_2 */
11306 { "vpabsd", { XM
, EXx
}, 0 },
11309 /* VEX_W_0F3820_P_2 */
11310 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
11313 /* VEX_W_0F3821_P_2 */
11314 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
11317 /* VEX_W_0F3822_P_2 */
11318 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
11321 /* VEX_W_0F3823_P_2 */
11322 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
11325 /* VEX_W_0F3824_P_2 */
11326 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
11329 /* VEX_W_0F3825_P_2 */
11330 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
11333 /* VEX_W_0F3828_P_2 */
11334 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
11337 /* VEX_W_0F3829_P_2 */
11338 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
11341 /* VEX_W_0F382A_P_2_M_0 */
11342 { "vmovntdqa", { XM
, Mx
}, 0 },
11345 /* VEX_W_0F382B_P_2 */
11346 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
11349 /* VEX_W_0F382C_P_2_M_0 */
11350 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
11353 /* VEX_W_0F382D_P_2_M_0 */
11354 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
11357 /* VEX_W_0F382E_P_2_M_0 */
11358 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
11361 /* VEX_W_0F382F_P_2_M_0 */
11362 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
11365 /* VEX_W_0F3830_P_2 */
11366 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
11369 /* VEX_W_0F3831_P_2 */
11370 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
11373 /* VEX_W_0F3832_P_2 */
11374 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
11377 /* VEX_W_0F3833_P_2 */
11378 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
11381 /* VEX_W_0F3834_P_2 */
11382 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
11385 /* VEX_W_0F3835_P_2 */
11386 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
11389 /* VEX_W_0F3836_P_2 */
11390 { "vpermd", { XM
, Vex
, EXx
}, 0 },
11393 /* VEX_W_0F3837_P_2 */
11394 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
11397 /* VEX_W_0F3838_P_2 */
11398 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
11401 /* VEX_W_0F3839_P_2 */
11402 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
11405 /* VEX_W_0F383A_P_2 */
11406 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
11409 /* VEX_W_0F383B_P_2 */
11410 { "vpminud", { XM
, Vex
, EXx
}, 0 },
11413 /* VEX_W_0F383C_P_2 */
11414 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
11417 /* VEX_W_0F383D_P_2 */
11418 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
11421 /* VEX_W_0F383E_P_2 */
11422 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
11425 /* VEX_W_0F383F_P_2 */
11426 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
11429 /* VEX_W_0F3840_P_2 */
11430 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
11433 /* VEX_W_0F3841_P_2 */
11434 { "vphminposuw", { XM
, EXx
}, 0 },
11437 /* VEX_W_0F3846_P_2 */
11438 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
11441 /* VEX_W_0F3858_P_2 */
11442 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
11445 /* VEX_W_0F3859_P_2 */
11446 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
11449 /* VEX_W_0F385A_P_2_M_0 */
11450 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
11453 /* VEX_W_0F3878_P_2 */
11454 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
11457 /* VEX_W_0F3879_P_2 */
11458 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
11461 /* VEX_W_0F38DB_P_2 */
11462 { "vaesimc", { XM
, EXx
}, 0 },
11465 /* VEX_W_0F38DC_P_2 */
11466 { "vaesenc", { XM
, Vex128
, EXx
}, 0 },
11469 /* VEX_W_0F38DD_P_2 */
11470 { "vaesenclast", { XM
, Vex128
, EXx
}, 0 },
11473 /* VEX_W_0F38DE_P_2 */
11474 { "vaesdec", { XM
, Vex128
, EXx
}, 0 },
11477 /* VEX_W_0F38DF_P_2 */
11478 { "vaesdeclast", { XM
, Vex128
, EXx
}, 0 },
11481 /* VEX_W_0F3A00_P_2 */
11483 { "vpermq", { XM
, EXx
, Ib
}, 0 },
11486 /* VEX_W_0F3A01_P_2 */
11488 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
11491 /* VEX_W_0F3A02_P_2 */
11492 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
11495 /* VEX_W_0F3A04_P_2 */
11496 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
11499 /* VEX_W_0F3A05_P_2 */
11500 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
11503 /* VEX_W_0F3A06_P_2 */
11504 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11507 /* VEX_W_0F3A08_P_2 */
11508 { "vroundps", { XM
, EXx
, Ib
}, 0 },
11511 /* VEX_W_0F3A09_P_2 */
11512 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
11515 /* VEX_W_0F3A0A_P_2 */
11516 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
11519 /* VEX_W_0F3A0B_P_2 */
11520 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
11523 /* VEX_W_0F3A0C_P_2 */
11524 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
11527 /* VEX_W_0F3A0D_P_2 */
11528 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
11531 /* VEX_W_0F3A0E_P_2 */
11532 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
11535 /* VEX_W_0F3A0F_P_2 */
11536 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
11539 /* VEX_W_0F3A14_P_2 */
11540 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
11543 /* VEX_W_0F3A15_P_2 */
11544 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
11547 /* VEX_W_0F3A18_P_2 */
11548 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11551 /* VEX_W_0F3A19_P_2 */
11552 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
11555 /* VEX_W_0F3A20_P_2 */
11556 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
11559 /* VEX_W_0F3A21_P_2 */
11560 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
11563 /* VEX_W_0F3A30_P_2_LEN_0 */
11564 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
11565 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
11568 /* VEX_W_0F3A31_P_2_LEN_0 */
11569 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
11570 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
11573 /* VEX_W_0F3A32_P_2_LEN_0 */
11574 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
11575 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
11578 /* VEX_W_0F3A33_P_2_LEN_0 */
11579 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
11580 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
11583 /* VEX_W_0F3A38_P_2 */
11584 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11587 /* VEX_W_0F3A39_P_2 */
11588 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
11591 /* VEX_W_0F3A40_P_2 */
11592 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
11595 /* VEX_W_0F3A41_P_2 */
11596 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
11599 /* VEX_W_0F3A42_P_2 */
11600 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
11603 /* VEX_W_0F3A44_P_2 */
11604 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
}, 0 },
11607 /* VEX_W_0F3A46_P_2 */
11608 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11611 /* VEX_W_0F3A48_P_2 */
11612 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11613 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11616 /* VEX_W_0F3A49_P_2 */
11617 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11618 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11621 /* VEX_W_0F3A4A_P_2 */
11622 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11625 /* VEX_W_0F3A4B_P_2 */
11626 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11629 /* VEX_W_0F3A4C_P_2 */
11630 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11633 /* VEX_W_0F3A60_P_2 */
11634 { "vpcmpestrm", { XM
, EXx
, Ib
}, 0 },
11637 /* VEX_W_0F3A61_P_2 */
11638 { "vpcmpestri", { XM
, EXx
, Ib
}, 0 },
11641 /* VEX_W_0F3A62_P_2 */
11642 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
11645 /* VEX_W_0F3A63_P_2 */
11646 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
11649 /* VEX_W_0F3ADF_P_2 */
11650 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
11652 #define NEED_VEX_W_TABLE
11653 #include "i386-dis-evex.h"
11654 #undef NEED_VEX_W_TABLE
11657 static const struct dis386 mod_table
[][2] = {
11660 { "leaS", { Gv
, M
}, 0 },
11665 { RM_TABLE (RM_C6_REG_7
) },
11670 { RM_TABLE (RM_C7_REG_7
) },
11674 { "Jcall^", { indirEp
}, 0 },
11678 { "Jjmp^", { indirEp
}, 0 },
11681 /* MOD_0F01_REG_0 */
11682 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11683 { RM_TABLE (RM_0F01_REG_0
) },
11686 /* MOD_0F01_REG_1 */
11687 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11688 { RM_TABLE (RM_0F01_REG_1
) },
11691 /* MOD_0F01_REG_2 */
11692 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11693 { RM_TABLE (RM_0F01_REG_2
) },
11696 /* MOD_0F01_REG_3 */
11697 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11698 { RM_TABLE (RM_0F01_REG_3
) },
11701 /* MOD_0F01_REG_5 */
11703 { RM_TABLE (RM_0F01_REG_5
) },
11706 /* MOD_0F01_REG_7 */
11707 { "invlpg", { Mb
}, 0 },
11708 { RM_TABLE (RM_0F01_REG_7
) },
11711 /* MOD_0F12_PREFIX_0 */
11712 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
11713 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
11717 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
11720 /* MOD_0F16_PREFIX_0 */
11721 { "movhps", { XM
, EXq
}, 0 },
11722 { "movlhps", { XM
, EXq
}, 0 },
11726 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
11729 /* MOD_0F18_REG_0 */
11730 { "prefetchnta", { Mb
}, 0 },
11733 /* MOD_0F18_REG_1 */
11734 { "prefetcht0", { Mb
}, 0 },
11737 /* MOD_0F18_REG_2 */
11738 { "prefetcht1", { Mb
}, 0 },
11741 /* MOD_0F18_REG_3 */
11742 { "prefetcht2", { Mb
}, 0 },
11745 /* MOD_0F18_REG_4 */
11746 { "nop/reserved", { Mb
}, 0 },
11749 /* MOD_0F18_REG_5 */
11750 { "nop/reserved", { Mb
}, 0 },
11753 /* MOD_0F18_REG_6 */
11754 { "nop/reserved", { Mb
}, 0 },
11757 /* MOD_0F18_REG_7 */
11758 { "nop/reserved", { Mb
}, 0 },
11761 /* MOD_0F1A_PREFIX_0 */
11762 { "bndldx", { Gbnd
, Ev_bnd
}, 0 },
11763 { "nopQ", { Ev
}, 0 },
11766 /* MOD_0F1B_PREFIX_0 */
11767 { "bndstx", { Ev_bnd
, Gbnd
}, 0 },
11768 { "nopQ", { Ev
}, 0 },
11771 /* MOD_0F1B_PREFIX_1 */
11772 { "bndmk", { Gbnd
, Ev_bnd
}, 0 },
11773 { "nopQ", { Ev
}, 0 },
11778 { "movL", { Rd
, Td
}, 0 },
11783 { "movL", { Td
, Rd
}, 0 },
11786 /* MOD_0F2B_PREFIX_0 */
11787 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
11790 /* MOD_0F2B_PREFIX_1 */
11791 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
11794 /* MOD_0F2B_PREFIX_2 */
11795 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
11798 /* MOD_0F2B_PREFIX_3 */
11799 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
11804 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
11807 /* MOD_0F71_REG_2 */
11809 { "psrlw", { MS
, Ib
}, 0 },
11812 /* MOD_0F71_REG_4 */
11814 { "psraw", { MS
, Ib
}, 0 },
11817 /* MOD_0F71_REG_6 */
11819 { "psllw", { MS
, Ib
}, 0 },
11822 /* MOD_0F72_REG_2 */
11824 { "psrld", { MS
, Ib
}, 0 },
11827 /* MOD_0F72_REG_4 */
11829 { "psrad", { MS
, Ib
}, 0 },
11832 /* MOD_0F72_REG_6 */
11834 { "pslld", { MS
, Ib
}, 0 },
11837 /* MOD_0F73_REG_2 */
11839 { "psrlq", { MS
, Ib
}, 0 },
11842 /* MOD_0F73_REG_3 */
11844 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11847 /* MOD_0F73_REG_6 */
11849 { "psllq", { MS
, Ib
}, 0 },
11852 /* MOD_0F73_REG_7 */
11854 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11857 /* MOD_0FAE_REG_0 */
11858 { "fxsave", { FXSAVE
}, 0 },
11859 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11862 /* MOD_0FAE_REG_1 */
11863 { "fxrstor", { FXSAVE
}, 0 },
11864 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11867 /* MOD_0FAE_REG_2 */
11868 { "ldmxcsr", { Md
}, 0 },
11869 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11872 /* MOD_0FAE_REG_3 */
11873 { "stmxcsr", { Md
}, 0 },
11874 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11877 /* MOD_0FAE_REG_4 */
11878 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4
) },
11879 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4
) },
11882 /* MOD_0FAE_REG_5 */
11883 { "xrstor", { FXSAVE
}, 0 },
11884 { RM_TABLE (RM_0FAE_REG_5
) },
11887 /* MOD_0FAE_REG_6 */
11888 { PREFIX_TABLE (PREFIX_0FAE_REG_6
) },
11889 { RM_TABLE (RM_0FAE_REG_6
) },
11892 /* MOD_0FAE_REG_7 */
11893 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11894 { RM_TABLE (RM_0FAE_REG_7
) },
11898 { "lssS", { Gv
, Mp
}, 0 },
11902 { "lfsS", { Gv
, Mp
}, 0 },
11906 { "lgsS", { Gv
, Mp
}, 0 },
11910 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
11913 /* MOD_0FC7_REG_3 */
11914 { "xrstors", { FXSAVE
}, 0 },
11917 /* MOD_0FC7_REG_4 */
11918 { "xsavec", { FXSAVE
}, 0 },
11921 /* MOD_0FC7_REG_5 */
11922 { "xsaves", { FXSAVE
}, 0 },
11925 /* MOD_0FC7_REG_6 */
11926 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
11927 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
11930 /* MOD_0FC7_REG_7 */
11931 { "vmptrst", { Mq
}, 0 },
11932 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
11937 { "pmovmskb", { Gdq
, MS
}, 0 },
11940 /* MOD_0FE7_PREFIX_2 */
11941 { "movntdq", { Mx
, XM
}, 0 },
11944 /* MOD_0FF0_PREFIX_3 */
11945 { "lddqu", { XM
, M
}, 0 },
11948 /* MOD_0F382A_PREFIX_2 */
11949 { "movntdqa", { XM
, Mx
}, 0 },
11953 { "bound{S|}", { Gv
, Ma
}, 0 },
11954 { EVEX_TABLE (EVEX_0F
) },
11958 { "lesS", { Gv
, Mp
}, 0 },
11959 { VEX_C4_TABLE (VEX_0F
) },
11963 { "ldsS", { Gv
, Mp
}, 0 },
11964 { VEX_C5_TABLE (VEX_0F
) },
11967 /* MOD_VEX_0F12_PREFIX_0 */
11968 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11969 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11973 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11976 /* MOD_VEX_0F16_PREFIX_0 */
11977 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11978 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11982 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11986 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11989 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11991 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
11994 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11996 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
11999 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
12001 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
12004 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
12006 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
12009 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
12011 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
12014 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
12016 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
12019 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
12021 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
12024 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
12026 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
12029 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
12031 { "knotw", { MaskG
, MaskR
}, 0 },
12034 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
12036 { "knotq", { MaskG
, MaskR
}, 0 },
12039 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
12041 { "knotb", { MaskG
, MaskR
}, 0 },
12044 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
12046 { "knotd", { MaskG
, MaskR
}, 0 },
12049 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
12051 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
12054 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
12056 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
12059 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
12061 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
12064 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
12066 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
12069 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
12071 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
12074 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
12076 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
12079 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
12081 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
12084 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
12086 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
12089 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12091 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
12094 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12096 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
12099 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12101 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
12104 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12106 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
12109 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12111 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
12114 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12116 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
12119 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12121 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
12124 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12126 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
12129 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12131 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
12134 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12136 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
12139 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12141 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
12146 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
12149 /* MOD_VEX_0F71_REG_2 */
12151 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
12154 /* MOD_VEX_0F71_REG_4 */
12156 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
12159 /* MOD_VEX_0F71_REG_6 */
12161 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
12164 /* MOD_VEX_0F72_REG_2 */
12166 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
12169 /* MOD_VEX_0F72_REG_4 */
12171 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
12174 /* MOD_VEX_0F72_REG_6 */
12176 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
12179 /* MOD_VEX_0F73_REG_2 */
12181 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
12184 /* MOD_VEX_0F73_REG_3 */
12186 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
12189 /* MOD_VEX_0F73_REG_6 */
12191 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
12194 /* MOD_VEX_0F73_REG_7 */
12196 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
12199 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12200 { "kmovw", { Ew
, MaskG
}, 0 },
12204 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12205 { "kmovq", { Eq
, MaskG
}, 0 },
12209 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12210 { "kmovb", { Eb
, MaskG
}, 0 },
12214 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12215 { "kmovd", { Ed
, MaskG
}, 0 },
12219 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12221 { "kmovw", { MaskG
, Rdq
}, 0 },
12224 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12226 { "kmovb", { MaskG
, Rdq
}, 0 },
12229 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12231 { "kmovd", { MaskG
, Rdq
}, 0 },
12234 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12236 { "kmovq", { MaskG
, Rdq
}, 0 },
12239 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12241 { "kmovw", { Gdq
, MaskR
}, 0 },
12244 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12246 { "kmovb", { Gdq
, MaskR
}, 0 },
12249 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12251 { "kmovd", { Gdq
, MaskR
}, 0 },
12254 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12256 { "kmovq", { Gdq
, MaskR
}, 0 },
12259 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12261 { "kortestw", { MaskG
, MaskR
}, 0 },
12264 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12266 { "kortestq", { MaskG
, MaskR
}, 0 },
12269 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12271 { "kortestb", { MaskG
, MaskR
}, 0 },
12274 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12276 { "kortestd", { MaskG
, MaskR
}, 0 },
12279 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12281 { "ktestw", { MaskG
, MaskR
}, 0 },
12284 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12286 { "ktestq", { MaskG
, MaskR
}, 0 },
12289 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12291 { "ktestb", { MaskG
, MaskR
}, 0 },
12294 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12296 { "ktestd", { MaskG
, MaskR
}, 0 },
12299 /* MOD_VEX_0FAE_REG_2 */
12300 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
12303 /* MOD_VEX_0FAE_REG_3 */
12304 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
12307 /* MOD_VEX_0FD7_PREFIX_2 */
12309 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
12312 /* MOD_VEX_0FE7_PREFIX_2 */
12313 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
12316 /* MOD_VEX_0FF0_PREFIX_3 */
12317 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
12320 /* MOD_VEX_0F381A_PREFIX_2 */
12321 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
12324 /* MOD_VEX_0F382A_PREFIX_2 */
12325 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
12328 /* MOD_VEX_0F382C_PREFIX_2 */
12329 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
12332 /* MOD_VEX_0F382D_PREFIX_2 */
12333 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
12336 /* MOD_VEX_0F382E_PREFIX_2 */
12337 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
12340 /* MOD_VEX_0F382F_PREFIX_2 */
12341 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
12344 /* MOD_VEX_0F385A_PREFIX_2 */
12345 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
12348 /* MOD_VEX_0F388C_PREFIX_2 */
12349 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
12352 /* MOD_VEX_0F388E_PREFIX_2 */
12353 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
12356 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12358 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
12361 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12363 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
12366 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12368 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
12371 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12373 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
12376 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12378 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
12381 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12383 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
12386 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12388 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
12391 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12393 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
12395 #define NEED_MOD_TABLE
12396 #include "i386-dis-evex.h"
12397 #undef NEED_MOD_TABLE
12400 static const struct dis386 rm_table
[][8] = {
12403 { "xabort", { Skip_MODRM
, Ib
}, 0 },
12407 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
12410 /* RM_0F01_REG_0 */
12412 { "vmcall", { Skip_MODRM
}, 0 },
12413 { "vmlaunch", { Skip_MODRM
}, 0 },
12414 { "vmresume", { Skip_MODRM
}, 0 },
12415 { "vmxoff", { Skip_MODRM
}, 0 },
12418 /* RM_0F01_REG_1 */
12419 { "monitor", { { OP_Monitor
, 0 } }, 0 },
12420 { "mwait", { { OP_Mwait
, 0 } }, 0 },
12421 { "clac", { Skip_MODRM
}, 0 },
12422 { "stac", { Skip_MODRM
}, 0 },
12426 { "encls", { Skip_MODRM
}, 0 },
12429 /* RM_0F01_REG_2 */
12430 { "xgetbv", { Skip_MODRM
}, 0 },
12431 { "xsetbv", { Skip_MODRM
}, 0 },
12434 { "vmfunc", { Skip_MODRM
}, 0 },
12435 { "xend", { Skip_MODRM
}, 0 },
12436 { "xtest", { Skip_MODRM
}, 0 },
12437 { "enclu", { Skip_MODRM
}, 0 },
12440 /* RM_0F01_REG_3 */
12441 { "vmrun", { Skip_MODRM
}, 0 },
12442 { "vmmcall", { Skip_MODRM
}, 0 },
12443 { "vmload", { Skip_MODRM
}, 0 },
12444 { "vmsave", { Skip_MODRM
}, 0 },
12445 { "stgi", { Skip_MODRM
}, 0 },
12446 { "clgi", { Skip_MODRM
}, 0 },
12447 { "skinit", { Skip_MODRM
}, 0 },
12448 { "invlpga", { Skip_MODRM
}, 0 },
12451 /* RM_0F01_REG_5 */
12458 { "rdpkru", { Skip_MODRM
}, 0 },
12459 { "wrpkru", { Skip_MODRM
}, 0 },
12462 /* RM_0F01_REG_7 */
12463 { "swapgs", { Skip_MODRM
}, 0 },
12464 { "rdtscp", { Skip_MODRM
}, 0 },
12465 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
12466 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
12467 { "clzero", { Skip_MODRM
}, 0 },
12470 /* RM_0FAE_REG_5 */
12471 { "lfence", { Skip_MODRM
}, 0 },
12474 /* RM_0FAE_REG_6 */
12475 { "mfence", { Skip_MODRM
}, 0 },
12478 /* RM_0FAE_REG_7 */
12479 { "sfence", { Skip_MODRM
}, 0 },
12484 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12486 /* We use the high bit to indicate different name for the same
12488 #define REP_PREFIX (0xf3 | 0x100)
12489 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12490 #define XRELEASE_PREFIX (0xf3 | 0x400)
12491 #define BND_PREFIX (0xf2 | 0x400)
12496 int newrex
, i
, length
;
12502 last_lock_prefix
= -1;
12503 last_repz_prefix
= -1;
12504 last_repnz_prefix
= -1;
12505 last_data_prefix
= -1;
12506 last_addr_prefix
= -1;
12507 last_rex_prefix
= -1;
12508 last_seg_prefix
= -1;
12510 active_seg_prefix
= 0;
12511 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12512 all_prefixes
[i
] = 0;
12515 /* The maximum instruction length is 15bytes. */
12516 while (length
< MAX_CODE_LENGTH
- 1)
12518 FETCH_DATA (the_info
, codep
+ 1);
12522 /* REX prefixes family. */
12539 if (address_mode
== mode_64bit
)
12543 last_rex_prefix
= i
;
12546 prefixes
|= PREFIX_REPZ
;
12547 last_repz_prefix
= i
;
12550 prefixes
|= PREFIX_REPNZ
;
12551 last_repnz_prefix
= i
;
12554 prefixes
|= PREFIX_LOCK
;
12555 last_lock_prefix
= i
;
12558 prefixes
|= PREFIX_CS
;
12559 last_seg_prefix
= i
;
12560 active_seg_prefix
= PREFIX_CS
;
12563 prefixes
|= PREFIX_SS
;
12564 last_seg_prefix
= i
;
12565 active_seg_prefix
= PREFIX_SS
;
12568 prefixes
|= PREFIX_DS
;
12569 last_seg_prefix
= i
;
12570 active_seg_prefix
= PREFIX_DS
;
12573 prefixes
|= PREFIX_ES
;
12574 last_seg_prefix
= i
;
12575 active_seg_prefix
= PREFIX_ES
;
12578 prefixes
|= PREFIX_FS
;
12579 last_seg_prefix
= i
;
12580 active_seg_prefix
= PREFIX_FS
;
12583 prefixes
|= PREFIX_GS
;
12584 last_seg_prefix
= i
;
12585 active_seg_prefix
= PREFIX_GS
;
12588 prefixes
|= PREFIX_DATA
;
12589 last_data_prefix
= i
;
12592 prefixes
|= PREFIX_ADDR
;
12593 last_addr_prefix
= i
;
12596 /* fwait is really an instruction. If there are prefixes
12597 before the fwait, they belong to the fwait, *not* to the
12598 following instruction. */
12600 if (prefixes
|| rex
)
12602 prefixes
|= PREFIX_FWAIT
;
12604 /* This ensures that the previous REX prefixes are noticed
12605 as unused prefixes, as in the return case below. */
12609 prefixes
= PREFIX_FWAIT
;
12614 /* Rex is ignored when followed by another prefix. */
12620 if (*codep
!= FWAIT_OPCODE
)
12621 all_prefixes
[i
++] = *codep
;
12629 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12632 static const char *
12633 prefix_name (int pref
, int sizeflag
)
12635 static const char *rexes
[16] =
12638 "rex.B", /* 0x41 */
12639 "rex.X", /* 0x42 */
12640 "rex.XB", /* 0x43 */
12641 "rex.R", /* 0x44 */
12642 "rex.RB", /* 0x45 */
12643 "rex.RX", /* 0x46 */
12644 "rex.RXB", /* 0x47 */
12645 "rex.W", /* 0x48 */
12646 "rex.WB", /* 0x49 */
12647 "rex.WX", /* 0x4a */
12648 "rex.WXB", /* 0x4b */
12649 "rex.WR", /* 0x4c */
12650 "rex.WRB", /* 0x4d */
12651 "rex.WRX", /* 0x4e */
12652 "rex.WRXB", /* 0x4f */
12657 /* REX prefixes family. */
12674 return rexes
[pref
- 0x40];
12694 return (sizeflag
& DFLAG
) ? "data16" : "data32";
12696 if (address_mode
== mode_64bit
)
12697 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
12699 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
12704 case XACQUIRE_PREFIX
:
12706 case XRELEASE_PREFIX
:
12715 static char op_out
[MAX_OPERANDS
][100];
12716 static int op_ad
, op_index
[MAX_OPERANDS
];
12717 static int two_source_ops
;
12718 static bfd_vma op_address
[MAX_OPERANDS
];
12719 static bfd_vma op_riprel
[MAX_OPERANDS
];
12720 static bfd_vma start_pc
;
12723 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12724 * (see topic "Redundant prefixes" in the "Differences from 8086"
12725 * section of the "Virtual 8086 Mode" chapter.)
12726 * 'pc' should be the address of this instruction, it will
12727 * be used to print the target address if this is a relative jump or call
12728 * The function returns the length of this instruction in bytes.
12731 static char intel_syntax
;
12732 static char intel_mnemonic
= !SYSV386_COMPAT
;
12733 static char open_char
;
12734 static char close_char
;
12735 static char separator_char
;
12736 static char scale_char
;
12744 static enum x86_64_isa isa64
;
12746 /* Here for backwards compatibility. When gdb stops using
12747 print_insn_i386_att and print_insn_i386_intel these functions can
12748 disappear, and print_insn_i386 be merged into print_insn. */
12750 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
12754 return print_insn (pc
, info
);
12758 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
12762 return print_insn (pc
, info
);
12766 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
12770 return print_insn (pc
, info
);
12774 print_i386_disassembler_options (FILE *stream
)
12776 fprintf (stream
, _("\n\
12777 The following i386/x86-64 specific disassembler options are supported for use\n\
12778 with the -M switch (multiple options should be separated by commas):\n"));
12780 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
12781 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
12782 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
12783 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
12784 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
12785 fprintf (stream
, _(" att-mnemonic\n"
12786 " Display instruction in AT&T mnemonic\n"));
12787 fprintf (stream
, _(" intel-mnemonic\n"
12788 " Display instruction in Intel mnemonic\n"));
12789 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
12790 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
12791 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
12792 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
12793 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
12794 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12795 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
12796 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
12800 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
12802 /* Get a pointer to struct dis386 with a valid name. */
12804 static const struct dis386
*
12805 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
12807 int vindex
, vex_table_index
;
12809 if (dp
->name
!= NULL
)
12812 switch (dp
->op
[0].bytemode
)
12814 case USE_REG_TABLE
:
12815 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
12818 case USE_MOD_TABLE
:
12819 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
12820 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
12824 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
12827 case USE_PREFIX_TABLE
:
12830 /* The prefix in VEX is implicit. */
12831 switch (vex
.prefix
)
12836 case REPE_PREFIX_OPCODE
:
12839 case DATA_PREFIX_OPCODE
:
12842 case REPNE_PREFIX_OPCODE
:
12852 int last_prefix
= -1;
12855 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12856 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12858 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12860 if (last_repz_prefix
> last_repnz_prefix
)
12863 prefix
= PREFIX_REPZ
;
12864 last_prefix
= last_repz_prefix
;
12869 prefix
= PREFIX_REPNZ
;
12870 last_prefix
= last_repnz_prefix
;
12873 /* Check if prefix should be ignored. */
12874 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
12875 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
12880 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12883 prefix
= PREFIX_DATA
;
12884 last_prefix
= last_data_prefix
;
12889 used_prefixes
|= prefix
;
12890 all_prefixes
[last_prefix
] = 0;
12893 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12896 case USE_X86_64_TABLE
:
12897 vindex
= address_mode
== mode_64bit
? 1 : 0;
12898 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12901 case USE_3BYTE_TABLE
:
12902 FETCH_DATA (info
, codep
+ 2);
12904 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12906 modrm
.mod
= (*codep
>> 6) & 3;
12907 modrm
.reg
= (*codep
>> 3) & 7;
12908 modrm
.rm
= *codep
& 7;
12911 case USE_VEX_LEN_TABLE
:
12915 switch (vex
.length
)
12928 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12931 case USE_XOP_8F_TABLE
:
12932 FETCH_DATA (info
, codep
+ 3);
12933 /* All bits in the REX prefix are ignored. */
12935 rex
= ~(*codep
>> 5) & 0x7;
12937 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12938 switch ((*codep
& 0x1f))
12944 vex_table_index
= XOP_08
;
12947 vex_table_index
= XOP_09
;
12950 vex_table_index
= XOP_0A
;
12954 vex
.w
= *codep
& 0x80;
12955 if (vex
.w
&& address_mode
== mode_64bit
)
12958 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12959 if (address_mode
!= mode_64bit
12960 && vex
.register_specifier
> 0x7)
12966 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12967 switch ((*codep
& 0x3))
12973 vex
.prefix
= DATA_PREFIX_OPCODE
;
12976 vex
.prefix
= REPE_PREFIX_OPCODE
;
12979 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12986 dp
= &xop_table
[vex_table_index
][vindex
];
12989 FETCH_DATA (info
, codep
+ 1);
12990 modrm
.mod
= (*codep
>> 6) & 3;
12991 modrm
.reg
= (*codep
>> 3) & 7;
12992 modrm
.rm
= *codep
& 7;
12995 case USE_VEX_C4_TABLE
:
12997 FETCH_DATA (info
, codep
+ 3);
12998 /* All bits in the REX prefix are ignored. */
13000 rex
= ~(*codep
>> 5) & 0x7;
13001 switch ((*codep
& 0x1f))
13007 vex_table_index
= VEX_0F
;
13010 vex_table_index
= VEX_0F38
;
13013 vex_table_index
= VEX_0F3A
;
13017 vex
.w
= *codep
& 0x80;
13018 if (address_mode
== mode_64bit
)
13022 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
13026 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
13027 is ignored, other REX bits are 0 and the highest bit in
13028 VEX.vvvv is also ignored. */
13030 vex
.register_specifier
= (~(*codep
>> 3)) & 0x7;
13032 vex
.length
= (*codep
& 0x4) ? 256 : 128;
13033 switch ((*codep
& 0x3))
13039 vex
.prefix
= DATA_PREFIX_OPCODE
;
13042 vex
.prefix
= REPE_PREFIX_OPCODE
;
13045 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13052 dp
= &vex_table
[vex_table_index
][vindex
];
13054 /* There is no MODRM byte for VEX [82|77]. */
13055 if (vindex
!= 0x77 && vindex
!= 0x82)
13057 FETCH_DATA (info
, codep
+ 1);
13058 modrm
.mod
= (*codep
>> 6) & 3;
13059 modrm
.reg
= (*codep
>> 3) & 7;
13060 modrm
.rm
= *codep
& 7;
13064 case USE_VEX_C5_TABLE
:
13066 FETCH_DATA (info
, codep
+ 2);
13067 /* All bits in the REX prefix are ignored. */
13069 rex
= (*codep
& 0x80) ? 0 : REX_R
;
13071 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
13073 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
13075 vex
.length
= (*codep
& 0x4) ? 256 : 128;
13076 switch ((*codep
& 0x3))
13082 vex
.prefix
= DATA_PREFIX_OPCODE
;
13085 vex
.prefix
= REPE_PREFIX_OPCODE
;
13088 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13095 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
13097 /* There is no MODRM byte for VEX [82|77]. */
13098 if (vindex
!= 0x77 && vindex
!= 0x82)
13100 FETCH_DATA (info
, codep
+ 1);
13101 modrm
.mod
= (*codep
>> 6) & 3;
13102 modrm
.reg
= (*codep
>> 3) & 7;
13103 modrm
.rm
= *codep
& 7;
13107 case USE_VEX_W_TABLE
:
13111 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
13114 case USE_EVEX_TABLE
:
13115 two_source_ops
= 0;
13118 FETCH_DATA (info
, codep
+ 4);
13119 /* All bits in the REX prefix are ignored. */
13121 /* The first byte after 0x62. */
13122 rex
= ~(*codep
>> 5) & 0x7;
13123 vex
.r
= *codep
& 0x10;
13124 switch ((*codep
& 0xf))
13127 return &bad_opcode
;
13129 vex_table_index
= EVEX_0F
;
13132 vex_table_index
= EVEX_0F38
;
13135 vex_table_index
= EVEX_0F3A
;
13139 /* The second byte after 0x62. */
13141 vex
.w
= *codep
& 0x80;
13142 if (vex
.w
&& address_mode
== mode_64bit
)
13145 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
13146 if (address_mode
!= mode_64bit
)
13148 /* In 16/32-bit mode silently ignore following bits. */
13152 vex
.register_specifier
&= 0x7;
13156 if (!(*codep
& 0x4))
13157 return &bad_opcode
;
13159 switch ((*codep
& 0x3))
13165 vex
.prefix
= DATA_PREFIX_OPCODE
;
13168 vex
.prefix
= REPE_PREFIX_OPCODE
;
13171 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13175 /* The third byte after 0x62. */
13178 /* Remember the static rounding bits. */
13179 vex
.ll
= (*codep
>> 5) & 3;
13180 vex
.b
= (*codep
& 0x10) != 0;
13182 vex
.v
= *codep
& 0x8;
13183 vex
.mask_register_specifier
= *codep
& 0x7;
13184 vex
.zeroing
= *codep
& 0x80;
13190 dp
= &evex_table
[vex_table_index
][vindex
];
13192 FETCH_DATA (info
, codep
+ 1);
13193 modrm
.mod
= (*codep
>> 6) & 3;
13194 modrm
.reg
= (*codep
>> 3) & 7;
13195 modrm
.rm
= *codep
& 7;
13197 /* Set vector length. */
13198 if (modrm
.mod
== 3 && vex
.b
)
13214 return &bad_opcode
;
13227 if (dp
->name
!= NULL
)
13230 return get_valid_dis386 (dp
, info
);
13234 get_sib (disassemble_info
*info
, int sizeflag
)
13236 /* If modrm.mod == 3, operand must be register. */
13238 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13242 FETCH_DATA (info
, codep
+ 2);
13243 sib
.index
= (codep
[1] >> 3) & 7;
13244 sib
.scale
= (codep
[1] >> 6) & 3;
13245 sib
.base
= codep
[1] & 7;
13250 print_insn (bfd_vma pc
, disassemble_info
*info
)
13252 const struct dis386
*dp
;
13254 char *op_txt
[MAX_OPERANDS
];
13256 int sizeflag
, orig_sizeflag
;
13258 struct dis_private priv
;
13261 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13262 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
13263 address_mode
= mode_32bit
;
13264 else if (info
->mach
== bfd_mach_i386_i8086
)
13266 address_mode
= mode_16bit
;
13267 priv
.orig_sizeflag
= 0;
13270 address_mode
= mode_64bit
;
13272 if (intel_syntax
== (char) -1)
13273 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
13275 for (p
= info
->disassembler_options
; p
!= NULL
; )
13277 if (CONST_STRNEQ (p
, "amd64"))
13279 else if (CONST_STRNEQ (p
, "intel64"))
13281 else if (CONST_STRNEQ (p
, "x86-64"))
13283 address_mode
= mode_64bit
;
13284 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13286 else if (CONST_STRNEQ (p
, "i386"))
13288 address_mode
= mode_32bit
;
13289 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13291 else if (CONST_STRNEQ (p
, "i8086"))
13293 address_mode
= mode_16bit
;
13294 priv
.orig_sizeflag
= 0;
13296 else if (CONST_STRNEQ (p
, "intel"))
13299 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
13300 intel_mnemonic
= 1;
13302 else if (CONST_STRNEQ (p
, "att"))
13305 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
13306 intel_mnemonic
= 0;
13308 else if (CONST_STRNEQ (p
, "addr"))
13310 if (address_mode
== mode_64bit
)
13312 if (p
[4] == '3' && p
[5] == '2')
13313 priv
.orig_sizeflag
&= ~AFLAG
;
13314 else if (p
[4] == '6' && p
[5] == '4')
13315 priv
.orig_sizeflag
|= AFLAG
;
13319 if (p
[4] == '1' && p
[5] == '6')
13320 priv
.orig_sizeflag
&= ~AFLAG
;
13321 else if (p
[4] == '3' && p
[5] == '2')
13322 priv
.orig_sizeflag
|= AFLAG
;
13325 else if (CONST_STRNEQ (p
, "data"))
13327 if (p
[4] == '1' && p
[5] == '6')
13328 priv
.orig_sizeflag
&= ~DFLAG
;
13329 else if (p
[4] == '3' && p
[5] == '2')
13330 priv
.orig_sizeflag
|= DFLAG
;
13332 else if (CONST_STRNEQ (p
, "suffix"))
13333 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
13335 p
= strchr (p
, ',');
13340 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
13342 (*info
->fprintf_func
) (info
->stream
,
13343 _("64-bit address is disabled"));
13349 names64
= intel_names64
;
13350 names32
= intel_names32
;
13351 names16
= intel_names16
;
13352 names8
= intel_names8
;
13353 names8rex
= intel_names8rex
;
13354 names_seg
= intel_names_seg
;
13355 names_mm
= intel_names_mm
;
13356 names_bnd
= intel_names_bnd
;
13357 names_xmm
= intel_names_xmm
;
13358 names_ymm
= intel_names_ymm
;
13359 names_zmm
= intel_names_zmm
;
13360 index64
= intel_index64
;
13361 index32
= intel_index32
;
13362 names_mask
= intel_names_mask
;
13363 index16
= intel_index16
;
13366 separator_char
= '+';
13371 names64
= att_names64
;
13372 names32
= att_names32
;
13373 names16
= att_names16
;
13374 names8
= att_names8
;
13375 names8rex
= att_names8rex
;
13376 names_seg
= att_names_seg
;
13377 names_mm
= att_names_mm
;
13378 names_bnd
= att_names_bnd
;
13379 names_xmm
= att_names_xmm
;
13380 names_ymm
= att_names_ymm
;
13381 names_zmm
= att_names_zmm
;
13382 index64
= att_index64
;
13383 index32
= att_index32
;
13384 names_mask
= att_names_mask
;
13385 index16
= att_index16
;
13388 separator_char
= ',';
13392 /* The output looks better if we put 7 bytes on a line, since that
13393 puts most long word instructions on a single line. Use 8 bytes
13395 if ((info
->mach
& bfd_mach_l1om
) != 0)
13396 info
->bytes_per_line
= 8;
13398 info
->bytes_per_line
= 7;
13400 info
->private_data
= &priv
;
13401 priv
.max_fetched
= priv
.the_buffer
;
13402 priv
.insn_start
= pc
;
13405 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13413 start_codep
= priv
.the_buffer
;
13414 codep
= priv
.the_buffer
;
13416 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
13420 /* Getting here means we tried for data but didn't get it. That
13421 means we have an incomplete instruction of some sort. Just
13422 print the first byte as a prefix or a .byte pseudo-op. */
13423 if (codep
> priv
.the_buffer
)
13425 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
13427 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
13430 /* Just print the first byte as a .byte instruction. */
13431 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
13432 (unsigned int) priv
.the_buffer
[0]);
13442 sizeflag
= priv
.orig_sizeflag
;
13444 if (!ckprefix () || rex_used
)
13446 /* Too many prefixes or unused REX prefixes. */
13448 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
13450 (*info
->fprintf_func
) (info
->stream
, "%s%s",
13452 prefix_name (all_prefixes
[i
], sizeflag
));
13456 insn_codep
= codep
;
13458 FETCH_DATA (info
, codep
+ 1);
13459 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
13461 if (((prefixes
& PREFIX_FWAIT
)
13462 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
13464 /* Handle prefixes before fwait. */
13465 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
13467 (*info
->fprintf_func
) (info
->stream
, "%s ",
13468 prefix_name (all_prefixes
[i
], sizeflag
));
13469 (*info
->fprintf_func
) (info
->stream
, "fwait");
13473 if (*codep
== 0x0f)
13475 unsigned char threebyte
;
13478 FETCH_DATA (info
, codep
+ 1);
13479 threebyte
= *codep
;
13480 dp
= &dis386_twobyte
[threebyte
];
13481 need_modrm
= twobyte_has_modrm
[*codep
];
13486 dp
= &dis386
[*codep
];
13487 need_modrm
= onebyte_has_modrm
[*codep
];
13491 /* Save sizeflag for printing the extra prefixes later before updating
13492 it for mnemonic and operand processing. The prefix names depend
13493 only on the address mode. */
13494 orig_sizeflag
= sizeflag
;
13495 if (prefixes
& PREFIX_ADDR
)
13497 if ((prefixes
& PREFIX_DATA
))
13503 FETCH_DATA (info
, codep
+ 1);
13504 modrm
.mod
= (*codep
>> 6) & 3;
13505 modrm
.reg
= (*codep
>> 3) & 7;
13506 modrm
.rm
= *codep
& 7;
13514 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
13516 get_sib (info
, sizeflag
);
13517 dofloat (sizeflag
);
13521 dp
= get_valid_dis386 (dp
, info
);
13522 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
13524 get_sib (info
, sizeflag
);
13525 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13528 op_ad
= MAX_OPERANDS
- 1 - i
;
13530 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
13531 /* For EVEX instruction after the last operand masking
13532 should be printed. */
13533 if (i
== 0 && vex
.evex
)
13535 /* Don't print {%k0}. */
13536 if (vex
.mask_register_specifier
)
13539 oappend (names_mask
[vex
.mask_register_specifier
]);
13549 /* Check if the REX prefix is used. */
13550 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
13551 all_prefixes
[last_rex_prefix
] = 0;
13553 /* Check if the SEG prefix is used. */
13554 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
13555 | PREFIX_FS
| PREFIX_GS
)) != 0
13556 && (used_prefixes
& active_seg_prefix
) != 0)
13557 all_prefixes
[last_seg_prefix
] = 0;
13559 /* Check if the ADDR prefix is used. */
13560 if ((prefixes
& PREFIX_ADDR
) != 0
13561 && (used_prefixes
& PREFIX_ADDR
) != 0)
13562 all_prefixes
[last_addr_prefix
] = 0;
13564 /* Check if the DATA prefix is used. */
13565 if ((prefixes
& PREFIX_DATA
) != 0
13566 && (used_prefixes
& PREFIX_DATA
) != 0)
13567 all_prefixes
[last_data_prefix
] = 0;
13569 /* Print the extra prefixes. */
13571 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
13572 if (all_prefixes
[i
])
13575 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
13578 prefix_length
+= strlen (name
) + 1;
13579 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
13582 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13583 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13584 used by putop and MMX/SSE operand and may be overriden by the
13585 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13587 if (dp
->prefix_requirement
== PREFIX_OPCODE
13588 && dp
!= &bad_opcode
13590 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
13592 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
13594 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
13596 && (used_prefixes
& PREFIX_DATA
) == 0))))
13598 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13599 return end_codep
- priv
.the_buffer
;
13602 /* Check maximum code length. */
13603 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
13605 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13606 return MAX_CODE_LENGTH
;
13609 obufp
= mnemonicendp
;
13610 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
13613 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
13615 /* The enter and bound instructions are printed with operands in the same
13616 order as the intel book; everything else is printed in reverse order. */
13617 if (intel_syntax
|| two_source_ops
)
13621 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13622 op_txt
[i
] = op_out
[i
];
13624 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
13625 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
13627 op_txt
[2] = op_out
[3];
13628 op_txt
[3] = op_out
[2];
13631 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
13633 op_ad
= op_index
[i
];
13634 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
13635 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
13636 riprel
= op_riprel
[i
];
13637 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
13638 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
13643 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13644 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
13648 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13652 (*info
->fprintf_func
) (info
->stream
, ",");
13653 if (op_index
[i
] != -1 && !op_riprel
[i
])
13654 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
13656 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
13660 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13661 if (op_index
[i
] != -1 && op_riprel
[i
])
13663 (*info
->fprintf_func
) (info
->stream
, " # ");
13664 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
13665 + op_address
[op_index
[i
]]), info
);
13668 return codep
- priv
.the_buffer
;
13671 static const char *float_mem
[] = {
13746 static const unsigned char float_mem_mode
[] = {
13821 #define ST { OP_ST, 0 }
13822 #define STi { OP_STi, 0 }
13824 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13825 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13826 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13827 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13828 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13829 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13830 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13831 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13832 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13834 static const struct dis386 float_reg
[][8] = {
13837 { "fadd", { ST
, STi
}, 0 },
13838 { "fmul", { ST
, STi
}, 0 },
13839 { "fcom", { STi
}, 0 },
13840 { "fcomp", { STi
}, 0 },
13841 { "fsub", { ST
, STi
}, 0 },
13842 { "fsubr", { ST
, STi
}, 0 },
13843 { "fdiv", { ST
, STi
}, 0 },
13844 { "fdivr", { ST
, STi
}, 0 },
13848 { "fld", { STi
}, 0 },
13849 { "fxch", { STi
}, 0 },
13859 { "fcmovb", { ST
, STi
}, 0 },
13860 { "fcmove", { ST
, STi
}, 0 },
13861 { "fcmovbe",{ ST
, STi
}, 0 },
13862 { "fcmovu", { ST
, STi
}, 0 },
13870 { "fcmovnb",{ ST
, STi
}, 0 },
13871 { "fcmovne",{ ST
, STi
}, 0 },
13872 { "fcmovnbe",{ ST
, STi
}, 0 },
13873 { "fcmovnu",{ ST
, STi
}, 0 },
13875 { "fucomi", { ST
, STi
}, 0 },
13876 { "fcomi", { ST
, STi
}, 0 },
13881 { "fadd", { STi
, ST
}, 0 },
13882 { "fmul", { STi
, ST
}, 0 },
13885 { "fsub!M", { STi
, ST
}, 0 },
13886 { "fsubM", { STi
, ST
}, 0 },
13887 { "fdiv!M", { STi
, ST
}, 0 },
13888 { "fdivM", { STi
, ST
}, 0 },
13892 { "ffree", { STi
}, 0 },
13894 { "fst", { STi
}, 0 },
13895 { "fstp", { STi
}, 0 },
13896 { "fucom", { STi
}, 0 },
13897 { "fucomp", { STi
}, 0 },
13903 { "faddp", { STi
, ST
}, 0 },
13904 { "fmulp", { STi
, ST
}, 0 },
13907 { "fsub!Mp", { STi
, ST
}, 0 },
13908 { "fsubMp", { STi
, ST
}, 0 },
13909 { "fdiv!Mp", { STi
, ST
}, 0 },
13910 { "fdivMp", { STi
, ST
}, 0 },
13914 { "ffreep", { STi
}, 0 },
13919 { "fucomip", { ST
, STi
}, 0 },
13920 { "fcomip", { ST
, STi
}, 0 },
13925 static char *fgrps
[][8] = {
13928 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13933 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13938 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13943 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13948 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13953 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13958 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13959 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13964 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13969 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13974 swap_operand (void)
13976 mnemonicendp
[0] = '.';
13977 mnemonicendp
[1] = 's';
13982 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13983 int sizeflag ATTRIBUTE_UNUSED
)
13985 /* Skip mod/rm byte. */
13991 dofloat (int sizeflag
)
13993 const struct dis386
*dp
;
13994 unsigned char floatop
;
13996 floatop
= codep
[-1];
13998 if (modrm
.mod
!= 3)
14000 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
14002 putop (float_mem
[fp_indx
], sizeflag
);
14005 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
14008 /* Skip mod/rm byte. */
14012 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
14013 if (dp
->name
== NULL
)
14015 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
14017 /* Instruction fnstsw is only one with strange arg. */
14018 if (floatop
== 0xdf && codep
[-1] == 0xe0)
14019 strcpy (op_out
[0], names16
[0]);
14023 putop (dp
->name
, sizeflag
);
14028 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
14033 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
14037 /* Like oappend (below), but S is a string starting with '%'.
14038 In Intel syntax, the '%' is elided. */
14040 oappend_maybe_intel (const char *s
)
14042 oappend (s
+ intel_syntax
);
14046 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14048 oappend_maybe_intel ("%st");
14052 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14054 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
14055 oappend_maybe_intel (scratchbuf
);
14058 /* Capital letters in template are macros. */
14060 putop (const char *in_template
, int sizeflag
)
14065 unsigned int l
= 0, len
= 1;
14068 #define SAVE_LAST(c) \
14069 if (l < len && l < sizeof (last)) \
14074 for (p
= in_template
; *p
; p
++)
14090 while (*++p
!= '|')
14091 if (*p
== '}' || *p
== '\0')
14094 /* Fall through. */
14099 while (*++p
!= '}')
14110 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14114 if (l
== 0 && len
== 1)
14119 if (sizeflag
& SUFFIX_ALWAYS
)
14132 if (address_mode
== mode_64bit
14133 && !(prefixes
& PREFIX_ADDR
))
14144 if (intel_syntax
&& !alt
)
14146 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14148 if (sizeflag
& DFLAG
)
14149 *obufp
++ = intel_syntax
? 'd' : 'l';
14151 *obufp
++ = intel_syntax
? 'w' : 's';
14152 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14156 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14159 if (modrm
.mod
== 3)
14165 if (sizeflag
& DFLAG
)
14166 *obufp
++ = intel_syntax
? 'd' : 'l';
14169 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14175 case 'E': /* For jcxz/jecxz */
14176 if (address_mode
== mode_64bit
)
14178 if (sizeflag
& AFLAG
)
14184 if (sizeflag
& AFLAG
)
14186 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14191 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
14193 if (sizeflag
& AFLAG
)
14194 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
14196 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
14197 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14201 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
14203 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14207 if (!(rex
& REX_W
))
14208 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14213 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
14214 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
14216 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
14219 if (prefixes
& PREFIX_DS
)
14238 if (l
!= 0 || len
!= 1)
14240 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14245 if (!need_vex
|| !vex
.evex
)
14248 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14250 switch (vex
.length
)
14268 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
14273 /* Fall through. */
14276 if (l
!= 0 || len
!= 1)
14284 if (sizeflag
& SUFFIX_ALWAYS
)
14288 if (intel_mnemonic
!= cond
)
14292 if ((prefixes
& PREFIX_FWAIT
) == 0)
14295 used_prefixes
|= PREFIX_FWAIT
;
14301 else if (intel_syntax
&& (sizeflag
& DFLAG
))
14305 if (!(rex
& REX_W
))
14306 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14310 && address_mode
== mode_64bit
14311 && isa64
== intel64
)
14316 /* Fall through. */
14319 && address_mode
== mode_64bit
14320 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14325 /* Fall through. */
14328 if (l
== 0 && len
== 1)
14333 if ((rex
& REX_W
) == 0
14334 && (prefixes
& PREFIX_DATA
))
14336 if ((sizeflag
& DFLAG
) == 0)
14338 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14342 if ((prefixes
& PREFIX_DATA
)
14344 || (sizeflag
& SUFFIX_ALWAYS
))
14351 if (sizeflag
& DFLAG
)
14355 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14361 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14367 if ((prefixes
& PREFIX_DATA
)
14369 || (sizeflag
& SUFFIX_ALWAYS
))
14376 if (sizeflag
& DFLAG
)
14377 *obufp
++ = intel_syntax
? 'd' : 'l';
14380 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14388 if (address_mode
== mode_64bit
14389 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14391 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14395 /* Fall through. */
14398 if (l
== 0 && len
== 1)
14401 if (intel_syntax
&& !alt
)
14404 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14410 if (sizeflag
& DFLAG
)
14411 *obufp
++ = intel_syntax
? 'd' : 'l';
14414 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14420 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14426 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
14441 else if (sizeflag
& DFLAG
)
14450 if (intel_syntax
&& !p
[1]
14451 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
14453 if (!(rex
& REX_W
))
14454 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14457 if (l
== 0 && len
== 1)
14461 if (address_mode
== mode_64bit
14462 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14464 if (sizeflag
& SUFFIX_ALWAYS
)
14486 /* Fall through. */
14489 if (l
== 0 && len
== 1)
14494 if (sizeflag
& SUFFIX_ALWAYS
)
14500 if (sizeflag
& DFLAG
)
14504 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14518 if (address_mode
== mode_64bit
14519 && !(prefixes
& PREFIX_ADDR
))
14530 if (l
!= 0 || len
!= 1)
14535 if (need_vex
&& vex
.prefix
)
14537 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
14544 if (prefixes
& PREFIX_DATA
)
14548 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14552 if (l
== 0 && len
== 1)
14554 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14565 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14573 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14575 switch (vex
.length
)
14591 if (l
== 0 && len
== 1)
14593 /* operand size flag for cwtl, cbtw */
14602 else if (sizeflag
& DFLAG
)
14606 if (!(rex
& REX_W
))
14607 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14614 && last
[0] != 'L'))
14621 if (last
[0] == 'X')
14622 *obufp
++ = vex
.w
? 'd': 's';
14624 *obufp
++ = vex
.w
? 'q': 'd';
14630 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14632 if (sizeflag
& DFLAG
)
14636 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14642 if (address_mode
== mode_64bit
14643 && (isa64
== intel64
14644 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
14646 else if ((prefixes
& PREFIX_DATA
))
14648 if (!(sizeflag
& DFLAG
))
14650 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14657 mnemonicendp
= obufp
;
14662 oappend (const char *s
)
14664 obufp
= stpcpy (obufp
, s
);
14670 /* Only print the active segment register. */
14671 if (!active_seg_prefix
)
14674 used_prefixes
|= active_seg_prefix
;
14675 switch (active_seg_prefix
)
14678 oappend_maybe_intel ("%cs:");
14681 oappend_maybe_intel ("%ds:");
14684 oappend_maybe_intel ("%ss:");
14687 oappend_maybe_intel ("%es:");
14690 oappend_maybe_intel ("%fs:");
14693 oappend_maybe_intel ("%gs:");
14701 OP_indirE (int bytemode
, int sizeflag
)
14705 OP_E (bytemode
, sizeflag
);
14709 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
14711 if (address_mode
== mode_64bit
)
14719 sprintf_vma (tmp
, disp
);
14720 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
14721 strcpy (buf
+ 2, tmp
+ i
);
14725 bfd_signed_vma v
= disp
;
14732 /* Check for possible overflow on 0x8000000000000000. */
14735 strcpy (buf
, "9223372036854775808");
14749 tmp
[28 - i
] = (v
% 10) + '0';
14753 strcpy (buf
, tmp
+ 29 - i
);
14759 sprintf (buf
, "0x%x", (unsigned int) disp
);
14761 sprintf (buf
, "%d", (int) disp
);
14765 /* Put DISP in BUF as signed hex number. */
14768 print_displacement (char *buf
, bfd_vma disp
)
14770 bfd_signed_vma val
= disp
;
14779 /* Check for possible overflow. */
14782 switch (address_mode
)
14785 strcpy (buf
+ j
, "0x8000000000000000");
14788 strcpy (buf
+ j
, "0x80000000");
14791 strcpy (buf
+ j
, "0x8000");
14801 sprintf_vma (tmp
, (bfd_vma
) val
);
14802 for (i
= 0; tmp
[i
] == '0'; i
++)
14804 if (tmp
[i
] == '\0')
14806 strcpy (buf
+ j
, tmp
+ i
);
14810 intel_operand_size (int bytemode
, int sizeflag
)
14814 && (bytemode
== x_mode
14815 || bytemode
== evex_half_bcst_xmmq_mode
))
14818 oappend ("QWORD PTR ");
14820 oappend ("DWORD PTR ");
14829 oappend ("BYTE PTR ");
14834 case dqw_swap_mode
:
14835 oappend ("WORD PTR ");
14838 if (address_mode
== mode_64bit
&& isa64
== intel64
)
14840 oappend ("QWORD PTR ");
14843 /* Fall through. */
14845 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14847 oappend ("QWORD PTR ");
14850 /* Fall through. */
14856 oappend ("QWORD PTR ");
14859 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14860 oappend ("DWORD PTR ");
14862 oappend ("WORD PTR ");
14863 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14867 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14869 oappend ("WORD PTR ");
14870 if (!(rex
& REX_W
))
14871 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14874 if (sizeflag
& DFLAG
)
14875 oappend ("QWORD PTR ");
14877 oappend ("DWORD PTR ");
14878 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14881 case d_scalar_mode
:
14882 case d_scalar_swap_mode
:
14885 oappend ("DWORD PTR ");
14888 case q_scalar_mode
:
14889 case q_scalar_swap_mode
:
14891 oappend ("QWORD PTR ");
14894 if (address_mode
== mode_64bit
)
14895 oappend ("QWORD PTR ");
14897 oappend ("DWORD PTR ");
14900 if (sizeflag
& DFLAG
)
14901 oappend ("FWORD PTR ");
14903 oappend ("DWORD PTR ");
14904 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14907 oappend ("TBYTE PTR ");
14911 case evex_x_gscat_mode
:
14912 case evex_x_nobcst_mode
:
14915 switch (vex
.length
)
14918 oappend ("XMMWORD PTR ");
14921 oappend ("YMMWORD PTR ");
14924 oappend ("ZMMWORD PTR ");
14931 oappend ("XMMWORD PTR ");
14934 oappend ("XMMWORD PTR ");
14937 oappend ("YMMWORD PTR ");
14940 case evex_half_bcst_xmmq_mode
:
14944 switch (vex
.length
)
14947 oappend ("QWORD PTR ");
14950 oappend ("XMMWORD PTR ");
14953 oappend ("YMMWORD PTR ");
14963 switch (vex
.length
)
14968 oappend ("BYTE PTR ");
14978 switch (vex
.length
)
14983 oappend ("WORD PTR ");
14993 switch (vex
.length
)
14998 oappend ("DWORD PTR ");
15008 switch (vex
.length
)
15013 oappend ("QWORD PTR ");
15023 switch (vex
.length
)
15026 oappend ("WORD PTR ");
15029 oappend ("DWORD PTR ");
15032 oappend ("QWORD PTR ");
15042 switch (vex
.length
)
15045 oappend ("DWORD PTR ");
15048 oappend ("QWORD PTR ");
15051 oappend ("XMMWORD PTR ");
15061 switch (vex
.length
)
15064 oappend ("QWORD PTR ");
15067 oappend ("YMMWORD PTR ");
15070 oappend ("ZMMWORD PTR ");
15080 switch (vex
.length
)
15084 oappend ("XMMWORD PTR ");
15091 oappend ("OWORD PTR ");
15094 case vex_w_dq_mode
:
15095 case vex_scalar_w_dq_mode
:
15100 oappend ("QWORD PTR ");
15102 oappend ("DWORD PTR ");
15104 case vex_vsib_d_w_dq_mode
:
15105 case vex_vsib_q_w_dq_mode
:
15112 oappend ("QWORD PTR ");
15114 oappend ("DWORD PTR ");
15118 switch (vex
.length
)
15121 oappend ("XMMWORD PTR ");
15124 oappend ("YMMWORD PTR ");
15127 oappend ("ZMMWORD PTR ");
15134 case vex_vsib_q_w_d_mode
:
15135 case vex_vsib_d_w_d_mode
:
15136 if (!need_vex
|| !vex
.evex
)
15139 switch (vex
.length
)
15142 oappend ("QWORD PTR ");
15145 oappend ("XMMWORD PTR ");
15148 oappend ("YMMWORD PTR ");
15156 if (!need_vex
|| vex
.length
!= 128)
15159 oappend ("DWORD PTR ");
15161 oappend ("BYTE PTR ");
15167 oappend ("QWORD PTR ");
15169 oappend ("WORD PTR ");
15178 OP_E_register (int bytemode
, int sizeflag
)
15180 int reg
= modrm
.rm
;
15181 const char **names
;
15187 if ((sizeflag
& SUFFIX_ALWAYS
)
15188 && (bytemode
== b_swap_mode
15189 || bytemode
== v_swap_mode
15190 || bytemode
== dqw_swap_mode
))
15216 names
= address_mode
== mode_64bit
? names64
: names32
;
15222 if (address_mode
== mode_64bit
&& isa64
== intel64
)
15227 /* Fall through. */
15229 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15235 /* Fall through. */
15242 case dqw_swap_mode
:
15248 if ((sizeflag
& DFLAG
)
15249 || (bytemode
!= v_mode
15250 && bytemode
!= v_swap_mode
))
15254 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15264 names
= names_mask
;
15269 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15272 oappend (names
[reg
]);
15276 OP_E_memory (int bytemode
, int sizeflag
)
15279 int add
= (rex
& REX_B
) ? 8 : 0;
15285 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15287 && bytemode
!= x_mode
15288 && bytemode
!= xmmq_mode
15289 && bytemode
!= evex_half_bcst_xmmq_mode
)
15298 case dqw_swap_mode
:
15305 case vex_vsib_d_w_dq_mode
:
15306 case vex_vsib_d_w_d_mode
:
15307 case vex_vsib_q_w_dq_mode
:
15308 case vex_vsib_q_w_d_mode
:
15309 case evex_x_gscat_mode
:
15311 shift
= vex
.w
? 3 : 2;
15314 case evex_half_bcst_xmmq_mode
:
15318 shift
= vex
.w
? 3 : 2;
15321 /* Fall through. */
15325 case evex_x_nobcst_mode
:
15327 switch (vex
.length
)
15350 case q_scalar_mode
:
15352 case q_scalar_swap_mode
:
15358 case d_scalar_mode
:
15360 case d_scalar_swap_mode
:
15372 /* Make necessary corrections to shift for modes that need it.
15373 For these modes we currently have shift 4, 5 or 6 depending on
15374 vex.length (it corresponds to xmmword, ymmword or zmmword
15375 operand). We might want to make it 3, 4 or 5 (e.g. for
15376 xmmq_mode). In case of broadcast enabled the corrections
15377 aren't needed, as element size is always 32 or 64 bits. */
15379 && (bytemode
== xmmq_mode
15380 || bytemode
== evex_half_bcst_xmmq_mode
))
15382 else if (bytemode
== xmmqd_mode
)
15384 else if (bytemode
== xmmdw_mode
)
15386 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
15394 intel_operand_size (bytemode
, sizeflag
);
15397 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15399 /* 32/64 bit address mode */
15408 int addr32flag
= !((sizeflag
& AFLAG
)
15409 || bytemode
== v_bnd_mode
15410 || bytemode
== bnd_mode
);
15411 const char **indexes64
= names64
;
15412 const char **indexes32
= names32
;
15422 vindex
= sib
.index
;
15428 case vex_vsib_d_w_dq_mode
:
15429 case vex_vsib_d_w_d_mode
:
15430 case vex_vsib_q_w_dq_mode
:
15431 case vex_vsib_q_w_d_mode
:
15441 switch (vex
.length
)
15444 indexes64
= indexes32
= names_xmm
;
15448 || bytemode
== vex_vsib_q_w_dq_mode
15449 || bytemode
== vex_vsib_q_w_d_mode
)
15450 indexes64
= indexes32
= names_ymm
;
15452 indexes64
= indexes32
= names_xmm
;
15456 || bytemode
== vex_vsib_q_w_dq_mode
15457 || bytemode
== vex_vsib_q_w_d_mode
)
15458 indexes64
= indexes32
= names_zmm
;
15460 indexes64
= indexes32
= names_ymm
;
15467 haveindex
= vindex
!= 4;
15474 rbase
= base
+ add
;
15482 if (address_mode
== mode_64bit
&& !havesib
)
15488 FETCH_DATA (the_info
, codep
+ 1);
15490 if ((disp
& 0x80) != 0)
15492 if (vex
.evex
&& shift
> 0)
15500 /* In 32bit mode, we need index register to tell [offset] from
15501 [eiz*1 + offset]. */
15502 needindex
= (havesib
15505 && address_mode
== mode_32bit
);
15506 havedisp
= (havebase
15508 || (havesib
&& (haveindex
|| scale
!= 0)));
15511 if (modrm
.mod
!= 0 || base
== 5)
15513 if (havedisp
|| riprel
)
15514 print_displacement (scratchbuf
, disp
);
15516 print_operand_value (scratchbuf
, 1, disp
);
15517 oappend (scratchbuf
);
15521 oappend (!addr32flag
? "(%rip)" : "(%eip)");
15525 if ((havebase
|| haveindex
|| riprel
)
15526 && (bytemode
!= v_bnd_mode
)
15527 && (bytemode
!= bnd_mode
))
15528 used_prefixes
|= PREFIX_ADDR
;
15530 if (havedisp
|| (intel_syntax
&& riprel
))
15532 *obufp
++ = open_char
;
15533 if (intel_syntax
&& riprel
)
15536 oappend (!addr32flag
? "rip" : "eip");
15540 oappend (address_mode
== mode_64bit
&& !addr32flag
15541 ? names64
[rbase
] : names32
[rbase
]);
15544 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15545 print index to tell base + index from base. */
15549 || (havebase
&& base
!= ESP_REG_NUM
))
15551 if (!intel_syntax
|| havebase
)
15553 *obufp
++ = separator_char
;
15557 oappend (address_mode
== mode_64bit
&& !addr32flag
15558 ? indexes64
[vindex
] : indexes32
[vindex
]);
15560 oappend (address_mode
== mode_64bit
&& !addr32flag
15561 ? index64
: index32
);
15563 *obufp
++ = scale_char
;
15565 sprintf (scratchbuf
, "%d", 1 << scale
);
15566 oappend (scratchbuf
);
15570 && (disp
|| modrm
.mod
!= 0 || base
== 5))
15572 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
15577 else if (modrm
.mod
!= 1 && disp
!= -disp
)
15581 disp
= - (bfd_signed_vma
) disp
;
15585 print_displacement (scratchbuf
, disp
);
15587 print_operand_value (scratchbuf
, 1, disp
);
15588 oappend (scratchbuf
);
15591 *obufp
++ = close_char
;
15594 else if (intel_syntax
)
15596 if (modrm
.mod
!= 0 || base
== 5)
15598 if (!active_seg_prefix
)
15600 oappend (names_seg
[ds_reg
- es_reg
]);
15603 print_operand_value (scratchbuf
, 1, disp
);
15604 oappend (scratchbuf
);
15610 /* 16 bit address mode */
15611 used_prefixes
|= prefixes
& PREFIX_ADDR
;
15618 if ((disp
& 0x8000) != 0)
15623 FETCH_DATA (the_info
, codep
+ 1);
15625 if ((disp
& 0x80) != 0)
15630 if ((disp
& 0x8000) != 0)
15636 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
15638 print_displacement (scratchbuf
, disp
);
15639 oappend (scratchbuf
);
15642 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
15644 *obufp
++ = open_char
;
15646 oappend (index16
[modrm
.rm
]);
15648 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
15650 if ((bfd_signed_vma
) disp
>= 0)
15655 else if (modrm
.mod
!= 1)
15659 disp
= - (bfd_signed_vma
) disp
;
15662 print_displacement (scratchbuf
, disp
);
15663 oappend (scratchbuf
);
15666 *obufp
++ = close_char
;
15669 else if (intel_syntax
)
15671 if (!active_seg_prefix
)
15673 oappend (names_seg
[ds_reg
- es_reg
]);
15676 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
15677 oappend (scratchbuf
);
15680 if (vex
.evex
&& vex
.b
15681 && (bytemode
== x_mode
15682 || bytemode
== xmmq_mode
15683 || bytemode
== evex_half_bcst_xmmq_mode
))
15686 || bytemode
== xmmq_mode
15687 || bytemode
== evex_half_bcst_xmmq_mode
)
15689 switch (vex
.length
)
15692 oappend ("{1to2}");
15695 oappend ("{1to4}");
15698 oappend ("{1to8}");
15706 switch (vex
.length
)
15709 oappend ("{1to4}");
15712 oappend ("{1to8}");
15715 oappend ("{1to16}");
15725 OP_E (int bytemode
, int sizeflag
)
15727 /* Skip mod/rm byte. */
15731 if (modrm
.mod
== 3)
15732 OP_E_register (bytemode
, sizeflag
);
15734 OP_E_memory (bytemode
, sizeflag
);
15738 OP_G (int bytemode
, int sizeflag
)
15749 oappend (names8rex
[modrm
.reg
+ add
]);
15751 oappend (names8
[modrm
.reg
+ add
]);
15754 oappend (names16
[modrm
.reg
+ add
]);
15759 oappend (names32
[modrm
.reg
+ add
]);
15762 oappend (names64
[modrm
.reg
+ add
]);
15765 oappend (names_bnd
[modrm
.reg
]);
15772 case dqw_swap_mode
:
15775 oappend (names64
[modrm
.reg
+ add
]);
15778 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
15779 oappend (names32
[modrm
.reg
+ add
]);
15781 oappend (names16
[modrm
.reg
+ add
]);
15782 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15786 if (address_mode
== mode_64bit
)
15787 oappend (names64
[modrm
.reg
+ add
]);
15789 oappend (names32
[modrm
.reg
+ add
]);
15793 if ((modrm
.reg
+ add
) > 0x7)
15798 oappend (names_mask
[modrm
.reg
+ add
]);
15801 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15814 FETCH_DATA (the_info
, codep
+ 8);
15815 a
= *codep
++ & 0xff;
15816 a
|= (*codep
++ & 0xff) << 8;
15817 a
|= (*codep
++ & 0xff) << 16;
15818 a
|= (*codep
++ & 0xffu
) << 24;
15819 b
= *codep
++ & 0xff;
15820 b
|= (*codep
++ & 0xff) << 8;
15821 b
|= (*codep
++ & 0xff) << 16;
15822 b
|= (*codep
++ & 0xffu
) << 24;
15823 x
= a
+ ((bfd_vma
) b
<< 32);
15831 static bfd_signed_vma
15834 bfd_signed_vma x
= 0;
15836 FETCH_DATA (the_info
, codep
+ 4);
15837 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15838 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15839 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15840 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15844 static bfd_signed_vma
15847 bfd_signed_vma x
= 0;
15849 FETCH_DATA (the_info
, codep
+ 4);
15850 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15851 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15852 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15853 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15855 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15865 FETCH_DATA (the_info
, codep
+ 2);
15866 x
= *codep
++ & 0xff;
15867 x
|= (*codep
++ & 0xff) << 8;
15872 set_op (bfd_vma op
, int riprel
)
15874 op_index
[op_ad
] = op_ad
;
15875 if (address_mode
== mode_64bit
)
15877 op_address
[op_ad
] = op
;
15878 op_riprel
[op_ad
] = riprel
;
15882 /* Mask to get a 32-bit address. */
15883 op_address
[op_ad
] = op
& 0xffffffff;
15884 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15889 OP_REG (int code
, int sizeflag
)
15896 case es_reg
: case ss_reg
: case cs_reg
:
15897 case ds_reg
: case fs_reg
: case gs_reg
:
15898 oappend (names_seg
[code
- es_reg
]);
15910 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15911 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15912 s
= names16
[code
- ax_reg
+ add
];
15914 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15915 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15918 s
= names8rex
[code
- al_reg
+ add
];
15920 s
= names8
[code
- al_reg
];
15922 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15923 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15924 if (address_mode
== mode_64bit
15925 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15927 s
= names64
[code
- rAX_reg
+ add
];
15930 code
+= eAX_reg
- rAX_reg
;
15931 /* Fall through. */
15932 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15933 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15936 s
= names64
[code
- eAX_reg
+ add
];
15939 if (sizeflag
& DFLAG
)
15940 s
= names32
[code
- eAX_reg
+ add
];
15942 s
= names16
[code
- eAX_reg
+ add
];
15943 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15947 s
= INTERNAL_DISASSEMBLER_ERROR
;
15954 OP_IMREG (int code
, int sizeflag
)
15966 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15967 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15968 s
= names16
[code
- ax_reg
];
15970 case es_reg
: case ss_reg
: case cs_reg
:
15971 case ds_reg
: case fs_reg
: case gs_reg
:
15972 s
= names_seg
[code
- es_reg
];
15974 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15975 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15978 s
= names8rex
[code
- al_reg
];
15980 s
= names8
[code
- al_reg
];
15982 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15983 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15986 s
= names64
[code
- eAX_reg
];
15989 if (sizeflag
& DFLAG
)
15990 s
= names32
[code
- eAX_reg
];
15992 s
= names16
[code
- eAX_reg
];
15993 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15996 case z_mode_ax_reg
:
15997 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
16001 if (!(rex
& REX_W
))
16002 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16005 s
= INTERNAL_DISASSEMBLER_ERROR
;
16012 OP_I (int bytemode
, int sizeflag
)
16015 bfd_signed_vma mask
= -1;
16020 FETCH_DATA (the_info
, codep
+ 1);
16025 if (address_mode
== mode_64bit
)
16030 /* Fall through. */
16037 if (sizeflag
& DFLAG
)
16047 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16059 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16064 scratchbuf
[0] = '$';
16065 print_operand_value (scratchbuf
+ 1, 1, op
);
16066 oappend_maybe_intel (scratchbuf
);
16067 scratchbuf
[0] = '\0';
16071 OP_I64 (int bytemode
, int sizeflag
)
16074 bfd_signed_vma mask
= -1;
16076 if (address_mode
!= mode_64bit
)
16078 OP_I (bytemode
, sizeflag
);
16085 FETCH_DATA (the_info
, codep
+ 1);
16095 if (sizeflag
& DFLAG
)
16105 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16113 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16118 scratchbuf
[0] = '$';
16119 print_operand_value (scratchbuf
+ 1, 1, op
);
16120 oappend_maybe_intel (scratchbuf
);
16121 scratchbuf
[0] = '\0';
16125 OP_sI (int bytemode
, int sizeflag
)
16133 FETCH_DATA (the_info
, codep
+ 1);
16135 if ((op
& 0x80) != 0)
16137 if (bytemode
== b_T_mode
)
16139 if (address_mode
!= mode_64bit
16140 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
16142 /* The operand-size prefix is overridden by a REX prefix. */
16143 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16151 if (!(rex
& REX_W
))
16153 if (sizeflag
& DFLAG
)
16161 /* The operand-size prefix is overridden by a REX prefix. */
16162 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16168 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16172 scratchbuf
[0] = '$';
16173 print_operand_value (scratchbuf
+ 1, 1, op
);
16174 oappend_maybe_intel (scratchbuf
);
16178 OP_J (int bytemode
, int sizeflag
)
16182 bfd_vma segment
= 0;
16187 FETCH_DATA (the_info
, codep
+ 1);
16189 if ((disp
& 0x80) != 0)
16193 if (isa64
== amd64
)
16195 if ((sizeflag
& DFLAG
)
16196 || (address_mode
== mode_64bit
16197 && (isa64
!= amd64
|| (rex
& REX_W
))))
16202 if ((disp
& 0x8000) != 0)
16204 /* In 16bit mode, address is wrapped around at 64k within
16205 the same segment. Otherwise, a data16 prefix on a jump
16206 instruction means that the pc is masked to 16 bits after
16207 the displacement is added! */
16209 if ((prefixes
& PREFIX_DATA
) == 0)
16210 segment
= ((start_pc
+ (codep
- start_codep
))
16211 & ~((bfd_vma
) 0xffff));
16213 if (address_mode
!= mode_64bit
16214 || (isa64
== amd64
&& !(rex
& REX_W
)))
16215 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16218 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16221 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
16223 print_operand_value (scratchbuf
, 1, disp
);
16224 oappend (scratchbuf
);
16228 OP_SEG (int bytemode
, int sizeflag
)
16230 if (bytemode
== w_mode
)
16231 oappend (names_seg
[modrm
.reg
]);
16233 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
16237 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
16241 if (sizeflag
& DFLAG
)
16251 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16253 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
16255 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
16256 oappend (scratchbuf
);
16260 OP_OFF (int bytemode
, int sizeflag
)
16264 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16265 intel_operand_size (bytemode
, sizeflag
);
16268 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16275 if (!active_seg_prefix
)
16277 oappend (names_seg
[ds_reg
- es_reg
]);
16281 print_operand_value (scratchbuf
, 1, off
);
16282 oappend (scratchbuf
);
16286 OP_OFF64 (int bytemode
, int sizeflag
)
16290 if (address_mode
!= mode_64bit
16291 || (prefixes
& PREFIX_ADDR
))
16293 OP_OFF (bytemode
, sizeflag
);
16297 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16298 intel_operand_size (bytemode
, sizeflag
);
16305 if (!active_seg_prefix
)
16307 oappend (names_seg
[ds_reg
- es_reg
]);
16311 print_operand_value (scratchbuf
, 1, off
);
16312 oappend (scratchbuf
);
16316 ptr_reg (int code
, int sizeflag
)
16320 *obufp
++ = open_char
;
16321 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
16322 if (address_mode
== mode_64bit
)
16324 if (!(sizeflag
& AFLAG
))
16325 s
= names32
[code
- eAX_reg
];
16327 s
= names64
[code
- eAX_reg
];
16329 else if (sizeflag
& AFLAG
)
16330 s
= names32
[code
- eAX_reg
];
16332 s
= names16
[code
- eAX_reg
];
16334 *obufp
++ = close_char
;
16339 OP_ESreg (int code
, int sizeflag
)
16345 case 0x6d: /* insw/insl */
16346 intel_operand_size (z_mode
, sizeflag
);
16348 case 0xa5: /* movsw/movsl/movsq */
16349 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16350 case 0xab: /* stosw/stosl */
16351 case 0xaf: /* scasw/scasl */
16352 intel_operand_size (v_mode
, sizeflag
);
16355 intel_operand_size (b_mode
, sizeflag
);
16358 oappend_maybe_intel ("%es:");
16359 ptr_reg (code
, sizeflag
);
16363 OP_DSreg (int code
, int sizeflag
)
16369 case 0x6f: /* outsw/outsl */
16370 intel_operand_size (z_mode
, sizeflag
);
16372 case 0xa5: /* movsw/movsl/movsq */
16373 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16374 case 0xad: /* lodsw/lodsl/lodsq */
16375 intel_operand_size (v_mode
, sizeflag
);
16378 intel_operand_size (b_mode
, sizeflag
);
16381 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16382 default segment register DS is printed. */
16383 if (!active_seg_prefix
)
16384 active_seg_prefix
= PREFIX_DS
;
16386 ptr_reg (code
, sizeflag
);
16390 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16398 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
16400 all_prefixes
[last_lock_prefix
] = 0;
16401 used_prefixes
|= PREFIX_LOCK
;
16406 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
16407 oappend_maybe_intel (scratchbuf
);
16411 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16420 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
16422 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
16423 oappend (scratchbuf
);
16427 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16429 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
16430 oappend_maybe_intel (scratchbuf
);
16434 OP_R (int bytemode
, int sizeflag
)
16436 /* Skip mod/rm byte. */
16439 OP_E_register (bytemode
, sizeflag
);
16443 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16445 int reg
= modrm
.reg
;
16446 const char **names
;
16448 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16449 if (prefixes
& PREFIX_DATA
)
16458 oappend (names
[reg
]);
16462 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16464 int reg
= modrm
.reg
;
16465 const char **names
;
16477 && bytemode
!= xmm_mode
16478 && bytemode
!= xmmq_mode
16479 && bytemode
!= evex_half_bcst_xmmq_mode
16480 && bytemode
!= ymm_mode
16481 && bytemode
!= scalar_mode
)
16483 switch (vex
.length
)
16490 || (bytemode
!= vex_vsib_q_w_dq_mode
16491 && bytemode
!= vex_vsib_q_w_d_mode
))
16503 else if (bytemode
== xmmq_mode
16504 || bytemode
== evex_half_bcst_xmmq_mode
)
16506 switch (vex
.length
)
16519 else if (bytemode
== ymm_mode
)
16523 oappend (names
[reg
]);
16527 OP_EM (int bytemode
, int sizeflag
)
16530 const char **names
;
16532 if (modrm
.mod
!= 3)
16535 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16537 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16538 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16540 OP_E (bytemode
, sizeflag
);
16544 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
16547 /* Skip mod/rm byte. */
16550 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16552 if (prefixes
& PREFIX_DATA
)
16561 oappend (names
[reg
]);
16564 /* cvt* are the only instructions in sse2 which have
16565 both SSE and MMX operands and also have 0x66 prefix
16566 in their opcode. 0x66 was originally used to differentiate
16567 between SSE and MMX instruction(operands). So we have to handle the
16568 cvt* separately using OP_EMC and OP_MXC */
16570 OP_EMC (int bytemode
, int sizeflag
)
16572 if (modrm
.mod
!= 3)
16574 if (intel_syntax
&& bytemode
== v_mode
)
16576 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16577 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16579 OP_E (bytemode
, sizeflag
);
16583 /* Skip mod/rm byte. */
16586 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16587 oappend (names_mm
[modrm
.rm
]);
16591 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16593 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16594 oappend (names_mm
[modrm
.reg
]);
16598 OP_EX (int bytemode
, int sizeflag
)
16601 const char **names
;
16603 /* Skip mod/rm byte. */
16607 if (modrm
.mod
!= 3)
16609 OP_E_memory (bytemode
, sizeflag
);
16624 if ((sizeflag
& SUFFIX_ALWAYS
)
16625 && (bytemode
== x_swap_mode
16626 || bytemode
== d_swap_mode
16627 || bytemode
== dqw_swap_mode
16628 || bytemode
== d_scalar_swap_mode
16629 || bytemode
== q_swap_mode
16630 || bytemode
== q_scalar_swap_mode
))
16634 && bytemode
!= xmm_mode
16635 && bytemode
!= xmmdw_mode
16636 && bytemode
!= xmmqd_mode
16637 && bytemode
!= xmm_mb_mode
16638 && bytemode
!= xmm_mw_mode
16639 && bytemode
!= xmm_md_mode
16640 && bytemode
!= xmm_mq_mode
16641 && bytemode
!= xmm_mdq_mode
16642 && bytemode
!= xmmq_mode
16643 && bytemode
!= evex_half_bcst_xmmq_mode
16644 && bytemode
!= ymm_mode
16645 && bytemode
!= d_scalar_mode
16646 && bytemode
!= d_scalar_swap_mode
16647 && bytemode
!= q_scalar_mode
16648 && bytemode
!= q_scalar_swap_mode
16649 && bytemode
!= vex_scalar_w_dq_mode
)
16651 switch (vex
.length
)
16666 else if (bytemode
== xmmq_mode
16667 || bytemode
== evex_half_bcst_xmmq_mode
)
16669 switch (vex
.length
)
16682 else if (bytemode
== ymm_mode
)
16686 oappend (names
[reg
]);
16690 OP_MS (int bytemode
, int sizeflag
)
16692 if (modrm
.mod
== 3)
16693 OP_EM (bytemode
, sizeflag
);
16699 OP_XS (int bytemode
, int sizeflag
)
16701 if (modrm
.mod
== 3)
16702 OP_EX (bytemode
, sizeflag
);
16708 OP_M (int bytemode
, int sizeflag
)
16710 if (modrm
.mod
== 3)
16711 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16714 OP_E (bytemode
, sizeflag
);
16718 OP_0f07 (int bytemode
, int sizeflag
)
16720 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
16723 OP_E (bytemode
, sizeflag
);
16726 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16727 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16730 NOP_Fixup1 (int bytemode
, int sizeflag
)
16732 if ((prefixes
& PREFIX_DATA
) != 0
16735 && address_mode
== mode_64bit
))
16736 OP_REG (bytemode
, sizeflag
);
16738 strcpy (obuf
, "nop");
16742 NOP_Fixup2 (int bytemode
, int sizeflag
)
16744 if ((prefixes
& PREFIX_DATA
) != 0
16747 && address_mode
== mode_64bit
))
16748 OP_IMREG (bytemode
, sizeflag
);
16751 static const char *const Suffix3DNow
[] = {
16752 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16753 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16754 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16755 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16756 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16757 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16758 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16759 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16760 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16761 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16762 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16763 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16764 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16765 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16766 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16767 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16768 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16769 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16770 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16771 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16772 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16773 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16774 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16775 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16776 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16777 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16778 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16779 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16780 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16781 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16782 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16783 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16784 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16785 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16786 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16787 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16788 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16789 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16790 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16791 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16792 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16793 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16794 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16795 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16796 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16797 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16798 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16799 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16800 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16801 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16802 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16803 /* CC */ NULL
, NULL
, NULL
, NULL
,
16804 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16805 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16806 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16807 /* DC */ NULL
, NULL
, NULL
, NULL
,
16808 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16809 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16810 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16811 /* EC */ NULL
, NULL
, NULL
, NULL
,
16812 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16813 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16814 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16815 /* FC */ NULL
, NULL
, NULL
, NULL
,
16819 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16821 const char *mnemonic
;
16823 FETCH_DATA (the_info
, codep
+ 1);
16824 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16825 place where an 8-bit immediate would normally go. ie. the last
16826 byte of the instruction. */
16827 obufp
= mnemonicendp
;
16828 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16830 oappend (mnemonic
);
16833 /* Since a variable sized modrm/sib chunk is between the start
16834 of the opcode (0x0f0f) and the opcode suffix, we need to do
16835 all the modrm processing first, and don't know until now that
16836 we have a bad opcode. This necessitates some cleaning up. */
16837 op_out
[0][0] = '\0';
16838 op_out
[1][0] = '\0';
16841 mnemonicendp
= obufp
;
16844 static struct op simd_cmp_op
[] =
16846 { STRING_COMMA_LEN ("eq") },
16847 { STRING_COMMA_LEN ("lt") },
16848 { STRING_COMMA_LEN ("le") },
16849 { STRING_COMMA_LEN ("unord") },
16850 { STRING_COMMA_LEN ("neq") },
16851 { STRING_COMMA_LEN ("nlt") },
16852 { STRING_COMMA_LEN ("nle") },
16853 { STRING_COMMA_LEN ("ord") }
16857 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16859 unsigned int cmp_type
;
16861 FETCH_DATA (the_info
, codep
+ 1);
16862 cmp_type
= *codep
++ & 0xff;
16863 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16866 char *p
= mnemonicendp
- 2;
16870 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16871 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16875 /* We have a reserved extension byte. Output it directly. */
16876 scratchbuf
[0] = '$';
16877 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16878 oappend_maybe_intel (scratchbuf
);
16879 scratchbuf
[0] = '\0';
16884 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
16885 int sizeflag ATTRIBUTE_UNUSED
)
16887 /* mwaitx %eax,%ecx,%ebx */
16890 const char **names
= (address_mode
== mode_64bit
16891 ? names64
: names32
);
16892 strcpy (op_out
[0], names
[0]);
16893 strcpy (op_out
[1], names
[1]);
16894 strcpy (op_out
[2], names
[3]);
16895 two_source_ops
= 1;
16897 /* Skip mod/rm byte. */
16903 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
16904 int sizeflag ATTRIBUTE_UNUSED
)
16906 /* mwait %eax,%ecx */
16909 const char **names
= (address_mode
== mode_64bit
16910 ? names64
: names32
);
16911 strcpy (op_out
[0], names
[0]);
16912 strcpy (op_out
[1], names
[1]);
16913 two_source_ops
= 1;
16915 /* Skip mod/rm byte. */
16921 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16922 int sizeflag ATTRIBUTE_UNUSED
)
16924 /* monitor %eax,%ecx,%edx" */
16927 const char **op1_names
;
16928 const char **names
= (address_mode
== mode_64bit
16929 ? names64
: names32
);
16931 if (!(prefixes
& PREFIX_ADDR
))
16932 op1_names
= (address_mode
== mode_16bit
16933 ? names16
: names
);
16936 /* Remove "addr16/addr32". */
16937 all_prefixes
[last_addr_prefix
] = 0;
16938 op1_names
= (address_mode
!= mode_32bit
16939 ? names32
: names16
);
16940 used_prefixes
|= PREFIX_ADDR
;
16942 strcpy (op_out
[0], op1_names
[0]);
16943 strcpy (op_out
[1], names
[1]);
16944 strcpy (op_out
[2], names
[2]);
16945 two_source_ops
= 1;
16947 /* Skip mod/rm byte. */
16955 /* Throw away prefixes and 1st. opcode byte. */
16956 codep
= insn_codep
+ 1;
16961 REP_Fixup (int bytemode
, int sizeflag
)
16963 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16965 if (prefixes
& PREFIX_REPZ
)
16966 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16973 OP_IMREG (bytemode
, sizeflag
);
16976 OP_ESreg (bytemode
, sizeflag
);
16979 OP_DSreg (bytemode
, sizeflag
);
16987 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16991 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16993 if (prefixes
& PREFIX_REPNZ
)
16994 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16997 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16998 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
17002 HLE_Fixup1 (int bytemode
, int sizeflag
)
17005 && (prefixes
& PREFIX_LOCK
) != 0)
17007 if (prefixes
& PREFIX_REPZ
)
17008 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
17009 if (prefixes
& PREFIX_REPNZ
)
17010 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
17013 OP_E (bytemode
, sizeflag
);
17016 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
17017 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
17021 HLE_Fixup2 (int bytemode
, int sizeflag
)
17023 if (modrm
.mod
!= 3)
17025 if (prefixes
& PREFIX_REPZ
)
17026 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
17027 if (prefixes
& PREFIX_REPNZ
)
17028 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
17031 OP_E (bytemode
, sizeflag
);
17034 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
17035 "xrelease" for memory operand. No check for LOCK prefix. */
17038 HLE_Fixup3 (int bytemode
, int sizeflag
)
17041 && last_repz_prefix
> last_repnz_prefix
17042 && (prefixes
& PREFIX_REPZ
) != 0)
17043 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
17045 OP_E (bytemode
, sizeflag
);
17049 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
17054 /* Change cmpxchg8b to cmpxchg16b. */
17055 char *p
= mnemonicendp
- 2;
17056 mnemonicendp
= stpcpy (p
, "16b");
17059 else if ((prefixes
& PREFIX_LOCK
) != 0)
17061 if (prefixes
& PREFIX_REPZ
)
17062 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
17063 if (prefixes
& PREFIX_REPNZ
)
17064 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
17067 OP_M (bytemode
, sizeflag
);
17071 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
17073 const char **names
;
17077 switch (vex
.length
)
17091 oappend (names
[reg
]);
17095 CRC32_Fixup (int bytemode
, int sizeflag
)
17097 /* Add proper suffix to "crc32". */
17098 char *p
= mnemonicendp
;
17117 if (sizeflag
& DFLAG
)
17121 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17125 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17132 if (modrm
.mod
== 3)
17136 /* Skip mod/rm byte. */
17141 add
= (rex
& REX_B
) ? 8 : 0;
17142 if (bytemode
== b_mode
)
17146 oappend (names8rex
[modrm
.rm
+ add
]);
17148 oappend (names8
[modrm
.rm
+ add
]);
17154 oappend (names64
[modrm
.rm
+ add
]);
17155 else if ((prefixes
& PREFIX_DATA
))
17156 oappend (names16
[modrm
.rm
+ add
]);
17158 oappend (names32
[modrm
.rm
+ add
]);
17162 OP_E (bytemode
, sizeflag
);
17166 FXSAVE_Fixup (int bytemode
, int sizeflag
)
17168 /* Add proper suffix to "fxsave" and "fxrstor". */
17172 char *p
= mnemonicendp
;
17178 OP_M (bytemode
, sizeflag
);
17181 /* Display the destination register operand for instructions with
17185 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17188 const char **names
;
17196 reg
= vex
.register_specifier
;
17203 if (bytemode
== vex_scalar_mode
)
17205 oappend (names_xmm
[reg
]);
17209 switch (vex
.length
)
17216 case vex_vsib_q_w_dq_mode
:
17217 case vex_vsib_q_w_d_mode
:
17233 names
= names_mask
;
17247 case vex_vsib_q_w_dq_mode
:
17248 case vex_vsib_q_w_d_mode
:
17249 names
= vex
.w
? names_ymm
: names_xmm
;
17258 names
= names_mask
;
17272 oappend (names
[reg
]);
17275 /* Get the VEX immediate byte without moving codep. */
17277 static unsigned char
17278 get_vex_imm8 (int sizeflag
, int opnum
)
17280 int bytes_before_imm
= 0;
17282 if (modrm
.mod
!= 3)
17284 /* There are SIB/displacement bytes. */
17285 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
17287 /* 32/64 bit address mode */
17288 int base
= modrm
.rm
;
17290 /* Check SIB byte. */
17293 FETCH_DATA (the_info
, codep
+ 1);
17295 /* When decoding the third source, don't increase
17296 bytes_before_imm as this has already been incremented
17297 by one in OP_E_memory while decoding the second
17300 bytes_before_imm
++;
17303 /* Don't increase bytes_before_imm when decoding the third source,
17304 it has already been incremented by OP_E_memory while decoding
17305 the second source operand. */
17311 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17312 SIB == 5, there is a 4 byte displacement. */
17314 /* No displacement. */
17316 /* Fall through. */
17318 /* 4 byte displacement. */
17319 bytes_before_imm
+= 4;
17322 /* 1 byte displacement. */
17323 bytes_before_imm
++;
17330 /* 16 bit address mode */
17331 /* Don't increase bytes_before_imm when decoding the third source,
17332 it has already been incremented by OP_E_memory while decoding
17333 the second source operand. */
17339 /* When modrm.rm == 6, there is a 2 byte displacement. */
17341 /* No displacement. */
17343 /* Fall through. */
17345 /* 2 byte displacement. */
17346 bytes_before_imm
+= 2;
17349 /* 1 byte displacement: when decoding the third source,
17350 don't increase bytes_before_imm as this has already
17351 been incremented by one in OP_E_memory while decoding
17352 the second source operand. */
17354 bytes_before_imm
++;
17362 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
17363 return codep
[bytes_before_imm
];
17367 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
17369 const char **names
;
17371 if (reg
== -1 && modrm
.mod
!= 3)
17373 OP_E_memory (bytemode
, sizeflag
);
17385 else if (reg
> 7 && address_mode
!= mode_64bit
)
17389 switch (vex
.length
)
17400 oappend (names
[reg
]);
17404 OP_EX_VexImmW (int bytemode
, int sizeflag
)
17407 static unsigned char vex_imm8
;
17409 if (vex_w_done
== 0)
17413 /* Skip mod/rm byte. */
17417 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
17420 reg
= vex_imm8
>> 4;
17422 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17424 else if (vex_w_done
== 1)
17429 reg
= vex_imm8
>> 4;
17431 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17435 /* Output the imm8 directly. */
17436 scratchbuf
[0] = '$';
17437 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
17438 oappend_maybe_intel (scratchbuf
);
17439 scratchbuf
[0] = '\0';
17445 OP_Vex_2src (int bytemode
, int sizeflag
)
17447 if (modrm
.mod
== 3)
17449 int reg
= modrm
.rm
;
17453 oappend (names_xmm
[reg
]);
17458 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
17460 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
17461 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17463 OP_E (bytemode
, sizeflag
);
17468 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
17470 if (modrm
.mod
== 3)
17472 /* Skip mod/rm byte. */
17478 oappend (names_xmm
[vex
.register_specifier
]);
17480 OP_Vex_2src (bytemode
, sizeflag
);
17484 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
17487 OP_Vex_2src (bytemode
, sizeflag
);
17489 oappend (names_xmm
[vex
.register_specifier
]);
17493 OP_EX_VexW (int bytemode
, int sizeflag
)
17501 /* Skip mod/rm byte. */
17506 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
17511 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
17514 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17518 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17519 int sizeflag ATTRIBUTE_UNUSED
)
17521 /* Skip the immediate byte and check for invalid bits. */
17522 FETCH_DATA (the_info
, codep
+ 1);
17523 if (*codep
++ & 0xf)
17528 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17531 const char **names
;
17533 FETCH_DATA (the_info
, codep
+ 1);
17536 if (bytemode
!= x_mode
)
17543 if (reg
> 7 && address_mode
!= mode_64bit
)
17546 switch (vex
.length
)
17557 oappend (names
[reg
]);
17561 OP_XMM_VexW (int bytemode
, int sizeflag
)
17563 /* Turn off the REX.W bit since it is used for swapping operands
17566 OP_XMM (bytemode
, sizeflag
);
17570 OP_EX_Vex (int bytemode
, int sizeflag
)
17572 if (modrm
.mod
!= 3)
17574 if (vex
.register_specifier
!= 0)
17578 OP_EX (bytemode
, sizeflag
);
17582 OP_XMM_Vex (int bytemode
, int sizeflag
)
17584 if (modrm
.mod
!= 3)
17586 if (vex
.register_specifier
!= 0)
17590 OP_XMM (bytemode
, sizeflag
);
17594 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17596 switch (vex
.length
)
17599 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
17602 mnemonicendp
= stpcpy (obuf
, "vzeroall");
17609 static struct op vex_cmp_op
[] =
17611 { STRING_COMMA_LEN ("eq") },
17612 { STRING_COMMA_LEN ("lt") },
17613 { STRING_COMMA_LEN ("le") },
17614 { STRING_COMMA_LEN ("unord") },
17615 { STRING_COMMA_LEN ("neq") },
17616 { STRING_COMMA_LEN ("nlt") },
17617 { STRING_COMMA_LEN ("nle") },
17618 { STRING_COMMA_LEN ("ord") },
17619 { STRING_COMMA_LEN ("eq_uq") },
17620 { STRING_COMMA_LEN ("nge") },
17621 { STRING_COMMA_LEN ("ngt") },
17622 { STRING_COMMA_LEN ("false") },
17623 { STRING_COMMA_LEN ("neq_oq") },
17624 { STRING_COMMA_LEN ("ge") },
17625 { STRING_COMMA_LEN ("gt") },
17626 { STRING_COMMA_LEN ("true") },
17627 { STRING_COMMA_LEN ("eq_os") },
17628 { STRING_COMMA_LEN ("lt_oq") },
17629 { STRING_COMMA_LEN ("le_oq") },
17630 { STRING_COMMA_LEN ("unord_s") },
17631 { STRING_COMMA_LEN ("neq_us") },
17632 { STRING_COMMA_LEN ("nlt_uq") },
17633 { STRING_COMMA_LEN ("nle_uq") },
17634 { STRING_COMMA_LEN ("ord_s") },
17635 { STRING_COMMA_LEN ("eq_us") },
17636 { STRING_COMMA_LEN ("nge_uq") },
17637 { STRING_COMMA_LEN ("ngt_uq") },
17638 { STRING_COMMA_LEN ("false_os") },
17639 { STRING_COMMA_LEN ("neq_os") },
17640 { STRING_COMMA_LEN ("ge_oq") },
17641 { STRING_COMMA_LEN ("gt_oq") },
17642 { STRING_COMMA_LEN ("true_us") },
17646 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17648 unsigned int cmp_type
;
17650 FETCH_DATA (the_info
, codep
+ 1);
17651 cmp_type
= *codep
++ & 0xff;
17652 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
17655 char *p
= mnemonicendp
- 2;
17659 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
17660 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
17664 /* We have a reserved extension byte. Output it directly. */
17665 scratchbuf
[0] = '$';
17666 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17667 oappend_maybe_intel (scratchbuf
);
17668 scratchbuf
[0] = '\0';
17673 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17674 int sizeflag ATTRIBUTE_UNUSED
)
17676 unsigned int cmp_type
;
17681 FETCH_DATA (the_info
, codep
+ 1);
17682 cmp_type
= *codep
++ & 0xff;
17683 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17684 If it's the case, print suffix, otherwise - print the immediate. */
17685 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
17690 char *p
= mnemonicendp
- 2;
17692 /* vpcmp* can have both one- and two-lettered suffix. */
17706 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
17707 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
17711 /* We have a reserved extension byte. Output it directly. */
17712 scratchbuf
[0] = '$';
17713 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17714 oappend_maybe_intel (scratchbuf
);
17715 scratchbuf
[0] = '\0';
17719 static const struct op pclmul_op
[] =
17721 { STRING_COMMA_LEN ("lql") },
17722 { STRING_COMMA_LEN ("hql") },
17723 { STRING_COMMA_LEN ("lqh") },
17724 { STRING_COMMA_LEN ("hqh") }
17728 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17729 int sizeflag ATTRIBUTE_UNUSED
)
17731 unsigned int pclmul_type
;
17733 FETCH_DATA (the_info
, codep
+ 1);
17734 pclmul_type
= *codep
++ & 0xff;
17735 switch (pclmul_type
)
17746 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
17749 char *p
= mnemonicendp
- 3;
17754 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
17755 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
17759 /* We have a reserved extension byte. Output it directly. */
17760 scratchbuf
[0] = '$';
17761 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
17762 oappend_maybe_intel (scratchbuf
);
17763 scratchbuf
[0] = '\0';
17768 MOVBE_Fixup (int bytemode
, int sizeflag
)
17770 /* Add proper suffix to "movbe". */
17771 char *p
= mnemonicendp
;
17780 if (sizeflag
& SUFFIX_ALWAYS
)
17786 if (sizeflag
& DFLAG
)
17790 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17795 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17802 OP_M (bytemode
, sizeflag
);
17806 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17809 const char **names
;
17811 /* Skip mod/rm byte. */
17825 oappend (names
[reg
]);
17829 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17831 const char **names
;
17838 oappend (names
[vex
.register_specifier
]);
17842 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17845 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
17849 if ((rex
& REX_R
) != 0 || !vex
.r
)
17855 oappend (names_mask
[modrm
.reg
]);
17859 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17862 || (bytemode
!= evex_rounding_mode
17863 && bytemode
!= evex_sae_mode
))
17865 if (modrm
.mod
== 3 && vex
.b
)
17868 case evex_rounding_mode
:
17869 oappend (names_rounding
[vex
.ll
]);
17871 case evex_sae_mode
: