opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_VexR (int, int);
  91 static void OP_VexW (int, int);
  92 static void OP_Rounding (int, int);
  93 static void OP_REG_VexI4 (int, int);
  94 static void OP_VexI4 (int, int);
  95 static void PCLMUL_Fixup (int, int);
  96 static void VPCMP_Fixup (int, int);
  97 static void VPCOM_Fixup (int, int);
  98 static void OP_0f07 (int, int);
  99 static void OP_Monitor (int, int);
 100 static void OP_Mwait (int, int);
 101 static void NOP_Fixup1 (int, int);
 102 static void NOP_Fixup2 (int, int);
 103 static void OP_3DNowSuffix (int, int);
 104 static void CMP_Fixup (int, int);
 105 static void BadOp (void);
 106 static void REP_Fixup (int, int);
 107 static void SEP_Fixup (int, int);
 108 static void BND_Fixup (int, int);
 109 static void NOTRACK_Fixup (int, int);
 110 static void HLE_Fixup1 (int, int);
 111 static void HLE_Fixup2 (int, int);
 112 static void HLE_Fixup3 (int, int);
 113 static void CMPXCHG8B_Fixup (int, int);
 114 static void XMM_Fixup (int, int);
 115 static void FXSAVE_Fixup (int, int);
 116
 117 static void MOVSXD_Fixup (int, int);
 118
 119 static void OP_Mask (int, int);
 120
 121 struct dis_private {
 122   /* Points to first byte not fetched.  */
 123   bfd_byte *max_fetched;
 124   bfd_byte the_buffer[MAX_MNEM_SIZE];
 125   bfd_vma insn_start;
 126   int orig_sizeflag;
 127   OPCODES_SIGJMP_BUF bailout;
 128 };
 129
 130 enum address_mode
 131 {
 132   mode_16bit,
 133   mode_32bit,
 134   mode_64bit
 135 };
 136
 137 enum address_mode address_mode;
 138
 139 /* Flags for the prefixes for the current instruction.  See below.  */
 140 static int prefixes;
 141
 142 /* REX prefix the current instruction.  See below.  */
 143 static int rex;
 144 /* Bits of REX we've already used.  */
 145 static int rex_used;
 146 /* Mark parts used in the REX prefix.  When we are testing for
 147    empty prefix (for 8bit register REX extension), just mask it
 148    out.  Otherwise test for REX bit is excuse for existence of REX
 149    only in case value is nonzero.  */
 150 #define USED_REX(value)                                 \
 151   {                                                     \
 152     if (value)                                          \
 153       {                                                 \
 154         if ((rex & value))                              \
 155           rex_used |= (value) | REX_OPCODE;             \
 156       }                                                 \
 157     else                                                \
 158       rex_used |= REX_OPCODE;                           \
 159   }
 160
 161 /* Flags for prefixes which we somehow handled when printing the
 162    current instruction.  */
 163 static int used_prefixes;
 164
 165 /* Flags stored in PREFIXES.  */
 166 #define PREFIX_REPZ 1
 167 #define PREFIX_REPNZ 2
 168 #define PREFIX_LOCK 4
 169 #define PREFIX_CS 8
 170 #define PREFIX_SS 0x10
 171 #define PREFIX_DS 0x20
 172 #define PREFIX_ES 0x40
 173 #define PREFIX_FS 0x80
 174 #define PREFIX_GS 0x100
 175 #define PREFIX_DATA 0x200
 176 #define PREFIX_ADDR 0x400
 177 #define PREFIX_FWAIT 0x800
 178
 179 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 180    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 181    on error.  */
 182 #define FETCH_DATA(info, addr) \
 183   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 184    ? 1 : fetch_data ((info), (addr)))
 185
 186 static int
 187 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 188 {
 189   int status;
 190   struct dis_private *priv = (struct dis_private *) info->private_data;
 191   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 192
 193   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 194     status = (*info->read_memory_func) (start,
 195                                         priv->max_fetched,
 196                                         addr - priv->max_fetched,
 197                                         info);
 198   else
 199     status = -1;
 200   if (status != 0)
 201     {
 202       /* If we did manage to read at least one byte, then
 203          print_insn_i386 will do something sensible.  Otherwise, print
 204          an error.  We do that here because this is where we know
 205          STATUS.  */
 206       if (priv->max_fetched == priv->the_buffer)
 207         (*info->memory_error_func) (status, start, info);
 208       OPCODES_SIGLONGJMP (priv->bailout, 1);
 209     }
 210   else
 211     priv->max_fetched = addr;
 212   return 1;
 213 }
 214
 215 /* Possible values for prefix requirement.  */
 216 #define PREFIX_IGNORED_SHIFT    16
 217 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 218 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 219 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 220 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 221 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 222
 223 /* Opcode prefixes.  */
 224 #define PREFIX_OPCODE           (PREFIX_REPZ \
 225                                  | PREFIX_REPNZ \
 226                                  | PREFIX_DATA)
 227
 228 /* Prefixes ignored.  */
 229 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 230                                  | PREFIX_IGNORED_REPNZ \
 231                                  | PREFIX_IGNORED_DATA)
 232
 233 #define XX { NULL, 0 }
 234 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 235
 236 #define Eb { OP_E, b_mode }
 237 #define Ebnd { OP_E, bnd_mode }
 238 #define EbS { OP_E, b_swap_mode }
 239 #define EbndS { OP_E, bnd_swap_mode }
 240 #define Ev { OP_E, v_mode }
 241 #define Eva { OP_E, va_mode }
 242 #define Ev_bnd { OP_E, v_bnd_mode }
 243 #define EvS { OP_E, v_swap_mode }
 244 #define Ed { OP_E, d_mode }
 245 #define Edq { OP_E, dq_mode }
 246 #define Edqw { OP_E, dqw_mode }
 247 #define Edqb { OP_E, dqb_mode }
 248 #define Edb { OP_E, db_mode }
 249 #define Edw { OP_E, dw_mode }
 250 #define Edqd { OP_E, dqd_mode }
 251 #define Eq { OP_E, q_mode }
 252 #define indirEv { OP_indirE, indir_v_mode }
 253 #define indirEp { OP_indirE, f_mode }
 254 #define stackEv { OP_E, stack_v_mode }
 255 #define Em { OP_E, m_mode }
 256 #define Ew { OP_E, w_mode }
 257 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 258 #define Ma { OP_M, a_mode }
 259 #define Mb { OP_M, b_mode }
 260 #define Md { OP_M, d_mode }
 261 #define Mo { OP_M, o_mode }
 262 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 263 #define Mq { OP_M, q_mode }
 264 #define Mv { OP_M, v_mode }
 265 #define Mv_bnd { OP_M, v_bndmk_mode }
 266 #define Mx { OP_M, x_mode }
 267 #define Mxmm { OP_M, xmm_mode }
 268 #define Gb { OP_G, b_mode }
 269 #define Gbnd { OP_G, bnd_mode }
 270 #define Gv { OP_G, v_mode }
 271 #define Gd { OP_G, d_mode }
 272 #define Gdq { OP_G, dq_mode }
 273 #define Gm { OP_G, m_mode }
 274 #define Gva { OP_G, va_mode }
 275 #define Gw { OP_G, w_mode }
 276 #define Ib { OP_I, b_mode }
 277 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 279 #define Iv { OP_I, v_mode }
 280 #define sIv { OP_sI, v_mode }
 281 #define Iv64 { OP_I64, v_mode }
 282 #define Id { OP_I, d_mode }
 283 #define Iw { OP_I, w_mode }
 284 #define I1 { OP_I, const_1_mode }
 285 #define Jb { OP_J, b_mode }
 286 #define Jv { OP_J, v_mode }
 287 #define Jdqw { OP_J, dqw_mode }
 288 #define Cm { OP_C, m_mode }
 289 #define Dm { OP_D, m_mode }
 290 #define Td { OP_T, d_mode }
 291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 292
 293 #define RMeAX { OP_REG, eAX_reg }
 294 #define RMeBX { OP_REG, eBX_reg }
 295 #define RMeCX { OP_REG, eCX_reg }
 296 #define RMeDX { OP_REG, eDX_reg }
 297 #define RMeSP { OP_REG, eSP_reg }
 298 #define RMeBP { OP_REG, eBP_reg }
 299 #define RMeSI { OP_REG, eSI_reg }
 300 #define RMeDI { OP_REG, eDI_reg }
 301 #define RMrAX { OP_REG, rAX_reg }
 302 #define RMrBX { OP_REG, rBX_reg }
 303 #define RMrCX { OP_REG, rCX_reg }
 304 #define RMrDX { OP_REG, rDX_reg }
 305 #define RMrSP { OP_REG, rSP_reg }
 306 #define RMrBP { OP_REG, rBP_reg }
 307 #define RMrSI { OP_REG, rSI_reg }
 308 #define RMrDI { OP_REG, rDI_reg }
 309 #define RMAL { OP_REG, al_reg }
 310 #define RMCL { OP_REG, cl_reg }
 311 #define RMDL { OP_REG, dl_reg }
 312 #define RMBL { OP_REG, bl_reg }
 313 #define RMAH { OP_REG, ah_reg }
 314 #define RMCH { OP_REG, ch_reg }
 315 #define RMDH { OP_REG, dh_reg }
 316 #define RMBH { OP_REG, bh_reg }
 317 #define RMAX { OP_REG, ax_reg }
 318 #define RMDX { OP_REG, dx_reg }
 319
 320 #define eAX { OP_IMREG, eAX_reg }
 321 #define AL { OP_IMREG, al_reg }
 322 #define CL { OP_IMREG, cl_reg }
 323 #define zAX { OP_IMREG, z_mode_ax_reg }
 324 #define indirDX { OP_IMREG, indir_dx_reg }
 325
 326 #define Sw { OP_SEG, w_mode }
 327 #define Sv { OP_SEG, v_mode }
 328 #define Ap { OP_DIR, 0 }
 329 #define Ob { OP_OFF64, b_mode }
 330 #define Ov { OP_OFF64, v_mode }
 331 #define Xb { OP_DSreg, eSI_reg }
 332 #define Xv { OP_DSreg, eSI_reg }
 333 #define Xz { OP_DSreg, eSI_reg }
 334 #define Yb { OP_ESreg, eDI_reg }
 335 #define Yv { OP_ESreg, eDI_reg }
 336 #define DSBX { OP_DSreg, eBX_reg }
 337
 338 #define es { OP_REG, es_reg }
 339 #define ss { OP_REG, ss_reg }
 340 #define cs { OP_REG, cs_reg }
 341 #define ds { OP_REG, ds_reg }
 342 #define fs { OP_REG, fs_reg }
 343 #define gs { OP_REG, gs_reg }
 344
 345 #define MX { OP_MMX, 0 }
 346 #define XM { OP_XMM, 0 }
 347 #define XMScalar { OP_XMM, scalar_mode }
 348 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 349 #define XMM { OP_XMM, xmm_mode }
 350 #define TMM { OP_XMM, tmm_mode }
 351 #define XMxmmq { OP_XMM, xmmq_mode }
 352 #define EM { OP_EM, v_mode }
 353 #define EMS { OP_EM, v_swap_mode }
 354 #define EMd { OP_EM, d_mode }
 355 #define EMx { OP_EM, x_mode }
 356 #define EXbwUnit { OP_EX, bw_unit_mode }
 357 #define EXw { OP_EX, w_mode }
 358 #define EXd { OP_EX, d_mode }
 359 #define EXdS { OP_EX, d_swap_mode }
 360 #define EXq { OP_EX, q_mode }
 361 #define EXqS { OP_EX, q_swap_mode }
 362 #define EXx { OP_EX, x_mode }
 363 #define EXxS { OP_EX, x_swap_mode }
 364 #define EXxmm { OP_EX, xmm_mode }
 365 #define EXymm { OP_EX, ymm_mode }
 366 #define EXtmm { OP_EX, tmm_mode }
 367 #define EXxmmq { OP_EX, xmmq_mode }
 368 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 369 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 370 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 371 #define EXxmm_md { OP_EX, xmm_md_mode }
 372 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 373 #define EXxmmdw { OP_EX, xmmdw_mode }
 374 #define EXxmmqd { OP_EX, xmmqd_mode }
 375 #define EXymmq { OP_EX, ymmq_mode }
 376 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 377 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 378 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 379 #define MS { OP_MS, v_mode }
 380 #define XS { OP_XS, v_mode }
 381 #define EMCq { OP_EMC, q_mode }
 382 #define MXC { OP_MXC, 0 }
 383 #define OPSUF { OP_3DNowSuffix, 0 }
 384 #define SEP { SEP_Fixup, 0 }
 385 #define CMP { CMP_Fixup, 0 }
 386 #define XMM0 { XMM_Fixup, 0 }
 387 #define FXSAVE { FXSAVE_Fixup, 0 }
 388
 389 #define Vex { OP_VEX, vex_mode }
 390 #define VexW { OP_VexW, vex_mode }
 391 #define VexScalar { OP_VEX, vex_scalar_mode }
 392 #define VexScalarR { OP_VexR, vex_scalar_mode }
 393 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 394 #define VexGdq { OP_VEX, dq_mode }
 395 #define VexTmm { OP_VEX, tmm_mode }
 396 #define XMVexI4 { OP_REG_VexI4, x_mode }
 397 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 398 #define VexI4 { OP_VexI4, 0 }
 399 #define PCLMUL { PCLMUL_Fixup, 0 }
 400 #define VPCMP { VPCMP_Fixup, 0 }
 401 #define VPCOM { VPCOM_Fixup, 0 }
 402
 403 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 404 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 405 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 406
 407 #define XMask { OP_Mask, mask_mode }
 408 #define MaskG { OP_G, mask_mode }
 409 #define MaskE { OP_E, mask_mode }
 410 #define MaskBDE { OP_E, mask_bd_mode }
 411 #define MaskVex { OP_VEX, mask_mode }
 412
 413 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 414 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 415 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 416 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 417
 418 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 419
 420 /* Used handle "rep" prefix for string instructions.  */
 421 #define Xbr { REP_Fixup, eSI_reg }
 422 #define Xvr { REP_Fixup, eSI_reg }
 423 #define Ybr { REP_Fixup, eDI_reg }
 424 #define Yvr { REP_Fixup, eDI_reg }
 425 #define Yzr { REP_Fixup, eDI_reg }
 426 #define indirDXr { REP_Fixup, indir_dx_reg }
 427 #define ALr { REP_Fixup, al_reg }
 428 #define eAXr { REP_Fixup, eAX_reg }
 429
 430 /* Used handle HLE prefix for lockable instructions.  */
 431 #define Ebh1 { HLE_Fixup1, b_mode }
 432 #define Evh1 { HLE_Fixup1, v_mode }
 433 #define Ebh2 { HLE_Fixup2, b_mode }
 434 #define Evh2 { HLE_Fixup2, v_mode }
 435 #define Ebh3 { HLE_Fixup3, b_mode }
 436 #define Evh3 { HLE_Fixup3, v_mode }
 437
 438 #define BND { BND_Fixup, 0 }
 439 #define NOTRACK { NOTRACK_Fixup, 0 }
 440
 441 #define cond_jump_flag { NULL, cond_jump_mode }
 442 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 443
 444 /* bits in sizeflag */
 445 #define SUFFIX_ALWAYS 4
 446 #define AFLAG 2
 447 #define DFLAG 1
 448
 449 enum
 450 {
 451   /* byte operand */
 452   b_mode = 1,
 453   /* byte operand with operand swapped */
 454   b_swap_mode,
 455   /* byte operand, sign extend like 'T' suffix */
 456   b_T_mode,
 457   /* operand size depends on prefixes */
 458   v_mode,
 459   /* operand size depends on prefixes with operand swapped */
 460   v_swap_mode,
 461   /* operand size depends on address prefix */
 462   va_mode,
 463   /* word operand */
 464   w_mode,
 465   /* double word operand  */
 466   d_mode,
 467   /* double word operand with operand swapped */
 468   d_swap_mode,
 469   /* quad word operand */
 470   q_mode,
 471   /* quad word operand with operand swapped */
 472   q_swap_mode,
 473   /* ten-byte operand */
 474   t_mode,
 475   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 476      broadcast enabled.  */
 477   x_mode,
 478   /* Similar to x_mode, but with different EVEX mem shifts.  */
 479   evex_x_gscat_mode,
 480   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 481   bw_unit_mode,
 482   /* Similar to x_mode, but with disabled broadcast.  */
 483   evex_x_nobcst_mode,
 484   /* Similar to x_mode, but with operands swapped and disabled broadcast
 485      in EVEX.  */
 486   x_swap_mode,
 487   /* 16-byte XMM operand */
 488   xmm_mode,
 489   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 490      memory operand (depending on vector length).  Broadcast isn't
 491      allowed.  */
 492   xmmq_mode,
 493   /* Same as xmmq_mode, but broadcast is allowed.  */
 494   evex_half_bcst_xmmq_mode,
 495   /* XMM register or byte memory operand */
 496   xmm_mb_mode,
 497   /* XMM register or word memory operand */
 498   xmm_mw_mode,
 499   /* XMM register or double word memory operand */
 500   xmm_md_mode,
 501   /* XMM register or quad word memory operand */
 502   xmm_mq_mode,
 503   /* 16-byte XMM, word, double word or quad word operand.  */
 504   xmmdw_mode,
 505   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 506   xmmqd_mode,
 507   /* 32-byte YMM operand */
 508   ymm_mode,
 509   /* quad word, ymmword or zmmword memory operand.  */
 510   ymmq_mode,
 511   /* 32-byte YMM or 16-byte word operand */
 512   ymmxmm_mode,
 513   /* TMM operand */
 514   tmm_mode,
 515   /* d_mode in 32bit, q_mode in 64bit mode.  */
 516   m_mode,
 517   /* pair of v_mode operands */
 518   a_mode,
 519   cond_jump_mode,
 520   loop_jcxz_mode,
 521   movsxd_mode,
 522   v_bnd_mode,
 523   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 524   v_bndmk_mode,
 525   /* operand size depends on REX prefixes.  */
 526   dq_mode,
 527   /* registers like dq_mode, memory like w_mode, displacements like
 528      v_mode without considering Intel64 ISA.  */
 529   dqw_mode,
 530   /* bounds operand */
 531   bnd_mode,
 532   /* bounds operand with operand swapped */
 533   bnd_swap_mode,
 534   /* 4- or 6-byte pointer operand */
 535   f_mode,
 536   const_1_mode,
 537   /* v_mode for indirect branch opcodes.  */
 538   indir_v_mode,
 539   /* v_mode for stack-related opcodes.  */
 540   stack_v_mode,
 541   /* non-quad operand size depends on prefixes */
 542   z_mode,
 543   /* 16-byte operand */
 544   o_mode,
 545   /* registers like dq_mode, memory like b_mode.  */
 546   dqb_mode,
 547   /* registers like d_mode, memory like b_mode.  */
 548   db_mode,
 549   /* registers like d_mode, memory like w_mode.  */
 550   dw_mode,
 551   /* registers like dq_mode, memory like d_mode.  */
 552   dqd_mode,
 553   /* normal vex mode */
 554   vex_mode,
 555
 556   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 557   vex_vsib_d_w_dq_mode,
 558   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 559   vex_vsib_d_w_d_mode,
 560   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 561   vex_vsib_q_w_dq_mode,
 562   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 563   vex_vsib_q_w_d_mode,
 564   /* mandatory non-vector SIB.  */
 565   vex_sibmem_mode,
 566
 567   /* scalar, ignore vector length.  */
 568   scalar_mode,
 569   /* like vex_mode, ignore vector length.  */
 570   vex_scalar_mode,
 571   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 572   vex_scalar_w_dq_mode,
 573
 574   /* Static rounding.  */
 575   evex_rounding_mode,
 576   /* Static rounding, 64-bit mode only.  */
 577   evex_rounding_64_mode,
 578   /* Supress all exceptions.  */
 579   evex_sae_mode,
 580
 581   /* Mask register operand.  */
 582   mask_mode,
 583   /* Mask register operand.  */
 584   mask_bd_mode,
 585
 586   es_reg,
 587   cs_reg,
 588   ss_reg,
 589   ds_reg,
 590   fs_reg,
 591   gs_reg,
 592
 593   eAX_reg,
 594   eCX_reg,
 595   eDX_reg,
 596   eBX_reg,
 597   eSP_reg,
 598   eBP_reg,
 599   eSI_reg,
 600   eDI_reg,
 601
 602   al_reg,
 603   cl_reg,
 604   dl_reg,
 605   bl_reg,
 606   ah_reg,
 607   ch_reg,
 608   dh_reg,
 609   bh_reg,
 610
 611   ax_reg,
 612   cx_reg,
 613   dx_reg,
 614   bx_reg,
 615   sp_reg,
 616   bp_reg,
 617   si_reg,
 618   di_reg,
 619
 620   rAX_reg,
 621   rCX_reg,
 622   rDX_reg,
 623   rBX_reg,
 624   rSP_reg,
 625   rBP_reg,
 626   rSI_reg,
 627   rDI_reg,
 628
 629   z_mode_ax_reg,
 630   indir_dx_reg
 631 };
 632
 633 enum
 634 {
 635   FLOATCODE = 1,
 636   USE_REG_TABLE,
 637   USE_MOD_TABLE,
 638   USE_RM_TABLE,
 639   USE_PREFIX_TABLE,
 640   USE_X86_64_TABLE,
 641   USE_3BYTE_TABLE,
 642   USE_XOP_8F_TABLE,
 643   USE_VEX_C4_TABLE,
 644   USE_VEX_C5_TABLE,
 645   USE_VEX_LEN_TABLE,
 646   USE_VEX_W_TABLE,
 647   USE_EVEX_TABLE,
 648   USE_EVEX_LEN_TABLE
 649 };
 650
 651 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 652
 653 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 654 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 655 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 656 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 657 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 658 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 659 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 660 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 661 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 662 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 663 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 664 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 665 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 666 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 667 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 668 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 669
 670 enum
 671 {
 672   REG_80 = 0,
 673   REG_81,
 674   REG_83,
 675   REG_8F,
 676   REG_C0,
 677   REG_C1,
 678   REG_C6,
 679   REG_C7,
 680   REG_D0,
 681   REG_D1,
 682   REG_D2,
 683   REG_D3,
 684   REG_F6,
 685   REG_F7,
 686   REG_FE,
 687   REG_FF,
 688   REG_0F00,
 689   REG_0F01,
 690   REG_0F0D,
 691   REG_0F18,
 692   REG_0F1C_P_0_MOD_0,
 693   REG_0F1E_P_1_MOD_3,
 694   REG_0F38D8_PREFIX_1,
 695   REG_0F3A0F_PREFIX_1_MOD_3,
 696   REG_0F71,
 697   REG_0F72,
 698   REG_0F73,
 699   REG_0FA6,
 700   REG_0FA7,
 701   REG_0FAE,
 702   REG_0FBA,
 703   REG_0FC7,
 704   REG_VEX_0F71,
 705   REG_VEX_0F72,
 706   REG_VEX_0F73,
 707   REG_VEX_0FAE,
 708   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 709   REG_VEX_0F38F3,
 710
 711   REG_0FXOP_09_01_L_0,
 712   REG_0FXOP_09_02_L_0,
 713   REG_0FXOP_09_12_M_1_L_0,
 714   REG_0FXOP_0A_12_L_0,
 715
 716   REG_EVEX_0F71,
 717   REG_EVEX_0F72,
 718   REG_EVEX_0F73,
 719   REG_EVEX_0F38C6,
 720   REG_EVEX_0F38C7
 721 };
 722
 723 enum
 724 {
 725   MOD_8D = 0,
 726   MOD_C6_REG_7,
 727   MOD_C7_REG_7,
 728   MOD_FF_REG_3,
 729   MOD_FF_REG_5,
 730   MOD_0F01_REG_0,
 731   MOD_0F01_REG_1,
 732   MOD_0F01_REG_2,
 733   MOD_0F01_REG_3,
 734   MOD_0F01_REG_5,
 735   MOD_0F01_REG_7,
 736   MOD_0F12_PREFIX_0,
 737   MOD_0F12_PREFIX_2,
 738   MOD_0F13,
 739   MOD_0F16_PREFIX_0,
 740   MOD_0F16_PREFIX_2,
 741   MOD_0F17,
 742   MOD_0F18_REG_0,
 743   MOD_0F18_REG_1,
 744   MOD_0F18_REG_2,
 745   MOD_0F18_REG_3,
 746   MOD_0F18_REG_4,
 747   MOD_0F18_REG_5,
 748   MOD_0F18_REG_6,
 749   MOD_0F18_REG_7,
 750   MOD_0F1A_PREFIX_0,
 751   MOD_0F1B_PREFIX_0,
 752   MOD_0F1B_PREFIX_1,
 753   MOD_0F1C_PREFIX_0,
 754   MOD_0F1E_PREFIX_1,
 755   MOD_0F2B_PREFIX_0,
 756   MOD_0F2B_PREFIX_1,
 757   MOD_0F2B_PREFIX_2,
 758   MOD_0F2B_PREFIX_3,
 759   MOD_0F50,
 760   MOD_0F71_REG_2,
 761   MOD_0F71_REG_4,
 762   MOD_0F71_REG_6,
 763   MOD_0F72_REG_2,
 764   MOD_0F72_REG_4,
 765   MOD_0F72_REG_6,
 766   MOD_0F73_REG_2,
 767   MOD_0F73_REG_3,
 768   MOD_0F73_REG_6,
 769   MOD_0F73_REG_7,
 770   MOD_0FAE_REG_0,
 771   MOD_0FAE_REG_1,
 772   MOD_0FAE_REG_2,
 773   MOD_0FAE_REG_3,
 774   MOD_0FAE_REG_4,
 775   MOD_0FAE_REG_5,
 776   MOD_0FAE_REG_6,
 777   MOD_0FAE_REG_7,
 778   MOD_0FB2,
 779   MOD_0FB4,
 780   MOD_0FB5,
 781   MOD_0FC3,
 782   MOD_0FC7_REG_3,
 783   MOD_0FC7_REG_4,
 784   MOD_0FC7_REG_5,
 785   MOD_0FC7_REG_6,
 786   MOD_0FC7_REG_7,
 787   MOD_0FD7,
 788   MOD_0FE7_PREFIX_2,
 789   MOD_0FF0_PREFIX_3,
 790   MOD_0F382A,
 791   MOD_0F38DC_PREFIX_1,
 792   MOD_0F38DD_PREFIX_1,
 793   MOD_0F38DE_PREFIX_1,
 794   MOD_0F38DF_PREFIX_1,
 795   MOD_0F38F5,
 796   MOD_0F38F6_PREFIX_0,
 797   MOD_0F38F8_PREFIX_1,
 798   MOD_0F38F8_PREFIX_2,
 799   MOD_0F38F8_PREFIX_3,
 800   MOD_0F38F9,
 801   MOD_0F38FA_PREFIX_1,
 802   MOD_0F38FB_PREFIX_1,
 803   MOD_0F3A0F_PREFIX_1,
 804   MOD_62_32BIT,
 805   MOD_C4_32BIT,
 806   MOD_C5_32BIT,
 807   MOD_VEX_0F12_PREFIX_0,
 808   MOD_VEX_0F12_PREFIX_2,
 809   MOD_VEX_0F13,
 810   MOD_VEX_0F16_PREFIX_0,
 811   MOD_VEX_0F16_PREFIX_2,
 812   MOD_VEX_0F17,
 813   MOD_VEX_0F2B,
 814   MOD_VEX_W_0_0F41_P_0_LEN_1,
 815   MOD_VEX_W_1_0F41_P_0_LEN_1,
 816   MOD_VEX_W_0_0F41_P_2_LEN_1,
 817   MOD_VEX_W_1_0F41_P_2_LEN_1,
 818   MOD_VEX_W_0_0F42_P_0_LEN_1,
 819   MOD_VEX_W_1_0F42_P_0_LEN_1,
 820   MOD_VEX_W_0_0F42_P_2_LEN_1,
 821   MOD_VEX_W_1_0F42_P_2_LEN_1,
 822   MOD_VEX_W_0_0F44_P_0_LEN_1,
 823   MOD_VEX_W_1_0F44_P_0_LEN_1,
 824   MOD_VEX_W_0_0F44_P_2_LEN_1,
 825   MOD_VEX_W_1_0F44_P_2_LEN_1,
 826   MOD_VEX_W_0_0F45_P_0_LEN_1,
 827   MOD_VEX_W_1_0F45_P_0_LEN_1,
 828   MOD_VEX_W_0_0F45_P_2_LEN_1,
 829   MOD_VEX_W_1_0F45_P_2_LEN_1,
 830   MOD_VEX_W_0_0F46_P_0_LEN_1,
 831   MOD_VEX_W_1_0F46_P_0_LEN_1,
 832   MOD_VEX_W_0_0F46_P_2_LEN_1,
 833   MOD_VEX_W_1_0F46_P_2_LEN_1,
 834   MOD_VEX_W_0_0F47_P_0_LEN_1,
 835   MOD_VEX_W_1_0F47_P_0_LEN_1,
 836   MOD_VEX_W_0_0F47_P_2_LEN_1,
 837   MOD_VEX_W_1_0F47_P_2_LEN_1,
 838   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 839   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 840   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 841   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 842   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 843   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 844   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 845   MOD_VEX_0F50,
 846   MOD_VEX_0F71_REG_2,
 847   MOD_VEX_0F71_REG_4,
 848   MOD_VEX_0F71_REG_6,
 849   MOD_VEX_0F72_REG_2,
 850   MOD_VEX_0F72_REG_4,
 851   MOD_VEX_0F72_REG_6,
 852   MOD_VEX_0F73_REG_2,
 853   MOD_VEX_0F73_REG_3,
 854   MOD_VEX_0F73_REG_6,
 855   MOD_VEX_0F73_REG_7,
 856   MOD_VEX_W_0_0F91_P_0_LEN_0,
 857   MOD_VEX_W_1_0F91_P_0_LEN_0,
 858   MOD_VEX_W_0_0F91_P_2_LEN_0,
 859   MOD_VEX_W_1_0F91_P_2_LEN_0,
 860   MOD_VEX_W_0_0F92_P_0_LEN_0,
 861   MOD_VEX_W_0_0F92_P_2_LEN_0,
 862   MOD_VEX_0F92_P_3_LEN_0,
 863   MOD_VEX_W_0_0F93_P_0_LEN_0,
 864   MOD_VEX_W_0_0F93_P_2_LEN_0,
 865   MOD_VEX_0F93_P_3_LEN_0,
 866   MOD_VEX_W_0_0F98_P_0_LEN_0,
 867   MOD_VEX_W_1_0F98_P_0_LEN_0,
 868   MOD_VEX_W_0_0F98_P_2_LEN_0,
 869   MOD_VEX_W_1_0F98_P_2_LEN_0,
 870   MOD_VEX_W_0_0F99_P_0_LEN_0,
 871   MOD_VEX_W_1_0F99_P_0_LEN_0,
 872   MOD_VEX_W_0_0F99_P_2_LEN_0,
 873   MOD_VEX_W_1_0F99_P_2_LEN_0,
 874   MOD_VEX_0FAE_REG_2,
 875   MOD_VEX_0FAE_REG_3,
 876   MOD_VEX_0FD7,
 877   MOD_VEX_0FE7,
 878   MOD_VEX_0FF0_PREFIX_3,
 879   MOD_VEX_0F381A,
 880   MOD_VEX_0F382A,
 881   MOD_VEX_0F382C,
 882   MOD_VEX_0F382D,
 883   MOD_VEX_0F382E,
 884   MOD_VEX_0F382F,
 885   MOD_VEX_0F3849_X86_64_P_0_W_0,
 886   MOD_VEX_0F3849_X86_64_P_2_W_0,
 887   MOD_VEX_0F3849_X86_64_P_3_W_0,
 888   MOD_VEX_0F384B_X86_64_P_1_W_0,
 889   MOD_VEX_0F384B_X86_64_P_2_W_0,
 890   MOD_VEX_0F384B_X86_64_P_3_W_0,
 891   MOD_VEX_0F385A,
 892   MOD_VEX_0F385C_X86_64_P_1_W_0,
 893   MOD_VEX_0F385E_X86_64_P_0_W_0,
 894   MOD_VEX_0F385E_X86_64_P_1_W_0,
 895   MOD_VEX_0F385E_X86_64_P_2_W_0,
 896   MOD_VEX_0F385E_X86_64_P_3_W_0,
 897   MOD_VEX_0F388C,
 898   MOD_VEX_0F388E,
 899   MOD_VEX_0F3A30_L_0,
 900   MOD_VEX_0F3A31_L_0,
 901   MOD_VEX_0F3A32_L_0,
 902   MOD_VEX_0F3A33_L_0,
 903
 904   MOD_VEX_0FXOP_09_12,
 905
 906   MOD_EVEX_0F12_PREFIX_0,
 907   MOD_EVEX_0F12_PREFIX_2,
 908   MOD_EVEX_0F13,
 909   MOD_EVEX_0F16_PREFIX_0,
 910   MOD_EVEX_0F16_PREFIX_2,
 911   MOD_EVEX_0F17,
 912   MOD_EVEX_0F2B,
 913   MOD_EVEX_0F381A_W_0,
 914   MOD_EVEX_0F381A_W_1,
 915   MOD_EVEX_0F381B_W_0,
 916   MOD_EVEX_0F381B_W_1,
 917   MOD_EVEX_0F3828_P_1,
 918   MOD_EVEX_0F382A_P_1_W_1,
 919   MOD_EVEX_0F3838_P_1,
 920   MOD_EVEX_0F383A_P_1_W_0,
 921   MOD_EVEX_0F385A_W_0,
 922   MOD_EVEX_0F385A_W_1,
 923   MOD_EVEX_0F385B_W_0,
 924   MOD_EVEX_0F385B_W_1,
 925   MOD_EVEX_0F387A_W_0,
 926   MOD_EVEX_0F387B_W_0,
 927   MOD_EVEX_0F387C,
 928   MOD_EVEX_0F38C6_REG_1,
 929   MOD_EVEX_0F38C6_REG_2,
 930   MOD_EVEX_0F38C6_REG_5,
 931   MOD_EVEX_0F38C6_REG_6,
 932   MOD_EVEX_0F38C7_REG_1,
 933   MOD_EVEX_0F38C7_REG_2,
 934   MOD_EVEX_0F38C7_REG_5,
 935   MOD_EVEX_0F38C7_REG_6
 936 };
 937
 938 enum
 939 {
 940   RM_C6_REG_7 = 0,
 941   RM_C7_REG_7,
 942   RM_0F01_REG_0,
 943   RM_0F01_REG_1,
 944   RM_0F01_REG_2,
 945   RM_0F01_REG_3,
 946   RM_0F01_REG_5_MOD_3,
 947   RM_0F01_REG_7_MOD_3,
 948   RM_0F1E_P_1_MOD_3_REG_7,
 949   RM_0F3A0F_P_1_MOD_3_REG_0,
 950   RM_0FAE_REG_6_MOD_3_P_0,
 951   RM_0FAE_REG_7_MOD_3,
 952   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 953 };
 954
 955 enum
 956 {
 957   PREFIX_90 = 0,
 958   PREFIX_0F01_REG_1_RM_4,
 959   PREFIX_0F01_REG_1_RM_5,
 960   PREFIX_0F01_REG_1_RM_6,
 961   PREFIX_0F01_REG_1_RM_7,
 962   PREFIX_0F01_REG_3_RM_1,
 963   PREFIX_0F01_REG_5_MOD_0,
 964   PREFIX_0F01_REG_5_MOD_3_RM_0,
 965   PREFIX_0F01_REG_5_MOD_3_RM_1,
 966   PREFIX_0F01_REG_5_MOD_3_RM_2,
 967   PREFIX_0F01_REG_5_MOD_3_RM_4,
 968   PREFIX_0F01_REG_5_MOD_3_RM_5,
 969   PREFIX_0F01_REG_5_MOD_3_RM_6,
 970   PREFIX_0F01_REG_5_MOD_3_RM_7,
 971   PREFIX_0F01_REG_7_MOD_3_RM_2,
 972   PREFIX_0F09,
 973   PREFIX_0F10,
 974   PREFIX_0F11,
 975   PREFIX_0F12,
 976   PREFIX_0F16,
 977   PREFIX_0F1A,
 978   PREFIX_0F1B,
 979   PREFIX_0F1C,
 980   PREFIX_0F1E,
 981   PREFIX_0F2A,
 982   PREFIX_0F2B,
 983   PREFIX_0F2C,
 984   PREFIX_0F2D,
 985   PREFIX_0F2E,
 986   PREFIX_0F2F,
 987   PREFIX_0F51,
 988   PREFIX_0F52,
 989   PREFIX_0F53,
 990   PREFIX_0F58,
 991   PREFIX_0F59,
 992   PREFIX_0F5A,
 993   PREFIX_0F5B,
 994   PREFIX_0F5C,
 995   PREFIX_0F5D,
 996   PREFIX_0F5E,
 997   PREFIX_0F5F,
 998   PREFIX_0F60,
 999   PREFIX_0F61,
1000   PREFIX_0F62,
1001   PREFIX_0F6F,
1002   PREFIX_0F70,
1003   PREFIX_0F78,
1004   PREFIX_0F79,
1005   PREFIX_0F7C,
1006   PREFIX_0F7D,
1007   PREFIX_0F7E,
1008   PREFIX_0F7F,
1009   PREFIX_0FAE_REG_0_MOD_3,
1010   PREFIX_0FAE_REG_1_MOD_3,
1011   PREFIX_0FAE_REG_2_MOD_3,
1012   PREFIX_0FAE_REG_3_MOD_3,
1013   PREFIX_0FAE_REG_4_MOD_0,
1014   PREFIX_0FAE_REG_4_MOD_3,
1015   PREFIX_0FAE_REG_5_MOD_3,
1016   PREFIX_0FAE_REG_6_MOD_0,
1017   PREFIX_0FAE_REG_6_MOD_3,
1018   PREFIX_0FAE_REG_7_MOD_0,
1019   PREFIX_0FB8,
1020   PREFIX_0FBC,
1021   PREFIX_0FBD,
1022   PREFIX_0FC2,
1023   PREFIX_0FC7_REG_6_MOD_0,
1024   PREFIX_0FC7_REG_6_MOD_3,
1025   PREFIX_0FC7_REG_7_MOD_3,
1026   PREFIX_0FD0,
1027   PREFIX_0FD6,
1028   PREFIX_0FE6,
1029   PREFIX_0FE7,
1030   PREFIX_0FF0,
1031   PREFIX_0FF7,
1032   PREFIX_0F38D8,
1033   PREFIX_0F38DC,
1034   PREFIX_0F38DD,
1035   PREFIX_0F38DE,
1036   PREFIX_0F38DF,
1037   PREFIX_0F38F0,
1038   PREFIX_0F38F1,
1039   PREFIX_0F38F6,
1040   PREFIX_0F38F8,
1041   PREFIX_0F38FA,
1042   PREFIX_0F38FB,
1043   PREFIX_0F3A0F,
1044   PREFIX_VEX_0F10,
1045   PREFIX_VEX_0F11,
1046   PREFIX_VEX_0F12,
1047   PREFIX_VEX_0F16,
1048   PREFIX_VEX_0F2A,
1049   PREFIX_VEX_0F2C,
1050   PREFIX_VEX_0F2D,
1051   PREFIX_VEX_0F2E,
1052   PREFIX_VEX_0F2F,
1053   PREFIX_VEX_0F41,
1054   PREFIX_VEX_0F42,
1055   PREFIX_VEX_0F44,
1056   PREFIX_VEX_0F45,
1057   PREFIX_VEX_0F46,
1058   PREFIX_VEX_0F47,
1059   PREFIX_VEX_0F4A,
1060   PREFIX_VEX_0F4B,
1061   PREFIX_VEX_0F51,
1062   PREFIX_VEX_0F52,
1063   PREFIX_VEX_0F53,
1064   PREFIX_VEX_0F58,
1065   PREFIX_VEX_0F59,
1066   PREFIX_VEX_0F5A,
1067   PREFIX_VEX_0F5B,
1068   PREFIX_VEX_0F5C,
1069   PREFIX_VEX_0F5D,
1070   PREFIX_VEX_0F5E,
1071   PREFIX_VEX_0F5F,
1072   PREFIX_VEX_0F6F,
1073   PREFIX_VEX_0F70,
1074   PREFIX_VEX_0F7C,
1075   PREFIX_VEX_0F7D,
1076   PREFIX_VEX_0F7E,
1077   PREFIX_VEX_0F7F,
1078   PREFIX_VEX_0F90,
1079   PREFIX_VEX_0F91,
1080   PREFIX_VEX_0F92,
1081   PREFIX_VEX_0F93,
1082   PREFIX_VEX_0F98,
1083   PREFIX_VEX_0F99,
1084   PREFIX_VEX_0FC2,
1085   PREFIX_VEX_0FD0,
1086   PREFIX_VEX_0FE6,
1087   PREFIX_VEX_0FF0,
1088   PREFIX_VEX_0F3849_X86_64,
1089   PREFIX_VEX_0F384B_X86_64,
1090   PREFIX_VEX_0F385C_X86_64,
1091   PREFIX_VEX_0F385E_X86_64,
1092   PREFIX_VEX_0F38F5,
1093   PREFIX_VEX_0F38F6,
1094   PREFIX_VEX_0F38F7,
1095   PREFIX_VEX_0F3AF0,
1096
1097   PREFIX_EVEX_0F10,
1098   PREFIX_EVEX_0F11,
1099   PREFIX_EVEX_0F12,
1100   PREFIX_EVEX_0F16,
1101   PREFIX_EVEX_0F2A,
1102   PREFIX_EVEX_0F51,
1103   PREFIX_EVEX_0F58,
1104   PREFIX_EVEX_0F59,
1105   PREFIX_EVEX_0F5A,
1106   PREFIX_EVEX_0F5B,
1107   PREFIX_EVEX_0F5C,
1108   PREFIX_EVEX_0F5D,
1109   PREFIX_EVEX_0F5E,
1110   PREFIX_EVEX_0F5F,
1111   PREFIX_EVEX_0F6F,
1112   PREFIX_EVEX_0F70,
1113   PREFIX_EVEX_0F78,
1114   PREFIX_EVEX_0F79,
1115   PREFIX_EVEX_0F7A,
1116   PREFIX_EVEX_0F7B,
1117   PREFIX_EVEX_0F7E,
1118   PREFIX_EVEX_0F7F,
1119   PREFIX_EVEX_0FC2,
1120   PREFIX_EVEX_0FE6,
1121   PREFIX_EVEX_0F3810,
1122   PREFIX_EVEX_0F3811,
1123   PREFIX_EVEX_0F3812,
1124   PREFIX_EVEX_0F3813,
1125   PREFIX_EVEX_0F3814,
1126   PREFIX_EVEX_0F3815,
1127   PREFIX_EVEX_0F3820,
1128   PREFIX_EVEX_0F3821,
1129   PREFIX_EVEX_0F3822,
1130   PREFIX_EVEX_0F3823,
1131   PREFIX_EVEX_0F3824,
1132   PREFIX_EVEX_0F3825,
1133   PREFIX_EVEX_0F3826,
1134   PREFIX_EVEX_0F3827,
1135   PREFIX_EVEX_0F3828,
1136   PREFIX_EVEX_0F3829,
1137   PREFIX_EVEX_0F382A,
1138   PREFIX_EVEX_0F3830,
1139   PREFIX_EVEX_0F3831,
1140   PREFIX_EVEX_0F3832,
1141   PREFIX_EVEX_0F3833,
1142   PREFIX_EVEX_0F3834,
1143   PREFIX_EVEX_0F3835,
1144   PREFIX_EVEX_0F3838,
1145   PREFIX_EVEX_0F3839,
1146   PREFIX_EVEX_0F383A,
1147   PREFIX_EVEX_0F3852,
1148   PREFIX_EVEX_0F3853,
1149   PREFIX_EVEX_0F3868,
1150   PREFIX_EVEX_0F3872,
1151   PREFIX_EVEX_0F389A,
1152   PREFIX_EVEX_0F389B,
1153   PREFIX_EVEX_0F38AA,
1154   PREFIX_EVEX_0F38AB,
1155 };
1156
1157 enum
1158 {
1159   X86_64_06 = 0,
1160   X86_64_07,
1161   X86_64_0E,
1162   X86_64_16,
1163   X86_64_17,
1164   X86_64_1E,
1165   X86_64_1F,
1166   X86_64_27,
1167   X86_64_2F,
1168   X86_64_37,
1169   X86_64_3F,
1170   X86_64_60,
1171   X86_64_61,
1172   X86_64_62,
1173   X86_64_63,
1174   X86_64_6D,
1175   X86_64_6F,
1176   X86_64_82,
1177   X86_64_9A,
1178   X86_64_C2,
1179   X86_64_C3,
1180   X86_64_C4,
1181   X86_64_C5,
1182   X86_64_CE,
1183   X86_64_D4,
1184   X86_64_D5,
1185   X86_64_E8,
1186   X86_64_E9,
1187   X86_64_EA,
1188   X86_64_0F01_REG_0,
1189   X86_64_0F01_REG_1,
1190   X86_64_0F01_REG_1_RM_5_PREFIX_2,
1191   X86_64_0F01_REG_1_RM_6_PREFIX_2,
1192   X86_64_0F01_REG_1_RM_7_PREFIX_2,
1193   X86_64_0F01_REG_2,
1194   X86_64_0F01_REG_3,
1195   X86_64_0F24,
1196   X86_64_0F26,
1197   X86_64_VEX_0F3849,
1198   X86_64_VEX_0F384B,
1199   X86_64_VEX_0F385C,
1200   X86_64_VEX_0F385E,
1201   X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1202   X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1203   X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1204   X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1205   X86_64_0FC7_REG_6_MOD_3_PREFIX_1
1206 };
1207
1208 enum
1209 {
1210   THREE_BYTE_0F38 = 0,
1211   THREE_BYTE_0F3A
1212 };
1213
1214 enum
1215 {
1216   XOP_08 = 0,
1217   XOP_09,
1218   XOP_0A
1219 };
1220
1221 enum
1222 {
1223   VEX_0F = 0,
1224   VEX_0F38,
1225   VEX_0F3A
1226 };
1227
1228 enum
1229 {
1230   EVEX_0F = 0,
1231   EVEX_0F38,
1232   EVEX_0F3A
1233 };
1234
1235 enum
1236 {
1237   VEX_LEN_0F12_P_0_M_0 = 0,
1238   VEX_LEN_0F12_P_0_M_1,
1239 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1240   VEX_LEN_0F13_M_0,
1241   VEX_LEN_0F16_P_0_M_0,
1242   VEX_LEN_0F16_P_0_M_1,
1243 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1244   VEX_LEN_0F17_M_0,
1245   VEX_LEN_0F41_P_0,
1246   VEX_LEN_0F41_P_2,
1247   VEX_LEN_0F42_P_0,
1248   VEX_LEN_0F42_P_2,
1249   VEX_LEN_0F44_P_0,
1250   VEX_LEN_0F44_P_2,
1251   VEX_LEN_0F45_P_0,
1252   VEX_LEN_0F45_P_2,
1253   VEX_LEN_0F46_P_0,
1254   VEX_LEN_0F46_P_2,
1255   VEX_LEN_0F47_P_0,
1256   VEX_LEN_0F47_P_2,
1257   VEX_LEN_0F4A_P_0,
1258   VEX_LEN_0F4A_P_2,
1259   VEX_LEN_0F4B_P_0,
1260   VEX_LEN_0F4B_P_2,
1261   VEX_LEN_0F6E,
1262   VEX_LEN_0F77,
1263   VEX_LEN_0F7E_P_1,
1264   VEX_LEN_0F7E_P_2,
1265   VEX_LEN_0F90_P_0,
1266   VEX_LEN_0F90_P_2,
1267   VEX_LEN_0F91_P_0,
1268   VEX_LEN_0F91_P_2,
1269   VEX_LEN_0F92_P_0,
1270   VEX_LEN_0F92_P_2,
1271   VEX_LEN_0F92_P_3,
1272   VEX_LEN_0F93_P_0,
1273   VEX_LEN_0F93_P_2,
1274   VEX_LEN_0F93_P_3,
1275   VEX_LEN_0F98_P_0,
1276   VEX_LEN_0F98_P_2,
1277   VEX_LEN_0F99_P_0,
1278   VEX_LEN_0F99_P_2,
1279   VEX_LEN_0FAE_R_2_M_0,
1280   VEX_LEN_0FAE_R_3_M_0,
1281   VEX_LEN_0FC4,
1282   VEX_LEN_0FC5,
1283   VEX_LEN_0FD6,
1284   VEX_LEN_0FF7,
1285   VEX_LEN_0F3816,
1286   VEX_LEN_0F3819,
1287   VEX_LEN_0F381A_M_0,
1288   VEX_LEN_0F3836,
1289   VEX_LEN_0F3841,
1290   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1291   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1292   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1293   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1294   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1295   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1296   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1297   VEX_LEN_0F385A_M_0,
1298   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1299   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1300   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1301   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1302   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1303   VEX_LEN_0F38DB,
1304   VEX_LEN_0F38F2,
1305   VEX_LEN_0F38F3_R_1,
1306   VEX_LEN_0F38F3_R_2,
1307   VEX_LEN_0F38F3_R_3,
1308   VEX_LEN_0F38F5_P_0,
1309   VEX_LEN_0F38F5_P_1,
1310   VEX_LEN_0F38F5_P_3,
1311   VEX_LEN_0F38F6_P_3,
1312   VEX_LEN_0F38F7_P_0,
1313   VEX_LEN_0F38F7_P_1,
1314   VEX_LEN_0F38F7_P_2,
1315   VEX_LEN_0F38F7_P_3,
1316   VEX_LEN_0F3A00,
1317   VEX_LEN_0F3A01,
1318   VEX_LEN_0F3A06,
1319   VEX_LEN_0F3A14,
1320   VEX_LEN_0F3A15,
1321   VEX_LEN_0F3A16,
1322   VEX_LEN_0F3A17,
1323   VEX_LEN_0F3A18,
1324   VEX_LEN_0F3A19,
1325   VEX_LEN_0F3A20,
1326   VEX_LEN_0F3A21,
1327   VEX_LEN_0F3A22,
1328   VEX_LEN_0F3A30,
1329   VEX_LEN_0F3A31,
1330   VEX_LEN_0F3A32,
1331   VEX_LEN_0F3A33,
1332   VEX_LEN_0F3A38,
1333   VEX_LEN_0F3A39,
1334   VEX_LEN_0F3A41,
1335   VEX_LEN_0F3A46,
1336   VEX_LEN_0F3A60,
1337   VEX_LEN_0F3A61,
1338   VEX_LEN_0F3A62,
1339   VEX_LEN_0F3A63,
1340   VEX_LEN_0F3ADF,
1341   VEX_LEN_0F3AF0_P_3,
1342   VEX_LEN_0FXOP_08_85,
1343   VEX_LEN_0FXOP_08_86,
1344   VEX_LEN_0FXOP_08_87,
1345   VEX_LEN_0FXOP_08_8E,
1346   VEX_LEN_0FXOP_08_8F,
1347   VEX_LEN_0FXOP_08_95,
1348   VEX_LEN_0FXOP_08_96,
1349   VEX_LEN_0FXOP_08_97,
1350   VEX_LEN_0FXOP_08_9E,
1351   VEX_LEN_0FXOP_08_9F,
1352   VEX_LEN_0FXOP_08_A3,
1353   VEX_LEN_0FXOP_08_A6,
1354   VEX_LEN_0FXOP_08_B6,
1355   VEX_LEN_0FXOP_08_C0,
1356   VEX_LEN_0FXOP_08_C1,
1357   VEX_LEN_0FXOP_08_C2,
1358   VEX_LEN_0FXOP_08_C3,
1359   VEX_LEN_0FXOP_08_CC,
1360   VEX_LEN_0FXOP_08_CD,
1361   VEX_LEN_0FXOP_08_CE,
1362   VEX_LEN_0FXOP_08_CF,
1363   VEX_LEN_0FXOP_08_EC,
1364   VEX_LEN_0FXOP_08_ED,
1365   VEX_LEN_0FXOP_08_EE,
1366   VEX_LEN_0FXOP_08_EF,
1367   VEX_LEN_0FXOP_09_01,
1368   VEX_LEN_0FXOP_09_02,
1369   VEX_LEN_0FXOP_09_12_M_1,
1370   VEX_LEN_0FXOP_09_82_W_0,
1371   VEX_LEN_0FXOP_09_83_W_0,
1372   VEX_LEN_0FXOP_09_90,
1373   VEX_LEN_0FXOP_09_91,
1374   VEX_LEN_0FXOP_09_92,
1375   VEX_LEN_0FXOP_09_93,
1376   VEX_LEN_0FXOP_09_94,
1377   VEX_LEN_0FXOP_09_95,
1378   VEX_LEN_0FXOP_09_96,
1379   VEX_LEN_0FXOP_09_97,
1380   VEX_LEN_0FXOP_09_98,
1381   VEX_LEN_0FXOP_09_99,
1382   VEX_LEN_0FXOP_09_9A,
1383   VEX_LEN_0FXOP_09_9B,
1384   VEX_LEN_0FXOP_09_C1,
1385   VEX_LEN_0FXOP_09_C2,
1386   VEX_LEN_0FXOP_09_C3,
1387   VEX_LEN_0FXOP_09_C6,
1388   VEX_LEN_0FXOP_09_C7,
1389   VEX_LEN_0FXOP_09_CB,
1390   VEX_LEN_0FXOP_09_D1,
1391   VEX_LEN_0FXOP_09_D2,
1392   VEX_LEN_0FXOP_09_D3,
1393   VEX_LEN_0FXOP_09_D6,
1394   VEX_LEN_0FXOP_09_D7,
1395   VEX_LEN_0FXOP_09_DB,
1396   VEX_LEN_0FXOP_09_E1,
1397   VEX_LEN_0FXOP_09_E2,
1398   VEX_LEN_0FXOP_09_E3,
1399   VEX_LEN_0FXOP_0A_12,
1400 };
1401
1402 enum
1403 {
1404   EVEX_LEN_0F6E = 0,
1405   EVEX_LEN_0F7E_P_1,
1406   EVEX_LEN_0F7E_P_2,
1407   EVEX_LEN_0FC4,
1408   EVEX_LEN_0FC5,
1409   EVEX_LEN_0FD6,
1410   EVEX_LEN_0F3816,
1411   EVEX_LEN_0F3819_W_0,
1412   EVEX_LEN_0F3819_W_1,
1413   EVEX_LEN_0F381A_W_0_M_0,
1414   EVEX_LEN_0F381A_W_1_M_0,
1415   EVEX_LEN_0F381B_W_0_M_0,
1416   EVEX_LEN_0F381B_W_1_M_0,
1417   EVEX_LEN_0F3836,
1418   EVEX_LEN_0F385A_W_0_M_0,
1419   EVEX_LEN_0F385A_W_1_M_0,
1420   EVEX_LEN_0F385B_W_0_M_0,
1421   EVEX_LEN_0F385B_W_1_M_0,
1422   EVEX_LEN_0F38C6_R_1_M_0,
1423   EVEX_LEN_0F38C6_R_2_M_0,
1424   EVEX_LEN_0F38C6_R_5_M_0,
1425   EVEX_LEN_0F38C6_R_6_M_0,
1426   EVEX_LEN_0F38C7_R_1_M_0_W_0,
1427   EVEX_LEN_0F38C7_R_1_M_0_W_1,
1428   EVEX_LEN_0F38C7_R_2_M_0_W_0,
1429   EVEX_LEN_0F38C7_R_2_M_0_W_1,
1430   EVEX_LEN_0F38C7_R_5_M_0_W_0,
1431   EVEX_LEN_0F38C7_R_5_M_0_W_1,
1432   EVEX_LEN_0F38C7_R_6_M_0_W_0,
1433   EVEX_LEN_0F38C7_R_6_M_0_W_1,
1434   EVEX_LEN_0F3A00_W_1,
1435   EVEX_LEN_0F3A01_W_1,
1436   EVEX_LEN_0F3A14,
1437   EVEX_LEN_0F3A15,
1438   EVEX_LEN_0F3A16,
1439   EVEX_LEN_0F3A17,
1440   EVEX_LEN_0F3A18_W_0,
1441   EVEX_LEN_0F3A18_W_1,
1442   EVEX_LEN_0F3A19_W_0,
1443   EVEX_LEN_0F3A19_W_1,
1444   EVEX_LEN_0F3A1A_W_0,
1445   EVEX_LEN_0F3A1A_W_1,
1446   EVEX_LEN_0F3A1B_W_0,
1447   EVEX_LEN_0F3A1B_W_1,
1448   EVEX_LEN_0F3A20,
1449   EVEX_LEN_0F3A21_W_0,
1450   EVEX_LEN_0F3A22,
1451   EVEX_LEN_0F3A23_W_0,
1452   EVEX_LEN_0F3A23_W_1,
1453   EVEX_LEN_0F3A38_W_0,
1454   EVEX_LEN_0F3A38_W_1,
1455   EVEX_LEN_0F3A39_W_0,
1456   EVEX_LEN_0F3A39_W_1,
1457   EVEX_LEN_0F3A3A_W_0,
1458   EVEX_LEN_0F3A3A_W_1,
1459   EVEX_LEN_0F3A3B_W_0,
1460   EVEX_LEN_0F3A3B_W_1,
1461   EVEX_LEN_0F3A43_W_0,
1462   EVEX_LEN_0F3A43_W_1
1463 };
1464
1465 enum
1466 {
1467   VEX_W_0F41_P_0_LEN_1 = 0,
1468   VEX_W_0F41_P_2_LEN_1,
1469   VEX_W_0F42_P_0_LEN_1,
1470   VEX_W_0F42_P_2_LEN_1,
1471   VEX_W_0F44_P_0_LEN_0,
1472   VEX_W_0F44_P_2_LEN_0,
1473   VEX_W_0F45_P_0_LEN_1,
1474   VEX_W_0F45_P_2_LEN_1,
1475   VEX_W_0F46_P_0_LEN_1,
1476   VEX_W_0F46_P_2_LEN_1,
1477   VEX_W_0F47_P_0_LEN_1,
1478   VEX_W_0F47_P_2_LEN_1,
1479   VEX_W_0F4A_P_0_LEN_1,
1480   VEX_W_0F4A_P_2_LEN_1,
1481   VEX_W_0F4B_P_0_LEN_1,
1482   VEX_W_0F4B_P_2_LEN_1,
1483   VEX_W_0F90_P_0_LEN_0,
1484   VEX_W_0F90_P_2_LEN_0,
1485   VEX_W_0F91_P_0_LEN_0,
1486   VEX_W_0F91_P_2_LEN_0,
1487   VEX_W_0F92_P_0_LEN_0,
1488   VEX_W_0F92_P_2_LEN_0,
1489   VEX_W_0F93_P_0_LEN_0,
1490   VEX_W_0F93_P_2_LEN_0,
1491   VEX_W_0F98_P_0_LEN_0,
1492   VEX_W_0F98_P_2_LEN_0,
1493   VEX_W_0F99_P_0_LEN_0,
1494   VEX_W_0F99_P_2_LEN_0,
1495   VEX_W_0F380C,
1496   VEX_W_0F380D,
1497   VEX_W_0F380E,
1498   VEX_W_0F380F,
1499   VEX_W_0F3813,
1500   VEX_W_0F3816_L_1,
1501   VEX_W_0F3818,
1502   VEX_W_0F3819_L_1,
1503   VEX_W_0F381A_M_0_L_1,
1504   VEX_W_0F382C_M_0,
1505   VEX_W_0F382D_M_0,
1506   VEX_W_0F382E_M_0,
1507   VEX_W_0F382F_M_0,
1508   VEX_W_0F3836,
1509   VEX_W_0F3846,
1510   VEX_W_0F3849_X86_64_P_0,
1511   VEX_W_0F3849_X86_64_P_2,
1512   VEX_W_0F3849_X86_64_P_3,
1513   VEX_W_0F384B_X86_64_P_1,
1514   VEX_W_0F384B_X86_64_P_2,
1515   VEX_W_0F384B_X86_64_P_3,
1516   VEX_W_0F3858,
1517   VEX_W_0F3859,
1518   VEX_W_0F385A_M_0_L_0,
1519   VEX_W_0F385C_X86_64_P_1,
1520   VEX_W_0F385E_X86_64_P_0,
1521   VEX_W_0F385E_X86_64_P_1,
1522   VEX_W_0F385E_X86_64_P_2,
1523   VEX_W_0F385E_X86_64_P_3,
1524   VEX_W_0F3878,
1525   VEX_W_0F3879,
1526   VEX_W_0F38CF,
1527   VEX_W_0F3A00_L_1,
1528   VEX_W_0F3A01_L_1,
1529   VEX_W_0F3A02,
1530   VEX_W_0F3A04,
1531   VEX_W_0F3A05,
1532   VEX_W_0F3A06_L_1,
1533   VEX_W_0F3A18_L_1,
1534   VEX_W_0F3A19_L_1,
1535   VEX_W_0F3A1D,
1536   VEX_W_0F3A38_L_1,
1537   VEX_W_0F3A39_L_1,
1538   VEX_W_0F3A46_L_1,
1539   VEX_W_0F3A4A,
1540   VEX_W_0F3A4B,
1541   VEX_W_0F3A4C,
1542   VEX_W_0F3ACE,
1543   VEX_W_0F3ACF,
1544
1545   VEX_W_0FXOP_08_85_L_0,
1546   VEX_W_0FXOP_08_86_L_0,
1547   VEX_W_0FXOP_08_87_L_0,
1548   VEX_W_0FXOP_08_8E_L_0,
1549   VEX_W_0FXOP_08_8F_L_0,
1550   VEX_W_0FXOP_08_95_L_0,
1551   VEX_W_0FXOP_08_96_L_0,
1552   VEX_W_0FXOP_08_97_L_0,
1553   VEX_W_0FXOP_08_9E_L_0,
1554   VEX_W_0FXOP_08_9F_L_0,
1555   VEX_W_0FXOP_08_A6_L_0,
1556   VEX_W_0FXOP_08_B6_L_0,
1557   VEX_W_0FXOP_08_C0_L_0,
1558   VEX_W_0FXOP_08_C1_L_0,
1559   VEX_W_0FXOP_08_C2_L_0,
1560   VEX_W_0FXOP_08_C3_L_0,
1561   VEX_W_0FXOP_08_CC_L_0,
1562   VEX_W_0FXOP_08_CD_L_0,
1563   VEX_W_0FXOP_08_CE_L_0,
1564   VEX_W_0FXOP_08_CF_L_0,
1565   VEX_W_0FXOP_08_EC_L_0,
1566   VEX_W_0FXOP_08_ED_L_0,
1567   VEX_W_0FXOP_08_EE_L_0,
1568   VEX_W_0FXOP_08_EF_L_0,
1569
1570   VEX_W_0FXOP_09_80,
1571   VEX_W_0FXOP_09_81,
1572   VEX_W_0FXOP_09_82,
1573   VEX_W_0FXOP_09_83,
1574   VEX_W_0FXOP_09_C1_L_0,
1575   VEX_W_0FXOP_09_C2_L_0,
1576   VEX_W_0FXOP_09_C3_L_0,
1577   VEX_W_0FXOP_09_C6_L_0,
1578   VEX_W_0FXOP_09_C7_L_0,
1579   VEX_W_0FXOP_09_CB_L_0,
1580   VEX_W_0FXOP_09_D1_L_0,
1581   VEX_W_0FXOP_09_D2_L_0,
1582   VEX_W_0FXOP_09_D3_L_0,
1583   VEX_W_0FXOP_09_D6_L_0,
1584   VEX_W_0FXOP_09_D7_L_0,
1585   VEX_W_0FXOP_09_DB_L_0,
1586   VEX_W_0FXOP_09_E1_L_0,
1587   VEX_W_0FXOP_09_E2_L_0,
1588   VEX_W_0FXOP_09_E3_L_0,
1589
1590   EVEX_W_0F10_P_1,
1591   EVEX_W_0F10_P_3,
1592   EVEX_W_0F11_P_1,
1593   EVEX_W_0F11_P_3,
1594   EVEX_W_0F12_P_0_M_1,
1595   EVEX_W_0F12_P_1,
1596   EVEX_W_0F12_P_3,
1597   EVEX_W_0F16_P_0_M_1,
1598   EVEX_W_0F16_P_1,
1599   EVEX_W_0F2A_P_3,
1600   EVEX_W_0F51_P_1,
1601   EVEX_W_0F51_P_3,
1602   EVEX_W_0F58_P_1,
1603   EVEX_W_0F58_P_3,
1604   EVEX_W_0F59_P_1,
1605   EVEX_W_0F59_P_3,
1606   EVEX_W_0F5A_P_0,
1607   EVEX_W_0F5A_P_1,
1608   EVEX_W_0F5A_P_2,
1609   EVEX_W_0F5A_P_3,
1610   EVEX_W_0F5B_P_0,
1611   EVEX_W_0F5B_P_1,
1612   EVEX_W_0F5B_P_2,
1613   EVEX_W_0F5C_P_1,
1614   EVEX_W_0F5C_P_3,
1615   EVEX_W_0F5D_P_1,
1616   EVEX_W_0F5D_P_3,
1617   EVEX_W_0F5E_P_1,
1618   EVEX_W_0F5E_P_3,
1619   EVEX_W_0F5F_P_1,
1620   EVEX_W_0F5F_P_3,
1621   EVEX_W_0F62,
1622   EVEX_W_0F66,
1623   EVEX_W_0F6A,
1624   EVEX_W_0F6B,
1625   EVEX_W_0F6C,
1626   EVEX_W_0F6D,
1627   EVEX_W_0F6F_P_1,
1628   EVEX_W_0F6F_P_2,
1629   EVEX_W_0F6F_P_3,
1630   EVEX_W_0F70_P_2,
1631   EVEX_W_0F72_R_2,
1632   EVEX_W_0F72_R_6,
1633   EVEX_W_0F73_R_2,
1634   EVEX_W_0F73_R_6,
1635   EVEX_W_0F76,
1636   EVEX_W_0F78_P_0,
1637   EVEX_W_0F78_P_2,
1638   EVEX_W_0F79_P_0,
1639   EVEX_W_0F79_P_2,
1640   EVEX_W_0F7A_P_1,
1641   EVEX_W_0F7A_P_2,
1642   EVEX_W_0F7A_P_3,
1643   EVEX_W_0F7B_P_2,
1644   EVEX_W_0F7B_P_3,
1645   EVEX_W_0F7E_P_1,
1646   EVEX_W_0F7F_P_1,
1647   EVEX_W_0F7F_P_2,
1648   EVEX_W_0F7F_P_3,
1649   EVEX_W_0FC2_P_1,
1650   EVEX_W_0FC2_P_3,
1651   EVEX_W_0FD2,
1652   EVEX_W_0FD3,
1653   EVEX_W_0FD4,
1654   EVEX_W_0FD6_L_0,
1655   EVEX_W_0FE6_P_1,
1656   EVEX_W_0FE6_P_2,
1657   EVEX_W_0FE6_P_3,
1658   EVEX_W_0FE7,
1659   EVEX_W_0FF2,
1660   EVEX_W_0FF3,
1661   EVEX_W_0FF4,
1662   EVEX_W_0FFA,
1663   EVEX_W_0FFB,
1664   EVEX_W_0FFE,
1665   EVEX_W_0F380D,
1666   EVEX_W_0F3810_P_1,
1667   EVEX_W_0F3810_P_2,
1668   EVEX_W_0F3811_P_1,
1669   EVEX_W_0F3811_P_2,
1670   EVEX_W_0F3812_P_1,
1671   EVEX_W_0F3812_P_2,
1672   EVEX_W_0F3813_P_1,
1673   EVEX_W_0F3813_P_2,
1674   EVEX_W_0F3814_P_1,
1675   EVEX_W_0F3815_P_1,
1676   EVEX_W_0F3819,
1677   EVEX_W_0F381A,
1678   EVEX_W_0F381B,
1679   EVEX_W_0F381E,
1680   EVEX_W_0F381F,
1681   EVEX_W_0F3820_P_1,
1682   EVEX_W_0F3821_P_1,
1683   EVEX_W_0F3822_P_1,
1684   EVEX_W_0F3823_P_1,
1685   EVEX_W_0F3824_P_1,
1686   EVEX_W_0F3825_P_1,
1687   EVEX_W_0F3825_P_2,
1688   EVEX_W_0F3828_P_2,
1689   EVEX_W_0F3829_P_2,
1690   EVEX_W_0F382A_P_1,
1691   EVEX_W_0F382A_P_2,
1692   EVEX_W_0F382B,
1693   EVEX_W_0F3830_P_1,
1694   EVEX_W_0F3831_P_1,
1695   EVEX_W_0F3832_P_1,
1696   EVEX_W_0F3833_P_1,
1697   EVEX_W_0F3834_P_1,
1698   EVEX_W_0F3835_P_1,
1699   EVEX_W_0F3835_P_2,
1700   EVEX_W_0F3837,
1701   EVEX_W_0F383A_P_1,
1702   EVEX_W_0F3852_P_1,
1703   EVEX_W_0F3859,
1704   EVEX_W_0F385A,
1705   EVEX_W_0F385B,
1706   EVEX_W_0F3870,
1707   EVEX_W_0F3872_P_1,
1708   EVEX_W_0F3872_P_2,
1709   EVEX_W_0F3872_P_3,
1710   EVEX_W_0F387A,
1711   EVEX_W_0F387B,
1712   EVEX_W_0F3883,
1713   EVEX_W_0F3891,
1714   EVEX_W_0F3893,
1715   EVEX_W_0F38A1,
1716   EVEX_W_0F38A3,
1717   EVEX_W_0F38C7_R_1_M_0,
1718   EVEX_W_0F38C7_R_2_M_0,
1719   EVEX_W_0F38C7_R_5_M_0,
1720   EVEX_W_0F38C7_R_6_M_0,
1721
1722   EVEX_W_0F3A00,
1723   EVEX_W_0F3A01,
1724   EVEX_W_0F3A05,
1725   EVEX_W_0F3A08,
1726   EVEX_W_0F3A09,
1727   EVEX_W_0F3A0A,
1728   EVEX_W_0F3A0B,
1729   EVEX_W_0F3A18,
1730   EVEX_W_0F3A19,
1731   EVEX_W_0F3A1A,
1732   EVEX_W_0F3A1B,
1733   EVEX_W_0F3A21,
1734   EVEX_W_0F3A23,
1735   EVEX_W_0F3A38,
1736   EVEX_W_0F3A39,
1737   EVEX_W_0F3A3A,
1738   EVEX_W_0F3A3B,
1739   EVEX_W_0F3A42,
1740   EVEX_W_0F3A43,
1741   EVEX_W_0F3A70,
1742   EVEX_W_0F3A72,
1743 };
1744
1745 typedef void (*op_rtn) (int bytemode, int sizeflag);
1746
1747 struct dis386 {
1748   const char *name;
1749   struct
1750     {
1751       op_rtn rtn;
1752       int bytemode;
1753     } op[MAX_OPERANDS];
1754   unsigned int prefix_requirement;
1755 };
1756
1757 /* Upper case letters in the instruction names here are macros.
1758    'A' => print 'b' if no register operands or suffix_always is true
1759    'B' => print 'b' if suffix_always is true
1760    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1761           size prefix
1762    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1763           suffix_always is true
1764    'E' => print 'e' if 32-bit form of jcxz
1765    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1766    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1767    'H' => print ",pt" or ",pn" branch hint
1768    'I' unused.
1769    'J' unused.
1770    'K' => print 'd' or 'q' if rex prefix is present.
1771    'L' unused.
1772    'M' => print 'r' if intel_mnemonic is false.
1773    'N' => print 'n' if instruction has no wait "prefix"
1774    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1775    'P' => behave as 'T' except with register operand outside of suffix_always
1776           mode
1777    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1778           is true
1779    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1780    'S' => print 'w', 'l' or 'q' if suffix_always is true
1781    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1782           prefix or if suffix_always is true.
1783    'U' unused.
1784    'V' unused.
1785    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1786    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1787    'Y' unused.
1788    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1789    '!' => change condition from true to false or from false to true.
1790    '%' => add 1 upper case letter to the macro.
1791    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1792           prefix or suffix_always is true (lcall/ljmp).
1793    '@' => in 64bit mode for Intel64 ISA or if instruction
1794           has no operand sizing prefix, print 'q' if suffix_always is true or
1795           nothing otherwise; behave as 'P' in all other cases
1796
1797    2 upper case letter macros:
1798    "XY" => print 'x' or 'y' if suffix_always is true or no register
1799            operands and no broadcast.
1800    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1801            register operands and no broadcast.
1802    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1803    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1804            being false, or no operand at all in 64bit mode, or if suffix_always
1805            is true.
1806    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1807    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1808    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1809    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1810    "BW" => print 'b' or 'w' depending on the VEX.W bit
1811    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1812            an operand size prefix, or suffix_always is true.  print
1813            'q' if rex prefix is present.
1814
1815    Many of the above letters print nothing in Intel mode.  See "putop"
1816    for the details.
1817
1818    Braces '{' and '}', and vertical bars '|', indicate alternative
1819    mnemonic strings for AT&T and Intel.  */
1820
1821 static const struct dis386 dis386[] = {
1822   /* 00 */
1823   { "addB",             { Ebh1, Gb }, 0 },
1824   { "addS",             { Evh1, Gv }, 0 },
1825   { "addB",             { Gb, EbS }, 0 },
1826   { "addS",             { Gv, EvS }, 0 },
1827   { "addB",             { AL, Ib }, 0 },
1828   { "addS",             { eAX, Iv }, 0 },
1829   { X86_64_TABLE (X86_64_06) },
1830   { X86_64_TABLE (X86_64_07) },
1831   /* 08 */
1832   { "orB",              { Ebh1, Gb }, 0 },
1833   { "orS",              { Evh1, Gv }, 0 },
1834   { "orB",              { Gb, EbS }, 0 },
1835   { "orS",              { Gv, EvS }, 0 },
1836   { "orB",              { AL, Ib }, 0 },
1837   { "orS",              { eAX, Iv }, 0 },
1838   { X86_64_TABLE (X86_64_0E) },
1839   { Bad_Opcode },       /* 0x0f extended opcode escape */
1840   /* 10 */
1841   { "adcB",             { Ebh1, Gb }, 0 },
1842   { "adcS",             { Evh1, Gv }, 0 },
1843   { "adcB",             { Gb, EbS }, 0 },
1844   { "adcS",             { Gv, EvS }, 0 },
1845   { "adcB",             { AL, Ib }, 0 },
1846   { "adcS",             { eAX, Iv }, 0 },
1847   { X86_64_TABLE (X86_64_16) },
1848   { X86_64_TABLE (X86_64_17) },
1849   /* 18 */
1850   { "sbbB",             { Ebh1, Gb }, 0 },
1851   { "sbbS",             { Evh1, Gv }, 0 },
1852   { "sbbB",             { Gb, EbS }, 0 },
1853   { "sbbS",             { Gv, EvS }, 0 },
1854   { "sbbB",             { AL, Ib }, 0 },
1855   { "sbbS",             { eAX, Iv }, 0 },
1856   { X86_64_TABLE (X86_64_1E) },
1857   { X86_64_TABLE (X86_64_1F) },
1858   /* 20 */
1859   { "andB",             { Ebh1, Gb }, 0 },
1860   { "andS",             { Evh1, Gv }, 0 },
1861   { "andB",             { Gb, EbS }, 0 },
1862   { "andS",             { Gv, EvS }, 0 },
1863   { "andB",             { AL, Ib }, 0 },
1864   { "andS",             { eAX, Iv }, 0 },
1865   { Bad_Opcode },       /* SEG ES prefix */
1866   { X86_64_TABLE (X86_64_27) },
1867   /* 28 */
1868   { "subB",             { Ebh1, Gb }, 0 },
1869   { "subS",             { Evh1, Gv }, 0 },
1870   { "subB",             { Gb, EbS }, 0 },
1871   { "subS",             { Gv, EvS }, 0 },
1872   { "subB",             { AL, Ib }, 0 },
1873   { "subS",             { eAX, Iv }, 0 },
1874   { Bad_Opcode },       /* SEG CS prefix */
1875   { X86_64_TABLE (X86_64_2F) },
1876   /* 30 */
1877   { "xorB",             { Ebh1, Gb }, 0 },
1878   { "xorS",             { Evh1, Gv }, 0 },
1879   { "xorB",             { Gb, EbS }, 0 },
1880   { "xorS",             { Gv, EvS }, 0 },
1881   { "xorB",             { AL, Ib }, 0 },
1882   { "xorS",             { eAX, Iv }, 0 },
1883   { Bad_Opcode },       /* SEG SS prefix */
1884   { X86_64_TABLE (X86_64_37) },
1885   /* 38 */
1886   { "cmpB",             { Eb, Gb }, 0 },
1887   { "cmpS",             { Ev, Gv }, 0 },
1888   { "cmpB",             { Gb, EbS }, 0 },
1889   { "cmpS",             { Gv, EvS }, 0 },
1890   { "cmpB",             { AL, Ib }, 0 },
1891   { "cmpS",             { eAX, Iv }, 0 },
1892   { Bad_Opcode },       /* SEG DS prefix */
1893   { X86_64_TABLE (X86_64_3F) },
1894   /* 40 */
1895   { "inc{S|}",          { RMeAX }, 0 },
1896   { "inc{S|}",          { RMeCX }, 0 },
1897   { "inc{S|}",          { RMeDX }, 0 },
1898   { "inc{S|}",          { RMeBX }, 0 },
1899   { "inc{S|}",          { RMeSP }, 0 },
1900   { "inc{S|}",          { RMeBP }, 0 },
1901   { "inc{S|}",          { RMeSI }, 0 },
1902   { "inc{S|}",          { RMeDI }, 0 },
1903   /* 48 */
1904   { "dec{S|}",          { RMeAX }, 0 },
1905   { "dec{S|}",          { RMeCX }, 0 },
1906   { "dec{S|}",          { RMeDX }, 0 },
1907   { "dec{S|}",          { RMeBX }, 0 },
1908   { "dec{S|}",          { RMeSP }, 0 },
1909   { "dec{S|}",          { RMeBP }, 0 },
1910   { "dec{S|}",          { RMeSI }, 0 },
1911   { "dec{S|}",          { RMeDI }, 0 },
1912   /* 50 */
1913   { "push{!P|}",                { RMrAX }, 0 },
1914   { "push{!P|}",                { RMrCX }, 0 },
1915   { "push{!P|}",                { RMrDX }, 0 },
1916   { "push{!P|}",                { RMrBX }, 0 },
1917   { "push{!P|}",                { RMrSP }, 0 },
1918   { "push{!P|}",                { RMrBP }, 0 },
1919   { "push{!P|}",                { RMrSI }, 0 },
1920   { "push{!P|}",                { RMrDI }, 0 },
1921   /* 58 */
1922   { "pop{!P|}",         { RMrAX }, 0 },
1923   { "pop{!P|}",         { RMrCX }, 0 },
1924   { "pop{!P|}",         { RMrDX }, 0 },
1925   { "pop{!P|}",         { RMrBX }, 0 },
1926   { "pop{!P|}",         { RMrSP }, 0 },
1927   { "pop{!P|}",         { RMrBP }, 0 },
1928   { "pop{!P|}",         { RMrSI }, 0 },
1929   { "pop{!P|}",         { RMrDI }, 0 },
1930   /* 60 */
1931   { X86_64_TABLE (X86_64_60) },
1932   { X86_64_TABLE (X86_64_61) },
1933   { X86_64_TABLE (X86_64_62) },
1934   { X86_64_TABLE (X86_64_63) },
1935   { Bad_Opcode },       /* seg fs */
1936   { Bad_Opcode },       /* seg gs */
1937   { Bad_Opcode },       /* op size prefix */
1938   { Bad_Opcode },       /* adr size prefix */
1939   /* 68 */
1940   { "pushP",            { sIv }, 0 },
1941   { "imulS",            { Gv, Ev, Iv }, 0 },
1942   { "pushP",            { sIbT }, 0 },
1943   { "imulS",            { Gv, Ev, sIb }, 0 },
1944   { "ins{b|}",          { Ybr, indirDX }, 0 },
1945   { X86_64_TABLE (X86_64_6D) },
1946   { "outs{b|}",         { indirDXr, Xb }, 0 },
1947   { X86_64_TABLE (X86_64_6F) },
1948   /* 70 */
1949   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
1950   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
1951   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
1952   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
1953   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
1954   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
1955   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
1956   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
1957   /* 78 */
1958   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
1959   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
1960   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
1961   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
1962   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
1963   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
1964   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
1965   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
1966   /* 80 */
1967   { REG_TABLE (REG_80) },
1968   { REG_TABLE (REG_81) },
1969   { X86_64_TABLE (X86_64_82) },
1970   { REG_TABLE (REG_83) },
1971   { "testB",            { Eb, Gb }, 0 },
1972   { "testS",            { Ev, Gv }, 0 },
1973   { "xchgB",            { Ebh2, Gb }, 0 },
1974   { "xchgS",            { Evh2, Gv }, 0 },
1975   /* 88 */
1976   { "movB",             { Ebh3, Gb }, 0 },
1977   { "movS",             { Evh3, Gv }, 0 },
1978   { "movB",             { Gb, EbS }, 0 },
1979   { "movS",             { Gv, EvS }, 0 },
1980   { "movD",             { Sv, Sw }, 0 },
1981   { MOD_TABLE (MOD_8D) },
1982   { "movD",             { Sw, Sv }, 0 },
1983   { REG_TABLE (REG_8F) },
1984   /* 90 */
1985   { PREFIX_TABLE (PREFIX_90) },
1986   { "xchgS",            { RMeCX, eAX }, 0 },
1987   { "xchgS",            { RMeDX, eAX }, 0 },
1988   { "xchgS",            { RMeBX, eAX }, 0 },
1989   { "xchgS",            { RMeSP, eAX }, 0 },
1990   { "xchgS",            { RMeBP, eAX }, 0 },
1991   { "xchgS",            { RMeSI, eAX }, 0 },
1992   { "xchgS",            { RMeDI, eAX }, 0 },
1993   /* 98 */
1994   { "cW{t|}R",          { XX }, 0 },
1995   { "cR{t|}O",          { XX }, 0 },
1996   { X86_64_TABLE (X86_64_9A) },
1997   { Bad_Opcode },       /* fwait */
1998   { "pushfP",           { XX }, 0 },
1999   { "popfP",            { XX }, 0 },
2000   { "sahf",             { XX }, 0 },
2001   { "lahf",             { XX }, 0 },
2002   /* a0 */
2003   { "mov%LB",           { AL, Ob }, 0 },
2004   { "mov%LS",           { eAX, Ov }, 0 },
2005   { "mov%LB",           { Ob, AL }, 0 },
2006   { "mov%LS",           { Ov, eAX }, 0 },
2007   { "movs{b|}",         { Ybr, Xb }, 0 },
2008   { "movs{R|}",         { Yvr, Xv }, 0 },
2009   { "cmps{b|}",         { Xb, Yb }, 0 },
2010   { "cmps{R|}",         { Xv, Yv }, 0 },
2011   /* a8 */
2012   { "testB",            { AL, Ib }, 0 },
2013   { "testS",            { eAX, Iv }, 0 },
2014   { "stosB",            { Ybr, AL }, 0 },
2015   { "stosS",            { Yvr, eAX }, 0 },
2016   { "lodsB",            { ALr, Xb }, 0 },
2017   { "lodsS",            { eAXr, Xv }, 0 },
2018   { "scasB",            { AL, Yb }, 0 },
2019   { "scasS",            { eAX, Yv }, 0 },
2020   /* b0 */
2021   { "movB",             { RMAL, Ib }, 0 },
2022   { "movB",             { RMCL, Ib }, 0 },
2023   { "movB",             { RMDL, Ib }, 0 },
2024   { "movB",             { RMBL, Ib }, 0 },
2025   { "movB",             { RMAH, Ib }, 0 },
2026   { "movB",             { RMCH, Ib }, 0 },
2027   { "movB",             { RMDH, Ib }, 0 },
2028   { "movB",             { RMBH, Ib }, 0 },
2029   /* b8 */
2030   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2031   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2032   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2033   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2034   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2035   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2036   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2037   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2038   /* c0 */
2039   { REG_TABLE (REG_C0) },
2040   { REG_TABLE (REG_C1) },
2041   { X86_64_TABLE (X86_64_C2) },
2042   { X86_64_TABLE (X86_64_C3) },
2043   { X86_64_TABLE (X86_64_C4) },
2044   { X86_64_TABLE (X86_64_C5) },
2045   { REG_TABLE (REG_C6) },
2046   { REG_TABLE (REG_C7) },
2047   /* c8 */
2048   { "enterP",           { Iw, Ib }, 0 },
2049   { "leaveP",           { XX }, 0 },
2050   { "{l|}ret{|f}%LP",   { Iw }, 0 },
2051   { "{l|}ret{|f}%LP",   { XX }, 0 },
2052   { "int3",             { XX }, 0 },
2053   { "int",              { Ib }, 0 },
2054   { X86_64_TABLE (X86_64_CE) },
2055   { "iret%LP",          { XX }, 0 },
2056   /* d0 */
2057   { REG_TABLE (REG_D0) },
2058   { REG_TABLE (REG_D1) },
2059   { REG_TABLE (REG_D2) },
2060   { REG_TABLE (REG_D3) },
2061   { X86_64_TABLE (X86_64_D4) },
2062   { X86_64_TABLE (X86_64_D5) },
2063   { Bad_Opcode },
2064   { "xlat",             { DSBX }, 0 },
2065   /* d8 */
2066   { FLOAT },
2067   { FLOAT },
2068   { FLOAT },
2069   { FLOAT },
2070   { FLOAT },
2071   { FLOAT },
2072   { FLOAT },
2073   { FLOAT },
2074   /* e0 */
2075   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2076   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2077   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2078   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2079   { "inB",              { AL, Ib }, 0 },
2080   { "inG",              { zAX, Ib }, 0 },
2081   { "outB",             { Ib, AL }, 0 },
2082   { "outG",             { Ib, zAX }, 0 },
2083   /* e8 */
2084   { X86_64_TABLE (X86_64_E8) },
2085   { X86_64_TABLE (X86_64_E9) },
2086   { X86_64_TABLE (X86_64_EA) },
2087   { "jmp",              { Jb, BND }, 0 },
2088   { "inB",              { AL, indirDX }, 0 },
2089   { "inG",              { zAX, indirDX }, 0 },
2090   { "outB",             { indirDX, AL }, 0 },
2091   { "outG",             { indirDX, zAX }, 0 },
2092   /* f0 */
2093   { Bad_Opcode },       /* lock prefix */
2094   { "icebp",            { XX }, 0 },
2095   { Bad_Opcode },       /* repne */
2096   { Bad_Opcode },       /* repz */
2097   { "hlt",              { XX }, 0 },
2098   { "cmc",              { XX }, 0 },
2099   { REG_TABLE (REG_F6) },
2100   { REG_TABLE (REG_F7) },
2101   /* f8 */
2102   { "clc",              { XX }, 0 },
2103   { "stc",              { XX }, 0 },
2104   { "cli",              { XX }, 0 },
2105   { "sti",              { XX }, 0 },
2106   { "cld",              { XX }, 0 },
2107   { "std",              { XX }, 0 },
2108   { REG_TABLE (REG_FE) },
2109   { REG_TABLE (REG_FF) },
2110 };
2111
2112 static const struct dis386 dis386_twobyte[] = {
2113   /* 00 */
2114   { REG_TABLE (REG_0F00 ) },
2115   { REG_TABLE (REG_0F01 ) },
2116   { "larS",             { Gv, Ew }, 0 },
2117   { "lslS",             { Gv, Ew }, 0 },
2118   { Bad_Opcode },
2119   { "syscall",          { XX }, 0 },
2120   { "clts",             { XX }, 0 },
2121   { "sysret%LQ",                { XX }, 0 },
2122   /* 08 */
2123   { "invd",             { XX }, 0 },
2124   { PREFIX_TABLE (PREFIX_0F09) },
2125   { Bad_Opcode },
2126   { "ud2",              { XX }, 0 },
2127   { Bad_Opcode },
2128   { REG_TABLE (REG_0F0D) },
2129   { "femms",            { XX }, 0 },
2130   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2131   /* 10 */
2132   { PREFIX_TABLE (PREFIX_0F10) },
2133   { PREFIX_TABLE (PREFIX_0F11) },
2134   { PREFIX_TABLE (PREFIX_0F12) },
2135   { MOD_TABLE (MOD_0F13) },
2136   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2137   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2138   { PREFIX_TABLE (PREFIX_0F16) },
2139   { MOD_TABLE (MOD_0F17) },
2140   /* 18 */
2141   { REG_TABLE (REG_0F18) },
2142   { "nopQ",             { Ev }, 0 },
2143   { PREFIX_TABLE (PREFIX_0F1A) },
2144   { PREFIX_TABLE (PREFIX_0F1B) },
2145   { PREFIX_TABLE (PREFIX_0F1C) },
2146   { "nopQ",             { Ev }, 0 },
2147   { PREFIX_TABLE (PREFIX_0F1E) },
2148   { "nopQ",             { Ev }, 0 },
2149   /* 20 */
2150   { "movZ",             { Em, Cm }, 0 },
2151   { "movZ",             { Em, Dm }, 0 },
2152   { "movZ",             { Cm, Em }, 0 },
2153   { "movZ",             { Dm, Em }, 0 },
2154   { X86_64_TABLE (X86_64_0F24) },
2155   { Bad_Opcode },
2156   { X86_64_TABLE (X86_64_0F26) },
2157   { Bad_Opcode },
2158   /* 28 */
2159   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2160   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2161   { PREFIX_TABLE (PREFIX_0F2A) },
2162   { PREFIX_TABLE (PREFIX_0F2B) },
2163   { PREFIX_TABLE (PREFIX_0F2C) },
2164   { PREFIX_TABLE (PREFIX_0F2D) },
2165   { PREFIX_TABLE (PREFIX_0F2E) },
2166   { PREFIX_TABLE (PREFIX_0F2F) },
2167   /* 30 */
2168   { "wrmsr",            { XX }, 0 },
2169   { "rdtsc",            { XX }, 0 },
2170   { "rdmsr",            { XX }, 0 },
2171   { "rdpmc",            { XX }, 0 },
2172   { "sysenter",         { SEP }, 0 },
2173   { "sysexit",          { SEP }, 0 },
2174   { Bad_Opcode },
2175   { "getsec",           { XX }, 0 },
2176   /* 38 */
2177   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2178   { Bad_Opcode },
2179   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2180   { Bad_Opcode },
2181   { Bad_Opcode },
2182   { Bad_Opcode },
2183   { Bad_Opcode },
2184   { Bad_Opcode },
2185   /* 40 */
2186   { "cmovoS",           { Gv, Ev }, 0 },
2187   { "cmovnoS",          { Gv, Ev }, 0 },
2188   { "cmovbS",           { Gv, Ev }, 0 },
2189   { "cmovaeS",          { Gv, Ev }, 0 },
2190   { "cmoveS",           { Gv, Ev }, 0 },
2191   { "cmovneS",          { Gv, Ev }, 0 },
2192   { "cmovbeS",          { Gv, Ev }, 0 },
2193   { "cmovaS",           { Gv, Ev }, 0 },
2194   /* 48 */
2195   { "cmovsS",           { Gv, Ev }, 0 },
2196   { "cmovnsS",          { Gv, Ev }, 0 },
2197   { "cmovpS",           { Gv, Ev }, 0 },
2198   { "cmovnpS",          { Gv, Ev }, 0 },
2199   { "cmovlS",           { Gv, Ev }, 0 },
2200   { "cmovgeS",          { Gv, Ev }, 0 },
2201   { "cmovleS",          { Gv, Ev }, 0 },
2202   { "cmovgS",           { Gv, Ev }, 0 },
2203   /* 50 */
2204   { MOD_TABLE (MOD_0F50) },
2205   { PREFIX_TABLE (PREFIX_0F51) },
2206   { PREFIX_TABLE (PREFIX_0F52) },
2207   { PREFIX_TABLE (PREFIX_0F53) },
2208   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2209   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2210   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2211   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2212   /* 58 */
2213   { PREFIX_TABLE (PREFIX_0F58) },
2214   { PREFIX_TABLE (PREFIX_0F59) },
2215   { PREFIX_TABLE (PREFIX_0F5A) },
2216   { PREFIX_TABLE (PREFIX_0F5B) },
2217   { PREFIX_TABLE (PREFIX_0F5C) },
2218   { PREFIX_TABLE (PREFIX_0F5D) },
2219   { PREFIX_TABLE (PREFIX_0F5E) },
2220   { PREFIX_TABLE (PREFIX_0F5F) },
2221   /* 60 */
2222   { PREFIX_TABLE (PREFIX_0F60) },
2223   { PREFIX_TABLE (PREFIX_0F61) },
2224   { PREFIX_TABLE (PREFIX_0F62) },
2225   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2226   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2227   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2228   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2229   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2230   /* 68 */
2231   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2232   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2233   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2234   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2235   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2236   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2237   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2238   { PREFIX_TABLE (PREFIX_0F6F) },
2239   /* 70 */
2240   { PREFIX_TABLE (PREFIX_0F70) },
2241   { REG_TABLE (REG_0F71) },
2242   { REG_TABLE (REG_0F72) },
2243   { REG_TABLE (REG_0F73) },
2244   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2245   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2246   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2247   { "emms",             { XX }, PREFIX_OPCODE },
2248   /* 78 */
2249   { PREFIX_TABLE (PREFIX_0F78) },
2250   { PREFIX_TABLE (PREFIX_0F79) },
2251   { Bad_Opcode },
2252   { Bad_Opcode },
2253   { PREFIX_TABLE (PREFIX_0F7C) },
2254   { PREFIX_TABLE (PREFIX_0F7D) },
2255   { PREFIX_TABLE (PREFIX_0F7E) },
2256   { PREFIX_TABLE (PREFIX_0F7F) },
2257   /* 80 */
2258   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2259   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2260   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2261   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2262   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2263   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2264   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2265   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2266   /* 88 */
2267   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2268   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2269   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2270   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2271   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2272   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2273   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2274   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2275   /* 90 */
2276   { "seto",             { Eb }, 0 },
2277   { "setno",            { Eb }, 0 },
2278   { "setb",             { Eb }, 0 },
2279   { "setae",            { Eb }, 0 },
2280   { "sete",             { Eb }, 0 },
2281   { "setne",            { Eb }, 0 },
2282   { "setbe",            { Eb }, 0 },
2283   { "seta",             { Eb }, 0 },
2284   /* 98 */
2285   { "sets",             { Eb }, 0 },
2286   { "setns",            { Eb }, 0 },
2287   { "setp",             { Eb }, 0 },
2288   { "setnp",            { Eb }, 0 },
2289   { "setl",             { Eb }, 0 },
2290   { "setge",            { Eb }, 0 },
2291   { "setle",            { Eb }, 0 },
2292   { "setg",             { Eb }, 0 },
2293   /* a0 */
2294   { "pushP",            { fs }, 0 },
2295   { "popP",             { fs }, 0 },
2296   { "cpuid",            { XX }, 0 },
2297   { "btS",              { Ev, Gv }, 0 },
2298   { "shldS",            { Ev, Gv, Ib }, 0 },
2299   { "shldS",            { Ev, Gv, CL }, 0 },
2300   { REG_TABLE (REG_0FA6) },
2301   { REG_TABLE (REG_0FA7) },
2302   /* a8 */
2303   { "pushP",            { gs }, 0 },
2304   { "popP",             { gs }, 0 },
2305   { "rsm",              { XX }, 0 },
2306   { "btsS",             { Evh1, Gv }, 0 },
2307   { "shrdS",            { Ev, Gv, Ib }, 0 },
2308   { "shrdS",            { Ev, Gv, CL }, 0 },
2309   { REG_TABLE (REG_0FAE) },
2310   { "imulS",            { Gv, Ev }, 0 },
2311   /* b0 */
2312   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2313   { "cmpxchgS",         { Evh1, Gv }, 0 },
2314   { MOD_TABLE (MOD_0FB2) },
2315   { "btrS",             { Evh1, Gv }, 0 },
2316   { MOD_TABLE (MOD_0FB4) },
2317   { MOD_TABLE (MOD_0FB5) },
2318   { "movz{bR|x}",       { Gv, Eb }, 0 },
2319   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2320   /* b8 */
2321   { PREFIX_TABLE (PREFIX_0FB8) },
2322   { "ud1S",             { Gv, Ev }, 0 },
2323   { REG_TABLE (REG_0FBA) },
2324   { "btcS",             { Evh1, Gv }, 0 },
2325   { PREFIX_TABLE (PREFIX_0FBC) },
2326   { PREFIX_TABLE (PREFIX_0FBD) },
2327   { "movs{bR|x}",       { Gv, Eb }, 0 },
2328   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2329   /* c0 */
2330   { "xaddB",            { Ebh1, Gb }, 0 },
2331   { "xaddS",            { Evh1, Gv }, 0 },
2332   { PREFIX_TABLE (PREFIX_0FC2) },
2333   { MOD_TABLE (MOD_0FC3) },
2334   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2335   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2336   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2337   { REG_TABLE (REG_0FC7) },
2338   /* c8 */
2339   { "bswap",            { RMeAX }, 0 },
2340   { "bswap",            { RMeCX }, 0 },
2341   { "bswap",            { RMeDX }, 0 },
2342   { "bswap",            { RMeBX }, 0 },
2343   { "bswap",            { RMeSP }, 0 },
2344   { "bswap",            { RMeBP }, 0 },
2345   { "bswap",            { RMeSI }, 0 },
2346   { "bswap",            { RMeDI }, 0 },
2347   /* d0 */
2348   { PREFIX_TABLE (PREFIX_0FD0) },
2349   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2350   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2351   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2352   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2353   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2354   { PREFIX_TABLE (PREFIX_0FD6) },
2355   { MOD_TABLE (MOD_0FD7) },
2356   /* d8 */
2357   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2358   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2359   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2360   { "pand",             { MX, EM }, PREFIX_OPCODE },
2361   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2362   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2363   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2364   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2365   /* e0 */
2366   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2367   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2368   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2369   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2370   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2371   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2372   { PREFIX_TABLE (PREFIX_0FE6) },
2373   { PREFIX_TABLE (PREFIX_0FE7) },
2374   /* e8 */
2375   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2376   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2377   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2378   { "por",              { MX, EM }, PREFIX_OPCODE },
2379   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2380   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2381   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2382   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2383   /* f0 */
2384   { PREFIX_TABLE (PREFIX_0FF0) },
2385   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2386   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2387   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2388   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2389   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2390   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2391   { PREFIX_TABLE (PREFIX_0FF7) },
2392   /* f8 */
2393   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2394   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2395   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2396   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2397   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2398   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2399   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2400   { "ud0S",             { Gv, Ev }, 0 },
2401 };
2402
2403 static const unsigned char onebyte_has_modrm[256] = {
2404   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2405   /*       -------------------------------        */
2406   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2407   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2408   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2409   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2410   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2411   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2412   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2413   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2414   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2415   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2416   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2417   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2418   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2419   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2420   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2421   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2422   /*       -------------------------------        */
2423   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2424 };
2425
2426 static const unsigned char twobyte_has_modrm[256] = {
2427   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2428   /*       -------------------------------        */
2429   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2430   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2431   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2432   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2433   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2434   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2435   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2436   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2437   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2438   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2439   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2440   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2441   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2442   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2443   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2444   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2445   /*       -------------------------------        */
2446   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2447 };
2448
2449 static char obuf[100];
2450 static char *obufp;
2451 static char *mnemonicendp;
2452 static char scratchbuf[100];
2453 static unsigned char *start_codep;
2454 static unsigned char *insn_codep;
2455 static unsigned char *codep;
2456 static unsigned char *end_codep;
2457 static int last_lock_prefix;
2458 static int last_repz_prefix;
2459 static int last_repnz_prefix;
2460 static int last_data_prefix;
2461 static int last_addr_prefix;
2462 static int last_rex_prefix;
2463 static int last_seg_prefix;
2464 static int fwait_prefix;
2465 /* The active segment register prefix.  */
2466 static int active_seg_prefix;
2467 #define MAX_CODE_LENGTH 15
2468 /* We can up to 14 prefixes since the maximum instruction length is
2469    15bytes.  */
2470 static int all_prefixes[MAX_CODE_LENGTH - 1];
2471 static disassemble_info *the_info;
2472 static struct
2473   {
2474     int mod;
2475     int reg;
2476     int rm;
2477   }
2478 modrm;
2479 static unsigned char need_modrm;
2480 static struct
2481   {
2482     int scale;
2483     int index;
2484     int base;
2485   }
2486 sib;
2487 static struct
2488   {
2489     int register_specifier;
2490     int length;
2491     int prefix;
2492     int w;
2493     int evex;
2494     int r;
2495     int v;
2496     int mask_register_specifier;
2497     int zeroing;
2498     int ll;
2499     int b;
2500   }
2501 vex;
2502 static unsigned char need_vex;
2503
2504 struct op
2505   {
2506     const char *name;
2507     unsigned int len;
2508   };
2509
2510 /* If we are accessing mod/rm/reg without need_modrm set, then the
2511    values are stale.  Hitting this abort likely indicates that you
2512    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2513 #define MODRM_CHECK  if (!need_modrm) abort ()
2514
2515 static const char **names64;
2516 static const char **names32;
2517 static const char **names16;
2518 static const char **names8;
2519 static const char **names8rex;
2520 static const char **names_seg;
2521 static const char *index64;
2522 static const char *index32;
2523 static const char **index16;
2524 static const char **names_bnd;
2525
2526 static const char *intel_names64[] = {
2527   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2528   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2529 };
2530 static const char *intel_names32[] = {
2531   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2532   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2533 };
2534 static const char *intel_names16[] = {
2535   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2536   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2537 };
2538 static const char *intel_names8[] = {
2539   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2540 };
2541 static const char *intel_names8rex[] = {
2542   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2543   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2544 };
2545 static const char *intel_names_seg[] = {
2546   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2547 };
2548 static const char *intel_index64 = "riz";
2549 static const char *intel_index32 = "eiz";
2550 static const char *intel_index16[] = {
2551   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2552 };
2553
2554 static const char *att_names64[] = {
2555   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2556   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2557 };
2558 static const char *att_names32[] = {
2559   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2560   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2561 };
2562 static const char *att_names16[] = {
2563   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2564   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2565 };
2566 static const char *att_names8[] = {
2567   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2568 };
2569 static const char *att_names8rex[] = {
2570   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2571   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2572 };
2573 static const char *att_names_seg[] = {
2574   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2575 };
2576 static const char *att_index64 = "%riz";
2577 static const char *att_index32 = "%eiz";
2578 static const char *att_index16[] = {
2579   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2580 };
2581
2582 static const char **names_mm;
2583 static const char *intel_names_mm[] = {
2584   "mm0", "mm1", "mm2", "mm3",
2585   "mm4", "mm5", "mm6", "mm7"
2586 };
2587 static const char *att_names_mm[] = {
2588   "%mm0", "%mm1", "%mm2", "%mm3",
2589   "%mm4", "%mm5", "%mm6", "%mm7"
2590 };
2591
2592 static const char *intel_names_bnd[] = {
2593   "bnd0", "bnd1", "bnd2", "bnd3"
2594 };
2595
2596 static const char *att_names_bnd[] = {
2597   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2598 };
2599
2600 static const char **names_xmm;
2601 static const char *intel_names_xmm[] = {
2602   "xmm0", "xmm1", "xmm2", "xmm3",
2603   "xmm4", "xmm5", "xmm6", "xmm7",
2604   "xmm8", "xmm9", "xmm10", "xmm11",
2605   "xmm12", "xmm13", "xmm14", "xmm15",
2606   "xmm16", "xmm17", "xmm18", "xmm19",
2607   "xmm20", "xmm21", "xmm22", "xmm23",
2608   "xmm24", "xmm25", "xmm26", "xmm27",
2609   "xmm28", "xmm29", "xmm30", "xmm31"
2610 };
2611 static const char *att_names_xmm[] = {
2612   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2613   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2614   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2615   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2616   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2617   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2618   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2619   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2620 };
2621
2622 static const char **names_ymm;
2623 static const char *intel_names_ymm[] = {
2624   "ymm0", "ymm1", "ymm2", "ymm3",
2625   "ymm4", "ymm5", "ymm6", "ymm7",
2626   "ymm8", "ymm9", "ymm10", "ymm11",
2627   "ymm12", "ymm13", "ymm14", "ymm15",
2628   "ymm16", "ymm17", "ymm18", "ymm19",
2629   "ymm20", "ymm21", "ymm22", "ymm23",
2630   "ymm24", "ymm25", "ymm26", "ymm27",
2631   "ymm28", "ymm29", "ymm30", "ymm31"
2632 };
2633 static const char *att_names_ymm[] = {
2634   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2635   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2636   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2637   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2638   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2639   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2640   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2641   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2642 };
2643
2644 static const char **names_zmm;
2645 static const char *intel_names_zmm[] = {
2646   "zmm0", "zmm1", "zmm2", "zmm3",
2647   "zmm4", "zmm5", "zmm6", "zmm7",
2648   "zmm8", "zmm9", "zmm10", "zmm11",
2649   "zmm12", "zmm13", "zmm14", "zmm15",
2650   "zmm16", "zmm17", "zmm18", "zmm19",
2651   "zmm20", "zmm21", "zmm22", "zmm23",
2652   "zmm24", "zmm25", "zmm26", "zmm27",
2653   "zmm28", "zmm29", "zmm30", "zmm31"
2654 };
2655 static const char *att_names_zmm[] = {
2656   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2657   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2658   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2659   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2660   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2661   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2662   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2663   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2664 };
2665
2666 static const char **names_tmm;
2667 static const char *intel_names_tmm[] = {
2668   "tmm0", "tmm1", "tmm2", "tmm3",
2669   "tmm4", "tmm5", "tmm6", "tmm7"
2670 };
2671 static const char *att_names_tmm[] = {
2672   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2673   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2674 };
2675
2676 static const char **names_mask;
2677 static const char *intel_names_mask[] = {
2678   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2679 };
2680 static const char *att_names_mask[] = {
2681   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2682 };
2683
2684 static const char *names_rounding[] =
2685 {
2686   "{rn-sae}",
2687   "{rd-sae}",
2688   "{ru-sae}",
2689   "{rz-sae}"
2690 };
2691
2692 static const struct dis386 reg_table[][8] = {
2693   /* REG_80 */
2694   {
2695     { "addA",   { Ebh1, Ib }, 0 },
2696     { "orA",    { Ebh1, Ib }, 0 },
2697     { "adcA",   { Ebh1, Ib }, 0 },
2698     { "sbbA",   { Ebh1, Ib }, 0 },
2699     { "andA",   { Ebh1, Ib }, 0 },
2700     { "subA",   { Ebh1, Ib }, 0 },
2701     { "xorA",   { Ebh1, Ib }, 0 },
2702     { "cmpA",   { Eb, Ib }, 0 },
2703   },
2704   /* REG_81 */
2705   {
2706     { "addQ",   { Evh1, Iv }, 0 },
2707     { "orQ",    { Evh1, Iv }, 0 },
2708     { "adcQ",   { Evh1, Iv }, 0 },
2709     { "sbbQ",   { Evh1, Iv }, 0 },
2710     { "andQ",   { Evh1, Iv }, 0 },
2711     { "subQ",   { Evh1, Iv }, 0 },
2712     { "xorQ",   { Evh1, Iv }, 0 },
2713     { "cmpQ",   { Ev, Iv }, 0 },
2714   },
2715   /* REG_83 */
2716   {
2717     { "addQ",   { Evh1, sIb }, 0 },
2718     { "orQ",    { Evh1, sIb }, 0 },
2719     { "adcQ",   { Evh1, sIb }, 0 },
2720     { "sbbQ",   { Evh1, sIb }, 0 },
2721     { "andQ",   { Evh1, sIb }, 0 },
2722     { "subQ",   { Evh1, sIb }, 0 },
2723     { "xorQ",   { Evh1, sIb }, 0 },
2724     { "cmpQ",   { Ev, sIb }, 0 },
2725   },
2726   /* REG_8F */
2727   {
2728     { "pop{P|}", { stackEv }, 0 },
2729     { XOP_8F_TABLE (XOP_09) },
2730     { Bad_Opcode },
2731     { Bad_Opcode },
2732     { Bad_Opcode },
2733     { XOP_8F_TABLE (XOP_09) },
2734   },
2735   /* REG_C0 */
2736   {
2737     { "rolA",   { Eb, Ib }, 0 },
2738     { "rorA",   { Eb, Ib }, 0 },
2739     { "rclA",   { Eb, Ib }, 0 },
2740     { "rcrA",   { Eb, Ib }, 0 },
2741     { "shlA",   { Eb, Ib }, 0 },
2742     { "shrA",   { Eb, Ib }, 0 },
2743     { "shlA",   { Eb, Ib }, 0 },
2744     { "sarA",   { Eb, Ib }, 0 },
2745   },
2746   /* REG_C1 */
2747   {
2748     { "rolQ",   { Ev, Ib }, 0 },
2749     { "rorQ",   { Ev, Ib }, 0 },
2750     { "rclQ",   { Ev, Ib }, 0 },
2751     { "rcrQ",   { Ev, Ib }, 0 },
2752     { "shlQ",   { Ev, Ib }, 0 },
2753     { "shrQ",   { Ev, Ib }, 0 },
2754     { "shlQ",   { Ev, Ib }, 0 },
2755     { "sarQ",   { Ev, Ib }, 0 },
2756   },
2757   /* REG_C6 */
2758   {
2759     { "movA",   { Ebh3, Ib }, 0 },
2760     { Bad_Opcode },
2761     { Bad_Opcode },
2762     { Bad_Opcode },
2763     { Bad_Opcode },
2764     { Bad_Opcode },
2765     { Bad_Opcode },
2766     { MOD_TABLE (MOD_C6_REG_7) },
2767   },
2768   /* REG_C7 */
2769   {
2770     { "movQ",   { Evh3, Iv }, 0 },
2771     { Bad_Opcode },
2772     { Bad_Opcode },
2773     { Bad_Opcode },
2774     { Bad_Opcode },
2775     { Bad_Opcode },
2776     { Bad_Opcode },
2777     { MOD_TABLE (MOD_C7_REG_7) },
2778   },
2779   /* REG_D0 */
2780   {
2781     { "rolA",   { Eb, I1 }, 0 },
2782     { "rorA",   { Eb, I1 }, 0 },
2783     { "rclA",   { Eb, I1 }, 0 },
2784     { "rcrA",   { Eb, I1 }, 0 },
2785     { "shlA",   { Eb, I1 }, 0 },
2786     { "shrA",   { Eb, I1 }, 0 },
2787     { "shlA",   { Eb, I1 }, 0 },
2788     { "sarA",   { Eb, I1 }, 0 },
2789   },
2790   /* REG_D1 */
2791   {
2792     { "rolQ",   { Ev, I1 }, 0 },
2793     { "rorQ",   { Ev, I1 }, 0 },
2794     { "rclQ",   { Ev, I1 }, 0 },
2795     { "rcrQ",   { Ev, I1 }, 0 },
2796     { "shlQ",   { Ev, I1 }, 0 },
2797     { "shrQ",   { Ev, I1 }, 0 },
2798     { "shlQ",   { Ev, I1 }, 0 },
2799     { "sarQ",   { Ev, I1 }, 0 },
2800   },
2801   /* REG_D2 */
2802   {
2803     { "rolA",   { Eb, CL }, 0 },
2804     { "rorA",   { Eb, CL }, 0 },
2805     { "rclA",   { Eb, CL }, 0 },
2806     { "rcrA",   { Eb, CL }, 0 },
2807     { "shlA",   { Eb, CL }, 0 },
2808     { "shrA",   { Eb, CL }, 0 },
2809     { "shlA",   { Eb, CL }, 0 },
2810     { "sarA",   { Eb, CL }, 0 },
2811   },
2812   /* REG_D3 */
2813   {
2814     { "rolQ",   { Ev, CL }, 0 },
2815     { "rorQ",   { Ev, CL }, 0 },
2816     { "rclQ",   { Ev, CL }, 0 },
2817     { "rcrQ",   { Ev, CL }, 0 },
2818     { "shlQ",   { Ev, CL }, 0 },
2819     { "shrQ",   { Ev, CL }, 0 },
2820     { "shlQ",   { Ev, CL }, 0 },
2821     { "sarQ",   { Ev, CL }, 0 },
2822   },
2823   /* REG_F6 */
2824   {
2825     { "testA",  { Eb, Ib }, 0 },
2826     { "testA",  { Eb, Ib }, 0 },
2827     { "notA",   { Ebh1 }, 0 },
2828     { "negA",   { Ebh1 }, 0 },
2829     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
2830     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
2831     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
2832     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
2833   },
2834   /* REG_F7 */
2835   {
2836     { "testQ",  { Ev, Iv }, 0 },
2837     { "testQ",  { Ev, Iv }, 0 },
2838     { "notQ",   { Evh1 }, 0 },
2839     { "negQ",   { Evh1 }, 0 },
2840     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
2841     { "imulQ",  { Ev }, 0 },
2842     { "divQ",   { Ev }, 0 },
2843     { "idivQ",  { Ev }, 0 },
2844   },
2845   /* REG_FE */
2846   {
2847     { "incA",   { Ebh1 }, 0 },
2848     { "decA",   { Ebh1 }, 0 },
2849   },
2850   /* REG_FF */
2851   {
2852     { "incQ",   { Evh1 }, 0 },
2853     { "decQ",   { Evh1 }, 0 },
2854     { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2855     { MOD_TABLE (MOD_FF_REG_3) },
2856     { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2857     { MOD_TABLE (MOD_FF_REG_5) },
2858     { "push{P|}", { stackEv }, 0 },
2859     { Bad_Opcode },
2860   },
2861   /* REG_0F00 */
2862   {
2863     { "sldtD",  { Sv }, 0 },
2864     { "strD",   { Sv }, 0 },
2865     { "lldt",   { Ew }, 0 },
2866     { "ltr",    { Ew }, 0 },
2867     { "verr",   { Ew }, 0 },
2868     { "verw",   { Ew }, 0 },
2869     { Bad_Opcode },
2870     { Bad_Opcode },
2871   },
2872   /* REG_0F01 */
2873   {
2874     { MOD_TABLE (MOD_0F01_REG_0) },
2875     { MOD_TABLE (MOD_0F01_REG_1) },
2876     { MOD_TABLE (MOD_0F01_REG_2) },
2877     { MOD_TABLE (MOD_0F01_REG_3) },
2878     { "smswD",  { Sv }, 0 },
2879     { MOD_TABLE (MOD_0F01_REG_5) },
2880     { "lmsw",   { Ew }, 0 },
2881     { MOD_TABLE (MOD_0F01_REG_7) },
2882   },
2883   /* REG_0F0D */
2884   {
2885     { "prefetch",       { Mb }, 0 },
2886     { "prefetchw",      { Mb }, 0 },
2887     { "prefetchwt1",    { Mb }, 0 },
2888     { "prefetch",       { Mb }, 0 },
2889     { "prefetch",       { Mb }, 0 },
2890     { "prefetch",       { Mb }, 0 },
2891     { "prefetch",       { Mb }, 0 },
2892     { "prefetch",       { Mb }, 0 },
2893   },
2894   /* REG_0F18 */
2895   {
2896     { MOD_TABLE (MOD_0F18_REG_0) },
2897     { MOD_TABLE (MOD_0F18_REG_1) },
2898     { MOD_TABLE (MOD_0F18_REG_2) },
2899     { MOD_TABLE (MOD_0F18_REG_3) },
2900     { MOD_TABLE (MOD_0F18_REG_4) },
2901     { MOD_TABLE (MOD_0F18_REG_5) },
2902     { MOD_TABLE (MOD_0F18_REG_6) },
2903     { MOD_TABLE (MOD_0F18_REG_7) },
2904   },
2905   /* REG_0F1C_P_0_MOD_0 */
2906   {
2907     { "cldemote",       { Mb }, 0 },
2908     { "nopQ",           { Ev }, 0 },
2909     { "nopQ",           { Ev }, 0 },
2910     { "nopQ",           { Ev }, 0 },
2911     { "nopQ",           { Ev }, 0 },
2912     { "nopQ",           { Ev }, 0 },
2913     { "nopQ",           { Ev }, 0 },
2914     { "nopQ",           { Ev }, 0 },
2915   },
2916   /* REG_0F1E_P_1_MOD_3 */
2917   {
2918     { "nopQ",           { Ev }, 0 },
2919     { "rdsspK",         { Edq }, PREFIX_OPCODE },
2920     { "nopQ",           { Ev }, 0 },
2921     { "nopQ",           { Ev }, 0 },
2922     { "nopQ",           { Ev }, 0 },
2923     { "nopQ",           { Ev }, 0 },
2924     { "nopQ",           { Ev }, 0 },
2925     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2926   },
2927   /* REG_0F38D8_PREFIX_1 */
2928   {
2929     { "aesencwide128kl",        { M }, 0 },
2930     { "aesdecwide128kl",        { M }, 0 },
2931     { "aesencwide256kl",        { M }, 0 },
2932     { "aesdecwide256kl",        { M }, 0 },
2933   },
2934   /* REG_0F3A0F_PREFIX_1_MOD_3 */
2935   {
2936     { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2937   },
2938   /* REG_0F71 */
2939   {
2940     { Bad_Opcode },
2941     { Bad_Opcode },
2942     { MOD_TABLE (MOD_0F71_REG_2) },
2943     { Bad_Opcode },
2944     { MOD_TABLE (MOD_0F71_REG_4) },
2945     { Bad_Opcode },
2946     { MOD_TABLE (MOD_0F71_REG_6) },
2947   },
2948   /* REG_0F72 */
2949   {
2950     { Bad_Opcode },
2951     { Bad_Opcode },
2952     { MOD_TABLE (MOD_0F72_REG_2) },
2953     { Bad_Opcode },
2954     { MOD_TABLE (MOD_0F72_REG_4) },
2955     { Bad_Opcode },
2956     { MOD_TABLE (MOD_0F72_REG_6) },
2957   },
2958   /* REG_0F73 */
2959   {
2960     { Bad_Opcode },
2961     { Bad_Opcode },
2962     { MOD_TABLE (MOD_0F73_REG_2) },
2963     { MOD_TABLE (MOD_0F73_REG_3) },
2964     { Bad_Opcode },
2965     { Bad_Opcode },
2966     { MOD_TABLE (MOD_0F73_REG_6) },
2967     { MOD_TABLE (MOD_0F73_REG_7) },
2968   },
2969   /* REG_0FA6 */
2970   {
2971     { "montmul",        { { OP_0f07, 0 } }, 0 },
2972     { "xsha1",          { { OP_0f07, 0 } }, 0 },
2973     { "xsha256",        { { OP_0f07, 0 } }, 0 },
2974   },
2975   /* REG_0FA7 */
2976   {
2977     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
2978     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
2979     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
2980     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
2981     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
2982     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
2983   },
2984   /* REG_0FAE */
2985   {
2986     { MOD_TABLE (MOD_0FAE_REG_0) },
2987     { MOD_TABLE (MOD_0FAE_REG_1) },
2988     { MOD_TABLE (MOD_0FAE_REG_2) },
2989     { MOD_TABLE (MOD_0FAE_REG_3) },
2990     { MOD_TABLE (MOD_0FAE_REG_4) },
2991     { MOD_TABLE (MOD_0FAE_REG_5) },
2992     { MOD_TABLE (MOD_0FAE_REG_6) },
2993     { MOD_TABLE (MOD_0FAE_REG_7) },
2994   },
2995   /* REG_0FBA */
2996   {
2997     { Bad_Opcode },
2998     { Bad_Opcode },
2999     { Bad_Opcode },
3000     { Bad_Opcode },
3001     { "btQ",    { Ev, Ib }, 0 },
3002     { "btsQ",   { Evh1, Ib }, 0 },
3003     { "btrQ",   { Evh1, Ib }, 0 },
3004     { "btcQ",   { Evh1, Ib }, 0 },
3005   },
3006   /* REG_0FC7 */
3007   {
3008     { Bad_Opcode },
3009     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3010     { Bad_Opcode },
3011     { MOD_TABLE (MOD_0FC7_REG_3) },
3012     { MOD_TABLE (MOD_0FC7_REG_4) },
3013     { MOD_TABLE (MOD_0FC7_REG_5) },
3014     { MOD_TABLE (MOD_0FC7_REG_6) },
3015     { MOD_TABLE (MOD_0FC7_REG_7) },
3016   },
3017   /* REG_VEX_0F71 */
3018   {
3019     { Bad_Opcode },
3020     { Bad_Opcode },
3021     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3022     { Bad_Opcode },
3023     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3024     { Bad_Opcode },
3025     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3026   },
3027   /* REG_VEX_0F72 */
3028   {
3029     { Bad_Opcode },
3030     { Bad_Opcode },
3031     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3032     { Bad_Opcode },
3033     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3034     { Bad_Opcode },
3035     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3036   },
3037   /* REG_VEX_0F73 */
3038   {
3039     { Bad_Opcode },
3040     { Bad_Opcode },
3041     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3042     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3043     { Bad_Opcode },
3044     { Bad_Opcode },
3045     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3046     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3047   },
3048   /* REG_VEX_0FAE */
3049   {
3050     { Bad_Opcode },
3051     { Bad_Opcode },
3052     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3053     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3054   },
3055   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3056   {
3057     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
3058   },
3059   /* REG_VEX_0F38F3 */
3060   {
3061     { Bad_Opcode },
3062     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1) },
3063     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2) },
3064     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3) },
3065   },
3066   /* REG_0FXOP_09_01_L_0 */
3067   {
3068     { Bad_Opcode },
3069     { "blcfill",        { VexGdq, Edq }, 0 },
3070     { "blsfill",        { VexGdq, Edq }, 0 },
3071     { "blcs",   { VexGdq, Edq }, 0 },
3072     { "tzmsk",  { VexGdq, Edq }, 0 },
3073     { "blcic",  { VexGdq, Edq }, 0 },
3074     { "blsic",  { VexGdq, Edq }, 0 },
3075     { "t1mskc", { VexGdq, Edq }, 0 },
3076   },
3077   /* REG_0FXOP_09_02_L_0 */
3078   {
3079     { Bad_Opcode },
3080     { "blcmsk", { VexGdq, Edq }, 0 },
3081     { Bad_Opcode },
3082     { Bad_Opcode },
3083     { Bad_Opcode },
3084     { Bad_Opcode },
3085     { "blci",   { VexGdq, Edq }, 0 },
3086   },
3087   /* REG_0FXOP_09_12_M_1_L_0 */
3088   {
3089     { "llwpcb", { Edq }, 0 },
3090     { "slwpcb", { Edq }, 0 },
3091   },
3092   /* REG_0FXOP_0A_12_L_0 */
3093   {
3094     { "lwpins", { VexGdq, Ed, Id }, 0 },
3095     { "lwpval", { VexGdq, Ed, Id }, 0 },
3096   },
3097
3098 #include "i386-dis-evex-reg.h"
3099 };
3100
3101 static const struct dis386 prefix_table[][4] = {
3102   /* PREFIX_90 */
3103   {
3104     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3105     { "pause", { XX }, 0 },
3106     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3107     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3108   },
3109
3110   /* PREFIX_0F01_REG_1_RM_4 */
3111   {
3112     { Bad_Opcode },
3113     { Bad_Opcode },
3114     { "tdcall",         { Skip_MODRM }, 0 },
3115     { Bad_Opcode },
3116   },
3117
3118   /* PREFIX_0F01_REG_1_RM_5 */
3119   {
3120     { Bad_Opcode },
3121     { Bad_Opcode },
3122     { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3123     { Bad_Opcode },
3124   },
3125
3126   /* PREFIX_0F01_REG_1_RM_6 */
3127   {
3128     { Bad_Opcode },
3129     { Bad_Opcode },
3130     { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3131     { Bad_Opcode },
3132   },
3133
3134   /* PREFIX_0F01_REG_1_RM_7 */
3135   {
3136     { "encls",          { Skip_MODRM }, 0 },
3137     { Bad_Opcode },
3138     { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3139     { Bad_Opcode },
3140   },
3141
3142   /* PREFIX_0F01_REG_3_RM_1 */
3143   {
3144     { "vmmcall",        { Skip_MODRM }, 0 },
3145     { "vmgexit",        { Skip_MODRM }, 0 },
3146     { Bad_Opcode },
3147     { "vmgexit",        { Skip_MODRM }, 0 },
3148   },
3149
3150   /* PREFIX_0F01_REG_5_MOD_0 */
3151   {
3152     { Bad_Opcode },
3153     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3154   },
3155
3156   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3157   {
3158     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3159     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3160     { Bad_Opcode },
3161     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3162   },
3163
3164   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3165   {
3166     { Bad_Opcode },
3167     { Bad_Opcode },
3168     { Bad_Opcode },
3169     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3170   },
3171
3172   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3173   {
3174     { Bad_Opcode },
3175     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3176   },
3177
3178   /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3179   {
3180     { Bad_Opcode },
3181     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3182   },
3183
3184   /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3185   {
3186     { Bad_Opcode },
3187     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3188   },
3189
3190   /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3191   {
3192     { "rdpkru", { Skip_MODRM }, 0 },
3193     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3194   },
3195
3196   /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3197   {
3198     { "wrpkru", { Skip_MODRM }, 0 },
3199     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3200   },
3201
3202   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3203   {
3204     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3205     { "mcommit",        { Skip_MODRM }, 0 },
3206   },
3207
3208   /* PREFIX_0F09 */
3209   {
3210     { "wbinvd",   { XX }, 0 },
3211     { "wbnoinvd", { XX }, 0 },
3212   },
3213
3214   /* PREFIX_0F10 */
3215   {
3216     { "movups", { XM, EXx }, PREFIX_OPCODE },
3217     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3218     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3219     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3220   },
3221
3222   /* PREFIX_0F11 */
3223   {
3224     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3225     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3226     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3227     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3228   },
3229
3230   /* PREFIX_0F12 */
3231   {
3232     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3233     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3234     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3235     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3236   },
3237
3238   /* PREFIX_0F16 */
3239   {
3240     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3241     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3242     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3243   },
3244
3245   /* PREFIX_0F1A */
3246   {
3247     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3248     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3249     { "bndmov", { Gbnd, Ebnd }, 0 },
3250     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3251   },
3252
3253   /* PREFIX_0F1B */
3254   {
3255     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3256     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3257     { "bndmov", { EbndS, Gbnd }, 0 },
3258     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3259   },
3260
3261   /* PREFIX_0F1C */
3262   {
3263     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3264     { "nopQ",   { Ev }, PREFIX_OPCODE },
3265     { "nopQ",   { Ev }, PREFIX_OPCODE },
3266     { "nopQ",   { Ev }, PREFIX_OPCODE },
3267   },
3268
3269   /* PREFIX_0F1E */
3270   {
3271     { "nopQ",   { Ev }, PREFIX_OPCODE },
3272     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3273     { "nopQ",   { Ev }, PREFIX_OPCODE },
3274     { "nopQ",   { Ev }, PREFIX_OPCODE },
3275   },
3276
3277   /* PREFIX_0F2A */
3278   {
3279     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3280     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3281     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3282     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3283   },
3284
3285   /* PREFIX_0F2B */
3286   {
3287     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3288     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3289     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3290     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3291   },
3292
3293   /* PREFIX_0F2C */
3294   {
3295     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3296     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3297     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3298     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3299   },
3300
3301   /* PREFIX_0F2D */
3302   {
3303     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3304     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3305     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3306     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3307   },
3308
3309   /* PREFIX_0F2E */
3310   {
3311     { "ucomiss",{ XM, EXd }, 0 },
3312     { Bad_Opcode },
3313     { "ucomisd",{ XM, EXq }, 0 },
3314   },
3315
3316   /* PREFIX_0F2F */
3317   {
3318     { "comiss", { XM, EXd }, 0 },
3319     { Bad_Opcode },
3320     { "comisd", { XM, EXq }, 0 },
3321   },
3322
3323   /* PREFIX_0F51 */
3324   {
3325     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3326     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3327     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3328     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3329   },
3330
3331   /* PREFIX_0F52 */
3332   {
3333     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3334     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3335   },
3336
3337   /* PREFIX_0F53 */
3338   {
3339     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3340     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3341   },
3342
3343   /* PREFIX_0F58 */
3344   {
3345     { "addps", { XM, EXx }, PREFIX_OPCODE },
3346     { "addss", { XM, EXd }, PREFIX_OPCODE },
3347     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3348     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3349   },
3350
3351   /* PREFIX_0F59 */
3352   {
3353     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3354     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3355     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3356     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3357   },
3358
3359   /* PREFIX_0F5A */
3360   {
3361     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3362     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3363     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3364     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3365   },
3366
3367   /* PREFIX_0F5B */
3368   {
3369     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3370     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3371     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3372   },
3373
3374   /* PREFIX_0F5C */
3375   {
3376     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3377     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3378     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3379     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3380   },
3381
3382   /* PREFIX_0F5D */
3383   {
3384     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3385     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3386     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3387     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3388   },
3389
3390   /* PREFIX_0F5E */
3391   {
3392     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3393     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3394     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3395     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3396   },
3397
3398   /* PREFIX_0F5F */
3399   {
3400     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3401     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3402     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3403     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3404   },
3405
3406   /* PREFIX_0F60 */
3407   {
3408     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3409     { Bad_Opcode },
3410     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3411   },
3412
3413   /* PREFIX_0F61 */
3414   {
3415     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3416     { Bad_Opcode },
3417     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3418   },
3419
3420   /* PREFIX_0F62 */
3421   {
3422     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3423     { Bad_Opcode },
3424     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3425   },
3426
3427   /* PREFIX_0F6F */
3428   {
3429     { "movq",   { MX, EM }, PREFIX_OPCODE },
3430     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3431     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3432   },
3433
3434   /* PREFIX_0F70 */
3435   {
3436     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3437     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3438     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3439     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3440   },
3441
3442   /* PREFIX_0F78 */
3443   {
3444     {"vmread",  { Em, Gm }, 0 },
3445     { Bad_Opcode },
3446     {"extrq",   { XS, Ib, Ib }, 0 },
3447     {"insertq", { XM, XS, Ib, Ib }, 0 },
3448   },
3449
3450   /* PREFIX_0F79 */
3451   {
3452     {"vmwrite", { Gm, Em }, 0 },
3453     { Bad_Opcode },
3454     {"extrq",   { XM, XS }, 0 },
3455     {"insertq", { XM, XS }, 0 },
3456   },
3457
3458   /* PREFIX_0F7C */
3459   {
3460     { Bad_Opcode },
3461     { Bad_Opcode },
3462     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3463     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3464   },
3465
3466   /* PREFIX_0F7D */
3467   {
3468     { Bad_Opcode },
3469     { Bad_Opcode },
3470     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3471     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3472   },
3473
3474   /* PREFIX_0F7E */
3475   {
3476     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3477     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3478     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3479   },
3480
3481   /* PREFIX_0F7F */
3482   {
3483     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3484     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3485     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3486   },
3487
3488   /* PREFIX_0FAE_REG_0_MOD_3 */
3489   {
3490     { Bad_Opcode },
3491     { "rdfsbase", { Ev }, 0 },
3492   },
3493
3494   /* PREFIX_0FAE_REG_1_MOD_3 */
3495   {
3496     { Bad_Opcode },
3497     { "rdgsbase", { Ev }, 0 },
3498   },
3499
3500   /* PREFIX_0FAE_REG_2_MOD_3 */
3501   {
3502     { Bad_Opcode },
3503     { "wrfsbase", { Ev }, 0 },
3504   },
3505
3506   /* PREFIX_0FAE_REG_3_MOD_3 */
3507   {
3508     { Bad_Opcode },
3509     { "wrgsbase", { Ev }, 0 },
3510   },
3511
3512   /* PREFIX_0FAE_REG_4_MOD_0 */
3513   {
3514     { "xsave",  { FXSAVE }, 0 },
3515     { "ptwrite{%LQ|}", { Edq }, 0 },
3516   },
3517
3518   /* PREFIX_0FAE_REG_4_MOD_3 */
3519   {
3520     { Bad_Opcode },
3521     { "ptwrite{%LQ|}", { Edq }, 0 },
3522   },
3523
3524   /* PREFIX_0FAE_REG_5_MOD_3 */
3525   {
3526     { "lfence",         { Skip_MODRM }, 0 },
3527     { "incsspK",        { Edq }, PREFIX_OPCODE },
3528   },
3529
3530   /* PREFIX_0FAE_REG_6_MOD_0 */
3531   {
3532     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3533     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3534     { "clwb",   { Mb }, PREFIX_OPCODE },
3535   },
3536
3537   /* PREFIX_0FAE_REG_6_MOD_3 */
3538   {
3539     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3540     { "umonitor",       { Eva }, PREFIX_OPCODE },
3541     { "tpause", { Edq }, PREFIX_OPCODE },
3542     { "umwait", { Edq }, PREFIX_OPCODE },
3543   },
3544
3545   /* PREFIX_0FAE_REG_7_MOD_0 */
3546   {
3547     { "clflush",        { Mb }, 0 },
3548     { Bad_Opcode },
3549     { "clflushopt",     { Mb }, 0 },
3550   },
3551
3552   /* PREFIX_0FB8 */
3553   {
3554     { Bad_Opcode },
3555     { "popcntS", { Gv, Ev }, 0 },
3556   },
3557
3558   /* PREFIX_0FBC */
3559   {
3560     { "bsfS",   { Gv, Ev }, 0 },
3561     { "tzcntS", { Gv, Ev }, 0 },
3562     { "bsfS",   { Gv, Ev }, 0 },
3563   },
3564
3565   /* PREFIX_0FBD */
3566   {
3567     { "bsrS",   { Gv, Ev }, 0 },
3568     { "lzcntS", { Gv, Ev }, 0 },
3569     { "bsrS",   { Gv, Ev }, 0 },
3570   },
3571
3572   /* PREFIX_0FC2 */
3573   {
3574     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3575     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3576     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3577     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3578   },
3579
3580   /* PREFIX_0FC7_REG_6_MOD_0 */
3581   {
3582     { "vmptrld",{ Mq }, 0 },
3583     { "vmxon",  { Mq }, 0 },
3584     { "vmclear",{ Mq }, 0 },
3585   },
3586
3587   /* PREFIX_0FC7_REG_6_MOD_3 */
3588   {
3589     { "rdrand", { Ev }, 0 },
3590     { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3591     { "rdrand", { Ev }, 0 }
3592   },
3593
3594   /* PREFIX_0FC7_REG_7_MOD_3 */
3595   {
3596     { "rdseed", { Ev }, 0 },
3597     { "rdpid",  { Em }, 0 },
3598     { "rdseed", { Ev }, 0 },
3599   },
3600
3601   /* PREFIX_0FD0 */
3602   {
3603     { Bad_Opcode },
3604     { Bad_Opcode },
3605     { "addsubpd", { XM, EXx }, 0 },
3606     { "addsubps", { XM, EXx }, 0 },
3607   },
3608
3609   /* PREFIX_0FD6 */
3610   {
3611     { Bad_Opcode },
3612     { "movq2dq",{ XM, MS }, 0 },
3613     { "movq",   { EXqS, XM }, 0 },
3614     { "movdq2q",{ MX, XS }, 0 },
3615   },
3616
3617   /* PREFIX_0FE6 */
3618   {
3619     { Bad_Opcode },
3620     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3621     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3622     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3623   },
3624
3625   /* PREFIX_0FE7 */
3626   {
3627     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3628     { Bad_Opcode },
3629     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3630   },
3631
3632   /* PREFIX_0FF0 */
3633   {
3634     { Bad_Opcode },
3635     { Bad_Opcode },
3636     { Bad_Opcode },
3637     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3638   },
3639
3640   /* PREFIX_0FF7 */
3641   {
3642     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3643     { Bad_Opcode },
3644     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3645   },
3646
3647   /* PREFIX_0F38D8 */
3648   {
3649     { Bad_Opcode },
3650     { REG_TABLE (REG_0F38D8_PREFIX_1) },
3651   },
3652
3653   /* PREFIX_0F38DC */
3654   {
3655     { Bad_Opcode },
3656     { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3657     { "aesenc", { XM, EXx }, 0 },
3658   },
3659
3660   /* PREFIX_0F38DD */
3661   {
3662     { Bad_Opcode },
3663     { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3664     { "aesenclast", { XM, EXx }, 0 },
3665   },
3666
3667   /* PREFIX_0F38DE */
3668   {
3669     { Bad_Opcode },
3670     { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3671     { "aesdec", { XM, EXx }, 0 },
3672   },
3673
3674   /* PREFIX_0F38DF */
3675   {
3676     { Bad_Opcode },
3677     { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3678     { "aesdeclast", { XM, EXx }, 0 },
3679   },
3680
3681   /* PREFIX_0F38F0 */
3682   {
3683     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3684     { Bad_Opcode },
3685     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3686     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3687   },
3688
3689   /* PREFIX_0F38F1 */
3690   {
3691     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3692     { Bad_Opcode },
3693     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3694     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3695   },
3696
3697   /* PREFIX_0F38F6 */
3698   {
3699     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3700     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
3701     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
3702     { Bad_Opcode },
3703   },
3704
3705   /* PREFIX_0F38F8 */
3706   {
3707     { Bad_Opcode },
3708     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3709     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3710     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3711   },
3712   /* PREFIX_0F38FA */
3713   {
3714     { Bad_Opcode },
3715     { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3716   },
3717
3718   /* PREFIX_0F38FB */
3719   {
3720     { Bad_Opcode },
3721     { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3722   },
3723
3724   /* PREFIX_0F3A0F */
3725   {
3726     { Bad_Opcode },
3727     { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3728   },
3729
3730   /* PREFIX_VEX_0F10 */
3731   {
3732     { "vmovups",        { XM, EXx }, 0 },
3733     { "vmovss",         { XMScalar, VexScalarR, EXxmm_md }, 0 },
3734     { "vmovupd",        { XM, EXx }, 0 },
3735     { "vmovsd",         { XMScalar, VexScalarR, EXxmm_mq }, 0 },
3736   },
3737
3738   /* PREFIX_VEX_0F11 */
3739   {
3740     { "vmovups",        { EXxS, XM }, 0 },
3741     { "vmovss",         { EXdS, VexScalarR, XMScalar }, 0 },
3742     { "vmovupd",        { EXxS, XM }, 0 },
3743     { "vmovsd",         { EXqS, VexScalarR, XMScalar }, 0 },
3744   },
3745
3746   /* PREFIX_VEX_0F12 */
3747   {
3748     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3749     { "vmovsldup",      { XM, EXx }, 0 },
3750     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3751     { "vmovddup",       { XM, EXymmq }, 0 },
3752   },
3753
3754   /* PREFIX_VEX_0F16 */
3755   {
3756     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3757     { "vmovshdup",      { XM, EXx }, 0 },
3758     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3759   },
3760
3761   /* PREFIX_VEX_0F2A */
3762   {
3763     { Bad_Opcode },
3764     { "vcvtsi2ss{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
3765     { Bad_Opcode },
3766     { "vcvtsi2sd{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
3767   },
3768
3769   /* PREFIX_VEX_0F2C */
3770   {
3771     { Bad_Opcode },
3772     { "vcvttss2si",     { Gdq, EXxmm_md, EXxEVexS }, 0 },
3773     { Bad_Opcode },
3774     { "vcvttsd2si",     { Gdq, EXxmm_mq, EXxEVexS }, 0 },
3775   },
3776
3777   /* PREFIX_VEX_0F2D */
3778   {
3779     { Bad_Opcode },
3780     { "vcvtss2si",      { Gdq, EXxmm_md, EXxEVexR }, 0 },
3781     { Bad_Opcode },
3782     { "vcvtsd2si",      { Gdq, EXxmm_mq, EXxEVexR }, 0 },
3783   },
3784
3785   /* PREFIX_VEX_0F2E */
3786   {
3787     { "vucomisX",       { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3788     { Bad_Opcode },
3789     { "vucomisX",       { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3790   },
3791
3792   /* PREFIX_VEX_0F2F */
3793   {
3794     { "vcomisX",        { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3795     { Bad_Opcode },
3796     { "vcomisX",        { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3797   },
3798
3799   /* PREFIX_VEX_0F41 */
3800   {
3801     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
3802     { Bad_Opcode },
3803     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
3804   },
3805
3806   /* PREFIX_VEX_0F42 */
3807   {
3808     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
3809     { Bad_Opcode },
3810     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
3811   },
3812
3813   /* PREFIX_VEX_0F44 */
3814   {
3815     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
3816     { Bad_Opcode },
3817     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
3818   },
3819
3820   /* PREFIX_VEX_0F45 */
3821   {
3822     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
3823     { Bad_Opcode },
3824     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
3825   },
3826
3827   /* PREFIX_VEX_0F46 */
3828   {
3829     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
3830     { Bad_Opcode },
3831     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
3832   },
3833
3834   /* PREFIX_VEX_0F47 */
3835   {
3836     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
3837     { Bad_Opcode },
3838     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
3839   },
3840
3841   /* PREFIX_VEX_0F4A */
3842   {
3843     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
3844     { Bad_Opcode },
3845     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
3846   },
3847
3848   /* PREFIX_VEX_0F4B */
3849   {
3850     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
3851     { Bad_Opcode },
3852     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
3853   },
3854
3855   /* PREFIX_VEX_0F51 */
3856   {
3857     { "vsqrtps",        { XM, EXx }, 0 },
3858     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
3859     { "vsqrtpd",        { XM, EXx }, 0 },
3860     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
3861   },
3862
3863   /* PREFIX_VEX_0F52 */
3864   {
3865     { "vrsqrtps",       { XM, EXx }, 0 },
3866     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
3867   },
3868
3869   /* PREFIX_VEX_0F53 */
3870   {
3871     { "vrcpps",         { XM, EXx }, 0 },
3872     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3873   },
3874
3875   /* PREFIX_VEX_0F58 */
3876   {
3877     { "vaddps",         { XM, Vex, EXx }, 0 },
3878     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3879     { "vaddpd",         { XM, Vex, EXx }, 0 },
3880     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3881   },
3882
3883   /* PREFIX_VEX_0F59 */
3884   {
3885     { "vmulps",         { XM, Vex, EXx }, 0 },
3886     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3887     { "vmulpd",         { XM, Vex, EXx }, 0 },
3888     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3889   },
3890
3891   /* PREFIX_VEX_0F5A */
3892   {
3893     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
3894     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
3895     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
3896     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
3897   },
3898
3899   /* PREFIX_VEX_0F5B */
3900   {
3901     { "vcvtdq2ps",      { XM, EXx }, 0 },
3902     { "vcvttps2dq",     { XM, EXx }, 0 },
3903     { "vcvtps2dq",      { XM, EXx }, 0 },
3904   },
3905
3906   /* PREFIX_VEX_0F5C */
3907   {
3908     { "vsubps",         { XM, Vex, EXx }, 0 },
3909     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3910     { "vsubpd",         { XM, Vex, EXx }, 0 },
3911     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3912   },
3913
3914   /* PREFIX_VEX_0F5D */
3915   {
3916     { "vminps",         { XM, Vex, EXx }, 0 },
3917     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3918     { "vminpd",         { XM, Vex, EXx }, 0 },
3919     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3920   },
3921
3922   /* PREFIX_VEX_0F5E */
3923   {
3924     { "vdivps",         { XM, Vex, EXx }, 0 },
3925     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3926     { "vdivpd",         { XM, Vex, EXx }, 0 },
3927     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3928   },
3929
3930   /* PREFIX_VEX_0F5F */
3931   {
3932     { "vmaxps",         { XM, Vex, EXx }, 0 },
3933     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3934     { "vmaxpd",         { XM, Vex, EXx }, 0 },
3935     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3936   },
3937
3938   /* PREFIX_VEX_0F6F */
3939   {
3940     { Bad_Opcode },
3941     { "vmovdqu",        { XM, EXx }, 0 },
3942     { "vmovdqa",        { XM, EXx }, 0 },
3943   },
3944
3945   /* PREFIX_VEX_0F70 */
3946   {
3947     { Bad_Opcode },
3948     { "vpshufhw",       { XM, EXx, Ib }, 0 },
3949     { "vpshufd",        { XM, EXx, Ib }, 0 },
3950     { "vpshuflw",       { XM, EXx, Ib }, 0 },
3951   },
3952
3953   /* PREFIX_VEX_0F7C */
3954   {
3955     { Bad_Opcode },
3956     { Bad_Opcode },
3957     { "vhaddpd",        { XM, Vex, EXx }, 0 },
3958     { "vhaddps",        { XM, Vex, EXx }, 0 },
3959   },
3960
3961   /* PREFIX_VEX_0F7D */
3962   {
3963     { Bad_Opcode },
3964     { Bad_Opcode },
3965     { "vhsubpd",        { XM, Vex, EXx }, 0 },
3966     { "vhsubps",        { XM, Vex, EXx }, 0 },
3967   },
3968
3969   /* PREFIX_VEX_0F7E */
3970   {
3971     { Bad_Opcode },
3972     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3973     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3974   },
3975
3976   /* PREFIX_VEX_0F7F */
3977   {
3978     { Bad_Opcode },
3979     { "vmovdqu",        { EXxS, XM }, 0 },
3980     { "vmovdqa",        { EXxS, XM }, 0 },
3981   },
3982
3983   /* PREFIX_VEX_0F90 */
3984   {
3985     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
3986     { Bad_Opcode },
3987     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
3988   },
3989
3990   /* PREFIX_VEX_0F91 */
3991   {
3992     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
3993     { Bad_Opcode },
3994     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
3995   },
3996
3997   /* PREFIX_VEX_0F92 */
3998   {
3999     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
4000     { Bad_Opcode },
4001     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
4002     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
4003   },
4004
4005   /* PREFIX_VEX_0F93 */
4006   {
4007     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
4008     { Bad_Opcode },
4009     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
4010     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
4011   },
4012
4013   /* PREFIX_VEX_0F98 */
4014   {
4015     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
4016     { Bad_Opcode },
4017     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
4018   },
4019
4020   /* PREFIX_VEX_0F99 */
4021   {
4022     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
4023     { Bad_Opcode },
4024     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
4025   },
4026
4027   /* PREFIX_VEX_0FC2 */
4028   {
4029     { "vcmpps",         { XM, Vex, EXx, CMP }, 0 },
4030     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
4031     { "vcmppd",         { XM, Vex, EXx, CMP }, 0 },
4032     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
4033   },
4034
4035   /* PREFIX_VEX_0FD0 */
4036   {
4037     { Bad_Opcode },
4038     { Bad_Opcode },
4039     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
4040     { "vaddsubps",      { XM, Vex, EXx }, 0 },
4041   },
4042
4043   /* PREFIX_VEX_0FE6 */
4044   {
4045     { Bad_Opcode },
4046     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
4047     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
4048     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
4049   },
4050
4051   /* PREFIX_VEX_0FF0 */
4052   {
4053     { Bad_Opcode },
4054     { Bad_Opcode },
4055     { Bad_Opcode },
4056     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4057   },
4058
4059   /* PREFIX_VEX_0F3849_X86_64 */
4060   {
4061     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
4062     { Bad_Opcode },
4063     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
4064     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
4065   },
4066
4067   /* PREFIX_VEX_0F384B_X86_64 */
4068   {
4069     { Bad_Opcode },
4070     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4071     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4072     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4073   },
4074
4075   /* PREFIX_VEX_0F385C_X86_64 */
4076   {
4077     { Bad_Opcode },
4078     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4079     { Bad_Opcode },
4080   },
4081
4082   /* PREFIX_VEX_0F385E_X86_64 */
4083   {
4084     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4085     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4086     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4087     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4088   },
4089
4090   /* PREFIX_VEX_0F38F5 */
4091   {
4092     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
4093     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
4094     { Bad_Opcode },
4095     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
4096   },
4097
4098   /* PREFIX_VEX_0F38F6 */
4099   {
4100     { Bad_Opcode },
4101     { Bad_Opcode },
4102     { Bad_Opcode },
4103     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
4104   },
4105
4106   /* PREFIX_VEX_0F38F7 */
4107   {
4108     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
4109     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
4110     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
4111     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
4112   },
4113
4114   /* PREFIX_VEX_0F3AF0 */
4115   {
4116     { Bad_Opcode },
4117     { Bad_Opcode },
4118     { Bad_Opcode },
4119     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
4120   },
4121
4122 #include "i386-dis-evex-prefix.h"
4123 };
4124
4125 static const struct dis386 x86_64_table[][2] = {
4126   /* X86_64_06 */
4127   {
4128     { "pushP", { es }, 0 },
4129   },
4130
4131   /* X86_64_07 */
4132   {
4133     { "popP", { es }, 0 },
4134   },
4135
4136   /* X86_64_0E */
4137   {
4138     { "pushP", { cs }, 0 },
4139   },
4140
4141   /* X86_64_16 */
4142   {
4143     { "pushP", { ss }, 0 },
4144   },
4145
4146   /* X86_64_17 */
4147   {
4148     { "popP", { ss }, 0 },
4149   },
4150
4151   /* X86_64_1E */
4152   {
4153     { "pushP", { ds }, 0 },
4154   },
4155
4156   /* X86_64_1F */
4157   {
4158     { "popP", { ds }, 0 },
4159   },
4160
4161   /* X86_64_27 */
4162   {
4163     { "daa", { XX }, 0 },
4164   },
4165
4166   /* X86_64_2F */
4167   {
4168     { "das", { XX }, 0 },
4169   },
4170
4171   /* X86_64_37 */
4172   {
4173     { "aaa", { XX }, 0 },
4174   },
4175
4176   /* X86_64_3F */
4177   {
4178     { "aas", { XX }, 0 },
4179   },
4180
4181   /* X86_64_60 */
4182   {
4183     { "pushaP", { XX }, 0 },
4184   },
4185
4186   /* X86_64_61 */
4187   {
4188     { "popaP", { XX }, 0 },
4189   },
4190
4191   /* X86_64_62 */
4192   {
4193     { MOD_TABLE (MOD_62_32BIT) },
4194     { EVEX_TABLE (EVEX_0F) },
4195   },
4196
4197   /* X86_64_63 */
4198   {
4199     { "arpl", { Ew, Gw }, 0 },
4200     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4201   },
4202
4203   /* X86_64_6D */
4204   {
4205     { "ins{R|}", { Yzr, indirDX }, 0 },
4206     { "ins{G|}", { Yzr, indirDX }, 0 },
4207   },
4208
4209   /* X86_64_6F */
4210   {
4211     { "outs{R|}", { indirDXr, Xz }, 0 },
4212     { "outs{G|}", { indirDXr, Xz }, 0 },
4213   },
4214
4215   /* X86_64_82 */
4216   {
4217     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4218     { REG_TABLE (REG_80) },
4219   },
4220
4221   /* X86_64_9A */
4222   {
4223     { "{l|}call{P|}", { Ap }, 0 },
4224   },
4225
4226   /* X86_64_C2 */
4227   {
4228     { "retP",           { Iw, BND }, 0 },
4229     { "ret@",           { Iw, BND }, 0 },
4230   },
4231
4232   /* X86_64_C3 */
4233   {
4234     { "retP",           { BND }, 0 },
4235     { "ret@",           { BND }, 0 },
4236   },
4237
4238   /* X86_64_C4 */
4239   {
4240     { MOD_TABLE (MOD_C4_32BIT) },
4241     { VEX_C4_TABLE (VEX_0F) },
4242   },
4243
4244   /* X86_64_C5 */
4245   {
4246     { MOD_TABLE (MOD_C5_32BIT) },
4247     { VEX_C5_TABLE (VEX_0F) },
4248   },
4249
4250   /* X86_64_CE */
4251   {
4252     { "into", { XX }, 0 },
4253   },
4254
4255   /* X86_64_D4 */
4256   {
4257     { "aam", { Ib }, 0 },
4258   },
4259
4260   /* X86_64_D5 */
4261   {
4262     { "aad", { Ib }, 0 },
4263   },
4264
4265   /* X86_64_E8 */
4266   {
4267     { "callP",          { Jv, BND }, 0 },
4268     { "call@",          { Jv, BND }, 0 }
4269   },
4270
4271   /* X86_64_E9 */
4272   {
4273     { "jmpP",           { Jv, BND }, 0 },
4274     { "jmp@",           { Jv, BND }, 0 }
4275   },
4276
4277   /* X86_64_EA */
4278   {
4279     { "{l|}jmp{P|}", { Ap }, 0 },
4280   },
4281
4282   /* X86_64_0F01_REG_0 */
4283   {
4284     { "sgdt{Q|Q}", { M }, 0 },
4285     { "sgdt", { M }, 0 },
4286   },
4287
4288   /* X86_64_0F01_REG_1 */
4289   {
4290     { "sidt{Q|Q}", { M }, 0 },
4291     { "sidt", { M }, 0 },
4292   },
4293
4294   /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4295   {
4296     { Bad_Opcode },
4297     { "seamret",        { Skip_MODRM }, 0 },
4298   },
4299
4300   /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4301   {
4302     { Bad_Opcode },
4303     { "seamops",        { Skip_MODRM }, 0 },
4304   },
4305
4306   /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4307   {
4308     { Bad_Opcode },
4309     { "seamcall",       { Skip_MODRM }, 0 },
4310   },
4311
4312   /* X86_64_0F01_REG_2 */
4313   {
4314     { "lgdt{Q|Q}", { M }, 0 },
4315     { "lgdt", { M }, 0 },
4316   },
4317
4318   /* X86_64_0F01_REG_3 */
4319   {
4320     { "lidt{Q|Q}", { M }, 0 },
4321     { "lidt", { M }, 0 },
4322   },
4323
4324   {
4325     /* X86_64_0F24 */
4326     { "movZ",           { Em, Td }, 0 },
4327   },
4328
4329   {
4330     /* X86_64_0F26 */
4331     { "movZ",           { Td, Em }, 0 },
4332   },
4333
4334   /* X86_64_VEX_0F3849 */
4335   {
4336     { Bad_Opcode },
4337     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4338   },
4339
4340   /* X86_64_VEX_0F384B */
4341   {
4342     { Bad_Opcode },
4343     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4344   },
4345
4346   /* X86_64_VEX_0F385C */
4347   {
4348     { Bad_Opcode },
4349     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4350   },
4351
4352   /* X86_64_VEX_0F385E */
4353   {
4354     { Bad_Opcode },
4355     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4356   },
4357
4358   /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4359   {
4360     { Bad_Opcode },
4361     { "uiret",  { Skip_MODRM }, 0 },
4362   },
4363
4364   /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4365   {
4366     { Bad_Opcode },
4367     { "testui", { Skip_MODRM }, 0 },
4368   },
4369
4370   /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4371   {
4372     { Bad_Opcode },
4373     { "clui",   { Skip_MODRM }, 0 },
4374   },
4375
4376   /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4377   {
4378     { Bad_Opcode },
4379     { "stui",   { Skip_MODRM }, 0 },
4380   },
4381
4382   /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4383   {
4384     { Bad_Opcode },
4385     { "senduipi",       { Eq }, 0 },
4386   },
4387 };
4388
4389 static const struct dis386 three_byte_table[][256] = {
4390
4391   /* THREE_BYTE_0F38 */
4392   {
4393     /* 00 */
4394     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
4395     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
4396     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
4397     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
4398     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
4399     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
4400     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
4401     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
4402     /* 08 */
4403     { "psignb",         { MX, EM }, PREFIX_OPCODE },
4404     { "psignw",         { MX, EM }, PREFIX_OPCODE },
4405     { "psignd",         { MX, EM }, PREFIX_OPCODE },
4406     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
4407     { Bad_Opcode },
4408     { Bad_Opcode },
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     /* 10 */
4412     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4413     { Bad_Opcode },
4414     { Bad_Opcode },
4415     { Bad_Opcode },
4416     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4417     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4418     { Bad_Opcode },
4419     { "ptest",  { XM, EXx }, PREFIX_DATA },
4420     /* 18 */
4421     { Bad_Opcode },
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
4426     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
4427     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
4428     { Bad_Opcode },
4429     /* 20 */
4430     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4431     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4432     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4433     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4434     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4435     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4436     { Bad_Opcode },
4437     { Bad_Opcode },
4438     /* 28 */
4439     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4440     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4441     { MOD_TABLE (MOD_0F382A) },
4442     { "packusdw", { XM, EXx }, PREFIX_DATA },
4443     { Bad_Opcode },
4444     { Bad_Opcode },
4445     { Bad_Opcode },
4446     { Bad_Opcode },
4447     /* 30 */
4448     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4449     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4450     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4451     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4452     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4453     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4454     { Bad_Opcode },
4455     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4456     /* 38 */
4457     { "pminsb", { XM, EXx }, PREFIX_DATA },
4458     { "pminsd", { XM, EXx }, PREFIX_DATA },
4459     { "pminuw", { XM, EXx }, PREFIX_DATA },
4460     { "pminud", { XM, EXx }, PREFIX_DATA },
4461     { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4462     { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4463     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4464     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4465     /* 40 */
4466     { "pmulld", { XM, EXx }, PREFIX_DATA },
4467     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4468     { Bad_Opcode },
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { Bad_Opcode },
4474     /* 48 */
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     { Bad_Opcode },
4481     { Bad_Opcode },
4482     { Bad_Opcode },
4483     /* 50 */
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     { Bad_Opcode },
4488     { Bad_Opcode },
4489     { Bad_Opcode },
4490     { Bad_Opcode },
4491     { Bad_Opcode },
4492     /* 58 */
4493     { Bad_Opcode },
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     /* 60 */
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     { Bad_Opcode },
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     { Bad_Opcode },
4510     /* 68 */
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     /* 70 */
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     /* 78 */
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     /* 80 */
4538     { "invept", { Gm, Mo }, PREFIX_DATA },
4539     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4540     { "invpcid", { Gm, M }, PREFIX_DATA },
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { Bad_Opcode },
4545     { Bad_Opcode },
4546     /* 88 */
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     /* 90 */
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { Bad_Opcode },
4564     /* 98 */
4565     { Bad_Opcode },
4566     { Bad_Opcode },
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     { Bad_Opcode },
4573     /* a0 */
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     { Bad_Opcode },
4582     /* a8 */
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { Bad_Opcode },
4587     { Bad_Opcode },
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     /* b0 */
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     { Bad_Opcode },
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     /* b8 */
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { Bad_Opcode },
4608     { Bad_Opcode },
4609     /* c0 */
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { Bad_Opcode },
4613     { Bad_Opcode },
4614     { Bad_Opcode },
4615     { Bad_Opcode },
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     /* c8 */
4619     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4620     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4621     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4622     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4623     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4624     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4625     { Bad_Opcode },
4626     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4627     /* d0 */
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632     { Bad_Opcode },
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     /* d8 */
4637     { PREFIX_TABLE (PREFIX_0F38D8) },
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     { "aesimc", { XM, EXx }, PREFIX_DATA },
4641     { PREFIX_TABLE (PREFIX_0F38DC) },
4642     { PREFIX_TABLE (PREFIX_0F38DD) },
4643     { PREFIX_TABLE (PREFIX_0F38DE) },
4644     { PREFIX_TABLE (PREFIX_0F38DF) },
4645     /* e0 */
4646     { Bad_Opcode },
4647     { Bad_Opcode },
4648     { Bad_Opcode },
4649     { Bad_Opcode },
4650     { Bad_Opcode },
4651     { Bad_Opcode },
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     /* e8 */
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { Bad_Opcode },
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { Bad_Opcode },
4662     { Bad_Opcode },
4663     /* f0 */
4664     { PREFIX_TABLE (PREFIX_0F38F0) },
4665     { PREFIX_TABLE (PREFIX_0F38F1) },
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     { Bad_Opcode },
4669     { MOD_TABLE (MOD_0F38F5) },
4670     { PREFIX_TABLE (PREFIX_0F38F6) },
4671     { Bad_Opcode },
4672     /* f8 */
4673     { PREFIX_TABLE (PREFIX_0F38F8) },
4674     { MOD_TABLE (MOD_0F38F9) },
4675     { PREFIX_TABLE (PREFIX_0F38FA) },
4676     { PREFIX_TABLE (PREFIX_0F38FB) },
4677     { Bad_Opcode },
4678     { Bad_Opcode },
4679     { Bad_Opcode },
4680     { Bad_Opcode },
4681   },
4682   /* THREE_BYTE_0F3A */
4683   {
4684     /* 00 */
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688     { Bad_Opcode },
4689     { Bad_Opcode },
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { Bad_Opcode },
4693     /* 08 */
4694     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4695     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4696     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4697     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4698     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4699     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4700     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4701     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
4702     /* 10 */
4703     { Bad_Opcode },
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     { Bad_Opcode },
4707     { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA },
4708     { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA },
4709     { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4710     { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
4711     /* 18 */
4712     { Bad_Opcode },
4713     { Bad_Opcode },
4714     { Bad_Opcode },
4715     { Bad_Opcode },
4716     { Bad_Opcode },
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     /* 20 */
4721     { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA },
4722     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4723     { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4724     { Bad_Opcode },
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { Bad_Opcode },
4728     { Bad_Opcode },
4729     /* 28 */
4730     { Bad_Opcode },
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     { Bad_Opcode },
4734     { Bad_Opcode },
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     { Bad_Opcode },
4738     /* 30 */
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     { Bad_Opcode },
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     /* 38 */
4748     { Bad_Opcode },
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     { Bad_Opcode },
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     /* 40 */
4757     { "dpps",   { XM, EXx, Ib }, PREFIX_DATA },
4758     { "dppd",   { XM, EXx, Ib }, PREFIX_DATA },
4759     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4760     { Bad_Opcode },
4761     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     /* 48 */
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { Bad_Opcode },
4773     { Bad_Opcode },
4774     /* 50 */
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     { Bad_Opcode },
4780     { Bad_Opcode },
4781     { Bad_Opcode },
4782     { Bad_Opcode },
4783     /* 58 */
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { Bad_Opcode },
4787     { Bad_Opcode },
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { Bad_Opcode },
4792     /* 60 */
4793     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4794     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4795     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4796     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4797     { Bad_Opcode },
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { Bad_Opcode },
4801     /* 68 */
4802     { Bad_Opcode },
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { Bad_Opcode },
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     /* 70 */
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     { Bad_Opcode },
4815     { Bad_Opcode },
4816     { Bad_Opcode },
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     /* 78 */
4820     { Bad_Opcode },
4821     { Bad_Opcode },
4822     { Bad_Opcode },
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     /* 80 */
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { Bad_Opcode },
4836     { Bad_Opcode },
4837     /* 88 */
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { Bad_Opcode },
4841     { Bad_Opcode },
4842     { Bad_Opcode },
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     /* 90 */
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     { Bad_Opcode },
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { Bad_Opcode },
4855     /* 98 */
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     /* a0 */
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { Bad_Opcode },
4872     { Bad_Opcode },
4873     /* a8 */
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     /* b0 */
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     /* b8 */
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { Bad_Opcode },
4900     /* c0 */
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     /* c8 */
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4915     { Bad_Opcode },
4916     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4917     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4918     /* d0 */
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     /* d8 */
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4936     /* e0 */
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     /* e8 */
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { Bad_Opcode },
4954     /* f0 */
4955     { PREFIX_TABLE (PREFIX_0F3A0F) },
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { Bad_Opcode },
4962     { Bad_Opcode },
4963     /* f8 */
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972   },
4973 };
4974
4975 static const struct dis386 xop_table[][256] = {
4976   /* XOP_08 */
4977   {
4978     /* 00 */
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { Bad_Opcode },
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     /* 08 */
4988     { Bad_Opcode },
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     /* 10 */
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     /* 18 */
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     /* 20 */
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     /* 28 */
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     /* 30 */
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     /* 38 */
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     /* 40 */
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     /* 48 */
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     /* 50 */
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     /* 58 */
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     /* 60 */
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     /* 68 */
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     /* 70 */
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     /* 78 */
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     /* 80 */
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5129     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5130     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5131     /* 88 */
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5139     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5140     /* 90 */
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5147     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5148     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5149     /* 98 */
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { Bad_Opcode },
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5157     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5158     /* a0 */
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
5162     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5166     { Bad_Opcode },
5167     /* a8 */
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     /* b0 */
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5184     { Bad_Opcode },
5185     /* b8 */
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     /* c0 */
5195     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5196     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5197     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5198     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     /* c8 */
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5209     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5210     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5211     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5212     /* d0 */
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     /* d8 */
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     /* e0 */
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     /* e8 */
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5245     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5246     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5247     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5248     /* f0 */
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     /* f8 */
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266   },
5267   /* XOP_09 */
5268   {
5269     /* 00 */
5270     { Bad_Opcode },
5271     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5272     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     /* 08 */
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     /* 10 */
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     /* 18 */
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     /* 20 */
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     /* 28 */
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     /* 30 */
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     /* 38 */
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     /* 40 */
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     /* 48 */
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { Bad_Opcode },
5359     /* 50 */
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     /* 58 */
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     /* 60 */
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     /* 68 */
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     /* 70 */
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     /* 78 */
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     /* 80 */
5414     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5415     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5416     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5417     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     /* 88 */
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     /* 90 */
5432     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5433     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5434     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5435     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5436     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5437     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5438     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5439     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5440     /* 98 */
5441     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5442     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5443     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5444     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     /* a0 */
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     /* a8 */
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     /* b0 */
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     /* b8 */
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     /* c0 */
5486     { Bad_Opcode },
5487     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5488     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5489     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5493     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5494     /* c8 */
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     /* d0 */
5504     { Bad_Opcode },
5505     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5506     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5507     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5511     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5512     /* d8 */
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     /* e0 */
5522     { Bad_Opcode },
5523     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5524     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5525     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     /* e8 */
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     /* f0 */
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     /* f8 */
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557   },
5558   /* XOP_0A */
5559   {
5560     /* 00 */
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     /* 08 */
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     /* 10 */
5579     { "bextrS", { Gdq, Edq, Id }, 0 },
5580     { Bad_Opcode },
5581     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     /* 18 */
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     /* 20 */
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     /* 28 */
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     /* 30 */
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     /* 38 */
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     /* 40 */
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     /* 48 */
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     /* 50 */
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     /* 58 */
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     /* 60 */
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     /* 68 */
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     /* 70 */
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     /* 78 */
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     /* 80 */
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     /* 88 */
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     /* 90 */
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     /* 98 */
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     /* a0 */
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     /* a8 */
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     /* b0 */
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     /* b8 */
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     /* c0 */
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     /* c8 */
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     /* d0 */
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     /* d8 */
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     /* e0 */
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     /* e8 */
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     /* f0 */
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     /* f8 */
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848   },
5849 };
5850
5851 static const struct dis386 vex_table[][256] = {
5852   /* VEX_0F */
5853   {
5854     /* 00 */
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     /* 08 */
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     /* 10 */
5873     { PREFIX_TABLE (PREFIX_VEX_0F10) },
5874     { PREFIX_TABLE (PREFIX_VEX_0F11) },
5875     { PREFIX_TABLE (PREFIX_VEX_0F12) },
5876     { MOD_TABLE (MOD_VEX_0F13) },
5877     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5878     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5879     { PREFIX_TABLE (PREFIX_VEX_0F16) },
5880     { MOD_TABLE (MOD_VEX_0F17) },
5881     /* 18 */
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     /* 20 */
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     /* 28 */
5900     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
5901     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
5902     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5903     { MOD_TABLE (MOD_VEX_0F2B) },
5904     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5905     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5906     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5907     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5908     /* 30 */
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     /* 38 */
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     /* 40 */
5927     { Bad_Opcode },
5928     { PREFIX_TABLE (PREFIX_VEX_0F41) },
5929     { PREFIX_TABLE (PREFIX_VEX_0F42) },
5930     { Bad_Opcode },
5931     { PREFIX_TABLE (PREFIX_VEX_0F44) },
5932     { PREFIX_TABLE (PREFIX_VEX_0F45) },
5933     { PREFIX_TABLE (PREFIX_VEX_0F46) },
5934     { PREFIX_TABLE (PREFIX_VEX_0F47) },
5935     /* 48 */
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
5939     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     /* 50 */
5945     { MOD_TABLE (MOD_VEX_0F50) },
5946     { PREFIX_TABLE (PREFIX_VEX_0F51) },
5947     { PREFIX_TABLE (PREFIX_VEX_0F52) },
5948     { PREFIX_TABLE (PREFIX_VEX_0F53) },
5949     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5950     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
5951     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
5952     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5953     /* 58 */
5954     { PREFIX_TABLE (PREFIX_VEX_0F58) },
5955     { PREFIX_TABLE (PREFIX_VEX_0F59) },
5956     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5957     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5958     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5959     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5960     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5961     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5962     /* 60 */
5963     { "vpunpcklbw",     { XM, Vex, EXx }, PREFIX_DATA },
5964     { "vpunpcklwd",     { XM, Vex, EXx }, PREFIX_DATA },
5965     { "vpunpckldq",     { XM, Vex, EXx }, PREFIX_DATA },
5966     { "vpacksswb",      { XM, Vex, EXx }, PREFIX_DATA },
5967     { "vpcmpgtb",       { XM, Vex, EXx }, PREFIX_DATA },
5968     { "vpcmpgtw",       { XM, Vex, EXx }, PREFIX_DATA },
5969     { "vpcmpgtd",       { XM, Vex, EXx }, PREFIX_DATA },
5970     { "vpackuswb",      { XM, Vex, EXx }, PREFIX_DATA },
5971     /* 68 */
5972     { "vpunpckhbw",     { XM, Vex, EXx }, PREFIX_DATA },
5973     { "vpunpckhwd",     { XM, Vex, EXx }, PREFIX_DATA },
5974     { "vpunpckhdq",     { XM, Vex, EXx }, PREFIX_DATA },
5975     { "vpackssdw",      { XM, Vex, EXx }, PREFIX_DATA },
5976     { "vpunpcklqdq",    { XM, Vex, EXx }, PREFIX_DATA },
5977     { "vpunpckhqdq",    { XM, Vex, EXx }, PREFIX_DATA },
5978     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
5979     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
5980     /* 70 */
5981     { PREFIX_TABLE (PREFIX_VEX_0F70) },
5982     { REG_TABLE (REG_VEX_0F71) },
5983     { REG_TABLE (REG_VEX_0F72) },
5984     { REG_TABLE (REG_VEX_0F73) },
5985     { "vpcmpeqb",       { XM, Vex, EXx }, PREFIX_DATA },
5986     { "vpcmpeqw",       { XM, Vex, EXx }, PREFIX_DATA },
5987     { "vpcmpeqd",       { XM, Vex, EXx }, PREFIX_DATA },
5988     { VEX_LEN_TABLE (VEX_LEN_0F77) },
5989     /* 78 */
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
5995     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
5996     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
5997     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
5998     /* 80 */
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     /* 88 */
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     /* 90 */
6017     { PREFIX_TABLE (PREFIX_VEX_0F90) },
6018     { PREFIX_TABLE (PREFIX_VEX_0F91) },
6019     { PREFIX_TABLE (PREFIX_VEX_0F92) },
6020     { PREFIX_TABLE (PREFIX_VEX_0F93) },
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     /* 98 */
6026     { PREFIX_TABLE (PREFIX_VEX_0F98) },
6027     { PREFIX_TABLE (PREFIX_VEX_0F99) },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     /* a0 */
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     /* a8 */
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { REG_TABLE (REG_VEX_0FAE) },
6051     { Bad_Opcode },
6052     /* b0 */
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     /* b8 */
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     /* c0 */
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6074     { Bad_Opcode },
6075     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6076     { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6077     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6078     { Bad_Opcode },
6079     /* c8 */
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     /* d0 */
6089     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6090     { "vpsrlw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6091     { "vpsrld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6092     { "vpsrlq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6093     { "vpaddq",         { XM, Vex, EXx }, PREFIX_DATA },
6094     { "vpmullw",        { XM, Vex, EXx }, PREFIX_DATA },
6095     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6096     { MOD_TABLE (MOD_VEX_0FD7) },
6097     /* d8 */
6098     { "vpsubusb",       { XM, Vex, EXx }, PREFIX_DATA },
6099     { "vpsubusw",       { XM, Vex, EXx }, PREFIX_DATA },
6100     { "vpminub",        { XM, Vex, EXx }, PREFIX_DATA },
6101     { "vpand",          { XM, Vex, EXx }, PREFIX_DATA },
6102     { "vpaddusb",       { XM, Vex, EXx }, PREFIX_DATA },
6103     { "vpaddusw",       { XM, Vex, EXx }, PREFIX_DATA },
6104     { "vpmaxub",        { XM, Vex, EXx }, PREFIX_DATA },
6105     { "vpandn",         { XM, Vex, EXx }, PREFIX_DATA },
6106     /* e0 */
6107     { "vpavgb",         { XM, Vex, EXx }, PREFIX_DATA },
6108     { "vpsraw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6109     { "vpsrad",         { XM, Vex, EXxmm }, PREFIX_DATA },
6110     { "vpavgw",         { XM, Vex, EXx }, PREFIX_DATA },
6111     { "vpmulhuw",       { XM, Vex, EXx }, PREFIX_DATA },
6112     { "vpmulhw",        { XM, Vex, EXx }, PREFIX_DATA },
6113     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6114     { MOD_TABLE (MOD_VEX_0FE7) },
6115     /* e8 */
6116     { "vpsubsb",        { XM, Vex, EXx }, PREFIX_DATA },
6117     { "vpsubsw",        { XM, Vex, EXx }, PREFIX_DATA },
6118     { "vpminsw",        { XM, Vex, EXx }, PREFIX_DATA },
6119     { "vpor",           { XM, Vex, EXx }, PREFIX_DATA },
6120     { "vpaddsb",        { XM, Vex, EXx }, PREFIX_DATA },
6121     { "vpaddsw",        { XM, Vex, EXx }, PREFIX_DATA },
6122     { "vpmaxsw",        { XM, Vex, EXx }, PREFIX_DATA },
6123     { "vpxor",          { XM, Vex, EXx }, PREFIX_DATA },
6124     /* f0 */
6125     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6126     { "vpsllw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6127     { "vpslld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6128     { "vpsllq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6129     { "vpmuludq",       { XM, Vex, EXx }, PREFIX_DATA },
6130     { "vpmaddwd",       { XM, Vex, EXx }, PREFIX_DATA },
6131     { "vpsadbw",        { XM, Vex, EXx }, PREFIX_DATA },
6132     { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6133     /* f8 */
6134     { "vpsubb",         { XM, Vex, EXx }, PREFIX_DATA },
6135     { "vpsubw",         { XM, Vex, EXx }, PREFIX_DATA },
6136     { "vpsubd",         { XM, Vex, EXx }, PREFIX_DATA },
6137     { "vpsubq",         { XM, Vex, EXx }, PREFIX_DATA },
6138     { "vpaddb",         { XM, Vex, EXx }, PREFIX_DATA },
6139     { "vpaddw",         { XM, Vex, EXx }, PREFIX_DATA },
6140     { "vpaddd",         { XM, Vex, EXx }, PREFIX_DATA },
6141     { Bad_Opcode },
6142   },
6143   /* VEX_0F38 */
6144   {
6145     /* 00 */
6146     { "vpshufb",        { XM, Vex, EXx }, PREFIX_DATA },
6147     { "vphaddw",        { XM, Vex, EXx }, PREFIX_DATA },
6148     { "vphaddd",        { XM, Vex, EXx }, PREFIX_DATA },
6149     { "vphaddsw",       { XM, Vex, EXx }, PREFIX_DATA },
6150     { "vpmaddubsw",     { XM, Vex, EXx }, PREFIX_DATA },
6151     { "vphsubw",        { XM, Vex, EXx }, PREFIX_DATA },
6152     { "vphsubd",        { XM, Vex, EXx }, PREFIX_DATA },
6153     { "vphsubsw",       { XM, Vex, EXx }, PREFIX_DATA },
6154     /* 08 */
6155     { "vpsignb",        { XM, Vex, EXx }, PREFIX_DATA },
6156     { "vpsignw",        { XM, Vex, EXx }, PREFIX_DATA },
6157     { "vpsignd",        { XM, Vex, EXx }, PREFIX_DATA },
6158     { "vpmulhrsw",      { XM, Vex, EXx }, PREFIX_DATA },
6159     { VEX_W_TABLE (VEX_W_0F380C) },
6160     { VEX_W_TABLE (VEX_W_0F380D) },
6161     { VEX_W_TABLE (VEX_W_0F380E) },
6162     { VEX_W_TABLE (VEX_W_0F380F) },
6163     /* 10 */
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { VEX_W_TABLE (VEX_W_0F3813) },
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6171     { "vptest",         { XM, EXx }, PREFIX_DATA },
6172     /* 18 */
6173     { VEX_W_TABLE (VEX_W_0F3818) },
6174     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6175     { MOD_TABLE (MOD_VEX_0F381A) },
6176     { Bad_Opcode },
6177     { "vpabsb",         { XM, EXx }, PREFIX_DATA },
6178     { "vpabsw",         { XM, EXx }, PREFIX_DATA },
6179     { "vpabsd",         { XM, EXx }, PREFIX_DATA },
6180     { Bad_Opcode },
6181     /* 20 */
6182     { "vpmovsxbw",      { XM, EXxmmq }, PREFIX_DATA },
6183     { "vpmovsxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6184     { "vpmovsxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6185     { "vpmovsxwd",      { XM, EXxmmq }, PREFIX_DATA },
6186     { "vpmovsxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6187     { "vpmovsxdq",      { XM, EXxmmq }, PREFIX_DATA },
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     /* 28 */
6191     { "vpmuldq",        { XM, Vex, EXx }, PREFIX_DATA },
6192     { "vpcmpeqq",       { XM, Vex, EXx }, PREFIX_DATA },
6193     { MOD_TABLE (MOD_VEX_0F382A) },
6194     { "vpackusdw",      { XM, Vex, EXx }, PREFIX_DATA },
6195     { MOD_TABLE (MOD_VEX_0F382C) },
6196     { MOD_TABLE (MOD_VEX_0F382D) },
6197     { MOD_TABLE (MOD_VEX_0F382E) },
6198     { MOD_TABLE (MOD_VEX_0F382F) },
6199     /* 30 */
6200     { "vpmovzxbw",      { XM, EXxmmq }, PREFIX_DATA },
6201     { "vpmovzxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6202     { "vpmovzxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6203     { "vpmovzxwd",      { XM, EXxmmq }, PREFIX_DATA },
6204     { "vpmovzxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6205     { "vpmovzxdq",      { XM, EXxmmq }, PREFIX_DATA },
6206     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6207     { "vpcmpgtq",       { XM, Vex, EXx }, PREFIX_DATA },
6208     /* 38 */
6209     { "vpminsb",        { XM, Vex, EXx }, PREFIX_DATA },
6210     { "vpminsd",        { XM, Vex, EXx }, PREFIX_DATA },
6211     { "vpminuw",        { XM, Vex, EXx }, PREFIX_DATA },
6212     { "vpminud",        { XM, Vex, EXx }, PREFIX_DATA },
6213     { "vpmaxsb",        { XM, Vex, EXx }, PREFIX_DATA },
6214     { "vpmaxsd",        { XM, Vex, EXx }, PREFIX_DATA },
6215     { "vpmaxuw",        { XM, Vex, EXx }, PREFIX_DATA },
6216     { "vpmaxud",        { XM, Vex, EXx }, PREFIX_DATA },
6217     /* 40 */
6218     { "vpmulld",        { XM, Vex, EXx }, PREFIX_DATA },
6219     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6224     { VEX_W_TABLE (VEX_W_0F3846) },
6225     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6226     /* 48 */
6227     { Bad_Opcode },
6228     { X86_64_TABLE (X86_64_VEX_0F3849) },
6229     { Bad_Opcode },
6230     { X86_64_TABLE (X86_64_VEX_0F384B) },
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     /* 50 */
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     /* 58 */
6245     { VEX_W_TABLE (VEX_W_0F3858) },
6246     { VEX_W_TABLE (VEX_W_0F3859) },
6247     { MOD_TABLE (MOD_VEX_0F385A) },
6248     { Bad_Opcode },
6249     { X86_64_TABLE (X86_64_VEX_0F385C) },
6250     { Bad_Opcode },
6251     { X86_64_TABLE (X86_64_VEX_0F385E) },
6252     { Bad_Opcode },
6253     /* 60 */
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     /* 68 */
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     /* 70 */
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     /* 78 */
6281     { VEX_W_TABLE (VEX_W_0F3878) },
6282     { VEX_W_TABLE (VEX_W_0F3879) },
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     /* 80 */
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     /* 88 */
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { MOD_TABLE (MOD_VEX_0F388C) },
6304     { Bad_Opcode },
6305     { MOD_TABLE (MOD_VEX_0F388E) },
6306     { Bad_Opcode },
6307     /* 90 */
6308     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6309     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6310     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6311     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6315     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6316     /* 98 */
6317     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6318     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6319     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6320     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6321     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6322     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6323     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6324     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6325     /* a0 */
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6333     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6334     /* a8 */
6335     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6336     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6337     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6338     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6339     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6340     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6341     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6342     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6343     /* b0 */
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6351     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6352     /* b8 */
6353     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6354     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6355     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6356     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6357     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6358     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6359     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6360     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6361     /* c0 */
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     /* c8 */
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { VEX_W_TABLE (VEX_W_0F38CF) },
6379     /* d0 */
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     /* d8 */
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6393     { "vaesenc",        { XM, Vex, EXx }, PREFIX_DATA },
6394     { "vaesenclast",    { XM, Vex, EXx }, PREFIX_DATA },
6395     { "vaesdec",        { XM, Vex, EXx }, PREFIX_DATA },
6396     { "vaesdeclast",    { XM, Vex, EXx }, PREFIX_DATA },
6397     /* e0 */
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     /* e8 */
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     /* f0 */
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6419     { REG_TABLE (REG_VEX_0F38F3) },
6420     { Bad_Opcode },
6421     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
6422     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
6423     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
6424     /* f8 */
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433   },
6434   /* VEX_0F3A */
6435   {
6436     /* 00 */
6437     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6438     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6439     { VEX_W_TABLE (VEX_W_0F3A02) },
6440     { Bad_Opcode },
6441     { VEX_W_TABLE (VEX_W_0F3A04) },
6442     { VEX_W_TABLE (VEX_W_0F3A05) },
6443     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6444     { Bad_Opcode },
6445     /* 08 */
6446     { "vroundps",       { XM, EXx, Ib }, PREFIX_DATA },
6447     { "vroundpd",       { XM, EXx, Ib }, PREFIX_DATA },
6448     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
6449     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
6450     { "vblendps",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6451     { "vblendpd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6452     { "vpblendw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6453     { "vpalignr",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6454     /* 10 */
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6460     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6461     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6462     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6463     /* 18 */
6464     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6465     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { VEX_W_TABLE (VEX_W_0F3A1D) },
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     /* 20 */
6473     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6474     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6475     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     /* 28 */
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     /* 30 */
6491     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6492     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6493     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6494     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     /* 38 */
6500     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6501     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     /* 40 */
6509     { "vdpps",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
6510     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6511     { "vmpsadbw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6512     { Bad_Opcode },
6513     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6514     { Bad_Opcode },
6515     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6516     { Bad_Opcode },
6517     /* 48 */
6518     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6519     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6520     { VEX_W_TABLE (VEX_W_0F3A4A) },
6521     { VEX_W_TABLE (VEX_W_0F3A4B) },
6522     { VEX_W_TABLE (VEX_W_0F3A4C) },
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     /* 50 */
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     /* 58 */
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6541     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6542     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6543     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6544     /* 60 */
6545     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6546     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6547     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6548     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     /* 68 */
6554     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6555     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6556     { "vfmaddss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6557     { "vfmaddsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6558     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6559     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6560     { "vfmsubss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6561     { "vfmsubsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6562     /* 70 */
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     /* 78 */
6572     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6573     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6574     { "vfnmaddss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6575     { "vfnmaddsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6576     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6577     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6578     { "vfnmsubss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6579     { "vfnmsubsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6580     /* 80 */
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     /* 88 */
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     /* 90 */
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     /* 98 */
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     /* a0 */
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     /* a8 */
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     /* b0 */
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     /* b8 */
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     /* c0 */
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     /* c8 */
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { VEX_W_TABLE (VEX_W_0F3ACE) },
6669     { VEX_W_TABLE (VEX_W_0F3ACF) },
6670     /* d0 */
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     /* d8 */
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6688     /* e0 */
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     /* e8 */
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     /* f0 */
6707     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     /* f8 */
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724   },
6725 };
6726
6727 #include "i386-dis-evex.h"
6728
6729 static const struct dis386 vex_len_table[][2] = {
6730   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6731   {
6732     { "vmovlpX",        { XM, Vex, EXq }, 0 },
6733   },
6734
6735   /* VEX_LEN_0F12_P_0_M_1 */
6736   {
6737     { "vmovhlps",       { XM, Vex, EXq }, 0 },
6738   },
6739
6740   /* VEX_LEN_0F13_M_0 */
6741   {
6742     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
6743   },
6744
6745   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6746   {
6747     { "vmovhpX",        { XM, Vex, EXq }, 0 },
6748   },
6749
6750   /* VEX_LEN_0F16_P_0_M_1 */
6751   {
6752     { "vmovlhps",       { XM, Vex, EXq }, 0 },
6753   },
6754
6755   /* VEX_LEN_0F17_M_0 */
6756   {
6757     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
6758   },
6759
6760   /* VEX_LEN_0F41_P_0 */
6761   {
6762     { Bad_Opcode },
6763     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
6764   },
6765   /* VEX_LEN_0F41_P_2 */
6766   {
6767     { Bad_Opcode },
6768     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
6769   },
6770   /* VEX_LEN_0F42_P_0 */
6771   {
6772     { Bad_Opcode },
6773     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
6774   },
6775   /* VEX_LEN_0F42_P_2 */
6776   {
6777     { Bad_Opcode },
6778     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
6779   },
6780   /* VEX_LEN_0F44_P_0 */
6781   {
6782     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
6783   },
6784   /* VEX_LEN_0F44_P_2 */
6785   {
6786     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
6787   },
6788   /* VEX_LEN_0F45_P_0 */
6789   {
6790     { Bad_Opcode },
6791     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
6792   },
6793   /* VEX_LEN_0F45_P_2 */
6794   {
6795     { Bad_Opcode },
6796     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
6797   },
6798   /* VEX_LEN_0F46_P_0 */
6799   {
6800     { Bad_Opcode },
6801     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
6802   },
6803   /* VEX_LEN_0F46_P_2 */
6804   {
6805     { Bad_Opcode },
6806     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
6807   },
6808   /* VEX_LEN_0F47_P_0 */
6809   {
6810     { Bad_Opcode },
6811     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
6812   },
6813   /* VEX_LEN_0F47_P_2 */
6814   {
6815     { Bad_Opcode },
6816     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
6817   },
6818   /* VEX_LEN_0F4A_P_0 */
6819   {
6820     { Bad_Opcode },
6821     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
6822   },
6823   /* VEX_LEN_0F4A_P_2 */
6824   {
6825     { Bad_Opcode },
6826     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
6827   },
6828   /* VEX_LEN_0F4B_P_0 */
6829   {
6830     { Bad_Opcode },
6831     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
6832   },
6833   /* VEX_LEN_0F4B_P_2 */
6834   {
6835     { Bad_Opcode },
6836     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
6837   },
6838
6839   /* VEX_LEN_0F6E */
6840   {
6841     { "vmovK",          { XMScalar, Edq }, PREFIX_DATA },
6842   },
6843
6844   /* VEX_LEN_0F77 */
6845   {
6846     { "vzeroupper",     { XX }, 0 },
6847     { "vzeroall",       { XX }, 0 },
6848   },
6849
6850   /* VEX_LEN_0F7E_P_1 */
6851   {
6852     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
6853   },
6854
6855   /* VEX_LEN_0F7E_P_2 */
6856   {
6857     { "vmovK",          { Edq, XMScalar }, 0 },
6858   },
6859
6860   /* VEX_LEN_0F90_P_0 */
6861   {
6862     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
6863   },
6864
6865   /* VEX_LEN_0F90_P_2 */
6866   {
6867     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
6868   },
6869
6870   /* VEX_LEN_0F91_P_0 */
6871   {
6872     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
6873   },
6874
6875   /* VEX_LEN_0F91_P_2 */
6876   {
6877     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
6878   },
6879
6880   /* VEX_LEN_0F92_P_0 */
6881   {
6882     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
6883   },
6884
6885   /* VEX_LEN_0F92_P_2 */
6886   {
6887     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
6888   },
6889
6890   /* VEX_LEN_0F92_P_3 */
6891   {
6892     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
6893   },
6894
6895   /* VEX_LEN_0F93_P_0 */
6896   {
6897     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
6898   },
6899
6900   /* VEX_LEN_0F93_P_2 */
6901   {
6902     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
6903   },
6904
6905   /* VEX_LEN_0F93_P_3 */
6906   {
6907     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
6908   },
6909
6910   /* VEX_LEN_0F98_P_0 */
6911   {
6912     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
6913   },
6914
6915   /* VEX_LEN_0F98_P_2 */
6916   {
6917     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
6918   },
6919
6920   /* VEX_LEN_0F99_P_0 */
6921   {
6922     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
6923   },
6924
6925   /* VEX_LEN_0F99_P_2 */
6926   {
6927     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
6928   },
6929
6930   /* VEX_LEN_0FAE_R_2_M_0 */
6931   {
6932     { "vldmxcsr",       { Md }, 0 },
6933   },
6934
6935   /* VEX_LEN_0FAE_R_3_M_0 */
6936   {
6937     { "vstmxcsr",       { Md }, 0 },
6938   },
6939
6940   /* VEX_LEN_0FC4 */
6941   {
6942     { "vpinsrw",        { XM, Vex, Edqw, Ib }, PREFIX_DATA },
6943   },
6944
6945   /* VEX_LEN_0FC5 */
6946   {
6947     { "vpextrw",        { Gdq, XS, Ib }, PREFIX_DATA },
6948   },
6949
6950   /* VEX_LEN_0FD6 */
6951   {
6952     { "vmovq",          { EXqS, XMScalar }, PREFIX_DATA },
6953   },
6954
6955   /* VEX_LEN_0FF7 */
6956   {
6957     { "vmaskmovdqu",    { XM, XS }, PREFIX_DATA },
6958   },
6959
6960   /* VEX_LEN_0F3816 */
6961   {
6962     { Bad_Opcode },
6963     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6964   },
6965
6966   /* VEX_LEN_0F3819 */
6967   {
6968     { Bad_Opcode },
6969     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6970   },
6971
6972   /* VEX_LEN_0F381A_M_0 */
6973   {
6974     { Bad_Opcode },
6975     { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6976   },
6977
6978   /* VEX_LEN_0F3836 */
6979   {
6980     { Bad_Opcode },
6981     { VEX_W_TABLE (VEX_W_0F3836) },
6982   },
6983
6984   /* VEX_LEN_0F3841 */
6985   {
6986     { "vphminposuw",    { XM, EXx }, PREFIX_DATA },
6987   },
6988
6989    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6990   {
6991     { "ldtilecfg", { M }, 0 },
6992   },
6993
6994   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6995   {
6996     { "tilerelease", { Skip_MODRM }, 0 },
6997   },
6998
6999   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
7000   {
7001     { "sttilecfg", { M }, 0 },
7002   },
7003
7004   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
7005   {
7006     { "tilezero", { TMM, Skip_MODRM }, 0 },
7007   },
7008
7009   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
7010   {
7011     { "tilestored", { MVexSIBMEM, TMM }, 0 },
7012   },
7013   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
7014   {
7015     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
7016   },
7017
7018   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
7019   {
7020     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
7021   },
7022
7023   /* VEX_LEN_0F385A_M_0 */
7024   {
7025     { Bad_Opcode },
7026     { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
7027   },
7028
7029   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
7030   {
7031     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
7032   },
7033
7034   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
7035   {
7036     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
7037   },
7038
7039   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
7040   {
7041     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
7042   },
7043
7044   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
7045   {
7046     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
7047   },
7048
7049   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
7050   {
7051     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
7052   },
7053
7054   /* VEX_LEN_0F38DB */
7055   {
7056     { "vaesimc",        { XM, EXx }, PREFIX_DATA },
7057   },
7058
7059   /* VEX_LEN_0F38F2 */
7060   {
7061     { "andnS",          { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
7062   },
7063
7064   /* VEX_LEN_0F38F3_R_1 */
7065   {
7066     { "blsrS",          { VexGdq, Edq }, PREFIX_OPCODE },
7067   },
7068
7069   /* VEX_LEN_0F38F3_R_2 */
7070   {
7071     { "blsmskS",        { VexGdq, Edq }, PREFIX_OPCODE },
7072   },
7073
7074   /* VEX_LEN_0F38F3_R_3 */
7075   {
7076     { "blsiS",          { VexGdq, Edq }, PREFIX_OPCODE },
7077   },
7078
7079   /* VEX_LEN_0F38F5_P_0 */
7080   {
7081     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
7082   },
7083
7084   /* VEX_LEN_0F38F5_P_1 */
7085   {
7086     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
7087   },
7088
7089   /* VEX_LEN_0F38F5_P_3 */
7090   {
7091     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
7092   },
7093
7094   /* VEX_LEN_0F38F6_P_3 */
7095   {
7096     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
7097   },
7098
7099   /* VEX_LEN_0F38F7_P_0 */
7100   {
7101     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
7102   },
7103
7104   /* VEX_LEN_0F38F7_P_1 */
7105   {
7106     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
7107   },
7108
7109   /* VEX_LEN_0F38F7_P_2 */
7110   {
7111     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
7112   },
7113
7114   /* VEX_LEN_0F38F7_P_3 */
7115   {
7116     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
7117   },
7118
7119   /* VEX_LEN_0F3A00 */
7120   {
7121     { Bad_Opcode },
7122     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7123   },
7124
7125   /* VEX_LEN_0F3A01 */
7126   {
7127     { Bad_Opcode },
7128     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7129   },
7130
7131   /* VEX_LEN_0F3A06 */
7132   {
7133     { Bad_Opcode },
7134     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7135   },
7136
7137   /* VEX_LEN_0F3A14 */
7138   {
7139     { "vpextrb",        { Edqb, XM, Ib }, PREFIX_DATA },
7140   },
7141
7142   /* VEX_LEN_0F3A15 */
7143   {
7144     { "vpextrw",        { Edqw, XM, Ib }, PREFIX_DATA },
7145   },
7146
7147   /* VEX_LEN_0F3A16  */
7148   {
7149     { "vpextrK",        { Edq, XM, Ib }, PREFIX_DATA },
7150   },
7151
7152   /* VEX_LEN_0F3A17 */
7153   {
7154     { "vextractps",     { Edqd, XM, Ib }, PREFIX_DATA },
7155   },
7156
7157   /* VEX_LEN_0F3A18 */
7158   {
7159     { Bad_Opcode },
7160     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7161   },
7162
7163   /* VEX_LEN_0F3A19 */
7164   {
7165     { Bad_Opcode },
7166     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7167   },
7168
7169   /* VEX_LEN_0F3A20 */
7170   {
7171     { "vpinsrb",        { XM, Vex, Edqb, Ib }, PREFIX_DATA },
7172   },
7173
7174   /* VEX_LEN_0F3A21 */
7175   {
7176     { "vinsertps",      { XM, Vex, EXd, Ib }, PREFIX_DATA },
7177   },
7178
7179   /* VEX_LEN_0F3A22 */
7180   {
7181     { "vpinsrK",        { XM, Vex, Edq, Ib }, PREFIX_DATA },
7182   },
7183
7184   /* VEX_LEN_0F3A30 */
7185   {
7186     { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7187   },
7188
7189   /* VEX_LEN_0F3A31 */
7190   {
7191     { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7192   },
7193
7194   /* VEX_LEN_0F3A32 */
7195   {
7196     { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7197   },
7198
7199   /* VEX_LEN_0F3A33 */
7200   {
7201     { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7202   },
7203
7204   /* VEX_LEN_0F3A38 */
7205   {
7206     { Bad_Opcode },
7207     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7208   },
7209
7210   /* VEX_LEN_0F3A39 */
7211   {
7212     { Bad_Opcode },
7213     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7214   },
7215
7216   /* VEX_LEN_0F3A41 */
7217   {
7218     { "vdppd",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
7219   },
7220
7221   /* VEX_LEN_0F3A46 */
7222   {
7223     { Bad_Opcode },
7224     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7225   },
7226
7227   /* VEX_LEN_0F3A60 */
7228   {
7229     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7230   },
7231
7232   /* VEX_LEN_0F3A61 */
7233   {
7234     { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7235   },
7236
7237   /* VEX_LEN_0F3A62 */
7238   {
7239     { "vpcmpistrm",     { XM, EXx, Ib }, PREFIX_DATA },
7240   },
7241
7242   /* VEX_LEN_0F3A63 */
7243   {
7244     { "vpcmpistri",     { XM, EXx, Ib }, PREFIX_DATA },
7245   },
7246
7247   /* VEX_LEN_0F3ADF */
7248   {
7249     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7250   },
7251
7252   /* VEX_LEN_0F3AF0_P_3 */
7253   {
7254     { "rorxS",          { Gdq, Edq, Ib }, 0 },
7255   },
7256
7257   /* VEX_LEN_0FXOP_08_85 */
7258   {
7259     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7260   },
7261
7262   /* VEX_LEN_0FXOP_08_86 */
7263   {
7264     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7265   },
7266
7267   /* VEX_LEN_0FXOP_08_87 */
7268   {
7269     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7270   },
7271
7272   /* VEX_LEN_0FXOP_08_8E */
7273   {
7274     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7275   },
7276
7277   /* VEX_LEN_0FXOP_08_8F */
7278   {
7279     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7280   },
7281
7282   /* VEX_LEN_0FXOP_08_95 */
7283   {
7284     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7285   },
7286
7287   /* VEX_LEN_0FXOP_08_96 */
7288   {
7289     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7290   },
7291
7292   /* VEX_LEN_0FXOP_08_97 */
7293   {
7294     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7295   },
7296
7297   /* VEX_LEN_0FXOP_08_9E */
7298   {
7299     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7300   },
7301
7302   /* VEX_LEN_0FXOP_08_9F */
7303   {
7304     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7305   },
7306
7307   /* VEX_LEN_0FXOP_08_A3 */
7308   {
7309     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7310   },
7311
7312   /* VEX_LEN_0FXOP_08_A6 */
7313   {
7314     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7315   },
7316
7317   /* VEX_LEN_0FXOP_08_B6 */
7318   {
7319     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7320   },
7321
7322   /* VEX_LEN_0FXOP_08_C0 */
7323   {
7324     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7325   },
7326
7327   /* VEX_LEN_0FXOP_08_C1 */
7328   {
7329     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7330   },
7331
7332   /* VEX_LEN_0FXOP_08_C2 */
7333   {
7334     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7335   },
7336
7337   /* VEX_LEN_0FXOP_08_C3 */
7338   {
7339     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7340   },
7341
7342   /* VEX_LEN_0FXOP_08_CC */
7343   {
7344     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7345   },
7346
7347   /* VEX_LEN_0FXOP_08_CD */
7348   {
7349     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7350   },
7351
7352   /* VEX_LEN_0FXOP_08_CE */
7353   {
7354     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7355   },
7356
7357   /* VEX_LEN_0FXOP_08_CF */
7358   {
7359     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7360   },
7361
7362   /* VEX_LEN_0FXOP_08_EC */
7363   {
7364     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7365   },
7366
7367   /* VEX_LEN_0FXOP_08_ED */
7368   {
7369     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7370   },
7371
7372   /* VEX_LEN_0FXOP_08_EE */
7373   {
7374     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7375   },
7376
7377   /* VEX_LEN_0FXOP_08_EF */
7378   {
7379     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7380   },
7381
7382   /* VEX_LEN_0FXOP_09_01 */
7383   {
7384     { REG_TABLE (REG_0FXOP_09_01_L_0) },
7385   },
7386
7387   /* VEX_LEN_0FXOP_09_02 */
7388   {
7389     { REG_TABLE (REG_0FXOP_09_02_L_0) },
7390   },
7391
7392   /* VEX_LEN_0FXOP_09_12_M_1 */
7393   {
7394     { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
7395   },
7396
7397   /* VEX_LEN_0FXOP_09_82_W_0 */
7398   {
7399     { "vfrczss",        { XM, EXd }, 0 },
7400   },
7401
7402   /* VEX_LEN_0FXOP_09_83_W_0 */
7403   {
7404     { "vfrczsd",        { XM, EXq }, 0 },
7405   },
7406
7407   /* VEX_LEN_0FXOP_09_90 */
7408   {
7409     { "vprotb",         { XM, EXx, VexW }, 0 },
7410   },
7411
7412   /* VEX_LEN_0FXOP_09_91 */
7413   {
7414     { "vprotw",         { XM, EXx, VexW }, 0 },
7415   },
7416
7417   /* VEX_LEN_0FXOP_09_92 */
7418   {
7419     { "vprotd",         { XM, EXx, VexW }, 0 },
7420   },
7421
7422   /* VEX_LEN_0FXOP_09_93 */
7423   {
7424     { "vprotq",         { XM, EXx, VexW }, 0 },
7425   },
7426
7427   /* VEX_LEN_0FXOP_09_94 */
7428   {
7429     { "vpshlb",         { XM, EXx, VexW }, 0 },
7430   },
7431
7432   /* VEX_LEN_0FXOP_09_95 */
7433   {
7434     { "vpshlw",         { XM, EXx, VexW }, 0 },
7435   },
7436
7437   /* VEX_LEN_0FXOP_09_96 */
7438   {
7439     { "vpshld",         { XM, EXx, VexW }, 0 },
7440   },
7441
7442   /* VEX_LEN_0FXOP_09_97 */
7443   {
7444     { "vpshlq",         { XM, EXx, VexW }, 0 },
7445   },
7446
7447   /* VEX_LEN_0FXOP_09_98 */
7448   {
7449     { "vpshab",         { XM, EXx, VexW }, 0 },
7450   },
7451
7452   /* VEX_LEN_0FXOP_09_99 */
7453   {
7454     { "vpshaw",         { XM, EXx, VexW }, 0 },
7455   },
7456
7457   /* VEX_LEN_0FXOP_09_9A */
7458   {
7459     { "vpshad",         { XM, EXx, VexW }, 0 },
7460   },
7461
7462   /* VEX_LEN_0FXOP_09_9B */
7463   {
7464     { "vpshaq",         { XM, EXx, VexW }, 0 },
7465   },
7466
7467   /* VEX_LEN_0FXOP_09_C1 */
7468   {
7469     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7470   },
7471
7472   /* VEX_LEN_0FXOP_09_C2 */
7473   {
7474     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7475   },
7476
7477   /* VEX_LEN_0FXOP_09_C3 */
7478   {
7479     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7480   },
7481
7482   /* VEX_LEN_0FXOP_09_C6 */
7483   {
7484     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7485   },
7486
7487   /* VEX_LEN_0FXOP_09_C7 */
7488   {
7489     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7490   },
7491
7492   /* VEX_LEN_0FXOP_09_CB */
7493   {
7494     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7495   },
7496
7497   /* VEX_LEN_0FXOP_09_D1 */
7498   {
7499     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7500   },
7501
7502   /* VEX_LEN_0FXOP_09_D2 */
7503   {
7504     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7505   },
7506
7507   /* VEX_LEN_0FXOP_09_D3 */
7508   {
7509     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7510   },
7511
7512   /* VEX_LEN_0FXOP_09_D6 */
7513   {
7514     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7515   },
7516
7517   /* VEX_LEN_0FXOP_09_D7 */
7518   {
7519     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7520   },
7521
7522   /* VEX_LEN_0FXOP_09_DB */
7523   {
7524     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7525   },
7526
7527   /* VEX_LEN_0FXOP_09_E1 */
7528   {
7529     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7530   },
7531
7532   /* VEX_LEN_0FXOP_09_E2 */
7533   {
7534     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7535   },
7536
7537   /* VEX_LEN_0FXOP_09_E3 */
7538   {
7539     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7540   },
7541
7542   /* VEX_LEN_0FXOP_0A_12 */
7543   {
7544     { REG_TABLE (REG_0FXOP_0A_12_L_0) },
7545   },
7546 };
7547
7548 #include "i386-dis-evex-len.h"
7549
7550 static const struct dis386 vex_w_table[][2] = {
7551   {
7552     /* VEX_W_0F41_P_0_LEN_1 */
7553     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
7554     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
7555   },
7556   {
7557     /* VEX_W_0F41_P_2_LEN_1 */
7558     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
7559     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
7560   },
7561   {
7562     /* VEX_W_0F42_P_0_LEN_1 */
7563     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
7564     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
7565   },
7566   {
7567     /* VEX_W_0F42_P_2_LEN_1 */
7568     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
7569     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
7570   },
7571   {
7572     /* VEX_W_0F44_P_0_LEN_0 */
7573     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
7574     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
7575   },
7576   {
7577     /* VEX_W_0F44_P_2_LEN_0 */
7578     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
7579     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
7580   },
7581   {
7582     /* VEX_W_0F45_P_0_LEN_1 */
7583     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
7584     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
7585   },
7586   {
7587     /* VEX_W_0F45_P_2_LEN_1 */
7588     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
7589     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
7590   },
7591   {
7592     /* VEX_W_0F46_P_0_LEN_1 */
7593     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
7594     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
7595   },
7596   {
7597     /* VEX_W_0F46_P_2_LEN_1 */
7598     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
7599     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
7600   },
7601   {
7602     /* VEX_W_0F47_P_0_LEN_1 */
7603     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
7604     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
7605   },
7606   {
7607     /* VEX_W_0F47_P_2_LEN_1 */
7608     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
7609     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
7610   },
7611   {
7612     /* VEX_W_0F4A_P_0_LEN_1 */
7613     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
7614     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
7615   },
7616   {
7617     /* VEX_W_0F4A_P_2_LEN_1 */
7618     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
7619     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
7620   },
7621   {
7622     /* VEX_W_0F4B_P_0_LEN_1 */
7623     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
7624     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
7625   },
7626   {
7627     /* VEX_W_0F4B_P_2_LEN_1 */
7628     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
7629   },
7630   {
7631     /* VEX_W_0F90_P_0_LEN_0 */
7632     { "kmovw",          { MaskG, MaskE }, 0 },
7633     { "kmovq",          { MaskG, MaskE }, 0 },
7634   },
7635   {
7636     /* VEX_W_0F90_P_2_LEN_0 */
7637     { "kmovb",          { MaskG, MaskBDE }, 0 },
7638     { "kmovd",          { MaskG, MaskBDE }, 0 },
7639   },
7640   {
7641     /* VEX_W_0F91_P_0_LEN_0 */
7642     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
7643     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
7644   },
7645   {
7646     /* VEX_W_0F91_P_2_LEN_0 */
7647     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
7648     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
7649   },
7650   {
7651     /* VEX_W_0F92_P_0_LEN_0 */
7652     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
7653   },
7654   {
7655     /* VEX_W_0F92_P_2_LEN_0 */
7656     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
7657   },
7658   {
7659     /* VEX_W_0F93_P_0_LEN_0 */
7660     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
7661   },
7662   {
7663     /* VEX_W_0F93_P_2_LEN_0 */
7664     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
7665   },
7666   {
7667     /* VEX_W_0F98_P_0_LEN_0 */
7668     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
7669     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
7670   },
7671   {
7672     /* VEX_W_0F98_P_2_LEN_0 */
7673     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
7674     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
7675   },
7676   {
7677     /* VEX_W_0F99_P_0_LEN_0 */
7678     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
7679     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
7680   },
7681   {
7682     /* VEX_W_0F99_P_2_LEN_0 */
7683     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
7684     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
7685   },
7686   {
7687     /* VEX_W_0F380C  */
7688     { "vpermilps",      { XM, Vex, EXx }, PREFIX_DATA },
7689   },
7690   {
7691     /* VEX_W_0F380D  */
7692     { "vpermilpd",      { XM, Vex, EXx }, PREFIX_DATA },
7693   },
7694   {
7695     /* VEX_W_0F380E  */
7696     { "vtestps",        { XM, EXx }, PREFIX_DATA },
7697   },
7698   {
7699     /* VEX_W_0F380F  */
7700     { "vtestpd",        { XM, EXx }, PREFIX_DATA },
7701   },
7702   {
7703     /* VEX_W_0F3813 */
7704     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7705   },
7706   {
7707     /* VEX_W_0F3816_L_1  */
7708     { "vpermps",        { XM, Vex, EXx }, PREFIX_DATA },
7709   },
7710   {
7711     /* VEX_W_0F3818 */
7712     { "vbroadcastss",   { XM, EXxmm_md }, PREFIX_DATA },
7713   },
7714   {
7715     /* VEX_W_0F3819_L_1 */
7716     { "vbroadcastsd",   { XM, EXxmm_mq }, PREFIX_DATA },
7717   },
7718   {
7719     /* VEX_W_0F381A_M_0_L_1 */
7720     { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7721   },
7722   {
7723     /* VEX_W_0F382C_M_0 */
7724     { "vmaskmovps",     { XM, Vex, Mx }, PREFIX_DATA },
7725   },
7726   {
7727     /* VEX_W_0F382D_M_0 */
7728     { "vmaskmovpd",     { XM, Vex, Mx }, PREFIX_DATA },
7729   },
7730   {
7731     /* VEX_W_0F382E_M_0 */
7732     { "vmaskmovps",     { Mx, Vex, XM }, PREFIX_DATA },
7733   },
7734   {
7735     /* VEX_W_0F382F_M_0 */
7736     { "vmaskmovpd",     { Mx, Vex, XM }, PREFIX_DATA },
7737   },
7738   {
7739     /* VEX_W_0F3836  */
7740     { "vpermd",         { XM, Vex, EXx }, PREFIX_DATA },
7741   },
7742   {
7743     /* VEX_W_0F3846 */
7744     { "vpsravd",        { XM, Vex, EXx }, PREFIX_DATA },
7745   },
7746   {
7747     /* VEX_W_0F3849_X86_64_P_0 */
7748     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7749   },
7750   {
7751     /* VEX_W_0F3849_X86_64_P_2 */
7752     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7753   },
7754   {
7755     /* VEX_W_0F3849_X86_64_P_3 */
7756     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7757   },
7758   {
7759     /* VEX_W_0F384B_X86_64_P_1 */
7760     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7761   },
7762   {
7763     /* VEX_W_0F384B_X86_64_P_2 */
7764     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7765   },
7766   {
7767     /* VEX_W_0F384B_X86_64_P_3 */
7768     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7769   },
7770   {
7771     /* VEX_W_0F3858 */
7772     { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
7773   },
7774   {
7775     /* VEX_W_0F3859 */
7776     { "vpbroadcastq",   { XM, EXxmm_mq }, PREFIX_DATA },
7777   },
7778   {
7779     /* VEX_W_0F385A_M_0_L_0 */
7780     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7781   },
7782   {
7783     /* VEX_W_0F385C_X86_64_P_1 */
7784     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7785   },
7786   {
7787     /* VEX_W_0F385E_X86_64_P_0 */
7788     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7789   },
7790   {
7791     /* VEX_W_0F385E_X86_64_P_1 */
7792     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7793   },
7794   {
7795     /* VEX_W_0F385E_X86_64_P_2 */
7796     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7797   },
7798   {
7799     /* VEX_W_0F385E_X86_64_P_3 */
7800     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7801   },
7802   {
7803     /* VEX_W_0F3878 */
7804     { "vpbroadcastb",   { XM, EXxmm_mb }, PREFIX_DATA },
7805   },
7806   {
7807     /* VEX_W_0F3879 */
7808     { "vpbroadcastw",   { XM, EXxmm_mw }, PREFIX_DATA },
7809   },
7810   {
7811     /* VEX_W_0F38CF */
7812     { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7813   },
7814   {
7815     /* VEX_W_0F3A00_L_1 */
7816     { Bad_Opcode },
7817     { "vpermq",         { XM, EXx, Ib }, PREFIX_DATA },
7818   },
7819   {
7820     /* VEX_W_0F3A01_L_1 */
7821     { Bad_Opcode },
7822     { "vpermpd",        { XM, EXx, Ib }, PREFIX_DATA },
7823   },
7824   {
7825     /* VEX_W_0F3A02 */
7826     { "vpblendd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
7827   },
7828   {
7829     /* VEX_W_0F3A04 */
7830     { "vpermilps",      { XM, EXx, Ib }, PREFIX_DATA },
7831   },
7832   {
7833     /* VEX_W_0F3A05 */
7834     { "vpermilpd",      { XM, EXx, Ib }, PREFIX_DATA },
7835   },
7836   {
7837     /* VEX_W_0F3A06_L_1 */
7838     { "vperm2f128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7839   },
7840   {
7841     /* VEX_W_0F3A18_L_1 */
7842     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7843   },
7844   {
7845     /* VEX_W_0F3A19_L_1 */
7846     { "vextractf128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7847   },
7848   {
7849     /* VEX_W_0F3A1D */
7850     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7851   },
7852   {
7853     /* VEX_W_0F3A38_L_1 */
7854     { "vinserti128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7855   },
7856   {
7857     /* VEX_W_0F3A39_L_1 */
7858     { "vextracti128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7859   },
7860   {
7861     /* VEX_W_0F3A46_L_1 */
7862     { "vperm2i128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7863   },
7864   {
7865     /* VEX_W_0F3A4A */
7866     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7867   },
7868   {
7869     /* VEX_W_0F3A4B */
7870     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7871   },
7872   {
7873     /* VEX_W_0F3A4C */
7874     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7875   },
7876   {
7877     /* VEX_W_0F3ACE */
7878     { Bad_Opcode },
7879     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7880   },
7881   {
7882     /* VEX_W_0F3ACF */
7883     { Bad_Opcode },
7884     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7885   },
7886   /* VEX_W_0FXOP_08_85_L_0 */
7887   {
7888     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7889   },
7890   /* VEX_W_0FXOP_08_86_L_0 */
7891   {
7892     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7893   },
7894   /* VEX_W_0FXOP_08_87_L_0 */
7895   {
7896     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7897   },
7898   /* VEX_W_0FXOP_08_8E_L_0 */
7899   {
7900     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7901   },
7902   /* VEX_W_0FXOP_08_8F_L_0 */
7903   {
7904     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7905   },
7906   /* VEX_W_0FXOP_08_95_L_0 */
7907   {
7908     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7909   },
7910   /* VEX_W_0FXOP_08_96_L_0 */
7911   {
7912     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7913   },
7914   /* VEX_W_0FXOP_08_97_L_0 */
7915   {
7916     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7917   },
7918   /* VEX_W_0FXOP_08_9E_L_0 */
7919   {
7920     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7921   },
7922   /* VEX_W_0FXOP_08_9F_L_0 */
7923   {
7924     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
7925   },
7926   /* VEX_W_0FXOP_08_A6_L_0 */
7927   {
7928     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
7929   },
7930   /* VEX_W_0FXOP_08_B6_L_0 */
7931   {
7932     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7933   },
7934   /* VEX_W_0FXOP_08_C0_L_0 */
7935   {
7936     { "vprotb",         { XM, EXx, Ib }, 0 },
7937   },
7938   /* VEX_W_0FXOP_08_C1_L_0 */
7939   {
7940     { "vprotw",         { XM, EXx, Ib }, 0 },
7941   },
7942   /* VEX_W_0FXOP_08_C2_L_0 */
7943   {
7944     { "vprotd",         { XM, EXx, Ib }, 0 },
7945   },
7946   /* VEX_W_0FXOP_08_C3_L_0 */
7947   {
7948     { "vprotq",         { XM, EXx, Ib }, 0 },
7949   },
7950   /* VEX_W_0FXOP_08_CC_L_0 */
7951   {
7952      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
7953   },
7954   /* VEX_W_0FXOP_08_CD_L_0 */
7955   {
7956      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
7957   },
7958   /* VEX_W_0FXOP_08_CE_L_0 */
7959   {
7960      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
7961   },
7962   /* VEX_W_0FXOP_08_CF_L_0 */
7963   {
7964      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
7965   },
7966   /* VEX_W_0FXOP_08_EC_L_0 */
7967   {
7968      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
7969   },
7970   /* VEX_W_0FXOP_08_ED_L_0 */
7971   {
7972      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
7973   },
7974   /* VEX_W_0FXOP_08_EE_L_0 */
7975   {
7976      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
7977   },
7978   /* VEX_W_0FXOP_08_EF_L_0 */
7979   {
7980      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
7981   },
7982   /* VEX_W_0FXOP_09_80 */
7983   {
7984     { "vfrczps",        { XM, EXx }, 0 },
7985   },
7986   /* VEX_W_0FXOP_09_81 */
7987   {
7988     { "vfrczpd",        { XM, EXx }, 0 },
7989   },
7990   /* VEX_W_0FXOP_09_82 */
7991   {
7992     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7993   },
7994   /* VEX_W_0FXOP_09_83 */
7995   {
7996     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7997   },
7998   /* VEX_W_0FXOP_09_C1_L_0 */
7999   {
8000     { "vphaddbw",       { XM, EXxmm }, 0 },
8001   },
8002   /* VEX_W_0FXOP_09_C2_L_0 */
8003   {
8004     { "vphaddbd",       { XM, EXxmm }, 0 },
8005   },
8006   /* VEX_W_0FXOP_09_C3_L_0 */
8007   {
8008     { "vphaddbq",       { XM, EXxmm }, 0 },
8009   },
8010   /* VEX_W_0FXOP_09_C6_L_0 */
8011   {
8012     { "vphaddwd",       { XM, EXxmm }, 0 },
8013   },
8014   /* VEX_W_0FXOP_09_C7_L_0 */
8015   {
8016     { "vphaddwq",       { XM, EXxmm }, 0 },
8017   },
8018   /* VEX_W_0FXOP_09_CB_L_0 */
8019   {
8020     { "vphadddq",       { XM, EXxmm }, 0 },
8021   },
8022   /* VEX_W_0FXOP_09_D1_L_0 */
8023   {
8024     { "vphaddubw",      { XM, EXxmm }, 0 },
8025   },
8026   /* VEX_W_0FXOP_09_D2_L_0 */
8027   {
8028     { "vphaddubd",      { XM, EXxmm }, 0 },
8029   },
8030   /* VEX_W_0FXOP_09_D3_L_0 */
8031   {
8032     { "vphaddubq",      { XM, EXxmm }, 0 },
8033   },
8034   /* VEX_W_0FXOP_09_D6_L_0 */
8035   {
8036     { "vphadduwd",      { XM, EXxmm }, 0 },
8037   },
8038   /* VEX_W_0FXOP_09_D7_L_0 */
8039   {
8040     { "vphadduwq",      { XM, EXxmm }, 0 },
8041   },
8042   /* VEX_W_0FXOP_09_DB_L_0 */
8043   {
8044     { "vphaddudq",      { XM, EXxmm }, 0 },
8045   },
8046   /* VEX_W_0FXOP_09_E1_L_0 */
8047   {
8048     { "vphsubbw",       { XM, EXxmm }, 0 },
8049   },
8050   /* VEX_W_0FXOP_09_E2_L_0 */
8051   {
8052     { "vphsubwd",       { XM, EXxmm }, 0 },
8053   },
8054   /* VEX_W_0FXOP_09_E3_L_0 */
8055   {
8056     { "vphsubdq",       { XM, EXxmm }, 0 },
8057   },
8058
8059 #include "i386-dis-evex-w.h"
8060 };
8061
8062 static const struct dis386 mod_table[][2] = {
8063   {
8064     /* MOD_8D */
8065     { "leaS",           { Gv, M }, 0 },
8066   },
8067   {
8068     /* MOD_C6_REG_7 */
8069     { Bad_Opcode },
8070     { RM_TABLE (RM_C6_REG_7) },
8071   },
8072   {
8073     /* MOD_C7_REG_7 */
8074     { Bad_Opcode },
8075     { RM_TABLE (RM_C7_REG_7) },
8076   },
8077   {
8078     /* MOD_FF_REG_3 */
8079     { "{l|}call^", { indirEp }, 0 },
8080   },
8081   {
8082     /* MOD_FF_REG_5 */
8083     { "{l|}jmp^", { indirEp }, 0 },
8084   },
8085   {
8086     /* MOD_0F01_REG_0 */
8087     { X86_64_TABLE (X86_64_0F01_REG_0) },
8088     { RM_TABLE (RM_0F01_REG_0) },
8089   },
8090   {
8091     /* MOD_0F01_REG_1 */
8092     { X86_64_TABLE (X86_64_0F01_REG_1) },
8093     { RM_TABLE (RM_0F01_REG_1) },
8094   },
8095   {
8096     /* MOD_0F01_REG_2 */
8097     { X86_64_TABLE (X86_64_0F01_REG_2) },
8098     { RM_TABLE (RM_0F01_REG_2) },
8099   },
8100   {
8101     /* MOD_0F01_REG_3 */
8102     { X86_64_TABLE (X86_64_0F01_REG_3) },
8103     { RM_TABLE (RM_0F01_REG_3) },
8104   },
8105   {
8106     /* MOD_0F01_REG_5 */
8107     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8108     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8109   },
8110   {
8111     /* MOD_0F01_REG_7 */
8112     { "invlpg",         { Mb }, 0 },
8113     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8114   },
8115   {
8116     /* MOD_0F12_PREFIX_0 */
8117     { "movlpX",         { XM, EXq }, 0 },
8118     { "movhlps",        { XM, EXq }, 0 },
8119   },
8120   {
8121     /* MOD_0F12_PREFIX_2 */
8122     { "movlpX", { XM, EXq }, 0 },
8123   },
8124   {
8125     /* MOD_0F13 */
8126     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
8127   },
8128   {
8129     /* MOD_0F16_PREFIX_0 */
8130     { "movhpX",         { XM, EXq }, 0 },
8131     { "movlhps",        { XM, EXq }, 0 },
8132   },
8133   {
8134     /* MOD_0F16_PREFIX_2 */
8135     { "movhpX", { XM, EXq }, 0 },
8136   },
8137   {
8138     /* MOD_0F17 */
8139     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
8140   },
8141   {
8142     /* MOD_0F18_REG_0 */
8143     { "prefetchnta",    { Mb }, 0 },
8144   },
8145   {
8146     /* MOD_0F18_REG_1 */
8147     { "prefetcht0",     { Mb }, 0 },
8148   },
8149   {
8150     /* MOD_0F18_REG_2 */
8151     { "prefetcht1",     { Mb }, 0 },
8152   },
8153   {
8154     /* MOD_0F18_REG_3 */
8155     { "prefetcht2",     { Mb }, 0 },
8156   },
8157   {
8158     /* MOD_0F18_REG_4 */
8159     { "nop/reserved",   { Mb }, 0 },
8160   },
8161   {
8162     /* MOD_0F18_REG_5 */
8163     { "nop/reserved",   { Mb }, 0 },
8164   },
8165   {
8166     /* MOD_0F18_REG_6 */
8167     { "nop/reserved",   { Mb }, 0 },
8168   },
8169   {
8170     /* MOD_0F18_REG_7 */
8171     { "nop/reserved",   { Mb }, 0 },
8172   },
8173   {
8174     /* MOD_0F1A_PREFIX_0 */
8175     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
8176     { "nopQ",           { Ev }, 0 },
8177   },
8178   {
8179     /* MOD_0F1B_PREFIX_0 */
8180     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
8181     { "nopQ",           { Ev }, 0 },
8182   },
8183   {
8184     /* MOD_0F1B_PREFIX_1 */
8185     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
8186     { "nopQ",           { Ev }, 0 },
8187   },
8188   {
8189     /* MOD_0F1C_PREFIX_0 */
8190     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8191     { "nopQ",           { Ev }, 0 },
8192   },
8193   {
8194     /* MOD_0F1E_PREFIX_1 */
8195     { "nopQ",           { Ev }, 0 },
8196     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8197   },
8198   {
8199     /* MOD_0F2B_PREFIX_0 */
8200     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
8201   },
8202   {
8203     /* MOD_0F2B_PREFIX_1 */
8204     {"movntss",         { Md, XM }, PREFIX_OPCODE },
8205   },
8206   {
8207     /* MOD_0F2B_PREFIX_2 */
8208     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
8209   },
8210   {
8211     /* MOD_0F2B_PREFIX_3 */
8212     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
8213   },
8214   {
8215     /* MOD_0F50 */
8216     { Bad_Opcode },
8217     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
8218   },
8219   {
8220     /* MOD_0F71_REG_2 */
8221     { Bad_Opcode },
8222     { "psrlw",          { MS, Ib }, PREFIX_OPCODE },
8223   },
8224   {
8225     /* MOD_0F71_REG_4 */
8226     { Bad_Opcode },
8227     { "psraw",          { MS, Ib }, PREFIX_OPCODE },
8228   },
8229   {
8230     /* MOD_0F71_REG_6 */
8231     { Bad_Opcode },
8232     { "psllw",          { MS, Ib }, PREFIX_OPCODE },
8233   },
8234   {
8235     /* MOD_0F72_REG_2 */
8236     { Bad_Opcode },
8237     { "psrld",          { MS, Ib }, PREFIX_OPCODE },
8238   },
8239   {
8240     /* MOD_0F72_REG_4 */
8241     { Bad_Opcode },
8242     { "psrad",          { MS, Ib }, PREFIX_OPCODE },
8243   },
8244   {
8245     /* MOD_0F72_REG_6 */
8246     { Bad_Opcode },
8247     { "pslld",          { MS, Ib }, PREFIX_OPCODE },
8248   },
8249   {
8250     /* MOD_0F73_REG_2 */
8251     { Bad_Opcode },
8252     { "psrlq",          { MS, Ib }, PREFIX_OPCODE },
8253   },
8254   {
8255     /* MOD_0F73_REG_3 */
8256     { Bad_Opcode },
8257     { "psrldq",         { XS, Ib }, PREFIX_DATA },
8258   },
8259   {
8260     /* MOD_0F73_REG_6 */
8261     { Bad_Opcode },
8262     { "psllq",          { MS, Ib }, PREFIX_OPCODE },
8263   },
8264   {
8265     /* MOD_0F73_REG_7 */
8266     { Bad_Opcode },
8267     { "pslldq",         { XS, Ib }, PREFIX_DATA },
8268   },
8269   {
8270     /* MOD_0FAE_REG_0 */
8271     { "fxsave",         { FXSAVE }, 0 },
8272     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8273   },
8274   {
8275     /* MOD_0FAE_REG_1 */
8276     { "fxrstor",        { FXSAVE }, 0 },
8277     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8278   },
8279   {
8280     /* MOD_0FAE_REG_2 */
8281     { "ldmxcsr",        { Md }, 0 },
8282     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8283   },
8284   {
8285     /* MOD_0FAE_REG_3 */
8286     { "stmxcsr",        { Md }, 0 },
8287     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8288   },
8289   {
8290     /* MOD_0FAE_REG_4 */
8291     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8292     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8293   },
8294   {
8295     /* MOD_0FAE_REG_5 */
8296     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
8297     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8298   },
8299   {
8300     /* MOD_0FAE_REG_6 */
8301     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8302     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8303   },
8304   {
8305     /* MOD_0FAE_REG_7 */
8306     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8307     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8308   },
8309   {
8310     /* MOD_0FB2 */
8311     { "lssS",           { Gv, Mp }, 0 },
8312   },
8313   {
8314     /* MOD_0FB4 */
8315     { "lfsS",           { Gv, Mp }, 0 },
8316   },
8317   {
8318     /* MOD_0FB5 */
8319     { "lgsS",           { Gv, Mp }, 0 },
8320   },
8321   {
8322     /* MOD_0FC3 */
8323     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8324   },
8325   {
8326     /* MOD_0FC7_REG_3 */
8327     { "xrstors",        { FXSAVE }, 0 },
8328   },
8329   {
8330     /* MOD_0FC7_REG_4 */
8331     { "xsavec",         { FXSAVE }, 0 },
8332   },
8333   {
8334     /* MOD_0FC7_REG_5 */
8335     { "xsaves",         { FXSAVE }, 0 },
8336   },
8337   {
8338     /* MOD_0FC7_REG_6 */
8339     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8340     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8341   },
8342   {
8343     /* MOD_0FC7_REG_7 */
8344     { "vmptrst",        { Mq }, 0 },
8345     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8346   },
8347   {
8348     /* MOD_0FD7 */
8349     { Bad_Opcode },
8350     { "pmovmskb",       { Gdq, MS }, 0 },
8351   },
8352   {
8353     /* MOD_0FE7_PREFIX_2 */
8354     { "movntdq",        { Mx, XM }, 0 },
8355   },
8356   {
8357     /* MOD_0FF0_PREFIX_3 */
8358     { "lddqu",          { XM, M }, 0 },
8359   },
8360   {
8361     /* MOD_0F382A */
8362     { "movntdqa",       { XM, Mx }, PREFIX_DATA },
8363   },
8364   {
8365     /* MOD_0F38DC_PREFIX_1 */
8366     { "aesenc128kl",    { XM, M }, 0 },
8367     { "loadiwkey",      { XM, EXx }, 0 },
8368   },
8369   {
8370     /* MOD_0F38DD_PREFIX_1 */
8371     { "aesdec128kl",    { XM, M }, 0 },
8372   },
8373   {
8374     /* MOD_0F38DE_PREFIX_1 */
8375     { "aesenc256kl",    { XM, M }, 0 },
8376   },
8377   {
8378     /* MOD_0F38DF_PREFIX_1 */
8379     { "aesdec256kl",    { XM, M }, 0 },
8380   },
8381   {
8382     /* MOD_0F38F5 */
8383     { "wrussK",         { M, Gdq }, PREFIX_DATA },
8384   },
8385   {
8386     /* MOD_0F38F6_PREFIX_0 */
8387     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
8388   },
8389   {
8390     /* MOD_0F38F8_PREFIX_1 */
8391     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
8392   },
8393   {
8394     /* MOD_0F38F8_PREFIX_2 */
8395     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
8396   },
8397   {
8398     /* MOD_0F38F8_PREFIX_3 */
8399     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
8400   },
8401   {
8402     /* MOD_0F38F9 */
8403     { "movdiri",        { Edq, Gdq }, PREFIX_OPCODE },
8404   },
8405   {
8406     /* MOD_0F38FA_PREFIX_1 */
8407     { Bad_Opcode },
8408     { "encodekey128", { Gd, Ed }, 0 },
8409   },
8410   {
8411     /* MOD_0F38FB_PREFIX_1 */
8412     { Bad_Opcode },
8413     { "encodekey256", { Gd, Ed }, 0 },
8414   },
8415   {
8416     /* MOD_0F3A0F_PREFIX_1 */
8417     { Bad_Opcode },
8418     { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8419   },
8420   {
8421     /* MOD_62_32BIT */
8422     { "bound{S|}",      { Gv, Ma }, 0 },
8423     { EVEX_TABLE (EVEX_0F) },
8424   },
8425   {
8426     /* MOD_C4_32BIT */
8427     { "lesS",           { Gv, Mp }, 0 },
8428     { VEX_C4_TABLE (VEX_0F) },
8429   },
8430   {
8431     /* MOD_C5_32BIT */
8432     { "ldsS",           { Gv, Mp }, 0 },
8433     { VEX_C5_TABLE (VEX_0F) },
8434   },
8435   {
8436     /* MOD_VEX_0F12_PREFIX_0 */
8437     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8438     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8439   },
8440   {
8441     /* MOD_VEX_0F12_PREFIX_2 */
8442     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8443   },
8444   {
8445     /* MOD_VEX_0F13 */
8446     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8447   },
8448   {
8449     /* MOD_VEX_0F16_PREFIX_0 */
8450     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8451     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8452   },
8453   {
8454     /* MOD_VEX_0F16_PREFIX_2 */
8455     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8456   },
8457   {
8458     /* MOD_VEX_0F17 */
8459     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8460   },
8461   {
8462     /* MOD_VEX_0F2B */
8463     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
8464   },
8465   {
8466     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
8467     { Bad_Opcode },
8468     { "kandw",          { MaskG, MaskVex, MaskE }, 0 },
8469   },
8470   {
8471     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
8472     { Bad_Opcode },
8473     { "kandq",          { MaskG, MaskVex, MaskE }, 0 },
8474   },
8475   {
8476     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
8477     { Bad_Opcode },
8478     { "kandb",          { MaskG, MaskVex, MaskE }, 0 },
8479   },
8480   {
8481     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
8482     { Bad_Opcode },
8483     { "kandd",          { MaskG, MaskVex, MaskE }, 0 },
8484   },
8485   {
8486     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
8487     { Bad_Opcode },
8488     { "kandnw",         { MaskG, MaskVex, MaskE }, 0 },
8489   },
8490   {
8491     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
8492     { Bad_Opcode },
8493     { "kandnq",         { MaskG, MaskVex, MaskE }, 0 },
8494   },
8495   {
8496     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
8497     { Bad_Opcode },
8498     { "kandnb",         { MaskG, MaskVex, MaskE }, 0 },
8499   },
8500   {
8501     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
8502     { Bad_Opcode },
8503     { "kandnd",         { MaskG, MaskVex, MaskE }, 0 },
8504   },
8505   {
8506     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
8507     { Bad_Opcode },
8508     { "knotw",          { MaskG, MaskE }, 0 },
8509   },
8510   {
8511     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
8512     { Bad_Opcode },
8513     { "knotq",          { MaskG, MaskE }, 0 },
8514   },
8515   {
8516     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
8517     { Bad_Opcode },
8518     { "knotb",          { MaskG, MaskE }, 0 },
8519   },
8520   {
8521     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
8522     { Bad_Opcode },
8523     { "knotd",          { MaskG, MaskE }, 0 },
8524   },
8525   {
8526     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
8527     { Bad_Opcode },
8528     { "korw",       { MaskG, MaskVex, MaskE }, 0 },
8529   },
8530   {
8531     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
8532     { Bad_Opcode },
8533     { "korq",       { MaskG, MaskVex, MaskE }, 0 },
8534   },
8535   {
8536     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
8537     { Bad_Opcode },
8538     { "korb",       { MaskG, MaskVex, MaskE }, 0 },
8539   },
8540   {
8541     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
8542     { Bad_Opcode },
8543     { "kord",       { MaskG, MaskVex, MaskE }, 0 },
8544   },
8545  {
8546     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
8547     { Bad_Opcode },
8548     { "kxnorw",     { MaskG, MaskVex, MaskE }, 0 },
8549   },
8550   {
8551     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
8552     { Bad_Opcode },
8553     { "kxnorq",     { MaskG, MaskVex, MaskE }, 0 },
8554   },
8555   {
8556     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
8557     { Bad_Opcode },
8558     { "kxnorb",     { MaskG, MaskVex, MaskE }, 0 },
8559   },
8560   {
8561     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
8562     { Bad_Opcode },
8563     { "kxnord",     { MaskG, MaskVex, MaskE }, 0 },
8564   },
8565   {
8566     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
8567     { Bad_Opcode },
8568     { "kxorw",      { MaskG, MaskVex, MaskE }, 0 },
8569   },
8570   {
8571     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
8572     { Bad_Opcode },
8573     { "kxorq",      { MaskG, MaskVex, MaskE }, 0 },
8574   },
8575   {
8576     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
8577     { Bad_Opcode },
8578     { "kxorb",      { MaskG, MaskVex, MaskE }, 0 },
8579   },
8580   {
8581     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
8582     { Bad_Opcode },
8583     { "kxord",      { MaskG, MaskVex, MaskE }, 0 },
8584   },
8585   {
8586     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
8587     { Bad_Opcode },
8588     { "kaddw",          { MaskG, MaskVex, MaskE }, 0 },
8589   },
8590   {
8591     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
8592     { Bad_Opcode },
8593     { "kaddq",          { MaskG, MaskVex, MaskE }, 0 },
8594   },
8595   {
8596     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
8597     { Bad_Opcode },
8598     { "kaddb",          { MaskG, MaskVex, MaskE }, 0 },
8599   },
8600   {
8601     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
8602     { Bad_Opcode },
8603     { "kaddd",          { MaskG, MaskVex, MaskE }, 0 },
8604   },
8605   {
8606     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
8607     { Bad_Opcode },
8608     { "kunpckwd",   { MaskG, MaskVex, MaskE }, 0 },
8609   },
8610   {
8611     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
8612     { Bad_Opcode },
8613     { "kunpckdq",   { MaskG, MaskVex, MaskE }, 0 },
8614   },
8615   {
8616     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
8617     { Bad_Opcode },
8618     { "kunpckbw",   { MaskG, MaskVex, MaskE }, 0 },
8619   },
8620   {
8621     /* MOD_VEX_0F50 */
8622     { Bad_Opcode },
8623     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
8624   },
8625   {
8626     /* MOD_VEX_0F71_REG_2 */
8627     { Bad_Opcode },
8628     { "vpsrlw",         { Vex, XS, Ib }, PREFIX_DATA },
8629   },
8630   {
8631     /* MOD_VEX_0F71_REG_4 */
8632     { Bad_Opcode },
8633     { "vpsraw",         { Vex, XS, Ib }, PREFIX_DATA },
8634   },
8635   {
8636     /* MOD_VEX_0F71_REG_6 */
8637     { Bad_Opcode },
8638     { "vpsllw",         { Vex, XS, Ib }, PREFIX_DATA },
8639   },
8640   {
8641     /* MOD_VEX_0F72_REG_2 */
8642     { Bad_Opcode },
8643     { "vpsrld",         { Vex, XS, Ib }, PREFIX_DATA },
8644   },
8645   {
8646     /* MOD_VEX_0F72_REG_4 */
8647     { Bad_Opcode },
8648     { "vpsrad",         { Vex, XS, Ib }, PREFIX_DATA },
8649   },
8650   {
8651     /* MOD_VEX_0F72_REG_6 */
8652     { Bad_Opcode },
8653     { "vpslld",         { Vex, XS, Ib }, PREFIX_DATA },
8654   },
8655   {
8656     /* MOD_VEX_0F73_REG_2 */
8657     { Bad_Opcode },
8658     { "vpsrlq",         { Vex, XS, Ib }, PREFIX_DATA },
8659   },
8660   {
8661     /* MOD_VEX_0F73_REG_3 */
8662     { Bad_Opcode },
8663     { "vpsrldq",        { Vex, XS, Ib }, PREFIX_DATA },
8664   },
8665   {
8666     /* MOD_VEX_0F73_REG_6 */
8667     { Bad_Opcode },
8668     { "vpsllq",         { Vex, XS, Ib }, PREFIX_DATA },
8669   },
8670   {
8671     /* MOD_VEX_0F73_REG_7 */
8672     { Bad_Opcode },
8673     { "vpslldq",        { Vex, XS, Ib }, PREFIX_DATA },
8674   },
8675   {
8676     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8677     { "kmovw",          { Ew, MaskG }, 0 },
8678     { Bad_Opcode },
8679   },
8680   {
8681     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8682     { "kmovq",          { Eq, MaskG }, 0 },
8683     { Bad_Opcode },
8684   },
8685   {
8686     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8687     { "kmovb",          { Eb, MaskG }, 0 },
8688     { Bad_Opcode },
8689   },
8690   {
8691     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8692     { "kmovd",          { Ed, MaskG }, 0 },
8693     { Bad_Opcode },
8694   },
8695   {
8696     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
8697     { Bad_Opcode },
8698     { "kmovw",          { MaskG, Edq }, 0 },
8699   },
8700   {
8701     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
8702     { Bad_Opcode },
8703     { "kmovb",          { MaskG, Edq }, 0 },
8704   },
8705   {
8706     /* MOD_VEX_0F92_P_3_LEN_0 */
8707     { Bad_Opcode },
8708     { "kmovK",          { MaskG, Edq }, 0 },
8709   },
8710   {
8711     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
8712     { Bad_Opcode },
8713     { "kmovw",          { Gdq, MaskE }, 0 },
8714   },
8715   {
8716     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
8717     { Bad_Opcode },
8718     { "kmovb",          { Gdq, MaskE }, 0 },
8719   },
8720   {
8721     /* MOD_VEX_0F93_P_3_LEN_0 */
8722     { Bad_Opcode },
8723     { "kmovK",          { Gdq, MaskE }, 0 },
8724   },
8725   {
8726     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
8727     { Bad_Opcode },
8728     { "kortestw", { MaskG, MaskE }, 0 },
8729   },
8730   {
8731     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
8732     { Bad_Opcode },
8733     { "kortestq", { MaskG, MaskE }, 0 },
8734   },
8735   {
8736     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
8737     { Bad_Opcode },
8738     { "kortestb", { MaskG, MaskE }, 0 },
8739   },
8740   {
8741     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
8742     { Bad_Opcode },
8743     { "kortestd", { MaskG, MaskE }, 0 },
8744   },
8745   {
8746     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
8747     { Bad_Opcode },
8748     { "ktestw", { MaskG, MaskE }, 0 },
8749   },
8750   {
8751     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
8752     { Bad_Opcode },
8753     { "ktestq", { MaskG, MaskE }, 0 },
8754   },
8755   {
8756     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
8757     { Bad_Opcode },
8758     { "ktestb", { MaskG, MaskE }, 0 },
8759   },
8760   {
8761     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
8762     { Bad_Opcode },
8763     { "ktestd", { MaskG, MaskE }, 0 },
8764   },
8765   {
8766     /* MOD_VEX_0FAE_REG_2 */
8767     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8768   },
8769   {
8770     /* MOD_VEX_0FAE_REG_3 */
8771     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8772   },
8773   {
8774     /* MOD_VEX_0FD7 */
8775     { Bad_Opcode },
8776     { "vpmovmskb",      { Gdq, XS }, PREFIX_DATA },
8777   },
8778   {
8779     /* MOD_VEX_0FE7 */
8780     { "vmovntdq",       { Mx, XM }, PREFIX_DATA },
8781   },
8782   {
8783     /* MOD_VEX_0FF0_PREFIX_3 */
8784     { "vlddqu",         { XM, M }, 0 },
8785   },
8786   {
8787     /* MOD_VEX_0F381A */
8788     { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8789   },
8790   {
8791     /* MOD_VEX_0F382A */
8792     { "vmovntdqa",      { XM, Mx }, PREFIX_DATA },
8793   },
8794   {
8795     /* MOD_VEX_0F382C */
8796     { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8797   },
8798   {
8799     /* MOD_VEX_0F382D */
8800     { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8801   },
8802   {
8803     /* MOD_VEX_0F382E */
8804     { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8805   },
8806   {
8807     /* MOD_VEX_0F382F */
8808     { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8809   },
8810   {
8811     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8812     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8813     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8814   },
8815   {
8816     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8817     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8818   },
8819   {
8820     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8821     { Bad_Opcode },
8822     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8823   },
8824   {
8825     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8826     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8827   },
8828   {
8829     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8830     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8831   },
8832   {
8833     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8834     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8835   },
8836   {
8837     /* MOD_VEX_0F385A */
8838     { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8839   },
8840   {
8841     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8842     { Bad_Opcode },
8843     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8844   },
8845   {
8846     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8847     { Bad_Opcode },
8848     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8849   },
8850   {
8851     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8852     { Bad_Opcode },
8853     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8854   },
8855   {
8856     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8857     { Bad_Opcode },
8858     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8859   },
8860   {
8861     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8862     { Bad_Opcode },
8863     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8864   },
8865   {
8866     /* MOD_VEX_0F388C */
8867     { "vpmaskmov%DQ",   { XM, Vex, Mx }, PREFIX_DATA },
8868   },
8869   {
8870     /* MOD_VEX_0F388E */
8871     { "vpmaskmov%DQ",   { Mx, Vex, XM }, PREFIX_DATA },
8872   },
8873   {
8874     /* MOD_VEX_0F3A30_L_0 */
8875     { Bad_Opcode },
8876     { "kshiftr%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8877   },
8878   {
8879     /* MOD_VEX_0F3A31_L_0 */
8880     { Bad_Opcode },
8881     { "kshiftr%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8882   },
8883   {
8884     /* MOD_VEX_0F3A32_L_0 */
8885     { Bad_Opcode },
8886     { "kshiftl%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8887   },
8888   {
8889     /* MOD_VEX_0F3A33_L_0 */
8890     { Bad_Opcode },
8891     { "kshiftl%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8892   },
8893   {
8894     /* MOD_VEX_0FXOP_09_12 */
8895     { Bad_Opcode },
8896     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8897   },
8898
8899 #include "i386-dis-evex-mod.h"
8900 };
8901
8902 static const struct dis386 rm_table[][8] = {
8903   {
8904     /* RM_C6_REG_7 */
8905     { "xabort",         { Skip_MODRM, Ib }, 0 },
8906   },
8907   {
8908     /* RM_C7_REG_7 */
8909     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
8910   },
8911   {
8912     /* RM_0F01_REG_0 */
8913     { "enclv",          { Skip_MODRM }, 0 },
8914     { "vmcall",         { Skip_MODRM }, 0 },
8915     { "vmlaunch",       { Skip_MODRM }, 0 },
8916     { "vmresume",       { Skip_MODRM }, 0 },
8917     { "vmxoff",         { Skip_MODRM }, 0 },
8918     { "pconfig",        { Skip_MODRM }, 0 },
8919   },
8920   {
8921     /* RM_0F01_REG_1 */
8922     { "monitor",        { { OP_Monitor, 0 } }, 0 },
8923     { "mwait",          { { OP_Mwait, 0 } }, 0 },
8924     { "clac",           { Skip_MODRM }, 0 },
8925     { "stac",           { Skip_MODRM }, 0 },
8926     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8927     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8928     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8929     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8930   },
8931   {
8932     /* RM_0F01_REG_2 */
8933     { "xgetbv",         { Skip_MODRM }, 0 },
8934     { "xsetbv",         { Skip_MODRM }, 0 },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { "vmfunc",         { Skip_MODRM }, 0 },
8938     { "xend",           { Skip_MODRM }, 0 },
8939     { "xtest",          { Skip_MODRM }, 0 },
8940     { "enclu",          { Skip_MODRM }, 0 },
8941   },
8942   {
8943     /* RM_0F01_REG_3 */
8944     { "vmrun",          { Skip_MODRM }, 0 },
8945     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8946     { "vmload",         { Skip_MODRM }, 0 },
8947     { "vmsave",         { Skip_MODRM }, 0 },
8948     { "stgi",           { Skip_MODRM }, 0 },
8949     { "clgi",           { Skip_MODRM }, 0 },
8950     { "skinit",         { Skip_MODRM }, 0 },
8951     { "invlpga",        { Skip_MODRM }, 0 },
8952   },
8953   {
8954     /* RM_0F01_REG_5_MOD_3 */
8955     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8956     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8957     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8958     { Bad_Opcode },
8959     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8960     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8961     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8962     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8963   },
8964   {
8965     /* RM_0F01_REG_7_MOD_3 */
8966     { "swapgs",         { Skip_MODRM }, 0  },
8967     { "rdtscp",         { Skip_MODRM }, 0  },
8968     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8969     { "mwaitx",         { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8970     { "clzero",         { Skip_MODRM }, 0  },
8971     { "rdpru",          { Skip_MODRM }, 0  },
8972   },
8973   {
8974     /* RM_0F1E_P_1_MOD_3_REG_7 */
8975     { "nopQ",           { Ev }, 0 },
8976     { "nopQ",           { Ev }, 0 },
8977     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
8978     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
8979     { "nopQ",           { Ev }, 0 },
8980     { "nopQ",           { Ev }, 0 },
8981     { "nopQ",           { Ev }, 0 },
8982     { "nopQ",           { Ev }, 0 },
8983   },
8984   {
8985     /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8986     { "hreset",         { Skip_MODRM, Ib }, 0 },
8987   },
8988   {
8989     /* RM_0FAE_REG_6_MOD_3 */
8990     { "mfence",         { Skip_MODRM }, 0 },
8991   },
8992   {
8993     /* RM_0FAE_REG_7_MOD_3 */
8994     { "sfence",         { Skip_MODRM }, 0 },
8995
8996   },
8997   {
8998     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8999     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
9000   },
9001 };
9002
9003 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9004
9005 /* We use the high bit to indicate different name for the same
9006    prefix.  */
9007 #define REP_PREFIX      (0xf3 | 0x100)
9008 #define XACQUIRE_PREFIX (0xf2 | 0x200)
9009 #define XRELEASE_PREFIX (0xf3 | 0x400)
9010 #define BND_PREFIX      (0xf2 | 0x400)
9011 #define NOTRACK_PREFIX  (0x3e | 0x100)
9012
9013 /* Remember if the current op is a jump instruction.  */
9014 static bfd_boolean op_is_jump = FALSE;
9015
9016 static int
9017 ckprefix (void)
9018 {
9019   int newrex, i, length;
9020   rex = 0;
9021   prefixes = 0;
9022   used_prefixes = 0;
9023   rex_used = 0;
9024   last_lock_prefix = -1;
9025   last_repz_prefix = -1;
9026   last_repnz_prefix = -1;
9027   last_data_prefix = -1;
9028   last_addr_prefix = -1;
9029   last_rex_prefix = -1;
9030   last_seg_prefix = -1;
9031   fwait_prefix = -1;
9032   active_seg_prefix = 0;
9033   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9034     all_prefixes[i] = 0;
9035   i = 0;
9036   length = 0;
9037   /* The maximum instruction length is 15bytes.  */
9038   while (length < MAX_CODE_LENGTH - 1)
9039     {
9040       FETCH_DATA (the_info, codep + 1);
9041       newrex = 0;
9042       switch (*codep)
9043         {
9044         /* REX prefixes family.  */
9045         case 0x40:
9046         case 0x41:
9047         case 0x42:
9048         case 0x43:
9049         case 0x44:
9050         case 0x45:
9051         case 0x46:
9052         case 0x47:
9053         case 0x48:
9054         case 0x49:
9055         case 0x4a:
9056         case 0x4b:
9057         case 0x4c:
9058         case 0x4d:
9059         case 0x4e:
9060         case 0x4f:
9061           if (address_mode == mode_64bit)
9062             newrex = *codep;
9063           else
9064             return 1;
9065           last_rex_prefix = i;
9066           break;
9067         case 0xf3:
9068           prefixes |= PREFIX_REPZ;
9069           last_repz_prefix = i;
9070           break;
9071         case 0xf2:
9072           prefixes |= PREFIX_REPNZ;
9073           last_repnz_prefix = i;
9074           break;
9075         case 0xf0:
9076           prefixes |= PREFIX_LOCK;
9077           last_lock_prefix = i;
9078           break;
9079         case 0x2e:
9080           prefixes |= PREFIX_CS;
9081           last_seg_prefix = i;
9082           active_seg_prefix = PREFIX_CS;
9083           break;
9084         case 0x36:
9085           prefixes |= PREFIX_SS;
9086           last_seg_prefix = i;
9087           active_seg_prefix = PREFIX_SS;
9088           break;
9089         case 0x3e:
9090           prefixes |= PREFIX_DS;
9091           last_seg_prefix = i;
9092           active_seg_prefix = PREFIX_DS;
9093           break;
9094         case 0x26:
9095           prefixes |= PREFIX_ES;
9096           last_seg_prefix = i;
9097           active_seg_prefix = PREFIX_ES;
9098           break;
9099         case 0x64:
9100           prefixes |= PREFIX_FS;
9101           last_seg_prefix = i;
9102           active_seg_prefix = PREFIX_FS;
9103           break;
9104         case 0x65:
9105           prefixes |= PREFIX_GS;
9106           last_seg_prefix = i;
9107           active_seg_prefix = PREFIX_GS;
9108           break;
9109         case 0x66:
9110           prefixes |= PREFIX_DATA;
9111           last_data_prefix = i;
9112           break;
9113         case 0x67:
9114           prefixes |= PREFIX_ADDR;
9115           last_addr_prefix = i;
9116           break;
9117         case FWAIT_OPCODE:
9118           /* fwait is really an instruction.  If there are prefixes
9119              before the fwait, they belong to the fwait, *not* to the
9120              following instruction.  */
9121           fwait_prefix = i;
9122           if (prefixes || rex)
9123             {
9124               prefixes |= PREFIX_FWAIT;
9125               codep++;
9126               /* This ensures that the previous REX prefixes are noticed
9127                  as unused prefixes, as in the return case below.  */
9128               rex_used = rex;
9129               return 1;
9130             }
9131           prefixes = PREFIX_FWAIT;
9132           break;
9133         default:
9134           return 1;
9135         }
9136       /* Rex is ignored when followed by another prefix.  */
9137       if (rex)
9138         {
9139           rex_used = rex;
9140           return 1;
9141         }
9142       if (*codep != FWAIT_OPCODE)
9143         all_prefixes[i++] = *codep;
9144       rex = newrex;
9145       codep++;
9146       length++;
9147     }
9148   return 0;
9149 }
9150
9151 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9152    prefix byte.  */
9153
9154 static const char *
9155 prefix_name (int pref, int sizeflag)
9156 {
9157   static const char *rexes [16] =
9158     {
9159       "rex",            /* 0x40 */
9160       "rex.B",          /* 0x41 */
9161       "rex.X",          /* 0x42 */
9162       "rex.XB",         /* 0x43 */
9163       "rex.R",          /* 0x44 */
9164       "rex.RB",         /* 0x45 */
9165       "rex.RX",         /* 0x46 */
9166       "rex.RXB",        /* 0x47 */
9167       "rex.W",          /* 0x48 */
9168       "rex.WB",         /* 0x49 */
9169       "rex.WX",         /* 0x4a */
9170       "rex.WXB",        /* 0x4b */
9171       "rex.WR",         /* 0x4c */
9172       "rex.WRB",        /* 0x4d */
9173       "rex.WRX",        /* 0x4e */
9174       "rex.WRXB",       /* 0x4f */
9175     };
9176
9177   switch (pref)
9178     {
9179     /* REX prefixes family.  */
9180     case 0x40:
9181     case 0x41:
9182     case 0x42:
9183     case 0x43:
9184     case 0x44:
9185     case 0x45:
9186     case 0x46:
9187     case 0x47:
9188     case 0x48:
9189     case 0x49:
9190     case 0x4a:
9191     case 0x4b:
9192     case 0x4c:
9193     case 0x4d:
9194     case 0x4e:
9195     case 0x4f:
9196       return rexes [pref - 0x40];
9197     case 0xf3:
9198       return "repz";
9199     case 0xf2:
9200       return "repnz";
9201     case 0xf0:
9202       return "lock";
9203     case 0x2e:
9204       return "cs";
9205     case 0x36:
9206       return "ss";
9207     case 0x3e:
9208       return "ds";
9209     case 0x26:
9210       return "es";
9211     case 0x64:
9212       return "fs";
9213     case 0x65:
9214       return "gs";
9215     case 0x66:
9216       return (sizeflag & DFLAG) ? "data16" : "data32";
9217     case 0x67:
9218       if (address_mode == mode_64bit)
9219         return (sizeflag & AFLAG) ? "addr32" : "addr64";
9220       else
9221         return (sizeflag & AFLAG) ? "addr16" : "addr32";
9222     case FWAIT_OPCODE:
9223       return "fwait";
9224     case REP_PREFIX:
9225       return "rep";
9226     case XACQUIRE_PREFIX:
9227       return "xacquire";
9228     case XRELEASE_PREFIX:
9229       return "xrelease";
9230     case BND_PREFIX:
9231       return "bnd";
9232     case NOTRACK_PREFIX:
9233       return "notrack";
9234     default:
9235       return NULL;
9236     }
9237 }
9238
9239 static char op_out[MAX_OPERANDS][100];
9240 static int op_ad, op_index[MAX_OPERANDS];
9241 static int two_source_ops;
9242 static bfd_vma op_address[MAX_OPERANDS];
9243 static bfd_vma op_riprel[MAX_OPERANDS];
9244 static bfd_vma start_pc;
9245
9246 /*
9247  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9248  *   (see topic "Redundant prefixes" in the "Differences from 8086"
9249  *   section of the "Virtual 8086 Mode" chapter.)
9250  * 'pc' should be the address of this instruction, it will
9251  *   be used to print the target address if this is a relative jump or call
9252  * The function returns the length of this instruction in bytes.
9253  */
9254
9255 static char intel_syntax;
9256 static char intel_mnemonic = !SYSV386_COMPAT;
9257 static char open_char;
9258 static char close_char;
9259 static char separator_char;
9260 static char scale_char;
9261
9262 enum x86_64_isa
9263 {
9264   amd64 = 1,
9265   intel64
9266 };
9267
9268 static enum x86_64_isa isa64;
9269
9270 /* Here for backwards compatibility.  When gdb stops using
9271    print_insn_i386_att and print_insn_i386_intel these functions can
9272    disappear, and print_insn_i386 be merged into print_insn.  */
9273 int
9274 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9275 {
9276   intel_syntax = 0;
9277
9278   return print_insn (pc, info);
9279 }
9280
9281 int
9282 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9283 {
9284   intel_syntax = 1;
9285
9286   return print_insn (pc, info);
9287 }
9288
9289 int
9290 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9291 {
9292   intel_syntax = -1;
9293
9294   return print_insn (pc, info);
9295 }
9296
9297 void
9298 print_i386_disassembler_options (FILE *stream)
9299 {
9300   fprintf (stream, _("\n\
9301 The following i386/x86-64 specific disassembler options are supported for use\n\
9302 with the -M switch (multiple options should be separated by commas):\n"));
9303
9304   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
9305   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
9306   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
9307   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
9308   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
9309   fprintf (stream, _("  att-mnemonic\n"
9310                      "              Display instruction in AT&T mnemonic\n"));
9311   fprintf (stream, _("  intel-mnemonic\n"
9312                      "              Display instruction in Intel mnemonic\n"));
9313   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9314   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9315   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9316   fprintf (stream, _("  data32      Assume 32bit data size\n"));
9317   fprintf (stream, _("  data16      Assume 16bit data size\n"));
9318   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9319   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
9320   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
9321 }
9322
9323 /* Bad opcode.  */
9324 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
9325
9326 /* Get a pointer to struct dis386 with a valid name.  */
9327
9328 static const struct dis386 *
9329 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9330 {
9331   int vindex, vex_table_index;
9332
9333   if (dp->name != NULL)
9334     return dp;
9335
9336   switch (dp->op[0].bytemode)
9337     {
9338     case USE_REG_TABLE:
9339       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9340       break;
9341
9342     case USE_MOD_TABLE:
9343       vindex = modrm.mod == 0x3 ? 1 : 0;
9344       dp = &mod_table[dp->op[1].bytemode][vindex];
9345       break;
9346
9347     case USE_RM_TABLE:
9348       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9349       break;
9350
9351     case USE_PREFIX_TABLE:
9352       if (need_vex)
9353         {
9354           /* The prefix in VEX is implicit.  */
9355           switch (vex.prefix)
9356             {
9357             case 0:
9358               vindex = 0;
9359               break;
9360             case REPE_PREFIX_OPCODE:
9361               vindex = 1;
9362               break;
9363             case DATA_PREFIX_OPCODE:
9364               vindex = 2;
9365               break;
9366             case REPNE_PREFIX_OPCODE:
9367               vindex = 3;
9368               break;
9369             default:
9370               abort ();
9371               break;
9372             }
9373         }
9374       else
9375         {
9376           int last_prefix = -1;
9377           int prefix = 0;
9378           vindex = 0;
9379           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9380              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9381              last one wins.  */
9382           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9383             {
9384               if (last_repz_prefix > last_repnz_prefix)
9385                 {
9386                   vindex = 1;
9387                   prefix = PREFIX_REPZ;
9388                   last_prefix = last_repz_prefix;
9389                 }
9390               else
9391                 {
9392                   vindex = 3;
9393                   prefix = PREFIX_REPNZ;
9394                   last_prefix = last_repnz_prefix;
9395                 }
9396
9397               /* Check if prefix should be ignored.  */
9398               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9399                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9400                    & prefix) != 0)
9401                 vindex = 0;
9402             }
9403
9404           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
9405             {
9406               vindex = 2;
9407               prefix = PREFIX_DATA;
9408               last_prefix = last_data_prefix;
9409             }
9410
9411           if (vindex != 0)
9412             {
9413               used_prefixes |= prefix;
9414               all_prefixes[last_prefix] = 0;
9415             }
9416         }
9417       dp = &prefix_table[dp->op[1].bytemode][vindex];
9418       break;
9419
9420     case USE_X86_64_TABLE:
9421       vindex = address_mode == mode_64bit ? 1 : 0;
9422       dp = &x86_64_table[dp->op[1].bytemode][vindex];
9423       break;
9424
9425     case USE_3BYTE_TABLE:
9426       FETCH_DATA (info, codep + 2);
9427       vindex = *codep++;
9428       dp = &three_byte_table[dp->op[1].bytemode][vindex];
9429       end_codep = codep;
9430       modrm.mod = (*codep >> 6) & 3;
9431       modrm.reg = (*codep >> 3) & 7;
9432       modrm.rm = *codep & 7;
9433       break;
9434
9435     case USE_VEX_LEN_TABLE:
9436       if (!need_vex)
9437         abort ();
9438
9439       switch (vex.length)
9440         {
9441         case 128:
9442           vindex = 0;
9443           break;
9444         case 256:
9445           vindex = 1;
9446           break;
9447         default:
9448           abort ();
9449           break;
9450         }
9451
9452       dp = &vex_len_table[dp->op[1].bytemode][vindex];
9453       break;
9454
9455     case USE_EVEX_LEN_TABLE:
9456       if (!vex.evex)
9457         abort ();
9458
9459       switch (vex.length)
9460         {
9461         case 128:
9462           vindex = 0;
9463           break;
9464         case 256:
9465           vindex = 1;
9466           break;
9467         case 512:
9468           vindex = 2;
9469           break;
9470         default:
9471           abort ();
9472           break;
9473         }
9474
9475       dp = &evex_len_table[dp->op[1].bytemode][vindex];
9476       break;
9477
9478     case USE_XOP_8F_TABLE:
9479       FETCH_DATA (info, codep + 3);
9480       rex = ~(*codep >> 5) & 0x7;
9481
9482       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
9483       switch ((*codep & 0x1f))
9484         {
9485         default:
9486           dp = &bad_opcode;
9487           return dp;
9488         case 0x8:
9489           vex_table_index = XOP_08;
9490           break;
9491         case 0x9:
9492           vex_table_index = XOP_09;
9493           break;
9494         case 0xa:
9495           vex_table_index = XOP_0A;
9496           break;
9497         }
9498       codep++;
9499       vex.w = *codep & 0x80;
9500       if (vex.w && address_mode == mode_64bit)
9501         rex |= REX_W;
9502
9503       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9504       if (address_mode != mode_64bit)
9505         {
9506           /* In 16/32-bit mode REX_B is silently ignored.  */
9507           rex &= ~REX_B;
9508         }
9509
9510       vex.length = (*codep & 0x4) ? 256 : 128;
9511       switch ((*codep & 0x3))
9512         {
9513         case 0:
9514           break;
9515         case 1:
9516           vex.prefix = DATA_PREFIX_OPCODE;
9517           break;
9518         case 2:
9519           vex.prefix = REPE_PREFIX_OPCODE;
9520           break;
9521         case 3:
9522           vex.prefix = REPNE_PREFIX_OPCODE;
9523           break;
9524         }
9525       need_vex = 1;
9526       codep++;
9527       vindex = *codep++;
9528       dp = &xop_table[vex_table_index][vindex];
9529
9530       end_codep = codep;
9531       FETCH_DATA (info, codep + 1);
9532       modrm.mod = (*codep >> 6) & 3;
9533       modrm.reg = (*codep >> 3) & 7;
9534       modrm.rm = *codep & 7;
9535
9536       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9537          having to decode the bits for every otherwise valid encoding.  */
9538       if (vex.prefix)
9539         return &bad_opcode;
9540       break;
9541
9542     case USE_VEX_C4_TABLE:
9543       /* VEX prefix.  */
9544       FETCH_DATA (info, codep + 3);
9545       rex = ~(*codep >> 5) & 0x7;
9546       switch ((*codep & 0x1f))
9547         {
9548         default:
9549           dp = &bad_opcode;
9550           return dp;
9551         case 0x1:
9552           vex_table_index = VEX_0F;
9553           break;
9554         case 0x2:
9555           vex_table_index = VEX_0F38;
9556           break;
9557         case 0x3:
9558           vex_table_index = VEX_0F3A;
9559           break;
9560         }
9561       codep++;
9562       vex.w = *codep & 0x80;
9563       if (address_mode == mode_64bit)
9564         {
9565           if (vex.w)
9566             rex |= REX_W;
9567         }
9568       else
9569         {
9570           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9571              is ignored, other REX bits are 0 and the highest bit in
9572              VEX.vvvv is also ignored (but we mustn't clear it here).  */
9573           rex = 0;
9574         }
9575       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9576       vex.length = (*codep & 0x4) ? 256 : 128;
9577       switch ((*codep & 0x3))
9578         {
9579         case 0:
9580           break;
9581         case 1:
9582           vex.prefix = DATA_PREFIX_OPCODE;
9583           break;
9584         case 2:
9585           vex.prefix = REPE_PREFIX_OPCODE;
9586           break;
9587         case 3:
9588           vex.prefix = REPNE_PREFIX_OPCODE;
9589           break;
9590         }
9591       need_vex = 1;
9592       codep++;
9593       vindex = *codep++;
9594       dp = &vex_table[vex_table_index][vindex];
9595       end_codep = codep;
9596       /* There is no MODRM byte for VEX0F 77.  */
9597       if (vex_table_index != VEX_0F || vindex != 0x77)
9598         {
9599           FETCH_DATA (info, codep + 1);
9600           modrm.mod = (*codep >> 6) & 3;
9601           modrm.reg = (*codep >> 3) & 7;
9602           modrm.rm = *codep & 7;
9603         }
9604       break;
9605
9606     case USE_VEX_C5_TABLE:
9607       /* VEX prefix.  */
9608       FETCH_DATA (info, codep + 2);
9609       rex = (*codep & 0x80) ? 0 : REX_R;
9610
9611       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9612          VEX.vvvv is 1.  */
9613       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9614       vex.length = (*codep & 0x4) ? 256 : 128;
9615       switch ((*codep & 0x3))
9616         {
9617         case 0:
9618           break;
9619         case 1:
9620           vex.prefix = DATA_PREFIX_OPCODE;
9621           break;
9622         case 2:
9623           vex.prefix = REPE_PREFIX_OPCODE;
9624           break;
9625         case 3:
9626           vex.prefix = REPNE_PREFIX_OPCODE;
9627           break;
9628         }
9629       need_vex = 1;
9630       codep++;
9631       vindex = *codep++;
9632       dp = &vex_table[dp->op[1].bytemode][vindex];
9633       end_codep = codep;
9634       /* There is no MODRM byte for VEX 77.  */
9635       if (vindex != 0x77)
9636         {
9637           FETCH_DATA (info, codep + 1);
9638           modrm.mod = (*codep >> 6) & 3;
9639           modrm.reg = (*codep >> 3) & 7;
9640           modrm.rm = *codep & 7;
9641         }
9642       break;
9643
9644     case USE_VEX_W_TABLE:
9645       if (!need_vex)
9646         abort ();
9647
9648       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
9649       break;
9650
9651     case USE_EVEX_TABLE:
9652       two_source_ops = 0;
9653       /* EVEX prefix.  */
9654       vex.evex = 1;
9655       FETCH_DATA (info, codep + 4);
9656       /* The first byte after 0x62.  */
9657       rex = ~(*codep >> 5) & 0x7;
9658       vex.r = *codep & 0x10;
9659       switch ((*codep & 0xf))
9660         {
9661         default:
9662           return &bad_opcode;
9663         case 0x1:
9664           vex_table_index = EVEX_0F;
9665           break;
9666         case 0x2:
9667           vex_table_index = EVEX_0F38;
9668           break;
9669         case 0x3:
9670           vex_table_index = EVEX_0F3A;
9671           break;
9672         }
9673
9674       /* The second byte after 0x62.  */
9675       codep++;
9676       vex.w = *codep & 0x80;
9677       if (vex.w && address_mode == mode_64bit)
9678         rex |= REX_W;
9679
9680       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9681
9682       /* The U bit.  */
9683       if (!(*codep & 0x4))
9684         return &bad_opcode;
9685
9686       switch ((*codep & 0x3))
9687         {
9688         case 0:
9689           break;
9690         case 1:
9691           vex.prefix = DATA_PREFIX_OPCODE;
9692           break;
9693         case 2:
9694           vex.prefix = REPE_PREFIX_OPCODE;
9695           break;
9696         case 3:
9697           vex.prefix = REPNE_PREFIX_OPCODE;
9698           break;
9699         }
9700
9701       /* The third byte after 0x62.  */
9702       codep++;
9703
9704       /* Remember the static rounding bits.  */
9705       vex.ll = (*codep >> 5) & 3;
9706       vex.b = (*codep & 0x10) != 0;
9707
9708       vex.v = *codep & 0x8;
9709       vex.mask_register_specifier = *codep & 0x7;
9710       vex.zeroing = *codep & 0x80;
9711
9712       if (address_mode != mode_64bit)
9713         {
9714           /* In 16/32-bit mode silently ignore following bits.  */
9715           rex &= ~REX_B;
9716           vex.r = 1;
9717           vex.v = 1;
9718         }
9719
9720       need_vex = 1;
9721       codep++;
9722       vindex = *codep++;
9723       dp = &evex_table[vex_table_index][vindex];
9724       end_codep = codep;
9725       FETCH_DATA (info, codep + 1);
9726       modrm.mod = (*codep >> 6) & 3;
9727       modrm.reg = (*codep >> 3) & 7;
9728       modrm.rm = *codep & 7;
9729
9730       /* Set vector length.  */
9731       if (modrm.mod == 3 && vex.b)
9732         vex.length = 512;
9733       else
9734         {
9735           switch (vex.ll)
9736             {
9737             case 0x0:
9738               vex.length = 128;
9739               break;
9740             case 0x1:
9741               vex.length = 256;
9742               break;
9743             case 0x2:
9744               vex.length = 512;
9745               break;
9746             default:
9747               return &bad_opcode;
9748             }
9749         }
9750       break;
9751
9752     case 0:
9753       dp = &bad_opcode;
9754       break;
9755
9756     default:
9757       abort ();
9758     }
9759
9760   if (dp->name != NULL)
9761     return dp;
9762   else
9763     return get_valid_dis386 (dp, info);
9764 }
9765
9766 static void
9767 get_sib (disassemble_info *info, int sizeflag)
9768 {
9769   /* If modrm.mod == 3, operand must be register.  */
9770   if (need_modrm
9771       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
9772       && modrm.mod != 3
9773       && modrm.rm == 4)
9774     {
9775       FETCH_DATA (info, codep + 2);
9776       sib.index = (codep [1] >> 3) & 7;
9777       sib.scale = (codep [1] >> 6) & 3;
9778       sib.base = codep [1] & 7;
9779     }
9780 }
9781
9782 static int
9783 print_insn (bfd_vma pc, disassemble_info *info)
9784 {
9785   const struct dis386 *dp;
9786   int i;
9787   char *op_txt[MAX_OPERANDS];
9788   int needcomma;
9789   int sizeflag, orig_sizeflag;
9790   const char *p;
9791   struct dis_private priv;
9792   int prefix_length;
9793
9794   priv.orig_sizeflag = AFLAG | DFLAG;
9795   if ((info->mach & bfd_mach_i386_i386) != 0)
9796     address_mode = mode_32bit;
9797   else if (info->mach == bfd_mach_i386_i8086)
9798     {
9799       address_mode = mode_16bit;
9800       priv.orig_sizeflag = 0;
9801     }
9802   else
9803     address_mode = mode_64bit;
9804
9805   if (intel_syntax == (char) -1)
9806     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
9807
9808   for (p = info->disassembler_options; p != NULL; )
9809     {
9810       if (CONST_STRNEQ (p, "amd64"))
9811         isa64 = amd64;
9812       else if (CONST_STRNEQ (p, "intel64"))
9813         isa64 = intel64;
9814       else if (CONST_STRNEQ (p, "x86-64"))
9815         {
9816           address_mode = mode_64bit;
9817           priv.orig_sizeflag |= AFLAG | DFLAG;
9818         }
9819       else if (CONST_STRNEQ (p, "i386"))
9820         {
9821           address_mode = mode_32bit;
9822           priv.orig_sizeflag |= AFLAG | DFLAG;
9823         }
9824       else if (CONST_STRNEQ (p, "i8086"))
9825         {
9826           address_mode = mode_16bit;
9827           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9828         }
9829       else if (CONST_STRNEQ (p, "intel"))
9830         {
9831           intel_syntax = 1;
9832           if (CONST_STRNEQ (p + 5, "-mnemonic"))
9833             intel_mnemonic = 1;
9834         }
9835       else if (CONST_STRNEQ (p, "att"))
9836         {
9837           intel_syntax = 0;
9838           if (CONST_STRNEQ (p + 3, "-mnemonic"))
9839             intel_mnemonic = 0;
9840         }
9841       else if (CONST_STRNEQ (p, "addr"))
9842         {
9843           if (address_mode == mode_64bit)
9844             {
9845               if (p[4] == '3' && p[5] == '2')
9846                 priv.orig_sizeflag &= ~AFLAG;
9847               else if (p[4] == '6' && p[5] == '4')
9848                 priv.orig_sizeflag |= AFLAG;
9849             }
9850           else
9851             {
9852               if (p[4] == '1' && p[5] == '6')
9853                 priv.orig_sizeflag &= ~AFLAG;
9854               else if (p[4] == '3' && p[5] == '2')
9855                 priv.orig_sizeflag |= AFLAG;
9856             }
9857         }
9858       else if (CONST_STRNEQ (p, "data"))
9859         {
9860           if (p[4] == '1' && p[5] == '6')
9861             priv.orig_sizeflag &= ~DFLAG;
9862           else if (p[4] == '3' && p[5] == '2')
9863             priv.orig_sizeflag |= DFLAG;
9864         }
9865       else if (CONST_STRNEQ (p, "suffix"))
9866         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9867
9868       p = strchr (p, ',');
9869       if (p != NULL)
9870         p++;
9871     }
9872
9873   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9874     {
9875       (*info->fprintf_func) (info->stream,
9876                              _("64-bit address is disabled"));
9877       return -1;
9878     }
9879
9880   if (intel_syntax)
9881     {
9882       names64 = intel_names64;
9883       names32 = intel_names32;
9884       names16 = intel_names16;
9885       names8 = intel_names8;
9886       names8rex = intel_names8rex;
9887       names_seg = intel_names_seg;
9888       names_mm = intel_names_mm;
9889       names_bnd = intel_names_bnd;
9890       names_xmm = intel_names_xmm;
9891       names_ymm = intel_names_ymm;
9892       names_zmm = intel_names_zmm;
9893       names_tmm = intel_names_tmm;
9894       index64 = intel_index64;
9895       index32 = intel_index32;
9896       names_mask = intel_names_mask;
9897       index16 = intel_index16;
9898       open_char = '[';
9899       close_char = ']';
9900       separator_char = '+';
9901       scale_char = '*';
9902     }
9903   else
9904     {
9905       names64 = att_names64;
9906       names32 = att_names32;
9907       names16 = att_names16;
9908       names8 = att_names8;
9909       names8rex = att_names8rex;
9910       names_seg = att_names_seg;
9911       names_mm = att_names_mm;
9912       names_bnd = att_names_bnd;
9913       names_xmm = att_names_xmm;
9914       names_ymm = att_names_ymm;
9915       names_zmm = att_names_zmm;
9916       names_tmm = att_names_tmm;
9917       index64 = att_index64;
9918       index32 = att_index32;
9919       names_mask = att_names_mask;
9920       index16 = att_index16;
9921       open_char = '(';
9922       close_char =  ')';
9923       separator_char = ',';
9924       scale_char = ',';
9925     }
9926
9927   /* The output looks better if we put 7 bytes on a line, since that
9928      puts most long word instructions on a single line.  Use 8 bytes
9929      for Intel L1OM.  */
9930   if ((info->mach & bfd_mach_l1om) != 0)
9931     info->bytes_per_line = 8;
9932   else
9933     info->bytes_per_line = 7;
9934
9935   info->private_data = &priv;
9936   priv.max_fetched = priv.the_buffer;
9937   priv.insn_start = pc;
9938
9939   obuf[0] = 0;
9940   for (i = 0; i < MAX_OPERANDS; ++i)
9941     {
9942       op_out[i][0] = 0;
9943       op_index[i] = -1;
9944     }
9945
9946   the_info = info;
9947   start_pc = pc;
9948   start_codep = priv.the_buffer;
9949   codep = priv.the_buffer;
9950
9951   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9952     {
9953       const char *name;
9954
9955       /* Getting here means we tried for data but didn't get it.  That
9956          means we have an incomplete instruction of some sort.  Just
9957          print the first byte as a prefix or a .byte pseudo-op.  */
9958       if (codep > priv.the_buffer)
9959         {
9960           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9961           if (name != NULL)
9962             (*info->fprintf_func) (info->stream, "%s", name);
9963           else
9964             {
9965               /* Just print the first byte as a .byte instruction.  */
9966               (*info->fprintf_func) (info->stream, ".byte 0x%x",
9967                                      (unsigned int) priv.the_buffer[0]);
9968             }
9969
9970           return 1;
9971         }
9972
9973       return -1;
9974     }
9975
9976   obufp = obuf;
9977   sizeflag = priv.orig_sizeflag;
9978
9979   if (!ckprefix () || rex_used)
9980     {
9981       /* Too many prefixes or unused REX prefixes.  */
9982       for (i = 0;
9983            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
9984            i++)
9985         (*info->fprintf_func) (info->stream, "%s%s",
9986                                i == 0 ? "" : " ",
9987                                prefix_name (all_prefixes[i], sizeflag));
9988       return i;
9989     }
9990
9991   insn_codep = codep;
9992
9993   FETCH_DATA (info, codep + 1);
9994   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9995
9996   if (((prefixes & PREFIX_FWAIT)
9997        && ((*codep < 0xd8) || (*codep > 0xdf))))
9998     {
9999       /* Handle prefixes before fwait.  */
10000       for (i = 0; i < fwait_prefix && all_prefixes[i];
10001            i++)
10002         (*info->fprintf_func) (info->stream, "%s ",
10003                                prefix_name (all_prefixes[i], sizeflag));
10004       (*info->fprintf_func) (info->stream, "fwait");
10005       return i + 1;
10006     }
10007
10008   if (*codep == 0x0f)
10009     {
10010       unsigned char threebyte;
10011
10012       codep++;
10013       FETCH_DATA (info, codep + 1);
10014       threebyte = *codep;
10015       dp = &dis386_twobyte[threebyte];
10016       need_modrm = twobyte_has_modrm[threebyte];
10017       codep++;
10018     }
10019   else
10020     {
10021       dp = &dis386[*codep];
10022       need_modrm = onebyte_has_modrm[*codep];
10023       codep++;
10024     }
10025
10026   /* Save sizeflag for printing the extra prefixes later before updating
10027      it for mnemonic and operand processing.  The prefix names depend
10028      only on the address mode.  */
10029   orig_sizeflag = sizeflag;
10030   if (prefixes & PREFIX_ADDR)
10031     sizeflag ^= AFLAG;
10032   if ((prefixes & PREFIX_DATA))
10033     sizeflag ^= DFLAG;
10034
10035   end_codep = codep;
10036   if (need_modrm)
10037     {
10038       FETCH_DATA (info, codep + 1);
10039       modrm.mod = (*codep >> 6) & 3;
10040       modrm.reg = (*codep >> 3) & 7;
10041       modrm.rm = *codep & 7;
10042     }
10043   else
10044     memset (&modrm, 0, sizeof (modrm));
10045
10046   need_vex = 0;
10047   memset (&vex, 0, sizeof (vex));
10048
10049   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
10050     {
10051       get_sib (info, sizeflag);
10052       dofloat (sizeflag);
10053     }
10054   else
10055     {
10056       dp = get_valid_dis386 (dp, info);
10057       if (dp != NULL && putop (dp->name, sizeflag) == 0)
10058         {
10059           get_sib (info, sizeflag);
10060           for (i = 0; i < MAX_OPERANDS; ++i)
10061             {
10062               obufp = op_out[i];
10063               op_ad = MAX_OPERANDS - 1 - i;
10064               if (dp->op[i].rtn)
10065                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10066               /* For EVEX instruction after the last operand masking
10067                  should be printed.  */
10068               if (i == 0 && vex.evex)
10069                 {
10070                   /* Don't print {%k0}.  */
10071                   if (vex.mask_register_specifier)
10072                     {
10073                       oappend ("{");
10074                       oappend (names_mask[vex.mask_register_specifier]);
10075                       oappend ("}");
10076                     }
10077                   if (vex.zeroing)
10078                     oappend ("{z}");
10079                 }
10080             }
10081         }
10082     }
10083
10084   /* Clear instruction information.  */
10085   if (the_info)
10086     {
10087       the_info->insn_info_valid = 0;
10088       the_info->branch_delay_insns = 0;
10089       the_info->data_size = 0;
10090       the_info->insn_type = dis_noninsn;
10091       the_info->target = 0;
10092       the_info->target2 = 0;
10093     }
10094
10095   /* Reset jump operation indicator.  */
10096   op_is_jump = FALSE;
10097
10098   {
10099     int jump_detection = 0;
10100
10101     /* Extract flags.  */
10102     for (i = 0; i < MAX_OPERANDS; ++i)
10103       {
10104         if ((dp->op[i].rtn == OP_J)
10105             || (dp->op[i].rtn == OP_indirE))
10106           jump_detection |= 1;
10107         else if ((dp->op[i].rtn == BND_Fixup)
10108                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
10109           jump_detection |= 2;
10110         else if ((dp->op[i].bytemode == cond_jump_mode)
10111                  || (dp->op[i].bytemode == loop_jcxz_mode))
10112           jump_detection |= 4;
10113       }
10114
10115     /* Determine if this is a jump or branch.  */
10116     if ((jump_detection & 0x3) == 0x3)
10117       {
10118         op_is_jump = TRUE;
10119         if (jump_detection & 0x4)
10120           the_info->insn_type = dis_condbranch;
10121         else
10122           the_info->insn_type =
10123             (dp->name && !strncmp(dp->name, "call", 4))
10124             ? dis_jsr : dis_branch;
10125       }
10126   }
10127
10128   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
10129      are all 0s in inverted form.  */
10130   if (need_vex && vex.register_specifier != 0)
10131     {
10132       (*info->fprintf_func) (info->stream, "(bad)");
10133       return end_codep - priv.the_buffer;
10134     }
10135
10136   switch (dp->prefix_requirement)
10137     {
10138     case PREFIX_DATA:
10139       /* If only the data prefix is marked as mandatory, its absence renders
10140          the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
10141       if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA))
10142         {
10143           (*info->fprintf_func) (info->stream, "(bad)");
10144           return end_codep - priv.the_buffer;
10145         }
10146       used_prefixes |= PREFIX_DATA;
10147       /* Fall through.  */
10148     case PREFIX_OPCODE:
10149       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
10150          unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
10151          used by putop and MMX/SSE operand and may be overridden by the
10152          PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
10153          separately.  */
10154       if (((need_vex
10155             ? vex.prefix == REPE_PREFIX_OPCODE
10156               || vex.prefix == REPNE_PREFIX_OPCODE
10157             : (prefixes
10158                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
10159            && (used_prefixes
10160                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
10161           || (((need_vex
10162                 ? vex.prefix == DATA_PREFIX_OPCODE
10163                 : ((prefixes
10164                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
10165                    == PREFIX_DATA))
10166                && (used_prefixes & PREFIX_DATA) == 0))
10167           || (vex.evex && dp->prefix_requirement != PREFIX_DATA
10168               && !vex.w != !(used_prefixes & PREFIX_DATA)))
10169         {
10170           (*info->fprintf_func) (info->stream, "(bad)");
10171           return end_codep - priv.the_buffer;
10172         }
10173       break;
10174     }
10175
10176   /* Check if the REX prefix is used.  */
10177   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
10178     all_prefixes[last_rex_prefix] = 0;
10179
10180   /* Check if the SEG prefix is used.  */
10181   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
10182                    | PREFIX_FS | PREFIX_GS)) != 0
10183       && (used_prefixes & active_seg_prefix) != 0)
10184     all_prefixes[last_seg_prefix] = 0;
10185
10186   /* Check if the ADDR prefix is used.  */
10187   if ((prefixes & PREFIX_ADDR) != 0
10188       && (used_prefixes & PREFIX_ADDR) != 0)
10189     all_prefixes[last_addr_prefix] = 0;
10190
10191   /* Check if the DATA prefix is used.  */
10192   if ((prefixes & PREFIX_DATA) != 0
10193       && (used_prefixes & PREFIX_DATA) != 0
10194       && !need_vex)
10195     all_prefixes[last_data_prefix] = 0;
10196
10197   /* Print the extra prefixes.  */
10198   prefix_length = 0;
10199   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10200     if (all_prefixes[i])
10201       {
10202         const char *name;
10203         name = prefix_name (all_prefixes[i], orig_sizeflag);
10204         if (name == NULL)
10205           abort ();
10206         prefix_length += strlen (name) + 1;
10207         (*info->fprintf_func) (info->stream, "%s ", name);
10208       }
10209
10210   /* Check maximum code length.  */
10211   if ((codep - start_codep) > MAX_CODE_LENGTH)
10212     {
10213       (*info->fprintf_func) (info->stream, "(bad)");
10214       return MAX_CODE_LENGTH;
10215     }
10216
10217   obufp = mnemonicendp;
10218   for (i = strlen (obuf) + prefix_length; i < 6; i++)
10219     oappend (" ");
10220   oappend (" ");
10221   (*info->fprintf_func) (info->stream, "%s", obuf);
10222
10223   /* The enter and bound instructions are printed with operands in the same
10224      order as the intel book; everything else is printed in reverse order.  */
10225   if (intel_syntax || two_source_ops)
10226     {
10227       bfd_vma riprel;
10228
10229       for (i = 0; i < MAX_OPERANDS; ++i)
10230         op_txt[i] = op_out[i];
10231
10232       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
10233           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
10234         {
10235           op_txt[2] = op_out[3];
10236           op_txt[3] = op_out[2];
10237         }
10238
10239       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10240         {
10241           op_ad = op_index[i];
10242           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10243           op_index[MAX_OPERANDS - 1 - i] = op_ad;
10244           riprel = op_riprel[i];
10245           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10246           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10247         }
10248     }
10249   else
10250     {
10251       for (i = 0; i < MAX_OPERANDS; ++i)
10252         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10253     }
10254
10255   needcomma = 0;
10256   for (i = 0; i < MAX_OPERANDS; ++i)
10257     if (*op_txt[i])
10258       {
10259         if (needcomma)
10260           (*info->fprintf_func) (info->stream, ",");
10261         if (op_index[i] != -1 && !op_riprel[i])
10262           {
10263             bfd_vma target = (bfd_vma) op_address[op_index[i]];
10264
10265             if (the_info && op_is_jump)
10266               {
10267                 the_info->insn_info_valid = 1;
10268                 the_info->branch_delay_insns = 0;
10269                 the_info->data_size = 0;
10270                 the_info->target = target;
10271                 the_info->target2 = 0;
10272               }
10273             (*info->print_address_func) (target, info);
10274           }
10275         else
10276           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10277         needcomma = 1;
10278       }
10279
10280   for (i = 0; i < MAX_OPERANDS; i++)
10281     if (op_index[i] != -1 && op_riprel[i])
10282       {
10283         (*info->fprintf_func) (info->stream, "        # ");
10284         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
10285                                                 + op_address[op_index[i]]), info);
10286         break;
10287       }
10288   return codep - priv.the_buffer;
10289 }
10290
10291 static const char *float_mem[] = {
10292   /* d8 */
10293   "fadd{s|}",
10294   "fmul{s|}",
10295   "fcom{s|}",
10296   "fcomp{s|}",
10297   "fsub{s|}",
10298   "fsubr{s|}",
10299   "fdiv{s|}",
10300   "fdivr{s|}",
10301   /* d9 */
10302   "fld{s|}",
10303   "(bad)",
10304   "fst{s|}",
10305   "fstp{s|}",
10306   "fldenv{C|C}",
10307   "fldcw",
10308   "fNstenv{C|C}",
10309   "fNstcw",
10310   /* da */
10311   "fiadd{l|}",
10312   "fimul{l|}",
10313   "ficom{l|}",
10314   "ficomp{l|}",
10315   "fisub{l|}",
10316   "fisubr{l|}",
10317   "fidiv{l|}",
10318   "fidivr{l|}",
10319   /* db */
10320   "fild{l|}",
10321   "fisttp{l|}",
10322   "fist{l|}",
10323   "fistp{l|}",
10324   "(bad)",
10325   "fld{t|}",
10326   "(bad)",
10327   "fstp{t|}",
10328   /* dc */
10329   "fadd{l|}",
10330   "fmul{l|}",
10331   "fcom{l|}",
10332   "fcomp{l|}",
10333   "fsub{l|}",
10334   "fsubr{l|}",
10335   "fdiv{l|}",
10336   "fdivr{l|}",
10337   /* dd */
10338   "fld{l|}",
10339   "fisttp{ll|}",
10340   "fst{l||}",
10341   "fstp{l|}",
10342   "frstor{C|C}",
10343   "(bad)",
10344   "fNsave{C|C}",
10345   "fNstsw",
10346   /* de */
10347   "fiadd{s|}",
10348   "fimul{s|}",
10349   "ficom{s|}",
10350   "ficomp{s|}",
10351   "fisub{s|}",
10352   "fisubr{s|}",
10353   "fidiv{s|}",
10354   "fidivr{s|}",
10355   /* df */
10356   "fild{s|}",
10357   "fisttp{s|}",
10358   "fist{s|}",
10359   "fistp{s|}",
10360   "fbld",
10361   "fild{ll|}",
10362   "fbstp",
10363   "fistp{ll|}",
10364 };
10365
10366 static const unsigned char float_mem_mode[] = {
10367   /* d8 */
10368   d_mode,
10369   d_mode,
10370   d_mode,
10371   d_mode,
10372   d_mode,
10373   d_mode,
10374   d_mode,
10375   d_mode,
10376   /* d9 */
10377   d_mode,
10378   0,
10379   d_mode,
10380   d_mode,
10381   0,
10382   w_mode,
10383   0,
10384   w_mode,
10385   /* da */
10386   d_mode,
10387   d_mode,
10388   d_mode,
10389   d_mode,
10390   d_mode,
10391   d_mode,
10392   d_mode,
10393   d_mode,
10394   /* db */
10395   d_mode,
10396   d_mode,
10397   d_mode,
10398   d_mode,
10399   0,
10400   t_mode,
10401   0,
10402   t_mode,
10403   /* dc */
10404   q_mode,
10405   q_mode,
10406   q_mode,
10407   q_mode,
10408   q_mode,
10409   q_mode,
10410   q_mode,
10411   q_mode,
10412   /* dd */
10413   q_mode,
10414   q_mode,
10415   q_mode,
10416   q_mode,
10417   0,
10418   0,
10419   0,
10420   w_mode,
10421   /* de */
10422   w_mode,
10423   w_mode,
10424   w_mode,
10425   w_mode,
10426   w_mode,
10427   w_mode,
10428   w_mode,
10429   w_mode,
10430   /* df */
10431   w_mode,
10432   w_mode,
10433   w_mode,
10434   w_mode,
10435   t_mode,
10436   q_mode,
10437   t_mode,
10438   q_mode
10439 };
10440
10441 #define ST { OP_ST, 0 }
10442 #define STi { OP_STi, 0 }
10443
10444 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10445 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10446 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10447 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10448 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10449 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10450 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10451 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10452 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10453
10454 static const struct dis386 float_reg[][8] = {
10455   /* d8 */
10456   {
10457     { "fadd",   { ST, STi }, 0 },
10458     { "fmul",   { ST, STi }, 0 },
10459     { "fcom",   { STi }, 0 },
10460     { "fcomp",  { STi }, 0 },
10461     { "fsub",   { ST, STi }, 0 },
10462     { "fsubr",  { ST, STi }, 0 },
10463     { "fdiv",   { ST, STi }, 0 },
10464     { "fdivr",  { ST, STi }, 0 },
10465   },
10466   /* d9 */
10467   {
10468     { "fld",    { STi }, 0 },
10469     { "fxch",   { STi }, 0 },
10470     { FGRPd9_2 },
10471     { Bad_Opcode },
10472     { FGRPd9_4 },
10473     { FGRPd9_5 },
10474     { FGRPd9_6 },
10475     { FGRPd9_7 },
10476   },
10477   /* da */
10478   {
10479     { "fcmovb", { ST, STi }, 0 },
10480     { "fcmove", { ST, STi }, 0 },
10481     { "fcmovbe",{ ST, STi }, 0 },
10482     { "fcmovu", { ST, STi }, 0 },
10483     { Bad_Opcode },
10484     { FGRPda_5 },
10485     { Bad_Opcode },
10486     { Bad_Opcode },
10487   },
10488   /* db */
10489   {
10490     { "fcmovnb",{ ST, STi }, 0 },
10491     { "fcmovne",{ ST, STi }, 0 },
10492     { "fcmovnbe",{ ST, STi }, 0 },
10493     { "fcmovnu",{ ST, STi }, 0 },
10494     { FGRPdb_4 },
10495     { "fucomi", { ST, STi }, 0 },
10496     { "fcomi",  { ST, STi }, 0 },
10497     { Bad_Opcode },
10498   },
10499   /* dc */
10500   {
10501     { "fadd",   { STi, ST }, 0 },
10502     { "fmul",   { STi, ST }, 0 },
10503     { Bad_Opcode },
10504     { Bad_Opcode },
10505     { "fsub{!M|r}",     { STi, ST }, 0 },
10506     { "fsub{M|}",       { STi, ST }, 0 },
10507     { "fdiv{!M|r}",     { STi, ST }, 0 },
10508     { "fdiv{M|}",       { STi, ST }, 0 },
10509   },
10510   /* dd */
10511   {
10512     { "ffree",  { STi }, 0 },
10513     { Bad_Opcode },
10514     { "fst",    { STi }, 0 },
10515     { "fstp",   { STi }, 0 },
10516     { "fucom",  { STi }, 0 },
10517     { "fucomp", { STi }, 0 },
10518     { Bad_Opcode },
10519     { Bad_Opcode },
10520   },
10521   /* de */
10522   {
10523     { "faddp",  { STi, ST }, 0 },
10524     { "fmulp",  { STi, ST }, 0 },
10525     { Bad_Opcode },
10526     { FGRPde_3 },
10527     { "fsub{!M|r}p",    { STi, ST }, 0 },
10528     { "fsub{M|}p",      { STi, ST }, 0 },
10529     { "fdiv{!M|r}p",    { STi, ST }, 0 },
10530     { "fdiv{M|}p",      { STi, ST }, 0 },
10531   },
10532   /* df */
10533   {
10534     { "ffreep", { STi }, 0 },
10535     { Bad_Opcode },
10536     { Bad_Opcode },
10537     { Bad_Opcode },
10538     { FGRPdf_4 },
10539     { "fucomip", { ST, STi }, 0 },
10540     { "fcomip", { ST, STi }, 0 },
10541     { Bad_Opcode },
10542   },
10543 };
10544
10545 static char *fgrps[][8] = {
10546   /* Bad opcode 0 */
10547   {
10548     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10549   },
10550
10551   /* d9_2  1 */
10552   {
10553     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10554   },
10555
10556   /* d9_4  2 */
10557   {
10558     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10559   },
10560
10561   /* d9_5  3 */
10562   {
10563     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10564   },
10565
10566   /* d9_6  4 */
10567   {
10568     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10569   },
10570
10571   /* d9_7  5 */
10572   {
10573     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10574   },
10575
10576   /* da_5  6 */
10577   {
10578     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10579   },
10580
10581   /* db_4  7 */
10582   {
10583     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10584     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10585   },
10586
10587   /* de_3  8 */
10588   {
10589     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10590   },
10591
10592   /* df_4  9 */
10593   {
10594     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10595   },
10596 };
10597
10598 static void
10599 swap_operand (void)
10600 {
10601   mnemonicendp[0] = '.';
10602   mnemonicendp[1] = 's';
10603   mnemonicendp += 2;
10604 }
10605
10606 static void
10607 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10608                int sizeflag ATTRIBUTE_UNUSED)
10609 {
10610   /* Skip mod/rm byte.  */
10611   MODRM_CHECK;
10612   codep++;
10613 }
10614
10615 static void
10616 dofloat (int sizeflag)
10617 {
10618   const struct dis386 *dp;
10619   unsigned char floatop;
10620
10621   floatop = codep[-1];
10622
10623   if (modrm.mod != 3)
10624     {
10625       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10626
10627       putop (float_mem[fp_indx], sizeflag);
10628       obufp = op_out[0];
10629       op_ad = 2;
10630       OP_E (float_mem_mode[fp_indx], sizeflag);
10631       return;
10632     }
10633   /* Skip mod/rm byte.  */
10634   MODRM_CHECK;
10635   codep++;
10636
10637   dp = &float_reg[floatop - 0xd8][modrm.reg];
10638   if (dp->name == NULL)
10639     {
10640       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10641
10642       /* Instruction fnstsw is only one with strange arg.  */
10643       if (floatop == 0xdf && codep[-1] == 0xe0)
10644         strcpy (op_out[0], names16[0]);
10645     }
10646   else
10647     {
10648       putop (dp->name, sizeflag);
10649
10650       obufp = op_out[0];
10651       op_ad = 2;
10652       if (dp->op[0].rtn)
10653         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10654
10655       obufp = op_out[1];
10656       op_ad = 1;
10657       if (dp->op[1].rtn)
10658         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10659     }
10660 }
10661
10662 /* Like oappend (below), but S is a string starting with '%'.
10663    In Intel syntax, the '%' is elided.  */
10664 static void
10665 oappend_maybe_intel (const char *s)
10666 {
10667   oappend (s + intel_syntax);
10668 }
10669
10670 static void
10671 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10672 {
10673   oappend_maybe_intel ("%st");
10674 }
10675
10676 static void
10677 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10678 {
10679   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10680   oappend_maybe_intel (scratchbuf);
10681 }
10682
10683 /* Capital letters in template are macros.  */
10684 static int
10685 putop (const char *in_template, int sizeflag)
10686 {
10687   const char *p;
10688   int alt = 0;
10689   int cond = 1;
10690   unsigned int l = 0, len = 0;
10691   char last[4];
10692
10693   for (p = in_template; *p; p++)
10694     {
10695       if (len > l)
10696         {
10697           if (l >= sizeof (last) || !ISUPPER (*p))
10698             abort ();
10699           last[l++] = *p;
10700           continue;
10701         }
10702       switch (*p)
10703         {
10704         default:
10705           *obufp++ = *p;
10706           break;
10707         case '%':
10708           len++;
10709           break;
10710         case '!':
10711           cond = 0;
10712           break;
10713         case '{':
10714           if (intel_syntax)
10715             {
10716               while (*++p != '|')
10717                 if (*p == '}' || *p == '\0')
10718                   abort ();
10719               alt = 1;
10720             }
10721           break;
10722         case '|':
10723           while (*++p != '}')
10724             {
10725               if (*p == '\0')
10726                 abort ();
10727             }
10728           break;
10729         case '}':
10730           alt = 0;
10731           break;
10732         case 'A':
10733           if (intel_syntax)
10734             break;
10735           if ((need_modrm && modrm.mod != 3)
10736               || (sizeflag & SUFFIX_ALWAYS))
10737             *obufp++ = 'b';
10738           break;
10739         case 'B':
10740           if (l == 0)
10741             {
10742             case_B:
10743               if (intel_syntax)
10744                 break;
10745               if (sizeflag & SUFFIX_ALWAYS)
10746                 *obufp++ = 'b';
10747             }
10748           else if (l == 1 && last[0] == 'L')
10749             {
10750               if (address_mode == mode_64bit
10751                   && !(prefixes & PREFIX_ADDR))
10752                 {
10753                   *obufp++ = 'a';
10754                   *obufp++ = 'b';
10755                   *obufp++ = 's';
10756                 }
10757
10758               goto case_B;
10759             }
10760           else
10761             abort ();
10762           break;
10763         case 'C':
10764           if (intel_syntax && !alt)
10765             break;
10766           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10767             {
10768               if (sizeflag & DFLAG)
10769                 *obufp++ = intel_syntax ? 'd' : 'l';
10770               else
10771                 *obufp++ = intel_syntax ? 'w' : 's';
10772               used_prefixes |= (prefixes & PREFIX_DATA);
10773             }
10774           break;
10775         case 'D':
10776           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10777             break;
10778           USED_REX (REX_W);
10779           if (modrm.mod == 3)
10780             {
10781               if (rex & REX_W)
10782                 *obufp++ = 'q';
10783               else
10784                 {
10785                   if (sizeflag & DFLAG)
10786                     *obufp++ = intel_syntax ? 'd' : 'l';
10787                   else
10788                     *obufp++ = 'w';
10789                   used_prefixes |= (prefixes & PREFIX_DATA);
10790                 }
10791             }
10792           else
10793             *obufp++ = 'w';
10794           break;
10795         case 'E':               /* For jcxz/jecxz */
10796           if (address_mode == mode_64bit)
10797             {
10798               if (sizeflag & AFLAG)
10799                 *obufp++ = 'r';
10800               else
10801                 *obufp++ = 'e';
10802             }
10803           else
10804             if (sizeflag & AFLAG)
10805               *obufp++ = 'e';
10806           used_prefixes |= (prefixes & PREFIX_ADDR);
10807           break;
10808         case 'F':
10809           if (intel_syntax)
10810             break;
10811           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10812             {
10813               if (sizeflag & AFLAG)
10814                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10815               else
10816                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10817               used_prefixes |= (prefixes & PREFIX_ADDR);
10818             }
10819           break;
10820         case 'G':
10821           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10822             break;
10823           if ((rex & REX_W) || (sizeflag & DFLAG))
10824             *obufp++ = 'l';
10825           else
10826             *obufp++ = 'w';
10827           if (!(rex & REX_W))
10828             used_prefixes |= (prefixes & PREFIX_DATA);
10829           break;
10830         case 'H':
10831           if (intel_syntax)
10832             break;
10833           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10834               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10835             {
10836               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10837               *obufp++ = ',';
10838               *obufp++ = 'p';
10839               if (prefixes & PREFIX_DS)
10840                 *obufp++ = 't';
10841               else
10842                 *obufp++ = 'n';
10843             }
10844           break;
10845         case 'K':
10846           USED_REX (REX_W);
10847           if (rex & REX_W)
10848             *obufp++ = 'q';
10849           else
10850             *obufp++ = 'd';
10851           break;
10852         case 'L':
10853           abort ();
10854         case 'M':
10855           if (intel_mnemonic != cond)
10856             *obufp++ = 'r';
10857           break;
10858         case 'N':
10859           if ((prefixes & PREFIX_FWAIT) == 0)
10860             *obufp++ = 'n';
10861           else
10862             used_prefixes |= PREFIX_FWAIT;
10863           break;
10864         case 'O':
10865           USED_REX (REX_W);
10866           if (rex & REX_W)
10867             *obufp++ = 'o';
10868           else if (intel_syntax && (sizeflag & DFLAG))
10869             *obufp++ = 'q';
10870           else
10871             *obufp++ = 'd';
10872           if (!(rex & REX_W))
10873             used_prefixes |= (prefixes & PREFIX_DATA);
10874           break;
10875         case '@':
10876           if (address_mode == mode_64bit
10877               && (isa64 == intel64 || (rex & REX_W)
10878                   || !(prefixes & PREFIX_DATA)))
10879             {
10880               if (sizeflag & SUFFIX_ALWAYS)
10881                 *obufp++ = 'q';
10882               break;
10883             }
10884           /* Fall through.  */
10885         case 'P':
10886           if (l == 0)
10887             {
10888               if ((modrm.mod == 3 || !cond)
10889                   && !(sizeflag & SUFFIX_ALWAYS))
10890                 break;
10891           /* Fall through.  */
10892         case 'T':
10893               if ((!(rex & REX_W) && (prefixes & PREFIX_DATA))
10894                   || ((sizeflag & SUFFIX_ALWAYS)
10895                       && address_mode != mode_64bit))
10896                 {
10897                   *obufp++ = (sizeflag & DFLAG) ?
10898                              intel_syntax ? 'd' : 'l' : 'w';
10899                   used_prefixes |= (prefixes & PREFIX_DATA);
10900                 }
10901               else if (sizeflag & SUFFIX_ALWAYS)
10902                 *obufp++ = 'q';
10903             }
10904           else if (l == 1 && last[0] == 'L')
10905             {
10906               if ((prefixes & PREFIX_DATA)
10907                   || (rex & REX_W)
10908                   || (sizeflag & SUFFIX_ALWAYS))
10909                 {
10910                   USED_REX (REX_W);
10911                   if (rex & REX_W)
10912                     *obufp++ = 'q';
10913                   else
10914                     {
10915                       if (sizeflag & DFLAG)
10916                         *obufp++ = intel_syntax ? 'd' : 'l';
10917                       else
10918                         *obufp++ = 'w';
10919                       used_prefixes |= (prefixes & PREFIX_DATA);
10920                     }
10921                 }
10922             }
10923           else
10924             abort ();
10925           break;
10926         case 'Q':
10927           if (l == 0)
10928             {
10929               if (intel_syntax && !alt)
10930                 break;
10931               USED_REX (REX_W);
10932               if ((need_modrm && modrm.mod != 3)
10933                   || (sizeflag & SUFFIX_ALWAYS))
10934                 {
10935                   if (rex & REX_W)
10936                     *obufp++ = 'q';
10937                   else
10938                     {
10939                       if (sizeflag & DFLAG)
10940                         *obufp++ = intel_syntax ? 'd' : 'l';
10941                       else
10942                         *obufp++ = 'w';
10943                       used_prefixes |= (prefixes & PREFIX_DATA);
10944                     }
10945                 }
10946             }
10947           else if (l == 1 && last[0] == 'D')
10948             *obufp++ = vex.w ? 'q' : 'd';
10949           else if (l == 1 && last[0] == 'L')
10950             {
10951               if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10952                        : address_mode != mode_64bit)
10953                 break;
10954               if ((rex & REX_W))
10955                 {
10956                   USED_REX (REX_W);
10957                   *obufp++ = 'q';
10958                 }
10959               else if((address_mode == mode_64bit && cond)
10960                       || (sizeflag & SUFFIX_ALWAYS))
10961                 *obufp++ = intel_syntax? 'd' : 'l';
10962             }
10963           else
10964             abort ();
10965           break;
10966         case 'R':
10967           USED_REX (REX_W);
10968           if (rex & REX_W)
10969             *obufp++ = 'q';
10970           else if (sizeflag & DFLAG)
10971             {
10972               if (intel_syntax)
10973                   *obufp++ = 'd';
10974               else
10975                   *obufp++ = 'l';
10976             }
10977           else
10978             *obufp++ = 'w';
10979           if (intel_syntax && !p[1]
10980               && ((rex & REX_W) || (sizeflag & DFLAG)))
10981             *obufp++ = 'e';
10982           if (!(rex & REX_W))
10983             used_prefixes |= (prefixes & PREFIX_DATA);
10984           break;
10985         case 'S':
10986           if (l == 0)
10987             {
10988             case_S:
10989               if (intel_syntax)
10990                 break;
10991               if (sizeflag & SUFFIX_ALWAYS)
10992                 {
10993                   if (rex & REX_W)
10994                     *obufp++ = 'q';
10995                   else
10996                     {
10997                       if (sizeflag & DFLAG)
10998                         *obufp++ = 'l';
10999                       else
11000                         *obufp++ = 'w';
11001                       used_prefixes |= (prefixes & PREFIX_DATA);
11002                     }
11003                 }
11004             }
11005           else if (l == 1 && last[0] == 'L')
11006             {
11007               if (address_mode == mode_64bit
11008                   && !(prefixes & PREFIX_ADDR))
11009                 {
11010                   *obufp++ = 'a';
11011                   *obufp++ = 'b';
11012                   *obufp++ = 's';
11013                 }
11014
11015               goto case_S;
11016             }
11017           else
11018             abort ();
11019           break;
11020         case 'V':
11021           if (l == 0)
11022             abort ();
11023           else if (l == 1 && last[0] == 'L')
11024             {
11025               if (rex & REX_W)
11026                 {
11027                   *obufp++ = 'a';
11028                   *obufp++ = 'b';
11029                   *obufp++ = 's';
11030                 }
11031             }
11032           else
11033             abort ();
11034           goto case_S;
11035         case 'W':
11036           if (l == 0)
11037             {
11038               /* operand size flag for cwtl, cbtw */
11039               USED_REX (REX_W);
11040               if (rex & REX_W)
11041                 {
11042                   if (intel_syntax)
11043                     *obufp++ = 'd';
11044                   else
11045                     *obufp++ = 'l';
11046                 }
11047               else if (sizeflag & DFLAG)
11048                 *obufp++ = 'w';
11049               else
11050                 *obufp++ = 'b';
11051               if (!(rex & REX_W))
11052                 used_prefixes |= (prefixes & PREFIX_DATA);
11053             }
11054           else if (l == 1)
11055             {
11056               if (!need_vex)
11057                 abort ();
11058               if (last[0] == 'X')
11059                 *obufp++ = vex.w ? 'd': 's';
11060               else if (last[0] == 'B')
11061                 *obufp++ = vex.w ? 'w': 'b';
11062               else
11063                 abort ();
11064             }
11065           else
11066             abort ();
11067           break;
11068         case 'X':
11069           if (l != 0)
11070             abort ();
11071           if (need_vex
11072               ? vex.prefix == DATA_PREFIX_OPCODE
11073               : prefixes & PREFIX_DATA)
11074             {
11075               *obufp++ = 'd';
11076               used_prefixes |= PREFIX_DATA;
11077             }
11078           else
11079             *obufp++ = 's';
11080           break;
11081         case 'Y':
11082           if (l == 1 && last[0] == 'X')
11083             {
11084               if (!need_vex)
11085                 abort ();
11086               if (intel_syntax
11087                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
11088                 break;
11089               switch (vex.length)
11090                 {
11091                 case 128:
11092                   *obufp++ = 'x';
11093                   break;
11094                 case 256:
11095                   *obufp++ = 'y';
11096                   break;
11097                 case 512:
11098                   if (!vex.evex)
11099                 default:
11100                     abort ();
11101                 }
11102             }
11103           else
11104             abort ();
11105           break;
11106         case 'Z':
11107           if (l == 0)
11108             {
11109               /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
11110               modrm.mod = 3;
11111               if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11112                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
11113             }
11114           else if (l == 1 && last[0] == 'X')
11115             {
11116               if (!need_vex || !vex.evex)
11117                 abort ();
11118               if (intel_syntax
11119                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
11120                 break;
11121               switch (vex.length)
11122                 {
11123                 case 128:
11124                   *obufp++ = 'x';
11125                   break;
11126                 case 256:
11127                   *obufp++ = 'y';
11128                   break;
11129                 case 512:
11130                   *obufp++ = 'z';
11131                   break;
11132                 default:
11133                   abort ();
11134                 }
11135             }
11136           else
11137             abort ();
11138           break;
11139         case '^':
11140           if (intel_syntax)
11141             break;
11142           if (isa64 == intel64 && (rex & REX_W))
11143             {
11144               USED_REX (REX_W);
11145               *obufp++ = 'q';
11146               break;
11147             }
11148           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11149             {
11150               if (sizeflag & DFLAG)
11151                 *obufp++ = 'l';
11152               else
11153                 *obufp++ = 'w';
11154               used_prefixes |= (prefixes & PREFIX_DATA);
11155             }
11156           break;
11157         }
11158
11159       if (len == l)
11160         len = l = 0;
11161     }
11162   *obufp = 0;
11163   mnemonicendp = obufp;
11164   return 0;
11165 }
11166
11167 static void
11168 oappend (const char *s)
11169 {
11170   obufp = stpcpy (obufp, s);
11171 }
11172
11173 static void
11174 append_seg (void)
11175 {
11176   /* Only print the active segment register.  */
11177   if (!active_seg_prefix)
11178     return;
11179
11180   used_prefixes |= active_seg_prefix;
11181   switch (active_seg_prefix)
11182     {
11183     case PREFIX_CS:
11184       oappend_maybe_intel ("%cs:");
11185       break;
11186     case PREFIX_DS:
11187       oappend_maybe_intel ("%ds:");
11188       break;
11189     case PREFIX_SS:
11190       oappend_maybe_intel ("%ss:");
11191       break;
11192     case PREFIX_ES:
11193       oappend_maybe_intel ("%es:");
11194       break;
11195     case PREFIX_FS:
11196       oappend_maybe_intel ("%fs:");
11197       break;
11198     case PREFIX_GS:
11199       oappend_maybe_intel ("%gs:");
11200       break;
11201     default:
11202       break;
11203     }
11204 }
11205
11206 static void
11207 OP_indirE (int bytemode, int sizeflag)
11208 {
11209   if (!intel_syntax)
11210     oappend ("*");
11211   OP_E (bytemode, sizeflag);
11212 }
11213
11214 static void
11215 print_operand_value (char *buf, int hex, bfd_vma disp)
11216 {
11217   if (address_mode == mode_64bit)
11218     {
11219       if (hex)
11220         {
11221           char tmp[30];
11222           int i;
11223           buf[0] = '0';
11224           buf[1] = 'x';
11225           sprintf_vma (tmp, disp);
11226           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11227           strcpy (buf + 2, tmp + i);
11228         }
11229       else
11230         {
11231           bfd_signed_vma v = disp;
11232           char tmp[30];
11233           int i;
11234           if (v < 0)
11235             {
11236               *(buf++) = '-';
11237               v = -disp;
11238               /* Check for possible overflow on 0x8000000000000000.  */
11239               if (v < 0)
11240                 {
11241                   strcpy (buf, "9223372036854775808");
11242                   return;
11243                 }
11244             }
11245           if (!v)
11246             {
11247               strcpy (buf, "0");
11248               return;
11249             }
11250
11251           i = 0;
11252           tmp[29] = 0;
11253           while (v)
11254             {
11255               tmp[28 - i] = (v % 10) + '0';
11256               v /= 10;
11257               i++;
11258             }
11259           strcpy (buf, tmp + 29 - i);
11260         }
11261     }
11262   else
11263     {
11264       if (hex)
11265         sprintf (buf, "0x%x", (unsigned int) disp);
11266       else
11267         sprintf (buf, "%d", (int) disp);
11268     }
11269 }
11270
11271 /* Put DISP in BUF as signed hex number.  */
11272
11273 static void
11274 print_displacement (char *buf, bfd_vma disp)
11275 {
11276   bfd_signed_vma val = disp;
11277   char tmp[30];
11278   int i, j = 0;
11279
11280   if (val < 0)
11281     {
11282       buf[j++] = '-';
11283       val = -disp;
11284
11285       /* Check for possible overflow.  */
11286       if (val < 0)
11287         {
11288           switch (address_mode)
11289             {
11290             case mode_64bit:
11291               strcpy (buf + j, "0x8000000000000000");
11292               break;
11293             case mode_32bit:
11294               strcpy (buf + j, "0x80000000");
11295               break;
11296             case mode_16bit:
11297               strcpy (buf + j, "0x8000");
11298               break;
11299             }
11300           return;
11301         }
11302     }
11303
11304   buf[j++] = '0';
11305   buf[j++] = 'x';
11306
11307   sprintf_vma (tmp, (bfd_vma) val);
11308   for (i = 0; tmp[i] == '0'; i++)
11309     continue;
11310   if (tmp[i] == '\0')
11311     i--;
11312   strcpy (buf + j, tmp + i);
11313 }
11314
11315 static void
11316 intel_operand_size (int bytemode, int sizeflag)
11317 {
11318   if (vex.evex
11319       && vex.b
11320       && (bytemode == x_mode
11321           || bytemode == evex_half_bcst_xmmq_mode))
11322     {
11323       if (vex.w)
11324         oappend ("QWORD PTR ");
11325       else
11326         oappend ("DWORD PTR ");
11327       return;
11328     }
11329   switch (bytemode)
11330     {
11331     case b_mode:
11332     case b_swap_mode:
11333     case dqb_mode:
11334     case db_mode:
11335       oappend ("BYTE PTR ");
11336       break;
11337     case w_mode:
11338     case dw_mode:
11339     case dqw_mode:
11340       oappend ("WORD PTR ");
11341       break;
11342     case indir_v_mode:
11343       if (address_mode == mode_64bit && isa64 == intel64)
11344         {
11345           oappend ("QWORD PTR ");
11346           break;
11347         }
11348       /* Fall through.  */
11349     case stack_v_mode:
11350       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11351         {
11352           oappend ("QWORD PTR ");
11353           break;
11354         }
11355       /* Fall through.  */
11356     case v_mode:
11357     case v_swap_mode:
11358     case dq_mode:
11359       USED_REX (REX_W);
11360       if (rex & REX_W)
11361         oappend ("QWORD PTR ");
11362       else if (bytemode == dq_mode)
11363         oappend ("DWORD PTR ");
11364       else
11365         {
11366           if (sizeflag & DFLAG)
11367             oappend ("DWORD PTR ");
11368           else
11369             oappend ("WORD PTR ");
11370           used_prefixes |= (prefixes & PREFIX_DATA);
11371         }
11372       break;
11373     case z_mode:
11374       if ((rex & REX_W) || (sizeflag & DFLAG))
11375         *obufp++ = 'D';
11376       oappend ("WORD PTR ");
11377       if (!(rex & REX_W))
11378         used_prefixes |= (prefixes & PREFIX_DATA);
11379       break;
11380     case a_mode:
11381       if (sizeflag & DFLAG)
11382         oappend ("QWORD PTR ");
11383       else
11384         oappend ("DWORD PTR ");
11385       used_prefixes |= (prefixes & PREFIX_DATA);
11386       break;
11387     case movsxd_mode:
11388       if (!(sizeflag & DFLAG) && isa64 == intel64)
11389         oappend ("WORD PTR ");
11390       else
11391         oappend ("DWORD PTR ");
11392       used_prefixes |= (prefixes & PREFIX_DATA);
11393       break;
11394     case d_mode:
11395     case d_swap_mode:
11396     case dqd_mode:
11397       oappend ("DWORD PTR ");
11398       break;
11399     case q_mode:
11400     case q_swap_mode:
11401       oappend ("QWORD PTR ");
11402       break;
11403     case m_mode:
11404       if (address_mode == mode_64bit)
11405         oappend ("QWORD PTR ");
11406       else
11407         oappend ("DWORD PTR ");
11408       break;
11409     case f_mode:
11410       if (sizeflag & DFLAG)
11411         oappend ("FWORD PTR ");
11412       else
11413         oappend ("DWORD PTR ");
11414       used_prefixes |= (prefixes & PREFIX_DATA);
11415       break;
11416     case t_mode:
11417       oappend ("TBYTE PTR ");
11418       break;
11419     case x_mode:
11420     case x_swap_mode:
11421     case evex_x_gscat_mode:
11422     case evex_x_nobcst_mode:
11423     case bw_unit_mode:
11424       if (need_vex)
11425         {
11426           switch (vex.length)
11427             {
11428             case 128:
11429               oappend ("XMMWORD PTR ");
11430               break;
11431             case 256:
11432               oappend ("YMMWORD PTR ");
11433               break;
11434             case 512:
11435               oappend ("ZMMWORD PTR ");
11436               break;
11437             default:
11438               abort ();
11439             }
11440         }
11441       else
11442         oappend ("XMMWORD PTR ");
11443       break;
11444     case xmm_mode:
11445       oappend ("XMMWORD PTR ");
11446       break;
11447     case ymm_mode:
11448       oappend ("YMMWORD PTR ");
11449       break;
11450     case xmmq_mode:
11451     case evex_half_bcst_xmmq_mode:
11452       if (!need_vex)
11453         abort ();
11454
11455       switch (vex.length)
11456         {
11457         case 128:
11458           oappend ("QWORD PTR ");
11459           break;
11460         case 256:
11461           oappend ("XMMWORD PTR ");
11462           break;
11463         case 512:
11464           oappend ("YMMWORD PTR ");
11465           break;
11466         default:
11467           abort ();
11468         }
11469       break;
11470     case xmm_mb_mode:
11471       if (!need_vex)
11472         abort ();
11473
11474       switch (vex.length)
11475         {
11476         case 128:
11477         case 256:
11478         case 512:
11479           oappend ("BYTE PTR ");
11480           break;
11481         default:
11482           abort ();
11483         }
11484       break;
11485     case xmm_mw_mode:
11486       if (!need_vex)
11487         abort ();
11488
11489       switch (vex.length)
11490         {
11491         case 128:
11492         case 256:
11493         case 512:
11494           oappend ("WORD PTR ");
11495           break;
11496         default:
11497           abort ();
11498         }
11499       break;
11500     case xmm_md_mode:
11501       if (!need_vex)
11502         abort ();
11503
11504       switch (vex.length)
11505         {
11506         case 128:
11507         case 256:
11508         case 512:
11509           oappend ("DWORD PTR ");
11510           break;
11511         default:
11512           abort ();
11513         }
11514       break;
11515     case xmm_mq_mode:
11516       if (!need_vex)
11517         abort ();
11518
11519       switch (vex.length)
11520         {
11521         case 128:
11522         case 256:
11523         case 512:
11524           oappend ("QWORD PTR ");
11525           break;
11526         default:
11527           abort ();
11528         }
11529       break;
11530     case xmmdw_mode:
11531       if (!need_vex)
11532         abort ();
11533
11534       switch (vex.length)
11535         {
11536         case 128:
11537           oappend ("WORD PTR ");
11538           break;
11539         case 256:
11540           oappend ("DWORD PTR ");
11541           break;
11542         case 512:
11543           oappend ("QWORD PTR ");
11544           break;
11545         default:
11546           abort ();
11547         }
11548       break;
11549     case xmmqd_mode:
11550       if (!need_vex)
11551         abort ();
11552
11553       switch (vex.length)
11554         {
11555         case 128:
11556           oappend ("DWORD PTR ");
11557           break;
11558         case 256:
11559           oappend ("QWORD PTR ");
11560           break;
11561         case 512:
11562           oappend ("XMMWORD PTR ");
11563           break;
11564         default:
11565           abort ();
11566         }
11567       break;
11568     case ymmq_mode:
11569       if (!need_vex)
11570         abort ();
11571
11572       switch (vex.length)
11573         {
11574         case 128:
11575           oappend ("QWORD PTR ");
11576           break;
11577         case 256:
11578           oappend ("YMMWORD PTR ");
11579           break;
11580         case 512:
11581           oappend ("ZMMWORD PTR ");
11582           break;
11583         default:
11584           abort ();
11585         }
11586       break;
11587     case ymmxmm_mode:
11588       if (!need_vex)
11589         abort ();
11590
11591       switch (vex.length)
11592         {
11593         case 128:
11594         case 256:
11595           oappend ("XMMWORD PTR ");
11596           break;
11597         default:
11598           abort ();
11599         }
11600       break;
11601     case o_mode:
11602       oappend ("OWORD PTR ");
11603       break;
11604     case vex_scalar_w_dq_mode:
11605       if (!need_vex)
11606         abort ();
11607
11608       if (vex.w)
11609         oappend ("QWORD PTR ");
11610       else
11611         oappend ("DWORD PTR ");
11612       break;
11613     case vex_vsib_d_w_dq_mode:
11614     case vex_vsib_q_w_dq_mode:
11615       if (!need_vex)
11616         abort ();
11617
11618       if (!vex.evex)
11619         {
11620           if (vex.w)
11621             oappend ("QWORD PTR ");
11622           else
11623             oappend ("DWORD PTR ");
11624         }
11625       else
11626         {
11627           switch (vex.length)
11628             {
11629             case 128:
11630               oappend ("XMMWORD PTR ");
11631               break;
11632             case 256:
11633               oappend ("YMMWORD PTR ");
11634               break;
11635             case 512:
11636               oappend ("ZMMWORD PTR ");
11637               break;
11638             default:
11639               abort ();
11640             }
11641         }
11642       break;
11643     case vex_vsib_q_w_d_mode:
11644     case vex_vsib_d_w_d_mode:
11645       if (!need_vex || !vex.evex)
11646         abort ();
11647
11648       switch (vex.length)
11649         {
11650         case 128:
11651           oappend ("QWORD PTR ");
11652           break;
11653         case 256:
11654           oappend ("XMMWORD PTR ");
11655           break;
11656         case 512:
11657           oappend ("YMMWORD PTR ");
11658           break;
11659         default:
11660           abort ();
11661         }
11662
11663       break;
11664     case mask_bd_mode:
11665       if (!need_vex || vex.length != 128)
11666         abort ();
11667       if (vex.w)
11668         oappend ("DWORD PTR ");
11669       else
11670         oappend ("BYTE PTR ");
11671       break;
11672     case mask_mode:
11673       if (!need_vex)
11674         abort ();
11675       if (vex.w)
11676         oappend ("QWORD PTR ");
11677       else
11678         oappend ("WORD PTR ");
11679       break;
11680     case v_bnd_mode:
11681     case v_bndmk_mode:
11682     default:
11683       break;
11684     }
11685 }
11686
11687 static void
11688 OP_E_register (int bytemode, int sizeflag)
11689 {
11690   int reg = modrm.rm;
11691   const char **names;
11692
11693   USED_REX (REX_B);
11694   if ((rex & REX_B))
11695     reg += 8;
11696
11697   if ((sizeflag & SUFFIX_ALWAYS)
11698       && (bytemode == b_swap_mode
11699           || bytemode == bnd_swap_mode
11700           || bytemode == v_swap_mode))
11701     swap_operand ();
11702
11703   switch (bytemode)
11704     {
11705     case b_mode:
11706     case b_swap_mode:
11707       if (reg & 4)
11708         USED_REX (0);
11709       if (rex)
11710         names = names8rex;
11711       else
11712         names = names8;
11713       break;
11714     case w_mode:
11715       names = names16;
11716       break;
11717     case d_mode:
11718     case dw_mode:
11719     case db_mode:
11720       names = names32;
11721       break;
11722     case q_mode:
11723       names = names64;
11724       break;
11725     case m_mode:
11726     case v_bnd_mode:
11727       names = address_mode == mode_64bit ? names64 : names32;
11728       break;
11729     case bnd_mode:
11730     case bnd_swap_mode:
11731       if (reg > 0x3)
11732         {
11733           oappend ("(bad)");
11734           return;
11735         }
11736       names = names_bnd;
11737       break;
11738     case indir_v_mode:
11739       if (address_mode == mode_64bit && isa64 == intel64)
11740         {
11741           names = names64;
11742           break;
11743         }
11744       /* Fall through.  */
11745     case stack_v_mode:
11746       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11747         {
11748           names = names64;
11749           break;
11750         }
11751       bytemode = v_mode;
11752       /* Fall through.  */
11753     case v_mode:
11754     case v_swap_mode:
11755     case dq_mode:
11756     case dqb_mode:
11757     case dqd_mode:
11758     case dqw_mode:
11759       USED_REX (REX_W);
11760       if (rex & REX_W)
11761         names = names64;
11762       else if (bytemode != v_mode && bytemode != v_swap_mode)
11763         names = names32;
11764       else
11765         {
11766           if (sizeflag & DFLAG)
11767             names = names32;
11768           else
11769             names = names16;
11770           used_prefixes |= (prefixes & PREFIX_DATA);
11771         }
11772       break;
11773     case movsxd_mode:
11774       if (!(sizeflag & DFLAG) && isa64 == intel64)
11775         names = names16;
11776       else
11777         names = names32;
11778       used_prefixes |= (prefixes & PREFIX_DATA);
11779       break;
11780     case va_mode:
11781       names = (address_mode == mode_64bit
11782                ? names64 : names32);
11783       if (!(prefixes & PREFIX_ADDR))
11784         names = (address_mode == mode_16bit
11785                      ? names16 : names);
11786       else
11787         {
11788           /* Remove "addr16/addr32".  */
11789           all_prefixes[last_addr_prefix] = 0;
11790           names = (address_mode != mode_32bit
11791                        ? names32 : names16);
11792           used_prefixes |= PREFIX_ADDR;
11793         }
11794       break;
11795     case mask_bd_mode:
11796     case mask_mode:
11797       if (reg > 0x7)
11798         {
11799           oappend ("(bad)");
11800           return;
11801         }
11802       names = names_mask;
11803       break;
11804     case 0:
11805       return;
11806     default:
11807       oappend (INTERNAL_DISASSEMBLER_ERROR);
11808       return;
11809     }
11810   oappend (names[reg]);
11811 }
11812
11813 static void
11814 OP_E_memory (int bytemode, int sizeflag)
11815 {
11816   bfd_vma disp = 0;
11817   int add = (rex & REX_B) ? 8 : 0;
11818   int riprel = 0;
11819   int shift;
11820
11821   if (vex.evex)
11822     {
11823       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
11824       if (vex.b
11825           && bytemode != x_mode
11826           && bytemode != xmmq_mode
11827           && bytemode != evex_half_bcst_xmmq_mode)
11828         {
11829           BadOp ();
11830           return;
11831         }
11832       switch (bytemode)
11833         {
11834         case dqw_mode:
11835         case dw_mode:
11836         case xmm_mw_mode:
11837           shift = 1;
11838           break;
11839         case dqb_mode:
11840         case db_mode:
11841         case xmm_mb_mode:
11842           shift = 0;
11843           break;
11844         case dq_mode:
11845           if (address_mode != mode_64bit)
11846             {
11847         case dqd_mode:
11848         case xmm_md_mode:
11849         case d_mode:
11850         case d_swap_mode:
11851               shift = 2;
11852               break;
11853             }
11854             /* fall through */
11855         case vex_scalar_w_dq_mode:
11856         case vex_vsib_d_w_dq_mode:
11857         case vex_vsib_d_w_d_mode:
11858         case vex_vsib_q_w_dq_mode:
11859         case vex_vsib_q_w_d_mode:
11860         case evex_x_gscat_mode:
11861           shift = vex.w ? 3 : 2;
11862           break;
11863         case x_mode:
11864         case evex_half_bcst_xmmq_mode:
11865         case xmmq_mode:
11866           if (vex.b)
11867             {
11868               shift = vex.w ? 3 : 2;
11869               break;
11870             }
11871           /* Fall through.  */
11872         case xmmqd_mode:
11873         case xmmdw_mode:
11874         case ymmq_mode:
11875         case evex_x_nobcst_mode:
11876         case x_swap_mode:
11877           switch (vex.length)
11878             {
11879             case 128:
11880               shift = 4;
11881               break;
11882             case 256:
11883               shift = 5;
11884               break;
11885             case 512:
11886               shift = 6;
11887               break;
11888             default:
11889               abort ();
11890             }
11891           /* Make necessary corrections to shift for modes that need it.  */
11892           if (bytemode == xmmq_mode
11893               || bytemode == evex_half_bcst_xmmq_mode
11894               || (bytemode == ymmq_mode && vex.length == 128))
11895             shift -= 1;
11896           else if (bytemode == xmmqd_mode)
11897             shift -= 2;
11898           else if (bytemode == xmmdw_mode)
11899             shift -= 3;
11900           break;
11901         case ymm_mode:
11902           shift = 5;
11903           break;
11904         case xmm_mode:
11905           shift = 4;
11906           break;
11907         case xmm_mq_mode:
11908         case q_mode:
11909         case q_swap_mode:
11910           shift = 3;
11911           break;
11912         case bw_unit_mode:
11913           shift = vex.w ? 1 : 0;
11914           break;
11915         default:
11916           abort ();
11917         }
11918     }
11919   else
11920     shift = 0;
11921
11922   USED_REX (REX_B);
11923   if (intel_syntax)
11924     intel_operand_size (bytemode, sizeflag);
11925   append_seg ();
11926
11927   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11928     {
11929       /* 32/64 bit address mode */
11930       int havedisp;
11931       int havesib;
11932       int havebase;
11933       int haveindex;
11934       int needindex;
11935       int needaddr32;
11936       int base, rbase;
11937       int vindex = 0;
11938       int scale = 0;
11939       int addr32flag = !((sizeflag & AFLAG)
11940                          || bytemode == v_bnd_mode
11941                          || bytemode == v_bndmk_mode
11942                          || bytemode == bnd_mode
11943                          || bytemode == bnd_swap_mode);
11944       const char **indexes64 = names64;
11945       const char **indexes32 = names32;
11946
11947       havesib = 0;
11948       havebase = 1;
11949       haveindex = 0;
11950       base = modrm.rm;
11951
11952       if (base == 4)
11953         {
11954           havesib = 1;
11955           vindex = sib.index;
11956           USED_REX (REX_X);
11957           if (rex & REX_X)
11958             vindex += 8;
11959           switch (bytemode)
11960             {
11961             case vex_vsib_d_w_dq_mode:
11962             case vex_vsib_d_w_d_mode:
11963             case vex_vsib_q_w_dq_mode:
11964             case vex_vsib_q_w_d_mode:
11965               if (!need_vex)
11966                 abort ();
11967               if (vex.evex)
11968                 {
11969                   if (!vex.v)
11970                     vindex += 16;
11971                 }
11972
11973               haveindex = 1;
11974               switch (vex.length)
11975                 {
11976                 case 128:
11977                   indexes64 = indexes32 = names_xmm;
11978                   break;
11979                 case 256:
11980                   if (!vex.w
11981                       || bytemode == vex_vsib_q_w_dq_mode
11982                       || bytemode == vex_vsib_q_w_d_mode)
11983                     indexes64 = indexes32 = names_ymm;
11984                   else
11985                     indexes64 = indexes32 = names_xmm;
11986                   break;
11987                 case 512:
11988                   if (!vex.w
11989                       || bytemode == vex_vsib_q_w_dq_mode
11990                       || bytemode == vex_vsib_q_w_d_mode)
11991                     indexes64 = indexes32 = names_zmm;
11992                   else
11993                     indexes64 = indexes32 = names_ymm;
11994                   break;
11995                 default:
11996                   abort ();
11997                 }
11998               break;
11999             default:
12000               haveindex = vindex != 4;
12001               break;
12002             }
12003           scale = sib.scale;
12004           base = sib.base;
12005           codep++;
12006         }
12007       else
12008         {
12009           /* mandatory non-vector SIB must have sib */
12010           if (bytemode == vex_sibmem_mode)
12011             {
12012               oappend ("(bad)");
12013               return;
12014             }
12015         }
12016       rbase = base + add;
12017
12018       switch (modrm.mod)
12019         {
12020         case 0:
12021           if (base == 5)
12022             {
12023               havebase = 0;
12024               if (address_mode == mode_64bit && !havesib)
12025                 riprel = 1;
12026               disp = get32s ();
12027               if (riprel && bytemode == v_bndmk_mode)
12028                 {
12029                   oappend ("(bad)");
12030                   return;
12031                 }
12032             }
12033           break;
12034         case 1:
12035           FETCH_DATA (the_info, codep + 1);
12036           disp = *codep++;
12037           if ((disp & 0x80) != 0)
12038             disp -= 0x100;
12039           if (vex.evex && shift > 0)
12040             disp <<= shift;
12041           break;
12042         case 2:
12043           disp = get32s ();
12044           break;
12045         }
12046
12047       needindex = 0;
12048       needaddr32 = 0;
12049       if (havesib
12050           && !havebase
12051           && !haveindex
12052           && address_mode != mode_16bit)
12053         {
12054           if (address_mode == mode_64bit)
12055             {
12056               if (addr32flag)
12057                 {
12058                   /* Without base nor index registers, zero-extend the
12059                      lower 32-bit displacement to 64 bits.  */
12060                   disp = (unsigned int) disp;
12061                   needindex = 1;
12062                 }
12063               needaddr32 = 1;
12064             }
12065           else
12066             {
12067               /* In 32-bit mode, we need index register to tell [offset]
12068                  from [eiz*1 + offset].  */
12069               needindex = 1;
12070             }
12071         }
12072
12073       havedisp = (havebase
12074                   || needindex
12075                   || (havesib && (haveindex || scale != 0)));
12076
12077       if (!intel_syntax)
12078         if (modrm.mod != 0 || base == 5)
12079           {
12080             if (havedisp || riprel)
12081               print_displacement (scratchbuf, disp);
12082             else
12083               print_operand_value (scratchbuf, 1, disp);
12084             oappend (scratchbuf);
12085             if (riprel)
12086               {
12087                 set_op (disp, 1);
12088                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
12089               }
12090           }
12091
12092       if ((havebase || haveindex || needindex || needaddr32 || riprel)
12093           && (address_mode != mode_64bit
12094               || ((bytemode != v_bnd_mode)
12095                   && (bytemode != v_bndmk_mode)
12096                   && (bytemode != bnd_mode)
12097                   && (bytemode != bnd_swap_mode))))
12098         used_prefixes |= PREFIX_ADDR;
12099
12100       if (havedisp || (intel_syntax && riprel))
12101         {
12102           *obufp++ = open_char;
12103           if (intel_syntax && riprel)
12104             {
12105               set_op (disp, 1);
12106               oappend (!addr32flag ? "rip" : "eip");
12107             }
12108           *obufp = '\0';
12109           if (havebase)
12110             oappend (address_mode == mode_64bit && !addr32flag
12111                      ? names64[rbase] : names32[rbase]);
12112           if (havesib)
12113             {
12114               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
12115                  print index to tell base + index from base.  */
12116               if (scale != 0
12117                   || needindex
12118                   || haveindex
12119                   || (havebase && base != ESP_REG_NUM))
12120                 {
12121                   if (!intel_syntax || havebase)
12122                     {
12123                       *obufp++ = separator_char;
12124                       *obufp = '\0';
12125                     }
12126                   if (haveindex)
12127                     oappend (address_mode == mode_64bit && !addr32flag
12128                              ? indexes64[vindex] : indexes32[vindex]);
12129                   else
12130                     oappend (address_mode == mode_64bit && !addr32flag
12131                              ? index64 : index32);
12132
12133                   *obufp++ = scale_char;
12134                   *obufp = '\0';
12135                   sprintf (scratchbuf, "%d", 1 << scale);
12136                   oappend (scratchbuf);
12137                 }
12138             }
12139           if (intel_syntax
12140               && (disp || modrm.mod != 0 || base == 5))
12141             {
12142               if (!havedisp || (bfd_signed_vma) disp >= 0)
12143                 {
12144                   *obufp++ = '+';
12145                   *obufp = '\0';
12146                 }
12147               else if (modrm.mod != 1 && disp != -disp)
12148                 {
12149                   *obufp++ = '-';
12150                   *obufp = '\0';
12151                   disp = -disp;
12152                 }
12153
12154               if (havedisp)
12155                 print_displacement (scratchbuf, disp);
12156               else
12157                 print_operand_value (scratchbuf, 1, disp);
12158               oappend (scratchbuf);
12159             }
12160
12161           *obufp++ = close_char;
12162           *obufp = '\0';
12163         }
12164       else if (intel_syntax)
12165         {
12166           if (modrm.mod != 0 || base == 5)
12167             {
12168               if (!active_seg_prefix)
12169                 {
12170                   oappend (names_seg[ds_reg - es_reg]);
12171                   oappend (":");
12172                 }
12173               print_operand_value (scratchbuf, 1, disp);
12174               oappend (scratchbuf);
12175             }
12176         }
12177     }
12178   else if (bytemode == v_bnd_mode
12179            || bytemode == v_bndmk_mode
12180            || bytemode == bnd_mode
12181            || bytemode == bnd_swap_mode)
12182     {
12183       oappend ("(bad)");
12184       return;
12185     }
12186   else
12187     {
12188       /* 16 bit address mode */
12189       used_prefixes |= prefixes & PREFIX_ADDR;
12190       switch (modrm.mod)
12191         {
12192         case 0:
12193           if (modrm.rm == 6)
12194             {
12195               disp = get16 ();
12196               if ((disp & 0x8000) != 0)
12197                 disp -= 0x10000;
12198             }
12199           break;
12200         case 1:
12201           FETCH_DATA (the_info, codep + 1);
12202           disp = *codep++;
12203           if ((disp & 0x80) != 0)
12204             disp -= 0x100;
12205           if (vex.evex && shift > 0)
12206             disp <<= shift;
12207           break;
12208         case 2:
12209           disp = get16 ();
12210           if ((disp & 0x8000) != 0)
12211             disp -= 0x10000;
12212           break;
12213         }
12214
12215       if (!intel_syntax)
12216         if (modrm.mod != 0 || modrm.rm == 6)
12217           {
12218             print_displacement (scratchbuf, disp);
12219             oappend (scratchbuf);
12220           }
12221
12222       if (modrm.mod != 0 || modrm.rm != 6)
12223         {
12224           *obufp++ = open_char;
12225           *obufp = '\0';
12226           oappend (index16[modrm.rm]);
12227           if (intel_syntax
12228               && (disp || modrm.mod != 0 || modrm.rm == 6))
12229             {
12230               if ((bfd_signed_vma) disp >= 0)
12231                 {
12232                   *obufp++ = '+';
12233                   *obufp = '\0';
12234                 }
12235               else if (modrm.mod != 1)
12236                 {
12237                   *obufp++ = '-';
12238                   *obufp = '\0';
12239                   disp = -disp;
12240                 }
12241
12242               print_displacement (scratchbuf, disp);
12243               oappend (scratchbuf);
12244             }
12245
12246           *obufp++ = close_char;
12247           *obufp = '\0';
12248         }
12249       else if (intel_syntax)
12250         {
12251           if (!active_seg_prefix)
12252             {
12253               oappend (names_seg[ds_reg - es_reg]);
12254               oappend (":");
12255             }
12256           print_operand_value (scratchbuf, 1, disp & 0xffff);
12257           oappend (scratchbuf);
12258         }
12259     }
12260   if (vex.evex && vex.b
12261       && (bytemode == x_mode
12262           || bytemode == xmmq_mode
12263           || bytemode == evex_half_bcst_xmmq_mode))
12264     {
12265       if (vex.w
12266           || bytemode == xmmq_mode
12267           || bytemode == evex_half_bcst_xmmq_mode)
12268         {
12269           switch (vex.length)
12270             {
12271             case 128:
12272               oappend ("{1to2}");
12273               break;
12274             case 256:
12275               oappend ("{1to4}");
12276               break;
12277             case 512:
12278               oappend ("{1to8}");
12279               break;
12280             default:
12281               abort ();
12282             }
12283         }
12284       else
12285         {
12286           switch (vex.length)
12287             {
12288             case 128:
12289               oappend ("{1to4}");
12290               break;
12291             case 256:
12292               oappend ("{1to8}");
12293               break;
12294             case 512:
12295               oappend ("{1to16}");
12296               break;
12297             default:
12298               abort ();
12299             }
12300         }
12301     }
12302 }
12303
12304 static void
12305 OP_E (int bytemode, int sizeflag)
12306 {
12307   /* Skip mod/rm byte.  */
12308   MODRM_CHECK;
12309   codep++;
12310
12311   if (modrm.mod == 3)
12312     OP_E_register (bytemode, sizeflag);
12313   else
12314     OP_E_memory (bytemode, sizeflag);
12315 }
12316
12317 static void
12318 OP_G (int bytemode, int sizeflag)
12319 {
12320   int add = 0;
12321   const char **names;
12322   USED_REX (REX_R);
12323   if (rex & REX_R)
12324     add += 8;
12325   switch (bytemode)
12326     {
12327     case b_mode:
12328       if (modrm.reg & 4)
12329         USED_REX (0);
12330       if (rex)
12331         oappend (names8rex[modrm.reg + add]);
12332       else
12333         oappend (names8[modrm.reg + add]);
12334       break;
12335     case w_mode:
12336       oappend (names16[modrm.reg + add]);
12337       break;
12338     case d_mode:
12339     case db_mode:
12340     case dw_mode:
12341       oappend (names32[modrm.reg + add]);
12342       break;
12343     case q_mode:
12344       oappend (names64[modrm.reg + add]);
12345       break;
12346     case bnd_mode:
12347       if (modrm.reg > 0x3)
12348         {
12349           oappend ("(bad)");
12350           return;
12351         }
12352       oappend (names_bnd[modrm.reg]);
12353       break;
12354     case v_mode:
12355     case dq_mode:
12356     case dqb_mode:
12357     case dqd_mode:
12358     case dqw_mode:
12359     case movsxd_mode:
12360       USED_REX (REX_W);
12361       if (rex & REX_W)
12362         oappend (names64[modrm.reg + add]);
12363       else if (bytemode != v_mode && bytemode != movsxd_mode)
12364         oappend (names32[modrm.reg + add]);
12365       else
12366         {
12367           if (sizeflag & DFLAG)
12368             oappend (names32[modrm.reg + add]);
12369           else
12370             oappend (names16[modrm.reg + add]);
12371           used_prefixes |= (prefixes & PREFIX_DATA);
12372         }
12373       break;
12374     case va_mode:
12375       names = (address_mode == mode_64bit
12376                ? names64 : names32);
12377       if (!(prefixes & PREFIX_ADDR))
12378         {
12379           if (address_mode == mode_16bit)
12380             names = names16;
12381         }
12382       else
12383         {
12384           /* Remove "addr16/addr32".  */
12385           all_prefixes[last_addr_prefix] = 0;
12386           names = (address_mode != mode_32bit
12387                        ? names32 : names16);
12388           used_prefixes |= PREFIX_ADDR;
12389         }
12390       oappend (names[modrm.reg + add]);
12391       break;
12392     case m_mode:
12393       if (address_mode == mode_64bit)
12394         oappend (names64[modrm.reg + add]);
12395       else
12396         oappend (names32[modrm.reg + add]);
12397       break;
12398     case mask_bd_mode:
12399     case mask_mode:
12400       if ((modrm.reg + add) > 0x7)
12401         {
12402           oappend ("(bad)");
12403           return;
12404         }
12405       oappend (names_mask[modrm.reg + add]);
12406       break;
12407     default:
12408       oappend (INTERNAL_DISASSEMBLER_ERROR);
12409       break;
12410     }
12411 }
12412
12413 static bfd_vma
12414 get64 (void)
12415 {
12416   bfd_vma x;
12417 #ifdef BFD64
12418   unsigned int a;
12419   unsigned int b;
12420
12421   FETCH_DATA (the_info, codep + 8);
12422   a = *codep++ & 0xff;
12423   a |= (*codep++ & 0xff) << 8;
12424   a |= (*codep++ & 0xff) << 16;
12425   a |= (*codep++ & 0xffu) << 24;
12426   b = *codep++ & 0xff;
12427   b |= (*codep++ & 0xff) << 8;
12428   b |= (*codep++ & 0xff) << 16;
12429   b |= (*codep++ & 0xffu) << 24;
12430   x = a + ((bfd_vma) b << 32);
12431 #else
12432   abort ();
12433   x = 0;
12434 #endif
12435   return x;
12436 }
12437
12438 static bfd_signed_vma
12439 get32 (void)
12440 {
12441   bfd_vma x = 0;
12442
12443   FETCH_DATA (the_info, codep + 4);
12444   x = *codep++ & (bfd_vma) 0xff;
12445   x |= (*codep++ & (bfd_vma) 0xff) << 8;
12446   x |= (*codep++ & (bfd_vma) 0xff) << 16;
12447   x |= (*codep++ & (bfd_vma) 0xff) << 24;
12448   return x;
12449 }
12450
12451 static bfd_signed_vma
12452 get32s (void)
12453 {
12454   bfd_vma x = 0;
12455
12456   FETCH_DATA (the_info, codep + 4);
12457   x = *codep++ & (bfd_vma) 0xff;
12458   x |= (*codep++ & (bfd_vma) 0xff) << 8;
12459   x |= (*codep++ & (bfd_vma) 0xff) << 16;
12460   x |= (*codep++ & (bfd_vma) 0xff) << 24;
12461
12462   x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12463
12464   return x;
12465 }
12466
12467 static int
12468 get16 (void)
12469 {
12470   int x = 0;
12471
12472   FETCH_DATA (the_info, codep + 2);
12473   x = *codep++ & 0xff;
12474   x |= (*codep++ & 0xff) << 8;
12475   return x;
12476 }
12477
12478 static void
12479 set_op (bfd_vma op, int riprel)
12480 {
12481   op_index[op_ad] = op_ad;
12482   if (address_mode == mode_64bit)
12483     {
12484       op_address[op_ad] = op;
12485       op_riprel[op_ad] = riprel;
12486     }
12487   else
12488     {
12489       /* Mask to get a 32-bit address.  */
12490       op_address[op_ad] = op & 0xffffffff;
12491       op_riprel[op_ad] = riprel & 0xffffffff;
12492     }
12493 }
12494
12495 static void
12496 OP_REG (int code, int sizeflag)
12497 {
12498   const char *s;
12499   int add;
12500
12501   switch (code)
12502     {
12503     case es_reg: case ss_reg: case cs_reg:
12504     case ds_reg: case fs_reg: case gs_reg:
12505       oappend (names_seg[code - es_reg]);
12506       return;
12507     }
12508
12509   USED_REX (REX_B);
12510   if (rex & REX_B)
12511     add = 8;
12512   else
12513     add = 0;
12514
12515   switch (code)
12516     {
12517     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12518     case sp_reg: case bp_reg: case si_reg: case di_reg:
12519       s = names16[code - ax_reg + add];
12520       break;
12521     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12522       USED_REX (0);
12523       /* Fall through.  */
12524     case al_reg: case cl_reg: case dl_reg: case bl_reg:
12525       if (rex)
12526         s = names8rex[code - al_reg + add];
12527       else
12528         s = names8[code - al_reg];
12529       break;
12530     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12531     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12532       if (address_mode == mode_64bit
12533           && ((sizeflag & DFLAG) || (rex & REX_W)))
12534         {
12535           s = names64[code - rAX_reg + add];
12536           break;
12537         }
12538       code += eAX_reg - rAX_reg;
12539       /* Fall through.  */
12540     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12541     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12542       USED_REX (REX_W);
12543       if (rex & REX_W)
12544         s = names64[code - eAX_reg + add];
12545       else
12546         {
12547           if (sizeflag & DFLAG)
12548             s = names32[code - eAX_reg + add];
12549           else
12550             s = names16[code - eAX_reg + add];
12551           used_prefixes |= (prefixes & PREFIX_DATA);
12552         }
12553       break;
12554     default:
12555       s = INTERNAL_DISASSEMBLER_ERROR;
12556       break;
12557     }
12558   oappend (s);
12559 }
12560
12561 static void
12562 OP_IMREG (int code, int sizeflag)
12563 {
12564   const char *s;
12565
12566   switch (code)
12567     {
12568     case indir_dx_reg:
12569       if (intel_syntax)
12570         s = "dx";
12571       else
12572         s = "(%dx)";
12573       break;
12574     case al_reg: case cl_reg:
12575       s = names8[code - al_reg];
12576       break;
12577     case eAX_reg:
12578       USED_REX (REX_W);
12579       if (rex & REX_W)
12580         {
12581           s = *names64;
12582           break;
12583         }
12584       /* Fall through.  */
12585     case z_mode_ax_reg:
12586       if ((rex & REX_W) || (sizeflag & DFLAG))
12587         s = *names32;
12588       else
12589         s = *names16;
12590       if (!(rex & REX_W))
12591         used_prefixes |= (prefixes & PREFIX_DATA);
12592       break;
12593     default:
12594       s = INTERNAL_DISASSEMBLER_ERROR;
12595       break;
12596     }
12597   oappend (s);
12598 }
12599
12600 static void
12601 OP_I (int bytemode, int sizeflag)
12602 {
12603   bfd_signed_vma op;
12604   bfd_signed_vma mask = -1;
12605
12606   switch (bytemode)
12607     {
12608     case b_mode:
12609       FETCH_DATA (the_info, codep + 1);
12610       op = *codep++;
12611       mask = 0xff;
12612       break;
12613     case v_mode:
12614       USED_REX (REX_W);
12615       if (rex & REX_W)
12616         op = get32s ();
12617       else
12618         {
12619           if (sizeflag & DFLAG)
12620             {
12621               op = get32 ();
12622               mask = 0xffffffff;
12623             }
12624           else
12625             {
12626               op = get16 ();
12627               mask = 0xfffff;
12628             }
12629           used_prefixes |= (prefixes & PREFIX_DATA);
12630         }
12631       break;
12632     case d_mode:
12633       mask = 0xffffffff;
12634       op = get32 ();
12635       break;
12636     case w_mode:
12637       mask = 0xfffff;
12638       op = get16 ();
12639       break;
12640     case const_1_mode:
12641       if (intel_syntax)
12642         oappend ("1");
12643       return;
12644     default:
12645       oappend (INTERNAL_DISASSEMBLER_ERROR);
12646       return;
12647     }
12648
12649   op &= mask;
12650   scratchbuf[0] = '$';
12651   print_operand_value (scratchbuf + 1, 1, op);
12652   oappend_maybe_intel (scratchbuf);
12653   scratchbuf[0] = '\0';
12654 }
12655
12656 static void
12657 OP_I64 (int bytemode, int sizeflag)
12658 {
12659   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
12660     {
12661       OP_I (bytemode, sizeflag);
12662       return;
12663     }
12664
12665   USED_REX (REX_W);
12666
12667   scratchbuf[0] = '$';
12668   print_operand_value (scratchbuf + 1, 1, get64 ());
12669   oappend_maybe_intel (scratchbuf);
12670   scratchbuf[0] = '\0';
12671 }
12672
12673 static void
12674 OP_sI (int bytemode, int sizeflag)
12675 {
12676   bfd_signed_vma op;
12677
12678   switch (bytemode)
12679     {
12680     case b_mode:
12681     case b_T_mode:
12682       FETCH_DATA (the_info, codep + 1);
12683       op = *codep++;
12684       if ((op & 0x80) != 0)
12685         op -= 0x100;
12686       if (bytemode == b_T_mode)
12687         {
12688           if (address_mode != mode_64bit
12689               || !((sizeflag & DFLAG) || (rex & REX_W)))
12690             {
12691               /* The operand-size prefix is overridden by a REX prefix.  */
12692               if ((sizeflag & DFLAG) || (rex & REX_W))
12693                 op &= 0xffffffff;
12694               else
12695                 op &= 0xffff;
12696           }
12697         }
12698       else
12699         {
12700           if (!(rex & REX_W))
12701             {
12702               if (sizeflag & DFLAG)
12703                 op &= 0xffffffff;
12704               else
12705                 op &= 0xffff;
12706             }
12707         }
12708       break;
12709     case v_mode:
12710       /* The operand-size prefix is overridden by a REX prefix.  */
12711       if ((sizeflag & DFLAG) || (rex & REX_W))
12712         op = get32s ();
12713       else
12714         op = get16 ();
12715       break;
12716     default:
12717       oappend (INTERNAL_DISASSEMBLER_ERROR);
12718       return;
12719     }
12720
12721   scratchbuf[0] = '$';
12722   print_operand_value (scratchbuf + 1, 1, op);
12723   oappend_maybe_intel (scratchbuf);
12724 }
12725
12726 static void
12727 OP_J (int bytemode, int sizeflag)
12728 {
12729   bfd_vma disp;
12730   bfd_vma mask = -1;
12731   bfd_vma segment = 0;
12732
12733   switch (bytemode)
12734     {
12735     case b_mode:
12736       FETCH_DATA (the_info, codep + 1);
12737       disp = *codep++;
12738       if ((disp & 0x80) != 0)
12739         disp -= 0x100;
12740       break;
12741     case v_mode:
12742     case dqw_mode:
12743       if ((sizeflag & DFLAG)
12744           || (address_mode == mode_64bit
12745               && ((isa64 == intel64 && bytemode != dqw_mode)
12746                   || (rex & REX_W))))
12747         disp = get32s ();
12748       else
12749         {
12750           disp = get16 ();
12751           if ((disp & 0x8000) != 0)
12752             disp -= 0x10000;
12753           /* In 16bit mode, address is wrapped around at 64k within
12754              the same segment.  Otherwise, a data16 prefix on a jump
12755              instruction means that the pc is masked to 16 bits after
12756              the displacement is added!  */
12757           mask = 0xffff;
12758           if ((prefixes & PREFIX_DATA) == 0)
12759             segment = ((start_pc + (codep - start_codep))
12760                        & ~((bfd_vma) 0xffff));
12761         }
12762       if (address_mode != mode_64bit
12763           || (isa64 != intel64 && !(rex & REX_W)))
12764         used_prefixes |= (prefixes & PREFIX_DATA);
12765       break;
12766     default:
12767       oappend (INTERNAL_DISASSEMBLER_ERROR);
12768       return;
12769     }
12770   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
12771   set_op (disp, 0);
12772   print_operand_value (scratchbuf, 1, disp);
12773   oappend (scratchbuf);
12774 }
12775
12776 static void
12777 OP_SEG (int bytemode, int sizeflag)
12778 {
12779   if (bytemode == w_mode)
12780     oappend (names_seg[modrm.reg]);
12781   else
12782     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12783 }
12784
12785 static void
12786 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12787 {
12788   int seg, offset;
12789
12790   if (sizeflag & DFLAG)
12791     {
12792       offset = get32 ();
12793       seg = get16 ();
12794     }
12795   else
12796     {
12797       offset = get16 ();
12798       seg = get16 ();
12799     }
12800   used_prefixes |= (prefixes & PREFIX_DATA);
12801   if (intel_syntax)
12802     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12803   else
12804     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12805   oappend (scratchbuf);
12806 }
12807
12808 static void
12809 OP_OFF (int bytemode, int sizeflag)
12810 {
12811   bfd_vma off;
12812
12813   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12814     intel_operand_size (bytemode, sizeflag);
12815   append_seg ();
12816
12817   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12818     off = get32 ();
12819   else
12820     off = get16 ();
12821
12822   if (intel_syntax)
12823     {
12824       if (!active_seg_prefix)
12825         {
12826           oappend (names_seg[ds_reg - es_reg]);
12827           oappend (":");
12828         }
12829     }
12830   print_operand_value (scratchbuf, 1, off);
12831   oappend (scratchbuf);
12832 }
12833
12834 static void
12835 OP_OFF64 (int bytemode, int sizeflag)
12836 {
12837   bfd_vma off;
12838
12839   if (address_mode != mode_64bit
12840       || (prefixes & PREFIX_ADDR))
12841     {
12842       OP_OFF (bytemode, sizeflag);
12843       return;
12844     }
12845
12846   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12847     intel_operand_size (bytemode, sizeflag);
12848   append_seg ();
12849
12850   off = get64 ();
12851
12852   if (intel_syntax)
12853     {
12854       if (!active_seg_prefix)
12855         {
12856           oappend (names_seg[ds_reg - es_reg]);
12857           oappend (":");
12858         }
12859     }
12860   print_operand_value (scratchbuf, 1, off);
12861   oappend (scratchbuf);
12862 }
12863
12864 static void
12865 ptr_reg (int code, int sizeflag)
12866 {
12867   const char *s;
12868
12869   *obufp++ = open_char;
12870   used_prefixes |= (prefixes & PREFIX_ADDR);
12871   if (address_mode == mode_64bit)
12872     {
12873       if (!(sizeflag & AFLAG))
12874         s = names32[code - eAX_reg];
12875       else
12876         s = names64[code - eAX_reg];
12877     }
12878   else if (sizeflag & AFLAG)
12879     s = names32[code - eAX_reg];
12880   else
12881     s = names16[code - eAX_reg];
12882   oappend (s);
12883   *obufp++ = close_char;
12884   *obufp = 0;
12885 }
12886
12887 static void
12888 OP_ESreg (int code, int sizeflag)
12889 {
12890   if (intel_syntax)
12891     {
12892       switch (codep[-1])
12893         {
12894         case 0x6d:      /* insw/insl */
12895           intel_operand_size (z_mode, sizeflag);
12896           break;
12897         case 0xa5:      /* movsw/movsl/movsq */
12898         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12899         case 0xab:      /* stosw/stosl */
12900         case 0xaf:      /* scasw/scasl */
12901           intel_operand_size (v_mode, sizeflag);
12902           break;
12903         default:
12904           intel_operand_size (b_mode, sizeflag);
12905         }
12906     }
12907   oappend_maybe_intel ("%es:");
12908   ptr_reg (code, sizeflag);
12909 }
12910
12911 static void
12912 OP_DSreg (int code, int sizeflag)
12913 {
12914   if (intel_syntax)
12915     {
12916       switch (codep[-1])
12917         {
12918         case 0x6f:      /* outsw/outsl */
12919           intel_operand_size (z_mode, sizeflag);
12920           break;
12921         case 0xa5:      /* movsw/movsl/movsq */
12922         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12923         case 0xad:      /* lodsw/lodsl/lodsq */
12924           intel_operand_size (v_mode, sizeflag);
12925           break;
12926         default:
12927           intel_operand_size (b_mode, sizeflag);
12928         }
12929     }
12930   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12931      default segment register DS is printed.  */
12932   if (!active_seg_prefix)
12933     active_seg_prefix = PREFIX_DS;
12934   append_seg ();
12935   ptr_reg (code, sizeflag);
12936 }
12937
12938 static void
12939 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12940 {
12941   int add;
12942   if (rex & REX_R)
12943     {
12944       USED_REX (REX_R);
12945       add = 8;
12946     }
12947   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12948     {
12949       all_prefixes[last_lock_prefix] = 0;
12950       used_prefixes |= PREFIX_LOCK;
12951       add = 8;
12952     }
12953   else
12954     add = 0;
12955   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12956   oappend_maybe_intel (scratchbuf);
12957 }
12958
12959 static void
12960 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12961 {
12962   int add;
12963   USED_REX (REX_R);
12964   if (rex & REX_R)
12965     add = 8;
12966   else
12967     add = 0;
12968   if (intel_syntax)
12969     sprintf (scratchbuf, "dr%d", modrm.reg + add);
12970   else
12971     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12972   oappend (scratchbuf);
12973 }
12974
12975 static void
12976 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12977 {
12978   sprintf (scratchbuf, "%%tr%d", modrm.reg);
12979   oappend_maybe_intel (scratchbuf);
12980 }
12981
12982 static void
12983 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12984 {
12985   int reg = modrm.reg;
12986   const char **names;
12987
12988   used_prefixes |= (prefixes & PREFIX_DATA);
12989   if (prefixes & PREFIX_DATA)
12990     {
12991       names = names_xmm;
12992       USED_REX (REX_R);
12993       if (rex & REX_R)
12994         reg += 8;
12995     }
12996   else
12997     names = names_mm;
12998   oappend (names[reg]);
12999 }
13000
13001 static void
13002 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13003 {
13004   int reg = modrm.reg;
13005   const char **names;
13006
13007   USED_REX (REX_R);
13008   if (rex & REX_R)
13009     reg += 8;
13010   if (vex.evex)
13011     {
13012       if (!vex.r)
13013         reg += 16;
13014     }
13015
13016   if (need_vex
13017       && bytemode != xmm_mode
13018       && bytemode != xmmq_mode
13019       && bytemode != evex_half_bcst_xmmq_mode
13020       && bytemode != ymm_mode
13021       && bytemode != tmm_mode
13022       && bytemode != scalar_mode)
13023     {
13024       switch (vex.length)
13025         {
13026         case 128:
13027           names = names_xmm;
13028           break;
13029         case 256:
13030           if (vex.w
13031               || (bytemode != vex_vsib_q_w_dq_mode
13032                   && bytemode != vex_vsib_q_w_d_mode))
13033             names = names_ymm;
13034           else
13035             names = names_xmm;
13036           break;
13037         case 512:
13038           names = names_zmm;
13039           break;
13040         default:
13041           abort ();
13042         }
13043     }
13044   else if (bytemode == xmmq_mode
13045            || bytemode == evex_half_bcst_xmmq_mode)
13046     {
13047       switch (vex.length)
13048         {
13049         case 128:
13050         case 256:
13051           names = names_xmm;
13052           break;
13053         case 512:
13054           names = names_ymm;
13055           break;
13056         default:
13057           abort ();
13058         }
13059     }
13060   else if (bytemode == tmm_mode)
13061     {
13062       modrm.reg = reg;
13063       if (reg >= 8)
13064         {
13065           oappend ("(bad)");
13066           return;
13067         }
13068       names = names_tmm;
13069     }
13070   else if (bytemode == ymm_mode)
13071     names = names_ymm;
13072   else
13073     names = names_xmm;
13074   oappend (names[reg]);
13075 }
13076
13077 static void
13078 OP_EM (int bytemode, int sizeflag)
13079 {
13080   int reg;
13081   const char **names;
13082
13083   if (modrm.mod != 3)
13084     {
13085       if (intel_syntax
13086           && (bytemode == v_mode || bytemode == v_swap_mode))
13087         {
13088           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13089           used_prefixes |= (prefixes & PREFIX_DATA);
13090         }
13091       OP_E (bytemode, sizeflag);
13092       return;
13093     }
13094
13095   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13096     swap_operand ();
13097
13098   /* Skip mod/rm byte.  */
13099   MODRM_CHECK;
13100   codep++;
13101   used_prefixes |= (prefixes & PREFIX_DATA);
13102   reg = modrm.rm;
13103   if (prefixes & PREFIX_DATA)
13104     {
13105       names = names_xmm;
13106       USED_REX (REX_B);
13107       if (rex & REX_B)
13108         reg += 8;
13109     }
13110   else
13111     names = names_mm;
13112   oappend (names[reg]);
13113 }
13114
13115 /* cvt* are the only instructions in sse2 which have
13116    both SSE and MMX operands and also have 0x66 prefix
13117    in their opcode. 0x66 was originally used to differentiate
13118    between SSE and MMX instruction(operands). So we have to handle the
13119    cvt* separately using OP_EMC and OP_MXC */
13120 static void
13121 OP_EMC (int bytemode, int sizeflag)
13122 {
13123   if (modrm.mod != 3)
13124     {
13125       if (intel_syntax && bytemode == v_mode)
13126         {
13127           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13128           used_prefixes |= (prefixes & PREFIX_DATA);
13129         }
13130       OP_E (bytemode, sizeflag);
13131       return;
13132     }
13133
13134   /* Skip mod/rm byte.  */
13135   MODRM_CHECK;
13136   codep++;
13137   used_prefixes |= (prefixes & PREFIX_DATA);
13138   oappend (names_mm[modrm.rm]);
13139 }
13140
13141 static void
13142 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13143 {
13144   used_prefixes |= (prefixes & PREFIX_DATA);
13145   oappend (names_mm[modrm.reg]);
13146 }
13147
13148 static void
13149 OP_EX (int bytemode, int sizeflag)
13150 {
13151   int reg;
13152   const char **names;
13153
13154   /* Skip mod/rm byte.  */
13155   MODRM_CHECK;
13156   codep++;
13157
13158   if (modrm.mod != 3)
13159     {
13160       OP_E_memory (bytemode, sizeflag);
13161       return;
13162     }
13163
13164   reg = modrm.rm;
13165   USED_REX (REX_B);
13166   if (rex & REX_B)
13167     reg += 8;
13168   if (vex.evex)
13169     {
13170       USED_REX (REX_X);
13171       if ((rex & REX_X))
13172         reg += 16;
13173     }
13174
13175   if ((sizeflag & SUFFIX_ALWAYS)
13176       && (bytemode == x_swap_mode
13177           || bytemode == d_swap_mode
13178           || bytemode == q_swap_mode))
13179     swap_operand ();
13180
13181   if (need_vex
13182       && bytemode != xmm_mode
13183       && bytemode != xmmdw_mode
13184       && bytemode != xmmqd_mode
13185       && bytemode != xmm_mb_mode
13186       && bytemode != xmm_mw_mode
13187       && bytemode != xmm_md_mode
13188       && bytemode != xmm_mq_mode
13189       && bytemode != xmmq_mode
13190       && bytemode != evex_half_bcst_xmmq_mode
13191       && bytemode != ymm_mode
13192       && bytemode != tmm_mode
13193       && bytemode != vex_scalar_w_dq_mode)
13194     {
13195       switch (vex.length)
13196         {
13197         case 128:
13198           names = names_xmm;
13199           break;
13200         case 256:
13201           names = names_ymm;
13202           break;
13203         case 512:
13204           names = names_zmm;
13205           break;
13206         default:
13207           abort ();
13208         }
13209     }
13210   else if (bytemode == xmmq_mode
13211            || bytemode == evex_half_bcst_xmmq_mode)
13212     {
13213       switch (vex.length)
13214         {
13215         case 128:
13216         case 256:
13217           names = names_xmm;
13218           break;
13219         case 512:
13220           names = names_ymm;
13221           break;
13222         default:
13223           abort ();
13224         }
13225     }
13226   else if (bytemode == tmm_mode)
13227     {
13228       modrm.rm = reg;
13229       if (reg >= 8)
13230         {
13231           oappend ("(bad)");
13232           return;
13233         }
13234       names = names_tmm;
13235     }
13236   else if (bytemode == ymm_mode)
13237     names = names_ymm;
13238   else
13239     names = names_xmm;
13240   oappend (names[reg]);
13241 }
13242
13243 static void
13244 OP_MS (int bytemode, int sizeflag)
13245 {
13246   if (modrm.mod == 3)
13247     OP_EM (bytemode, sizeflag);
13248   else
13249     BadOp ();
13250 }
13251
13252 static void
13253 OP_XS (int bytemode, int sizeflag)
13254 {
13255   if (modrm.mod == 3)
13256     OP_EX (bytemode, sizeflag);
13257   else
13258     BadOp ();
13259 }
13260
13261 static void
13262 OP_M (int bytemode, int sizeflag)
13263 {
13264   if (modrm.mod == 3)
13265     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13266     BadOp ();
13267   else
13268     OP_E (bytemode, sizeflag);
13269 }
13270
13271 static void
13272 OP_0f07 (int bytemode, int sizeflag)
13273 {
13274   if (modrm.mod != 3 || modrm.rm != 0)
13275     BadOp ();
13276   else
13277     OP_E (bytemode, sizeflag);
13278 }
13279
13280 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13281    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
13282
13283 static void
13284 NOP_Fixup1 (int bytemode, int sizeflag)
13285 {
13286   if ((prefixes & PREFIX_DATA) != 0
13287       || (rex != 0
13288           && rex != 0x48
13289           && address_mode == mode_64bit))
13290     OP_REG (bytemode, sizeflag);
13291   else
13292     strcpy (obuf, "nop");
13293 }
13294
13295 static void
13296 NOP_Fixup2 (int bytemode, int sizeflag)
13297 {
13298   if ((prefixes & PREFIX_DATA) != 0
13299       || (rex != 0
13300           && rex != 0x48
13301           && address_mode == mode_64bit))
13302     OP_IMREG (bytemode, sizeflag);
13303 }
13304
13305 static const char *const Suffix3DNow[] = {
13306 /* 00 */        NULL,           NULL,           NULL,           NULL,
13307 /* 04 */        NULL,           NULL,           NULL,           NULL,
13308 /* 08 */        NULL,           NULL,           NULL,           NULL,
13309 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
13310 /* 10 */        NULL,           NULL,           NULL,           NULL,
13311 /* 14 */        NULL,           NULL,           NULL,           NULL,
13312 /* 18 */        NULL,           NULL,           NULL,           NULL,
13313 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
13314 /* 20 */        NULL,           NULL,           NULL,           NULL,
13315 /* 24 */        NULL,           NULL,           NULL,           NULL,
13316 /* 28 */        NULL,           NULL,           NULL,           NULL,
13317 /* 2C */        NULL,           NULL,           NULL,           NULL,
13318 /* 30 */        NULL,           NULL,           NULL,           NULL,
13319 /* 34 */        NULL,           NULL,           NULL,           NULL,
13320 /* 38 */        NULL,           NULL,           NULL,           NULL,
13321 /* 3C */        NULL,           NULL,           NULL,           NULL,
13322 /* 40 */        NULL,           NULL,           NULL,           NULL,
13323 /* 44 */        NULL,           NULL,           NULL,           NULL,
13324 /* 48 */        NULL,           NULL,           NULL,           NULL,
13325 /* 4C */        NULL,           NULL,           NULL,           NULL,
13326 /* 50 */        NULL,           NULL,           NULL,           NULL,
13327 /* 54 */        NULL,           NULL,           NULL,           NULL,
13328 /* 58 */        NULL,           NULL,           NULL,           NULL,
13329 /* 5C */        NULL,           NULL,           NULL,           NULL,
13330 /* 60 */        NULL,           NULL,           NULL,           NULL,
13331 /* 64 */        NULL,           NULL,           NULL,           NULL,
13332 /* 68 */        NULL,           NULL,           NULL,           NULL,
13333 /* 6C */        NULL,           NULL,           NULL,           NULL,
13334 /* 70 */        NULL,           NULL,           NULL,           NULL,
13335 /* 74 */        NULL,           NULL,           NULL,           NULL,
13336 /* 78 */        NULL,           NULL,           NULL,           NULL,
13337 /* 7C */        NULL,           NULL,           NULL,           NULL,
13338 /* 80 */        NULL,           NULL,           NULL,           NULL,
13339 /* 84 */        NULL,           NULL,           NULL,           NULL,
13340 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
13341 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
13342 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
13343 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
13344 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
13345 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
13346 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
13347 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
13348 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
13349 /* AC */        NULL,           NULL,           "pfacc",        NULL,
13350 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
13351 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
13352 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
13353 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
13354 /* C0 */        NULL,           NULL,           NULL,           NULL,
13355 /* C4 */        NULL,           NULL,           NULL,           NULL,
13356 /* C8 */        NULL,           NULL,           NULL,           NULL,
13357 /* CC */        NULL,           NULL,           NULL,           NULL,
13358 /* D0 */        NULL,           NULL,           NULL,           NULL,
13359 /* D4 */        NULL,           NULL,           NULL,           NULL,
13360 /* D8 */        NULL,           NULL,           NULL,           NULL,
13361 /* DC */        NULL,           NULL,           NULL,           NULL,
13362 /* E0 */        NULL,           NULL,           NULL,           NULL,
13363 /* E4 */        NULL,           NULL,           NULL,           NULL,
13364 /* E8 */        NULL,           NULL,           NULL,           NULL,
13365 /* EC */        NULL,           NULL,           NULL,           NULL,
13366 /* F0 */        NULL,           NULL,           NULL,           NULL,
13367 /* F4 */        NULL,           NULL,           NULL,           NULL,
13368 /* F8 */        NULL,           NULL,           NULL,           NULL,
13369 /* FC */        NULL,           NULL,           NULL,           NULL,
13370 };
13371
13372 static void
13373 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13374 {
13375   const char *mnemonic;
13376
13377   FETCH_DATA (the_info, codep + 1);
13378   /* AMD 3DNow! instructions are specified by an opcode suffix in the
13379      place where an 8-bit immediate would normally go.  ie. the last
13380      byte of the instruction.  */
13381   obufp = mnemonicendp;
13382   mnemonic = Suffix3DNow[*codep++ & 0xff];
13383   if (mnemonic)
13384     oappend (mnemonic);
13385   else
13386     {
13387       /* Since a variable sized modrm/sib chunk is between the start
13388          of the opcode (0x0f0f) and the opcode suffix, we need to do
13389          all the modrm processing first, and don't know until now that
13390          we have a bad opcode.  This necessitates some cleaning up.  */
13391       op_out[0][0] = '\0';
13392       op_out[1][0] = '\0';
13393       BadOp ();
13394     }
13395   mnemonicendp = obufp;
13396 }
13397
13398 static const struct op simd_cmp_op[] =
13399 {
13400   { STRING_COMMA_LEN ("eq") },
13401   { STRING_COMMA_LEN ("lt") },
13402   { STRING_COMMA_LEN ("le") },
13403   { STRING_COMMA_LEN ("unord") },
13404   { STRING_COMMA_LEN ("neq") },
13405   { STRING_COMMA_LEN ("nlt") },
13406   { STRING_COMMA_LEN ("nle") },
13407   { STRING_COMMA_LEN ("ord") }
13408 };
13409
13410 static const struct op vex_cmp_op[] =
13411 {
13412   { STRING_COMMA_LEN ("eq_uq") },
13413   { STRING_COMMA_LEN ("nge") },
13414   { STRING_COMMA_LEN ("ngt") },
13415   { STRING_COMMA_LEN ("false") },
13416   { STRING_COMMA_LEN ("neq_oq") },
13417   { STRING_COMMA_LEN ("ge") },
13418   { STRING_COMMA_LEN ("gt") },
13419   { STRING_COMMA_LEN ("true") },
13420   { STRING_COMMA_LEN ("eq_os") },
13421   { STRING_COMMA_LEN ("lt_oq") },
13422   { STRING_COMMA_LEN ("le_oq") },
13423   { STRING_COMMA_LEN ("unord_s") },
13424   { STRING_COMMA_LEN ("neq_us") },
13425   { STRING_COMMA_LEN ("nlt_uq") },
13426   { STRING_COMMA_LEN ("nle_uq") },
13427   { STRING_COMMA_LEN ("ord_s") },
13428   { STRING_COMMA_LEN ("eq_us") },
13429   { STRING_COMMA_LEN ("nge_uq") },
13430   { STRING_COMMA_LEN ("ngt_uq") },
13431   { STRING_COMMA_LEN ("false_os") },
13432   { STRING_COMMA_LEN ("neq_os") },
13433   { STRING_COMMA_LEN ("ge_oq") },
13434   { STRING_COMMA_LEN ("gt_oq") },
13435   { STRING_COMMA_LEN ("true_us") },
13436 };
13437
13438 static void
13439 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13440 {
13441   unsigned int cmp_type;
13442
13443   FETCH_DATA (the_info, codep + 1);
13444   cmp_type = *codep++ & 0xff;
13445   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13446     {
13447       char suffix [3];
13448       char *p = mnemonicendp - 2;
13449       suffix[0] = p[0];
13450       suffix[1] = p[1];
13451       suffix[2] = '\0';
13452       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13453       mnemonicendp += simd_cmp_op[cmp_type].len;
13454     }
13455   else if (need_vex
13456            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13457     {
13458       char suffix [3];
13459       char *p = mnemonicendp - 2;
13460       suffix[0] = p[0];
13461       suffix[1] = p[1];
13462       suffix[2] = '\0';
13463       cmp_type -= ARRAY_SIZE (simd_cmp_op);
13464       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13465       mnemonicendp += vex_cmp_op[cmp_type].len;
13466     }
13467   else
13468     {
13469       /* We have a reserved extension byte.  Output it directly.  */
13470       scratchbuf[0] = '$';
13471       print_operand_value (scratchbuf + 1, 1, cmp_type);
13472       oappend_maybe_intel (scratchbuf);
13473       scratchbuf[0] = '\0';
13474     }
13475 }
13476
13477 static void
13478 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13479 {
13480   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13481   if (!intel_syntax)
13482     {
13483       strcpy (op_out[0], names32[0]);
13484       strcpy (op_out[1], names32[1]);
13485       if (bytemode == eBX_reg)
13486         strcpy (op_out[2], names32[3]);
13487       two_source_ops = 1;
13488     }
13489   /* Skip mod/rm byte.  */
13490   MODRM_CHECK;
13491   codep++;
13492 }
13493
13494 static void
13495 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13496             int sizeflag ATTRIBUTE_UNUSED)
13497 {
13498   /* monitor %{e,r,}ax,%ecx,%edx"  */
13499   if (!intel_syntax)
13500     {
13501       const char **names = (address_mode == mode_64bit
13502                             ? names64 : names32);
13503
13504       if (prefixes & PREFIX_ADDR)
13505         {
13506           /* Remove "addr16/addr32".  */
13507           all_prefixes[last_addr_prefix] = 0;
13508           names = (address_mode != mode_32bit
13509                    ? names32 : names16);
13510           used_prefixes |= PREFIX_ADDR;
13511         }
13512       else if (address_mode == mode_16bit)
13513         names = names16;
13514       strcpy (op_out[0], names[0]);
13515       strcpy (op_out[1], names32[1]);
13516       strcpy (op_out[2], names32[2]);
13517       two_source_ops = 1;
13518     }
13519   /* Skip mod/rm byte.  */
13520   MODRM_CHECK;
13521   codep++;
13522 }
13523
13524 static void
13525 BadOp (void)
13526 {
13527   /* Throw away prefixes and 1st. opcode byte.  */
13528   codep = insn_codep + 1;
13529   oappend ("(bad)");
13530 }
13531
13532 static void
13533 REP_Fixup (int bytemode, int sizeflag)
13534 {
13535   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13536      lods and stos.  */
13537   if (prefixes & PREFIX_REPZ)
13538     all_prefixes[last_repz_prefix] = REP_PREFIX;
13539
13540   switch (bytemode)
13541     {
13542     case al_reg:
13543     case eAX_reg:
13544     case indir_dx_reg:
13545       OP_IMREG (bytemode, sizeflag);
13546       break;
13547     case eDI_reg:
13548       OP_ESreg (bytemode, sizeflag);
13549       break;
13550     case eSI_reg:
13551       OP_DSreg (bytemode, sizeflag);
13552       break;
13553     default:
13554       abort ();
13555       break;
13556     }
13557 }
13558
13559 static void
13560 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13561 {
13562   if ( isa64 != amd64 )
13563     return;
13564
13565   obufp = obuf;
13566   BadOp ();
13567   mnemonicendp = obufp;
13568   ++codep;
13569 }
13570
13571 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13572    "bnd".  */
13573
13574 static void
13575 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13576 {
13577   if (prefixes & PREFIX_REPNZ)
13578     all_prefixes[last_repnz_prefix] = BND_PREFIX;
13579 }
13580
13581 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13582    "notrack".  */
13583
13584 static void
13585 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
13586                int sizeflag ATTRIBUTE_UNUSED)
13587 {
13588   if (active_seg_prefix == PREFIX_DS
13589       && (address_mode != mode_64bit || last_data_prefix < 0))
13590     {
13591       /* NOTRACK prefix is only valid on indirect branch instructions.
13592          NB: DATA prefix is unsupported for Intel64.  */
13593       active_seg_prefix = 0;
13594       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
13595     }
13596 }
13597
13598 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
13599    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13600  */
13601
13602 static void
13603 HLE_Fixup1 (int bytemode, int sizeflag)
13604 {
13605   if (modrm.mod != 3
13606       && (prefixes & PREFIX_LOCK) != 0)
13607     {
13608       if (prefixes & PREFIX_REPZ)
13609         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13610       if (prefixes & PREFIX_REPNZ)
13611         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13612     }
13613
13614   OP_E (bytemode, sizeflag);
13615 }
13616
13617 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
13618    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13619  */
13620
13621 static void
13622 HLE_Fixup2 (int bytemode, int sizeflag)
13623 {
13624   if (modrm.mod != 3)
13625     {
13626       if (prefixes & PREFIX_REPZ)
13627         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13628       if (prefixes & PREFIX_REPNZ)
13629         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13630     }
13631
13632   OP_E (bytemode, sizeflag);
13633 }
13634
13635 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13636    "xrelease" for memory operand.  No check for LOCK prefix.   */
13637
13638 static void
13639 HLE_Fixup3 (int bytemode, int sizeflag)
13640 {
13641   if (modrm.mod != 3
13642       && last_repz_prefix > last_repnz_prefix
13643       && (prefixes & PREFIX_REPZ) != 0)
13644     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13645
13646   OP_E (bytemode, sizeflag);
13647 }
13648
13649 static void
13650 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13651 {
13652   USED_REX (REX_W);
13653   if (rex & REX_W)
13654     {
13655       /* Change cmpxchg8b to cmpxchg16b.  */
13656       char *p = mnemonicendp - 2;
13657       mnemonicendp = stpcpy (p, "16b");
13658       bytemode = o_mode;
13659     }
13660   else if ((prefixes & PREFIX_LOCK) != 0)
13661     {
13662       if (prefixes & PREFIX_REPZ)
13663         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13664       if (prefixes & PREFIX_REPNZ)
13665         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13666     }
13667
13668   OP_M (bytemode, sizeflag);
13669 }
13670
13671 static void
13672 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13673 {
13674   const char **names;
13675
13676   if (need_vex)
13677     {
13678       switch (vex.length)
13679         {
13680         case 128:
13681           names = names_xmm;
13682           break;
13683         case 256:
13684           names = names_ymm;
13685           break;
13686         default:
13687           abort ();
13688         }
13689     }
13690   else
13691     names = names_xmm;
13692   oappend (names[reg]);
13693 }
13694
13695 static void
13696 FXSAVE_Fixup (int bytemode, int sizeflag)
13697 {
13698   /* Add proper suffix to "fxsave" and "fxrstor".  */
13699   USED_REX (REX_W);
13700   if (rex & REX_W)
13701     {
13702       char *p = mnemonicendp;
13703       *p++ = '6';
13704       *p++ = '4';
13705       *p = '\0';
13706       mnemonicendp = p;
13707     }
13708   OP_M (bytemode, sizeflag);
13709 }
13710
13711 /* Display the destination register operand for instructions with
13712    VEX. */
13713
13714 static void
13715 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13716 {
13717   int reg;
13718   const char **names;
13719
13720   if (!need_vex)
13721     abort ();
13722
13723   reg = vex.register_specifier;
13724   vex.register_specifier = 0;
13725   if (address_mode != mode_64bit)
13726     reg &= 7;
13727   else if (vex.evex && !vex.v)
13728     reg += 16;
13729
13730   if (bytemode == vex_scalar_mode)
13731     {
13732       oappend (names_xmm[reg]);
13733       return;
13734     }
13735
13736   if (bytemode == tmm_mode)
13737     {
13738       /* All 3 TMM registers must be distinct.  */
13739       if (reg >= 8)
13740         oappend ("(bad)");
13741       else
13742         {
13743           /* This must be the 3rd operand.  */
13744           if (obufp != op_out[2])
13745             abort ();
13746           oappend (names_tmm[reg]);
13747           if (reg == modrm.reg || reg == modrm.rm)
13748             strcpy (obufp, "/(bad)");
13749         }
13750
13751       if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
13752         {
13753           if (modrm.reg <= 8
13754               && (modrm.reg == modrm.rm || modrm.reg == reg))
13755             strcat (op_out[0], "/(bad)");
13756           if (modrm.rm <= 8
13757               && (modrm.rm == modrm.reg || modrm.rm == reg))
13758             strcat (op_out[1], "/(bad)");
13759         }
13760
13761       return;
13762     }
13763
13764   switch (vex.length)
13765     {
13766     case 128:
13767       switch (bytemode)
13768         {
13769         case vex_mode:
13770         case vex_vsib_q_w_dq_mode:
13771         case vex_vsib_q_w_d_mode:
13772           names = names_xmm;
13773           break;
13774         case dq_mode:
13775           if (rex & REX_W)
13776             names = names64;
13777           else
13778             names = names32;
13779           break;
13780         case mask_bd_mode:
13781         case mask_mode:
13782           if (reg > 0x7)
13783             {
13784               oappend ("(bad)");
13785               return;
13786             }
13787           names = names_mask;
13788           break;
13789         default:
13790           abort ();
13791           return;
13792         }
13793       break;
13794     case 256:
13795       switch (bytemode)
13796         {
13797         case vex_mode:
13798           names = names_ymm;
13799           break;
13800         case vex_vsib_q_w_dq_mode:
13801         case vex_vsib_q_w_d_mode:
13802           names = vex.w ? names_ymm : names_xmm;
13803           break;
13804         case mask_bd_mode:
13805         case mask_mode:
13806           if (reg > 0x7)
13807             {
13808               oappend ("(bad)");
13809               return;
13810             }
13811           names = names_mask;
13812           break;
13813         default:
13814           /* See PR binutils/20893 for a reproducer.  */
13815           oappend ("(bad)");
13816           return;
13817         }
13818       break;
13819     case 512:
13820       names = names_zmm;
13821       break;
13822     default:
13823       abort ();
13824       break;
13825     }
13826   oappend (names[reg]);
13827 }
13828
13829 static void
13830 OP_VexR (int bytemode, int sizeflag)
13831 {
13832   if (modrm.mod == 3)
13833     OP_VEX (bytemode, sizeflag);
13834 }
13835
13836 static void
13837 OP_VexW (int bytemode, int sizeflag)
13838 {
13839   OP_VEX (bytemode, sizeflag);
13840
13841   if (vex.w)
13842     {
13843       /* Swap 2nd and 3rd operands.  */
13844       strcpy (scratchbuf, op_out[2]);
13845       strcpy (op_out[2], op_out[1]);
13846       strcpy (op_out[1], scratchbuf);
13847     }
13848 }
13849
13850 static void
13851 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13852 {
13853   int reg;
13854   const char **names = names_xmm;
13855
13856   FETCH_DATA (the_info, codep + 1);
13857   reg = *codep++;
13858
13859   if (bytemode != x_mode && bytemode != scalar_mode)
13860     abort ();
13861
13862   reg >>= 4;
13863   if (address_mode != mode_64bit)
13864     reg &= 7;
13865
13866   if (bytemode == x_mode && vex.length == 256)
13867     names = names_ymm;
13868
13869   oappend (names[reg]);
13870
13871   if (vex.w)
13872     {
13873       /* Swap 3rd and 4th operands.  */
13874       strcpy (scratchbuf, op_out[3]);
13875       strcpy (op_out[3], op_out[2]);
13876       strcpy (op_out[2], scratchbuf);
13877     }
13878 }
13879
13880 static void
13881 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
13882           int sizeflag ATTRIBUTE_UNUSED)
13883 {
13884   scratchbuf[0] = '$';
13885   print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
13886   oappend_maybe_intel (scratchbuf);
13887 }
13888
13889 static void
13890 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
13891              int sizeflag ATTRIBUTE_UNUSED)
13892 {
13893   unsigned int cmp_type;
13894
13895   if (!vex.evex)
13896     abort ();
13897
13898   FETCH_DATA (the_info, codep + 1);
13899   cmp_type = *codep++ & 0xff;
13900   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13901      If it's the case, print suffix, otherwise - print the immediate.  */
13902   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13903       && cmp_type != 3
13904       && cmp_type != 7)
13905     {
13906       char suffix [3];
13907       char *p = mnemonicendp - 2;
13908
13909       /* vpcmp* can have both one- and two-lettered suffix.  */
13910       if (p[0] == 'p')
13911         {
13912           p++;
13913           suffix[0] = p[0];
13914           suffix[1] = '\0';
13915         }
13916       else
13917         {
13918           suffix[0] = p[0];
13919           suffix[1] = p[1];
13920           suffix[2] = '\0';
13921         }
13922
13923       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13924       mnemonicendp += simd_cmp_op[cmp_type].len;
13925     }
13926   else
13927     {
13928       /* We have a reserved extension byte.  Output it directly.  */
13929       scratchbuf[0] = '$';
13930       print_operand_value (scratchbuf + 1, 1, cmp_type);
13931       oappend_maybe_intel (scratchbuf);
13932       scratchbuf[0] = '\0';
13933     }
13934 }
13935
13936 static const struct op xop_cmp_op[] =
13937 {
13938   { STRING_COMMA_LEN ("lt") },
13939   { STRING_COMMA_LEN ("le") },
13940   { STRING_COMMA_LEN ("gt") },
13941   { STRING_COMMA_LEN ("ge") },
13942   { STRING_COMMA_LEN ("eq") },
13943   { STRING_COMMA_LEN ("neq") },
13944   { STRING_COMMA_LEN ("false") },
13945   { STRING_COMMA_LEN ("true") }
13946 };
13947
13948 static void
13949 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
13950              int sizeflag ATTRIBUTE_UNUSED)
13951 {
13952   unsigned int cmp_type;
13953
13954   FETCH_DATA (the_info, codep + 1);
13955   cmp_type = *codep++ & 0xff;
13956   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13957     {
13958       char suffix[3];
13959       char *p = mnemonicendp - 2;
13960
13961       /* vpcom* can have both one- and two-lettered suffix.  */
13962       if (p[0] == 'm')
13963         {
13964           p++;
13965           suffix[0] = p[0];
13966           suffix[1] = '\0';
13967         }
13968       else
13969         {
13970           suffix[0] = p[0];
13971           suffix[1] = p[1];
13972           suffix[2] = '\0';
13973         }
13974
13975       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13976       mnemonicendp += xop_cmp_op[cmp_type].len;
13977     }
13978   else
13979     {
13980       /* We have a reserved extension byte.  Output it directly.  */
13981       scratchbuf[0] = '$';
13982       print_operand_value (scratchbuf + 1, 1, cmp_type);
13983       oappend_maybe_intel (scratchbuf);
13984       scratchbuf[0] = '\0';
13985     }
13986 }
13987
13988 static const struct op pclmul_op[] =
13989 {
13990   { STRING_COMMA_LEN ("lql") },
13991   { STRING_COMMA_LEN ("hql") },
13992   { STRING_COMMA_LEN ("lqh") },
13993   { STRING_COMMA_LEN ("hqh") }
13994 };
13995
13996 static void
13997 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13998               int sizeflag ATTRIBUTE_UNUSED)
13999 {
14000   unsigned int pclmul_type;
14001
14002   FETCH_DATA (the_info, codep + 1);
14003   pclmul_type = *codep++ & 0xff;
14004   switch (pclmul_type)
14005     {
14006     case 0x10:
14007       pclmul_type = 2;
14008       break;
14009     case 0x11:
14010       pclmul_type = 3;
14011       break;
14012     default:
14013       break;
14014     }
14015   if (pclmul_type < ARRAY_SIZE (pclmul_op))
14016     {
14017       char suffix [4];
14018       char *p = mnemonicendp - 3;
14019       suffix[0] = p[0];
14020       suffix[1] = p[1];
14021       suffix[2] = p[2];
14022       suffix[3] = '\0';
14023       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14024       mnemonicendp += pclmul_op[pclmul_type].len;
14025     }
14026   else
14027     {
14028       /* We have a reserved extension byte.  Output it directly.  */
14029       scratchbuf[0] = '$';
14030       print_operand_value (scratchbuf + 1, 1, pclmul_type);
14031       oappend_maybe_intel (scratchbuf);
14032       scratchbuf[0] = '\0';
14033     }
14034 }
14035
14036 static void
14037 MOVSXD_Fixup (int bytemode, int sizeflag)
14038 {
14039   /* Add proper suffix to "movsxd".  */
14040   char *p = mnemonicendp;
14041
14042   switch (bytemode)
14043     {
14044     case movsxd_mode:
14045       if (intel_syntax)
14046         {
14047           *p++ = 'x';
14048           *p++ = 'd';
14049           goto skip;
14050         }
14051
14052       USED_REX (REX_W);
14053       if (rex & REX_W)
14054         {
14055           *p++ = 'l';
14056           *p++ = 'q';
14057         }
14058       else
14059         {
14060           *p++ = 'x';
14061           *p++ = 'd';
14062         }
14063       break;
14064     default:
14065       oappend (INTERNAL_DISASSEMBLER_ERROR);
14066       break;
14067     }
14068
14069  skip:
14070   mnemonicendp = p;
14071   *p = '\0';
14072   OP_E (bytemode, sizeflag);
14073 }
14074
14075 static void
14076 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14077 {
14078   if (!vex.evex
14079       || (bytemode != mask_mode && bytemode != mask_bd_mode))
14080     abort ();
14081
14082   USED_REX (REX_R);
14083   if ((rex & REX_R) != 0 || !vex.r)
14084     {
14085       BadOp ();
14086       return;
14087     }
14088
14089   oappend (names_mask [modrm.reg]);
14090 }
14091
14092 static void
14093 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14094 {
14095   if (modrm.mod == 3 && vex.b)
14096     switch (bytemode)
14097       {
14098       case evex_rounding_64_mode:
14099         if (address_mode != mode_64bit)
14100           {
14101             oappend ("(bad)");
14102             break;
14103           }
14104         /* Fall through.  */
14105       case evex_rounding_mode:
14106         oappend (names_rounding[vex.ll]);
14107         break;
14108       case evex_sae_mode:
14109         oappend ("{sae}");
14110         break;
14111       default:
14112         abort ();
14113         break;
14114       }
14115 }