1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2016 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void OP_LWPCB_E (int, int);
121 static void OP_LWP_E (int, int);
122 static void OP_Vex_2src_1 (int, int);
123 static void OP_Vex_2src_2 (int, int);
125 static void MOVBE_Fixup (int, int);
127 static void OP_Mask (int, int);
130 /* Points to first byte not fetched. */
131 bfd_byte
*max_fetched
;
132 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
135 OPCODES_SIGJMP_BUF bailout
;
145 enum address_mode address_mode
;
147 /* Flags for the prefixes for the current instruction. See below. */
150 /* REX prefix the current instruction. See below. */
152 /* Bits of REX we've already used. */
154 /* REX bits in original REX prefix ignored. */
155 static int rex_ignored
;
156 /* Mark parts used in the REX prefix. When we are testing for
157 empty prefix (for 8bit register REX extension), just mask it
158 out. Otherwise test for REX bit is excuse for existence of REX
159 only in case value is nonzero. */
160 #define USED_REX(value) \
165 rex_used |= (value) | REX_OPCODE; \
168 rex_used |= REX_OPCODE; \
171 /* Flags for prefixes which we somehow handled when printing the
172 current instruction. */
173 static int used_prefixes
;
175 /* Flags stored in PREFIXES. */
176 #define PREFIX_REPZ 1
177 #define PREFIX_REPNZ 2
178 #define PREFIX_LOCK 4
180 #define PREFIX_SS 0x10
181 #define PREFIX_DS 0x20
182 #define PREFIX_ES 0x40
183 #define PREFIX_FS 0x80
184 #define PREFIX_GS 0x100
185 #define PREFIX_DATA 0x200
186 #define PREFIX_ADDR 0x400
187 #define PREFIX_FWAIT 0x800
189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
190 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
192 #define FETCH_DATA(info, addr) \
193 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
194 ? 1 : fetch_data ((info), (addr)))
197 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
200 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
201 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
203 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
204 status
= (*info
->read_memory_func
) (start
,
206 addr
- priv
->max_fetched
,
212 /* If we did manage to read at least one byte, then
213 print_insn_i386 will do something sensible. Otherwise, print
214 an error. We do that here because this is where we know
216 if (priv
->max_fetched
== priv
->the_buffer
)
217 (*info
->memory_error_func
) (status
, start
, info
);
218 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
221 priv
->max_fetched
= addr
;
225 /* Possible values for prefix requirement. */
226 #define PREFIX_IGNORED_SHIFT 16
227 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
228 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
233 /* Opcode prefixes. */
234 #define PREFIX_OPCODE (PREFIX_REPZ \
238 /* Prefixes ignored. */
239 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
240 | PREFIX_IGNORED_REPNZ \
241 | PREFIX_IGNORED_DATA)
243 #define XX { NULL, 0 }
244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
246 #define Eb { OP_E, b_mode }
247 #define Ebnd { OP_E, bnd_mode }
248 #define EbS { OP_E, b_swap_mode }
249 #define Ev { OP_E, v_mode }
250 #define Ev_bnd { OP_E, v_bnd_mode }
251 #define EvS { OP_E, v_swap_mode }
252 #define Ed { OP_E, d_mode }
253 #define Edq { OP_E, dq_mode }
254 #define Edqw { OP_E, dqw_mode }
255 #define EdqwS { OP_E, dqw_swap_mode }
256 #define Edqb { OP_E, dqb_mode }
257 #define Edb { OP_E, db_mode }
258 #define Edw { OP_E, dw_mode }
259 #define Edqd { OP_E, dqd_mode }
260 #define Eq { OP_E, q_mode }
261 #define indirEv { OP_indirE, indir_v_mode }
262 #define indirEp { OP_indirE, f_mode }
263 #define stackEv { OP_E, stack_v_mode }
264 #define Em { OP_E, m_mode }
265 #define Ew { OP_E, w_mode }
266 #define M { OP_M, 0 } /* lea, lgdt, etc. */
267 #define Ma { OP_M, a_mode }
268 #define Mb { OP_M, b_mode }
269 #define Md { OP_M, d_mode }
270 #define Mo { OP_M, o_mode }
271 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
272 #define Mq { OP_M, q_mode }
273 #define Mx { OP_M, x_mode }
274 #define Mxmm { OP_M, xmm_mode }
275 #define Gb { OP_G, b_mode }
276 #define Gbnd { OP_G, bnd_mode }
277 #define Gv { OP_G, v_mode }
278 #define Gd { OP_G, d_mode }
279 #define Gdq { OP_G, dq_mode }
280 #define Gm { OP_G, m_mode }
281 #define Gw { OP_G, w_mode }
282 #define Rd { OP_R, d_mode }
283 #define Rdq { OP_R, dq_mode }
284 #define Rm { OP_R, m_mode }
285 #define Ib { OP_I, b_mode }
286 #define sIb { OP_sI, b_mode } /* sign extened byte */
287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
288 #define Iv { OP_I, v_mode }
289 #define sIv { OP_sI, v_mode }
290 #define Iq { OP_I, q_mode }
291 #define Iv64 { OP_I64, v_mode }
292 #define Iw { OP_I, w_mode }
293 #define I1 { OP_I, const_1_mode }
294 #define Jb { OP_J, b_mode }
295 #define Jv { OP_J, v_mode }
296 #define Cm { OP_C, m_mode }
297 #define Dm { OP_D, m_mode }
298 #define Td { OP_T, d_mode }
299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
301 #define RMeAX { OP_REG, eAX_reg }
302 #define RMeBX { OP_REG, eBX_reg }
303 #define RMeCX { OP_REG, eCX_reg }
304 #define RMeDX { OP_REG, eDX_reg }
305 #define RMeSP { OP_REG, eSP_reg }
306 #define RMeBP { OP_REG, eBP_reg }
307 #define RMeSI { OP_REG, eSI_reg }
308 #define RMeDI { OP_REG, eDI_reg }
309 #define RMrAX { OP_REG, rAX_reg }
310 #define RMrBX { OP_REG, rBX_reg }
311 #define RMrCX { OP_REG, rCX_reg }
312 #define RMrDX { OP_REG, rDX_reg }
313 #define RMrSP { OP_REG, rSP_reg }
314 #define RMrBP { OP_REG, rBP_reg }
315 #define RMrSI { OP_REG, rSI_reg }
316 #define RMrDI { OP_REG, rDI_reg }
317 #define RMAL { OP_REG, al_reg }
318 #define RMCL { OP_REG, cl_reg }
319 #define RMDL { OP_REG, dl_reg }
320 #define RMBL { OP_REG, bl_reg }
321 #define RMAH { OP_REG, ah_reg }
322 #define RMCH { OP_REG, ch_reg }
323 #define RMDH { OP_REG, dh_reg }
324 #define RMBH { OP_REG, bh_reg }
325 #define RMAX { OP_REG, ax_reg }
326 #define RMDX { OP_REG, dx_reg }
328 #define eAX { OP_IMREG, eAX_reg }
329 #define eBX { OP_IMREG, eBX_reg }
330 #define eCX { OP_IMREG, eCX_reg }
331 #define eDX { OP_IMREG, eDX_reg }
332 #define eSP { OP_IMREG, eSP_reg }
333 #define eBP { OP_IMREG, eBP_reg }
334 #define eSI { OP_IMREG, eSI_reg }
335 #define eDI { OP_IMREG, eDI_reg }
336 #define AL { OP_IMREG, al_reg }
337 #define CL { OP_IMREG, cl_reg }
338 #define DL { OP_IMREG, dl_reg }
339 #define BL { OP_IMREG, bl_reg }
340 #define AH { OP_IMREG, ah_reg }
341 #define CH { OP_IMREG, ch_reg }
342 #define DH { OP_IMREG, dh_reg }
343 #define BH { OP_IMREG, bh_reg }
344 #define AX { OP_IMREG, ax_reg }
345 #define DX { OP_IMREG, dx_reg }
346 #define zAX { OP_IMREG, z_mode_ax_reg }
347 #define indirDX { OP_IMREG, indir_dx_reg }
349 #define Sw { OP_SEG, w_mode }
350 #define Sv { OP_SEG, v_mode }
351 #define Ap { OP_DIR, 0 }
352 #define Ob { OP_OFF64, b_mode }
353 #define Ov { OP_OFF64, v_mode }
354 #define Xb { OP_DSreg, eSI_reg }
355 #define Xv { OP_DSreg, eSI_reg }
356 #define Xz { OP_DSreg, eSI_reg }
357 #define Yb { OP_ESreg, eDI_reg }
358 #define Yv { OP_ESreg, eDI_reg }
359 #define DSBX { OP_DSreg, eBX_reg }
361 #define es { OP_REG, es_reg }
362 #define ss { OP_REG, ss_reg }
363 #define cs { OP_REG, cs_reg }
364 #define ds { OP_REG, ds_reg }
365 #define fs { OP_REG, fs_reg }
366 #define gs { OP_REG, gs_reg }
368 #define MX { OP_MMX, 0 }
369 #define XM { OP_XMM, 0 }
370 #define XMScalar { OP_XMM, scalar_mode }
371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
372 #define XMM { OP_XMM, xmm_mode }
373 #define XMxmmq { OP_XMM, xmmq_mode }
374 #define EM { OP_EM, v_mode }
375 #define EMS { OP_EM, v_swap_mode }
376 #define EMd { OP_EM, d_mode }
377 #define EMx { OP_EM, x_mode }
378 #define EXw { OP_EX, w_mode }
379 #define EXd { OP_EX, d_mode }
380 #define EXdScalar { OP_EX, d_scalar_mode }
381 #define EXdS { OP_EX, d_swap_mode }
382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
383 #define EXq { OP_EX, q_mode }
384 #define EXqScalar { OP_EX, q_scalar_mode }
385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
386 #define EXqS { OP_EX, q_swap_mode }
387 #define EXx { OP_EX, x_mode }
388 #define EXxS { OP_EX, x_swap_mode }
389 #define EXxmm { OP_EX, xmm_mode }
390 #define EXymm { OP_EX, ymm_mode }
391 #define EXxmmq { OP_EX, xmmq_mode }
392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
395 #define EXxmm_md { OP_EX, xmm_md_mode }
396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
398 #define EXxmmdw { OP_EX, xmmdw_mode }
399 #define EXxmmqd { OP_EX, xmmqd_mode }
400 #define EXymmq { OP_EX, ymmq_mode }
401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
405 #define MS { OP_MS, v_mode }
406 #define XS { OP_XS, v_mode }
407 #define EMCq { OP_EMC, q_mode }
408 #define MXC { OP_MXC, 0 }
409 #define OPSUF { OP_3DNowSuffix, 0 }
410 #define CMP { CMP_Fixup, 0 }
411 #define XMM0 { XMM_Fixup, 0 }
412 #define FXSAVE { FXSAVE_Fixup, 0 }
413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
416 #define Vex { OP_VEX, vex_mode }
417 #define VexScalar { OP_VEX, vex_scalar_mode }
418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
419 #define Vex128 { OP_VEX, vex128_mode }
420 #define Vex256 { OP_VEX, vex256_mode }
421 #define VexGdq { OP_VEX, dq_mode }
422 #define VexI4 { VEXI4_Fixup, 0}
423 #define EXdVex { OP_EX_Vex, d_mode }
424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
426 #define EXqVex { OP_EX_Vex, q_mode }
427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
429 #define EXVexW { OP_EX_VexW, x_mode }
430 #define EXdVexW { OP_EX_VexW, d_mode }
431 #define EXqVexW { OP_EX_VexW, q_mode }
432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
433 #define XMVex { OP_XMM_Vex, 0 }
434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
435 #define XMVexW { OP_XMM_VexW, 0 }
436 #define XMVexI4 { OP_REG_VexI4, x_mode }
437 #define PCLMUL { PCLMUL_Fixup, 0 }
438 #define VZERO { VZERO_Fixup, 0 }
439 #define VCMP { VCMP_Fixup, 0 }
440 #define VPCMP { VPCMP_Fixup, 0 }
442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
445 #define XMask { OP_Mask, mask_mode }
446 #define MaskG { OP_G, mask_mode }
447 #define MaskE { OP_E, mask_mode }
448 #define MaskBDE { OP_E, mask_bd_mode }
449 #define MaskR { OP_R, mask_mode }
450 #define MaskVex { OP_VEX, mask_mode }
452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
457 /* Used handle "rep" prefix for string instructions. */
458 #define Xbr { REP_Fixup, eSI_reg }
459 #define Xvr { REP_Fixup, eSI_reg }
460 #define Ybr { REP_Fixup, eDI_reg }
461 #define Yvr { REP_Fixup, eDI_reg }
462 #define Yzr { REP_Fixup, eDI_reg }
463 #define indirDXr { REP_Fixup, indir_dx_reg }
464 #define ALr { REP_Fixup, al_reg }
465 #define eAXr { REP_Fixup, eAX_reg }
467 /* Used handle HLE prefix for lockable instructions. */
468 #define Ebh1 { HLE_Fixup1, b_mode }
469 #define Evh1 { HLE_Fixup1, v_mode }
470 #define Ebh2 { HLE_Fixup2, b_mode }
471 #define Evh2 { HLE_Fixup2, v_mode }
472 #define Ebh3 { HLE_Fixup3, b_mode }
473 #define Evh3 { HLE_Fixup3, v_mode }
475 #define BND { BND_Fixup, 0 }
477 #define cond_jump_flag { NULL, cond_jump_mode }
478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
480 /* bits in sizeflag */
481 #define SUFFIX_ALWAYS 4
489 /* byte operand with operand swapped */
491 /* byte operand, sign extend like 'T' suffix */
493 /* operand size depends on prefixes */
495 /* operand size depends on prefixes with operand swapped */
499 /* double word operand */
501 /* double word operand with operand swapped */
503 /* quad word operand */
505 /* quad word operand with operand swapped */
507 /* ten-byte operand */
509 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
510 broadcast enabled. */
512 /* Similar to x_mode, but with different EVEX mem shifts. */
514 /* Similar to x_mode, but with disabled broadcast. */
516 /* Similar to x_mode, but with operands swapped and disabled broadcast
519 /* 16-byte XMM operand */
521 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
522 memory operand (depending on vector length). Broadcast isn't
525 /* Same as xmmq_mode, but broadcast is allowed. */
526 evex_half_bcst_xmmq_mode
,
527 /* XMM register or byte memory operand */
529 /* XMM register or word memory operand */
531 /* XMM register or double word memory operand */
533 /* XMM register or quad word memory operand */
535 /* XMM register or double/quad word memory operand, depending on
538 /* 16-byte XMM, word, double word or quad word operand. */
540 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
542 /* 32-byte YMM operand */
544 /* quad word, ymmword or zmmword memory operand. */
546 /* 32-byte YMM or 16-byte word operand */
548 /* d_mode in 32bit, q_mode in 64bit mode. */
550 /* pair of v_mode operands */
555 /* operand size depends on REX prefixes. */
557 /* registers like dq_mode, memory like w_mode. */
561 /* 4- or 6-byte pointer operand */
564 /* v_mode for indirect branch opcodes. */
566 /* v_mode for stack-related opcodes. */
568 /* non-quad operand size depends on prefixes */
570 /* 16-byte operand */
572 /* registers like dq_mode, memory like b_mode. */
574 /* registers like d_mode, memory like b_mode. */
576 /* registers like d_mode, memory like w_mode. */
578 /* registers like dq_mode, memory like d_mode. */
580 /* normal vex mode */
582 /* 128bit vex mode */
584 /* 256bit vex mode */
586 /* operand size depends on the VEX.W bit. */
589 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
590 vex_vsib_d_w_dq_mode
,
591 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
593 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
594 vex_vsib_q_w_dq_mode
,
595 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
598 /* scalar, ignore vector length. */
600 /* like d_mode, ignore vector length. */
602 /* like d_swap_mode, ignore vector length. */
604 /* like q_mode, ignore vector length. */
606 /* like q_swap_mode, ignore vector length. */
608 /* like vex_mode, ignore vector length. */
610 /* like vex_w_dq_mode, ignore vector length. */
611 vex_scalar_w_dq_mode
,
613 /* Static rounding. */
615 /* Supress all exceptions. */
618 /* Mask register operand. */
620 /* Mask register operand. */
687 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
689 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
690 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
691 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
692 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
693 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
694 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
695 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
696 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
697 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
698 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
699 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
700 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
701 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
702 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
703 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
821 MOD_VEX_0F12_PREFIX_0
,
823 MOD_VEX_0F16_PREFIX_0
,
826 MOD_VEX_W_0_0F41_P_0_LEN_1
,
827 MOD_VEX_W_1_0F41_P_0_LEN_1
,
828 MOD_VEX_W_0_0F41_P_2_LEN_1
,
829 MOD_VEX_W_1_0F41_P_2_LEN_1
,
830 MOD_VEX_W_0_0F42_P_0_LEN_1
,
831 MOD_VEX_W_1_0F42_P_0_LEN_1
,
832 MOD_VEX_W_0_0F42_P_2_LEN_1
,
833 MOD_VEX_W_1_0F42_P_2_LEN_1
,
834 MOD_VEX_W_0_0F44_P_0_LEN_1
,
835 MOD_VEX_W_1_0F44_P_0_LEN_1
,
836 MOD_VEX_W_0_0F44_P_2_LEN_1
,
837 MOD_VEX_W_1_0F44_P_2_LEN_1
,
838 MOD_VEX_W_0_0F45_P_0_LEN_1
,
839 MOD_VEX_W_1_0F45_P_0_LEN_1
,
840 MOD_VEX_W_0_0F45_P_2_LEN_1
,
841 MOD_VEX_W_1_0F45_P_2_LEN_1
,
842 MOD_VEX_W_0_0F46_P_0_LEN_1
,
843 MOD_VEX_W_1_0F46_P_0_LEN_1
,
844 MOD_VEX_W_0_0F46_P_2_LEN_1
,
845 MOD_VEX_W_1_0F46_P_2_LEN_1
,
846 MOD_VEX_W_0_0F47_P_0_LEN_1
,
847 MOD_VEX_W_1_0F47_P_0_LEN_1
,
848 MOD_VEX_W_0_0F47_P_2_LEN_1
,
849 MOD_VEX_W_1_0F47_P_2_LEN_1
,
850 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
851 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
852 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
853 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
854 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
855 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
856 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
868 MOD_VEX_W_0_0F91_P_0_LEN_0
,
869 MOD_VEX_W_1_0F91_P_0_LEN_0
,
870 MOD_VEX_W_0_0F91_P_2_LEN_0
,
871 MOD_VEX_W_1_0F91_P_2_LEN_0
,
872 MOD_VEX_W_0_0F92_P_0_LEN_0
,
873 MOD_VEX_W_0_0F92_P_2_LEN_0
,
874 MOD_VEX_W_0_0F92_P_3_LEN_0
,
875 MOD_VEX_W_1_0F92_P_3_LEN_0
,
876 MOD_VEX_W_0_0F93_P_0_LEN_0
,
877 MOD_VEX_W_0_0F93_P_2_LEN_0
,
878 MOD_VEX_W_0_0F93_P_3_LEN_0
,
879 MOD_VEX_W_1_0F93_P_3_LEN_0
,
880 MOD_VEX_W_0_0F98_P_0_LEN_0
,
881 MOD_VEX_W_1_0F98_P_0_LEN_0
,
882 MOD_VEX_W_0_0F98_P_2_LEN_0
,
883 MOD_VEX_W_1_0F98_P_2_LEN_0
,
884 MOD_VEX_W_0_0F99_P_0_LEN_0
,
885 MOD_VEX_W_1_0F99_P_0_LEN_0
,
886 MOD_VEX_W_0_0F99_P_2_LEN_0
,
887 MOD_VEX_W_1_0F99_P_2_LEN_0
,
890 MOD_VEX_0FD7_PREFIX_2
,
891 MOD_VEX_0FE7_PREFIX_2
,
892 MOD_VEX_0FF0_PREFIX_3
,
893 MOD_VEX_0F381A_PREFIX_2
,
894 MOD_VEX_0F382A_PREFIX_2
,
895 MOD_VEX_0F382C_PREFIX_2
,
896 MOD_VEX_0F382D_PREFIX_2
,
897 MOD_VEX_0F382E_PREFIX_2
,
898 MOD_VEX_0F382F_PREFIX_2
,
899 MOD_VEX_0F385A_PREFIX_2
,
900 MOD_VEX_0F388C_PREFIX_2
,
901 MOD_VEX_0F388E_PREFIX_2
,
902 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
903 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
904 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
905 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
906 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
907 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
908 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
909 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
911 MOD_EVEX_0F10_PREFIX_1
,
912 MOD_EVEX_0F10_PREFIX_3
,
913 MOD_EVEX_0F11_PREFIX_1
,
914 MOD_EVEX_0F11_PREFIX_3
,
915 MOD_EVEX_0F12_PREFIX_0
,
916 MOD_EVEX_0F16_PREFIX_0
,
917 MOD_EVEX_0F38C6_REG_1
,
918 MOD_EVEX_0F38C6_REG_2
,
919 MOD_EVEX_0F38C6_REG_5
,
920 MOD_EVEX_0F38C6_REG_6
,
921 MOD_EVEX_0F38C7_REG_1
,
922 MOD_EVEX_0F38C7_REG_2
,
923 MOD_EVEX_0F38C7_REG_5
,
924 MOD_EVEX_0F38C7_REG_6
987 PREFIX_MOD_0_0FAE_REG_4
,
988 PREFIX_MOD_3_0FAE_REG_4
,
991 PREFIX_RM_0_0FAE_REG_7
,
997 PREFIX_MOD_0_0FC7_REG_6
,
998 PREFIX_MOD_3_0FC7_REG_6
,
999 PREFIX_MOD_3_0FC7_REG_7
,
1123 PREFIX_VEX_0F71_REG_2
,
1124 PREFIX_VEX_0F71_REG_4
,
1125 PREFIX_VEX_0F71_REG_6
,
1126 PREFIX_VEX_0F72_REG_2
,
1127 PREFIX_VEX_0F72_REG_4
,
1128 PREFIX_VEX_0F72_REG_6
,
1129 PREFIX_VEX_0F73_REG_2
,
1130 PREFIX_VEX_0F73_REG_3
,
1131 PREFIX_VEX_0F73_REG_6
,
1132 PREFIX_VEX_0F73_REG_7
,
1304 PREFIX_VEX_0F38F3_REG_1
,
1305 PREFIX_VEX_0F38F3_REG_2
,
1306 PREFIX_VEX_0F38F3_REG_3
,
1423 PREFIX_EVEX_0F71_REG_2
,
1424 PREFIX_EVEX_0F71_REG_4
,
1425 PREFIX_EVEX_0F71_REG_6
,
1426 PREFIX_EVEX_0F72_REG_0
,
1427 PREFIX_EVEX_0F72_REG_1
,
1428 PREFIX_EVEX_0F72_REG_2
,
1429 PREFIX_EVEX_0F72_REG_4
,
1430 PREFIX_EVEX_0F72_REG_6
,
1431 PREFIX_EVEX_0F73_REG_2
,
1432 PREFIX_EVEX_0F73_REG_3
,
1433 PREFIX_EVEX_0F73_REG_6
,
1434 PREFIX_EVEX_0F73_REG_7
,
1617 PREFIX_EVEX_0F38C6_REG_1
,
1618 PREFIX_EVEX_0F38C6_REG_2
,
1619 PREFIX_EVEX_0F38C6_REG_5
,
1620 PREFIX_EVEX_0F38C6_REG_6
,
1621 PREFIX_EVEX_0F38C7_REG_1
,
1622 PREFIX_EVEX_0F38C7_REG_2
,
1623 PREFIX_EVEX_0F38C7_REG_5
,
1624 PREFIX_EVEX_0F38C7_REG_6
,
1713 THREE_BYTE_0F38
= 0,
1741 VEX_LEN_0F10_P_1
= 0,
1745 VEX_LEN_0F12_P_0_M_0
,
1746 VEX_LEN_0F12_P_0_M_1
,
1749 VEX_LEN_0F16_P_0_M_0
,
1750 VEX_LEN_0F16_P_0_M_1
,
1814 VEX_LEN_0FAE_R_2_M_0
,
1815 VEX_LEN_0FAE_R_3_M_0
,
1824 VEX_LEN_0F381A_P_2_M_0
,
1827 VEX_LEN_0F385A_P_2_M_0
,
1834 VEX_LEN_0F38F3_R_1_P_0
,
1835 VEX_LEN_0F38F3_R_2_P_0
,
1836 VEX_LEN_0F38F3_R_3_P_0
,
1882 VEX_LEN_0FXOP_08_CC
,
1883 VEX_LEN_0FXOP_08_CD
,
1884 VEX_LEN_0FXOP_08_CE
,
1885 VEX_LEN_0FXOP_08_CF
,
1886 VEX_LEN_0FXOP_08_EC
,
1887 VEX_LEN_0FXOP_08_ED
,
1888 VEX_LEN_0FXOP_08_EE
,
1889 VEX_LEN_0FXOP_08_EF
,
1890 VEX_LEN_0FXOP_09_80
,
1924 VEX_W_0F41_P_0_LEN_1
,
1925 VEX_W_0F41_P_2_LEN_1
,
1926 VEX_W_0F42_P_0_LEN_1
,
1927 VEX_W_0F42_P_2_LEN_1
,
1928 VEX_W_0F44_P_0_LEN_0
,
1929 VEX_W_0F44_P_2_LEN_0
,
1930 VEX_W_0F45_P_0_LEN_1
,
1931 VEX_W_0F45_P_2_LEN_1
,
1932 VEX_W_0F46_P_0_LEN_1
,
1933 VEX_W_0F46_P_2_LEN_1
,
1934 VEX_W_0F47_P_0_LEN_1
,
1935 VEX_W_0F47_P_2_LEN_1
,
1936 VEX_W_0F4A_P_0_LEN_1
,
1937 VEX_W_0F4A_P_2_LEN_1
,
1938 VEX_W_0F4B_P_0_LEN_1
,
1939 VEX_W_0F4B_P_2_LEN_1
,
2019 VEX_W_0F90_P_0_LEN_0
,
2020 VEX_W_0F90_P_2_LEN_0
,
2021 VEX_W_0F91_P_0_LEN_0
,
2022 VEX_W_0F91_P_2_LEN_0
,
2023 VEX_W_0F92_P_0_LEN_0
,
2024 VEX_W_0F92_P_2_LEN_0
,
2025 VEX_W_0F92_P_3_LEN_0
,
2026 VEX_W_0F93_P_0_LEN_0
,
2027 VEX_W_0F93_P_2_LEN_0
,
2028 VEX_W_0F93_P_3_LEN_0
,
2029 VEX_W_0F98_P_0_LEN_0
,
2030 VEX_W_0F98_P_2_LEN_0
,
2031 VEX_W_0F99_P_0_LEN_0
,
2032 VEX_W_0F99_P_2_LEN_0
,
2111 VEX_W_0F381A_P_2_M_0
,
2123 VEX_W_0F382A_P_2_M_0
,
2125 VEX_W_0F382C_P_2_M_0
,
2126 VEX_W_0F382D_P_2_M_0
,
2127 VEX_W_0F382E_P_2_M_0
,
2128 VEX_W_0F382F_P_2_M_0
,
2150 VEX_W_0F385A_P_2_M_0
,
2178 VEX_W_0F3A30_P_2_LEN_0
,
2179 VEX_W_0F3A31_P_2_LEN_0
,
2180 VEX_W_0F3A32_P_2_LEN_0
,
2181 VEX_W_0F3A33_P_2_LEN_0
,
2201 EVEX_W_0F10_P_1_M_0
,
2202 EVEX_W_0F10_P_1_M_1
,
2204 EVEX_W_0F10_P_3_M_0
,
2205 EVEX_W_0F10_P_3_M_1
,
2207 EVEX_W_0F11_P_1_M_0
,
2208 EVEX_W_0F11_P_1_M_1
,
2210 EVEX_W_0F11_P_3_M_0
,
2211 EVEX_W_0F11_P_3_M_1
,
2212 EVEX_W_0F12_P_0_M_0
,
2213 EVEX_W_0F12_P_0_M_1
,
2223 EVEX_W_0F16_P_0_M_0
,
2224 EVEX_W_0F16_P_0_M_1
,
2295 EVEX_W_0F72_R_2_P_2
,
2296 EVEX_W_0F72_R_6_P_2
,
2297 EVEX_W_0F73_R_2_P_2
,
2298 EVEX_W_0F73_R_6_P_2
,
2398 EVEX_W_0F38C7_R_1_P_2
,
2399 EVEX_W_0F38C7_R_2_P_2
,
2400 EVEX_W_0F38C7_R_5_P_2
,
2401 EVEX_W_0F38C7_R_6_P_2
,
2436 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2445 unsigned int prefix_requirement
;
2448 /* Upper case letters in the instruction names here are macros.
2449 'A' => print 'b' if no register operands or suffix_always is true
2450 'B' => print 'b' if suffix_always is true
2451 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2453 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2454 suffix_always is true
2455 'E' => print 'e' if 32-bit form of jcxz
2456 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2457 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2458 'H' => print ",pt" or ",pn" branch hint
2459 'I' => honor following macro letter even in Intel mode (implemented only
2460 for some of the macro letters)
2462 'K' => print 'd' or 'q' if rex prefix is present.
2463 'L' => print 'l' if suffix_always is true
2464 'M' => print 'r' if intel_mnemonic is false.
2465 'N' => print 'n' if instruction has no wait "prefix"
2466 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2467 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2468 or suffix_always is true. print 'q' if rex prefix is present.
2469 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2471 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2472 'S' => print 'w', 'l' or 'q' if suffix_always is true
2473 'T' => print 'q' in 64bit mode if instruction has no operand size
2474 prefix and behave as 'P' otherwise
2475 'U' => print 'q' in 64bit mode if instruction has no operand size
2476 prefix and behave as 'Q' otherwise
2477 'V' => print 'q' in 64bit mode if instruction has no operand size
2478 prefix and behave as 'S' otherwise
2479 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2480 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2481 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2482 suffix_always is true.
2483 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2484 '!' => change condition from true to false or from false to true.
2485 '%' => add 1 upper case letter to the macro.
2486 '^' => print 'w' or 'l' depending on operand size prefix or
2487 suffix_always is true (lcall/ljmp).
2488 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2489 on operand size prefix.
2490 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2491 has no operand size prefix for AMD64 ISA, behave as 'P'
2494 2 upper case letter macros:
2495 "XY" => print 'x' or 'y' if suffix_always is true or no register
2496 operands and no broadcast.
2497 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2498 register operands and no broadcast.
2499 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2500 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2501 or suffix_always is true
2502 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2503 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2504 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2505 "LW" => print 'd', 'q' depending on the VEX.W bit
2506 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2507 an operand size prefix, or suffix_always is true. print
2508 'q' if rex prefix is present.
2510 Many of the above letters print nothing in Intel mode. See "putop"
2513 Braces '{' and '}', and vertical bars '|', indicate alternative
2514 mnemonic strings for AT&T and Intel. */
2516 static const struct dis386 dis386
[] = {
2518 { "addB", { Ebh1
, Gb
}, 0 },
2519 { "addS", { Evh1
, Gv
}, 0 },
2520 { "addB", { Gb
, EbS
}, 0 },
2521 { "addS", { Gv
, EvS
}, 0 },
2522 { "addB", { AL
, Ib
}, 0 },
2523 { "addS", { eAX
, Iv
}, 0 },
2524 { X86_64_TABLE (X86_64_06
) },
2525 { X86_64_TABLE (X86_64_07
) },
2527 { "orB", { Ebh1
, Gb
}, 0 },
2528 { "orS", { Evh1
, Gv
}, 0 },
2529 { "orB", { Gb
, EbS
}, 0 },
2530 { "orS", { Gv
, EvS
}, 0 },
2531 { "orB", { AL
, Ib
}, 0 },
2532 { "orS", { eAX
, Iv
}, 0 },
2533 { X86_64_TABLE (X86_64_0D
) },
2534 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2536 { "adcB", { Ebh1
, Gb
}, 0 },
2537 { "adcS", { Evh1
, Gv
}, 0 },
2538 { "adcB", { Gb
, EbS
}, 0 },
2539 { "adcS", { Gv
, EvS
}, 0 },
2540 { "adcB", { AL
, Ib
}, 0 },
2541 { "adcS", { eAX
, Iv
}, 0 },
2542 { X86_64_TABLE (X86_64_16
) },
2543 { X86_64_TABLE (X86_64_17
) },
2545 { "sbbB", { Ebh1
, Gb
}, 0 },
2546 { "sbbS", { Evh1
, Gv
}, 0 },
2547 { "sbbB", { Gb
, EbS
}, 0 },
2548 { "sbbS", { Gv
, EvS
}, 0 },
2549 { "sbbB", { AL
, Ib
}, 0 },
2550 { "sbbS", { eAX
, Iv
}, 0 },
2551 { X86_64_TABLE (X86_64_1E
) },
2552 { X86_64_TABLE (X86_64_1F
) },
2554 { "andB", { Ebh1
, Gb
}, 0 },
2555 { "andS", { Evh1
, Gv
}, 0 },
2556 { "andB", { Gb
, EbS
}, 0 },
2557 { "andS", { Gv
, EvS
}, 0 },
2558 { "andB", { AL
, Ib
}, 0 },
2559 { "andS", { eAX
, Iv
}, 0 },
2560 { Bad_Opcode
}, /* SEG ES prefix */
2561 { X86_64_TABLE (X86_64_27
) },
2563 { "subB", { Ebh1
, Gb
}, 0 },
2564 { "subS", { Evh1
, Gv
}, 0 },
2565 { "subB", { Gb
, EbS
}, 0 },
2566 { "subS", { Gv
, EvS
}, 0 },
2567 { "subB", { AL
, Ib
}, 0 },
2568 { "subS", { eAX
, Iv
}, 0 },
2569 { Bad_Opcode
}, /* SEG CS prefix */
2570 { X86_64_TABLE (X86_64_2F
) },
2572 { "xorB", { Ebh1
, Gb
}, 0 },
2573 { "xorS", { Evh1
, Gv
}, 0 },
2574 { "xorB", { Gb
, EbS
}, 0 },
2575 { "xorS", { Gv
, EvS
}, 0 },
2576 { "xorB", { AL
, Ib
}, 0 },
2577 { "xorS", { eAX
, Iv
}, 0 },
2578 { Bad_Opcode
}, /* SEG SS prefix */
2579 { X86_64_TABLE (X86_64_37
) },
2581 { "cmpB", { Eb
, Gb
}, 0 },
2582 { "cmpS", { Ev
, Gv
}, 0 },
2583 { "cmpB", { Gb
, EbS
}, 0 },
2584 { "cmpS", { Gv
, EvS
}, 0 },
2585 { "cmpB", { AL
, Ib
}, 0 },
2586 { "cmpS", { eAX
, Iv
}, 0 },
2587 { Bad_Opcode
}, /* SEG DS prefix */
2588 { X86_64_TABLE (X86_64_3F
) },
2590 { "inc{S|}", { RMeAX
}, 0 },
2591 { "inc{S|}", { RMeCX
}, 0 },
2592 { "inc{S|}", { RMeDX
}, 0 },
2593 { "inc{S|}", { RMeBX
}, 0 },
2594 { "inc{S|}", { RMeSP
}, 0 },
2595 { "inc{S|}", { RMeBP
}, 0 },
2596 { "inc{S|}", { RMeSI
}, 0 },
2597 { "inc{S|}", { RMeDI
}, 0 },
2599 { "dec{S|}", { RMeAX
}, 0 },
2600 { "dec{S|}", { RMeCX
}, 0 },
2601 { "dec{S|}", { RMeDX
}, 0 },
2602 { "dec{S|}", { RMeBX
}, 0 },
2603 { "dec{S|}", { RMeSP
}, 0 },
2604 { "dec{S|}", { RMeBP
}, 0 },
2605 { "dec{S|}", { RMeSI
}, 0 },
2606 { "dec{S|}", { RMeDI
}, 0 },
2608 { "pushV", { RMrAX
}, 0 },
2609 { "pushV", { RMrCX
}, 0 },
2610 { "pushV", { RMrDX
}, 0 },
2611 { "pushV", { RMrBX
}, 0 },
2612 { "pushV", { RMrSP
}, 0 },
2613 { "pushV", { RMrBP
}, 0 },
2614 { "pushV", { RMrSI
}, 0 },
2615 { "pushV", { RMrDI
}, 0 },
2617 { "popV", { RMrAX
}, 0 },
2618 { "popV", { RMrCX
}, 0 },
2619 { "popV", { RMrDX
}, 0 },
2620 { "popV", { RMrBX
}, 0 },
2621 { "popV", { RMrSP
}, 0 },
2622 { "popV", { RMrBP
}, 0 },
2623 { "popV", { RMrSI
}, 0 },
2624 { "popV", { RMrDI
}, 0 },
2626 { X86_64_TABLE (X86_64_60
) },
2627 { X86_64_TABLE (X86_64_61
) },
2628 { X86_64_TABLE (X86_64_62
) },
2629 { X86_64_TABLE (X86_64_63
) },
2630 { Bad_Opcode
}, /* seg fs */
2631 { Bad_Opcode
}, /* seg gs */
2632 { Bad_Opcode
}, /* op size prefix */
2633 { Bad_Opcode
}, /* adr size prefix */
2635 { "pushT", { sIv
}, 0 },
2636 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2637 { "pushT", { sIbT
}, 0 },
2638 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2639 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2640 { X86_64_TABLE (X86_64_6D
) },
2641 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2642 { X86_64_TABLE (X86_64_6F
) },
2644 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2645 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2646 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2647 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2648 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2649 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2650 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2651 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2653 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2654 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2655 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2656 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2657 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2658 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2659 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2660 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2662 { REG_TABLE (REG_80
) },
2663 { REG_TABLE (REG_81
) },
2665 { REG_TABLE (REG_82
) },
2666 { "testB", { Eb
, Gb
}, 0 },
2667 { "testS", { Ev
, Gv
}, 0 },
2668 { "xchgB", { Ebh2
, Gb
}, 0 },
2669 { "xchgS", { Evh2
, Gv
}, 0 },
2671 { "movB", { Ebh3
, Gb
}, 0 },
2672 { "movS", { Evh3
, Gv
}, 0 },
2673 { "movB", { Gb
, EbS
}, 0 },
2674 { "movS", { Gv
, EvS
}, 0 },
2675 { "movD", { Sv
, Sw
}, 0 },
2676 { MOD_TABLE (MOD_8D
) },
2677 { "movD", { Sw
, Sv
}, 0 },
2678 { REG_TABLE (REG_8F
) },
2680 { PREFIX_TABLE (PREFIX_90
) },
2681 { "xchgS", { RMeCX
, eAX
}, 0 },
2682 { "xchgS", { RMeDX
, eAX
}, 0 },
2683 { "xchgS", { RMeBX
, eAX
}, 0 },
2684 { "xchgS", { RMeSP
, eAX
}, 0 },
2685 { "xchgS", { RMeBP
, eAX
}, 0 },
2686 { "xchgS", { RMeSI
, eAX
}, 0 },
2687 { "xchgS", { RMeDI
, eAX
}, 0 },
2689 { "cW{t|}R", { XX
}, 0 },
2690 { "cR{t|}O", { XX
}, 0 },
2691 { X86_64_TABLE (X86_64_9A
) },
2692 { Bad_Opcode
}, /* fwait */
2693 { "pushfT", { XX
}, 0 },
2694 { "popfT", { XX
}, 0 },
2695 { "sahf", { XX
}, 0 },
2696 { "lahf", { XX
}, 0 },
2698 { "mov%LB", { AL
, Ob
}, 0 },
2699 { "mov%LS", { eAX
, Ov
}, 0 },
2700 { "mov%LB", { Ob
, AL
}, 0 },
2701 { "mov%LS", { Ov
, eAX
}, 0 },
2702 { "movs{b|}", { Ybr
, Xb
}, 0 },
2703 { "movs{R|}", { Yvr
, Xv
}, 0 },
2704 { "cmps{b|}", { Xb
, Yb
}, 0 },
2705 { "cmps{R|}", { Xv
, Yv
}, 0 },
2707 { "testB", { AL
, Ib
}, 0 },
2708 { "testS", { eAX
, Iv
}, 0 },
2709 { "stosB", { Ybr
, AL
}, 0 },
2710 { "stosS", { Yvr
, eAX
}, 0 },
2711 { "lodsB", { ALr
, Xb
}, 0 },
2712 { "lodsS", { eAXr
, Xv
}, 0 },
2713 { "scasB", { AL
, Yb
}, 0 },
2714 { "scasS", { eAX
, Yv
}, 0 },
2716 { "movB", { RMAL
, Ib
}, 0 },
2717 { "movB", { RMCL
, Ib
}, 0 },
2718 { "movB", { RMDL
, Ib
}, 0 },
2719 { "movB", { RMBL
, Ib
}, 0 },
2720 { "movB", { RMAH
, Ib
}, 0 },
2721 { "movB", { RMCH
, Ib
}, 0 },
2722 { "movB", { RMDH
, Ib
}, 0 },
2723 { "movB", { RMBH
, Ib
}, 0 },
2725 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2726 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2727 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2728 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2729 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2730 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2731 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2732 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2734 { REG_TABLE (REG_C0
) },
2735 { REG_TABLE (REG_C1
) },
2736 { "retT", { Iw
, BND
}, 0 },
2737 { "retT", { BND
}, 0 },
2738 { X86_64_TABLE (X86_64_C4
) },
2739 { X86_64_TABLE (X86_64_C5
) },
2740 { REG_TABLE (REG_C6
) },
2741 { REG_TABLE (REG_C7
) },
2743 { "enterT", { Iw
, Ib
}, 0 },
2744 { "leaveT", { XX
}, 0 },
2745 { "Jret{|f}P", { Iw
}, 0 },
2746 { "Jret{|f}P", { XX
}, 0 },
2747 { "int3", { XX
}, 0 },
2748 { "int", { Ib
}, 0 },
2749 { X86_64_TABLE (X86_64_CE
) },
2750 { "iret%LP", { XX
}, 0 },
2752 { REG_TABLE (REG_D0
) },
2753 { REG_TABLE (REG_D1
) },
2754 { REG_TABLE (REG_D2
) },
2755 { REG_TABLE (REG_D3
) },
2756 { X86_64_TABLE (X86_64_D4
) },
2757 { X86_64_TABLE (X86_64_D5
) },
2759 { "xlat", { DSBX
}, 0 },
2770 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2771 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2772 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2773 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2774 { "inB", { AL
, Ib
}, 0 },
2775 { "inG", { zAX
, Ib
}, 0 },
2776 { "outB", { Ib
, AL
}, 0 },
2777 { "outG", { Ib
, zAX
}, 0 },
2779 { X86_64_TABLE (X86_64_E8
) },
2780 { X86_64_TABLE (X86_64_E9
) },
2781 { X86_64_TABLE (X86_64_EA
) },
2782 { "jmp", { Jb
, BND
}, 0 },
2783 { "inB", { AL
, indirDX
}, 0 },
2784 { "inG", { zAX
, indirDX
}, 0 },
2785 { "outB", { indirDX
, AL
}, 0 },
2786 { "outG", { indirDX
, zAX
}, 0 },
2788 { Bad_Opcode
}, /* lock prefix */
2789 { "icebp", { XX
}, 0 },
2790 { Bad_Opcode
}, /* repne */
2791 { Bad_Opcode
}, /* repz */
2792 { "hlt", { XX
}, 0 },
2793 { "cmc", { XX
}, 0 },
2794 { REG_TABLE (REG_F6
) },
2795 { REG_TABLE (REG_F7
) },
2797 { "clc", { XX
}, 0 },
2798 { "stc", { XX
}, 0 },
2799 { "cli", { XX
}, 0 },
2800 { "sti", { XX
}, 0 },
2801 { "cld", { XX
}, 0 },
2802 { "std", { XX
}, 0 },
2803 { REG_TABLE (REG_FE
) },
2804 { REG_TABLE (REG_FF
) },
2807 static const struct dis386 dis386_twobyte
[] = {
2809 { REG_TABLE (REG_0F00
) },
2810 { REG_TABLE (REG_0F01
) },
2811 { "larS", { Gv
, Ew
}, 0 },
2812 { "lslS", { Gv
, Ew
}, 0 },
2814 { "syscall", { XX
}, 0 },
2815 { "clts", { XX
}, 0 },
2816 { "sysret%LP", { XX
}, 0 },
2818 { "invd", { XX
}, 0 },
2819 { "wbinvd", { XX
}, 0 },
2821 { "ud2", { XX
}, 0 },
2823 { REG_TABLE (REG_0F0D
) },
2824 { "femms", { XX
}, 0 },
2825 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2827 { PREFIX_TABLE (PREFIX_0F10
) },
2828 { PREFIX_TABLE (PREFIX_0F11
) },
2829 { PREFIX_TABLE (PREFIX_0F12
) },
2830 { MOD_TABLE (MOD_0F13
) },
2831 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2832 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2833 { PREFIX_TABLE (PREFIX_0F16
) },
2834 { MOD_TABLE (MOD_0F17
) },
2836 { REG_TABLE (REG_0F18
) },
2837 { "nopQ", { Ev
}, 0 },
2838 { PREFIX_TABLE (PREFIX_0F1A
) },
2839 { PREFIX_TABLE (PREFIX_0F1B
) },
2840 { "nopQ", { Ev
}, 0 },
2841 { "nopQ", { Ev
}, 0 },
2842 { "nopQ", { Ev
}, 0 },
2843 { "nopQ", { Ev
}, 0 },
2845 { "movZ", { Rm
, Cm
}, 0 },
2846 { "movZ", { Rm
, Dm
}, 0 },
2847 { "movZ", { Cm
, Rm
}, 0 },
2848 { "movZ", { Dm
, Rm
}, 0 },
2849 { MOD_TABLE (MOD_0F24
) },
2851 { MOD_TABLE (MOD_0F26
) },
2854 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2855 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2856 { PREFIX_TABLE (PREFIX_0F2A
) },
2857 { PREFIX_TABLE (PREFIX_0F2B
) },
2858 { PREFIX_TABLE (PREFIX_0F2C
) },
2859 { PREFIX_TABLE (PREFIX_0F2D
) },
2860 { PREFIX_TABLE (PREFIX_0F2E
) },
2861 { PREFIX_TABLE (PREFIX_0F2F
) },
2863 { "wrmsr", { XX
}, 0 },
2864 { "rdtsc", { XX
}, 0 },
2865 { "rdmsr", { XX
}, 0 },
2866 { "rdpmc", { XX
}, 0 },
2867 { "sysenter", { XX
}, 0 },
2868 { "sysexit", { XX
}, 0 },
2870 { "getsec", { XX
}, 0 },
2872 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2874 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2881 { "cmovoS", { Gv
, Ev
}, 0 },
2882 { "cmovnoS", { Gv
, Ev
}, 0 },
2883 { "cmovbS", { Gv
, Ev
}, 0 },
2884 { "cmovaeS", { Gv
, Ev
}, 0 },
2885 { "cmoveS", { Gv
, Ev
}, 0 },
2886 { "cmovneS", { Gv
, Ev
}, 0 },
2887 { "cmovbeS", { Gv
, Ev
}, 0 },
2888 { "cmovaS", { Gv
, Ev
}, 0 },
2890 { "cmovsS", { Gv
, Ev
}, 0 },
2891 { "cmovnsS", { Gv
, Ev
}, 0 },
2892 { "cmovpS", { Gv
, Ev
}, 0 },
2893 { "cmovnpS", { Gv
, Ev
}, 0 },
2894 { "cmovlS", { Gv
, Ev
}, 0 },
2895 { "cmovgeS", { Gv
, Ev
}, 0 },
2896 { "cmovleS", { Gv
, Ev
}, 0 },
2897 { "cmovgS", { Gv
, Ev
}, 0 },
2899 { MOD_TABLE (MOD_0F51
) },
2900 { PREFIX_TABLE (PREFIX_0F51
) },
2901 { PREFIX_TABLE (PREFIX_0F52
) },
2902 { PREFIX_TABLE (PREFIX_0F53
) },
2903 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2904 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2905 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2906 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2908 { PREFIX_TABLE (PREFIX_0F58
) },
2909 { PREFIX_TABLE (PREFIX_0F59
) },
2910 { PREFIX_TABLE (PREFIX_0F5A
) },
2911 { PREFIX_TABLE (PREFIX_0F5B
) },
2912 { PREFIX_TABLE (PREFIX_0F5C
) },
2913 { PREFIX_TABLE (PREFIX_0F5D
) },
2914 { PREFIX_TABLE (PREFIX_0F5E
) },
2915 { PREFIX_TABLE (PREFIX_0F5F
) },
2917 { PREFIX_TABLE (PREFIX_0F60
) },
2918 { PREFIX_TABLE (PREFIX_0F61
) },
2919 { PREFIX_TABLE (PREFIX_0F62
) },
2920 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2921 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2922 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2923 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2924 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2926 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2927 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2928 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2929 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2930 { PREFIX_TABLE (PREFIX_0F6C
) },
2931 { PREFIX_TABLE (PREFIX_0F6D
) },
2932 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2933 { PREFIX_TABLE (PREFIX_0F6F
) },
2935 { PREFIX_TABLE (PREFIX_0F70
) },
2936 { REG_TABLE (REG_0F71
) },
2937 { REG_TABLE (REG_0F72
) },
2938 { REG_TABLE (REG_0F73
) },
2939 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2940 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2941 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2942 { "emms", { XX
}, PREFIX_OPCODE
},
2944 { PREFIX_TABLE (PREFIX_0F78
) },
2945 { PREFIX_TABLE (PREFIX_0F79
) },
2946 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2948 { PREFIX_TABLE (PREFIX_0F7C
) },
2949 { PREFIX_TABLE (PREFIX_0F7D
) },
2950 { PREFIX_TABLE (PREFIX_0F7E
) },
2951 { PREFIX_TABLE (PREFIX_0F7F
) },
2953 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2954 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2955 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2956 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2957 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2958 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2959 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2960 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2962 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2963 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2964 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2965 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2966 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2967 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2968 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2969 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2971 { "seto", { Eb
}, 0 },
2972 { "setno", { Eb
}, 0 },
2973 { "setb", { Eb
}, 0 },
2974 { "setae", { Eb
}, 0 },
2975 { "sete", { Eb
}, 0 },
2976 { "setne", { Eb
}, 0 },
2977 { "setbe", { Eb
}, 0 },
2978 { "seta", { Eb
}, 0 },
2980 { "sets", { Eb
}, 0 },
2981 { "setns", { Eb
}, 0 },
2982 { "setp", { Eb
}, 0 },
2983 { "setnp", { Eb
}, 0 },
2984 { "setl", { Eb
}, 0 },
2985 { "setge", { Eb
}, 0 },
2986 { "setle", { Eb
}, 0 },
2987 { "setg", { Eb
}, 0 },
2989 { "pushT", { fs
}, 0 },
2990 { "popT", { fs
}, 0 },
2991 { "cpuid", { XX
}, 0 },
2992 { "btS", { Ev
, Gv
}, 0 },
2993 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2994 { "shldS", { Ev
, Gv
, CL
}, 0 },
2995 { REG_TABLE (REG_0FA6
) },
2996 { REG_TABLE (REG_0FA7
) },
2998 { "pushT", { gs
}, 0 },
2999 { "popT", { gs
}, 0 },
3000 { "rsm", { XX
}, 0 },
3001 { "btsS", { Evh1
, Gv
}, 0 },
3002 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
3003 { "shrdS", { Ev
, Gv
, CL
}, 0 },
3004 { REG_TABLE (REG_0FAE
) },
3005 { "imulS", { Gv
, Ev
}, 0 },
3007 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
3008 { "cmpxchgS", { Evh1
, Gv
}, 0 },
3009 { MOD_TABLE (MOD_0FB2
) },
3010 { "btrS", { Evh1
, Gv
}, 0 },
3011 { MOD_TABLE (MOD_0FB4
) },
3012 { MOD_TABLE (MOD_0FB5
) },
3013 { "movz{bR|x}", { Gv
, Eb
}, 0 },
3014 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
3016 { PREFIX_TABLE (PREFIX_0FB8
) },
3017 { "ud1", { XX
}, 0 },
3018 { REG_TABLE (REG_0FBA
) },
3019 { "btcS", { Evh1
, Gv
}, 0 },
3020 { PREFIX_TABLE (PREFIX_0FBC
) },
3021 { PREFIX_TABLE (PREFIX_0FBD
) },
3022 { "movs{bR|x}", { Gv
, Eb
}, 0 },
3023 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
3025 { "xaddB", { Ebh1
, Gb
}, 0 },
3026 { "xaddS", { Evh1
, Gv
}, 0 },
3027 { PREFIX_TABLE (PREFIX_0FC2
) },
3028 { MOD_TABLE (MOD_0FC3
) },
3029 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
3030 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
3031 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3032 { REG_TABLE (REG_0FC7
) },
3034 { "bswap", { RMeAX
}, 0 },
3035 { "bswap", { RMeCX
}, 0 },
3036 { "bswap", { RMeDX
}, 0 },
3037 { "bswap", { RMeBX
}, 0 },
3038 { "bswap", { RMeSP
}, 0 },
3039 { "bswap", { RMeBP
}, 0 },
3040 { "bswap", { RMeSI
}, 0 },
3041 { "bswap", { RMeDI
}, 0 },
3043 { PREFIX_TABLE (PREFIX_0FD0
) },
3044 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
3045 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
3046 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
3047 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
3048 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
3049 { PREFIX_TABLE (PREFIX_0FD6
) },
3050 { MOD_TABLE (MOD_0FD7
) },
3052 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
3053 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
3054 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
3055 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
3056 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
3057 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
3058 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
3059 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
3061 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
3062 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
3063 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
3064 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
3065 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
3066 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
3067 { PREFIX_TABLE (PREFIX_0FE6
) },
3068 { PREFIX_TABLE (PREFIX_0FE7
) },
3070 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
3071 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
3072 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
3073 { "por", { MX
, EM
}, PREFIX_OPCODE
},
3074 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
3075 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
3076 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
3077 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
3079 { PREFIX_TABLE (PREFIX_0FF0
) },
3080 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
3081 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
3082 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
3083 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
3084 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
3085 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
3086 { PREFIX_TABLE (PREFIX_0FF7
) },
3088 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
3089 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
3090 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
3091 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
3092 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
3093 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
3094 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
3098 static const unsigned char onebyte_has_modrm
[256] = {
3099 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3100 /* ------------------------------- */
3101 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3102 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3103 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3104 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3105 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3106 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3107 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3108 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3109 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3110 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3111 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3112 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3113 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3114 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3115 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3116 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3117 /* ------------------------------- */
3118 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3121 static const unsigned char twobyte_has_modrm
[256] = {
3122 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3123 /* ------------------------------- */
3124 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3125 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3126 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3127 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3128 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3129 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3130 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3131 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3132 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3133 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3134 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3135 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3136 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3137 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3138 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3139 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3140 /* ------------------------------- */
3141 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3144 static char obuf
[100];
3146 static char *mnemonicendp
;
3147 static char scratchbuf
[100];
3148 static unsigned char *start_codep
;
3149 static unsigned char *insn_codep
;
3150 static unsigned char *codep
;
3151 static unsigned char *end_codep
;
3152 static int last_lock_prefix
;
3153 static int last_repz_prefix
;
3154 static int last_repnz_prefix
;
3155 static int last_data_prefix
;
3156 static int last_addr_prefix
;
3157 static int last_rex_prefix
;
3158 static int last_seg_prefix
;
3159 static int fwait_prefix
;
3160 /* The active segment register prefix. */
3161 static int active_seg_prefix
;
3162 #define MAX_CODE_LENGTH 15
3163 /* We can up to 14 prefixes since the maximum instruction length is
3165 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3166 static disassemble_info
*the_info
;
3174 static unsigned char need_modrm
;
3184 int register_specifier
;
3191 int mask_register_specifier
;
3197 static unsigned char need_vex
;
3198 static unsigned char need_vex_reg
;
3199 static unsigned char vex_w_done
;
3207 /* If we are accessing mod/rm/reg without need_modrm set, then the
3208 values are stale. Hitting this abort likely indicates that you
3209 need to update onebyte_has_modrm or twobyte_has_modrm. */
3210 #define MODRM_CHECK if (!need_modrm) abort ()
3212 static const char **names64
;
3213 static const char **names32
;
3214 static const char **names16
;
3215 static const char **names8
;
3216 static const char **names8rex
;
3217 static const char **names_seg
;
3218 static const char *index64
;
3219 static const char *index32
;
3220 static const char **index16
;
3221 static const char **names_bnd
;
3223 static const char *intel_names64
[] = {
3224 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3225 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3227 static const char *intel_names32
[] = {
3228 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3229 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3231 static const char *intel_names16
[] = {
3232 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3233 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3235 static const char *intel_names8
[] = {
3236 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3238 static const char *intel_names8rex
[] = {
3239 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3240 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3242 static const char *intel_names_seg
[] = {
3243 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3245 static const char *intel_index64
= "riz";
3246 static const char *intel_index32
= "eiz";
3247 static const char *intel_index16
[] = {
3248 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3251 static const char *att_names64
[] = {
3252 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3253 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3255 static const char *att_names32
[] = {
3256 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3257 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3259 static const char *att_names16
[] = {
3260 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3261 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3263 static const char *att_names8
[] = {
3264 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3266 static const char *att_names8rex
[] = {
3267 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3268 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3270 static const char *att_names_seg
[] = {
3271 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3273 static const char *att_index64
= "%riz";
3274 static const char *att_index32
= "%eiz";
3275 static const char *att_index16
[] = {
3276 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3279 static const char **names_mm
;
3280 static const char *intel_names_mm
[] = {
3281 "mm0", "mm1", "mm2", "mm3",
3282 "mm4", "mm5", "mm6", "mm7"
3284 static const char *att_names_mm
[] = {
3285 "%mm0", "%mm1", "%mm2", "%mm3",
3286 "%mm4", "%mm5", "%mm6", "%mm7"
3289 static const char *intel_names_bnd
[] = {
3290 "bnd0", "bnd1", "bnd2", "bnd3"
3293 static const char *att_names_bnd
[] = {
3294 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3297 static const char **names_xmm
;
3298 static const char *intel_names_xmm
[] = {
3299 "xmm0", "xmm1", "xmm2", "xmm3",
3300 "xmm4", "xmm5", "xmm6", "xmm7",
3301 "xmm8", "xmm9", "xmm10", "xmm11",
3302 "xmm12", "xmm13", "xmm14", "xmm15",
3303 "xmm16", "xmm17", "xmm18", "xmm19",
3304 "xmm20", "xmm21", "xmm22", "xmm23",
3305 "xmm24", "xmm25", "xmm26", "xmm27",
3306 "xmm28", "xmm29", "xmm30", "xmm31"
3308 static const char *att_names_xmm
[] = {
3309 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3310 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3311 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3312 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3313 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3314 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3315 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3316 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3319 static const char **names_ymm
;
3320 static const char *intel_names_ymm
[] = {
3321 "ymm0", "ymm1", "ymm2", "ymm3",
3322 "ymm4", "ymm5", "ymm6", "ymm7",
3323 "ymm8", "ymm9", "ymm10", "ymm11",
3324 "ymm12", "ymm13", "ymm14", "ymm15",
3325 "ymm16", "ymm17", "ymm18", "ymm19",
3326 "ymm20", "ymm21", "ymm22", "ymm23",
3327 "ymm24", "ymm25", "ymm26", "ymm27",
3328 "ymm28", "ymm29", "ymm30", "ymm31"
3330 static const char *att_names_ymm
[] = {
3331 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3332 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3333 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3334 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3335 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3336 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3337 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3338 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3341 static const char **names_zmm
;
3342 static const char *intel_names_zmm
[] = {
3343 "zmm0", "zmm1", "zmm2", "zmm3",
3344 "zmm4", "zmm5", "zmm6", "zmm7",
3345 "zmm8", "zmm9", "zmm10", "zmm11",
3346 "zmm12", "zmm13", "zmm14", "zmm15",
3347 "zmm16", "zmm17", "zmm18", "zmm19",
3348 "zmm20", "zmm21", "zmm22", "zmm23",
3349 "zmm24", "zmm25", "zmm26", "zmm27",
3350 "zmm28", "zmm29", "zmm30", "zmm31"
3352 static const char *att_names_zmm
[] = {
3353 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3354 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3355 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3356 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3357 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3358 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3359 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3360 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3363 static const char **names_mask
;
3364 static const char *intel_names_mask
[] = {
3365 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3367 static const char *att_names_mask
[] = {
3368 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3371 static const char *names_rounding
[] =
3379 static const struct dis386 reg_table
[][8] = {
3382 { "addA", { Ebh1
, Ib
}, 0 },
3383 { "orA", { Ebh1
, Ib
}, 0 },
3384 { "adcA", { Ebh1
, Ib
}, 0 },
3385 { "sbbA", { Ebh1
, Ib
}, 0 },
3386 { "andA", { Ebh1
, Ib
}, 0 },
3387 { "subA", { Ebh1
, Ib
}, 0 },
3388 { "xorA", { Ebh1
, Ib
}, 0 },
3389 { "cmpA", { Eb
, Ib
}, 0 },
3393 { "addQ", { Evh1
, Iv
}, 0 },
3394 { "orQ", { Evh1
, Iv
}, 0 },
3395 { "adcQ", { Evh1
, Iv
}, 0 },
3396 { "sbbQ", { Evh1
, Iv
}, 0 },
3397 { "andQ", { Evh1
, Iv
}, 0 },
3398 { "subQ", { Evh1
, Iv
}, 0 },
3399 { "xorQ", { Evh1
, Iv
}, 0 },
3400 { "cmpQ", { Ev
, Iv
}, 0 },
3404 { "addQ", { Evh1
, sIb
}, 0 },
3405 { "orQ", { Evh1
, sIb
}, 0 },
3406 { "adcQ", { Evh1
, sIb
}, 0 },
3407 { "sbbQ", { Evh1
, sIb
}, 0 },
3408 { "andQ", { Evh1
, sIb
}, 0 },
3409 { "subQ", { Evh1
, sIb
}, 0 },
3410 { "xorQ", { Evh1
, sIb
}, 0 },
3411 { "cmpQ", { Ev
, sIb
}, 0 },
3415 { "popU", { stackEv
}, 0 },
3416 { XOP_8F_TABLE (XOP_09
) },
3420 { XOP_8F_TABLE (XOP_09
) },
3424 { "rolA", { Eb
, Ib
}, 0 },
3425 { "rorA", { Eb
, Ib
}, 0 },
3426 { "rclA", { Eb
, Ib
}, 0 },
3427 { "rcrA", { Eb
, Ib
}, 0 },
3428 { "shlA", { Eb
, Ib
}, 0 },
3429 { "shrA", { Eb
, Ib
}, 0 },
3431 { "sarA", { Eb
, Ib
}, 0 },
3435 { "rolQ", { Ev
, Ib
}, 0 },
3436 { "rorQ", { Ev
, Ib
}, 0 },
3437 { "rclQ", { Ev
, Ib
}, 0 },
3438 { "rcrQ", { Ev
, Ib
}, 0 },
3439 { "shlQ", { Ev
, Ib
}, 0 },
3440 { "shrQ", { Ev
, Ib
}, 0 },
3442 { "sarQ", { Ev
, Ib
}, 0 },
3446 { "movA", { Ebh3
, Ib
}, 0 },
3453 { MOD_TABLE (MOD_C6_REG_7
) },
3457 { "movQ", { Evh3
, Iv
}, 0 },
3464 { MOD_TABLE (MOD_C7_REG_7
) },
3468 { "rolA", { Eb
, I1
}, 0 },
3469 { "rorA", { Eb
, I1
}, 0 },
3470 { "rclA", { Eb
, I1
}, 0 },
3471 { "rcrA", { Eb
, I1
}, 0 },
3472 { "shlA", { Eb
, I1
}, 0 },
3473 { "shrA", { Eb
, I1
}, 0 },
3475 { "sarA", { Eb
, I1
}, 0 },
3479 { "rolQ", { Ev
, I1
}, 0 },
3480 { "rorQ", { Ev
, I1
}, 0 },
3481 { "rclQ", { Ev
, I1
}, 0 },
3482 { "rcrQ", { Ev
, I1
}, 0 },
3483 { "shlQ", { Ev
, I1
}, 0 },
3484 { "shrQ", { Ev
, I1
}, 0 },
3486 { "sarQ", { Ev
, I1
}, 0 },
3490 { "rolA", { Eb
, CL
}, 0 },
3491 { "rorA", { Eb
, CL
}, 0 },
3492 { "rclA", { Eb
, CL
}, 0 },
3493 { "rcrA", { Eb
, CL
}, 0 },
3494 { "shlA", { Eb
, CL
}, 0 },
3495 { "shrA", { Eb
, CL
}, 0 },
3497 { "sarA", { Eb
, CL
}, 0 },
3501 { "rolQ", { Ev
, CL
}, 0 },
3502 { "rorQ", { Ev
, CL
}, 0 },
3503 { "rclQ", { Ev
, CL
}, 0 },
3504 { "rcrQ", { Ev
, CL
}, 0 },
3505 { "shlQ", { Ev
, CL
}, 0 },
3506 { "shrQ", { Ev
, CL
}, 0 },
3508 { "sarQ", { Ev
, CL
}, 0 },
3512 { "testA", { Eb
, Ib
}, 0 },
3514 { "notA", { Ebh1
}, 0 },
3515 { "negA", { Ebh1
}, 0 },
3516 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3517 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3518 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3519 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3523 { "testQ", { Ev
, Iv
}, 0 },
3525 { "notQ", { Evh1
}, 0 },
3526 { "negQ", { Evh1
}, 0 },
3527 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3528 { "imulQ", { Ev
}, 0 },
3529 { "divQ", { Ev
}, 0 },
3530 { "idivQ", { Ev
}, 0 },
3534 { "incA", { Ebh1
}, 0 },
3535 { "decA", { Ebh1
}, 0 },
3539 { "incQ", { Evh1
}, 0 },
3540 { "decQ", { Evh1
}, 0 },
3541 { "call{&|}", { indirEv
, BND
}, 0 },
3542 { MOD_TABLE (MOD_FF_REG_3
) },
3543 { "jmp{&|}", { indirEv
, BND
}, 0 },
3544 { MOD_TABLE (MOD_FF_REG_5
) },
3545 { "pushU", { stackEv
}, 0 },
3550 { "sldtD", { Sv
}, 0 },
3551 { "strD", { Sv
}, 0 },
3552 { "lldt", { Ew
}, 0 },
3553 { "ltr", { Ew
}, 0 },
3554 { "verr", { Ew
}, 0 },
3555 { "verw", { Ew
}, 0 },
3561 { MOD_TABLE (MOD_0F01_REG_0
) },
3562 { MOD_TABLE (MOD_0F01_REG_1
) },
3563 { MOD_TABLE (MOD_0F01_REG_2
) },
3564 { MOD_TABLE (MOD_0F01_REG_3
) },
3565 { "smswD", { Sv
}, 0 },
3566 { MOD_TABLE (MOD_0F01_REG_5
) },
3567 { "lmsw", { Ew
}, 0 },
3568 { MOD_TABLE (MOD_0F01_REG_7
) },
3572 { "prefetch", { Mb
}, 0 },
3573 { "prefetchw", { Mb
}, 0 },
3574 { "prefetchwt1", { Mb
}, 0 },
3575 { "prefetch", { Mb
}, 0 },
3576 { "prefetch", { Mb
}, 0 },
3577 { "prefetch", { Mb
}, 0 },
3578 { "prefetch", { Mb
}, 0 },
3579 { "prefetch", { Mb
}, 0 },
3583 { MOD_TABLE (MOD_0F18_REG_0
) },
3584 { MOD_TABLE (MOD_0F18_REG_1
) },
3585 { MOD_TABLE (MOD_0F18_REG_2
) },
3586 { MOD_TABLE (MOD_0F18_REG_3
) },
3587 { MOD_TABLE (MOD_0F18_REG_4
) },
3588 { MOD_TABLE (MOD_0F18_REG_5
) },
3589 { MOD_TABLE (MOD_0F18_REG_6
) },
3590 { MOD_TABLE (MOD_0F18_REG_7
) },
3596 { MOD_TABLE (MOD_0F71_REG_2
) },
3598 { MOD_TABLE (MOD_0F71_REG_4
) },
3600 { MOD_TABLE (MOD_0F71_REG_6
) },
3606 { MOD_TABLE (MOD_0F72_REG_2
) },
3608 { MOD_TABLE (MOD_0F72_REG_4
) },
3610 { MOD_TABLE (MOD_0F72_REG_6
) },
3616 { MOD_TABLE (MOD_0F73_REG_2
) },
3617 { MOD_TABLE (MOD_0F73_REG_3
) },
3620 { MOD_TABLE (MOD_0F73_REG_6
) },
3621 { MOD_TABLE (MOD_0F73_REG_7
) },
3625 { "montmul", { { OP_0f07
, 0 } }, 0 },
3626 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3627 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3631 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3632 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3633 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3634 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3635 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3636 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3640 { MOD_TABLE (MOD_0FAE_REG_0
) },
3641 { MOD_TABLE (MOD_0FAE_REG_1
) },
3642 { MOD_TABLE (MOD_0FAE_REG_2
) },
3643 { MOD_TABLE (MOD_0FAE_REG_3
) },
3644 { MOD_TABLE (MOD_0FAE_REG_4
) },
3645 { MOD_TABLE (MOD_0FAE_REG_5
) },
3646 { MOD_TABLE (MOD_0FAE_REG_6
) },
3647 { MOD_TABLE (MOD_0FAE_REG_7
) },
3655 { "btQ", { Ev
, Ib
}, 0 },
3656 { "btsQ", { Evh1
, Ib
}, 0 },
3657 { "btrQ", { Evh1
, Ib
}, 0 },
3658 { "btcQ", { Evh1
, Ib
}, 0 },
3663 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3665 { MOD_TABLE (MOD_0FC7_REG_3
) },
3666 { MOD_TABLE (MOD_0FC7_REG_4
) },
3667 { MOD_TABLE (MOD_0FC7_REG_5
) },
3668 { MOD_TABLE (MOD_0FC7_REG_6
) },
3669 { MOD_TABLE (MOD_0FC7_REG_7
) },
3675 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3677 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3679 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3685 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3687 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3689 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3695 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3696 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3699 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3700 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3706 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3707 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3709 /* REG_VEX_0F38F3 */
3712 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3713 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3714 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3718 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3719 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3723 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3724 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3726 /* REG_XOP_TBM_01 */
3729 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3730 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3731 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3732 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3733 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3734 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3735 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3737 /* REG_XOP_TBM_02 */
3740 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3745 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3747 #define NEED_REG_TABLE
3748 #include "i386-dis-evex.h"
3749 #undef NEED_REG_TABLE
3752 static const struct dis386 prefix_table
[][4] = {
3755 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3756 { "pause", { XX
}, 0 },
3757 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3758 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3763 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3764 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3765 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3766 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3771 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3772 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3773 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3774 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3779 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3780 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3781 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3782 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3787 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3788 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3789 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3794 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3795 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3796 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3797 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3802 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3803 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3804 { "bndmov", { Ebnd
, Gbnd
}, 0 },
3805 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3810 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3811 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_OPCODE
},
3812 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3813 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3818 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3819 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3820 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3821 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3826 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3827 { "cvttss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3828 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3829 { "cvttsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3834 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3835 { "cvtss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3836 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3837 { "cvtsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3842 { "ucomiss",{ XM
, EXd
}, 0 },
3844 { "ucomisd",{ XM
, EXq
}, 0 },
3849 { "comiss", { XM
, EXd
}, 0 },
3851 { "comisd", { XM
, EXq
}, 0 },
3856 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3857 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3858 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3859 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3864 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3865 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3870 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3871 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3876 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3877 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3878 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3879 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3884 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3885 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3886 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3887 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3892 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3893 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3894 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3895 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3900 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3901 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3902 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3907 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3908 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3909 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3910 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3915 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3916 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3917 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3918 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3923 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3924 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3925 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3926 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3931 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3932 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3933 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3934 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3939 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3941 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3946 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3948 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3953 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3955 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3962 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3969 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3974 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3975 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3976 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3981 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3982 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3983 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3984 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3987 /* PREFIX_0F73_REG_3 */
3991 { "psrldq", { XS
, Ib
}, 0 },
3994 /* PREFIX_0F73_REG_7 */
3998 { "pslldq", { XS
, Ib
}, 0 },
4003 {"vmread", { Em
, Gm
}, 0 },
4005 {"extrq", { XS
, Ib
, Ib
}, 0 },
4006 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
4011 {"vmwrite", { Gm
, Em
}, 0 },
4013 {"extrq", { XM
, XS
}, 0 },
4014 {"insertq", { XM
, XS
}, 0 },
4021 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
4022 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
4029 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
4030 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
4035 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
4036 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
4037 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
4042 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
4043 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
4044 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
4047 /* PREFIX_0FAE_REG_0 */
4050 { "rdfsbase", { Ev
}, 0 },
4053 /* PREFIX_0FAE_REG_1 */
4056 { "rdgsbase", { Ev
}, 0 },
4059 /* PREFIX_0FAE_REG_2 */
4062 { "wrfsbase", { Ev
}, 0 },
4065 /* PREFIX_0FAE_REG_3 */
4068 { "wrgsbase", { Ev
}, 0 },
4071 /* PREFIX_MOD_0_0FAE_REG_4 */
4073 { "xsave", { FXSAVE
}, 0 },
4074 { "ptwrite%LQ", { Edq
}, 0 },
4077 /* PREFIX_MOD_3_0FAE_REG_4 */
4080 { "ptwrite%LQ", { Edq
}, 0 },
4083 /* PREFIX_0FAE_REG_6 */
4085 { "xsaveopt", { FXSAVE
}, 0 },
4087 { "clwb", { Mb
}, 0 },
4090 /* PREFIX_0FAE_REG_7 */
4092 { "clflush", { Mb
}, 0 },
4094 { "clflushopt", { Mb
}, 0 },
4097 /* PREFIX_RM_0_0FAE_REG_7 */
4099 { "sfence", { Skip_MODRM
}, 0 },
4101 { "pcommit", { Skip_MODRM
}, 0 },
4107 { "popcntS", { Gv
, Ev
}, 0 },
4112 { "bsfS", { Gv
, Ev
}, 0 },
4113 { "tzcntS", { Gv
, Ev
}, 0 },
4114 { "bsfS", { Gv
, Ev
}, 0 },
4119 { "bsrS", { Gv
, Ev
}, 0 },
4120 { "lzcntS", { Gv
, Ev
}, 0 },
4121 { "bsrS", { Gv
, Ev
}, 0 },
4126 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4127 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4128 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4129 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4132 /* PREFIX_MOD_0_0FC3 */
4134 { "movntiS", { Ev
, Gv
}, PREFIX_OPCODE
},
4137 /* PREFIX_MOD_0_0FC7_REG_6 */
4139 { "vmptrld",{ Mq
}, 0 },
4140 { "vmxon", { Mq
}, 0 },
4141 { "vmclear",{ Mq
}, 0 },
4144 /* PREFIX_MOD_3_0FC7_REG_6 */
4146 { "rdrand", { Ev
}, 0 },
4148 { "rdrand", { Ev
}, 0 }
4151 /* PREFIX_MOD_3_0FC7_REG_7 */
4153 { "rdseed", { Ev
}, 0 },
4154 { "rdpid", { Em
}, 0 },
4155 { "rdseed", { Ev
}, 0 },
4162 { "addsubpd", { XM
, EXx
}, 0 },
4163 { "addsubps", { XM
, EXx
}, 0 },
4169 { "movq2dq",{ XM
, MS
}, 0 },
4170 { "movq", { EXqS
, XM
}, 0 },
4171 { "movdq2q",{ MX
, XS
}, 0 },
4177 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4178 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4179 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4184 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4186 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4194 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4199 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4201 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4208 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4215 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4222 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4229 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4236 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4243 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4250 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4257 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4264 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4271 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4278 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4285 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4292 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4299 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4306 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4313 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4320 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4327 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4334 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4341 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4348 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4355 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4362 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4369 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4376 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4383 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4390 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4397 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4404 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4411 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4418 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4425 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4432 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4439 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4444 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4449 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4454 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4459 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4464 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4469 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4476 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4483 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4490 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4497 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4504 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4509 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4511 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4512 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4517 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4519 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4520 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4526 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4527 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4535 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4542 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4549 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4556 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4563 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4570 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4577 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4584 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4591 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4598 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4605 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4612 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4619 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4626 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4633 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4640 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4647 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4654 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4661 { "pcmpestrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4668 { "pcmpestri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4675 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4682 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4687 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4694 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4697 /* PREFIX_VEX_0F10 */
4699 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4700 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4701 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4702 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4705 /* PREFIX_VEX_0F11 */
4707 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4708 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4709 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4710 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4713 /* PREFIX_VEX_0F12 */
4715 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4716 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4717 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4718 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4721 /* PREFIX_VEX_0F16 */
4723 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4724 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4725 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4728 /* PREFIX_VEX_0F2A */
4731 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4733 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4736 /* PREFIX_VEX_0F2C */
4739 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4741 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4744 /* PREFIX_VEX_0F2D */
4747 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4749 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4752 /* PREFIX_VEX_0F2E */
4754 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4756 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4759 /* PREFIX_VEX_0F2F */
4761 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4763 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4766 /* PREFIX_VEX_0F41 */
4768 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4770 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4773 /* PREFIX_VEX_0F42 */
4775 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4777 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4780 /* PREFIX_VEX_0F44 */
4782 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4784 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4787 /* PREFIX_VEX_0F45 */
4789 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4791 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4794 /* PREFIX_VEX_0F46 */
4796 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4798 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4801 /* PREFIX_VEX_0F47 */
4803 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4805 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4808 /* PREFIX_VEX_0F4A */
4810 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4812 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4815 /* PREFIX_VEX_0F4B */
4817 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4819 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4822 /* PREFIX_VEX_0F51 */
4824 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4825 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4826 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4827 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4830 /* PREFIX_VEX_0F52 */
4832 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4833 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
4836 /* PREFIX_VEX_0F53 */
4838 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
4839 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
4842 /* PREFIX_VEX_0F58 */
4844 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
4845 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
4846 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
4847 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
4850 /* PREFIX_VEX_0F59 */
4852 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
4853 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
4854 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
4855 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
4858 /* PREFIX_VEX_0F5A */
4860 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
4861 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
4862 { "vcvtpd2ps%XY", { XMM
, EXx
}, 0 },
4863 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
4866 /* PREFIX_VEX_0F5B */
4868 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
4869 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
4870 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
4873 /* PREFIX_VEX_0F5C */
4875 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
4876 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
4877 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
4878 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
4881 /* PREFIX_VEX_0F5D */
4883 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
4884 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
4885 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
4886 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
4889 /* PREFIX_VEX_0F5E */
4891 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
4892 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
4893 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
4894 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
4897 /* PREFIX_VEX_0F5F */
4899 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
4900 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
4901 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
4902 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
4905 /* PREFIX_VEX_0F60 */
4909 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
4912 /* PREFIX_VEX_0F61 */
4916 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
4919 /* PREFIX_VEX_0F62 */
4923 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
4926 /* PREFIX_VEX_0F63 */
4930 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
4933 /* PREFIX_VEX_0F64 */
4937 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
4940 /* PREFIX_VEX_0F65 */
4944 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
4947 /* PREFIX_VEX_0F66 */
4951 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
4954 /* PREFIX_VEX_0F67 */
4958 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
4961 /* PREFIX_VEX_0F68 */
4965 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
4968 /* PREFIX_VEX_0F69 */
4972 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
4975 /* PREFIX_VEX_0F6A */
4979 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
4982 /* PREFIX_VEX_0F6B */
4986 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
4989 /* PREFIX_VEX_0F6C */
4993 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
4996 /* PREFIX_VEX_0F6D */
5000 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
5003 /* PREFIX_VEX_0F6E */
5007 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
5010 /* PREFIX_VEX_0F6F */
5013 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
5014 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
5017 /* PREFIX_VEX_0F70 */
5020 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
5021 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
5022 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
5025 /* PREFIX_VEX_0F71_REG_2 */
5029 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
5032 /* PREFIX_VEX_0F71_REG_4 */
5036 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
5039 /* PREFIX_VEX_0F71_REG_6 */
5043 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
5046 /* PREFIX_VEX_0F72_REG_2 */
5050 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
5053 /* PREFIX_VEX_0F72_REG_4 */
5057 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
5060 /* PREFIX_VEX_0F72_REG_6 */
5064 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
5067 /* PREFIX_VEX_0F73_REG_2 */
5071 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
5074 /* PREFIX_VEX_0F73_REG_3 */
5078 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
5081 /* PREFIX_VEX_0F73_REG_6 */
5085 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
5088 /* PREFIX_VEX_0F73_REG_7 */
5092 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
5095 /* PREFIX_VEX_0F74 */
5099 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
5102 /* PREFIX_VEX_0F75 */
5106 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
5109 /* PREFIX_VEX_0F76 */
5113 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
5116 /* PREFIX_VEX_0F77 */
5118 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
5121 /* PREFIX_VEX_0F7C */
5125 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
5126 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
5129 /* PREFIX_VEX_0F7D */
5133 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
5134 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
5137 /* PREFIX_VEX_0F7E */
5140 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5141 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5144 /* PREFIX_VEX_0F7F */
5147 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
5148 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
5151 /* PREFIX_VEX_0F90 */
5153 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5155 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5158 /* PREFIX_VEX_0F91 */
5160 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5162 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5165 /* PREFIX_VEX_0F92 */
5167 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5169 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5170 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5173 /* PREFIX_VEX_0F93 */
5175 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5177 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5178 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5181 /* PREFIX_VEX_0F98 */
5183 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5185 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5188 /* PREFIX_VEX_0F99 */
5190 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5192 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5195 /* PREFIX_VEX_0FC2 */
5197 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
5198 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
5199 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
5200 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
5203 /* PREFIX_VEX_0FC4 */
5207 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5210 /* PREFIX_VEX_0FC5 */
5214 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5217 /* PREFIX_VEX_0FD0 */
5221 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
5222 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
5225 /* PREFIX_VEX_0FD1 */
5229 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
5232 /* PREFIX_VEX_0FD2 */
5236 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
5239 /* PREFIX_VEX_0FD3 */
5243 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
5246 /* PREFIX_VEX_0FD4 */
5250 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
5253 /* PREFIX_VEX_0FD5 */
5257 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
5260 /* PREFIX_VEX_0FD6 */
5264 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5267 /* PREFIX_VEX_0FD7 */
5271 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5274 /* PREFIX_VEX_0FD8 */
5278 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
5281 /* PREFIX_VEX_0FD9 */
5285 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
5288 /* PREFIX_VEX_0FDA */
5292 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
5295 /* PREFIX_VEX_0FDB */
5299 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
5302 /* PREFIX_VEX_0FDC */
5306 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
5309 /* PREFIX_VEX_0FDD */
5313 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
5316 /* PREFIX_VEX_0FDE */
5320 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
5323 /* PREFIX_VEX_0FDF */
5327 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
5330 /* PREFIX_VEX_0FE0 */
5334 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
5337 /* PREFIX_VEX_0FE1 */
5341 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
5344 /* PREFIX_VEX_0FE2 */
5348 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
5351 /* PREFIX_VEX_0FE3 */
5355 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
5358 /* PREFIX_VEX_0FE4 */
5362 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
5365 /* PREFIX_VEX_0FE5 */
5369 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
5372 /* PREFIX_VEX_0FE6 */
5375 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
5376 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
5377 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5380 /* PREFIX_VEX_0FE7 */
5384 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5387 /* PREFIX_VEX_0FE8 */
5391 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5394 /* PREFIX_VEX_0FE9 */
5398 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5401 /* PREFIX_VEX_0FEA */
5405 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5408 /* PREFIX_VEX_0FEB */
5412 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5415 /* PREFIX_VEX_0FEC */
5419 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5422 /* PREFIX_VEX_0FED */
5426 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5429 /* PREFIX_VEX_0FEE */
5433 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5436 /* PREFIX_VEX_0FEF */
5440 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5443 /* PREFIX_VEX_0FF0 */
5448 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5451 /* PREFIX_VEX_0FF1 */
5455 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5458 /* PREFIX_VEX_0FF2 */
5462 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5465 /* PREFIX_VEX_0FF3 */
5469 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5472 /* PREFIX_VEX_0FF4 */
5476 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5479 /* PREFIX_VEX_0FF5 */
5483 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5486 /* PREFIX_VEX_0FF6 */
5490 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5493 /* PREFIX_VEX_0FF7 */
5497 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5500 /* PREFIX_VEX_0FF8 */
5504 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5507 /* PREFIX_VEX_0FF9 */
5511 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5514 /* PREFIX_VEX_0FFA */
5518 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5521 /* PREFIX_VEX_0FFB */
5525 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5528 /* PREFIX_VEX_0FFC */
5532 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5535 /* PREFIX_VEX_0FFD */
5539 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5542 /* PREFIX_VEX_0FFE */
5546 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5549 /* PREFIX_VEX_0F3800 */
5553 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5556 /* PREFIX_VEX_0F3801 */
5560 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5563 /* PREFIX_VEX_0F3802 */
5567 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5570 /* PREFIX_VEX_0F3803 */
5574 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5577 /* PREFIX_VEX_0F3804 */
5581 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5584 /* PREFIX_VEX_0F3805 */
5588 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5591 /* PREFIX_VEX_0F3806 */
5595 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5598 /* PREFIX_VEX_0F3807 */
5602 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5605 /* PREFIX_VEX_0F3808 */
5609 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5612 /* PREFIX_VEX_0F3809 */
5616 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5619 /* PREFIX_VEX_0F380A */
5623 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5626 /* PREFIX_VEX_0F380B */
5630 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5633 /* PREFIX_VEX_0F380C */
5637 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5640 /* PREFIX_VEX_0F380D */
5644 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5647 /* PREFIX_VEX_0F380E */
5651 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5654 /* PREFIX_VEX_0F380F */
5658 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5661 /* PREFIX_VEX_0F3813 */
5665 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5668 /* PREFIX_VEX_0F3816 */
5672 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5675 /* PREFIX_VEX_0F3817 */
5679 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5682 /* PREFIX_VEX_0F3818 */
5686 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5689 /* PREFIX_VEX_0F3819 */
5693 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5696 /* PREFIX_VEX_0F381A */
5700 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5703 /* PREFIX_VEX_0F381C */
5707 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5710 /* PREFIX_VEX_0F381D */
5714 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5717 /* PREFIX_VEX_0F381E */
5721 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5724 /* PREFIX_VEX_0F3820 */
5728 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5731 /* PREFIX_VEX_0F3821 */
5735 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5738 /* PREFIX_VEX_0F3822 */
5742 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5745 /* PREFIX_VEX_0F3823 */
5749 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5752 /* PREFIX_VEX_0F3824 */
5756 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5759 /* PREFIX_VEX_0F3825 */
5763 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5766 /* PREFIX_VEX_0F3828 */
5770 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5773 /* PREFIX_VEX_0F3829 */
5777 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5780 /* PREFIX_VEX_0F382A */
5784 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5787 /* PREFIX_VEX_0F382B */
5791 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5794 /* PREFIX_VEX_0F382C */
5798 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5801 /* PREFIX_VEX_0F382D */
5805 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5808 /* PREFIX_VEX_0F382E */
5812 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5815 /* PREFIX_VEX_0F382F */
5819 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5822 /* PREFIX_VEX_0F3830 */
5826 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5829 /* PREFIX_VEX_0F3831 */
5833 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
5836 /* PREFIX_VEX_0F3832 */
5840 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
5843 /* PREFIX_VEX_0F3833 */
5847 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
5850 /* PREFIX_VEX_0F3834 */
5854 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
5857 /* PREFIX_VEX_0F3835 */
5861 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
5864 /* PREFIX_VEX_0F3836 */
5868 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5871 /* PREFIX_VEX_0F3837 */
5875 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
5878 /* PREFIX_VEX_0F3838 */
5882 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
5885 /* PREFIX_VEX_0F3839 */
5889 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
5892 /* PREFIX_VEX_0F383A */
5896 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
5899 /* PREFIX_VEX_0F383B */
5903 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
5906 /* PREFIX_VEX_0F383C */
5910 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
5913 /* PREFIX_VEX_0F383D */
5917 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
5920 /* PREFIX_VEX_0F383E */
5924 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
5927 /* PREFIX_VEX_0F383F */
5931 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
5934 /* PREFIX_VEX_0F3840 */
5938 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
5941 /* PREFIX_VEX_0F3841 */
5945 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5948 /* PREFIX_VEX_0F3845 */
5952 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5955 /* PREFIX_VEX_0F3846 */
5959 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5962 /* PREFIX_VEX_0F3847 */
5966 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5969 /* PREFIX_VEX_0F3858 */
5973 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5976 /* PREFIX_VEX_0F3859 */
5980 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5983 /* PREFIX_VEX_0F385A */
5987 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5990 /* PREFIX_VEX_0F3878 */
5994 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5997 /* PREFIX_VEX_0F3879 */
6001 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
6004 /* PREFIX_VEX_0F388C */
6008 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
6011 /* PREFIX_VEX_0F388E */
6015 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
6018 /* PREFIX_VEX_0F3890 */
6022 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6025 /* PREFIX_VEX_0F3891 */
6029 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6032 /* PREFIX_VEX_0F3892 */
6036 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6039 /* PREFIX_VEX_0F3893 */
6043 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6046 /* PREFIX_VEX_0F3896 */
6050 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6053 /* PREFIX_VEX_0F3897 */
6057 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6060 /* PREFIX_VEX_0F3898 */
6064 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6067 /* PREFIX_VEX_0F3899 */
6071 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6074 /* PREFIX_VEX_0F389A */
6078 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6081 /* PREFIX_VEX_0F389B */
6085 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6088 /* PREFIX_VEX_0F389C */
6092 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6095 /* PREFIX_VEX_0F389D */
6099 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6102 /* PREFIX_VEX_0F389E */
6106 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6109 /* PREFIX_VEX_0F389F */
6113 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6116 /* PREFIX_VEX_0F38A6 */
6120 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6124 /* PREFIX_VEX_0F38A7 */
6128 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6131 /* PREFIX_VEX_0F38A8 */
6135 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6138 /* PREFIX_VEX_0F38A9 */
6142 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6145 /* PREFIX_VEX_0F38AA */
6149 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6152 /* PREFIX_VEX_0F38AB */
6156 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6159 /* PREFIX_VEX_0F38AC */
6163 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6166 /* PREFIX_VEX_0F38AD */
6170 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6173 /* PREFIX_VEX_0F38AE */
6177 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6180 /* PREFIX_VEX_0F38AF */
6184 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6187 /* PREFIX_VEX_0F38B6 */
6191 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6194 /* PREFIX_VEX_0F38B7 */
6198 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6201 /* PREFIX_VEX_0F38B8 */
6205 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6208 /* PREFIX_VEX_0F38B9 */
6212 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6215 /* PREFIX_VEX_0F38BA */
6219 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6222 /* PREFIX_VEX_0F38BB */
6226 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6229 /* PREFIX_VEX_0F38BC */
6233 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6236 /* PREFIX_VEX_0F38BD */
6240 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6243 /* PREFIX_VEX_0F38BE */
6247 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6250 /* PREFIX_VEX_0F38BF */
6254 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6257 /* PREFIX_VEX_0F38DB */
6261 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6264 /* PREFIX_VEX_0F38DC */
6268 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
6271 /* PREFIX_VEX_0F38DD */
6275 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
6278 /* PREFIX_VEX_0F38DE */
6282 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
6285 /* PREFIX_VEX_0F38DF */
6289 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
6292 /* PREFIX_VEX_0F38F2 */
6294 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6297 /* PREFIX_VEX_0F38F3_REG_1 */
6299 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6302 /* PREFIX_VEX_0F38F3_REG_2 */
6304 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6307 /* PREFIX_VEX_0F38F3_REG_3 */
6309 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6312 /* PREFIX_VEX_0F38F5 */
6314 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6315 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6317 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6320 /* PREFIX_VEX_0F38F6 */
6325 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6328 /* PREFIX_VEX_0F38F7 */
6330 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6331 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6332 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6333 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6336 /* PREFIX_VEX_0F3A00 */
6340 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6343 /* PREFIX_VEX_0F3A01 */
6347 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6350 /* PREFIX_VEX_0F3A02 */
6354 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6357 /* PREFIX_VEX_0F3A04 */
6361 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6364 /* PREFIX_VEX_0F3A05 */
6368 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6371 /* PREFIX_VEX_0F3A06 */
6375 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6378 /* PREFIX_VEX_0F3A08 */
6382 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6385 /* PREFIX_VEX_0F3A09 */
6389 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6392 /* PREFIX_VEX_0F3A0A */
6396 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6399 /* PREFIX_VEX_0F3A0B */
6403 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6406 /* PREFIX_VEX_0F3A0C */
6410 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6413 /* PREFIX_VEX_0F3A0D */
6417 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6420 /* PREFIX_VEX_0F3A0E */
6424 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6427 /* PREFIX_VEX_0F3A0F */
6431 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6434 /* PREFIX_VEX_0F3A14 */
6438 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6441 /* PREFIX_VEX_0F3A15 */
6445 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6448 /* PREFIX_VEX_0F3A16 */
6452 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6455 /* PREFIX_VEX_0F3A17 */
6459 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6462 /* PREFIX_VEX_0F3A18 */
6466 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6469 /* PREFIX_VEX_0F3A19 */
6473 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6476 /* PREFIX_VEX_0F3A1D */
6480 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6483 /* PREFIX_VEX_0F3A20 */
6487 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6490 /* PREFIX_VEX_0F3A21 */
6494 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6497 /* PREFIX_VEX_0F3A22 */
6501 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6504 /* PREFIX_VEX_0F3A30 */
6508 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6511 /* PREFIX_VEX_0F3A31 */
6515 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6518 /* PREFIX_VEX_0F3A32 */
6522 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6525 /* PREFIX_VEX_0F3A33 */
6529 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6532 /* PREFIX_VEX_0F3A38 */
6536 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6539 /* PREFIX_VEX_0F3A39 */
6543 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6546 /* PREFIX_VEX_0F3A40 */
6550 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6553 /* PREFIX_VEX_0F3A41 */
6557 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6560 /* PREFIX_VEX_0F3A42 */
6564 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6567 /* PREFIX_VEX_0F3A44 */
6571 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
6574 /* PREFIX_VEX_0F3A46 */
6578 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6581 /* PREFIX_VEX_0F3A48 */
6585 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6588 /* PREFIX_VEX_0F3A49 */
6592 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6595 /* PREFIX_VEX_0F3A4A */
6599 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6602 /* PREFIX_VEX_0F3A4B */
6606 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6609 /* PREFIX_VEX_0F3A4C */
6613 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6616 /* PREFIX_VEX_0F3A5C */
6620 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6623 /* PREFIX_VEX_0F3A5D */
6627 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6630 /* PREFIX_VEX_0F3A5E */
6634 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6637 /* PREFIX_VEX_0F3A5F */
6641 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6644 /* PREFIX_VEX_0F3A60 */
6648 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6652 /* PREFIX_VEX_0F3A61 */
6656 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6659 /* PREFIX_VEX_0F3A62 */
6663 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6666 /* PREFIX_VEX_0F3A63 */
6670 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6673 /* PREFIX_VEX_0F3A68 */
6677 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6680 /* PREFIX_VEX_0F3A69 */
6684 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6687 /* PREFIX_VEX_0F3A6A */
6691 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6694 /* PREFIX_VEX_0F3A6B */
6698 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6701 /* PREFIX_VEX_0F3A6C */
6705 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6708 /* PREFIX_VEX_0F3A6D */
6712 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6715 /* PREFIX_VEX_0F3A6E */
6719 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6722 /* PREFIX_VEX_0F3A6F */
6726 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6729 /* PREFIX_VEX_0F3A78 */
6733 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6736 /* PREFIX_VEX_0F3A79 */
6740 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6743 /* PREFIX_VEX_0F3A7A */
6747 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6750 /* PREFIX_VEX_0F3A7B */
6754 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6757 /* PREFIX_VEX_0F3A7C */
6761 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6765 /* PREFIX_VEX_0F3A7D */
6769 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6772 /* PREFIX_VEX_0F3A7E */
6776 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6779 /* PREFIX_VEX_0F3A7F */
6783 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6786 /* PREFIX_VEX_0F3ADF */
6790 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6793 /* PREFIX_VEX_0F3AF0 */
6798 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6801 #define NEED_PREFIX_TABLE
6802 #include "i386-dis-evex.h"
6803 #undef NEED_PREFIX_TABLE
6806 static const struct dis386 x86_64_table
[][2] = {
6809 { "pushP", { es
}, 0 },
6814 { "popP", { es
}, 0 },
6819 { "pushP", { cs
}, 0 },
6824 { "pushP", { ss
}, 0 },
6829 { "popP", { ss
}, 0 },
6834 { "pushP", { ds
}, 0 },
6839 { "popP", { ds
}, 0 },
6844 { "daa", { XX
}, 0 },
6849 { "das", { XX
}, 0 },
6854 { "aaa", { XX
}, 0 },
6859 { "aas", { XX
}, 0 },
6864 { "pushaP", { XX
}, 0 },
6869 { "popaP", { XX
}, 0 },
6874 { MOD_TABLE (MOD_62_32BIT
) },
6875 { EVEX_TABLE (EVEX_0F
) },
6880 { "arpl", { Ew
, Gw
}, 0 },
6881 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6886 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6887 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6892 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6893 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6898 { "Jcall{T|}", { Ap
}, 0 },
6903 { MOD_TABLE (MOD_C4_32BIT
) },
6904 { VEX_C4_TABLE (VEX_0F
) },
6909 { MOD_TABLE (MOD_C5_32BIT
) },
6910 { VEX_C5_TABLE (VEX_0F
) },
6915 { "into", { XX
}, 0 },
6920 { "aam", { Ib
}, 0 },
6925 { "aad", { Ib
}, 0 },
6930 { "callP", { Jv
, BND
}, 0 },
6931 { "call@", { Jv
, BND
}, 0 }
6936 { "jmpP", { Jv
, BND
}, 0 },
6937 { "jmp@", { Jv
, BND
}, 0 }
6942 { "Jjmp{T|}", { Ap
}, 0 },
6945 /* X86_64_0F01_REG_0 */
6947 { "sgdt{Q|IQ}", { M
}, 0 },
6948 { "sgdt", { M
}, 0 },
6951 /* X86_64_0F01_REG_1 */
6953 { "sidt{Q|IQ}", { M
}, 0 },
6954 { "sidt", { M
}, 0 },
6957 /* X86_64_0F01_REG_2 */
6959 { "lgdt{Q|Q}", { M
}, 0 },
6960 { "lgdt", { M
}, 0 },
6963 /* X86_64_0F01_REG_3 */
6965 { "lidt{Q|Q}", { M
}, 0 },
6966 { "lidt", { M
}, 0 },
6970 static const struct dis386 three_byte_table
[][256] = {
6972 /* THREE_BYTE_0F38 */
6975 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6976 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6977 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6978 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6979 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6980 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6981 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6982 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6984 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6985 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6986 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6987 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6993 { PREFIX_TABLE (PREFIX_0F3810
) },
6997 { PREFIX_TABLE (PREFIX_0F3814
) },
6998 { PREFIX_TABLE (PREFIX_0F3815
) },
7000 { PREFIX_TABLE (PREFIX_0F3817
) },
7006 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7007 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7008 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7011 { PREFIX_TABLE (PREFIX_0F3820
) },
7012 { PREFIX_TABLE (PREFIX_0F3821
) },
7013 { PREFIX_TABLE (PREFIX_0F3822
) },
7014 { PREFIX_TABLE (PREFIX_0F3823
) },
7015 { PREFIX_TABLE (PREFIX_0F3824
) },
7016 { PREFIX_TABLE (PREFIX_0F3825
) },
7020 { PREFIX_TABLE (PREFIX_0F3828
) },
7021 { PREFIX_TABLE (PREFIX_0F3829
) },
7022 { PREFIX_TABLE (PREFIX_0F382A
) },
7023 { PREFIX_TABLE (PREFIX_0F382B
) },
7029 { PREFIX_TABLE (PREFIX_0F3830
) },
7030 { PREFIX_TABLE (PREFIX_0F3831
) },
7031 { PREFIX_TABLE (PREFIX_0F3832
) },
7032 { PREFIX_TABLE (PREFIX_0F3833
) },
7033 { PREFIX_TABLE (PREFIX_0F3834
) },
7034 { PREFIX_TABLE (PREFIX_0F3835
) },
7036 { PREFIX_TABLE (PREFIX_0F3837
) },
7038 { PREFIX_TABLE (PREFIX_0F3838
) },
7039 { PREFIX_TABLE (PREFIX_0F3839
) },
7040 { PREFIX_TABLE (PREFIX_0F383A
) },
7041 { PREFIX_TABLE (PREFIX_0F383B
) },
7042 { PREFIX_TABLE (PREFIX_0F383C
) },
7043 { PREFIX_TABLE (PREFIX_0F383D
) },
7044 { PREFIX_TABLE (PREFIX_0F383E
) },
7045 { PREFIX_TABLE (PREFIX_0F383F
) },
7047 { PREFIX_TABLE (PREFIX_0F3840
) },
7048 { PREFIX_TABLE (PREFIX_0F3841
) },
7119 { PREFIX_TABLE (PREFIX_0F3880
) },
7120 { PREFIX_TABLE (PREFIX_0F3881
) },
7121 { PREFIX_TABLE (PREFIX_0F3882
) },
7200 { PREFIX_TABLE (PREFIX_0F38C8
) },
7201 { PREFIX_TABLE (PREFIX_0F38C9
) },
7202 { PREFIX_TABLE (PREFIX_0F38CA
) },
7203 { PREFIX_TABLE (PREFIX_0F38CB
) },
7204 { PREFIX_TABLE (PREFIX_0F38CC
) },
7205 { PREFIX_TABLE (PREFIX_0F38CD
) },
7221 { PREFIX_TABLE (PREFIX_0F38DB
) },
7222 { PREFIX_TABLE (PREFIX_0F38DC
) },
7223 { PREFIX_TABLE (PREFIX_0F38DD
) },
7224 { PREFIX_TABLE (PREFIX_0F38DE
) },
7225 { PREFIX_TABLE (PREFIX_0F38DF
) },
7245 { PREFIX_TABLE (PREFIX_0F38F0
) },
7246 { PREFIX_TABLE (PREFIX_0F38F1
) },
7251 { PREFIX_TABLE (PREFIX_0F38F6
) },
7263 /* THREE_BYTE_0F3A */
7275 { PREFIX_TABLE (PREFIX_0F3A08
) },
7276 { PREFIX_TABLE (PREFIX_0F3A09
) },
7277 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7278 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7279 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7280 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7281 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7282 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7288 { PREFIX_TABLE (PREFIX_0F3A14
) },
7289 { PREFIX_TABLE (PREFIX_0F3A15
) },
7290 { PREFIX_TABLE (PREFIX_0F3A16
) },
7291 { PREFIX_TABLE (PREFIX_0F3A17
) },
7302 { PREFIX_TABLE (PREFIX_0F3A20
) },
7303 { PREFIX_TABLE (PREFIX_0F3A21
) },
7304 { PREFIX_TABLE (PREFIX_0F3A22
) },
7338 { PREFIX_TABLE (PREFIX_0F3A40
) },
7339 { PREFIX_TABLE (PREFIX_0F3A41
) },
7340 { PREFIX_TABLE (PREFIX_0F3A42
) },
7342 { PREFIX_TABLE (PREFIX_0F3A44
) },
7374 { PREFIX_TABLE (PREFIX_0F3A60
) },
7375 { PREFIX_TABLE (PREFIX_0F3A61
) },
7376 { PREFIX_TABLE (PREFIX_0F3A62
) },
7377 { PREFIX_TABLE (PREFIX_0F3A63
) },
7495 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7516 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7555 /* THREE_BYTE_0F7A */
7594 { "ptest", { XX
}, PREFIX_OPCODE
},
7631 { "phaddbw", { XM
, EXq
}, PREFIX_OPCODE
},
7632 { "phaddbd", { XM
, EXq
}, PREFIX_OPCODE
},
7633 { "phaddbq", { XM
, EXq
}, PREFIX_OPCODE
},
7636 { "phaddwd", { XM
, EXq
}, PREFIX_OPCODE
},
7637 { "phaddwq", { XM
, EXq
}, PREFIX_OPCODE
},
7642 { "phadddq", { XM
, EXq
}, PREFIX_OPCODE
},
7649 { "phaddubw", { XM
, EXq
}, PREFIX_OPCODE
},
7650 { "phaddubd", { XM
, EXq
}, PREFIX_OPCODE
},
7651 { "phaddubq", { XM
, EXq
}, PREFIX_OPCODE
},
7654 { "phadduwd", { XM
, EXq
}, PREFIX_OPCODE
},
7655 { "phadduwq", { XM
, EXq
}, PREFIX_OPCODE
},
7660 { "phaddudq", { XM
, EXq
}, PREFIX_OPCODE
},
7667 { "phsubbw", { XM
, EXq
}, PREFIX_OPCODE
},
7668 { "phsubbd", { XM
, EXq
}, PREFIX_OPCODE
},
7669 { "phsubbq", { XM
, EXq
}, PREFIX_OPCODE
},
7848 static const struct dis386 xop_table
[][256] = {
8001 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8002 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8003 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8011 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8012 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8019 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8020 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8021 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8029 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8030 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8034 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8035 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8038 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8056 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
8068 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
8069 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
8070 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
8071 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
8081 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
8082 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
8083 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
8084 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
8117 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
8118 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
8119 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
8120 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
8144 { REG_TABLE (REG_XOP_TBM_01
) },
8145 { REG_TABLE (REG_XOP_TBM_02
) },
8163 { REG_TABLE (REG_XOP_LWPCB
) },
8287 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8288 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8289 { "vfrczss", { XM
, EXd
}, 0 },
8290 { "vfrczsd", { XM
, EXq
}, 0 },
8305 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8306 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8307 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8308 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8309 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8310 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8311 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8312 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8314 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8315 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8316 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8317 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8360 { "vphaddbw", { XM
, EXxmm
}, 0 },
8361 { "vphaddbd", { XM
, EXxmm
}, 0 },
8362 { "vphaddbq", { XM
, EXxmm
}, 0 },
8365 { "vphaddwd", { XM
, EXxmm
}, 0 },
8366 { "vphaddwq", { XM
, EXxmm
}, 0 },
8371 { "vphadddq", { XM
, EXxmm
}, 0 },
8378 { "vphaddubw", { XM
, EXxmm
}, 0 },
8379 { "vphaddubd", { XM
, EXxmm
}, 0 },
8380 { "vphaddubq", { XM
, EXxmm
}, 0 },
8383 { "vphadduwd", { XM
, EXxmm
}, 0 },
8384 { "vphadduwq", { XM
, EXxmm
}, 0 },
8389 { "vphaddudq", { XM
, EXxmm
}, 0 },
8396 { "vphsubbw", { XM
, EXxmm
}, 0 },
8397 { "vphsubwd", { XM
, EXxmm
}, 0 },
8398 { "vphsubdq", { XM
, EXxmm
}, 0 },
8452 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8454 { REG_TABLE (REG_XOP_LWP
) },
8724 static const struct dis386 vex_table
[][256] = {
8746 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8749 { MOD_TABLE (MOD_VEX_0F13
) },
8750 { VEX_W_TABLE (VEX_W_0F14
) },
8751 { VEX_W_TABLE (VEX_W_0F15
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8753 { MOD_TABLE (MOD_VEX_0F17
) },
8773 { VEX_W_TABLE (VEX_W_0F28
) },
8774 { VEX_W_TABLE (VEX_W_0F29
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8776 { MOD_TABLE (MOD_VEX_0F2B
) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8812 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8818 { MOD_TABLE (MOD_VEX_0F50
) },
8819 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8820 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8821 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8822 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8823 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8824 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8825 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8827 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8828 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8830 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8831 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8832 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8833 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8834 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8836 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8837 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8838 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8839 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8840 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8841 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8842 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8843 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8845 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8846 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8847 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8848 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8849 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8850 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8851 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8852 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8854 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8855 { REG_TABLE (REG_VEX_0F71
) },
8856 { REG_TABLE (REG_VEX_0F72
) },
8857 { REG_TABLE (REG_VEX_0F73
) },
8858 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8859 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8860 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8861 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8867 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8870 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8923 { REG_TABLE (REG_VEX_0FAE
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8950 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8962 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8963 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8964 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8965 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8966 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8967 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8968 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8969 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8971 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8972 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8973 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8974 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8975 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8978 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8980 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8981 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8982 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8983 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8984 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8985 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8986 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8987 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8989 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8990 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8991 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8992 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8994 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8995 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8996 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8999 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
9000 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
9001 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
9002 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
9004 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
9005 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
9007 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
9008 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
9009 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
9010 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
9011 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
9012 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
9013 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
9020 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
9031 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
9032 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
9033 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
9034 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
9035 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
9064 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
9082 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
9083 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
9118 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
9176 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
9181 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
9182 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
9183 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
9184 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
9187 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
9188 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
9191 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
9193 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
9194 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
9195 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
9196 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
9197 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
9205 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
9206 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
9208 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
9209 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
9210 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
9211 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
9212 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
9213 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
9214 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
9215 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
9223 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
9224 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
9226 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
9227 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
9228 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
9229 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
9230 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
9231 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
9232 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
9233 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
9265 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9266 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9267 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9268 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9269 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9291 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9292 { REG_TABLE (REG_VEX_0F38F3
) },
9294 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9295 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9296 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9310 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9311 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9312 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9314 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9315 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9316 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9319 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9320 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9321 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9322 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9323 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9324 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9325 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9326 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9332 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9333 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9334 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9335 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9337 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9338 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9342 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9346 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9347 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9348 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9364 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9365 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9366 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9367 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9373 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9374 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9382 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9383 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9384 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9386 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9388 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9391 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9392 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9393 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9394 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9395 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9413 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9414 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9415 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9416 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9418 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9419 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9420 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9421 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9427 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9428 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9429 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9430 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9431 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9432 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9433 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9434 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9445 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9446 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9447 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9448 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9449 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9450 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9451 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9452 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9560 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9580 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9600 #define NEED_OPCODE_TABLE
9601 #include "i386-dis-evex.h"
9602 #undef NEED_OPCODE_TABLE
9603 static const struct dis386 vex_len_table
[][2] = {
9604 /* VEX_LEN_0F10_P_1 */
9606 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9607 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9610 /* VEX_LEN_0F10_P_3 */
9612 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9613 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9616 /* VEX_LEN_0F11_P_1 */
9618 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9619 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9622 /* VEX_LEN_0F11_P_3 */
9624 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9625 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9628 /* VEX_LEN_0F12_P_0_M_0 */
9630 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9633 /* VEX_LEN_0F12_P_0_M_1 */
9635 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9638 /* VEX_LEN_0F12_P_2 */
9640 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9643 /* VEX_LEN_0F13_M_0 */
9645 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9648 /* VEX_LEN_0F16_P_0_M_0 */
9650 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9653 /* VEX_LEN_0F16_P_0_M_1 */
9655 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9658 /* VEX_LEN_0F16_P_2 */
9660 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9663 /* VEX_LEN_0F17_M_0 */
9665 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9668 /* VEX_LEN_0F2A_P_1 */
9670 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9671 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9674 /* VEX_LEN_0F2A_P_3 */
9676 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9677 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9680 /* VEX_LEN_0F2C_P_1 */
9682 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9683 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9686 /* VEX_LEN_0F2C_P_3 */
9688 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9689 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9692 /* VEX_LEN_0F2D_P_1 */
9694 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9695 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9698 /* VEX_LEN_0F2D_P_3 */
9700 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9701 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9704 /* VEX_LEN_0F2E_P_0 */
9706 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9707 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9710 /* VEX_LEN_0F2E_P_2 */
9712 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9713 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9716 /* VEX_LEN_0F2F_P_0 */
9718 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9719 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9722 /* VEX_LEN_0F2F_P_2 */
9724 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9725 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9728 /* VEX_LEN_0F41_P_0 */
9731 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9733 /* VEX_LEN_0F41_P_2 */
9736 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9738 /* VEX_LEN_0F42_P_0 */
9741 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9743 /* VEX_LEN_0F42_P_2 */
9746 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9748 /* VEX_LEN_0F44_P_0 */
9750 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9752 /* VEX_LEN_0F44_P_2 */
9754 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9756 /* VEX_LEN_0F45_P_0 */
9759 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9761 /* VEX_LEN_0F45_P_2 */
9764 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9766 /* VEX_LEN_0F46_P_0 */
9769 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9771 /* VEX_LEN_0F46_P_2 */
9774 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9776 /* VEX_LEN_0F47_P_0 */
9779 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9781 /* VEX_LEN_0F47_P_2 */
9784 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9786 /* VEX_LEN_0F4A_P_0 */
9789 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9791 /* VEX_LEN_0F4A_P_2 */
9794 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9796 /* VEX_LEN_0F4B_P_0 */
9799 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9801 /* VEX_LEN_0F4B_P_2 */
9804 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9807 /* VEX_LEN_0F51_P_1 */
9809 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9810 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9813 /* VEX_LEN_0F51_P_3 */
9815 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9816 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9819 /* VEX_LEN_0F52_P_1 */
9821 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9822 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9825 /* VEX_LEN_0F53_P_1 */
9827 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9828 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9831 /* VEX_LEN_0F58_P_1 */
9833 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9834 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9837 /* VEX_LEN_0F58_P_3 */
9839 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9840 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9843 /* VEX_LEN_0F59_P_1 */
9845 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9846 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9849 /* VEX_LEN_0F59_P_3 */
9851 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9852 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9855 /* VEX_LEN_0F5A_P_1 */
9857 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9858 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9861 /* VEX_LEN_0F5A_P_3 */
9863 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9864 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9867 /* VEX_LEN_0F5C_P_1 */
9869 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9870 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9873 /* VEX_LEN_0F5C_P_3 */
9875 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9876 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9879 /* VEX_LEN_0F5D_P_1 */
9881 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9882 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9885 /* VEX_LEN_0F5D_P_3 */
9887 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9888 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9891 /* VEX_LEN_0F5E_P_1 */
9893 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9894 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9897 /* VEX_LEN_0F5E_P_3 */
9899 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9900 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9903 /* VEX_LEN_0F5F_P_1 */
9905 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9906 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9909 /* VEX_LEN_0F5F_P_3 */
9911 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9912 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9915 /* VEX_LEN_0F6E_P_2 */
9917 { "vmovK", { XMScalar
, Edq
}, 0 },
9918 { "vmovK", { XMScalar
, Edq
}, 0 },
9921 /* VEX_LEN_0F7E_P_1 */
9923 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9924 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9927 /* VEX_LEN_0F7E_P_2 */
9929 { "vmovK", { Edq
, XMScalar
}, 0 },
9930 { "vmovK", { Edq
, XMScalar
}, 0 },
9933 /* VEX_LEN_0F90_P_0 */
9935 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9938 /* VEX_LEN_0F90_P_2 */
9940 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9943 /* VEX_LEN_0F91_P_0 */
9945 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9948 /* VEX_LEN_0F91_P_2 */
9950 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9953 /* VEX_LEN_0F92_P_0 */
9955 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9958 /* VEX_LEN_0F92_P_2 */
9960 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9963 /* VEX_LEN_0F92_P_3 */
9965 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9968 /* VEX_LEN_0F93_P_0 */
9970 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9973 /* VEX_LEN_0F93_P_2 */
9975 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9978 /* VEX_LEN_0F93_P_3 */
9980 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9983 /* VEX_LEN_0F98_P_0 */
9985 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9988 /* VEX_LEN_0F98_P_2 */
9990 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9993 /* VEX_LEN_0F99_P_0 */
9995 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9998 /* VEX_LEN_0F99_P_2 */
10000 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
10003 /* VEX_LEN_0FAE_R_2_M_0 */
10005 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
10008 /* VEX_LEN_0FAE_R_3_M_0 */
10010 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
10013 /* VEX_LEN_0FC2_P_1 */
10015 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
10016 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
10019 /* VEX_LEN_0FC2_P_3 */
10021 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
10022 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
10025 /* VEX_LEN_0FC4_P_2 */
10027 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
10030 /* VEX_LEN_0FC5_P_2 */
10032 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
10035 /* VEX_LEN_0FD6_P_2 */
10037 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
10038 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
10041 /* VEX_LEN_0FF7_P_2 */
10043 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
10046 /* VEX_LEN_0F3816_P_2 */
10049 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
10052 /* VEX_LEN_0F3819_P_2 */
10055 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
10058 /* VEX_LEN_0F381A_P_2_M_0 */
10061 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
10064 /* VEX_LEN_0F3836_P_2 */
10067 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
10070 /* VEX_LEN_0F3841_P_2 */
10072 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
10075 /* VEX_LEN_0F385A_P_2_M_0 */
10078 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
10081 /* VEX_LEN_0F38DB_P_2 */
10083 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
10086 /* VEX_LEN_0F38DC_P_2 */
10088 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
10091 /* VEX_LEN_0F38DD_P_2 */
10093 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
10096 /* VEX_LEN_0F38DE_P_2 */
10098 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
10101 /* VEX_LEN_0F38DF_P_2 */
10103 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
10106 /* VEX_LEN_0F38F2_P_0 */
10108 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
10111 /* VEX_LEN_0F38F3_R_1_P_0 */
10113 { "blsrS", { VexGdq
, Edq
}, 0 },
10116 /* VEX_LEN_0F38F3_R_2_P_0 */
10118 { "blsmskS", { VexGdq
, Edq
}, 0 },
10121 /* VEX_LEN_0F38F3_R_3_P_0 */
10123 { "blsiS", { VexGdq
, Edq
}, 0 },
10126 /* VEX_LEN_0F38F5_P_0 */
10128 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
10131 /* VEX_LEN_0F38F5_P_1 */
10133 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
10136 /* VEX_LEN_0F38F5_P_3 */
10138 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
10141 /* VEX_LEN_0F38F6_P_3 */
10143 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
10146 /* VEX_LEN_0F38F7_P_0 */
10148 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
10151 /* VEX_LEN_0F38F7_P_1 */
10153 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
10156 /* VEX_LEN_0F38F7_P_2 */
10158 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
10161 /* VEX_LEN_0F38F7_P_3 */
10163 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
10166 /* VEX_LEN_0F3A00_P_2 */
10169 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
10172 /* VEX_LEN_0F3A01_P_2 */
10175 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
10178 /* VEX_LEN_0F3A06_P_2 */
10181 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
10184 /* VEX_LEN_0F3A0A_P_2 */
10186 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10187 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10190 /* VEX_LEN_0F3A0B_P_2 */
10192 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10193 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10196 /* VEX_LEN_0F3A14_P_2 */
10198 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
10201 /* VEX_LEN_0F3A15_P_2 */
10203 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
10206 /* VEX_LEN_0F3A16_P_2 */
10208 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
10211 /* VEX_LEN_0F3A17_P_2 */
10213 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
10216 /* VEX_LEN_0F3A18_P_2 */
10219 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
10222 /* VEX_LEN_0F3A19_P_2 */
10225 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
10228 /* VEX_LEN_0F3A20_P_2 */
10230 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
10233 /* VEX_LEN_0F3A21_P_2 */
10235 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
10238 /* VEX_LEN_0F3A22_P_2 */
10240 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
10243 /* VEX_LEN_0F3A30_P_2 */
10245 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
10248 /* VEX_LEN_0F3A31_P_2 */
10250 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
10253 /* VEX_LEN_0F3A32_P_2 */
10255 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
10258 /* VEX_LEN_0F3A33_P_2 */
10260 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
10263 /* VEX_LEN_0F3A38_P_2 */
10266 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
10269 /* VEX_LEN_0F3A39_P_2 */
10272 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
10275 /* VEX_LEN_0F3A41_P_2 */
10277 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
10280 /* VEX_LEN_0F3A44_P_2 */
10282 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
10285 /* VEX_LEN_0F3A46_P_2 */
10288 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
10291 /* VEX_LEN_0F3A60_P_2 */
10293 { VEX_W_TABLE (VEX_W_0F3A60_P_2
) },
10296 /* VEX_LEN_0F3A61_P_2 */
10298 { VEX_W_TABLE (VEX_W_0F3A61_P_2
) },
10301 /* VEX_LEN_0F3A62_P_2 */
10303 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
10306 /* VEX_LEN_0F3A63_P_2 */
10308 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
10311 /* VEX_LEN_0F3A6A_P_2 */
10313 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10316 /* VEX_LEN_0F3A6B_P_2 */
10318 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10321 /* VEX_LEN_0F3A6E_P_2 */
10323 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10326 /* VEX_LEN_0F3A6F_P_2 */
10328 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10331 /* VEX_LEN_0F3A7A_P_2 */
10333 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10336 /* VEX_LEN_0F3A7B_P_2 */
10338 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10341 /* VEX_LEN_0F3A7E_P_2 */
10343 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10346 /* VEX_LEN_0F3A7F_P_2 */
10348 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10351 /* VEX_LEN_0F3ADF_P_2 */
10353 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
10356 /* VEX_LEN_0F3AF0_P_3 */
10358 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
10361 /* VEX_LEN_0FXOP_08_CC */
10363 { "vpcomb", { XM
, Vex128
, EXx
, Ib
}, 0 },
10366 /* VEX_LEN_0FXOP_08_CD */
10368 { "vpcomw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10371 /* VEX_LEN_0FXOP_08_CE */
10373 { "vpcomd", { XM
, Vex128
, EXx
, Ib
}, 0 },
10376 /* VEX_LEN_0FXOP_08_CF */
10378 { "vpcomq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10381 /* VEX_LEN_0FXOP_08_EC */
10383 { "vpcomub", { XM
, Vex128
, EXx
, Ib
}, 0 },
10386 /* VEX_LEN_0FXOP_08_ED */
10388 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10391 /* VEX_LEN_0FXOP_08_EE */
10393 { "vpcomud", { XM
, Vex128
, EXx
, Ib
}, 0 },
10396 /* VEX_LEN_0FXOP_08_EF */
10398 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10401 /* VEX_LEN_0FXOP_09_80 */
10403 { "vfrczps", { XM
, EXxmm
}, 0 },
10404 { "vfrczps", { XM
, EXymmq
}, 0 },
10407 /* VEX_LEN_0FXOP_09_81 */
10409 { "vfrczpd", { XM
, EXxmm
}, 0 },
10410 { "vfrczpd", { XM
, EXymmq
}, 0 },
10414 static const struct dis386 vex_w_table
[][2] = {
10416 /* VEX_W_0F10_P_0 */
10417 { "vmovups", { XM
, EXx
}, 0 },
10420 /* VEX_W_0F10_P_1 */
10421 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
10424 /* VEX_W_0F10_P_2 */
10425 { "vmovupd", { XM
, EXx
}, 0 },
10428 /* VEX_W_0F10_P_3 */
10429 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
10432 /* VEX_W_0F11_P_0 */
10433 { "vmovups", { EXxS
, XM
}, 0 },
10436 /* VEX_W_0F11_P_1 */
10437 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
10440 /* VEX_W_0F11_P_2 */
10441 { "vmovupd", { EXxS
, XM
}, 0 },
10444 /* VEX_W_0F11_P_3 */
10445 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
10448 /* VEX_W_0F12_P_0_M_0 */
10449 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
10452 /* VEX_W_0F12_P_0_M_1 */
10453 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
10456 /* VEX_W_0F12_P_1 */
10457 { "vmovsldup", { XM
, EXx
}, 0 },
10460 /* VEX_W_0F12_P_2 */
10461 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
10464 /* VEX_W_0F12_P_3 */
10465 { "vmovddup", { XM
, EXymmq
}, 0 },
10468 /* VEX_W_0F13_M_0 */
10469 { "vmovlpX", { EXq
, XM
}, 0 },
10473 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
10477 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
10480 /* VEX_W_0F16_P_0_M_0 */
10481 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
10484 /* VEX_W_0F16_P_0_M_1 */
10485 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
10488 /* VEX_W_0F16_P_1 */
10489 { "vmovshdup", { XM
, EXx
}, 0 },
10492 /* VEX_W_0F16_P_2 */
10493 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
10496 /* VEX_W_0F17_M_0 */
10497 { "vmovhpX", { EXq
, XM
}, 0 },
10501 { "vmovapX", { XM
, EXx
}, 0 },
10505 { "vmovapX", { EXxS
, XM
}, 0 },
10508 /* VEX_W_0F2B_M_0 */
10509 { "vmovntpX", { Mx
, XM
}, 0 },
10512 /* VEX_W_0F2E_P_0 */
10513 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
10516 /* VEX_W_0F2E_P_2 */
10517 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
10520 /* VEX_W_0F2F_P_0 */
10521 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
10524 /* VEX_W_0F2F_P_2 */
10525 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
10528 /* VEX_W_0F41_P_0_LEN_1 */
10529 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
10530 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
10533 /* VEX_W_0F41_P_2_LEN_1 */
10534 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
10535 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
10538 /* VEX_W_0F42_P_0_LEN_1 */
10539 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
10540 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
10543 /* VEX_W_0F42_P_2_LEN_1 */
10544 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
10545 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
10548 /* VEX_W_0F44_P_0_LEN_0 */
10549 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
10550 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
10553 /* VEX_W_0F44_P_2_LEN_0 */
10554 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
10555 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
10558 /* VEX_W_0F45_P_0_LEN_1 */
10559 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
10560 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
10563 /* VEX_W_0F45_P_2_LEN_1 */
10564 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
10565 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
10568 /* VEX_W_0F46_P_0_LEN_1 */
10569 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
10570 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
10573 /* VEX_W_0F46_P_2_LEN_1 */
10574 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
10575 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
10578 /* VEX_W_0F47_P_0_LEN_1 */
10579 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
10580 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
10583 /* VEX_W_0F47_P_2_LEN_1 */
10584 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
10585 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
10588 /* VEX_W_0F4A_P_0_LEN_1 */
10589 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
10590 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
10593 /* VEX_W_0F4A_P_2_LEN_1 */
10594 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
10595 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
10598 /* VEX_W_0F4B_P_0_LEN_1 */
10599 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
10600 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
10603 /* VEX_W_0F4B_P_2_LEN_1 */
10604 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
10607 /* VEX_W_0F50_M_0 */
10608 { "vmovmskpX", { Gdq
, XS
}, 0 },
10611 /* VEX_W_0F51_P_0 */
10612 { "vsqrtps", { XM
, EXx
}, 0 },
10615 /* VEX_W_0F51_P_1 */
10616 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10619 /* VEX_W_0F51_P_2 */
10620 { "vsqrtpd", { XM
, EXx
}, 0 },
10623 /* VEX_W_0F51_P_3 */
10624 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10627 /* VEX_W_0F52_P_0 */
10628 { "vrsqrtps", { XM
, EXx
}, 0 },
10631 /* VEX_W_0F52_P_1 */
10632 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10635 /* VEX_W_0F53_P_0 */
10636 { "vrcpps", { XM
, EXx
}, 0 },
10639 /* VEX_W_0F53_P_1 */
10640 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10643 /* VEX_W_0F58_P_0 */
10644 { "vaddps", { XM
, Vex
, EXx
}, 0 },
10647 /* VEX_W_0F58_P_1 */
10648 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10651 /* VEX_W_0F58_P_2 */
10652 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
10655 /* VEX_W_0F58_P_3 */
10656 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10659 /* VEX_W_0F59_P_0 */
10660 { "vmulps", { XM
, Vex
, EXx
}, 0 },
10663 /* VEX_W_0F59_P_1 */
10664 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10667 /* VEX_W_0F59_P_2 */
10668 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
10671 /* VEX_W_0F59_P_3 */
10672 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10675 /* VEX_W_0F5A_P_0 */
10676 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
10679 /* VEX_W_0F5A_P_1 */
10680 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10683 /* VEX_W_0F5A_P_3 */
10684 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10687 /* VEX_W_0F5B_P_0 */
10688 { "vcvtdq2ps", { XM
, EXx
}, 0 },
10691 /* VEX_W_0F5B_P_1 */
10692 { "vcvttps2dq", { XM
, EXx
}, 0 },
10695 /* VEX_W_0F5B_P_2 */
10696 { "vcvtps2dq", { XM
, EXx
}, 0 },
10699 /* VEX_W_0F5C_P_0 */
10700 { "vsubps", { XM
, Vex
, EXx
}, 0 },
10703 /* VEX_W_0F5C_P_1 */
10704 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10707 /* VEX_W_0F5C_P_2 */
10708 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
10711 /* VEX_W_0F5C_P_3 */
10712 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10715 /* VEX_W_0F5D_P_0 */
10716 { "vminps", { XM
, Vex
, EXx
}, 0 },
10719 /* VEX_W_0F5D_P_1 */
10720 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10723 /* VEX_W_0F5D_P_2 */
10724 { "vminpd", { XM
, Vex
, EXx
}, 0 },
10727 /* VEX_W_0F5D_P_3 */
10728 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10731 /* VEX_W_0F5E_P_0 */
10732 { "vdivps", { XM
, Vex
, EXx
}, 0 },
10735 /* VEX_W_0F5E_P_1 */
10736 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10739 /* VEX_W_0F5E_P_2 */
10740 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
10743 /* VEX_W_0F5E_P_3 */
10744 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10747 /* VEX_W_0F5F_P_0 */
10748 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
10751 /* VEX_W_0F5F_P_1 */
10752 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10755 /* VEX_W_0F5F_P_2 */
10756 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
10759 /* VEX_W_0F5F_P_3 */
10760 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10763 /* VEX_W_0F60_P_2 */
10764 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
10767 /* VEX_W_0F61_P_2 */
10768 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
10771 /* VEX_W_0F62_P_2 */
10772 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
10775 /* VEX_W_0F63_P_2 */
10776 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
10779 /* VEX_W_0F64_P_2 */
10780 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
10783 /* VEX_W_0F65_P_2 */
10784 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
10787 /* VEX_W_0F66_P_2 */
10788 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
10791 /* VEX_W_0F67_P_2 */
10792 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
10795 /* VEX_W_0F68_P_2 */
10796 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
10799 /* VEX_W_0F69_P_2 */
10800 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
10803 /* VEX_W_0F6A_P_2 */
10804 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
10807 /* VEX_W_0F6B_P_2 */
10808 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
10811 /* VEX_W_0F6C_P_2 */
10812 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
10815 /* VEX_W_0F6D_P_2 */
10816 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
10819 /* VEX_W_0F6F_P_1 */
10820 { "vmovdqu", { XM
, EXx
}, 0 },
10823 /* VEX_W_0F6F_P_2 */
10824 { "vmovdqa", { XM
, EXx
}, 0 },
10827 /* VEX_W_0F70_P_1 */
10828 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
10831 /* VEX_W_0F70_P_2 */
10832 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
10835 /* VEX_W_0F70_P_3 */
10836 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
10839 /* VEX_W_0F71_R_2_P_2 */
10840 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
10843 /* VEX_W_0F71_R_4_P_2 */
10844 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
10847 /* VEX_W_0F71_R_6_P_2 */
10848 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
10851 /* VEX_W_0F72_R_2_P_2 */
10852 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
10855 /* VEX_W_0F72_R_4_P_2 */
10856 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
10859 /* VEX_W_0F72_R_6_P_2 */
10860 { "vpslld", { Vex
, XS
, Ib
}, 0 },
10863 /* VEX_W_0F73_R_2_P_2 */
10864 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
10867 /* VEX_W_0F73_R_3_P_2 */
10868 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
10871 /* VEX_W_0F73_R_6_P_2 */
10872 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
10875 /* VEX_W_0F73_R_7_P_2 */
10876 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
10879 /* VEX_W_0F74_P_2 */
10880 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
10883 /* VEX_W_0F75_P_2 */
10884 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
10887 /* VEX_W_0F76_P_2 */
10888 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
10891 /* VEX_W_0F77_P_0 */
10892 { "", { VZERO
}, 0 },
10895 /* VEX_W_0F7C_P_2 */
10896 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
10899 /* VEX_W_0F7C_P_3 */
10900 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
10903 /* VEX_W_0F7D_P_2 */
10904 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
10907 /* VEX_W_0F7D_P_3 */
10908 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
10911 /* VEX_W_0F7E_P_1 */
10912 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
10915 /* VEX_W_0F7F_P_1 */
10916 { "vmovdqu", { EXxS
, XM
}, 0 },
10919 /* VEX_W_0F7F_P_2 */
10920 { "vmovdqa", { EXxS
, XM
}, 0 },
10923 /* VEX_W_0F90_P_0_LEN_0 */
10924 { "kmovw", { MaskG
, MaskE
}, 0 },
10925 { "kmovq", { MaskG
, MaskE
}, 0 },
10928 /* VEX_W_0F90_P_2_LEN_0 */
10929 { "kmovb", { MaskG
, MaskBDE
}, 0 },
10930 { "kmovd", { MaskG
, MaskBDE
}, 0 },
10933 /* VEX_W_0F91_P_0_LEN_0 */
10934 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
10935 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
10938 /* VEX_W_0F91_P_2_LEN_0 */
10939 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
10940 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
10943 /* VEX_W_0F92_P_0_LEN_0 */
10944 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10947 /* VEX_W_0F92_P_2_LEN_0 */
10948 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10951 /* VEX_W_0F92_P_3_LEN_0 */
10952 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0
) },
10953 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0
) },
10956 /* VEX_W_0F93_P_0_LEN_0 */
10957 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10960 /* VEX_W_0F93_P_2_LEN_0 */
10961 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10964 /* VEX_W_0F93_P_3_LEN_0 */
10965 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0
) },
10966 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0
) },
10969 /* VEX_W_0F98_P_0_LEN_0 */
10970 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10971 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10974 /* VEX_W_0F98_P_2_LEN_0 */
10975 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10976 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10979 /* VEX_W_0F99_P_0_LEN_0 */
10980 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10981 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10984 /* VEX_W_0F99_P_2_LEN_0 */
10985 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10986 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10989 /* VEX_W_0FAE_R_2_M_0 */
10990 { "vldmxcsr", { Md
}, 0 },
10993 /* VEX_W_0FAE_R_3_M_0 */
10994 { "vstmxcsr", { Md
}, 0 },
10997 /* VEX_W_0FC2_P_0 */
10998 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
11001 /* VEX_W_0FC2_P_1 */
11002 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
11005 /* VEX_W_0FC2_P_2 */
11006 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
11009 /* VEX_W_0FC2_P_3 */
11010 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
11013 /* VEX_W_0FC4_P_2 */
11014 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
11017 /* VEX_W_0FC5_P_2 */
11018 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
11021 /* VEX_W_0FD0_P_2 */
11022 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
11025 /* VEX_W_0FD0_P_3 */
11026 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
11029 /* VEX_W_0FD1_P_2 */
11030 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
11033 /* VEX_W_0FD2_P_2 */
11034 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
11037 /* VEX_W_0FD3_P_2 */
11038 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
11041 /* VEX_W_0FD4_P_2 */
11042 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
11045 /* VEX_W_0FD5_P_2 */
11046 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
11049 /* VEX_W_0FD6_P_2 */
11050 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
11053 /* VEX_W_0FD7_P_2_M_1 */
11054 { "vpmovmskb", { Gdq
, XS
}, 0 },
11057 /* VEX_W_0FD8_P_2 */
11058 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
11061 /* VEX_W_0FD9_P_2 */
11062 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
11065 /* VEX_W_0FDA_P_2 */
11066 { "vpminub", { XM
, Vex
, EXx
}, 0 },
11069 /* VEX_W_0FDB_P_2 */
11070 { "vpand", { XM
, Vex
, EXx
}, 0 },
11073 /* VEX_W_0FDC_P_2 */
11074 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
11077 /* VEX_W_0FDD_P_2 */
11078 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
11081 /* VEX_W_0FDE_P_2 */
11082 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
11085 /* VEX_W_0FDF_P_2 */
11086 { "vpandn", { XM
, Vex
, EXx
}, 0 },
11089 /* VEX_W_0FE0_P_2 */
11090 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
11093 /* VEX_W_0FE1_P_2 */
11094 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
11097 /* VEX_W_0FE2_P_2 */
11098 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
11101 /* VEX_W_0FE3_P_2 */
11102 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
11105 /* VEX_W_0FE4_P_2 */
11106 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
11109 /* VEX_W_0FE5_P_2 */
11110 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
11113 /* VEX_W_0FE6_P_1 */
11114 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
11117 /* VEX_W_0FE6_P_2 */
11118 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
11121 /* VEX_W_0FE6_P_3 */
11122 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
11125 /* VEX_W_0FE7_P_2_M_0 */
11126 { "vmovntdq", { Mx
, XM
}, 0 },
11129 /* VEX_W_0FE8_P_2 */
11130 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
11133 /* VEX_W_0FE9_P_2 */
11134 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
11137 /* VEX_W_0FEA_P_2 */
11138 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
11141 /* VEX_W_0FEB_P_2 */
11142 { "vpor", { XM
, Vex
, EXx
}, 0 },
11145 /* VEX_W_0FEC_P_2 */
11146 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
11149 /* VEX_W_0FED_P_2 */
11150 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
11153 /* VEX_W_0FEE_P_2 */
11154 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
11157 /* VEX_W_0FEF_P_2 */
11158 { "vpxor", { XM
, Vex
, EXx
}, 0 },
11161 /* VEX_W_0FF0_P_3_M_0 */
11162 { "vlddqu", { XM
, M
}, 0 },
11165 /* VEX_W_0FF1_P_2 */
11166 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
11169 /* VEX_W_0FF2_P_2 */
11170 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
11173 /* VEX_W_0FF3_P_2 */
11174 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
11177 /* VEX_W_0FF4_P_2 */
11178 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
11181 /* VEX_W_0FF5_P_2 */
11182 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
11185 /* VEX_W_0FF6_P_2 */
11186 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
11189 /* VEX_W_0FF7_P_2 */
11190 { "vmaskmovdqu", { XM
, XS
}, 0 },
11193 /* VEX_W_0FF8_P_2 */
11194 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
11197 /* VEX_W_0FF9_P_2 */
11198 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
11201 /* VEX_W_0FFA_P_2 */
11202 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
11205 /* VEX_W_0FFB_P_2 */
11206 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
11209 /* VEX_W_0FFC_P_2 */
11210 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
11213 /* VEX_W_0FFD_P_2 */
11214 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
11217 /* VEX_W_0FFE_P_2 */
11218 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
11221 /* VEX_W_0F3800_P_2 */
11222 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
11225 /* VEX_W_0F3801_P_2 */
11226 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
11229 /* VEX_W_0F3802_P_2 */
11230 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
11233 /* VEX_W_0F3803_P_2 */
11234 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
11237 /* VEX_W_0F3804_P_2 */
11238 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
11241 /* VEX_W_0F3805_P_2 */
11242 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
11245 /* VEX_W_0F3806_P_2 */
11246 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
11249 /* VEX_W_0F3807_P_2 */
11250 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
11253 /* VEX_W_0F3808_P_2 */
11254 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
11257 /* VEX_W_0F3809_P_2 */
11258 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
11261 /* VEX_W_0F380A_P_2 */
11262 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
11265 /* VEX_W_0F380B_P_2 */
11266 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
11269 /* VEX_W_0F380C_P_2 */
11270 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
11273 /* VEX_W_0F380D_P_2 */
11274 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
11277 /* VEX_W_0F380E_P_2 */
11278 { "vtestps", { XM
, EXx
}, 0 },
11281 /* VEX_W_0F380F_P_2 */
11282 { "vtestpd", { XM
, EXx
}, 0 },
11285 /* VEX_W_0F3816_P_2 */
11286 { "vpermps", { XM
, Vex
, EXx
}, 0 },
11289 /* VEX_W_0F3817_P_2 */
11290 { "vptest", { XM
, EXx
}, 0 },
11293 /* VEX_W_0F3818_P_2 */
11294 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
11297 /* VEX_W_0F3819_P_2 */
11298 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
11301 /* VEX_W_0F381A_P_2_M_0 */
11302 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
11305 /* VEX_W_0F381C_P_2 */
11306 { "vpabsb", { XM
, EXx
}, 0 },
11309 /* VEX_W_0F381D_P_2 */
11310 { "vpabsw", { XM
, EXx
}, 0 },
11313 /* VEX_W_0F381E_P_2 */
11314 { "vpabsd", { XM
, EXx
}, 0 },
11317 /* VEX_W_0F3820_P_2 */
11318 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
11321 /* VEX_W_0F3821_P_2 */
11322 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
11325 /* VEX_W_0F3822_P_2 */
11326 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
11329 /* VEX_W_0F3823_P_2 */
11330 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
11333 /* VEX_W_0F3824_P_2 */
11334 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
11337 /* VEX_W_0F3825_P_2 */
11338 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
11341 /* VEX_W_0F3828_P_2 */
11342 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
11345 /* VEX_W_0F3829_P_2 */
11346 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
11349 /* VEX_W_0F382A_P_2_M_0 */
11350 { "vmovntdqa", { XM
, Mx
}, 0 },
11353 /* VEX_W_0F382B_P_2 */
11354 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
11357 /* VEX_W_0F382C_P_2_M_0 */
11358 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
11361 /* VEX_W_0F382D_P_2_M_0 */
11362 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
11365 /* VEX_W_0F382E_P_2_M_0 */
11366 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
11369 /* VEX_W_0F382F_P_2_M_0 */
11370 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
11373 /* VEX_W_0F3830_P_2 */
11374 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
11377 /* VEX_W_0F3831_P_2 */
11378 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
11381 /* VEX_W_0F3832_P_2 */
11382 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
11385 /* VEX_W_0F3833_P_2 */
11386 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
11389 /* VEX_W_0F3834_P_2 */
11390 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
11393 /* VEX_W_0F3835_P_2 */
11394 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
11397 /* VEX_W_0F3836_P_2 */
11398 { "vpermd", { XM
, Vex
, EXx
}, 0 },
11401 /* VEX_W_0F3837_P_2 */
11402 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
11405 /* VEX_W_0F3838_P_2 */
11406 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
11409 /* VEX_W_0F3839_P_2 */
11410 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
11413 /* VEX_W_0F383A_P_2 */
11414 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
11417 /* VEX_W_0F383B_P_2 */
11418 { "vpminud", { XM
, Vex
, EXx
}, 0 },
11421 /* VEX_W_0F383C_P_2 */
11422 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
11425 /* VEX_W_0F383D_P_2 */
11426 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
11429 /* VEX_W_0F383E_P_2 */
11430 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
11433 /* VEX_W_0F383F_P_2 */
11434 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
11437 /* VEX_W_0F3840_P_2 */
11438 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
11441 /* VEX_W_0F3841_P_2 */
11442 { "vphminposuw", { XM
, EXx
}, 0 },
11445 /* VEX_W_0F3846_P_2 */
11446 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
11449 /* VEX_W_0F3858_P_2 */
11450 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
11453 /* VEX_W_0F3859_P_2 */
11454 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
11457 /* VEX_W_0F385A_P_2_M_0 */
11458 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
11461 /* VEX_W_0F3878_P_2 */
11462 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
11465 /* VEX_W_0F3879_P_2 */
11466 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
11469 /* VEX_W_0F38DB_P_2 */
11470 { "vaesimc", { XM
, EXx
}, 0 },
11473 /* VEX_W_0F38DC_P_2 */
11474 { "vaesenc", { XM
, Vex128
, EXx
}, 0 },
11477 /* VEX_W_0F38DD_P_2 */
11478 { "vaesenclast", { XM
, Vex128
, EXx
}, 0 },
11481 /* VEX_W_0F38DE_P_2 */
11482 { "vaesdec", { XM
, Vex128
, EXx
}, 0 },
11485 /* VEX_W_0F38DF_P_2 */
11486 { "vaesdeclast", { XM
, Vex128
, EXx
}, 0 },
11489 /* VEX_W_0F3A00_P_2 */
11491 { "vpermq", { XM
, EXx
, Ib
}, 0 },
11494 /* VEX_W_0F3A01_P_2 */
11496 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
11499 /* VEX_W_0F3A02_P_2 */
11500 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
11503 /* VEX_W_0F3A04_P_2 */
11504 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
11507 /* VEX_W_0F3A05_P_2 */
11508 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
11511 /* VEX_W_0F3A06_P_2 */
11512 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11515 /* VEX_W_0F3A08_P_2 */
11516 { "vroundps", { XM
, EXx
, Ib
}, 0 },
11519 /* VEX_W_0F3A09_P_2 */
11520 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
11523 /* VEX_W_0F3A0A_P_2 */
11524 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
11527 /* VEX_W_0F3A0B_P_2 */
11528 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
11531 /* VEX_W_0F3A0C_P_2 */
11532 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
11535 /* VEX_W_0F3A0D_P_2 */
11536 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
11539 /* VEX_W_0F3A0E_P_2 */
11540 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
11543 /* VEX_W_0F3A0F_P_2 */
11544 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
11547 /* VEX_W_0F3A14_P_2 */
11548 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
11551 /* VEX_W_0F3A15_P_2 */
11552 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
11555 /* VEX_W_0F3A18_P_2 */
11556 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11559 /* VEX_W_0F3A19_P_2 */
11560 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
11563 /* VEX_W_0F3A20_P_2 */
11564 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
11567 /* VEX_W_0F3A21_P_2 */
11568 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
11571 /* VEX_W_0F3A30_P_2_LEN_0 */
11572 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
11573 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
11576 /* VEX_W_0F3A31_P_2_LEN_0 */
11577 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
11578 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
11581 /* VEX_W_0F3A32_P_2_LEN_0 */
11582 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
11583 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
11586 /* VEX_W_0F3A33_P_2_LEN_0 */
11587 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
11588 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
11591 /* VEX_W_0F3A38_P_2 */
11592 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11595 /* VEX_W_0F3A39_P_2 */
11596 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
11599 /* VEX_W_0F3A40_P_2 */
11600 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
11603 /* VEX_W_0F3A41_P_2 */
11604 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
11607 /* VEX_W_0F3A42_P_2 */
11608 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
11611 /* VEX_W_0F3A44_P_2 */
11612 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
}, 0 },
11615 /* VEX_W_0F3A46_P_2 */
11616 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11619 /* VEX_W_0F3A48_P_2 */
11620 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11621 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11624 /* VEX_W_0F3A49_P_2 */
11625 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11626 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11629 /* VEX_W_0F3A4A_P_2 */
11630 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11633 /* VEX_W_0F3A4B_P_2 */
11634 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11637 /* VEX_W_0F3A4C_P_2 */
11638 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11641 /* VEX_W_0F3A60_P_2 */
11642 { "vpcmpestrm", { XM
, EXx
, Ib
}, 0 },
11645 /* VEX_W_0F3A61_P_2 */
11646 { "vpcmpestri", { XM
, EXx
, Ib
}, 0 },
11649 /* VEX_W_0F3A62_P_2 */
11650 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
11653 /* VEX_W_0F3A63_P_2 */
11654 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
11657 /* VEX_W_0F3ADF_P_2 */
11658 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
11660 #define NEED_VEX_W_TABLE
11661 #include "i386-dis-evex.h"
11662 #undef NEED_VEX_W_TABLE
11665 static const struct dis386 mod_table
[][2] = {
11668 { "leaS", { Gv
, M
}, 0 },
11673 { RM_TABLE (RM_C6_REG_7
) },
11678 { RM_TABLE (RM_C7_REG_7
) },
11682 { "Jcall^", { indirEp
}, 0 },
11686 { "Jjmp^", { indirEp
}, 0 },
11689 /* MOD_0F01_REG_0 */
11690 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11691 { RM_TABLE (RM_0F01_REG_0
) },
11694 /* MOD_0F01_REG_1 */
11695 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11696 { RM_TABLE (RM_0F01_REG_1
) },
11699 /* MOD_0F01_REG_2 */
11700 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11701 { RM_TABLE (RM_0F01_REG_2
) },
11704 /* MOD_0F01_REG_3 */
11705 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11706 { RM_TABLE (RM_0F01_REG_3
) },
11709 /* MOD_0F01_REG_5 */
11711 { RM_TABLE (RM_0F01_REG_5
) },
11714 /* MOD_0F01_REG_7 */
11715 { "invlpg", { Mb
}, 0 },
11716 { RM_TABLE (RM_0F01_REG_7
) },
11719 /* MOD_0F12_PREFIX_0 */
11720 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
11721 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
11725 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
11728 /* MOD_0F16_PREFIX_0 */
11729 { "movhps", { XM
, EXq
}, 0 },
11730 { "movlhps", { XM
, EXq
}, 0 },
11734 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
11737 /* MOD_0F18_REG_0 */
11738 { "prefetchnta", { Mb
}, 0 },
11741 /* MOD_0F18_REG_1 */
11742 { "prefetcht0", { Mb
}, 0 },
11745 /* MOD_0F18_REG_2 */
11746 { "prefetcht1", { Mb
}, 0 },
11749 /* MOD_0F18_REG_3 */
11750 { "prefetcht2", { Mb
}, 0 },
11753 /* MOD_0F18_REG_4 */
11754 { "nop/reserved", { Mb
}, 0 },
11757 /* MOD_0F18_REG_5 */
11758 { "nop/reserved", { Mb
}, 0 },
11761 /* MOD_0F18_REG_6 */
11762 { "nop/reserved", { Mb
}, 0 },
11765 /* MOD_0F18_REG_7 */
11766 { "nop/reserved", { Mb
}, 0 },
11769 /* MOD_0F1A_PREFIX_0 */
11770 { "bndldx", { Gbnd
, Ev_bnd
}, 0 },
11771 { "nopQ", { Ev
}, 0 },
11774 /* MOD_0F1B_PREFIX_0 */
11775 { "bndstx", { Ev_bnd
, Gbnd
}, 0 },
11776 { "nopQ", { Ev
}, 0 },
11779 /* MOD_0F1B_PREFIX_1 */
11780 { "bndmk", { Gbnd
, Ev_bnd
}, 0 },
11781 { "nopQ", { Ev
}, 0 },
11786 { "movL", { Rd
, Td
}, 0 },
11791 { "movL", { Td
, Rd
}, 0 },
11794 /* MOD_0F2B_PREFIX_0 */
11795 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
11798 /* MOD_0F2B_PREFIX_1 */
11799 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
11802 /* MOD_0F2B_PREFIX_2 */
11803 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
11806 /* MOD_0F2B_PREFIX_3 */
11807 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
11812 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
11815 /* MOD_0F71_REG_2 */
11817 { "psrlw", { MS
, Ib
}, 0 },
11820 /* MOD_0F71_REG_4 */
11822 { "psraw", { MS
, Ib
}, 0 },
11825 /* MOD_0F71_REG_6 */
11827 { "psllw", { MS
, Ib
}, 0 },
11830 /* MOD_0F72_REG_2 */
11832 { "psrld", { MS
, Ib
}, 0 },
11835 /* MOD_0F72_REG_4 */
11837 { "psrad", { MS
, Ib
}, 0 },
11840 /* MOD_0F72_REG_6 */
11842 { "pslld", { MS
, Ib
}, 0 },
11845 /* MOD_0F73_REG_2 */
11847 { "psrlq", { MS
, Ib
}, 0 },
11850 /* MOD_0F73_REG_3 */
11852 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11855 /* MOD_0F73_REG_6 */
11857 { "psllq", { MS
, Ib
}, 0 },
11860 /* MOD_0F73_REG_7 */
11862 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11865 /* MOD_0FAE_REG_0 */
11866 { "fxsave", { FXSAVE
}, 0 },
11867 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11870 /* MOD_0FAE_REG_1 */
11871 { "fxrstor", { FXSAVE
}, 0 },
11872 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11875 /* MOD_0FAE_REG_2 */
11876 { "ldmxcsr", { Md
}, 0 },
11877 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11880 /* MOD_0FAE_REG_3 */
11881 { "stmxcsr", { Md
}, 0 },
11882 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11885 /* MOD_0FAE_REG_4 */
11886 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4
) },
11887 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4
) },
11890 /* MOD_0FAE_REG_5 */
11891 { "xrstor", { FXSAVE
}, 0 },
11892 { RM_TABLE (RM_0FAE_REG_5
) },
11895 /* MOD_0FAE_REG_6 */
11896 { PREFIX_TABLE (PREFIX_0FAE_REG_6
) },
11897 { RM_TABLE (RM_0FAE_REG_6
) },
11900 /* MOD_0FAE_REG_7 */
11901 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11902 { RM_TABLE (RM_0FAE_REG_7
) },
11906 { "lssS", { Gv
, Mp
}, 0 },
11910 { "lfsS", { Gv
, Mp
}, 0 },
11914 { "lgsS", { Gv
, Mp
}, 0 },
11918 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
11921 /* MOD_0FC7_REG_3 */
11922 { "xrstors", { FXSAVE
}, 0 },
11925 /* MOD_0FC7_REG_4 */
11926 { "xsavec", { FXSAVE
}, 0 },
11929 /* MOD_0FC7_REG_5 */
11930 { "xsaves", { FXSAVE
}, 0 },
11933 /* MOD_0FC7_REG_6 */
11934 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
11935 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
11938 /* MOD_0FC7_REG_7 */
11939 { "vmptrst", { Mq
}, 0 },
11940 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
11945 { "pmovmskb", { Gdq
, MS
}, 0 },
11948 /* MOD_0FE7_PREFIX_2 */
11949 { "movntdq", { Mx
, XM
}, 0 },
11952 /* MOD_0FF0_PREFIX_3 */
11953 { "lddqu", { XM
, M
}, 0 },
11956 /* MOD_0F382A_PREFIX_2 */
11957 { "movntdqa", { XM
, Mx
}, 0 },
11961 { "bound{S|}", { Gv
, Ma
}, 0 },
11962 { EVEX_TABLE (EVEX_0F
) },
11966 { "lesS", { Gv
, Mp
}, 0 },
11967 { VEX_C4_TABLE (VEX_0F
) },
11971 { "ldsS", { Gv
, Mp
}, 0 },
11972 { VEX_C5_TABLE (VEX_0F
) },
11975 /* MOD_VEX_0F12_PREFIX_0 */
11976 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11977 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11981 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11984 /* MOD_VEX_0F16_PREFIX_0 */
11985 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11986 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11990 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11994 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11997 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11999 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
12002 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
12004 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
12007 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
12009 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
12012 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
12014 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
12017 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
12019 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
12022 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
12024 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
12027 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
12029 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
12032 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
12034 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
12037 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
12039 { "knotw", { MaskG
, MaskR
}, 0 },
12042 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
12044 { "knotq", { MaskG
, MaskR
}, 0 },
12047 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
12049 { "knotb", { MaskG
, MaskR
}, 0 },
12052 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
12054 { "knotd", { MaskG
, MaskR
}, 0 },
12057 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
12059 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
12062 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
12064 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
12067 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
12069 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
12072 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
12074 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
12077 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
12079 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
12082 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
12084 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
12087 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
12089 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
12092 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
12094 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
12097 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12099 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
12102 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12104 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
12107 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12109 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
12112 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12114 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
12117 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12119 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
12122 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12124 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
12127 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12129 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
12132 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12134 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
12137 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12139 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
12142 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12144 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
12147 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12149 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
12154 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
12157 /* MOD_VEX_0F71_REG_2 */
12159 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
12162 /* MOD_VEX_0F71_REG_4 */
12164 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
12167 /* MOD_VEX_0F71_REG_6 */
12169 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
12172 /* MOD_VEX_0F72_REG_2 */
12174 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
12177 /* MOD_VEX_0F72_REG_4 */
12179 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
12182 /* MOD_VEX_0F72_REG_6 */
12184 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
12187 /* MOD_VEX_0F73_REG_2 */
12189 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
12192 /* MOD_VEX_0F73_REG_3 */
12194 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
12197 /* MOD_VEX_0F73_REG_6 */
12199 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
12202 /* MOD_VEX_0F73_REG_7 */
12204 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
12207 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12208 { "kmovw", { Ew
, MaskG
}, 0 },
12212 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12213 { "kmovq", { Eq
, MaskG
}, 0 },
12217 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12218 { "kmovb", { Eb
, MaskG
}, 0 },
12222 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12223 { "kmovd", { Ed
, MaskG
}, 0 },
12227 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12229 { "kmovw", { MaskG
, Rdq
}, 0 },
12232 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12234 { "kmovb", { MaskG
, Rdq
}, 0 },
12237 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12239 { "kmovd", { MaskG
, Rdq
}, 0 },
12242 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12244 { "kmovq", { MaskG
, Rdq
}, 0 },
12247 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12249 { "kmovw", { Gdq
, MaskR
}, 0 },
12252 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12254 { "kmovb", { Gdq
, MaskR
}, 0 },
12257 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12259 { "kmovd", { Gdq
, MaskR
}, 0 },
12262 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12264 { "kmovq", { Gdq
, MaskR
}, 0 },
12267 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12269 { "kortestw", { MaskG
, MaskR
}, 0 },
12272 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12274 { "kortestq", { MaskG
, MaskR
}, 0 },
12277 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12279 { "kortestb", { MaskG
, MaskR
}, 0 },
12282 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12284 { "kortestd", { MaskG
, MaskR
}, 0 },
12287 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12289 { "ktestw", { MaskG
, MaskR
}, 0 },
12292 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12294 { "ktestq", { MaskG
, MaskR
}, 0 },
12297 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12299 { "ktestb", { MaskG
, MaskR
}, 0 },
12302 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12304 { "ktestd", { MaskG
, MaskR
}, 0 },
12307 /* MOD_VEX_0FAE_REG_2 */
12308 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
12311 /* MOD_VEX_0FAE_REG_3 */
12312 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
12315 /* MOD_VEX_0FD7_PREFIX_2 */
12317 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
12320 /* MOD_VEX_0FE7_PREFIX_2 */
12321 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
12324 /* MOD_VEX_0FF0_PREFIX_3 */
12325 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
12328 /* MOD_VEX_0F381A_PREFIX_2 */
12329 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
12332 /* MOD_VEX_0F382A_PREFIX_2 */
12333 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
12336 /* MOD_VEX_0F382C_PREFIX_2 */
12337 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
12340 /* MOD_VEX_0F382D_PREFIX_2 */
12341 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
12344 /* MOD_VEX_0F382E_PREFIX_2 */
12345 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
12348 /* MOD_VEX_0F382F_PREFIX_2 */
12349 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
12352 /* MOD_VEX_0F385A_PREFIX_2 */
12353 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
12356 /* MOD_VEX_0F388C_PREFIX_2 */
12357 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
12360 /* MOD_VEX_0F388E_PREFIX_2 */
12361 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
12364 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12366 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
12369 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12371 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
12374 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12376 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
12379 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12381 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
12384 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12386 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
12389 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12391 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
12394 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12396 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
12399 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12401 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
12403 #define NEED_MOD_TABLE
12404 #include "i386-dis-evex.h"
12405 #undef NEED_MOD_TABLE
12408 static const struct dis386 rm_table
[][8] = {
12411 { "xabort", { Skip_MODRM
, Ib
}, 0 },
12415 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
12418 /* RM_0F01_REG_0 */
12420 { "vmcall", { Skip_MODRM
}, 0 },
12421 { "vmlaunch", { Skip_MODRM
}, 0 },
12422 { "vmresume", { Skip_MODRM
}, 0 },
12423 { "vmxoff", { Skip_MODRM
}, 0 },
12426 /* RM_0F01_REG_1 */
12427 { "monitor", { { OP_Monitor
, 0 } }, 0 },
12428 { "mwait", { { OP_Mwait
, 0 } }, 0 },
12429 { "clac", { Skip_MODRM
}, 0 },
12430 { "stac", { Skip_MODRM
}, 0 },
12434 { "encls", { Skip_MODRM
}, 0 },
12437 /* RM_0F01_REG_2 */
12438 { "xgetbv", { Skip_MODRM
}, 0 },
12439 { "xsetbv", { Skip_MODRM
}, 0 },
12442 { "vmfunc", { Skip_MODRM
}, 0 },
12443 { "xend", { Skip_MODRM
}, 0 },
12444 { "xtest", { Skip_MODRM
}, 0 },
12445 { "enclu", { Skip_MODRM
}, 0 },
12448 /* RM_0F01_REG_3 */
12449 { "vmrun", { Skip_MODRM
}, 0 },
12450 { "vmmcall", { Skip_MODRM
}, 0 },
12451 { "vmload", { Skip_MODRM
}, 0 },
12452 { "vmsave", { Skip_MODRM
}, 0 },
12453 { "stgi", { Skip_MODRM
}, 0 },
12454 { "clgi", { Skip_MODRM
}, 0 },
12455 { "skinit", { Skip_MODRM
}, 0 },
12456 { "invlpga", { Skip_MODRM
}, 0 },
12459 /* RM_0F01_REG_5 */
12466 { "rdpkru", { Skip_MODRM
}, 0 },
12467 { "wrpkru", { Skip_MODRM
}, 0 },
12470 /* RM_0F01_REG_7 */
12471 { "swapgs", { Skip_MODRM
}, 0 },
12472 { "rdtscp", { Skip_MODRM
}, 0 },
12473 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
12474 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
12475 { "clzero", { Skip_MODRM
}, 0 },
12478 /* RM_0FAE_REG_5 */
12479 { "lfence", { Skip_MODRM
}, 0 },
12482 /* RM_0FAE_REG_6 */
12483 { "mfence", { Skip_MODRM
}, 0 },
12486 /* RM_0FAE_REG_7 */
12487 { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7
) },
12491 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12493 /* We use the high bit to indicate different name for the same
12495 #define REP_PREFIX (0xf3 | 0x100)
12496 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12497 #define XRELEASE_PREFIX (0xf3 | 0x400)
12498 #define BND_PREFIX (0xf2 | 0x400)
12503 int newrex
, i
, length
;
12509 last_lock_prefix
= -1;
12510 last_repz_prefix
= -1;
12511 last_repnz_prefix
= -1;
12512 last_data_prefix
= -1;
12513 last_addr_prefix
= -1;
12514 last_rex_prefix
= -1;
12515 last_seg_prefix
= -1;
12517 active_seg_prefix
= 0;
12518 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12519 all_prefixes
[i
] = 0;
12522 /* The maximum instruction length is 15bytes. */
12523 while (length
< MAX_CODE_LENGTH
- 1)
12525 FETCH_DATA (the_info
, codep
+ 1);
12529 /* REX prefixes family. */
12546 if (address_mode
== mode_64bit
)
12550 last_rex_prefix
= i
;
12553 prefixes
|= PREFIX_REPZ
;
12554 last_repz_prefix
= i
;
12557 prefixes
|= PREFIX_REPNZ
;
12558 last_repnz_prefix
= i
;
12561 prefixes
|= PREFIX_LOCK
;
12562 last_lock_prefix
= i
;
12565 prefixes
|= PREFIX_CS
;
12566 last_seg_prefix
= i
;
12567 active_seg_prefix
= PREFIX_CS
;
12570 prefixes
|= PREFIX_SS
;
12571 last_seg_prefix
= i
;
12572 active_seg_prefix
= PREFIX_SS
;
12575 prefixes
|= PREFIX_DS
;
12576 last_seg_prefix
= i
;
12577 active_seg_prefix
= PREFIX_DS
;
12580 prefixes
|= PREFIX_ES
;
12581 last_seg_prefix
= i
;
12582 active_seg_prefix
= PREFIX_ES
;
12585 prefixes
|= PREFIX_FS
;
12586 last_seg_prefix
= i
;
12587 active_seg_prefix
= PREFIX_FS
;
12590 prefixes
|= PREFIX_GS
;
12591 last_seg_prefix
= i
;
12592 active_seg_prefix
= PREFIX_GS
;
12595 prefixes
|= PREFIX_DATA
;
12596 last_data_prefix
= i
;
12599 prefixes
|= PREFIX_ADDR
;
12600 last_addr_prefix
= i
;
12603 /* fwait is really an instruction. If there are prefixes
12604 before the fwait, they belong to the fwait, *not* to the
12605 following instruction. */
12607 if (prefixes
|| rex
)
12609 prefixes
|= PREFIX_FWAIT
;
12611 /* This ensures that the previous REX prefixes are noticed
12612 as unused prefixes, as in the return case below. */
12616 prefixes
= PREFIX_FWAIT
;
12621 /* Rex is ignored when followed by another prefix. */
12627 if (*codep
!= FWAIT_OPCODE
)
12628 all_prefixes
[i
++] = *codep
;
12636 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12639 static const char *
12640 prefix_name (int pref
, int sizeflag
)
12642 static const char *rexes
[16] =
12645 "rex.B", /* 0x41 */
12646 "rex.X", /* 0x42 */
12647 "rex.XB", /* 0x43 */
12648 "rex.R", /* 0x44 */
12649 "rex.RB", /* 0x45 */
12650 "rex.RX", /* 0x46 */
12651 "rex.RXB", /* 0x47 */
12652 "rex.W", /* 0x48 */
12653 "rex.WB", /* 0x49 */
12654 "rex.WX", /* 0x4a */
12655 "rex.WXB", /* 0x4b */
12656 "rex.WR", /* 0x4c */
12657 "rex.WRB", /* 0x4d */
12658 "rex.WRX", /* 0x4e */
12659 "rex.WRXB", /* 0x4f */
12664 /* REX prefixes family. */
12681 return rexes
[pref
- 0x40];
12701 return (sizeflag
& DFLAG
) ? "data16" : "data32";
12703 if (address_mode
== mode_64bit
)
12704 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
12706 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
12711 case XACQUIRE_PREFIX
:
12713 case XRELEASE_PREFIX
:
12722 static char op_out
[MAX_OPERANDS
][100];
12723 static int op_ad
, op_index
[MAX_OPERANDS
];
12724 static int two_source_ops
;
12725 static bfd_vma op_address
[MAX_OPERANDS
];
12726 static bfd_vma op_riprel
[MAX_OPERANDS
];
12727 static bfd_vma start_pc
;
12730 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12731 * (see topic "Redundant prefixes" in the "Differences from 8086"
12732 * section of the "Virtual 8086 Mode" chapter.)
12733 * 'pc' should be the address of this instruction, it will
12734 * be used to print the target address if this is a relative jump or call
12735 * The function returns the length of this instruction in bytes.
12738 static char intel_syntax
;
12739 static char intel_mnemonic
= !SYSV386_COMPAT
;
12740 static char open_char
;
12741 static char close_char
;
12742 static char separator_char
;
12743 static char scale_char
;
12751 static enum x86_64_isa isa64
;
12753 /* Here for backwards compatibility. When gdb stops using
12754 print_insn_i386_att and print_insn_i386_intel these functions can
12755 disappear, and print_insn_i386 be merged into print_insn. */
12757 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
12761 return print_insn (pc
, info
);
12765 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
12769 return print_insn (pc
, info
);
12773 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
12777 return print_insn (pc
, info
);
12781 print_i386_disassembler_options (FILE *stream
)
12783 fprintf (stream
, _("\n\
12784 The following i386/x86-64 specific disassembler options are supported for use\n\
12785 with the -M switch (multiple options should be separated by commas):\n"));
12787 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
12788 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
12789 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
12790 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
12791 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
12792 fprintf (stream
, _(" att-mnemonic\n"
12793 " Display instruction in AT&T mnemonic\n"));
12794 fprintf (stream
, _(" intel-mnemonic\n"
12795 " Display instruction in Intel mnemonic\n"));
12796 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
12797 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
12798 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
12799 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
12800 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
12801 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12802 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
12803 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
12807 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
12809 /* Get a pointer to struct dis386 with a valid name. */
12811 static const struct dis386
*
12812 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
12814 int vindex
, vex_table_index
;
12816 if (dp
->name
!= NULL
)
12819 switch (dp
->op
[0].bytemode
)
12821 case USE_REG_TABLE
:
12822 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
12825 case USE_MOD_TABLE
:
12826 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
12827 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
12831 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
12834 case USE_PREFIX_TABLE
:
12837 /* The prefix in VEX is implicit. */
12838 switch (vex
.prefix
)
12843 case REPE_PREFIX_OPCODE
:
12846 case DATA_PREFIX_OPCODE
:
12849 case REPNE_PREFIX_OPCODE
:
12859 int last_prefix
= -1;
12862 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12863 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12865 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12867 if (last_repz_prefix
> last_repnz_prefix
)
12870 prefix
= PREFIX_REPZ
;
12871 last_prefix
= last_repz_prefix
;
12876 prefix
= PREFIX_REPNZ
;
12877 last_prefix
= last_repnz_prefix
;
12880 /* Check if prefix should be ignored. */
12881 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
12882 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
12887 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12890 prefix
= PREFIX_DATA
;
12891 last_prefix
= last_data_prefix
;
12896 used_prefixes
|= prefix
;
12897 all_prefixes
[last_prefix
] = 0;
12900 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12903 case USE_X86_64_TABLE
:
12904 vindex
= address_mode
== mode_64bit
? 1 : 0;
12905 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12908 case USE_3BYTE_TABLE
:
12909 FETCH_DATA (info
, codep
+ 2);
12911 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12913 modrm
.mod
= (*codep
>> 6) & 3;
12914 modrm
.reg
= (*codep
>> 3) & 7;
12915 modrm
.rm
= *codep
& 7;
12918 case USE_VEX_LEN_TABLE
:
12922 switch (vex
.length
)
12935 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12938 case USE_XOP_8F_TABLE
:
12939 FETCH_DATA (info
, codep
+ 3);
12940 /* All bits in the REX prefix are ignored. */
12942 rex
= ~(*codep
>> 5) & 0x7;
12944 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12945 switch ((*codep
& 0x1f))
12951 vex_table_index
= XOP_08
;
12954 vex_table_index
= XOP_09
;
12957 vex_table_index
= XOP_0A
;
12961 vex
.w
= *codep
& 0x80;
12962 if (vex
.w
&& address_mode
== mode_64bit
)
12965 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12966 if (address_mode
!= mode_64bit
12967 && vex
.register_specifier
> 0x7)
12973 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12974 switch ((*codep
& 0x3))
12980 vex
.prefix
= DATA_PREFIX_OPCODE
;
12983 vex
.prefix
= REPE_PREFIX_OPCODE
;
12986 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12993 dp
= &xop_table
[vex_table_index
][vindex
];
12996 FETCH_DATA (info
, codep
+ 1);
12997 modrm
.mod
= (*codep
>> 6) & 3;
12998 modrm
.reg
= (*codep
>> 3) & 7;
12999 modrm
.rm
= *codep
& 7;
13002 case USE_VEX_C4_TABLE
:
13004 FETCH_DATA (info
, codep
+ 3);
13005 /* All bits in the REX prefix are ignored. */
13007 rex
= ~(*codep
>> 5) & 0x7;
13008 switch ((*codep
& 0x1f))
13014 vex_table_index
= VEX_0F
;
13017 vex_table_index
= VEX_0F38
;
13020 vex_table_index
= VEX_0F3A
;
13024 vex
.w
= *codep
& 0x80;
13025 if (vex
.w
&& address_mode
== mode_64bit
)
13028 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
13029 if (address_mode
!= mode_64bit
13030 && vex
.register_specifier
> 0x7)
13036 vex
.length
= (*codep
& 0x4) ? 256 : 128;
13037 switch ((*codep
& 0x3))
13043 vex
.prefix
= DATA_PREFIX_OPCODE
;
13046 vex
.prefix
= REPE_PREFIX_OPCODE
;
13049 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13056 dp
= &vex_table
[vex_table_index
][vindex
];
13058 /* There is no MODRM byte for VEX [82|77]. */
13059 if (vindex
!= 0x77 && vindex
!= 0x82)
13061 FETCH_DATA (info
, codep
+ 1);
13062 modrm
.mod
= (*codep
>> 6) & 3;
13063 modrm
.reg
= (*codep
>> 3) & 7;
13064 modrm
.rm
= *codep
& 7;
13068 case USE_VEX_C5_TABLE
:
13070 FETCH_DATA (info
, codep
+ 2);
13071 /* All bits in the REX prefix are ignored. */
13073 rex
= (*codep
& 0x80) ? 0 : REX_R
;
13075 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
13076 if (address_mode
!= mode_64bit
13077 && vex
.register_specifier
> 0x7)
13085 vex
.length
= (*codep
& 0x4) ? 256 : 128;
13086 switch ((*codep
& 0x3))
13092 vex
.prefix
= DATA_PREFIX_OPCODE
;
13095 vex
.prefix
= REPE_PREFIX_OPCODE
;
13098 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13105 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
13107 /* There is no MODRM byte for VEX [82|77]. */
13108 if (vindex
!= 0x77 && vindex
!= 0x82)
13110 FETCH_DATA (info
, codep
+ 1);
13111 modrm
.mod
= (*codep
>> 6) & 3;
13112 modrm
.reg
= (*codep
>> 3) & 7;
13113 modrm
.rm
= *codep
& 7;
13117 case USE_VEX_W_TABLE
:
13121 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
13124 case USE_EVEX_TABLE
:
13125 two_source_ops
= 0;
13128 FETCH_DATA (info
, codep
+ 4);
13129 /* All bits in the REX prefix are ignored. */
13131 /* The first byte after 0x62. */
13132 rex
= ~(*codep
>> 5) & 0x7;
13133 vex
.r
= *codep
& 0x10;
13134 switch ((*codep
& 0xf))
13137 return &bad_opcode
;
13139 vex_table_index
= EVEX_0F
;
13142 vex_table_index
= EVEX_0F38
;
13145 vex_table_index
= EVEX_0F3A
;
13149 /* The second byte after 0x62. */
13151 vex
.w
= *codep
& 0x80;
13152 if (vex
.w
&& address_mode
== mode_64bit
)
13155 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
13156 if (address_mode
!= mode_64bit
)
13158 /* In 16/32-bit mode silently ignore following bits. */
13162 vex
.register_specifier
&= 0x7;
13166 if (!(*codep
& 0x4))
13167 return &bad_opcode
;
13169 switch ((*codep
& 0x3))
13175 vex
.prefix
= DATA_PREFIX_OPCODE
;
13178 vex
.prefix
= REPE_PREFIX_OPCODE
;
13181 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13185 /* The third byte after 0x62. */
13188 /* Remember the static rounding bits. */
13189 vex
.ll
= (*codep
>> 5) & 3;
13190 vex
.b
= (*codep
& 0x10) != 0;
13192 vex
.v
= *codep
& 0x8;
13193 vex
.mask_register_specifier
= *codep
& 0x7;
13194 vex
.zeroing
= *codep
& 0x80;
13200 dp
= &evex_table
[vex_table_index
][vindex
];
13202 FETCH_DATA (info
, codep
+ 1);
13203 modrm
.mod
= (*codep
>> 6) & 3;
13204 modrm
.reg
= (*codep
>> 3) & 7;
13205 modrm
.rm
= *codep
& 7;
13207 /* Set vector length. */
13208 if (modrm
.mod
== 3 && vex
.b
)
13224 return &bad_opcode
;
13237 if (dp
->name
!= NULL
)
13240 return get_valid_dis386 (dp
, info
);
13244 get_sib (disassemble_info
*info
, int sizeflag
)
13246 /* If modrm.mod == 3, operand must be register. */
13248 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13252 FETCH_DATA (info
, codep
+ 2);
13253 sib
.index
= (codep
[1] >> 3) & 7;
13254 sib
.scale
= (codep
[1] >> 6) & 3;
13255 sib
.base
= codep
[1] & 7;
13260 print_insn (bfd_vma pc
, disassemble_info
*info
)
13262 const struct dis386
*dp
;
13264 char *op_txt
[MAX_OPERANDS
];
13266 int sizeflag
, orig_sizeflag
;
13268 struct dis_private priv
;
13271 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13272 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
13273 address_mode
= mode_32bit
;
13274 else if (info
->mach
== bfd_mach_i386_i8086
)
13276 address_mode
= mode_16bit
;
13277 priv
.orig_sizeflag
= 0;
13280 address_mode
= mode_64bit
;
13282 if (intel_syntax
== (char) -1)
13283 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
13285 for (p
= info
->disassembler_options
; p
!= NULL
; )
13287 if (CONST_STRNEQ (p
, "amd64"))
13289 else if (CONST_STRNEQ (p
, "intel64"))
13291 else if (CONST_STRNEQ (p
, "x86-64"))
13293 address_mode
= mode_64bit
;
13294 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13296 else if (CONST_STRNEQ (p
, "i386"))
13298 address_mode
= mode_32bit
;
13299 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13301 else if (CONST_STRNEQ (p
, "i8086"))
13303 address_mode
= mode_16bit
;
13304 priv
.orig_sizeflag
= 0;
13306 else if (CONST_STRNEQ (p
, "intel"))
13309 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
13310 intel_mnemonic
= 1;
13312 else if (CONST_STRNEQ (p
, "att"))
13315 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
13316 intel_mnemonic
= 0;
13318 else if (CONST_STRNEQ (p
, "addr"))
13320 if (address_mode
== mode_64bit
)
13322 if (p
[4] == '3' && p
[5] == '2')
13323 priv
.orig_sizeflag
&= ~AFLAG
;
13324 else if (p
[4] == '6' && p
[5] == '4')
13325 priv
.orig_sizeflag
|= AFLAG
;
13329 if (p
[4] == '1' && p
[5] == '6')
13330 priv
.orig_sizeflag
&= ~AFLAG
;
13331 else if (p
[4] == '3' && p
[5] == '2')
13332 priv
.orig_sizeflag
|= AFLAG
;
13335 else if (CONST_STRNEQ (p
, "data"))
13337 if (p
[4] == '1' && p
[5] == '6')
13338 priv
.orig_sizeflag
&= ~DFLAG
;
13339 else if (p
[4] == '3' && p
[5] == '2')
13340 priv
.orig_sizeflag
|= DFLAG
;
13342 else if (CONST_STRNEQ (p
, "suffix"))
13343 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
13345 p
= strchr (p
, ',');
13350 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
13352 (*info
->fprintf_func
) (info
->stream
,
13353 _("64-bit address is disabled"));
13359 names64
= intel_names64
;
13360 names32
= intel_names32
;
13361 names16
= intel_names16
;
13362 names8
= intel_names8
;
13363 names8rex
= intel_names8rex
;
13364 names_seg
= intel_names_seg
;
13365 names_mm
= intel_names_mm
;
13366 names_bnd
= intel_names_bnd
;
13367 names_xmm
= intel_names_xmm
;
13368 names_ymm
= intel_names_ymm
;
13369 names_zmm
= intel_names_zmm
;
13370 index64
= intel_index64
;
13371 index32
= intel_index32
;
13372 names_mask
= intel_names_mask
;
13373 index16
= intel_index16
;
13376 separator_char
= '+';
13381 names64
= att_names64
;
13382 names32
= att_names32
;
13383 names16
= att_names16
;
13384 names8
= att_names8
;
13385 names8rex
= att_names8rex
;
13386 names_seg
= att_names_seg
;
13387 names_mm
= att_names_mm
;
13388 names_bnd
= att_names_bnd
;
13389 names_xmm
= att_names_xmm
;
13390 names_ymm
= att_names_ymm
;
13391 names_zmm
= att_names_zmm
;
13392 index64
= att_index64
;
13393 index32
= att_index32
;
13394 names_mask
= att_names_mask
;
13395 index16
= att_index16
;
13398 separator_char
= ',';
13402 /* The output looks better if we put 7 bytes on a line, since that
13403 puts most long word instructions on a single line. Use 8 bytes
13405 if ((info
->mach
& bfd_mach_l1om
) != 0)
13406 info
->bytes_per_line
= 8;
13408 info
->bytes_per_line
= 7;
13410 info
->private_data
= &priv
;
13411 priv
.max_fetched
= priv
.the_buffer
;
13412 priv
.insn_start
= pc
;
13415 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13423 start_codep
= priv
.the_buffer
;
13424 codep
= priv
.the_buffer
;
13426 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
13430 /* Getting here means we tried for data but didn't get it. That
13431 means we have an incomplete instruction of some sort. Just
13432 print the first byte as a prefix or a .byte pseudo-op. */
13433 if (codep
> priv
.the_buffer
)
13435 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
13437 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
13440 /* Just print the first byte as a .byte instruction. */
13441 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
13442 (unsigned int) priv
.the_buffer
[0]);
13452 sizeflag
= priv
.orig_sizeflag
;
13454 if (!ckprefix () || rex_used
)
13456 /* Too many prefixes or unused REX prefixes. */
13458 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
13460 (*info
->fprintf_func
) (info
->stream
, "%s%s",
13462 prefix_name (all_prefixes
[i
], sizeflag
));
13466 insn_codep
= codep
;
13468 FETCH_DATA (info
, codep
+ 1);
13469 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
13471 if (((prefixes
& PREFIX_FWAIT
)
13472 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
13474 /* Handle prefixes before fwait. */
13475 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
13477 (*info
->fprintf_func
) (info
->stream
, "%s ",
13478 prefix_name (all_prefixes
[i
], sizeflag
));
13479 (*info
->fprintf_func
) (info
->stream
, "fwait");
13483 if (*codep
== 0x0f)
13485 unsigned char threebyte
;
13488 FETCH_DATA (info
, codep
+ 1);
13489 threebyte
= *codep
;
13490 dp
= &dis386_twobyte
[threebyte
];
13491 need_modrm
= twobyte_has_modrm
[*codep
];
13496 dp
= &dis386
[*codep
];
13497 need_modrm
= onebyte_has_modrm
[*codep
];
13501 /* Save sizeflag for printing the extra prefixes later before updating
13502 it for mnemonic and operand processing. The prefix names depend
13503 only on the address mode. */
13504 orig_sizeflag
= sizeflag
;
13505 if (prefixes
& PREFIX_ADDR
)
13507 if ((prefixes
& PREFIX_DATA
))
13513 FETCH_DATA (info
, codep
+ 1);
13514 modrm
.mod
= (*codep
>> 6) & 3;
13515 modrm
.reg
= (*codep
>> 3) & 7;
13516 modrm
.rm
= *codep
& 7;
13524 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
13526 get_sib (info
, sizeflag
);
13527 dofloat (sizeflag
);
13531 dp
= get_valid_dis386 (dp
, info
);
13532 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
13534 get_sib (info
, sizeflag
);
13535 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13538 op_ad
= MAX_OPERANDS
- 1 - i
;
13540 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
13541 /* For EVEX instruction after the last operand masking
13542 should be printed. */
13543 if (i
== 0 && vex
.evex
)
13545 /* Don't print {%k0}. */
13546 if (vex
.mask_register_specifier
)
13549 oappend (names_mask
[vex
.mask_register_specifier
]);
13559 /* Check if the REX prefix is used. */
13560 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
13561 all_prefixes
[last_rex_prefix
] = 0;
13563 /* Check if the SEG prefix is used. */
13564 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
13565 | PREFIX_FS
| PREFIX_GS
)) != 0
13566 && (used_prefixes
& active_seg_prefix
) != 0)
13567 all_prefixes
[last_seg_prefix
] = 0;
13569 /* Check if the ADDR prefix is used. */
13570 if ((prefixes
& PREFIX_ADDR
) != 0
13571 && (used_prefixes
& PREFIX_ADDR
) != 0)
13572 all_prefixes
[last_addr_prefix
] = 0;
13574 /* Check if the DATA prefix is used. */
13575 if ((prefixes
& PREFIX_DATA
) != 0
13576 && (used_prefixes
& PREFIX_DATA
) != 0)
13577 all_prefixes
[last_data_prefix
] = 0;
13579 /* Print the extra prefixes. */
13581 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
13582 if (all_prefixes
[i
])
13585 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
13588 prefix_length
+= strlen (name
) + 1;
13589 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
13592 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13593 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13594 used by putop and MMX/SSE operand and may be overriden by the
13595 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13597 if (dp
->prefix_requirement
== PREFIX_OPCODE
13598 && dp
!= &bad_opcode
13600 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
13602 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
13604 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
13606 && (used_prefixes
& PREFIX_DATA
) == 0))))
13608 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13609 return end_codep
- priv
.the_buffer
;
13612 /* Check maximum code length. */
13613 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
13615 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13616 return MAX_CODE_LENGTH
;
13619 obufp
= mnemonicendp
;
13620 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
13623 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
13625 /* The enter and bound instructions are printed with operands in the same
13626 order as the intel book; everything else is printed in reverse order. */
13627 if (intel_syntax
|| two_source_ops
)
13631 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13632 op_txt
[i
] = op_out
[i
];
13634 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
13635 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
13637 op_txt
[2] = op_out
[3];
13638 op_txt
[3] = op_out
[2];
13641 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
13643 op_ad
= op_index
[i
];
13644 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
13645 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
13646 riprel
= op_riprel
[i
];
13647 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
13648 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
13653 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13654 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
13658 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13662 (*info
->fprintf_func
) (info
->stream
, ",");
13663 if (op_index
[i
] != -1 && !op_riprel
[i
])
13664 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
13666 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
13670 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13671 if (op_index
[i
] != -1 && op_riprel
[i
])
13673 (*info
->fprintf_func
) (info
->stream
, " # ");
13674 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
13675 + op_address
[op_index
[i
]]), info
);
13678 return codep
- priv
.the_buffer
;
13681 static const char *float_mem
[] = {
13756 static const unsigned char float_mem_mode
[] = {
13831 #define ST { OP_ST, 0 }
13832 #define STi { OP_STi, 0 }
13834 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13835 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13836 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13837 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13838 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13839 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13840 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13841 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13842 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13844 static const struct dis386 float_reg
[][8] = {
13847 { "fadd", { ST
, STi
}, 0 },
13848 { "fmul", { ST
, STi
}, 0 },
13849 { "fcom", { STi
}, 0 },
13850 { "fcomp", { STi
}, 0 },
13851 { "fsub", { ST
, STi
}, 0 },
13852 { "fsubr", { ST
, STi
}, 0 },
13853 { "fdiv", { ST
, STi
}, 0 },
13854 { "fdivr", { ST
, STi
}, 0 },
13858 { "fld", { STi
}, 0 },
13859 { "fxch", { STi
}, 0 },
13869 { "fcmovb", { ST
, STi
}, 0 },
13870 { "fcmove", { ST
, STi
}, 0 },
13871 { "fcmovbe",{ ST
, STi
}, 0 },
13872 { "fcmovu", { ST
, STi
}, 0 },
13880 { "fcmovnb",{ ST
, STi
}, 0 },
13881 { "fcmovne",{ ST
, STi
}, 0 },
13882 { "fcmovnbe",{ ST
, STi
}, 0 },
13883 { "fcmovnu",{ ST
, STi
}, 0 },
13885 { "fucomi", { ST
, STi
}, 0 },
13886 { "fcomi", { ST
, STi
}, 0 },
13891 { "fadd", { STi
, ST
}, 0 },
13892 { "fmul", { STi
, ST
}, 0 },
13895 { "fsub!M", { STi
, ST
}, 0 },
13896 { "fsubM", { STi
, ST
}, 0 },
13897 { "fdiv!M", { STi
, ST
}, 0 },
13898 { "fdivM", { STi
, ST
}, 0 },
13902 { "ffree", { STi
}, 0 },
13904 { "fst", { STi
}, 0 },
13905 { "fstp", { STi
}, 0 },
13906 { "fucom", { STi
}, 0 },
13907 { "fucomp", { STi
}, 0 },
13913 { "faddp", { STi
, ST
}, 0 },
13914 { "fmulp", { STi
, ST
}, 0 },
13917 { "fsub!Mp", { STi
, ST
}, 0 },
13918 { "fsubMp", { STi
, ST
}, 0 },
13919 { "fdiv!Mp", { STi
, ST
}, 0 },
13920 { "fdivMp", { STi
, ST
}, 0 },
13924 { "ffreep", { STi
}, 0 },
13929 { "fucomip", { ST
, STi
}, 0 },
13930 { "fcomip", { ST
, STi
}, 0 },
13935 static char *fgrps
[][8] = {
13938 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13943 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13948 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13953 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13958 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13963 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13968 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13969 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13974 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13979 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13984 swap_operand (void)
13986 mnemonicendp
[0] = '.';
13987 mnemonicendp
[1] = 's';
13992 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13993 int sizeflag ATTRIBUTE_UNUSED
)
13995 /* Skip mod/rm byte. */
14001 dofloat (int sizeflag
)
14003 const struct dis386
*dp
;
14004 unsigned char floatop
;
14006 floatop
= codep
[-1];
14008 if (modrm
.mod
!= 3)
14010 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
14012 putop (float_mem
[fp_indx
], sizeflag
);
14015 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
14018 /* Skip mod/rm byte. */
14022 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
14023 if (dp
->name
== NULL
)
14025 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
14027 /* Instruction fnstsw is only one with strange arg. */
14028 if (floatop
== 0xdf && codep
[-1] == 0xe0)
14029 strcpy (op_out
[0], names16
[0]);
14033 putop (dp
->name
, sizeflag
);
14038 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
14043 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
14047 /* Like oappend (below), but S is a string starting with '%'.
14048 In Intel syntax, the '%' is elided. */
14050 oappend_maybe_intel (const char *s
)
14052 oappend (s
+ intel_syntax
);
14056 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14058 oappend_maybe_intel ("%st");
14062 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14064 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
14065 oappend_maybe_intel (scratchbuf
);
14068 /* Capital letters in template are macros. */
14070 putop (const char *in_template
, int sizeflag
)
14075 unsigned int l
= 0, len
= 1;
14078 #define SAVE_LAST(c) \
14079 if (l < len && l < sizeof (last)) \
14084 for (p
= in_template
; *p
; p
++)
14101 while (*++p
!= '|')
14102 if (*p
== '}' || *p
== '\0')
14105 /* Fall through. */
14110 while (*++p
!= '}')
14121 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14125 if (l
== 0 && len
== 1)
14130 if (sizeflag
& SUFFIX_ALWAYS
)
14143 if (address_mode
== mode_64bit
14144 && !(prefixes
& PREFIX_ADDR
))
14155 if (intel_syntax
&& !alt
)
14157 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14159 if (sizeflag
& DFLAG
)
14160 *obufp
++ = intel_syntax
? 'd' : 'l';
14162 *obufp
++ = intel_syntax
? 'w' : 's';
14163 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14167 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14170 if (modrm
.mod
== 3)
14176 if (sizeflag
& DFLAG
)
14177 *obufp
++ = intel_syntax
? 'd' : 'l';
14180 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14186 case 'E': /* For jcxz/jecxz */
14187 if (address_mode
== mode_64bit
)
14189 if (sizeflag
& AFLAG
)
14195 if (sizeflag
& AFLAG
)
14197 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14202 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
14204 if (sizeflag
& AFLAG
)
14205 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
14207 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
14208 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14212 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
14214 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14218 if (!(rex
& REX_W
))
14219 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14224 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
14225 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
14227 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
14230 if (prefixes
& PREFIX_DS
)
14249 if (l
!= 0 || len
!= 1)
14251 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14256 if (!need_vex
|| !vex
.evex
)
14259 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14261 switch (vex
.length
)
14279 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
14284 /* Fall through. */
14287 if (l
!= 0 || len
!= 1)
14295 if (sizeflag
& SUFFIX_ALWAYS
)
14299 if (intel_mnemonic
!= cond
)
14303 if ((prefixes
& PREFIX_FWAIT
) == 0)
14306 used_prefixes
|= PREFIX_FWAIT
;
14312 else if (intel_syntax
&& (sizeflag
& DFLAG
))
14316 if (!(rex
& REX_W
))
14317 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14321 && address_mode
== mode_64bit
14322 && isa64
== intel64
)
14327 /* Fall through. */
14330 && address_mode
== mode_64bit
14331 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14336 /* Fall through. */
14339 if (l
== 0 && len
== 1)
14344 if ((rex
& REX_W
) == 0
14345 && (prefixes
& PREFIX_DATA
))
14347 if ((sizeflag
& DFLAG
) == 0)
14349 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14353 if ((prefixes
& PREFIX_DATA
)
14355 || (sizeflag
& SUFFIX_ALWAYS
))
14362 if (sizeflag
& DFLAG
)
14366 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14372 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14378 if ((prefixes
& PREFIX_DATA
)
14380 || (sizeflag
& SUFFIX_ALWAYS
))
14387 if (sizeflag
& DFLAG
)
14388 *obufp
++ = intel_syntax
? 'd' : 'l';
14391 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14399 if (address_mode
== mode_64bit
14400 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14402 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14406 /* Fall through. */
14409 if (l
== 0 && len
== 1)
14412 if (intel_syntax
&& !alt
)
14415 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14421 if (sizeflag
& DFLAG
)
14422 *obufp
++ = intel_syntax
? 'd' : 'l';
14425 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14431 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14437 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
14452 else if (sizeflag
& DFLAG
)
14461 if (intel_syntax
&& !p
[1]
14462 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
14464 if (!(rex
& REX_W
))
14465 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14468 if (l
== 0 && len
== 1)
14472 if (address_mode
== mode_64bit
14473 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14475 if (sizeflag
& SUFFIX_ALWAYS
)
14497 /* Fall through. */
14500 if (l
== 0 && len
== 1)
14505 if (sizeflag
& SUFFIX_ALWAYS
)
14511 if (sizeflag
& DFLAG
)
14515 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14529 if (address_mode
== mode_64bit
14530 && !(prefixes
& PREFIX_ADDR
))
14541 if (l
!= 0 || len
!= 1)
14546 if (need_vex
&& vex
.prefix
)
14548 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
14555 if (prefixes
& PREFIX_DATA
)
14559 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14563 if (l
== 0 && len
== 1)
14565 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14576 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14584 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14586 switch (vex
.length
)
14602 if (l
== 0 && len
== 1)
14604 /* operand size flag for cwtl, cbtw */
14613 else if (sizeflag
& DFLAG
)
14617 if (!(rex
& REX_W
))
14618 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14625 && last
[0] != 'L'))
14632 if (last
[0] == 'X')
14633 *obufp
++ = vex
.w
? 'd': 's';
14635 *obufp
++ = vex
.w
? 'q': 'd';
14641 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14643 if (sizeflag
& DFLAG
)
14647 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14653 if (address_mode
== mode_64bit
14654 && (isa64
== intel64
14655 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
14657 else if ((prefixes
& PREFIX_DATA
))
14659 if (!(sizeflag
& DFLAG
))
14661 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14668 mnemonicendp
= obufp
;
14673 oappend (const char *s
)
14675 obufp
= stpcpy (obufp
, s
);
14681 /* Only print the active segment register. */
14682 if (!active_seg_prefix
)
14685 used_prefixes
|= active_seg_prefix
;
14686 switch (active_seg_prefix
)
14689 oappend_maybe_intel ("%cs:");
14692 oappend_maybe_intel ("%ds:");
14695 oappend_maybe_intel ("%ss:");
14698 oappend_maybe_intel ("%es:");
14701 oappend_maybe_intel ("%fs:");
14704 oappend_maybe_intel ("%gs:");
14712 OP_indirE (int bytemode
, int sizeflag
)
14716 OP_E (bytemode
, sizeflag
);
14720 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
14722 if (address_mode
== mode_64bit
)
14730 sprintf_vma (tmp
, disp
);
14731 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
14732 strcpy (buf
+ 2, tmp
+ i
);
14736 bfd_signed_vma v
= disp
;
14743 /* Check for possible overflow on 0x8000000000000000. */
14746 strcpy (buf
, "9223372036854775808");
14760 tmp
[28 - i
] = (v
% 10) + '0';
14764 strcpy (buf
, tmp
+ 29 - i
);
14770 sprintf (buf
, "0x%x", (unsigned int) disp
);
14772 sprintf (buf
, "%d", (int) disp
);
14776 /* Put DISP in BUF as signed hex number. */
14779 print_displacement (char *buf
, bfd_vma disp
)
14781 bfd_signed_vma val
= disp
;
14790 /* Check for possible overflow. */
14793 switch (address_mode
)
14796 strcpy (buf
+ j
, "0x8000000000000000");
14799 strcpy (buf
+ j
, "0x80000000");
14802 strcpy (buf
+ j
, "0x8000");
14812 sprintf_vma (tmp
, (bfd_vma
) val
);
14813 for (i
= 0; tmp
[i
] == '0'; i
++)
14815 if (tmp
[i
] == '\0')
14817 strcpy (buf
+ j
, tmp
+ i
);
14821 intel_operand_size (int bytemode
, int sizeflag
)
14825 && (bytemode
== x_mode
14826 || bytemode
== evex_half_bcst_xmmq_mode
))
14829 oappend ("QWORD PTR ");
14831 oappend ("DWORD PTR ");
14840 oappend ("BYTE PTR ");
14845 case dqw_swap_mode
:
14846 oappend ("WORD PTR ");
14849 if (address_mode
== mode_64bit
&& isa64
== intel64
)
14851 oappend ("QWORD PTR ");
14855 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14857 oappend ("QWORD PTR ");
14866 oappend ("QWORD PTR ");
14869 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14870 oappend ("DWORD PTR ");
14872 oappend ("WORD PTR ");
14873 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14877 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14879 oappend ("WORD PTR ");
14880 if (!(rex
& REX_W
))
14881 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14884 if (sizeflag
& DFLAG
)
14885 oappend ("QWORD PTR ");
14887 oappend ("DWORD PTR ");
14888 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14891 case d_scalar_mode
:
14892 case d_scalar_swap_mode
:
14895 oappend ("DWORD PTR ");
14898 case q_scalar_mode
:
14899 case q_scalar_swap_mode
:
14901 oappend ("QWORD PTR ");
14904 if (address_mode
== mode_64bit
)
14905 oappend ("QWORD PTR ");
14907 oappend ("DWORD PTR ");
14910 if (sizeflag
& DFLAG
)
14911 oappend ("FWORD PTR ");
14913 oappend ("DWORD PTR ");
14914 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14917 oappend ("TBYTE PTR ");
14921 case evex_x_gscat_mode
:
14922 case evex_x_nobcst_mode
:
14925 switch (vex
.length
)
14928 oappend ("XMMWORD PTR ");
14931 oappend ("YMMWORD PTR ");
14934 oappend ("ZMMWORD PTR ");
14941 oappend ("XMMWORD PTR ");
14944 oappend ("XMMWORD PTR ");
14947 oappend ("YMMWORD PTR ");
14950 case evex_half_bcst_xmmq_mode
:
14954 switch (vex
.length
)
14957 oappend ("QWORD PTR ");
14960 oappend ("XMMWORD PTR ");
14963 oappend ("YMMWORD PTR ");
14973 switch (vex
.length
)
14978 oappend ("BYTE PTR ");
14988 switch (vex
.length
)
14993 oappend ("WORD PTR ");
15003 switch (vex
.length
)
15008 oappend ("DWORD PTR ");
15018 switch (vex
.length
)
15023 oappend ("QWORD PTR ");
15033 switch (vex
.length
)
15036 oappend ("WORD PTR ");
15039 oappend ("DWORD PTR ");
15042 oappend ("QWORD PTR ");
15052 switch (vex
.length
)
15055 oappend ("DWORD PTR ");
15058 oappend ("QWORD PTR ");
15061 oappend ("XMMWORD PTR ");
15071 switch (vex
.length
)
15074 oappend ("QWORD PTR ");
15077 oappend ("YMMWORD PTR ");
15080 oappend ("ZMMWORD PTR ");
15090 switch (vex
.length
)
15094 oappend ("XMMWORD PTR ");
15101 oappend ("OWORD PTR ");
15104 case vex_w_dq_mode
:
15105 case vex_scalar_w_dq_mode
:
15110 oappend ("QWORD PTR ");
15112 oappend ("DWORD PTR ");
15114 case vex_vsib_d_w_dq_mode
:
15115 case vex_vsib_q_w_dq_mode
:
15122 oappend ("QWORD PTR ");
15124 oappend ("DWORD PTR ");
15128 switch (vex
.length
)
15131 oappend ("XMMWORD PTR ");
15134 oappend ("YMMWORD PTR ");
15137 oappend ("ZMMWORD PTR ");
15144 case vex_vsib_q_w_d_mode
:
15145 case vex_vsib_d_w_d_mode
:
15146 if (!need_vex
|| !vex
.evex
)
15149 switch (vex
.length
)
15152 oappend ("QWORD PTR ");
15155 oappend ("XMMWORD PTR ");
15158 oappend ("YMMWORD PTR ");
15166 if (!need_vex
|| vex
.length
!= 128)
15169 oappend ("DWORD PTR ");
15171 oappend ("BYTE PTR ");
15177 oappend ("QWORD PTR ");
15179 oappend ("WORD PTR ");
15188 OP_E_register (int bytemode
, int sizeflag
)
15190 int reg
= modrm
.rm
;
15191 const char **names
;
15197 if ((sizeflag
& SUFFIX_ALWAYS
)
15198 && (bytemode
== b_swap_mode
15199 || bytemode
== v_swap_mode
15200 || bytemode
== dqw_swap_mode
))
15226 names
= address_mode
== mode_64bit
? names64
: names32
;
15232 if (address_mode
== mode_64bit
&& isa64
== intel64
)
15238 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15251 case dqw_swap_mode
:
15257 if ((sizeflag
& DFLAG
)
15258 || (bytemode
!= v_mode
15259 && bytemode
!= v_swap_mode
))
15263 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15268 names
= names_mask
;
15273 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15276 oappend (names
[reg
]);
15280 OP_E_memory (int bytemode
, int sizeflag
)
15283 int add
= (rex
& REX_B
) ? 8 : 0;
15289 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15291 && bytemode
!= x_mode
15292 && bytemode
!= xmmq_mode
15293 && bytemode
!= evex_half_bcst_xmmq_mode
)
15302 case dqw_swap_mode
:
15309 case vex_vsib_d_w_dq_mode
:
15310 case vex_vsib_d_w_d_mode
:
15311 case vex_vsib_q_w_dq_mode
:
15312 case vex_vsib_q_w_d_mode
:
15313 case evex_x_gscat_mode
:
15315 shift
= vex
.w
? 3 : 2;
15318 case evex_half_bcst_xmmq_mode
:
15322 shift
= vex
.w
? 3 : 2;
15325 /* Fall through if vex.b == 0. */
15329 case evex_x_nobcst_mode
:
15331 switch (vex
.length
)
15354 case q_scalar_mode
:
15356 case q_scalar_swap_mode
:
15362 case d_scalar_mode
:
15364 case d_scalar_swap_mode
:
15376 /* Make necessary corrections to shift for modes that need it.
15377 For these modes we currently have shift 4, 5 or 6 depending on
15378 vex.length (it corresponds to xmmword, ymmword or zmmword
15379 operand). We might want to make it 3, 4 or 5 (e.g. for
15380 xmmq_mode). In case of broadcast enabled the corrections
15381 aren't needed, as element size is always 32 or 64 bits. */
15383 && (bytemode
== xmmq_mode
15384 || bytemode
== evex_half_bcst_xmmq_mode
))
15386 else if (bytemode
== xmmqd_mode
)
15388 else if (bytemode
== xmmdw_mode
)
15390 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
15398 intel_operand_size (bytemode
, sizeflag
);
15401 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15403 /* 32/64 bit address mode */
15412 int addr32flag
= !((sizeflag
& AFLAG
)
15413 || bytemode
== v_bnd_mode
15414 || bytemode
== bnd_mode
);
15415 const char **indexes64
= names64
;
15416 const char **indexes32
= names32
;
15426 vindex
= sib
.index
;
15432 case vex_vsib_d_w_dq_mode
:
15433 case vex_vsib_d_w_d_mode
:
15434 case vex_vsib_q_w_dq_mode
:
15435 case vex_vsib_q_w_d_mode
:
15445 switch (vex
.length
)
15448 indexes64
= indexes32
= names_xmm
;
15452 || bytemode
== vex_vsib_q_w_dq_mode
15453 || bytemode
== vex_vsib_q_w_d_mode
)
15454 indexes64
= indexes32
= names_ymm
;
15456 indexes64
= indexes32
= names_xmm
;
15460 || bytemode
== vex_vsib_q_w_dq_mode
15461 || bytemode
== vex_vsib_q_w_d_mode
)
15462 indexes64
= indexes32
= names_zmm
;
15464 indexes64
= indexes32
= names_ymm
;
15471 haveindex
= vindex
!= 4;
15478 rbase
= base
+ add
;
15486 if (address_mode
== mode_64bit
&& !havesib
)
15492 FETCH_DATA (the_info
, codep
+ 1);
15494 if ((disp
& 0x80) != 0)
15496 if (vex
.evex
&& shift
> 0)
15504 /* In 32bit mode, we need index register to tell [offset] from
15505 [eiz*1 + offset]. */
15506 needindex
= (havesib
15509 && address_mode
== mode_32bit
);
15510 havedisp
= (havebase
15512 || (havesib
&& (haveindex
|| scale
!= 0)));
15515 if (modrm
.mod
!= 0 || base
== 5)
15517 if (havedisp
|| riprel
)
15518 print_displacement (scratchbuf
, disp
);
15520 print_operand_value (scratchbuf
, 1, disp
);
15521 oappend (scratchbuf
);
15525 oappend (sizeflag
& AFLAG
? "(%rip)" : "(%eip)");
15529 if ((havebase
|| haveindex
|| riprel
)
15530 && (bytemode
!= v_bnd_mode
)
15531 && (bytemode
!= bnd_mode
))
15532 used_prefixes
|= PREFIX_ADDR
;
15534 if (havedisp
|| (intel_syntax
&& riprel
))
15536 *obufp
++ = open_char
;
15537 if (intel_syntax
&& riprel
)
15540 oappend (sizeflag
& AFLAG
? "rip" : "eip");
15544 oappend (address_mode
== mode_64bit
&& !addr32flag
15545 ? names64
[rbase
] : names32
[rbase
]);
15548 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15549 print index to tell base + index from base. */
15553 || (havebase
&& base
!= ESP_REG_NUM
))
15555 if (!intel_syntax
|| havebase
)
15557 *obufp
++ = separator_char
;
15561 oappend (address_mode
== mode_64bit
&& !addr32flag
15562 ? indexes64
[vindex
] : indexes32
[vindex
]);
15564 oappend (address_mode
== mode_64bit
&& !addr32flag
15565 ? index64
: index32
);
15567 *obufp
++ = scale_char
;
15569 sprintf (scratchbuf
, "%d", 1 << scale
);
15570 oappend (scratchbuf
);
15574 && (disp
|| modrm
.mod
!= 0 || base
== 5))
15576 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
15581 else if (modrm
.mod
!= 1 && disp
!= -disp
)
15585 disp
= - (bfd_signed_vma
) disp
;
15589 print_displacement (scratchbuf
, disp
);
15591 print_operand_value (scratchbuf
, 1, disp
);
15592 oappend (scratchbuf
);
15595 *obufp
++ = close_char
;
15598 else if (intel_syntax
)
15600 if (modrm
.mod
!= 0 || base
== 5)
15602 if (!active_seg_prefix
)
15604 oappend (names_seg
[ds_reg
- es_reg
]);
15607 print_operand_value (scratchbuf
, 1, disp
);
15608 oappend (scratchbuf
);
15614 /* 16 bit address mode */
15615 used_prefixes
|= prefixes
& PREFIX_ADDR
;
15622 if ((disp
& 0x8000) != 0)
15627 FETCH_DATA (the_info
, codep
+ 1);
15629 if ((disp
& 0x80) != 0)
15634 if ((disp
& 0x8000) != 0)
15640 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
15642 print_displacement (scratchbuf
, disp
);
15643 oappend (scratchbuf
);
15646 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
15648 *obufp
++ = open_char
;
15650 oappend (index16
[modrm
.rm
]);
15652 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
15654 if ((bfd_signed_vma
) disp
>= 0)
15659 else if (modrm
.mod
!= 1)
15663 disp
= - (bfd_signed_vma
) disp
;
15666 print_displacement (scratchbuf
, disp
);
15667 oappend (scratchbuf
);
15670 *obufp
++ = close_char
;
15673 else if (intel_syntax
)
15675 if (!active_seg_prefix
)
15677 oappend (names_seg
[ds_reg
- es_reg
]);
15680 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
15681 oappend (scratchbuf
);
15684 if (vex
.evex
&& vex
.b
15685 && (bytemode
== x_mode
15686 || bytemode
== xmmq_mode
15687 || bytemode
== evex_half_bcst_xmmq_mode
))
15690 || bytemode
== xmmq_mode
15691 || bytemode
== evex_half_bcst_xmmq_mode
)
15693 switch (vex
.length
)
15696 oappend ("{1to2}");
15699 oappend ("{1to4}");
15702 oappend ("{1to8}");
15710 switch (vex
.length
)
15713 oappend ("{1to4}");
15716 oappend ("{1to8}");
15719 oappend ("{1to16}");
15729 OP_E (int bytemode
, int sizeflag
)
15731 /* Skip mod/rm byte. */
15735 if (modrm
.mod
== 3)
15736 OP_E_register (bytemode
, sizeflag
);
15738 OP_E_memory (bytemode
, sizeflag
);
15742 OP_G (int bytemode
, int sizeflag
)
15753 oappend (names8rex
[modrm
.reg
+ add
]);
15755 oappend (names8
[modrm
.reg
+ add
]);
15758 oappend (names16
[modrm
.reg
+ add
]);
15763 oappend (names32
[modrm
.reg
+ add
]);
15766 oappend (names64
[modrm
.reg
+ add
]);
15769 oappend (names_bnd
[modrm
.reg
]);
15776 case dqw_swap_mode
:
15779 oappend (names64
[modrm
.reg
+ add
]);
15782 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
15783 oappend (names32
[modrm
.reg
+ add
]);
15785 oappend (names16
[modrm
.reg
+ add
]);
15786 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15790 if (address_mode
== mode_64bit
)
15791 oappend (names64
[modrm
.reg
+ add
]);
15793 oappend (names32
[modrm
.reg
+ add
]);
15797 oappend (names_mask
[modrm
.reg
+ add
]);
15800 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15813 FETCH_DATA (the_info
, codep
+ 8);
15814 a
= *codep
++ & 0xff;
15815 a
|= (*codep
++ & 0xff) << 8;
15816 a
|= (*codep
++ & 0xff) << 16;
15817 a
|= (*codep
++ & 0xffu
) << 24;
15818 b
= *codep
++ & 0xff;
15819 b
|= (*codep
++ & 0xff) << 8;
15820 b
|= (*codep
++ & 0xff) << 16;
15821 b
|= (*codep
++ & 0xffu
) << 24;
15822 x
= a
+ ((bfd_vma
) b
<< 32);
15830 static bfd_signed_vma
15833 bfd_signed_vma x
= 0;
15835 FETCH_DATA (the_info
, codep
+ 4);
15836 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15837 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15838 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15839 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15843 static bfd_signed_vma
15846 bfd_signed_vma x
= 0;
15848 FETCH_DATA (the_info
, codep
+ 4);
15849 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15850 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15851 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15852 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15854 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15864 FETCH_DATA (the_info
, codep
+ 2);
15865 x
= *codep
++ & 0xff;
15866 x
|= (*codep
++ & 0xff) << 8;
15871 set_op (bfd_vma op
, int riprel
)
15873 op_index
[op_ad
] = op_ad
;
15874 if (address_mode
== mode_64bit
)
15876 op_address
[op_ad
] = op
;
15877 op_riprel
[op_ad
] = riprel
;
15881 /* Mask to get a 32-bit address. */
15882 op_address
[op_ad
] = op
& 0xffffffff;
15883 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15888 OP_REG (int code
, int sizeflag
)
15895 case es_reg
: case ss_reg
: case cs_reg
:
15896 case ds_reg
: case fs_reg
: case gs_reg
:
15897 oappend (names_seg
[code
- es_reg
]);
15909 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15910 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15911 s
= names16
[code
- ax_reg
+ add
];
15913 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15914 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15917 s
= names8rex
[code
- al_reg
+ add
];
15919 s
= names8
[code
- al_reg
];
15921 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15922 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15923 if (address_mode
== mode_64bit
15924 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15926 s
= names64
[code
- rAX_reg
+ add
];
15929 code
+= eAX_reg
- rAX_reg
;
15930 /* Fall through. */
15931 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15932 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15935 s
= names64
[code
- eAX_reg
+ add
];
15938 if (sizeflag
& DFLAG
)
15939 s
= names32
[code
- eAX_reg
+ add
];
15941 s
= names16
[code
- eAX_reg
+ add
];
15942 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15946 s
= INTERNAL_DISASSEMBLER_ERROR
;
15953 OP_IMREG (int code
, int sizeflag
)
15965 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15966 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15967 s
= names16
[code
- ax_reg
];
15969 case es_reg
: case ss_reg
: case cs_reg
:
15970 case ds_reg
: case fs_reg
: case gs_reg
:
15971 s
= names_seg
[code
- es_reg
];
15973 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15974 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15977 s
= names8rex
[code
- al_reg
];
15979 s
= names8
[code
- al_reg
];
15981 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15982 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15985 s
= names64
[code
- eAX_reg
];
15988 if (sizeflag
& DFLAG
)
15989 s
= names32
[code
- eAX_reg
];
15991 s
= names16
[code
- eAX_reg
];
15992 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15995 case z_mode_ax_reg
:
15996 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
16000 if (!(rex
& REX_W
))
16001 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16004 s
= INTERNAL_DISASSEMBLER_ERROR
;
16011 OP_I (int bytemode
, int sizeflag
)
16014 bfd_signed_vma mask
= -1;
16019 FETCH_DATA (the_info
, codep
+ 1);
16024 if (address_mode
== mode_64bit
)
16029 /* Fall through. */
16036 if (sizeflag
& DFLAG
)
16046 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16058 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16063 scratchbuf
[0] = '$';
16064 print_operand_value (scratchbuf
+ 1, 1, op
);
16065 oappend_maybe_intel (scratchbuf
);
16066 scratchbuf
[0] = '\0';
16070 OP_I64 (int bytemode
, int sizeflag
)
16073 bfd_signed_vma mask
= -1;
16075 if (address_mode
!= mode_64bit
)
16077 OP_I (bytemode
, sizeflag
);
16084 FETCH_DATA (the_info
, codep
+ 1);
16094 if (sizeflag
& DFLAG
)
16104 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16112 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16117 scratchbuf
[0] = '$';
16118 print_operand_value (scratchbuf
+ 1, 1, op
);
16119 oappend_maybe_intel (scratchbuf
);
16120 scratchbuf
[0] = '\0';
16124 OP_sI (int bytemode
, int sizeflag
)
16132 FETCH_DATA (the_info
, codep
+ 1);
16134 if ((op
& 0x80) != 0)
16136 if (bytemode
== b_T_mode
)
16138 if (address_mode
!= mode_64bit
16139 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
16141 /* The operand-size prefix is overridden by a REX prefix. */
16142 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16150 if (!(rex
& REX_W
))
16152 if (sizeflag
& DFLAG
)
16160 /* The operand-size prefix is overridden by a REX prefix. */
16161 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16167 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16171 scratchbuf
[0] = '$';
16172 print_operand_value (scratchbuf
+ 1, 1, op
);
16173 oappend_maybe_intel (scratchbuf
);
16177 OP_J (int bytemode
, int sizeflag
)
16181 bfd_vma segment
= 0;
16186 FETCH_DATA (the_info
, codep
+ 1);
16188 if ((disp
& 0x80) != 0)
16192 if (isa64
== amd64
)
16194 if ((sizeflag
& DFLAG
)
16195 || (address_mode
== mode_64bit
16196 && (isa64
!= amd64
|| (rex
& REX_W
))))
16201 if ((disp
& 0x8000) != 0)
16203 /* In 16bit mode, address is wrapped around at 64k within
16204 the same segment. Otherwise, a data16 prefix on a jump
16205 instruction means that the pc is masked to 16 bits after
16206 the displacement is added! */
16208 if ((prefixes
& PREFIX_DATA
) == 0)
16209 segment
= ((start_pc
+ (codep
- start_codep
))
16210 & ~((bfd_vma
) 0xffff));
16212 if (address_mode
!= mode_64bit
16213 || (isa64
== amd64
&& !(rex
& REX_W
)))
16214 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16217 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16220 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
16222 print_operand_value (scratchbuf
, 1, disp
);
16223 oappend (scratchbuf
);
16227 OP_SEG (int bytemode
, int sizeflag
)
16229 if (bytemode
== w_mode
)
16230 oappend (names_seg
[modrm
.reg
]);
16232 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
16236 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
16240 if (sizeflag
& DFLAG
)
16250 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16252 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
16254 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
16255 oappend (scratchbuf
);
16259 OP_OFF (int bytemode
, int sizeflag
)
16263 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16264 intel_operand_size (bytemode
, sizeflag
);
16267 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16274 if (!active_seg_prefix
)
16276 oappend (names_seg
[ds_reg
- es_reg
]);
16280 print_operand_value (scratchbuf
, 1, off
);
16281 oappend (scratchbuf
);
16285 OP_OFF64 (int bytemode
, int sizeflag
)
16289 if (address_mode
!= mode_64bit
16290 || (prefixes
& PREFIX_ADDR
))
16292 OP_OFF (bytemode
, sizeflag
);
16296 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16297 intel_operand_size (bytemode
, sizeflag
);
16304 if (!active_seg_prefix
)
16306 oappend (names_seg
[ds_reg
- es_reg
]);
16310 print_operand_value (scratchbuf
, 1, off
);
16311 oappend (scratchbuf
);
16315 ptr_reg (int code
, int sizeflag
)
16319 *obufp
++ = open_char
;
16320 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
16321 if (address_mode
== mode_64bit
)
16323 if (!(sizeflag
& AFLAG
))
16324 s
= names32
[code
- eAX_reg
];
16326 s
= names64
[code
- eAX_reg
];
16328 else if (sizeflag
& AFLAG
)
16329 s
= names32
[code
- eAX_reg
];
16331 s
= names16
[code
- eAX_reg
];
16333 *obufp
++ = close_char
;
16338 OP_ESreg (int code
, int sizeflag
)
16344 case 0x6d: /* insw/insl */
16345 intel_operand_size (z_mode
, sizeflag
);
16347 case 0xa5: /* movsw/movsl/movsq */
16348 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16349 case 0xab: /* stosw/stosl */
16350 case 0xaf: /* scasw/scasl */
16351 intel_operand_size (v_mode
, sizeflag
);
16354 intel_operand_size (b_mode
, sizeflag
);
16357 oappend_maybe_intel ("%es:");
16358 ptr_reg (code
, sizeflag
);
16362 OP_DSreg (int code
, int sizeflag
)
16368 case 0x6f: /* outsw/outsl */
16369 intel_operand_size (z_mode
, sizeflag
);
16371 case 0xa5: /* movsw/movsl/movsq */
16372 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16373 case 0xad: /* lodsw/lodsl/lodsq */
16374 intel_operand_size (v_mode
, sizeflag
);
16377 intel_operand_size (b_mode
, sizeflag
);
16380 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16381 default segment register DS is printed. */
16382 if (!active_seg_prefix
)
16383 active_seg_prefix
= PREFIX_DS
;
16385 ptr_reg (code
, sizeflag
);
16389 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16397 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
16399 all_prefixes
[last_lock_prefix
] = 0;
16400 used_prefixes
|= PREFIX_LOCK
;
16405 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
16406 oappend_maybe_intel (scratchbuf
);
16410 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16419 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
16421 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
16422 oappend (scratchbuf
);
16426 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16428 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
16429 oappend_maybe_intel (scratchbuf
);
16433 OP_R (int bytemode
, int sizeflag
)
16435 /* Skip mod/rm byte. */
16438 OP_E_register (bytemode
, sizeflag
);
16442 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16444 int reg
= modrm
.reg
;
16445 const char **names
;
16447 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16448 if (prefixes
& PREFIX_DATA
)
16457 oappend (names
[reg
]);
16461 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16463 int reg
= modrm
.reg
;
16464 const char **names
;
16476 && bytemode
!= xmm_mode
16477 && bytemode
!= xmmq_mode
16478 && bytemode
!= evex_half_bcst_xmmq_mode
16479 && bytemode
!= ymm_mode
16480 && bytemode
!= scalar_mode
)
16482 switch (vex
.length
)
16489 || (bytemode
!= vex_vsib_q_w_dq_mode
16490 && bytemode
!= vex_vsib_q_w_d_mode
))
16502 else if (bytemode
== xmmq_mode
16503 || bytemode
== evex_half_bcst_xmmq_mode
)
16505 switch (vex
.length
)
16518 else if (bytemode
== ymm_mode
)
16522 oappend (names
[reg
]);
16526 OP_EM (int bytemode
, int sizeflag
)
16529 const char **names
;
16531 if (modrm
.mod
!= 3)
16534 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16536 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16537 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16539 OP_E (bytemode
, sizeflag
);
16543 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
16546 /* Skip mod/rm byte. */
16549 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16551 if (prefixes
& PREFIX_DATA
)
16560 oappend (names
[reg
]);
16563 /* cvt* are the only instructions in sse2 which have
16564 both SSE and MMX operands and also have 0x66 prefix
16565 in their opcode. 0x66 was originally used to differentiate
16566 between SSE and MMX instruction(operands). So we have to handle the
16567 cvt* separately using OP_EMC and OP_MXC */
16569 OP_EMC (int bytemode
, int sizeflag
)
16571 if (modrm
.mod
!= 3)
16573 if (intel_syntax
&& bytemode
== v_mode
)
16575 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16576 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16578 OP_E (bytemode
, sizeflag
);
16582 /* Skip mod/rm byte. */
16585 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16586 oappend (names_mm
[modrm
.rm
]);
16590 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16592 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16593 oappend (names_mm
[modrm
.reg
]);
16597 OP_EX (int bytemode
, int sizeflag
)
16600 const char **names
;
16602 /* Skip mod/rm byte. */
16606 if (modrm
.mod
!= 3)
16608 OP_E_memory (bytemode
, sizeflag
);
16623 if ((sizeflag
& SUFFIX_ALWAYS
)
16624 && (bytemode
== x_swap_mode
16625 || bytemode
== d_swap_mode
16626 || bytemode
== dqw_swap_mode
16627 || bytemode
== d_scalar_swap_mode
16628 || bytemode
== q_swap_mode
16629 || bytemode
== q_scalar_swap_mode
))
16633 && bytemode
!= xmm_mode
16634 && bytemode
!= xmmdw_mode
16635 && bytemode
!= xmmqd_mode
16636 && bytemode
!= xmm_mb_mode
16637 && bytemode
!= xmm_mw_mode
16638 && bytemode
!= xmm_md_mode
16639 && bytemode
!= xmm_mq_mode
16640 && bytemode
!= xmm_mdq_mode
16641 && bytemode
!= xmmq_mode
16642 && bytemode
!= evex_half_bcst_xmmq_mode
16643 && bytemode
!= ymm_mode
16644 && bytemode
!= d_scalar_mode
16645 && bytemode
!= d_scalar_swap_mode
16646 && bytemode
!= q_scalar_mode
16647 && bytemode
!= q_scalar_swap_mode
16648 && bytemode
!= vex_scalar_w_dq_mode
)
16650 switch (vex
.length
)
16665 else if (bytemode
== xmmq_mode
16666 || bytemode
== evex_half_bcst_xmmq_mode
)
16668 switch (vex
.length
)
16681 else if (bytemode
== ymm_mode
)
16685 oappend (names
[reg
]);
16689 OP_MS (int bytemode
, int sizeflag
)
16691 if (modrm
.mod
== 3)
16692 OP_EM (bytemode
, sizeflag
);
16698 OP_XS (int bytemode
, int sizeflag
)
16700 if (modrm
.mod
== 3)
16701 OP_EX (bytemode
, sizeflag
);
16707 OP_M (int bytemode
, int sizeflag
)
16709 if (modrm
.mod
== 3)
16710 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16713 OP_E (bytemode
, sizeflag
);
16717 OP_0f07 (int bytemode
, int sizeflag
)
16719 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
16722 OP_E (bytemode
, sizeflag
);
16725 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16726 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16729 NOP_Fixup1 (int bytemode
, int sizeflag
)
16731 if ((prefixes
& PREFIX_DATA
) != 0
16734 && address_mode
== mode_64bit
))
16735 OP_REG (bytemode
, sizeflag
);
16737 strcpy (obuf
, "nop");
16741 NOP_Fixup2 (int bytemode
, int sizeflag
)
16743 if ((prefixes
& PREFIX_DATA
) != 0
16746 && address_mode
== mode_64bit
))
16747 OP_IMREG (bytemode
, sizeflag
);
16750 static const char *const Suffix3DNow
[] = {
16751 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16752 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16753 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16754 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16755 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16756 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16757 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16758 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16759 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16760 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16761 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16762 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16763 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16764 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16765 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16766 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16767 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16768 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16769 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16770 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16771 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16772 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16773 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16774 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16775 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16776 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16777 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16778 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16779 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16780 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16781 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16782 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16783 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16784 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16785 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16786 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16787 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16788 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16789 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16790 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16791 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16792 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16793 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16794 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16795 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16796 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16797 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16798 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16799 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16800 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16801 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16802 /* CC */ NULL
, NULL
, NULL
, NULL
,
16803 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16804 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16805 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16806 /* DC */ NULL
, NULL
, NULL
, NULL
,
16807 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16808 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16809 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16810 /* EC */ NULL
, NULL
, NULL
, NULL
,
16811 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16812 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16813 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16814 /* FC */ NULL
, NULL
, NULL
, NULL
,
16818 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16820 const char *mnemonic
;
16822 FETCH_DATA (the_info
, codep
+ 1);
16823 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16824 place where an 8-bit immediate would normally go. ie. the last
16825 byte of the instruction. */
16826 obufp
= mnemonicendp
;
16827 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16829 oappend (mnemonic
);
16832 /* Since a variable sized modrm/sib chunk is between the start
16833 of the opcode (0x0f0f) and the opcode suffix, we need to do
16834 all the modrm processing first, and don't know until now that
16835 we have a bad opcode. This necessitates some cleaning up. */
16836 op_out
[0][0] = '\0';
16837 op_out
[1][0] = '\0';
16840 mnemonicendp
= obufp
;
16843 static struct op simd_cmp_op
[] =
16845 { STRING_COMMA_LEN ("eq") },
16846 { STRING_COMMA_LEN ("lt") },
16847 { STRING_COMMA_LEN ("le") },
16848 { STRING_COMMA_LEN ("unord") },
16849 { STRING_COMMA_LEN ("neq") },
16850 { STRING_COMMA_LEN ("nlt") },
16851 { STRING_COMMA_LEN ("nle") },
16852 { STRING_COMMA_LEN ("ord") }
16856 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16858 unsigned int cmp_type
;
16860 FETCH_DATA (the_info
, codep
+ 1);
16861 cmp_type
= *codep
++ & 0xff;
16862 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16865 char *p
= mnemonicendp
- 2;
16869 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16870 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16874 /* We have a reserved extension byte. Output it directly. */
16875 scratchbuf
[0] = '$';
16876 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16877 oappend_maybe_intel (scratchbuf
);
16878 scratchbuf
[0] = '\0';
16883 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
16884 int sizeflag ATTRIBUTE_UNUSED
)
16886 /* mwaitx %eax,%ecx,%ebx */
16889 const char **names
= (address_mode
== mode_64bit
16890 ? names64
: names32
);
16891 strcpy (op_out
[0], names
[0]);
16892 strcpy (op_out
[1], names
[1]);
16893 strcpy (op_out
[2], names
[3]);
16894 two_source_ops
= 1;
16896 /* Skip mod/rm byte. */
16902 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
16903 int sizeflag ATTRIBUTE_UNUSED
)
16905 /* mwait %eax,%ecx */
16908 const char **names
= (address_mode
== mode_64bit
16909 ? names64
: names32
);
16910 strcpy (op_out
[0], names
[0]);
16911 strcpy (op_out
[1], names
[1]);
16912 two_source_ops
= 1;
16914 /* Skip mod/rm byte. */
16920 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16921 int sizeflag ATTRIBUTE_UNUSED
)
16923 /* monitor %eax,%ecx,%edx" */
16926 const char **op1_names
;
16927 const char **names
= (address_mode
== mode_64bit
16928 ? names64
: names32
);
16930 if (!(prefixes
& PREFIX_ADDR
))
16931 op1_names
= (address_mode
== mode_16bit
16932 ? names16
: names
);
16935 /* Remove "addr16/addr32". */
16936 all_prefixes
[last_addr_prefix
] = 0;
16937 op1_names
= (address_mode
!= mode_32bit
16938 ? names32
: names16
);
16939 used_prefixes
|= PREFIX_ADDR
;
16941 strcpy (op_out
[0], op1_names
[0]);
16942 strcpy (op_out
[1], names
[1]);
16943 strcpy (op_out
[2], names
[2]);
16944 two_source_ops
= 1;
16946 /* Skip mod/rm byte. */
16954 /* Throw away prefixes and 1st. opcode byte. */
16955 codep
= insn_codep
+ 1;
16960 REP_Fixup (int bytemode
, int sizeflag
)
16962 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16964 if (prefixes
& PREFIX_REPZ
)
16965 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16972 OP_IMREG (bytemode
, sizeflag
);
16975 OP_ESreg (bytemode
, sizeflag
);
16978 OP_DSreg (bytemode
, sizeflag
);
16986 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16990 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16992 if (prefixes
& PREFIX_REPNZ
)
16993 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16996 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16997 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
17001 HLE_Fixup1 (int bytemode
, int sizeflag
)
17004 && (prefixes
& PREFIX_LOCK
) != 0)
17006 if (prefixes
& PREFIX_REPZ
)
17007 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
17008 if (prefixes
& PREFIX_REPNZ
)
17009 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
17012 OP_E (bytemode
, sizeflag
);
17015 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
17016 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
17020 HLE_Fixup2 (int bytemode
, int sizeflag
)
17022 if (modrm
.mod
!= 3)
17024 if (prefixes
& PREFIX_REPZ
)
17025 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
17026 if (prefixes
& PREFIX_REPNZ
)
17027 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
17030 OP_E (bytemode
, sizeflag
);
17033 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
17034 "xrelease" for memory operand. No check for LOCK prefix. */
17037 HLE_Fixup3 (int bytemode
, int sizeflag
)
17040 && last_repz_prefix
> last_repnz_prefix
17041 && (prefixes
& PREFIX_REPZ
) != 0)
17042 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
17044 OP_E (bytemode
, sizeflag
);
17048 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
17053 /* Change cmpxchg8b to cmpxchg16b. */
17054 char *p
= mnemonicendp
- 2;
17055 mnemonicendp
= stpcpy (p
, "16b");
17058 else if ((prefixes
& PREFIX_LOCK
) != 0)
17060 if (prefixes
& PREFIX_REPZ
)
17061 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
17062 if (prefixes
& PREFIX_REPNZ
)
17063 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
17066 OP_M (bytemode
, sizeflag
);
17070 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
17072 const char **names
;
17076 switch (vex
.length
)
17090 oappend (names
[reg
]);
17094 CRC32_Fixup (int bytemode
, int sizeflag
)
17096 /* Add proper suffix to "crc32". */
17097 char *p
= mnemonicendp
;
17116 if (sizeflag
& DFLAG
)
17120 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17124 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17131 if (modrm
.mod
== 3)
17135 /* Skip mod/rm byte. */
17140 add
= (rex
& REX_B
) ? 8 : 0;
17141 if (bytemode
== b_mode
)
17145 oappend (names8rex
[modrm
.rm
+ add
]);
17147 oappend (names8
[modrm
.rm
+ add
]);
17153 oappend (names64
[modrm
.rm
+ add
]);
17154 else if ((prefixes
& PREFIX_DATA
))
17155 oappend (names16
[modrm
.rm
+ add
]);
17157 oappend (names32
[modrm
.rm
+ add
]);
17161 OP_E (bytemode
, sizeflag
);
17165 FXSAVE_Fixup (int bytemode
, int sizeflag
)
17167 /* Add proper suffix to "fxsave" and "fxrstor". */
17171 char *p
= mnemonicendp
;
17177 OP_M (bytemode
, sizeflag
);
17180 /* Display the destination register operand for instructions with
17184 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17187 const char **names
;
17195 reg
= vex
.register_specifier
;
17202 if (bytemode
== vex_scalar_mode
)
17204 oappend (names_xmm
[reg
]);
17208 switch (vex
.length
)
17215 case vex_vsib_q_w_dq_mode
:
17216 case vex_vsib_q_w_d_mode
:
17227 names
= names_mask
;
17241 case vex_vsib_q_w_dq_mode
:
17242 case vex_vsib_q_w_d_mode
:
17243 names
= vex
.w
? names_ymm
: names_xmm
;
17247 names
= names_mask
;
17261 oappend (names
[reg
]);
17264 /* Get the VEX immediate byte without moving codep. */
17266 static unsigned char
17267 get_vex_imm8 (int sizeflag
, int opnum
)
17269 int bytes_before_imm
= 0;
17271 if (modrm
.mod
!= 3)
17273 /* There are SIB/displacement bytes. */
17274 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
17276 /* 32/64 bit address mode */
17277 int base
= modrm
.rm
;
17279 /* Check SIB byte. */
17282 FETCH_DATA (the_info
, codep
+ 1);
17284 /* When decoding the third source, don't increase
17285 bytes_before_imm as this has already been incremented
17286 by one in OP_E_memory while decoding the second
17289 bytes_before_imm
++;
17292 /* Don't increase bytes_before_imm when decoding the third source,
17293 it has already been incremented by OP_E_memory while decoding
17294 the second source operand. */
17300 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17301 SIB == 5, there is a 4 byte displacement. */
17303 /* No displacement. */
17306 /* 4 byte displacement. */
17307 bytes_before_imm
+= 4;
17310 /* 1 byte displacement. */
17311 bytes_before_imm
++;
17318 /* 16 bit address mode */
17319 /* Don't increase bytes_before_imm when decoding the third source,
17320 it has already been incremented by OP_E_memory while decoding
17321 the second source operand. */
17327 /* When modrm.rm == 6, there is a 2 byte displacement. */
17329 /* No displacement. */
17332 /* 2 byte displacement. */
17333 bytes_before_imm
+= 2;
17336 /* 1 byte displacement: when decoding the third source,
17337 don't increase bytes_before_imm as this has already
17338 been incremented by one in OP_E_memory while decoding
17339 the second source operand. */
17341 bytes_before_imm
++;
17349 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
17350 return codep
[bytes_before_imm
];
17354 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
17356 const char **names
;
17358 if (reg
== -1 && modrm
.mod
!= 3)
17360 OP_E_memory (bytemode
, sizeflag
);
17372 else if (reg
> 7 && address_mode
!= mode_64bit
)
17376 switch (vex
.length
)
17387 oappend (names
[reg
]);
17391 OP_EX_VexImmW (int bytemode
, int sizeflag
)
17394 static unsigned char vex_imm8
;
17396 if (vex_w_done
== 0)
17400 /* Skip mod/rm byte. */
17404 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
17407 reg
= vex_imm8
>> 4;
17409 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17411 else if (vex_w_done
== 1)
17416 reg
= vex_imm8
>> 4;
17418 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17422 /* Output the imm8 directly. */
17423 scratchbuf
[0] = '$';
17424 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
17425 oappend_maybe_intel (scratchbuf
);
17426 scratchbuf
[0] = '\0';
17432 OP_Vex_2src (int bytemode
, int sizeflag
)
17434 if (modrm
.mod
== 3)
17436 int reg
= modrm
.rm
;
17440 oappend (names_xmm
[reg
]);
17445 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
17447 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
17448 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17450 OP_E (bytemode
, sizeflag
);
17455 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
17457 if (modrm
.mod
== 3)
17459 /* Skip mod/rm byte. */
17465 oappend (names_xmm
[vex
.register_specifier
]);
17467 OP_Vex_2src (bytemode
, sizeflag
);
17471 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
17474 OP_Vex_2src (bytemode
, sizeflag
);
17476 oappend (names_xmm
[vex
.register_specifier
]);
17480 OP_EX_VexW (int bytemode
, int sizeflag
)
17488 /* Skip mod/rm byte. */
17493 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
17498 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
17501 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17505 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17506 int sizeflag ATTRIBUTE_UNUSED
)
17508 /* Skip the immediate byte and check for invalid bits. */
17509 FETCH_DATA (the_info
, codep
+ 1);
17510 if (*codep
++ & 0xf)
17515 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17518 const char **names
;
17520 FETCH_DATA (the_info
, codep
+ 1);
17523 if (bytemode
!= x_mode
)
17530 if (reg
> 7 && address_mode
!= mode_64bit
)
17533 switch (vex
.length
)
17544 oappend (names
[reg
]);
17548 OP_XMM_VexW (int bytemode
, int sizeflag
)
17550 /* Turn off the REX.W bit since it is used for swapping operands
17553 OP_XMM (bytemode
, sizeflag
);
17557 OP_EX_Vex (int bytemode
, int sizeflag
)
17559 if (modrm
.mod
!= 3)
17561 if (vex
.register_specifier
!= 0)
17565 OP_EX (bytemode
, sizeflag
);
17569 OP_XMM_Vex (int bytemode
, int sizeflag
)
17571 if (modrm
.mod
!= 3)
17573 if (vex
.register_specifier
!= 0)
17577 OP_XMM (bytemode
, sizeflag
);
17581 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17583 switch (vex
.length
)
17586 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
17589 mnemonicendp
= stpcpy (obuf
, "vzeroall");
17596 static struct op vex_cmp_op
[] =
17598 { STRING_COMMA_LEN ("eq") },
17599 { STRING_COMMA_LEN ("lt") },
17600 { STRING_COMMA_LEN ("le") },
17601 { STRING_COMMA_LEN ("unord") },
17602 { STRING_COMMA_LEN ("neq") },
17603 { STRING_COMMA_LEN ("nlt") },
17604 { STRING_COMMA_LEN ("nle") },
17605 { STRING_COMMA_LEN ("ord") },
17606 { STRING_COMMA_LEN ("eq_uq") },
17607 { STRING_COMMA_LEN ("nge") },
17608 { STRING_COMMA_LEN ("ngt") },
17609 { STRING_COMMA_LEN ("false") },
17610 { STRING_COMMA_LEN ("neq_oq") },
17611 { STRING_COMMA_LEN ("ge") },
17612 { STRING_COMMA_LEN ("gt") },
17613 { STRING_COMMA_LEN ("true") },
17614 { STRING_COMMA_LEN ("eq_os") },
17615 { STRING_COMMA_LEN ("lt_oq") },
17616 { STRING_COMMA_LEN ("le_oq") },
17617 { STRING_COMMA_LEN ("unord_s") },
17618 { STRING_COMMA_LEN ("neq_us") },
17619 { STRING_COMMA_LEN ("nlt_uq") },
17620 { STRING_COMMA_LEN ("nle_uq") },
17621 { STRING_COMMA_LEN ("ord_s") },
17622 { STRING_COMMA_LEN ("eq_us") },
17623 { STRING_COMMA_LEN ("nge_uq") },
17624 { STRING_COMMA_LEN ("ngt_uq") },
17625 { STRING_COMMA_LEN ("false_os") },
17626 { STRING_COMMA_LEN ("neq_os") },
17627 { STRING_COMMA_LEN ("ge_oq") },
17628 { STRING_COMMA_LEN ("gt_oq") },
17629 { STRING_COMMA_LEN ("true_us") },
17633 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17635 unsigned int cmp_type
;
17637 FETCH_DATA (the_info
, codep
+ 1);
17638 cmp_type
= *codep
++ & 0xff;
17639 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
17642 char *p
= mnemonicendp
- 2;
17646 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
17647 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
17651 /* We have a reserved extension byte. Output it directly. */
17652 scratchbuf
[0] = '$';
17653 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17654 oappend_maybe_intel (scratchbuf
);
17655 scratchbuf
[0] = '\0';
17660 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17661 int sizeflag ATTRIBUTE_UNUSED
)
17663 unsigned int cmp_type
;
17668 FETCH_DATA (the_info
, codep
+ 1);
17669 cmp_type
= *codep
++ & 0xff;
17670 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17671 If it's the case, print suffix, otherwise - print the immediate. */
17672 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
17677 char *p
= mnemonicendp
- 2;
17679 /* vpcmp* can have both one- and two-lettered suffix. */
17693 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
17694 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
17698 /* We have a reserved extension byte. Output it directly. */
17699 scratchbuf
[0] = '$';
17700 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17701 oappend_maybe_intel (scratchbuf
);
17702 scratchbuf
[0] = '\0';
17706 static const struct op pclmul_op
[] =
17708 { STRING_COMMA_LEN ("lql") },
17709 { STRING_COMMA_LEN ("hql") },
17710 { STRING_COMMA_LEN ("lqh") },
17711 { STRING_COMMA_LEN ("hqh") }
17715 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17716 int sizeflag ATTRIBUTE_UNUSED
)
17718 unsigned int pclmul_type
;
17720 FETCH_DATA (the_info
, codep
+ 1);
17721 pclmul_type
= *codep
++ & 0xff;
17722 switch (pclmul_type
)
17733 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
17736 char *p
= mnemonicendp
- 3;
17741 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
17742 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
17746 /* We have a reserved extension byte. Output it directly. */
17747 scratchbuf
[0] = '$';
17748 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
17749 oappend_maybe_intel (scratchbuf
);
17750 scratchbuf
[0] = '\0';
17755 MOVBE_Fixup (int bytemode
, int sizeflag
)
17757 /* Add proper suffix to "movbe". */
17758 char *p
= mnemonicendp
;
17767 if (sizeflag
& SUFFIX_ALWAYS
)
17773 if (sizeflag
& DFLAG
)
17777 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17782 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17789 OP_M (bytemode
, sizeflag
);
17793 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17796 const char **names
;
17798 /* Skip mod/rm byte. */
17812 oappend (names
[reg
]);
17816 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17818 const char **names
;
17825 oappend (names
[vex
.register_specifier
]);
17829 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17832 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
17836 if ((rex
& REX_R
) != 0 || !vex
.r
)
17842 oappend (names_mask
[modrm
.reg
]);
17846 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17849 || (bytemode
!= evex_rounding_mode
17850 && bytemode
!= evex_sae_mode
))
17852 if (modrm
.mod
== 3 && vex
.b
)
17855 case evex_rounding_mode
:
17856 oappend (names_rounding
[vex
.ll
]);
17858 case evex_sae_mode
: