1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2019 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void OP_Mwaitx (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
128 static void OP_Mask (int, int);
131 /* Points to first byte not fetched. */
132 bfd_byte
*max_fetched
;
133 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
136 OPCODES_SIGJMP_BUF bailout
;
146 enum address_mode address_mode
;
148 /* Flags for the prefixes for the current instruction. See below. */
151 /* REX prefix the current instruction. See below. */
153 /* Bits of REX we've already used. */
155 /* REX bits in original REX prefix ignored. */
156 static int rex_ignored
;
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes
;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
201 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
202 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
204 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
205 status
= (*info
->read_memory_func
) (start
,
207 addr
- priv
->max_fetched
,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv
->max_fetched
== priv
->the_buffer
)
218 (*info
->memory_error_func
) (status
, start
, info
);
219 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
222 priv
->max_fetched
= addr
;
226 /* Possible values for prefix requirement. */
227 #define PREFIX_IGNORED_SHIFT 16
228 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234 /* Opcode prefixes. */
235 #define PREFIX_OPCODE (PREFIX_REPZ \
239 /* Prefixes ignored. */
240 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
241 | PREFIX_IGNORED_REPNZ \
242 | PREFIX_IGNORED_DATA)
244 #define XX { NULL, 0 }
245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
247 #define Eb { OP_E, b_mode }
248 #define Ebnd { OP_E, bnd_mode }
249 #define EbS { OP_E, b_swap_mode }
250 #define EbndS { OP_E, bnd_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Eva { OP_E, va_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Eq { OP_E, q_mode }
263 #define indirEv { OP_indirE, indir_v_mode }
264 #define indirEp { OP_indirE, f_mode }
265 #define stackEv { OP_E, stack_v_mode }
266 #define Em { OP_E, m_mode }
267 #define Ew { OP_E, w_mode }
268 #define M { OP_M, 0 } /* lea, lgdt, etc. */
269 #define Ma { OP_M, a_mode }
270 #define Mb { OP_M, b_mode }
271 #define Md { OP_M, d_mode }
272 #define Mo { OP_M, o_mode }
273 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
274 #define Mq { OP_M, q_mode }
275 #define Mv_bnd { OP_M, v_bndmk_mode }
276 #define Mx { OP_M, x_mode }
277 #define Mxmm { OP_M, xmm_mode }
278 #define Gb { OP_G, b_mode }
279 #define Gbnd { OP_G, bnd_mode }
280 #define Gv { OP_G, v_mode }
281 #define Gd { OP_G, d_mode }
282 #define Gdq { OP_G, dq_mode }
283 #define Gm { OP_G, m_mode }
284 #define Gva { OP_G, va_mode }
285 #define Gw { OP_G, w_mode }
286 #define Rd { OP_R, d_mode }
287 #define Rdq { OP_R, dq_mode }
288 #define Rm { OP_R, m_mode }
289 #define Ib { OP_I, b_mode }
290 #define sIb { OP_sI, b_mode } /* sign extened byte */
291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
292 #define Iv { OP_I, v_mode }
293 #define sIv { OP_sI, v_mode }
294 #define Iv64 { OP_I64, v_mode }
295 #define Id { OP_I, d_mode }
296 #define Iw { OP_I, w_mode }
297 #define I1 { OP_I, const_1_mode }
298 #define Jb { OP_J, b_mode }
299 #define Jv { OP_J, v_mode }
300 #define Cm { OP_C, m_mode }
301 #define Dm { OP_D, m_mode }
302 #define Td { OP_T, d_mode }
303 #define Skip_MODRM { OP_Skip_MODRM, 0 }
305 #define RMeAX { OP_REG, eAX_reg }
306 #define RMeBX { OP_REG, eBX_reg }
307 #define RMeCX { OP_REG, eCX_reg }
308 #define RMeDX { OP_REG, eDX_reg }
309 #define RMeSP { OP_REG, eSP_reg }
310 #define RMeBP { OP_REG, eBP_reg }
311 #define RMeSI { OP_REG, eSI_reg }
312 #define RMeDI { OP_REG, eDI_reg }
313 #define RMrAX { OP_REG, rAX_reg }
314 #define RMrBX { OP_REG, rBX_reg }
315 #define RMrCX { OP_REG, rCX_reg }
316 #define RMrDX { OP_REG, rDX_reg }
317 #define RMrSP { OP_REG, rSP_reg }
318 #define RMrBP { OP_REG, rBP_reg }
319 #define RMrSI { OP_REG, rSI_reg }
320 #define RMrDI { OP_REG, rDI_reg }
321 #define RMAL { OP_REG, al_reg }
322 #define RMCL { OP_REG, cl_reg }
323 #define RMDL { OP_REG, dl_reg }
324 #define RMBL { OP_REG, bl_reg }
325 #define RMAH { OP_REG, ah_reg }
326 #define RMCH { OP_REG, ch_reg }
327 #define RMDH { OP_REG, dh_reg }
328 #define RMBH { OP_REG, bh_reg }
329 #define RMAX { OP_REG, ax_reg }
330 #define RMDX { OP_REG, dx_reg }
332 #define eAX { OP_IMREG, eAX_reg }
333 #define eBX { OP_IMREG, eBX_reg }
334 #define eCX { OP_IMREG, eCX_reg }
335 #define eDX { OP_IMREG, eDX_reg }
336 #define eSP { OP_IMREG, eSP_reg }
337 #define eBP { OP_IMREG, eBP_reg }
338 #define eSI { OP_IMREG, eSI_reg }
339 #define eDI { OP_IMREG, eDI_reg }
340 #define AL { OP_IMREG, al_reg }
341 #define CL { OP_IMREG, cl_reg }
342 #define DL { OP_IMREG, dl_reg }
343 #define BL { OP_IMREG, bl_reg }
344 #define AH { OP_IMREG, ah_reg }
345 #define CH { OP_IMREG, ch_reg }
346 #define DH { OP_IMREG, dh_reg }
347 #define BH { OP_IMREG, bh_reg }
348 #define AX { OP_IMREG, ax_reg }
349 #define DX { OP_IMREG, dx_reg }
350 #define zAX { OP_IMREG, z_mode_ax_reg }
351 #define indirDX { OP_IMREG, indir_dx_reg }
353 #define Sw { OP_SEG, w_mode }
354 #define Sv { OP_SEG, v_mode }
355 #define Ap { OP_DIR, 0 }
356 #define Ob { OP_OFF64, b_mode }
357 #define Ov { OP_OFF64, v_mode }
358 #define Xb { OP_DSreg, eSI_reg }
359 #define Xv { OP_DSreg, eSI_reg }
360 #define Xz { OP_DSreg, eSI_reg }
361 #define Yb { OP_ESreg, eDI_reg }
362 #define Yv { OP_ESreg, eDI_reg }
363 #define DSBX { OP_DSreg, eBX_reg }
365 #define es { OP_REG, es_reg }
366 #define ss { OP_REG, ss_reg }
367 #define cs { OP_REG, cs_reg }
368 #define ds { OP_REG, ds_reg }
369 #define fs { OP_REG, fs_reg }
370 #define gs { OP_REG, gs_reg }
372 #define MX { OP_MMX, 0 }
373 #define XM { OP_XMM, 0 }
374 #define XMScalar { OP_XMM, scalar_mode }
375 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
376 #define XMM { OP_XMM, xmm_mode }
377 #define XMxmmq { OP_XMM, xmmq_mode }
378 #define EM { OP_EM, v_mode }
379 #define EMS { OP_EM, v_swap_mode }
380 #define EMd { OP_EM, d_mode }
381 #define EMx { OP_EM, x_mode }
382 #define EXbScalar { OP_EX, b_scalar_mode }
383 #define EXw { OP_EX, w_mode }
384 #define EXwScalar { OP_EX, w_scalar_mode }
385 #define EXd { OP_EX, d_mode }
386 #define EXdScalar { OP_EX, d_scalar_mode }
387 #define EXdS { OP_EX, d_swap_mode }
388 #define EXq { OP_EX, q_mode }
389 #define EXqScalar { OP_EX, q_scalar_mode }
390 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
391 #define EXqS { OP_EX, q_swap_mode }
392 #define EXx { OP_EX, x_mode }
393 #define EXxS { OP_EX, x_swap_mode }
394 #define EXxmm { OP_EX, xmm_mode }
395 #define EXymm { OP_EX, ymm_mode }
396 #define EXxmmq { OP_EX, xmmq_mode }
397 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
398 #define EXxmm_mb { OP_EX, xmm_mb_mode }
399 #define EXxmm_mw { OP_EX, xmm_mw_mode }
400 #define EXxmm_md { OP_EX, xmm_md_mode }
401 #define EXxmm_mq { OP_EX, xmm_mq_mode }
402 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
403 #define EXxmmdw { OP_EX, xmmdw_mode }
404 #define EXxmmqd { OP_EX, xmmqd_mode }
405 #define EXymmq { OP_EX, ymmq_mode }
406 #define EXVexWdq { OP_EX, vex_w_dq_mode }
407 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
408 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
409 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
410 #define MS { OP_MS, v_mode }
411 #define XS { OP_XS, v_mode }
412 #define EMCq { OP_EMC, q_mode }
413 #define MXC { OP_MXC, 0 }
414 #define OPSUF { OP_3DNowSuffix, 0 }
415 #define CMP { CMP_Fixup, 0 }
416 #define XMM0 { XMM_Fixup, 0 }
417 #define FXSAVE { FXSAVE_Fixup, 0 }
418 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
419 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
421 #define Vex { OP_VEX, vex_mode }
422 #define VexScalar { OP_VEX, vex_scalar_mode }
423 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
424 #define Vex128 { OP_VEX, vex128_mode }
425 #define Vex256 { OP_VEX, vex256_mode }
426 #define VexGdq { OP_VEX, dq_mode }
427 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
429 #define EXVexW { OP_EX_VexW, x_mode }
430 #define EXdVexW { OP_EX_VexW, d_mode }
431 #define EXqVexW { OP_EX_VexW, q_mode }
432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
433 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
434 #define XMVexW { OP_XMM_VexW, 0 }
435 #define XMVexI4 { OP_REG_VexI4, x_mode }
436 #define PCLMUL { PCLMUL_Fixup, 0 }
437 #define VCMP { VCMP_Fixup, 0 }
438 #define VPCMP { VPCMP_Fixup, 0 }
439 #define VPCOM { VPCOM_Fixup, 0 }
441 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
442 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
445 #define XMask { OP_Mask, mask_mode }
446 #define MaskG { OP_G, mask_mode }
447 #define MaskE { OP_E, mask_mode }
448 #define MaskBDE { OP_E, mask_bd_mode }
449 #define MaskR { OP_R, mask_mode }
450 #define MaskVex { OP_VEX, mask_mode }
452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
457 /* Used handle "rep" prefix for string instructions. */
458 #define Xbr { REP_Fixup, eSI_reg }
459 #define Xvr { REP_Fixup, eSI_reg }
460 #define Ybr { REP_Fixup, eDI_reg }
461 #define Yvr { REP_Fixup, eDI_reg }
462 #define Yzr { REP_Fixup, eDI_reg }
463 #define indirDXr { REP_Fixup, indir_dx_reg }
464 #define ALr { REP_Fixup, al_reg }
465 #define eAXr { REP_Fixup, eAX_reg }
467 /* Used handle HLE prefix for lockable instructions. */
468 #define Ebh1 { HLE_Fixup1, b_mode }
469 #define Evh1 { HLE_Fixup1, v_mode }
470 #define Ebh2 { HLE_Fixup2, b_mode }
471 #define Evh2 { HLE_Fixup2, v_mode }
472 #define Ebh3 { HLE_Fixup3, b_mode }
473 #define Evh3 { HLE_Fixup3, v_mode }
475 #define BND { BND_Fixup, 0 }
476 #define NOTRACK { NOTRACK_Fixup, 0 }
478 #define cond_jump_flag { NULL, cond_jump_mode }
479 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
481 /* bits in sizeflag */
482 #define SUFFIX_ALWAYS 4
490 /* byte operand with operand swapped */
492 /* byte operand, sign extend like 'T' suffix */
494 /* operand size depends on prefixes */
496 /* operand size depends on prefixes with operand swapped */
498 /* operand size depends on address prefix */
502 /* double word operand */
504 /* double word operand with operand swapped */
506 /* quad word operand */
508 /* quad word operand with operand swapped */
510 /* ten-byte operand */
512 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
513 broadcast enabled. */
515 /* Similar to x_mode, but with different EVEX mem shifts. */
517 /* Similar to x_mode, but with disabled broadcast. */
519 /* Similar to x_mode, but with operands swapped and disabled broadcast
522 /* 16-byte XMM operand */
524 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
525 memory operand (depending on vector length). Broadcast isn't
528 /* Same as xmmq_mode, but broadcast is allowed. */
529 evex_half_bcst_xmmq_mode
,
530 /* XMM register or byte memory operand */
532 /* XMM register or word memory operand */
534 /* XMM register or double word memory operand */
536 /* XMM register or quad word memory operand */
538 /* XMM register or double/quad word memory operand, depending on
541 /* 16-byte XMM, word, double word or quad word operand. */
543 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
545 /* 32-byte YMM operand */
547 /* quad word, ymmword or zmmword memory operand. */
549 /* 32-byte YMM or 16-byte word operand */
551 /* d_mode in 32bit, q_mode in 64bit mode. */
553 /* pair of v_mode operands */
558 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
560 /* operand size depends on REX prefixes. */
562 /* registers like dq_mode, memory like w_mode. */
566 /* bounds operand with operand swapped */
568 /* 4- or 6-byte pointer operand */
571 /* v_mode for indirect branch opcodes. */
573 /* v_mode for stack-related opcodes. */
575 /* non-quad operand size depends on prefixes */
577 /* 16-byte operand */
579 /* registers like dq_mode, memory like b_mode. */
581 /* registers like d_mode, memory like b_mode. */
583 /* registers like d_mode, memory like w_mode. */
585 /* registers like dq_mode, memory like d_mode. */
587 /* normal vex mode */
589 /* 128bit vex mode */
591 /* 256bit vex mode */
593 /* operand size depends on the VEX.W bit. */
596 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
597 vex_vsib_d_w_dq_mode
,
598 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
600 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
601 vex_vsib_q_w_dq_mode
,
602 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
605 /* scalar, ignore vector length. */
607 /* like b_mode, ignore vector length. */
609 /* like w_mode, ignore vector length. */
611 /* like d_mode, ignore vector length. */
613 /* like d_swap_mode, ignore vector length. */
615 /* like q_mode, ignore vector length. */
617 /* like q_swap_mode, ignore vector length. */
619 /* like vex_mode, ignore vector length. */
621 /* like vex_w_dq_mode, ignore vector length. */
622 vex_scalar_w_dq_mode
,
624 /* Static rounding. */
626 /* Static rounding, 64-bit mode only. */
627 evex_rounding_64_mode
,
628 /* Supress all exceptions. */
631 /* Mask register operand. */
633 /* Mask register operand. */
701 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
703 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
704 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
705 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
706 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
707 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
708 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
709 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
710 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
711 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
712 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
713 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
714 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
715 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
716 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
717 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
718 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
846 MOD_VEX_0F12_PREFIX_0
,
848 MOD_VEX_0F16_PREFIX_0
,
851 MOD_VEX_W_0_0F41_P_0_LEN_1
,
852 MOD_VEX_W_1_0F41_P_0_LEN_1
,
853 MOD_VEX_W_0_0F41_P_2_LEN_1
,
854 MOD_VEX_W_1_0F41_P_2_LEN_1
,
855 MOD_VEX_W_0_0F42_P_0_LEN_1
,
856 MOD_VEX_W_1_0F42_P_0_LEN_1
,
857 MOD_VEX_W_0_0F42_P_2_LEN_1
,
858 MOD_VEX_W_1_0F42_P_2_LEN_1
,
859 MOD_VEX_W_0_0F44_P_0_LEN_1
,
860 MOD_VEX_W_1_0F44_P_0_LEN_1
,
861 MOD_VEX_W_0_0F44_P_2_LEN_1
,
862 MOD_VEX_W_1_0F44_P_2_LEN_1
,
863 MOD_VEX_W_0_0F45_P_0_LEN_1
,
864 MOD_VEX_W_1_0F45_P_0_LEN_1
,
865 MOD_VEX_W_0_0F45_P_2_LEN_1
,
866 MOD_VEX_W_1_0F45_P_2_LEN_1
,
867 MOD_VEX_W_0_0F46_P_0_LEN_1
,
868 MOD_VEX_W_1_0F46_P_0_LEN_1
,
869 MOD_VEX_W_0_0F46_P_2_LEN_1
,
870 MOD_VEX_W_1_0F46_P_2_LEN_1
,
871 MOD_VEX_W_0_0F47_P_0_LEN_1
,
872 MOD_VEX_W_1_0F47_P_0_LEN_1
,
873 MOD_VEX_W_0_0F47_P_2_LEN_1
,
874 MOD_VEX_W_1_0F47_P_2_LEN_1
,
875 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
876 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
877 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
878 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
879 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
880 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
881 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
893 MOD_VEX_W_0_0F91_P_0_LEN_0
,
894 MOD_VEX_W_1_0F91_P_0_LEN_0
,
895 MOD_VEX_W_0_0F91_P_2_LEN_0
,
896 MOD_VEX_W_1_0F91_P_2_LEN_0
,
897 MOD_VEX_W_0_0F92_P_0_LEN_0
,
898 MOD_VEX_W_0_0F92_P_2_LEN_0
,
899 MOD_VEX_0F92_P_3_LEN_0
,
900 MOD_VEX_W_0_0F93_P_0_LEN_0
,
901 MOD_VEX_W_0_0F93_P_2_LEN_0
,
902 MOD_VEX_0F93_P_3_LEN_0
,
903 MOD_VEX_W_0_0F98_P_0_LEN_0
,
904 MOD_VEX_W_1_0F98_P_0_LEN_0
,
905 MOD_VEX_W_0_0F98_P_2_LEN_0
,
906 MOD_VEX_W_1_0F98_P_2_LEN_0
,
907 MOD_VEX_W_0_0F99_P_0_LEN_0
,
908 MOD_VEX_W_1_0F99_P_0_LEN_0
,
909 MOD_VEX_W_0_0F99_P_2_LEN_0
,
910 MOD_VEX_W_1_0F99_P_2_LEN_0
,
913 MOD_VEX_0FD7_PREFIX_2
,
914 MOD_VEX_0FE7_PREFIX_2
,
915 MOD_VEX_0FF0_PREFIX_3
,
916 MOD_VEX_0F381A_PREFIX_2
,
917 MOD_VEX_0F382A_PREFIX_2
,
918 MOD_VEX_0F382C_PREFIX_2
,
919 MOD_VEX_0F382D_PREFIX_2
,
920 MOD_VEX_0F382E_PREFIX_2
,
921 MOD_VEX_0F382F_PREFIX_2
,
922 MOD_VEX_0F385A_PREFIX_2
,
923 MOD_VEX_0F388C_PREFIX_2
,
924 MOD_VEX_0F388E_PREFIX_2
,
925 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
926 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
927 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
928 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
929 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
930 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
931 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
932 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
934 MOD_EVEX_0F12_PREFIX_0
,
935 MOD_EVEX_0F16_PREFIX_0
,
936 MOD_EVEX_0F38C6_REG_1
,
937 MOD_EVEX_0F38C6_REG_2
,
938 MOD_EVEX_0F38C6_REG_5
,
939 MOD_EVEX_0F38C6_REG_6
,
940 MOD_EVEX_0F38C7_REG_1
,
941 MOD_EVEX_0F38C7_REG_2
,
942 MOD_EVEX_0F38C7_REG_5
,
943 MOD_EVEX_0F38C7_REG_6
956 RM_0F1E_P_1_MOD_3_REG_7
,
957 RM_0FAE_REG_6_MOD_3_P_0
,
964 PREFIX_0F01_REG_5_MOD_0
,
965 PREFIX_0F01_REG_5_MOD_3_RM_0
,
966 PREFIX_0F01_REG_5_MOD_3_RM_2
,
967 PREFIX_0F01_REG_7_MOD_3_RM_2
,
968 PREFIX_0F01_REG_7_MOD_3_RM_3
,
1010 PREFIX_0FAE_REG_0_MOD_3
,
1011 PREFIX_0FAE_REG_1_MOD_3
,
1012 PREFIX_0FAE_REG_2_MOD_3
,
1013 PREFIX_0FAE_REG_3_MOD_3
,
1014 PREFIX_0FAE_REG_4_MOD_0
,
1015 PREFIX_0FAE_REG_4_MOD_3
,
1016 PREFIX_0FAE_REG_5_MOD_0
,
1017 PREFIX_0FAE_REG_5_MOD_3
,
1018 PREFIX_0FAE_REG_6_MOD_0
,
1019 PREFIX_0FAE_REG_6_MOD_3
,
1020 PREFIX_0FAE_REG_7_MOD_0
,
1026 PREFIX_0FC7_REG_6_MOD_0
,
1027 PREFIX_0FC7_REG_6_MOD_3
,
1028 PREFIX_0FC7_REG_7_MOD_3
,
1158 PREFIX_VEX_0F71_REG_2
,
1159 PREFIX_VEX_0F71_REG_4
,
1160 PREFIX_VEX_0F71_REG_6
,
1161 PREFIX_VEX_0F72_REG_2
,
1162 PREFIX_VEX_0F72_REG_4
,
1163 PREFIX_VEX_0F72_REG_6
,
1164 PREFIX_VEX_0F73_REG_2
,
1165 PREFIX_VEX_0F73_REG_3
,
1166 PREFIX_VEX_0F73_REG_6
,
1167 PREFIX_VEX_0F73_REG_7
,
1340 PREFIX_VEX_0F38F3_REG_1
,
1341 PREFIX_VEX_0F38F3_REG_2
,
1342 PREFIX_VEX_0F38F3_REG_3
,
1461 PREFIX_EVEX_0F71_REG_2
,
1462 PREFIX_EVEX_0F71_REG_4
,
1463 PREFIX_EVEX_0F71_REG_6
,
1464 PREFIX_EVEX_0F72_REG_0
,
1465 PREFIX_EVEX_0F72_REG_1
,
1466 PREFIX_EVEX_0F72_REG_2
,
1467 PREFIX_EVEX_0F72_REG_4
,
1468 PREFIX_EVEX_0F72_REG_6
,
1469 PREFIX_EVEX_0F73_REG_2
,
1470 PREFIX_EVEX_0F73_REG_3
,
1471 PREFIX_EVEX_0F73_REG_6
,
1472 PREFIX_EVEX_0F73_REG_7
,
1669 PREFIX_EVEX_0F38C6_REG_1
,
1670 PREFIX_EVEX_0F38C6_REG_2
,
1671 PREFIX_EVEX_0F38C6_REG_5
,
1672 PREFIX_EVEX_0F38C6_REG_6
,
1673 PREFIX_EVEX_0F38C7_REG_1
,
1674 PREFIX_EVEX_0F38C7_REG_2
,
1675 PREFIX_EVEX_0F38C7_REG_5
,
1676 PREFIX_EVEX_0F38C7_REG_6
,
1778 THREE_BYTE_0F38
= 0,
1805 VEX_LEN_0F12_P_0_M_0
= 0,
1806 VEX_LEN_0F12_P_0_M_1
,
1809 VEX_LEN_0F16_P_0_M_0
,
1810 VEX_LEN_0F16_P_0_M_1
,
1847 VEX_LEN_0FAE_R_2_M_0
,
1848 VEX_LEN_0FAE_R_3_M_0
,
1855 VEX_LEN_0F381A_P_2_M_0
,
1858 VEX_LEN_0F385A_P_2_M_0
,
1861 VEX_LEN_0F38F3_R_1_P_0
,
1862 VEX_LEN_0F38F3_R_2_P_0
,
1863 VEX_LEN_0F38F3_R_3_P_0
,
1906 VEX_LEN_0FXOP_08_CC
,
1907 VEX_LEN_0FXOP_08_CD
,
1908 VEX_LEN_0FXOP_08_CE
,
1909 VEX_LEN_0FXOP_08_CF
,
1910 VEX_LEN_0FXOP_08_EC
,
1911 VEX_LEN_0FXOP_08_ED
,
1912 VEX_LEN_0FXOP_08_EE
,
1913 VEX_LEN_0FXOP_08_EF
,
1914 VEX_LEN_0FXOP_09_80
,
1920 EVEX_LEN_0F6E_P_2
= 0,
1924 EVEX_LEN_0F3819_P_2_W_0
,
1925 EVEX_LEN_0F3819_P_2_W_1
,
1926 EVEX_LEN_0F381A_P_2_W_0
,
1927 EVEX_LEN_0F381A_P_2_W_1
,
1928 EVEX_LEN_0F381B_P_2_W_0
,
1929 EVEX_LEN_0F381B_P_2_W_1
,
1930 EVEX_LEN_0F385A_P_2_W_0
,
1931 EVEX_LEN_0F385A_P_2_W_1
,
1932 EVEX_LEN_0F385B_P_2_W_0
,
1933 EVEX_LEN_0F385B_P_2_W_1
,
1934 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1935 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1936 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1937 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1938 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1939 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1940 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1941 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1942 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1943 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1944 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1945 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1946 EVEX_LEN_0F3A18_P_2_W_0
,
1947 EVEX_LEN_0F3A18_P_2_W_1
,
1948 EVEX_LEN_0F3A19_P_2_W_0
,
1949 EVEX_LEN_0F3A19_P_2_W_1
,
1950 EVEX_LEN_0F3A1A_P_2_W_0
,
1951 EVEX_LEN_0F3A1A_P_2_W_1
,
1952 EVEX_LEN_0F3A1B_P_2_W_0
,
1953 EVEX_LEN_0F3A1B_P_2_W_1
,
1954 EVEX_LEN_0F3A23_P_2_W_0
,
1955 EVEX_LEN_0F3A23_P_2_W_1
,
1956 EVEX_LEN_0F3A38_P_2_W_0
,
1957 EVEX_LEN_0F3A38_P_2_W_1
,
1958 EVEX_LEN_0F3A39_P_2_W_0
,
1959 EVEX_LEN_0F3A39_P_2_W_1
,
1960 EVEX_LEN_0F3A3A_P_2_W_0
,
1961 EVEX_LEN_0F3A3A_P_2_W_1
,
1962 EVEX_LEN_0F3A3B_P_2_W_0
,
1963 EVEX_LEN_0F3A3B_P_2_W_1
,
1964 EVEX_LEN_0F3A43_P_2_W_0
,
1965 EVEX_LEN_0F3A43_P_2_W_1
1970 VEX_W_0F41_P_0_LEN_1
= 0,
1971 VEX_W_0F41_P_2_LEN_1
,
1972 VEX_W_0F42_P_0_LEN_1
,
1973 VEX_W_0F42_P_2_LEN_1
,
1974 VEX_W_0F44_P_0_LEN_0
,
1975 VEX_W_0F44_P_2_LEN_0
,
1976 VEX_W_0F45_P_0_LEN_1
,
1977 VEX_W_0F45_P_2_LEN_1
,
1978 VEX_W_0F46_P_0_LEN_1
,
1979 VEX_W_0F46_P_2_LEN_1
,
1980 VEX_W_0F47_P_0_LEN_1
,
1981 VEX_W_0F47_P_2_LEN_1
,
1982 VEX_W_0F4A_P_0_LEN_1
,
1983 VEX_W_0F4A_P_2_LEN_1
,
1984 VEX_W_0F4B_P_0_LEN_1
,
1985 VEX_W_0F4B_P_2_LEN_1
,
1986 VEX_W_0F90_P_0_LEN_0
,
1987 VEX_W_0F90_P_2_LEN_0
,
1988 VEX_W_0F91_P_0_LEN_0
,
1989 VEX_W_0F91_P_2_LEN_0
,
1990 VEX_W_0F92_P_0_LEN_0
,
1991 VEX_W_0F92_P_2_LEN_0
,
1992 VEX_W_0F93_P_0_LEN_0
,
1993 VEX_W_0F93_P_2_LEN_0
,
1994 VEX_W_0F98_P_0_LEN_0
,
1995 VEX_W_0F98_P_2_LEN_0
,
1996 VEX_W_0F99_P_0_LEN_0
,
1997 VEX_W_0F99_P_2_LEN_0
,
2005 VEX_W_0F381A_P_2_M_0
,
2006 VEX_W_0F382C_P_2_M_0
,
2007 VEX_W_0F382D_P_2_M_0
,
2008 VEX_W_0F382E_P_2_M_0
,
2009 VEX_W_0F382F_P_2_M_0
,
2014 VEX_W_0F385A_P_2_M_0
,
2026 VEX_W_0F3A30_P_2_LEN_0
,
2027 VEX_W_0F3A31_P_2_LEN_0
,
2028 VEX_W_0F3A32_P_2_LEN_0
,
2029 VEX_W_0F3A33_P_2_LEN_0
,
2049 EVEX_W_0F12_P_0_M_0
,
2050 EVEX_W_0F12_P_0_M_1
,
2060 EVEX_W_0F16_P_0_M_0
,
2061 EVEX_W_0F16_P_0_M_1
,
2130 EVEX_W_0F72_R_2_P_2
,
2131 EVEX_W_0F72_R_6_P_2
,
2132 EVEX_W_0F73_R_2_P_2
,
2133 EVEX_W_0F73_R_6_P_2
,
2243 EVEX_W_0F38C7_R_1_P_2
,
2244 EVEX_W_0F38C7_R_2_P_2
,
2245 EVEX_W_0F38C7_R_5_P_2
,
2246 EVEX_W_0F38C7_R_6_P_2
,
2285 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2294 unsigned int prefix_requirement
;
2297 /* Upper case letters in the instruction names here are macros.
2298 'A' => print 'b' if no register operands or suffix_always is true
2299 'B' => print 'b' if suffix_always is true
2300 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2302 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2303 suffix_always is true
2304 'E' => print 'e' if 32-bit form of jcxz
2305 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2306 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2307 'H' => print ",pt" or ",pn" branch hint
2308 'I' => honor following macro letter even in Intel mode (implemented only
2309 for some of the macro letters)
2311 'K' => print 'd' or 'q' if rex prefix is present.
2312 'L' => print 'l' if suffix_always is true
2313 'M' => print 'r' if intel_mnemonic is false.
2314 'N' => print 'n' if instruction has no wait "prefix"
2315 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2316 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2317 or suffix_always is true. print 'q' if rex prefix is present.
2318 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2320 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2321 'S' => print 'w', 'l' or 'q' if suffix_always is true
2322 'T' => print 'q' in 64bit mode if instruction has no operand size
2323 prefix and behave as 'P' otherwise
2324 'U' => print 'q' in 64bit mode if instruction has no operand size
2325 prefix and behave as 'Q' otherwise
2326 'V' => print 'q' in 64bit mode if instruction has no operand size
2327 prefix and behave as 'S' otherwise
2328 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2329 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2331 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2332 '!' => change condition from true to false or from false to true.
2333 '%' => add 1 upper case letter to the macro.
2334 '^' => print 'w' or 'l' depending on operand size prefix or
2335 suffix_always is true (lcall/ljmp).
2336 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2337 on operand size prefix.
2338 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2339 has no operand size prefix for AMD64 ISA, behave as 'P'
2342 2 upper case letter macros:
2343 "XY" => print 'x' or 'y' if suffix_always is true or no register
2344 operands and no broadcast.
2345 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2346 register operands and no broadcast.
2347 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2348 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2349 or suffix_always is true
2350 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2351 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2352 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2353 "LW" => print 'd', 'q' depending on the VEX.W bit
2354 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2355 an operand size prefix, or suffix_always is true. print
2356 'q' if rex prefix is present.
2358 Many of the above letters print nothing in Intel mode. See "putop"
2361 Braces '{' and '}', and vertical bars '|', indicate alternative
2362 mnemonic strings for AT&T and Intel. */
2364 static const struct dis386 dis386
[] = {
2366 { "addB", { Ebh1
, Gb
}, 0 },
2367 { "addS", { Evh1
, Gv
}, 0 },
2368 { "addB", { Gb
, EbS
}, 0 },
2369 { "addS", { Gv
, EvS
}, 0 },
2370 { "addB", { AL
, Ib
}, 0 },
2371 { "addS", { eAX
, Iv
}, 0 },
2372 { X86_64_TABLE (X86_64_06
) },
2373 { X86_64_TABLE (X86_64_07
) },
2375 { "orB", { Ebh1
, Gb
}, 0 },
2376 { "orS", { Evh1
, Gv
}, 0 },
2377 { "orB", { Gb
, EbS
}, 0 },
2378 { "orS", { Gv
, EvS
}, 0 },
2379 { "orB", { AL
, Ib
}, 0 },
2380 { "orS", { eAX
, Iv
}, 0 },
2381 { X86_64_TABLE (X86_64_0D
) },
2382 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2384 { "adcB", { Ebh1
, Gb
}, 0 },
2385 { "adcS", { Evh1
, Gv
}, 0 },
2386 { "adcB", { Gb
, EbS
}, 0 },
2387 { "adcS", { Gv
, EvS
}, 0 },
2388 { "adcB", { AL
, Ib
}, 0 },
2389 { "adcS", { eAX
, Iv
}, 0 },
2390 { X86_64_TABLE (X86_64_16
) },
2391 { X86_64_TABLE (X86_64_17
) },
2393 { "sbbB", { Ebh1
, Gb
}, 0 },
2394 { "sbbS", { Evh1
, Gv
}, 0 },
2395 { "sbbB", { Gb
, EbS
}, 0 },
2396 { "sbbS", { Gv
, EvS
}, 0 },
2397 { "sbbB", { AL
, Ib
}, 0 },
2398 { "sbbS", { eAX
, Iv
}, 0 },
2399 { X86_64_TABLE (X86_64_1E
) },
2400 { X86_64_TABLE (X86_64_1F
) },
2402 { "andB", { Ebh1
, Gb
}, 0 },
2403 { "andS", { Evh1
, Gv
}, 0 },
2404 { "andB", { Gb
, EbS
}, 0 },
2405 { "andS", { Gv
, EvS
}, 0 },
2406 { "andB", { AL
, Ib
}, 0 },
2407 { "andS", { eAX
, Iv
}, 0 },
2408 { Bad_Opcode
}, /* SEG ES prefix */
2409 { X86_64_TABLE (X86_64_27
) },
2411 { "subB", { Ebh1
, Gb
}, 0 },
2412 { "subS", { Evh1
, Gv
}, 0 },
2413 { "subB", { Gb
, EbS
}, 0 },
2414 { "subS", { Gv
, EvS
}, 0 },
2415 { "subB", { AL
, Ib
}, 0 },
2416 { "subS", { eAX
, Iv
}, 0 },
2417 { Bad_Opcode
}, /* SEG CS prefix */
2418 { X86_64_TABLE (X86_64_2F
) },
2420 { "xorB", { Ebh1
, Gb
}, 0 },
2421 { "xorS", { Evh1
, Gv
}, 0 },
2422 { "xorB", { Gb
, EbS
}, 0 },
2423 { "xorS", { Gv
, EvS
}, 0 },
2424 { "xorB", { AL
, Ib
}, 0 },
2425 { "xorS", { eAX
, Iv
}, 0 },
2426 { Bad_Opcode
}, /* SEG SS prefix */
2427 { X86_64_TABLE (X86_64_37
) },
2429 { "cmpB", { Eb
, Gb
}, 0 },
2430 { "cmpS", { Ev
, Gv
}, 0 },
2431 { "cmpB", { Gb
, EbS
}, 0 },
2432 { "cmpS", { Gv
, EvS
}, 0 },
2433 { "cmpB", { AL
, Ib
}, 0 },
2434 { "cmpS", { eAX
, Iv
}, 0 },
2435 { Bad_Opcode
}, /* SEG DS prefix */
2436 { X86_64_TABLE (X86_64_3F
) },
2438 { "inc{S|}", { RMeAX
}, 0 },
2439 { "inc{S|}", { RMeCX
}, 0 },
2440 { "inc{S|}", { RMeDX
}, 0 },
2441 { "inc{S|}", { RMeBX
}, 0 },
2442 { "inc{S|}", { RMeSP
}, 0 },
2443 { "inc{S|}", { RMeBP
}, 0 },
2444 { "inc{S|}", { RMeSI
}, 0 },
2445 { "inc{S|}", { RMeDI
}, 0 },
2447 { "dec{S|}", { RMeAX
}, 0 },
2448 { "dec{S|}", { RMeCX
}, 0 },
2449 { "dec{S|}", { RMeDX
}, 0 },
2450 { "dec{S|}", { RMeBX
}, 0 },
2451 { "dec{S|}", { RMeSP
}, 0 },
2452 { "dec{S|}", { RMeBP
}, 0 },
2453 { "dec{S|}", { RMeSI
}, 0 },
2454 { "dec{S|}", { RMeDI
}, 0 },
2456 { "pushV", { RMrAX
}, 0 },
2457 { "pushV", { RMrCX
}, 0 },
2458 { "pushV", { RMrDX
}, 0 },
2459 { "pushV", { RMrBX
}, 0 },
2460 { "pushV", { RMrSP
}, 0 },
2461 { "pushV", { RMrBP
}, 0 },
2462 { "pushV", { RMrSI
}, 0 },
2463 { "pushV", { RMrDI
}, 0 },
2465 { "popV", { RMrAX
}, 0 },
2466 { "popV", { RMrCX
}, 0 },
2467 { "popV", { RMrDX
}, 0 },
2468 { "popV", { RMrBX
}, 0 },
2469 { "popV", { RMrSP
}, 0 },
2470 { "popV", { RMrBP
}, 0 },
2471 { "popV", { RMrSI
}, 0 },
2472 { "popV", { RMrDI
}, 0 },
2474 { X86_64_TABLE (X86_64_60
) },
2475 { X86_64_TABLE (X86_64_61
) },
2476 { X86_64_TABLE (X86_64_62
) },
2477 { X86_64_TABLE (X86_64_63
) },
2478 { Bad_Opcode
}, /* seg fs */
2479 { Bad_Opcode
}, /* seg gs */
2480 { Bad_Opcode
}, /* op size prefix */
2481 { Bad_Opcode
}, /* adr size prefix */
2483 { "pushT", { sIv
}, 0 },
2484 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2485 { "pushT", { sIbT
}, 0 },
2486 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2487 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2488 { X86_64_TABLE (X86_64_6D
) },
2489 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2490 { X86_64_TABLE (X86_64_6F
) },
2492 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2493 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2494 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2495 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2496 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2497 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2498 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2499 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2501 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2502 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2503 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2504 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2505 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2506 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2507 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2508 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2510 { REG_TABLE (REG_80
) },
2511 { REG_TABLE (REG_81
) },
2512 { X86_64_TABLE (X86_64_82
) },
2513 { REG_TABLE (REG_83
) },
2514 { "testB", { Eb
, Gb
}, 0 },
2515 { "testS", { Ev
, Gv
}, 0 },
2516 { "xchgB", { Ebh2
, Gb
}, 0 },
2517 { "xchgS", { Evh2
, Gv
}, 0 },
2519 { "movB", { Ebh3
, Gb
}, 0 },
2520 { "movS", { Evh3
, Gv
}, 0 },
2521 { "movB", { Gb
, EbS
}, 0 },
2522 { "movS", { Gv
, EvS
}, 0 },
2523 { "movD", { Sv
, Sw
}, 0 },
2524 { MOD_TABLE (MOD_8D
) },
2525 { "movD", { Sw
, Sv
}, 0 },
2526 { REG_TABLE (REG_8F
) },
2528 { PREFIX_TABLE (PREFIX_90
) },
2529 { "xchgS", { RMeCX
, eAX
}, 0 },
2530 { "xchgS", { RMeDX
, eAX
}, 0 },
2531 { "xchgS", { RMeBX
, eAX
}, 0 },
2532 { "xchgS", { RMeSP
, eAX
}, 0 },
2533 { "xchgS", { RMeBP
, eAX
}, 0 },
2534 { "xchgS", { RMeSI
, eAX
}, 0 },
2535 { "xchgS", { RMeDI
, eAX
}, 0 },
2537 { "cW{t|}R", { XX
}, 0 },
2538 { "cR{t|}O", { XX
}, 0 },
2539 { X86_64_TABLE (X86_64_9A
) },
2540 { Bad_Opcode
}, /* fwait */
2541 { "pushfT", { XX
}, 0 },
2542 { "popfT", { XX
}, 0 },
2543 { "sahf", { XX
}, 0 },
2544 { "lahf", { XX
}, 0 },
2546 { "mov%LB", { AL
, Ob
}, 0 },
2547 { "mov%LS", { eAX
, Ov
}, 0 },
2548 { "mov%LB", { Ob
, AL
}, 0 },
2549 { "mov%LS", { Ov
, eAX
}, 0 },
2550 { "movs{b|}", { Ybr
, Xb
}, 0 },
2551 { "movs{R|}", { Yvr
, Xv
}, 0 },
2552 { "cmps{b|}", { Xb
, Yb
}, 0 },
2553 { "cmps{R|}", { Xv
, Yv
}, 0 },
2555 { "testB", { AL
, Ib
}, 0 },
2556 { "testS", { eAX
, Iv
}, 0 },
2557 { "stosB", { Ybr
, AL
}, 0 },
2558 { "stosS", { Yvr
, eAX
}, 0 },
2559 { "lodsB", { ALr
, Xb
}, 0 },
2560 { "lodsS", { eAXr
, Xv
}, 0 },
2561 { "scasB", { AL
, Yb
}, 0 },
2562 { "scasS", { eAX
, Yv
}, 0 },
2564 { "movB", { RMAL
, Ib
}, 0 },
2565 { "movB", { RMCL
, Ib
}, 0 },
2566 { "movB", { RMDL
, Ib
}, 0 },
2567 { "movB", { RMBL
, Ib
}, 0 },
2568 { "movB", { RMAH
, Ib
}, 0 },
2569 { "movB", { RMCH
, Ib
}, 0 },
2570 { "movB", { RMDH
, Ib
}, 0 },
2571 { "movB", { RMBH
, Ib
}, 0 },
2573 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2574 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2575 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2576 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2577 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2578 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2579 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2580 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2582 { REG_TABLE (REG_C0
) },
2583 { REG_TABLE (REG_C1
) },
2584 { "retT", { Iw
, BND
}, 0 },
2585 { "retT", { BND
}, 0 },
2586 { X86_64_TABLE (X86_64_C4
) },
2587 { X86_64_TABLE (X86_64_C5
) },
2588 { REG_TABLE (REG_C6
) },
2589 { REG_TABLE (REG_C7
) },
2591 { "enterT", { Iw
, Ib
}, 0 },
2592 { "leaveT", { XX
}, 0 },
2593 { "Jret{|f}P", { Iw
}, 0 },
2594 { "Jret{|f}P", { XX
}, 0 },
2595 { "int3", { XX
}, 0 },
2596 { "int", { Ib
}, 0 },
2597 { X86_64_TABLE (X86_64_CE
) },
2598 { "iret%LP", { XX
}, 0 },
2600 { REG_TABLE (REG_D0
) },
2601 { REG_TABLE (REG_D1
) },
2602 { REG_TABLE (REG_D2
) },
2603 { REG_TABLE (REG_D3
) },
2604 { X86_64_TABLE (X86_64_D4
) },
2605 { X86_64_TABLE (X86_64_D5
) },
2607 { "xlat", { DSBX
}, 0 },
2618 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2619 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2620 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2621 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2622 { "inB", { AL
, Ib
}, 0 },
2623 { "inG", { zAX
, Ib
}, 0 },
2624 { "outB", { Ib
, AL
}, 0 },
2625 { "outG", { Ib
, zAX
}, 0 },
2627 { X86_64_TABLE (X86_64_E8
) },
2628 { X86_64_TABLE (X86_64_E9
) },
2629 { X86_64_TABLE (X86_64_EA
) },
2630 { "jmp", { Jb
, BND
}, 0 },
2631 { "inB", { AL
, indirDX
}, 0 },
2632 { "inG", { zAX
, indirDX
}, 0 },
2633 { "outB", { indirDX
, AL
}, 0 },
2634 { "outG", { indirDX
, zAX
}, 0 },
2636 { Bad_Opcode
}, /* lock prefix */
2637 { "icebp", { XX
}, 0 },
2638 { Bad_Opcode
}, /* repne */
2639 { Bad_Opcode
}, /* repz */
2640 { "hlt", { XX
}, 0 },
2641 { "cmc", { XX
}, 0 },
2642 { REG_TABLE (REG_F6
) },
2643 { REG_TABLE (REG_F7
) },
2645 { "clc", { XX
}, 0 },
2646 { "stc", { XX
}, 0 },
2647 { "cli", { XX
}, 0 },
2648 { "sti", { XX
}, 0 },
2649 { "cld", { XX
}, 0 },
2650 { "std", { XX
}, 0 },
2651 { REG_TABLE (REG_FE
) },
2652 { REG_TABLE (REG_FF
) },
2655 static const struct dis386 dis386_twobyte
[] = {
2657 { REG_TABLE (REG_0F00
) },
2658 { REG_TABLE (REG_0F01
) },
2659 { "larS", { Gv
, Ew
}, 0 },
2660 { "lslS", { Gv
, Ew
}, 0 },
2662 { "syscall", { XX
}, 0 },
2663 { "clts", { XX
}, 0 },
2664 { "sysret%LP", { XX
}, 0 },
2666 { "invd", { XX
}, 0 },
2667 { PREFIX_TABLE (PREFIX_0F09
) },
2669 { "ud2", { XX
}, 0 },
2671 { REG_TABLE (REG_0F0D
) },
2672 { "femms", { XX
}, 0 },
2673 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2675 { PREFIX_TABLE (PREFIX_0F10
) },
2676 { PREFIX_TABLE (PREFIX_0F11
) },
2677 { PREFIX_TABLE (PREFIX_0F12
) },
2678 { MOD_TABLE (MOD_0F13
) },
2679 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2680 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2681 { PREFIX_TABLE (PREFIX_0F16
) },
2682 { MOD_TABLE (MOD_0F17
) },
2684 { REG_TABLE (REG_0F18
) },
2685 { "nopQ", { Ev
}, 0 },
2686 { PREFIX_TABLE (PREFIX_0F1A
) },
2687 { PREFIX_TABLE (PREFIX_0F1B
) },
2688 { PREFIX_TABLE (PREFIX_0F1C
) },
2689 { "nopQ", { Ev
}, 0 },
2690 { PREFIX_TABLE (PREFIX_0F1E
) },
2691 { "nopQ", { Ev
}, 0 },
2693 { "movZ", { Rm
, Cm
}, 0 },
2694 { "movZ", { Rm
, Dm
}, 0 },
2695 { "movZ", { Cm
, Rm
}, 0 },
2696 { "movZ", { Dm
, Rm
}, 0 },
2697 { MOD_TABLE (MOD_0F24
) },
2699 { MOD_TABLE (MOD_0F26
) },
2702 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2703 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2704 { PREFIX_TABLE (PREFIX_0F2A
) },
2705 { PREFIX_TABLE (PREFIX_0F2B
) },
2706 { PREFIX_TABLE (PREFIX_0F2C
) },
2707 { PREFIX_TABLE (PREFIX_0F2D
) },
2708 { PREFIX_TABLE (PREFIX_0F2E
) },
2709 { PREFIX_TABLE (PREFIX_0F2F
) },
2711 { "wrmsr", { XX
}, 0 },
2712 { "rdtsc", { XX
}, 0 },
2713 { "rdmsr", { XX
}, 0 },
2714 { "rdpmc", { XX
}, 0 },
2715 { "sysenter", { XX
}, 0 },
2716 { "sysexit", { XX
}, 0 },
2718 { "getsec", { XX
}, 0 },
2720 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2722 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2729 { "cmovoS", { Gv
, Ev
}, 0 },
2730 { "cmovnoS", { Gv
, Ev
}, 0 },
2731 { "cmovbS", { Gv
, Ev
}, 0 },
2732 { "cmovaeS", { Gv
, Ev
}, 0 },
2733 { "cmoveS", { Gv
, Ev
}, 0 },
2734 { "cmovneS", { Gv
, Ev
}, 0 },
2735 { "cmovbeS", { Gv
, Ev
}, 0 },
2736 { "cmovaS", { Gv
, Ev
}, 0 },
2738 { "cmovsS", { Gv
, Ev
}, 0 },
2739 { "cmovnsS", { Gv
, Ev
}, 0 },
2740 { "cmovpS", { Gv
, Ev
}, 0 },
2741 { "cmovnpS", { Gv
, Ev
}, 0 },
2742 { "cmovlS", { Gv
, Ev
}, 0 },
2743 { "cmovgeS", { Gv
, Ev
}, 0 },
2744 { "cmovleS", { Gv
, Ev
}, 0 },
2745 { "cmovgS", { Gv
, Ev
}, 0 },
2747 { MOD_TABLE (MOD_0F51
) },
2748 { PREFIX_TABLE (PREFIX_0F51
) },
2749 { PREFIX_TABLE (PREFIX_0F52
) },
2750 { PREFIX_TABLE (PREFIX_0F53
) },
2751 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2752 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2753 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2754 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2756 { PREFIX_TABLE (PREFIX_0F58
) },
2757 { PREFIX_TABLE (PREFIX_0F59
) },
2758 { PREFIX_TABLE (PREFIX_0F5A
) },
2759 { PREFIX_TABLE (PREFIX_0F5B
) },
2760 { PREFIX_TABLE (PREFIX_0F5C
) },
2761 { PREFIX_TABLE (PREFIX_0F5D
) },
2762 { PREFIX_TABLE (PREFIX_0F5E
) },
2763 { PREFIX_TABLE (PREFIX_0F5F
) },
2765 { PREFIX_TABLE (PREFIX_0F60
) },
2766 { PREFIX_TABLE (PREFIX_0F61
) },
2767 { PREFIX_TABLE (PREFIX_0F62
) },
2768 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2769 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2770 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2771 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2772 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2774 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2775 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2776 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2777 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2778 { PREFIX_TABLE (PREFIX_0F6C
) },
2779 { PREFIX_TABLE (PREFIX_0F6D
) },
2780 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2781 { PREFIX_TABLE (PREFIX_0F6F
) },
2783 { PREFIX_TABLE (PREFIX_0F70
) },
2784 { REG_TABLE (REG_0F71
) },
2785 { REG_TABLE (REG_0F72
) },
2786 { REG_TABLE (REG_0F73
) },
2787 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2788 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2789 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2790 { "emms", { XX
}, PREFIX_OPCODE
},
2792 { PREFIX_TABLE (PREFIX_0F78
) },
2793 { PREFIX_TABLE (PREFIX_0F79
) },
2796 { PREFIX_TABLE (PREFIX_0F7C
) },
2797 { PREFIX_TABLE (PREFIX_0F7D
) },
2798 { PREFIX_TABLE (PREFIX_0F7E
) },
2799 { PREFIX_TABLE (PREFIX_0F7F
) },
2801 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2802 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2803 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2804 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2805 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2806 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2807 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2808 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2810 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2811 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2812 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2813 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2814 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2815 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2816 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2817 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2819 { "seto", { Eb
}, 0 },
2820 { "setno", { Eb
}, 0 },
2821 { "setb", { Eb
}, 0 },
2822 { "setae", { Eb
}, 0 },
2823 { "sete", { Eb
}, 0 },
2824 { "setne", { Eb
}, 0 },
2825 { "setbe", { Eb
}, 0 },
2826 { "seta", { Eb
}, 0 },
2828 { "sets", { Eb
}, 0 },
2829 { "setns", { Eb
}, 0 },
2830 { "setp", { Eb
}, 0 },
2831 { "setnp", { Eb
}, 0 },
2832 { "setl", { Eb
}, 0 },
2833 { "setge", { Eb
}, 0 },
2834 { "setle", { Eb
}, 0 },
2835 { "setg", { Eb
}, 0 },
2837 { "pushT", { fs
}, 0 },
2838 { "popT", { fs
}, 0 },
2839 { "cpuid", { XX
}, 0 },
2840 { "btS", { Ev
, Gv
}, 0 },
2841 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2842 { "shldS", { Ev
, Gv
, CL
}, 0 },
2843 { REG_TABLE (REG_0FA6
) },
2844 { REG_TABLE (REG_0FA7
) },
2846 { "pushT", { gs
}, 0 },
2847 { "popT", { gs
}, 0 },
2848 { "rsm", { XX
}, 0 },
2849 { "btsS", { Evh1
, Gv
}, 0 },
2850 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2851 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2852 { REG_TABLE (REG_0FAE
) },
2853 { "imulS", { Gv
, Ev
}, 0 },
2855 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2856 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2857 { MOD_TABLE (MOD_0FB2
) },
2858 { "btrS", { Evh1
, Gv
}, 0 },
2859 { MOD_TABLE (MOD_0FB4
) },
2860 { MOD_TABLE (MOD_0FB5
) },
2861 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2862 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2864 { PREFIX_TABLE (PREFIX_0FB8
) },
2865 { "ud1S", { Gv
, Ev
}, 0 },
2866 { REG_TABLE (REG_0FBA
) },
2867 { "btcS", { Evh1
, Gv
}, 0 },
2868 { PREFIX_TABLE (PREFIX_0FBC
) },
2869 { PREFIX_TABLE (PREFIX_0FBD
) },
2870 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2871 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2873 { "xaddB", { Ebh1
, Gb
}, 0 },
2874 { "xaddS", { Evh1
, Gv
}, 0 },
2875 { PREFIX_TABLE (PREFIX_0FC2
) },
2876 { MOD_TABLE (MOD_0FC3
) },
2877 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2878 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2879 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2880 { REG_TABLE (REG_0FC7
) },
2882 { "bswap", { RMeAX
}, 0 },
2883 { "bswap", { RMeCX
}, 0 },
2884 { "bswap", { RMeDX
}, 0 },
2885 { "bswap", { RMeBX
}, 0 },
2886 { "bswap", { RMeSP
}, 0 },
2887 { "bswap", { RMeBP
}, 0 },
2888 { "bswap", { RMeSI
}, 0 },
2889 { "bswap", { RMeDI
}, 0 },
2891 { PREFIX_TABLE (PREFIX_0FD0
) },
2892 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2893 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2894 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2895 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2896 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2897 { PREFIX_TABLE (PREFIX_0FD6
) },
2898 { MOD_TABLE (MOD_0FD7
) },
2900 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2901 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2902 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2903 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2904 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2905 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2906 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2907 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2909 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2910 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2911 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2912 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2913 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2914 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2915 { PREFIX_TABLE (PREFIX_0FE6
) },
2916 { PREFIX_TABLE (PREFIX_0FE7
) },
2918 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2919 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2920 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2921 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2922 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2923 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2924 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2925 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2927 { PREFIX_TABLE (PREFIX_0FF0
) },
2928 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2929 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2930 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2931 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2932 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2933 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2934 { PREFIX_TABLE (PREFIX_0FF7
) },
2936 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2937 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2938 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2939 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2940 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2941 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2942 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2943 { "ud0S", { Gv
, Ev
}, 0 },
2946 static const unsigned char onebyte_has_modrm
[256] = {
2947 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2948 /* ------------------------------- */
2949 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2950 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2951 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2952 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2953 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2954 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2955 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2956 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2957 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2958 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2959 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2960 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2961 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2962 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2963 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2964 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2965 /* ------------------------------- */
2966 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2969 static const unsigned char twobyte_has_modrm
[256] = {
2970 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2971 /* ------------------------------- */
2972 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2973 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2974 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2975 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2976 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2977 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2978 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2979 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2980 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2981 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2982 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2983 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2984 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2985 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2986 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2987 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2988 /* ------------------------------- */
2989 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2992 static char obuf
[100];
2994 static char *mnemonicendp
;
2995 static char scratchbuf
[100];
2996 static unsigned char *start_codep
;
2997 static unsigned char *insn_codep
;
2998 static unsigned char *codep
;
2999 static unsigned char *end_codep
;
3000 static int last_lock_prefix
;
3001 static int last_repz_prefix
;
3002 static int last_repnz_prefix
;
3003 static int last_data_prefix
;
3004 static int last_addr_prefix
;
3005 static int last_rex_prefix
;
3006 static int last_seg_prefix
;
3007 static int fwait_prefix
;
3008 /* The active segment register prefix. */
3009 static int active_seg_prefix
;
3010 #define MAX_CODE_LENGTH 15
3011 /* We can up to 14 prefixes since the maximum instruction length is
3013 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3014 static disassemble_info
*the_info
;
3022 static unsigned char need_modrm
;
3032 int register_specifier
;
3039 int mask_register_specifier
;
3045 static unsigned char need_vex
;
3046 static unsigned char need_vex_reg
;
3047 static unsigned char vex_w_done
;
3055 /* If we are accessing mod/rm/reg without need_modrm set, then the
3056 values are stale. Hitting this abort likely indicates that you
3057 need to update onebyte_has_modrm or twobyte_has_modrm. */
3058 #define MODRM_CHECK if (!need_modrm) abort ()
3060 static const char **names64
;
3061 static const char **names32
;
3062 static const char **names16
;
3063 static const char **names8
;
3064 static const char **names8rex
;
3065 static const char **names_seg
;
3066 static const char *index64
;
3067 static const char *index32
;
3068 static const char **index16
;
3069 static const char **names_bnd
;
3071 static const char *intel_names64
[] = {
3072 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3073 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3075 static const char *intel_names32
[] = {
3076 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3077 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3079 static const char *intel_names16
[] = {
3080 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3081 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3083 static const char *intel_names8
[] = {
3084 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3086 static const char *intel_names8rex
[] = {
3087 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3088 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3090 static const char *intel_names_seg
[] = {
3091 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3093 static const char *intel_index64
= "riz";
3094 static const char *intel_index32
= "eiz";
3095 static const char *intel_index16
[] = {
3096 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3099 static const char *att_names64
[] = {
3100 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3101 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3103 static const char *att_names32
[] = {
3104 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3105 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3107 static const char *att_names16
[] = {
3108 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3109 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3111 static const char *att_names8
[] = {
3112 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3114 static const char *att_names8rex
[] = {
3115 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3116 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3118 static const char *att_names_seg
[] = {
3119 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3121 static const char *att_index64
= "%riz";
3122 static const char *att_index32
= "%eiz";
3123 static const char *att_index16
[] = {
3124 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3127 static const char **names_mm
;
3128 static const char *intel_names_mm
[] = {
3129 "mm0", "mm1", "mm2", "mm3",
3130 "mm4", "mm5", "mm6", "mm7"
3132 static const char *att_names_mm
[] = {
3133 "%mm0", "%mm1", "%mm2", "%mm3",
3134 "%mm4", "%mm5", "%mm6", "%mm7"
3137 static const char *intel_names_bnd
[] = {
3138 "bnd0", "bnd1", "bnd2", "bnd3"
3141 static const char *att_names_bnd
[] = {
3142 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3145 static const char **names_xmm
;
3146 static const char *intel_names_xmm
[] = {
3147 "xmm0", "xmm1", "xmm2", "xmm3",
3148 "xmm4", "xmm5", "xmm6", "xmm7",
3149 "xmm8", "xmm9", "xmm10", "xmm11",
3150 "xmm12", "xmm13", "xmm14", "xmm15",
3151 "xmm16", "xmm17", "xmm18", "xmm19",
3152 "xmm20", "xmm21", "xmm22", "xmm23",
3153 "xmm24", "xmm25", "xmm26", "xmm27",
3154 "xmm28", "xmm29", "xmm30", "xmm31"
3156 static const char *att_names_xmm
[] = {
3157 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3158 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3159 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3160 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3161 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3162 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3163 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3164 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3167 static const char **names_ymm
;
3168 static const char *intel_names_ymm
[] = {
3169 "ymm0", "ymm1", "ymm2", "ymm3",
3170 "ymm4", "ymm5", "ymm6", "ymm7",
3171 "ymm8", "ymm9", "ymm10", "ymm11",
3172 "ymm12", "ymm13", "ymm14", "ymm15",
3173 "ymm16", "ymm17", "ymm18", "ymm19",
3174 "ymm20", "ymm21", "ymm22", "ymm23",
3175 "ymm24", "ymm25", "ymm26", "ymm27",
3176 "ymm28", "ymm29", "ymm30", "ymm31"
3178 static const char *att_names_ymm
[] = {
3179 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3180 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3181 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3182 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3183 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3184 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3185 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3186 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3189 static const char **names_zmm
;
3190 static const char *intel_names_zmm
[] = {
3191 "zmm0", "zmm1", "zmm2", "zmm3",
3192 "zmm4", "zmm5", "zmm6", "zmm7",
3193 "zmm8", "zmm9", "zmm10", "zmm11",
3194 "zmm12", "zmm13", "zmm14", "zmm15",
3195 "zmm16", "zmm17", "zmm18", "zmm19",
3196 "zmm20", "zmm21", "zmm22", "zmm23",
3197 "zmm24", "zmm25", "zmm26", "zmm27",
3198 "zmm28", "zmm29", "zmm30", "zmm31"
3200 static const char *att_names_zmm
[] = {
3201 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3202 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3203 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3204 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3205 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3206 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3207 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3208 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3211 static const char **names_mask
;
3212 static const char *intel_names_mask
[] = {
3213 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3215 static const char *att_names_mask
[] = {
3216 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3219 static const char *names_rounding
[] =
3227 static const struct dis386 reg_table
[][8] = {
3230 { "addA", { Ebh1
, Ib
}, 0 },
3231 { "orA", { Ebh1
, Ib
}, 0 },
3232 { "adcA", { Ebh1
, Ib
}, 0 },
3233 { "sbbA", { Ebh1
, Ib
}, 0 },
3234 { "andA", { Ebh1
, Ib
}, 0 },
3235 { "subA", { Ebh1
, Ib
}, 0 },
3236 { "xorA", { Ebh1
, Ib
}, 0 },
3237 { "cmpA", { Eb
, Ib
}, 0 },
3241 { "addQ", { Evh1
, Iv
}, 0 },
3242 { "orQ", { Evh1
, Iv
}, 0 },
3243 { "adcQ", { Evh1
, Iv
}, 0 },
3244 { "sbbQ", { Evh1
, Iv
}, 0 },
3245 { "andQ", { Evh1
, Iv
}, 0 },
3246 { "subQ", { Evh1
, Iv
}, 0 },
3247 { "xorQ", { Evh1
, Iv
}, 0 },
3248 { "cmpQ", { Ev
, Iv
}, 0 },
3252 { "addQ", { Evh1
, sIb
}, 0 },
3253 { "orQ", { Evh1
, sIb
}, 0 },
3254 { "adcQ", { Evh1
, sIb
}, 0 },
3255 { "sbbQ", { Evh1
, sIb
}, 0 },
3256 { "andQ", { Evh1
, sIb
}, 0 },
3257 { "subQ", { Evh1
, sIb
}, 0 },
3258 { "xorQ", { Evh1
, sIb
}, 0 },
3259 { "cmpQ", { Ev
, sIb
}, 0 },
3263 { "popU", { stackEv
}, 0 },
3264 { XOP_8F_TABLE (XOP_09
) },
3268 { XOP_8F_TABLE (XOP_09
) },
3272 { "rolA", { Eb
, Ib
}, 0 },
3273 { "rorA", { Eb
, Ib
}, 0 },
3274 { "rclA", { Eb
, Ib
}, 0 },
3275 { "rcrA", { Eb
, Ib
}, 0 },
3276 { "shlA", { Eb
, Ib
}, 0 },
3277 { "shrA", { Eb
, Ib
}, 0 },
3278 { "shlA", { Eb
, Ib
}, 0 },
3279 { "sarA", { Eb
, Ib
}, 0 },
3283 { "rolQ", { Ev
, Ib
}, 0 },
3284 { "rorQ", { Ev
, Ib
}, 0 },
3285 { "rclQ", { Ev
, Ib
}, 0 },
3286 { "rcrQ", { Ev
, Ib
}, 0 },
3287 { "shlQ", { Ev
, Ib
}, 0 },
3288 { "shrQ", { Ev
, Ib
}, 0 },
3289 { "shlQ", { Ev
, Ib
}, 0 },
3290 { "sarQ", { Ev
, Ib
}, 0 },
3294 { "movA", { Ebh3
, Ib
}, 0 },
3301 { MOD_TABLE (MOD_C6_REG_7
) },
3305 { "movQ", { Evh3
, Iv
}, 0 },
3312 { MOD_TABLE (MOD_C7_REG_7
) },
3316 { "rolA", { Eb
, I1
}, 0 },
3317 { "rorA", { Eb
, I1
}, 0 },
3318 { "rclA", { Eb
, I1
}, 0 },
3319 { "rcrA", { Eb
, I1
}, 0 },
3320 { "shlA", { Eb
, I1
}, 0 },
3321 { "shrA", { Eb
, I1
}, 0 },
3322 { "shlA", { Eb
, I1
}, 0 },
3323 { "sarA", { Eb
, I1
}, 0 },
3327 { "rolQ", { Ev
, I1
}, 0 },
3328 { "rorQ", { Ev
, I1
}, 0 },
3329 { "rclQ", { Ev
, I1
}, 0 },
3330 { "rcrQ", { Ev
, I1
}, 0 },
3331 { "shlQ", { Ev
, I1
}, 0 },
3332 { "shrQ", { Ev
, I1
}, 0 },
3333 { "shlQ", { Ev
, I1
}, 0 },
3334 { "sarQ", { Ev
, I1
}, 0 },
3338 { "rolA", { Eb
, CL
}, 0 },
3339 { "rorA", { Eb
, CL
}, 0 },
3340 { "rclA", { Eb
, CL
}, 0 },
3341 { "rcrA", { Eb
, CL
}, 0 },
3342 { "shlA", { Eb
, CL
}, 0 },
3343 { "shrA", { Eb
, CL
}, 0 },
3344 { "shlA", { Eb
, CL
}, 0 },
3345 { "sarA", { Eb
, CL
}, 0 },
3349 { "rolQ", { Ev
, CL
}, 0 },
3350 { "rorQ", { Ev
, CL
}, 0 },
3351 { "rclQ", { Ev
, CL
}, 0 },
3352 { "rcrQ", { Ev
, CL
}, 0 },
3353 { "shlQ", { Ev
, CL
}, 0 },
3354 { "shrQ", { Ev
, CL
}, 0 },
3355 { "shlQ", { Ev
, CL
}, 0 },
3356 { "sarQ", { Ev
, CL
}, 0 },
3360 { "testA", { Eb
, Ib
}, 0 },
3361 { "testA", { Eb
, Ib
}, 0 },
3362 { "notA", { Ebh1
}, 0 },
3363 { "negA", { Ebh1
}, 0 },
3364 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3365 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3366 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3367 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3371 { "testQ", { Ev
, Iv
}, 0 },
3372 { "testQ", { Ev
, Iv
}, 0 },
3373 { "notQ", { Evh1
}, 0 },
3374 { "negQ", { Evh1
}, 0 },
3375 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3376 { "imulQ", { Ev
}, 0 },
3377 { "divQ", { Ev
}, 0 },
3378 { "idivQ", { Ev
}, 0 },
3382 { "incA", { Ebh1
}, 0 },
3383 { "decA", { Ebh1
}, 0 },
3387 { "incQ", { Evh1
}, 0 },
3388 { "decQ", { Evh1
}, 0 },
3389 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3390 { MOD_TABLE (MOD_FF_REG_3
) },
3391 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3392 { MOD_TABLE (MOD_FF_REG_5
) },
3393 { "pushU", { stackEv
}, 0 },
3398 { "sldtD", { Sv
}, 0 },
3399 { "strD", { Sv
}, 0 },
3400 { "lldt", { Ew
}, 0 },
3401 { "ltr", { Ew
}, 0 },
3402 { "verr", { Ew
}, 0 },
3403 { "verw", { Ew
}, 0 },
3409 { MOD_TABLE (MOD_0F01_REG_0
) },
3410 { MOD_TABLE (MOD_0F01_REG_1
) },
3411 { MOD_TABLE (MOD_0F01_REG_2
) },
3412 { MOD_TABLE (MOD_0F01_REG_3
) },
3413 { "smswD", { Sv
}, 0 },
3414 { MOD_TABLE (MOD_0F01_REG_5
) },
3415 { "lmsw", { Ew
}, 0 },
3416 { MOD_TABLE (MOD_0F01_REG_7
) },
3420 { "prefetch", { Mb
}, 0 },
3421 { "prefetchw", { Mb
}, 0 },
3422 { "prefetchwt1", { Mb
}, 0 },
3423 { "prefetch", { Mb
}, 0 },
3424 { "prefetch", { Mb
}, 0 },
3425 { "prefetch", { Mb
}, 0 },
3426 { "prefetch", { Mb
}, 0 },
3427 { "prefetch", { Mb
}, 0 },
3431 { MOD_TABLE (MOD_0F18_REG_0
) },
3432 { MOD_TABLE (MOD_0F18_REG_1
) },
3433 { MOD_TABLE (MOD_0F18_REG_2
) },
3434 { MOD_TABLE (MOD_0F18_REG_3
) },
3435 { MOD_TABLE (MOD_0F18_REG_4
) },
3436 { MOD_TABLE (MOD_0F18_REG_5
) },
3437 { MOD_TABLE (MOD_0F18_REG_6
) },
3438 { MOD_TABLE (MOD_0F18_REG_7
) },
3440 /* REG_0F1C_P_0_MOD_0 */
3442 { "cldemote", { Mb
}, 0 },
3443 { "nopQ", { Ev
}, 0 },
3444 { "nopQ", { Ev
}, 0 },
3445 { "nopQ", { Ev
}, 0 },
3446 { "nopQ", { Ev
}, 0 },
3447 { "nopQ", { Ev
}, 0 },
3448 { "nopQ", { Ev
}, 0 },
3449 { "nopQ", { Ev
}, 0 },
3451 /* REG_0F1E_P_1_MOD_3 */
3453 { "nopQ", { Ev
}, 0 },
3454 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3455 { "nopQ", { Ev
}, 0 },
3456 { "nopQ", { Ev
}, 0 },
3457 { "nopQ", { Ev
}, 0 },
3458 { "nopQ", { Ev
}, 0 },
3459 { "nopQ", { Ev
}, 0 },
3460 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
3466 { MOD_TABLE (MOD_0F71_REG_2
) },
3468 { MOD_TABLE (MOD_0F71_REG_4
) },
3470 { MOD_TABLE (MOD_0F71_REG_6
) },
3476 { MOD_TABLE (MOD_0F72_REG_2
) },
3478 { MOD_TABLE (MOD_0F72_REG_4
) },
3480 { MOD_TABLE (MOD_0F72_REG_6
) },
3486 { MOD_TABLE (MOD_0F73_REG_2
) },
3487 { MOD_TABLE (MOD_0F73_REG_3
) },
3490 { MOD_TABLE (MOD_0F73_REG_6
) },
3491 { MOD_TABLE (MOD_0F73_REG_7
) },
3495 { "montmul", { { OP_0f07
, 0 } }, 0 },
3496 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3497 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3501 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3502 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3503 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3504 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3505 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3506 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3510 { MOD_TABLE (MOD_0FAE_REG_0
) },
3511 { MOD_TABLE (MOD_0FAE_REG_1
) },
3512 { MOD_TABLE (MOD_0FAE_REG_2
) },
3513 { MOD_TABLE (MOD_0FAE_REG_3
) },
3514 { MOD_TABLE (MOD_0FAE_REG_4
) },
3515 { MOD_TABLE (MOD_0FAE_REG_5
) },
3516 { MOD_TABLE (MOD_0FAE_REG_6
) },
3517 { MOD_TABLE (MOD_0FAE_REG_7
) },
3525 { "btQ", { Ev
, Ib
}, 0 },
3526 { "btsQ", { Evh1
, Ib
}, 0 },
3527 { "btrQ", { Evh1
, Ib
}, 0 },
3528 { "btcQ", { Evh1
, Ib
}, 0 },
3533 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3535 { MOD_TABLE (MOD_0FC7_REG_3
) },
3536 { MOD_TABLE (MOD_0FC7_REG_4
) },
3537 { MOD_TABLE (MOD_0FC7_REG_5
) },
3538 { MOD_TABLE (MOD_0FC7_REG_6
) },
3539 { MOD_TABLE (MOD_0FC7_REG_7
) },
3545 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3547 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3549 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3555 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3557 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3559 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3565 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3566 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3569 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3570 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3576 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3577 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3579 /* REG_VEX_0F38F3 */
3582 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3583 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3584 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3588 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3589 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3593 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3594 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3596 /* REG_XOP_TBM_01 */
3599 { "blcfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3600 { "blsfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3601 { "blcs", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3602 { "tzmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3603 { "blcic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3604 { "blsic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3605 { "t1mskc", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3607 /* REG_XOP_TBM_02 */
3610 { "blcmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3615 { "blci", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3618 #include "i386-dis-evex-reg.h"
3621 static const struct dis386 prefix_table
[][4] = {
3624 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3625 { "pause", { XX
}, 0 },
3626 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3627 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3630 /* PREFIX_0F01_REG_5_MOD_0 */
3633 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3636 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3639 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3642 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3645 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3648 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3650 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3653 /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3655 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
3660 { "wbinvd", { XX
}, 0 },
3661 { "wbnoinvd", { XX
}, 0 },
3666 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3667 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3668 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3669 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3674 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3675 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3676 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3677 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3682 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3683 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3684 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3685 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3690 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3691 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3692 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3697 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3698 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3699 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3700 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3705 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3706 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3707 { "bndmov", { EbndS
, Gbnd
}, 0 },
3708 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3713 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3714 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3715 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3716 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3721 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3722 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3723 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3724 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3729 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3730 { "cvtsi2ss%LQ", { XM
, Edq
}, PREFIX_OPCODE
},
3731 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3732 { "cvtsi2sd%LQ", { XM
, Edq
}, 0 },
3737 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3738 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3739 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3740 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3745 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3746 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3747 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3748 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3753 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3754 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3755 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3756 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3761 { "ucomiss",{ XM
, EXd
}, 0 },
3763 { "ucomisd",{ XM
, EXq
}, 0 },
3768 { "comiss", { XM
, EXd
}, 0 },
3770 { "comisd", { XM
, EXq
}, 0 },
3775 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3776 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3777 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3778 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3783 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3784 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3789 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3790 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3795 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3796 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3797 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3798 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3803 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3804 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3805 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3806 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3811 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3812 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3813 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3814 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3819 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3820 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3821 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3826 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3827 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3828 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3829 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3834 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3835 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3836 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3837 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3842 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3843 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3844 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3845 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3850 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3851 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3852 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3853 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3858 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3860 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3865 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3867 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3872 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3874 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3881 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3888 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3893 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3894 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3895 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3900 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3901 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3902 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3903 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3906 /* PREFIX_0F73_REG_3 */
3910 { "psrldq", { XS
, Ib
}, 0 },
3913 /* PREFIX_0F73_REG_7 */
3917 { "pslldq", { XS
, Ib
}, 0 },
3922 {"vmread", { Em
, Gm
}, 0 },
3924 {"extrq", { XS
, Ib
, Ib
}, 0 },
3925 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3930 {"vmwrite", { Gm
, Em
}, 0 },
3932 {"extrq", { XM
, XS
}, 0 },
3933 {"insertq", { XM
, XS
}, 0 },
3940 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3941 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3948 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3949 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3954 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3955 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3956 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3961 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3962 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3963 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3966 /* PREFIX_0FAE_REG_0_MOD_3 */
3969 { "rdfsbase", { Ev
}, 0 },
3972 /* PREFIX_0FAE_REG_1_MOD_3 */
3975 { "rdgsbase", { Ev
}, 0 },
3978 /* PREFIX_0FAE_REG_2_MOD_3 */
3981 { "wrfsbase", { Ev
}, 0 },
3984 /* PREFIX_0FAE_REG_3_MOD_3 */
3987 { "wrgsbase", { Ev
}, 0 },
3990 /* PREFIX_0FAE_REG_4_MOD_0 */
3992 { "xsave", { FXSAVE
}, 0 },
3993 { "ptwrite%LQ", { Edq
}, 0 },
3996 /* PREFIX_0FAE_REG_4_MOD_3 */
3999 { "ptwrite%LQ", { Edq
}, 0 },
4002 /* PREFIX_0FAE_REG_5_MOD_0 */
4004 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
4007 /* PREFIX_0FAE_REG_5_MOD_3 */
4009 { "lfence", { Skip_MODRM
}, 0 },
4010 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
4013 /* PREFIX_0FAE_REG_6_MOD_0 */
4015 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
4016 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
4017 { "clwb", { Mb
}, PREFIX_OPCODE
},
4020 /* PREFIX_0FAE_REG_6_MOD_3 */
4022 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
4023 { "umonitor", { Eva
}, PREFIX_OPCODE
},
4024 { "tpause", { Edq
}, PREFIX_OPCODE
},
4025 { "umwait", { Edq
}, PREFIX_OPCODE
},
4028 /* PREFIX_0FAE_REG_7_MOD_0 */
4030 { "clflush", { Mb
}, 0 },
4032 { "clflushopt", { Mb
}, 0 },
4038 { "popcntS", { Gv
, Ev
}, 0 },
4043 { "bsfS", { Gv
, Ev
}, 0 },
4044 { "tzcntS", { Gv
, Ev
}, 0 },
4045 { "bsfS", { Gv
, Ev
}, 0 },
4050 { "bsrS", { Gv
, Ev
}, 0 },
4051 { "lzcntS", { Gv
, Ev
}, 0 },
4052 { "bsrS", { Gv
, Ev
}, 0 },
4057 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4058 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4059 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4060 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4063 /* PREFIX_0FC3_MOD_0 */
4065 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
4068 /* PREFIX_0FC7_REG_6_MOD_0 */
4070 { "vmptrld",{ Mq
}, 0 },
4071 { "vmxon", { Mq
}, 0 },
4072 { "vmclear",{ Mq
}, 0 },
4075 /* PREFIX_0FC7_REG_6_MOD_3 */
4077 { "rdrand", { Ev
}, 0 },
4079 { "rdrand", { Ev
}, 0 }
4082 /* PREFIX_0FC7_REG_7_MOD_3 */
4084 { "rdseed", { Ev
}, 0 },
4085 { "rdpid", { Em
}, 0 },
4086 { "rdseed", { Ev
}, 0 },
4093 { "addsubpd", { XM
, EXx
}, 0 },
4094 { "addsubps", { XM
, EXx
}, 0 },
4100 { "movq2dq",{ XM
, MS
}, 0 },
4101 { "movq", { EXqS
, XM
}, 0 },
4102 { "movdq2q",{ MX
, XS
}, 0 },
4108 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4109 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4110 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4115 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4117 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4125 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4130 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4132 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4139 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4146 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4153 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4160 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4167 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4174 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4181 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4188 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4195 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4202 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4209 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4216 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4223 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4230 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4237 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4244 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4251 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4258 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4265 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4272 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4279 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4286 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4293 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4300 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4307 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4314 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4321 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4328 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4335 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4342 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4349 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4356 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4363 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4370 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4375 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4380 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4385 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4390 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4395 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4400 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4407 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4414 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4421 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4428 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4435 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4442 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4447 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4449 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4450 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4455 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4457 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4458 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4465 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4470 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4471 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4472 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4479 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4480 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4481 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4486 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4493 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4500 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4507 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4514 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4521 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4528 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4535 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4542 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4549 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4556 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4563 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4570 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4577 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4584 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4591 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4598 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4605 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4612 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4619 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4626 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4633 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4640 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4645 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4652 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4659 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4666 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4669 /* PREFIX_VEX_0F10 */
4671 { "vmovups", { XM
, EXx
}, 0 },
4672 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
4673 { "vmovupd", { XM
, EXx
}, 0 },
4674 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
4677 /* PREFIX_VEX_0F11 */
4679 { "vmovups", { EXxS
, XM
}, 0 },
4680 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4681 { "vmovupd", { EXxS
, XM
}, 0 },
4682 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4685 /* PREFIX_VEX_0F12 */
4687 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4688 { "vmovsldup", { XM
, EXx
}, 0 },
4689 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4690 { "vmovddup", { XM
, EXymmq
}, 0 },
4693 /* PREFIX_VEX_0F16 */
4695 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4696 { "vmovshdup", { XM
, EXx
}, 0 },
4697 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4700 /* PREFIX_VEX_0F2A */
4703 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4705 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4708 /* PREFIX_VEX_0F2C */
4711 { "vcvttss2si", { Gdq
, EXdScalar
}, 0 },
4713 { "vcvttsd2si", { Gdq
, EXqScalar
}, 0 },
4716 /* PREFIX_VEX_0F2D */
4719 { "vcvtss2si", { Gdq
, EXdScalar
}, 0 },
4721 { "vcvtsd2si", { Gdq
, EXqScalar
}, 0 },
4724 /* PREFIX_VEX_0F2E */
4726 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
4728 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
4731 /* PREFIX_VEX_0F2F */
4733 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
4735 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
4738 /* PREFIX_VEX_0F41 */
4740 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4742 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4745 /* PREFIX_VEX_0F42 */
4747 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4749 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4752 /* PREFIX_VEX_0F44 */
4754 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4756 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4759 /* PREFIX_VEX_0F45 */
4761 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4763 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4766 /* PREFIX_VEX_0F46 */
4768 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4770 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4773 /* PREFIX_VEX_0F47 */
4775 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4777 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4780 /* PREFIX_VEX_0F4A */
4782 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4784 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4787 /* PREFIX_VEX_0F4B */
4789 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4791 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4794 /* PREFIX_VEX_0F51 */
4796 { "vsqrtps", { XM
, EXx
}, 0 },
4797 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4798 { "vsqrtpd", { XM
, EXx
}, 0 },
4799 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4802 /* PREFIX_VEX_0F52 */
4804 { "vrsqrtps", { XM
, EXx
}, 0 },
4805 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4808 /* PREFIX_VEX_0F53 */
4810 { "vrcpps", { XM
, EXx
}, 0 },
4811 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4814 /* PREFIX_VEX_0F58 */
4816 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4817 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4818 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4819 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4822 /* PREFIX_VEX_0F59 */
4824 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4825 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4826 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4827 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4830 /* PREFIX_VEX_0F5A */
4832 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4833 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4834 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4835 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4838 /* PREFIX_VEX_0F5B */
4840 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4841 { "vcvttps2dq", { XM
, EXx
}, 0 },
4842 { "vcvtps2dq", { XM
, EXx
}, 0 },
4845 /* PREFIX_VEX_0F5C */
4847 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4848 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4849 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4850 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4853 /* PREFIX_VEX_0F5D */
4855 { "vminps", { XM
, Vex
, EXx
}, 0 },
4856 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4857 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4858 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4861 /* PREFIX_VEX_0F5E */
4863 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4864 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4865 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4866 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4869 /* PREFIX_VEX_0F5F */
4871 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4872 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4873 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4874 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4877 /* PREFIX_VEX_0F60 */
4881 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4884 /* PREFIX_VEX_0F61 */
4888 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4891 /* PREFIX_VEX_0F62 */
4895 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4898 /* PREFIX_VEX_0F63 */
4902 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4905 /* PREFIX_VEX_0F64 */
4909 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4912 /* PREFIX_VEX_0F65 */
4916 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4919 /* PREFIX_VEX_0F66 */
4923 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4926 /* PREFIX_VEX_0F67 */
4930 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4933 /* PREFIX_VEX_0F68 */
4937 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4940 /* PREFIX_VEX_0F69 */
4944 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4947 /* PREFIX_VEX_0F6A */
4951 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4954 /* PREFIX_VEX_0F6B */
4958 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4961 /* PREFIX_VEX_0F6C */
4965 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4968 /* PREFIX_VEX_0F6D */
4972 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4975 /* PREFIX_VEX_0F6E */
4979 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4982 /* PREFIX_VEX_0F6F */
4985 { "vmovdqu", { XM
, EXx
}, 0 },
4986 { "vmovdqa", { XM
, EXx
}, 0 },
4989 /* PREFIX_VEX_0F70 */
4992 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4993 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4994 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4997 /* PREFIX_VEX_0F71_REG_2 */
5001 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
5004 /* PREFIX_VEX_0F71_REG_4 */
5008 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
5011 /* PREFIX_VEX_0F71_REG_6 */
5015 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
5018 /* PREFIX_VEX_0F72_REG_2 */
5022 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
5025 /* PREFIX_VEX_0F72_REG_4 */
5029 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
5032 /* PREFIX_VEX_0F72_REG_6 */
5036 { "vpslld", { Vex
, XS
, Ib
}, 0 },
5039 /* PREFIX_VEX_0F73_REG_2 */
5043 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5046 /* PREFIX_VEX_0F73_REG_3 */
5050 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5053 /* PREFIX_VEX_0F73_REG_6 */
5057 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5060 /* PREFIX_VEX_0F73_REG_7 */
5064 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5067 /* PREFIX_VEX_0F74 */
5071 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5074 /* PREFIX_VEX_0F75 */
5078 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5081 /* PREFIX_VEX_0F76 */
5085 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5088 /* PREFIX_VEX_0F77 */
5090 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5093 /* PREFIX_VEX_0F7C */
5097 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5098 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5101 /* PREFIX_VEX_0F7D */
5105 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5106 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5109 /* PREFIX_VEX_0F7E */
5112 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5113 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5116 /* PREFIX_VEX_0F7F */
5119 { "vmovdqu", { EXxS
, XM
}, 0 },
5120 { "vmovdqa", { EXxS
, XM
}, 0 },
5123 /* PREFIX_VEX_0F90 */
5125 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5127 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5130 /* PREFIX_VEX_0F91 */
5132 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5134 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5137 /* PREFIX_VEX_0F92 */
5139 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5141 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5142 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5145 /* PREFIX_VEX_0F93 */
5147 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5149 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5150 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5153 /* PREFIX_VEX_0F98 */
5155 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5157 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5160 /* PREFIX_VEX_0F99 */
5162 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5164 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5167 /* PREFIX_VEX_0FC2 */
5169 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5170 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
5171 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5172 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
5175 /* PREFIX_VEX_0FC4 */
5179 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5182 /* PREFIX_VEX_0FC5 */
5186 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5189 /* PREFIX_VEX_0FD0 */
5193 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5194 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5197 /* PREFIX_VEX_0FD1 */
5201 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5204 /* PREFIX_VEX_0FD2 */
5208 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5211 /* PREFIX_VEX_0FD3 */
5215 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5218 /* PREFIX_VEX_0FD4 */
5222 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5225 /* PREFIX_VEX_0FD5 */
5229 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5232 /* PREFIX_VEX_0FD6 */
5236 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5239 /* PREFIX_VEX_0FD7 */
5243 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5246 /* PREFIX_VEX_0FD8 */
5250 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5253 /* PREFIX_VEX_0FD9 */
5257 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5260 /* PREFIX_VEX_0FDA */
5264 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5267 /* PREFIX_VEX_0FDB */
5271 { "vpand", { XM
, Vex
, EXx
}, 0 },
5274 /* PREFIX_VEX_0FDC */
5278 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5281 /* PREFIX_VEX_0FDD */
5285 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5288 /* PREFIX_VEX_0FDE */
5292 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5295 /* PREFIX_VEX_0FDF */
5299 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5302 /* PREFIX_VEX_0FE0 */
5306 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5309 /* PREFIX_VEX_0FE1 */
5313 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5316 /* PREFIX_VEX_0FE2 */
5320 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5323 /* PREFIX_VEX_0FE3 */
5327 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5330 /* PREFIX_VEX_0FE4 */
5334 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5337 /* PREFIX_VEX_0FE5 */
5341 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5344 /* PREFIX_VEX_0FE6 */
5347 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5348 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5349 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5352 /* PREFIX_VEX_0FE7 */
5356 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5359 /* PREFIX_VEX_0FE8 */
5363 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5366 /* PREFIX_VEX_0FE9 */
5370 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5373 /* PREFIX_VEX_0FEA */
5377 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5380 /* PREFIX_VEX_0FEB */
5384 { "vpor", { XM
, Vex
, EXx
}, 0 },
5387 /* PREFIX_VEX_0FEC */
5391 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5394 /* PREFIX_VEX_0FED */
5398 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5401 /* PREFIX_VEX_0FEE */
5405 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5408 /* PREFIX_VEX_0FEF */
5412 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5415 /* PREFIX_VEX_0FF0 */
5420 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5423 /* PREFIX_VEX_0FF1 */
5427 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5430 /* PREFIX_VEX_0FF2 */
5434 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5437 /* PREFIX_VEX_0FF3 */
5441 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5444 /* PREFIX_VEX_0FF4 */
5448 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5451 /* PREFIX_VEX_0FF5 */
5455 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5458 /* PREFIX_VEX_0FF6 */
5462 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5465 /* PREFIX_VEX_0FF7 */
5469 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5472 /* PREFIX_VEX_0FF8 */
5476 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5479 /* PREFIX_VEX_0FF9 */
5483 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5486 /* PREFIX_VEX_0FFA */
5490 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5493 /* PREFIX_VEX_0FFB */
5497 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5500 /* PREFIX_VEX_0FFC */
5504 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5507 /* PREFIX_VEX_0FFD */
5511 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5514 /* PREFIX_VEX_0FFE */
5518 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5521 /* PREFIX_VEX_0F3800 */
5525 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5528 /* PREFIX_VEX_0F3801 */
5532 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5535 /* PREFIX_VEX_0F3802 */
5539 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5542 /* PREFIX_VEX_0F3803 */
5546 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5549 /* PREFIX_VEX_0F3804 */
5553 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5556 /* PREFIX_VEX_0F3805 */
5560 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5563 /* PREFIX_VEX_0F3806 */
5567 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5570 /* PREFIX_VEX_0F3807 */
5574 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5577 /* PREFIX_VEX_0F3808 */
5581 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5584 /* PREFIX_VEX_0F3809 */
5588 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5591 /* PREFIX_VEX_0F380A */
5595 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5598 /* PREFIX_VEX_0F380B */
5602 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5605 /* PREFIX_VEX_0F380C */
5609 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5612 /* PREFIX_VEX_0F380D */
5616 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5619 /* PREFIX_VEX_0F380E */
5623 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5626 /* PREFIX_VEX_0F380F */
5630 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5633 /* PREFIX_VEX_0F3813 */
5637 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5640 /* PREFIX_VEX_0F3816 */
5644 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5647 /* PREFIX_VEX_0F3817 */
5651 { "vptest", { XM
, EXx
}, 0 },
5654 /* PREFIX_VEX_0F3818 */
5658 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5661 /* PREFIX_VEX_0F3819 */
5665 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5668 /* PREFIX_VEX_0F381A */
5672 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5675 /* PREFIX_VEX_0F381C */
5679 { "vpabsb", { XM
, EXx
}, 0 },
5682 /* PREFIX_VEX_0F381D */
5686 { "vpabsw", { XM
, EXx
}, 0 },
5689 /* PREFIX_VEX_0F381E */
5693 { "vpabsd", { XM
, EXx
}, 0 },
5696 /* PREFIX_VEX_0F3820 */
5700 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5703 /* PREFIX_VEX_0F3821 */
5707 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5710 /* PREFIX_VEX_0F3822 */
5714 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5717 /* PREFIX_VEX_0F3823 */
5721 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5724 /* PREFIX_VEX_0F3824 */
5728 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5731 /* PREFIX_VEX_0F3825 */
5735 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5738 /* PREFIX_VEX_0F3828 */
5742 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5745 /* PREFIX_VEX_0F3829 */
5749 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5752 /* PREFIX_VEX_0F382A */
5756 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5759 /* PREFIX_VEX_0F382B */
5763 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5766 /* PREFIX_VEX_0F382C */
5770 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5773 /* PREFIX_VEX_0F382D */
5777 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5780 /* PREFIX_VEX_0F382E */
5784 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5787 /* PREFIX_VEX_0F382F */
5791 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5794 /* PREFIX_VEX_0F3830 */
5798 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5801 /* PREFIX_VEX_0F3831 */
5805 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5808 /* PREFIX_VEX_0F3832 */
5812 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5815 /* PREFIX_VEX_0F3833 */
5819 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5822 /* PREFIX_VEX_0F3834 */
5826 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5829 /* PREFIX_VEX_0F3835 */
5833 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5836 /* PREFIX_VEX_0F3836 */
5840 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5843 /* PREFIX_VEX_0F3837 */
5847 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5850 /* PREFIX_VEX_0F3838 */
5854 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5857 /* PREFIX_VEX_0F3839 */
5861 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5864 /* PREFIX_VEX_0F383A */
5868 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5871 /* PREFIX_VEX_0F383B */
5875 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5878 /* PREFIX_VEX_0F383C */
5882 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5885 /* PREFIX_VEX_0F383D */
5889 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5892 /* PREFIX_VEX_0F383E */
5896 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5899 /* PREFIX_VEX_0F383F */
5903 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5906 /* PREFIX_VEX_0F3840 */
5910 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5913 /* PREFIX_VEX_0F3841 */
5917 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5920 /* PREFIX_VEX_0F3845 */
5924 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5927 /* PREFIX_VEX_0F3846 */
5931 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5934 /* PREFIX_VEX_0F3847 */
5938 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5941 /* PREFIX_VEX_0F3858 */
5945 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5948 /* PREFIX_VEX_0F3859 */
5952 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5955 /* PREFIX_VEX_0F385A */
5959 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5962 /* PREFIX_VEX_0F3878 */
5966 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5969 /* PREFIX_VEX_0F3879 */
5973 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5976 /* PREFIX_VEX_0F388C */
5980 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5983 /* PREFIX_VEX_0F388E */
5987 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5990 /* PREFIX_VEX_0F3890 */
5994 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5997 /* PREFIX_VEX_0F3891 */
6001 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6004 /* PREFIX_VEX_0F3892 */
6008 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6011 /* PREFIX_VEX_0F3893 */
6015 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6018 /* PREFIX_VEX_0F3896 */
6022 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6025 /* PREFIX_VEX_0F3897 */
6029 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6032 /* PREFIX_VEX_0F3898 */
6036 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6039 /* PREFIX_VEX_0F3899 */
6043 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6046 /* PREFIX_VEX_0F389A */
6050 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6053 /* PREFIX_VEX_0F389B */
6057 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6060 /* PREFIX_VEX_0F389C */
6064 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6067 /* PREFIX_VEX_0F389D */
6071 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6074 /* PREFIX_VEX_0F389E */
6078 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6081 /* PREFIX_VEX_0F389F */
6085 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6088 /* PREFIX_VEX_0F38A6 */
6092 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6096 /* PREFIX_VEX_0F38A7 */
6100 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6103 /* PREFIX_VEX_0F38A8 */
6107 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6110 /* PREFIX_VEX_0F38A9 */
6114 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6117 /* PREFIX_VEX_0F38AA */
6121 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6124 /* PREFIX_VEX_0F38AB */
6128 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6131 /* PREFIX_VEX_0F38AC */
6135 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6138 /* PREFIX_VEX_0F38AD */
6142 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6145 /* PREFIX_VEX_0F38AE */
6149 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6152 /* PREFIX_VEX_0F38AF */
6156 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6159 /* PREFIX_VEX_0F38B6 */
6163 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6166 /* PREFIX_VEX_0F38B7 */
6170 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6173 /* PREFIX_VEX_0F38B8 */
6177 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6180 /* PREFIX_VEX_0F38B9 */
6184 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6187 /* PREFIX_VEX_0F38BA */
6191 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6194 /* PREFIX_VEX_0F38BB */
6198 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6201 /* PREFIX_VEX_0F38BC */
6205 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6208 /* PREFIX_VEX_0F38BD */
6212 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6215 /* PREFIX_VEX_0F38BE */
6219 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6222 /* PREFIX_VEX_0F38BF */
6226 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6229 /* PREFIX_VEX_0F38CF */
6233 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6236 /* PREFIX_VEX_0F38DB */
6240 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6243 /* PREFIX_VEX_0F38DC */
6247 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6250 /* PREFIX_VEX_0F38DD */
6254 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6257 /* PREFIX_VEX_0F38DE */
6261 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6264 /* PREFIX_VEX_0F38DF */
6268 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6271 /* PREFIX_VEX_0F38F2 */
6273 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6276 /* PREFIX_VEX_0F38F3_REG_1 */
6278 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6281 /* PREFIX_VEX_0F38F3_REG_2 */
6283 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6286 /* PREFIX_VEX_0F38F3_REG_3 */
6288 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6291 /* PREFIX_VEX_0F38F5 */
6293 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6294 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6296 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6299 /* PREFIX_VEX_0F38F6 */
6304 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6307 /* PREFIX_VEX_0F38F7 */
6309 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6310 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6311 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6312 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6315 /* PREFIX_VEX_0F3A00 */
6319 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6322 /* PREFIX_VEX_0F3A01 */
6326 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6329 /* PREFIX_VEX_0F3A02 */
6333 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6336 /* PREFIX_VEX_0F3A04 */
6340 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6343 /* PREFIX_VEX_0F3A05 */
6347 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6350 /* PREFIX_VEX_0F3A06 */
6354 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6357 /* PREFIX_VEX_0F3A08 */
6361 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6364 /* PREFIX_VEX_0F3A09 */
6368 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6371 /* PREFIX_VEX_0F3A0A */
6375 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
6378 /* PREFIX_VEX_0F3A0B */
6382 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
6385 /* PREFIX_VEX_0F3A0C */
6389 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6392 /* PREFIX_VEX_0F3A0D */
6396 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6399 /* PREFIX_VEX_0F3A0E */
6403 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6406 /* PREFIX_VEX_0F3A0F */
6410 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6413 /* PREFIX_VEX_0F3A14 */
6417 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6420 /* PREFIX_VEX_0F3A15 */
6424 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6427 /* PREFIX_VEX_0F3A16 */
6431 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6434 /* PREFIX_VEX_0F3A17 */
6438 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6441 /* PREFIX_VEX_0F3A18 */
6445 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6448 /* PREFIX_VEX_0F3A19 */
6452 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6455 /* PREFIX_VEX_0F3A1D */
6459 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6462 /* PREFIX_VEX_0F3A20 */
6466 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6469 /* PREFIX_VEX_0F3A21 */
6473 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6476 /* PREFIX_VEX_0F3A22 */
6480 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6483 /* PREFIX_VEX_0F3A30 */
6487 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6490 /* PREFIX_VEX_0F3A31 */
6494 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6497 /* PREFIX_VEX_0F3A32 */
6501 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6504 /* PREFIX_VEX_0F3A33 */
6508 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6511 /* PREFIX_VEX_0F3A38 */
6515 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6518 /* PREFIX_VEX_0F3A39 */
6522 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6525 /* PREFIX_VEX_0F3A40 */
6529 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6532 /* PREFIX_VEX_0F3A41 */
6536 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6539 /* PREFIX_VEX_0F3A42 */
6543 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6546 /* PREFIX_VEX_0F3A44 */
6550 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6553 /* PREFIX_VEX_0F3A46 */
6557 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6560 /* PREFIX_VEX_0F3A48 */
6564 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6567 /* PREFIX_VEX_0F3A49 */
6571 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6574 /* PREFIX_VEX_0F3A4A */
6578 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6581 /* PREFIX_VEX_0F3A4B */
6585 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6588 /* PREFIX_VEX_0F3A4C */
6592 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6595 /* PREFIX_VEX_0F3A5C */
6599 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6602 /* PREFIX_VEX_0F3A5D */
6606 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6609 /* PREFIX_VEX_0F3A5E */
6613 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6616 /* PREFIX_VEX_0F3A5F */
6620 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6623 /* PREFIX_VEX_0F3A60 */
6627 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6631 /* PREFIX_VEX_0F3A61 */
6635 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6638 /* PREFIX_VEX_0F3A62 */
6642 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6645 /* PREFIX_VEX_0F3A63 */
6649 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6652 /* PREFIX_VEX_0F3A68 */
6656 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6659 /* PREFIX_VEX_0F3A69 */
6663 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6666 /* PREFIX_VEX_0F3A6A */
6670 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6673 /* PREFIX_VEX_0F3A6B */
6677 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6680 /* PREFIX_VEX_0F3A6C */
6684 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6687 /* PREFIX_VEX_0F3A6D */
6691 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6694 /* PREFIX_VEX_0F3A6E */
6698 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6701 /* PREFIX_VEX_0F3A6F */
6705 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6708 /* PREFIX_VEX_0F3A78 */
6712 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6715 /* PREFIX_VEX_0F3A79 */
6719 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6722 /* PREFIX_VEX_0F3A7A */
6726 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6729 /* PREFIX_VEX_0F3A7B */
6733 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6736 /* PREFIX_VEX_0F3A7C */
6740 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6744 /* PREFIX_VEX_0F3A7D */
6748 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6751 /* PREFIX_VEX_0F3A7E */
6755 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6758 /* PREFIX_VEX_0F3A7F */
6762 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6765 /* PREFIX_VEX_0F3ACE */
6769 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6772 /* PREFIX_VEX_0F3ACF */
6776 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6779 /* PREFIX_VEX_0F3ADF */
6783 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6786 /* PREFIX_VEX_0F3AF0 */
6791 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6794 #include "i386-dis-evex-prefix.h"
6797 static const struct dis386 x86_64_table
[][2] = {
6800 { "pushP", { es
}, 0 },
6805 { "popP", { es
}, 0 },
6810 { "pushP", { cs
}, 0 },
6815 { "pushP", { ss
}, 0 },
6820 { "popP", { ss
}, 0 },
6825 { "pushP", { ds
}, 0 },
6830 { "popP", { ds
}, 0 },
6835 { "daa", { XX
}, 0 },
6840 { "das", { XX
}, 0 },
6845 { "aaa", { XX
}, 0 },
6850 { "aas", { XX
}, 0 },
6855 { "pushaP", { XX
}, 0 },
6860 { "popaP", { XX
}, 0 },
6865 { MOD_TABLE (MOD_62_32BIT
) },
6866 { EVEX_TABLE (EVEX_0F
) },
6871 { "arpl", { Ew
, Gw
}, 0 },
6872 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6877 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6878 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6883 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6884 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6889 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6890 { REG_TABLE (REG_80
) },
6895 { "Jcall{T|}", { Ap
}, 0 },
6900 { MOD_TABLE (MOD_C4_32BIT
) },
6901 { VEX_C4_TABLE (VEX_0F
) },
6906 { MOD_TABLE (MOD_C5_32BIT
) },
6907 { VEX_C5_TABLE (VEX_0F
) },
6912 { "into", { XX
}, 0 },
6917 { "aam", { Ib
}, 0 },
6922 { "aad", { Ib
}, 0 },
6927 { "callP", { Jv
, BND
}, 0 },
6928 { "call@", { Jv
, BND
}, 0 }
6933 { "jmpP", { Jv
, BND
}, 0 },
6934 { "jmp@", { Jv
, BND
}, 0 }
6939 { "Jjmp{T|}", { Ap
}, 0 },
6942 /* X86_64_0F01_REG_0 */
6944 { "sgdt{Q|IQ}", { M
}, 0 },
6945 { "sgdt", { M
}, 0 },
6948 /* X86_64_0F01_REG_1 */
6950 { "sidt{Q|IQ}", { M
}, 0 },
6951 { "sidt", { M
}, 0 },
6954 /* X86_64_0F01_REG_2 */
6956 { "lgdt{Q|Q}", { M
}, 0 },
6957 { "lgdt", { M
}, 0 },
6960 /* X86_64_0F01_REG_3 */
6962 { "lidt{Q|Q}", { M
}, 0 },
6963 { "lidt", { M
}, 0 },
6967 static const struct dis386 three_byte_table
[][256] = {
6969 /* THREE_BYTE_0F38 */
6972 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6973 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6974 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6975 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6976 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6977 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6978 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6979 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6981 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6982 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6983 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6984 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6990 { PREFIX_TABLE (PREFIX_0F3810
) },
6994 { PREFIX_TABLE (PREFIX_0F3814
) },
6995 { PREFIX_TABLE (PREFIX_0F3815
) },
6997 { PREFIX_TABLE (PREFIX_0F3817
) },
7003 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7004 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7005 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7008 { PREFIX_TABLE (PREFIX_0F3820
) },
7009 { PREFIX_TABLE (PREFIX_0F3821
) },
7010 { PREFIX_TABLE (PREFIX_0F3822
) },
7011 { PREFIX_TABLE (PREFIX_0F3823
) },
7012 { PREFIX_TABLE (PREFIX_0F3824
) },
7013 { PREFIX_TABLE (PREFIX_0F3825
) },
7017 { PREFIX_TABLE (PREFIX_0F3828
) },
7018 { PREFIX_TABLE (PREFIX_0F3829
) },
7019 { PREFIX_TABLE (PREFIX_0F382A
) },
7020 { PREFIX_TABLE (PREFIX_0F382B
) },
7026 { PREFIX_TABLE (PREFIX_0F3830
) },
7027 { PREFIX_TABLE (PREFIX_0F3831
) },
7028 { PREFIX_TABLE (PREFIX_0F3832
) },
7029 { PREFIX_TABLE (PREFIX_0F3833
) },
7030 { PREFIX_TABLE (PREFIX_0F3834
) },
7031 { PREFIX_TABLE (PREFIX_0F3835
) },
7033 { PREFIX_TABLE (PREFIX_0F3837
) },
7035 { PREFIX_TABLE (PREFIX_0F3838
) },
7036 { PREFIX_TABLE (PREFIX_0F3839
) },
7037 { PREFIX_TABLE (PREFIX_0F383A
) },
7038 { PREFIX_TABLE (PREFIX_0F383B
) },
7039 { PREFIX_TABLE (PREFIX_0F383C
) },
7040 { PREFIX_TABLE (PREFIX_0F383D
) },
7041 { PREFIX_TABLE (PREFIX_0F383E
) },
7042 { PREFIX_TABLE (PREFIX_0F383F
) },
7044 { PREFIX_TABLE (PREFIX_0F3840
) },
7045 { PREFIX_TABLE (PREFIX_0F3841
) },
7116 { PREFIX_TABLE (PREFIX_0F3880
) },
7117 { PREFIX_TABLE (PREFIX_0F3881
) },
7118 { PREFIX_TABLE (PREFIX_0F3882
) },
7197 { PREFIX_TABLE (PREFIX_0F38C8
) },
7198 { PREFIX_TABLE (PREFIX_0F38C9
) },
7199 { PREFIX_TABLE (PREFIX_0F38CA
) },
7200 { PREFIX_TABLE (PREFIX_0F38CB
) },
7201 { PREFIX_TABLE (PREFIX_0F38CC
) },
7202 { PREFIX_TABLE (PREFIX_0F38CD
) },
7204 { PREFIX_TABLE (PREFIX_0F38CF
) },
7218 { PREFIX_TABLE (PREFIX_0F38DB
) },
7219 { PREFIX_TABLE (PREFIX_0F38DC
) },
7220 { PREFIX_TABLE (PREFIX_0F38DD
) },
7221 { PREFIX_TABLE (PREFIX_0F38DE
) },
7222 { PREFIX_TABLE (PREFIX_0F38DF
) },
7242 { PREFIX_TABLE (PREFIX_0F38F0
) },
7243 { PREFIX_TABLE (PREFIX_0F38F1
) },
7247 { PREFIX_TABLE (PREFIX_0F38F5
) },
7248 { PREFIX_TABLE (PREFIX_0F38F6
) },
7251 { PREFIX_TABLE (PREFIX_0F38F8
) },
7252 { PREFIX_TABLE (PREFIX_0F38F9
) },
7260 /* THREE_BYTE_0F3A */
7272 { PREFIX_TABLE (PREFIX_0F3A08
) },
7273 { PREFIX_TABLE (PREFIX_0F3A09
) },
7274 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7275 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7276 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7277 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7278 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7279 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7285 { PREFIX_TABLE (PREFIX_0F3A14
) },
7286 { PREFIX_TABLE (PREFIX_0F3A15
) },
7287 { PREFIX_TABLE (PREFIX_0F3A16
) },
7288 { PREFIX_TABLE (PREFIX_0F3A17
) },
7299 { PREFIX_TABLE (PREFIX_0F3A20
) },
7300 { PREFIX_TABLE (PREFIX_0F3A21
) },
7301 { PREFIX_TABLE (PREFIX_0F3A22
) },
7335 { PREFIX_TABLE (PREFIX_0F3A40
) },
7336 { PREFIX_TABLE (PREFIX_0F3A41
) },
7337 { PREFIX_TABLE (PREFIX_0F3A42
) },
7339 { PREFIX_TABLE (PREFIX_0F3A44
) },
7371 { PREFIX_TABLE (PREFIX_0F3A60
) },
7372 { PREFIX_TABLE (PREFIX_0F3A61
) },
7373 { PREFIX_TABLE (PREFIX_0F3A62
) },
7374 { PREFIX_TABLE (PREFIX_0F3A63
) },
7492 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7494 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7495 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7513 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7553 static const struct dis386 xop_table
[][256] = {
7706 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7707 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7708 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7716 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7717 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7724 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7725 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7726 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7734 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7735 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7739 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7740 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7743 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7761 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7773 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7774 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7775 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7776 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7786 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7787 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7788 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7789 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7822 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7823 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7824 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7825 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7849 { REG_TABLE (REG_XOP_TBM_01
) },
7850 { REG_TABLE (REG_XOP_TBM_02
) },
7868 { REG_TABLE (REG_XOP_LWPCB
) },
7992 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7993 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7994 { "vfrczss", { XM
, EXd
}, 0 },
7995 { "vfrczsd", { XM
, EXq
}, 0 },
8010 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8011 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8012 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8013 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8014 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8015 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8016 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8017 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8019 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8020 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8021 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8022 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8065 { "vphaddbw", { XM
, EXxmm
}, 0 },
8066 { "vphaddbd", { XM
, EXxmm
}, 0 },
8067 { "vphaddbq", { XM
, EXxmm
}, 0 },
8070 { "vphaddwd", { XM
, EXxmm
}, 0 },
8071 { "vphaddwq", { XM
, EXxmm
}, 0 },
8076 { "vphadddq", { XM
, EXxmm
}, 0 },
8083 { "vphaddubw", { XM
, EXxmm
}, 0 },
8084 { "vphaddubd", { XM
, EXxmm
}, 0 },
8085 { "vphaddubq", { XM
, EXxmm
}, 0 },
8088 { "vphadduwd", { XM
, EXxmm
}, 0 },
8089 { "vphadduwq", { XM
, EXxmm
}, 0 },
8094 { "vphaddudq", { XM
, EXxmm
}, 0 },
8101 { "vphsubbw", { XM
, EXxmm
}, 0 },
8102 { "vphsubwd", { XM
, EXxmm
}, 0 },
8103 { "vphsubdq", { XM
, EXxmm
}, 0 },
8157 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8159 { REG_TABLE (REG_XOP_LWP
) },
8429 static const struct dis386 vex_table
[][256] = {
8451 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8452 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8453 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8454 { MOD_TABLE (MOD_VEX_0F13
) },
8455 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
8456 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
8457 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8458 { MOD_TABLE (MOD_VEX_0F17
) },
8478 { "vmovapX", { XM
, EXx
}, 0 },
8479 { "vmovapX", { EXxS
, XM
}, 0 },
8480 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8481 { MOD_TABLE (MOD_VEX_0F2B
) },
8482 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8483 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8484 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8485 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8506 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8507 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8509 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8510 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8511 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8512 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8516 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8517 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8523 { MOD_TABLE (MOD_VEX_0F50
) },
8524 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8525 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8526 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8527 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8528 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8529 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8530 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8532 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8533 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8534 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8535 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8536 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8537 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8538 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8539 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8541 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8542 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8543 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8544 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8545 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8546 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8547 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8548 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8550 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8551 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8552 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8553 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8555 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8556 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8557 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8559 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8560 { REG_TABLE (REG_VEX_0F71
) },
8561 { REG_TABLE (REG_VEX_0F72
) },
8562 { REG_TABLE (REG_VEX_0F73
) },
8563 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8564 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8565 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8566 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8572 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8573 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8574 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8575 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8595 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8596 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8597 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8598 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8604 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8605 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8628 { REG_TABLE (REG_VEX_0FAE
) },
8651 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8653 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8654 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8655 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8667 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8668 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8672 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8677 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8686 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8688 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8690 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8745 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8823 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8824 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8825 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8859 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8860 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8881 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8997 { REG_TABLE (REG_VEX_0F38F3
) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9020 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9031 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9118 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9137 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9139 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9150 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9151 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9152 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9246 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9247 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9265 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9285 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9305 #include "i386-dis-evex.h"
9307 static const struct dis386 vex_len_table
[][2] = {
9308 /* VEX_LEN_0F12_P_0_M_0 */
9310 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
9313 /* VEX_LEN_0F12_P_0_M_1 */
9315 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9318 /* VEX_LEN_0F12_P_2 */
9320 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
9323 /* VEX_LEN_0F13_M_0 */
9325 { "vmovlpX", { EXq
, XM
}, 0 },
9328 /* VEX_LEN_0F16_P_0_M_0 */
9330 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
9333 /* VEX_LEN_0F16_P_0_M_1 */
9335 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9338 /* VEX_LEN_0F16_P_2 */
9340 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
9343 /* VEX_LEN_0F17_M_0 */
9345 { "vmovhpX", { EXq
, XM
}, 0 },
9348 /* VEX_LEN_0F41_P_0 */
9351 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9353 /* VEX_LEN_0F41_P_2 */
9356 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9358 /* VEX_LEN_0F42_P_0 */
9361 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9363 /* VEX_LEN_0F42_P_2 */
9366 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9368 /* VEX_LEN_0F44_P_0 */
9370 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9372 /* VEX_LEN_0F44_P_2 */
9374 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9376 /* VEX_LEN_0F45_P_0 */
9379 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9381 /* VEX_LEN_0F45_P_2 */
9384 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9386 /* VEX_LEN_0F46_P_0 */
9389 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9391 /* VEX_LEN_0F46_P_2 */
9394 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9396 /* VEX_LEN_0F47_P_0 */
9399 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9401 /* VEX_LEN_0F47_P_2 */
9404 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9406 /* VEX_LEN_0F4A_P_0 */
9409 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9411 /* VEX_LEN_0F4A_P_2 */
9414 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9416 /* VEX_LEN_0F4B_P_0 */
9419 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9421 /* VEX_LEN_0F4B_P_2 */
9424 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9427 /* VEX_LEN_0F6E_P_2 */
9429 { "vmovK", { XMScalar
, Edq
}, 0 },
9432 /* VEX_LEN_0F77_P_1 */
9434 { "vzeroupper", { XX
}, 0 },
9435 { "vzeroall", { XX
}, 0 },
9438 /* VEX_LEN_0F7E_P_1 */
9440 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
9443 /* VEX_LEN_0F7E_P_2 */
9445 { "vmovK", { Edq
, XMScalar
}, 0 },
9448 /* VEX_LEN_0F90_P_0 */
9450 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9453 /* VEX_LEN_0F90_P_2 */
9455 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9458 /* VEX_LEN_0F91_P_0 */
9460 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9463 /* VEX_LEN_0F91_P_2 */
9465 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9468 /* VEX_LEN_0F92_P_0 */
9470 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9473 /* VEX_LEN_0F92_P_2 */
9475 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9478 /* VEX_LEN_0F92_P_3 */
9480 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9483 /* VEX_LEN_0F93_P_0 */
9485 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9488 /* VEX_LEN_0F93_P_2 */
9490 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9493 /* VEX_LEN_0F93_P_3 */
9495 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9498 /* VEX_LEN_0F98_P_0 */
9500 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9503 /* VEX_LEN_0F98_P_2 */
9505 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9508 /* VEX_LEN_0F99_P_0 */
9510 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9513 /* VEX_LEN_0F99_P_2 */
9515 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9518 /* VEX_LEN_0FAE_R_2_M_0 */
9520 { "vldmxcsr", { Md
}, 0 },
9523 /* VEX_LEN_0FAE_R_3_M_0 */
9525 { "vstmxcsr", { Md
}, 0 },
9528 /* VEX_LEN_0FC4_P_2 */
9530 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9533 /* VEX_LEN_0FC5_P_2 */
9535 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9538 /* VEX_LEN_0FD6_P_2 */
9540 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
9543 /* VEX_LEN_0FF7_P_2 */
9545 { "vmaskmovdqu", { XM
, XS
}, 0 },
9548 /* VEX_LEN_0F3816_P_2 */
9551 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9554 /* VEX_LEN_0F3819_P_2 */
9557 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9560 /* VEX_LEN_0F381A_P_2_M_0 */
9563 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9566 /* VEX_LEN_0F3836_P_2 */
9569 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9572 /* VEX_LEN_0F3841_P_2 */
9574 { "vphminposuw", { XM
, EXx
}, 0 },
9577 /* VEX_LEN_0F385A_P_2_M_0 */
9580 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9583 /* VEX_LEN_0F38DB_P_2 */
9585 { "vaesimc", { XM
, EXx
}, 0 },
9588 /* VEX_LEN_0F38F2_P_0 */
9590 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9593 /* VEX_LEN_0F38F3_R_1_P_0 */
9595 { "blsrS", { VexGdq
, Edq
}, 0 },
9598 /* VEX_LEN_0F38F3_R_2_P_0 */
9600 { "blsmskS", { VexGdq
, Edq
}, 0 },
9603 /* VEX_LEN_0F38F3_R_3_P_0 */
9605 { "blsiS", { VexGdq
, Edq
}, 0 },
9608 /* VEX_LEN_0F38F5_P_0 */
9610 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9613 /* VEX_LEN_0F38F5_P_1 */
9615 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9618 /* VEX_LEN_0F38F5_P_3 */
9620 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9623 /* VEX_LEN_0F38F6_P_3 */
9625 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9628 /* VEX_LEN_0F38F7_P_0 */
9630 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9633 /* VEX_LEN_0F38F7_P_1 */
9635 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9638 /* VEX_LEN_0F38F7_P_2 */
9640 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9643 /* VEX_LEN_0F38F7_P_3 */
9645 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9648 /* VEX_LEN_0F3A00_P_2 */
9651 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9654 /* VEX_LEN_0F3A01_P_2 */
9657 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9660 /* VEX_LEN_0F3A06_P_2 */
9663 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9666 /* VEX_LEN_0F3A14_P_2 */
9668 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9671 /* VEX_LEN_0F3A15_P_2 */
9673 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9676 /* VEX_LEN_0F3A16_P_2 */
9678 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9681 /* VEX_LEN_0F3A17_P_2 */
9683 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9686 /* VEX_LEN_0F3A18_P_2 */
9689 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9692 /* VEX_LEN_0F3A19_P_2 */
9695 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9698 /* VEX_LEN_0F3A20_P_2 */
9700 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9703 /* VEX_LEN_0F3A21_P_2 */
9705 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9708 /* VEX_LEN_0F3A22_P_2 */
9710 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9713 /* VEX_LEN_0F3A30_P_2 */
9715 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9718 /* VEX_LEN_0F3A31_P_2 */
9720 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9723 /* VEX_LEN_0F3A32_P_2 */
9725 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9728 /* VEX_LEN_0F3A33_P_2 */
9730 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9733 /* VEX_LEN_0F3A38_P_2 */
9736 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9739 /* VEX_LEN_0F3A39_P_2 */
9742 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9745 /* VEX_LEN_0F3A41_P_2 */
9747 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9750 /* VEX_LEN_0F3A46_P_2 */
9753 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9756 /* VEX_LEN_0F3A60_P_2 */
9758 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9761 /* VEX_LEN_0F3A61_P_2 */
9763 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9766 /* VEX_LEN_0F3A62_P_2 */
9768 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9771 /* VEX_LEN_0F3A63_P_2 */
9773 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9776 /* VEX_LEN_0F3A6A_P_2 */
9778 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9781 /* VEX_LEN_0F3A6B_P_2 */
9783 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9786 /* VEX_LEN_0F3A6E_P_2 */
9788 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9791 /* VEX_LEN_0F3A6F_P_2 */
9793 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9796 /* VEX_LEN_0F3A7A_P_2 */
9798 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9801 /* VEX_LEN_0F3A7B_P_2 */
9803 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9806 /* VEX_LEN_0F3A7E_P_2 */
9808 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9811 /* VEX_LEN_0F3A7F_P_2 */
9813 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9816 /* VEX_LEN_0F3ADF_P_2 */
9818 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9821 /* VEX_LEN_0F3AF0_P_3 */
9823 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9826 /* VEX_LEN_0FXOP_08_CC */
9828 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9831 /* VEX_LEN_0FXOP_08_CD */
9833 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9836 /* VEX_LEN_0FXOP_08_CE */
9838 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9841 /* VEX_LEN_0FXOP_08_CF */
9843 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9846 /* VEX_LEN_0FXOP_08_EC */
9848 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9851 /* VEX_LEN_0FXOP_08_ED */
9853 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9856 /* VEX_LEN_0FXOP_08_EE */
9858 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9861 /* VEX_LEN_0FXOP_08_EF */
9863 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9866 /* VEX_LEN_0FXOP_09_80 */
9868 { "vfrczps", { XM
, EXxmm
}, 0 },
9869 { "vfrczps", { XM
, EXymmq
}, 0 },
9872 /* VEX_LEN_0FXOP_09_81 */
9874 { "vfrczpd", { XM
, EXxmm
}, 0 },
9875 { "vfrczpd", { XM
, EXymmq
}, 0 },
9879 #include "i386-dis-evex-len.h"
9881 static const struct dis386 vex_w_table
[][2] = {
9883 /* VEX_W_0F41_P_0_LEN_1 */
9884 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9885 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9888 /* VEX_W_0F41_P_2_LEN_1 */
9889 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9890 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9893 /* VEX_W_0F42_P_0_LEN_1 */
9894 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9895 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9898 /* VEX_W_0F42_P_2_LEN_1 */
9899 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9900 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9903 /* VEX_W_0F44_P_0_LEN_0 */
9904 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9905 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9908 /* VEX_W_0F44_P_2_LEN_0 */
9909 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9910 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9913 /* VEX_W_0F45_P_0_LEN_1 */
9914 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9915 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9918 /* VEX_W_0F45_P_2_LEN_1 */
9919 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9920 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9923 /* VEX_W_0F46_P_0_LEN_1 */
9924 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9925 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9928 /* VEX_W_0F46_P_2_LEN_1 */
9929 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9930 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9933 /* VEX_W_0F47_P_0_LEN_1 */
9934 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9935 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9938 /* VEX_W_0F47_P_2_LEN_1 */
9939 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9940 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9943 /* VEX_W_0F4A_P_0_LEN_1 */
9944 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9945 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9948 /* VEX_W_0F4A_P_2_LEN_1 */
9949 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9950 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9953 /* VEX_W_0F4B_P_0_LEN_1 */
9954 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9955 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9958 /* VEX_W_0F4B_P_2_LEN_1 */
9959 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9962 /* VEX_W_0F90_P_0_LEN_0 */
9963 { "kmovw", { MaskG
, MaskE
}, 0 },
9964 { "kmovq", { MaskG
, MaskE
}, 0 },
9967 /* VEX_W_0F90_P_2_LEN_0 */
9968 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9969 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9972 /* VEX_W_0F91_P_0_LEN_0 */
9973 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9974 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9977 /* VEX_W_0F91_P_2_LEN_0 */
9978 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
9979 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
9982 /* VEX_W_0F92_P_0_LEN_0 */
9983 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
9986 /* VEX_W_0F92_P_2_LEN_0 */
9987 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
9990 /* VEX_W_0F93_P_0_LEN_0 */
9991 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
9994 /* VEX_W_0F93_P_2_LEN_0 */
9995 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
9998 /* VEX_W_0F98_P_0_LEN_0 */
9999 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10000 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10003 /* VEX_W_0F98_P_2_LEN_0 */
10004 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10005 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10008 /* VEX_W_0F99_P_0_LEN_0 */
10009 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10010 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10013 /* VEX_W_0F99_P_2_LEN_0 */
10014 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10015 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10018 /* VEX_W_0F380C_P_2 */
10019 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10022 /* VEX_W_0F380D_P_2 */
10023 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10026 /* VEX_W_0F380E_P_2 */
10027 { "vtestps", { XM
, EXx
}, 0 },
10030 /* VEX_W_0F380F_P_2 */
10031 { "vtestpd", { XM
, EXx
}, 0 },
10034 /* VEX_W_0F3816_P_2 */
10035 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10038 /* VEX_W_0F3818_P_2 */
10039 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10042 /* VEX_W_0F3819_P_2 */
10043 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10046 /* VEX_W_0F381A_P_2_M_0 */
10047 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10050 /* VEX_W_0F382C_P_2_M_0 */
10051 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10054 /* VEX_W_0F382D_P_2_M_0 */
10055 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10058 /* VEX_W_0F382E_P_2_M_0 */
10059 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10062 /* VEX_W_0F382F_P_2_M_0 */
10063 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10066 /* VEX_W_0F3836_P_2 */
10067 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10070 /* VEX_W_0F3846_P_2 */
10071 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10074 /* VEX_W_0F3858_P_2 */
10075 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10078 /* VEX_W_0F3859_P_2 */
10079 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10082 /* VEX_W_0F385A_P_2_M_0 */
10083 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10086 /* VEX_W_0F3878_P_2 */
10087 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10090 /* VEX_W_0F3879_P_2 */
10091 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10094 /* VEX_W_0F38CF_P_2 */
10095 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10098 /* VEX_W_0F3A00_P_2 */
10100 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10103 /* VEX_W_0F3A01_P_2 */
10105 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10108 /* VEX_W_0F3A02_P_2 */
10109 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10112 /* VEX_W_0F3A04_P_2 */
10113 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10116 /* VEX_W_0F3A05_P_2 */
10117 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10120 /* VEX_W_0F3A06_P_2 */
10121 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10124 /* VEX_W_0F3A18_P_2 */
10125 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10128 /* VEX_W_0F3A19_P_2 */
10129 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10132 /* VEX_W_0F3A30_P_2_LEN_0 */
10133 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10134 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10137 /* VEX_W_0F3A31_P_2_LEN_0 */
10138 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10139 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10142 /* VEX_W_0F3A32_P_2_LEN_0 */
10143 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10144 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10147 /* VEX_W_0F3A33_P_2_LEN_0 */
10148 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10149 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10152 /* VEX_W_0F3A38_P_2 */
10153 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10156 /* VEX_W_0F3A39_P_2 */
10157 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10160 /* VEX_W_0F3A46_P_2 */
10161 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10164 /* VEX_W_0F3A48_P_2 */
10165 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10166 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10169 /* VEX_W_0F3A49_P_2 */
10170 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10171 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10174 /* VEX_W_0F3A4A_P_2 */
10175 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10178 /* VEX_W_0F3A4B_P_2 */
10179 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10182 /* VEX_W_0F3A4C_P_2 */
10183 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10186 /* VEX_W_0F3ACE_P_2 */
10188 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10191 /* VEX_W_0F3ACF_P_2 */
10193 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10196 #include "i386-dis-evex-w.h"
10199 static const struct dis386 mod_table
[][2] = {
10202 { "leaS", { Gv
, M
}, 0 },
10207 { RM_TABLE (RM_C6_REG_7
) },
10212 { RM_TABLE (RM_C7_REG_7
) },
10216 { "Jcall^", { indirEp
}, 0 },
10220 { "Jjmp^", { indirEp
}, 0 },
10223 /* MOD_0F01_REG_0 */
10224 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10225 { RM_TABLE (RM_0F01_REG_0
) },
10228 /* MOD_0F01_REG_1 */
10229 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10230 { RM_TABLE (RM_0F01_REG_1
) },
10233 /* MOD_0F01_REG_2 */
10234 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10235 { RM_TABLE (RM_0F01_REG_2
) },
10238 /* MOD_0F01_REG_3 */
10239 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10240 { RM_TABLE (RM_0F01_REG_3
) },
10243 /* MOD_0F01_REG_5 */
10244 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
10245 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
10248 /* MOD_0F01_REG_7 */
10249 { "invlpg", { Mb
}, 0 },
10250 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
10253 /* MOD_0F12_PREFIX_0 */
10254 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
10255 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
10259 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10262 /* MOD_0F16_PREFIX_0 */
10263 { "movhps", { XM
, EXq
}, 0 },
10264 { "movlhps", { XM
, EXq
}, 0 },
10268 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10271 /* MOD_0F18_REG_0 */
10272 { "prefetchnta", { Mb
}, 0 },
10275 /* MOD_0F18_REG_1 */
10276 { "prefetcht0", { Mb
}, 0 },
10279 /* MOD_0F18_REG_2 */
10280 { "prefetcht1", { Mb
}, 0 },
10283 /* MOD_0F18_REG_3 */
10284 { "prefetcht2", { Mb
}, 0 },
10287 /* MOD_0F18_REG_4 */
10288 { "nop/reserved", { Mb
}, 0 },
10291 /* MOD_0F18_REG_5 */
10292 { "nop/reserved", { Mb
}, 0 },
10295 /* MOD_0F18_REG_6 */
10296 { "nop/reserved", { Mb
}, 0 },
10299 /* MOD_0F18_REG_7 */
10300 { "nop/reserved", { Mb
}, 0 },
10303 /* MOD_0F1A_PREFIX_0 */
10304 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10305 { "nopQ", { Ev
}, 0 },
10308 /* MOD_0F1B_PREFIX_0 */
10309 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10310 { "nopQ", { Ev
}, 0 },
10313 /* MOD_0F1B_PREFIX_1 */
10314 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10315 { "nopQ", { Ev
}, 0 },
10318 /* MOD_0F1C_PREFIX_0 */
10319 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
10320 { "nopQ", { Ev
}, 0 },
10323 /* MOD_0F1E_PREFIX_1 */
10324 { "nopQ", { Ev
}, 0 },
10325 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
10330 { "movL", { Rd
, Td
}, 0 },
10335 { "movL", { Td
, Rd
}, 0 },
10338 /* MOD_0F2B_PREFIX_0 */
10339 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10342 /* MOD_0F2B_PREFIX_1 */
10343 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10346 /* MOD_0F2B_PREFIX_2 */
10347 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10350 /* MOD_0F2B_PREFIX_3 */
10351 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10356 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10359 /* MOD_0F71_REG_2 */
10361 { "psrlw", { MS
, Ib
}, 0 },
10364 /* MOD_0F71_REG_4 */
10366 { "psraw", { MS
, Ib
}, 0 },
10369 /* MOD_0F71_REG_6 */
10371 { "psllw", { MS
, Ib
}, 0 },
10374 /* MOD_0F72_REG_2 */
10376 { "psrld", { MS
, Ib
}, 0 },
10379 /* MOD_0F72_REG_4 */
10381 { "psrad", { MS
, Ib
}, 0 },
10384 /* MOD_0F72_REG_6 */
10386 { "pslld", { MS
, Ib
}, 0 },
10389 /* MOD_0F73_REG_2 */
10391 { "psrlq", { MS
, Ib
}, 0 },
10394 /* MOD_0F73_REG_3 */
10396 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10399 /* MOD_0F73_REG_6 */
10401 { "psllq", { MS
, Ib
}, 0 },
10404 /* MOD_0F73_REG_7 */
10406 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10409 /* MOD_0FAE_REG_0 */
10410 { "fxsave", { FXSAVE
}, 0 },
10411 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
10414 /* MOD_0FAE_REG_1 */
10415 { "fxrstor", { FXSAVE
}, 0 },
10416 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
10419 /* MOD_0FAE_REG_2 */
10420 { "ldmxcsr", { Md
}, 0 },
10421 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
10424 /* MOD_0FAE_REG_3 */
10425 { "stmxcsr", { Md
}, 0 },
10426 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
10429 /* MOD_0FAE_REG_4 */
10430 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
10431 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
10434 /* MOD_0FAE_REG_5 */
10435 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0
) },
10436 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
10439 /* MOD_0FAE_REG_6 */
10440 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
10441 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
10444 /* MOD_0FAE_REG_7 */
10445 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
10446 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
10450 { "lssS", { Gv
, Mp
}, 0 },
10454 { "lfsS", { Gv
, Mp
}, 0 },
10458 { "lgsS", { Gv
, Mp
}, 0 },
10462 { PREFIX_TABLE (PREFIX_0FC3_MOD_0
) },
10465 /* MOD_0FC7_REG_3 */
10466 { "xrstors", { FXSAVE
}, 0 },
10469 /* MOD_0FC7_REG_4 */
10470 { "xsavec", { FXSAVE
}, 0 },
10473 /* MOD_0FC7_REG_5 */
10474 { "xsaves", { FXSAVE
}, 0 },
10477 /* MOD_0FC7_REG_6 */
10478 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
10479 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
10482 /* MOD_0FC7_REG_7 */
10483 { "vmptrst", { Mq
}, 0 },
10484 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
10489 { "pmovmskb", { Gdq
, MS
}, 0 },
10492 /* MOD_0FE7_PREFIX_2 */
10493 { "movntdq", { Mx
, XM
}, 0 },
10496 /* MOD_0FF0_PREFIX_3 */
10497 { "lddqu", { XM
, M
}, 0 },
10500 /* MOD_0F382A_PREFIX_2 */
10501 { "movntdqa", { XM
, Mx
}, 0 },
10504 /* MOD_0F38F5_PREFIX_2 */
10505 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10508 /* MOD_0F38F6_PREFIX_0 */
10509 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10512 /* MOD_0F38F8_PREFIX_1 */
10513 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
10516 /* MOD_0F38F8_PREFIX_2 */
10517 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10520 /* MOD_0F38F8_PREFIX_3 */
10521 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
10524 /* MOD_0F38F9_PREFIX_0 */
10525 { "movdiri", { Em
, Gv
}, PREFIX_OPCODE
},
10529 { "bound{S|}", { Gv
, Ma
}, 0 },
10530 { EVEX_TABLE (EVEX_0F
) },
10534 { "lesS", { Gv
, Mp
}, 0 },
10535 { VEX_C4_TABLE (VEX_0F
) },
10539 { "ldsS", { Gv
, Mp
}, 0 },
10540 { VEX_C5_TABLE (VEX_0F
) },
10543 /* MOD_VEX_0F12_PREFIX_0 */
10544 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10545 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10549 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10552 /* MOD_VEX_0F16_PREFIX_0 */
10553 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10554 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10558 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10562 { "vmovntpX", { Mx
, XM
}, 0 },
10565 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10567 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10570 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10572 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10575 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10577 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10580 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10582 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10585 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10587 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10590 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10592 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10595 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10597 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10600 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10602 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10605 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10607 { "knotw", { MaskG
, MaskR
}, 0 },
10610 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10612 { "knotq", { MaskG
, MaskR
}, 0 },
10615 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10617 { "knotb", { MaskG
, MaskR
}, 0 },
10620 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10622 { "knotd", { MaskG
, MaskR
}, 0 },
10625 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10627 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10630 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10632 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10635 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10637 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10640 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10642 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10645 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10647 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10650 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10652 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10655 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10657 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10660 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10662 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10665 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10667 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10670 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10672 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10675 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10677 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10680 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10682 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10685 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10687 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10690 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10692 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10695 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10697 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10700 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10702 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10705 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10707 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10710 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10712 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10715 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10717 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10722 { "vmovmskpX", { Gdq
, XS
}, 0 },
10725 /* MOD_VEX_0F71_REG_2 */
10727 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10730 /* MOD_VEX_0F71_REG_4 */
10732 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10735 /* MOD_VEX_0F71_REG_6 */
10737 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10740 /* MOD_VEX_0F72_REG_2 */
10742 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10745 /* MOD_VEX_0F72_REG_4 */
10747 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10750 /* MOD_VEX_0F72_REG_6 */
10752 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10755 /* MOD_VEX_0F73_REG_2 */
10757 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10760 /* MOD_VEX_0F73_REG_3 */
10762 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10765 /* MOD_VEX_0F73_REG_6 */
10767 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10770 /* MOD_VEX_0F73_REG_7 */
10772 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10775 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10776 { "kmovw", { Ew
, MaskG
}, 0 },
10780 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10781 { "kmovq", { Eq
, MaskG
}, 0 },
10785 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10786 { "kmovb", { Eb
, MaskG
}, 0 },
10790 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10791 { "kmovd", { Ed
, MaskG
}, 0 },
10795 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10797 { "kmovw", { MaskG
, Rdq
}, 0 },
10800 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10802 { "kmovb", { MaskG
, Rdq
}, 0 },
10805 /* MOD_VEX_0F92_P_3_LEN_0 */
10807 { "kmovK", { MaskG
, Rdq
}, 0 },
10810 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10812 { "kmovw", { Gdq
, MaskR
}, 0 },
10815 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10817 { "kmovb", { Gdq
, MaskR
}, 0 },
10820 /* MOD_VEX_0F93_P_3_LEN_0 */
10822 { "kmovK", { Gdq
, MaskR
}, 0 },
10825 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10827 { "kortestw", { MaskG
, MaskR
}, 0 },
10830 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10832 { "kortestq", { MaskG
, MaskR
}, 0 },
10835 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10837 { "kortestb", { MaskG
, MaskR
}, 0 },
10840 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10842 { "kortestd", { MaskG
, MaskR
}, 0 },
10845 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10847 { "ktestw", { MaskG
, MaskR
}, 0 },
10850 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10852 { "ktestq", { MaskG
, MaskR
}, 0 },
10855 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10857 { "ktestb", { MaskG
, MaskR
}, 0 },
10860 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10862 { "ktestd", { MaskG
, MaskR
}, 0 },
10865 /* MOD_VEX_0FAE_REG_2 */
10866 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10869 /* MOD_VEX_0FAE_REG_3 */
10870 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10873 /* MOD_VEX_0FD7_PREFIX_2 */
10875 { "vpmovmskb", { Gdq
, XS
}, 0 },
10878 /* MOD_VEX_0FE7_PREFIX_2 */
10879 { "vmovntdq", { Mx
, XM
}, 0 },
10882 /* MOD_VEX_0FF0_PREFIX_3 */
10883 { "vlddqu", { XM
, M
}, 0 },
10886 /* MOD_VEX_0F381A_PREFIX_2 */
10887 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10890 /* MOD_VEX_0F382A_PREFIX_2 */
10891 { "vmovntdqa", { XM
, Mx
}, 0 },
10894 /* MOD_VEX_0F382C_PREFIX_2 */
10895 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10898 /* MOD_VEX_0F382D_PREFIX_2 */
10899 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10902 /* MOD_VEX_0F382E_PREFIX_2 */
10903 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10906 /* MOD_VEX_0F382F_PREFIX_2 */
10907 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10910 /* MOD_VEX_0F385A_PREFIX_2 */
10911 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10914 /* MOD_VEX_0F388C_PREFIX_2 */
10915 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10918 /* MOD_VEX_0F388E_PREFIX_2 */
10919 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10922 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10924 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10927 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10929 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10932 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10934 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10937 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10939 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10942 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10944 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10947 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10949 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10952 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10954 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10957 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10959 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10962 #include "i386-dis-evex-mod.h"
10965 static const struct dis386 rm_table
[][8] = {
10968 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10972 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
10975 /* RM_0F01_REG_0 */
10976 { "enclv", { Skip_MODRM
}, 0 },
10977 { "vmcall", { Skip_MODRM
}, 0 },
10978 { "vmlaunch", { Skip_MODRM
}, 0 },
10979 { "vmresume", { Skip_MODRM
}, 0 },
10980 { "vmxoff", { Skip_MODRM
}, 0 },
10981 { "pconfig", { Skip_MODRM
}, 0 },
10984 /* RM_0F01_REG_1 */
10985 { "monitor", { { OP_Monitor
, 0 } }, 0 },
10986 { "mwait", { { OP_Mwait
, 0 } }, 0 },
10987 { "clac", { Skip_MODRM
}, 0 },
10988 { "stac", { Skip_MODRM
}, 0 },
10992 { "encls", { Skip_MODRM
}, 0 },
10995 /* RM_0F01_REG_2 */
10996 { "xgetbv", { Skip_MODRM
}, 0 },
10997 { "xsetbv", { Skip_MODRM
}, 0 },
11000 { "vmfunc", { Skip_MODRM
}, 0 },
11001 { "xend", { Skip_MODRM
}, 0 },
11002 { "xtest", { Skip_MODRM
}, 0 },
11003 { "enclu", { Skip_MODRM
}, 0 },
11006 /* RM_0F01_REG_3 */
11007 { "vmrun", { Skip_MODRM
}, 0 },
11008 { "vmmcall", { Skip_MODRM
}, 0 },
11009 { "vmload", { Skip_MODRM
}, 0 },
11010 { "vmsave", { Skip_MODRM
}, 0 },
11011 { "stgi", { Skip_MODRM
}, 0 },
11012 { "clgi", { Skip_MODRM
}, 0 },
11013 { "skinit", { Skip_MODRM
}, 0 },
11014 { "invlpga", { Skip_MODRM
}, 0 },
11017 /* RM_0F01_REG_5_MOD_3 */
11018 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
11020 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
11024 { "rdpkru", { Skip_MODRM
}, 0 },
11025 { "wrpkru", { Skip_MODRM
}, 0 },
11028 /* RM_0F01_REG_7_MOD_3 */
11029 { "swapgs", { Skip_MODRM
}, 0 },
11030 { "rdtscp", { Skip_MODRM
}, 0 },
11031 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
11032 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3
) },
11033 { "clzero", { Skip_MODRM
}, 0 },
11036 /* RM_0F1E_P_1_MOD_3_REG_7 */
11037 { "nopQ", { Ev
}, 0 },
11038 { "nopQ", { Ev
}, 0 },
11039 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11040 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11041 { "nopQ", { Ev
}, 0 },
11042 { "nopQ", { Ev
}, 0 },
11043 { "nopQ", { Ev
}, 0 },
11044 { "nopQ", { Ev
}, 0 },
11047 /* RM_0FAE_REG_6_MOD_3 */
11048 { "mfence", { Skip_MODRM
}, 0 },
11051 /* RM_0FAE_REG_7_MOD_3 */
11052 { "sfence", { Skip_MODRM
}, 0 },
11057 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11059 /* We use the high bit to indicate different name for the same
11061 #define REP_PREFIX (0xf3 | 0x100)
11062 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11063 #define XRELEASE_PREFIX (0xf3 | 0x400)
11064 #define BND_PREFIX (0xf2 | 0x400)
11065 #define NOTRACK_PREFIX (0x3e | 0x100)
11070 int newrex
, i
, length
;
11076 last_lock_prefix
= -1;
11077 last_repz_prefix
= -1;
11078 last_repnz_prefix
= -1;
11079 last_data_prefix
= -1;
11080 last_addr_prefix
= -1;
11081 last_rex_prefix
= -1;
11082 last_seg_prefix
= -1;
11084 active_seg_prefix
= 0;
11085 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11086 all_prefixes
[i
] = 0;
11089 /* The maximum instruction length is 15bytes. */
11090 while (length
< MAX_CODE_LENGTH
- 1)
11092 FETCH_DATA (the_info
, codep
+ 1);
11096 /* REX prefixes family. */
11113 if (address_mode
== mode_64bit
)
11117 last_rex_prefix
= i
;
11120 prefixes
|= PREFIX_REPZ
;
11121 last_repz_prefix
= i
;
11124 prefixes
|= PREFIX_REPNZ
;
11125 last_repnz_prefix
= i
;
11128 prefixes
|= PREFIX_LOCK
;
11129 last_lock_prefix
= i
;
11132 prefixes
|= PREFIX_CS
;
11133 last_seg_prefix
= i
;
11134 active_seg_prefix
= PREFIX_CS
;
11137 prefixes
|= PREFIX_SS
;
11138 last_seg_prefix
= i
;
11139 active_seg_prefix
= PREFIX_SS
;
11142 prefixes
|= PREFIX_DS
;
11143 last_seg_prefix
= i
;
11144 active_seg_prefix
= PREFIX_DS
;
11147 prefixes
|= PREFIX_ES
;
11148 last_seg_prefix
= i
;
11149 active_seg_prefix
= PREFIX_ES
;
11152 prefixes
|= PREFIX_FS
;
11153 last_seg_prefix
= i
;
11154 active_seg_prefix
= PREFIX_FS
;
11157 prefixes
|= PREFIX_GS
;
11158 last_seg_prefix
= i
;
11159 active_seg_prefix
= PREFIX_GS
;
11162 prefixes
|= PREFIX_DATA
;
11163 last_data_prefix
= i
;
11166 prefixes
|= PREFIX_ADDR
;
11167 last_addr_prefix
= i
;
11170 /* fwait is really an instruction. If there are prefixes
11171 before the fwait, they belong to the fwait, *not* to the
11172 following instruction. */
11174 if (prefixes
|| rex
)
11176 prefixes
|= PREFIX_FWAIT
;
11178 /* This ensures that the previous REX prefixes are noticed
11179 as unused prefixes, as in the return case below. */
11183 prefixes
= PREFIX_FWAIT
;
11188 /* Rex is ignored when followed by another prefix. */
11194 if (*codep
!= FWAIT_OPCODE
)
11195 all_prefixes
[i
++] = *codep
;
11203 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11206 static const char *
11207 prefix_name (int pref
, int sizeflag
)
11209 static const char *rexes
[16] =
11212 "rex.B", /* 0x41 */
11213 "rex.X", /* 0x42 */
11214 "rex.XB", /* 0x43 */
11215 "rex.R", /* 0x44 */
11216 "rex.RB", /* 0x45 */
11217 "rex.RX", /* 0x46 */
11218 "rex.RXB", /* 0x47 */
11219 "rex.W", /* 0x48 */
11220 "rex.WB", /* 0x49 */
11221 "rex.WX", /* 0x4a */
11222 "rex.WXB", /* 0x4b */
11223 "rex.WR", /* 0x4c */
11224 "rex.WRB", /* 0x4d */
11225 "rex.WRX", /* 0x4e */
11226 "rex.WRXB", /* 0x4f */
11231 /* REX prefixes family. */
11248 return rexes
[pref
- 0x40];
11268 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11270 if (address_mode
== mode_64bit
)
11271 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11273 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11278 case XACQUIRE_PREFIX
:
11280 case XRELEASE_PREFIX
:
11284 case NOTRACK_PREFIX
:
11291 static char op_out
[MAX_OPERANDS
][100];
11292 static int op_ad
, op_index
[MAX_OPERANDS
];
11293 static int two_source_ops
;
11294 static bfd_vma op_address
[MAX_OPERANDS
];
11295 static bfd_vma op_riprel
[MAX_OPERANDS
];
11296 static bfd_vma start_pc
;
11299 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11300 * (see topic "Redundant prefixes" in the "Differences from 8086"
11301 * section of the "Virtual 8086 Mode" chapter.)
11302 * 'pc' should be the address of this instruction, it will
11303 * be used to print the target address if this is a relative jump or call
11304 * The function returns the length of this instruction in bytes.
11307 static char intel_syntax
;
11308 static char intel_mnemonic
= !SYSV386_COMPAT
;
11309 static char open_char
;
11310 static char close_char
;
11311 static char separator_char
;
11312 static char scale_char
;
11320 static enum x86_64_isa isa64
;
11322 /* Here for backwards compatibility. When gdb stops using
11323 print_insn_i386_att and print_insn_i386_intel these functions can
11324 disappear, and print_insn_i386 be merged into print_insn. */
11326 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11330 return print_insn (pc
, info
);
11334 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11338 return print_insn (pc
, info
);
11342 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11346 return print_insn (pc
, info
);
11350 print_i386_disassembler_options (FILE *stream
)
11352 fprintf (stream
, _("\n\
11353 The following i386/x86-64 specific disassembler options are supported for use\n\
11354 with the -M switch (multiple options should be separated by commas):\n"));
11356 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11357 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11358 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11359 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11360 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11361 fprintf (stream
, _(" att-mnemonic\n"
11362 " Display instruction in AT&T mnemonic\n"));
11363 fprintf (stream
, _(" intel-mnemonic\n"
11364 " Display instruction in Intel mnemonic\n"));
11365 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11366 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11367 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11368 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11369 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11370 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11371 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11372 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11376 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11378 /* Get a pointer to struct dis386 with a valid name. */
11380 static const struct dis386
*
11381 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11383 int vindex
, vex_table_index
;
11385 if (dp
->name
!= NULL
)
11388 switch (dp
->op
[0].bytemode
)
11390 case USE_REG_TABLE
:
11391 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11394 case USE_MOD_TABLE
:
11395 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11396 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11400 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11403 case USE_PREFIX_TABLE
:
11406 /* The prefix in VEX is implicit. */
11407 switch (vex
.prefix
)
11412 case REPE_PREFIX_OPCODE
:
11415 case DATA_PREFIX_OPCODE
:
11418 case REPNE_PREFIX_OPCODE
:
11428 int last_prefix
= -1;
11431 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11432 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11434 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11436 if (last_repz_prefix
> last_repnz_prefix
)
11439 prefix
= PREFIX_REPZ
;
11440 last_prefix
= last_repz_prefix
;
11445 prefix
= PREFIX_REPNZ
;
11446 last_prefix
= last_repnz_prefix
;
11449 /* Check if prefix should be ignored. */
11450 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11451 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11456 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11459 prefix
= PREFIX_DATA
;
11460 last_prefix
= last_data_prefix
;
11465 used_prefixes
|= prefix
;
11466 all_prefixes
[last_prefix
] = 0;
11469 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11472 case USE_X86_64_TABLE
:
11473 vindex
= address_mode
== mode_64bit
? 1 : 0;
11474 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11477 case USE_3BYTE_TABLE
:
11478 FETCH_DATA (info
, codep
+ 2);
11480 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11482 modrm
.mod
= (*codep
>> 6) & 3;
11483 modrm
.reg
= (*codep
>> 3) & 7;
11484 modrm
.rm
= *codep
& 7;
11487 case USE_VEX_LEN_TABLE
:
11491 switch (vex
.length
)
11504 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11507 case USE_EVEX_LEN_TABLE
:
11511 switch (vex
.length
)
11527 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11530 case USE_XOP_8F_TABLE
:
11531 FETCH_DATA (info
, codep
+ 3);
11532 /* All bits in the REX prefix are ignored. */
11534 rex
= ~(*codep
>> 5) & 0x7;
11536 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11537 switch ((*codep
& 0x1f))
11543 vex_table_index
= XOP_08
;
11546 vex_table_index
= XOP_09
;
11549 vex_table_index
= XOP_0A
;
11553 vex
.w
= *codep
& 0x80;
11554 if (vex
.w
&& address_mode
== mode_64bit
)
11557 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11558 if (address_mode
!= mode_64bit
)
11560 /* In 16/32-bit mode REX_B is silently ignored. */
11564 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11565 switch ((*codep
& 0x3))
11570 vex
.prefix
= DATA_PREFIX_OPCODE
;
11573 vex
.prefix
= REPE_PREFIX_OPCODE
;
11576 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11583 dp
= &xop_table
[vex_table_index
][vindex
];
11586 FETCH_DATA (info
, codep
+ 1);
11587 modrm
.mod
= (*codep
>> 6) & 3;
11588 modrm
.reg
= (*codep
>> 3) & 7;
11589 modrm
.rm
= *codep
& 7;
11592 case USE_VEX_C4_TABLE
:
11594 FETCH_DATA (info
, codep
+ 3);
11595 /* All bits in the REX prefix are ignored. */
11597 rex
= ~(*codep
>> 5) & 0x7;
11598 switch ((*codep
& 0x1f))
11604 vex_table_index
= VEX_0F
;
11607 vex_table_index
= VEX_0F38
;
11610 vex_table_index
= VEX_0F3A
;
11614 vex
.w
= *codep
& 0x80;
11615 if (address_mode
== mode_64bit
)
11622 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11623 is ignored, other REX bits are 0 and the highest bit in
11624 VEX.vvvv is also ignored (but we mustn't clear it here). */
11627 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11628 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11629 switch ((*codep
& 0x3))
11634 vex
.prefix
= DATA_PREFIX_OPCODE
;
11637 vex
.prefix
= REPE_PREFIX_OPCODE
;
11640 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11647 dp
= &vex_table
[vex_table_index
][vindex
];
11649 /* There is no MODRM byte for VEX0F 77. */
11650 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11652 FETCH_DATA (info
, codep
+ 1);
11653 modrm
.mod
= (*codep
>> 6) & 3;
11654 modrm
.reg
= (*codep
>> 3) & 7;
11655 modrm
.rm
= *codep
& 7;
11659 case USE_VEX_C5_TABLE
:
11661 FETCH_DATA (info
, codep
+ 2);
11662 /* All bits in the REX prefix are ignored. */
11664 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11666 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11668 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11669 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11670 switch ((*codep
& 0x3))
11675 vex
.prefix
= DATA_PREFIX_OPCODE
;
11678 vex
.prefix
= REPE_PREFIX_OPCODE
;
11681 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11688 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11690 /* There is no MODRM byte for VEX 77. */
11691 if (vindex
!= 0x77)
11693 FETCH_DATA (info
, codep
+ 1);
11694 modrm
.mod
= (*codep
>> 6) & 3;
11695 modrm
.reg
= (*codep
>> 3) & 7;
11696 modrm
.rm
= *codep
& 7;
11700 case USE_VEX_W_TABLE
:
11704 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11707 case USE_EVEX_TABLE
:
11708 two_source_ops
= 0;
11711 FETCH_DATA (info
, codep
+ 4);
11712 /* All bits in the REX prefix are ignored. */
11714 /* The first byte after 0x62. */
11715 rex
= ~(*codep
>> 5) & 0x7;
11716 vex
.r
= *codep
& 0x10;
11717 switch ((*codep
& 0xf))
11720 return &bad_opcode
;
11722 vex_table_index
= EVEX_0F
;
11725 vex_table_index
= EVEX_0F38
;
11728 vex_table_index
= EVEX_0F3A
;
11732 /* The second byte after 0x62. */
11734 vex
.w
= *codep
& 0x80;
11735 if (vex
.w
&& address_mode
== mode_64bit
)
11738 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11741 if (!(*codep
& 0x4))
11742 return &bad_opcode
;
11744 switch ((*codep
& 0x3))
11749 vex
.prefix
= DATA_PREFIX_OPCODE
;
11752 vex
.prefix
= REPE_PREFIX_OPCODE
;
11755 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11759 /* The third byte after 0x62. */
11762 /* Remember the static rounding bits. */
11763 vex
.ll
= (*codep
>> 5) & 3;
11764 vex
.b
= (*codep
& 0x10) != 0;
11766 vex
.v
= *codep
& 0x8;
11767 vex
.mask_register_specifier
= *codep
& 0x7;
11768 vex
.zeroing
= *codep
& 0x80;
11770 if (address_mode
!= mode_64bit
)
11772 /* In 16/32-bit mode silently ignore following bits. */
11782 dp
= &evex_table
[vex_table_index
][vindex
];
11784 FETCH_DATA (info
, codep
+ 1);
11785 modrm
.mod
= (*codep
>> 6) & 3;
11786 modrm
.reg
= (*codep
>> 3) & 7;
11787 modrm
.rm
= *codep
& 7;
11789 /* Set vector length. */
11790 if (modrm
.mod
== 3 && vex
.b
)
11806 return &bad_opcode
;
11819 if (dp
->name
!= NULL
)
11822 return get_valid_dis386 (dp
, info
);
11826 get_sib (disassemble_info
*info
, int sizeflag
)
11828 /* If modrm.mod == 3, operand must be register. */
11830 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11834 FETCH_DATA (info
, codep
+ 2);
11835 sib
.index
= (codep
[1] >> 3) & 7;
11836 sib
.scale
= (codep
[1] >> 6) & 3;
11837 sib
.base
= codep
[1] & 7;
11842 print_insn (bfd_vma pc
, disassemble_info
*info
)
11844 const struct dis386
*dp
;
11846 char *op_txt
[MAX_OPERANDS
];
11848 int sizeflag
, orig_sizeflag
;
11850 struct dis_private priv
;
11853 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11854 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11855 address_mode
= mode_32bit
;
11856 else if (info
->mach
== bfd_mach_i386_i8086
)
11858 address_mode
= mode_16bit
;
11859 priv
.orig_sizeflag
= 0;
11862 address_mode
= mode_64bit
;
11864 if (intel_syntax
== (char) -1)
11865 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11867 for (p
= info
->disassembler_options
; p
!= NULL
; )
11869 if (CONST_STRNEQ (p
, "amd64"))
11871 else if (CONST_STRNEQ (p
, "intel64"))
11873 else if (CONST_STRNEQ (p
, "x86-64"))
11875 address_mode
= mode_64bit
;
11876 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11878 else if (CONST_STRNEQ (p
, "i386"))
11880 address_mode
= mode_32bit
;
11881 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11883 else if (CONST_STRNEQ (p
, "i8086"))
11885 address_mode
= mode_16bit
;
11886 priv
.orig_sizeflag
= 0;
11888 else if (CONST_STRNEQ (p
, "intel"))
11891 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11892 intel_mnemonic
= 1;
11894 else if (CONST_STRNEQ (p
, "att"))
11897 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11898 intel_mnemonic
= 0;
11900 else if (CONST_STRNEQ (p
, "addr"))
11902 if (address_mode
== mode_64bit
)
11904 if (p
[4] == '3' && p
[5] == '2')
11905 priv
.orig_sizeflag
&= ~AFLAG
;
11906 else if (p
[4] == '6' && p
[5] == '4')
11907 priv
.orig_sizeflag
|= AFLAG
;
11911 if (p
[4] == '1' && p
[5] == '6')
11912 priv
.orig_sizeflag
&= ~AFLAG
;
11913 else if (p
[4] == '3' && p
[5] == '2')
11914 priv
.orig_sizeflag
|= AFLAG
;
11917 else if (CONST_STRNEQ (p
, "data"))
11919 if (p
[4] == '1' && p
[5] == '6')
11920 priv
.orig_sizeflag
&= ~DFLAG
;
11921 else if (p
[4] == '3' && p
[5] == '2')
11922 priv
.orig_sizeflag
|= DFLAG
;
11924 else if (CONST_STRNEQ (p
, "suffix"))
11925 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11927 p
= strchr (p
, ',');
11932 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11934 (*info
->fprintf_func
) (info
->stream
,
11935 _("64-bit address is disabled"));
11941 names64
= intel_names64
;
11942 names32
= intel_names32
;
11943 names16
= intel_names16
;
11944 names8
= intel_names8
;
11945 names8rex
= intel_names8rex
;
11946 names_seg
= intel_names_seg
;
11947 names_mm
= intel_names_mm
;
11948 names_bnd
= intel_names_bnd
;
11949 names_xmm
= intel_names_xmm
;
11950 names_ymm
= intel_names_ymm
;
11951 names_zmm
= intel_names_zmm
;
11952 index64
= intel_index64
;
11953 index32
= intel_index32
;
11954 names_mask
= intel_names_mask
;
11955 index16
= intel_index16
;
11958 separator_char
= '+';
11963 names64
= att_names64
;
11964 names32
= att_names32
;
11965 names16
= att_names16
;
11966 names8
= att_names8
;
11967 names8rex
= att_names8rex
;
11968 names_seg
= att_names_seg
;
11969 names_mm
= att_names_mm
;
11970 names_bnd
= att_names_bnd
;
11971 names_xmm
= att_names_xmm
;
11972 names_ymm
= att_names_ymm
;
11973 names_zmm
= att_names_zmm
;
11974 index64
= att_index64
;
11975 index32
= att_index32
;
11976 names_mask
= att_names_mask
;
11977 index16
= att_index16
;
11980 separator_char
= ',';
11984 /* The output looks better if we put 7 bytes on a line, since that
11985 puts most long word instructions on a single line. Use 8 bytes
11987 if ((info
->mach
& bfd_mach_l1om
) != 0)
11988 info
->bytes_per_line
= 8;
11990 info
->bytes_per_line
= 7;
11992 info
->private_data
= &priv
;
11993 priv
.max_fetched
= priv
.the_buffer
;
11994 priv
.insn_start
= pc
;
11997 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12005 start_codep
= priv
.the_buffer
;
12006 codep
= priv
.the_buffer
;
12008 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12012 /* Getting here means we tried for data but didn't get it. That
12013 means we have an incomplete instruction of some sort. Just
12014 print the first byte as a prefix or a .byte pseudo-op. */
12015 if (codep
> priv
.the_buffer
)
12017 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12019 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12022 /* Just print the first byte as a .byte instruction. */
12023 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12024 (unsigned int) priv
.the_buffer
[0]);
12034 sizeflag
= priv
.orig_sizeflag
;
12036 if (!ckprefix () || rex_used
)
12038 /* Too many prefixes or unused REX prefixes. */
12040 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12042 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12044 prefix_name (all_prefixes
[i
], sizeflag
));
12048 insn_codep
= codep
;
12050 FETCH_DATA (info
, codep
+ 1);
12051 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12053 if (((prefixes
& PREFIX_FWAIT
)
12054 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12056 /* Handle prefixes before fwait. */
12057 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12059 (*info
->fprintf_func
) (info
->stream
, "%s ",
12060 prefix_name (all_prefixes
[i
], sizeflag
));
12061 (*info
->fprintf_func
) (info
->stream
, "fwait");
12065 if (*codep
== 0x0f)
12067 unsigned char threebyte
;
12070 FETCH_DATA (info
, codep
+ 1);
12071 threebyte
= *codep
;
12072 dp
= &dis386_twobyte
[threebyte
];
12073 need_modrm
= twobyte_has_modrm
[*codep
];
12078 dp
= &dis386
[*codep
];
12079 need_modrm
= onebyte_has_modrm
[*codep
];
12083 /* Save sizeflag for printing the extra prefixes later before updating
12084 it for mnemonic and operand processing. The prefix names depend
12085 only on the address mode. */
12086 orig_sizeflag
= sizeflag
;
12087 if (prefixes
& PREFIX_ADDR
)
12089 if ((prefixes
& PREFIX_DATA
))
12095 FETCH_DATA (info
, codep
+ 1);
12096 modrm
.mod
= (*codep
>> 6) & 3;
12097 modrm
.reg
= (*codep
>> 3) & 7;
12098 modrm
.rm
= *codep
& 7;
12104 memset (&vex
, 0, sizeof (vex
));
12106 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12108 get_sib (info
, sizeflag
);
12109 dofloat (sizeflag
);
12113 dp
= get_valid_dis386 (dp
, info
);
12114 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12116 get_sib (info
, sizeflag
);
12117 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12120 op_ad
= MAX_OPERANDS
- 1 - i
;
12122 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12123 /* For EVEX instruction after the last operand masking
12124 should be printed. */
12125 if (i
== 0 && vex
.evex
)
12127 /* Don't print {%k0}. */
12128 if (vex
.mask_register_specifier
)
12131 oappend (names_mask
[vex
.mask_register_specifier
]);
12141 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12142 are all 0s in inverted form. */
12143 if (need_vex
&& vex
.register_specifier
!= 0)
12145 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12146 return end_codep
- priv
.the_buffer
;
12149 /* Check if the REX prefix is used. */
12150 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
12151 all_prefixes
[last_rex_prefix
] = 0;
12153 /* Check if the SEG prefix is used. */
12154 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12155 | PREFIX_FS
| PREFIX_GS
)) != 0
12156 && (used_prefixes
& active_seg_prefix
) != 0)
12157 all_prefixes
[last_seg_prefix
] = 0;
12159 /* Check if the ADDR prefix is used. */
12160 if ((prefixes
& PREFIX_ADDR
) != 0
12161 && (used_prefixes
& PREFIX_ADDR
) != 0)
12162 all_prefixes
[last_addr_prefix
] = 0;
12164 /* Check if the DATA prefix is used. */
12165 if ((prefixes
& PREFIX_DATA
) != 0
12166 && (used_prefixes
& PREFIX_DATA
) != 0)
12167 all_prefixes
[last_data_prefix
] = 0;
12169 /* Print the extra prefixes. */
12171 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12172 if (all_prefixes
[i
])
12175 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12178 prefix_length
+= strlen (name
) + 1;
12179 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12182 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12183 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12184 used by putop and MMX/SSE operand and may be overriden by the
12185 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12187 if (dp
->prefix_requirement
== PREFIX_OPCODE
12188 && dp
!= &bad_opcode
12190 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
12192 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12194 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12196 && (used_prefixes
& PREFIX_DATA
) == 0))))
12198 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12199 return end_codep
- priv
.the_buffer
;
12202 /* Check maximum code length. */
12203 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12205 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12206 return MAX_CODE_LENGTH
;
12209 obufp
= mnemonicendp
;
12210 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12213 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12215 /* The enter and bound instructions are printed with operands in the same
12216 order as the intel book; everything else is printed in reverse order. */
12217 if (intel_syntax
|| two_source_ops
)
12221 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12222 op_txt
[i
] = op_out
[i
];
12224 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12225 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12227 op_txt
[2] = op_out
[3];
12228 op_txt
[3] = op_out
[2];
12231 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12233 op_ad
= op_index
[i
];
12234 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12235 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12236 riprel
= op_riprel
[i
];
12237 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12238 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12243 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12244 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12248 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12252 (*info
->fprintf_func
) (info
->stream
, ",");
12253 if (op_index
[i
] != -1 && !op_riprel
[i
])
12254 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
12256 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12260 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12261 if (op_index
[i
] != -1 && op_riprel
[i
])
12263 (*info
->fprintf_func
) (info
->stream
, " # ");
12264 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12265 + op_address
[op_index
[i
]]), info
);
12268 return codep
- priv
.the_buffer
;
12271 static const char *float_mem
[] = {
12346 static const unsigned char float_mem_mode
[] = {
12421 #define ST { OP_ST, 0 }
12422 #define STi { OP_STi, 0 }
12424 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12425 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12426 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12427 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12428 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12429 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12430 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12431 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12432 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12434 static const struct dis386 float_reg
[][8] = {
12437 { "fadd", { ST
, STi
}, 0 },
12438 { "fmul", { ST
, STi
}, 0 },
12439 { "fcom", { STi
}, 0 },
12440 { "fcomp", { STi
}, 0 },
12441 { "fsub", { ST
, STi
}, 0 },
12442 { "fsubr", { ST
, STi
}, 0 },
12443 { "fdiv", { ST
, STi
}, 0 },
12444 { "fdivr", { ST
, STi
}, 0 },
12448 { "fld", { STi
}, 0 },
12449 { "fxch", { STi
}, 0 },
12459 { "fcmovb", { ST
, STi
}, 0 },
12460 { "fcmove", { ST
, STi
}, 0 },
12461 { "fcmovbe",{ ST
, STi
}, 0 },
12462 { "fcmovu", { ST
, STi
}, 0 },
12470 { "fcmovnb",{ ST
, STi
}, 0 },
12471 { "fcmovne",{ ST
, STi
}, 0 },
12472 { "fcmovnbe",{ ST
, STi
}, 0 },
12473 { "fcmovnu",{ ST
, STi
}, 0 },
12475 { "fucomi", { ST
, STi
}, 0 },
12476 { "fcomi", { ST
, STi
}, 0 },
12481 { "fadd", { STi
, ST
}, 0 },
12482 { "fmul", { STi
, ST
}, 0 },
12485 { "fsub{!M|r}", { STi
, ST
}, 0 },
12486 { "fsub{M|}", { STi
, ST
}, 0 },
12487 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12488 { "fdiv{M|}", { STi
, ST
}, 0 },
12492 { "ffree", { STi
}, 0 },
12494 { "fst", { STi
}, 0 },
12495 { "fstp", { STi
}, 0 },
12496 { "fucom", { STi
}, 0 },
12497 { "fucomp", { STi
}, 0 },
12503 { "faddp", { STi
, ST
}, 0 },
12504 { "fmulp", { STi
, ST
}, 0 },
12507 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12508 { "fsub{M|}p", { STi
, ST
}, 0 },
12509 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12510 { "fdiv{M|}p", { STi
, ST
}, 0 },
12514 { "ffreep", { STi
}, 0 },
12519 { "fucomip", { ST
, STi
}, 0 },
12520 { "fcomip", { ST
, STi
}, 0 },
12525 static char *fgrps
[][8] = {
12528 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12533 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12538 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12543 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12548 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12553 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12558 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12563 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12564 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12569 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12574 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12579 swap_operand (void)
12581 mnemonicendp
[0] = '.';
12582 mnemonicendp
[1] = 's';
12587 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12588 int sizeflag ATTRIBUTE_UNUSED
)
12590 /* Skip mod/rm byte. */
12596 dofloat (int sizeflag
)
12598 const struct dis386
*dp
;
12599 unsigned char floatop
;
12601 floatop
= codep
[-1];
12603 if (modrm
.mod
!= 3)
12605 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12607 putop (float_mem
[fp_indx
], sizeflag
);
12610 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12613 /* Skip mod/rm byte. */
12617 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12618 if (dp
->name
== NULL
)
12620 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12622 /* Instruction fnstsw is only one with strange arg. */
12623 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12624 strcpy (op_out
[0], names16
[0]);
12628 putop (dp
->name
, sizeflag
);
12633 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12638 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12642 /* Like oappend (below), but S is a string starting with '%'.
12643 In Intel syntax, the '%' is elided. */
12645 oappend_maybe_intel (const char *s
)
12647 oappend (s
+ intel_syntax
);
12651 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12653 oappend_maybe_intel ("%st");
12657 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12659 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12660 oappend_maybe_intel (scratchbuf
);
12663 /* Capital letters in template are macros. */
12665 putop (const char *in_template
, int sizeflag
)
12670 unsigned int l
= 0, len
= 1;
12673 #define SAVE_LAST(c) \
12674 if (l < len && l < sizeof (last)) \
12679 for (p
= in_template
; *p
; p
++)
12695 while (*++p
!= '|')
12696 if (*p
== '}' || *p
== '\0')
12699 /* Fall through. */
12704 while (*++p
!= '}')
12715 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12719 if (l
== 0 && len
== 1)
12724 if (sizeflag
& SUFFIX_ALWAYS
)
12737 if (address_mode
== mode_64bit
12738 && !(prefixes
& PREFIX_ADDR
))
12749 if (intel_syntax
&& !alt
)
12751 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12753 if (sizeflag
& DFLAG
)
12754 *obufp
++ = intel_syntax
? 'd' : 'l';
12756 *obufp
++ = intel_syntax
? 'w' : 's';
12757 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12761 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12764 if (modrm
.mod
== 3)
12770 if (sizeflag
& DFLAG
)
12771 *obufp
++ = intel_syntax
? 'd' : 'l';
12774 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12780 case 'E': /* For jcxz/jecxz */
12781 if (address_mode
== mode_64bit
)
12783 if (sizeflag
& AFLAG
)
12789 if (sizeflag
& AFLAG
)
12791 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12796 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12798 if (sizeflag
& AFLAG
)
12799 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12801 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12802 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12806 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12808 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12812 if (!(rex
& REX_W
))
12813 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12818 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12819 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12821 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12824 if (prefixes
& PREFIX_DS
)
12843 if (l
!= 0 || len
!= 1)
12845 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12850 if (!need_vex
|| !vex
.evex
)
12853 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12855 switch (vex
.length
)
12873 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12878 /* Fall through. */
12881 if (l
!= 0 || len
!= 1)
12889 if (sizeflag
& SUFFIX_ALWAYS
)
12893 if (intel_mnemonic
!= cond
)
12897 if ((prefixes
& PREFIX_FWAIT
) == 0)
12900 used_prefixes
|= PREFIX_FWAIT
;
12906 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12910 if (!(rex
& REX_W
))
12911 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12915 && address_mode
== mode_64bit
12916 && isa64
== intel64
)
12921 /* Fall through. */
12924 && address_mode
== mode_64bit
12925 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12930 /* Fall through. */
12933 if (l
== 0 && len
== 1)
12938 if ((rex
& REX_W
) == 0
12939 && (prefixes
& PREFIX_DATA
))
12941 if ((sizeflag
& DFLAG
) == 0)
12943 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12947 if ((prefixes
& PREFIX_DATA
)
12949 || (sizeflag
& SUFFIX_ALWAYS
))
12956 if (sizeflag
& DFLAG
)
12960 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12966 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12972 if ((prefixes
& PREFIX_DATA
)
12974 || (sizeflag
& SUFFIX_ALWAYS
))
12981 if (sizeflag
& DFLAG
)
12982 *obufp
++ = intel_syntax
? 'd' : 'l';
12985 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12993 if (address_mode
== mode_64bit
12994 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12996 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13000 /* Fall through. */
13003 if (l
== 0 && len
== 1)
13006 if (intel_syntax
&& !alt
)
13009 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13015 if (sizeflag
& DFLAG
)
13016 *obufp
++ = intel_syntax
? 'd' : 'l';
13019 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13025 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13031 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13046 else if (sizeflag
& DFLAG
)
13055 if (intel_syntax
&& !p
[1]
13056 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13058 if (!(rex
& REX_W
))
13059 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13062 if (l
== 0 && len
== 1)
13066 if (address_mode
== mode_64bit
13067 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13069 if (sizeflag
& SUFFIX_ALWAYS
)
13091 /* Fall through. */
13094 if (l
== 0 && len
== 1)
13099 if (sizeflag
& SUFFIX_ALWAYS
)
13105 if (sizeflag
& DFLAG
)
13109 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13123 if (address_mode
== mode_64bit
13124 && !(prefixes
& PREFIX_ADDR
))
13135 if (l
!= 0 || len
!= 1)
13140 if (need_vex
&& vex
.prefix
)
13142 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
13149 if (prefixes
& PREFIX_DATA
)
13153 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13157 if (l
== 0 && len
== 1)
13161 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13169 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13171 switch (vex
.length
)
13187 if (l
== 0 && len
== 1)
13189 /* operand size flag for cwtl, cbtw */
13198 else if (sizeflag
& DFLAG
)
13202 if (!(rex
& REX_W
))
13203 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13210 && last
[0] != 'L'))
13217 if (last
[0] == 'X')
13218 *obufp
++ = vex
.w
? 'd': 's';
13220 *obufp
++ = vex
.w
? 'q': 'd';
13226 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13228 if (sizeflag
& DFLAG
)
13232 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13238 if (address_mode
== mode_64bit
13239 && (isa64
== intel64
13240 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13242 else if ((prefixes
& PREFIX_DATA
))
13244 if (!(sizeflag
& DFLAG
))
13246 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13253 mnemonicendp
= obufp
;
13258 oappend (const char *s
)
13260 obufp
= stpcpy (obufp
, s
);
13266 /* Only print the active segment register. */
13267 if (!active_seg_prefix
)
13270 used_prefixes
|= active_seg_prefix
;
13271 switch (active_seg_prefix
)
13274 oappend_maybe_intel ("%cs:");
13277 oappend_maybe_intel ("%ds:");
13280 oappend_maybe_intel ("%ss:");
13283 oappend_maybe_intel ("%es:");
13286 oappend_maybe_intel ("%fs:");
13289 oappend_maybe_intel ("%gs:");
13297 OP_indirE (int bytemode
, int sizeflag
)
13301 OP_E (bytemode
, sizeflag
);
13305 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13307 if (address_mode
== mode_64bit
)
13315 sprintf_vma (tmp
, disp
);
13316 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13317 strcpy (buf
+ 2, tmp
+ i
);
13321 bfd_signed_vma v
= disp
;
13328 /* Check for possible overflow on 0x8000000000000000. */
13331 strcpy (buf
, "9223372036854775808");
13345 tmp
[28 - i
] = (v
% 10) + '0';
13349 strcpy (buf
, tmp
+ 29 - i
);
13355 sprintf (buf
, "0x%x", (unsigned int) disp
);
13357 sprintf (buf
, "%d", (int) disp
);
13361 /* Put DISP in BUF as signed hex number. */
13364 print_displacement (char *buf
, bfd_vma disp
)
13366 bfd_signed_vma val
= disp
;
13375 /* Check for possible overflow. */
13378 switch (address_mode
)
13381 strcpy (buf
+ j
, "0x8000000000000000");
13384 strcpy (buf
+ j
, "0x80000000");
13387 strcpy (buf
+ j
, "0x8000");
13397 sprintf_vma (tmp
, (bfd_vma
) val
);
13398 for (i
= 0; tmp
[i
] == '0'; i
++)
13400 if (tmp
[i
] == '\0')
13402 strcpy (buf
+ j
, tmp
+ i
);
13406 intel_operand_size (int bytemode
, int sizeflag
)
13410 && (bytemode
== x_mode
13411 || bytemode
== evex_half_bcst_xmmq_mode
))
13414 oappend ("QWORD PTR ");
13416 oappend ("DWORD PTR ");
13425 oappend ("BYTE PTR ");
13430 oappend ("WORD PTR ");
13433 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13435 oappend ("QWORD PTR ");
13438 /* Fall through. */
13440 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13442 oappend ("QWORD PTR ");
13445 /* Fall through. */
13451 oappend ("QWORD PTR ");
13454 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13455 oappend ("DWORD PTR ");
13457 oappend ("WORD PTR ");
13458 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13462 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13464 oappend ("WORD PTR ");
13465 if (!(rex
& REX_W
))
13466 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13469 if (sizeflag
& DFLAG
)
13470 oappend ("QWORD PTR ");
13472 oappend ("DWORD PTR ");
13473 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13476 case d_scalar_mode
:
13477 case d_scalar_swap_mode
:
13480 oappend ("DWORD PTR ");
13483 case q_scalar_mode
:
13484 case q_scalar_swap_mode
:
13486 oappend ("QWORD PTR ");
13489 if (address_mode
== mode_64bit
)
13490 oappend ("QWORD PTR ");
13492 oappend ("DWORD PTR ");
13495 if (sizeflag
& DFLAG
)
13496 oappend ("FWORD PTR ");
13498 oappend ("DWORD PTR ");
13499 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13502 oappend ("TBYTE PTR ");
13506 case evex_x_gscat_mode
:
13507 case evex_x_nobcst_mode
:
13508 case b_scalar_mode
:
13509 case w_scalar_mode
:
13512 switch (vex
.length
)
13515 oappend ("XMMWORD PTR ");
13518 oappend ("YMMWORD PTR ");
13521 oappend ("ZMMWORD PTR ");
13528 oappend ("XMMWORD PTR ");
13531 oappend ("XMMWORD PTR ");
13534 oappend ("YMMWORD PTR ");
13537 case evex_half_bcst_xmmq_mode
:
13541 switch (vex
.length
)
13544 oappend ("QWORD PTR ");
13547 oappend ("XMMWORD PTR ");
13550 oappend ("YMMWORD PTR ");
13560 switch (vex
.length
)
13565 oappend ("BYTE PTR ");
13575 switch (vex
.length
)
13580 oappend ("WORD PTR ");
13590 switch (vex
.length
)
13595 oappend ("DWORD PTR ");
13605 switch (vex
.length
)
13610 oappend ("QWORD PTR ");
13620 switch (vex
.length
)
13623 oappend ("WORD PTR ");
13626 oappend ("DWORD PTR ");
13629 oappend ("QWORD PTR ");
13639 switch (vex
.length
)
13642 oappend ("DWORD PTR ");
13645 oappend ("QWORD PTR ");
13648 oappend ("XMMWORD PTR ");
13658 switch (vex
.length
)
13661 oappend ("QWORD PTR ");
13664 oappend ("YMMWORD PTR ");
13667 oappend ("ZMMWORD PTR ");
13677 switch (vex
.length
)
13681 oappend ("XMMWORD PTR ");
13688 oappend ("OWORD PTR ");
13691 case vex_w_dq_mode
:
13692 case vex_scalar_w_dq_mode
:
13697 oappend ("QWORD PTR ");
13699 oappend ("DWORD PTR ");
13701 case vex_vsib_d_w_dq_mode
:
13702 case vex_vsib_q_w_dq_mode
:
13709 oappend ("QWORD PTR ");
13711 oappend ("DWORD PTR ");
13715 switch (vex
.length
)
13718 oappend ("XMMWORD PTR ");
13721 oappend ("YMMWORD PTR ");
13724 oappend ("ZMMWORD PTR ");
13731 case vex_vsib_q_w_d_mode
:
13732 case vex_vsib_d_w_d_mode
:
13733 if (!need_vex
|| !vex
.evex
)
13736 switch (vex
.length
)
13739 oappend ("QWORD PTR ");
13742 oappend ("XMMWORD PTR ");
13745 oappend ("YMMWORD PTR ");
13753 if (!need_vex
|| vex
.length
!= 128)
13756 oappend ("DWORD PTR ");
13758 oappend ("BYTE PTR ");
13764 oappend ("QWORD PTR ");
13766 oappend ("WORD PTR ");
13776 OP_E_register (int bytemode
, int sizeflag
)
13778 int reg
= modrm
.rm
;
13779 const char **names
;
13785 if ((sizeflag
& SUFFIX_ALWAYS
)
13786 && (bytemode
== b_swap_mode
13787 || bytemode
== bnd_swap_mode
13788 || bytemode
== v_swap_mode
))
13814 names
= address_mode
== mode_64bit
? names64
: names32
;
13817 case bnd_swap_mode
:
13826 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13831 /* Fall through. */
13833 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13839 /* Fall through. */
13851 if ((sizeflag
& DFLAG
)
13852 || (bytemode
!= v_mode
13853 && bytemode
!= v_swap_mode
))
13857 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13861 names
= (address_mode
== mode_64bit
13862 ? names64
: names32
);
13863 if (!(prefixes
& PREFIX_ADDR
))
13864 names
= (address_mode
== mode_16bit
13865 ? names16
: names
);
13868 /* Remove "addr16/addr32". */
13869 all_prefixes
[last_addr_prefix
] = 0;
13870 names
= (address_mode
!= mode_32bit
13871 ? names32
: names16
);
13872 used_prefixes
|= PREFIX_ADDR
;
13882 names
= names_mask
;
13887 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13890 oappend (names
[reg
]);
13894 OP_E_memory (int bytemode
, int sizeflag
)
13897 int add
= (rex
& REX_B
) ? 8 : 0;
13903 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13905 && bytemode
!= x_mode
13906 && bytemode
!= xmmq_mode
13907 && bytemode
!= evex_half_bcst_xmmq_mode
)
13923 if (address_mode
!= mode_64bit
)
13929 case vex_vsib_d_w_dq_mode
:
13930 case vex_vsib_d_w_d_mode
:
13931 case vex_vsib_q_w_dq_mode
:
13932 case vex_vsib_q_w_d_mode
:
13933 case evex_x_gscat_mode
:
13935 shift
= vex
.w
? 3 : 2;
13938 case evex_half_bcst_xmmq_mode
:
13942 shift
= vex
.w
? 3 : 2;
13945 /* Fall through. */
13949 case evex_x_nobcst_mode
:
13951 switch (vex
.length
)
13974 case q_scalar_mode
:
13976 case q_scalar_swap_mode
:
13982 case d_scalar_mode
:
13984 case d_scalar_swap_mode
:
13987 case w_scalar_mode
:
13991 case b_scalar_mode
:
13998 /* Make necessary corrections to shift for modes that need it.
13999 For these modes we currently have shift 4, 5 or 6 depending on
14000 vex.length (it corresponds to xmmword, ymmword or zmmword
14001 operand). We might want to make it 3, 4 or 5 (e.g. for
14002 xmmq_mode). In case of broadcast enabled the corrections
14003 aren't needed, as element size is always 32 or 64 bits. */
14005 && (bytemode
== xmmq_mode
14006 || bytemode
== evex_half_bcst_xmmq_mode
))
14008 else if (bytemode
== xmmqd_mode
)
14010 else if (bytemode
== xmmdw_mode
)
14012 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14020 intel_operand_size (bytemode
, sizeflag
);
14023 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14025 /* 32/64 bit address mode */
14035 int addr32flag
= !((sizeflag
& AFLAG
)
14036 || bytemode
== v_bnd_mode
14037 || bytemode
== v_bndmk_mode
14038 || bytemode
== bnd_mode
14039 || bytemode
== bnd_swap_mode
);
14040 const char **indexes64
= names64
;
14041 const char **indexes32
= names32
;
14051 vindex
= sib
.index
;
14057 case vex_vsib_d_w_dq_mode
:
14058 case vex_vsib_d_w_d_mode
:
14059 case vex_vsib_q_w_dq_mode
:
14060 case vex_vsib_q_w_d_mode
:
14070 switch (vex
.length
)
14073 indexes64
= indexes32
= names_xmm
;
14077 || bytemode
== vex_vsib_q_w_dq_mode
14078 || bytemode
== vex_vsib_q_w_d_mode
)
14079 indexes64
= indexes32
= names_ymm
;
14081 indexes64
= indexes32
= names_xmm
;
14085 || bytemode
== vex_vsib_q_w_dq_mode
14086 || bytemode
== vex_vsib_q_w_d_mode
)
14087 indexes64
= indexes32
= names_zmm
;
14089 indexes64
= indexes32
= names_ymm
;
14096 haveindex
= vindex
!= 4;
14103 rbase
= base
+ add
;
14111 if (address_mode
== mode_64bit
&& !havesib
)
14114 if (riprel
&& bytemode
== v_bndmk_mode
)
14122 FETCH_DATA (the_info
, codep
+ 1);
14124 if ((disp
& 0x80) != 0)
14126 if (vex
.evex
&& shift
> 0)
14139 && address_mode
!= mode_16bit
)
14141 if (address_mode
== mode_64bit
)
14143 /* Display eiz instead of addr32. */
14144 needindex
= addr32flag
;
14149 /* In 32-bit mode, we need index register to tell [offset]
14150 from [eiz*1 + offset]. */
14155 havedisp
= (havebase
14157 || (havesib
&& (haveindex
|| scale
!= 0)));
14160 if (modrm
.mod
!= 0 || base
== 5)
14162 if (havedisp
|| riprel
)
14163 print_displacement (scratchbuf
, disp
);
14165 print_operand_value (scratchbuf
, 1, disp
);
14166 oappend (scratchbuf
);
14170 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14174 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14175 && (bytemode
!= v_bnd_mode
)
14176 && (bytemode
!= v_bndmk_mode
)
14177 && (bytemode
!= bnd_mode
)
14178 && (bytemode
!= bnd_swap_mode
))
14179 used_prefixes
|= PREFIX_ADDR
;
14181 if (havedisp
|| (intel_syntax
&& riprel
))
14183 *obufp
++ = open_char
;
14184 if (intel_syntax
&& riprel
)
14187 oappend (!addr32flag
? "rip" : "eip");
14191 oappend (address_mode
== mode_64bit
&& !addr32flag
14192 ? names64
[rbase
] : names32
[rbase
]);
14195 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14196 print index to tell base + index from base. */
14200 || (havebase
&& base
!= ESP_REG_NUM
))
14202 if (!intel_syntax
|| havebase
)
14204 *obufp
++ = separator_char
;
14208 oappend (address_mode
== mode_64bit
&& !addr32flag
14209 ? indexes64
[vindex
] : indexes32
[vindex
]);
14211 oappend (address_mode
== mode_64bit
&& !addr32flag
14212 ? index64
: index32
);
14214 *obufp
++ = scale_char
;
14216 sprintf (scratchbuf
, "%d", 1 << scale
);
14217 oappend (scratchbuf
);
14221 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14223 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14228 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14232 disp
= - (bfd_signed_vma
) disp
;
14236 print_displacement (scratchbuf
, disp
);
14238 print_operand_value (scratchbuf
, 1, disp
);
14239 oappend (scratchbuf
);
14242 *obufp
++ = close_char
;
14245 else if (intel_syntax
)
14247 if (modrm
.mod
!= 0 || base
== 5)
14249 if (!active_seg_prefix
)
14251 oappend (names_seg
[ds_reg
- es_reg
]);
14254 print_operand_value (scratchbuf
, 1, disp
);
14255 oappend (scratchbuf
);
14261 /* 16 bit address mode */
14262 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14269 if ((disp
& 0x8000) != 0)
14274 FETCH_DATA (the_info
, codep
+ 1);
14276 if ((disp
& 0x80) != 0)
14278 if (vex
.evex
&& shift
> 0)
14283 if ((disp
& 0x8000) != 0)
14289 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14291 print_displacement (scratchbuf
, disp
);
14292 oappend (scratchbuf
);
14295 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14297 *obufp
++ = open_char
;
14299 oappend (index16
[modrm
.rm
]);
14301 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14303 if ((bfd_signed_vma
) disp
>= 0)
14308 else if (modrm
.mod
!= 1)
14312 disp
= - (bfd_signed_vma
) disp
;
14315 print_displacement (scratchbuf
, disp
);
14316 oappend (scratchbuf
);
14319 *obufp
++ = close_char
;
14322 else if (intel_syntax
)
14324 if (!active_seg_prefix
)
14326 oappend (names_seg
[ds_reg
- es_reg
]);
14329 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14330 oappend (scratchbuf
);
14333 if (vex
.evex
&& vex
.b
14334 && (bytemode
== x_mode
14335 || bytemode
== xmmq_mode
14336 || bytemode
== evex_half_bcst_xmmq_mode
))
14339 || bytemode
== xmmq_mode
14340 || bytemode
== evex_half_bcst_xmmq_mode
)
14342 switch (vex
.length
)
14345 oappend ("{1to2}");
14348 oappend ("{1to4}");
14351 oappend ("{1to8}");
14359 switch (vex
.length
)
14362 oappend ("{1to4}");
14365 oappend ("{1to8}");
14368 oappend ("{1to16}");
14378 OP_E (int bytemode
, int sizeflag
)
14380 /* Skip mod/rm byte. */
14384 if (modrm
.mod
== 3)
14385 OP_E_register (bytemode
, sizeflag
);
14387 OP_E_memory (bytemode
, sizeflag
);
14391 OP_G (int bytemode
, int sizeflag
)
14394 const char **names
;
14403 oappend (names8rex
[modrm
.reg
+ add
]);
14405 oappend (names8
[modrm
.reg
+ add
]);
14408 oappend (names16
[modrm
.reg
+ add
]);
14413 oappend (names32
[modrm
.reg
+ add
]);
14416 oappend (names64
[modrm
.reg
+ add
]);
14419 if (modrm
.reg
> 0x3)
14424 oappend (names_bnd
[modrm
.reg
]);
14433 oappend (names64
[modrm
.reg
+ add
]);
14436 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
14437 oappend (names32
[modrm
.reg
+ add
]);
14439 oappend (names16
[modrm
.reg
+ add
]);
14440 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14444 names
= (address_mode
== mode_64bit
14445 ? names64
: names32
);
14446 if (!(prefixes
& PREFIX_ADDR
))
14448 if (address_mode
== mode_16bit
)
14453 /* Remove "addr16/addr32". */
14454 all_prefixes
[last_addr_prefix
] = 0;
14455 names
= (address_mode
!= mode_32bit
14456 ? names32
: names16
);
14457 used_prefixes
|= PREFIX_ADDR
;
14459 oappend (names
[modrm
.reg
+ add
]);
14462 if (address_mode
== mode_64bit
)
14463 oappend (names64
[modrm
.reg
+ add
]);
14465 oappend (names32
[modrm
.reg
+ add
]);
14469 if ((modrm
.reg
+ add
) > 0x7)
14474 oappend (names_mask
[modrm
.reg
+ add
]);
14477 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14490 FETCH_DATA (the_info
, codep
+ 8);
14491 a
= *codep
++ & 0xff;
14492 a
|= (*codep
++ & 0xff) << 8;
14493 a
|= (*codep
++ & 0xff) << 16;
14494 a
|= (*codep
++ & 0xffu
) << 24;
14495 b
= *codep
++ & 0xff;
14496 b
|= (*codep
++ & 0xff) << 8;
14497 b
|= (*codep
++ & 0xff) << 16;
14498 b
|= (*codep
++ & 0xffu
) << 24;
14499 x
= a
+ ((bfd_vma
) b
<< 32);
14507 static bfd_signed_vma
14510 bfd_signed_vma x
= 0;
14512 FETCH_DATA (the_info
, codep
+ 4);
14513 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14514 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14515 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14516 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14520 static bfd_signed_vma
14523 bfd_signed_vma x
= 0;
14525 FETCH_DATA (the_info
, codep
+ 4);
14526 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14527 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14528 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14529 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14531 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14541 FETCH_DATA (the_info
, codep
+ 2);
14542 x
= *codep
++ & 0xff;
14543 x
|= (*codep
++ & 0xff) << 8;
14548 set_op (bfd_vma op
, int riprel
)
14550 op_index
[op_ad
] = op_ad
;
14551 if (address_mode
== mode_64bit
)
14553 op_address
[op_ad
] = op
;
14554 op_riprel
[op_ad
] = riprel
;
14558 /* Mask to get a 32-bit address. */
14559 op_address
[op_ad
] = op
& 0xffffffff;
14560 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14565 OP_REG (int code
, int sizeflag
)
14572 case es_reg
: case ss_reg
: case cs_reg
:
14573 case ds_reg
: case fs_reg
: case gs_reg
:
14574 oappend (names_seg
[code
- es_reg
]);
14586 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14587 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14588 s
= names16
[code
- ax_reg
+ add
];
14590 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14591 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14594 s
= names8rex
[code
- al_reg
+ add
];
14596 s
= names8
[code
- al_reg
];
14598 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14599 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14600 if (address_mode
== mode_64bit
14601 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14603 s
= names64
[code
- rAX_reg
+ add
];
14606 code
+= eAX_reg
- rAX_reg
;
14607 /* Fall through. */
14608 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14609 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14612 s
= names64
[code
- eAX_reg
+ add
];
14615 if (sizeflag
& DFLAG
)
14616 s
= names32
[code
- eAX_reg
+ add
];
14618 s
= names16
[code
- eAX_reg
+ add
];
14619 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14623 s
= INTERNAL_DISASSEMBLER_ERROR
;
14630 OP_IMREG (int code
, int sizeflag
)
14642 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14643 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14644 s
= names16
[code
- ax_reg
];
14646 case es_reg
: case ss_reg
: case cs_reg
:
14647 case ds_reg
: case fs_reg
: case gs_reg
:
14648 s
= names_seg
[code
- es_reg
];
14650 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14651 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14654 s
= names8rex
[code
- al_reg
];
14656 s
= names8
[code
- al_reg
];
14658 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14659 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14662 s
= names64
[code
- eAX_reg
];
14665 if (sizeflag
& DFLAG
)
14666 s
= names32
[code
- eAX_reg
];
14668 s
= names16
[code
- eAX_reg
];
14669 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14672 case z_mode_ax_reg
:
14673 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14677 if (!(rex
& REX_W
))
14678 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14681 s
= INTERNAL_DISASSEMBLER_ERROR
;
14688 OP_I (int bytemode
, int sizeflag
)
14691 bfd_signed_vma mask
= -1;
14696 FETCH_DATA (the_info
, codep
+ 1);
14706 if (sizeflag
& DFLAG
)
14716 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14732 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14737 scratchbuf
[0] = '$';
14738 print_operand_value (scratchbuf
+ 1, 1, op
);
14739 oappend_maybe_intel (scratchbuf
);
14740 scratchbuf
[0] = '\0';
14744 OP_I64 (int bytemode
, int sizeflag
)
14746 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
14748 OP_I (bytemode
, sizeflag
);
14754 scratchbuf
[0] = '$';
14755 print_operand_value (scratchbuf
+ 1, 1, get64 ());
14756 oappend_maybe_intel (scratchbuf
);
14757 scratchbuf
[0] = '\0';
14761 OP_sI (int bytemode
, int sizeflag
)
14769 FETCH_DATA (the_info
, codep
+ 1);
14771 if ((op
& 0x80) != 0)
14773 if (bytemode
== b_T_mode
)
14775 if (address_mode
!= mode_64bit
14776 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14778 /* The operand-size prefix is overridden by a REX prefix. */
14779 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14787 if (!(rex
& REX_W
))
14789 if (sizeflag
& DFLAG
)
14797 /* The operand-size prefix is overridden by a REX prefix. */
14798 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14804 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14808 scratchbuf
[0] = '$';
14809 print_operand_value (scratchbuf
+ 1, 1, op
);
14810 oappend_maybe_intel (scratchbuf
);
14814 OP_J (int bytemode
, int sizeflag
)
14818 bfd_vma segment
= 0;
14823 FETCH_DATA (the_info
, codep
+ 1);
14825 if ((disp
& 0x80) != 0)
14829 if (isa64
== amd64
)
14831 if ((sizeflag
& DFLAG
)
14832 || (address_mode
== mode_64bit
14833 && (isa64
!= amd64
|| (rex
& REX_W
))))
14838 if ((disp
& 0x8000) != 0)
14840 /* In 16bit mode, address is wrapped around at 64k within
14841 the same segment. Otherwise, a data16 prefix on a jump
14842 instruction means that the pc is masked to 16 bits after
14843 the displacement is added! */
14845 if ((prefixes
& PREFIX_DATA
) == 0)
14846 segment
= ((start_pc
+ (codep
- start_codep
))
14847 & ~((bfd_vma
) 0xffff));
14849 if (address_mode
!= mode_64bit
14850 || (isa64
== amd64
&& !(rex
& REX_W
)))
14851 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14854 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14857 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14859 print_operand_value (scratchbuf
, 1, disp
);
14860 oappend (scratchbuf
);
14864 OP_SEG (int bytemode
, int sizeflag
)
14866 if (bytemode
== w_mode
)
14867 oappend (names_seg
[modrm
.reg
]);
14869 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14873 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14877 if (sizeflag
& DFLAG
)
14887 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14889 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14891 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14892 oappend (scratchbuf
);
14896 OP_OFF (int bytemode
, int sizeflag
)
14900 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14901 intel_operand_size (bytemode
, sizeflag
);
14904 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14911 if (!active_seg_prefix
)
14913 oappend (names_seg
[ds_reg
- es_reg
]);
14917 print_operand_value (scratchbuf
, 1, off
);
14918 oappend (scratchbuf
);
14922 OP_OFF64 (int bytemode
, int sizeflag
)
14926 if (address_mode
!= mode_64bit
14927 || (prefixes
& PREFIX_ADDR
))
14929 OP_OFF (bytemode
, sizeflag
);
14933 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14934 intel_operand_size (bytemode
, sizeflag
);
14941 if (!active_seg_prefix
)
14943 oappend (names_seg
[ds_reg
- es_reg
]);
14947 print_operand_value (scratchbuf
, 1, off
);
14948 oappend (scratchbuf
);
14952 ptr_reg (int code
, int sizeflag
)
14956 *obufp
++ = open_char
;
14957 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14958 if (address_mode
== mode_64bit
)
14960 if (!(sizeflag
& AFLAG
))
14961 s
= names32
[code
- eAX_reg
];
14963 s
= names64
[code
- eAX_reg
];
14965 else if (sizeflag
& AFLAG
)
14966 s
= names32
[code
- eAX_reg
];
14968 s
= names16
[code
- eAX_reg
];
14970 *obufp
++ = close_char
;
14975 OP_ESreg (int code
, int sizeflag
)
14981 case 0x6d: /* insw/insl */
14982 intel_operand_size (z_mode
, sizeflag
);
14984 case 0xa5: /* movsw/movsl/movsq */
14985 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14986 case 0xab: /* stosw/stosl */
14987 case 0xaf: /* scasw/scasl */
14988 intel_operand_size (v_mode
, sizeflag
);
14991 intel_operand_size (b_mode
, sizeflag
);
14994 oappend_maybe_intel ("%es:");
14995 ptr_reg (code
, sizeflag
);
14999 OP_DSreg (int code
, int sizeflag
)
15005 case 0x6f: /* outsw/outsl */
15006 intel_operand_size (z_mode
, sizeflag
);
15008 case 0xa5: /* movsw/movsl/movsq */
15009 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15010 case 0xad: /* lodsw/lodsl/lodsq */
15011 intel_operand_size (v_mode
, sizeflag
);
15014 intel_operand_size (b_mode
, sizeflag
);
15017 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15018 default segment register DS is printed. */
15019 if (!active_seg_prefix
)
15020 active_seg_prefix
= PREFIX_DS
;
15022 ptr_reg (code
, sizeflag
);
15026 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15034 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15036 all_prefixes
[last_lock_prefix
] = 0;
15037 used_prefixes
|= PREFIX_LOCK
;
15042 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15043 oappend_maybe_intel (scratchbuf
);
15047 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15056 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15058 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15059 oappend (scratchbuf
);
15063 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15065 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15066 oappend_maybe_intel (scratchbuf
);
15070 OP_R (int bytemode
, int sizeflag
)
15072 /* Skip mod/rm byte. */
15075 OP_E_register (bytemode
, sizeflag
);
15079 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15081 int reg
= modrm
.reg
;
15082 const char **names
;
15084 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15085 if (prefixes
& PREFIX_DATA
)
15094 oappend (names
[reg
]);
15098 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15100 int reg
= modrm
.reg
;
15101 const char **names
;
15113 && bytemode
!= xmm_mode
15114 && bytemode
!= xmmq_mode
15115 && bytemode
!= evex_half_bcst_xmmq_mode
15116 && bytemode
!= ymm_mode
15117 && bytemode
!= scalar_mode
)
15119 switch (vex
.length
)
15126 || (bytemode
!= vex_vsib_q_w_dq_mode
15127 && bytemode
!= vex_vsib_q_w_d_mode
))
15139 else if (bytemode
== xmmq_mode
15140 || bytemode
== evex_half_bcst_xmmq_mode
)
15142 switch (vex
.length
)
15155 else if (bytemode
== ymm_mode
)
15159 oappend (names
[reg
]);
15163 OP_EM (int bytemode
, int sizeflag
)
15166 const char **names
;
15168 if (modrm
.mod
!= 3)
15171 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15173 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15174 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15176 OP_E (bytemode
, sizeflag
);
15180 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15183 /* Skip mod/rm byte. */
15186 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15188 if (prefixes
& PREFIX_DATA
)
15197 oappend (names
[reg
]);
15200 /* cvt* are the only instructions in sse2 which have
15201 both SSE and MMX operands and also have 0x66 prefix
15202 in their opcode. 0x66 was originally used to differentiate
15203 between SSE and MMX instruction(operands). So we have to handle the
15204 cvt* separately using OP_EMC and OP_MXC */
15206 OP_EMC (int bytemode
, int sizeflag
)
15208 if (modrm
.mod
!= 3)
15210 if (intel_syntax
&& bytemode
== v_mode
)
15212 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15213 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15215 OP_E (bytemode
, sizeflag
);
15219 /* Skip mod/rm byte. */
15222 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15223 oappend (names_mm
[modrm
.rm
]);
15227 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15229 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15230 oappend (names_mm
[modrm
.reg
]);
15234 OP_EX (int bytemode
, int sizeflag
)
15237 const char **names
;
15239 /* Skip mod/rm byte. */
15243 if (modrm
.mod
!= 3)
15245 OP_E_memory (bytemode
, sizeflag
);
15260 if ((sizeflag
& SUFFIX_ALWAYS
)
15261 && (bytemode
== x_swap_mode
15262 || bytemode
== d_swap_mode
15263 || bytemode
== d_scalar_swap_mode
15264 || bytemode
== q_swap_mode
15265 || bytemode
== q_scalar_swap_mode
))
15269 && bytemode
!= xmm_mode
15270 && bytemode
!= xmmdw_mode
15271 && bytemode
!= xmmqd_mode
15272 && bytemode
!= xmm_mb_mode
15273 && bytemode
!= xmm_mw_mode
15274 && bytemode
!= xmm_md_mode
15275 && bytemode
!= xmm_mq_mode
15276 && bytemode
!= xmm_mdq_mode
15277 && bytemode
!= xmmq_mode
15278 && bytemode
!= evex_half_bcst_xmmq_mode
15279 && bytemode
!= ymm_mode
15280 && bytemode
!= d_scalar_mode
15281 && bytemode
!= d_scalar_swap_mode
15282 && bytemode
!= q_scalar_mode
15283 && bytemode
!= q_scalar_swap_mode
15284 && bytemode
!= vex_scalar_w_dq_mode
)
15286 switch (vex
.length
)
15301 else if (bytemode
== xmmq_mode
15302 || bytemode
== evex_half_bcst_xmmq_mode
)
15304 switch (vex
.length
)
15317 else if (bytemode
== ymm_mode
)
15321 oappend (names
[reg
]);
15325 OP_MS (int bytemode
, int sizeflag
)
15327 if (modrm
.mod
== 3)
15328 OP_EM (bytemode
, sizeflag
);
15334 OP_XS (int bytemode
, int sizeflag
)
15336 if (modrm
.mod
== 3)
15337 OP_EX (bytemode
, sizeflag
);
15343 OP_M (int bytemode
, int sizeflag
)
15345 if (modrm
.mod
== 3)
15346 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15349 OP_E (bytemode
, sizeflag
);
15353 OP_0f07 (int bytemode
, int sizeflag
)
15355 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15358 OP_E (bytemode
, sizeflag
);
15361 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15362 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15365 NOP_Fixup1 (int bytemode
, int sizeflag
)
15367 if ((prefixes
& PREFIX_DATA
) != 0
15370 && address_mode
== mode_64bit
))
15371 OP_REG (bytemode
, sizeflag
);
15373 strcpy (obuf
, "nop");
15377 NOP_Fixup2 (int bytemode
, int sizeflag
)
15379 if ((prefixes
& PREFIX_DATA
) != 0
15382 && address_mode
== mode_64bit
))
15383 OP_IMREG (bytemode
, sizeflag
);
15386 static const char *const Suffix3DNow
[] = {
15387 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15388 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15389 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15390 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15391 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15392 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15393 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15394 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15395 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15396 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15397 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15398 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15399 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15400 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15401 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15402 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15403 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15404 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15405 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15406 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15407 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15408 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15409 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15410 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15411 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15412 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15413 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15414 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15415 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15416 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15417 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15418 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15419 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15420 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15421 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15422 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15423 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15424 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15425 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15426 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15427 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15428 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15429 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15430 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15431 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15432 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15433 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15434 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15435 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15436 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15437 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15438 /* CC */ NULL
, NULL
, NULL
, NULL
,
15439 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15440 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15441 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15442 /* DC */ NULL
, NULL
, NULL
, NULL
,
15443 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15444 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15445 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15446 /* EC */ NULL
, NULL
, NULL
, NULL
,
15447 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15448 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15449 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15450 /* FC */ NULL
, NULL
, NULL
, NULL
,
15454 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15456 const char *mnemonic
;
15458 FETCH_DATA (the_info
, codep
+ 1);
15459 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15460 place where an 8-bit immediate would normally go. ie. the last
15461 byte of the instruction. */
15462 obufp
= mnemonicendp
;
15463 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15465 oappend (mnemonic
);
15468 /* Since a variable sized modrm/sib chunk is between the start
15469 of the opcode (0x0f0f) and the opcode suffix, we need to do
15470 all the modrm processing first, and don't know until now that
15471 we have a bad opcode. This necessitates some cleaning up. */
15472 op_out
[0][0] = '\0';
15473 op_out
[1][0] = '\0';
15476 mnemonicendp
= obufp
;
15479 static struct op simd_cmp_op
[] =
15481 { STRING_COMMA_LEN ("eq") },
15482 { STRING_COMMA_LEN ("lt") },
15483 { STRING_COMMA_LEN ("le") },
15484 { STRING_COMMA_LEN ("unord") },
15485 { STRING_COMMA_LEN ("neq") },
15486 { STRING_COMMA_LEN ("nlt") },
15487 { STRING_COMMA_LEN ("nle") },
15488 { STRING_COMMA_LEN ("ord") }
15492 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15494 unsigned int cmp_type
;
15496 FETCH_DATA (the_info
, codep
+ 1);
15497 cmp_type
= *codep
++ & 0xff;
15498 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15501 char *p
= mnemonicendp
- 2;
15505 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15506 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15510 /* We have a reserved extension byte. Output it directly. */
15511 scratchbuf
[0] = '$';
15512 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15513 oappend_maybe_intel (scratchbuf
);
15514 scratchbuf
[0] = '\0';
15519 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
15520 int sizeflag ATTRIBUTE_UNUSED
)
15522 /* mwaitx %eax,%ecx,%ebx */
15525 const char **names
= (address_mode
== mode_64bit
15526 ? names64
: names32
);
15527 strcpy (op_out
[0], names
[0]);
15528 strcpy (op_out
[1], names
[1]);
15529 strcpy (op_out
[2], names
[3]);
15530 two_source_ops
= 1;
15532 /* Skip mod/rm byte. */
15538 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
15539 int sizeflag ATTRIBUTE_UNUSED
)
15541 /* mwait %eax,%ecx */
15544 const char **names
= (address_mode
== mode_64bit
15545 ? names64
: names32
);
15546 strcpy (op_out
[0], names
[0]);
15547 strcpy (op_out
[1], names
[1]);
15548 two_source_ops
= 1;
15550 /* Skip mod/rm byte. */
15556 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15557 int sizeflag ATTRIBUTE_UNUSED
)
15559 /* monitor %eax,%ecx,%edx" */
15562 const char **op1_names
;
15563 const char **names
= (address_mode
== mode_64bit
15564 ? names64
: names32
);
15566 if (!(prefixes
& PREFIX_ADDR
))
15567 op1_names
= (address_mode
== mode_16bit
15568 ? names16
: names
);
15571 /* Remove "addr16/addr32". */
15572 all_prefixes
[last_addr_prefix
] = 0;
15573 op1_names
= (address_mode
!= mode_32bit
15574 ? names32
: names16
);
15575 used_prefixes
|= PREFIX_ADDR
;
15577 strcpy (op_out
[0], op1_names
[0]);
15578 strcpy (op_out
[1], names
[1]);
15579 strcpy (op_out
[2], names
[2]);
15580 two_source_ops
= 1;
15582 /* Skip mod/rm byte. */
15590 /* Throw away prefixes and 1st. opcode byte. */
15591 codep
= insn_codep
+ 1;
15596 REP_Fixup (int bytemode
, int sizeflag
)
15598 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15600 if (prefixes
& PREFIX_REPZ
)
15601 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15608 OP_IMREG (bytemode
, sizeflag
);
15611 OP_ESreg (bytemode
, sizeflag
);
15614 OP_DSreg (bytemode
, sizeflag
);
15622 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15626 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15628 if (prefixes
& PREFIX_REPNZ
)
15629 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15632 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15636 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15637 int sizeflag ATTRIBUTE_UNUSED
)
15639 if (active_seg_prefix
== PREFIX_DS
15640 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15642 /* NOTRACK prefix is only valid on indirect branch instructions.
15643 NB: DATA prefix is unsupported for Intel64. */
15644 active_seg_prefix
= 0;
15645 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15649 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15650 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15654 HLE_Fixup1 (int bytemode
, int sizeflag
)
15657 && (prefixes
& PREFIX_LOCK
) != 0)
15659 if (prefixes
& PREFIX_REPZ
)
15660 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15661 if (prefixes
& PREFIX_REPNZ
)
15662 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15665 OP_E (bytemode
, sizeflag
);
15668 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15669 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15673 HLE_Fixup2 (int bytemode
, int sizeflag
)
15675 if (modrm
.mod
!= 3)
15677 if (prefixes
& PREFIX_REPZ
)
15678 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15679 if (prefixes
& PREFIX_REPNZ
)
15680 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15683 OP_E (bytemode
, sizeflag
);
15686 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15687 "xrelease" for memory operand. No check for LOCK prefix. */
15690 HLE_Fixup3 (int bytemode
, int sizeflag
)
15693 && last_repz_prefix
> last_repnz_prefix
15694 && (prefixes
& PREFIX_REPZ
) != 0)
15695 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15697 OP_E (bytemode
, sizeflag
);
15701 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15706 /* Change cmpxchg8b to cmpxchg16b. */
15707 char *p
= mnemonicendp
- 2;
15708 mnemonicendp
= stpcpy (p
, "16b");
15711 else if ((prefixes
& PREFIX_LOCK
) != 0)
15713 if (prefixes
& PREFIX_REPZ
)
15714 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15715 if (prefixes
& PREFIX_REPNZ
)
15716 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15719 OP_M (bytemode
, sizeflag
);
15723 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15725 const char **names
;
15729 switch (vex
.length
)
15743 oappend (names
[reg
]);
15747 CRC32_Fixup (int bytemode
, int sizeflag
)
15749 /* Add proper suffix to "crc32". */
15750 char *p
= mnemonicendp
;
15769 if (sizeflag
& DFLAG
)
15773 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15777 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15784 if (modrm
.mod
== 3)
15788 /* Skip mod/rm byte. */
15793 add
= (rex
& REX_B
) ? 8 : 0;
15794 if (bytemode
== b_mode
)
15798 oappend (names8rex
[modrm
.rm
+ add
]);
15800 oappend (names8
[modrm
.rm
+ add
]);
15806 oappend (names64
[modrm
.rm
+ add
]);
15807 else if ((prefixes
& PREFIX_DATA
))
15808 oappend (names16
[modrm
.rm
+ add
]);
15810 oappend (names32
[modrm
.rm
+ add
]);
15814 OP_E (bytemode
, sizeflag
);
15818 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15820 /* Add proper suffix to "fxsave" and "fxrstor". */
15824 char *p
= mnemonicendp
;
15830 OP_M (bytemode
, sizeflag
);
15834 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15836 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15839 char *p
= mnemonicendp
;
15844 else if (sizeflag
& SUFFIX_ALWAYS
)
15851 OP_EX (bytemode
, sizeflag
);
15854 /* Display the destination register operand for instructions with
15858 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15861 const char **names
;
15869 reg
= vex
.register_specifier
;
15870 vex
.register_specifier
= 0;
15871 if (address_mode
!= mode_64bit
)
15873 else if (vex
.evex
&& !vex
.v
)
15876 if (bytemode
== vex_scalar_mode
)
15878 oappend (names_xmm
[reg
]);
15882 switch (vex
.length
)
15889 case vex_vsib_q_w_dq_mode
:
15890 case vex_vsib_q_w_d_mode
:
15906 names
= names_mask
;
15920 case vex_vsib_q_w_dq_mode
:
15921 case vex_vsib_q_w_d_mode
:
15922 names
= vex
.w
? names_ymm
: names_xmm
;
15931 names
= names_mask
;
15934 /* See PR binutils/20893 for a reproducer. */
15946 oappend (names
[reg
]);
15949 /* Get the VEX immediate byte without moving codep. */
15951 static unsigned char
15952 get_vex_imm8 (int sizeflag
, int opnum
)
15954 int bytes_before_imm
= 0;
15956 if (modrm
.mod
!= 3)
15958 /* There are SIB/displacement bytes. */
15959 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15961 /* 32/64 bit address mode */
15962 int base
= modrm
.rm
;
15964 /* Check SIB byte. */
15967 FETCH_DATA (the_info
, codep
+ 1);
15969 /* When decoding the third source, don't increase
15970 bytes_before_imm as this has already been incremented
15971 by one in OP_E_memory while decoding the second
15974 bytes_before_imm
++;
15977 /* Don't increase bytes_before_imm when decoding the third source,
15978 it has already been incremented by OP_E_memory while decoding
15979 the second source operand. */
15985 /* When modrm.rm == 5 or modrm.rm == 4 and base in
15986 SIB == 5, there is a 4 byte displacement. */
15988 /* No displacement. */
15990 /* Fall through. */
15992 /* 4 byte displacement. */
15993 bytes_before_imm
+= 4;
15996 /* 1 byte displacement. */
15997 bytes_before_imm
++;
16004 /* 16 bit address mode */
16005 /* Don't increase bytes_before_imm when decoding the third source,
16006 it has already been incremented by OP_E_memory while decoding
16007 the second source operand. */
16013 /* When modrm.rm == 6, there is a 2 byte displacement. */
16015 /* No displacement. */
16017 /* Fall through. */
16019 /* 2 byte displacement. */
16020 bytes_before_imm
+= 2;
16023 /* 1 byte displacement: when decoding the third source,
16024 don't increase bytes_before_imm as this has already
16025 been incremented by one in OP_E_memory while decoding
16026 the second source operand. */
16028 bytes_before_imm
++;
16036 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16037 return codep
[bytes_before_imm
];
16041 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16043 const char **names
;
16045 if (reg
== -1 && modrm
.mod
!= 3)
16047 OP_E_memory (bytemode
, sizeflag
);
16059 if (address_mode
!= mode_64bit
)
16063 switch (vex
.length
)
16074 oappend (names
[reg
]);
16078 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16081 static unsigned char vex_imm8
;
16083 if (vex_w_done
== 0)
16087 /* Skip mod/rm byte. */
16091 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16094 reg
= vex_imm8
>> 4;
16096 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16098 else if (vex_w_done
== 1)
16103 reg
= vex_imm8
>> 4;
16105 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16109 /* Output the imm8 directly. */
16110 scratchbuf
[0] = '$';
16111 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16112 oappend_maybe_intel (scratchbuf
);
16113 scratchbuf
[0] = '\0';
16119 OP_Vex_2src (int bytemode
, int sizeflag
)
16121 if (modrm
.mod
== 3)
16123 int reg
= modrm
.rm
;
16127 oappend (names_xmm
[reg
]);
16132 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16134 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16135 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16137 OP_E (bytemode
, sizeflag
);
16142 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16144 if (modrm
.mod
== 3)
16146 /* Skip mod/rm byte. */
16153 unsigned int reg
= vex
.register_specifier
;
16154 vex
.register_specifier
= 0;
16156 if (address_mode
!= mode_64bit
)
16158 oappend (names_xmm
[reg
]);
16161 OP_Vex_2src (bytemode
, sizeflag
);
16165 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16168 OP_Vex_2src (bytemode
, sizeflag
);
16171 unsigned int reg
= vex
.register_specifier
;
16172 vex
.register_specifier
= 0;
16174 if (address_mode
!= mode_64bit
)
16176 oappend (names_xmm
[reg
]);
16181 OP_EX_VexW (int bytemode
, int sizeflag
)
16187 /* Skip mod/rm byte. */
16192 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16197 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16200 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16208 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16211 const char **names
;
16213 FETCH_DATA (the_info
, codep
+ 1);
16216 if (bytemode
!= x_mode
)
16220 if (address_mode
!= mode_64bit
)
16223 switch (vex
.length
)
16234 oappend (names
[reg
]);
16238 OP_XMM_VexW (int bytemode
, int sizeflag
)
16240 /* Turn off the REX.W bit since it is used for swapping operands
16243 OP_XMM (bytemode
, sizeflag
);
16247 OP_EX_Vex (int bytemode
, int sizeflag
)
16249 if (modrm
.mod
!= 3)
16251 OP_EX (bytemode
, sizeflag
);
16255 OP_XMM_Vex (int bytemode
, int sizeflag
)
16257 if (modrm
.mod
!= 3)
16259 OP_XMM (bytemode
, sizeflag
);
16262 static struct op vex_cmp_op
[] =
16264 { STRING_COMMA_LEN ("eq") },
16265 { STRING_COMMA_LEN ("lt") },
16266 { STRING_COMMA_LEN ("le") },
16267 { STRING_COMMA_LEN ("unord") },
16268 { STRING_COMMA_LEN ("neq") },
16269 { STRING_COMMA_LEN ("nlt") },
16270 { STRING_COMMA_LEN ("nle") },
16271 { STRING_COMMA_LEN ("ord") },
16272 { STRING_COMMA_LEN ("eq_uq") },
16273 { STRING_COMMA_LEN ("nge") },
16274 { STRING_COMMA_LEN ("ngt") },
16275 { STRING_COMMA_LEN ("false") },
16276 { STRING_COMMA_LEN ("neq_oq") },
16277 { STRING_COMMA_LEN ("ge") },
16278 { STRING_COMMA_LEN ("gt") },
16279 { STRING_COMMA_LEN ("true") },
16280 { STRING_COMMA_LEN ("eq_os") },
16281 { STRING_COMMA_LEN ("lt_oq") },
16282 { STRING_COMMA_LEN ("le_oq") },
16283 { STRING_COMMA_LEN ("unord_s") },
16284 { STRING_COMMA_LEN ("neq_us") },
16285 { STRING_COMMA_LEN ("nlt_uq") },
16286 { STRING_COMMA_LEN ("nle_uq") },
16287 { STRING_COMMA_LEN ("ord_s") },
16288 { STRING_COMMA_LEN ("eq_us") },
16289 { STRING_COMMA_LEN ("nge_uq") },
16290 { STRING_COMMA_LEN ("ngt_uq") },
16291 { STRING_COMMA_LEN ("false_os") },
16292 { STRING_COMMA_LEN ("neq_os") },
16293 { STRING_COMMA_LEN ("ge_oq") },
16294 { STRING_COMMA_LEN ("gt_oq") },
16295 { STRING_COMMA_LEN ("true_us") },
16299 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16301 unsigned int cmp_type
;
16303 FETCH_DATA (the_info
, codep
+ 1);
16304 cmp_type
= *codep
++ & 0xff;
16305 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16308 char *p
= mnemonicendp
- 2;
16312 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16313 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16317 /* We have a reserved extension byte. Output it directly. */
16318 scratchbuf
[0] = '$';
16319 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16320 oappend_maybe_intel (scratchbuf
);
16321 scratchbuf
[0] = '\0';
16326 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16327 int sizeflag ATTRIBUTE_UNUSED
)
16329 unsigned int cmp_type
;
16334 FETCH_DATA (the_info
, codep
+ 1);
16335 cmp_type
= *codep
++ & 0xff;
16336 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16337 If it's the case, print suffix, otherwise - print the immediate. */
16338 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16343 char *p
= mnemonicendp
- 2;
16345 /* vpcmp* can have both one- and two-lettered suffix. */
16359 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16360 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16364 /* We have a reserved extension byte. Output it directly. */
16365 scratchbuf
[0] = '$';
16366 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16367 oappend_maybe_intel (scratchbuf
);
16368 scratchbuf
[0] = '\0';
16372 static const struct op xop_cmp_op
[] =
16374 { STRING_COMMA_LEN ("lt") },
16375 { STRING_COMMA_LEN ("le") },
16376 { STRING_COMMA_LEN ("gt") },
16377 { STRING_COMMA_LEN ("ge") },
16378 { STRING_COMMA_LEN ("eq") },
16379 { STRING_COMMA_LEN ("neq") },
16380 { STRING_COMMA_LEN ("false") },
16381 { STRING_COMMA_LEN ("true") }
16385 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16386 int sizeflag ATTRIBUTE_UNUSED
)
16388 unsigned int cmp_type
;
16390 FETCH_DATA (the_info
, codep
+ 1);
16391 cmp_type
= *codep
++ & 0xff;
16392 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16395 char *p
= mnemonicendp
- 2;
16397 /* vpcom* can have both one- and two-lettered suffix. */
16411 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16412 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16416 /* We have a reserved extension byte. Output it directly. */
16417 scratchbuf
[0] = '$';
16418 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16419 oappend_maybe_intel (scratchbuf
);
16420 scratchbuf
[0] = '\0';
16424 static const struct op pclmul_op
[] =
16426 { STRING_COMMA_LEN ("lql") },
16427 { STRING_COMMA_LEN ("hql") },
16428 { STRING_COMMA_LEN ("lqh") },
16429 { STRING_COMMA_LEN ("hqh") }
16433 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16434 int sizeflag ATTRIBUTE_UNUSED
)
16436 unsigned int pclmul_type
;
16438 FETCH_DATA (the_info
, codep
+ 1);
16439 pclmul_type
= *codep
++ & 0xff;
16440 switch (pclmul_type
)
16451 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16454 char *p
= mnemonicendp
- 3;
16459 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16460 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16464 /* We have a reserved extension byte. Output it directly. */
16465 scratchbuf
[0] = '$';
16466 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16467 oappend_maybe_intel (scratchbuf
);
16468 scratchbuf
[0] = '\0';
16473 MOVBE_Fixup (int bytemode
, int sizeflag
)
16475 /* Add proper suffix to "movbe". */
16476 char *p
= mnemonicendp
;
16485 if (sizeflag
& SUFFIX_ALWAYS
)
16491 if (sizeflag
& DFLAG
)
16495 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16500 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16507 OP_M (bytemode
, sizeflag
);
16511 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16514 const char **names
;
16516 /* Skip mod/rm byte. */
16530 oappend (names
[reg
]);
16534 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16536 const char **names
;
16537 unsigned int reg
= vex
.register_specifier
;
16538 vex
.register_specifier
= 0;
16545 if (address_mode
!= mode_64bit
)
16547 oappend (names
[reg
]);
16551 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16554 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16558 if ((rex
& REX_R
) != 0 || !vex
.r
)
16564 oappend (names_mask
[modrm
.reg
]);
16568 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16571 || (bytemode
!= evex_rounding_mode
16572 && bytemode
!= evex_rounding_64_mode
16573 && bytemode
!= evex_sae_mode
))
16575 if (modrm
.mod
== 3 && vex
.b
)
16578 case evex_rounding_64_mode
:
16579 if (address_mode
!= mode_64bit
)
16584 /* Fall through. */
16585 case evex_rounding_mode
:
16586 oappend (names_rounding
[vex
.ll
]);
16588 case evex_sae_mode
: