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x86: correct decoding of nop/reserved space (0f18 ... 0x1f)
[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2021 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 July 1988
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
34
35 #include "sysdep.h"
36 #include "disassemble.h"
37 #include "opintl.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
41
42 #include <setjmp.h>
43
44 static int print_insn (bfd_vma, disassemble_info *);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma get64 (void);
59 static bfd_signed_vma get32 (void);
60 static bfd_signed_vma get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_VexR (int, int);
91 static void OP_VexW (int, int);
92 static void OP_Rounding (int, int);
93 static void OP_REG_VexI4 (int, int);
94 static void OP_VexI4 (int, int);
95 static void PCLMUL_Fixup (int, int);
96 static void VPCMP_Fixup (int, int);
97 static void VPCOM_Fixup (int, int);
98 static void OP_0f07 (int, int);
99 static void OP_Monitor (int, int);
100 static void OP_Mwait (int, int);
101 static void NOP_Fixup1 (int, int);
102 static void NOP_Fixup2 (int, int);
103 static void OP_3DNowSuffix (int, int);
104 static void CMP_Fixup (int, int);
105 static void BadOp (void);
106 static void REP_Fixup (int, int);
107 static void SEP_Fixup (int, int);
108 static void BND_Fixup (int, int);
109 static void NOTRACK_Fixup (int, int);
110 static void HLE_Fixup1 (int, int);
111 static void HLE_Fixup2 (int, int);
112 static void HLE_Fixup3 (int, int);
113 static void CMPXCHG8B_Fixup (int, int);
114 static void XMM_Fixup (int, int);
115 static void FXSAVE_Fixup (int, int);
116
117 static void MOVSXD_Fixup (int, int);
118
119 static void OP_Mask (int, int);
120
121 struct dis_private {
122 /* Points to first byte not fetched. */
123 bfd_byte *max_fetched;
124 bfd_byte the_buffer[MAX_MNEM_SIZE];
125 bfd_vma insn_start;
126 int orig_sizeflag;
127 OPCODES_SIGJMP_BUF bailout;
128 };
129
130 enum address_mode
131 {
132 mode_16bit,
133 mode_32bit,
134 mode_64bit
135 };
136
137 enum address_mode address_mode;
138
139 /* Flags for the prefixes for the current instruction. See below. */
140 static int prefixes;
141
142 /* REX prefix the current instruction. See below. */
143 static int rex;
144 /* Bits of REX we've already used. */
145 static int rex_used;
146 /* Mark parts used in the REX prefix. When we are testing for
147 empty prefix (for 8bit register REX extension), just mask it
148 out. Otherwise test for REX bit is excuse for existence of REX
149 only in case value is nonzero. */
150 #define USED_REX(value) \
151 { \
152 if (value) \
153 { \
154 if ((rex & value)) \
155 rex_used |= (value) | REX_OPCODE; \
156 } \
157 else \
158 rex_used |= REX_OPCODE; \
159 }
160
161 /* Flags for prefixes which we somehow handled when printing the
162 current instruction. */
163 static int used_prefixes;
164
165 /* Flags stored in PREFIXES. */
166 #define PREFIX_REPZ 1
167 #define PREFIX_REPNZ 2
168 #define PREFIX_LOCK 4
169 #define PREFIX_CS 8
170 #define PREFIX_SS 0x10
171 #define PREFIX_DS 0x20
172 #define PREFIX_ES 0x40
173 #define PREFIX_FS 0x80
174 #define PREFIX_GS 0x100
175 #define PREFIX_DATA 0x200
176 #define PREFIX_ADDR 0x400
177 #define PREFIX_FWAIT 0x800
178
179 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
180 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
181 on error. */
182 #define FETCH_DATA(info, addr) \
183 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
184 ? 1 : fetch_data ((info), (addr)))
185
186 static int
187 fetch_data (struct disassemble_info *info, bfd_byte *addr)
188 {
189 int status;
190 struct dis_private *priv = (struct dis_private *) info->private_data;
191 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
192
193 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
194 status = (*info->read_memory_func) (start,
195 priv->max_fetched,
196 addr - priv->max_fetched,
197 info);
198 else
199 status = -1;
200 if (status != 0)
201 {
202 /* If we did manage to read at least one byte, then
203 print_insn_i386 will do something sensible. Otherwise, print
204 an error. We do that here because this is where we know
205 STATUS. */
206 if (priv->max_fetched == priv->the_buffer)
207 (*info->memory_error_func) (status, start, info);
208 OPCODES_SIGLONGJMP (priv->bailout, 1);
209 }
210 else
211 priv->max_fetched = addr;
212 return 1;
213 }
214
215 /* Possible values for prefix requirement. */
216 #define PREFIX_IGNORED_SHIFT 16
217 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
218 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
219 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
220 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
221 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
222
223 /* Opcode prefixes. */
224 #define PREFIX_OPCODE (PREFIX_REPZ \
225 | PREFIX_REPNZ \
226 | PREFIX_DATA)
227
228 /* Prefixes ignored. */
229 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
230 | PREFIX_IGNORED_REPNZ \
231 | PREFIX_IGNORED_DATA)
232
233 #define XX { NULL, 0 }
234 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
235
236 #define Eb { OP_E, b_mode }
237 #define Ebnd { OP_E, bnd_mode }
238 #define EbS { OP_E, b_swap_mode }
239 #define EbndS { OP_E, bnd_swap_mode }
240 #define Ev { OP_E, v_mode }
241 #define Eva { OP_E, va_mode }
242 #define Ev_bnd { OP_E, v_bnd_mode }
243 #define EvS { OP_E, v_swap_mode }
244 #define Ed { OP_E, d_mode }
245 #define Edq { OP_E, dq_mode }
246 #define Edqw { OP_E, dqw_mode }
247 #define Edqb { OP_E, dqb_mode }
248 #define Edb { OP_E, db_mode }
249 #define Edw { OP_E, dw_mode }
250 #define Edqd { OP_E, dqd_mode }
251 #define Eq { OP_E, q_mode }
252 #define indirEv { OP_indirE, indir_v_mode }
253 #define indirEp { OP_indirE, f_mode }
254 #define stackEv { OP_E, stack_v_mode }
255 #define Em { OP_E, m_mode }
256 #define Ew { OP_E, w_mode }
257 #define M { OP_M, 0 } /* lea, lgdt, etc. */
258 #define Ma { OP_M, a_mode }
259 #define Mb { OP_M, b_mode }
260 #define Md { OP_M, d_mode }
261 #define Mo { OP_M, o_mode }
262 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
263 #define Mq { OP_M, q_mode }
264 #define Mv { OP_M, v_mode }
265 #define Mv_bnd { OP_M, v_bndmk_mode }
266 #define Mx { OP_M, x_mode }
267 #define Mxmm { OP_M, xmm_mode }
268 #define Gb { OP_G, b_mode }
269 #define Gbnd { OP_G, bnd_mode }
270 #define Gv { OP_G, v_mode }
271 #define Gd { OP_G, d_mode }
272 #define Gdq { OP_G, dq_mode }
273 #define Gm { OP_G, m_mode }
274 #define Gva { OP_G, va_mode }
275 #define Gw { OP_G, w_mode }
276 #define Ib { OP_I, b_mode }
277 #define sIb { OP_sI, b_mode } /* sign extened byte */
278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
279 #define Iv { OP_I, v_mode }
280 #define sIv { OP_sI, v_mode }
281 #define Iv64 { OP_I64, v_mode }
282 #define Id { OP_I, d_mode }
283 #define Iw { OP_I, w_mode }
284 #define I1 { OP_I, const_1_mode }
285 #define Jb { OP_J, b_mode }
286 #define Jv { OP_J, v_mode }
287 #define Jdqw { OP_J, dqw_mode }
288 #define Cm { OP_C, m_mode }
289 #define Dm { OP_D, m_mode }
290 #define Td { OP_T, d_mode }
291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
292
293 #define RMeAX { OP_REG, eAX_reg }
294 #define RMeBX { OP_REG, eBX_reg }
295 #define RMeCX { OP_REG, eCX_reg }
296 #define RMeDX { OP_REG, eDX_reg }
297 #define RMeSP { OP_REG, eSP_reg }
298 #define RMeBP { OP_REG, eBP_reg }
299 #define RMeSI { OP_REG, eSI_reg }
300 #define RMeDI { OP_REG, eDI_reg }
301 #define RMrAX { OP_REG, rAX_reg }
302 #define RMrBX { OP_REG, rBX_reg }
303 #define RMrCX { OP_REG, rCX_reg }
304 #define RMrDX { OP_REG, rDX_reg }
305 #define RMrSP { OP_REG, rSP_reg }
306 #define RMrBP { OP_REG, rBP_reg }
307 #define RMrSI { OP_REG, rSI_reg }
308 #define RMrDI { OP_REG, rDI_reg }
309 #define RMAL { OP_REG, al_reg }
310 #define RMCL { OP_REG, cl_reg }
311 #define RMDL { OP_REG, dl_reg }
312 #define RMBL { OP_REG, bl_reg }
313 #define RMAH { OP_REG, ah_reg }
314 #define RMCH { OP_REG, ch_reg }
315 #define RMDH { OP_REG, dh_reg }
316 #define RMBH { OP_REG, bh_reg }
317 #define RMAX { OP_REG, ax_reg }
318 #define RMDX { OP_REG, dx_reg }
319
320 #define eAX { OP_IMREG, eAX_reg }
321 #define AL { OP_IMREG, al_reg }
322 #define CL { OP_IMREG, cl_reg }
323 #define zAX { OP_IMREG, z_mode_ax_reg }
324 #define indirDX { OP_IMREG, indir_dx_reg }
325
326 #define Sw { OP_SEG, w_mode }
327 #define Sv { OP_SEG, v_mode }
328 #define Ap { OP_DIR, 0 }
329 #define Ob { OP_OFF64, b_mode }
330 #define Ov { OP_OFF64, v_mode }
331 #define Xb { OP_DSreg, eSI_reg }
332 #define Xv { OP_DSreg, eSI_reg }
333 #define Xz { OP_DSreg, eSI_reg }
334 #define Yb { OP_ESreg, eDI_reg }
335 #define Yv { OP_ESreg, eDI_reg }
336 #define DSBX { OP_DSreg, eBX_reg }
337
338 #define es { OP_REG, es_reg }
339 #define ss { OP_REG, ss_reg }
340 #define cs { OP_REG, cs_reg }
341 #define ds { OP_REG, ds_reg }
342 #define fs { OP_REG, fs_reg }
343 #define gs { OP_REG, gs_reg }
344
345 #define MX { OP_MMX, 0 }
346 #define XM { OP_XMM, 0 }
347 #define XMScalar { OP_XMM, scalar_mode }
348 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
349 #define XMM { OP_XMM, xmm_mode }
350 #define TMM { OP_XMM, tmm_mode }
351 #define XMxmmq { OP_XMM, xmmq_mode }
352 #define EM { OP_EM, v_mode }
353 #define EMS { OP_EM, v_swap_mode }
354 #define EMd { OP_EM, d_mode }
355 #define EMx { OP_EM, x_mode }
356 #define EXbwUnit { OP_EX, bw_unit_mode }
357 #define EXw { OP_EX, w_mode }
358 #define EXd { OP_EX, d_mode }
359 #define EXdS { OP_EX, d_swap_mode }
360 #define EXq { OP_EX, q_mode }
361 #define EXqS { OP_EX, q_swap_mode }
362 #define EXx { OP_EX, x_mode }
363 #define EXxS { OP_EX, x_swap_mode }
364 #define EXxmm { OP_EX, xmm_mode }
365 #define EXymm { OP_EX, ymm_mode }
366 #define EXtmm { OP_EX, tmm_mode }
367 #define EXxmmq { OP_EX, xmmq_mode }
368 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
369 #define EXxmm_mb { OP_EX, xmm_mb_mode }
370 #define EXxmm_mw { OP_EX, xmm_mw_mode }
371 #define EXxmm_md { OP_EX, xmm_md_mode }
372 #define EXxmm_mq { OP_EX, xmm_mq_mode }
373 #define EXxmmdw { OP_EX, xmmdw_mode }
374 #define EXxmmqd { OP_EX, xmmqd_mode }
375 #define EXymmq { OP_EX, ymmq_mode }
376 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
377 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
378 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
379 #define MS { OP_MS, v_mode }
380 #define XS { OP_XS, v_mode }
381 #define EMCq { OP_EMC, q_mode }
382 #define MXC { OP_MXC, 0 }
383 #define OPSUF { OP_3DNowSuffix, 0 }
384 #define SEP { SEP_Fixup, 0 }
385 #define CMP { CMP_Fixup, 0 }
386 #define XMM0 { XMM_Fixup, 0 }
387 #define FXSAVE { FXSAVE_Fixup, 0 }
388
389 #define Vex { OP_VEX, vex_mode }
390 #define VexW { OP_VexW, vex_mode }
391 #define VexScalar { OP_VEX, vex_scalar_mode }
392 #define VexScalarR { OP_VexR, vex_scalar_mode }
393 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
394 #define VexGdq { OP_VEX, dq_mode }
395 #define VexTmm { OP_VEX, tmm_mode }
396 #define XMVexI4 { OP_REG_VexI4, x_mode }
397 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
398 #define VexI4 { OP_VexI4, 0 }
399 #define PCLMUL { PCLMUL_Fixup, 0 }
400 #define VPCMP { VPCMP_Fixup, 0 }
401 #define VPCOM { VPCOM_Fixup, 0 }
402
403 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
404 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
405 #define EXxEVexS { OP_Rounding, evex_sae_mode }
406
407 #define XMask { OP_Mask, mask_mode }
408 #define MaskG { OP_G, mask_mode }
409 #define MaskE { OP_E, mask_mode }
410 #define MaskBDE { OP_E, mask_bd_mode }
411 #define MaskVex { OP_VEX, mask_mode }
412
413 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
414 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
415 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
416 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
417
418 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
419
420 /* Used handle "rep" prefix for string instructions. */
421 #define Xbr { REP_Fixup, eSI_reg }
422 #define Xvr { REP_Fixup, eSI_reg }
423 #define Ybr { REP_Fixup, eDI_reg }
424 #define Yvr { REP_Fixup, eDI_reg }
425 #define Yzr { REP_Fixup, eDI_reg }
426 #define indirDXr { REP_Fixup, indir_dx_reg }
427 #define ALr { REP_Fixup, al_reg }
428 #define eAXr { REP_Fixup, eAX_reg }
429
430 /* Used handle HLE prefix for lockable instructions. */
431 #define Ebh1 { HLE_Fixup1, b_mode }
432 #define Evh1 { HLE_Fixup1, v_mode }
433 #define Ebh2 { HLE_Fixup2, b_mode }
434 #define Evh2 { HLE_Fixup2, v_mode }
435 #define Ebh3 { HLE_Fixup3, b_mode }
436 #define Evh3 { HLE_Fixup3, v_mode }
437
438 #define BND { BND_Fixup, 0 }
439 #define NOTRACK { NOTRACK_Fixup, 0 }
440
441 #define cond_jump_flag { NULL, cond_jump_mode }
442 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
443
444 /* bits in sizeflag */
445 #define SUFFIX_ALWAYS 4
446 #define AFLAG 2
447 #define DFLAG 1
448
449 enum
450 {
451 /* byte operand */
452 b_mode = 1,
453 /* byte operand with operand swapped */
454 b_swap_mode,
455 /* byte operand, sign extend like 'T' suffix */
456 b_T_mode,
457 /* operand size depends on prefixes */
458 v_mode,
459 /* operand size depends on prefixes with operand swapped */
460 v_swap_mode,
461 /* operand size depends on address prefix */
462 va_mode,
463 /* word operand */
464 w_mode,
465 /* double word operand */
466 d_mode,
467 /* double word operand with operand swapped */
468 d_swap_mode,
469 /* quad word operand */
470 q_mode,
471 /* quad word operand with operand swapped */
472 q_swap_mode,
473 /* ten-byte operand */
474 t_mode,
475 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
476 broadcast enabled. */
477 x_mode,
478 /* Similar to x_mode, but with different EVEX mem shifts. */
479 evex_x_gscat_mode,
480 /* Similar to x_mode, but with yet different EVEX mem shifts. */
481 bw_unit_mode,
482 /* Similar to x_mode, but with disabled broadcast. */
483 evex_x_nobcst_mode,
484 /* Similar to x_mode, but with operands swapped and disabled broadcast
485 in EVEX. */
486 x_swap_mode,
487 /* 16-byte XMM operand */
488 xmm_mode,
489 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
490 memory operand (depending on vector length). Broadcast isn't
491 allowed. */
492 xmmq_mode,
493 /* Same as xmmq_mode, but broadcast is allowed. */
494 evex_half_bcst_xmmq_mode,
495 /* XMM register or byte memory operand */
496 xmm_mb_mode,
497 /* XMM register or word memory operand */
498 xmm_mw_mode,
499 /* XMM register or double word memory operand */
500 xmm_md_mode,
501 /* XMM register or quad word memory operand */
502 xmm_mq_mode,
503 /* 16-byte XMM, word, double word or quad word operand. */
504 xmmdw_mode,
505 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
506 xmmqd_mode,
507 /* 32-byte YMM operand */
508 ymm_mode,
509 /* quad word, ymmword or zmmword memory operand. */
510 ymmq_mode,
511 /* 32-byte YMM or 16-byte word operand */
512 ymmxmm_mode,
513 /* TMM operand */
514 tmm_mode,
515 /* d_mode in 32bit, q_mode in 64bit mode. */
516 m_mode,
517 /* pair of v_mode operands */
518 a_mode,
519 cond_jump_mode,
520 loop_jcxz_mode,
521 movsxd_mode,
522 v_bnd_mode,
523 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
524 v_bndmk_mode,
525 /* operand size depends on REX prefixes. */
526 dq_mode,
527 /* registers like dq_mode, memory like w_mode, displacements like
528 v_mode without considering Intel64 ISA. */
529 dqw_mode,
530 /* bounds operand */
531 bnd_mode,
532 /* bounds operand with operand swapped */
533 bnd_swap_mode,
534 /* 4- or 6-byte pointer operand */
535 f_mode,
536 const_1_mode,
537 /* v_mode for indirect branch opcodes. */
538 indir_v_mode,
539 /* v_mode for stack-related opcodes. */
540 stack_v_mode,
541 /* non-quad operand size depends on prefixes */
542 z_mode,
543 /* 16-byte operand */
544 o_mode,
545 /* registers like dq_mode, memory like b_mode. */
546 dqb_mode,
547 /* registers like d_mode, memory like b_mode. */
548 db_mode,
549 /* registers like d_mode, memory like w_mode. */
550 dw_mode,
551 /* registers like dq_mode, memory like d_mode. */
552 dqd_mode,
553 /* normal vex mode */
554 vex_mode,
555
556 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
557 vex_vsib_d_w_dq_mode,
558 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
559 vex_vsib_d_w_d_mode,
560 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
561 vex_vsib_q_w_dq_mode,
562 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
563 vex_vsib_q_w_d_mode,
564 /* mandatory non-vector SIB. */
565 vex_sibmem_mode,
566
567 /* scalar, ignore vector length. */
568 scalar_mode,
569 /* like vex_mode, ignore vector length. */
570 vex_scalar_mode,
571 /* Operand size depends on the VEX.W bit, ignore vector length. */
572 vex_scalar_w_dq_mode,
573
574 /* Static rounding. */
575 evex_rounding_mode,
576 /* Static rounding, 64-bit mode only. */
577 evex_rounding_64_mode,
578 /* Supress all exceptions. */
579 evex_sae_mode,
580
581 /* Mask register operand. */
582 mask_mode,
583 /* Mask register operand. */
584 mask_bd_mode,
585
586 es_reg,
587 cs_reg,
588 ss_reg,
589 ds_reg,
590 fs_reg,
591 gs_reg,
592
593 eAX_reg,
594 eCX_reg,
595 eDX_reg,
596 eBX_reg,
597 eSP_reg,
598 eBP_reg,
599 eSI_reg,
600 eDI_reg,
601
602 al_reg,
603 cl_reg,
604 dl_reg,
605 bl_reg,
606 ah_reg,
607 ch_reg,
608 dh_reg,
609 bh_reg,
610
611 ax_reg,
612 cx_reg,
613 dx_reg,
614 bx_reg,
615 sp_reg,
616 bp_reg,
617 si_reg,
618 di_reg,
619
620 rAX_reg,
621 rCX_reg,
622 rDX_reg,
623 rBX_reg,
624 rSP_reg,
625 rBP_reg,
626 rSI_reg,
627 rDI_reg,
628
629 z_mode_ax_reg,
630 indir_dx_reg
631 };
632
633 enum
634 {
635 FLOATCODE = 1,
636 USE_REG_TABLE,
637 USE_MOD_TABLE,
638 USE_RM_TABLE,
639 USE_PREFIX_TABLE,
640 USE_X86_64_TABLE,
641 USE_3BYTE_TABLE,
642 USE_XOP_8F_TABLE,
643 USE_VEX_C4_TABLE,
644 USE_VEX_C5_TABLE,
645 USE_VEX_LEN_TABLE,
646 USE_VEX_W_TABLE,
647 USE_EVEX_TABLE,
648 USE_EVEX_LEN_TABLE
649 };
650
651 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
652
653 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
654 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
655 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
656 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
657 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
658 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
659 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
660 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
661 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
662 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
663 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
664 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
665 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
666 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
667 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
668 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
669
670 enum
671 {
672 REG_80 = 0,
673 REG_81,
674 REG_83,
675 REG_8F,
676 REG_C0,
677 REG_C1,
678 REG_C6,
679 REG_C7,
680 REG_D0,
681 REG_D1,
682 REG_D2,
683 REG_D3,
684 REG_F6,
685 REG_F7,
686 REG_FE,
687 REG_FF,
688 REG_0F00,
689 REG_0F01,
690 REG_0F0D,
691 REG_0F18,
692 REG_0F1C_P_0_MOD_0,
693 REG_0F1E_P_1_MOD_3,
694 REG_0F38D8_PREFIX_1,
695 REG_0F3A0F_PREFIX_1_MOD_3,
696 REG_0F71,
697 REG_0F72,
698 REG_0F73,
699 REG_0FA6,
700 REG_0FA7,
701 REG_0FAE,
702 REG_0FBA,
703 REG_0FC7,
704 REG_VEX_0F71,
705 REG_VEX_0F72,
706 REG_VEX_0F73,
707 REG_VEX_0FAE,
708 REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
709 REG_VEX_0F38F3,
710
711 REG_0FXOP_09_01_L_0,
712 REG_0FXOP_09_02_L_0,
713 REG_0FXOP_09_12_M_1_L_0,
714 REG_0FXOP_0A_12_L_0,
715
716 REG_EVEX_0F71,
717 REG_EVEX_0F72,
718 REG_EVEX_0F73,
719 REG_EVEX_0F38C6,
720 REG_EVEX_0F38C7
721 };
722
723 enum
724 {
725 MOD_8D = 0,
726 MOD_C6_REG_7,
727 MOD_C7_REG_7,
728 MOD_FF_REG_3,
729 MOD_FF_REG_5,
730 MOD_0F01_REG_0,
731 MOD_0F01_REG_1,
732 MOD_0F01_REG_2,
733 MOD_0F01_REG_3,
734 MOD_0F01_REG_5,
735 MOD_0F01_REG_7,
736 MOD_0F12_PREFIX_0,
737 MOD_0F12_PREFIX_2,
738 MOD_0F13,
739 MOD_0F16_PREFIX_0,
740 MOD_0F16_PREFIX_2,
741 MOD_0F17,
742 MOD_0F18_REG_0,
743 MOD_0F18_REG_1,
744 MOD_0F18_REG_2,
745 MOD_0F18_REG_3,
746 MOD_0F1A_PREFIX_0,
747 MOD_0F1B_PREFIX_0,
748 MOD_0F1B_PREFIX_1,
749 MOD_0F1C_PREFIX_0,
750 MOD_0F1E_PREFIX_1,
751 MOD_0F2B_PREFIX_0,
752 MOD_0F2B_PREFIX_1,
753 MOD_0F2B_PREFIX_2,
754 MOD_0F2B_PREFIX_3,
755 MOD_0F50,
756 MOD_0F71_REG_2,
757 MOD_0F71_REG_4,
758 MOD_0F71_REG_6,
759 MOD_0F72_REG_2,
760 MOD_0F72_REG_4,
761 MOD_0F72_REG_6,
762 MOD_0F73_REG_2,
763 MOD_0F73_REG_3,
764 MOD_0F73_REG_6,
765 MOD_0F73_REG_7,
766 MOD_0FAE_REG_0,
767 MOD_0FAE_REG_1,
768 MOD_0FAE_REG_2,
769 MOD_0FAE_REG_3,
770 MOD_0FAE_REG_4,
771 MOD_0FAE_REG_5,
772 MOD_0FAE_REG_6,
773 MOD_0FAE_REG_7,
774 MOD_0FB2,
775 MOD_0FB4,
776 MOD_0FB5,
777 MOD_0FC3,
778 MOD_0FC7_REG_3,
779 MOD_0FC7_REG_4,
780 MOD_0FC7_REG_5,
781 MOD_0FC7_REG_6,
782 MOD_0FC7_REG_7,
783 MOD_0FD7,
784 MOD_0FE7_PREFIX_2,
785 MOD_0FF0_PREFIX_3,
786 MOD_0F382A,
787 MOD_0F38DC_PREFIX_1,
788 MOD_0F38DD_PREFIX_1,
789 MOD_0F38DE_PREFIX_1,
790 MOD_0F38DF_PREFIX_1,
791 MOD_0F38F5,
792 MOD_0F38F6_PREFIX_0,
793 MOD_0F38F8_PREFIX_1,
794 MOD_0F38F8_PREFIX_2,
795 MOD_0F38F8_PREFIX_3,
796 MOD_0F38F9,
797 MOD_0F38FA_PREFIX_1,
798 MOD_0F38FB_PREFIX_1,
799 MOD_0F3A0F_PREFIX_1,
800 MOD_62_32BIT,
801 MOD_C4_32BIT,
802 MOD_C5_32BIT,
803 MOD_VEX_0F12_PREFIX_0,
804 MOD_VEX_0F12_PREFIX_2,
805 MOD_VEX_0F13,
806 MOD_VEX_0F16_PREFIX_0,
807 MOD_VEX_0F16_PREFIX_2,
808 MOD_VEX_0F17,
809 MOD_VEX_0F2B,
810 MOD_VEX_W_0_0F41_P_0_LEN_1,
811 MOD_VEX_W_1_0F41_P_0_LEN_1,
812 MOD_VEX_W_0_0F41_P_2_LEN_1,
813 MOD_VEX_W_1_0F41_P_2_LEN_1,
814 MOD_VEX_W_0_0F42_P_0_LEN_1,
815 MOD_VEX_W_1_0F42_P_0_LEN_1,
816 MOD_VEX_W_0_0F42_P_2_LEN_1,
817 MOD_VEX_W_1_0F42_P_2_LEN_1,
818 MOD_VEX_W_0_0F44_P_0_LEN_1,
819 MOD_VEX_W_1_0F44_P_0_LEN_1,
820 MOD_VEX_W_0_0F44_P_2_LEN_1,
821 MOD_VEX_W_1_0F44_P_2_LEN_1,
822 MOD_VEX_W_0_0F45_P_0_LEN_1,
823 MOD_VEX_W_1_0F45_P_0_LEN_1,
824 MOD_VEX_W_0_0F45_P_2_LEN_1,
825 MOD_VEX_W_1_0F45_P_2_LEN_1,
826 MOD_VEX_W_0_0F46_P_0_LEN_1,
827 MOD_VEX_W_1_0F46_P_0_LEN_1,
828 MOD_VEX_W_0_0F46_P_2_LEN_1,
829 MOD_VEX_W_1_0F46_P_2_LEN_1,
830 MOD_VEX_W_0_0F47_P_0_LEN_1,
831 MOD_VEX_W_1_0F47_P_0_LEN_1,
832 MOD_VEX_W_0_0F47_P_2_LEN_1,
833 MOD_VEX_W_1_0F47_P_2_LEN_1,
834 MOD_VEX_W_0_0F4A_P_0_LEN_1,
835 MOD_VEX_W_1_0F4A_P_0_LEN_1,
836 MOD_VEX_W_0_0F4A_P_2_LEN_1,
837 MOD_VEX_W_1_0F4A_P_2_LEN_1,
838 MOD_VEX_W_0_0F4B_P_0_LEN_1,
839 MOD_VEX_W_1_0F4B_P_0_LEN_1,
840 MOD_VEX_W_0_0F4B_P_2_LEN_1,
841 MOD_VEX_0F50,
842 MOD_VEX_0F71_REG_2,
843 MOD_VEX_0F71_REG_4,
844 MOD_VEX_0F71_REG_6,
845 MOD_VEX_0F72_REG_2,
846 MOD_VEX_0F72_REG_4,
847 MOD_VEX_0F72_REG_6,
848 MOD_VEX_0F73_REG_2,
849 MOD_VEX_0F73_REG_3,
850 MOD_VEX_0F73_REG_6,
851 MOD_VEX_0F73_REG_7,
852 MOD_VEX_W_0_0F91_P_0_LEN_0,
853 MOD_VEX_W_1_0F91_P_0_LEN_0,
854 MOD_VEX_W_0_0F91_P_2_LEN_0,
855 MOD_VEX_W_1_0F91_P_2_LEN_0,
856 MOD_VEX_W_0_0F92_P_0_LEN_0,
857 MOD_VEX_W_0_0F92_P_2_LEN_0,
858 MOD_VEX_0F92_P_3_LEN_0,
859 MOD_VEX_W_0_0F93_P_0_LEN_0,
860 MOD_VEX_W_0_0F93_P_2_LEN_0,
861 MOD_VEX_0F93_P_3_LEN_0,
862 MOD_VEX_W_0_0F98_P_0_LEN_0,
863 MOD_VEX_W_1_0F98_P_0_LEN_0,
864 MOD_VEX_W_0_0F98_P_2_LEN_0,
865 MOD_VEX_W_1_0F98_P_2_LEN_0,
866 MOD_VEX_W_0_0F99_P_0_LEN_0,
867 MOD_VEX_W_1_0F99_P_0_LEN_0,
868 MOD_VEX_W_0_0F99_P_2_LEN_0,
869 MOD_VEX_W_1_0F99_P_2_LEN_0,
870 MOD_VEX_0FAE_REG_2,
871 MOD_VEX_0FAE_REG_3,
872 MOD_VEX_0FD7,
873 MOD_VEX_0FE7,
874 MOD_VEX_0FF0_PREFIX_3,
875 MOD_VEX_0F381A,
876 MOD_VEX_0F382A,
877 MOD_VEX_0F382C,
878 MOD_VEX_0F382D,
879 MOD_VEX_0F382E,
880 MOD_VEX_0F382F,
881 MOD_VEX_0F3849_X86_64_P_0_W_0,
882 MOD_VEX_0F3849_X86_64_P_2_W_0,
883 MOD_VEX_0F3849_X86_64_P_3_W_0,
884 MOD_VEX_0F384B_X86_64_P_1_W_0,
885 MOD_VEX_0F384B_X86_64_P_2_W_0,
886 MOD_VEX_0F384B_X86_64_P_3_W_0,
887 MOD_VEX_0F385A,
888 MOD_VEX_0F385C_X86_64_P_1_W_0,
889 MOD_VEX_0F385E_X86_64_P_0_W_0,
890 MOD_VEX_0F385E_X86_64_P_1_W_0,
891 MOD_VEX_0F385E_X86_64_P_2_W_0,
892 MOD_VEX_0F385E_X86_64_P_3_W_0,
893 MOD_VEX_0F388C,
894 MOD_VEX_0F388E,
895 MOD_VEX_0F3A30_L_0,
896 MOD_VEX_0F3A31_L_0,
897 MOD_VEX_0F3A32_L_0,
898 MOD_VEX_0F3A33_L_0,
899
900 MOD_VEX_0FXOP_09_12,
901
902 MOD_EVEX_0F12_PREFIX_0,
903 MOD_EVEX_0F12_PREFIX_2,
904 MOD_EVEX_0F13,
905 MOD_EVEX_0F16_PREFIX_0,
906 MOD_EVEX_0F16_PREFIX_2,
907 MOD_EVEX_0F17,
908 MOD_EVEX_0F2B,
909 MOD_EVEX_0F381A_W_0,
910 MOD_EVEX_0F381A_W_1,
911 MOD_EVEX_0F381B_W_0,
912 MOD_EVEX_0F381B_W_1,
913 MOD_EVEX_0F3828_P_1,
914 MOD_EVEX_0F382A_P_1_W_1,
915 MOD_EVEX_0F3838_P_1,
916 MOD_EVEX_0F383A_P_1_W_0,
917 MOD_EVEX_0F385A_W_0,
918 MOD_EVEX_0F385A_W_1,
919 MOD_EVEX_0F385B_W_0,
920 MOD_EVEX_0F385B_W_1,
921 MOD_EVEX_0F387A_W_0,
922 MOD_EVEX_0F387B_W_0,
923 MOD_EVEX_0F387C,
924 MOD_EVEX_0F38C6_REG_1,
925 MOD_EVEX_0F38C6_REG_2,
926 MOD_EVEX_0F38C6_REG_5,
927 MOD_EVEX_0F38C6_REG_6,
928 MOD_EVEX_0F38C7_REG_1,
929 MOD_EVEX_0F38C7_REG_2,
930 MOD_EVEX_0F38C7_REG_5,
931 MOD_EVEX_0F38C7_REG_6
932 };
933
934 enum
935 {
936 RM_C6_REG_7 = 0,
937 RM_C7_REG_7,
938 RM_0F01_REG_0,
939 RM_0F01_REG_1,
940 RM_0F01_REG_2,
941 RM_0F01_REG_3,
942 RM_0F01_REG_5_MOD_3,
943 RM_0F01_REG_7_MOD_3,
944 RM_0F1E_P_1_MOD_3_REG_7,
945 RM_0F3A0F_P_1_MOD_3_REG_0,
946 RM_0FAE_REG_6_MOD_3_P_0,
947 RM_0FAE_REG_7_MOD_3,
948 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
949 };
950
951 enum
952 {
953 PREFIX_90 = 0,
954 PREFIX_0F01_REG_1_RM_4,
955 PREFIX_0F01_REG_1_RM_5,
956 PREFIX_0F01_REG_1_RM_6,
957 PREFIX_0F01_REG_1_RM_7,
958 PREFIX_0F01_REG_3_RM_1,
959 PREFIX_0F01_REG_5_MOD_0,
960 PREFIX_0F01_REG_5_MOD_3_RM_0,
961 PREFIX_0F01_REG_5_MOD_3_RM_1,
962 PREFIX_0F01_REG_5_MOD_3_RM_2,
963 PREFIX_0F01_REG_5_MOD_3_RM_4,
964 PREFIX_0F01_REG_5_MOD_3_RM_5,
965 PREFIX_0F01_REG_5_MOD_3_RM_6,
966 PREFIX_0F01_REG_5_MOD_3_RM_7,
967 PREFIX_0F01_REG_7_MOD_3_RM_2,
968 PREFIX_0F01_REG_7_MOD_3_RM_6,
969 PREFIX_0F01_REG_7_MOD_3_RM_7,
970 PREFIX_0F09,
971 PREFIX_0F10,
972 PREFIX_0F11,
973 PREFIX_0F12,
974 PREFIX_0F16,
975 PREFIX_0F1A,
976 PREFIX_0F1B,
977 PREFIX_0F1C,
978 PREFIX_0F1E,
979 PREFIX_0F2A,
980 PREFIX_0F2B,
981 PREFIX_0F2C,
982 PREFIX_0F2D,
983 PREFIX_0F2E,
984 PREFIX_0F2F,
985 PREFIX_0F51,
986 PREFIX_0F52,
987 PREFIX_0F53,
988 PREFIX_0F58,
989 PREFIX_0F59,
990 PREFIX_0F5A,
991 PREFIX_0F5B,
992 PREFIX_0F5C,
993 PREFIX_0F5D,
994 PREFIX_0F5E,
995 PREFIX_0F5F,
996 PREFIX_0F60,
997 PREFIX_0F61,
998 PREFIX_0F62,
999 PREFIX_0F6F,
1000 PREFIX_0F70,
1001 PREFIX_0F78,
1002 PREFIX_0F79,
1003 PREFIX_0F7C,
1004 PREFIX_0F7D,
1005 PREFIX_0F7E,
1006 PREFIX_0F7F,
1007 PREFIX_0FAE_REG_0_MOD_3,
1008 PREFIX_0FAE_REG_1_MOD_3,
1009 PREFIX_0FAE_REG_2_MOD_3,
1010 PREFIX_0FAE_REG_3_MOD_3,
1011 PREFIX_0FAE_REG_4_MOD_0,
1012 PREFIX_0FAE_REG_4_MOD_3,
1013 PREFIX_0FAE_REG_5_MOD_3,
1014 PREFIX_0FAE_REG_6_MOD_0,
1015 PREFIX_0FAE_REG_6_MOD_3,
1016 PREFIX_0FAE_REG_7_MOD_0,
1017 PREFIX_0FB8,
1018 PREFIX_0FBC,
1019 PREFIX_0FBD,
1020 PREFIX_0FC2,
1021 PREFIX_0FC7_REG_6_MOD_0,
1022 PREFIX_0FC7_REG_6_MOD_3,
1023 PREFIX_0FC7_REG_7_MOD_3,
1024 PREFIX_0FD0,
1025 PREFIX_0FD6,
1026 PREFIX_0FE6,
1027 PREFIX_0FE7,
1028 PREFIX_0FF0,
1029 PREFIX_0FF7,
1030 PREFIX_0F38D8,
1031 PREFIX_0F38DC,
1032 PREFIX_0F38DD,
1033 PREFIX_0F38DE,
1034 PREFIX_0F38DF,
1035 PREFIX_0F38F0,
1036 PREFIX_0F38F1,
1037 PREFIX_0F38F6,
1038 PREFIX_0F38F8,
1039 PREFIX_0F38FA,
1040 PREFIX_0F38FB,
1041 PREFIX_0F3A0F,
1042 PREFIX_VEX_0F10,
1043 PREFIX_VEX_0F11,
1044 PREFIX_VEX_0F12,
1045 PREFIX_VEX_0F16,
1046 PREFIX_VEX_0F2A,
1047 PREFIX_VEX_0F2C,
1048 PREFIX_VEX_0F2D,
1049 PREFIX_VEX_0F2E,
1050 PREFIX_VEX_0F2F,
1051 PREFIX_VEX_0F41,
1052 PREFIX_VEX_0F42,
1053 PREFIX_VEX_0F44,
1054 PREFIX_VEX_0F45,
1055 PREFIX_VEX_0F46,
1056 PREFIX_VEX_0F47,
1057 PREFIX_VEX_0F4A,
1058 PREFIX_VEX_0F4B,
1059 PREFIX_VEX_0F51,
1060 PREFIX_VEX_0F52,
1061 PREFIX_VEX_0F53,
1062 PREFIX_VEX_0F58,
1063 PREFIX_VEX_0F59,
1064 PREFIX_VEX_0F5A,
1065 PREFIX_VEX_0F5B,
1066 PREFIX_VEX_0F5C,
1067 PREFIX_VEX_0F5D,
1068 PREFIX_VEX_0F5E,
1069 PREFIX_VEX_0F5F,
1070 PREFIX_VEX_0F6F,
1071 PREFIX_VEX_0F70,
1072 PREFIX_VEX_0F7C,
1073 PREFIX_VEX_0F7D,
1074 PREFIX_VEX_0F7E,
1075 PREFIX_VEX_0F7F,
1076 PREFIX_VEX_0F90,
1077 PREFIX_VEX_0F91,
1078 PREFIX_VEX_0F92,
1079 PREFIX_VEX_0F93,
1080 PREFIX_VEX_0F98,
1081 PREFIX_VEX_0F99,
1082 PREFIX_VEX_0FC2,
1083 PREFIX_VEX_0FD0,
1084 PREFIX_VEX_0FE6,
1085 PREFIX_VEX_0FF0,
1086 PREFIX_VEX_0F3849_X86_64,
1087 PREFIX_VEX_0F384B_X86_64,
1088 PREFIX_VEX_0F385C_X86_64,
1089 PREFIX_VEX_0F385E_X86_64,
1090 PREFIX_VEX_0F38F5,
1091 PREFIX_VEX_0F38F6,
1092 PREFIX_VEX_0F38F7,
1093 PREFIX_VEX_0F3AF0,
1094
1095 PREFIX_EVEX_0F10,
1096 PREFIX_EVEX_0F11,
1097 PREFIX_EVEX_0F12,
1098 PREFIX_EVEX_0F16,
1099 PREFIX_EVEX_0F2A,
1100 PREFIX_EVEX_0F51,
1101 PREFIX_EVEX_0F58,
1102 PREFIX_EVEX_0F59,
1103 PREFIX_EVEX_0F5A,
1104 PREFIX_EVEX_0F5B,
1105 PREFIX_EVEX_0F5C,
1106 PREFIX_EVEX_0F5D,
1107 PREFIX_EVEX_0F5E,
1108 PREFIX_EVEX_0F5F,
1109 PREFIX_EVEX_0F6F,
1110 PREFIX_EVEX_0F70,
1111 PREFIX_EVEX_0F78,
1112 PREFIX_EVEX_0F79,
1113 PREFIX_EVEX_0F7A,
1114 PREFIX_EVEX_0F7B,
1115 PREFIX_EVEX_0F7E,
1116 PREFIX_EVEX_0F7F,
1117 PREFIX_EVEX_0FC2,
1118 PREFIX_EVEX_0FE6,
1119 PREFIX_EVEX_0F3810,
1120 PREFIX_EVEX_0F3811,
1121 PREFIX_EVEX_0F3812,
1122 PREFIX_EVEX_0F3813,
1123 PREFIX_EVEX_0F3814,
1124 PREFIX_EVEX_0F3815,
1125 PREFIX_EVEX_0F3820,
1126 PREFIX_EVEX_0F3821,
1127 PREFIX_EVEX_0F3822,
1128 PREFIX_EVEX_0F3823,
1129 PREFIX_EVEX_0F3824,
1130 PREFIX_EVEX_0F3825,
1131 PREFIX_EVEX_0F3826,
1132 PREFIX_EVEX_0F3827,
1133 PREFIX_EVEX_0F3828,
1134 PREFIX_EVEX_0F3829,
1135 PREFIX_EVEX_0F382A,
1136 PREFIX_EVEX_0F3830,
1137 PREFIX_EVEX_0F3831,
1138 PREFIX_EVEX_0F3832,
1139 PREFIX_EVEX_0F3833,
1140 PREFIX_EVEX_0F3834,
1141 PREFIX_EVEX_0F3835,
1142 PREFIX_EVEX_0F3838,
1143 PREFIX_EVEX_0F3839,
1144 PREFIX_EVEX_0F383A,
1145 PREFIX_EVEX_0F3852,
1146 PREFIX_EVEX_0F3853,
1147 PREFIX_EVEX_0F3868,
1148 PREFIX_EVEX_0F3872,
1149 PREFIX_EVEX_0F389A,
1150 PREFIX_EVEX_0F389B,
1151 PREFIX_EVEX_0F38AA,
1152 PREFIX_EVEX_0F38AB,
1153 };
1154
1155 enum
1156 {
1157 X86_64_06 = 0,
1158 X86_64_07,
1159 X86_64_0E,
1160 X86_64_16,
1161 X86_64_17,
1162 X86_64_1E,
1163 X86_64_1F,
1164 X86_64_27,
1165 X86_64_2F,
1166 X86_64_37,
1167 X86_64_3F,
1168 X86_64_60,
1169 X86_64_61,
1170 X86_64_62,
1171 X86_64_63,
1172 X86_64_6D,
1173 X86_64_6F,
1174 X86_64_82,
1175 X86_64_9A,
1176 X86_64_C2,
1177 X86_64_C3,
1178 X86_64_C4,
1179 X86_64_C5,
1180 X86_64_CE,
1181 X86_64_D4,
1182 X86_64_D5,
1183 X86_64_E8,
1184 X86_64_E9,
1185 X86_64_EA,
1186 X86_64_0F01_REG_0,
1187 X86_64_0F01_REG_1,
1188 X86_64_0F01_REG_1_RM_5_PREFIX_2,
1189 X86_64_0F01_REG_1_RM_6_PREFIX_2,
1190 X86_64_0F01_REG_1_RM_7_PREFIX_2,
1191 X86_64_0F01_REG_2,
1192 X86_64_0F01_REG_3,
1193 X86_64_0F24,
1194 X86_64_0F26,
1195 X86_64_VEX_0F3849,
1196 X86_64_VEX_0F384B,
1197 X86_64_VEX_0F385C,
1198 X86_64_VEX_0F385E,
1199 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1200 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1201 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1202 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1203 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1204 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1205 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1206 X86_64_0FC7_REG_6_MOD_3_PREFIX_1
1207 };
1208
1209 enum
1210 {
1211 THREE_BYTE_0F38 = 0,
1212 THREE_BYTE_0F3A
1213 };
1214
1215 enum
1216 {
1217 XOP_08 = 0,
1218 XOP_09,
1219 XOP_0A
1220 };
1221
1222 enum
1223 {
1224 VEX_0F = 0,
1225 VEX_0F38,
1226 VEX_0F3A
1227 };
1228
1229 enum
1230 {
1231 EVEX_0F = 0,
1232 EVEX_0F38,
1233 EVEX_0F3A
1234 };
1235
1236 enum
1237 {
1238 VEX_LEN_0F12_P_0_M_0 = 0,
1239 VEX_LEN_0F12_P_0_M_1,
1240 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1241 VEX_LEN_0F13_M_0,
1242 VEX_LEN_0F16_P_0_M_0,
1243 VEX_LEN_0F16_P_0_M_1,
1244 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1245 VEX_LEN_0F17_M_0,
1246 VEX_LEN_0F41_P_0,
1247 VEX_LEN_0F41_P_2,
1248 VEX_LEN_0F42_P_0,
1249 VEX_LEN_0F42_P_2,
1250 VEX_LEN_0F44_P_0,
1251 VEX_LEN_0F44_P_2,
1252 VEX_LEN_0F45_P_0,
1253 VEX_LEN_0F45_P_2,
1254 VEX_LEN_0F46_P_0,
1255 VEX_LEN_0F46_P_2,
1256 VEX_LEN_0F47_P_0,
1257 VEX_LEN_0F47_P_2,
1258 VEX_LEN_0F4A_P_0,
1259 VEX_LEN_0F4A_P_2,
1260 VEX_LEN_0F4B_P_0,
1261 VEX_LEN_0F4B_P_2,
1262 VEX_LEN_0F6E,
1263 VEX_LEN_0F77,
1264 VEX_LEN_0F7E_P_1,
1265 VEX_LEN_0F7E_P_2,
1266 VEX_LEN_0F90_P_0,
1267 VEX_LEN_0F90_P_2,
1268 VEX_LEN_0F91_P_0,
1269 VEX_LEN_0F91_P_2,
1270 VEX_LEN_0F92_P_0,
1271 VEX_LEN_0F92_P_2,
1272 VEX_LEN_0F92_P_3,
1273 VEX_LEN_0F93_P_0,
1274 VEX_LEN_0F93_P_2,
1275 VEX_LEN_0F93_P_3,
1276 VEX_LEN_0F98_P_0,
1277 VEX_LEN_0F98_P_2,
1278 VEX_LEN_0F99_P_0,
1279 VEX_LEN_0F99_P_2,
1280 VEX_LEN_0FAE_R_2_M_0,
1281 VEX_LEN_0FAE_R_3_M_0,
1282 VEX_LEN_0FC4,
1283 VEX_LEN_0FC5,
1284 VEX_LEN_0FD6,
1285 VEX_LEN_0FF7,
1286 VEX_LEN_0F3816,
1287 VEX_LEN_0F3819,
1288 VEX_LEN_0F381A_M_0,
1289 VEX_LEN_0F3836,
1290 VEX_LEN_0F3841,
1291 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1292 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1293 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1294 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1295 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1296 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1297 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1298 VEX_LEN_0F385A_M_0,
1299 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1300 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1301 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1302 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1303 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1304 VEX_LEN_0F38DB,
1305 VEX_LEN_0F38F2,
1306 VEX_LEN_0F38F3_R_1,
1307 VEX_LEN_0F38F3_R_2,
1308 VEX_LEN_0F38F3_R_3,
1309 VEX_LEN_0F38F5_P_0,
1310 VEX_LEN_0F38F5_P_1,
1311 VEX_LEN_0F38F5_P_3,
1312 VEX_LEN_0F38F6_P_3,
1313 VEX_LEN_0F38F7_P_0,
1314 VEX_LEN_0F38F7_P_1,
1315 VEX_LEN_0F38F7_P_2,
1316 VEX_LEN_0F38F7_P_3,
1317 VEX_LEN_0F3A00,
1318 VEX_LEN_0F3A01,
1319 VEX_LEN_0F3A06,
1320 VEX_LEN_0F3A14,
1321 VEX_LEN_0F3A15,
1322 VEX_LEN_0F3A16,
1323 VEX_LEN_0F3A17,
1324 VEX_LEN_0F3A18,
1325 VEX_LEN_0F3A19,
1326 VEX_LEN_0F3A20,
1327 VEX_LEN_0F3A21,
1328 VEX_LEN_0F3A22,
1329 VEX_LEN_0F3A30,
1330 VEX_LEN_0F3A31,
1331 VEX_LEN_0F3A32,
1332 VEX_LEN_0F3A33,
1333 VEX_LEN_0F3A38,
1334 VEX_LEN_0F3A39,
1335 VEX_LEN_0F3A41,
1336 VEX_LEN_0F3A46,
1337 VEX_LEN_0F3A60,
1338 VEX_LEN_0F3A61,
1339 VEX_LEN_0F3A62,
1340 VEX_LEN_0F3A63,
1341 VEX_LEN_0F3ADF,
1342 VEX_LEN_0F3AF0_P_3,
1343 VEX_LEN_0FXOP_08_85,
1344 VEX_LEN_0FXOP_08_86,
1345 VEX_LEN_0FXOP_08_87,
1346 VEX_LEN_0FXOP_08_8E,
1347 VEX_LEN_0FXOP_08_8F,
1348 VEX_LEN_0FXOP_08_95,
1349 VEX_LEN_0FXOP_08_96,
1350 VEX_LEN_0FXOP_08_97,
1351 VEX_LEN_0FXOP_08_9E,
1352 VEX_LEN_0FXOP_08_9F,
1353 VEX_LEN_0FXOP_08_A3,
1354 VEX_LEN_0FXOP_08_A6,
1355 VEX_LEN_0FXOP_08_B6,
1356 VEX_LEN_0FXOP_08_C0,
1357 VEX_LEN_0FXOP_08_C1,
1358 VEX_LEN_0FXOP_08_C2,
1359 VEX_LEN_0FXOP_08_C3,
1360 VEX_LEN_0FXOP_08_CC,
1361 VEX_LEN_0FXOP_08_CD,
1362 VEX_LEN_0FXOP_08_CE,
1363 VEX_LEN_0FXOP_08_CF,
1364 VEX_LEN_0FXOP_08_EC,
1365 VEX_LEN_0FXOP_08_ED,
1366 VEX_LEN_0FXOP_08_EE,
1367 VEX_LEN_0FXOP_08_EF,
1368 VEX_LEN_0FXOP_09_01,
1369 VEX_LEN_0FXOP_09_02,
1370 VEX_LEN_0FXOP_09_12_M_1,
1371 VEX_LEN_0FXOP_09_82_W_0,
1372 VEX_LEN_0FXOP_09_83_W_0,
1373 VEX_LEN_0FXOP_09_90,
1374 VEX_LEN_0FXOP_09_91,
1375 VEX_LEN_0FXOP_09_92,
1376 VEX_LEN_0FXOP_09_93,
1377 VEX_LEN_0FXOP_09_94,
1378 VEX_LEN_0FXOP_09_95,
1379 VEX_LEN_0FXOP_09_96,
1380 VEX_LEN_0FXOP_09_97,
1381 VEX_LEN_0FXOP_09_98,
1382 VEX_LEN_0FXOP_09_99,
1383 VEX_LEN_0FXOP_09_9A,
1384 VEX_LEN_0FXOP_09_9B,
1385 VEX_LEN_0FXOP_09_C1,
1386 VEX_LEN_0FXOP_09_C2,
1387 VEX_LEN_0FXOP_09_C3,
1388 VEX_LEN_0FXOP_09_C6,
1389 VEX_LEN_0FXOP_09_C7,
1390 VEX_LEN_0FXOP_09_CB,
1391 VEX_LEN_0FXOP_09_D1,
1392 VEX_LEN_0FXOP_09_D2,
1393 VEX_LEN_0FXOP_09_D3,
1394 VEX_LEN_0FXOP_09_D6,
1395 VEX_LEN_0FXOP_09_D7,
1396 VEX_LEN_0FXOP_09_DB,
1397 VEX_LEN_0FXOP_09_E1,
1398 VEX_LEN_0FXOP_09_E2,
1399 VEX_LEN_0FXOP_09_E3,
1400 VEX_LEN_0FXOP_0A_12,
1401 };
1402
1403 enum
1404 {
1405 EVEX_LEN_0F6E = 0,
1406 EVEX_LEN_0F7E_P_1,
1407 EVEX_LEN_0F7E_P_2,
1408 EVEX_LEN_0FC4,
1409 EVEX_LEN_0FC5,
1410 EVEX_LEN_0FD6,
1411 EVEX_LEN_0F3816,
1412 EVEX_LEN_0F3819_W_0,
1413 EVEX_LEN_0F3819_W_1,
1414 EVEX_LEN_0F381A_W_0_M_0,
1415 EVEX_LEN_0F381A_W_1_M_0,
1416 EVEX_LEN_0F381B_W_0_M_0,
1417 EVEX_LEN_0F381B_W_1_M_0,
1418 EVEX_LEN_0F3836,
1419 EVEX_LEN_0F385A_W_0_M_0,
1420 EVEX_LEN_0F385A_W_1_M_0,
1421 EVEX_LEN_0F385B_W_0_M_0,
1422 EVEX_LEN_0F385B_W_1_M_0,
1423 EVEX_LEN_0F38C6_R_1_M_0,
1424 EVEX_LEN_0F38C6_R_2_M_0,
1425 EVEX_LEN_0F38C6_R_5_M_0,
1426 EVEX_LEN_0F38C6_R_6_M_0,
1427 EVEX_LEN_0F38C7_R_1_M_0_W_0,
1428 EVEX_LEN_0F38C7_R_1_M_0_W_1,
1429 EVEX_LEN_0F38C7_R_2_M_0_W_0,
1430 EVEX_LEN_0F38C7_R_2_M_0_W_1,
1431 EVEX_LEN_0F38C7_R_5_M_0_W_0,
1432 EVEX_LEN_0F38C7_R_5_M_0_W_1,
1433 EVEX_LEN_0F38C7_R_6_M_0_W_0,
1434 EVEX_LEN_0F38C7_R_6_M_0_W_1,
1435 EVEX_LEN_0F3A00_W_1,
1436 EVEX_LEN_0F3A01_W_1,
1437 EVEX_LEN_0F3A14,
1438 EVEX_LEN_0F3A15,
1439 EVEX_LEN_0F3A16,
1440 EVEX_LEN_0F3A17,
1441 EVEX_LEN_0F3A18_W_0,
1442 EVEX_LEN_0F3A18_W_1,
1443 EVEX_LEN_0F3A19_W_0,
1444 EVEX_LEN_0F3A19_W_1,
1445 EVEX_LEN_0F3A1A_W_0,
1446 EVEX_LEN_0F3A1A_W_1,
1447 EVEX_LEN_0F3A1B_W_0,
1448 EVEX_LEN_0F3A1B_W_1,
1449 EVEX_LEN_0F3A20,
1450 EVEX_LEN_0F3A21_W_0,
1451 EVEX_LEN_0F3A22,
1452 EVEX_LEN_0F3A23_W_0,
1453 EVEX_LEN_0F3A23_W_1,
1454 EVEX_LEN_0F3A38_W_0,
1455 EVEX_LEN_0F3A38_W_1,
1456 EVEX_LEN_0F3A39_W_0,
1457 EVEX_LEN_0F3A39_W_1,
1458 EVEX_LEN_0F3A3A_W_0,
1459 EVEX_LEN_0F3A3A_W_1,
1460 EVEX_LEN_0F3A3B_W_0,
1461 EVEX_LEN_0F3A3B_W_1,
1462 EVEX_LEN_0F3A43_W_0,
1463 EVEX_LEN_0F3A43_W_1
1464 };
1465
1466 enum
1467 {
1468 VEX_W_0F41_P_0_LEN_1 = 0,
1469 VEX_W_0F41_P_2_LEN_1,
1470 VEX_W_0F42_P_0_LEN_1,
1471 VEX_W_0F42_P_2_LEN_1,
1472 VEX_W_0F44_P_0_LEN_0,
1473 VEX_W_0F44_P_2_LEN_0,
1474 VEX_W_0F45_P_0_LEN_1,
1475 VEX_W_0F45_P_2_LEN_1,
1476 VEX_W_0F46_P_0_LEN_1,
1477 VEX_W_0F46_P_2_LEN_1,
1478 VEX_W_0F47_P_0_LEN_1,
1479 VEX_W_0F47_P_2_LEN_1,
1480 VEX_W_0F4A_P_0_LEN_1,
1481 VEX_W_0F4A_P_2_LEN_1,
1482 VEX_W_0F4B_P_0_LEN_1,
1483 VEX_W_0F4B_P_2_LEN_1,
1484 VEX_W_0F90_P_0_LEN_0,
1485 VEX_W_0F90_P_2_LEN_0,
1486 VEX_W_0F91_P_0_LEN_0,
1487 VEX_W_0F91_P_2_LEN_0,
1488 VEX_W_0F92_P_0_LEN_0,
1489 VEX_W_0F92_P_2_LEN_0,
1490 VEX_W_0F93_P_0_LEN_0,
1491 VEX_W_0F93_P_2_LEN_0,
1492 VEX_W_0F98_P_0_LEN_0,
1493 VEX_W_0F98_P_2_LEN_0,
1494 VEX_W_0F99_P_0_LEN_0,
1495 VEX_W_0F99_P_2_LEN_0,
1496 VEX_W_0F380C,
1497 VEX_W_0F380D,
1498 VEX_W_0F380E,
1499 VEX_W_0F380F,
1500 VEX_W_0F3813,
1501 VEX_W_0F3816_L_1,
1502 VEX_W_0F3818,
1503 VEX_W_0F3819_L_1,
1504 VEX_W_0F381A_M_0_L_1,
1505 VEX_W_0F382C_M_0,
1506 VEX_W_0F382D_M_0,
1507 VEX_W_0F382E_M_0,
1508 VEX_W_0F382F_M_0,
1509 VEX_W_0F3836,
1510 VEX_W_0F3846,
1511 VEX_W_0F3849_X86_64_P_0,
1512 VEX_W_0F3849_X86_64_P_2,
1513 VEX_W_0F3849_X86_64_P_3,
1514 VEX_W_0F384B_X86_64_P_1,
1515 VEX_W_0F384B_X86_64_P_2,
1516 VEX_W_0F384B_X86_64_P_3,
1517 VEX_W_0F3850,
1518 VEX_W_0F3851,
1519 VEX_W_0F3852,
1520 VEX_W_0F3853,
1521 VEX_W_0F3858,
1522 VEX_W_0F3859,
1523 VEX_W_0F385A_M_0_L_0,
1524 VEX_W_0F385C_X86_64_P_1,
1525 VEX_W_0F385E_X86_64_P_0,
1526 VEX_W_0F385E_X86_64_P_1,
1527 VEX_W_0F385E_X86_64_P_2,
1528 VEX_W_0F385E_X86_64_P_3,
1529 VEX_W_0F3878,
1530 VEX_W_0F3879,
1531 VEX_W_0F38CF,
1532 VEX_W_0F3A00_L_1,
1533 VEX_W_0F3A01_L_1,
1534 VEX_W_0F3A02,
1535 VEX_W_0F3A04,
1536 VEX_W_0F3A05,
1537 VEX_W_0F3A06_L_1,
1538 VEX_W_0F3A18_L_1,
1539 VEX_W_0F3A19_L_1,
1540 VEX_W_0F3A1D,
1541 VEX_W_0F3A38_L_1,
1542 VEX_W_0F3A39_L_1,
1543 VEX_W_0F3A46_L_1,
1544 VEX_W_0F3A4A,
1545 VEX_W_0F3A4B,
1546 VEX_W_0F3A4C,
1547 VEX_W_0F3ACE,
1548 VEX_W_0F3ACF,
1549
1550 VEX_W_0FXOP_08_85_L_0,
1551 VEX_W_0FXOP_08_86_L_0,
1552 VEX_W_0FXOP_08_87_L_0,
1553 VEX_W_0FXOP_08_8E_L_0,
1554 VEX_W_0FXOP_08_8F_L_0,
1555 VEX_W_0FXOP_08_95_L_0,
1556 VEX_W_0FXOP_08_96_L_0,
1557 VEX_W_0FXOP_08_97_L_0,
1558 VEX_W_0FXOP_08_9E_L_0,
1559 VEX_W_0FXOP_08_9F_L_0,
1560 VEX_W_0FXOP_08_A6_L_0,
1561 VEX_W_0FXOP_08_B6_L_0,
1562 VEX_W_0FXOP_08_C0_L_0,
1563 VEX_W_0FXOP_08_C1_L_0,
1564 VEX_W_0FXOP_08_C2_L_0,
1565 VEX_W_0FXOP_08_C3_L_0,
1566 VEX_W_0FXOP_08_CC_L_0,
1567 VEX_W_0FXOP_08_CD_L_0,
1568 VEX_W_0FXOP_08_CE_L_0,
1569 VEX_W_0FXOP_08_CF_L_0,
1570 VEX_W_0FXOP_08_EC_L_0,
1571 VEX_W_0FXOP_08_ED_L_0,
1572 VEX_W_0FXOP_08_EE_L_0,
1573 VEX_W_0FXOP_08_EF_L_0,
1574
1575 VEX_W_0FXOP_09_80,
1576 VEX_W_0FXOP_09_81,
1577 VEX_W_0FXOP_09_82,
1578 VEX_W_0FXOP_09_83,
1579 VEX_W_0FXOP_09_C1_L_0,
1580 VEX_W_0FXOP_09_C2_L_0,
1581 VEX_W_0FXOP_09_C3_L_0,
1582 VEX_W_0FXOP_09_C6_L_0,
1583 VEX_W_0FXOP_09_C7_L_0,
1584 VEX_W_0FXOP_09_CB_L_0,
1585 VEX_W_0FXOP_09_D1_L_0,
1586 VEX_W_0FXOP_09_D2_L_0,
1587 VEX_W_0FXOP_09_D3_L_0,
1588 VEX_W_0FXOP_09_D6_L_0,
1589 VEX_W_0FXOP_09_D7_L_0,
1590 VEX_W_0FXOP_09_DB_L_0,
1591 VEX_W_0FXOP_09_E1_L_0,
1592 VEX_W_0FXOP_09_E2_L_0,
1593 VEX_W_0FXOP_09_E3_L_0,
1594
1595 EVEX_W_0F10_P_1,
1596 EVEX_W_0F10_P_3,
1597 EVEX_W_0F11_P_1,
1598 EVEX_W_0F11_P_3,
1599 EVEX_W_0F12_P_0_M_1,
1600 EVEX_W_0F12_P_1,
1601 EVEX_W_0F12_P_3,
1602 EVEX_W_0F16_P_0_M_1,
1603 EVEX_W_0F16_P_1,
1604 EVEX_W_0F2A_P_3,
1605 EVEX_W_0F51_P_1,
1606 EVEX_W_0F51_P_3,
1607 EVEX_W_0F58_P_1,
1608 EVEX_W_0F58_P_3,
1609 EVEX_W_0F59_P_1,
1610 EVEX_W_0F59_P_3,
1611 EVEX_W_0F5A_P_0,
1612 EVEX_W_0F5A_P_1,
1613 EVEX_W_0F5A_P_2,
1614 EVEX_W_0F5A_P_3,
1615 EVEX_W_0F5B_P_0,
1616 EVEX_W_0F5B_P_1,
1617 EVEX_W_0F5B_P_2,
1618 EVEX_W_0F5C_P_1,
1619 EVEX_W_0F5C_P_3,
1620 EVEX_W_0F5D_P_1,
1621 EVEX_W_0F5D_P_3,
1622 EVEX_W_0F5E_P_1,
1623 EVEX_W_0F5E_P_3,
1624 EVEX_W_0F5F_P_1,
1625 EVEX_W_0F5F_P_3,
1626 EVEX_W_0F62,
1627 EVEX_W_0F66,
1628 EVEX_W_0F6A,
1629 EVEX_W_0F6B,
1630 EVEX_W_0F6C,
1631 EVEX_W_0F6D,
1632 EVEX_W_0F6F_P_1,
1633 EVEX_W_0F6F_P_2,
1634 EVEX_W_0F6F_P_3,
1635 EVEX_W_0F70_P_2,
1636 EVEX_W_0F72_R_2,
1637 EVEX_W_0F72_R_6,
1638 EVEX_W_0F73_R_2,
1639 EVEX_W_0F73_R_6,
1640 EVEX_W_0F76,
1641 EVEX_W_0F78_P_0,
1642 EVEX_W_0F78_P_2,
1643 EVEX_W_0F79_P_0,
1644 EVEX_W_0F79_P_2,
1645 EVEX_W_0F7A_P_1,
1646 EVEX_W_0F7A_P_2,
1647 EVEX_W_0F7A_P_3,
1648 EVEX_W_0F7B_P_2,
1649 EVEX_W_0F7B_P_3,
1650 EVEX_W_0F7E_P_1,
1651 EVEX_W_0F7F_P_1,
1652 EVEX_W_0F7F_P_2,
1653 EVEX_W_0F7F_P_3,
1654 EVEX_W_0FC2_P_1,
1655 EVEX_W_0FC2_P_3,
1656 EVEX_W_0FD2,
1657 EVEX_W_0FD3,
1658 EVEX_W_0FD4,
1659 EVEX_W_0FD6_L_0,
1660 EVEX_W_0FE6_P_1,
1661 EVEX_W_0FE6_P_2,
1662 EVEX_W_0FE6_P_3,
1663 EVEX_W_0FE7,
1664 EVEX_W_0FF2,
1665 EVEX_W_0FF3,
1666 EVEX_W_0FF4,
1667 EVEX_W_0FFA,
1668 EVEX_W_0FFB,
1669 EVEX_W_0FFE,
1670 EVEX_W_0F380D,
1671 EVEX_W_0F3810_P_1,
1672 EVEX_W_0F3810_P_2,
1673 EVEX_W_0F3811_P_1,
1674 EVEX_W_0F3811_P_2,
1675 EVEX_W_0F3812_P_1,
1676 EVEX_W_0F3812_P_2,
1677 EVEX_W_0F3813_P_1,
1678 EVEX_W_0F3813_P_2,
1679 EVEX_W_0F3814_P_1,
1680 EVEX_W_0F3815_P_1,
1681 EVEX_W_0F3819,
1682 EVEX_W_0F381A,
1683 EVEX_W_0F381B,
1684 EVEX_W_0F381E,
1685 EVEX_W_0F381F,
1686 EVEX_W_0F3820_P_1,
1687 EVEX_W_0F3821_P_1,
1688 EVEX_W_0F3822_P_1,
1689 EVEX_W_0F3823_P_1,
1690 EVEX_W_0F3824_P_1,
1691 EVEX_W_0F3825_P_1,
1692 EVEX_W_0F3825_P_2,
1693 EVEX_W_0F3828_P_2,
1694 EVEX_W_0F3829_P_2,
1695 EVEX_W_0F382A_P_1,
1696 EVEX_W_0F382A_P_2,
1697 EVEX_W_0F382B,
1698 EVEX_W_0F3830_P_1,
1699 EVEX_W_0F3831_P_1,
1700 EVEX_W_0F3832_P_1,
1701 EVEX_W_0F3833_P_1,
1702 EVEX_W_0F3834_P_1,
1703 EVEX_W_0F3835_P_1,
1704 EVEX_W_0F3835_P_2,
1705 EVEX_W_0F3837,
1706 EVEX_W_0F383A_P_1,
1707 EVEX_W_0F3852_P_1,
1708 EVEX_W_0F3859,
1709 EVEX_W_0F385A,
1710 EVEX_W_0F385B,
1711 EVEX_W_0F3870,
1712 EVEX_W_0F3872_P_1,
1713 EVEX_W_0F3872_P_2,
1714 EVEX_W_0F3872_P_3,
1715 EVEX_W_0F387A,
1716 EVEX_W_0F387B,
1717 EVEX_W_0F3883,
1718 EVEX_W_0F3891,
1719 EVEX_W_0F3893,
1720 EVEX_W_0F38A1,
1721 EVEX_W_0F38A3,
1722 EVEX_W_0F38C7_R_1_M_0,
1723 EVEX_W_0F38C7_R_2_M_0,
1724 EVEX_W_0F38C7_R_5_M_0,
1725 EVEX_W_0F38C7_R_6_M_0,
1726
1727 EVEX_W_0F3A00,
1728 EVEX_W_0F3A01,
1729 EVEX_W_0F3A05,
1730 EVEX_W_0F3A08,
1731 EVEX_W_0F3A09,
1732 EVEX_W_0F3A0A,
1733 EVEX_W_0F3A0B,
1734 EVEX_W_0F3A18,
1735 EVEX_W_0F3A19,
1736 EVEX_W_0F3A1A,
1737 EVEX_W_0F3A1B,
1738 EVEX_W_0F3A21,
1739 EVEX_W_0F3A23,
1740 EVEX_W_0F3A38,
1741 EVEX_W_0F3A39,
1742 EVEX_W_0F3A3A,
1743 EVEX_W_0F3A3B,
1744 EVEX_W_0F3A42,
1745 EVEX_W_0F3A43,
1746 EVEX_W_0F3A70,
1747 EVEX_W_0F3A72,
1748 };
1749
1750 typedef void (*op_rtn) (int bytemode, int sizeflag);
1751
1752 struct dis386 {
1753 const char *name;
1754 struct
1755 {
1756 op_rtn rtn;
1757 int bytemode;
1758 } op[MAX_OPERANDS];
1759 unsigned int prefix_requirement;
1760 };
1761
1762 /* Upper case letters in the instruction names here are macros.
1763 'A' => print 'b' if no register operands or suffix_always is true
1764 'B' => print 'b' if suffix_always is true
1765 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1766 size prefix
1767 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1768 suffix_always is true
1769 'E' => print 'e' if 32-bit form of jcxz
1770 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1771 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1772 'H' => print ",pt" or ",pn" branch hint
1773 'I' unused.
1774 'J' unused.
1775 'K' => print 'd' or 'q' if rex prefix is present.
1776 'L' unused.
1777 'M' => print 'r' if intel_mnemonic is false.
1778 'N' => print 'n' if instruction has no wait "prefix"
1779 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1780 'P' => behave as 'T' except with register operand outside of suffix_always
1781 mode
1782 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1783 is true
1784 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1785 'S' => print 'w', 'l' or 'q' if suffix_always is true
1786 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1787 prefix or if suffix_always is true.
1788 'U' unused.
1789 'V' unused.
1790 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1791 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1792 'Y' unused.
1793 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1794 '!' => change condition from true to false or from false to true.
1795 '%' => add 1 upper case letter to the macro.
1796 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1797 prefix or suffix_always is true (lcall/ljmp).
1798 '@' => in 64bit mode for Intel64 ISA or if instruction
1799 has no operand sizing prefix, print 'q' if suffix_always is true or
1800 nothing otherwise; behave as 'P' in all other cases
1801
1802 2 upper case letter macros:
1803 "XY" => print 'x' or 'y' if suffix_always is true or no register
1804 operands and no broadcast.
1805 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1806 register operands and no broadcast.
1807 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1808 "XV" => print "{vex3}" pseudo prefix
1809 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1810 being false, or no operand at all in 64bit mode, or if suffix_always
1811 is true.
1812 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1813 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1814 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1815 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1816 "BW" => print 'b' or 'w' depending on the VEX.W bit
1817 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1818 an operand size prefix, or suffix_always is true. print
1819 'q' if rex prefix is present.
1820
1821 Many of the above letters print nothing in Intel mode. See "putop"
1822 for the details.
1823
1824 Braces '{' and '}', and vertical bars '|', indicate alternative
1825 mnemonic strings for AT&T and Intel. */
1826
1827 static const struct dis386 dis386[] = {
1828 /* 00 */
1829 { "addB", { Ebh1, Gb }, 0 },
1830 { "addS", { Evh1, Gv }, 0 },
1831 { "addB", { Gb, EbS }, 0 },
1832 { "addS", { Gv, EvS }, 0 },
1833 { "addB", { AL, Ib }, 0 },
1834 { "addS", { eAX, Iv }, 0 },
1835 { X86_64_TABLE (X86_64_06) },
1836 { X86_64_TABLE (X86_64_07) },
1837 /* 08 */
1838 { "orB", { Ebh1, Gb }, 0 },
1839 { "orS", { Evh1, Gv }, 0 },
1840 { "orB", { Gb, EbS }, 0 },
1841 { "orS", { Gv, EvS }, 0 },
1842 { "orB", { AL, Ib }, 0 },
1843 { "orS", { eAX, Iv }, 0 },
1844 { X86_64_TABLE (X86_64_0E) },
1845 { Bad_Opcode }, /* 0x0f extended opcode escape */
1846 /* 10 */
1847 { "adcB", { Ebh1, Gb }, 0 },
1848 { "adcS", { Evh1, Gv }, 0 },
1849 { "adcB", { Gb, EbS }, 0 },
1850 { "adcS", { Gv, EvS }, 0 },
1851 { "adcB", { AL, Ib }, 0 },
1852 { "adcS", { eAX, Iv }, 0 },
1853 { X86_64_TABLE (X86_64_16) },
1854 { X86_64_TABLE (X86_64_17) },
1855 /* 18 */
1856 { "sbbB", { Ebh1, Gb }, 0 },
1857 { "sbbS", { Evh1, Gv }, 0 },
1858 { "sbbB", { Gb, EbS }, 0 },
1859 { "sbbS", { Gv, EvS }, 0 },
1860 { "sbbB", { AL, Ib }, 0 },
1861 { "sbbS", { eAX, Iv }, 0 },
1862 { X86_64_TABLE (X86_64_1E) },
1863 { X86_64_TABLE (X86_64_1F) },
1864 /* 20 */
1865 { "andB", { Ebh1, Gb }, 0 },
1866 { "andS", { Evh1, Gv }, 0 },
1867 { "andB", { Gb, EbS }, 0 },
1868 { "andS", { Gv, EvS }, 0 },
1869 { "andB", { AL, Ib }, 0 },
1870 { "andS", { eAX, Iv }, 0 },
1871 { Bad_Opcode }, /* SEG ES prefix */
1872 { X86_64_TABLE (X86_64_27) },
1873 /* 28 */
1874 { "subB", { Ebh1, Gb }, 0 },
1875 { "subS", { Evh1, Gv }, 0 },
1876 { "subB", { Gb, EbS }, 0 },
1877 { "subS", { Gv, EvS }, 0 },
1878 { "subB", { AL, Ib }, 0 },
1879 { "subS", { eAX, Iv }, 0 },
1880 { Bad_Opcode }, /* SEG CS prefix */
1881 { X86_64_TABLE (X86_64_2F) },
1882 /* 30 */
1883 { "xorB", { Ebh1, Gb }, 0 },
1884 { "xorS", { Evh1, Gv }, 0 },
1885 { "xorB", { Gb, EbS }, 0 },
1886 { "xorS", { Gv, EvS }, 0 },
1887 { "xorB", { AL, Ib }, 0 },
1888 { "xorS", { eAX, Iv }, 0 },
1889 { Bad_Opcode }, /* SEG SS prefix */
1890 { X86_64_TABLE (X86_64_37) },
1891 /* 38 */
1892 { "cmpB", { Eb, Gb }, 0 },
1893 { "cmpS", { Ev, Gv }, 0 },
1894 { "cmpB", { Gb, EbS }, 0 },
1895 { "cmpS", { Gv, EvS }, 0 },
1896 { "cmpB", { AL, Ib }, 0 },
1897 { "cmpS", { eAX, Iv }, 0 },
1898 { Bad_Opcode }, /* SEG DS prefix */
1899 { X86_64_TABLE (X86_64_3F) },
1900 /* 40 */
1901 { "inc{S|}", { RMeAX }, 0 },
1902 { "inc{S|}", { RMeCX }, 0 },
1903 { "inc{S|}", { RMeDX }, 0 },
1904 { "inc{S|}", { RMeBX }, 0 },
1905 { "inc{S|}", { RMeSP }, 0 },
1906 { "inc{S|}", { RMeBP }, 0 },
1907 { "inc{S|}", { RMeSI }, 0 },
1908 { "inc{S|}", { RMeDI }, 0 },
1909 /* 48 */
1910 { "dec{S|}", { RMeAX }, 0 },
1911 { "dec{S|}", { RMeCX }, 0 },
1912 { "dec{S|}", { RMeDX }, 0 },
1913 { "dec{S|}", { RMeBX }, 0 },
1914 { "dec{S|}", { RMeSP }, 0 },
1915 { "dec{S|}", { RMeBP }, 0 },
1916 { "dec{S|}", { RMeSI }, 0 },
1917 { "dec{S|}", { RMeDI }, 0 },
1918 /* 50 */
1919 { "push{!P|}", { RMrAX }, 0 },
1920 { "push{!P|}", { RMrCX }, 0 },
1921 { "push{!P|}", { RMrDX }, 0 },
1922 { "push{!P|}", { RMrBX }, 0 },
1923 { "push{!P|}", { RMrSP }, 0 },
1924 { "push{!P|}", { RMrBP }, 0 },
1925 { "push{!P|}", { RMrSI }, 0 },
1926 { "push{!P|}", { RMrDI }, 0 },
1927 /* 58 */
1928 { "pop{!P|}", { RMrAX }, 0 },
1929 { "pop{!P|}", { RMrCX }, 0 },
1930 { "pop{!P|}", { RMrDX }, 0 },
1931 { "pop{!P|}", { RMrBX }, 0 },
1932 { "pop{!P|}", { RMrSP }, 0 },
1933 { "pop{!P|}", { RMrBP }, 0 },
1934 { "pop{!P|}", { RMrSI }, 0 },
1935 { "pop{!P|}", { RMrDI }, 0 },
1936 /* 60 */
1937 { X86_64_TABLE (X86_64_60) },
1938 { X86_64_TABLE (X86_64_61) },
1939 { X86_64_TABLE (X86_64_62) },
1940 { X86_64_TABLE (X86_64_63) },
1941 { Bad_Opcode }, /* seg fs */
1942 { Bad_Opcode }, /* seg gs */
1943 { Bad_Opcode }, /* op size prefix */
1944 { Bad_Opcode }, /* adr size prefix */
1945 /* 68 */
1946 { "pushP", { sIv }, 0 },
1947 { "imulS", { Gv, Ev, Iv }, 0 },
1948 { "pushP", { sIbT }, 0 },
1949 { "imulS", { Gv, Ev, sIb }, 0 },
1950 { "ins{b|}", { Ybr, indirDX }, 0 },
1951 { X86_64_TABLE (X86_64_6D) },
1952 { "outs{b|}", { indirDXr, Xb }, 0 },
1953 { X86_64_TABLE (X86_64_6F) },
1954 /* 70 */
1955 { "joH", { Jb, BND, cond_jump_flag }, 0 },
1956 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
1957 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
1958 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
1959 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
1960 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
1961 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
1962 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
1963 /* 78 */
1964 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
1965 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
1966 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
1967 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
1968 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
1969 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
1970 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
1971 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
1972 /* 80 */
1973 { REG_TABLE (REG_80) },
1974 { REG_TABLE (REG_81) },
1975 { X86_64_TABLE (X86_64_82) },
1976 { REG_TABLE (REG_83) },
1977 { "testB", { Eb, Gb }, 0 },
1978 { "testS", { Ev, Gv }, 0 },
1979 { "xchgB", { Ebh2, Gb }, 0 },
1980 { "xchgS", { Evh2, Gv }, 0 },
1981 /* 88 */
1982 { "movB", { Ebh3, Gb }, 0 },
1983 { "movS", { Evh3, Gv }, 0 },
1984 { "movB", { Gb, EbS }, 0 },
1985 { "movS", { Gv, EvS }, 0 },
1986 { "movD", { Sv, Sw }, 0 },
1987 { MOD_TABLE (MOD_8D) },
1988 { "movD", { Sw, Sv }, 0 },
1989 { REG_TABLE (REG_8F) },
1990 /* 90 */
1991 { PREFIX_TABLE (PREFIX_90) },
1992 { "xchgS", { RMeCX, eAX }, 0 },
1993 { "xchgS", { RMeDX, eAX }, 0 },
1994 { "xchgS", { RMeBX, eAX }, 0 },
1995 { "xchgS", { RMeSP, eAX }, 0 },
1996 { "xchgS", { RMeBP, eAX }, 0 },
1997 { "xchgS", { RMeSI, eAX }, 0 },
1998 { "xchgS", { RMeDI, eAX }, 0 },
1999 /* 98 */
2000 { "cW{t|}R", { XX }, 0 },
2001 { "cR{t|}O", { XX }, 0 },
2002 { X86_64_TABLE (X86_64_9A) },
2003 { Bad_Opcode }, /* fwait */
2004 { "pushfP", { XX }, 0 },
2005 { "popfP", { XX }, 0 },
2006 { "sahf", { XX }, 0 },
2007 { "lahf", { XX }, 0 },
2008 /* a0 */
2009 { "mov%LB", { AL, Ob }, 0 },
2010 { "mov%LS", { eAX, Ov }, 0 },
2011 { "mov%LB", { Ob, AL }, 0 },
2012 { "mov%LS", { Ov, eAX }, 0 },
2013 { "movs{b|}", { Ybr, Xb }, 0 },
2014 { "movs{R|}", { Yvr, Xv }, 0 },
2015 { "cmps{b|}", { Xb, Yb }, 0 },
2016 { "cmps{R|}", { Xv, Yv }, 0 },
2017 /* a8 */
2018 { "testB", { AL, Ib }, 0 },
2019 { "testS", { eAX, Iv }, 0 },
2020 { "stosB", { Ybr, AL }, 0 },
2021 { "stosS", { Yvr, eAX }, 0 },
2022 { "lodsB", { ALr, Xb }, 0 },
2023 { "lodsS", { eAXr, Xv }, 0 },
2024 { "scasB", { AL, Yb }, 0 },
2025 { "scasS", { eAX, Yv }, 0 },
2026 /* b0 */
2027 { "movB", { RMAL, Ib }, 0 },
2028 { "movB", { RMCL, Ib }, 0 },
2029 { "movB", { RMDL, Ib }, 0 },
2030 { "movB", { RMBL, Ib }, 0 },
2031 { "movB", { RMAH, Ib }, 0 },
2032 { "movB", { RMCH, Ib }, 0 },
2033 { "movB", { RMDH, Ib }, 0 },
2034 { "movB", { RMBH, Ib }, 0 },
2035 /* b8 */
2036 { "mov%LV", { RMeAX, Iv64 }, 0 },
2037 { "mov%LV", { RMeCX, Iv64 }, 0 },
2038 { "mov%LV", { RMeDX, Iv64 }, 0 },
2039 { "mov%LV", { RMeBX, Iv64 }, 0 },
2040 { "mov%LV", { RMeSP, Iv64 }, 0 },
2041 { "mov%LV", { RMeBP, Iv64 }, 0 },
2042 { "mov%LV", { RMeSI, Iv64 }, 0 },
2043 { "mov%LV", { RMeDI, Iv64 }, 0 },
2044 /* c0 */
2045 { REG_TABLE (REG_C0) },
2046 { REG_TABLE (REG_C1) },
2047 { X86_64_TABLE (X86_64_C2) },
2048 { X86_64_TABLE (X86_64_C3) },
2049 { X86_64_TABLE (X86_64_C4) },
2050 { X86_64_TABLE (X86_64_C5) },
2051 { REG_TABLE (REG_C6) },
2052 { REG_TABLE (REG_C7) },
2053 /* c8 */
2054 { "enterP", { Iw, Ib }, 0 },
2055 { "leaveP", { XX }, 0 },
2056 { "{l|}ret{|f}%LP", { Iw }, 0 },
2057 { "{l|}ret{|f}%LP", { XX }, 0 },
2058 { "int3", { XX }, 0 },
2059 { "int", { Ib }, 0 },
2060 { X86_64_TABLE (X86_64_CE) },
2061 { "iret%LP", { XX }, 0 },
2062 /* d0 */
2063 { REG_TABLE (REG_D0) },
2064 { REG_TABLE (REG_D1) },
2065 { REG_TABLE (REG_D2) },
2066 { REG_TABLE (REG_D3) },
2067 { X86_64_TABLE (X86_64_D4) },
2068 { X86_64_TABLE (X86_64_D5) },
2069 { Bad_Opcode },
2070 { "xlat", { DSBX }, 0 },
2071 /* d8 */
2072 { FLOAT },
2073 { FLOAT },
2074 { FLOAT },
2075 { FLOAT },
2076 { FLOAT },
2077 { FLOAT },
2078 { FLOAT },
2079 { FLOAT },
2080 /* e0 */
2081 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2082 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2083 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2084 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2085 { "inB", { AL, Ib }, 0 },
2086 { "inG", { zAX, Ib }, 0 },
2087 { "outB", { Ib, AL }, 0 },
2088 { "outG", { Ib, zAX }, 0 },
2089 /* e8 */
2090 { X86_64_TABLE (X86_64_E8) },
2091 { X86_64_TABLE (X86_64_E9) },
2092 { X86_64_TABLE (X86_64_EA) },
2093 { "jmp", { Jb, BND }, 0 },
2094 { "inB", { AL, indirDX }, 0 },
2095 { "inG", { zAX, indirDX }, 0 },
2096 { "outB", { indirDX, AL }, 0 },
2097 { "outG", { indirDX, zAX }, 0 },
2098 /* f0 */
2099 { Bad_Opcode }, /* lock prefix */
2100 { "icebp", { XX }, 0 },
2101 { Bad_Opcode }, /* repne */
2102 { Bad_Opcode }, /* repz */
2103 { "hlt", { XX }, 0 },
2104 { "cmc", { XX }, 0 },
2105 { REG_TABLE (REG_F6) },
2106 { REG_TABLE (REG_F7) },
2107 /* f8 */
2108 { "clc", { XX }, 0 },
2109 { "stc", { XX }, 0 },
2110 { "cli", { XX }, 0 },
2111 { "sti", { XX }, 0 },
2112 { "cld", { XX }, 0 },
2113 { "std", { XX }, 0 },
2114 { REG_TABLE (REG_FE) },
2115 { REG_TABLE (REG_FF) },
2116 };
2117
2118 static const struct dis386 dis386_twobyte[] = {
2119 /* 00 */
2120 { REG_TABLE (REG_0F00 ) },
2121 { REG_TABLE (REG_0F01 ) },
2122 { "larS", { Gv, Ew }, 0 },
2123 { "lslS", { Gv, Ew }, 0 },
2124 { Bad_Opcode },
2125 { "syscall", { XX }, 0 },
2126 { "clts", { XX }, 0 },
2127 { "sysret%LQ", { XX }, 0 },
2128 /* 08 */
2129 { "invd", { XX }, 0 },
2130 { PREFIX_TABLE (PREFIX_0F09) },
2131 { Bad_Opcode },
2132 { "ud2", { XX }, 0 },
2133 { Bad_Opcode },
2134 { REG_TABLE (REG_0F0D) },
2135 { "femms", { XX }, 0 },
2136 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2137 /* 10 */
2138 { PREFIX_TABLE (PREFIX_0F10) },
2139 { PREFIX_TABLE (PREFIX_0F11) },
2140 { PREFIX_TABLE (PREFIX_0F12) },
2141 { MOD_TABLE (MOD_0F13) },
2142 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2143 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2144 { PREFIX_TABLE (PREFIX_0F16) },
2145 { MOD_TABLE (MOD_0F17) },
2146 /* 18 */
2147 { REG_TABLE (REG_0F18) },
2148 { "nopQ", { Ev }, 0 },
2149 { PREFIX_TABLE (PREFIX_0F1A) },
2150 { PREFIX_TABLE (PREFIX_0F1B) },
2151 { PREFIX_TABLE (PREFIX_0F1C) },
2152 { "nopQ", { Ev }, 0 },
2153 { PREFIX_TABLE (PREFIX_0F1E) },
2154 { "nopQ", { Ev }, 0 },
2155 /* 20 */
2156 { "movZ", { Em, Cm }, 0 },
2157 { "movZ", { Em, Dm }, 0 },
2158 { "movZ", { Cm, Em }, 0 },
2159 { "movZ", { Dm, Em }, 0 },
2160 { X86_64_TABLE (X86_64_0F24) },
2161 { Bad_Opcode },
2162 { X86_64_TABLE (X86_64_0F26) },
2163 { Bad_Opcode },
2164 /* 28 */
2165 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2166 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2167 { PREFIX_TABLE (PREFIX_0F2A) },
2168 { PREFIX_TABLE (PREFIX_0F2B) },
2169 { PREFIX_TABLE (PREFIX_0F2C) },
2170 { PREFIX_TABLE (PREFIX_0F2D) },
2171 { PREFIX_TABLE (PREFIX_0F2E) },
2172 { PREFIX_TABLE (PREFIX_0F2F) },
2173 /* 30 */
2174 { "wrmsr", { XX }, 0 },
2175 { "rdtsc", { XX }, 0 },
2176 { "rdmsr", { XX }, 0 },
2177 { "rdpmc", { XX }, 0 },
2178 { "sysenter", { SEP }, 0 },
2179 { "sysexit%LQ", { SEP }, 0 },
2180 { Bad_Opcode },
2181 { "getsec", { XX }, 0 },
2182 /* 38 */
2183 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2184 { Bad_Opcode },
2185 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2186 { Bad_Opcode },
2187 { Bad_Opcode },
2188 { Bad_Opcode },
2189 { Bad_Opcode },
2190 { Bad_Opcode },
2191 /* 40 */
2192 { "cmovoS", { Gv, Ev }, 0 },
2193 { "cmovnoS", { Gv, Ev }, 0 },
2194 { "cmovbS", { Gv, Ev }, 0 },
2195 { "cmovaeS", { Gv, Ev }, 0 },
2196 { "cmoveS", { Gv, Ev }, 0 },
2197 { "cmovneS", { Gv, Ev }, 0 },
2198 { "cmovbeS", { Gv, Ev }, 0 },
2199 { "cmovaS", { Gv, Ev }, 0 },
2200 /* 48 */
2201 { "cmovsS", { Gv, Ev }, 0 },
2202 { "cmovnsS", { Gv, Ev }, 0 },
2203 { "cmovpS", { Gv, Ev }, 0 },
2204 { "cmovnpS", { Gv, Ev }, 0 },
2205 { "cmovlS", { Gv, Ev }, 0 },
2206 { "cmovgeS", { Gv, Ev }, 0 },
2207 { "cmovleS", { Gv, Ev }, 0 },
2208 { "cmovgS", { Gv, Ev }, 0 },
2209 /* 50 */
2210 { MOD_TABLE (MOD_0F50) },
2211 { PREFIX_TABLE (PREFIX_0F51) },
2212 { PREFIX_TABLE (PREFIX_0F52) },
2213 { PREFIX_TABLE (PREFIX_0F53) },
2214 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2215 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2216 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2217 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2218 /* 58 */
2219 { PREFIX_TABLE (PREFIX_0F58) },
2220 { PREFIX_TABLE (PREFIX_0F59) },
2221 { PREFIX_TABLE (PREFIX_0F5A) },
2222 { PREFIX_TABLE (PREFIX_0F5B) },
2223 { PREFIX_TABLE (PREFIX_0F5C) },
2224 { PREFIX_TABLE (PREFIX_0F5D) },
2225 { PREFIX_TABLE (PREFIX_0F5E) },
2226 { PREFIX_TABLE (PREFIX_0F5F) },
2227 /* 60 */
2228 { PREFIX_TABLE (PREFIX_0F60) },
2229 { PREFIX_TABLE (PREFIX_0F61) },
2230 { PREFIX_TABLE (PREFIX_0F62) },
2231 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2232 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2233 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2234 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2235 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2236 /* 68 */
2237 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2238 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2239 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2240 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2241 { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2242 { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2243 { "movK", { MX, Edq }, PREFIX_OPCODE },
2244 { PREFIX_TABLE (PREFIX_0F6F) },
2245 /* 70 */
2246 { PREFIX_TABLE (PREFIX_0F70) },
2247 { REG_TABLE (REG_0F71) },
2248 { REG_TABLE (REG_0F72) },
2249 { REG_TABLE (REG_0F73) },
2250 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2251 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2252 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2253 { "emms", { XX }, PREFIX_OPCODE },
2254 /* 78 */
2255 { PREFIX_TABLE (PREFIX_0F78) },
2256 { PREFIX_TABLE (PREFIX_0F79) },
2257 { Bad_Opcode },
2258 { Bad_Opcode },
2259 { PREFIX_TABLE (PREFIX_0F7C) },
2260 { PREFIX_TABLE (PREFIX_0F7D) },
2261 { PREFIX_TABLE (PREFIX_0F7E) },
2262 { PREFIX_TABLE (PREFIX_0F7F) },
2263 /* 80 */
2264 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2265 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2266 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2267 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2268 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2269 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2270 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2271 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2272 /* 88 */
2273 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2274 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2275 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2276 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2277 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2278 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2279 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2280 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2281 /* 90 */
2282 { "seto", { Eb }, 0 },
2283 { "setno", { Eb }, 0 },
2284 { "setb", { Eb }, 0 },
2285 { "setae", { Eb }, 0 },
2286 { "sete", { Eb }, 0 },
2287 { "setne", { Eb }, 0 },
2288 { "setbe", { Eb }, 0 },
2289 { "seta", { Eb }, 0 },
2290 /* 98 */
2291 { "sets", { Eb }, 0 },
2292 { "setns", { Eb }, 0 },
2293 { "setp", { Eb }, 0 },
2294 { "setnp", { Eb }, 0 },
2295 { "setl", { Eb }, 0 },
2296 { "setge", { Eb }, 0 },
2297 { "setle", { Eb }, 0 },
2298 { "setg", { Eb }, 0 },
2299 /* a0 */
2300 { "pushP", { fs }, 0 },
2301 { "popP", { fs }, 0 },
2302 { "cpuid", { XX }, 0 },
2303 { "btS", { Ev, Gv }, 0 },
2304 { "shldS", { Ev, Gv, Ib }, 0 },
2305 { "shldS", { Ev, Gv, CL }, 0 },
2306 { REG_TABLE (REG_0FA6) },
2307 { REG_TABLE (REG_0FA7) },
2308 /* a8 */
2309 { "pushP", { gs }, 0 },
2310 { "popP", { gs }, 0 },
2311 { "rsm", { XX }, 0 },
2312 { "btsS", { Evh1, Gv }, 0 },
2313 { "shrdS", { Ev, Gv, Ib }, 0 },
2314 { "shrdS", { Ev, Gv, CL }, 0 },
2315 { REG_TABLE (REG_0FAE) },
2316 { "imulS", { Gv, Ev }, 0 },
2317 /* b0 */
2318 { "cmpxchgB", { Ebh1, Gb }, 0 },
2319 { "cmpxchgS", { Evh1, Gv }, 0 },
2320 { MOD_TABLE (MOD_0FB2) },
2321 { "btrS", { Evh1, Gv }, 0 },
2322 { MOD_TABLE (MOD_0FB4) },
2323 { MOD_TABLE (MOD_0FB5) },
2324 { "movz{bR|x}", { Gv, Eb }, 0 },
2325 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2326 /* b8 */
2327 { PREFIX_TABLE (PREFIX_0FB8) },
2328 { "ud1S", { Gv, Ev }, 0 },
2329 { REG_TABLE (REG_0FBA) },
2330 { "btcS", { Evh1, Gv }, 0 },
2331 { PREFIX_TABLE (PREFIX_0FBC) },
2332 { PREFIX_TABLE (PREFIX_0FBD) },
2333 { "movs{bR|x}", { Gv, Eb }, 0 },
2334 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2335 /* c0 */
2336 { "xaddB", { Ebh1, Gb }, 0 },
2337 { "xaddS", { Evh1, Gv }, 0 },
2338 { PREFIX_TABLE (PREFIX_0FC2) },
2339 { MOD_TABLE (MOD_0FC3) },
2340 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
2341 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
2342 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2343 { REG_TABLE (REG_0FC7) },
2344 /* c8 */
2345 { "bswap", { RMeAX }, 0 },
2346 { "bswap", { RMeCX }, 0 },
2347 { "bswap", { RMeDX }, 0 },
2348 { "bswap", { RMeBX }, 0 },
2349 { "bswap", { RMeSP }, 0 },
2350 { "bswap", { RMeBP }, 0 },
2351 { "bswap", { RMeSI }, 0 },
2352 { "bswap", { RMeDI }, 0 },
2353 /* d0 */
2354 { PREFIX_TABLE (PREFIX_0FD0) },
2355 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2356 { "psrld", { MX, EM }, PREFIX_OPCODE },
2357 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2358 { "paddq", { MX, EM }, PREFIX_OPCODE },
2359 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2360 { PREFIX_TABLE (PREFIX_0FD6) },
2361 { MOD_TABLE (MOD_0FD7) },
2362 /* d8 */
2363 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2364 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2365 { "pminub", { MX, EM }, PREFIX_OPCODE },
2366 { "pand", { MX, EM }, PREFIX_OPCODE },
2367 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2368 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2369 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2370 { "pandn", { MX, EM }, PREFIX_OPCODE },
2371 /* e0 */
2372 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2373 { "psraw", { MX, EM }, PREFIX_OPCODE },
2374 { "psrad", { MX, EM }, PREFIX_OPCODE },
2375 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2376 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2377 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2378 { PREFIX_TABLE (PREFIX_0FE6) },
2379 { PREFIX_TABLE (PREFIX_0FE7) },
2380 /* e8 */
2381 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2382 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2383 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2384 { "por", { MX, EM }, PREFIX_OPCODE },
2385 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2386 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2387 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2388 { "pxor", { MX, EM }, PREFIX_OPCODE },
2389 /* f0 */
2390 { PREFIX_TABLE (PREFIX_0FF0) },
2391 { "psllw", { MX, EM }, PREFIX_OPCODE },
2392 { "pslld", { MX, EM }, PREFIX_OPCODE },
2393 { "psllq", { MX, EM }, PREFIX_OPCODE },
2394 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2395 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2396 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2397 { PREFIX_TABLE (PREFIX_0FF7) },
2398 /* f8 */
2399 { "psubb", { MX, EM }, PREFIX_OPCODE },
2400 { "psubw", { MX, EM }, PREFIX_OPCODE },
2401 { "psubd", { MX, EM }, PREFIX_OPCODE },
2402 { "psubq", { MX, EM }, PREFIX_OPCODE },
2403 { "paddb", { MX, EM }, PREFIX_OPCODE },
2404 { "paddw", { MX, EM }, PREFIX_OPCODE },
2405 { "paddd", { MX, EM }, PREFIX_OPCODE },
2406 { "ud0S", { Gv, Ev }, 0 },
2407 };
2408
2409 static const unsigned char onebyte_has_modrm[256] = {
2410 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2411 /* ------------------------------- */
2412 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2413 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2414 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2415 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2416 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2417 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2418 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2419 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2420 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2421 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2422 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2423 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2424 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2425 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2426 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2427 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2428 /* ------------------------------- */
2429 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2430 };
2431
2432 static const unsigned char twobyte_has_modrm[256] = {
2433 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2434 /* ------------------------------- */
2435 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2436 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2437 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2438 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2439 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2440 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2441 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2442 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2443 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2444 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2445 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2446 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2447 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2448 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2449 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2450 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2451 /* ------------------------------- */
2452 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2453 };
2454
2455 static char obuf[100];
2456 static char *obufp;
2457 static char *mnemonicendp;
2458 static char scratchbuf[100];
2459 static unsigned char *start_codep;
2460 static unsigned char *insn_codep;
2461 static unsigned char *codep;
2462 static unsigned char *end_codep;
2463 static int last_lock_prefix;
2464 static int last_repz_prefix;
2465 static int last_repnz_prefix;
2466 static int last_data_prefix;
2467 static int last_addr_prefix;
2468 static int last_rex_prefix;
2469 static int last_seg_prefix;
2470 static int fwait_prefix;
2471 /* The active segment register prefix. */
2472 static int active_seg_prefix;
2473 #define MAX_CODE_LENGTH 15
2474 /* We can up to 14 prefixes since the maximum instruction length is
2475 15bytes. */
2476 static int all_prefixes[MAX_CODE_LENGTH - 1];
2477 static disassemble_info *the_info;
2478 static struct
2479 {
2480 int mod;
2481 int reg;
2482 int rm;
2483 }
2484 modrm;
2485 static unsigned char need_modrm;
2486 static struct
2487 {
2488 int scale;
2489 int index;
2490 int base;
2491 }
2492 sib;
2493 static struct
2494 {
2495 int register_specifier;
2496 int length;
2497 int prefix;
2498 int w;
2499 int evex;
2500 int r;
2501 int v;
2502 int mask_register_specifier;
2503 int zeroing;
2504 int ll;
2505 int b;
2506 }
2507 vex;
2508 static unsigned char need_vex;
2509
2510 struct op
2511 {
2512 const char *name;
2513 unsigned int len;
2514 };
2515
2516 /* If we are accessing mod/rm/reg without need_modrm set, then the
2517 values are stale. Hitting this abort likely indicates that you
2518 need to update onebyte_has_modrm or twobyte_has_modrm. */
2519 #define MODRM_CHECK if (!need_modrm) abort ()
2520
2521 static const char **names64;
2522 static const char **names32;
2523 static const char **names16;
2524 static const char **names8;
2525 static const char **names8rex;
2526 static const char **names_seg;
2527 static const char *index64;
2528 static const char *index32;
2529 static const char **index16;
2530 static const char **names_bnd;
2531
2532 static const char *intel_names64[] = {
2533 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2534 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2535 };
2536 static const char *intel_names32[] = {
2537 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2538 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2539 };
2540 static const char *intel_names16[] = {
2541 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2542 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2543 };
2544 static const char *intel_names8[] = {
2545 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2546 };
2547 static const char *intel_names8rex[] = {
2548 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2549 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2550 };
2551 static const char *intel_names_seg[] = {
2552 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2553 };
2554 static const char *intel_index64 = "riz";
2555 static const char *intel_index32 = "eiz";
2556 static const char *intel_index16[] = {
2557 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2558 };
2559
2560 static const char *att_names64[] = {
2561 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2562 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2563 };
2564 static const char *att_names32[] = {
2565 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2566 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2567 };
2568 static const char *att_names16[] = {
2569 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2570 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2571 };
2572 static const char *att_names8[] = {
2573 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2574 };
2575 static const char *att_names8rex[] = {
2576 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2577 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2578 };
2579 static const char *att_names_seg[] = {
2580 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2581 };
2582 static const char *att_index64 = "%riz";
2583 static const char *att_index32 = "%eiz";
2584 static const char *att_index16[] = {
2585 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2586 };
2587
2588 static const char **names_mm;
2589 static const char *intel_names_mm[] = {
2590 "mm0", "mm1", "mm2", "mm3",
2591 "mm4", "mm5", "mm6", "mm7"
2592 };
2593 static const char *att_names_mm[] = {
2594 "%mm0", "%mm1", "%mm2", "%mm3",
2595 "%mm4", "%mm5", "%mm6", "%mm7"
2596 };
2597
2598 static const char *intel_names_bnd[] = {
2599 "bnd0", "bnd1", "bnd2", "bnd3"
2600 };
2601
2602 static const char *att_names_bnd[] = {
2603 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2604 };
2605
2606 static const char **names_xmm;
2607 static const char *intel_names_xmm[] = {
2608 "xmm0", "xmm1", "xmm2", "xmm3",
2609 "xmm4", "xmm5", "xmm6", "xmm7",
2610 "xmm8", "xmm9", "xmm10", "xmm11",
2611 "xmm12", "xmm13", "xmm14", "xmm15",
2612 "xmm16", "xmm17", "xmm18", "xmm19",
2613 "xmm20", "xmm21", "xmm22", "xmm23",
2614 "xmm24", "xmm25", "xmm26", "xmm27",
2615 "xmm28", "xmm29", "xmm30", "xmm31"
2616 };
2617 static const char *att_names_xmm[] = {
2618 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2619 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2620 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2621 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2622 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2623 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2624 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2625 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2626 };
2627
2628 static const char **names_ymm;
2629 static const char *intel_names_ymm[] = {
2630 "ymm0", "ymm1", "ymm2", "ymm3",
2631 "ymm4", "ymm5", "ymm6", "ymm7",
2632 "ymm8", "ymm9", "ymm10", "ymm11",
2633 "ymm12", "ymm13", "ymm14", "ymm15",
2634 "ymm16", "ymm17", "ymm18", "ymm19",
2635 "ymm20", "ymm21", "ymm22", "ymm23",
2636 "ymm24", "ymm25", "ymm26", "ymm27",
2637 "ymm28", "ymm29", "ymm30", "ymm31"
2638 };
2639 static const char *att_names_ymm[] = {
2640 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2641 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2642 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2643 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2644 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2645 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2646 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2647 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2648 };
2649
2650 static const char **names_zmm;
2651 static const char *intel_names_zmm[] = {
2652 "zmm0", "zmm1", "zmm2", "zmm3",
2653 "zmm4", "zmm5", "zmm6", "zmm7",
2654 "zmm8", "zmm9", "zmm10", "zmm11",
2655 "zmm12", "zmm13", "zmm14", "zmm15",
2656 "zmm16", "zmm17", "zmm18", "zmm19",
2657 "zmm20", "zmm21", "zmm22", "zmm23",
2658 "zmm24", "zmm25", "zmm26", "zmm27",
2659 "zmm28", "zmm29", "zmm30", "zmm31"
2660 };
2661 static const char *att_names_zmm[] = {
2662 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2663 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2664 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2665 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2666 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2667 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2668 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2669 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2670 };
2671
2672 static const char **names_tmm;
2673 static const char *intel_names_tmm[] = {
2674 "tmm0", "tmm1", "tmm2", "tmm3",
2675 "tmm4", "tmm5", "tmm6", "tmm7"
2676 };
2677 static const char *att_names_tmm[] = {
2678 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2679 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2680 };
2681
2682 static const char **names_mask;
2683 static const char *intel_names_mask[] = {
2684 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2685 };
2686 static const char *att_names_mask[] = {
2687 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2688 };
2689
2690 static const char *names_rounding[] =
2691 {
2692 "{rn-sae}",
2693 "{rd-sae}",
2694 "{ru-sae}",
2695 "{rz-sae}"
2696 };
2697
2698 static const struct dis386 reg_table[][8] = {
2699 /* REG_80 */
2700 {
2701 { "addA", { Ebh1, Ib }, 0 },
2702 { "orA", { Ebh1, Ib }, 0 },
2703 { "adcA", { Ebh1, Ib }, 0 },
2704 { "sbbA", { Ebh1, Ib }, 0 },
2705 { "andA", { Ebh1, Ib }, 0 },
2706 { "subA", { Ebh1, Ib }, 0 },
2707 { "xorA", { Ebh1, Ib }, 0 },
2708 { "cmpA", { Eb, Ib }, 0 },
2709 },
2710 /* REG_81 */
2711 {
2712 { "addQ", { Evh1, Iv }, 0 },
2713 { "orQ", { Evh1, Iv }, 0 },
2714 { "adcQ", { Evh1, Iv }, 0 },
2715 { "sbbQ", { Evh1, Iv }, 0 },
2716 { "andQ", { Evh1, Iv }, 0 },
2717 { "subQ", { Evh1, Iv }, 0 },
2718 { "xorQ", { Evh1, Iv }, 0 },
2719 { "cmpQ", { Ev, Iv }, 0 },
2720 },
2721 /* REG_83 */
2722 {
2723 { "addQ", { Evh1, sIb }, 0 },
2724 { "orQ", { Evh1, sIb }, 0 },
2725 { "adcQ", { Evh1, sIb }, 0 },
2726 { "sbbQ", { Evh1, sIb }, 0 },
2727 { "andQ", { Evh1, sIb }, 0 },
2728 { "subQ", { Evh1, sIb }, 0 },
2729 { "xorQ", { Evh1, sIb }, 0 },
2730 { "cmpQ", { Ev, sIb }, 0 },
2731 },
2732 /* REG_8F */
2733 {
2734 { "pop{P|}", { stackEv }, 0 },
2735 { XOP_8F_TABLE (XOP_09) },
2736 { Bad_Opcode },
2737 { Bad_Opcode },
2738 { Bad_Opcode },
2739 { XOP_8F_TABLE (XOP_09) },
2740 },
2741 /* REG_C0 */
2742 {
2743 { "rolA", { Eb, Ib }, 0 },
2744 { "rorA", { Eb, Ib }, 0 },
2745 { "rclA", { Eb, Ib }, 0 },
2746 { "rcrA", { Eb, Ib }, 0 },
2747 { "shlA", { Eb, Ib }, 0 },
2748 { "shrA", { Eb, Ib }, 0 },
2749 { "shlA", { Eb, Ib }, 0 },
2750 { "sarA", { Eb, Ib }, 0 },
2751 },
2752 /* REG_C1 */
2753 {
2754 { "rolQ", { Ev, Ib }, 0 },
2755 { "rorQ", { Ev, Ib }, 0 },
2756 { "rclQ", { Ev, Ib }, 0 },
2757 { "rcrQ", { Ev, Ib }, 0 },
2758 { "shlQ", { Ev, Ib }, 0 },
2759 { "shrQ", { Ev, Ib }, 0 },
2760 { "shlQ", { Ev, Ib }, 0 },
2761 { "sarQ", { Ev, Ib }, 0 },
2762 },
2763 /* REG_C6 */
2764 {
2765 { "movA", { Ebh3, Ib }, 0 },
2766 { Bad_Opcode },
2767 { Bad_Opcode },
2768 { Bad_Opcode },
2769 { Bad_Opcode },
2770 { Bad_Opcode },
2771 { Bad_Opcode },
2772 { MOD_TABLE (MOD_C6_REG_7) },
2773 },
2774 /* REG_C7 */
2775 {
2776 { "movQ", { Evh3, Iv }, 0 },
2777 { Bad_Opcode },
2778 { Bad_Opcode },
2779 { Bad_Opcode },
2780 { Bad_Opcode },
2781 { Bad_Opcode },
2782 { Bad_Opcode },
2783 { MOD_TABLE (MOD_C7_REG_7) },
2784 },
2785 /* REG_D0 */
2786 {
2787 { "rolA", { Eb, I1 }, 0 },
2788 { "rorA", { Eb, I1 }, 0 },
2789 { "rclA", { Eb, I1 }, 0 },
2790 { "rcrA", { Eb, I1 }, 0 },
2791 { "shlA", { Eb, I1 }, 0 },
2792 { "shrA", { Eb, I1 }, 0 },
2793 { "shlA", { Eb, I1 }, 0 },
2794 { "sarA", { Eb, I1 }, 0 },
2795 },
2796 /* REG_D1 */
2797 {
2798 { "rolQ", { Ev, I1 }, 0 },
2799 { "rorQ", { Ev, I1 }, 0 },
2800 { "rclQ", { Ev, I1 }, 0 },
2801 { "rcrQ", { Ev, I1 }, 0 },
2802 { "shlQ", { Ev, I1 }, 0 },
2803 { "shrQ", { Ev, I1 }, 0 },
2804 { "shlQ", { Ev, I1 }, 0 },
2805 { "sarQ", { Ev, I1 }, 0 },
2806 },
2807 /* REG_D2 */
2808 {
2809 { "rolA", { Eb, CL }, 0 },
2810 { "rorA", { Eb, CL }, 0 },
2811 { "rclA", { Eb, CL }, 0 },
2812 { "rcrA", { Eb, CL }, 0 },
2813 { "shlA", { Eb, CL }, 0 },
2814 { "shrA", { Eb, CL }, 0 },
2815 { "shlA", { Eb, CL }, 0 },
2816 { "sarA", { Eb, CL }, 0 },
2817 },
2818 /* REG_D3 */
2819 {
2820 { "rolQ", { Ev, CL }, 0 },
2821 { "rorQ", { Ev, CL }, 0 },
2822 { "rclQ", { Ev, CL }, 0 },
2823 { "rcrQ", { Ev, CL }, 0 },
2824 { "shlQ", { Ev, CL }, 0 },
2825 { "shrQ", { Ev, CL }, 0 },
2826 { "shlQ", { Ev, CL }, 0 },
2827 { "sarQ", { Ev, CL }, 0 },
2828 },
2829 /* REG_F6 */
2830 {
2831 { "testA", { Eb, Ib }, 0 },
2832 { "testA", { Eb, Ib }, 0 },
2833 { "notA", { Ebh1 }, 0 },
2834 { "negA", { Ebh1 }, 0 },
2835 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
2836 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
2837 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
2838 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
2839 },
2840 /* REG_F7 */
2841 {
2842 { "testQ", { Ev, Iv }, 0 },
2843 { "testQ", { Ev, Iv }, 0 },
2844 { "notQ", { Evh1 }, 0 },
2845 { "negQ", { Evh1 }, 0 },
2846 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
2847 { "imulQ", { Ev }, 0 },
2848 { "divQ", { Ev }, 0 },
2849 { "idivQ", { Ev }, 0 },
2850 },
2851 /* REG_FE */
2852 {
2853 { "incA", { Ebh1 }, 0 },
2854 { "decA", { Ebh1 }, 0 },
2855 },
2856 /* REG_FF */
2857 {
2858 { "incQ", { Evh1 }, 0 },
2859 { "decQ", { Evh1 }, 0 },
2860 { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2861 { MOD_TABLE (MOD_FF_REG_3) },
2862 { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2863 { MOD_TABLE (MOD_FF_REG_5) },
2864 { "push{P|}", { stackEv }, 0 },
2865 { Bad_Opcode },
2866 },
2867 /* REG_0F00 */
2868 {
2869 { "sldtD", { Sv }, 0 },
2870 { "strD", { Sv }, 0 },
2871 { "lldt", { Ew }, 0 },
2872 { "ltr", { Ew }, 0 },
2873 { "verr", { Ew }, 0 },
2874 { "verw", { Ew }, 0 },
2875 { Bad_Opcode },
2876 { Bad_Opcode },
2877 },
2878 /* REG_0F01 */
2879 {
2880 { MOD_TABLE (MOD_0F01_REG_0) },
2881 { MOD_TABLE (MOD_0F01_REG_1) },
2882 { MOD_TABLE (MOD_0F01_REG_2) },
2883 { MOD_TABLE (MOD_0F01_REG_3) },
2884 { "smswD", { Sv }, 0 },
2885 { MOD_TABLE (MOD_0F01_REG_5) },
2886 { "lmsw", { Ew }, 0 },
2887 { MOD_TABLE (MOD_0F01_REG_7) },
2888 },
2889 /* REG_0F0D */
2890 {
2891 { "prefetch", { Mb }, 0 },
2892 { "prefetchw", { Mb }, 0 },
2893 { "prefetchwt1", { Mb }, 0 },
2894 { "prefetch", { Mb }, 0 },
2895 { "prefetch", { Mb }, 0 },
2896 { "prefetch", { Mb }, 0 },
2897 { "prefetch", { Mb }, 0 },
2898 { "prefetch", { Mb }, 0 },
2899 },
2900 /* REG_0F18 */
2901 {
2902 { MOD_TABLE (MOD_0F18_REG_0) },
2903 { MOD_TABLE (MOD_0F18_REG_1) },
2904 { MOD_TABLE (MOD_0F18_REG_2) },
2905 { MOD_TABLE (MOD_0F18_REG_3) },
2906 { "nopQ", { Ev }, 0 },
2907 { "nopQ", { Ev }, 0 },
2908 { "nopQ", { Ev }, 0 },
2909 { "nopQ", { Ev }, 0 },
2910 },
2911 /* REG_0F1C_P_0_MOD_0 */
2912 {
2913 { "cldemote", { Mb }, 0 },
2914 { "nopQ", { Ev }, 0 },
2915 { "nopQ", { Ev }, 0 },
2916 { "nopQ", { Ev }, 0 },
2917 { "nopQ", { Ev }, 0 },
2918 { "nopQ", { Ev }, 0 },
2919 { "nopQ", { Ev }, 0 },
2920 { "nopQ", { Ev }, 0 },
2921 },
2922 /* REG_0F1E_P_1_MOD_3 */
2923 {
2924 { "nopQ", { Ev }, PREFIX_IGNORED },
2925 { "rdsspK", { Edq }, 0 },
2926 { "nopQ", { Ev }, PREFIX_IGNORED },
2927 { "nopQ", { Ev }, PREFIX_IGNORED },
2928 { "nopQ", { Ev }, PREFIX_IGNORED },
2929 { "nopQ", { Ev }, PREFIX_IGNORED },
2930 { "nopQ", { Ev }, PREFIX_IGNORED },
2931 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2932 },
2933 /* REG_0F38D8_PREFIX_1 */
2934 {
2935 { "aesencwide128kl", { M }, 0 },
2936 { "aesdecwide128kl", { M }, 0 },
2937 { "aesencwide256kl", { M }, 0 },
2938 { "aesdecwide256kl", { M }, 0 },
2939 },
2940 /* REG_0F3A0F_PREFIX_1_MOD_3 */
2941 {
2942 { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2943 },
2944 /* REG_0F71 */
2945 {
2946 { Bad_Opcode },
2947 { Bad_Opcode },
2948 { MOD_TABLE (MOD_0F71_REG_2) },
2949 { Bad_Opcode },
2950 { MOD_TABLE (MOD_0F71_REG_4) },
2951 { Bad_Opcode },
2952 { MOD_TABLE (MOD_0F71_REG_6) },
2953 },
2954 /* REG_0F72 */
2955 {
2956 { Bad_Opcode },
2957 { Bad_Opcode },
2958 { MOD_TABLE (MOD_0F72_REG_2) },
2959 { Bad_Opcode },
2960 { MOD_TABLE (MOD_0F72_REG_4) },
2961 { Bad_Opcode },
2962 { MOD_TABLE (MOD_0F72_REG_6) },
2963 },
2964 /* REG_0F73 */
2965 {
2966 { Bad_Opcode },
2967 { Bad_Opcode },
2968 { MOD_TABLE (MOD_0F73_REG_2) },
2969 { MOD_TABLE (MOD_0F73_REG_3) },
2970 { Bad_Opcode },
2971 { Bad_Opcode },
2972 { MOD_TABLE (MOD_0F73_REG_6) },
2973 { MOD_TABLE (MOD_0F73_REG_7) },
2974 },
2975 /* REG_0FA6 */
2976 {
2977 { "montmul", { { OP_0f07, 0 } }, 0 },
2978 { "xsha1", { { OP_0f07, 0 } }, 0 },
2979 { "xsha256", { { OP_0f07, 0 } }, 0 },
2980 },
2981 /* REG_0FA7 */
2982 {
2983 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2984 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2985 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2986 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2987 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2988 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2989 },
2990 /* REG_0FAE */
2991 {
2992 { MOD_TABLE (MOD_0FAE_REG_0) },
2993 { MOD_TABLE (MOD_0FAE_REG_1) },
2994 { MOD_TABLE (MOD_0FAE_REG_2) },
2995 { MOD_TABLE (MOD_0FAE_REG_3) },
2996 { MOD_TABLE (MOD_0FAE_REG_4) },
2997 { MOD_TABLE (MOD_0FAE_REG_5) },
2998 { MOD_TABLE (MOD_0FAE_REG_6) },
2999 { MOD_TABLE (MOD_0FAE_REG_7) },
3000 },
3001 /* REG_0FBA */
3002 {
3003 { Bad_Opcode },
3004 { Bad_Opcode },
3005 { Bad_Opcode },
3006 { Bad_Opcode },
3007 { "btQ", { Ev, Ib }, 0 },
3008 { "btsQ", { Evh1, Ib }, 0 },
3009 { "btrQ", { Evh1, Ib }, 0 },
3010 { "btcQ", { Evh1, Ib }, 0 },
3011 },
3012 /* REG_0FC7 */
3013 {
3014 { Bad_Opcode },
3015 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3016 { Bad_Opcode },
3017 { MOD_TABLE (MOD_0FC7_REG_3) },
3018 { MOD_TABLE (MOD_0FC7_REG_4) },
3019 { MOD_TABLE (MOD_0FC7_REG_5) },
3020 { MOD_TABLE (MOD_0FC7_REG_6) },
3021 { MOD_TABLE (MOD_0FC7_REG_7) },
3022 },
3023 /* REG_VEX_0F71 */
3024 {
3025 { Bad_Opcode },
3026 { Bad_Opcode },
3027 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3028 { Bad_Opcode },
3029 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3030 { Bad_Opcode },
3031 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3032 },
3033 /* REG_VEX_0F72 */
3034 {
3035 { Bad_Opcode },
3036 { Bad_Opcode },
3037 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3038 { Bad_Opcode },
3039 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3040 { Bad_Opcode },
3041 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3042 },
3043 /* REG_VEX_0F73 */
3044 {
3045 { Bad_Opcode },
3046 { Bad_Opcode },
3047 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3048 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3049 { Bad_Opcode },
3050 { Bad_Opcode },
3051 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3052 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3053 },
3054 /* REG_VEX_0FAE */
3055 {
3056 { Bad_Opcode },
3057 { Bad_Opcode },
3058 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3059 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3060 },
3061 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3062 {
3063 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
3064 },
3065 /* REG_VEX_0F38F3 */
3066 {
3067 { Bad_Opcode },
3068 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1) },
3069 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2) },
3070 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3) },
3071 },
3072 /* REG_0FXOP_09_01_L_0 */
3073 {
3074 { Bad_Opcode },
3075 { "blcfill", { VexGdq, Edq }, 0 },
3076 { "blsfill", { VexGdq, Edq }, 0 },
3077 { "blcs", { VexGdq, Edq }, 0 },
3078 { "tzmsk", { VexGdq, Edq }, 0 },
3079 { "blcic", { VexGdq, Edq }, 0 },
3080 { "blsic", { VexGdq, Edq }, 0 },
3081 { "t1mskc", { VexGdq, Edq }, 0 },
3082 },
3083 /* REG_0FXOP_09_02_L_0 */
3084 {
3085 { Bad_Opcode },
3086 { "blcmsk", { VexGdq, Edq }, 0 },
3087 { Bad_Opcode },
3088 { Bad_Opcode },
3089 { Bad_Opcode },
3090 { Bad_Opcode },
3091 { "blci", { VexGdq, Edq }, 0 },
3092 },
3093 /* REG_0FXOP_09_12_M_1_L_0 */
3094 {
3095 { "llwpcb", { Edq }, 0 },
3096 { "slwpcb", { Edq }, 0 },
3097 },
3098 /* REG_0FXOP_0A_12_L_0 */
3099 {
3100 { "lwpins", { VexGdq, Ed, Id }, 0 },
3101 { "lwpval", { VexGdq, Ed, Id }, 0 },
3102 },
3103
3104 #include "i386-dis-evex-reg.h"
3105 };
3106
3107 static const struct dis386 prefix_table[][4] = {
3108 /* PREFIX_90 */
3109 {
3110 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3111 { "pause", { XX }, 0 },
3112 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3113 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3114 },
3115
3116 /* PREFIX_0F01_REG_1_RM_4 */
3117 {
3118 { Bad_Opcode },
3119 { Bad_Opcode },
3120 { "tdcall", { Skip_MODRM }, 0 },
3121 { Bad_Opcode },
3122 },
3123
3124 /* PREFIX_0F01_REG_1_RM_5 */
3125 {
3126 { Bad_Opcode },
3127 { Bad_Opcode },
3128 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3129 { Bad_Opcode },
3130 },
3131
3132 /* PREFIX_0F01_REG_1_RM_6 */
3133 {
3134 { Bad_Opcode },
3135 { Bad_Opcode },
3136 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3137 { Bad_Opcode },
3138 },
3139
3140 /* PREFIX_0F01_REG_1_RM_7 */
3141 {
3142 { "encls", { Skip_MODRM }, 0 },
3143 { Bad_Opcode },
3144 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3145 { Bad_Opcode },
3146 },
3147
3148 /* PREFIX_0F01_REG_3_RM_1 */
3149 {
3150 { "vmmcall", { Skip_MODRM }, 0 },
3151 { "vmgexit", { Skip_MODRM }, 0 },
3152 { Bad_Opcode },
3153 { "vmgexit", { Skip_MODRM }, 0 },
3154 },
3155
3156 /* PREFIX_0F01_REG_5_MOD_0 */
3157 {
3158 { Bad_Opcode },
3159 { "rstorssp", { Mq }, PREFIX_OPCODE },
3160 },
3161
3162 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3163 {
3164 { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
3165 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3166 { Bad_Opcode },
3167 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3168 },
3169
3170 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3171 {
3172 { Bad_Opcode },
3173 { Bad_Opcode },
3174 { Bad_Opcode },
3175 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3176 },
3177
3178 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3179 {
3180 { Bad_Opcode },
3181 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3182 },
3183
3184 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3185 {
3186 { Bad_Opcode },
3187 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3188 },
3189
3190 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3191 {
3192 { Bad_Opcode },
3193 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3194 },
3195
3196 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3197 {
3198 { "rdpkru", { Skip_MODRM }, 0 },
3199 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3200 },
3201
3202 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3203 {
3204 { "wrpkru", { Skip_MODRM }, 0 },
3205 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3206 },
3207
3208 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3209 {
3210 { "monitorx", { { OP_Monitor, 0 } }, 0 },
3211 { "mcommit", { Skip_MODRM }, 0 },
3212 },
3213
3214 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3215 {
3216 { "invlpgb", { Skip_MODRM }, 0 },
3217 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3218 { Bad_Opcode },
3219 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3220 },
3221
3222 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3223 {
3224 { "tlbsync", { Skip_MODRM }, 0 },
3225 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3226 { Bad_Opcode },
3227 { "pvalidate", { Skip_MODRM }, 0 },
3228 },
3229
3230 /* PREFIX_0F09 */
3231 {
3232 { "wbinvd", { XX }, 0 },
3233 { "wbnoinvd", { XX }, 0 },
3234 },
3235
3236 /* PREFIX_0F10 */
3237 {
3238 { "movups", { XM, EXx }, PREFIX_OPCODE },
3239 { "movss", { XM, EXd }, PREFIX_OPCODE },
3240 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3241 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3242 },
3243
3244 /* PREFIX_0F11 */
3245 {
3246 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3247 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3248 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3249 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3250 },
3251
3252 /* PREFIX_0F12 */
3253 {
3254 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3255 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3256 { MOD_TABLE (MOD_0F12_PREFIX_2) },
3257 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3258 },
3259
3260 /* PREFIX_0F16 */
3261 {
3262 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3263 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3264 { MOD_TABLE (MOD_0F16_PREFIX_2) },
3265 },
3266
3267 /* PREFIX_0F1A */
3268 {
3269 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3270 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3271 { "bndmov", { Gbnd, Ebnd }, 0 },
3272 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3273 },
3274
3275 /* PREFIX_0F1B */
3276 {
3277 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3278 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3279 { "bndmov", { EbndS, Gbnd }, 0 },
3280 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3281 },
3282
3283 /* PREFIX_0F1C */
3284 {
3285 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3286 { "nopQ", { Ev }, PREFIX_IGNORED },
3287 { "nopQ", { Ev }, 0 },
3288 { "nopQ", { Ev }, PREFIX_IGNORED },
3289 },
3290
3291 /* PREFIX_0F1E */
3292 {
3293 { "nopQ", { Ev }, 0 },
3294 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3295 { "nopQ", { Ev }, 0 },
3296 { NULL, { XX }, PREFIX_IGNORED },
3297 },
3298
3299 /* PREFIX_0F2A */
3300 {
3301 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3302 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3303 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3304 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3305 },
3306
3307 /* PREFIX_0F2B */
3308 {
3309 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3310 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3311 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3312 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3313 },
3314
3315 /* PREFIX_0F2C */
3316 {
3317 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3318 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3319 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3320 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3321 },
3322
3323 /* PREFIX_0F2D */
3324 {
3325 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3326 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3327 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3328 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3329 },
3330
3331 /* PREFIX_0F2E */
3332 {
3333 { "ucomiss",{ XM, EXd }, 0 },
3334 { Bad_Opcode },
3335 { "ucomisd",{ XM, EXq }, 0 },
3336 },
3337
3338 /* PREFIX_0F2F */
3339 {
3340 { "comiss", { XM, EXd }, 0 },
3341 { Bad_Opcode },
3342 { "comisd", { XM, EXq }, 0 },
3343 },
3344
3345 /* PREFIX_0F51 */
3346 {
3347 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3348 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3349 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3350 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3351 },
3352
3353 /* PREFIX_0F52 */
3354 {
3355 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3356 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3357 },
3358
3359 /* PREFIX_0F53 */
3360 {
3361 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3362 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3363 },
3364
3365 /* PREFIX_0F58 */
3366 {
3367 { "addps", { XM, EXx }, PREFIX_OPCODE },
3368 { "addss", { XM, EXd }, PREFIX_OPCODE },
3369 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3370 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3371 },
3372
3373 /* PREFIX_0F59 */
3374 {
3375 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3376 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3377 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3378 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3379 },
3380
3381 /* PREFIX_0F5A */
3382 {
3383 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3384 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3385 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3386 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3387 },
3388
3389 /* PREFIX_0F5B */
3390 {
3391 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3392 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3393 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3394 },
3395
3396 /* PREFIX_0F5C */
3397 {
3398 { "subps", { XM, EXx }, PREFIX_OPCODE },
3399 { "subss", { XM, EXd }, PREFIX_OPCODE },
3400 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3401 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3402 },
3403
3404 /* PREFIX_0F5D */
3405 {
3406 { "minps", { XM, EXx }, PREFIX_OPCODE },
3407 { "minss", { XM, EXd }, PREFIX_OPCODE },
3408 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3409 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3410 },
3411
3412 /* PREFIX_0F5E */
3413 {
3414 { "divps", { XM, EXx }, PREFIX_OPCODE },
3415 { "divss", { XM, EXd }, PREFIX_OPCODE },
3416 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3417 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3418 },
3419
3420 /* PREFIX_0F5F */
3421 {
3422 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3423 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3424 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3425 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3426 },
3427
3428 /* PREFIX_0F60 */
3429 {
3430 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3431 { Bad_Opcode },
3432 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3433 },
3434
3435 /* PREFIX_0F61 */
3436 {
3437 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3438 { Bad_Opcode },
3439 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3440 },
3441
3442 /* PREFIX_0F62 */
3443 {
3444 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3445 { Bad_Opcode },
3446 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3447 },
3448
3449 /* PREFIX_0F6F */
3450 {
3451 { "movq", { MX, EM }, PREFIX_OPCODE },
3452 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3453 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3454 },
3455
3456 /* PREFIX_0F70 */
3457 {
3458 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3459 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3460 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3461 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3462 },
3463
3464 /* PREFIX_0F78 */
3465 {
3466 {"vmread", { Em, Gm }, 0 },
3467 { Bad_Opcode },
3468 {"extrq", { XS, Ib, Ib }, 0 },
3469 {"insertq", { XM, XS, Ib, Ib }, 0 },
3470 },
3471
3472 /* PREFIX_0F79 */
3473 {
3474 {"vmwrite", { Gm, Em }, 0 },
3475 { Bad_Opcode },
3476 {"extrq", { XM, XS }, 0 },
3477 {"insertq", { XM, XS }, 0 },
3478 },
3479
3480 /* PREFIX_0F7C */
3481 {
3482 { Bad_Opcode },
3483 { Bad_Opcode },
3484 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3485 { "haddps", { XM, EXx }, PREFIX_OPCODE },
3486 },
3487
3488 /* PREFIX_0F7D */
3489 {
3490 { Bad_Opcode },
3491 { Bad_Opcode },
3492 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3493 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3494 },
3495
3496 /* PREFIX_0F7E */
3497 {
3498 { "movK", { Edq, MX }, PREFIX_OPCODE },
3499 { "movq", { XM, EXq }, PREFIX_OPCODE },
3500 { "movK", { Edq, XM }, PREFIX_OPCODE },
3501 },
3502
3503 /* PREFIX_0F7F */
3504 {
3505 { "movq", { EMS, MX }, PREFIX_OPCODE },
3506 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3507 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3508 },
3509
3510 /* PREFIX_0FAE_REG_0_MOD_3 */
3511 {
3512 { Bad_Opcode },
3513 { "rdfsbase", { Ev }, 0 },
3514 },
3515
3516 /* PREFIX_0FAE_REG_1_MOD_3 */
3517 {
3518 { Bad_Opcode },
3519 { "rdgsbase", { Ev }, 0 },
3520 },
3521
3522 /* PREFIX_0FAE_REG_2_MOD_3 */
3523 {
3524 { Bad_Opcode },
3525 { "wrfsbase", { Ev }, 0 },
3526 },
3527
3528 /* PREFIX_0FAE_REG_3_MOD_3 */
3529 {
3530 { Bad_Opcode },
3531 { "wrgsbase", { Ev }, 0 },
3532 },
3533
3534 /* PREFIX_0FAE_REG_4_MOD_0 */
3535 {
3536 { "xsave", { FXSAVE }, 0 },
3537 { "ptwrite{%LQ|}", { Edq }, 0 },
3538 },
3539
3540 /* PREFIX_0FAE_REG_4_MOD_3 */
3541 {
3542 { Bad_Opcode },
3543 { "ptwrite{%LQ|}", { Edq }, 0 },
3544 },
3545
3546 /* PREFIX_0FAE_REG_5_MOD_3 */
3547 {
3548 { "lfence", { Skip_MODRM }, 0 },
3549 { "incsspK", { Edq }, PREFIX_OPCODE },
3550 },
3551
3552 /* PREFIX_0FAE_REG_6_MOD_0 */
3553 {
3554 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
3555 { "clrssbsy", { Mq }, PREFIX_OPCODE },
3556 { "clwb", { Mb }, PREFIX_OPCODE },
3557 },
3558
3559 /* PREFIX_0FAE_REG_6_MOD_3 */
3560 {
3561 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3562 { "umonitor", { Eva }, PREFIX_OPCODE },
3563 { "tpause", { Edq }, PREFIX_OPCODE },
3564 { "umwait", { Edq }, PREFIX_OPCODE },
3565 },
3566
3567 /* PREFIX_0FAE_REG_7_MOD_0 */
3568 {
3569 { "clflush", { Mb }, 0 },
3570 { Bad_Opcode },
3571 { "clflushopt", { Mb }, 0 },
3572 },
3573
3574 /* PREFIX_0FB8 */
3575 {
3576 { Bad_Opcode },
3577 { "popcntS", { Gv, Ev }, 0 },
3578 },
3579
3580 /* PREFIX_0FBC */
3581 {
3582 { "bsfS", { Gv, Ev }, 0 },
3583 { "tzcntS", { Gv, Ev }, 0 },
3584 { "bsfS", { Gv, Ev }, 0 },
3585 },
3586
3587 /* PREFIX_0FBD */
3588 {
3589 { "bsrS", { Gv, Ev }, 0 },
3590 { "lzcntS", { Gv, Ev }, 0 },
3591 { "bsrS", { Gv, Ev }, 0 },
3592 },
3593
3594 /* PREFIX_0FC2 */
3595 {
3596 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
3597 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
3598 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
3599 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
3600 },
3601
3602 /* PREFIX_0FC7_REG_6_MOD_0 */
3603 {
3604 { "vmptrld",{ Mq }, 0 },
3605 { "vmxon", { Mq }, 0 },
3606 { "vmclear",{ Mq }, 0 },
3607 },
3608
3609 /* PREFIX_0FC7_REG_6_MOD_3 */
3610 {
3611 { "rdrand", { Ev }, 0 },
3612 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3613 { "rdrand", { Ev }, 0 }
3614 },
3615
3616 /* PREFIX_0FC7_REG_7_MOD_3 */
3617 {
3618 { "rdseed", { Ev }, 0 },
3619 { "rdpid", { Em }, 0 },
3620 { "rdseed", { Ev }, 0 },
3621 },
3622
3623 /* PREFIX_0FD0 */
3624 {
3625 { Bad_Opcode },
3626 { Bad_Opcode },
3627 { "addsubpd", { XM, EXx }, 0 },
3628 { "addsubps", { XM, EXx }, 0 },
3629 },
3630
3631 /* PREFIX_0FD6 */
3632 {
3633 { Bad_Opcode },
3634 { "movq2dq",{ XM, MS }, 0 },
3635 { "movq", { EXqS, XM }, 0 },
3636 { "movdq2q",{ MX, XS }, 0 },
3637 },
3638
3639 /* PREFIX_0FE6 */
3640 {
3641 { Bad_Opcode },
3642 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3643 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3644 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3645 },
3646
3647 /* PREFIX_0FE7 */
3648 {
3649 { "movntq", { Mq, MX }, PREFIX_OPCODE },
3650 { Bad_Opcode },
3651 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3652 },
3653
3654 /* PREFIX_0FF0 */
3655 {
3656 { Bad_Opcode },
3657 { Bad_Opcode },
3658 { Bad_Opcode },
3659 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3660 },
3661
3662 /* PREFIX_0FF7 */
3663 {
3664 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3665 { Bad_Opcode },
3666 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3667 },
3668
3669 /* PREFIX_0F38D8 */
3670 {
3671 { Bad_Opcode },
3672 { REG_TABLE (REG_0F38D8_PREFIX_1) },
3673 },
3674
3675 /* PREFIX_0F38DC */
3676 {
3677 { Bad_Opcode },
3678 { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3679 { "aesenc", { XM, EXx }, 0 },
3680 },
3681
3682 /* PREFIX_0F38DD */
3683 {
3684 { Bad_Opcode },
3685 { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3686 { "aesenclast", { XM, EXx }, 0 },
3687 },
3688
3689 /* PREFIX_0F38DE */
3690 {
3691 { Bad_Opcode },
3692 { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3693 { "aesdec", { XM, EXx }, 0 },
3694 },
3695
3696 /* PREFIX_0F38DF */
3697 {
3698 { Bad_Opcode },
3699 { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3700 { "aesdeclast", { XM, EXx }, 0 },
3701 },
3702
3703 /* PREFIX_0F38F0 */
3704 {
3705 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3706 { Bad_Opcode },
3707 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3708 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3709 },
3710
3711 /* PREFIX_0F38F1 */
3712 {
3713 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3714 { Bad_Opcode },
3715 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3716 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3717 },
3718
3719 /* PREFIX_0F38F6 */
3720 {
3721 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3722 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
3723 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
3724 { Bad_Opcode },
3725 },
3726
3727 /* PREFIX_0F38F8 */
3728 {
3729 { Bad_Opcode },
3730 { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3731 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3732 { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3733 },
3734 /* PREFIX_0F38FA */
3735 {
3736 { Bad_Opcode },
3737 { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3738 },
3739
3740 /* PREFIX_0F38FB */
3741 {
3742 { Bad_Opcode },
3743 { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3744 },
3745
3746 /* PREFIX_0F3A0F */
3747 {
3748 { Bad_Opcode },
3749 { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3750 },
3751
3752 /* PREFIX_VEX_0F10 */
3753 {
3754 { "vmovups", { XM, EXx }, 0 },
3755 { "vmovss", { XMScalar, VexScalarR, EXxmm_md }, 0 },
3756 { "vmovupd", { XM, EXx }, 0 },
3757 { "vmovsd", { XMScalar, VexScalarR, EXxmm_mq }, 0 },
3758 },
3759
3760 /* PREFIX_VEX_0F11 */
3761 {
3762 { "vmovups", { EXxS, XM }, 0 },
3763 { "vmovss", { EXdS, VexScalarR, XMScalar }, 0 },
3764 { "vmovupd", { EXxS, XM }, 0 },
3765 { "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 },
3766 },
3767
3768 /* PREFIX_VEX_0F12 */
3769 {
3770 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3771 { "vmovsldup", { XM, EXx }, 0 },
3772 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3773 { "vmovddup", { XM, EXymmq }, 0 },
3774 },
3775
3776 /* PREFIX_VEX_0F16 */
3777 {
3778 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3779 { "vmovshdup", { XM, EXx }, 0 },
3780 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3781 },
3782
3783 /* PREFIX_VEX_0F2A */
3784 {
3785 { Bad_Opcode },
3786 { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
3787 { Bad_Opcode },
3788 { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
3789 },
3790
3791 /* PREFIX_VEX_0F2C */
3792 {
3793 { Bad_Opcode },
3794 { "vcvttss2si", { Gdq, EXxmm_md, EXxEVexS }, 0 },
3795 { Bad_Opcode },
3796 { "vcvttsd2si", { Gdq, EXxmm_mq, EXxEVexS }, 0 },
3797 },
3798
3799 /* PREFIX_VEX_0F2D */
3800 {
3801 { Bad_Opcode },
3802 { "vcvtss2si", { Gdq, EXxmm_md, EXxEVexR }, 0 },
3803 { Bad_Opcode },
3804 { "vcvtsd2si", { Gdq, EXxmm_mq, EXxEVexR }, 0 },
3805 },
3806
3807 /* PREFIX_VEX_0F2E */
3808 {
3809 { "vucomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3810 { Bad_Opcode },
3811 { "vucomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3812 },
3813
3814 /* PREFIX_VEX_0F2F */
3815 {
3816 { "vcomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3817 { Bad_Opcode },
3818 { "vcomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3819 },
3820
3821 /* PREFIX_VEX_0F41 */
3822 {
3823 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
3824 { Bad_Opcode },
3825 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
3826 },
3827
3828 /* PREFIX_VEX_0F42 */
3829 {
3830 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
3831 { Bad_Opcode },
3832 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
3833 },
3834
3835 /* PREFIX_VEX_0F44 */
3836 {
3837 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
3838 { Bad_Opcode },
3839 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
3840 },
3841
3842 /* PREFIX_VEX_0F45 */
3843 {
3844 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
3845 { Bad_Opcode },
3846 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
3847 },
3848
3849 /* PREFIX_VEX_0F46 */
3850 {
3851 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
3852 { Bad_Opcode },
3853 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
3854 },
3855
3856 /* PREFIX_VEX_0F47 */
3857 {
3858 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
3859 { Bad_Opcode },
3860 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
3861 },
3862
3863 /* PREFIX_VEX_0F4A */
3864 {
3865 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
3866 { Bad_Opcode },
3867 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
3868 },
3869
3870 /* PREFIX_VEX_0F4B */
3871 {
3872 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
3873 { Bad_Opcode },
3874 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
3875 },
3876
3877 /* PREFIX_VEX_0F51 */
3878 {
3879 { "vsqrtps", { XM, EXx }, 0 },
3880 { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3881 { "vsqrtpd", { XM, EXx }, 0 },
3882 { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3883 },
3884
3885 /* PREFIX_VEX_0F52 */
3886 {
3887 { "vrsqrtps", { XM, EXx }, 0 },
3888 { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3889 },
3890
3891 /* PREFIX_VEX_0F53 */
3892 {
3893 { "vrcpps", { XM, EXx }, 0 },
3894 { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3895 },
3896
3897 /* PREFIX_VEX_0F58 */
3898 {
3899 { "vaddps", { XM, Vex, EXx }, 0 },
3900 { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3901 { "vaddpd", { XM, Vex, EXx }, 0 },
3902 { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3903 },
3904
3905 /* PREFIX_VEX_0F59 */
3906 {
3907 { "vmulps", { XM, Vex, EXx }, 0 },
3908 { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3909 { "vmulpd", { XM, Vex, EXx }, 0 },
3910 { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3911 },
3912
3913 /* PREFIX_VEX_0F5A */
3914 {
3915 { "vcvtps2pd", { XM, EXxmmq }, 0 },
3916 { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 },
3917 { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
3918 { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3919 },
3920
3921 /* PREFIX_VEX_0F5B */
3922 {
3923 { "vcvtdq2ps", { XM, EXx }, 0 },
3924 { "vcvttps2dq", { XM, EXx }, 0 },
3925 { "vcvtps2dq", { XM, EXx }, 0 },
3926 },
3927
3928 /* PREFIX_VEX_0F5C */
3929 {
3930 { "vsubps", { XM, Vex, EXx }, 0 },
3931 { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3932 { "vsubpd", { XM, Vex, EXx }, 0 },
3933 { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3934 },
3935
3936 /* PREFIX_VEX_0F5D */
3937 {
3938 { "vminps", { XM, Vex, EXx }, 0 },
3939 { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3940 { "vminpd", { XM, Vex, EXx }, 0 },
3941 { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3942 },
3943
3944 /* PREFIX_VEX_0F5E */
3945 {
3946 { "vdivps", { XM, Vex, EXx }, 0 },
3947 { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3948 { "vdivpd", { XM, Vex, EXx }, 0 },
3949 { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3950 },
3951
3952 /* PREFIX_VEX_0F5F */
3953 {
3954 { "vmaxps", { XM, Vex, EXx }, 0 },
3955 { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3956 { "vmaxpd", { XM, Vex, EXx }, 0 },
3957 { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3958 },
3959
3960 /* PREFIX_VEX_0F6F */
3961 {
3962 { Bad_Opcode },
3963 { "vmovdqu", { XM, EXx }, 0 },
3964 { "vmovdqa", { XM, EXx }, 0 },
3965 },
3966
3967 /* PREFIX_VEX_0F70 */
3968 {
3969 { Bad_Opcode },
3970 { "vpshufhw", { XM, EXx, Ib }, 0 },
3971 { "vpshufd", { XM, EXx, Ib }, 0 },
3972 { "vpshuflw", { XM, EXx, Ib }, 0 },
3973 },
3974
3975 /* PREFIX_VEX_0F7C */
3976 {
3977 { Bad_Opcode },
3978 { Bad_Opcode },
3979 { "vhaddpd", { XM, Vex, EXx }, 0 },
3980 { "vhaddps", { XM, Vex, EXx }, 0 },
3981 },
3982
3983 /* PREFIX_VEX_0F7D */
3984 {
3985 { Bad_Opcode },
3986 { Bad_Opcode },
3987 { "vhsubpd", { XM, Vex, EXx }, 0 },
3988 { "vhsubps", { XM, Vex, EXx }, 0 },
3989 },
3990
3991 /* PREFIX_VEX_0F7E */
3992 {
3993 { Bad_Opcode },
3994 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3995 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3996 },
3997
3998 /* PREFIX_VEX_0F7F */
3999 {
4000 { Bad_Opcode },
4001 { "vmovdqu", { EXxS, XM }, 0 },
4002 { "vmovdqa", { EXxS, XM }, 0 },
4003 },
4004
4005 /* PREFIX_VEX_0F90 */
4006 {
4007 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4008 { Bad_Opcode },
4009 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
4010 },
4011
4012 /* PREFIX_VEX_0F91 */
4013 {
4014 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4015 { Bad_Opcode },
4016 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
4017 },
4018
4019 /* PREFIX_VEX_0F92 */
4020 {
4021 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
4022 { Bad_Opcode },
4023 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
4024 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
4025 },
4026
4027 /* PREFIX_VEX_0F93 */
4028 {
4029 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
4030 { Bad_Opcode },
4031 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
4032 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
4033 },
4034
4035 /* PREFIX_VEX_0F98 */
4036 {
4037 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
4038 { Bad_Opcode },
4039 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
4040 },
4041
4042 /* PREFIX_VEX_0F99 */
4043 {
4044 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
4045 { Bad_Opcode },
4046 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
4047 },
4048
4049 /* PREFIX_VEX_0FC2 */
4050 {
4051 { "vcmpps", { XM, Vex, EXx, CMP }, 0 },
4052 { "vcmpss", { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
4053 { "vcmppd", { XM, Vex, EXx, CMP }, 0 },
4054 { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
4055 },
4056
4057 /* PREFIX_VEX_0FD0 */
4058 {
4059 { Bad_Opcode },
4060 { Bad_Opcode },
4061 { "vaddsubpd", { XM, Vex, EXx }, 0 },
4062 { "vaddsubps", { XM, Vex, EXx }, 0 },
4063 },
4064
4065 /* PREFIX_VEX_0FE6 */
4066 {
4067 { Bad_Opcode },
4068 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
4069 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
4070 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
4071 },
4072
4073 /* PREFIX_VEX_0FF0 */
4074 {
4075 { Bad_Opcode },
4076 { Bad_Opcode },
4077 { Bad_Opcode },
4078 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4079 },
4080
4081 /* PREFIX_VEX_0F3849_X86_64 */
4082 {
4083 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
4084 { Bad_Opcode },
4085 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
4086 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
4087 },
4088
4089 /* PREFIX_VEX_0F384B_X86_64 */
4090 {
4091 { Bad_Opcode },
4092 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4093 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4094 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4095 },
4096
4097 /* PREFIX_VEX_0F385C_X86_64 */
4098 {
4099 { Bad_Opcode },
4100 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4101 { Bad_Opcode },
4102 },
4103
4104 /* PREFIX_VEX_0F385E_X86_64 */
4105 {
4106 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4107 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4108 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4109 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4110 },
4111
4112 /* PREFIX_VEX_0F38F5 */
4113 {
4114 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
4115 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
4116 { Bad_Opcode },
4117 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
4118 },
4119
4120 /* PREFIX_VEX_0F38F6 */
4121 {
4122 { Bad_Opcode },
4123 { Bad_Opcode },
4124 { Bad_Opcode },
4125 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
4126 },
4127
4128 /* PREFIX_VEX_0F38F7 */
4129 {
4130 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
4131 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
4132 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
4133 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
4134 },
4135
4136 /* PREFIX_VEX_0F3AF0 */
4137 {
4138 { Bad_Opcode },
4139 { Bad_Opcode },
4140 { Bad_Opcode },
4141 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
4142 },
4143
4144 #include "i386-dis-evex-prefix.h"
4145 };
4146
4147 static const struct dis386 x86_64_table[][2] = {
4148 /* X86_64_06 */
4149 {
4150 { "pushP", { es }, 0 },
4151 },
4152
4153 /* X86_64_07 */
4154 {
4155 { "popP", { es }, 0 },
4156 },
4157
4158 /* X86_64_0E */
4159 {
4160 { "pushP", { cs }, 0 },
4161 },
4162
4163 /* X86_64_16 */
4164 {
4165 { "pushP", { ss }, 0 },
4166 },
4167
4168 /* X86_64_17 */
4169 {
4170 { "popP", { ss }, 0 },
4171 },
4172
4173 /* X86_64_1E */
4174 {
4175 { "pushP", { ds }, 0 },
4176 },
4177
4178 /* X86_64_1F */
4179 {
4180 { "popP", { ds }, 0 },
4181 },
4182
4183 /* X86_64_27 */
4184 {
4185 { "daa", { XX }, 0 },
4186 },
4187
4188 /* X86_64_2F */
4189 {
4190 { "das", { XX }, 0 },
4191 },
4192
4193 /* X86_64_37 */
4194 {
4195 { "aaa", { XX }, 0 },
4196 },
4197
4198 /* X86_64_3F */
4199 {
4200 { "aas", { XX }, 0 },
4201 },
4202
4203 /* X86_64_60 */
4204 {
4205 { "pushaP", { XX }, 0 },
4206 },
4207
4208 /* X86_64_61 */
4209 {
4210 { "popaP", { XX }, 0 },
4211 },
4212
4213 /* X86_64_62 */
4214 {
4215 { MOD_TABLE (MOD_62_32BIT) },
4216 { EVEX_TABLE (EVEX_0F) },
4217 },
4218
4219 /* X86_64_63 */
4220 {
4221 { "arpl", { Ew, Gw }, 0 },
4222 { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4223 },
4224
4225 /* X86_64_6D */
4226 {
4227 { "ins{R|}", { Yzr, indirDX }, 0 },
4228 { "ins{G|}", { Yzr, indirDX }, 0 },
4229 },
4230
4231 /* X86_64_6F */
4232 {
4233 { "outs{R|}", { indirDXr, Xz }, 0 },
4234 { "outs{G|}", { indirDXr, Xz }, 0 },
4235 },
4236
4237 /* X86_64_82 */
4238 {
4239 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4240 { REG_TABLE (REG_80) },
4241 },
4242
4243 /* X86_64_9A */
4244 {
4245 { "{l|}call{P|}", { Ap }, 0 },
4246 },
4247
4248 /* X86_64_C2 */
4249 {
4250 { "retP", { Iw, BND }, 0 },
4251 { "ret@", { Iw, BND }, 0 },
4252 },
4253
4254 /* X86_64_C3 */
4255 {
4256 { "retP", { BND }, 0 },
4257 { "ret@", { BND }, 0 },
4258 },
4259
4260 /* X86_64_C4 */
4261 {
4262 { MOD_TABLE (MOD_C4_32BIT) },
4263 { VEX_C4_TABLE (VEX_0F) },
4264 },
4265
4266 /* X86_64_C5 */
4267 {
4268 { MOD_TABLE (MOD_C5_32BIT) },
4269 { VEX_C5_TABLE (VEX_0F) },
4270 },
4271
4272 /* X86_64_CE */
4273 {
4274 { "into", { XX }, 0 },
4275 },
4276
4277 /* X86_64_D4 */
4278 {
4279 { "aam", { Ib }, 0 },
4280 },
4281
4282 /* X86_64_D5 */
4283 {
4284 { "aad", { Ib }, 0 },
4285 },
4286
4287 /* X86_64_E8 */
4288 {
4289 { "callP", { Jv, BND }, 0 },
4290 { "call@", { Jv, BND }, 0 }
4291 },
4292
4293 /* X86_64_E9 */
4294 {
4295 { "jmpP", { Jv, BND }, 0 },
4296 { "jmp@", { Jv, BND }, 0 }
4297 },
4298
4299 /* X86_64_EA */
4300 {
4301 { "{l|}jmp{P|}", { Ap }, 0 },
4302 },
4303
4304 /* X86_64_0F01_REG_0 */
4305 {
4306 { "sgdt{Q|Q}", { M }, 0 },
4307 { "sgdt", { M }, 0 },
4308 },
4309
4310 /* X86_64_0F01_REG_1 */
4311 {
4312 { "sidt{Q|Q}", { M }, 0 },
4313 { "sidt", { M }, 0 },
4314 },
4315
4316 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4317 {
4318 { Bad_Opcode },
4319 { "seamret", { Skip_MODRM }, 0 },
4320 },
4321
4322 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4323 {
4324 { Bad_Opcode },
4325 { "seamops", { Skip_MODRM }, 0 },
4326 },
4327
4328 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4329 {
4330 { Bad_Opcode },
4331 { "seamcall", { Skip_MODRM }, 0 },
4332 },
4333
4334 /* X86_64_0F01_REG_2 */
4335 {
4336 { "lgdt{Q|Q}", { M }, 0 },
4337 { "lgdt", { M }, 0 },
4338 },
4339
4340 /* X86_64_0F01_REG_3 */
4341 {
4342 { "lidt{Q|Q}", { M }, 0 },
4343 { "lidt", { M }, 0 },
4344 },
4345
4346 {
4347 /* X86_64_0F24 */
4348 { "movZ", { Em, Td }, 0 },
4349 },
4350
4351 {
4352 /* X86_64_0F26 */
4353 { "movZ", { Td, Em }, 0 },
4354 },
4355
4356 /* X86_64_VEX_0F3849 */
4357 {
4358 { Bad_Opcode },
4359 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4360 },
4361
4362 /* X86_64_VEX_0F384B */
4363 {
4364 { Bad_Opcode },
4365 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4366 },
4367
4368 /* X86_64_VEX_0F385C */
4369 {
4370 { Bad_Opcode },
4371 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4372 },
4373
4374 /* X86_64_VEX_0F385E */
4375 {
4376 { Bad_Opcode },
4377 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4378 },
4379
4380 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4381 {
4382 { Bad_Opcode },
4383 { "uiret", { Skip_MODRM }, 0 },
4384 },
4385
4386 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4387 {
4388 { Bad_Opcode },
4389 { "testui", { Skip_MODRM }, 0 },
4390 },
4391
4392 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4393 {
4394 { Bad_Opcode },
4395 { "clui", { Skip_MODRM }, 0 },
4396 },
4397
4398 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4399 {
4400 { Bad_Opcode },
4401 { "stui", { Skip_MODRM }, 0 },
4402 },
4403
4404 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4405 {
4406 { Bad_Opcode },
4407 { "rmpadjust", { Skip_MODRM }, 0 },
4408 },
4409
4410 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4411 {
4412 { Bad_Opcode },
4413 { "rmpupdate", { Skip_MODRM }, 0 },
4414 },
4415
4416 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4417 {
4418 { Bad_Opcode },
4419 { "psmash", { Skip_MODRM }, 0 },
4420 },
4421
4422 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4423 {
4424 { Bad_Opcode },
4425 { "senduipi", { Eq }, 0 },
4426 },
4427 };
4428
4429 static const struct dis386 three_byte_table[][256] = {
4430
4431 /* THREE_BYTE_0F38 */
4432 {
4433 /* 00 */
4434 { "pshufb", { MX, EM }, PREFIX_OPCODE },
4435 { "phaddw", { MX, EM }, PREFIX_OPCODE },
4436 { "phaddd", { MX, EM }, PREFIX_OPCODE },
4437 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
4438 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
4439 { "phsubw", { MX, EM }, PREFIX_OPCODE },
4440 { "phsubd", { MX, EM }, PREFIX_OPCODE },
4441 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
4442 /* 08 */
4443 { "psignb", { MX, EM }, PREFIX_OPCODE },
4444 { "psignw", { MX, EM }, PREFIX_OPCODE },
4445 { "psignd", { MX, EM }, PREFIX_OPCODE },
4446 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4447 { Bad_Opcode },
4448 { Bad_Opcode },
4449 { Bad_Opcode },
4450 { Bad_Opcode },
4451 /* 10 */
4452 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4453 { Bad_Opcode },
4454 { Bad_Opcode },
4455 { Bad_Opcode },
4456 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4457 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4458 { Bad_Opcode },
4459 { "ptest", { XM, EXx }, PREFIX_DATA },
4460 /* 18 */
4461 { Bad_Opcode },
4462 { Bad_Opcode },
4463 { Bad_Opcode },
4464 { Bad_Opcode },
4465 { "pabsb", { MX, EM }, PREFIX_OPCODE },
4466 { "pabsw", { MX, EM }, PREFIX_OPCODE },
4467 { "pabsd", { MX, EM }, PREFIX_OPCODE },
4468 { Bad_Opcode },
4469 /* 20 */
4470 { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4471 { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4472 { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4473 { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4474 { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4475 { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4476 { Bad_Opcode },
4477 { Bad_Opcode },
4478 /* 28 */
4479 { "pmuldq", { XM, EXx }, PREFIX_DATA },
4480 { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4481 { MOD_TABLE (MOD_0F382A) },
4482 { "packusdw", { XM, EXx }, PREFIX_DATA },
4483 { Bad_Opcode },
4484 { Bad_Opcode },
4485 { Bad_Opcode },
4486 { Bad_Opcode },
4487 /* 30 */
4488 { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4489 { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4490 { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4491 { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4492 { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4493 { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4494 { Bad_Opcode },
4495 { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4496 /* 38 */
4497 { "pminsb", { XM, EXx }, PREFIX_DATA },
4498 { "pminsd", { XM, EXx }, PREFIX_DATA },
4499 { "pminuw", { XM, EXx }, PREFIX_DATA },
4500 { "pminud", { XM, EXx }, PREFIX_DATA },
4501 { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4502 { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4503 { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4504 { "pmaxud", { XM, EXx }, PREFIX_DATA },
4505 /* 40 */
4506 { "pmulld", { XM, EXx }, PREFIX_DATA },
4507 { "phminposuw", { XM, EXx }, PREFIX_DATA },
4508 { Bad_Opcode },
4509 { Bad_Opcode },
4510 { Bad_Opcode },
4511 { Bad_Opcode },
4512 { Bad_Opcode },
4513 { Bad_Opcode },
4514 /* 48 */
4515 { Bad_Opcode },
4516 { Bad_Opcode },
4517 { Bad_Opcode },
4518 { Bad_Opcode },
4519 { Bad_Opcode },
4520 { Bad_Opcode },
4521 { Bad_Opcode },
4522 { Bad_Opcode },
4523 /* 50 */
4524 { Bad_Opcode },
4525 { Bad_Opcode },
4526 { Bad_Opcode },
4527 { Bad_Opcode },
4528 { Bad_Opcode },
4529 { Bad_Opcode },
4530 { Bad_Opcode },
4531 { Bad_Opcode },
4532 /* 58 */
4533 { Bad_Opcode },
4534 { Bad_Opcode },
4535 { Bad_Opcode },
4536 { Bad_Opcode },
4537 { Bad_Opcode },
4538 { Bad_Opcode },
4539 { Bad_Opcode },
4540 { Bad_Opcode },
4541 /* 60 */
4542 { Bad_Opcode },
4543 { Bad_Opcode },
4544 { Bad_Opcode },
4545 { Bad_Opcode },
4546 { Bad_Opcode },
4547 { Bad_Opcode },
4548 { Bad_Opcode },
4549 { Bad_Opcode },
4550 /* 68 */
4551 { Bad_Opcode },
4552 { Bad_Opcode },
4553 { Bad_Opcode },
4554 { Bad_Opcode },
4555 { Bad_Opcode },
4556 { Bad_Opcode },
4557 { Bad_Opcode },
4558 { Bad_Opcode },
4559 /* 70 */
4560 { Bad_Opcode },
4561 { Bad_Opcode },
4562 { Bad_Opcode },
4563 { Bad_Opcode },
4564 { Bad_Opcode },
4565 { Bad_Opcode },
4566 { Bad_Opcode },
4567 { Bad_Opcode },
4568 /* 78 */
4569 { Bad_Opcode },
4570 { Bad_Opcode },
4571 { Bad_Opcode },
4572 { Bad_Opcode },
4573 { Bad_Opcode },
4574 { Bad_Opcode },
4575 { Bad_Opcode },
4576 { Bad_Opcode },
4577 /* 80 */
4578 { "invept", { Gm, Mo }, PREFIX_DATA },
4579 { "invvpid", { Gm, Mo }, PREFIX_DATA },
4580 { "invpcid", { Gm, M }, PREFIX_DATA },
4581 { Bad_Opcode },
4582 { Bad_Opcode },
4583 { Bad_Opcode },
4584 { Bad_Opcode },
4585 { Bad_Opcode },
4586 /* 88 */
4587 { Bad_Opcode },
4588 { Bad_Opcode },
4589 { Bad_Opcode },
4590 { Bad_Opcode },
4591 { Bad_Opcode },
4592 { Bad_Opcode },
4593 { Bad_Opcode },
4594 { Bad_Opcode },
4595 /* 90 */
4596 { Bad_Opcode },
4597 { Bad_Opcode },
4598 { Bad_Opcode },
4599 { Bad_Opcode },
4600 { Bad_Opcode },
4601 { Bad_Opcode },
4602 { Bad_Opcode },
4603 { Bad_Opcode },
4604 /* 98 */
4605 { Bad_Opcode },
4606 { Bad_Opcode },
4607 { Bad_Opcode },
4608 { Bad_Opcode },
4609 { Bad_Opcode },
4610 { Bad_Opcode },
4611 { Bad_Opcode },
4612 { Bad_Opcode },
4613 /* a0 */
4614 { Bad_Opcode },
4615 { Bad_Opcode },
4616 { Bad_Opcode },
4617 { Bad_Opcode },
4618 { Bad_Opcode },
4619 { Bad_Opcode },
4620 { Bad_Opcode },
4621 { Bad_Opcode },
4622 /* a8 */
4623 { Bad_Opcode },
4624 { Bad_Opcode },
4625 { Bad_Opcode },
4626 { Bad_Opcode },
4627 { Bad_Opcode },
4628 { Bad_Opcode },
4629 { Bad_Opcode },
4630 { Bad_Opcode },
4631 /* b0 */
4632 { Bad_Opcode },
4633 { Bad_Opcode },
4634 { Bad_Opcode },
4635 { Bad_Opcode },
4636 { Bad_Opcode },
4637 { Bad_Opcode },
4638 { Bad_Opcode },
4639 { Bad_Opcode },
4640 /* b8 */
4641 { Bad_Opcode },
4642 { Bad_Opcode },
4643 { Bad_Opcode },
4644 { Bad_Opcode },
4645 { Bad_Opcode },
4646 { Bad_Opcode },
4647 { Bad_Opcode },
4648 { Bad_Opcode },
4649 /* c0 */
4650 { Bad_Opcode },
4651 { Bad_Opcode },
4652 { Bad_Opcode },
4653 { Bad_Opcode },
4654 { Bad_Opcode },
4655 { Bad_Opcode },
4656 { Bad_Opcode },
4657 { Bad_Opcode },
4658 /* c8 */
4659 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4660 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4661 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4662 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4663 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4664 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4665 { Bad_Opcode },
4666 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4667 /* d0 */
4668 { Bad_Opcode },
4669 { Bad_Opcode },
4670 { Bad_Opcode },
4671 { Bad_Opcode },
4672 { Bad_Opcode },
4673 { Bad_Opcode },
4674 { Bad_Opcode },
4675 { Bad_Opcode },
4676 /* d8 */
4677 { PREFIX_TABLE (PREFIX_0F38D8) },
4678 { Bad_Opcode },
4679 { Bad_Opcode },
4680 { "aesimc", { XM, EXx }, PREFIX_DATA },
4681 { PREFIX_TABLE (PREFIX_0F38DC) },
4682 { PREFIX_TABLE (PREFIX_0F38DD) },
4683 { PREFIX_TABLE (PREFIX_0F38DE) },
4684 { PREFIX_TABLE (PREFIX_0F38DF) },
4685 /* e0 */
4686 { Bad_Opcode },
4687 { Bad_Opcode },
4688 { Bad_Opcode },
4689 { Bad_Opcode },
4690 { Bad_Opcode },
4691 { Bad_Opcode },
4692 { Bad_Opcode },
4693 { Bad_Opcode },
4694 /* e8 */
4695 { Bad_Opcode },
4696 { Bad_Opcode },
4697 { Bad_Opcode },
4698 { Bad_Opcode },
4699 { Bad_Opcode },
4700 { Bad_Opcode },
4701 { Bad_Opcode },
4702 { Bad_Opcode },
4703 /* f0 */
4704 { PREFIX_TABLE (PREFIX_0F38F0) },
4705 { PREFIX_TABLE (PREFIX_0F38F1) },
4706 { Bad_Opcode },
4707 { Bad_Opcode },
4708 { Bad_Opcode },
4709 { MOD_TABLE (MOD_0F38F5) },
4710 { PREFIX_TABLE (PREFIX_0F38F6) },
4711 { Bad_Opcode },
4712 /* f8 */
4713 { PREFIX_TABLE (PREFIX_0F38F8) },
4714 { MOD_TABLE (MOD_0F38F9) },
4715 { PREFIX_TABLE (PREFIX_0F38FA) },
4716 { PREFIX_TABLE (PREFIX_0F38FB) },
4717 { Bad_Opcode },
4718 { Bad_Opcode },
4719 { Bad_Opcode },
4720 { Bad_Opcode },
4721 },
4722 /* THREE_BYTE_0F3A */
4723 {
4724 /* 00 */
4725 { Bad_Opcode },
4726 { Bad_Opcode },
4727 { Bad_Opcode },
4728 { Bad_Opcode },
4729 { Bad_Opcode },
4730 { Bad_Opcode },
4731 { Bad_Opcode },
4732 { Bad_Opcode },
4733 /* 08 */
4734 { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4735 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4736 { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4737 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4738 { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4739 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4740 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4741 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
4742 /* 10 */
4743 { Bad_Opcode },
4744 { Bad_Opcode },
4745 { Bad_Opcode },
4746 { Bad_Opcode },
4747 { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA },
4748 { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA },
4749 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4750 { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
4751 /* 18 */
4752 { Bad_Opcode },
4753 { Bad_Opcode },
4754 { Bad_Opcode },
4755 { Bad_Opcode },
4756 { Bad_Opcode },
4757 { Bad_Opcode },
4758 { Bad_Opcode },
4759 { Bad_Opcode },
4760 /* 20 */
4761 { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA },
4762 { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4763 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4764 { Bad_Opcode },
4765 { Bad_Opcode },
4766 { Bad_Opcode },
4767 { Bad_Opcode },
4768 { Bad_Opcode },
4769 /* 28 */
4770 { Bad_Opcode },
4771 { Bad_Opcode },
4772 { Bad_Opcode },
4773 { Bad_Opcode },
4774 { Bad_Opcode },
4775 { Bad_Opcode },
4776 { Bad_Opcode },
4777 { Bad_Opcode },
4778 /* 30 */
4779 { Bad_Opcode },
4780 { Bad_Opcode },
4781 { Bad_Opcode },
4782 { Bad_Opcode },
4783 { Bad_Opcode },
4784 { Bad_Opcode },
4785 { Bad_Opcode },
4786 { Bad_Opcode },
4787 /* 38 */
4788 { Bad_Opcode },
4789 { Bad_Opcode },
4790 { Bad_Opcode },
4791 { Bad_Opcode },
4792 { Bad_Opcode },
4793 { Bad_Opcode },
4794 { Bad_Opcode },
4795 { Bad_Opcode },
4796 /* 40 */
4797 { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
4798 { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
4799 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4800 { Bad_Opcode },
4801 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4802 { Bad_Opcode },
4803 { Bad_Opcode },
4804 { Bad_Opcode },
4805 /* 48 */
4806 { Bad_Opcode },
4807 { Bad_Opcode },
4808 { Bad_Opcode },
4809 { Bad_Opcode },
4810 { Bad_Opcode },
4811 { Bad_Opcode },
4812 { Bad_Opcode },
4813 { Bad_Opcode },
4814 /* 50 */
4815 { Bad_Opcode },
4816 { Bad_Opcode },
4817 { Bad_Opcode },
4818 { Bad_Opcode },
4819 { Bad_Opcode },
4820 { Bad_Opcode },
4821 { Bad_Opcode },
4822 { Bad_Opcode },
4823 /* 58 */
4824 { Bad_Opcode },
4825 { Bad_Opcode },
4826 { Bad_Opcode },
4827 { Bad_Opcode },
4828 { Bad_Opcode },
4829 { Bad_Opcode },
4830 { Bad_Opcode },
4831 { Bad_Opcode },
4832 /* 60 */
4833 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4834 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4835 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4836 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4837 { Bad_Opcode },
4838 { Bad_Opcode },
4839 { Bad_Opcode },
4840 { Bad_Opcode },
4841 /* 68 */
4842 { Bad_Opcode },
4843 { Bad_Opcode },
4844 { Bad_Opcode },
4845 { Bad_Opcode },
4846 { Bad_Opcode },
4847 { Bad_Opcode },
4848 { Bad_Opcode },
4849 { Bad_Opcode },
4850 /* 70 */
4851 { Bad_Opcode },
4852 { Bad_Opcode },
4853 { Bad_Opcode },
4854 { Bad_Opcode },
4855 { Bad_Opcode },
4856 { Bad_Opcode },
4857 { Bad_Opcode },
4858 { Bad_Opcode },
4859 /* 78 */
4860 { Bad_Opcode },
4861 { Bad_Opcode },
4862 { Bad_Opcode },
4863 { Bad_Opcode },
4864 { Bad_Opcode },
4865 { Bad_Opcode },
4866 { Bad_Opcode },
4867 { Bad_Opcode },
4868 /* 80 */
4869 { Bad_Opcode },
4870 { Bad_Opcode },
4871 { Bad_Opcode },
4872 { Bad_Opcode },
4873 { Bad_Opcode },
4874 { Bad_Opcode },
4875 { Bad_Opcode },
4876 { Bad_Opcode },
4877 /* 88 */
4878 { Bad_Opcode },
4879 { Bad_Opcode },
4880 { Bad_Opcode },
4881 { Bad_Opcode },
4882 { Bad_Opcode },
4883 { Bad_Opcode },
4884 { Bad_Opcode },
4885 { Bad_Opcode },
4886 /* 90 */
4887 { Bad_Opcode },
4888 { Bad_Opcode },
4889 { Bad_Opcode },
4890 { Bad_Opcode },
4891 { Bad_Opcode },
4892 { Bad_Opcode },
4893 { Bad_Opcode },
4894 { Bad_Opcode },
4895 /* 98 */
4896 { Bad_Opcode },
4897 { Bad_Opcode },
4898 { Bad_Opcode },
4899 { Bad_Opcode },
4900 { Bad_Opcode },
4901 { Bad_Opcode },
4902 { Bad_Opcode },
4903 { Bad_Opcode },
4904 /* a0 */
4905 { Bad_Opcode },
4906 { Bad_Opcode },
4907 { Bad_Opcode },
4908 { Bad_Opcode },
4909 { Bad_Opcode },
4910 { Bad_Opcode },
4911 { Bad_Opcode },
4912 { Bad_Opcode },
4913 /* a8 */
4914 { Bad_Opcode },
4915 { Bad_Opcode },
4916 { Bad_Opcode },
4917 { Bad_Opcode },
4918 { Bad_Opcode },
4919 { Bad_Opcode },
4920 { Bad_Opcode },
4921 { Bad_Opcode },
4922 /* b0 */
4923 { Bad_Opcode },
4924 { Bad_Opcode },
4925 { Bad_Opcode },
4926 { Bad_Opcode },
4927 { Bad_Opcode },
4928 { Bad_Opcode },
4929 { Bad_Opcode },
4930 { Bad_Opcode },
4931 /* b8 */
4932 { Bad_Opcode },
4933 { Bad_Opcode },
4934 { Bad_Opcode },
4935 { Bad_Opcode },
4936 { Bad_Opcode },
4937 { Bad_Opcode },
4938 { Bad_Opcode },
4939 { Bad_Opcode },
4940 /* c0 */
4941 { Bad_Opcode },
4942 { Bad_Opcode },
4943 { Bad_Opcode },
4944 { Bad_Opcode },
4945 { Bad_Opcode },
4946 { Bad_Opcode },
4947 { Bad_Opcode },
4948 { Bad_Opcode },
4949 /* c8 */
4950 { Bad_Opcode },
4951 { Bad_Opcode },
4952 { Bad_Opcode },
4953 { Bad_Opcode },
4954 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4955 { Bad_Opcode },
4956 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4957 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4958 /* d0 */
4959 { Bad_Opcode },
4960 { Bad_Opcode },
4961 { Bad_Opcode },
4962 { Bad_Opcode },
4963 { Bad_Opcode },
4964 { Bad_Opcode },
4965 { Bad_Opcode },
4966 { Bad_Opcode },
4967 /* d8 */
4968 { Bad_Opcode },
4969 { Bad_Opcode },
4970 { Bad_Opcode },
4971 { Bad_Opcode },
4972 { Bad_Opcode },
4973 { Bad_Opcode },
4974 { Bad_Opcode },
4975 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4976 /* e0 */
4977 { Bad_Opcode },
4978 { Bad_Opcode },
4979 { Bad_Opcode },
4980 { Bad_Opcode },
4981 { Bad_Opcode },
4982 { Bad_Opcode },
4983 { Bad_Opcode },
4984 { Bad_Opcode },
4985 /* e8 */
4986 { Bad_Opcode },
4987 { Bad_Opcode },
4988 { Bad_Opcode },
4989 { Bad_Opcode },
4990 { Bad_Opcode },
4991 { Bad_Opcode },
4992 { Bad_Opcode },
4993 { Bad_Opcode },
4994 /* f0 */
4995 { PREFIX_TABLE (PREFIX_0F3A0F) },
4996 { Bad_Opcode },
4997 { Bad_Opcode },
4998 { Bad_Opcode },
4999 { Bad_Opcode },
5000 { Bad_Opcode },
5001 { Bad_Opcode },
5002 { Bad_Opcode },
5003 /* f8 */
5004 { Bad_Opcode },
5005 { Bad_Opcode },
5006 { Bad_Opcode },
5007 { Bad_Opcode },
5008 { Bad_Opcode },
5009 { Bad_Opcode },
5010 { Bad_Opcode },
5011 { Bad_Opcode },
5012 },
5013 };
5014
5015 static const struct dis386 xop_table[][256] = {
5016 /* XOP_08 */
5017 {
5018 /* 00 */
5019 { Bad_Opcode },
5020 { Bad_Opcode },
5021 { Bad_Opcode },
5022 { Bad_Opcode },
5023 { Bad_Opcode },
5024 { Bad_Opcode },
5025 { Bad_Opcode },
5026 { Bad_Opcode },
5027 /* 08 */
5028 { Bad_Opcode },
5029 { Bad_Opcode },
5030 { Bad_Opcode },
5031 { Bad_Opcode },
5032 { Bad_Opcode },
5033 { Bad_Opcode },
5034 { Bad_Opcode },
5035 { Bad_Opcode },
5036 /* 10 */
5037 { Bad_Opcode },
5038 { Bad_Opcode },
5039 { Bad_Opcode },
5040 { Bad_Opcode },
5041 { Bad_Opcode },
5042 { Bad_Opcode },
5043 { Bad_Opcode },
5044 { Bad_Opcode },
5045 /* 18 */
5046 { Bad_Opcode },
5047 { Bad_Opcode },
5048 { Bad_Opcode },
5049 { Bad_Opcode },
5050 { Bad_Opcode },
5051 { Bad_Opcode },
5052 { Bad_Opcode },
5053 { Bad_Opcode },
5054 /* 20 */
5055 { Bad_Opcode },
5056 { Bad_Opcode },
5057 { Bad_Opcode },
5058 { Bad_Opcode },
5059 { Bad_Opcode },
5060 { Bad_Opcode },
5061 { Bad_Opcode },
5062 { Bad_Opcode },
5063 /* 28 */
5064 { Bad_Opcode },
5065 { Bad_Opcode },
5066 { Bad_Opcode },
5067 { Bad_Opcode },
5068 { Bad_Opcode },
5069 { Bad_Opcode },
5070 { Bad_Opcode },
5071 { Bad_Opcode },
5072 /* 30 */
5073 { Bad_Opcode },
5074 { Bad_Opcode },
5075 { Bad_Opcode },
5076 { Bad_Opcode },
5077 { Bad_Opcode },
5078 { Bad_Opcode },
5079 { Bad_Opcode },
5080 { Bad_Opcode },
5081 /* 38 */
5082 { Bad_Opcode },
5083 { Bad_Opcode },
5084 { Bad_Opcode },
5085 { Bad_Opcode },
5086 { Bad_Opcode },
5087 { Bad_Opcode },
5088 { Bad_Opcode },
5089 { Bad_Opcode },
5090 /* 40 */
5091 { Bad_Opcode },
5092 { Bad_Opcode },
5093 { Bad_Opcode },
5094 { Bad_Opcode },
5095 { Bad_Opcode },
5096 { Bad_Opcode },
5097 { Bad_Opcode },
5098 { Bad_Opcode },
5099 /* 48 */
5100 { Bad_Opcode },
5101 { Bad_Opcode },
5102 { Bad_Opcode },
5103 { Bad_Opcode },
5104 { Bad_Opcode },
5105 { Bad_Opcode },
5106 { Bad_Opcode },
5107 { Bad_Opcode },
5108 /* 50 */
5109 { Bad_Opcode },
5110 { Bad_Opcode },
5111 { Bad_Opcode },
5112 { Bad_Opcode },
5113 { Bad_Opcode },
5114 { Bad_Opcode },
5115 { Bad_Opcode },
5116 { Bad_Opcode },
5117 /* 58 */
5118 { Bad_Opcode },
5119 { Bad_Opcode },
5120 { Bad_Opcode },
5121 { Bad_Opcode },
5122 { Bad_Opcode },
5123 { Bad_Opcode },
5124 { Bad_Opcode },
5125 { Bad_Opcode },
5126 /* 60 */
5127 { Bad_Opcode },
5128 { Bad_Opcode },
5129 { Bad_Opcode },
5130 { Bad_Opcode },
5131 { Bad_Opcode },
5132 { Bad_Opcode },
5133 { Bad_Opcode },
5134 { Bad_Opcode },
5135 /* 68 */
5136 { Bad_Opcode },
5137 { Bad_Opcode },
5138 { Bad_Opcode },
5139 { Bad_Opcode },
5140 { Bad_Opcode },
5141 { Bad_Opcode },
5142 { Bad_Opcode },
5143 { Bad_Opcode },
5144 /* 70 */
5145 { Bad_Opcode },
5146 { Bad_Opcode },
5147 { Bad_Opcode },
5148 { Bad_Opcode },
5149 { Bad_Opcode },
5150 { Bad_Opcode },
5151 { Bad_Opcode },
5152 { Bad_Opcode },
5153 /* 78 */
5154 { Bad_Opcode },
5155 { Bad_Opcode },
5156 { Bad_Opcode },
5157 { Bad_Opcode },
5158 { Bad_Opcode },
5159 { Bad_Opcode },
5160 { Bad_Opcode },
5161 { Bad_Opcode },
5162 /* 80 */
5163 { Bad_Opcode },
5164 { Bad_Opcode },
5165 { Bad_Opcode },
5166 { Bad_Opcode },
5167 { Bad_Opcode },
5168 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5169 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5170 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5171 /* 88 */
5172 { Bad_Opcode },
5173 { Bad_Opcode },
5174 { Bad_Opcode },
5175 { Bad_Opcode },
5176 { Bad_Opcode },
5177 { Bad_Opcode },
5178 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5179 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5180 /* 90 */
5181 { Bad_Opcode },
5182 { Bad_Opcode },
5183 { Bad_Opcode },
5184 { Bad_Opcode },
5185 { Bad_Opcode },
5186 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5187 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5188 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5189 /* 98 */
5190 { Bad_Opcode },
5191 { Bad_Opcode },
5192 { Bad_Opcode },
5193 { Bad_Opcode },
5194 { Bad_Opcode },
5195 { Bad_Opcode },
5196 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5197 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5198 /* a0 */
5199 { Bad_Opcode },
5200 { Bad_Opcode },
5201 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
5202 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5203 { Bad_Opcode },
5204 { Bad_Opcode },
5205 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5206 { Bad_Opcode },
5207 /* a8 */
5208 { Bad_Opcode },
5209 { Bad_Opcode },
5210 { Bad_Opcode },
5211 { Bad_Opcode },
5212 { Bad_Opcode },
5213 { Bad_Opcode },
5214 { Bad_Opcode },
5215 { Bad_Opcode },
5216 /* b0 */
5217 { Bad_Opcode },
5218 { Bad_Opcode },
5219 { Bad_Opcode },
5220 { Bad_Opcode },
5221 { Bad_Opcode },
5222 { Bad_Opcode },
5223 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5224 { Bad_Opcode },
5225 /* b8 */
5226 { Bad_Opcode },
5227 { Bad_Opcode },
5228 { Bad_Opcode },
5229 { Bad_Opcode },
5230 { Bad_Opcode },
5231 { Bad_Opcode },
5232 { Bad_Opcode },
5233 { Bad_Opcode },
5234 /* c0 */
5235 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5236 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5237 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5238 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5239 { Bad_Opcode },
5240 { Bad_Opcode },
5241 { Bad_Opcode },
5242 { Bad_Opcode },
5243 /* c8 */
5244 { Bad_Opcode },
5245 { Bad_Opcode },
5246 { Bad_Opcode },
5247 { Bad_Opcode },
5248 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5249 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5250 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5251 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5252 /* d0 */
5253 { Bad_Opcode },
5254 { Bad_Opcode },
5255 { Bad_Opcode },
5256 { Bad_Opcode },
5257 { Bad_Opcode },
5258 { Bad_Opcode },
5259 { Bad_Opcode },
5260 { Bad_Opcode },
5261 /* d8 */
5262 { Bad_Opcode },
5263 { Bad_Opcode },
5264 { Bad_Opcode },
5265 { Bad_Opcode },
5266 { Bad_Opcode },
5267 { Bad_Opcode },
5268 { Bad_Opcode },
5269 { Bad_Opcode },
5270 /* e0 */
5271 { Bad_Opcode },
5272 { Bad_Opcode },
5273 { Bad_Opcode },
5274 { Bad_Opcode },
5275 { Bad_Opcode },
5276 { Bad_Opcode },
5277 { Bad_Opcode },
5278 { Bad_Opcode },
5279 /* e8 */
5280 { Bad_Opcode },
5281 { Bad_Opcode },
5282 { Bad_Opcode },
5283 { Bad_Opcode },
5284 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5285 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5286 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5287 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5288 /* f0 */
5289 { Bad_Opcode },
5290 { Bad_Opcode },
5291 { Bad_Opcode },
5292 { Bad_Opcode },
5293 { Bad_Opcode },
5294 { Bad_Opcode },
5295 { Bad_Opcode },
5296 { Bad_Opcode },
5297 /* f8 */
5298 { Bad_Opcode },
5299 { Bad_Opcode },
5300 { Bad_Opcode },
5301 { Bad_Opcode },
5302 { Bad_Opcode },
5303 { Bad_Opcode },
5304 { Bad_Opcode },
5305 { Bad_Opcode },
5306 },
5307 /* XOP_09 */
5308 {
5309 /* 00 */
5310 { Bad_Opcode },
5311 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5312 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5313 { Bad_Opcode },
5314 { Bad_Opcode },
5315 { Bad_Opcode },
5316 { Bad_Opcode },
5317 { Bad_Opcode },
5318 /* 08 */
5319 { Bad_Opcode },
5320 { Bad_Opcode },
5321 { Bad_Opcode },
5322 { Bad_Opcode },
5323 { Bad_Opcode },
5324 { Bad_Opcode },
5325 { Bad_Opcode },
5326 { Bad_Opcode },
5327 /* 10 */
5328 { Bad_Opcode },
5329 { Bad_Opcode },
5330 { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
5331 { Bad_Opcode },
5332 { Bad_Opcode },
5333 { Bad_Opcode },
5334 { Bad_Opcode },
5335 { Bad_Opcode },
5336 /* 18 */
5337 { Bad_Opcode },
5338 { Bad_Opcode },
5339 { Bad_Opcode },
5340 { Bad_Opcode },
5341 { Bad_Opcode },
5342 { Bad_Opcode },
5343 { Bad_Opcode },
5344 { Bad_Opcode },
5345 /* 20 */
5346 { Bad_Opcode },
5347 { Bad_Opcode },
5348 { Bad_Opcode },
5349 { Bad_Opcode },
5350 { Bad_Opcode },
5351 { Bad_Opcode },
5352 { Bad_Opcode },
5353 { Bad_Opcode },
5354 /* 28 */
5355 { Bad_Opcode },
5356 { Bad_Opcode },
5357 { Bad_Opcode },
5358 { Bad_Opcode },
5359 { Bad_Opcode },
5360 { Bad_Opcode },
5361 { Bad_Opcode },
5362 { Bad_Opcode },
5363 /* 30 */
5364 { Bad_Opcode },
5365 { Bad_Opcode },
5366 { Bad_Opcode },
5367 { Bad_Opcode },
5368 { Bad_Opcode },
5369 { Bad_Opcode },
5370 { Bad_Opcode },
5371 { Bad_Opcode },
5372 /* 38 */
5373 { Bad_Opcode },
5374 { Bad_Opcode },
5375 { Bad_Opcode },
5376 { Bad_Opcode },
5377 { Bad_Opcode },
5378 { Bad_Opcode },
5379 { Bad_Opcode },
5380 { Bad_Opcode },
5381 /* 40 */
5382 { Bad_Opcode },
5383 { Bad_Opcode },
5384 { Bad_Opcode },
5385 { Bad_Opcode },
5386 { Bad_Opcode },
5387 { Bad_Opcode },
5388 { Bad_Opcode },
5389 { Bad_Opcode },
5390 /* 48 */
5391 { Bad_Opcode },
5392 { Bad_Opcode },
5393 { Bad_Opcode },
5394 { Bad_Opcode },
5395 { Bad_Opcode },
5396 { Bad_Opcode },
5397 { Bad_Opcode },
5398 { Bad_Opcode },
5399 /* 50 */
5400 { Bad_Opcode },
5401 { Bad_Opcode },
5402 { Bad_Opcode },
5403 { Bad_Opcode },
5404 { Bad_Opcode },
5405 { Bad_Opcode },
5406 { Bad_Opcode },
5407 { Bad_Opcode },
5408 /* 58 */
5409 { Bad_Opcode },
5410 { Bad_Opcode },
5411 { Bad_Opcode },
5412 { Bad_Opcode },
5413 { Bad_Opcode },
5414 { Bad_Opcode },
5415 { Bad_Opcode },
5416 { Bad_Opcode },
5417 /* 60 */
5418 { Bad_Opcode },
5419 { Bad_Opcode },
5420 { Bad_Opcode },
5421 { Bad_Opcode },
5422 { Bad_Opcode },
5423 { Bad_Opcode },
5424 { Bad_Opcode },
5425 { Bad_Opcode },
5426 /* 68 */
5427 { Bad_Opcode },
5428 { Bad_Opcode },
5429 { Bad_Opcode },
5430 { Bad_Opcode },
5431 { Bad_Opcode },
5432 { Bad_Opcode },
5433 { Bad_Opcode },
5434 { Bad_Opcode },
5435 /* 70 */
5436 { Bad_Opcode },
5437 { Bad_Opcode },
5438 { Bad_Opcode },
5439 { Bad_Opcode },
5440 { Bad_Opcode },
5441 { Bad_Opcode },
5442 { Bad_Opcode },
5443 { Bad_Opcode },
5444 /* 78 */
5445 { Bad_Opcode },
5446 { Bad_Opcode },
5447 { Bad_Opcode },
5448 { Bad_Opcode },
5449 { Bad_Opcode },
5450 { Bad_Opcode },
5451 { Bad_Opcode },
5452 { Bad_Opcode },
5453 /* 80 */
5454 { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5455 { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5456 { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5457 { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5458 { Bad_Opcode },
5459 { Bad_Opcode },
5460 { Bad_Opcode },
5461 { Bad_Opcode },
5462 /* 88 */
5463 { Bad_Opcode },
5464 { Bad_Opcode },
5465 { Bad_Opcode },
5466 { Bad_Opcode },
5467 { Bad_Opcode },
5468 { Bad_Opcode },
5469 { Bad_Opcode },
5470 { Bad_Opcode },
5471 /* 90 */
5472 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5473 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5474 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5475 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5476 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5477 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5478 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5479 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5480 /* 98 */
5481 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5482 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5483 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5484 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5485 { Bad_Opcode },
5486 { Bad_Opcode },
5487 { Bad_Opcode },
5488 { Bad_Opcode },
5489 /* a0 */
5490 { Bad_Opcode },
5491 { Bad_Opcode },
5492 { Bad_Opcode },
5493 { Bad_Opcode },
5494 { Bad_Opcode },
5495 { Bad_Opcode },
5496 { Bad_Opcode },
5497 { Bad_Opcode },
5498 /* a8 */
5499 { Bad_Opcode },
5500 { Bad_Opcode },
5501 { Bad_Opcode },
5502 { Bad_Opcode },
5503 { Bad_Opcode },
5504 { Bad_Opcode },
5505 { Bad_Opcode },
5506 { Bad_Opcode },
5507 /* b0 */
5508 { Bad_Opcode },
5509 { Bad_Opcode },
5510 { Bad_Opcode },
5511 { Bad_Opcode },
5512 { Bad_Opcode },
5513 { Bad_Opcode },
5514 { Bad_Opcode },
5515 { Bad_Opcode },
5516 /* b8 */
5517 { Bad_Opcode },
5518 { Bad_Opcode },
5519 { Bad_Opcode },
5520 { Bad_Opcode },
5521 { Bad_Opcode },
5522 { Bad_Opcode },
5523 { Bad_Opcode },
5524 { Bad_Opcode },
5525 /* c0 */
5526 { Bad_Opcode },
5527 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5528 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5529 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5530 { Bad_Opcode },
5531 { Bad_Opcode },
5532 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5533 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5534 /* c8 */
5535 { Bad_Opcode },
5536 { Bad_Opcode },
5537 { Bad_Opcode },
5538 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5539 { Bad_Opcode },
5540 { Bad_Opcode },
5541 { Bad_Opcode },
5542 { Bad_Opcode },
5543 /* d0 */
5544 { Bad_Opcode },
5545 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5546 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5547 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5548 { Bad_Opcode },
5549 { Bad_Opcode },
5550 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5551 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5552 /* d8 */
5553 { Bad_Opcode },
5554 { Bad_Opcode },
5555 { Bad_Opcode },
5556 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5557 { Bad_Opcode },
5558 { Bad_Opcode },
5559 { Bad_Opcode },
5560 { Bad_Opcode },
5561 /* e0 */
5562 { Bad_Opcode },
5563 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5564 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5565 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5566 { Bad_Opcode },
5567 { Bad_Opcode },
5568 { Bad_Opcode },
5569 { Bad_Opcode },
5570 /* e8 */
5571 { Bad_Opcode },
5572 { Bad_Opcode },
5573 { Bad_Opcode },
5574 { Bad_Opcode },
5575 { Bad_Opcode },
5576 { Bad_Opcode },
5577 { Bad_Opcode },
5578 { Bad_Opcode },
5579 /* f0 */
5580 { Bad_Opcode },
5581 { Bad_Opcode },
5582 { Bad_Opcode },
5583 { Bad_Opcode },
5584 { Bad_Opcode },
5585 { Bad_Opcode },
5586 { Bad_Opcode },
5587 { Bad_Opcode },
5588 /* f8 */
5589 { Bad_Opcode },
5590 { Bad_Opcode },
5591 { Bad_Opcode },
5592 { Bad_Opcode },
5593 { Bad_Opcode },
5594 { Bad_Opcode },
5595 { Bad_Opcode },
5596 { Bad_Opcode },
5597 },
5598 /* XOP_0A */
5599 {
5600 /* 00 */
5601 { Bad_Opcode },
5602 { Bad_Opcode },
5603 { Bad_Opcode },
5604 { Bad_Opcode },
5605 { Bad_Opcode },
5606 { Bad_Opcode },
5607 { Bad_Opcode },
5608 { Bad_Opcode },
5609 /* 08 */
5610 { Bad_Opcode },
5611 { Bad_Opcode },
5612 { Bad_Opcode },
5613 { Bad_Opcode },
5614 { Bad_Opcode },
5615 { Bad_Opcode },
5616 { Bad_Opcode },
5617 { Bad_Opcode },
5618 /* 10 */
5619 { "bextrS", { Gdq, Edq, Id }, 0 },
5620 { Bad_Opcode },
5621 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5622 { Bad_Opcode },
5623 { Bad_Opcode },
5624 { Bad_Opcode },
5625 { Bad_Opcode },
5626 { Bad_Opcode },
5627 /* 18 */
5628 { Bad_Opcode },
5629 { Bad_Opcode },
5630 { Bad_Opcode },
5631 { Bad_Opcode },
5632 { Bad_Opcode },
5633 { Bad_Opcode },
5634 { Bad_Opcode },
5635 { Bad_Opcode },
5636 /* 20 */
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 { Bad_Opcode },
5640 { Bad_Opcode },
5641 { Bad_Opcode },
5642 { Bad_Opcode },
5643 { Bad_Opcode },
5644 { Bad_Opcode },
5645 /* 28 */
5646 { Bad_Opcode },
5647 { Bad_Opcode },
5648 { Bad_Opcode },
5649 { Bad_Opcode },
5650 { Bad_Opcode },
5651 { Bad_Opcode },
5652 { Bad_Opcode },
5653 { Bad_Opcode },
5654 /* 30 */
5655 { Bad_Opcode },
5656 { Bad_Opcode },
5657 { Bad_Opcode },
5658 { Bad_Opcode },
5659 { Bad_Opcode },
5660 { Bad_Opcode },
5661 { Bad_Opcode },
5662 { Bad_Opcode },
5663 /* 38 */
5664 { Bad_Opcode },
5665 { Bad_Opcode },
5666 { Bad_Opcode },
5667 { Bad_Opcode },
5668 { Bad_Opcode },
5669 { Bad_Opcode },
5670 { Bad_Opcode },
5671 { Bad_Opcode },
5672 /* 40 */
5673 { Bad_Opcode },
5674 { Bad_Opcode },
5675 { Bad_Opcode },
5676 { Bad_Opcode },
5677 { Bad_Opcode },
5678 { Bad_Opcode },
5679 { Bad_Opcode },
5680 { Bad_Opcode },
5681 /* 48 */
5682 { Bad_Opcode },
5683 { Bad_Opcode },
5684 { Bad_Opcode },
5685 { Bad_Opcode },
5686 { Bad_Opcode },
5687 { Bad_Opcode },
5688 { Bad_Opcode },
5689 { Bad_Opcode },
5690 /* 50 */
5691 { Bad_Opcode },
5692 { Bad_Opcode },
5693 { Bad_Opcode },
5694 { Bad_Opcode },
5695 { Bad_Opcode },
5696 { Bad_Opcode },
5697 { Bad_Opcode },
5698 { Bad_Opcode },
5699 /* 58 */
5700 { Bad_Opcode },
5701 { Bad_Opcode },
5702 { Bad_Opcode },
5703 { Bad_Opcode },
5704 { Bad_Opcode },
5705 { Bad_Opcode },
5706 { Bad_Opcode },
5707 { Bad_Opcode },
5708 /* 60 */
5709 { Bad_Opcode },
5710 { Bad_Opcode },
5711 { Bad_Opcode },
5712 { Bad_Opcode },
5713 { Bad_Opcode },
5714 { Bad_Opcode },
5715 { Bad_Opcode },
5716 { Bad_Opcode },
5717 /* 68 */
5718 { Bad_Opcode },
5719 { Bad_Opcode },
5720 { Bad_Opcode },
5721 { Bad_Opcode },
5722 { Bad_Opcode },
5723 { Bad_Opcode },
5724 { Bad_Opcode },
5725 { Bad_Opcode },
5726 /* 70 */
5727 { Bad_Opcode },
5728 { Bad_Opcode },
5729 { Bad_Opcode },
5730 { Bad_Opcode },
5731 { Bad_Opcode },
5732 { Bad_Opcode },
5733 { Bad_Opcode },
5734 { Bad_Opcode },
5735 /* 78 */
5736 { Bad_Opcode },
5737 { Bad_Opcode },
5738 { Bad_Opcode },
5739 { Bad_Opcode },
5740 { Bad_Opcode },
5741 { Bad_Opcode },
5742 { Bad_Opcode },
5743 { Bad_Opcode },
5744 /* 80 */
5745 { Bad_Opcode },
5746 { Bad_Opcode },
5747 { Bad_Opcode },
5748 { Bad_Opcode },
5749 { Bad_Opcode },
5750 { Bad_Opcode },
5751 { Bad_Opcode },
5752 { Bad_Opcode },
5753 /* 88 */
5754 { Bad_Opcode },
5755 { Bad_Opcode },
5756 { Bad_Opcode },
5757 { Bad_Opcode },
5758 { Bad_Opcode },
5759 { Bad_Opcode },
5760 { Bad_Opcode },
5761 { Bad_Opcode },
5762 /* 90 */
5763 { Bad_Opcode },
5764 { Bad_Opcode },
5765 { Bad_Opcode },
5766 { Bad_Opcode },
5767 { Bad_Opcode },
5768 { Bad_Opcode },
5769 { Bad_Opcode },
5770 { Bad_Opcode },
5771 /* 98 */
5772 { Bad_Opcode },
5773 { Bad_Opcode },
5774 { Bad_Opcode },
5775 { Bad_Opcode },
5776 { Bad_Opcode },
5777 { Bad_Opcode },
5778 { Bad_Opcode },
5779 { Bad_Opcode },
5780 /* a0 */
5781 { Bad_Opcode },
5782 { Bad_Opcode },
5783 { Bad_Opcode },
5784 { Bad_Opcode },
5785 { Bad_Opcode },
5786 { Bad_Opcode },
5787 { Bad_Opcode },
5788 { Bad_Opcode },
5789 /* a8 */
5790 { Bad_Opcode },
5791 { Bad_Opcode },
5792 { Bad_Opcode },
5793 { Bad_Opcode },
5794 { Bad_Opcode },
5795 { Bad_Opcode },
5796 { Bad_Opcode },
5797 { Bad_Opcode },
5798 /* b0 */
5799 { Bad_Opcode },
5800 { Bad_Opcode },
5801 { Bad_Opcode },
5802 { Bad_Opcode },
5803 { Bad_Opcode },
5804 { Bad_Opcode },
5805 { Bad_Opcode },
5806 { Bad_Opcode },
5807 /* b8 */
5808 { Bad_Opcode },
5809 { Bad_Opcode },
5810 { Bad_Opcode },
5811 { Bad_Opcode },
5812 { Bad_Opcode },
5813 { Bad_Opcode },
5814 { Bad_Opcode },
5815 { Bad_Opcode },
5816 /* c0 */
5817 { Bad_Opcode },
5818 { Bad_Opcode },
5819 { Bad_Opcode },
5820 { Bad_Opcode },
5821 { Bad_Opcode },
5822 { Bad_Opcode },
5823 { Bad_Opcode },
5824 { Bad_Opcode },
5825 /* c8 */
5826 { Bad_Opcode },
5827 { Bad_Opcode },
5828 { Bad_Opcode },
5829 { Bad_Opcode },
5830 { Bad_Opcode },
5831 { Bad_Opcode },
5832 { Bad_Opcode },
5833 { Bad_Opcode },
5834 /* d0 */
5835 { Bad_Opcode },
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 { Bad_Opcode },
5839 { Bad_Opcode },
5840 { Bad_Opcode },
5841 { Bad_Opcode },
5842 { Bad_Opcode },
5843 /* d8 */
5844 { Bad_Opcode },
5845 { Bad_Opcode },
5846 { Bad_Opcode },
5847 { Bad_Opcode },
5848 { Bad_Opcode },
5849 { Bad_Opcode },
5850 { Bad_Opcode },
5851 { Bad_Opcode },
5852 /* e0 */
5853 { Bad_Opcode },
5854 { Bad_Opcode },
5855 { Bad_Opcode },
5856 { Bad_Opcode },
5857 { Bad_Opcode },
5858 { Bad_Opcode },
5859 { Bad_Opcode },
5860 { Bad_Opcode },
5861 /* e8 */
5862 { Bad_Opcode },
5863 { Bad_Opcode },
5864 { Bad_Opcode },
5865 { Bad_Opcode },
5866 { Bad_Opcode },
5867 { Bad_Opcode },
5868 { Bad_Opcode },
5869 { Bad_Opcode },
5870 /* f0 */
5871 { Bad_Opcode },
5872 { Bad_Opcode },
5873 { Bad_Opcode },
5874 { Bad_Opcode },
5875 { Bad_Opcode },
5876 { Bad_Opcode },
5877 { Bad_Opcode },
5878 { Bad_Opcode },
5879 /* f8 */
5880 { Bad_Opcode },
5881 { Bad_Opcode },
5882 { Bad_Opcode },
5883 { Bad_Opcode },
5884 { Bad_Opcode },
5885 { Bad_Opcode },
5886 { Bad_Opcode },
5887 { Bad_Opcode },
5888 },
5889 };
5890
5891 static const struct dis386 vex_table[][256] = {
5892 /* VEX_0F */
5893 {
5894 /* 00 */
5895 { Bad_Opcode },
5896 { Bad_Opcode },
5897 { Bad_Opcode },
5898 { Bad_Opcode },
5899 { Bad_Opcode },
5900 { Bad_Opcode },
5901 { Bad_Opcode },
5902 { Bad_Opcode },
5903 /* 08 */
5904 { Bad_Opcode },
5905 { Bad_Opcode },
5906 { Bad_Opcode },
5907 { Bad_Opcode },
5908 { Bad_Opcode },
5909 { Bad_Opcode },
5910 { Bad_Opcode },
5911 { Bad_Opcode },
5912 /* 10 */
5913 { PREFIX_TABLE (PREFIX_VEX_0F10) },
5914 { PREFIX_TABLE (PREFIX_VEX_0F11) },
5915 { PREFIX_TABLE (PREFIX_VEX_0F12) },
5916 { MOD_TABLE (MOD_VEX_0F13) },
5917 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5918 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5919 { PREFIX_TABLE (PREFIX_VEX_0F16) },
5920 { MOD_TABLE (MOD_VEX_0F17) },
5921 /* 18 */
5922 { Bad_Opcode },
5923 { Bad_Opcode },
5924 { Bad_Opcode },
5925 { Bad_Opcode },
5926 { Bad_Opcode },
5927 { Bad_Opcode },
5928 { Bad_Opcode },
5929 { Bad_Opcode },
5930 /* 20 */
5931 { Bad_Opcode },
5932 { Bad_Opcode },
5933 { Bad_Opcode },
5934 { Bad_Opcode },
5935 { Bad_Opcode },
5936 { Bad_Opcode },
5937 { Bad_Opcode },
5938 { Bad_Opcode },
5939 /* 28 */
5940 { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
5941 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
5942 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5943 { MOD_TABLE (MOD_VEX_0F2B) },
5944 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5945 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5946 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5947 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5948 /* 30 */
5949 { Bad_Opcode },
5950 { Bad_Opcode },
5951 { Bad_Opcode },
5952 { Bad_Opcode },
5953 { Bad_Opcode },
5954 { Bad_Opcode },
5955 { Bad_Opcode },
5956 { Bad_Opcode },
5957 /* 38 */
5958 { Bad_Opcode },
5959 { Bad_Opcode },
5960 { Bad_Opcode },
5961 { Bad_Opcode },
5962 { Bad_Opcode },
5963 { Bad_Opcode },
5964 { Bad_Opcode },
5965 { Bad_Opcode },
5966 /* 40 */
5967 { Bad_Opcode },
5968 { PREFIX_TABLE (PREFIX_VEX_0F41) },
5969 { PREFIX_TABLE (PREFIX_VEX_0F42) },
5970 { Bad_Opcode },
5971 { PREFIX_TABLE (PREFIX_VEX_0F44) },
5972 { PREFIX_TABLE (PREFIX_VEX_0F45) },
5973 { PREFIX_TABLE (PREFIX_VEX_0F46) },
5974 { PREFIX_TABLE (PREFIX_VEX_0F47) },
5975 /* 48 */
5976 { Bad_Opcode },
5977 { Bad_Opcode },
5978 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
5979 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
5980 { Bad_Opcode },
5981 { Bad_Opcode },
5982 { Bad_Opcode },
5983 { Bad_Opcode },
5984 /* 50 */
5985 { MOD_TABLE (MOD_VEX_0F50) },
5986 { PREFIX_TABLE (PREFIX_VEX_0F51) },
5987 { PREFIX_TABLE (PREFIX_VEX_0F52) },
5988 { PREFIX_TABLE (PREFIX_VEX_0F53) },
5989 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5990 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5991 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5992 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5993 /* 58 */
5994 { PREFIX_TABLE (PREFIX_VEX_0F58) },
5995 { PREFIX_TABLE (PREFIX_VEX_0F59) },
5996 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5997 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5998 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5999 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
6000 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
6001 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
6002 /* 60 */
6003 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
6004 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
6005 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
6006 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
6007 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
6008 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
6009 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
6010 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
6011 /* 68 */
6012 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
6013 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
6014 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
6015 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
6016 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
6017 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
6018 { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6019 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6020 /* 70 */
6021 { PREFIX_TABLE (PREFIX_VEX_0F70) },
6022 { REG_TABLE (REG_VEX_0F71) },
6023 { REG_TABLE (REG_VEX_0F72) },
6024 { REG_TABLE (REG_VEX_0F73) },
6025 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
6026 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
6027 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
6028 { VEX_LEN_TABLE (VEX_LEN_0F77) },
6029 /* 78 */
6030 { Bad_Opcode },
6031 { Bad_Opcode },
6032 { Bad_Opcode },
6033 { Bad_Opcode },
6034 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
6035 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
6036 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6037 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6038 /* 80 */
6039 { Bad_Opcode },
6040 { Bad_Opcode },
6041 { Bad_Opcode },
6042 { Bad_Opcode },
6043 { Bad_Opcode },
6044 { Bad_Opcode },
6045 { Bad_Opcode },
6046 { Bad_Opcode },
6047 /* 88 */
6048 { Bad_Opcode },
6049 { Bad_Opcode },
6050 { Bad_Opcode },
6051 { Bad_Opcode },
6052 { Bad_Opcode },
6053 { Bad_Opcode },
6054 { Bad_Opcode },
6055 { Bad_Opcode },
6056 /* 90 */
6057 { PREFIX_TABLE (PREFIX_VEX_0F90) },
6058 { PREFIX_TABLE (PREFIX_VEX_0F91) },
6059 { PREFIX_TABLE (PREFIX_VEX_0F92) },
6060 { PREFIX_TABLE (PREFIX_VEX_0F93) },
6061 { Bad_Opcode },
6062 { Bad_Opcode },
6063 { Bad_Opcode },
6064 { Bad_Opcode },
6065 /* 98 */
6066 { PREFIX_TABLE (PREFIX_VEX_0F98) },
6067 { PREFIX_TABLE (PREFIX_VEX_0F99) },
6068 { Bad_Opcode },
6069 { Bad_Opcode },
6070 { Bad_Opcode },
6071 { Bad_Opcode },
6072 { Bad_Opcode },
6073 { Bad_Opcode },
6074 /* a0 */
6075 { Bad_Opcode },
6076 { Bad_Opcode },
6077 { Bad_Opcode },
6078 { Bad_Opcode },
6079 { Bad_Opcode },
6080 { Bad_Opcode },
6081 { Bad_Opcode },
6082 { Bad_Opcode },
6083 /* a8 */
6084 { Bad_Opcode },
6085 { Bad_Opcode },
6086 { Bad_Opcode },
6087 { Bad_Opcode },
6088 { Bad_Opcode },
6089 { Bad_Opcode },
6090 { REG_TABLE (REG_VEX_0FAE) },
6091 { Bad_Opcode },
6092 /* b0 */
6093 { Bad_Opcode },
6094 { Bad_Opcode },
6095 { Bad_Opcode },
6096 { Bad_Opcode },
6097 { Bad_Opcode },
6098 { Bad_Opcode },
6099 { Bad_Opcode },
6100 { Bad_Opcode },
6101 /* b8 */
6102 { Bad_Opcode },
6103 { Bad_Opcode },
6104 { Bad_Opcode },
6105 { Bad_Opcode },
6106 { Bad_Opcode },
6107 { Bad_Opcode },
6108 { Bad_Opcode },
6109 { Bad_Opcode },
6110 /* c0 */
6111 { Bad_Opcode },
6112 { Bad_Opcode },
6113 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6114 { Bad_Opcode },
6115 { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6116 { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6117 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6118 { Bad_Opcode },
6119 /* c8 */
6120 { Bad_Opcode },
6121 { Bad_Opcode },
6122 { Bad_Opcode },
6123 { Bad_Opcode },
6124 { Bad_Opcode },
6125 { Bad_Opcode },
6126 { Bad_Opcode },
6127 { Bad_Opcode },
6128 /* d0 */
6129 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6130 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
6131 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
6132 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
6133 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
6134 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
6135 { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6136 { MOD_TABLE (MOD_VEX_0FD7) },
6137 /* d8 */
6138 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
6139 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
6140 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
6141 { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
6142 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
6143 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
6144 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
6145 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
6146 /* e0 */
6147 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
6148 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
6149 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
6150 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
6151 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
6152 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
6153 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6154 { MOD_TABLE (MOD_VEX_0FE7) },
6155 /* e8 */
6156 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
6157 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6158 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
6159 { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
6160 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
6161 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6162 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
6163 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
6164 /* f0 */
6165 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6166 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
6167 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
6168 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
6169 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
6170 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
6171 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
6172 { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6173 /* f8 */
6174 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
6175 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
6176 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
6177 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
6178 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
6179 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
6180 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
6181 { Bad_Opcode },
6182 },
6183 /* VEX_0F38 */
6184 {
6185 /* 00 */
6186 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
6187 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
6188 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
6189 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6190 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
6191 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
6192 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
6193 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6194 /* 08 */
6195 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
6196 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
6197 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
6198 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
6199 { VEX_W_TABLE (VEX_W_0F380C) },
6200 { VEX_W_TABLE (VEX_W_0F380D) },
6201 { VEX_W_TABLE (VEX_W_0F380E) },
6202 { VEX_W_TABLE (VEX_W_0F380F) },
6203 /* 10 */
6204 { Bad_Opcode },
6205 { Bad_Opcode },
6206 { Bad_Opcode },
6207 { VEX_W_TABLE (VEX_W_0F3813) },
6208 { Bad_Opcode },
6209 { Bad_Opcode },
6210 { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6211 { "vptest", { XM, EXx }, PREFIX_DATA },
6212 /* 18 */
6213 { VEX_W_TABLE (VEX_W_0F3818) },
6214 { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6215 { MOD_TABLE (MOD_VEX_0F381A) },
6216 { Bad_Opcode },
6217 { "vpabsb", { XM, EXx }, PREFIX_DATA },
6218 { "vpabsw", { XM, EXx }, PREFIX_DATA },
6219 { "vpabsd", { XM, EXx }, PREFIX_DATA },
6220 { Bad_Opcode },
6221 /* 20 */
6222 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA },
6223 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA },
6224 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA },
6225 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA },
6226 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA },
6227 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA },
6228 { Bad_Opcode },
6229 { Bad_Opcode },
6230 /* 28 */
6231 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
6232 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
6233 { MOD_TABLE (MOD_VEX_0F382A) },
6234 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
6235 { MOD_TABLE (MOD_VEX_0F382C) },
6236 { MOD_TABLE (MOD_VEX_0F382D) },
6237 { MOD_TABLE (MOD_VEX_0F382E) },
6238 { MOD_TABLE (MOD_VEX_0F382F) },
6239 /* 30 */
6240 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
6241 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
6242 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA },
6243 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA },
6244 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA },
6245 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA },
6246 { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6247 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6248 /* 38 */
6249 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
6250 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
6251 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
6252 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
6253 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
6254 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
6255 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
6256 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
6257 /* 40 */
6258 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
6259 { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6260 { Bad_Opcode },
6261 { Bad_Opcode },
6262 { Bad_Opcode },
6263 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6264 { VEX_W_TABLE (VEX_W_0F3846) },
6265 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6266 /* 48 */
6267 { Bad_Opcode },
6268 { X86_64_TABLE (X86_64_VEX_0F3849) },
6269 { Bad_Opcode },
6270 { X86_64_TABLE (X86_64_VEX_0F384B) },
6271 { Bad_Opcode },
6272 { Bad_Opcode },
6273 { Bad_Opcode },
6274 { Bad_Opcode },
6275 /* 50 */
6276 { VEX_W_TABLE (VEX_W_0F3850) },
6277 { VEX_W_TABLE (VEX_W_0F3851) },
6278 { VEX_W_TABLE (VEX_W_0F3852) },
6279 { VEX_W_TABLE (VEX_W_0F3853) },
6280 { Bad_Opcode },
6281 { Bad_Opcode },
6282 { Bad_Opcode },
6283 { Bad_Opcode },
6284 /* 58 */
6285 { VEX_W_TABLE (VEX_W_0F3858) },
6286 { VEX_W_TABLE (VEX_W_0F3859) },
6287 { MOD_TABLE (MOD_VEX_0F385A) },
6288 { Bad_Opcode },
6289 { X86_64_TABLE (X86_64_VEX_0F385C) },
6290 { Bad_Opcode },
6291 { X86_64_TABLE (X86_64_VEX_0F385E) },
6292 { Bad_Opcode },
6293 /* 60 */
6294 { Bad_Opcode },
6295 { Bad_Opcode },
6296 { Bad_Opcode },
6297 { Bad_Opcode },
6298 { Bad_Opcode },
6299 { Bad_Opcode },
6300 { Bad_Opcode },
6301 { Bad_Opcode },
6302 /* 68 */
6303 { Bad_Opcode },
6304 { Bad_Opcode },
6305 { Bad_Opcode },
6306 { Bad_Opcode },
6307 { Bad_Opcode },
6308 { Bad_Opcode },
6309 { Bad_Opcode },
6310 { Bad_Opcode },
6311 /* 70 */
6312 { Bad_Opcode },
6313 { Bad_Opcode },
6314 { Bad_Opcode },
6315 { Bad_Opcode },
6316 { Bad_Opcode },
6317 { Bad_Opcode },
6318 { Bad_Opcode },
6319 { Bad_Opcode },
6320 /* 78 */
6321 { VEX_W_TABLE (VEX_W_0F3878) },
6322 { VEX_W_TABLE (VEX_W_0F3879) },
6323 { Bad_Opcode },
6324 { Bad_Opcode },
6325 { Bad_Opcode },
6326 { Bad_Opcode },
6327 { Bad_Opcode },
6328 { Bad_Opcode },
6329 /* 80 */
6330 { Bad_Opcode },
6331 { Bad_Opcode },
6332 { Bad_Opcode },
6333 { Bad_Opcode },
6334 { Bad_Opcode },
6335 { Bad_Opcode },
6336 { Bad_Opcode },
6337 { Bad_Opcode },
6338 /* 88 */
6339 { Bad_Opcode },
6340 { Bad_Opcode },
6341 { Bad_Opcode },
6342 { Bad_Opcode },
6343 { MOD_TABLE (MOD_VEX_0F388C) },
6344 { Bad_Opcode },
6345 { MOD_TABLE (MOD_VEX_0F388E) },
6346 { Bad_Opcode },
6347 /* 90 */
6348 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6349 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6350 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6351 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6352 { Bad_Opcode },
6353 { Bad_Opcode },
6354 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6355 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6356 /* 98 */
6357 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6358 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6359 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6360 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6361 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6362 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6363 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6364 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6365 /* a0 */
6366 { Bad_Opcode },
6367 { Bad_Opcode },
6368 { Bad_Opcode },
6369 { Bad_Opcode },
6370 { Bad_Opcode },
6371 { Bad_Opcode },
6372 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6373 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6374 /* a8 */
6375 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6376 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6377 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6378 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6379 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6380 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6381 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6382 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6383 /* b0 */
6384 { Bad_Opcode },
6385 { Bad_Opcode },
6386 { Bad_Opcode },
6387 { Bad_Opcode },
6388 { Bad_Opcode },
6389 { Bad_Opcode },
6390 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6391 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6392 /* b8 */
6393 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6394 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6395 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6396 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6397 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6398 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6399 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6400 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6401 /* c0 */
6402 { Bad_Opcode },
6403 { Bad_Opcode },
6404 { Bad_Opcode },
6405 { Bad_Opcode },
6406 { Bad_Opcode },
6407 { Bad_Opcode },
6408 { Bad_Opcode },
6409 { Bad_Opcode },
6410 /* c8 */
6411 { Bad_Opcode },
6412 { Bad_Opcode },
6413 { Bad_Opcode },
6414 { Bad_Opcode },
6415 { Bad_Opcode },
6416 { Bad_Opcode },
6417 { Bad_Opcode },
6418 { VEX_W_TABLE (VEX_W_0F38CF) },
6419 /* d0 */
6420 { Bad_Opcode },
6421 { Bad_Opcode },
6422 { Bad_Opcode },
6423 { Bad_Opcode },
6424 { Bad_Opcode },
6425 { Bad_Opcode },
6426 { Bad_Opcode },
6427 { Bad_Opcode },
6428 /* d8 */
6429 { Bad_Opcode },
6430 { Bad_Opcode },
6431 { Bad_Opcode },
6432 { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6433 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
6434 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
6435 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
6436 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
6437 /* e0 */
6438 { Bad_Opcode },
6439 { Bad_Opcode },
6440 { Bad_Opcode },
6441 { Bad_Opcode },
6442 { Bad_Opcode },
6443 { Bad_Opcode },
6444 { Bad_Opcode },
6445 { Bad_Opcode },
6446 /* e8 */
6447 { Bad_Opcode },
6448 { Bad_Opcode },
6449 { Bad_Opcode },
6450 { Bad_Opcode },
6451 { Bad_Opcode },
6452 { Bad_Opcode },
6453 { Bad_Opcode },
6454 { Bad_Opcode },
6455 /* f0 */
6456 { Bad_Opcode },
6457 { Bad_Opcode },
6458 { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6459 { REG_TABLE (REG_VEX_0F38F3) },
6460 { Bad_Opcode },
6461 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
6462 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
6463 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
6464 /* f8 */
6465 { Bad_Opcode },
6466 { Bad_Opcode },
6467 { Bad_Opcode },
6468 { Bad_Opcode },
6469 { Bad_Opcode },
6470 { Bad_Opcode },
6471 { Bad_Opcode },
6472 { Bad_Opcode },
6473 },
6474 /* VEX_0F3A */
6475 {
6476 /* 00 */
6477 { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6478 { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6479 { VEX_W_TABLE (VEX_W_0F3A02) },
6480 { Bad_Opcode },
6481 { VEX_W_TABLE (VEX_W_0F3A04) },
6482 { VEX_W_TABLE (VEX_W_0F3A05) },
6483 { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6484 { Bad_Opcode },
6485 /* 08 */
6486 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6487 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6488 { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
6489 { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
6490 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6491 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6492 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6493 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6494 /* 10 */
6495 { Bad_Opcode },
6496 { Bad_Opcode },
6497 { Bad_Opcode },
6498 { Bad_Opcode },
6499 { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6500 { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6501 { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6502 { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6503 /* 18 */
6504 { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6505 { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6506 { Bad_Opcode },
6507 { Bad_Opcode },
6508 { Bad_Opcode },
6509 { VEX_W_TABLE (VEX_W_0F3A1D) },
6510 { Bad_Opcode },
6511 { Bad_Opcode },
6512 /* 20 */
6513 { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6514 { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6515 { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6516 { Bad_Opcode },
6517 { Bad_Opcode },
6518 { Bad_Opcode },
6519 { Bad_Opcode },
6520 { Bad_Opcode },
6521 /* 28 */
6522 { Bad_Opcode },
6523 { Bad_Opcode },
6524 { Bad_Opcode },
6525 { Bad_Opcode },
6526 { Bad_Opcode },
6527 { Bad_Opcode },
6528 { Bad_Opcode },
6529 { Bad_Opcode },
6530 /* 30 */
6531 { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6532 { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6533 { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6534 { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6535 { Bad_Opcode },
6536 { Bad_Opcode },
6537 { Bad_Opcode },
6538 { Bad_Opcode },
6539 /* 38 */
6540 { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6541 { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6542 { Bad_Opcode },
6543 { Bad_Opcode },
6544 { Bad_Opcode },
6545 { Bad_Opcode },
6546 { Bad_Opcode },
6547 { Bad_Opcode },
6548 /* 40 */
6549 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6550 { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6551 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6552 { Bad_Opcode },
6553 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6554 { Bad_Opcode },
6555 { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6556 { Bad_Opcode },
6557 /* 48 */
6558 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6559 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6560 { VEX_W_TABLE (VEX_W_0F3A4A) },
6561 { VEX_W_TABLE (VEX_W_0F3A4B) },
6562 { VEX_W_TABLE (VEX_W_0F3A4C) },
6563 { Bad_Opcode },
6564 { Bad_Opcode },
6565 { Bad_Opcode },
6566 /* 50 */
6567 { Bad_Opcode },
6568 { Bad_Opcode },
6569 { Bad_Opcode },
6570 { Bad_Opcode },
6571 { Bad_Opcode },
6572 { Bad_Opcode },
6573 { Bad_Opcode },
6574 { Bad_Opcode },
6575 /* 58 */
6576 { Bad_Opcode },
6577 { Bad_Opcode },
6578 { Bad_Opcode },
6579 { Bad_Opcode },
6580 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6581 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6582 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6583 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6584 /* 60 */
6585 { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6586 { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6587 { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6588 { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6589 { Bad_Opcode },
6590 { Bad_Opcode },
6591 { Bad_Opcode },
6592 { Bad_Opcode },
6593 /* 68 */
6594 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6595 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6596 { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6597 { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6598 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6599 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6600 { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6601 { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6602 /* 70 */
6603 { Bad_Opcode },
6604 { Bad_Opcode },
6605 { Bad_Opcode },
6606 { Bad_Opcode },
6607 { Bad_Opcode },
6608 { Bad_Opcode },
6609 { Bad_Opcode },
6610 { Bad_Opcode },
6611 /* 78 */
6612 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6613 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6614 { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6615 { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6616 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6617 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6618 { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6619 { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6620 /* 80 */
6621 { Bad_Opcode },
6622 { Bad_Opcode },
6623 { Bad_Opcode },
6624 { Bad_Opcode },
6625 { Bad_Opcode },
6626 { Bad_Opcode },
6627 { Bad_Opcode },
6628 { Bad_Opcode },
6629 /* 88 */
6630 { Bad_Opcode },
6631 { Bad_Opcode },
6632 { Bad_Opcode },
6633 { Bad_Opcode },
6634 { Bad_Opcode },
6635 { Bad_Opcode },
6636 { Bad_Opcode },
6637 { Bad_Opcode },
6638 /* 90 */
6639 { Bad_Opcode },
6640 { Bad_Opcode },
6641 { Bad_Opcode },
6642 { Bad_Opcode },
6643 { Bad_Opcode },
6644 { Bad_Opcode },
6645 { Bad_Opcode },
6646 { Bad_Opcode },
6647 /* 98 */
6648 { Bad_Opcode },
6649 { Bad_Opcode },
6650 { Bad_Opcode },
6651 { Bad_Opcode },
6652 { Bad_Opcode },
6653 { Bad_Opcode },
6654 { Bad_Opcode },
6655 { Bad_Opcode },
6656 /* a0 */
6657 { Bad_Opcode },
6658 { Bad_Opcode },
6659 { Bad_Opcode },
6660 { Bad_Opcode },
6661 { Bad_Opcode },
6662 { Bad_Opcode },
6663 { Bad_Opcode },
6664 { Bad_Opcode },
6665 /* a8 */
6666 { Bad_Opcode },
6667 { Bad_Opcode },
6668 { Bad_Opcode },
6669 { Bad_Opcode },
6670 { Bad_Opcode },
6671 { Bad_Opcode },
6672 { Bad_Opcode },
6673 { Bad_Opcode },
6674 /* b0 */
6675 { Bad_Opcode },
6676 { Bad_Opcode },
6677 { Bad_Opcode },
6678 { Bad_Opcode },
6679 { Bad_Opcode },
6680 { Bad_Opcode },
6681 { Bad_Opcode },
6682 { Bad_Opcode },
6683 /* b8 */
6684 { Bad_Opcode },
6685 { Bad_Opcode },
6686 { Bad_Opcode },
6687 { Bad_Opcode },
6688 { Bad_Opcode },
6689 { Bad_Opcode },
6690 { Bad_Opcode },
6691 { Bad_Opcode },
6692 /* c0 */
6693 { Bad_Opcode },
6694 { Bad_Opcode },
6695 { Bad_Opcode },
6696 { Bad_Opcode },
6697 { Bad_Opcode },
6698 { Bad_Opcode },
6699 { Bad_Opcode },
6700 { Bad_Opcode },
6701 /* c8 */
6702 { Bad_Opcode },
6703 { Bad_Opcode },
6704 { Bad_Opcode },
6705 { Bad_Opcode },
6706 { Bad_Opcode },
6707 { Bad_Opcode },
6708 { VEX_W_TABLE (VEX_W_0F3ACE) },
6709 { VEX_W_TABLE (VEX_W_0F3ACF) },
6710 /* d0 */
6711 { Bad_Opcode },
6712 { Bad_Opcode },
6713 { Bad_Opcode },
6714 { Bad_Opcode },
6715 { Bad_Opcode },
6716 { Bad_Opcode },
6717 { Bad_Opcode },
6718 { Bad_Opcode },
6719 /* d8 */
6720 { Bad_Opcode },
6721 { Bad_Opcode },
6722 { Bad_Opcode },
6723 { Bad_Opcode },
6724 { Bad_Opcode },
6725 { Bad_Opcode },
6726 { Bad_Opcode },
6727 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6728 /* e0 */
6729 { Bad_Opcode },
6730 { Bad_Opcode },
6731 { Bad_Opcode },
6732 { Bad_Opcode },
6733 { Bad_Opcode },
6734 { Bad_Opcode },
6735 { Bad_Opcode },
6736 { Bad_Opcode },
6737 /* e8 */
6738 { Bad_Opcode },
6739 { Bad_Opcode },
6740 { Bad_Opcode },
6741 { Bad_Opcode },
6742 { Bad_Opcode },
6743 { Bad_Opcode },
6744 { Bad_Opcode },
6745 { Bad_Opcode },
6746 /* f0 */
6747 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
6748 { Bad_Opcode },
6749 { Bad_Opcode },
6750 { Bad_Opcode },
6751 { Bad_Opcode },
6752 { Bad_Opcode },
6753 { Bad_Opcode },
6754 { Bad_Opcode },
6755 /* f8 */
6756 { Bad_Opcode },
6757 { Bad_Opcode },
6758 { Bad_Opcode },
6759 { Bad_Opcode },
6760 { Bad_Opcode },
6761 { Bad_Opcode },
6762 { Bad_Opcode },
6763 { Bad_Opcode },
6764 },
6765 };
6766
6767 #include "i386-dis-evex.h"
6768
6769 static const struct dis386 vex_len_table[][2] = {
6770 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6771 {
6772 { "vmovlpX", { XM, Vex, EXq }, 0 },
6773 },
6774
6775 /* VEX_LEN_0F12_P_0_M_1 */
6776 {
6777 { "vmovhlps", { XM, Vex, EXq }, 0 },
6778 },
6779
6780 /* VEX_LEN_0F13_M_0 */
6781 {
6782 { "vmovlpX", { EXq, XM }, PREFIX_OPCODE },
6783 },
6784
6785 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6786 {
6787 { "vmovhpX", { XM, Vex, EXq }, 0 },
6788 },
6789
6790 /* VEX_LEN_0F16_P_0_M_1 */
6791 {
6792 { "vmovlhps", { XM, Vex, EXq }, 0 },
6793 },
6794
6795 /* VEX_LEN_0F17_M_0 */
6796 {
6797 { "vmovhpX", { EXq, XM }, PREFIX_OPCODE },
6798 },
6799
6800 /* VEX_LEN_0F41_P_0 */
6801 {
6802 { Bad_Opcode },
6803 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
6804 },
6805 /* VEX_LEN_0F41_P_2 */
6806 {
6807 { Bad_Opcode },
6808 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
6809 },
6810 /* VEX_LEN_0F42_P_0 */
6811 {
6812 { Bad_Opcode },
6813 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
6814 },
6815 /* VEX_LEN_0F42_P_2 */
6816 {
6817 { Bad_Opcode },
6818 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
6819 },
6820 /* VEX_LEN_0F44_P_0 */
6821 {
6822 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
6823 },
6824 /* VEX_LEN_0F44_P_2 */
6825 {
6826 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
6827 },
6828 /* VEX_LEN_0F45_P_0 */
6829 {
6830 { Bad_Opcode },
6831 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
6832 },
6833 /* VEX_LEN_0F45_P_2 */
6834 {
6835 { Bad_Opcode },
6836 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
6837 },
6838 /* VEX_LEN_0F46_P_0 */
6839 {
6840 { Bad_Opcode },
6841 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
6842 },
6843 /* VEX_LEN_0F46_P_2 */
6844 {
6845 { Bad_Opcode },
6846 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
6847 },
6848 /* VEX_LEN_0F47_P_0 */
6849 {
6850 { Bad_Opcode },
6851 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
6852 },
6853 /* VEX_LEN_0F47_P_2 */
6854 {
6855 { Bad_Opcode },
6856 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
6857 },
6858 /* VEX_LEN_0F4A_P_0 */
6859 {
6860 { Bad_Opcode },
6861 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
6862 },
6863 /* VEX_LEN_0F4A_P_2 */
6864 {
6865 { Bad_Opcode },
6866 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
6867 },
6868 /* VEX_LEN_0F4B_P_0 */
6869 {
6870 { Bad_Opcode },
6871 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
6872 },
6873 /* VEX_LEN_0F4B_P_2 */
6874 {
6875 { Bad_Opcode },
6876 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
6877 },
6878
6879 /* VEX_LEN_0F6E */
6880 {
6881 { "vmovK", { XMScalar, Edq }, PREFIX_DATA },
6882 },
6883
6884 /* VEX_LEN_0F77 */
6885 {
6886 { "vzeroupper", { XX }, 0 },
6887 { "vzeroall", { XX }, 0 },
6888 },
6889
6890 /* VEX_LEN_0F7E_P_1 */
6891 {
6892 { "vmovq", { XMScalar, EXxmm_mq }, 0 },
6893 },
6894
6895 /* VEX_LEN_0F7E_P_2 */
6896 {
6897 { "vmovK", { Edq, XMScalar }, 0 },
6898 },
6899
6900 /* VEX_LEN_0F90_P_0 */
6901 {
6902 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
6903 },
6904
6905 /* VEX_LEN_0F90_P_2 */
6906 {
6907 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
6908 },
6909
6910 /* VEX_LEN_0F91_P_0 */
6911 {
6912 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
6913 },
6914
6915 /* VEX_LEN_0F91_P_2 */
6916 {
6917 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
6918 },
6919
6920 /* VEX_LEN_0F92_P_0 */
6921 {
6922 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
6923 },
6924
6925 /* VEX_LEN_0F92_P_2 */
6926 {
6927 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
6928 },
6929
6930 /* VEX_LEN_0F92_P_3 */
6931 {
6932 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
6933 },
6934
6935 /* VEX_LEN_0F93_P_0 */
6936 {
6937 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
6938 },
6939
6940 /* VEX_LEN_0F93_P_2 */
6941 {
6942 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
6943 },
6944
6945 /* VEX_LEN_0F93_P_3 */
6946 {
6947 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
6948 },
6949
6950 /* VEX_LEN_0F98_P_0 */
6951 {
6952 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
6953 },
6954
6955 /* VEX_LEN_0F98_P_2 */
6956 {
6957 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
6958 },
6959
6960 /* VEX_LEN_0F99_P_0 */
6961 {
6962 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
6963 },
6964
6965 /* VEX_LEN_0F99_P_2 */
6966 {
6967 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
6968 },
6969
6970 /* VEX_LEN_0FAE_R_2_M_0 */
6971 {
6972 { "vldmxcsr", { Md }, 0 },
6973 },
6974
6975 /* VEX_LEN_0FAE_R_3_M_0 */
6976 {
6977 { "vstmxcsr", { Md }, 0 },
6978 },
6979
6980 /* VEX_LEN_0FC4 */
6981 {
6982 { "vpinsrw", { XM, Vex, Edqw, Ib }, PREFIX_DATA },
6983 },
6984
6985 /* VEX_LEN_0FC5 */
6986 {
6987 { "vpextrw", { Gdq, XS, Ib }, PREFIX_DATA },
6988 },
6989
6990 /* VEX_LEN_0FD6 */
6991 {
6992 { "vmovq", { EXqS, XMScalar }, PREFIX_DATA },
6993 },
6994
6995 /* VEX_LEN_0FF7 */
6996 {
6997 { "vmaskmovdqu", { XM, XS }, PREFIX_DATA },
6998 },
6999
7000 /* VEX_LEN_0F3816 */
7001 {
7002 { Bad_Opcode },
7003 { VEX_W_TABLE (VEX_W_0F3816_L_1) },
7004 },
7005
7006 /* VEX_LEN_0F3819 */
7007 {
7008 { Bad_Opcode },
7009 { VEX_W_TABLE (VEX_W_0F3819_L_1) },
7010 },
7011
7012 /* VEX_LEN_0F381A_M_0 */
7013 {
7014 { Bad_Opcode },
7015 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
7016 },
7017
7018 /* VEX_LEN_0F3836 */
7019 {
7020 { Bad_Opcode },
7021 { VEX_W_TABLE (VEX_W_0F3836) },
7022 },
7023
7024 /* VEX_LEN_0F3841 */
7025 {
7026 { "vphminposuw", { XM, EXx }, PREFIX_DATA },
7027 },
7028
7029 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
7030 {
7031 { "ldtilecfg", { M }, 0 },
7032 },
7033
7034 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
7035 {
7036 { "tilerelease", { Skip_MODRM }, 0 },
7037 },
7038
7039 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
7040 {
7041 { "sttilecfg", { M }, 0 },
7042 },
7043
7044 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
7045 {
7046 { "tilezero", { TMM, Skip_MODRM }, 0 },
7047 },
7048
7049 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
7050 {
7051 { "tilestored", { MVexSIBMEM, TMM }, 0 },
7052 },
7053 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
7054 {
7055 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
7056 },
7057
7058 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
7059 {
7060 { "tileloadd", { TMM, MVexSIBMEM }, 0 },
7061 },
7062
7063 /* VEX_LEN_0F385A_M_0 */
7064 {
7065 { Bad_Opcode },
7066 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
7067 },
7068
7069 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
7070 {
7071 { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
7072 },
7073
7074 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
7075 {
7076 { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
7077 },
7078
7079 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
7080 {
7081 { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
7082 },
7083
7084 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
7085 {
7086 { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
7087 },
7088
7089 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
7090 {
7091 { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
7092 },
7093
7094 /* VEX_LEN_0F38DB */
7095 {
7096 { "vaesimc", { XM, EXx }, PREFIX_DATA },
7097 },
7098
7099 /* VEX_LEN_0F38F2 */
7100 {
7101 { "andnS", { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
7102 },
7103
7104 /* VEX_LEN_0F38F3_R_1 */
7105 {
7106 { "blsrS", { VexGdq, Edq }, PREFIX_OPCODE },
7107 },
7108
7109 /* VEX_LEN_0F38F3_R_2 */
7110 {
7111 { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE },
7112 },
7113
7114 /* VEX_LEN_0F38F3_R_3 */
7115 {
7116 { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE },
7117 },
7118
7119 /* VEX_LEN_0F38F5_P_0 */
7120 {
7121 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
7122 },
7123
7124 /* VEX_LEN_0F38F5_P_1 */
7125 {
7126 { "pextS", { Gdq, VexGdq, Edq }, 0 },
7127 },
7128
7129 /* VEX_LEN_0F38F5_P_3 */
7130 {
7131 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
7132 },
7133
7134 /* VEX_LEN_0F38F6_P_3 */
7135 {
7136 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
7137 },
7138
7139 /* VEX_LEN_0F38F7_P_0 */
7140 {
7141 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
7142 },
7143
7144 /* VEX_LEN_0F38F7_P_1 */
7145 {
7146 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
7147 },
7148
7149 /* VEX_LEN_0F38F7_P_2 */
7150 {
7151 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
7152 },
7153
7154 /* VEX_LEN_0F38F7_P_3 */
7155 {
7156 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
7157 },
7158
7159 /* VEX_LEN_0F3A00 */
7160 {
7161 { Bad_Opcode },
7162 { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7163 },
7164
7165 /* VEX_LEN_0F3A01 */
7166 {
7167 { Bad_Opcode },
7168 { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7169 },
7170
7171 /* VEX_LEN_0F3A06 */
7172 {
7173 { Bad_Opcode },
7174 { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7175 },
7176
7177 /* VEX_LEN_0F3A14 */
7178 {
7179 { "vpextrb", { Edqb, XM, Ib }, PREFIX_DATA },
7180 },
7181
7182 /* VEX_LEN_0F3A15 */
7183 {
7184 { "vpextrw", { Edqw, XM, Ib }, PREFIX_DATA },
7185 },
7186
7187 /* VEX_LEN_0F3A16 */
7188 {
7189 { "vpextrK", { Edq, XM, Ib }, PREFIX_DATA },
7190 },
7191
7192 /* VEX_LEN_0F3A17 */
7193 {
7194 { "vextractps", { Edqd, XM, Ib }, PREFIX_DATA },
7195 },
7196
7197 /* VEX_LEN_0F3A18 */
7198 {
7199 { Bad_Opcode },
7200 { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7201 },
7202
7203 /* VEX_LEN_0F3A19 */
7204 {
7205 { Bad_Opcode },
7206 { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7207 },
7208
7209 /* VEX_LEN_0F3A20 */
7210 {
7211 { "vpinsrb", { XM, Vex, Edqb, Ib }, PREFIX_DATA },
7212 },
7213
7214 /* VEX_LEN_0F3A21 */
7215 {
7216 { "vinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA },
7217 },
7218
7219 /* VEX_LEN_0F3A22 */
7220 {
7221 { "vpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
7222 },
7223
7224 /* VEX_LEN_0F3A30 */
7225 {
7226 { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7227 },
7228
7229 /* VEX_LEN_0F3A31 */
7230 {
7231 { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7232 },
7233
7234 /* VEX_LEN_0F3A32 */
7235 {
7236 { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7237 },
7238
7239 /* VEX_LEN_0F3A33 */
7240 {
7241 { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7242 },
7243
7244 /* VEX_LEN_0F3A38 */
7245 {
7246 { Bad_Opcode },
7247 { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7248 },
7249
7250 /* VEX_LEN_0F3A39 */
7251 {
7252 { Bad_Opcode },
7253 { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7254 },
7255
7256 /* VEX_LEN_0F3A41 */
7257 {
7258 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7259 },
7260
7261 /* VEX_LEN_0F3A46 */
7262 {
7263 { Bad_Opcode },
7264 { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7265 },
7266
7267 /* VEX_LEN_0F3A60 */
7268 {
7269 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7270 },
7271
7272 /* VEX_LEN_0F3A61 */
7273 {
7274 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7275 },
7276
7277 /* VEX_LEN_0F3A62 */
7278 {
7279 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7280 },
7281
7282 /* VEX_LEN_0F3A63 */
7283 {
7284 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7285 },
7286
7287 /* VEX_LEN_0F3ADF */
7288 {
7289 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7290 },
7291
7292 /* VEX_LEN_0F3AF0_P_3 */
7293 {
7294 { "rorxS", { Gdq, Edq, Ib }, 0 },
7295 },
7296
7297 /* VEX_LEN_0FXOP_08_85 */
7298 {
7299 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7300 },
7301
7302 /* VEX_LEN_0FXOP_08_86 */
7303 {
7304 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7305 },
7306
7307 /* VEX_LEN_0FXOP_08_87 */
7308 {
7309 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7310 },
7311
7312 /* VEX_LEN_0FXOP_08_8E */
7313 {
7314 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7315 },
7316
7317 /* VEX_LEN_0FXOP_08_8F */
7318 {
7319 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7320 },
7321
7322 /* VEX_LEN_0FXOP_08_95 */
7323 {
7324 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7325 },
7326
7327 /* VEX_LEN_0FXOP_08_96 */
7328 {
7329 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7330 },
7331
7332 /* VEX_LEN_0FXOP_08_97 */
7333 {
7334 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7335 },
7336
7337 /* VEX_LEN_0FXOP_08_9E */
7338 {
7339 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7340 },
7341
7342 /* VEX_LEN_0FXOP_08_9F */
7343 {
7344 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7345 },
7346
7347 /* VEX_LEN_0FXOP_08_A3 */
7348 {
7349 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
7350 },
7351
7352 /* VEX_LEN_0FXOP_08_A6 */
7353 {
7354 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7355 },
7356
7357 /* VEX_LEN_0FXOP_08_B6 */
7358 {
7359 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7360 },
7361
7362 /* VEX_LEN_0FXOP_08_C0 */
7363 {
7364 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7365 },
7366
7367 /* VEX_LEN_0FXOP_08_C1 */
7368 {
7369 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7370 },
7371
7372 /* VEX_LEN_0FXOP_08_C2 */
7373 {
7374 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7375 },
7376
7377 /* VEX_LEN_0FXOP_08_C3 */
7378 {
7379 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7380 },
7381
7382 /* VEX_LEN_0FXOP_08_CC */
7383 {
7384 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7385 },
7386
7387 /* VEX_LEN_0FXOP_08_CD */
7388 {
7389 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7390 },
7391
7392 /* VEX_LEN_0FXOP_08_CE */
7393 {
7394 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7395 },
7396
7397 /* VEX_LEN_0FXOP_08_CF */
7398 {
7399 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7400 },
7401
7402 /* VEX_LEN_0FXOP_08_EC */
7403 {
7404 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7405 },
7406
7407 /* VEX_LEN_0FXOP_08_ED */
7408 {
7409 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7410 },
7411
7412 /* VEX_LEN_0FXOP_08_EE */
7413 {
7414 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7415 },
7416
7417 /* VEX_LEN_0FXOP_08_EF */
7418 {
7419 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7420 },
7421
7422 /* VEX_LEN_0FXOP_09_01 */
7423 {
7424 { REG_TABLE (REG_0FXOP_09_01_L_0) },
7425 },
7426
7427 /* VEX_LEN_0FXOP_09_02 */
7428 {
7429 { REG_TABLE (REG_0FXOP_09_02_L_0) },
7430 },
7431
7432 /* VEX_LEN_0FXOP_09_12_M_1 */
7433 {
7434 { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
7435 },
7436
7437 /* VEX_LEN_0FXOP_09_82_W_0 */
7438 {
7439 { "vfrczss", { XM, EXd }, 0 },
7440 },
7441
7442 /* VEX_LEN_0FXOP_09_83_W_0 */
7443 {
7444 { "vfrczsd", { XM, EXq }, 0 },
7445 },
7446
7447 /* VEX_LEN_0FXOP_09_90 */
7448 {
7449 { "vprotb", { XM, EXx, VexW }, 0 },
7450 },
7451
7452 /* VEX_LEN_0FXOP_09_91 */
7453 {
7454 { "vprotw", { XM, EXx, VexW }, 0 },
7455 },
7456
7457 /* VEX_LEN_0FXOP_09_92 */
7458 {
7459 { "vprotd", { XM, EXx, VexW }, 0 },
7460 },
7461
7462 /* VEX_LEN_0FXOP_09_93 */
7463 {
7464 { "vprotq", { XM, EXx, VexW }, 0 },
7465 },
7466
7467 /* VEX_LEN_0FXOP_09_94 */
7468 {
7469 { "vpshlb", { XM, EXx, VexW }, 0 },
7470 },
7471
7472 /* VEX_LEN_0FXOP_09_95 */
7473 {
7474 { "vpshlw", { XM, EXx, VexW }, 0 },
7475 },
7476
7477 /* VEX_LEN_0FXOP_09_96 */
7478 {
7479 { "vpshld", { XM, EXx, VexW }, 0 },
7480 },
7481
7482 /* VEX_LEN_0FXOP_09_97 */
7483 {
7484 { "vpshlq", { XM, EXx, VexW }, 0 },
7485 },
7486
7487 /* VEX_LEN_0FXOP_09_98 */
7488 {
7489 { "vpshab", { XM, EXx, VexW }, 0 },
7490 },
7491
7492 /* VEX_LEN_0FXOP_09_99 */
7493 {
7494 { "vpshaw", { XM, EXx, VexW }, 0 },
7495 },
7496
7497 /* VEX_LEN_0FXOP_09_9A */
7498 {
7499 { "vpshad", { XM, EXx, VexW }, 0 },
7500 },
7501
7502 /* VEX_LEN_0FXOP_09_9B */
7503 {
7504 { "vpshaq", { XM, EXx, VexW }, 0 },
7505 },
7506
7507 /* VEX_LEN_0FXOP_09_C1 */
7508 {
7509 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7510 },
7511
7512 /* VEX_LEN_0FXOP_09_C2 */
7513 {
7514 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7515 },
7516
7517 /* VEX_LEN_0FXOP_09_C3 */
7518 {
7519 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7520 },
7521
7522 /* VEX_LEN_0FXOP_09_C6 */
7523 {
7524 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7525 },
7526
7527 /* VEX_LEN_0FXOP_09_C7 */
7528 {
7529 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7530 },
7531
7532 /* VEX_LEN_0FXOP_09_CB */
7533 {
7534 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7535 },
7536
7537 /* VEX_LEN_0FXOP_09_D1 */
7538 {
7539 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7540 },
7541
7542 /* VEX_LEN_0FXOP_09_D2 */
7543 {
7544 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7545 },
7546
7547 /* VEX_LEN_0FXOP_09_D3 */
7548 {
7549 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7550 },
7551
7552 /* VEX_LEN_0FXOP_09_D6 */
7553 {
7554 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7555 },
7556
7557 /* VEX_LEN_0FXOP_09_D7 */
7558 {
7559 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7560 },
7561
7562 /* VEX_LEN_0FXOP_09_DB */
7563 {
7564 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7565 },
7566
7567 /* VEX_LEN_0FXOP_09_E1 */
7568 {
7569 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7570 },
7571
7572 /* VEX_LEN_0FXOP_09_E2 */
7573 {
7574 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7575 },
7576
7577 /* VEX_LEN_0FXOP_09_E3 */
7578 {
7579 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7580 },
7581
7582 /* VEX_LEN_0FXOP_0A_12 */
7583 {
7584 { REG_TABLE (REG_0FXOP_0A_12_L_0) },
7585 },
7586 };
7587
7588 #include "i386-dis-evex-len.h"
7589
7590 static const struct dis386 vex_w_table[][2] = {
7591 {
7592 /* VEX_W_0F41_P_0_LEN_1 */
7593 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
7594 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
7595 },
7596 {
7597 /* VEX_W_0F41_P_2_LEN_1 */
7598 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
7599 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
7600 },
7601 {
7602 /* VEX_W_0F42_P_0_LEN_1 */
7603 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
7604 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
7605 },
7606 {
7607 /* VEX_W_0F42_P_2_LEN_1 */
7608 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
7609 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
7610 },
7611 {
7612 /* VEX_W_0F44_P_0_LEN_0 */
7613 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
7614 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
7615 },
7616 {
7617 /* VEX_W_0F44_P_2_LEN_0 */
7618 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
7619 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
7620 },
7621 {
7622 /* VEX_W_0F45_P_0_LEN_1 */
7623 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
7624 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
7625 },
7626 {
7627 /* VEX_W_0F45_P_2_LEN_1 */
7628 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
7629 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
7630 },
7631 {
7632 /* VEX_W_0F46_P_0_LEN_1 */
7633 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
7634 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
7635 },
7636 {
7637 /* VEX_W_0F46_P_2_LEN_1 */
7638 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
7639 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
7640 },
7641 {
7642 /* VEX_W_0F47_P_0_LEN_1 */
7643 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
7644 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
7645 },
7646 {
7647 /* VEX_W_0F47_P_2_LEN_1 */
7648 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
7649 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
7650 },
7651 {
7652 /* VEX_W_0F4A_P_0_LEN_1 */
7653 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
7654 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
7655 },
7656 {
7657 /* VEX_W_0F4A_P_2_LEN_1 */
7658 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
7659 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
7660 },
7661 {
7662 /* VEX_W_0F4B_P_0_LEN_1 */
7663 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
7664 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
7665 },
7666 {
7667 /* VEX_W_0F4B_P_2_LEN_1 */
7668 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
7669 },
7670 {
7671 /* VEX_W_0F90_P_0_LEN_0 */
7672 { "kmovw", { MaskG, MaskE }, 0 },
7673 { "kmovq", { MaskG, MaskE }, 0 },
7674 },
7675 {
7676 /* VEX_W_0F90_P_2_LEN_0 */
7677 { "kmovb", { MaskG, MaskBDE }, 0 },
7678 { "kmovd", { MaskG, MaskBDE }, 0 },
7679 },
7680 {
7681 /* VEX_W_0F91_P_0_LEN_0 */
7682 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
7683 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
7684 },
7685 {
7686 /* VEX_W_0F91_P_2_LEN_0 */
7687 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
7688 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
7689 },
7690 {
7691 /* VEX_W_0F92_P_0_LEN_0 */
7692 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
7693 },
7694 {
7695 /* VEX_W_0F92_P_2_LEN_0 */
7696 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
7697 },
7698 {
7699 /* VEX_W_0F93_P_0_LEN_0 */
7700 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
7701 },
7702 {
7703 /* VEX_W_0F93_P_2_LEN_0 */
7704 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
7705 },
7706 {
7707 /* VEX_W_0F98_P_0_LEN_0 */
7708 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
7709 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
7710 },
7711 {
7712 /* VEX_W_0F98_P_2_LEN_0 */
7713 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
7714 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
7715 },
7716 {
7717 /* VEX_W_0F99_P_0_LEN_0 */
7718 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
7719 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
7720 },
7721 {
7722 /* VEX_W_0F99_P_2_LEN_0 */
7723 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
7724 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
7725 },
7726 {
7727 /* VEX_W_0F380C */
7728 { "vpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7729 },
7730 {
7731 /* VEX_W_0F380D */
7732 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
7733 },
7734 {
7735 /* VEX_W_0F380E */
7736 { "vtestps", { XM, EXx }, PREFIX_DATA },
7737 },
7738 {
7739 /* VEX_W_0F380F */
7740 { "vtestpd", { XM, EXx }, PREFIX_DATA },
7741 },
7742 {
7743 /* VEX_W_0F3813 */
7744 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7745 },
7746 {
7747 /* VEX_W_0F3816_L_1 */
7748 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
7749 },
7750 {
7751 /* VEX_W_0F3818 */
7752 { "vbroadcastss", { XM, EXxmm_md }, PREFIX_DATA },
7753 },
7754 {
7755 /* VEX_W_0F3819_L_1 */
7756 { "vbroadcastsd", { XM, EXxmm_mq }, PREFIX_DATA },
7757 },
7758 {
7759 /* VEX_W_0F381A_M_0_L_1 */
7760 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7761 },
7762 {
7763 /* VEX_W_0F382C_M_0 */
7764 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
7765 },
7766 {
7767 /* VEX_W_0F382D_M_0 */
7768 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
7769 },
7770 {
7771 /* VEX_W_0F382E_M_0 */
7772 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
7773 },
7774 {
7775 /* VEX_W_0F382F_M_0 */
7776 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
7777 },
7778 {
7779 /* VEX_W_0F3836 */
7780 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
7781 },
7782 {
7783 /* VEX_W_0F3846 */
7784 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
7785 },
7786 {
7787 /* VEX_W_0F3849_X86_64_P_0 */
7788 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7789 },
7790 {
7791 /* VEX_W_0F3849_X86_64_P_2 */
7792 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7793 },
7794 {
7795 /* VEX_W_0F3849_X86_64_P_3 */
7796 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7797 },
7798 {
7799 /* VEX_W_0F384B_X86_64_P_1 */
7800 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7801 },
7802 {
7803 /* VEX_W_0F384B_X86_64_P_2 */
7804 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7805 },
7806 {
7807 /* VEX_W_0F384B_X86_64_P_3 */
7808 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7809 },
7810 {
7811 /* VEX_W_0F3850 */
7812 { "%XV vpdpbusd", { XM, Vex, EXx }, 0 },
7813 },
7814 {
7815 /* VEX_W_0F3851 */
7816 { "%XV vpdpbusds", { XM, Vex, EXx }, 0 },
7817 },
7818 {
7819 /* VEX_W_0F3852 */
7820 { "%XV vpdpwssd", { XM, Vex, EXx }, 0 },
7821 },
7822 {
7823 /* VEX_W_0F3853 */
7824 { "%XV vpdpwssds", { XM, Vex, EXx }, 0 },
7825 },
7826 {
7827 /* VEX_W_0F3858 */
7828 { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
7829 },
7830 {
7831 /* VEX_W_0F3859 */
7832 { "vpbroadcastq", { XM, EXxmm_mq }, PREFIX_DATA },
7833 },
7834 {
7835 /* VEX_W_0F385A_M_0_L_0 */
7836 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7837 },
7838 {
7839 /* VEX_W_0F385C_X86_64_P_1 */
7840 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7841 },
7842 {
7843 /* VEX_W_0F385E_X86_64_P_0 */
7844 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7845 },
7846 {
7847 /* VEX_W_0F385E_X86_64_P_1 */
7848 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7849 },
7850 {
7851 /* VEX_W_0F385E_X86_64_P_2 */
7852 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7853 },
7854 {
7855 /* VEX_W_0F385E_X86_64_P_3 */
7856 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7857 },
7858 {
7859 /* VEX_W_0F3878 */
7860 { "vpbroadcastb", { XM, EXxmm_mb }, PREFIX_DATA },
7861 },
7862 {
7863 /* VEX_W_0F3879 */
7864 { "vpbroadcastw", { XM, EXxmm_mw }, PREFIX_DATA },
7865 },
7866 {
7867 /* VEX_W_0F38CF */
7868 { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7869 },
7870 {
7871 /* VEX_W_0F3A00_L_1 */
7872 { Bad_Opcode },
7873 { "vpermq", { XM, EXx, Ib }, PREFIX_DATA },
7874 },
7875 {
7876 /* VEX_W_0F3A01_L_1 */
7877 { Bad_Opcode },
7878 { "vpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7879 },
7880 {
7881 /* VEX_W_0F3A02 */
7882 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7883 },
7884 {
7885 /* VEX_W_0F3A04 */
7886 { "vpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7887 },
7888 {
7889 /* VEX_W_0F3A05 */
7890 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
7891 },
7892 {
7893 /* VEX_W_0F3A06_L_1 */
7894 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7895 },
7896 {
7897 /* VEX_W_0F3A18_L_1 */
7898 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7899 },
7900 {
7901 /* VEX_W_0F3A19_L_1 */
7902 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
7903 },
7904 {
7905 /* VEX_W_0F3A1D */
7906 { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7907 },
7908 {
7909 /* VEX_W_0F3A38_L_1 */
7910 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7911 },
7912 {
7913 /* VEX_W_0F3A39_L_1 */
7914 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
7915 },
7916 {
7917 /* VEX_W_0F3A46_L_1 */
7918 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7919 },
7920 {
7921 /* VEX_W_0F3A4A */
7922 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7923 },
7924 {
7925 /* VEX_W_0F3A4B */
7926 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7927 },
7928 {
7929 /* VEX_W_0F3A4C */
7930 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7931 },
7932 {
7933 /* VEX_W_0F3ACE */
7934 { Bad_Opcode },
7935 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7936 },
7937 {
7938 /* VEX_W_0F3ACF */
7939 { Bad_Opcode },
7940 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7941 },
7942 /* VEX_W_0FXOP_08_85_L_0 */
7943 {
7944 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
7945 },
7946 /* VEX_W_0FXOP_08_86_L_0 */
7947 {
7948 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7949 },
7950 /* VEX_W_0FXOP_08_87_L_0 */
7951 {
7952 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7953 },
7954 /* VEX_W_0FXOP_08_8E_L_0 */
7955 {
7956 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7957 },
7958 /* VEX_W_0FXOP_08_8F_L_0 */
7959 {
7960 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7961 },
7962 /* VEX_W_0FXOP_08_95_L_0 */
7963 {
7964 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
7965 },
7966 /* VEX_W_0FXOP_08_96_L_0 */
7967 {
7968 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7969 },
7970 /* VEX_W_0FXOP_08_97_L_0 */
7971 {
7972 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7973 },
7974 /* VEX_W_0FXOP_08_9E_L_0 */
7975 {
7976 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7977 },
7978 /* VEX_W_0FXOP_08_9F_L_0 */
7979 {
7980 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7981 },
7982 /* VEX_W_0FXOP_08_A6_L_0 */
7983 {
7984 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7985 },
7986 /* VEX_W_0FXOP_08_B6_L_0 */
7987 {
7988 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7989 },
7990 /* VEX_W_0FXOP_08_C0_L_0 */
7991 {
7992 { "vprotb", { XM, EXx, Ib }, 0 },
7993 },
7994 /* VEX_W_0FXOP_08_C1_L_0 */
7995 {
7996 { "vprotw", { XM, EXx, Ib }, 0 },
7997 },
7998 /* VEX_W_0FXOP_08_C2_L_0 */
7999 {
8000 { "vprotd", { XM, EXx, Ib }, 0 },
8001 },
8002 /* VEX_W_0FXOP_08_C3_L_0 */
8003 {
8004 { "vprotq", { XM, EXx, Ib }, 0 },
8005 },
8006 /* VEX_W_0FXOP_08_CC_L_0 */
8007 {
8008 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
8009 },
8010 /* VEX_W_0FXOP_08_CD_L_0 */
8011 {
8012 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
8013 },
8014 /* VEX_W_0FXOP_08_CE_L_0 */
8015 {
8016 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
8017 },
8018 /* VEX_W_0FXOP_08_CF_L_0 */
8019 {
8020 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
8021 },
8022 /* VEX_W_0FXOP_08_EC_L_0 */
8023 {
8024 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
8025 },
8026 /* VEX_W_0FXOP_08_ED_L_0 */
8027 {
8028 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
8029 },
8030 /* VEX_W_0FXOP_08_EE_L_0 */
8031 {
8032 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
8033 },
8034 /* VEX_W_0FXOP_08_EF_L_0 */
8035 {
8036 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
8037 },
8038 /* VEX_W_0FXOP_09_80 */
8039 {
8040 { "vfrczps", { XM, EXx }, 0 },
8041 },
8042 /* VEX_W_0FXOP_09_81 */
8043 {
8044 { "vfrczpd", { XM, EXx }, 0 },
8045 },
8046 /* VEX_W_0FXOP_09_82 */
8047 {
8048 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
8049 },
8050 /* VEX_W_0FXOP_09_83 */
8051 {
8052 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
8053 },
8054 /* VEX_W_0FXOP_09_C1_L_0 */
8055 {
8056 { "vphaddbw", { XM, EXxmm }, 0 },
8057 },
8058 /* VEX_W_0FXOP_09_C2_L_0 */
8059 {
8060 { "vphaddbd", { XM, EXxmm }, 0 },
8061 },
8062 /* VEX_W_0FXOP_09_C3_L_0 */
8063 {
8064 { "vphaddbq", { XM, EXxmm }, 0 },
8065 },
8066 /* VEX_W_0FXOP_09_C6_L_0 */
8067 {
8068 { "vphaddwd", { XM, EXxmm }, 0 },
8069 },
8070 /* VEX_W_0FXOP_09_C7_L_0 */
8071 {
8072 { "vphaddwq", { XM, EXxmm }, 0 },
8073 },
8074 /* VEX_W_0FXOP_09_CB_L_0 */
8075 {
8076 { "vphadddq", { XM, EXxmm }, 0 },
8077 },
8078 /* VEX_W_0FXOP_09_D1_L_0 */
8079 {
8080 { "vphaddubw", { XM, EXxmm }, 0 },
8081 },
8082 /* VEX_W_0FXOP_09_D2_L_0 */
8083 {
8084 { "vphaddubd", { XM, EXxmm }, 0 },
8085 },
8086 /* VEX_W_0FXOP_09_D3_L_0 */
8087 {
8088 { "vphaddubq", { XM, EXxmm }, 0 },
8089 },
8090 /* VEX_W_0FXOP_09_D6_L_0 */
8091 {
8092 { "vphadduwd", { XM, EXxmm }, 0 },
8093 },
8094 /* VEX_W_0FXOP_09_D7_L_0 */
8095 {
8096 { "vphadduwq", { XM, EXxmm }, 0 },
8097 },
8098 /* VEX_W_0FXOP_09_DB_L_0 */
8099 {
8100 { "vphaddudq", { XM, EXxmm }, 0 },
8101 },
8102 /* VEX_W_0FXOP_09_E1_L_0 */
8103 {
8104 { "vphsubbw", { XM, EXxmm }, 0 },
8105 },
8106 /* VEX_W_0FXOP_09_E2_L_0 */
8107 {
8108 { "vphsubwd", { XM, EXxmm }, 0 },
8109 },
8110 /* VEX_W_0FXOP_09_E3_L_0 */
8111 {
8112 { "vphsubdq", { XM, EXxmm }, 0 },
8113 },
8114
8115 #include "i386-dis-evex-w.h"
8116 };
8117
8118 static const struct dis386 mod_table[][2] = {
8119 {
8120 /* MOD_8D */
8121 { "leaS", { Gv, M }, 0 },
8122 },
8123 {
8124 /* MOD_C6_REG_7 */
8125 { Bad_Opcode },
8126 { RM_TABLE (RM_C6_REG_7) },
8127 },
8128 {
8129 /* MOD_C7_REG_7 */
8130 { Bad_Opcode },
8131 { RM_TABLE (RM_C7_REG_7) },
8132 },
8133 {
8134 /* MOD_FF_REG_3 */
8135 { "{l|}call^", { indirEp }, 0 },
8136 },
8137 {
8138 /* MOD_FF_REG_5 */
8139 { "{l|}jmp^", { indirEp }, 0 },
8140 },
8141 {
8142 /* MOD_0F01_REG_0 */
8143 { X86_64_TABLE (X86_64_0F01_REG_0) },
8144 { RM_TABLE (RM_0F01_REG_0) },
8145 },
8146 {
8147 /* MOD_0F01_REG_1 */
8148 { X86_64_TABLE (X86_64_0F01_REG_1) },
8149 { RM_TABLE (RM_0F01_REG_1) },
8150 },
8151 {
8152 /* MOD_0F01_REG_2 */
8153 { X86_64_TABLE (X86_64_0F01_REG_2) },
8154 { RM_TABLE (RM_0F01_REG_2) },
8155 },
8156 {
8157 /* MOD_0F01_REG_3 */
8158 { X86_64_TABLE (X86_64_0F01_REG_3) },
8159 { RM_TABLE (RM_0F01_REG_3) },
8160 },
8161 {
8162 /* MOD_0F01_REG_5 */
8163 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8164 { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8165 },
8166 {
8167 /* MOD_0F01_REG_7 */
8168 { "invlpg", { Mb }, 0 },
8169 { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8170 },
8171 {
8172 /* MOD_0F12_PREFIX_0 */
8173 { "movlpX", { XM, EXq }, 0 },
8174 { "movhlps", { XM, EXq }, 0 },
8175 },
8176 {
8177 /* MOD_0F12_PREFIX_2 */
8178 { "movlpX", { XM, EXq }, 0 },
8179 },
8180 {
8181 /* MOD_0F13 */
8182 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
8183 },
8184 {
8185 /* MOD_0F16_PREFIX_0 */
8186 { "movhpX", { XM, EXq }, 0 },
8187 { "movlhps", { XM, EXq }, 0 },
8188 },
8189 {
8190 /* MOD_0F16_PREFIX_2 */
8191 { "movhpX", { XM, EXq }, 0 },
8192 },
8193 {
8194 /* MOD_0F17 */
8195 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
8196 },
8197 {
8198 /* MOD_0F18_REG_0 */
8199 { "prefetchnta", { Mb }, 0 },
8200 { "nopQ", { Ev }, 0 },
8201 },
8202 {
8203 /* MOD_0F18_REG_1 */
8204 { "prefetcht0", { Mb }, 0 },
8205 { "nopQ", { Ev }, 0 },
8206 },
8207 {
8208 /* MOD_0F18_REG_2 */
8209 { "prefetcht1", { Mb }, 0 },
8210 { "nopQ", { Ev }, 0 },
8211 },
8212 {
8213 /* MOD_0F18_REG_3 */
8214 { "prefetcht2", { Mb }, 0 },
8215 { "nopQ", { Ev }, 0 },
8216 },
8217 {
8218 /* MOD_0F1A_PREFIX_0 */
8219 { "bndldx", { Gbnd, Mv_bnd }, 0 },
8220 { "nopQ", { Ev }, 0 },
8221 },
8222 {
8223 /* MOD_0F1B_PREFIX_0 */
8224 { "bndstx", { Mv_bnd, Gbnd }, 0 },
8225 { "nopQ", { Ev }, 0 },
8226 },
8227 {
8228 /* MOD_0F1B_PREFIX_1 */
8229 { "bndmk", { Gbnd, Mv_bnd }, 0 },
8230 { "nopQ", { Ev }, PREFIX_IGNORED },
8231 },
8232 {
8233 /* MOD_0F1C_PREFIX_0 */
8234 { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8235 { "nopQ", { Ev }, 0 },
8236 },
8237 {
8238 /* MOD_0F1E_PREFIX_1 */
8239 { "nopQ", { Ev }, PREFIX_IGNORED },
8240 { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8241 },
8242 {
8243 /* MOD_0F2B_PREFIX_0 */
8244 {"movntps", { Mx, XM }, PREFIX_OPCODE },
8245 },
8246 {
8247 /* MOD_0F2B_PREFIX_1 */
8248 {"movntss", { Md, XM }, PREFIX_OPCODE },
8249 },
8250 {
8251 /* MOD_0F2B_PREFIX_2 */
8252 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
8253 },
8254 {
8255 /* MOD_0F2B_PREFIX_3 */
8256 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
8257 },
8258 {
8259 /* MOD_0F50 */
8260 { Bad_Opcode },
8261 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
8262 },
8263 {
8264 /* MOD_0F71_REG_2 */
8265 { Bad_Opcode },
8266 { "psrlw", { MS, Ib }, PREFIX_OPCODE },
8267 },
8268 {
8269 /* MOD_0F71_REG_4 */
8270 { Bad_Opcode },
8271 { "psraw", { MS, Ib }, PREFIX_OPCODE },
8272 },
8273 {
8274 /* MOD_0F71_REG_6 */
8275 { Bad_Opcode },
8276 { "psllw", { MS, Ib }, PREFIX_OPCODE },
8277 },
8278 {
8279 /* MOD_0F72_REG_2 */
8280 { Bad_Opcode },
8281 { "psrld", { MS, Ib }, PREFIX_OPCODE },
8282 },
8283 {
8284 /* MOD_0F72_REG_4 */
8285 { Bad_Opcode },
8286 { "psrad", { MS, Ib }, PREFIX_OPCODE },
8287 },
8288 {
8289 /* MOD_0F72_REG_6 */
8290 { Bad_Opcode },
8291 { "pslld", { MS, Ib }, PREFIX_OPCODE },
8292 },
8293 {
8294 /* MOD_0F73_REG_2 */
8295 { Bad_Opcode },
8296 { "psrlq", { MS, Ib }, PREFIX_OPCODE },
8297 },
8298 {
8299 /* MOD_0F73_REG_3 */
8300 { Bad_Opcode },
8301 { "psrldq", { XS, Ib }, PREFIX_DATA },
8302 },
8303 {
8304 /* MOD_0F73_REG_6 */
8305 { Bad_Opcode },
8306 { "psllq", { MS, Ib }, PREFIX_OPCODE },
8307 },
8308 {
8309 /* MOD_0F73_REG_7 */
8310 { Bad_Opcode },
8311 { "pslldq", { XS, Ib }, PREFIX_DATA },
8312 },
8313 {
8314 /* MOD_0FAE_REG_0 */
8315 { "fxsave", { FXSAVE }, 0 },
8316 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8317 },
8318 {
8319 /* MOD_0FAE_REG_1 */
8320 { "fxrstor", { FXSAVE }, 0 },
8321 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8322 },
8323 {
8324 /* MOD_0FAE_REG_2 */
8325 { "ldmxcsr", { Md }, 0 },
8326 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8327 },
8328 {
8329 /* MOD_0FAE_REG_3 */
8330 { "stmxcsr", { Md }, 0 },
8331 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8332 },
8333 {
8334 /* MOD_0FAE_REG_4 */
8335 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8336 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8337 },
8338 {
8339 /* MOD_0FAE_REG_5 */
8340 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
8341 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8342 },
8343 {
8344 /* MOD_0FAE_REG_6 */
8345 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8346 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8347 },
8348 {
8349 /* MOD_0FAE_REG_7 */
8350 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8351 { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8352 },
8353 {
8354 /* MOD_0FB2 */
8355 { "lssS", { Gv, Mp }, 0 },
8356 },
8357 {
8358 /* MOD_0FB4 */
8359 { "lfsS", { Gv, Mp }, 0 },
8360 },
8361 {
8362 /* MOD_0FB5 */
8363 { "lgsS", { Gv, Mp }, 0 },
8364 },
8365 {
8366 /* MOD_0FC3 */
8367 { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8368 },
8369 {
8370 /* MOD_0FC7_REG_3 */
8371 { "xrstors", { FXSAVE }, 0 },
8372 },
8373 {
8374 /* MOD_0FC7_REG_4 */
8375 { "xsavec", { FXSAVE }, 0 },
8376 },
8377 {
8378 /* MOD_0FC7_REG_5 */
8379 { "xsaves", { FXSAVE }, 0 },
8380 },
8381 {
8382 /* MOD_0FC7_REG_6 */
8383 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8384 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8385 },
8386 {
8387 /* MOD_0FC7_REG_7 */
8388 { "vmptrst", { Mq }, 0 },
8389 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8390 },
8391 {
8392 /* MOD_0FD7 */
8393 { Bad_Opcode },
8394 { "pmovmskb", { Gdq, MS }, 0 },
8395 },
8396 {
8397 /* MOD_0FE7_PREFIX_2 */
8398 { "movntdq", { Mx, XM }, 0 },
8399 },
8400 {
8401 /* MOD_0FF0_PREFIX_3 */
8402 { "lddqu", { XM, M }, 0 },
8403 },
8404 {
8405 /* MOD_0F382A */
8406 { "movntdqa", { XM, Mx }, PREFIX_DATA },
8407 },
8408 {
8409 /* MOD_0F38DC_PREFIX_1 */
8410 { "aesenc128kl", { XM, M }, 0 },
8411 { "loadiwkey", { XM, EXx }, 0 },
8412 },
8413 {
8414 /* MOD_0F38DD_PREFIX_1 */
8415 { "aesdec128kl", { XM, M }, 0 },
8416 },
8417 {
8418 /* MOD_0F38DE_PREFIX_1 */
8419 { "aesenc256kl", { XM, M }, 0 },
8420 },
8421 {
8422 /* MOD_0F38DF_PREFIX_1 */
8423 { "aesdec256kl", { XM, M }, 0 },
8424 },
8425 {
8426 /* MOD_0F38F5 */
8427 { "wrussK", { M, Gdq }, PREFIX_DATA },
8428 },
8429 {
8430 /* MOD_0F38F6_PREFIX_0 */
8431 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
8432 },
8433 {
8434 /* MOD_0F38F8_PREFIX_1 */
8435 { "enqcmds", { Gva, M }, PREFIX_OPCODE },
8436 },
8437 {
8438 /* MOD_0F38F8_PREFIX_2 */
8439 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
8440 },
8441 {
8442 /* MOD_0F38F8_PREFIX_3 */
8443 { "enqcmd", { Gva, M }, PREFIX_OPCODE },
8444 },
8445 {
8446 /* MOD_0F38F9 */
8447 { "movdiri", { Edq, Gdq }, PREFIX_OPCODE },
8448 },
8449 {
8450 /* MOD_0F38FA_PREFIX_1 */
8451 { Bad_Opcode },
8452 { "encodekey128", { Gd, Ed }, 0 },
8453 },
8454 {
8455 /* MOD_0F38FB_PREFIX_1 */
8456 { Bad_Opcode },
8457 { "encodekey256", { Gd, Ed }, 0 },
8458 },
8459 {
8460 /* MOD_0F3A0F_PREFIX_1 */
8461 { Bad_Opcode },
8462 { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8463 },
8464 {
8465 /* MOD_62_32BIT */
8466 { "bound{S|}", { Gv, Ma }, 0 },
8467 { EVEX_TABLE (EVEX_0F) },
8468 },
8469 {
8470 /* MOD_C4_32BIT */
8471 { "lesS", { Gv, Mp }, 0 },
8472 { VEX_C4_TABLE (VEX_0F) },
8473 },
8474 {
8475 /* MOD_C5_32BIT */
8476 { "ldsS", { Gv, Mp }, 0 },
8477 { VEX_C5_TABLE (VEX_0F) },
8478 },
8479 {
8480 /* MOD_VEX_0F12_PREFIX_0 */
8481 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8482 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8483 },
8484 {
8485 /* MOD_VEX_0F12_PREFIX_2 */
8486 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8487 },
8488 {
8489 /* MOD_VEX_0F13 */
8490 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8491 },
8492 {
8493 /* MOD_VEX_0F16_PREFIX_0 */
8494 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8495 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8496 },
8497 {
8498 /* MOD_VEX_0F16_PREFIX_2 */
8499 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8500 },
8501 {
8502 /* MOD_VEX_0F17 */
8503 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8504 },
8505 {
8506 /* MOD_VEX_0F2B */
8507 { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
8508 },
8509 {
8510 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
8511 { Bad_Opcode },
8512 { "kandw", { MaskG, MaskVex, MaskE }, 0 },
8513 },
8514 {
8515 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
8516 { Bad_Opcode },
8517 { "kandq", { MaskG, MaskVex, MaskE }, 0 },
8518 },
8519 {
8520 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
8521 { Bad_Opcode },
8522 { "kandb", { MaskG, MaskVex, MaskE }, 0 },
8523 },
8524 {
8525 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
8526 { Bad_Opcode },
8527 { "kandd", { MaskG, MaskVex, MaskE }, 0 },
8528 },
8529 {
8530 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
8531 { Bad_Opcode },
8532 { "kandnw", { MaskG, MaskVex, MaskE }, 0 },
8533 },
8534 {
8535 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
8536 { Bad_Opcode },
8537 { "kandnq", { MaskG, MaskVex, MaskE }, 0 },
8538 },
8539 {
8540 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
8541 { Bad_Opcode },
8542 { "kandnb", { MaskG, MaskVex, MaskE }, 0 },
8543 },
8544 {
8545 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
8546 { Bad_Opcode },
8547 { "kandnd", { MaskG, MaskVex, MaskE }, 0 },
8548 },
8549 {
8550 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
8551 { Bad_Opcode },
8552 { "knotw", { MaskG, MaskE }, 0 },
8553 },
8554 {
8555 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
8556 { Bad_Opcode },
8557 { "knotq", { MaskG, MaskE }, 0 },
8558 },
8559 {
8560 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
8561 { Bad_Opcode },
8562 { "knotb", { MaskG, MaskE }, 0 },
8563 },
8564 {
8565 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
8566 { Bad_Opcode },
8567 { "knotd", { MaskG, MaskE }, 0 },
8568 },
8569 {
8570 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
8571 { Bad_Opcode },
8572 { "korw", { MaskG, MaskVex, MaskE }, 0 },
8573 },
8574 {
8575 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
8576 { Bad_Opcode },
8577 { "korq", { MaskG, MaskVex, MaskE }, 0 },
8578 },
8579 {
8580 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
8581 { Bad_Opcode },
8582 { "korb", { MaskG, MaskVex, MaskE }, 0 },
8583 },
8584 {
8585 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
8586 { Bad_Opcode },
8587 { "kord", { MaskG, MaskVex, MaskE }, 0 },
8588 },
8589 {
8590 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
8591 { Bad_Opcode },
8592 { "kxnorw", { MaskG, MaskVex, MaskE }, 0 },
8593 },
8594 {
8595 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
8596 { Bad_Opcode },
8597 { "kxnorq", { MaskG, MaskVex, MaskE }, 0 },
8598 },
8599 {
8600 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
8601 { Bad_Opcode },
8602 { "kxnorb", { MaskG, MaskVex, MaskE }, 0 },
8603 },
8604 {
8605 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
8606 { Bad_Opcode },
8607 { "kxnord", { MaskG, MaskVex, MaskE }, 0 },
8608 },
8609 {
8610 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
8611 { Bad_Opcode },
8612 { "kxorw", { MaskG, MaskVex, MaskE }, 0 },
8613 },
8614 {
8615 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
8616 { Bad_Opcode },
8617 { "kxorq", { MaskG, MaskVex, MaskE }, 0 },
8618 },
8619 {
8620 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
8621 { Bad_Opcode },
8622 { "kxorb", { MaskG, MaskVex, MaskE }, 0 },
8623 },
8624 {
8625 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
8626 { Bad_Opcode },
8627 { "kxord", { MaskG, MaskVex, MaskE }, 0 },
8628 },
8629 {
8630 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
8631 { Bad_Opcode },
8632 { "kaddw", { MaskG, MaskVex, MaskE }, 0 },
8633 },
8634 {
8635 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
8636 { Bad_Opcode },
8637 { "kaddq", { MaskG, MaskVex, MaskE }, 0 },
8638 },
8639 {
8640 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
8641 { Bad_Opcode },
8642 { "kaddb", { MaskG, MaskVex, MaskE }, 0 },
8643 },
8644 {
8645 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
8646 { Bad_Opcode },
8647 { "kaddd", { MaskG, MaskVex, MaskE }, 0 },
8648 },
8649 {
8650 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
8651 { Bad_Opcode },
8652 { "kunpckwd", { MaskG, MaskVex, MaskE }, 0 },
8653 },
8654 {
8655 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
8656 { Bad_Opcode },
8657 { "kunpckdq", { MaskG, MaskVex, MaskE }, 0 },
8658 },
8659 {
8660 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
8661 { Bad_Opcode },
8662 { "kunpckbw", { MaskG, MaskVex, MaskE }, 0 },
8663 },
8664 {
8665 /* MOD_VEX_0F50 */
8666 { Bad_Opcode },
8667 { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
8668 },
8669 {
8670 /* MOD_VEX_0F71_REG_2 */
8671 { Bad_Opcode },
8672 { "vpsrlw", { Vex, XS, Ib }, PREFIX_DATA },
8673 },
8674 {
8675 /* MOD_VEX_0F71_REG_4 */
8676 { Bad_Opcode },
8677 { "vpsraw", { Vex, XS, Ib }, PREFIX_DATA },
8678 },
8679 {
8680 /* MOD_VEX_0F71_REG_6 */
8681 { Bad_Opcode },
8682 { "vpsllw", { Vex, XS, Ib }, PREFIX_DATA },
8683 },
8684 {
8685 /* MOD_VEX_0F72_REG_2 */
8686 { Bad_Opcode },
8687 { "vpsrld", { Vex, XS, Ib }, PREFIX_DATA },
8688 },
8689 {
8690 /* MOD_VEX_0F72_REG_4 */
8691 { Bad_Opcode },
8692 { "vpsrad", { Vex, XS, Ib }, PREFIX_DATA },
8693 },
8694 {
8695 /* MOD_VEX_0F72_REG_6 */
8696 { Bad_Opcode },
8697 { "vpslld", { Vex, XS, Ib }, PREFIX_DATA },
8698 },
8699 {
8700 /* MOD_VEX_0F73_REG_2 */
8701 { Bad_Opcode },
8702 { "vpsrlq", { Vex, XS, Ib }, PREFIX_DATA },
8703 },
8704 {
8705 /* MOD_VEX_0F73_REG_3 */
8706 { Bad_Opcode },
8707 { "vpsrldq", { Vex, XS, Ib }, PREFIX_DATA },
8708 },
8709 {
8710 /* MOD_VEX_0F73_REG_6 */
8711 { Bad_Opcode },
8712 { "vpsllq", { Vex, XS, Ib }, PREFIX_DATA },
8713 },
8714 {
8715 /* MOD_VEX_0F73_REG_7 */
8716 { Bad_Opcode },
8717 { "vpslldq", { Vex, XS, Ib }, PREFIX_DATA },
8718 },
8719 {
8720 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8721 { "kmovw", { Ew, MaskG }, 0 },
8722 { Bad_Opcode },
8723 },
8724 {
8725 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8726 { "kmovq", { Eq, MaskG }, 0 },
8727 { Bad_Opcode },
8728 },
8729 {
8730 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8731 { "kmovb", { Eb, MaskG }, 0 },
8732 { Bad_Opcode },
8733 },
8734 {
8735 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8736 { "kmovd", { Ed, MaskG }, 0 },
8737 { Bad_Opcode },
8738 },
8739 {
8740 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
8741 { Bad_Opcode },
8742 { "kmovw", { MaskG, Edq }, 0 },
8743 },
8744 {
8745 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
8746 { Bad_Opcode },
8747 { "kmovb", { MaskG, Edq }, 0 },
8748 },
8749 {
8750 /* MOD_VEX_0F92_P_3_LEN_0 */
8751 { Bad_Opcode },
8752 { "kmovK", { MaskG, Edq }, 0 },
8753 },
8754 {
8755 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
8756 { Bad_Opcode },
8757 { "kmovw", { Gdq, MaskE }, 0 },
8758 },
8759 {
8760 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
8761 { Bad_Opcode },
8762 { "kmovb", { Gdq, MaskE }, 0 },
8763 },
8764 {
8765 /* MOD_VEX_0F93_P_3_LEN_0 */
8766 { Bad_Opcode },
8767 { "kmovK", { Gdq, MaskE }, 0 },
8768 },
8769 {
8770 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
8771 { Bad_Opcode },
8772 { "kortestw", { MaskG, MaskE }, 0 },
8773 },
8774 {
8775 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
8776 { Bad_Opcode },
8777 { "kortestq", { MaskG, MaskE }, 0 },
8778 },
8779 {
8780 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
8781 { Bad_Opcode },
8782 { "kortestb", { MaskG, MaskE }, 0 },
8783 },
8784 {
8785 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
8786 { Bad_Opcode },
8787 { "kortestd", { MaskG, MaskE }, 0 },
8788 },
8789 {
8790 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
8791 { Bad_Opcode },
8792 { "ktestw", { MaskG, MaskE }, 0 },
8793 },
8794 {
8795 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
8796 { Bad_Opcode },
8797 { "ktestq", { MaskG, MaskE }, 0 },
8798 },
8799 {
8800 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
8801 { Bad_Opcode },
8802 { "ktestb", { MaskG, MaskE }, 0 },
8803 },
8804 {
8805 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
8806 { Bad_Opcode },
8807 { "ktestd", { MaskG, MaskE }, 0 },
8808 },
8809 {
8810 /* MOD_VEX_0FAE_REG_2 */
8811 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8812 },
8813 {
8814 /* MOD_VEX_0FAE_REG_3 */
8815 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8816 },
8817 {
8818 /* MOD_VEX_0FD7 */
8819 { Bad_Opcode },
8820 { "vpmovmskb", { Gdq, XS }, PREFIX_DATA },
8821 },
8822 {
8823 /* MOD_VEX_0FE7 */
8824 { "vmovntdq", { Mx, XM }, PREFIX_DATA },
8825 },
8826 {
8827 /* MOD_VEX_0FF0_PREFIX_3 */
8828 { "vlddqu", { XM, M }, 0 },
8829 },
8830 {
8831 /* MOD_VEX_0F381A */
8832 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8833 },
8834 {
8835 /* MOD_VEX_0F382A */
8836 { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
8837 },
8838 {
8839 /* MOD_VEX_0F382C */
8840 { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8841 },
8842 {
8843 /* MOD_VEX_0F382D */
8844 { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8845 },
8846 {
8847 /* MOD_VEX_0F382E */
8848 { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8849 },
8850 {
8851 /* MOD_VEX_0F382F */
8852 { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8853 },
8854 {
8855 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8856 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8857 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8858 },
8859 {
8860 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8861 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8862 },
8863 {
8864 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8865 { Bad_Opcode },
8866 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8867 },
8868 {
8869 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8870 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8871 },
8872 {
8873 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8874 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8875 },
8876 {
8877 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8878 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8879 },
8880 {
8881 /* MOD_VEX_0F385A */
8882 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8883 },
8884 {
8885 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8886 { Bad_Opcode },
8887 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8888 },
8889 {
8890 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8891 { Bad_Opcode },
8892 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8893 },
8894 {
8895 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8896 { Bad_Opcode },
8897 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8898 },
8899 {
8900 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8901 { Bad_Opcode },
8902 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8903 },
8904 {
8905 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8906 { Bad_Opcode },
8907 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8908 },
8909 {
8910 /* MOD_VEX_0F388C */
8911 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
8912 },
8913 {
8914 /* MOD_VEX_0F388E */
8915 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
8916 },
8917 {
8918 /* MOD_VEX_0F3A30_L_0 */
8919 { Bad_Opcode },
8920 { "kshiftr%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8921 },
8922 {
8923 /* MOD_VEX_0F3A31_L_0 */
8924 { Bad_Opcode },
8925 { "kshiftr%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8926 },
8927 {
8928 /* MOD_VEX_0F3A32_L_0 */
8929 { Bad_Opcode },
8930 { "kshiftl%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8931 },
8932 {
8933 /* MOD_VEX_0F3A33_L_0 */
8934 { Bad_Opcode },
8935 { "kshiftl%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8936 },
8937 {
8938 /* MOD_VEX_0FXOP_09_12 */
8939 { Bad_Opcode },
8940 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8941 },
8942
8943 #include "i386-dis-evex-mod.h"
8944 };
8945
8946 static const struct dis386 rm_table[][8] = {
8947 {
8948 /* RM_C6_REG_7 */
8949 { "xabort", { Skip_MODRM, Ib }, 0 },
8950 },
8951 {
8952 /* RM_C7_REG_7 */
8953 { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
8954 },
8955 {
8956 /* RM_0F01_REG_0 */
8957 { "enclv", { Skip_MODRM }, 0 },
8958 { "vmcall", { Skip_MODRM }, 0 },
8959 { "vmlaunch", { Skip_MODRM }, 0 },
8960 { "vmresume", { Skip_MODRM }, 0 },
8961 { "vmxoff", { Skip_MODRM }, 0 },
8962 { "pconfig", { Skip_MODRM }, 0 },
8963 },
8964 {
8965 /* RM_0F01_REG_1 */
8966 { "monitor", { { OP_Monitor, 0 } }, 0 },
8967 { "mwait", { { OP_Mwait, 0 } }, 0 },
8968 { "clac", { Skip_MODRM }, 0 },
8969 { "stac", { Skip_MODRM }, 0 },
8970 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8971 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8972 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8973 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8974 },
8975 {
8976 /* RM_0F01_REG_2 */
8977 { "xgetbv", { Skip_MODRM }, 0 },
8978 { "xsetbv", { Skip_MODRM }, 0 },
8979 { Bad_Opcode },
8980 { Bad_Opcode },
8981 { "vmfunc", { Skip_MODRM }, 0 },
8982 { "xend", { Skip_MODRM }, 0 },
8983 { "xtest", { Skip_MODRM }, 0 },
8984 { "enclu", { Skip_MODRM }, 0 },
8985 },
8986 {
8987 /* RM_0F01_REG_3 */
8988 { "vmrun", { Skip_MODRM }, 0 },
8989 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8990 { "vmload", { Skip_MODRM }, 0 },
8991 { "vmsave", { Skip_MODRM }, 0 },
8992 { "stgi", { Skip_MODRM }, 0 },
8993 { "clgi", { Skip_MODRM }, 0 },
8994 { "skinit", { Skip_MODRM }, 0 },
8995 { "invlpga", { Skip_MODRM }, 0 },
8996 },
8997 {
8998 /* RM_0F01_REG_5_MOD_3 */
8999 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
9000 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
9001 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
9002 { Bad_Opcode },
9003 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
9004 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
9005 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
9006 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
9007 },
9008 {
9009 /* RM_0F01_REG_7_MOD_3 */
9010 { "swapgs", { Skip_MODRM }, 0 },
9011 { "rdtscp", { Skip_MODRM }, 0 },
9012 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
9013 { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
9014 { "clzero", { Skip_MODRM }, 0 },
9015 { "rdpru", { Skip_MODRM }, 0 },
9016 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
9017 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
9018 },
9019 {
9020 /* RM_0F1E_P_1_MOD_3_REG_7 */
9021 { "nopQ", { Ev }, PREFIX_IGNORED },
9022 { "nopQ", { Ev }, PREFIX_IGNORED },
9023 { "endbr64", { Skip_MODRM }, 0 },
9024 { "endbr32", { Skip_MODRM }, 0 },
9025 { "nopQ", { Ev }, PREFIX_IGNORED },
9026 { "nopQ", { Ev }, PREFIX_IGNORED },
9027 { "nopQ", { Ev }, PREFIX_IGNORED },
9028 { "nopQ", { Ev }, PREFIX_IGNORED },
9029 },
9030 {
9031 /* RM_0F3A0F_P_1_MOD_3_REG_0 */
9032 { "hreset", { Skip_MODRM, Ib }, 0 },
9033 },
9034 {
9035 /* RM_0FAE_REG_6_MOD_3 */
9036 { "mfence", { Skip_MODRM }, 0 },
9037 },
9038 {
9039 /* RM_0FAE_REG_7_MOD_3 */
9040 { "sfence", { Skip_MODRM }, 0 },
9041
9042 },
9043 {
9044 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
9045 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
9046 },
9047 };
9048
9049 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9050
9051 /* We use the high bit to indicate different name for the same
9052 prefix. */
9053 #define REP_PREFIX (0xf3 | 0x100)
9054 #define XACQUIRE_PREFIX (0xf2 | 0x200)
9055 #define XRELEASE_PREFIX (0xf3 | 0x400)
9056 #define BND_PREFIX (0xf2 | 0x400)
9057 #define NOTRACK_PREFIX (0x3e | 0x100)
9058
9059 /* Remember if the current op is a jump instruction. */
9060 static bfd_boolean op_is_jump = FALSE;
9061
9062 static int
9063 ckprefix (void)
9064 {
9065 int newrex, i, length;
9066 rex = 0;
9067 prefixes = 0;
9068 used_prefixes = 0;
9069 rex_used = 0;
9070 last_lock_prefix = -1;
9071 last_repz_prefix = -1;
9072 last_repnz_prefix = -1;
9073 last_data_prefix = -1;
9074 last_addr_prefix = -1;
9075 last_rex_prefix = -1;
9076 last_seg_prefix = -1;
9077 fwait_prefix = -1;
9078 active_seg_prefix = 0;
9079 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9080 all_prefixes[i] = 0;
9081 i = 0;
9082 length = 0;
9083 /* The maximum instruction length is 15bytes. */
9084 while (length < MAX_CODE_LENGTH - 1)
9085 {
9086 FETCH_DATA (the_info, codep + 1);
9087 newrex = 0;
9088 switch (*codep)
9089 {
9090 /* REX prefixes family. */
9091 case 0x40:
9092 case 0x41:
9093 case 0x42:
9094 case 0x43:
9095 case 0x44:
9096 case 0x45:
9097 case 0x46:
9098 case 0x47:
9099 case 0x48:
9100 case 0x49:
9101 case 0x4a:
9102 case 0x4b:
9103 case 0x4c:
9104 case 0x4d:
9105 case 0x4e:
9106 case 0x4f:
9107 if (address_mode == mode_64bit)
9108 newrex = *codep;
9109 else
9110 return 1;
9111 last_rex_prefix = i;
9112 break;
9113 case 0xf3:
9114 prefixes |= PREFIX_REPZ;
9115 last_repz_prefix = i;
9116 break;
9117 case 0xf2:
9118 prefixes |= PREFIX_REPNZ;
9119 last_repnz_prefix = i;
9120 break;
9121 case 0xf0:
9122 prefixes |= PREFIX_LOCK;
9123 last_lock_prefix = i;
9124 break;
9125 case 0x2e:
9126 prefixes |= PREFIX_CS;
9127 last_seg_prefix = i;
9128
9129 if (address_mode != mode_64bit)
9130 active_seg_prefix = PREFIX_CS;
9131
9132 break;
9133 case 0x36:
9134 prefixes |= PREFIX_SS;
9135 last_seg_prefix = i;
9136
9137 if (address_mode != mode_64bit)
9138 active_seg_prefix = PREFIX_SS;
9139
9140 break;
9141 case 0x3e:
9142 prefixes |= PREFIX_DS;
9143 last_seg_prefix = i;
9144
9145 if (address_mode != mode_64bit)
9146 active_seg_prefix = PREFIX_DS;
9147
9148 break;
9149 case 0x26:
9150 prefixes |= PREFIX_ES;
9151 last_seg_prefix = i;
9152
9153 if (address_mode != mode_64bit)
9154 active_seg_prefix = PREFIX_ES;
9155
9156 break;
9157 case 0x64:
9158 prefixes |= PREFIX_FS;
9159 last_seg_prefix = i;
9160 active_seg_prefix = PREFIX_FS;
9161 break;
9162 case 0x65:
9163 prefixes |= PREFIX_GS;
9164 last_seg_prefix = i;
9165 active_seg_prefix = PREFIX_GS;
9166 break;
9167 case 0x66:
9168 prefixes |= PREFIX_DATA;
9169 last_data_prefix = i;
9170 break;
9171 case 0x67:
9172 prefixes |= PREFIX_ADDR;
9173 last_addr_prefix = i;
9174 break;
9175 case FWAIT_OPCODE:
9176 /* fwait is really an instruction. If there are prefixes
9177 before the fwait, they belong to the fwait, *not* to the
9178 following instruction. */
9179 fwait_prefix = i;
9180 if (prefixes || rex)
9181 {
9182 prefixes |= PREFIX_FWAIT;
9183 codep++;
9184 /* This ensures that the previous REX prefixes are noticed
9185 as unused prefixes, as in the return case below. */
9186 rex_used = rex;
9187 return 1;
9188 }
9189 prefixes = PREFIX_FWAIT;
9190 break;
9191 default:
9192 return 1;
9193 }
9194 /* Rex is ignored when followed by another prefix. */
9195 if (rex)
9196 {
9197 rex_used = rex;
9198 return 1;
9199 }
9200 if (*codep != FWAIT_OPCODE)
9201 all_prefixes[i++] = *codep;
9202 rex = newrex;
9203 codep++;
9204 length++;
9205 }
9206 return 0;
9207 }
9208
9209 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9210 prefix byte. */
9211
9212 static const char *
9213 prefix_name (int pref, int sizeflag)
9214 {
9215 static const char *rexes [16] =
9216 {
9217 "rex", /* 0x40 */
9218 "rex.B", /* 0x41 */
9219 "rex.X", /* 0x42 */
9220 "rex.XB", /* 0x43 */
9221 "rex.R", /* 0x44 */
9222 "rex.RB", /* 0x45 */
9223 "rex.RX", /* 0x46 */
9224 "rex.RXB", /* 0x47 */
9225 "rex.W", /* 0x48 */
9226 "rex.WB", /* 0x49 */
9227 "rex.WX", /* 0x4a */
9228 "rex.WXB", /* 0x4b */
9229 "rex.WR", /* 0x4c */
9230 "rex.WRB", /* 0x4d */
9231 "rex.WRX", /* 0x4e */
9232 "rex.WRXB", /* 0x4f */
9233 };
9234
9235 switch (pref)
9236 {
9237 /* REX prefixes family. */
9238 case 0x40:
9239 case 0x41:
9240 case 0x42:
9241 case 0x43:
9242 case 0x44:
9243 case 0x45:
9244 case 0x46:
9245 case 0x47:
9246 case 0x48:
9247 case 0x49:
9248 case 0x4a:
9249 case 0x4b:
9250 case 0x4c:
9251 case 0x4d:
9252 case 0x4e:
9253 case 0x4f:
9254 return rexes [pref - 0x40];
9255 case 0xf3:
9256 return "repz";
9257 case 0xf2:
9258 return "repnz";
9259 case 0xf0:
9260 return "lock";
9261 case 0x2e:
9262 return "cs";
9263 case 0x36:
9264 return "ss";
9265 case 0x3e:
9266 return "ds";
9267 case 0x26:
9268 return "es";
9269 case 0x64:
9270 return "fs";
9271 case 0x65:
9272 return "gs";
9273 case 0x66:
9274 return (sizeflag & DFLAG) ? "data16" : "data32";
9275 case 0x67:
9276 if (address_mode == mode_64bit)
9277 return (sizeflag & AFLAG) ? "addr32" : "addr64";
9278 else
9279 return (sizeflag & AFLAG) ? "addr16" : "addr32";
9280 case FWAIT_OPCODE:
9281 return "fwait";
9282 case REP_PREFIX:
9283 return "rep";
9284 case XACQUIRE_PREFIX:
9285 return "xacquire";
9286 case XRELEASE_PREFIX:
9287 return "xrelease";
9288 case BND_PREFIX:
9289 return "bnd";
9290 case NOTRACK_PREFIX:
9291 return "notrack";
9292 default:
9293 return NULL;
9294 }
9295 }
9296
9297 static char op_out[MAX_OPERANDS][100];
9298 static int op_ad, op_index[MAX_OPERANDS];
9299 static int two_source_ops;
9300 static bfd_vma op_address[MAX_OPERANDS];
9301 static bfd_vma op_riprel[MAX_OPERANDS];
9302 static bfd_vma start_pc;
9303
9304 /*
9305 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9306 * (see topic "Redundant prefixes" in the "Differences from 8086"
9307 * section of the "Virtual 8086 Mode" chapter.)
9308 * 'pc' should be the address of this instruction, it will
9309 * be used to print the target address if this is a relative jump or call
9310 * The function returns the length of this instruction in bytes.
9311 */
9312
9313 static char intel_syntax;
9314 static char intel_mnemonic = !SYSV386_COMPAT;
9315 static char open_char;
9316 static char close_char;
9317 static char separator_char;
9318 static char scale_char;
9319
9320 enum x86_64_isa
9321 {
9322 amd64 = 1,
9323 intel64
9324 };
9325
9326 static enum x86_64_isa isa64;
9327
9328 /* Here for backwards compatibility. When gdb stops using
9329 print_insn_i386_att and print_insn_i386_intel these functions can
9330 disappear, and print_insn_i386 be merged into print_insn. */
9331 int
9332 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9333 {
9334 intel_syntax = 0;
9335
9336 return print_insn (pc, info);
9337 }
9338
9339 int
9340 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9341 {
9342 intel_syntax = 1;
9343
9344 return print_insn (pc, info);
9345 }
9346
9347 int
9348 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9349 {
9350 intel_syntax = -1;
9351
9352 return print_insn (pc, info);
9353 }
9354
9355 void
9356 print_i386_disassembler_options (FILE *stream)
9357 {
9358 fprintf (stream, _("\n\
9359 The following i386/x86-64 specific disassembler options are supported for use\n\
9360 with the -M switch (multiple options should be separated by commas):\n"));
9361
9362 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
9363 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
9364 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
9365 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
9366 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9367 fprintf (stream, _(" att-mnemonic\n"
9368 " Display instruction in AT&T mnemonic\n"));
9369 fprintf (stream, _(" intel-mnemonic\n"
9370 " Display instruction in Intel mnemonic\n"));
9371 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
9372 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
9373 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
9374 fprintf (stream, _(" data32 Assume 32bit data size\n"));
9375 fprintf (stream, _(" data16 Assume 16bit data size\n"));
9376 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9377 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
9378 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
9379 }
9380
9381 /* Bad opcode. */
9382 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
9383
9384 /* Get a pointer to struct dis386 with a valid name. */
9385
9386 static const struct dis386 *
9387 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9388 {
9389 int vindex, vex_table_index;
9390
9391 if (dp->name != NULL)
9392 return dp;
9393
9394 switch (dp->op[0].bytemode)
9395 {
9396 case USE_REG_TABLE:
9397 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9398 break;
9399
9400 case USE_MOD_TABLE:
9401 vindex = modrm.mod == 0x3 ? 1 : 0;
9402 dp = &mod_table[dp->op[1].bytemode][vindex];
9403 break;
9404
9405 case USE_RM_TABLE:
9406 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9407 break;
9408
9409 case USE_PREFIX_TABLE:
9410 if (need_vex)
9411 {
9412 /* The prefix in VEX is implicit. */
9413 switch (vex.prefix)
9414 {
9415 case 0:
9416 vindex = 0;
9417 break;
9418 case REPE_PREFIX_OPCODE:
9419 vindex = 1;
9420 break;
9421 case DATA_PREFIX_OPCODE:
9422 vindex = 2;
9423 break;
9424 case REPNE_PREFIX_OPCODE:
9425 vindex = 3;
9426 break;
9427 default:
9428 abort ();
9429 break;
9430 }
9431 }
9432 else
9433 {
9434 int last_prefix = -1;
9435 int prefix = 0;
9436 vindex = 0;
9437 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9438 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9439 last one wins. */
9440 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9441 {
9442 if (last_repz_prefix > last_repnz_prefix)
9443 {
9444 vindex = 1;
9445 prefix = PREFIX_REPZ;
9446 last_prefix = last_repz_prefix;
9447 }
9448 else
9449 {
9450 vindex = 3;
9451 prefix = PREFIX_REPNZ;
9452 last_prefix = last_repnz_prefix;
9453 }
9454
9455 /* Check if prefix should be ignored. */
9456 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9457 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9458 & prefix) != 0
9459 && !prefix_table[dp->op[1].bytemode][vindex].name)
9460 vindex = 0;
9461 }
9462
9463 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
9464 {
9465 vindex = 2;
9466 prefix = PREFIX_DATA;
9467 last_prefix = last_data_prefix;
9468 }
9469
9470 if (vindex != 0)
9471 {
9472 used_prefixes |= prefix;
9473 all_prefixes[last_prefix] = 0;
9474 }
9475 }
9476 dp = &prefix_table[dp->op[1].bytemode][vindex];
9477 break;
9478
9479 case USE_X86_64_TABLE:
9480 vindex = address_mode == mode_64bit ? 1 : 0;
9481 dp = &x86_64_table[dp->op[1].bytemode][vindex];
9482 break;
9483
9484 case USE_3BYTE_TABLE:
9485 FETCH_DATA (info, codep + 2);
9486 vindex = *codep++;
9487 dp = &three_byte_table[dp->op[1].bytemode][vindex];
9488 end_codep = codep;
9489 modrm.mod = (*codep >> 6) & 3;
9490 modrm.reg = (*codep >> 3) & 7;
9491 modrm.rm = *codep & 7;
9492 break;
9493
9494 case USE_VEX_LEN_TABLE:
9495 if (!need_vex)
9496 abort ();
9497
9498 switch (vex.length)
9499 {
9500 case 128:
9501 vindex = 0;
9502 break;
9503 case 256:
9504 vindex = 1;
9505 break;
9506 default:
9507 abort ();
9508 break;
9509 }
9510
9511 dp = &vex_len_table[dp->op[1].bytemode][vindex];
9512 break;
9513
9514 case USE_EVEX_LEN_TABLE:
9515 if (!vex.evex)
9516 abort ();
9517
9518 switch (vex.length)
9519 {
9520 case 128:
9521 vindex = 0;
9522 break;
9523 case 256:
9524 vindex = 1;
9525 break;
9526 case 512:
9527 vindex = 2;
9528 break;
9529 default:
9530 abort ();
9531 break;
9532 }
9533
9534 dp = &evex_len_table[dp->op[1].bytemode][vindex];
9535 break;
9536
9537 case USE_XOP_8F_TABLE:
9538 FETCH_DATA (info, codep + 3);
9539 rex = ~(*codep >> 5) & 0x7;
9540
9541 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9542 switch ((*codep & 0x1f))
9543 {
9544 default:
9545 dp = &bad_opcode;
9546 return dp;
9547 case 0x8:
9548 vex_table_index = XOP_08;
9549 break;
9550 case 0x9:
9551 vex_table_index = XOP_09;
9552 break;
9553 case 0xa:
9554 vex_table_index = XOP_0A;
9555 break;
9556 }
9557 codep++;
9558 vex.w = *codep & 0x80;
9559 if (vex.w && address_mode == mode_64bit)
9560 rex |= REX_W;
9561
9562 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9563 if (address_mode != mode_64bit)
9564 {
9565 /* In 16/32-bit mode REX_B is silently ignored. */
9566 rex &= ~REX_B;
9567 }
9568
9569 vex.length = (*codep & 0x4) ? 256 : 128;
9570 switch ((*codep & 0x3))
9571 {
9572 case 0:
9573 break;
9574 case 1:
9575 vex.prefix = DATA_PREFIX_OPCODE;
9576 break;
9577 case 2:
9578 vex.prefix = REPE_PREFIX_OPCODE;
9579 break;
9580 case 3:
9581 vex.prefix = REPNE_PREFIX_OPCODE;
9582 break;
9583 }
9584 need_vex = 1;
9585 codep++;
9586 vindex = *codep++;
9587 dp = &xop_table[vex_table_index][vindex];
9588
9589 end_codep = codep;
9590 FETCH_DATA (info, codep + 1);
9591 modrm.mod = (*codep >> 6) & 3;
9592 modrm.reg = (*codep >> 3) & 7;
9593 modrm.rm = *codep & 7;
9594
9595 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9596 having to decode the bits for every otherwise valid encoding. */
9597 if (vex.prefix)
9598 return &bad_opcode;
9599 break;
9600
9601 case USE_VEX_C4_TABLE:
9602 /* VEX prefix. */
9603 FETCH_DATA (info, codep + 3);
9604 rex = ~(*codep >> 5) & 0x7;
9605 switch ((*codep & 0x1f))
9606 {
9607 default:
9608 dp = &bad_opcode;
9609 return dp;
9610 case 0x1:
9611 vex_table_index = VEX_0F;
9612 break;
9613 case 0x2:
9614 vex_table_index = VEX_0F38;
9615 break;
9616 case 0x3:
9617 vex_table_index = VEX_0F3A;
9618 break;
9619 }
9620 codep++;
9621 vex.w = *codep & 0x80;
9622 if (address_mode == mode_64bit)
9623 {
9624 if (vex.w)
9625 rex |= REX_W;
9626 }
9627 else
9628 {
9629 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9630 is ignored, other REX bits are 0 and the highest bit in
9631 VEX.vvvv is also ignored (but we mustn't clear it here). */
9632 rex = 0;
9633 }
9634 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9635 vex.length = (*codep & 0x4) ? 256 : 128;
9636 switch ((*codep & 0x3))
9637 {
9638 case 0:
9639 break;
9640 case 1:
9641 vex.prefix = DATA_PREFIX_OPCODE;
9642 break;
9643 case 2:
9644 vex.prefix = REPE_PREFIX_OPCODE;
9645 break;
9646 case 3:
9647 vex.prefix = REPNE_PREFIX_OPCODE;
9648 break;
9649 }
9650 need_vex = 1;
9651 codep++;
9652 vindex = *codep++;
9653 dp = &vex_table[vex_table_index][vindex];
9654 end_codep = codep;
9655 /* There is no MODRM byte for VEX0F 77. */
9656 if (vex_table_index != VEX_0F || vindex != 0x77)
9657 {
9658 FETCH_DATA (info, codep + 1);
9659 modrm.mod = (*codep >> 6) & 3;
9660 modrm.reg = (*codep >> 3) & 7;
9661 modrm.rm = *codep & 7;
9662 }
9663 break;
9664
9665 case USE_VEX_C5_TABLE:
9666 /* VEX prefix. */
9667 FETCH_DATA (info, codep + 2);
9668 rex = (*codep & 0x80) ? 0 : REX_R;
9669
9670 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9671 VEX.vvvv is 1. */
9672 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9673 vex.length = (*codep & 0x4) ? 256 : 128;
9674 switch ((*codep & 0x3))
9675 {
9676 case 0:
9677 break;
9678 case 1:
9679 vex.prefix = DATA_PREFIX_OPCODE;
9680 break;
9681 case 2:
9682 vex.prefix = REPE_PREFIX_OPCODE;
9683 break;
9684 case 3:
9685 vex.prefix = REPNE_PREFIX_OPCODE;
9686 break;
9687 }
9688 need_vex = 1;
9689 codep++;
9690 vindex = *codep++;
9691 dp = &vex_table[dp->op[1].bytemode][vindex];
9692 end_codep = codep;
9693 /* There is no MODRM byte for VEX 77. */
9694 if (vindex != 0x77)
9695 {
9696 FETCH_DATA (info, codep + 1);
9697 modrm.mod = (*codep >> 6) & 3;
9698 modrm.reg = (*codep >> 3) & 7;
9699 modrm.rm = *codep & 7;
9700 }
9701 break;
9702
9703 case USE_VEX_W_TABLE:
9704 if (!need_vex)
9705 abort ();
9706
9707 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
9708 break;
9709
9710 case USE_EVEX_TABLE:
9711 two_source_ops = 0;
9712 /* EVEX prefix. */
9713 vex.evex = 1;
9714 FETCH_DATA (info, codep + 4);
9715 /* The first byte after 0x62. */
9716 rex = ~(*codep >> 5) & 0x7;
9717 vex.r = *codep & 0x10;
9718 switch ((*codep & 0xf))
9719 {
9720 default:
9721 return &bad_opcode;
9722 case 0x1:
9723 vex_table_index = EVEX_0F;
9724 break;
9725 case 0x2:
9726 vex_table_index = EVEX_0F38;
9727 break;
9728 case 0x3:
9729 vex_table_index = EVEX_0F3A;
9730 break;
9731 }
9732
9733 /* The second byte after 0x62. */
9734 codep++;
9735 vex.w = *codep & 0x80;
9736 if (vex.w && address_mode == mode_64bit)
9737 rex |= REX_W;
9738
9739 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9740
9741 /* The U bit. */
9742 if (!(*codep & 0x4))
9743 return &bad_opcode;
9744
9745 switch ((*codep & 0x3))
9746 {
9747 case 0:
9748 break;
9749 case 1:
9750 vex.prefix = DATA_PREFIX_OPCODE;
9751 break;
9752 case 2:
9753 vex.prefix = REPE_PREFIX_OPCODE;
9754 break;
9755 case 3:
9756 vex.prefix = REPNE_PREFIX_OPCODE;
9757 break;
9758 }
9759
9760 /* The third byte after 0x62. */
9761 codep++;
9762
9763 /* Remember the static rounding bits. */
9764 vex.ll = (*codep >> 5) & 3;
9765 vex.b = (*codep & 0x10) != 0;
9766
9767 vex.v = *codep & 0x8;
9768 vex.mask_register_specifier = *codep & 0x7;
9769 vex.zeroing = *codep & 0x80;
9770
9771 if (address_mode != mode_64bit)
9772 {
9773 /* In 16/32-bit mode silently ignore following bits. */
9774 rex &= ~REX_B;
9775 vex.r = 1;
9776 vex.v = 1;
9777 }
9778
9779 need_vex = 1;
9780 codep++;
9781 vindex = *codep++;
9782 dp = &evex_table[vex_table_index][vindex];
9783 end_codep = codep;
9784 FETCH_DATA (info, codep + 1);
9785 modrm.mod = (*codep >> 6) & 3;
9786 modrm.reg = (*codep >> 3) & 7;
9787 modrm.rm = *codep & 7;
9788
9789 /* Set vector length. */
9790 if (modrm.mod == 3 && vex.b)
9791 vex.length = 512;
9792 else
9793 {
9794 switch (vex.ll)
9795 {
9796 case 0x0:
9797 vex.length = 128;
9798 break;
9799 case 0x1:
9800 vex.length = 256;
9801 break;
9802 case 0x2:
9803 vex.length = 512;
9804 break;
9805 default:
9806 return &bad_opcode;
9807 }
9808 }
9809 break;
9810
9811 case 0:
9812 dp = &bad_opcode;
9813 break;
9814
9815 default:
9816 abort ();
9817 }
9818
9819 if (dp->name != NULL)
9820 return dp;
9821 else
9822 return get_valid_dis386 (dp, info);
9823 }
9824
9825 static void
9826 get_sib (disassemble_info *info, int sizeflag)
9827 {
9828 /* If modrm.mod == 3, operand must be register. */
9829 if (need_modrm
9830 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
9831 && modrm.mod != 3
9832 && modrm.rm == 4)
9833 {
9834 FETCH_DATA (info, codep + 2);
9835 sib.index = (codep [1] >> 3) & 7;
9836 sib.scale = (codep [1] >> 6) & 3;
9837 sib.base = codep [1] & 7;
9838 }
9839 }
9840
9841 static int
9842 print_insn (bfd_vma pc, disassemble_info *info)
9843 {
9844 const struct dis386 *dp;
9845 int i;
9846 char *op_txt[MAX_OPERANDS];
9847 int needcomma;
9848 int sizeflag, orig_sizeflag;
9849 const char *p;
9850 struct dis_private priv;
9851 int prefix_length;
9852
9853 priv.orig_sizeflag = AFLAG | DFLAG;
9854 if ((info->mach & bfd_mach_i386_i386) != 0)
9855 address_mode = mode_32bit;
9856 else if (info->mach == bfd_mach_i386_i8086)
9857 {
9858 address_mode = mode_16bit;
9859 priv.orig_sizeflag = 0;
9860 }
9861 else
9862 address_mode = mode_64bit;
9863
9864 if (intel_syntax == (char) -1)
9865 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
9866
9867 for (p = info->disassembler_options; p != NULL; )
9868 {
9869 if (CONST_STRNEQ (p, "amd64"))
9870 isa64 = amd64;
9871 else if (CONST_STRNEQ (p, "intel64"))
9872 isa64 = intel64;
9873 else if (CONST_STRNEQ (p, "x86-64"))
9874 {
9875 address_mode = mode_64bit;
9876 priv.orig_sizeflag |= AFLAG | DFLAG;
9877 }
9878 else if (CONST_STRNEQ (p, "i386"))
9879 {
9880 address_mode = mode_32bit;
9881 priv.orig_sizeflag |= AFLAG | DFLAG;
9882 }
9883 else if (CONST_STRNEQ (p, "i8086"))
9884 {
9885 address_mode = mode_16bit;
9886 priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9887 }
9888 else if (CONST_STRNEQ (p, "intel"))
9889 {
9890 intel_syntax = 1;
9891 if (CONST_STRNEQ (p + 5, "-mnemonic"))
9892 intel_mnemonic = 1;
9893 }
9894 else if (CONST_STRNEQ (p, "att"))
9895 {
9896 intel_syntax = 0;
9897 if (CONST_STRNEQ (p + 3, "-mnemonic"))
9898 intel_mnemonic = 0;
9899 }
9900 else if (CONST_STRNEQ (p, "addr"))
9901 {
9902 if (address_mode == mode_64bit)
9903 {
9904 if (p[4] == '3' && p[5] == '2')
9905 priv.orig_sizeflag &= ~AFLAG;
9906 else if (p[4] == '6' && p[5] == '4')
9907 priv.orig_sizeflag |= AFLAG;
9908 }
9909 else
9910 {
9911 if (p[4] == '1' && p[5] == '6')
9912 priv.orig_sizeflag &= ~AFLAG;
9913 else if (p[4] == '3' && p[5] == '2')
9914 priv.orig_sizeflag |= AFLAG;
9915 }
9916 }
9917 else if (CONST_STRNEQ (p, "data"))
9918 {
9919 if (p[4] == '1' && p[5] == '6')
9920 priv.orig_sizeflag &= ~DFLAG;
9921 else if (p[4] == '3' && p[5] == '2')
9922 priv.orig_sizeflag |= DFLAG;
9923 }
9924 else if (CONST_STRNEQ (p, "suffix"))
9925 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9926
9927 p = strchr (p, ',');
9928 if (p != NULL)
9929 p++;
9930 }
9931
9932 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9933 {
9934 (*info->fprintf_func) (info->stream,
9935 _("64-bit address is disabled"));
9936 return -1;
9937 }
9938
9939 if (intel_syntax)
9940 {
9941 names64 = intel_names64;
9942 names32 = intel_names32;
9943 names16 = intel_names16;
9944 names8 = intel_names8;
9945 names8rex = intel_names8rex;
9946 names_seg = intel_names_seg;
9947 names_mm = intel_names_mm;
9948 names_bnd = intel_names_bnd;
9949 names_xmm = intel_names_xmm;
9950 names_ymm = intel_names_ymm;
9951 names_zmm = intel_names_zmm;
9952 names_tmm = intel_names_tmm;
9953 index64 = intel_index64;
9954 index32 = intel_index32;
9955 names_mask = intel_names_mask;
9956 index16 = intel_index16;
9957 open_char = '[';
9958 close_char = ']';
9959 separator_char = '+';
9960 scale_char = '*';
9961 }
9962 else
9963 {
9964 names64 = att_names64;
9965 names32 = att_names32;
9966 names16 = att_names16;
9967 names8 = att_names8;
9968 names8rex = att_names8rex;
9969 names_seg = att_names_seg;
9970 names_mm = att_names_mm;
9971 names_bnd = att_names_bnd;
9972 names_xmm = att_names_xmm;
9973 names_ymm = att_names_ymm;
9974 names_zmm = att_names_zmm;
9975 names_tmm = att_names_tmm;
9976 index64 = att_index64;
9977 index32 = att_index32;
9978 names_mask = att_names_mask;
9979 index16 = att_index16;
9980 open_char = '(';
9981 close_char = ')';
9982 separator_char = ',';
9983 scale_char = ',';
9984 }
9985
9986 /* The output looks better if we put 7 bytes on a line, since that
9987 puts most long word instructions on a single line. Use 8 bytes
9988 for Intel L1OM. */
9989 if ((info->mach & bfd_mach_l1om) != 0)
9990 info->bytes_per_line = 8;
9991 else
9992 info->bytes_per_line = 7;
9993
9994 info->private_data = &priv;
9995 priv.max_fetched = priv.the_buffer;
9996 priv.insn_start = pc;
9997
9998 obuf[0] = 0;
9999 for (i = 0; i < MAX_OPERANDS; ++i)
10000 {
10001 op_out[i][0] = 0;
10002 op_index[i] = -1;
10003 }
10004
10005 the_info = info;
10006 start_pc = pc;
10007 start_codep = priv.the_buffer;
10008 codep = priv.the_buffer;
10009
10010 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
10011 {
10012 const char *name;
10013
10014 /* Getting here means we tried for data but didn't get it. That
10015 means we have an incomplete instruction of some sort. Just
10016 print the first byte as a prefix or a .byte pseudo-op. */
10017 if (codep > priv.the_buffer)
10018 {
10019 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10020 if (name != NULL)
10021 (*info->fprintf_func) (info->stream, "%s", name);
10022 else
10023 {
10024 /* Just print the first byte as a .byte instruction. */
10025 (*info->fprintf_func) (info->stream, ".byte 0x%x",
10026 (unsigned int) priv.the_buffer[0]);
10027 }
10028
10029 return 1;
10030 }
10031
10032 return -1;
10033 }
10034
10035 obufp = obuf;
10036 sizeflag = priv.orig_sizeflag;
10037
10038 if (!ckprefix () || rex_used)
10039 {
10040 /* Too many prefixes or unused REX prefixes. */
10041 for (i = 0;
10042 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
10043 i++)
10044 (*info->fprintf_func) (info->stream, "%s%s",
10045 i == 0 ? "" : " ",
10046 prefix_name (all_prefixes[i], sizeflag));
10047 return i;
10048 }
10049
10050 insn_codep = codep;
10051
10052 FETCH_DATA (info, codep + 1);
10053 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
10054
10055 if (((prefixes & PREFIX_FWAIT)
10056 && ((*codep < 0xd8) || (*codep > 0xdf))))
10057 {
10058 /* Handle prefixes before fwait. */
10059 for (i = 0; i < fwait_prefix && all_prefixes[i];
10060 i++)
10061 (*info->fprintf_func) (info->stream, "%s ",
10062 prefix_name (all_prefixes[i], sizeflag));
10063 (*info->fprintf_func) (info->stream, "fwait");
10064 return i + 1;
10065 }
10066
10067 if (*codep == 0x0f)
10068 {
10069 unsigned char threebyte;
10070
10071 codep++;
10072 FETCH_DATA (info, codep + 1);
10073 threebyte = *codep;
10074 dp = &dis386_twobyte[threebyte];
10075 need_modrm = twobyte_has_modrm[threebyte];
10076 codep++;
10077 }
10078 else
10079 {
10080 dp = &dis386[*codep];
10081 need_modrm = onebyte_has_modrm[*codep];
10082 codep++;
10083 }
10084
10085 /* Save sizeflag for printing the extra prefixes later before updating
10086 it for mnemonic and operand processing. The prefix names depend
10087 only on the address mode. */
10088 orig_sizeflag = sizeflag;
10089 if (prefixes & PREFIX_ADDR)
10090 sizeflag ^= AFLAG;
10091 if ((prefixes & PREFIX_DATA))
10092 sizeflag ^= DFLAG;
10093
10094 end_codep = codep;
10095 if (need_modrm)
10096 {
10097 FETCH_DATA (info, codep + 1);
10098 modrm.mod = (*codep >> 6) & 3;
10099 modrm.reg = (*codep >> 3) & 7;
10100 modrm.rm = *codep & 7;
10101 }
10102 else
10103 memset (&modrm, 0, sizeof (modrm));
10104
10105 need_vex = 0;
10106 memset (&vex, 0, sizeof (vex));
10107
10108 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
10109 {
10110 get_sib (info, sizeflag);
10111 dofloat (sizeflag);
10112 }
10113 else
10114 {
10115 dp = get_valid_dis386 (dp, info);
10116 if (dp != NULL && putop (dp->name, sizeflag) == 0)
10117 {
10118 get_sib (info, sizeflag);
10119 for (i = 0; i < MAX_OPERANDS; ++i)
10120 {
10121 obufp = op_out[i];
10122 op_ad = MAX_OPERANDS - 1 - i;
10123 if (dp->op[i].rtn)
10124 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10125 /* For EVEX instruction after the last operand masking
10126 should be printed. */
10127 if (i == 0 && vex.evex)
10128 {
10129 /* Don't print {%k0}. */
10130 if (vex.mask_register_specifier)
10131 {
10132 oappend ("{");
10133 oappend (names_mask[vex.mask_register_specifier]);
10134 oappend ("}");
10135 }
10136 if (vex.zeroing)
10137 oappend ("{z}");
10138 }
10139 }
10140 }
10141 }
10142
10143 /* Clear instruction information. */
10144 if (the_info)
10145 {
10146 the_info->insn_info_valid = 0;
10147 the_info->branch_delay_insns = 0;
10148 the_info->data_size = 0;
10149 the_info->insn_type = dis_noninsn;
10150 the_info->target = 0;
10151 the_info->target2 = 0;
10152 }
10153
10154 /* Reset jump operation indicator. */
10155 op_is_jump = FALSE;
10156
10157 {
10158 int jump_detection = 0;
10159
10160 /* Extract flags. */
10161 for (i = 0; i < MAX_OPERANDS; ++i)
10162 {
10163 if ((dp->op[i].rtn == OP_J)
10164 || (dp->op[i].rtn == OP_indirE))
10165 jump_detection |= 1;
10166 else if ((dp->op[i].rtn == BND_Fixup)
10167 || (!dp->op[i].rtn && !dp->op[i].bytemode))
10168 jump_detection |= 2;
10169 else if ((dp->op[i].bytemode == cond_jump_mode)
10170 || (dp->op[i].bytemode == loop_jcxz_mode))
10171 jump_detection |= 4;
10172 }
10173
10174 /* Determine if this is a jump or branch. */
10175 if ((jump_detection & 0x3) == 0x3)
10176 {
10177 op_is_jump = TRUE;
10178 if (jump_detection & 0x4)
10179 the_info->insn_type = dis_condbranch;
10180 else
10181 the_info->insn_type =
10182 (dp->name && !strncmp(dp->name, "call", 4))
10183 ? dis_jsr : dis_branch;
10184 }
10185 }
10186
10187 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
10188 are all 0s in inverted form. */
10189 if (need_vex && vex.register_specifier != 0)
10190 {
10191 (*info->fprintf_func) (info->stream, "(bad)");
10192 return end_codep - priv.the_buffer;
10193 }
10194
10195 switch (dp->prefix_requirement)
10196 {
10197 case PREFIX_DATA:
10198 /* If only the data prefix is marked as mandatory, its absence renders
10199 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
10200 if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA))
10201 {
10202 (*info->fprintf_func) (info->stream, "(bad)");
10203 return end_codep - priv.the_buffer;
10204 }
10205 used_prefixes |= PREFIX_DATA;
10206 /* Fall through. */
10207 case PREFIX_OPCODE:
10208 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
10209 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
10210 used by putop and MMX/SSE operand and may be overridden by the
10211 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
10212 separately. */
10213 if (((need_vex
10214 ? vex.prefix == REPE_PREFIX_OPCODE
10215 || vex.prefix == REPNE_PREFIX_OPCODE
10216 : (prefixes
10217 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
10218 && (used_prefixes
10219 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
10220 || (((need_vex
10221 ? vex.prefix == DATA_PREFIX_OPCODE
10222 : ((prefixes
10223 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
10224 == PREFIX_DATA))
10225 && (used_prefixes & PREFIX_DATA) == 0))
10226 || (vex.evex && dp->prefix_requirement != PREFIX_DATA
10227 && !vex.w != !(used_prefixes & PREFIX_DATA)))
10228 {
10229 (*info->fprintf_func) (info->stream, "(bad)");
10230 return end_codep - priv.the_buffer;
10231 }
10232 break;
10233
10234 case PREFIX_IGNORED:
10235 /* Zap data size and rep prefixes from used_prefixes and reinstate their
10236 origins in all_prefixes. */
10237 used_prefixes &= ~PREFIX_OPCODE;
10238 if (last_data_prefix >= 0)
10239 all_prefixes[last_repz_prefix] = 0x66;
10240 if (last_repz_prefix >= 0)
10241 all_prefixes[last_repz_prefix] = 0xf3;
10242 if (last_repnz_prefix >= 0)
10243 all_prefixes[last_repnz_prefix] = 0xf2;
10244 break;
10245 }
10246
10247 /* Check if the REX prefix is used. */
10248 if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
10249 all_prefixes[last_rex_prefix] = 0;
10250
10251 /* Check if the SEG prefix is used. */
10252 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
10253 | PREFIX_FS | PREFIX_GS)) != 0
10254 && (used_prefixes & active_seg_prefix) != 0)
10255 all_prefixes[last_seg_prefix] = 0;
10256
10257 /* Check if the ADDR prefix is used. */
10258 if ((prefixes & PREFIX_ADDR) != 0
10259 && (used_prefixes & PREFIX_ADDR) != 0)
10260 all_prefixes[last_addr_prefix] = 0;
10261
10262 /* Check if the DATA prefix is used. */
10263 if ((prefixes & PREFIX_DATA) != 0
10264 && (used_prefixes & PREFIX_DATA) != 0
10265 && !need_vex)
10266 all_prefixes[last_data_prefix] = 0;
10267
10268 /* Print the extra prefixes. */
10269 prefix_length = 0;
10270 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10271 if (all_prefixes[i])
10272 {
10273 const char *name;
10274 name = prefix_name (all_prefixes[i], orig_sizeflag);
10275 if (name == NULL)
10276 abort ();
10277 prefix_length += strlen (name) + 1;
10278 (*info->fprintf_func) (info->stream, "%s ", name);
10279 }
10280
10281 /* Check maximum code length. */
10282 if ((codep - start_codep) > MAX_CODE_LENGTH)
10283 {
10284 (*info->fprintf_func) (info->stream, "(bad)");
10285 return MAX_CODE_LENGTH;
10286 }
10287
10288 obufp = mnemonicendp;
10289 for (i = strlen (obuf) + prefix_length; i < 6; i++)
10290 oappend (" ");
10291 oappend (" ");
10292 (*info->fprintf_func) (info->stream, "%s", obuf);
10293
10294 /* The enter and bound instructions are printed with operands in the same
10295 order as the intel book; everything else is printed in reverse order. */
10296 if (intel_syntax || two_source_ops)
10297 {
10298 bfd_vma riprel;
10299
10300 for (i = 0; i < MAX_OPERANDS; ++i)
10301 op_txt[i] = op_out[i];
10302
10303 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
10304 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
10305 {
10306 op_txt[2] = op_out[3];
10307 op_txt[3] = op_out[2];
10308 }
10309
10310 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10311 {
10312 op_ad = op_index[i];
10313 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10314 op_index[MAX_OPERANDS - 1 - i] = op_ad;
10315 riprel = op_riprel[i];
10316 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10317 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10318 }
10319 }
10320 else
10321 {
10322 for (i = 0; i < MAX_OPERANDS; ++i)
10323 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10324 }
10325
10326 needcomma = 0;
10327 for (i = 0; i < MAX_OPERANDS; ++i)
10328 if (*op_txt[i])
10329 {
10330 if (needcomma)
10331 (*info->fprintf_func) (info->stream, ",");
10332 if (op_index[i] != -1 && !op_riprel[i])
10333 {
10334 bfd_vma target = (bfd_vma) op_address[op_index[i]];
10335
10336 if (the_info && op_is_jump)
10337 {
10338 the_info->insn_info_valid = 1;
10339 the_info->branch_delay_insns = 0;
10340 the_info->data_size = 0;
10341 the_info->target = target;
10342 the_info->target2 = 0;
10343 }
10344 (*info->print_address_func) (target, info);
10345 }
10346 else
10347 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10348 needcomma = 1;
10349 }
10350
10351 for (i = 0; i < MAX_OPERANDS; i++)
10352 if (op_index[i] != -1 && op_riprel[i])
10353 {
10354 (*info->fprintf_func) (info->stream, " # ");
10355 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
10356 + op_address[op_index[i]]), info);
10357 break;
10358 }
10359 return codep - priv.the_buffer;
10360 }
10361
10362 static const char *float_mem[] = {
10363 /* d8 */
10364 "fadd{s|}",
10365 "fmul{s|}",
10366 "fcom{s|}",
10367 "fcomp{s|}",
10368 "fsub{s|}",
10369 "fsubr{s|}",
10370 "fdiv{s|}",
10371 "fdivr{s|}",
10372 /* d9 */
10373 "fld{s|}",
10374 "(bad)",
10375 "fst{s|}",
10376 "fstp{s|}",
10377 "fldenv{C|C}",
10378 "fldcw",
10379 "fNstenv{C|C}",
10380 "fNstcw",
10381 /* da */
10382 "fiadd{l|}",
10383 "fimul{l|}",
10384 "ficom{l|}",
10385 "ficomp{l|}",
10386 "fisub{l|}",
10387 "fisubr{l|}",
10388 "fidiv{l|}",
10389 "fidivr{l|}",
10390 /* db */
10391 "fild{l|}",
10392 "fisttp{l|}",
10393 "fist{l|}",
10394 "fistp{l|}",
10395 "(bad)",
10396 "fld{t|}",
10397 "(bad)",
10398 "fstp{t|}",
10399 /* dc */
10400 "fadd{l|}",
10401 "fmul{l|}",
10402 "fcom{l|}",
10403 "fcomp{l|}",
10404 "fsub{l|}",
10405 "fsubr{l|}",
10406 "fdiv{l|}",
10407 "fdivr{l|}",
10408 /* dd */
10409 "fld{l|}",
10410 "fisttp{ll|}",
10411 "fst{l||}",
10412 "fstp{l|}",
10413 "frstor{C|C}",
10414 "(bad)",
10415 "fNsave{C|C}",
10416 "fNstsw",
10417 /* de */
10418 "fiadd{s|}",
10419 "fimul{s|}",
10420 "ficom{s|}",
10421 "ficomp{s|}",
10422 "fisub{s|}",
10423 "fisubr{s|}",
10424 "fidiv{s|}",
10425 "fidivr{s|}",
10426 /* df */
10427 "fild{s|}",
10428 "fisttp{s|}",
10429 "fist{s|}",
10430 "fistp{s|}",
10431 "fbld",
10432 "fild{ll|}",
10433 "fbstp",
10434 "fistp{ll|}",
10435 };
10436
10437 static const unsigned char float_mem_mode[] = {
10438 /* d8 */
10439 d_mode,
10440 d_mode,
10441 d_mode,
10442 d_mode,
10443 d_mode,
10444 d_mode,
10445 d_mode,
10446 d_mode,
10447 /* d9 */
10448 d_mode,
10449 0,
10450 d_mode,
10451 d_mode,
10452 0,
10453 w_mode,
10454 0,
10455 w_mode,
10456 /* da */
10457 d_mode,
10458 d_mode,
10459 d_mode,
10460 d_mode,
10461 d_mode,
10462 d_mode,
10463 d_mode,
10464 d_mode,
10465 /* db */
10466 d_mode,
10467 d_mode,
10468 d_mode,
10469 d_mode,
10470 0,
10471 t_mode,
10472 0,
10473 t_mode,
10474 /* dc */
10475 q_mode,
10476 q_mode,
10477 q_mode,
10478 q_mode,
10479 q_mode,
10480 q_mode,
10481 q_mode,
10482 q_mode,
10483 /* dd */
10484 q_mode,
10485 q_mode,
10486 q_mode,
10487 q_mode,
10488 0,
10489 0,
10490 0,
10491 w_mode,
10492 /* de */
10493 w_mode,
10494 w_mode,
10495 w_mode,
10496 w_mode,
10497 w_mode,
10498 w_mode,
10499 w_mode,
10500 w_mode,
10501 /* df */
10502 w_mode,
10503 w_mode,
10504 w_mode,
10505 w_mode,
10506 t_mode,
10507 q_mode,
10508 t_mode,
10509 q_mode
10510 };
10511
10512 #define ST { OP_ST, 0 }
10513 #define STi { OP_STi, 0 }
10514
10515 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10516 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10517 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10518 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10519 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10520 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10521 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10522 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10523 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10524
10525 static const struct dis386 float_reg[][8] = {
10526 /* d8 */
10527 {
10528 { "fadd", { ST, STi }, 0 },
10529 { "fmul", { ST, STi }, 0 },
10530 { "fcom", { STi }, 0 },
10531 { "fcomp", { STi }, 0 },
10532 { "fsub", { ST, STi }, 0 },
10533 { "fsubr", { ST, STi }, 0 },
10534 { "fdiv", { ST, STi }, 0 },
10535 { "fdivr", { ST, STi }, 0 },
10536 },
10537 /* d9 */
10538 {
10539 { "fld", { STi }, 0 },
10540 { "fxch", { STi }, 0 },
10541 { FGRPd9_2 },
10542 { Bad_Opcode },
10543 { FGRPd9_4 },
10544 { FGRPd9_5 },
10545 { FGRPd9_6 },
10546 { FGRPd9_7 },
10547 },
10548 /* da */
10549 {
10550 { "fcmovb", { ST, STi }, 0 },
10551 { "fcmove", { ST, STi }, 0 },
10552 { "fcmovbe",{ ST, STi }, 0 },
10553 { "fcmovu", { ST, STi }, 0 },
10554 { Bad_Opcode },
10555 { FGRPda_5 },
10556 { Bad_Opcode },
10557 { Bad_Opcode },
10558 },
10559 /* db */
10560 {
10561 { "fcmovnb",{ ST, STi }, 0 },
10562 { "fcmovne",{ ST, STi }, 0 },
10563 { "fcmovnbe",{ ST, STi }, 0 },
10564 { "fcmovnu",{ ST, STi }, 0 },
10565 { FGRPdb_4 },
10566 { "fucomi", { ST, STi }, 0 },
10567 { "fcomi", { ST, STi }, 0 },
10568 { Bad_Opcode },
10569 },
10570 /* dc */
10571 {
10572 { "fadd", { STi, ST }, 0 },
10573 { "fmul", { STi, ST }, 0 },
10574 { Bad_Opcode },
10575 { Bad_Opcode },
10576 { "fsub{!M|r}", { STi, ST }, 0 },
10577 { "fsub{M|}", { STi, ST }, 0 },
10578 { "fdiv{!M|r}", { STi, ST }, 0 },
10579 { "fdiv{M|}", { STi, ST }, 0 },
10580 },
10581 /* dd */
10582 {
10583 { "ffree", { STi }, 0 },
10584 { Bad_Opcode },
10585 { "fst", { STi }, 0 },
10586 { "fstp", { STi }, 0 },
10587 { "fucom", { STi }, 0 },
10588 { "fucomp", { STi }, 0 },
10589 { Bad_Opcode },
10590 { Bad_Opcode },
10591 },
10592 /* de */
10593 {
10594 { "faddp", { STi, ST }, 0 },
10595 { "fmulp", { STi, ST }, 0 },
10596 { Bad_Opcode },
10597 { FGRPde_3 },
10598 { "fsub{!M|r}p", { STi, ST }, 0 },
10599 { "fsub{M|}p", { STi, ST }, 0 },
10600 { "fdiv{!M|r}p", { STi, ST }, 0 },
10601 { "fdiv{M|}p", { STi, ST }, 0 },
10602 },
10603 /* df */
10604 {
10605 { "ffreep", { STi }, 0 },
10606 { Bad_Opcode },
10607 { Bad_Opcode },
10608 { Bad_Opcode },
10609 { FGRPdf_4 },
10610 { "fucomip", { ST, STi }, 0 },
10611 { "fcomip", { ST, STi }, 0 },
10612 { Bad_Opcode },
10613 },
10614 };
10615
10616 static char *fgrps[][8] = {
10617 /* Bad opcode 0 */
10618 {
10619 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10620 },
10621
10622 /* d9_2 1 */
10623 {
10624 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10625 },
10626
10627 /* d9_4 2 */
10628 {
10629 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10630 },
10631
10632 /* d9_5 3 */
10633 {
10634 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10635 },
10636
10637 /* d9_6 4 */
10638 {
10639 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10640 },
10641
10642 /* d9_7 5 */
10643 {
10644 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10645 },
10646
10647 /* da_5 6 */
10648 {
10649 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10650 },
10651
10652 /* db_4 7 */
10653 {
10654 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10655 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10656 },
10657
10658 /* de_3 8 */
10659 {
10660 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10661 },
10662
10663 /* df_4 9 */
10664 {
10665 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10666 },
10667 };
10668
10669 static void
10670 swap_operand (void)
10671 {
10672 mnemonicendp[0] = '.';
10673 mnemonicendp[1] = 's';
10674 mnemonicendp += 2;
10675 }
10676
10677 static void
10678 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10679 int sizeflag ATTRIBUTE_UNUSED)
10680 {
10681 /* Skip mod/rm byte. */
10682 MODRM_CHECK;
10683 codep++;
10684 }
10685
10686 static void
10687 dofloat (int sizeflag)
10688 {
10689 const struct dis386 *dp;
10690 unsigned char floatop;
10691
10692 floatop = codep[-1];
10693
10694 if (modrm.mod != 3)
10695 {
10696 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10697
10698 putop (float_mem[fp_indx], sizeflag);
10699 obufp = op_out[0];
10700 op_ad = 2;
10701 OP_E (float_mem_mode[fp_indx], sizeflag);
10702 return;
10703 }
10704 /* Skip mod/rm byte. */
10705 MODRM_CHECK;
10706 codep++;
10707
10708 dp = &float_reg[floatop - 0xd8][modrm.reg];
10709 if (dp->name == NULL)
10710 {
10711 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10712
10713 /* Instruction fnstsw is only one with strange arg. */
10714 if (floatop == 0xdf && codep[-1] == 0xe0)
10715 strcpy (op_out[0], names16[0]);
10716 }
10717 else
10718 {
10719 putop (dp->name, sizeflag);
10720
10721 obufp = op_out[0];
10722 op_ad = 2;
10723 if (dp->op[0].rtn)
10724 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10725
10726 obufp = op_out[1];
10727 op_ad = 1;
10728 if (dp->op[1].rtn)
10729 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10730 }
10731 }
10732
10733 /* Like oappend (below), but S is a string starting with '%'.
10734 In Intel syntax, the '%' is elided. */
10735 static void
10736 oappend_maybe_intel (const char *s)
10737 {
10738 oappend (s + intel_syntax);
10739 }
10740
10741 static void
10742 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10743 {
10744 oappend_maybe_intel ("%st");
10745 }
10746
10747 static void
10748 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10749 {
10750 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10751 oappend_maybe_intel (scratchbuf);
10752 }
10753
10754 /* Capital letters in template are macros. */
10755 static int
10756 putop (const char *in_template, int sizeflag)
10757 {
10758 const char *p;
10759 int alt = 0;
10760 int cond = 1;
10761 unsigned int l = 0, len = 0;
10762 char last[4];
10763
10764 for (p = in_template; *p; p++)
10765 {
10766 if (len > l)
10767 {
10768 if (l >= sizeof (last) || !ISUPPER (*p))
10769 abort ();
10770 last[l++] = *p;
10771 continue;
10772 }
10773 switch (*p)
10774 {
10775 default:
10776 *obufp++ = *p;
10777 break;
10778 case '%':
10779 len++;
10780 break;
10781 case '!':
10782 cond = 0;
10783 break;
10784 case '{':
10785 if (intel_syntax)
10786 {
10787 while (*++p != '|')
10788 if (*p == '}' || *p == '\0')
10789 abort ();
10790 alt = 1;
10791 }
10792 break;
10793 case '|':
10794 while (*++p != '}')
10795 {
10796 if (*p == '\0')
10797 abort ();
10798 }
10799 break;
10800 case '}':
10801 alt = 0;
10802 break;
10803 case 'A':
10804 if (intel_syntax)
10805 break;
10806 if ((need_modrm && modrm.mod != 3)
10807 || (sizeflag & SUFFIX_ALWAYS))
10808 *obufp++ = 'b';
10809 break;
10810 case 'B':
10811 if (l == 0)
10812 {
10813 case_B:
10814 if (intel_syntax)
10815 break;
10816 if (sizeflag & SUFFIX_ALWAYS)
10817 *obufp++ = 'b';
10818 }
10819 else if (l == 1 && last[0] == 'L')
10820 {
10821 if (address_mode == mode_64bit
10822 && !(prefixes & PREFIX_ADDR))
10823 {
10824 *obufp++ = 'a';
10825 *obufp++ = 'b';
10826 *obufp++ = 's';
10827 }
10828
10829 goto case_B;
10830 }
10831 else
10832 abort ();
10833 break;
10834 case 'C':
10835 if (intel_syntax && !alt)
10836 break;
10837 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10838 {
10839 if (sizeflag & DFLAG)
10840 *obufp++ = intel_syntax ? 'd' : 'l';
10841 else
10842 *obufp++ = intel_syntax ? 'w' : 's';
10843 used_prefixes |= (prefixes & PREFIX_DATA);
10844 }
10845 break;
10846 case 'D':
10847 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10848 break;
10849 USED_REX (REX_W);
10850 if (modrm.mod == 3)
10851 {
10852 if (rex & REX_W)
10853 *obufp++ = 'q';
10854 else
10855 {
10856 if (sizeflag & DFLAG)
10857 *obufp++ = intel_syntax ? 'd' : 'l';
10858 else
10859 *obufp++ = 'w';
10860 used_prefixes |= (prefixes & PREFIX_DATA);
10861 }
10862 }
10863 else
10864 *obufp++ = 'w';
10865 break;
10866 case 'E': /* For jcxz/jecxz */
10867 if (address_mode == mode_64bit)
10868 {
10869 if (sizeflag & AFLAG)
10870 *obufp++ = 'r';
10871 else
10872 *obufp++ = 'e';
10873 }
10874 else
10875 if (sizeflag & AFLAG)
10876 *obufp++ = 'e';
10877 used_prefixes |= (prefixes & PREFIX_ADDR);
10878 break;
10879 case 'F':
10880 if (intel_syntax)
10881 break;
10882 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10883 {
10884 if (sizeflag & AFLAG)
10885 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10886 else
10887 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10888 used_prefixes |= (prefixes & PREFIX_ADDR);
10889 }
10890 break;
10891 case 'G':
10892 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10893 break;
10894 if ((rex & REX_W) || (sizeflag & DFLAG))
10895 *obufp++ = 'l';
10896 else
10897 *obufp++ = 'w';
10898 if (!(rex & REX_W))
10899 used_prefixes |= (prefixes & PREFIX_DATA);
10900 break;
10901 case 'H':
10902 if (intel_syntax)
10903 break;
10904 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10905 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10906 {
10907 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10908 *obufp++ = ',';
10909 *obufp++ = 'p';
10910
10911 /* Set active_seg_prefix even if not set in 64-bit mode
10912 because here it is a valid branch hint. */
10913 if (prefixes & PREFIX_DS)
10914 {
10915 active_seg_prefix = PREFIX_DS;
10916 *obufp++ = 't';
10917 }
10918 else
10919 {
10920 active_seg_prefix = PREFIX_CS;
10921 *obufp++ = 'n';
10922 }
10923 }
10924 break;
10925 case 'K':
10926 USED_REX (REX_W);
10927 if (rex & REX_W)
10928 *obufp++ = 'q';
10929 else
10930 *obufp++ = 'd';
10931 break;
10932 case 'L':
10933 abort ();
10934 case 'M':
10935 if (intel_mnemonic != cond)
10936 *obufp++ = 'r';
10937 break;
10938 case 'N':
10939 if ((prefixes & PREFIX_FWAIT) == 0)
10940 *obufp++ = 'n';
10941 else
10942 used_prefixes |= PREFIX_FWAIT;
10943 break;
10944 case 'O':
10945 USED_REX (REX_W);
10946 if (rex & REX_W)
10947 *obufp++ = 'o';
10948 else if (intel_syntax && (sizeflag & DFLAG))
10949 *obufp++ = 'q';
10950 else
10951 *obufp++ = 'd';
10952 if (!(rex & REX_W))
10953 used_prefixes |= (prefixes & PREFIX_DATA);
10954 break;
10955 case '@':
10956 if (address_mode == mode_64bit
10957 && (isa64 == intel64 || (rex & REX_W)
10958 || !(prefixes & PREFIX_DATA)))
10959 {
10960 if (sizeflag & SUFFIX_ALWAYS)
10961 *obufp++ = 'q';
10962 break;
10963 }
10964 /* Fall through. */
10965 case 'P':
10966 if (l == 0)
10967 {
10968 if ((modrm.mod == 3 || !cond)
10969 && !(sizeflag & SUFFIX_ALWAYS))
10970 break;
10971 /* Fall through. */
10972 case 'T':
10973 if ((!(rex & REX_W) && (prefixes & PREFIX_DATA))
10974 || ((sizeflag & SUFFIX_ALWAYS)
10975 && address_mode != mode_64bit))
10976 {
10977 *obufp++ = (sizeflag & DFLAG) ?
10978 intel_syntax ? 'd' : 'l' : 'w';
10979 used_prefixes |= (prefixes & PREFIX_DATA);
10980 }
10981 else if (sizeflag & SUFFIX_ALWAYS)
10982 *obufp++ = 'q';
10983 }
10984 else if (l == 1 && last[0] == 'L')
10985 {
10986 if ((prefixes & PREFIX_DATA)
10987 || (rex & REX_W)
10988 || (sizeflag & SUFFIX_ALWAYS))
10989 {
10990 USED_REX (REX_W);
10991 if (rex & REX_W)
10992 *obufp++ = 'q';
10993 else
10994 {
10995 if (sizeflag & DFLAG)
10996 *obufp++ = intel_syntax ? 'd' : 'l';
10997 else
10998 *obufp++ = 'w';
10999 used_prefixes |= (prefixes & PREFIX_DATA);
11000 }
11001 }
11002 }
11003 else
11004 abort ();
11005 break;
11006 case 'Q':
11007 if (l == 0)
11008 {
11009 if (intel_syntax && !alt)
11010 break;
11011 USED_REX (REX_W);
11012 if ((need_modrm && modrm.mod != 3)
11013 || (sizeflag & SUFFIX_ALWAYS))
11014 {
11015 if (rex & REX_W)
11016 *obufp++ = 'q';
11017 else
11018 {
11019 if (sizeflag & DFLAG)
11020 *obufp++ = intel_syntax ? 'd' : 'l';
11021 else
11022 *obufp++ = 'w';
11023 used_prefixes |= (prefixes & PREFIX_DATA);
11024 }
11025 }
11026 }
11027 else if (l == 1 && last[0] == 'D')
11028 *obufp++ = vex.w ? 'q' : 'd';
11029 else if (l == 1 && last[0] == 'L')
11030 {
11031 if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
11032 : address_mode != mode_64bit)
11033 break;
11034 if ((rex & REX_W))
11035 {
11036 USED_REX (REX_W);
11037 *obufp++ = 'q';
11038 }
11039 else if((address_mode == mode_64bit && cond)
11040 || (sizeflag & SUFFIX_ALWAYS))
11041 *obufp++ = intel_syntax? 'd' : 'l';
11042 }
11043 else
11044 abort ();
11045 break;
11046 case 'R':
11047 USED_REX (REX_W);
11048 if (rex & REX_W)
11049 *obufp++ = 'q';
11050 else if (sizeflag & DFLAG)
11051 {
11052 if (intel_syntax)
11053 *obufp++ = 'd';
11054 else
11055 *obufp++ = 'l';
11056 }
11057 else
11058 *obufp++ = 'w';
11059 if (intel_syntax && !p[1]
11060 && ((rex & REX_W) || (sizeflag & DFLAG)))
11061 *obufp++ = 'e';
11062 if (!(rex & REX_W))
11063 used_prefixes |= (prefixes & PREFIX_DATA);
11064 break;
11065 case 'S':
11066 if (l == 0)
11067 {
11068 case_S:
11069 if (intel_syntax)
11070 break;
11071 if (sizeflag & SUFFIX_ALWAYS)
11072 {
11073 if (rex & REX_W)
11074 *obufp++ = 'q';
11075 else
11076 {
11077 if (sizeflag & DFLAG)
11078 *obufp++ = 'l';
11079 else
11080 *obufp++ = 'w';
11081 used_prefixes |= (prefixes & PREFIX_DATA);
11082 }
11083 }
11084 }
11085 else if (l == 1 && last[0] == 'L')
11086 {
11087 if (address_mode == mode_64bit
11088 && !(prefixes & PREFIX_ADDR))
11089 {
11090 *obufp++ = 'a';
11091 *obufp++ = 'b';
11092 *obufp++ = 's';
11093 }
11094
11095 goto case_S;
11096 }
11097 else
11098 abort ();
11099 break;
11100 case 'V':
11101 if (l == 0)
11102 abort ();
11103 else if (l == 1
11104 && (last[0] == 'L' || last[0] == 'X'))
11105 {
11106 if (last[0] == 'X')
11107 {
11108 *obufp++ = '{';
11109 *obufp++ = 'v';
11110 *obufp++ = 'e';
11111 *obufp++ = 'x';
11112 *obufp++ = '}';
11113 }
11114 else if (rex & REX_W)
11115 {
11116 *obufp++ = 'a';
11117 *obufp++ = 'b';
11118 *obufp++ = 's';
11119 }
11120 }
11121 else
11122 abort ();
11123 goto case_S;
11124 case 'W':
11125 if (l == 0)
11126 {
11127 /* operand size flag for cwtl, cbtw */
11128 USED_REX (REX_W);
11129 if (rex & REX_W)
11130 {
11131 if (intel_syntax)
11132 *obufp++ = 'd';
11133 else
11134 *obufp++ = 'l';
11135 }
11136 else if (sizeflag & DFLAG)
11137 *obufp++ = 'w';
11138 else
11139 *obufp++ = 'b';
11140 if (!(rex & REX_W))
11141 used_prefixes |= (prefixes & PREFIX_DATA);
11142 }
11143 else if (l == 1)
11144 {
11145 if (!need_vex)
11146 abort ();
11147 if (last[0] == 'X')
11148 *obufp++ = vex.w ? 'd': 's';
11149 else if (last[0] == 'B')
11150 *obufp++ = vex.w ? 'w': 'b';
11151 else
11152 abort ();
11153 }
11154 else
11155 abort ();
11156 break;
11157 case 'X':
11158 if (l != 0)
11159 abort ();
11160 if (need_vex
11161 ? vex.prefix == DATA_PREFIX_OPCODE
11162 : prefixes & PREFIX_DATA)
11163 {
11164 *obufp++ = 'd';
11165 used_prefixes |= PREFIX_DATA;
11166 }
11167 else
11168 *obufp++ = 's';
11169 break;
11170 case 'Y':
11171 if (l == 1 && last[0] == 'X')
11172 {
11173 if (!need_vex)
11174 abort ();
11175 if (intel_syntax
11176 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
11177 break;
11178 switch (vex.length)
11179 {
11180 case 128:
11181 *obufp++ = 'x';
11182 break;
11183 case 256:
11184 *obufp++ = 'y';
11185 break;
11186 case 512:
11187 if (!vex.evex)
11188 default:
11189 abort ();
11190 }
11191 }
11192 else
11193 abort ();
11194 break;
11195 case 'Z':
11196 if (l == 0)
11197 {
11198 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
11199 modrm.mod = 3;
11200 if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11201 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
11202 }
11203 else if (l == 1 && last[0] == 'X')
11204 {
11205 if (!need_vex || !vex.evex)
11206 abort ();
11207 if (intel_syntax
11208 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
11209 break;
11210 switch (vex.length)
11211 {
11212 case 128:
11213 *obufp++ = 'x';
11214 break;
11215 case 256:
11216 *obufp++ = 'y';
11217 break;
11218 case 512:
11219 *obufp++ = 'z';
11220 break;
11221 default:
11222 abort ();
11223 }
11224 }
11225 else
11226 abort ();
11227 break;
11228 case '^':
11229 if (intel_syntax)
11230 break;
11231 if (isa64 == intel64 && (rex & REX_W))
11232 {
11233 USED_REX (REX_W);
11234 *obufp++ = 'q';
11235 break;
11236 }
11237 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11238 {
11239 if (sizeflag & DFLAG)
11240 *obufp++ = 'l';
11241 else
11242 *obufp++ = 'w';
11243 used_prefixes |= (prefixes & PREFIX_DATA);
11244 }
11245 break;
11246 }
11247
11248 if (len == l)
11249 len = l = 0;
11250 }
11251 *obufp = 0;
11252 mnemonicendp = obufp;
11253 return 0;
11254 }
11255
11256 static void
11257 oappend (const char *s)
11258 {
11259 obufp = stpcpy (obufp, s);
11260 }
11261
11262 static void
11263 append_seg (void)
11264 {
11265 /* Only print the active segment register. */
11266 if (!active_seg_prefix)
11267 return;
11268
11269 used_prefixes |= active_seg_prefix;
11270 switch (active_seg_prefix)
11271 {
11272 case PREFIX_CS:
11273 oappend_maybe_intel ("%cs:");
11274 break;
11275 case PREFIX_DS:
11276 oappend_maybe_intel ("%ds:");
11277 break;
11278 case PREFIX_SS:
11279 oappend_maybe_intel ("%ss:");
11280 break;
11281 case PREFIX_ES:
11282 oappend_maybe_intel ("%es:");
11283 break;
11284 case PREFIX_FS:
11285 oappend_maybe_intel ("%fs:");
11286 break;
11287 case PREFIX_GS:
11288 oappend_maybe_intel ("%gs:");
11289 break;
11290 default:
11291 break;
11292 }
11293 }
11294
11295 static void
11296 OP_indirE (int bytemode, int sizeflag)
11297 {
11298 if (!intel_syntax)
11299 oappend ("*");
11300 OP_E (bytemode, sizeflag);
11301 }
11302
11303 static void
11304 print_operand_value (char *buf, int hex, bfd_vma disp)
11305 {
11306 if (address_mode == mode_64bit)
11307 {
11308 if (hex)
11309 {
11310 char tmp[30];
11311 int i;
11312 buf[0] = '0';
11313 buf[1] = 'x';
11314 sprintf_vma (tmp, disp);
11315 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11316 strcpy (buf + 2, tmp + i);
11317 }
11318 else
11319 {
11320 bfd_signed_vma v = disp;
11321 char tmp[30];
11322 int i;
11323 if (v < 0)
11324 {
11325 *(buf++) = '-';
11326 v = -disp;
11327 /* Check for possible overflow on 0x8000000000000000. */
11328 if (v < 0)
11329 {
11330 strcpy (buf, "9223372036854775808");
11331 return;
11332 }
11333 }
11334 if (!v)
11335 {
11336 strcpy (buf, "0");
11337 return;
11338 }
11339
11340 i = 0;
11341 tmp[29] = 0;
11342 while (v)
11343 {
11344 tmp[28 - i] = (v % 10) + '0';
11345 v /= 10;
11346 i++;
11347 }
11348 strcpy (buf, tmp + 29 - i);
11349 }
11350 }
11351 else
11352 {
11353 if (hex)
11354 sprintf (buf, "0x%x", (unsigned int) disp);
11355 else
11356 sprintf (buf, "%d", (int) disp);
11357 }
11358 }
11359
11360 /* Put DISP in BUF as signed hex number. */
11361
11362 static void
11363 print_displacement (char *buf, bfd_vma disp)
11364 {
11365 bfd_signed_vma val = disp;
11366 char tmp[30];
11367 int i, j = 0;
11368
11369 if (val < 0)
11370 {
11371 buf[j++] = '-';
11372 val = -disp;
11373
11374 /* Check for possible overflow. */
11375 if (val < 0)
11376 {
11377 switch (address_mode)
11378 {
11379 case mode_64bit:
11380 strcpy (buf + j, "0x8000000000000000");
11381 break;
11382 case mode_32bit:
11383 strcpy (buf + j, "0x80000000");
11384 break;
11385 case mode_16bit:
11386 strcpy (buf + j, "0x8000");
11387 break;
11388 }
11389 return;
11390 }
11391 }
11392
11393 buf[j++] = '0';
11394 buf[j++] = 'x';
11395
11396 sprintf_vma (tmp, (bfd_vma) val);
11397 for (i = 0; tmp[i] == '0'; i++)
11398 continue;
11399 if (tmp[i] == '\0')
11400 i--;
11401 strcpy (buf + j, tmp + i);
11402 }
11403
11404 static void
11405 intel_operand_size (int bytemode, int sizeflag)
11406 {
11407 if (vex.evex
11408 && vex.b
11409 && (bytemode == x_mode
11410 || bytemode == evex_half_bcst_xmmq_mode))
11411 {
11412 if (vex.w)
11413 oappend ("QWORD PTR ");
11414 else
11415 oappend ("DWORD PTR ");
11416 return;
11417 }
11418 switch (bytemode)
11419 {
11420 case b_mode:
11421 case b_swap_mode:
11422 case dqb_mode:
11423 case db_mode:
11424 oappend ("BYTE PTR ");
11425 break;
11426 case w_mode:
11427 case dw_mode:
11428 case dqw_mode:
11429 oappend ("WORD PTR ");
11430 break;
11431 case indir_v_mode:
11432 if (address_mode == mode_64bit && isa64 == intel64)
11433 {
11434 oappend ("QWORD PTR ");
11435 break;
11436 }
11437 /* Fall through. */
11438 case stack_v_mode:
11439 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11440 {
11441 oappend ("QWORD PTR ");
11442 break;
11443 }
11444 /* Fall through. */
11445 case v_mode:
11446 case v_swap_mode:
11447 case dq_mode:
11448 USED_REX (REX_W);
11449 if (rex & REX_W)
11450 oappend ("QWORD PTR ");
11451 else if (bytemode == dq_mode)
11452 oappend ("DWORD PTR ");
11453 else
11454 {
11455 if (sizeflag & DFLAG)
11456 oappend ("DWORD PTR ");
11457 else
11458 oappend ("WORD PTR ");
11459 used_prefixes |= (prefixes & PREFIX_DATA);
11460 }
11461 break;
11462 case z_mode:
11463 if ((rex & REX_W) || (sizeflag & DFLAG))
11464 *obufp++ = 'D';
11465 oappend ("WORD PTR ");
11466 if (!(rex & REX_W))
11467 used_prefixes |= (prefixes & PREFIX_DATA);
11468 break;
11469 case a_mode:
11470 if (sizeflag & DFLAG)
11471 oappend ("QWORD PTR ");
11472 else
11473 oappend ("DWORD PTR ");
11474 used_prefixes |= (prefixes & PREFIX_DATA);
11475 break;
11476 case movsxd_mode:
11477 if (!(sizeflag & DFLAG) && isa64 == intel64)
11478 oappend ("WORD PTR ");
11479 else
11480 oappend ("DWORD PTR ");
11481 used_prefixes |= (prefixes & PREFIX_DATA);
11482 break;
11483 case d_mode:
11484 case d_swap_mode:
11485 case dqd_mode:
11486 oappend ("DWORD PTR ");
11487 break;
11488 case q_mode:
11489 case q_swap_mode:
11490 oappend ("QWORD PTR ");
11491 break;
11492 case m_mode:
11493 if (address_mode == mode_64bit)
11494 oappend ("QWORD PTR ");
11495 else
11496 oappend ("DWORD PTR ");
11497 break;
11498 case f_mode:
11499 if (sizeflag & DFLAG)
11500 oappend ("FWORD PTR ");
11501 else
11502 oappend ("DWORD PTR ");
11503 used_prefixes |= (prefixes & PREFIX_DATA);
11504 break;
11505 case t_mode:
11506 oappend ("TBYTE PTR ");
11507 break;
11508 case x_mode:
11509 case x_swap_mode:
11510 case evex_x_gscat_mode:
11511 case evex_x_nobcst_mode:
11512 case bw_unit_mode:
11513 if (need_vex)
11514 {
11515 switch (vex.length)
11516 {
11517 case 128:
11518 oappend ("XMMWORD PTR ");
11519 break;
11520 case 256:
11521 oappend ("YMMWORD PTR ");
11522 break;
11523 case 512:
11524 oappend ("ZMMWORD PTR ");
11525 break;
11526 default:
11527 abort ();
11528 }
11529 }
11530 else
11531 oappend ("XMMWORD PTR ");
11532 break;
11533 case xmm_mode:
11534 oappend ("XMMWORD PTR ");
11535 break;
11536 case ymm_mode:
11537 oappend ("YMMWORD PTR ");
11538 break;
11539 case xmmq_mode:
11540 case evex_half_bcst_xmmq_mode:
11541 if (!need_vex)
11542 abort ();
11543
11544 switch (vex.length)
11545 {
11546 case 128:
11547 oappend ("QWORD PTR ");
11548 break;
11549 case 256:
11550 oappend ("XMMWORD PTR ");
11551 break;
11552 case 512:
11553 oappend ("YMMWORD PTR ");
11554 break;
11555 default:
11556 abort ();
11557 }
11558 break;
11559 case xmm_mb_mode:
11560 if (!need_vex)
11561 abort ();
11562
11563 switch (vex.length)
11564 {
11565 case 128:
11566 case 256:
11567 case 512:
11568 oappend ("BYTE PTR ");
11569 break;
11570 default:
11571 abort ();
11572 }
11573 break;
11574 case xmm_mw_mode:
11575 if (!need_vex)
11576 abort ();
11577
11578 switch (vex.length)
11579 {
11580 case 128:
11581 case 256:
11582 case 512:
11583 oappend ("WORD PTR ");
11584 break;
11585 default:
11586 abort ();
11587 }
11588 break;
11589 case xmm_md_mode:
11590 if (!need_vex)
11591 abort ();
11592
11593 switch (vex.length)
11594 {
11595 case 128:
11596 case 256:
11597 case 512:
11598 oappend ("DWORD PTR ");
11599 break;
11600 default:
11601 abort ();
11602 }
11603 break;
11604 case xmm_mq_mode:
11605 if (!need_vex)
11606 abort ();
11607
11608 switch (vex.length)
11609 {
11610 case 128:
11611 case 256:
11612 case 512:
11613 oappend ("QWORD PTR ");
11614 break;
11615 default:
11616 abort ();
11617 }
11618 break;
11619 case xmmdw_mode:
11620 if (!need_vex)
11621 abort ();
11622
11623 switch (vex.length)
11624 {
11625 case 128:
11626 oappend ("WORD PTR ");
11627 break;
11628 case 256:
11629 oappend ("DWORD PTR ");
11630 break;
11631 case 512:
11632 oappend ("QWORD PTR ");
11633 break;
11634 default:
11635 abort ();
11636 }
11637 break;
11638 case xmmqd_mode:
11639 if (!need_vex)
11640 abort ();
11641
11642 switch (vex.length)
11643 {
11644 case 128:
11645 oappend ("DWORD PTR ");
11646 break;
11647 case 256:
11648 oappend ("QWORD PTR ");
11649 break;
11650 case 512:
11651 oappend ("XMMWORD PTR ");
11652 break;
11653 default:
11654 abort ();
11655 }
11656 break;
11657 case ymmq_mode:
11658 if (!need_vex)
11659 abort ();
11660
11661 switch (vex.length)
11662 {
11663 case 128:
11664 oappend ("QWORD PTR ");
11665 break;
11666 case 256:
11667 oappend ("YMMWORD PTR ");
11668 break;
11669 case 512:
11670 oappend ("ZMMWORD PTR ");
11671 break;
11672 default:
11673 abort ();
11674 }
11675 break;
11676 case ymmxmm_mode:
11677 if (!need_vex)
11678 abort ();
11679
11680 switch (vex.length)
11681 {
11682 case 128:
11683 case 256:
11684 oappend ("XMMWORD PTR ");
11685 break;
11686 default:
11687 abort ();
11688 }
11689 break;
11690 case o_mode:
11691 oappend ("OWORD PTR ");
11692 break;
11693 case vex_scalar_w_dq_mode:
11694 if (!need_vex)
11695 abort ();
11696
11697 if (vex.w)
11698 oappend ("QWORD PTR ");
11699 else
11700 oappend ("DWORD PTR ");
11701 break;
11702 case vex_vsib_d_w_dq_mode:
11703 case vex_vsib_q_w_dq_mode:
11704 if (!need_vex)
11705 abort ();
11706
11707 if (!vex.evex)
11708 {
11709 if (vex.w)
11710 oappend ("QWORD PTR ");
11711 else
11712 oappend ("DWORD PTR ");
11713 }
11714 else
11715 {
11716 switch (vex.length)
11717 {
11718 case 128:
11719 oappend ("XMMWORD PTR ");
11720 break;
11721 case 256:
11722 oappend ("YMMWORD PTR ");
11723 break;
11724 case 512:
11725 oappend ("ZMMWORD PTR ");
11726 break;
11727 default:
11728 abort ();
11729 }
11730 }
11731 break;
11732 case vex_vsib_q_w_d_mode:
11733 case vex_vsib_d_w_d_mode:
11734 if (!need_vex || !vex.evex)
11735 abort ();
11736
11737 switch (vex.length)
11738 {
11739 case 128:
11740 oappend ("QWORD PTR ");
11741 break;
11742 case 256:
11743 oappend ("XMMWORD PTR ");
11744 break;
11745 case 512:
11746 oappend ("YMMWORD PTR ");
11747 break;
11748 default:
11749 abort ();
11750 }
11751
11752 break;
11753 case mask_bd_mode:
11754 if (!need_vex || vex.length != 128)
11755 abort ();
11756 if (vex.w)
11757 oappend ("DWORD PTR ");
11758 else
11759 oappend ("BYTE PTR ");
11760 break;
11761 case mask_mode:
11762 if (!need_vex)
11763 abort ();
11764 if (vex.w)
11765 oappend ("QWORD PTR ");
11766 else
11767 oappend ("WORD PTR ");
11768 break;
11769 case v_bnd_mode:
11770 case v_bndmk_mode:
11771 default:
11772 break;
11773 }
11774 }
11775
11776 static void
11777 OP_E_register (int bytemode, int sizeflag)
11778 {
11779 int reg = modrm.rm;
11780 const char **names;
11781
11782 USED_REX (REX_B);
11783 if ((rex & REX_B))
11784 reg += 8;
11785
11786 if ((sizeflag & SUFFIX_ALWAYS)
11787 && (bytemode == b_swap_mode
11788 || bytemode == bnd_swap_mode
11789 || bytemode == v_swap_mode))
11790 swap_operand ();
11791
11792 switch (bytemode)
11793 {
11794 case b_mode:
11795 case b_swap_mode:
11796 if (reg & 4)
11797 USED_REX (0);
11798 if (rex)
11799 names = names8rex;
11800 else
11801 names = names8;
11802 break;
11803 case w_mode:
11804 names = names16;
11805 break;
11806 case d_mode:
11807 case dw_mode:
11808 case db_mode:
11809 names = names32;
11810 break;
11811 case q_mode:
11812 names = names64;
11813 break;
11814 case m_mode:
11815 case v_bnd_mode:
11816 names = address_mode == mode_64bit ? names64 : names32;
11817 break;
11818 case bnd_mode:
11819 case bnd_swap_mode:
11820 if (reg > 0x3)
11821 {
11822 oappend ("(bad)");
11823 return;
11824 }
11825 names = names_bnd;
11826 break;
11827 case indir_v_mode:
11828 if (address_mode == mode_64bit && isa64 == intel64)
11829 {
11830 names = names64;
11831 break;
11832 }
11833 /* Fall through. */
11834 case stack_v_mode:
11835 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11836 {
11837 names = names64;
11838 break;
11839 }
11840 bytemode = v_mode;
11841 /* Fall through. */
11842 case v_mode:
11843 case v_swap_mode:
11844 case dq_mode:
11845 case dqb_mode:
11846 case dqd_mode:
11847 case dqw_mode:
11848 USED_REX (REX_W);
11849 if (rex & REX_W)
11850 names = names64;
11851 else if (bytemode != v_mode && bytemode != v_swap_mode)
11852 names = names32;
11853 else
11854 {
11855 if (sizeflag & DFLAG)
11856 names = names32;
11857 else
11858 names = names16;
11859 used_prefixes |= (prefixes & PREFIX_DATA);
11860 }
11861 break;
11862 case movsxd_mode:
11863 if (!(sizeflag & DFLAG) && isa64 == intel64)
11864 names = names16;
11865 else
11866 names = names32;
11867 used_prefixes |= (prefixes & PREFIX_DATA);
11868 break;
11869 case va_mode:
11870 names = (address_mode == mode_64bit
11871 ? names64 : names32);
11872 if (!(prefixes & PREFIX_ADDR))
11873 names = (address_mode == mode_16bit
11874 ? names16 : names);
11875 else
11876 {
11877 /* Remove "addr16/addr32". */
11878 all_prefixes[last_addr_prefix] = 0;
11879 names = (address_mode != mode_32bit
11880 ? names32 : names16);
11881 used_prefixes |= PREFIX_ADDR;
11882 }
11883 break;
11884 case mask_bd_mode:
11885 case mask_mode:
11886 if (reg > 0x7)
11887 {
11888 oappend ("(bad)");
11889 return;
11890 }
11891 names = names_mask;
11892 break;
11893 case 0:
11894 return;
11895 default:
11896 oappend (INTERNAL_DISASSEMBLER_ERROR);
11897 return;
11898 }
11899 oappend (names[reg]);
11900 }
11901
11902 static void
11903 OP_E_memory (int bytemode, int sizeflag)
11904 {
11905 bfd_vma disp = 0;
11906 int add = (rex & REX_B) ? 8 : 0;
11907 int riprel = 0;
11908 int shift;
11909
11910 if (vex.evex)
11911 {
11912 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
11913 if (vex.b
11914 && bytemode != x_mode
11915 && bytemode != xmmq_mode
11916 && bytemode != evex_half_bcst_xmmq_mode)
11917 {
11918 BadOp ();
11919 return;
11920 }
11921 switch (bytemode)
11922 {
11923 case dqw_mode:
11924 case dw_mode:
11925 case xmm_mw_mode:
11926 shift = 1;
11927 break;
11928 case dqb_mode:
11929 case db_mode:
11930 case xmm_mb_mode:
11931 shift = 0;
11932 break;
11933 case dq_mode:
11934 if (address_mode != mode_64bit)
11935 {
11936 case dqd_mode:
11937 case xmm_md_mode:
11938 case d_mode:
11939 case d_swap_mode:
11940 shift = 2;
11941 break;
11942 }
11943 /* fall through */
11944 case vex_scalar_w_dq_mode:
11945 case vex_vsib_d_w_dq_mode:
11946 case vex_vsib_d_w_d_mode:
11947 case vex_vsib_q_w_dq_mode:
11948 case vex_vsib_q_w_d_mode:
11949 case evex_x_gscat_mode:
11950 shift = vex.w ? 3 : 2;
11951 break;
11952 case x_mode:
11953 case evex_half_bcst_xmmq_mode:
11954 case xmmq_mode:
11955 if (vex.b)
11956 {
11957 shift = vex.w ? 3 : 2;
11958 break;
11959 }
11960 /* Fall through. */
11961 case xmmqd_mode:
11962 case xmmdw_mode:
11963 case ymmq_mode:
11964 case evex_x_nobcst_mode:
11965 case x_swap_mode:
11966 switch (vex.length)
11967 {
11968 case 128:
11969 shift = 4;
11970 break;
11971 case 256:
11972 shift = 5;
11973 break;
11974 case 512:
11975 shift = 6;
11976 break;
11977 default:
11978 abort ();
11979 }
11980 /* Make necessary corrections to shift for modes that need it. */
11981 if (bytemode == xmmq_mode
11982 || bytemode == evex_half_bcst_xmmq_mode
11983 || (bytemode == ymmq_mode && vex.length == 128))
11984 shift -= 1;
11985 else if (bytemode == xmmqd_mode)
11986 shift -= 2;
11987 else if (bytemode == xmmdw_mode)
11988 shift -= 3;
11989 break;
11990 case ymm_mode:
11991 shift = 5;
11992 break;
11993 case xmm_mode:
11994 shift = 4;
11995 break;
11996 case xmm_mq_mode:
11997 case q_mode:
11998 case q_swap_mode:
11999 shift = 3;
12000 break;
12001 case bw_unit_mode:
12002 shift = vex.w ? 1 : 0;
12003 break;
12004 default:
12005 abort ();
12006 }
12007 }
12008 else
12009 shift = 0;
12010
12011 USED_REX (REX_B);
12012 if (intel_syntax)
12013 intel_operand_size (bytemode, sizeflag);
12014 append_seg ();
12015
12016 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12017 {
12018 /* 32/64 bit address mode */
12019 int havedisp;
12020 int havesib;
12021 int havebase;
12022 int haveindex;
12023 int needindex;
12024 int needaddr32;
12025 int base, rbase;
12026 int vindex = 0;
12027 int scale = 0;
12028 int addr32flag = !((sizeflag & AFLAG)
12029 || bytemode == v_bnd_mode
12030 || bytemode == v_bndmk_mode
12031 || bytemode == bnd_mode
12032 || bytemode == bnd_swap_mode);
12033 const char **indexes64 = names64;
12034 const char **indexes32 = names32;
12035
12036 havesib = 0;
12037 havebase = 1;
12038 haveindex = 0;
12039 base = modrm.rm;
12040
12041 if (base == 4)
12042 {
12043 havesib = 1;
12044 vindex = sib.index;
12045 USED_REX (REX_X);
12046 if (rex & REX_X)
12047 vindex += 8;
12048 switch (bytemode)
12049 {
12050 case vex_vsib_d_w_dq_mode:
12051 case vex_vsib_d_w_d_mode:
12052 case vex_vsib_q_w_dq_mode:
12053 case vex_vsib_q_w_d_mode:
12054 if (!need_vex)
12055 abort ();
12056 if (vex.evex)
12057 {
12058 if (!vex.v)
12059 vindex += 16;
12060 }
12061
12062 haveindex = 1;
12063 switch (vex.length)
12064 {
12065 case 128:
12066 indexes64 = indexes32 = names_xmm;
12067 break;
12068 case 256:
12069 if (!vex.w
12070 || bytemode == vex_vsib_q_w_dq_mode
12071 || bytemode == vex_vsib_q_w_d_mode)
12072 indexes64 = indexes32 = names_ymm;
12073 else
12074 indexes64 = indexes32 = names_xmm;
12075 break;
12076 case 512:
12077 if (!vex.w
12078 || bytemode == vex_vsib_q_w_dq_mode
12079 || bytemode == vex_vsib_q_w_d_mode)
12080 indexes64 = indexes32 = names_zmm;
12081 else
12082 indexes64 = indexes32 = names_ymm;
12083 break;
12084 default:
12085 abort ();
12086 }
12087 break;
12088 default:
12089 haveindex = vindex != 4;
12090 break;
12091 }
12092 scale = sib.scale;
12093 base = sib.base;
12094 codep++;
12095 }
12096 else
12097 {
12098 /* mandatory non-vector SIB must have sib */
12099 if (bytemode == vex_sibmem_mode)
12100 {
12101 oappend ("(bad)");
12102 return;
12103 }
12104 }
12105 rbase = base + add;
12106
12107 switch (modrm.mod)
12108 {
12109 case 0:
12110 if (base == 5)
12111 {
12112 havebase = 0;
12113 if (address_mode == mode_64bit && !havesib)
12114 riprel = 1;
12115 disp = get32s ();
12116 if (riprel && bytemode == v_bndmk_mode)
12117 {
12118 oappend ("(bad)");
12119 return;
12120 }
12121 }
12122 break;
12123 case 1:
12124 FETCH_DATA (the_info, codep + 1);
12125 disp = *codep++;
12126 if ((disp & 0x80) != 0)
12127 disp -= 0x100;
12128 if (vex.evex && shift > 0)
12129 disp <<= shift;
12130 break;
12131 case 2:
12132 disp = get32s ();
12133 break;
12134 }
12135
12136 needindex = 0;
12137 needaddr32 = 0;
12138 if (havesib
12139 && !havebase
12140 && !haveindex
12141 && address_mode != mode_16bit)
12142 {
12143 if (address_mode == mode_64bit)
12144 {
12145 if (addr32flag)
12146 {
12147 /* Without base nor index registers, zero-extend the
12148 lower 32-bit displacement to 64 bits. */
12149 disp = (unsigned int) disp;
12150 needindex = 1;
12151 }
12152 needaddr32 = 1;
12153 }
12154 else
12155 {
12156 /* In 32-bit mode, we need index register to tell [offset]
12157 from [eiz*1 + offset]. */
12158 needindex = 1;
12159 }
12160 }
12161
12162 havedisp = (havebase
12163 || needindex
12164 || (havesib && (haveindex || scale != 0)));
12165
12166 if (!intel_syntax)
12167 if (modrm.mod != 0 || base == 5)
12168 {
12169 if (havedisp || riprel)
12170 print_displacement (scratchbuf, disp);
12171 else
12172 print_operand_value (scratchbuf, 1, disp);
12173 oappend (scratchbuf);
12174 if (riprel)
12175 {
12176 set_op (disp, 1);
12177 oappend (!addr32flag ? "(%rip)" : "(%eip)");
12178 }
12179 }
12180
12181 if ((havebase || haveindex || needindex || needaddr32 || riprel)
12182 && (address_mode != mode_64bit
12183 || ((bytemode != v_bnd_mode)
12184 && (bytemode != v_bndmk_mode)
12185 && (bytemode != bnd_mode)
12186 && (bytemode != bnd_swap_mode))))
12187 used_prefixes |= PREFIX_ADDR;
12188
12189 if (havedisp || (intel_syntax && riprel))
12190 {
12191 *obufp++ = open_char;
12192 if (intel_syntax && riprel)
12193 {
12194 set_op (disp, 1);
12195 oappend (!addr32flag ? "rip" : "eip");
12196 }
12197 *obufp = '\0';
12198 if (havebase)
12199 oappend (address_mode == mode_64bit && !addr32flag
12200 ? names64[rbase] : names32[rbase]);
12201 if (havesib)
12202 {
12203 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
12204 print index to tell base + index from base. */
12205 if (scale != 0
12206 || needindex
12207 || haveindex
12208 || (havebase && base != ESP_REG_NUM))
12209 {
12210 if (!intel_syntax || havebase)
12211 {
12212 *obufp++ = separator_char;
12213 *obufp = '\0';
12214 }
12215 if (haveindex)
12216 oappend (address_mode == mode_64bit && !addr32flag
12217 ? indexes64[vindex] : indexes32[vindex]);
12218 else
12219 oappend (address_mode == mode_64bit && !addr32flag
12220 ? index64 : index32);
12221
12222 *obufp++ = scale_char;
12223 *obufp = '\0';
12224 sprintf (scratchbuf, "%d", 1 << scale);
12225 oappend (scratchbuf);
12226 }
12227 }
12228 if (intel_syntax
12229 && (disp || modrm.mod != 0 || base == 5))
12230 {
12231 if (!havedisp || (bfd_signed_vma) disp >= 0)
12232 {
12233 *obufp++ = '+';
12234 *obufp = '\0';
12235 }
12236 else if (modrm.mod != 1 && disp != -disp)
12237 {
12238 *obufp++ = '-';
12239 *obufp = '\0';
12240 disp = -disp;
12241 }
12242
12243 if (havedisp)
12244 print_displacement (scratchbuf, disp);
12245 else
12246 print_operand_value (scratchbuf, 1, disp);
12247 oappend (scratchbuf);
12248 }
12249
12250 *obufp++ = close_char;
12251 *obufp = '\0';
12252 }
12253 else if (intel_syntax)
12254 {
12255 if (modrm.mod != 0 || base == 5)
12256 {
12257 if (!active_seg_prefix)
12258 {
12259 oappend (names_seg[ds_reg - es_reg]);
12260 oappend (":");
12261 }
12262 print_operand_value (scratchbuf, 1, disp);
12263 oappend (scratchbuf);
12264 }
12265 }
12266 }
12267 else if (bytemode == v_bnd_mode
12268 || bytemode == v_bndmk_mode
12269 || bytemode == bnd_mode
12270 || bytemode == bnd_swap_mode)
12271 {
12272 oappend ("(bad)");
12273 return;
12274 }
12275 else
12276 {
12277 /* 16 bit address mode */
12278 used_prefixes |= prefixes & PREFIX_ADDR;
12279 switch (modrm.mod)
12280 {
12281 case 0:
12282 if (modrm.rm == 6)
12283 {
12284 disp = get16 ();
12285 if ((disp & 0x8000) != 0)
12286 disp -= 0x10000;
12287 }
12288 break;
12289 case 1:
12290 FETCH_DATA (the_info, codep + 1);
12291 disp = *codep++;
12292 if ((disp & 0x80) != 0)
12293 disp -= 0x100;
12294 if (vex.evex && shift > 0)
12295 disp <<= shift;
12296 break;
12297 case 2:
12298 disp = get16 ();
12299 if ((disp & 0x8000) != 0)
12300 disp -= 0x10000;
12301 break;
12302 }
12303
12304 if (!intel_syntax)
12305 if (modrm.mod != 0 || modrm.rm == 6)
12306 {
12307 print_displacement (scratchbuf, disp);
12308 oappend (scratchbuf);
12309 }
12310
12311 if (modrm.mod != 0 || modrm.rm != 6)
12312 {
12313 *obufp++ = open_char;
12314 *obufp = '\0';
12315 oappend (index16[modrm.rm]);
12316 if (intel_syntax
12317 && (disp || modrm.mod != 0 || modrm.rm == 6))
12318 {
12319 if ((bfd_signed_vma) disp >= 0)
12320 {
12321 *obufp++ = '+';
12322 *obufp = '\0';
12323 }
12324 else if (modrm.mod != 1)
12325 {
12326 *obufp++ = '-';
12327 *obufp = '\0';
12328 disp = -disp;
12329 }
12330
12331 print_displacement (scratchbuf, disp);
12332 oappend (scratchbuf);
12333 }
12334
12335 *obufp++ = close_char;
12336 *obufp = '\0';
12337 }
12338 else if (intel_syntax)
12339 {
12340 if (!active_seg_prefix)
12341 {
12342 oappend (names_seg[ds_reg - es_reg]);
12343 oappend (":");
12344 }
12345 print_operand_value (scratchbuf, 1, disp & 0xffff);
12346 oappend (scratchbuf);
12347 }
12348 }
12349 if (vex.evex && vex.b
12350 && (bytemode == x_mode
12351 || bytemode == xmmq_mode
12352 || bytemode == evex_half_bcst_xmmq_mode))
12353 {
12354 if (vex.w
12355 || bytemode == xmmq_mode
12356 || bytemode == evex_half_bcst_xmmq_mode)
12357 {
12358 switch (vex.length)
12359 {
12360 case 128:
12361 oappend ("{1to2}");
12362 break;
12363 case 256:
12364 oappend ("{1to4}");
12365 break;
12366 case 512:
12367 oappend ("{1to8}");
12368 break;
12369 default:
12370 abort ();
12371 }
12372 }
12373 else
12374 {
12375 switch (vex.length)
12376 {
12377 case 128:
12378 oappend ("{1to4}");
12379 break;
12380 case 256:
12381 oappend ("{1to8}");
12382 break;
12383 case 512:
12384 oappend ("{1to16}");
12385 break;
12386 default:
12387 abort ();
12388 }
12389 }
12390 }
12391 }
12392
12393 static void
12394 OP_E (int bytemode, int sizeflag)
12395 {
12396 /* Skip mod/rm byte. */
12397 MODRM_CHECK;
12398 codep++;
12399
12400 if (modrm.mod == 3)
12401 OP_E_register (bytemode, sizeflag);
12402 else
12403 OP_E_memory (bytemode, sizeflag);
12404 }
12405
12406 static void
12407 OP_G (int bytemode, int sizeflag)
12408 {
12409 int add = 0;
12410 const char **names;
12411 USED_REX (REX_R);
12412 if (rex & REX_R)
12413 add += 8;
12414 switch (bytemode)
12415 {
12416 case b_mode:
12417 if (modrm.reg & 4)
12418 USED_REX (0);
12419 if (rex)
12420 oappend (names8rex[modrm.reg + add]);
12421 else
12422 oappend (names8[modrm.reg + add]);
12423 break;
12424 case w_mode:
12425 oappend (names16[modrm.reg + add]);
12426 break;
12427 case d_mode:
12428 case db_mode:
12429 case dw_mode:
12430 oappend (names32[modrm.reg + add]);
12431 break;
12432 case q_mode:
12433 oappend (names64[modrm.reg + add]);
12434 break;
12435 case bnd_mode:
12436 if (modrm.reg > 0x3)
12437 {
12438 oappend ("(bad)");
12439 return;
12440 }
12441 oappend (names_bnd[modrm.reg]);
12442 break;
12443 case v_mode:
12444 case dq_mode:
12445 case dqb_mode:
12446 case dqd_mode:
12447 case dqw_mode:
12448 case movsxd_mode:
12449 USED_REX (REX_W);
12450 if (rex & REX_W)
12451 oappend (names64[modrm.reg + add]);
12452 else if (bytemode != v_mode && bytemode != movsxd_mode)
12453 oappend (names32[modrm.reg + add]);
12454 else
12455 {
12456 if (sizeflag & DFLAG)
12457 oappend (names32[modrm.reg + add]);
12458 else
12459 oappend (names16[modrm.reg + add]);
12460 used_prefixes |= (prefixes & PREFIX_DATA);
12461 }
12462 break;
12463 case va_mode:
12464 names = (address_mode == mode_64bit
12465 ? names64 : names32);
12466 if (!(prefixes & PREFIX_ADDR))
12467 {
12468 if (address_mode == mode_16bit)
12469 names = names16;
12470 }
12471 else
12472 {
12473 /* Remove "addr16/addr32". */
12474 all_prefixes[last_addr_prefix] = 0;
12475 names = (address_mode != mode_32bit
12476 ? names32 : names16);
12477 used_prefixes |= PREFIX_ADDR;
12478 }
12479 oappend (names[modrm.reg + add]);
12480 break;
12481 case m_mode:
12482 if (address_mode == mode_64bit)
12483 oappend (names64[modrm.reg + add]);
12484 else
12485 oappend (names32[modrm.reg + add]);
12486 break;
12487 case mask_bd_mode:
12488 case mask_mode:
12489 if ((modrm.reg + add) > 0x7)
12490 {
12491 oappend ("(bad)");
12492 return;
12493 }
12494 oappend (names_mask[modrm.reg + add]);
12495 break;
12496 default:
12497 oappend (INTERNAL_DISASSEMBLER_ERROR);
12498 break;
12499 }
12500 }
12501
12502 static bfd_vma
12503 get64 (void)
12504 {
12505 bfd_vma x;
12506 #ifdef BFD64
12507 unsigned int a;
12508 unsigned int b;
12509
12510 FETCH_DATA (the_info, codep + 8);
12511 a = *codep++ & 0xff;
12512 a |= (*codep++ & 0xff) << 8;
12513 a |= (*codep++ & 0xff) << 16;
12514 a |= (*codep++ & 0xffu) << 24;
12515 b = *codep++ & 0xff;
12516 b |= (*codep++ & 0xff) << 8;
12517 b |= (*codep++ & 0xff) << 16;
12518 b |= (*codep++ & 0xffu) << 24;
12519 x = a + ((bfd_vma) b << 32);
12520 #else
12521 abort ();
12522 x = 0;
12523 #endif
12524 return x;
12525 }
12526
12527 static bfd_signed_vma
12528 get32 (void)
12529 {
12530 bfd_vma x = 0;
12531
12532 FETCH_DATA (the_info, codep + 4);
12533 x = *codep++ & (bfd_vma) 0xff;
12534 x |= (*codep++ & (bfd_vma) 0xff) << 8;
12535 x |= (*codep++ & (bfd_vma) 0xff) << 16;
12536 x |= (*codep++ & (bfd_vma) 0xff) << 24;
12537 return x;
12538 }
12539
12540 static bfd_signed_vma
12541 get32s (void)
12542 {
12543 bfd_vma x = 0;
12544
12545 FETCH_DATA (the_info, codep + 4);
12546 x = *codep++ & (bfd_vma) 0xff;
12547 x |= (*codep++ & (bfd_vma) 0xff) << 8;
12548 x |= (*codep++ & (bfd_vma) 0xff) << 16;
12549 x |= (*codep++ & (bfd_vma) 0xff) << 24;
12550
12551 x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12552
12553 return x;
12554 }
12555
12556 static int
12557 get16 (void)
12558 {
12559 int x = 0;
12560
12561 FETCH_DATA (the_info, codep + 2);
12562 x = *codep++ & 0xff;
12563 x |= (*codep++ & 0xff) << 8;
12564 return x;
12565 }
12566
12567 static void
12568 set_op (bfd_vma op, int riprel)
12569 {
12570 op_index[op_ad] = op_ad;
12571 if (address_mode == mode_64bit)
12572 {
12573 op_address[op_ad] = op;
12574 op_riprel[op_ad] = riprel;
12575 }
12576 else
12577 {
12578 /* Mask to get a 32-bit address. */
12579 op_address[op_ad] = op & 0xffffffff;
12580 op_riprel[op_ad] = riprel & 0xffffffff;
12581 }
12582 }
12583
12584 static void
12585 OP_REG (int code, int sizeflag)
12586 {
12587 const char *s;
12588 int add;
12589
12590 switch (code)
12591 {
12592 case es_reg: case ss_reg: case cs_reg:
12593 case ds_reg: case fs_reg: case gs_reg:
12594 oappend (names_seg[code - es_reg]);
12595 return;
12596 }
12597
12598 USED_REX (REX_B);
12599 if (rex & REX_B)
12600 add = 8;
12601 else
12602 add = 0;
12603
12604 switch (code)
12605 {
12606 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12607 case sp_reg: case bp_reg: case si_reg: case di_reg:
12608 s = names16[code - ax_reg + add];
12609 break;
12610 case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12611 USED_REX (0);
12612 /* Fall through. */
12613 case al_reg: case cl_reg: case dl_reg: case bl_reg:
12614 if (rex)
12615 s = names8rex[code - al_reg + add];
12616 else
12617 s = names8[code - al_reg];
12618 break;
12619 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12620 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12621 if (address_mode == mode_64bit
12622 && ((sizeflag & DFLAG) || (rex & REX_W)))
12623 {
12624 s = names64[code - rAX_reg + add];
12625 break;
12626 }
12627 code += eAX_reg - rAX_reg;
12628 /* Fall through. */
12629 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12630 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12631 USED_REX (REX_W);
12632 if (rex & REX_W)
12633 s = names64[code - eAX_reg + add];
12634 else
12635 {
12636 if (sizeflag & DFLAG)
12637 s = names32[code - eAX_reg + add];
12638 else
12639 s = names16[code - eAX_reg + add];
12640 used_prefixes |= (prefixes & PREFIX_DATA);
12641 }
12642 break;
12643 default:
12644 s = INTERNAL_DISASSEMBLER_ERROR;
12645 break;
12646 }
12647 oappend (s);
12648 }
12649
12650 static void
12651 OP_IMREG (int code, int sizeflag)
12652 {
12653 const char *s;
12654
12655 switch (code)
12656 {
12657 case indir_dx_reg:
12658 if (intel_syntax)
12659 s = "dx";
12660 else
12661 s = "(%dx)";
12662 break;
12663 case al_reg: case cl_reg:
12664 s = names8[code - al_reg];
12665 break;
12666 case eAX_reg:
12667 USED_REX (REX_W);
12668 if (rex & REX_W)
12669 {
12670 s = *names64;
12671 break;
12672 }
12673 /* Fall through. */
12674 case z_mode_ax_reg:
12675 if ((rex & REX_W) || (sizeflag & DFLAG))
12676 s = *names32;
12677 else
12678 s = *names16;
12679 if (!(rex & REX_W))
12680 used_prefixes |= (prefixes & PREFIX_DATA);
12681 break;
12682 default:
12683 s = INTERNAL_DISASSEMBLER_ERROR;
12684 break;
12685 }
12686 oappend (s);
12687 }
12688
12689 static void
12690 OP_I (int bytemode, int sizeflag)
12691 {
12692 bfd_signed_vma op;
12693 bfd_signed_vma mask = -1;
12694
12695 switch (bytemode)
12696 {
12697 case b_mode:
12698 FETCH_DATA (the_info, codep + 1);
12699 op = *codep++;
12700 mask = 0xff;
12701 break;
12702 case v_mode:
12703 USED_REX (REX_W);
12704 if (rex & REX_W)
12705 op = get32s ();
12706 else
12707 {
12708 if (sizeflag & DFLAG)
12709 {
12710 op = get32 ();
12711 mask = 0xffffffff;
12712 }
12713 else
12714 {
12715 op = get16 ();
12716 mask = 0xfffff;
12717 }
12718 used_prefixes |= (prefixes & PREFIX_DATA);
12719 }
12720 break;
12721 case d_mode:
12722 mask = 0xffffffff;
12723 op = get32 ();
12724 break;
12725 case w_mode:
12726 mask = 0xfffff;
12727 op = get16 ();
12728 break;
12729 case const_1_mode:
12730 if (intel_syntax)
12731 oappend ("1");
12732 return;
12733 default:
12734 oappend (INTERNAL_DISASSEMBLER_ERROR);
12735 return;
12736 }
12737
12738 op &= mask;
12739 scratchbuf[0] = '$';
12740 print_operand_value (scratchbuf + 1, 1, op);
12741 oappend_maybe_intel (scratchbuf);
12742 scratchbuf[0] = '\0';
12743 }
12744
12745 static void
12746 OP_I64 (int bytemode, int sizeflag)
12747 {
12748 if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
12749 {
12750 OP_I (bytemode, sizeflag);
12751 return;
12752 }
12753
12754 USED_REX (REX_W);
12755
12756 scratchbuf[0] = '$';
12757 print_operand_value (scratchbuf + 1, 1, get64 ());
12758 oappend_maybe_intel (scratchbuf);
12759 scratchbuf[0] = '\0';
12760 }
12761
12762 static void
12763 OP_sI (int bytemode, int sizeflag)
12764 {
12765 bfd_signed_vma op;
12766
12767 switch (bytemode)
12768 {
12769 case b_mode:
12770 case b_T_mode:
12771 FETCH_DATA (the_info, codep + 1);
12772 op = *codep++;
12773 if ((op & 0x80) != 0)
12774 op -= 0x100;
12775 if (bytemode == b_T_mode)
12776 {
12777 if (address_mode != mode_64bit
12778 || !((sizeflag & DFLAG) || (rex & REX_W)))
12779 {
12780 /* The operand-size prefix is overridden by a REX prefix. */
12781 if ((sizeflag & DFLAG) || (rex & REX_W))
12782 op &= 0xffffffff;
12783 else
12784 op &= 0xffff;
12785 }
12786 }
12787 else
12788 {
12789 if (!(rex & REX_W))
12790 {
12791 if (sizeflag & DFLAG)
12792 op &= 0xffffffff;
12793 else
12794 op &= 0xffff;
12795 }
12796 }
12797 break;
12798 case v_mode:
12799 /* The operand-size prefix is overridden by a REX prefix. */
12800 if ((sizeflag & DFLAG) || (rex & REX_W))
12801 op = get32s ();
12802 else
12803 op = get16 ();
12804 break;
12805 default:
12806 oappend (INTERNAL_DISASSEMBLER_ERROR);
12807 return;
12808 }
12809
12810 scratchbuf[0] = '$';
12811 print_operand_value (scratchbuf + 1, 1, op);
12812 oappend_maybe_intel (scratchbuf);
12813 }
12814
12815 static void
12816 OP_J (int bytemode, int sizeflag)
12817 {
12818 bfd_vma disp;
12819 bfd_vma mask = -1;
12820 bfd_vma segment = 0;
12821
12822 switch (bytemode)
12823 {
12824 case b_mode:
12825 FETCH_DATA (the_info, codep + 1);
12826 disp = *codep++;
12827 if ((disp & 0x80) != 0)
12828 disp -= 0x100;
12829 break;
12830 case v_mode:
12831 case dqw_mode:
12832 if ((sizeflag & DFLAG)
12833 || (address_mode == mode_64bit
12834 && ((isa64 == intel64 && bytemode != dqw_mode)
12835 || (rex & REX_W))))
12836 disp = get32s ();
12837 else
12838 {
12839 disp = get16 ();
12840 if ((disp & 0x8000) != 0)
12841 disp -= 0x10000;
12842 /* In 16bit mode, address is wrapped around at 64k within
12843 the same segment. Otherwise, a data16 prefix on a jump
12844 instruction means that the pc is masked to 16 bits after
12845 the displacement is added! */
12846 mask = 0xffff;
12847 if ((prefixes & PREFIX_DATA) == 0)
12848 segment = ((start_pc + (codep - start_codep))
12849 & ~((bfd_vma) 0xffff));
12850 }
12851 if (address_mode != mode_64bit
12852 || (isa64 != intel64 && !(rex & REX_W)))
12853 used_prefixes |= (prefixes & PREFIX_DATA);
12854 break;
12855 default:
12856 oappend (INTERNAL_DISASSEMBLER_ERROR);
12857 return;
12858 }
12859 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
12860 set_op (disp, 0);
12861 print_operand_value (scratchbuf, 1, disp);
12862 oappend (scratchbuf);
12863 }
12864
12865 static void
12866 OP_SEG (int bytemode, int sizeflag)
12867 {
12868 if (bytemode == w_mode)
12869 oappend (names_seg[modrm.reg]);
12870 else
12871 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12872 }
12873
12874 static void
12875 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12876 {
12877 int seg, offset;
12878
12879 if (sizeflag & DFLAG)
12880 {
12881 offset = get32 ();
12882 seg = get16 ();
12883 }
12884 else
12885 {
12886 offset = get16 ();
12887 seg = get16 ();
12888 }
12889 used_prefixes |= (prefixes & PREFIX_DATA);
12890 if (intel_syntax)
12891 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12892 else
12893 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12894 oappend (scratchbuf);
12895 }
12896
12897 static void
12898 OP_OFF (int bytemode, int sizeflag)
12899 {
12900 bfd_vma off;
12901
12902 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12903 intel_operand_size (bytemode, sizeflag);
12904 append_seg ();
12905
12906 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12907 off = get32 ();
12908 else
12909 off = get16 ();
12910
12911 if (intel_syntax)
12912 {
12913 if (!active_seg_prefix)
12914 {
12915 oappend (names_seg[ds_reg - es_reg]);
12916 oappend (":");
12917 }
12918 }
12919 print_operand_value (scratchbuf, 1, off);
12920 oappend (scratchbuf);
12921 }
12922
12923 static void
12924 OP_OFF64 (int bytemode, int sizeflag)
12925 {
12926 bfd_vma off;
12927
12928 if (address_mode != mode_64bit
12929 || (prefixes & PREFIX_ADDR))
12930 {
12931 OP_OFF (bytemode, sizeflag);
12932 return;
12933 }
12934
12935 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12936 intel_operand_size (bytemode, sizeflag);
12937 append_seg ();
12938
12939 off = get64 ();
12940
12941 if (intel_syntax)
12942 {
12943 if (!active_seg_prefix)
12944 {
12945 oappend (names_seg[ds_reg - es_reg]);
12946 oappend (":");
12947 }
12948 }
12949 print_operand_value (scratchbuf, 1, off);
12950 oappend (scratchbuf);
12951 }
12952
12953 static void
12954 ptr_reg (int code, int sizeflag)
12955 {
12956 const char *s;
12957
12958 *obufp++ = open_char;
12959 used_prefixes |= (prefixes & PREFIX_ADDR);
12960 if (address_mode == mode_64bit)
12961 {
12962 if (!(sizeflag & AFLAG))
12963 s = names32[code - eAX_reg];
12964 else
12965 s = names64[code - eAX_reg];
12966 }
12967 else if (sizeflag & AFLAG)
12968 s = names32[code - eAX_reg];
12969 else
12970 s = names16[code - eAX_reg];
12971 oappend (s);
12972 *obufp++ = close_char;
12973 *obufp = 0;
12974 }
12975
12976 static void
12977 OP_ESreg (int code, int sizeflag)
12978 {
12979 if (intel_syntax)
12980 {
12981 switch (codep[-1])
12982 {
12983 case 0x6d: /* insw/insl */
12984 intel_operand_size (z_mode, sizeflag);
12985 break;
12986 case 0xa5: /* movsw/movsl/movsq */
12987 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12988 case 0xab: /* stosw/stosl */
12989 case 0xaf: /* scasw/scasl */
12990 intel_operand_size (v_mode, sizeflag);
12991 break;
12992 default:
12993 intel_operand_size (b_mode, sizeflag);
12994 }
12995 }
12996 oappend_maybe_intel ("%es:");
12997 ptr_reg (code, sizeflag);
12998 }
12999
13000 static void
13001 OP_DSreg (int code, int sizeflag)
13002 {
13003 if (intel_syntax)
13004 {
13005 switch (codep[-1])
13006 {
13007 case 0x6f: /* outsw/outsl */
13008 intel_operand_size (z_mode, sizeflag);
13009 break;
13010 case 0xa5: /* movsw/movsl/movsq */
13011 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13012 case 0xad: /* lodsw/lodsl/lodsq */
13013 intel_operand_size (v_mode, sizeflag);
13014 break;
13015 default:
13016 intel_operand_size (b_mode, sizeflag);
13017 }
13018 }
13019 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
13020 default segment register DS is printed. */
13021 if (!active_seg_prefix)
13022 active_seg_prefix = PREFIX_DS;
13023 append_seg ();
13024 ptr_reg (code, sizeflag);
13025 }
13026
13027 static void
13028 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13029 {
13030 int add;
13031 if (rex & REX_R)
13032 {
13033 USED_REX (REX_R);
13034 add = 8;
13035 }
13036 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13037 {
13038 all_prefixes[last_lock_prefix] = 0;
13039 used_prefixes |= PREFIX_LOCK;
13040 add = 8;
13041 }
13042 else
13043 add = 0;
13044 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13045 oappend_maybe_intel (scratchbuf);
13046 }
13047
13048 static void
13049 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13050 {
13051 int add;
13052 USED_REX (REX_R);
13053 if (rex & REX_R)
13054 add = 8;
13055 else
13056 add = 0;
13057 if (intel_syntax)
13058 sprintf (scratchbuf, "dr%d", modrm.reg + add);
13059 else
13060 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13061 oappend (scratchbuf);
13062 }
13063
13064 static void
13065 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13066 {
13067 sprintf (scratchbuf, "%%tr%d", modrm.reg);
13068 oappend_maybe_intel (scratchbuf);
13069 }
13070
13071 static void
13072 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13073 {
13074 int reg = modrm.reg;
13075 const char **names;
13076
13077 used_prefixes |= (prefixes & PREFIX_DATA);
13078 if (prefixes & PREFIX_DATA)
13079 {
13080 names = names_xmm;
13081 USED_REX (REX_R);
13082 if (rex & REX_R)
13083 reg += 8;
13084 }
13085 else
13086 names = names_mm;
13087 oappend (names[reg]);
13088 }
13089
13090 static void
13091 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13092 {
13093 int reg = modrm.reg;
13094 const char **names;
13095
13096 USED_REX (REX_R);
13097 if (rex & REX_R)
13098 reg += 8;
13099 if (vex.evex)
13100 {
13101 if (!vex.r)
13102 reg += 16;
13103 }
13104
13105 if (need_vex
13106 && bytemode != xmm_mode
13107 && bytemode != xmmq_mode
13108 && bytemode != evex_half_bcst_xmmq_mode
13109 && bytemode != ymm_mode
13110 && bytemode != tmm_mode
13111 && bytemode != scalar_mode)
13112 {
13113 switch (vex.length)
13114 {
13115 case 128:
13116 names = names_xmm;
13117 break;
13118 case 256:
13119 if (vex.w
13120 || (bytemode != vex_vsib_q_w_dq_mode
13121 && bytemode != vex_vsib_q_w_d_mode))
13122 names = names_ymm;
13123 else
13124 names = names_xmm;
13125 break;
13126 case 512:
13127 names = names_zmm;
13128 break;
13129 default:
13130 abort ();
13131 }
13132 }
13133 else if (bytemode == xmmq_mode
13134 || bytemode == evex_half_bcst_xmmq_mode)
13135 {
13136 switch (vex.length)
13137 {
13138 case 128:
13139 case 256:
13140 names = names_xmm;
13141 break;
13142 case 512:
13143 names = names_ymm;
13144 break;
13145 default:
13146 abort ();
13147 }
13148 }
13149 else if (bytemode == tmm_mode)
13150 {
13151 modrm.reg = reg;
13152 if (reg >= 8)
13153 {
13154 oappend ("(bad)");
13155 return;
13156 }
13157 names = names_tmm;
13158 }
13159 else if (bytemode == ymm_mode)
13160 names = names_ymm;
13161 else
13162 names = names_xmm;
13163 oappend (names[reg]);
13164 }
13165
13166 static void
13167 OP_EM (int bytemode, int sizeflag)
13168 {
13169 int reg;
13170 const char **names;
13171
13172 if (modrm.mod != 3)
13173 {
13174 if (intel_syntax
13175 && (bytemode == v_mode || bytemode == v_swap_mode))
13176 {
13177 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13178 used_prefixes |= (prefixes & PREFIX_DATA);
13179 }
13180 OP_E (bytemode, sizeflag);
13181 return;
13182 }
13183
13184 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13185 swap_operand ();
13186
13187 /* Skip mod/rm byte. */
13188 MODRM_CHECK;
13189 codep++;
13190 used_prefixes |= (prefixes & PREFIX_DATA);
13191 reg = modrm.rm;
13192 if (prefixes & PREFIX_DATA)
13193 {
13194 names = names_xmm;
13195 USED_REX (REX_B);
13196 if (rex & REX_B)
13197 reg += 8;
13198 }
13199 else
13200 names = names_mm;
13201 oappend (names[reg]);
13202 }
13203
13204 /* cvt* are the only instructions in sse2 which have
13205 both SSE and MMX operands and also have 0x66 prefix
13206 in their opcode. 0x66 was originally used to differentiate
13207 between SSE and MMX instruction(operands). So we have to handle the
13208 cvt* separately using OP_EMC and OP_MXC */
13209 static void
13210 OP_EMC (int bytemode, int sizeflag)
13211 {
13212 if (modrm.mod != 3)
13213 {
13214 if (intel_syntax && bytemode == v_mode)
13215 {
13216 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13217 used_prefixes |= (prefixes & PREFIX_DATA);
13218 }
13219 OP_E (bytemode, sizeflag);
13220 return;
13221 }
13222
13223 /* Skip mod/rm byte. */
13224 MODRM_CHECK;
13225 codep++;
13226 used_prefixes |= (prefixes & PREFIX_DATA);
13227 oappend (names_mm[modrm.rm]);
13228 }
13229
13230 static void
13231 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13232 {
13233 used_prefixes |= (prefixes & PREFIX_DATA);
13234 oappend (names_mm[modrm.reg]);
13235 }
13236
13237 static void
13238 OP_EX (int bytemode, int sizeflag)
13239 {
13240 int reg;
13241 const char **names;
13242
13243 /* Skip mod/rm byte. */
13244 MODRM_CHECK;
13245 codep++;
13246
13247 if (modrm.mod != 3)
13248 {
13249 OP_E_memory (bytemode, sizeflag);
13250 return;
13251 }
13252
13253 reg = modrm.rm;
13254 USED_REX (REX_B);
13255 if (rex & REX_B)
13256 reg += 8;
13257 if (vex.evex)
13258 {
13259 USED_REX (REX_X);
13260 if ((rex & REX_X))
13261 reg += 16;
13262 }
13263
13264 if ((sizeflag & SUFFIX_ALWAYS)
13265 && (bytemode == x_swap_mode
13266 || bytemode == d_swap_mode
13267 || bytemode == q_swap_mode))
13268 swap_operand ();
13269
13270 if (need_vex
13271 && bytemode != xmm_mode
13272 && bytemode != xmmdw_mode
13273 && bytemode != xmmqd_mode
13274 && bytemode != xmm_mb_mode
13275 && bytemode != xmm_mw_mode
13276 && bytemode != xmm_md_mode
13277 && bytemode != xmm_mq_mode
13278 && bytemode != xmmq_mode
13279 && bytemode != evex_half_bcst_xmmq_mode
13280 && bytemode != ymm_mode
13281 && bytemode != tmm_mode
13282 && bytemode != vex_scalar_w_dq_mode)
13283 {
13284 switch (vex.length)
13285 {
13286 case 128:
13287 names = names_xmm;
13288 break;
13289 case 256:
13290 names = names_ymm;
13291 break;
13292 case 512:
13293 names = names_zmm;
13294 break;
13295 default:
13296 abort ();
13297 }
13298 }
13299 else if (bytemode == xmmq_mode
13300 || bytemode == evex_half_bcst_xmmq_mode)
13301 {
13302 switch (vex.length)
13303 {
13304 case 128:
13305 case 256:
13306 names = names_xmm;
13307 break;
13308 case 512:
13309 names = names_ymm;
13310 break;
13311 default:
13312 abort ();
13313 }
13314 }
13315 else if (bytemode == tmm_mode)
13316 {
13317 modrm.rm = reg;
13318 if (reg >= 8)
13319 {
13320 oappend ("(bad)");
13321 return;
13322 }
13323 names = names_tmm;
13324 }
13325 else if (bytemode == ymm_mode)
13326 names = names_ymm;
13327 else
13328 names = names_xmm;
13329 oappend (names[reg]);
13330 }
13331
13332 static void
13333 OP_MS (int bytemode, int sizeflag)
13334 {
13335 if (modrm.mod == 3)
13336 OP_EM (bytemode, sizeflag);
13337 else
13338 BadOp ();
13339 }
13340
13341 static void
13342 OP_XS (int bytemode, int sizeflag)
13343 {
13344 if (modrm.mod == 3)
13345 OP_EX (bytemode, sizeflag);
13346 else
13347 BadOp ();
13348 }
13349
13350 static void
13351 OP_M (int bytemode, int sizeflag)
13352 {
13353 if (modrm.mod == 3)
13354 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13355 BadOp ();
13356 else
13357 OP_E (bytemode, sizeflag);
13358 }
13359
13360 static void
13361 OP_0f07 (int bytemode, int sizeflag)
13362 {
13363 if (modrm.mod != 3 || modrm.rm != 0)
13364 BadOp ();
13365 else
13366 OP_E (bytemode, sizeflag);
13367 }
13368
13369 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13370 32bit mode and "xchg %rax,%rax" in 64bit mode. */
13371
13372 static void
13373 NOP_Fixup1 (int bytemode, int sizeflag)
13374 {
13375 if ((prefixes & PREFIX_DATA) != 0
13376 || (rex != 0
13377 && rex != 0x48
13378 && address_mode == mode_64bit))
13379 OP_REG (bytemode, sizeflag);
13380 else
13381 strcpy (obuf, "nop");
13382 }
13383
13384 static void
13385 NOP_Fixup2 (int bytemode, int sizeflag)
13386 {
13387 if ((prefixes & PREFIX_DATA) != 0
13388 || (rex != 0
13389 && rex != 0x48
13390 && address_mode == mode_64bit))
13391 OP_IMREG (bytemode, sizeflag);
13392 }
13393
13394 static const char *const Suffix3DNow[] = {
13395 /* 00 */ NULL, NULL, NULL, NULL,
13396 /* 04 */ NULL, NULL, NULL, NULL,
13397 /* 08 */ NULL, NULL, NULL, NULL,
13398 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
13399 /* 10 */ NULL, NULL, NULL, NULL,
13400 /* 14 */ NULL, NULL, NULL, NULL,
13401 /* 18 */ NULL, NULL, NULL, NULL,
13402 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
13403 /* 20 */ NULL, NULL, NULL, NULL,
13404 /* 24 */ NULL, NULL, NULL, NULL,
13405 /* 28 */ NULL, NULL, NULL, NULL,
13406 /* 2C */ NULL, NULL, NULL, NULL,
13407 /* 30 */ NULL, NULL, NULL, NULL,
13408 /* 34 */ NULL, NULL, NULL, NULL,
13409 /* 38 */ NULL, NULL, NULL, NULL,
13410 /* 3C */ NULL, NULL, NULL, NULL,
13411 /* 40 */ NULL, NULL, NULL, NULL,
13412 /* 44 */ NULL, NULL, NULL, NULL,
13413 /* 48 */ NULL, NULL, NULL, NULL,
13414 /* 4C */ NULL, NULL, NULL, NULL,
13415 /* 50 */ NULL, NULL, NULL, NULL,
13416 /* 54 */ NULL, NULL, NULL, NULL,
13417 /* 58 */ NULL, NULL, NULL, NULL,
13418 /* 5C */ NULL, NULL, NULL, NULL,
13419 /* 60 */ NULL, NULL, NULL, NULL,
13420 /* 64 */ NULL, NULL, NULL, NULL,
13421 /* 68 */ NULL, NULL, NULL, NULL,
13422 /* 6C */ NULL, NULL, NULL, NULL,
13423 /* 70 */ NULL, NULL, NULL, NULL,
13424 /* 74 */ NULL, NULL, NULL, NULL,
13425 /* 78 */ NULL, NULL, NULL, NULL,
13426 /* 7C */ NULL, NULL, NULL, NULL,
13427 /* 80 */ NULL, NULL, NULL, NULL,
13428 /* 84 */ NULL, NULL, NULL, NULL,
13429 /* 88 */ NULL, NULL, "pfnacc", NULL,
13430 /* 8C */ NULL, NULL, "pfpnacc", NULL,
13431 /* 90 */ "pfcmpge", NULL, NULL, NULL,
13432 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
13433 /* 98 */ NULL, NULL, "pfsub", NULL,
13434 /* 9C */ NULL, NULL, "pfadd", NULL,
13435 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
13436 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
13437 /* A8 */ NULL, NULL, "pfsubr", NULL,
13438 /* AC */ NULL, NULL, "pfacc", NULL,
13439 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
13440 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
13441 /* B8 */ NULL, NULL, NULL, "pswapd",
13442 /* BC */ NULL, NULL, NULL, "pavgusb",
13443 /* C0 */ NULL, NULL, NULL, NULL,
13444 /* C4 */ NULL, NULL, NULL, NULL,
13445 /* C8 */ NULL, NULL, NULL, NULL,
13446 /* CC */ NULL, NULL, NULL, NULL,
13447 /* D0 */ NULL, NULL, NULL, NULL,
13448 /* D4 */ NULL, NULL, NULL, NULL,
13449 /* D8 */ NULL, NULL, NULL, NULL,
13450 /* DC */ NULL, NULL, NULL, NULL,
13451 /* E0 */ NULL, NULL, NULL, NULL,
13452 /* E4 */ NULL, NULL, NULL, NULL,
13453 /* E8 */ NULL, NULL, NULL, NULL,
13454 /* EC */ NULL, NULL, NULL, NULL,
13455 /* F0 */ NULL, NULL, NULL, NULL,
13456 /* F4 */ NULL, NULL, NULL, NULL,
13457 /* F8 */ NULL, NULL, NULL, NULL,
13458 /* FC */ NULL, NULL, NULL, NULL,
13459 };
13460
13461 static void
13462 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13463 {
13464 const char *mnemonic;
13465
13466 FETCH_DATA (the_info, codep + 1);
13467 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13468 place where an 8-bit immediate would normally go. ie. the last
13469 byte of the instruction. */
13470 obufp = mnemonicendp;
13471 mnemonic = Suffix3DNow[*codep++ & 0xff];
13472 if (mnemonic)
13473 oappend (mnemonic);
13474 else
13475 {
13476 /* Since a variable sized modrm/sib chunk is between the start
13477 of the opcode (0x0f0f) and the opcode suffix, we need to do
13478 all the modrm processing first, and don't know until now that
13479 we have a bad opcode. This necessitates some cleaning up. */
13480 op_out[0][0] = '\0';
13481 op_out[1][0] = '\0';
13482 BadOp ();
13483 }
13484 mnemonicendp = obufp;
13485 }
13486
13487 static const struct op simd_cmp_op[] =
13488 {
13489 { STRING_COMMA_LEN ("eq") },
13490 { STRING_COMMA_LEN ("lt") },
13491 { STRING_COMMA_LEN ("le") },
13492 { STRING_COMMA_LEN ("unord") },
13493 { STRING_COMMA_LEN ("neq") },
13494 { STRING_COMMA_LEN ("nlt") },
13495 { STRING_COMMA_LEN ("nle") },
13496 { STRING_COMMA_LEN ("ord") }
13497 };
13498
13499 static const struct op vex_cmp_op[] =
13500 {
13501 { STRING_COMMA_LEN ("eq_uq") },
13502 { STRING_COMMA_LEN ("nge") },
13503 { STRING_COMMA_LEN ("ngt") },
13504 { STRING_COMMA_LEN ("false") },
13505 { STRING_COMMA_LEN ("neq_oq") },
13506 { STRING_COMMA_LEN ("ge") },
13507 { STRING_COMMA_LEN ("gt") },
13508 { STRING_COMMA_LEN ("true") },
13509 { STRING_COMMA_LEN ("eq_os") },
13510 { STRING_COMMA_LEN ("lt_oq") },
13511 { STRING_COMMA_LEN ("le_oq") },
13512 { STRING_COMMA_LEN ("unord_s") },
13513 { STRING_COMMA_LEN ("neq_us") },
13514 { STRING_COMMA_LEN ("nlt_uq") },
13515 { STRING_COMMA_LEN ("nle_uq") },
13516 { STRING_COMMA_LEN ("ord_s") },
13517 { STRING_COMMA_LEN ("eq_us") },
13518 { STRING_COMMA_LEN ("nge_uq") },
13519 { STRING_COMMA_LEN ("ngt_uq") },
13520 { STRING_COMMA_LEN ("false_os") },
13521 { STRING_COMMA_LEN ("neq_os") },
13522 { STRING_COMMA_LEN ("ge_oq") },
13523 { STRING_COMMA_LEN ("gt_oq") },
13524 { STRING_COMMA_LEN ("true_us") },
13525 };
13526
13527 static void
13528 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13529 {
13530 unsigned int cmp_type;
13531
13532 FETCH_DATA (the_info, codep + 1);
13533 cmp_type = *codep++ & 0xff;
13534 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13535 {
13536 char suffix [3];
13537 char *p = mnemonicendp - 2;
13538 suffix[0] = p[0];
13539 suffix[1] = p[1];
13540 suffix[2] = '\0';
13541 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13542 mnemonicendp += simd_cmp_op[cmp_type].len;
13543 }
13544 else if (need_vex
13545 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13546 {
13547 char suffix [3];
13548 char *p = mnemonicendp - 2;
13549 suffix[0] = p[0];
13550 suffix[1] = p[1];
13551 suffix[2] = '\0';
13552 cmp_type -= ARRAY_SIZE (simd_cmp_op);
13553 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13554 mnemonicendp += vex_cmp_op[cmp_type].len;
13555 }
13556 else
13557 {
13558 /* We have a reserved extension byte. Output it directly. */
13559 scratchbuf[0] = '$';
13560 print_operand_value (scratchbuf + 1, 1, cmp_type);
13561 oappend_maybe_intel (scratchbuf);
13562 scratchbuf[0] = '\0';
13563 }
13564 }
13565
13566 static void
13567 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13568 {
13569 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13570 if (!intel_syntax)
13571 {
13572 strcpy (op_out[0], names32[0]);
13573 strcpy (op_out[1], names32[1]);
13574 if (bytemode == eBX_reg)
13575 strcpy (op_out[2], names32[3]);
13576 two_source_ops = 1;
13577 }
13578 /* Skip mod/rm byte. */
13579 MODRM_CHECK;
13580 codep++;
13581 }
13582
13583 static void
13584 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13585 int sizeflag ATTRIBUTE_UNUSED)
13586 {
13587 /* monitor %{e,r,}ax,%ecx,%edx" */
13588 if (!intel_syntax)
13589 {
13590 const char **names = (address_mode == mode_64bit
13591 ? names64 : names32);
13592
13593 if (prefixes & PREFIX_ADDR)
13594 {
13595 /* Remove "addr16/addr32". */
13596 all_prefixes[last_addr_prefix] = 0;
13597 names = (address_mode != mode_32bit
13598 ? names32 : names16);
13599 used_prefixes |= PREFIX_ADDR;
13600 }
13601 else if (address_mode == mode_16bit)
13602 names = names16;
13603 strcpy (op_out[0], names[0]);
13604 strcpy (op_out[1], names32[1]);
13605 strcpy (op_out[2], names32[2]);
13606 two_source_ops = 1;
13607 }
13608 /* Skip mod/rm byte. */
13609 MODRM_CHECK;
13610 codep++;
13611 }
13612
13613 static void
13614 BadOp (void)
13615 {
13616 /* Throw away prefixes and 1st. opcode byte. */
13617 codep = insn_codep + 1;
13618 oappend ("(bad)");
13619 }
13620
13621 static void
13622 REP_Fixup (int bytemode, int sizeflag)
13623 {
13624 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13625 lods and stos. */
13626 if (prefixes & PREFIX_REPZ)
13627 all_prefixes[last_repz_prefix] = REP_PREFIX;
13628
13629 switch (bytemode)
13630 {
13631 case al_reg:
13632 case eAX_reg:
13633 case indir_dx_reg:
13634 OP_IMREG (bytemode, sizeflag);
13635 break;
13636 case eDI_reg:
13637 OP_ESreg (bytemode, sizeflag);
13638 break;
13639 case eSI_reg:
13640 OP_DSreg (bytemode, sizeflag);
13641 break;
13642 default:
13643 abort ();
13644 break;
13645 }
13646 }
13647
13648 static void
13649 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13650 {
13651 if ( isa64 != amd64 )
13652 return;
13653
13654 obufp = obuf;
13655 BadOp ();
13656 mnemonicendp = obufp;
13657 ++codep;
13658 }
13659
13660 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13661 "bnd". */
13662
13663 static void
13664 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13665 {
13666 if (prefixes & PREFIX_REPNZ)
13667 all_prefixes[last_repnz_prefix] = BND_PREFIX;
13668 }
13669
13670 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13671 "notrack". */
13672
13673 static void
13674 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
13675 int sizeflag ATTRIBUTE_UNUSED)
13676 {
13677
13678 /* Since active_seg_prefix is not set in 64-bit mode, check whether
13679 we've seen a PREFIX_DS. */
13680 if ((prefixes & PREFIX_DS) != 0
13681 && (address_mode != mode_64bit || last_data_prefix < 0))
13682 {
13683 /* NOTRACK prefix is only valid on indirect branch instructions.
13684 NB: DATA prefix is unsupported for Intel64. */
13685 active_seg_prefix = 0;
13686 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
13687 }
13688 }
13689
13690 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13691 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13692 */
13693
13694 static void
13695 HLE_Fixup1 (int bytemode, int sizeflag)
13696 {
13697 if (modrm.mod != 3
13698 && (prefixes & PREFIX_LOCK) != 0)
13699 {
13700 if (prefixes & PREFIX_REPZ)
13701 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13702 if (prefixes & PREFIX_REPNZ)
13703 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13704 }
13705
13706 OP_E (bytemode, sizeflag);
13707 }
13708
13709 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13710 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13711 */
13712
13713 static void
13714 HLE_Fixup2 (int bytemode, int sizeflag)
13715 {
13716 if (modrm.mod != 3)
13717 {
13718 if (prefixes & PREFIX_REPZ)
13719 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13720 if (prefixes & PREFIX_REPNZ)
13721 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13722 }
13723
13724 OP_E (bytemode, sizeflag);
13725 }
13726
13727 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13728 "xrelease" for memory operand. No check for LOCK prefix. */
13729
13730 static void
13731 HLE_Fixup3 (int bytemode, int sizeflag)
13732 {
13733 if (modrm.mod != 3
13734 && last_repz_prefix > last_repnz_prefix
13735 && (prefixes & PREFIX_REPZ) != 0)
13736 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13737
13738 OP_E (bytemode, sizeflag);
13739 }
13740
13741 static void
13742 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13743 {
13744 USED_REX (REX_W);
13745 if (rex & REX_W)
13746 {
13747 /* Change cmpxchg8b to cmpxchg16b. */
13748 char *p = mnemonicendp - 2;
13749 mnemonicendp = stpcpy (p, "16b");
13750 bytemode = o_mode;
13751 }
13752 else if ((prefixes & PREFIX_LOCK) != 0)
13753 {
13754 if (prefixes & PREFIX_REPZ)
13755 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13756 if (prefixes & PREFIX_REPNZ)
13757 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13758 }
13759
13760 OP_M (bytemode, sizeflag);
13761 }
13762
13763 static void
13764 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13765 {
13766 const char **names;
13767
13768 if (need_vex)
13769 {
13770 switch (vex.length)
13771 {
13772 case 128:
13773 names = names_xmm;
13774 break;
13775 case 256:
13776 names = names_ymm;
13777 break;
13778 default:
13779 abort ();
13780 }
13781 }
13782 else
13783 names = names_xmm;
13784 oappend (names[reg]);
13785 }
13786
13787 static void
13788 FXSAVE_Fixup (int bytemode, int sizeflag)
13789 {
13790 /* Add proper suffix to "fxsave" and "fxrstor". */
13791 USED_REX (REX_W);
13792 if (rex & REX_W)
13793 {
13794 char *p = mnemonicendp;
13795 *p++ = '6';
13796 *p++ = '4';
13797 *p = '\0';
13798 mnemonicendp = p;
13799 }
13800 OP_M (bytemode, sizeflag);
13801 }
13802
13803 /* Display the destination register operand for instructions with
13804 VEX. */
13805
13806 static void
13807 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13808 {
13809 int reg;
13810 const char **names;
13811
13812 if (!need_vex)
13813 abort ();
13814
13815 reg = vex.register_specifier;
13816 vex.register_specifier = 0;
13817 if (address_mode != mode_64bit)
13818 reg &= 7;
13819 else if (vex.evex && !vex.v)
13820 reg += 16;
13821
13822 if (bytemode == vex_scalar_mode)
13823 {
13824 oappend (names_xmm[reg]);
13825 return;
13826 }
13827
13828 if (bytemode == tmm_mode)
13829 {
13830 /* All 3 TMM registers must be distinct. */
13831 if (reg >= 8)
13832 oappend ("(bad)");
13833 else
13834 {
13835 /* This must be the 3rd operand. */
13836 if (obufp != op_out[2])
13837 abort ();
13838 oappend (names_tmm[reg]);
13839 if (reg == modrm.reg || reg == modrm.rm)
13840 strcpy (obufp, "/(bad)");
13841 }
13842
13843 if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
13844 {
13845 if (modrm.reg <= 8
13846 && (modrm.reg == modrm.rm || modrm.reg == reg))
13847 strcat (op_out[0], "/(bad)");
13848 if (modrm.rm <= 8
13849 && (modrm.rm == modrm.reg || modrm.rm == reg))
13850 strcat (op_out[1], "/(bad)");
13851 }
13852
13853 return;
13854 }
13855
13856 switch (vex.length)
13857 {
13858 case 128:
13859 switch (bytemode)
13860 {
13861 case vex_mode:
13862 case vex_vsib_q_w_dq_mode:
13863 case vex_vsib_q_w_d_mode:
13864 names = names_xmm;
13865 break;
13866 case dq_mode:
13867 if (rex & REX_W)
13868 names = names64;
13869 else
13870 names = names32;
13871 break;
13872 case mask_bd_mode:
13873 case mask_mode:
13874 if (reg > 0x7)
13875 {
13876 oappend ("(bad)");
13877 return;
13878 }
13879 names = names_mask;
13880 break;
13881 default:
13882 abort ();
13883 return;
13884 }
13885 break;
13886 case 256:
13887 switch (bytemode)
13888 {
13889 case vex_mode:
13890 names = names_ymm;
13891 break;
13892 case vex_vsib_q_w_dq_mode:
13893 case vex_vsib_q_w_d_mode:
13894 names = vex.w ? names_ymm : names_xmm;
13895 break;
13896 case mask_bd_mode:
13897 case mask_mode:
13898 if (reg > 0x7)
13899 {
13900 oappend ("(bad)");
13901 return;
13902 }
13903 names = names_mask;
13904 break;
13905 default:
13906 /* See PR binutils/20893 for a reproducer. */
13907 oappend ("(bad)");
13908 return;
13909 }
13910 break;
13911 case 512:
13912 names = names_zmm;
13913 break;
13914 default:
13915 abort ();
13916 break;
13917 }
13918 oappend (names[reg]);
13919 }
13920
13921 static void
13922 OP_VexR (int bytemode, int sizeflag)
13923 {
13924 if (modrm.mod == 3)
13925 OP_VEX (bytemode, sizeflag);
13926 }
13927
13928 static void
13929 OP_VexW (int bytemode, int sizeflag)
13930 {
13931 OP_VEX (bytemode, sizeflag);
13932
13933 if (vex.w)
13934 {
13935 /* Swap 2nd and 3rd operands. */
13936 strcpy (scratchbuf, op_out[2]);
13937 strcpy (op_out[2], op_out[1]);
13938 strcpy (op_out[1], scratchbuf);
13939 }
13940 }
13941
13942 static void
13943 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13944 {
13945 int reg;
13946 const char **names = names_xmm;
13947
13948 FETCH_DATA (the_info, codep + 1);
13949 reg = *codep++;
13950
13951 if (bytemode != x_mode && bytemode != scalar_mode)
13952 abort ();
13953
13954 reg >>= 4;
13955 if (address_mode != mode_64bit)
13956 reg &= 7;
13957
13958 if (bytemode == x_mode && vex.length == 256)
13959 names = names_ymm;
13960
13961 oappend (names[reg]);
13962
13963 if (vex.w)
13964 {
13965 /* Swap 3rd and 4th operands. */
13966 strcpy (scratchbuf, op_out[3]);
13967 strcpy (op_out[3], op_out[2]);
13968 strcpy (op_out[2], scratchbuf);
13969 }
13970 }
13971
13972 static void
13973 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
13974 int sizeflag ATTRIBUTE_UNUSED)
13975 {
13976 scratchbuf[0] = '$';
13977 print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
13978 oappend_maybe_intel (scratchbuf);
13979 }
13980
13981 static void
13982 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
13983 int sizeflag ATTRIBUTE_UNUSED)
13984 {
13985 unsigned int cmp_type;
13986
13987 if (!vex.evex)
13988 abort ();
13989
13990 FETCH_DATA (the_info, codep + 1);
13991 cmp_type = *codep++ & 0xff;
13992 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13993 If it's the case, print suffix, otherwise - print the immediate. */
13994 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13995 && cmp_type != 3
13996 && cmp_type != 7)
13997 {
13998 char suffix [3];
13999 char *p = mnemonicendp - 2;
14000
14001 /* vpcmp* can have both one- and two-lettered suffix. */
14002 if (p[0] == 'p')
14003 {
14004 p++;
14005 suffix[0] = p[0];
14006 suffix[1] = '\0';
14007 }
14008 else
14009 {
14010 suffix[0] = p[0];
14011 suffix[1] = p[1];
14012 suffix[2] = '\0';
14013 }
14014
14015 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14016 mnemonicendp += simd_cmp_op[cmp_type].len;
14017 }
14018 else
14019 {
14020 /* We have a reserved extension byte. Output it directly. */
14021 scratchbuf[0] = '$';
14022 print_operand_value (scratchbuf + 1, 1, cmp_type);
14023 oappend_maybe_intel (scratchbuf);
14024 scratchbuf[0] = '\0';
14025 }
14026 }
14027
14028 static const struct op xop_cmp_op[] =
14029 {
14030 { STRING_COMMA_LEN ("lt") },
14031 { STRING_COMMA_LEN ("le") },
14032 { STRING_COMMA_LEN ("gt") },
14033 { STRING_COMMA_LEN ("ge") },
14034 { STRING_COMMA_LEN ("eq") },
14035 { STRING_COMMA_LEN ("neq") },
14036 { STRING_COMMA_LEN ("false") },
14037 { STRING_COMMA_LEN ("true") }
14038 };
14039
14040 static void
14041 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
14042 int sizeflag ATTRIBUTE_UNUSED)
14043 {
14044 unsigned int cmp_type;
14045
14046 FETCH_DATA (the_info, codep + 1);
14047 cmp_type = *codep++ & 0xff;
14048 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
14049 {
14050 char suffix[3];
14051 char *p = mnemonicendp - 2;
14052
14053 /* vpcom* can have both one- and two-lettered suffix. */
14054 if (p[0] == 'm')
14055 {
14056 p++;
14057 suffix[0] = p[0];
14058 suffix[1] = '\0';
14059 }
14060 else
14061 {
14062 suffix[0] = p[0];
14063 suffix[1] = p[1];
14064 suffix[2] = '\0';
14065 }
14066
14067 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
14068 mnemonicendp += xop_cmp_op[cmp_type].len;
14069 }
14070 else
14071 {
14072 /* We have a reserved extension byte. Output it directly. */
14073 scratchbuf[0] = '$';
14074 print_operand_value (scratchbuf + 1, 1, cmp_type);
14075 oappend_maybe_intel (scratchbuf);
14076 scratchbuf[0] = '\0';
14077 }
14078 }
14079
14080 static const struct op pclmul_op[] =
14081 {
14082 { STRING_COMMA_LEN ("lql") },
14083 { STRING_COMMA_LEN ("hql") },
14084 { STRING_COMMA_LEN ("lqh") },
14085 { STRING_COMMA_LEN ("hqh") }
14086 };
14087
14088 static void
14089 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
14090 int sizeflag ATTRIBUTE_UNUSED)
14091 {
14092 unsigned int pclmul_type;
14093
14094 FETCH_DATA (the_info, codep + 1);
14095 pclmul_type = *codep++ & 0xff;
14096 switch (pclmul_type)
14097 {
14098 case 0x10:
14099 pclmul_type = 2;
14100 break;
14101 case 0x11:
14102 pclmul_type = 3;
14103 break;
14104 default:
14105 break;
14106 }
14107 if (pclmul_type < ARRAY_SIZE (pclmul_op))
14108 {
14109 char suffix [4];
14110 char *p = mnemonicendp - 3;
14111 suffix[0] = p[0];
14112 suffix[1] = p[1];
14113 suffix[2] = p[2];
14114 suffix[3] = '\0';
14115 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14116 mnemonicendp += pclmul_op[pclmul_type].len;
14117 }
14118 else
14119 {
14120 /* We have a reserved extension byte. Output it directly. */
14121 scratchbuf[0] = '$';
14122 print_operand_value (scratchbuf + 1, 1, pclmul_type);
14123 oappend_maybe_intel (scratchbuf);
14124 scratchbuf[0] = '\0';
14125 }
14126 }
14127
14128 static void
14129 MOVSXD_Fixup (int bytemode, int sizeflag)
14130 {
14131 /* Add proper suffix to "movsxd". */
14132 char *p = mnemonicendp;
14133
14134 switch (bytemode)
14135 {
14136 case movsxd_mode:
14137 if (intel_syntax)
14138 {
14139 *p++ = 'x';
14140 *p++ = 'd';
14141 goto skip;
14142 }
14143
14144 USED_REX (REX_W);
14145 if (rex & REX_W)
14146 {
14147 *p++ = 'l';
14148 *p++ = 'q';
14149 }
14150 else
14151 {
14152 *p++ = 'x';
14153 *p++ = 'd';
14154 }
14155 break;
14156 default:
14157 oappend (INTERNAL_DISASSEMBLER_ERROR);
14158 break;
14159 }
14160
14161 skip:
14162 mnemonicendp = p;
14163 *p = '\0';
14164 OP_E (bytemode, sizeflag);
14165 }
14166
14167 static void
14168 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14169 {
14170 if (!vex.evex
14171 || (bytemode != mask_mode && bytemode != mask_bd_mode))
14172 abort ();
14173
14174 USED_REX (REX_R);
14175 if ((rex & REX_R) != 0 || !vex.r)
14176 {
14177 BadOp ();
14178 return;
14179 }
14180
14181 oappend (names_mask [modrm.reg]);
14182 }
14183
14184 static void
14185 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14186 {
14187 if (modrm.mod == 3 && vex.b)
14188 switch (bytemode)
14189 {
14190 case evex_rounding_64_mode:
14191 if (address_mode != mode_64bit)
14192 {
14193 oappend ("(bad)");
14194 break;
14195 }
14196 /* Fall through. */
14197 case evex_rounding_mode:
14198 oappend (names_rounding[vex.ll]);
14199 break;
14200 case evex_sae_mode:
14201 oappend ("{sae}");
14202 break;
14203 default:
14204 abort ();
14205 break;
14206 }
14207 }
GDB Binutils - Deliverables
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