opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VZERO_Fixup (int, int);
  99 static void VCMP_Fixup (int, int);
 100 static void VPCMP_Fixup (int, int);
 101 static void VPCOM_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Ev_bnd { OP_E, v_bnd_mode }
 253 #define EvS { OP_E, v_swap_mode }
 254 #define Ed { OP_E, d_mode }
 255 #define Edq { OP_E, dq_mode }
 256 #define Edqw { OP_E, dqw_mode }
 257 #define Edqb { OP_E, dqb_mode }
 258 #define Edb { OP_E, db_mode }
 259 #define Edw { OP_E, dw_mode }
 260 #define Edqd { OP_E, dqd_mode }
 261 #define Eq { OP_E, q_mode }
 262 #define indirEv { OP_indirE, indir_v_mode }
 263 #define indirEp { OP_indirE, f_mode }
 264 #define stackEv { OP_E, stack_v_mode }
 265 #define Em { OP_E, m_mode }
 266 #define Ew { OP_E, w_mode }
 267 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 268 #define Ma { OP_M, a_mode }
 269 #define Mb { OP_M, b_mode }
 270 #define Md { OP_M, d_mode }
 271 #define Mo { OP_M, o_mode }
 272 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 273 #define Mq { OP_M, q_mode }
 274 #define Mx { OP_M, x_mode }
 275 #define Mxmm { OP_M, xmm_mode }
 276 #define Gb { OP_G, b_mode }
 277 #define Gbnd { OP_G, bnd_mode }
 278 #define Gv { OP_G, v_mode }
 279 #define Gd { OP_G, d_mode }
 280 #define Gdq { OP_G, dq_mode }
 281 #define Gm { OP_G, m_mode }
 282 #define Gw { OP_G, w_mode }
 283 #define Rd { OP_R, d_mode }
 284 #define Rdq { OP_R, dq_mode }
 285 #define Rm { OP_R, m_mode }
 286 #define Ib { OP_I, b_mode }
 287 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 288 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 289 #define Iv { OP_I, v_mode }
 290 #define sIv { OP_sI, v_mode }
 291 #define Iq { OP_I, q_mode }
 292 #define Iv64 { OP_I64, v_mode }
 293 #define Iw { OP_I, w_mode }
 294 #define I1 { OP_I, const_1_mode }
 295 #define Jb { OP_J, b_mode }
 296 #define Jv { OP_J, v_mode }
 297 #define Cm { OP_C, m_mode }
 298 #define Dm { OP_D, m_mode }
 299 #define Td { OP_T, d_mode }
 300 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 301
 302 #define RMeAX { OP_REG, eAX_reg }
 303 #define RMeBX { OP_REG, eBX_reg }
 304 #define RMeCX { OP_REG, eCX_reg }
 305 #define RMeDX { OP_REG, eDX_reg }
 306 #define RMeSP { OP_REG, eSP_reg }
 307 #define RMeBP { OP_REG, eBP_reg }
 308 #define RMeSI { OP_REG, eSI_reg }
 309 #define RMeDI { OP_REG, eDI_reg }
 310 #define RMrAX { OP_REG, rAX_reg }
 311 #define RMrBX { OP_REG, rBX_reg }
 312 #define RMrCX { OP_REG, rCX_reg }
 313 #define RMrDX { OP_REG, rDX_reg }
 314 #define RMrSP { OP_REG, rSP_reg }
 315 #define RMrBP { OP_REG, rBP_reg }
 316 #define RMrSI { OP_REG, rSI_reg }
 317 #define RMrDI { OP_REG, rDI_reg }
 318 #define RMAL { OP_REG, al_reg }
 319 #define RMCL { OP_REG, cl_reg }
 320 #define RMDL { OP_REG, dl_reg }
 321 #define RMBL { OP_REG, bl_reg }
 322 #define RMAH { OP_REG, ah_reg }
 323 #define RMCH { OP_REG, ch_reg }
 324 #define RMDH { OP_REG, dh_reg }
 325 #define RMBH { OP_REG, bh_reg }
 326 #define RMAX { OP_REG, ax_reg }
 327 #define RMDX { OP_REG, dx_reg }
 328
 329 #define eAX { OP_IMREG, eAX_reg }
 330 #define eBX { OP_IMREG, eBX_reg }
 331 #define eCX { OP_IMREG, eCX_reg }
 332 #define eDX { OP_IMREG, eDX_reg }
 333 #define eSP { OP_IMREG, eSP_reg }
 334 #define eBP { OP_IMREG, eBP_reg }
 335 #define eSI { OP_IMREG, eSI_reg }
 336 #define eDI { OP_IMREG, eDI_reg }
 337 #define AL { OP_IMREG, al_reg }
 338 #define CL { OP_IMREG, cl_reg }
 339 #define DL { OP_IMREG, dl_reg }
 340 #define BL { OP_IMREG, bl_reg }
 341 #define AH { OP_IMREG, ah_reg }
 342 #define CH { OP_IMREG, ch_reg }
 343 #define DH { OP_IMREG, dh_reg }
 344 #define BH { OP_IMREG, bh_reg }
 345 #define AX { OP_IMREG, ax_reg }
 346 #define DX { OP_IMREG, dx_reg }
 347 #define zAX { OP_IMREG, z_mode_ax_reg }
 348 #define indirDX { OP_IMREG, indir_dx_reg }
 349
 350 #define Sw { OP_SEG, w_mode }
 351 #define Sv { OP_SEG, v_mode }
 352 #define Ap { OP_DIR, 0 }
 353 #define Ob { OP_OFF64, b_mode }
 354 #define Ov { OP_OFF64, v_mode }
 355 #define Xb { OP_DSreg, eSI_reg }
 356 #define Xv { OP_DSreg, eSI_reg }
 357 #define Xz { OP_DSreg, eSI_reg }
 358 #define Yb { OP_ESreg, eDI_reg }
 359 #define Yv { OP_ESreg, eDI_reg }
 360 #define DSBX { OP_DSreg, eBX_reg }
 361
 362 #define es { OP_REG, es_reg }
 363 #define ss { OP_REG, ss_reg }
 364 #define cs { OP_REG, cs_reg }
 365 #define ds { OP_REG, ds_reg }
 366 #define fs { OP_REG, fs_reg }
 367 #define gs { OP_REG, gs_reg }
 368
 369 #define MX { OP_MMX, 0 }
 370 #define XM { OP_XMM, 0 }
 371 #define XMScalar { OP_XMM, scalar_mode }
 372 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 373 #define XMM { OP_XMM, xmm_mode }
 374 #define XMxmmq { OP_XMM, xmmq_mode }
 375 #define EM { OP_EM, v_mode }
 376 #define EMS { OP_EM, v_swap_mode }
 377 #define EMd { OP_EM, d_mode }
 378 #define EMx { OP_EM, x_mode }
 379 #define EXbScalar { OP_EX, b_scalar_mode }
 380 #define EXw { OP_EX, w_mode }
 381 #define EXwScalar { OP_EX, w_scalar_mode }
 382 #define EXd { OP_EX, d_mode }
 383 #define EXdScalar { OP_EX, d_scalar_mode }
 384 #define EXdS { OP_EX, d_swap_mode }
 385 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 386 #define EXq { OP_EX, q_mode }
 387 #define EXqScalar { OP_EX, q_scalar_mode }
 388 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 389 #define EXqS { OP_EX, q_swap_mode }
 390 #define EXx { OP_EX, x_mode }
 391 #define EXxS { OP_EX, x_swap_mode }
 392 #define EXxmm { OP_EX, xmm_mode }
 393 #define EXymm { OP_EX, ymm_mode }
 394 #define EXxmmq { OP_EX, xmmq_mode }
 395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 398 #define EXxmm_md { OP_EX, xmm_md_mode }
 399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 400 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 401 #define EXxmmdw { OP_EX, xmmdw_mode }
 402 #define EXxmmqd { OP_EX, xmmqd_mode }
 403 #define EXymmq { OP_EX, ymmq_mode }
 404 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 405 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 406 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 407 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 408 #define MS { OP_MS, v_mode }
 409 #define XS { OP_XS, v_mode }
 410 #define EMCq { OP_EMC, q_mode }
 411 #define MXC { OP_MXC, 0 }
 412 #define OPSUF { OP_3DNowSuffix, 0 }
 413 #define CMP { CMP_Fixup, 0 }
 414 #define XMM0 { XMM_Fixup, 0 }
 415 #define FXSAVE { FXSAVE_Fixup, 0 }
 416 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 417 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 418
 419 #define Vex { OP_VEX, vex_mode }
 420 #define VexScalar { OP_VEX, vex_scalar_mode }
 421 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 422 #define Vex128 { OP_VEX, vex128_mode }
 423 #define Vex256 { OP_VEX, vex256_mode }
 424 #define VexGdq { OP_VEX, dq_mode }
 425 #define EXdVex { OP_EX_Vex, d_mode }
 426 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 427 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 428 #define EXqVex { OP_EX_Vex, q_mode }
 429 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 430 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 431 #define EXVexW { OP_EX_VexW, x_mode }
 432 #define EXdVexW { OP_EX_VexW, d_mode }
 433 #define EXqVexW { OP_EX_VexW, q_mode }
 434 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 435 #define XMVex { OP_XMM_Vex, 0 }
 436 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 437 #define XMVexW { OP_XMM_VexW, 0 }
 438 #define XMVexI4 { OP_REG_VexI4, x_mode }
 439 #define PCLMUL { PCLMUL_Fixup, 0 }
 440 #define VZERO { VZERO_Fixup, 0 }
 441 #define VCMP { VCMP_Fixup, 0 }
 442 #define VPCMP { VPCMP_Fixup, 0 }
 443 #define VPCOM { VPCOM_Fixup, 0 }
 444
 445 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 446 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 447
 448 #define XMask { OP_Mask, mask_mode }
 449 #define MaskG { OP_G, mask_mode }
 450 #define MaskE { OP_E, mask_mode }
 451 #define MaskBDE { OP_E, mask_bd_mode }
 452 #define MaskR { OP_R, mask_mode }
 453 #define MaskVex { OP_VEX, mask_mode }
 454
 455 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 456 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 457 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 458 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 459
 460 /* Used handle "rep" prefix for string instructions.  */
 461 #define Xbr { REP_Fixup, eSI_reg }
 462 #define Xvr { REP_Fixup, eSI_reg }
 463 #define Ybr { REP_Fixup, eDI_reg }
 464 #define Yvr { REP_Fixup, eDI_reg }
 465 #define Yzr { REP_Fixup, eDI_reg }
 466 #define indirDXr { REP_Fixup, indir_dx_reg }
 467 #define ALr { REP_Fixup, al_reg }
 468 #define eAXr { REP_Fixup, eAX_reg }
 469
 470 /* Used handle HLE prefix for lockable instructions.  */
 471 #define Ebh1 { HLE_Fixup1, b_mode }
 472 #define Evh1 { HLE_Fixup1, v_mode }
 473 #define Ebh2 { HLE_Fixup2, b_mode }
 474 #define Evh2 { HLE_Fixup2, v_mode }
 475 #define Ebh3 { HLE_Fixup3, b_mode }
 476 #define Evh3 { HLE_Fixup3, v_mode }
 477
 478 #define BND { BND_Fixup, 0 }
 479 #define NOTRACK { NOTRACK_Fixup, 0 }
 480
 481 #define cond_jump_flag { NULL, cond_jump_mode }
 482 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 483
 484 /* bits in sizeflag */
 485 #define SUFFIX_ALWAYS 4
 486 #define AFLAG 2
 487 #define DFLAG 1
 488
 489 enum
 490 {
 491   /* byte operand */
 492   b_mode = 1,
 493   /* byte operand with operand swapped */
 494   b_swap_mode,
 495   /* byte operand, sign extend like 'T' suffix */
 496   b_T_mode,
 497   /* operand size depends on prefixes */
 498   v_mode,
 499   /* operand size depends on prefixes with operand swapped */
 500   v_swap_mode,
 501   /* word operand */
 502   w_mode,
 503   /* double word operand  */
 504   d_mode,
 505   /* double word operand with operand swapped */
 506   d_swap_mode,
 507   /* quad word operand */
 508   q_mode,
 509   /* quad word operand with operand swapped */
 510   q_swap_mode,
 511   /* ten-byte operand */
 512   t_mode,
 513   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 514      broadcast enabled.  */
 515   x_mode,
 516   /* Similar to x_mode, but with different EVEX mem shifts.  */
 517   evex_x_gscat_mode,
 518   /* Similar to x_mode, but with disabled broadcast.  */
 519   evex_x_nobcst_mode,
 520   /* Similar to x_mode, but with operands swapped and disabled broadcast
 521      in EVEX.  */
 522   x_swap_mode,
 523   /* 16-byte XMM operand */
 524   xmm_mode,
 525   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 526      memory operand (depending on vector length).  Broadcast isn't
 527      allowed.  */
 528   xmmq_mode,
 529   /* Same as xmmq_mode, but broadcast is allowed.  */
 530   evex_half_bcst_xmmq_mode,
 531   /* XMM register or byte memory operand */
 532   xmm_mb_mode,
 533   /* XMM register or word memory operand */
 534   xmm_mw_mode,
 535   /* XMM register or double word memory operand */
 536   xmm_md_mode,
 537   /* XMM register or quad word memory operand */
 538   xmm_mq_mode,
 539   /* XMM register or double/quad word memory operand, depending on
 540      VEX.W.  */
 541   xmm_mdq_mode,
 542   /* 16-byte XMM, word, double word or quad word operand.  */
 543   xmmdw_mode,
 544   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 545   xmmqd_mode,
 546   /* 32-byte YMM operand */
 547   ymm_mode,
 548   /* quad word, ymmword or zmmword memory operand.  */
 549   ymmq_mode,
 550   /* 32-byte YMM or 16-byte word operand */
 551   ymmxmm_mode,
 552   /* d_mode in 32bit, q_mode in 64bit mode.  */
 553   m_mode,
 554   /* pair of v_mode operands */
 555   a_mode,
 556   cond_jump_mode,
 557   loop_jcxz_mode,
 558   v_bnd_mode,
 559   /* operand size depends on REX prefixes.  */
 560   dq_mode,
 561   /* registers like dq_mode, memory like w_mode.  */
 562   dqw_mode,
 563   bnd_mode,
 564   /* 4- or 6-byte pointer operand */
 565   f_mode,
 566   const_1_mode,
 567   /* v_mode for indirect branch opcodes.  */
 568   indir_v_mode,
 569   /* v_mode for stack-related opcodes.  */
 570   stack_v_mode,
 571   /* non-quad operand size depends on prefixes */
 572   z_mode,
 573   /* 16-byte operand */
 574   o_mode,
 575   /* registers like dq_mode, memory like b_mode.  */
 576   dqb_mode,
 577   /* registers like d_mode, memory like b_mode.  */
 578   db_mode,
 579   /* registers like d_mode, memory like w_mode.  */
 580   dw_mode,
 581   /* registers like dq_mode, memory like d_mode.  */
 582   dqd_mode,
 583   /* normal vex mode */
 584   vex_mode,
 585   /* 128bit vex mode */
 586   vex128_mode,
 587   /* 256bit vex mode */
 588   vex256_mode,
 589   /* operand size depends on the VEX.W bit.  */
 590   vex_w_dq_mode,
 591
 592   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 593   vex_vsib_d_w_dq_mode,
 594   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 595   vex_vsib_d_w_d_mode,
 596   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 597   vex_vsib_q_w_dq_mode,
 598   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 599   vex_vsib_q_w_d_mode,
 600
 601   /* scalar, ignore vector length.  */
 602   scalar_mode,
 603   /* like b_mode, ignore vector length.  */
 604   b_scalar_mode,
 605   /* like w_mode, ignore vector length.  */
 606   w_scalar_mode,
 607   /* like d_mode, ignore vector length.  */
 608   d_scalar_mode,
 609   /* like d_swap_mode, ignore vector length.  */
 610   d_scalar_swap_mode,
 611   /* like q_mode, ignore vector length.  */
 612   q_scalar_mode,
 613   /* like q_swap_mode, ignore vector length.  */
 614   q_scalar_swap_mode,
 615   /* like vex_mode, ignore vector length.  */
 616   vex_scalar_mode,
 617   /* like vex_w_dq_mode, ignore vector length.  */
 618   vex_scalar_w_dq_mode,
 619
 620   /* Static rounding.  */
 621   evex_rounding_mode,
 622   /* Supress all exceptions.  */
 623   evex_sae_mode,
 624
 625   /* Mask register operand.  */
 626   mask_mode,
 627   /* Mask register operand.  */
 628   mask_bd_mode,
 629
 630   es_reg,
 631   cs_reg,
 632   ss_reg,
 633   ds_reg,
 634   fs_reg,
 635   gs_reg,
 636
 637   eAX_reg,
 638   eCX_reg,
 639   eDX_reg,
 640   eBX_reg,
 641   eSP_reg,
 642   eBP_reg,
 643   eSI_reg,
 644   eDI_reg,
 645
 646   al_reg,
 647   cl_reg,
 648   dl_reg,
 649   bl_reg,
 650   ah_reg,
 651   ch_reg,
 652   dh_reg,
 653   bh_reg,
 654
 655   ax_reg,
 656   cx_reg,
 657   dx_reg,
 658   bx_reg,
 659   sp_reg,
 660   bp_reg,
 661   si_reg,
 662   di_reg,
 663
 664   rAX_reg,
 665   rCX_reg,
 666   rDX_reg,
 667   rBX_reg,
 668   rSP_reg,
 669   rBP_reg,
 670   rSI_reg,
 671   rDI_reg,
 672
 673   z_mode_ax_reg,
 674   indir_dx_reg
 675 };
 676
 677 enum
 678 {
 679   FLOATCODE = 1,
 680   USE_REG_TABLE,
 681   USE_MOD_TABLE,
 682   USE_RM_TABLE,
 683   USE_PREFIX_TABLE,
 684   USE_X86_64_TABLE,
 685   USE_3BYTE_TABLE,
 686   USE_XOP_8F_TABLE,
 687   USE_VEX_C4_TABLE,
 688   USE_VEX_C5_TABLE,
 689   USE_VEX_LEN_TABLE,
 690   USE_VEX_W_TABLE,
 691   USE_EVEX_TABLE
 692 };
 693
 694 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 695
 696 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 697 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 698 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 699 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 700 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 701 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 702 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 703 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 704 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 705 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 706 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 707 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 708 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 709 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 710 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 711
 712 enum
 713 {
 714   REG_80 = 0,
 715   REG_81,
 716   REG_83,
 717   REG_8F,
 718   REG_C0,
 719   REG_C1,
 720   REG_C6,
 721   REG_C7,
 722   REG_D0,
 723   REG_D1,
 724   REG_D2,
 725   REG_D3,
 726   REG_F6,
 727   REG_F7,
 728   REG_FE,
 729   REG_FF,
 730   REG_0F00,
 731   REG_0F01,
 732   REG_0F0D,
 733   REG_0F18,
 734   REG_0F1E_MOD_3,
 735   REG_0F71,
 736   REG_0F72,
 737   REG_0F73,
 738   REG_0FA6,
 739   REG_0FA7,
 740   REG_0FAE,
 741   REG_0FBA,
 742   REG_0FC7,
 743   REG_VEX_0F71,
 744   REG_VEX_0F72,
 745   REG_VEX_0F73,
 746   REG_VEX_0FAE,
 747   REG_VEX_0F38F3,
 748   REG_XOP_LWPCB,
 749   REG_XOP_LWP,
 750   REG_XOP_TBM_01,
 751   REG_XOP_TBM_02,
 752
 753   REG_EVEX_0F71,
 754   REG_EVEX_0F72,
 755   REG_EVEX_0F73,
 756   REG_EVEX_0F38C6,
 757   REG_EVEX_0F38C7
 758 };
 759
 760 enum
 761 {
 762   MOD_8D = 0,
 763   MOD_C6_REG_7,
 764   MOD_C7_REG_7,
 765   MOD_FF_REG_3,
 766   MOD_FF_REG_5,
 767   MOD_0F01_REG_0,
 768   MOD_0F01_REG_1,
 769   MOD_0F01_REG_2,
 770   MOD_0F01_REG_3,
 771   MOD_0F01_REG_5,
 772   MOD_0F01_REG_7,
 773   MOD_0F12_PREFIX_0,
 774   MOD_0F13,
 775   MOD_0F16_PREFIX_0,
 776   MOD_0F17,
 777   MOD_0F18_REG_0,
 778   MOD_0F18_REG_1,
 779   MOD_0F18_REG_2,
 780   MOD_0F18_REG_3,
 781   MOD_0F18_REG_4,
 782   MOD_0F18_REG_5,
 783   MOD_0F18_REG_6,
 784   MOD_0F18_REG_7,
 785   MOD_0F1A_PREFIX_0,
 786   MOD_0F1B_PREFIX_0,
 787   MOD_0F1B_PREFIX_1,
 788   MOD_0F1E_PREFIX_1,
 789   MOD_0F24,
 790   MOD_0F26,
 791   MOD_0F2B_PREFIX_0,
 792   MOD_0F2B_PREFIX_1,
 793   MOD_0F2B_PREFIX_2,
 794   MOD_0F2B_PREFIX_3,
 795   MOD_0F51,
 796   MOD_0F71_REG_2,
 797   MOD_0F71_REG_4,
 798   MOD_0F71_REG_6,
 799   MOD_0F72_REG_2,
 800   MOD_0F72_REG_4,
 801   MOD_0F72_REG_6,
 802   MOD_0F73_REG_2,
 803   MOD_0F73_REG_3,
 804   MOD_0F73_REG_6,
 805   MOD_0F73_REG_7,
 806   MOD_0FAE_REG_0,
 807   MOD_0FAE_REG_1,
 808   MOD_0FAE_REG_2,
 809   MOD_0FAE_REG_3,
 810   MOD_0FAE_REG_4,
 811   MOD_0FAE_REG_5,
 812   MOD_0FAE_REG_6,
 813   MOD_0FAE_REG_7,
 814   MOD_0FB2,
 815   MOD_0FB4,
 816   MOD_0FB5,
 817   MOD_0FC3,
 818   MOD_0FC7_REG_3,
 819   MOD_0FC7_REG_4,
 820   MOD_0FC7_REG_5,
 821   MOD_0FC7_REG_6,
 822   MOD_0FC7_REG_7,
 823   MOD_0FD7,
 824   MOD_0FE7_PREFIX_2,
 825   MOD_0FF0_PREFIX_3,
 826   MOD_0F382A_PREFIX_2,
 827   MOD_0F38F5_PREFIX_2,
 828   MOD_0F38F6_PREFIX_0,
 829   MOD_62_32BIT,
 830   MOD_C4_32BIT,
 831   MOD_C5_32BIT,
 832   MOD_VEX_0F12_PREFIX_0,
 833   MOD_VEX_0F13,
 834   MOD_VEX_0F16_PREFIX_0,
 835   MOD_VEX_0F17,
 836   MOD_VEX_0F2B,
 837   MOD_VEX_W_0_0F41_P_0_LEN_1,
 838   MOD_VEX_W_1_0F41_P_0_LEN_1,
 839   MOD_VEX_W_0_0F41_P_2_LEN_1,
 840   MOD_VEX_W_1_0F41_P_2_LEN_1,
 841   MOD_VEX_W_0_0F42_P_0_LEN_1,
 842   MOD_VEX_W_1_0F42_P_0_LEN_1,
 843   MOD_VEX_W_0_0F42_P_2_LEN_1,
 844   MOD_VEX_W_1_0F42_P_2_LEN_1,
 845   MOD_VEX_W_0_0F44_P_0_LEN_1,
 846   MOD_VEX_W_1_0F44_P_0_LEN_1,
 847   MOD_VEX_W_0_0F44_P_2_LEN_1,
 848   MOD_VEX_W_1_0F44_P_2_LEN_1,
 849   MOD_VEX_W_0_0F45_P_0_LEN_1,
 850   MOD_VEX_W_1_0F45_P_0_LEN_1,
 851   MOD_VEX_W_0_0F45_P_2_LEN_1,
 852   MOD_VEX_W_1_0F45_P_2_LEN_1,
 853   MOD_VEX_W_0_0F46_P_0_LEN_1,
 854   MOD_VEX_W_1_0F46_P_0_LEN_1,
 855   MOD_VEX_W_0_0F46_P_2_LEN_1,
 856   MOD_VEX_W_1_0F46_P_2_LEN_1,
 857   MOD_VEX_W_0_0F47_P_0_LEN_1,
 858   MOD_VEX_W_1_0F47_P_0_LEN_1,
 859   MOD_VEX_W_0_0F47_P_2_LEN_1,
 860   MOD_VEX_W_1_0F47_P_2_LEN_1,
 861   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 862   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 863   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 864   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 865   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 866   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 867   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 868   MOD_VEX_0F50,
 869   MOD_VEX_0F71_REG_2,
 870   MOD_VEX_0F71_REG_4,
 871   MOD_VEX_0F71_REG_6,
 872   MOD_VEX_0F72_REG_2,
 873   MOD_VEX_0F72_REG_4,
 874   MOD_VEX_0F72_REG_6,
 875   MOD_VEX_0F73_REG_2,
 876   MOD_VEX_0F73_REG_3,
 877   MOD_VEX_0F73_REG_6,
 878   MOD_VEX_0F73_REG_7,
 879   MOD_VEX_W_0_0F91_P_0_LEN_0,
 880   MOD_VEX_W_1_0F91_P_0_LEN_0,
 881   MOD_VEX_W_0_0F91_P_2_LEN_0,
 882   MOD_VEX_W_1_0F91_P_2_LEN_0,
 883   MOD_VEX_W_0_0F92_P_0_LEN_0,
 884   MOD_VEX_W_0_0F92_P_2_LEN_0,
 885   MOD_VEX_W_0_0F92_P_3_LEN_0,
 886   MOD_VEX_W_1_0F92_P_3_LEN_0,
 887   MOD_VEX_W_0_0F93_P_0_LEN_0,
 888   MOD_VEX_W_0_0F93_P_2_LEN_0,
 889   MOD_VEX_W_0_0F93_P_3_LEN_0,
 890   MOD_VEX_W_1_0F93_P_3_LEN_0,
 891   MOD_VEX_W_0_0F98_P_0_LEN_0,
 892   MOD_VEX_W_1_0F98_P_0_LEN_0,
 893   MOD_VEX_W_0_0F98_P_2_LEN_0,
 894   MOD_VEX_W_1_0F98_P_2_LEN_0,
 895   MOD_VEX_W_0_0F99_P_0_LEN_0,
 896   MOD_VEX_W_1_0F99_P_0_LEN_0,
 897   MOD_VEX_W_0_0F99_P_2_LEN_0,
 898   MOD_VEX_W_1_0F99_P_2_LEN_0,
 899   MOD_VEX_0FAE_REG_2,
 900   MOD_VEX_0FAE_REG_3,
 901   MOD_VEX_0FD7_PREFIX_2,
 902   MOD_VEX_0FE7_PREFIX_2,
 903   MOD_VEX_0FF0_PREFIX_3,
 904   MOD_VEX_0F381A_PREFIX_2,
 905   MOD_VEX_0F382A_PREFIX_2,
 906   MOD_VEX_0F382C_PREFIX_2,
 907   MOD_VEX_0F382D_PREFIX_2,
 908   MOD_VEX_0F382E_PREFIX_2,
 909   MOD_VEX_0F382F_PREFIX_2,
 910   MOD_VEX_0F385A_PREFIX_2,
 911   MOD_VEX_0F388C_PREFIX_2,
 912   MOD_VEX_0F388E_PREFIX_2,
 913   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 914   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 915   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 916   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 917   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 918   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 919   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 920   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 921
 922   MOD_EVEX_0F10_PREFIX_1,
 923   MOD_EVEX_0F10_PREFIX_3,
 924   MOD_EVEX_0F11_PREFIX_1,
 925   MOD_EVEX_0F11_PREFIX_3,
 926   MOD_EVEX_0F12_PREFIX_0,
 927   MOD_EVEX_0F16_PREFIX_0,
 928   MOD_EVEX_0F38C6_REG_1,
 929   MOD_EVEX_0F38C6_REG_2,
 930   MOD_EVEX_0F38C6_REG_5,
 931   MOD_EVEX_0F38C6_REG_6,
 932   MOD_EVEX_0F38C7_REG_1,
 933   MOD_EVEX_0F38C7_REG_2,
 934   MOD_EVEX_0F38C7_REG_5,
 935   MOD_EVEX_0F38C7_REG_6
 936 };
 937
 938 enum
 939 {
 940   RM_C6_REG_7 = 0,
 941   RM_C7_REG_7,
 942   RM_0F01_REG_0,
 943   RM_0F01_REG_1,
 944   RM_0F01_REG_2,
 945   RM_0F01_REG_3,
 946   RM_0F01_REG_5,
 947   RM_0F01_REG_7,
 948   RM_0F1E_MOD_3_REG_7,
 949   RM_0FAE_REG_6,
 950   RM_0FAE_REG_7
 951 };
 952
 953 enum
 954 {
 955   PREFIX_90 = 0,
 956   PREFIX_MOD_0_0F01_REG_5,
 957   PREFIX_MOD_3_0F01_REG_5_RM_0,
 958   PREFIX_MOD_3_0F01_REG_5_RM_2,
 959   PREFIX_0F09,
 960   PREFIX_0F10,
 961   PREFIX_0F11,
 962   PREFIX_0F12,
 963   PREFIX_0F16,
 964   PREFIX_0F1A,
 965   PREFIX_0F1B,
 966   PREFIX_0F1E,
 967   PREFIX_0F2A,
 968   PREFIX_0F2B,
 969   PREFIX_0F2C,
 970   PREFIX_0F2D,
 971   PREFIX_0F2E,
 972   PREFIX_0F2F,
 973   PREFIX_0F51,
 974   PREFIX_0F52,
 975   PREFIX_0F53,
 976   PREFIX_0F58,
 977   PREFIX_0F59,
 978   PREFIX_0F5A,
 979   PREFIX_0F5B,
 980   PREFIX_0F5C,
 981   PREFIX_0F5D,
 982   PREFIX_0F5E,
 983   PREFIX_0F5F,
 984   PREFIX_0F60,
 985   PREFIX_0F61,
 986   PREFIX_0F62,
 987   PREFIX_0F6C,
 988   PREFIX_0F6D,
 989   PREFIX_0F6F,
 990   PREFIX_0F70,
 991   PREFIX_0F73_REG_3,
 992   PREFIX_0F73_REG_7,
 993   PREFIX_0F78,
 994   PREFIX_0F79,
 995   PREFIX_0F7C,
 996   PREFIX_0F7D,
 997   PREFIX_0F7E,
 998   PREFIX_0F7F,
 999   PREFIX_0FAE_REG_0,
1000   PREFIX_0FAE_REG_1,
1001   PREFIX_0FAE_REG_2,
1002   PREFIX_0FAE_REG_3,
1003   PREFIX_MOD_0_0FAE_REG_4,
1004   PREFIX_MOD_3_0FAE_REG_4,
1005   PREFIX_MOD_0_0FAE_REG_5,
1006   PREFIX_MOD_3_0FAE_REG_5,
1007   PREFIX_0FAE_REG_6,
1008   PREFIX_0FAE_REG_7,
1009   PREFIX_0FB8,
1010   PREFIX_0FBC,
1011   PREFIX_0FBD,
1012   PREFIX_0FC2,
1013   PREFIX_MOD_0_0FC3,
1014   PREFIX_MOD_0_0FC7_REG_6,
1015   PREFIX_MOD_3_0FC7_REG_6,
1016   PREFIX_MOD_3_0FC7_REG_7,
1017   PREFIX_0FD0,
1018   PREFIX_0FD6,
1019   PREFIX_0FE6,
1020   PREFIX_0FE7,
1021   PREFIX_0FF0,
1022   PREFIX_0FF7,
1023   PREFIX_0F3810,
1024   PREFIX_0F3814,
1025   PREFIX_0F3815,
1026   PREFIX_0F3817,
1027   PREFIX_0F3820,
1028   PREFIX_0F3821,
1029   PREFIX_0F3822,
1030   PREFIX_0F3823,
1031   PREFIX_0F3824,
1032   PREFIX_0F3825,
1033   PREFIX_0F3828,
1034   PREFIX_0F3829,
1035   PREFIX_0F382A,
1036   PREFIX_0F382B,
1037   PREFIX_0F3830,
1038   PREFIX_0F3831,
1039   PREFIX_0F3832,
1040   PREFIX_0F3833,
1041   PREFIX_0F3834,
1042   PREFIX_0F3835,
1043   PREFIX_0F3837,
1044   PREFIX_0F3838,
1045   PREFIX_0F3839,
1046   PREFIX_0F383A,
1047   PREFIX_0F383B,
1048   PREFIX_0F383C,
1049   PREFIX_0F383D,
1050   PREFIX_0F383E,
1051   PREFIX_0F383F,
1052   PREFIX_0F3840,
1053   PREFIX_0F3841,
1054   PREFIX_0F3880,
1055   PREFIX_0F3881,
1056   PREFIX_0F3882,
1057   PREFIX_0F38C8,
1058   PREFIX_0F38C9,
1059   PREFIX_0F38CA,
1060   PREFIX_0F38CB,
1061   PREFIX_0F38CC,
1062   PREFIX_0F38CD,
1063   PREFIX_0F38CF,
1064   PREFIX_0F38DB,
1065   PREFIX_0F38DC,
1066   PREFIX_0F38DD,
1067   PREFIX_0F38DE,
1068   PREFIX_0F38DF,
1069   PREFIX_0F38F0,
1070   PREFIX_0F38F1,
1071   PREFIX_0F38F5,
1072   PREFIX_0F38F6,
1073   PREFIX_0F3A08,
1074   PREFIX_0F3A09,
1075   PREFIX_0F3A0A,
1076   PREFIX_0F3A0B,
1077   PREFIX_0F3A0C,
1078   PREFIX_0F3A0D,
1079   PREFIX_0F3A0E,
1080   PREFIX_0F3A14,
1081   PREFIX_0F3A15,
1082   PREFIX_0F3A16,
1083   PREFIX_0F3A17,
1084   PREFIX_0F3A20,
1085   PREFIX_0F3A21,
1086   PREFIX_0F3A22,
1087   PREFIX_0F3A40,
1088   PREFIX_0F3A41,
1089   PREFIX_0F3A42,
1090   PREFIX_0F3A44,
1091   PREFIX_0F3A60,
1092   PREFIX_0F3A61,
1093   PREFIX_0F3A62,
1094   PREFIX_0F3A63,
1095   PREFIX_0F3ACC,
1096   PREFIX_0F3ACE,
1097   PREFIX_0F3ACF,
1098   PREFIX_0F3ADF,
1099   PREFIX_VEX_0F10,
1100   PREFIX_VEX_0F11,
1101   PREFIX_VEX_0F12,
1102   PREFIX_VEX_0F16,
1103   PREFIX_VEX_0F2A,
1104   PREFIX_VEX_0F2C,
1105   PREFIX_VEX_0F2D,
1106   PREFIX_VEX_0F2E,
1107   PREFIX_VEX_0F2F,
1108   PREFIX_VEX_0F41,
1109   PREFIX_VEX_0F42,
1110   PREFIX_VEX_0F44,
1111   PREFIX_VEX_0F45,
1112   PREFIX_VEX_0F46,
1113   PREFIX_VEX_0F47,
1114   PREFIX_VEX_0F4A,
1115   PREFIX_VEX_0F4B,
1116   PREFIX_VEX_0F51,
1117   PREFIX_VEX_0F52,
1118   PREFIX_VEX_0F53,
1119   PREFIX_VEX_0F58,
1120   PREFIX_VEX_0F59,
1121   PREFIX_VEX_0F5A,
1122   PREFIX_VEX_0F5B,
1123   PREFIX_VEX_0F5C,
1124   PREFIX_VEX_0F5D,
1125   PREFIX_VEX_0F5E,
1126   PREFIX_VEX_0F5F,
1127   PREFIX_VEX_0F60,
1128   PREFIX_VEX_0F61,
1129   PREFIX_VEX_0F62,
1130   PREFIX_VEX_0F63,
1131   PREFIX_VEX_0F64,
1132   PREFIX_VEX_0F65,
1133   PREFIX_VEX_0F66,
1134   PREFIX_VEX_0F67,
1135   PREFIX_VEX_0F68,
1136   PREFIX_VEX_0F69,
1137   PREFIX_VEX_0F6A,
1138   PREFIX_VEX_0F6B,
1139   PREFIX_VEX_0F6C,
1140   PREFIX_VEX_0F6D,
1141   PREFIX_VEX_0F6E,
1142   PREFIX_VEX_0F6F,
1143   PREFIX_VEX_0F70,
1144   PREFIX_VEX_0F71_REG_2,
1145   PREFIX_VEX_0F71_REG_4,
1146   PREFIX_VEX_0F71_REG_6,
1147   PREFIX_VEX_0F72_REG_2,
1148   PREFIX_VEX_0F72_REG_4,
1149   PREFIX_VEX_0F72_REG_6,
1150   PREFIX_VEX_0F73_REG_2,
1151   PREFIX_VEX_0F73_REG_3,
1152   PREFIX_VEX_0F73_REG_6,
1153   PREFIX_VEX_0F73_REG_7,
1154   PREFIX_VEX_0F74,
1155   PREFIX_VEX_0F75,
1156   PREFIX_VEX_0F76,
1157   PREFIX_VEX_0F77,
1158   PREFIX_VEX_0F7C,
1159   PREFIX_VEX_0F7D,
1160   PREFIX_VEX_0F7E,
1161   PREFIX_VEX_0F7F,
1162   PREFIX_VEX_0F90,
1163   PREFIX_VEX_0F91,
1164   PREFIX_VEX_0F92,
1165   PREFIX_VEX_0F93,
1166   PREFIX_VEX_0F98,
1167   PREFIX_VEX_0F99,
1168   PREFIX_VEX_0FC2,
1169   PREFIX_VEX_0FC4,
1170   PREFIX_VEX_0FC5,
1171   PREFIX_VEX_0FD0,
1172   PREFIX_VEX_0FD1,
1173   PREFIX_VEX_0FD2,
1174   PREFIX_VEX_0FD3,
1175   PREFIX_VEX_0FD4,
1176   PREFIX_VEX_0FD5,
1177   PREFIX_VEX_0FD6,
1178   PREFIX_VEX_0FD7,
1179   PREFIX_VEX_0FD8,
1180   PREFIX_VEX_0FD9,
1181   PREFIX_VEX_0FDA,
1182   PREFIX_VEX_0FDB,
1183   PREFIX_VEX_0FDC,
1184   PREFIX_VEX_0FDD,
1185   PREFIX_VEX_0FDE,
1186   PREFIX_VEX_0FDF,
1187   PREFIX_VEX_0FE0,
1188   PREFIX_VEX_0FE1,
1189   PREFIX_VEX_0FE2,
1190   PREFIX_VEX_0FE3,
1191   PREFIX_VEX_0FE4,
1192   PREFIX_VEX_0FE5,
1193   PREFIX_VEX_0FE6,
1194   PREFIX_VEX_0FE7,
1195   PREFIX_VEX_0FE8,
1196   PREFIX_VEX_0FE9,
1197   PREFIX_VEX_0FEA,
1198   PREFIX_VEX_0FEB,
1199   PREFIX_VEX_0FEC,
1200   PREFIX_VEX_0FED,
1201   PREFIX_VEX_0FEE,
1202   PREFIX_VEX_0FEF,
1203   PREFIX_VEX_0FF0,
1204   PREFIX_VEX_0FF1,
1205   PREFIX_VEX_0FF2,
1206   PREFIX_VEX_0FF3,
1207   PREFIX_VEX_0FF4,
1208   PREFIX_VEX_0FF5,
1209   PREFIX_VEX_0FF6,
1210   PREFIX_VEX_0FF7,
1211   PREFIX_VEX_0FF8,
1212   PREFIX_VEX_0FF9,
1213   PREFIX_VEX_0FFA,
1214   PREFIX_VEX_0FFB,
1215   PREFIX_VEX_0FFC,
1216   PREFIX_VEX_0FFD,
1217   PREFIX_VEX_0FFE,
1218   PREFIX_VEX_0F3800,
1219   PREFIX_VEX_0F3801,
1220   PREFIX_VEX_0F3802,
1221   PREFIX_VEX_0F3803,
1222   PREFIX_VEX_0F3804,
1223   PREFIX_VEX_0F3805,
1224   PREFIX_VEX_0F3806,
1225   PREFIX_VEX_0F3807,
1226   PREFIX_VEX_0F3808,
1227   PREFIX_VEX_0F3809,
1228   PREFIX_VEX_0F380A,
1229   PREFIX_VEX_0F380B,
1230   PREFIX_VEX_0F380C,
1231   PREFIX_VEX_0F380D,
1232   PREFIX_VEX_0F380E,
1233   PREFIX_VEX_0F380F,
1234   PREFIX_VEX_0F3813,
1235   PREFIX_VEX_0F3816,
1236   PREFIX_VEX_0F3817,
1237   PREFIX_VEX_0F3818,
1238   PREFIX_VEX_0F3819,
1239   PREFIX_VEX_0F381A,
1240   PREFIX_VEX_0F381C,
1241   PREFIX_VEX_0F381D,
1242   PREFIX_VEX_0F381E,
1243   PREFIX_VEX_0F3820,
1244   PREFIX_VEX_0F3821,
1245   PREFIX_VEX_0F3822,
1246   PREFIX_VEX_0F3823,
1247   PREFIX_VEX_0F3824,
1248   PREFIX_VEX_0F3825,
1249   PREFIX_VEX_0F3828,
1250   PREFIX_VEX_0F3829,
1251   PREFIX_VEX_0F382A,
1252   PREFIX_VEX_0F382B,
1253   PREFIX_VEX_0F382C,
1254   PREFIX_VEX_0F382D,
1255   PREFIX_VEX_0F382E,
1256   PREFIX_VEX_0F382F,
1257   PREFIX_VEX_0F3830,
1258   PREFIX_VEX_0F3831,
1259   PREFIX_VEX_0F3832,
1260   PREFIX_VEX_0F3833,
1261   PREFIX_VEX_0F3834,
1262   PREFIX_VEX_0F3835,
1263   PREFIX_VEX_0F3836,
1264   PREFIX_VEX_0F3837,
1265   PREFIX_VEX_0F3838,
1266   PREFIX_VEX_0F3839,
1267   PREFIX_VEX_0F383A,
1268   PREFIX_VEX_0F383B,
1269   PREFIX_VEX_0F383C,
1270   PREFIX_VEX_0F383D,
1271   PREFIX_VEX_0F383E,
1272   PREFIX_VEX_0F383F,
1273   PREFIX_VEX_0F3840,
1274   PREFIX_VEX_0F3841,
1275   PREFIX_VEX_0F3845,
1276   PREFIX_VEX_0F3846,
1277   PREFIX_VEX_0F3847,
1278   PREFIX_VEX_0F3858,
1279   PREFIX_VEX_0F3859,
1280   PREFIX_VEX_0F385A,
1281   PREFIX_VEX_0F3878,
1282   PREFIX_VEX_0F3879,
1283   PREFIX_VEX_0F388C,
1284   PREFIX_VEX_0F388E,
1285   PREFIX_VEX_0F3890,
1286   PREFIX_VEX_0F3891,
1287   PREFIX_VEX_0F3892,
1288   PREFIX_VEX_0F3893,
1289   PREFIX_VEX_0F3896,
1290   PREFIX_VEX_0F3897,
1291   PREFIX_VEX_0F3898,
1292   PREFIX_VEX_0F3899,
1293   PREFIX_VEX_0F389A,
1294   PREFIX_VEX_0F389B,
1295   PREFIX_VEX_0F389C,
1296   PREFIX_VEX_0F389D,
1297   PREFIX_VEX_0F389E,
1298   PREFIX_VEX_0F389F,
1299   PREFIX_VEX_0F38A6,
1300   PREFIX_VEX_0F38A7,
1301   PREFIX_VEX_0F38A8,
1302   PREFIX_VEX_0F38A9,
1303   PREFIX_VEX_0F38AA,
1304   PREFIX_VEX_0F38AB,
1305   PREFIX_VEX_0F38AC,
1306   PREFIX_VEX_0F38AD,
1307   PREFIX_VEX_0F38AE,
1308   PREFIX_VEX_0F38AF,
1309   PREFIX_VEX_0F38B6,
1310   PREFIX_VEX_0F38B7,
1311   PREFIX_VEX_0F38B8,
1312   PREFIX_VEX_0F38B9,
1313   PREFIX_VEX_0F38BA,
1314   PREFIX_VEX_0F38BB,
1315   PREFIX_VEX_0F38BC,
1316   PREFIX_VEX_0F38BD,
1317   PREFIX_VEX_0F38BE,
1318   PREFIX_VEX_0F38BF,
1319   PREFIX_VEX_0F38CF,
1320   PREFIX_VEX_0F38DB,
1321   PREFIX_VEX_0F38DC,
1322   PREFIX_VEX_0F38DD,
1323   PREFIX_VEX_0F38DE,
1324   PREFIX_VEX_0F38DF,
1325   PREFIX_VEX_0F38F2,
1326   PREFIX_VEX_0F38F3_REG_1,
1327   PREFIX_VEX_0F38F3_REG_2,
1328   PREFIX_VEX_0F38F3_REG_3,
1329   PREFIX_VEX_0F38F5,
1330   PREFIX_VEX_0F38F6,
1331   PREFIX_VEX_0F38F7,
1332   PREFIX_VEX_0F3A00,
1333   PREFIX_VEX_0F3A01,
1334   PREFIX_VEX_0F3A02,
1335   PREFIX_VEX_0F3A04,
1336   PREFIX_VEX_0F3A05,
1337   PREFIX_VEX_0F3A06,
1338   PREFIX_VEX_0F3A08,
1339   PREFIX_VEX_0F3A09,
1340   PREFIX_VEX_0F3A0A,
1341   PREFIX_VEX_0F3A0B,
1342   PREFIX_VEX_0F3A0C,
1343   PREFIX_VEX_0F3A0D,
1344   PREFIX_VEX_0F3A0E,
1345   PREFIX_VEX_0F3A0F,
1346   PREFIX_VEX_0F3A14,
1347   PREFIX_VEX_0F3A15,
1348   PREFIX_VEX_0F3A16,
1349   PREFIX_VEX_0F3A17,
1350   PREFIX_VEX_0F3A18,
1351   PREFIX_VEX_0F3A19,
1352   PREFIX_VEX_0F3A1D,
1353   PREFIX_VEX_0F3A20,
1354   PREFIX_VEX_0F3A21,
1355   PREFIX_VEX_0F3A22,
1356   PREFIX_VEX_0F3A30,
1357   PREFIX_VEX_0F3A31,
1358   PREFIX_VEX_0F3A32,
1359   PREFIX_VEX_0F3A33,
1360   PREFIX_VEX_0F3A38,
1361   PREFIX_VEX_0F3A39,
1362   PREFIX_VEX_0F3A40,
1363   PREFIX_VEX_0F3A41,
1364   PREFIX_VEX_0F3A42,
1365   PREFIX_VEX_0F3A44,
1366   PREFIX_VEX_0F3A46,
1367   PREFIX_VEX_0F3A48,
1368   PREFIX_VEX_0F3A49,
1369   PREFIX_VEX_0F3A4A,
1370   PREFIX_VEX_0F3A4B,
1371   PREFIX_VEX_0F3A4C,
1372   PREFIX_VEX_0F3A5C,
1373   PREFIX_VEX_0F3A5D,
1374   PREFIX_VEX_0F3A5E,
1375   PREFIX_VEX_0F3A5F,
1376   PREFIX_VEX_0F3A60,
1377   PREFIX_VEX_0F3A61,
1378   PREFIX_VEX_0F3A62,
1379   PREFIX_VEX_0F3A63,
1380   PREFIX_VEX_0F3A68,
1381   PREFIX_VEX_0F3A69,
1382   PREFIX_VEX_0F3A6A,
1383   PREFIX_VEX_0F3A6B,
1384   PREFIX_VEX_0F3A6C,
1385   PREFIX_VEX_0F3A6D,
1386   PREFIX_VEX_0F3A6E,
1387   PREFIX_VEX_0F3A6F,
1388   PREFIX_VEX_0F3A78,
1389   PREFIX_VEX_0F3A79,
1390   PREFIX_VEX_0F3A7A,
1391   PREFIX_VEX_0F3A7B,
1392   PREFIX_VEX_0F3A7C,
1393   PREFIX_VEX_0F3A7D,
1394   PREFIX_VEX_0F3A7E,
1395   PREFIX_VEX_0F3A7F,
1396   PREFIX_VEX_0F3ACE,
1397   PREFIX_VEX_0F3ACF,
1398   PREFIX_VEX_0F3ADF,
1399   PREFIX_VEX_0F3AF0,
1400
1401   PREFIX_EVEX_0F10,
1402   PREFIX_EVEX_0F11,
1403   PREFIX_EVEX_0F12,
1404   PREFIX_EVEX_0F13,
1405   PREFIX_EVEX_0F14,
1406   PREFIX_EVEX_0F15,
1407   PREFIX_EVEX_0F16,
1408   PREFIX_EVEX_0F17,
1409   PREFIX_EVEX_0F28,
1410   PREFIX_EVEX_0F29,
1411   PREFIX_EVEX_0F2A,
1412   PREFIX_EVEX_0F2B,
1413   PREFIX_EVEX_0F2C,
1414   PREFIX_EVEX_0F2D,
1415   PREFIX_EVEX_0F2E,
1416   PREFIX_EVEX_0F2F,
1417   PREFIX_EVEX_0F51,
1418   PREFIX_EVEX_0F54,
1419   PREFIX_EVEX_0F55,
1420   PREFIX_EVEX_0F56,
1421   PREFIX_EVEX_0F57,
1422   PREFIX_EVEX_0F58,
1423   PREFIX_EVEX_0F59,
1424   PREFIX_EVEX_0F5A,
1425   PREFIX_EVEX_0F5B,
1426   PREFIX_EVEX_0F5C,
1427   PREFIX_EVEX_0F5D,
1428   PREFIX_EVEX_0F5E,
1429   PREFIX_EVEX_0F5F,
1430   PREFIX_EVEX_0F60,
1431   PREFIX_EVEX_0F61,
1432   PREFIX_EVEX_0F62,
1433   PREFIX_EVEX_0F63,
1434   PREFIX_EVEX_0F64,
1435   PREFIX_EVEX_0F65,
1436   PREFIX_EVEX_0F66,
1437   PREFIX_EVEX_0F67,
1438   PREFIX_EVEX_0F68,
1439   PREFIX_EVEX_0F69,
1440   PREFIX_EVEX_0F6A,
1441   PREFIX_EVEX_0F6B,
1442   PREFIX_EVEX_0F6C,
1443   PREFIX_EVEX_0F6D,
1444   PREFIX_EVEX_0F6E,
1445   PREFIX_EVEX_0F6F,
1446   PREFIX_EVEX_0F70,
1447   PREFIX_EVEX_0F71_REG_2,
1448   PREFIX_EVEX_0F71_REG_4,
1449   PREFIX_EVEX_0F71_REG_6,
1450   PREFIX_EVEX_0F72_REG_0,
1451   PREFIX_EVEX_0F72_REG_1,
1452   PREFIX_EVEX_0F72_REG_2,
1453   PREFIX_EVEX_0F72_REG_4,
1454   PREFIX_EVEX_0F72_REG_6,
1455   PREFIX_EVEX_0F73_REG_2,
1456   PREFIX_EVEX_0F73_REG_3,
1457   PREFIX_EVEX_0F73_REG_6,
1458   PREFIX_EVEX_0F73_REG_7,
1459   PREFIX_EVEX_0F74,
1460   PREFIX_EVEX_0F75,
1461   PREFIX_EVEX_0F76,
1462   PREFIX_EVEX_0F78,
1463   PREFIX_EVEX_0F79,
1464   PREFIX_EVEX_0F7A,
1465   PREFIX_EVEX_0F7B,
1466   PREFIX_EVEX_0F7E,
1467   PREFIX_EVEX_0F7F,
1468   PREFIX_EVEX_0FC2,
1469   PREFIX_EVEX_0FC4,
1470   PREFIX_EVEX_0FC5,
1471   PREFIX_EVEX_0FC6,
1472   PREFIX_EVEX_0FD1,
1473   PREFIX_EVEX_0FD2,
1474   PREFIX_EVEX_0FD3,
1475   PREFIX_EVEX_0FD4,
1476   PREFIX_EVEX_0FD5,
1477   PREFIX_EVEX_0FD6,
1478   PREFIX_EVEX_0FD8,
1479   PREFIX_EVEX_0FD9,
1480   PREFIX_EVEX_0FDA,
1481   PREFIX_EVEX_0FDB,
1482   PREFIX_EVEX_0FDC,
1483   PREFIX_EVEX_0FDD,
1484   PREFIX_EVEX_0FDE,
1485   PREFIX_EVEX_0FDF,
1486   PREFIX_EVEX_0FE0,
1487   PREFIX_EVEX_0FE1,
1488   PREFIX_EVEX_0FE2,
1489   PREFIX_EVEX_0FE3,
1490   PREFIX_EVEX_0FE4,
1491   PREFIX_EVEX_0FE5,
1492   PREFIX_EVEX_0FE6,
1493   PREFIX_EVEX_0FE7,
1494   PREFIX_EVEX_0FE8,
1495   PREFIX_EVEX_0FE9,
1496   PREFIX_EVEX_0FEA,
1497   PREFIX_EVEX_0FEB,
1498   PREFIX_EVEX_0FEC,
1499   PREFIX_EVEX_0FED,
1500   PREFIX_EVEX_0FEE,
1501   PREFIX_EVEX_0FEF,
1502   PREFIX_EVEX_0FF1,
1503   PREFIX_EVEX_0FF2,
1504   PREFIX_EVEX_0FF3,
1505   PREFIX_EVEX_0FF4,
1506   PREFIX_EVEX_0FF5,
1507   PREFIX_EVEX_0FF6,
1508   PREFIX_EVEX_0FF8,
1509   PREFIX_EVEX_0FF9,
1510   PREFIX_EVEX_0FFA,
1511   PREFIX_EVEX_0FFB,
1512   PREFIX_EVEX_0FFC,
1513   PREFIX_EVEX_0FFD,
1514   PREFIX_EVEX_0FFE,
1515   PREFIX_EVEX_0F3800,
1516   PREFIX_EVEX_0F3804,
1517   PREFIX_EVEX_0F380B,
1518   PREFIX_EVEX_0F380C,
1519   PREFIX_EVEX_0F380D,
1520   PREFIX_EVEX_0F3810,
1521   PREFIX_EVEX_0F3811,
1522   PREFIX_EVEX_0F3812,
1523   PREFIX_EVEX_0F3813,
1524   PREFIX_EVEX_0F3814,
1525   PREFIX_EVEX_0F3815,
1526   PREFIX_EVEX_0F3816,
1527   PREFIX_EVEX_0F3818,
1528   PREFIX_EVEX_0F3819,
1529   PREFIX_EVEX_0F381A,
1530   PREFIX_EVEX_0F381B,
1531   PREFIX_EVEX_0F381C,
1532   PREFIX_EVEX_0F381D,
1533   PREFIX_EVEX_0F381E,
1534   PREFIX_EVEX_0F381F,
1535   PREFIX_EVEX_0F3820,
1536   PREFIX_EVEX_0F3821,
1537   PREFIX_EVEX_0F3822,
1538   PREFIX_EVEX_0F3823,
1539   PREFIX_EVEX_0F3824,
1540   PREFIX_EVEX_0F3825,
1541   PREFIX_EVEX_0F3826,
1542   PREFIX_EVEX_0F3827,
1543   PREFIX_EVEX_0F3828,
1544   PREFIX_EVEX_0F3829,
1545   PREFIX_EVEX_0F382A,
1546   PREFIX_EVEX_0F382B,
1547   PREFIX_EVEX_0F382C,
1548   PREFIX_EVEX_0F382D,
1549   PREFIX_EVEX_0F3830,
1550   PREFIX_EVEX_0F3831,
1551   PREFIX_EVEX_0F3832,
1552   PREFIX_EVEX_0F3833,
1553   PREFIX_EVEX_0F3834,
1554   PREFIX_EVEX_0F3835,
1555   PREFIX_EVEX_0F3836,
1556   PREFIX_EVEX_0F3837,
1557   PREFIX_EVEX_0F3838,
1558   PREFIX_EVEX_0F3839,
1559   PREFIX_EVEX_0F383A,
1560   PREFIX_EVEX_0F383B,
1561   PREFIX_EVEX_0F383C,
1562   PREFIX_EVEX_0F383D,
1563   PREFIX_EVEX_0F383E,
1564   PREFIX_EVEX_0F383F,
1565   PREFIX_EVEX_0F3840,
1566   PREFIX_EVEX_0F3842,
1567   PREFIX_EVEX_0F3843,
1568   PREFIX_EVEX_0F3844,
1569   PREFIX_EVEX_0F3845,
1570   PREFIX_EVEX_0F3846,
1571   PREFIX_EVEX_0F3847,
1572   PREFIX_EVEX_0F384C,
1573   PREFIX_EVEX_0F384D,
1574   PREFIX_EVEX_0F384E,
1575   PREFIX_EVEX_0F384F,
1576   PREFIX_EVEX_0F3850,
1577   PREFIX_EVEX_0F3851,
1578   PREFIX_EVEX_0F3852,
1579   PREFIX_EVEX_0F3853,
1580   PREFIX_EVEX_0F3854,
1581   PREFIX_EVEX_0F3855,
1582   PREFIX_EVEX_0F3858,
1583   PREFIX_EVEX_0F3859,
1584   PREFIX_EVEX_0F385A,
1585   PREFIX_EVEX_0F385B,
1586   PREFIX_EVEX_0F3862,
1587   PREFIX_EVEX_0F3863,
1588   PREFIX_EVEX_0F3864,
1589   PREFIX_EVEX_0F3865,
1590   PREFIX_EVEX_0F3866,
1591   PREFIX_EVEX_0F3870,
1592   PREFIX_EVEX_0F3871,
1593   PREFIX_EVEX_0F3872,
1594   PREFIX_EVEX_0F3873,
1595   PREFIX_EVEX_0F3875,
1596   PREFIX_EVEX_0F3876,
1597   PREFIX_EVEX_0F3877,
1598   PREFIX_EVEX_0F3878,
1599   PREFIX_EVEX_0F3879,
1600   PREFIX_EVEX_0F387A,
1601   PREFIX_EVEX_0F387B,
1602   PREFIX_EVEX_0F387C,
1603   PREFIX_EVEX_0F387D,
1604   PREFIX_EVEX_0F387E,
1605   PREFIX_EVEX_0F387F,
1606   PREFIX_EVEX_0F3883,
1607   PREFIX_EVEX_0F3888,
1608   PREFIX_EVEX_0F3889,
1609   PREFIX_EVEX_0F388A,
1610   PREFIX_EVEX_0F388B,
1611   PREFIX_EVEX_0F388D,
1612   PREFIX_EVEX_0F388F,
1613   PREFIX_EVEX_0F3890,
1614   PREFIX_EVEX_0F3891,
1615   PREFIX_EVEX_0F3892,
1616   PREFIX_EVEX_0F3893,
1617   PREFIX_EVEX_0F3896,
1618   PREFIX_EVEX_0F3897,
1619   PREFIX_EVEX_0F3898,
1620   PREFIX_EVEX_0F3899,
1621   PREFIX_EVEX_0F389A,
1622   PREFIX_EVEX_0F389B,
1623   PREFIX_EVEX_0F389C,
1624   PREFIX_EVEX_0F389D,
1625   PREFIX_EVEX_0F389E,
1626   PREFIX_EVEX_0F389F,
1627   PREFIX_EVEX_0F38A0,
1628   PREFIX_EVEX_0F38A1,
1629   PREFIX_EVEX_0F38A2,
1630   PREFIX_EVEX_0F38A3,
1631   PREFIX_EVEX_0F38A6,
1632   PREFIX_EVEX_0F38A7,
1633   PREFIX_EVEX_0F38A8,
1634   PREFIX_EVEX_0F38A9,
1635   PREFIX_EVEX_0F38AA,
1636   PREFIX_EVEX_0F38AB,
1637   PREFIX_EVEX_0F38AC,
1638   PREFIX_EVEX_0F38AD,
1639   PREFIX_EVEX_0F38AE,
1640   PREFIX_EVEX_0F38AF,
1641   PREFIX_EVEX_0F38B4,
1642   PREFIX_EVEX_0F38B5,
1643   PREFIX_EVEX_0F38B6,
1644   PREFIX_EVEX_0F38B7,
1645   PREFIX_EVEX_0F38B8,
1646   PREFIX_EVEX_0F38B9,
1647   PREFIX_EVEX_0F38BA,
1648   PREFIX_EVEX_0F38BB,
1649   PREFIX_EVEX_0F38BC,
1650   PREFIX_EVEX_0F38BD,
1651   PREFIX_EVEX_0F38BE,
1652   PREFIX_EVEX_0F38BF,
1653   PREFIX_EVEX_0F38C4,
1654   PREFIX_EVEX_0F38C6_REG_1,
1655   PREFIX_EVEX_0F38C6_REG_2,
1656   PREFIX_EVEX_0F38C6_REG_5,
1657   PREFIX_EVEX_0F38C6_REG_6,
1658   PREFIX_EVEX_0F38C7_REG_1,
1659   PREFIX_EVEX_0F38C7_REG_2,
1660   PREFIX_EVEX_0F38C7_REG_5,
1661   PREFIX_EVEX_0F38C7_REG_6,
1662   PREFIX_EVEX_0F38C8,
1663   PREFIX_EVEX_0F38CA,
1664   PREFIX_EVEX_0F38CB,
1665   PREFIX_EVEX_0F38CC,
1666   PREFIX_EVEX_0F38CD,
1667   PREFIX_EVEX_0F38CF,
1668   PREFIX_EVEX_0F38DC,
1669   PREFIX_EVEX_0F38DD,
1670   PREFIX_EVEX_0F38DE,
1671   PREFIX_EVEX_0F38DF,
1672
1673   PREFIX_EVEX_0F3A00,
1674   PREFIX_EVEX_0F3A01,
1675   PREFIX_EVEX_0F3A03,
1676   PREFIX_EVEX_0F3A04,
1677   PREFIX_EVEX_0F3A05,
1678   PREFIX_EVEX_0F3A08,
1679   PREFIX_EVEX_0F3A09,
1680   PREFIX_EVEX_0F3A0A,
1681   PREFIX_EVEX_0F3A0B,
1682   PREFIX_EVEX_0F3A0F,
1683   PREFIX_EVEX_0F3A14,
1684   PREFIX_EVEX_0F3A15,
1685   PREFIX_EVEX_0F3A16,
1686   PREFIX_EVEX_0F3A17,
1687   PREFIX_EVEX_0F3A18,
1688   PREFIX_EVEX_0F3A19,
1689   PREFIX_EVEX_0F3A1A,
1690   PREFIX_EVEX_0F3A1B,
1691   PREFIX_EVEX_0F3A1D,
1692   PREFIX_EVEX_0F3A1E,
1693   PREFIX_EVEX_0F3A1F,
1694   PREFIX_EVEX_0F3A20,
1695   PREFIX_EVEX_0F3A21,
1696   PREFIX_EVEX_0F3A22,
1697   PREFIX_EVEX_0F3A23,
1698   PREFIX_EVEX_0F3A25,
1699   PREFIX_EVEX_0F3A26,
1700   PREFIX_EVEX_0F3A27,
1701   PREFIX_EVEX_0F3A38,
1702   PREFIX_EVEX_0F3A39,
1703   PREFIX_EVEX_0F3A3A,
1704   PREFIX_EVEX_0F3A3B,
1705   PREFIX_EVEX_0F3A3E,
1706   PREFIX_EVEX_0F3A3F,
1707   PREFIX_EVEX_0F3A42,
1708   PREFIX_EVEX_0F3A43,
1709   PREFIX_EVEX_0F3A44,
1710   PREFIX_EVEX_0F3A50,
1711   PREFIX_EVEX_0F3A51,
1712   PREFIX_EVEX_0F3A54,
1713   PREFIX_EVEX_0F3A55,
1714   PREFIX_EVEX_0F3A56,
1715   PREFIX_EVEX_0F3A57,
1716   PREFIX_EVEX_0F3A66,
1717   PREFIX_EVEX_0F3A67,
1718   PREFIX_EVEX_0F3A70,
1719   PREFIX_EVEX_0F3A71,
1720   PREFIX_EVEX_0F3A72,
1721   PREFIX_EVEX_0F3A73,
1722   PREFIX_EVEX_0F3ACE,
1723   PREFIX_EVEX_0F3ACF
1724 };
1725
1726 enum
1727 {
1728   X86_64_06 = 0,
1729   X86_64_07,
1730   X86_64_0D,
1731   X86_64_16,
1732   X86_64_17,
1733   X86_64_1E,
1734   X86_64_1F,
1735   X86_64_27,
1736   X86_64_2F,
1737   X86_64_37,
1738   X86_64_3F,
1739   X86_64_60,
1740   X86_64_61,
1741   X86_64_62,
1742   X86_64_63,
1743   X86_64_6D,
1744   X86_64_6F,
1745   X86_64_82,
1746   X86_64_9A,
1747   X86_64_C4,
1748   X86_64_C5,
1749   X86_64_CE,
1750   X86_64_D4,
1751   X86_64_D5,
1752   X86_64_E8,
1753   X86_64_E9,
1754   X86_64_EA,
1755   X86_64_0F01_REG_0,
1756   X86_64_0F01_REG_1,
1757   X86_64_0F01_REG_2,
1758   X86_64_0F01_REG_3
1759 };
1760
1761 enum
1762 {
1763   THREE_BYTE_0F38 = 0,
1764   THREE_BYTE_0F3A
1765 };
1766
1767 enum
1768 {
1769   XOP_08 = 0,
1770   XOP_09,
1771   XOP_0A
1772 };
1773
1774 enum
1775 {
1776   VEX_0F = 0,
1777   VEX_0F38,
1778   VEX_0F3A
1779 };
1780
1781 enum
1782 {
1783   EVEX_0F = 0,
1784   EVEX_0F38,
1785   EVEX_0F3A
1786 };
1787
1788 enum
1789 {
1790   VEX_LEN_0F10_P_1 = 0,
1791   VEX_LEN_0F10_P_3,
1792   VEX_LEN_0F11_P_1,
1793   VEX_LEN_0F11_P_3,
1794   VEX_LEN_0F12_P_0_M_0,
1795   VEX_LEN_0F12_P_0_M_1,
1796   VEX_LEN_0F12_P_2,
1797   VEX_LEN_0F13_M_0,
1798   VEX_LEN_0F16_P_0_M_0,
1799   VEX_LEN_0F16_P_0_M_1,
1800   VEX_LEN_0F16_P_2,
1801   VEX_LEN_0F17_M_0,
1802   VEX_LEN_0F2A_P_1,
1803   VEX_LEN_0F2A_P_3,
1804   VEX_LEN_0F2C_P_1,
1805   VEX_LEN_0F2C_P_3,
1806   VEX_LEN_0F2D_P_1,
1807   VEX_LEN_0F2D_P_3,
1808   VEX_LEN_0F2E_P_0,
1809   VEX_LEN_0F2E_P_2,
1810   VEX_LEN_0F2F_P_0,
1811   VEX_LEN_0F2F_P_2,
1812   VEX_LEN_0F41_P_0,
1813   VEX_LEN_0F41_P_2,
1814   VEX_LEN_0F42_P_0,
1815   VEX_LEN_0F42_P_2,
1816   VEX_LEN_0F44_P_0,
1817   VEX_LEN_0F44_P_2,
1818   VEX_LEN_0F45_P_0,
1819   VEX_LEN_0F45_P_2,
1820   VEX_LEN_0F46_P_0,
1821   VEX_LEN_0F46_P_2,
1822   VEX_LEN_0F47_P_0,
1823   VEX_LEN_0F47_P_2,
1824   VEX_LEN_0F4A_P_0,
1825   VEX_LEN_0F4A_P_2,
1826   VEX_LEN_0F4B_P_0,
1827   VEX_LEN_0F4B_P_2,
1828   VEX_LEN_0F51_P_1,
1829   VEX_LEN_0F51_P_3,
1830   VEX_LEN_0F52_P_1,
1831   VEX_LEN_0F53_P_1,
1832   VEX_LEN_0F58_P_1,
1833   VEX_LEN_0F58_P_3,
1834   VEX_LEN_0F59_P_1,
1835   VEX_LEN_0F59_P_3,
1836   VEX_LEN_0F5A_P_1,
1837   VEX_LEN_0F5A_P_3,
1838   VEX_LEN_0F5C_P_1,
1839   VEX_LEN_0F5C_P_3,
1840   VEX_LEN_0F5D_P_1,
1841   VEX_LEN_0F5D_P_3,
1842   VEX_LEN_0F5E_P_1,
1843   VEX_LEN_0F5E_P_3,
1844   VEX_LEN_0F5F_P_1,
1845   VEX_LEN_0F5F_P_3,
1846   VEX_LEN_0F6E_P_2,
1847   VEX_LEN_0F7E_P_1,
1848   VEX_LEN_0F7E_P_2,
1849   VEX_LEN_0F90_P_0,
1850   VEX_LEN_0F90_P_2,
1851   VEX_LEN_0F91_P_0,
1852   VEX_LEN_0F91_P_2,
1853   VEX_LEN_0F92_P_0,
1854   VEX_LEN_0F92_P_2,
1855   VEX_LEN_0F92_P_3,
1856   VEX_LEN_0F93_P_0,
1857   VEX_LEN_0F93_P_2,
1858   VEX_LEN_0F93_P_3,
1859   VEX_LEN_0F98_P_0,
1860   VEX_LEN_0F98_P_2,
1861   VEX_LEN_0F99_P_0,
1862   VEX_LEN_0F99_P_2,
1863   VEX_LEN_0FAE_R_2_M_0,
1864   VEX_LEN_0FAE_R_3_M_0,
1865   VEX_LEN_0FC2_P_1,
1866   VEX_LEN_0FC2_P_3,
1867   VEX_LEN_0FC4_P_2,
1868   VEX_LEN_0FC5_P_2,
1869   VEX_LEN_0FD6_P_2,
1870   VEX_LEN_0FF7_P_2,
1871   VEX_LEN_0F3816_P_2,
1872   VEX_LEN_0F3819_P_2,
1873   VEX_LEN_0F381A_P_2_M_0,
1874   VEX_LEN_0F3836_P_2,
1875   VEX_LEN_0F3841_P_2,
1876   VEX_LEN_0F385A_P_2_M_0,
1877   VEX_LEN_0F38DB_P_2,
1878   VEX_LEN_0F38F2_P_0,
1879   VEX_LEN_0F38F3_R_1_P_0,
1880   VEX_LEN_0F38F3_R_2_P_0,
1881   VEX_LEN_0F38F3_R_3_P_0,
1882   VEX_LEN_0F38F5_P_0,
1883   VEX_LEN_0F38F5_P_1,
1884   VEX_LEN_0F38F5_P_3,
1885   VEX_LEN_0F38F6_P_3,
1886   VEX_LEN_0F38F7_P_0,
1887   VEX_LEN_0F38F7_P_1,
1888   VEX_LEN_0F38F7_P_2,
1889   VEX_LEN_0F38F7_P_3,
1890   VEX_LEN_0F3A00_P_2,
1891   VEX_LEN_0F3A01_P_2,
1892   VEX_LEN_0F3A06_P_2,
1893   VEX_LEN_0F3A0A_P_2,
1894   VEX_LEN_0F3A0B_P_2,
1895   VEX_LEN_0F3A14_P_2,
1896   VEX_LEN_0F3A15_P_2,
1897   VEX_LEN_0F3A16_P_2,
1898   VEX_LEN_0F3A17_P_2,
1899   VEX_LEN_0F3A18_P_2,
1900   VEX_LEN_0F3A19_P_2,
1901   VEX_LEN_0F3A20_P_2,
1902   VEX_LEN_0F3A21_P_2,
1903   VEX_LEN_0F3A22_P_2,
1904   VEX_LEN_0F3A30_P_2,
1905   VEX_LEN_0F3A31_P_2,
1906   VEX_LEN_0F3A32_P_2,
1907   VEX_LEN_0F3A33_P_2,
1908   VEX_LEN_0F3A38_P_2,
1909   VEX_LEN_0F3A39_P_2,
1910   VEX_LEN_0F3A41_P_2,
1911   VEX_LEN_0F3A46_P_2,
1912   VEX_LEN_0F3A60_P_2,
1913   VEX_LEN_0F3A61_P_2,
1914   VEX_LEN_0F3A62_P_2,
1915   VEX_LEN_0F3A63_P_2,
1916   VEX_LEN_0F3A6A_P_2,
1917   VEX_LEN_0F3A6B_P_2,
1918   VEX_LEN_0F3A6E_P_2,
1919   VEX_LEN_0F3A6F_P_2,
1920   VEX_LEN_0F3A7A_P_2,
1921   VEX_LEN_0F3A7B_P_2,
1922   VEX_LEN_0F3A7E_P_2,
1923   VEX_LEN_0F3A7F_P_2,
1924   VEX_LEN_0F3ADF_P_2,
1925   VEX_LEN_0F3AF0_P_3,
1926   VEX_LEN_0FXOP_08_CC,
1927   VEX_LEN_0FXOP_08_CD,
1928   VEX_LEN_0FXOP_08_CE,
1929   VEX_LEN_0FXOP_08_CF,
1930   VEX_LEN_0FXOP_08_EC,
1931   VEX_LEN_0FXOP_08_ED,
1932   VEX_LEN_0FXOP_08_EE,
1933   VEX_LEN_0FXOP_08_EF,
1934   VEX_LEN_0FXOP_09_80,
1935   VEX_LEN_0FXOP_09_81
1936 };
1937
1938 enum
1939 {
1940   VEX_W_0F10_P_0 = 0,
1941   VEX_W_0F10_P_1,
1942   VEX_W_0F10_P_2,
1943   VEX_W_0F10_P_3,
1944   VEX_W_0F11_P_0,
1945   VEX_W_0F11_P_1,
1946   VEX_W_0F11_P_2,
1947   VEX_W_0F11_P_3,
1948   VEX_W_0F12_P_0_M_0,
1949   VEX_W_0F12_P_0_M_1,
1950   VEX_W_0F12_P_1,
1951   VEX_W_0F12_P_2,
1952   VEX_W_0F12_P_3,
1953   VEX_W_0F13_M_0,
1954   VEX_W_0F14,
1955   VEX_W_0F15,
1956   VEX_W_0F16_P_0_M_0,
1957   VEX_W_0F16_P_0_M_1,
1958   VEX_W_0F16_P_1,
1959   VEX_W_0F16_P_2,
1960   VEX_W_0F17_M_0,
1961   VEX_W_0F28,
1962   VEX_W_0F29,
1963   VEX_W_0F2B_M_0,
1964   VEX_W_0F2E_P_0,
1965   VEX_W_0F2E_P_2,
1966   VEX_W_0F2F_P_0,
1967   VEX_W_0F2F_P_2,
1968   VEX_W_0F41_P_0_LEN_1,
1969   VEX_W_0F41_P_2_LEN_1,
1970   VEX_W_0F42_P_0_LEN_1,
1971   VEX_W_0F42_P_2_LEN_1,
1972   VEX_W_0F44_P_0_LEN_0,
1973   VEX_W_0F44_P_2_LEN_0,
1974   VEX_W_0F45_P_0_LEN_1,
1975   VEX_W_0F45_P_2_LEN_1,
1976   VEX_W_0F46_P_0_LEN_1,
1977   VEX_W_0F46_P_2_LEN_1,
1978   VEX_W_0F47_P_0_LEN_1,
1979   VEX_W_0F47_P_2_LEN_1,
1980   VEX_W_0F4A_P_0_LEN_1,
1981   VEX_W_0F4A_P_2_LEN_1,
1982   VEX_W_0F4B_P_0_LEN_1,
1983   VEX_W_0F4B_P_2_LEN_1,
1984   VEX_W_0F50_M_0,
1985   VEX_W_0F51_P_0,
1986   VEX_W_0F51_P_1,
1987   VEX_W_0F51_P_2,
1988   VEX_W_0F51_P_3,
1989   VEX_W_0F52_P_0,
1990   VEX_W_0F52_P_1,
1991   VEX_W_0F53_P_0,
1992   VEX_W_0F53_P_1,
1993   VEX_W_0F58_P_0,
1994   VEX_W_0F58_P_1,
1995   VEX_W_0F58_P_2,
1996   VEX_W_0F58_P_3,
1997   VEX_W_0F59_P_0,
1998   VEX_W_0F59_P_1,
1999   VEX_W_0F59_P_2,
2000   VEX_W_0F59_P_3,
2001   VEX_W_0F5A_P_0,
2002   VEX_W_0F5A_P_1,
2003   VEX_W_0F5A_P_3,
2004   VEX_W_0F5B_P_0,
2005   VEX_W_0F5B_P_1,
2006   VEX_W_0F5B_P_2,
2007   VEX_W_0F5C_P_0,
2008   VEX_W_0F5C_P_1,
2009   VEX_W_0F5C_P_2,
2010   VEX_W_0F5C_P_3,
2011   VEX_W_0F5D_P_0,
2012   VEX_W_0F5D_P_1,
2013   VEX_W_0F5D_P_2,
2014   VEX_W_0F5D_P_3,
2015   VEX_W_0F5E_P_0,
2016   VEX_W_0F5E_P_1,
2017   VEX_W_0F5E_P_2,
2018   VEX_W_0F5E_P_3,
2019   VEX_W_0F5F_P_0,
2020   VEX_W_0F5F_P_1,
2021   VEX_W_0F5F_P_2,
2022   VEX_W_0F5F_P_3,
2023   VEX_W_0F60_P_2,
2024   VEX_W_0F61_P_2,
2025   VEX_W_0F62_P_2,
2026   VEX_W_0F63_P_2,
2027   VEX_W_0F64_P_2,
2028   VEX_W_0F65_P_2,
2029   VEX_W_0F66_P_2,
2030   VEX_W_0F67_P_2,
2031   VEX_W_0F68_P_2,
2032   VEX_W_0F69_P_2,
2033   VEX_W_0F6A_P_2,
2034   VEX_W_0F6B_P_2,
2035   VEX_W_0F6C_P_2,
2036   VEX_W_0F6D_P_2,
2037   VEX_W_0F6F_P_1,
2038   VEX_W_0F6F_P_2,
2039   VEX_W_0F70_P_1,
2040   VEX_W_0F70_P_2,
2041   VEX_W_0F70_P_3,
2042   VEX_W_0F71_R_2_P_2,
2043   VEX_W_0F71_R_4_P_2,
2044   VEX_W_0F71_R_6_P_2,
2045   VEX_W_0F72_R_2_P_2,
2046   VEX_W_0F72_R_4_P_2,
2047   VEX_W_0F72_R_6_P_2,
2048   VEX_W_0F73_R_2_P_2,
2049   VEX_W_0F73_R_3_P_2,
2050   VEX_W_0F73_R_6_P_2,
2051   VEX_W_0F73_R_7_P_2,
2052   VEX_W_0F74_P_2,
2053   VEX_W_0F75_P_2,
2054   VEX_W_0F76_P_2,
2055   VEX_W_0F77_P_0,
2056   VEX_W_0F7C_P_2,
2057   VEX_W_0F7C_P_3,
2058   VEX_W_0F7D_P_2,
2059   VEX_W_0F7D_P_3,
2060   VEX_W_0F7E_P_1,
2061   VEX_W_0F7F_P_1,
2062   VEX_W_0F7F_P_2,
2063   VEX_W_0F90_P_0_LEN_0,
2064   VEX_W_0F90_P_2_LEN_0,
2065   VEX_W_0F91_P_0_LEN_0,
2066   VEX_W_0F91_P_2_LEN_0,
2067   VEX_W_0F92_P_0_LEN_0,
2068   VEX_W_0F92_P_2_LEN_0,
2069   VEX_W_0F92_P_3_LEN_0,
2070   VEX_W_0F93_P_0_LEN_0,
2071   VEX_W_0F93_P_2_LEN_0,
2072   VEX_W_0F93_P_3_LEN_0,
2073   VEX_W_0F98_P_0_LEN_0,
2074   VEX_W_0F98_P_2_LEN_0,
2075   VEX_W_0F99_P_0_LEN_0,
2076   VEX_W_0F99_P_2_LEN_0,
2077   VEX_W_0FAE_R_2_M_0,
2078   VEX_W_0FAE_R_3_M_0,
2079   VEX_W_0FC2_P_0,
2080   VEX_W_0FC2_P_1,
2081   VEX_W_0FC2_P_2,
2082   VEX_W_0FC2_P_3,
2083   VEX_W_0FC4_P_2,
2084   VEX_W_0FC5_P_2,
2085   VEX_W_0FD0_P_2,
2086   VEX_W_0FD0_P_3,
2087   VEX_W_0FD1_P_2,
2088   VEX_W_0FD2_P_2,
2089   VEX_W_0FD3_P_2,
2090   VEX_W_0FD4_P_2,
2091   VEX_W_0FD5_P_2,
2092   VEX_W_0FD6_P_2,
2093   VEX_W_0FD7_P_2_M_1,
2094   VEX_W_0FD8_P_2,
2095   VEX_W_0FD9_P_2,
2096   VEX_W_0FDA_P_2,
2097   VEX_W_0FDB_P_2,
2098   VEX_W_0FDC_P_2,
2099   VEX_W_0FDD_P_2,
2100   VEX_W_0FDE_P_2,
2101   VEX_W_0FDF_P_2,
2102   VEX_W_0FE0_P_2,
2103   VEX_W_0FE1_P_2,
2104   VEX_W_0FE2_P_2,
2105   VEX_W_0FE3_P_2,
2106   VEX_W_0FE4_P_2,
2107   VEX_W_0FE5_P_2,
2108   VEX_W_0FE6_P_1,
2109   VEX_W_0FE6_P_2,
2110   VEX_W_0FE6_P_3,
2111   VEX_W_0FE7_P_2_M_0,
2112   VEX_W_0FE8_P_2,
2113   VEX_W_0FE9_P_2,
2114   VEX_W_0FEA_P_2,
2115   VEX_W_0FEB_P_2,
2116   VEX_W_0FEC_P_2,
2117   VEX_W_0FED_P_2,
2118   VEX_W_0FEE_P_2,
2119   VEX_W_0FEF_P_2,
2120   VEX_W_0FF0_P_3_M_0,
2121   VEX_W_0FF1_P_2,
2122   VEX_W_0FF2_P_2,
2123   VEX_W_0FF3_P_2,
2124   VEX_W_0FF4_P_2,
2125   VEX_W_0FF5_P_2,
2126   VEX_W_0FF6_P_2,
2127   VEX_W_0FF7_P_2,
2128   VEX_W_0FF8_P_2,
2129   VEX_W_0FF9_P_2,
2130   VEX_W_0FFA_P_2,
2131   VEX_W_0FFB_P_2,
2132   VEX_W_0FFC_P_2,
2133   VEX_W_0FFD_P_2,
2134   VEX_W_0FFE_P_2,
2135   VEX_W_0F3800_P_2,
2136   VEX_W_0F3801_P_2,
2137   VEX_W_0F3802_P_2,
2138   VEX_W_0F3803_P_2,
2139   VEX_W_0F3804_P_2,
2140   VEX_W_0F3805_P_2,
2141   VEX_W_0F3806_P_2,
2142   VEX_W_0F3807_P_2,
2143   VEX_W_0F3808_P_2,
2144   VEX_W_0F3809_P_2,
2145   VEX_W_0F380A_P_2,
2146   VEX_W_0F380B_P_2,
2147   VEX_W_0F380C_P_2,
2148   VEX_W_0F380D_P_2,
2149   VEX_W_0F380E_P_2,
2150   VEX_W_0F380F_P_2,
2151   VEX_W_0F3816_P_2,
2152   VEX_W_0F3817_P_2,
2153   VEX_W_0F3818_P_2,
2154   VEX_W_0F3819_P_2,
2155   VEX_W_0F381A_P_2_M_0,
2156   VEX_W_0F381C_P_2,
2157   VEX_W_0F381D_P_2,
2158   VEX_W_0F381E_P_2,
2159   VEX_W_0F3820_P_2,
2160   VEX_W_0F3821_P_2,
2161   VEX_W_0F3822_P_2,
2162   VEX_W_0F3823_P_2,
2163   VEX_W_0F3824_P_2,
2164   VEX_W_0F3825_P_2,
2165   VEX_W_0F3828_P_2,
2166   VEX_W_0F3829_P_2,
2167   VEX_W_0F382A_P_2_M_0,
2168   VEX_W_0F382B_P_2,
2169   VEX_W_0F382C_P_2_M_0,
2170   VEX_W_0F382D_P_2_M_0,
2171   VEX_W_0F382E_P_2_M_0,
2172   VEX_W_0F382F_P_2_M_0,
2173   VEX_W_0F3830_P_2,
2174   VEX_W_0F3831_P_2,
2175   VEX_W_0F3832_P_2,
2176   VEX_W_0F3833_P_2,
2177   VEX_W_0F3834_P_2,
2178   VEX_W_0F3835_P_2,
2179   VEX_W_0F3836_P_2,
2180   VEX_W_0F3837_P_2,
2181   VEX_W_0F3838_P_2,
2182   VEX_W_0F3839_P_2,
2183   VEX_W_0F383A_P_2,
2184   VEX_W_0F383B_P_2,
2185   VEX_W_0F383C_P_2,
2186   VEX_W_0F383D_P_2,
2187   VEX_W_0F383E_P_2,
2188   VEX_W_0F383F_P_2,
2189   VEX_W_0F3840_P_2,
2190   VEX_W_0F3841_P_2,
2191   VEX_W_0F3846_P_2,
2192   VEX_W_0F3858_P_2,
2193   VEX_W_0F3859_P_2,
2194   VEX_W_0F385A_P_2_M_0,
2195   VEX_W_0F3878_P_2,
2196   VEX_W_0F3879_P_2,
2197   VEX_W_0F38CF_P_2,
2198   VEX_W_0F38DB_P_2,
2199   VEX_W_0F3A00_P_2,
2200   VEX_W_0F3A01_P_2,
2201   VEX_W_0F3A02_P_2,
2202   VEX_W_0F3A04_P_2,
2203   VEX_W_0F3A05_P_2,
2204   VEX_W_0F3A06_P_2,
2205   VEX_W_0F3A08_P_2,
2206   VEX_W_0F3A09_P_2,
2207   VEX_W_0F3A0A_P_2,
2208   VEX_W_0F3A0B_P_2,
2209   VEX_W_0F3A0C_P_2,
2210   VEX_W_0F3A0D_P_2,
2211   VEX_W_0F3A0E_P_2,
2212   VEX_W_0F3A0F_P_2,
2213   VEX_W_0F3A14_P_2,
2214   VEX_W_0F3A15_P_2,
2215   VEX_W_0F3A18_P_2,
2216   VEX_W_0F3A19_P_2,
2217   VEX_W_0F3A20_P_2,
2218   VEX_W_0F3A21_P_2,
2219   VEX_W_0F3A30_P_2_LEN_0,
2220   VEX_W_0F3A31_P_2_LEN_0,
2221   VEX_W_0F3A32_P_2_LEN_0,
2222   VEX_W_0F3A33_P_2_LEN_0,
2223   VEX_W_0F3A38_P_2,
2224   VEX_W_0F3A39_P_2,
2225   VEX_W_0F3A40_P_2,
2226   VEX_W_0F3A41_P_2,
2227   VEX_W_0F3A42_P_2,
2228   VEX_W_0F3A46_P_2,
2229   VEX_W_0F3A48_P_2,
2230   VEX_W_0F3A49_P_2,
2231   VEX_W_0F3A4A_P_2,
2232   VEX_W_0F3A4B_P_2,
2233   VEX_W_0F3A4C_P_2,
2234   VEX_W_0F3A62_P_2,
2235   VEX_W_0F3A63_P_2,
2236   VEX_W_0F3ACE_P_2,
2237   VEX_W_0F3ACF_P_2,
2238   VEX_W_0F3ADF_P_2,
2239
2240   EVEX_W_0F10_P_0,
2241   EVEX_W_0F10_P_1_M_0,
2242   EVEX_W_0F10_P_1_M_1,
2243   EVEX_W_0F10_P_2,
2244   EVEX_W_0F10_P_3_M_0,
2245   EVEX_W_0F10_P_3_M_1,
2246   EVEX_W_0F11_P_0,
2247   EVEX_W_0F11_P_1_M_0,
2248   EVEX_W_0F11_P_1_M_1,
2249   EVEX_W_0F11_P_2,
2250   EVEX_W_0F11_P_3_M_0,
2251   EVEX_W_0F11_P_3_M_1,
2252   EVEX_W_0F12_P_0_M_0,
2253   EVEX_W_0F12_P_0_M_1,
2254   EVEX_W_0F12_P_1,
2255   EVEX_W_0F12_P_2,
2256   EVEX_W_0F12_P_3,
2257   EVEX_W_0F13_P_0,
2258   EVEX_W_0F13_P_2,
2259   EVEX_W_0F14_P_0,
2260   EVEX_W_0F14_P_2,
2261   EVEX_W_0F15_P_0,
2262   EVEX_W_0F15_P_2,
2263   EVEX_W_0F16_P_0_M_0,
2264   EVEX_W_0F16_P_0_M_1,
2265   EVEX_W_0F16_P_1,
2266   EVEX_W_0F16_P_2,
2267   EVEX_W_0F17_P_0,
2268   EVEX_W_0F17_P_2,
2269   EVEX_W_0F28_P_0,
2270   EVEX_W_0F28_P_2,
2271   EVEX_W_0F29_P_0,
2272   EVEX_W_0F29_P_2,
2273   EVEX_W_0F2A_P_1,
2274   EVEX_W_0F2A_P_3,
2275   EVEX_W_0F2B_P_0,
2276   EVEX_W_0F2B_P_2,
2277   EVEX_W_0F2E_P_0,
2278   EVEX_W_0F2E_P_2,
2279   EVEX_W_0F2F_P_0,
2280   EVEX_W_0F2F_P_2,
2281   EVEX_W_0F51_P_0,
2282   EVEX_W_0F51_P_1,
2283   EVEX_W_0F51_P_2,
2284   EVEX_W_0F51_P_3,
2285   EVEX_W_0F54_P_0,
2286   EVEX_W_0F54_P_2,
2287   EVEX_W_0F55_P_0,
2288   EVEX_W_0F55_P_2,
2289   EVEX_W_0F56_P_0,
2290   EVEX_W_0F56_P_2,
2291   EVEX_W_0F57_P_0,
2292   EVEX_W_0F57_P_2,
2293   EVEX_W_0F58_P_0,
2294   EVEX_W_0F58_P_1,
2295   EVEX_W_0F58_P_2,
2296   EVEX_W_0F58_P_3,
2297   EVEX_W_0F59_P_0,
2298   EVEX_W_0F59_P_1,
2299   EVEX_W_0F59_P_2,
2300   EVEX_W_0F59_P_3,
2301   EVEX_W_0F5A_P_0,
2302   EVEX_W_0F5A_P_1,
2303   EVEX_W_0F5A_P_2,
2304   EVEX_W_0F5A_P_3,
2305   EVEX_W_0F5B_P_0,
2306   EVEX_W_0F5B_P_1,
2307   EVEX_W_0F5B_P_2,
2308   EVEX_W_0F5C_P_0,
2309   EVEX_W_0F5C_P_1,
2310   EVEX_W_0F5C_P_2,
2311   EVEX_W_0F5C_P_3,
2312   EVEX_W_0F5D_P_0,
2313   EVEX_W_0F5D_P_1,
2314   EVEX_W_0F5D_P_2,
2315   EVEX_W_0F5D_P_3,
2316   EVEX_W_0F5E_P_0,
2317   EVEX_W_0F5E_P_1,
2318   EVEX_W_0F5E_P_2,
2319   EVEX_W_0F5E_P_3,
2320   EVEX_W_0F5F_P_0,
2321   EVEX_W_0F5F_P_1,
2322   EVEX_W_0F5F_P_2,
2323   EVEX_W_0F5F_P_3,
2324   EVEX_W_0F62_P_2,
2325   EVEX_W_0F66_P_2,
2326   EVEX_W_0F6A_P_2,
2327   EVEX_W_0F6B_P_2,
2328   EVEX_W_0F6C_P_2,
2329   EVEX_W_0F6D_P_2,
2330   EVEX_W_0F6E_P_2,
2331   EVEX_W_0F6F_P_1,
2332   EVEX_W_0F6F_P_2,
2333   EVEX_W_0F6F_P_3,
2334   EVEX_W_0F70_P_2,
2335   EVEX_W_0F72_R_2_P_2,
2336   EVEX_W_0F72_R_6_P_2,
2337   EVEX_W_0F73_R_2_P_2,
2338   EVEX_W_0F73_R_6_P_2,
2339   EVEX_W_0F76_P_2,
2340   EVEX_W_0F78_P_0,
2341   EVEX_W_0F78_P_2,
2342   EVEX_W_0F79_P_0,
2343   EVEX_W_0F79_P_2,
2344   EVEX_W_0F7A_P_1,
2345   EVEX_W_0F7A_P_2,
2346   EVEX_W_0F7A_P_3,
2347   EVEX_W_0F7B_P_1,
2348   EVEX_W_0F7B_P_2,
2349   EVEX_W_0F7B_P_3,
2350   EVEX_W_0F7E_P_1,
2351   EVEX_W_0F7E_P_2,
2352   EVEX_W_0F7F_P_1,
2353   EVEX_W_0F7F_P_2,
2354   EVEX_W_0F7F_P_3,
2355   EVEX_W_0FC2_P_0,
2356   EVEX_W_0FC2_P_1,
2357   EVEX_W_0FC2_P_2,
2358   EVEX_W_0FC2_P_3,
2359   EVEX_W_0FC6_P_0,
2360   EVEX_W_0FC6_P_2,
2361   EVEX_W_0FD2_P_2,
2362   EVEX_W_0FD3_P_2,
2363   EVEX_W_0FD4_P_2,
2364   EVEX_W_0FD6_P_2,
2365   EVEX_W_0FE6_P_1,
2366   EVEX_W_0FE6_P_2,
2367   EVEX_W_0FE6_P_3,
2368   EVEX_W_0FE7_P_2,
2369   EVEX_W_0FF2_P_2,
2370   EVEX_W_0FF3_P_2,
2371   EVEX_W_0FF4_P_2,
2372   EVEX_W_0FFA_P_2,
2373   EVEX_W_0FFB_P_2,
2374   EVEX_W_0FFE_P_2,
2375   EVEX_W_0F380C_P_2,
2376   EVEX_W_0F380D_P_2,
2377   EVEX_W_0F3810_P_1,
2378   EVEX_W_0F3810_P_2,
2379   EVEX_W_0F3811_P_1,
2380   EVEX_W_0F3811_P_2,
2381   EVEX_W_0F3812_P_1,
2382   EVEX_W_0F3812_P_2,
2383   EVEX_W_0F3813_P_1,
2384   EVEX_W_0F3813_P_2,
2385   EVEX_W_0F3814_P_1,
2386   EVEX_W_0F3815_P_1,
2387   EVEX_W_0F3818_P_2,
2388   EVEX_W_0F3819_P_2,
2389   EVEX_W_0F381A_P_2,
2390   EVEX_W_0F381B_P_2,
2391   EVEX_W_0F381E_P_2,
2392   EVEX_W_0F381F_P_2,
2393   EVEX_W_0F3820_P_1,
2394   EVEX_W_0F3821_P_1,
2395   EVEX_W_0F3822_P_1,
2396   EVEX_W_0F3823_P_1,
2397   EVEX_W_0F3824_P_1,
2398   EVEX_W_0F3825_P_1,
2399   EVEX_W_0F3825_P_2,
2400   EVEX_W_0F3826_P_1,
2401   EVEX_W_0F3826_P_2,
2402   EVEX_W_0F3828_P_1,
2403   EVEX_W_0F3828_P_2,
2404   EVEX_W_0F3829_P_1,
2405   EVEX_W_0F3829_P_2,
2406   EVEX_W_0F382A_P_1,
2407   EVEX_W_0F382A_P_2,
2408   EVEX_W_0F382B_P_2,
2409   EVEX_W_0F3830_P_1,
2410   EVEX_W_0F3831_P_1,
2411   EVEX_W_0F3832_P_1,
2412   EVEX_W_0F3833_P_1,
2413   EVEX_W_0F3834_P_1,
2414   EVEX_W_0F3835_P_1,
2415   EVEX_W_0F3835_P_2,
2416   EVEX_W_0F3837_P_2,
2417   EVEX_W_0F3838_P_1,
2418   EVEX_W_0F3839_P_1,
2419   EVEX_W_0F383A_P_1,
2420   EVEX_W_0F3840_P_2,
2421   EVEX_W_0F3854_P_2,
2422   EVEX_W_0F3855_P_2,
2423   EVEX_W_0F3858_P_2,
2424   EVEX_W_0F3859_P_2,
2425   EVEX_W_0F385A_P_2,
2426   EVEX_W_0F385B_P_2,
2427   EVEX_W_0F3862_P_2,
2428   EVEX_W_0F3863_P_2,
2429   EVEX_W_0F3866_P_2,
2430   EVEX_W_0F3870_P_2,
2431   EVEX_W_0F3871_P_2,
2432   EVEX_W_0F3872_P_2,
2433   EVEX_W_0F3873_P_2,
2434   EVEX_W_0F3875_P_2,
2435   EVEX_W_0F3878_P_2,
2436   EVEX_W_0F3879_P_2,
2437   EVEX_W_0F387A_P_2,
2438   EVEX_W_0F387B_P_2,
2439   EVEX_W_0F387D_P_2,
2440   EVEX_W_0F3883_P_2,
2441   EVEX_W_0F388D_P_2,
2442   EVEX_W_0F3891_P_2,
2443   EVEX_W_0F3893_P_2,
2444   EVEX_W_0F38A1_P_2,
2445   EVEX_W_0F38A3_P_2,
2446   EVEX_W_0F38C7_R_1_P_2,
2447   EVEX_W_0F38C7_R_2_P_2,
2448   EVEX_W_0F38C7_R_5_P_2,
2449   EVEX_W_0F38C7_R_6_P_2,
2450
2451   EVEX_W_0F3A00_P_2,
2452   EVEX_W_0F3A01_P_2,
2453   EVEX_W_0F3A04_P_2,
2454   EVEX_W_0F3A05_P_2,
2455   EVEX_W_0F3A08_P_2,
2456   EVEX_W_0F3A09_P_2,
2457   EVEX_W_0F3A0A_P_2,
2458   EVEX_W_0F3A0B_P_2,
2459   EVEX_W_0F3A16_P_2,
2460   EVEX_W_0F3A18_P_2,
2461   EVEX_W_0F3A19_P_2,
2462   EVEX_W_0F3A1A_P_2,
2463   EVEX_W_0F3A1B_P_2,
2464   EVEX_W_0F3A1D_P_2,
2465   EVEX_W_0F3A21_P_2,
2466   EVEX_W_0F3A22_P_2,
2467   EVEX_W_0F3A23_P_2,
2468   EVEX_W_0F3A38_P_2,
2469   EVEX_W_0F3A39_P_2,
2470   EVEX_W_0F3A3A_P_2,
2471   EVEX_W_0F3A3B_P_2,
2472   EVEX_W_0F3A3E_P_2,
2473   EVEX_W_0F3A3F_P_2,
2474   EVEX_W_0F3A42_P_2,
2475   EVEX_W_0F3A43_P_2,
2476   EVEX_W_0F3A50_P_2,
2477   EVEX_W_0F3A51_P_2,
2478   EVEX_W_0F3A56_P_2,
2479   EVEX_W_0F3A57_P_2,
2480   EVEX_W_0F3A66_P_2,
2481   EVEX_W_0F3A67_P_2,
2482   EVEX_W_0F3A70_P_2,
2483   EVEX_W_0F3A71_P_2,
2484   EVEX_W_0F3A72_P_2,
2485   EVEX_W_0F3A73_P_2,
2486   EVEX_W_0F3ACE_P_2,
2487   EVEX_W_0F3ACF_P_2
2488 };
2489
2490 typedef void (*op_rtn) (int bytemode, int sizeflag);
2491
2492 struct dis386 {
2493   const char *name;
2494   struct
2495     {
2496       op_rtn rtn;
2497       int bytemode;
2498     } op[MAX_OPERANDS];
2499   unsigned int prefix_requirement;
2500 };
2501
2502 /* Upper case letters in the instruction names here are macros.
2503    'A' => print 'b' if no register operands or suffix_always is true
2504    'B' => print 'b' if suffix_always is true
2505    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2506           size prefix
2507    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2508           suffix_always is true
2509    'E' => print 'e' if 32-bit form of jcxz
2510    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2511    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2512    'H' => print ",pt" or ",pn" branch hint
2513    'I' => honor following macro letter even in Intel mode (implemented only
2514           for some of the macro letters)
2515    'J' => print 'l'
2516    'K' => print 'd' or 'q' if rex prefix is present.
2517    'L' => print 'l' if suffix_always is true
2518    'M' => print 'r' if intel_mnemonic is false.
2519    'N' => print 'n' if instruction has no wait "prefix"
2520    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2521    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2522           or suffix_always is true.  print 'q' if rex prefix is present.
2523    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2524           is true
2525    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2526    'S' => print 'w', 'l' or 'q' if suffix_always is true
2527    'T' => print 'q' in 64bit mode if instruction has no operand size
2528           prefix and behave as 'P' otherwise
2529    'U' => print 'q' in 64bit mode if instruction has no operand size
2530           prefix and behave as 'Q' otherwise
2531    'V' => print 'q' in 64bit mode if instruction has no operand size
2532           prefix and behave as 'S' otherwise
2533    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2534    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2535    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2536           suffix_always is true.
2537    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2538    '!' => change condition from true to false or from false to true.
2539    '%' => add 1 upper case letter to the macro.
2540    '^' => print 'w' or 'l' depending on operand size prefix or
2541           suffix_always is true (lcall/ljmp).
2542    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2543           on operand size prefix.
2544    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2545           has no operand size prefix for AMD64 ISA, behave as 'P'
2546           otherwise
2547
2548    2 upper case letter macros:
2549    "XY" => print 'x' or 'y' if suffix_always is true or no register
2550            operands and no broadcast.
2551    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2552            register operands and no broadcast.
2553    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2554    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2555            or suffix_always is true
2556    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2557    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2558    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2559    "LW" => print 'd', 'q' depending on the VEX.W bit
2560    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2561            an operand size prefix, or suffix_always is true.  print
2562            'q' if rex prefix is present.
2563
2564    Many of the above letters print nothing in Intel mode.  See "putop"
2565    for the details.
2566
2567    Braces '{' and '}', and vertical bars '|', indicate alternative
2568    mnemonic strings for AT&T and Intel.  */
2569
2570 static const struct dis386 dis386[] = {
2571   /* 00 */
2572   { "addB",             { Ebh1, Gb }, 0 },
2573   { "addS",             { Evh1, Gv }, 0 },
2574   { "addB",             { Gb, EbS }, 0 },
2575   { "addS",             { Gv, EvS }, 0 },
2576   { "addB",             { AL, Ib }, 0 },
2577   { "addS",             { eAX, Iv }, 0 },
2578   { X86_64_TABLE (X86_64_06) },
2579   { X86_64_TABLE (X86_64_07) },
2580   /* 08 */
2581   { "orB",              { Ebh1, Gb }, 0 },
2582   { "orS",              { Evh1, Gv }, 0 },
2583   { "orB",              { Gb, EbS }, 0 },
2584   { "orS",              { Gv, EvS }, 0 },
2585   { "orB",              { AL, Ib }, 0 },
2586   { "orS",              { eAX, Iv }, 0 },
2587   { X86_64_TABLE (X86_64_0D) },
2588   { Bad_Opcode },       /* 0x0f extended opcode escape */
2589   /* 10 */
2590   { "adcB",             { Ebh1, Gb }, 0 },
2591   { "adcS",             { Evh1, Gv }, 0 },
2592   { "adcB",             { Gb, EbS }, 0 },
2593   { "adcS",             { Gv, EvS }, 0 },
2594   { "adcB",             { AL, Ib }, 0 },
2595   { "adcS",             { eAX, Iv }, 0 },
2596   { X86_64_TABLE (X86_64_16) },
2597   { X86_64_TABLE (X86_64_17) },
2598   /* 18 */
2599   { "sbbB",             { Ebh1, Gb }, 0 },
2600   { "sbbS",             { Evh1, Gv }, 0 },
2601   { "sbbB",             { Gb, EbS }, 0 },
2602   { "sbbS",             { Gv, EvS }, 0 },
2603   { "sbbB",             { AL, Ib }, 0 },
2604   { "sbbS",             { eAX, Iv }, 0 },
2605   { X86_64_TABLE (X86_64_1E) },
2606   { X86_64_TABLE (X86_64_1F) },
2607   /* 20 */
2608   { "andB",             { Ebh1, Gb }, 0 },
2609   { "andS",             { Evh1, Gv }, 0 },
2610   { "andB",             { Gb, EbS }, 0 },
2611   { "andS",             { Gv, EvS }, 0 },
2612   { "andB",             { AL, Ib }, 0 },
2613   { "andS",             { eAX, Iv }, 0 },
2614   { Bad_Opcode },       /* SEG ES prefix */
2615   { X86_64_TABLE (X86_64_27) },
2616   /* 28 */
2617   { "subB",             { Ebh1, Gb }, 0 },
2618   { "subS",             { Evh1, Gv }, 0 },
2619   { "subB",             { Gb, EbS }, 0 },
2620   { "subS",             { Gv, EvS }, 0 },
2621   { "subB",             { AL, Ib }, 0 },
2622   { "subS",             { eAX, Iv }, 0 },
2623   { Bad_Opcode },       /* SEG CS prefix */
2624   { X86_64_TABLE (X86_64_2F) },
2625   /* 30 */
2626   { "xorB",             { Ebh1, Gb }, 0 },
2627   { "xorS",             { Evh1, Gv }, 0 },
2628   { "xorB",             { Gb, EbS }, 0 },
2629   { "xorS",             { Gv, EvS }, 0 },
2630   { "xorB",             { AL, Ib }, 0 },
2631   { "xorS",             { eAX, Iv }, 0 },
2632   { Bad_Opcode },       /* SEG SS prefix */
2633   { X86_64_TABLE (X86_64_37) },
2634   /* 38 */
2635   { "cmpB",             { Eb, Gb }, 0 },
2636   { "cmpS",             { Ev, Gv }, 0 },
2637   { "cmpB",             { Gb, EbS }, 0 },
2638   { "cmpS",             { Gv, EvS }, 0 },
2639   { "cmpB",             { AL, Ib }, 0 },
2640   { "cmpS",             { eAX, Iv }, 0 },
2641   { Bad_Opcode },       /* SEG DS prefix */
2642   { X86_64_TABLE (X86_64_3F) },
2643   /* 40 */
2644   { "inc{S|}",          { RMeAX }, 0 },
2645   { "inc{S|}",          { RMeCX }, 0 },
2646   { "inc{S|}",          { RMeDX }, 0 },
2647   { "inc{S|}",          { RMeBX }, 0 },
2648   { "inc{S|}",          { RMeSP }, 0 },
2649   { "inc{S|}",          { RMeBP }, 0 },
2650   { "inc{S|}",          { RMeSI }, 0 },
2651   { "inc{S|}",          { RMeDI }, 0 },
2652   /* 48 */
2653   { "dec{S|}",          { RMeAX }, 0 },
2654   { "dec{S|}",          { RMeCX }, 0 },
2655   { "dec{S|}",          { RMeDX }, 0 },
2656   { "dec{S|}",          { RMeBX }, 0 },
2657   { "dec{S|}",          { RMeSP }, 0 },
2658   { "dec{S|}",          { RMeBP }, 0 },
2659   { "dec{S|}",          { RMeSI }, 0 },
2660   { "dec{S|}",          { RMeDI }, 0 },
2661   /* 50 */
2662   { "pushV",            { RMrAX }, 0 },
2663   { "pushV",            { RMrCX }, 0 },
2664   { "pushV",            { RMrDX }, 0 },
2665   { "pushV",            { RMrBX }, 0 },
2666   { "pushV",            { RMrSP }, 0 },
2667   { "pushV",            { RMrBP }, 0 },
2668   { "pushV",            { RMrSI }, 0 },
2669   { "pushV",            { RMrDI }, 0 },
2670   /* 58 */
2671   { "popV",             { RMrAX }, 0 },
2672   { "popV",             { RMrCX }, 0 },
2673   { "popV",             { RMrDX }, 0 },
2674   { "popV",             { RMrBX }, 0 },
2675   { "popV",             { RMrSP }, 0 },
2676   { "popV",             { RMrBP }, 0 },
2677   { "popV",             { RMrSI }, 0 },
2678   { "popV",             { RMrDI }, 0 },
2679   /* 60 */
2680   { X86_64_TABLE (X86_64_60) },
2681   { X86_64_TABLE (X86_64_61) },
2682   { X86_64_TABLE (X86_64_62) },
2683   { X86_64_TABLE (X86_64_63) },
2684   { Bad_Opcode },       /* seg fs */
2685   { Bad_Opcode },       /* seg gs */
2686   { Bad_Opcode },       /* op size prefix */
2687   { Bad_Opcode },       /* adr size prefix */
2688   /* 68 */
2689   { "pushT",            { sIv }, 0 },
2690   { "imulS",            { Gv, Ev, Iv }, 0 },
2691   { "pushT",            { sIbT }, 0 },
2692   { "imulS",            { Gv, Ev, sIb }, 0 },
2693   { "ins{b|}",          { Ybr, indirDX }, 0 },
2694   { X86_64_TABLE (X86_64_6D) },
2695   { "outs{b|}",         { indirDXr, Xb }, 0 },
2696   { X86_64_TABLE (X86_64_6F) },
2697   /* 70 */
2698   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2699   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2700   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2701   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2702   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2703   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2704   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2705   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2706   /* 78 */
2707   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2708   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2709   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2710   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2711   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2712   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2713   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2714   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2715   /* 80 */
2716   { REG_TABLE (REG_80) },
2717   { REG_TABLE (REG_81) },
2718   { X86_64_TABLE (X86_64_82) },
2719   { REG_TABLE (REG_83) },
2720   { "testB",            { Eb, Gb }, 0 },
2721   { "testS",            { Ev, Gv }, 0 },
2722   { "xchgB",            { Ebh2, Gb }, 0 },
2723   { "xchgS",            { Evh2, Gv }, 0 },
2724   /* 88 */
2725   { "movB",             { Ebh3, Gb }, 0 },
2726   { "movS",             { Evh3, Gv }, 0 },
2727   { "movB",             { Gb, EbS }, 0 },
2728   { "movS",             { Gv, EvS }, 0 },
2729   { "movD",             { Sv, Sw }, 0 },
2730   { MOD_TABLE (MOD_8D) },
2731   { "movD",             { Sw, Sv }, 0 },
2732   { REG_TABLE (REG_8F) },
2733   /* 90 */
2734   { PREFIX_TABLE (PREFIX_90) },
2735   { "xchgS",            { RMeCX, eAX }, 0 },
2736   { "xchgS",            { RMeDX, eAX }, 0 },
2737   { "xchgS",            { RMeBX, eAX }, 0 },
2738   { "xchgS",            { RMeSP, eAX }, 0 },
2739   { "xchgS",            { RMeBP, eAX }, 0 },
2740   { "xchgS",            { RMeSI, eAX }, 0 },
2741   { "xchgS",            { RMeDI, eAX }, 0 },
2742   /* 98 */
2743   { "cW{t|}R",          { XX }, 0 },
2744   { "cR{t|}O",          { XX }, 0 },
2745   { X86_64_TABLE (X86_64_9A) },
2746   { Bad_Opcode },       /* fwait */
2747   { "pushfT",           { XX }, 0 },
2748   { "popfT",            { XX }, 0 },
2749   { "sahf",             { XX }, 0 },
2750   { "lahf",             { XX }, 0 },
2751   /* a0 */
2752   { "mov%LB",           { AL, Ob }, 0 },
2753   { "mov%LS",           { eAX, Ov }, 0 },
2754   { "mov%LB",           { Ob, AL }, 0 },
2755   { "mov%LS",           { Ov, eAX }, 0 },
2756   { "movs{b|}",         { Ybr, Xb }, 0 },
2757   { "movs{R|}",         { Yvr, Xv }, 0 },
2758   { "cmps{b|}",         { Xb, Yb }, 0 },
2759   { "cmps{R|}",         { Xv, Yv }, 0 },
2760   /* a8 */
2761   { "testB",            { AL, Ib }, 0 },
2762   { "testS",            { eAX, Iv }, 0 },
2763   { "stosB",            { Ybr, AL }, 0 },
2764   { "stosS",            { Yvr, eAX }, 0 },
2765   { "lodsB",            { ALr, Xb }, 0 },
2766   { "lodsS",            { eAXr, Xv }, 0 },
2767   { "scasB",            { AL, Yb }, 0 },
2768   { "scasS",            { eAX, Yv }, 0 },
2769   /* b0 */
2770   { "movB",             { RMAL, Ib }, 0 },
2771   { "movB",             { RMCL, Ib }, 0 },
2772   { "movB",             { RMDL, Ib }, 0 },
2773   { "movB",             { RMBL, Ib }, 0 },
2774   { "movB",             { RMAH, Ib }, 0 },
2775   { "movB",             { RMCH, Ib }, 0 },
2776   { "movB",             { RMDH, Ib }, 0 },
2777   { "movB",             { RMBH, Ib }, 0 },
2778   /* b8 */
2779   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2780   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2781   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2782   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2783   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2784   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2785   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2786   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2787   /* c0 */
2788   { REG_TABLE (REG_C0) },
2789   { REG_TABLE (REG_C1) },
2790   { "retT",             { Iw, BND }, 0 },
2791   { "retT",             { BND }, 0 },
2792   { X86_64_TABLE (X86_64_C4) },
2793   { X86_64_TABLE (X86_64_C5) },
2794   { REG_TABLE (REG_C6) },
2795   { REG_TABLE (REG_C7) },
2796   /* c8 */
2797   { "enterT",           { Iw, Ib }, 0 },
2798   { "leaveT",           { XX }, 0 },
2799   { "Jret{|f}P",        { Iw }, 0 },
2800   { "Jret{|f}P",        { XX }, 0 },
2801   { "int3",             { XX }, 0 },
2802   { "int",              { Ib }, 0 },
2803   { X86_64_TABLE (X86_64_CE) },
2804   { "iret%LP",          { XX }, 0 },
2805   /* d0 */
2806   { REG_TABLE (REG_D0) },
2807   { REG_TABLE (REG_D1) },
2808   { REG_TABLE (REG_D2) },
2809   { REG_TABLE (REG_D3) },
2810   { X86_64_TABLE (X86_64_D4) },
2811   { X86_64_TABLE (X86_64_D5) },
2812   { Bad_Opcode },
2813   { "xlat",             { DSBX }, 0 },
2814   /* d8 */
2815   { FLOAT },
2816   { FLOAT },
2817   { FLOAT },
2818   { FLOAT },
2819   { FLOAT },
2820   { FLOAT },
2821   { FLOAT },
2822   { FLOAT },
2823   /* e0 */
2824   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2825   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2826   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2827   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2828   { "inB",              { AL, Ib }, 0 },
2829   { "inG",              { zAX, Ib }, 0 },
2830   { "outB",             { Ib, AL }, 0 },
2831   { "outG",             { Ib, zAX }, 0 },
2832   /* e8 */
2833   { X86_64_TABLE (X86_64_E8) },
2834   { X86_64_TABLE (X86_64_E9) },
2835   { X86_64_TABLE (X86_64_EA) },
2836   { "jmp",              { Jb, BND }, 0 },
2837   { "inB",              { AL, indirDX }, 0 },
2838   { "inG",              { zAX, indirDX }, 0 },
2839   { "outB",             { indirDX, AL }, 0 },
2840   { "outG",             { indirDX, zAX }, 0 },
2841   /* f0 */
2842   { Bad_Opcode },       /* lock prefix */
2843   { "icebp",            { XX }, 0 },
2844   { Bad_Opcode },       /* repne */
2845   { Bad_Opcode },       /* repz */
2846   { "hlt",              { XX }, 0 },
2847   { "cmc",              { XX }, 0 },
2848   { REG_TABLE (REG_F6) },
2849   { REG_TABLE (REG_F7) },
2850   /* f8 */
2851   { "clc",              { XX }, 0 },
2852   { "stc",              { XX }, 0 },
2853   { "cli",              { XX }, 0 },
2854   { "sti",              { XX }, 0 },
2855   { "cld",              { XX }, 0 },
2856   { "std",              { XX }, 0 },
2857   { REG_TABLE (REG_FE) },
2858   { REG_TABLE (REG_FF) },
2859 };
2860
2861 static const struct dis386 dis386_twobyte[] = {
2862   /* 00 */
2863   { REG_TABLE (REG_0F00 ) },
2864   { REG_TABLE (REG_0F01 ) },
2865   { "larS",             { Gv, Ew }, 0 },
2866   { "lslS",             { Gv, Ew }, 0 },
2867   { Bad_Opcode },
2868   { "syscall",          { XX }, 0 },
2869   { "clts",             { XX }, 0 },
2870   { "sysret%LP",                { XX }, 0 },
2871   /* 08 */
2872   { "invd",             { XX }, 0 },
2873   { PREFIX_TABLE (PREFIX_0F09) },
2874   { Bad_Opcode },
2875   { "ud2",              { XX }, 0 },
2876   { Bad_Opcode },
2877   { REG_TABLE (REG_0F0D) },
2878   { "femms",            { XX }, 0 },
2879   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2880   /* 10 */
2881   { PREFIX_TABLE (PREFIX_0F10) },
2882   { PREFIX_TABLE (PREFIX_0F11) },
2883   { PREFIX_TABLE (PREFIX_0F12) },
2884   { MOD_TABLE (MOD_0F13) },
2885   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2886   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2887   { PREFIX_TABLE (PREFIX_0F16) },
2888   { MOD_TABLE (MOD_0F17) },
2889   /* 18 */
2890   { REG_TABLE (REG_0F18) },
2891   { "nopQ",             { Ev }, 0 },
2892   { PREFIX_TABLE (PREFIX_0F1A) },
2893   { PREFIX_TABLE (PREFIX_0F1B) },
2894   { "nopQ",             { Ev }, 0 },
2895   { "nopQ",             { Ev }, 0 },
2896   { PREFIX_TABLE (PREFIX_0F1E) },
2897   { "nopQ",             { Ev }, 0 },
2898   /* 20 */
2899   { "movZ",             { Rm, Cm }, 0 },
2900   { "movZ",             { Rm, Dm }, 0 },
2901   { "movZ",             { Cm, Rm }, 0 },
2902   { "movZ",             { Dm, Rm }, 0 },
2903   { MOD_TABLE (MOD_0F24) },
2904   { Bad_Opcode },
2905   { MOD_TABLE (MOD_0F26) },
2906   { Bad_Opcode },
2907   /* 28 */
2908   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2909   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2910   { PREFIX_TABLE (PREFIX_0F2A) },
2911   { PREFIX_TABLE (PREFIX_0F2B) },
2912   { PREFIX_TABLE (PREFIX_0F2C) },
2913   { PREFIX_TABLE (PREFIX_0F2D) },
2914   { PREFIX_TABLE (PREFIX_0F2E) },
2915   { PREFIX_TABLE (PREFIX_0F2F) },
2916   /* 30 */
2917   { "wrmsr",            { XX }, 0 },
2918   { "rdtsc",            { XX }, 0 },
2919   { "rdmsr",            { XX }, 0 },
2920   { "rdpmc",            { XX }, 0 },
2921   { "sysenter",         { XX }, 0 },
2922   { "sysexit",          { XX }, 0 },
2923   { Bad_Opcode },
2924   { "getsec",           { XX }, 0 },
2925   /* 38 */
2926   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2927   { Bad_Opcode },
2928   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2929   { Bad_Opcode },
2930   { Bad_Opcode },
2931   { Bad_Opcode },
2932   { Bad_Opcode },
2933   { Bad_Opcode },
2934   /* 40 */
2935   { "cmovoS",           { Gv, Ev }, 0 },
2936   { "cmovnoS",          { Gv, Ev }, 0 },
2937   { "cmovbS",           { Gv, Ev }, 0 },
2938   { "cmovaeS",          { Gv, Ev }, 0 },
2939   { "cmoveS",           { Gv, Ev }, 0 },
2940   { "cmovneS",          { Gv, Ev }, 0 },
2941   { "cmovbeS",          { Gv, Ev }, 0 },
2942   { "cmovaS",           { Gv, Ev }, 0 },
2943   /* 48 */
2944   { "cmovsS",           { Gv, Ev }, 0 },
2945   { "cmovnsS",          { Gv, Ev }, 0 },
2946   { "cmovpS",           { Gv, Ev }, 0 },
2947   { "cmovnpS",          { Gv, Ev }, 0 },
2948   { "cmovlS",           { Gv, Ev }, 0 },
2949   { "cmovgeS",          { Gv, Ev }, 0 },
2950   { "cmovleS",          { Gv, Ev }, 0 },
2951   { "cmovgS",           { Gv, Ev }, 0 },
2952   /* 50 */
2953   { MOD_TABLE (MOD_0F51) },
2954   { PREFIX_TABLE (PREFIX_0F51) },
2955   { PREFIX_TABLE (PREFIX_0F52) },
2956   { PREFIX_TABLE (PREFIX_0F53) },
2957   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2958   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2959   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2960   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2961   /* 58 */
2962   { PREFIX_TABLE (PREFIX_0F58) },
2963   { PREFIX_TABLE (PREFIX_0F59) },
2964   { PREFIX_TABLE (PREFIX_0F5A) },
2965   { PREFIX_TABLE (PREFIX_0F5B) },
2966   { PREFIX_TABLE (PREFIX_0F5C) },
2967   { PREFIX_TABLE (PREFIX_0F5D) },
2968   { PREFIX_TABLE (PREFIX_0F5E) },
2969   { PREFIX_TABLE (PREFIX_0F5F) },
2970   /* 60 */
2971   { PREFIX_TABLE (PREFIX_0F60) },
2972   { PREFIX_TABLE (PREFIX_0F61) },
2973   { PREFIX_TABLE (PREFIX_0F62) },
2974   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2975   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2976   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2977   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2978   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2979   /* 68 */
2980   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2981   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2982   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2983   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2984   { PREFIX_TABLE (PREFIX_0F6C) },
2985   { PREFIX_TABLE (PREFIX_0F6D) },
2986   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2987   { PREFIX_TABLE (PREFIX_0F6F) },
2988   /* 70 */
2989   { PREFIX_TABLE (PREFIX_0F70) },
2990   { REG_TABLE (REG_0F71) },
2991   { REG_TABLE (REG_0F72) },
2992   { REG_TABLE (REG_0F73) },
2993   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2994   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2995   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2996   { "emms",             { XX }, PREFIX_OPCODE },
2997   /* 78 */
2998   { PREFIX_TABLE (PREFIX_0F78) },
2999   { PREFIX_TABLE (PREFIX_0F79) },
3000   { Bad_Opcode },
3001   { Bad_Opcode },
3002   { PREFIX_TABLE (PREFIX_0F7C) },
3003   { PREFIX_TABLE (PREFIX_0F7D) },
3004   { PREFIX_TABLE (PREFIX_0F7E) },
3005   { PREFIX_TABLE (PREFIX_0F7F) },
3006   /* 80 */
3007   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
3008   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
3009   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
3010   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
3011   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
3012   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
3013   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
3014   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
3015   /* 88 */
3016   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
3017   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
3018   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
3019   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
3020   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
3021   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
3022   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
3023   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
3024   /* 90 */
3025   { "seto",             { Eb }, 0 },
3026   { "setno",            { Eb }, 0 },
3027   { "setb",             { Eb }, 0 },
3028   { "setae",            { Eb }, 0 },
3029   { "sete",             { Eb }, 0 },
3030   { "setne",            { Eb }, 0 },
3031   { "setbe",            { Eb }, 0 },
3032   { "seta",             { Eb }, 0 },
3033   /* 98 */
3034   { "sets",             { Eb }, 0 },
3035   { "setns",            { Eb }, 0 },
3036   { "setp",             { Eb }, 0 },
3037   { "setnp",            { Eb }, 0 },
3038   { "setl",             { Eb }, 0 },
3039   { "setge",            { Eb }, 0 },
3040   { "setle",            { Eb }, 0 },
3041   { "setg",             { Eb }, 0 },
3042   /* a0 */
3043   { "pushT",            { fs }, 0 },
3044   { "popT",             { fs }, 0 },
3045   { "cpuid",            { XX }, 0 },
3046   { "btS",              { Ev, Gv }, 0 },
3047   { "shldS",            { Ev, Gv, Ib }, 0 },
3048   { "shldS",            { Ev, Gv, CL }, 0 },
3049   { REG_TABLE (REG_0FA6) },
3050   { REG_TABLE (REG_0FA7) },
3051   /* a8 */
3052   { "pushT",            { gs }, 0 },
3053   { "popT",             { gs }, 0 },
3054   { "rsm",              { XX }, 0 },
3055   { "btsS",             { Evh1, Gv }, 0 },
3056   { "shrdS",            { Ev, Gv, Ib }, 0 },
3057   { "shrdS",            { Ev, Gv, CL }, 0 },
3058   { REG_TABLE (REG_0FAE) },
3059   { "imulS",            { Gv, Ev }, 0 },
3060   /* b0 */
3061   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3062   { "cmpxchgS",         { Evh1, Gv }, 0 },
3063   { MOD_TABLE (MOD_0FB2) },
3064   { "btrS",             { Evh1, Gv }, 0 },
3065   { MOD_TABLE (MOD_0FB4) },
3066   { MOD_TABLE (MOD_0FB5) },
3067   { "movz{bR|x}",       { Gv, Eb }, 0 },
3068   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3069   /* b8 */
3070   { PREFIX_TABLE (PREFIX_0FB8) },
3071   { "ud1S",             { Gv, Ev }, 0 },
3072   { REG_TABLE (REG_0FBA) },
3073   { "btcS",             { Evh1, Gv }, 0 },
3074   { PREFIX_TABLE (PREFIX_0FBC) },
3075   { PREFIX_TABLE (PREFIX_0FBD) },
3076   { "movs{bR|x}",       { Gv, Eb }, 0 },
3077   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3078   /* c0 */
3079   { "xaddB",            { Ebh1, Gb }, 0 },
3080   { "xaddS",            { Evh1, Gv }, 0 },
3081   { PREFIX_TABLE (PREFIX_0FC2) },
3082   { MOD_TABLE (MOD_0FC3) },
3083   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3084   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3085   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3086   { REG_TABLE (REG_0FC7) },
3087   /* c8 */
3088   { "bswap",            { RMeAX }, 0 },
3089   { "bswap",            { RMeCX }, 0 },
3090   { "bswap",            { RMeDX }, 0 },
3091   { "bswap",            { RMeBX }, 0 },
3092   { "bswap",            { RMeSP }, 0 },
3093   { "bswap",            { RMeBP }, 0 },
3094   { "bswap",            { RMeSI }, 0 },
3095   { "bswap",            { RMeDI }, 0 },
3096   /* d0 */
3097   { PREFIX_TABLE (PREFIX_0FD0) },
3098   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3099   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3100   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3101   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3102   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3103   { PREFIX_TABLE (PREFIX_0FD6) },
3104   { MOD_TABLE (MOD_0FD7) },
3105   /* d8 */
3106   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3107   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3108   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3109   { "pand",             { MX, EM }, PREFIX_OPCODE },
3110   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3111   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3112   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3113   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3114   /* e0 */
3115   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3116   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3117   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3118   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3119   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3120   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3121   { PREFIX_TABLE (PREFIX_0FE6) },
3122   { PREFIX_TABLE (PREFIX_0FE7) },
3123   /* e8 */
3124   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3125   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3126   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3127   { "por",              { MX, EM }, PREFIX_OPCODE },
3128   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3129   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3130   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3131   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3132   /* f0 */
3133   { PREFIX_TABLE (PREFIX_0FF0) },
3134   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3135   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3136   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3137   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3138   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3139   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3140   { PREFIX_TABLE (PREFIX_0FF7) },
3141   /* f8 */
3142   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3143   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3144   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3145   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3146   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3147   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3148   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3149   { "ud0S",             { Gv, Ev }, 0 },
3150 };
3151
3152 static const unsigned char onebyte_has_modrm[256] = {
3153   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3154   /*       -------------------------------        */
3155   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3156   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3157   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3158   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3159   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3160   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3161   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3162   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3163   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3164   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3165   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3166   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3167   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3168   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3169   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3170   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3171   /*       -------------------------------        */
3172   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3173 };
3174
3175 static const unsigned char twobyte_has_modrm[256] = {
3176   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3177   /*       -------------------------------        */
3178   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3179   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3180   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3181   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3182   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3183   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3184   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3185   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3186   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3187   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3188   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3189   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
3190   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3191   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3192   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3193   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
3194   /*       -------------------------------        */
3195   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3196 };
3197
3198 static char obuf[100];
3199 static char *obufp;
3200 static char *mnemonicendp;
3201 static char scratchbuf[100];
3202 static unsigned char *start_codep;
3203 static unsigned char *insn_codep;
3204 static unsigned char *codep;
3205 static unsigned char *end_codep;
3206 static int last_lock_prefix;
3207 static int last_repz_prefix;
3208 static int last_repnz_prefix;
3209 static int last_data_prefix;
3210 static int last_addr_prefix;
3211 static int last_rex_prefix;
3212 static int last_seg_prefix;
3213 static int fwait_prefix;
3214 /* The active segment register prefix.  */
3215 static int active_seg_prefix;
3216 #define MAX_CODE_LENGTH 15
3217 /* We can up to 14 prefixes since the maximum instruction length is
3218    15bytes.  */
3219 static int all_prefixes[MAX_CODE_LENGTH - 1];
3220 static disassemble_info *the_info;
3221 static struct
3222   {
3223     int mod;
3224     int reg;
3225     int rm;
3226   }
3227 modrm;
3228 static unsigned char need_modrm;
3229 static struct
3230   {
3231     int scale;
3232     int index;
3233     int base;
3234   }
3235 sib;
3236 static struct
3237   {
3238     int register_specifier;
3239     int length;
3240     int prefix;
3241     int w;
3242     int evex;
3243     int r;
3244     int v;
3245     int mask_register_specifier;
3246     int zeroing;
3247     int ll;
3248     int b;
3249   }
3250 vex;
3251 static unsigned char need_vex;
3252 static unsigned char need_vex_reg;
3253 static unsigned char vex_w_done;
3254
3255 struct op
3256   {
3257     const char *name;
3258     unsigned int len;
3259   };
3260
3261 /* If we are accessing mod/rm/reg without need_modrm set, then the
3262    values are stale.  Hitting this abort likely indicates that you
3263    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3264 #define MODRM_CHECK  if (!need_modrm) abort ()
3265
3266 static const char **names64;
3267 static const char **names32;
3268 static const char **names16;
3269 static const char **names8;
3270 static const char **names8rex;
3271 static const char **names_seg;
3272 static const char *index64;
3273 static const char *index32;
3274 static const char **index16;
3275 static const char **names_bnd;
3276
3277 static const char *intel_names64[] = {
3278   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3279   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3280 };
3281 static const char *intel_names32[] = {
3282   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3283   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3284 };
3285 static const char *intel_names16[] = {
3286   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3287   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3288 };
3289 static const char *intel_names8[] = {
3290   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3291 };
3292 static const char *intel_names8rex[] = {
3293   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3294   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3295 };
3296 static const char *intel_names_seg[] = {
3297   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3298 };
3299 static const char *intel_index64 = "riz";
3300 static const char *intel_index32 = "eiz";
3301 static const char *intel_index16[] = {
3302   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3303 };
3304
3305 static const char *att_names64[] = {
3306   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3307   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3308 };
3309 static const char *att_names32[] = {
3310   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3311   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3312 };
3313 static const char *att_names16[] = {
3314   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3315   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3316 };
3317 static const char *att_names8[] = {
3318   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3319 };
3320 static const char *att_names8rex[] = {
3321   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3322   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3323 };
3324 static const char *att_names_seg[] = {
3325   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3326 };
3327 static const char *att_index64 = "%riz";
3328 static const char *att_index32 = "%eiz";
3329 static const char *att_index16[] = {
3330   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3331 };
3332
3333 static const char **names_mm;
3334 static const char *intel_names_mm[] = {
3335   "mm0", "mm1", "mm2", "mm3",
3336   "mm4", "mm5", "mm6", "mm7"
3337 };
3338 static const char *att_names_mm[] = {
3339   "%mm0", "%mm1", "%mm2", "%mm3",
3340   "%mm4", "%mm5", "%mm6", "%mm7"
3341 };
3342
3343 static const char *intel_names_bnd[] = {
3344   "bnd0", "bnd1", "bnd2", "bnd3"
3345 };
3346
3347 static const char *att_names_bnd[] = {
3348   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3349 };
3350
3351 static const char **names_xmm;
3352 static const char *intel_names_xmm[] = {
3353   "xmm0", "xmm1", "xmm2", "xmm3",
3354   "xmm4", "xmm5", "xmm6", "xmm7",
3355   "xmm8", "xmm9", "xmm10", "xmm11",
3356   "xmm12", "xmm13", "xmm14", "xmm15",
3357   "xmm16", "xmm17", "xmm18", "xmm19",
3358   "xmm20", "xmm21", "xmm22", "xmm23",
3359   "xmm24", "xmm25", "xmm26", "xmm27",
3360   "xmm28", "xmm29", "xmm30", "xmm31"
3361 };
3362 static const char *att_names_xmm[] = {
3363   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3364   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3365   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3366   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3367   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3368   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3369   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3370   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3371 };
3372
3373 static const char **names_ymm;
3374 static const char *intel_names_ymm[] = {
3375   "ymm0", "ymm1", "ymm2", "ymm3",
3376   "ymm4", "ymm5", "ymm6", "ymm7",
3377   "ymm8", "ymm9", "ymm10", "ymm11",
3378   "ymm12", "ymm13", "ymm14", "ymm15",
3379   "ymm16", "ymm17", "ymm18", "ymm19",
3380   "ymm20", "ymm21", "ymm22", "ymm23",
3381   "ymm24", "ymm25", "ymm26", "ymm27",
3382   "ymm28", "ymm29", "ymm30", "ymm31"
3383 };
3384 static const char *att_names_ymm[] = {
3385   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3386   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3387   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3388   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3389   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3390   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3391   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3392   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3393 };
3394
3395 static const char **names_zmm;
3396 static const char *intel_names_zmm[] = {
3397   "zmm0", "zmm1", "zmm2", "zmm3",
3398   "zmm4", "zmm5", "zmm6", "zmm7",
3399   "zmm8", "zmm9", "zmm10", "zmm11",
3400   "zmm12", "zmm13", "zmm14", "zmm15",
3401   "zmm16", "zmm17", "zmm18", "zmm19",
3402   "zmm20", "zmm21", "zmm22", "zmm23",
3403   "zmm24", "zmm25", "zmm26", "zmm27",
3404   "zmm28", "zmm29", "zmm30", "zmm31"
3405 };
3406 static const char *att_names_zmm[] = {
3407   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3408   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3409   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3410   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3411   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3412   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3413   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3414   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3415 };
3416
3417 static const char **names_mask;
3418 static const char *intel_names_mask[] = {
3419   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3420 };
3421 static const char *att_names_mask[] = {
3422   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3423 };
3424
3425 static const char *names_rounding[] =
3426 {
3427   "{rn-sae}",
3428   "{rd-sae}",
3429   "{ru-sae}",
3430   "{rz-sae}"
3431 };
3432
3433 static const struct dis386 reg_table[][8] = {
3434   /* REG_80 */
3435   {
3436     { "addA",   { Ebh1, Ib }, 0 },
3437     { "orA",    { Ebh1, Ib }, 0 },
3438     { "adcA",   { Ebh1, Ib }, 0 },
3439     { "sbbA",   { Ebh1, Ib }, 0 },
3440     { "andA",   { Ebh1, Ib }, 0 },
3441     { "subA",   { Ebh1, Ib }, 0 },
3442     { "xorA",   { Ebh1, Ib }, 0 },
3443     { "cmpA",   { Eb, Ib }, 0 },
3444   },
3445   /* REG_81 */
3446   {
3447     { "addQ",   { Evh1, Iv }, 0 },
3448     { "orQ",    { Evh1, Iv }, 0 },
3449     { "adcQ",   { Evh1, Iv }, 0 },
3450     { "sbbQ",   { Evh1, Iv }, 0 },
3451     { "andQ",   { Evh1, Iv }, 0 },
3452     { "subQ",   { Evh1, Iv }, 0 },
3453     { "xorQ",   { Evh1, Iv }, 0 },
3454     { "cmpQ",   { Ev, Iv }, 0 },
3455   },
3456   /* REG_83 */
3457   {
3458     { "addQ",   { Evh1, sIb }, 0 },
3459     { "orQ",    { Evh1, sIb }, 0 },
3460     { "adcQ",   { Evh1, sIb }, 0 },
3461     { "sbbQ",   { Evh1, sIb }, 0 },
3462     { "andQ",   { Evh1, sIb }, 0 },
3463     { "subQ",   { Evh1, sIb }, 0 },
3464     { "xorQ",   { Evh1, sIb }, 0 },
3465     { "cmpQ",   { Ev, sIb }, 0 },
3466   },
3467   /* REG_8F */
3468   {
3469     { "popU",   { stackEv }, 0 },
3470     { XOP_8F_TABLE (XOP_09) },
3471     { Bad_Opcode },
3472     { Bad_Opcode },
3473     { Bad_Opcode },
3474     { XOP_8F_TABLE (XOP_09) },
3475   },
3476   /* REG_C0 */
3477   {
3478     { "rolA",   { Eb, Ib }, 0 },
3479     { "rorA",   { Eb, Ib }, 0 },
3480     { "rclA",   { Eb, Ib }, 0 },
3481     { "rcrA",   { Eb, Ib }, 0 },
3482     { "shlA",   { Eb, Ib }, 0 },
3483     { "shrA",   { Eb, Ib }, 0 },
3484     { "shlA",   { Eb, Ib }, 0 },
3485     { "sarA",   { Eb, Ib }, 0 },
3486   },
3487   /* REG_C1 */
3488   {
3489     { "rolQ",   { Ev, Ib }, 0 },
3490     { "rorQ",   { Ev, Ib }, 0 },
3491     { "rclQ",   { Ev, Ib }, 0 },
3492     { "rcrQ",   { Ev, Ib }, 0 },
3493     { "shlQ",   { Ev, Ib }, 0 },
3494     { "shrQ",   { Ev, Ib }, 0 },
3495     { "shlQ",   { Ev, Ib }, 0 },
3496     { "sarQ",   { Ev, Ib }, 0 },
3497   },
3498   /* REG_C6 */
3499   {
3500     { "movA",   { Ebh3, Ib }, 0 },
3501     { Bad_Opcode },
3502     { Bad_Opcode },
3503     { Bad_Opcode },
3504     { Bad_Opcode },
3505     { Bad_Opcode },
3506     { Bad_Opcode },
3507     { MOD_TABLE (MOD_C6_REG_7) },
3508   },
3509   /* REG_C7 */
3510   {
3511     { "movQ",   { Evh3, Iv }, 0 },
3512     { Bad_Opcode },
3513     { Bad_Opcode },
3514     { Bad_Opcode },
3515     { Bad_Opcode },
3516     { Bad_Opcode },
3517     { Bad_Opcode },
3518     { MOD_TABLE (MOD_C7_REG_7) },
3519   },
3520   /* REG_D0 */
3521   {
3522     { "rolA",   { Eb, I1 }, 0 },
3523     { "rorA",   { Eb, I1 }, 0 },
3524     { "rclA",   { Eb, I1 }, 0 },
3525     { "rcrA",   { Eb, I1 }, 0 },
3526     { "shlA",   { Eb, I1 }, 0 },
3527     { "shrA",   { Eb, I1 }, 0 },
3528     { "shlA",   { Eb, I1 }, 0 },
3529     { "sarA",   { Eb, I1 }, 0 },
3530   },
3531   /* REG_D1 */
3532   {
3533     { "rolQ",   { Ev, I1 }, 0 },
3534     { "rorQ",   { Ev, I1 }, 0 },
3535     { "rclQ",   { Ev, I1 }, 0 },
3536     { "rcrQ",   { Ev, I1 }, 0 },
3537     { "shlQ",   { Ev, I1 }, 0 },
3538     { "shrQ",   { Ev, I1 }, 0 },
3539     { "shlQ",   { Ev, I1 }, 0 },
3540     { "sarQ",   { Ev, I1 }, 0 },
3541   },
3542   /* REG_D2 */
3543   {
3544     { "rolA",   { Eb, CL }, 0 },
3545     { "rorA",   { Eb, CL }, 0 },
3546     { "rclA",   { Eb, CL }, 0 },
3547     { "rcrA",   { Eb, CL }, 0 },
3548     { "shlA",   { Eb, CL }, 0 },
3549     { "shrA",   { Eb, CL }, 0 },
3550     { "shlA",   { Eb, CL }, 0 },
3551     { "sarA",   { Eb, CL }, 0 },
3552   },
3553   /* REG_D3 */
3554   {
3555     { "rolQ",   { Ev, CL }, 0 },
3556     { "rorQ",   { Ev, CL }, 0 },
3557     { "rclQ",   { Ev, CL }, 0 },
3558     { "rcrQ",   { Ev, CL }, 0 },
3559     { "shlQ",   { Ev, CL }, 0 },
3560     { "shrQ",   { Ev, CL }, 0 },
3561     { "shlQ",   { Ev, CL }, 0 },
3562     { "sarQ",   { Ev, CL }, 0 },
3563   },
3564   /* REG_F6 */
3565   {
3566     { "testA",  { Eb, Ib }, 0 },
3567     { "testA",  { Eb, Ib }, 0 },
3568     { "notA",   { Ebh1 }, 0 },
3569     { "negA",   { Ebh1 }, 0 },
3570     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3571     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3572     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3573     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3574   },
3575   /* REG_F7 */
3576   {
3577     { "testQ",  { Ev, Iv }, 0 },
3578     { "testQ",  { Ev, Iv }, 0 },
3579     { "notQ",   { Evh1 }, 0 },
3580     { "negQ",   { Evh1 }, 0 },
3581     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3582     { "imulQ",  { Ev }, 0 },
3583     { "divQ",   { Ev }, 0 },
3584     { "idivQ",  { Ev }, 0 },
3585   },
3586   /* REG_FE */
3587   {
3588     { "incA",   { Ebh1 }, 0 },
3589     { "decA",   { Ebh1 }, 0 },
3590   },
3591   /* REG_FF */
3592   {
3593     { "incQ",   { Evh1 }, 0 },
3594     { "decQ",   { Evh1 }, 0 },
3595     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3596     { MOD_TABLE (MOD_FF_REG_3) },
3597     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3598     { MOD_TABLE (MOD_FF_REG_5) },
3599     { "pushU",  { stackEv }, 0 },
3600     { Bad_Opcode },
3601   },
3602   /* REG_0F00 */
3603   {
3604     { "sldtD",  { Sv }, 0 },
3605     { "strD",   { Sv }, 0 },
3606     { "lldt",   { Ew }, 0 },
3607     { "ltr",    { Ew }, 0 },
3608     { "verr",   { Ew }, 0 },
3609     { "verw",   { Ew }, 0 },
3610     { Bad_Opcode },
3611     { Bad_Opcode },
3612   },
3613   /* REG_0F01 */
3614   {
3615     { MOD_TABLE (MOD_0F01_REG_0) },
3616     { MOD_TABLE (MOD_0F01_REG_1) },
3617     { MOD_TABLE (MOD_0F01_REG_2) },
3618     { MOD_TABLE (MOD_0F01_REG_3) },
3619     { "smswD",  { Sv }, 0 },
3620     { MOD_TABLE (MOD_0F01_REG_5) },
3621     { "lmsw",   { Ew }, 0 },
3622     { MOD_TABLE (MOD_0F01_REG_7) },
3623   },
3624   /* REG_0F0D */
3625   {
3626     { "prefetch",       { Mb }, 0 },
3627     { "prefetchw",      { Mb }, 0 },
3628     { "prefetchwt1",    { Mb }, 0 },
3629     { "prefetch",       { Mb }, 0 },
3630     { "prefetch",       { Mb }, 0 },
3631     { "prefetch",       { Mb }, 0 },
3632     { "prefetch",       { Mb }, 0 },
3633     { "prefetch",       { Mb }, 0 },
3634   },
3635   /* REG_0F18 */
3636   {
3637     { MOD_TABLE (MOD_0F18_REG_0) },
3638     { MOD_TABLE (MOD_0F18_REG_1) },
3639     { MOD_TABLE (MOD_0F18_REG_2) },
3640     { MOD_TABLE (MOD_0F18_REG_3) },
3641     { MOD_TABLE (MOD_0F18_REG_4) },
3642     { MOD_TABLE (MOD_0F18_REG_5) },
3643     { MOD_TABLE (MOD_0F18_REG_6) },
3644     { MOD_TABLE (MOD_0F18_REG_7) },
3645   },
3646   /* REG_0F1E_MOD_3 */
3647   {
3648     { "nopQ",           { Ev }, 0 },
3649     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3650     { "nopQ",           { Ev }, 0 },
3651     { "nopQ",           { Ev }, 0 },
3652     { "nopQ",           { Ev }, 0 },
3653     { "nopQ",           { Ev }, 0 },
3654     { "nopQ",           { Ev }, 0 },
3655     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3656   },
3657   /* REG_0F71 */
3658   {
3659     { Bad_Opcode },
3660     { Bad_Opcode },
3661     { MOD_TABLE (MOD_0F71_REG_2) },
3662     { Bad_Opcode },
3663     { MOD_TABLE (MOD_0F71_REG_4) },
3664     { Bad_Opcode },
3665     { MOD_TABLE (MOD_0F71_REG_6) },
3666   },
3667   /* REG_0F72 */
3668   {
3669     { Bad_Opcode },
3670     { Bad_Opcode },
3671     { MOD_TABLE (MOD_0F72_REG_2) },
3672     { Bad_Opcode },
3673     { MOD_TABLE (MOD_0F72_REG_4) },
3674     { Bad_Opcode },
3675     { MOD_TABLE (MOD_0F72_REG_6) },
3676   },
3677   /* REG_0F73 */
3678   {
3679     { Bad_Opcode },
3680     { Bad_Opcode },
3681     { MOD_TABLE (MOD_0F73_REG_2) },
3682     { MOD_TABLE (MOD_0F73_REG_3) },
3683     { Bad_Opcode },
3684     { Bad_Opcode },
3685     { MOD_TABLE (MOD_0F73_REG_6) },
3686     { MOD_TABLE (MOD_0F73_REG_7) },
3687   },
3688   /* REG_0FA6 */
3689   {
3690     { "montmul",        { { OP_0f07, 0 } }, 0 },
3691     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3692     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3693   },
3694   /* REG_0FA7 */
3695   {
3696     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3697     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3698     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3699     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3700     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3701     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3702   },
3703   /* REG_0FAE */
3704   {
3705     { MOD_TABLE (MOD_0FAE_REG_0) },
3706     { MOD_TABLE (MOD_0FAE_REG_1) },
3707     { MOD_TABLE (MOD_0FAE_REG_2) },
3708     { MOD_TABLE (MOD_0FAE_REG_3) },
3709     { MOD_TABLE (MOD_0FAE_REG_4) },
3710     { MOD_TABLE (MOD_0FAE_REG_5) },
3711     { MOD_TABLE (MOD_0FAE_REG_6) },
3712     { MOD_TABLE (MOD_0FAE_REG_7) },
3713   },
3714   /* REG_0FBA */
3715   {
3716     { Bad_Opcode },
3717     { Bad_Opcode },
3718     { Bad_Opcode },
3719     { Bad_Opcode },
3720     { "btQ",    { Ev, Ib }, 0 },
3721     { "btsQ",   { Evh1, Ib }, 0 },
3722     { "btrQ",   { Evh1, Ib }, 0 },
3723     { "btcQ",   { Evh1, Ib }, 0 },
3724   },
3725   /* REG_0FC7 */
3726   {
3727     { Bad_Opcode },
3728     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3729     { Bad_Opcode },
3730     { MOD_TABLE (MOD_0FC7_REG_3) },
3731     { MOD_TABLE (MOD_0FC7_REG_4) },
3732     { MOD_TABLE (MOD_0FC7_REG_5) },
3733     { MOD_TABLE (MOD_0FC7_REG_6) },
3734     { MOD_TABLE (MOD_0FC7_REG_7) },
3735   },
3736   /* REG_VEX_0F71 */
3737   {
3738     { Bad_Opcode },
3739     { Bad_Opcode },
3740     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3741     { Bad_Opcode },
3742     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3743     { Bad_Opcode },
3744     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3745   },
3746   /* REG_VEX_0F72 */
3747   {
3748     { Bad_Opcode },
3749     { Bad_Opcode },
3750     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3751     { Bad_Opcode },
3752     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3753     { Bad_Opcode },
3754     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3755   },
3756   /* REG_VEX_0F73 */
3757   {
3758     { Bad_Opcode },
3759     { Bad_Opcode },
3760     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3761     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3762     { Bad_Opcode },
3763     { Bad_Opcode },
3764     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3765     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3766   },
3767   /* REG_VEX_0FAE */
3768   {
3769     { Bad_Opcode },
3770     { Bad_Opcode },
3771     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3772     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3773   },
3774   /* REG_VEX_0F38F3 */
3775   {
3776     { Bad_Opcode },
3777     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3778     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3779     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3780   },
3781   /* REG_XOP_LWPCB */
3782   {
3783     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3784     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3785   },
3786   /* REG_XOP_LWP */
3787   {
3788     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3789     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3790   },
3791   /* REG_XOP_TBM_01 */
3792   {
3793     { Bad_Opcode },
3794     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3795     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3796     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3797     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3798     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3799     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3800     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3801   },
3802   /* REG_XOP_TBM_02 */
3803   {
3804     { Bad_Opcode },
3805     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3806     { Bad_Opcode },
3807     { Bad_Opcode },
3808     { Bad_Opcode },
3809     { Bad_Opcode },
3810     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3811   },
3812 #define NEED_REG_TABLE
3813 #include "i386-dis-evex.h"
3814 #undef NEED_REG_TABLE
3815 };
3816
3817 static const struct dis386 prefix_table[][4] = {
3818   /* PREFIX_90 */
3819   {
3820     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3821     { "pause", { XX }, 0 },
3822     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3823     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3824   },
3825
3826   /* PREFIX_MOD_0_0F01_REG_5 */
3827   {
3828     { Bad_Opcode },
3829     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3830   },
3831
3832   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3833   {
3834     { Bad_Opcode },
3835     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3836   },
3837
3838   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3839   {
3840     { Bad_Opcode },
3841     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3842   },
3843
3844   /* PREFIX_0F09 */
3845   {
3846     { "wbinvd",   { XX }, 0 },
3847     { "wbnoinvd", { XX }, 0 },
3848   },
3849
3850   /* PREFIX_0F10 */
3851   {
3852     { "movups", { XM, EXx }, PREFIX_OPCODE },
3853     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3854     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3855     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3856   },
3857
3858   /* PREFIX_0F11 */
3859   {
3860     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3861     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3862     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3863     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3864   },
3865
3866   /* PREFIX_0F12 */
3867   {
3868     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3869     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3870     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3871     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3872   },
3873
3874   /* PREFIX_0F16 */
3875   {
3876     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3877     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3878     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3879   },
3880
3881   /* PREFIX_0F1A */
3882   {
3883     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3884     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3885     { "bndmov", { Gbnd, Ebnd }, 0 },
3886     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3887   },
3888
3889   /* PREFIX_0F1B */
3890   {
3891     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3892     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3893     { "bndmov", { Ebnd, Gbnd }, 0 },
3894     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3895   },
3896
3897   /* PREFIX_0F1E */
3898   {
3899     { "nopQ",   { Ev }, PREFIX_OPCODE },
3900     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3901     { "nopQ",   { Ev }, PREFIX_OPCODE },
3902     { "nopQ",   { Ev }, PREFIX_OPCODE },
3903   },
3904
3905   /* PREFIX_0F2A */
3906   {
3907     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3908     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3909     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3910     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3911   },
3912
3913   /* PREFIX_0F2B */
3914   {
3915     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3916     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3917     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3918     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3919   },
3920
3921   /* PREFIX_0F2C */
3922   {
3923     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3924     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3925     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3926     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3927   },
3928
3929   /* PREFIX_0F2D */
3930   {
3931     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3932     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3933     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3934     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3935   },
3936
3937   /* PREFIX_0F2E */
3938   {
3939     { "ucomiss",{ XM, EXd }, 0 },
3940     { Bad_Opcode },
3941     { "ucomisd",{ XM, EXq }, 0 },
3942   },
3943
3944   /* PREFIX_0F2F */
3945   {
3946     { "comiss", { XM, EXd }, 0 },
3947     { Bad_Opcode },
3948     { "comisd", { XM, EXq }, 0 },
3949   },
3950
3951   /* PREFIX_0F51 */
3952   {
3953     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3954     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3955     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3956     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3957   },
3958
3959   /* PREFIX_0F52 */
3960   {
3961     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3962     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3963   },
3964
3965   /* PREFIX_0F53 */
3966   {
3967     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3968     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3969   },
3970
3971   /* PREFIX_0F58 */
3972   {
3973     { "addps", { XM, EXx }, PREFIX_OPCODE },
3974     { "addss", { XM, EXd }, PREFIX_OPCODE },
3975     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3976     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3977   },
3978
3979   /* PREFIX_0F59 */
3980   {
3981     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3982     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3983     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3984     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3985   },
3986
3987   /* PREFIX_0F5A */
3988   {
3989     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3990     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3991     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3992     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3993   },
3994
3995   /* PREFIX_0F5B */
3996   {
3997     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3998     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3999     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
4000   },
4001
4002   /* PREFIX_0F5C */
4003   {
4004     { "subps",  { XM, EXx }, PREFIX_OPCODE },
4005     { "subss",  { XM, EXd }, PREFIX_OPCODE },
4006     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
4007     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
4008   },
4009
4010   /* PREFIX_0F5D */
4011   {
4012     { "minps",  { XM, EXx }, PREFIX_OPCODE },
4013     { "minss",  { XM, EXd }, PREFIX_OPCODE },
4014     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
4015     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
4016   },
4017
4018   /* PREFIX_0F5E */
4019   {
4020     { "divps",  { XM, EXx }, PREFIX_OPCODE },
4021     { "divss",  { XM, EXd }, PREFIX_OPCODE },
4022     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
4023     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
4024   },
4025
4026   /* PREFIX_0F5F */
4027   {
4028     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
4029     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
4030     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
4031     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
4032   },
4033
4034   /* PREFIX_0F60 */
4035   {
4036     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
4037     { Bad_Opcode },
4038     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
4039   },
4040
4041   /* PREFIX_0F61 */
4042   {
4043     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
4044     { Bad_Opcode },
4045     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4046   },
4047
4048   /* PREFIX_0F62 */
4049   {
4050     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4051     { Bad_Opcode },
4052     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4053   },
4054
4055   /* PREFIX_0F6C */
4056   {
4057     { Bad_Opcode },
4058     { Bad_Opcode },
4059     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4060   },
4061
4062   /* PREFIX_0F6D */
4063   {
4064     { Bad_Opcode },
4065     { Bad_Opcode },
4066     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4067   },
4068
4069   /* PREFIX_0F6F */
4070   {
4071     { "movq",   { MX, EM }, PREFIX_OPCODE },
4072     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4073     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4074   },
4075
4076   /* PREFIX_0F70 */
4077   {
4078     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4079     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4080     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4081     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4082   },
4083
4084   /* PREFIX_0F73_REG_3 */
4085   {
4086     { Bad_Opcode },
4087     { Bad_Opcode },
4088     { "psrldq", { XS, Ib }, 0 },
4089   },
4090
4091   /* PREFIX_0F73_REG_7 */
4092   {
4093     { Bad_Opcode },
4094     { Bad_Opcode },
4095     { "pslldq", { XS, Ib }, 0 },
4096   },
4097
4098   /* PREFIX_0F78 */
4099   {
4100     {"vmread",  { Em, Gm }, 0 },
4101     { Bad_Opcode },
4102     {"extrq",   { XS, Ib, Ib }, 0 },
4103     {"insertq", { XM, XS, Ib, Ib }, 0 },
4104   },
4105
4106   /* PREFIX_0F79 */
4107   {
4108     {"vmwrite", { Gm, Em }, 0 },
4109     { Bad_Opcode },
4110     {"extrq",   { XM, XS }, 0 },
4111     {"insertq", { XM, XS }, 0 },
4112   },
4113
4114   /* PREFIX_0F7C */
4115   {
4116     { Bad_Opcode },
4117     { Bad_Opcode },
4118     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4119     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4120   },
4121
4122   /* PREFIX_0F7D */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4127     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4128   },
4129
4130   /* PREFIX_0F7E */
4131   {
4132     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4133     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4134     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4135   },
4136
4137   /* PREFIX_0F7F */
4138   {
4139     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4140     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4141     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4142   },
4143
4144   /* PREFIX_0FAE_REG_0 */
4145   {
4146     { Bad_Opcode },
4147     { "rdfsbase", { Ev }, 0 },
4148   },
4149
4150   /* PREFIX_0FAE_REG_1 */
4151   {
4152     { Bad_Opcode },
4153     { "rdgsbase", { Ev }, 0 },
4154   },
4155
4156   /* PREFIX_0FAE_REG_2 */
4157   {
4158     { Bad_Opcode },
4159     { "wrfsbase", { Ev }, 0 },
4160   },
4161
4162   /* PREFIX_0FAE_REG_3 */
4163   {
4164     { Bad_Opcode },
4165     { "wrgsbase", { Ev }, 0 },
4166   },
4167
4168   /* PREFIX_MOD_0_0FAE_REG_4 */
4169   {
4170     { "xsave",  { FXSAVE }, 0 },
4171     { "ptwrite%LQ", { Edq }, 0 },
4172   },
4173
4174   /* PREFIX_MOD_3_0FAE_REG_4 */
4175   {
4176     { Bad_Opcode },
4177     { "ptwrite%LQ", { Edq }, 0 },
4178   },
4179
4180   /* PREFIX_MOD_0_0FAE_REG_5 */
4181   {
4182     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4183   },
4184
4185   /* PREFIX_MOD_3_0FAE_REG_5 */
4186   {
4187     { "lfence",         { Skip_MODRM }, 0 },
4188     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4189   },
4190
4191   /* PREFIX_0FAE_REG_6 */
4192   {
4193     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4194     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4195     { "clwb",   { Mb }, PREFIX_OPCODE },
4196   },
4197
4198   /* PREFIX_0FAE_REG_7 */
4199   {
4200     { "clflush",        { Mb }, 0 },
4201     { Bad_Opcode },
4202     { "clflushopt",     { Mb }, 0 },
4203   },
4204
4205   /* PREFIX_0FB8 */
4206   {
4207     { Bad_Opcode },
4208     { "popcntS", { Gv, Ev }, 0 },
4209   },
4210
4211   /* PREFIX_0FBC */
4212   {
4213     { "bsfS",   { Gv, Ev }, 0 },
4214     { "tzcntS", { Gv, Ev }, 0 },
4215     { "bsfS",   { Gv, Ev }, 0 },
4216   },
4217
4218   /* PREFIX_0FBD */
4219   {
4220     { "bsrS",   { Gv, Ev }, 0 },
4221     { "lzcntS", { Gv, Ev }, 0 },
4222     { "bsrS",   { Gv, Ev }, 0 },
4223   },
4224
4225   /* PREFIX_0FC2 */
4226   {
4227     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4228     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4229     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4230     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4231   },
4232
4233   /* PREFIX_MOD_0_0FC3 */
4234   {
4235     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4236   },
4237
4238   /* PREFIX_MOD_0_0FC7_REG_6 */
4239   {
4240     { "vmptrld",{ Mq }, 0 },
4241     { "vmxon",  { Mq }, 0 },
4242     { "vmclear",{ Mq }, 0 },
4243   },
4244
4245   /* PREFIX_MOD_3_0FC7_REG_6 */
4246   {
4247     { "rdrand", { Ev }, 0 },
4248     { Bad_Opcode },
4249     { "rdrand", { Ev }, 0 }
4250   },
4251
4252   /* PREFIX_MOD_3_0FC7_REG_7 */
4253   {
4254     { "rdseed", { Ev }, 0 },
4255     { "rdpid",  { Em }, 0 },
4256     { "rdseed", { Ev }, 0 },
4257   },
4258
4259   /* PREFIX_0FD0 */
4260   {
4261     { Bad_Opcode },
4262     { Bad_Opcode },
4263     { "addsubpd", { XM, EXx }, 0 },
4264     { "addsubps", { XM, EXx }, 0 },
4265   },
4266
4267   /* PREFIX_0FD6 */
4268   {
4269     { Bad_Opcode },
4270     { "movq2dq",{ XM, MS }, 0 },
4271     { "movq",   { EXqS, XM }, 0 },
4272     { "movdq2q",{ MX, XS }, 0 },
4273   },
4274
4275   /* PREFIX_0FE6 */
4276   {
4277     { Bad_Opcode },
4278     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4279     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4280     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4281   },
4282
4283   /* PREFIX_0FE7 */
4284   {
4285     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4286     { Bad_Opcode },
4287     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4288   },
4289
4290   /* PREFIX_0FF0 */
4291   {
4292     { Bad_Opcode },
4293     { Bad_Opcode },
4294     { Bad_Opcode },
4295     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4296   },
4297
4298   /* PREFIX_0FF7 */
4299   {
4300     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4301     { Bad_Opcode },
4302     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4303   },
4304
4305   /* PREFIX_0F3810 */
4306   {
4307     { Bad_Opcode },
4308     { Bad_Opcode },
4309     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4310   },
4311
4312   /* PREFIX_0F3814 */
4313   {
4314     { Bad_Opcode },
4315     { Bad_Opcode },
4316     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4317   },
4318
4319   /* PREFIX_0F3815 */
4320   {
4321     { Bad_Opcode },
4322     { Bad_Opcode },
4323     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4324   },
4325
4326   /* PREFIX_0F3817 */
4327   {
4328     { Bad_Opcode },
4329     { Bad_Opcode },
4330     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4331   },
4332
4333   /* PREFIX_0F3820 */
4334   {
4335     { Bad_Opcode },
4336     { Bad_Opcode },
4337     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4338   },
4339
4340   /* PREFIX_0F3821 */
4341   {
4342     { Bad_Opcode },
4343     { Bad_Opcode },
4344     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4345   },
4346
4347   /* PREFIX_0F3822 */
4348   {
4349     { Bad_Opcode },
4350     { Bad_Opcode },
4351     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4352   },
4353
4354   /* PREFIX_0F3823 */
4355   {
4356     { Bad_Opcode },
4357     { Bad_Opcode },
4358     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4359   },
4360
4361   /* PREFIX_0F3824 */
4362   {
4363     { Bad_Opcode },
4364     { Bad_Opcode },
4365     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4366   },
4367
4368   /* PREFIX_0F3825 */
4369   {
4370     { Bad_Opcode },
4371     { Bad_Opcode },
4372     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4373   },
4374
4375   /* PREFIX_0F3828 */
4376   {
4377     { Bad_Opcode },
4378     { Bad_Opcode },
4379     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4380   },
4381
4382   /* PREFIX_0F3829 */
4383   {
4384     { Bad_Opcode },
4385     { Bad_Opcode },
4386     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4387   },
4388
4389   /* PREFIX_0F382A */
4390   {
4391     { Bad_Opcode },
4392     { Bad_Opcode },
4393     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4394   },
4395
4396   /* PREFIX_0F382B */
4397   {
4398     { Bad_Opcode },
4399     { Bad_Opcode },
4400     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4401   },
4402
4403   /* PREFIX_0F3830 */
4404   {
4405     { Bad_Opcode },
4406     { Bad_Opcode },
4407     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4408   },
4409
4410   /* PREFIX_0F3831 */
4411   {
4412     { Bad_Opcode },
4413     { Bad_Opcode },
4414     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4415   },
4416
4417   /* PREFIX_0F3832 */
4418   {
4419     { Bad_Opcode },
4420     { Bad_Opcode },
4421     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4422   },
4423
4424   /* PREFIX_0F3833 */
4425   {
4426     { Bad_Opcode },
4427     { Bad_Opcode },
4428     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4429   },
4430
4431   /* PREFIX_0F3834 */
4432   {
4433     { Bad_Opcode },
4434     { Bad_Opcode },
4435     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4436   },
4437
4438   /* PREFIX_0F3835 */
4439   {
4440     { Bad_Opcode },
4441     { Bad_Opcode },
4442     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4443   },
4444
4445   /* PREFIX_0F3837 */
4446   {
4447     { Bad_Opcode },
4448     { Bad_Opcode },
4449     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4450   },
4451
4452   /* PREFIX_0F3838 */
4453   {
4454     { Bad_Opcode },
4455     { Bad_Opcode },
4456     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4457   },
4458
4459   /* PREFIX_0F3839 */
4460   {
4461     { Bad_Opcode },
4462     { Bad_Opcode },
4463     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4464   },
4465
4466   /* PREFIX_0F383A */
4467   {
4468     { Bad_Opcode },
4469     { Bad_Opcode },
4470     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4471   },
4472
4473   /* PREFIX_0F383B */
4474   {
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4478   },
4479
4480   /* PREFIX_0F383C */
4481   {
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4485   },
4486
4487   /* PREFIX_0F383D */
4488   {
4489     { Bad_Opcode },
4490     { Bad_Opcode },
4491     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4492   },
4493
4494   /* PREFIX_0F383E */
4495   {
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4499   },
4500
4501   /* PREFIX_0F383F */
4502   {
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4506   },
4507
4508   /* PREFIX_0F3840 */
4509   {
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4513   },
4514
4515   /* PREFIX_0F3841 */
4516   {
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4520   },
4521
4522   /* PREFIX_0F3880 */
4523   {
4524     { Bad_Opcode },
4525     { Bad_Opcode },
4526     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4527   },
4528
4529   /* PREFIX_0F3881 */
4530   {
4531     { Bad_Opcode },
4532     { Bad_Opcode },
4533     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4534   },
4535
4536   /* PREFIX_0F3882 */
4537   {
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4541   },
4542
4543   /* PREFIX_0F38C8 */
4544   {
4545     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4546   },
4547
4548   /* PREFIX_0F38C9 */
4549   {
4550     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4551   },
4552
4553   /* PREFIX_0F38CA */
4554   {
4555     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4556   },
4557
4558   /* PREFIX_0F38CB */
4559   {
4560     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4561   },
4562
4563   /* PREFIX_0F38CC */
4564   {
4565     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4566   },
4567
4568   /* PREFIX_0F38CD */
4569   {
4570     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F38CF */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4578   },
4579
4580   /* PREFIX_0F38DB */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4585   },
4586
4587   /* PREFIX_0F38DC */
4588   {
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4592   },
4593
4594   /* PREFIX_0F38DD */
4595   {
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4599   },
4600
4601   /* PREFIX_0F38DE */
4602   {
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4606   },
4607
4608   /* PREFIX_0F38DF */
4609   {
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4613   },
4614
4615   /* PREFIX_0F38F0 */
4616   {
4617     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4618     { Bad_Opcode },
4619     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4620     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4621   },
4622
4623   /* PREFIX_0F38F1 */
4624   {
4625     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4626     { Bad_Opcode },
4627     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4628     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4629   },
4630
4631   /* PREFIX_0F38F5 */
4632   {
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4636   },
4637
4638   /* PREFIX_0F38F6 */
4639   {
4640     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4641     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4642     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4643     { Bad_Opcode },
4644   },
4645
4646   /* PREFIX_0F3A08 */
4647   {
4648     { Bad_Opcode },
4649     { Bad_Opcode },
4650     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4651   },
4652
4653   /* PREFIX_0F3A09 */
4654   {
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4658   },
4659
4660   /* PREFIX_0F3A0A */
4661   {
4662     { Bad_Opcode },
4663     { Bad_Opcode },
4664     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4665   },
4666
4667   /* PREFIX_0F3A0B */
4668   {
4669     { Bad_Opcode },
4670     { Bad_Opcode },
4671     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4672   },
4673
4674   /* PREFIX_0F3A0C */
4675   {
4676     { Bad_Opcode },
4677     { Bad_Opcode },
4678     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4679   },
4680
4681   /* PREFIX_0F3A0D */
4682   {
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4686   },
4687
4688   /* PREFIX_0F3A0E */
4689   {
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4693   },
4694
4695   /* PREFIX_0F3A14 */
4696   {
4697     { Bad_Opcode },
4698     { Bad_Opcode },
4699     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4700   },
4701
4702   /* PREFIX_0F3A15 */
4703   {
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4707   },
4708
4709   /* PREFIX_0F3A16 */
4710   {
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4714   },
4715
4716   /* PREFIX_0F3A17 */
4717   {
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4721   },
4722
4723   /* PREFIX_0F3A20 */
4724   {
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4728   },
4729
4730   /* PREFIX_0F3A21 */
4731   {
4732     { Bad_Opcode },
4733     { Bad_Opcode },
4734     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4735   },
4736
4737   /* PREFIX_0F3A22 */
4738   {
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4742   },
4743
4744   /* PREFIX_0F3A40 */
4745   {
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4749   },
4750
4751   /* PREFIX_0F3A41 */
4752   {
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4756   },
4757
4758   /* PREFIX_0F3A42 */
4759   {
4760     { Bad_Opcode },
4761     { Bad_Opcode },
4762     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4763   },
4764
4765   /* PREFIX_0F3A44 */
4766   {
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4770   },
4771
4772   /* PREFIX_0F3A60 */
4773   {
4774     { Bad_Opcode },
4775     { Bad_Opcode },
4776     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4777   },
4778
4779   /* PREFIX_0F3A61 */
4780   {
4781     { Bad_Opcode },
4782     { Bad_Opcode },
4783     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4784   },
4785
4786   /* PREFIX_0F3A62 */
4787   {
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4791   },
4792
4793   /* PREFIX_0F3A63 */
4794   {
4795     { Bad_Opcode },
4796     { Bad_Opcode },
4797     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4798   },
4799
4800   /* PREFIX_0F3ACC */
4801   {
4802     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4803   },
4804
4805   /* PREFIX_0F3ACE */
4806   {
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4810   },
4811
4812   /* PREFIX_0F3ACF */
4813   {
4814     { Bad_Opcode },
4815     { Bad_Opcode },
4816     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4817   },
4818
4819   /* PREFIX_0F3ADF */
4820   {
4821     { Bad_Opcode },
4822     { Bad_Opcode },
4823     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4824   },
4825
4826   /* PREFIX_VEX_0F10 */
4827   {
4828     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4829     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4830     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4831     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4832   },
4833
4834   /* PREFIX_VEX_0F11 */
4835   {
4836     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4837     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4838     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4839     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4840   },
4841
4842   /* PREFIX_VEX_0F12 */
4843   {
4844     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4845     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4846     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4847     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4848   },
4849
4850   /* PREFIX_VEX_0F16 */
4851   {
4852     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4853     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4854     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4855   },
4856
4857   /* PREFIX_VEX_0F2A */
4858   {
4859     { Bad_Opcode },
4860     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4861     { Bad_Opcode },
4862     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4863   },
4864
4865   /* PREFIX_VEX_0F2C */
4866   {
4867     { Bad_Opcode },
4868     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4869     { Bad_Opcode },
4870     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4871   },
4872
4873   /* PREFIX_VEX_0F2D */
4874   {
4875     { Bad_Opcode },
4876     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4877     { Bad_Opcode },
4878     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4879   },
4880
4881   /* PREFIX_VEX_0F2E */
4882   {
4883     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4884     { Bad_Opcode },
4885     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4886   },
4887
4888   /* PREFIX_VEX_0F2F */
4889   {
4890     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4891     { Bad_Opcode },
4892     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4893   },
4894
4895   /* PREFIX_VEX_0F41 */
4896   {
4897     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4898     { Bad_Opcode },
4899     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4900   },
4901
4902   /* PREFIX_VEX_0F42 */
4903   {
4904     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4905     { Bad_Opcode },
4906     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4907   },
4908
4909   /* PREFIX_VEX_0F44 */
4910   {
4911     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4912     { Bad_Opcode },
4913     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4914   },
4915
4916   /* PREFIX_VEX_0F45 */
4917   {
4918     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4919     { Bad_Opcode },
4920     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4921   },
4922
4923   /* PREFIX_VEX_0F46 */
4924   {
4925     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4926     { Bad_Opcode },
4927     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4928   },
4929
4930   /* PREFIX_VEX_0F47 */
4931   {
4932     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4933     { Bad_Opcode },
4934     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4935   },
4936
4937   /* PREFIX_VEX_0F4A */
4938   {
4939     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4940     { Bad_Opcode },
4941     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4942   },
4943
4944   /* PREFIX_VEX_0F4B */
4945   {
4946     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4947     { Bad_Opcode },
4948     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4949   },
4950
4951   /* PREFIX_VEX_0F51 */
4952   {
4953     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4954     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4955     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4956     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4957   },
4958
4959   /* PREFIX_VEX_0F52 */
4960   {
4961     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4962     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4963   },
4964
4965   /* PREFIX_VEX_0F53 */
4966   {
4967     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4968     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4969   },
4970
4971   /* PREFIX_VEX_0F58 */
4972   {
4973     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4974     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4975     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4976     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4977   },
4978
4979   /* PREFIX_VEX_0F59 */
4980   {
4981     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4982     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4983     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4984     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4985   },
4986
4987   /* PREFIX_VEX_0F5A */
4988   {
4989     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4990     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4991     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4992     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4993   },
4994
4995   /* PREFIX_VEX_0F5B */
4996   {
4997     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4998     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4999     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
5000   },
5001
5002   /* PREFIX_VEX_0F5C */
5003   {
5004     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
5005     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
5006     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
5007     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
5008   },
5009
5010   /* PREFIX_VEX_0F5D */
5011   {
5012     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
5013     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
5014     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
5015     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
5016   },
5017
5018   /* PREFIX_VEX_0F5E */
5019   {
5020     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
5021     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
5022     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
5023     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
5024   },
5025
5026   /* PREFIX_VEX_0F5F */
5027   {
5028     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
5029     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
5030     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
5031     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
5032   },
5033
5034   /* PREFIX_VEX_0F60 */
5035   {
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { VEX_W_TABLE (VEX_W_0F60_P_2) },
5039   },
5040
5041   /* PREFIX_VEX_0F61 */
5042   {
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { VEX_W_TABLE (VEX_W_0F61_P_2) },
5046   },
5047
5048   /* PREFIX_VEX_0F62 */
5049   {
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { VEX_W_TABLE (VEX_W_0F62_P_2) },
5053   },
5054
5055   /* PREFIX_VEX_0F63 */
5056   {
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { VEX_W_TABLE (VEX_W_0F63_P_2) },
5060   },
5061
5062   /* PREFIX_VEX_0F64 */
5063   {
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { VEX_W_TABLE (VEX_W_0F64_P_2) },
5067   },
5068
5069   /* PREFIX_VEX_0F65 */
5070   {
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { VEX_W_TABLE (VEX_W_0F65_P_2) },
5074   },
5075
5076   /* PREFIX_VEX_0F66 */
5077   {
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { VEX_W_TABLE (VEX_W_0F66_P_2) },
5081   },
5082
5083   /* PREFIX_VEX_0F67 */
5084   {
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { VEX_W_TABLE (VEX_W_0F67_P_2) },
5088   },
5089
5090   /* PREFIX_VEX_0F68 */
5091   {
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { VEX_W_TABLE (VEX_W_0F68_P_2) },
5095   },
5096
5097   /* PREFIX_VEX_0F69 */
5098   {
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { VEX_W_TABLE (VEX_W_0F69_P_2) },
5102   },
5103
5104   /* PREFIX_VEX_0F6A */
5105   {
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5109   },
5110
5111   /* PREFIX_VEX_0F6B */
5112   {
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5116   },
5117
5118   /* PREFIX_VEX_0F6C */
5119   {
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5123   },
5124
5125   /* PREFIX_VEX_0F6D */
5126   {
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5130   },
5131
5132   /* PREFIX_VEX_0F6E */
5133   {
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5137   },
5138
5139   /* PREFIX_VEX_0F6F */
5140   {
5141     { Bad_Opcode },
5142     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5143     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5144   },
5145
5146   /* PREFIX_VEX_0F70 */
5147   {
5148     { Bad_Opcode },
5149     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5150     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5151     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5152   },
5153
5154   /* PREFIX_VEX_0F71_REG_2 */
5155   {
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5159   },
5160
5161   /* PREFIX_VEX_0F71_REG_4 */
5162   {
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5166   },
5167
5168   /* PREFIX_VEX_0F71_REG_6 */
5169   {
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5173   },
5174
5175   /* PREFIX_VEX_0F72_REG_2 */
5176   {
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5180   },
5181
5182   /* PREFIX_VEX_0F72_REG_4 */
5183   {
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5187   },
5188
5189   /* PREFIX_VEX_0F72_REG_6 */
5190   {
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5194   },
5195
5196   /* PREFIX_VEX_0F73_REG_2 */
5197   {
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5201   },
5202
5203   /* PREFIX_VEX_0F73_REG_3 */
5204   {
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5208   },
5209
5210   /* PREFIX_VEX_0F73_REG_6 */
5211   {
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5215   },
5216
5217   /* PREFIX_VEX_0F73_REG_7 */
5218   {
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5222   },
5223
5224   /* PREFIX_VEX_0F74 */
5225   {
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5229   },
5230
5231   /* PREFIX_VEX_0F75 */
5232   {
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5236   },
5237
5238   /* PREFIX_VEX_0F76 */
5239   {
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5243   },
5244
5245   /* PREFIX_VEX_0F77 */
5246   {
5247     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5248   },
5249
5250   /* PREFIX_VEX_0F7C */
5251   {
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5255     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5256   },
5257
5258   /* PREFIX_VEX_0F7D */
5259   {
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5263     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5264   },
5265
5266   /* PREFIX_VEX_0F7E */
5267   {
5268     { Bad_Opcode },
5269     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5270     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5271   },
5272
5273   /* PREFIX_VEX_0F7F */
5274   {
5275     { Bad_Opcode },
5276     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5277     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5278   },
5279
5280   /* PREFIX_VEX_0F90 */
5281   {
5282     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5283     { Bad_Opcode },
5284     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5285   },
5286
5287   /* PREFIX_VEX_0F91 */
5288   {
5289     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5290     { Bad_Opcode },
5291     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5292   },
5293
5294   /* PREFIX_VEX_0F92 */
5295   {
5296     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5297     { Bad_Opcode },
5298     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5299     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5300   },
5301
5302   /* PREFIX_VEX_0F93 */
5303   {
5304     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5305     { Bad_Opcode },
5306     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5307     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5308   },
5309
5310   /* PREFIX_VEX_0F98 */
5311   {
5312     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5313     { Bad_Opcode },
5314     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5315   },
5316
5317   /* PREFIX_VEX_0F99 */
5318   {
5319     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5320     { Bad_Opcode },
5321     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5322   },
5323
5324   /* PREFIX_VEX_0FC2 */
5325   {
5326     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5327     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5328     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5329     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5330   },
5331
5332   /* PREFIX_VEX_0FC4 */
5333   {
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5337   },
5338
5339   /* PREFIX_VEX_0FC5 */
5340   {
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5344   },
5345
5346   /* PREFIX_VEX_0FD0 */
5347   {
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5351     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5352   },
5353
5354   /* PREFIX_VEX_0FD1 */
5355   {
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5359   },
5360
5361   /* PREFIX_VEX_0FD2 */
5362   {
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5366   },
5367
5368   /* PREFIX_VEX_0FD3 */
5369   {
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5373   },
5374
5375   /* PREFIX_VEX_0FD4 */
5376   {
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5380   },
5381
5382   /* PREFIX_VEX_0FD5 */
5383   {
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5387   },
5388
5389   /* PREFIX_VEX_0FD6 */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5394   },
5395
5396   /* PREFIX_VEX_0FD7 */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5401   },
5402
5403   /* PREFIX_VEX_0FD8 */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5408   },
5409
5410   /* PREFIX_VEX_0FD9 */
5411   {
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5415   },
5416
5417   /* PREFIX_VEX_0FDA */
5418   {
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5422   },
5423
5424   /* PREFIX_VEX_0FDB */
5425   {
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5429   },
5430
5431   /* PREFIX_VEX_0FDC */
5432   {
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5436   },
5437
5438   /* PREFIX_VEX_0FDD */
5439   {
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5443   },
5444
5445   /* PREFIX_VEX_0FDE */
5446   {
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5450   },
5451
5452   /* PREFIX_VEX_0FDF */
5453   {
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5457   },
5458
5459   /* PREFIX_VEX_0FE0 */
5460   {
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5464   },
5465
5466   /* PREFIX_VEX_0FE1 */
5467   {
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5471   },
5472
5473   /* PREFIX_VEX_0FE2 */
5474   {
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5478   },
5479
5480   /* PREFIX_VEX_0FE3 */
5481   {
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5485   },
5486
5487   /* PREFIX_VEX_0FE4 */
5488   {
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5492   },
5493
5494   /* PREFIX_VEX_0FE5 */
5495   {
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5499   },
5500
5501   /* PREFIX_VEX_0FE6 */
5502   {
5503     { Bad_Opcode },
5504     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5505     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5506     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5507   },
5508
5509   /* PREFIX_VEX_0FE7 */
5510   {
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5514   },
5515
5516   /* PREFIX_VEX_0FE8 */
5517   {
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5521   },
5522
5523   /* PREFIX_VEX_0FE9 */
5524   {
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5528   },
5529
5530   /* PREFIX_VEX_0FEA */
5531   {
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5535   },
5536
5537   /* PREFIX_VEX_0FEB */
5538   {
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5542   },
5543
5544   /* PREFIX_VEX_0FEC */
5545   {
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5549   },
5550
5551   /* PREFIX_VEX_0FED */
5552   {
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5556   },
5557
5558   /* PREFIX_VEX_0FEE */
5559   {
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5563   },
5564
5565   /* PREFIX_VEX_0FEF */
5566   {
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5570   },
5571
5572   /* PREFIX_VEX_0FF0 */
5573   {
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5578   },
5579
5580   /* PREFIX_VEX_0FF1 */
5581   {
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5585   },
5586
5587   /* PREFIX_VEX_0FF2 */
5588   {
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5592   },
5593
5594   /* PREFIX_VEX_0FF3 */
5595   {
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5599   },
5600
5601   /* PREFIX_VEX_0FF4 */
5602   {
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5606   },
5607
5608   /* PREFIX_VEX_0FF5 */
5609   {
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5613   },
5614
5615   /* PREFIX_VEX_0FF6 */
5616   {
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5620   },
5621
5622   /* PREFIX_VEX_0FF7 */
5623   {
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5627   },
5628
5629   /* PREFIX_VEX_0FF8 */
5630   {
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5634   },
5635
5636   /* PREFIX_VEX_0FF9 */
5637   {
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5641   },
5642
5643   /* PREFIX_VEX_0FFA */
5644   {
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5648   },
5649
5650   /* PREFIX_VEX_0FFB */
5651   {
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5655   },
5656
5657   /* PREFIX_VEX_0FFC */
5658   {
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5662   },
5663
5664   /* PREFIX_VEX_0FFD */
5665   {
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5669   },
5670
5671   /* PREFIX_VEX_0FFE */
5672   {
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5676   },
5677
5678   /* PREFIX_VEX_0F3800 */
5679   {
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5683   },
5684
5685   /* PREFIX_VEX_0F3801 */
5686   {
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5690   },
5691
5692   /* PREFIX_VEX_0F3802 */
5693   {
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5697   },
5698
5699   /* PREFIX_VEX_0F3803 */
5700   {
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5704   },
5705
5706   /* PREFIX_VEX_0F3804 */
5707   {
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5711   },
5712
5713   /* PREFIX_VEX_0F3805 */
5714   {
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5718   },
5719
5720   /* PREFIX_VEX_0F3806 */
5721   {
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5725   },
5726
5727   /* PREFIX_VEX_0F3807 */
5728   {
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5732   },
5733
5734   /* PREFIX_VEX_0F3808 */
5735   {
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5739   },
5740
5741   /* PREFIX_VEX_0F3809 */
5742   {
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5746   },
5747
5748   /* PREFIX_VEX_0F380A */
5749   {
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5753   },
5754
5755   /* PREFIX_VEX_0F380B */
5756   {
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5760   },
5761
5762   /* PREFIX_VEX_0F380C */
5763   {
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5767   },
5768
5769   /* PREFIX_VEX_0F380D */
5770   {
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5774   },
5775
5776   /* PREFIX_VEX_0F380E */
5777   {
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5781   },
5782
5783   /* PREFIX_VEX_0F380F */
5784   {
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5788   },
5789
5790   /* PREFIX_VEX_0F3813 */
5791   {
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5795   },
5796
5797   /* PREFIX_VEX_0F3816 */
5798   {
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5802   },
5803
5804   /* PREFIX_VEX_0F3817 */
5805   {
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5809   },
5810
5811   /* PREFIX_VEX_0F3818 */
5812   {
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5816   },
5817
5818   /* PREFIX_VEX_0F3819 */
5819   {
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5823   },
5824
5825   /* PREFIX_VEX_0F381A */
5826   {
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5830   },
5831
5832   /* PREFIX_VEX_0F381C */
5833   {
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5837   },
5838
5839   /* PREFIX_VEX_0F381D */
5840   {
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5844   },
5845
5846   /* PREFIX_VEX_0F381E */
5847   {
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5851   },
5852
5853   /* PREFIX_VEX_0F3820 */
5854   {
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5858   },
5859
5860   /* PREFIX_VEX_0F3821 */
5861   {
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5865   },
5866
5867   /* PREFIX_VEX_0F3822 */
5868   {
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5872   },
5873
5874   /* PREFIX_VEX_0F3823 */
5875   {
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5879   },
5880
5881   /* PREFIX_VEX_0F3824 */
5882   {
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5886   },
5887
5888   /* PREFIX_VEX_0F3825 */
5889   {
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5893   },
5894
5895   /* PREFIX_VEX_0F3828 */
5896   {
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5900   },
5901
5902   /* PREFIX_VEX_0F3829 */
5903   {
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5907   },
5908
5909   /* PREFIX_VEX_0F382A */
5910   {
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5914   },
5915
5916   /* PREFIX_VEX_0F382B */
5917   {
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5921   },
5922
5923   /* PREFIX_VEX_0F382C */
5924   {
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5928   },
5929
5930   /* PREFIX_VEX_0F382D */
5931   {
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5935   },
5936
5937   /* PREFIX_VEX_0F382E */
5938   {
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5942   },
5943
5944   /* PREFIX_VEX_0F382F */
5945   {
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5949   },
5950
5951   /* PREFIX_VEX_0F3830 */
5952   {
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5956   },
5957
5958   /* PREFIX_VEX_0F3831 */
5959   {
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5963   },
5964
5965   /* PREFIX_VEX_0F3832 */
5966   {
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5970   },
5971
5972   /* PREFIX_VEX_0F3833 */
5973   {
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5977   },
5978
5979   /* PREFIX_VEX_0F3834 */
5980   {
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5984   },
5985
5986   /* PREFIX_VEX_0F3835 */
5987   {
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5991   },
5992
5993   /* PREFIX_VEX_0F3836 */
5994   {
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5998   },
5999
6000   /* PREFIX_VEX_0F3837 */
6001   {
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
6005   },
6006
6007   /* PREFIX_VEX_0F3838 */
6008   {
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
6012   },
6013
6014   /* PREFIX_VEX_0F3839 */
6015   {
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
6019   },
6020
6021   /* PREFIX_VEX_0F383A */
6022   {
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
6026   },
6027
6028   /* PREFIX_VEX_0F383B */
6029   {
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
6033   },
6034
6035   /* PREFIX_VEX_0F383C */
6036   {
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
6040   },
6041
6042   /* PREFIX_VEX_0F383D */
6043   {
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
6047   },
6048
6049   /* PREFIX_VEX_0F383E */
6050   {
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
6054   },
6055
6056   /* PREFIX_VEX_0F383F */
6057   {
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
6061   },
6062
6063   /* PREFIX_VEX_0F3840 */
6064   {
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6068   },
6069
6070   /* PREFIX_VEX_0F3841 */
6071   {
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6075   },
6076
6077   /* PREFIX_VEX_0F3845 */
6078   {
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6082   },
6083
6084   /* PREFIX_VEX_0F3846 */
6085   {
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6089   },
6090
6091   /* PREFIX_VEX_0F3847 */
6092   {
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6096   },
6097
6098   /* PREFIX_VEX_0F3858 */
6099   {
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6103   },
6104
6105   /* PREFIX_VEX_0F3859 */
6106   {
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6110   },
6111
6112   /* PREFIX_VEX_0F385A */
6113   {
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6117   },
6118
6119   /* PREFIX_VEX_0F3878 */
6120   {
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6124   },
6125
6126   /* PREFIX_VEX_0F3879 */
6127   {
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6131   },
6132
6133   /* PREFIX_VEX_0F388C */
6134   {
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6138   },
6139
6140   /* PREFIX_VEX_0F388E */
6141   {
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6145   },
6146
6147   /* PREFIX_VEX_0F3890 */
6148   {
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6152   },
6153
6154   /* PREFIX_VEX_0F3891 */
6155   {
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6159   },
6160
6161   /* PREFIX_VEX_0F3892 */
6162   {
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6166   },
6167
6168   /* PREFIX_VEX_0F3893 */
6169   {
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6173   },
6174
6175   /* PREFIX_VEX_0F3896 */
6176   {
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6180   },
6181
6182   /* PREFIX_VEX_0F3897 */
6183   {
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6187   },
6188
6189   /* PREFIX_VEX_0F3898 */
6190   {
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6194   },
6195
6196   /* PREFIX_VEX_0F3899 */
6197   {
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6201   },
6202
6203   /* PREFIX_VEX_0F389A */
6204   {
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6208   },
6209
6210   /* PREFIX_VEX_0F389B */
6211   {
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6215   },
6216
6217   /* PREFIX_VEX_0F389C */
6218   {
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6222   },
6223
6224   /* PREFIX_VEX_0F389D */
6225   {
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6229   },
6230
6231   /* PREFIX_VEX_0F389E */
6232   {
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6236   },
6237
6238   /* PREFIX_VEX_0F389F */
6239   {
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6243   },
6244
6245   /* PREFIX_VEX_0F38A6 */
6246   {
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6250     { Bad_Opcode },
6251   },
6252
6253   /* PREFIX_VEX_0F38A7 */
6254   {
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6258   },
6259
6260   /* PREFIX_VEX_0F38A8 */
6261   {
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6265   },
6266
6267   /* PREFIX_VEX_0F38A9 */
6268   {
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6272   },
6273
6274   /* PREFIX_VEX_0F38AA */
6275   {
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6279   },
6280
6281   /* PREFIX_VEX_0F38AB */
6282   {
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6286   },
6287
6288   /* PREFIX_VEX_0F38AC */
6289   {
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6293   },
6294
6295   /* PREFIX_VEX_0F38AD */
6296   {
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6300   },
6301
6302   /* PREFIX_VEX_0F38AE */
6303   {
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6307   },
6308
6309   /* PREFIX_VEX_0F38AF */
6310   {
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6314   },
6315
6316   /* PREFIX_VEX_0F38B6 */
6317   {
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6321   },
6322
6323   /* PREFIX_VEX_0F38B7 */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6328   },
6329
6330   /* PREFIX_VEX_0F38B8 */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6335   },
6336
6337   /* PREFIX_VEX_0F38B9 */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6342   },
6343
6344   /* PREFIX_VEX_0F38BA */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6349   },
6350
6351   /* PREFIX_VEX_0F38BB */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6356   },
6357
6358   /* PREFIX_VEX_0F38BC */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6363   },
6364
6365   /* PREFIX_VEX_0F38BD */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6370   },
6371
6372   /* PREFIX_VEX_0F38BE */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6377   },
6378
6379   /* PREFIX_VEX_0F38BF */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6384   },
6385
6386   /* PREFIX_VEX_0F38CF */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6391   },
6392
6393   /* PREFIX_VEX_0F38DB */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6398   },
6399
6400   /* PREFIX_VEX_0F38DC */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { "vaesenc",        { XM, Vex, EXx }, 0 },
6405   },
6406
6407   /* PREFIX_VEX_0F38DD */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6412   },
6413
6414   /* PREFIX_VEX_0F38DE */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { "vaesdec",        { XM, Vex, EXx }, 0 },
6419   },
6420
6421   /* PREFIX_VEX_0F38DF */
6422   {
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6426   },
6427
6428   /* PREFIX_VEX_0F38F2 */
6429   {
6430     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6431   },
6432
6433   /* PREFIX_VEX_0F38F3_REG_1 */
6434   {
6435     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6436   },
6437
6438   /* PREFIX_VEX_0F38F3_REG_2 */
6439   {
6440     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6441   },
6442
6443   /* PREFIX_VEX_0F38F3_REG_3 */
6444   {
6445     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6446   },
6447
6448   /* PREFIX_VEX_0F38F5 */
6449   {
6450     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6451     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6452     { Bad_Opcode },
6453     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6454   },
6455
6456   /* PREFIX_VEX_0F38F6 */
6457   {
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6462   },
6463
6464   /* PREFIX_VEX_0F38F7 */
6465   {
6466     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6467     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6468     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6469     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6470   },
6471
6472   /* PREFIX_VEX_0F3A00 */
6473   {
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6477   },
6478
6479   /* PREFIX_VEX_0F3A01 */
6480   {
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6484   },
6485
6486   /* PREFIX_VEX_0F3A02 */
6487   {
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6491   },
6492
6493   /* PREFIX_VEX_0F3A04 */
6494   {
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6498   },
6499
6500   /* PREFIX_VEX_0F3A05 */
6501   {
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6505   },
6506
6507   /* PREFIX_VEX_0F3A06 */
6508   {
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6512   },
6513
6514   /* PREFIX_VEX_0F3A08 */
6515   {
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6519   },
6520
6521   /* PREFIX_VEX_0F3A09 */
6522   {
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6526   },
6527
6528   /* PREFIX_VEX_0F3A0A */
6529   {
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6533   },
6534
6535   /* PREFIX_VEX_0F3A0B */
6536   {
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6540   },
6541
6542   /* PREFIX_VEX_0F3A0C */
6543   {
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6547   },
6548
6549   /* PREFIX_VEX_0F3A0D */
6550   {
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6554   },
6555
6556   /* PREFIX_VEX_0F3A0E */
6557   {
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6561   },
6562
6563   /* PREFIX_VEX_0F3A0F */
6564   {
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6568   },
6569
6570   /* PREFIX_VEX_0F3A14 */
6571   {
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6575   },
6576
6577   /* PREFIX_VEX_0F3A15 */
6578   {
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6582   },
6583
6584   /* PREFIX_VEX_0F3A16 */
6585   {
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6589   },
6590
6591   /* PREFIX_VEX_0F3A17 */
6592   {
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6596   },
6597
6598   /* PREFIX_VEX_0F3A18 */
6599   {
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6603   },
6604
6605   /* PREFIX_VEX_0F3A19 */
6606   {
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6610   },
6611
6612   /* PREFIX_VEX_0F3A1D */
6613   {
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6617   },
6618
6619   /* PREFIX_VEX_0F3A20 */
6620   {
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6624   },
6625
6626   /* PREFIX_VEX_0F3A21 */
6627   {
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6631   },
6632
6633   /* PREFIX_VEX_0F3A22 */
6634   {
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6638   },
6639
6640   /* PREFIX_VEX_0F3A30 */
6641   {
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6645   },
6646
6647   /* PREFIX_VEX_0F3A31 */
6648   {
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6652   },
6653
6654   /* PREFIX_VEX_0F3A32 */
6655   {
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6659   },
6660
6661   /* PREFIX_VEX_0F3A33 */
6662   {
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6666   },
6667
6668   /* PREFIX_VEX_0F3A38 */
6669   {
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6673   },
6674
6675   /* PREFIX_VEX_0F3A39 */
6676   {
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6680   },
6681
6682   /* PREFIX_VEX_0F3A40 */
6683   {
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6687   },
6688
6689   /* PREFIX_VEX_0F3A41 */
6690   {
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6694   },
6695
6696   /* PREFIX_VEX_0F3A42 */
6697   {
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6701   },
6702
6703   /* PREFIX_VEX_0F3A44 */
6704   {
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6708   },
6709
6710   /* PREFIX_VEX_0F3A46 */
6711   {
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6715   },
6716
6717   /* PREFIX_VEX_0F3A48 */
6718   {
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6722   },
6723
6724   /* PREFIX_VEX_0F3A49 */
6725   {
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6729   },
6730
6731   /* PREFIX_VEX_0F3A4A */
6732   {
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6736   },
6737
6738   /* PREFIX_VEX_0F3A4B */
6739   {
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6743   },
6744
6745   /* PREFIX_VEX_0F3A4C */
6746   {
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6750   },
6751
6752   /* PREFIX_VEX_0F3A5C */
6753   {
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6757   },
6758
6759   /* PREFIX_VEX_0F3A5D */
6760   {
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6764   },
6765
6766   /* PREFIX_VEX_0F3A5E */
6767   {
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6771   },
6772
6773   /* PREFIX_VEX_0F3A5F */
6774   {
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6778   },
6779
6780   /* PREFIX_VEX_0F3A60 */
6781   {
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6785     { Bad_Opcode },
6786   },
6787
6788   /* PREFIX_VEX_0F3A61 */
6789   {
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6793   },
6794
6795   /* PREFIX_VEX_0F3A62 */
6796   {
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6800   },
6801
6802   /* PREFIX_VEX_0F3A63 */
6803   {
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6807   },
6808
6809   /* PREFIX_VEX_0F3A68 */
6810   {
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6814   },
6815
6816   /* PREFIX_VEX_0F3A69 */
6817   {
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6821   },
6822
6823   /* PREFIX_VEX_0F3A6A */
6824   {
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6828   },
6829
6830   /* PREFIX_VEX_0F3A6B */
6831   {
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6835   },
6836
6837   /* PREFIX_VEX_0F3A6C */
6838   {
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6842   },
6843
6844   /* PREFIX_VEX_0F3A6D */
6845   {
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6849   },
6850
6851   /* PREFIX_VEX_0F3A6E */
6852   {
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6856   },
6857
6858   /* PREFIX_VEX_0F3A6F */
6859   {
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6863   },
6864
6865   /* PREFIX_VEX_0F3A78 */
6866   {
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6870   },
6871
6872   /* PREFIX_VEX_0F3A79 */
6873   {
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6877   },
6878
6879   /* PREFIX_VEX_0F3A7A */
6880   {
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6884   },
6885
6886   /* PREFIX_VEX_0F3A7B */
6887   {
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6891   },
6892
6893   /* PREFIX_VEX_0F3A7C */
6894   {
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6898     { Bad_Opcode },
6899   },
6900
6901   /* PREFIX_VEX_0F3A7D */
6902   {
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6906   },
6907
6908   /* PREFIX_VEX_0F3A7E */
6909   {
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6913   },
6914
6915   /* PREFIX_VEX_0F3A7F */
6916   {
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6920   },
6921
6922   /* PREFIX_VEX_0F3ACE */
6923   {
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6927   },
6928
6929   /* PREFIX_VEX_0F3ACF */
6930   {
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6934   },
6935
6936   /* PREFIX_VEX_0F3ADF */
6937   {
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6941   },
6942
6943   /* PREFIX_VEX_0F3AF0 */
6944   {
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6949   },
6950
6951 #define NEED_PREFIX_TABLE
6952 #include "i386-dis-evex.h"
6953 #undef NEED_PREFIX_TABLE
6954 };
6955
6956 static const struct dis386 x86_64_table[][2] = {
6957   /* X86_64_06 */
6958   {
6959     { "pushP", { es }, 0 },
6960   },
6961
6962   /* X86_64_07 */
6963   {
6964     { "popP", { es }, 0 },
6965   },
6966
6967   /* X86_64_0D */
6968   {
6969     { "pushP", { cs }, 0 },
6970   },
6971
6972   /* X86_64_16 */
6973   {
6974     { "pushP", { ss }, 0 },
6975   },
6976
6977   /* X86_64_17 */
6978   {
6979     { "popP", { ss }, 0 },
6980   },
6981
6982   /* X86_64_1E */
6983   {
6984     { "pushP", { ds }, 0 },
6985   },
6986
6987   /* X86_64_1F */
6988   {
6989     { "popP", { ds }, 0 },
6990   },
6991
6992   /* X86_64_27 */
6993   {
6994     { "daa", { XX }, 0 },
6995   },
6996
6997   /* X86_64_2F */
6998   {
6999     { "das", { XX }, 0 },
7000   },
7001
7002   /* X86_64_37 */
7003   {
7004     { "aaa", { XX }, 0 },
7005   },
7006
7007   /* X86_64_3F */
7008   {
7009     { "aas", { XX }, 0 },
7010   },
7011
7012   /* X86_64_60 */
7013   {
7014     { "pushaP", { XX }, 0 },
7015   },
7016
7017   /* X86_64_61 */
7018   {
7019     { "popaP", { XX }, 0 },
7020   },
7021
7022   /* X86_64_62 */
7023   {
7024     { MOD_TABLE (MOD_62_32BIT) },
7025     { EVEX_TABLE (EVEX_0F) },
7026   },
7027
7028   /* X86_64_63 */
7029   {
7030     { "arpl", { Ew, Gw }, 0 },
7031     { "movs{lq|xd}", { Gv, Ed }, 0 },
7032   },
7033
7034   /* X86_64_6D */
7035   {
7036     { "ins{R|}", { Yzr, indirDX }, 0 },
7037     { "ins{G|}", { Yzr, indirDX }, 0 },
7038   },
7039
7040   /* X86_64_6F */
7041   {
7042     { "outs{R|}", { indirDXr, Xz }, 0 },
7043     { "outs{G|}", { indirDXr, Xz }, 0 },
7044   },
7045
7046   /* X86_64_82 */
7047   {
7048     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
7049     { REG_TABLE (REG_80) },
7050   },
7051
7052   /* X86_64_9A */
7053   {
7054     { "Jcall{T|}", { Ap }, 0 },
7055   },
7056
7057   /* X86_64_C4 */
7058   {
7059     { MOD_TABLE (MOD_C4_32BIT) },
7060     { VEX_C4_TABLE (VEX_0F) },
7061   },
7062
7063   /* X86_64_C5 */
7064   {
7065     { MOD_TABLE (MOD_C5_32BIT) },
7066     { VEX_C5_TABLE (VEX_0F) },
7067   },
7068
7069   /* X86_64_CE */
7070   {
7071     { "into", { XX }, 0 },
7072   },
7073
7074   /* X86_64_D4 */
7075   {
7076     { "aam", { Ib }, 0 },
7077   },
7078
7079   /* X86_64_D5 */
7080   {
7081     { "aad", { Ib }, 0 },
7082   },
7083
7084   /* X86_64_E8 */
7085   {
7086     { "callP",          { Jv, BND }, 0 },
7087     { "call@",          { Jv, BND }, 0 }
7088   },
7089
7090   /* X86_64_E9 */
7091   {
7092     { "jmpP",           { Jv, BND }, 0 },
7093     { "jmp@",           { Jv, BND }, 0 }
7094   },
7095
7096   /* X86_64_EA */
7097   {
7098     { "Jjmp{T|}", { Ap }, 0 },
7099   },
7100
7101   /* X86_64_0F01_REG_0 */
7102   {
7103     { "sgdt{Q|IQ}", { M }, 0 },
7104     { "sgdt", { M }, 0 },
7105   },
7106
7107   /* X86_64_0F01_REG_1 */
7108   {
7109     { "sidt{Q|IQ}", { M }, 0 },
7110     { "sidt", { M }, 0 },
7111   },
7112
7113   /* X86_64_0F01_REG_2 */
7114   {
7115     { "lgdt{Q|Q}", { M }, 0 },
7116     { "lgdt", { M }, 0 },
7117   },
7118
7119   /* X86_64_0F01_REG_3 */
7120   {
7121     { "lidt{Q|Q}", { M }, 0 },
7122     { "lidt", { M }, 0 },
7123   },
7124 };
7125
7126 static const struct dis386 three_byte_table[][256] = {
7127
7128   /* THREE_BYTE_0F38 */
7129   {
7130     /* 00 */
7131     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7132     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7133     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7134     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7135     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7136     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7137     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7138     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7139     /* 08 */
7140     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7141     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7142     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7143     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     /* 10 */
7149     { PREFIX_TABLE (PREFIX_0F3810) },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { PREFIX_TABLE (PREFIX_0F3814) },
7154     { PREFIX_TABLE (PREFIX_0F3815) },
7155     { Bad_Opcode },
7156     { PREFIX_TABLE (PREFIX_0F3817) },
7157     /* 18 */
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7163     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7164     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7165     { Bad_Opcode },
7166     /* 20 */
7167     { PREFIX_TABLE (PREFIX_0F3820) },
7168     { PREFIX_TABLE (PREFIX_0F3821) },
7169     { PREFIX_TABLE (PREFIX_0F3822) },
7170     { PREFIX_TABLE (PREFIX_0F3823) },
7171     { PREFIX_TABLE (PREFIX_0F3824) },
7172     { PREFIX_TABLE (PREFIX_0F3825) },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     /* 28 */
7176     { PREFIX_TABLE (PREFIX_0F3828) },
7177     { PREFIX_TABLE (PREFIX_0F3829) },
7178     { PREFIX_TABLE (PREFIX_0F382A) },
7179     { PREFIX_TABLE (PREFIX_0F382B) },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     /* 30 */
7185     { PREFIX_TABLE (PREFIX_0F3830) },
7186     { PREFIX_TABLE (PREFIX_0F3831) },
7187     { PREFIX_TABLE (PREFIX_0F3832) },
7188     { PREFIX_TABLE (PREFIX_0F3833) },
7189     { PREFIX_TABLE (PREFIX_0F3834) },
7190     { PREFIX_TABLE (PREFIX_0F3835) },
7191     { Bad_Opcode },
7192     { PREFIX_TABLE (PREFIX_0F3837) },
7193     /* 38 */
7194     { PREFIX_TABLE (PREFIX_0F3838) },
7195     { PREFIX_TABLE (PREFIX_0F3839) },
7196     { PREFIX_TABLE (PREFIX_0F383A) },
7197     { PREFIX_TABLE (PREFIX_0F383B) },
7198     { PREFIX_TABLE (PREFIX_0F383C) },
7199     { PREFIX_TABLE (PREFIX_0F383D) },
7200     { PREFIX_TABLE (PREFIX_0F383E) },
7201     { PREFIX_TABLE (PREFIX_0F383F) },
7202     /* 40 */
7203     { PREFIX_TABLE (PREFIX_0F3840) },
7204     { PREFIX_TABLE (PREFIX_0F3841) },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     /* 48 */
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     /* 50 */
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     /* 58 */
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     /* 60 */
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     /* 68 */
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     /* 70 */
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     /* 78 */
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     /* 80 */
7275     { PREFIX_TABLE (PREFIX_0F3880) },
7276     { PREFIX_TABLE (PREFIX_0F3881) },
7277     { PREFIX_TABLE (PREFIX_0F3882) },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     /* 88 */
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     /* 90 */
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     /* 98 */
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     /* a0 */
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     /* a8 */
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     /* b0 */
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     /* b8 */
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     /* c0 */
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     /* c8 */
7356     { PREFIX_TABLE (PREFIX_0F38C8) },
7357     { PREFIX_TABLE (PREFIX_0F38C9) },
7358     { PREFIX_TABLE (PREFIX_0F38CA) },
7359     { PREFIX_TABLE (PREFIX_0F38CB) },
7360     { PREFIX_TABLE (PREFIX_0F38CC) },
7361     { PREFIX_TABLE (PREFIX_0F38CD) },
7362     { Bad_Opcode },
7363     { PREFIX_TABLE (PREFIX_0F38CF) },
7364     /* d0 */
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     /* d8 */
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { PREFIX_TABLE (PREFIX_0F38DB) },
7378     { PREFIX_TABLE (PREFIX_0F38DC) },
7379     { PREFIX_TABLE (PREFIX_0F38DD) },
7380     { PREFIX_TABLE (PREFIX_0F38DE) },
7381     { PREFIX_TABLE (PREFIX_0F38DF) },
7382     /* e0 */
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     /* e8 */
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     /* f0 */
7401     { PREFIX_TABLE (PREFIX_0F38F0) },
7402     { PREFIX_TABLE (PREFIX_0F38F1) },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { PREFIX_TABLE (PREFIX_0F38F5) },
7407     { PREFIX_TABLE (PREFIX_0F38F6) },
7408     { Bad_Opcode },
7409     /* f8 */
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418   },
7419   /* THREE_BYTE_0F3A */
7420   {
7421     /* 00 */
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     /* 08 */
7431     { PREFIX_TABLE (PREFIX_0F3A08) },
7432     { PREFIX_TABLE (PREFIX_0F3A09) },
7433     { PREFIX_TABLE (PREFIX_0F3A0A) },
7434     { PREFIX_TABLE (PREFIX_0F3A0B) },
7435     { PREFIX_TABLE (PREFIX_0F3A0C) },
7436     { PREFIX_TABLE (PREFIX_0F3A0D) },
7437     { PREFIX_TABLE (PREFIX_0F3A0E) },
7438     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7439     /* 10 */
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { PREFIX_TABLE (PREFIX_0F3A14) },
7445     { PREFIX_TABLE (PREFIX_0F3A15) },
7446     { PREFIX_TABLE (PREFIX_0F3A16) },
7447     { PREFIX_TABLE (PREFIX_0F3A17) },
7448     /* 18 */
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     /* 20 */
7458     { PREFIX_TABLE (PREFIX_0F3A20) },
7459     { PREFIX_TABLE (PREFIX_0F3A21) },
7460     { PREFIX_TABLE (PREFIX_0F3A22) },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     /* 28 */
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     /* 30 */
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     /* 38 */
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     /* 40 */
7494     { PREFIX_TABLE (PREFIX_0F3A40) },
7495     { PREFIX_TABLE (PREFIX_0F3A41) },
7496     { PREFIX_TABLE (PREFIX_0F3A42) },
7497     { Bad_Opcode },
7498     { PREFIX_TABLE (PREFIX_0F3A44) },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     /* 48 */
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     /* 50 */
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     /* 58 */
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     /* 60 */
7530     { PREFIX_TABLE (PREFIX_0F3A60) },
7531     { PREFIX_TABLE (PREFIX_0F3A61) },
7532     { PREFIX_TABLE (PREFIX_0F3A62) },
7533     { PREFIX_TABLE (PREFIX_0F3A63) },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     /* 68 */
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     /* 70 */
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     /* 78 */
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     /* 80 */
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     /* 88 */
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     /* 90 */
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     /* 98 */
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     /* a0 */
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     /* a8 */
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     /* b0 */
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     /* b8 */
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     /* c0 */
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     /* c8 */
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { PREFIX_TABLE (PREFIX_0F3ACC) },
7652     { Bad_Opcode },
7653     { PREFIX_TABLE (PREFIX_0F3ACE) },
7654     { PREFIX_TABLE (PREFIX_0F3ACF) },
7655     /* d0 */
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     /* d8 */
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { PREFIX_TABLE (PREFIX_0F3ADF) },
7673     /* e0 */
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     /* e8 */
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     /* f0 */
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     /* f8 */
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709   },
7710 };
7711
7712 static const struct dis386 xop_table[][256] = {
7713   /* XOP_08 */
7714   {
7715     /* 00 */
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     /* 08 */
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     /* 10 */
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     /* 18 */
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     /* 20 */
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     /* 28 */
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     /* 30 */
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     /* 38 */
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     /* 40 */
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     /* 48 */
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     /* 50 */
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     /* 58 */
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     /* 60 */
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     /* 68 */
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     /* 70 */
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     /* 78 */
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     /* 80 */
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7866     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7867     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7868     /* 88 */
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7876     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7877     /* 90 */
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7884     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7885     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7886     /* 98 */
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7894     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7895     /* a0 */
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7899     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7903     { Bad_Opcode },
7904     /* a8 */
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     /* b0 */
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7921     { Bad_Opcode },
7922     /* b8 */
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     /* c0 */
7932     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7933     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7934     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7935     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     /* c8 */
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7946     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7947     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7948     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7949     /* d0 */
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     /* d8 */
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     /* e0 */
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     /* e8 */
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7982     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7983     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7984     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7985     /* f0 */
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     /* f8 */
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003   },
8004   /* XOP_09 */
8005   {
8006     /* 00 */
8007     { Bad_Opcode },
8008     { REG_TABLE (REG_XOP_TBM_01) },
8009     { REG_TABLE (REG_XOP_TBM_02) },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     /* 08 */
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     /* 10 */
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { REG_TABLE (REG_XOP_LWPCB) },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     /* 18 */
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     /* 20 */
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     /* 28 */
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     /* 30 */
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     /* 38 */
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     /* 40 */
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     /* 48 */
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     /* 50 */
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     /* 58 */
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     /* 60 */
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     /* 68 */
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     /* 70 */
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     /* 78 */
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     /* 80 */
8151     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8152     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8153     { "vfrczss",        { XM, EXd }, 0 },
8154     { "vfrczsd",        { XM, EXq }, 0 },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     /* 88 */
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     /* 90 */
8169     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8170     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8171     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8172     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8173     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8174     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8175     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8176     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8177     /* 98 */
8178     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8179     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8180     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8181     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     /* a0 */
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     /* a8 */
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     /* b0 */
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     /* b8 */
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     /* c0 */
8223     { Bad_Opcode },
8224     { "vphaddbw",       { XM, EXxmm }, 0 },
8225     { "vphaddbd",       { XM, EXxmm }, 0 },
8226     { "vphaddbq",       { XM, EXxmm }, 0 },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { "vphaddwd",       { XM, EXxmm }, 0 },
8230     { "vphaddwq",       { XM, EXxmm }, 0 },
8231     /* c8 */
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { "vphadddq",       { XM, EXxmm }, 0 },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     /* d0 */
8241     { Bad_Opcode },
8242     { "vphaddubw",      { XM, EXxmm }, 0 },
8243     { "vphaddubd",      { XM, EXxmm }, 0 },
8244     { "vphaddubq",      { XM, EXxmm }, 0 },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { "vphadduwd",      { XM, EXxmm }, 0 },
8248     { "vphadduwq",      { XM, EXxmm }, 0 },
8249     /* d8 */
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { "vphaddudq",      { XM, EXxmm }, 0 },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     /* e0 */
8259     { Bad_Opcode },
8260     { "vphsubbw",       { XM, EXxmm }, 0 },
8261     { "vphsubwd",       { XM, EXxmm }, 0 },
8262     { "vphsubdq",       { XM, EXxmm }, 0 },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     /* e8 */
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     /* f0 */
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     /* f8 */
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294   },
8295   /* XOP_0A */
8296   {
8297     /* 00 */
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     /* 08 */
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     /* 10 */
8316     { "bextr",  { Gv, Ev, Iq }, 0 },
8317     { Bad_Opcode },
8318     { REG_TABLE (REG_XOP_LWP) },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     /* 18 */
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     /* 20 */
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     /* 28 */
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     /* 30 */
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     /* 38 */
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     /* 40 */
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     /* 48 */
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     /* 50 */
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     /* 58 */
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     /* 60 */
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     /* 68 */
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     /* 70 */
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     /* 78 */
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     /* 80 */
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     /* 88 */
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     /* 90 */
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     /* 98 */
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     /* a0 */
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     /* a8 */
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     /* b0 */
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     /* b8 */
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     /* c0 */
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     /* c8 */
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     /* d0 */
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     /* d8 */
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     /* e0 */
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     /* e8 */
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     /* f0 */
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     /* f8 */
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585   },
8586 };
8587
8588 static const struct dis386 vex_table[][256] = {
8589   /* VEX_0F */
8590   {
8591     /* 00 */
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     /* 08 */
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     /* 10 */
8610     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8611     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8612     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8613     { MOD_TABLE (MOD_VEX_0F13) },
8614     { VEX_W_TABLE (VEX_W_0F14) },
8615     { VEX_W_TABLE (VEX_W_0F15) },
8616     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8617     { MOD_TABLE (MOD_VEX_0F17) },
8618     /* 18 */
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     /* 20 */
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     /* 28 */
8637     { VEX_W_TABLE (VEX_W_0F28) },
8638     { VEX_W_TABLE (VEX_W_0F29) },
8639     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8640     { MOD_TABLE (MOD_VEX_0F2B) },
8641     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8642     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8644     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8645     /* 30 */
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     /* 38 */
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     /* 40 */
8664     { Bad_Opcode },
8665     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8666     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8667     { Bad_Opcode },
8668     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8669     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8670     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8671     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8672     /* 48 */
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8676     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     /* 50 */
8682     { MOD_TABLE (MOD_VEX_0F50) },
8683     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8684     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8685     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8686     { "vandpX",         { XM, Vex, EXx }, 0 },
8687     { "vandnpX",        { XM, Vex, EXx }, 0 },
8688     { "vorpX",          { XM, Vex, EXx }, 0 },
8689     { "vxorpX",         { XM, Vex, EXx }, 0 },
8690     /* 58 */
8691     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8692     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8693     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8694     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8695     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8696     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8699     /* 60 */
8700     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8708     /* 68 */
8709     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8712     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8713     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8714     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8715     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8716     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8717     /* 70 */
8718     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8719     { REG_TABLE (REG_VEX_0F71) },
8720     { REG_TABLE (REG_VEX_0F72) },
8721     { REG_TABLE (REG_VEX_0F73) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8723     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8724     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8726     /* 78 */
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8735     /* 80 */
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     /* 88 */
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     /* 90 */
8754     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     /* 98 */
8763     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     /* a0 */
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     /* a8 */
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { REG_TABLE (REG_VEX_0FAE) },
8788     { Bad_Opcode },
8789     /* b0 */
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     /* b8 */
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     /* c0 */
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8811     { Bad_Opcode },
8812     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8813     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8814     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8815     { Bad_Opcode },
8816     /* c8 */
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     /* d0 */
8826     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8827     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8828     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8829     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8830     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8831     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8832     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8833     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8834     /* d8 */
8835     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8836     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8837     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8838     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8839     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8840     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8841     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8842     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8843     /* e0 */
8844     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8845     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8846     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8847     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8848     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8849     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8850     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8851     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8852     /* e8 */
8853     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8854     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8855     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8856     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8857     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8858     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8859     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8860     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8861     /* f0 */
8862     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8863     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8864     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8865     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8866     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8867     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8868     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8869     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8870     /* f8 */
8871     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8872     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8873     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8874     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8875     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8876     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8877     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8878     { Bad_Opcode },
8879   },
8880   /* VEX_0F38 */
8881   {
8882     /* 00 */
8883     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8891     /* 08 */
8892     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8900     /* 10 */
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8909     /* 18 */
8910     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8913     { Bad_Opcode },
8914     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8917     { Bad_Opcode },
8918     /* 20 */
8919     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     /* 28 */
8928     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8936     /* 30 */
8937     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8945     /* 38 */
8946     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8954     /* 40 */
8955     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8963     /* 48 */
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     /* 50 */
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     /* 58 */
8982     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     /* 60 */
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     /* 68 */
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     /* 70 */
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     /* 78 */
9018     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     /* 80 */
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     /* 88 */
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9041     { Bad_Opcode },
9042     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9043     { Bad_Opcode },
9044     /* 90 */
9045     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9046     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9053     /* 98 */
9054     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9055     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9061     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9062     /* a0 */
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9071     /* a8 */
9072     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9078     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9079     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9080     /* b0 */
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9089     /* b8 */
9090     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9098     /* c0 */
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     /* c8 */
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9116     /* d0 */
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     /* d8 */
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9132     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9134     /* e0 */
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     /* e8 */
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     /* f0 */
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9156     { REG_TABLE (REG_VEX_0F38F3) },
9157     { Bad_Opcode },
9158     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9159     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9160     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9161     /* f8 */
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170   },
9171   /* VEX_0F3A */
9172   {
9173     /* 00 */
9174     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9175     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9176     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9177     { Bad_Opcode },
9178     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9179     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9180     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9181     { Bad_Opcode },
9182     /* 08 */
9183     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9184     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9185     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9186     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9187     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9188     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9189     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9190     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9191     /* 10 */
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9197     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9198     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9199     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9200     /* 18 */
9201     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9202     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     /* 20 */
9210     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9211     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9212     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     /* 28 */
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     /* 30 */
9228     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9229     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9230     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9231     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     /* 38 */
9237     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9238     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     /* 40 */
9246     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9247     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9248     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9249     { Bad_Opcode },
9250     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9251     { Bad_Opcode },
9252     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9253     { Bad_Opcode },
9254     /* 48 */
9255     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9256     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9257     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9258     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9259     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     /* 50 */
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     /* 58 */
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9278     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9279     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9280     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9281     /* 60 */
9282     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9283     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9284     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9285     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     /* 68 */
9291     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9292     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9293     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9294     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9295     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9296     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9297     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9298     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9299     /* 70 */
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     /* 78 */
9309     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9310     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9311     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9312     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9313     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9314     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9315     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9316     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9317     /* 80 */
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     /* 88 */
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     /* 90 */
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     /* 98 */
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347     { Bad_Opcode },
9348     { Bad_Opcode },
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     /* a0 */
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     /* a8 */
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     { Bad_Opcode },
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     /* b0 */
9372     { Bad_Opcode },
9373     { Bad_Opcode },
9374     { Bad_Opcode },
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     /* b8 */
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     /* c0 */
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     /* c8 */
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9406     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9407     /* d0 */
9408     { Bad_Opcode },
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     /* d8 */
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     { Bad_Opcode },
9424     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9425     /* e0 */
9426     { Bad_Opcode },
9427     { Bad_Opcode },
9428     { Bad_Opcode },
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     /* e8 */
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     /* f0 */
9444     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     /* f8 */
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461   },
9462 };
9463
9464 #define NEED_OPCODE_TABLE
9465 #include "i386-dis-evex.h"
9466 #undef NEED_OPCODE_TABLE
9467 static const struct dis386 vex_len_table[][2] = {
9468   /* VEX_LEN_0F10_P_1 */
9469   {
9470     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9471     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9472   },
9473
9474   /* VEX_LEN_0F10_P_3 */
9475   {
9476     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9477     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9478   },
9479
9480   /* VEX_LEN_0F11_P_1 */
9481   {
9482     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9483     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9484   },
9485
9486   /* VEX_LEN_0F11_P_3 */
9487   {
9488     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9489     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9490   },
9491
9492   /* VEX_LEN_0F12_P_0_M_0 */
9493   {
9494     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9495   },
9496
9497   /* VEX_LEN_0F12_P_0_M_1 */
9498   {
9499     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9500   },
9501
9502   /* VEX_LEN_0F12_P_2 */
9503   {
9504     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9505   },
9506
9507   /* VEX_LEN_0F13_M_0 */
9508   {
9509     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9510   },
9511
9512   /* VEX_LEN_0F16_P_0_M_0 */
9513   {
9514     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9515   },
9516
9517   /* VEX_LEN_0F16_P_0_M_1 */
9518   {
9519     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9520   },
9521
9522   /* VEX_LEN_0F16_P_2 */
9523   {
9524     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9525   },
9526
9527   /* VEX_LEN_0F17_M_0 */
9528   {
9529     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9530   },
9531
9532   /* VEX_LEN_0F2A_P_1 */
9533   {
9534     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9535     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9536   },
9537
9538   /* VEX_LEN_0F2A_P_3 */
9539   {
9540     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9541     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9542   },
9543
9544   /* VEX_LEN_0F2C_P_1 */
9545   {
9546     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9547     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9548   },
9549
9550   /* VEX_LEN_0F2C_P_3 */
9551   {
9552     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9553     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9554   },
9555
9556   /* VEX_LEN_0F2D_P_1 */
9557   {
9558     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9559     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9560   },
9561
9562   /* VEX_LEN_0F2D_P_3 */
9563   {
9564     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9565     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9566   },
9567
9568   /* VEX_LEN_0F2E_P_0 */
9569   {
9570     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9571     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9572   },
9573
9574   /* VEX_LEN_0F2E_P_2 */
9575   {
9576     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9577     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9578   },
9579
9580   /* VEX_LEN_0F2F_P_0 */
9581   {
9582     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9583     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9584   },
9585
9586   /* VEX_LEN_0F2F_P_2 */
9587   {
9588     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9589     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9590   },
9591
9592   /* VEX_LEN_0F41_P_0 */
9593   {
9594     { Bad_Opcode },
9595     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9596   },
9597   /* VEX_LEN_0F41_P_2 */
9598   {
9599     { Bad_Opcode },
9600     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9601   },
9602   /* VEX_LEN_0F42_P_0 */
9603   {
9604     { Bad_Opcode },
9605     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9606   },
9607   /* VEX_LEN_0F42_P_2 */
9608   {
9609     { Bad_Opcode },
9610     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9611   },
9612   /* VEX_LEN_0F44_P_0 */
9613   {
9614     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9615   },
9616   /* VEX_LEN_0F44_P_2 */
9617   {
9618     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9619   },
9620   /* VEX_LEN_0F45_P_0 */
9621   {
9622     { Bad_Opcode },
9623     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9624   },
9625   /* VEX_LEN_0F45_P_2 */
9626   {
9627     { Bad_Opcode },
9628     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9629   },
9630   /* VEX_LEN_0F46_P_0 */
9631   {
9632     { Bad_Opcode },
9633     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9634   },
9635   /* VEX_LEN_0F46_P_2 */
9636   {
9637     { Bad_Opcode },
9638     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9639   },
9640   /* VEX_LEN_0F47_P_0 */
9641   {
9642     { Bad_Opcode },
9643     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9644   },
9645   /* VEX_LEN_0F47_P_2 */
9646   {
9647     { Bad_Opcode },
9648     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9649   },
9650   /* VEX_LEN_0F4A_P_0 */
9651   {
9652     { Bad_Opcode },
9653     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9654   },
9655   /* VEX_LEN_0F4A_P_2 */
9656   {
9657     { Bad_Opcode },
9658     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9659   },
9660   /* VEX_LEN_0F4B_P_0 */
9661   {
9662     { Bad_Opcode },
9663     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9664   },
9665   /* VEX_LEN_0F4B_P_2 */
9666   {
9667     { Bad_Opcode },
9668     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9669   },
9670
9671   /* VEX_LEN_0F51_P_1 */
9672   {
9673     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9674     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9675   },
9676
9677   /* VEX_LEN_0F51_P_3 */
9678   {
9679     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9680     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9681   },
9682
9683   /* VEX_LEN_0F52_P_1 */
9684   {
9685     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9686     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9687   },
9688
9689   /* VEX_LEN_0F53_P_1 */
9690   {
9691     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9692     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9693   },
9694
9695   /* VEX_LEN_0F58_P_1 */
9696   {
9697     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9698     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9699   },
9700
9701   /* VEX_LEN_0F58_P_3 */
9702   {
9703     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9704     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9705   },
9706
9707   /* VEX_LEN_0F59_P_1 */
9708   {
9709     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9710     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9711   },
9712
9713   /* VEX_LEN_0F59_P_3 */
9714   {
9715     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9716     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9717   },
9718
9719   /* VEX_LEN_0F5A_P_1 */
9720   {
9721     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9722     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9723   },
9724
9725   /* VEX_LEN_0F5A_P_3 */
9726   {
9727     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9728     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9729   },
9730
9731   /* VEX_LEN_0F5C_P_1 */
9732   {
9733     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9734     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9735   },
9736
9737   /* VEX_LEN_0F5C_P_3 */
9738   {
9739     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9740     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9741   },
9742
9743   /* VEX_LEN_0F5D_P_1 */
9744   {
9745     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9746     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9747   },
9748
9749   /* VEX_LEN_0F5D_P_3 */
9750   {
9751     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9752     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9753   },
9754
9755   /* VEX_LEN_0F5E_P_1 */
9756   {
9757     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9758     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9759   },
9760
9761   /* VEX_LEN_0F5E_P_3 */
9762   {
9763     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9764     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9765   },
9766
9767   /* VEX_LEN_0F5F_P_1 */
9768   {
9769     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9770     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9771   },
9772
9773   /* VEX_LEN_0F5F_P_3 */
9774   {
9775     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9776     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9777   },
9778
9779   /* VEX_LEN_0F6E_P_2 */
9780   {
9781     { "vmovK",          { XMScalar, Edq }, 0 },
9782     { "vmovK",          { XMScalar, Edq }, 0 },
9783   },
9784
9785   /* VEX_LEN_0F7E_P_1 */
9786   {
9787     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9788     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9789   },
9790
9791   /* VEX_LEN_0F7E_P_2 */
9792   {
9793     { "vmovK",          { Edq, XMScalar }, 0 },
9794     { "vmovK",          { Edq, XMScalar }, 0 },
9795   },
9796
9797   /* VEX_LEN_0F90_P_0 */
9798   {
9799     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9800   },
9801
9802   /* VEX_LEN_0F90_P_2 */
9803   {
9804     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9805   },
9806
9807   /* VEX_LEN_0F91_P_0 */
9808   {
9809     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9810   },
9811
9812   /* VEX_LEN_0F91_P_2 */
9813   {
9814     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9815   },
9816
9817   /* VEX_LEN_0F92_P_0 */
9818   {
9819     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9820   },
9821
9822   /* VEX_LEN_0F92_P_2 */
9823   {
9824     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9825   },
9826
9827   /* VEX_LEN_0F92_P_3 */
9828   {
9829     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9830   },
9831
9832   /* VEX_LEN_0F93_P_0 */
9833   {
9834     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9835   },
9836
9837   /* VEX_LEN_0F93_P_2 */
9838   {
9839     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9840   },
9841
9842   /* VEX_LEN_0F93_P_3 */
9843   {
9844     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9845   },
9846
9847   /* VEX_LEN_0F98_P_0 */
9848   {
9849     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9850   },
9851
9852   /* VEX_LEN_0F98_P_2 */
9853   {
9854     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9855   },
9856
9857   /* VEX_LEN_0F99_P_0 */
9858   {
9859     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9860   },
9861
9862   /* VEX_LEN_0F99_P_2 */
9863   {
9864     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9865   },
9866
9867   /* VEX_LEN_0FAE_R_2_M_0 */
9868   {
9869     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9870   },
9871
9872   /* VEX_LEN_0FAE_R_3_M_0 */
9873   {
9874     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9875   },
9876
9877   /* VEX_LEN_0FC2_P_1 */
9878   {
9879     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9880     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9881   },
9882
9883   /* VEX_LEN_0FC2_P_3 */
9884   {
9885     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9886     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9887   },
9888
9889   /* VEX_LEN_0FC4_P_2 */
9890   {
9891     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9892   },
9893
9894   /* VEX_LEN_0FC5_P_2 */
9895   {
9896     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9897   },
9898
9899   /* VEX_LEN_0FD6_P_2 */
9900   {
9901     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9902     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9903   },
9904
9905   /* VEX_LEN_0FF7_P_2 */
9906   {
9907     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9908   },
9909
9910   /* VEX_LEN_0F3816_P_2 */
9911   {
9912     { Bad_Opcode },
9913     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9914   },
9915
9916   /* VEX_LEN_0F3819_P_2 */
9917   {
9918     { Bad_Opcode },
9919     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9920   },
9921
9922   /* VEX_LEN_0F381A_P_2_M_0 */
9923   {
9924     { Bad_Opcode },
9925     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9926   },
9927
9928   /* VEX_LEN_0F3836_P_2 */
9929   {
9930     { Bad_Opcode },
9931     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9932   },
9933
9934   /* VEX_LEN_0F3841_P_2 */
9935   {
9936     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9937   },
9938
9939   /* VEX_LEN_0F385A_P_2_M_0 */
9940   {
9941     { Bad_Opcode },
9942     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9943   },
9944
9945   /* VEX_LEN_0F38DB_P_2 */
9946   {
9947     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9948   },
9949
9950   /* VEX_LEN_0F38F2_P_0 */
9951   {
9952     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9953   },
9954
9955   /* VEX_LEN_0F38F3_R_1_P_0 */
9956   {
9957     { "blsrS",          { VexGdq, Edq }, 0 },
9958   },
9959
9960   /* VEX_LEN_0F38F3_R_2_P_0 */
9961   {
9962     { "blsmskS",        { VexGdq, Edq }, 0 },
9963   },
9964
9965   /* VEX_LEN_0F38F3_R_3_P_0 */
9966   {
9967     { "blsiS",          { VexGdq, Edq }, 0 },
9968   },
9969
9970   /* VEX_LEN_0F38F5_P_0 */
9971   {
9972     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9973   },
9974
9975   /* VEX_LEN_0F38F5_P_1 */
9976   {
9977     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9978   },
9979
9980   /* VEX_LEN_0F38F5_P_3 */
9981   {
9982     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9983   },
9984
9985   /* VEX_LEN_0F38F6_P_3 */
9986   {
9987     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9988   },
9989
9990   /* VEX_LEN_0F38F7_P_0 */
9991   {
9992     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9993   },
9994
9995   /* VEX_LEN_0F38F7_P_1 */
9996   {
9997     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9998   },
9999
10000   /* VEX_LEN_0F38F7_P_2 */
10001   {
10002     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10003   },
10004
10005   /* VEX_LEN_0F38F7_P_3 */
10006   {
10007     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10008   },
10009
10010   /* VEX_LEN_0F3A00_P_2 */
10011   {
10012     { Bad_Opcode },
10013     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10014   },
10015
10016   /* VEX_LEN_0F3A01_P_2 */
10017   {
10018     { Bad_Opcode },
10019     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10020   },
10021
10022   /* VEX_LEN_0F3A06_P_2 */
10023   {
10024     { Bad_Opcode },
10025     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10026   },
10027
10028   /* VEX_LEN_0F3A0A_P_2 */
10029   {
10030     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10031     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10032   },
10033
10034   /* VEX_LEN_0F3A0B_P_2 */
10035   {
10036     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10037     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10038   },
10039
10040   /* VEX_LEN_0F3A14_P_2 */
10041   {
10042     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10043   },
10044
10045   /* VEX_LEN_0F3A15_P_2 */
10046   {
10047     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10048   },
10049
10050   /* VEX_LEN_0F3A16_P_2  */
10051   {
10052     { "vpextrK",        { Edq, XM, Ib }, 0 },
10053   },
10054
10055   /* VEX_LEN_0F3A17_P_2 */
10056   {
10057     { "vextractps",     { Edqd, XM, Ib }, 0 },
10058   },
10059
10060   /* VEX_LEN_0F3A18_P_2 */
10061   {
10062     { Bad_Opcode },
10063     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10064   },
10065
10066   /* VEX_LEN_0F3A19_P_2 */
10067   {
10068     { Bad_Opcode },
10069     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10070   },
10071
10072   /* VEX_LEN_0F3A20_P_2 */
10073   {
10074     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10075   },
10076
10077   /* VEX_LEN_0F3A21_P_2 */
10078   {
10079     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10080   },
10081
10082   /* VEX_LEN_0F3A22_P_2 */
10083   {
10084     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10085   },
10086
10087   /* VEX_LEN_0F3A30_P_2 */
10088   {
10089     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10090   },
10091
10092   /* VEX_LEN_0F3A31_P_2 */
10093   {
10094     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10095   },
10096
10097   /* VEX_LEN_0F3A32_P_2 */
10098   {
10099     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10100   },
10101
10102   /* VEX_LEN_0F3A33_P_2 */
10103   {
10104     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10105   },
10106
10107   /* VEX_LEN_0F3A38_P_2 */
10108   {
10109     { Bad_Opcode },
10110     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10111   },
10112
10113   /* VEX_LEN_0F3A39_P_2 */
10114   {
10115     { Bad_Opcode },
10116     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10117   },
10118
10119   /* VEX_LEN_0F3A41_P_2 */
10120   {
10121     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10122   },
10123
10124   /* VEX_LEN_0F3A46_P_2 */
10125   {
10126     { Bad_Opcode },
10127     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10128   },
10129
10130   /* VEX_LEN_0F3A60_P_2 */
10131   {
10132     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10133   },
10134
10135   /* VEX_LEN_0F3A61_P_2 */
10136   {
10137     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10138   },
10139
10140   /* VEX_LEN_0F3A62_P_2 */
10141   {
10142     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10143   },
10144
10145   /* VEX_LEN_0F3A63_P_2 */
10146   {
10147     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10148   },
10149
10150   /* VEX_LEN_0F3A6A_P_2 */
10151   {
10152     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10153   },
10154
10155   /* VEX_LEN_0F3A6B_P_2 */
10156   {
10157     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10158   },
10159
10160   /* VEX_LEN_0F3A6E_P_2 */
10161   {
10162     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10163   },
10164
10165   /* VEX_LEN_0F3A6F_P_2 */
10166   {
10167     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10168   },
10169
10170   /* VEX_LEN_0F3A7A_P_2 */
10171   {
10172     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10173   },
10174
10175   /* VEX_LEN_0F3A7B_P_2 */
10176   {
10177     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10178   },
10179
10180   /* VEX_LEN_0F3A7E_P_2 */
10181   {
10182     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10183   },
10184
10185   /* VEX_LEN_0F3A7F_P_2 */
10186   {
10187     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10188   },
10189
10190   /* VEX_LEN_0F3ADF_P_2 */
10191   {
10192     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10193   },
10194
10195   /* VEX_LEN_0F3AF0_P_3 */
10196   {
10197     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10198   },
10199
10200   /* VEX_LEN_0FXOP_08_CC */
10201   {
10202      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
10203   },
10204
10205   /* VEX_LEN_0FXOP_08_CD */
10206   {
10207      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
10208   },
10209
10210   /* VEX_LEN_0FXOP_08_CE */
10211   {
10212      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
10213   },
10214
10215   /* VEX_LEN_0FXOP_08_CF */
10216   {
10217      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
10218   },
10219
10220   /* VEX_LEN_0FXOP_08_EC */
10221   {
10222      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
10223   },
10224
10225   /* VEX_LEN_0FXOP_08_ED */
10226   {
10227      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
10228   },
10229
10230   /* VEX_LEN_0FXOP_08_EE */
10231   {
10232      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
10233   },
10234
10235   /* VEX_LEN_0FXOP_08_EF */
10236   {
10237      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
10238   },
10239
10240   /* VEX_LEN_0FXOP_09_80 */
10241   {
10242     { "vfrczps",        { XM, EXxmm }, 0 },
10243     { "vfrczps",        { XM, EXymmq }, 0 },
10244   },
10245
10246   /* VEX_LEN_0FXOP_09_81 */
10247   {
10248     { "vfrczpd",        { XM, EXxmm }, 0 },
10249     { "vfrczpd",        { XM, EXymmq }, 0 },
10250   },
10251 };
10252
10253 static const struct dis386 vex_w_table[][2] = {
10254   {
10255     /* VEX_W_0F10_P_0 */
10256     { "vmovups",        { XM, EXx }, 0 },
10257   },
10258   {
10259     /* VEX_W_0F10_P_1 */
10260     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10261   },
10262   {
10263     /* VEX_W_0F10_P_2 */
10264     { "vmovupd",        { XM, EXx }, 0 },
10265   },
10266   {
10267     /* VEX_W_0F10_P_3 */
10268     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10269   },
10270   {
10271     /* VEX_W_0F11_P_0 */
10272     { "vmovups",        { EXxS, XM }, 0 },
10273   },
10274   {
10275     /* VEX_W_0F11_P_1 */
10276     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10277   },
10278   {
10279     /* VEX_W_0F11_P_2 */
10280     { "vmovupd",        { EXxS, XM }, 0 },
10281   },
10282   {
10283     /* VEX_W_0F11_P_3 */
10284     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10285   },
10286   {
10287     /* VEX_W_0F12_P_0_M_0 */
10288     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10289   },
10290   {
10291     /* VEX_W_0F12_P_0_M_1 */
10292     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10293   },
10294   {
10295     /* VEX_W_0F12_P_1 */
10296     { "vmovsldup",      { XM, EXx }, 0 },
10297   },
10298   {
10299     /* VEX_W_0F12_P_2 */
10300     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10301   },
10302   {
10303     /* VEX_W_0F12_P_3 */
10304     { "vmovddup",       { XM, EXymmq }, 0 },
10305   },
10306   {
10307     /* VEX_W_0F13_M_0 */
10308     { "vmovlpX",        { EXq, XM }, 0 },
10309   },
10310   {
10311     /* VEX_W_0F14 */
10312     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10313   },
10314   {
10315     /* VEX_W_0F15 */
10316     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10317   },
10318   {
10319     /* VEX_W_0F16_P_0_M_0 */
10320     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10321   },
10322   {
10323     /* VEX_W_0F16_P_0_M_1 */
10324     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10325   },
10326   {
10327     /* VEX_W_0F16_P_1 */
10328     { "vmovshdup",      { XM, EXx }, 0 },
10329   },
10330   {
10331     /* VEX_W_0F16_P_2 */
10332     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10333   },
10334   {
10335     /* VEX_W_0F17_M_0 */
10336     { "vmovhpX",        { EXq, XM }, 0 },
10337   },
10338   {
10339     /* VEX_W_0F28 */
10340     { "vmovapX",        { XM, EXx }, 0 },
10341   },
10342   {
10343     /* VEX_W_0F29 */
10344     { "vmovapX",        { EXxS, XM }, 0 },
10345   },
10346   {
10347     /* VEX_W_0F2B_M_0 */
10348     { "vmovntpX",       { Mx, XM }, 0 },
10349   },
10350   {
10351     /* VEX_W_0F2E_P_0 */
10352     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10353   },
10354   {
10355     /* VEX_W_0F2E_P_2 */
10356     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10357   },
10358   {
10359     /* VEX_W_0F2F_P_0 */
10360     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10361   },
10362   {
10363     /* VEX_W_0F2F_P_2 */
10364     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10365   },
10366   {
10367     /* VEX_W_0F41_P_0_LEN_1 */
10368     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10369     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10370   },
10371   {
10372     /* VEX_W_0F41_P_2_LEN_1 */
10373     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10374     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10375   },
10376   {
10377     /* VEX_W_0F42_P_0_LEN_1 */
10378     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10379     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10380   },
10381   {
10382     /* VEX_W_0F42_P_2_LEN_1 */
10383     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10384     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10385   },
10386   {
10387     /* VEX_W_0F44_P_0_LEN_0 */
10388     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10389     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10390   },
10391   {
10392     /* VEX_W_0F44_P_2_LEN_0 */
10393     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10394     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10395   },
10396   {
10397     /* VEX_W_0F45_P_0_LEN_1 */
10398     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10399     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10400   },
10401   {
10402     /* VEX_W_0F45_P_2_LEN_1 */
10403     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10404     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10405   },
10406   {
10407     /* VEX_W_0F46_P_0_LEN_1 */
10408     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10409     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10410   },
10411   {
10412     /* VEX_W_0F46_P_2_LEN_1 */
10413     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10414     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10415   },
10416   {
10417     /* VEX_W_0F47_P_0_LEN_1 */
10418     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10419     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10420   },
10421   {
10422     /* VEX_W_0F47_P_2_LEN_1 */
10423     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10424     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10425   },
10426   {
10427     /* VEX_W_0F4A_P_0_LEN_1 */
10428     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10429     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10430   },
10431   {
10432     /* VEX_W_0F4A_P_2_LEN_1 */
10433     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10434     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10435   },
10436   {
10437     /* VEX_W_0F4B_P_0_LEN_1 */
10438     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10439     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10440   },
10441   {
10442     /* VEX_W_0F4B_P_2_LEN_1 */
10443     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10444   },
10445   {
10446     /* VEX_W_0F50_M_0 */
10447     { "vmovmskpX",      { Gdq, XS }, 0 },
10448   },
10449   {
10450     /* VEX_W_0F51_P_0 */
10451     { "vsqrtps",        { XM, EXx }, 0 },
10452   },
10453   {
10454     /* VEX_W_0F51_P_1 */
10455     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10456   },
10457   {
10458     /* VEX_W_0F51_P_2  */
10459     { "vsqrtpd",        { XM, EXx }, 0 },
10460   },
10461   {
10462     /* VEX_W_0F51_P_3 */
10463     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10464   },
10465   {
10466     /* VEX_W_0F52_P_0 */
10467     { "vrsqrtps",       { XM, EXx }, 0 },
10468   },
10469   {
10470     /* VEX_W_0F52_P_1 */
10471     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10472   },
10473   {
10474     /* VEX_W_0F53_P_0  */
10475     { "vrcpps",         { XM, EXx }, 0 },
10476   },
10477   {
10478     /* VEX_W_0F53_P_1  */
10479     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10480   },
10481   {
10482     /* VEX_W_0F58_P_0  */
10483     { "vaddps",         { XM, Vex, EXx }, 0 },
10484   },
10485   {
10486     /* VEX_W_0F58_P_1  */
10487     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10488   },
10489   {
10490     /* VEX_W_0F58_P_2  */
10491     { "vaddpd",         { XM, Vex, EXx }, 0 },
10492   },
10493   {
10494     /* VEX_W_0F58_P_3  */
10495     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10496   },
10497   {
10498     /* VEX_W_0F59_P_0  */
10499     { "vmulps",         { XM, Vex, EXx }, 0 },
10500   },
10501   {
10502     /* VEX_W_0F59_P_1  */
10503     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10504   },
10505   {
10506     /* VEX_W_0F59_P_2  */
10507     { "vmulpd",         { XM, Vex, EXx }, 0 },
10508   },
10509   {
10510     /* VEX_W_0F59_P_3  */
10511     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10512   },
10513   {
10514     /* VEX_W_0F5A_P_0  */
10515     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10516   },
10517   {
10518     /* VEX_W_0F5A_P_1  */
10519     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10520   },
10521   {
10522     /* VEX_W_0F5A_P_3  */
10523     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10524   },
10525   {
10526     /* VEX_W_0F5B_P_0  */
10527     { "vcvtdq2ps",      { XM, EXx }, 0 },
10528   },
10529   {
10530     /* VEX_W_0F5B_P_1  */
10531     { "vcvttps2dq",     { XM, EXx }, 0 },
10532   },
10533   {
10534     /* VEX_W_0F5B_P_2  */
10535     { "vcvtps2dq",      { XM, EXx }, 0 },
10536   },
10537   {
10538     /* VEX_W_0F5C_P_0  */
10539     { "vsubps",         { XM, Vex, EXx }, 0 },
10540   },
10541   {
10542     /* VEX_W_0F5C_P_1  */
10543     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10544   },
10545   {
10546     /* VEX_W_0F5C_P_2  */
10547     { "vsubpd",         { XM, Vex, EXx }, 0 },
10548   },
10549   {
10550     /* VEX_W_0F5C_P_3  */
10551     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10552   },
10553   {
10554     /* VEX_W_0F5D_P_0  */
10555     { "vminps",         { XM, Vex, EXx }, 0 },
10556   },
10557   {
10558     /* VEX_W_0F5D_P_1  */
10559     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10560   },
10561   {
10562     /* VEX_W_0F5D_P_2  */
10563     { "vminpd",         { XM, Vex, EXx }, 0 },
10564   },
10565   {
10566     /* VEX_W_0F5D_P_3  */
10567     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10568   },
10569   {
10570     /* VEX_W_0F5E_P_0  */
10571     { "vdivps",         { XM, Vex, EXx }, 0 },
10572   },
10573   {
10574     /* VEX_W_0F5E_P_1  */
10575     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10576   },
10577   {
10578     /* VEX_W_0F5E_P_2  */
10579     { "vdivpd",         { XM, Vex, EXx }, 0 },
10580   },
10581   {
10582     /* VEX_W_0F5E_P_3  */
10583     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10584   },
10585   {
10586     /* VEX_W_0F5F_P_0  */
10587     { "vmaxps",         { XM, Vex, EXx }, 0 },
10588   },
10589   {
10590     /* VEX_W_0F5F_P_1  */
10591     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10592   },
10593   {
10594     /* VEX_W_0F5F_P_2  */
10595     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10596   },
10597   {
10598     /* VEX_W_0F5F_P_3  */
10599     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10600   },
10601   {
10602     /* VEX_W_0F60_P_2  */
10603     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10604   },
10605   {
10606     /* VEX_W_0F61_P_2  */
10607     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10608   },
10609   {
10610     /* VEX_W_0F62_P_2  */
10611     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10612   },
10613   {
10614     /* VEX_W_0F63_P_2  */
10615     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10616   },
10617   {
10618     /* VEX_W_0F64_P_2  */
10619     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10620   },
10621   {
10622     /* VEX_W_0F65_P_2  */
10623     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10624   },
10625   {
10626     /* VEX_W_0F66_P_2  */
10627     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10628   },
10629   {
10630     /* VEX_W_0F67_P_2  */
10631     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10632   },
10633   {
10634     /* VEX_W_0F68_P_2  */
10635     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10636   },
10637   {
10638     /* VEX_W_0F69_P_2  */
10639     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10640   },
10641   {
10642     /* VEX_W_0F6A_P_2  */
10643     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10644   },
10645   {
10646     /* VEX_W_0F6B_P_2  */
10647     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10648   },
10649   {
10650     /* VEX_W_0F6C_P_2  */
10651     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10652   },
10653   {
10654     /* VEX_W_0F6D_P_2  */
10655     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10656   },
10657   {
10658     /* VEX_W_0F6F_P_1  */
10659     { "vmovdqu",        { XM, EXx }, 0 },
10660   },
10661   {
10662     /* VEX_W_0F6F_P_2  */
10663     { "vmovdqa",        { XM, EXx }, 0 },
10664   },
10665   {
10666     /* VEX_W_0F70_P_1 */
10667     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10668   },
10669   {
10670     /* VEX_W_0F70_P_2 */
10671     { "vpshufd",        { XM, EXx, Ib }, 0 },
10672   },
10673   {
10674     /* VEX_W_0F70_P_3 */
10675     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10676   },
10677   {
10678     /* VEX_W_0F71_R_2_P_2  */
10679     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10680   },
10681   {
10682     /* VEX_W_0F71_R_4_P_2  */
10683     { "vpsraw",         { Vex, XS, Ib }, 0 },
10684   },
10685   {
10686     /* VEX_W_0F71_R_6_P_2  */
10687     { "vpsllw",         { Vex, XS, Ib }, 0 },
10688   },
10689   {
10690     /* VEX_W_0F72_R_2_P_2  */
10691     { "vpsrld",         { Vex, XS, Ib }, 0 },
10692   },
10693   {
10694     /* VEX_W_0F72_R_4_P_2  */
10695     { "vpsrad",         { Vex, XS, Ib }, 0 },
10696   },
10697   {
10698     /* VEX_W_0F72_R_6_P_2  */
10699     { "vpslld",         { Vex, XS, Ib }, 0 },
10700   },
10701   {
10702     /* VEX_W_0F73_R_2_P_2  */
10703     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10704   },
10705   {
10706     /* VEX_W_0F73_R_3_P_2  */
10707     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10708   },
10709   {
10710     /* VEX_W_0F73_R_6_P_2  */
10711     { "vpsllq",         { Vex, XS, Ib }, 0 },
10712   },
10713   {
10714     /* VEX_W_0F73_R_7_P_2  */
10715     { "vpslldq",        { Vex, XS, Ib }, 0 },
10716   },
10717   {
10718     /* VEX_W_0F74_P_2 */
10719     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10720   },
10721   {
10722     /* VEX_W_0F75_P_2 */
10723     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10724   },
10725   {
10726     /* VEX_W_0F76_P_2 */
10727     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10728   },
10729   {
10730     /* VEX_W_0F77_P_0 */
10731     { "",               { VZERO }, 0 },
10732   },
10733   {
10734     /* VEX_W_0F7C_P_2 */
10735     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10736   },
10737   {
10738     /* VEX_W_0F7C_P_3 */
10739     { "vhaddps",        { XM, Vex, EXx }, 0 },
10740   },
10741   {
10742     /* VEX_W_0F7D_P_2 */
10743     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10744   },
10745   {
10746     /* VEX_W_0F7D_P_3 */
10747     { "vhsubps",        { XM, Vex, EXx }, 0 },
10748   },
10749   {
10750     /* VEX_W_0F7E_P_1 */
10751     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10752   },
10753   {
10754     /* VEX_W_0F7F_P_1 */
10755     { "vmovdqu",        { EXxS, XM }, 0 },
10756   },
10757   {
10758     /* VEX_W_0F7F_P_2 */
10759     { "vmovdqa",        { EXxS, XM }, 0 },
10760   },
10761   {
10762     /* VEX_W_0F90_P_0_LEN_0 */
10763     { "kmovw",          { MaskG, MaskE }, 0 },
10764     { "kmovq",          { MaskG, MaskE }, 0 },
10765   },
10766   {
10767     /* VEX_W_0F90_P_2_LEN_0 */
10768     { "kmovb",          { MaskG, MaskBDE }, 0 },
10769     { "kmovd",          { MaskG, MaskBDE }, 0 },
10770   },
10771   {
10772     /* VEX_W_0F91_P_0_LEN_0 */
10773     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10774     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10775   },
10776   {
10777     /* VEX_W_0F91_P_2_LEN_0 */
10778     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10779     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10780   },
10781   {
10782     /* VEX_W_0F92_P_0_LEN_0 */
10783     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10784   },
10785   {
10786     /* VEX_W_0F92_P_2_LEN_0 */
10787     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10788   },
10789   {
10790     /* VEX_W_0F92_P_3_LEN_0 */
10791     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10792     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10793   },
10794   {
10795     /* VEX_W_0F93_P_0_LEN_0 */
10796     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10797   },
10798   {
10799     /* VEX_W_0F93_P_2_LEN_0 */
10800     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10801   },
10802   {
10803     /* VEX_W_0F93_P_3_LEN_0 */
10804     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10805     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10806   },
10807   {
10808     /* VEX_W_0F98_P_0_LEN_0 */
10809     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10810     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10811   },
10812   {
10813     /* VEX_W_0F98_P_2_LEN_0 */
10814     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10815     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10816   },
10817   {
10818     /* VEX_W_0F99_P_0_LEN_0 */
10819     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10820     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10821   },
10822   {
10823     /* VEX_W_0F99_P_2_LEN_0 */
10824     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10825     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10826   },
10827   {
10828     /* VEX_W_0FAE_R_2_M_0 */
10829     { "vldmxcsr",       { Md }, 0 },
10830   },
10831   {
10832     /* VEX_W_0FAE_R_3_M_0 */
10833     { "vstmxcsr",       { Md }, 0 },
10834   },
10835   {
10836     /* VEX_W_0FC2_P_0 */
10837     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10838   },
10839   {
10840     /* VEX_W_0FC2_P_1 */
10841     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10842   },
10843   {
10844     /* VEX_W_0FC2_P_2 */
10845     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10846   },
10847   {
10848     /* VEX_W_0FC2_P_3 */
10849     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10850   },
10851   {
10852     /* VEX_W_0FC4_P_2 */
10853     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10854   },
10855   {
10856     /* VEX_W_0FC5_P_2 */
10857     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10858   },
10859   {
10860     /* VEX_W_0FD0_P_2 */
10861     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10862   },
10863   {
10864     /* VEX_W_0FD0_P_3 */
10865     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10866   },
10867   {
10868     /* VEX_W_0FD1_P_2 */
10869     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10870   },
10871   {
10872     /* VEX_W_0FD2_P_2 */
10873     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10874   },
10875   {
10876     /* VEX_W_0FD3_P_2 */
10877     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10878   },
10879   {
10880     /* VEX_W_0FD4_P_2 */
10881     { "vpaddq",         { XM, Vex, EXx }, 0 },
10882   },
10883   {
10884     /* VEX_W_0FD5_P_2 */
10885     { "vpmullw",        { XM, Vex, EXx }, 0 },
10886   },
10887   {
10888     /* VEX_W_0FD6_P_2 */
10889     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10890   },
10891   {
10892     /* VEX_W_0FD7_P_2_M_1 */
10893     { "vpmovmskb",      { Gdq, XS }, 0 },
10894   },
10895   {
10896     /* VEX_W_0FD8_P_2 */
10897     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10898   },
10899   {
10900     /* VEX_W_0FD9_P_2 */
10901     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10902   },
10903   {
10904     /* VEX_W_0FDA_P_2 */
10905     { "vpminub",        { XM, Vex, EXx }, 0 },
10906   },
10907   {
10908     /* VEX_W_0FDB_P_2 */
10909     { "vpand",          { XM, Vex, EXx }, 0 },
10910   },
10911   {
10912     /* VEX_W_0FDC_P_2 */
10913     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10914   },
10915   {
10916     /* VEX_W_0FDD_P_2 */
10917     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10918   },
10919   {
10920     /* VEX_W_0FDE_P_2 */
10921     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10922   },
10923   {
10924     /* VEX_W_0FDF_P_2 */
10925     { "vpandn",         { XM, Vex, EXx }, 0 },
10926   },
10927   {
10928     /* VEX_W_0FE0_P_2  */
10929     { "vpavgb",         { XM, Vex, EXx }, 0 },
10930   },
10931   {
10932     /* VEX_W_0FE1_P_2  */
10933     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10934   },
10935   {
10936     /* VEX_W_0FE2_P_2  */
10937     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10938   },
10939   {
10940     /* VEX_W_0FE3_P_2  */
10941     { "vpavgw",         { XM, Vex, EXx }, 0 },
10942   },
10943   {
10944     /* VEX_W_0FE4_P_2  */
10945     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
10946   },
10947   {
10948     /* VEX_W_0FE5_P_2  */
10949     { "vpmulhw",        { XM, Vex, EXx }, 0 },
10950   },
10951   {
10952     /* VEX_W_0FE6_P_1  */
10953     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
10954   },
10955   {
10956     /* VEX_W_0FE6_P_2  */
10957     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
10958   },
10959   {
10960     /* VEX_W_0FE6_P_3  */
10961     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
10962   },
10963   {
10964     /* VEX_W_0FE7_P_2_M_0 */
10965     { "vmovntdq",       { Mx, XM }, 0 },
10966   },
10967   {
10968     /* VEX_W_0FE8_P_2  */
10969     { "vpsubsb",        { XM, Vex, EXx }, 0 },
10970   },
10971   {
10972     /* VEX_W_0FE9_P_2  */
10973     { "vpsubsw",        { XM, Vex, EXx }, 0 },
10974   },
10975   {
10976     /* VEX_W_0FEA_P_2  */
10977     { "vpminsw",        { XM, Vex, EXx }, 0 },
10978   },
10979   {
10980     /* VEX_W_0FEB_P_2  */
10981     { "vpor",           { XM, Vex, EXx }, 0 },
10982   },
10983   {
10984     /* VEX_W_0FEC_P_2  */
10985     { "vpaddsb",        { XM, Vex, EXx }, 0 },
10986   },
10987   {
10988     /* VEX_W_0FED_P_2  */
10989     { "vpaddsw",        { XM, Vex, EXx }, 0 },
10990   },
10991   {
10992     /* VEX_W_0FEE_P_2  */
10993     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
10994   },
10995   {
10996     /* VEX_W_0FEF_P_2  */
10997     { "vpxor",          { XM, Vex, EXx }, 0 },
10998   },
10999   {
11000     /* VEX_W_0FF0_P_3_M_0 */
11001     { "vlddqu",         { XM, M }, 0 },
11002   },
11003   {
11004     /* VEX_W_0FF1_P_2 */
11005     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11006   },
11007   {
11008     /* VEX_W_0FF2_P_2 */
11009     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11010   },
11011   {
11012     /* VEX_W_0FF3_P_2 */
11013     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11014   },
11015   {
11016     /* VEX_W_0FF4_P_2 */
11017     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11018   },
11019   {
11020     /* VEX_W_0FF5_P_2 */
11021     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11022   },
11023   {
11024     /* VEX_W_0FF6_P_2 */
11025     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11026   },
11027   {
11028     /* VEX_W_0FF7_P_2 */
11029     { "vmaskmovdqu",    { XM, XS }, 0 },
11030   },
11031   {
11032     /* VEX_W_0FF8_P_2 */
11033     { "vpsubb",         { XM, Vex, EXx }, 0 },
11034   },
11035   {
11036     /* VEX_W_0FF9_P_2 */
11037     { "vpsubw",         { XM, Vex, EXx }, 0 },
11038   },
11039   {
11040     /* VEX_W_0FFA_P_2 */
11041     { "vpsubd",         { XM, Vex, EXx }, 0 },
11042   },
11043   {
11044     /* VEX_W_0FFB_P_2 */
11045     { "vpsubq",         { XM, Vex, EXx }, 0 },
11046   },
11047   {
11048     /* VEX_W_0FFC_P_2 */
11049     { "vpaddb",         { XM, Vex, EXx }, 0 },
11050   },
11051   {
11052     /* VEX_W_0FFD_P_2 */
11053     { "vpaddw",         { XM, Vex, EXx }, 0 },
11054   },
11055   {
11056     /* VEX_W_0FFE_P_2 */
11057     { "vpaddd",         { XM, Vex, EXx }, 0 },
11058   },
11059   {
11060     /* VEX_W_0F3800_P_2  */
11061     { "vpshufb",        { XM, Vex, EXx }, 0 },
11062   },
11063   {
11064     /* VEX_W_0F3801_P_2  */
11065     { "vphaddw",        { XM, Vex, EXx }, 0 },
11066   },
11067   {
11068     /* VEX_W_0F3802_P_2  */
11069     { "vphaddd",        { XM, Vex, EXx }, 0 },
11070   },
11071   {
11072     /* VEX_W_0F3803_P_2  */
11073     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11074   },
11075   {
11076     /* VEX_W_0F3804_P_2  */
11077     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11078   },
11079   {
11080     /* VEX_W_0F3805_P_2  */
11081     { "vphsubw",        { XM, Vex, EXx }, 0 },
11082   },
11083   {
11084     /* VEX_W_0F3806_P_2  */
11085     { "vphsubd",        { XM, Vex, EXx }, 0 },
11086   },
11087   {
11088     /* VEX_W_0F3807_P_2  */
11089     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11090   },
11091   {
11092     /* VEX_W_0F3808_P_2  */
11093     { "vpsignb",        { XM, Vex, EXx }, 0 },
11094   },
11095   {
11096     /* VEX_W_0F3809_P_2  */
11097     { "vpsignw",        { XM, Vex, EXx }, 0 },
11098   },
11099   {
11100     /* VEX_W_0F380A_P_2  */
11101     { "vpsignd",        { XM, Vex, EXx }, 0 },
11102   },
11103   {
11104     /* VEX_W_0F380B_P_2  */
11105     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11106   },
11107   {
11108     /* VEX_W_0F380C_P_2  */
11109     { "vpermilps",      { XM, Vex, EXx }, 0 },
11110   },
11111   {
11112     /* VEX_W_0F380D_P_2  */
11113     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11114   },
11115   {
11116     /* VEX_W_0F380E_P_2  */
11117     { "vtestps",        { XM, EXx }, 0 },
11118   },
11119   {
11120     /* VEX_W_0F380F_P_2  */
11121     { "vtestpd",        { XM, EXx }, 0 },
11122   },
11123   {
11124     /* VEX_W_0F3816_P_2  */
11125     { "vpermps",        { XM, Vex, EXx }, 0 },
11126   },
11127   {
11128     /* VEX_W_0F3817_P_2 */
11129     { "vptest",         { XM, EXx }, 0 },
11130   },
11131   {
11132     /* VEX_W_0F3818_P_2 */
11133     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11134   },
11135   {
11136     /* VEX_W_0F3819_P_2 */
11137     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11138   },
11139   {
11140     /* VEX_W_0F381A_P_2_M_0 */
11141     { "vbroadcastf128", { XM, Mxmm }, 0 },
11142   },
11143   {
11144     /* VEX_W_0F381C_P_2 */
11145     { "vpabsb",         { XM, EXx }, 0 },
11146   },
11147   {
11148     /* VEX_W_0F381D_P_2 */
11149     { "vpabsw",         { XM, EXx }, 0 },
11150   },
11151   {
11152     /* VEX_W_0F381E_P_2 */
11153     { "vpabsd",         { XM, EXx }, 0 },
11154   },
11155   {
11156     /* VEX_W_0F3820_P_2 */
11157     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11158   },
11159   {
11160     /* VEX_W_0F3821_P_2 */
11161     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11162   },
11163   {
11164     /* VEX_W_0F3822_P_2 */
11165     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11166   },
11167   {
11168     /* VEX_W_0F3823_P_2 */
11169     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11170   },
11171   {
11172     /* VEX_W_0F3824_P_2 */
11173     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11174   },
11175   {
11176     /* VEX_W_0F3825_P_2 */
11177     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11178   },
11179   {
11180     /* VEX_W_0F3828_P_2 */
11181     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11182   },
11183   {
11184     /* VEX_W_0F3829_P_2 */
11185     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11186   },
11187   {
11188     /* VEX_W_0F382A_P_2_M_0 */
11189     { "vmovntdqa",      { XM, Mx }, 0 },
11190   },
11191   {
11192     /* VEX_W_0F382B_P_2 */
11193     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11194   },
11195   {
11196     /* VEX_W_0F382C_P_2_M_0 */
11197     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11198   },
11199   {
11200     /* VEX_W_0F382D_P_2_M_0 */
11201     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11202   },
11203   {
11204     /* VEX_W_0F382E_P_2_M_0 */
11205     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11206   },
11207   {
11208     /* VEX_W_0F382F_P_2_M_0 */
11209     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11210   },
11211   {
11212     /* VEX_W_0F3830_P_2 */
11213     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11214   },
11215   {
11216     /* VEX_W_0F3831_P_2 */
11217     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11218   },
11219   {
11220     /* VEX_W_0F3832_P_2 */
11221     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11222   },
11223   {
11224     /* VEX_W_0F3833_P_2 */
11225     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11226   },
11227   {
11228     /* VEX_W_0F3834_P_2 */
11229     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11230   },
11231   {
11232     /* VEX_W_0F3835_P_2 */
11233     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11234   },
11235   {
11236     /* VEX_W_0F3836_P_2  */
11237     { "vpermd",         { XM, Vex, EXx }, 0 },
11238   },
11239   {
11240     /* VEX_W_0F3837_P_2 */
11241     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11242   },
11243   {
11244     /* VEX_W_0F3838_P_2 */
11245     { "vpminsb",        { XM, Vex, EXx }, 0 },
11246   },
11247   {
11248     /* VEX_W_0F3839_P_2 */
11249     { "vpminsd",        { XM, Vex, EXx }, 0 },
11250   },
11251   {
11252     /* VEX_W_0F383A_P_2 */
11253     { "vpminuw",        { XM, Vex, EXx }, 0 },
11254   },
11255   {
11256     /* VEX_W_0F383B_P_2 */
11257     { "vpminud",        { XM, Vex, EXx }, 0 },
11258   },
11259   {
11260     /* VEX_W_0F383C_P_2 */
11261     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11262   },
11263   {
11264     /* VEX_W_0F383D_P_2 */
11265     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11266   },
11267   {
11268     /* VEX_W_0F383E_P_2 */
11269     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11270   },
11271   {
11272     /* VEX_W_0F383F_P_2 */
11273     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11274   },
11275   {
11276     /* VEX_W_0F3840_P_2 */
11277     { "vpmulld",        { XM, Vex, EXx }, 0 },
11278   },
11279   {
11280     /* VEX_W_0F3841_P_2 */
11281     { "vphminposuw",    { XM, EXx }, 0 },
11282   },
11283   {
11284     /* VEX_W_0F3846_P_2 */
11285     { "vpsravd",        { XM, Vex, EXx }, 0 },
11286   },
11287   {
11288     /* VEX_W_0F3858_P_2 */
11289     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11290   },
11291   {
11292     /* VEX_W_0F3859_P_2 */
11293     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11294   },
11295   {
11296     /* VEX_W_0F385A_P_2_M_0 */
11297     { "vbroadcasti128", { XM, Mxmm }, 0 },
11298   },
11299   {
11300     /* VEX_W_0F3878_P_2 */
11301     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11302   },
11303   {
11304     /* VEX_W_0F3879_P_2 */
11305     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11306   },
11307   {
11308     /* VEX_W_0F38CF_P_2 */
11309     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
11310   },
11311   {
11312     /* VEX_W_0F38DB_P_2 */
11313     { "vaesimc",        { XM, EXx }, 0 },
11314   },
11315   {
11316     /* VEX_W_0F3A00_P_2 */
11317     { Bad_Opcode },
11318     { "vpermq",         { XM, EXx, Ib }, 0 },
11319   },
11320   {
11321     /* VEX_W_0F3A01_P_2 */
11322     { Bad_Opcode },
11323     { "vpermpd",        { XM, EXx, Ib }, 0 },
11324   },
11325   {
11326     /* VEX_W_0F3A02_P_2 */
11327     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11328   },
11329   {
11330     /* VEX_W_0F3A04_P_2 */
11331     { "vpermilps",      { XM, EXx, Ib }, 0 },
11332   },
11333   {
11334     /* VEX_W_0F3A05_P_2 */
11335     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11336   },
11337   {
11338     /* VEX_W_0F3A06_P_2 */
11339     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11340   },
11341   {
11342     /* VEX_W_0F3A08_P_2 */
11343     { "vroundps",       { XM, EXx, Ib }, 0 },
11344   },
11345   {
11346     /* VEX_W_0F3A09_P_2 */
11347     { "vroundpd",       { XM, EXx, Ib }, 0 },
11348   },
11349   {
11350     /* VEX_W_0F3A0A_P_2 */
11351     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11352   },
11353   {
11354     /* VEX_W_0F3A0B_P_2 */
11355     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11356   },
11357   {
11358     /* VEX_W_0F3A0C_P_2 */
11359     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11360   },
11361   {
11362     /* VEX_W_0F3A0D_P_2 */
11363     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11364   },
11365   {
11366     /* VEX_W_0F3A0E_P_2 */
11367     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11368   },
11369   {
11370     /* VEX_W_0F3A0F_P_2 */
11371     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11372   },
11373   {
11374     /* VEX_W_0F3A14_P_2 */
11375     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11376   },
11377   {
11378     /* VEX_W_0F3A15_P_2 */
11379     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11380   },
11381   {
11382     /* VEX_W_0F3A18_P_2 */
11383     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11384   },
11385   {
11386     /* VEX_W_0F3A19_P_2 */
11387     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11388   },
11389   {
11390     /* VEX_W_0F3A20_P_2 */
11391     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11392   },
11393   {
11394     /* VEX_W_0F3A21_P_2 */
11395     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11396   },
11397   {
11398     /* VEX_W_0F3A30_P_2_LEN_0 */
11399     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11400     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11401   },
11402   {
11403     /* VEX_W_0F3A31_P_2_LEN_0 */
11404     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11405     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11406   },
11407   {
11408     /* VEX_W_0F3A32_P_2_LEN_0 */
11409     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11410     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11411   },
11412   {
11413     /* VEX_W_0F3A33_P_2_LEN_0 */
11414     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11415     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11416   },
11417   {
11418     /* VEX_W_0F3A38_P_2 */
11419     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11420   },
11421   {
11422     /* VEX_W_0F3A39_P_2 */
11423     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11424   },
11425   {
11426     /* VEX_W_0F3A40_P_2 */
11427     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11428   },
11429   {
11430     /* VEX_W_0F3A41_P_2 */
11431     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11432   },
11433   {
11434     /* VEX_W_0F3A42_P_2 */
11435     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11436   },
11437   {
11438     /* VEX_W_0F3A46_P_2 */
11439     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11440   },
11441   {
11442     /* VEX_W_0F3A48_P_2 */
11443     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11444     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11445   },
11446   {
11447     /* VEX_W_0F3A49_P_2 */
11448     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11449     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11450   },
11451   {
11452     /* VEX_W_0F3A4A_P_2 */
11453     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11454   },
11455   {
11456     /* VEX_W_0F3A4B_P_2 */
11457     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11458   },
11459   {
11460     /* VEX_W_0F3A4C_P_2 */
11461     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11462   },
11463   {
11464     /* VEX_W_0F3A62_P_2 */
11465     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11466   },
11467   {
11468     /* VEX_W_0F3A63_P_2 */
11469     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11470   },
11471   {
11472     /* VEX_W_0F3ACE_P_2 */
11473     { Bad_Opcode },
11474     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
11475   },
11476   {
11477     /* VEX_W_0F3ACF_P_2 */
11478     { Bad_Opcode },
11479     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
11480   },
11481   {
11482     /* VEX_W_0F3ADF_P_2 */
11483     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11484   },
11485 #define NEED_VEX_W_TABLE
11486 #include "i386-dis-evex.h"
11487 #undef NEED_VEX_W_TABLE
11488 };
11489
11490 static const struct dis386 mod_table[][2] = {
11491   {
11492     /* MOD_8D */
11493     { "leaS",           { Gv, M }, 0 },
11494   },
11495   {
11496     /* MOD_C6_REG_7 */
11497     { Bad_Opcode },
11498     { RM_TABLE (RM_C6_REG_7) },
11499   },
11500   {
11501     /* MOD_C7_REG_7 */
11502     { Bad_Opcode },
11503     { RM_TABLE (RM_C7_REG_7) },
11504   },
11505   {
11506     /* MOD_FF_REG_3 */
11507     { "Jcall^", { indirEp }, 0 },
11508   },
11509   {
11510     /* MOD_FF_REG_5 */
11511     { "Jjmp^", { indirEp }, 0 },
11512   },
11513   {
11514     /* MOD_0F01_REG_0 */
11515     { X86_64_TABLE (X86_64_0F01_REG_0) },
11516     { RM_TABLE (RM_0F01_REG_0) },
11517   },
11518   {
11519     /* MOD_0F01_REG_1 */
11520     { X86_64_TABLE (X86_64_0F01_REG_1) },
11521     { RM_TABLE (RM_0F01_REG_1) },
11522   },
11523   {
11524     /* MOD_0F01_REG_2 */
11525     { X86_64_TABLE (X86_64_0F01_REG_2) },
11526     { RM_TABLE (RM_0F01_REG_2) },
11527   },
11528   {
11529     /* MOD_0F01_REG_3 */
11530     { X86_64_TABLE (X86_64_0F01_REG_3) },
11531     { RM_TABLE (RM_0F01_REG_3) },
11532   },
11533   {
11534     /* MOD_0F01_REG_5 */
11535     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11536     { RM_TABLE (RM_0F01_REG_5) },
11537   },
11538   {
11539     /* MOD_0F01_REG_7 */
11540     { "invlpg",         { Mb }, 0 },
11541     { RM_TABLE (RM_0F01_REG_7) },
11542   },
11543   {
11544     /* MOD_0F12_PREFIX_0 */
11545     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11546     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11547   },
11548   {
11549     /* MOD_0F13 */
11550     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11551   },
11552   {
11553     /* MOD_0F16_PREFIX_0 */
11554     { "movhps",         { XM, EXq }, 0 },
11555     { "movlhps",        { XM, EXq }, 0 },
11556   },
11557   {
11558     /* MOD_0F17 */
11559     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11560   },
11561   {
11562     /* MOD_0F18_REG_0 */
11563     { "prefetchnta",    { Mb }, 0 },
11564   },
11565   {
11566     /* MOD_0F18_REG_1 */
11567     { "prefetcht0",     { Mb }, 0 },
11568   },
11569   {
11570     /* MOD_0F18_REG_2 */
11571     { "prefetcht1",     { Mb }, 0 },
11572   },
11573   {
11574     /* MOD_0F18_REG_3 */
11575     { "prefetcht2",     { Mb }, 0 },
11576   },
11577   {
11578     /* MOD_0F18_REG_4 */
11579     { "nop/reserved",   { Mb }, 0 },
11580   },
11581   {
11582     /* MOD_0F18_REG_5 */
11583     { "nop/reserved",   { Mb }, 0 },
11584   },
11585   {
11586     /* MOD_0F18_REG_6 */
11587     { "nop/reserved",   { Mb }, 0 },
11588   },
11589   {
11590     /* MOD_0F18_REG_7 */
11591     { "nop/reserved",   { Mb }, 0 },
11592   },
11593   {
11594     /* MOD_0F1A_PREFIX_0 */
11595     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11596     { "nopQ",           { Ev }, 0 },
11597   },
11598   {
11599     /* MOD_0F1B_PREFIX_0 */
11600     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11601     { "nopQ",           { Ev }, 0 },
11602   },
11603   {
11604     /* MOD_0F1B_PREFIX_1 */
11605     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11606     { "nopQ",           { Ev }, 0 },
11607   },
11608   {
11609     /* MOD_0F1E_PREFIX_1 */
11610     { "nopQ",           { Ev }, 0 },
11611     { REG_TABLE (REG_0F1E_MOD_3) },
11612   },
11613   {
11614     /* MOD_0F24 */
11615     { Bad_Opcode },
11616     { "movL",           { Rd, Td }, 0 },
11617   },
11618   {
11619     /* MOD_0F26 */
11620     { Bad_Opcode },
11621     { "movL",           { Td, Rd }, 0 },
11622   },
11623   {
11624     /* MOD_0F2B_PREFIX_0 */
11625     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11626   },
11627   {
11628     /* MOD_0F2B_PREFIX_1 */
11629     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11630   },
11631   {
11632     /* MOD_0F2B_PREFIX_2 */
11633     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11634   },
11635   {
11636     /* MOD_0F2B_PREFIX_3 */
11637     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11638   },
11639   {
11640     /* MOD_0F51 */
11641     { Bad_Opcode },
11642     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11643   },
11644   {
11645     /* MOD_0F71_REG_2 */
11646     { Bad_Opcode },
11647     { "psrlw",          { MS, Ib }, 0 },
11648   },
11649   {
11650     /* MOD_0F71_REG_4 */
11651     { Bad_Opcode },
11652     { "psraw",          { MS, Ib }, 0 },
11653   },
11654   {
11655     /* MOD_0F71_REG_6 */
11656     { Bad_Opcode },
11657     { "psllw",          { MS, Ib }, 0 },
11658   },
11659   {
11660     /* MOD_0F72_REG_2 */
11661     { Bad_Opcode },
11662     { "psrld",          { MS, Ib }, 0 },
11663   },
11664   {
11665     /* MOD_0F72_REG_4 */
11666     { Bad_Opcode },
11667     { "psrad",          { MS, Ib }, 0 },
11668   },
11669   {
11670     /* MOD_0F72_REG_6 */
11671     { Bad_Opcode },
11672     { "pslld",          { MS, Ib }, 0 },
11673   },
11674   {
11675     /* MOD_0F73_REG_2 */
11676     { Bad_Opcode },
11677     { "psrlq",          { MS, Ib }, 0 },
11678   },
11679   {
11680     /* MOD_0F73_REG_3 */
11681     { Bad_Opcode },
11682     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11683   },
11684   {
11685     /* MOD_0F73_REG_6 */
11686     { Bad_Opcode },
11687     { "psllq",          { MS, Ib }, 0 },
11688   },
11689   {
11690     /* MOD_0F73_REG_7 */
11691     { Bad_Opcode },
11692     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11693   },
11694   {
11695     /* MOD_0FAE_REG_0 */
11696     { "fxsave",         { FXSAVE }, 0 },
11697     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11698   },
11699   {
11700     /* MOD_0FAE_REG_1 */
11701     { "fxrstor",        { FXSAVE }, 0 },
11702     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11703   },
11704   {
11705     /* MOD_0FAE_REG_2 */
11706     { "ldmxcsr",        { Md }, 0 },
11707     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11708   },
11709   {
11710     /* MOD_0FAE_REG_3 */
11711     { "stmxcsr",        { Md }, 0 },
11712     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11713   },
11714   {
11715     /* MOD_0FAE_REG_4 */
11716     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11717     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11718   },
11719   {
11720     /* MOD_0FAE_REG_5 */
11721     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11722     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11723   },
11724   {
11725     /* MOD_0FAE_REG_6 */
11726     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11727     { RM_TABLE (RM_0FAE_REG_6) },
11728   },
11729   {
11730     /* MOD_0FAE_REG_7 */
11731     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11732     { RM_TABLE (RM_0FAE_REG_7) },
11733   },
11734   {
11735     /* MOD_0FB2 */
11736     { "lssS",           { Gv, Mp }, 0 },
11737   },
11738   {
11739     /* MOD_0FB4 */
11740     { "lfsS",           { Gv, Mp }, 0 },
11741   },
11742   {
11743     /* MOD_0FB5 */
11744     { "lgsS",           { Gv, Mp }, 0 },
11745   },
11746   {
11747     /* MOD_0FC3 */
11748     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11749   },
11750   {
11751     /* MOD_0FC7_REG_3 */
11752     { "xrstors",        { FXSAVE }, 0 },
11753   },
11754   {
11755     /* MOD_0FC7_REG_4 */
11756     { "xsavec",         { FXSAVE }, 0 },
11757   },
11758   {
11759     /* MOD_0FC7_REG_5 */
11760     { "xsaves",         { FXSAVE }, 0 },
11761   },
11762   {
11763     /* MOD_0FC7_REG_6 */
11764     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11765     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11766   },
11767   {
11768     /* MOD_0FC7_REG_7 */
11769     { "vmptrst",        { Mq }, 0 },
11770     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11771   },
11772   {
11773     /* MOD_0FD7 */
11774     { Bad_Opcode },
11775     { "pmovmskb",       { Gdq, MS }, 0 },
11776   },
11777   {
11778     /* MOD_0FE7_PREFIX_2 */
11779     { "movntdq",        { Mx, XM }, 0 },
11780   },
11781   {
11782     /* MOD_0FF0_PREFIX_3 */
11783     { "lddqu",          { XM, M }, 0 },
11784   },
11785   {
11786     /* MOD_0F382A_PREFIX_2 */
11787     { "movntdqa",       { XM, Mx }, 0 },
11788   },
11789   {
11790     /* MOD_0F38F5_PREFIX_2 */
11791     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11792   },
11793   {
11794     /* MOD_0F38F6_PREFIX_0 */
11795     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11796   },
11797   {
11798     /* MOD_62_32BIT */
11799     { "bound{S|}",      { Gv, Ma }, 0 },
11800     { EVEX_TABLE (EVEX_0F) },
11801   },
11802   {
11803     /* MOD_C4_32BIT */
11804     { "lesS",           { Gv, Mp }, 0 },
11805     { VEX_C4_TABLE (VEX_0F) },
11806   },
11807   {
11808     /* MOD_C5_32BIT */
11809     { "ldsS",           { Gv, Mp }, 0 },
11810     { VEX_C5_TABLE (VEX_0F) },
11811   },
11812   {
11813     /* MOD_VEX_0F12_PREFIX_0 */
11814     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11815     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11816   },
11817   {
11818     /* MOD_VEX_0F13 */
11819     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11820   },
11821   {
11822     /* MOD_VEX_0F16_PREFIX_0 */
11823     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11824     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11825   },
11826   {
11827     /* MOD_VEX_0F17 */
11828     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11829   },
11830   {
11831     /* MOD_VEX_0F2B */
11832     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11833   },
11834   {
11835     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11836     { Bad_Opcode },
11837     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11838   },
11839   {
11840     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11841     { Bad_Opcode },
11842     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11843   },
11844   {
11845     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11846     { Bad_Opcode },
11847     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11848   },
11849   {
11850     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11851     { Bad_Opcode },
11852     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11853   },
11854   {
11855     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11856     { Bad_Opcode },
11857     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11858   },
11859   {
11860     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11861     { Bad_Opcode },
11862     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11863   },
11864   {
11865     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11866     { Bad_Opcode },
11867     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11868   },
11869   {
11870     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11871     { Bad_Opcode },
11872     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11873   },
11874   {
11875     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11876     { Bad_Opcode },
11877     { "knotw",          { MaskG, MaskR }, 0 },
11878   },
11879   {
11880     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11881     { Bad_Opcode },
11882     { "knotq",          { MaskG, MaskR }, 0 },
11883   },
11884   {
11885     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11886     { Bad_Opcode },
11887     { "knotb",          { MaskG, MaskR }, 0 },
11888   },
11889   {
11890     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11891     { Bad_Opcode },
11892     { "knotd",          { MaskG, MaskR }, 0 },
11893   },
11894   {
11895     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11896     { Bad_Opcode },
11897     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11898   },
11899   {
11900     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11901     { Bad_Opcode },
11902     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11903   },
11904   {
11905     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11906     { Bad_Opcode },
11907     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11908   },
11909   {
11910     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11911     { Bad_Opcode },
11912     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11913   },
11914  {
11915     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11916     { Bad_Opcode },
11917     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11918   },
11919   {
11920     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11921     { Bad_Opcode },
11922     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11923   },
11924   {
11925     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11926     { Bad_Opcode },
11927     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11928   },
11929   {
11930     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11931     { Bad_Opcode },
11932     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11933   },
11934   {
11935     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11936     { Bad_Opcode },
11937     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11938   },
11939   {
11940     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11941     { Bad_Opcode },
11942     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11943   },
11944   {
11945     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11946     { Bad_Opcode },
11947     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11948   },
11949   {
11950     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11951     { Bad_Opcode },
11952     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11953   },
11954   {
11955     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11956     { Bad_Opcode },
11957     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11958   },
11959   {
11960     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11961     { Bad_Opcode },
11962     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11963   },
11964   {
11965     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11966     { Bad_Opcode },
11967     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11968   },
11969   {
11970     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11971     { Bad_Opcode },
11972     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11973   },
11974   {
11975     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11976     { Bad_Opcode },
11977     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11978   },
11979   {
11980     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11981     { Bad_Opcode },
11982     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11983   },
11984   {
11985     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11986     { Bad_Opcode },
11987     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11988   },
11989   {
11990     /* MOD_VEX_0F50 */
11991     { Bad_Opcode },
11992     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11993   },
11994   {
11995     /* MOD_VEX_0F71_REG_2 */
11996     { Bad_Opcode },
11997     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11998   },
11999   {
12000     /* MOD_VEX_0F71_REG_4 */
12001     { Bad_Opcode },
12002     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12003   },
12004   {
12005     /* MOD_VEX_0F71_REG_6 */
12006     { Bad_Opcode },
12007     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12008   },
12009   {
12010     /* MOD_VEX_0F72_REG_2 */
12011     { Bad_Opcode },
12012     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12013   },
12014   {
12015     /* MOD_VEX_0F72_REG_4 */
12016     { Bad_Opcode },
12017     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12018   },
12019   {
12020     /* MOD_VEX_0F72_REG_6 */
12021     { Bad_Opcode },
12022     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12023   },
12024   {
12025     /* MOD_VEX_0F73_REG_2 */
12026     { Bad_Opcode },
12027     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12028   },
12029   {
12030     /* MOD_VEX_0F73_REG_3 */
12031     { Bad_Opcode },
12032     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12033   },
12034   {
12035     /* MOD_VEX_0F73_REG_6 */
12036     { Bad_Opcode },
12037     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12038   },
12039   {
12040     /* MOD_VEX_0F73_REG_7 */
12041     { Bad_Opcode },
12042     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12043   },
12044   {
12045     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12046     { "kmovw",          { Ew, MaskG }, 0 },
12047     { Bad_Opcode },
12048   },
12049   {
12050     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12051     { "kmovq",          { Eq, MaskG }, 0 },
12052     { Bad_Opcode },
12053   },
12054   {
12055     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12056     { "kmovb",          { Eb, MaskG }, 0 },
12057     { Bad_Opcode },
12058   },
12059   {
12060     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12061     { "kmovd",          { Ed, MaskG }, 0 },
12062     { Bad_Opcode },
12063   },
12064   {
12065     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12066     { Bad_Opcode },
12067     { "kmovw",          { MaskG, Rdq }, 0 },
12068   },
12069   {
12070     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12071     { Bad_Opcode },
12072     { "kmovb",          { MaskG, Rdq }, 0 },
12073   },
12074   {
12075     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12076     { Bad_Opcode },
12077     { "kmovd",          { MaskG, Rdq }, 0 },
12078   },
12079   {
12080     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12081     { Bad_Opcode },
12082     { "kmovq",          { MaskG, Rdq }, 0 },
12083   },
12084   {
12085     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12086     { Bad_Opcode },
12087     { "kmovw",          { Gdq, MaskR }, 0 },
12088   },
12089   {
12090     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12091     { Bad_Opcode },
12092     { "kmovb",          { Gdq, MaskR }, 0 },
12093   },
12094   {
12095     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12096     { Bad_Opcode },
12097     { "kmovd",          { Gdq, MaskR }, 0 },
12098   },
12099   {
12100     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12101     { Bad_Opcode },
12102     { "kmovq",          { Gdq, MaskR }, 0 },
12103   },
12104   {
12105     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12106     { Bad_Opcode },
12107     { "kortestw", { MaskG, MaskR }, 0 },
12108   },
12109   {
12110     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12111     { Bad_Opcode },
12112     { "kortestq", { MaskG, MaskR }, 0 },
12113   },
12114   {
12115     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12116     { Bad_Opcode },
12117     { "kortestb", { MaskG, MaskR }, 0 },
12118   },
12119   {
12120     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12121     { Bad_Opcode },
12122     { "kortestd", { MaskG, MaskR }, 0 },
12123   },
12124   {
12125     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12126     { Bad_Opcode },
12127     { "ktestw", { MaskG, MaskR }, 0 },
12128   },
12129   {
12130     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12131     { Bad_Opcode },
12132     { "ktestq", { MaskG, MaskR }, 0 },
12133   },
12134   {
12135     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12136     { Bad_Opcode },
12137     { "ktestb", { MaskG, MaskR }, 0 },
12138   },
12139   {
12140     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12141     { Bad_Opcode },
12142     { "ktestd", { MaskG, MaskR }, 0 },
12143   },
12144   {
12145     /* MOD_VEX_0FAE_REG_2 */
12146     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12147   },
12148   {
12149     /* MOD_VEX_0FAE_REG_3 */
12150     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12151   },
12152   {
12153     /* MOD_VEX_0FD7_PREFIX_2 */
12154     { Bad_Opcode },
12155     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12156   },
12157   {
12158     /* MOD_VEX_0FE7_PREFIX_2 */
12159     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12160   },
12161   {
12162     /* MOD_VEX_0FF0_PREFIX_3 */
12163     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12164   },
12165   {
12166     /* MOD_VEX_0F381A_PREFIX_2 */
12167     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12168   },
12169   {
12170     /* MOD_VEX_0F382A_PREFIX_2 */
12171     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12172   },
12173   {
12174     /* MOD_VEX_0F382C_PREFIX_2 */
12175     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12176   },
12177   {
12178     /* MOD_VEX_0F382D_PREFIX_2 */
12179     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12180   },
12181   {
12182     /* MOD_VEX_0F382E_PREFIX_2 */
12183     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12184   },
12185   {
12186     /* MOD_VEX_0F382F_PREFIX_2 */
12187     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12188   },
12189   {
12190     /* MOD_VEX_0F385A_PREFIX_2 */
12191     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12192   },
12193   {
12194     /* MOD_VEX_0F388C_PREFIX_2 */
12195     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12196   },
12197   {
12198     /* MOD_VEX_0F388E_PREFIX_2 */
12199     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12200   },
12201   {
12202     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12203     { Bad_Opcode },
12204     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12205   },
12206   {
12207     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12208     { Bad_Opcode },
12209     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12210   },
12211   {
12212     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12213     { Bad_Opcode },
12214     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12215   },
12216   {
12217     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12218     { Bad_Opcode },
12219     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12220   },
12221   {
12222     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12223     { Bad_Opcode },
12224     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12225   },
12226   {
12227     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12228     { Bad_Opcode },
12229     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12230   },
12231   {
12232     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12233     { Bad_Opcode },
12234     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12235   },
12236   {
12237     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12238     { Bad_Opcode },
12239     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12240   },
12241 #define NEED_MOD_TABLE
12242 #include "i386-dis-evex.h"
12243 #undef NEED_MOD_TABLE
12244 };
12245
12246 static const struct dis386 rm_table[][8] = {
12247   {
12248     /* RM_C6_REG_7 */
12249     { "xabort",         { Skip_MODRM, Ib }, 0 },
12250   },
12251   {
12252     /* RM_C7_REG_7 */
12253     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12254   },
12255   {
12256     /* RM_0F01_REG_0 */
12257     { Bad_Opcode },
12258     { "vmcall",         { Skip_MODRM }, 0 },
12259     { "vmlaunch",       { Skip_MODRM }, 0 },
12260     { "vmresume",       { Skip_MODRM }, 0 },
12261     { "vmxoff",         { Skip_MODRM }, 0 },
12262   },
12263   {
12264     /* RM_0F01_REG_1 */
12265     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12266     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12267     { "clac",           { Skip_MODRM }, 0 },
12268     { "stac",           { Skip_MODRM }, 0 },
12269     { Bad_Opcode },
12270     { Bad_Opcode },
12271     { Bad_Opcode },
12272     { "encls",          { Skip_MODRM }, 0 },
12273   },
12274   {
12275     /* RM_0F01_REG_2 */
12276     { "xgetbv",         { Skip_MODRM }, 0 },
12277     { "xsetbv",         { Skip_MODRM }, 0 },
12278     { Bad_Opcode },
12279     { Bad_Opcode },
12280     { "vmfunc",         { Skip_MODRM }, 0 },
12281     { "xend",           { Skip_MODRM }, 0 },
12282     { "xtest",          { Skip_MODRM }, 0 },
12283     { "enclu",          { Skip_MODRM }, 0 },
12284   },
12285   {
12286     /* RM_0F01_REG_3 */
12287     { "vmrun",          { Skip_MODRM }, 0 },
12288     { "vmmcall",        { Skip_MODRM }, 0 },
12289     { "vmload",         { Skip_MODRM }, 0 },
12290     { "vmsave",         { Skip_MODRM }, 0 },
12291     { "stgi",           { Skip_MODRM }, 0 },
12292     { "clgi",           { Skip_MODRM }, 0 },
12293     { "skinit",         { Skip_MODRM }, 0 },
12294     { "invlpga",        { Skip_MODRM }, 0 },
12295   },
12296   {
12297     /* RM_0F01_REG_5 */
12298     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12299     { Bad_Opcode },
12300     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12301     { Bad_Opcode },
12302     { Bad_Opcode },
12303     { Bad_Opcode },
12304     { "rdpkru",         { Skip_MODRM }, 0 },
12305     { "wrpkru",         { Skip_MODRM }, 0 },
12306   },
12307   {
12308     /* RM_0F01_REG_7 */
12309     { "swapgs",         { Skip_MODRM }, 0  },
12310     { "rdtscp",         { Skip_MODRM }, 0  },
12311     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12312     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12313     { "clzero",         { Skip_MODRM }, 0  },
12314   },
12315   {
12316     /* RM_0F1E_MOD_3_REG_7 */
12317     { "nopQ",           { Ev }, 0 },
12318     { "nopQ",           { Ev }, 0 },
12319     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
12320     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
12321     { "nopQ",           { Ev }, 0 },
12322     { "nopQ",           { Ev }, 0 },
12323     { "nopQ",           { Ev }, 0 },
12324     { "nopQ",           { Ev }, 0 },
12325   },
12326   {
12327     /* RM_0FAE_REG_6 */
12328     { "mfence",         { Skip_MODRM }, 0 },
12329   },
12330   {
12331     /* RM_0FAE_REG_7 */
12332     { "sfence",         { Skip_MODRM }, 0 },
12333
12334   },
12335 };
12336
12337 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12338
12339 /* We use the high bit to indicate different name for the same
12340    prefix.  */
12341 #define REP_PREFIX      (0xf3 | 0x100)
12342 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12343 #define XRELEASE_PREFIX (0xf3 | 0x400)
12344 #define BND_PREFIX      (0xf2 | 0x400)
12345 #define NOTRACK_PREFIX  (0x3e | 0x100)
12346
12347 static int
12348 ckprefix (void)
12349 {
12350   int newrex, i, length;
12351   rex = 0;
12352   rex_ignored = 0;
12353   prefixes = 0;
12354   used_prefixes = 0;
12355   rex_used = 0;
12356   last_lock_prefix = -1;
12357   last_repz_prefix = -1;
12358   last_repnz_prefix = -1;
12359   last_data_prefix = -1;
12360   last_addr_prefix = -1;
12361   last_rex_prefix = -1;
12362   last_seg_prefix = -1;
12363   fwait_prefix = -1;
12364   active_seg_prefix = 0;
12365   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12366     all_prefixes[i] = 0;
12367   i = 0;
12368   length = 0;
12369   /* The maximum instruction length is 15bytes.  */
12370   while (length < MAX_CODE_LENGTH - 1)
12371     {
12372       FETCH_DATA (the_info, codep + 1);
12373       newrex = 0;
12374       switch (*codep)
12375         {
12376         /* REX prefixes family.  */
12377         case 0x40:
12378         case 0x41:
12379         case 0x42:
12380         case 0x43:
12381         case 0x44:
12382         case 0x45:
12383         case 0x46:
12384         case 0x47:
12385         case 0x48:
12386         case 0x49:
12387         case 0x4a:
12388         case 0x4b:
12389         case 0x4c:
12390         case 0x4d:
12391         case 0x4e:
12392         case 0x4f:
12393           if (address_mode == mode_64bit)
12394             newrex = *codep;
12395           else
12396             return 1;
12397           last_rex_prefix = i;
12398           break;
12399         case 0xf3:
12400           prefixes |= PREFIX_REPZ;
12401           last_repz_prefix = i;
12402           break;
12403         case 0xf2:
12404           prefixes |= PREFIX_REPNZ;
12405           last_repnz_prefix = i;
12406           break;
12407         case 0xf0:
12408           prefixes |= PREFIX_LOCK;
12409           last_lock_prefix = i;
12410           break;
12411         case 0x2e:
12412           prefixes |= PREFIX_CS;
12413           last_seg_prefix = i;
12414           active_seg_prefix = PREFIX_CS;
12415           break;
12416         case 0x36:
12417           prefixes |= PREFIX_SS;
12418           last_seg_prefix = i;
12419           active_seg_prefix = PREFIX_SS;
12420           break;
12421         case 0x3e:
12422           prefixes |= PREFIX_DS;
12423           last_seg_prefix = i;
12424           active_seg_prefix = PREFIX_DS;
12425           break;
12426         case 0x26:
12427           prefixes |= PREFIX_ES;
12428           last_seg_prefix = i;
12429           active_seg_prefix = PREFIX_ES;
12430           break;
12431         case 0x64:
12432           prefixes |= PREFIX_FS;
12433           last_seg_prefix = i;
12434           active_seg_prefix = PREFIX_FS;
12435           break;
12436         case 0x65:
12437           prefixes |= PREFIX_GS;
12438           last_seg_prefix = i;
12439           active_seg_prefix = PREFIX_GS;
12440           break;
12441         case 0x66:
12442           prefixes |= PREFIX_DATA;
12443           last_data_prefix = i;
12444           break;
12445         case 0x67:
12446           prefixes |= PREFIX_ADDR;
12447           last_addr_prefix = i;
12448           break;
12449         case FWAIT_OPCODE:
12450           /* fwait is really an instruction.  If there are prefixes
12451              before the fwait, they belong to the fwait, *not* to the
12452              following instruction.  */
12453           fwait_prefix = i;
12454           if (prefixes || rex)
12455             {
12456               prefixes |= PREFIX_FWAIT;
12457               codep++;
12458               /* This ensures that the previous REX prefixes are noticed
12459                  as unused prefixes, as in the return case below.  */
12460               rex_used = rex;
12461               return 1;
12462             }
12463           prefixes = PREFIX_FWAIT;
12464           break;
12465         default:
12466           return 1;
12467         }
12468       /* Rex is ignored when followed by another prefix.  */
12469       if (rex)
12470         {
12471           rex_used = rex;
12472           return 1;
12473         }
12474       if (*codep != FWAIT_OPCODE)
12475         all_prefixes[i++] = *codep;
12476       rex = newrex;
12477       codep++;
12478       length++;
12479     }
12480   return 0;
12481 }
12482
12483 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12484    prefix byte.  */
12485
12486 static const char *
12487 prefix_name (int pref, int sizeflag)
12488 {
12489   static const char *rexes [16] =
12490     {
12491       "rex",            /* 0x40 */
12492       "rex.B",          /* 0x41 */
12493       "rex.X",          /* 0x42 */
12494       "rex.XB",         /* 0x43 */
12495       "rex.R",          /* 0x44 */
12496       "rex.RB",         /* 0x45 */
12497       "rex.RX",         /* 0x46 */
12498       "rex.RXB",        /* 0x47 */
12499       "rex.W",          /* 0x48 */
12500       "rex.WB",         /* 0x49 */
12501       "rex.WX",         /* 0x4a */
12502       "rex.WXB",        /* 0x4b */
12503       "rex.WR",         /* 0x4c */
12504       "rex.WRB",        /* 0x4d */
12505       "rex.WRX",        /* 0x4e */
12506       "rex.WRXB",       /* 0x4f */
12507     };
12508
12509   switch (pref)
12510     {
12511     /* REX prefixes family.  */
12512     case 0x40:
12513     case 0x41:
12514     case 0x42:
12515     case 0x43:
12516     case 0x44:
12517     case 0x45:
12518     case 0x46:
12519     case 0x47:
12520     case 0x48:
12521     case 0x49:
12522     case 0x4a:
12523     case 0x4b:
12524     case 0x4c:
12525     case 0x4d:
12526     case 0x4e:
12527     case 0x4f:
12528       return rexes [pref - 0x40];
12529     case 0xf3:
12530       return "repz";
12531     case 0xf2:
12532       return "repnz";
12533     case 0xf0:
12534       return "lock";
12535     case 0x2e:
12536       return "cs";
12537     case 0x36:
12538       return "ss";
12539     case 0x3e:
12540       return "ds";
12541     case 0x26:
12542       return "es";
12543     case 0x64:
12544       return "fs";
12545     case 0x65:
12546       return "gs";
12547     case 0x66:
12548       return (sizeflag & DFLAG) ? "data16" : "data32";
12549     case 0x67:
12550       if (address_mode == mode_64bit)
12551         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12552       else
12553         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12554     case FWAIT_OPCODE:
12555       return "fwait";
12556     case REP_PREFIX:
12557       return "rep";
12558     case XACQUIRE_PREFIX:
12559       return "xacquire";
12560     case XRELEASE_PREFIX:
12561       return "xrelease";
12562     case BND_PREFIX:
12563       return "bnd";
12564     case NOTRACK_PREFIX:
12565       return "notrack";
12566     default:
12567       return NULL;
12568     }
12569 }
12570
12571 static char op_out[MAX_OPERANDS][100];
12572 static int op_ad, op_index[MAX_OPERANDS];
12573 static int two_source_ops;
12574 static bfd_vma op_address[MAX_OPERANDS];
12575 static bfd_vma op_riprel[MAX_OPERANDS];
12576 static bfd_vma start_pc;
12577
12578 /*
12579  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12580  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12581  *   section of the "Virtual 8086 Mode" chapter.)
12582  * 'pc' should be the address of this instruction, it will
12583  *   be used to print the target address if this is a relative jump or call
12584  * The function returns the length of this instruction in bytes.
12585  */
12586
12587 static char intel_syntax;
12588 static char intel_mnemonic = !SYSV386_COMPAT;
12589 static char open_char;
12590 static char close_char;
12591 static char separator_char;
12592 static char scale_char;
12593
12594 enum x86_64_isa
12595 {
12596   amd64 = 0,
12597   intel64
12598 };
12599
12600 static enum x86_64_isa isa64;
12601
12602 /* Here for backwards compatibility.  When gdb stops using
12603    print_insn_i386_att and print_insn_i386_intel these functions can
12604    disappear, and print_insn_i386 be merged into print_insn.  */
12605 int
12606 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12607 {
12608   intel_syntax = 0;
12609
12610   return print_insn (pc, info);
12611 }
12612
12613 int
12614 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12615 {
12616   intel_syntax = 1;
12617
12618   return print_insn (pc, info);
12619 }
12620
12621 int
12622 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12623 {
12624   intel_syntax = -1;
12625
12626   return print_insn (pc, info);
12627 }
12628
12629 void
12630 print_i386_disassembler_options (FILE *stream)
12631 {
12632   fprintf (stream, _("\n\
12633 The following i386/x86-64 specific disassembler options are supported for use\n\
12634 with the -M switch (multiple options should be separated by commas):\n"));
12635
12636   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12637   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12638   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12639   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12640   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12641   fprintf (stream, _("  att-mnemonic\n"
12642                      "              Display instruction in AT&T mnemonic\n"));
12643   fprintf (stream, _("  intel-mnemonic\n"
12644                      "              Display instruction in Intel mnemonic\n"));
12645   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12646   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12647   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12648   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12649   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12650   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12651   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12652   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12653 }
12654
12655 /* Bad opcode.  */
12656 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12657
12658 /* Get a pointer to struct dis386 with a valid name.  */
12659
12660 static const struct dis386 *
12661 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12662 {
12663   int vindex, vex_table_index;
12664
12665   if (dp->name != NULL)
12666     return dp;
12667
12668   switch (dp->op[0].bytemode)
12669     {
12670     case USE_REG_TABLE:
12671       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12672       break;
12673
12674     case USE_MOD_TABLE:
12675       vindex = modrm.mod == 0x3 ? 1 : 0;
12676       dp = &mod_table[dp->op[1].bytemode][vindex];
12677       break;
12678
12679     case USE_RM_TABLE:
12680       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12681       break;
12682
12683     case USE_PREFIX_TABLE:
12684       if (need_vex)
12685         {
12686           /* The prefix in VEX is implicit.  */
12687           switch (vex.prefix)
12688             {
12689             case 0:
12690               vindex = 0;
12691               break;
12692             case REPE_PREFIX_OPCODE:
12693               vindex = 1;
12694               break;
12695             case DATA_PREFIX_OPCODE:
12696               vindex = 2;
12697               break;
12698             case REPNE_PREFIX_OPCODE:
12699               vindex = 3;
12700               break;
12701             default:
12702               abort ();
12703               break;
12704             }
12705         }
12706       else
12707         {
12708           int last_prefix = -1;
12709           int prefix = 0;
12710           vindex = 0;
12711           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12712              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12713              last one wins.  */
12714           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12715             {
12716               if (last_repz_prefix > last_repnz_prefix)
12717                 {
12718                   vindex = 1;
12719                   prefix = PREFIX_REPZ;
12720                   last_prefix = last_repz_prefix;
12721                 }
12722               else
12723                 {
12724                   vindex = 3;
12725                   prefix = PREFIX_REPNZ;
12726                   last_prefix = last_repnz_prefix;
12727                 }
12728
12729               /* Check if prefix should be ignored.  */
12730               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12731                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12732                    & prefix) != 0)
12733                 vindex = 0;
12734             }
12735
12736           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12737             {
12738               vindex = 2;
12739               prefix = PREFIX_DATA;
12740               last_prefix = last_data_prefix;
12741             }
12742
12743           if (vindex != 0)
12744             {
12745               used_prefixes |= prefix;
12746               all_prefixes[last_prefix] = 0;
12747             }
12748         }
12749       dp = &prefix_table[dp->op[1].bytemode][vindex];
12750       break;
12751
12752     case USE_X86_64_TABLE:
12753       vindex = address_mode == mode_64bit ? 1 : 0;
12754       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12755       break;
12756
12757     case USE_3BYTE_TABLE:
12758       FETCH_DATA (info, codep + 2);
12759       vindex = *codep++;
12760       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12761       end_codep = codep;
12762       modrm.mod = (*codep >> 6) & 3;
12763       modrm.reg = (*codep >> 3) & 7;
12764       modrm.rm = *codep & 7;
12765       break;
12766
12767     case USE_VEX_LEN_TABLE:
12768       if (!need_vex)
12769         abort ();
12770
12771       switch (vex.length)
12772         {
12773         case 128:
12774           vindex = 0;
12775           break;
12776         case 256:
12777           vindex = 1;
12778           break;
12779         default:
12780           abort ();
12781           break;
12782         }
12783
12784       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12785       break;
12786
12787     case USE_XOP_8F_TABLE:
12788       FETCH_DATA (info, codep + 3);
12789       /* All bits in the REX prefix are ignored.  */
12790       rex_ignored = rex;
12791       rex = ~(*codep >> 5) & 0x7;
12792
12793       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12794       switch ((*codep & 0x1f))
12795         {
12796         default:
12797           dp = &bad_opcode;
12798           return dp;
12799         case 0x8:
12800           vex_table_index = XOP_08;
12801           break;
12802         case 0x9:
12803           vex_table_index = XOP_09;
12804           break;
12805         case 0xa:
12806           vex_table_index = XOP_0A;
12807           break;
12808         }
12809       codep++;
12810       vex.w = *codep & 0x80;
12811       if (vex.w && address_mode == mode_64bit)
12812         rex |= REX_W;
12813
12814       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12815       if (address_mode != mode_64bit)
12816         {
12817           /* In 16/32-bit mode REX_B is silently ignored.  */
12818           rex &= ~REX_B;
12819         }
12820
12821       vex.length = (*codep & 0x4) ? 256 : 128;
12822       switch ((*codep & 0x3))
12823         {
12824         case 0:
12825           vex.prefix = 0;
12826           break;
12827         case 1:
12828           vex.prefix = DATA_PREFIX_OPCODE;
12829           break;
12830         case 2:
12831           vex.prefix = REPE_PREFIX_OPCODE;
12832           break;
12833         case 3:
12834           vex.prefix = REPNE_PREFIX_OPCODE;
12835           break;
12836         }
12837       need_vex = 1;
12838       need_vex_reg = 1;
12839       codep++;
12840       vindex = *codep++;
12841       dp = &xop_table[vex_table_index][vindex];
12842
12843       end_codep = codep;
12844       FETCH_DATA (info, codep + 1);
12845       modrm.mod = (*codep >> 6) & 3;
12846       modrm.reg = (*codep >> 3) & 7;
12847       modrm.rm = *codep & 7;
12848       break;
12849
12850     case USE_VEX_C4_TABLE:
12851       /* VEX prefix.  */
12852       FETCH_DATA (info, codep + 3);
12853       /* All bits in the REX prefix are ignored.  */
12854       rex_ignored = rex;
12855       rex = ~(*codep >> 5) & 0x7;
12856       switch ((*codep & 0x1f))
12857         {
12858         default:
12859           dp = &bad_opcode;
12860           return dp;
12861         case 0x1:
12862           vex_table_index = VEX_0F;
12863           break;
12864         case 0x2:
12865           vex_table_index = VEX_0F38;
12866           break;
12867         case 0x3:
12868           vex_table_index = VEX_0F3A;
12869           break;
12870         }
12871       codep++;
12872       vex.w = *codep & 0x80;
12873       if (address_mode == mode_64bit)
12874         {
12875           if (vex.w)
12876             rex |= REX_W;
12877         }
12878       else
12879         {
12880           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12881              is ignored, other REX bits are 0 and the highest bit in
12882              VEX.vvvv is also ignored (but we mustn't clear it here).  */
12883           rex = 0;
12884         }
12885       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12886       vex.length = (*codep & 0x4) ? 256 : 128;
12887       switch ((*codep & 0x3))
12888         {
12889         case 0:
12890           vex.prefix = 0;
12891           break;
12892         case 1:
12893           vex.prefix = DATA_PREFIX_OPCODE;
12894           break;
12895         case 2:
12896           vex.prefix = REPE_PREFIX_OPCODE;
12897           break;
12898         case 3:
12899           vex.prefix = REPNE_PREFIX_OPCODE;
12900           break;
12901         }
12902       need_vex = 1;
12903       need_vex_reg = 1;
12904       codep++;
12905       vindex = *codep++;
12906       dp = &vex_table[vex_table_index][vindex];
12907       end_codep = codep;
12908       /* There is no MODRM byte for VEX0F 77.  */
12909       if (vex_table_index != VEX_0F || vindex != 0x77)
12910         {
12911           FETCH_DATA (info, codep + 1);
12912           modrm.mod = (*codep >> 6) & 3;
12913           modrm.reg = (*codep >> 3) & 7;
12914           modrm.rm = *codep & 7;
12915         }
12916       break;
12917
12918     case USE_VEX_C5_TABLE:
12919       /* VEX prefix.  */
12920       FETCH_DATA (info, codep + 2);
12921       /* All bits in the REX prefix are ignored.  */
12922       rex_ignored = rex;
12923       rex = (*codep & 0x80) ? 0 : REX_R;
12924
12925       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12926          VEX.vvvv is 1.  */
12927       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12928       vex.w = 0;
12929       vex.length = (*codep & 0x4) ? 256 : 128;
12930       switch ((*codep & 0x3))
12931         {
12932         case 0:
12933           vex.prefix = 0;
12934           break;
12935         case 1:
12936           vex.prefix = DATA_PREFIX_OPCODE;
12937           break;
12938         case 2:
12939           vex.prefix = REPE_PREFIX_OPCODE;
12940           break;
12941         case 3:
12942           vex.prefix = REPNE_PREFIX_OPCODE;
12943           break;
12944         }
12945       need_vex = 1;
12946       need_vex_reg = 1;
12947       codep++;
12948       vindex = *codep++;
12949       dp = &vex_table[dp->op[1].bytemode][vindex];
12950       end_codep = codep;
12951       /* There is no MODRM byte for VEX 77.  */
12952       if (vindex != 0x77)
12953         {
12954           FETCH_DATA (info, codep + 1);
12955           modrm.mod = (*codep >> 6) & 3;
12956           modrm.reg = (*codep >> 3) & 7;
12957           modrm.rm = *codep & 7;
12958         }
12959       break;
12960
12961     case USE_VEX_W_TABLE:
12962       if (!need_vex)
12963         abort ();
12964
12965       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12966       break;
12967
12968     case USE_EVEX_TABLE:
12969       two_source_ops = 0;
12970       /* EVEX prefix.  */
12971       vex.evex = 1;
12972       FETCH_DATA (info, codep + 4);
12973       /* All bits in the REX prefix are ignored.  */
12974       rex_ignored = rex;
12975       /* The first byte after 0x62.  */
12976       rex = ~(*codep >> 5) & 0x7;
12977       vex.r = *codep & 0x10;
12978       switch ((*codep & 0xf))
12979         {
12980         default:
12981           return &bad_opcode;
12982         case 0x1:
12983           vex_table_index = EVEX_0F;
12984           break;
12985         case 0x2:
12986           vex_table_index = EVEX_0F38;
12987           break;
12988         case 0x3:
12989           vex_table_index = EVEX_0F3A;
12990           break;
12991         }
12992
12993       /* The second byte after 0x62.  */
12994       codep++;
12995       vex.w = *codep & 0x80;
12996       if (vex.w && address_mode == mode_64bit)
12997         rex |= REX_W;
12998
12999       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13000
13001       /* The U bit.  */
13002       if (!(*codep & 0x4))
13003         return &bad_opcode;
13004
13005       switch ((*codep & 0x3))
13006         {
13007         case 0:
13008           vex.prefix = 0;
13009           break;
13010         case 1:
13011           vex.prefix = DATA_PREFIX_OPCODE;
13012           break;
13013         case 2:
13014           vex.prefix = REPE_PREFIX_OPCODE;
13015           break;
13016         case 3:
13017           vex.prefix = REPNE_PREFIX_OPCODE;
13018           break;
13019         }
13020
13021       /* The third byte after 0x62.  */
13022       codep++;
13023
13024       /* Remember the static rounding bits.  */
13025       vex.ll = (*codep >> 5) & 3;
13026       vex.b = (*codep & 0x10) != 0;
13027
13028       vex.v = *codep & 0x8;
13029       vex.mask_register_specifier = *codep & 0x7;
13030       vex.zeroing = *codep & 0x80;
13031
13032       if (address_mode != mode_64bit)
13033         {
13034           /* In 16/32-bit mode silently ignore following bits.  */
13035           rex &= ~REX_B;
13036           vex.r = 1;
13037           vex.v = 1;
13038         }
13039
13040       need_vex = 1;
13041       need_vex_reg = 1;
13042       codep++;
13043       vindex = *codep++;
13044       dp = &evex_table[vex_table_index][vindex];
13045       end_codep = codep;
13046       FETCH_DATA (info, codep + 1);
13047       modrm.mod = (*codep >> 6) & 3;
13048       modrm.reg = (*codep >> 3) & 7;
13049       modrm.rm = *codep & 7;
13050
13051       /* Set vector length.  */
13052       if (modrm.mod == 3 && vex.b)
13053         vex.length = 512;
13054       else
13055         {
13056           switch (vex.ll)
13057             {
13058             case 0x0:
13059               vex.length = 128;
13060               break;
13061             case 0x1:
13062               vex.length = 256;
13063               break;
13064             case 0x2:
13065               vex.length = 512;
13066               break;
13067             default:
13068               return &bad_opcode;
13069             }
13070         }
13071       break;
13072
13073     case 0:
13074       dp = &bad_opcode;
13075       break;
13076
13077     default:
13078       abort ();
13079     }
13080
13081   if (dp->name != NULL)
13082     return dp;
13083   else
13084     return get_valid_dis386 (dp, info);
13085 }
13086
13087 static void
13088 get_sib (disassemble_info *info, int sizeflag)
13089 {
13090   /* If modrm.mod == 3, operand must be register.  */
13091   if (need_modrm
13092       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13093       && modrm.mod != 3
13094       && modrm.rm == 4)
13095     {
13096       FETCH_DATA (info, codep + 2);
13097       sib.index = (codep [1] >> 3) & 7;
13098       sib.scale = (codep [1] >> 6) & 3;
13099       sib.base = codep [1] & 7;
13100     }
13101 }
13102
13103 static int
13104 print_insn (bfd_vma pc, disassemble_info *info)
13105 {
13106   const struct dis386 *dp;
13107   int i;
13108   char *op_txt[MAX_OPERANDS];
13109   int needcomma;
13110   int sizeflag, orig_sizeflag;
13111   const char *p;
13112   struct dis_private priv;
13113   int prefix_length;
13114
13115   priv.orig_sizeflag = AFLAG | DFLAG;
13116   if ((info->mach & bfd_mach_i386_i386) != 0)
13117     address_mode = mode_32bit;
13118   else if (info->mach == bfd_mach_i386_i8086)
13119     {
13120       address_mode = mode_16bit;
13121       priv.orig_sizeflag = 0;
13122     }
13123   else
13124     address_mode = mode_64bit;
13125
13126   if (intel_syntax == (char) -1)
13127     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13128
13129   for (p = info->disassembler_options; p != NULL; )
13130     {
13131       if (CONST_STRNEQ (p, "amd64"))
13132         isa64 = amd64;
13133       else if (CONST_STRNEQ (p, "intel64"))
13134         isa64 = intel64;
13135       else if (CONST_STRNEQ (p, "x86-64"))
13136         {
13137           address_mode = mode_64bit;
13138           priv.orig_sizeflag = AFLAG | DFLAG;
13139         }
13140       else if (CONST_STRNEQ (p, "i386"))
13141         {
13142           address_mode = mode_32bit;
13143           priv.orig_sizeflag = AFLAG | DFLAG;
13144         }
13145       else if (CONST_STRNEQ (p, "i8086"))
13146         {
13147           address_mode = mode_16bit;
13148           priv.orig_sizeflag = 0;
13149         }
13150       else if (CONST_STRNEQ (p, "intel"))
13151         {
13152           intel_syntax = 1;
13153           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13154             intel_mnemonic = 1;
13155         }
13156       else if (CONST_STRNEQ (p, "att"))
13157         {
13158           intel_syntax = 0;
13159           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13160             intel_mnemonic = 0;
13161         }
13162       else if (CONST_STRNEQ (p, "addr"))
13163         {
13164           if (address_mode == mode_64bit)
13165             {
13166               if (p[4] == '3' && p[5] == '2')
13167                 priv.orig_sizeflag &= ~AFLAG;
13168               else if (p[4] == '6' && p[5] == '4')
13169                 priv.orig_sizeflag |= AFLAG;
13170             }
13171           else
13172             {
13173               if (p[4] == '1' && p[5] == '6')
13174                 priv.orig_sizeflag &= ~AFLAG;
13175               else if (p[4] == '3' && p[5] == '2')
13176                 priv.orig_sizeflag |= AFLAG;
13177             }
13178         }
13179       else if (CONST_STRNEQ (p, "data"))
13180         {
13181           if (p[4] == '1' && p[5] == '6')
13182             priv.orig_sizeflag &= ~DFLAG;
13183           else if (p[4] == '3' && p[5] == '2')
13184             priv.orig_sizeflag |= DFLAG;
13185         }
13186       else if (CONST_STRNEQ (p, "suffix"))
13187         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13188
13189       p = strchr (p, ',');
13190       if (p != NULL)
13191         p++;
13192     }
13193
13194   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13195     {
13196       (*info->fprintf_func) (info->stream,
13197                              _("64-bit address is disabled"));
13198       return -1;
13199     }
13200
13201   if (intel_syntax)
13202     {
13203       names64 = intel_names64;
13204       names32 = intel_names32;
13205       names16 = intel_names16;
13206       names8 = intel_names8;
13207       names8rex = intel_names8rex;
13208       names_seg = intel_names_seg;
13209       names_mm = intel_names_mm;
13210       names_bnd = intel_names_bnd;
13211       names_xmm = intel_names_xmm;
13212       names_ymm = intel_names_ymm;
13213       names_zmm = intel_names_zmm;
13214       index64 = intel_index64;
13215       index32 = intel_index32;
13216       names_mask = intel_names_mask;
13217       index16 = intel_index16;
13218       open_char = '[';
13219       close_char = ']';
13220       separator_char = '+';
13221       scale_char = '*';
13222     }
13223   else
13224     {
13225       names64 = att_names64;
13226       names32 = att_names32;
13227       names16 = att_names16;
13228       names8 = att_names8;
13229       names8rex = att_names8rex;
13230       names_seg = att_names_seg;
13231       names_mm = att_names_mm;
13232       names_bnd = att_names_bnd;
13233       names_xmm = att_names_xmm;
13234       names_ymm = att_names_ymm;
13235       names_zmm = att_names_zmm;
13236       index64 = att_index64;
13237       index32 = att_index32;
13238       names_mask = att_names_mask;
13239       index16 = att_index16;
13240       open_char = '(';
13241       close_char =  ')';
13242       separator_char = ',';
13243       scale_char = ',';
13244     }
13245
13246   /* The output looks better if we put 7 bytes on a line, since that
13247      puts most long word instructions on a single line.  Use 8 bytes
13248      for Intel L1OM.  */
13249   if ((info->mach & bfd_mach_l1om) != 0)
13250     info->bytes_per_line = 8;
13251   else
13252     info->bytes_per_line = 7;
13253
13254   info->private_data = &priv;
13255   priv.max_fetched = priv.the_buffer;
13256   priv.insn_start = pc;
13257
13258   obuf[0] = 0;
13259   for (i = 0; i < MAX_OPERANDS; ++i)
13260     {
13261       op_out[i][0] = 0;
13262       op_index[i] = -1;
13263     }
13264
13265   the_info = info;
13266   start_pc = pc;
13267   start_codep = priv.the_buffer;
13268   codep = priv.the_buffer;
13269
13270   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13271     {
13272       const char *name;
13273
13274       /* Getting here means we tried for data but didn't get it.  That
13275          means we have an incomplete instruction of some sort.  Just
13276          print the first byte as a prefix or a .byte pseudo-op.  */
13277       if (codep > priv.the_buffer)
13278         {
13279           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13280           if (name != NULL)
13281             (*info->fprintf_func) (info->stream, "%s", name);
13282           else
13283             {
13284               /* Just print the first byte as a .byte instruction.  */
13285               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13286                                      (unsigned int) priv.the_buffer[0]);
13287             }
13288
13289           return 1;
13290         }
13291
13292       return -1;
13293     }
13294
13295   obufp = obuf;
13296   sizeflag = priv.orig_sizeflag;
13297
13298   if (!ckprefix () || rex_used)
13299     {
13300       /* Too many prefixes or unused REX prefixes.  */
13301       for (i = 0;
13302            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13303            i++)
13304         (*info->fprintf_func) (info->stream, "%s%s",
13305                                i == 0 ? "" : " ",
13306                                prefix_name (all_prefixes[i], sizeflag));
13307       return i;
13308     }
13309
13310   insn_codep = codep;
13311
13312   FETCH_DATA (info, codep + 1);
13313   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13314
13315   if (((prefixes & PREFIX_FWAIT)
13316        && ((*codep < 0xd8) || (*codep > 0xdf))))
13317     {
13318       /* Handle prefixes before fwait.  */
13319       for (i = 0; i < fwait_prefix && all_prefixes[i];
13320            i++)
13321         (*info->fprintf_func) (info->stream, "%s ",
13322                                prefix_name (all_prefixes[i], sizeflag));
13323       (*info->fprintf_func) (info->stream, "fwait");
13324       return i + 1;
13325     }
13326
13327   if (*codep == 0x0f)
13328     {
13329       unsigned char threebyte;
13330
13331       codep++;
13332       FETCH_DATA (info, codep + 1);
13333       threebyte = *codep;
13334       dp = &dis386_twobyte[threebyte];
13335       need_modrm = twobyte_has_modrm[*codep];
13336       codep++;
13337     }
13338   else
13339     {
13340       dp = &dis386[*codep];
13341       need_modrm = onebyte_has_modrm[*codep];
13342       codep++;
13343     }
13344
13345   /* Save sizeflag for printing the extra prefixes later before updating
13346      it for mnemonic and operand processing.  The prefix names depend
13347      only on the address mode.  */
13348   orig_sizeflag = sizeflag;
13349   if (prefixes & PREFIX_ADDR)
13350     sizeflag ^= AFLAG;
13351   if ((prefixes & PREFIX_DATA))
13352     sizeflag ^= DFLAG;
13353
13354   end_codep = codep;
13355   if (need_modrm)
13356     {
13357       FETCH_DATA (info, codep + 1);
13358       modrm.mod = (*codep >> 6) & 3;
13359       modrm.reg = (*codep >> 3) & 7;
13360       modrm.rm = *codep & 7;
13361     }
13362
13363   need_vex = 0;
13364   need_vex_reg = 0;
13365   vex_w_done = 0;
13366   vex.evex = 0;
13367
13368   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13369     {
13370       get_sib (info, sizeflag);
13371       dofloat (sizeflag);
13372     }
13373   else
13374     {
13375       dp = get_valid_dis386 (dp, info);
13376       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13377         {
13378           get_sib (info, sizeflag);
13379           for (i = 0; i < MAX_OPERANDS; ++i)
13380             {
13381               obufp = op_out[i];
13382               op_ad = MAX_OPERANDS - 1 - i;
13383               if (dp->op[i].rtn)
13384                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13385               /* For EVEX instruction after the last operand masking
13386                  should be printed.  */
13387               if (i == 0 && vex.evex)
13388                 {
13389                   /* Don't print {%k0}.  */
13390                   if (vex.mask_register_specifier)
13391                     {
13392                       oappend ("{");
13393                       oappend (names_mask[vex.mask_register_specifier]);
13394                       oappend ("}");
13395                     }
13396                   if (vex.zeroing)
13397                     oappend ("{z}");
13398                 }
13399             }
13400         }
13401     }
13402
13403   /* Check if the REX prefix is used.  */
13404   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13405     all_prefixes[last_rex_prefix] = 0;
13406
13407   /* Check if the SEG prefix is used.  */
13408   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13409                    | PREFIX_FS | PREFIX_GS)) != 0
13410       && (used_prefixes & active_seg_prefix) != 0)
13411     all_prefixes[last_seg_prefix] = 0;
13412
13413   /* Check if the ADDR prefix is used.  */
13414   if ((prefixes & PREFIX_ADDR) != 0
13415       && (used_prefixes & PREFIX_ADDR) != 0)
13416     all_prefixes[last_addr_prefix] = 0;
13417
13418   /* Check if the DATA prefix is used.  */
13419   if ((prefixes & PREFIX_DATA) != 0
13420       && (used_prefixes & PREFIX_DATA) != 0)
13421     all_prefixes[last_data_prefix] = 0;
13422
13423   /* Print the extra prefixes.  */
13424   prefix_length = 0;
13425   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13426     if (all_prefixes[i])
13427       {
13428         const char *name;
13429         name = prefix_name (all_prefixes[i], orig_sizeflag);
13430         if (name == NULL)
13431           abort ();
13432         prefix_length += strlen (name) + 1;
13433         (*info->fprintf_func) (info->stream, "%s ", name);
13434       }
13435
13436   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13437      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13438      used by putop and MMX/SSE operand and may be overriden by the
13439      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13440      separately.  */
13441   if (dp->prefix_requirement == PREFIX_OPCODE
13442       && dp != &bad_opcode
13443       && (((prefixes
13444             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13445            && (used_prefixes
13446                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13447           || ((((prefixes
13448                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13449                 == PREFIX_DATA)
13450                && (used_prefixes & PREFIX_DATA) == 0))))
13451     {
13452       (*info->fprintf_func) (info->stream, "(bad)");
13453       return end_codep - priv.the_buffer;
13454     }
13455
13456   /* Check maximum code length.  */
13457   if ((codep - start_codep) > MAX_CODE_LENGTH)
13458     {
13459       (*info->fprintf_func) (info->stream, "(bad)");
13460       return MAX_CODE_LENGTH;
13461     }
13462
13463   obufp = mnemonicendp;
13464   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13465     oappend (" ");
13466   oappend (" ");
13467   (*info->fprintf_func) (info->stream, "%s", obuf);
13468
13469   /* The enter and bound instructions are printed with operands in the same
13470      order as the intel book; everything else is printed in reverse order.  */
13471   if (intel_syntax || two_source_ops)
13472     {
13473       bfd_vma riprel;
13474
13475       for (i = 0; i < MAX_OPERANDS; ++i)
13476         op_txt[i] = op_out[i];
13477
13478       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13479           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13480         {
13481           op_txt[2] = op_out[3];
13482           op_txt[3] = op_out[2];
13483         }
13484
13485       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13486         {
13487           op_ad = op_index[i];
13488           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13489           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13490           riprel = op_riprel[i];
13491           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13492           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13493         }
13494     }
13495   else
13496     {
13497       for (i = 0; i < MAX_OPERANDS; ++i)
13498         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13499     }
13500
13501   needcomma = 0;
13502   for (i = 0; i < MAX_OPERANDS; ++i)
13503     if (*op_txt[i])
13504       {
13505         if (needcomma)
13506           (*info->fprintf_func) (info->stream, ",");
13507         if (op_index[i] != -1 && !op_riprel[i])
13508           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13509         else
13510           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13511         needcomma = 1;
13512       }
13513
13514   for (i = 0; i < MAX_OPERANDS; i++)
13515     if (op_index[i] != -1 && op_riprel[i])
13516       {
13517         (*info->fprintf_func) (info->stream, "        # ");
13518         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13519                                                 + op_address[op_index[i]]), info);
13520         break;
13521       }
13522   return codep - priv.the_buffer;
13523 }
13524
13525 static const char *float_mem[] = {
13526   /* d8 */
13527   "fadd{s|}",
13528   "fmul{s|}",
13529   "fcom{s|}",
13530   "fcomp{s|}",
13531   "fsub{s|}",
13532   "fsubr{s|}",
13533   "fdiv{s|}",
13534   "fdivr{s|}",
13535   /* d9 */
13536   "fld{s|}",
13537   "(bad)",
13538   "fst{s|}",
13539   "fstp{s|}",
13540   "fldenvIC",
13541   "fldcw",
13542   "fNstenvIC",
13543   "fNstcw",
13544   /* da */
13545   "fiadd{l|}",
13546   "fimul{l|}",
13547   "ficom{l|}",
13548   "ficomp{l|}",
13549   "fisub{l|}",
13550   "fisubr{l|}",
13551   "fidiv{l|}",
13552   "fidivr{l|}",
13553   /* db */
13554   "fild{l|}",
13555   "fisttp{l|}",
13556   "fist{l|}",
13557   "fistp{l|}",
13558   "(bad)",
13559   "fld{t||t|}",
13560   "(bad)",
13561   "fstp{t||t|}",
13562   /* dc */
13563   "fadd{l|}",
13564   "fmul{l|}",
13565   "fcom{l|}",
13566   "fcomp{l|}",
13567   "fsub{l|}",
13568   "fsubr{l|}",
13569   "fdiv{l|}",
13570   "fdivr{l|}",
13571   /* dd */
13572   "fld{l|}",
13573   "fisttp{ll|}",
13574   "fst{l||}",
13575   "fstp{l|}",
13576   "frstorIC",
13577   "(bad)",
13578   "fNsaveIC",
13579   "fNstsw",
13580   /* de */
13581   "fiadd{s|}",
13582   "fimul{s|}",
13583   "ficom{s|}",
13584   "ficomp{s|}",
13585   "fisub{s|}",
13586   "fisubr{s|}",
13587   "fidiv{s|}",
13588   "fidivr{s|}",
13589   /* df */
13590   "fild{s|}",
13591   "fisttp{s|}",
13592   "fist{s|}",
13593   "fistp{s|}",
13594   "fbld",
13595   "fild{ll|}",
13596   "fbstp",
13597   "fistp{ll|}",
13598 };
13599
13600 static const unsigned char float_mem_mode[] = {
13601   /* d8 */
13602   d_mode,
13603   d_mode,
13604   d_mode,
13605   d_mode,
13606   d_mode,
13607   d_mode,
13608   d_mode,
13609   d_mode,
13610   /* d9 */
13611   d_mode,
13612   0,
13613   d_mode,
13614   d_mode,
13615   0,
13616   w_mode,
13617   0,
13618   w_mode,
13619   /* da */
13620   d_mode,
13621   d_mode,
13622   d_mode,
13623   d_mode,
13624   d_mode,
13625   d_mode,
13626   d_mode,
13627   d_mode,
13628   /* db */
13629   d_mode,
13630   d_mode,
13631   d_mode,
13632   d_mode,
13633   0,
13634   t_mode,
13635   0,
13636   t_mode,
13637   /* dc */
13638   q_mode,
13639   q_mode,
13640   q_mode,
13641   q_mode,
13642   q_mode,
13643   q_mode,
13644   q_mode,
13645   q_mode,
13646   /* dd */
13647   q_mode,
13648   q_mode,
13649   q_mode,
13650   q_mode,
13651   0,
13652   0,
13653   0,
13654   w_mode,
13655   /* de */
13656   w_mode,
13657   w_mode,
13658   w_mode,
13659   w_mode,
13660   w_mode,
13661   w_mode,
13662   w_mode,
13663   w_mode,
13664   /* df */
13665   w_mode,
13666   w_mode,
13667   w_mode,
13668   w_mode,
13669   t_mode,
13670   q_mode,
13671   t_mode,
13672   q_mode
13673 };
13674
13675 #define ST { OP_ST, 0 }
13676 #define STi { OP_STi, 0 }
13677
13678 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13679 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13680 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13681 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13682 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13683 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13684 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13685 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13686 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13687
13688 static const struct dis386 float_reg[][8] = {
13689   /* d8 */
13690   {
13691     { "fadd",   { ST, STi }, 0 },
13692     { "fmul",   { ST, STi }, 0 },
13693     { "fcom",   { STi }, 0 },
13694     { "fcomp",  { STi }, 0 },
13695     { "fsub",   { ST, STi }, 0 },
13696     { "fsubr",  { ST, STi }, 0 },
13697     { "fdiv",   { ST, STi }, 0 },
13698     { "fdivr",  { ST, STi }, 0 },
13699   },
13700   /* d9 */
13701   {
13702     { "fld",    { STi }, 0 },
13703     { "fxch",   { STi }, 0 },
13704     { FGRPd9_2 },
13705     { Bad_Opcode },
13706     { FGRPd9_4 },
13707     { FGRPd9_5 },
13708     { FGRPd9_6 },
13709     { FGRPd9_7 },
13710   },
13711   /* da */
13712   {
13713     { "fcmovb", { ST, STi }, 0 },
13714     { "fcmove", { ST, STi }, 0 },
13715     { "fcmovbe",{ ST, STi }, 0 },
13716     { "fcmovu", { ST, STi }, 0 },
13717     { Bad_Opcode },
13718     { FGRPda_5 },
13719     { Bad_Opcode },
13720     { Bad_Opcode },
13721   },
13722   /* db */
13723   {
13724     { "fcmovnb",{ ST, STi }, 0 },
13725     { "fcmovne",{ ST, STi }, 0 },
13726     { "fcmovnbe",{ ST, STi }, 0 },
13727     { "fcmovnu",{ ST, STi }, 0 },
13728     { FGRPdb_4 },
13729     { "fucomi", { ST, STi }, 0 },
13730     { "fcomi",  { ST, STi }, 0 },
13731     { Bad_Opcode },
13732   },
13733   /* dc */
13734   {
13735     { "fadd",   { STi, ST }, 0 },
13736     { "fmul",   { STi, ST }, 0 },
13737     { Bad_Opcode },
13738     { Bad_Opcode },
13739     { "fsub!M", { STi, ST }, 0 },
13740     { "fsubM",  { STi, ST }, 0 },
13741     { "fdiv!M", { STi, ST }, 0 },
13742     { "fdivM",  { STi, ST }, 0 },
13743   },
13744   /* dd */
13745   {
13746     { "ffree",  { STi }, 0 },
13747     { Bad_Opcode },
13748     { "fst",    { STi }, 0 },
13749     { "fstp",   { STi }, 0 },
13750     { "fucom",  { STi }, 0 },
13751     { "fucomp", { STi }, 0 },
13752     { Bad_Opcode },
13753     { Bad_Opcode },
13754   },
13755   /* de */
13756   {
13757     { "faddp",  { STi, ST }, 0 },
13758     { "fmulp",  { STi, ST }, 0 },
13759     { Bad_Opcode },
13760     { FGRPde_3 },
13761     { "fsub!Mp", { STi, ST }, 0 },
13762     { "fsubMp", { STi, ST }, 0 },
13763     { "fdiv!Mp", { STi, ST }, 0 },
13764     { "fdivMp", { STi, ST }, 0 },
13765   },
13766   /* df */
13767   {
13768     { "ffreep", { STi }, 0 },
13769     { Bad_Opcode },
13770     { Bad_Opcode },
13771     { Bad_Opcode },
13772     { FGRPdf_4 },
13773     { "fucomip", { ST, STi }, 0 },
13774     { "fcomip", { ST, STi }, 0 },
13775     { Bad_Opcode },
13776   },
13777 };
13778
13779 static char *fgrps[][8] = {
13780   /* Bad opcode 0 */
13781   {
13782     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13783   },
13784
13785   /* d9_2  1 */
13786   {
13787     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13788   },
13789
13790   /* d9_4  2 */
13791   {
13792     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13793   },
13794
13795   /* d9_5  3 */
13796   {
13797     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13798   },
13799
13800   /* d9_6  4 */
13801   {
13802     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13803   },
13804
13805   /* d9_7  5 */
13806   {
13807     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13808   },
13809
13810   /* da_5  6 */
13811   {
13812     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13813   },
13814
13815   /* db_4  7 */
13816   {
13817     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13818     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13819   },
13820
13821   /* de_3  8 */
13822   {
13823     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13824   },
13825
13826   /* df_4  9 */
13827   {
13828     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13829   },
13830 };
13831
13832 static void
13833 swap_operand (void)
13834 {
13835   mnemonicendp[0] = '.';
13836   mnemonicendp[1] = 's';
13837   mnemonicendp += 2;
13838 }
13839
13840 static void
13841 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13842                int sizeflag ATTRIBUTE_UNUSED)
13843 {
13844   /* Skip mod/rm byte.  */
13845   MODRM_CHECK;
13846   codep++;
13847 }
13848
13849 static void
13850 dofloat (int sizeflag)
13851 {
13852   const struct dis386 *dp;
13853   unsigned char floatop;
13854
13855   floatop = codep[-1];
13856
13857   if (modrm.mod != 3)
13858     {
13859       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13860
13861       putop (float_mem[fp_indx], sizeflag);
13862       obufp = op_out[0];
13863       op_ad = 2;
13864       OP_E (float_mem_mode[fp_indx], sizeflag);
13865       return;
13866     }
13867   /* Skip mod/rm byte.  */
13868   MODRM_CHECK;
13869   codep++;
13870
13871   dp = &float_reg[floatop - 0xd8][modrm.reg];
13872   if (dp->name == NULL)
13873     {
13874       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13875
13876       /* Instruction fnstsw is only one with strange arg.  */
13877       if (floatop == 0xdf && codep[-1] == 0xe0)
13878         strcpy (op_out[0], names16[0]);
13879     }
13880   else
13881     {
13882       putop (dp->name, sizeflag);
13883
13884       obufp = op_out[0];
13885       op_ad = 2;
13886       if (dp->op[0].rtn)
13887         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13888
13889       obufp = op_out[1];
13890       op_ad = 1;
13891       if (dp->op[1].rtn)
13892         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13893     }
13894 }
13895
13896 /* Like oappend (below), but S is a string starting with '%'.
13897    In Intel syntax, the '%' is elided.  */
13898 static void
13899 oappend_maybe_intel (const char *s)
13900 {
13901   oappend (s + intel_syntax);
13902 }
13903
13904 static void
13905 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13906 {
13907   oappend_maybe_intel ("%st");
13908 }
13909
13910 static void
13911 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13912 {
13913   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13914   oappend_maybe_intel (scratchbuf);
13915 }
13916
13917 /* Capital letters in template are macros.  */
13918 static int
13919 putop (const char *in_template, int sizeflag)
13920 {
13921   const char *p;
13922   int alt = 0;
13923   int cond = 1;
13924   unsigned int l = 0, len = 1;
13925   char last[4];
13926
13927 #define SAVE_LAST(c)                    \
13928   if (l < len && l < sizeof (last))     \
13929     last[l++] = c;                      \
13930   else                                  \
13931     abort ();
13932
13933   for (p = in_template; *p; p++)
13934     {
13935       switch (*p)
13936         {
13937         default:
13938           *obufp++ = *p;
13939           break;
13940         case '%':
13941           len++;
13942           break;
13943         case '!':
13944           cond = 0;
13945           break;
13946         case '{':
13947           if (intel_syntax)
13948             {
13949               while (*++p != '|')
13950                 if (*p == '}' || *p == '\0')
13951                   abort ();
13952             }
13953           /* Fall through.  */
13954         case 'I':
13955           alt = 1;
13956           continue;
13957         case '|':
13958           while (*++p != '}')
13959             {
13960               if (*p == '\0')
13961                 abort ();
13962             }
13963           break;
13964         case '}':
13965           break;
13966         case 'A':
13967           if (intel_syntax)
13968             break;
13969           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13970             *obufp++ = 'b';
13971           break;
13972         case 'B':
13973           if (l == 0 && len == 1)
13974             {
13975 case_B:
13976               if (intel_syntax)
13977                 break;
13978               if (sizeflag & SUFFIX_ALWAYS)
13979                 *obufp++ = 'b';
13980             }
13981           else
13982             {
13983               if (l != 1
13984                   || len != 2
13985                   || last[0] != 'L')
13986                 {
13987                   SAVE_LAST (*p);
13988                   break;
13989                 }
13990
13991               if (address_mode == mode_64bit
13992                   && !(prefixes & PREFIX_ADDR))
13993                 {
13994                   *obufp++ = 'a';
13995                   *obufp++ = 'b';
13996                   *obufp++ = 's';
13997                 }
13998
13999               goto case_B;
14000             }
14001           break;
14002         case 'C':
14003           if (intel_syntax && !alt)
14004             break;
14005           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14006             {
14007               if (sizeflag & DFLAG)
14008                 *obufp++ = intel_syntax ? 'd' : 'l';
14009               else
14010                 *obufp++ = intel_syntax ? 'w' : 's';
14011               used_prefixes |= (prefixes & PREFIX_DATA);
14012             }
14013           break;
14014         case 'D':
14015           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14016             break;
14017           USED_REX (REX_W);
14018           if (modrm.mod == 3)
14019             {
14020               if (rex & REX_W)
14021                 *obufp++ = 'q';
14022               else
14023                 {
14024                   if (sizeflag & DFLAG)
14025                     *obufp++ = intel_syntax ? 'd' : 'l';
14026                   else
14027                     *obufp++ = 'w';
14028                   used_prefixes |= (prefixes & PREFIX_DATA);
14029                 }
14030             }
14031           else
14032             *obufp++ = 'w';
14033           break;
14034         case 'E':               /* For jcxz/jecxz */
14035           if (address_mode == mode_64bit)
14036             {
14037               if (sizeflag & AFLAG)
14038                 *obufp++ = 'r';
14039               else
14040                 *obufp++ = 'e';
14041             }
14042           else
14043             if (sizeflag & AFLAG)
14044               *obufp++ = 'e';
14045           used_prefixes |= (prefixes & PREFIX_ADDR);
14046           break;
14047         case 'F':
14048           if (intel_syntax)
14049             break;
14050           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14051             {
14052               if (sizeflag & AFLAG)
14053                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14054               else
14055                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14056               used_prefixes |= (prefixes & PREFIX_ADDR);
14057             }
14058           break;
14059         case 'G':
14060           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14061             break;
14062           if ((rex & REX_W) || (sizeflag & DFLAG))
14063             *obufp++ = 'l';
14064           else
14065             *obufp++ = 'w';
14066           if (!(rex & REX_W))
14067             used_prefixes |= (prefixes & PREFIX_DATA);
14068           break;
14069         case 'H':
14070           if (intel_syntax)
14071             break;
14072           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14073               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14074             {
14075               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14076               *obufp++ = ',';
14077               *obufp++ = 'p';
14078               if (prefixes & PREFIX_DS)
14079                 *obufp++ = 't';
14080               else
14081                 *obufp++ = 'n';
14082             }
14083           break;
14084         case 'J':
14085           if (intel_syntax)
14086             break;
14087           *obufp++ = 'l';
14088           break;
14089         case 'K':
14090           USED_REX (REX_W);
14091           if (rex & REX_W)
14092             *obufp++ = 'q';
14093           else
14094             *obufp++ = 'd';
14095           break;
14096         case 'Z':
14097           if (l != 0 || len != 1)
14098             {
14099               if (l != 1 || len != 2 || last[0] != 'X')
14100                 {
14101                   SAVE_LAST (*p);
14102                   break;
14103                 }
14104               if (!need_vex || !vex.evex)
14105                 abort ();
14106               if (intel_syntax
14107                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14108                 break;
14109               switch (vex.length)
14110                 {
14111                 case 128:
14112                   *obufp++ = 'x';
14113                   break;
14114                 case 256:
14115                   *obufp++ = 'y';
14116                   break;
14117                 case 512:
14118                   *obufp++ = 'z';
14119                   break;
14120                 default:
14121                   abort ();
14122                 }
14123               break;
14124             }
14125           if (intel_syntax)
14126             break;
14127           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14128             {
14129               *obufp++ = 'q';
14130               break;
14131             }
14132           /* Fall through.  */
14133           goto case_L;
14134         case 'L':
14135           if (l != 0 || len != 1)
14136             {
14137               SAVE_LAST (*p);
14138               break;
14139             }
14140 case_L:
14141           if (intel_syntax)
14142             break;
14143           if (sizeflag & SUFFIX_ALWAYS)
14144             *obufp++ = 'l';
14145           break;
14146         case 'M':
14147           if (intel_mnemonic != cond)
14148             *obufp++ = 'r';
14149           break;
14150         case 'N':
14151           if ((prefixes & PREFIX_FWAIT) == 0)
14152             *obufp++ = 'n';
14153           else
14154             used_prefixes |= PREFIX_FWAIT;
14155           break;
14156         case 'O':
14157           USED_REX (REX_W);
14158           if (rex & REX_W)
14159             *obufp++ = 'o';
14160           else if (intel_syntax && (sizeflag & DFLAG))
14161             *obufp++ = 'q';
14162           else
14163             *obufp++ = 'd';
14164           if (!(rex & REX_W))
14165             used_prefixes |= (prefixes & PREFIX_DATA);
14166           break;
14167         case '&':
14168           if (!intel_syntax
14169               && address_mode == mode_64bit
14170               && isa64 == intel64)
14171             {
14172               *obufp++ = 'q';
14173               break;
14174             }
14175           /* Fall through.  */
14176         case 'T':
14177           if (!intel_syntax
14178               && address_mode == mode_64bit
14179               && ((sizeflag & DFLAG) || (rex & REX_W)))
14180             {
14181               *obufp++ = 'q';
14182               break;
14183             }
14184           /* Fall through.  */
14185           goto case_P;
14186         case 'P':
14187           if (l == 0 && len == 1)
14188             {
14189 case_P:
14190               if (intel_syntax)
14191                 {
14192                   if ((rex & REX_W) == 0
14193                       && (prefixes & PREFIX_DATA))
14194                     {
14195                       if ((sizeflag & DFLAG) == 0)
14196                         *obufp++ = 'w';
14197                       used_prefixes |= (prefixes & PREFIX_DATA);
14198                     }
14199                   break;
14200                 }
14201               if ((prefixes & PREFIX_DATA)
14202                   || (rex & REX_W)
14203                   || (sizeflag & SUFFIX_ALWAYS))
14204                 {
14205                   USED_REX (REX_W);
14206                   if (rex & REX_W)
14207                     *obufp++ = 'q';
14208                   else
14209                     {
14210                       if (sizeflag & DFLAG)
14211                         *obufp++ = 'l';
14212                       else
14213                         *obufp++ = 'w';
14214                       used_prefixes |= (prefixes & PREFIX_DATA);
14215                     }
14216                 }
14217             }
14218           else
14219             {
14220               if (l != 1 || len != 2 || last[0] != 'L')
14221                 {
14222                   SAVE_LAST (*p);
14223                   break;
14224                 }
14225
14226               if ((prefixes & PREFIX_DATA)
14227                   || (rex & REX_W)
14228                   || (sizeflag & SUFFIX_ALWAYS))
14229                 {
14230                   USED_REX (REX_W);
14231                   if (rex & REX_W)
14232                     *obufp++ = 'q';
14233                   else
14234                     {
14235                       if (sizeflag & DFLAG)
14236                         *obufp++ = intel_syntax ? 'd' : 'l';
14237                       else
14238                         *obufp++ = 'w';
14239                       used_prefixes |= (prefixes & PREFIX_DATA);
14240                     }
14241                 }
14242             }
14243           break;
14244         case 'U':
14245           if (intel_syntax)
14246             break;
14247           if (address_mode == mode_64bit
14248               && ((sizeflag & DFLAG) || (rex & REX_W)))
14249             {
14250               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14251                 *obufp++ = 'q';
14252               break;
14253             }
14254           /* Fall through.  */
14255           goto case_Q;
14256         case 'Q':
14257           if (l == 0 && len == 1)
14258             {
14259 case_Q:
14260               if (intel_syntax && !alt)
14261                 break;
14262               USED_REX (REX_W);
14263               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14264                 {
14265                   if (rex & REX_W)
14266                     *obufp++ = 'q';
14267                   else
14268                     {
14269                       if (sizeflag & DFLAG)
14270                         *obufp++ = intel_syntax ? 'd' : 'l';
14271                       else
14272                         *obufp++ = 'w';
14273                       used_prefixes |= (prefixes & PREFIX_DATA);
14274                     }
14275                 }
14276             }
14277           else
14278             {
14279               if (l != 1 || len != 2 || last[0] != 'L')
14280                 {
14281                   SAVE_LAST (*p);
14282                   break;
14283                 }
14284               if (intel_syntax
14285                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14286                 break;
14287               if ((rex & REX_W))
14288                 {
14289                   USED_REX (REX_W);
14290                   *obufp++ = 'q';
14291                 }
14292               else
14293                 *obufp++ = 'l';
14294             }
14295           break;
14296         case 'R':
14297           USED_REX (REX_W);
14298           if (rex & REX_W)
14299             *obufp++ = 'q';
14300           else if (sizeflag & DFLAG)
14301             {
14302               if (intel_syntax)
14303                   *obufp++ = 'd';
14304               else
14305                   *obufp++ = 'l';
14306             }
14307           else
14308             *obufp++ = 'w';
14309           if (intel_syntax && !p[1]
14310               && ((rex & REX_W) || (sizeflag & DFLAG)))
14311             *obufp++ = 'e';
14312           if (!(rex & REX_W))
14313             used_prefixes |= (prefixes & PREFIX_DATA);
14314           break;
14315         case 'V':
14316           if (l == 0 && len == 1)
14317             {
14318               if (intel_syntax)
14319                 break;
14320               if (address_mode == mode_64bit
14321                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14322                 {
14323                   if (sizeflag & SUFFIX_ALWAYS)
14324                     *obufp++ = 'q';
14325                   break;
14326                 }
14327             }
14328           else
14329             {
14330               if (l != 1
14331                   || len != 2
14332                   || last[0] != 'L')
14333                 {
14334                   SAVE_LAST (*p);
14335                   break;
14336                 }
14337
14338               if (rex & REX_W)
14339                 {
14340                   *obufp++ = 'a';
14341                   *obufp++ = 'b';
14342                   *obufp++ = 's';
14343                 }
14344             }
14345           /* Fall through.  */
14346           goto case_S;
14347         case 'S':
14348           if (l == 0 && len == 1)
14349             {
14350 case_S:
14351               if (intel_syntax)
14352                 break;
14353               if (sizeflag & SUFFIX_ALWAYS)
14354                 {
14355                   if (rex & REX_W)
14356                     *obufp++ = 'q';
14357                   else
14358                     {
14359                       if (sizeflag & DFLAG)
14360                         *obufp++ = 'l';
14361                       else
14362                         *obufp++ = 'w';
14363                       used_prefixes |= (prefixes & PREFIX_DATA);
14364                     }
14365                 }
14366             }
14367           else
14368             {
14369               if (l != 1
14370                   || len != 2
14371                   || last[0] != 'L')
14372                 {
14373                   SAVE_LAST (*p);
14374                   break;
14375                 }
14376
14377               if (address_mode == mode_64bit
14378                   && !(prefixes & PREFIX_ADDR))
14379                 {
14380                   *obufp++ = 'a';
14381                   *obufp++ = 'b';
14382                   *obufp++ = 's';
14383                 }
14384
14385               goto case_S;
14386             }
14387           break;
14388         case 'X':
14389           if (l != 0 || len != 1)
14390             {
14391               SAVE_LAST (*p);
14392               break;
14393             }
14394           if (need_vex && vex.prefix)
14395             {
14396               if (vex.prefix == DATA_PREFIX_OPCODE)
14397                 *obufp++ = 'd';
14398               else
14399                 *obufp++ = 's';
14400             }
14401           else
14402             {
14403               if (prefixes & PREFIX_DATA)
14404                 *obufp++ = 'd';
14405               else
14406                 *obufp++ = 's';
14407               used_prefixes |= (prefixes & PREFIX_DATA);
14408             }
14409           break;
14410         case 'Y':
14411           if (l == 0 && len == 1)
14412             {
14413               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14414                 break;
14415               if (rex & REX_W)
14416                 {
14417                   USED_REX (REX_W);
14418                   *obufp++ = 'q';
14419                 }
14420               break;
14421             }
14422           else
14423             {
14424               if (l != 1 || len != 2 || last[0] != 'X')
14425                 {
14426                   SAVE_LAST (*p);
14427                   break;
14428                 }
14429               if (!need_vex)
14430                 abort ();
14431               if (intel_syntax
14432                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14433                 break;
14434               switch (vex.length)
14435                 {
14436                 case 128:
14437                   *obufp++ = 'x';
14438                   break;
14439                 case 256:
14440                   *obufp++ = 'y';
14441                   break;
14442                 case 512:
14443                   if (!vex.evex)
14444                 default:
14445                     abort ();
14446                 }
14447             }
14448           break;
14449         case 'W':
14450           if (l == 0 && len == 1)
14451             {
14452               /* operand size flag for cwtl, cbtw */
14453               USED_REX (REX_W);
14454               if (rex & REX_W)
14455                 {
14456                   if (intel_syntax)
14457                     *obufp++ = 'd';
14458                   else
14459                     *obufp++ = 'l';
14460                 }
14461               else if (sizeflag & DFLAG)
14462                 *obufp++ = 'w';
14463               else
14464                 *obufp++ = 'b';
14465               if (!(rex & REX_W))
14466                 used_prefixes |= (prefixes & PREFIX_DATA);
14467             }
14468           else
14469             {
14470               if (l != 1
14471                   || len != 2
14472                   || (last[0] != 'X'
14473                       && last[0] != 'L'))
14474                 {
14475                   SAVE_LAST (*p);
14476                   break;
14477                 }
14478               if (!need_vex)
14479                 abort ();
14480               if (last[0] == 'X')
14481                 *obufp++ = vex.w ? 'd': 's';
14482               else
14483                 *obufp++ = vex.w ? 'q': 'd';
14484             }
14485           break;
14486         case '^':
14487           if (intel_syntax)
14488             break;
14489           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14490             {
14491               if (sizeflag & DFLAG)
14492                 *obufp++ = 'l';
14493               else
14494                 *obufp++ = 'w';
14495               used_prefixes |= (prefixes & PREFIX_DATA);
14496             }
14497           break;
14498         case '@':
14499           if (intel_syntax)
14500             break;
14501           if (address_mode == mode_64bit
14502               && (isa64 == intel64
14503                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14504               *obufp++ = 'q';
14505           else if ((prefixes & PREFIX_DATA))
14506             {
14507               if (!(sizeflag & DFLAG))
14508                 *obufp++ = 'w';
14509               used_prefixes |= (prefixes & PREFIX_DATA);
14510             }
14511           break;
14512         }
14513       alt = 0;
14514     }
14515   *obufp = 0;
14516   mnemonicendp = obufp;
14517   return 0;
14518 }
14519
14520 static void
14521 oappend (const char *s)
14522 {
14523   obufp = stpcpy (obufp, s);
14524 }
14525
14526 static void
14527 append_seg (void)
14528 {
14529   /* Only print the active segment register.  */
14530   if (!active_seg_prefix)
14531     return;
14532
14533   used_prefixes |= active_seg_prefix;
14534   switch (active_seg_prefix)
14535     {
14536     case PREFIX_CS:
14537       oappend_maybe_intel ("%cs:");
14538       break;
14539     case PREFIX_DS:
14540       oappend_maybe_intel ("%ds:");
14541       break;
14542     case PREFIX_SS:
14543       oappend_maybe_intel ("%ss:");
14544       break;
14545     case PREFIX_ES:
14546       oappend_maybe_intel ("%es:");
14547       break;
14548     case PREFIX_FS:
14549       oappend_maybe_intel ("%fs:");
14550       break;
14551     case PREFIX_GS:
14552       oappend_maybe_intel ("%gs:");
14553       break;
14554     default:
14555       break;
14556     }
14557 }
14558
14559 static void
14560 OP_indirE (int bytemode, int sizeflag)
14561 {
14562   if (!intel_syntax)
14563     oappend ("*");
14564   OP_E (bytemode, sizeflag);
14565 }
14566
14567 static void
14568 print_operand_value (char *buf, int hex, bfd_vma disp)
14569 {
14570   if (address_mode == mode_64bit)
14571     {
14572       if (hex)
14573         {
14574           char tmp[30];
14575           int i;
14576           buf[0] = '0';
14577           buf[1] = 'x';
14578           sprintf_vma (tmp, disp);
14579           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14580           strcpy (buf + 2, tmp + i);
14581         }
14582       else
14583         {
14584           bfd_signed_vma v = disp;
14585           char tmp[30];
14586           int i;
14587           if (v < 0)
14588             {
14589               *(buf++) = '-';
14590               v = -disp;
14591               /* Check for possible overflow on 0x8000000000000000.  */
14592               if (v < 0)
14593                 {
14594                   strcpy (buf, "9223372036854775808");
14595                   return;
14596                 }
14597             }
14598           if (!v)
14599             {
14600               strcpy (buf, "0");
14601               return;
14602             }
14603
14604           i = 0;
14605           tmp[29] = 0;
14606           while (v)
14607             {
14608               tmp[28 - i] = (v % 10) + '0';
14609               v /= 10;
14610               i++;
14611             }
14612           strcpy (buf, tmp + 29 - i);
14613         }
14614     }
14615   else
14616     {
14617       if (hex)
14618         sprintf (buf, "0x%x", (unsigned int) disp);
14619       else
14620         sprintf (buf, "%d", (int) disp);
14621     }
14622 }
14623
14624 /* Put DISP in BUF as signed hex number.  */
14625
14626 static void
14627 print_displacement (char *buf, bfd_vma disp)
14628 {
14629   bfd_signed_vma val = disp;
14630   char tmp[30];
14631   int i, j = 0;
14632
14633   if (val < 0)
14634     {
14635       buf[j++] = '-';
14636       val = -disp;
14637
14638       /* Check for possible overflow.  */
14639       if (val < 0)
14640         {
14641           switch (address_mode)
14642             {
14643             case mode_64bit:
14644               strcpy (buf + j, "0x8000000000000000");
14645               break;
14646             case mode_32bit:
14647               strcpy (buf + j, "0x80000000");
14648               break;
14649             case mode_16bit:
14650               strcpy (buf + j, "0x8000");
14651               break;
14652             }
14653           return;
14654         }
14655     }
14656
14657   buf[j++] = '0';
14658   buf[j++] = 'x';
14659
14660   sprintf_vma (tmp, (bfd_vma) val);
14661   for (i = 0; tmp[i] == '0'; i++)
14662     continue;
14663   if (tmp[i] == '\0')
14664     i--;
14665   strcpy (buf + j, tmp + i);
14666 }
14667
14668 static void
14669 intel_operand_size (int bytemode, int sizeflag)
14670 {
14671   if (vex.evex
14672       && vex.b
14673       && (bytemode == x_mode
14674           || bytemode == evex_half_bcst_xmmq_mode))
14675     {
14676       if (vex.w)
14677         oappend ("QWORD PTR ");
14678       else
14679         oappend ("DWORD PTR ");
14680       return;
14681     }
14682   switch (bytemode)
14683     {
14684     case b_mode:
14685     case b_swap_mode:
14686     case dqb_mode:
14687     case db_mode:
14688       oappend ("BYTE PTR ");
14689       break;
14690     case w_mode:
14691     case dw_mode:
14692     case dqw_mode:
14693       oappend ("WORD PTR ");
14694       break;
14695     case indir_v_mode:
14696       if (address_mode == mode_64bit && isa64 == intel64)
14697         {
14698           oappend ("QWORD PTR ");
14699           break;
14700         }
14701       /* Fall through.  */
14702     case stack_v_mode:
14703       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14704         {
14705           oappend ("QWORD PTR ");
14706           break;
14707         }
14708       /* Fall through.  */
14709     case v_mode:
14710     case v_swap_mode:
14711     case dq_mode:
14712       USED_REX (REX_W);
14713       if (rex & REX_W)
14714         oappend ("QWORD PTR ");
14715       else
14716         {
14717           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14718             oappend ("DWORD PTR ");
14719           else
14720             oappend ("WORD PTR ");
14721           used_prefixes |= (prefixes & PREFIX_DATA);
14722         }
14723       break;
14724     case z_mode:
14725       if ((rex & REX_W) || (sizeflag & DFLAG))
14726         *obufp++ = 'D';
14727       oappend ("WORD PTR ");
14728       if (!(rex & REX_W))
14729         used_prefixes |= (prefixes & PREFIX_DATA);
14730       break;
14731     case a_mode:
14732       if (sizeflag & DFLAG)
14733         oappend ("QWORD PTR ");
14734       else
14735         oappend ("DWORD PTR ");
14736       used_prefixes |= (prefixes & PREFIX_DATA);
14737       break;
14738     case d_mode:
14739     case d_scalar_mode:
14740     case d_scalar_swap_mode:
14741     case d_swap_mode:
14742     case dqd_mode:
14743       oappend ("DWORD PTR ");
14744       break;
14745     case q_mode:
14746     case q_scalar_mode:
14747     case q_scalar_swap_mode:
14748     case q_swap_mode:
14749       oappend ("QWORD PTR ");
14750       break;
14751     case m_mode:
14752       if (address_mode == mode_64bit)
14753         oappend ("QWORD PTR ");
14754       else
14755         oappend ("DWORD PTR ");
14756       break;
14757     case f_mode:
14758       if (sizeflag & DFLAG)
14759         oappend ("FWORD PTR ");
14760       else
14761         oappend ("DWORD PTR ");
14762       used_prefixes |= (prefixes & PREFIX_DATA);
14763       break;
14764     case t_mode:
14765       oappend ("TBYTE PTR ");
14766       break;
14767     case x_mode:
14768     case x_swap_mode:
14769     case evex_x_gscat_mode:
14770     case evex_x_nobcst_mode:
14771     case b_scalar_mode:
14772     case w_scalar_mode:
14773       if (need_vex)
14774         {
14775           switch (vex.length)
14776             {
14777             case 128:
14778               oappend ("XMMWORD PTR ");
14779               break;
14780             case 256:
14781               oappend ("YMMWORD PTR ");
14782               break;
14783             case 512:
14784               oappend ("ZMMWORD PTR ");
14785               break;
14786             default:
14787               abort ();
14788             }
14789         }
14790       else
14791         oappend ("XMMWORD PTR ");
14792       break;
14793     case xmm_mode:
14794       oappend ("XMMWORD PTR ");
14795       break;
14796     case ymm_mode:
14797       oappend ("YMMWORD PTR ");
14798       break;
14799     case xmmq_mode:
14800     case evex_half_bcst_xmmq_mode:
14801       if (!need_vex)
14802         abort ();
14803
14804       switch (vex.length)
14805         {
14806         case 128:
14807           oappend ("QWORD PTR ");
14808           break;
14809         case 256:
14810           oappend ("XMMWORD PTR ");
14811           break;
14812         case 512:
14813           oappend ("YMMWORD PTR ");
14814           break;
14815         default:
14816           abort ();
14817         }
14818       break;
14819     case xmm_mb_mode:
14820       if (!need_vex)
14821         abort ();
14822
14823       switch (vex.length)
14824         {
14825         case 128:
14826         case 256:
14827         case 512:
14828           oappend ("BYTE PTR ");
14829           break;
14830         default:
14831           abort ();
14832         }
14833       break;
14834     case xmm_mw_mode:
14835       if (!need_vex)
14836         abort ();
14837
14838       switch (vex.length)
14839         {
14840         case 128:
14841         case 256:
14842         case 512:
14843           oappend ("WORD PTR ");
14844           break;
14845         default:
14846           abort ();
14847         }
14848       break;
14849     case xmm_md_mode:
14850       if (!need_vex)
14851         abort ();
14852
14853       switch (vex.length)
14854         {
14855         case 128:
14856         case 256:
14857         case 512:
14858           oappend ("DWORD PTR ");
14859           break;
14860         default:
14861           abort ();
14862         }
14863       break;
14864     case xmm_mq_mode:
14865       if (!need_vex)
14866         abort ();
14867
14868       switch (vex.length)
14869         {
14870         case 128:
14871         case 256:
14872         case 512:
14873           oappend ("QWORD PTR ");
14874           break;
14875         default:
14876           abort ();
14877         }
14878       break;
14879     case xmmdw_mode:
14880       if (!need_vex)
14881         abort ();
14882
14883       switch (vex.length)
14884         {
14885         case 128:
14886           oappend ("WORD PTR ");
14887           break;
14888         case 256:
14889           oappend ("DWORD PTR ");
14890           break;
14891         case 512:
14892           oappend ("QWORD PTR ");
14893           break;
14894         default:
14895           abort ();
14896         }
14897       break;
14898     case xmmqd_mode:
14899       if (!need_vex)
14900         abort ();
14901
14902       switch (vex.length)
14903         {
14904         case 128:
14905           oappend ("DWORD PTR ");
14906           break;
14907         case 256:
14908           oappend ("QWORD PTR ");
14909           break;
14910         case 512:
14911           oappend ("XMMWORD PTR ");
14912           break;
14913         default:
14914           abort ();
14915         }
14916       break;
14917     case ymmq_mode:
14918       if (!need_vex)
14919         abort ();
14920
14921       switch (vex.length)
14922         {
14923         case 128:
14924           oappend ("QWORD PTR ");
14925           break;
14926         case 256:
14927           oappend ("YMMWORD PTR ");
14928           break;
14929         case 512:
14930           oappend ("ZMMWORD PTR ");
14931           break;
14932         default:
14933           abort ();
14934         }
14935       break;
14936     case ymmxmm_mode:
14937       if (!need_vex)
14938         abort ();
14939
14940       switch (vex.length)
14941         {
14942         case 128:
14943         case 256:
14944           oappend ("XMMWORD PTR ");
14945           break;
14946         default:
14947           abort ();
14948         }
14949       break;
14950     case o_mode:
14951       oappend ("OWORD PTR ");
14952       break;
14953     case xmm_mdq_mode:
14954     case vex_w_dq_mode:
14955     case vex_scalar_w_dq_mode:
14956       if (!need_vex)
14957         abort ();
14958
14959       if (vex.w)
14960         oappend ("QWORD PTR ");
14961       else
14962         oappend ("DWORD PTR ");
14963       break;
14964     case vex_vsib_d_w_dq_mode:
14965     case vex_vsib_q_w_dq_mode:
14966       if (!need_vex)
14967         abort ();
14968
14969       if (!vex.evex)
14970         {
14971           if (vex.w)
14972             oappend ("QWORD PTR ");
14973           else
14974             oappend ("DWORD PTR ");
14975         }
14976       else
14977         {
14978           switch (vex.length)
14979             {
14980             case 128:
14981               oappend ("XMMWORD PTR ");
14982               break;
14983             case 256:
14984               oappend ("YMMWORD PTR ");
14985               break;
14986             case 512:
14987               oappend ("ZMMWORD PTR ");
14988               break;
14989             default:
14990               abort ();
14991             }
14992         }
14993       break;
14994     case vex_vsib_q_w_d_mode:
14995     case vex_vsib_d_w_d_mode:
14996       if (!need_vex || !vex.evex)
14997         abort ();
14998
14999       switch (vex.length)
15000         {
15001         case 128:
15002           oappend ("QWORD PTR ");
15003           break;
15004         case 256:
15005           oappend ("XMMWORD PTR ");
15006           break;
15007         case 512:
15008           oappend ("YMMWORD PTR ");
15009           break;
15010         default:
15011           abort ();
15012         }
15013
15014       break;
15015     case mask_bd_mode:
15016       if (!need_vex || vex.length != 128)
15017         abort ();
15018       if (vex.w)
15019         oappend ("DWORD PTR ");
15020       else
15021         oappend ("BYTE PTR ");
15022       break;
15023     case mask_mode:
15024       if (!need_vex)
15025         abort ();
15026       if (vex.w)
15027         oappend ("QWORD PTR ");
15028       else
15029         oappend ("WORD PTR ");
15030       break;
15031     case v_bnd_mode:
15032     default:
15033       break;
15034     }
15035 }
15036
15037 static void
15038 OP_E_register (int bytemode, int sizeflag)
15039 {
15040   int reg = modrm.rm;
15041   const char **names;
15042
15043   USED_REX (REX_B);
15044   if ((rex & REX_B))
15045     reg += 8;
15046
15047   if ((sizeflag & SUFFIX_ALWAYS)
15048       && (bytemode == b_swap_mode
15049           || bytemode == v_swap_mode))
15050     swap_operand ();
15051
15052   switch (bytemode)
15053     {
15054     case b_mode:
15055     case b_swap_mode:
15056       USED_REX (0);
15057       if (rex)
15058         names = names8rex;
15059       else
15060         names = names8;
15061       break;
15062     case w_mode:
15063       names = names16;
15064       break;
15065     case d_mode:
15066     case dw_mode:
15067     case db_mode:
15068       names = names32;
15069       break;
15070     case q_mode:
15071       names = names64;
15072       break;
15073     case m_mode:
15074     case v_bnd_mode:
15075       names = address_mode == mode_64bit ? names64 : names32;
15076       break;
15077     case bnd_mode:
15078       if (reg > 0x3)
15079         {
15080           oappend ("(bad)");
15081           return;
15082         }
15083       names = names_bnd;
15084       break;
15085     case indir_v_mode:
15086       if (address_mode == mode_64bit && isa64 == intel64)
15087         {
15088           names = names64;
15089           break;
15090         }
15091       /* Fall through.  */
15092     case stack_v_mode:
15093       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15094         {
15095           names = names64;
15096           break;
15097         }
15098       bytemode = v_mode;
15099       /* Fall through.  */
15100     case v_mode:
15101     case v_swap_mode:
15102     case dq_mode:
15103     case dqb_mode:
15104     case dqd_mode:
15105     case dqw_mode:
15106       USED_REX (REX_W);
15107       if (rex & REX_W)
15108         names = names64;
15109       else
15110         {
15111           if ((sizeflag & DFLAG)
15112               || (bytemode != v_mode
15113                   && bytemode != v_swap_mode))
15114             names = names32;
15115           else
15116             names = names16;
15117           used_prefixes |= (prefixes & PREFIX_DATA);
15118         }
15119       break;
15120     case mask_bd_mode:
15121     case mask_mode:
15122       if (reg > 0x7)
15123         {
15124           oappend ("(bad)");
15125           return;
15126         }
15127       names = names_mask;
15128       break;
15129     case 0:
15130       return;
15131     default:
15132       oappend (INTERNAL_DISASSEMBLER_ERROR);
15133       return;
15134     }
15135   oappend (names[reg]);
15136 }
15137
15138 static void
15139 OP_E_memory (int bytemode, int sizeflag)
15140 {
15141   bfd_vma disp = 0;
15142   int add = (rex & REX_B) ? 8 : 0;
15143   int riprel = 0;
15144   int shift;
15145
15146   if (vex.evex)
15147     {
15148       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15149       if (vex.b
15150           && bytemode != x_mode
15151           && bytemode != xmmq_mode
15152           && bytemode != evex_half_bcst_xmmq_mode)
15153         {
15154           BadOp ();
15155           return;
15156         }
15157       switch (bytemode)
15158         {
15159         case dqw_mode:
15160         case dw_mode:
15161           shift = 1;
15162           break;
15163         case dqb_mode:
15164         case db_mode:
15165           shift = 0;
15166           break;
15167         case vex_vsib_d_w_dq_mode:
15168         case vex_vsib_d_w_d_mode:
15169         case vex_vsib_q_w_dq_mode:
15170         case vex_vsib_q_w_d_mode:
15171         case evex_x_gscat_mode:
15172         case xmm_mdq_mode:
15173           shift = vex.w ? 3 : 2;
15174           break;
15175         case x_mode:
15176         case evex_half_bcst_xmmq_mode:
15177         case xmmq_mode:
15178           if (vex.b)
15179             {
15180               shift = vex.w ? 3 : 2;
15181               break;
15182             }
15183           /* Fall through.  */
15184         case xmmqd_mode:
15185         case xmmdw_mode:
15186         case ymmq_mode:
15187         case evex_x_nobcst_mode:
15188         case x_swap_mode:
15189           switch (vex.length)
15190             {
15191             case 128:
15192               shift = 4;
15193               break;
15194             case 256:
15195               shift = 5;
15196               break;
15197             case 512:
15198               shift = 6;
15199               break;
15200             default:
15201               abort ();
15202             }
15203           break;
15204         case ymm_mode:
15205           shift = 5;
15206           break;
15207         case xmm_mode:
15208           shift = 4;
15209           break;
15210         case xmm_mq_mode:
15211         case q_mode:
15212         case q_scalar_mode:
15213         case q_swap_mode:
15214         case q_scalar_swap_mode:
15215           shift = 3;
15216           break;
15217         case dqd_mode:
15218         case xmm_md_mode:
15219         case d_mode:
15220         case d_scalar_mode:
15221         case d_swap_mode:
15222         case d_scalar_swap_mode:
15223           shift = 2;
15224           break;
15225     case w_scalar_mode:
15226         case xmm_mw_mode:
15227           shift = 1;
15228           break;
15229     case b_scalar_mode:
15230         case xmm_mb_mode:
15231           shift = 0;
15232           break;
15233         default:
15234           abort ();
15235         }
15236       /* Make necessary corrections to shift for modes that need it.
15237          For these modes we currently have shift 4, 5 or 6 depending on
15238          vex.length (it corresponds to xmmword, ymmword or zmmword
15239          operand).  We might want to make it 3, 4 or 5 (e.g. for
15240          xmmq_mode).  In case of broadcast enabled the corrections
15241          aren't needed, as element size is always 32 or 64 bits.  */
15242       if (!vex.b
15243           && (bytemode == xmmq_mode
15244               || bytemode == evex_half_bcst_xmmq_mode))
15245         shift -= 1;
15246       else if (bytemode == xmmqd_mode)
15247         shift -= 2;
15248       else if (bytemode == xmmdw_mode)
15249         shift -= 3;
15250       else if (bytemode == ymmq_mode && vex.length == 128)
15251         shift -= 1;
15252     }
15253   else
15254     shift = 0;
15255
15256   USED_REX (REX_B);
15257   if (intel_syntax)
15258     intel_operand_size (bytemode, sizeflag);
15259   append_seg ();
15260
15261   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15262     {
15263       /* 32/64 bit address mode */
15264       int havedisp;
15265       int havesib;
15266       int havebase;
15267       int haveindex;
15268       int needindex;
15269       int base, rbase;
15270       int vindex = 0;
15271       int scale = 0;
15272       int addr32flag = !((sizeflag & AFLAG)
15273                          || bytemode == v_bnd_mode
15274                          || bytemode == bnd_mode);
15275       const char **indexes64 = names64;
15276       const char **indexes32 = names32;
15277
15278       havesib = 0;
15279       havebase = 1;
15280       haveindex = 0;
15281       base = modrm.rm;
15282
15283       if (base == 4)
15284         {
15285           havesib = 1;
15286           vindex = sib.index;
15287           USED_REX (REX_X);
15288           if (rex & REX_X)
15289             vindex += 8;
15290           switch (bytemode)
15291             {
15292             case vex_vsib_d_w_dq_mode:
15293             case vex_vsib_d_w_d_mode:
15294             case vex_vsib_q_w_dq_mode:
15295             case vex_vsib_q_w_d_mode:
15296               if (!need_vex)
15297                 abort ();
15298               if (vex.evex)
15299                 {
15300                   if (!vex.v)
15301                     vindex += 16;
15302                 }
15303
15304               haveindex = 1;
15305               switch (vex.length)
15306                 {
15307                 case 128:
15308                   indexes64 = indexes32 = names_xmm;
15309                   break;
15310                 case 256:
15311                   if (!vex.w
15312                       || bytemode == vex_vsib_q_w_dq_mode
15313                       || bytemode == vex_vsib_q_w_d_mode)
15314                     indexes64 = indexes32 = names_ymm;
15315                   else
15316                     indexes64 = indexes32 = names_xmm;
15317                   break;
15318                 case 512:
15319                   if (!vex.w
15320                       || bytemode == vex_vsib_q_w_dq_mode
15321                       || bytemode == vex_vsib_q_w_d_mode)
15322                     indexes64 = indexes32 = names_zmm;
15323                   else
15324                     indexes64 = indexes32 = names_ymm;
15325                   break;
15326                 default:
15327                   abort ();
15328                 }
15329               break;
15330             default:
15331               haveindex = vindex != 4;
15332               break;
15333             }
15334           scale = sib.scale;
15335           base = sib.base;
15336           codep++;
15337         }
15338       rbase = base + add;
15339
15340       switch (modrm.mod)
15341         {
15342         case 0:
15343           if (base == 5)
15344             {
15345               havebase = 0;
15346               if (address_mode == mode_64bit && !havesib)
15347                 riprel = 1;
15348               disp = get32s ();
15349             }
15350           break;
15351         case 1:
15352           FETCH_DATA (the_info, codep + 1);
15353           disp = *codep++;
15354           if ((disp & 0x80) != 0)
15355             disp -= 0x100;
15356           if (vex.evex && shift > 0)
15357             disp <<= shift;
15358           break;
15359         case 2:
15360           disp = get32s ();
15361           break;
15362         }
15363
15364       /* In 32bit mode, we need index register to tell [offset] from
15365          [eiz*1 + offset].  */
15366       needindex = (havesib
15367                    && !havebase
15368                    && !haveindex
15369                    && address_mode == mode_32bit);
15370       havedisp = (havebase
15371                   || needindex
15372                   || (havesib && (haveindex || scale != 0)));
15373
15374       if (!intel_syntax)
15375         if (modrm.mod != 0 || base == 5)
15376           {
15377             if (havedisp || riprel)
15378               print_displacement (scratchbuf, disp);
15379             else
15380               print_operand_value (scratchbuf, 1, disp);
15381             oappend (scratchbuf);
15382             if (riprel)
15383               {
15384                 set_op (disp, 1);
15385                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15386               }
15387           }
15388
15389       if ((havebase || haveindex || riprel)
15390           && (bytemode != v_bnd_mode)
15391           && (bytemode != bnd_mode))
15392         used_prefixes |= PREFIX_ADDR;
15393
15394       if (havedisp || (intel_syntax && riprel))
15395         {
15396           *obufp++ = open_char;
15397           if (intel_syntax && riprel)
15398             {
15399               set_op (disp, 1);
15400               oappend (!addr32flag ? "rip" : "eip");
15401             }
15402           *obufp = '\0';
15403           if (havebase)
15404             oappend (address_mode == mode_64bit && !addr32flag
15405                      ? names64[rbase] : names32[rbase]);
15406           if (havesib)
15407             {
15408               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15409                  print index to tell base + index from base.  */
15410               if (scale != 0
15411                   || needindex
15412                   || haveindex
15413                   || (havebase && base != ESP_REG_NUM))
15414                 {
15415                   if (!intel_syntax || havebase)
15416                     {
15417                       *obufp++ = separator_char;
15418                       *obufp = '\0';
15419                     }
15420                   if (haveindex)
15421                     oappend (address_mode == mode_64bit && !addr32flag
15422                              ? indexes64[vindex] : indexes32[vindex]);
15423                   else
15424                     oappend (address_mode == mode_64bit && !addr32flag
15425                              ? index64 : index32);
15426
15427                   *obufp++ = scale_char;
15428                   *obufp = '\0';
15429                   sprintf (scratchbuf, "%d", 1 << scale);
15430                   oappend (scratchbuf);
15431                 }
15432             }
15433           if (intel_syntax
15434               && (disp || modrm.mod != 0 || base == 5))
15435             {
15436               if (!havedisp || (bfd_signed_vma) disp >= 0)
15437                 {
15438                   *obufp++ = '+';
15439                   *obufp = '\0';
15440                 }
15441               else if (modrm.mod != 1 && disp != -disp)
15442                 {
15443                   *obufp++ = '-';
15444                   *obufp = '\0';
15445                   disp = - (bfd_signed_vma) disp;
15446                 }
15447
15448               if (havedisp)
15449                 print_displacement (scratchbuf, disp);
15450               else
15451                 print_operand_value (scratchbuf, 1, disp);
15452               oappend (scratchbuf);
15453             }
15454
15455           *obufp++ = close_char;
15456           *obufp = '\0';
15457         }
15458       else if (intel_syntax)
15459         {
15460           if (modrm.mod != 0 || base == 5)
15461             {
15462               if (!active_seg_prefix)
15463                 {
15464                   oappend (names_seg[ds_reg - es_reg]);
15465                   oappend (":");
15466                 }
15467               print_operand_value (scratchbuf, 1, disp);
15468               oappend (scratchbuf);
15469             }
15470         }
15471     }
15472   else
15473     {
15474       /* 16 bit address mode */
15475       used_prefixes |= prefixes & PREFIX_ADDR;
15476       switch (modrm.mod)
15477         {
15478         case 0:
15479           if (modrm.rm == 6)
15480             {
15481               disp = get16 ();
15482               if ((disp & 0x8000) != 0)
15483                 disp -= 0x10000;
15484             }
15485           break;
15486         case 1:
15487           FETCH_DATA (the_info, codep + 1);
15488           disp = *codep++;
15489           if ((disp & 0x80) != 0)
15490             disp -= 0x100;
15491           if (vex.evex && shift > 0)
15492             disp <<= shift;
15493           break;
15494         case 2:
15495           disp = get16 ();
15496           if ((disp & 0x8000) != 0)
15497             disp -= 0x10000;
15498           break;
15499         }
15500
15501       if (!intel_syntax)
15502         if (modrm.mod != 0 || modrm.rm == 6)
15503           {
15504             print_displacement (scratchbuf, disp);
15505             oappend (scratchbuf);
15506           }
15507
15508       if (modrm.mod != 0 || modrm.rm != 6)
15509         {
15510           *obufp++ = open_char;
15511           *obufp = '\0';
15512           oappend (index16[modrm.rm]);
15513           if (intel_syntax
15514               && (disp || modrm.mod != 0 || modrm.rm == 6))
15515             {
15516               if ((bfd_signed_vma) disp >= 0)
15517                 {
15518                   *obufp++ = '+';
15519                   *obufp = '\0';
15520                 }
15521               else if (modrm.mod != 1)
15522                 {
15523                   *obufp++ = '-';
15524                   *obufp = '\0';
15525                   disp = - (bfd_signed_vma) disp;
15526                 }
15527
15528               print_displacement (scratchbuf, disp);
15529               oappend (scratchbuf);
15530             }
15531
15532           *obufp++ = close_char;
15533           *obufp = '\0';
15534         }
15535       else if (intel_syntax)
15536         {
15537           if (!active_seg_prefix)
15538             {
15539               oappend (names_seg[ds_reg - es_reg]);
15540               oappend (":");
15541             }
15542           print_operand_value (scratchbuf, 1, disp & 0xffff);
15543           oappend (scratchbuf);
15544         }
15545     }
15546   if (vex.evex && vex.b
15547       && (bytemode == x_mode
15548           || bytemode == xmmq_mode
15549           || bytemode == evex_half_bcst_xmmq_mode))
15550     {
15551       if (vex.w
15552           || bytemode == xmmq_mode
15553           || bytemode == evex_half_bcst_xmmq_mode)
15554         {
15555           switch (vex.length)
15556             {
15557             case 128:
15558               oappend ("{1to2}");
15559               break;
15560             case 256:
15561               oappend ("{1to4}");
15562               break;
15563             case 512:
15564               oappend ("{1to8}");
15565               break;
15566             default:
15567               abort ();
15568             }
15569         }
15570       else
15571         {
15572           switch (vex.length)
15573             {
15574             case 128:
15575               oappend ("{1to4}");
15576               break;
15577             case 256:
15578               oappend ("{1to8}");
15579               break;
15580             case 512:
15581               oappend ("{1to16}");
15582               break;
15583             default:
15584               abort ();
15585             }
15586         }
15587     }
15588 }
15589
15590 static void
15591 OP_E (int bytemode, int sizeflag)
15592 {
15593   /* Skip mod/rm byte.  */
15594   MODRM_CHECK;
15595   codep++;
15596
15597   if (modrm.mod == 3)
15598     OP_E_register (bytemode, sizeflag);
15599   else
15600     OP_E_memory (bytemode, sizeflag);
15601 }
15602
15603 static void
15604 OP_G (int bytemode, int sizeflag)
15605 {
15606   int add = 0;
15607   USED_REX (REX_R);
15608   if (rex & REX_R)
15609     add += 8;
15610   switch (bytemode)
15611     {
15612     case b_mode:
15613       USED_REX (0);
15614       if (rex)
15615         oappend (names8rex[modrm.reg + add]);
15616       else
15617         oappend (names8[modrm.reg + add]);
15618       break;
15619     case w_mode:
15620       oappend (names16[modrm.reg + add]);
15621       break;
15622     case d_mode:
15623     case db_mode:
15624     case dw_mode:
15625       oappend (names32[modrm.reg + add]);
15626       break;
15627     case q_mode:
15628       oappend (names64[modrm.reg + add]);
15629       break;
15630     case bnd_mode:
15631       if (modrm.reg > 0x3)
15632         {
15633           oappend ("(bad)");
15634           return;
15635         }
15636       oappend (names_bnd[modrm.reg]);
15637       break;
15638     case v_mode:
15639     case dq_mode:
15640     case dqb_mode:
15641     case dqd_mode:
15642     case dqw_mode:
15643       USED_REX (REX_W);
15644       if (rex & REX_W)
15645         oappend (names64[modrm.reg + add]);
15646       else
15647         {
15648           if ((sizeflag & DFLAG) || bytemode != v_mode)
15649             oappend (names32[modrm.reg + add]);
15650           else
15651             oappend (names16[modrm.reg + add]);
15652           used_prefixes |= (prefixes & PREFIX_DATA);
15653         }
15654       break;
15655     case m_mode:
15656       if (address_mode == mode_64bit)
15657         oappend (names64[modrm.reg + add]);
15658       else
15659         oappend (names32[modrm.reg + add]);
15660       break;
15661     case mask_bd_mode:
15662     case mask_mode:
15663       if ((modrm.reg + add) > 0x7)
15664         {
15665           oappend ("(bad)");
15666           return;
15667         }
15668       oappend (names_mask[modrm.reg + add]);
15669       break;
15670     default:
15671       oappend (INTERNAL_DISASSEMBLER_ERROR);
15672       break;
15673     }
15674 }
15675
15676 static bfd_vma
15677 get64 (void)
15678 {
15679   bfd_vma x;
15680 #ifdef BFD64
15681   unsigned int a;
15682   unsigned int b;
15683
15684   FETCH_DATA (the_info, codep + 8);
15685   a = *codep++ & 0xff;
15686   a |= (*codep++ & 0xff) << 8;
15687   a |= (*codep++ & 0xff) << 16;
15688   a |= (*codep++ & 0xffu) << 24;
15689   b = *codep++ & 0xff;
15690   b |= (*codep++ & 0xff) << 8;
15691   b |= (*codep++ & 0xff) << 16;
15692   b |= (*codep++ & 0xffu) << 24;
15693   x = a + ((bfd_vma) b << 32);
15694 #else
15695   abort ();
15696   x = 0;
15697 #endif
15698   return x;
15699 }
15700
15701 static bfd_signed_vma
15702 get32 (void)
15703 {
15704   bfd_signed_vma x = 0;
15705
15706   FETCH_DATA (the_info, codep + 4);
15707   x = *codep++ & (bfd_signed_vma) 0xff;
15708   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15709   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15710   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15711   return x;
15712 }
15713
15714 static bfd_signed_vma
15715 get32s (void)
15716 {
15717   bfd_signed_vma x = 0;
15718
15719   FETCH_DATA (the_info, codep + 4);
15720   x = *codep++ & (bfd_signed_vma) 0xff;
15721   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15722   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15723   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15724
15725   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15726
15727   return x;
15728 }
15729
15730 static int
15731 get16 (void)
15732 {
15733   int x = 0;
15734
15735   FETCH_DATA (the_info, codep + 2);
15736   x = *codep++ & 0xff;
15737   x |= (*codep++ & 0xff) << 8;
15738   return x;
15739 }
15740
15741 static void
15742 set_op (bfd_vma op, int riprel)
15743 {
15744   op_index[op_ad] = op_ad;
15745   if (address_mode == mode_64bit)
15746     {
15747       op_address[op_ad] = op;
15748       op_riprel[op_ad] = riprel;
15749     }
15750   else
15751     {
15752       /* Mask to get a 32-bit address.  */
15753       op_address[op_ad] = op & 0xffffffff;
15754       op_riprel[op_ad] = riprel & 0xffffffff;
15755     }
15756 }
15757
15758 static void
15759 OP_REG (int code, int sizeflag)
15760 {
15761   const char *s;
15762   int add;
15763
15764   switch (code)
15765     {
15766     case es_reg: case ss_reg: case cs_reg:
15767     case ds_reg: case fs_reg: case gs_reg:
15768       oappend (names_seg[code - es_reg]);
15769       return;
15770     }
15771
15772   USED_REX (REX_B);
15773   if (rex & REX_B)
15774     add = 8;
15775   else
15776     add = 0;
15777
15778   switch (code)
15779     {
15780     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15781     case sp_reg: case bp_reg: case si_reg: case di_reg:
15782       s = names16[code - ax_reg + add];
15783       break;
15784     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15785     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15786       USED_REX (0);
15787       if (rex)
15788         s = names8rex[code - al_reg + add];
15789       else
15790         s = names8[code - al_reg];
15791       break;
15792     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15793     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15794       if (address_mode == mode_64bit
15795           && ((sizeflag & DFLAG) || (rex & REX_W)))
15796         {
15797           s = names64[code - rAX_reg + add];
15798           break;
15799         }
15800       code += eAX_reg - rAX_reg;
15801       /* Fall through.  */
15802     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15803     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15804       USED_REX (REX_W);
15805       if (rex & REX_W)
15806         s = names64[code - eAX_reg + add];
15807       else
15808         {
15809           if (sizeflag & DFLAG)
15810             s = names32[code - eAX_reg + add];
15811           else
15812             s = names16[code - eAX_reg + add];
15813           used_prefixes |= (prefixes & PREFIX_DATA);
15814         }
15815       break;
15816     default:
15817       s = INTERNAL_DISASSEMBLER_ERROR;
15818       break;
15819     }
15820   oappend (s);
15821 }
15822
15823 static void
15824 OP_IMREG (int code, int sizeflag)
15825 {
15826   const char *s;
15827
15828   switch (code)
15829     {
15830     case indir_dx_reg:
15831       if (intel_syntax)
15832         s = "dx";
15833       else
15834         s = "(%dx)";
15835       break;
15836     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15837     case sp_reg: case bp_reg: case si_reg: case di_reg:
15838       s = names16[code - ax_reg];
15839       break;
15840     case es_reg: case ss_reg: case cs_reg:
15841     case ds_reg: case fs_reg: case gs_reg:
15842       s = names_seg[code - es_reg];
15843       break;
15844     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15845     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15846       USED_REX (0);
15847       if (rex)
15848         s = names8rex[code - al_reg];
15849       else
15850         s = names8[code - al_reg];
15851       break;
15852     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15853     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15854       USED_REX (REX_W);
15855       if (rex & REX_W)
15856         s = names64[code - eAX_reg];
15857       else
15858         {
15859           if (sizeflag & DFLAG)
15860             s = names32[code - eAX_reg];
15861           else
15862             s = names16[code - eAX_reg];
15863           used_prefixes |= (prefixes & PREFIX_DATA);
15864         }
15865       break;
15866     case z_mode_ax_reg:
15867       if ((rex & REX_W) || (sizeflag & DFLAG))
15868         s = *names32;
15869       else
15870         s = *names16;
15871       if (!(rex & REX_W))
15872         used_prefixes |= (prefixes & PREFIX_DATA);
15873       break;
15874     default:
15875       s = INTERNAL_DISASSEMBLER_ERROR;
15876       break;
15877     }
15878   oappend (s);
15879 }
15880
15881 static void
15882 OP_I (int bytemode, int sizeflag)
15883 {
15884   bfd_signed_vma op;
15885   bfd_signed_vma mask = -1;
15886
15887   switch (bytemode)
15888     {
15889     case b_mode:
15890       FETCH_DATA (the_info, codep + 1);
15891       op = *codep++;
15892       mask = 0xff;
15893       break;
15894     case q_mode:
15895       if (address_mode == mode_64bit)
15896         {
15897           op = get32s ();
15898           break;
15899         }
15900       /* Fall through.  */
15901     case v_mode:
15902       USED_REX (REX_W);
15903       if (rex & REX_W)
15904         op = get32s ();
15905       else
15906         {
15907           if (sizeflag & DFLAG)
15908             {
15909               op = get32 ();
15910               mask = 0xffffffff;
15911             }
15912           else
15913             {
15914               op = get16 ();
15915               mask = 0xfffff;
15916             }
15917           used_prefixes |= (prefixes & PREFIX_DATA);
15918         }
15919       break;
15920     case w_mode:
15921       mask = 0xfffff;
15922       op = get16 ();
15923       break;
15924     case const_1_mode:
15925       if (intel_syntax)
15926         oappend ("1");
15927       return;
15928     default:
15929       oappend (INTERNAL_DISASSEMBLER_ERROR);
15930       return;
15931     }
15932
15933   op &= mask;
15934   scratchbuf[0] = '$';
15935   print_operand_value (scratchbuf + 1, 1, op);
15936   oappend_maybe_intel (scratchbuf);
15937   scratchbuf[0] = '\0';
15938 }
15939
15940 static void
15941 OP_I64 (int bytemode, int sizeflag)
15942 {
15943   bfd_signed_vma op;
15944   bfd_signed_vma mask = -1;
15945
15946   if (address_mode != mode_64bit)
15947     {
15948       OP_I (bytemode, sizeflag);
15949       return;
15950     }
15951
15952   switch (bytemode)
15953     {
15954     case b_mode:
15955       FETCH_DATA (the_info, codep + 1);
15956       op = *codep++;
15957       mask = 0xff;
15958       break;
15959     case v_mode:
15960       USED_REX (REX_W);
15961       if (rex & REX_W)
15962         op = get64 ();
15963       else
15964         {
15965           if (sizeflag & DFLAG)
15966             {
15967               op = get32 ();
15968               mask = 0xffffffff;
15969             }
15970           else
15971             {
15972               op = get16 ();
15973               mask = 0xfffff;
15974             }
15975           used_prefixes |= (prefixes & PREFIX_DATA);
15976         }
15977       break;
15978     case w_mode:
15979       mask = 0xfffff;
15980       op = get16 ();
15981       break;
15982     default:
15983       oappend (INTERNAL_DISASSEMBLER_ERROR);
15984       return;
15985     }
15986
15987   op &= mask;
15988   scratchbuf[0] = '$';
15989   print_operand_value (scratchbuf + 1, 1, op);
15990   oappend_maybe_intel (scratchbuf);
15991   scratchbuf[0] = '\0';
15992 }
15993
15994 static void
15995 OP_sI (int bytemode, int sizeflag)
15996 {
15997   bfd_signed_vma op;
15998
15999   switch (bytemode)
16000     {
16001     case b_mode:
16002     case b_T_mode:
16003       FETCH_DATA (the_info, codep + 1);
16004       op = *codep++;
16005       if ((op & 0x80) != 0)
16006         op -= 0x100;
16007       if (bytemode == b_T_mode)
16008         {
16009           if (address_mode != mode_64bit
16010               || !((sizeflag & DFLAG) || (rex & REX_W)))
16011             {
16012               /* The operand-size prefix is overridden by a REX prefix.  */
16013               if ((sizeflag & DFLAG) || (rex & REX_W))
16014                 op &= 0xffffffff;
16015               else
16016                 op &= 0xffff;
16017           }
16018         }
16019       else
16020         {
16021           if (!(rex & REX_W))
16022             {
16023               if (sizeflag & DFLAG)
16024                 op &= 0xffffffff;
16025               else
16026                 op &= 0xffff;
16027             }
16028         }
16029       break;
16030     case v_mode:
16031       /* The operand-size prefix is overridden by a REX prefix.  */
16032       if ((sizeflag & DFLAG) || (rex & REX_W))
16033         op = get32s ();
16034       else
16035         op = get16 ();
16036       break;
16037     default:
16038       oappend (INTERNAL_DISASSEMBLER_ERROR);
16039       return;
16040     }
16041
16042   scratchbuf[0] = '$';
16043   print_operand_value (scratchbuf + 1, 1, op);
16044   oappend_maybe_intel (scratchbuf);
16045 }
16046
16047 static void
16048 OP_J (int bytemode, int sizeflag)
16049 {
16050   bfd_vma disp;
16051   bfd_vma mask = -1;
16052   bfd_vma segment = 0;
16053
16054   switch (bytemode)
16055     {
16056     case b_mode:
16057       FETCH_DATA (the_info, codep + 1);
16058       disp = *codep++;
16059       if ((disp & 0x80) != 0)
16060         disp -= 0x100;
16061       break;
16062     case v_mode:
16063       if (isa64 == amd64)
16064         USED_REX (REX_W);
16065       if ((sizeflag & DFLAG)
16066           || (address_mode == mode_64bit
16067               && (isa64 != amd64 || (rex & REX_W))))
16068         disp = get32s ();
16069       else
16070         {
16071           disp = get16 ();
16072           if ((disp & 0x8000) != 0)
16073             disp -= 0x10000;
16074           /* In 16bit mode, address is wrapped around at 64k within
16075              the same segment.  Otherwise, a data16 prefix on a jump
16076              instruction means that the pc is masked to 16 bits after
16077              the displacement is added!  */
16078           mask = 0xffff;
16079           if ((prefixes & PREFIX_DATA) == 0)
16080             segment = ((start_pc + (codep - start_codep))
16081                        & ~((bfd_vma) 0xffff));
16082         }
16083       if (address_mode != mode_64bit
16084           || (isa64 == amd64 && !(rex & REX_W)))
16085         used_prefixes |= (prefixes & PREFIX_DATA);
16086       break;
16087     default:
16088       oappend (INTERNAL_DISASSEMBLER_ERROR);
16089       return;
16090     }
16091   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16092   set_op (disp, 0);
16093   print_operand_value (scratchbuf, 1, disp);
16094   oappend (scratchbuf);
16095 }
16096
16097 static void
16098 OP_SEG (int bytemode, int sizeflag)
16099 {
16100   if (bytemode == w_mode)
16101     oappend (names_seg[modrm.reg]);
16102   else
16103     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16104 }
16105
16106 static void
16107 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16108 {
16109   int seg, offset;
16110
16111   if (sizeflag & DFLAG)
16112     {
16113       offset = get32 ();
16114       seg = get16 ();
16115     }
16116   else
16117     {
16118       offset = get16 ();
16119       seg = get16 ();
16120     }
16121   used_prefixes |= (prefixes & PREFIX_DATA);
16122   if (intel_syntax)
16123     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16124   else
16125     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16126   oappend (scratchbuf);
16127 }
16128
16129 static void
16130 OP_OFF (int bytemode, int sizeflag)
16131 {
16132   bfd_vma off;
16133
16134   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16135     intel_operand_size (bytemode, sizeflag);
16136   append_seg ();
16137
16138   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16139     off = get32 ();
16140   else
16141     off = get16 ();
16142
16143   if (intel_syntax)
16144     {
16145       if (!active_seg_prefix)
16146         {
16147           oappend (names_seg[ds_reg - es_reg]);
16148           oappend (":");
16149         }
16150     }
16151   print_operand_value (scratchbuf, 1, off);
16152   oappend (scratchbuf);
16153 }
16154
16155 static void
16156 OP_OFF64 (int bytemode, int sizeflag)
16157 {
16158   bfd_vma off;
16159
16160   if (address_mode != mode_64bit
16161       || (prefixes & PREFIX_ADDR))
16162     {
16163       OP_OFF (bytemode, sizeflag);
16164       return;
16165     }
16166
16167   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16168     intel_operand_size (bytemode, sizeflag);
16169   append_seg ();
16170
16171   off = get64 ();
16172
16173   if (intel_syntax)
16174     {
16175       if (!active_seg_prefix)
16176         {
16177           oappend (names_seg[ds_reg - es_reg]);
16178           oappend (":");
16179         }
16180     }
16181   print_operand_value (scratchbuf, 1, off);
16182   oappend (scratchbuf);
16183 }
16184
16185 static void
16186 ptr_reg (int code, int sizeflag)
16187 {
16188   const char *s;
16189
16190   *obufp++ = open_char;
16191   used_prefixes |= (prefixes & PREFIX_ADDR);
16192   if (address_mode == mode_64bit)
16193     {
16194       if (!(sizeflag & AFLAG))
16195         s = names32[code - eAX_reg];
16196       else
16197         s = names64[code - eAX_reg];
16198     }
16199   else if (sizeflag & AFLAG)
16200     s = names32[code - eAX_reg];
16201   else
16202     s = names16[code - eAX_reg];
16203   oappend (s);
16204   *obufp++ = close_char;
16205   *obufp = 0;
16206 }
16207
16208 static void
16209 OP_ESreg (int code, int sizeflag)
16210 {
16211   if (intel_syntax)
16212     {
16213       switch (codep[-1])
16214         {
16215         case 0x6d:      /* insw/insl */
16216           intel_operand_size (z_mode, sizeflag);
16217           break;
16218         case 0xa5:      /* movsw/movsl/movsq */
16219         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16220         case 0xab:      /* stosw/stosl */
16221         case 0xaf:      /* scasw/scasl */
16222           intel_operand_size (v_mode, sizeflag);
16223           break;
16224         default:
16225           intel_operand_size (b_mode, sizeflag);
16226         }
16227     }
16228   oappend_maybe_intel ("%es:");
16229   ptr_reg (code, sizeflag);
16230 }
16231
16232 static void
16233 OP_DSreg (int code, int sizeflag)
16234 {
16235   if (intel_syntax)
16236     {
16237       switch (codep[-1])
16238         {
16239         case 0x6f:      /* outsw/outsl */
16240           intel_operand_size (z_mode, sizeflag);
16241           break;
16242         case 0xa5:      /* movsw/movsl/movsq */
16243         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16244         case 0xad:      /* lodsw/lodsl/lodsq */
16245           intel_operand_size (v_mode, sizeflag);
16246           break;
16247         default:
16248           intel_operand_size (b_mode, sizeflag);
16249         }
16250     }
16251   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16252      default segment register DS is printed.  */
16253   if (!active_seg_prefix)
16254     active_seg_prefix = PREFIX_DS;
16255   append_seg ();
16256   ptr_reg (code, sizeflag);
16257 }
16258
16259 static void
16260 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16261 {
16262   int add;
16263   if (rex & REX_R)
16264     {
16265       USED_REX (REX_R);
16266       add = 8;
16267     }
16268   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16269     {
16270       all_prefixes[last_lock_prefix] = 0;
16271       used_prefixes |= PREFIX_LOCK;
16272       add = 8;
16273     }
16274   else
16275     add = 0;
16276   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16277   oappend_maybe_intel (scratchbuf);
16278 }
16279
16280 static void
16281 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16282 {
16283   int add;
16284   USED_REX (REX_R);
16285   if (rex & REX_R)
16286     add = 8;
16287   else
16288     add = 0;
16289   if (intel_syntax)
16290     sprintf (scratchbuf, "db%d", modrm.reg + add);
16291   else
16292     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16293   oappend (scratchbuf);
16294 }
16295
16296 static void
16297 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16298 {
16299   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16300   oappend_maybe_intel (scratchbuf);
16301 }
16302
16303 static void
16304 OP_R (int bytemode, int sizeflag)
16305 {
16306   /* Skip mod/rm byte.  */
16307   MODRM_CHECK;
16308   codep++;
16309   OP_E_register (bytemode, sizeflag);
16310 }
16311
16312 static void
16313 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16314 {
16315   int reg = modrm.reg;
16316   const char **names;
16317
16318   used_prefixes |= (prefixes & PREFIX_DATA);
16319   if (prefixes & PREFIX_DATA)
16320     {
16321       names = names_xmm;
16322       USED_REX (REX_R);
16323       if (rex & REX_R)
16324         reg += 8;
16325     }
16326   else
16327     names = names_mm;
16328   oappend (names[reg]);
16329 }
16330
16331 static void
16332 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16333 {
16334   int reg = modrm.reg;
16335   const char **names;
16336
16337   USED_REX (REX_R);
16338   if (rex & REX_R)
16339     reg += 8;
16340   if (vex.evex)
16341     {
16342       if (!vex.r)
16343         reg += 16;
16344     }
16345
16346   if (need_vex
16347       && bytemode != xmm_mode
16348       && bytemode != xmmq_mode
16349       && bytemode != evex_half_bcst_xmmq_mode
16350       && bytemode != ymm_mode
16351       && bytemode != scalar_mode)
16352     {
16353       switch (vex.length)
16354         {
16355         case 128:
16356           names = names_xmm;
16357           break;
16358         case 256:
16359           if (vex.w
16360               || (bytemode != vex_vsib_q_w_dq_mode
16361                   && bytemode != vex_vsib_q_w_d_mode))
16362             names = names_ymm;
16363           else
16364             names = names_xmm;
16365           break;
16366         case 512:
16367           names = names_zmm;
16368           break;
16369         default:
16370           abort ();
16371         }
16372     }
16373   else if (bytemode == xmmq_mode
16374            || bytemode == evex_half_bcst_xmmq_mode)
16375     {
16376       switch (vex.length)
16377         {
16378         case 128:
16379         case 256:
16380           names = names_xmm;
16381           break;
16382         case 512:
16383           names = names_ymm;
16384           break;
16385         default:
16386           abort ();
16387         }
16388     }
16389   else if (bytemode == ymm_mode)
16390     names = names_ymm;
16391   else
16392     names = names_xmm;
16393   oappend (names[reg]);
16394 }
16395
16396 static void
16397 OP_EM (int bytemode, int sizeflag)
16398 {
16399   int reg;
16400   const char **names;
16401
16402   if (modrm.mod != 3)
16403     {
16404       if (intel_syntax
16405           && (bytemode == v_mode || bytemode == v_swap_mode))
16406         {
16407           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16408           used_prefixes |= (prefixes & PREFIX_DATA);
16409         }
16410       OP_E (bytemode, sizeflag);
16411       return;
16412     }
16413
16414   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16415     swap_operand ();
16416
16417   /* Skip mod/rm byte.  */
16418   MODRM_CHECK;
16419   codep++;
16420   used_prefixes |= (prefixes & PREFIX_DATA);
16421   reg = modrm.rm;
16422   if (prefixes & PREFIX_DATA)
16423     {
16424       names = names_xmm;
16425       USED_REX (REX_B);
16426       if (rex & REX_B)
16427         reg += 8;
16428     }
16429   else
16430     names = names_mm;
16431   oappend (names[reg]);
16432 }
16433
16434 /* cvt* are the only instructions in sse2 which have
16435    both SSE and MMX operands and also have 0x66 prefix
16436    in their opcode. 0x66 was originally used to differentiate
16437    between SSE and MMX instruction(operands). So we have to handle the
16438    cvt* separately using OP_EMC and OP_MXC */
16439 static void
16440 OP_EMC (int bytemode, int sizeflag)
16441 {
16442   if (modrm.mod != 3)
16443     {
16444       if (intel_syntax && bytemode == v_mode)
16445         {
16446           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16447           used_prefixes |= (prefixes & PREFIX_DATA);
16448         }
16449       OP_E (bytemode, sizeflag);
16450       return;
16451     }
16452
16453   /* Skip mod/rm byte.  */
16454   MODRM_CHECK;
16455   codep++;
16456   used_prefixes |= (prefixes & PREFIX_DATA);
16457   oappend (names_mm[modrm.rm]);
16458 }
16459
16460 static void
16461 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16462 {
16463   used_prefixes |= (prefixes & PREFIX_DATA);
16464   oappend (names_mm[modrm.reg]);
16465 }
16466
16467 static void
16468 OP_EX (int bytemode, int sizeflag)
16469 {
16470   int reg;
16471   const char **names;
16472
16473   /* Skip mod/rm byte.  */
16474   MODRM_CHECK;
16475   codep++;
16476
16477   if (modrm.mod != 3)
16478     {
16479       OP_E_memory (bytemode, sizeflag);
16480       return;
16481     }
16482
16483   reg = modrm.rm;
16484   USED_REX (REX_B);
16485   if (rex & REX_B)
16486     reg += 8;
16487   if (vex.evex)
16488     {
16489       USED_REX (REX_X);
16490       if ((rex & REX_X))
16491         reg += 16;
16492     }
16493
16494   if ((sizeflag & SUFFIX_ALWAYS)
16495       && (bytemode == x_swap_mode
16496           || bytemode == d_swap_mode
16497           || bytemode == d_scalar_swap_mode
16498           || bytemode == q_swap_mode
16499           || bytemode == q_scalar_swap_mode))
16500     swap_operand ();
16501
16502   if (need_vex
16503       && bytemode != xmm_mode
16504       && bytemode != xmmdw_mode
16505       && bytemode != xmmqd_mode
16506       && bytemode != xmm_mb_mode
16507       && bytemode != xmm_mw_mode
16508       && bytemode != xmm_md_mode
16509       && bytemode != xmm_mq_mode
16510       && bytemode != xmm_mdq_mode
16511       && bytemode != xmmq_mode
16512       && bytemode != evex_half_bcst_xmmq_mode
16513       && bytemode != ymm_mode
16514       && bytemode != d_scalar_mode
16515       && bytemode != d_scalar_swap_mode
16516       && bytemode != q_scalar_mode
16517       && bytemode != q_scalar_swap_mode
16518       && bytemode != vex_scalar_w_dq_mode)
16519     {
16520       switch (vex.length)
16521         {
16522         case 128:
16523           names = names_xmm;
16524           break;
16525         case 256:
16526           names = names_ymm;
16527           break;
16528         case 512:
16529           names = names_zmm;
16530           break;
16531         default:
16532           abort ();
16533         }
16534     }
16535   else if (bytemode == xmmq_mode
16536            || bytemode == evex_half_bcst_xmmq_mode)
16537     {
16538       switch (vex.length)
16539         {
16540         case 128:
16541         case 256:
16542           names = names_xmm;
16543           break;
16544         case 512:
16545           names = names_ymm;
16546           break;
16547         default:
16548           abort ();
16549         }
16550     }
16551   else if (bytemode == ymm_mode)
16552     names = names_ymm;
16553   else
16554     names = names_xmm;
16555   oappend (names[reg]);
16556 }
16557
16558 static void
16559 OP_MS (int bytemode, int sizeflag)
16560 {
16561   if (modrm.mod == 3)
16562     OP_EM (bytemode, sizeflag);
16563   else
16564     BadOp ();
16565 }
16566
16567 static void
16568 OP_XS (int bytemode, int sizeflag)
16569 {
16570   if (modrm.mod == 3)
16571     OP_EX (bytemode, sizeflag);
16572   else
16573     BadOp ();
16574 }
16575
16576 static void
16577 OP_M (int bytemode, int sizeflag)
16578 {
16579   if (modrm.mod == 3)
16580     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16581     BadOp ();
16582   else
16583     OP_E (bytemode, sizeflag);
16584 }
16585
16586 static void
16587 OP_0f07 (int bytemode, int sizeflag)
16588 {
16589   if (modrm.mod != 3 || modrm.rm != 0)
16590     BadOp ();
16591   else
16592     OP_E (bytemode, sizeflag);
16593 }
16594
16595 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16596    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16597
16598 static void
16599 NOP_Fixup1 (int bytemode, int sizeflag)
16600 {
16601   if ((prefixes & PREFIX_DATA) != 0
16602       || (rex != 0
16603           && rex != 0x48
16604           && address_mode == mode_64bit))
16605     OP_REG (bytemode, sizeflag);
16606   else
16607     strcpy (obuf, "nop");
16608 }
16609
16610 static void
16611 NOP_Fixup2 (int bytemode, int sizeflag)
16612 {
16613   if ((prefixes & PREFIX_DATA) != 0
16614       || (rex != 0
16615           && rex != 0x48
16616           && address_mode == mode_64bit))
16617     OP_IMREG (bytemode, sizeflag);
16618 }
16619
16620 static const char *const Suffix3DNow[] = {
16621 /* 00 */        NULL,           NULL,           NULL,           NULL,
16622 /* 04 */        NULL,           NULL,           NULL,           NULL,
16623 /* 08 */        NULL,           NULL,           NULL,           NULL,
16624 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16625 /* 10 */        NULL,           NULL,           NULL,           NULL,
16626 /* 14 */        NULL,           NULL,           NULL,           NULL,
16627 /* 18 */        NULL,           NULL,           NULL,           NULL,
16628 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16629 /* 20 */        NULL,           NULL,           NULL,           NULL,
16630 /* 24 */        NULL,           NULL,           NULL,           NULL,
16631 /* 28 */        NULL,           NULL,           NULL,           NULL,
16632 /* 2C */        NULL,           NULL,           NULL,           NULL,
16633 /* 30 */        NULL,           NULL,           NULL,           NULL,
16634 /* 34 */        NULL,           NULL,           NULL,           NULL,
16635 /* 38 */        NULL,           NULL,           NULL,           NULL,
16636 /* 3C */        NULL,           NULL,           NULL,           NULL,
16637 /* 40 */        NULL,           NULL,           NULL,           NULL,
16638 /* 44 */        NULL,           NULL,           NULL,           NULL,
16639 /* 48 */        NULL,           NULL,           NULL,           NULL,
16640 /* 4C */        NULL,           NULL,           NULL,           NULL,
16641 /* 50 */        NULL,           NULL,           NULL,           NULL,
16642 /* 54 */        NULL,           NULL,           NULL,           NULL,
16643 /* 58 */        NULL,           NULL,           NULL,           NULL,
16644 /* 5C */        NULL,           NULL,           NULL,           NULL,
16645 /* 60 */        NULL,           NULL,           NULL,           NULL,
16646 /* 64 */        NULL,           NULL,           NULL,           NULL,
16647 /* 68 */        NULL,           NULL,           NULL,           NULL,
16648 /* 6C */        NULL,           NULL,           NULL,           NULL,
16649 /* 70 */        NULL,           NULL,           NULL,           NULL,
16650 /* 74 */        NULL,           NULL,           NULL,           NULL,
16651 /* 78 */        NULL,           NULL,           NULL,           NULL,
16652 /* 7C */        NULL,           NULL,           NULL,           NULL,
16653 /* 80 */        NULL,           NULL,           NULL,           NULL,
16654 /* 84 */        NULL,           NULL,           NULL,           NULL,
16655 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16656 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16657 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16658 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16659 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16660 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16661 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16662 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16663 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16664 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16665 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16666 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16667 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16668 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16669 /* C0 */        NULL,           NULL,           NULL,           NULL,
16670 /* C4 */        NULL,           NULL,           NULL,           NULL,
16671 /* C8 */        NULL,           NULL,           NULL,           NULL,
16672 /* CC */        NULL,           NULL,           NULL,           NULL,
16673 /* D0 */        NULL,           NULL,           NULL,           NULL,
16674 /* D4 */        NULL,           NULL,           NULL,           NULL,
16675 /* D8 */        NULL,           NULL,           NULL,           NULL,
16676 /* DC */        NULL,           NULL,           NULL,           NULL,
16677 /* E0 */        NULL,           NULL,           NULL,           NULL,
16678 /* E4 */        NULL,           NULL,           NULL,           NULL,
16679 /* E8 */        NULL,           NULL,           NULL,           NULL,
16680 /* EC */        NULL,           NULL,           NULL,           NULL,
16681 /* F0 */        NULL,           NULL,           NULL,           NULL,
16682 /* F4 */        NULL,           NULL,           NULL,           NULL,
16683 /* F8 */        NULL,           NULL,           NULL,           NULL,
16684 /* FC */        NULL,           NULL,           NULL,           NULL,
16685 };
16686
16687 static void
16688 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16689 {
16690   const char *mnemonic;
16691
16692   FETCH_DATA (the_info, codep + 1);
16693   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16694      place where an 8-bit immediate would normally go.  ie. the last
16695      byte of the instruction.  */
16696   obufp = mnemonicendp;
16697   mnemonic = Suffix3DNow[*codep++ & 0xff];
16698   if (mnemonic)
16699     oappend (mnemonic);
16700   else
16701     {
16702       /* Since a variable sized modrm/sib chunk is between the start
16703          of the opcode (0x0f0f) and the opcode suffix, we need to do
16704          all the modrm processing first, and don't know until now that
16705          we have a bad opcode.  This necessitates some cleaning up.  */
16706       op_out[0][0] = '\0';
16707       op_out[1][0] = '\0';
16708       BadOp ();
16709     }
16710   mnemonicendp = obufp;
16711 }
16712
16713 static struct op simd_cmp_op[] =
16714 {
16715   { STRING_COMMA_LEN ("eq") },
16716   { STRING_COMMA_LEN ("lt") },
16717   { STRING_COMMA_LEN ("le") },
16718   { STRING_COMMA_LEN ("unord") },
16719   { STRING_COMMA_LEN ("neq") },
16720   { STRING_COMMA_LEN ("nlt") },
16721   { STRING_COMMA_LEN ("nle") },
16722   { STRING_COMMA_LEN ("ord") }
16723 };
16724
16725 static void
16726 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16727 {
16728   unsigned int cmp_type;
16729
16730   FETCH_DATA (the_info, codep + 1);
16731   cmp_type = *codep++ & 0xff;
16732   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16733     {
16734       char suffix [3];
16735       char *p = mnemonicendp - 2;
16736       suffix[0] = p[0];
16737       suffix[1] = p[1];
16738       suffix[2] = '\0';
16739       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16740       mnemonicendp += simd_cmp_op[cmp_type].len;
16741     }
16742   else
16743     {
16744       /* We have a reserved extension byte.  Output it directly.  */
16745       scratchbuf[0] = '$';
16746       print_operand_value (scratchbuf + 1, 1, cmp_type);
16747       oappend_maybe_intel (scratchbuf);
16748       scratchbuf[0] = '\0';
16749     }
16750 }
16751
16752 static void
16753 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16754           int sizeflag ATTRIBUTE_UNUSED)
16755 {
16756   /* mwaitx %eax,%ecx,%ebx */
16757   if (!intel_syntax)
16758     {
16759       const char **names = (address_mode == mode_64bit
16760                             ? names64 : names32);
16761       strcpy (op_out[0], names[0]);
16762       strcpy (op_out[1], names[1]);
16763       strcpy (op_out[2], names[3]);
16764       two_source_ops = 1;
16765     }
16766   /* Skip mod/rm byte.  */
16767   MODRM_CHECK;
16768   codep++;
16769 }
16770
16771 static void
16772 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16773           int sizeflag ATTRIBUTE_UNUSED)
16774 {
16775   /* mwait %eax,%ecx  */
16776   if (!intel_syntax)
16777     {
16778       const char **names = (address_mode == mode_64bit
16779                             ? names64 : names32);
16780       strcpy (op_out[0], names[0]);
16781       strcpy (op_out[1], names[1]);
16782       two_source_ops = 1;
16783     }
16784   /* Skip mod/rm byte.  */
16785   MODRM_CHECK;
16786   codep++;
16787 }
16788
16789 static void
16790 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16791             int sizeflag ATTRIBUTE_UNUSED)
16792 {
16793   /* monitor %eax,%ecx,%edx"  */
16794   if (!intel_syntax)
16795     {
16796       const char **op1_names;
16797       const char **names = (address_mode == mode_64bit
16798                             ? names64 : names32);
16799
16800       if (!(prefixes & PREFIX_ADDR))
16801         op1_names = (address_mode == mode_16bit
16802                      ? names16 : names);
16803       else
16804         {
16805           /* Remove "addr16/addr32".  */
16806           all_prefixes[last_addr_prefix] = 0;
16807           op1_names = (address_mode != mode_32bit
16808                        ? names32 : names16);
16809           used_prefixes |= PREFIX_ADDR;
16810         }
16811       strcpy (op_out[0], op1_names[0]);
16812       strcpy (op_out[1], names[1]);
16813       strcpy (op_out[2], names[2]);
16814       two_source_ops = 1;
16815     }
16816   /* Skip mod/rm byte.  */
16817   MODRM_CHECK;
16818   codep++;
16819 }
16820
16821 static void
16822 BadOp (void)
16823 {
16824   /* Throw away prefixes and 1st. opcode byte.  */
16825   codep = insn_codep + 1;
16826   oappend ("(bad)");
16827 }
16828
16829 static void
16830 REP_Fixup (int bytemode, int sizeflag)
16831 {
16832   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16833      lods and stos.  */
16834   if (prefixes & PREFIX_REPZ)
16835     all_prefixes[last_repz_prefix] = REP_PREFIX;
16836
16837   switch (bytemode)
16838     {
16839     case al_reg:
16840     case eAX_reg:
16841     case indir_dx_reg:
16842       OP_IMREG (bytemode, sizeflag);
16843       break;
16844     case eDI_reg:
16845       OP_ESreg (bytemode, sizeflag);
16846       break;
16847     case eSI_reg:
16848       OP_DSreg (bytemode, sizeflag);
16849       break;
16850     default:
16851       abort ();
16852       break;
16853     }
16854 }
16855
16856 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16857    "bnd".  */
16858
16859 static void
16860 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16861 {
16862   if (prefixes & PREFIX_REPNZ)
16863     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16864 }
16865
16866 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16867    "notrack".  */
16868
16869 static void
16870 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16871                int sizeflag ATTRIBUTE_UNUSED)
16872 {
16873   if (active_seg_prefix == PREFIX_DS
16874       && (address_mode != mode_64bit || last_data_prefix < 0))
16875     {
16876       /* NOTRACK prefix is only valid on indirect branch instructions.
16877          NB: DATA prefix is unsupported for Intel64.  */
16878       active_seg_prefix = 0;
16879       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16880     }
16881 }
16882
16883 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16884    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16885  */
16886
16887 static void
16888 HLE_Fixup1 (int bytemode, int sizeflag)
16889 {
16890   if (modrm.mod != 3
16891       && (prefixes & PREFIX_LOCK) != 0)
16892     {
16893       if (prefixes & PREFIX_REPZ)
16894         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16895       if (prefixes & PREFIX_REPNZ)
16896         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16897     }
16898
16899   OP_E (bytemode, sizeflag);
16900 }
16901
16902 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16903    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16904  */
16905
16906 static void
16907 HLE_Fixup2 (int bytemode, int sizeflag)
16908 {
16909   if (modrm.mod != 3)
16910     {
16911       if (prefixes & PREFIX_REPZ)
16912         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16913       if (prefixes & PREFIX_REPNZ)
16914         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16915     }
16916
16917   OP_E (bytemode, sizeflag);
16918 }
16919
16920 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16921    "xrelease" for memory operand.  No check for LOCK prefix.   */
16922
16923 static void
16924 HLE_Fixup3 (int bytemode, int sizeflag)
16925 {
16926   if (modrm.mod != 3
16927       && last_repz_prefix > last_repnz_prefix
16928       && (prefixes & PREFIX_REPZ) != 0)
16929     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16930
16931   OP_E (bytemode, sizeflag);
16932 }
16933
16934 static void
16935 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16936 {
16937   USED_REX (REX_W);
16938   if (rex & REX_W)
16939     {
16940       /* Change cmpxchg8b to cmpxchg16b.  */
16941       char *p = mnemonicendp - 2;
16942       mnemonicendp = stpcpy (p, "16b");
16943       bytemode = o_mode;
16944     }
16945   else if ((prefixes & PREFIX_LOCK) != 0)
16946     {
16947       if (prefixes & PREFIX_REPZ)
16948         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16949       if (prefixes & PREFIX_REPNZ)
16950         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16951     }
16952
16953   OP_M (bytemode, sizeflag);
16954 }
16955
16956 static void
16957 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16958 {
16959   const char **names;
16960
16961   if (need_vex)
16962     {
16963       switch (vex.length)
16964         {
16965         case 128:
16966           names = names_xmm;
16967           break;
16968         case 256:
16969           names = names_ymm;
16970           break;
16971         default:
16972           abort ();
16973         }
16974     }
16975   else
16976     names = names_xmm;
16977   oappend (names[reg]);
16978 }
16979
16980 static void
16981 CRC32_Fixup (int bytemode, int sizeflag)
16982 {
16983   /* Add proper suffix to "crc32".  */
16984   char *p = mnemonicendp;
16985
16986   switch (bytemode)
16987     {
16988     case b_mode:
16989       if (intel_syntax)
16990         goto skip;
16991
16992       *p++ = 'b';
16993       break;
16994     case v_mode:
16995       if (intel_syntax)
16996         goto skip;
16997
16998       USED_REX (REX_W);
16999       if (rex & REX_W)
17000         *p++ = 'q';
17001       else
17002         {
17003           if (sizeflag & DFLAG)
17004             *p++ = 'l';
17005           else
17006             *p++ = 'w';
17007           used_prefixes |= (prefixes & PREFIX_DATA);
17008         }
17009       break;
17010     default:
17011       oappend (INTERNAL_DISASSEMBLER_ERROR);
17012       break;
17013     }
17014   mnemonicendp = p;
17015   *p = '\0';
17016
17017 skip:
17018   if (modrm.mod == 3)
17019     {
17020       int add;
17021
17022       /* Skip mod/rm byte.  */
17023       MODRM_CHECK;
17024       codep++;
17025
17026       USED_REX (REX_B);
17027       add = (rex & REX_B) ? 8 : 0;
17028       if (bytemode == b_mode)
17029         {
17030           USED_REX (0);
17031           if (rex)
17032             oappend (names8rex[modrm.rm + add]);
17033           else
17034             oappend (names8[modrm.rm + add]);
17035         }
17036       else
17037         {
17038           USED_REX (REX_W);
17039           if (rex & REX_W)
17040             oappend (names64[modrm.rm + add]);
17041           else if ((prefixes & PREFIX_DATA))
17042             oappend (names16[modrm.rm + add]);
17043           else
17044             oappend (names32[modrm.rm + add]);
17045         }
17046     }
17047   else
17048     OP_E (bytemode, sizeflag);
17049 }
17050
17051 static void
17052 FXSAVE_Fixup (int bytemode, int sizeflag)
17053 {
17054   /* Add proper suffix to "fxsave" and "fxrstor".  */
17055   USED_REX (REX_W);
17056   if (rex & REX_W)
17057     {
17058       char *p = mnemonicendp;
17059       *p++ = '6';
17060       *p++ = '4';
17061       *p = '\0';
17062       mnemonicendp = p;
17063     }
17064   OP_M (bytemode, sizeflag);
17065 }
17066
17067 static void
17068 PCMPESTR_Fixup (int bytemode, int sizeflag)
17069 {
17070   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
17071   if (!intel_syntax)
17072     {
17073       char *p = mnemonicendp;
17074
17075       USED_REX (REX_W);
17076       if (rex & REX_W)
17077         *p++ = 'q';
17078       else if (sizeflag & SUFFIX_ALWAYS)
17079         *p++ = 'l';
17080
17081       *p = '\0';
17082       mnemonicendp = p;
17083     }
17084
17085   OP_EX (bytemode, sizeflag);
17086 }
17087
17088 /* Display the destination register operand for instructions with
17089    VEX. */
17090
17091 static void
17092 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17093 {
17094   int reg;
17095   const char **names;
17096
17097   if (!need_vex)
17098     abort ();
17099
17100   if (!need_vex_reg)
17101     return;
17102
17103   reg = vex.register_specifier;
17104   if (address_mode != mode_64bit)
17105     reg &= 7;
17106   else if (vex.evex && !vex.v)
17107     reg += 16;
17108
17109   if (bytemode == vex_scalar_mode)
17110     {
17111       oappend (names_xmm[reg]);
17112       return;
17113     }
17114
17115   switch (vex.length)
17116     {
17117     case 128:
17118       switch (bytemode)
17119         {
17120         case vex_mode:
17121         case vex128_mode:
17122         case vex_vsib_q_w_dq_mode:
17123         case vex_vsib_q_w_d_mode:
17124           names = names_xmm;
17125           break;
17126         case dq_mode:
17127           if (rex & REX_W)
17128             names = names64;
17129           else
17130             names = names32;
17131           break;
17132         case mask_bd_mode:
17133         case mask_mode:
17134           if (reg > 0x7)
17135             {
17136               oappend ("(bad)");
17137               return;
17138             }
17139           names = names_mask;
17140           break;
17141         default:
17142           abort ();
17143           return;
17144         }
17145       break;
17146     case 256:
17147       switch (bytemode)
17148         {
17149         case vex_mode:
17150         case vex256_mode:
17151           names = names_ymm;
17152           break;
17153         case vex_vsib_q_w_dq_mode:
17154         case vex_vsib_q_w_d_mode:
17155           names = vex.w ? names_ymm : names_xmm;
17156           break;
17157         case mask_bd_mode:
17158         case mask_mode:
17159           if (reg > 0x7)
17160             {
17161               oappend ("(bad)");
17162               return;
17163             }
17164           names = names_mask;
17165           break;
17166         default:
17167           /* See PR binutils/20893 for a reproducer.  */
17168           oappend ("(bad)");
17169           return;
17170         }
17171       break;
17172     case 512:
17173       names = names_zmm;
17174       break;
17175     default:
17176       abort ();
17177       break;
17178     }
17179   oappend (names[reg]);
17180 }
17181
17182 /* Get the VEX immediate byte without moving codep.  */
17183
17184 static unsigned char
17185 get_vex_imm8 (int sizeflag, int opnum)
17186 {
17187   int bytes_before_imm = 0;
17188
17189   if (modrm.mod != 3)
17190     {
17191       /* There are SIB/displacement bytes.  */
17192       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17193         {
17194           /* 32/64 bit address mode */
17195           int base = modrm.rm;
17196
17197           /* Check SIB byte.  */
17198           if (base == 4)
17199             {
17200               FETCH_DATA (the_info, codep + 1);
17201               base = *codep & 7;
17202               /* When decoding the third source, don't increase
17203                  bytes_before_imm as this has already been incremented
17204                  by one in OP_E_memory while decoding the second
17205                  source operand.  */
17206               if (opnum == 0)
17207                 bytes_before_imm++;
17208             }
17209
17210           /* Don't increase bytes_before_imm when decoding the third source,
17211              it has already been incremented by OP_E_memory while decoding
17212              the second source operand.  */
17213           if (opnum == 0)
17214             {
17215               switch (modrm.mod)
17216                 {
17217                   case 0:
17218                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17219                        SIB == 5, there is a 4 byte displacement.  */
17220                     if (base != 5)
17221                       /* No displacement. */
17222                       break;
17223                     /* Fall through.  */
17224                   case 2:
17225                     /* 4 byte displacement.  */
17226                     bytes_before_imm += 4;
17227                     break;
17228                   case 1:
17229                     /* 1 byte displacement.  */
17230                     bytes_before_imm++;
17231                     break;
17232                 }
17233             }
17234         }
17235       else
17236         {
17237           /* 16 bit address mode */
17238           /* Don't increase bytes_before_imm when decoding the third source,
17239              it has already been incremented by OP_E_memory while decoding
17240              the second source operand.  */
17241           if (opnum == 0)
17242             {
17243               switch (modrm.mod)
17244                 {
17245                 case 0:
17246                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17247                   if (modrm.rm != 6)
17248                     /* No displacement. */
17249                     break;
17250                   /* Fall through.  */
17251                 case 2:
17252                   /* 2 byte displacement.  */
17253                   bytes_before_imm += 2;
17254                   break;
17255                 case 1:
17256                   /* 1 byte displacement: when decoding the third source,
17257                      don't increase bytes_before_imm as this has already
17258                      been incremented by one in OP_E_memory while decoding
17259                      the second source operand.  */
17260                   if (opnum == 0)
17261                     bytes_before_imm++;
17262
17263                   break;
17264                 }
17265             }
17266         }
17267     }
17268
17269   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17270   return codep [bytes_before_imm];
17271 }
17272
17273 static void
17274 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17275 {
17276   const char **names;
17277
17278   if (reg == -1 && modrm.mod != 3)
17279     {
17280       OP_E_memory (bytemode, sizeflag);
17281       return;
17282     }
17283   else
17284     {
17285       if (reg == -1)
17286         {
17287           reg = modrm.rm;
17288           USED_REX (REX_B);
17289           if (rex & REX_B)
17290             reg += 8;
17291         }
17292       if (address_mode != mode_64bit)
17293         reg &= 7;
17294     }
17295
17296   switch (vex.length)
17297     {
17298     case 128:
17299       names = names_xmm;
17300       break;
17301     case 256:
17302       names = names_ymm;
17303       break;
17304     default:
17305       abort ();
17306     }
17307   oappend (names[reg]);
17308 }
17309
17310 static void
17311 OP_EX_VexImmW (int bytemode, int sizeflag)
17312 {
17313   int reg = -1;
17314   static unsigned char vex_imm8;
17315
17316   if (vex_w_done == 0)
17317     {
17318       vex_w_done = 1;
17319
17320       /* Skip mod/rm byte.  */
17321       MODRM_CHECK;
17322       codep++;
17323
17324       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17325
17326       if (vex.w)
17327           reg = vex_imm8 >> 4;
17328
17329       OP_EX_VexReg (bytemode, sizeflag, reg);
17330     }
17331   else if (vex_w_done == 1)
17332     {
17333       vex_w_done = 2;
17334
17335       if (!vex.w)
17336           reg = vex_imm8 >> 4;
17337
17338       OP_EX_VexReg (bytemode, sizeflag, reg);
17339     }
17340   else
17341     {
17342       /* Output the imm8 directly.  */
17343       scratchbuf[0] = '$';
17344       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17345       oappend_maybe_intel (scratchbuf);
17346       scratchbuf[0] = '\0';
17347       codep++;
17348     }
17349 }
17350
17351 static void
17352 OP_Vex_2src (int bytemode, int sizeflag)
17353 {
17354   if (modrm.mod == 3)
17355     {
17356       int reg = modrm.rm;
17357       USED_REX (REX_B);
17358       if (rex & REX_B)
17359         reg += 8;
17360       oappend (names_xmm[reg]);
17361     }
17362   else
17363     {
17364       if (intel_syntax
17365           && (bytemode == v_mode || bytemode == v_swap_mode))
17366         {
17367           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17368           used_prefixes |= (prefixes & PREFIX_DATA);
17369         }
17370       OP_E (bytemode, sizeflag);
17371     }
17372 }
17373
17374 static void
17375 OP_Vex_2src_1 (int bytemode, int sizeflag)
17376 {
17377   if (modrm.mod == 3)
17378     {
17379       /* Skip mod/rm byte.   */
17380       MODRM_CHECK;
17381       codep++;
17382     }
17383
17384   if (vex.w)
17385     {
17386       unsigned int reg = vex.register_specifier;
17387
17388       if (address_mode != mode_64bit)
17389         reg &= 7;
17390       oappend (names_xmm[reg]);
17391     }
17392   else
17393     OP_Vex_2src (bytemode, sizeflag);
17394 }
17395
17396 static void
17397 OP_Vex_2src_2 (int bytemode, int sizeflag)
17398 {
17399   if (vex.w)
17400     OP_Vex_2src (bytemode, sizeflag);
17401   else
17402     {
17403       unsigned int reg = vex.register_specifier;
17404
17405       if (address_mode != mode_64bit)
17406         reg &= 7;
17407       oappend (names_xmm[reg]);
17408     }
17409 }
17410
17411 static void
17412 OP_EX_VexW (int bytemode, int sizeflag)
17413 {
17414   int reg = -1;
17415
17416   if (!vex_w_done)
17417     {
17418       /* Skip mod/rm byte.  */
17419       MODRM_CHECK;
17420       codep++;
17421
17422       if (vex.w)
17423         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17424     }
17425   else
17426     {
17427       if (!vex.w)
17428         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17429     }
17430
17431   OP_EX_VexReg (bytemode, sizeflag, reg);
17432
17433   if (vex_w_done)
17434     codep++;
17435   vex_w_done = 1;
17436 }
17437
17438 static void
17439 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17440 {
17441   int reg;
17442   const char **names;
17443
17444   FETCH_DATA (the_info, codep + 1);
17445   reg = *codep++;
17446
17447   if (bytemode != x_mode)
17448     abort ();
17449
17450   reg >>= 4;
17451   if (address_mode != mode_64bit)
17452     reg &= 7;
17453
17454   switch (vex.length)
17455     {
17456     case 128:
17457       names = names_xmm;
17458       break;
17459     case 256:
17460       names = names_ymm;
17461       break;
17462     default:
17463       abort ();
17464     }
17465   oappend (names[reg]);
17466 }
17467
17468 static void
17469 OP_XMM_VexW (int bytemode, int sizeflag)
17470 {
17471   /* Turn off the REX.W bit since it is used for swapping operands
17472      now.  */
17473   rex &= ~REX_W;
17474   OP_XMM (bytemode, sizeflag);
17475 }
17476
17477 static void
17478 OP_EX_Vex (int bytemode, int sizeflag)
17479 {
17480   if (modrm.mod != 3)
17481     {
17482       if (vex.register_specifier != 0)
17483         BadOp ();
17484       need_vex_reg = 0;
17485     }
17486   OP_EX (bytemode, sizeflag);
17487 }
17488
17489 static void
17490 OP_XMM_Vex (int bytemode, int sizeflag)
17491 {
17492   if (modrm.mod != 3)
17493     {
17494       if (vex.register_specifier != 0)
17495         BadOp ();
17496       need_vex_reg = 0;
17497     }
17498   OP_XMM (bytemode, sizeflag);
17499 }
17500
17501 static void
17502 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17503 {
17504   switch (vex.length)
17505     {
17506     case 128:
17507       mnemonicendp = stpcpy (obuf, "vzeroupper");
17508       break;
17509     case 256:
17510       mnemonicendp = stpcpy (obuf, "vzeroall");
17511       break;
17512     default:
17513       abort ();
17514     }
17515 }
17516
17517 static struct op vex_cmp_op[] =
17518 {
17519   { STRING_COMMA_LEN ("eq") },
17520   { STRING_COMMA_LEN ("lt") },
17521   { STRING_COMMA_LEN ("le") },
17522   { STRING_COMMA_LEN ("unord") },
17523   { STRING_COMMA_LEN ("neq") },
17524   { STRING_COMMA_LEN ("nlt") },
17525   { STRING_COMMA_LEN ("nle") },
17526   { STRING_COMMA_LEN ("ord") },
17527   { STRING_COMMA_LEN ("eq_uq") },
17528   { STRING_COMMA_LEN ("nge") },
17529   { STRING_COMMA_LEN ("ngt") },
17530   { STRING_COMMA_LEN ("false") },
17531   { STRING_COMMA_LEN ("neq_oq") },
17532   { STRING_COMMA_LEN ("ge") },
17533   { STRING_COMMA_LEN ("gt") },
17534   { STRING_COMMA_LEN ("true") },
17535   { STRING_COMMA_LEN ("eq_os") },
17536   { STRING_COMMA_LEN ("lt_oq") },
17537   { STRING_COMMA_LEN ("le_oq") },
17538   { STRING_COMMA_LEN ("unord_s") },
17539   { STRING_COMMA_LEN ("neq_us") },
17540   { STRING_COMMA_LEN ("nlt_uq") },
17541   { STRING_COMMA_LEN ("nle_uq") },
17542   { STRING_COMMA_LEN ("ord_s") },
17543   { STRING_COMMA_LEN ("eq_us") },
17544   { STRING_COMMA_LEN ("nge_uq") },
17545   { STRING_COMMA_LEN ("ngt_uq") },
17546   { STRING_COMMA_LEN ("false_os") },
17547   { STRING_COMMA_LEN ("neq_os") },
17548   { STRING_COMMA_LEN ("ge_oq") },
17549   { STRING_COMMA_LEN ("gt_oq") },
17550   { STRING_COMMA_LEN ("true_us") },
17551 };
17552
17553 static void
17554 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17555 {
17556   unsigned int cmp_type;
17557
17558   FETCH_DATA (the_info, codep + 1);
17559   cmp_type = *codep++ & 0xff;
17560   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17561     {
17562       char suffix [3];
17563       char *p = mnemonicendp - 2;
17564       suffix[0] = p[0];
17565       suffix[1] = p[1];
17566       suffix[2] = '\0';
17567       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17568       mnemonicendp += vex_cmp_op[cmp_type].len;
17569     }
17570   else
17571     {
17572       /* We have a reserved extension byte.  Output it directly.  */
17573       scratchbuf[0] = '$';
17574       print_operand_value (scratchbuf + 1, 1, cmp_type);
17575       oappend_maybe_intel (scratchbuf);
17576       scratchbuf[0] = '\0';
17577     }
17578 }
17579
17580 static void
17581 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17582              int sizeflag ATTRIBUTE_UNUSED)
17583 {
17584   unsigned int cmp_type;
17585
17586   if (!vex.evex)
17587     abort ();
17588
17589   FETCH_DATA (the_info, codep + 1);
17590   cmp_type = *codep++ & 0xff;
17591   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17592      If it's the case, print suffix, otherwise - print the immediate.  */
17593   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17594       && cmp_type != 3
17595       && cmp_type != 7)
17596     {
17597       char suffix [3];
17598       char *p = mnemonicendp - 2;
17599
17600       /* vpcmp* can have both one- and two-lettered suffix.  */
17601       if (p[0] == 'p')
17602         {
17603           p++;
17604           suffix[0] = p[0];
17605           suffix[1] = '\0';
17606         }
17607       else
17608         {
17609           suffix[0] = p[0];
17610           suffix[1] = p[1];
17611           suffix[2] = '\0';
17612         }
17613
17614       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17615       mnemonicendp += simd_cmp_op[cmp_type].len;
17616     }
17617   else
17618     {
17619       /* We have a reserved extension byte.  Output it directly.  */
17620       scratchbuf[0] = '$';
17621       print_operand_value (scratchbuf + 1, 1, cmp_type);
17622       oappend_maybe_intel (scratchbuf);
17623       scratchbuf[0] = '\0';
17624     }
17625 }
17626
17627 static const struct op xop_cmp_op[] =
17628 {
17629   { STRING_COMMA_LEN ("lt") },
17630   { STRING_COMMA_LEN ("le") },
17631   { STRING_COMMA_LEN ("gt") },
17632   { STRING_COMMA_LEN ("ge") },
17633   { STRING_COMMA_LEN ("eq") },
17634   { STRING_COMMA_LEN ("neq") },
17635   { STRING_COMMA_LEN ("false") },
17636   { STRING_COMMA_LEN ("true") }
17637 };
17638
17639 static void
17640 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
17641              int sizeflag ATTRIBUTE_UNUSED)
17642 {
17643   unsigned int cmp_type;
17644
17645   FETCH_DATA (the_info, codep + 1);
17646   cmp_type = *codep++ & 0xff;
17647   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
17648     {
17649       char suffix[3];
17650       char *p = mnemonicendp - 2;
17651
17652       /* vpcom* can have both one- and two-lettered suffix.  */
17653       if (p[0] == 'm')
17654         {
17655           p++;
17656           suffix[0] = p[0];
17657           suffix[1] = '\0';
17658         }
17659       else
17660         {
17661           suffix[0] = p[0];
17662           suffix[1] = p[1];
17663           suffix[2] = '\0';
17664         }
17665
17666       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
17667       mnemonicendp += xop_cmp_op[cmp_type].len;
17668     }
17669   else
17670     {
17671       /* We have a reserved extension byte.  Output it directly.  */
17672       scratchbuf[0] = '$';
17673       print_operand_value (scratchbuf + 1, 1, cmp_type);
17674       oappend_maybe_intel (scratchbuf);
17675       scratchbuf[0] = '\0';
17676     }
17677 }
17678
17679 static const struct op pclmul_op[] =
17680 {
17681   { STRING_COMMA_LEN ("lql") },
17682   { STRING_COMMA_LEN ("hql") },
17683   { STRING_COMMA_LEN ("lqh") },
17684   { STRING_COMMA_LEN ("hqh") }
17685 };
17686
17687 static void
17688 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17689               int sizeflag ATTRIBUTE_UNUSED)
17690 {
17691   unsigned int pclmul_type;
17692
17693   FETCH_DATA (the_info, codep + 1);
17694   pclmul_type = *codep++ & 0xff;
17695   switch (pclmul_type)
17696     {
17697     case 0x10:
17698       pclmul_type = 2;
17699       break;
17700     case 0x11:
17701       pclmul_type = 3;
17702       break;
17703     default:
17704       break;
17705     }
17706   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17707     {
17708       char suffix [4];
17709       char *p = mnemonicendp - 3;
17710       suffix[0] = p[0];
17711       suffix[1] = p[1];
17712       suffix[2] = p[2];
17713       suffix[3] = '\0';
17714       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17715       mnemonicendp += pclmul_op[pclmul_type].len;
17716     }
17717   else
17718     {
17719       /* We have a reserved extension byte.  Output it directly.  */
17720       scratchbuf[0] = '$';
17721       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17722       oappend_maybe_intel (scratchbuf);
17723       scratchbuf[0] = '\0';
17724     }
17725 }
17726
17727 static void
17728 MOVBE_Fixup (int bytemode, int sizeflag)
17729 {
17730   /* Add proper suffix to "movbe".  */
17731   char *p = mnemonicendp;
17732
17733   switch (bytemode)
17734     {
17735     case v_mode:
17736       if (intel_syntax)
17737         goto skip;
17738
17739       USED_REX (REX_W);
17740       if (sizeflag & SUFFIX_ALWAYS)
17741         {
17742           if (rex & REX_W)
17743             *p++ = 'q';
17744           else
17745             {
17746               if (sizeflag & DFLAG)
17747                 *p++ = 'l';
17748               else
17749                 *p++ = 'w';
17750               used_prefixes |= (prefixes & PREFIX_DATA);
17751             }
17752         }
17753       break;
17754     default:
17755       oappend (INTERNAL_DISASSEMBLER_ERROR);
17756       break;
17757     }
17758   mnemonicendp = p;
17759   *p = '\0';
17760
17761 skip:
17762   OP_M (bytemode, sizeflag);
17763 }
17764
17765 static void
17766 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17767 {
17768   int reg;
17769   const char **names;
17770
17771   /* Skip mod/rm byte.  */
17772   MODRM_CHECK;
17773   codep++;
17774
17775   if (rex & REX_W)
17776     names = names64;
17777   else
17778     names = names32;
17779
17780   reg = modrm.rm;
17781   USED_REX (REX_B);
17782   if (rex & REX_B)
17783     reg += 8;
17784
17785   oappend (names[reg]);
17786 }
17787
17788 static void
17789 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17790 {
17791   const char **names;
17792   unsigned int reg = vex.register_specifier;
17793
17794   if (rex & REX_W)
17795     names = names64;
17796   else
17797     names = names32;
17798
17799   if (address_mode != mode_64bit)
17800     reg &= 7;
17801   oappend (names[reg]);
17802 }
17803
17804 static void
17805 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17806 {
17807   if (!vex.evex
17808       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17809     abort ();
17810
17811   USED_REX (REX_R);
17812   if ((rex & REX_R) != 0 || !vex.r)
17813     {
17814       BadOp ();
17815       return;
17816     }
17817
17818   oappend (names_mask [modrm.reg]);
17819 }
17820
17821 static void
17822 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17823 {
17824   if (!vex.evex
17825       || (bytemode != evex_rounding_mode
17826           && bytemode != evex_sae_mode))
17827     abort ();
17828   if (modrm.mod == 3 && vex.b)
17829     switch (bytemode)
17830       {
17831       case evex_rounding_mode:
17832         oappend (names_rounding[vex.ll]);
17833         break;
17834       case evex_sae_mode:
17835         oappend ("{sae}");
17836         break;
17837       default:
17838         break;
17839       }
17840 }