opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2017 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Ev_bnd { OP_E, v_bnd_mode }
 253 #define EvS { OP_E, v_swap_mode }
 254 #define Ed { OP_E, d_mode }
 255 #define Edq { OP_E, dq_mode }
 256 #define Edqw { OP_E, dqw_mode }
 257 #define Edqb { OP_E, dqb_mode }
 258 #define Edb { OP_E, db_mode }
 259 #define Edw { OP_E, dw_mode }
 260 #define Edqd { OP_E, dqd_mode }
 261 #define Eq { OP_E, q_mode }
 262 #define indirEv { OP_indirE, indir_v_mode }
 263 #define indirEp { OP_indirE, f_mode }
 264 #define stackEv { OP_E, stack_v_mode }
 265 #define Em { OP_E, m_mode }
 266 #define Ew { OP_E, w_mode }
 267 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 268 #define Ma { OP_M, a_mode }
 269 #define Mb { OP_M, b_mode }
 270 #define Md { OP_M, d_mode }
 271 #define Mo { OP_M, o_mode }
 272 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 273 #define Mq { OP_M, q_mode }
 274 #define Mx { OP_M, x_mode }
 275 #define Mxmm { OP_M, xmm_mode }
 276 #define Gb { OP_G, b_mode }
 277 #define Gbnd { OP_G, bnd_mode }
 278 #define Gv { OP_G, v_mode }
 279 #define Gd { OP_G, d_mode }
 280 #define Gdq { OP_G, dq_mode }
 281 #define Gm { OP_G, m_mode }
 282 #define Gw { OP_G, w_mode }
 283 #define Rd { OP_R, d_mode }
 284 #define Rdq { OP_R, dq_mode }
 285 #define Rm { OP_R, m_mode }
 286 #define Ib { OP_I, b_mode }
 287 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 288 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 289 #define Iv { OP_I, v_mode }
 290 #define sIv { OP_sI, v_mode }
 291 #define Iq { OP_I, q_mode }
 292 #define Iv64 { OP_I64, v_mode }
 293 #define Iw { OP_I, w_mode }
 294 #define I1 { OP_I, const_1_mode }
 295 #define Jb { OP_J, b_mode }
 296 #define Jv { OP_J, v_mode }
 297 #define Cm { OP_C, m_mode }
 298 #define Dm { OP_D, m_mode }
 299 #define Td { OP_T, d_mode }
 300 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 301
 302 #define RMeAX { OP_REG, eAX_reg }
 303 #define RMeBX { OP_REG, eBX_reg }
 304 #define RMeCX { OP_REG, eCX_reg }
 305 #define RMeDX { OP_REG, eDX_reg }
 306 #define RMeSP { OP_REG, eSP_reg }
 307 #define RMeBP { OP_REG, eBP_reg }
 308 #define RMeSI { OP_REG, eSI_reg }
 309 #define RMeDI { OP_REG, eDI_reg }
 310 #define RMrAX { OP_REG, rAX_reg }
 311 #define RMrBX { OP_REG, rBX_reg }
 312 #define RMrCX { OP_REG, rCX_reg }
 313 #define RMrDX { OP_REG, rDX_reg }
 314 #define RMrSP { OP_REG, rSP_reg }
 315 #define RMrBP { OP_REG, rBP_reg }
 316 #define RMrSI { OP_REG, rSI_reg }
 317 #define RMrDI { OP_REG, rDI_reg }
 318 #define RMAL { OP_REG, al_reg }
 319 #define RMCL { OP_REG, cl_reg }
 320 #define RMDL { OP_REG, dl_reg }
 321 #define RMBL { OP_REG, bl_reg }
 322 #define RMAH { OP_REG, ah_reg }
 323 #define RMCH { OP_REG, ch_reg }
 324 #define RMDH { OP_REG, dh_reg }
 325 #define RMBH { OP_REG, bh_reg }
 326 #define RMAX { OP_REG, ax_reg }
 327 #define RMDX { OP_REG, dx_reg }
 328
 329 #define eAX { OP_IMREG, eAX_reg }
 330 #define eBX { OP_IMREG, eBX_reg }
 331 #define eCX { OP_IMREG, eCX_reg }
 332 #define eDX { OP_IMREG, eDX_reg }
 333 #define eSP { OP_IMREG, eSP_reg }
 334 #define eBP { OP_IMREG, eBP_reg }
 335 #define eSI { OP_IMREG, eSI_reg }
 336 #define eDI { OP_IMREG, eDI_reg }
 337 #define AL { OP_IMREG, al_reg }
 338 #define CL { OP_IMREG, cl_reg }
 339 #define DL { OP_IMREG, dl_reg }
 340 #define BL { OP_IMREG, bl_reg }
 341 #define AH { OP_IMREG, ah_reg }
 342 #define CH { OP_IMREG, ch_reg }
 343 #define DH { OP_IMREG, dh_reg }
 344 #define BH { OP_IMREG, bh_reg }
 345 #define AX { OP_IMREG, ax_reg }
 346 #define DX { OP_IMREG, dx_reg }
 347 #define zAX { OP_IMREG, z_mode_ax_reg }
 348 #define indirDX { OP_IMREG, indir_dx_reg }
 349
 350 #define Sw { OP_SEG, w_mode }
 351 #define Sv { OP_SEG, v_mode }
 352 #define Ap { OP_DIR, 0 }
 353 #define Ob { OP_OFF64, b_mode }
 354 #define Ov { OP_OFF64, v_mode }
 355 #define Xb { OP_DSreg, eSI_reg }
 356 #define Xv { OP_DSreg, eSI_reg }
 357 #define Xz { OP_DSreg, eSI_reg }
 358 #define Yb { OP_ESreg, eDI_reg }
 359 #define Yv { OP_ESreg, eDI_reg }
 360 #define DSBX { OP_DSreg, eBX_reg }
 361
 362 #define es { OP_REG, es_reg }
 363 #define ss { OP_REG, ss_reg }
 364 #define cs { OP_REG, cs_reg }
 365 #define ds { OP_REG, ds_reg }
 366 #define fs { OP_REG, fs_reg }
 367 #define gs { OP_REG, gs_reg }
 368
 369 #define MX { OP_MMX, 0 }
 370 #define XM { OP_XMM, 0 }
 371 #define XMScalar { OP_XMM, scalar_mode }
 372 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 373 #define XMM { OP_XMM, xmm_mode }
 374 #define XMxmmq { OP_XMM, xmmq_mode }
 375 #define EM { OP_EM, v_mode }
 376 #define EMS { OP_EM, v_swap_mode }
 377 #define EMd { OP_EM, d_mode }
 378 #define EMx { OP_EM, x_mode }
 379 #define EXw { OP_EX, w_mode }
 380 #define EXd { OP_EX, d_mode }
 381 #define EXdScalar { OP_EX, d_scalar_mode }
 382 #define EXdS { OP_EX, d_swap_mode }
 383 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 384 #define EXq { OP_EX, q_mode }
 385 #define EXqScalar { OP_EX, q_scalar_mode }
 386 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 387 #define EXqS { OP_EX, q_swap_mode }
 388 #define EXx { OP_EX, x_mode }
 389 #define EXxS { OP_EX, x_swap_mode }
 390 #define EXxmm { OP_EX, xmm_mode }
 391 #define EXymm { OP_EX, ymm_mode }
 392 #define EXxmmq { OP_EX, xmmq_mode }
 393 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 394 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 395 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 396 #define EXxmm_md { OP_EX, xmm_md_mode }
 397 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 398 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 399 #define EXxmmdw { OP_EX, xmmdw_mode }
 400 #define EXxmmqd { OP_EX, xmmqd_mode }
 401 #define EXymmq { OP_EX, ymmq_mode }
 402 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 403 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 404 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 405 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 406 #define MS { OP_MS, v_mode }
 407 #define XS { OP_XS, v_mode }
 408 #define EMCq { OP_EMC, q_mode }
 409 #define MXC { OP_MXC, 0 }
 410 #define OPSUF { OP_3DNowSuffix, 0 }
 411 #define CMP { CMP_Fixup, 0 }
 412 #define XMM0 { XMM_Fixup, 0 }
 413 #define FXSAVE { FXSAVE_Fixup, 0 }
 414 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 415 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 416
 417 #define Vex { OP_VEX, vex_mode }
 418 #define VexScalar { OP_VEX, vex_scalar_mode }
 419 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 420 #define Vex128 { OP_VEX, vex128_mode }
 421 #define Vex256 { OP_VEX, vex256_mode }
 422 #define VexGdq { OP_VEX, dq_mode }
 423 #define VexI4 { VEXI4_Fixup, 0}
 424 #define EXdVex { OP_EX_Vex, d_mode }
 425 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 426 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 427 #define EXqVex { OP_EX_Vex, q_mode }
 428 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 429 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 430 #define EXVexW { OP_EX_VexW, x_mode }
 431 #define EXdVexW { OP_EX_VexW, d_mode }
 432 #define EXqVexW { OP_EX_VexW, q_mode }
 433 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 434 #define XMVex { OP_XMM_Vex, 0 }
 435 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 436 #define XMVexW { OP_XMM_VexW, 0 }
 437 #define XMVexI4 { OP_REG_VexI4, x_mode }
 438 #define PCLMUL { PCLMUL_Fixup, 0 }
 439 #define VZERO { VZERO_Fixup, 0 }
 440 #define VCMP { VCMP_Fixup, 0 }
 441 #define VPCMP { VPCMP_Fixup, 0 }
 442
 443 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 444 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 445
 446 #define XMask { OP_Mask, mask_mode }
 447 #define MaskG { OP_G, mask_mode }
 448 #define MaskE { OP_E, mask_mode }
 449 #define MaskBDE { OP_E, mask_bd_mode }
 450 #define MaskR { OP_R, mask_mode }
 451 #define MaskVex { OP_VEX, mask_mode }
 452
 453 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 454 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 455 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 456 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 457
 458 /* Used handle "rep" prefix for string instructions.  */
 459 #define Xbr { REP_Fixup, eSI_reg }
 460 #define Xvr { REP_Fixup, eSI_reg }
 461 #define Ybr { REP_Fixup, eDI_reg }
 462 #define Yvr { REP_Fixup, eDI_reg }
 463 #define Yzr { REP_Fixup, eDI_reg }
 464 #define indirDXr { REP_Fixup, indir_dx_reg }
 465 #define ALr { REP_Fixup, al_reg }
 466 #define eAXr { REP_Fixup, eAX_reg }
 467
 468 /* Used handle HLE prefix for lockable instructions.  */
 469 #define Ebh1 { HLE_Fixup1, b_mode }
 470 #define Evh1 { HLE_Fixup1, v_mode }
 471 #define Ebh2 { HLE_Fixup2, b_mode }
 472 #define Evh2 { HLE_Fixup2, v_mode }
 473 #define Ebh3 { HLE_Fixup3, b_mode }
 474 #define Evh3 { HLE_Fixup3, v_mode }
 475
 476 #define BND { BND_Fixup, 0 }
 477 #define NOTRACK { NOTRACK_Fixup, 0 }
 478
 479 #define cond_jump_flag { NULL, cond_jump_mode }
 480 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 481
 482 /* bits in sizeflag */
 483 #define SUFFIX_ALWAYS 4
 484 #define AFLAG 2
 485 #define DFLAG 1
 486
 487 enum
 488 {
 489   /* byte operand */
 490   b_mode = 1,
 491   /* byte operand with operand swapped */
 492   b_swap_mode,
 493   /* byte operand, sign extend like 'T' suffix */
 494   b_T_mode,
 495   /* operand size depends on prefixes */
 496   v_mode,
 497   /* operand size depends on prefixes with operand swapped */
 498   v_swap_mode,
 499   /* word operand */
 500   w_mode,
 501   /* double word operand  */
 502   d_mode,
 503   /* double word operand with operand swapped */
 504   d_swap_mode,
 505   /* quad word operand */
 506   q_mode,
 507   /* quad word operand with operand swapped */
 508   q_swap_mode,
 509   /* ten-byte operand */
 510   t_mode,
 511   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 512      broadcast enabled.  */
 513   x_mode,
 514   /* Similar to x_mode, but with different EVEX mem shifts.  */
 515   evex_x_gscat_mode,
 516   /* Similar to x_mode, but with disabled broadcast.  */
 517   evex_x_nobcst_mode,
 518   /* Similar to x_mode, but with operands swapped and disabled broadcast
 519      in EVEX.  */
 520   x_swap_mode,
 521   /* 16-byte XMM operand */
 522   xmm_mode,
 523   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 524      memory operand (depending on vector length).  Broadcast isn't
 525      allowed.  */
 526   xmmq_mode,
 527   /* Same as xmmq_mode, but broadcast is allowed.  */
 528   evex_half_bcst_xmmq_mode,
 529   /* XMM register or byte memory operand */
 530   xmm_mb_mode,
 531   /* XMM register or word memory operand */
 532   xmm_mw_mode,
 533   /* XMM register or double word memory operand */
 534   xmm_md_mode,
 535   /* XMM register or quad word memory operand */
 536   xmm_mq_mode,
 537   /* XMM register or double/quad word memory operand, depending on
 538      VEX.W.  */
 539   xmm_mdq_mode,
 540   /* 16-byte XMM, word, double word or quad word operand.  */
 541   xmmdw_mode,
 542   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 543   xmmqd_mode,
 544   /* 32-byte YMM operand */
 545   ymm_mode,
 546   /* quad word, ymmword or zmmword memory operand.  */
 547   ymmq_mode,
 548   /* 32-byte YMM or 16-byte word operand */
 549   ymmxmm_mode,
 550   /* d_mode in 32bit, q_mode in 64bit mode.  */
 551   m_mode,
 552   /* pair of v_mode operands */
 553   a_mode,
 554   cond_jump_mode,
 555   loop_jcxz_mode,
 556   v_bnd_mode,
 557   /* operand size depends on REX prefixes.  */
 558   dq_mode,
 559   /* registers like dq_mode, memory like w_mode.  */
 560   dqw_mode,
 561   bnd_mode,
 562   /* 4- or 6-byte pointer operand */
 563   f_mode,
 564   const_1_mode,
 565   /* v_mode for indirect branch opcodes.  */
 566   indir_v_mode,
 567   /* v_mode for stack-related opcodes.  */
 568   stack_v_mode,
 569   /* non-quad operand size depends on prefixes */
 570   z_mode,
 571   /* 16-byte operand */
 572   o_mode,
 573   /* registers like dq_mode, memory like b_mode.  */
 574   dqb_mode,
 575   /* registers like d_mode, memory like b_mode.  */
 576   db_mode,
 577   /* registers like d_mode, memory like w_mode.  */
 578   dw_mode,
 579   /* registers like dq_mode, memory like d_mode.  */
 580   dqd_mode,
 581   /* normal vex mode */
 582   vex_mode,
 583   /* 128bit vex mode */
 584   vex128_mode,
 585   /* 256bit vex mode */
 586   vex256_mode,
 587   /* operand size depends on the VEX.W bit.  */
 588   vex_w_dq_mode,
 589
 590   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 591   vex_vsib_d_w_dq_mode,
 592   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 593   vex_vsib_d_w_d_mode,
 594   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 595   vex_vsib_q_w_dq_mode,
 596   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 597   vex_vsib_q_w_d_mode,
 598
 599   /* scalar, ignore vector length.  */
 600   scalar_mode,
 601   /* like d_mode, ignore vector length.  */
 602   d_scalar_mode,
 603   /* like d_swap_mode, ignore vector length.  */
 604   d_scalar_swap_mode,
 605   /* like q_mode, ignore vector length.  */
 606   q_scalar_mode,
 607   /* like q_swap_mode, ignore vector length.  */
 608   q_scalar_swap_mode,
 609   /* like vex_mode, ignore vector length.  */
 610   vex_scalar_mode,
 611   /* like vex_w_dq_mode, ignore vector length.  */
 612   vex_scalar_w_dq_mode,
 613
 614   /* Static rounding.  */
 615   evex_rounding_mode,
 616   /* Supress all exceptions.  */
 617   evex_sae_mode,
 618
 619   /* Mask register operand.  */
 620   mask_mode,
 621   /* Mask register operand.  */
 622   mask_bd_mode,
 623
 624   es_reg,
 625   cs_reg,
 626   ss_reg,
 627   ds_reg,
 628   fs_reg,
 629   gs_reg,
 630
 631   eAX_reg,
 632   eCX_reg,
 633   eDX_reg,
 634   eBX_reg,
 635   eSP_reg,
 636   eBP_reg,
 637   eSI_reg,
 638   eDI_reg,
 639
 640   al_reg,
 641   cl_reg,
 642   dl_reg,
 643   bl_reg,
 644   ah_reg,
 645   ch_reg,
 646   dh_reg,
 647   bh_reg,
 648
 649   ax_reg,
 650   cx_reg,
 651   dx_reg,
 652   bx_reg,
 653   sp_reg,
 654   bp_reg,
 655   si_reg,
 656   di_reg,
 657
 658   rAX_reg,
 659   rCX_reg,
 660   rDX_reg,
 661   rBX_reg,
 662   rSP_reg,
 663   rBP_reg,
 664   rSI_reg,
 665   rDI_reg,
 666
 667   z_mode_ax_reg,
 668   indir_dx_reg
 669 };
 670
 671 enum
 672 {
 673   FLOATCODE = 1,
 674   USE_REG_TABLE,
 675   USE_MOD_TABLE,
 676   USE_RM_TABLE,
 677   USE_PREFIX_TABLE,
 678   USE_X86_64_TABLE,
 679   USE_3BYTE_TABLE,
 680   USE_XOP_8F_TABLE,
 681   USE_VEX_C4_TABLE,
 682   USE_VEX_C5_TABLE,
 683   USE_VEX_LEN_TABLE,
 684   USE_VEX_W_TABLE,
 685   USE_EVEX_TABLE
 686 };
 687
 688 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 689
 690 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 691 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 692 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 693 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 694 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 695 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 696 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 697 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 698 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 699 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 700 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 701 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 702 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 703 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 704 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 705
 706 enum
 707 {
 708   REG_80 = 0,
 709   REG_81,
 710   REG_83,
 711   REG_8F,
 712   REG_C0,
 713   REG_C1,
 714   REG_C6,
 715   REG_C7,
 716   REG_D0,
 717   REG_D1,
 718   REG_D2,
 719   REG_D3,
 720   REG_F6,
 721   REG_F7,
 722   REG_FE,
 723   REG_FF,
 724   REG_0F00,
 725   REG_0F01,
 726   REG_0F0D,
 727   REG_0F18,
 728   REG_0F1E_MOD_3,
 729   REG_0F71,
 730   REG_0F72,
 731   REG_0F73,
 732   REG_0FA6,
 733   REG_0FA7,
 734   REG_0FAE,
 735   REG_0FBA,
 736   REG_0FC7,
 737   REG_VEX_0F71,
 738   REG_VEX_0F72,
 739   REG_VEX_0F73,
 740   REG_VEX_0FAE,
 741   REG_VEX_0F38F3,
 742   REG_XOP_LWPCB,
 743   REG_XOP_LWP,
 744   REG_XOP_TBM_01,
 745   REG_XOP_TBM_02,
 746
 747   REG_EVEX_0F71,
 748   REG_EVEX_0F72,
 749   REG_EVEX_0F73,
 750   REG_EVEX_0F38C6,
 751   REG_EVEX_0F38C7
 752 };
 753
 754 enum
 755 {
 756   MOD_8D = 0,
 757   MOD_C6_REG_7,
 758   MOD_C7_REG_7,
 759   MOD_FF_REG_3,
 760   MOD_FF_REG_5,
 761   MOD_0F01_REG_0,
 762   MOD_0F01_REG_1,
 763   MOD_0F01_REG_2,
 764   MOD_0F01_REG_3,
 765   MOD_0F01_REG_5,
 766   MOD_0F01_REG_7,
 767   MOD_0F12_PREFIX_0,
 768   MOD_0F13,
 769   MOD_0F16_PREFIX_0,
 770   MOD_0F17,
 771   MOD_0F18_REG_0,
 772   MOD_0F18_REG_1,
 773   MOD_0F18_REG_2,
 774   MOD_0F18_REG_3,
 775   MOD_0F18_REG_4,
 776   MOD_0F18_REG_5,
 777   MOD_0F18_REG_6,
 778   MOD_0F18_REG_7,
 779   MOD_0F1A_PREFIX_0,
 780   MOD_0F1B_PREFIX_0,
 781   MOD_0F1B_PREFIX_1,
 782   MOD_0F1E_PREFIX_1,
 783   MOD_0F24,
 784   MOD_0F26,
 785   MOD_0F2B_PREFIX_0,
 786   MOD_0F2B_PREFIX_1,
 787   MOD_0F2B_PREFIX_2,
 788   MOD_0F2B_PREFIX_3,
 789   MOD_0F51,
 790   MOD_0F71_REG_2,
 791   MOD_0F71_REG_4,
 792   MOD_0F71_REG_6,
 793   MOD_0F72_REG_2,
 794   MOD_0F72_REG_4,
 795   MOD_0F72_REG_6,
 796   MOD_0F73_REG_2,
 797   MOD_0F73_REG_3,
 798   MOD_0F73_REG_6,
 799   MOD_0F73_REG_7,
 800   MOD_0FAE_REG_0,
 801   MOD_0FAE_REG_1,
 802   MOD_0FAE_REG_2,
 803   MOD_0FAE_REG_3,
 804   MOD_0FAE_REG_4,
 805   MOD_0FAE_REG_5,
 806   MOD_0FAE_REG_6,
 807   MOD_0FAE_REG_7,
 808   MOD_0FB2,
 809   MOD_0FB4,
 810   MOD_0FB5,
 811   MOD_0FC3,
 812   MOD_0FC7_REG_3,
 813   MOD_0FC7_REG_4,
 814   MOD_0FC7_REG_5,
 815   MOD_0FC7_REG_6,
 816   MOD_0FC7_REG_7,
 817   MOD_0FD7,
 818   MOD_0FE7_PREFIX_2,
 819   MOD_0FF0_PREFIX_3,
 820   MOD_0F382A_PREFIX_2,
 821   MOD_0F38F5_PREFIX_2,
 822   MOD_0F38F6_PREFIX_0,
 823   MOD_62_32BIT,
 824   MOD_C4_32BIT,
 825   MOD_C5_32BIT,
 826   MOD_VEX_0F12_PREFIX_0,
 827   MOD_VEX_0F13,
 828   MOD_VEX_0F16_PREFIX_0,
 829   MOD_VEX_0F17,
 830   MOD_VEX_0F2B,
 831   MOD_VEX_W_0_0F41_P_0_LEN_1,
 832   MOD_VEX_W_1_0F41_P_0_LEN_1,
 833   MOD_VEX_W_0_0F41_P_2_LEN_1,
 834   MOD_VEX_W_1_0F41_P_2_LEN_1,
 835   MOD_VEX_W_0_0F42_P_0_LEN_1,
 836   MOD_VEX_W_1_0F42_P_0_LEN_1,
 837   MOD_VEX_W_0_0F42_P_2_LEN_1,
 838   MOD_VEX_W_1_0F42_P_2_LEN_1,
 839   MOD_VEX_W_0_0F44_P_0_LEN_1,
 840   MOD_VEX_W_1_0F44_P_0_LEN_1,
 841   MOD_VEX_W_0_0F44_P_2_LEN_1,
 842   MOD_VEX_W_1_0F44_P_2_LEN_1,
 843   MOD_VEX_W_0_0F45_P_0_LEN_1,
 844   MOD_VEX_W_1_0F45_P_0_LEN_1,
 845   MOD_VEX_W_0_0F45_P_2_LEN_1,
 846   MOD_VEX_W_1_0F45_P_2_LEN_1,
 847   MOD_VEX_W_0_0F46_P_0_LEN_1,
 848   MOD_VEX_W_1_0F46_P_0_LEN_1,
 849   MOD_VEX_W_0_0F46_P_2_LEN_1,
 850   MOD_VEX_W_1_0F46_P_2_LEN_1,
 851   MOD_VEX_W_0_0F47_P_0_LEN_1,
 852   MOD_VEX_W_1_0F47_P_0_LEN_1,
 853   MOD_VEX_W_0_0F47_P_2_LEN_1,
 854   MOD_VEX_W_1_0F47_P_2_LEN_1,
 855   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 856   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 857   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 858   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 859   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 860   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 861   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 862   MOD_VEX_0F50,
 863   MOD_VEX_0F71_REG_2,
 864   MOD_VEX_0F71_REG_4,
 865   MOD_VEX_0F71_REG_6,
 866   MOD_VEX_0F72_REG_2,
 867   MOD_VEX_0F72_REG_4,
 868   MOD_VEX_0F72_REG_6,
 869   MOD_VEX_0F73_REG_2,
 870   MOD_VEX_0F73_REG_3,
 871   MOD_VEX_0F73_REG_6,
 872   MOD_VEX_0F73_REG_7,
 873   MOD_VEX_W_0_0F91_P_0_LEN_0,
 874   MOD_VEX_W_1_0F91_P_0_LEN_0,
 875   MOD_VEX_W_0_0F91_P_2_LEN_0,
 876   MOD_VEX_W_1_0F91_P_2_LEN_0,
 877   MOD_VEX_W_0_0F92_P_0_LEN_0,
 878   MOD_VEX_W_0_0F92_P_2_LEN_0,
 879   MOD_VEX_W_0_0F92_P_3_LEN_0,
 880   MOD_VEX_W_1_0F92_P_3_LEN_0,
 881   MOD_VEX_W_0_0F93_P_0_LEN_0,
 882   MOD_VEX_W_0_0F93_P_2_LEN_0,
 883   MOD_VEX_W_0_0F93_P_3_LEN_0,
 884   MOD_VEX_W_1_0F93_P_3_LEN_0,
 885   MOD_VEX_W_0_0F98_P_0_LEN_0,
 886   MOD_VEX_W_1_0F98_P_0_LEN_0,
 887   MOD_VEX_W_0_0F98_P_2_LEN_0,
 888   MOD_VEX_W_1_0F98_P_2_LEN_0,
 889   MOD_VEX_W_0_0F99_P_0_LEN_0,
 890   MOD_VEX_W_1_0F99_P_0_LEN_0,
 891   MOD_VEX_W_0_0F99_P_2_LEN_0,
 892   MOD_VEX_W_1_0F99_P_2_LEN_0,
 893   MOD_VEX_0FAE_REG_2,
 894   MOD_VEX_0FAE_REG_3,
 895   MOD_VEX_0FD7_PREFIX_2,
 896   MOD_VEX_0FE7_PREFIX_2,
 897   MOD_VEX_0FF0_PREFIX_3,
 898   MOD_VEX_0F381A_PREFIX_2,
 899   MOD_VEX_0F382A_PREFIX_2,
 900   MOD_VEX_0F382C_PREFIX_2,
 901   MOD_VEX_0F382D_PREFIX_2,
 902   MOD_VEX_0F382E_PREFIX_2,
 903   MOD_VEX_0F382F_PREFIX_2,
 904   MOD_VEX_0F385A_PREFIX_2,
 905   MOD_VEX_0F388C_PREFIX_2,
 906   MOD_VEX_0F388E_PREFIX_2,
 907   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 908   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 909   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 910   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 911   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 912   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 913   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 914   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 915
 916   MOD_EVEX_0F10_PREFIX_1,
 917   MOD_EVEX_0F10_PREFIX_3,
 918   MOD_EVEX_0F11_PREFIX_1,
 919   MOD_EVEX_0F11_PREFIX_3,
 920   MOD_EVEX_0F12_PREFIX_0,
 921   MOD_EVEX_0F16_PREFIX_0,
 922   MOD_EVEX_0F38C6_REG_1,
 923   MOD_EVEX_0F38C6_REG_2,
 924   MOD_EVEX_0F38C6_REG_5,
 925   MOD_EVEX_0F38C6_REG_6,
 926   MOD_EVEX_0F38C7_REG_1,
 927   MOD_EVEX_0F38C7_REG_2,
 928   MOD_EVEX_0F38C7_REG_5,
 929   MOD_EVEX_0F38C7_REG_6
 930 };
 931
 932 enum
 933 {
 934   RM_C6_REG_7 = 0,
 935   RM_C7_REG_7,
 936   RM_0F01_REG_0,
 937   RM_0F01_REG_1,
 938   RM_0F01_REG_2,
 939   RM_0F01_REG_3,
 940   RM_0F01_REG_5,
 941   RM_0F01_REG_7,
 942   RM_0F1E_MOD_3_REG_7,
 943   RM_0FAE_REG_6,
 944   RM_0FAE_REG_7
 945 };
 946
 947 enum
 948 {
 949   PREFIX_90 = 0,
 950   PREFIX_MOD_0_0F01_REG_5,
 951   PREFIX_MOD_3_0F01_REG_5_RM_0,
 952   PREFIX_MOD_3_0F01_REG_5_RM_2,
 953   PREFIX_0F10,
 954   PREFIX_0F11,
 955   PREFIX_0F12,
 956   PREFIX_0F16,
 957   PREFIX_0F1A,
 958   PREFIX_0F1B,
 959   PREFIX_0F1E,
 960   PREFIX_0F2A,
 961   PREFIX_0F2B,
 962   PREFIX_0F2C,
 963   PREFIX_0F2D,
 964   PREFIX_0F2E,
 965   PREFIX_0F2F,
 966   PREFIX_0F51,
 967   PREFIX_0F52,
 968   PREFIX_0F53,
 969   PREFIX_0F58,
 970   PREFIX_0F59,
 971   PREFIX_0F5A,
 972   PREFIX_0F5B,
 973   PREFIX_0F5C,
 974   PREFIX_0F5D,
 975   PREFIX_0F5E,
 976   PREFIX_0F5F,
 977   PREFIX_0F60,
 978   PREFIX_0F61,
 979   PREFIX_0F62,
 980   PREFIX_0F6C,
 981   PREFIX_0F6D,
 982   PREFIX_0F6F,
 983   PREFIX_0F70,
 984   PREFIX_0F73_REG_3,
 985   PREFIX_0F73_REG_7,
 986   PREFIX_0F78,
 987   PREFIX_0F79,
 988   PREFIX_0F7C,
 989   PREFIX_0F7D,
 990   PREFIX_0F7E,
 991   PREFIX_0F7F,
 992   PREFIX_0FAE_REG_0,
 993   PREFIX_0FAE_REG_1,
 994   PREFIX_0FAE_REG_2,
 995   PREFIX_0FAE_REG_3,
 996   PREFIX_MOD_0_0FAE_REG_4,
 997   PREFIX_MOD_3_0FAE_REG_4,
 998   PREFIX_MOD_0_0FAE_REG_5,
 999   PREFIX_MOD_3_0FAE_REG_5,
1000   PREFIX_0FAE_REG_6,
1001   PREFIX_0FAE_REG_7,
1002   PREFIX_0FB8,
1003   PREFIX_0FBC,
1004   PREFIX_0FBD,
1005   PREFIX_0FC2,
1006   PREFIX_MOD_0_0FC3,
1007   PREFIX_MOD_0_0FC7_REG_6,
1008   PREFIX_MOD_3_0FC7_REG_6,
1009   PREFIX_MOD_3_0FC7_REG_7,
1010   PREFIX_0FD0,
1011   PREFIX_0FD6,
1012   PREFIX_0FE6,
1013   PREFIX_0FE7,
1014   PREFIX_0FF0,
1015   PREFIX_0FF7,
1016   PREFIX_0F3810,
1017   PREFIX_0F3814,
1018   PREFIX_0F3815,
1019   PREFIX_0F3817,
1020   PREFIX_0F3820,
1021   PREFIX_0F3821,
1022   PREFIX_0F3822,
1023   PREFIX_0F3823,
1024   PREFIX_0F3824,
1025   PREFIX_0F3825,
1026   PREFIX_0F3828,
1027   PREFIX_0F3829,
1028   PREFIX_0F382A,
1029   PREFIX_0F382B,
1030   PREFIX_0F3830,
1031   PREFIX_0F3831,
1032   PREFIX_0F3832,
1033   PREFIX_0F3833,
1034   PREFIX_0F3834,
1035   PREFIX_0F3835,
1036   PREFIX_0F3837,
1037   PREFIX_0F3838,
1038   PREFIX_0F3839,
1039   PREFIX_0F383A,
1040   PREFIX_0F383B,
1041   PREFIX_0F383C,
1042   PREFIX_0F383D,
1043   PREFIX_0F383E,
1044   PREFIX_0F383F,
1045   PREFIX_0F3840,
1046   PREFIX_0F3841,
1047   PREFIX_0F3880,
1048   PREFIX_0F3881,
1049   PREFIX_0F3882,
1050   PREFIX_0F38C8,
1051   PREFIX_0F38C9,
1052   PREFIX_0F38CA,
1053   PREFIX_0F38CB,
1054   PREFIX_0F38CC,
1055   PREFIX_0F38CD,
1056   PREFIX_0F38DB,
1057   PREFIX_0F38DC,
1058   PREFIX_0F38DD,
1059   PREFIX_0F38DE,
1060   PREFIX_0F38DF,
1061   PREFIX_0F38F0,
1062   PREFIX_0F38F1,
1063   PREFIX_0F38F5,
1064   PREFIX_0F38F6,
1065   PREFIX_0F3A08,
1066   PREFIX_0F3A09,
1067   PREFIX_0F3A0A,
1068   PREFIX_0F3A0B,
1069   PREFIX_0F3A0C,
1070   PREFIX_0F3A0D,
1071   PREFIX_0F3A0E,
1072   PREFIX_0F3A14,
1073   PREFIX_0F3A15,
1074   PREFIX_0F3A16,
1075   PREFIX_0F3A17,
1076   PREFIX_0F3A20,
1077   PREFIX_0F3A21,
1078   PREFIX_0F3A22,
1079   PREFIX_0F3A40,
1080   PREFIX_0F3A41,
1081   PREFIX_0F3A42,
1082   PREFIX_0F3A44,
1083   PREFIX_0F3A60,
1084   PREFIX_0F3A61,
1085   PREFIX_0F3A62,
1086   PREFIX_0F3A63,
1087   PREFIX_0F3ACC,
1088   PREFIX_0F3ADF,
1089   PREFIX_VEX_0F10,
1090   PREFIX_VEX_0F11,
1091   PREFIX_VEX_0F12,
1092   PREFIX_VEX_0F16,
1093   PREFIX_VEX_0F2A,
1094   PREFIX_VEX_0F2C,
1095   PREFIX_VEX_0F2D,
1096   PREFIX_VEX_0F2E,
1097   PREFIX_VEX_0F2F,
1098   PREFIX_VEX_0F41,
1099   PREFIX_VEX_0F42,
1100   PREFIX_VEX_0F44,
1101   PREFIX_VEX_0F45,
1102   PREFIX_VEX_0F46,
1103   PREFIX_VEX_0F47,
1104   PREFIX_VEX_0F4A,
1105   PREFIX_VEX_0F4B,
1106   PREFIX_VEX_0F51,
1107   PREFIX_VEX_0F52,
1108   PREFIX_VEX_0F53,
1109   PREFIX_VEX_0F58,
1110   PREFIX_VEX_0F59,
1111   PREFIX_VEX_0F5A,
1112   PREFIX_VEX_0F5B,
1113   PREFIX_VEX_0F5C,
1114   PREFIX_VEX_0F5D,
1115   PREFIX_VEX_0F5E,
1116   PREFIX_VEX_0F5F,
1117   PREFIX_VEX_0F60,
1118   PREFIX_VEX_0F61,
1119   PREFIX_VEX_0F62,
1120   PREFIX_VEX_0F63,
1121   PREFIX_VEX_0F64,
1122   PREFIX_VEX_0F65,
1123   PREFIX_VEX_0F66,
1124   PREFIX_VEX_0F67,
1125   PREFIX_VEX_0F68,
1126   PREFIX_VEX_0F69,
1127   PREFIX_VEX_0F6A,
1128   PREFIX_VEX_0F6B,
1129   PREFIX_VEX_0F6C,
1130   PREFIX_VEX_0F6D,
1131   PREFIX_VEX_0F6E,
1132   PREFIX_VEX_0F6F,
1133   PREFIX_VEX_0F70,
1134   PREFIX_VEX_0F71_REG_2,
1135   PREFIX_VEX_0F71_REG_4,
1136   PREFIX_VEX_0F71_REG_6,
1137   PREFIX_VEX_0F72_REG_2,
1138   PREFIX_VEX_0F72_REG_4,
1139   PREFIX_VEX_0F72_REG_6,
1140   PREFIX_VEX_0F73_REG_2,
1141   PREFIX_VEX_0F73_REG_3,
1142   PREFIX_VEX_0F73_REG_6,
1143   PREFIX_VEX_0F73_REG_7,
1144   PREFIX_VEX_0F74,
1145   PREFIX_VEX_0F75,
1146   PREFIX_VEX_0F76,
1147   PREFIX_VEX_0F77,
1148   PREFIX_VEX_0F7C,
1149   PREFIX_VEX_0F7D,
1150   PREFIX_VEX_0F7E,
1151   PREFIX_VEX_0F7F,
1152   PREFIX_VEX_0F90,
1153   PREFIX_VEX_0F91,
1154   PREFIX_VEX_0F92,
1155   PREFIX_VEX_0F93,
1156   PREFIX_VEX_0F98,
1157   PREFIX_VEX_0F99,
1158   PREFIX_VEX_0FC2,
1159   PREFIX_VEX_0FC4,
1160   PREFIX_VEX_0FC5,
1161   PREFIX_VEX_0FD0,
1162   PREFIX_VEX_0FD1,
1163   PREFIX_VEX_0FD2,
1164   PREFIX_VEX_0FD3,
1165   PREFIX_VEX_0FD4,
1166   PREFIX_VEX_0FD5,
1167   PREFIX_VEX_0FD6,
1168   PREFIX_VEX_0FD7,
1169   PREFIX_VEX_0FD8,
1170   PREFIX_VEX_0FD9,
1171   PREFIX_VEX_0FDA,
1172   PREFIX_VEX_0FDB,
1173   PREFIX_VEX_0FDC,
1174   PREFIX_VEX_0FDD,
1175   PREFIX_VEX_0FDE,
1176   PREFIX_VEX_0FDF,
1177   PREFIX_VEX_0FE0,
1178   PREFIX_VEX_0FE1,
1179   PREFIX_VEX_0FE2,
1180   PREFIX_VEX_0FE3,
1181   PREFIX_VEX_0FE4,
1182   PREFIX_VEX_0FE5,
1183   PREFIX_VEX_0FE6,
1184   PREFIX_VEX_0FE7,
1185   PREFIX_VEX_0FE8,
1186   PREFIX_VEX_0FE9,
1187   PREFIX_VEX_0FEA,
1188   PREFIX_VEX_0FEB,
1189   PREFIX_VEX_0FEC,
1190   PREFIX_VEX_0FED,
1191   PREFIX_VEX_0FEE,
1192   PREFIX_VEX_0FEF,
1193   PREFIX_VEX_0FF0,
1194   PREFIX_VEX_0FF1,
1195   PREFIX_VEX_0FF2,
1196   PREFIX_VEX_0FF3,
1197   PREFIX_VEX_0FF4,
1198   PREFIX_VEX_0FF5,
1199   PREFIX_VEX_0FF6,
1200   PREFIX_VEX_0FF7,
1201   PREFIX_VEX_0FF8,
1202   PREFIX_VEX_0FF9,
1203   PREFIX_VEX_0FFA,
1204   PREFIX_VEX_0FFB,
1205   PREFIX_VEX_0FFC,
1206   PREFIX_VEX_0FFD,
1207   PREFIX_VEX_0FFE,
1208   PREFIX_VEX_0F3800,
1209   PREFIX_VEX_0F3801,
1210   PREFIX_VEX_0F3802,
1211   PREFIX_VEX_0F3803,
1212   PREFIX_VEX_0F3804,
1213   PREFIX_VEX_0F3805,
1214   PREFIX_VEX_0F3806,
1215   PREFIX_VEX_0F3807,
1216   PREFIX_VEX_0F3808,
1217   PREFIX_VEX_0F3809,
1218   PREFIX_VEX_0F380A,
1219   PREFIX_VEX_0F380B,
1220   PREFIX_VEX_0F380C,
1221   PREFIX_VEX_0F380D,
1222   PREFIX_VEX_0F380E,
1223   PREFIX_VEX_0F380F,
1224   PREFIX_VEX_0F3813,
1225   PREFIX_VEX_0F3816,
1226   PREFIX_VEX_0F3817,
1227   PREFIX_VEX_0F3818,
1228   PREFIX_VEX_0F3819,
1229   PREFIX_VEX_0F381A,
1230   PREFIX_VEX_0F381C,
1231   PREFIX_VEX_0F381D,
1232   PREFIX_VEX_0F381E,
1233   PREFIX_VEX_0F3820,
1234   PREFIX_VEX_0F3821,
1235   PREFIX_VEX_0F3822,
1236   PREFIX_VEX_0F3823,
1237   PREFIX_VEX_0F3824,
1238   PREFIX_VEX_0F3825,
1239   PREFIX_VEX_0F3828,
1240   PREFIX_VEX_0F3829,
1241   PREFIX_VEX_0F382A,
1242   PREFIX_VEX_0F382B,
1243   PREFIX_VEX_0F382C,
1244   PREFIX_VEX_0F382D,
1245   PREFIX_VEX_0F382E,
1246   PREFIX_VEX_0F382F,
1247   PREFIX_VEX_0F3830,
1248   PREFIX_VEX_0F3831,
1249   PREFIX_VEX_0F3832,
1250   PREFIX_VEX_0F3833,
1251   PREFIX_VEX_0F3834,
1252   PREFIX_VEX_0F3835,
1253   PREFIX_VEX_0F3836,
1254   PREFIX_VEX_0F3837,
1255   PREFIX_VEX_0F3838,
1256   PREFIX_VEX_0F3839,
1257   PREFIX_VEX_0F383A,
1258   PREFIX_VEX_0F383B,
1259   PREFIX_VEX_0F383C,
1260   PREFIX_VEX_0F383D,
1261   PREFIX_VEX_0F383E,
1262   PREFIX_VEX_0F383F,
1263   PREFIX_VEX_0F3840,
1264   PREFIX_VEX_0F3841,
1265   PREFIX_VEX_0F3845,
1266   PREFIX_VEX_0F3846,
1267   PREFIX_VEX_0F3847,
1268   PREFIX_VEX_0F3858,
1269   PREFIX_VEX_0F3859,
1270   PREFIX_VEX_0F385A,
1271   PREFIX_VEX_0F3878,
1272   PREFIX_VEX_0F3879,
1273   PREFIX_VEX_0F388C,
1274   PREFIX_VEX_0F388E,
1275   PREFIX_VEX_0F3890,
1276   PREFIX_VEX_0F3891,
1277   PREFIX_VEX_0F3892,
1278   PREFIX_VEX_0F3893,
1279   PREFIX_VEX_0F3896,
1280   PREFIX_VEX_0F3897,
1281   PREFIX_VEX_0F3898,
1282   PREFIX_VEX_0F3899,
1283   PREFIX_VEX_0F389A,
1284   PREFIX_VEX_0F389B,
1285   PREFIX_VEX_0F389C,
1286   PREFIX_VEX_0F389D,
1287   PREFIX_VEX_0F389E,
1288   PREFIX_VEX_0F389F,
1289   PREFIX_VEX_0F38A6,
1290   PREFIX_VEX_0F38A7,
1291   PREFIX_VEX_0F38A8,
1292   PREFIX_VEX_0F38A9,
1293   PREFIX_VEX_0F38AA,
1294   PREFIX_VEX_0F38AB,
1295   PREFIX_VEX_0F38AC,
1296   PREFIX_VEX_0F38AD,
1297   PREFIX_VEX_0F38AE,
1298   PREFIX_VEX_0F38AF,
1299   PREFIX_VEX_0F38B6,
1300   PREFIX_VEX_0F38B7,
1301   PREFIX_VEX_0F38B8,
1302   PREFIX_VEX_0F38B9,
1303   PREFIX_VEX_0F38BA,
1304   PREFIX_VEX_0F38BB,
1305   PREFIX_VEX_0F38BC,
1306   PREFIX_VEX_0F38BD,
1307   PREFIX_VEX_0F38BE,
1308   PREFIX_VEX_0F38BF,
1309   PREFIX_VEX_0F38DB,
1310   PREFIX_VEX_0F38DC,
1311   PREFIX_VEX_0F38DD,
1312   PREFIX_VEX_0F38DE,
1313   PREFIX_VEX_0F38DF,
1314   PREFIX_VEX_0F38F2,
1315   PREFIX_VEX_0F38F3_REG_1,
1316   PREFIX_VEX_0F38F3_REG_2,
1317   PREFIX_VEX_0F38F3_REG_3,
1318   PREFIX_VEX_0F38F5,
1319   PREFIX_VEX_0F38F6,
1320   PREFIX_VEX_0F38F7,
1321   PREFIX_VEX_0F3A00,
1322   PREFIX_VEX_0F3A01,
1323   PREFIX_VEX_0F3A02,
1324   PREFIX_VEX_0F3A04,
1325   PREFIX_VEX_0F3A05,
1326   PREFIX_VEX_0F3A06,
1327   PREFIX_VEX_0F3A08,
1328   PREFIX_VEX_0F3A09,
1329   PREFIX_VEX_0F3A0A,
1330   PREFIX_VEX_0F3A0B,
1331   PREFIX_VEX_0F3A0C,
1332   PREFIX_VEX_0F3A0D,
1333   PREFIX_VEX_0F3A0E,
1334   PREFIX_VEX_0F3A0F,
1335   PREFIX_VEX_0F3A14,
1336   PREFIX_VEX_0F3A15,
1337   PREFIX_VEX_0F3A16,
1338   PREFIX_VEX_0F3A17,
1339   PREFIX_VEX_0F3A18,
1340   PREFIX_VEX_0F3A19,
1341   PREFIX_VEX_0F3A1D,
1342   PREFIX_VEX_0F3A20,
1343   PREFIX_VEX_0F3A21,
1344   PREFIX_VEX_0F3A22,
1345   PREFIX_VEX_0F3A30,
1346   PREFIX_VEX_0F3A31,
1347   PREFIX_VEX_0F3A32,
1348   PREFIX_VEX_0F3A33,
1349   PREFIX_VEX_0F3A38,
1350   PREFIX_VEX_0F3A39,
1351   PREFIX_VEX_0F3A40,
1352   PREFIX_VEX_0F3A41,
1353   PREFIX_VEX_0F3A42,
1354   PREFIX_VEX_0F3A44,
1355   PREFIX_VEX_0F3A46,
1356   PREFIX_VEX_0F3A48,
1357   PREFIX_VEX_0F3A49,
1358   PREFIX_VEX_0F3A4A,
1359   PREFIX_VEX_0F3A4B,
1360   PREFIX_VEX_0F3A4C,
1361   PREFIX_VEX_0F3A5C,
1362   PREFIX_VEX_0F3A5D,
1363   PREFIX_VEX_0F3A5E,
1364   PREFIX_VEX_0F3A5F,
1365   PREFIX_VEX_0F3A60,
1366   PREFIX_VEX_0F3A61,
1367   PREFIX_VEX_0F3A62,
1368   PREFIX_VEX_0F3A63,
1369   PREFIX_VEX_0F3A68,
1370   PREFIX_VEX_0F3A69,
1371   PREFIX_VEX_0F3A6A,
1372   PREFIX_VEX_0F3A6B,
1373   PREFIX_VEX_0F3A6C,
1374   PREFIX_VEX_0F3A6D,
1375   PREFIX_VEX_0F3A6E,
1376   PREFIX_VEX_0F3A6F,
1377   PREFIX_VEX_0F3A78,
1378   PREFIX_VEX_0F3A79,
1379   PREFIX_VEX_0F3A7A,
1380   PREFIX_VEX_0F3A7B,
1381   PREFIX_VEX_0F3A7C,
1382   PREFIX_VEX_0F3A7D,
1383   PREFIX_VEX_0F3A7E,
1384   PREFIX_VEX_0F3A7F,
1385   PREFIX_VEX_0F3ADF,
1386   PREFIX_VEX_0F3AF0,
1387
1388   PREFIX_EVEX_0F10,
1389   PREFIX_EVEX_0F11,
1390   PREFIX_EVEX_0F12,
1391   PREFIX_EVEX_0F13,
1392   PREFIX_EVEX_0F14,
1393   PREFIX_EVEX_0F15,
1394   PREFIX_EVEX_0F16,
1395   PREFIX_EVEX_0F17,
1396   PREFIX_EVEX_0F28,
1397   PREFIX_EVEX_0F29,
1398   PREFIX_EVEX_0F2A,
1399   PREFIX_EVEX_0F2B,
1400   PREFIX_EVEX_0F2C,
1401   PREFIX_EVEX_0F2D,
1402   PREFIX_EVEX_0F2E,
1403   PREFIX_EVEX_0F2F,
1404   PREFIX_EVEX_0F51,
1405   PREFIX_EVEX_0F54,
1406   PREFIX_EVEX_0F55,
1407   PREFIX_EVEX_0F56,
1408   PREFIX_EVEX_0F57,
1409   PREFIX_EVEX_0F58,
1410   PREFIX_EVEX_0F59,
1411   PREFIX_EVEX_0F5A,
1412   PREFIX_EVEX_0F5B,
1413   PREFIX_EVEX_0F5C,
1414   PREFIX_EVEX_0F5D,
1415   PREFIX_EVEX_0F5E,
1416   PREFIX_EVEX_0F5F,
1417   PREFIX_EVEX_0F60,
1418   PREFIX_EVEX_0F61,
1419   PREFIX_EVEX_0F62,
1420   PREFIX_EVEX_0F63,
1421   PREFIX_EVEX_0F64,
1422   PREFIX_EVEX_0F65,
1423   PREFIX_EVEX_0F66,
1424   PREFIX_EVEX_0F67,
1425   PREFIX_EVEX_0F68,
1426   PREFIX_EVEX_0F69,
1427   PREFIX_EVEX_0F6A,
1428   PREFIX_EVEX_0F6B,
1429   PREFIX_EVEX_0F6C,
1430   PREFIX_EVEX_0F6D,
1431   PREFIX_EVEX_0F6E,
1432   PREFIX_EVEX_0F6F,
1433   PREFIX_EVEX_0F70,
1434   PREFIX_EVEX_0F71_REG_2,
1435   PREFIX_EVEX_0F71_REG_4,
1436   PREFIX_EVEX_0F71_REG_6,
1437   PREFIX_EVEX_0F72_REG_0,
1438   PREFIX_EVEX_0F72_REG_1,
1439   PREFIX_EVEX_0F72_REG_2,
1440   PREFIX_EVEX_0F72_REG_4,
1441   PREFIX_EVEX_0F72_REG_6,
1442   PREFIX_EVEX_0F73_REG_2,
1443   PREFIX_EVEX_0F73_REG_3,
1444   PREFIX_EVEX_0F73_REG_6,
1445   PREFIX_EVEX_0F73_REG_7,
1446   PREFIX_EVEX_0F74,
1447   PREFIX_EVEX_0F75,
1448   PREFIX_EVEX_0F76,
1449   PREFIX_EVEX_0F78,
1450   PREFIX_EVEX_0F79,
1451   PREFIX_EVEX_0F7A,
1452   PREFIX_EVEX_0F7B,
1453   PREFIX_EVEX_0F7E,
1454   PREFIX_EVEX_0F7F,
1455   PREFIX_EVEX_0FC2,
1456   PREFIX_EVEX_0FC4,
1457   PREFIX_EVEX_0FC5,
1458   PREFIX_EVEX_0FC6,
1459   PREFIX_EVEX_0FD1,
1460   PREFIX_EVEX_0FD2,
1461   PREFIX_EVEX_0FD3,
1462   PREFIX_EVEX_0FD4,
1463   PREFIX_EVEX_0FD5,
1464   PREFIX_EVEX_0FD6,
1465   PREFIX_EVEX_0FD8,
1466   PREFIX_EVEX_0FD9,
1467   PREFIX_EVEX_0FDA,
1468   PREFIX_EVEX_0FDB,
1469   PREFIX_EVEX_0FDC,
1470   PREFIX_EVEX_0FDD,
1471   PREFIX_EVEX_0FDE,
1472   PREFIX_EVEX_0FDF,
1473   PREFIX_EVEX_0FE0,
1474   PREFIX_EVEX_0FE1,
1475   PREFIX_EVEX_0FE2,
1476   PREFIX_EVEX_0FE3,
1477   PREFIX_EVEX_0FE4,
1478   PREFIX_EVEX_0FE5,
1479   PREFIX_EVEX_0FE6,
1480   PREFIX_EVEX_0FE7,
1481   PREFIX_EVEX_0FE8,
1482   PREFIX_EVEX_0FE9,
1483   PREFIX_EVEX_0FEA,
1484   PREFIX_EVEX_0FEB,
1485   PREFIX_EVEX_0FEC,
1486   PREFIX_EVEX_0FED,
1487   PREFIX_EVEX_0FEE,
1488   PREFIX_EVEX_0FEF,
1489   PREFIX_EVEX_0FF1,
1490   PREFIX_EVEX_0FF2,
1491   PREFIX_EVEX_0FF3,
1492   PREFIX_EVEX_0FF4,
1493   PREFIX_EVEX_0FF5,
1494   PREFIX_EVEX_0FF6,
1495   PREFIX_EVEX_0FF8,
1496   PREFIX_EVEX_0FF9,
1497   PREFIX_EVEX_0FFA,
1498   PREFIX_EVEX_0FFB,
1499   PREFIX_EVEX_0FFC,
1500   PREFIX_EVEX_0FFD,
1501   PREFIX_EVEX_0FFE,
1502   PREFIX_EVEX_0F3800,
1503   PREFIX_EVEX_0F3804,
1504   PREFIX_EVEX_0F380B,
1505   PREFIX_EVEX_0F380C,
1506   PREFIX_EVEX_0F380D,
1507   PREFIX_EVEX_0F3810,
1508   PREFIX_EVEX_0F3811,
1509   PREFIX_EVEX_0F3812,
1510   PREFIX_EVEX_0F3813,
1511   PREFIX_EVEX_0F3814,
1512   PREFIX_EVEX_0F3815,
1513   PREFIX_EVEX_0F3816,
1514   PREFIX_EVEX_0F3818,
1515   PREFIX_EVEX_0F3819,
1516   PREFIX_EVEX_0F381A,
1517   PREFIX_EVEX_0F381B,
1518   PREFIX_EVEX_0F381C,
1519   PREFIX_EVEX_0F381D,
1520   PREFIX_EVEX_0F381E,
1521   PREFIX_EVEX_0F381F,
1522   PREFIX_EVEX_0F3820,
1523   PREFIX_EVEX_0F3821,
1524   PREFIX_EVEX_0F3822,
1525   PREFIX_EVEX_0F3823,
1526   PREFIX_EVEX_0F3824,
1527   PREFIX_EVEX_0F3825,
1528   PREFIX_EVEX_0F3826,
1529   PREFIX_EVEX_0F3827,
1530   PREFIX_EVEX_0F3828,
1531   PREFIX_EVEX_0F3829,
1532   PREFIX_EVEX_0F382A,
1533   PREFIX_EVEX_0F382B,
1534   PREFIX_EVEX_0F382C,
1535   PREFIX_EVEX_0F382D,
1536   PREFIX_EVEX_0F3830,
1537   PREFIX_EVEX_0F3831,
1538   PREFIX_EVEX_0F3832,
1539   PREFIX_EVEX_0F3833,
1540   PREFIX_EVEX_0F3834,
1541   PREFIX_EVEX_0F3835,
1542   PREFIX_EVEX_0F3836,
1543   PREFIX_EVEX_0F3837,
1544   PREFIX_EVEX_0F3838,
1545   PREFIX_EVEX_0F3839,
1546   PREFIX_EVEX_0F383A,
1547   PREFIX_EVEX_0F383B,
1548   PREFIX_EVEX_0F383C,
1549   PREFIX_EVEX_0F383D,
1550   PREFIX_EVEX_0F383E,
1551   PREFIX_EVEX_0F383F,
1552   PREFIX_EVEX_0F3840,
1553   PREFIX_EVEX_0F3842,
1554   PREFIX_EVEX_0F3843,
1555   PREFIX_EVEX_0F3844,
1556   PREFIX_EVEX_0F3845,
1557   PREFIX_EVEX_0F3846,
1558   PREFIX_EVEX_0F3847,
1559   PREFIX_EVEX_0F384C,
1560   PREFIX_EVEX_0F384D,
1561   PREFIX_EVEX_0F384E,
1562   PREFIX_EVEX_0F384F,
1563   PREFIX_EVEX_0F3852,
1564   PREFIX_EVEX_0F3853,
1565   PREFIX_EVEX_0F3855,
1566   PREFIX_EVEX_0F3858,
1567   PREFIX_EVEX_0F3859,
1568   PREFIX_EVEX_0F385A,
1569   PREFIX_EVEX_0F385B,
1570   PREFIX_EVEX_0F3864,
1571   PREFIX_EVEX_0F3865,
1572   PREFIX_EVEX_0F3866,
1573   PREFIX_EVEX_0F3875,
1574   PREFIX_EVEX_0F3876,
1575   PREFIX_EVEX_0F3877,
1576   PREFIX_EVEX_0F3878,
1577   PREFIX_EVEX_0F3879,
1578   PREFIX_EVEX_0F387A,
1579   PREFIX_EVEX_0F387B,
1580   PREFIX_EVEX_0F387C,
1581   PREFIX_EVEX_0F387D,
1582   PREFIX_EVEX_0F387E,
1583   PREFIX_EVEX_0F387F,
1584   PREFIX_EVEX_0F3883,
1585   PREFIX_EVEX_0F3888,
1586   PREFIX_EVEX_0F3889,
1587   PREFIX_EVEX_0F388A,
1588   PREFIX_EVEX_0F388B,
1589   PREFIX_EVEX_0F388D,
1590   PREFIX_EVEX_0F3890,
1591   PREFIX_EVEX_0F3891,
1592   PREFIX_EVEX_0F3892,
1593   PREFIX_EVEX_0F3893,
1594   PREFIX_EVEX_0F3896,
1595   PREFIX_EVEX_0F3897,
1596   PREFIX_EVEX_0F3898,
1597   PREFIX_EVEX_0F3899,
1598   PREFIX_EVEX_0F389A,
1599   PREFIX_EVEX_0F389B,
1600   PREFIX_EVEX_0F389C,
1601   PREFIX_EVEX_0F389D,
1602   PREFIX_EVEX_0F389E,
1603   PREFIX_EVEX_0F389F,
1604   PREFIX_EVEX_0F38A0,
1605   PREFIX_EVEX_0F38A1,
1606   PREFIX_EVEX_0F38A2,
1607   PREFIX_EVEX_0F38A3,
1608   PREFIX_EVEX_0F38A6,
1609   PREFIX_EVEX_0F38A7,
1610   PREFIX_EVEX_0F38A8,
1611   PREFIX_EVEX_0F38A9,
1612   PREFIX_EVEX_0F38AA,
1613   PREFIX_EVEX_0F38AB,
1614   PREFIX_EVEX_0F38AC,
1615   PREFIX_EVEX_0F38AD,
1616   PREFIX_EVEX_0F38AE,
1617   PREFIX_EVEX_0F38AF,
1618   PREFIX_EVEX_0F38B4,
1619   PREFIX_EVEX_0F38B5,
1620   PREFIX_EVEX_0F38B6,
1621   PREFIX_EVEX_0F38B7,
1622   PREFIX_EVEX_0F38B8,
1623   PREFIX_EVEX_0F38B9,
1624   PREFIX_EVEX_0F38BA,
1625   PREFIX_EVEX_0F38BB,
1626   PREFIX_EVEX_0F38BC,
1627   PREFIX_EVEX_0F38BD,
1628   PREFIX_EVEX_0F38BE,
1629   PREFIX_EVEX_0F38BF,
1630   PREFIX_EVEX_0F38C4,
1631   PREFIX_EVEX_0F38C6_REG_1,
1632   PREFIX_EVEX_0F38C6_REG_2,
1633   PREFIX_EVEX_0F38C6_REG_5,
1634   PREFIX_EVEX_0F38C6_REG_6,
1635   PREFIX_EVEX_0F38C7_REG_1,
1636   PREFIX_EVEX_0F38C7_REG_2,
1637   PREFIX_EVEX_0F38C7_REG_5,
1638   PREFIX_EVEX_0F38C7_REG_6,
1639   PREFIX_EVEX_0F38C8,
1640   PREFIX_EVEX_0F38CA,
1641   PREFIX_EVEX_0F38CB,
1642   PREFIX_EVEX_0F38CC,
1643   PREFIX_EVEX_0F38CD,
1644
1645   PREFIX_EVEX_0F3A00,
1646   PREFIX_EVEX_0F3A01,
1647   PREFIX_EVEX_0F3A03,
1648   PREFIX_EVEX_0F3A04,
1649   PREFIX_EVEX_0F3A05,
1650   PREFIX_EVEX_0F3A08,
1651   PREFIX_EVEX_0F3A09,
1652   PREFIX_EVEX_0F3A0A,
1653   PREFIX_EVEX_0F3A0B,
1654   PREFIX_EVEX_0F3A0F,
1655   PREFIX_EVEX_0F3A14,
1656   PREFIX_EVEX_0F3A15,
1657   PREFIX_EVEX_0F3A16,
1658   PREFIX_EVEX_0F3A17,
1659   PREFIX_EVEX_0F3A18,
1660   PREFIX_EVEX_0F3A19,
1661   PREFIX_EVEX_0F3A1A,
1662   PREFIX_EVEX_0F3A1B,
1663   PREFIX_EVEX_0F3A1D,
1664   PREFIX_EVEX_0F3A1E,
1665   PREFIX_EVEX_0F3A1F,
1666   PREFIX_EVEX_0F3A20,
1667   PREFIX_EVEX_0F3A21,
1668   PREFIX_EVEX_0F3A22,
1669   PREFIX_EVEX_0F3A23,
1670   PREFIX_EVEX_0F3A25,
1671   PREFIX_EVEX_0F3A26,
1672   PREFIX_EVEX_0F3A27,
1673   PREFIX_EVEX_0F3A38,
1674   PREFIX_EVEX_0F3A39,
1675   PREFIX_EVEX_0F3A3A,
1676   PREFIX_EVEX_0F3A3B,
1677   PREFIX_EVEX_0F3A3E,
1678   PREFIX_EVEX_0F3A3F,
1679   PREFIX_EVEX_0F3A42,
1680   PREFIX_EVEX_0F3A43,
1681   PREFIX_EVEX_0F3A50,
1682   PREFIX_EVEX_0F3A51,
1683   PREFIX_EVEX_0F3A54,
1684   PREFIX_EVEX_0F3A55,
1685   PREFIX_EVEX_0F3A56,
1686   PREFIX_EVEX_0F3A57,
1687   PREFIX_EVEX_0F3A66,
1688   PREFIX_EVEX_0F3A67
1689 };
1690
1691 enum
1692 {
1693   X86_64_06 = 0,
1694   X86_64_07,
1695   X86_64_0D,
1696   X86_64_16,
1697   X86_64_17,
1698   X86_64_1E,
1699   X86_64_1F,
1700   X86_64_27,
1701   X86_64_2F,
1702   X86_64_37,
1703   X86_64_3F,
1704   X86_64_60,
1705   X86_64_61,
1706   X86_64_62,
1707   X86_64_63,
1708   X86_64_6D,
1709   X86_64_6F,
1710   X86_64_82,
1711   X86_64_9A,
1712   X86_64_C4,
1713   X86_64_C5,
1714   X86_64_CE,
1715   X86_64_D4,
1716   X86_64_D5,
1717   X86_64_E8,
1718   X86_64_E9,
1719   X86_64_EA,
1720   X86_64_0F01_REG_0,
1721   X86_64_0F01_REG_1,
1722   X86_64_0F01_REG_2,
1723   X86_64_0F01_REG_3
1724 };
1725
1726 enum
1727 {
1728   THREE_BYTE_0F38 = 0,
1729   THREE_BYTE_0F3A
1730 };
1731
1732 enum
1733 {
1734   XOP_08 = 0,
1735   XOP_09,
1736   XOP_0A
1737 };
1738
1739 enum
1740 {
1741   VEX_0F = 0,
1742   VEX_0F38,
1743   VEX_0F3A
1744 };
1745
1746 enum
1747 {
1748   EVEX_0F = 0,
1749   EVEX_0F38,
1750   EVEX_0F3A
1751 };
1752
1753 enum
1754 {
1755   VEX_LEN_0F10_P_1 = 0,
1756   VEX_LEN_0F10_P_3,
1757   VEX_LEN_0F11_P_1,
1758   VEX_LEN_0F11_P_3,
1759   VEX_LEN_0F12_P_0_M_0,
1760   VEX_LEN_0F12_P_0_M_1,
1761   VEX_LEN_0F12_P_2,
1762   VEX_LEN_0F13_M_0,
1763   VEX_LEN_0F16_P_0_M_0,
1764   VEX_LEN_0F16_P_0_M_1,
1765   VEX_LEN_0F16_P_2,
1766   VEX_LEN_0F17_M_0,
1767   VEX_LEN_0F2A_P_1,
1768   VEX_LEN_0F2A_P_3,
1769   VEX_LEN_0F2C_P_1,
1770   VEX_LEN_0F2C_P_3,
1771   VEX_LEN_0F2D_P_1,
1772   VEX_LEN_0F2D_P_3,
1773   VEX_LEN_0F2E_P_0,
1774   VEX_LEN_0F2E_P_2,
1775   VEX_LEN_0F2F_P_0,
1776   VEX_LEN_0F2F_P_2,
1777   VEX_LEN_0F41_P_0,
1778   VEX_LEN_0F41_P_2,
1779   VEX_LEN_0F42_P_0,
1780   VEX_LEN_0F42_P_2,
1781   VEX_LEN_0F44_P_0,
1782   VEX_LEN_0F44_P_2,
1783   VEX_LEN_0F45_P_0,
1784   VEX_LEN_0F45_P_2,
1785   VEX_LEN_0F46_P_0,
1786   VEX_LEN_0F46_P_2,
1787   VEX_LEN_0F47_P_0,
1788   VEX_LEN_0F47_P_2,
1789   VEX_LEN_0F4A_P_0,
1790   VEX_LEN_0F4A_P_2,
1791   VEX_LEN_0F4B_P_0,
1792   VEX_LEN_0F4B_P_2,
1793   VEX_LEN_0F51_P_1,
1794   VEX_LEN_0F51_P_3,
1795   VEX_LEN_0F52_P_1,
1796   VEX_LEN_0F53_P_1,
1797   VEX_LEN_0F58_P_1,
1798   VEX_LEN_0F58_P_3,
1799   VEX_LEN_0F59_P_1,
1800   VEX_LEN_0F59_P_3,
1801   VEX_LEN_0F5A_P_1,
1802   VEX_LEN_0F5A_P_3,
1803   VEX_LEN_0F5C_P_1,
1804   VEX_LEN_0F5C_P_3,
1805   VEX_LEN_0F5D_P_1,
1806   VEX_LEN_0F5D_P_3,
1807   VEX_LEN_0F5E_P_1,
1808   VEX_LEN_0F5E_P_3,
1809   VEX_LEN_0F5F_P_1,
1810   VEX_LEN_0F5F_P_3,
1811   VEX_LEN_0F6E_P_2,
1812   VEX_LEN_0F7E_P_1,
1813   VEX_LEN_0F7E_P_2,
1814   VEX_LEN_0F90_P_0,
1815   VEX_LEN_0F90_P_2,
1816   VEX_LEN_0F91_P_0,
1817   VEX_LEN_0F91_P_2,
1818   VEX_LEN_0F92_P_0,
1819   VEX_LEN_0F92_P_2,
1820   VEX_LEN_0F92_P_3,
1821   VEX_LEN_0F93_P_0,
1822   VEX_LEN_0F93_P_2,
1823   VEX_LEN_0F93_P_3,
1824   VEX_LEN_0F98_P_0,
1825   VEX_LEN_0F98_P_2,
1826   VEX_LEN_0F99_P_0,
1827   VEX_LEN_0F99_P_2,
1828   VEX_LEN_0FAE_R_2_M_0,
1829   VEX_LEN_0FAE_R_3_M_0,
1830   VEX_LEN_0FC2_P_1,
1831   VEX_LEN_0FC2_P_3,
1832   VEX_LEN_0FC4_P_2,
1833   VEX_LEN_0FC5_P_2,
1834   VEX_LEN_0FD6_P_2,
1835   VEX_LEN_0FF7_P_2,
1836   VEX_LEN_0F3816_P_2,
1837   VEX_LEN_0F3819_P_2,
1838   VEX_LEN_0F381A_P_2_M_0,
1839   VEX_LEN_0F3836_P_2,
1840   VEX_LEN_0F3841_P_2,
1841   VEX_LEN_0F385A_P_2_M_0,
1842   VEX_LEN_0F38DB_P_2,
1843   VEX_LEN_0F38DC_P_2,
1844   VEX_LEN_0F38DD_P_2,
1845   VEX_LEN_0F38DE_P_2,
1846   VEX_LEN_0F38DF_P_2,
1847   VEX_LEN_0F38F2_P_0,
1848   VEX_LEN_0F38F3_R_1_P_0,
1849   VEX_LEN_0F38F3_R_2_P_0,
1850   VEX_LEN_0F38F3_R_3_P_0,
1851   VEX_LEN_0F38F5_P_0,
1852   VEX_LEN_0F38F5_P_1,
1853   VEX_LEN_0F38F5_P_3,
1854   VEX_LEN_0F38F6_P_3,
1855   VEX_LEN_0F38F7_P_0,
1856   VEX_LEN_0F38F7_P_1,
1857   VEX_LEN_0F38F7_P_2,
1858   VEX_LEN_0F38F7_P_3,
1859   VEX_LEN_0F3A00_P_2,
1860   VEX_LEN_0F3A01_P_2,
1861   VEX_LEN_0F3A06_P_2,
1862   VEX_LEN_0F3A0A_P_2,
1863   VEX_LEN_0F3A0B_P_2,
1864   VEX_LEN_0F3A14_P_2,
1865   VEX_LEN_0F3A15_P_2,
1866   VEX_LEN_0F3A16_P_2,
1867   VEX_LEN_0F3A17_P_2,
1868   VEX_LEN_0F3A18_P_2,
1869   VEX_LEN_0F3A19_P_2,
1870   VEX_LEN_0F3A20_P_2,
1871   VEX_LEN_0F3A21_P_2,
1872   VEX_LEN_0F3A22_P_2,
1873   VEX_LEN_0F3A30_P_2,
1874   VEX_LEN_0F3A31_P_2,
1875   VEX_LEN_0F3A32_P_2,
1876   VEX_LEN_0F3A33_P_2,
1877   VEX_LEN_0F3A38_P_2,
1878   VEX_LEN_0F3A39_P_2,
1879   VEX_LEN_0F3A41_P_2,
1880   VEX_LEN_0F3A44_P_2,
1881   VEX_LEN_0F3A46_P_2,
1882   VEX_LEN_0F3A60_P_2,
1883   VEX_LEN_0F3A61_P_2,
1884   VEX_LEN_0F3A62_P_2,
1885   VEX_LEN_0F3A63_P_2,
1886   VEX_LEN_0F3A6A_P_2,
1887   VEX_LEN_0F3A6B_P_2,
1888   VEX_LEN_0F3A6E_P_2,
1889   VEX_LEN_0F3A6F_P_2,
1890   VEX_LEN_0F3A7A_P_2,
1891   VEX_LEN_0F3A7B_P_2,
1892   VEX_LEN_0F3A7E_P_2,
1893   VEX_LEN_0F3A7F_P_2,
1894   VEX_LEN_0F3ADF_P_2,
1895   VEX_LEN_0F3AF0_P_3,
1896   VEX_LEN_0FXOP_08_CC,
1897   VEX_LEN_0FXOP_08_CD,
1898   VEX_LEN_0FXOP_08_CE,
1899   VEX_LEN_0FXOP_08_CF,
1900   VEX_LEN_0FXOP_08_EC,
1901   VEX_LEN_0FXOP_08_ED,
1902   VEX_LEN_0FXOP_08_EE,
1903   VEX_LEN_0FXOP_08_EF,
1904   VEX_LEN_0FXOP_09_80,
1905   VEX_LEN_0FXOP_09_81
1906 };
1907
1908 enum
1909 {
1910   VEX_W_0F10_P_0 = 0,
1911   VEX_W_0F10_P_1,
1912   VEX_W_0F10_P_2,
1913   VEX_W_0F10_P_3,
1914   VEX_W_0F11_P_0,
1915   VEX_W_0F11_P_1,
1916   VEX_W_0F11_P_2,
1917   VEX_W_0F11_P_3,
1918   VEX_W_0F12_P_0_M_0,
1919   VEX_W_0F12_P_0_M_1,
1920   VEX_W_0F12_P_1,
1921   VEX_W_0F12_P_2,
1922   VEX_W_0F12_P_3,
1923   VEX_W_0F13_M_0,
1924   VEX_W_0F14,
1925   VEX_W_0F15,
1926   VEX_W_0F16_P_0_M_0,
1927   VEX_W_0F16_P_0_M_1,
1928   VEX_W_0F16_P_1,
1929   VEX_W_0F16_P_2,
1930   VEX_W_0F17_M_0,
1931   VEX_W_0F28,
1932   VEX_W_0F29,
1933   VEX_W_0F2B_M_0,
1934   VEX_W_0F2E_P_0,
1935   VEX_W_0F2E_P_2,
1936   VEX_W_0F2F_P_0,
1937   VEX_W_0F2F_P_2,
1938   VEX_W_0F41_P_0_LEN_1,
1939   VEX_W_0F41_P_2_LEN_1,
1940   VEX_W_0F42_P_0_LEN_1,
1941   VEX_W_0F42_P_2_LEN_1,
1942   VEX_W_0F44_P_0_LEN_0,
1943   VEX_W_0F44_P_2_LEN_0,
1944   VEX_W_0F45_P_0_LEN_1,
1945   VEX_W_0F45_P_2_LEN_1,
1946   VEX_W_0F46_P_0_LEN_1,
1947   VEX_W_0F46_P_2_LEN_1,
1948   VEX_W_0F47_P_0_LEN_1,
1949   VEX_W_0F47_P_2_LEN_1,
1950   VEX_W_0F4A_P_0_LEN_1,
1951   VEX_W_0F4A_P_2_LEN_1,
1952   VEX_W_0F4B_P_0_LEN_1,
1953   VEX_W_0F4B_P_2_LEN_1,
1954   VEX_W_0F50_M_0,
1955   VEX_W_0F51_P_0,
1956   VEX_W_0F51_P_1,
1957   VEX_W_0F51_P_2,
1958   VEX_W_0F51_P_3,
1959   VEX_W_0F52_P_0,
1960   VEX_W_0F52_P_1,
1961   VEX_W_0F53_P_0,
1962   VEX_W_0F53_P_1,
1963   VEX_W_0F58_P_0,
1964   VEX_W_0F58_P_1,
1965   VEX_W_0F58_P_2,
1966   VEX_W_0F58_P_3,
1967   VEX_W_0F59_P_0,
1968   VEX_W_0F59_P_1,
1969   VEX_W_0F59_P_2,
1970   VEX_W_0F59_P_3,
1971   VEX_W_0F5A_P_0,
1972   VEX_W_0F5A_P_1,
1973   VEX_W_0F5A_P_3,
1974   VEX_W_0F5B_P_0,
1975   VEX_W_0F5B_P_1,
1976   VEX_W_0F5B_P_2,
1977   VEX_W_0F5C_P_0,
1978   VEX_W_0F5C_P_1,
1979   VEX_W_0F5C_P_2,
1980   VEX_W_0F5C_P_3,
1981   VEX_W_0F5D_P_0,
1982   VEX_W_0F5D_P_1,
1983   VEX_W_0F5D_P_2,
1984   VEX_W_0F5D_P_3,
1985   VEX_W_0F5E_P_0,
1986   VEX_W_0F5E_P_1,
1987   VEX_W_0F5E_P_2,
1988   VEX_W_0F5E_P_3,
1989   VEX_W_0F5F_P_0,
1990   VEX_W_0F5F_P_1,
1991   VEX_W_0F5F_P_2,
1992   VEX_W_0F5F_P_3,
1993   VEX_W_0F60_P_2,
1994   VEX_W_0F61_P_2,
1995   VEX_W_0F62_P_2,
1996   VEX_W_0F63_P_2,
1997   VEX_W_0F64_P_2,
1998   VEX_W_0F65_P_2,
1999   VEX_W_0F66_P_2,
2000   VEX_W_0F67_P_2,
2001   VEX_W_0F68_P_2,
2002   VEX_W_0F69_P_2,
2003   VEX_W_0F6A_P_2,
2004   VEX_W_0F6B_P_2,
2005   VEX_W_0F6C_P_2,
2006   VEX_W_0F6D_P_2,
2007   VEX_W_0F6F_P_1,
2008   VEX_W_0F6F_P_2,
2009   VEX_W_0F70_P_1,
2010   VEX_W_0F70_P_2,
2011   VEX_W_0F70_P_3,
2012   VEX_W_0F71_R_2_P_2,
2013   VEX_W_0F71_R_4_P_2,
2014   VEX_W_0F71_R_6_P_2,
2015   VEX_W_0F72_R_2_P_2,
2016   VEX_W_0F72_R_4_P_2,
2017   VEX_W_0F72_R_6_P_2,
2018   VEX_W_0F73_R_2_P_2,
2019   VEX_W_0F73_R_3_P_2,
2020   VEX_W_0F73_R_6_P_2,
2021   VEX_W_0F73_R_7_P_2,
2022   VEX_W_0F74_P_2,
2023   VEX_W_0F75_P_2,
2024   VEX_W_0F76_P_2,
2025   VEX_W_0F77_P_0,
2026   VEX_W_0F7C_P_2,
2027   VEX_W_0F7C_P_3,
2028   VEX_W_0F7D_P_2,
2029   VEX_W_0F7D_P_3,
2030   VEX_W_0F7E_P_1,
2031   VEX_W_0F7F_P_1,
2032   VEX_W_0F7F_P_2,
2033   VEX_W_0F90_P_0_LEN_0,
2034   VEX_W_0F90_P_2_LEN_0,
2035   VEX_W_0F91_P_0_LEN_0,
2036   VEX_W_0F91_P_2_LEN_0,
2037   VEX_W_0F92_P_0_LEN_0,
2038   VEX_W_0F92_P_2_LEN_0,
2039   VEX_W_0F92_P_3_LEN_0,
2040   VEX_W_0F93_P_0_LEN_0,
2041   VEX_W_0F93_P_2_LEN_0,
2042   VEX_W_0F93_P_3_LEN_0,
2043   VEX_W_0F98_P_0_LEN_0,
2044   VEX_W_0F98_P_2_LEN_0,
2045   VEX_W_0F99_P_0_LEN_0,
2046   VEX_W_0F99_P_2_LEN_0,
2047   VEX_W_0FAE_R_2_M_0,
2048   VEX_W_0FAE_R_3_M_0,
2049   VEX_W_0FC2_P_0,
2050   VEX_W_0FC2_P_1,
2051   VEX_W_0FC2_P_2,
2052   VEX_W_0FC2_P_3,
2053   VEX_W_0FC4_P_2,
2054   VEX_W_0FC5_P_2,
2055   VEX_W_0FD0_P_2,
2056   VEX_W_0FD0_P_3,
2057   VEX_W_0FD1_P_2,
2058   VEX_W_0FD2_P_2,
2059   VEX_W_0FD3_P_2,
2060   VEX_W_0FD4_P_2,
2061   VEX_W_0FD5_P_2,
2062   VEX_W_0FD6_P_2,
2063   VEX_W_0FD7_P_2_M_1,
2064   VEX_W_0FD8_P_2,
2065   VEX_W_0FD9_P_2,
2066   VEX_W_0FDA_P_2,
2067   VEX_W_0FDB_P_2,
2068   VEX_W_0FDC_P_2,
2069   VEX_W_0FDD_P_2,
2070   VEX_W_0FDE_P_2,
2071   VEX_W_0FDF_P_2,
2072   VEX_W_0FE0_P_2,
2073   VEX_W_0FE1_P_2,
2074   VEX_W_0FE2_P_2,
2075   VEX_W_0FE3_P_2,
2076   VEX_W_0FE4_P_2,
2077   VEX_W_0FE5_P_2,
2078   VEX_W_0FE6_P_1,
2079   VEX_W_0FE6_P_2,
2080   VEX_W_0FE6_P_3,
2081   VEX_W_0FE7_P_2_M_0,
2082   VEX_W_0FE8_P_2,
2083   VEX_W_0FE9_P_2,
2084   VEX_W_0FEA_P_2,
2085   VEX_W_0FEB_P_2,
2086   VEX_W_0FEC_P_2,
2087   VEX_W_0FED_P_2,
2088   VEX_W_0FEE_P_2,
2089   VEX_W_0FEF_P_2,
2090   VEX_W_0FF0_P_3_M_0,
2091   VEX_W_0FF1_P_2,
2092   VEX_W_0FF2_P_2,
2093   VEX_W_0FF3_P_2,
2094   VEX_W_0FF4_P_2,
2095   VEX_W_0FF5_P_2,
2096   VEX_W_0FF6_P_2,
2097   VEX_W_0FF7_P_2,
2098   VEX_W_0FF8_P_2,
2099   VEX_W_0FF9_P_2,
2100   VEX_W_0FFA_P_2,
2101   VEX_W_0FFB_P_2,
2102   VEX_W_0FFC_P_2,
2103   VEX_W_0FFD_P_2,
2104   VEX_W_0FFE_P_2,
2105   VEX_W_0F3800_P_2,
2106   VEX_W_0F3801_P_2,
2107   VEX_W_0F3802_P_2,
2108   VEX_W_0F3803_P_2,
2109   VEX_W_0F3804_P_2,
2110   VEX_W_0F3805_P_2,
2111   VEX_W_0F3806_P_2,
2112   VEX_W_0F3807_P_2,
2113   VEX_W_0F3808_P_2,
2114   VEX_W_0F3809_P_2,
2115   VEX_W_0F380A_P_2,
2116   VEX_W_0F380B_P_2,
2117   VEX_W_0F380C_P_2,
2118   VEX_W_0F380D_P_2,
2119   VEX_W_0F380E_P_2,
2120   VEX_W_0F380F_P_2,
2121   VEX_W_0F3816_P_2,
2122   VEX_W_0F3817_P_2,
2123   VEX_W_0F3818_P_2,
2124   VEX_W_0F3819_P_2,
2125   VEX_W_0F381A_P_2_M_0,
2126   VEX_W_0F381C_P_2,
2127   VEX_W_0F381D_P_2,
2128   VEX_W_0F381E_P_2,
2129   VEX_W_0F3820_P_2,
2130   VEX_W_0F3821_P_2,
2131   VEX_W_0F3822_P_2,
2132   VEX_W_0F3823_P_2,
2133   VEX_W_0F3824_P_2,
2134   VEX_W_0F3825_P_2,
2135   VEX_W_0F3828_P_2,
2136   VEX_W_0F3829_P_2,
2137   VEX_W_0F382A_P_2_M_0,
2138   VEX_W_0F382B_P_2,
2139   VEX_W_0F382C_P_2_M_0,
2140   VEX_W_0F382D_P_2_M_0,
2141   VEX_W_0F382E_P_2_M_0,
2142   VEX_W_0F382F_P_2_M_0,
2143   VEX_W_0F3830_P_2,
2144   VEX_W_0F3831_P_2,
2145   VEX_W_0F3832_P_2,
2146   VEX_W_0F3833_P_2,
2147   VEX_W_0F3834_P_2,
2148   VEX_W_0F3835_P_2,
2149   VEX_W_0F3836_P_2,
2150   VEX_W_0F3837_P_2,
2151   VEX_W_0F3838_P_2,
2152   VEX_W_0F3839_P_2,
2153   VEX_W_0F383A_P_2,
2154   VEX_W_0F383B_P_2,
2155   VEX_W_0F383C_P_2,
2156   VEX_W_0F383D_P_2,
2157   VEX_W_0F383E_P_2,
2158   VEX_W_0F383F_P_2,
2159   VEX_W_0F3840_P_2,
2160   VEX_W_0F3841_P_2,
2161   VEX_W_0F3846_P_2,
2162   VEX_W_0F3858_P_2,
2163   VEX_W_0F3859_P_2,
2164   VEX_W_0F385A_P_2_M_0,
2165   VEX_W_0F3878_P_2,
2166   VEX_W_0F3879_P_2,
2167   VEX_W_0F38DB_P_2,
2168   VEX_W_0F38DC_P_2,
2169   VEX_W_0F38DD_P_2,
2170   VEX_W_0F38DE_P_2,
2171   VEX_W_0F38DF_P_2,
2172   VEX_W_0F3A00_P_2,
2173   VEX_W_0F3A01_P_2,
2174   VEX_W_0F3A02_P_2,
2175   VEX_W_0F3A04_P_2,
2176   VEX_W_0F3A05_P_2,
2177   VEX_W_0F3A06_P_2,
2178   VEX_W_0F3A08_P_2,
2179   VEX_W_0F3A09_P_2,
2180   VEX_W_0F3A0A_P_2,
2181   VEX_W_0F3A0B_P_2,
2182   VEX_W_0F3A0C_P_2,
2183   VEX_W_0F3A0D_P_2,
2184   VEX_W_0F3A0E_P_2,
2185   VEX_W_0F3A0F_P_2,
2186   VEX_W_0F3A14_P_2,
2187   VEX_W_0F3A15_P_2,
2188   VEX_W_0F3A18_P_2,
2189   VEX_W_0F3A19_P_2,
2190   VEX_W_0F3A20_P_2,
2191   VEX_W_0F3A21_P_2,
2192   VEX_W_0F3A30_P_2_LEN_0,
2193   VEX_W_0F3A31_P_2_LEN_0,
2194   VEX_W_0F3A32_P_2_LEN_0,
2195   VEX_W_0F3A33_P_2_LEN_0,
2196   VEX_W_0F3A38_P_2,
2197   VEX_W_0F3A39_P_2,
2198   VEX_W_0F3A40_P_2,
2199   VEX_W_0F3A41_P_2,
2200   VEX_W_0F3A42_P_2,
2201   VEX_W_0F3A44_P_2,
2202   VEX_W_0F3A46_P_2,
2203   VEX_W_0F3A48_P_2,
2204   VEX_W_0F3A49_P_2,
2205   VEX_W_0F3A4A_P_2,
2206   VEX_W_0F3A4B_P_2,
2207   VEX_W_0F3A4C_P_2,
2208   VEX_W_0F3A62_P_2,
2209   VEX_W_0F3A63_P_2,
2210   VEX_W_0F3ADF_P_2,
2211
2212   EVEX_W_0F10_P_0,
2213   EVEX_W_0F10_P_1_M_0,
2214   EVEX_W_0F10_P_1_M_1,
2215   EVEX_W_0F10_P_2,
2216   EVEX_W_0F10_P_3_M_0,
2217   EVEX_W_0F10_P_3_M_1,
2218   EVEX_W_0F11_P_0,
2219   EVEX_W_0F11_P_1_M_0,
2220   EVEX_W_0F11_P_1_M_1,
2221   EVEX_W_0F11_P_2,
2222   EVEX_W_0F11_P_3_M_0,
2223   EVEX_W_0F11_P_3_M_1,
2224   EVEX_W_0F12_P_0_M_0,
2225   EVEX_W_0F12_P_0_M_1,
2226   EVEX_W_0F12_P_1,
2227   EVEX_W_0F12_P_2,
2228   EVEX_W_0F12_P_3,
2229   EVEX_W_0F13_P_0,
2230   EVEX_W_0F13_P_2,
2231   EVEX_W_0F14_P_0,
2232   EVEX_W_0F14_P_2,
2233   EVEX_W_0F15_P_0,
2234   EVEX_W_0F15_P_2,
2235   EVEX_W_0F16_P_0_M_0,
2236   EVEX_W_0F16_P_0_M_1,
2237   EVEX_W_0F16_P_1,
2238   EVEX_W_0F16_P_2,
2239   EVEX_W_0F17_P_0,
2240   EVEX_W_0F17_P_2,
2241   EVEX_W_0F28_P_0,
2242   EVEX_W_0F28_P_2,
2243   EVEX_W_0F29_P_0,
2244   EVEX_W_0F29_P_2,
2245   EVEX_W_0F2A_P_1,
2246   EVEX_W_0F2A_P_3,
2247   EVEX_W_0F2B_P_0,
2248   EVEX_W_0F2B_P_2,
2249   EVEX_W_0F2E_P_0,
2250   EVEX_W_0F2E_P_2,
2251   EVEX_W_0F2F_P_0,
2252   EVEX_W_0F2F_P_2,
2253   EVEX_W_0F51_P_0,
2254   EVEX_W_0F51_P_1,
2255   EVEX_W_0F51_P_2,
2256   EVEX_W_0F51_P_3,
2257   EVEX_W_0F54_P_0,
2258   EVEX_W_0F54_P_2,
2259   EVEX_W_0F55_P_0,
2260   EVEX_W_0F55_P_2,
2261   EVEX_W_0F56_P_0,
2262   EVEX_W_0F56_P_2,
2263   EVEX_W_0F57_P_0,
2264   EVEX_W_0F57_P_2,
2265   EVEX_W_0F58_P_0,
2266   EVEX_W_0F58_P_1,
2267   EVEX_W_0F58_P_2,
2268   EVEX_W_0F58_P_3,
2269   EVEX_W_0F59_P_0,
2270   EVEX_W_0F59_P_1,
2271   EVEX_W_0F59_P_2,
2272   EVEX_W_0F59_P_3,
2273   EVEX_W_0F5A_P_0,
2274   EVEX_W_0F5A_P_1,
2275   EVEX_W_0F5A_P_2,
2276   EVEX_W_0F5A_P_3,
2277   EVEX_W_0F5B_P_0,
2278   EVEX_W_0F5B_P_1,
2279   EVEX_W_0F5B_P_2,
2280   EVEX_W_0F5C_P_0,
2281   EVEX_W_0F5C_P_1,
2282   EVEX_W_0F5C_P_2,
2283   EVEX_W_0F5C_P_3,
2284   EVEX_W_0F5D_P_0,
2285   EVEX_W_0F5D_P_1,
2286   EVEX_W_0F5D_P_2,
2287   EVEX_W_0F5D_P_3,
2288   EVEX_W_0F5E_P_0,
2289   EVEX_W_0F5E_P_1,
2290   EVEX_W_0F5E_P_2,
2291   EVEX_W_0F5E_P_3,
2292   EVEX_W_0F5F_P_0,
2293   EVEX_W_0F5F_P_1,
2294   EVEX_W_0F5F_P_2,
2295   EVEX_W_0F5F_P_3,
2296   EVEX_W_0F62_P_2,
2297   EVEX_W_0F66_P_2,
2298   EVEX_W_0F6A_P_2,
2299   EVEX_W_0F6B_P_2,
2300   EVEX_W_0F6C_P_2,
2301   EVEX_W_0F6D_P_2,
2302   EVEX_W_0F6E_P_2,
2303   EVEX_W_0F6F_P_1,
2304   EVEX_W_0F6F_P_2,
2305   EVEX_W_0F6F_P_3,
2306   EVEX_W_0F70_P_2,
2307   EVEX_W_0F72_R_2_P_2,
2308   EVEX_W_0F72_R_6_P_2,
2309   EVEX_W_0F73_R_2_P_2,
2310   EVEX_W_0F73_R_6_P_2,
2311   EVEX_W_0F76_P_2,
2312   EVEX_W_0F78_P_0,
2313   EVEX_W_0F78_P_2,
2314   EVEX_W_0F79_P_0,
2315   EVEX_W_0F79_P_2,
2316   EVEX_W_0F7A_P_1,
2317   EVEX_W_0F7A_P_2,
2318   EVEX_W_0F7A_P_3,
2319   EVEX_W_0F7B_P_1,
2320   EVEX_W_0F7B_P_2,
2321   EVEX_W_0F7B_P_3,
2322   EVEX_W_0F7E_P_1,
2323   EVEX_W_0F7E_P_2,
2324   EVEX_W_0F7F_P_1,
2325   EVEX_W_0F7F_P_2,
2326   EVEX_W_0F7F_P_3,
2327   EVEX_W_0FC2_P_0,
2328   EVEX_W_0FC2_P_1,
2329   EVEX_W_0FC2_P_2,
2330   EVEX_W_0FC2_P_3,
2331   EVEX_W_0FC6_P_0,
2332   EVEX_W_0FC6_P_2,
2333   EVEX_W_0FD2_P_2,
2334   EVEX_W_0FD3_P_2,
2335   EVEX_W_0FD4_P_2,
2336   EVEX_W_0FD6_P_2,
2337   EVEX_W_0FE6_P_1,
2338   EVEX_W_0FE6_P_2,
2339   EVEX_W_0FE6_P_3,
2340   EVEX_W_0FE7_P_2,
2341   EVEX_W_0FF2_P_2,
2342   EVEX_W_0FF3_P_2,
2343   EVEX_W_0FF4_P_2,
2344   EVEX_W_0FFA_P_2,
2345   EVEX_W_0FFB_P_2,
2346   EVEX_W_0FFE_P_2,
2347   EVEX_W_0F380C_P_2,
2348   EVEX_W_0F380D_P_2,
2349   EVEX_W_0F3810_P_1,
2350   EVEX_W_0F3810_P_2,
2351   EVEX_W_0F3811_P_1,
2352   EVEX_W_0F3811_P_2,
2353   EVEX_W_0F3812_P_1,
2354   EVEX_W_0F3812_P_2,
2355   EVEX_W_0F3813_P_1,
2356   EVEX_W_0F3813_P_2,
2357   EVEX_W_0F3814_P_1,
2358   EVEX_W_0F3815_P_1,
2359   EVEX_W_0F3818_P_2,
2360   EVEX_W_0F3819_P_2,
2361   EVEX_W_0F381A_P_2,
2362   EVEX_W_0F381B_P_2,
2363   EVEX_W_0F381E_P_2,
2364   EVEX_W_0F381F_P_2,
2365   EVEX_W_0F3820_P_1,
2366   EVEX_W_0F3821_P_1,
2367   EVEX_W_0F3822_P_1,
2368   EVEX_W_0F3823_P_1,
2369   EVEX_W_0F3824_P_1,
2370   EVEX_W_0F3825_P_1,
2371   EVEX_W_0F3825_P_2,
2372   EVEX_W_0F3826_P_1,
2373   EVEX_W_0F3826_P_2,
2374   EVEX_W_0F3828_P_1,
2375   EVEX_W_0F3828_P_2,
2376   EVEX_W_0F3829_P_1,
2377   EVEX_W_0F3829_P_2,
2378   EVEX_W_0F382A_P_1,
2379   EVEX_W_0F382A_P_2,
2380   EVEX_W_0F382B_P_2,
2381   EVEX_W_0F3830_P_1,
2382   EVEX_W_0F3831_P_1,
2383   EVEX_W_0F3832_P_1,
2384   EVEX_W_0F3833_P_1,
2385   EVEX_W_0F3834_P_1,
2386   EVEX_W_0F3835_P_1,
2387   EVEX_W_0F3835_P_2,
2388   EVEX_W_0F3837_P_2,
2389   EVEX_W_0F3838_P_1,
2390   EVEX_W_0F3839_P_1,
2391   EVEX_W_0F383A_P_1,
2392   EVEX_W_0F3840_P_2,
2393   EVEX_W_0F3855_P_2,
2394   EVEX_W_0F3858_P_2,
2395   EVEX_W_0F3859_P_2,
2396   EVEX_W_0F385A_P_2,
2397   EVEX_W_0F385B_P_2,
2398   EVEX_W_0F3866_P_2,
2399   EVEX_W_0F3875_P_2,
2400   EVEX_W_0F3878_P_2,
2401   EVEX_W_0F3879_P_2,
2402   EVEX_W_0F387A_P_2,
2403   EVEX_W_0F387B_P_2,
2404   EVEX_W_0F387D_P_2,
2405   EVEX_W_0F3883_P_2,
2406   EVEX_W_0F388D_P_2,
2407   EVEX_W_0F3891_P_2,
2408   EVEX_W_0F3893_P_2,
2409   EVEX_W_0F38A1_P_2,
2410   EVEX_W_0F38A3_P_2,
2411   EVEX_W_0F38C7_R_1_P_2,
2412   EVEX_W_0F38C7_R_2_P_2,
2413   EVEX_W_0F38C7_R_5_P_2,
2414   EVEX_W_0F38C7_R_6_P_2,
2415
2416   EVEX_W_0F3A00_P_2,
2417   EVEX_W_0F3A01_P_2,
2418   EVEX_W_0F3A04_P_2,
2419   EVEX_W_0F3A05_P_2,
2420   EVEX_W_0F3A08_P_2,
2421   EVEX_W_0F3A09_P_2,
2422   EVEX_W_0F3A0A_P_2,
2423   EVEX_W_0F3A0B_P_2,
2424   EVEX_W_0F3A16_P_2,
2425   EVEX_W_0F3A18_P_2,
2426   EVEX_W_0F3A19_P_2,
2427   EVEX_W_0F3A1A_P_2,
2428   EVEX_W_0F3A1B_P_2,
2429   EVEX_W_0F3A1D_P_2,
2430   EVEX_W_0F3A21_P_2,
2431   EVEX_W_0F3A22_P_2,
2432   EVEX_W_0F3A23_P_2,
2433   EVEX_W_0F3A38_P_2,
2434   EVEX_W_0F3A39_P_2,
2435   EVEX_W_0F3A3A_P_2,
2436   EVEX_W_0F3A3B_P_2,
2437   EVEX_W_0F3A3E_P_2,
2438   EVEX_W_0F3A3F_P_2,
2439   EVEX_W_0F3A42_P_2,
2440   EVEX_W_0F3A43_P_2,
2441   EVEX_W_0F3A50_P_2,
2442   EVEX_W_0F3A51_P_2,
2443   EVEX_W_0F3A56_P_2,
2444   EVEX_W_0F3A57_P_2,
2445   EVEX_W_0F3A66_P_2,
2446   EVEX_W_0F3A67_P_2
2447 };
2448
2449 typedef void (*op_rtn) (int bytemode, int sizeflag);
2450
2451 struct dis386 {
2452   const char *name;
2453   struct
2454     {
2455       op_rtn rtn;
2456       int bytemode;
2457     } op[MAX_OPERANDS];
2458   unsigned int prefix_requirement;
2459 };
2460
2461 /* Upper case letters in the instruction names here are macros.
2462    'A' => print 'b' if no register operands or suffix_always is true
2463    'B' => print 'b' if suffix_always is true
2464    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2465           size prefix
2466    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2467           suffix_always is true
2468    'E' => print 'e' if 32-bit form of jcxz
2469    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2470    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2471    'H' => print ",pt" or ",pn" branch hint
2472    'I' => honor following macro letter even in Intel mode (implemented only
2473           for some of the macro letters)
2474    'J' => print 'l'
2475    'K' => print 'd' or 'q' if rex prefix is present.
2476    'L' => print 'l' if suffix_always is true
2477    'M' => print 'r' if intel_mnemonic is false.
2478    'N' => print 'n' if instruction has no wait "prefix"
2479    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2480    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2481           or suffix_always is true.  print 'q' if rex prefix is present.
2482    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2483           is true
2484    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2485    'S' => print 'w', 'l' or 'q' if suffix_always is true
2486    'T' => print 'q' in 64bit mode if instruction has no operand size
2487           prefix and behave as 'P' otherwise
2488    'U' => print 'q' in 64bit mode if instruction has no operand size
2489           prefix and behave as 'Q' otherwise
2490    'V' => print 'q' in 64bit mode if instruction has no operand size
2491           prefix and behave as 'S' otherwise
2492    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2493    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2494    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2495           suffix_always is true.
2496    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2497    '!' => change condition from true to false or from false to true.
2498    '%' => add 1 upper case letter to the macro.
2499    '^' => print 'w' or 'l' depending on operand size prefix or
2500           suffix_always is true (lcall/ljmp).
2501    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2502           on operand size prefix.
2503    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2504           has no operand size prefix for AMD64 ISA, behave as 'P'
2505           otherwise
2506
2507    2 upper case letter macros:
2508    "XY" => print 'x' or 'y' if suffix_always is true or no register
2509            operands and no broadcast.
2510    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2511            register operands and no broadcast.
2512    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2513    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2514            or suffix_always is true
2515    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2516    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2517    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2518    "LW" => print 'd', 'q' depending on the VEX.W bit
2519    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2520            an operand size prefix, or suffix_always is true.  print
2521            'q' if rex prefix is present.
2522
2523    Many of the above letters print nothing in Intel mode.  See "putop"
2524    for the details.
2525
2526    Braces '{' and '}', and vertical bars '|', indicate alternative
2527    mnemonic strings for AT&T and Intel.  */
2528
2529 static const struct dis386 dis386[] = {
2530   /* 00 */
2531   { "addB",             { Ebh1, Gb }, 0 },
2532   { "addS",             { Evh1, Gv }, 0 },
2533   { "addB",             { Gb, EbS }, 0 },
2534   { "addS",             { Gv, EvS }, 0 },
2535   { "addB",             { AL, Ib }, 0 },
2536   { "addS",             { eAX, Iv }, 0 },
2537   { X86_64_TABLE (X86_64_06) },
2538   { X86_64_TABLE (X86_64_07) },
2539   /* 08 */
2540   { "orB",              { Ebh1, Gb }, 0 },
2541   { "orS",              { Evh1, Gv }, 0 },
2542   { "orB",              { Gb, EbS }, 0 },
2543   { "orS",              { Gv, EvS }, 0 },
2544   { "orB",              { AL, Ib }, 0 },
2545   { "orS",              { eAX, Iv }, 0 },
2546   { X86_64_TABLE (X86_64_0D) },
2547   { Bad_Opcode },       /* 0x0f extended opcode escape */
2548   /* 10 */
2549   { "adcB",             { Ebh1, Gb }, 0 },
2550   { "adcS",             { Evh1, Gv }, 0 },
2551   { "adcB",             { Gb, EbS }, 0 },
2552   { "adcS",             { Gv, EvS }, 0 },
2553   { "adcB",             { AL, Ib }, 0 },
2554   { "adcS",             { eAX, Iv }, 0 },
2555   { X86_64_TABLE (X86_64_16) },
2556   { X86_64_TABLE (X86_64_17) },
2557   /* 18 */
2558   { "sbbB",             { Ebh1, Gb }, 0 },
2559   { "sbbS",             { Evh1, Gv }, 0 },
2560   { "sbbB",             { Gb, EbS }, 0 },
2561   { "sbbS",             { Gv, EvS }, 0 },
2562   { "sbbB",             { AL, Ib }, 0 },
2563   { "sbbS",             { eAX, Iv }, 0 },
2564   { X86_64_TABLE (X86_64_1E) },
2565   { X86_64_TABLE (X86_64_1F) },
2566   /* 20 */
2567   { "andB",             { Ebh1, Gb }, 0 },
2568   { "andS",             { Evh1, Gv }, 0 },
2569   { "andB",             { Gb, EbS }, 0 },
2570   { "andS",             { Gv, EvS }, 0 },
2571   { "andB",             { AL, Ib }, 0 },
2572   { "andS",             { eAX, Iv }, 0 },
2573   { Bad_Opcode },       /* SEG ES prefix */
2574   { X86_64_TABLE (X86_64_27) },
2575   /* 28 */
2576   { "subB",             { Ebh1, Gb }, 0 },
2577   { "subS",             { Evh1, Gv }, 0 },
2578   { "subB",             { Gb, EbS }, 0 },
2579   { "subS",             { Gv, EvS }, 0 },
2580   { "subB",             { AL, Ib }, 0 },
2581   { "subS",             { eAX, Iv }, 0 },
2582   { Bad_Opcode },       /* SEG CS prefix */
2583   { X86_64_TABLE (X86_64_2F) },
2584   /* 30 */
2585   { "xorB",             { Ebh1, Gb }, 0 },
2586   { "xorS",             { Evh1, Gv }, 0 },
2587   { "xorB",             { Gb, EbS }, 0 },
2588   { "xorS",             { Gv, EvS }, 0 },
2589   { "xorB",             { AL, Ib }, 0 },
2590   { "xorS",             { eAX, Iv }, 0 },
2591   { Bad_Opcode },       /* SEG SS prefix */
2592   { X86_64_TABLE (X86_64_37) },
2593   /* 38 */
2594   { "cmpB",             { Eb, Gb }, 0 },
2595   { "cmpS",             { Ev, Gv }, 0 },
2596   { "cmpB",             { Gb, EbS }, 0 },
2597   { "cmpS",             { Gv, EvS }, 0 },
2598   { "cmpB",             { AL, Ib }, 0 },
2599   { "cmpS",             { eAX, Iv }, 0 },
2600   { Bad_Opcode },       /* SEG DS prefix */
2601   { X86_64_TABLE (X86_64_3F) },
2602   /* 40 */
2603   { "inc{S|}",          { RMeAX }, 0 },
2604   { "inc{S|}",          { RMeCX }, 0 },
2605   { "inc{S|}",          { RMeDX }, 0 },
2606   { "inc{S|}",          { RMeBX }, 0 },
2607   { "inc{S|}",          { RMeSP }, 0 },
2608   { "inc{S|}",          { RMeBP }, 0 },
2609   { "inc{S|}",          { RMeSI }, 0 },
2610   { "inc{S|}",          { RMeDI }, 0 },
2611   /* 48 */
2612   { "dec{S|}",          { RMeAX }, 0 },
2613   { "dec{S|}",          { RMeCX }, 0 },
2614   { "dec{S|}",          { RMeDX }, 0 },
2615   { "dec{S|}",          { RMeBX }, 0 },
2616   { "dec{S|}",          { RMeSP }, 0 },
2617   { "dec{S|}",          { RMeBP }, 0 },
2618   { "dec{S|}",          { RMeSI }, 0 },
2619   { "dec{S|}",          { RMeDI }, 0 },
2620   /* 50 */
2621   { "pushV",            { RMrAX }, 0 },
2622   { "pushV",            { RMrCX }, 0 },
2623   { "pushV",            { RMrDX }, 0 },
2624   { "pushV",            { RMrBX }, 0 },
2625   { "pushV",            { RMrSP }, 0 },
2626   { "pushV",            { RMrBP }, 0 },
2627   { "pushV",            { RMrSI }, 0 },
2628   { "pushV",            { RMrDI }, 0 },
2629   /* 58 */
2630   { "popV",             { RMrAX }, 0 },
2631   { "popV",             { RMrCX }, 0 },
2632   { "popV",             { RMrDX }, 0 },
2633   { "popV",             { RMrBX }, 0 },
2634   { "popV",             { RMrSP }, 0 },
2635   { "popV",             { RMrBP }, 0 },
2636   { "popV",             { RMrSI }, 0 },
2637   { "popV",             { RMrDI }, 0 },
2638   /* 60 */
2639   { X86_64_TABLE (X86_64_60) },
2640   { X86_64_TABLE (X86_64_61) },
2641   { X86_64_TABLE (X86_64_62) },
2642   { X86_64_TABLE (X86_64_63) },
2643   { Bad_Opcode },       /* seg fs */
2644   { Bad_Opcode },       /* seg gs */
2645   { Bad_Opcode },       /* op size prefix */
2646   { Bad_Opcode },       /* adr size prefix */
2647   /* 68 */
2648   { "pushT",            { sIv }, 0 },
2649   { "imulS",            { Gv, Ev, Iv }, 0 },
2650   { "pushT",            { sIbT }, 0 },
2651   { "imulS",            { Gv, Ev, sIb }, 0 },
2652   { "ins{b|}",          { Ybr, indirDX }, 0 },
2653   { X86_64_TABLE (X86_64_6D) },
2654   { "outs{b|}",         { indirDXr, Xb }, 0 },
2655   { X86_64_TABLE (X86_64_6F) },
2656   /* 70 */
2657   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2658   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2659   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2660   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2661   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2662   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2663   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2664   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2665   /* 78 */
2666   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2667   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2668   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2669   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2670   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2671   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2672   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2673   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2674   /* 80 */
2675   { REG_TABLE (REG_80) },
2676   { REG_TABLE (REG_81) },
2677   { X86_64_TABLE (X86_64_82) },
2678   { REG_TABLE (REG_83) },
2679   { "testB",            { Eb, Gb }, 0 },
2680   { "testS",            { Ev, Gv }, 0 },
2681   { "xchgB",            { Ebh2, Gb }, 0 },
2682   { "xchgS",            { Evh2, Gv }, 0 },
2683   /* 88 */
2684   { "movB",             { Ebh3, Gb }, 0 },
2685   { "movS",             { Evh3, Gv }, 0 },
2686   { "movB",             { Gb, EbS }, 0 },
2687   { "movS",             { Gv, EvS }, 0 },
2688   { "movD",             { Sv, Sw }, 0 },
2689   { MOD_TABLE (MOD_8D) },
2690   { "movD",             { Sw, Sv }, 0 },
2691   { REG_TABLE (REG_8F) },
2692   /* 90 */
2693   { PREFIX_TABLE (PREFIX_90) },
2694   { "xchgS",            { RMeCX, eAX }, 0 },
2695   { "xchgS",            { RMeDX, eAX }, 0 },
2696   { "xchgS",            { RMeBX, eAX }, 0 },
2697   { "xchgS",            { RMeSP, eAX }, 0 },
2698   { "xchgS",            { RMeBP, eAX }, 0 },
2699   { "xchgS",            { RMeSI, eAX }, 0 },
2700   { "xchgS",            { RMeDI, eAX }, 0 },
2701   /* 98 */
2702   { "cW{t|}R",          { XX }, 0 },
2703   { "cR{t|}O",          { XX }, 0 },
2704   { X86_64_TABLE (X86_64_9A) },
2705   { Bad_Opcode },       /* fwait */
2706   { "pushfT",           { XX }, 0 },
2707   { "popfT",            { XX }, 0 },
2708   { "sahf",             { XX }, 0 },
2709   { "lahf",             { XX }, 0 },
2710   /* a0 */
2711   { "mov%LB",           { AL, Ob }, 0 },
2712   { "mov%LS",           { eAX, Ov }, 0 },
2713   { "mov%LB",           { Ob, AL }, 0 },
2714   { "mov%LS",           { Ov, eAX }, 0 },
2715   { "movs{b|}",         { Ybr, Xb }, 0 },
2716   { "movs{R|}",         { Yvr, Xv }, 0 },
2717   { "cmps{b|}",         { Xb, Yb }, 0 },
2718   { "cmps{R|}",         { Xv, Yv }, 0 },
2719   /* a8 */
2720   { "testB",            { AL, Ib }, 0 },
2721   { "testS",            { eAX, Iv }, 0 },
2722   { "stosB",            { Ybr, AL }, 0 },
2723   { "stosS",            { Yvr, eAX }, 0 },
2724   { "lodsB",            { ALr, Xb }, 0 },
2725   { "lodsS",            { eAXr, Xv }, 0 },
2726   { "scasB",            { AL, Yb }, 0 },
2727   { "scasS",            { eAX, Yv }, 0 },
2728   /* b0 */
2729   { "movB",             { RMAL, Ib }, 0 },
2730   { "movB",             { RMCL, Ib }, 0 },
2731   { "movB",             { RMDL, Ib }, 0 },
2732   { "movB",             { RMBL, Ib }, 0 },
2733   { "movB",             { RMAH, Ib }, 0 },
2734   { "movB",             { RMCH, Ib }, 0 },
2735   { "movB",             { RMDH, Ib }, 0 },
2736   { "movB",             { RMBH, Ib }, 0 },
2737   /* b8 */
2738   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2739   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2740   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2741   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2742   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2743   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2744   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2745   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2746   /* c0 */
2747   { REG_TABLE (REG_C0) },
2748   { REG_TABLE (REG_C1) },
2749   { "retT",             { Iw, BND }, 0 },
2750   { "retT",             { BND }, 0 },
2751   { X86_64_TABLE (X86_64_C4) },
2752   { X86_64_TABLE (X86_64_C5) },
2753   { REG_TABLE (REG_C6) },
2754   { REG_TABLE (REG_C7) },
2755   /* c8 */
2756   { "enterT",           { Iw, Ib }, 0 },
2757   { "leaveT",           { XX }, 0 },
2758   { "Jret{|f}P",        { Iw }, 0 },
2759   { "Jret{|f}P",        { XX }, 0 },
2760   { "int3",             { XX }, 0 },
2761   { "int",              { Ib }, 0 },
2762   { X86_64_TABLE (X86_64_CE) },
2763   { "iret%LP",          { XX }, 0 },
2764   /* d0 */
2765   { REG_TABLE (REG_D0) },
2766   { REG_TABLE (REG_D1) },
2767   { REG_TABLE (REG_D2) },
2768   { REG_TABLE (REG_D3) },
2769   { X86_64_TABLE (X86_64_D4) },
2770   { X86_64_TABLE (X86_64_D5) },
2771   { Bad_Opcode },
2772   { "xlat",             { DSBX }, 0 },
2773   /* d8 */
2774   { FLOAT },
2775   { FLOAT },
2776   { FLOAT },
2777   { FLOAT },
2778   { FLOAT },
2779   { FLOAT },
2780   { FLOAT },
2781   { FLOAT },
2782   /* e0 */
2783   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2784   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2785   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2786   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2787   { "inB",              { AL, Ib }, 0 },
2788   { "inG",              { zAX, Ib }, 0 },
2789   { "outB",             { Ib, AL }, 0 },
2790   { "outG",             { Ib, zAX }, 0 },
2791   /* e8 */
2792   { X86_64_TABLE (X86_64_E8) },
2793   { X86_64_TABLE (X86_64_E9) },
2794   { X86_64_TABLE (X86_64_EA) },
2795   { "jmp",              { Jb, BND }, 0 },
2796   { "inB",              { AL, indirDX }, 0 },
2797   { "inG",              { zAX, indirDX }, 0 },
2798   { "outB",             { indirDX, AL }, 0 },
2799   { "outG",             { indirDX, zAX }, 0 },
2800   /* f0 */
2801   { Bad_Opcode },       /* lock prefix */
2802   { "icebp",            { XX }, 0 },
2803   { Bad_Opcode },       /* repne */
2804   { Bad_Opcode },       /* repz */
2805   { "hlt",              { XX }, 0 },
2806   { "cmc",              { XX }, 0 },
2807   { REG_TABLE (REG_F6) },
2808   { REG_TABLE (REG_F7) },
2809   /* f8 */
2810   { "clc",              { XX }, 0 },
2811   { "stc",              { XX }, 0 },
2812   { "cli",              { XX }, 0 },
2813   { "sti",              { XX }, 0 },
2814   { "cld",              { XX }, 0 },
2815   { "std",              { XX }, 0 },
2816   { REG_TABLE (REG_FE) },
2817   { REG_TABLE (REG_FF) },
2818 };
2819
2820 static const struct dis386 dis386_twobyte[] = {
2821   /* 00 */
2822   { REG_TABLE (REG_0F00 ) },
2823   { REG_TABLE (REG_0F01 ) },
2824   { "larS",             { Gv, Ew }, 0 },
2825   { "lslS",             { Gv, Ew }, 0 },
2826   { Bad_Opcode },
2827   { "syscall",          { XX }, 0 },
2828   { "clts",             { XX }, 0 },
2829   { "sysret%LP",                { XX }, 0 },
2830   /* 08 */
2831   { "invd",             { XX }, 0 },
2832   { "wbinvd",           { XX }, 0 },
2833   { Bad_Opcode },
2834   { "ud2",              { XX }, 0 },
2835   { Bad_Opcode },
2836   { REG_TABLE (REG_0F0D) },
2837   { "femms",            { XX }, 0 },
2838   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2839   /* 10 */
2840   { PREFIX_TABLE (PREFIX_0F10) },
2841   { PREFIX_TABLE (PREFIX_0F11) },
2842   { PREFIX_TABLE (PREFIX_0F12) },
2843   { MOD_TABLE (MOD_0F13) },
2844   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2845   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2846   { PREFIX_TABLE (PREFIX_0F16) },
2847   { MOD_TABLE (MOD_0F17) },
2848   /* 18 */
2849   { REG_TABLE (REG_0F18) },
2850   { "nopQ",             { Ev }, 0 },
2851   { PREFIX_TABLE (PREFIX_0F1A) },
2852   { PREFIX_TABLE (PREFIX_0F1B) },
2853   { "nopQ",             { Ev }, 0 },
2854   { "nopQ",             { Ev }, 0 },
2855   { PREFIX_TABLE (PREFIX_0F1E) },
2856   { "nopQ",             { Ev }, 0 },
2857   /* 20 */
2858   { "movZ",             { Rm, Cm }, 0 },
2859   { "movZ",             { Rm, Dm }, 0 },
2860   { "movZ",             { Cm, Rm }, 0 },
2861   { "movZ",             { Dm, Rm }, 0 },
2862   { MOD_TABLE (MOD_0F24) },
2863   { Bad_Opcode },
2864   { MOD_TABLE (MOD_0F26) },
2865   { Bad_Opcode },
2866   /* 28 */
2867   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2868   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2869   { PREFIX_TABLE (PREFIX_0F2A) },
2870   { PREFIX_TABLE (PREFIX_0F2B) },
2871   { PREFIX_TABLE (PREFIX_0F2C) },
2872   { PREFIX_TABLE (PREFIX_0F2D) },
2873   { PREFIX_TABLE (PREFIX_0F2E) },
2874   { PREFIX_TABLE (PREFIX_0F2F) },
2875   /* 30 */
2876   { "wrmsr",            { XX }, 0 },
2877   { "rdtsc",            { XX }, 0 },
2878   { "rdmsr",            { XX }, 0 },
2879   { "rdpmc",            { XX }, 0 },
2880   { "sysenter",         { XX }, 0 },
2881   { "sysexit",          { XX }, 0 },
2882   { Bad_Opcode },
2883   { "getsec",           { XX }, 0 },
2884   /* 38 */
2885   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2886   { Bad_Opcode },
2887   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2888   { Bad_Opcode },
2889   { Bad_Opcode },
2890   { Bad_Opcode },
2891   { Bad_Opcode },
2892   { Bad_Opcode },
2893   /* 40 */
2894   { "cmovoS",           { Gv, Ev }, 0 },
2895   { "cmovnoS",          { Gv, Ev }, 0 },
2896   { "cmovbS",           { Gv, Ev }, 0 },
2897   { "cmovaeS",          { Gv, Ev }, 0 },
2898   { "cmoveS",           { Gv, Ev }, 0 },
2899   { "cmovneS",          { Gv, Ev }, 0 },
2900   { "cmovbeS",          { Gv, Ev }, 0 },
2901   { "cmovaS",           { Gv, Ev }, 0 },
2902   /* 48 */
2903   { "cmovsS",           { Gv, Ev }, 0 },
2904   { "cmovnsS",          { Gv, Ev }, 0 },
2905   { "cmovpS",           { Gv, Ev }, 0 },
2906   { "cmovnpS",          { Gv, Ev }, 0 },
2907   { "cmovlS",           { Gv, Ev }, 0 },
2908   { "cmovgeS",          { Gv, Ev }, 0 },
2909   { "cmovleS",          { Gv, Ev }, 0 },
2910   { "cmovgS",           { Gv, Ev }, 0 },
2911   /* 50 */
2912   { MOD_TABLE (MOD_0F51) },
2913   { PREFIX_TABLE (PREFIX_0F51) },
2914   { PREFIX_TABLE (PREFIX_0F52) },
2915   { PREFIX_TABLE (PREFIX_0F53) },
2916   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2917   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2918   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2919   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2920   /* 58 */
2921   { PREFIX_TABLE (PREFIX_0F58) },
2922   { PREFIX_TABLE (PREFIX_0F59) },
2923   { PREFIX_TABLE (PREFIX_0F5A) },
2924   { PREFIX_TABLE (PREFIX_0F5B) },
2925   { PREFIX_TABLE (PREFIX_0F5C) },
2926   { PREFIX_TABLE (PREFIX_0F5D) },
2927   { PREFIX_TABLE (PREFIX_0F5E) },
2928   { PREFIX_TABLE (PREFIX_0F5F) },
2929   /* 60 */
2930   { PREFIX_TABLE (PREFIX_0F60) },
2931   { PREFIX_TABLE (PREFIX_0F61) },
2932   { PREFIX_TABLE (PREFIX_0F62) },
2933   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2934   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2935   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2936   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2937   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2938   /* 68 */
2939   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2940   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2941   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2942   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2943   { PREFIX_TABLE (PREFIX_0F6C) },
2944   { PREFIX_TABLE (PREFIX_0F6D) },
2945   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2946   { PREFIX_TABLE (PREFIX_0F6F) },
2947   /* 70 */
2948   { PREFIX_TABLE (PREFIX_0F70) },
2949   { REG_TABLE (REG_0F71) },
2950   { REG_TABLE (REG_0F72) },
2951   { REG_TABLE (REG_0F73) },
2952   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2953   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2954   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2955   { "emms",             { XX }, PREFIX_OPCODE },
2956   /* 78 */
2957   { PREFIX_TABLE (PREFIX_0F78) },
2958   { PREFIX_TABLE (PREFIX_0F79) },
2959   { Bad_Opcode },
2960   { Bad_Opcode },
2961   { PREFIX_TABLE (PREFIX_0F7C) },
2962   { PREFIX_TABLE (PREFIX_0F7D) },
2963   { PREFIX_TABLE (PREFIX_0F7E) },
2964   { PREFIX_TABLE (PREFIX_0F7F) },
2965   /* 80 */
2966   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2967   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2968   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2969   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2970   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2971   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2972   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2973   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2974   /* 88 */
2975   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2976   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2977   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2978   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2979   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2980   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2981   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2982   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2983   /* 90 */
2984   { "seto",             { Eb }, 0 },
2985   { "setno",            { Eb }, 0 },
2986   { "setb",             { Eb }, 0 },
2987   { "setae",            { Eb }, 0 },
2988   { "sete",             { Eb }, 0 },
2989   { "setne",            { Eb }, 0 },
2990   { "setbe",            { Eb }, 0 },
2991   { "seta",             { Eb }, 0 },
2992   /* 98 */
2993   { "sets",             { Eb }, 0 },
2994   { "setns",            { Eb }, 0 },
2995   { "setp",             { Eb }, 0 },
2996   { "setnp",            { Eb }, 0 },
2997   { "setl",             { Eb }, 0 },
2998   { "setge",            { Eb }, 0 },
2999   { "setle",            { Eb }, 0 },
3000   { "setg",             { Eb }, 0 },
3001   /* a0 */
3002   { "pushT",            { fs }, 0 },
3003   { "popT",             { fs }, 0 },
3004   { "cpuid",            { XX }, 0 },
3005   { "btS",              { Ev, Gv }, 0 },
3006   { "shldS",            { Ev, Gv, Ib }, 0 },
3007   { "shldS",            { Ev, Gv, CL }, 0 },
3008   { REG_TABLE (REG_0FA6) },
3009   { REG_TABLE (REG_0FA7) },
3010   /* a8 */
3011   { "pushT",            { gs }, 0 },
3012   { "popT",             { gs }, 0 },
3013   { "rsm",              { XX }, 0 },
3014   { "btsS",             { Evh1, Gv }, 0 },
3015   { "shrdS",            { Ev, Gv, Ib }, 0 },
3016   { "shrdS",            { Ev, Gv, CL }, 0 },
3017   { REG_TABLE (REG_0FAE) },
3018   { "imulS",            { Gv, Ev }, 0 },
3019   /* b0 */
3020   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3021   { "cmpxchgS",         { Evh1, Gv }, 0 },
3022   { MOD_TABLE (MOD_0FB2) },
3023   { "btrS",             { Evh1, Gv }, 0 },
3024   { MOD_TABLE (MOD_0FB4) },
3025   { MOD_TABLE (MOD_0FB5) },
3026   { "movz{bR|x}",       { Gv, Eb }, 0 },
3027   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3028   /* b8 */
3029   { PREFIX_TABLE (PREFIX_0FB8) },
3030   { "ud1",              { XX }, 0 },
3031   { REG_TABLE (REG_0FBA) },
3032   { "btcS",             { Evh1, Gv }, 0 },
3033   { PREFIX_TABLE (PREFIX_0FBC) },
3034   { PREFIX_TABLE (PREFIX_0FBD) },
3035   { "movs{bR|x}",       { Gv, Eb }, 0 },
3036   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3037   /* c0 */
3038   { "xaddB",            { Ebh1, Gb }, 0 },
3039   { "xaddS",            { Evh1, Gv }, 0 },
3040   { PREFIX_TABLE (PREFIX_0FC2) },
3041   { MOD_TABLE (MOD_0FC3) },
3042   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3043   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3044   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3045   { REG_TABLE (REG_0FC7) },
3046   /* c8 */
3047   { "bswap",            { RMeAX }, 0 },
3048   { "bswap",            { RMeCX }, 0 },
3049   { "bswap",            { RMeDX }, 0 },
3050   { "bswap",            { RMeBX }, 0 },
3051   { "bswap",            { RMeSP }, 0 },
3052   { "bswap",            { RMeBP }, 0 },
3053   { "bswap",            { RMeSI }, 0 },
3054   { "bswap",            { RMeDI }, 0 },
3055   /* d0 */
3056   { PREFIX_TABLE (PREFIX_0FD0) },
3057   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3058   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3059   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3060   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3061   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3062   { PREFIX_TABLE (PREFIX_0FD6) },
3063   { MOD_TABLE (MOD_0FD7) },
3064   /* d8 */
3065   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3066   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3067   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3068   { "pand",             { MX, EM }, PREFIX_OPCODE },
3069   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3070   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3071   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3072   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3073   /* e0 */
3074   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3075   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3076   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3077   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3078   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3079   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3080   { PREFIX_TABLE (PREFIX_0FE6) },
3081   { PREFIX_TABLE (PREFIX_0FE7) },
3082   /* e8 */
3083   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3084   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3085   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3086   { "por",              { MX, EM }, PREFIX_OPCODE },
3087   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3088   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3089   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3090   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3091   /* f0 */
3092   { PREFIX_TABLE (PREFIX_0FF0) },
3093   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3094   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3095   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3096   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3097   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3098   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3099   { PREFIX_TABLE (PREFIX_0FF7) },
3100   /* f8 */
3101   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3102   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3103   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3104   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3105   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3106   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3107   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3108   { Bad_Opcode },
3109 };
3110
3111 static const unsigned char onebyte_has_modrm[256] = {
3112   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3113   /*       -------------------------------        */
3114   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3115   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3116   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3117   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3118   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3119   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3120   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3121   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3122   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3123   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3124   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3125   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3126   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3127   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3128   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3129   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3130   /*       -------------------------------        */
3131   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3132 };
3133
3134 static const unsigned char twobyte_has_modrm[256] = {
3135   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3136   /*       -------------------------------        */
3137   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3138   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3139   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3140   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3141   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3142   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3143   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3144   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3145   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3146   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3147   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3148   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3149   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3150   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3151   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3152   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3153   /*       -------------------------------        */
3154   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3155 };
3156
3157 static char obuf[100];
3158 static char *obufp;
3159 static char *mnemonicendp;
3160 static char scratchbuf[100];
3161 static unsigned char *start_codep;
3162 static unsigned char *insn_codep;
3163 static unsigned char *codep;
3164 static unsigned char *end_codep;
3165 static int last_lock_prefix;
3166 static int last_repz_prefix;
3167 static int last_repnz_prefix;
3168 static int last_data_prefix;
3169 static int last_addr_prefix;
3170 static int last_rex_prefix;
3171 static int last_seg_prefix;
3172 static int fwait_prefix;
3173 /* The active segment register prefix.  */
3174 static int active_seg_prefix;
3175 #define MAX_CODE_LENGTH 15
3176 /* We can up to 14 prefixes since the maximum instruction length is
3177    15bytes.  */
3178 static int all_prefixes[MAX_CODE_LENGTH - 1];
3179 static disassemble_info *the_info;
3180 static struct
3181   {
3182     int mod;
3183     int reg;
3184     int rm;
3185   }
3186 modrm;
3187 static unsigned char need_modrm;
3188 static struct
3189   {
3190     int scale;
3191     int index;
3192     int base;
3193   }
3194 sib;
3195 static struct
3196   {
3197     int register_specifier;
3198     int length;
3199     int prefix;
3200     int w;
3201     int evex;
3202     int r;
3203     int v;
3204     int mask_register_specifier;
3205     int zeroing;
3206     int ll;
3207     int b;
3208   }
3209 vex;
3210 static unsigned char need_vex;
3211 static unsigned char need_vex_reg;
3212 static unsigned char vex_w_done;
3213
3214 struct op
3215   {
3216     const char *name;
3217     unsigned int len;
3218   };
3219
3220 /* If we are accessing mod/rm/reg without need_modrm set, then the
3221    values are stale.  Hitting this abort likely indicates that you
3222    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3223 #define MODRM_CHECK  if (!need_modrm) abort ()
3224
3225 static const char **names64;
3226 static const char **names32;
3227 static const char **names16;
3228 static const char **names8;
3229 static const char **names8rex;
3230 static const char **names_seg;
3231 static const char *index64;
3232 static const char *index32;
3233 static const char **index16;
3234 static const char **names_bnd;
3235
3236 static const char *intel_names64[] = {
3237   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3238   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3239 };
3240 static const char *intel_names32[] = {
3241   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3242   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3243 };
3244 static const char *intel_names16[] = {
3245   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3246   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3247 };
3248 static const char *intel_names8[] = {
3249   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3250 };
3251 static const char *intel_names8rex[] = {
3252   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3253   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3254 };
3255 static const char *intel_names_seg[] = {
3256   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3257 };
3258 static const char *intel_index64 = "riz";
3259 static const char *intel_index32 = "eiz";
3260 static const char *intel_index16[] = {
3261   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3262 };
3263
3264 static const char *att_names64[] = {
3265   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3266   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3267 };
3268 static const char *att_names32[] = {
3269   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3270   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3271 };
3272 static const char *att_names16[] = {
3273   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3274   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3275 };
3276 static const char *att_names8[] = {
3277   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3278 };
3279 static const char *att_names8rex[] = {
3280   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3281   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3282 };
3283 static const char *att_names_seg[] = {
3284   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3285 };
3286 static const char *att_index64 = "%riz";
3287 static const char *att_index32 = "%eiz";
3288 static const char *att_index16[] = {
3289   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3290 };
3291
3292 static const char **names_mm;
3293 static const char *intel_names_mm[] = {
3294   "mm0", "mm1", "mm2", "mm3",
3295   "mm4", "mm5", "mm6", "mm7"
3296 };
3297 static const char *att_names_mm[] = {
3298   "%mm0", "%mm1", "%mm2", "%mm3",
3299   "%mm4", "%mm5", "%mm6", "%mm7"
3300 };
3301
3302 static const char *intel_names_bnd[] = {
3303   "bnd0", "bnd1", "bnd2", "bnd3"
3304 };
3305
3306 static const char *att_names_bnd[] = {
3307   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3308 };
3309
3310 static const char **names_xmm;
3311 static const char *intel_names_xmm[] = {
3312   "xmm0", "xmm1", "xmm2", "xmm3",
3313   "xmm4", "xmm5", "xmm6", "xmm7",
3314   "xmm8", "xmm9", "xmm10", "xmm11",
3315   "xmm12", "xmm13", "xmm14", "xmm15",
3316   "xmm16", "xmm17", "xmm18", "xmm19",
3317   "xmm20", "xmm21", "xmm22", "xmm23",
3318   "xmm24", "xmm25", "xmm26", "xmm27",
3319   "xmm28", "xmm29", "xmm30", "xmm31"
3320 };
3321 static const char *att_names_xmm[] = {
3322   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3323   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3324   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3325   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3326   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3327   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3328   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3329   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3330 };
3331
3332 static const char **names_ymm;
3333 static const char *intel_names_ymm[] = {
3334   "ymm0", "ymm1", "ymm2", "ymm3",
3335   "ymm4", "ymm5", "ymm6", "ymm7",
3336   "ymm8", "ymm9", "ymm10", "ymm11",
3337   "ymm12", "ymm13", "ymm14", "ymm15",
3338   "ymm16", "ymm17", "ymm18", "ymm19",
3339   "ymm20", "ymm21", "ymm22", "ymm23",
3340   "ymm24", "ymm25", "ymm26", "ymm27",
3341   "ymm28", "ymm29", "ymm30", "ymm31"
3342 };
3343 static const char *att_names_ymm[] = {
3344   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3345   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3346   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3347   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3348   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3349   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3350   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3351   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3352 };
3353
3354 static const char **names_zmm;
3355 static const char *intel_names_zmm[] = {
3356   "zmm0", "zmm1", "zmm2", "zmm3",
3357   "zmm4", "zmm5", "zmm6", "zmm7",
3358   "zmm8", "zmm9", "zmm10", "zmm11",
3359   "zmm12", "zmm13", "zmm14", "zmm15",
3360   "zmm16", "zmm17", "zmm18", "zmm19",
3361   "zmm20", "zmm21", "zmm22", "zmm23",
3362   "zmm24", "zmm25", "zmm26", "zmm27",
3363   "zmm28", "zmm29", "zmm30", "zmm31"
3364 };
3365 static const char *att_names_zmm[] = {
3366   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3367   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3368   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3369   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3370   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3371   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3372   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3373   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3374 };
3375
3376 static const char **names_mask;
3377 static const char *intel_names_mask[] = {
3378   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3379 };
3380 static const char *att_names_mask[] = {
3381   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3382 };
3383
3384 static const char *names_rounding[] =
3385 {
3386   "{rn-sae}",
3387   "{rd-sae}",
3388   "{ru-sae}",
3389   "{rz-sae}"
3390 };
3391
3392 static const struct dis386 reg_table[][8] = {
3393   /* REG_80 */
3394   {
3395     { "addA",   { Ebh1, Ib }, 0 },
3396     { "orA",    { Ebh1, Ib }, 0 },
3397     { "adcA",   { Ebh1, Ib }, 0 },
3398     { "sbbA",   { Ebh1, Ib }, 0 },
3399     { "andA",   { Ebh1, Ib }, 0 },
3400     { "subA",   { Ebh1, Ib }, 0 },
3401     { "xorA",   { Ebh1, Ib }, 0 },
3402     { "cmpA",   { Eb, Ib }, 0 },
3403   },
3404   /* REG_81 */
3405   {
3406     { "addQ",   { Evh1, Iv }, 0 },
3407     { "orQ",    { Evh1, Iv }, 0 },
3408     { "adcQ",   { Evh1, Iv }, 0 },
3409     { "sbbQ",   { Evh1, Iv }, 0 },
3410     { "andQ",   { Evh1, Iv }, 0 },
3411     { "subQ",   { Evh1, Iv }, 0 },
3412     { "xorQ",   { Evh1, Iv }, 0 },
3413     { "cmpQ",   { Ev, Iv }, 0 },
3414   },
3415   /* REG_83 */
3416   {
3417     { "addQ",   { Evh1, sIb }, 0 },
3418     { "orQ",    { Evh1, sIb }, 0 },
3419     { "adcQ",   { Evh1, sIb }, 0 },
3420     { "sbbQ",   { Evh1, sIb }, 0 },
3421     { "andQ",   { Evh1, sIb }, 0 },
3422     { "subQ",   { Evh1, sIb }, 0 },
3423     { "xorQ",   { Evh1, sIb }, 0 },
3424     { "cmpQ",   { Ev, sIb }, 0 },
3425   },
3426   /* REG_8F */
3427   {
3428     { "popU",   { stackEv }, 0 },
3429     { XOP_8F_TABLE (XOP_09) },
3430     { Bad_Opcode },
3431     { Bad_Opcode },
3432     { Bad_Opcode },
3433     { XOP_8F_TABLE (XOP_09) },
3434   },
3435   /* REG_C0 */
3436   {
3437     { "rolA",   { Eb, Ib }, 0 },
3438     { "rorA",   { Eb, Ib }, 0 },
3439     { "rclA",   { Eb, Ib }, 0 },
3440     { "rcrA",   { Eb, Ib }, 0 },
3441     { "shlA",   { Eb, Ib }, 0 },
3442     { "shrA",   { Eb, Ib }, 0 },
3443     { "shlA",   { Eb, Ib }, 0 },
3444     { "sarA",   { Eb, Ib }, 0 },
3445   },
3446   /* REG_C1 */
3447   {
3448     { "rolQ",   { Ev, Ib }, 0 },
3449     { "rorQ",   { Ev, Ib }, 0 },
3450     { "rclQ",   { Ev, Ib }, 0 },
3451     { "rcrQ",   { Ev, Ib }, 0 },
3452     { "shlQ",   { Ev, Ib }, 0 },
3453     { "shrQ",   { Ev, Ib }, 0 },
3454     { "shlQ",   { Ev, Ib }, 0 },
3455     { "sarQ",   { Ev, Ib }, 0 },
3456   },
3457   /* REG_C6 */
3458   {
3459     { "movA",   { Ebh3, Ib }, 0 },
3460     { Bad_Opcode },
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { Bad_Opcode },
3464     { Bad_Opcode },
3465     { Bad_Opcode },
3466     { MOD_TABLE (MOD_C6_REG_7) },
3467   },
3468   /* REG_C7 */
3469   {
3470     { "movQ",   { Evh3, Iv }, 0 },
3471     { Bad_Opcode },
3472     { Bad_Opcode },
3473     { Bad_Opcode },
3474     { Bad_Opcode },
3475     { Bad_Opcode },
3476     { Bad_Opcode },
3477     { MOD_TABLE (MOD_C7_REG_7) },
3478   },
3479   /* REG_D0 */
3480   {
3481     { "rolA",   { Eb, I1 }, 0 },
3482     { "rorA",   { Eb, I1 }, 0 },
3483     { "rclA",   { Eb, I1 }, 0 },
3484     { "rcrA",   { Eb, I1 }, 0 },
3485     { "shlA",   { Eb, I1 }, 0 },
3486     { "shrA",   { Eb, I1 }, 0 },
3487     { "shlA",   { Eb, I1 }, 0 },
3488     { "sarA",   { Eb, I1 }, 0 },
3489   },
3490   /* REG_D1 */
3491   {
3492     { "rolQ",   { Ev, I1 }, 0 },
3493     { "rorQ",   { Ev, I1 }, 0 },
3494     { "rclQ",   { Ev, I1 }, 0 },
3495     { "rcrQ",   { Ev, I1 }, 0 },
3496     { "shlQ",   { Ev, I1 }, 0 },
3497     { "shrQ",   { Ev, I1 }, 0 },
3498     { "shlQ",   { Ev, I1 }, 0 },
3499     { "sarQ",   { Ev, I1 }, 0 },
3500   },
3501   /* REG_D2 */
3502   {
3503     { "rolA",   { Eb, CL }, 0 },
3504     { "rorA",   { Eb, CL }, 0 },
3505     { "rclA",   { Eb, CL }, 0 },
3506     { "rcrA",   { Eb, CL }, 0 },
3507     { "shlA",   { Eb, CL }, 0 },
3508     { "shrA",   { Eb, CL }, 0 },
3509     { "shlA",   { Eb, CL }, 0 },
3510     { "sarA",   { Eb, CL }, 0 },
3511   },
3512   /* REG_D3 */
3513   {
3514     { "rolQ",   { Ev, CL }, 0 },
3515     { "rorQ",   { Ev, CL }, 0 },
3516     { "rclQ",   { Ev, CL }, 0 },
3517     { "rcrQ",   { Ev, CL }, 0 },
3518     { "shlQ",   { Ev, CL }, 0 },
3519     { "shrQ",   { Ev, CL }, 0 },
3520     { "shlQ",   { Ev, CL }, 0 },
3521     { "sarQ",   { Ev, CL }, 0 },
3522   },
3523   /* REG_F6 */
3524   {
3525     { "testA",  { Eb, Ib }, 0 },
3526     { "testA",  { Eb, Ib }, 0 },
3527     { "notA",   { Ebh1 }, 0 },
3528     { "negA",   { Ebh1 }, 0 },
3529     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3530     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3531     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3532     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3533   },
3534   /* REG_F7 */
3535   {
3536     { "testQ",  { Ev, Iv }, 0 },
3537     { "testQ",  { Ev, Iv }, 0 },
3538     { "notQ",   { Evh1 }, 0 },
3539     { "negQ",   { Evh1 }, 0 },
3540     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3541     { "imulQ",  { Ev }, 0 },
3542     { "divQ",   { Ev }, 0 },
3543     { "idivQ",  { Ev }, 0 },
3544   },
3545   /* REG_FE */
3546   {
3547     { "incA",   { Ebh1 }, 0 },
3548     { "decA",   { Ebh1 }, 0 },
3549   },
3550   /* REG_FF */
3551   {
3552     { "incQ",   { Evh1 }, 0 },
3553     { "decQ",   { Evh1 }, 0 },
3554     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3555     { MOD_TABLE (MOD_FF_REG_3) },
3556     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3557     { MOD_TABLE (MOD_FF_REG_5) },
3558     { "pushU",  { stackEv }, 0 },
3559     { Bad_Opcode },
3560   },
3561   /* REG_0F00 */
3562   {
3563     { "sldtD",  { Sv }, 0 },
3564     { "strD",   { Sv }, 0 },
3565     { "lldt",   { Ew }, 0 },
3566     { "ltr",    { Ew }, 0 },
3567     { "verr",   { Ew }, 0 },
3568     { "verw",   { Ew }, 0 },
3569     { Bad_Opcode },
3570     { Bad_Opcode },
3571   },
3572   /* REG_0F01 */
3573   {
3574     { MOD_TABLE (MOD_0F01_REG_0) },
3575     { MOD_TABLE (MOD_0F01_REG_1) },
3576     { MOD_TABLE (MOD_0F01_REG_2) },
3577     { MOD_TABLE (MOD_0F01_REG_3) },
3578     { "smswD",  { Sv }, 0 },
3579     { MOD_TABLE (MOD_0F01_REG_5) },
3580     { "lmsw",   { Ew }, 0 },
3581     { MOD_TABLE (MOD_0F01_REG_7) },
3582   },
3583   /* REG_0F0D */
3584   {
3585     { "prefetch",       { Mb }, 0 },
3586     { "prefetchw",      { Mb }, 0 },
3587     { "prefetchwt1",    { Mb }, 0 },
3588     { "prefetch",       { Mb }, 0 },
3589     { "prefetch",       { Mb }, 0 },
3590     { "prefetch",       { Mb }, 0 },
3591     { "prefetch",       { Mb }, 0 },
3592     { "prefetch",       { Mb }, 0 },
3593   },
3594   /* REG_0F18 */
3595   {
3596     { MOD_TABLE (MOD_0F18_REG_0) },
3597     { MOD_TABLE (MOD_0F18_REG_1) },
3598     { MOD_TABLE (MOD_0F18_REG_2) },
3599     { MOD_TABLE (MOD_0F18_REG_3) },
3600     { MOD_TABLE (MOD_0F18_REG_4) },
3601     { MOD_TABLE (MOD_0F18_REG_5) },
3602     { MOD_TABLE (MOD_0F18_REG_6) },
3603     { MOD_TABLE (MOD_0F18_REG_7) },
3604   },
3605   /* REG_0F1E_MOD_3 */
3606   {
3607     { "nopQ",           { Ev }, 0 },
3608     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3609     { "nopQ",           { Ev }, 0 },
3610     { "nopQ",           { Ev }, 0 },
3611     { "nopQ",           { Ev }, 0 },
3612     { "nopQ",           { Ev }, 0 },
3613     { "nopQ",           { Ev }, 0 },
3614     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3615   },
3616   /* REG_0F71 */
3617   {
3618     { Bad_Opcode },
3619     { Bad_Opcode },
3620     { MOD_TABLE (MOD_0F71_REG_2) },
3621     { Bad_Opcode },
3622     { MOD_TABLE (MOD_0F71_REG_4) },
3623     { Bad_Opcode },
3624     { MOD_TABLE (MOD_0F71_REG_6) },
3625   },
3626   /* REG_0F72 */
3627   {
3628     { Bad_Opcode },
3629     { Bad_Opcode },
3630     { MOD_TABLE (MOD_0F72_REG_2) },
3631     { Bad_Opcode },
3632     { MOD_TABLE (MOD_0F72_REG_4) },
3633     { Bad_Opcode },
3634     { MOD_TABLE (MOD_0F72_REG_6) },
3635   },
3636   /* REG_0F73 */
3637   {
3638     { Bad_Opcode },
3639     { Bad_Opcode },
3640     { MOD_TABLE (MOD_0F73_REG_2) },
3641     { MOD_TABLE (MOD_0F73_REG_3) },
3642     { Bad_Opcode },
3643     { Bad_Opcode },
3644     { MOD_TABLE (MOD_0F73_REG_6) },
3645     { MOD_TABLE (MOD_0F73_REG_7) },
3646   },
3647   /* REG_0FA6 */
3648   {
3649     { "montmul",        { { OP_0f07, 0 } }, 0 },
3650     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3651     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3652   },
3653   /* REG_0FA7 */
3654   {
3655     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3656     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3657     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3658     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3659     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3660     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3661   },
3662   /* REG_0FAE */
3663   {
3664     { MOD_TABLE (MOD_0FAE_REG_0) },
3665     { MOD_TABLE (MOD_0FAE_REG_1) },
3666     { MOD_TABLE (MOD_0FAE_REG_2) },
3667     { MOD_TABLE (MOD_0FAE_REG_3) },
3668     { MOD_TABLE (MOD_0FAE_REG_4) },
3669     { MOD_TABLE (MOD_0FAE_REG_5) },
3670     { MOD_TABLE (MOD_0FAE_REG_6) },
3671     { MOD_TABLE (MOD_0FAE_REG_7) },
3672   },
3673   /* REG_0FBA */
3674   {
3675     { Bad_Opcode },
3676     { Bad_Opcode },
3677     { Bad_Opcode },
3678     { Bad_Opcode },
3679     { "btQ",    { Ev, Ib }, 0 },
3680     { "btsQ",   { Evh1, Ib }, 0 },
3681     { "btrQ",   { Evh1, Ib }, 0 },
3682     { "btcQ",   { Evh1, Ib }, 0 },
3683   },
3684   /* REG_0FC7 */
3685   {
3686     { Bad_Opcode },
3687     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3688     { Bad_Opcode },
3689     { MOD_TABLE (MOD_0FC7_REG_3) },
3690     { MOD_TABLE (MOD_0FC7_REG_4) },
3691     { MOD_TABLE (MOD_0FC7_REG_5) },
3692     { MOD_TABLE (MOD_0FC7_REG_6) },
3693     { MOD_TABLE (MOD_0FC7_REG_7) },
3694   },
3695   /* REG_VEX_0F71 */
3696   {
3697     { Bad_Opcode },
3698     { Bad_Opcode },
3699     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3700     { Bad_Opcode },
3701     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3702     { Bad_Opcode },
3703     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3704   },
3705   /* REG_VEX_0F72 */
3706   {
3707     { Bad_Opcode },
3708     { Bad_Opcode },
3709     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3710     { Bad_Opcode },
3711     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3712     { Bad_Opcode },
3713     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3714   },
3715   /* REG_VEX_0F73 */
3716   {
3717     { Bad_Opcode },
3718     { Bad_Opcode },
3719     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3720     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3721     { Bad_Opcode },
3722     { Bad_Opcode },
3723     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3724     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3725   },
3726   /* REG_VEX_0FAE */
3727   {
3728     { Bad_Opcode },
3729     { Bad_Opcode },
3730     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3731     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3732   },
3733   /* REG_VEX_0F38F3 */
3734   {
3735     { Bad_Opcode },
3736     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3737     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3738     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3739   },
3740   /* REG_XOP_LWPCB */
3741   {
3742     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3743     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3744   },
3745   /* REG_XOP_LWP */
3746   {
3747     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3748     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3749   },
3750   /* REG_XOP_TBM_01 */
3751   {
3752     { Bad_Opcode },
3753     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3754     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3755     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3756     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3757     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3758     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3759     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3760   },
3761   /* REG_XOP_TBM_02 */
3762   {
3763     { Bad_Opcode },
3764     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3765     { Bad_Opcode },
3766     { Bad_Opcode },
3767     { Bad_Opcode },
3768     { Bad_Opcode },
3769     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3770   },
3771 #define NEED_REG_TABLE
3772 #include "i386-dis-evex.h"
3773 #undef NEED_REG_TABLE
3774 };
3775
3776 static const struct dis386 prefix_table[][4] = {
3777   /* PREFIX_90 */
3778   {
3779     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3780     { "pause", { XX }, 0 },
3781     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3782     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3783   },
3784
3785   /* PREFIX_MOD_0_0F01_REG_5 */
3786   {
3787     { Bad_Opcode },
3788     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3789   },
3790
3791   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3792   {
3793     { Bad_Opcode },
3794     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3795   },
3796
3797   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3798   {
3799     { Bad_Opcode },
3800     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3801   },
3802
3803   /* PREFIX_0F10 */
3804   {
3805     { "movups", { XM, EXx }, PREFIX_OPCODE },
3806     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3807     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3808     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3809   },
3810
3811   /* PREFIX_0F11 */
3812   {
3813     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3814     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3815     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3816     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3817   },
3818
3819   /* PREFIX_0F12 */
3820   {
3821     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3822     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3823     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3824     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3825   },
3826
3827   /* PREFIX_0F16 */
3828   {
3829     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3830     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3831     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3832   },
3833
3834   /* PREFIX_0F1A */
3835   {
3836     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3837     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3838     { "bndmov", { Gbnd, Ebnd }, 0 },
3839     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3840   },
3841
3842   /* PREFIX_0F1B */
3843   {
3844     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3845     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3846     { "bndmov", { Ebnd, Gbnd }, 0 },
3847     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3848   },
3849
3850   /* PREFIX_0F1E */
3851   {
3852     { "nopQ",   { Ev }, PREFIX_OPCODE },
3853     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3854     { "nopQ",   { Ev }, PREFIX_OPCODE },
3855     { "nopQ",   { Ev }, PREFIX_OPCODE },
3856   },
3857
3858   /* PREFIX_0F2A */
3859   {
3860     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3861     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3862     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3863     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3864   },
3865
3866   /* PREFIX_0F2B */
3867   {
3868     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3869     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3870     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3871     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3872   },
3873
3874   /* PREFIX_0F2C */
3875   {
3876     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3877     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3878     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3879     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3880   },
3881
3882   /* PREFIX_0F2D */
3883   {
3884     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3885     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3886     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3887     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3888   },
3889
3890   /* PREFIX_0F2E */
3891   {
3892     { "ucomiss",{ XM, EXd }, 0 },
3893     { Bad_Opcode },
3894     { "ucomisd",{ XM, EXq }, 0 },
3895   },
3896
3897   /* PREFIX_0F2F */
3898   {
3899     { "comiss", { XM, EXd }, 0 },
3900     { Bad_Opcode },
3901     { "comisd", { XM, EXq }, 0 },
3902   },
3903
3904   /* PREFIX_0F51 */
3905   {
3906     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3907     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3908     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3909     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3910   },
3911
3912   /* PREFIX_0F52 */
3913   {
3914     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3915     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3916   },
3917
3918   /* PREFIX_0F53 */
3919   {
3920     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3921     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3922   },
3923
3924   /* PREFIX_0F58 */
3925   {
3926     { "addps", { XM, EXx }, PREFIX_OPCODE },
3927     { "addss", { XM, EXd }, PREFIX_OPCODE },
3928     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3929     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3930   },
3931
3932   /* PREFIX_0F59 */
3933   {
3934     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3935     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3936     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3937     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3938   },
3939
3940   /* PREFIX_0F5A */
3941   {
3942     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3943     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3944     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3945     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3946   },
3947
3948   /* PREFIX_0F5B */
3949   {
3950     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3951     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3952     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3953   },
3954
3955   /* PREFIX_0F5C */
3956   {
3957     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3958     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3959     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3960     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3961   },
3962
3963   /* PREFIX_0F5D */
3964   {
3965     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3966     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3967     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3968     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3969   },
3970
3971   /* PREFIX_0F5E */
3972   {
3973     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3974     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3975     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3976     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3977   },
3978
3979   /* PREFIX_0F5F */
3980   {
3981     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3982     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3983     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3984     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3985   },
3986
3987   /* PREFIX_0F60 */
3988   {
3989     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3990     { Bad_Opcode },
3991     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3992   },
3993
3994   /* PREFIX_0F61 */
3995   {
3996     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3997     { Bad_Opcode },
3998     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3999   },
4000
4001   /* PREFIX_0F62 */
4002   {
4003     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4004     { Bad_Opcode },
4005     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4006   },
4007
4008   /* PREFIX_0F6C */
4009   {
4010     { Bad_Opcode },
4011     { Bad_Opcode },
4012     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4013   },
4014
4015   /* PREFIX_0F6D */
4016   {
4017     { Bad_Opcode },
4018     { Bad_Opcode },
4019     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4020   },
4021
4022   /* PREFIX_0F6F */
4023   {
4024     { "movq",   { MX, EM }, PREFIX_OPCODE },
4025     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4026     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4027   },
4028
4029   /* PREFIX_0F70 */
4030   {
4031     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4032     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4033     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4034     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4035   },
4036
4037   /* PREFIX_0F73_REG_3 */
4038   {
4039     { Bad_Opcode },
4040     { Bad_Opcode },
4041     { "psrldq", { XS, Ib }, 0 },
4042   },
4043
4044   /* PREFIX_0F73_REG_7 */
4045   {
4046     { Bad_Opcode },
4047     { Bad_Opcode },
4048     { "pslldq", { XS, Ib }, 0 },
4049   },
4050
4051   /* PREFIX_0F78 */
4052   {
4053     {"vmread",  { Em, Gm }, 0 },
4054     { Bad_Opcode },
4055     {"extrq",   { XS, Ib, Ib }, 0 },
4056     {"insertq", { XM, XS, Ib, Ib }, 0 },
4057   },
4058
4059   /* PREFIX_0F79 */
4060   {
4061     {"vmwrite", { Gm, Em }, 0 },
4062     { Bad_Opcode },
4063     {"extrq",   { XM, XS }, 0 },
4064     {"insertq", { XM, XS }, 0 },
4065   },
4066
4067   /* PREFIX_0F7C */
4068   {
4069     { Bad_Opcode },
4070     { Bad_Opcode },
4071     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4072     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4073   },
4074
4075   /* PREFIX_0F7D */
4076   {
4077     { Bad_Opcode },
4078     { Bad_Opcode },
4079     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4080     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4081   },
4082
4083   /* PREFIX_0F7E */
4084   {
4085     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4086     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4087     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4088   },
4089
4090   /* PREFIX_0F7F */
4091   {
4092     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4093     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4094     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4095   },
4096
4097   /* PREFIX_0FAE_REG_0 */
4098   {
4099     { Bad_Opcode },
4100     { "rdfsbase", { Ev }, 0 },
4101   },
4102
4103   /* PREFIX_0FAE_REG_1 */
4104   {
4105     { Bad_Opcode },
4106     { "rdgsbase", { Ev }, 0 },
4107   },
4108
4109   /* PREFIX_0FAE_REG_2 */
4110   {
4111     { Bad_Opcode },
4112     { "wrfsbase", { Ev }, 0 },
4113   },
4114
4115   /* PREFIX_0FAE_REG_3 */
4116   {
4117     { Bad_Opcode },
4118     { "wrgsbase", { Ev }, 0 },
4119   },
4120
4121   /* PREFIX_MOD_0_0FAE_REG_4 */
4122   {
4123     { "xsave",  { FXSAVE }, 0 },
4124     { "ptwrite%LQ", { Edq }, 0 },
4125   },
4126
4127   /* PREFIX_MOD_3_0FAE_REG_4 */
4128   {
4129     { Bad_Opcode },
4130     { "ptwrite%LQ", { Edq }, 0 },
4131   },
4132
4133   /* PREFIX_MOD_0_0FAE_REG_5 */
4134   {
4135     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4136   },
4137
4138   /* PREFIX_MOD_3_0FAE_REG_5 */
4139   {
4140     { "lfence",         { Skip_MODRM }, 0 },
4141     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4142   },
4143
4144   /* PREFIX_0FAE_REG_6 */
4145   {
4146     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4147     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4148     { "clwb",   { Mb }, PREFIX_OPCODE },
4149   },
4150
4151   /* PREFIX_0FAE_REG_7 */
4152   {
4153     { "clflush",        { Mb }, 0 },
4154     { Bad_Opcode },
4155     { "clflushopt",     { Mb }, 0 },
4156   },
4157
4158   /* PREFIX_0FB8 */
4159   {
4160     { Bad_Opcode },
4161     { "popcntS", { Gv, Ev }, 0 },
4162   },
4163
4164   /* PREFIX_0FBC */
4165   {
4166     { "bsfS",   { Gv, Ev }, 0 },
4167     { "tzcntS", { Gv, Ev }, 0 },
4168     { "bsfS",   { Gv, Ev }, 0 },
4169   },
4170
4171   /* PREFIX_0FBD */
4172   {
4173     { "bsrS",   { Gv, Ev }, 0 },
4174     { "lzcntS", { Gv, Ev }, 0 },
4175     { "bsrS",   { Gv, Ev }, 0 },
4176   },
4177
4178   /* PREFIX_0FC2 */
4179   {
4180     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4181     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4182     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4183     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4184   },
4185
4186   /* PREFIX_MOD_0_0FC3 */
4187   {
4188     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4189   },
4190
4191   /* PREFIX_MOD_0_0FC7_REG_6 */
4192   {
4193     { "vmptrld",{ Mq }, 0 },
4194     { "vmxon",  { Mq }, 0 },
4195     { "vmclear",{ Mq }, 0 },
4196   },
4197
4198   /* PREFIX_MOD_3_0FC7_REG_6 */
4199   {
4200     { "rdrand", { Ev }, 0 },
4201     { Bad_Opcode },
4202     { "rdrand", { Ev }, 0 }
4203   },
4204
4205   /* PREFIX_MOD_3_0FC7_REG_7 */
4206   {
4207     { "rdseed", { Ev }, 0 },
4208     { "rdpid",  { Em }, 0 },
4209     { "rdseed", { Ev }, 0 },
4210   },
4211
4212   /* PREFIX_0FD0 */
4213   {
4214     { Bad_Opcode },
4215     { Bad_Opcode },
4216     { "addsubpd", { XM, EXx }, 0 },
4217     { "addsubps", { XM, EXx }, 0 },
4218   },
4219
4220   /* PREFIX_0FD6 */
4221   {
4222     { Bad_Opcode },
4223     { "movq2dq",{ XM, MS }, 0 },
4224     { "movq",   { EXqS, XM }, 0 },
4225     { "movdq2q",{ MX, XS }, 0 },
4226   },
4227
4228   /* PREFIX_0FE6 */
4229   {
4230     { Bad_Opcode },
4231     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4232     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4233     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4234   },
4235
4236   /* PREFIX_0FE7 */
4237   {
4238     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4239     { Bad_Opcode },
4240     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4241   },
4242
4243   /* PREFIX_0FF0 */
4244   {
4245     { Bad_Opcode },
4246     { Bad_Opcode },
4247     { Bad_Opcode },
4248     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4249   },
4250
4251   /* PREFIX_0FF7 */
4252   {
4253     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4254     { Bad_Opcode },
4255     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4256   },
4257
4258   /* PREFIX_0F3810 */
4259   {
4260     { Bad_Opcode },
4261     { Bad_Opcode },
4262     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4263   },
4264
4265   /* PREFIX_0F3814 */
4266   {
4267     { Bad_Opcode },
4268     { Bad_Opcode },
4269     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4270   },
4271
4272   /* PREFIX_0F3815 */
4273   {
4274     { Bad_Opcode },
4275     { Bad_Opcode },
4276     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4277   },
4278
4279   /* PREFIX_0F3817 */
4280   {
4281     { Bad_Opcode },
4282     { Bad_Opcode },
4283     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4284   },
4285
4286   /* PREFIX_0F3820 */
4287   {
4288     { Bad_Opcode },
4289     { Bad_Opcode },
4290     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4291   },
4292
4293   /* PREFIX_0F3821 */
4294   {
4295     { Bad_Opcode },
4296     { Bad_Opcode },
4297     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4298   },
4299
4300   /* PREFIX_0F3822 */
4301   {
4302     { Bad_Opcode },
4303     { Bad_Opcode },
4304     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4305   },
4306
4307   /* PREFIX_0F3823 */
4308   {
4309     { Bad_Opcode },
4310     { Bad_Opcode },
4311     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4312   },
4313
4314   /* PREFIX_0F3824 */
4315   {
4316     { Bad_Opcode },
4317     { Bad_Opcode },
4318     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4319   },
4320
4321   /* PREFIX_0F3825 */
4322   {
4323     { Bad_Opcode },
4324     { Bad_Opcode },
4325     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4326   },
4327
4328   /* PREFIX_0F3828 */
4329   {
4330     { Bad_Opcode },
4331     { Bad_Opcode },
4332     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4333   },
4334
4335   /* PREFIX_0F3829 */
4336   {
4337     { Bad_Opcode },
4338     { Bad_Opcode },
4339     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4340   },
4341
4342   /* PREFIX_0F382A */
4343   {
4344     { Bad_Opcode },
4345     { Bad_Opcode },
4346     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4347   },
4348
4349   /* PREFIX_0F382B */
4350   {
4351     { Bad_Opcode },
4352     { Bad_Opcode },
4353     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4354   },
4355
4356   /* PREFIX_0F3830 */
4357   {
4358     { Bad_Opcode },
4359     { Bad_Opcode },
4360     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4361   },
4362
4363   /* PREFIX_0F3831 */
4364   {
4365     { Bad_Opcode },
4366     { Bad_Opcode },
4367     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4368   },
4369
4370   /* PREFIX_0F3832 */
4371   {
4372     { Bad_Opcode },
4373     { Bad_Opcode },
4374     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4375   },
4376
4377   /* PREFIX_0F3833 */
4378   {
4379     { Bad_Opcode },
4380     { Bad_Opcode },
4381     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4382   },
4383
4384   /* PREFIX_0F3834 */
4385   {
4386     { Bad_Opcode },
4387     { Bad_Opcode },
4388     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4389   },
4390
4391   /* PREFIX_0F3835 */
4392   {
4393     { Bad_Opcode },
4394     { Bad_Opcode },
4395     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4396   },
4397
4398   /* PREFIX_0F3837 */
4399   {
4400     { Bad_Opcode },
4401     { Bad_Opcode },
4402     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4403   },
4404
4405   /* PREFIX_0F3838 */
4406   {
4407     { Bad_Opcode },
4408     { Bad_Opcode },
4409     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4410   },
4411
4412   /* PREFIX_0F3839 */
4413   {
4414     { Bad_Opcode },
4415     { Bad_Opcode },
4416     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4417   },
4418
4419   /* PREFIX_0F383A */
4420   {
4421     { Bad_Opcode },
4422     { Bad_Opcode },
4423     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4424   },
4425
4426   /* PREFIX_0F383B */
4427   {
4428     { Bad_Opcode },
4429     { Bad_Opcode },
4430     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4431   },
4432
4433   /* PREFIX_0F383C */
4434   {
4435     { Bad_Opcode },
4436     { Bad_Opcode },
4437     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4438   },
4439
4440   /* PREFIX_0F383D */
4441   {
4442     { Bad_Opcode },
4443     { Bad_Opcode },
4444     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4445   },
4446
4447   /* PREFIX_0F383E */
4448   {
4449     { Bad_Opcode },
4450     { Bad_Opcode },
4451     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4452   },
4453
4454   /* PREFIX_0F383F */
4455   {
4456     { Bad_Opcode },
4457     { Bad_Opcode },
4458     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4459   },
4460
4461   /* PREFIX_0F3840 */
4462   {
4463     { Bad_Opcode },
4464     { Bad_Opcode },
4465     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4466   },
4467
4468   /* PREFIX_0F3841 */
4469   {
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4473   },
4474
4475   /* PREFIX_0F3880 */
4476   {
4477     { Bad_Opcode },
4478     { Bad_Opcode },
4479     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4480   },
4481
4482   /* PREFIX_0F3881 */
4483   {
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4487   },
4488
4489   /* PREFIX_0F3882 */
4490   {
4491     { Bad_Opcode },
4492     { Bad_Opcode },
4493     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4494   },
4495
4496   /* PREFIX_0F38C8 */
4497   {
4498     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4499   },
4500
4501   /* PREFIX_0F38C9 */
4502   {
4503     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4504   },
4505
4506   /* PREFIX_0F38CA */
4507   {
4508     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4509   },
4510
4511   /* PREFIX_0F38CB */
4512   {
4513     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4514   },
4515
4516   /* PREFIX_0F38CC */
4517   {
4518     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4519   },
4520
4521   /* PREFIX_0F38CD */
4522   {
4523     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4524   },
4525
4526   /* PREFIX_0F38DB */
4527   {
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4531   },
4532
4533   /* PREFIX_0F38DC */
4534   {
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4538   },
4539
4540   /* PREFIX_0F38DD */
4541   {
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4545   },
4546
4547   /* PREFIX_0F38DE */
4548   {
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4552   },
4553
4554   /* PREFIX_0F38DF */
4555   {
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4559   },
4560
4561   /* PREFIX_0F38F0 */
4562   {
4563     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4564     { Bad_Opcode },
4565     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4566     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4567   },
4568
4569   /* PREFIX_0F38F1 */
4570   {
4571     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4572     { Bad_Opcode },
4573     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4574     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4575   },
4576
4577   /* PREFIX_0F38F5 */
4578   {
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4582   },
4583
4584   /* PREFIX_0F38F6 */
4585   {
4586     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4587     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4588     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4589     { Bad_Opcode },
4590   },
4591
4592   /* PREFIX_0F3A08 */
4593   {
4594     { Bad_Opcode },
4595     { Bad_Opcode },
4596     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4597   },
4598
4599   /* PREFIX_0F3A09 */
4600   {
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4604   },
4605
4606   /* PREFIX_0F3A0A */
4607   {
4608     { Bad_Opcode },
4609     { Bad_Opcode },
4610     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4611   },
4612
4613   /* PREFIX_0F3A0B */
4614   {
4615     { Bad_Opcode },
4616     { Bad_Opcode },
4617     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4618   },
4619
4620   /* PREFIX_0F3A0C */
4621   {
4622     { Bad_Opcode },
4623     { Bad_Opcode },
4624     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4625   },
4626
4627   /* PREFIX_0F3A0D */
4628   {
4629     { Bad_Opcode },
4630     { Bad_Opcode },
4631     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4632   },
4633
4634   /* PREFIX_0F3A0E */
4635   {
4636     { Bad_Opcode },
4637     { Bad_Opcode },
4638     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4639   },
4640
4641   /* PREFIX_0F3A14 */
4642   {
4643     { Bad_Opcode },
4644     { Bad_Opcode },
4645     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4646   },
4647
4648   /* PREFIX_0F3A15 */
4649   {
4650     { Bad_Opcode },
4651     { Bad_Opcode },
4652     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4653   },
4654
4655   /* PREFIX_0F3A16 */
4656   {
4657     { Bad_Opcode },
4658     { Bad_Opcode },
4659     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4660   },
4661
4662   /* PREFIX_0F3A17 */
4663   {
4664     { Bad_Opcode },
4665     { Bad_Opcode },
4666     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4667   },
4668
4669   /* PREFIX_0F3A20 */
4670   {
4671     { Bad_Opcode },
4672     { Bad_Opcode },
4673     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4674   },
4675
4676   /* PREFIX_0F3A21 */
4677   {
4678     { Bad_Opcode },
4679     { Bad_Opcode },
4680     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4681   },
4682
4683   /* PREFIX_0F3A22 */
4684   {
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4688   },
4689
4690   /* PREFIX_0F3A40 */
4691   {
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4695   },
4696
4697   /* PREFIX_0F3A41 */
4698   {
4699     { Bad_Opcode },
4700     { Bad_Opcode },
4701     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4702   },
4703
4704   /* PREFIX_0F3A42 */
4705   {
4706     { Bad_Opcode },
4707     { Bad_Opcode },
4708     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4709   },
4710
4711   /* PREFIX_0F3A44 */
4712   {
4713     { Bad_Opcode },
4714     { Bad_Opcode },
4715     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4716   },
4717
4718   /* PREFIX_0F3A60 */
4719   {
4720     { Bad_Opcode },
4721     { Bad_Opcode },
4722     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4723   },
4724
4725   /* PREFIX_0F3A61 */
4726   {
4727     { Bad_Opcode },
4728     { Bad_Opcode },
4729     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4730   },
4731
4732   /* PREFIX_0F3A62 */
4733   {
4734     { Bad_Opcode },
4735     { Bad_Opcode },
4736     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4737   },
4738
4739   /* PREFIX_0F3A63 */
4740   {
4741     { Bad_Opcode },
4742     { Bad_Opcode },
4743     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4744   },
4745
4746   /* PREFIX_0F3ACC */
4747   {
4748     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4749   },
4750
4751   /* PREFIX_0F3ADF */
4752   {
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4756   },
4757
4758   /* PREFIX_VEX_0F10 */
4759   {
4760     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4761     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4762     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4763     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4764   },
4765
4766   /* PREFIX_VEX_0F11 */
4767   {
4768     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4769     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4770     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4771     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4772   },
4773
4774   /* PREFIX_VEX_0F12 */
4775   {
4776     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4777     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4778     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4779     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4780   },
4781
4782   /* PREFIX_VEX_0F16 */
4783   {
4784     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4785     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4786     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4787   },
4788
4789   /* PREFIX_VEX_0F2A */
4790   {
4791     { Bad_Opcode },
4792     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4793     { Bad_Opcode },
4794     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4795   },
4796
4797   /* PREFIX_VEX_0F2C */
4798   {
4799     { Bad_Opcode },
4800     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4801     { Bad_Opcode },
4802     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4803   },
4804
4805   /* PREFIX_VEX_0F2D */
4806   {
4807     { Bad_Opcode },
4808     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4809     { Bad_Opcode },
4810     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4811   },
4812
4813   /* PREFIX_VEX_0F2E */
4814   {
4815     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4816     { Bad_Opcode },
4817     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4818   },
4819
4820   /* PREFIX_VEX_0F2F */
4821   {
4822     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4823     { Bad_Opcode },
4824     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4825   },
4826
4827   /* PREFIX_VEX_0F41 */
4828   {
4829     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4830     { Bad_Opcode },
4831     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4832   },
4833
4834   /* PREFIX_VEX_0F42 */
4835   {
4836     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4837     { Bad_Opcode },
4838     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4839   },
4840
4841   /* PREFIX_VEX_0F44 */
4842   {
4843     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4844     { Bad_Opcode },
4845     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4846   },
4847
4848   /* PREFIX_VEX_0F45 */
4849   {
4850     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4851     { Bad_Opcode },
4852     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4853   },
4854
4855   /* PREFIX_VEX_0F46 */
4856   {
4857     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4858     { Bad_Opcode },
4859     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4860   },
4861
4862   /* PREFIX_VEX_0F47 */
4863   {
4864     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4865     { Bad_Opcode },
4866     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4867   },
4868
4869   /* PREFIX_VEX_0F4A */
4870   {
4871     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4872     { Bad_Opcode },
4873     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4874   },
4875
4876   /* PREFIX_VEX_0F4B */
4877   {
4878     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4879     { Bad_Opcode },
4880     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4881   },
4882
4883   /* PREFIX_VEX_0F51 */
4884   {
4885     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4886     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4887     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4888     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4889   },
4890
4891   /* PREFIX_VEX_0F52 */
4892   {
4893     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4894     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4895   },
4896
4897   /* PREFIX_VEX_0F53 */
4898   {
4899     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4900     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4901   },
4902
4903   /* PREFIX_VEX_0F58 */
4904   {
4905     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4906     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4907     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4908     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4909   },
4910
4911   /* PREFIX_VEX_0F59 */
4912   {
4913     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4914     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4915     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4916     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4917   },
4918
4919   /* PREFIX_VEX_0F5A */
4920   {
4921     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4922     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4923     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4924     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4925   },
4926
4927   /* PREFIX_VEX_0F5B */
4928   {
4929     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4930     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4931     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4932   },
4933
4934   /* PREFIX_VEX_0F5C */
4935   {
4936     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4937     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4938     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4939     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4940   },
4941
4942   /* PREFIX_VEX_0F5D */
4943   {
4944     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4945     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4946     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4947     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4948   },
4949
4950   /* PREFIX_VEX_0F5E */
4951   {
4952     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4953     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4954     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4955     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4956   },
4957
4958   /* PREFIX_VEX_0F5F */
4959   {
4960     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4961     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4962     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4963     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4964   },
4965
4966   /* PREFIX_VEX_0F60 */
4967   {
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4971   },
4972
4973   /* PREFIX_VEX_0F61 */
4974   {
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4978   },
4979
4980   /* PREFIX_VEX_0F62 */
4981   {
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4985   },
4986
4987   /* PREFIX_VEX_0F63 */
4988   {
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4992   },
4993
4994   /* PREFIX_VEX_0F64 */
4995   {
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4999   },
5000
5001   /* PREFIX_VEX_0F65 */
5002   {
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { VEX_W_TABLE (VEX_W_0F65_P_2) },
5006   },
5007
5008   /* PREFIX_VEX_0F66 */
5009   {
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { VEX_W_TABLE (VEX_W_0F66_P_2) },
5013   },
5014
5015   /* PREFIX_VEX_0F67 */
5016   {
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { VEX_W_TABLE (VEX_W_0F67_P_2) },
5020   },
5021
5022   /* PREFIX_VEX_0F68 */
5023   {
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { VEX_W_TABLE (VEX_W_0F68_P_2) },
5027   },
5028
5029   /* PREFIX_VEX_0F69 */
5030   {
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { VEX_W_TABLE (VEX_W_0F69_P_2) },
5034   },
5035
5036   /* PREFIX_VEX_0F6A */
5037   {
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5041   },
5042
5043   /* PREFIX_VEX_0F6B */
5044   {
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5048   },
5049
5050   /* PREFIX_VEX_0F6C */
5051   {
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5055   },
5056
5057   /* PREFIX_VEX_0F6D */
5058   {
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5062   },
5063
5064   /* PREFIX_VEX_0F6E */
5065   {
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5069   },
5070
5071   /* PREFIX_VEX_0F6F */
5072   {
5073     { Bad_Opcode },
5074     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5075     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5076   },
5077
5078   /* PREFIX_VEX_0F70 */
5079   {
5080     { Bad_Opcode },
5081     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5082     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5083     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5084   },
5085
5086   /* PREFIX_VEX_0F71_REG_2 */
5087   {
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5091   },
5092
5093   /* PREFIX_VEX_0F71_REG_4 */
5094   {
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5098   },
5099
5100   /* PREFIX_VEX_0F71_REG_6 */
5101   {
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5105   },
5106
5107   /* PREFIX_VEX_0F72_REG_2 */
5108   {
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5112   },
5113
5114   /* PREFIX_VEX_0F72_REG_4 */
5115   {
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5119   },
5120
5121   /* PREFIX_VEX_0F72_REG_6 */
5122   {
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5126   },
5127
5128   /* PREFIX_VEX_0F73_REG_2 */
5129   {
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5133   },
5134
5135   /* PREFIX_VEX_0F73_REG_3 */
5136   {
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5140   },
5141
5142   /* PREFIX_VEX_0F73_REG_6 */
5143   {
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5147   },
5148
5149   /* PREFIX_VEX_0F73_REG_7 */
5150   {
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5154   },
5155
5156   /* PREFIX_VEX_0F74 */
5157   {
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5161   },
5162
5163   /* PREFIX_VEX_0F75 */
5164   {
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5168   },
5169
5170   /* PREFIX_VEX_0F76 */
5171   {
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5175   },
5176
5177   /* PREFIX_VEX_0F77 */
5178   {
5179     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5180   },
5181
5182   /* PREFIX_VEX_0F7C */
5183   {
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5187     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5188   },
5189
5190   /* PREFIX_VEX_0F7D */
5191   {
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5195     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5196   },
5197
5198   /* PREFIX_VEX_0F7E */
5199   {
5200     { Bad_Opcode },
5201     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5202     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5203   },
5204
5205   /* PREFIX_VEX_0F7F */
5206   {
5207     { Bad_Opcode },
5208     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5209     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5210   },
5211
5212   /* PREFIX_VEX_0F90 */
5213   {
5214     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5215     { Bad_Opcode },
5216     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5217   },
5218
5219   /* PREFIX_VEX_0F91 */
5220   {
5221     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5222     { Bad_Opcode },
5223     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5224   },
5225
5226   /* PREFIX_VEX_0F92 */
5227   {
5228     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5229     { Bad_Opcode },
5230     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5231     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5232   },
5233
5234   /* PREFIX_VEX_0F93 */
5235   {
5236     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5237     { Bad_Opcode },
5238     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5239     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5240   },
5241
5242   /* PREFIX_VEX_0F98 */
5243   {
5244     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5245     { Bad_Opcode },
5246     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5247   },
5248
5249   /* PREFIX_VEX_0F99 */
5250   {
5251     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5252     { Bad_Opcode },
5253     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5254   },
5255
5256   /* PREFIX_VEX_0FC2 */
5257   {
5258     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5259     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5260     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5261     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5262   },
5263
5264   /* PREFIX_VEX_0FC4 */
5265   {
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5269   },
5270
5271   /* PREFIX_VEX_0FC5 */
5272   {
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5276   },
5277
5278   /* PREFIX_VEX_0FD0 */
5279   {
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5283     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5284   },
5285
5286   /* PREFIX_VEX_0FD1 */
5287   {
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5291   },
5292
5293   /* PREFIX_VEX_0FD2 */
5294   {
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5298   },
5299
5300   /* PREFIX_VEX_0FD3 */
5301   {
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5305   },
5306
5307   /* PREFIX_VEX_0FD4 */
5308   {
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5312   },
5313
5314   /* PREFIX_VEX_0FD5 */
5315   {
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5319   },
5320
5321   /* PREFIX_VEX_0FD6 */
5322   {
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5326   },
5327
5328   /* PREFIX_VEX_0FD7 */
5329   {
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5333   },
5334
5335   /* PREFIX_VEX_0FD8 */
5336   {
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5340   },
5341
5342   /* PREFIX_VEX_0FD9 */
5343   {
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5347   },
5348
5349   /* PREFIX_VEX_0FDA */
5350   {
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5354   },
5355
5356   /* PREFIX_VEX_0FDB */
5357   {
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5361   },
5362
5363   /* PREFIX_VEX_0FDC */
5364   {
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5368   },
5369
5370   /* PREFIX_VEX_0FDD */
5371   {
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5375   },
5376
5377   /* PREFIX_VEX_0FDE */
5378   {
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5382   },
5383
5384   /* PREFIX_VEX_0FDF */
5385   {
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5389   },
5390
5391   /* PREFIX_VEX_0FE0 */
5392   {
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5396   },
5397
5398   /* PREFIX_VEX_0FE1 */
5399   {
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5403   },
5404
5405   /* PREFIX_VEX_0FE2 */
5406   {
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5410   },
5411
5412   /* PREFIX_VEX_0FE3 */
5413   {
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5417   },
5418
5419   /* PREFIX_VEX_0FE4 */
5420   {
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5424   },
5425
5426   /* PREFIX_VEX_0FE5 */
5427   {
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5431   },
5432
5433   /* PREFIX_VEX_0FE6 */
5434   {
5435     { Bad_Opcode },
5436     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5437     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5438     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5439   },
5440
5441   /* PREFIX_VEX_0FE7 */
5442   {
5443     { Bad_Opcode },
5444     { Bad_Opcode },
5445     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5446   },
5447
5448   /* PREFIX_VEX_0FE8 */
5449   {
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5453   },
5454
5455   /* PREFIX_VEX_0FE9 */
5456   {
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5460   },
5461
5462   /* PREFIX_VEX_0FEA */
5463   {
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5467   },
5468
5469   /* PREFIX_VEX_0FEB */
5470   {
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5474   },
5475
5476   /* PREFIX_VEX_0FEC */
5477   {
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5481   },
5482
5483   /* PREFIX_VEX_0FED */
5484   {
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5488   },
5489
5490   /* PREFIX_VEX_0FEE */
5491   {
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5495   },
5496
5497   /* PREFIX_VEX_0FEF */
5498   {
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5502   },
5503
5504   /* PREFIX_VEX_0FF0 */
5505   {
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5510   },
5511
5512   /* PREFIX_VEX_0FF1 */
5513   {
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5517   },
5518
5519   /* PREFIX_VEX_0FF2 */
5520   {
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5524   },
5525
5526   /* PREFIX_VEX_0FF3 */
5527   {
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5531   },
5532
5533   /* PREFIX_VEX_0FF4 */
5534   {
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5538   },
5539
5540   /* PREFIX_VEX_0FF5 */
5541   {
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5545   },
5546
5547   /* PREFIX_VEX_0FF6 */
5548   {
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5552   },
5553
5554   /* PREFIX_VEX_0FF7 */
5555   {
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5559   },
5560
5561   /* PREFIX_VEX_0FF8 */
5562   {
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5566   },
5567
5568   /* PREFIX_VEX_0FF9 */
5569   {
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5573   },
5574
5575   /* PREFIX_VEX_0FFA */
5576   {
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5580   },
5581
5582   /* PREFIX_VEX_0FFB */
5583   {
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5587   },
5588
5589   /* PREFIX_VEX_0FFC */
5590   {
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5594   },
5595
5596   /* PREFIX_VEX_0FFD */
5597   {
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5601   },
5602
5603   /* PREFIX_VEX_0FFE */
5604   {
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5608   },
5609
5610   /* PREFIX_VEX_0F3800 */
5611   {
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5615   },
5616
5617   /* PREFIX_VEX_0F3801 */
5618   {
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5622   },
5623
5624   /* PREFIX_VEX_0F3802 */
5625   {
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5629   },
5630
5631   /* PREFIX_VEX_0F3803 */
5632   {
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5636   },
5637
5638   /* PREFIX_VEX_0F3804 */
5639   {
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5643   },
5644
5645   /* PREFIX_VEX_0F3805 */
5646   {
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5650   },
5651
5652   /* PREFIX_VEX_0F3806 */
5653   {
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5657   },
5658
5659   /* PREFIX_VEX_0F3807 */
5660   {
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5664   },
5665
5666   /* PREFIX_VEX_0F3808 */
5667   {
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5671   },
5672
5673   /* PREFIX_VEX_0F3809 */
5674   {
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5678   },
5679
5680   /* PREFIX_VEX_0F380A */
5681   {
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5685   },
5686
5687   /* PREFIX_VEX_0F380B */
5688   {
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5692   },
5693
5694   /* PREFIX_VEX_0F380C */
5695   {
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5699   },
5700
5701   /* PREFIX_VEX_0F380D */
5702   {
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5706   },
5707
5708   /* PREFIX_VEX_0F380E */
5709   {
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5713   },
5714
5715   /* PREFIX_VEX_0F380F */
5716   {
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5720   },
5721
5722   /* PREFIX_VEX_0F3813 */
5723   {
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5727   },
5728
5729   /* PREFIX_VEX_0F3816 */
5730   {
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5734   },
5735
5736   /* PREFIX_VEX_0F3817 */
5737   {
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5741   },
5742
5743   /* PREFIX_VEX_0F3818 */
5744   {
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5748   },
5749
5750   /* PREFIX_VEX_0F3819 */
5751   {
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5755   },
5756
5757   /* PREFIX_VEX_0F381A */
5758   {
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5762   },
5763
5764   /* PREFIX_VEX_0F381C */
5765   {
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5769   },
5770
5771   /* PREFIX_VEX_0F381D */
5772   {
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5776   },
5777
5778   /* PREFIX_VEX_0F381E */
5779   {
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5783   },
5784
5785   /* PREFIX_VEX_0F3820 */
5786   {
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5790   },
5791
5792   /* PREFIX_VEX_0F3821 */
5793   {
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5797   },
5798
5799   /* PREFIX_VEX_0F3822 */
5800   {
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5804   },
5805
5806   /* PREFIX_VEX_0F3823 */
5807   {
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5811   },
5812
5813   /* PREFIX_VEX_0F3824 */
5814   {
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5818   },
5819
5820   /* PREFIX_VEX_0F3825 */
5821   {
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5825   },
5826
5827   /* PREFIX_VEX_0F3828 */
5828   {
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5832   },
5833
5834   /* PREFIX_VEX_0F3829 */
5835   {
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5839   },
5840
5841   /* PREFIX_VEX_0F382A */
5842   {
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5846   },
5847
5848   /* PREFIX_VEX_0F382B */
5849   {
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5853   },
5854
5855   /* PREFIX_VEX_0F382C */
5856   {
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5860   },
5861
5862   /* PREFIX_VEX_0F382D */
5863   {
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5867   },
5868
5869   /* PREFIX_VEX_0F382E */
5870   {
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5874   },
5875
5876   /* PREFIX_VEX_0F382F */
5877   {
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5881   },
5882
5883   /* PREFIX_VEX_0F3830 */
5884   {
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5888   },
5889
5890   /* PREFIX_VEX_0F3831 */
5891   {
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5895   },
5896
5897   /* PREFIX_VEX_0F3832 */
5898   {
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5902   },
5903
5904   /* PREFIX_VEX_0F3833 */
5905   {
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5909   },
5910
5911   /* PREFIX_VEX_0F3834 */
5912   {
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5916   },
5917
5918   /* PREFIX_VEX_0F3835 */
5919   {
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5923   },
5924
5925   /* PREFIX_VEX_0F3836 */
5926   {
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5930   },
5931
5932   /* PREFIX_VEX_0F3837 */
5933   {
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5937   },
5938
5939   /* PREFIX_VEX_0F3838 */
5940   {
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5944   },
5945
5946   /* PREFIX_VEX_0F3839 */
5947   {
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5951   },
5952
5953   /* PREFIX_VEX_0F383A */
5954   {
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5958   },
5959
5960   /* PREFIX_VEX_0F383B */
5961   {
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5965   },
5966
5967   /* PREFIX_VEX_0F383C */
5968   {
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5972   },
5973
5974   /* PREFIX_VEX_0F383D */
5975   {
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5979   },
5980
5981   /* PREFIX_VEX_0F383E */
5982   {
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5986   },
5987
5988   /* PREFIX_VEX_0F383F */
5989   {
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5993   },
5994
5995   /* PREFIX_VEX_0F3840 */
5996   {
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6000   },
6001
6002   /* PREFIX_VEX_0F3841 */
6003   {
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6007   },
6008
6009   /* PREFIX_VEX_0F3845 */
6010   {
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6014   },
6015
6016   /* PREFIX_VEX_0F3846 */
6017   {
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6021   },
6022
6023   /* PREFIX_VEX_0F3847 */
6024   {
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6028   },
6029
6030   /* PREFIX_VEX_0F3858 */
6031   {
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6035   },
6036
6037   /* PREFIX_VEX_0F3859 */
6038   {
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6042   },
6043
6044   /* PREFIX_VEX_0F385A */
6045   {
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6049   },
6050
6051   /* PREFIX_VEX_0F3878 */
6052   {
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6056   },
6057
6058   /* PREFIX_VEX_0F3879 */
6059   {
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6063   },
6064
6065   /* PREFIX_VEX_0F388C */
6066   {
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6070   },
6071
6072   /* PREFIX_VEX_0F388E */
6073   {
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6077   },
6078
6079   /* PREFIX_VEX_0F3890 */
6080   {
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6084   },
6085
6086   /* PREFIX_VEX_0F3891 */
6087   {
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6091   },
6092
6093   /* PREFIX_VEX_0F3892 */
6094   {
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6098   },
6099
6100   /* PREFIX_VEX_0F3893 */
6101   {
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6105   },
6106
6107   /* PREFIX_VEX_0F3896 */
6108   {
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6112   },
6113
6114   /* PREFIX_VEX_0F3897 */
6115   {
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6119   },
6120
6121   /* PREFIX_VEX_0F3898 */
6122   {
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6126   },
6127
6128   /* PREFIX_VEX_0F3899 */
6129   {
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6133   },
6134
6135   /* PREFIX_VEX_0F389A */
6136   {
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6140   },
6141
6142   /* PREFIX_VEX_0F389B */
6143   {
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6147   },
6148
6149   /* PREFIX_VEX_0F389C */
6150   {
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6154   },
6155
6156   /* PREFIX_VEX_0F389D */
6157   {
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6161   },
6162
6163   /* PREFIX_VEX_0F389E */
6164   {
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6168   },
6169
6170   /* PREFIX_VEX_0F389F */
6171   {
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6175   },
6176
6177   /* PREFIX_VEX_0F38A6 */
6178   {
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6182     { Bad_Opcode },
6183   },
6184
6185   /* PREFIX_VEX_0F38A7 */
6186   {
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6190   },
6191
6192   /* PREFIX_VEX_0F38A8 */
6193   {
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6197   },
6198
6199   /* PREFIX_VEX_0F38A9 */
6200   {
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6204   },
6205
6206   /* PREFIX_VEX_0F38AA */
6207   {
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6211   },
6212
6213   /* PREFIX_VEX_0F38AB */
6214   {
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6218   },
6219
6220   /* PREFIX_VEX_0F38AC */
6221   {
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6225   },
6226
6227   /* PREFIX_VEX_0F38AD */
6228   {
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6232   },
6233
6234   /* PREFIX_VEX_0F38AE */
6235   {
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6239   },
6240
6241   /* PREFIX_VEX_0F38AF */
6242   {
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6246   },
6247
6248   /* PREFIX_VEX_0F38B6 */
6249   {
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6253   },
6254
6255   /* PREFIX_VEX_0F38B7 */
6256   {
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6260   },
6261
6262   /* PREFIX_VEX_0F38B8 */
6263   {
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6267   },
6268
6269   /* PREFIX_VEX_0F38B9 */
6270   {
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6274   },
6275
6276   /* PREFIX_VEX_0F38BA */
6277   {
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6281   },
6282
6283   /* PREFIX_VEX_0F38BB */
6284   {
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6288   },
6289
6290   /* PREFIX_VEX_0F38BC */
6291   {
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6295   },
6296
6297   /* PREFIX_VEX_0F38BD */
6298   {
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6302   },
6303
6304   /* PREFIX_VEX_0F38BE */
6305   {
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6309   },
6310
6311   /* PREFIX_VEX_0F38BF */
6312   {
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6316   },
6317
6318   /* PREFIX_VEX_0F38DB */
6319   {
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6323   },
6324
6325   /* PREFIX_VEX_0F38DC */
6326   {
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6330   },
6331
6332   /* PREFIX_VEX_0F38DD */
6333   {
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6337   },
6338
6339   /* PREFIX_VEX_0F38DE */
6340   {
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6344   },
6345
6346   /* PREFIX_VEX_0F38DF */
6347   {
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6351   },
6352
6353   /* PREFIX_VEX_0F38F2 */
6354   {
6355     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6356   },
6357
6358   /* PREFIX_VEX_0F38F3_REG_1 */
6359   {
6360     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6361   },
6362
6363   /* PREFIX_VEX_0F38F3_REG_2 */
6364   {
6365     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6366   },
6367
6368   /* PREFIX_VEX_0F38F3_REG_3 */
6369   {
6370     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6371   },
6372
6373   /* PREFIX_VEX_0F38F5 */
6374   {
6375     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6376     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6377     { Bad_Opcode },
6378     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6379   },
6380
6381   /* PREFIX_VEX_0F38F6 */
6382   {
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6387   },
6388
6389   /* PREFIX_VEX_0F38F7 */
6390   {
6391     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6392     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6393     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6394     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6395   },
6396
6397   /* PREFIX_VEX_0F3A00 */
6398   {
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6402   },
6403
6404   /* PREFIX_VEX_0F3A01 */
6405   {
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6409   },
6410
6411   /* PREFIX_VEX_0F3A02 */
6412   {
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6416   },
6417
6418   /* PREFIX_VEX_0F3A04 */
6419   {
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6423   },
6424
6425   /* PREFIX_VEX_0F3A05 */
6426   {
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6430   },
6431
6432   /* PREFIX_VEX_0F3A06 */
6433   {
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6437   },
6438
6439   /* PREFIX_VEX_0F3A08 */
6440   {
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6444   },
6445
6446   /* PREFIX_VEX_0F3A09 */
6447   {
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6451   },
6452
6453   /* PREFIX_VEX_0F3A0A */
6454   {
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6458   },
6459
6460   /* PREFIX_VEX_0F3A0B */
6461   {
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6465   },
6466
6467   /* PREFIX_VEX_0F3A0C */
6468   {
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6472   },
6473
6474   /* PREFIX_VEX_0F3A0D */
6475   {
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6479   },
6480
6481   /* PREFIX_VEX_0F3A0E */
6482   {
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6486   },
6487
6488   /* PREFIX_VEX_0F3A0F */
6489   {
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6493   },
6494
6495   /* PREFIX_VEX_0F3A14 */
6496   {
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6500   },
6501
6502   /* PREFIX_VEX_0F3A15 */
6503   {
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6507   },
6508
6509   /* PREFIX_VEX_0F3A16 */
6510   {
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6514   },
6515
6516   /* PREFIX_VEX_0F3A17 */
6517   {
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6521   },
6522
6523   /* PREFIX_VEX_0F3A18 */
6524   {
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6528   },
6529
6530   /* PREFIX_VEX_0F3A19 */
6531   {
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6535   },
6536
6537   /* PREFIX_VEX_0F3A1D */
6538   {
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6542   },
6543
6544   /* PREFIX_VEX_0F3A20 */
6545   {
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6549   },
6550
6551   /* PREFIX_VEX_0F3A21 */
6552   {
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6556   },
6557
6558   /* PREFIX_VEX_0F3A22 */
6559   {
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6563   },
6564
6565   /* PREFIX_VEX_0F3A30 */
6566   {
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6570   },
6571
6572   /* PREFIX_VEX_0F3A31 */
6573   {
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6577   },
6578
6579   /* PREFIX_VEX_0F3A32 */
6580   {
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6584   },
6585
6586   /* PREFIX_VEX_0F3A33 */
6587   {
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6591   },
6592
6593   /* PREFIX_VEX_0F3A38 */
6594   {
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6598   },
6599
6600   /* PREFIX_VEX_0F3A39 */
6601   {
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6605   },
6606
6607   /* PREFIX_VEX_0F3A40 */
6608   {
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6612   },
6613
6614   /* PREFIX_VEX_0F3A41 */
6615   {
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6619   },
6620
6621   /* PREFIX_VEX_0F3A42 */
6622   {
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6626   },
6627
6628   /* PREFIX_VEX_0F3A44 */
6629   {
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6633   },
6634
6635   /* PREFIX_VEX_0F3A46 */
6636   {
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6640   },
6641
6642   /* PREFIX_VEX_0F3A48 */
6643   {
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6647   },
6648
6649   /* PREFIX_VEX_0F3A49 */
6650   {
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6654   },
6655
6656   /* PREFIX_VEX_0F3A4A */
6657   {
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6661   },
6662
6663   /* PREFIX_VEX_0F3A4B */
6664   {
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6668   },
6669
6670   /* PREFIX_VEX_0F3A4C */
6671   {
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6675   },
6676
6677   /* PREFIX_VEX_0F3A5C */
6678   {
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6682   },
6683
6684   /* PREFIX_VEX_0F3A5D */
6685   {
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6689   },
6690
6691   /* PREFIX_VEX_0F3A5E */
6692   {
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6696   },
6697
6698   /* PREFIX_VEX_0F3A5F */
6699   {
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6703   },
6704
6705   /* PREFIX_VEX_0F3A60 */
6706   {
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6710     { Bad_Opcode },
6711   },
6712
6713   /* PREFIX_VEX_0F3A61 */
6714   {
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6718   },
6719
6720   /* PREFIX_VEX_0F3A62 */
6721   {
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6725   },
6726
6727   /* PREFIX_VEX_0F3A63 */
6728   {
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6732   },
6733
6734   /* PREFIX_VEX_0F3A68 */
6735   {
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6739   },
6740
6741   /* PREFIX_VEX_0F3A69 */
6742   {
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6746   },
6747
6748   /* PREFIX_VEX_0F3A6A */
6749   {
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6753   },
6754
6755   /* PREFIX_VEX_0F3A6B */
6756   {
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6760   },
6761
6762   /* PREFIX_VEX_0F3A6C */
6763   {
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6767   },
6768
6769   /* PREFIX_VEX_0F3A6D */
6770   {
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6774   },
6775
6776   /* PREFIX_VEX_0F3A6E */
6777   {
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6781   },
6782
6783   /* PREFIX_VEX_0F3A6F */
6784   {
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6788   },
6789
6790   /* PREFIX_VEX_0F3A78 */
6791   {
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6795   },
6796
6797   /* PREFIX_VEX_0F3A79 */
6798   {
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6802   },
6803
6804   /* PREFIX_VEX_0F3A7A */
6805   {
6806     { Bad_Opcode },
6807     { Bad_Opcode },
6808     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6809   },
6810
6811   /* PREFIX_VEX_0F3A7B */
6812   {
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6816   },
6817
6818   /* PREFIX_VEX_0F3A7C */
6819   {
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6823     { Bad_Opcode },
6824   },
6825
6826   /* PREFIX_VEX_0F3A7D */
6827   {
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6831   },
6832
6833   /* PREFIX_VEX_0F3A7E */
6834   {
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6838   },
6839
6840   /* PREFIX_VEX_0F3A7F */
6841   {
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6845   },
6846
6847   /* PREFIX_VEX_0F3ADF */
6848   {
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6852   },
6853
6854   /* PREFIX_VEX_0F3AF0 */
6855   {
6856     { Bad_Opcode },
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6860   },
6861
6862 #define NEED_PREFIX_TABLE
6863 #include "i386-dis-evex.h"
6864 #undef NEED_PREFIX_TABLE
6865 };
6866
6867 static const struct dis386 x86_64_table[][2] = {
6868   /* X86_64_06 */
6869   {
6870     { "pushP", { es }, 0 },
6871   },
6872
6873   /* X86_64_07 */
6874   {
6875     { "popP", { es }, 0 },
6876   },
6877
6878   /* X86_64_0D */
6879   {
6880     { "pushP", { cs }, 0 },
6881   },
6882
6883   /* X86_64_16 */
6884   {
6885     { "pushP", { ss }, 0 },
6886   },
6887
6888   /* X86_64_17 */
6889   {
6890     { "popP", { ss }, 0 },
6891   },
6892
6893   /* X86_64_1E */
6894   {
6895     { "pushP", { ds }, 0 },
6896   },
6897
6898   /* X86_64_1F */
6899   {
6900     { "popP", { ds }, 0 },
6901   },
6902
6903   /* X86_64_27 */
6904   {
6905     { "daa", { XX }, 0 },
6906   },
6907
6908   /* X86_64_2F */
6909   {
6910     { "das", { XX }, 0 },
6911   },
6912
6913   /* X86_64_37 */
6914   {
6915     { "aaa", { XX }, 0 },
6916   },
6917
6918   /* X86_64_3F */
6919   {
6920     { "aas", { XX }, 0 },
6921   },
6922
6923   /* X86_64_60 */
6924   {
6925     { "pushaP", { XX }, 0 },
6926   },
6927
6928   /* X86_64_61 */
6929   {
6930     { "popaP", { XX }, 0 },
6931   },
6932
6933   /* X86_64_62 */
6934   {
6935     { MOD_TABLE (MOD_62_32BIT) },
6936     { EVEX_TABLE (EVEX_0F) },
6937   },
6938
6939   /* X86_64_63 */
6940   {
6941     { "arpl", { Ew, Gw }, 0 },
6942     { "movs{lq|xd}", { Gv, Ed }, 0 },
6943   },
6944
6945   /* X86_64_6D */
6946   {
6947     { "ins{R|}", { Yzr, indirDX }, 0 },
6948     { "ins{G|}", { Yzr, indirDX }, 0 },
6949   },
6950
6951   /* X86_64_6F */
6952   {
6953     { "outs{R|}", { indirDXr, Xz }, 0 },
6954     { "outs{G|}", { indirDXr, Xz }, 0 },
6955   },
6956
6957   /* X86_64_82 */
6958   {
6959     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6960     { REG_TABLE (REG_80) },
6961   },
6962
6963   /* X86_64_9A */
6964   {
6965     { "Jcall{T|}", { Ap }, 0 },
6966   },
6967
6968   /* X86_64_C4 */
6969   {
6970     { MOD_TABLE (MOD_C4_32BIT) },
6971     { VEX_C4_TABLE (VEX_0F) },
6972   },
6973
6974   /* X86_64_C5 */
6975   {
6976     { MOD_TABLE (MOD_C5_32BIT) },
6977     { VEX_C5_TABLE (VEX_0F) },
6978   },
6979
6980   /* X86_64_CE */
6981   {
6982     { "into", { XX }, 0 },
6983   },
6984
6985   /* X86_64_D4 */
6986   {
6987     { "aam", { Ib }, 0 },
6988   },
6989
6990   /* X86_64_D5 */
6991   {
6992     { "aad", { Ib }, 0 },
6993   },
6994
6995   /* X86_64_E8 */
6996   {
6997     { "callP",          { Jv, BND }, 0 },
6998     { "call@",          { Jv, BND }, 0 }
6999   },
7000
7001   /* X86_64_E9 */
7002   {
7003     { "jmpP",           { Jv, BND }, 0 },
7004     { "jmp@",           { Jv, BND }, 0 }
7005   },
7006
7007   /* X86_64_EA */
7008   {
7009     { "Jjmp{T|}", { Ap }, 0 },
7010   },
7011
7012   /* X86_64_0F01_REG_0 */
7013   {
7014     { "sgdt{Q|IQ}", { M }, 0 },
7015     { "sgdt", { M }, 0 },
7016   },
7017
7018   /* X86_64_0F01_REG_1 */
7019   {
7020     { "sidt{Q|IQ}", { M }, 0 },
7021     { "sidt", { M }, 0 },
7022   },
7023
7024   /* X86_64_0F01_REG_2 */
7025   {
7026     { "lgdt{Q|Q}", { M }, 0 },
7027     { "lgdt", { M }, 0 },
7028   },
7029
7030   /* X86_64_0F01_REG_3 */
7031   {
7032     { "lidt{Q|Q}", { M }, 0 },
7033     { "lidt", { M }, 0 },
7034   },
7035 };
7036
7037 static const struct dis386 three_byte_table[][256] = {
7038
7039   /* THREE_BYTE_0F38 */
7040   {
7041     /* 00 */
7042     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7043     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7044     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7045     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7046     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7047     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7048     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7049     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7050     /* 08 */
7051     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7052     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7053     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7054     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     /* 10 */
7060     { PREFIX_TABLE (PREFIX_0F3810) },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { PREFIX_TABLE (PREFIX_0F3814) },
7065     { PREFIX_TABLE (PREFIX_0F3815) },
7066     { Bad_Opcode },
7067     { PREFIX_TABLE (PREFIX_0F3817) },
7068     /* 18 */
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7074     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7075     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7076     { Bad_Opcode },
7077     /* 20 */
7078     { PREFIX_TABLE (PREFIX_0F3820) },
7079     { PREFIX_TABLE (PREFIX_0F3821) },
7080     { PREFIX_TABLE (PREFIX_0F3822) },
7081     { PREFIX_TABLE (PREFIX_0F3823) },
7082     { PREFIX_TABLE (PREFIX_0F3824) },
7083     { PREFIX_TABLE (PREFIX_0F3825) },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     /* 28 */
7087     { PREFIX_TABLE (PREFIX_0F3828) },
7088     { PREFIX_TABLE (PREFIX_0F3829) },
7089     { PREFIX_TABLE (PREFIX_0F382A) },
7090     { PREFIX_TABLE (PREFIX_0F382B) },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     /* 30 */
7096     { PREFIX_TABLE (PREFIX_0F3830) },
7097     { PREFIX_TABLE (PREFIX_0F3831) },
7098     { PREFIX_TABLE (PREFIX_0F3832) },
7099     { PREFIX_TABLE (PREFIX_0F3833) },
7100     { PREFIX_TABLE (PREFIX_0F3834) },
7101     { PREFIX_TABLE (PREFIX_0F3835) },
7102     { Bad_Opcode },
7103     { PREFIX_TABLE (PREFIX_0F3837) },
7104     /* 38 */
7105     { PREFIX_TABLE (PREFIX_0F3838) },
7106     { PREFIX_TABLE (PREFIX_0F3839) },
7107     { PREFIX_TABLE (PREFIX_0F383A) },
7108     { PREFIX_TABLE (PREFIX_0F383B) },
7109     { PREFIX_TABLE (PREFIX_0F383C) },
7110     { PREFIX_TABLE (PREFIX_0F383D) },
7111     { PREFIX_TABLE (PREFIX_0F383E) },
7112     { PREFIX_TABLE (PREFIX_0F383F) },
7113     /* 40 */
7114     { PREFIX_TABLE (PREFIX_0F3840) },
7115     { PREFIX_TABLE (PREFIX_0F3841) },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     /* 48 */
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     /* 50 */
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     /* 58 */
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     /* 60 */
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     /* 68 */
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     /* 70 */
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     /* 78 */
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     /* 80 */
7186     { PREFIX_TABLE (PREFIX_0F3880) },
7187     { PREFIX_TABLE (PREFIX_0F3881) },
7188     { PREFIX_TABLE (PREFIX_0F3882) },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     /* 88 */
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     /* 90 */
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     /* 98 */
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     /* a0 */
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     /* a8 */
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     /* b0 */
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     /* b8 */
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     /* c0 */
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     /* c8 */
7267     { PREFIX_TABLE (PREFIX_0F38C8) },
7268     { PREFIX_TABLE (PREFIX_0F38C9) },
7269     { PREFIX_TABLE (PREFIX_0F38CA) },
7270     { PREFIX_TABLE (PREFIX_0F38CB) },
7271     { PREFIX_TABLE (PREFIX_0F38CC) },
7272     { PREFIX_TABLE (PREFIX_0F38CD) },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     /* d0 */
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     /* d8 */
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { PREFIX_TABLE (PREFIX_0F38DB) },
7289     { PREFIX_TABLE (PREFIX_0F38DC) },
7290     { PREFIX_TABLE (PREFIX_0F38DD) },
7291     { PREFIX_TABLE (PREFIX_0F38DE) },
7292     { PREFIX_TABLE (PREFIX_0F38DF) },
7293     /* e0 */
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     /* e8 */
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     /* f0 */
7312     { PREFIX_TABLE (PREFIX_0F38F0) },
7313     { PREFIX_TABLE (PREFIX_0F38F1) },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { PREFIX_TABLE (PREFIX_0F38F5) },
7318     { PREFIX_TABLE (PREFIX_0F38F6) },
7319     { Bad_Opcode },
7320     /* f8 */
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329   },
7330   /* THREE_BYTE_0F3A */
7331   {
7332     /* 00 */
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     /* 08 */
7342     { PREFIX_TABLE (PREFIX_0F3A08) },
7343     { PREFIX_TABLE (PREFIX_0F3A09) },
7344     { PREFIX_TABLE (PREFIX_0F3A0A) },
7345     { PREFIX_TABLE (PREFIX_0F3A0B) },
7346     { PREFIX_TABLE (PREFIX_0F3A0C) },
7347     { PREFIX_TABLE (PREFIX_0F3A0D) },
7348     { PREFIX_TABLE (PREFIX_0F3A0E) },
7349     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7350     /* 10 */
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { PREFIX_TABLE (PREFIX_0F3A14) },
7356     { PREFIX_TABLE (PREFIX_0F3A15) },
7357     { PREFIX_TABLE (PREFIX_0F3A16) },
7358     { PREFIX_TABLE (PREFIX_0F3A17) },
7359     /* 18 */
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     /* 20 */
7369     { PREFIX_TABLE (PREFIX_0F3A20) },
7370     { PREFIX_TABLE (PREFIX_0F3A21) },
7371     { PREFIX_TABLE (PREFIX_0F3A22) },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     /* 28 */
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     /* 30 */
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     /* 38 */
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     /* 40 */
7405     { PREFIX_TABLE (PREFIX_0F3A40) },
7406     { PREFIX_TABLE (PREFIX_0F3A41) },
7407     { PREFIX_TABLE (PREFIX_0F3A42) },
7408     { Bad_Opcode },
7409     { PREFIX_TABLE (PREFIX_0F3A44) },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     /* 48 */
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     /* 50 */
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     /* 58 */
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     /* 60 */
7441     { PREFIX_TABLE (PREFIX_0F3A60) },
7442     { PREFIX_TABLE (PREFIX_0F3A61) },
7443     { PREFIX_TABLE (PREFIX_0F3A62) },
7444     { PREFIX_TABLE (PREFIX_0F3A63) },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     /* 68 */
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     /* 70 */
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     /* 78 */
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     /* 80 */
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     /* 88 */
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     /* 90 */
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     /* 98 */
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     /* a0 */
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     /* a8 */
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     /* b0 */
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     /* b8 */
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     /* c0 */
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     /* c8 */
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { PREFIX_TABLE (PREFIX_0F3ACC) },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     /* d0 */
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     /* d8 */
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { PREFIX_TABLE (PREFIX_0F3ADF) },
7584     /* e0 */
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     /* e8 */
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     /* f0 */
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     /* f8 */
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620   },
7621 };
7622
7623 static const struct dis386 xop_table[][256] = {
7624   /* XOP_08 */
7625   {
7626     /* 00 */
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     /* 08 */
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     /* 10 */
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     /* 18 */
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     /* 20 */
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     /* 28 */
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     /* 30 */
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     /* 38 */
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     /* 40 */
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     /* 48 */
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     /* 50 */
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     /* 58 */
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     /* 60 */
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     /* 68 */
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     /* 70 */
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     /* 78 */
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     /* 80 */
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7777     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7778     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7779     /* 88 */
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7787     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7788     /* 90 */
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7795     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7796     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7797     /* 98 */
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7805     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7806     /* a0 */
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7810     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7814     { Bad_Opcode },
7815     /* a8 */
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     /* b0 */
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7832     { Bad_Opcode },
7833     /* b8 */
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     /* c0 */
7843     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7844     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7845     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7846     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     /* c8 */
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7857     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7858     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7859     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7860     /* d0 */
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     /* d8 */
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     /* e0 */
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     /* e8 */
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7893     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7894     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7895     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7896     /* f0 */
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     /* f8 */
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914   },
7915   /* XOP_09 */
7916   {
7917     /* 00 */
7918     { Bad_Opcode },
7919     { REG_TABLE (REG_XOP_TBM_01) },
7920     { REG_TABLE (REG_XOP_TBM_02) },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     /* 08 */
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     /* 10 */
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { REG_TABLE (REG_XOP_LWPCB) },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     /* 18 */
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     /* 20 */
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     /* 28 */
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     /* 30 */
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     /* 38 */
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     /* 40 */
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     /* 48 */
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     /* 50 */
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     /* 58 */
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     /* 60 */
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     /* 68 */
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     /* 70 */
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     /* 78 */
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     /* 80 */
8062     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8063     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8064     { "vfrczss",        { XM, EXd }, 0 },
8065     { "vfrczsd",        { XM, EXq }, 0 },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     /* 88 */
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     /* 90 */
8080     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8081     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8082     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8083     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8084     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8085     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8086     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8087     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8088     /* 98 */
8089     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8090     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8091     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8092     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     /* a0 */
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     /* a8 */
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     /* b0 */
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     /* b8 */
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     /* c0 */
8134     { Bad_Opcode },
8135     { "vphaddbw",       { XM, EXxmm }, 0 },
8136     { "vphaddbd",       { XM, EXxmm }, 0 },
8137     { "vphaddbq",       { XM, EXxmm }, 0 },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { "vphaddwd",       { XM, EXxmm }, 0 },
8141     { "vphaddwq",       { XM, EXxmm }, 0 },
8142     /* c8 */
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { "vphadddq",       { XM, EXxmm }, 0 },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     /* d0 */
8152     { Bad_Opcode },
8153     { "vphaddubw",      { XM, EXxmm }, 0 },
8154     { "vphaddubd",      { XM, EXxmm }, 0 },
8155     { "vphaddubq",      { XM, EXxmm }, 0 },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { "vphadduwd",      { XM, EXxmm }, 0 },
8159     { "vphadduwq",      { XM, EXxmm }, 0 },
8160     /* d8 */
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { "vphaddudq",      { XM, EXxmm }, 0 },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     /* e0 */
8170     { Bad_Opcode },
8171     { "vphsubbw",       { XM, EXxmm }, 0 },
8172     { "vphsubwd",       { XM, EXxmm }, 0 },
8173     { "vphsubdq",       { XM, EXxmm }, 0 },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     /* e8 */
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     /* f0 */
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     /* f8 */
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205   },
8206   /* XOP_0A */
8207   {
8208     /* 00 */
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     /* 08 */
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     /* 10 */
8227     { "bextr",  { Gv, Ev, Iq }, 0 },
8228     { Bad_Opcode },
8229     { REG_TABLE (REG_XOP_LWP) },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     /* 18 */
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     /* 20 */
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     /* 28 */
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     /* 30 */
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     /* 38 */
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     /* 40 */
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     /* 48 */
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     /* 50 */
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     /* 58 */
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     /* 60 */
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     /* 68 */
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     /* 70 */
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     /* 78 */
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     /* 80 */
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     /* 88 */
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     /* 90 */
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     /* 98 */
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     /* a0 */
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     /* a8 */
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     /* b0 */
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     /* b8 */
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     /* c0 */
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     /* c8 */
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     /* d0 */
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     /* d8 */
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     /* e0 */
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     /* e8 */
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     /* f0 */
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     /* f8 */
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496   },
8497 };
8498
8499 static const struct dis386 vex_table[][256] = {
8500   /* VEX_0F */
8501   {
8502     /* 00 */
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     /* 08 */
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     /* 10 */
8521     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8522     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8523     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8524     { MOD_TABLE (MOD_VEX_0F13) },
8525     { VEX_W_TABLE (VEX_W_0F14) },
8526     { VEX_W_TABLE (VEX_W_0F15) },
8527     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8528     { MOD_TABLE (MOD_VEX_0F17) },
8529     /* 18 */
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     /* 20 */
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     /* 28 */
8548     { VEX_W_TABLE (VEX_W_0F28) },
8549     { VEX_W_TABLE (VEX_W_0F29) },
8550     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8551     { MOD_TABLE (MOD_VEX_0F2B) },
8552     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8554     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8556     /* 30 */
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     /* 38 */
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     /* 40 */
8575     { Bad_Opcode },
8576     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8577     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8578     { Bad_Opcode },
8579     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8580     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8581     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8582     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8583     /* 48 */
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8587     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     /* 50 */
8593     { MOD_TABLE (MOD_VEX_0F50) },
8594     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8595     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8596     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8597     { "vandpX",         { XM, Vex, EXx }, 0 },
8598     { "vandnpX",        { XM, Vex, EXx }, 0 },
8599     { "vorpX",          { XM, Vex, EXx }, 0 },
8600     { "vxorpX",         { XM, Vex, EXx }, 0 },
8601     /* 58 */
8602     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8603     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8604     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8605     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8606     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8607     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8608     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8609     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8610     /* 60 */
8611     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8612     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8613     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8614     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8615     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8616     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8617     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8618     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8619     /* 68 */
8620     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8621     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8622     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8623     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8624     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8625     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8626     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8627     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8628     /* 70 */
8629     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8630     { REG_TABLE (REG_VEX_0F71) },
8631     { REG_TABLE (REG_VEX_0F72) },
8632     { REG_TABLE (REG_VEX_0F73) },
8633     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8634     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8635     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8636     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8637     /* 78 */
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8644     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8645     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8646     /* 80 */
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     /* 88 */
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     /* 90 */
8665     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8666     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8667     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8668     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     /* 98 */
8674     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     /* a0 */
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     /* a8 */
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { REG_TABLE (REG_VEX_0FAE) },
8699     { Bad_Opcode },
8700     /* b0 */
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     /* b8 */
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     /* c0 */
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8722     { Bad_Opcode },
8723     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8724     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8725     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8726     { Bad_Opcode },
8727     /* c8 */
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     /* d0 */
8737     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8738     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8739     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8740     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8741     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8742     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8743     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8744     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8745     /* d8 */
8746     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8747     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8748     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8749     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8750     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8751     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8752     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8753     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8754     /* e0 */
8755     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8756     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8757     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8758     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8759     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8760     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8761     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8762     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8763     /* e8 */
8764     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8765     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8766     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8767     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8768     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8769     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8770     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8771     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8772     /* f0 */
8773     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8774     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8775     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8776     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8777     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8778     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8779     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8780     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8781     /* f8 */
8782     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8783     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8784     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8785     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8786     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8787     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8788     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8789     { Bad_Opcode },
8790   },
8791   /* VEX_0F38 */
8792   {
8793     /* 00 */
8794     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8800     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8802     /* 08 */
8803     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8811     /* 10 */
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8819     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8820     /* 18 */
8821     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8822     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8823     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8824     { Bad_Opcode },
8825     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8826     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8828     { Bad_Opcode },
8829     /* 20 */
8830     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8831     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8832     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8833     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8834     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8835     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     /* 28 */
8839     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8840     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8841     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8842     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8843     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8844     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8845     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8846     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8847     /* 30 */
8848     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8849     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8850     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8851     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8852     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8853     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8854     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8855     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8856     /* 38 */
8857     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8858     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8859     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8860     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8861     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8862     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8863     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8864     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8865     /* 40 */
8866     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8867     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8872     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8873     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8874     /* 48 */
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     /* 50 */
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     /* 58 */
8893     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     /* 60 */
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     /* 68 */
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     /* 70 */
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     /* 78 */
8929     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     /* 80 */
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     /* 88 */
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8952     { Bad_Opcode },
8953     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8954     { Bad_Opcode },
8955     /* 90 */
8956     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8958     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8963     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8964     /* 98 */
8965     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8969     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8973     /* a0 */
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8981     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8982     /* a8 */
8983     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8985     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8986     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8988     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8990     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8991     /* b0 */
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9000     /* b8 */
9001     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9009     /* c0 */
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     /* c8 */
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     /* d0 */
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     /* d8 */
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9045     /* e0 */
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     /* e8 */
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     /* f0 */
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9067     { REG_TABLE (REG_VEX_0F38F3) },
9068     { Bad_Opcode },
9069     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9072     /* f8 */
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081   },
9082   /* VEX_0F3A */
9083   {
9084     /* 00 */
9085     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9086     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9087     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9088     { Bad_Opcode },
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9092     { Bad_Opcode },
9093     /* 08 */
9094     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9102     /* 10 */
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9108     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9111     /* 18 */
9112     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9113     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     /* 20 */
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     /* 28 */
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     /* 30 */
9139     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9140     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9141     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9142     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     /* 38 */
9148     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9149     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     /* 40 */
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9158     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9159     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9160     { Bad_Opcode },
9161     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9162     { Bad_Opcode },
9163     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9164     { Bad_Opcode },
9165     /* 48 */
9166     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9167     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9168     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9169     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9170     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     /* 50 */
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     /* 58 */
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9189     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9190     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9191     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9192     /* 60 */
9193     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9194     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9195     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9196     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     /* 68 */
9202     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9203     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9204     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9205     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9206     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9207     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9208     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9209     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9210     /* 70 */
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     /* 78 */
9220     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9221     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9222     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9223     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9224     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9225     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9226     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9227     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9228     /* 80 */
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     /* 88 */
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     /* 90 */
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     /* 98 */
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     /* a0 */
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     /* a8 */
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     /* b0 */
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     /* b8 */
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     /* c0 */
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     /* c8 */
9310     { Bad_Opcode },
9311     { Bad_Opcode },
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315     { Bad_Opcode },
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     /* d0 */
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     /* d8 */
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9336     /* e0 */
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     /* e8 */
9346     { Bad_Opcode },
9347     { Bad_Opcode },
9348     { Bad_Opcode },
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     /* f0 */
9355     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     /* f8 */
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     { Bad_Opcode },
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372   },
9373 };
9374
9375 #define NEED_OPCODE_TABLE
9376 #include "i386-dis-evex.h"
9377 #undef NEED_OPCODE_TABLE
9378 static const struct dis386 vex_len_table[][2] = {
9379   /* VEX_LEN_0F10_P_1 */
9380   {
9381     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9382     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9383   },
9384
9385   /* VEX_LEN_0F10_P_3 */
9386   {
9387     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9388     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9389   },
9390
9391   /* VEX_LEN_0F11_P_1 */
9392   {
9393     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9394     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9395   },
9396
9397   /* VEX_LEN_0F11_P_3 */
9398   {
9399     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9400     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9401   },
9402
9403   /* VEX_LEN_0F12_P_0_M_0 */
9404   {
9405     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9406   },
9407
9408   /* VEX_LEN_0F12_P_0_M_1 */
9409   {
9410     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9411   },
9412
9413   /* VEX_LEN_0F12_P_2 */
9414   {
9415     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9416   },
9417
9418   /* VEX_LEN_0F13_M_0 */
9419   {
9420     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9421   },
9422
9423   /* VEX_LEN_0F16_P_0_M_0 */
9424   {
9425     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9426   },
9427
9428   /* VEX_LEN_0F16_P_0_M_1 */
9429   {
9430     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9431   },
9432
9433   /* VEX_LEN_0F16_P_2 */
9434   {
9435     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9436   },
9437
9438   /* VEX_LEN_0F17_M_0 */
9439   {
9440     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9441   },
9442
9443   /* VEX_LEN_0F2A_P_1 */
9444   {
9445     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9446     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9447   },
9448
9449   /* VEX_LEN_0F2A_P_3 */
9450   {
9451     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9452     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9453   },
9454
9455   /* VEX_LEN_0F2C_P_1 */
9456   {
9457     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9458     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9459   },
9460
9461   /* VEX_LEN_0F2C_P_3 */
9462   {
9463     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9464     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9465   },
9466
9467   /* VEX_LEN_0F2D_P_1 */
9468   {
9469     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9470     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9471   },
9472
9473   /* VEX_LEN_0F2D_P_3 */
9474   {
9475     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9476     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9477   },
9478
9479   /* VEX_LEN_0F2E_P_0 */
9480   {
9481     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9482     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9483   },
9484
9485   /* VEX_LEN_0F2E_P_2 */
9486   {
9487     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9488     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9489   },
9490
9491   /* VEX_LEN_0F2F_P_0 */
9492   {
9493     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9494     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9495   },
9496
9497   /* VEX_LEN_0F2F_P_2 */
9498   {
9499     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9500     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9501   },
9502
9503   /* VEX_LEN_0F41_P_0 */
9504   {
9505     { Bad_Opcode },
9506     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9507   },
9508   /* VEX_LEN_0F41_P_2 */
9509   {
9510     { Bad_Opcode },
9511     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9512   },
9513   /* VEX_LEN_0F42_P_0 */
9514   {
9515     { Bad_Opcode },
9516     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9517   },
9518   /* VEX_LEN_0F42_P_2 */
9519   {
9520     { Bad_Opcode },
9521     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9522   },
9523   /* VEX_LEN_0F44_P_0 */
9524   {
9525     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9526   },
9527   /* VEX_LEN_0F44_P_2 */
9528   {
9529     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9530   },
9531   /* VEX_LEN_0F45_P_0 */
9532   {
9533     { Bad_Opcode },
9534     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9535   },
9536   /* VEX_LEN_0F45_P_2 */
9537   {
9538     { Bad_Opcode },
9539     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9540   },
9541   /* VEX_LEN_0F46_P_0 */
9542   {
9543     { Bad_Opcode },
9544     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9545   },
9546   /* VEX_LEN_0F46_P_2 */
9547   {
9548     { Bad_Opcode },
9549     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9550   },
9551   /* VEX_LEN_0F47_P_0 */
9552   {
9553     { Bad_Opcode },
9554     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9555   },
9556   /* VEX_LEN_0F47_P_2 */
9557   {
9558     { Bad_Opcode },
9559     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9560   },
9561   /* VEX_LEN_0F4A_P_0 */
9562   {
9563     { Bad_Opcode },
9564     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9565   },
9566   /* VEX_LEN_0F4A_P_2 */
9567   {
9568     { Bad_Opcode },
9569     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9570   },
9571   /* VEX_LEN_0F4B_P_0 */
9572   {
9573     { Bad_Opcode },
9574     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9575   },
9576   /* VEX_LEN_0F4B_P_2 */
9577   {
9578     { Bad_Opcode },
9579     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9580   },
9581
9582   /* VEX_LEN_0F51_P_1 */
9583   {
9584     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9585     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9586   },
9587
9588   /* VEX_LEN_0F51_P_3 */
9589   {
9590     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9591     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9592   },
9593
9594   /* VEX_LEN_0F52_P_1 */
9595   {
9596     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9597     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9598   },
9599
9600   /* VEX_LEN_0F53_P_1 */
9601   {
9602     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9603     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9604   },
9605
9606   /* VEX_LEN_0F58_P_1 */
9607   {
9608     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9609     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9610   },
9611
9612   /* VEX_LEN_0F58_P_3 */
9613   {
9614     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9615     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9616   },
9617
9618   /* VEX_LEN_0F59_P_1 */
9619   {
9620     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9621     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9622   },
9623
9624   /* VEX_LEN_0F59_P_3 */
9625   {
9626     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9627     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9628   },
9629
9630   /* VEX_LEN_0F5A_P_1 */
9631   {
9632     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9633     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9634   },
9635
9636   /* VEX_LEN_0F5A_P_3 */
9637   {
9638     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9639     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9640   },
9641
9642   /* VEX_LEN_0F5C_P_1 */
9643   {
9644     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9645     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9646   },
9647
9648   /* VEX_LEN_0F5C_P_3 */
9649   {
9650     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9651     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9652   },
9653
9654   /* VEX_LEN_0F5D_P_1 */
9655   {
9656     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9657     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9658   },
9659
9660   /* VEX_LEN_0F5D_P_3 */
9661   {
9662     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9663     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9664   },
9665
9666   /* VEX_LEN_0F5E_P_1 */
9667   {
9668     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9669     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9670   },
9671
9672   /* VEX_LEN_0F5E_P_3 */
9673   {
9674     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9675     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9676   },
9677
9678   /* VEX_LEN_0F5F_P_1 */
9679   {
9680     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9681     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9682   },
9683
9684   /* VEX_LEN_0F5F_P_3 */
9685   {
9686     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9687     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9688   },
9689
9690   /* VEX_LEN_0F6E_P_2 */
9691   {
9692     { "vmovK",          { XMScalar, Edq }, 0 },
9693     { "vmovK",          { XMScalar, Edq }, 0 },
9694   },
9695
9696   /* VEX_LEN_0F7E_P_1 */
9697   {
9698     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9699     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9700   },
9701
9702   /* VEX_LEN_0F7E_P_2 */
9703   {
9704     { "vmovK",          { Edq, XMScalar }, 0 },
9705     { "vmovK",          { Edq, XMScalar }, 0 },
9706   },
9707
9708   /* VEX_LEN_0F90_P_0 */
9709   {
9710     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9711   },
9712
9713   /* VEX_LEN_0F90_P_2 */
9714   {
9715     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9716   },
9717
9718   /* VEX_LEN_0F91_P_0 */
9719   {
9720     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9721   },
9722
9723   /* VEX_LEN_0F91_P_2 */
9724   {
9725     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9726   },
9727
9728   /* VEX_LEN_0F92_P_0 */
9729   {
9730     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9731   },
9732
9733   /* VEX_LEN_0F92_P_2 */
9734   {
9735     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9736   },
9737
9738   /* VEX_LEN_0F92_P_3 */
9739   {
9740     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9741   },
9742
9743   /* VEX_LEN_0F93_P_0 */
9744   {
9745     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9746   },
9747
9748   /* VEX_LEN_0F93_P_2 */
9749   {
9750     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9751   },
9752
9753   /* VEX_LEN_0F93_P_3 */
9754   {
9755     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9756   },
9757
9758   /* VEX_LEN_0F98_P_0 */
9759   {
9760     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9761   },
9762
9763   /* VEX_LEN_0F98_P_2 */
9764   {
9765     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9766   },
9767
9768   /* VEX_LEN_0F99_P_0 */
9769   {
9770     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9771   },
9772
9773   /* VEX_LEN_0F99_P_2 */
9774   {
9775     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9776   },
9777
9778   /* VEX_LEN_0FAE_R_2_M_0 */
9779   {
9780     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9781   },
9782
9783   /* VEX_LEN_0FAE_R_3_M_0 */
9784   {
9785     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9786   },
9787
9788   /* VEX_LEN_0FC2_P_1 */
9789   {
9790     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9791     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9792   },
9793
9794   /* VEX_LEN_0FC2_P_3 */
9795   {
9796     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9797     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9798   },
9799
9800   /* VEX_LEN_0FC4_P_2 */
9801   {
9802     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9803   },
9804
9805   /* VEX_LEN_0FC5_P_2 */
9806   {
9807     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9808   },
9809
9810   /* VEX_LEN_0FD6_P_2 */
9811   {
9812     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9813     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9814   },
9815
9816   /* VEX_LEN_0FF7_P_2 */
9817   {
9818     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9819   },
9820
9821   /* VEX_LEN_0F3816_P_2 */
9822   {
9823     { Bad_Opcode },
9824     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9825   },
9826
9827   /* VEX_LEN_0F3819_P_2 */
9828   {
9829     { Bad_Opcode },
9830     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9831   },
9832
9833   /* VEX_LEN_0F381A_P_2_M_0 */
9834   {
9835     { Bad_Opcode },
9836     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9837   },
9838
9839   /* VEX_LEN_0F3836_P_2 */
9840   {
9841     { Bad_Opcode },
9842     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9843   },
9844
9845   /* VEX_LEN_0F3841_P_2 */
9846   {
9847     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9848   },
9849
9850   /* VEX_LEN_0F385A_P_2_M_0 */
9851   {
9852     { Bad_Opcode },
9853     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9854   },
9855
9856   /* VEX_LEN_0F38DB_P_2 */
9857   {
9858     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9859   },
9860
9861   /* VEX_LEN_0F38DC_P_2 */
9862   {
9863     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9864   },
9865
9866   /* VEX_LEN_0F38DD_P_2 */
9867   {
9868     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9869   },
9870
9871   /* VEX_LEN_0F38DE_P_2 */
9872   {
9873     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9874   },
9875
9876   /* VEX_LEN_0F38DF_P_2 */
9877   {
9878     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9879   },
9880
9881   /* VEX_LEN_0F38F2_P_0 */
9882   {
9883     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9884   },
9885
9886   /* VEX_LEN_0F38F3_R_1_P_0 */
9887   {
9888     { "blsrS",          { VexGdq, Edq }, 0 },
9889   },
9890
9891   /* VEX_LEN_0F38F3_R_2_P_0 */
9892   {
9893     { "blsmskS",        { VexGdq, Edq }, 0 },
9894   },
9895
9896   /* VEX_LEN_0F38F3_R_3_P_0 */
9897   {
9898     { "blsiS",          { VexGdq, Edq }, 0 },
9899   },
9900
9901   /* VEX_LEN_0F38F5_P_0 */
9902   {
9903     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9904   },
9905
9906   /* VEX_LEN_0F38F5_P_1 */
9907   {
9908     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9909   },
9910
9911   /* VEX_LEN_0F38F5_P_3 */
9912   {
9913     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9914   },
9915
9916   /* VEX_LEN_0F38F6_P_3 */
9917   {
9918     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9919   },
9920
9921   /* VEX_LEN_0F38F7_P_0 */
9922   {
9923     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9924   },
9925
9926   /* VEX_LEN_0F38F7_P_1 */
9927   {
9928     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9929   },
9930
9931   /* VEX_LEN_0F38F7_P_2 */
9932   {
9933     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9934   },
9935
9936   /* VEX_LEN_0F38F7_P_3 */
9937   {
9938     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9939   },
9940
9941   /* VEX_LEN_0F3A00_P_2 */
9942   {
9943     { Bad_Opcode },
9944     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9945   },
9946
9947   /* VEX_LEN_0F3A01_P_2 */
9948   {
9949     { Bad_Opcode },
9950     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9951   },
9952
9953   /* VEX_LEN_0F3A06_P_2 */
9954   {
9955     { Bad_Opcode },
9956     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9957   },
9958
9959   /* VEX_LEN_0F3A0A_P_2 */
9960   {
9961     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9962     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9963   },
9964
9965   /* VEX_LEN_0F3A0B_P_2 */
9966   {
9967     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9968     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9969   },
9970
9971   /* VEX_LEN_0F3A14_P_2 */
9972   {
9973     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9974   },
9975
9976   /* VEX_LEN_0F3A15_P_2 */
9977   {
9978     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9979   },
9980
9981   /* VEX_LEN_0F3A16_P_2  */
9982   {
9983     { "vpextrK",        { Edq, XM, Ib }, 0 },
9984   },
9985
9986   /* VEX_LEN_0F3A17_P_2 */
9987   {
9988     { "vextractps",     { Edqd, XM, Ib }, 0 },
9989   },
9990
9991   /* VEX_LEN_0F3A18_P_2 */
9992   {
9993     { Bad_Opcode },
9994     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9995   },
9996
9997   /* VEX_LEN_0F3A19_P_2 */
9998   {
9999     { Bad_Opcode },
10000     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10001   },
10002
10003   /* VEX_LEN_0F3A20_P_2 */
10004   {
10005     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10006   },
10007
10008   /* VEX_LEN_0F3A21_P_2 */
10009   {
10010     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10011   },
10012
10013   /* VEX_LEN_0F3A22_P_2 */
10014   {
10015     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10016   },
10017
10018   /* VEX_LEN_0F3A30_P_2 */
10019   {
10020     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10021   },
10022
10023   /* VEX_LEN_0F3A31_P_2 */
10024   {
10025     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10026   },
10027
10028   /* VEX_LEN_0F3A32_P_2 */
10029   {
10030     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10031   },
10032
10033   /* VEX_LEN_0F3A33_P_2 */
10034   {
10035     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10036   },
10037
10038   /* VEX_LEN_0F3A38_P_2 */
10039   {
10040     { Bad_Opcode },
10041     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10042   },
10043
10044   /* VEX_LEN_0F3A39_P_2 */
10045   {
10046     { Bad_Opcode },
10047     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10048   },
10049
10050   /* VEX_LEN_0F3A41_P_2 */
10051   {
10052     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10053   },
10054
10055   /* VEX_LEN_0F3A44_P_2 */
10056   {
10057     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10058   },
10059
10060   /* VEX_LEN_0F3A46_P_2 */
10061   {
10062     { Bad_Opcode },
10063     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10064   },
10065
10066   /* VEX_LEN_0F3A60_P_2 */
10067   {
10068     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10069   },
10070
10071   /* VEX_LEN_0F3A61_P_2 */
10072   {
10073     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10074   },
10075
10076   /* VEX_LEN_0F3A62_P_2 */
10077   {
10078     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10079   },
10080
10081   /* VEX_LEN_0F3A63_P_2 */
10082   {
10083     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10084   },
10085
10086   /* VEX_LEN_0F3A6A_P_2 */
10087   {
10088     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10089   },
10090
10091   /* VEX_LEN_0F3A6B_P_2 */
10092   {
10093     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10094   },
10095
10096   /* VEX_LEN_0F3A6E_P_2 */
10097   {
10098     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10099   },
10100
10101   /* VEX_LEN_0F3A6F_P_2 */
10102   {
10103     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10104   },
10105
10106   /* VEX_LEN_0F3A7A_P_2 */
10107   {
10108     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10109   },
10110
10111   /* VEX_LEN_0F3A7B_P_2 */
10112   {
10113     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10114   },
10115
10116   /* VEX_LEN_0F3A7E_P_2 */
10117   {
10118     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10119   },
10120
10121   /* VEX_LEN_0F3A7F_P_2 */
10122   {
10123     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10124   },
10125
10126   /* VEX_LEN_0F3ADF_P_2 */
10127   {
10128     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10129   },
10130
10131   /* VEX_LEN_0F3AF0_P_3 */
10132   {
10133     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10134   },
10135
10136   /* VEX_LEN_0FXOP_08_CC */
10137   {
10138      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10139   },
10140
10141   /* VEX_LEN_0FXOP_08_CD */
10142   {
10143      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10144   },
10145
10146   /* VEX_LEN_0FXOP_08_CE */
10147   {
10148      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10149   },
10150
10151   /* VEX_LEN_0FXOP_08_CF */
10152   {
10153      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10154   },
10155
10156   /* VEX_LEN_0FXOP_08_EC */
10157   {
10158      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10159   },
10160
10161   /* VEX_LEN_0FXOP_08_ED */
10162   {
10163      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10164   },
10165
10166   /* VEX_LEN_0FXOP_08_EE */
10167   {
10168      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10169   },
10170
10171   /* VEX_LEN_0FXOP_08_EF */
10172   {
10173      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10174   },
10175
10176   /* VEX_LEN_0FXOP_09_80 */
10177   {
10178     { "vfrczps",        { XM, EXxmm }, 0 },
10179     { "vfrczps",        { XM, EXymmq }, 0 },
10180   },
10181
10182   /* VEX_LEN_0FXOP_09_81 */
10183   {
10184     { "vfrczpd",        { XM, EXxmm }, 0 },
10185     { "vfrczpd",        { XM, EXymmq }, 0 },
10186   },
10187 };
10188
10189 static const struct dis386 vex_w_table[][2] = {
10190   {
10191     /* VEX_W_0F10_P_0 */
10192     { "vmovups",        { XM, EXx }, 0 },
10193   },
10194   {
10195     /* VEX_W_0F10_P_1 */
10196     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10197   },
10198   {
10199     /* VEX_W_0F10_P_2 */
10200     { "vmovupd",        { XM, EXx }, 0 },
10201   },
10202   {
10203     /* VEX_W_0F10_P_3 */
10204     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10205   },
10206   {
10207     /* VEX_W_0F11_P_0 */
10208     { "vmovups",        { EXxS, XM }, 0 },
10209   },
10210   {
10211     /* VEX_W_0F11_P_1 */
10212     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10213   },
10214   {
10215     /* VEX_W_0F11_P_2 */
10216     { "vmovupd",        { EXxS, XM }, 0 },
10217   },
10218   {
10219     /* VEX_W_0F11_P_3 */
10220     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10221   },
10222   {
10223     /* VEX_W_0F12_P_0_M_0 */
10224     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10225   },
10226   {
10227     /* VEX_W_0F12_P_0_M_1 */
10228     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10229   },
10230   {
10231     /* VEX_W_0F12_P_1 */
10232     { "vmovsldup",      { XM, EXx }, 0 },
10233   },
10234   {
10235     /* VEX_W_0F12_P_2 */
10236     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10237   },
10238   {
10239     /* VEX_W_0F12_P_3 */
10240     { "vmovddup",       { XM, EXymmq }, 0 },
10241   },
10242   {
10243     /* VEX_W_0F13_M_0 */
10244     { "vmovlpX",        { EXq, XM }, 0 },
10245   },
10246   {
10247     /* VEX_W_0F14 */
10248     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10249   },
10250   {
10251     /* VEX_W_0F15 */
10252     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10253   },
10254   {
10255     /* VEX_W_0F16_P_0_M_0 */
10256     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10257   },
10258   {
10259     /* VEX_W_0F16_P_0_M_1 */
10260     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10261   },
10262   {
10263     /* VEX_W_0F16_P_1 */
10264     { "vmovshdup",      { XM, EXx }, 0 },
10265   },
10266   {
10267     /* VEX_W_0F16_P_2 */
10268     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10269   },
10270   {
10271     /* VEX_W_0F17_M_0 */
10272     { "vmovhpX",        { EXq, XM }, 0 },
10273   },
10274   {
10275     /* VEX_W_0F28 */
10276     { "vmovapX",        { XM, EXx }, 0 },
10277   },
10278   {
10279     /* VEX_W_0F29 */
10280     { "vmovapX",        { EXxS, XM }, 0 },
10281   },
10282   {
10283     /* VEX_W_0F2B_M_0 */
10284     { "vmovntpX",       { Mx, XM }, 0 },
10285   },
10286   {
10287     /* VEX_W_0F2E_P_0 */
10288     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10289   },
10290   {
10291     /* VEX_W_0F2E_P_2 */
10292     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10293   },
10294   {
10295     /* VEX_W_0F2F_P_0 */
10296     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10297   },
10298   {
10299     /* VEX_W_0F2F_P_2 */
10300     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10301   },
10302   {
10303     /* VEX_W_0F41_P_0_LEN_1 */
10304     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10305     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10306   },
10307   {
10308     /* VEX_W_0F41_P_2_LEN_1 */
10309     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10310     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10311   },
10312   {
10313     /* VEX_W_0F42_P_0_LEN_1 */
10314     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10315     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10316   },
10317   {
10318     /* VEX_W_0F42_P_2_LEN_1 */
10319     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10320     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10321   },
10322   {
10323     /* VEX_W_0F44_P_0_LEN_0 */
10324     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10325     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10326   },
10327   {
10328     /* VEX_W_0F44_P_2_LEN_0 */
10329     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10330     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10331   },
10332   {
10333     /* VEX_W_0F45_P_0_LEN_1 */
10334     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10335     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10336   },
10337   {
10338     /* VEX_W_0F45_P_2_LEN_1 */
10339     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10340     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10341   },
10342   {
10343     /* VEX_W_0F46_P_0_LEN_1 */
10344     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10345     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10346   },
10347   {
10348     /* VEX_W_0F46_P_2_LEN_1 */
10349     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10350     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10351   },
10352   {
10353     /* VEX_W_0F47_P_0_LEN_1 */
10354     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10355     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10356   },
10357   {
10358     /* VEX_W_0F47_P_2_LEN_1 */
10359     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10360     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10361   },
10362   {
10363     /* VEX_W_0F4A_P_0_LEN_1 */
10364     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10365     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10366   },
10367   {
10368     /* VEX_W_0F4A_P_2_LEN_1 */
10369     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10370     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10371   },
10372   {
10373     /* VEX_W_0F4B_P_0_LEN_1 */
10374     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10375     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10376   },
10377   {
10378     /* VEX_W_0F4B_P_2_LEN_1 */
10379     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10380   },
10381   {
10382     /* VEX_W_0F50_M_0 */
10383     { "vmovmskpX",      { Gdq, XS }, 0 },
10384   },
10385   {
10386     /* VEX_W_0F51_P_0 */
10387     { "vsqrtps",        { XM, EXx }, 0 },
10388   },
10389   {
10390     /* VEX_W_0F51_P_1 */
10391     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10392   },
10393   {
10394     /* VEX_W_0F51_P_2  */
10395     { "vsqrtpd",        { XM, EXx }, 0 },
10396   },
10397   {
10398     /* VEX_W_0F51_P_3 */
10399     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10400   },
10401   {
10402     /* VEX_W_0F52_P_0 */
10403     { "vrsqrtps",       { XM, EXx }, 0 },
10404   },
10405   {
10406     /* VEX_W_0F52_P_1 */
10407     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10408   },
10409   {
10410     /* VEX_W_0F53_P_0  */
10411     { "vrcpps",         { XM, EXx }, 0 },
10412   },
10413   {
10414     /* VEX_W_0F53_P_1  */
10415     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10416   },
10417   {
10418     /* VEX_W_0F58_P_0  */
10419     { "vaddps",         { XM, Vex, EXx }, 0 },
10420   },
10421   {
10422     /* VEX_W_0F58_P_1  */
10423     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10424   },
10425   {
10426     /* VEX_W_0F58_P_2  */
10427     { "vaddpd",         { XM, Vex, EXx }, 0 },
10428   },
10429   {
10430     /* VEX_W_0F58_P_3  */
10431     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10432   },
10433   {
10434     /* VEX_W_0F59_P_0  */
10435     { "vmulps",         { XM, Vex, EXx }, 0 },
10436   },
10437   {
10438     /* VEX_W_0F59_P_1  */
10439     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10440   },
10441   {
10442     /* VEX_W_0F59_P_2  */
10443     { "vmulpd",         { XM, Vex, EXx }, 0 },
10444   },
10445   {
10446     /* VEX_W_0F59_P_3  */
10447     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10448   },
10449   {
10450     /* VEX_W_0F5A_P_0  */
10451     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10452   },
10453   {
10454     /* VEX_W_0F5A_P_1  */
10455     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10456   },
10457   {
10458     /* VEX_W_0F5A_P_3  */
10459     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10460   },
10461   {
10462     /* VEX_W_0F5B_P_0  */
10463     { "vcvtdq2ps",      { XM, EXx }, 0 },
10464   },
10465   {
10466     /* VEX_W_0F5B_P_1  */
10467     { "vcvttps2dq",     { XM, EXx }, 0 },
10468   },
10469   {
10470     /* VEX_W_0F5B_P_2  */
10471     { "vcvtps2dq",      { XM, EXx }, 0 },
10472   },
10473   {
10474     /* VEX_W_0F5C_P_0  */
10475     { "vsubps",         { XM, Vex, EXx }, 0 },
10476   },
10477   {
10478     /* VEX_W_0F5C_P_1  */
10479     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10480   },
10481   {
10482     /* VEX_W_0F5C_P_2  */
10483     { "vsubpd",         { XM, Vex, EXx }, 0 },
10484   },
10485   {
10486     /* VEX_W_0F5C_P_3  */
10487     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10488   },
10489   {
10490     /* VEX_W_0F5D_P_0  */
10491     { "vminps",         { XM, Vex, EXx }, 0 },
10492   },
10493   {
10494     /* VEX_W_0F5D_P_1  */
10495     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10496   },
10497   {
10498     /* VEX_W_0F5D_P_2  */
10499     { "vminpd",         { XM, Vex, EXx }, 0 },
10500   },
10501   {
10502     /* VEX_W_0F5D_P_3  */
10503     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10504   },
10505   {
10506     /* VEX_W_0F5E_P_0  */
10507     { "vdivps",         { XM, Vex, EXx }, 0 },
10508   },
10509   {
10510     /* VEX_W_0F5E_P_1  */
10511     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10512   },
10513   {
10514     /* VEX_W_0F5E_P_2  */
10515     { "vdivpd",         { XM, Vex, EXx }, 0 },
10516   },
10517   {
10518     /* VEX_W_0F5E_P_3  */
10519     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10520   },
10521   {
10522     /* VEX_W_0F5F_P_0  */
10523     { "vmaxps",         { XM, Vex, EXx }, 0 },
10524   },
10525   {
10526     /* VEX_W_0F5F_P_1  */
10527     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10528   },
10529   {
10530     /* VEX_W_0F5F_P_2  */
10531     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10532   },
10533   {
10534     /* VEX_W_0F5F_P_3  */
10535     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10536   },
10537   {
10538     /* VEX_W_0F60_P_2  */
10539     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10540   },
10541   {
10542     /* VEX_W_0F61_P_2  */
10543     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10544   },
10545   {
10546     /* VEX_W_0F62_P_2  */
10547     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10548   },
10549   {
10550     /* VEX_W_0F63_P_2  */
10551     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10552   },
10553   {
10554     /* VEX_W_0F64_P_2  */
10555     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10556   },
10557   {
10558     /* VEX_W_0F65_P_2  */
10559     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10560   },
10561   {
10562     /* VEX_W_0F66_P_2  */
10563     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10564   },
10565   {
10566     /* VEX_W_0F67_P_2  */
10567     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10568   },
10569   {
10570     /* VEX_W_0F68_P_2  */
10571     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10572   },
10573   {
10574     /* VEX_W_0F69_P_2  */
10575     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10576   },
10577   {
10578     /* VEX_W_0F6A_P_2  */
10579     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10580   },
10581   {
10582     /* VEX_W_0F6B_P_2  */
10583     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10584   },
10585   {
10586     /* VEX_W_0F6C_P_2  */
10587     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10588   },
10589   {
10590     /* VEX_W_0F6D_P_2  */
10591     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10592   },
10593   {
10594     /* VEX_W_0F6F_P_1  */
10595     { "vmovdqu",        { XM, EXx }, 0 },
10596   },
10597   {
10598     /* VEX_W_0F6F_P_2  */
10599     { "vmovdqa",        { XM, EXx }, 0 },
10600   },
10601   {
10602     /* VEX_W_0F70_P_1 */
10603     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10604   },
10605   {
10606     /* VEX_W_0F70_P_2 */
10607     { "vpshufd",        { XM, EXx, Ib }, 0 },
10608   },
10609   {
10610     /* VEX_W_0F70_P_3 */
10611     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10612   },
10613   {
10614     /* VEX_W_0F71_R_2_P_2  */
10615     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10616   },
10617   {
10618     /* VEX_W_0F71_R_4_P_2  */
10619     { "vpsraw",         { Vex, XS, Ib }, 0 },
10620   },
10621   {
10622     /* VEX_W_0F71_R_6_P_2  */
10623     { "vpsllw",         { Vex, XS, Ib }, 0 },
10624   },
10625   {
10626     /* VEX_W_0F72_R_2_P_2  */
10627     { "vpsrld",         { Vex, XS, Ib }, 0 },
10628   },
10629   {
10630     /* VEX_W_0F72_R_4_P_2  */
10631     { "vpsrad",         { Vex, XS, Ib }, 0 },
10632   },
10633   {
10634     /* VEX_W_0F72_R_6_P_2  */
10635     { "vpslld",         { Vex, XS, Ib }, 0 },
10636   },
10637   {
10638     /* VEX_W_0F73_R_2_P_2  */
10639     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10640   },
10641   {
10642     /* VEX_W_0F73_R_3_P_2  */
10643     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10644   },
10645   {
10646     /* VEX_W_0F73_R_6_P_2  */
10647     { "vpsllq",         { Vex, XS, Ib }, 0 },
10648   },
10649   {
10650     /* VEX_W_0F73_R_7_P_2  */
10651     { "vpslldq",        { Vex, XS, Ib }, 0 },
10652   },
10653   {
10654     /* VEX_W_0F74_P_2 */
10655     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10656   },
10657   {
10658     /* VEX_W_0F75_P_2 */
10659     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10660   },
10661   {
10662     /* VEX_W_0F76_P_2 */
10663     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10664   },
10665   {
10666     /* VEX_W_0F77_P_0 */
10667     { "",               { VZERO }, 0 },
10668   },
10669   {
10670     /* VEX_W_0F7C_P_2 */
10671     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10672   },
10673   {
10674     /* VEX_W_0F7C_P_3 */
10675     { "vhaddps",        { XM, Vex, EXx }, 0 },
10676   },
10677   {
10678     /* VEX_W_0F7D_P_2 */
10679     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10680   },
10681   {
10682     /* VEX_W_0F7D_P_3 */
10683     { "vhsubps",        { XM, Vex, EXx }, 0 },
10684   },
10685   {
10686     /* VEX_W_0F7E_P_1 */
10687     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10688   },
10689   {
10690     /* VEX_W_0F7F_P_1 */
10691     { "vmovdqu",        { EXxS, XM }, 0 },
10692   },
10693   {
10694     /* VEX_W_0F7F_P_2 */
10695     { "vmovdqa",        { EXxS, XM }, 0 },
10696   },
10697   {
10698     /* VEX_W_0F90_P_0_LEN_0 */
10699     { "kmovw",          { MaskG, MaskE }, 0 },
10700     { "kmovq",          { MaskG, MaskE }, 0 },
10701   },
10702   {
10703     /* VEX_W_0F90_P_2_LEN_0 */
10704     { "kmovb",          { MaskG, MaskBDE }, 0 },
10705     { "kmovd",          { MaskG, MaskBDE }, 0 },
10706   },
10707   {
10708     /* VEX_W_0F91_P_0_LEN_0 */
10709     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10710     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10711   },
10712   {
10713     /* VEX_W_0F91_P_2_LEN_0 */
10714     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10715     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10716   },
10717   {
10718     /* VEX_W_0F92_P_0_LEN_0 */
10719     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10720   },
10721   {
10722     /* VEX_W_0F92_P_2_LEN_0 */
10723     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10724   },
10725   {
10726     /* VEX_W_0F92_P_3_LEN_0 */
10727     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10728     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10729   },
10730   {
10731     /* VEX_W_0F93_P_0_LEN_0 */
10732     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10733   },
10734   {
10735     /* VEX_W_0F93_P_2_LEN_0 */
10736     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10737   },
10738   {
10739     /* VEX_W_0F93_P_3_LEN_0 */
10740     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10741     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10742   },
10743   {
10744     /* VEX_W_0F98_P_0_LEN_0 */
10745     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10746     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10747   },
10748   {
10749     /* VEX_W_0F98_P_2_LEN_0 */
10750     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10751     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10752   },
10753   {
10754     /* VEX_W_0F99_P_0_LEN_0 */
10755     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10756     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10757   },
10758   {
10759     /* VEX_W_0F99_P_2_LEN_0 */
10760     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10761     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10762   },
10763   {
10764     /* VEX_W_0FAE_R_2_M_0 */
10765     { "vldmxcsr",       { Md }, 0 },
10766   },
10767   {
10768     /* VEX_W_0FAE_R_3_M_0 */
10769     { "vstmxcsr",       { Md }, 0 },
10770   },
10771   {
10772     /* VEX_W_0FC2_P_0 */
10773     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10774   },
10775   {
10776     /* VEX_W_0FC2_P_1 */
10777     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10778   },
10779   {
10780     /* VEX_W_0FC2_P_2 */
10781     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10782   },
10783   {
10784     /* VEX_W_0FC2_P_3 */
10785     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10786   },
10787   {
10788     /* VEX_W_0FC4_P_2 */
10789     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10790   },
10791   {
10792     /* VEX_W_0FC5_P_2 */
10793     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10794   },
10795   {
10796     /* VEX_W_0FD0_P_2 */
10797     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10798   },
10799   {
10800     /* VEX_W_0FD0_P_3 */
10801     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10802   },
10803   {
10804     /* VEX_W_0FD1_P_2 */
10805     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10806   },
10807   {
10808     /* VEX_W_0FD2_P_2 */
10809     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10810   },
10811   {
10812     /* VEX_W_0FD3_P_2 */
10813     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10814   },
10815   {
10816     /* VEX_W_0FD4_P_2 */
10817     { "vpaddq",         { XM, Vex, EXx }, 0 },
10818   },
10819   {
10820     /* VEX_W_0FD5_P_2 */
10821     { "vpmullw",        { XM, Vex, EXx }, 0 },
10822   },
10823   {
10824     /* VEX_W_0FD6_P_2 */
10825     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10826   },
10827   {
10828     /* VEX_W_0FD7_P_2_M_1 */
10829     { "vpmovmskb",      { Gdq, XS }, 0 },
10830   },
10831   {
10832     /* VEX_W_0FD8_P_2 */
10833     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10834   },
10835   {
10836     /* VEX_W_0FD9_P_2 */
10837     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10838   },
10839   {
10840     /* VEX_W_0FDA_P_2 */
10841     { "vpminub",        { XM, Vex, EXx }, 0 },
10842   },
10843   {
10844     /* VEX_W_0FDB_P_2 */
10845     { "vpand",          { XM, Vex, EXx }, 0 },
10846   },
10847   {
10848     /* VEX_W_0FDC_P_2 */
10849     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10850   },
10851   {
10852     /* VEX_W_0FDD_P_2 */
10853     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10854   },
10855   {
10856     /* VEX_W_0FDE_P_2 */
10857     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10858   },
10859   {
10860     /* VEX_W_0FDF_P_2 */
10861     { "vpandn",         { XM, Vex, EXx }, 0 },
10862   },
10863   {
10864     /* VEX_W_0FE0_P_2  */
10865     { "vpavgb",         { XM, Vex, EXx }, 0 },
10866   },
10867   {
10868     /* VEX_W_0FE1_P_2  */
10869     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10870   },
10871   {
10872     /* VEX_W_0FE2_P_2  */
10873     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10874   },
10875   {
10876     /* VEX_W_0FE3_P_2  */
10877     { "vpavgw",         { XM, Vex, EXx }, 0 },
10878   },
10879   {
10880     /* VEX_W_0FE4_P_2  */
10881     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
10882   },
10883   {
10884     /* VEX_W_0FE5_P_2  */
10885     { "vpmulhw",        { XM, Vex, EXx }, 0 },
10886   },
10887   {
10888     /* VEX_W_0FE6_P_1  */
10889     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
10890   },
10891   {
10892     /* VEX_W_0FE6_P_2  */
10893     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
10894   },
10895   {
10896     /* VEX_W_0FE6_P_3  */
10897     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
10898   },
10899   {
10900     /* VEX_W_0FE7_P_2_M_0 */
10901     { "vmovntdq",       { Mx, XM }, 0 },
10902   },
10903   {
10904     /* VEX_W_0FE8_P_2  */
10905     { "vpsubsb",        { XM, Vex, EXx }, 0 },
10906   },
10907   {
10908     /* VEX_W_0FE9_P_2  */
10909     { "vpsubsw",        { XM, Vex, EXx }, 0 },
10910   },
10911   {
10912     /* VEX_W_0FEA_P_2  */
10913     { "vpminsw",        { XM, Vex, EXx }, 0 },
10914   },
10915   {
10916     /* VEX_W_0FEB_P_2  */
10917     { "vpor",           { XM, Vex, EXx }, 0 },
10918   },
10919   {
10920     /* VEX_W_0FEC_P_2  */
10921     { "vpaddsb",        { XM, Vex, EXx }, 0 },
10922   },
10923   {
10924     /* VEX_W_0FED_P_2  */
10925     { "vpaddsw",        { XM, Vex, EXx }, 0 },
10926   },
10927   {
10928     /* VEX_W_0FEE_P_2  */
10929     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
10930   },
10931   {
10932     /* VEX_W_0FEF_P_2  */
10933     { "vpxor",          { XM, Vex, EXx }, 0 },
10934   },
10935   {
10936     /* VEX_W_0FF0_P_3_M_0 */
10937     { "vlddqu",         { XM, M }, 0 },
10938   },
10939   {
10940     /* VEX_W_0FF1_P_2 */
10941     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
10942   },
10943   {
10944     /* VEX_W_0FF2_P_2 */
10945     { "vpslld",         { XM, Vex, EXxmm }, 0 },
10946   },
10947   {
10948     /* VEX_W_0FF3_P_2 */
10949     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
10950   },
10951   {
10952     /* VEX_W_0FF4_P_2 */
10953     { "vpmuludq",       { XM, Vex, EXx }, 0 },
10954   },
10955   {
10956     /* VEX_W_0FF5_P_2 */
10957     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
10958   },
10959   {
10960     /* VEX_W_0FF6_P_2 */
10961     { "vpsadbw",        { XM, Vex, EXx }, 0 },
10962   },
10963   {
10964     /* VEX_W_0FF7_P_2 */
10965     { "vmaskmovdqu",    { XM, XS }, 0 },
10966   },
10967   {
10968     /* VEX_W_0FF8_P_2 */
10969     { "vpsubb",         { XM, Vex, EXx }, 0 },
10970   },
10971   {
10972     /* VEX_W_0FF9_P_2 */
10973     { "vpsubw",         { XM, Vex, EXx }, 0 },
10974   },
10975   {
10976     /* VEX_W_0FFA_P_2 */
10977     { "vpsubd",         { XM, Vex, EXx }, 0 },
10978   },
10979   {
10980     /* VEX_W_0FFB_P_2 */
10981     { "vpsubq",         { XM, Vex, EXx }, 0 },
10982   },
10983   {
10984     /* VEX_W_0FFC_P_2 */
10985     { "vpaddb",         { XM, Vex, EXx }, 0 },
10986   },
10987   {
10988     /* VEX_W_0FFD_P_2 */
10989     { "vpaddw",         { XM, Vex, EXx }, 0 },
10990   },
10991   {
10992     /* VEX_W_0FFE_P_2 */
10993     { "vpaddd",         { XM, Vex, EXx }, 0 },
10994   },
10995   {
10996     /* VEX_W_0F3800_P_2  */
10997     { "vpshufb",        { XM, Vex, EXx }, 0 },
10998   },
10999   {
11000     /* VEX_W_0F3801_P_2  */
11001     { "vphaddw",        { XM, Vex, EXx }, 0 },
11002   },
11003   {
11004     /* VEX_W_0F3802_P_2  */
11005     { "vphaddd",        { XM, Vex, EXx }, 0 },
11006   },
11007   {
11008     /* VEX_W_0F3803_P_2  */
11009     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11010   },
11011   {
11012     /* VEX_W_0F3804_P_2  */
11013     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11014   },
11015   {
11016     /* VEX_W_0F3805_P_2  */
11017     { "vphsubw",        { XM, Vex, EXx }, 0 },
11018   },
11019   {
11020     /* VEX_W_0F3806_P_2  */
11021     { "vphsubd",        { XM, Vex, EXx }, 0 },
11022   },
11023   {
11024     /* VEX_W_0F3807_P_2  */
11025     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11026   },
11027   {
11028     /* VEX_W_0F3808_P_2  */
11029     { "vpsignb",        { XM, Vex, EXx }, 0 },
11030   },
11031   {
11032     /* VEX_W_0F3809_P_2  */
11033     { "vpsignw",        { XM, Vex, EXx }, 0 },
11034   },
11035   {
11036     /* VEX_W_0F380A_P_2  */
11037     { "vpsignd",        { XM, Vex, EXx }, 0 },
11038   },
11039   {
11040     /* VEX_W_0F380B_P_2  */
11041     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11042   },
11043   {
11044     /* VEX_W_0F380C_P_2  */
11045     { "vpermilps",      { XM, Vex, EXx }, 0 },
11046   },
11047   {
11048     /* VEX_W_0F380D_P_2  */
11049     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11050   },
11051   {
11052     /* VEX_W_0F380E_P_2  */
11053     { "vtestps",        { XM, EXx }, 0 },
11054   },
11055   {
11056     /* VEX_W_0F380F_P_2  */
11057     { "vtestpd",        { XM, EXx }, 0 },
11058   },
11059   {
11060     /* VEX_W_0F3816_P_2  */
11061     { "vpermps",        { XM, Vex, EXx }, 0 },
11062   },
11063   {
11064     /* VEX_W_0F3817_P_2 */
11065     { "vptest",         { XM, EXx }, 0 },
11066   },
11067   {
11068     /* VEX_W_0F3818_P_2 */
11069     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11070   },
11071   {
11072     /* VEX_W_0F3819_P_2 */
11073     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11074   },
11075   {
11076     /* VEX_W_0F381A_P_2_M_0 */
11077     { "vbroadcastf128", { XM, Mxmm }, 0 },
11078   },
11079   {
11080     /* VEX_W_0F381C_P_2 */
11081     { "vpabsb",         { XM, EXx }, 0 },
11082   },
11083   {
11084     /* VEX_W_0F381D_P_2 */
11085     { "vpabsw",         { XM, EXx }, 0 },
11086   },
11087   {
11088     /* VEX_W_0F381E_P_2 */
11089     { "vpabsd",         { XM, EXx }, 0 },
11090   },
11091   {
11092     /* VEX_W_0F3820_P_2 */
11093     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11094   },
11095   {
11096     /* VEX_W_0F3821_P_2 */
11097     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11098   },
11099   {
11100     /* VEX_W_0F3822_P_2 */
11101     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11102   },
11103   {
11104     /* VEX_W_0F3823_P_2 */
11105     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11106   },
11107   {
11108     /* VEX_W_0F3824_P_2 */
11109     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11110   },
11111   {
11112     /* VEX_W_0F3825_P_2 */
11113     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11114   },
11115   {
11116     /* VEX_W_0F3828_P_2 */
11117     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11118   },
11119   {
11120     /* VEX_W_0F3829_P_2 */
11121     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11122   },
11123   {
11124     /* VEX_W_0F382A_P_2_M_0 */
11125     { "vmovntdqa",      { XM, Mx }, 0 },
11126   },
11127   {
11128     /* VEX_W_0F382B_P_2 */
11129     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11130   },
11131   {
11132     /* VEX_W_0F382C_P_2_M_0 */
11133     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11134   },
11135   {
11136     /* VEX_W_0F382D_P_2_M_0 */
11137     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11138   },
11139   {
11140     /* VEX_W_0F382E_P_2_M_0 */
11141     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11142   },
11143   {
11144     /* VEX_W_0F382F_P_2_M_0 */
11145     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11146   },
11147   {
11148     /* VEX_W_0F3830_P_2 */
11149     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11150   },
11151   {
11152     /* VEX_W_0F3831_P_2 */
11153     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11154   },
11155   {
11156     /* VEX_W_0F3832_P_2 */
11157     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11158   },
11159   {
11160     /* VEX_W_0F3833_P_2 */
11161     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11162   },
11163   {
11164     /* VEX_W_0F3834_P_2 */
11165     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11166   },
11167   {
11168     /* VEX_W_0F3835_P_2 */
11169     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11170   },
11171   {
11172     /* VEX_W_0F3836_P_2  */
11173     { "vpermd",         { XM, Vex, EXx }, 0 },
11174   },
11175   {
11176     /* VEX_W_0F3837_P_2 */
11177     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11178   },
11179   {
11180     /* VEX_W_0F3838_P_2 */
11181     { "vpminsb",        { XM, Vex, EXx }, 0 },
11182   },
11183   {
11184     /* VEX_W_0F3839_P_2 */
11185     { "vpminsd",        { XM, Vex, EXx }, 0 },
11186   },
11187   {
11188     /* VEX_W_0F383A_P_2 */
11189     { "vpminuw",        { XM, Vex, EXx }, 0 },
11190   },
11191   {
11192     /* VEX_W_0F383B_P_2 */
11193     { "vpminud",        { XM, Vex, EXx }, 0 },
11194   },
11195   {
11196     /* VEX_W_0F383C_P_2 */
11197     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11198   },
11199   {
11200     /* VEX_W_0F383D_P_2 */
11201     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11202   },
11203   {
11204     /* VEX_W_0F383E_P_2 */
11205     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11206   },
11207   {
11208     /* VEX_W_0F383F_P_2 */
11209     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11210   },
11211   {
11212     /* VEX_W_0F3840_P_2 */
11213     { "vpmulld",        { XM, Vex, EXx }, 0 },
11214   },
11215   {
11216     /* VEX_W_0F3841_P_2 */
11217     { "vphminposuw",    { XM, EXx }, 0 },
11218   },
11219   {
11220     /* VEX_W_0F3846_P_2 */
11221     { "vpsravd",        { XM, Vex, EXx }, 0 },
11222   },
11223   {
11224     /* VEX_W_0F3858_P_2 */
11225     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11226   },
11227   {
11228     /* VEX_W_0F3859_P_2 */
11229     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11230   },
11231   {
11232     /* VEX_W_0F385A_P_2_M_0 */
11233     { "vbroadcasti128", { XM, Mxmm }, 0 },
11234   },
11235   {
11236     /* VEX_W_0F3878_P_2 */
11237     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11238   },
11239   {
11240     /* VEX_W_0F3879_P_2 */
11241     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11242   },
11243   {
11244     /* VEX_W_0F38DB_P_2 */
11245     { "vaesimc",        { XM, EXx }, 0 },
11246   },
11247   {
11248     /* VEX_W_0F38DC_P_2 */
11249     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11250   },
11251   {
11252     /* VEX_W_0F38DD_P_2 */
11253     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11254   },
11255   {
11256     /* VEX_W_0F38DE_P_2 */
11257     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11258   },
11259   {
11260     /* VEX_W_0F38DF_P_2 */
11261     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11262   },
11263   {
11264     /* VEX_W_0F3A00_P_2 */
11265     { Bad_Opcode },
11266     { "vpermq",         { XM, EXx, Ib }, 0 },
11267   },
11268   {
11269     /* VEX_W_0F3A01_P_2 */
11270     { Bad_Opcode },
11271     { "vpermpd",        { XM, EXx, Ib }, 0 },
11272   },
11273   {
11274     /* VEX_W_0F3A02_P_2 */
11275     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11276   },
11277   {
11278     /* VEX_W_0F3A04_P_2 */
11279     { "vpermilps",      { XM, EXx, Ib }, 0 },
11280   },
11281   {
11282     /* VEX_W_0F3A05_P_2 */
11283     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11284   },
11285   {
11286     /* VEX_W_0F3A06_P_2 */
11287     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11288   },
11289   {
11290     /* VEX_W_0F3A08_P_2 */
11291     { "vroundps",       { XM, EXx, Ib }, 0 },
11292   },
11293   {
11294     /* VEX_W_0F3A09_P_2 */
11295     { "vroundpd",       { XM, EXx, Ib }, 0 },
11296   },
11297   {
11298     /* VEX_W_0F3A0A_P_2 */
11299     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11300   },
11301   {
11302     /* VEX_W_0F3A0B_P_2 */
11303     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11304   },
11305   {
11306     /* VEX_W_0F3A0C_P_2 */
11307     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11308   },
11309   {
11310     /* VEX_W_0F3A0D_P_2 */
11311     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11312   },
11313   {
11314     /* VEX_W_0F3A0E_P_2 */
11315     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11316   },
11317   {
11318     /* VEX_W_0F3A0F_P_2 */
11319     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11320   },
11321   {
11322     /* VEX_W_0F3A14_P_2 */
11323     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11324   },
11325   {
11326     /* VEX_W_0F3A15_P_2 */
11327     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11328   },
11329   {
11330     /* VEX_W_0F3A18_P_2 */
11331     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11332   },
11333   {
11334     /* VEX_W_0F3A19_P_2 */
11335     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11336   },
11337   {
11338     /* VEX_W_0F3A20_P_2 */
11339     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11340   },
11341   {
11342     /* VEX_W_0F3A21_P_2 */
11343     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11344   },
11345   {
11346     /* VEX_W_0F3A30_P_2_LEN_0 */
11347     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11348     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11349   },
11350   {
11351     /* VEX_W_0F3A31_P_2_LEN_0 */
11352     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11353     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11354   },
11355   {
11356     /* VEX_W_0F3A32_P_2_LEN_0 */
11357     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11358     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11359   },
11360   {
11361     /* VEX_W_0F3A33_P_2_LEN_0 */
11362     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11363     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11364   },
11365   {
11366     /* VEX_W_0F3A38_P_2 */
11367     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11368   },
11369   {
11370     /* VEX_W_0F3A39_P_2 */
11371     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11372   },
11373   {
11374     /* VEX_W_0F3A40_P_2 */
11375     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11376   },
11377   {
11378     /* VEX_W_0F3A41_P_2 */
11379     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11380   },
11381   {
11382     /* VEX_W_0F3A42_P_2 */
11383     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11384   },
11385   {
11386     /* VEX_W_0F3A44_P_2 */
11387     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11388   },
11389   {
11390     /* VEX_W_0F3A46_P_2 */
11391     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11392   },
11393   {
11394     /* VEX_W_0F3A48_P_2 */
11395     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11396     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11397   },
11398   {
11399     /* VEX_W_0F3A49_P_2 */
11400     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11401     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11402   },
11403   {
11404     /* VEX_W_0F3A4A_P_2 */
11405     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11406   },
11407   {
11408     /* VEX_W_0F3A4B_P_2 */
11409     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11410   },
11411   {
11412     /* VEX_W_0F3A4C_P_2 */
11413     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11414   },
11415   {
11416     /* VEX_W_0F3A62_P_2 */
11417     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11418   },
11419   {
11420     /* VEX_W_0F3A63_P_2 */
11421     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11422   },
11423   {
11424     /* VEX_W_0F3ADF_P_2 */
11425     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11426   },
11427 #define NEED_VEX_W_TABLE
11428 #include "i386-dis-evex.h"
11429 #undef NEED_VEX_W_TABLE
11430 };
11431
11432 static const struct dis386 mod_table[][2] = {
11433   {
11434     /* MOD_8D */
11435     { "leaS",           { Gv, M }, 0 },
11436   },
11437   {
11438     /* MOD_C6_REG_7 */
11439     { Bad_Opcode },
11440     { RM_TABLE (RM_C6_REG_7) },
11441   },
11442   {
11443     /* MOD_C7_REG_7 */
11444     { Bad_Opcode },
11445     { RM_TABLE (RM_C7_REG_7) },
11446   },
11447   {
11448     /* MOD_FF_REG_3 */
11449     { "Jcall^", { indirEp }, 0 },
11450   },
11451   {
11452     /* MOD_FF_REG_5 */
11453     { "Jjmp^", { indirEp }, 0 },
11454   },
11455   {
11456     /* MOD_0F01_REG_0 */
11457     { X86_64_TABLE (X86_64_0F01_REG_0) },
11458     { RM_TABLE (RM_0F01_REG_0) },
11459   },
11460   {
11461     /* MOD_0F01_REG_1 */
11462     { X86_64_TABLE (X86_64_0F01_REG_1) },
11463     { RM_TABLE (RM_0F01_REG_1) },
11464   },
11465   {
11466     /* MOD_0F01_REG_2 */
11467     { X86_64_TABLE (X86_64_0F01_REG_2) },
11468     { RM_TABLE (RM_0F01_REG_2) },
11469   },
11470   {
11471     /* MOD_0F01_REG_3 */
11472     { X86_64_TABLE (X86_64_0F01_REG_3) },
11473     { RM_TABLE (RM_0F01_REG_3) },
11474   },
11475   {
11476     /* MOD_0F01_REG_5 */
11477     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11478     { RM_TABLE (RM_0F01_REG_5) },
11479   },
11480   {
11481     /* MOD_0F01_REG_7 */
11482     { "invlpg",         { Mb }, 0 },
11483     { RM_TABLE (RM_0F01_REG_7) },
11484   },
11485   {
11486     /* MOD_0F12_PREFIX_0 */
11487     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11488     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11489   },
11490   {
11491     /* MOD_0F13 */
11492     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11493   },
11494   {
11495     /* MOD_0F16_PREFIX_0 */
11496     { "movhps",         { XM, EXq }, 0 },
11497     { "movlhps",        { XM, EXq }, 0 },
11498   },
11499   {
11500     /* MOD_0F17 */
11501     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11502   },
11503   {
11504     /* MOD_0F18_REG_0 */
11505     { "prefetchnta",    { Mb }, 0 },
11506   },
11507   {
11508     /* MOD_0F18_REG_1 */
11509     { "prefetcht0",     { Mb }, 0 },
11510   },
11511   {
11512     /* MOD_0F18_REG_2 */
11513     { "prefetcht1",     { Mb }, 0 },
11514   },
11515   {
11516     /* MOD_0F18_REG_3 */
11517     { "prefetcht2",     { Mb }, 0 },
11518   },
11519   {
11520     /* MOD_0F18_REG_4 */
11521     { "nop/reserved",   { Mb }, 0 },
11522   },
11523   {
11524     /* MOD_0F18_REG_5 */
11525     { "nop/reserved",   { Mb }, 0 },
11526   },
11527   {
11528     /* MOD_0F18_REG_6 */
11529     { "nop/reserved",   { Mb }, 0 },
11530   },
11531   {
11532     /* MOD_0F18_REG_7 */
11533     { "nop/reserved",   { Mb }, 0 },
11534   },
11535   {
11536     /* MOD_0F1A_PREFIX_0 */
11537     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11538     { "nopQ",           { Ev }, 0 },
11539   },
11540   {
11541     /* MOD_0F1B_PREFIX_0 */
11542     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11543     { "nopQ",           { Ev }, 0 },
11544   },
11545   {
11546     /* MOD_0F1B_PREFIX_1 */
11547     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11548     { "nopQ",           { Ev }, 0 },
11549   },
11550   {
11551     /* MOD_0F1E_PREFIX_1 */
11552     { "nopQ",           { Ev }, 0 },
11553     { REG_TABLE (REG_0F1E_MOD_3) },
11554   },
11555   {
11556     /* MOD_0F24 */
11557     { Bad_Opcode },
11558     { "movL",           { Rd, Td }, 0 },
11559   },
11560   {
11561     /* MOD_0F26 */
11562     { Bad_Opcode },
11563     { "movL",           { Td, Rd }, 0 },
11564   },
11565   {
11566     /* MOD_0F2B_PREFIX_0 */
11567     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11568   },
11569   {
11570     /* MOD_0F2B_PREFIX_1 */
11571     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11572   },
11573   {
11574     /* MOD_0F2B_PREFIX_2 */
11575     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11576   },
11577   {
11578     /* MOD_0F2B_PREFIX_3 */
11579     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11580   },
11581   {
11582     /* MOD_0F51 */
11583     { Bad_Opcode },
11584     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11585   },
11586   {
11587     /* MOD_0F71_REG_2 */
11588     { Bad_Opcode },
11589     { "psrlw",          { MS, Ib }, 0 },
11590   },
11591   {
11592     /* MOD_0F71_REG_4 */
11593     { Bad_Opcode },
11594     { "psraw",          { MS, Ib }, 0 },
11595   },
11596   {
11597     /* MOD_0F71_REG_6 */
11598     { Bad_Opcode },
11599     { "psllw",          { MS, Ib }, 0 },
11600   },
11601   {
11602     /* MOD_0F72_REG_2 */
11603     { Bad_Opcode },
11604     { "psrld",          { MS, Ib }, 0 },
11605   },
11606   {
11607     /* MOD_0F72_REG_4 */
11608     { Bad_Opcode },
11609     { "psrad",          { MS, Ib }, 0 },
11610   },
11611   {
11612     /* MOD_0F72_REG_6 */
11613     { Bad_Opcode },
11614     { "pslld",          { MS, Ib }, 0 },
11615   },
11616   {
11617     /* MOD_0F73_REG_2 */
11618     { Bad_Opcode },
11619     { "psrlq",          { MS, Ib }, 0 },
11620   },
11621   {
11622     /* MOD_0F73_REG_3 */
11623     { Bad_Opcode },
11624     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11625   },
11626   {
11627     /* MOD_0F73_REG_6 */
11628     { Bad_Opcode },
11629     { "psllq",          { MS, Ib }, 0 },
11630   },
11631   {
11632     /* MOD_0F73_REG_7 */
11633     { Bad_Opcode },
11634     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11635   },
11636   {
11637     /* MOD_0FAE_REG_0 */
11638     { "fxsave",         { FXSAVE }, 0 },
11639     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11640   },
11641   {
11642     /* MOD_0FAE_REG_1 */
11643     { "fxrstor",        { FXSAVE }, 0 },
11644     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11645   },
11646   {
11647     /* MOD_0FAE_REG_2 */
11648     { "ldmxcsr",        { Md }, 0 },
11649     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11650   },
11651   {
11652     /* MOD_0FAE_REG_3 */
11653     { "stmxcsr",        { Md }, 0 },
11654     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11655   },
11656   {
11657     /* MOD_0FAE_REG_4 */
11658     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11659     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11660   },
11661   {
11662     /* MOD_0FAE_REG_5 */
11663     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11664     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11665   },
11666   {
11667     /* MOD_0FAE_REG_6 */
11668     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11669     { RM_TABLE (RM_0FAE_REG_6) },
11670   },
11671   {
11672     /* MOD_0FAE_REG_7 */
11673     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11674     { RM_TABLE (RM_0FAE_REG_7) },
11675   },
11676   {
11677     /* MOD_0FB2 */
11678     { "lssS",           { Gv, Mp }, 0 },
11679   },
11680   {
11681     /* MOD_0FB4 */
11682     { "lfsS",           { Gv, Mp }, 0 },
11683   },
11684   {
11685     /* MOD_0FB5 */
11686     { "lgsS",           { Gv, Mp }, 0 },
11687   },
11688   {
11689     /* MOD_0FC3 */
11690     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11691   },
11692   {
11693     /* MOD_0FC7_REG_3 */
11694     { "xrstors",        { FXSAVE }, 0 },
11695   },
11696   {
11697     /* MOD_0FC7_REG_4 */
11698     { "xsavec",         { FXSAVE }, 0 },
11699   },
11700   {
11701     /* MOD_0FC7_REG_5 */
11702     { "xsaves",         { FXSAVE }, 0 },
11703   },
11704   {
11705     /* MOD_0FC7_REG_6 */
11706     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11707     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11708   },
11709   {
11710     /* MOD_0FC7_REG_7 */
11711     { "vmptrst",        { Mq }, 0 },
11712     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11713   },
11714   {
11715     /* MOD_0FD7 */
11716     { Bad_Opcode },
11717     { "pmovmskb",       { Gdq, MS }, 0 },
11718   },
11719   {
11720     /* MOD_0FE7_PREFIX_2 */
11721     { "movntdq",        { Mx, XM }, 0 },
11722   },
11723   {
11724     /* MOD_0FF0_PREFIX_3 */
11725     { "lddqu",          { XM, M }, 0 },
11726   },
11727   {
11728     /* MOD_0F382A_PREFIX_2 */
11729     { "movntdqa",       { XM, Mx }, 0 },
11730   },
11731   {
11732     /* MOD_0F38F5_PREFIX_2 */
11733     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11734   },
11735   {
11736     /* MOD_0F38F6_PREFIX_0 */
11737     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11738   },
11739   {
11740     /* MOD_62_32BIT */
11741     { "bound{S|}",      { Gv, Ma }, 0 },
11742     { EVEX_TABLE (EVEX_0F) },
11743   },
11744   {
11745     /* MOD_C4_32BIT */
11746     { "lesS",           { Gv, Mp }, 0 },
11747     { VEX_C4_TABLE (VEX_0F) },
11748   },
11749   {
11750     /* MOD_C5_32BIT */
11751     { "ldsS",           { Gv, Mp }, 0 },
11752     { VEX_C5_TABLE (VEX_0F) },
11753   },
11754   {
11755     /* MOD_VEX_0F12_PREFIX_0 */
11756     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11757     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11758   },
11759   {
11760     /* MOD_VEX_0F13 */
11761     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11762   },
11763   {
11764     /* MOD_VEX_0F16_PREFIX_0 */
11765     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11766     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11767   },
11768   {
11769     /* MOD_VEX_0F17 */
11770     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11771   },
11772   {
11773     /* MOD_VEX_0F2B */
11774     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11775   },
11776   {
11777     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11778     { Bad_Opcode },
11779     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11780   },
11781   {
11782     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11783     { Bad_Opcode },
11784     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11785   },
11786   {
11787     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11788     { Bad_Opcode },
11789     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11790   },
11791   {
11792     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11793     { Bad_Opcode },
11794     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11795   },
11796   {
11797     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11798     { Bad_Opcode },
11799     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11800   },
11801   {
11802     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11803     { Bad_Opcode },
11804     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11805   },
11806   {
11807     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11808     { Bad_Opcode },
11809     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11810   },
11811   {
11812     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11813     { Bad_Opcode },
11814     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11815   },
11816   {
11817     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11818     { Bad_Opcode },
11819     { "knotw",          { MaskG, MaskR }, 0 },
11820   },
11821   {
11822     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11823     { Bad_Opcode },
11824     { "knotq",          { MaskG, MaskR }, 0 },
11825   },
11826   {
11827     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11828     { Bad_Opcode },
11829     { "knotb",          { MaskG, MaskR }, 0 },
11830   },
11831   {
11832     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11833     { Bad_Opcode },
11834     { "knotd",          { MaskG, MaskR }, 0 },
11835   },
11836   {
11837     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11838     { Bad_Opcode },
11839     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11840   },
11841   {
11842     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11843     { Bad_Opcode },
11844     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11845   },
11846   {
11847     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11848     { Bad_Opcode },
11849     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11850   },
11851   {
11852     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11853     { Bad_Opcode },
11854     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11855   },
11856  {
11857     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11858     { Bad_Opcode },
11859     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11860   },
11861   {
11862     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11863     { Bad_Opcode },
11864     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11865   },
11866   {
11867     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11868     { Bad_Opcode },
11869     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11870   },
11871   {
11872     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11873     { Bad_Opcode },
11874     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11875   },
11876   {
11877     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11878     { Bad_Opcode },
11879     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11880   },
11881   {
11882     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11883     { Bad_Opcode },
11884     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11885   },
11886   {
11887     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11888     { Bad_Opcode },
11889     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11890   },
11891   {
11892     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11893     { Bad_Opcode },
11894     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11895   },
11896   {
11897     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11898     { Bad_Opcode },
11899     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11900   },
11901   {
11902     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11903     { Bad_Opcode },
11904     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11905   },
11906   {
11907     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11908     { Bad_Opcode },
11909     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11910   },
11911   {
11912     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11913     { Bad_Opcode },
11914     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11915   },
11916   {
11917     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11918     { Bad_Opcode },
11919     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11920   },
11921   {
11922     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11923     { Bad_Opcode },
11924     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11925   },
11926   {
11927     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11928     { Bad_Opcode },
11929     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11930   },
11931   {
11932     /* MOD_VEX_0F50 */
11933     { Bad_Opcode },
11934     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11935   },
11936   {
11937     /* MOD_VEX_0F71_REG_2 */
11938     { Bad_Opcode },
11939     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11940   },
11941   {
11942     /* MOD_VEX_0F71_REG_4 */
11943     { Bad_Opcode },
11944     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11945   },
11946   {
11947     /* MOD_VEX_0F71_REG_6 */
11948     { Bad_Opcode },
11949     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11950   },
11951   {
11952     /* MOD_VEX_0F72_REG_2 */
11953     { Bad_Opcode },
11954     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11955   },
11956   {
11957     /* MOD_VEX_0F72_REG_4 */
11958     { Bad_Opcode },
11959     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11960   },
11961   {
11962     /* MOD_VEX_0F72_REG_6 */
11963     { Bad_Opcode },
11964     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11965   },
11966   {
11967     /* MOD_VEX_0F73_REG_2 */
11968     { Bad_Opcode },
11969     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11970   },
11971   {
11972     /* MOD_VEX_0F73_REG_3 */
11973     { Bad_Opcode },
11974     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11975   },
11976   {
11977     /* MOD_VEX_0F73_REG_6 */
11978     { Bad_Opcode },
11979     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11980   },
11981   {
11982     /* MOD_VEX_0F73_REG_7 */
11983     { Bad_Opcode },
11984     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11985   },
11986   {
11987     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11988     { "kmovw",          { Ew, MaskG }, 0 },
11989     { Bad_Opcode },
11990   },
11991   {
11992     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11993     { "kmovq",          { Eq, MaskG }, 0 },
11994     { Bad_Opcode },
11995   },
11996   {
11997     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11998     { "kmovb",          { Eb, MaskG }, 0 },
11999     { Bad_Opcode },
12000   },
12001   {
12002     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12003     { "kmovd",          { Ed, MaskG }, 0 },
12004     { Bad_Opcode },
12005   },
12006   {
12007     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12008     { Bad_Opcode },
12009     { "kmovw",          { MaskG, Rdq }, 0 },
12010   },
12011   {
12012     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12013     { Bad_Opcode },
12014     { "kmovb",          { MaskG, Rdq }, 0 },
12015   },
12016   {
12017     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12018     { Bad_Opcode },
12019     { "kmovd",          { MaskG, Rdq }, 0 },
12020   },
12021   {
12022     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12023     { Bad_Opcode },
12024     { "kmovq",          { MaskG, Rdq }, 0 },
12025   },
12026   {
12027     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12028     { Bad_Opcode },
12029     { "kmovw",          { Gdq, MaskR }, 0 },
12030   },
12031   {
12032     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12033     { Bad_Opcode },
12034     { "kmovb",          { Gdq, MaskR }, 0 },
12035   },
12036   {
12037     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12038     { Bad_Opcode },
12039     { "kmovd",          { Gdq, MaskR }, 0 },
12040   },
12041   {
12042     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12043     { Bad_Opcode },
12044     { "kmovq",          { Gdq, MaskR }, 0 },
12045   },
12046   {
12047     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12048     { Bad_Opcode },
12049     { "kortestw", { MaskG, MaskR }, 0 },
12050   },
12051   {
12052     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12053     { Bad_Opcode },
12054     { "kortestq", { MaskG, MaskR }, 0 },
12055   },
12056   {
12057     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12058     { Bad_Opcode },
12059     { "kortestb", { MaskG, MaskR }, 0 },
12060   },
12061   {
12062     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12063     { Bad_Opcode },
12064     { "kortestd", { MaskG, MaskR }, 0 },
12065   },
12066   {
12067     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12068     { Bad_Opcode },
12069     { "ktestw", { MaskG, MaskR }, 0 },
12070   },
12071   {
12072     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12073     { Bad_Opcode },
12074     { "ktestq", { MaskG, MaskR }, 0 },
12075   },
12076   {
12077     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12078     { Bad_Opcode },
12079     { "ktestb", { MaskG, MaskR }, 0 },
12080   },
12081   {
12082     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12083     { Bad_Opcode },
12084     { "ktestd", { MaskG, MaskR }, 0 },
12085   },
12086   {
12087     /* MOD_VEX_0FAE_REG_2 */
12088     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12089   },
12090   {
12091     /* MOD_VEX_0FAE_REG_3 */
12092     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12093   },
12094   {
12095     /* MOD_VEX_0FD7_PREFIX_2 */
12096     { Bad_Opcode },
12097     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12098   },
12099   {
12100     /* MOD_VEX_0FE7_PREFIX_2 */
12101     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12102   },
12103   {
12104     /* MOD_VEX_0FF0_PREFIX_3 */
12105     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12106   },
12107   {
12108     /* MOD_VEX_0F381A_PREFIX_2 */
12109     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12110   },
12111   {
12112     /* MOD_VEX_0F382A_PREFIX_2 */
12113     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12114   },
12115   {
12116     /* MOD_VEX_0F382C_PREFIX_2 */
12117     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12118   },
12119   {
12120     /* MOD_VEX_0F382D_PREFIX_2 */
12121     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12122   },
12123   {
12124     /* MOD_VEX_0F382E_PREFIX_2 */
12125     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12126   },
12127   {
12128     /* MOD_VEX_0F382F_PREFIX_2 */
12129     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12130   },
12131   {
12132     /* MOD_VEX_0F385A_PREFIX_2 */
12133     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12134   },
12135   {
12136     /* MOD_VEX_0F388C_PREFIX_2 */
12137     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12138   },
12139   {
12140     /* MOD_VEX_0F388E_PREFIX_2 */
12141     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12142   },
12143   {
12144     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12145     { Bad_Opcode },
12146     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12147   },
12148   {
12149     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12150     { Bad_Opcode },
12151     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12152   },
12153   {
12154     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12155     { Bad_Opcode },
12156     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12157   },
12158   {
12159     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12160     { Bad_Opcode },
12161     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12162   },
12163   {
12164     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12165     { Bad_Opcode },
12166     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12167   },
12168   {
12169     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12170     { Bad_Opcode },
12171     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12172   },
12173   {
12174     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12175     { Bad_Opcode },
12176     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12177   },
12178   {
12179     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12180     { Bad_Opcode },
12181     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12182   },
12183 #define NEED_MOD_TABLE
12184 #include "i386-dis-evex.h"
12185 #undef NEED_MOD_TABLE
12186 };
12187
12188 static const struct dis386 rm_table[][8] = {
12189   {
12190     /* RM_C6_REG_7 */
12191     { "xabort",         { Skip_MODRM, Ib }, 0 },
12192   },
12193   {
12194     /* RM_C7_REG_7 */
12195     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12196   },
12197   {
12198     /* RM_0F01_REG_0 */
12199     { Bad_Opcode },
12200     { "vmcall",         { Skip_MODRM }, 0 },
12201     { "vmlaunch",       { Skip_MODRM }, 0 },
12202     { "vmresume",       { Skip_MODRM }, 0 },
12203     { "vmxoff",         { Skip_MODRM }, 0 },
12204   },
12205   {
12206     /* RM_0F01_REG_1 */
12207     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12208     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12209     { "clac",           { Skip_MODRM }, 0 },
12210     { "stac",           { Skip_MODRM }, 0 },
12211     { Bad_Opcode },
12212     { Bad_Opcode },
12213     { Bad_Opcode },
12214     { "encls",          { Skip_MODRM }, 0 },
12215   },
12216   {
12217     /* RM_0F01_REG_2 */
12218     { "xgetbv",         { Skip_MODRM }, 0 },
12219     { "xsetbv",         { Skip_MODRM }, 0 },
12220     { Bad_Opcode },
12221     { Bad_Opcode },
12222     { "vmfunc",         { Skip_MODRM }, 0 },
12223     { "xend",           { Skip_MODRM }, 0 },
12224     { "xtest",          { Skip_MODRM }, 0 },
12225     { "enclu",          { Skip_MODRM }, 0 },
12226   },
12227   {
12228     /* RM_0F01_REG_3 */
12229     { "vmrun",          { Skip_MODRM }, 0 },
12230     { "vmmcall",        { Skip_MODRM }, 0 },
12231     { "vmload",         { Skip_MODRM }, 0 },
12232     { "vmsave",         { Skip_MODRM }, 0 },
12233     { "stgi",           { Skip_MODRM }, 0 },
12234     { "clgi",           { Skip_MODRM }, 0 },
12235     { "skinit",         { Skip_MODRM }, 0 },
12236     { "invlpga",        { Skip_MODRM }, 0 },
12237   },
12238   {
12239     /* RM_0F01_REG_5 */
12240     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12241     { Bad_Opcode },
12242     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12243     { Bad_Opcode },
12244     { Bad_Opcode },
12245     { Bad_Opcode },
12246     { "rdpkru",         { Skip_MODRM }, 0 },
12247     { "wrpkru",         { Skip_MODRM }, 0 },
12248   },
12249   {
12250     /* RM_0F01_REG_7 */
12251     { "swapgs",         { Skip_MODRM }, 0  },
12252     { "rdtscp",         { Skip_MODRM }, 0  },
12253     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12254     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12255     { "clzero",         { Skip_MODRM }, 0  },
12256   },
12257   {
12258     /* RM_0F1E_MOD_3_REG_7 */
12259     { "nopQ",           { Ev }, 0 },
12260     { "nopQ",           { Ev }, 0 },
12261     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
12262     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
12263     { "nopQ",           { Ev }, 0 },
12264     { "nopQ",           { Ev }, 0 },
12265     { "nopQ",           { Ev }, 0 },
12266     { "nopQ",           { Ev }, 0 },
12267   },
12268   {
12269     /* RM_0FAE_REG_6 */
12270     { "mfence",         { Skip_MODRM }, 0 },
12271   },
12272   {
12273     /* RM_0FAE_REG_7 */
12274     { "sfence",         { Skip_MODRM }, 0 },
12275
12276   },
12277 };
12278
12279 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12280
12281 /* We use the high bit to indicate different name for the same
12282    prefix.  */
12283 #define REP_PREFIX      (0xf3 | 0x100)
12284 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12285 #define XRELEASE_PREFIX (0xf3 | 0x400)
12286 #define BND_PREFIX      (0xf2 | 0x400)
12287 #define NOTRACK_PREFIX  (0x3e | 0x100)
12288
12289 static int
12290 ckprefix (void)
12291 {
12292   int newrex, i, length;
12293   rex = 0;
12294   rex_ignored = 0;
12295   prefixes = 0;
12296   used_prefixes = 0;
12297   rex_used = 0;
12298   last_lock_prefix = -1;
12299   last_repz_prefix = -1;
12300   last_repnz_prefix = -1;
12301   last_data_prefix = -1;
12302   last_addr_prefix = -1;
12303   last_rex_prefix = -1;
12304   last_seg_prefix = -1;
12305   fwait_prefix = -1;
12306   active_seg_prefix = 0;
12307   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12308     all_prefixes[i] = 0;
12309   i = 0;
12310   length = 0;
12311   /* The maximum instruction length is 15bytes.  */
12312   while (length < MAX_CODE_LENGTH - 1)
12313     {
12314       FETCH_DATA (the_info, codep + 1);
12315       newrex = 0;
12316       switch (*codep)
12317         {
12318         /* REX prefixes family.  */
12319         case 0x40:
12320         case 0x41:
12321         case 0x42:
12322         case 0x43:
12323         case 0x44:
12324         case 0x45:
12325         case 0x46:
12326         case 0x47:
12327         case 0x48:
12328         case 0x49:
12329         case 0x4a:
12330         case 0x4b:
12331         case 0x4c:
12332         case 0x4d:
12333         case 0x4e:
12334         case 0x4f:
12335           if (address_mode == mode_64bit)
12336             newrex = *codep;
12337           else
12338             return 1;
12339           last_rex_prefix = i;
12340           break;
12341         case 0xf3:
12342           prefixes |= PREFIX_REPZ;
12343           last_repz_prefix = i;
12344           break;
12345         case 0xf2:
12346           prefixes |= PREFIX_REPNZ;
12347           last_repnz_prefix = i;
12348           break;
12349         case 0xf0:
12350           prefixes |= PREFIX_LOCK;
12351           last_lock_prefix = i;
12352           break;
12353         case 0x2e:
12354           prefixes |= PREFIX_CS;
12355           last_seg_prefix = i;
12356           active_seg_prefix = PREFIX_CS;
12357           break;
12358         case 0x36:
12359           prefixes |= PREFIX_SS;
12360           last_seg_prefix = i;
12361           active_seg_prefix = PREFIX_SS;
12362           break;
12363         case 0x3e:
12364           prefixes |= PREFIX_DS;
12365           last_seg_prefix = i;
12366           active_seg_prefix = PREFIX_DS;
12367           break;
12368         case 0x26:
12369           prefixes |= PREFIX_ES;
12370           last_seg_prefix = i;
12371           active_seg_prefix = PREFIX_ES;
12372           break;
12373         case 0x64:
12374           prefixes |= PREFIX_FS;
12375           last_seg_prefix = i;
12376           active_seg_prefix = PREFIX_FS;
12377           break;
12378         case 0x65:
12379           prefixes |= PREFIX_GS;
12380           last_seg_prefix = i;
12381           active_seg_prefix = PREFIX_GS;
12382           break;
12383         case 0x66:
12384           prefixes |= PREFIX_DATA;
12385           last_data_prefix = i;
12386           break;
12387         case 0x67:
12388           prefixes |= PREFIX_ADDR;
12389           last_addr_prefix = i;
12390           break;
12391         case FWAIT_OPCODE:
12392           /* fwait is really an instruction.  If there are prefixes
12393              before the fwait, they belong to the fwait, *not* to the
12394              following instruction.  */
12395           fwait_prefix = i;
12396           if (prefixes || rex)
12397             {
12398               prefixes |= PREFIX_FWAIT;
12399               codep++;
12400               /* This ensures that the previous REX prefixes are noticed
12401                  as unused prefixes, as in the return case below.  */
12402               rex_used = rex;
12403               return 1;
12404             }
12405           prefixes = PREFIX_FWAIT;
12406           break;
12407         default:
12408           return 1;
12409         }
12410       /* Rex is ignored when followed by another prefix.  */
12411       if (rex)
12412         {
12413           rex_used = rex;
12414           return 1;
12415         }
12416       if (*codep != FWAIT_OPCODE)
12417         all_prefixes[i++] = *codep;
12418       rex = newrex;
12419       codep++;
12420       length++;
12421     }
12422   return 0;
12423 }
12424
12425 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12426    prefix byte.  */
12427
12428 static const char *
12429 prefix_name (int pref, int sizeflag)
12430 {
12431   static const char *rexes [16] =
12432     {
12433       "rex",            /* 0x40 */
12434       "rex.B",          /* 0x41 */
12435       "rex.X",          /* 0x42 */
12436       "rex.XB",         /* 0x43 */
12437       "rex.R",          /* 0x44 */
12438       "rex.RB",         /* 0x45 */
12439       "rex.RX",         /* 0x46 */
12440       "rex.RXB",        /* 0x47 */
12441       "rex.W",          /* 0x48 */
12442       "rex.WB",         /* 0x49 */
12443       "rex.WX",         /* 0x4a */
12444       "rex.WXB",        /* 0x4b */
12445       "rex.WR",         /* 0x4c */
12446       "rex.WRB",        /* 0x4d */
12447       "rex.WRX",        /* 0x4e */
12448       "rex.WRXB",       /* 0x4f */
12449     };
12450
12451   switch (pref)
12452     {
12453     /* REX prefixes family.  */
12454     case 0x40:
12455     case 0x41:
12456     case 0x42:
12457     case 0x43:
12458     case 0x44:
12459     case 0x45:
12460     case 0x46:
12461     case 0x47:
12462     case 0x48:
12463     case 0x49:
12464     case 0x4a:
12465     case 0x4b:
12466     case 0x4c:
12467     case 0x4d:
12468     case 0x4e:
12469     case 0x4f:
12470       return rexes [pref - 0x40];
12471     case 0xf3:
12472       return "repz";
12473     case 0xf2:
12474       return "repnz";
12475     case 0xf0:
12476       return "lock";
12477     case 0x2e:
12478       return "cs";
12479     case 0x36:
12480       return "ss";
12481     case 0x3e:
12482       return "ds";
12483     case 0x26:
12484       return "es";
12485     case 0x64:
12486       return "fs";
12487     case 0x65:
12488       return "gs";
12489     case 0x66:
12490       return (sizeflag & DFLAG) ? "data16" : "data32";
12491     case 0x67:
12492       if (address_mode == mode_64bit)
12493         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12494       else
12495         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12496     case FWAIT_OPCODE:
12497       return "fwait";
12498     case REP_PREFIX:
12499       return "rep";
12500     case XACQUIRE_PREFIX:
12501       return "xacquire";
12502     case XRELEASE_PREFIX:
12503       return "xrelease";
12504     case BND_PREFIX:
12505       return "bnd";
12506     case NOTRACK_PREFIX:
12507       return "notrack";
12508     default:
12509       return NULL;
12510     }
12511 }
12512
12513 static char op_out[MAX_OPERANDS][100];
12514 static int op_ad, op_index[MAX_OPERANDS];
12515 static int two_source_ops;
12516 static bfd_vma op_address[MAX_OPERANDS];
12517 static bfd_vma op_riprel[MAX_OPERANDS];
12518 static bfd_vma start_pc;
12519
12520 /*
12521  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12522  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12523  *   section of the "Virtual 8086 Mode" chapter.)
12524  * 'pc' should be the address of this instruction, it will
12525  *   be used to print the target address if this is a relative jump or call
12526  * The function returns the length of this instruction in bytes.
12527  */
12528
12529 static char intel_syntax;
12530 static char intel_mnemonic = !SYSV386_COMPAT;
12531 static char open_char;
12532 static char close_char;
12533 static char separator_char;
12534 static char scale_char;
12535
12536 enum x86_64_isa
12537 {
12538   amd64 = 0,
12539   intel64
12540 };
12541
12542 static enum x86_64_isa isa64;
12543
12544 /* Here for backwards compatibility.  When gdb stops using
12545    print_insn_i386_att and print_insn_i386_intel these functions can
12546    disappear, and print_insn_i386 be merged into print_insn.  */
12547 int
12548 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12549 {
12550   intel_syntax = 0;
12551
12552   return print_insn (pc, info);
12553 }
12554
12555 int
12556 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12557 {
12558   intel_syntax = 1;
12559
12560   return print_insn (pc, info);
12561 }
12562
12563 int
12564 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12565 {
12566   intel_syntax = -1;
12567
12568   return print_insn (pc, info);
12569 }
12570
12571 void
12572 print_i386_disassembler_options (FILE *stream)
12573 {
12574   fprintf (stream, _("\n\
12575 The following i386/x86-64 specific disassembler options are supported for use\n\
12576 with the -M switch (multiple options should be separated by commas):\n"));
12577
12578   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12579   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12580   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12581   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12582   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12583   fprintf (stream, _("  att-mnemonic\n"
12584                      "              Display instruction in AT&T mnemonic\n"));
12585   fprintf (stream, _("  intel-mnemonic\n"
12586                      "              Display instruction in Intel mnemonic\n"));
12587   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12588   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12589   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12590   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12591   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12592   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12593   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12594   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12595 }
12596
12597 /* Bad opcode.  */
12598 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12599
12600 /* Get a pointer to struct dis386 with a valid name.  */
12601
12602 static const struct dis386 *
12603 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12604 {
12605   int vindex, vex_table_index;
12606
12607   if (dp->name != NULL)
12608     return dp;
12609
12610   switch (dp->op[0].bytemode)
12611     {
12612     case USE_REG_TABLE:
12613       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12614       break;
12615
12616     case USE_MOD_TABLE:
12617       vindex = modrm.mod == 0x3 ? 1 : 0;
12618       dp = &mod_table[dp->op[1].bytemode][vindex];
12619       break;
12620
12621     case USE_RM_TABLE:
12622       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12623       break;
12624
12625     case USE_PREFIX_TABLE:
12626       if (need_vex)
12627         {
12628           /* The prefix in VEX is implicit.  */
12629           switch (vex.prefix)
12630             {
12631             case 0:
12632               vindex = 0;
12633               break;
12634             case REPE_PREFIX_OPCODE:
12635               vindex = 1;
12636               break;
12637             case DATA_PREFIX_OPCODE:
12638               vindex = 2;
12639               break;
12640             case REPNE_PREFIX_OPCODE:
12641               vindex = 3;
12642               break;
12643             default:
12644               abort ();
12645               break;
12646             }
12647         }
12648       else
12649         {
12650           int last_prefix = -1;
12651           int prefix = 0;
12652           vindex = 0;
12653           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12654              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12655              last one wins.  */
12656           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12657             {
12658               if (last_repz_prefix > last_repnz_prefix)
12659                 {
12660                   vindex = 1;
12661                   prefix = PREFIX_REPZ;
12662                   last_prefix = last_repz_prefix;
12663                 }
12664               else
12665                 {
12666                   vindex = 3;
12667                   prefix = PREFIX_REPNZ;
12668                   last_prefix = last_repnz_prefix;
12669                 }
12670
12671               /* Check if prefix should be ignored.  */
12672               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12673                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12674                    & prefix) != 0)
12675                 vindex = 0;
12676             }
12677
12678           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12679             {
12680               vindex = 2;
12681               prefix = PREFIX_DATA;
12682               last_prefix = last_data_prefix;
12683             }
12684
12685           if (vindex != 0)
12686             {
12687               used_prefixes |= prefix;
12688               all_prefixes[last_prefix] = 0;
12689             }
12690         }
12691       dp = &prefix_table[dp->op[1].bytemode][vindex];
12692       break;
12693
12694     case USE_X86_64_TABLE:
12695       vindex = address_mode == mode_64bit ? 1 : 0;
12696       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12697       break;
12698
12699     case USE_3BYTE_TABLE:
12700       FETCH_DATA (info, codep + 2);
12701       vindex = *codep++;
12702       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12703       end_codep = codep;
12704       modrm.mod = (*codep >> 6) & 3;
12705       modrm.reg = (*codep >> 3) & 7;
12706       modrm.rm = *codep & 7;
12707       break;
12708
12709     case USE_VEX_LEN_TABLE:
12710       if (!need_vex)
12711         abort ();
12712
12713       switch (vex.length)
12714         {
12715         case 128:
12716           vindex = 0;
12717           break;
12718         case 256:
12719           vindex = 1;
12720           break;
12721         default:
12722           abort ();
12723           break;
12724         }
12725
12726       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12727       break;
12728
12729     case USE_XOP_8F_TABLE:
12730       FETCH_DATA (info, codep + 3);
12731       /* All bits in the REX prefix are ignored.  */
12732       rex_ignored = rex;
12733       rex = ~(*codep >> 5) & 0x7;
12734
12735       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12736       switch ((*codep & 0x1f))
12737         {
12738         default:
12739           dp = &bad_opcode;
12740           return dp;
12741         case 0x8:
12742           vex_table_index = XOP_08;
12743           break;
12744         case 0x9:
12745           vex_table_index = XOP_09;
12746           break;
12747         case 0xa:
12748           vex_table_index = XOP_0A;
12749           break;
12750         }
12751       codep++;
12752       vex.w = *codep & 0x80;
12753       if (vex.w && address_mode == mode_64bit)
12754         rex |= REX_W;
12755
12756       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12757       if (address_mode != mode_64bit)
12758         {
12759           /* In 16/32-bit mode REX_B is silently ignored.  */
12760           rex &= ~REX_B;
12761           if (vex.register_specifier > 0x7)
12762             {
12763               dp = &bad_opcode;
12764               return dp;
12765             }
12766         }
12767
12768       vex.length = (*codep & 0x4) ? 256 : 128;
12769       switch ((*codep & 0x3))
12770         {
12771         case 0:
12772           vex.prefix = 0;
12773           break;
12774         case 1:
12775           vex.prefix = DATA_PREFIX_OPCODE;
12776           break;
12777         case 2:
12778           vex.prefix = REPE_PREFIX_OPCODE;
12779           break;
12780         case 3:
12781           vex.prefix = REPNE_PREFIX_OPCODE;
12782           break;
12783         }
12784       need_vex = 1;
12785       need_vex_reg = 1;
12786       codep++;
12787       vindex = *codep++;
12788       dp = &xop_table[vex_table_index][vindex];
12789
12790       end_codep = codep;
12791       FETCH_DATA (info, codep + 1);
12792       modrm.mod = (*codep >> 6) & 3;
12793       modrm.reg = (*codep >> 3) & 7;
12794       modrm.rm = *codep & 7;
12795       break;
12796
12797     case USE_VEX_C4_TABLE:
12798       /* VEX prefix.  */
12799       FETCH_DATA (info, codep + 3);
12800       /* All bits in the REX prefix are ignored.  */
12801       rex_ignored = rex;
12802       rex = ~(*codep >> 5) & 0x7;
12803       switch ((*codep & 0x1f))
12804         {
12805         default:
12806           dp = &bad_opcode;
12807           return dp;
12808         case 0x1:
12809           vex_table_index = VEX_0F;
12810           break;
12811         case 0x2:
12812           vex_table_index = VEX_0F38;
12813           break;
12814         case 0x3:
12815           vex_table_index = VEX_0F3A;
12816           break;
12817         }
12818       codep++;
12819       vex.w = *codep & 0x80;
12820       if (address_mode == mode_64bit)
12821         {
12822           if (vex.w)
12823             rex |= REX_W;
12824           vex.register_specifier = (~(*codep >> 3)) & 0xf;
12825         }
12826       else
12827         {
12828           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12829              is ignored, other REX bits are 0 and the highest bit in
12830              VEX.vvvv is also ignored.  */
12831           rex = 0;
12832           vex.register_specifier = (~(*codep >> 3)) & 0x7;
12833         }
12834       vex.length = (*codep & 0x4) ? 256 : 128;
12835       switch ((*codep & 0x3))
12836         {
12837         case 0:
12838           vex.prefix = 0;
12839           break;
12840         case 1:
12841           vex.prefix = DATA_PREFIX_OPCODE;
12842           break;
12843         case 2:
12844           vex.prefix = REPE_PREFIX_OPCODE;
12845           break;
12846         case 3:
12847           vex.prefix = REPNE_PREFIX_OPCODE;
12848           break;
12849         }
12850       need_vex = 1;
12851       need_vex_reg = 1;
12852       codep++;
12853       vindex = *codep++;
12854       dp = &vex_table[vex_table_index][vindex];
12855       end_codep = codep;
12856       /* There is no MODRM byte for VEX0F 77.  */
12857       if (vex_table_index != VEX_0F || vindex != 0x77)
12858         {
12859           FETCH_DATA (info, codep + 1);
12860           modrm.mod = (*codep >> 6) & 3;
12861           modrm.reg = (*codep >> 3) & 7;
12862           modrm.rm = *codep & 7;
12863         }
12864       break;
12865
12866     case USE_VEX_C5_TABLE:
12867       /* VEX prefix.  */
12868       FETCH_DATA (info, codep + 2);
12869       /* All bits in the REX prefix are ignored.  */
12870       rex_ignored = rex;
12871       rex = (*codep & 0x80) ? 0 : REX_R;
12872
12873       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12874          VEX.vvvv is 1.  */
12875       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12876       vex.w = 0;
12877       vex.length = (*codep & 0x4) ? 256 : 128;
12878       switch ((*codep & 0x3))
12879         {
12880         case 0:
12881           vex.prefix = 0;
12882           break;
12883         case 1:
12884           vex.prefix = DATA_PREFIX_OPCODE;
12885           break;
12886         case 2:
12887           vex.prefix = REPE_PREFIX_OPCODE;
12888           break;
12889         case 3:
12890           vex.prefix = REPNE_PREFIX_OPCODE;
12891           break;
12892         }
12893       need_vex = 1;
12894       need_vex_reg = 1;
12895       codep++;
12896       vindex = *codep++;
12897       dp = &vex_table[dp->op[1].bytemode][vindex];
12898       end_codep = codep;
12899       /* There is no MODRM byte for VEX 77.  */
12900       if (vindex != 0x77)
12901         {
12902           FETCH_DATA (info, codep + 1);
12903           modrm.mod = (*codep >> 6) & 3;
12904           modrm.reg = (*codep >> 3) & 7;
12905           modrm.rm = *codep & 7;
12906         }
12907       break;
12908
12909     case USE_VEX_W_TABLE:
12910       if (!need_vex)
12911         abort ();
12912
12913       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12914       break;
12915
12916     case USE_EVEX_TABLE:
12917       two_source_ops = 0;
12918       /* EVEX prefix.  */
12919       vex.evex = 1;
12920       FETCH_DATA (info, codep + 4);
12921       /* All bits in the REX prefix are ignored.  */
12922       rex_ignored = rex;
12923       /* The first byte after 0x62.  */
12924       rex = ~(*codep >> 5) & 0x7;
12925       vex.r = *codep & 0x10;
12926       switch ((*codep & 0xf))
12927         {
12928         default:
12929           return &bad_opcode;
12930         case 0x1:
12931           vex_table_index = EVEX_0F;
12932           break;
12933         case 0x2:
12934           vex_table_index = EVEX_0F38;
12935           break;
12936         case 0x3:
12937           vex_table_index = EVEX_0F3A;
12938           break;
12939         }
12940
12941       /* The second byte after 0x62.  */
12942       codep++;
12943       vex.w = *codep & 0x80;
12944       if (vex.w && address_mode == mode_64bit)
12945         rex |= REX_W;
12946
12947       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12948       if (address_mode != mode_64bit)
12949         {
12950           /* In 16/32-bit mode silently ignore following bits.  */
12951           rex &= ~REX_B;
12952           vex.r = 1;
12953           vex.v = 1;
12954           vex.register_specifier &= 0x7;
12955         }
12956
12957       /* The U bit.  */
12958       if (!(*codep & 0x4))
12959         return &bad_opcode;
12960
12961       switch ((*codep & 0x3))
12962         {
12963         case 0:
12964           vex.prefix = 0;
12965           break;
12966         case 1:
12967           vex.prefix = DATA_PREFIX_OPCODE;
12968           break;
12969         case 2:
12970           vex.prefix = REPE_PREFIX_OPCODE;
12971           break;
12972         case 3:
12973           vex.prefix = REPNE_PREFIX_OPCODE;
12974           break;
12975         }
12976
12977       /* The third byte after 0x62.  */
12978       codep++;
12979
12980       /* Remember the static rounding bits.  */
12981       vex.ll = (*codep >> 5) & 3;
12982       vex.b = (*codep & 0x10) != 0;
12983
12984       vex.v = *codep & 0x8;
12985       vex.mask_register_specifier = *codep & 0x7;
12986       vex.zeroing = *codep & 0x80;
12987
12988       need_vex = 1;
12989       need_vex_reg = 1;
12990       codep++;
12991       vindex = *codep++;
12992       dp = &evex_table[vex_table_index][vindex];
12993       end_codep = codep;
12994       FETCH_DATA (info, codep + 1);
12995       modrm.mod = (*codep >> 6) & 3;
12996       modrm.reg = (*codep >> 3) & 7;
12997       modrm.rm = *codep & 7;
12998
12999       /* Set vector length.  */
13000       if (modrm.mod == 3 && vex.b)
13001         vex.length = 512;
13002       else
13003         {
13004           switch (vex.ll)
13005             {
13006             case 0x0:
13007               vex.length = 128;
13008               break;
13009             case 0x1:
13010               vex.length = 256;
13011               break;
13012             case 0x2:
13013               vex.length = 512;
13014               break;
13015             default:
13016               return &bad_opcode;
13017             }
13018         }
13019       break;
13020
13021     case 0:
13022       dp = &bad_opcode;
13023       break;
13024
13025     default:
13026       abort ();
13027     }
13028
13029   if (dp->name != NULL)
13030     return dp;
13031   else
13032     return get_valid_dis386 (dp, info);
13033 }
13034
13035 static void
13036 get_sib (disassemble_info *info, int sizeflag)
13037 {
13038   /* If modrm.mod == 3, operand must be register.  */
13039   if (need_modrm
13040       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13041       && modrm.mod != 3
13042       && modrm.rm == 4)
13043     {
13044       FETCH_DATA (info, codep + 2);
13045       sib.index = (codep [1] >> 3) & 7;
13046       sib.scale = (codep [1] >> 6) & 3;
13047       sib.base = codep [1] & 7;
13048     }
13049 }
13050
13051 static int
13052 print_insn (bfd_vma pc, disassemble_info *info)
13053 {
13054   const struct dis386 *dp;
13055   int i;
13056   char *op_txt[MAX_OPERANDS];
13057   int needcomma;
13058   int sizeflag, orig_sizeflag;
13059   const char *p;
13060   struct dis_private priv;
13061   int prefix_length;
13062
13063   priv.orig_sizeflag = AFLAG | DFLAG;
13064   if ((info->mach & bfd_mach_i386_i386) != 0)
13065     address_mode = mode_32bit;
13066   else if (info->mach == bfd_mach_i386_i8086)
13067     {
13068       address_mode = mode_16bit;
13069       priv.orig_sizeflag = 0;
13070     }
13071   else
13072     address_mode = mode_64bit;
13073
13074   if (intel_syntax == (char) -1)
13075     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13076
13077   for (p = info->disassembler_options; p != NULL; )
13078     {
13079       if (CONST_STRNEQ (p, "amd64"))
13080         isa64 = amd64;
13081       else if (CONST_STRNEQ (p, "intel64"))
13082         isa64 = intel64;
13083       else if (CONST_STRNEQ (p, "x86-64"))
13084         {
13085           address_mode = mode_64bit;
13086           priv.orig_sizeflag = AFLAG | DFLAG;
13087         }
13088       else if (CONST_STRNEQ (p, "i386"))
13089         {
13090           address_mode = mode_32bit;
13091           priv.orig_sizeflag = AFLAG | DFLAG;
13092         }
13093       else if (CONST_STRNEQ (p, "i8086"))
13094         {
13095           address_mode = mode_16bit;
13096           priv.orig_sizeflag = 0;
13097         }
13098       else if (CONST_STRNEQ (p, "intel"))
13099         {
13100           intel_syntax = 1;
13101           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13102             intel_mnemonic = 1;
13103         }
13104       else if (CONST_STRNEQ (p, "att"))
13105         {
13106           intel_syntax = 0;
13107           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13108             intel_mnemonic = 0;
13109         }
13110       else if (CONST_STRNEQ (p, "addr"))
13111         {
13112           if (address_mode == mode_64bit)
13113             {
13114               if (p[4] == '3' && p[5] == '2')
13115                 priv.orig_sizeflag &= ~AFLAG;
13116               else if (p[4] == '6' && p[5] == '4')
13117                 priv.orig_sizeflag |= AFLAG;
13118             }
13119           else
13120             {
13121               if (p[4] == '1' && p[5] == '6')
13122                 priv.orig_sizeflag &= ~AFLAG;
13123               else if (p[4] == '3' && p[5] == '2')
13124                 priv.orig_sizeflag |= AFLAG;
13125             }
13126         }
13127       else if (CONST_STRNEQ (p, "data"))
13128         {
13129           if (p[4] == '1' && p[5] == '6')
13130             priv.orig_sizeflag &= ~DFLAG;
13131           else if (p[4] == '3' && p[5] == '2')
13132             priv.orig_sizeflag |= DFLAG;
13133         }
13134       else if (CONST_STRNEQ (p, "suffix"))
13135         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13136
13137       p = strchr (p, ',');
13138       if (p != NULL)
13139         p++;
13140     }
13141
13142   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13143     {
13144       (*info->fprintf_func) (info->stream,
13145                              _("64-bit address is disabled"));
13146       return -1;
13147     }
13148
13149   if (intel_syntax)
13150     {
13151       names64 = intel_names64;
13152       names32 = intel_names32;
13153       names16 = intel_names16;
13154       names8 = intel_names8;
13155       names8rex = intel_names8rex;
13156       names_seg = intel_names_seg;
13157       names_mm = intel_names_mm;
13158       names_bnd = intel_names_bnd;
13159       names_xmm = intel_names_xmm;
13160       names_ymm = intel_names_ymm;
13161       names_zmm = intel_names_zmm;
13162       index64 = intel_index64;
13163       index32 = intel_index32;
13164       names_mask = intel_names_mask;
13165       index16 = intel_index16;
13166       open_char = '[';
13167       close_char = ']';
13168       separator_char = '+';
13169       scale_char = '*';
13170     }
13171   else
13172     {
13173       names64 = att_names64;
13174       names32 = att_names32;
13175       names16 = att_names16;
13176       names8 = att_names8;
13177       names8rex = att_names8rex;
13178       names_seg = att_names_seg;
13179       names_mm = att_names_mm;
13180       names_bnd = att_names_bnd;
13181       names_xmm = att_names_xmm;
13182       names_ymm = att_names_ymm;
13183       names_zmm = att_names_zmm;
13184       index64 = att_index64;
13185       index32 = att_index32;
13186       names_mask = att_names_mask;
13187       index16 = att_index16;
13188       open_char = '(';
13189       close_char =  ')';
13190       separator_char = ',';
13191       scale_char = ',';
13192     }
13193
13194   /* The output looks better if we put 7 bytes on a line, since that
13195      puts most long word instructions on a single line.  Use 8 bytes
13196      for Intel L1OM.  */
13197   if ((info->mach & bfd_mach_l1om) != 0)
13198     info->bytes_per_line = 8;
13199   else
13200     info->bytes_per_line = 7;
13201
13202   info->private_data = &priv;
13203   priv.max_fetched = priv.the_buffer;
13204   priv.insn_start = pc;
13205
13206   obuf[0] = 0;
13207   for (i = 0; i < MAX_OPERANDS; ++i)
13208     {
13209       op_out[i][0] = 0;
13210       op_index[i] = -1;
13211     }
13212
13213   the_info = info;
13214   start_pc = pc;
13215   start_codep = priv.the_buffer;
13216   codep = priv.the_buffer;
13217
13218   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13219     {
13220       const char *name;
13221
13222       /* Getting here means we tried for data but didn't get it.  That
13223          means we have an incomplete instruction of some sort.  Just
13224          print the first byte as a prefix or a .byte pseudo-op.  */
13225       if (codep > priv.the_buffer)
13226         {
13227           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13228           if (name != NULL)
13229             (*info->fprintf_func) (info->stream, "%s", name);
13230           else
13231             {
13232               /* Just print the first byte as a .byte instruction.  */
13233               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13234                                      (unsigned int) priv.the_buffer[0]);
13235             }
13236
13237           return 1;
13238         }
13239
13240       return -1;
13241     }
13242
13243   obufp = obuf;
13244   sizeflag = priv.orig_sizeflag;
13245
13246   if (!ckprefix () || rex_used)
13247     {
13248       /* Too many prefixes or unused REX prefixes.  */
13249       for (i = 0;
13250            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13251            i++)
13252         (*info->fprintf_func) (info->stream, "%s%s",
13253                                i == 0 ? "" : " ",
13254                                prefix_name (all_prefixes[i], sizeflag));
13255       return i;
13256     }
13257
13258   insn_codep = codep;
13259
13260   FETCH_DATA (info, codep + 1);
13261   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13262
13263   if (((prefixes & PREFIX_FWAIT)
13264        && ((*codep < 0xd8) || (*codep > 0xdf))))
13265     {
13266       /* Handle prefixes before fwait.  */
13267       for (i = 0; i < fwait_prefix && all_prefixes[i];
13268            i++)
13269         (*info->fprintf_func) (info->stream, "%s ",
13270                                prefix_name (all_prefixes[i], sizeflag));
13271       (*info->fprintf_func) (info->stream, "fwait");
13272       return i + 1;
13273     }
13274
13275   if (*codep == 0x0f)
13276     {
13277       unsigned char threebyte;
13278
13279       codep++;
13280       FETCH_DATA (info, codep + 1);
13281       threebyte = *codep;
13282       dp = &dis386_twobyte[threebyte];
13283       need_modrm = twobyte_has_modrm[*codep];
13284       codep++;
13285     }
13286   else
13287     {
13288       dp = &dis386[*codep];
13289       need_modrm = onebyte_has_modrm[*codep];
13290       codep++;
13291     }
13292
13293   /* Save sizeflag for printing the extra prefixes later before updating
13294      it for mnemonic and operand processing.  The prefix names depend
13295      only on the address mode.  */
13296   orig_sizeflag = sizeflag;
13297   if (prefixes & PREFIX_ADDR)
13298     sizeflag ^= AFLAG;
13299   if ((prefixes & PREFIX_DATA))
13300     sizeflag ^= DFLAG;
13301
13302   end_codep = codep;
13303   if (need_modrm)
13304     {
13305       FETCH_DATA (info, codep + 1);
13306       modrm.mod = (*codep >> 6) & 3;
13307       modrm.reg = (*codep >> 3) & 7;
13308       modrm.rm = *codep & 7;
13309     }
13310
13311   need_vex = 0;
13312   need_vex_reg = 0;
13313   vex_w_done = 0;
13314   vex.evex = 0;
13315
13316   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13317     {
13318       get_sib (info, sizeflag);
13319       dofloat (sizeflag);
13320     }
13321   else
13322     {
13323       dp = get_valid_dis386 (dp, info);
13324       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13325         {
13326           get_sib (info, sizeflag);
13327           for (i = 0; i < MAX_OPERANDS; ++i)
13328             {
13329               obufp = op_out[i];
13330               op_ad = MAX_OPERANDS - 1 - i;
13331               if (dp->op[i].rtn)
13332                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13333               /* For EVEX instruction after the last operand masking
13334                  should be printed.  */
13335               if (i == 0 && vex.evex)
13336                 {
13337                   /* Don't print {%k0}.  */
13338                   if (vex.mask_register_specifier)
13339                     {
13340                       oappend ("{");
13341                       oappend (names_mask[vex.mask_register_specifier]);
13342                       oappend ("}");
13343                     }
13344                   if (vex.zeroing)
13345                     oappend ("{z}");
13346                 }
13347             }
13348         }
13349     }
13350
13351   /* Check if the REX prefix is used.  */
13352   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13353     all_prefixes[last_rex_prefix] = 0;
13354
13355   /* Check if the SEG prefix is used.  */
13356   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13357                    | PREFIX_FS | PREFIX_GS)) != 0
13358       && (used_prefixes & active_seg_prefix) != 0)
13359     all_prefixes[last_seg_prefix] = 0;
13360
13361   /* Check if the ADDR prefix is used.  */
13362   if ((prefixes & PREFIX_ADDR) != 0
13363       && (used_prefixes & PREFIX_ADDR) != 0)
13364     all_prefixes[last_addr_prefix] = 0;
13365
13366   /* Check if the DATA prefix is used.  */
13367   if ((prefixes & PREFIX_DATA) != 0
13368       && (used_prefixes & PREFIX_DATA) != 0)
13369     all_prefixes[last_data_prefix] = 0;
13370
13371   /* Print the extra prefixes.  */
13372   prefix_length = 0;
13373   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13374     if (all_prefixes[i])
13375       {
13376         const char *name;
13377         name = prefix_name (all_prefixes[i], orig_sizeflag);
13378         if (name == NULL)
13379           abort ();
13380         prefix_length += strlen (name) + 1;
13381         (*info->fprintf_func) (info->stream, "%s ", name);
13382       }
13383
13384   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13385      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13386      used by putop and MMX/SSE operand and may be overriden by the
13387      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13388      separately.  */
13389   if (dp->prefix_requirement == PREFIX_OPCODE
13390       && dp != &bad_opcode
13391       && (((prefixes
13392             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13393            && (used_prefixes
13394                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13395           || ((((prefixes
13396                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13397                 == PREFIX_DATA)
13398                && (used_prefixes & PREFIX_DATA) == 0))))
13399     {
13400       (*info->fprintf_func) (info->stream, "(bad)");
13401       return end_codep - priv.the_buffer;
13402     }
13403
13404   /* Check maximum code length.  */
13405   if ((codep - start_codep) > MAX_CODE_LENGTH)
13406     {
13407       (*info->fprintf_func) (info->stream, "(bad)");
13408       return MAX_CODE_LENGTH;
13409     }
13410
13411   obufp = mnemonicendp;
13412   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13413     oappend (" ");
13414   oappend (" ");
13415   (*info->fprintf_func) (info->stream, "%s", obuf);
13416
13417   /* The enter and bound instructions are printed with operands in the same
13418      order as the intel book; everything else is printed in reverse order.  */
13419   if (intel_syntax || two_source_ops)
13420     {
13421       bfd_vma riprel;
13422
13423       for (i = 0; i < MAX_OPERANDS; ++i)
13424         op_txt[i] = op_out[i];
13425
13426       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13427           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13428         {
13429           op_txt[2] = op_out[3];
13430           op_txt[3] = op_out[2];
13431         }
13432
13433       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13434         {
13435           op_ad = op_index[i];
13436           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13437           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13438           riprel = op_riprel[i];
13439           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13440           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13441         }
13442     }
13443   else
13444     {
13445       for (i = 0; i < MAX_OPERANDS; ++i)
13446         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13447     }
13448
13449   needcomma = 0;
13450   for (i = 0; i < MAX_OPERANDS; ++i)
13451     if (*op_txt[i])
13452       {
13453         if (needcomma)
13454           (*info->fprintf_func) (info->stream, ",");
13455         if (op_index[i] != -1 && !op_riprel[i])
13456           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13457         else
13458           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13459         needcomma = 1;
13460       }
13461
13462   for (i = 0; i < MAX_OPERANDS; i++)
13463     if (op_index[i] != -1 && op_riprel[i])
13464       {
13465         (*info->fprintf_func) (info->stream, "        # ");
13466         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13467                                                 + op_address[op_index[i]]), info);
13468         break;
13469       }
13470   return codep - priv.the_buffer;
13471 }
13472
13473 static const char *float_mem[] = {
13474   /* d8 */
13475   "fadd{s|}",
13476   "fmul{s|}",
13477   "fcom{s|}",
13478   "fcomp{s|}",
13479   "fsub{s|}",
13480   "fsubr{s|}",
13481   "fdiv{s|}",
13482   "fdivr{s|}",
13483   /* d9 */
13484   "fld{s|}",
13485   "(bad)",
13486   "fst{s|}",
13487   "fstp{s|}",
13488   "fldenvIC",
13489   "fldcw",
13490   "fNstenvIC",
13491   "fNstcw",
13492   /* da */
13493   "fiadd{l|}",
13494   "fimul{l|}",
13495   "ficom{l|}",
13496   "ficomp{l|}",
13497   "fisub{l|}",
13498   "fisubr{l|}",
13499   "fidiv{l|}",
13500   "fidivr{l|}",
13501   /* db */
13502   "fild{l|}",
13503   "fisttp{l|}",
13504   "fist{l|}",
13505   "fistp{l|}",
13506   "(bad)",
13507   "fld{t||t|}",
13508   "(bad)",
13509   "fstp{t||t|}",
13510   /* dc */
13511   "fadd{l|}",
13512   "fmul{l|}",
13513   "fcom{l|}",
13514   "fcomp{l|}",
13515   "fsub{l|}",
13516   "fsubr{l|}",
13517   "fdiv{l|}",
13518   "fdivr{l|}",
13519   /* dd */
13520   "fld{l|}",
13521   "fisttp{ll|}",
13522   "fst{l||}",
13523   "fstp{l|}",
13524   "frstorIC",
13525   "(bad)",
13526   "fNsaveIC",
13527   "fNstsw",
13528   /* de */
13529   "fiadd",
13530   "fimul",
13531   "ficom",
13532   "ficomp",
13533   "fisub",
13534   "fisubr",
13535   "fidiv",
13536   "fidivr",
13537   /* df */
13538   "fild",
13539   "fisttp",
13540   "fist",
13541   "fistp",
13542   "fbld",
13543   "fild{ll|}",
13544   "fbstp",
13545   "fistp{ll|}",
13546 };
13547
13548 static const unsigned char float_mem_mode[] = {
13549   /* d8 */
13550   d_mode,
13551   d_mode,
13552   d_mode,
13553   d_mode,
13554   d_mode,
13555   d_mode,
13556   d_mode,
13557   d_mode,
13558   /* d9 */
13559   d_mode,
13560   0,
13561   d_mode,
13562   d_mode,
13563   0,
13564   w_mode,
13565   0,
13566   w_mode,
13567   /* da */
13568   d_mode,
13569   d_mode,
13570   d_mode,
13571   d_mode,
13572   d_mode,
13573   d_mode,
13574   d_mode,
13575   d_mode,
13576   /* db */
13577   d_mode,
13578   d_mode,
13579   d_mode,
13580   d_mode,
13581   0,
13582   t_mode,
13583   0,
13584   t_mode,
13585   /* dc */
13586   q_mode,
13587   q_mode,
13588   q_mode,
13589   q_mode,
13590   q_mode,
13591   q_mode,
13592   q_mode,
13593   q_mode,
13594   /* dd */
13595   q_mode,
13596   q_mode,
13597   q_mode,
13598   q_mode,
13599   0,
13600   0,
13601   0,
13602   w_mode,
13603   /* de */
13604   w_mode,
13605   w_mode,
13606   w_mode,
13607   w_mode,
13608   w_mode,
13609   w_mode,
13610   w_mode,
13611   w_mode,
13612   /* df */
13613   w_mode,
13614   w_mode,
13615   w_mode,
13616   w_mode,
13617   t_mode,
13618   q_mode,
13619   t_mode,
13620   q_mode
13621 };
13622
13623 #define ST { OP_ST, 0 }
13624 #define STi { OP_STi, 0 }
13625
13626 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13627 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13628 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13629 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13630 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13631 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13632 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13633 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13634 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13635
13636 static const struct dis386 float_reg[][8] = {
13637   /* d8 */
13638   {
13639     { "fadd",   { ST, STi }, 0 },
13640     { "fmul",   { ST, STi }, 0 },
13641     { "fcom",   { STi }, 0 },
13642     { "fcomp",  { STi }, 0 },
13643     { "fsub",   { ST, STi }, 0 },
13644     { "fsubr",  { ST, STi }, 0 },
13645     { "fdiv",   { ST, STi }, 0 },
13646     { "fdivr",  { ST, STi }, 0 },
13647   },
13648   /* d9 */
13649   {
13650     { "fld",    { STi }, 0 },
13651     { "fxch",   { STi }, 0 },
13652     { FGRPd9_2 },
13653     { Bad_Opcode },
13654     { FGRPd9_4 },
13655     { FGRPd9_5 },
13656     { FGRPd9_6 },
13657     { FGRPd9_7 },
13658   },
13659   /* da */
13660   {
13661     { "fcmovb", { ST, STi }, 0 },
13662     { "fcmove", { ST, STi }, 0 },
13663     { "fcmovbe",{ ST, STi }, 0 },
13664     { "fcmovu", { ST, STi }, 0 },
13665     { Bad_Opcode },
13666     { FGRPda_5 },
13667     { Bad_Opcode },
13668     { Bad_Opcode },
13669   },
13670   /* db */
13671   {
13672     { "fcmovnb",{ ST, STi }, 0 },
13673     { "fcmovne",{ ST, STi }, 0 },
13674     { "fcmovnbe",{ ST, STi }, 0 },
13675     { "fcmovnu",{ ST, STi }, 0 },
13676     { FGRPdb_4 },
13677     { "fucomi", { ST, STi }, 0 },
13678     { "fcomi",  { ST, STi }, 0 },
13679     { Bad_Opcode },
13680   },
13681   /* dc */
13682   {
13683     { "fadd",   { STi, ST }, 0 },
13684     { "fmul",   { STi, ST }, 0 },
13685     { Bad_Opcode },
13686     { Bad_Opcode },
13687     { "fsub!M", { STi, ST }, 0 },
13688     { "fsubM",  { STi, ST }, 0 },
13689     { "fdiv!M", { STi, ST }, 0 },
13690     { "fdivM",  { STi, ST }, 0 },
13691   },
13692   /* dd */
13693   {
13694     { "ffree",  { STi }, 0 },
13695     { Bad_Opcode },
13696     { "fst",    { STi }, 0 },
13697     { "fstp",   { STi }, 0 },
13698     { "fucom",  { STi }, 0 },
13699     { "fucomp", { STi }, 0 },
13700     { Bad_Opcode },
13701     { Bad_Opcode },
13702   },
13703   /* de */
13704   {
13705     { "faddp",  { STi, ST }, 0 },
13706     { "fmulp",  { STi, ST }, 0 },
13707     { Bad_Opcode },
13708     { FGRPde_3 },
13709     { "fsub!Mp", { STi, ST }, 0 },
13710     { "fsubMp", { STi, ST }, 0 },
13711     { "fdiv!Mp", { STi, ST }, 0 },
13712     { "fdivMp", { STi, ST }, 0 },
13713   },
13714   /* df */
13715   {
13716     { "ffreep", { STi }, 0 },
13717     { Bad_Opcode },
13718     { Bad_Opcode },
13719     { Bad_Opcode },
13720     { FGRPdf_4 },
13721     { "fucomip", { ST, STi }, 0 },
13722     { "fcomip", { ST, STi }, 0 },
13723     { Bad_Opcode },
13724   },
13725 };
13726
13727 static char *fgrps[][8] = {
13728   /* Bad opcode 0 */
13729   {
13730     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13731   },
13732
13733   /* d9_2  1 */
13734   {
13735     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13736   },
13737
13738   /* d9_4  2 */
13739   {
13740     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13741   },
13742
13743   /* d9_5  3 */
13744   {
13745     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13746   },
13747
13748   /* d9_6  4 */
13749   {
13750     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13751   },
13752
13753   /* d9_7  5 */
13754   {
13755     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13756   },
13757
13758   /* da_5  6 */
13759   {
13760     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13761   },
13762
13763   /* db_4  7 */
13764   {
13765     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13766     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13767   },
13768
13769   /* de_3  8 */
13770   {
13771     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13772   },
13773
13774   /* df_4  9 */
13775   {
13776     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13777   },
13778 };
13779
13780 static void
13781 swap_operand (void)
13782 {
13783   mnemonicendp[0] = '.';
13784   mnemonicendp[1] = 's';
13785   mnemonicendp += 2;
13786 }
13787
13788 static void
13789 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13790                int sizeflag ATTRIBUTE_UNUSED)
13791 {
13792   /* Skip mod/rm byte.  */
13793   MODRM_CHECK;
13794   codep++;
13795 }
13796
13797 static void
13798 dofloat (int sizeflag)
13799 {
13800   const struct dis386 *dp;
13801   unsigned char floatop;
13802
13803   floatop = codep[-1];
13804
13805   if (modrm.mod != 3)
13806     {
13807       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13808
13809       putop (float_mem[fp_indx], sizeflag);
13810       obufp = op_out[0];
13811       op_ad = 2;
13812       OP_E (float_mem_mode[fp_indx], sizeflag);
13813       return;
13814     }
13815   /* Skip mod/rm byte.  */
13816   MODRM_CHECK;
13817   codep++;
13818
13819   dp = &float_reg[floatop - 0xd8][modrm.reg];
13820   if (dp->name == NULL)
13821     {
13822       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13823
13824       /* Instruction fnstsw is only one with strange arg.  */
13825       if (floatop == 0xdf && codep[-1] == 0xe0)
13826         strcpy (op_out[0], names16[0]);
13827     }
13828   else
13829     {
13830       putop (dp->name, sizeflag);
13831
13832       obufp = op_out[0];
13833       op_ad = 2;
13834       if (dp->op[0].rtn)
13835         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13836
13837       obufp = op_out[1];
13838       op_ad = 1;
13839       if (dp->op[1].rtn)
13840         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13841     }
13842 }
13843
13844 /* Like oappend (below), but S is a string starting with '%'.
13845    In Intel syntax, the '%' is elided.  */
13846 static void
13847 oappend_maybe_intel (const char *s)
13848 {
13849   oappend (s + intel_syntax);
13850 }
13851
13852 static void
13853 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13854 {
13855   oappend_maybe_intel ("%st");
13856 }
13857
13858 static void
13859 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13860 {
13861   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13862   oappend_maybe_intel (scratchbuf);
13863 }
13864
13865 /* Capital letters in template are macros.  */
13866 static int
13867 putop (const char *in_template, int sizeflag)
13868 {
13869   const char *p;
13870   int alt = 0;
13871   int cond = 1;
13872   unsigned int l = 0, len = 1;
13873   char last[4];
13874
13875 #define SAVE_LAST(c)                    \
13876   if (l < len && l < sizeof (last))     \
13877     last[l++] = c;                      \
13878   else                                  \
13879     abort ();
13880
13881   for (p = in_template; *p; p++)
13882     {
13883       switch (*p)
13884         {
13885         default:
13886           *obufp++ = *p;
13887           break;
13888         case '%':
13889           len++;
13890           break;
13891         case '!':
13892           cond = 0;
13893           break;
13894         case '{':
13895           if (intel_syntax)
13896             {
13897               while (*++p != '|')
13898                 if (*p == '}' || *p == '\0')
13899                   abort ();
13900             }
13901           /* Fall through.  */
13902         case 'I':
13903           alt = 1;
13904           continue;
13905         case '|':
13906           while (*++p != '}')
13907             {
13908               if (*p == '\0')
13909                 abort ();
13910             }
13911           break;
13912         case '}':
13913           break;
13914         case 'A':
13915           if (intel_syntax)
13916             break;
13917           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13918             *obufp++ = 'b';
13919           break;
13920         case 'B':
13921           if (l == 0 && len == 1)
13922             {
13923 case_B:
13924               if (intel_syntax)
13925                 break;
13926               if (sizeflag & SUFFIX_ALWAYS)
13927                 *obufp++ = 'b';
13928             }
13929           else
13930             {
13931               if (l != 1
13932                   || len != 2
13933                   || last[0] != 'L')
13934                 {
13935                   SAVE_LAST (*p);
13936                   break;
13937                 }
13938
13939               if (address_mode == mode_64bit
13940                   && !(prefixes & PREFIX_ADDR))
13941                 {
13942                   *obufp++ = 'a';
13943                   *obufp++ = 'b';
13944                   *obufp++ = 's';
13945                 }
13946
13947               goto case_B;
13948             }
13949           break;
13950         case 'C':
13951           if (intel_syntax && !alt)
13952             break;
13953           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13954             {
13955               if (sizeflag & DFLAG)
13956                 *obufp++ = intel_syntax ? 'd' : 'l';
13957               else
13958                 *obufp++ = intel_syntax ? 'w' : 's';
13959               used_prefixes |= (prefixes & PREFIX_DATA);
13960             }
13961           break;
13962         case 'D':
13963           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13964             break;
13965           USED_REX (REX_W);
13966           if (modrm.mod == 3)
13967             {
13968               if (rex & REX_W)
13969                 *obufp++ = 'q';
13970               else
13971                 {
13972                   if (sizeflag & DFLAG)
13973                     *obufp++ = intel_syntax ? 'd' : 'l';
13974                   else
13975                     *obufp++ = 'w';
13976                   used_prefixes |= (prefixes & PREFIX_DATA);
13977                 }
13978             }
13979           else
13980             *obufp++ = 'w';
13981           break;
13982         case 'E':               /* For jcxz/jecxz */
13983           if (address_mode == mode_64bit)
13984             {
13985               if (sizeflag & AFLAG)
13986                 *obufp++ = 'r';
13987               else
13988                 *obufp++ = 'e';
13989             }
13990           else
13991             if (sizeflag & AFLAG)
13992               *obufp++ = 'e';
13993           used_prefixes |= (prefixes & PREFIX_ADDR);
13994           break;
13995         case 'F':
13996           if (intel_syntax)
13997             break;
13998           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13999             {
14000               if (sizeflag & AFLAG)
14001                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14002               else
14003                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14004               used_prefixes |= (prefixes & PREFIX_ADDR);
14005             }
14006           break;
14007         case 'G':
14008           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14009             break;
14010           if ((rex & REX_W) || (sizeflag & DFLAG))
14011             *obufp++ = 'l';
14012           else
14013             *obufp++ = 'w';
14014           if (!(rex & REX_W))
14015             used_prefixes |= (prefixes & PREFIX_DATA);
14016           break;
14017         case 'H':
14018           if (intel_syntax)
14019             break;
14020           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14021               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14022             {
14023               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14024               *obufp++ = ',';
14025               *obufp++ = 'p';
14026               if (prefixes & PREFIX_DS)
14027                 *obufp++ = 't';
14028               else
14029                 *obufp++ = 'n';
14030             }
14031           break;
14032         case 'J':
14033           if (intel_syntax)
14034             break;
14035           *obufp++ = 'l';
14036           break;
14037         case 'K':
14038           USED_REX (REX_W);
14039           if (rex & REX_W)
14040             *obufp++ = 'q';
14041           else
14042             *obufp++ = 'd';
14043           break;
14044         case 'Z':
14045           if (l != 0 || len != 1)
14046             {
14047               if (l != 1 || len != 2 || last[0] != 'X')
14048                 {
14049                   SAVE_LAST (*p);
14050                   break;
14051                 }
14052               if (!need_vex || !vex.evex)
14053                 abort ();
14054               if (intel_syntax
14055                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14056                 break;
14057               switch (vex.length)
14058                 {
14059                 case 128:
14060                   *obufp++ = 'x';
14061                   break;
14062                 case 256:
14063                   *obufp++ = 'y';
14064                   break;
14065                 case 512:
14066                   *obufp++ = 'z';
14067                   break;
14068                 default:
14069                   abort ();
14070                 }
14071               break;
14072             }
14073           if (intel_syntax)
14074             break;
14075           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14076             {
14077               *obufp++ = 'q';
14078               break;
14079             }
14080           /* Fall through.  */
14081           goto case_L;
14082         case 'L':
14083           if (l != 0 || len != 1)
14084             {
14085               SAVE_LAST (*p);
14086               break;
14087             }
14088 case_L:
14089           if (intel_syntax)
14090             break;
14091           if (sizeflag & SUFFIX_ALWAYS)
14092             *obufp++ = 'l';
14093           break;
14094         case 'M':
14095           if (intel_mnemonic != cond)
14096             *obufp++ = 'r';
14097           break;
14098         case 'N':
14099           if ((prefixes & PREFIX_FWAIT) == 0)
14100             *obufp++ = 'n';
14101           else
14102             used_prefixes |= PREFIX_FWAIT;
14103           break;
14104         case 'O':
14105           USED_REX (REX_W);
14106           if (rex & REX_W)
14107             *obufp++ = 'o';
14108           else if (intel_syntax && (sizeflag & DFLAG))
14109             *obufp++ = 'q';
14110           else
14111             *obufp++ = 'd';
14112           if (!(rex & REX_W))
14113             used_prefixes |= (prefixes & PREFIX_DATA);
14114           break;
14115         case '&':
14116           if (!intel_syntax
14117               && address_mode == mode_64bit
14118               && isa64 == intel64)
14119             {
14120               *obufp++ = 'q';
14121               break;
14122             }
14123           /* Fall through.  */
14124         case 'T':
14125           if (!intel_syntax
14126               && address_mode == mode_64bit
14127               && ((sizeflag & DFLAG) || (rex & REX_W)))
14128             {
14129               *obufp++ = 'q';
14130               break;
14131             }
14132           /* Fall through.  */
14133           goto case_P;
14134         case 'P':
14135           if (l == 0 && len == 1)
14136             {
14137 case_P:
14138               if (intel_syntax)
14139                 {
14140                   if ((rex & REX_W) == 0
14141                       && (prefixes & PREFIX_DATA))
14142                     {
14143                       if ((sizeflag & DFLAG) == 0)
14144                         *obufp++ = 'w';
14145                       used_prefixes |= (prefixes & PREFIX_DATA);
14146                     }
14147                   break;
14148                 }
14149               if ((prefixes & PREFIX_DATA)
14150                   || (rex & REX_W)
14151                   || (sizeflag & SUFFIX_ALWAYS))
14152                 {
14153                   USED_REX (REX_W);
14154                   if (rex & REX_W)
14155                     *obufp++ = 'q';
14156                   else
14157                     {
14158                       if (sizeflag & DFLAG)
14159                         *obufp++ = 'l';
14160                       else
14161                         *obufp++ = 'w';
14162                       used_prefixes |= (prefixes & PREFIX_DATA);
14163                     }
14164                 }
14165             }
14166           else
14167             {
14168               if (l != 1 || len != 2 || last[0] != 'L')
14169                 {
14170                   SAVE_LAST (*p);
14171                   break;
14172                 }
14173
14174               if ((prefixes & PREFIX_DATA)
14175                   || (rex & REX_W)
14176                   || (sizeflag & SUFFIX_ALWAYS))
14177                 {
14178                   USED_REX (REX_W);
14179                   if (rex & REX_W)
14180                     *obufp++ = 'q';
14181                   else
14182                     {
14183                       if (sizeflag & DFLAG)
14184                         *obufp++ = intel_syntax ? 'd' : 'l';
14185                       else
14186                         *obufp++ = 'w';
14187                       used_prefixes |= (prefixes & PREFIX_DATA);
14188                     }
14189                 }
14190             }
14191           break;
14192         case 'U':
14193           if (intel_syntax)
14194             break;
14195           if (address_mode == mode_64bit
14196               && ((sizeflag & DFLAG) || (rex & REX_W)))
14197             {
14198               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14199                 *obufp++ = 'q';
14200               break;
14201             }
14202           /* Fall through.  */
14203           goto case_Q;
14204         case 'Q':
14205           if (l == 0 && len == 1)
14206             {
14207 case_Q:
14208               if (intel_syntax && !alt)
14209                 break;
14210               USED_REX (REX_W);
14211               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14212                 {
14213                   if (rex & REX_W)
14214                     *obufp++ = 'q';
14215                   else
14216                     {
14217                       if (sizeflag & DFLAG)
14218                         *obufp++ = intel_syntax ? 'd' : 'l';
14219                       else
14220                         *obufp++ = 'w';
14221                       used_prefixes |= (prefixes & PREFIX_DATA);
14222                     }
14223                 }
14224             }
14225           else
14226             {
14227               if (l != 1 || len != 2 || last[0] != 'L')
14228                 {
14229                   SAVE_LAST (*p);
14230                   break;
14231                 }
14232               if (intel_syntax
14233                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14234                 break;
14235               if ((rex & REX_W))
14236                 {
14237                   USED_REX (REX_W);
14238                   *obufp++ = 'q';
14239                 }
14240               else
14241                 *obufp++ = 'l';
14242             }
14243           break;
14244         case 'R':
14245           USED_REX (REX_W);
14246           if (rex & REX_W)
14247             *obufp++ = 'q';
14248           else if (sizeflag & DFLAG)
14249             {
14250               if (intel_syntax)
14251                   *obufp++ = 'd';
14252               else
14253                   *obufp++ = 'l';
14254             }
14255           else
14256             *obufp++ = 'w';
14257           if (intel_syntax && !p[1]
14258               && ((rex & REX_W) || (sizeflag & DFLAG)))
14259             *obufp++ = 'e';
14260           if (!(rex & REX_W))
14261             used_prefixes |= (prefixes & PREFIX_DATA);
14262           break;
14263         case 'V':
14264           if (l == 0 && len == 1)
14265             {
14266               if (intel_syntax)
14267                 break;
14268               if (address_mode == mode_64bit
14269                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14270                 {
14271                   if (sizeflag & SUFFIX_ALWAYS)
14272                     *obufp++ = 'q';
14273                   break;
14274                 }
14275             }
14276           else
14277             {
14278               if (l != 1
14279                   || len != 2
14280                   || last[0] != 'L')
14281                 {
14282                   SAVE_LAST (*p);
14283                   break;
14284                 }
14285
14286               if (rex & REX_W)
14287                 {
14288                   *obufp++ = 'a';
14289                   *obufp++ = 'b';
14290                   *obufp++ = 's';
14291                 }
14292             }
14293           /* Fall through.  */
14294           goto case_S;
14295         case 'S':
14296           if (l == 0 && len == 1)
14297             {
14298 case_S:
14299               if (intel_syntax)
14300                 break;
14301               if (sizeflag & SUFFIX_ALWAYS)
14302                 {
14303                   if (rex & REX_W)
14304                     *obufp++ = 'q';
14305                   else
14306                     {
14307                       if (sizeflag & DFLAG)
14308                         *obufp++ = 'l';
14309                       else
14310                         *obufp++ = 'w';
14311                       used_prefixes |= (prefixes & PREFIX_DATA);
14312                     }
14313                 }
14314             }
14315           else
14316             {
14317               if (l != 1
14318                   || len != 2
14319                   || last[0] != 'L')
14320                 {
14321                   SAVE_LAST (*p);
14322                   break;
14323                 }
14324
14325               if (address_mode == mode_64bit
14326                   && !(prefixes & PREFIX_ADDR))
14327                 {
14328                   *obufp++ = 'a';
14329                   *obufp++ = 'b';
14330                   *obufp++ = 's';
14331                 }
14332
14333               goto case_S;
14334             }
14335           break;
14336         case 'X':
14337           if (l != 0 || len != 1)
14338             {
14339               SAVE_LAST (*p);
14340               break;
14341             }
14342           if (need_vex && vex.prefix)
14343             {
14344               if (vex.prefix == DATA_PREFIX_OPCODE)
14345                 *obufp++ = 'd';
14346               else
14347                 *obufp++ = 's';
14348             }
14349           else
14350             {
14351               if (prefixes & PREFIX_DATA)
14352                 *obufp++ = 'd';
14353               else
14354                 *obufp++ = 's';
14355               used_prefixes |= (prefixes & PREFIX_DATA);
14356             }
14357           break;
14358         case 'Y':
14359           if (l == 0 && len == 1)
14360             {
14361               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14362                 break;
14363               if (rex & REX_W)
14364                 {
14365                   USED_REX (REX_W);
14366                   *obufp++ = 'q';
14367                 }
14368               break;
14369             }
14370           else
14371             {
14372               if (l != 1 || len != 2 || last[0] != 'X')
14373                 {
14374                   SAVE_LAST (*p);
14375                   break;
14376                 }
14377               if (!need_vex)
14378                 abort ();
14379               if (intel_syntax
14380                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14381                 break;
14382               switch (vex.length)
14383                 {
14384                 case 128:
14385                   *obufp++ = 'x';
14386                   break;
14387                 case 256:
14388                   *obufp++ = 'y';
14389                   break;
14390                 case 512:
14391                   if (!vex.evex)
14392                 default:
14393                     abort ();
14394                 }
14395             }
14396           break;
14397         case 'W':
14398           if (l == 0 && len == 1)
14399             {
14400               /* operand size flag for cwtl, cbtw */
14401               USED_REX (REX_W);
14402               if (rex & REX_W)
14403                 {
14404                   if (intel_syntax)
14405                     *obufp++ = 'd';
14406                   else
14407                     *obufp++ = 'l';
14408                 }
14409               else if (sizeflag & DFLAG)
14410                 *obufp++ = 'w';
14411               else
14412                 *obufp++ = 'b';
14413               if (!(rex & REX_W))
14414                 used_prefixes |= (prefixes & PREFIX_DATA);
14415             }
14416           else
14417             {
14418               if (l != 1
14419                   || len != 2
14420                   || (last[0] != 'X'
14421                       && last[0] != 'L'))
14422                 {
14423                   SAVE_LAST (*p);
14424                   break;
14425                 }
14426               if (!need_vex)
14427                 abort ();
14428               if (last[0] == 'X')
14429                 *obufp++ = vex.w ? 'd': 's';
14430               else
14431                 *obufp++ = vex.w ? 'q': 'd';
14432             }
14433           break;
14434         case '^':
14435           if (intel_syntax)
14436             break;
14437           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14438             {
14439               if (sizeflag & DFLAG)
14440                 *obufp++ = 'l';
14441               else
14442                 *obufp++ = 'w';
14443               used_prefixes |= (prefixes & PREFIX_DATA);
14444             }
14445           break;
14446         case '@':
14447           if (intel_syntax)
14448             break;
14449           if (address_mode == mode_64bit
14450               && (isa64 == intel64
14451                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14452               *obufp++ = 'q';
14453           else if ((prefixes & PREFIX_DATA))
14454             {
14455               if (!(sizeflag & DFLAG))
14456                 *obufp++ = 'w';
14457               used_prefixes |= (prefixes & PREFIX_DATA);
14458             }
14459           break;
14460         }
14461       alt = 0;
14462     }
14463   *obufp = 0;
14464   mnemonicendp = obufp;
14465   return 0;
14466 }
14467
14468 static void
14469 oappend (const char *s)
14470 {
14471   obufp = stpcpy (obufp, s);
14472 }
14473
14474 static void
14475 append_seg (void)
14476 {
14477   /* Only print the active segment register.  */
14478   if (!active_seg_prefix)
14479     return;
14480
14481   used_prefixes |= active_seg_prefix;
14482   switch (active_seg_prefix)
14483     {
14484     case PREFIX_CS:
14485       oappend_maybe_intel ("%cs:");
14486       break;
14487     case PREFIX_DS:
14488       oappend_maybe_intel ("%ds:");
14489       break;
14490     case PREFIX_SS:
14491       oappend_maybe_intel ("%ss:");
14492       break;
14493     case PREFIX_ES:
14494       oappend_maybe_intel ("%es:");
14495       break;
14496     case PREFIX_FS:
14497       oappend_maybe_intel ("%fs:");
14498       break;
14499     case PREFIX_GS:
14500       oappend_maybe_intel ("%gs:");
14501       break;
14502     default:
14503       break;
14504     }
14505 }
14506
14507 static void
14508 OP_indirE (int bytemode, int sizeflag)
14509 {
14510   if (!intel_syntax)
14511     oappend ("*");
14512   OP_E (bytemode, sizeflag);
14513 }
14514
14515 static void
14516 print_operand_value (char *buf, int hex, bfd_vma disp)
14517 {
14518   if (address_mode == mode_64bit)
14519     {
14520       if (hex)
14521         {
14522           char tmp[30];
14523           int i;
14524           buf[0] = '0';
14525           buf[1] = 'x';
14526           sprintf_vma (tmp, disp);
14527           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14528           strcpy (buf + 2, tmp + i);
14529         }
14530       else
14531         {
14532           bfd_signed_vma v = disp;
14533           char tmp[30];
14534           int i;
14535           if (v < 0)
14536             {
14537               *(buf++) = '-';
14538               v = -disp;
14539               /* Check for possible overflow on 0x8000000000000000.  */
14540               if (v < 0)
14541                 {
14542                   strcpy (buf, "9223372036854775808");
14543                   return;
14544                 }
14545             }
14546           if (!v)
14547             {
14548               strcpy (buf, "0");
14549               return;
14550             }
14551
14552           i = 0;
14553           tmp[29] = 0;
14554           while (v)
14555             {
14556               tmp[28 - i] = (v % 10) + '0';
14557               v /= 10;
14558               i++;
14559             }
14560           strcpy (buf, tmp + 29 - i);
14561         }
14562     }
14563   else
14564     {
14565       if (hex)
14566         sprintf (buf, "0x%x", (unsigned int) disp);
14567       else
14568         sprintf (buf, "%d", (int) disp);
14569     }
14570 }
14571
14572 /* Put DISP in BUF as signed hex number.  */
14573
14574 static void
14575 print_displacement (char *buf, bfd_vma disp)
14576 {
14577   bfd_signed_vma val = disp;
14578   char tmp[30];
14579   int i, j = 0;
14580
14581   if (val < 0)
14582     {
14583       buf[j++] = '-';
14584       val = -disp;
14585
14586       /* Check for possible overflow.  */
14587       if (val < 0)
14588         {
14589           switch (address_mode)
14590             {
14591             case mode_64bit:
14592               strcpy (buf + j, "0x8000000000000000");
14593               break;
14594             case mode_32bit:
14595               strcpy (buf + j, "0x80000000");
14596               break;
14597             case mode_16bit:
14598               strcpy (buf + j, "0x8000");
14599               break;
14600             }
14601           return;
14602         }
14603     }
14604
14605   buf[j++] = '0';
14606   buf[j++] = 'x';
14607
14608   sprintf_vma (tmp, (bfd_vma) val);
14609   for (i = 0; tmp[i] == '0'; i++)
14610     continue;
14611   if (tmp[i] == '\0')
14612     i--;
14613   strcpy (buf + j, tmp + i);
14614 }
14615
14616 static void
14617 intel_operand_size (int bytemode, int sizeflag)
14618 {
14619   if (vex.evex
14620       && vex.b
14621       && (bytemode == x_mode
14622           || bytemode == evex_half_bcst_xmmq_mode))
14623     {
14624       if (vex.w)
14625         oappend ("QWORD PTR ");
14626       else
14627         oappend ("DWORD PTR ");
14628       return;
14629     }
14630   switch (bytemode)
14631     {
14632     case b_mode:
14633     case b_swap_mode:
14634     case dqb_mode:
14635     case db_mode:
14636       oappend ("BYTE PTR ");
14637       break;
14638     case w_mode:
14639     case dw_mode:
14640     case dqw_mode:
14641       oappend ("WORD PTR ");
14642       break;
14643     case indir_v_mode:
14644       if (address_mode == mode_64bit && isa64 == intel64)
14645         {
14646           oappend ("QWORD PTR ");
14647           break;
14648         }
14649       /* Fall through.  */
14650     case stack_v_mode:
14651       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14652         {
14653           oappend ("QWORD PTR ");
14654           break;
14655         }
14656       /* Fall through.  */
14657     case v_mode:
14658     case v_swap_mode:
14659     case dq_mode:
14660       USED_REX (REX_W);
14661       if (rex & REX_W)
14662         oappend ("QWORD PTR ");
14663       else
14664         {
14665           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14666             oappend ("DWORD PTR ");
14667           else
14668             oappend ("WORD PTR ");
14669           used_prefixes |= (prefixes & PREFIX_DATA);
14670         }
14671       break;
14672     case z_mode:
14673       if ((rex & REX_W) || (sizeflag & DFLAG))
14674         *obufp++ = 'D';
14675       oappend ("WORD PTR ");
14676       if (!(rex & REX_W))
14677         used_prefixes |= (prefixes & PREFIX_DATA);
14678       break;
14679     case a_mode:
14680       if (sizeflag & DFLAG)
14681         oappend ("QWORD PTR ");
14682       else
14683         oappend ("DWORD PTR ");
14684       used_prefixes |= (prefixes & PREFIX_DATA);
14685       break;
14686     case d_mode:
14687     case d_scalar_mode:
14688     case d_scalar_swap_mode:
14689     case d_swap_mode:
14690     case dqd_mode:
14691       oappend ("DWORD PTR ");
14692       break;
14693     case q_mode:
14694     case q_scalar_mode:
14695     case q_scalar_swap_mode:
14696     case q_swap_mode:
14697       oappend ("QWORD PTR ");
14698       break;
14699     case m_mode:
14700       if (address_mode == mode_64bit)
14701         oappend ("QWORD PTR ");
14702       else
14703         oappend ("DWORD PTR ");
14704       break;
14705     case f_mode:
14706       if (sizeflag & DFLAG)
14707         oappend ("FWORD PTR ");
14708       else
14709         oappend ("DWORD PTR ");
14710       used_prefixes |= (prefixes & PREFIX_DATA);
14711       break;
14712     case t_mode:
14713       oappend ("TBYTE PTR ");
14714       break;
14715     case x_mode:
14716     case x_swap_mode:
14717     case evex_x_gscat_mode:
14718     case evex_x_nobcst_mode:
14719       if (need_vex)
14720         {
14721           switch (vex.length)
14722             {
14723             case 128:
14724               oappend ("XMMWORD PTR ");
14725               break;
14726             case 256:
14727               oappend ("YMMWORD PTR ");
14728               break;
14729             case 512:
14730               oappend ("ZMMWORD PTR ");
14731               break;
14732             default:
14733               abort ();
14734             }
14735         }
14736       else
14737         oappend ("XMMWORD PTR ");
14738       break;
14739     case xmm_mode:
14740       oappend ("XMMWORD PTR ");
14741       break;
14742     case ymm_mode:
14743       oappend ("YMMWORD PTR ");
14744       break;
14745     case xmmq_mode:
14746     case evex_half_bcst_xmmq_mode:
14747       if (!need_vex)
14748         abort ();
14749
14750       switch (vex.length)
14751         {
14752         case 128:
14753           oappend ("QWORD PTR ");
14754           break;
14755         case 256:
14756           oappend ("XMMWORD PTR ");
14757           break;
14758         case 512:
14759           oappend ("YMMWORD PTR ");
14760           break;
14761         default:
14762           abort ();
14763         }
14764       break;
14765     case xmm_mb_mode:
14766       if (!need_vex)
14767         abort ();
14768
14769       switch (vex.length)
14770         {
14771         case 128:
14772         case 256:
14773         case 512:
14774           oappend ("BYTE PTR ");
14775           break;
14776         default:
14777           abort ();
14778         }
14779       break;
14780     case xmm_mw_mode:
14781       if (!need_vex)
14782         abort ();
14783
14784       switch (vex.length)
14785         {
14786         case 128:
14787         case 256:
14788         case 512:
14789           oappend ("WORD PTR ");
14790           break;
14791         default:
14792           abort ();
14793         }
14794       break;
14795     case xmm_md_mode:
14796       if (!need_vex)
14797         abort ();
14798
14799       switch (vex.length)
14800         {
14801         case 128:
14802         case 256:
14803         case 512:
14804           oappend ("DWORD PTR ");
14805           break;
14806         default:
14807           abort ();
14808         }
14809       break;
14810     case xmm_mq_mode:
14811       if (!need_vex)
14812         abort ();
14813
14814       switch (vex.length)
14815         {
14816         case 128:
14817         case 256:
14818         case 512:
14819           oappend ("QWORD PTR ");
14820           break;
14821         default:
14822           abort ();
14823         }
14824       break;
14825     case xmmdw_mode:
14826       if (!need_vex)
14827         abort ();
14828
14829       switch (vex.length)
14830         {
14831         case 128:
14832           oappend ("WORD PTR ");
14833           break;
14834         case 256:
14835           oappend ("DWORD PTR ");
14836           break;
14837         case 512:
14838           oappend ("QWORD PTR ");
14839           break;
14840         default:
14841           abort ();
14842         }
14843       break;
14844     case xmmqd_mode:
14845       if (!need_vex)
14846         abort ();
14847
14848       switch (vex.length)
14849         {
14850         case 128:
14851           oappend ("DWORD PTR ");
14852           break;
14853         case 256:
14854           oappend ("QWORD PTR ");
14855           break;
14856         case 512:
14857           oappend ("XMMWORD PTR ");
14858           break;
14859         default:
14860           abort ();
14861         }
14862       break;
14863     case ymmq_mode:
14864       if (!need_vex)
14865         abort ();
14866
14867       switch (vex.length)
14868         {
14869         case 128:
14870           oappend ("QWORD PTR ");
14871           break;
14872         case 256:
14873           oappend ("YMMWORD PTR ");
14874           break;
14875         case 512:
14876           oappend ("ZMMWORD PTR ");
14877           break;
14878         default:
14879           abort ();
14880         }
14881       break;
14882     case ymmxmm_mode:
14883       if (!need_vex)
14884         abort ();
14885
14886       switch (vex.length)
14887         {
14888         case 128:
14889         case 256:
14890           oappend ("XMMWORD PTR ");
14891           break;
14892         default:
14893           abort ();
14894         }
14895       break;
14896     case o_mode:
14897       oappend ("OWORD PTR ");
14898       break;
14899     case xmm_mdq_mode:
14900     case vex_w_dq_mode:
14901     case vex_scalar_w_dq_mode:
14902       if (!need_vex)
14903         abort ();
14904
14905       if (vex.w)
14906         oappend ("QWORD PTR ");
14907       else
14908         oappend ("DWORD PTR ");
14909       break;
14910     case vex_vsib_d_w_dq_mode:
14911     case vex_vsib_q_w_dq_mode:
14912       if (!need_vex)
14913         abort ();
14914
14915       if (!vex.evex)
14916         {
14917           if (vex.w)
14918             oappend ("QWORD PTR ");
14919           else
14920             oappend ("DWORD PTR ");
14921         }
14922       else
14923         {
14924           switch (vex.length)
14925             {
14926             case 128:
14927               oappend ("XMMWORD PTR ");
14928               break;
14929             case 256:
14930               oappend ("YMMWORD PTR ");
14931               break;
14932             case 512:
14933               oappend ("ZMMWORD PTR ");
14934               break;
14935             default:
14936               abort ();
14937             }
14938         }
14939       break;
14940     case vex_vsib_q_w_d_mode:
14941     case vex_vsib_d_w_d_mode:
14942       if (!need_vex || !vex.evex)
14943         abort ();
14944
14945       switch (vex.length)
14946         {
14947         case 128:
14948           oappend ("QWORD PTR ");
14949           break;
14950         case 256:
14951           oappend ("XMMWORD PTR ");
14952           break;
14953         case 512:
14954           oappend ("YMMWORD PTR ");
14955           break;
14956         default:
14957           abort ();
14958         }
14959
14960       break;
14961     case mask_bd_mode:
14962       if (!need_vex || vex.length != 128)
14963         abort ();
14964       if (vex.w)
14965         oappend ("DWORD PTR ");
14966       else
14967         oappend ("BYTE PTR ");
14968       break;
14969     case mask_mode:
14970       if (!need_vex)
14971         abort ();
14972       if (vex.w)
14973         oappend ("QWORD PTR ");
14974       else
14975         oappend ("WORD PTR ");
14976       break;
14977     case v_bnd_mode:
14978     default:
14979       break;
14980     }
14981 }
14982
14983 static void
14984 OP_E_register (int bytemode, int sizeflag)
14985 {
14986   int reg = modrm.rm;
14987   const char **names;
14988
14989   USED_REX (REX_B);
14990   if ((rex & REX_B))
14991     reg += 8;
14992
14993   if ((sizeflag & SUFFIX_ALWAYS)
14994       && (bytemode == b_swap_mode
14995           || bytemode == v_swap_mode))
14996     swap_operand ();
14997
14998   switch (bytemode)
14999     {
15000     case b_mode:
15001     case b_swap_mode:
15002       USED_REX (0);
15003       if (rex)
15004         names = names8rex;
15005       else
15006         names = names8;
15007       break;
15008     case w_mode:
15009       names = names16;
15010       break;
15011     case d_mode:
15012     case dw_mode:
15013     case db_mode:
15014       names = names32;
15015       break;
15016     case q_mode:
15017       names = names64;
15018       break;
15019     case m_mode:
15020     case v_bnd_mode:
15021       names = address_mode == mode_64bit ? names64 : names32;
15022       break;
15023     case bnd_mode:
15024       if (reg > 0x3)
15025         {
15026           oappend ("(bad)");
15027           return;
15028         }
15029       names = names_bnd;
15030       break;
15031     case indir_v_mode:
15032       if (address_mode == mode_64bit && isa64 == intel64)
15033         {
15034           names = names64;
15035           break;
15036         }
15037       /* Fall through.  */
15038     case stack_v_mode:
15039       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15040         {
15041           names = names64;
15042           break;
15043         }
15044       bytemode = v_mode;
15045       /* Fall through.  */
15046     case v_mode:
15047     case v_swap_mode:
15048     case dq_mode:
15049     case dqb_mode:
15050     case dqd_mode:
15051     case dqw_mode:
15052       USED_REX (REX_W);
15053       if (rex & REX_W)
15054         names = names64;
15055       else
15056         {
15057           if ((sizeflag & DFLAG)
15058               || (bytemode != v_mode
15059                   && bytemode != v_swap_mode))
15060             names = names32;
15061           else
15062             names = names16;
15063           used_prefixes |= (prefixes & PREFIX_DATA);
15064         }
15065       break;
15066     case mask_bd_mode:
15067     case mask_mode:
15068       if (reg > 0x7)
15069         {
15070           oappend ("(bad)");
15071           return;
15072         }
15073       names = names_mask;
15074       break;
15075     case 0:
15076       return;
15077     default:
15078       oappend (INTERNAL_DISASSEMBLER_ERROR);
15079       return;
15080     }
15081   oappend (names[reg]);
15082 }
15083
15084 static void
15085 OP_E_memory (int bytemode, int sizeflag)
15086 {
15087   bfd_vma disp = 0;
15088   int add = (rex & REX_B) ? 8 : 0;
15089   int riprel = 0;
15090   int shift;
15091
15092   if (vex.evex)
15093     {
15094       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15095       if (vex.b
15096           && bytemode != x_mode
15097           && bytemode != xmmq_mode
15098           && bytemode != evex_half_bcst_xmmq_mode)
15099         {
15100           BadOp ();
15101           return;
15102         }
15103       switch (bytemode)
15104         {
15105         case dqw_mode:
15106         case dw_mode:
15107           shift = 1;
15108           break;
15109         case dqb_mode:
15110         case db_mode:
15111           shift = 0;
15112           break;
15113         case vex_vsib_d_w_dq_mode:
15114         case vex_vsib_d_w_d_mode:
15115         case vex_vsib_q_w_dq_mode:
15116         case vex_vsib_q_w_d_mode:
15117         case evex_x_gscat_mode:
15118         case xmm_mdq_mode:
15119           shift = vex.w ? 3 : 2;
15120           break;
15121         case x_mode:
15122         case evex_half_bcst_xmmq_mode:
15123         case xmmq_mode:
15124           if (vex.b)
15125             {
15126               shift = vex.w ? 3 : 2;
15127               break;
15128             }
15129           /* Fall through.  */
15130         case xmmqd_mode:
15131         case xmmdw_mode:
15132         case ymmq_mode:
15133         case evex_x_nobcst_mode:
15134         case x_swap_mode:
15135           switch (vex.length)
15136             {
15137             case 128:
15138               shift = 4;
15139               break;
15140             case 256:
15141               shift = 5;
15142               break;
15143             case 512:
15144               shift = 6;
15145               break;
15146             default:
15147               abort ();
15148             }
15149           break;
15150         case ymm_mode:
15151           shift = 5;
15152           break;
15153         case xmm_mode:
15154           shift = 4;
15155           break;
15156         case xmm_mq_mode:
15157         case q_mode:
15158         case q_scalar_mode:
15159         case q_swap_mode:
15160         case q_scalar_swap_mode:
15161           shift = 3;
15162           break;
15163         case dqd_mode:
15164         case xmm_md_mode:
15165         case d_mode:
15166         case d_scalar_mode:
15167         case d_swap_mode:
15168         case d_scalar_swap_mode:
15169           shift = 2;
15170           break;
15171         case xmm_mw_mode:
15172           shift = 1;
15173           break;
15174         case xmm_mb_mode:
15175           shift = 0;
15176           break;
15177         default:
15178           abort ();
15179         }
15180       /* Make necessary corrections to shift for modes that need it.
15181          For these modes we currently have shift 4, 5 or 6 depending on
15182          vex.length (it corresponds to xmmword, ymmword or zmmword
15183          operand).  We might want to make it 3, 4 or 5 (e.g. for
15184          xmmq_mode).  In case of broadcast enabled the corrections
15185          aren't needed, as element size is always 32 or 64 bits.  */
15186       if (!vex.b
15187           && (bytemode == xmmq_mode
15188               || bytemode == evex_half_bcst_xmmq_mode))
15189         shift -= 1;
15190       else if (bytemode == xmmqd_mode)
15191         shift -= 2;
15192       else if (bytemode == xmmdw_mode)
15193         shift -= 3;
15194       else if (bytemode == ymmq_mode && vex.length == 128)
15195         shift -= 1;
15196     }
15197   else
15198     shift = 0;
15199
15200   USED_REX (REX_B);
15201   if (intel_syntax)
15202     intel_operand_size (bytemode, sizeflag);
15203   append_seg ();
15204
15205   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15206     {
15207       /* 32/64 bit address mode */
15208       int havedisp;
15209       int havesib;
15210       int havebase;
15211       int haveindex;
15212       int needindex;
15213       int base, rbase;
15214       int vindex = 0;
15215       int scale = 0;
15216       int addr32flag = !((sizeflag & AFLAG)
15217                          || bytemode == v_bnd_mode
15218                          || bytemode == bnd_mode);
15219       const char **indexes64 = names64;
15220       const char **indexes32 = names32;
15221
15222       havesib = 0;
15223       havebase = 1;
15224       haveindex = 0;
15225       base = modrm.rm;
15226
15227       if (base == 4)
15228         {
15229           havesib = 1;
15230           vindex = sib.index;
15231           USED_REX (REX_X);
15232           if (rex & REX_X)
15233             vindex += 8;
15234           switch (bytemode)
15235             {
15236             case vex_vsib_d_w_dq_mode:
15237             case vex_vsib_d_w_d_mode:
15238             case vex_vsib_q_w_dq_mode:
15239             case vex_vsib_q_w_d_mode:
15240               if (!need_vex)
15241                 abort ();
15242               if (vex.evex)
15243                 {
15244                   if (!vex.v)
15245                     vindex += 16;
15246                 }
15247
15248               haveindex = 1;
15249               switch (vex.length)
15250                 {
15251                 case 128:
15252                   indexes64 = indexes32 = names_xmm;
15253                   break;
15254                 case 256:
15255                   if (!vex.w
15256                       || bytemode == vex_vsib_q_w_dq_mode
15257                       || bytemode == vex_vsib_q_w_d_mode)
15258                     indexes64 = indexes32 = names_ymm;
15259                   else
15260                     indexes64 = indexes32 = names_xmm;
15261                   break;
15262                 case 512:
15263                   if (!vex.w
15264                       || bytemode == vex_vsib_q_w_dq_mode
15265                       || bytemode == vex_vsib_q_w_d_mode)
15266                     indexes64 = indexes32 = names_zmm;
15267                   else
15268                     indexes64 = indexes32 = names_ymm;
15269                   break;
15270                 default:
15271                   abort ();
15272                 }
15273               break;
15274             default:
15275               haveindex = vindex != 4;
15276               break;
15277             }
15278           scale = sib.scale;
15279           base = sib.base;
15280           codep++;
15281         }
15282       rbase = base + add;
15283
15284       switch (modrm.mod)
15285         {
15286         case 0:
15287           if (base == 5)
15288             {
15289               havebase = 0;
15290               if (address_mode == mode_64bit && !havesib)
15291                 riprel = 1;
15292               disp = get32s ();
15293             }
15294           break;
15295         case 1:
15296           FETCH_DATA (the_info, codep + 1);
15297           disp = *codep++;
15298           if ((disp & 0x80) != 0)
15299             disp -= 0x100;
15300           if (vex.evex && shift > 0)
15301             disp <<= shift;
15302           break;
15303         case 2:
15304           disp = get32s ();
15305           break;
15306         }
15307
15308       /* In 32bit mode, we need index register to tell [offset] from
15309          [eiz*1 + offset].  */
15310       needindex = (havesib
15311                    && !havebase
15312                    && !haveindex
15313                    && address_mode == mode_32bit);
15314       havedisp = (havebase
15315                   || needindex
15316                   || (havesib && (haveindex || scale != 0)));
15317
15318       if (!intel_syntax)
15319         if (modrm.mod != 0 || base == 5)
15320           {
15321             if (havedisp || riprel)
15322               print_displacement (scratchbuf, disp);
15323             else
15324               print_operand_value (scratchbuf, 1, disp);
15325             oappend (scratchbuf);
15326             if (riprel)
15327               {
15328                 set_op (disp, 1);
15329                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15330               }
15331           }
15332
15333       if ((havebase || haveindex || riprel)
15334           && (bytemode != v_bnd_mode)
15335           && (bytemode != bnd_mode))
15336         used_prefixes |= PREFIX_ADDR;
15337
15338       if (havedisp || (intel_syntax && riprel))
15339         {
15340           *obufp++ = open_char;
15341           if (intel_syntax && riprel)
15342             {
15343               set_op (disp, 1);
15344               oappend (!addr32flag ? "rip" : "eip");
15345             }
15346           *obufp = '\0';
15347           if (havebase)
15348             oappend (address_mode == mode_64bit && !addr32flag
15349                      ? names64[rbase] : names32[rbase]);
15350           if (havesib)
15351             {
15352               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15353                  print index to tell base + index from base.  */
15354               if (scale != 0
15355                   || needindex
15356                   || haveindex
15357                   || (havebase && base != ESP_REG_NUM))
15358                 {
15359                   if (!intel_syntax || havebase)
15360                     {
15361                       *obufp++ = separator_char;
15362                       *obufp = '\0';
15363                     }
15364                   if (haveindex)
15365                     oappend (address_mode == mode_64bit && !addr32flag
15366                              ? indexes64[vindex] : indexes32[vindex]);
15367                   else
15368                     oappend (address_mode == mode_64bit && !addr32flag
15369                              ? index64 : index32);
15370
15371                   *obufp++ = scale_char;
15372                   *obufp = '\0';
15373                   sprintf (scratchbuf, "%d", 1 << scale);
15374                   oappend (scratchbuf);
15375                 }
15376             }
15377           if (intel_syntax
15378               && (disp || modrm.mod != 0 || base == 5))
15379             {
15380               if (!havedisp || (bfd_signed_vma) disp >= 0)
15381                 {
15382                   *obufp++ = '+';
15383                   *obufp = '\0';
15384                 }
15385               else if (modrm.mod != 1 && disp != -disp)
15386                 {
15387                   *obufp++ = '-';
15388                   *obufp = '\0';
15389                   disp = - (bfd_signed_vma) disp;
15390                 }
15391
15392               if (havedisp)
15393                 print_displacement (scratchbuf, disp);
15394               else
15395                 print_operand_value (scratchbuf, 1, disp);
15396               oappend (scratchbuf);
15397             }
15398
15399           *obufp++ = close_char;
15400           *obufp = '\0';
15401         }
15402       else if (intel_syntax)
15403         {
15404           if (modrm.mod != 0 || base == 5)
15405             {
15406               if (!active_seg_prefix)
15407                 {
15408                   oappend (names_seg[ds_reg - es_reg]);
15409                   oappend (":");
15410                 }
15411               print_operand_value (scratchbuf, 1, disp);
15412               oappend (scratchbuf);
15413             }
15414         }
15415     }
15416   else
15417     {
15418       /* 16 bit address mode */
15419       used_prefixes |= prefixes & PREFIX_ADDR;
15420       switch (modrm.mod)
15421         {
15422         case 0:
15423           if (modrm.rm == 6)
15424             {
15425               disp = get16 ();
15426               if ((disp & 0x8000) != 0)
15427                 disp -= 0x10000;
15428             }
15429           break;
15430         case 1:
15431           FETCH_DATA (the_info, codep + 1);
15432           disp = *codep++;
15433           if ((disp & 0x80) != 0)
15434             disp -= 0x100;
15435           break;
15436         case 2:
15437           disp = get16 ();
15438           if ((disp & 0x8000) != 0)
15439             disp -= 0x10000;
15440           break;
15441         }
15442
15443       if (!intel_syntax)
15444         if (modrm.mod != 0 || modrm.rm == 6)
15445           {
15446             print_displacement (scratchbuf, disp);
15447             oappend (scratchbuf);
15448           }
15449
15450       if (modrm.mod != 0 || modrm.rm != 6)
15451         {
15452           *obufp++ = open_char;
15453           *obufp = '\0';
15454           oappend (index16[modrm.rm]);
15455           if (intel_syntax
15456               && (disp || modrm.mod != 0 || modrm.rm == 6))
15457             {
15458               if ((bfd_signed_vma) disp >= 0)
15459                 {
15460                   *obufp++ = '+';
15461                   *obufp = '\0';
15462                 }
15463               else if (modrm.mod != 1)
15464                 {
15465                   *obufp++ = '-';
15466                   *obufp = '\0';
15467                   disp = - (bfd_signed_vma) disp;
15468                 }
15469
15470               print_displacement (scratchbuf, disp);
15471               oappend (scratchbuf);
15472             }
15473
15474           *obufp++ = close_char;
15475           *obufp = '\0';
15476         }
15477       else if (intel_syntax)
15478         {
15479           if (!active_seg_prefix)
15480             {
15481               oappend (names_seg[ds_reg - es_reg]);
15482               oappend (":");
15483             }
15484           print_operand_value (scratchbuf, 1, disp & 0xffff);
15485           oappend (scratchbuf);
15486         }
15487     }
15488   if (vex.evex && vex.b
15489       && (bytemode == x_mode
15490           || bytemode == xmmq_mode
15491           || bytemode == evex_half_bcst_xmmq_mode))
15492     {
15493       if (vex.w
15494           || bytemode == xmmq_mode
15495           || bytemode == evex_half_bcst_xmmq_mode)
15496         {
15497           switch (vex.length)
15498             {
15499             case 128:
15500               oappend ("{1to2}");
15501               break;
15502             case 256:
15503               oappend ("{1to4}");
15504               break;
15505             case 512:
15506               oappend ("{1to8}");
15507               break;
15508             default:
15509               abort ();
15510             }
15511         }
15512       else
15513         {
15514           switch (vex.length)
15515             {
15516             case 128:
15517               oappend ("{1to4}");
15518               break;
15519             case 256:
15520               oappend ("{1to8}");
15521               break;
15522             case 512:
15523               oappend ("{1to16}");
15524               break;
15525             default:
15526               abort ();
15527             }
15528         }
15529     }
15530 }
15531
15532 static void
15533 OP_E (int bytemode, int sizeflag)
15534 {
15535   /* Skip mod/rm byte.  */
15536   MODRM_CHECK;
15537   codep++;
15538
15539   if (modrm.mod == 3)
15540     OP_E_register (bytemode, sizeflag);
15541   else
15542     OP_E_memory (bytemode, sizeflag);
15543 }
15544
15545 static void
15546 OP_G (int bytemode, int sizeflag)
15547 {
15548   int add = 0;
15549   USED_REX (REX_R);
15550   if (rex & REX_R)
15551     add += 8;
15552   switch (bytemode)
15553     {
15554     case b_mode:
15555       USED_REX (0);
15556       if (rex)
15557         oappend (names8rex[modrm.reg + add]);
15558       else
15559         oappend (names8[modrm.reg + add]);
15560       break;
15561     case w_mode:
15562       oappend (names16[modrm.reg + add]);
15563       break;
15564     case d_mode:
15565     case db_mode:
15566     case dw_mode:
15567       oappend (names32[modrm.reg + add]);
15568       break;
15569     case q_mode:
15570       oappend (names64[modrm.reg + add]);
15571       break;
15572     case bnd_mode:
15573       if (modrm.reg > 0x3)
15574         {
15575           oappend ("(bad)");
15576           return;
15577         }
15578       oappend (names_bnd[modrm.reg]);
15579       break;
15580     case v_mode:
15581     case dq_mode:
15582     case dqb_mode:
15583     case dqd_mode:
15584     case dqw_mode:
15585       USED_REX (REX_W);
15586       if (rex & REX_W)
15587         oappend (names64[modrm.reg + add]);
15588       else
15589         {
15590           if ((sizeflag & DFLAG) || bytemode != v_mode)
15591             oappend (names32[modrm.reg + add]);
15592           else
15593             oappend (names16[modrm.reg + add]);
15594           used_prefixes |= (prefixes & PREFIX_DATA);
15595         }
15596       break;
15597     case m_mode:
15598       if (address_mode == mode_64bit)
15599         oappend (names64[modrm.reg + add]);
15600       else
15601         oappend (names32[modrm.reg + add]);
15602       break;
15603     case mask_bd_mode:
15604     case mask_mode:
15605       if ((modrm.reg + add) > 0x7)
15606         {
15607           oappend ("(bad)");
15608           return;
15609         }
15610       oappend (names_mask[modrm.reg + add]);
15611       break;
15612     default:
15613       oappend (INTERNAL_DISASSEMBLER_ERROR);
15614       break;
15615     }
15616 }
15617
15618 static bfd_vma
15619 get64 (void)
15620 {
15621   bfd_vma x;
15622 #ifdef BFD64
15623   unsigned int a;
15624   unsigned int b;
15625
15626   FETCH_DATA (the_info, codep + 8);
15627   a = *codep++ & 0xff;
15628   a |= (*codep++ & 0xff) << 8;
15629   a |= (*codep++ & 0xff) << 16;
15630   a |= (*codep++ & 0xffu) << 24;
15631   b = *codep++ & 0xff;
15632   b |= (*codep++ & 0xff) << 8;
15633   b |= (*codep++ & 0xff) << 16;
15634   b |= (*codep++ & 0xffu) << 24;
15635   x = a + ((bfd_vma) b << 32);
15636 #else
15637   abort ();
15638   x = 0;
15639 #endif
15640   return x;
15641 }
15642
15643 static bfd_signed_vma
15644 get32 (void)
15645 {
15646   bfd_signed_vma x = 0;
15647
15648   FETCH_DATA (the_info, codep + 4);
15649   x = *codep++ & (bfd_signed_vma) 0xff;
15650   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15651   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15652   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15653   return x;
15654 }
15655
15656 static bfd_signed_vma
15657 get32s (void)
15658 {
15659   bfd_signed_vma x = 0;
15660
15661   FETCH_DATA (the_info, codep + 4);
15662   x = *codep++ & (bfd_signed_vma) 0xff;
15663   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15664   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15665   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15666
15667   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15668
15669   return x;
15670 }
15671
15672 static int
15673 get16 (void)
15674 {
15675   int x = 0;
15676
15677   FETCH_DATA (the_info, codep + 2);
15678   x = *codep++ & 0xff;
15679   x |= (*codep++ & 0xff) << 8;
15680   return x;
15681 }
15682
15683 static void
15684 set_op (bfd_vma op, int riprel)
15685 {
15686   op_index[op_ad] = op_ad;
15687   if (address_mode == mode_64bit)
15688     {
15689       op_address[op_ad] = op;
15690       op_riprel[op_ad] = riprel;
15691     }
15692   else
15693     {
15694       /* Mask to get a 32-bit address.  */
15695       op_address[op_ad] = op & 0xffffffff;
15696       op_riprel[op_ad] = riprel & 0xffffffff;
15697     }
15698 }
15699
15700 static void
15701 OP_REG (int code, int sizeflag)
15702 {
15703   const char *s;
15704   int add;
15705
15706   switch (code)
15707     {
15708     case es_reg: case ss_reg: case cs_reg:
15709     case ds_reg: case fs_reg: case gs_reg:
15710       oappend (names_seg[code - es_reg]);
15711       return;
15712     }
15713
15714   USED_REX (REX_B);
15715   if (rex & REX_B)
15716     add = 8;
15717   else
15718     add = 0;
15719
15720   switch (code)
15721     {
15722     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15723     case sp_reg: case bp_reg: case si_reg: case di_reg:
15724       s = names16[code - ax_reg + add];
15725       break;
15726     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15727     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15728       USED_REX (0);
15729       if (rex)
15730         s = names8rex[code - al_reg + add];
15731       else
15732         s = names8[code - al_reg];
15733       break;
15734     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15735     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15736       if (address_mode == mode_64bit
15737           && ((sizeflag & DFLAG) || (rex & REX_W)))
15738         {
15739           s = names64[code - rAX_reg + add];
15740           break;
15741         }
15742       code += eAX_reg - rAX_reg;
15743       /* Fall through.  */
15744     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15745     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15746       USED_REX (REX_W);
15747       if (rex & REX_W)
15748         s = names64[code - eAX_reg + add];
15749       else
15750         {
15751           if (sizeflag & DFLAG)
15752             s = names32[code - eAX_reg + add];
15753           else
15754             s = names16[code - eAX_reg + add];
15755           used_prefixes |= (prefixes & PREFIX_DATA);
15756         }
15757       break;
15758     default:
15759       s = INTERNAL_DISASSEMBLER_ERROR;
15760       break;
15761     }
15762   oappend (s);
15763 }
15764
15765 static void
15766 OP_IMREG (int code, int sizeflag)
15767 {
15768   const char *s;
15769
15770   switch (code)
15771     {
15772     case indir_dx_reg:
15773       if (intel_syntax)
15774         s = "dx";
15775       else
15776         s = "(%dx)";
15777       break;
15778     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15779     case sp_reg: case bp_reg: case si_reg: case di_reg:
15780       s = names16[code - ax_reg];
15781       break;
15782     case es_reg: case ss_reg: case cs_reg:
15783     case ds_reg: case fs_reg: case gs_reg:
15784       s = names_seg[code - es_reg];
15785       break;
15786     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15787     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15788       USED_REX (0);
15789       if (rex)
15790         s = names8rex[code - al_reg];
15791       else
15792         s = names8[code - al_reg];
15793       break;
15794     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15795     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15796       USED_REX (REX_W);
15797       if (rex & REX_W)
15798         s = names64[code - eAX_reg];
15799       else
15800         {
15801           if (sizeflag & DFLAG)
15802             s = names32[code - eAX_reg];
15803           else
15804             s = names16[code - eAX_reg];
15805           used_prefixes |= (prefixes & PREFIX_DATA);
15806         }
15807       break;
15808     case z_mode_ax_reg:
15809       if ((rex & REX_W) || (sizeflag & DFLAG))
15810         s = *names32;
15811       else
15812         s = *names16;
15813       if (!(rex & REX_W))
15814         used_prefixes |= (prefixes & PREFIX_DATA);
15815       break;
15816     default:
15817       s = INTERNAL_DISASSEMBLER_ERROR;
15818       break;
15819     }
15820   oappend (s);
15821 }
15822
15823 static void
15824 OP_I (int bytemode, int sizeflag)
15825 {
15826   bfd_signed_vma op;
15827   bfd_signed_vma mask = -1;
15828
15829   switch (bytemode)
15830     {
15831     case b_mode:
15832       FETCH_DATA (the_info, codep + 1);
15833       op = *codep++;
15834       mask = 0xff;
15835       break;
15836     case q_mode:
15837       if (address_mode == mode_64bit)
15838         {
15839           op = get32s ();
15840           break;
15841         }
15842       /* Fall through.  */
15843     case v_mode:
15844       USED_REX (REX_W);
15845       if (rex & REX_W)
15846         op = get32s ();
15847       else
15848         {
15849           if (sizeflag & DFLAG)
15850             {
15851               op = get32 ();
15852               mask = 0xffffffff;
15853             }
15854           else
15855             {
15856               op = get16 ();
15857               mask = 0xfffff;
15858             }
15859           used_prefixes |= (prefixes & PREFIX_DATA);
15860         }
15861       break;
15862     case w_mode:
15863       mask = 0xfffff;
15864       op = get16 ();
15865       break;
15866     case const_1_mode:
15867       if (intel_syntax)
15868         oappend ("1");
15869       return;
15870     default:
15871       oappend (INTERNAL_DISASSEMBLER_ERROR);
15872       return;
15873     }
15874
15875   op &= mask;
15876   scratchbuf[0] = '$';
15877   print_operand_value (scratchbuf + 1, 1, op);
15878   oappend_maybe_intel (scratchbuf);
15879   scratchbuf[0] = '\0';
15880 }
15881
15882 static void
15883 OP_I64 (int bytemode, int sizeflag)
15884 {
15885   bfd_signed_vma op;
15886   bfd_signed_vma mask = -1;
15887
15888   if (address_mode != mode_64bit)
15889     {
15890       OP_I (bytemode, sizeflag);
15891       return;
15892     }
15893
15894   switch (bytemode)
15895     {
15896     case b_mode:
15897       FETCH_DATA (the_info, codep + 1);
15898       op = *codep++;
15899       mask = 0xff;
15900       break;
15901     case v_mode:
15902       USED_REX (REX_W);
15903       if (rex & REX_W)
15904         op = get64 ();
15905       else
15906         {
15907           if (sizeflag & DFLAG)
15908             {
15909               op = get32 ();
15910               mask = 0xffffffff;
15911             }
15912           else
15913             {
15914               op = get16 ();
15915               mask = 0xfffff;
15916             }
15917           used_prefixes |= (prefixes & PREFIX_DATA);
15918         }
15919       break;
15920     case w_mode:
15921       mask = 0xfffff;
15922       op = get16 ();
15923       break;
15924     default:
15925       oappend (INTERNAL_DISASSEMBLER_ERROR);
15926       return;
15927     }
15928
15929   op &= mask;
15930   scratchbuf[0] = '$';
15931   print_operand_value (scratchbuf + 1, 1, op);
15932   oappend_maybe_intel (scratchbuf);
15933   scratchbuf[0] = '\0';
15934 }
15935
15936 static void
15937 OP_sI (int bytemode, int sizeflag)
15938 {
15939   bfd_signed_vma op;
15940
15941   switch (bytemode)
15942     {
15943     case b_mode:
15944     case b_T_mode:
15945       FETCH_DATA (the_info, codep + 1);
15946       op = *codep++;
15947       if ((op & 0x80) != 0)
15948         op -= 0x100;
15949       if (bytemode == b_T_mode)
15950         {
15951           if (address_mode != mode_64bit
15952               || !((sizeflag & DFLAG) || (rex & REX_W)))
15953             {
15954               /* The operand-size prefix is overridden by a REX prefix.  */
15955               if ((sizeflag & DFLAG) || (rex & REX_W))
15956                 op &= 0xffffffff;
15957               else
15958                 op &= 0xffff;
15959           }
15960         }
15961       else
15962         {
15963           if (!(rex & REX_W))
15964             {
15965               if (sizeflag & DFLAG)
15966                 op &= 0xffffffff;
15967               else
15968                 op &= 0xffff;
15969             }
15970         }
15971       break;
15972     case v_mode:
15973       /* The operand-size prefix is overridden by a REX prefix.  */
15974       if ((sizeflag & DFLAG) || (rex & REX_W))
15975         op = get32s ();
15976       else
15977         op = get16 ();
15978       break;
15979     default:
15980       oappend (INTERNAL_DISASSEMBLER_ERROR);
15981       return;
15982     }
15983
15984   scratchbuf[0] = '$';
15985   print_operand_value (scratchbuf + 1, 1, op);
15986   oappend_maybe_intel (scratchbuf);
15987 }
15988
15989 static void
15990 OP_J (int bytemode, int sizeflag)
15991 {
15992   bfd_vma disp;
15993   bfd_vma mask = -1;
15994   bfd_vma segment = 0;
15995
15996   switch (bytemode)
15997     {
15998     case b_mode:
15999       FETCH_DATA (the_info, codep + 1);
16000       disp = *codep++;
16001       if ((disp & 0x80) != 0)
16002         disp -= 0x100;
16003       break;
16004     case v_mode:
16005       if (isa64 == amd64)
16006         USED_REX (REX_W);
16007       if ((sizeflag & DFLAG)
16008           || (address_mode == mode_64bit
16009               && (isa64 != amd64 || (rex & REX_W))))
16010         disp = get32s ();
16011       else
16012         {
16013           disp = get16 ();
16014           if ((disp & 0x8000) != 0)
16015             disp -= 0x10000;
16016           /* In 16bit mode, address is wrapped around at 64k within
16017              the same segment.  Otherwise, a data16 prefix on a jump
16018              instruction means that the pc is masked to 16 bits after
16019              the displacement is added!  */
16020           mask = 0xffff;
16021           if ((prefixes & PREFIX_DATA) == 0)
16022             segment = ((start_pc + (codep - start_codep))
16023                        & ~((bfd_vma) 0xffff));
16024         }
16025       if (address_mode != mode_64bit
16026           || (isa64 == amd64 && !(rex & REX_W)))
16027         used_prefixes |= (prefixes & PREFIX_DATA);
16028       break;
16029     default:
16030       oappend (INTERNAL_DISASSEMBLER_ERROR);
16031       return;
16032     }
16033   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16034   set_op (disp, 0);
16035   print_operand_value (scratchbuf, 1, disp);
16036   oappend (scratchbuf);
16037 }
16038
16039 static void
16040 OP_SEG (int bytemode, int sizeflag)
16041 {
16042   if (bytemode == w_mode)
16043     oappend (names_seg[modrm.reg]);
16044   else
16045     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16046 }
16047
16048 static void
16049 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16050 {
16051   int seg, offset;
16052
16053   if (sizeflag & DFLAG)
16054     {
16055       offset = get32 ();
16056       seg = get16 ();
16057     }
16058   else
16059     {
16060       offset = get16 ();
16061       seg = get16 ();
16062     }
16063   used_prefixes |= (prefixes & PREFIX_DATA);
16064   if (intel_syntax)
16065     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16066   else
16067     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16068   oappend (scratchbuf);
16069 }
16070
16071 static void
16072 OP_OFF (int bytemode, int sizeflag)
16073 {
16074   bfd_vma off;
16075
16076   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16077     intel_operand_size (bytemode, sizeflag);
16078   append_seg ();
16079
16080   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16081     off = get32 ();
16082   else
16083     off = get16 ();
16084
16085   if (intel_syntax)
16086     {
16087       if (!active_seg_prefix)
16088         {
16089           oappend (names_seg[ds_reg - es_reg]);
16090           oappend (":");
16091         }
16092     }
16093   print_operand_value (scratchbuf, 1, off);
16094   oappend (scratchbuf);
16095 }
16096
16097 static void
16098 OP_OFF64 (int bytemode, int sizeflag)
16099 {
16100   bfd_vma off;
16101
16102   if (address_mode != mode_64bit
16103       || (prefixes & PREFIX_ADDR))
16104     {
16105       OP_OFF (bytemode, sizeflag);
16106       return;
16107     }
16108
16109   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16110     intel_operand_size (bytemode, sizeflag);
16111   append_seg ();
16112
16113   off = get64 ();
16114
16115   if (intel_syntax)
16116     {
16117       if (!active_seg_prefix)
16118         {
16119           oappend (names_seg[ds_reg - es_reg]);
16120           oappend (":");
16121         }
16122     }
16123   print_operand_value (scratchbuf, 1, off);
16124   oappend (scratchbuf);
16125 }
16126
16127 static void
16128 ptr_reg (int code, int sizeflag)
16129 {
16130   const char *s;
16131
16132   *obufp++ = open_char;
16133   used_prefixes |= (prefixes & PREFIX_ADDR);
16134   if (address_mode == mode_64bit)
16135     {
16136       if (!(sizeflag & AFLAG))
16137         s = names32[code - eAX_reg];
16138       else
16139         s = names64[code - eAX_reg];
16140     }
16141   else if (sizeflag & AFLAG)
16142     s = names32[code - eAX_reg];
16143   else
16144     s = names16[code - eAX_reg];
16145   oappend (s);
16146   *obufp++ = close_char;
16147   *obufp = 0;
16148 }
16149
16150 static void
16151 OP_ESreg (int code, int sizeflag)
16152 {
16153   if (intel_syntax)
16154     {
16155       switch (codep[-1])
16156         {
16157         case 0x6d:      /* insw/insl */
16158           intel_operand_size (z_mode, sizeflag);
16159           break;
16160         case 0xa5:      /* movsw/movsl/movsq */
16161         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16162         case 0xab:      /* stosw/stosl */
16163         case 0xaf:      /* scasw/scasl */
16164           intel_operand_size (v_mode, sizeflag);
16165           break;
16166         default:
16167           intel_operand_size (b_mode, sizeflag);
16168         }
16169     }
16170   oappend_maybe_intel ("%es:");
16171   ptr_reg (code, sizeflag);
16172 }
16173
16174 static void
16175 OP_DSreg (int code, int sizeflag)
16176 {
16177   if (intel_syntax)
16178     {
16179       switch (codep[-1])
16180         {
16181         case 0x6f:      /* outsw/outsl */
16182           intel_operand_size (z_mode, sizeflag);
16183           break;
16184         case 0xa5:      /* movsw/movsl/movsq */
16185         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16186         case 0xad:      /* lodsw/lodsl/lodsq */
16187           intel_operand_size (v_mode, sizeflag);
16188           break;
16189         default:
16190           intel_operand_size (b_mode, sizeflag);
16191         }
16192     }
16193   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16194      default segment register DS is printed.  */
16195   if (!active_seg_prefix)
16196     active_seg_prefix = PREFIX_DS;
16197   append_seg ();
16198   ptr_reg (code, sizeflag);
16199 }
16200
16201 static void
16202 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16203 {
16204   int add;
16205   if (rex & REX_R)
16206     {
16207       USED_REX (REX_R);
16208       add = 8;
16209     }
16210   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16211     {
16212       all_prefixes[last_lock_prefix] = 0;
16213       used_prefixes |= PREFIX_LOCK;
16214       add = 8;
16215     }
16216   else
16217     add = 0;
16218   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16219   oappend_maybe_intel (scratchbuf);
16220 }
16221
16222 static void
16223 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16224 {
16225   int add;
16226   USED_REX (REX_R);
16227   if (rex & REX_R)
16228     add = 8;
16229   else
16230     add = 0;
16231   if (intel_syntax)
16232     sprintf (scratchbuf, "db%d", modrm.reg + add);
16233   else
16234     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16235   oappend (scratchbuf);
16236 }
16237
16238 static void
16239 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16240 {
16241   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16242   oappend_maybe_intel (scratchbuf);
16243 }
16244
16245 static void
16246 OP_R (int bytemode, int sizeflag)
16247 {
16248   /* Skip mod/rm byte.  */
16249   MODRM_CHECK;
16250   codep++;
16251   OP_E_register (bytemode, sizeflag);
16252 }
16253
16254 static void
16255 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16256 {
16257   int reg = modrm.reg;
16258   const char **names;
16259
16260   used_prefixes |= (prefixes & PREFIX_DATA);
16261   if (prefixes & PREFIX_DATA)
16262     {
16263       names = names_xmm;
16264       USED_REX (REX_R);
16265       if (rex & REX_R)
16266         reg += 8;
16267     }
16268   else
16269     names = names_mm;
16270   oappend (names[reg]);
16271 }
16272
16273 static void
16274 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16275 {
16276   int reg = modrm.reg;
16277   const char **names;
16278
16279   USED_REX (REX_R);
16280   if (rex & REX_R)
16281     reg += 8;
16282   if (vex.evex)
16283     {
16284       if (!vex.r)
16285         reg += 16;
16286     }
16287
16288   if (need_vex
16289       && bytemode != xmm_mode
16290       && bytemode != xmmq_mode
16291       && bytemode != evex_half_bcst_xmmq_mode
16292       && bytemode != ymm_mode
16293       && bytemode != scalar_mode)
16294     {
16295       switch (vex.length)
16296         {
16297         case 128:
16298           names = names_xmm;
16299           break;
16300         case 256:
16301           if (vex.w
16302               || (bytemode != vex_vsib_q_w_dq_mode
16303                   && bytemode != vex_vsib_q_w_d_mode))
16304             names = names_ymm;
16305           else
16306             names = names_xmm;
16307           break;
16308         case 512:
16309           names = names_zmm;
16310           break;
16311         default:
16312           abort ();
16313         }
16314     }
16315   else if (bytemode == xmmq_mode
16316            || bytemode == evex_half_bcst_xmmq_mode)
16317     {
16318       switch (vex.length)
16319         {
16320         case 128:
16321         case 256:
16322           names = names_xmm;
16323           break;
16324         case 512:
16325           names = names_ymm;
16326           break;
16327         default:
16328           abort ();
16329         }
16330     }
16331   else if (bytemode == ymm_mode)
16332     names = names_ymm;
16333   else
16334     names = names_xmm;
16335   oappend (names[reg]);
16336 }
16337
16338 static void
16339 OP_EM (int bytemode, int sizeflag)
16340 {
16341   int reg;
16342   const char **names;
16343
16344   if (modrm.mod != 3)
16345     {
16346       if (intel_syntax
16347           && (bytemode == v_mode || bytemode == v_swap_mode))
16348         {
16349           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16350           used_prefixes |= (prefixes & PREFIX_DATA);
16351         }
16352       OP_E (bytemode, sizeflag);
16353       return;
16354     }
16355
16356   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16357     swap_operand ();
16358
16359   /* Skip mod/rm byte.  */
16360   MODRM_CHECK;
16361   codep++;
16362   used_prefixes |= (prefixes & PREFIX_DATA);
16363   reg = modrm.rm;
16364   if (prefixes & PREFIX_DATA)
16365     {
16366       names = names_xmm;
16367       USED_REX (REX_B);
16368       if (rex & REX_B)
16369         reg += 8;
16370     }
16371   else
16372     names = names_mm;
16373   oappend (names[reg]);
16374 }
16375
16376 /* cvt* are the only instructions in sse2 which have
16377    both SSE and MMX operands and also have 0x66 prefix
16378    in their opcode. 0x66 was originally used to differentiate
16379    between SSE and MMX instruction(operands). So we have to handle the
16380    cvt* separately using OP_EMC and OP_MXC */
16381 static void
16382 OP_EMC (int bytemode, int sizeflag)
16383 {
16384   if (modrm.mod != 3)
16385     {
16386       if (intel_syntax && bytemode == v_mode)
16387         {
16388           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16389           used_prefixes |= (prefixes & PREFIX_DATA);
16390         }
16391       OP_E (bytemode, sizeflag);
16392       return;
16393     }
16394
16395   /* Skip mod/rm byte.  */
16396   MODRM_CHECK;
16397   codep++;
16398   used_prefixes |= (prefixes & PREFIX_DATA);
16399   oappend (names_mm[modrm.rm]);
16400 }
16401
16402 static void
16403 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16404 {
16405   used_prefixes |= (prefixes & PREFIX_DATA);
16406   oappend (names_mm[modrm.reg]);
16407 }
16408
16409 static void
16410 OP_EX (int bytemode, int sizeflag)
16411 {
16412   int reg;
16413   const char **names;
16414
16415   /* Skip mod/rm byte.  */
16416   MODRM_CHECK;
16417   codep++;
16418
16419   if (modrm.mod != 3)
16420     {
16421       OP_E_memory (bytemode, sizeflag);
16422       return;
16423     }
16424
16425   reg = modrm.rm;
16426   USED_REX (REX_B);
16427   if (rex & REX_B)
16428     reg += 8;
16429   if (vex.evex)
16430     {
16431       USED_REX (REX_X);
16432       if ((rex & REX_X))
16433         reg += 16;
16434     }
16435
16436   if ((sizeflag & SUFFIX_ALWAYS)
16437       && (bytemode == x_swap_mode
16438           || bytemode == d_swap_mode
16439           || bytemode == d_scalar_swap_mode
16440           || bytemode == q_swap_mode
16441           || bytemode == q_scalar_swap_mode))
16442     swap_operand ();
16443
16444   if (need_vex
16445       && bytemode != xmm_mode
16446       && bytemode != xmmdw_mode
16447       && bytemode != xmmqd_mode
16448       && bytemode != xmm_mb_mode
16449       && bytemode != xmm_mw_mode
16450       && bytemode != xmm_md_mode
16451       && bytemode != xmm_mq_mode
16452       && bytemode != xmm_mdq_mode
16453       && bytemode != xmmq_mode
16454       && bytemode != evex_half_bcst_xmmq_mode
16455       && bytemode != ymm_mode
16456       && bytemode != d_scalar_mode
16457       && bytemode != d_scalar_swap_mode
16458       && bytemode != q_scalar_mode
16459       && bytemode != q_scalar_swap_mode
16460       && bytemode != vex_scalar_w_dq_mode)
16461     {
16462       switch (vex.length)
16463         {
16464         case 128:
16465           names = names_xmm;
16466           break;
16467         case 256:
16468           names = names_ymm;
16469           break;
16470         case 512:
16471           names = names_zmm;
16472           break;
16473         default:
16474           abort ();
16475         }
16476     }
16477   else if (bytemode == xmmq_mode
16478            || bytemode == evex_half_bcst_xmmq_mode)
16479     {
16480       switch (vex.length)
16481         {
16482         case 128:
16483         case 256:
16484           names = names_xmm;
16485           break;
16486         case 512:
16487           names = names_ymm;
16488           break;
16489         default:
16490           abort ();
16491         }
16492     }
16493   else if (bytemode == ymm_mode)
16494     names = names_ymm;
16495   else
16496     names = names_xmm;
16497   oappend (names[reg]);
16498 }
16499
16500 static void
16501 OP_MS (int bytemode, int sizeflag)
16502 {
16503   if (modrm.mod == 3)
16504     OP_EM (bytemode, sizeflag);
16505   else
16506     BadOp ();
16507 }
16508
16509 static void
16510 OP_XS (int bytemode, int sizeflag)
16511 {
16512   if (modrm.mod == 3)
16513     OP_EX (bytemode, sizeflag);
16514   else
16515     BadOp ();
16516 }
16517
16518 static void
16519 OP_M (int bytemode, int sizeflag)
16520 {
16521   if (modrm.mod == 3)
16522     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16523     BadOp ();
16524   else
16525     OP_E (bytemode, sizeflag);
16526 }
16527
16528 static void
16529 OP_0f07 (int bytemode, int sizeflag)
16530 {
16531   if (modrm.mod != 3 || modrm.rm != 0)
16532     BadOp ();
16533   else
16534     OP_E (bytemode, sizeflag);
16535 }
16536
16537 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16538    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16539
16540 static void
16541 NOP_Fixup1 (int bytemode, int sizeflag)
16542 {
16543   if ((prefixes & PREFIX_DATA) != 0
16544       || (rex != 0
16545           && rex != 0x48
16546           && address_mode == mode_64bit))
16547     OP_REG (bytemode, sizeflag);
16548   else
16549     strcpy (obuf, "nop");
16550 }
16551
16552 static void
16553 NOP_Fixup2 (int bytemode, int sizeflag)
16554 {
16555   if ((prefixes & PREFIX_DATA) != 0
16556       || (rex != 0
16557           && rex != 0x48
16558           && address_mode == mode_64bit))
16559     OP_IMREG (bytemode, sizeflag);
16560 }
16561
16562 static const char *const Suffix3DNow[] = {
16563 /* 00 */        NULL,           NULL,           NULL,           NULL,
16564 /* 04 */        NULL,           NULL,           NULL,           NULL,
16565 /* 08 */        NULL,           NULL,           NULL,           NULL,
16566 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16567 /* 10 */        NULL,           NULL,           NULL,           NULL,
16568 /* 14 */        NULL,           NULL,           NULL,           NULL,
16569 /* 18 */        NULL,           NULL,           NULL,           NULL,
16570 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16571 /* 20 */        NULL,           NULL,           NULL,           NULL,
16572 /* 24 */        NULL,           NULL,           NULL,           NULL,
16573 /* 28 */        NULL,           NULL,           NULL,           NULL,
16574 /* 2C */        NULL,           NULL,           NULL,           NULL,
16575 /* 30 */        NULL,           NULL,           NULL,           NULL,
16576 /* 34 */        NULL,           NULL,           NULL,           NULL,
16577 /* 38 */        NULL,           NULL,           NULL,           NULL,
16578 /* 3C */        NULL,           NULL,           NULL,           NULL,
16579 /* 40 */        NULL,           NULL,           NULL,           NULL,
16580 /* 44 */        NULL,           NULL,           NULL,           NULL,
16581 /* 48 */        NULL,           NULL,           NULL,           NULL,
16582 /* 4C */        NULL,           NULL,           NULL,           NULL,
16583 /* 50 */        NULL,           NULL,           NULL,           NULL,
16584 /* 54 */        NULL,           NULL,           NULL,           NULL,
16585 /* 58 */        NULL,           NULL,           NULL,           NULL,
16586 /* 5C */        NULL,           NULL,           NULL,           NULL,
16587 /* 60 */        NULL,           NULL,           NULL,           NULL,
16588 /* 64 */        NULL,           NULL,           NULL,           NULL,
16589 /* 68 */        NULL,           NULL,           NULL,           NULL,
16590 /* 6C */        NULL,           NULL,           NULL,           NULL,
16591 /* 70 */        NULL,           NULL,           NULL,           NULL,
16592 /* 74 */        NULL,           NULL,           NULL,           NULL,
16593 /* 78 */        NULL,           NULL,           NULL,           NULL,
16594 /* 7C */        NULL,           NULL,           NULL,           NULL,
16595 /* 80 */        NULL,           NULL,           NULL,           NULL,
16596 /* 84 */        NULL,           NULL,           NULL,           NULL,
16597 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16598 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16599 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16600 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16601 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16602 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16603 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16604 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16605 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16606 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16607 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16608 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16609 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16610 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16611 /* C0 */        NULL,           NULL,           NULL,           NULL,
16612 /* C4 */        NULL,           NULL,           NULL,           NULL,
16613 /* C8 */        NULL,           NULL,           NULL,           NULL,
16614 /* CC */        NULL,           NULL,           NULL,           NULL,
16615 /* D0 */        NULL,           NULL,           NULL,           NULL,
16616 /* D4 */        NULL,           NULL,           NULL,           NULL,
16617 /* D8 */        NULL,           NULL,           NULL,           NULL,
16618 /* DC */        NULL,           NULL,           NULL,           NULL,
16619 /* E0 */        NULL,           NULL,           NULL,           NULL,
16620 /* E4 */        NULL,           NULL,           NULL,           NULL,
16621 /* E8 */        NULL,           NULL,           NULL,           NULL,
16622 /* EC */        NULL,           NULL,           NULL,           NULL,
16623 /* F0 */        NULL,           NULL,           NULL,           NULL,
16624 /* F4 */        NULL,           NULL,           NULL,           NULL,
16625 /* F8 */        NULL,           NULL,           NULL,           NULL,
16626 /* FC */        NULL,           NULL,           NULL,           NULL,
16627 };
16628
16629 static void
16630 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16631 {
16632   const char *mnemonic;
16633
16634   FETCH_DATA (the_info, codep + 1);
16635   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16636      place where an 8-bit immediate would normally go.  ie. the last
16637      byte of the instruction.  */
16638   obufp = mnemonicendp;
16639   mnemonic = Suffix3DNow[*codep++ & 0xff];
16640   if (mnemonic)
16641     oappend (mnemonic);
16642   else
16643     {
16644       /* Since a variable sized modrm/sib chunk is between the start
16645          of the opcode (0x0f0f) and the opcode suffix, we need to do
16646          all the modrm processing first, and don't know until now that
16647          we have a bad opcode.  This necessitates some cleaning up.  */
16648       op_out[0][0] = '\0';
16649       op_out[1][0] = '\0';
16650       BadOp ();
16651     }
16652   mnemonicendp = obufp;
16653 }
16654
16655 static struct op simd_cmp_op[] =
16656 {
16657   { STRING_COMMA_LEN ("eq") },
16658   { STRING_COMMA_LEN ("lt") },
16659   { STRING_COMMA_LEN ("le") },
16660   { STRING_COMMA_LEN ("unord") },
16661   { STRING_COMMA_LEN ("neq") },
16662   { STRING_COMMA_LEN ("nlt") },
16663   { STRING_COMMA_LEN ("nle") },
16664   { STRING_COMMA_LEN ("ord") }
16665 };
16666
16667 static void
16668 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16669 {
16670   unsigned int cmp_type;
16671
16672   FETCH_DATA (the_info, codep + 1);
16673   cmp_type = *codep++ & 0xff;
16674   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16675     {
16676       char suffix [3];
16677       char *p = mnemonicendp - 2;
16678       suffix[0] = p[0];
16679       suffix[1] = p[1];
16680       suffix[2] = '\0';
16681       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16682       mnemonicendp += simd_cmp_op[cmp_type].len;
16683     }
16684   else
16685     {
16686       /* We have a reserved extension byte.  Output it directly.  */
16687       scratchbuf[0] = '$';
16688       print_operand_value (scratchbuf + 1, 1, cmp_type);
16689       oappend_maybe_intel (scratchbuf);
16690       scratchbuf[0] = '\0';
16691     }
16692 }
16693
16694 static void
16695 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16696           int sizeflag ATTRIBUTE_UNUSED)
16697 {
16698   /* mwaitx %eax,%ecx,%ebx */
16699   if (!intel_syntax)
16700     {
16701       const char **names = (address_mode == mode_64bit
16702                             ? names64 : names32);
16703       strcpy (op_out[0], names[0]);
16704       strcpy (op_out[1], names[1]);
16705       strcpy (op_out[2], names[3]);
16706       two_source_ops = 1;
16707     }
16708   /* Skip mod/rm byte.  */
16709   MODRM_CHECK;
16710   codep++;
16711 }
16712
16713 static void
16714 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16715           int sizeflag ATTRIBUTE_UNUSED)
16716 {
16717   /* mwait %eax,%ecx  */
16718   if (!intel_syntax)
16719     {
16720       const char **names = (address_mode == mode_64bit
16721                             ? names64 : names32);
16722       strcpy (op_out[0], names[0]);
16723       strcpy (op_out[1], names[1]);
16724       two_source_ops = 1;
16725     }
16726   /* Skip mod/rm byte.  */
16727   MODRM_CHECK;
16728   codep++;
16729 }
16730
16731 static void
16732 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16733             int sizeflag ATTRIBUTE_UNUSED)
16734 {
16735   /* monitor %eax,%ecx,%edx"  */
16736   if (!intel_syntax)
16737     {
16738       const char **op1_names;
16739       const char **names = (address_mode == mode_64bit
16740                             ? names64 : names32);
16741
16742       if (!(prefixes & PREFIX_ADDR))
16743         op1_names = (address_mode == mode_16bit
16744                      ? names16 : names);
16745       else
16746         {
16747           /* Remove "addr16/addr32".  */
16748           all_prefixes[last_addr_prefix] = 0;
16749           op1_names = (address_mode != mode_32bit
16750                        ? names32 : names16);
16751           used_prefixes |= PREFIX_ADDR;
16752         }
16753       strcpy (op_out[0], op1_names[0]);
16754       strcpy (op_out[1], names[1]);
16755       strcpy (op_out[2], names[2]);
16756       two_source_ops = 1;
16757     }
16758   /* Skip mod/rm byte.  */
16759   MODRM_CHECK;
16760   codep++;
16761 }
16762
16763 static void
16764 BadOp (void)
16765 {
16766   /* Throw away prefixes and 1st. opcode byte.  */
16767   codep = insn_codep + 1;
16768   oappend ("(bad)");
16769 }
16770
16771 static void
16772 REP_Fixup (int bytemode, int sizeflag)
16773 {
16774   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16775      lods and stos.  */
16776   if (prefixes & PREFIX_REPZ)
16777     all_prefixes[last_repz_prefix] = REP_PREFIX;
16778
16779   switch (bytemode)
16780     {
16781     case al_reg:
16782     case eAX_reg:
16783     case indir_dx_reg:
16784       OP_IMREG (bytemode, sizeflag);
16785       break;
16786     case eDI_reg:
16787       OP_ESreg (bytemode, sizeflag);
16788       break;
16789     case eSI_reg:
16790       OP_DSreg (bytemode, sizeflag);
16791       break;
16792     default:
16793       abort ();
16794       break;
16795     }
16796 }
16797
16798 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16799    "bnd".  */
16800
16801 static void
16802 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16803 {
16804   if (prefixes & PREFIX_REPNZ)
16805     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16806 }
16807
16808 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16809    "notrack".  */
16810
16811 static void
16812 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16813                int sizeflag ATTRIBUTE_UNUSED)
16814 {
16815   if (active_seg_prefix == PREFIX_DS
16816       && (address_mode != mode_64bit || last_data_prefix < 0))
16817     {
16818       /* NOTRACK prefix is only valid on indirect branch instructions.
16819          NB: DATA prefix is unsupported for Intel64.  */
16820       active_seg_prefix = 0;
16821       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16822     }
16823 }
16824
16825 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16826    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16827  */
16828
16829 static void
16830 HLE_Fixup1 (int bytemode, int sizeflag)
16831 {
16832   if (modrm.mod != 3
16833       && (prefixes & PREFIX_LOCK) != 0)
16834     {
16835       if (prefixes & PREFIX_REPZ)
16836         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16837       if (prefixes & PREFIX_REPNZ)
16838         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16839     }
16840
16841   OP_E (bytemode, sizeflag);
16842 }
16843
16844 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16845    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16846  */
16847
16848 static void
16849 HLE_Fixup2 (int bytemode, int sizeflag)
16850 {
16851   if (modrm.mod != 3)
16852     {
16853       if (prefixes & PREFIX_REPZ)
16854         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16855       if (prefixes & PREFIX_REPNZ)
16856         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16857     }
16858
16859   OP_E (bytemode, sizeflag);
16860 }
16861
16862 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16863    "xrelease" for memory operand.  No check for LOCK prefix.   */
16864
16865 static void
16866 HLE_Fixup3 (int bytemode, int sizeflag)
16867 {
16868   if (modrm.mod != 3
16869       && last_repz_prefix > last_repnz_prefix
16870       && (prefixes & PREFIX_REPZ) != 0)
16871     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16872
16873   OP_E (bytemode, sizeflag);
16874 }
16875
16876 static void
16877 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16878 {
16879   USED_REX (REX_W);
16880   if (rex & REX_W)
16881     {
16882       /* Change cmpxchg8b to cmpxchg16b.  */
16883       char *p = mnemonicendp - 2;
16884       mnemonicendp = stpcpy (p, "16b");
16885       bytemode = o_mode;
16886     }
16887   else if ((prefixes & PREFIX_LOCK) != 0)
16888     {
16889       if (prefixes & PREFIX_REPZ)
16890         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16891       if (prefixes & PREFIX_REPNZ)
16892         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16893     }
16894
16895   OP_M (bytemode, sizeflag);
16896 }
16897
16898 static void
16899 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16900 {
16901   const char **names;
16902
16903   if (need_vex)
16904     {
16905       switch (vex.length)
16906         {
16907         case 128:
16908           names = names_xmm;
16909           break;
16910         case 256:
16911           names = names_ymm;
16912           break;
16913         default:
16914           abort ();
16915         }
16916     }
16917   else
16918     names = names_xmm;
16919   oappend (names[reg]);
16920 }
16921
16922 static void
16923 CRC32_Fixup (int bytemode, int sizeflag)
16924 {
16925   /* Add proper suffix to "crc32".  */
16926   char *p = mnemonicendp;
16927
16928   switch (bytemode)
16929     {
16930     case b_mode:
16931       if (intel_syntax)
16932         goto skip;
16933
16934       *p++ = 'b';
16935       break;
16936     case v_mode:
16937       if (intel_syntax)
16938         goto skip;
16939
16940       USED_REX (REX_W);
16941       if (rex & REX_W)
16942         *p++ = 'q';
16943       else
16944         {
16945           if (sizeflag & DFLAG)
16946             *p++ = 'l';
16947           else
16948             *p++ = 'w';
16949           used_prefixes |= (prefixes & PREFIX_DATA);
16950         }
16951       break;
16952     default:
16953       oappend (INTERNAL_DISASSEMBLER_ERROR);
16954       break;
16955     }
16956   mnemonicendp = p;
16957   *p = '\0';
16958
16959 skip:
16960   if (modrm.mod == 3)
16961     {
16962       int add;
16963
16964       /* Skip mod/rm byte.  */
16965       MODRM_CHECK;
16966       codep++;
16967
16968       USED_REX (REX_B);
16969       add = (rex & REX_B) ? 8 : 0;
16970       if (bytemode == b_mode)
16971         {
16972           USED_REX (0);
16973           if (rex)
16974             oappend (names8rex[modrm.rm + add]);
16975           else
16976             oappend (names8[modrm.rm + add]);
16977         }
16978       else
16979         {
16980           USED_REX (REX_W);
16981           if (rex & REX_W)
16982             oappend (names64[modrm.rm + add]);
16983           else if ((prefixes & PREFIX_DATA))
16984             oappend (names16[modrm.rm + add]);
16985           else
16986             oappend (names32[modrm.rm + add]);
16987         }
16988     }
16989   else
16990     OP_E (bytemode, sizeflag);
16991 }
16992
16993 static void
16994 FXSAVE_Fixup (int bytemode, int sizeflag)
16995 {
16996   /* Add proper suffix to "fxsave" and "fxrstor".  */
16997   USED_REX (REX_W);
16998   if (rex & REX_W)
16999     {
17000       char *p = mnemonicendp;
17001       *p++ = '6';
17002       *p++ = '4';
17003       *p = '\0';
17004       mnemonicendp = p;
17005     }
17006   OP_M (bytemode, sizeflag);
17007 }
17008
17009 static void
17010 PCMPESTR_Fixup (int bytemode, int sizeflag)
17011 {
17012   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
17013   if (!intel_syntax)
17014     {
17015       char *p = mnemonicendp;
17016
17017       USED_REX (REX_W);
17018       if (rex & REX_W)
17019         *p++ = 'q';
17020       else if (sizeflag & SUFFIX_ALWAYS)
17021         *p++ = 'l';
17022
17023       *p = '\0';
17024       mnemonicendp = p;
17025     }
17026
17027   OP_EX (bytemode, sizeflag);
17028 }
17029
17030 /* Display the destination register operand for instructions with
17031    VEX. */
17032
17033 static void
17034 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17035 {
17036   int reg;
17037   const char **names;
17038
17039   if (!need_vex)
17040     abort ();
17041
17042   if (!need_vex_reg)
17043     return;
17044
17045   reg = vex.register_specifier;
17046   if (vex.evex)
17047     {
17048       if (!vex.v)
17049         reg += 16;
17050     }
17051
17052   if (bytemode == vex_scalar_mode)
17053     {
17054       oappend (names_xmm[reg]);
17055       return;
17056     }
17057
17058   switch (vex.length)
17059     {
17060     case 128:
17061       switch (bytemode)
17062         {
17063         case vex_mode:
17064         case vex128_mode:
17065         case vex_vsib_q_w_dq_mode:
17066         case vex_vsib_q_w_d_mode:
17067           names = names_xmm;
17068           break;
17069         case dq_mode:
17070           if (vex.w)
17071             names = names64;
17072           else
17073             names = names32;
17074           break;
17075         case mask_bd_mode:
17076         case mask_mode:
17077           if (reg > 0x7)
17078             {
17079               oappend ("(bad)");
17080               return;
17081             }
17082           names = names_mask;
17083           break;
17084         default:
17085           abort ();
17086           return;
17087         }
17088       break;
17089     case 256:
17090       switch (bytemode)
17091         {
17092         case vex_mode:
17093         case vex256_mode:
17094           names = names_ymm;
17095           break;
17096         case vex_vsib_q_w_dq_mode:
17097         case vex_vsib_q_w_d_mode:
17098           names = vex.w ? names_ymm : names_xmm;
17099           break;
17100         case mask_bd_mode:
17101         case mask_mode:
17102           if (reg > 0x7)
17103             {
17104               oappend ("(bad)");
17105               return;
17106             }
17107           names = names_mask;
17108           break;
17109         default:
17110           /* See PR binutils/20893 for a reproducer.  */
17111           oappend ("(bad)");
17112           return;
17113         }
17114       break;
17115     case 512:
17116       names = names_zmm;
17117       break;
17118     default:
17119       abort ();
17120       break;
17121     }
17122   oappend (names[reg]);
17123 }
17124
17125 /* Get the VEX immediate byte without moving codep.  */
17126
17127 static unsigned char
17128 get_vex_imm8 (int sizeflag, int opnum)
17129 {
17130   int bytes_before_imm = 0;
17131
17132   if (modrm.mod != 3)
17133     {
17134       /* There are SIB/displacement bytes.  */
17135       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17136         {
17137           /* 32/64 bit address mode */
17138           int base = modrm.rm;
17139
17140           /* Check SIB byte.  */
17141           if (base == 4)
17142             {
17143               FETCH_DATA (the_info, codep + 1);
17144               base = *codep & 7;
17145               /* When decoding the third source, don't increase
17146                  bytes_before_imm as this has already been incremented
17147                  by one in OP_E_memory while decoding the second
17148                  source operand.  */
17149               if (opnum == 0)
17150                 bytes_before_imm++;
17151             }
17152
17153           /* Don't increase bytes_before_imm when decoding the third source,
17154              it has already been incremented by OP_E_memory while decoding
17155              the second source operand.  */
17156           if (opnum == 0)
17157             {
17158               switch (modrm.mod)
17159                 {
17160                   case 0:
17161                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17162                        SIB == 5, there is a 4 byte displacement.  */
17163                     if (base != 5)
17164                       /* No displacement. */
17165                       break;
17166                     /* Fall through.  */
17167                   case 2:
17168                     /* 4 byte displacement.  */
17169                     bytes_before_imm += 4;
17170                     break;
17171                   case 1:
17172                     /* 1 byte displacement.  */
17173                     bytes_before_imm++;
17174                     break;
17175                 }
17176             }
17177         }
17178       else
17179         {
17180           /* 16 bit address mode */
17181           /* Don't increase bytes_before_imm when decoding the third source,
17182              it has already been incremented by OP_E_memory while decoding
17183              the second source operand.  */
17184           if (opnum == 0)
17185             {
17186               switch (modrm.mod)
17187                 {
17188                 case 0:
17189                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17190                   if (modrm.rm != 6)
17191                     /* No displacement. */
17192                     break;
17193                   /* Fall through.  */
17194                 case 2:
17195                   /* 2 byte displacement.  */
17196                   bytes_before_imm += 2;
17197                   break;
17198                 case 1:
17199                   /* 1 byte displacement: when decoding the third source,
17200                      don't increase bytes_before_imm as this has already
17201                      been incremented by one in OP_E_memory while decoding
17202                      the second source operand.  */
17203                   if (opnum == 0)
17204                     bytes_before_imm++;
17205
17206                   break;
17207                 }
17208             }
17209         }
17210     }
17211
17212   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17213   return codep [bytes_before_imm];
17214 }
17215
17216 static void
17217 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17218 {
17219   const char **names;
17220
17221   if (reg == -1 && modrm.mod != 3)
17222     {
17223       OP_E_memory (bytemode, sizeflag);
17224       return;
17225     }
17226   else
17227     {
17228       if (reg == -1)
17229         {
17230           reg = modrm.rm;
17231           USED_REX (REX_B);
17232           if (rex & REX_B)
17233             reg += 8;
17234         }
17235       else if (reg > 7 && address_mode != mode_64bit)
17236         BadOp ();
17237     }
17238
17239   switch (vex.length)
17240     {
17241     case 128:
17242       names = names_xmm;
17243       break;
17244     case 256:
17245       names = names_ymm;
17246       break;
17247     default:
17248       abort ();
17249     }
17250   oappend (names[reg]);
17251 }
17252
17253 static void
17254 OP_EX_VexImmW (int bytemode, int sizeflag)
17255 {
17256   int reg = -1;
17257   static unsigned char vex_imm8;
17258
17259   if (vex_w_done == 0)
17260     {
17261       vex_w_done = 1;
17262
17263       /* Skip mod/rm byte.  */
17264       MODRM_CHECK;
17265       codep++;
17266
17267       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17268
17269       if (vex.w)
17270           reg = vex_imm8 >> 4;
17271
17272       OP_EX_VexReg (bytemode, sizeflag, reg);
17273     }
17274   else if (vex_w_done == 1)
17275     {
17276       vex_w_done = 2;
17277
17278       if (!vex.w)
17279           reg = vex_imm8 >> 4;
17280
17281       OP_EX_VexReg (bytemode, sizeflag, reg);
17282     }
17283   else
17284     {
17285       /* Output the imm8 directly.  */
17286       scratchbuf[0] = '$';
17287       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17288       oappend_maybe_intel (scratchbuf);
17289       scratchbuf[0] = '\0';
17290       codep++;
17291     }
17292 }
17293
17294 static void
17295 OP_Vex_2src (int bytemode, int sizeflag)
17296 {
17297   if (modrm.mod == 3)
17298     {
17299       int reg = modrm.rm;
17300       USED_REX (REX_B);
17301       if (rex & REX_B)
17302         reg += 8;
17303       oappend (names_xmm[reg]);
17304     }
17305   else
17306     {
17307       if (intel_syntax
17308           && (bytemode == v_mode || bytemode == v_swap_mode))
17309         {
17310           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17311           used_prefixes |= (prefixes & PREFIX_DATA);
17312         }
17313       OP_E (bytemode, sizeflag);
17314     }
17315 }
17316
17317 static void
17318 OP_Vex_2src_1 (int bytemode, int sizeflag)
17319 {
17320   if (modrm.mod == 3)
17321     {
17322       /* Skip mod/rm byte.   */
17323       MODRM_CHECK;
17324       codep++;
17325     }
17326
17327   if (vex.w)
17328     oappend (names_xmm[vex.register_specifier]);
17329   else
17330     OP_Vex_2src (bytemode, sizeflag);
17331 }
17332
17333 static void
17334 OP_Vex_2src_2 (int bytemode, int sizeflag)
17335 {
17336   if (vex.w)
17337     OP_Vex_2src (bytemode, sizeflag);
17338   else
17339     oappend (names_xmm[vex.register_specifier]);
17340 }
17341
17342 static void
17343 OP_EX_VexW (int bytemode, int sizeflag)
17344 {
17345   int reg = -1;
17346
17347   if (!vex_w_done)
17348     {
17349       vex_w_done = 1;
17350
17351       /* Skip mod/rm byte.  */
17352       MODRM_CHECK;
17353       codep++;
17354
17355       if (vex.w)
17356         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17357     }
17358   else
17359     {
17360       if (!vex.w)
17361         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17362     }
17363
17364   OP_EX_VexReg (bytemode, sizeflag, reg);
17365 }
17366
17367 static void
17368 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17369              int sizeflag ATTRIBUTE_UNUSED)
17370 {
17371   /* Skip the immediate byte and check for invalid bits.  */
17372   FETCH_DATA (the_info, codep + 1);
17373   if (*codep++ & 0xf)
17374     BadOp ();
17375 }
17376
17377 static void
17378 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17379 {
17380   int reg;
17381   const char **names;
17382
17383   FETCH_DATA (the_info, codep + 1);
17384   reg = *codep++;
17385
17386   if (bytemode != x_mode)
17387     abort ();
17388
17389   if (reg & 0xf)
17390       BadOp ();
17391
17392   reg >>= 4;
17393   if (reg > 7 && address_mode != mode_64bit)
17394     BadOp ();
17395
17396   switch (vex.length)
17397     {
17398     case 128:
17399       names = names_xmm;
17400       break;
17401     case 256:
17402       names = names_ymm;
17403       break;
17404     default:
17405       abort ();
17406     }
17407   oappend (names[reg]);
17408 }
17409
17410 static void
17411 OP_XMM_VexW (int bytemode, int sizeflag)
17412 {
17413   /* Turn off the REX.W bit since it is used for swapping operands
17414      now.  */
17415   rex &= ~REX_W;
17416   OP_XMM (bytemode, sizeflag);
17417 }
17418
17419 static void
17420 OP_EX_Vex (int bytemode, int sizeflag)
17421 {
17422   if (modrm.mod != 3)
17423     {
17424       if (vex.register_specifier != 0)
17425         BadOp ();
17426       need_vex_reg = 0;
17427     }
17428   OP_EX (bytemode, sizeflag);
17429 }
17430
17431 static void
17432 OP_XMM_Vex (int bytemode, int sizeflag)
17433 {
17434   if (modrm.mod != 3)
17435     {
17436       if (vex.register_specifier != 0)
17437         BadOp ();
17438       need_vex_reg = 0;
17439     }
17440   OP_XMM (bytemode, sizeflag);
17441 }
17442
17443 static void
17444 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17445 {
17446   switch (vex.length)
17447     {
17448     case 128:
17449       mnemonicendp = stpcpy (obuf, "vzeroupper");
17450       break;
17451     case 256:
17452       mnemonicendp = stpcpy (obuf, "vzeroall");
17453       break;
17454     default:
17455       abort ();
17456     }
17457 }
17458
17459 static struct op vex_cmp_op[] =
17460 {
17461   { STRING_COMMA_LEN ("eq") },
17462   { STRING_COMMA_LEN ("lt") },
17463   { STRING_COMMA_LEN ("le") },
17464   { STRING_COMMA_LEN ("unord") },
17465   { STRING_COMMA_LEN ("neq") },
17466   { STRING_COMMA_LEN ("nlt") },
17467   { STRING_COMMA_LEN ("nle") },
17468   { STRING_COMMA_LEN ("ord") },
17469   { STRING_COMMA_LEN ("eq_uq") },
17470   { STRING_COMMA_LEN ("nge") },
17471   { STRING_COMMA_LEN ("ngt") },
17472   { STRING_COMMA_LEN ("false") },
17473   { STRING_COMMA_LEN ("neq_oq") },
17474   { STRING_COMMA_LEN ("ge") },
17475   { STRING_COMMA_LEN ("gt") },
17476   { STRING_COMMA_LEN ("true") },
17477   { STRING_COMMA_LEN ("eq_os") },
17478   { STRING_COMMA_LEN ("lt_oq") },
17479   { STRING_COMMA_LEN ("le_oq") },
17480   { STRING_COMMA_LEN ("unord_s") },
17481   { STRING_COMMA_LEN ("neq_us") },
17482   { STRING_COMMA_LEN ("nlt_uq") },
17483   { STRING_COMMA_LEN ("nle_uq") },
17484   { STRING_COMMA_LEN ("ord_s") },
17485   { STRING_COMMA_LEN ("eq_us") },
17486   { STRING_COMMA_LEN ("nge_uq") },
17487   { STRING_COMMA_LEN ("ngt_uq") },
17488   { STRING_COMMA_LEN ("false_os") },
17489   { STRING_COMMA_LEN ("neq_os") },
17490   { STRING_COMMA_LEN ("ge_oq") },
17491   { STRING_COMMA_LEN ("gt_oq") },
17492   { STRING_COMMA_LEN ("true_us") },
17493 };
17494
17495 static void
17496 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17497 {
17498   unsigned int cmp_type;
17499
17500   FETCH_DATA (the_info, codep + 1);
17501   cmp_type = *codep++ & 0xff;
17502   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17503     {
17504       char suffix [3];
17505       char *p = mnemonicendp - 2;
17506       suffix[0] = p[0];
17507       suffix[1] = p[1];
17508       suffix[2] = '\0';
17509       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17510       mnemonicendp += vex_cmp_op[cmp_type].len;
17511     }
17512   else
17513     {
17514       /* We have a reserved extension byte.  Output it directly.  */
17515       scratchbuf[0] = '$';
17516       print_operand_value (scratchbuf + 1, 1, cmp_type);
17517       oappend_maybe_intel (scratchbuf);
17518       scratchbuf[0] = '\0';
17519     }
17520 }
17521
17522 static void
17523 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17524              int sizeflag ATTRIBUTE_UNUSED)
17525 {
17526   unsigned int cmp_type;
17527
17528   if (!vex.evex)
17529     abort ();
17530
17531   FETCH_DATA (the_info, codep + 1);
17532   cmp_type = *codep++ & 0xff;
17533   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17534      If it's the case, print suffix, otherwise - print the immediate.  */
17535   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17536       && cmp_type != 3
17537       && cmp_type != 7)
17538     {
17539       char suffix [3];
17540       char *p = mnemonicendp - 2;
17541
17542       /* vpcmp* can have both one- and two-lettered suffix.  */
17543       if (p[0] == 'p')
17544         {
17545           p++;
17546           suffix[0] = p[0];
17547           suffix[1] = '\0';
17548         }
17549       else
17550         {
17551           suffix[0] = p[0];
17552           suffix[1] = p[1];
17553           suffix[2] = '\0';
17554         }
17555
17556       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17557       mnemonicendp += simd_cmp_op[cmp_type].len;
17558     }
17559   else
17560     {
17561       /* We have a reserved extension byte.  Output it directly.  */
17562       scratchbuf[0] = '$';
17563       print_operand_value (scratchbuf + 1, 1, cmp_type);
17564       oappend_maybe_intel (scratchbuf);
17565       scratchbuf[0] = '\0';
17566     }
17567 }
17568
17569 static const struct op pclmul_op[] =
17570 {
17571   { STRING_COMMA_LEN ("lql") },
17572   { STRING_COMMA_LEN ("hql") },
17573   { STRING_COMMA_LEN ("lqh") },
17574   { STRING_COMMA_LEN ("hqh") }
17575 };
17576
17577 static void
17578 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17579               int sizeflag ATTRIBUTE_UNUSED)
17580 {
17581   unsigned int pclmul_type;
17582
17583   FETCH_DATA (the_info, codep + 1);
17584   pclmul_type = *codep++ & 0xff;
17585   switch (pclmul_type)
17586     {
17587     case 0x10:
17588       pclmul_type = 2;
17589       break;
17590     case 0x11:
17591       pclmul_type = 3;
17592       break;
17593     default:
17594       break;
17595     }
17596   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17597     {
17598       char suffix [4];
17599       char *p = mnemonicendp - 3;
17600       suffix[0] = p[0];
17601       suffix[1] = p[1];
17602       suffix[2] = p[2];
17603       suffix[3] = '\0';
17604       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17605       mnemonicendp += pclmul_op[pclmul_type].len;
17606     }
17607   else
17608     {
17609       /* We have a reserved extension byte.  Output it directly.  */
17610       scratchbuf[0] = '$';
17611       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17612       oappend_maybe_intel (scratchbuf);
17613       scratchbuf[0] = '\0';
17614     }
17615 }
17616
17617 static void
17618 MOVBE_Fixup (int bytemode, int sizeflag)
17619 {
17620   /* Add proper suffix to "movbe".  */
17621   char *p = mnemonicendp;
17622
17623   switch (bytemode)
17624     {
17625     case v_mode:
17626       if (intel_syntax)
17627         goto skip;
17628
17629       USED_REX (REX_W);
17630       if (sizeflag & SUFFIX_ALWAYS)
17631         {
17632           if (rex & REX_W)
17633             *p++ = 'q';
17634           else
17635             {
17636               if (sizeflag & DFLAG)
17637                 *p++ = 'l';
17638               else
17639                 *p++ = 'w';
17640               used_prefixes |= (prefixes & PREFIX_DATA);
17641             }
17642         }
17643       break;
17644     default:
17645       oappend (INTERNAL_DISASSEMBLER_ERROR);
17646       break;
17647     }
17648   mnemonicendp = p;
17649   *p = '\0';
17650
17651 skip:
17652   OP_M (bytemode, sizeflag);
17653 }
17654
17655 static void
17656 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17657 {
17658   int reg;
17659   const char **names;
17660
17661   /* Skip mod/rm byte.  */
17662   MODRM_CHECK;
17663   codep++;
17664
17665   if (vex.w)
17666     names = names64;
17667   else
17668     names = names32;
17669
17670   reg = modrm.rm;
17671   USED_REX (REX_B);
17672   if (rex & REX_B)
17673     reg += 8;
17674
17675   oappend (names[reg]);
17676 }
17677
17678 static void
17679 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17680 {
17681   const char **names;
17682
17683   if (vex.w)
17684     names = names64;
17685   else
17686     names = names32;
17687
17688   oappend (names[vex.register_specifier]);
17689 }
17690
17691 static void
17692 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17693 {
17694   if (!vex.evex
17695       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17696     abort ();
17697
17698   USED_REX (REX_R);
17699   if ((rex & REX_R) != 0 || !vex.r)
17700     {
17701       BadOp ();
17702       return;
17703     }
17704
17705   oappend (names_mask [modrm.reg]);
17706 }
17707
17708 static void
17709 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17710 {
17711   if (!vex.evex
17712       || (bytemode != evex_rounding_mode
17713           && bytemode != evex_sae_mode))
17714     abort ();
17715   if (modrm.mod == 3 && vex.b)
17716     switch (bytemode)
17717       {
17718       case evex_rounding_mode:
17719         oappend (names_rounding[vex.ll]);
17720         break;
17721       case evex_sae_mode:
17722         oappend ("{sae}");
17723         break;
17724       default:
17725         break;
17726       }
17727 }