opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void OP_Mwaitx (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   OPCODES_SIGJMP_BUF bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Edqa { OP_E, dqa_mode }
 263 #define Eq { OP_E, q_mode }
 264 #define indirEv { OP_indirE, indir_v_mode }
 265 #define indirEp { OP_indirE, f_mode }
 266 #define stackEv { OP_E, stack_v_mode }
 267 #define Em { OP_E, m_mode }
 268 #define Ew { OP_E, w_mode }
 269 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 270 #define Ma { OP_M, a_mode }
 271 #define Mb { OP_M, b_mode }
 272 #define Md { OP_M, d_mode }
 273 #define Mo { OP_M, o_mode }
 274 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 275 #define Mq { OP_M, q_mode }
 276 #define Mv_bnd { OP_M, v_bndmk_mode }
 277 #define Mx { OP_M, x_mode }
 278 #define Mxmm { OP_M, xmm_mode }
 279 #define Gb { OP_G, b_mode }
 280 #define Gbnd { OP_G, bnd_mode }
 281 #define Gv { OP_G, v_mode }
 282 #define Gd { OP_G, d_mode }
 283 #define Gdq { OP_G, dq_mode }
 284 #define Gm { OP_G, m_mode }
 285 #define Gva { OP_G, va_mode }
 286 #define Gw { OP_G, w_mode }
 287 #define Rd { OP_R, d_mode }
 288 #define Rdq { OP_R, dq_mode }
 289 #define Rm { OP_R, m_mode }
 290 #define Ib { OP_I, b_mode }
 291 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 293 #define Iv { OP_I, v_mode }
 294 #define sIv { OP_sI, v_mode }
 295 #define Iq { OP_I, q_mode }
 296 #define Iv64 { OP_I64, v_mode }
 297 #define Iw { OP_I, w_mode }
 298 #define I1 { OP_I, const_1_mode }
 299 #define Jb { OP_J, b_mode }
 300 #define Jv { OP_J, v_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXbScalar { OP_EX, b_scalar_mode }
 384 #define EXw { OP_EX, w_mode }
 385 #define EXwScalar { OP_EX, w_scalar_mode }
 386 #define EXd { OP_EX, d_mode }
 387 #define EXdScalar { OP_EX, d_scalar_mode }
 388 #define EXdS { OP_EX, d_swap_mode }
 389 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 390 #define EXq { OP_EX, q_mode }
 391 #define EXqScalar { OP_EX, q_scalar_mode }
 392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 393 #define EXqS { OP_EX, q_swap_mode }
 394 #define EXx { OP_EX, x_mode }
 395 #define EXxS { OP_EX, x_swap_mode }
 396 #define EXxmm { OP_EX, xmm_mode }
 397 #define EXymm { OP_EX, ymm_mode }
 398 #define EXxmmq { OP_EX, xmmq_mode }
 399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 402 #define EXxmm_md { OP_EX, xmm_md_mode }
 403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 405 #define EXxmmdw { OP_EX, xmmdw_mode }
 406 #define EXxmmqd { OP_EX, xmmqd_mode }
 407 #define EXymmq { OP_EX, ymmq_mode }
 408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 412 #define MS { OP_MS, v_mode }
 413 #define XS { OP_XS, v_mode }
 414 #define EMCq { OP_EMC, q_mode }
 415 #define MXC { OP_MXC, 0 }
 416 #define OPSUF { OP_3DNowSuffix, 0 }
 417 #define CMP { CMP_Fixup, 0 }
 418 #define XMM0 { XMM_Fixup, 0 }
 419 #define FXSAVE { FXSAVE_Fixup, 0 }
 420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 422
 423 #define Vex { OP_VEX, vex_mode }
 424 #define VexScalar { OP_VEX, vex_scalar_mode }
 425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 426 #define Vex128 { OP_VEX, vex128_mode }
 427 #define Vex256 { OP_VEX, vex256_mode }
 428 #define VexGdq { OP_VEX, dq_mode }
 429 #define EXdVex { OP_EX_Vex, d_mode }
 430 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 431 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 432 #define EXqVex { OP_EX_Vex, q_mode }
 433 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 434 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 435 #define EXVexW { OP_EX_VexW, x_mode }
 436 #define EXdVexW { OP_EX_VexW, d_mode }
 437 #define EXqVexW { OP_EX_VexW, q_mode }
 438 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 439 #define XMVex { OP_XMM_Vex, 0 }
 440 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 441 #define XMVexW { OP_XMM_VexW, 0 }
 442 #define XMVexI4 { OP_REG_VexI4, x_mode }
 443 #define PCLMUL { PCLMUL_Fixup, 0 }
 444 #define VCMP { VCMP_Fixup, 0 }
 445 #define VPCMP { VPCMP_Fixup, 0 }
 446 #define VPCOM { VPCOM_Fixup, 0 }
 447
 448 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 449 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 450 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 451
 452 #define XMask { OP_Mask, mask_mode }
 453 #define MaskG { OP_G, mask_mode }
 454 #define MaskE { OP_E, mask_mode }
 455 #define MaskBDE { OP_E, mask_bd_mode }
 456 #define MaskR { OP_R, mask_mode }
 457 #define MaskVex { OP_VEX, mask_mode }
 458
 459 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 460 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 461 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 462 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 463
 464 /* Used handle "rep" prefix for string instructions.  */
 465 #define Xbr { REP_Fixup, eSI_reg }
 466 #define Xvr { REP_Fixup, eSI_reg }
 467 #define Ybr { REP_Fixup, eDI_reg }
 468 #define Yvr { REP_Fixup, eDI_reg }
 469 #define Yzr { REP_Fixup, eDI_reg }
 470 #define indirDXr { REP_Fixup, indir_dx_reg }
 471 #define ALr { REP_Fixup, al_reg }
 472 #define eAXr { REP_Fixup, eAX_reg }
 473
 474 /* Used handle HLE prefix for lockable instructions.  */
 475 #define Ebh1 { HLE_Fixup1, b_mode }
 476 #define Evh1 { HLE_Fixup1, v_mode }
 477 #define Ebh2 { HLE_Fixup2, b_mode }
 478 #define Evh2 { HLE_Fixup2, v_mode }
 479 #define Ebh3 { HLE_Fixup3, b_mode }
 480 #define Evh3 { HLE_Fixup3, v_mode }
 481
 482 #define BND { BND_Fixup, 0 }
 483 #define NOTRACK { NOTRACK_Fixup, 0 }
 484
 485 #define cond_jump_flag { NULL, cond_jump_mode }
 486 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 487
 488 /* bits in sizeflag */
 489 #define SUFFIX_ALWAYS 4
 490 #define AFLAG 2
 491 #define DFLAG 1
 492
 493 enum
 494 {
 495   /* byte operand */
 496   b_mode = 1,
 497   /* byte operand with operand swapped */
 498   b_swap_mode,
 499   /* byte operand, sign extend like 'T' suffix */
 500   b_T_mode,
 501   /* operand size depends on prefixes */
 502   v_mode,
 503   /* operand size depends on prefixes with operand swapped */
 504   v_swap_mode,
 505   /* operand size depends on address prefix */
 506   va_mode,
 507   /* word operand */
 508   w_mode,
 509   /* double word operand  */
 510   d_mode,
 511   /* double word operand with operand swapped */
 512   d_swap_mode,
 513   /* quad word operand */
 514   q_mode,
 515   /* quad word operand with operand swapped */
 516   q_swap_mode,
 517   /* ten-byte operand */
 518   t_mode,
 519   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 520      broadcast enabled.  */
 521   x_mode,
 522   /* Similar to x_mode, but with different EVEX mem shifts.  */
 523   evex_x_gscat_mode,
 524   /* Similar to x_mode, but with disabled broadcast.  */
 525   evex_x_nobcst_mode,
 526   /* Similar to x_mode, but with operands swapped and disabled broadcast
 527      in EVEX.  */
 528   x_swap_mode,
 529   /* 16-byte XMM operand */
 530   xmm_mode,
 531   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 532      memory operand (depending on vector length).  Broadcast isn't
 533      allowed.  */
 534   xmmq_mode,
 535   /* Same as xmmq_mode, but broadcast is allowed.  */
 536   evex_half_bcst_xmmq_mode,
 537   /* XMM register or byte memory operand */
 538   xmm_mb_mode,
 539   /* XMM register or word memory operand */
 540   xmm_mw_mode,
 541   /* XMM register or double word memory operand */
 542   xmm_md_mode,
 543   /* XMM register or quad word memory operand */
 544   xmm_mq_mode,
 545   /* XMM register or double/quad word memory operand, depending on
 546      VEX.W.  */
 547   xmm_mdq_mode,
 548   /* 16-byte XMM, word, double word or quad word operand.  */
 549   xmmdw_mode,
 550   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 551   xmmqd_mode,
 552   /* 32-byte YMM operand */
 553   ymm_mode,
 554   /* quad word, ymmword or zmmword memory operand.  */
 555   ymmq_mode,
 556   /* 32-byte YMM or 16-byte word operand */
 557   ymmxmm_mode,
 558   /* d_mode in 32bit, q_mode in 64bit mode.  */
 559   m_mode,
 560   /* pair of v_mode operands */
 561   a_mode,
 562   cond_jump_mode,
 563   loop_jcxz_mode,
 564   v_bnd_mode,
 565   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 566   v_bndmk_mode,
 567   /* operand size depends on REX prefixes.  */
 568   dq_mode,
 569   /* registers like dq_mode, memory like w_mode.  */
 570   dqw_mode,
 571   /* bounds operand */
 572   bnd_mode,
 573   /* bounds operand with operand swapped */
 574   bnd_swap_mode,
 575   /* 4- or 6-byte pointer operand */
 576   f_mode,
 577   const_1_mode,
 578   /* v_mode for indirect branch opcodes.  */
 579   indir_v_mode,
 580   /* v_mode for stack-related opcodes.  */
 581   stack_v_mode,
 582   /* non-quad operand size depends on prefixes */
 583   z_mode,
 584   /* 16-byte operand */
 585   o_mode,
 586   /* registers like dq_mode, memory like b_mode.  */
 587   dqb_mode,
 588   /* registers like d_mode, memory like b_mode.  */
 589   db_mode,
 590   /* registers like d_mode, memory like w_mode.  */
 591   dw_mode,
 592   /* registers like dq_mode, memory like d_mode.  */
 593   dqd_mode,
 594   /* operand size depends on the W bit as well as address mode.  */
 595   dqa_mode,
 596   /* normal vex mode */
 597   vex_mode,
 598   /* 128bit vex mode */
 599   vex128_mode,
 600   /* 256bit vex mode */
 601   vex256_mode,
 602   /* operand size depends on the VEX.W bit.  */
 603   vex_w_dq_mode,
 604
 605   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 606   vex_vsib_d_w_dq_mode,
 607   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 608   vex_vsib_d_w_d_mode,
 609   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 610   vex_vsib_q_w_dq_mode,
 611   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 612   vex_vsib_q_w_d_mode,
 613
 614   /* scalar, ignore vector length.  */
 615   scalar_mode,
 616   /* like b_mode, ignore vector length.  */
 617   b_scalar_mode,
 618   /* like w_mode, ignore vector length.  */
 619   w_scalar_mode,
 620   /* like d_mode, ignore vector length.  */
 621   d_scalar_mode,
 622   /* like d_swap_mode, ignore vector length.  */
 623   d_scalar_swap_mode,
 624   /* like q_mode, ignore vector length.  */
 625   q_scalar_mode,
 626   /* like q_swap_mode, ignore vector length.  */
 627   q_scalar_swap_mode,
 628   /* like vex_mode, ignore vector length.  */
 629   vex_scalar_mode,
 630   /* like vex_w_dq_mode, ignore vector length.  */
 631   vex_scalar_w_dq_mode,
 632
 633   /* Static rounding.  */
 634   evex_rounding_mode,
 635   /* Static rounding, 64-bit mode only.  */
 636   evex_rounding_64_mode,
 637   /* Supress all exceptions.  */
 638   evex_sae_mode,
 639
 640   /* Mask register operand.  */
 641   mask_mode,
 642   /* Mask register operand.  */
 643   mask_bd_mode,
 644
 645   es_reg,
 646   cs_reg,
 647   ss_reg,
 648   ds_reg,
 649   fs_reg,
 650   gs_reg,
 651
 652   eAX_reg,
 653   eCX_reg,
 654   eDX_reg,
 655   eBX_reg,
 656   eSP_reg,
 657   eBP_reg,
 658   eSI_reg,
 659   eDI_reg,
 660
 661   al_reg,
 662   cl_reg,
 663   dl_reg,
 664   bl_reg,
 665   ah_reg,
 666   ch_reg,
 667   dh_reg,
 668   bh_reg,
 669
 670   ax_reg,
 671   cx_reg,
 672   dx_reg,
 673   bx_reg,
 674   sp_reg,
 675   bp_reg,
 676   si_reg,
 677   di_reg,
 678
 679   rAX_reg,
 680   rCX_reg,
 681   rDX_reg,
 682   rBX_reg,
 683   rSP_reg,
 684   rBP_reg,
 685   rSI_reg,
 686   rDI_reg,
 687
 688   z_mode_ax_reg,
 689   indir_dx_reg
 690 };
 691
 692 enum
 693 {
 694   FLOATCODE = 1,
 695   USE_REG_TABLE,
 696   USE_MOD_TABLE,
 697   USE_RM_TABLE,
 698   USE_PREFIX_TABLE,
 699   USE_X86_64_TABLE,
 700   USE_3BYTE_TABLE,
 701   USE_XOP_8F_TABLE,
 702   USE_VEX_C4_TABLE,
 703   USE_VEX_C5_TABLE,
 704   USE_VEX_LEN_TABLE,
 705   USE_VEX_W_TABLE,
 706   USE_EVEX_TABLE,
 707   USE_EVEX_LEN_TABLE
 708 };
 709
 710 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 711
 712 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 713 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 714 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 715 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 716 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 717 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 718 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 719 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 720 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 721 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 722 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 723 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 724 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 725 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 726 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 727 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 728
 729 enum
 730 {
 731   REG_80 = 0,
 732   REG_81,
 733   REG_83,
 734   REG_8F,
 735   REG_C0,
 736   REG_C1,
 737   REG_C6,
 738   REG_C7,
 739   REG_D0,
 740   REG_D1,
 741   REG_D2,
 742   REG_D3,
 743   REG_F6,
 744   REG_F7,
 745   REG_FE,
 746   REG_FF,
 747   REG_0F00,
 748   REG_0F01,
 749   REG_0F0D,
 750   REG_0F18,
 751   REG_0F1C_MOD_0,
 752   REG_0F1E_MOD_3,
 753   REG_0F71,
 754   REG_0F72,
 755   REG_0F73,
 756   REG_0FA6,
 757   REG_0FA7,
 758   REG_0FAE,
 759   REG_0FBA,
 760   REG_0FC7,
 761   REG_VEX_0F71,
 762   REG_VEX_0F72,
 763   REG_VEX_0F73,
 764   REG_VEX_0FAE,
 765   REG_VEX_0F38F3,
 766   REG_XOP_LWPCB,
 767   REG_XOP_LWP,
 768   REG_XOP_TBM_01,
 769   REG_XOP_TBM_02,
 770
 771   REG_EVEX_0F71,
 772   REG_EVEX_0F72,
 773   REG_EVEX_0F73,
 774   REG_EVEX_0F38C6,
 775   REG_EVEX_0F38C7
 776 };
 777
 778 enum
 779 {
 780   MOD_8D = 0,
 781   MOD_C6_REG_7,
 782   MOD_C7_REG_7,
 783   MOD_FF_REG_3,
 784   MOD_FF_REG_5,
 785   MOD_0F01_REG_0,
 786   MOD_0F01_REG_1,
 787   MOD_0F01_REG_2,
 788   MOD_0F01_REG_3,
 789   MOD_0F01_REG_5,
 790   MOD_0F01_REG_7,
 791   MOD_0F12_PREFIX_0,
 792   MOD_0F13,
 793   MOD_0F16_PREFIX_0,
 794   MOD_0F17,
 795   MOD_0F18_REG_0,
 796   MOD_0F18_REG_1,
 797   MOD_0F18_REG_2,
 798   MOD_0F18_REG_3,
 799   MOD_0F18_REG_4,
 800   MOD_0F18_REG_5,
 801   MOD_0F18_REG_6,
 802   MOD_0F18_REG_7,
 803   MOD_0F1A_PREFIX_0,
 804   MOD_0F1B_PREFIX_0,
 805   MOD_0F1B_PREFIX_1,
 806   MOD_0F1C_PREFIX_0,
 807   MOD_0F1E_PREFIX_1,
 808   MOD_0F24,
 809   MOD_0F26,
 810   MOD_0F2B_PREFIX_0,
 811   MOD_0F2B_PREFIX_1,
 812   MOD_0F2B_PREFIX_2,
 813   MOD_0F2B_PREFIX_3,
 814   MOD_0F51,
 815   MOD_0F71_REG_2,
 816   MOD_0F71_REG_4,
 817   MOD_0F71_REG_6,
 818   MOD_0F72_REG_2,
 819   MOD_0F72_REG_4,
 820   MOD_0F72_REG_6,
 821   MOD_0F73_REG_2,
 822   MOD_0F73_REG_3,
 823   MOD_0F73_REG_6,
 824   MOD_0F73_REG_7,
 825   MOD_0FAE_REG_0,
 826   MOD_0FAE_REG_1,
 827   MOD_0FAE_REG_2,
 828   MOD_0FAE_REG_3,
 829   MOD_0FAE_REG_4,
 830   MOD_0FAE_REG_5,
 831   MOD_0FAE_REG_6,
 832   MOD_0FAE_REG_7,
 833   MOD_0FB2,
 834   MOD_0FB4,
 835   MOD_0FB5,
 836   MOD_0FC3,
 837   MOD_0FC7_REG_3,
 838   MOD_0FC7_REG_4,
 839   MOD_0FC7_REG_5,
 840   MOD_0FC7_REG_6,
 841   MOD_0FC7_REG_7,
 842   MOD_0FD7,
 843   MOD_0FE7_PREFIX_2,
 844   MOD_0FF0_PREFIX_3,
 845   MOD_0F382A_PREFIX_2,
 846   MOD_0F38F5_PREFIX_2,
 847   MOD_0F38F6_PREFIX_0,
 848   MOD_0F38F8_PREFIX_2,
 849   MOD_0F38F9_PREFIX_0,
 850   MOD_62_32BIT,
 851   MOD_C4_32BIT,
 852   MOD_C5_32BIT,
 853   MOD_VEX_0F12_PREFIX_0,
 854   MOD_VEX_0F13,
 855   MOD_VEX_0F16_PREFIX_0,
 856   MOD_VEX_0F17,
 857   MOD_VEX_0F2B,
 858   MOD_VEX_W_0_0F41_P_0_LEN_1,
 859   MOD_VEX_W_1_0F41_P_0_LEN_1,
 860   MOD_VEX_W_0_0F41_P_2_LEN_1,
 861   MOD_VEX_W_1_0F41_P_2_LEN_1,
 862   MOD_VEX_W_0_0F42_P_0_LEN_1,
 863   MOD_VEX_W_1_0F42_P_0_LEN_1,
 864   MOD_VEX_W_0_0F42_P_2_LEN_1,
 865   MOD_VEX_W_1_0F42_P_2_LEN_1,
 866   MOD_VEX_W_0_0F44_P_0_LEN_1,
 867   MOD_VEX_W_1_0F44_P_0_LEN_1,
 868   MOD_VEX_W_0_0F44_P_2_LEN_1,
 869   MOD_VEX_W_1_0F44_P_2_LEN_1,
 870   MOD_VEX_W_0_0F45_P_0_LEN_1,
 871   MOD_VEX_W_1_0F45_P_0_LEN_1,
 872   MOD_VEX_W_0_0F45_P_2_LEN_1,
 873   MOD_VEX_W_1_0F45_P_2_LEN_1,
 874   MOD_VEX_W_0_0F46_P_0_LEN_1,
 875   MOD_VEX_W_1_0F46_P_0_LEN_1,
 876   MOD_VEX_W_0_0F46_P_2_LEN_1,
 877   MOD_VEX_W_1_0F46_P_2_LEN_1,
 878   MOD_VEX_W_0_0F47_P_0_LEN_1,
 879   MOD_VEX_W_1_0F47_P_0_LEN_1,
 880   MOD_VEX_W_0_0F47_P_2_LEN_1,
 881   MOD_VEX_W_1_0F47_P_2_LEN_1,
 882   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 883   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 884   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 885   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 886   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 887   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 888   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 889   MOD_VEX_0F50,
 890   MOD_VEX_0F71_REG_2,
 891   MOD_VEX_0F71_REG_4,
 892   MOD_VEX_0F71_REG_6,
 893   MOD_VEX_0F72_REG_2,
 894   MOD_VEX_0F72_REG_4,
 895   MOD_VEX_0F72_REG_6,
 896   MOD_VEX_0F73_REG_2,
 897   MOD_VEX_0F73_REG_3,
 898   MOD_VEX_0F73_REG_6,
 899   MOD_VEX_0F73_REG_7,
 900   MOD_VEX_W_0_0F91_P_0_LEN_0,
 901   MOD_VEX_W_1_0F91_P_0_LEN_0,
 902   MOD_VEX_W_0_0F91_P_2_LEN_0,
 903   MOD_VEX_W_1_0F91_P_2_LEN_0,
 904   MOD_VEX_W_0_0F92_P_0_LEN_0,
 905   MOD_VEX_W_0_0F92_P_2_LEN_0,
 906   MOD_VEX_0F92_P_3_LEN_0,
 907   MOD_VEX_W_0_0F93_P_0_LEN_0,
 908   MOD_VEX_W_0_0F93_P_2_LEN_0,
 909   MOD_VEX_0F93_P_3_LEN_0,
 910   MOD_VEX_W_0_0F98_P_0_LEN_0,
 911   MOD_VEX_W_1_0F98_P_0_LEN_0,
 912   MOD_VEX_W_0_0F98_P_2_LEN_0,
 913   MOD_VEX_W_1_0F98_P_2_LEN_0,
 914   MOD_VEX_W_0_0F99_P_0_LEN_0,
 915   MOD_VEX_W_1_0F99_P_0_LEN_0,
 916   MOD_VEX_W_0_0F99_P_2_LEN_0,
 917   MOD_VEX_W_1_0F99_P_2_LEN_0,
 918   MOD_VEX_0FAE_REG_2,
 919   MOD_VEX_0FAE_REG_3,
 920   MOD_VEX_0FD7_PREFIX_2,
 921   MOD_VEX_0FE7_PREFIX_2,
 922   MOD_VEX_0FF0_PREFIX_3,
 923   MOD_VEX_0F381A_PREFIX_2,
 924   MOD_VEX_0F382A_PREFIX_2,
 925   MOD_VEX_0F382C_PREFIX_2,
 926   MOD_VEX_0F382D_PREFIX_2,
 927   MOD_VEX_0F382E_PREFIX_2,
 928   MOD_VEX_0F382F_PREFIX_2,
 929   MOD_VEX_0F385A_PREFIX_2,
 930   MOD_VEX_0F388C_PREFIX_2,
 931   MOD_VEX_0F388E_PREFIX_2,
 932   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 933   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 934   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 935   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 936   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 937   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 938   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 939   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 940
 941   MOD_EVEX_0F10_PREFIX_1,
 942   MOD_EVEX_0F10_PREFIX_3,
 943   MOD_EVEX_0F11_PREFIX_1,
 944   MOD_EVEX_0F11_PREFIX_3,
 945   MOD_EVEX_0F12_PREFIX_0,
 946   MOD_EVEX_0F16_PREFIX_0,
 947   MOD_EVEX_0F38C6_REG_1,
 948   MOD_EVEX_0F38C6_REG_2,
 949   MOD_EVEX_0F38C6_REG_5,
 950   MOD_EVEX_0F38C6_REG_6,
 951   MOD_EVEX_0F38C7_REG_1,
 952   MOD_EVEX_0F38C7_REG_2,
 953   MOD_EVEX_0F38C7_REG_5,
 954   MOD_EVEX_0F38C7_REG_6
 955 };
 956
 957 enum
 958 {
 959   RM_C6_REG_7 = 0,
 960   RM_C7_REG_7,
 961   RM_0F01_REG_0,
 962   RM_0F01_REG_1,
 963   RM_0F01_REG_2,
 964   RM_0F01_REG_3,
 965   RM_0F01_REG_5,
 966   RM_0F01_REG_7,
 967   RM_0F1E_MOD_3_REG_7,
 968   RM_0FAE_REG_6,
 969   RM_0FAE_REG_7
 970 };
 971
 972 enum
 973 {
 974   PREFIX_90 = 0,
 975   PREFIX_MOD_0_0F01_REG_5,
 976   PREFIX_MOD_3_0F01_REG_5_RM_0,
 977   PREFIX_MOD_3_0F01_REG_5_RM_2,
 978   PREFIX_0F09,
 979   PREFIX_0F10,
 980   PREFIX_0F11,
 981   PREFIX_0F12,
 982   PREFIX_0F16,
 983   PREFIX_0F1A,
 984   PREFIX_0F1B,
 985   PREFIX_0F1C,
 986   PREFIX_0F1E,
 987   PREFIX_0F2A,
 988   PREFIX_0F2B,
 989   PREFIX_0F2C,
 990   PREFIX_0F2D,
 991   PREFIX_0F2E,
 992   PREFIX_0F2F,
 993   PREFIX_0F51,
 994   PREFIX_0F52,
 995   PREFIX_0F53,
 996   PREFIX_0F58,
 997   PREFIX_0F59,
 998   PREFIX_0F5A,
 999   PREFIX_0F5B,
1000   PREFIX_0F5C,
1001   PREFIX_0F5D,
1002   PREFIX_0F5E,
1003   PREFIX_0F5F,
1004   PREFIX_0F60,
1005   PREFIX_0F61,
1006   PREFIX_0F62,
1007   PREFIX_0F6C,
1008   PREFIX_0F6D,
1009   PREFIX_0F6F,
1010   PREFIX_0F70,
1011   PREFIX_0F73_REG_3,
1012   PREFIX_0F73_REG_7,
1013   PREFIX_0F78,
1014   PREFIX_0F79,
1015   PREFIX_0F7C,
1016   PREFIX_0F7D,
1017   PREFIX_0F7E,
1018   PREFIX_0F7F,
1019   PREFIX_0FAE_REG_0,
1020   PREFIX_0FAE_REG_1,
1021   PREFIX_0FAE_REG_2,
1022   PREFIX_0FAE_REG_3,
1023   PREFIX_MOD_0_0FAE_REG_4,
1024   PREFIX_MOD_3_0FAE_REG_4,
1025   PREFIX_MOD_0_0FAE_REG_5,
1026   PREFIX_MOD_3_0FAE_REG_5,
1027   PREFIX_MOD_0_0FAE_REG_6,
1028   PREFIX_MOD_1_0FAE_REG_6,
1029   PREFIX_0FAE_REG_7,
1030   PREFIX_0FB8,
1031   PREFIX_0FBC,
1032   PREFIX_0FBD,
1033   PREFIX_0FC2,
1034   PREFIX_MOD_0_0FC3,
1035   PREFIX_MOD_0_0FC7_REG_6,
1036   PREFIX_MOD_3_0FC7_REG_6,
1037   PREFIX_MOD_3_0FC7_REG_7,
1038   PREFIX_0FD0,
1039   PREFIX_0FD6,
1040   PREFIX_0FE6,
1041   PREFIX_0FE7,
1042   PREFIX_0FF0,
1043   PREFIX_0FF7,
1044   PREFIX_0F3810,
1045   PREFIX_0F3814,
1046   PREFIX_0F3815,
1047   PREFIX_0F3817,
1048   PREFIX_0F3820,
1049   PREFIX_0F3821,
1050   PREFIX_0F3822,
1051   PREFIX_0F3823,
1052   PREFIX_0F3824,
1053   PREFIX_0F3825,
1054   PREFIX_0F3828,
1055   PREFIX_0F3829,
1056   PREFIX_0F382A,
1057   PREFIX_0F382B,
1058   PREFIX_0F3830,
1059   PREFIX_0F3831,
1060   PREFIX_0F3832,
1061   PREFIX_0F3833,
1062   PREFIX_0F3834,
1063   PREFIX_0F3835,
1064   PREFIX_0F3837,
1065   PREFIX_0F3838,
1066   PREFIX_0F3839,
1067   PREFIX_0F383A,
1068   PREFIX_0F383B,
1069   PREFIX_0F383C,
1070   PREFIX_0F383D,
1071   PREFIX_0F383E,
1072   PREFIX_0F383F,
1073   PREFIX_0F3840,
1074   PREFIX_0F3841,
1075   PREFIX_0F3880,
1076   PREFIX_0F3881,
1077   PREFIX_0F3882,
1078   PREFIX_0F38C8,
1079   PREFIX_0F38C9,
1080   PREFIX_0F38CA,
1081   PREFIX_0F38CB,
1082   PREFIX_0F38CC,
1083   PREFIX_0F38CD,
1084   PREFIX_0F38CF,
1085   PREFIX_0F38DB,
1086   PREFIX_0F38DC,
1087   PREFIX_0F38DD,
1088   PREFIX_0F38DE,
1089   PREFIX_0F38DF,
1090   PREFIX_0F38F0,
1091   PREFIX_0F38F1,
1092   PREFIX_0F38F5,
1093   PREFIX_0F38F6,
1094   PREFIX_0F38F8,
1095   PREFIX_0F38F9,
1096   PREFIX_0F3A08,
1097   PREFIX_0F3A09,
1098   PREFIX_0F3A0A,
1099   PREFIX_0F3A0B,
1100   PREFIX_0F3A0C,
1101   PREFIX_0F3A0D,
1102   PREFIX_0F3A0E,
1103   PREFIX_0F3A14,
1104   PREFIX_0F3A15,
1105   PREFIX_0F3A16,
1106   PREFIX_0F3A17,
1107   PREFIX_0F3A20,
1108   PREFIX_0F3A21,
1109   PREFIX_0F3A22,
1110   PREFIX_0F3A40,
1111   PREFIX_0F3A41,
1112   PREFIX_0F3A42,
1113   PREFIX_0F3A44,
1114   PREFIX_0F3A60,
1115   PREFIX_0F3A61,
1116   PREFIX_0F3A62,
1117   PREFIX_0F3A63,
1118   PREFIX_0F3ACC,
1119   PREFIX_0F3ACE,
1120   PREFIX_0F3ACF,
1121   PREFIX_0F3ADF,
1122   PREFIX_VEX_0F10,
1123   PREFIX_VEX_0F11,
1124   PREFIX_VEX_0F12,
1125   PREFIX_VEX_0F16,
1126   PREFIX_VEX_0F2A,
1127   PREFIX_VEX_0F2C,
1128   PREFIX_VEX_0F2D,
1129   PREFIX_VEX_0F2E,
1130   PREFIX_VEX_0F2F,
1131   PREFIX_VEX_0F41,
1132   PREFIX_VEX_0F42,
1133   PREFIX_VEX_0F44,
1134   PREFIX_VEX_0F45,
1135   PREFIX_VEX_0F46,
1136   PREFIX_VEX_0F47,
1137   PREFIX_VEX_0F4A,
1138   PREFIX_VEX_0F4B,
1139   PREFIX_VEX_0F51,
1140   PREFIX_VEX_0F52,
1141   PREFIX_VEX_0F53,
1142   PREFIX_VEX_0F58,
1143   PREFIX_VEX_0F59,
1144   PREFIX_VEX_0F5A,
1145   PREFIX_VEX_0F5B,
1146   PREFIX_VEX_0F5C,
1147   PREFIX_VEX_0F5D,
1148   PREFIX_VEX_0F5E,
1149   PREFIX_VEX_0F5F,
1150   PREFIX_VEX_0F60,
1151   PREFIX_VEX_0F61,
1152   PREFIX_VEX_0F62,
1153   PREFIX_VEX_0F63,
1154   PREFIX_VEX_0F64,
1155   PREFIX_VEX_0F65,
1156   PREFIX_VEX_0F66,
1157   PREFIX_VEX_0F67,
1158   PREFIX_VEX_0F68,
1159   PREFIX_VEX_0F69,
1160   PREFIX_VEX_0F6A,
1161   PREFIX_VEX_0F6B,
1162   PREFIX_VEX_0F6C,
1163   PREFIX_VEX_0F6D,
1164   PREFIX_VEX_0F6E,
1165   PREFIX_VEX_0F6F,
1166   PREFIX_VEX_0F70,
1167   PREFIX_VEX_0F71_REG_2,
1168   PREFIX_VEX_0F71_REG_4,
1169   PREFIX_VEX_0F71_REG_6,
1170   PREFIX_VEX_0F72_REG_2,
1171   PREFIX_VEX_0F72_REG_4,
1172   PREFIX_VEX_0F72_REG_6,
1173   PREFIX_VEX_0F73_REG_2,
1174   PREFIX_VEX_0F73_REG_3,
1175   PREFIX_VEX_0F73_REG_6,
1176   PREFIX_VEX_0F73_REG_7,
1177   PREFIX_VEX_0F74,
1178   PREFIX_VEX_0F75,
1179   PREFIX_VEX_0F76,
1180   PREFIX_VEX_0F77,
1181   PREFIX_VEX_0F7C,
1182   PREFIX_VEX_0F7D,
1183   PREFIX_VEX_0F7E,
1184   PREFIX_VEX_0F7F,
1185   PREFIX_VEX_0F90,
1186   PREFIX_VEX_0F91,
1187   PREFIX_VEX_0F92,
1188   PREFIX_VEX_0F93,
1189   PREFIX_VEX_0F98,
1190   PREFIX_VEX_0F99,
1191   PREFIX_VEX_0FC2,
1192   PREFIX_VEX_0FC4,
1193   PREFIX_VEX_0FC5,
1194   PREFIX_VEX_0FD0,
1195   PREFIX_VEX_0FD1,
1196   PREFIX_VEX_0FD2,
1197   PREFIX_VEX_0FD3,
1198   PREFIX_VEX_0FD4,
1199   PREFIX_VEX_0FD5,
1200   PREFIX_VEX_0FD6,
1201   PREFIX_VEX_0FD7,
1202   PREFIX_VEX_0FD8,
1203   PREFIX_VEX_0FD9,
1204   PREFIX_VEX_0FDA,
1205   PREFIX_VEX_0FDB,
1206   PREFIX_VEX_0FDC,
1207   PREFIX_VEX_0FDD,
1208   PREFIX_VEX_0FDE,
1209   PREFIX_VEX_0FDF,
1210   PREFIX_VEX_0FE0,
1211   PREFIX_VEX_0FE1,
1212   PREFIX_VEX_0FE2,
1213   PREFIX_VEX_0FE3,
1214   PREFIX_VEX_0FE4,
1215   PREFIX_VEX_0FE5,
1216   PREFIX_VEX_0FE6,
1217   PREFIX_VEX_0FE7,
1218   PREFIX_VEX_0FE8,
1219   PREFIX_VEX_0FE9,
1220   PREFIX_VEX_0FEA,
1221   PREFIX_VEX_0FEB,
1222   PREFIX_VEX_0FEC,
1223   PREFIX_VEX_0FED,
1224   PREFIX_VEX_0FEE,
1225   PREFIX_VEX_0FEF,
1226   PREFIX_VEX_0FF0,
1227   PREFIX_VEX_0FF1,
1228   PREFIX_VEX_0FF2,
1229   PREFIX_VEX_0FF3,
1230   PREFIX_VEX_0FF4,
1231   PREFIX_VEX_0FF5,
1232   PREFIX_VEX_0FF6,
1233   PREFIX_VEX_0FF7,
1234   PREFIX_VEX_0FF8,
1235   PREFIX_VEX_0FF9,
1236   PREFIX_VEX_0FFA,
1237   PREFIX_VEX_0FFB,
1238   PREFIX_VEX_0FFC,
1239   PREFIX_VEX_0FFD,
1240   PREFIX_VEX_0FFE,
1241   PREFIX_VEX_0F3800,
1242   PREFIX_VEX_0F3801,
1243   PREFIX_VEX_0F3802,
1244   PREFIX_VEX_0F3803,
1245   PREFIX_VEX_0F3804,
1246   PREFIX_VEX_0F3805,
1247   PREFIX_VEX_0F3806,
1248   PREFIX_VEX_0F3807,
1249   PREFIX_VEX_0F3808,
1250   PREFIX_VEX_0F3809,
1251   PREFIX_VEX_0F380A,
1252   PREFIX_VEX_0F380B,
1253   PREFIX_VEX_0F380C,
1254   PREFIX_VEX_0F380D,
1255   PREFIX_VEX_0F380E,
1256   PREFIX_VEX_0F380F,
1257   PREFIX_VEX_0F3813,
1258   PREFIX_VEX_0F3816,
1259   PREFIX_VEX_0F3817,
1260   PREFIX_VEX_0F3818,
1261   PREFIX_VEX_0F3819,
1262   PREFIX_VEX_0F381A,
1263   PREFIX_VEX_0F381C,
1264   PREFIX_VEX_0F381D,
1265   PREFIX_VEX_0F381E,
1266   PREFIX_VEX_0F3820,
1267   PREFIX_VEX_0F3821,
1268   PREFIX_VEX_0F3822,
1269   PREFIX_VEX_0F3823,
1270   PREFIX_VEX_0F3824,
1271   PREFIX_VEX_0F3825,
1272   PREFIX_VEX_0F3828,
1273   PREFIX_VEX_0F3829,
1274   PREFIX_VEX_0F382A,
1275   PREFIX_VEX_0F382B,
1276   PREFIX_VEX_0F382C,
1277   PREFIX_VEX_0F382D,
1278   PREFIX_VEX_0F382E,
1279   PREFIX_VEX_0F382F,
1280   PREFIX_VEX_0F3830,
1281   PREFIX_VEX_0F3831,
1282   PREFIX_VEX_0F3832,
1283   PREFIX_VEX_0F3833,
1284   PREFIX_VEX_0F3834,
1285   PREFIX_VEX_0F3835,
1286   PREFIX_VEX_0F3836,
1287   PREFIX_VEX_0F3837,
1288   PREFIX_VEX_0F3838,
1289   PREFIX_VEX_0F3839,
1290   PREFIX_VEX_0F383A,
1291   PREFIX_VEX_0F383B,
1292   PREFIX_VEX_0F383C,
1293   PREFIX_VEX_0F383D,
1294   PREFIX_VEX_0F383E,
1295   PREFIX_VEX_0F383F,
1296   PREFIX_VEX_0F3840,
1297   PREFIX_VEX_0F3841,
1298   PREFIX_VEX_0F3845,
1299   PREFIX_VEX_0F3846,
1300   PREFIX_VEX_0F3847,
1301   PREFIX_VEX_0F3858,
1302   PREFIX_VEX_0F3859,
1303   PREFIX_VEX_0F385A,
1304   PREFIX_VEX_0F3878,
1305   PREFIX_VEX_0F3879,
1306   PREFIX_VEX_0F388C,
1307   PREFIX_VEX_0F388E,
1308   PREFIX_VEX_0F3890,
1309   PREFIX_VEX_0F3891,
1310   PREFIX_VEX_0F3892,
1311   PREFIX_VEX_0F3893,
1312   PREFIX_VEX_0F3896,
1313   PREFIX_VEX_0F3897,
1314   PREFIX_VEX_0F3898,
1315   PREFIX_VEX_0F3899,
1316   PREFIX_VEX_0F389A,
1317   PREFIX_VEX_0F389B,
1318   PREFIX_VEX_0F389C,
1319   PREFIX_VEX_0F389D,
1320   PREFIX_VEX_0F389E,
1321   PREFIX_VEX_0F389F,
1322   PREFIX_VEX_0F38A6,
1323   PREFIX_VEX_0F38A7,
1324   PREFIX_VEX_0F38A8,
1325   PREFIX_VEX_0F38A9,
1326   PREFIX_VEX_0F38AA,
1327   PREFIX_VEX_0F38AB,
1328   PREFIX_VEX_0F38AC,
1329   PREFIX_VEX_0F38AD,
1330   PREFIX_VEX_0F38AE,
1331   PREFIX_VEX_0F38AF,
1332   PREFIX_VEX_0F38B6,
1333   PREFIX_VEX_0F38B7,
1334   PREFIX_VEX_0F38B8,
1335   PREFIX_VEX_0F38B9,
1336   PREFIX_VEX_0F38BA,
1337   PREFIX_VEX_0F38BB,
1338   PREFIX_VEX_0F38BC,
1339   PREFIX_VEX_0F38BD,
1340   PREFIX_VEX_0F38BE,
1341   PREFIX_VEX_0F38BF,
1342   PREFIX_VEX_0F38CF,
1343   PREFIX_VEX_0F38DB,
1344   PREFIX_VEX_0F38DC,
1345   PREFIX_VEX_0F38DD,
1346   PREFIX_VEX_0F38DE,
1347   PREFIX_VEX_0F38DF,
1348   PREFIX_VEX_0F38F2,
1349   PREFIX_VEX_0F38F3_REG_1,
1350   PREFIX_VEX_0F38F3_REG_2,
1351   PREFIX_VEX_0F38F3_REG_3,
1352   PREFIX_VEX_0F38F5,
1353   PREFIX_VEX_0F38F6,
1354   PREFIX_VEX_0F38F7,
1355   PREFIX_VEX_0F3A00,
1356   PREFIX_VEX_0F3A01,
1357   PREFIX_VEX_0F3A02,
1358   PREFIX_VEX_0F3A04,
1359   PREFIX_VEX_0F3A05,
1360   PREFIX_VEX_0F3A06,
1361   PREFIX_VEX_0F3A08,
1362   PREFIX_VEX_0F3A09,
1363   PREFIX_VEX_0F3A0A,
1364   PREFIX_VEX_0F3A0B,
1365   PREFIX_VEX_0F3A0C,
1366   PREFIX_VEX_0F3A0D,
1367   PREFIX_VEX_0F3A0E,
1368   PREFIX_VEX_0F3A0F,
1369   PREFIX_VEX_0F3A14,
1370   PREFIX_VEX_0F3A15,
1371   PREFIX_VEX_0F3A16,
1372   PREFIX_VEX_0F3A17,
1373   PREFIX_VEX_0F3A18,
1374   PREFIX_VEX_0F3A19,
1375   PREFIX_VEX_0F3A1D,
1376   PREFIX_VEX_0F3A20,
1377   PREFIX_VEX_0F3A21,
1378   PREFIX_VEX_0F3A22,
1379   PREFIX_VEX_0F3A30,
1380   PREFIX_VEX_0F3A31,
1381   PREFIX_VEX_0F3A32,
1382   PREFIX_VEX_0F3A33,
1383   PREFIX_VEX_0F3A38,
1384   PREFIX_VEX_0F3A39,
1385   PREFIX_VEX_0F3A40,
1386   PREFIX_VEX_0F3A41,
1387   PREFIX_VEX_0F3A42,
1388   PREFIX_VEX_0F3A44,
1389   PREFIX_VEX_0F3A46,
1390   PREFIX_VEX_0F3A48,
1391   PREFIX_VEX_0F3A49,
1392   PREFIX_VEX_0F3A4A,
1393   PREFIX_VEX_0F3A4B,
1394   PREFIX_VEX_0F3A4C,
1395   PREFIX_VEX_0F3A5C,
1396   PREFIX_VEX_0F3A5D,
1397   PREFIX_VEX_0F3A5E,
1398   PREFIX_VEX_0F3A5F,
1399   PREFIX_VEX_0F3A60,
1400   PREFIX_VEX_0F3A61,
1401   PREFIX_VEX_0F3A62,
1402   PREFIX_VEX_0F3A63,
1403   PREFIX_VEX_0F3A68,
1404   PREFIX_VEX_0F3A69,
1405   PREFIX_VEX_0F3A6A,
1406   PREFIX_VEX_0F3A6B,
1407   PREFIX_VEX_0F3A6C,
1408   PREFIX_VEX_0F3A6D,
1409   PREFIX_VEX_0F3A6E,
1410   PREFIX_VEX_0F3A6F,
1411   PREFIX_VEX_0F3A78,
1412   PREFIX_VEX_0F3A79,
1413   PREFIX_VEX_0F3A7A,
1414   PREFIX_VEX_0F3A7B,
1415   PREFIX_VEX_0F3A7C,
1416   PREFIX_VEX_0F3A7D,
1417   PREFIX_VEX_0F3A7E,
1418   PREFIX_VEX_0F3A7F,
1419   PREFIX_VEX_0F3ACE,
1420   PREFIX_VEX_0F3ACF,
1421   PREFIX_VEX_0F3ADF,
1422   PREFIX_VEX_0F3AF0,
1423
1424   PREFIX_EVEX_0F10,
1425   PREFIX_EVEX_0F11,
1426   PREFIX_EVEX_0F12,
1427   PREFIX_EVEX_0F13,
1428   PREFIX_EVEX_0F14,
1429   PREFIX_EVEX_0F15,
1430   PREFIX_EVEX_0F16,
1431   PREFIX_EVEX_0F17,
1432   PREFIX_EVEX_0F28,
1433   PREFIX_EVEX_0F29,
1434   PREFIX_EVEX_0F2A,
1435   PREFIX_EVEX_0F2B,
1436   PREFIX_EVEX_0F2C,
1437   PREFIX_EVEX_0F2D,
1438   PREFIX_EVEX_0F2E,
1439   PREFIX_EVEX_0F2F,
1440   PREFIX_EVEX_0F51,
1441   PREFIX_EVEX_0F54,
1442   PREFIX_EVEX_0F55,
1443   PREFIX_EVEX_0F56,
1444   PREFIX_EVEX_0F57,
1445   PREFIX_EVEX_0F58,
1446   PREFIX_EVEX_0F59,
1447   PREFIX_EVEX_0F5A,
1448   PREFIX_EVEX_0F5B,
1449   PREFIX_EVEX_0F5C,
1450   PREFIX_EVEX_0F5D,
1451   PREFIX_EVEX_0F5E,
1452   PREFIX_EVEX_0F5F,
1453   PREFIX_EVEX_0F60,
1454   PREFIX_EVEX_0F61,
1455   PREFIX_EVEX_0F62,
1456   PREFIX_EVEX_0F63,
1457   PREFIX_EVEX_0F64,
1458   PREFIX_EVEX_0F65,
1459   PREFIX_EVEX_0F66,
1460   PREFIX_EVEX_0F67,
1461   PREFIX_EVEX_0F68,
1462   PREFIX_EVEX_0F69,
1463   PREFIX_EVEX_0F6A,
1464   PREFIX_EVEX_0F6B,
1465   PREFIX_EVEX_0F6C,
1466   PREFIX_EVEX_0F6D,
1467   PREFIX_EVEX_0F6E,
1468   PREFIX_EVEX_0F6F,
1469   PREFIX_EVEX_0F70,
1470   PREFIX_EVEX_0F71_REG_2,
1471   PREFIX_EVEX_0F71_REG_4,
1472   PREFIX_EVEX_0F71_REG_6,
1473   PREFIX_EVEX_0F72_REG_0,
1474   PREFIX_EVEX_0F72_REG_1,
1475   PREFIX_EVEX_0F72_REG_2,
1476   PREFIX_EVEX_0F72_REG_4,
1477   PREFIX_EVEX_0F72_REG_6,
1478   PREFIX_EVEX_0F73_REG_2,
1479   PREFIX_EVEX_0F73_REG_3,
1480   PREFIX_EVEX_0F73_REG_6,
1481   PREFIX_EVEX_0F73_REG_7,
1482   PREFIX_EVEX_0F74,
1483   PREFIX_EVEX_0F75,
1484   PREFIX_EVEX_0F76,
1485   PREFIX_EVEX_0F78,
1486   PREFIX_EVEX_0F79,
1487   PREFIX_EVEX_0F7A,
1488   PREFIX_EVEX_0F7B,
1489   PREFIX_EVEX_0F7E,
1490   PREFIX_EVEX_0F7F,
1491   PREFIX_EVEX_0FC2,
1492   PREFIX_EVEX_0FC4,
1493   PREFIX_EVEX_0FC5,
1494   PREFIX_EVEX_0FC6,
1495   PREFIX_EVEX_0FD1,
1496   PREFIX_EVEX_0FD2,
1497   PREFIX_EVEX_0FD3,
1498   PREFIX_EVEX_0FD4,
1499   PREFIX_EVEX_0FD5,
1500   PREFIX_EVEX_0FD6,
1501   PREFIX_EVEX_0FD8,
1502   PREFIX_EVEX_0FD9,
1503   PREFIX_EVEX_0FDA,
1504   PREFIX_EVEX_0FDB,
1505   PREFIX_EVEX_0FDC,
1506   PREFIX_EVEX_0FDD,
1507   PREFIX_EVEX_0FDE,
1508   PREFIX_EVEX_0FDF,
1509   PREFIX_EVEX_0FE0,
1510   PREFIX_EVEX_0FE1,
1511   PREFIX_EVEX_0FE2,
1512   PREFIX_EVEX_0FE3,
1513   PREFIX_EVEX_0FE4,
1514   PREFIX_EVEX_0FE5,
1515   PREFIX_EVEX_0FE6,
1516   PREFIX_EVEX_0FE7,
1517   PREFIX_EVEX_0FE8,
1518   PREFIX_EVEX_0FE9,
1519   PREFIX_EVEX_0FEA,
1520   PREFIX_EVEX_0FEB,
1521   PREFIX_EVEX_0FEC,
1522   PREFIX_EVEX_0FED,
1523   PREFIX_EVEX_0FEE,
1524   PREFIX_EVEX_0FEF,
1525   PREFIX_EVEX_0FF1,
1526   PREFIX_EVEX_0FF2,
1527   PREFIX_EVEX_0FF3,
1528   PREFIX_EVEX_0FF4,
1529   PREFIX_EVEX_0FF5,
1530   PREFIX_EVEX_0FF6,
1531   PREFIX_EVEX_0FF8,
1532   PREFIX_EVEX_0FF9,
1533   PREFIX_EVEX_0FFA,
1534   PREFIX_EVEX_0FFB,
1535   PREFIX_EVEX_0FFC,
1536   PREFIX_EVEX_0FFD,
1537   PREFIX_EVEX_0FFE,
1538   PREFIX_EVEX_0F3800,
1539   PREFIX_EVEX_0F3804,
1540   PREFIX_EVEX_0F380B,
1541   PREFIX_EVEX_0F380C,
1542   PREFIX_EVEX_0F380D,
1543   PREFIX_EVEX_0F3810,
1544   PREFIX_EVEX_0F3811,
1545   PREFIX_EVEX_0F3812,
1546   PREFIX_EVEX_0F3813,
1547   PREFIX_EVEX_0F3814,
1548   PREFIX_EVEX_0F3815,
1549   PREFIX_EVEX_0F3816,
1550   PREFIX_EVEX_0F3818,
1551   PREFIX_EVEX_0F3819,
1552   PREFIX_EVEX_0F381A,
1553   PREFIX_EVEX_0F381B,
1554   PREFIX_EVEX_0F381C,
1555   PREFIX_EVEX_0F381D,
1556   PREFIX_EVEX_0F381E,
1557   PREFIX_EVEX_0F381F,
1558   PREFIX_EVEX_0F3820,
1559   PREFIX_EVEX_0F3821,
1560   PREFIX_EVEX_0F3822,
1561   PREFIX_EVEX_0F3823,
1562   PREFIX_EVEX_0F3824,
1563   PREFIX_EVEX_0F3825,
1564   PREFIX_EVEX_0F3826,
1565   PREFIX_EVEX_0F3827,
1566   PREFIX_EVEX_0F3828,
1567   PREFIX_EVEX_0F3829,
1568   PREFIX_EVEX_0F382A,
1569   PREFIX_EVEX_0F382B,
1570   PREFIX_EVEX_0F382C,
1571   PREFIX_EVEX_0F382D,
1572   PREFIX_EVEX_0F3830,
1573   PREFIX_EVEX_0F3831,
1574   PREFIX_EVEX_0F3832,
1575   PREFIX_EVEX_0F3833,
1576   PREFIX_EVEX_0F3834,
1577   PREFIX_EVEX_0F3835,
1578   PREFIX_EVEX_0F3836,
1579   PREFIX_EVEX_0F3837,
1580   PREFIX_EVEX_0F3838,
1581   PREFIX_EVEX_0F3839,
1582   PREFIX_EVEX_0F383A,
1583   PREFIX_EVEX_0F383B,
1584   PREFIX_EVEX_0F383C,
1585   PREFIX_EVEX_0F383D,
1586   PREFIX_EVEX_0F383E,
1587   PREFIX_EVEX_0F383F,
1588   PREFIX_EVEX_0F3840,
1589   PREFIX_EVEX_0F3842,
1590   PREFIX_EVEX_0F3843,
1591   PREFIX_EVEX_0F3844,
1592   PREFIX_EVEX_0F3845,
1593   PREFIX_EVEX_0F3846,
1594   PREFIX_EVEX_0F3847,
1595   PREFIX_EVEX_0F384C,
1596   PREFIX_EVEX_0F384D,
1597   PREFIX_EVEX_0F384E,
1598   PREFIX_EVEX_0F384F,
1599   PREFIX_EVEX_0F3850,
1600   PREFIX_EVEX_0F3851,
1601   PREFIX_EVEX_0F3852,
1602   PREFIX_EVEX_0F3853,
1603   PREFIX_EVEX_0F3854,
1604   PREFIX_EVEX_0F3855,
1605   PREFIX_EVEX_0F3858,
1606   PREFIX_EVEX_0F3859,
1607   PREFIX_EVEX_0F385A,
1608   PREFIX_EVEX_0F385B,
1609   PREFIX_EVEX_0F3862,
1610   PREFIX_EVEX_0F3863,
1611   PREFIX_EVEX_0F3864,
1612   PREFIX_EVEX_0F3865,
1613   PREFIX_EVEX_0F3866,
1614   PREFIX_EVEX_0F3870,
1615   PREFIX_EVEX_0F3871,
1616   PREFIX_EVEX_0F3872,
1617   PREFIX_EVEX_0F3873,
1618   PREFIX_EVEX_0F3875,
1619   PREFIX_EVEX_0F3876,
1620   PREFIX_EVEX_0F3877,
1621   PREFIX_EVEX_0F3878,
1622   PREFIX_EVEX_0F3879,
1623   PREFIX_EVEX_0F387A,
1624   PREFIX_EVEX_0F387B,
1625   PREFIX_EVEX_0F387C,
1626   PREFIX_EVEX_0F387D,
1627   PREFIX_EVEX_0F387E,
1628   PREFIX_EVEX_0F387F,
1629   PREFIX_EVEX_0F3883,
1630   PREFIX_EVEX_0F3888,
1631   PREFIX_EVEX_0F3889,
1632   PREFIX_EVEX_0F388A,
1633   PREFIX_EVEX_0F388B,
1634   PREFIX_EVEX_0F388D,
1635   PREFIX_EVEX_0F388F,
1636   PREFIX_EVEX_0F3890,
1637   PREFIX_EVEX_0F3891,
1638   PREFIX_EVEX_0F3892,
1639   PREFIX_EVEX_0F3893,
1640   PREFIX_EVEX_0F3896,
1641   PREFIX_EVEX_0F3897,
1642   PREFIX_EVEX_0F3898,
1643   PREFIX_EVEX_0F3899,
1644   PREFIX_EVEX_0F389A,
1645   PREFIX_EVEX_0F389B,
1646   PREFIX_EVEX_0F389C,
1647   PREFIX_EVEX_0F389D,
1648   PREFIX_EVEX_0F389E,
1649   PREFIX_EVEX_0F389F,
1650   PREFIX_EVEX_0F38A0,
1651   PREFIX_EVEX_0F38A1,
1652   PREFIX_EVEX_0F38A2,
1653   PREFIX_EVEX_0F38A3,
1654   PREFIX_EVEX_0F38A6,
1655   PREFIX_EVEX_0F38A7,
1656   PREFIX_EVEX_0F38A8,
1657   PREFIX_EVEX_0F38A9,
1658   PREFIX_EVEX_0F38AA,
1659   PREFIX_EVEX_0F38AB,
1660   PREFIX_EVEX_0F38AC,
1661   PREFIX_EVEX_0F38AD,
1662   PREFIX_EVEX_0F38AE,
1663   PREFIX_EVEX_0F38AF,
1664   PREFIX_EVEX_0F38B4,
1665   PREFIX_EVEX_0F38B5,
1666   PREFIX_EVEX_0F38B6,
1667   PREFIX_EVEX_0F38B7,
1668   PREFIX_EVEX_0F38B8,
1669   PREFIX_EVEX_0F38B9,
1670   PREFIX_EVEX_0F38BA,
1671   PREFIX_EVEX_0F38BB,
1672   PREFIX_EVEX_0F38BC,
1673   PREFIX_EVEX_0F38BD,
1674   PREFIX_EVEX_0F38BE,
1675   PREFIX_EVEX_0F38BF,
1676   PREFIX_EVEX_0F38C4,
1677   PREFIX_EVEX_0F38C6_REG_1,
1678   PREFIX_EVEX_0F38C6_REG_2,
1679   PREFIX_EVEX_0F38C6_REG_5,
1680   PREFIX_EVEX_0F38C6_REG_6,
1681   PREFIX_EVEX_0F38C7_REG_1,
1682   PREFIX_EVEX_0F38C7_REG_2,
1683   PREFIX_EVEX_0F38C7_REG_5,
1684   PREFIX_EVEX_0F38C7_REG_6,
1685   PREFIX_EVEX_0F38C8,
1686   PREFIX_EVEX_0F38CA,
1687   PREFIX_EVEX_0F38CB,
1688   PREFIX_EVEX_0F38CC,
1689   PREFIX_EVEX_0F38CD,
1690   PREFIX_EVEX_0F38CF,
1691   PREFIX_EVEX_0F38DC,
1692   PREFIX_EVEX_0F38DD,
1693   PREFIX_EVEX_0F38DE,
1694   PREFIX_EVEX_0F38DF,
1695
1696   PREFIX_EVEX_0F3A00,
1697   PREFIX_EVEX_0F3A01,
1698   PREFIX_EVEX_0F3A03,
1699   PREFIX_EVEX_0F3A04,
1700   PREFIX_EVEX_0F3A05,
1701   PREFIX_EVEX_0F3A08,
1702   PREFIX_EVEX_0F3A09,
1703   PREFIX_EVEX_0F3A0A,
1704   PREFIX_EVEX_0F3A0B,
1705   PREFIX_EVEX_0F3A0F,
1706   PREFIX_EVEX_0F3A14,
1707   PREFIX_EVEX_0F3A15,
1708   PREFIX_EVEX_0F3A16,
1709   PREFIX_EVEX_0F3A17,
1710   PREFIX_EVEX_0F3A18,
1711   PREFIX_EVEX_0F3A19,
1712   PREFIX_EVEX_0F3A1A,
1713   PREFIX_EVEX_0F3A1B,
1714   PREFIX_EVEX_0F3A1D,
1715   PREFIX_EVEX_0F3A1E,
1716   PREFIX_EVEX_0F3A1F,
1717   PREFIX_EVEX_0F3A20,
1718   PREFIX_EVEX_0F3A21,
1719   PREFIX_EVEX_0F3A22,
1720   PREFIX_EVEX_0F3A23,
1721   PREFIX_EVEX_0F3A25,
1722   PREFIX_EVEX_0F3A26,
1723   PREFIX_EVEX_0F3A27,
1724   PREFIX_EVEX_0F3A38,
1725   PREFIX_EVEX_0F3A39,
1726   PREFIX_EVEX_0F3A3A,
1727   PREFIX_EVEX_0F3A3B,
1728   PREFIX_EVEX_0F3A3E,
1729   PREFIX_EVEX_0F3A3F,
1730   PREFIX_EVEX_0F3A42,
1731   PREFIX_EVEX_0F3A43,
1732   PREFIX_EVEX_0F3A44,
1733   PREFIX_EVEX_0F3A50,
1734   PREFIX_EVEX_0F3A51,
1735   PREFIX_EVEX_0F3A54,
1736   PREFIX_EVEX_0F3A55,
1737   PREFIX_EVEX_0F3A56,
1738   PREFIX_EVEX_0F3A57,
1739   PREFIX_EVEX_0F3A66,
1740   PREFIX_EVEX_0F3A67,
1741   PREFIX_EVEX_0F3A70,
1742   PREFIX_EVEX_0F3A71,
1743   PREFIX_EVEX_0F3A72,
1744   PREFIX_EVEX_0F3A73,
1745   PREFIX_EVEX_0F3ACE,
1746   PREFIX_EVEX_0F3ACF
1747 };
1748
1749 enum
1750 {
1751   X86_64_06 = 0,
1752   X86_64_07,
1753   X86_64_0D,
1754   X86_64_16,
1755   X86_64_17,
1756   X86_64_1E,
1757   X86_64_1F,
1758   X86_64_27,
1759   X86_64_2F,
1760   X86_64_37,
1761   X86_64_3F,
1762   X86_64_60,
1763   X86_64_61,
1764   X86_64_62,
1765   X86_64_63,
1766   X86_64_6D,
1767   X86_64_6F,
1768   X86_64_82,
1769   X86_64_9A,
1770   X86_64_C4,
1771   X86_64_C5,
1772   X86_64_CE,
1773   X86_64_D4,
1774   X86_64_D5,
1775   X86_64_E8,
1776   X86_64_E9,
1777   X86_64_EA,
1778   X86_64_0F01_REG_0,
1779   X86_64_0F01_REG_1,
1780   X86_64_0F01_REG_2,
1781   X86_64_0F01_REG_3
1782 };
1783
1784 enum
1785 {
1786   THREE_BYTE_0F38 = 0,
1787   THREE_BYTE_0F3A
1788 };
1789
1790 enum
1791 {
1792   XOP_08 = 0,
1793   XOP_09,
1794   XOP_0A
1795 };
1796
1797 enum
1798 {
1799   VEX_0F = 0,
1800   VEX_0F38,
1801   VEX_0F3A
1802 };
1803
1804 enum
1805 {
1806   EVEX_0F = 0,
1807   EVEX_0F38,
1808   EVEX_0F3A
1809 };
1810
1811 enum
1812 {
1813   VEX_LEN_0F12_P_0_M_0 = 0,
1814   VEX_LEN_0F12_P_0_M_1,
1815   VEX_LEN_0F12_P_2,
1816   VEX_LEN_0F13_M_0,
1817   VEX_LEN_0F16_P_0_M_0,
1818   VEX_LEN_0F16_P_0_M_1,
1819   VEX_LEN_0F16_P_2,
1820   VEX_LEN_0F17_M_0,
1821   VEX_LEN_0F2A_P_1,
1822   VEX_LEN_0F2A_P_3,
1823   VEX_LEN_0F2C_P_1,
1824   VEX_LEN_0F2C_P_3,
1825   VEX_LEN_0F2D_P_1,
1826   VEX_LEN_0F2D_P_3,
1827   VEX_LEN_0F41_P_0,
1828   VEX_LEN_0F41_P_2,
1829   VEX_LEN_0F42_P_0,
1830   VEX_LEN_0F42_P_2,
1831   VEX_LEN_0F44_P_0,
1832   VEX_LEN_0F44_P_2,
1833   VEX_LEN_0F45_P_0,
1834   VEX_LEN_0F45_P_2,
1835   VEX_LEN_0F46_P_0,
1836   VEX_LEN_0F46_P_2,
1837   VEX_LEN_0F47_P_0,
1838   VEX_LEN_0F47_P_2,
1839   VEX_LEN_0F4A_P_0,
1840   VEX_LEN_0F4A_P_2,
1841   VEX_LEN_0F4B_P_0,
1842   VEX_LEN_0F4B_P_2,
1843   VEX_LEN_0F6E_P_2,
1844   VEX_LEN_0F77_P_0,
1845   VEX_LEN_0F7E_P_1,
1846   VEX_LEN_0F7E_P_2,
1847   VEX_LEN_0F90_P_0,
1848   VEX_LEN_0F90_P_2,
1849   VEX_LEN_0F91_P_0,
1850   VEX_LEN_0F91_P_2,
1851   VEX_LEN_0F92_P_0,
1852   VEX_LEN_0F92_P_2,
1853   VEX_LEN_0F92_P_3,
1854   VEX_LEN_0F93_P_0,
1855   VEX_LEN_0F93_P_2,
1856   VEX_LEN_0F93_P_3,
1857   VEX_LEN_0F98_P_0,
1858   VEX_LEN_0F98_P_2,
1859   VEX_LEN_0F99_P_0,
1860   VEX_LEN_0F99_P_2,
1861   VEX_LEN_0FAE_R_2_M_0,
1862   VEX_LEN_0FAE_R_3_M_0,
1863   VEX_LEN_0FC4_P_2,
1864   VEX_LEN_0FC5_P_2,
1865   VEX_LEN_0FD6_P_2,
1866   VEX_LEN_0FF7_P_2,
1867   VEX_LEN_0F3816_P_2,
1868   VEX_LEN_0F3819_P_2,
1869   VEX_LEN_0F381A_P_2_M_0,
1870   VEX_LEN_0F3836_P_2,
1871   VEX_LEN_0F3841_P_2,
1872   VEX_LEN_0F385A_P_2_M_0,
1873   VEX_LEN_0F38DB_P_2,
1874   VEX_LEN_0F38F2_P_0,
1875   VEX_LEN_0F38F3_R_1_P_0,
1876   VEX_LEN_0F38F3_R_2_P_0,
1877   VEX_LEN_0F38F3_R_3_P_0,
1878   VEX_LEN_0F38F5_P_0,
1879   VEX_LEN_0F38F5_P_1,
1880   VEX_LEN_0F38F5_P_3,
1881   VEX_LEN_0F38F6_P_3,
1882   VEX_LEN_0F38F7_P_0,
1883   VEX_LEN_0F38F7_P_1,
1884   VEX_LEN_0F38F7_P_2,
1885   VEX_LEN_0F38F7_P_3,
1886   VEX_LEN_0F3A00_P_2,
1887   VEX_LEN_0F3A01_P_2,
1888   VEX_LEN_0F3A06_P_2,
1889   VEX_LEN_0F3A14_P_2,
1890   VEX_LEN_0F3A15_P_2,
1891   VEX_LEN_0F3A16_P_2,
1892   VEX_LEN_0F3A17_P_2,
1893   VEX_LEN_0F3A18_P_2,
1894   VEX_LEN_0F3A19_P_2,
1895   VEX_LEN_0F3A20_P_2,
1896   VEX_LEN_0F3A21_P_2,
1897   VEX_LEN_0F3A22_P_2,
1898   VEX_LEN_0F3A30_P_2,
1899   VEX_LEN_0F3A31_P_2,
1900   VEX_LEN_0F3A32_P_2,
1901   VEX_LEN_0F3A33_P_2,
1902   VEX_LEN_0F3A38_P_2,
1903   VEX_LEN_0F3A39_P_2,
1904   VEX_LEN_0F3A41_P_2,
1905   VEX_LEN_0F3A46_P_2,
1906   VEX_LEN_0F3A60_P_2,
1907   VEX_LEN_0F3A61_P_2,
1908   VEX_LEN_0F3A62_P_2,
1909   VEX_LEN_0F3A63_P_2,
1910   VEX_LEN_0F3A6A_P_2,
1911   VEX_LEN_0F3A6B_P_2,
1912   VEX_LEN_0F3A6E_P_2,
1913   VEX_LEN_0F3A6F_P_2,
1914   VEX_LEN_0F3A7A_P_2,
1915   VEX_LEN_0F3A7B_P_2,
1916   VEX_LEN_0F3A7E_P_2,
1917   VEX_LEN_0F3A7F_P_2,
1918   VEX_LEN_0F3ADF_P_2,
1919   VEX_LEN_0F3AF0_P_3,
1920   VEX_LEN_0FXOP_08_CC,
1921   VEX_LEN_0FXOP_08_CD,
1922   VEX_LEN_0FXOP_08_CE,
1923   VEX_LEN_0FXOP_08_CF,
1924   VEX_LEN_0FXOP_08_EC,
1925   VEX_LEN_0FXOP_08_ED,
1926   VEX_LEN_0FXOP_08_EE,
1927   VEX_LEN_0FXOP_08_EF,
1928   VEX_LEN_0FXOP_09_80,
1929   VEX_LEN_0FXOP_09_81
1930 };
1931
1932 enum
1933 {
1934   EVEX_LEN_0F6E_P_2 = 0,
1935   EVEX_LEN_0F7E_P_1,
1936   EVEX_LEN_0F7E_P_2,
1937   EVEX_LEN_0FD6_P_2
1938 };
1939
1940 enum
1941 {
1942   VEX_W_0F41_P_0_LEN_1 = 0,
1943   VEX_W_0F41_P_2_LEN_1,
1944   VEX_W_0F42_P_0_LEN_1,
1945   VEX_W_0F42_P_2_LEN_1,
1946   VEX_W_0F44_P_0_LEN_0,
1947   VEX_W_0F44_P_2_LEN_0,
1948   VEX_W_0F45_P_0_LEN_1,
1949   VEX_W_0F45_P_2_LEN_1,
1950   VEX_W_0F46_P_0_LEN_1,
1951   VEX_W_0F46_P_2_LEN_1,
1952   VEX_W_0F47_P_0_LEN_1,
1953   VEX_W_0F47_P_2_LEN_1,
1954   VEX_W_0F4A_P_0_LEN_1,
1955   VEX_W_0F4A_P_2_LEN_1,
1956   VEX_W_0F4B_P_0_LEN_1,
1957   VEX_W_0F4B_P_2_LEN_1,
1958   VEX_W_0F90_P_0_LEN_0,
1959   VEX_W_0F90_P_2_LEN_0,
1960   VEX_W_0F91_P_0_LEN_0,
1961   VEX_W_0F91_P_2_LEN_0,
1962   VEX_W_0F92_P_0_LEN_0,
1963   VEX_W_0F92_P_2_LEN_0,
1964   VEX_W_0F93_P_0_LEN_0,
1965   VEX_W_0F93_P_2_LEN_0,
1966   VEX_W_0F98_P_0_LEN_0,
1967   VEX_W_0F98_P_2_LEN_0,
1968   VEX_W_0F99_P_0_LEN_0,
1969   VEX_W_0F99_P_2_LEN_0,
1970   VEX_W_0F380C_P_2,
1971   VEX_W_0F380D_P_2,
1972   VEX_W_0F380E_P_2,
1973   VEX_W_0F380F_P_2,
1974   VEX_W_0F3816_P_2,
1975   VEX_W_0F3818_P_2,
1976   VEX_W_0F3819_P_2,
1977   VEX_W_0F381A_P_2_M_0,
1978   VEX_W_0F382C_P_2_M_0,
1979   VEX_W_0F382D_P_2_M_0,
1980   VEX_W_0F382E_P_2_M_0,
1981   VEX_W_0F382F_P_2_M_0,
1982   VEX_W_0F3836_P_2,
1983   VEX_W_0F3846_P_2,
1984   VEX_W_0F3858_P_2,
1985   VEX_W_0F3859_P_2,
1986   VEX_W_0F385A_P_2_M_0,
1987   VEX_W_0F3878_P_2,
1988   VEX_W_0F3879_P_2,
1989   VEX_W_0F38CF_P_2,
1990   VEX_W_0F3A00_P_2,
1991   VEX_W_0F3A01_P_2,
1992   VEX_W_0F3A02_P_2,
1993   VEX_W_0F3A04_P_2,
1994   VEX_W_0F3A05_P_2,
1995   VEX_W_0F3A06_P_2,
1996   VEX_W_0F3A18_P_2,
1997   VEX_W_0F3A19_P_2,
1998   VEX_W_0F3A30_P_2_LEN_0,
1999   VEX_W_0F3A31_P_2_LEN_0,
2000   VEX_W_0F3A32_P_2_LEN_0,
2001   VEX_W_0F3A33_P_2_LEN_0,
2002   VEX_W_0F3A38_P_2,
2003   VEX_W_0F3A39_P_2,
2004   VEX_W_0F3A46_P_2,
2005   VEX_W_0F3A48_P_2,
2006   VEX_W_0F3A49_P_2,
2007   VEX_W_0F3A4A_P_2,
2008   VEX_W_0F3A4B_P_2,
2009   VEX_W_0F3A4C_P_2,
2010   VEX_W_0F3ACE_P_2,
2011   VEX_W_0F3ACF_P_2,
2012
2013   EVEX_W_0F10_P_0,
2014   EVEX_W_0F10_P_1_M_0,
2015   EVEX_W_0F10_P_1_M_1,
2016   EVEX_W_0F10_P_2,
2017   EVEX_W_0F10_P_3_M_0,
2018   EVEX_W_0F10_P_3_M_1,
2019   EVEX_W_0F11_P_0,
2020   EVEX_W_0F11_P_1_M_0,
2021   EVEX_W_0F11_P_1_M_1,
2022   EVEX_W_0F11_P_2,
2023   EVEX_W_0F11_P_3_M_0,
2024   EVEX_W_0F11_P_3_M_1,
2025   EVEX_W_0F12_P_0_M_0,
2026   EVEX_W_0F12_P_0_M_1,
2027   EVEX_W_0F12_P_1,
2028   EVEX_W_0F12_P_2,
2029   EVEX_W_0F12_P_3,
2030   EVEX_W_0F13_P_0,
2031   EVEX_W_0F13_P_2,
2032   EVEX_W_0F14_P_0,
2033   EVEX_W_0F14_P_2,
2034   EVEX_W_0F15_P_0,
2035   EVEX_W_0F15_P_2,
2036   EVEX_W_0F16_P_0_M_0,
2037   EVEX_W_0F16_P_0_M_1,
2038   EVEX_W_0F16_P_1,
2039   EVEX_W_0F16_P_2,
2040   EVEX_W_0F17_P_0,
2041   EVEX_W_0F17_P_2,
2042   EVEX_W_0F28_P_0,
2043   EVEX_W_0F28_P_2,
2044   EVEX_W_0F29_P_0,
2045   EVEX_W_0F29_P_2,
2046   EVEX_W_0F2A_P_1,
2047   EVEX_W_0F2A_P_3,
2048   EVEX_W_0F2B_P_0,
2049   EVEX_W_0F2B_P_2,
2050   EVEX_W_0F2E_P_0,
2051   EVEX_W_0F2E_P_2,
2052   EVEX_W_0F2F_P_0,
2053   EVEX_W_0F2F_P_2,
2054   EVEX_W_0F51_P_0,
2055   EVEX_W_0F51_P_1,
2056   EVEX_W_0F51_P_2,
2057   EVEX_W_0F51_P_3,
2058   EVEX_W_0F54_P_0,
2059   EVEX_W_0F54_P_2,
2060   EVEX_W_0F55_P_0,
2061   EVEX_W_0F55_P_2,
2062   EVEX_W_0F56_P_0,
2063   EVEX_W_0F56_P_2,
2064   EVEX_W_0F57_P_0,
2065   EVEX_W_0F57_P_2,
2066   EVEX_W_0F58_P_0,
2067   EVEX_W_0F58_P_1,
2068   EVEX_W_0F58_P_2,
2069   EVEX_W_0F58_P_3,
2070   EVEX_W_0F59_P_0,
2071   EVEX_W_0F59_P_1,
2072   EVEX_W_0F59_P_2,
2073   EVEX_W_0F59_P_3,
2074   EVEX_W_0F5A_P_0,
2075   EVEX_W_0F5A_P_1,
2076   EVEX_W_0F5A_P_2,
2077   EVEX_W_0F5A_P_3,
2078   EVEX_W_0F5B_P_0,
2079   EVEX_W_0F5B_P_1,
2080   EVEX_W_0F5B_P_2,
2081   EVEX_W_0F5C_P_0,
2082   EVEX_W_0F5C_P_1,
2083   EVEX_W_0F5C_P_2,
2084   EVEX_W_0F5C_P_3,
2085   EVEX_W_0F5D_P_0,
2086   EVEX_W_0F5D_P_1,
2087   EVEX_W_0F5D_P_2,
2088   EVEX_W_0F5D_P_3,
2089   EVEX_W_0F5E_P_0,
2090   EVEX_W_0F5E_P_1,
2091   EVEX_W_0F5E_P_2,
2092   EVEX_W_0F5E_P_3,
2093   EVEX_W_0F5F_P_0,
2094   EVEX_W_0F5F_P_1,
2095   EVEX_W_0F5F_P_2,
2096   EVEX_W_0F5F_P_3,
2097   EVEX_W_0F62_P_2,
2098   EVEX_W_0F66_P_2,
2099   EVEX_W_0F6A_P_2,
2100   EVEX_W_0F6B_P_2,
2101   EVEX_W_0F6C_P_2,
2102   EVEX_W_0F6D_P_2,
2103   EVEX_W_0F6E_P_2,
2104   EVEX_W_0F6F_P_1,
2105   EVEX_W_0F6F_P_2,
2106   EVEX_W_0F6F_P_3,
2107   EVEX_W_0F70_P_2,
2108   EVEX_W_0F72_R_2_P_2,
2109   EVEX_W_0F72_R_6_P_2,
2110   EVEX_W_0F73_R_2_P_2,
2111   EVEX_W_0F73_R_6_P_2,
2112   EVEX_W_0F76_P_2,
2113   EVEX_W_0F78_P_0,
2114   EVEX_W_0F78_P_2,
2115   EVEX_W_0F79_P_0,
2116   EVEX_W_0F79_P_2,
2117   EVEX_W_0F7A_P_1,
2118   EVEX_W_0F7A_P_2,
2119   EVEX_W_0F7A_P_3,
2120   EVEX_W_0F7B_P_1,
2121   EVEX_W_0F7B_P_2,
2122   EVEX_W_0F7B_P_3,
2123   EVEX_W_0F7E_P_1,
2124   EVEX_W_0F7E_P_2,
2125   EVEX_W_0F7F_P_1,
2126   EVEX_W_0F7F_P_2,
2127   EVEX_W_0F7F_P_3,
2128   EVEX_W_0FC2_P_0,
2129   EVEX_W_0FC2_P_1,
2130   EVEX_W_0FC2_P_2,
2131   EVEX_W_0FC2_P_3,
2132   EVEX_W_0FC6_P_0,
2133   EVEX_W_0FC6_P_2,
2134   EVEX_W_0FD2_P_2,
2135   EVEX_W_0FD3_P_2,
2136   EVEX_W_0FD4_P_2,
2137   EVEX_W_0FD6_P_2,
2138   EVEX_W_0FE6_P_1,
2139   EVEX_W_0FE6_P_2,
2140   EVEX_W_0FE6_P_3,
2141   EVEX_W_0FE7_P_2,
2142   EVEX_W_0FF2_P_2,
2143   EVEX_W_0FF3_P_2,
2144   EVEX_W_0FF4_P_2,
2145   EVEX_W_0FFA_P_2,
2146   EVEX_W_0FFB_P_2,
2147   EVEX_W_0FFE_P_2,
2148   EVEX_W_0F380C_P_2,
2149   EVEX_W_0F380D_P_2,
2150   EVEX_W_0F3810_P_1,
2151   EVEX_W_0F3810_P_2,
2152   EVEX_W_0F3811_P_1,
2153   EVEX_W_0F3811_P_2,
2154   EVEX_W_0F3812_P_1,
2155   EVEX_W_0F3812_P_2,
2156   EVEX_W_0F3813_P_1,
2157   EVEX_W_0F3813_P_2,
2158   EVEX_W_0F3814_P_1,
2159   EVEX_W_0F3815_P_1,
2160   EVEX_W_0F3818_P_2,
2161   EVEX_W_0F3819_P_2,
2162   EVEX_W_0F381A_P_2,
2163   EVEX_W_0F381B_P_2,
2164   EVEX_W_0F381E_P_2,
2165   EVEX_W_0F381F_P_2,
2166   EVEX_W_0F3820_P_1,
2167   EVEX_W_0F3821_P_1,
2168   EVEX_W_0F3822_P_1,
2169   EVEX_W_0F3823_P_1,
2170   EVEX_W_0F3824_P_1,
2171   EVEX_W_0F3825_P_1,
2172   EVEX_W_0F3825_P_2,
2173   EVEX_W_0F3826_P_1,
2174   EVEX_W_0F3826_P_2,
2175   EVEX_W_0F3828_P_1,
2176   EVEX_W_0F3828_P_2,
2177   EVEX_W_0F3829_P_1,
2178   EVEX_W_0F3829_P_2,
2179   EVEX_W_0F382A_P_1,
2180   EVEX_W_0F382A_P_2,
2181   EVEX_W_0F382B_P_2,
2182   EVEX_W_0F3830_P_1,
2183   EVEX_W_0F3831_P_1,
2184   EVEX_W_0F3832_P_1,
2185   EVEX_W_0F3833_P_1,
2186   EVEX_W_0F3834_P_1,
2187   EVEX_W_0F3835_P_1,
2188   EVEX_W_0F3835_P_2,
2189   EVEX_W_0F3837_P_2,
2190   EVEX_W_0F3838_P_1,
2191   EVEX_W_0F3839_P_1,
2192   EVEX_W_0F383A_P_1,
2193   EVEX_W_0F3840_P_2,
2194   EVEX_W_0F3854_P_2,
2195   EVEX_W_0F3855_P_2,
2196   EVEX_W_0F3858_P_2,
2197   EVEX_W_0F3859_P_2,
2198   EVEX_W_0F385A_P_2,
2199   EVEX_W_0F385B_P_2,
2200   EVEX_W_0F3862_P_2,
2201   EVEX_W_0F3863_P_2,
2202   EVEX_W_0F3866_P_2,
2203   EVEX_W_0F3870_P_2,
2204   EVEX_W_0F3871_P_2,
2205   EVEX_W_0F3872_P_2,
2206   EVEX_W_0F3873_P_2,
2207   EVEX_W_0F3875_P_2,
2208   EVEX_W_0F3878_P_2,
2209   EVEX_W_0F3879_P_2,
2210   EVEX_W_0F387A_P_2,
2211   EVEX_W_0F387B_P_2,
2212   EVEX_W_0F387D_P_2,
2213   EVEX_W_0F3883_P_2,
2214   EVEX_W_0F388D_P_2,
2215   EVEX_W_0F3891_P_2,
2216   EVEX_W_0F3893_P_2,
2217   EVEX_W_0F38A1_P_2,
2218   EVEX_W_0F38A3_P_2,
2219   EVEX_W_0F38C7_R_1_P_2,
2220   EVEX_W_0F38C7_R_2_P_2,
2221   EVEX_W_0F38C7_R_5_P_2,
2222   EVEX_W_0F38C7_R_6_P_2,
2223
2224   EVEX_W_0F3A00_P_2,
2225   EVEX_W_0F3A01_P_2,
2226   EVEX_W_0F3A04_P_2,
2227   EVEX_W_0F3A05_P_2,
2228   EVEX_W_0F3A08_P_2,
2229   EVEX_W_0F3A09_P_2,
2230   EVEX_W_0F3A0A_P_2,
2231   EVEX_W_0F3A0B_P_2,
2232   EVEX_W_0F3A18_P_2,
2233   EVEX_W_0F3A19_P_2,
2234   EVEX_W_0F3A1A_P_2,
2235   EVEX_W_0F3A1B_P_2,
2236   EVEX_W_0F3A1D_P_2,
2237   EVEX_W_0F3A21_P_2,
2238   EVEX_W_0F3A23_P_2,
2239   EVEX_W_0F3A38_P_2,
2240   EVEX_W_0F3A39_P_2,
2241   EVEX_W_0F3A3A_P_2,
2242   EVEX_W_0F3A3B_P_2,
2243   EVEX_W_0F3A3E_P_2,
2244   EVEX_W_0F3A3F_P_2,
2245   EVEX_W_0F3A42_P_2,
2246   EVEX_W_0F3A43_P_2,
2247   EVEX_W_0F3A50_P_2,
2248   EVEX_W_0F3A51_P_2,
2249   EVEX_W_0F3A56_P_2,
2250   EVEX_W_0F3A57_P_2,
2251   EVEX_W_0F3A66_P_2,
2252   EVEX_W_0F3A67_P_2,
2253   EVEX_W_0F3A70_P_2,
2254   EVEX_W_0F3A71_P_2,
2255   EVEX_W_0F3A72_P_2,
2256   EVEX_W_0F3A73_P_2,
2257   EVEX_W_0F3ACE_P_2,
2258   EVEX_W_0F3ACF_P_2
2259 };
2260
2261 typedef void (*op_rtn) (int bytemode, int sizeflag);
2262
2263 struct dis386 {
2264   const char *name;
2265   struct
2266     {
2267       op_rtn rtn;
2268       int bytemode;
2269     } op[MAX_OPERANDS];
2270   unsigned int prefix_requirement;
2271 };
2272
2273 /* Upper case letters in the instruction names here are macros.
2274    'A' => print 'b' if no register operands or suffix_always is true
2275    'B' => print 'b' if suffix_always is true
2276    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2277           size prefix
2278    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2279           suffix_always is true
2280    'E' => print 'e' if 32-bit form of jcxz
2281    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2282    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2283    'H' => print ",pt" or ",pn" branch hint
2284    'I' => honor following macro letter even in Intel mode (implemented only
2285           for some of the macro letters)
2286    'J' => print 'l'
2287    'K' => print 'd' or 'q' if rex prefix is present.
2288    'L' => print 'l' if suffix_always is true
2289    'M' => print 'r' if intel_mnemonic is false.
2290    'N' => print 'n' if instruction has no wait "prefix"
2291    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2292    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2293           or suffix_always is true.  print 'q' if rex prefix is present.
2294    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2295           is true
2296    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2297    'S' => print 'w', 'l' or 'q' if suffix_always is true
2298    'T' => print 'q' in 64bit mode if instruction has no operand size
2299           prefix and behave as 'P' otherwise
2300    'U' => print 'q' in 64bit mode if instruction has no operand size
2301           prefix and behave as 'Q' otherwise
2302    'V' => print 'q' in 64bit mode if instruction has no operand size
2303           prefix and behave as 'S' otherwise
2304    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2305    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2306    'Y' unused.
2307    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2308    '!' => change condition from true to false or from false to true.
2309    '%' => add 1 upper case letter to the macro.
2310    '^' => print 'w' or 'l' depending on operand size prefix or
2311           suffix_always is true (lcall/ljmp).
2312    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2313           on operand size prefix.
2314    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2315           has no operand size prefix for AMD64 ISA, behave as 'P'
2316           otherwise
2317
2318    2 upper case letter macros:
2319    "XY" => print 'x' or 'y' if suffix_always is true or no register
2320            operands and no broadcast.
2321    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2322            register operands and no broadcast.
2323    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2324    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2325            or suffix_always is true
2326    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2327    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2328    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2329    "LW" => print 'd', 'q' depending on the VEX.W bit
2330    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2331            an operand size prefix, or suffix_always is true.  print
2332            'q' if rex prefix is present.
2333
2334    Many of the above letters print nothing in Intel mode.  See "putop"
2335    for the details.
2336
2337    Braces '{' and '}', and vertical bars '|', indicate alternative
2338    mnemonic strings for AT&T and Intel.  */
2339
2340 static const struct dis386 dis386[] = {
2341   /* 00 */
2342   { "addB",             { Ebh1, Gb }, 0 },
2343   { "addS",             { Evh1, Gv }, 0 },
2344   { "addB",             { Gb, EbS }, 0 },
2345   { "addS",             { Gv, EvS }, 0 },
2346   { "addB",             { AL, Ib }, 0 },
2347   { "addS",             { eAX, Iv }, 0 },
2348   { X86_64_TABLE (X86_64_06) },
2349   { X86_64_TABLE (X86_64_07) },
2350   /* 08 */
2351   { "orB",              { Ebh1, Gb }, 0 },
2352   { "orS",              { Evh1, Gv }, 0 },
2353   { "orB",              { Gb, EbS }, 0 },
2354   { "orS",              { Gv, EvS }, 0 },
2355   { "orB",              { AL, Ib }, 0 },
2356   { "orS",              { eAX, Iv }, 0 },
2357   { X86_64_TABLE (X86_64_0D) },
2358   { Bad_Opcode },       /* 0x0f extended opcode escape */
2359   /* 10 */
2360   { "adcB",             { Ebh1, Gb }, 0 },
2361   { "adcS",             { Evh1, Gv }, 0 },
2362   { "adcB",             { Gb, EbS }, 0 },
2363   { "adcS",             { Gv, EvS }, 0 },
2364   { "adcB",             { AL, Ib }, 0 },
2365   { "adcS",             { eAX, Iv }, 0 },
2366   { X86_64_TABLE (X86_64_16) },
2367   { X86_64_TABLE (X86_64_17) },
2368   /* 18 */
2369   { "sbbB",             { Ebh1, Gb }, 0 },
2370   { "sbbS",             { Evh1, Gv }, 0 },
2371   { "sbbB",             { Gb, EbS }, 0 },
2372   { "sbbS",             { Gv, EvS }, 0 },
2373   { "sbbB",             { AL, Ib }, 0 },
2374   { "sbbS",             { eAX, Iv }, 0 },
2375   { X86_64_TABLE (X86_64_1E) },
2376   { X86_64_TABLE (X86_64_1F) },
2377   /* 20 */
2378   { "andB",             { Ebh1, Gb }, 0 },
2379   { "andS",             { Evh1, Gv }, 0 },
2380   { "andB",             { Gb, EbS }, 0 },
2381   { "andS",             { Gv, EvS }, 0 },
2382   { "andB",             { AL, Ib }, 0 },
2383   { "andS",             { eAX, Iv }, 0 },
2384   { Bad_Opcode },       /* SEG ES prefix */
2385   { X86_64_TABLE (X86_64_27) },
2386   /* 28 */
2387   { "subB",             { Ebh1, Gb }, 0 },
2388   { "subS",             { Evh1, Gv }, 0 },
2389   { "subB",             { Gb, EbS }, 0 },
2390   { "subS",             { Gv, EvS }, 0 },
2391   { "subB",             { AL, Ib }, 0 },
2392   { "subS",             { eAX, Iv }, 0 },
2393   { Bad_Opcode },       /* SEG CS prefix */
2394   { X86_64_TABLE (X86_64_2F) },
2395   /* 30 */
2396   { "xorB",             { Ebh1, Gb }, 0 },
2397   { "xorS",             { Evh1, Gv }, 0 },
2398   { "xorB",             { Gb, EbS }, 0 },
2399   { "xorS",             { Gv, EvS }, 0 },
2400   { "xorB",             { AL, Ib }, 0 },
2401   { "xorS",             { eAX, Iv }, 0 },
2402   { Bad_Opcode },       /* SEG SS prefix */
2403   { X86_64_TABLE (X86_64_37) },
2404   /* 38 */
2405   { "cmpB",             { Eb, Gb }, 0 },
2406   { "cmpS",             { Ev, Gv }, 0 },
2407   { "cmpB",             { Gb, EbS }, 0 },
2408   { "cmpS",             { Gv, EvS }, 0 },
2409   { "cmpB",             { AL, Ib }, 0 },
2410   { "cmpS",             { eAX, Iv }, 0 },
2411   { Bad_Opcode },       /* SEG DS prefix */
2412   { X86_64_TABLE (X86_64_3F) },
2413   /* 40 */
2414   { "inc{S|}",          { RMeAX }, 0 },
2415   { "inc{S|}",          { RMeCX }, 0 },
2416   { "inc{S|}",          { RMeDX }, 0 },
2417   { "inc{S|}",          { RMeBX }, 0 },
2418   { "inc{S|}",          { RMeSP }, 0 },
2419   { "inc{S|}",          { RMeBP }, 0 },
2420   { "inc{S|}",          { RMeSI }, 0 },
2421   { "inc{S|}",          { RMeDI }, 0 },
2422   /* 48 */
2423   { "dec{S|}",          { RMeAX }, 0 },
2424   { "dec{S|}",          { RMeCX }, 0 },
2425   { "dec{S|}",          { RMeDX }, 0 },
2426   { "dec{S|}",          { RMeBX }, 0 },
2427   { "dec{S|}",          { RMeSP }, 0 },
2428   { "dec{S|}",          { RMeBP }, 0 },
2429   { "dec{S|}",          { RMeSI }, 0 },
2430   { "dec{S|}",          { RMeDI }, 0 },
2431   /* 50 */
2432   { "pushV",            { RMrAX }, 0 },
2433   { "pushV",            { RMrCX }, 0 },
2434   { "pushV",            { RMrDX }, 0 },
2435   { "pushV",            { RMrBX }, 0 },
2436   { "pushV",            { RMrSP }, 0 },
2437   { "pushV",            { RMrBP }, 0 },
2438   { "pushV",            { RMrSI }, 0 },
2439   { "pushV",            { RMrDI }, 0 },
2440   /* 58 */
2441   { "popV",             { RMrAX }, 0 },
2442   { "popV",             { RMrCX }, 0 },
2443   { "popV",             { RMrDX }, 0 },
2444   { "popV",             { RMrBX }, 0 },
2445   { "popV",             { RMrSP }, 0 },
2446   { "popV",             { RMrBP }, 0 },
2447   { "popV",             { RMrSI }, 0 },
2448   { "popV",             { RMrDI }, 0 },
2449   /* 60 */
2450   { X86_64_TABLE (X86_64_60) },
2451   { X86_64_TABLE (X86_64_61) },
2452   { X86_64_TABLE (X86_64_62) },
2453   { X86_64_TABLE (X86_64_63) },
2454   { Bad_Opcode },       /* seg fs */
2455   { Bad_Opcode },       /* seg gs */
2456   { Bad_Opcode },       /* op size prefix */
2457   { Bad_Opcode },       /* adr size prefix */
2458   /* 68 */
2459   { "pushT",            { sIv }, 0 },
2460   { "imulS",            { Gv, Ev, Iv }, 0 },
2461   { "pushT",            { sIbT }, 0 },
2462   { "imulS",            { Gv, Ev, sIb }, 0 },
2463   { "ins{b|}",          { Ybr, indirDX }, 0 },
2464   { X86_64_TABLE (X86_64_6D) },
2465   { "outs{b|}",         { indirDXr, Xb }, 0 },
2466   { X86_64_TABLE (X86_64_6F) },
2467   /* 70 */
2468   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2469   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2470   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2471   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2472   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2473   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2474   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2475   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2476   /* 78 */
2477   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2478   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2479   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2480   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2481   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2482   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2483   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2484   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2485   /* 80 */
2486   { REG_TABLE (REG_80) },
2487   { REG_TABLE (REG_81) },
2488   { X86_64_TABLE (X86_64_82) },
2489   { REG_TABLE (REG_83) },
2490   { "testB",            { Eb, Gb }, 0 },
2491   { "testS",            { Ev, Gv }, 0 },
2492   { "xchgB",            { Ebh2, Gb }, 0 },
2493   { "xchgS",            { Evh2, Gv }, 0 },
2494   /* 88 */
2495   { "movB",             { Ebh3, Gb }, 0 },
2496   { "movS",             { Evh3, Gv }, 0 },
2497   { "movB",             { Gb, EbS }, 0 },
2498   { "movS",             { Gv, EvS }, 0 },
2499   { "movD",             { Sv, Sw }, 0 },
2500   { MOD_TABLE (MOD_8D) },
2501   { "movD",             { Sw, Sv }, 0 },
2502   { REG_TABLE (REG_8F) },
2503   /* 90 */
2504   { PREFIX_TABLE (PREFIX_90) },
2505   { "xchgS",            { RMeCX, eAX }, 0 },
2506   { "xchgS",            { RMeDX, eAX }, 0 },
2507   { "xchgS",            { RMeBX, eAX }, 0 },
2508   { "xchgS",            { RMeSP, eAX }, 0 },
2509   { "xchgS",            { RMeBP, eAX }, 0 },
2510   { "xchgS",            { RMeSI, eAX }, 0 },
2511   { "xchgS",            { RMeDI, eAX }, 0 },
2512   /* 98 */
2513   { "cW{t|}R",          { XX }, 0 },
2514   { "cR{t|}O",          { XX }, 0 },
2515   { X86_64_TABLE (X86_64_9A) },
2516   { Bad_Opcode },       /* fwait */
2517   { "pushfT",           { XX }, 0 },
2518   { "popfT",            { XX }, 0 },
2519   { "sahf",             { XX }, 0 },
2520   { "lahf",             { XX }, 0 },
2521   /* a0 */
2522   { "mov%LB",           { AL, Ob }, 0 },
2523   { "mov%LS",           { eAX, Ov }, 0 },
2524   { "mov%LB",           { Ob, AL }, 0 },
2525   { "mov%LS",           { Ov, eAX }, 0 },
2526   { "movs{b|}",         { Ybr, Xb }, 0 },
2527   { "movs{R|}",         { Yvr, Xv }, 0 },
2528   { "cmps{b|}",         { Xb, Yb }, 0 },
2529   { "cmps{R|}",         { Xv, Yv }, 0 },
2530   /* a8 */
2531   { "testB",            { AL, Ib }, 0 },
2532   { "testS",            { eAX, Iv }, 0 },
2533   { "stosB",            { Ybr, AL }, 0 },
2534   { "stosS",            { Yvr, eAX }, 0 },
2535   { "lodsB",            { ALr, Xb }, 0 },
2536   { "lodsS",            { eAXr, Xv }, 0 },
2537   { "scasB",            { AL, Yb }, 0 },
2538   { "scasS",            { eAX, Yv }, 0 },
2539   /* b0 */
2540   { "movB",             { RMAL, Ib }, 0 },
2541   { "movB",             { RMCL, Ib }, 0 },
2542   { "movB",             { RMDL, Ib }, 0 },
2543   { "movB",             { RMBL, Ib }, 0 },
2544   { "movB",             { RMAH, Ib }, 0 },
2545   { "movB",             { RMCH, Ib }, 0 },
2546   { "movB",             { RMDH, Ib }, 0 },
2547   { "movB",             { RMBH, Ib }, 0 },
2548   /* b8 */
2549   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2550   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2551   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2552   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2553   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2554   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2555   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2556   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2557   /* c0 */
2558   { REG_TABLE (REG_C0) },
2559   { REG_TABLE (REG_C1) },
2560   { "retT",             { Iw, BND }, 0 },
2561   { "retT",             { BND }, 0 },
2562   { X86_64_TABLE (X86_64_C4) },
2563   { X86_64_TABLE (X86_64_C5) },
2564   { REG_TABLE (REG_C6) },
2565   { REG_TABLE (REG_C7) },
2566   /* c8 */
2567   { "enterT",           { Iw, Ib }, 0 },
2568   { "leaveT",           { XX }, 0 },
2569   { "Jret{|f}P",        { Iw }, 0 },
2570   { "Jret{|f}P",        { XX }, 0 },
2571   { "int3",             { XX }, 0 },
2572   { "int",              { Ib }, 0 },
2573   { X86_64_TABLE (X86_64_CE) },
2574   { "iret%LP",          { XX }, 0 },
2575   /* d0 */
2576   { REG_TABLE (REG_D0) },
2577   { REG_TABLE (REG_D1) },
2578   { REG_TABLE (REG_D2) },
2579   { REG_TABLE (REG_D3) },
2580   { X86_64_TABLE (X86_64_D4) },
2581   { X86_64_TABLE (X86_64_D5) },
2582   { Bad_Opcode },
2583   { "xlat",             { DSBX }, 0 },
2584   /* d8 */
2585   { FLOAT },
2586   { FLOAT },
2587   { FLOAT },
2588   { FLOAT },
2589   { FLOAT },
2590   { FLOAT },
2591   { FLOAT },
2592   { FLOAT },
2593   /* e0 */
2594   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2595   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2596   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2597   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2598   { "inB",              { AL, Ib }, 0 },
2599   { "inG",              { zAX, Ib }, 0 },
2600   { "outB",             { Ib, AL }, 0 },
2601   { "outG",             { Ib, zAX }, 0 },
2602   /* e8 */
2603   { X86_64_TABLE (X86_64_E8) },
2604   { X86_64_TABLE (X86_64_E9) },
2605   { X86_64_TABLE (X86_64_EA) },
2606   { "jmp",              { Jb, BND }, 0 },
2607   { "inB",              { AL, indirDX }, 0 },
2608   { "inG",              { zAX, indirDX }, 0 },
2609   { "outB",             { indirDX, AL }, 0 },
2610   { "outG",             { indirDX, zAX }, 0 },
2611   /* f0 */
2612   { Bad_Opcode },       /* lock prefix */
2613   { "icebp",            { XX }, 0 },
2614   { Bad_Opcode },       /* repne */
2615   { Bad_Opcode },       /* repz */
2616   { "hlt",              { XX }, 0 },
2617   { "cmc",              { XX }, 0 },
2618   { REG_TABLE (REG_F6) },
2619   { REG_TABLE (REG_F7) },
2620   /* f8 */
2621   { "clc",              { XX }, 0 },
2622   { "stc",              { XX }, 0 },
2623   { "cli",              { XX }, 0 },
2624   { "sti",              { XX }, 0 },
2625   { "cld",              { XX }, 0 },
2626   { "std",              { XX }, 0 },
2627   { REG_TABLE (REG_FE) },
2628   { REG_TABLE (REG_FF) },
2629 };
2630
2631 static const struct dis386 dis386_twobyte[] = {
2632   /* 00 */
2633   { REG_TABLE (REG_0F00 ) },
2634   { REG_TABLE (REG_0F01 ) },
2635   { "larS",             { Gv, Ew }, 0 },
2636   { "lslS",             { Gv, Ew }, 0 },
2637   { Bad_Opcode },
2638   { "syscall",          { XX }, 0 },
2639   { "clts",             { XX }, 0 },
2640   { "sysret%LP",                { XX }, 0 },
2641   /* 08 */
2642   { "invd",             { XX }, 0 },
2643   { PREFIX_TABLE (PREFIX_0F09) },
2644   { Bad_Opcode },
2645   { "ud2",              { XX }, 0 },
2646   { Bad_Opcode },
2647   { REG_TABLE (REG_0F0D) },
2648   { "femms",            { XX }, 0 },
2649   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2650   /* 10 */
2651   { PREFIX_TABLE (PREFIX_0F10) },
2652   { PREFIX_TABLE (PREFIX_0F11) },
2653   { PREFIX_TABLE (PREFIX_0F12) },
2654   { MOD_TABLE (MOD_0F13) },
2655   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2656   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2657   { PREFIX_TABLE (PREFIX_0F16) },
2658   { MOD_TABLE (MOD_0F17) },
2659   /* 18 */
2660   { REG_TABLE (REG_0F18) },
2661   { "nopQ",             { Ev }, 0 },
2662   { PREFIX_TABLE (PREFIX_0F1A) },
2663   { PREFIX_TABLE (PREFIX_0F1B) },
2664   { PREFIX_TABLE (PREFIX_0F1C) },
2665   { "nopQ",             { Ev }, 0 },
2666   { PREFIX_TABLE (PREFIX_0F1E) },
2667   { "nopQ",             { Ev }, 0 },
2668   /* 20 */
2669   { "movZ",             { Rm, Cm }, 0 },
2670   { "movZ",             { Rm, Dm }, 0 },
2671   { "movZ",             { Cm, Rm }, 0 },
2672   { "movZ",             { Dm, Rm }, 0 },
2673   { MOD_TABLE (MOD_0F24) },
2674   { Bad_Opcode },
2675   { MOD_TABLE (MOD_0F26) },
2676   { Bad_Opcode },
2677   /* 28 */
2678   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2679   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2680   { PREFIX_TABLE (PREFIX_0F2A) },
2681   { PREFIX_TABLE (PREFIX_0F2B) },
2682   { PREFIX_TABLE (PREFIX_0F2C) },
2683   { PREFIX_TABLE (PREFIX_0F2D) },
2684   { PREFIX_TABLE (PREFIX_0F2E) },
2685   { PREFIX_TABLE (PREFIX_0F2F) },
2686   /* 30 */
2687   { "wrmsr",            { XX }, 0 },
2688   { "rdtsc",            { XX }, 0 },
2689   { "rdmsr",            { XX }, 0 },
2690   { "rdpmc",            { XX }, 0 },
2691   { "sysenter",         { XX }, 0 },
2692   { "sysexit",          { XX }, 0 },
2693   { Bad_Opcode },
2694   { "getsec",           { XX }, 0 },
2695   /* 38 */
2696   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2697   { Bad_Opcode },
2698   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2699   { Bad_Opcode },
2700   { Bad_Opcode },
2701   { Bad_Opcode },
2702   { Bad_Opcode },
2703   { Bad_Opcode },
2704   /* 40 */
2705   { "cmovoS",           { Gv, Ev }, 0 },
2706   { "cmovnoS",          { Gv, Ev }, 0 },
2707   { "cmovbS",           { Gv, Ev }, 0 },
2708   { "cmovaeS",          { Gv, Ev }, 0 },
2709   { "cmoveS",           { Gv, Ev }, 0 },
2710   { "cmovneS",          { Gv, Ev }, 0 },
2711   { "cmovbeS",          { Gv, Ev }, 0 },
2712   { "cmovaS",           { Gv, Ev }, 0 },
2713   /* 48 */
2714   { "cmovsS",           { Gv, Ev }, 0 },
2715   { "cmovnsS",          { Gv, Ev }, 0 },
2716   { "cmovpS",           { Gv, Ev }, 0 },
2717   { "cmovnpS",          { Gv, Ev }, 0 },
2718   { "cmovlS",           { Gv, Ev }, 0 },
2719   { "cmovgeS",          { Gv, Ev }, 0 },
2720   { "cmovleS",          { Gv, Ev }, 0 },
2721   { "cmovgS",           { Gv, Ev }, 0 },
2722   /* 50 */
2723   { MOD_TABLE (MOD_0F51) },
2724   { PREFIX_TABLE (PREFIX_0F51) },
2725   { PREFIX_TABLE (PREFIX_0F52) },
2726   { PREFIX_TABLE (PREFIX_0F53) },
2727   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2728   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2729   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2730   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2731   /* 58 */
2732   { PREFIX_TABLE (PREFIX_0F58) },
2733   { PREFIX_TABLE (PREFIX_0F59) },
2734   { PREFIX_TABLE (PREFIX_0F5A) },
2735   { PREFIX_TABLE (PREFIX_0F5B) },
2736   { PREFIX_TABLE (PREFIX_0F5C) },
2737   { PREFIX_TABLE (PREFIX_0F5D) },
2738   { PREFIX_TABLE (PREFIX_0F5E) },
2739   { PREFIX_TABLE (PREFIX_0F5F) },
2740   /* 60 */
2741   { PREFIX_TABLE (PREFIX_0F60) },
2742   { PREFIX_TABLE (PREFIX_0F61) },
2743   { PREFIX_TABLE (PREFIX_0F62) },
2744   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2745   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2746   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2747   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2748   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2749   /* 68 */
2750   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2751   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2752   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2753   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2754   { PREFIX_TABLE (PREFIX_0F6C) },
2755   { PREFIX_TABLE (PREFIX_0F6D) },
2756   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2757   { PREFIX_TABLE (PREFIX_0F6F) },
2758   /* 70 */
2759   { PREFIX_TABLE (PREFIX_0F70) },
2760   { REG_TABLE (REG_0F71) },
2761   { REG_TABLE (REG_0F72) },
2762   { REG_TABLE (REG_0F73) },
2763   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2764   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2765   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2766   { "emms",             { XX }, PREFIX_OPCODE },
2767   /* 78 */
2768   { PREFIX_TABLE (PREFIX_0F78) },
2769   { PREFIX_TABLE (PREFIX_0F79) },
2770   { Bad_Opcode },
2771   { Bad_Opcode },
2772   { PREFIX_TABLE (PREFIX_0F7C) },
2773   { PREFIX_TABLE (PREFIX_0F7D) },
2774   { PREFIX_TABLE (PREFIX_0F7E) },
2775   { PREFIX_TABLE (PREFIX_0F7F) },
2776   /* 80 */
2777   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2778   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2779   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2780   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2781   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2782   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2783   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2784   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2785   /* 88 */
2786   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2787   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2788   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2789   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2790   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2791   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2792   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2793   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2794   /* 90 */
2795   { "seto",             { Eb }, 0 },
2796   { "setno",            { Eb }, 0 },
2797   { "setb",             { Eb }, 0 },
2798   { "setae",            { Eb }, 0 },
2799   { "sete",             { Eb }, 0 },
2800   { "setne",            { Eb }, 0 },
2801   { "setbe",            { Eb }, 0 },
2802   { "seta",             { Eb }, 0 },
2803   /* 98 */
2804   { "sets",             { Eb }, 0 },
2805   { "setns",            { Eb }, 0 },
2806   { "setp",             { Eb }, 0 },
2807   { "setnp",            { Eb }, 0 },
2808   { "setl",             { Eb }, 0 },
2809   { "setge",            { Eb }, 0 },
2810   { "setle",            { Eb }, 0 },
2811   { "setg",             { Eb }, 0 },
2812   /* a0 */
2813   { "pushT",            { fs }, 0 },
2814   { "popT",             { fs }, 0 },
2815   { "cpuid",            { XX }, 0 },
2816   { "btS",              { Ev, Gv }, 0 },
2817   { "shldS",            { Ev, Gv, Ib }, 0 },
2818   { "shldS",            { Ev, Gv, CL }, 0 },
2819   { REG_TABLE (REG_0FA6) },
2820   { REG_TABLE (REG_0FA7) },
2821   /* a8 */
2822   { "pushT",            { gs }, 0 },
2823   { "popT",             { gs }, 0 },
2824   { "rsm",              { XX }, 0 },
2825   { "btsS",             { Evh1, Gv }, 0 },
2826   { "shrdS",            { Ev, Gv, Ib }, 0 },
2827   { "shrdS",            { Ev, Gv, CL }, 0 },
2828   { REG_TABLE (REG_0FAE) },
2829   { "imulS",            { Gv, Ev }, 0 },
2830   /* b0 */
2831   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2832   { "cmpxchgS",         { Evh1, Gv }, 0 },
2833   { MOD_TABLE (MOD_0FB2) },
2834   { "btrS",             { Evh1, Gv }, 0 },
2835   { MOD_TABLE (MOD_0FB4) },
2836   { MOD_TABLE (MOD_0FB5) },
2837   { "movz{bR|x}",       { Gv, Eb }, 0 },
2838   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2839   /* b8 */
2840   { PREFIX_TABLE (PREFIX_0FB8) },
2841   { "ud1S",             { Gv, Ev }, 0 },
2842   { REG_TABLE (REG_0FBA) },
2843   { "btcS",             { Evh1, Gv }, 0 },
2844   { PREFIX_TABLE (PREFIX_0FBC) },
2845   { PREFIX_TABLE (PREFIX_0FBD) },
2846   { "movs{bR|x}",       { Gv, Eb }, 0 },
2847   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2848   /* c0 */
2849   { "xaddB",            { Ebh1, Gb }, 0 },
2850   { "xaddS",            { Evh1, Gv }, 0 },
2851   { PREFIX_TABLE (PREFIX_0FC2) },
2852   { MOD_TABLE (MOD_0FC3) },
2853   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2854   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2855   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2856   { REG_TABLE (REG_0FC7) },
2857   /* c8 */
2858   { "bswap",            { RMeAX }, 0 },
2859   { "bswap",            { RMeCX }, 0 },
2860   { "bswap",            { RMeDX }, 0 },
2861   { "bswap",            { RMeBX }, 0 },
2862   { "bswap",            { RMeSP }, 0 },
2863   { "bswap",            { RMeBP }, 0 },
2864   { "bswap",            { RMeSI }, 0 },
2865   { "bswap",            { RMeDI }, 0 },
2866   /* d0 */
2867   { PREFIX_TABLE (PREFIX_0FD0) },
2868   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2869   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2870   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2871   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2872   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2873   { PREFIX_TABLE (PREFIX_0FD6) },
2874   { MOD_TABLE (MOD_0FD7) },
2875   /* d8 */
2876   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2877   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2878   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2879   { "pand",             { MX, EM }, PREFIX_OPCODE },
2880   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2881   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2882   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2883   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2884   /* e0 */
2885   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2886   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2887   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2888   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2889   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2890   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2891   { PREFIX_TABLE (PREFIX_0FE6) },
2892   { PREFIX_TABLE (PREFIX_0FE7) },
2893   /* e8 */
2894   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2895   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2896   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2897   { "por",              { MX, EM }, PREFIX_OPCODE },
2898   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2899   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2900   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2901   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2902   /* f0 */
2903   { PREFIX_TABLE (PREFIX_0FF0) },
2904   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2905   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2906   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2907   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2908   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2909   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2910   { PREFIX_TABLE (PREFIX_0FF7) },
2911   /* f8 */
2912   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2913   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2914   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2915   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2916   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2917   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2918   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2919   { "ud0S",             { Gv, Ev }, 0 },
2920 };
2921
2922 static const unsigned char onebyte_has_modrm[256] = {
2923   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2924   /*       -------------------------------        */
2925   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2926   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2927   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2928   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2929   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2930   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2931   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2932   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2933   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2934   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2935   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2936   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2937   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2938   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2939   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2940   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2941   /*       -------------------------------        */
2942   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2943 };
2944
2945 static const unsigned char twobyte_has_modrm[256] = {
2946   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2947   /*       -------------------------------        */
2948   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2949   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2950   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2951   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2952   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2953   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2954   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2955   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2956   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2957   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2958   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2959   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2960   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2961   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2962   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2963   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2964   /*       -------------------------------        */
2965   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2966 };
2967
2968 static char obuf[100];
2969 static char *obufp;
2970 static char *mnemonicendp;
2971 static char scratchbuf[100];
2972 static unsigned char *start_codep;
2973 static unsigned char *insn_codep;
2974 static unsigned char *codep;
2975 static unsigned char *end_codep;
2976 static int last_lock_prefix;
2977 static int last_repz_prefix;
2978 static int last_repnz_prefix;
2979 static int last_data_prefix;
2980 static int last_addr_prefix;
2981 static int last_rex_prefix;
2982 static int last_seg_prefix;
2983 static int fwait_prefix;
2984 /* The active segment register prefix.  */
2985 static int active_seg_prefix;
2986 #define MAX_CODE_LENGTH 15
2987 /* We can up to 14 prefixes since the maximum instruction length is
2988    15bytes.  */
2989 static int all_prefixes[MAX_CODE_LENGTH - 1];
2990 static disassemble_info *the_info;
2991 static struct
2992   {
2993     int mod;
2994     int reg;
2995     int rm;
2996   }
2997 modrm;
2998 static unsigned char need_modrm;
2999 static struct
3000   {
3001     int scale;
3002     int index;
3003     int base;
3004   }
3005 sib;
3006 static struct
3007   {
3008     int register_specifier;
3009     int length;
3010     int prefix;
3011     int w;
3012     int evex;
3013     int r;
3014     int v;
3015     int mask_register_specifier;
3016     int zeroing;
3017     int ll;
3018     int b;
3019   }
3020 vex;
3021 static unsigned char need_vex;
3022 static unsigned char need_vex_reg;
3023 static unsigned char vex_w_done;
3024
3025 struct op
3026   {
3027     const char *name;
3028     unsigned int len;
3029   };
3030
3031 /* If we are accessing mod/rm/reg without need_modrm set, then the
3032    values are stale.  Hitting this abort likely indicates that you
3033    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3034 #define MODRM_CHECK  if (!need_modrm) abort ()
3035
3036 static const char **names64;
3037 static const char **names32;
3038 static const char **names16;
3039 static const char **names8;
3040 static const char **names8rex;
3041 static const char **names_seg;
3042 static const char *index64;
3043 static const char *index32;
3044 static const char **index16;
3045 static const char **names_bnd;
3046
3047 static const char *intel_names64[] = {
3048   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3049   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3050 };
3051 static const char *intel_names32[] = {
3052   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3053   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3054 };
3055 static const char *intel_names16[] = {
3056   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3057   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3058 };
3059 static const char *intel_names8[] = {
3060   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3061 };
3062 static const char *intel_names8rex[] = {
3063   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3064   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3065 };
3066 static const char *intel_names_seg[] = {
3067   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3068 };
3069 static const char *intel_index64 = "riz";
3070 static const char *intel_index32 = "eiz";
3071 static const char *intel_index16[] = {
3072   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3073 };
3074
3075 static const char *att_names64[] = {
3076   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3077   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3078 };
3079 static const char *att_names32[] = {
3080   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3081   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3082 };
3083 static const char *att_names16[] = {
3084   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3085   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3086 };
3087 static const char *att_names8[] = {
3088   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3089 };
3090 static const char *att_names8rex[] = {
3091   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3092   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3093 };
3094 static const char *att_names_seg[] = {
3095   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3096 };
3097 static const char *att_index64 = "%riz";
3098 static const char *att_index32 = "%eiz";
3099 static const char *att_index16[] = {
3100   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3101 };
3102
3103 static const char **names_mm;
3104 static const char *intel_names_mm[] = {
3105   "mm0", "mm1", "mm2", "mm3",
3106   "mm4", "mm5", "mm6", "mm7"
3107 };
3108 static const char *att_names_mm[] = {
3109   "%mm0", "%mm1", "%mm2", "%mm3",
3110   "%mm4", "%mm5", "%mm6", "%mm7"
3111 };
3112
3113 static const char *intel_names_bnd[] = {
3114   "bnd0", "bnd1", "bnd2", "bnd3"
3115 };
3116
3117 static const char *att_names_bnd[] = {
3118   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3119 };
3120
3121 static const char **names_xmm;
3122 static const char *intel_names_xmm[] = {
3123   "xmm0", "xmm1", "xmm2", "xmm3",
3124   "xmm4", "xmm5", "xmm6", "xmm7",
3125   "xmm8", "xmm9", "xmm10", "xmm11",
3126   "xmm12", "xmm13", "xmm14", "xmm15",
3127   "xmm16", "xmm17", "xmm18", "xmm19",
3128   "xmm20", "xmm21", "xmm22", "xmm23",
3129   "xmm24", "xmm25", "xmm26", "xmm27",
3130   "xmm28", "xmm29", "xmm30", "xmm31"
3131 };
3132 static const char *att_names_xmm[] = {
3133   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3134   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3135   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3136   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3137   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3138   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3139   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3140   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3141 };
3142
3143 static const char **names_ymm;
3144 static const char *intel_names_ymm[] = {
3145   "ymm0", "ymm1", "ymm2", "ymm3",
3146   "ymm4", "ymm5", "ymm6", "ymm7",
3147   "ymm8", "ymm9", "ymm10", "ymm11",
3148   "ymm12", "ymm13", "ymm14", "ymm15",
3149   "ymm16", "ymm17", "ymm18", "ymm19",
3150   "ymm20", "ymm21", "ymm22", "ymm23",
3151   "ymm24", "ymm25", "ymm26", "ymm27",
3152   "ymm28", "ymm29", "ymm30", "ymm31"
3153 };
3154 static const char *att_names_ymm[] = {
3155   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3156   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3157   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3158   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3159   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3160   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3161   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3162   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3163 };
3164
3165 static const char **names_zmm;
3166 static const char *intel_names_zmm[] = {
3167   "zmm0", "zmm1", "zmm2", "zmm3",
3168   "zmm4", "zmm5", "zmm6", "zmm7",
3169   "zmm8", "zmm9", "zmm10", "zmm11",
3170   "zmm12", "zmm13", "zmm14", "zmm15",
3171   "zmm16", "zmm17", "zmm18", "zmm19",
3172   "zmm20", "zmm21", "zmm22", "zmm23",
3173   "zmm24", "zmm25", "zmm26", "zmm27",
3174   "zmm28", "zmm29", "zmm30", "zmm31"
3175 };
3176 static const char *att_names_zmm[] = {
3177   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3178   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3179   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3180   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3181   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3182   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3183   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3184   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3185 };
3186
3187 static const char **names_mask;
3188 static const char *intel_names_mask[] = {
3189   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3190 };
3191 static const char *att_names_mask[] = {
3192   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3193 };
3194
3195 static const char *names_rounding[] =
3196 {
3197   "{rn-sae}",
3198   "{rd-sae}",
3199   "{ru-sae}",
3200   "{rz-sae}"
3201 };
3202
3203 static const struct dis386 reg_table[][8] = {
3204   /* REG_80 */
3205   {
3206     { "addA",   { Ebh1, Ib }, 0 },
3207     { "orA",    { Ebh1, Ib }, 0 },
3208     { "adcA",   { Ebh1, Ib }, 0 },
3209     { "sbbA",   { Ebh1, Ib }, 0 },
3210     { "andA",   { Ebh1, Ib }, 0 },
3211     { "subA",   { Ebh1, Ib }, 0 },
3212     { "xorA",   { Ebh1, Ib }, 0 },
3213     { "cmpA",   { Eb, Ib }, 0 },
3214   },
3215   /* REG_81 */
3216   {
3217     { "addQ",   { Evh1, Iv }, 0 },
3218     { "orQ",    { Evh1, Iv }, 0 },
3219     { "adcQ",   { Evh1, Iv }, 0 },
3220     { "sbbQ",   { Evh1, Iv }, 0 },
3221     { "andQ",   { Evh1, Iv }, 0 },
3222     { "subQ",   { Evh1, Iv }, 0 },
3223     { "xorQ",   { Evh1, Iv }, 0 },
3224     { "cmpQ",   { Ev, Iv }, 0 },
3225   },
3226   /* REG_83 */
3227   {
3228     { "addQ",   { Evh1, sIb }, 0 },
3229     { "orQ",    { Evh1, sIb }, 0 },
3230     { "adcQ",   { Evh1, sIb }, 0 },
3231     { "sbbQ",   { Evh1, sIb }, 0 },
3232     { "andQ",   { Evh1, sIb }, 0 },
3233     { "subQ",   { Evh1, sIb }, 0 },
3234     { "xorQ",   { Evh1, sIb }, 0 },
3235     { "cmpQ",   { Ev, sIb }, 0 },
3236   },
3237   /* REG_8F */
3238   {
3239     { "popU",   { stackEv }, 0 },
3240     { XOP_8F_TABLE (XOP_09) },
3241     { Bad_Opcode },
3242     { Bad_Opcode },
3243     { Bad_Opcode },
3244     { XOP_8F_TABLE (XOP_09) },
3245   },
3246   /* REG_C0 */
3247   {
3248     { "rolA",   { Eb, Ib }, 0 },
3249     { "rorA",   { Eb, Ib }, 0 },
3250     { "rclA",   { Eb, Ib }, 0 },
3251     { "rcrA",   { Eb, Ib }, 0 },
3252     { "shlA",   { Eb, Ib }, 0 },
3253     { "shrA",   { Eb, Ib }, 0 },
3254     { "shlA",   { Eb, Ib }, 0 },
3255     { "sarA",   { Eb, Ib }, 0 },
3256   },
3257   /* REG_C1 */
3258   {
3259     { "rolQ",   { Ev, Ib }, 0 },
3260     { "rorQ",   { Ev, Ib }, 0 },
3261     { "rclQ",   { Ev, Ib }, 0 },
3262     { "rcrQ",   { Ev, Ib }, 0 },
3263     { "shlQ",   { Ev, Ib }, 0 },
3264     { "shrQ",   { Ev, Ib }, 0 },
3265     { "shlQ",   { Ev, Ib }, 0 },
3266     { "sarQ",   { Ev, Ib }, 0 },
3267   },
3268   /* REG_C6 */
3269   {
3270     { "movA",   { Ebh3, Ib }, 0 },
3271     { Bad_Opcode },
3272     { Bad_Opcode },
3273     { Bad_Opcode },
3274     { Bad_Opcode },
3275     { Bad_Opcode },
3276     { Bad_Opcode },
3277     { MOD_TABLE (MOD_C6_REG_7) },
3278   },
3279   /* REG_C7 */
3280   {
3281     { "movQ",   { Evh3, Iv }, 0 },
3282     { Bad_Opcode },
3283     { Bad_Opcode },
3284     { Bad_Opcode },
3285     { Bad_Opcode },
3286     { Bad_Opcode },
3287     { Bad_Opcode },
3288     { MOD_TABLE (MOD_C7_REG_7) },
3289   },
3290   /* REG_D0 */
3291   {
3292     { "rolA",   { Eb, I1 }, 0 },
3293     { "rorA",   { Eb, I1 }, 0 },
3294     { "rclA",   { Eb, I1 }, 0 },
3295     { "rcrA",   { Eb, I1 }, 0 },
3296     { "shlA",   { Eb, I1 }, 0 },
3297     { "shrA",   { Eb, I1 }, 0 },
3298     { "shlA",   { Eb, I1 }, 0 },
3299     { "sarA",   { Eb, I1 }, 0 },
3300   },
3301   /* REG_D1 */
3302   {
3303     { "rolQ",   { Ev, I1 }, 0 },
3304     { "rorQ",   { Ev, I1 }, 0 },
3305     { "rclQ",   { Ev, I1 }, 0 },
3306     { "rcrQ",   { Ev, I1 }, 0 },
3307     { "shlQ",   { Ev, I1 }, 0 },
3308     { "shrQ",   { Ev, I1 }, 0 },
3309     { "shlQ",   { Ev, I1 }, 0 },
3310     { "sarQ",   { Ev, I1 }, 0 },
3311   },
3312   /* REG_D2 */
3313   {
3314     { "rolA",   { Eb, CL }, 0 },
3315     { "rorA",   { Eb, CL }, 0 },
3316     { "rclA",   { Eb, CL }, 0 },
3317     { "rcrA",   { Eb, CL }, 0 },
3318     { "shlA",   { Eb, CL }, 0 },
3319     { "shrA",   { Eb, CL }, 0 },
3320     { "shlA",   { Eb, CL }, 0 },
3321     { "sarA",   { Eb, CL }, 0 },
3322   },
3323   /* REG_D3 */
3324   {
3325     { "rolQ",   { Ev, CL }, 0 },
3326     { "rorQ",   { Ev, CL }, 0 },
3327     { "rclQ",   { Ev, CL }, 0 },
3328     { "rcrQ",   { Ev, CL }, 0 },
3329     { "shlQ",   { Ev, CL }, 0 },
3330     { "shrQ",   { Ev, CL }, 0 },
3331     { "shlQ",   { Ev, CL }, 0 },
3332     { "sarQ",   { Ev, CL }, 0 },
3333   },
3334   /* REG_F6 */
3335   {
3336     { "testA",  { Eb, Ib }, 0 },
3337     { "testA",  { Eb, Ib }, 0 },
3338     { "notA",   { Ebh1 }, 0 },
3339     { "negA",   { Ebh1 }, 0 },
3340     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3341     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3342     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3343     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3344   },
3345   /* REG_F7 */
3346   {
3347     { "testQ",  { Ev, Iv }, 0 },
3348     { "testQ",  { Ev, Iv }, 0 },
3349     { "notQ",   { Evh1 }, 0 },
3350     { "negQ",   { Evh1 }, 0 },
3351     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3352     { "imulQ",  { Ev }, 0 },
3353     { "divQ",   { Ev }, 0 },
3354     { "idivQ",  { Ev }, 0 },
3355   },
3356   /* REG_FE */
3357   {
3358     { "incA",   { Ebh1 }, 0 },
3359     { "decA",   { Ebh1 }, 0 },
3360   },
3361   /* REG_FF */
3362   {
3363     { "incQ",   { Evh1 }, 0 },
3364     { "decQ",   { Evh1 }, 0 },
3365     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3366     { MOD_TABLE (MOD_FF_REG_3) },
3367     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3368     { MOD_TABLE (MOD_FF_REG_5) },
3369     { "pushU",  { stackEv }, 0 },
3370     { Bad_Opcode },
3371   },
3372   /* REG_0F00 */
3373   {
3374     { "sldtD",  { Sv }, 0 },
3375     { "strD",   { Sv }, 0 },
3376     { "lldt",   { Ew }, 0 },
3377     { "ltr",    { Ew }, 0 },
3378     { "verr",   { Ew }, 0 },
3379     { "verw",   { Ew }, 0 },
3380     { Bad_Opcode },
3381     { Bad_Opcode },
3382   },
3383   /* REG_0F01 */
3384   {
3385     { MOD_TABLE (MOD_0F01_REG_0) },
3386     { MOD_TABLE (MOD_0F01_REG_1) },
3387     { MOD_TABLE (MOD_0F01_REG_2) },
3388     { MOD_TABLE (MOD_0F01_REG_3) },
3389     { "smswD",  { Sv }, 0 },
3390     { MOD_TABLE (MOD_0F01_REG_5) },
3391     { "lmsw",   { Ew }, 0 },
3392     { MOD_TABLE (MOD_0F01_REG_7) },
3393   },
3394   /* REG_0F0D */
3395   {
3396     { "prefetch",       { Mb }, 0 },
3397     { "prefetchw",      { Mb }, 0 },
3398     { "prefetchwt1",    { Mb }, 0 },
3399     { "prefetch",       { Mb }, 0 },
3400     { "prefetch",       { Mb }, 0 },
3401     { "prefetch",       { Mb }, 0 },
3402     { "prefetch",       { Mb }, 0 },
3403     { "prefetch",       { Mb }, 0 },
3404   },
3405   /* REG_0F18 */
3406   {
3407     { MOD_TABLE (MOD_0F18_REG_0) },
3408     { MOD_TABLE (MOD_0F18_REG_1) },
3409     { MOD_TABLE (MOD_0F18_REG_2) },
3410     { MOD_TABLE (MOD_0F18_REG_3) },
3411     { MOD_TABLE (MOD_0F18_REG_4) },
3412     { MOD_TABLE (MOD_0F18_REG_5) },
3413     { MOD_TABLE (MOD_0F18_REG_6) },
3414     { MOD_TABLE (MOD_0F18_REG_7) },
3415   },
3416   /* REG_0F1C_MOD_0 */
3417   {
3418     { "cldemote",       { Mb }, 0 },
3419     { "nopQ",           { Ev }, 0 },
3420     { "nopQ",           { Ev }, 0 },
3421     { "nopQ",           { Ev }, 0 },
3422     { "nopQ",           { Ev }, 0 },
3423     { "nopQ",           { Ev }, 0 },
3424     { "nopQ",           { Ev }, 0 },
3425     { "nopQ",           { Ev }, 0 },
3426   },
3427   /* REG_0F1E_MOD_3 */
3428   {
3429     { "nopQ",           { Ev }, 0 },
3430     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3431     { "nopQ",           { Ev }, 0 },
3432     { "nopQ",           { Ev }, 0 },
3433     { "nopQ",           { Ev }, 0 },
3434     { "nopQ",           { Ev }, 0 },
3435     { "nopQ",           { Ev }, 0 },
3436     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3437   },
3438   /* REG_0F71 */
3439   {
3440     { Bad_Opcode },
3441     { Bad_Opcode },
3442     { MOD_TABLE (MOD_0F71_REG_2) },
3443     { Bad_Opcode },
3444     { MOD_TABLE (MOD_0F71_REG_4) },
3445     { Bad_Opcode },
3446     { MOD_TABLE (MOD_0F71_REG_6) },
3447   },
3448   /* REG_0F72 */
3449   {
3450     { Bad_Opcode },
3451     { Bad_Opcode },
3452     { MOD_TABLE (MOD_0F72_REG_2) },
3453     { Bad_Opcode },
3454     { MOD_TABLE (MOD_0F72_REG_4) },
3455     { Bad_Opcode },
3456     { MOD_TABLE (MOD_0F72_REG_6) },
3457   },
3458   /* REG_0F73 */
3459   {
3460     { Bad_Opcode },
3461     { Bad_Opcode },
3462     { MOD_TABLE (MOD_0F73_REG_2) },
3463     { MOD_TABLE (MOD_0F73_REG_3) },
3464     { Bad_Opcode },
3465     { Bad_Opcode },
3466     { MOD_TABLE (MOD_0F73_REG_6) },
3467     { MOD_TABLE (MOD_0F73_REG_7) },
3468   },
3469   /* REG_0FA6 */
3470   {
3471     { "montmul",        { { OP_0f07, 0 } }, 0 },
3472     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3473     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3474   },
3475   /* REG_0FA7 */
3476   {
3477     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3478     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3479     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3480     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3481     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3482     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3483   },
3484   /* REG_0FAE */
3485   {
3486     { MOD_TABLE (MOD_0FAE_REG_0) },
3487     { MOD_TABLE (MOD_0FAE_REG_1) },
3488     { MOD_TABLE (MOD_0FAE_REG_2) },
3489     { MOD_TABLE (MOD_0FAE_REG_3) },
3490     { MOD_TABLE (MOD_0FAE_REG_4) },
3491     { MOD_TABLE (MOD_0FAE_REG_5) },
3492     { MOD_TABLE (MOD_0FAE_REG_6) },
3493     { MOD_TABLE (MOD_0FAE_REG_7) },
3494   },
3495   /* REG_0FBA */
3496   {
3497     { Bad_Opcode },
3498     { Bad_Opcode },
3499     { Bad_Opcode },
3500     { Bad_Opcode },
3501     { "btQ",    { Ev, Ib }, 0 },
3502     { "btsQ",   { Evh1, Ib }, 0 },
3503     { "btrQ",   { Evh1, Ib }, 0 },
3504     { "btcQ",   { Evh1, Ib }, 0 },
3505   },
3506   /* REG_0FC7 */
3507   {
3508     { Bad_Opcode },
3509     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3510     { Bad_Opcode },
3511     { MOD_TABLE (MOD_0FC7_REG_3) },
3512     { MOD_TABLE (MOD_0FC7_REG_4) },
3513     { MOD_TABLE (MOD_0FC7_REG_5) },
3514     { MOD_TABLE (MOD_0FC7_REG_6) },
3515     { MOD_TABLE (MOD_0FC7_REG_7) },
3516   },
3517   /* REG_VEX_0F71 */
3518   {
3519     { Bad_Opcode },
3520     { Bad_Opcode },
3521     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3522     { Bad_Opcode },
3523     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3524     { Bad_Opcode },
3525     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3526   },
3527   /* REG_VEX_0F72 */
3528   {
3529     { Bad_Opcode },
3530     { Bad_Opcode },
3531     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3532     { Bad_Opcode },
3533     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3534     { Bad_Opcode },
3535     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3536   },
3537   /* REG_VEX_0F73 */
3538   {
3539     { Bad_Opcode },
3540     { Bad_Opcode },
3541     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3542     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3543     { Bad_Opcode },
3544     { Bad_Opcode },
3545     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3546     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3547   },
3548   /* REG_VEX_0FAE */
3549   {
3550     { Bad_Opcode },
3551     { Bad_Opcode },
3552     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3553     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3554   },
3555   /* REG_VEX_0F38F3 */
3556   {
3557     { Bad_Opcode },
3558     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3559     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3560     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3561   },
3562   /* REG_XOP_LWPCB */
3563   {
3564     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3565     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3566   },
3567   /* REG_XOP_LWP */
3568   {
3569     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3570     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3571   },
3572   /* REG_XOP_TBM_01 */
3573   {
3574     { Bad_Opcode },
3575     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3576     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3577     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3578     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3579     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3580     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3581     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3582   },
3583   /* REG_XOP_TBM_02 */
3584   {
3585     { Bad_Opcode },
3586     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3587     { Bad_Opcode },
3588     { Bad_Opcode },
3589     { Bad_Opcode },
3590     { Bad_Opcode },
3591     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3592   },
3593 #define NEED_REG_TABLE
3594 #include "i386-dis-evex.h"
3595 #undef NEED_REG_TABLE
3596 };
3597
3598 static const struct dis386 prefix_table[][4] = {
3599   /* PREFIX_90 */
3600   {
3601     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3602     { "pause", { XX }, 0 },
3603     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3604     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3605   },
3606
3607   /* PREFIX_MOD_0_0F01_REG_5 */
3608   {
3609     { Bad_Opcode },
3610     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3611   },
3612
3613   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3614   {
3615     { Bad_Opcode },
3616     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3617   },
3618
3619   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3620   {
3621     { Bad_Opcode },
3622     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3623   },
3624
3625   /* PREFIX_0F09 */
3626   {
3627     { "wbinvd",   { XX }, 0 },
3628     { "wbnoinvd", { XX }, 0 },
3629   },
3630
3631   /* PREFIX_0F10 */
3632   {
3633     { "movups", { XM, EXx }, PREFIX_OPCODE },
3634     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3635     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3636     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3637   },
3638
3639   /* PREFIX_0F11 */
3640   {
3641     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3642     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3643     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3644     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3645   },
3646
3647   /* PREFIX_0F12 */
3648   {
3649     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3650     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3651     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3652     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3653   },
3654
3655   /* PREFIX_0F16 */
3656   {
3657     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3658     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3659     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3660   },
3661
3662   /* PREFIX_0F1A */
3663   {
3664     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3665     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3666     { "bndmov", { Gbnd, Ebnd }, 0 },
3667     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3668   },
3669
3670   /* PREFIX_0F1B */
3671   {
3672     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3673     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3674     { "bndmov", { EbndS, Gbnd }, 0 },
3675     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3676   },
3677
3678   /* PREFIX_0F1C */
3679   {
3680     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3681     { "nopQ",   { Ev }, PREFIX_OPCODE },
3682     { "nopQ",   { Ev }, PREFIX_OPCODE },
3683     { "nopQ",   { Ev }, PREFIX_OPCODE },
3684   },
3685
3686   /* PREFIX_0F1E */
3687   {
3688     { "nopQ",   { Ev }, PREFIX_OPCODE },
3689     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3690     { "nopQ",   { Ev }, PREFIX_OPCODE },
3691     { "nopQ",   { Ev }, PREFIX_OPCODE },
3692   },
3693
3694   /* PREFIX_0F2A */
3695   {
3696     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3697     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3698     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3699     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3700   },
3701
3702   /* PREFIX_0F2B */
3703   {
3704     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3705     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3706     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3707     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3708   },
3709
3710   /* PREFIX_0F2C */
3711   {
3712     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3713     { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3714     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3715     { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3716   },
3717
3718   /* PREFIX_0F2D */
3719   {
3720     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3721     { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3722     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3723     { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3724   },
3725
3726   /* PREFIX_0F2E */
3727   {
3728     { "ucomiss",{ XM, EXd }, 0 },
3729     { Bad_Opcode },
3730     { "ucomisd",{ XM, EXq }, 0 },
3731   },
3732
3733   /* PREFIX_0F2F */
3734   {
3735     { "comiss", { XM, EXd }, 0 },
3736     { Bad_Opcode },
3737     { "comisd", { XM, EXq }, 0 },
3738   },
3739
3740   /* PREFIX_0F51 */
3741   {
3742     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3743     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3744     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3745     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3746   },
3747
3748   /* PREFIX_0F52 */
3749   {
3750     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3751     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3752   },
3753
3754   /* PREFIX_0F53 */
3755   {
3756     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3757     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3758   },
3759
3760   /* PREFIX_0F58 */
3761   {
3762     { "addps", { XM, EXx }, PREFIX_OPCODE },
3763     { "addss", { XM, EXd }, PREFIX_OPCODE },
3764     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3765     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3766   },
3767
3768   /* PREFIX_0F59 */
3769   {
3770     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3771     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3772     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3773     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3774   },
3775
3776   /* PREFIX_0F5A */
3777   {
3778     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3779     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3780     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3781     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3782   },
3783
3784   /* PREFIX_0F5B */
3785   {
3786     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3787     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3788     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3789   },
3790
3791   /* PREFIX_0F5C */
3792   {
3793     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3794     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3795     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3796     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3797   },
3798
3799   /* PREFIX_0F5D */
3800   {
3801     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3802     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3803     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3804     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3805   },
3806
3807   /* PREFIX_0F5E */
3808   {
3809     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3810     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3811     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3812     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3813   },
3814
3815   /* PREFIX_0F5F */
3816   {
3817     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3818     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3819     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3820     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3821   },
3822
3823   /* PREFIX_0F60 */
3824   {
3825     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3826     { Bad_Opcode },
3827     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3828   },
3829
3830   /* PREFIX_0F61 */
3831   {
3832     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3833     { Bad_Opcode },
3834     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3835   },
3836
3837   /* PREFIX_0F62 */
3838   {
3839     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3840     { Bad_Opcode },
3841     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3842   },
3843
3844   /* PREFIX_0F6C */
3845   {
3846     { Bad_Opcode },
3847     { Bad_Opcode },
3848     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3849   },
3850
3851   /* PREFIX_0F6D */
3852   {
3853     { Bad_Opcode },
3854     { Bad_Opcode },
3855     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3856   },
3857
3858   /* PREFIX_0F6F */
3859   {
3860     { "movq",   { MX, EM }, PREFIX_OPCODE },
3861     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3862     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3863   },
3864
3865   /* PREFIX_0F70 */
3866   {
3867     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3868     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3869     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3870     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3871   },
3872
3873   /* PREFIX_0F73_REG_3 */
3874   {
3875     { Bad_Opcode },
3876     { Bad_Opcode },
3877     { "psrldq", { XS, Ib }, 0 },
3878   },
3879
3880   /* PREFIX_0F73_REG_7 */
3881   {
3882     { Bad_Opcode },
3883     { Bad_Opcode },
3884     { "pslldq", { XS, Ib }, 0 },
3885   },
3886
3887   /* PREFIX_0F78 */
3888   {
3889     {"vmread",  { Em, Gm }, 0 },
3890     { Bad_Opcode },
3891     {"extrq",   { XS, Ib, Ib }, 0 },
3892     {"insertq", { XM, XS, Ib, Ib }, 0 },
3893   },
3894
3895   /* PREFIX_0F79 */
3896   {
3897     {"vmwrite", { Gm, Em }, 0 },
3898     { Bad_Opcode },
3899     {"extrq",   { XM, XS }, 0 },
3900     {"insertq", { XM, XS }, 0 },
3901   },
3902
3903   /* PREFIX_0F7C */
3904   {
3905     { Bad_Opcode },
3906     { Bad_Opcode },
3907     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3908     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3909   },
3910
3911   /* PREFIX_0F7D */
3912   {
3913     { Bad_Opcode },
3914     { Bad_Opcode },
3915     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3916     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3917   },
3918
3919   /* PREFIX_0F7E */
3920   {
3921     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3922     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3923     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3924   },
3925
3926   /* PREFIX_0F7F */
3927   {
3928     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3929     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3930     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3931   },
3932
3933   /* PREFIX_0FAE_REG_0 */
3934   {
3935     { Bad_Opcode },
3936     { "rdfsbase", { Ev }, 0 },
3937   },
3938
3939   /* PREFIX_0FAE_REG_1 */
3940   {
3941     { Bad_Opcode },
3942     { "rdgsbase", { Ev }, 0 },
3943   },
3944
3945   /* PREFIX_0FAE_REG_2 */
3946   {
3947     { Bad_Opcode },
3948     { "wrfsbase", { Ev }, 0 },
3949   },
3950
3951   /* PREFIX_0FAE_REG_3 */
3952   {
3953     { Bad_Opcode },
3954     { "wrgsbase", { Ev }, 0 },
3955   },
3956
3957   /* PREFIX_MOD_0_0FAE_REG_4 */
3958   {
3959     { "xsave",  { FXSAVE }, 0 },
3960     { "ptwrite%LQ", { Edq }, 0 },
3961   },
3962
3963   /* PREFIX_MOD_3_0FAE_REG_4 */
3964   {
3965     { Bad_Opcode },
3966     { "ptwrite%LQ", { Edq }, 0 },
3967   },
3968
3969   /* PREFIX_MOD_0_0FAE_REG_5 */
3970   {
3971     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3972   },
3973
3974   /* PREFIX_MOD_3_0FAE_REG_5 */
3975   {
3976     { "lfence",         { Skip_MODRM }, 0 },
3977     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3978   },
3979
3980   /* PREFIX_MOD_0_0FAE_REG_6 */
3981   {
3982     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3983     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3984     { "clwb",   { Mb }, PREFIX_OPCODE },
3985   },
3986
3987   /* PREFIX_MOD_1_0FAE_REG_6 */
3988   {
3989     { RM_TABLE (RM_0FAE_REG_6) },
3990     { "umonitor",       { Eva }, PREFIX_OPCODE },
3991     { "tpause", { Edq }, PREFIX_OPCODE },
3992     { "umwait", { Edq }, PREFIX_OPCODE },
3993   },
3994
3995   /* PREFIX_0FAE_REG_7 */
3996   {
3997     { "clflush",        { Mb }, 0 },
3998     { Bad_Opcode },
3999     { "clflushopt",     { Mb }, 0 },
4000   },
4001
4002   /* PREFIX_0FB8 */
4003   {
4004     { Bad_Opcode },
4005     { "popcntS", { Gv, Ev }, 0 },
4006   },
4007
4008   /* PREFIX_0FBC */
4009   {
4010     { "bsfS",   { Gv, Ev }, 0 },
4011     { "tzcntS", { Gv, Ev }, 0 },
4012     { "bsfS",   { Gv, Ev }, 0 },
4013   },
4014
4015   /* PREFIX_0FBD */
4016   {
4017     { "bsrS",   { Gv, Ev }, 0 },
4018     { "lzcntS", { Gv, Ev }, 0 },
4019     { "bsrS",   { Gv, Ev }, 0 },
4020   },
4021
4022   /* PREFIX_0FC2 */
4023   {
4024     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4025     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4026     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4027     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4028   },
4029
4030   /* PREFIX_MOD_0_0FC3 */
4031   {
4032     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4033   },
4034
4035   /* PREFIX_MOD_0_0FC7_REG_6 */
4036   {
4037     { "vmptrld",{ Mq }, 0 },
4038     { "vmxon",  { Mq }, 0 },
4039     { "vmclear",{ Mq }, 0 },
4040   },
4041
4042   /* PREFIX_MOD_3_0FC7_REG_6 */
4043   {
4044     { "rdrand", { Ev }, 0 },
4045     { Bad_Opcode },
4046     { "rdrand", { Ev }, 0 }
4047   },
4048
4049   /* PREFIX_MOD_3_0FC7_REG_7 */
4050   {
4051     { "rdseed", { Ev }, 0 },
4052     { "rdpid",  { Em }, 0 },
4053     { "rdseed", { Ev }, 0 },
4054   },
4055
4056   /* PREFIX_0FD0 */
4057   {
4058     { Bad_Opcode },
4059     { Bad_Opcode },
4060     { "addsubpd", { XM, EXx }, 0 },
4061     { "addsubps", { XM, EXx }, 0 },
4062   },
4063
4064   /* PREFIX_0FD6 */
4065   {
4066     { Bad_Opcode },
4067     { "movq2dq",{ XM, MS }, 0 },
4068     { "movq",   { EXqS, XM }, 0 },
4069     { "movdq2q",{ MX, XS }, 0 },
4070   },
4071
4072   /* PREFIX_0FE6 */
4073   {
4074     { Bad_Opcode },
4075     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4076     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4077     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4078   },
4079
4080   /* PREFIX_0FE7 */
4081   {
4082     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4083     { Bad_Opcode },
4084     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4085   },
4086
4087   /* PREFIX_0FF0 */
4088   {
4089     { Bad_Opcode },
4090     { Bad_Opcode },
4091     { Bad_Opcode },
4092     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4093   },
4094
4095   /* PREFIX_0FF7 */
4096   {
4097     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4098     { Bad_Opcode },
4099     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4100   },
4101
4102   /* PREFIX_0F3810 */
4103   {
4104     { Bad_Opcode },
4105     { Bad_Opcode },
4106     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4107   },
4108
4109   /* PREFIX_0F3814 */
4110   {
4111     { Bad_Opcode },
4112     { Bad_Opcode },
4113     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4114   },
4115
4116   /* PREFIX_0F3815 */
4117   {
4118     { Bad_Opcode },
4119     { Bad_Opcode },
4120     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4121   },
4122
4123   /* PREFIX_0F3817 */
4124   {
4125     { Bad_Opcode },
4126     { Bad_Opcode },
4127     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4128   },
4129
4130   /* PREFIX_0F3820 */
4131   {
4132     { Bad_Opcode },
4133     { Bad_Opcode },
4134     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4135   },
4136
4137   /* PREFIX_0F3821 */
4138   {
4139     { Bad_Opcode },
4140     { Bad_Opcode },
4141     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4142   },
4143
4144   /* PREFIX_0F3822 */
4145   {
4146     { Bad_Opcode },
4147     { Bad_Opcode },
4148     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4149   },
4150
4151   /* PREFIX_0F3823 */
4152   {
4153     { Bad_Opcode },
4154     { Bad_Opcode },
4155     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4156   },
4157
4158   /* PREFIX_0F3824 */
4159   {
4160     { Bad_Opcode },
4161     { Bad_Opcode },
4162     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4163   },
4164
4165   /* PREFIX_0F3825 */
4166   {
4167     { Bad_Opcode },
4168     { Bad_Opcode },
4169     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4170   },
4171
4172   /* PREFIX_0F3828 */
4173   {
4174     { Bad_Opcode },
4175     { Bad_Opcode },
4176     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4177   },
4178
4179   /* PREFIX_0F3829 */
4180   {
4181     { Bad_Opcode },
4182     { Bad_Opcode },
4183     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4184   },
4185
4186   /* PREFIX_0F382A */
4187   {
4188     { Bad_Opcode },
4189     { Bad_Opcode },
4190     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4191   },
4192
4193   /* PREFIX_0F382B */
4194   {
4195     { Bad_Opcode },
4196     { Bad_Opcode },
4197     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4198   },
4199
4200   /* PREFIX_0F3830 */
4201   {
4202     { Bad_Opcode },
4203     { Bad_Opcode },
4204     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4205   },
4206
4207   /* PREFIX_0F3831 */
4208   {
4209     { Bad_Opcode },
4210     { Bad_Opcode },
4211     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4212   },
4213
4214   /* PREFIX_0F3832 */
4215   {
4216     { Bad_Opcode },
4217     { Bad_Opcode },
4218     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4219   },
4220
4221   /* PREFIX_0F3833 */
4222   {
4223     { Bad_Opcode },
4224     { Bad_Opcode },
4225     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4226   },
4227
4228   /* PREFIX_0F3834 */
4229   {
4230     { Bad_Opcode },
4231     { Bad_Opcode },
4232     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4233   },
4234
4235   /* PREFIX_0F3835 */
4236   {
4237     { Bad_Opcode },
4238     { Bad_Opcode },
4239     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4240   },
4241
4242   /* PREFIX_0F3837 */
4243   {
4244     { Bad_Opcode },
4245     { Bad_Opcode },
4246     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4247   },
4248
4249   /* PREFIX_0F3838 */
4250   {
4251     { Bad_Opcode },
4252     { Bad_Opcode },
4253     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4254   },
4255
4256   /* PREFIX_0F3839 */
4257   {
4258     { Bad_Opcode },
4259     { Bad_Opcode },
4260     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4261   },
4262
4263   /* PREFIX_0F383A */
4264   {
4265     { Bad_Opcode },
4266     { Bad_Opcode },
4267     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4268   },
4269
4270   /* PREFIX_0F383B */
4271   {
4272     { Bad_Opcode },
4273     { Bad_Opcode },
4274     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4275   },
4276
4277   /* PREFIX_0F383C */
4278   {
4279     { Bad_Opcode },
4280     { Bad_Opcode },
4281     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4282   },
4283
4284   /* PREFIX_0F383D */
4285   {
4286     { Bad_Opcode },
4287     { Bad_Opcode },
4288     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4289   },
4290
4291   /* PREFIX_0F383E */
4292   {
4293     { Bad_Opcode },
4294     { Bad_Opcode },
4295     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4296   },
4297
4298   /* PREFIX_0F383F */
4299   {
4300     { Bad_Opcode },
4301     { Bad_Opcode },
4302     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4303   },
4304
4305   /* PREFIX_0F3840 */
4306   {
4307     { Bad_Opcode },
4308     { Bad_Opcode },
4309     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4310   },
4311
4312   /* PREFIX_0F3841 */
4313   {
4314     { Bad_Opcode },
4315     { Bad_Opcode },
4316     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4317   },
4318
4319   /* PREFIX_0F3880 */
4320   {
4321     { Bad_Opcode },
4322     { Bad_Opcode },
4323     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4324   },
4325
4326   /* PREFIX_0F3881 */
4327   {
4328     { Bad_Opcode },
4329     { Bad_Opcode },
4330     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4331   },
4332
4333   /* PREFIX_0F3882 */
4334   {
4335     { Bad_Opcode },
4336     { Bad_Opcode },
4337     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4338   },
4339
4340   /* PREFIX_0F38C8 */
4341   {
4342     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4343   },
4344
4345   /* PREFIX_0F38C9 */
4346   {
4347     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4348   },
4349
4350   /* PREFIX_0F38CA */
4351   {
4352     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4353   },
4354
4355   /* PREFIX_0F38CB */
4356   {
4357     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4358   },
4359
4360   /* PREFIX_0F38CC */
4361   {
4362     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4363   },
4364
4365   /* PREFIX_0F38CD */
4366   {
4367     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4368   },
4369
4370   /* PREFIX_0F38CF */
4371   {
4372     { Bad_Opcode },
4373     { Bad_Opcode },
4374     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4375   },
4376
4377   /* PREFIX_0F38DB */
4378   {
4379     { Bad_Opcode },
4380     { Bad_Opcode },
4381     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4382   },
4383
4384   /* PREFIX_0F38DC */
4385   {
4386     { Bad_Opcode },
4387     { Bad_Opcode },
4388     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4389   },
4390
4391   /* PREFIX_0F38DD */
4392   {
4393     { Bad_Opcode },
4394     { Bad_Opcode },
4395     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4396   },
4397
4398   /* PREFIX_0F38DE */
4399   {
4400     { Bad_Opcode },
4401     { Bad_Opcode },
4402     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4403   },
4404
4405   /* PREFIX_0F38DF */
4406   {
4407     { Bad_Opcode },
4408     { Bad_Opcode },
4409     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4410   },
4411
4412   /* PREFIX_0F38F0 */
4413   {
4414     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4415     { Bad_Opcode },
4416     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4417     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4418   },
4419
4420   /* PREFIX_0F38F1 */
4421   {
4422     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4423     { Bad_Opcode },
4424     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4425     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4426   },
4427
4428   /* PREFIX_0F38F5 */
4429   {
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4433   },
4434
4435   /* PREFIX_0F38F6 */
4436   {
4437     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4438     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4439     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4440     { Bad_Opcode },
4441   },
4442
4443   /* PREFIX_0F38F8 */
4444   {
4445     { Bad_Opcode },
4446     { Bad_Opcode },
4447     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4448   },
4449
4450   /* PREFIX_0F38F9 */
4451   {
4452     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4453   },
4454
4455   /* PREFIX_0F3A08 */
4456   {
4457     { Bad_Opcode },
4458     { Bad_Opcode },
4459     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4460   },
4461
4462   /* PREFIX_0F3A09 */
4463   {
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4467   },
4468
4469   /* PREFIX_0F3A0A */
4470   {
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4474   },
4475
4476   /* PREFIX_0F3A0B */
4477   {
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4481   },
4482
4483   /* PREFIX_0F3A0C */
4484   {
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4488   },
4489
4490   /* PREFIX_0F3A0D */
4491   {
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4495   },
4496
4497   /* PREFIX_0F3A0E */
4498   {
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4502   },
4503
4504   /* PREFIX_0F3A14 */
4505   {
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4509   },
4510
4511   /* PREFIX_0F3A15 */
4512   {
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4516   },
4517
4518   /* PREFIX_0F3A16 */
4519   {
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4523   },
4524
4525   /* PREFIX_0F3A17 */
4526   {
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4530   },
4531
4532   /* PREFIX_0F3A20 */
4533   {
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4537   },
4538
4539   /* PREFIX_0F3A21 */
4540   {
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4544   },
4545
4546   /* PREFIX_0F3A22 */
4547   {
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4551   },
4552
4553   /* PREFIX_0F3A40 */
4554   {
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4558   },
4559
4560   /* PREFIX_0F3A41 */
4561   {
4562     { Bad_Opcode },
4563     { Bad_Opcode },
4564     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4565   },
4566
4567   /* PREFIX_0F3A42 */
4568   {
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4572   },
4573
4574   /* PREFIX_0F3A44 */
4575   {
4576     { Bad_Opcode },
4577     { Bad_Opcode },
4578     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4579   },
4580
4581   /* PREFIX_0F3A60 */
4582   {
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4586   },
4587
4588   /* PREFIX_0F3A61 */
4589   {
4590     { Bad_Opcode },
4591     { Bad_Opcode },
4592     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4593   },
4594
4595   /* PREFIX_0F3A62 */
4596   {
4597     { Bad_Opcode },
4598     { Bad_Opcode },
4599     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4600   },
4601
4602   /* PREFIX_0F3A63 */
4603   {
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4607   },
4608
4609   /* PREFIX_0F3ACC */
4610   {
4611     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4612   },
4613
4614   /* PREFIX_0F3ACE */
4615   {
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4619   },
4620
4621   /* PREFIX_0F3ACF */
4622   {
4623     { Bad_Opcode },
4624     { Bad_Opcode },
4625     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4626   },
4627
4628   /* PREFIX_0F3ADF */
4629   {
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4633   },
4634
4635   /* PREFIX_VEX_0F10 */
4636   {
4637     { "vmovups",        { XM, EXx }, 0 },
4638     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4639     { "vmovupd",        { XM, EXx }, 0 },
4640     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4641   },
4642
4643   /* PREFIX_VEX_0F11 */
4644   {
4645     { "vmovups",        { EXxS, XM }, 0 },
4646     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4647     { "vmovupd",        { EXxS, XM }, 0 },
4648     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4649   },
4650
4651   /* PREFIX_VEX_0F12 */
4652   {
4653     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4654     { "vmovsldup",      { XM, EXx }, 0 },
4655     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4656     { "vmovddup",       { XM, EXymmq }, 0 },
4657   },
4658
4659   /* PREFIX_VEX_0F16 */
4660   {
4661     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4662     { "vmovshdup",      { XM, EXx }, 0 },
4663     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4664   },
4665
4666   /* PREFIX_VEX_0F2A */
4667   {
4668     { Bad_Opcode },
4669     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4670     { Bad_Opcode },
4671     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4672   },
4673
4674   /* PREFIX_VEX_0F2C */
4675   {
4676     { Bad_Opcode },
4677     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4678     { Bad_Opcode },
4679     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4680   },
4681
4682   /* PREFIX_VEX_0F2D */
4683   {
4684     { Bad_Opcode },
4685     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4686     { Bad_Opcode },
4687     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4688   },
4689
4690   /* PREFIX_VEX_0F2E */
4691   {
4692     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4693     { Bad_Opcode },
4694     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4695   },
4696
4697   /* PREFIX_VEX_0F2F */
4698   {
4699     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4700     { Bad_Opcode },
4701     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4702   },
4703
4704   /* PREFIX_VEX_0F41 */
4705   {
4706     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4707     { Bad_Opcode },
4708     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4709   },
4710
4711   /* PREFIX_VEX_0F42 */
4712   {
4713     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4714     { Bad_Opcode },
4715     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4716   },
4717
4718   /* PREFIX_VEX_0F44 */
4719   {
4720     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4721     { Bad_Opcode },
4722     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4723   },
4724
4725   /* PREFIX_VEX_0F45 */
4726   {
4727     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4728     { Bad_Opcode },
4729     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4730   },
4731
4732   /* PREFIX_VEX_0F46 */
4733   {
4734     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4735     { Bad_Opcode },
4736     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4737   },
4738
4739   /* PREFIX_VEX_0F47 */
4740   {
4741     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4742     { Bad_Opcode },
4743     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4744   },
4745
4746   /* PREFIX_VEX_0F4A */
4747   {
4748     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4749     { Bad_Opcode },
4750     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4751   },
4752
4753   /* PREFIX_VEX_0F4B */
4754   {
4755     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4756     { Bad_Opcode },
4757     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4758   },
4759
4760   /* PREFIX_VEX_0F51 */
4761   {
4762     { "vsqrtps",        { XM, EXx }, 0 },
4763     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4764     { "vsqrtpd",        { XM, EXx }, 0 },
4765     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4766   },
4767
4768   /* PREFIX_VEX_0F52 */
4769   {
4770     { "vrsqrtps",       { XM, EXx }, 0 },
4771     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4772   },
4773
4774   /* PREFIX_VEX_0F53 */
4775   {
4776     { "vrcpps",         { XM, EXx }, 0 },
4777     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4778   },
4779
4780   /* PREFIX_VEX_0F58 */
4781   {
4782     { "vaddps",         { XM, Vex, EXx }, 0 },
4783     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4784     { "vaddpd",         { XM, Vex, EXx }, 0 },
4785     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4786   },
4787
4788   /* PREFIX_VEX_0F59 */
4789   {
4790     { "vmulps",         { XM, Vex, EXx }, 0 },
4791     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4792     { "vmulpd",         { XM, Vex, EXx }, 0 },
4793     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4794   },
4795
4796   /* PREFIX_VEX_0F5A */
4797   {
4798     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4799     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4800     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4801     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4802   },
4803
4804   /* PREFIX_VEX_0F5B */
4805   {
4806     { "vcvtdq2ps",      { XM, EXx }, 0 },
4807     { "vcvttps2dq",     { XM, EXx }, 0 },
4808     { "vcvtps2dq",      { XM, EXx }, 0 },
4809   },
4810
4811   /* PREFIX_VEX_0F5C */
4812   {
4813     { "vsubps",         { XM, Vex, EXx }, 0 },
4814     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4815     { "vsubpd",         { XM, Vex, EXx }, 0 },
4816     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4817   },
4818
4819   /* PREFIX_VEX_0F5D */
4820   {
4821     { "vminps",         { XM, Vex, EXx }, 0 },
4822     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4823     { "vminpd",         { XM, Vex, EXx }, 0 },
4824     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4825   },
4826
4827   /* PREFIX_VEX_0F5E */
4828   {
4829     { "vdivps",         { XM, Vex, EXx }, 0 },
4830     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4831     { "vdivpd",         { XM, Vex, EXx }, 0 },
4832     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4833   },
4834
4835   /* PREFIX_VEX_0F5F */
4836   {
4837     { "vmaxps",         { XM, Vex, EXx }, 0 },
4838     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4839     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4840     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4841   },
4842
4843   /* PREFIX_VEX_0F60 */
4844   {
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4848   },
4849
4850   /* PREFIX_VEX_0F61 */
4851   {
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4855   },
4856
4857   /* PREFIX_VEX_0F62 */
4858   {
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4862   },
4863
4864   /* PREFIX_VEX_0F63 */
4865   {
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4869   },
4870
4871   /* PREFIX_VEX_0F64 */
4872   {
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4876   },
4877
4878   /* PREFIX_VEX_0F65 */
4879   {
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4883   },
4884
4885   /* PREFIX_VEX_0F66 */
4886   {
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4890   },
4891
4892   /* PREFIX_VEX_0F67 */
4893   {
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4897   },
4898
4899   /* PREFIX_VEX_0F68 */
4900   {
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4904   },
4905
4906   /* PREFIX_VEX_0F69 */
4907   {
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4911   },
4912
4913   /* PREFIX_VEX_0F6A */
4914   {
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4918   },
4919
4920   /* PREFIX_VEX_0F6B */
4921   {
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4925   },
4926
4927   /* PREFIX_VEX_0F6C */
4928   {
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4932   },
4933
4934   /* PREFIX_VEX_0F6D */
4935   {
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4939   },
4940
4941   /* PREFIX_VEX_0F6E */
4942   {
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4946   },
4947
4948   /* PREFIX_VEX_0F6F */
4949   {
4950     { Bad_Opcode },
4951     { "vmovdqu",        { XM, EXx }, 0 },
4952     { "vmovdqa",        { XM, EXx }, 0 },
4953   },
4954
4955   /* PREFIX_VEX_0F70 */
4956   {
4957     { Bad_Opcode },
4958     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4959     { "vpshufd",        { XM, EXx, Ib }, 0 },
4960     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4961   },
4962
4963   /* PREFIX_VEX_0F71_REG_2 */
4964   {
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4968   },
4969
4970   /* PREFIX_VEX_0F71_REG_4 */
4971   {
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { "vpsraw",         { Vex, XS, Ib }, 0 },
4975   },
4976
4977   /* PREFIX_VEX_0F71_REG_6 */
4978   {
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { "vpsllw",         { Vex, XS, Ib }, 0 },
4982   },
4983
4984   /* PREFIX_VEX_0F72_REG_2 */
4985   {
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { "vpsrld",         { Vex, XS, Ib }, 0 },
4989   },
4990
4991   /* PREFIX_VEX_0F72_REG_4 */
4992   {
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { "vpsrad",         { Vex, XS, Ib }, 0 },
4996   },
4997
4998   /* PREFIX_VEX_0F72_REG_6 */
4999   {
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { "vpslld",         { Vex, XS, Ib }, 0 },
5003   },
5004
5005   /* PREFIX_VEX_0F73_REG_2 */
5006   {
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5010   },
5011
5012   /* PREFIX_VEX_0F73_REG_3 */
5013   {
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5017   },
5018
5019   /* PREFIX_VEX_0F73_REG_6 */
5020   {
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { "vpsllq",         { Vex, XS, Ib }, 0 },
5024   },
5025
5026   /* PREFIX_VEX_0F73_REG_7 */
5027   {
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { "vpslldq",        { Vex, XS, Ib }, 0 },
5031   },
5032
5033   /* PREFIX_VEX_0F74 */
5034   {
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5038   },
5039
5040   /* PREFIX_VEX_0F75 */
5041   {
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5045   },
5046
5047   /* PREFIX_VEX_0F76 */
5048   {
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5052   },
5053
5054   /* PREFIX_VEX_0F77 */
5055   {
5056     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5057   },
5058
5059   /* PREFIX_VEX_0F7C */
5060   {
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5064     { "vhaddps",        { XM, Vex, EXx }, 0 },
5065   },
5066
5067   /* PREFIX_VEX_0F7D */
5068   {
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5072     { "vhsubps",        { XM, Vex, EXx }, 0 },
5073   },
5074
5075   /* PREFIX_VEX_0F7E */
5076   {
5077     { Bad_Opcode },
5078     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5079     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5080   },
5081
5082   /* PREFIX_VEX_0F7F */
5083   {
5084     { Bad_Opcode },
5085     { "vmovdqu",        { EXxS, XM }, 0 },
5086     { "vmovdqa",        { EXxS, XM }, 0 },
5087   },
5088
5089   /* PREFIX_VEX_0F90 */
5090   {
5091     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5092     { Bad_Opcode },
5093     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5094   },
5095
5096   /* PREFIX_VEX_0F91 */
5097   {
5098     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5099     { Bad_Opcode },
5100     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5101   },
5102
5103   /* PREFIX_VEX_0F92 */
5104   {
5105     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5106     { Bad_Opcode },
5107     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5108     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5109   },
5110
5111   /* PREFIX_VEX_0F93 */
5112   {
5113     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5114     { Bad_Opcode },
5115     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5116     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5117   },
5118
5119   /* PREFIX_VEX_0F98 */
5120   {
5121     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5122     { Bad_Opcode },
5123     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5124   },
5125
5126   /* PREFIX_VEX_0F99 */
5127   {
5128     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5129     { Bad_Opcode },
5130     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5131   },
5132
5133   /* PREFIX_VEX_0FC2 */
5134   {
5135     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5136     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5137     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5138     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5139   },
5140
5141   /* PREFIX_VEX_0FC4 */
5142   {
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5146   },
5147
5148   /* PREFIX_VEX_0FC5 */
5149   {
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5153   },
5154
5155   /* PREFIX_VEX_0FD0 */
5156   {
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5160     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5161   },
5162
5163   /* PREFIX_VEX_0FD1 */
5164   {
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5168   },
5169
5170   /* PREFIX_VEX_0FD2 */
5171   {
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5175   },
5176
5177   /* PREFIX_VEX_0FD3 */
5178   {
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5182   },
5183
5184   /* PREFIX_VEX_0FD4 */
5185   {
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { "vpaddq",         { XM, Vex, EXx }, 0 },
5189   },
5190
5191   /* PREFIX_VEX_0FD5 */
5192   {
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { "vpmullw",        { XM, Vex, EXx }, 0 },
5196   },
5197
5198   /* PREFIX_VEX_0FD6 */
5199   {
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5203   },
5204
5205   /* PREFIX_VEX_0FD7 */
5206   {
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5210   },
5211
5212   /* PREFIX_VEX_0FD8 */
5213   {
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5217   },
5218
5219   /* PREFIX_VEX_0FD9 */
5220   {
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5224   },
5225
5226   /* PREFIX_VEX_0FDA */
5227   {
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { "vpminub",        { XM, Vex, EXx }, 0 },
5231   },
5232
5233   /* PREFIX_VEX_0FDB */
5234   {
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { "vpand",          { XM, Vex, EXx }, 0 },
5238   },
5239
5240   /* PREFIX_VEX_0FDC */
5241   {
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5245   },
5246
5247   /* PREFIX_VEX_0FDD */
5248   {
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5252   },
5253
5254   /* PREFIX_VEX_0FDE */
5255   {
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5259   },
5260
5261   /* PREFIX_VEX_0FDF */
5262   {
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { "vpandn",         { XM, Vex, EXx }, 0 },
5266   },
5267
5268   /* PREFIX_VEX_0FE0 */
5269   {
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { "vpavgb",         { XM, Vex, EXx }, 0 },
5273   },
5274
5275   /* PREFIX_VEX_0FE1 */
5276   {
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5280   },
5281
5282   /* PREFIX_VEX_0FE2 */
5283   {
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5287   },
5288
5289   /* PREFIX_VEX_0FE3 */
5290   {
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { "vpavgw",         { XM, Vex, EXx }, 0 },
5294   },
5295
5296   /* PREFIX_VEX_0FE4 */
5297   {
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5301   },
5302
5303   /* PREFIX_VEX_0FE5 */
5304   {
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5308   },
5309
5310   /* PREFIX_VEX_0FE6 */
5311   {
5312     { Bad_Opcode },
5313     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5314     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5315     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5316   },
5317
5318   /* PREFIX_VEX_0FE7 */
5319   {
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5323   },
5324
5325   /* PREFIX_VEX_0FE8 */
5326   {
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5330   },
5331
5332   /* PREFIX_VEX_0FE9 */
5333   {
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5337   },
5338
5339   /* PREFIX_VEX_0FEA */
5340   {
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { "vpminsw",        { XM, Vex, EXx }, 0 },
5344   },
5345
5346   /* PREFIX_VEX_0FEB */
5347   {
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { "vpor",           { XM, Vex, EXx }, 0 },
5351   },
5352
5353   /* PREFIX_VEX_0FEC */
5354   {
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5358   },
5359
5360   /* PREFIX_VEX_0FED */
5361   {
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5365   },
5366
5367   /* PREFIX_VEX_0FEE */
5368   {
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5372   },
5373
5374   /* PREFIX_VEX_0FEF */
5375   {
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { "vpxor",          { XM, Vex, EXx }, 0 },
5379   },
5380
5381   /* PREFIX_VEX_0FF0 */
5382   {
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5387   },
5388
5389   /* PREFIX_VEX_0FF1 */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5394   },
5395
5396   /* PREFIX_VEX_0FF2 */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5401   },
5402
5403   /* PREFIX_VEX_0FF3 */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5408   },
5409
5410   /* PREFIX_VEX_0FF4 */
5411   {
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5415   },
5416
5417   /* PREFIX_VEX_0FF5 */
5418   {
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5422   },
5423
5424   /* PREFIX_VEX_0FF6 */
5425   {
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5429   },
5430
5431   /* PREFIX_VEX_0FF7 */
5432   {
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5436   },
5437
5438   /* PREFIX_VEX_0FF8 */
5439   {
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { "vpsubb",         { XM, Vex, EXx }, 0 },
5443   },
5444
5445   /* PREFIX_VEX_0FF9 */
5446   {
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { "vpsubw",         { XM, Vex, EXx }, 0 },
5450   },
5451
5452   /* PREFIX_VEX_0FFA */
5453   {
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { "vpsubd",         { XM, Vex, EXx }, 0 },
5457   },
5458
5459   /* PREFIX_VEX_0FFB */
5460   {
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { "vpsubq",         { XM, Vex, EXx }, 0 },
5464   },
5465
5466   /* PREFIX_VEX_0FFC */
5467   {
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { "vpaddb",         { XM, Vex, EXx }, 0 },
5471   },
5472
5473   /* PREFIX_VEX_0FFD */
5474   {
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { "vpaddw",         { XM, Vex, EXx }, 0 },
5478   },
5479
5480   /* PREFIX_VEX_0FFE */
5481   {
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { "vpaddd",         { XM, Vex, EXx }, 0 },
5485   },
5486
5487   /* PREFIX_VEX_0F3800 */
5488   {
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { "vpshufb",        { XM, Vex, EXx }, 0 },
5492   },
5493
5494   /* PREFIX_VEX_0F3801 */
5495   {
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { "vphaddw",        { XM, Vex, EXx }, 0 },
5499   },
5500
5501   /* PREFIX_VEX_0F3802 */
5502   {
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { "vphaddd",        { XM, Vex, EXx }, 0 },
5506   },
5507
5508   /* PREFIX_VEX_0F3803 */
5509   {
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5513   },
5514
5515   /* PREFIX_VEX_0F3804 */
5516   {
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5520   },
5521
5522   /* PREFIX_VEX_0F3805 */
5523   {
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { "vphsubw",        { XM, Vex, EXx }, 0 },
5527   },
5528
5529   /* PREFIX_VEX_0F3806 */
5530   {
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { "vphsubd",        { XM, Vex, EXx }, 0 },
5534   },
5535
5536   /* PREFIX_VEX_0F3807 */
5537   {
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5541   },
5542
5543   /* PREFIX_VEX_0F3808 */
5544   {
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { "vpsignb",        { XM, Vex, EXx }, 0 },
5548   },
5549
5550   /* PREFIX_VEX_0F3809 */
5551   {
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { "vpsignw",        { XM, Vex, EXx }, 0 },
5555   },
5556
5557   /* PREFIX_VEX_0F380A */
5558   {
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { "vpsignd",        { XM, Vex, EXx }, 0 },
5562   },
5563
5564   /* PREFIX_VEX_0F380B */
5565   {
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5569   },
5570
5571   /* PREFIX_VEX_0F380C */
5572   {
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5576   },
5577
5578   /* PREFIX_VEX_0F380D */
5579   {
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5583   },
5584
5585   /* PREFIX_VEX_0F380E */
5586   {
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5590   },
5591
5592   /* PREFIX_VEX_0F380F */
5593   {
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5597   },
5598
5599   /* PREFIX_VEX_0F3813 */
5600   {
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5604   },
5605
5606   /* PREFIX_VEX_0F3816 */
5607   {
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5611   },
5612
5613   /* PREFIX_VEX_0F3817 */
5614   {
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { "vptest",         { XM, EXx }, 0 },
5618   },
5619
5620   /* PREFIX_VEX_0F3818 */
5621   {
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5625   },
5626
5627   /* PREFIX_VEX_0F3819 */
5628   {
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5632   },
5633
5634   /* PREFIX_VEX_0F381A */
5635   {
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5639   },
5640
5641   /* PREFIX_VEX_0F381C */
5642   {
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { "vpabsb",         { XM, EXx }, 0 },
5646   },
5647
5648   /* PREFIX_VEX_0F381D */
5649   {
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { "vpabsw",         { XM, EXx }, 0 },
5653   },
5654
5655   /* PREFIX_VEX_0F381E */
5656   {
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { "vpabsd",         { XM, EXx }, 0 },
5660   },
5661
5662   /* PREFIX_VEX_0F3820 */
5663   {
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5667   },
5668
5669   /* PREFIX_VEX_0F3821 */
5670   {
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5674   },
5675
5676   /* PREFIX_VEX_0F3822 */
5677   {
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5681   },
5682
5683   /* PREFIX_VEX_0F3823 */
5684   {
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5688   },
5689
5690   /* PREFIX_VEX_0F3824 */
5691   {
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5695   },
5696
5697   /* PREFIX_VEX_0F3825 */
5698   {
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5702   },
5703
5704   /* PREFIX_VEX_0F3828 */
5705   {
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5709   },
5710
5711   /* PREFIX_VEX_0F3829 */
5712   {
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5716   },
5717
5718   /* PREFIX_VEX_0F382A */
5719   {
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5723   },
5724
5725   /* PREFIX_VEX_0F382B */
5726   {
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5730   },
5731
5732   /* PREFIX_VEX_0F382C */
5733   {
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5737   },
5738
5739   /* PREFIX_VEX_0F382D */
5740   {
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5744   },
5745
5746   /* PREFIX_VEX_0F382E */
5747   {
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5751   },
5752
5753   /* PREFIX_VEX_0F382F */
5754   {
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5758   },
5759
5760   /* PREFIX_VEX_0F3830 */
5761   {
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5765   },
5766
5767   /* PREFIX_VEX_0F3831 */
5768   {
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5772   },
5773
5774   /* PREFIX_VEX_0F3832 */
5775   {
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5779   },
5780
5781   /* PREFIX_VEX_0F3833 */
5782   {
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5786   },
5787
5788   /* PREFIX_VEX_0F3834 */
5789   {
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5793   },
5794
5795   /* PREFIX_VEX_0F3835 */
5796   {
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5800   },
5801
5802   /* PREFIX_VEX_0F3836 */
5803   {
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5807   },
5808
5809   /* PREFIX_VEX_0F3837 */
5810   {
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5814   },
5815
5816   /* PREFIX_VEX_0F3838 */
5817   {
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { "vpminsb",        { XM, Vex, EXx }, 0 },
5821   },
5822
5823   /* PREFIX_VEX_0F3839 */
5824   {
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { "vpminsd",        { XM, Vex, EXx }, 0 },
5828   },
5829
5830   /* PREFIX_VEX_0F383A */
5831   {
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { "vpminuw",        { XM, Vex, EXx }, 0 },
5835   },
5836
5837   /* PREFIX_VEX_0F383B */
5838   {
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { "vpminud",        { XM, Vex, EXx }, 0 },
5842   },
5843
5844   /* PREFIX_VEX_0F383C */
5845   {
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5849   },
5850
5851   /* PREFIX_VEX_0F383D */
5852   {
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5856   },
5857
5858   /* PREFIX_VEX_0F383E */
5859   {
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5863   },
5864
5865   /* PREFIX_VEX_0F383F */
5866   {
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5870   },
5871
5872   /* PREFIX_VEX_0F3840 */
5873   {
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { "vpmulld",        { XM, Vex, EXx }, 0 },
5877   },
5878
5879   /* PREFIX_VEX_0F3841 */
5880   {
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5884   },
5885
5886   /* PREFIX_VEX_0F3845 */
5887   {
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5891   },
5892
5893   /* PREFIX_VEX_0F3846 */
5894   {
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5898   },
5899
5900   /* PREFIX_VEX_0F3847 */
5901   {
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5905   },
5906
5907   /* PREFIX_VEX_0F3858 */
5908   {
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5912   },
5913
5914   /* PREFIX_VEX_0F3859 */
5915   {
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5919   },
5920
5921   /* PREFIX_VEX_0F385A */
5922   {
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5926   },
5927
5928   /* PREFIX_VEX_0F3878 */
5929   {
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5933   },
5934
5935   /* PREFIX_VEX_0F3879 */
5936   {
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5940   },
5941
5942   /* PREFIX_VEX_0F388C */
5943   {
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5947   },
5948
5949   /* PREFIX_VEX_0F388E */
5950   {
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5954   },
5955
5956   /* PREFIX_VEX_0F3890 */
5957   {
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5961   },
5962
5963   /* PREFIX_VEX_0F3891 */
5964   {
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5968   },
5969
5970   /* PREFIX_VEX_0F3892 */
5971   {
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5975   },
5976
5977   /* PREFIX_VEX_0F3893 */
5978   {
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5982   },
5983
5984   /* PREFIX_VEX_0F3896 */
5985   {
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
5989   },
5990
5991   /* PREFIX_VEX_0F3897 */
5992   {
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
5996   },
5997
5998   /* PREFIX_VEX_0F3898 */
5999   {
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6003   },
6004
6005   /* PREFIX_VEX_0F3899 */
6006   {
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6010   },
6011
6012   /* PREFIX_VEX_0F389A */
6013   {
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6017   },
6018
6019   /* PREFIX_VEX_0F389B */
6020   {
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6024   },
6025
6026   /* PREFIX_VEX_0F389C */
6027   {
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6031   },
6032
6033   /* PREFIX_VEX_0F389D */
6034   {
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6038   },
6039
6040   /* PREFIX_VEX_0F389E */
6041   {
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6045   },
6046
6047   /* PREFIX_VEX_0F389F */
6048   {
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6052   },
6053
6054   /* PREFIX_VEX_0F38A6 */
6055   {
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6059     { Bad_Opcode },
6060   },
6061
6062   /* PREFIX_VEX_0F38A7 */
6063   {
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6067   },
6068
6069   /* PREFIX_VEX_0F38A8 */
6070   {
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6074   },
6075
6076   /* PREFIX_VEX_0F38A9 */
6077   {
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6081   },
6082
6083   /* PREFIX_VEX_0F38AA */
6084   {
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6088   },
6089
6090   /* PREFIX_VEX_0F38AB */
6091   {
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6095   },
6096
6097   /* PREFIX_VEX_0F38AC */
6098   {
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6102   },
6103
6104   /* PREFIX_VEX_0F38AD */
6105   {
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6109   },
6110
6111   /* PREFIX_VEX_0F38AE */
6112   {
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6116   },
6117
6118   /* PREFIX_VEX_0F38AF */
6119   {
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6123   },
6124
6125   /* PREFIX_VEX_0F38B6 */
6126   {
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6130   },
6131
6132   /* PREFIX_VEX_0F38B7 */
6133   {
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6137   },
6138
6139   /* PREFIX_VEX_0F38B8 */
6140   {
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6144   },
6145
6146   /* PREFIX_VEX_0F38B9 */
6147   {
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6151   },
6152
6153   /* PREFIX_VEX_0F38BA */
6154   {
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6158   },
6159
6160   /* PREFIX_VEX_0F38BB */
6161   {
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6165   },
6166
6167   /* PREFIX_VEX_0F38BC */
6168   {
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6172   },
6173
6174   /* PREFIX_VEX_0F38BD */
6175   {
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6179   },
6180
6181   /* PREFIX_VEX_0F38BE */
6182   {
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6186   },
6187
6188   /* PREFIX_VEX_0F38BF */
6189   {
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6193   },
6194
6195   /* PREFIX_VEX_0F38CF */
6196   {
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6200   },
6201
6202   /* PREFIX_VEX_0F38DB */
6203   {
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6207   },
6208
6209   /* PREFIX_VEX_0F38DC */
6210   {
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { "vaesenc",        { XM, Vex, EXx }, 0 },
6214   },
6215
6216   /* PREFIX_VEX_0F38DD */
6217   {
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6221   },
6222
6223   /* PREFIX_VEX_0F38DE */
6224   {
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { "vaesdec",        { XM, Vex, EXx }, 0 },
6228   },
6229
6230   /* PREFIX_VEX_0F38DF */
6231   {
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6235   },
6236
6237   /* PREFIX_VEX_0F38F2 */
6238   {
6239     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6240   },
6241
6242   /* PREFIX_VEX_0F38F3_REG_1 */
6243   {
6244     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6245   },
6246
6247   /* PREFIX_VEX_0F38F3_REG_2 */
6248   {
6249     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6250   },
6251
6252   /* PREFIX_VEX_0F38F3_REG_3 */
6253   {
6254     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6255   },
6256
6257   /* PREFIX_VEX_0F38F5 */
6258   {
6259     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6260     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6261     { Bad_Opcode },
6262     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6263   },
6264
6265   /* PREFIX_VEX_0F38F6 */
6266   {
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6271   },
6272
6273   /* PREFIX_VEX_0F38F7 */
6274   {
6275     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6276     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6277     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6278     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6279   },
6280
6281   /* PREFIX_VEX_0F3A00 */
6282   {
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6286   },
6287
6288   /* PREFIX_VEX_0F3A01 */
6289   {
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6293   },
6294
6295   /* PREFIX_VEX_0F3A02 */
6296   {
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6300   },
6301
6302   /* PREFIX_VEX_0F3A04 */
6303   {
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6307   },
6308
6309   /* PREFIX_VEX_0F3A05 */
6310   {
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6314   },
6315
6316   /* PREFIX_VEX_0F3A06 */
6317   {
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6321   },
6322
6323   /* PREFIX_VEX_0F3A08 */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { "vroundps",       { XM, EXx, Ib }, 0 },
6328   },
6329
6330   /* PREFIX_VEX_0F3A09 */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { "vroundpd",       { XM, EXx, Ib }, 0 },
6335   },
6336
6337   /* PREFIX_VEX_0F3A0A */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6342   },
6343
6344   /* PREFIX_VEX_0F3A0B */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6349   },
6350
6351   /* PREFIX_VEX_0F3A0C */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6356   },
6357
6358   /* PREFIX_VEX_0F3A0D */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6363   },
6364
6365   /* PREFIX_VEX_0F3A0E */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6370   },
6371
6372   /* PREFIX_VEX_0F3A0F */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6377   },
6378
6379   /* PREFIX_VEX_0F3A14 */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6384   },
6385
6386   /* PREFIX_VEX_0F3A15 */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6391   },
6392
6393   /* PREFIX_VEX_0F3A16 */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6398   },
6399
6400   /* PREFIX_VEX_0F3A17 */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6405   },
6406
6407   /* PREFIX_VEX_0F3A18 */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6412   },
6413
6414   /* PREFIX_VEX_0F3A19 */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6419   },
6420
6421   /* PREFIX_VEX_0F3A1D */
6422   {
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6426   },
6427
6428   /* PREFIX_VEX_0F3A20 */
6429   {
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6433   },
6434
6435   /* PREFIX_VEX_0F3A21 */
6436   {
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6440   },
6441
6442   /* PREFIX_VEX_0F3A22 */
6443   {
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6447   },
6448
6449   /* PREFIX_VEX_0F3A30 */
6450   {
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6454   },
6455
6456   /* PREFIX_VEX_0F3A31 */
6457   {
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6461   },
6462
6463   /* PREFIX_VEX_0F3A32 */
6464   {
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6468   },
6469
6470   /* PREFIX_VEX_0F3A33 */
6471   {
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6475   },
6476
6477   /* PREFIX_VEX_0F3A38 */
6478   {
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6482   },
6483
6484   /* PREFIX_VEX_0F3A39 */
6485   {
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6489   },
6490
6491   /* PREFIX_VEX_0F3A40 */
6492   {
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6496   },
6497
6498   /* PREFIX_VEX_0F3A41 */
6499   {
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6503   },
6504
6505   /* PREFIX_VEX_0F3A42 */
6506   {
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6510   },
6511
6512   /* PREFIX_VEX_0F3A44 */
6513   {
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6517   },
6518
6519   /* PREFIX_VEX_0F3A46 */
6520   {
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6524   },
6525
6526   /* PREFIX_VEX_0F3A48 */
6527   {
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6531   },
6532
6533   /* PREFIX_VEX_0F3A49 */
6534   {
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6538   },
6539
6540   /* PREFIX_VEX_0F3A4A */
6541   {
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6545   },
6546
6547   /* PREFIX_VEX_0F3A4B */
6548   {
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6552   },
6553
6554   /* PREFIX_VEX_0F3A4C */
6555   {
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6559   },
6560
6561   /* PREFIX_VEX_0F3A5C */
6562   {
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6566   },
6567
6568   /* PREFIX_VEX_0F3A5D */
6569   {
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6573   },
6574
6575   /* PREFIX_VEX_0F3A5E */
6576   {
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6580   },
6581
6582   /* PREFIX_VEX_0F3A5F */
6583   {
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6587   },
6588
6589   /* PREFIX_VEX_0F3A60 */
6590   {
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6594     { Bad_Opcode },
6595   },
6596
6597   /* PREFIX_VEX_0F3A61 */
6598   {
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6602   },
6603
6604   /* PREFIX_VEX_0F3A62 */
6605   {
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6609   },
6610
6611   /* PREFIX_VEX_0F3A63 */
6612   {
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6616   },
6617
6618   /* PREFIX_VEX_0F3A68 */
6619   {
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6623   },
6624
6625   /* PREFIX_VEX_0F3A69 */
6626   {
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6630   },
6631
6632   /* PREFIX_VEX_0F3A6A */
6633   {
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6637   },
6638
6639   /* PREFIX_VEX_0F3A6B */
6640   {
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6644   },
6645
6646   /* PREFIX_VEX_0F3A6C */
6647   {
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6651   },
6652
6653   /* PREFIX_VEX_0F3A6D */
6654   {
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6658   },
6659
6660   /* PREFIX_VEX_0F3A6E */
6661   {
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6665   },
6666
6667   /* PREFIX_VEX_0F3A6F */
6668   {
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6672   },
6673
6674   /* PREFIX_VEX_0F3A78 */
6675   {
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6679   },
6680
6681   /* PREFIX_VEX_0F3A79 */
6682   {
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6686   },
6687
6688   /* PREFIX_VEX_0F3A7A */
6689   {
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6693   },
6694
6695   /* PREFIX_VEX_0F3A7B */
6696   {
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6700   },
6701
6702   /* PREFIX_VEX_0F3A7C */
6703   {
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6707     { Bad_Opcode },
6708   },
6709
6710   /* PREFIX_VEX_0F3A7D */
6711   {
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6715   },
6716
6717   /* PREFIX_VEX_0F3A7E */
6718   {
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6722   },
6723
6724   /* PREFIX_VEX_0F3A7F */
6725   {
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6729   },
6730
6731   /* PREFIX_VEX_0F3ACE */
6732   {
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6736   },
6737
6738   /* PREFIX_VEX_0F3ACF */
6739   {
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6743   },
6744
6745   /* PREFIX_VEX_0F3ADF */
6746   {
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6750   },
6751
6752   /* PREFIX_VEX_0F3AF0 */
6753   {
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6758   },
6759
6760 #define NEED_PREFIX_TABLE
6761 #include "i386-dis-evex.h"
6762 #undef NEED_PREFIX_TABLE
6763 };
6764
6765 static const struct dis386 x86_64_table[][2] = {
6766   /* X86_64_06 */
6767   {
6768     { "pushP", { es }, 0 },
6769   },
6770
6771   /* X86_64_07 */
6772   {
6773     { "popP", { es }, 0 },
6774   },
6775
6776   /* X86_64_0D */
6777   {
6778     { "pushP", { cs }, 0 },
6779   },
6780
6781   /* X86_64_16 */
6782   {
6783     { "pushP", { ss }, 0 },
6784   },
6785
6786   /* X86_64_17 */
6787   {
6788     { "popP", { ss }, 0 },
6789   },
6790
6791   /* X86_64_1E */
6792   {
6793     { "pushP", { ds }, 0 },
6794   },
6795
6796   /* X86_64_1F */
6797   {
6798     { "popP", { ds }, 0 },
6799   },
6800
6801   /* X86_64_27 */
6802   {
6803     { "daa", { XX }, 0 },
6804   },
6805
6806   /* X86_64_2F */
6807   {
6808     { "das", { XX }, 0 },
6809   },
6810
6811   /* X86_64_37 */
6812   {
6813     { "aaa", { XX }, 0 },
6814   },
6815
6816   /* X86_64_3F */
6817   {
6818     { "aas", { XX }, 0 },
6819   },
6820
6821   /* X86_64_60 */
6822   {
6823     { "pushaP", { XX }, 0 },
6824   },
6825
6826   /* X86_64_61 */
6827   {
6828     { "popaP", { XX }, 0 },
6829   },
6830
6831   /* X86_64_62 */
6832   {
6833     { MOD_TABLE (MOD_62_32BIT) },
6834     { EVEX_TABLE (EVEX_0F) },
6835   },
6836
6837   /* X86_64_63 */
6838   {
6839     { "arpl", { Ew, Gw }, 0 },
6840     { "movs{lq|xd}", { Gv, Ed }, 0 },
6841   },
6842
6843   /* X86_64_6D */
6844   {
6845     { "ins{R|}", { Yzr, indirDX }, 0 },
6846     { "ins{G|}", { Yzr, indirDX }, 0 },
6847   },
6848
6849   /* X86_64_6F */
6850   {
6851     { "outs{R|}", { indirDXr, Xz }, 0 },
6852     { "outs{G|}", { indirDXr, Xz }, 0 },
6853   },
6854
6855   /* X86_64_82 */
6856   {
6857     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6858     { REG_TABLE (REG_80) },
6859   },
6860
6861   /* X86_64_9A */
6862   {
6863     { "Jcall{T|}", { Ap }, 0 },
6864   },
6865
6866   /* X86_64_C4 */
6867   {
6868     { MOD_TABLE (MOD_C4_32BIT) },
6869     { VEX_C4_TABLE (VEX_0F) },
6870   },
6871
6872   /* X86_64_C5 */
6873   {
6874     { MOD_TABLE (MOD_C5_32BIT) },
6875     { VEX_C5_TABLE (VEX_0F) },
6876   },
6877
6878   /* X86_64_CE */
6879   {
6880     { "into", { XX }, 0 },
6881   },
6882
6883   /* X86_64_D4 */
6884   {
6885     { "aam", { Ib }, 0 },
6886   },
6887
6888   /* X86_64_D5 */
6889   {
6890     { "aad", { Ib }, 0 },
6891   },
6892
6893   /* X86_64_E8 */
6894   {
6895     { "callP",          { Jv, BND }, 0 },
6896     { "call@",          { Jv, BND }, 0 }
6897   },
6898
6899   /* X86_64_E9 */
6900   {
6901     { "jmpP",           { Jv, BND }, 0 },
6902     { "jmp@",           { Jv, BND }, 0 }
6903   },
6904
6905   /* X86_64_EA */
6906   {
6907     { "Jjmp{T|}", { Ap }, 0 },
6908   },
6909
6910   /* X86_64_0F01_REG_0 */
6911   {
6912     { "sgdt{Q|IQ}", { M }, 0 },
6913     { "sgdt", { M }, 0 },
6914   },
6915
6916   /* X86_64_0F01_REG_1 */
6917   {
6918     { "sidt{Q|IQ}", { M }, 0 },
6919     { "sidt", { M }, 0 },
6920   },
6921
6922   /* X86_64_0F01_REG_2 */
6923   {
6924     { "lgdt{Q|Q}", { M }, 0 },
6925     { "lgdt", { M }, 0 },
6926   },
6927
6928   /* X86_64_0F01_REG_3 */
6929   {
6930     { "lidt{Q|Q}", { M }, 0 },
6931     { "lidt", { M }, 0 },
6932   },
6933 };
6934
6935 static const struct dis386 three_byte_table[][256] = {
6936
6937   /* THREE_BYTE_0F38 */
6938   {
6939     /* 00 */
6940     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6941     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6942     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6943     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6944     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6945     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6946     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6947     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6948     /* 08 */
6949     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6950     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6951     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6952     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     /* 10 */
6958     { PREFIX_TABLE (PREFIX_0F3810) },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { PREFIX_TABLE (PREFIX_0F3814) },
6963     { PREFIX_TABLE (PREFIX_0F3815) },
6964     { Bad_Opcode },
6965     { PREFIX_TABLE (PREFIX_0F3817) },
6966     /* 18 */
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6972     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6973     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6974     { Bad_Opcode },
6975     /* 20 */
6976     { PREFIX_TABLE (PREFIX_0F3820) },
6977     { PREFIX_TABLE (PREFIX_0F3821) },
6978     { PREFIX_TABLE (PREFIX_0F3822) },
6979     { PREFIX_TABLE (PREFIX_0F3823) },
6980     { PREFIX_TABLE (PREFIX_0F3824) },
6981     { PREFIX_TABLE (PREFIX_0F3825) },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     /* 28 */
6985     { PREFIX_TABLE (PREFIX_0F3828) },
6986     { PREFIX_TABLE (PREFIX_0F3829) },
6987     { PREFIX_TABLE (PREFIX_0F382A) },
6988     { PREFIX_TABLE (PREFIX_0F382B) },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     /* 30 */
6994     { PREFIX_TABLE (PREFIX_0F3830) },
6995     { PREFIX_TABLE (PREFIX_0F3831) },
6996     { PREFIX_TABLE (PREFIX_0F3832) },
6997     { PREFIX_TABLE (PREFIX_0F3833) },
6998     { PREFIX_TABLE (PREFIX_0F3834) },
6999     { PREFIX_TABLE (PREFIX_0F3835) },
7000     { Bad_Opcode },
7001     { PREFIX_TABLE (PREFIX_0F3837) },
7002     /* 38 */
7003     { PREFIX_TABLE (PREFIX_0F3838) },
7004     { PREFIX_TABLE (PREFIX_0F3839) },
7005     { PREFIX_TABLE (PREFIX_0F383A) },
7006     { PREFIX_TABLE (PREFIX_0F383B) },
7007     { PREFIX_TABLE (PREFIX_0F383C) },
7008     { PREFIX_TABLE (PREFIX_0F383D) },
7009     { PREFIX_TABLE (PREFIX_0F383E) },
7010     { PREFIX_TABLE (PREFIX_0F383F) },
7011     /* 40 */
7012     { PREFIX_TABLE (PREFIX_0F3840) },
7013     { PREFIX_TABLE (PREFIX_0F3841) },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     /* 48 */
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     /* 50 */
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     /* 58 */
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     /* 60 */
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     /* 68 */
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     /* 70 */
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     /* 78 */
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     /* 80 */
7084     { PREFIX_TABLE (PREFIX_0F3880) },
7085     { PREFIX_TABLE (PREFIX_0F3881) },
7086     { PREFIX_TABLE (PREFIX_0F3882) },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     /* 88 */
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     /* 90 */
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     /* 98 */
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     /* a0 */
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     /* a8 */
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     /* b0 */
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     /* b8 */
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     /* c0 */
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     /* c8 */
7165     { PREFIX_TABLE (PREFIX_0F38C8) },
7166     { PREFIX_TABLE (PREFIX_0F38C9) },
7167     { PREFIX_TABLE (PREFIX_0F38CA) },
7168     { PREFIX_TABLE (PREFIX_0F38CB) },
7169     { PREFIX_TABLE (PREFIX_0F38CC) },
7170     { PREFIX_TABLE (PREFIX_0F38CD) },
7171     { Bad_Opcode },
7172     { PREFIX_TABLE (PREFIX_0F38CF) },
7173     /* d0 */
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     /* d8 */
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { PREFIX_TABLE (PREFIX_0F38DB) },
7187     { PREFIX_TABLE (PREFIX_0F38DC) },
7188     { PREFIX_TABLE (PREFIX_0F38DD) },
7189     { PREFIX_TABLE (PREFIX_0F38DE) },
7190     { PREFIX_TABLE (PREFIX_0F38DF) },
7191     /* e0 */
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     /* e8 */
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     /* f0 */
7210     { PREFIX_TABLE (PREFIX_0F38F0) },
7211     { PREFIX_TABLE (PREFIX_0F38F1) },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { PREFIX_TABLE (PREFIX_0F38F5) },
7216     { PREFIX_TABLE (PREFIX_0F38F6) },
7217     { Bad_Opcode },
7218     /* f8 */
7219     { PREFIX_TABLE (PREFIX_0F38F8) },
7220     { PREFIX_TABLE (PREFIX_0F38F9) },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227   },
7228   /* THREE_BYTE_0F3A */
7229   {
7230     /* 00 */
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     /* 08 */
7240     { PREFIX_TABLE (PREFIX_0F3A08) },
7241     { PREFIX_TABLE (PREFIX_0F3A09) },
7242     { PREFIX_TABLE (PREFIX_0F3A0A) },
7243     { PREFIX_TABLE (PREFIX_0F3A0B) },
7244     { PREFIX_TABLE (PREFIX_0F3A0C) },
7245     { PREFIX_TABLE (PREFIX_0F3A0D) },
7246     { PREFIX_TABLE (PREFIX_0F3A0E) },
7247     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7248     /* 10 */
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { PREFIX_TABLE (PREFIX_0F3A14) },
7254     { PREFIX_TABLE (PREFIX_0F3A15) },
7255     { PREFIX_TABLE (PREFIX_0F3A16) },
7256     { PREFIX_TABLE (PREFIX_0F3A17) },
7257     /* 18 */
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     /* 20 */
7267     { PREFIX_TABLE (PREFIX_0F3A20) },
7268     { PREFIX_TABLE (PREFIX_0F3A21) },
7269     { PREFIX_TABLE (PREFIX_0F3A22) },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     /* 28 */
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     /* 30 */
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     /* 38 */
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     /* 40 */
7303     { PREFIX_TABLE (PREFIX_0F3A40) },
7304     { PREFIX_TABLE (PREFIX_0F3A41) },
7305     { PREFIX_TABLE (PREFIX_0F3A42) },
7306     { Bad_Opcode },
7307     { PREFIX_TABLE (PREFIX_0F3A44) },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     /* 48 */
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     /* 50 */
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     /* 58 */
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     /* 60 */
7339     { PREFIX_TABLE (PREFIX_0F3A60) },
7340     { PREFIX_TABLE (PREFIX_0F3A61) },
7341     { PREFIX_TABLE (PREFIX_0F3A62) },
7342     { PREFIX_TABLE (PREFIX_0F3A63) },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     /* 68 */
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     /* 70 */
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     /* 78 */
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     /* 80 */
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     /* 88 */
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     /* 90 */
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     /* 98 */
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     /* a0 */
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     /* a8 */
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     /* b0 */
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     /* b8 */
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     /* c0 */
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     /* c8 */
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { PREFIX_TABLE (PREFIX_0F3ACC) },
7461     { Bad_Opcode },
7462     { PREFIX_TABLE (PREFIX_0F3ACE) },
7463     { PREFIX_TABLE (PREFIX_0F3ACF) },
7464     /* d0 */
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     /* d8 */
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { PREFIX_TABLE (PREFIX_0F3ADF) },
7482     /* e0 */
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     /* e8 */
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     /* f0 */
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     /* f8 */
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518   },
7519 };
7520
7521 static const struct dis386 xop_table[][256] = {
7522   /* XOP_08 */
7523   {
7524     /* 00 */
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     /* 08 */
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     /* 10 */
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     /* 18 */
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     /* 20 */
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     /* 28 */
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     /* 30 */
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     /* 38 */
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     /* 40 */
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     /* 48 */
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     /* 50 */
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     /* 58 */
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     /* 60 */
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     /* 68 */
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     /* 70 */
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     /* 78 */
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     /* 80 */
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7675     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7676     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7677     /* 88 */
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7685     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7686     /* 90 */
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7693     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7694     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7695     /* 98 */
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7703     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7704     /* a0 */
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7708     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7712     { Bad_Opcode },
7713     /* a8 */
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     /* b0 */
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7730     { Bad_Opcode },
7731     /* b8 */
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     /* c0 */
7741     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7742     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7743     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7744     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     /* c8 */
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7755     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7756     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7757     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7758     /* d0 */
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     /* d8 */
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     /* e0 */
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     /* e8 */
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7791     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7792     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7793     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7794     /* f0 */
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     /* f8 */
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812   },
7813   /* XOP_09 */
7814   {
7815     /* 00 */
7816     { Bad_Opcode },
7817     { REG_TABLE (REG_XOP_TBM_01) },
7818     { REG_TABLE (REG_XOP_TBM_02) },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     /* 08 */
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     /* 10 */
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { REG_TABLE (REG_XOP_LWPCB) },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     /* 18 */
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     /* 20 */
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     /* 28 */
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     /* 30 */
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     /* 38 */
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     /* 40 */
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     /* 48 */
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     /* 50 */
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     /* 58 */
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     /* 60 */
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     /* 68 */
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     /* 70 */
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     /* 78 */
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     /* 80 */
7960     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7961     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7962     { "vfrczss",        { XM, EXd }, 0 },
7963     { "vfrczsd",        { XM, EXq }, 0 },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     /* 88 */
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     /* 90 */
7978     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7979     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7980     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7981     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7982     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7983     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7984     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7985     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7986     /* 98 */
7987     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7988     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7989     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7990     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     /* a0 */
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     /* a8 */
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     /* b0 */
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     /* b8 */
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     /* c0 */
8032     { Bad_Opcode },
8033     { "vphaddbw",       { XM, EXxmm }, 0 },
8034     { "vphaddbd",       { XM, EXxmm }, 0 },
8035     { "vphaddbq",       { XM, EXxmm }, 0 },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { "vphaddwd",       { XM, EXxmm }, 0 },
8039     { "vphaddwq",       { XM, EXxmm }, 0 },
8040     /* c8 */
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { "vphadddq",       { XM, EXxmm }, 0 },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     /* d0 */
8050     { Bad_Opcode },
8051     { "vphaddubw",      { XM, EXxmm }, 0 },
8052     { "vphaddubd",      { XM, EXxmm }, 0 },
8053     { "vphaddubq",      { XM, EXxmm }, 0 },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { "vphadduwd",      { XM, EXxmm }, 0 },
8057     { "vphadduwq",      { XM, EXxmm }, 0 },
8058     /* d8 */
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { "vphaddudq",      { XM, EXxmm }, 0 },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     /* e0 */
8068     { Bad_Opcode },
8069     { "vphsubbw",       { XM, EXxmm }, 0 },
8070     { "vphsubwd",       { XM, EXxmm }, 0 },
8071     { "vphsubdq",       { XM, EXxmm }, 0 },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     /* e8 */
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     /* f0 */
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     /* f8 */
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103   },
8104   /* XOP_0A */
8105   {
8106     /* 00 */
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     /* 08 */
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     /* 10 */
8125     { "bextr",  { Gv, Ev, Iq }, 0 },
8126     { Bad_Opcode },
8127     { REG_TABLE (REG_XOP_LWP) },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     /* 18 */
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     /* 20 */
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     /* 28 */
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     /* 30 */
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     /* 38 */
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     /* 40 */
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     /* 48 */
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     /* 50 */
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     /* 58 */
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     /* 60 */
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     /* 68 */
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     /* 70 */
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     /* 78 */
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     /* 80 */
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     /* 88 */
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     /* 90 */
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     /* 98 */
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     /* a0 */
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     /* a8 */
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     /* b0 */
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     /* b8 */
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     /* c0 */
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     /* c8 */
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     /* d0 */
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     /* d8 */
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     /* e0 */
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     /* e8 */
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     /* f0 */
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     /* f8 */
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394   },
8395 };
8396
8397 static const struct dis386 vex_table[][256] = {
8398   /* VEX_0F */
8399   {
8400     /* 00 */
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     /* 08 */
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     /* 10 */
8419     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8420     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8421     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8422     { MOD_TABLE (MOD_VEX_0F13) },
8423     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8424     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8425     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8426     { MOD_TABLE (MOD_VEX_0F17) },
8427     /* 18 */
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     /* 20 */
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     /* 28 */
8446     { "vmovapX",        { XM, EXx }, 0 },
8447     { "vmovapX",        { EXxS, XM }, 0 },
8448     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8449     { MOD_TABLE (MOD_VEX_0F2B) },
8450     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8451     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8452     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8453     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8454     /* 30 */
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     /* 38 */
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     /* 40 */
8473     { Bad_Opcode },
8474     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8475     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8476     { Bad_Opcode },
8477     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8478     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8479     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8480     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8481     /* 48 */
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8485     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     /* 50 */
8491     { MOD_TABLE (MOD_VEX_0F50) },
8492     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8493     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8494     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8495     { "vandpX",         { XM, Vex, EXx }, 0 },
8496     { "vandnpX",        { XM, Vex, EXx }, 0 },
8497     { "vorpX",          { XM, Vex, EXx }, 0 },
8498     { "vxorpX",         { XM, Vex, EXx }, 0 },
8499     /* 58 */
8500     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8501     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8502     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8503     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8504     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8505     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8506     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8507     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8508     /* 60 */
8509     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8510     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8511     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8512     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8513     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8515     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8516     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8517     /* 68 */
8518     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8519     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8520     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8521     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8522     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8523     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8524     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8525     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8526     /* 70 */
8527     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8528     { REG_TABLE (REG_VEX_0F71) },
8529     { REG_TABLE (REG_VEX_0F72) },
8530     { REG_TABLE (REG_VEX_0F73) },
8531     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8532     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8533     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8535     /* 78 */
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8541     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8542     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8544     /* 80 */
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     /* 88 */
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     /* 90 */
8563     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8564     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8565     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8566     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     /* 98 */
8572     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8573     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     /* a0 */
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     /* a8 */
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { REG_TABLE (REG_VEX_0FAE) },
8597     { Bad_Opcode },
8598     /* b0 */
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     /* b8 */
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     /* c0 */
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8620     { Bad_Opcode },
8621     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8622     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8623     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8624     { Bad_Opcode },
8625     /* c8 */
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     /* d0 */
8635     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8636     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8637     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8638     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8639     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8640     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8641     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8642     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8643     /* d8 */
8644     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8645     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8646     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8647     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8648     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8649     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8650     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8651     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8652     /* e0 */
8653     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8654     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8655     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8656     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8657     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8658     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8659     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8660     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8661     /* e8 */
8662     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8663     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8664     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8665     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8666     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8667     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8668     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8669     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8670     /* f0 */
8671     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8672     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8679     /* f8 */
8680     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8687     { Bad_Opcode },
8688   },
8689   /* VEX_0F38 */
8690   {
8691     /* 00 */
8692     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8693     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8694     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8695     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8696     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8700     /* 08 */
8701     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8709     /* 10 */
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8717     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8718     /* 18 */
8719     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8720     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8721     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8722     { Bad_Opcode },
8723     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8724     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8726     { Bad_Opcode },
8727     /* 20 */
8728     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     /* 28 */
8737     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8745     /* 30 */
8746     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8754     /* 38 */
8755     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8763     /* 40 */
8764     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8772     /* 48 */
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     /* 50 */
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     /* 58 */
8791     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     /* 60 */
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     /* 68 */
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     /* 70 */
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     /* 78 */
8827     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8828     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     /* 80 */
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     /* 88 */
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8850     { Bad_Opcode },
8851     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8852     { Bad_Opcode },
8853     /* 90 */
8854     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8855     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8856     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8857     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8861     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8862     /* 98 */
8863     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8864     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8865     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8866     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8867     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8868     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8869     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8870     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8871     /* a0 */
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8879     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8880     /* a8 */
8881     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8882     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8883     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8889     /* b0 */
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8898     /* b8 */
8899     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8907     /* c0 */
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     /* c8 */
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8925     /* d0 */
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     /* d8 */
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8943     /* e0 */
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     /* e8 */
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     /* f0 */
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8965     { REG_TABLE (REG_VEX_0F38F3) },
8966     { Bad_Opcode },
8967     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8969     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8970     /* f8 */
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979   },
8980   /* VEX_0F3A */
8981   {
8982     /* 00 */
8983     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8985     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8986     { Bad_Opcode },
8987     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8988     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8990     { Bad_Opcode },
8991     /* 08 */
8992     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9000     /* 10 */
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9009     /* 18 */
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     /* 20 */
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     /* 28 */
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     /* 30 */
9037     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     /* 38 */
9046     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     /* 40 */
9055     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9058     { Bad_Opcode },
9059     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9060     { Bad_Opcode },
9061     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9062     { Bad_Opcode },
9063     /* 48 */
9064     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9065     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9068     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     /* 50 */
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     /* 58 */
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9087     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9090     /* 60 */
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     /* 68 */
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9103     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9104     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9105     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9106     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9107     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9108     /* 70 */
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     /* 78 */
9118     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9119     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9126     /* 80 */
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     /* 88 */
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     /* 90 */
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     /* 98 */
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     /* a0 */
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     /* a8 */
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     /* b0 */
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     /* b8 */
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     /* c0 */
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     /* c8 */
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9215     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9216     /* d0 */
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     /* d8 */
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9234     /* e0 */
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     /* e8 */
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     /* f0 */
9253     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     /* f8 */
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270   },
9271 };
9272
9273 #define NEED_OPCODE_TABLE
9274 #include "i386-dis-evex.h"
9275 #undef NEED_OPCODE_TABLE
9276 static const struct dis386 vex_len_table[][2] = {
9277   /* VEX_LEN_0F12_P_0_M_0 */
9278   {
9279     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9280   },
9281
9282   /* VEX_LEN_0F12_P_0_M_1 */
9283   {
9284     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9285   },
9286
9287   /* VEX_LEN_0F12_P_2 */
9288   {
9289     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9290   },
9291
9292   /* VEX_LEN_0F13_M_0 */
9293   {
9294     { "vmovlpX",        { EXq, XM }, 0 },
9295   },
9296
9297   /* VEX_LEN_0F16_P_0_M_0 */
9298   {
9299     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9300   },
9301
9302   /* VEX_LEN_0F16_P_0_M_1 */
9303   {
9304     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9305   },
9306
9307   /* VEX_LEN_0F16_P_2 */
9308   {
9309     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9310   },
9311
9312   /* VEX_LEN_0F17_M_0 */
9313   {
9314     { "vmovhpX",        { EXq, XM }, 0 },
9315   },
9316
9317   /* VEX_LEN_0F2A_P_1 */
9318   {
9319     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9320     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9321   },
9322
9323   /* VEX_LEN_0F2A_P_3 */
9324   {
9325     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9326     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9327   },
9328
9329   /* VEX_LEN_0F2C_P_1 */
9330   {
9331     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9332     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9333   },
9334
9335   /* VEX_LEN_0F2C_P_3 */
9336   {
9337     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9338     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9339   },
9340
9341   /* VEX_LEN_0F2D_P_1 */
9342   {
9343     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9344     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9345   },
9346
9347   /* VEX_LEN_0F2D_P_3 */
9348   {
9349     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9350     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9351   },
9352
9353   /* VEX_LEN_0F41_P_0 */
9354   {
9355     { Bad_Opcode },
9356     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9357   },
9358   /* VEX_LEN_0F41_P_2 */
9359   {
9360     { Bad_Opcode },
9361     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9362   },
9363   /* VEX_LEN_0F42_P_0 */
9364   {
9365     { Bad_Opcode },
9366     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9367   },
9368   /* VEX_LEN_0F42_P_2 */
9369   {
9370     { Bad_Opcode },
9371     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9372   },
9373   /* VEX_LEN_0F44_P_0 */
9374   {
9375     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9376   },
9377   /* VEX_LEN_0F44_P_2 */
9378   {
9379     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9380   },
9381   /* VEX_LEN_0F45_P_0 */
9382   {
9383     { Bad_Opcode },
9384     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9385   },
9386   /* VEX_LEN_0F45_P_2 */
9387   {
9388     { Bad_Opcode },
9389     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9390   },
9391   /* VEX_LEN_0F46_P_0 */
9392   {
9393     { Bad_Opcode },
9394     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9395   },
9396   /* VEX_LEN_0F46_P_2 */
9397   {
9398     { Bad_Opcode },
9399     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9400   },
9401   /* VEX_LEN_0F47_P_0 */
9402   {
9403     { Bad_Opcode },
9404     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9405   },
9406   /* VEX_LEN_0F47_P_2 */
9407   {
9408     { Bad_Opcode },
9409     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9410   },
9411   /* VEX_LEN_0F4A_P_0 */
9412   {
9413     { Bad_Opcode },
9414     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9415   },
9416   /* VEX_LEN_0F4A_P_2 */
9417   {
9418     { Bad_Opcode },
9419     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9420   },
9421   /* VEX_LEN_0F4B_P_0 */
9422   {
9423     { Bad_Opcode },
9424     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9425   },
9426   /* VEX_LEN_0F4B_P_2 */
9427   {
9428     { Bad_Opcode },
9429     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9430   },
9431
9432   /* VEX_LEN_0F6E_P_2 */
9433   {
9434     { "vmovK",          { XMScalar, Edq }, 0 },
9435   },
9436
9437   /* VEX_LEN_0F77_P_1 */
9438   {
9439     { "vzeroupper",     { XX }, 0 },
9440     { "vzeroall",       { XX }, 0 },
9441   },
9442
9443   /* VEX_LEN_0F7E_P_1 */
9444   {
9445     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9446   },
9447
9448   /* VEX_LEN_0F7E_P_2 */
9449   {
9450     { "vmovK",          { Edq, XMScalar }, 0 },
9451   },
9452
9453   /* VEX_LEN_0F90_P_0 */
9454   {
9455     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9456   },
9457
9458   /* VEX_LEN_0F90_P_2 */
9459   {
9460     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9461   },
9462
9463   /* VEX_LEN_0F91_P_0 */
9464   {
9465     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9466   },
9467
9468   /* VEX_LEN_0F91_P_2 */
9469   {
9470     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9471   },
9472
9473   /* VEX_LEN_0F92_P_0 */
9474   {
9475     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9476   },
9477
9478   /* VEX_LEN_0F92_P_2 */
9479   {
9480     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9481   },
9482
9483   /* VEX_LEN_0F92_P_3 */
9484   {
9485     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9486   },
9487
9488   /* VEX_LEN_0F93_P_0 */
9489   {
9490     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9491   },
9492
9493   /* VEX_LEN_0F93_P_2 */
9494   {
9495     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9496   },
9497
9498   /* VEX_LEN_0F93_P_3 */
9499   {
9500     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9501   },
9502
9503   /* VEX_LEN_0F98_P_0 */
9504   {
9505     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9506   },
9507
9508   /* VEX_LEN_0F98_P_2 */
9509   {
9510     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9511   },
9512
9513   /* VEX_LEN_0F99_P_0 */
9514   {
9515     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9516   },
9517
9518   /* VEX_LEN_0F99_P_2 */
9519   {
9520     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9521   },
9522
9523   /* VEX_LEN_0FAE_R_2_M_0 */
9524   {
9525     { "vldmxcsr",       { Md }, 0 },
9526   },
9527
9528   /* VEX_LEN_0FAE_R_3_M_0 */
9529   {
9530     { "vstmxcsr",       { Md }, 0 },
9531   },
9532
9533   /* VEX_LEN_0FC4_P_2 */
9534   {
9535     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9536   },
9537
9538   /* VEX_LEN_0FC5_P_2 */
9539   {
9540     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9541   },
9542
9543   /* VEX_LEN_0FD6_P_2 */
9544   {
9545     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9546   },
9547
9548   /* VEX_LEN_0FF7_P_2 */
9549   {
9550     { "vmaskmovdqu",    { XM, XS }, 0 },
9551   },
9552
9553   /* VEX_LEN_0F3816_P_2 */
9554   {
9555     { Bad_Opcode },
9556     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9557   },
9558
9559   /* VEX_LEN_0F3819_P_2 */
9560   {
9561     { Bad_Opcode },
9562     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9563   },
9564
9565   /* VEX_LEN_0F381A_P_2_M_0 */
9566   {
9567     { Bad_Opcode },
9568     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9569   },
9570
9571   /* VEX_LEN_0F3836_P_2 */
9572   {
9573     { Bad_Opcode },
9574     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9575   },
9576
9577   /* VEX_LEN_0F3841_P_2 */
9578   {
9579     { "vphminposuw",    { XM, EXx }, 0 },
9580   },
9581
9582   /* VEX_LEN_0F385A_P_2_M_0 */
9583   {
9584     { Bad_Opcode },
9585     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9586   },
9587
9588   /* VEX_LEN_0F38DB_P_2 */
9589   {
9590     { "vaesimc",        { XM, EXx }, 0 },
9591   },
9592
9593   /* VEX_LEN_0F38F2_P_0 */
9594   {
9595     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9596   },
9597
9598   /* VEX_LEN_0F38F3_R_1_P_0 */
9599   {
9600     { "blsrS",          { VexGdq, Edq }, 0 },
9601   },
9602
9603   /* VEX_LEN_0F38F3_R_2_P_0 */
9604   {
9605     { "blsmskS",        { VexGdq, Edq }, 0 },
9606   },
9607
9608   /* VEX_LEN_0F38F3_R_3_P_0 */
9609   {
9610     { "blsiS",          { VexGdq, Edq }, 0 },
9611   },
9612
9613   /* VEX_LEN_0F38F5_P_0 */
9614   {
9615     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9616   },
9617
9618   /* VEX_LEN_0F38F5_P_1 */
9619   {
9620     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9621   },
9622
9623   /* VEX_LEN_0F38F5_P_3 */
9624   {
9625     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9626   },
9627
9628   /* VEX_LEN_0F38F6_P_3 */
9629   {
9630     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9631   },
9632
9633   /* VEX_LEN_0F38F7_P_0 */
9634   {
9635     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9636   },
9637
9638   /* VEX_LEN_0F38F7_P_1 */
9639   {
9640     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9641   },
9642
9643   /* VEX_LEN_0F38F7_P_2 */
9644   {
9645     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9646   },
9647
9648   /* VEX_LEN_0F38F7_P_3 */
9649   {
9650     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9651   },
9652
9653   /* VEX_LEN_0F3A00_P_2 */
9654   {
9655     { Bad_Opcode },
9656     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9657   },
9658
9659   /* VEX_LEN_0F3A01_P_2 */
9660   {
9661     { Bad_Opcode },
9662     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9663   },
9664
9665   /* VEX_LEN_0F3A06_P_2 */
9666   {
9667     { Bad_Opcode },
9668     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9669   },
9670
9671   /* VEX_LEN_0F3A14_P_2 */
9672   {
9673     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9674   },
9675
9676   /* VEX_LEN_0F3A15_P_2 */
9677   {
9678     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9679   },
9680
9681   /* VEX_LEN_0F3A16_P_2  */
9682   {
9683     { "vpextrK",        { Edq, XM, Ib }, 0 },
9684   },
9685
9686   /* VEX_LEN_0F3A17_P_2 */
9687   {
9688     { "vextractps",     { Edqd, XM, Ib }, 0 },
9689   },
9690
9691   /* VEX_LEN_0F3A18_P_2 */
9692   {
9693     { Bad_Opcode },
9694     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9695   },
9696
9697   /* VEX_LEN_0F3A19_P_2 */
9698   {
9699     { Bad_Opcode },
9700     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9701   },
9702
9703   /* VEX_LEN_0F3A20_P_2 */
9704   {
9705     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9706   },
9707
9708   /* VEX_LEN_0F3A21_P_2 */
9709   {
9710     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9711   },
9712
9713   /* VEX_LEN_0F3A22_P_2 */
9714   {
9715     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9716   },
9717
9718   /* VEX_LEN_0F3A30_P_2 */
9719   {
9720     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9721   },
9722
9723   /* VEX_LEN_0F3A31_P_2 */
9724   {
9725     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9726   },
9727
9728   /* VEX_LEN_0F3A32_P_2 */
9729   {
9730     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9731   },
9732
9733   /* VEX_LEN_0F3A33_P_2 */
9734   {
9735     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9736   },
9737
9738   /* VEX_LEN_0F3A38_P_2 */
9739   {
9740     { Bad_Opcode },
9741     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9742   },
9743
9744   /* VEX_LEN_0F3A39_P_2 */
9745   {
9746     { Bad_Opcode },
9747     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9748   },
9749
9750   /* VEX_LEN_0F3A41_P_2 */
9751   {
9752     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9753   },
9754
9755   /* VEX_LEN_0F3A46_P_2 */
9756   {
9757     { Bad_Opcode },
9758     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9759   },
9760
9761   /* VEX_LEN_0F3A60_P_2 */
9762   {
9763     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9764   },
9765
9766   /* VEX_LEN_0F3A61_P_2 */
9767   {
9768     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9769   },
9770
9771   /* VEX_LEN_0F3A62_P_2 */
9772   {
9773     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9774   },
9775
9776   /* VEX_LEN_0F3A63_P_2 */
9777   {
9778     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9779   },
9780
9781   /* VEX_LEN_0F3A6A_P_2 */
9782   {
9783     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9784   },
9785
9786   /* VEX_LEN_0F3A6B_P_2 */
9787   {
9788     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9789   },
9790
9791   /* VEX_LEN_0F3A6E_P_2 */
9792   {
9793     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9794   },
9795
9796   /* VEX_LEN_0F3A6F_P_2 */
9797   {
9798     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9799   },
9800
9801   /* VEX_LEN_0F3A7A_P_2 */
9802   {
9803     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9804   },
9805
9806   /* VEX_LEN_0F3A7B_P_2 */
9807   {
9808     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9809   },
9810
9811   /* VEX_LEN_0F3A7E_P_2 */
9812   {
9813     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9814   },
9815
9816   /* VEX_LEN_0F3A7F_P_2 */
9817   {
9818     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9819   },
9820
9821   /* VEX_LEN_0F3ADF_P_2 */
9822   {
9823     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9824   },
9825
9826   /* VEX_LEN_0F3AF0_P_3 */
9827   {
9828     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9829   },
9830
9831   /* VEX_LEN_0FXOP_08_CC */
9832   {
9833      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9834   },
9835
9836   /* VEX_LEN_0FXOP_08_CD */
9837   {
9838      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9839   },
9840
9841   /* VEX_LEN_0FXOP_08_CE */
9842   {
9843      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9844   },
9845
9846   /* VEX_LEN_0FXOP_08_CF */
9847   {
9848      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9849   },
9850
9851   /* VEX_LEN_0FXOP_08_EC */
9852   {
9853      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9854   },
9855
9856   /* VEX_LEN_0FXOP_08_ED */
9857   {
9858      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9859   },
9860
9861   /* VEX_LEN_0FXOP_08_EE */
9862   {
9863      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9864   },
9865
9866   /* VEX_LEN_0FXOP_08_EF */
9867   {
9868      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9869   },
9870
9871   /* VEX_LEN_0FXOP_09_80 */
9872   {
9873     { "vfrczps",        { XM, EXxmm }, 0 },
9874     { "vfrczps",        { XM, EXymmq }, 0 },
9875   },
9876
9877   /* VEX_LEN_0FXOP_09_81 */
9878   {
9879     { "vfrczpd",        { XM, EXxmm }, 0 },
9880     { "vfrczpd",        { XM, EXymmq }, 0 },
9881   },
9882 };
9883
9884 static const struct dis386 evex_len_table[][3] = {
9885 #define NEED_EVEX_LEN_TABLE
9886 #include "i386-dis-evex.h"
9887 #undef NEED_EVEX_LEN_TABLE
9888 };
9889
9890 static const struct dis386 vex_w_table[][2] = {
9891   {
9892     /* VEX_W_0F41_P_0_LEN_1 */
9893     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9894     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9895   },
9896   {
9897     /* VEX_W_0F41_P_2_LEN_1 */
9898     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9899     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9900   },
9901   {
9902     /* VEX_W_0F42_P_0_LEN_1 */
9903     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9904     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9905   },
9906   {
9907     /* VEX_W_0F42_P_2_LEN_1 */
9908     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9909     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9910   },
9911   {
9912     /* VEX_W_0F44_P_0_LEN_0 */
9913     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9914     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9915   },
9916   {
9917     /* VEX_W_0F44_P_2_LEN_0 */
9918     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9919     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9920   },
9921   {
9922     /* VEX_W_0F45_P_0_LEN_1 */
9923     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9924     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9925   },
9926   {
9927     /* VEX_W_0F45_P_2_LEN_1 */
9928     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9929     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9930   },
9931   {
9932     /* VEX_W_0F46_P_0_LEN_1 */
9933     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9934     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9935   },
9936   {
9937     /* VEX_W_0F46_P_2_LEN_1 */
9938     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9939     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9940   },
9941   {
9942     /* VEX_W_0F47_P_0_LEN_1 */
9943     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9944     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9945   },
9946   {
9947     /* VEX_W_0F47_P_2_LEN_1 */
9948     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9949     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9950   },
9951   {
9952     /* VEX_W_0F4A_P_0_LEN_1 */
9953     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9954     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9955   },
9956   {
9957     /* VEX_W_0F4A_P_2_LEN_1 */
9958     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9959     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9960   },
9961   {
9962     /* VEX_W_0F4B_P_0_LEN_1 */
9963     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9964     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9965   },
9966   {
9967     /* VEX_W_0F4B_P_2_LEN_1 */
9968     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9969   },
9970   {
9971     /* VEX_W_0F90_P_0_LEN_0 */
9972     { "kmovw",          { MaskG, MaskE }, 0 },
9973     { "kmovq",          { MaskG, MaskE }, 0 },
9974   },
9975   {
9976     /* VEX_W_0F90_P_2_LEN_0 */
9977     { "kmovb",          { MaskG, MaskBDE }, 0 },
9978     { "kmovd",          { MaskG, MaskBDE }, 0 },
9979   },
9980   {
9981     /* VEX_W_0F91_P_0_LEN_0 */
9982     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9983     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9984   },
9985   {
9986     /* VEX_W_0F91_P_2_LEN_0 */
9987     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9988     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9989   },
9990   {
9991     /* VEX_W_0F92_P_0_LEN_0 */
9992     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9993   },
9994   {
9995     /* VEX_W_0F92_P_2_LEN_0 */
9996     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9997   },
9998   {
9999     /* VEX_W_0F93_P_0_LEN_0 */
10000     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10001   },
10002   {
10003     /* VEX_W_0F93_P_2_LEN_0 */
10004     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10005   },
10006   {
10007     /* VEX_W_0F98_P_0_LEN_0 */
10008     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10009     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10010   },
10011   {
10012     /* VEX_W_0F98_P_2_LEN_0 */
10013     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10014     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10015   },
10016   {
10017     /* VEX_W_0F99_P_0_LEN_0 */
10018     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10019     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10020   },
10021   {
10022     /* VEX_W_0F99_P_2_LEN_0 */
10023     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10024     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10025   },
10026   {
10027     /* VEX_W_0F380C_P_2  */
10028     { "vpermilps",      { XM, Vex, EXx }, 0 },
10029   },
10030   {
10031     /* VEX_W_0F380D_P_2  */
10032     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10033   },
10034   {
10035     /* VEX_W_0F380E_P_2  */
10036     { "vtestps",        { XM, EXx }, 0 },
10037   },
10038   {
10039     /* VEX_W_0F380F_P_2  */
10040     { "vtestpd",        { XM, EXx }, 0 },
10041   },
10042   {
10043     /* VEX_W_0F3816_P_2  */
10044     { "vpermps",        { XM, Vex, EXx }, 0 },
10045   },
10046   {
10047     /* VEX_W_0F3818_P_2 */
10048     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10049   },
10050   {
10051     /* VEX_W_0F3819_P_2 */
10052     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10053   },
10054   {
10055     /* VEX_W_0F381A_P_2_M_0 */
10056     { "vbroadcastf128", { XM, Mxmm }, 0 },
10057   },
10058   {
10059     /* VEX_W_0F382C_P_2_M_0 */
10060     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10061   },
10062   {
10063     /* VEX_W_0F382D_P_2_M_0 */
10064     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10065   },
10066   {
10067     /* VEX_W_0F382E_P_2_M_0 */
10068     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10069   },
10070   {
10071     /* VEX_W_0F382F_P_2_M_0 */
10072     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10073   },
10074   {
10075     /* VEX_W_0F3836_P_2  */
10076     { "vpermd",         { XM, Vex, EXx }, 0 },
10077   },
10078   {
10079     /* VEX_W_0F3846_P_2 */
10080     { "vpsravd",        { XM, Vex, EXx }, 0 },
10081   },
10082   {
10083     /* VEX_W_0F3858_P_2 */
10084     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10085   },
10086   {
10087     /* VEX_W_0F3859_P_2 */
10088     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10089   },
10090   {
10091     /* VEX_W_0F385A_P_2_M_0 */
10092     { "vbroadcasti128", { XM, Mxmm }, 0 },
10093   },
10094   {
10095     /* VEX_W_0F3878_P_2 */
10096     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10097   },
10098   {
10099     /* VEX_W_0F3879_P_2 */
10100     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10101   },
10102   {
10103     /* VEX_W_0F38CF_P_2 */
10104     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10105   },
10106   {
10107     /* VEX_W_0F3A00_P_2 */
10108     { Bad_Opcode },
10109     { "vpermq",         { XM, EXx, Ib }, 0 },
10110   },
10111   {
10112     /* VEX_W_0F3A01_P_2 */
10113     { Bad_Opcode },
10114     { "vpermpd",        { XM, EXx, Ib }, 0 },
10115   },
10116   {
10117     /* VEX_W_0F3A02_P_2 */
10118     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10119   },
10120   {
10121     /* VEX_W_0F3A04_P_2 */
10122     { "vpermilps",      { XM, EXx, Ib }, 0 },
10123   },
10124   {
10125     /* VEX_W_0F3A05_P_2 */
10126     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10127   },
10128   {
10129     /* VEX_W_0F3A06_P_2 */
10130     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10131   },
10132   {
10133     /* VEX_W_0F3A18_P_2 */
10134     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10135   },
10136   {
10137     /* VEX_W_0F3A19_P_2 */
10138     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10139   },
10140   {
10141     /* VEX_W_0F3A30_P_2_LEN_0 */
10142     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10143     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10144   },
10145   {
10146     /* VEX_W_0F3A31_P_2_LEN_0 */
10147     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10148     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10149   },
10150   {
10151     /* VEX_W_0F3A32_P_2_LEN_0 */
10152     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10153     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10154   },
10155   {
10156     /* VEX_W_0F3A33_P_2_LEN_0 */
10157     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10158     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10159   },
10160   {
10161     /* VEX_W_0F3A38_P_2 */
10162     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10163   },
10164   {
10165     /* VEX_W_0F3A39_P_2 */
10166     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10167   },
10168   {
10169     /* VEX_W_0F3A46_P_2 */
10170     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10171   },
10172   {
10173     /* VEX_W_0F3A48_P_2 */
10174     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10175     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10176   },
10177   {
10178     /* VEX_W_0F3A49_P_2 */
10179     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10180     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10181   },
10182   {
10183     /* VEX_W_0F3A4A_P_2 */
10184     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10185   },
10186   {
10187     /* VEX_W_0F3A4B_P_2 */
10188     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10189   },
10190   {
10191     /* VEX_W_0F3A4C_P_2 */
10192     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10193   },
10194   {
10195     /* VEX_W_0F3ACE_P_2 */
10196     { Bad_Opcode },
10197     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10198   },
10199   {
10200     /* VEX_W_0F3ACF_P_2 */
10201     { Bad_Opcode },
10202     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10203   },
10204 #define NEED_VEX_W_TABLE
10205 #include "i386-dis-evex.h"
10206 #undef NEED_VEX_W_TABLE
10207 };
10208
10209 static const struct dis386 mod_table[][2] = {
10210   {
10211     /* MOD_8D */
10212     { "leaS",           { Gv, M }, 0 },
10213   },
10214   {
10215     /* MOD_C6_REG_7 */
10216     { Bad_Opcode },
10217     { RM_TABLE (RM_C6_REG_7) },
10218   },
10219   {
10220     /* MOD_C7_REG_7 */
10221     { Bad_Opcode },
10222     { RM_TABLE (RM_C7_REG_7) },
10223   },
10224   {
10225     /* MOD_FF_REG_3 */
10226     { "Jcall^", { indirEp }, 0 },
10227   },
10228   {
10229     /* MOD_FF_REG_5 */
10230     { "Jjmp^", { indirEp }, 0 },
10231   },
10232   {
10233     /* MOD_0F01_REG_0 */
10234     { X86_64_TABLE (X86_64_0F01_REG_0) },
10235     { RM_TABLE (RM_0F01_REG_0) },
10236   },
10237   {
10238     /* MOD_0F01_REG_1 */
10239     { X86_64_TABLE (X86_64_0F01_REG_1) },
10240     { RM_TABLE (RM_0F01_REG_1) },
10241   },
10242   {
10243     /* MOD_0F01_REG_2 */
10244     { X86_64_TABLE (X86_64_0F01_REG_2) },
10245     { RM_TABLE (RM_0F01_REG_2) },
10246   },
10247   {
10248     /* MOD_0F01_REG_3 */
10249     { X86_64_TABLE (X86_64_0F01_REG_3) },
10250     { RM_TABLE (RM_0F01_REG_3) },
10251   },
10252   {
10253     /* MOD_0F01_REG_5 */
10254     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
10255     { RM_TABLE (RM_0F01_REG_5) },
10256   },
10257   {
10258     /* MOD_0F01_REG_7 */
10259     { "invlpg",         { Mb }, 0 },
10260     { RM_TABLE (RM_0F01_REG_7) },
10261   },
10262   {
10263     /* MOD_0F12_PREFIX_0 */
10264     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10265     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10266   },
10267   {
10268     /* MOD_0F13 */
10269     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10270   },
10271   {
10272     /* MOD_0F16_PREFIX_0 */
10273     { "movhps",         { XM, EXq }, 0 },
10274     { "movlhps",        { XM, EXq }, 0 },
10275   },
10276   {
10277     /* MOD_0F17 */
10278     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10279   },
10280   {
10281     /* MOD_0F18_REG_0 */
10282     { "prefetchnta",    { Mb }, 0 },
10283   },
10284   {
10285     /* MOD_0F18_REG_1 */
10286     { "prefetcht0",     { Mb }, 0 },
10287   },
10288   {
10289     /* MOD_0F18_REG_2 */
10290     { "prefetcht1",     { Mb }, 0 },
10291   },
10292   {
10293     /* MOD_0F18_REG_3 */
10294     { "prefetcht2",     { Mb }, 0 },
10295   },
10296   {
10297     /* MOD_0F18_REG_4 */
10298     { "nop/reserved",   { Mb }, 0 },
10299   },
10300   {
10301     /* MOD_0F18_REG_5 */
10302     { "nop/reserved",   { Mb }, 0 },
10303   },
10304   {
10305     /* MOD_0F18_REG_6 */
10306     { "nop/reserved",   { Mb }, 0 },
10307   },
10308   {
10309     /* MOD_0F18_REG_7 */
10310     { "nop/reserved",   { Mb }, 0 },
10311   },
10312   {
10313     /* MOD_0F1A_PREFIX_0 */
10314     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10315     { "nopQ",           { Ev }, 0 },
10316   },
10317   {
10318     /* MOD_0F1B_PREFIX_0 */
10319     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10320     { "nopQ",           { Ev }, 0 },
10321   },
10322   {
10323     /* MOD_0F1B_PREFIX_1 */
10324     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10325     { "nopQ",           { Ev }, 0 },
10326   },
10327   {
10328     /* MOD_0F1C_PREFIX_0 */
10329     { REG_TABLE (REG_0F1C_MOD_0) },
10330     { "nopQ",           { Ev }, 0 },
10331   },
10332   {
10333     /* MOD_0F1E_PREFIX_1 */
10334     { "nopQ",           { Ev }, 0 },
10335     { REG_TABLE (REG_0F1E_MOD_3) },
10336   },
10337   {
10338     /* MOD_0F24 */
10339     { Bad_Opcode },
10340     { "movL",           { Rd, Td }, 0 },
10341   },
10342   {
10343     /* MOD_0F26 */
10344     { Bad_Opcode },
10345     { "movL",           { Td, Rd }, 0 },
10346   },
10347   {
10348     /* MOD_0F2B_PREFIX_0 */
10349     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10350   },
10351   {
10352     /* MOD_0F2B_PREFIX_1 */
10353     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10354   },
10355   {
10356     /* MOD_0F2B_PREFIX_2 */
10357     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10358   },
10359   {
10360     /* MOD_0F2B_PREFIX_3 */
10361     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10362   },
10363   {
10364     /* MOD_0F51 */
10365     { Bad_Opcode },
10366     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10367   },
10368   {
10369     /* MOD_0F71_REG_2 */
10370     { Bad_Opcode },
10371     { "psrlw",          { MS, Ib }, 0 },
10372   },
10373   {
10374     /* MOD_0F71_REG_4 */
10375     { Bad_Opcode },
10376     { "psraw",          { MS, Ib }, 0 },
10377   },
10378   {
10379     /* MOD_0F71_REG_6 */
10380     { Bad_Opcode },
10381     { "psllw",          { MS, Ib }, 0 },
10382   },
10383   {
10384     /* MOD_0F72_REG_2 */
10385     { Bad_Opcode },
10386     { "psrld",          { MS, Ib }, 0 },
10387   },
10388   {
10389     /* MOD_0F72_REG_4 */
10390     { Bad_Opcode },
10391     { "psrad",          { MS, Ib }, 0 },
10392   },
10393   {
10394     /* MOD_0F72_REG_6 */
10395     { Bad_Opcode },
10396     { "pslld",          { MS, Ib }, 0 },
10397   },
10398   {
10399     /* MOD_0F73_REG_2 */
10400     { Bad_Opcode },
10401     { "psrlq",          { MS, Ib }, 0 },
10402   },
10403   {
10404     /* MOD_0F73_REG_3 */
10405     { Bad_Opcode },
10406     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10407   },
10408   {
10409     /* MOD_0F73_REG_6 */
10410     { Bad_Opcode },
10411     { "psllq",          { MS, Ib }, 0 },
10412   },
10413   {
10414     /* MOD_0F73_REG_7 */
10415     { Bad_Opcode },
10416     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10417   },
10418   {
10419     /* MOD_0FAE_REG_0 */
10420     { "fxsave",         { FXSAVE }, 0 },
10421     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10422   },
10423   {
10424     /* MOD_0FAE_REG_1 */
10425     { "fxrstor",        { FXSAVE }, 0 },
10426     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10427   },
10428   {
10429     /* MOD_0FAE_REG_2 */
10430     { "ldmxcsr",        { Md }, 0 },
10431     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10432   },
10433   {
10434     /* MOD_0FAE_REG_3 */
10435     { "stmxcsr",        { Md }, 0 },
10436     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10437   },
10438   {
10439     /* MOD_0FAE_REG_4 */
10440     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
10441     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
10442   },
10443   {
10444     /* MOD_0FAE_REG_5 */
10445     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
10446     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
10447   },
10448   {
10449     /* MOD_0FAE_REG_6 */
10450     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
10451     { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
10452   },
10453   {
10454     /* MOD_0FAE_REG_7 */
10455     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
10456     { RM_TABLE (RM_0FAE_REG_7) },
10457   },
10458   {
10459     /* MOD_0FB2 */
10460     { "lssS",           { Gv, Mp }, 0 },
10461   },
10462   {
10463     /* MOD_0FB4 */
10464     { "lfsS",           { Gv, Mp }, 0 },
10465   },
10466   {
10467     /* MOD_0FB5 */
10468     { "lgsS",           { Gv, Mp }, 0 },
10469   },
10470   {
10471     /* MOD_0FC3 */
10472     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
10473   },
10474   {
10475     /* MOD_0FC7_REG_3 */
10476     { "xrstors",        { FXSAVE }, 0 },
10477   },
10478   {
10479     /* MOD_0FC7_REG_4 */
10480     { "xsavec",         { FXSAVE }, 0 },
10481   },
10482   {
10483     /* MOD_0FC7_REG_5 */
10484     { "xsaves",         { FXSAVE }, 0 },
10485   },
10486   {
10487     /* MOD_0FC7_REG_6 */
10488     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
10489     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
10490   },
10491   {
10492     /* MOD_0FC7_REG_7 */
10493     { "vmptrst",        { Mq }, 0 },
10494     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
10495   },
10496   {
10497     /* MOD_0FD7 */
10498     { Bad_Opcode },
10499     { "pmovmskb",       { Gdq, MS }, 0 },
10500   },
10501   {
10502     /* MOD_0FE7_PREFIX_2 */
10503     { "movntdq",        { Mx, XM }, 0 },
10504   },
10505   {
10506     /* MOD_0FF0_PREFIX_3 */
10507     { "lddqu",          { XM, M }, 0 },
10508   },
10509   {
10510     /* MOD_0F382A_PREFIX_2 */
10511     { "movntdqa",       { XM, Mx }, 0 },
10512   },
10513   {
10514     /* MOD_0F38F5_PREFIX_2 */
10515     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10516   },
10517   {
10518     /* MOD_0F38F6_PREFIX_0 */
10519     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10520   },
10521   {
10522     /* MOD_0F38F8_PREFIX_2 */
10523     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10524   },
10525   {
10526     /* MOD_0F38F9_PREFIX_0 */
10527     { "movdiri",        { Em, Gv }, PREFIX_OPCODE },
10528   },
10529   {
10530     /* MOD_62_32BIT */
10531     { "bound{S|}",      { Gv, Ma }, 0 },
10532     { EVEX_TABLE (EVEX_0F) },
10533   },
10534   {
10535     /* MOD_C4_32BIT */
10536     { "lesS",           { Gv, Mp }, 0 },
10537     { VEX_C4_TABLE (VEX_0F) },
10538   },
10539   {
10540     /* MOD_C5_32BIT */
10541     { "ldsS",           { Gv, Mp }, 0 },
10542     { VEX_C5_TABLE (VEX_0F) },
10543   },
10544   {
10545     /* MOD_VEX_0F12_PREFIX_0 */
10546     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10547     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10548   },
10549   {
10550     /* MOD_VEX_0F13 */
10551     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10552   },
10553   {
10554     /* MOD_VEX_0F16_PREFIX_0 */
10555     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10556     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10557   },
10558   {
10559     /* MOD_VEX_0F17 */
10560     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10561   },
10562   {
10563     /* MOD_VEX_0F2B */
10564     { "vmovntpX",       { Mx, XM }, 0 },
10565   },
10566   {
10567     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10568     { Bad_Opcode },
10569     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10570   },
10571   {
10572     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10573     { Bad_Opcode },
10574     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10575   },
10576   {
10577     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10578     { Bad_Opcode },
10579     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10580   },
10581   {
10582     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10583     { Bad_Opcode },
10584     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10585   },
10586   {
10587     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10588     { Bad_Opcode },
10589     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10590   },
10591   {
10592     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10593     { Bad_Opcode },
10594     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10595   },
10596   {
10597     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10598     { Bad_Opcode },
10599     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10600   },
10601   {
10602     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10603     { Bad_Opcode },
10604     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10605   },
10606   {
10607     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10608     { Bad_Opcode },
10609     { "knotw",          { MaskG, MaskR }, 0 },
10610   },
10611   {
10612     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10613     { Bad_Opcode },
10614     { "knotq",          { MaskG, MaskR }, 0 },
10615   },
10616   {
10617     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10618     { Bad_Opcode },
10619     { "knotb",          { MaskG, MaskR }, 0 },
10620   },
10621   {
10622     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10623     { Bad_Opcode },
10624     { "knotd",          { MaskG, MaskR }, 0 },
10625   },
10626   {
10627     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10628     { Bad_Opcode },
10629     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10630   },
10631   {
10632     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10633     { Bad_Opcode },
10634     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10635   },
10636   {
10637     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10638     { Bad_Opcode },
10639     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10640   },
10641   {
10642     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10643     { Bad_Opcode },
10644     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10645   },
10646  {
10647     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10648     { Bad_Opcode },
10649     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10650   },
10651   {
10652     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10653     { Bad_Opcode },
10654     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10655   },
10656   {
10657     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10658     { Bad_Opcode },
10659     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10660   },
10661   {
10662     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10663     { Bad_Opcode },
10664     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10665   },
10666   {
10667     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10668     { Bad_Opcode },
10669     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10670   },
10671   {
10672     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10673     { Bad_Opcode },
10674     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10675   },
10676   {
10677     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10678     { Bad_Opcode },
10679     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10680   },
10681   {
10682     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10683     { Bad_Opcode },
10684     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10685   },
10686   {
10687     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10688     { Bad_Opcode },
10689     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10690   },
10691   {
10692     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10693     { Bad_Opcode },
10694     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10695   },
10696   {
10697     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10698     { Bad_Opcode },
10699     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10700   },
10701   {
10702     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10703     { Bad_Opcode },
10704     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10705   },
10706   {
10707     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10708     { Bad_Opcode },
10709     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10710   },
10711   {
10712     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10713     { Bad_Opcode },
10714     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10715   },
10716   {
10717     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10718     { Bad_Opcode },
10719     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10720   },
10721   {
10722     /* MOD_VEX_0F50 */
10723     { Bad_Opcode },
10724     { "vmovmskpX",      { Gdq, XS }, 0 },
10725   },
10726   {
10727     /* MOD_VEX_0F71_REG_2 */
10728     { Bad_Opcode },
10729     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10730   },
10731   {
10732     /* MOD_VEX_0F71_REG_4 */
10733     { Bad_Opcode },
10734     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10735   },
10736   {
10737     /* MOD_VEX_0F71_REG_6 */
10738     { Bad_Opcode },
10739     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10740   },
10741   {
10742     /* MOD_VEX_0F72_REG_2 */
10743     { Bad_Opcode },
10744     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10745   },
10746   {
10747     /* MOD_VEX_0F72_REG_4 */
10748     { Bad_Opcode },
10749     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10750   },
10751   {
10752     /* MOD_VEX_0F72_REG_6 */
10753     { Bad_Opcode },
10754     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10755   },
10756   {
10757     /* MOD_VEX_0F73_REG_2 */
10758     { Bad_Opcode },
10759     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10760   },
10761   {
10762     /* MOD_VEX_0F73_REG_3 */
10763     { Bad_Opcode },
10764     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10765   },
10766   {
10767     /* MOD_VEX_0F73_REG_6 */
10768     { Bad_Opcode },
10769     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10770   },
10771   {
10772     /* MOD_VEX_0F73_REG_7 */
10773     { Bad_Opcode },
10774     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10775   },
10776   {
10777     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10778     { "kmovw",          { Ew, MaskG }, 0 },
10779     { Bad_Opcode },
10780   },
10781   {
10782     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10783     { "kmovq",          { Eq, MaskG }, 0 },
10784     { Bad_Opcode },
10785   },
10786   {
10787     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10788     { "kmovb",          { Eb, MaskG }, 0 },
10789     { Bad_Opcode },
10790   },
10791   {
10792     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10793     { "kmovd",          { Ed, MaskG }, 0 },
10794     { Bad_Opcode },
10795   },
10796   {
10797     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10798     { Bad_Opcode },
10799     { "kmovw",          { MaskG, Rdq }, 0 },
10800   },
10801   {
10802     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10803     { Bad_Opcode },
10804     { "kmovb",          { MaskG, Rdq }, 0 },
10805   },
10806   {
10807     /* MOD_VEX_0F92_P_3_LEN_0 */
10808     { Bad_Opcode },
10809     { "kmovK",          { MaskG, Rdq }, 0 },
10810   },
10811   {
10812     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10813     { Bad_Opcode },
10814     { "kmovw",          { Gdq, MaskR }, 0 },
10815   },
10816   {
10817     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10818     { Bad_Opcode },
10819     { "kmovb",          { Gdq, MaskR }, 0 },
10820   },
10821   {
10822     /* MOD_VEX_0F93_P_3_LEN_0 */
10823     { Bad_Opcode },
10824     { "kmovK",          { Gdq, MaskR }, 0 },
10825   },
10826   {
10827     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10828     { Bad_Opcode },
10829     { "kortestw", { MaskG, MaskR }, 0 },
10830   },
10831   {
10832     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10833     { Bad_Opcode },
10834     { "kortestq", { MaskG, MaskR }, 0 },
10835   },
10836   {
10837     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10838     { Bad_Opcode },
10839     { "kortestb", { MaskG, MaskR }, 0 },
10840   },
10841   {
10842     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10843     { Bad_Opcode },
10844     { "kortestd", { MaskG, MaskR }, 0 },
10845   },
10846   {
10847     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10848     { Bad_Opcode },
10849     { "ktestw", { MaskG, MaskR }, 0 },
10850   },
10851   {
10852     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10853     { Bad_Opcode },
10854     { "ktestq", { MaskG, MaskR }, 0 },
10855   },
10856   {
10857     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10858     { Bad_Opcode },
10859     { "ktestb", { MaskG, MaskR }, 0 },
10860   },
10861   {
10862     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10863     { Bad_Opcode },
10864     { "ktestd", { MaskG, MaskR }, 0 },
10865   },
10866   {
10867     /* MOD_VEX_0FAE_REG_2 */
10868     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10869   },
10870   {
10871     /* MOD_VEX_0FAE_REG_3 */
10872     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10873   },
10874   {
10875     /* MOD_VEX_0FD7_PREFIX_2 */
10876     { Bad_Opcode },
10877     { "vpmovmskb",      { Gdq, XS }, 0 },
10878   },
10879   {
10880     /* MOD_VEX_0FE7_PREFIX_2 */
10881     { "vmovntdq",       { Mx, XM }, 0 },
10882   },
10883   {
10884     /* MOD_VEX_0FF0_PREFIX_3 */
10885     { "vlddqu",         { XM, M }, 0 },
10886   },
10887   {
10888     /* MOD_VEX_0F381A_PREFIX_2 */
10889     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10890   },
10891   {
10892     /* MOD_VEX_0F382A_PREFIX_2 */
10893     { "vmovntdqa",      { XM, Mx }, 0 },
10894   },
10895   {
10896     /* MOD_VEX_0F382C_PREFIX_2 */
10897     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10898   },
10899   {
10900     /* MOD_VEX_0F382D_PREFIX_2 */
10901     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10902   },
10903   {
10904     /* MOD_VEX_0F382E_PREFIX_2 */
10905     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10906   },
10907   {
10908     /* MOD_VEX_0F382F_PREFIX_2 */
10909     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10910   },
10911   {
10912     /* MOD_VEX_0F385A_PREFIX_2 */
10913     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10914   },
10915   {
10916     /* MOD_VEX_0F388C_PREFIX_2 */
10917     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10918   },
10919   {
10920     /* MOD_VEX_0F388E_PREFIX_2 */
10921     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10922   },
10923   {
10924     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10925     { Bad_Opcode },
10926     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10927   },
10928   {
10929     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10930     { Bad_Opcode },
10931     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10932   },
10933   {
10934     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10935     { Bad_Opcode },
10936     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10937   },
10938   {
10939     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10940     { Bad_Opcode },
10941     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10942   },
10943   {
10944     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10945     { Bad_Opcode },
10946     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10947   },
10948   {
10949     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10950     { Bad_Opcode },
10951     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10952   },
10953   {
10954     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10955     { Bad_Opcode },
10956     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10957   },
10958   {
10959     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10960     { Bad_Opcode },
10961     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10962   },
10963 #define NEED_MOD_TABLE
10964 #include "i386-dis-evex.h"
10965 #undef NEED_MOD_TABLE
10966 };
10967
10968 static const struct dis386 rm_table[][8] = {
10969   {
10970     /* RM_C6_REG_7 */
10971     { "xabort",         { Skip_MODRM, Ib }, 0 },
10972   },
10973   {
10974     /* RM_C7_REG_7 */
10975     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
10976   },
10977   {
10978     /* RM_0F01_REG_0 */
10979     { "enclv",          { Skip_MODRM }, 0 },
10980     { "vmcall",         { Skip_MODRM }, 0 },
10981     { "vmlaunch",       { Skip_MODRM }, 0 },
10982     { "vmresume",       { Skip_MODRM }, 0 },
10983     { "vmxoff",         { Skip_MODRM }, 0 },
10984     { "pconfig",        { Skip_MODRM }, 0 },
10985   },
10986   {
10987     /* RM_0F01_REG_1 */
10988     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10989     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10990     { "clac",           { Skip_MODRM }, 0 },
10991     { "stac",           { Skip_MODRM }, 0 },
10992     { Bad_Opcode },
10993     { Bad_Opcode },
10994     { Bad_Opcode },
10995     { "encls",          { Skip_MODRM }, 0 },
10996   },
10997   {
10998     /* RM_0F01_REG_2 */
10999     { "xgetbv",         { Skip_MODRM }, 0 },
11000     { "xsetbv",         { Skip_MODRM }, 0 },
11001     { Bad_Opcode },
11002     { Bad_Opcode },
11003     { "vmfunc",         { Skip_MODRM }, 0 },
11004     { "xend",           { Skip_MODRM }, 0 },
11005     { "xtest",          { Skip_MODRM }, 0 },
11006     { "enclu",          { Skip_MODRM }, 0 },
11007   },
11008   {
11009     /* RM_0F01_REG_3 */
11010     { "vmrun",          { Skip_MODRM }, 0 },
11011     { "vmmcall",        { Skip_MODRM }, 0 },
11012     { "vmload",         { Skip_MODRM }, 0 },
11013     { "vmsave",         { Skip_MODRM }, 0 },
11014     { "stgi",           { Skip_MODRM }, 0 },
11015     { "clgi",           { Skip_MODRM }, 0 },
11016     { "skinit",         { Skip_MODRM }, 0 },
11017     { "invlpga",        { Skip_MODRM }, 0 },
11018   },
11019   {
11020     /* RM_0F01_REG_5 */
11021     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
11022     { Bad_Opcode },
11023     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
11024     { Bad_Opcode },
11025     { Bad_Opcode },
11026     { Bad_Opcode },
11027     { "rdpkru",         { Skip_MODRM }, 0 },
11028     { "wrpkru",         { Skip_MODRM }, 0 },
11029   },
11030   {
11031     /* RM_0F01_REG_7 */
11032     { "swapgs",         { Skip_MODRM }, 0  },
11033     { "rdtscp",         { Skip_MODRM }, 0  },
11034     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
11035     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
11036     { "clzero",         { Skip_MODRM }, 0  },
11037   },
11038   {
11039     /* RM_0F1E_MOD_3_REG_7 */
11040     { "nopQ",           { Ev }, 0 },
11041     { "nopQ",           { Ev }, 0 },
11042     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11043     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11044     { "nopQ",           { Ev }, 0 },
11045     { "nopQ",           { Ev }, 0 },
11046     { "nopQ",           { Ev }, 0 },
11047     { "nopQ",           { Ev }, 0 },
11048   },
11049   {
11050     /* RM_0FAE_REG_6 */
11051     { "mfence",         { Skip_MODRM }, 0 },
11052   },
11053   {
11054     /* RM_0FAE_REG_7 */
11055     { "sfence",         { Skip_MODRM }, 0 },
11056
11057   },
11058 };
11059
11060 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11061
11062 /* We use the high bit to indicate different name for the same
11063    prefix.  */
11064 #define REP_PREFIX      (0xf3 | 0x100)
11065 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11066 #define XRELEASE_PREFIX (0xf3 | 0x400)
11067 #define BND_PREFIX      (0xf2 | 0x400)
11068 #define NOTRACK_PREFIX  (0x3e | 0x100)
11069
11070 static int
11071 ckprefix (void)
11072 {
11073   int newrex, i, length;
11074   rex = 0;
11075   rex_ignored = 0;
11076   prefixes = 0;
11077   used_prefixes = 0;
11078   rex_used = 0;
11079   last_lock_prefix = -1;
11080   last_repz_prefix = -1;
11081   last_repnz_prefix = -1;
11082   last_data_prefix = -1;
11083   last_addr_prefix = -1;
11084   last_rex_prefix = -1;
11085   last_seg_prefix = -1;
11086   fwait_prefix = -1;
11087   active_seg_prefix = 0;
11088   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11089     all_prefixes[i] = 0;
11090   i = 0;
11091   length = 0;
11092   /* The maximum instruction length is 15bytes.  */
11093   while (length < MAX_CODE_LENGTH - 1)
11094     {
11095       FETCH_DATA (the_info, codep + 1);
11096       newrex = 0;
11097       switch (*codep)
11098         {
11099         /* REX prefixes family.  */
11100         case 0x40:
11101         case 0x41:
11102         case 0x42:
11103         case 0x43:
11104         case 0x44:
11105         case 0x45:
11106         case 0x46:
11107         case 0x47:
11108         case 0x48:
11109         case 0x49:
11110         case 0x4a:
11111         case 0x4b:
11112         case 0x4c:
11113         case 0x4d:
11114         case 0x4e:
11115         case 0x4f:
11116           if (address_mode == mode_64bit)
11117             newrex = *codep;
11118           else
11119             return 1;
11120           last_rex_prefix = i;
11121           break;
11122         case 0xf3:
11123           prefixes |= PREFIX_REPZ;
11124           last_repz_prefix = i;
11125           break;
11126         case 0xf2:
11127           prefixes |= PREFIX_REPNZ;
11128           last_repnz_prefix = i;
11129           break;
11130         case 0xf0:
11131           prefixes |= PREFIX_LOCK;
11132           last_lock_prefix = i;
11133           break;
11134         case 0x2e:
11135           prefixes |= PREFIX_CS;
11136           last_seg_prefix = i;
11137           active_seg_prefix = PREFIX_CS;
11138           break;
11139         case 0x36:
11140           prefixes |= PREFIX_SS;
11141           last_seg_prefix = i;
11142           active_seg_prefix = PREFIX_SS;
11143           break;
11144         case 0x3e:
11145           prefixes |= PREFIX_DS;
11146           last_seg_prefix = i;
11147           active_seg_prefix = PREFIX_DS;
11148           break;
11149         case 0x26:
11150           prefixes |= PREFIX_ES;
11151           last_seg_prefix = i;
11152           active_seg_prefix = PREFIX_ES;
11153           break;
11154         case 0x64:
11155           prefixes |= PREFIX_FS;
11156           last_seg_prefix = i;
11157           active_seg_prefix = PREFIX_FS;
11158           break;
11159         case 0x65:
11160           prefixes |= PREFIX_GS;
11161           last_seg_prefix = i;
11162           active_seg_prefix = PREFIX_GS;
11163           break;
11164         case 0x66:
11165           prefixes |= PREFIX_DATA;
11166           last_data_prefix = i;
11167           break;
11168         case 0x67:
11169           prefixes |= PREFIX_ADDR;
11170           last_addr_prefix = i;
11171           break;
11172         case FWAIT_OPCODE:
11173           /* fwait is really an instruction.  If there are prefixes
11174              before the fwait, they belong to the fwait, *not* to the
11175              following instruction.  */
11176           fwait_prefix = i;
11177           if (prefixes || rex)
11178             {
11179               prefixes |= PREFIX_FWAIT;
11180               codep++;
11181               /* This ensures that the previous REX prefixes are noticed
11182                  as unused prefixes, as in the return case below.  */
11183               rex_used = rex;
11184               return 1;
11185             }
11186           prefixes = PREFIX_FWAIT;
11187           break;
11188         default:
11189           return 1;
11190         }
11191       /* Rex is ignored when followed by another prefix.  */
11192       if (rex)
11193         {
11194           rex_used = rex;
11195           return 1;
11196         }
11197       if (*codep != FWAIT_OPCODE)
11198         all_prefixes[i++] = *codep;
11199       rex = newrex;
11200       codep++;
11201       length++;
11202     }
11203   return 0;
11204 }
11205
11206 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11207    prefix byte.  */
11208
11209 static const char *
11210 prefix_name (int pref, int sizeflag)
11211 {
11212   static const char *rexes [16] =
11213     {
11214       "rex",            /* 0x40 */
11215       "rex.B",          /* 0x41 */
11216       "rex.X",          /* 0x42 */
11217       "rex.XB",         /* 0x43 */
11218       "rex.R",          /* 0x44 */
11219       "rex.RB",         /* 0x45 */
11220       "rex.RX",         /* 0x46 */
11221       "rex.RXB",        /* 0x47 */
11222       "rex.W",          /* 0x48 */
11223       "rex.WB",         /* 0x49 */
11224       "rex.WX",         /* 0x4a */
11225       "rex.WXB",        /* 0x4b */
11226       "rex.WR",         /* 0x4c */
11227       "rex.WRB",        /* 0x4d */
11228       "rex.WRX",        /* 0x4e */
11229       "rex.WRXB",       /* 0x4f */
11230     };
11231
11232   switch (pref)
11233     {
11234     /* REX prefixes family.  */
11235     case 0x40:
11236     case 0x41:
11237     case 0x42:
11238     case 0x43:
11239     case 0x44:
11240     case 0x45:
11241     case 0x46:
11242     case 0x47:
11243     case 0x48:
11244     case 0x49:
11245     case 0x4a:
11246     case 0x4b:
11247     case 0x4c:
11248     case 0x4d:
11249     case 0x4e:
11250     case 0x4f:
11251       return rexes [pref - 0x40];
11252     case 0xf3:
11253       return "repz";
11254     case 0xf2:
11255       return "repnz";
11256     case 0xf0:
11257       return "lock";
11258     case 0x2e:
11259       return "cs";
11260     case 0x36:
11261       return "ss";
11262     case 0x3e:
11263       return "ds";
11264     case 0x26:
11265       return "es";
11266     case 0x64:
11267       return "fs";
11268     case 0x65:
11269       return "gs";
11270     case 0x66:
11271       return (sizeflag & DFLAG) ? "data16" : "data32";
11272     case 0x67:
11273       if (address_mode == mode_64bit)
11274         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11275       else
11276         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11277     case FWAIT_OPCODE:
11278       return "fwait";
11279     case REP_PREFIX:
11280       return "rep";
11281     case XACQUIRE_PREFIX:
11282       return "xacquire";
11283     case XRELEASE_PREFIX:
11284       return "xrelease";
11285     case BND_PREFIX:
11286       return "bnd";
11287     case NOTRACK_PREFIX:
11288       return "notrack";
11289     default:
11290       return NULL;
11291     }
11292 }
11293
11294 static char op_out[MAX_OPERANDS][100];
11295 static int op_ad, op_index[MAX_OPERANDS];
11296 static int two_source_ops;
11297 static bfd_vma op_address[MAX_OPERANDS];
11298 static bfd_vma op_riprel[MAX_OPERANDS];
11299 static bfd_vma start_pc;
11300
11301 /*
11302  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11303  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11304  *   section of the "Virtual 8086 Mode" chapter.)
11305  * 'pc' should be the address of this instruction, it will
11306  *   be used to print the target address if this is a relative jump or call
11307  * The function returns the length of this instruction in bytes.
11308  */
11309
11310 static char intel_syntax;
11311 static char intel_mnemonic = !SYSV386_COMPAT;
11312 static char open_char;
11313 static char close_char;
11314 static char separator_char;
11315 static char scale_char;
11316
11317 enum x86_64_isa
11318 {
11319   amd64 = 0,
11320   intel64
11321 };
11322
11323 static enum x86_64_isa isa64;
11324
11325 /* Here for backwards compatibility.  When gdb stops using
11326    print_insn_i386_att and print_insn_i386_intel these functions can
11327    disappear, and print_insn_i386 be merged into print_insn.  */
11328 int
11329 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11330 {
11331   intel_syntax = 0;
11332
11333   return print_insn (pc, info);
11334 }
11335
11336 int
11337 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11338 {
11339   intel_syntax = 1;
11340
11341   return print_insn (pc, info);
11342 }
11343
11344 int
11345 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11346 {
11347   intel_syntax = -1;
11348
11349   return print_insn (pc, info);
11350 }
11351
11352 void
11353 print_i386_disassembler_options (FILE *stream)
11354 {
11355   fprintf (stream, _("\n\
11356 The following i386/x86-64 specific disassembler options are supported for use\n\
11357 with the -M switch (multiple options should be separated by commas):\n"));
11358
11359   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11360   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11361   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11362   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11363   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11364   fprintf (stream, _("  att-mnemonic\n"
11365                      "              Display instruction in AT&T mnemonic\n"));
11366   fprintf (stream, _("  intel-mnemonic\n"
11367                      "              Display instruction in Intel mnemonic\n"));
11368   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11369   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11370   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11371   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11372   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11373   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11374   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11375   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11376 }
11377
11378 /* Bad opcode.  */
11379 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11380
11381 /* Get a pointer to struct dis386 with a valid name.  */
11382
11383 static const struct dis386 *
11384 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11385 {
11386   int vindex, vex_table_index;
11387
11388   if (dp->name != NULL)
11389     return dp;
11390
11391   switch (dp->op[0].bytemode)
11392     {
11393     case USE_REG_TABLE:
11394       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11395       break;
11396
11397     case USE_MOD_TABLE:
11398       vindex = modrm.mod == 0x3 ? 1 : 0;
11399       dp = &mod_table[dp->op[1].bytemode][vindex];
11400       break;
11401
11402     case USE_RM_TABLE:
11403       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11404       break;
11405
11406     case USE_PREFIX_TABLE:
11407       if (need_vex)
11408         {
11409           /* The prefix in VEX is implicit.  */
11410           switch (vex.prefix)
11411             {
11412             case 0:
11413               vindex = 0;
11414               break;
11415             case REPE_PREFIX_OPCODE:
11416               vindex = 1;
11417               break;
11418             case DATA_PREFIX_OPCODE:
11419               vindex = 2;
11420               break;
11421             case REPNE_PREFIX_OPCODE:
11422               vindex = 3;
11423               break;
11424             default:
11425               abort ();
11426               break;
11427             }
11428         }
11429       else
11430         {
11431           int last_prefix = -1;
11432           int prefix = 0;
11433           vindex = 0;
11434           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11435              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11436              last one wins.  */
11437           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11438             {
11439               if (last_repz_prefix > last_repnz_prefix)
11440                 {
11441                   vindex = 1;
11442                   prefix = PREFIX_REPZ;
11443                   last_prefix = last_repz_prefix;
11444                 }
11445               else
11446                 {
11447                   vindex = 3;
11448                   prefix = PREFIX_REPNZ;
11449                   last_prefix = last_repnz_prefix;
11450                 }
11451
11452               /* Check if prefix should be ignored.  */
11453               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11454                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11455                    & prefix) != 0)
11456                 vindex = 0;
11457             }
11458
11459           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11460             {
11461               vindex = 2;
11462               prefix = PREFIX_DATA;
11463               last_prefix = last_data_prefix;
11464             }
11465
11466           if (vindex != 0)
11467             {
11468               used_prefixes |= prefix;
11469               all_prefixes[last_prefix] = 0;
11470             }
11471         }
11472       dp = &prefix_table[dp->op[1].bytemode][vindex];
11473       break;
11474
11475     case USE_X86_64_TABLE:
11476       vindex = address_mode == mode_64bit ? 1 : 0;
11477       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11478       break;
11479
11480     case USE_3BYTE_TABLE:
11481       FETCH_DATA (info, codep + 2);
11482       vindex = *codep++;
11483       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11484       end_codep = codep;
11485       modrm.mod = (*codep >> 6) & 3;
11486       modrm.reg = (*codep >> 3) & 7;
11487       modrm.rm = *codep & 7;
11488       break;
11489
11490     case USE_VEX_LEN_TABLE:
11491       if (!need_vex)
11492         abort ();
11493
11494       switch (vex.length)
11495         {
11496         case 128:
11497           vindex = 0;
11498           break;
11499         case 256:
11500           vindex = 1;
11501           break;
11502         default:
11503           abort ();
11504           break;
11505         }
11506
11507       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11508       break;
11509
11510     case USE_EVEX_LEN_TABLE:
11511       if (!vex.evex)
11512         abort ();
11513
11514       switch (vex.length)
11515         {
11516         case 128:
11517           vindex = 0;
11518           break;
11519         case 256:
11520           vindex = 1;
11521           break;
11522         case 512:
11523           vindex = 2;
11524           break;
11525         default:
11526           abort ();
11527           break;
11528         }
11529
11530       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11531       break;
11532
11533     case USE_XOP_8F_TABLE:
11534       FETCH_DATA (info, codep + 3);
11535       /* All bits in the REX prefix are ignored.  */
11536       rex_ignored = rex;
11537       rex = ~(*codep >> 5) & 0x7;
11538
11539       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11540       switch ((*codep & 0x1f))
11541         {
11542         default:
11543           dp = &bad_opcode;
11544           return dp;
11545         case 0x8:
11546           vex_table_index = XOP_08;
11547           break;
11548         case 0x9:
11549           vex_table_index = XOP_09;
11550           break;
11551         case 0xa:
11552           vex_table_index = XOP_0A;
11553           break;
11554         }
11555       codep++;
11556       vex.w = *codep & 0x80;
11557       if (vex.w && address_mode == mode_64bit)
11558         rex |= REX_W;
11559
11560       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11561       if (address_mode != mode_64bit)
11562         {
11563           /* In 16/32-bit mode REX_B is silently ignored.  */
11564           rex &= ~REX_B;
11565         }
11566
11567       vex.length = (*codep & 0x4) ? 256 : 128;
11568       switch ((*codep & 0x3))
11569         {
11570         case 0:
11571           break;
11572         case 1:
11573           vex.prefix = DATA_PREFIX_OPCODE;
11574           break;
11575         case 2:
11576           vex.prefix = REPE_PREFIX_OPCODE;
11577           break;
11578         case 3:
11579           vex.prefix = REPNE_PREFIX_OPCODE;
11580           break;
11581         }
11582       need_vex = 1;
11583       need_vex_reg = 1;
11584       codep++;
11585       vindex = *codep++;
11586       dp = &xop_table[vex_table_index][vindex];
11587
11588       end_codep = codep;
11589       FETCH_DATA (info, codep + 1);
11590       modrm.mod = (*codep >> 6) & 3;
11591       modrm.reg = (*codep >> 3) & 7;
11592       modrm.rm = *codep & 7;
11593       break;
11594
11595     case USE_VEX_C4_TABLE:
11596       /* VEX prefix.  */
11597       FETCH_DATA (info, codep + 3);
11598       /* All bits in the REX prefix are ignored.  */
11599       rex_ignored = rex;
11600       rex = ~(*codep >> 5) & 0x7;
11601       switch ((*codep & 0x1f))
11602         {
11603         default:
11604           dp = &bad_opcode;
11605           return dp;
11606         case 0x1:
11607           vex_table_index = VEX_0F;
11608           break;
11609         case 0x2:
11610           vex_table_index = VEX_0F38;
11611           break;
11612         case 0x3:
11613           vex_table_index = VEX_0F3A;
11614           break;
11615         }
11616       codep++;
11617       vex.w = *codep & 0x80;
11618       if (address_mode == mode_64bit)
11619         {
11620           if (vex.w)
11621             rex |= REX_W;
11622         }
11623       else
11624         {
11625           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11626              is ignored, other REX bits are 0 and the highest bit in
11627              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11628           rex = 0;
11629         }
11630       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11631       vex.length = (*codep & 0x4) ? 256 : 128;
11632       switch ((*codep & 0x3))
11633         {
11634         case 0:
11635           break;
11636         case 1:
11637           vex.prefix = DATA_PREFIX_OPCODE;
11638           break;
11639         case 2:
11640           vex.prefix = REPE_PREFIX_OPCODE;
11641           break;
11642         case 3:
11643           vex.prefix = REPNE_PREFIX_OPCODE;
11644           break;
11645         }
11646       need_vex = 1;
11647       need_vex_reg = 1;
11648       codep++;
11649       vindex = *codep++;
11650       dp = &vex_table[vex_table_index][vindex];
11651       end_codep = codep;
11652       /* There is no MODRM byte for VEX0F 77.  */
11653       if (vex_table_index != VEX_0F || vindex != 0x77)
11654         {
11655           FETCH_DATA (info, codep + 1);
11656           modrm.mod = (*codep >> 6) & 3;
11657           modrm.reg = (*codep >> 3) & 7;
11658           modrm.rm = *codep & 7;
11659         }
11660       break;
11661
11662     case USE_VEX_C5_TABLE:
11663       /* VEX prefix.  */
11664       FETCH_DATA (info, codep + 2);
11665       /* All bits in the REX prefix are ignored.  */
11666       rex_ignored = rex;
11667       rex = (*codep & 0x80) ? 0 : REX_R;
11668
11669       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11670          VEX.vvvv is 1.  */
11671       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11672       vex.length = (*codep & 0x4) ? 256 : 128;
11673       switch ((*codep & 0x3))
11674         {
11675         case 0:
11676           break;
11677         case 1:
11678           vex.prefix = DATA_PREFIX_OPCODE;
11679           break;
11680         case 2:
11681           vex.prefix = REPE_PREFIX_OPCODE;
11682           break;
11683         case 3:
11684           vex.prefix = REPNE_PREFIX_OPCODE;
11685           break;
11686         }
11687       need_vex = 1;
11688       need_vex_reg = 1;
11689       codep++;
11690       vindex = *codep++;
11691       dp = &vex_table[dp->op[1].bytemode][vindex];
11692       end_codep = codep;
11693       /* There is no MODRM byte for VEX 77.  */
11694       if (vindex != 0x77)
11695         {
11696           FETCH_DATA (info, codep + 1);
11697           modrm.mod = (*codep >> 6) & 3;
11698           modrm.reg = (*codep >> 3) & 7;
11699           modrm.rm = *codep & 7;
11700         }
11701       break;
11702
11703     case USE_VEX_W_TABLE:
11704       if (!need_vex)
11705         abort ();
11706
11707       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11708       break;
11709
11710     case USE_EVEX_TABLE:
11711       two_source_ops = 0;
11712       /* EVEX prefix.  */
11713       vex.evex = 1;
11714       FETCH_DATA (info, codep + 4);
11715       /* All bits in the REX prefix are ignored.  */
11716       rex_ignored = rex;
11717       /* The first byte after 0x62.  */
11718       rex = ~(*codep >> 5) & 0x7;
11719       vex.r = *codep & 0x10;
11720       switch ((*codep & 0xf))
11721         {
11722         default:
11723           return &bad_opcode;
11724         case 0x1:
11725           vex_table_index = EVEX_0F;
11726           break;
11727         case 0x2:
11728           vex_table_index = EVEX_0F38;
11729           break;
11730         case 0x3:
11731           vex_table_index = EVEX_0F3A;
11732           break;
11733         }
11734
11735       /* The second byte after 0x62.  */
11736       codep++;
11737       vex.w = *codep & 0x80;
11738       if (vex.w && address_mode == mode_64bit)
11739         rex |= REX_W;
11740
11741       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11742
11743       /* The U bit.  */
11744       if (!(*codep & 0x4))
11745         return &bad_opcode;
11746
11747       switch ((*codep & 0x3))
11748         {
11749         case 0:
11750           break;
11751         case 1:
11752           vex.prefix = DATA_PREFIX_OPCODE;
11753           break;
11754         case 2:
11755           vex.prefix = REPE_PREFIX_OPCODE;
11756           break;
11757         case 3:
11758           vex.prefix = REPNE_PREFIX_OPCODE;
11759           break;
11760         }
11761
11762       /* The third byte after 0x62.  */
11763       codep++;
11764
11765       /* Remember the static rounding bits.  */
11766       vex.ll = (*codep >> 5) & 3;
11767       vex.b = (*codep & 0x10) != 0;
11768
11769       vex.v = *codep & 0x8;
11770       vex.mask_register_specifier = *codep & 0x7;
11771       vex.zeroing = *codep & 0x80;
11772
11773       if (address_mode != mode_64bit)
11774         {
11775           /* In 16/32-bit mode silently ignore following bits.  */
11776           rex &= ~REX_B;
11777           vex.r = 1;
11778           vex.v = 1;
11779         }
11780
11781       need_vex = 1;
11782       need_vex_reg = 1;
11783       codep++;
11784       vindex = *codep++;
11785       dp = &evex_table[vex_table_index][vindex];
11786       end_codep = codep;
11787       FETCH_DATA (info, codep + 1);
11788       modrm.mod = (*codep >> 6) & 3;
11789       modrm.reg = (*codep >> 3) & 7;
11790       modrm.rm = *codep & 7;
11791
11792       /* Set vector length.  */
11793       if (modrm.mod == 3 && vex.b)
11794         vex.length = 512;
11795       else
11796         {
11797           switch (vex.ll)
11798             {
11799             case 0x0:
11800               vex.length = 128;
11801               break;
11802             case 0x1:
11803               vex.length = 256;
11804               break;
11805             case 0x2:
11806               vex.length = 512;
11807               break;
11808             default:
11809               return &bad_opcode;
11810             }
11811         }
11812       break;
11813
11814     case 0:
11815       dp = &bad_opcode;
11816       break;
11817
11818     default:
11819       abort ();
11820     }
11821
11822   if (dp->name != NULL)
11823     return dp;
11824   else
11825     return get_valid_dis386 (dp, info);
11826 }
11827
11828 static void
11829 get_sib (disassemble_info *info, int sizeflag)
11830 {
11831   /* If modrm.mod == 3, operand must be register.  */
11832   if (need_modrm
11833       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11834       && modrm.mod != 3
11835       && modrm.rm == 4)
11836     {
11837       FETCH_DATA (info, codep + 2);
11838       sib.index = (codep [1] >> 3) & 7;
11839       sib.scale = (codep [1] >> 6) & 3;
11840       sib.base = codep [1] & 7;
11841     }
11842 }
11843
11844 static int
11845 print_insn (bfd_vma pc, disassemble_info *info)
11846 {
11847   const struct dis386 *dp;
11848   int i;
11849   char *op_txt[MAX_OPERANDS];
11850   int needcomma;
11851   int sizeflag, orig_sizeflag;
11852   const char *p;
11853   struct dis_private priv;
11854   int prefix_length;
11855
11856   priv.orig_sizeflag = AFLAG | DFLAG;
11857   if ((info->mach & bfd_mach_i386_i386) != 0)
11858     address_mode = mode_32bit;
11859   else if (info->mach == bfd_mach_i386_i8086)
11860     {
11861       address_mode = mode_16bit;
11862       priv.orig_sizeflag = 0;
11863     }
11864   else
11865     address_mode = mode_64bit;
11866
11867   if (intel_syntax == (char) -1)
11868     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11869
11870   for (p = info->disassembler_options; p != NULL; )
11871     {
11872       if (CONST_STRNEQ (p, "amd64"))
11873         isa64 = amd64;
11874       else if (CONST_STRNEQ (p, "intel64"))
11875         isa64 = intel64;
11876       else if (CONST_STRNEQ (p, "x86-64"))
11877         {
11878           address_mode = mode_64bit;
11879           priv.orig_sizeflag = AFLAG | DFLAG;
11880         }
11881       else if (CONST_STRNEQ (p, "i386"))
11882         {
11883           address_mode = mode_32bit;
11884           priv.orig_sizeflag = AFLAG | DFLAG;
11885         }
11886       else if (CONST_STRNEQ (p, "i8086"))
11887         {
11888           address_mode = mode_16bit;
11889           priv.orig_sizeflag = 0;
11890         }
11891       else if (CONST_STRNEQ (p, "intel"))
11892         {
11893           intel_syntax = 1;
11894           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11895             intel_mnemonic = 1;
11896         }
11897       else if (CONST_STRNEQ (p, "att"))
11898         {
11899           intel_syntax = 0;
11900           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11901             intel_mnemonic = 0;
11902         }
11903       else if (CONST_STRNEQ (p, "addr"))
11904         {
11905           if (address_mode == mode_64bit)
11906             {
11907               if (p[4] == '3' && p[5] == '2')
11908                 priv.orig_sizeflag &= ~AFLAG;
11909               else if (p[4] == '6' && p[5] == '4')
11910                 priv.orig_sizeflag |= AFLAG;
11911             }
11912           else
11913             {
11914               if (p[4] == '1' && p[5] == '6')
11915                 priv.orig_sizeflag &= ~AFLAG;
11916               else if (p[4] == '3' && p[5] == '2')
11917                 priv.orig_sizeflag |= AFLAG;
11918             }
11919         }
11920       else if (CONST_STRNEQ (p, "data"))
11921         {
11922           if (p[4] == '1' && p[5] == '6')
11923             priv.orig_sizeflag &= ~DFLAG;
11924           else if (p[4] == '3' && p[5] == '2')
11925             priv.orig_sizeflag |= DFLAG;
11926         }
11927       else if (CONST_STRNEQ (p, "suffix"))
11928         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11929
11930       p = strchr (p, ',');
11931       if (p != NULL)
11932         p++;
11933     }
11934
11935   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11936     {
11937       (*info->fprintf_func) (info->stream,
11938                              _("64-bit address is disabled"));
11939       return -1;
11940     }
11941
11942   if (intel_syntax)
11943     {
11944       names64 = intel_names64;
11945       names32 = intel_names32;
11946       names16 = intel_names16;
11947       names8 = intel_names8;
11948       names8rex = intel_names8rex;
11949       names_seg = intel_names_seg;
11950       names_mm = intel_names_mm;
11951       names_bnd = intel_names_bnd;
11952       names_xmm = intel_names_xmm;
11953       names_ymm = intel_names_ymm;
11954       names_zmm = intel_names_zmm;
11955       index64 = intel_index64;
11956       index32 = intel_index32;
11957       names_mask = intel_names_mask;
11958       index16 = intel_index16;
11959       open_char = '[';
11960       close_char = ']';
11961       separator_char = '+';
11962       scale_char = '*';
11963     }
11964   else
11965     {
11966       names64 = att_names64;
11967       names32 = att_names32;
11968       names16 = att_names16;
11969       names8 = att_names8;
11970       names8rex = att_names8rex;
11971       names_seg = att_names_seg;
11972       names_mm = att_names_mm;
11973       names_bnd = att_names_bnd;
11974       names_xmm = att_names_xmm;
11975       names_ymm = att_names_ymm;
11976       names_zmm = att_names_zmm;
11977       index64 = att_index64;
11978       index32 = att_index32;
11979       names_mask = att_names_mask;
11980       index16 = att_index16;
11981       open_char = '(';
11982       close_char =  ')';
11983       separator_char = ',';
11984       scale_char = ',';
11985     }
11986
11987   /* The output looks better if we put 7 bytes on a line, since that
11988      puts most long word instructions on a single line.  Use 8 bytes
11989      for Intel L1OM.  */
11990   if ((info->mach & bfd_mach_l1om) != 0)
11991     info->bytes_per_line = 8;
11992   else
11993     info->bytes_per_line = 7;
11994
11995   info->private_data = &priv;
11996   priv.max_fetched = priv.the_buffer;
11997   priv.insn_start = pc;
11998
11999   obuf[0] = 0;
12000   for (i = 0; i < MAX_OPERANDS; ++i)
12001     {
12002       op_out[i][0] = 0;
12003       op_index[i] = -1;
12004     }
12005
12006   the_info = info;
12007   start_pc = pc;
12008   start_codep = priv.the_buffer;
12009   codep = priv.the_buffer;
12010
12011   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12012     {
12013       const char *name;
12014
12015       /* Getting here means we tried for data but didn't get it.  That
12016          means we have an incomplete instruction of some sort.  Just
12017          print the first byte as a prefix or a .byte pseudo-op.  */
12018       if (codep > priv.the_buffer)
12019         {
12020           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12021           if (name != NULL)
12022             (*info->fprintf_func) (info->stream, "%s", name);
12023           else
12024             {
12025               /* Just print the first byte as a .byte instruction.  */
12026               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12027                                      (unsigned int) priv.the_buffer[0]);
12028             }
12029
12030           return 1;
12031         }
12032
12033       return -1;
12034     }
12035
12036   obufp = obuf;
12037   sizeflag = priv.orig_sizeflag;
12038
12039   if (!ckprefix () || rex_used)
12040     {
12041       /* Too many prefixes or unused REX prefixes.  */
12042       for (i = 0;
12043            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12044            i++)
12045         (*info->fprintf_func) (info->stream, "%s%s",
12046                                i == 0 ? "" : " ",
12047                                prefix_name (all_prefixes[i], sizeflag));
12048       return i;
12049     }
12050
12051   insn_codep = codep;
12052
12053   FETCH_DATA (info, codep + 1);
12054   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12055
12056   if (((prefixes & PREFIX_FWAIT)
12057        && ((*codep < 0xd8) || (*codep > 0xdf))))
12058     {
12059       /* Handle prefixes before fwait.  */
12060       for (i = 0; i < fwait_prefix && all_prefixes[i];
12061            i++)
12062         (*info->fprintf_func) (info->stream, "%s ",
12063                                prefix_name (all_prefixes[i], sizeflag));
12064       (*info->fprintf_func) (info->stream, "fwait");
12065       return i + 1;
12066     }
12067
12068   if (*codep == 0x0f)
12069     {
12070       unsigned char threebyte;
12071
12072       codep++;
12073       FETCH_DATA (info, codep + 1);
12074       threebyte = *codep;
12075       dp = &dis386_twobyte[threebyte];
12076       need_modrm = twobyte_has_modrm[*codep];
12077       codep++;
12078     }
12079   else
12080     {
12081       dp = &dis386[*codep];
12082       need_modrm = onebyte_has_modrm[*codep];
12083       codep++;
12084     }
12085
12086   /* Save sizeflag for printing the extra prefixes later before updating
12087      it for mnemonic and operand processing.  The prefix names depend
12088      only on the address mode.  */
12089   orig_sizeflag = sizeflag;
12090   if (prefixes & PREFIX_ADDR)
12091     sizeflag ^= AFLAG;
12092   if ((prefixes & PREFIX_DATA))
12093     sizeflag ^= DFLAG;
12094
12095   end_codep = codep;
12096   if (need_modrm)
12097     {
12098       FETCH_DATA (info, codep + 1);
12099       modrm.mod = (*codep >> 6) & 3;
12100       modrm.reg = (*codep >> 3) & 7;
12101       modrm.rm = *codep & 7;
12102     }
12103
12104   need_vex = 0;
12105   need_vex_reg = 0;
12106   vex_w_done = 0;
12107   memset (&vex, 0, sizeof (vex));
12108
12109   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12110     {
12111       get_sib (info, sizeflag);
12112       dofloat (sizeflag);
12113     }
12114   else
12115     {
12116       dp = get_valid_dis386 (dp, info);
12117       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12118         {
12119           get_sib (info, sizeflag);
12120           for (i = 0; i < MAX_OPERANDS; ++i)
12121             {
12122               obufp = op_out[i];
12123               op_ad = MAX_OPERANDS - 1 - i;
12124               if (dp->op[i].rtn)
12125                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12126               /* For EVEX instruction after the last operand masking
12127                  should be printed.  */
12128               if (i == 0 && vex.evex)
12129                 {
12130                   /* Don't print {%k0}.  */
12131                   if (vex.mask_register_specifier)
12132                     {
12133                       oappend ("{");
12134                       oappend (names_mask[vex.mask_register_specifier]);
12135                       oappend ("}");
12136                     }
12137                   if (vex.zeroing)
12138                     oappend ("{z}");
12139                 }
12140             }
12141         }
12142     }
12143
12144   /* Check if the REX prefix is used.  */
12145   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12146     all_prefixes[last_rex_prefix] = 0;
12147
12148   /* Check if the SEG prefix is used.  */
12149   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12150                    | PREFIX_FS | PREFIX_GS)) != 0
12151       && (used_prefixes & active_seg_prefix) != 0)
12152     all_prefixes[last_seg_prefix] = 0;
12153
12154   /* Check if the ADDR prefix is used.  */
12155   if ((prefixes & PREFIX_ADDR) != 0
12156       && (used_prefixes & PREFIX_ADDR) != 0)
12157     all_prefixes[last_addr_prefix] = 0;
12158
12159   /* Check if the DATA prefix is used.  */
12160   if ((prefixes & PREFIX_DATA) != 0
12161       && (used_prefixes & PREFIX_DATA) != 0)
12162     all_prefixes[last_data_prefix] = 0;
12163
12164   /* Print the extra prefixes.  */
12165   prefix_length = 0;
12166   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12167     if (all_prefixes[i])
12168       {
12169         const char *name;
12170         name = prefix_name (all_prefixes[i], orig_sizeflag);
12171         if (name == NULL)
12172           abort ();
12173         prefix_length += strlen (name) + 1;
12174         (*info->fprintf_func) (info->stream, "%s ", name);
12175       }
12176
12177   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12178      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12179      used by putop and MMX/SSE operand and may be overriden by the
12180      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12181      separately.  */
12182   if (dp->prefix_requirement == PREFIX_OPCODE
12183       && dp != &bad_opcode
12184       && (((prefixes
12185             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12186            && (used_prefixes
12187                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12188           || ((((prefixes
12189                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12190                 == PREFIX_DATA)
12191                && (used_prefixes & PREFIX_DATA) == 0))))
12192     {
12193       (*info->fprintf_func) (info->stream, "(bad)");
12194       return end_codep - priv.the_buffer;
12195     }
12196
12197   /* Check maximum code length.  */
12198   if ((codep - start_codep) > MAX_CODE_LENGTH)
12199     {
12200       (*info->fprintf_func) (info->stream, "(bad)");
12201       return MAX_CODE_LENGTH;
12202     }
12203
12204   obufp = mnemonicendp;
12205   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12206     oappend (" ");
12207   oappend (" ");
12208   (*info->fprintf_func) (info->stream, "%s", obuf);
12209
12210   /* The enter and bound instructions are printed with operands in the same
12211      order as the intel book; everything else is printed in reverse order.  */
12212   if (intel_syntax || two_source_ops)
12213     {
12214       bfd_vma riprel;
12215
12216       for (i = 0; i < MAX_OPERANDS; ++i)
12217         op_txt[i] = op_out[i];
12218
12219       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12220           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12221         {
12222           op_txt[2] = op_out[3];
12223           op_txt[3] = op_out[2];
12224         }
12225
12226       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12227         {
12228           op_ad = op_index[i];
12229           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12230           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12231           riprel = op_riprel[i];
12232           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12233           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12234         }
12235     }
12236   else
12237     {
12238       for (i = 0; i < MAX_OPERANDS; ++i)
12239         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12240     }
12241
12242   needcomma = 0;
12243   for (i = 0; i < MAX_OPERANDS; ++i)
12244     if (*op_txt[i])
12245       {
12246         if (needcomma)
12247           (*info->fprintf_func) (info->stream, ",");
12248         if (op_index[i] != -1 && !op_riprel[i])
12249           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12250         else
12251           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12252         needcomma = 1;
12253       }
12254
12255   for (i = 0; i < MAX_OPERANDS; i++)
12256     if (op_index[i] != -1 && op_riprel[i])
12257       {
12258         (*info->fprintf_func) (info->stream, "        # ");
12259         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12260                                                 + op_address[op_index[i]]), info);
12261         break;
12262       }
12263   return codep - priv.the_buffer;
12264 }
12265
12266 static const char *float_mem[] = {
12267   /* d8 */
12268   "fadd{s|}",
12269   "fmul{s|}",
12270   "fcom{s|}",
12271   "fcomp{s|}",
12272   "fsub{s|}",
12273   "fsubr{s|}",
12274   "fdiv{s|}",
12275   "fdivr{s|}",
12276   /* d9 */
12277   "fld{s|}",
12278   "(bad)",
12279   "fst{s|}",
12280   "fstp{s|}",
12281   "fldenvIC",
12282   "fldcw",
12283   "fNstenvIC",
12284   "fNstcw",
12285   /* da */
12286   "fiadd{l|}",
12287   "fimul{l|}",
12288   "ficom{l|}",
12289   "ficomp{l|}",
12290   "fisub{l|}",
12291   "fisubr{l|}",
12292   "fidiv{l|}",
12293   "fidivr{l|}",
12294   /* db */
12295   "fild{l|}",
12296   "fisttp{l|}",
12297   "fist{l|}",
12298   "fistp{l|}",
12299   "(bad)",
12300   "fld{t||t|}",
12301   "(bad)",
12302   "fstp{t||t|}",
12303   /* dc */
12304   "fadd{l|}",
12305   "fmul{l|}",
12306   "fcom{l|}",
12307   "fcomp{l|}",
12308   "fsub{l|}",
12309   "fsubr{l|}",
12310   "fdiv{l|}",
12311   "fdivr{l|}",
12312   /* dd */
12313   "fld{l|}",
12314   "fisttp{ll|}",
12315   "fst{l||}",
12316   "fstp{l|}",
12317   "frstorIC",
12318   "(bad)",
12319   "fNsaveIC",
12320   "fNstsw",
12321   /* de */
12322   "fiadd{s|}",
12323   "fimul{s|}",
12324   "ficom{s|}",
12325   "ficomp{s|}",
12326   "fisub{s|}",
12327   "fisubr{s|}",
12328   "fidiv{s|}",
12329   "fidivr{s|}",
12330   /* df */
12331   "fild{s|}",
12332   "fisttp{s|}",
12333   "fist{s|}",
12334   "fistp{s|}",
12335   "fbld",
12336   "fild{ll|}",
12337   "fbstp",
12338   "fistp{ll|}",
12339 };
12340
12341 static const unsigned char float_mem_mode[] = {
12342   /* d8 */
12343   d_mode,
12344   d_mode,
12345   d_mode,
12346   d_mode,
12347   d_mode,
12348   d_mode,
12349   d_mode,
12350   d_mode,
12351   /* d9 */
12352   d_mode,
12353   0,
12354   d_mode,
12355   d_mode,
12356   0,
12357   w_mode,
12358   0,
12359   w_mode,
12360   /* da */
12361   d_mode,
12362   d_mode,
12363   d_mode,
12364   d_mode,
12365   d_mode,
12366   d_mode,
12367   d_mode,
12368   d_mode,
12369   /* db */
12370   d_mode,
12371   d_mode,
12372   d_mode,
12373   d_mode,
12374   0,
12375   t_mode,
12376   0,
12377   t_mode,
12378   /* dc */
12379   q_mode,
12380   q_mode,
12381   q_mode,
12382   q_mode,
12383   q_mode,
12384   q_mode,
12385   q_mode,
12386   q_mode,
12387   /* dd */
12388   q_mode,
12389   q_mode,
12390   q_mode,
12391   q_mode,
12392   0,
12393   0,
12394   0,
12395   w_mode,
12396   /* de */
12397   w_mode,
12398   w_mode,
12399   w_mode,
12400   w_mode,
12401   w_mode,
12402   w_mode,
12403   w_mode,
12404   w_mode,
12405   /* df */
12406   w_mode,
12407   w_mode,
12408   w_mode,
12409   w_mode,
12410   t_mode,
12411   q_mode,
12412   t_mode,
12413   q_mode
12414 };
12415
12416 #define ST { OP_ST, 0 }
12417 #define STi { OP_STi, 0 }
12418
12419 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12420 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12421 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12422 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12423 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12424 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12425 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12426 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12427 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12428
12429 static const struct dis386 float_reg[][8] = {
12430   /* d8 */
12431   {
12432     { "fadd",   { ST, STi }, 0 },
12433     { "fmul",   { ST, STi }, 0 },
12434     { "fcom",   { STi }, 0 },
12435     { "fcomp",  { STi }, 0 },
12436     { "fsub",   { ST, STi }, 0 },
12437     { "fsubr",  { ST, STi }, 0 },
12438     { "fdiv",   { ST, STi }, 0 },
12439     { "fdivr",  { ST, STi }, 0 },
12440   },
12441   /* d9 */
12442   {
12443     { "fld",    { STi }, 0 },
12444     { "fxch",   { STi }, 0 },
12445     { FGRPd9_2 },
12446     { Bad_Opcode },
12447     { FGRPd9_4 },
12448     { FGRPd9_5 },
12449     { FGRPd9_6 },
12450     { FGRPd9_7 },
12451   },
12452   /* da */
12453   {
12454     { "fcmovb", { ST, STi }, 0 },
12455     { "fcmove", { ST, STi }, 0 },
12456     { "fcmovbe",{ ST, STi }, 0 },
12457     { "fcmovu", { ST, STi }, 0 },
12458     { Bad_Opcode },
12459     { FGRPda_5 },
12460     { Bad_Opcode },
12461     { Bad_Opcode },
12462   },
12463   /* db */
12464   {
12465     { "fcmovnb",{ ST, STi }, 0 },
12466     { "fcmovne",{ ST, STi }, 0 },
12467     { "fcmovnbe",{ ST, STi }, 0 },
12468     { "fcmovnu",{ ST, STi }, 0 },
12469     { FGRPdb_4 },
12470     { "fucomi", { ST, STi }, 0 },
12471     { "fcomi",  { ST, STi }, 0 },
12472     { Bad_Opcode },
12473   },
12474   /* dc */
12475   {
12476     { "fadd",   { STi, ST }, 0 },
12477     { "fmul",   { STi, ST }, 0 },
12478     { Bad_Opcode },
12479     { Bad_Opcode },
12480     { "fsub{!M|r}",     { STi, ST }, 0 },
12481     { "fsub{M|}",       { STi, ST }, 0 },
12482     { "fdiv{!M|r}",     { STi, ST }, 0 },
12483     { "fdiv{M|}",       { STi, ST }, 0 },
12484   },
12485   /* dd */
12486   {
12487     { "ffree",  { STi }, 0 },
12488     { Bad_Opcode },
12489     { "fst",    { STi }, 0 },
12490     { "fstp",   { STi }, 0 },
12491     { "fucom",  { STi }, 0 },
12492     { "fucomp", { STi }, 0 },
12493     { Bad_Opcode },
12494     { Bad_Opcode },
12495   },
12496   /* de */
12497   {
12498     { "faddp",  { STi, ST }, 0 },
12499     { "fmulp",  { STi, ST }, 0 },
12500     { Bad_Opcode },
12501     { FGRPde_3 },
12502     { "fsub{!M|r}p",    { STi, ST }, 0 },
12503     { "fsub{M|}p",      { STi, ST }, 0 },
12504     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12505     { "fdiv{M|}p",      { STi, ST }, 0 },
12506   },
12507   /* df */
12508   {
12509     { "ffreep", { STi }, 0 },
12510     { Bad_Opcode },
12511     { Bad_Opcode },
12512     { Bad_Opcode },
12513     { FGRPdf_4 },
12514     { "fucomip", { ST, STi }, 0 },
12515     { "fcomip", { ST, STi }, 0 },
12516     { Bad_Opcode },
12517   },
12518 };
12519
12520 static char *fgrps[][8] = {
12521   /* Bad opcode 0 */
12522   {
12523     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12524   },
12525
12526   /* d9_2  1 */
12527   {
12528     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12529   },
12530
12531   /* d9_4  2 */
12532   {
12533     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12534   },
12535
12536   /* d9_5  3 */
12537   {
12538     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12539   },
12540
12541   /* d9_6  4 */
12542   {
12543     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12544   },
12545
12546   /* d9_7  5 */
12547   {
12548     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12549   },
12550
12551   /* da_5  6 */
12552   {
12553     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12554   },
12555
12556   /* db_4  7 */
12557   {
12558     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12559     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12560   },
12561
12562   /* de_3  8 */
12563   {
12564     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12565   },
12566
12567   /* df_4  9 */
12568   {
12569     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12570   },
12571 };
12572
12573 static void
12574 swap_operand (void)
12575 {
12576   mnemonicendp[0] = '.';
12577   mnemonicendp[1] = 's';
12578   mnemonicendp += 2;
12579 }
12580
12581 static void
12582 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12583                int sizeflag ATTRIBUTE_UNUSED)
12584 {
12585   /* Skip mod/rm byte.  */
12586   MODRM_CHECK;
12587   codep++;
12588 }
12589
12590 static void
12591 dofloat (int sizeflag)
12592 {
12593   const struct dis386 *dp;
12594   unsigned char floatop;
12595
12596   floatop = codep[-1];
12597
12598   if (modrm.mod != 3)
12599     {
12600       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12601
12602       putop (float_mem[fp_indx], sizeflag);
12603       obufp = op_out[0];
12604       op_ad = 2;
12605       OP_E (float_mem_mode[fp_indx], sizeflag);
12606       return;
12607     }
12608   /* Skip mod/rm byte.  */
12609   MODRM_CHECK;
12610   codep++;
12611
12612   dp = &float_reg[floatop - 0xd8][modrm.reg];
12613   if (dp->name == NULL)
12614     {
12615       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12616
12617       /* Instruction fnstsw is only one with strange arg.  */
12618       if (floatop == 0xdf && codep[-1] == 0xe0)
12619         strcpy (op_out[0], names16[0]);
12620     }
12621   else
12622     {
12623       putop (dp->name, sizeflag);
12624
12625       obufp = op_out[0];
12626       op_ad = 2;
12627       if (dp->op[0].rtn)
12628         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12629
12630       obufp = op_out[1];
12631       op_ad = 1;
12632       if (dp->op[1].rtn)
12633         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12634     }
12635 }
12636
12637 /* Like oappend (below), but S is a string starting with '%'.
12638    In Intel syntax, the '%' is elided.  */
12639 static void
12640 oappend_maybe_intel (const char *s)
12641 {
12642   oappend (s + intel_syntax);
12643 }
12644
12645 static void
12646 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12647 {
12648   oappend_maybe_intel ("%st");
12649 }
12650
12651 static void
12652 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12653 {
12654   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12655   oappend_maybe_intel (scratchbuf);
12656 }
12657
12658 /* Capital letters in template are macros.  */
12659 static int
12660 putop (const char *in_template, int sizeflag)
12661 {
12662   const char *p;
12663   int alt = 0;
12664   int cond = 1;
12665   unsigned int l = 0, len = 1;
12666   char last[4];
12667
12668 #define SAVE_LAST(c)                    \
12669   if (l < len && l < sizeof (last))     \
12670     last[l++] = c;                      \
12671   else                                  \
12672     abort ();
12673
12674   for (p = in_template; *p; p++)
12675     {
12676       switch (*p)
12677         {
12678         default:
12679           *obufp++ = *p;
12680           break;
12681         case '%':
12682           len++;
12683           break;
12684         case '!':
12685           cond = 0;
12686           break;
12687         case '{':
12688           if (intel_syntax)
12689             {
12690               while (*++p != '|')
12691                 if (*p == '}' || *p == '\0')
12692                   abort ();
12693             }
12694           /* Fall through.  */
12695         case 'I':
12696           alt = 1;
12697           continue;
12698         case '|':
12699           while (*++p != '}')
12700             {
12701               if (*p == '\0')
12702                 abort ();
12703             }
12704           break;
12705         case '}':
12706           break;
12707         case 'A':
12708           if (intel_syntax)
12709             break;
12710           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12711             *obufp++ = 'b';
12712           break;
12713         case 'B':
12714           if (l == 0 && len == 1)
12715             {
12716 case_B:
12717               if (intel_syntax)
12718                 break;
12719               if (sizeflag & SUFFIX_ALWAYS)
12720                 *obufp++ = 'b';
12721             }
12722           else
12723             {
12724               if (l != 1
12725                   || len != 2
12726                   || last[0] != 'L')
12727                 {
12728                   SAVE_LAST (*p);
12729                   break;
12730                 }
12731
12732               if (address_mode == mode_64bit
12733                   && !(prefixes & PREFIX_ADDR))
12734                 {
12735                   *obufp++ = 'a';
12736                   *obufp++ = 'b';
12737                   *obufp++ = 's';
12738                 }
12739
12740               goto case_B;
12741             }
12742           break;
12743         case 'C':
12744           if (intel_syntax && !alt)
12745             break;
12746           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12747             {
12748               if (sizeflag & DFLAG)
12749                 *obufp++ = intel_syntax ? 'd' : 'l';
12750               else
12751                 *obufp++ = intel_syntax ? 'w' : 's';
12752               used_prefixes |= (prefixes & PREFIX_DATA);
12753             }
12754           break;
12755         case 'D':
12756           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12757             break;
12758           USED_REX (REX_W);
12759           if (modrm.mod == 3)
12760             {
12761               if (rex & REX_W)
12762                 *obufp++ = 'q';
12763               else
12764                 {
12765                   if (sizeflag & DFLAG)
12766                     *obufp++ = intel_syntax ? 'd' : 'l';
12767                   else
12768                     *obufp++ = 'w';
12769                   used_prefixes |= (prefixes & PREFIX_DATA);
12770                 }
12771             }
12772           else
12773             *obufp++ = 'w';
12774           break;
12775         case 'E':               /* For jcxz/jecxz */
12776           if (address_mode == mode_64bit)
12777             {
12778               if (sizeflag & AFLAG)
12779                 *obufp++ = 'r';
12780               else
12781                 *obufp++ = 'e';
12782             }
12783           else
12784             if (sizeflag & AFLAG)
12785               *obufp++ = 'e';
12786           used_prefixes |= (prefixes & PREFIX_ADDR);
12787           break;
12788         case 'F':
12789           if (intel_syntax)
12790             break;
12791           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12792             {
12793               if (sizeflag & AFLAG)
12794                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12795               else
12796                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12797               used_prefixes |= (prefixes & PREFIX_ADDR);
12798             }
12799           break;
12800         case 'G':
12801           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12802             break;
12803           if ((rex & REX_W) || (sizeflag & DFLAG))
12804             *obufp++ = 'l';
12805           else
12806             *obufp++ = 'w';
12807           if (!(rex & REX_W))
12808             used_prefixes |= (prefixes & PREFIX_DATA);
12809           break;
12810         case 'H':
12811           if (intel_syntax)
12812             break;
12813           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12814               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12815             {
12816               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12817               *obufp++ = ',';
12818               *obufp++ = 'p';
12819               if (prefixes & PREFIX_DS)
12820                 *obufp++ = 't';
12821               else
12822                 *obufp++ = 'n';
12823             }
12824           break;
12825         case 'J':
12826           if (intel_syntax)
12827             break;
12828           *obufp++ = 'l';
12829           break;
12830         case 'K':
12831           USED_REX (REX_W);
12832           if (rex & REX_W)
12833             *obufp++ = 'q';
12834           else
12835             *obufp++ = 'd';
12836           break;
12837         case 'Z':
12838           if (l != 0 || len != 1)
12839             {
12840               if (l != 1 || len != 2 || last[0] != 'X')
12841                 {
12842                   SAVE_LAST (*p);
12843                   break;
12844                 }
12845               if (!need_vex || !vex.evex)
12846                 abort ();
12847               if (intel_syntax
12848                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12849                 break;
12850               switch (vex.length)
12851                 {
12852                 case 128:
12853                   *obufp++ = 'x';
12854                   break;
12855                 case 256:
12856                   *obufp++ = 'y';
12857                   break;
12858                 case 512:
12859                   *obufp++ = 'z';
12860                   break;
12861                 default:
12862                   abort ();
12863                 }
12864               break;
12865             }
12866           if (intel_syntax)
12867             break;
12868           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12869             {
12870               *obufp++ = 'q';
12871               break;
12872             }
12873           /* Fall through.  */
12874           goto case_L;
12875         case 'L':
12876           if (l != 0 || len != 1)
12877             {
12878               SAVE_LAST (*p);
12879               break;
12880             }
12881 case_L:
12882           if (intel_syntax)
12883             break;
12884           if (sizeflag & SUFFIX_ALWAYS)
12885             *obufp++ = 'l';
12886           break;
12887         case 'M':
12888           if (intel_mnemonic != cond)
12889             *obufp++ = 'r';
12890           break;
12891         case 'N':
12892           if ((prefixes & PREFIX_FWAIT) == 0)
12893             *obufp++ = 'n';
12894           else
12895             used_prefixes |= PREFIX_FWAIT;
12896           break;
12897         case 'O':
12898           USED_REX (REX_W);
12899           if (rex & REX_W)
12900             *obufp++ = 'o';
12901           else if (intel_syntax && (sizeflag & DFLAG))
12902             *obufp++ = 'q';
12903           else
12904             *obufp++ = 'd';
12905           if (!(rex & REX_W))
12906             used_prefixes |= (prefixes & PREFIX_DATA);
12907           break;
12908         case '&':
12909           if (!intel_syntax
12910               && address_mode == mode_64bit
12911               && isa64 == intel64)
12912             {
12913               *obufp++ = 'q';
12914               break;
12915             }
12916           /* Fall through.  */
12917         case 'T':
12918           if (!intel_syntax
12919               && address_mode == mode_64bit
12920               && ((sizeflag & DFLAG) || (rex & REX_W)))
12921             {
12922               *obufp++ = 'q';
12923               break;
12924             }
12925           /* Fall through.  */
12926           goto case_P;
12927         case 'P':
12928           if (l == 0 && len == 1)
12929             {
12930 case_P:
12931               if (intel_syntax)
12932                 {
12933                   if ((rex & REX_W) == 0
12934                       && (prefixes & PREFIX_DATA))
12935                     {
12936                       if ((sizeflag & DFLAG) == 0)
12937                         *obufp++ = 'w';
12938                       used_prefixes |= (prefixes & PREFIX_DATA);
12939                     }
12940                   break;
12941                 }
12942               if ((prefixes & PREFIX_DATA)
12943                   || (rex & REX_W)
12944                   || (sizeflag & SUFFIX_ALWAYS))
12945                 {
12946                   USED_REX (REX_W);
12947                   if (rex & REX_W)
12948                     *obufp++ = 'q';
12949                   else
12950                     {
12951                       if (sizeflag & DFLAG)
12952                         *obufp++ = 'l';
12953                       else
12954                         *obufp++ = 'w';
12955                       used_prefixes |= (prefixes & PREFIX_DATA);
12956                     }
12957                 }
12958             }
12959           else
12960             {
12961               if (l != 1 || len != 2 || last[0] != 'L')
12962                 {
12963                   SAVE_LAST (*p);
12964                   break;
12965                 }
12966
12967               if ((prefixes & PREFIX_DATA)
12968                   || (rex & REX_W)
12969                   || (sizeflag & SUFFIX_ALWAYS))
12970                 {
12971                   USED_REX (REX_W);
12972                   if (rex & REX_W)
12973                     *obufp++ = 'q';
12974                   else
12975                     {
12976                       if (sizeflag & DFLAG)
12977                         *obufp++ = intel_syntax ? 'd' : 'l';
12978                       else
12979                         *obufp++ = 'w';
12980                       used_prefixes |= (prefixes & PREFIX_DATA);
12981                     }
12982                 }
12983             }
12984           break;
12985         case 'U':
12986           if (intel_syntax)
12987             break;
12988           if (address_mode == mode_64bit
12989               && ((sizeflag & DFLAG) || (rex & REX_W)))
12990             {
12991               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12992                 *obufp++ = 'q';
12993               break;
12994             }
12995           /* Fall through.  */
12996           goto case_Q;
12997         case 'Q':
12998           if (l == 0 && len == 1)
12999             {
13000 case_Q:
13001               if (intel_syntax && !alt)
13002                 break;
13003               USED_REX (REX_W);
13004               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13005                 {
13006                   if (rex & REX_W)
13007                     *obufp++ = 'q';
13008                   else
13009                     {
13010                       if (sizeflag & DFLAG)
13011                         *obufp++ = intel_syntax ? 'd' : 'l';
13012                       else
13013                         *obufp++ = 'w';
13014                       used_prefixes |= (prefixes & PREFIX_DATA);
13015                     }
13016                 }
13017             }
13018           else
13019             {
13020               if (l != 1 || len != 2 || last[0] != 'L')
13021                 {
13022                   SAVE_LAST (*p);
13023                   break;
13024                 }
13025               if (intel_syntax
13026                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13027                 break;
13028               if ((rex & REX_W))
13029                 {
13030                   USED_REX (REX_W);
13031                   *obufp++ = 'q';
13032                 }
13033               else
13034                 *obufp++ = 'l';
13035             }
13036           break;
13037         case 'R':
13038           USED_REX (REX_W);
13039           if (rex & REX_W)
13040             *obufp++ = 'q';
13041           else if (sizeflag & DFLAG)
13042             {
13043               if (intel_syntax)
13044                   *obufp++ = 'd';
13045               else
13046                   *obufp++ = 'l';
13047             }
13048           else
13049             *obufp++ = 'w';
13050           if (intel_syntax && !p[1]
13051               && ((rex & REX_W) || (sizeflag & DFLAG)))
13052             *obufp++ = 'e';
13053           if (!(rex & REX_W))
13054             used_prefixes |= (prefixes & PREFIX_DATA);
13055           break;
13056         case 'V':
13057           if (l == 0 && len == 1)
13058             {
13059               if (intel_syntax)
13060                 break;
13061               if (address_mode == mode_64bit
13062                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13063                 {
13064                   if (sizeflag & SUFFIX_ALWAYS)
13065                     *obufp++ = 'q';
13066                   break;
13067                 }
13068             }
13069           else
13070             {
13071               if (l != 1
13072                   || len != 2
13073                   || last[0] != 'L')
13074                 {
13075                   SAVE_LAST (*p);
13076                   break;
13077                 }
13078
13079               if (rex & REX_W)
13080                 {
13081                   *obufp++ = 'a';
13082                   *obufp++ = 'b';
13083                   *obufp++ = 's';
13084                 }
13085             }
13086           /* Fall through.  */
13087           goto case_S;
13088         case 'S':
13089           if (l == 0 && len == 1)
13090             {
13091 case_S:
13092               if (intel_syntax)
13093                 break;
13094               if (sizeflag & SUFFIX_ALWAYS)
13095                 {
13096                   if (rex & REX_W)
13097                     *obufp++ = 'q';
13098                   else
13099                     {
13100                       if (sizeflag & DFLAG)
13101                         *obufp++ = 'l';
13102                       else
13103                         *obufp++ = 'w';
13104                       used_prefixes |= (prefixes & PREFIX_DATA);
13105                     }
13106                 }
13107             }
13108           else
13109             {
13110               if (l != 1
13111                   || len != 2
13112                   || last[0] != 'L')
13113                 {
13114                   SAVE_LAST (*p);
13115                   break;
13116                 }
13117
13118               if (address_mode == mode_64bit
13119                   && !(prefixes & PREFIX_ADDR))
13120                 {
13121                   *obufp++ = 'a';
13122                   *obufp++ = 'b';
13123                   *obufp++ = 's';
13124                 }
13125
13126               goto case_S;
13127             }
13128           break;
13129         case 'X':
13130           if (l != 0 || len != 1)
13131             {
13132               SAVE_LAST (*p);
13133               break;
13134             }
13135           if (need_vex && vex.prefix)
13136             {
13137               if (vex.prefix == DATA_PREFIX_OPCODE)
13138                 *obufp++ = 'd';
13139               else
13140                 *obufp++ = 's';
13141             }
13142           else
13143             {
13144               if (prefixes & PREFIX_DATA)
13145                 *obufp++ = 'd';
13146               else
13147                 *obufp++ = 's';
13148               used_prefixes |= (prefixes & PREFIX_DATA);
13149             }
13150           break;
13151         case 'Y':
13152           if (l == 0 && len == 1)
13153             abort ();
13154           else
13155             {
13156               if (l != 1 || len != 2 || last[0] != 'X')
13157                 {
13158                   SAVE_LAST (*p);
13159                   break;
13160                 }
13161               if (!need_vex)
13162                 abort ();
13163               if (intel_syntax
13164                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13165                 break;
13166               switch (vex.length)
13167                 {
13168                 case 128:
13169                   *obufp++ = 'x';
13170                   break;
13171                 case 256:
13172                   *obufp++ = 'y';
13173                   break;
13174                 case 512:
13175                   if (!vex.evex)
13176                 default:
13177                     abort ();
13178                 }
13179             }
13180           break;
13181         case 'W':
13182           if (l == 0 && len == 1)
13183             {
13184               /* operand size flag for cwtl, cbtw */
13185               USED_REX (REX_W);
13186               if (rex & REX_W)
13187                 {
13188                   if (intel_syntax)
13189                     *obufp++ = 'd';
13190                   else
13191                     *obufp++ = 'l';
13192                 }
13193               else if (sizeflag & DFLAG)
13194                 *obufp++ = 'w';
13195               else
13196                 *obufp++ = 'b';
13197               if (!(rex & REX_W))
13198                 used_prefixes |= (prefixes & PREFIX_DATA);
13199             }
13200           else
13201             {
13202               if (l != 1
13203                   || len != 2
13204                   || (last[0] != 'X'
13205                       && last[0] != 'L'))
13206                 {
13207                   SAVE_LAST (*p);
13208                   break;
13209                 }
13210               if (!need_vex)
13211                 abort ();
13212               if (last[0] == 'X')
13213                 *obufp++ = vex.w ? 'd': 's';
13214               else
13215                 *obufp++ = vex.w ? 'q': 'd';
13216             }
13217           break;
13218         case '^':
13219           if (intel_syntax)
13220             break;
13221           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13222             {
13223               if (sizeflag & DFLAG)
13224                 *obufp++ = 'l';
13225               else
13226                 *obufp++ = 'w';
13227               used_prefixes |= (prefixes & PREFIX_DATA);
13228             }
13229           break;
13230         case '@':
13231           if (intel_syntax)
13232             break;
13233           if (address_mode == mode_64bit
13234               && (isa64 == intel64
13235                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13236               *obufp++ = 'q';
13237           else if ((prefixes & PREFIX_DATA))
13238             {
13239               if (!(sizeflag & DFLAG))
13240                 *obufp++ = 'w';
13241               used_prefixes |= (prefixes & PREFIX_DATA);
13242             }
13243           break;
13244         }
13245       alt = 0;
13246     }
13247   *obufp = 0;
13248   mnemonicendp = obufp;
13249   return 0;
13250 }
13251
13252 static void
13253 oappend (const char *s)
13254 {
13255   obufp = stpcpy (obufp, s);
13256 }
13257
13258 static void
13259 append_seg (void)
13260 {
13261   /* Only print the active segment register.  */
13262   if (!active_seg_prefix)
13263     return;
13264
13265   used_prefixes |= active_seg_prefix;
13266   switch (active_seg_prefix)
13267     {
13268     case PREFIX_CS:
13269       oappend_maybe_intel ("%cs:");
13270       break;
13271     case PREFIX_DS:
13272       oappend_maybe_intel ("%ds:");
13273       break;
13274     case PREFIX_SS:
13275       oappend_maybe_intel ("%ss:");
13276       break;
13277     case PREFIX_ES:
13278       oappend_maybe_intel ("%es:");
13279       break;
13280     case PREFIX_FS:
13281       oappend_maybe_intel ("%fs:");
13282       break;
13283     case PREFIX_GS:
13284       oappend_maybe_intel ("%gs:");
13285       break;
13286     default:
13287       break;
13288     }
13289 }
13290
13291 static void
13292 OP_indirE (int bytemode, int sizeflag)
13293 {
13294   if (!intel_syntax)
13295     oappend ("*");
13296   OP_E (bytemode, sizeflag);
13297 }
13298
13299 static void
13300 print_operand_value (char *buf, int hex, bfd_vma disp)
13301 {
13302   if (address_mode == mode_64bit)
13303     {
13304       if (hex)
13305         {
13306           char tmp[30];
13307           int i;
13308           buf[0] = '0';
13309           buf[1] = 'x';
13310           sprintf_vma (tmp, disp);
13311           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13312           strcpy (buf + 2, tmp + i);
13313         }
13314       else
13315         {
13316           bfd_signed_vma v = disp;
13317           char tmp[30];
13318           int i;
13319           if (v < 0)
13320             {
13321               *(buf++) = '-';
13322               v = -disp;
13323               /* Check for possible overflow on 0x8000000000000000.  */
13324               if (v < 0)
13325                 {
13326                   strcpy (buf, "9223372036854775808");
13327                   return;
13328                 }
13329             }
13330           if (!v)
13331             {
13332               strcpy (buf, "0");
13333               return;
13334             }
13335
13336           i = 0;
13337           tmp[29] = 0;
13338           while (v)
13339             {
13340               tmp[28 - i] = (v % 10) + '0';
13341               v /= 10;
13342               i++;
13343             }
13344           strcpy (buf, tmp + 29 - i);
13345         }
13346     }
13347   else
13348     {
13349       if (hex)
13350         sprintf (buf, "0x%x", (unsigned int) disp);
13351       else
13352         sprintf (buf, "%d", (int) disp);
13353     }
13354 }
13355
13356 /* Put DISP in BUF as signed hex number.  */
13357
13358 static void
13359 print_displacement (char *buf, bfd_vma disp)
13360 {
13361   bfd_signed_vma val = disp;
13362   char tmp[30];
13363   int i, j = 0;
13364
13365   if (val < 0)
13366     {
13367       buf[j++] = '-';
13368       val = -disp;
13369
13370       /* Check for possible overflow.  */
13371       if (val < 0)
13372         {
13373           switch (address_mode)
13374             {
13375             case mode_64bit:
13376               strcpy (buf + j, "0x8000000000000000");
13377               break;
13378             case mode_32bit:
13379               strcpy (buf + j, "0x80000000");
13380               break;
13381             case mode_16bit:
13382               strcpy (buf + j, "0x8000");
13383               break;
13384             }
13385           return;
13386         }
13387     }
13388
13389   buf[j++] = '0';
13390   buf[j++] = 'x';
13391
13392   sprintf_vma (tmp, (bfd_vma) val);
13393   for (i = 0; tmp[i] == '0'; i++)
13394     continue;
13395   if (tmp[i] == '\0')
13396     i--;
13397   strcpy (buf + j, tmp + i);
13398 }
13399
13400 static void
13401 intel_operand_size (int bytemode, int sizeflag)
13402 {
13403   if (vex.evex
13404       && vex.b
13405       && (bytemode == x_mode
13406           || bytemode == evex_half_bcst_xmmq_mode))
13407     {
13408       if (vex.w)
13409         oappend ("QWORD PTR ");
13410       else
13411         oappend ("DWORD PTR ");
13412       return;
13413     }
13414   switch (bytemode)
13415     {
13416     case b_mode:
13417     case b_swap_mode:
13418     case dqb_mode:
13419     case db_mode:
13420       oappend ("BYTE PTR ");
13421       break;
13422     case w_mode:
13423     case dw_mode:
13424     case dqw_mode:
13425       oappend ("WORD PTR ");
13426       break;
13427     case indir_v_mode:
13428       if (address_mode == mode_64bit && isa64 == intel64)
13429         {
13430           oappend ("QWORD PTR ");
13431           break;
13432         }
13433       /* Fall through.  */
13434     case stack_v_mode:
13435       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13436         {
13437           oappend ("QWORD PTR ");
13438           break;
13439         }
13440       /* Fall through.  */
13441     case v_mode:
13442     case v_swap_mode:
13443     case dq_mode:
13444       USED_REX (REX_W);
13445       if (rex & REX_W)
13446         oappend ("QWORD PTR ");
13447       else
13448         {
13449           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13450             oappend ("DWORD PTR ");
13451           else
13452             oappend ("WORD PTR ");
13453           used_prefixes |= (prefixes & PREFIX_DATA);
13454         }
13455       break;
13456     case z_mode:
13457       if ((rex & REX_W) || (sizeflag & DFLAG))
13458         *obufp++ = 'D';
13459       oappend ("WORD PTR ");
13460       if (!(rex & REX_W))
13461         used_prefixes |= (prefixes & PREFIX_DATA);
13462       break;
13463     case a_mode:
13464       if (sizeflag & DFLAG)
13465         oappend ("QWORD PTR ");
13466       else
13467         oappend ("DWORD PTR ");
13468       used_prefixes |= (prefixes & PREFIX_DATA);
13469       break;
13470     case d_mode:
13471     case d_scalar_mode:
13472     case d_scalar_swap_mode:
13473     case d_swap_mode:
13474     case dqd_mode:
13475       oappend ("DWORD PTR ");
13476       break;
13477     case q_mode:
13478     case q_scalar_mode:
13479     case q_scalar_swap_mode:
13480     case q_swap_mode:
13481       oappend ("QWORD PTR ");
13482       break;
13483     case dqa_mode:
13484     case m_mode:
13485       if (address_mode == mode_64bit)
13486         oappend ("QWORD PTR ");
13487       else
13488         oappend ("DWORD PTR ");
13489       break;
13490     case f_mode:
13491       if (sizeflag & DFLAG)
13492         oappend ("FWORD PTR ");
13493       else
13494         oappend ("DWORD PTR ");
13495       used_prefixes |= (prefixes & PREFIX_DATA);
13496       break;
13497     case t_mode:
13498       oappend ("TBYTE PTR ");
13499       break;
13500     case x_mode:
13501     case x_swap_mode:
13502     case evex_x_gscat_mode:
13503     case evex_x_nobcst_mode:
13504     case b_scalar_mode:
13505     case w_scalar_mode:
13506       if (need_vex)
13507         {
13508           switch (vex.length)
13509             {
13510             case 128:
13511               oappend ("XMMWORD PTR ");
13512               break;
13513             case 256:
13514               oappend ("YMMWORD PTR ");
13515               break;
13516             case 512:
13517               oappend ("ZMMWORD PTR ");
13518               break;
13519             default:
13520               abort ();
13521             }
13522         }
13523       else
13524         oappend ("XMMWORD PTR ");
13525       break;
13526     case xmm_mode:
13527       oappend ("XMMWORD PTR ");
13528       break;
13529     case ymm_mode:
13530       oappend ("YMMWORD PTR ");
13531       break;
13532     case xmmq_mode:
13533     case evex_half_bcst_xmmq_mode:
13534       if (!need_vex)
13535         abort ();
13536
13537       switch (vex.length)
13538         {
13539         case 128:
13540           oappend ("QWORD PTR ");
13541           break;
13542         case 256:
13543           oappend ("XMMWORD PTR ");
13544           break;
13545         case 512:
13546           oappend ("YMMWORD PTR ");
13547           break;
13548         default:
13549           abort ();
13550         }
13551       break;
13552     case xmm_mb_mode:
13553       if (!need_vex)
13554         abort ();
13555
13556       switch (vex.length)
13557         {
13558         case 128:
13559         case 256:
13560         case 512:
13561           oappend ("BYTE PTR ");
13562           break;
13563         default:
13564           abort ();
13565         }
13566       break;
13567     case xmm_mw_mode:
13568       if (!need_vex)
13569         abort ();
13570
13571       switch (vex.length)
13572         {
13573         case 128:
13574         case 256:
13575         case 512:
13576           oappend ("WORD PTR ");
13577           break;
13578         default:
13579           abort ();
13580         }
13581       break;
13582     case xmm_md_mode:
13583       if (!need_vex)
13584         abort ();
13585
13586       switch (vex.length)
13587         {
13588         case 128:
13589         case 256:
13590         case 512:
13591           oappend ("DWORD PTR ");
13592           break;
13593         default:
13594           abort ();
13595         }
13596       break;
13597     case xmm_mq_mode:
13598       if (!need_vex)
13599         abort ();
13600
13601       switch (vex.length)
13602         {
13603         case 128:
13604         case 256:
13605         case 512:
13606           oappend ("QWORD PTR ");
13607           break;
13608         default:
13609           abort ();
13610         }
13611       break;
13612     case xmmdw_mode:
13613       if (!need_vex)
13614         abort ();
13615
13616       switch (vex.length)
13617         {
13618         case 128:
13619           oappend ("WORD PTR ");
13620           break;
13621         case 256:
13622           oappend ("DWORD PTR ");
13623           break;
13624         case 512:
13625           oappend ("QWORD PTR ");
13626           break;
13627         default:
13628           abort ();
13629         }
13630       break;
13631     case xmmqd_mode:
13632       if (!need_vex)
13633         abort ();
13634
13635       switch (vex.length)
13636         {
13637         case 128:
13638           oappend ("DWORD PTR ");
13639           break;
13640         case 256:
13641           oappend ("QWORD PTR ");
13642           break;
13643         case 512:
13644           oappend ("XMMWORD PTR ");
13645           break;
13646         default:
13647           abort ();
13648         }
13649       break;
13650     case ymmq_mode:
13651       if (!need_vex)
13652         abort ();
13653
13654       switch (vex.length)
13655         {
13656         case 128:
13657           oappend ("QWORD PTR ");
13658           break;
13659         case 256:
13660           oappend ("YMMWORD PTR ");
13661           break;
13662         case 512:
13663           oappend ("ZMMWORD PTR ");
13664           break;
13665         default:
13666           abort ();
13667         }
13668       break;
13669     case ymmxmm_mode:
13670       if (!need_vex)
13671         abort ();
13672
13673       switch (vex.length)
13674         {
13675         case 128:
13676         case 256:
13677           oappend ("XMMWORD PTR ");
13678           break;
13679         default:
13680           abort ();
13681         }
13682       break;
13683     case o_mode:
13684       oappend ("OWORD PTR ");
13685       break;
13686     case xmm_mdq_mode:
13687     case vex_w_dq_mode:
13688     case vex_scalar_w_dq_mode:
13689       if (!need_vex)
13690         abort ();
13691
13692       if (vex.w)
13693         oappend ("QWORD PTR ");
13694       else
13695         oappend ("DWORD PTR ");
13696       break;
13697     case vex_vsib_d_w_dq_mode:
13698     case vex_vsib_q_w_dq_mode:
13699       if (!need_vex)
13700         abort ();
13701
13702       if (!vex.evex)
13703         {
13704           if (vex.w)
13705             oappend ("QWORD PTR ");
13706           else
13707             oappend ("DWORD PTR ");
13708         }
13709       else
13710         {
13711           switch (vex.length)
13712             {
13713             case 128:
13714               oappend ("XMMWORD PTR ");
13715               break;
13716             case 256:
13717               oappend ("YMMWORD PTR ");
13718               break;
13719             case 512:
13720               oappend ("ZMMWORD PTR ");
13721               break;
13722             default:
13723               abort ();
13724             }
13725         }
13726       break;
13727     case vex_vsib_q_w_d_mode:
13728     case vex_vsib_d_w_d_mode:
13729       if (!need_vex || !vex.evex)
13730         abort ();
13731
13732       switch (vex.length)
13733         {
13734         case 128:
13735           oappend ("QWORD PTR ");
13736           break;
13737         case 256:
13738           oappend ("XMMWORD PTR ");
13739           break;
13740         case 512:
13741           oappend ("YMMWORD PTR ");
13742           break;
13743         default:
13744           abort ();
13745         }
13746
13747       break;
13748     case mask_bd_mode:
13749       if (!need_vex || vex.length != 128)
13750         abort ();
13751       if (vex.w)
13752         oappend ("DWORD PTR ");
13753       else
13754         oappend ("BYTE PTR ");
13755       break;
13756     case mask_mode:
13757       if (!need_vex)
13758         abort ();
13759       if (vex.w)
13760         oappend ("QWORD PTR ");
13761       else
13762         oappend ("WORD PTR ");
13763       break;
13764     case v_bnd_mode:
13765     case v_bndmk_mode:
13766     default:
13767       break;
13768     }
13769 }
13770
13771 static void
13772 OP_E_register (int bytemode, int sizeflag)
13773 {
13774   int reg = modrm.rm;
13775   const char **names;
13776
13777   USED_REX (REX_B);
13778   if ((rex & REX_B))
13779     reg += 8;
13780
13781   if ((sizeflag & SUFFIX_ALWAYS)
13782       && (bytemode == b_swap_mode
13783           || bytemode == bnd_swap_mode
13784           || bytemode == v_swap_mode))
13785     swap_operand ();
13786
13787   switch (bytemode)
13788     {
13789     case b_mode:
13790     case b_swap_mode:
13791       USED_REX (0);
13792       if (rex)
13793         names = names8rex;
13794       else
13795         names = names8;
13796       break;
13797     case w_mode:
13798       names = names16;
13799       break;
13800     case d_mode:
13801     case dw_mode:
13802     case db_mode:
13803       names = names32;
13804       break;
13805     case q_mode:
13806       names = names64;
13807       break;
13808     case m_mode:
13809     case v_bnd_mode:
13810       names = address_mode == mode_64bit ? names64 : names32;
13811       break;
13812     case bnd_mode:
13813     case bnd_swap_mode:
13814       if (reg > 0x3)
13815         {
13816           oappend ("(bad)");
13817           return;
13818         }
13819       names = names_bnd;
13820       break;
13821     case indir_v_mode:
13822       if (address_mode == mode_64bit && isa64 == intel64)
13823         {
13824           names = names64;
13825           break;
13826         }
13827       /* Fall through.  */
13828     case stack_v_mode:
13829       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13830         {
13831           names = names64;
13832           break;
13833         }
13834       bytemode = v_mode;
13835       /* Fall through.  */
13836     case v_mode:
13837     case v_swap_mode:
13838     case dq_mode:
13839     case dqb_mode:
13840     case dqd_mode:
13841     case dqw_mode:
13842     case dqa_mode:
13843       USED_REX (REX_W);
13844       if (rex & REX_W)
13845         names = names64;
13846       else
13847         {
13848           if ((sizeflag & DFLAG)
13849               || (bytemode != v_mode
13850                   && bytemode != v_swap_mode))
13851             names = names32;
13852           else
13853             names = names16;
13854           used_prefixes |= (prefixes & PREFIX_DATA);
13855         }
13856       break;
13857     case va_mode:
13858       names = (address_mode == mode_64bit
13859                ? names64 : names32);
13860       if (!(prefixes & PREFIX_ADDR))
13861         names = (address_mode == mode_16bit
13862                      ? names16 : names);
13863       else
13864         {
13865           /* Remove "addr16/addr32".  */
13866           all_prefixes[last_addr_prefix] = 0;
13867           names = (address_mode != mode_32bit
13868                        ? names32 : names16);
13869           used_prefixes |= PREFIX_ADDR;
13870         }
13871       break;
13872     case mask_bd_mode:
13873     case mask_mode:
13874       if (reg > 0x7)
13875         {
13876           oappend ("(bad)");
13877           return;
13878         }
13879       names = names_mask;
13880       break;
13881     case 0:
13882       return;
13883     default:
13884       oappend (INTERNAL_DISASSEMBLER_ERROR);
13885       return;
13886     }
13887   oappend (names[reg]);
13888 }
13889
13890 static void
13891 OP_E_memory (int bytemode, int sizeflag)
13892 {
13893   bfd_vma disp = 0;
13894   int add = (rex & REX_B) ? 8 : 0;
13895   int riprel = 0;
13896   int shift;
13897
13898   if (vex.evex)
13899     {
13900       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13901       if (vex.b
13902           && bytemode != x_mode
13903           && bytemode != xmmq_mode
13904           && bytemode != evex_half_bcst_xmmq_mode)
13905         {
13906           BadOp ();
13907           return;
13908         }
13909       switch (bytemode)
13910         {
13911         case dqw_mode:
13912         case dw_mode:
13913           shift = 1;
13914           break;
13915         case dqb_mode:
13916         case db_mode:
13917           shift = 0;
13918           break;
13919         case dq_mode:
13920           if (address_mode != mode_64bit)
13921             {
13922               shift = 2;
13923               break;
13924             }
13925             /* fall through */
13926         case vex_vsib_d_w_dq_mode:
13927         case vex_vsib_d_w_d_mode:
13928         case vex_vsib_q_w_dq_mode:
13929         case vex_vsib_q_w_d_mode:
13930         case evex_x_gscat_mode:
13931         case xmm_mdq_mode:
13932           shift = vex.w ? 3 : 2;
13933           break;
13934         case x_mode:
13935         case evex_half_bcst_xmmq_mode:
13936         case xmmq_mode:
13937           if (vex.b)
13938             {
13939               shift = vex.w ? 3 : 2;
13940               break;
13941             }
13942           /* Fall through.  */
13943         case xmmqd_mode:
13944         case xmmdw_mode:
13945         case ymmq_mode:
13946         case evex_x_nobcst_mode:
13947         case x_swap_mode:
13948           switch (vex.length)
13949             {
13950             case 128:
13951               shift = 4;
13952               break;
13953             case 256:
13954               shift = 5;
13955               break;
13956             case 512:
13957               shift = 6;
13958               break;
13959             default:
13960               abort ();
13961             }
13962           break;
13963         case ymm_mode:
13964           shift = 5;
13965           break;
13966         case xmm_mode:
13967           shift = 4;
13968           break;
13969         case xmm_mq_mode:
13970         case q_mode:
13971         case q_scalar_mode:
13972         case q_swap_mode:
13973         case q_scalar_swap_mode:
13974           shift = 3;
13975           break;
13976         case dqd_mode:
13977         case xmm_md_mode:
13978         case d_mode:
13979         case d_scalar_mode:
13980         case d_swap_mode:
13981         case d_scalar_swap_mode:
13982           shift = 2;
13983           break;
13984         case w_scalar_mode:
13985         case xmm_mw_mode:
13986           shift = 1;
13987           break;
13988         case b_scalar_mode:
13989         case xmm_mb_mode:
13990           shift = 0;
13991           break;
13992         case dqa_mode:
13993           shift = address_mode == mode_64bit ? 3 : 2;
13994           break;
13995         default:
13996           abort ();
13997         }
13998       /* Make necessary corrections to shift for modes that need it.
13999          For these modes we currently have shift 4, 5 or 6 depending on
14000          vex.length (it corresponds to xmmword, ymmword or zmmword
14001          operand).  We might want to make it 3, 4 or 5 (e.g. for
14002          xmmq_mode).  In case of broadcast enabled the corrections
14003          aren't needed, as element size is always 32 or 64 bits.  */
14004       if (!vex.b
14005           && (bytemode == xmmq_mode
14006               || bytemode == evex_half_bcst_xmmq_mode))
14007         shift -= 1;
14008       else if (bytemode == xmmqd_mode)
14009         shift -= 2;
14010       else if (bytemode == xmmdw_mode)
14011         shift -= 3;
14012       else if (bytemode == ymmq_mode && vex.length == 128)
14013         shift -= 1;
14014     }
14015   else
14016     shift = 0;
14017
14018   USED_REX (REX_B);
14019   if (intel_syntax)
14020     intel_operand_size (bytemode, sizeflag);
14021   append_seg ();
14022
14023   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14024     {
14025       /* 32/64 bit address mode */
14026       int havedisp;
14027       int havesib;
14028       int havebase;
14029       int haveindex;
14030       int needindex;
14031       int needaddr32;
14032       int base, rbase;
14033       int vindex = 0;
14034       int scale = 0;
14035       int addr32flag = !((sizeflag & AFLAG)
14036                          || bytemode == v_bnd_mode
14037                          || bytemode == v_bndmk_mode
14038                          || bytemode == bnd_mode
14039                          || bytemode == bnd_swap_mode);
14040       const char **indexes64 = names64;
14041       const char **indexes32 = names32;
14042
14043       havesib = 0;
14044       havebase = 1;
14045       haveindex = 0;
14046       base = modrm.rm;
14047
14048       if (base == 4)
14049         {
14050           havesib = 1;
14051           vindex = sib.index;
14052           USED_REX (REX_X);
14053           if (rex & REX_X)
14054             vindex += 8;
14055           switch (bytemode)
14056             {
14057             case vex_vsib_d_w_dq_mode:
14058             case vex_vsib_d_w_d_mode:
14059             case vex_vsib_q_w_dq_mode:
14060             case vex_vsib_q_w_d_mode:
14061               if (!need_vex)
14062                 abort ();
14063               if (vex.evex)
14064                 {
14065                   if (!vex.v)
14066                     vindex += 16;
14067                 }
14068
14069               haveindex = 1;
14070               switch (vex.length)
14071                 {
14072                 case 128:
14073                   indexes64 = indexes32 = names_xmm;
14074                   break;
14075                 case 256:
14076                   if (!vex.w
14077                       || bytemode == vex_vsib_q_w_dq_mode
14078                       || bytemode == vex_vsib_q_w_d_mode)
14079                     indexes64 = indexes32 = names_ymm;
14080                   else
14081                     indexes64 = indexes32 = names_xmm;
14082                   break;
14083                 case 512:
14084                   if (!vex.w
14085                       || bytemode == vex_vsib_q_w_dq_mode
14086                       || bytemode == vex_vsib_q_w_d_mode)
14087                     indexes64 = indexes32 = names_zmm;
14088                   else
14089                     indexes64 = indexes32 = names_ymm;
14090                   break;
14091                 default:
14092                   abort ();
14093                 }
14094               break;
14095             default:
14096               haveindex = vindex != 4;
14097               break;
14098             }
14099           scale = sib.scale;
14100           base = sib.base;
14101           codep++;
14102         }
14103       rbase = base + add;
14104
14105       switch (modrm.mod)
14106         {
14107         case 0:
14108           if (base == 5)
14109             {
14110               havebase = 0;
14111               if (address_mode == mode_64bit && !havesib)
14112                 riprel = 1;
14113               disp = get32s ();
14114               if (riprel && bytemode == v_bndmk_mode)
14115                 {
14116                   oappend ("(bad)");
14117                   return;
14118                 }
14119             }
14120           break;
14121         case 1:
14122           FETCH_DATA (the_info, codep + 1);
14123           disp = *codep++;
14124           if ((disp & 0x80) != 0)
14125             disp -= 0x100;
14126           if (vex.evex && shift > 0)
14127             disp <<= shift;
14128           break;
14129         case 2:
14130           disp = get32s ();
14131           break;
14132         }
14133
14134       needindex = 0;
14135       needaddr32 = 0;
14136       if (havesib
14137           && !havebase
14138           && !haveindex
14139           && address_mode != mode_16bit)
14140         {
14141           if (address_mode == mode_64bit)
14142             {
14143               /* Display eiz instead of addr32.  */
14144               needindex = addr32flag;
14145               needaddr32 = 1;
14146             }
14147           else
14148             {
14149               /* In 32-bit mode, we need index register to tell [offset]
14150                  from [eiz*1 + offset].  */
14151               needindex = 1;
14152             }
14153         }
14154
14155       havedisp = (havebase
14156                   || needindex
14157                   || (havesib && (haveindex || scale != 0)));
14158
14159       if (!intel_syntax)
14160         if (modrm.mod != 0 || base == 5)
14161           {
14162             if (havedisp || riprel)
14163               print_displacement (scratchbuf, disp);
14164             else
14165               print_operand_value (scratchbuf, 1, disp);
14166             oappend (scratchbuf);
14167             if (riprel)
14168               {
14169                 set_op (disp, 1);
14170                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14171               }
14172           }
14173
14174       if ((havebase || haveindex || needaddr32 || riprel)
14175           && (bytemode != v_bnd_mode)
14176           && (bytemode != v_bndmk_mode)
14177           && (bytemode != bnd_mode)
14178           && (bytemode != bnd_swap_mode))
14179         used_prefixes |= PREFIX_ADDR;
14180
14181       if (havedisp || (intel_syntax && riprel))
14182         {
14183           *obufp++ = open_char;
14184           if (intel_syntax && riprel)
14185             {
14186               set_op (disp, 1);
14187               oappend (!addr32flag ? "rip" : "eip");
14188             }
14189           *obufp = '\0';
14190           if (havebase)
14191             oappend (address_mode == mode_64bit && !addr32flag
14192                      ? names64[rbase] : names32[rbase]);
14193           if (havesib)
14194             {
14195               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14196                  print index to tell base + index from base.  */
14197               if (scale != 0
14198                   || needindex
14199                   || haveindex
14200                   || (havebase && base != ESP_REG_NUM))
14201                 {
14202                   if (!intel_syntax || havebase)
14203                     {
14204                       *obufp++ = separator_char;
14205                       *obufp = '\0';
14206                     }
14207                   if (haveindex)
14208                     oappend (address_mode == mode_64bit && !addr32flag
14209                              ? indexes64[vindex] : indexes32[vindex]);
14210                   else
14211                     oappend (address_mode == mode_64bit && !addr32flag
14212                              ? index64 : index32);
14213
14214                   *obufp++ = scale_char;
14215                   *obufp = '\0';
14216                   sprintf (scratchbuf, "%d", 1 << scale);
14217                   oappend (scratchbuf);
14218                 }
14219             }
14220           if (intel_syntax
14221               && (disp || modrm.mod != 0 || base == 5))
14222             {
14223               if (!havedisp || (bfd_signed_vma) disp >= 0)
14224                 {
14225                   *obufp++ = '+';
14226                   *obufp = '\0';
14227                 }
14228               else if (modrm.mod != 1 && disp != -disp)
14229                 {
14230                   *obufp++ = '-';
14231                   *obufp = '\0';
14232                   disp = - (bfd_signed_vma) disp;
14233                 }
14234
14235               if (havedisp)
14236                 print_displacement (scratchbuf, disp);
14237               else
14238                 print_operand_value (scratchbuf, 1, disp);
14239               oappend (scratchbuf);
14240             }
14241
14242           *obufp++ = close_char;
14243           *obufp = '\0';
14244         }
14245       else if (intel_syntax)
14246         {
14247           if (modrm.mod != 0 || base == 5)
14248             {
14249               if (!active_seg_prefix)
14250                 {
14251                   oappend (names_seg[ds_reg - es_reg]);
14252                   oappend (":");
14253                 }
14254               print_operand_value (scratchbuf, 1, disp);
14255               oappend (scratchbuf);
14256             }
14257         }
14258     }
14259   else
14260     {
14261       /* 16 bit address mode */
14262       used_prefixes |= prefixes & PREFIX_ADDR;
14263       switch (modrm.mod)
14264         {
14265         case 0:
14266           if (modrm.rm == 6)
14267             {
14268               disp = get16 ();
14269               if ((disp & 0x8000) != 0)
14270                 disp -= 0x10000;
14271             }
14272           break;
14273         case 1:
14274           FETCH_DATA (the_info, codep + 1);
14275           disp = *codep++;
14276           if ((disp & 0x80) != 0)
14277             disp -= 0x100;
14278           if (vex.evex && shift > 0)
14279             disp <<= shift;
14280           break;
14281         case 2:
14282           disp = get16 ();
14283           if ((disp & 0x8000) != 0)
14284             disp -= 0x10000;
14285           break;
14286         }
14287
14288       if (!intel_syntax)
14289         if (modrm.mod != 0 || modrm.rm == 6)
14290           {
14291             print_displacement (scratchbuf, disp);
14292             oappend (scratchbuf);
14293           }
14294
14295       if (modrm.mod != 0 || modrm.rm != 6)
14296         {
14297           *obufp++ = open_char;
14298           *obufp = '\0';
14299           oappend (index16[modrm.rm]);
14300           if (intel_syntax
14301               && (disp || modrm.mod != 0 || modrm.rm == 6))
14302             {
14303               if ((bfd_signed_vma) disp >= 0)
14304                 {
14305                   *obufp++ = '+';
14306                   *obufp = '\0';
14307                 }
14308               else if (modrm.mod != 1)
14309                 {
14310                   *obufp++ = '-';
14311                   *obufp = '\0';
14312                   disp = - (bfd_signed_vma) disp;
14313                 }
14314
14315               print_displacement (scratchbuf, disp);
14316               oappend (scratchbuf);
14317             }
14318
14319           *obufp++ = close_char;
14320           *obufp = '\0';
14321         }
14322       else if (intel_syntax)
14323         {
14324           if (!active_seg_prefix)
14325             {
14326               oappend (names_seg[ds_reg - es_reg]);
14327               oappend (":");
14328             }
14329           print_operand_value (scratchbuf, 1, disp & 0xffff);
14330           oappend (scratchbuf);
14331         }
14332     }
14333   if (vex.evex && vex.b
14334       && (bytemode == x_mode
14335           || bytemode == xmmq_mode
14336           || bytemode == evex_half_bcst_xmmq_mode))
14337     {
14338       if (vex.w
14339           || bytemode == xmmq_mode
14340           || bytemode == evex_half_bcst_xmmq_mode)
14341         {
14342           switch (vex.length)
14343             {
14344             case 128:
14345               oappend ("{1to2}");
14346               break;
14347             case 256:
14348               oappend ("{1to4}");
14349               break;
14350             case 512:
14351               oappend ("{1to8}");
14352               break;
14353             default:
14354               abort ();
14355             }
14356         }
14357       else
14358         {
14359           switch (vex.length)
14360             {
14361             case 128:
14362               oappend ("{1to4}");
14363               break;
14364             case 256:
14365               oappend ("{1to8}");
14366               break;
14367             case 512:
14368               oappend ("{1to16}");
14369               break;
14370             default:
14371               abort ();
14372             }
14373         }
14374     }
14375 }
14376
14377 static void
14378 OP_E (int bytemode, int sizeflag)
14379 {
14380   /* Skip mod/rm byte.  */
14381   MODRM_CHECK;
14382   codep++;
14383
14384   if (modrm.mod == 3)
14385     OP_E_register (bytemode, sizeflag);
14386   else
14387     OP_E_memory (bytemode, sizeflag);
14388 }
14389
14390 static void
14391 OP_G (int bytemode, int sizeflag)
14392 {
14393   int add = 0;
14394   const char **names;
14395   USED_REX (REX_R);
14396   if (rex & REX_R)
14397     add += 8;
14398   switch (bytemode)
14399     {
14400     case b_mode:
14401       USED_REX (0);
14402       if (rex)
14403         oappend (names8rex[modrm.reg + add]);
14404       else
14405         oappend (names8[modrm.reg + add]);
14406       break;
14407     case w_mode:
14408       oappend (names16[modrm.reg + add]);
14409       break;
14410     case d_mode:
14411     case db_mode:
14412     case dw_mode:
14413       oappend (names32[modrm.reg + add]);
14414       break;
14415     case q_mode:
14416       oappend (names64[modrm.reg + add]);
14417       break;
14418     case bnd_mode:
14419       if (modrm.reg > 0x3)
14420         {
14421           oappend ("(bad)");
14422           return;
14423         }
14424       oappend (names_bnd[modrm.reg]);
14425       break;
14426     case v_mode:
14427     case dq_mode:
14428     case dqb_mode:
14429     case dqd_mode:
14430     case dqw_mode:
14431       USED_REX (REX_W);
14432       if (rex & REX_W)
14433         oappend (names64[modrm.reg + add]);
14434       else
14435         {
14436           if ((sizeflag & DFLAG) || bytemode != v_mode)
14437             oappend (names32[modrm.reg + add]);
14438           else
14439             oappend (names16[modrm.reg + add]);
14440           used_prefixes |= (prefixes & PREFIX_DATA);
14441         }
14442       break;
14443     case va_mode:
14444       names = (address_mode == mode_64bit
14445                ? names64 : names32);
14446       if (!(prefixes & PREFIX_ADDR))
14447         {
14448           if (address_mode == mode_16bit)
14449             names = names16;
14450         }
14451       else
14452         {
14453           /* Remove "addr16/addr32".  */
14454           all_prefixes[last_addr_prefix] = 0;
14455           names = (address_mode != mode_32bit
14456                        ? names32 : names16);
14457           used_prefixes |= PREFIX_ADDR;
14458         }
14459       oappend (names[modrm.reg + add]);
14460       break;
14461     case m_mode:
14462       if (address_mode == mode_64bit)
14463         oappend (names64[modrm.reg + add]);
14464       else
14465         oappend (names32[modrm.reg + add]);
14466       break;
14467     case mask_bd_mode:
14468     case mask_mode:
14469       if ((modrm.reg + add) > 0x7)
14470         {
14471           oappend ("(bad)");
14472           return;
14473         }
14474       oappend (names_mask[modrm.reg + add]);
14475       break;
14476     default:
14477       oappend (INTERNAL_DISASSEMBLER_ERROR);
14478       break;
14479     }
14480 }
14481
14482 static bfd_vma
14483 get64 (void)
14484 {
14485   bfd_vma x;
14486 #ifdef BFD64
14487   unsigned int a;
14488   unsigned int b;
14489
14490   FETCH_DATA (the_info, codep + 8);
14491   a = *codep++ & 0xff;
14492   a |= (*codep++ & 0xff) << 8;
14493   a |= (*codep++ & 0xff) << 16;
14494   a |= (*codep++ & 0xffu) << 24;
14495   b = *codep++ & 0xff;
14496   b |= (*codep++ & 0xff) << 8;
14497   b |= (*codep++ & 0xff) << 16;
14498   b |= (*codep++ & 0xffu) << 24;
14499   x = a + ((bfd_vma) b << 32);
14500 #else
14501   abort ();
14502   x = 0;
14503 #endif
14504   return x;
14505 }
14506
14507 static bfd_signed_vma
14508 get32 (void)
14509 {
14510   bfd_signed_vma x = 0;
14511
14512   FETCH_DATA (the_info, codep + 4);
14513   x = *codep++ & (bfd_signed_vma) 0xff;
14514   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14515   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14516   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14517   return x;
14518 }
14519
14520 static bfd_signed_vma
14521 get32s (void)
14522 {
14523   bfd_signed_vma x = 0;
14524
14525   FETCH_DATA (the_info, codep + 4);
14526   x = *codep++ & (bfd_signed_vma) 0xff;
14527   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14528   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14529   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14530
14531   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14532
14533   return x;
14534 }
14535
14536 static int
14537 get16 (void)
14538 {
14539   int x = 0;
14540
14541   FETCH_DATA (the_info, codep + 2);
14542   x = *codep++ & 0xff;
14543   x |= (*codep++ & 0xff) << 8;
14544   return x;
14545 }
14546
14547 static void
14548 set_op (bfd_vma op, int riprel)
14549 {
14550   op_index[op_ad] = op_ad;
14551   if (address_mode == mode_64bit)
14552     {
14553       op_address[op_ad] = op;
14554       op_riprel[op_ad] = riprel;
14555     }
14556   else
14557     {
14558       /* Mask to get a 32-bit address.  */
14559       op_address[op_ad] = op & 0xffffffff;
14560       op_riprel[op_ad] = riprel & 0xffffffff;
14561     }
14562 }
14563
14564 static void
14565 OP_REG (int code, int sizeflag)
14566 {
14567   const char *s;
14568   int add;
14569
14570   switch (code)
14571     {
14572     case es_reg: case ss_reg: case cs_reg:
14573     case ds_reg: case fs_reg: case gs_reg:
14574       oappend (names_seg[code - es_reg]);
14575       return;
14576     }
14577
14578   USED_REX (REX_B);
14579   if (rex & REX_B)
14580     add = 8;
14581   else
14582     add = 0;
14583
14584   switch (code)
14585     {
14586     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14587     case sp_reg: case bp_reg: case si_reg: case di_reg:
14588       s = names16[code - ax_reg + add];
14589       break;
14590     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14591     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14592       USED_REX (0);
14593       if (rex)
14594         s = names8rex[code - al_reg + add];
14595       else
14596         s = names8[code - al_reg];
14597       break;
14598     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14599     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14600       if (address_mode == mode_64bit
14601           && ((sizeflag & DFLAG) || (rex & REX_W)))
14602         {
14603           s = names64[code - rAX_reg + add];
14604           break;
14605         }
14606       code += eAX_reg - rAX_reg;
14607       /* Fall through.  */
14608     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14609     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14610       USED_REX (REX_W);
14611       if (rex & REX_W)
14612         s = names64[code - eAX_reg + add];
14613       else
14614         {
14615           if (sizeflag & DFLAG)
14616             s = names32[code - eAX_reg + add];
14617           else
14618             s = names16[code - eAX_reg + add];
14619           used_prefixes |= (prefixes & PREFIX_DATA);
14620         }
14621       break;
14622     default:
14623       s = INTERNAL_DISASSEMBLER_ERROR;
14624       break;
14625     }
14626   oappend (s);
14627 }
14628
14629 static void
14630 OP_IMREG (int code, int sizeflag)
14631 {
14632   const char *s;
14633
14634   switch (code)
14635     {
14636     case indir_dx_reg:
14637       if (intel_syntax)
14638         s = "dx";
14639       else
14640         s = "(%dx)";
14641       break;
14642     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14643     case sp_reg: case bp_reg: case si_reg: case di_reg:
14644       s = names16[code - ax_reg];
14645       break;
14646     case es_reg: case ss_reg: case cs_reg:
14647     case ds_reg: case fs_reg: case gs_reg:
14648       s = names_seg[code - es_reg];
14649       break;
14650     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14651     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14652       USED_REX (0);
14653       if (rex)
14654         s = names8rex[code - al_reg];
14655       else
14656         s = names8[code - al_reg];
14657       break;
14658     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14659     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14660       USED_REX (REX_W);
14661       if (rex & REX_W)
14662         s = names64[code - eAX_reg];
14663       else
14664         {
14665           if (sizeflag & DFLAG)
14666             s = names32[code - eAX_reg];
14667           else
14668             s = names16[code - eAX_reg];
14669           used_prefixes |= (prefixes & PREFIX_DATA);
14670         }
14671       break;
14672     case z_mode_ax_reg:
14673       if ((rex & REX_W) || (sizeflag & DFLAG))
14674         s = *names32;
14675       else
14676         s = *names16;
14677       if (!(rex & REX_W))
14678         used_prefixes |= (prefixes & PREFIX_DATA);
14679       break;
14680     default:
14681       s = INTERNAL_DISASSEMBLER_ERROR;
14682       break;
14683     }
14684   oappend (s);
14685 }
14686
14687 static void
14688 OP_I (int bytemode, int sizeflag)
14689 {
14690   bfd_signed_vma op;
14691   bfd_signed_vma mask = -1;
14692
14693   switch (bytemode)
14694     {
14695     case b_mode:
14696       FETCH_DATA (the_info, codep + 1);
14697       op = *codep++;
14698       mask = 0xff;
14699       break;
14700     case q_mode:
14701       if (address_mode == mode_64bit)
14702         {
14703           op = get32s ();
14704           break;
14705         }
14706       /* Fall through.  */
14707     case v_mode:
14708       USED_REX (REX_W);
14709       if (rex & REX_W)
14710         op = get32s ();
14711       else
14712         {
14713           if (sizeflag & DFLAG)
14714             {
14715               op = get32 ();
14716               mask = 0xffffffff;
14717             }
14718           else
14719             {
14720               op = get16 ();
14721               mask = 0xfffff;
14722             }
14723           used_prefixes |= (prefixes & PREFIX_DATA);
14724         }
14725       break;
14726     case w_mode:
14727       mask = 0xfffff;
14728       op = get16 ();
14729       break;
14730     case const_1_mode:
14731       if (intel_syntax)
14732         oappend ("1");
14733       return;
14734     default:
14735       oappend (INTERNAL_DISASSEMBLER_ERROR);
14736       return;
14737     }
14738
14739   op &= mask;
14740   scratchbuf[0] = '$';
14741   print_operand_value (scratchbuf + 1, 1, op);
14742   oappend_maybe_intel (scratchbuf);
14743   scratchbuf[0] = '\0';
14744 }
14745
14746 static void
14747 OP_I64 (int bytemode, int sizeflag)
14748 {
14749   bfd_signed_vma op;
14750   bfd_signed_vma mask = -1;
14751
14752   if (address_mode != mode_64bit)
14753     {
14754       OP_I (bytemode, sizeflag);
14755       return;
14756     }
14757
14758   switch (bytemode)
14759     {
14760     case b_mode:
14761       FETCH_DATA (the_info, codep + 1);
14762       op = *codep++;
14763       mask = 0xff;
14764       break;
14765     case v_mode:
14766       USED_REX (REX_W);
14767       if (rex & REX_W)
14768         op = get64 ();
14769       else
14770         {
14771           if (sizeflag & DFLAG)
14772             {
14773               op = get32 ();
14774               mask = 0xffffffff;
14775             }
14776           else
14777             {
14778               op = get16 ();
14779               mask = 0xfffff;
14780             }
14781           used_prefixes |= (prefixes & PREFIX_DATA);
14782         }
14783       break;
14784     case w_mode:
14785       mask = 0xfffff;
14786       op = get16 ();
14787       break;
14788     default:
14789       oappend (INTERNAL_DISASSEMBLER_ERROR);
14790       return;
14791     }
14792
14793   op &= mask;
14794   scratchbuf[0] = '$';
14795   print_operand_value (scratchbuf + 1, 1, op);
14796   oappend_maybe_intel (scratchbuf);
14797   scratchbuf[0] = '\0';
14798 }
14799
14800 static void
14801 OP_sI (int bytemode, int sizeflag)
14802 {
14803   bfd_signed_vma op;
14804
14805   switch (bytemode)
14806     {
14807     case b_mode:
14808     case b_T_mode:
14809       FETCH_DATA (the_info, codep + 1);
14810       op = *codep++;
14811       if ((op & 0x80) != 0)
14812         op -= 0x100;
14813       if (bytemode == b_T_mode)
14814         {
14815           if (address_mode != mode_64bit
14816               || !((sizeflag & DFLAG) || (rex & REX_W)))
14817             {
14818               /* The operand-size prefix is overridden by a REX prefix.  */
14819               if ((sizeflag & DFLAG) || (rex & REX_W))
14820                 op &= 0xffffffff;
14821               else
14822                 op &= 0xffff;
14823           }
14824         }
14825       else
14826         {
14827           if (!(rex & REX_W))
14828             {
14829               if (sizeflag & DFLAG)
14830                 op &= 0xffffffff;
14831               else
14832                 op &= 0xffff;
14833             }
14834         }
14835       break;
14836     case v_mode:
14837       /* The operand-size prefix is overridden by a REX prefix.  */
14838       if ((sizeflag & DFLAG) || (rex & REX_W))
14839         op = get32s ();
14840       else
14841         op = get16 ();
14842       break;
14843     default:
14844       oappend (INTERNAL_DISASSEMBLER_ERROR);
14845       return;
14846     }
14847
14848   scratchbuf[0] = '$';
14849   print_operand_value (scratchbuf + 1, 1, op);
14850   oappend_maybe_intel (scratchbuf);
14851 }
14852
14853 static void
14854 OP_J (int bytemode, int sizeflag)
14855 {
14856   bfd_vma disp;
14857   bfd_vma mask = -1;
14858   bfd_vma segment = 0;
14859
14860   switch (bytemode)
14861     {
14862     case b_mode:
14863       FETCH_DATA (the_info, codep + 1);
14864       disp = *codep++;
14865       if ((disp & 0x80) != 0)
14866         disp -= 0x100;
14867       break;
14868     case v_mode:
14869       if (isa64 == amd64)
14870         USED_REX (REX_W);
14871       if ((sizeflag & DFLAG)
14872           || (address_mode == mode_64bit
14873               && (isa64 != amd64 || (rex & REX_W))))
14874         disp = get32s ();
14875       else
14876         {
14877           disp = get16 ();
14878           if ((disp & 0x8000) != 0)
14879             disp -= 0x10000;
14880           /* In 16bit mode, address is wrapped around at 64k within
14881              the same segment.  Otherwise, a data16 prefix on a jump
14882              instruction means that the pc is masked to 16 bits after
14883              the displacement is added!  */
14884           mask = 0xffff;
14885           if ((prefixes & PREFIX_DATA) == 0)
14886             segment = ((start_pc + (codep - start_codep))
14887                        & ~((bfd_vma) 0xffff));
14888         }
14889       if (address_mode != mode_64bit
14890           || (isa64 == amd64 && !(rex & REX_W)))
14891         used_prefixes |= (prefixes & PREFIX_DATA);
14892       break;
14893     default:
14894       oappend (INTERNAL_DISASSEMBLER_ERROR);
14895       return;
14896     }
14897   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14898   set_op (disp, 0);
14899   print_operand_value (scratchbuf, 1, disp);
14900   oappend (scratchbuf);
14901 }
14902
14903 static void
14904 OP_SEG (int bytemode, int sizeflag)
14905 {
14906   if (bytemode == w_mode)
14907     oappend (names_seg[modrm.reg]);
14908   else
14909     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14910 }
14911
14912 static void
14913 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14914 {
14915   int seg, offset;
14916
14917   if (sizeflag & DFLAG)
14918     {
14919       offset = get32 ();
14920       seg = get16 ();
14921     }
14922   else
14923     {
14924       offset = get16 ();
14925       seg = get16 ();
14926     }
14927   used_prefixes |= (prefixes & PREFIX_DATA);
14928   if (intel_syntax)
14929     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14930   else
14931     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14932   oappend (scratchbuf);
14933 }
14934
14935 static void
14936 OP_OFF (int bytemode, int sizeflag)
14937 {
14938   bfd_vma off;
14939
14940   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14941     intel_operand_size (bytemode, sizeflag);
14942   append_seg ();
14943
14944   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14945     off = get32 ();
14946   else
14947     off = get16 ();
14948
14949   if (intel_syntax)
14950     {
14951       if (!active_seg_prefix)
14952         {
14953           oappend (names_seg[ds_reg - es_reg]);
14954           oappend (":");
14955         }
14956     }
14957   print_operand_value (scratchbuf, 1, off);
14958   oappend (scratchbuf);
14959 }
14960
14961 static void
14962 OP_OFF64 (int bytemode, int sizeflag)
14963 {
14964   bfd_vma off;
14965
14966   if (address_mode != mode_64bit
14967       || (prefixes & PREFIX_ADDR))
14968     {
14969       OP_OFF (bytemode, sizeflag);
14970       return;
14971     }
14972
14973   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14974     intel_operand_size (bytemode, sizeflag);
14975   append_seg ();
14976
14977   off = get64 ();
14978
14979   if (intel_syntax)
14980     {
14981       if (!active_seg_prefix)
14982         {
14983           oappend (names_seg[ds_reg - es_reg]);
14984           oappend (":");
14985         }
14986     }
14987   print_operand_value (scratchbuf, 1, off);
14988   oappend (scratchbuf);
14989 }
14990
14991 static void
14992 ptr_reg (int code, int sizeflag)
14993 {
14994   const char *s;
14995
14996   *obufp++ = open_char;
14997   used_prefixes |= (prefixes & PREFIX_ADDR);
14998   if (address_mode == mode_64bit)
14999     {
15000       if (!(sizeflag & AFLAG))
15001         s = names32[code - eAX_reg];
15002       else
15003         s = names64[code - eAX_reg];
15004     }
15005   else if (sizeflag & AFLAG)
15006     s = names32[code - eAX_reg];
15007   else
15008     s = names16[code - eAX_reg];
15009   oappend (s);
15010   *obufp++ = close_char;
15011   *obufp = 0;
15012 }
15013
15014 static void
15015 OP_ESreg (int code, int sizeflag)
15016 {
15017   if (intel_syntax)
15018     {
15019       switch (codep[-1])
15020         {
15021         case 0x6d:      /* insw/insl */
15022           intel_operand_size (z_mode, sizeflag);
15023           break;
15024         case 0xa5:      /* movsw/movsl/movsq */
15025         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15026         case 0xab:      /* stosw/stosl */
15027         case 0xaf:      /* scasw/scasl */
15028           intel_operand_size (v_mode, sizeflag);
15029           break;
15030         default:
15031           intel_operand_size (b_mode, sizeflag);
15032         }
15033     }
15034   oappend_maybe_intel ("%es:");
15035   ptr_reg (code, sizeflag);
15036 }
15037
15038 static void
15039 OP_DSreg (int code, int sizeflag)
15040 {
15041   if (intel_syntax)
15042     {
15043       switch (codep[-1])
15044         {
15045         case 0x6f:      /* outsw/outsl */
15046           intel_operand_size (z_mode, sizeflag);
15047           break;
15048         case 0xa5:      /* movsw/movsl/movsq */
15049         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15050         case 0xad:      /* lodsw/lodsl/lodsq */
15051           intel_operand_size (v_mode, sizeflag);
15052           break;
15053         default:
15054           intel_operand_size (b_mode, sizeflag);
15055         }
15056     }
15057   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15058      default segment register DS is printed.  */
15059   if (!active_seg_prefix)
15060     active_seg_prefix = PREFIX_DS;
15061   append_seg ();
15062   ptr_reg (code, sizeflag);
15063 }
15064
15065 static void
15066 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15067 {
15068   int add;
15069   if (rex & REX_R)
15070     {
15071       USED_REX (REX_R);
15072       add = 8;
15073     }
15074   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15075     {
15076       all_prefixes[last_lock_prefix] = 0;
15077       used_prefixes |= PREFIX_LOCK;
15078       add = 8;
15079     }
15080   else
15081     add = 0;
15082   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15083   oappend_maybe_intel (scratchbuf);
15084 }
15085
15086 static void
15087 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15088 {
15089   int add;
15090   USED_REX (REX_R);
15091   if (rex & REX_R)
15092     add = 8;
15093   else
15094     add = 0;
15095   if (intel_syntax)
15096     sprintf (scratchbuf, "db%d", modrm.reg + add);
15097   else
15098     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15099   oappend (scratchbuf);
15100 }
15101
15102 static void
15103 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15104 {
15105   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15106   oappend_maybe_intel (scratchbuf);
15107 }
15108
15109 static void
15110 OP_R (int bytemode, int sizeflag)
15111 {
15112   /* Skip mod/rm byte.  */
15113   MODRM_CHECK;
15114   codep++;
15115   OP_E_register (bytemode, sizeflag);
15116 }
15117
15118 static void
15119 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15120 {
15121   int reg = modrm.reg;
15122   const char **names;
15123
15124   used_prefixes |= (prefixes & PREFIX_DATA);
15125   if (prefixes & PREFIX_DATA)
15126     {
15127       names = names_xmm;
15128       USED_REX (REX_R);
15129       if (rex & REX_R)
15130         reg += 8;
15131     }
15132   else
15133     names = names_mm;
15134   oappend (names[reg]);
15135 }
15136
15137 static void
15138 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15139 {
15140   int reg = modrm.reg;
15141   const char **names;
15142
15143   USED_REX (REX_R);
15144   if (rex & REX_R)
15145     reg += 8;
15146   if (vex.evex)
15147     {
15148       if (!vex.r)
15149         reg += 16;
15150     }
15151
15152   if (need_vex
15153       && bytemode != xmm_mode
15154       && bytemode != xmmq_mode
15155       && bytemode != evex_half_bcst_xmmq_mode
15156       && bytemode != ymm_mode
15157       && bytemode != scalar_mode)
15158     {
15159       switch (vex.length)
15160         {
15161         case 128:
15162           names = names_xmm;
15163           break;
15164         case 256:
15165           if (vex.w
15166               || (bytemode != vex_vsib_q_w_dq_mode
15167                   && bytemode != vex_vsib_q_w_d_mode))
15168             names = names_ymm;
15169           else
15170             names = names_xmm;
15171           break;
15172         case 512:
15173           names = names_zmm;
15174           break;
15175         default:
15176           abort ();
15177         }
15178     }
15179   else if (bytemode == xmmq_mode
15180            || bytemode == evex_half_bcst_xmmq_mode)
15181     {
15182       switch (vex.length)
15183         {
15184         case 128:
15185         case 256:
15186           names = names_xmm;
15187           break;
15188         case 512:
15189           names = names_ymm;
15190           break;
15191         default:
15192           abort ();
15193         }
15194     }
15195   else if (bytemode == ymm_mode)
15196     names = names_ymm;
15197   else
15198     names = names_xmm;
15199   oappend (names[reg]);
15200 }
15201
15202 static void
15203 OP_EM (int bytemode, int sizeflag)
15204 {
15205   int reg;
15206   const char **names;
15207
15208   if (modrm.mod != 3)
15209     {
15210       if (intel_syntax
15211           && (bytemode == v_mode || bytemode == v_swap_mode))
15212         {
15213           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15214           used_prefixes |= (prefixes & PREFIX_DATA);
15215         }
15216       OP_E (bytemode, sizeflag);
15217       return;
15218     }
15219
15220   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15221     swap_operand ();
15222
15223   /* Skip mod/rm byte.  */
15224   MODRM_CHECK;
15225   codep++;
15226   used_prefixes |= (prefixes & PREFIX_DATA);
15227   reg = modrm.rm;
15228   if (prefixes & PREFIX_DATA)
15229     {
15230       names = names_xmm;
15231       USED_REX (REX_B);
15232       if (rex & REX_B)
15233         reg += 8;
15234     }
15235   else
15236     names = names_mm;
15237   oappend (names[reg]);
15238 }
15239
15240 /* cvt* are the only instructions in sse2 which have
15241    both SSE and MMX operands and also have 0x66 prefix
15242    in their opcode. 0x66 was originally used to differentiate
15243    between SSE and MMX instruction(operands). So we have to handle the
15244    cvt* separately using OP_EMC and OP_MXC */
15245 static void
15246 OP_EMC (int bytemode, int sizeflag)
15247 {
15248   if (modrm.mod != 3)
15249     {
15250       if (intel_syntax && bytemode == v_mode)
15251         {
15252           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15253           used_prefixes |= (prefixes & PREFIX_DATA);
15254         }
15255       OP_E (bytemode, sizeflag);
15256       return;
15257     }
15258
15259   /* Skip mod/rm byte.  */
15260   MODRM_CHECK;
15261   codep++;
15262   used_prefixes |= (prefixes & PREFIX_DATA);
15263   oappend (names_mm[modrm.rm]);
15264 }
15265
15266 static void
15267 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15268 {
15269   used_prefixes |= (prefixes & PREFIX_DATA);
15270   oappend (names_mm[modrm.reg]);
15271 }
15272
15273 static void
15274 OP_EX (int bytemode, int sizeflag)
15275 {
15276   int reg;
15277   const char **names;
15278
15279   /* Skip mod/rm byte.  */
15280   MODRM_CHECK;
15281   codep++;
15282
15283   if (modrm.mod != 3)
15284     {
15285       OP_E_memory (bytemode, sizeflag);
15286       return;
15287     }
15288
15289   reg = modrm.rm;
15290   USED_REX (REX_B);
15291   if (rex & REX_B)
15292     reg += 8;
15293   if (vex.evex)
15294     {
15295       USED_REX (REX_X);
15296       if ((rex & REX_X))
15297         reg += 16;
15298     }
15299
15300   if ((sizeflag & SUFFIX_ALWAYS)
15301       && (bytemode == x_swap_mode
15302           || bytemode == d_swap_mode
15303           || bytemode == d_scalar_swap_mode
15304           || bytemode == q_swap_mode
15305           || bytemode == q_scalar_swap_mode))
15306     swap_operand ();
15307
15308   if (need_vex
15309       && bytemode != xmm_mode
15310       && bytemode != xmmdw_mode
15311       && bytemode != xmmqd_mode
15312       && bytemode != xmm_mb_mode
15313       && bytemode != xmm_mw_mode
15314       && bytemode != xmm_md_mode
15315       && bytemode != xmm_mq_mode
15316       && bytemode != xmm_mdq_mode
15317       && bytemode != xmmq_mode
15318       && bytemode != evex_half_bcst_xmmq_mode
15319       && bytemode != ymm_mode
15320       && bytemode != d_scalar_mode
15321       && bytemode != d_scalar_swap_mode
15322       && bytemode != q_scalar_mode
15323       && bytemode != q_scalar_swap_mode
15324       && bytemode != vex_scalar_w_dq_mode)
15325     {
15326       switch (vex.length)
15327         {
15328         case 128:
15329           names = names_xmm;
15330           break;
15331         case 256:
15332           names = names_ymm;
15333           break;
15334         case 512:
15335           names = names_zmm;
15336           break;
15337         default:
15338           abort ();
15339         }
15340     }
15341   else if (bytemode == xmmq_mode
15342            || bytemode == evex_half_bcst_xmmq_mode)
15343     {
15344       switch (vex.length)
15345         {
15346         case 128:
15347         case 256:
15348           names = names_xmm;
15349           break;
15350         case 512:
15351           names = names_ymm;
15352           break;
15353         default:
15354           abort ();
15355         }
15356     }
15357   else if (bytemode == ymm_mode)
15358     names = names_ymm;
15359   else
15360     names = names_xmm;
15361   oappend (names[reg]);
15362 }
15363
15364 static void
15365 OP_MS (int bytemode, int sizeflag)
15366 {
15367   if (modrm.mod == 3)
15368     OP_EM (bytemode, sizeflag);
15369   else
15370     BadOp ();
15371 }
15372
15373 static void
15374 OP_XS (int bytemode, int sizeflag)
15375 {
15376   if (modrm.mod == 3)
15377     OP_EX (bytemode, sizeflag);
15378   else
15379     BadOp ();
15380 }
15381
15382 static void
15383 OP_M (int bytemode, int sizeflag)
15384 {
15385   if (modrm.mod == 3)
15386     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15387     BadOp ();
15388   else
15389     OP_E (bytemode, sizeflag);
15390 }
15391
15392 static void
15393 OP_0f07 (int bytemode, int sizeflag)
15394 {
15395   if (modrm.mod != 3 || modrm.rm != 0)
15396     BadOp ();
15397   else
15398     OP_E (bytemode, sizeflag);
15399 }
15400
15401 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15402    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15403
15404 static void
15405 NOP_Fixup1 (int bytemode, int sizeflag)
15406 {
15407   if ((prefixes & PREFIX_DATA) != 0
15408       || (rex != 0
15409           && rex != 0x48
15410           && address_mode == mode_64bit))
15411     OP_REG (bytemode, sizeflag);
15412   else
15413     strcpy (obuf, "nop");
15414 }
15415
15416 static void
15417 NOP_Fixup2 (int bytemode, int sizeflag)
15418 {
15419   if ((prefixes & PREFIX_DATA) != 0
15420       || (rex != 0
15421           && rex != 0x48
15422           && address_mode == mode_64bit))
15423     OP_IMREG (bytemode, sizeflag);
15424 }
15425
15426 static const char *const Suffix3DNow[] = {
15427 /* 00 */        NULL,           NULL,           NULL,           NULL,
15428 /* 04 */        NULL,           NULL,           NULL,           NULL,
15429 /* 08 */        NULL,           NULL,           NULL,           NULL,
15430 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15431 /* 10 */        NULL,           NULL,           NULL,           NULL,
15432 /* 14 */        NULL,           NULL,           NULL,           NULL,
15433 /* 18 */        NULL,           NULL,           NULL,           NULL,
15434 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15435 /* 20 */        NULL,           NULL,           NULL,           NULL,
15436 /* 24 */        NULL,           NULL,           NULL,           NULL,
15437 /* 28 */        NULL,           NULL,           NULL,           NULL,
15438 /* 2C */        NULL,           NULL,           NULL,           NULL,
15439 /* 30 */        NULL,           NULL,           NULL,           NULL,
15440 /* 34 */        NULL,           NULL,           NULL,           NULL,
15441 /* 38 */        NULL,           NULL,           NULL,           NULL,
15442 /* 3C */        NULL,           NULL,           NULL,           NULL,
15443 /* 40 */        NULL,           NULL,           NULL,           NULL,
15444 /* 44 */        NULL,           NULL,           NULL,           NULL,
15445 /* 48 */        NULL,           NULL,           NULL,           NULL,
15446 /* 4C */        NULL,           NULL,           NULL,           NULL,
15447 /* 50 */        NULL,           NULL,           NULL,           NULL,
15448 /* 54 */        NULL,           NULL,           NULL,           NULL,
15449 /* 58 */        NULL,           NULL,           NULL,           NULL,
15450 /* 5C */        NULL,           NULL,           NULL,           NULL,
15451 /* 60 */        NULL,           NULL,           NULL,           NULL,
15452 /* 64 */        NULL,           NULL,           NULL,           NULL,
15453 /* 68 */        NULL,           NULL,           NULL,           NULL,
15454 /* 6C */        NULL,           NULL,           NULL,           NULL,
15455 /* 70 */        NULL,           NULL,           NULL,           NULL,
15456 /* 74 */        NULL,           NULL,           NULL,           NULL,
15457 /* 78 */        NULL,           NULL,           NULL,           NULL,
15458 /* 7C */        NULL,           NULL,           NULL,           NULL,
15459 /* 80 */        NULL,           NULL,           NULL,           NULL,
15460 /* 84 */        NULL,           NULL,           NULL,           NULL,
15461 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15462 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15463 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15464 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15465 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15466 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15467 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15468 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15469 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15470 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15471 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15472 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15473 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15474 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15475 /* C0 */        NULL,           NULL,           NULL,           NULL,
15476 /* C4 */        NULL,           NULL,           NULL,           NULL,
15477 /* C8 */        NULL,           NULL,           NULL,           NULL,
15478 /* CC */        NULL,           NULL,           NULL,           NULL,
15479 /* D0 */        NULL,           NULL,           NULL,           NULL,
15480 /* D4 */        NULL,           NULL,           NULL,           NULL,
15481 /* D8 */        NULL,           NULL,           NULL,           NULL,
15482 /* DC */        NULL,           NULL,           NULL,           NULL,
15483 /* E0 */        NULL,           NULL,           NULL,           NULL,
15484 /* E4 */        NULL,           NULL,           NULL,           NULL,
15485 /* E8 */        NULL,           NULL,           NULL,           NULL,
15486 /* EC */        NULL,           NULL,           NULL,           NULL,
15487 /* F0 */        NULL,           NULL,           NULL,           NULL,
15488 /* F4 */        NULL,           NULL,           NULL,           NULL,
15489 /* F8 */        NULL,           NULL,           NULL,           NULL,
15490 /* FC */        NULL,           NULL,           NULL,           NULL,
15491 };
15492
15493 static void
15494 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15495 {
15496   const char *mnemonic;
15497
15498   FETCH_DATA (the_info, codep + 1);
15499   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15500      place where an 8-bit immediate would normally go.  ie. the last
15501      byte of the instruction.  */
15502   obufp = mnemonicendp;
15503   mnemonic = Suffix3DNow[*codep++ & 0xff];
15504   if (mnemonic)
15505     oappend (mnemonic);
15506   else
15507     {
15508       /* Since a variable sized modrm/sib chunk is between the start
15509          of the opcode (0x0f0f) and the opcode suffix, we need to do
15510          all the modrm processing first, and don't know until now that
15511          we have a bad opcode.  This necessitates some cleaning up.  */
15512       op_out[0][0] = '\0';
15513       op_out[1][0] = '\0';
15514       BadOp ();
15515     }
15516   mnemonicendp = obufp;
15517 }
15518
15519 static struct op simd_cmp_op[] =
15520 {
15521   { STRING_COMMA_LEN ("eq") },
15522   { STRING_COMMA_LEN ("lt") },
15523   { STRING_COMMA_LEN ("le") },
15524   { STRING_COMMA_LEN ("unord") },
15525   { STRING_COMMA_LEN ("neq") },
15526   { STRING_COMMA_LEN ("nlt") },
15527   { STRING_COMMA_LEN ("nle") },
15528   { STRING_COMMA_LEN ("ord") }
15529 };
15530
15531 static void
15532 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15533 {
15534   unsigned int cmp_type;
15535
15536   FETCH_DATA (the_info, codep + 1);
15537   cmp_type = *codep++ & 0xff;
15538   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15539     {
15540       char suffix [3];
15541       char *p = mnemonicendp - 2;
15542       suffix[0] = p[0];
15543       suffix[1] = p[1];
15544       suffix[2] = '\0';
15545       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15546       mnemonicendp += simd_cmp_op[cmp_type].len;
15547     }
15548   else
15549     {
15550       /* We have a reserved extension byte.  Output it directly.  */
15551       scratchbuf[0] = '$';
15552       print_operand_value (scratchbuf + 1, 1, cmp_type);
15553       oappend_maybe_intel (scratchbuf);
15554       scratchbuf[0] = '\0';
15555     }
15556 }
15557
15558 static void
15559 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
15560           int sizeflag ATTRIBUTE_UNUSED)
15561 {
15562   /* mwaitx %eax,%ecx,%ebx */
15563   if (!intel_syntax)
15564     {
15565       const char **names = (address_mode == mode_64bit
15566                             ? names64 : names32);
15567       strcpy (op_out[0], names[0]);
15568       strcpy (op_out[1], names[1]);
15569       strcpy (op_out[2], names[3]);
15570       two_source_ops = 1;
15571     }
15572   /* Skip mod/rm byte.  */
15573   MODRM_CHECK;
15574   codep++;
15575 }
15576
15577 static void
15578 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15579           int sizeflag ATTRIBUTE_UNUSED)
15580 {
15581   /* mwait %eax,%ecx  */
15582   if (!intel_syntax)
15583     {
15584       const char **names = (address_mode == mode_64bit
15585                             ? names64 : names32);
15586       strcpy (op_out[0], names[0]);
15587       strcpy (op_out[1], names[1]);
15588       two_source_ops = 1;
15589     }
15590   /* Skip mod/rm byte.  */
15591   MODRM_CHECK;
15592   codep++;
15593 }
15594
15595 static void
15596 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15597             int sizeflag ATTRIBUTE_UNUSED)
15598 {
15599   /* monitor %eax,%ecx,%edx"  */
15600   if (!intel_syntax)
15601     {
15602       const char **op1_names;
15603       const char **names = (address_mode == mode_64bit
15604                             ? names64 : names32);
15605
15606       if (!(prefixes & PREFIX_ADDR))
15607         op1_names = (address_mode == mode_16bit
15608                      ? names16 : names);
15609       else
15610         {
15611           /* Remove "addr16/addr32".  */
15612           all_prefixes[last_addr_prefix] = 0;
15613           op1_names = (address_mode != mode_32bit
15614                        ? names32 : names16);
15615           used_prefixes |= PREFIX_ADDR;
15616         }
15617       strcpy (op_out[0], op1_names[0]);
15618       strcpy (op_out[1], names[1]);
15619       strcpy (op_out[2], names[2]);
15620       two_source_ops = 1;
15621     }
15622   /* Skip mod/rm byte.  */
15623   MODRM_CHECK;
15624   codep++;
15625 }
15626
15627 static void
15628 BadOp (void)
15629 {
15630   /* Throw away prefixes and 1st. opcode byte.  */
15631   codep = insn_codep + 1;
15632   oappend ("(bad)");
15633 }
15634
15635 static void
15636 REP_Fixup (int bytemode, int sizeflag)
15637 {
15638   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15639      lods and stos.  */
15640   if (prefixes & PREFIX_REPZ)
15641     all_prefixes[last_repz_prefix] = REP_PREFIX;
15642
15643   switch (bytemode)
15644     {
15645     case al_reg:
15646     case eAX_reg:
15647     case indir_dx_reg:
15648       OP_IMREG (bytemode, sizeflag);
15649       break;
15650     case eDI_reg:
15651       OP_ESreg (bytemode, sizeflag);
15652       break;
15653     case eSI_reg:
15654       OP_DSreg (bytemode, sizeflag);
15655       break;
15656     default:
15657       abort ();
15658       break;
15659     }
15660 }
15661
15662 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15663    "bnd".  */
15664
15665 static void
15666 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15667 {
15668   if (prefixes & PREFIX_REPNZ)
15669     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15670 }
15671
15672 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15673    "notrack".  */
15674
15675 static void
15676 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15677                int sizeflag ATTRIBUTE_UNUSED)
15678 {
15679   if (active_seg_prefix == PREFIX_DS
15680       && (address_mode != mode_64bit || last_data_prefix < 0))
15681     {
15682       /* NOTRACK prefix is only valid on indirect branch instructions.
15683          NB: DATA prefix is unsupported for Intel64.  */
15684       active_seg_prefix = 0;
15685       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15686     }
15687 }
15688
15689 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15690    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15691  */
15692
15693 static void
15694 HLE_Fixup1 (int bytemode, int sizeflag)
15695 {
15696   if (modrm.mod != 3
15697       && (prefixes & PREFIX_LOCK) != 0)
15698     {
15699       if (prefixes & PREFIX_REPZ)
15700         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15701       if (prefixes & PREFIX_REPNZ)
15702         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15703     }
15704
15705   OP_E (bytemode, sizeflag);
15706 }
15707
15708 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15709    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15710  */
15711
15712 static void
15713 HLE_Fixup2 (int bytemode, int sizeflag)
15714 {
15715   if (modrm.mod != 3)
15716     {
15717       if (prefixes & PREFIX_REPZ)
15718         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15719       if (prefixes & PREFIX_REPNZ)
15720         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15721     }
15722
15723   OP_E (bytemode, sizeflag);
15724 }
15725
15726 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15727    "xrelease" for memory operand.  No check for LOCK prefix.   */
15728
15729 static void
15730 HLE_Fixup3 (int bytemode, int sizeflag)
15731 {
15732   if (modrm.mod != 3
15733       && last_repz_prefix > last_repnz_prefix
15734       && (prefixes & PREFIX_REPZ) != 0)
15735     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15736
15737   OP_E (bytemode, sizeflag);
15738 }
15739
15740 static void
15741 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15742 {
15743   USED_REX (REX_W);
15744   if (rex & REX_W)
15745     {
15746       /* Change cmpxchg8b to cmpxchg16b.  */
15747       char *p = mnemonicendp - 2;
15748       mnemonicendp = stpcpy (p, "16b");
15749       bytemode = o_mode;
15750     }
15751   else if ((prefixes & PREFIX_LOCK) != 0)
15752     {
15753       if (prefixes & PREFIX_REPZ)
15754         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15755       if (prefixes & PREFIX_REPNZ)
15756         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15757     }
15758
15759   OP_M (bytemode, sizeflag);
15760 }
15761
15762 static void
15763 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15764 {
15765   const char **names;
15766
15767   if (need_vex)
15768     {
15769       switch (vex.length)
15770         {
15771         case 128:
15772           names = names_xmm;
15773           break;
15774         case 256:
15775           names = names_ymm;
15776           break;
15777         default:
15778           abort ();
15779         }
15780     }
15781   else
15782     names = names_xmm;
15783   oappend (names[reg]);
15784 }
15785
15786 static void
15787 CRC32_Fixup (int bytemode, int sizeflag)
15788 {
15789   /* Add proper suffix to "crc32".  */
15790   char *p = mnemonicendp;
15791
15792   switch (bytemode)
15793     {
15794     case b_mode:
15795       if (intel_syntax)
15796         goto skip;
15797
15798       *p++ = 'b';
15799       break;
15800     case v_mode:
15801       if (intel_syntax)
15802         goto skip;
15803
15804       USED_REX (REX_W);
15805       if (rex & REX_W)
15806         *p++ = 'q';
15807       else
15808         {
15809           if (sizeflag & DFLAG)
15810             *p++ = 'l';
15811           else
15812             *p++ = 'w';
15813           used_prefixes |= (prefixes & PREFIX_DATA);
15814         }
15815       break;
15816     default:
15817       oappend (INTERNAL_DISASSEMBLER_ERROR);
15818       break;
15819     }
15820   mnemonicendp = p;
15821   *p = '\0';
15822
15823 skip:
15824   if (modrm.mod == 3)
15825     {
15826       int add;
15827
15828       /* Skip mod/rm byte.  */
15829       MODRM_CHECK;
15830       codep++;
15831
15832       USED_REX (REX_B);
15833       add = (rex & REX_B) ? 8 : 0;
15834       if (bytemode == b_mode)
15835         {
15836           USED_REX (0);
15837           if (rex)
15838             oappend (names8rex[modrm.rm + add]);
15839           else
15840             oappend (names8[modrm.rm + add]);
15841         }
15842       else
15843         {
15844           USED_REX (REX_W);
15845           if (rex & REX_W)
15846             oappend (names64[modrm.rm + add]);
15847           else if ((prefixes & PREFIX_DATA))
15848             oappend (names16[modrm.rm + add]);
15849           else
15850             oappend (names32[modrm.rm + add]);
15851         }
15852     }
15853   else
15854     OP_E (bytemode, sizeflag);
15855 }
15856
15857 static void
15858 FXSAVE_Fixup (int bytemode, int sizeflag)
15859 {
15860   /* Add proper suffix to "fxsave" and "fxrstor".  */
15861   USED_REX (REX_W);
15862   if (rex & REX_W)
15863     {
15864       char *p = mnemonicendp;
15865       *p++ = '6';
15866       *p++ = '4';
15867       *p = '\0';
15868       mnemonicendp = p;
15869     }
15870   OP_M (bytemode, sizeflag);
15871 }
15872
15873 static void
15874 PCMPESTR_Fixup (int bytemode, int sizeflag)
15875 {
15876   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15877   if (!intel_syntax)
15878     {
15879       char *p = mnemonicendp;
15880
15881       USED_REX (REX_W);
15882       if (rex & REX_W)
15883         *p++ = 'q';
15884       else if (sizeflag & SUFFIX_ALWAYS)
15885         *p++ = 'l';
15886
15887       *p = '\0';
15888       mnemonicendp = p;
15889     }
15890
15891   OP_EX (bytemode, sizeflag);
15892 }
15893
15894 /* Display the destination register operand for instructions with
15895    VEX. */
15896
15897 static void
15898 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15899 {
15900   int reg;
15901   const char **names;
15902
15903   if (!need_vex)
15904     abort ();
15905
15906   if (!need_vex_reg)
15907     return;
15908
15909   reg = vex.register_specifier;
15910   if (address_mode != mode_64bit)
15911     reg &= 7;
15912   else if (vex.evex && !vex.v)
15913     reg += 16;
15914
15915   if (bytemode == vex_scalar_mode)
15916     {
15917       oappend (names_xmm[reg]);
15918       return;
15919     }
15920
15921   switch (vex.length)
15922     {
15923     case 128:
15924       switch (bytemode)
15925         {
15926         case vex_mode:
15927         case vex128_mode:
15928         case vex_vsib_q_w_dq_mode:
15929         case vex_vsib_q_w_d_mode:
15930           names = names_xmm;
15931           break;
15932         case dq_mode:
15933           if (rex & REX_W)
15934             names = names64;
15935           else
15936             names = names32;
15937           break;
15938         case mask_bd_mode:
15939         case mask_mode:
15940           if (reg > 0x7)
15941             {
15942               oappend ("(bad)");
15943               return;
15944             }
15945           names = names_mask;
15946           break;
15947         default:
15948           abort ();
15949           return;
15950         }
15951       break;
15952     case 256:
15953       switch (bytemode)
15954         {
15955         case vex_mode:
15956         case vex256_mode:
15957           names = names_ymm;
15958           break;
15959         case vex_vsib_q_w_dq_mode:
15960         case vex_vsib_q_w_d_mode:
15961           names = vex.w ? names_ymm : names_xmm;
15962           break;
15963         case mask_bd_mode:
15964         case mask_mode:
15965           if (reg > 0x7)
15966             {
15967               oappend ("(bad)");
15968               return;
15969             }
15970           names = names_mask;
15971           break;
15972         default:
15973           /* See PR binutils/20893 for a reproducer.  */
15974           oappend ("(bad)");
15975           return;
15976         }
15977       break;
15978     case 512:
15979       names = names_zmm;
15980       break;
15981     default:
15982       abort ();
15983       break;
15984     }
15985   oappend (names[reg]);
15986 }
15987
15988 /* Get the VEX immediate byte without moving codep.  */
15989
15990 static unsigned char
15991 get_vex_imm8 (int sizeflag, int opnum)
15992 {
15993   int bytes_before_imm = 0;
15994
15995   if (modrm.mod != 3)
15996     {
15997       /* There are SIB/displacement bytes.  */
15998       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15999         {
16000           /* 32/64 bit address mode */
16001           int base = modrm.rm;
16002
16003           /* Check SIB byte.  */
16004           if (base == 4)
16005             {
16006               FETCH_DATA (the_info, codep + 1);
16007               base = *codep & 7;
16008               /* When decoding the third source, don't increase
16009                  bytes_before_imm as this has already been incremented
16010                  by one in OP_E_memory while decoding the second
16011                  source operand.  */
16012               if (opnum == 0)
16013                 bytes_before_imm++;
16014             }
16015
16016           /* Don't increase bytes_before_imm when decoding the third source,
16017              it has already been incremented by OP_E_memory while decoding
16018              the second source operand.  */
16019           if (opnum == 0)
16020             {
16021               switch (modrm.mod)
16022                 {
16023                   case 0:
16024                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16025                        SIB == 5, there is a 4 byte displacement.  */
16026                     if (base != 5)
16027                       /* No displacement. */
16028                       break;
16029                     /* Fall through.  */
16030                   case 2:
16031                     /* 4 byte displacement.  */
16032                     bytes_before_imm += 4;
16033                     break;
16034                   case 1:
16035                     /* 1 byte displacement.  */
16036                     bytes_before_imm++;
16037                     break;
16038                 }
16039             }
16040         }
16041       else
16042         {
16043           /* 16 bit address mode */
16044           /* Don't increase bytes_before_imm when decoding the third source,
16045              it has already been incremented by OP_E_memory while decoding
16046              the second source operand.  */
16047           if (opnum == 0)
16048             {
16049               switch (modrm.mod)
16050                 {
16051                 case 0:
16052                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16053                   if (modrm.rm != 6)
16054                     /* No displacement. */
16055                     break;
16056                   /* Fall through.  */
16057                 case 2:
16058                   /* 2 byte displacement.  */
16059                   bytes_before_imm += 2;
16060                   break;
16061                 case 1:
16062                   /* 1 byte displacement: when decoding the third source,
16063                      don't increase bytes_before_imm as this has already
16064                      been incremented by one in OP_E_memory while decoding
16065                      the second source operand.  */
16066                   if (opnum == 0)
16067                     bytes_before_imm++;
16068
16069                   break;
16070                 }
16071             }
16072         }
16073     }
16074
16075   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16076   return codep [bytes_before_imm];
16077 }
16078
16079 static void
16080 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16081 {
16082   const char **names;
16083
16084   if (reg == -1 && modrm.mod != 3)
16085     {
16086       OP_E_memory (bytemode, sizeflag);
16087       return;
16088     }
16089   else
16090     {
16091       if (reg == -1)
16092         {
16093           reg = modrm.rm;
16094           USED_REX (REX_B);
16095           if (rex & REX_B)
16096             reg += 8;
16097         }
16098       if (address_mode != mode_64bit)
16099         reg &= 7;
16100     }
16101
16102   switch (vex.length)
16103     {
16104     case 128:
16105       names = names_xmm;
16106       break;
16107     case 256:
16108       names = names_ymm;
16109       break;
16110     default:
16111       abort ();
16112     }
16113   oappend (names[reg]);
16114 }
16115
16116 static void
16117 OP_EX_VexImmW (int bytemode, int sizeflag)
16118 {
16119   int reg = -1;
16120   static unsigned char vex_imm8;
16121
16122   if (vex_w_done == 0)
16123     {
16124       vex_w_done = 1;
16125
16126       /* Skip mod/rm byte.  */
16127       MODRM_CHECK;
16128       codep++;
16129
16130       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16131
16132       if (vex.w)
16133           reg = vex_imm8 >> 4;
16134
16135       OP_EX_VexReg (bytemode, sizeflag, reg);
16136     }
16137   else if (vex_w_done == 1)
16138     {
16139       vex_w_done = 2;
16140
16141       if (!vex.w)
16142           reg = vex_imm8 >> 4;
16143
16144       OP_EX_VexReg (bytemode, sizeflag, reg);
16145     }
16146   else
16147     {
16148       /* Output the imm8 directly.  */
16149       scratchbuf[0] = '$';
16150       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16151       oappend_maybe_intel (scratchbuf);
16152       scratchbuf[0] = '\0';
16153       codep++;
16154     }
16155 }
16156
16157 static void
16158 OP_Vex_2src (int bytemode, int sizeflag)
16159 {
16160   if (modrm.mod == 3)
16161     {
16162       int reg = modrm.rm;
16163       USED_REX (REX_B);
16164       if (rex & REX_B)
16165         reg += 8;
16166       oappend (names_xmm[reg]);
16167     }
16168   else
16169     {
16170       if (intel_syntax
16171           && (bytemode == v_mode || bytemode == v_swap_mode))
16172         {
16173           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16174           used_prefixes |= (prefixes & PREFIX_DATA);
16175         }
16176       OP_E (bytemode, sizeflag);
16177     }
16178 }
16179
16180 static void
16181 OP_Vex_2src_1 (int bytemode, int sizeflag)
16182 {
16183   if (modrm.mod == 3)
16184     {
16185       /* Skip mod/rm byte.   */
16186       MODRM_CHECK;
16187       codep++;
16188     }
16189
16190   if (vex.w)
16191     {
16192       unsigned int reg = vex.register_specifier;
16193
16194       if (address_mode != mode_64bit)
16195         reg &= 7;
16196       oappend (names_xmm[reg]);
16197     }
16198   else
16199     OP_Vex_2src (bytemode, sizeflag);
16200 }
16201
16202 static void
16203 OP_Vex_2src_2 (int bytemode, int sizeflag)
16204 {
16205   if (vex.w)
16206     OP_Vex_2src (bytemode, sizeflag);
16207   else
16208     {
16209       unsigned int reg = vex.register_specifier;
16210
16211       if (address_mode != mode_64bit)
16212         reg &= 7;
16213       oappend (names_xmm[reg]);
16214     }
16215 }
16216
16217 static void
16218 OP_EX_VexW (int bytemode, int sizeflag)
16219 {
16220   int reg = -1;
16221
16222   if (!vex_w_done)
16223     {
16224       /* Skip mod/rm byte.  */
16225       MODRM_CHECK;
16226       codep++;
16227
16228       if (vex.w)
16229         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16230     }
16231   else
16232     {
16233       if (!vex.w)
16234         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16235     }
16236
16237   OP_EX_VexReg (bytemode, sizeflag, reg);
16238
16239   if (vex_w_done)
16240     codep++;
16241   vex_w_done = 1;
16242 }
16243
16244 static void
16245 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16246 {
16247   int reg;
16248   const char **names;
16249
16250   FETCH_DATA (the_info, codep + 1);
16251   reg = *codep++;
16252
16253   if (bytemode != x_mode)
16254     abort ();
16255
16256   reg >>= 4;
16257   if (address_mode != mode_64bit)
16258     reg &= 7;
16259
16260   switch (vex.length)
16261     {
16262     case 128:
16263       names = names_xmm;
16264       break;
16265     case 256:
16266       names = names_ymm;
16267       break;
16268     default:
16269       abort ();
16270     }
16271   oappend (names[reg]);
16272 }
16273
16274 static void
16275 OP_XMM_VexW (int bytemode, int sizeflag)
16276 {
16277   /* Turn off the REX.W bit since it is used for swapping operands
16278      now.  */
16279   rex &= ~REX_W;
16280   OP_XMM (bytemode, sizeflag);
16281 }
16282
16283 static void
16284 OP_EX_Vex (int bytemode, int sizeflag)
16285 {
16286   if (modrm.mod != 3)
16287     {
16288       if (vex.register_specifier != 0)
16289         BadOp ();
16290       need_vex_reg = 0;
16291     }
16292   OP_EX (bytemode, sizeflag);
16293 }
16294
16295 static void
16296 OP_XMM_Vex (int bytemode, int sizeflag)
16297 {
16298   if (modrm.mod != 3)
16299     {
16300       if (vex.register_specifier != 0)
16301         BadOp ();
16302       need_vex_reg = 0;
16303     }
16304   OP_XMM (bytemode, sizeflag);
16305 }
16306
16307 static struct op vex_cmp_op[] =
16308 {
16309   { STRING_COMMA_LEN ("eq") },
16310   { STRING_COMMA_LEN ("lt") },
16311   { STRING_COMMA_LEN ("le") },
16312   { STRING_COMMA_LEN ("unord") },
16313   { STRING_COMMA_LEN ("neq") },
16314   { STRING_COMMA_LEN ("nlt") },
16315   { STRING_COMMA_LEN ("nle") },
16316   { STRING_COMMA_LEN ("ord") },
16317   { STRING_COMMA_LEN ("eq_uq") },
16318   { STRING_COMMA_LEN ("nge") },
16319   { STRING_COMMA_LEN ("ngt") },
16320   { STRING_COMMA_LEN ("false") },
16321   { STRING_COMMA_LEN ("neq_oq") },
16322   { STRING_COMMA_LEN ("ge") },
16323   { STRING_COMMA_LEN ("gt") },
16324   { STRING_COMMA_LEN ("true") },
16325   { STRING_COMMA_LEN ("eq_os") },
16326   { STRING_COMMA_LEN ("lt_oq") },
16327   { STRING_COMMA_LEN ("le_oq") },
16328   { STRING_COMMA_LEN ("unord_s") },
16329   { STRING_COMMA_LEN ("neq_us") },
16330   { STRING_COMMA_LEN ("nlt_uq") },
16331   { STRING_COMMA_LEN ("nle_uq") },
16332   { STRING_COMMA_LEN ("ord_s") },
16333   { STRING_COMMA_LEN ("eq_us") },
16334   { STRING_COMMA_LEN ("nge_uq") },
16335   { STRING_COMMA_LEN ("ngt_uq") },
16336   { STRING_COMMA_LEN ("false_os") },
16337   { STRING_COMMA_LEN ("neq_os") },
16338   { STRING_COMMA_LEN ("ge_oq") },
16339   { STRING_COMMA_LEN ("gt_oq") },
16340   { STRING_COMMA_LEN ("true_us") },
16341 };
16342
16343 static void
16344 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16345 {
16346   unsigned int cmp_type;
16347
16348   FETCH_DATA (the_info, codep + 1);
16349   cmp_type = *codep++ & 0xff;
16350   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16351     {
16352       char suffix [3];
16353       char *p = mnemonicendp - 2;
16354       suffix[0] = p[0];
16355       suffix[1] = p[1];
16356       suffix[2] = '\0';
16357       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16358       mnemonicendp += vex_cmp_op[cmp_type].len;
16359     }
16360   else
16361     {
16362       /* We have a reserved extension byte.  Output it directly.  */
16363       scratchbuf[0] = '$';
16364       print_operand_value (scratchbuf + 1, 1, cmp_type);
16365       oappend_maybe_intel (scratchbuf);
16366       scratchbuf[0] = '\0';
16367     }
16368 }
16369
16370 static void
16371 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16372              int sizeflag ATTRIBUTE_UNUSED)
16373 {
16374   unsigned int cmp_type;
16375
16376   if (!vex.evex)
16377     abort ();
16378
16379   FETCH_DATA (the_info, codep + 1);
16380   cmp_type = *codep++ & 0xff;
16381   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16382      If it's the case, print suffix, otherwise - print the immediate.  */
16383   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16384       && cmp_type != 3
16385       && cmp_type != 7)
16386     {
16387       char suffix [3];
16388       char *p = mnemonicendp - 2;
16389
16390       /* vpcmp* can have both one- and two-lettered suffix.  */
16391       if (p[0] == 'p')
16392         {
16393           p++;
16394           suffix[0] = p[0];
16395           suffix[1] = '\0';
16396         }
16397       else
16398         {
16399           suffix[0] = p[0];
16400           suffix[1] = p[1];
16401           suffix[2] = '\0';
16402         }
16403
16404       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16405       mnemonicendp += simd_cmp_op[cmp_type].len;
16406     }
16407   else
16408     {
16409       /* We have a reserved extension byte.  Output it directly.  */
16410       scratchbuf[0] = '$';
16411       print_operand_value (scratchbuf + 1, 1, cmp_type);
16412       oappend_maybe_intel (scratchbuf);
16413       scratchbuf[0] = '\0';
16414     }
16415 }
16416
16417 static const struct op xop_cmp_op[] =
16418 {
16419   { STRING_COMMA_LEN ("lt") },
16420   { STRING_COMMA_LEN ("le") },
16421   { STRING_COMMA_LEN ("gt") },
16422   { STRING_COMMA_LEN ("ge") },
16423   { STRING_COMMA_LEN ("eq") },
16424   { STRING_COMMA_LEN ("neq") },
16425   { STRING_COMMA_LEN ("false") },
16426   { STRING_COMMA_LEN ("true") }
16427 };
16428
16429 static void
16430 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16431              int sizeflag ATTRIBUTE_UNUSED)
16432 {
16433   unsigned int cmp_type;
16434
16435   FETCH_DATA (the_info, codep + 1);
16436   cmp_type = *codep++ & 0xff;
16437   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16438     {
16439       char suffix[3];
16440       char *p = mnemonicendp - 2;
16441
16442       /* vpcom* can have both one- and two-lettered suffix.  */
16443       if (p[0] == 'm')
16444         {
16445           p++;
16446           suffix[0] = p[0];
16447           suffix[1] = '\0';
16448         }
16449       else
16450         {
16451           suffix[0] = p[0];
16452           suffix[1] = p[1];
16453           suffix[2] = '\0';
16454         }
16455
16456       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16457       mnemonicendp += xop_cmp_op[cmp_type].len;
16458     }
16459   else
16460     {
16461       /* We have a reserved extension byte.  Output it directly.  */
16462       scratchbuf[0] = '$';
16463       print_operand_value (scratchbuf + 1, 1, cmp_type);
16464       oappend_maybe_intel (scratchbuf);
16465       scratchbuf[0] = '\0';
16466     }
16467 }
16468
16469 static const struct op pclmul_op[] =
16470 {
16471   { STRING_COMMA_LEN ("lql") },
16472   { STRING_COMMA_LEN ("hql") },
16473   { STRING_COMMA_LEN ("lqh") },
16474   { STRING_COMMA_LEN ("hqh") }
16475 };
16476
16477 static void
16478 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16479               int sizeflag ATTRIBUTE_UNUSED)
16480 {
16481   unsigned int pclmul_type;
16482
16483   FETCH_DATA (the_info, codep + 1);
16484   pclmul_type = *codep++ & 0xff;
16485   switch (pclmul_type)
16486     {
16487     case 0x10:
16488       pclmul_type = 2;
16489       break;
16490     case 0x11:
16491       pclmul_type = 3;
16492       break;
16493     default:
16494       break;
16495     }
16496   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16497     {
16498       char suffix [4];
16499       char *p = mnemonicendp - 3;
16500       suffix[0] = p[0];
16501       suffix[1] = p[1];
16502       suffix[2] = p[2];
16503       suffix[3] = '\0';
16504       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16505       mnemonicendp += pclmul_op[pclmul_type].len;
16506     }
16507   else
16508     {
16509       /* We have a reserved extension byte.  Output it directly.  */
16510       scratchbuf[0] = '$';
16511       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16512       oappend_maybe_intel (scratchbuf);
16513       scratchbuf[0] = '\0';
16514     }
16515 }
16516
16517 static void
16518 MOVBE_Fixup (int bytemode, int sizeflag)
16519 {
16520   /* Add proper suffix to "movbe".  */
16521   char *p = mnemonicendp;
16522
16523   switch (bytemode)
16524     {
16525     case v_mode:
16526       if (intel_syntax)
16527         goto skip;
16528
16529       USED_REX (REX_W);
16530       if (sizeflag & SUFFIX_ALWAYS)
16531         {
16532           if (rex & REX_W)
16533             *p++ = 'q';
16534           else
16535             {
16536               if (sizeflag & DFLAG)
16537                 *p++ = 'l';
16538               else
16539                 *p++ = 'w';
16540               used_prefixes |= (prefixes & PREFIX_DATA);
16541             }
16542         }
16543       break;
16544     default:
16545       oappend (INTERNAL_DISASSEMBLER_ERROR);
16546       break;
16547     }
16548   mnemonicendp = p;
16549   *p = '\0';
16550
16551 skip:
16552   OP_M (bytemode, sizeflag);
16553 }
16554
16555 static void
16556 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16557 {
16558   int reg;
16559   const char **names;
16560
16561   /* Skip mod/rm byte.  */
16562   MODRM_CHECK;
16563   codep++;
16564
16565   if (rex & REX_W)
16566     names = names64;
16567   else
16568     names = names32;
16569
16570   reg = modrm.rm;
16571   USED_REX (REX_B);
16572   if (rex & REX_B)
16573     reg += 8;
16574
16575   oappend (names[reg]);
16576 }
16577
16578 static void
16579 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16580 {
16581   const char **names;
16582   unsigned int reg = vex.register_specifier;
16583
16584   if (rex & REX_W)
16585     names = names64;
16586   else
16587     names = names32;
16588
16589   if (address_mode != mode_64bit)
16590     reg &= 7;
16591   oappend (names[reg]);
16592 }
16593
16594 static void
16595 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16596 {
16597   if (!vex.evex
16598       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16599     abort ();
16600
16601   USED_REX (REX_R);
16602   if ((rex & REX_R) != 0 || !vex.r)
16603     {
16604       BadOp ();
16605       return;
16606     }
16607
16608   oappend (names_mask [modrm.reg]);
16609 }
16610
16611 static void
16612 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16613 {
16614   if (!vex.evex
16615       || (bytemode != evex_rounding_mode
16616           && bytemode != evex_rounding_64_mode
16617           && bytemode != evex_sae_mode))
16618     abort ();
16619   if (modrm.mod == 3 && vex.b)
16620     switch (bytemode)
16621       {
16622       case evex_rounding_64_mode:
16623         if (address_mode != mode_64bit)
16624           {
16625             oappend ("(bad)");
16626             break;
16627           }
16628         /* Fall through.  */
16629       case evex_rounding_mode:
16630         oappend (names_rounding[vex.ll]);
16631         break;
16632       case evex_sae_mode:
16633         oappend ("{sae}");
16634         break;
16635       default:
16636         break;
16637       }
16638 }