opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2014 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void OP_LWPCB_E (int, int);
 120 static void OP_LWP_E (int, int);
 121 static void OP_Vex_2src_1 (int, int);
 122 static void OP_Vex_2src_2 (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125
 126 static void OP_Mask (int, int);
 127
 128 struct dis_private {
 129   /* Points to first byte not fetched.  */
 130   bfd_byte *max_fetched;
 131   bfd_byte the_buffer[MAX_MNEM_SIZE];
 132   bfd_vma insn_start;
 133   int orig_sizeflag;
 134   OPCODES_SIGJMP_BUF bailout;
 135 };
 136
 137 enum address_mode
 138 {
 139   mode_16bit,
 140   mode_32bit,
 141   mode_64bit
 142 };
 143
 144 enum address_mode address_mode;
 145
 146 /* Flags for the prefixes for the current instruction.  See below.  */
 147 static int prefixes;
 148
 149 /* REX prefix the current instruction.  See below.  */
 150 static int rex;
 151 /* Bits of REX we've already used.  */
 152 static int rex_used;
 153 /* REX bits in original REX prefix ignored.  */
 154 static int rex_ignored;
 155 /* Mark parts used in the REX prefix.  When we are testing for
 156    empty prefix (for 8bit register REX extension), just mask it
 157    out.  Otherwise test for REX bit is excuse for existence of REX
 158    only in case value is nonzero.  */
 159 #define USED_REX(value)                                 \
 160   {                                                     \
 161     if (value)                                          \
 162       {                                                 \
 163         if ((rex & value))                              \
 164           rex_used |= (value) | REX_OPCODE;             \
 165       }                                                 \
 166     else                                                \
 167       rex_used |= REX_OPCODE;                           \
 168   }
 169
 170 /* Flags for prefixes which we somehow handled when printing the
 171    current instruction.  */
 172 static int used_prefixes;
 173
 174 /* Flags stored in PREFIXES.  */
 175 #define PREFIX_REPZ 1
 176 #define PREFIX_REPNZ 2
 177 #define PREFIX_LOCK 4
 178 #define PREFIX_CS 8
 179 #define PREFIX_SS 0x10
 180 #define PREFIX_DS 0x20
 181 #define PREFIX_ES 0x40
 182 #define PREFIX_FS 0x80
 183 #define PREFIX_GS 0x100
 184 #define PREFIX_DATA 0x200
 185 #define PREFIX_ADDR 0x400
 186 #define PREFIX_FWAIT 0x800
 187
 188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 189    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 190    on error.  */
 191 #define FETCH_DATA(info, addr) \
 192   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 193    ? 1 : fetch_data ((info), (addr)))
 194
 195 static int
 196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 197 {
 198   int status;
 199   struct dis_private *priv = (struct dis_private *) info->private_data;
 200   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 201
 202   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 203     status = (*info->read_memory_func) (start,
 204                                         priv->max_fetched,
 205                                         addr - priv->max_fetched,
 206                                         info);
 207   else
 208     status = -1;
 209   if (status != 0)
 210     {
 211       /* If we did manage to read at least one byte, then
 212          print_insn_i386 will do something sensible.  Otherwise, print
 213          an error.  We do that here because this is where we know
 214          STATUS.  */
 215       if (priv->max_fetched == priv->the_buffer)
 216         (*info->memory_error_func) (status, start, info);
 217       OPCODES_SIGLONGJMP (priv->bailout, 1);
 218     }
 219   else
 220     priv->max_fetched = addr;
 221   return 1;
 222 }
 223
 224 #define XX { NULL, 0 }
 225 #define Bad_Opcode NULL, { { NULL, 0 } }
 226
 227 #define Eb { OP_E, b_mode }
 228 #define Ebnd { OP_E, bnd_mode }
 229 #define EbS { OP_E, b_swap_mode }
 230 #define Ev { OP_E, v_mode }
 231 #define Ev_bnd { OP_E, v_bnd_mode }
 232 #define EvS { OP_E, v_swap_mode }
 233 #define Ed { OP_E, d_mode }
 234 #define Edq { OP_E, dq_mode }
 235 #define Edqw { OP_E, dqw_mode }
 236 #define EdqwS { OP_E, dqw_swap_mode }
 237 #define Edqb { OP_E, dqb_mode }
 238 #define Edb { OP_E, db_mode }
 239 #define Edw { OP_E, dw_mode }
 240 #define Edqd { OP_E, dqd_mode }
 241 #define Eq { OP_E, q_mode }
 242 #define indirEv { OP_indirE, stack_v_mode }
 243 #define indirEp { OP_indirE, f_mode }
 244 #define stackEv { OP_E, stack_v_mode }
 245 #define Em { OP_E, m_mode }
 246 #define Ew { OP_E, w_mode }
 247 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 248 #define Ma { OP_M, a_mode }
 249 #define Mb { OP_M, b_mode }
 250 #define Md { OP_M, d_mode }
 251 #define Mo { OP_M, o_mode }
 252 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 253 #define Mq { OP_M, q_mode }
 254 #define Mx { OP_M, x_mode }
 255 #define Mxmm { OP_M, xmm_mode }
 256 #define Gb { OP_G, b_mode }
 257 #define Gbnd { OP_G, bnd_mode }
 258 #define Gv { OP_G, v_mode }
 259 #define Gd { OP_G, d_mode }
 260 #define Gdq { OP_G, dq_mode }
 261 #define Gm { OP_G, m_mode }
 262 #define Gw { OP_G, w_mode }
 263 #define Rd { OP_R, d_mode }
 264 #define Rdq { OP_R, dq_mode }
 265 #define Rm { OP_R, m_mode }
 266 #define Ib { OP_I, b_mode }
 267 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 268 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 269 #define Iv { OP_I, v_mode }
 270 #define sIv { OP_sI, v_mode }
 271 #define Iq { OP_I, q_mode }
 272 #define Iv64 { OP_I64, v_mode }
 273 #define Iw { OP_I, w_mode }
 274 #define I1 { OP_I, const_1_mode }
 275 #define Jb { OP_J, b_mode }
 276 #define Jv { OP_J, v_mode }
 277 #define Cm { OP_C, m_mode }
 278 #define Dm { OP_D, m_mode }
 279 #define Td { OP_T, d_mode }
 280 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 281
 282 #define RMeAX { OP_REG, eAX_reg }
 283 #define RMeBX { OP_REG, eBX_reg }
 284 #define RMeCX { OP_REG, eCX_reg }
 285 #define RMeDX { OP_REG, eDX_reg }
 286 #define RMeSP { OP_REG, eSP_reg }
 287 #define RMeBP { OP_REG, eBP_reg }
 288 #define RMeSI { OP_REG, eSI_reg }
 289 #define RMeDI { OP_REG, eDI_reg }
 290 #define RMrAX { OP_REG, rAX_reg }
 291 #define RMrBX { OP_REG, rBX_reg }
 292 #define RMrCX { OP_REG, rCX_reg }
 293 #define RMrDX { OP_REG, rDX_reg }
 294 #define RMrSP { OP_REG, rSP_reg }
 295 #define RMrBP { OP_REG, rBP_reg }
 296 #define RMrSI { OP_REG, rSI_reg }
 297 #define RMrDI { OP_REG, rDI_reg }
 298 #define RMAL { OP_REG, al_reg }
 299 #define RMCL { OP_REG, cl_reg }
 300 #define RMDL { OP_REG, dl_reg }
 301 #define RMBL { OP_REG, bl_reg }
 302 #define RMAH { OP_REG, ah_reg }
 303 #define RMCH { OP_REG, ch_reg }
 304 #define RMDH { OP_REG, dh_reg }
 305 #define RMBH { OP_REG, bh_reg }
 306 #define RMAX { OP_REG, ax_reg }
 307 #define RMDX { OP_REG, dx_reg }
 308
 309 #define eAX { OP_IMREG, eAX_reg }
 310 #define eBX { OP_IMREG, eBX_reg }
 311 #define eCX { OP_IMREG, eCX_reg }
 312 #define eDX { OP_IMREG, eDX_reg }
 313 #define eSP { OP_IMREG, eSP_reg }
 314 #define eBP { OP_IMREG, eBP_reg }
 315 #define eSI { OP_IMREG, eSI_reg }
 316 #define eDI { OP_IMREG, eDI_reg }
 317 #define AL { OP_IMREG, al_reg }
 318 #define CL { OP_IMREG, cl_reg }
 319 #define DL { OP_IMREG, dl_reg }
 320 #define BL { OP_IMREG, bl_reg }
 321 #define AH { OP_IMREG, ah_reg }
 322 #define CH { OP_IMREG, ch_reg }
 323 #define DH { OP_IMREG, dh_reg }
 324 #define BH { OP_IMREG, bh_reg }
 325 #define AX { OP_IMREG, ax_reg }
 326 #define DX { OP_IMREG, dx_reg }
 327 #define zAX { OP_IMREG, z_mode_ax_reg }
 328 #define indirDX { OP_IMREG, indir_dx_reg }
 329
 330 #define Sw { OP_SEG, w_mode }
 331 #define Sv { OP_SEG, v_mode }
 332 #define Ap { OP_DIR, 0 }
 333 #define Ob { OP_OFF64, b_mode }
 334 #define Ov { OP_OFF64, v_mode }
 335 #define Xb { OP_DSreg, eSI_reg }
 336 #define Xv { OP_DSreg, eSI_reg }
 337 #define Xz { OP_DSreg, eSI_reg }
 338 #define Yb { OP_ESreg, eDI_reg }
 339 #define Yv { OP_ESreg, eDI_reg }
 340 #define DSBX { OP_DSreg, eBX_reg }
 341
 342 #define es { OP_REG, es_reg }
 343 #define ss { OP_REG, ss_reg }
 344 #define cs { OP_REG, cs_reg }
 345 #define ds { OP_REG, ds_reg }
 346 #define fs { OP_REG, fs_reg }
 347 #define gs { OP_REG, gs_reg }
 348
 349 #define MX { OP_MMX, 0 }
 350 #define XM { OP_XMM, 0 }
 351 #define XMScalar { OP_XMM, scalar_mode }
 352 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 353 #define XMM { OP_XMM, xmm_mode }
 354 #define XMxmmq { OP_XMM, xmmq_mode }
 355 #define EM { OP_EM, v_mode }
 356 #define EMS { OP_EM, v_swap_mode }
 357 #define EMd { OP_EM, d_mode }
 358 #define EMx { OP_EM, x_mode }
 359 #define EXw { OP_EX, w_mode }
 360 #define EXd { OP_EX, d_mode }
 361 #define EXdScalar { OP_EX, d_scalar_mode }
 362 #define EXdS { OP_EX, d_swap_mode }
 363 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 364 #define EXq { OP_EX, q_mode }
 365 #define EXqScalar { OP_EX, q_scalar_mode }
 366 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 367 #define EXqS { OP_EX, q_swap_mode }
 368 #define EXx { OP_EX, x_mode }
 369 #define EXxS { OP_EX, x_swap_mode }
 370 #define EXxmm { OP_EX, xmm_mode }
 371 #define EXymm { OP_EX, ymm_mode }
 372 #define EXxmmq { OP_EX, xmmq_mode }
 373 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 374 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 375 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 376 #define EXxmm_md { OP_EX, xmm_md_mode }
 377 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 378 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 379 #define EXxmmdw { OP_EX, xmmdw_mode }
 380 #define EXxmmqd { OP_EX, xmmqd_mode }
 381 #define EXymmq { OP_EX, ymmq_mode }
 382 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 383 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 384 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 385 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 386 #define MS { OP_MS, v_mode }
 387 #define XS { OP_XS, v_mode }
 388 #define EMCq { OP_EMC, q_mode }
 389 #define MXC { OP_MXC, 0 }
 390 #define OPSUF { OP_3DNowSuffix, 0 }
 391 #define CMP { CMP_Fixup, 0 }
 392 #define XMM0 { XMM_Fixup, 0 }
 393 #define FXSAVE { FXSAVE_Fixup, 0 }
 394 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 395 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 396
 397 #define Vex { OP_VEX, vex_mode }
 398 #define VexScalar { OP_VEX, vex_scalar_mode }
 399 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 400 #define Vex128 { OP_VEX, vex128_mode }
 401 #define Vex256 { OP_VEX, vex256_mode }
 402 #define VexGdq { OP_VEX, dq_mode }
 403 #define VexI4 { VEXI4_Fixup, 0}
 404 #define EXdVex { OP_EX_Vex, d_mode }
 405 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 406 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 407 #define EXqVex { OP_EX_Vex, q_mode }
 408 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 409 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 410 #define EXVexW { OP_EX_VexW, x_mode }
 411 #define EXdVexW { OP_EX_VexW, d_mode }
 412 #define EXqVexW { OP_EX_VexW, q_mode }
 413 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 414 #define XMVex { OP_XMM_Vex, 0 }
 415 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 416 #define XMVexW { OP_XMM_VexW, 0 }
 417 #define XMVexI4 { OP_REG_VexI4, x_mode }
 418 #define PCLMUL { PCLMUL_Fixup, 0 }
 419 #define VZERO { VZERO_Fixup, 0 }
 420 #define VCMP { VCMP_Fixup, 0 }
 421 #define VPCMP { VPCMP_Fixup, 0 }
 422
 423 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 424 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 425
 426 #define XMask { OP_Mask, mask_mode }
 427 #define MaskG { OP_G, mask_mode }
 428 #define MaskE { OP_E, mask_mode }
 429 #define MaskBDE { OP_E, mask_bd_mode }
 430 #define MaskR { OP_R, mask_mode }
 431 #define MaskVex { OP_VEX, mask_mode }
 432
 433 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 434 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 435 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 436 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 437
 438 /* Used handle "rep" prefix for string instructions.  */
 439 #define Xbr { REP_Fixup, eSI_reg }
 440 #define Xvr { REP_Fixup, eSI_reg }
 441 #define Ybr { REP_Fixup, eDI_reg }
 442 #define Yvr { REP_Fixup, eDI_reg }
 443 #define Yzr { REP_Fixup, eDI_reg }
 444 #define indirDXr { REP_Fixup, indir_dx_reg }
 445 #define ALr { REP_Fixup, al_reg }
 446 #define eAXr { REP_Fixup, eAX_reg }
 447
 448 /* Used handle HLE prefix for lockable instructions.  */
 449 #define Ebh1 { HLE_Fixup1, b_mode }
 450 #define Evh1 { HLE_Fixup1, v_mode }
 451 #define Ebh2 { HLE_Fixup2, b_mode }
 452 #define Evh2 { HLE_Fixup2, v_mode }
 453 #define Ebh3 { HLE_Fixup3, b_mode }
 454 #define Evh3 { HLE_Fixup3, v_mode }
 455
 456 #define BND { BND_Fixup, 0 }
 457
 458 #define cond_jump_flag { NULL, cond_jump_mode }
 459 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 460
 461 /* bits in sizeflag */
 462 #define SUFFIX_ALWAYS 4
 463 #define AFLAG 2
 464 #define DFLAG 1
 465
 466 enum
 467 {
 468   /* byte operand */
 469   b_mode = 1,
 470   /* byte operand with operand swapped */
 471   b_swap_mode,
 472   /* byte operand, sign extend like 'T' suffix */
 473   b_T_mode,
 474   /* operand size depends on prefixes */
 475   v_mode,
 476   /* operand size depends on prefixes with operand swapped */
 477   v_swap_mode,
 478   /* word operand */
 479   w_mode,
 480   /* double word operand  */
 481   d_mode,
 482   /* double word operand with operand swapped */
 483   d_swap_mode,
 484   /* quad word operand */
 485   q_mode,
 486   /* quad word operand with operand swapped */
 487   q_swap_mode,
 488   /* ten-byte operand */
 489   t_mode,
 490   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 491      broadcast enabled.  */
 492   x_mode,
 493   /* Similar to x_mode, but with different EVEX mem shifts.  */
 494   evex_x_gscat_mode,
 495   /* Similar to x_mode, but with disabled broadcast.  */
 496   evex_x_nobcst_mode,
 497   /* Similar to x_mode, but with operands swapped and disabled broadcast
 498      in EVEX.  */
 499   x_swap_mode,
 500   /* 16-byte XMM operand */
 501   xmm_mode,
 502   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 503      memory operand (depending on vector length).  Broadcast isn't
 504      allowed.  */
 505   xmmq_mode,
 506   /* Same as xmmq_mode, but broadcast is allowed.  */
 507   evex_half_bcst_xmmq_mode,
 508   /* XMM register or byte memory operand */
 509   xmm_mb_mode,
 510   /* XMM register or word memory operand */
 511   xmm_mw_mode,
 512   /* XMM register or double word memory operand */
 513   xmm_md_mode,
 514   /* XMM register or quad word memory operand */
 515   xmm_mq_mode,
 516   /* XMM register or double/quad word memory operand, depending on
 517      VEX.W.  */
 518   xmm_mdq_mode,
 519   /* 16-byte XMM, word, double word or quad word operand.  */
 520   xmmdw_mode,
 521   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 522   xmmqd_mode,
 523   /* 32-byte YMM operand */
 524   ymm_mode,
 525   /* quad word, ymmword or zmmword memory operand.  */
 526   ymmq_mode,
 527   /* 32-byte YMM or 16-byte word operand */
 528   ymmxmm_mode,
 529   /* d_mode in 32bit, q_mode in 64bit mode.  */
 530   m_mode,
 531   /* pair of v_mode operands */
 532   a_mode,
 533   cond_jump_mode,
 534   loop_jcxz_mode,
 535   v_bnd_mode,
 536   /* operand size depends on REX prefixes.  */
 537   dq_mode,
 538   /* registers like dq_mode, memory like w_mode.  */
 539   dqw_mode,
 540   dqw_swap_mode,
 541   bnd_mode,
 542   /* 4- or 6-byte pointer operand */
 543   f_mode,
 544   const_1_mode,
 545   /* v_mode for stack-related opcodes.  */
 546   stack_v_mode,
 547   /* non-quad operand size depends on prefixes */
 548   z_mode,
 549   /* 16-byte operand */
 550   o_mode,
 551   /* registers like dq_mode, memory like b_mode.  */
 552   dqb_mode,
 553   /* registers like d_mode, memory like b_mode.  */
 554   db_mode,
 555   /* registers like d_mode, memory like w_mode.  */
 556   dw_mode,
 557   /* registers like dq_mode, memory like d_mode.  */
 558   dqd_mode,
 559   /* normal vex mode */
 560   vex_mode,
 561   /* 128bit vex mode */
 562   vex128_mode,
 563   /* 256bit vex mode */
 564   vex256_mode,
 565   /* operand size depends on the VEX.W bit.  */
 566   vex_w_dq_mode,
 567
 568   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 569   vex_vsib_d_w_dq_mode,
 570   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 571   vex_vsib_d_w_d_mode,
 572   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 573   vex_vsib_q_w_dq_mode,
 574   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 575   vex_vsib_q_w_d_mode,
 576
 577   /* scalar, ignore vector length.  */
 578   scalar_mode,
 579   /* like d_mode, ignore vector length.  */
 580   d_scalar_mode,
 581   /* like d_swap_mode, ignore vector length.  */
 582   d_scalar_swap_mode,
 583   /* like q_mode, ignore vector length.  */
 584   q_scalar_mode,
 585   /* like q_swap_mode, ignore vector length.  */
 586   q_scalar_swap_mode,
 587   /* like vex_mode, ignore vector length.  */
 588   vex_scalar_mode,
 589   /* like vex_w_dq_mode, ignore vector length.  */
 590   vex_scalar_w_dq_mode,
 591
 592   /* Static rounding.  */
 593   evex_rounding_mode,
 594   /* Supress all exceptions.  */
 595   evex_sae_mode,
 596
 597   /* Mask register operand.  */
 598   mask_mode,
 599   /* Mask register operand.  */
 600   mask_bd_mode,
 601
 602   es_reg,
 603   cs_reg,
 604   ss_reg,
 605   ds_reg,
 606   fs_reg,
 607   gs_reg,
 608
 609   eAX_reg,
 610   eCX_reg,
 611   eDX_reg,
 612   eBX_reg,
 613   eSP_reg,
 614   eBP_reg,
 615   eSI_reg,
 616   eDI_reg,
 617
 618   al_reg,
 619   cl_reg,
 620   dl_reg,
 621   bl_reg,
 622   ah_reg,
 623   ch_reg,
 624   dh_reg,
 625   bh_reg,
 626
 627   ax_reg,
 628   cx_reg,
 629   dx_reg,
 630   bx_reg,
 631   sp_reg,
 632   bp_reg,
 633   si_reg,
 634   di_reg,
 635
 636   rAX_reg,
 637   rCX_reg,
 638   rDX_reg,
 639   rBX_reg,
 640   rSP_reg,
 641   rBP_reg,
 642   rSI_reg,
 643   rDI_reg,
 644
 645   z_mode_ax_reg,
 646   indir_dx_reg
 647 };
 648
 649 enum
 650 {
 651   FLOATCODE = 1,
 652   USE_REG_TABLE,
 653   USE_MOD_TABLE,
 654   USE_RM_TABLE,
 655   USE_PREFIX_TABLE,
 656   USE_X86_64_TABLE,
 657   USE_3BYTE_TABLE,
 658   USE_XOP_8F_TABLE,
 659   USE_VEX_C4_TABLE,
 660   USE_VEX_C5_TABLE,
 661   USE_VEX_LEN_TABLE,
 662   USE_VEX_W_TABLE,
 663   USE_EVEX_TABLE
 664 };
 665
 666 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 667
 668 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 669 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 670 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 671 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 672 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 673 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 674 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 675 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 676 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 677 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 678 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 679 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 680 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 681
 682 enum
 683 {
 684   REG_80 = 0,
 685   REG_81,
 686   REG_82,
 687   REG_8F,
 688   REG_C0,
 689   REG_C1,
 690   REG_C6,
 691   REG_C7,
 692   REG_D0,
 693   REG_D1,
 694   REG_D2,
 695   REG_D3,
 696   REG_F6,
 697   REG_F7,
 698   REG_FE,
 699   REG_FF,
 700   REG_0F00,
 701   REG_0F01,
 702   REG_0F0D,
 703   REG_0F18,
 704   REG_0F71,
 705   REG_0F72,
 706   REG_0F73,
 707   REG_0FA6,
 708   REG_0FA7,
 709   REG_0FAE,
 710   REG_0FBA,
 711   REG_0FC7,
 712   REG_VEX_0F71,
 713   REG_VEX_0F72,
 714   REG_VEX_0F73,
 715   REG_VEX_0FAE,
 716   REG_VEX_0F38F3,
 717   REG_XOP_LWPCB,
 718   REG_XOP_LWP,
 719   REG_XOP_TBM_01,
 720   REG_XOP_TBM_02,
 721
 722   REG_EVEX_0F71,
 723   REG_EVEX_0F72,
 724   REG_EVEX_0F73,
 725   REG_EVEX_0F38C6,
 726   REG_EVEX_0F38C7
 727 };
 728
 729 enum
 730 {
 731   MOD_8D = 0,
 732   MOD_C6_REG_7,
 733   MOD_C7_REG_7,
 734   MOD_FF_REG_3,
 735   MOD_FF_REG_5,
 736   MOD_0F01_REG_0,
 737   MOD_0F01_REG_1,
 738   MOD_0F01_REG_2,
 739   MOD_0F01_REG_3,
 740   MOD_0F01_REG_7,
 741   MOD_0F12_PREFIX_0,
 742   MOD_0F13,
 743   MOD_0F16_PREFIX_0,
 744   MOD_0F17,
 745   MOD_0F18_REG_0,
 746   MOD_0F18_REG_1,
 747   MOD_0F18_REG_2,
 748   MOD_0F18_REG_3,
 749   MOD_0F18_REG_4,
 750   MOD_0F18_REG_5,
 751   MOD_0F18_REG_6,
 752   MOD_0F18_REG_7,
 753   MOD_0F1A_PREFIX_0,
 754   MOD_0F1B_PREFIX_0,
 755   MOD_0F1B_PREFIX_1,
 756   MOD_0F24,
 757   MOD_0F26,
 758   MOD_0F2B_PREFIX_0,
 759   MOD_0F2B_PREFIX_1,
 760   MOD_0F2B_PREFIX_2,
 761   MOD_0F2B_PREFIX_3,
 762   MOD_0F51,
 763   MOD_0F71_REG_2,
 764   MOD_0F71_REG_4,
 765   MOD_0F71_REG_6,
 766   MOD_0F72_REG_2,
 767   MOD_0F72_REG_4,
 768   MOD_0F72_REG_6,
 769   MOD_0F73_REG_2,
 770   MOD_0F73_REG_3,
 771   MOD_0F73_REG_6,
 772   MOD_0F73_REG_7,
 773   MOD_0FAE_REG_0,
 774   MOD_0FAE_REG_1,
 775   MOD_0FAE_REG_2,
 776   MOD_0FAE_REG_3,
 777   MOD_0FAE_REG_4,
 778   MOD_0FAE_REG_5,
 779   MOD_0FAE_REG_6,
 780   MOD_0FAE_REG_7,
 781   MOD_0FB2,
 782   MOD_0FB4,
 783   MOD_0FB5,
 784   MOD_0FC7_REG_3,
 785   MOD_0FC7_REG_4,
 786   MOD_0FC7_REG_5,
 787   MOD_0FC7_REG_6,
 788   MOD_0FC7_REG_7,
 789   MOD_0FD7,
 790   MOD_0FE7_PREFIX_2,
 791   MOD_0FF0_PREFIX_3,
 792   MOD_0F382A_PREFIX_2,
 793   MOD_62_32BIT,
 794   MOD_C4_32BIT,
 795   MOD_C5_32BIT,
 796   MOD_VEX_0F12_PREFIX_0,
 797   MOD_VEX_0F13,
 798   MOD_VEX_0F16_PREFIX_0,
 799   MOD_VEX_0F17,
 800   MOD_VEX_0F2B,
 801   MOD_VEX_0F50,
 802   MOD_VEX_0F71_REG_2,
 803   MOD_VEX_0F71_REG_4,
 804   MOD_VEX_0F71_REG_6,
 805   MOD_VEX_0F72_REG_2,
 806   MOD_VEX_0F72_REG_4,
 807   MOD_VEX_0F72_REG_6,
 808   MOD_VEX_0F73_REG_2,
 809   MOD_VEX_0F73_REG_3,
 810   MOD_VEX_0F73_REG_6,
 811   MOD_VEX_0F73_REG_7,
 812   MOD_VEX_0FAE_REG_2,
 813   MOD_VEX_0FAE_REG_3,
 814   MOD_VEX_0FD7_PREFIX_2,
 815   MOD_VEX_0FE7_PREFIX_2,
 816   MOD_VEX_0FF0_PREFIX_3,
 817   MOD_VEX_0F381A_PREFIX_2,
 818   MOD_VEX_0F382A_PREFIX_2,
 819   MOD_VEX_0F382C_PREFIX_2,
 820   MOD_VEX_0F382D_PREFIX_2,
 821   MOD_VEX_0F382E_PREFIX_2,
 822   MOD_VEX_0F382F_PREFIX_2,
 823   MOD_VEX_0F385A_PREFIX_2,
 824   MOD_VEX_0F388C_PREFIX_2,
 825   MOD_VEX_0F388E_PREFIX_2,
 826
 827   MOD_EVEX_0F10_PREFIX_1,
 828   MOD_EVEX_0F10_PREFIX_3,
 829   MOD_EVEX_0F11_PREFIX_1,
 830   MOD_EVEX_0F11_PREFIX_3,
 831   MOD_EVEX_0F12_PREFIX_0,
 832   MOD_EVEX_0F16_PREFIX_0,
 833   MOD_EVEX_0F38C6_REG_1,
 834   MOD_EVEX_0F38C6_REG_2,
 835   MOD_EVEX_0F38C6_REG_5,
 836   MOD_EVEX_0F38C6_REG_6,
 837   MOD_EVEX_0F38C7_REG_1,
 838   MOD_EVEX_0F38C7_REG_2,
 839   MOD_EVEX_0F38C7_REG_5,
 840   MOD_EVEX_0F38C7_REG_6
 841 };
 842
 843 enum
 844 {
 845   RM_C6_REG_7 = 0,
 846   RM_C7_REG_7,
 847   RM_0F01_REG_0,
 848   RM_0F01_REG_1,
 849   RM_0F01_REG_2,
 850   RM_0F01_REG_3,
 851   RM_0F01_REG_7,
 852   RM_0FAE_REG_5,
 853   RM_0FAE_REG_6,
 854   RM_0FAE_REG_7
 855 };
 856
 857 enum
 858 {
 859   PREFIX_90 = 0,
 860   PREFIX_0F10,
 861   PREFIX_0F11,
 862   PREFIX_0F12,
 863   PREFIX_0F16,
 864   PREFIX_0F1A,
 865   PREFIX_0F1B,
 866   PREFIX_0F2A,
 867   PREFIX_0F2B,
 868   PREFIX_0F2C,
 869   PREFIX_0F2D,
 870   PREFIX_0F2E,
 871   PREFIX_0F2F,
 872   PREFIX_0F51,
 873   PREFIX_0F52,
 874   PREFIX_0F53,
 875   PREFIX_0F58,
 876   PREFIX_0F59,
 877   PREFIX_0F5A,
 878   PREFIX_0F5B,
 879   PREFIX_0F5C,
 880   PREFIX_0F5D,
 881   PREFIX_0F5E,
 882   PREFIX_0F5F,
 883   PREFIX_0F60,
 884   PREFIX_0F61,
 885   PREFIX_0F62,
 886   PREFIX_0F6C,
 887   PREFIX_0F6D,
 888   PREFIX_0F6F,
 889   PREFIX_0F70,
 890   PREFIX_0F73_REG_3,
 891   PREFIX_0F73_REG_7,
 892   PREFIX_0F78,
 893   PREFIX_0F79,
 894   PREFIX_0F7C,
 895   PREFIX_0F7D,
 896   PREFIX_0F7E,
 897   PREFIX_0F7F,
 898   PREFIX_0FAE_REG_0,
 899   PREFIX_0FAE_REG_1,
 900   PREFIX_0FAE_REG_2,
 901   PREFIX_0FAE_REG_3,
 902   PREFIX_0FAE_REG_7,
 903   PREFIX_0FB8,
 904   PREFIX_0FBC,
 905   PREFIX_0FBD,
 906   PREFIX_0FC2,
 907   PREFIX_0FC3,
 908   PREFIX_0FC7_REG_6,
 909   PREFIX_0FD0,
 910   PREFIX_0FD6,
 911   PREFIX_0FE6,
 912   PREFIX_0FE7,
 913   PREFIX_0FF0,
 914   PREFIX_0FF7,
 915   PREFIX_0F3810,
 916   PREFIX_0F3814,
 917   PREFIX_0F3815,
 918   PREFIX_0F3817,
 919   PREFIX_0F3820,
 920   PREFIX_0F3821,
 921   PREFIX_0F3822,
 922   PREFIX_0F3823,
 923   PREFIX_0F3824,
 924   PREFIX_0F3825,
 925   PREFIX_0F3828,
 926   PREFIX_0F3829,
 927   PREFIX_0F382A,
 928   PREFIX_0F382B,
 929   PREFIX_0F3830,
 930   PREFIX_0F3831,
 931   PREFIX_0F3832,
 932   PREFIX_0F3833,
 933   PREFIX_0F3834,
 934   PREFIX_0F3835,
 935   PREFIX_0F3837,
 936   PREFIX_0F3838,
 937   PREFIX_0F3839,
 938   PREFIX_0F383A,
 939   PREFIX_0F383B,
 940   PREFIX_0F383C,
 941   PREFIX_0F383D,
 942   PREFIX_0F383E,
 943   PREFIX_0F383F,
 944   PREFIX_0F3840,
 945   PREFIX_0F3841,
 946   PREFIX_0F3880,
 947   PREFIX_0F3881,
 948   PREFIX_0F3882,
 949   PREFIX_0F38C8,
 950   PREFIX_0F38C9,
 951   PREFIX_0F38CA,
 952   PREFIX_0F38CB,
 953   PREFIX_0F38CC,
 954   PREFIX_0F38CD,
 955   PREFIX_0F38DB,
 956   PREFIX_0F38DC,
 957   PREFIX_0F38DD,
 958   PREFIX_0F38DE,
 959   PREFIX_0F38DF,
 960   PREFIX_0F38F0,
 961   PREFIX_0F38F1,
 962   PREFIX_0F38F6,
 963   PREFIX_0F3A08,
 964   PREFIX_0F3A09,
 965   PREFIX_0F3A0A,
 966   PREFIX_0F3A0B,
 967   PREFIX_0F3A0C,
 968   PREFIX_0F3A0D,
 969   PREFIX_0F3A0E,
 970   PREFIX_0F3A14,
 971   PREFIX_0F3A15,
 972   PREFIX_0F3A16,
 973   PREFIX_0F3A17,
 974   PREFIX_0F3A20,
 975   PREFIX_0F3A21,
 976   PREFIX_0F3A22,
 977   PREFIX_0F3A40,
 978   PREFIX_0F3A41,
 979   PREFIX_0F3A42,
 980   PREFIX_0F3A44,
 981   PREFIX_0F3A60,
 982   PREFIX_0F3A61,
 983   PREFIX_0F3A62,
 984   PREFIX_0F3A63,
 985   PREFIX_0F3ACC,
 986   PREFIX_0F3ADF,
 987   PREFIX_VEX_0F10,
 988   PREFIX_VEX_0F11,
 989   PREFIX_VEX_0F12,
 990   PREFIX_VEX_0F16,
 991   PREFIX_VEX_0F2A,
 992   PREFIX_VEX_0F2C,
 993   PREFIX_VEX_0F2D,
 994   PREFIX_VEX_0F2E,
 995   PREFIX_VEX_0F2F,
 996   PREFIX_VEX_0F41,
 997   PREFIX_VEX_0F42,
 998   PREFIX_VEX_0F44,
 999   PREFIX_VEX_0F45,
1000   PREFIX_VEX_0F46,
1001   PREFIX_VEX_0F47,
1002   PREFIX_VEX_0F4A,
1003   PREFIX_VEX_0F4B,
1004   PREFIX_VEX_0F51,
1005   PREFIX_VEX_0F52,
1006   PREFIX_VEX_0F53,
1007   PREFIX_VEX_0F58,
1008   PREFIX_VEX_0F59,
1009   PREFIX_VEX_0F5A,
1010   PREFIX_VEX_0F5B,
1011   PREFIX_VEX_0F5C,
1012   PREFIX_VEX_0F5D,
1013   PREFIX_VEX_0F5E,
1014   PREFIX_VEX_0F5F,
1015   PREFIX_VEX_0F60,
1016   PREFIX_VEX_0F61,
1017   PREFIX_VEX_0F62,
1018   PREFIX_VEX_0F63,
1019   PREFIX_VEX_0F64,
1020   PREFIX_VEX_0F65,
1021   PREFIX_VEX_0F66,
1022   PREFIX_VEX_0F67,
1023   PREFIX_VEX_0F68,
1024   PREFIX_VEX_0F69,
1025   PREFIX_VEX_0F6A,
1026   PREFIX_VEX_0F6B,
1027   PREFIX_VEX_0F6C,
1028   PREFIX_VEX_0F6D,
1029   PREFIX_VEX_0F6E,
1030   PREFIX_VEX_0F6F,
1031   PREFIX_VEX_0F70,
1032   PREFIX_VEX_0F71_REG_2,
1033   PREFIX_VEX_0F71_REG_4,
1034   PREFIX_VEX_0F71_REG_6,
1035   PREFIX_VEX_0F72_REG_2,
1036   PREFIX_VEX_0F72_REG_4,
1037   PREFIX_VEX_0F72_REG_6,
1038   PREFIX_VEX_0F73_REG_2,
1039   PREFIX_VEX_0F73_REG_3,
1040   PREFIX_VEX_0F73_REG_6,
1041   PREFIX_VEX_0F73_REG_7,
1042   PREFIX_VEX_0F74,
1043   PREFIX_VEX_0F75,
1044   PREFIX_VEX_0F76,
1045   PREFIX_VEX_0F77,
1046   PREFIX_VEX_0F7C,
1047   PREFIX_VEX_0F7D,
1048   PREFIX_VEX_0F7E,
1049   PREFIX_VEX_0F7F,
1050   PREFIX_VEX_0F90,
1051   PREFIX_VEX_0F91,
1052   PREFIX_VEX_0F92,
1053   PREFIX_VEX_0F93,
1054   PREFIX_VEX_0F98,
1055   PREFIX_VEX_0F99,
1056   PREFIX_VEX_0FC2,
1057   PREFIX_VEX_0FC4,
1058   PREFIX_VEX_0FC5,
1059   PREFIX_VEX_0FD0,
1060   PREFIX_VEX_0FD1,
1061   PREFIX_VEX_0FD2,
1062   PREFIX_VEX_0FD3,
1063   PREFIX_VEX_0FD4,
1064   PREFIX_VEX_0FD5,
1065   PREFIX_VEX_0FD6,
1066   PREFIX_VEX_0FD7,
1067   PREFIX_VEX_0FD8,
1068   PREFIX_VEX_0FD9,
1069   PREFIX_VEX_0FDA,
1070   PREFIX_VEX_0FDB,
1071   PREFIX_VEX_0FDC,
1072   PREFIX_VEX_0FDD,
1073   PREFIX_VEX_0FDE,
1074   PREFIX_VEX_0FDF,
1075   PREFIX_VEX_0FE0,
1076   PREFIX_VEX_0FE1,
1077   PREFIX_VEX_0FE2,
1078   PREFIX_VEX_0FE3,
1079   PREFIX_VEX_0FE4,
1080   PREFIX_VEX_0FE5,
1081   PREFIX_VEX_0FE6,
1082   PREFIX_VEX_0FE7,
1083   PREFIX_VEX_0FE8,
1084   PREFIX_VEX_0FE9,
1085   PREFIX_VEX_0FEA,
1086   PREFIX_VEX_0FEB,
1087   PREFIX_VEX_0FEC,
1088   PREFIX_VEX_0FED,
1089   PREFIX_VEX_0FEE,
1090   PREFIX_VEX_0FEF,
1091   PREFIX_VEX_0FF0,
1092   PREFIX_VEX_0FF1,
1093   PREFIX_VEX_0FF2,
1094   PREFIX_VEX_0FF3,
1095   PREFIX_VEX_0FF4,
1096   PREFIX_VEX_0FF5,
1097   PREFIX_VEX_0FF6,
1098   PREFIX_VEX_0FF7,
1099   PREFIX_VEX_0FF8,
1100   PREFIX_VEX_0FF9,
1101   PREFIX_VEX_0FFA,
1102   PREFIX_VEX_0FFB,
1103   PREFIX_VEX_0FFC,
1104   PREFIX_VEX_0FFD,
1105   PREFIX_VEX_0FFE,
1106   PREFIX_VEX_0F3800,
1107   PREFIX_VEX_0F3801,
1108   PREFIX_VEX_0F3802,
1109   PREFIX_VEX_0F3803,
1110   PREFIX_VEX_0F3804,
1111   PREFIX_VEX_0F3805,
1112   PREFIX_VEX_0F3806,
1113   PREFIX_VEX_0F3807,
1114   PREFIX_VEX_0F3808,
1115   PREFIX_VEX_0F3809,
1116   PREFIX_VEX_0F380A,
1117   PREFIX_VEX_0F380B,
1118   PREFIX_VEX_0F380C,
1119   PREFIX_VEX_0F380D,
1120   PREFIX_VEX_0F380E,
1121   PREFIX_VEX_0F380F,
1122   PREFIX_VEX_0F3813,
1123   PREFIX_VEX_0F3816,
1124   PREFIX_VEX_0F3817,
1125   PREFIX_VEX_0F3818,
1126   PREFIX_VEX_0F3819,
1127   PREFIX_VEX_0F381A,
1128   PREFIX_VEX_0F381C,
1129   PREFIX_VEX_0F381D,
1130   PREFIX_VEX_0F381E,
1131   PREFIX_VEX_0F3820,
1132   PREFIX_VEX_0F3821,
1133   PREFIX_VEX_0F3822,
1134   PREFIX_VEX_0F3823,
1135   PREFIX_VEX_0F3824,
1136   PREFIX_VEX_0F3825,
1137   PREFIX_VEX_0F3828,
1138   PREFIX_VEX_0F3829,
1139   PREFIX_VEX_0F382A,
1140   PREFIX_VEX_0F382B,
1141   PREFIX_VEX_0F382C,
1142   PREFIX_VEX_0F382D,
1143   PREFIX_VEX_0F382E,
1144   PREFIX_VEX_0F382F,
1145   PREFIX_VEX_0F3830,
1146   PREFIX_VEX_0F3831,
1147   PREFIX_VEX_0F3832,
1148   PREFIX_VEX_0F3833,
1149   PREFIX_VEX_0F3834,
1150   PREFIX_VEX_0F3835,
1151   PREFIX_VEX_0F3836,
1152   PREFIX_VEX_0F3837,
1153   PREFIX_VEX_0F3838,
1154   PREFIX_VEX_0F3839,
1155   PREFIX_VEX_0F383A,
1156   PREFIX_VEX_0F383B,
1157   PREFIX_VEX_0F383C,
1158   PREFIX_VEX_0F383D,
1159   PREFIX_VEX_0F383E,
1160   PREFIX_VEX_0F383F,
1161   PREFIX_VEX_0F3840,
1162   PREFIX_VEX_0F3841,
1163   PREFIX_VEX_0F3845,
1164   PREFIX_VEX_0F3846,
1165   PREFIX_VEX_0F3847,
1166   PREFIX_VEX_0F3858,
1167   PREFIX_VEX_0F3859,
1168   PREFIX_VEX_0F385A,
1169   PREFIX_VEX_0F3878,
1170   PREFIX_VEX_0F3879,
1171   PREFIX_VEX_0F388C,
1172   PREFIX_VEX_0F388E,
1173   PREFIX_VEX_0F3890,
1174   PREFIX_VEX_0F3891,
1175   PREFIX_VEX_0F3892,
1176   PREFIX_VEX_0F3893,
1177   PREFIX_VEX_0F3896,
1178   PREFIX_VEX_0F3897,
1179   PREFIX_VEX_0F3898,
1180   PREFIX_VEX_0F3899,
1181   PREFIX_VEX_0F389A,
1182   PREFIX_VEX_0F389B,
1183   PREFIX_VEX_0F389C,
1184   PREFIX_VEX_0F389D,
1185   PREFIX_VEX_0F389E,
1186   PREFIX_VEX_0F389F,
1187   PREFIX_VEX_0F38A6,
1188   PREFIX_VEX_0F38A7,
1189   PREFIX_VEX_0F38A8,
1190   PREFIX_VEX_0F38A9,
1191   PREFIX_VEX_0F38AA,
1192   PREFIX_VEX_0F38AB,
1193   PREFIX_VEX_0F38AC,
1194   PREFIX_VEX_0F38AD,
1195   PREFIX_VEX_0F38AE,
1196   PREFIX_VEX_0F38AF,
1197   PREFIX_VEX_0F38B6,
1198   PREFIX_VEX_0F38B7,
1199   PREFIX_VEX_0F38B8,
1200   PREFIX_VEX_0F38B9,
1201   PREFIX_VEX_0F38BA,
1202   PREFIX_VEX_0F38BB,
1203   PREFIX_VEX_0F38BC,
1204   PREFIX_VEX_0F38BD,
1205   PREFIX_VEX_0F38BE,
1206   PREFIX_VEX_0F38BF,
1207   PREFIX_VEX_0F38DB,
1208   PREFIX_VEX_0F38DC,
1209   PREFIX_VEX_0F38DD,
1210   PREFIX_VEX_0F38DE,
1211   PREFIX_VEX_0F38DF,
1212   PREFIX_VEX_0F38F2,
1213   PREFIX_VEX_0F38F3_REG_1,
1214   PREFIX_VEX_0F38F3_REG_2,
1215   PREFIX_VEX_0F38F3_REG_3,
1216   PREFIX_VEX_0F38F5,
1217   PREFIX_VEX_0F38F6,
1218   PREFIX_VEX_0F38F7,
1219   PREFIX_VEX_0F3A00,
1220   PREFIX_VEX_0F3A01,
1221   PREFIX_VEX_0F3A02,
1222   PREFIX_VEX_0F3A04,
1223   PREFIX_VEX_0F3A05,
1224   PREFIX_VEX_0F3A06,
1225   PREFIX_VEX_0F3A08,
1226   PREFIX_VEX_0F3A09,
1227   PREFIX_VEX_0F3A0A,
1228   PREFIX_VEX_0F3A0B,
1229   PREFIX_VEX_0F3A0C,
1230   PREFIX_VEX_0F3A0D,
1231   PREFIX_VEX_0F3A0E,
1232   PREFIX_VEX_0F3A0F,
1233   PREFIX_VEX_0F3A14,
1234   PREFIX_VEX_0F3A15,
1235   PREFIX_VEX_0F3A16,
1236   PREFIX_VEX_0F3A17,
1237   PREFIX_VEX_0F3A18,
1238   PREFIX_VEX_0F3A19,
1239   PREFIX_VEX_0F3A1D,
1240   PREFIX_VEX_0F3A20,
1241   PREFIX_VEX_0F3A21,
1242   PREFIX_VEX_0F3A22,
1243   PREFIX_VEX_0F3A30,
1244   PREFIX_VEX_0F3A31,
1245   PREFIX_VEX_0F3A32,
1246   PREFIX_VEX_0F3A33,
1247   PREFIX_VEX_0F3A38,
1248   PREFIX_VEX_0F3A39,
1249   PREFIX_VEX_0F3A40,
1250   PREFIX_VEX_0F3A41,
1251   PREFIX_VEX_0F3A42,
1252   PREFIX_VEX_0F3A44,
1253   PREFIX_VEX_0F3A46,
1254   PREFIX_VEX_0F3A48,
1255   PREFIX_VEX_0F3A49,
1256   PREFIX_VEX_0F3A4A,
1257   PREFIX_VEX_0F3A4B,
1258   PREFIX_VEX_0F3A4C,
1259   PREFIX_VEX_0F3A5C,
1260   PREFIX_VEX_0F3A5D,
1261   PREFIX_VEX_0F3A5E,
1262   PREFIX_VEX_0F3A5F,
1263   PREFIX_VEX_0F3A60,
1264   PREFIX_VEX_0F3A61,
1265   PREFIX_VEX_0F3A62,
1266   PREFIX_VEX_0F3A63,
1267   PREFIX_VEX_0F3A68,
1268   PREFIX_VEX_0F3A69,
1269   PREFIX_VEX_0F3A6A,
1270   PREFIX_VEX_0F3A6B,
1271   PREFIX_VEX_0F3A6C,
1272   PREFIX_VEX_0F3A6D,
1273   PREFIX_VEX_0F3A6E,
1274   PREFIX_VEX_0F3A6F,
1275   PREFIX_VEX_0F3A78,
1276   PREFIX_VEX_0F3A79,
1277   PREFIX_VEX_0F3A7A,
1278   PREFIX_VEX_0F3A7B,
1279   PREFIX_VEX_0F3A7C,
1280   PREFIX_VEX_0F3A7D,
1281   PREFIX_VEX_0F3A7E,
1282   PREFIX_VEX_0F3A7F,
1283   PREFIX_VEX_0F3ADF,
1284   PREFIX_VEX_0F3AF0,
1285
1286   PREFIX_EVEX_0F10,
1287   PREFIX_EVEX_0F11,
1288   PREFIX_EVEX_0F12,
1289   PREFIX_EVEX_0F13,
1290   PREFIX_EVEX_0F14,
1291   PREFIX_EVEX_0F15,
1292   PREFIX_EVEX_0F16,
1293   PREFIX_EVEX_0F17,
1294   PREFIX_EVEX_0F28,
1295   PREFIX_EVEX_0F29,
1296   PREFIX_EVEX_0F2A,
1297   PREFIX_EVEX_0F2B,
1298   PREFIX_EVEX_0F2C,
1299   PREFIX_EVEX_0F2D,
1300   PREFIX_EVEX_0F2E,
1301   PREFIX_EVEX_0F2F,
1302   PREFIX_EVEX_0F51,
1303   PREFIX_EVEX_0F54,
1304   PREFIX_EVEX_0F55,
1305   PREFIX_EVEX_0F56,
1306   PREFIX_EVEX_0F57,
1307   PREFIX_EVEX_0F58,
1308   PREFIX_EVEX_0F59,
1309   PREFIX_EVEX_0F5A,
1310   PREFIX_EVEX_0F5B,
1311   PREFIX_EVEX_0F5C,
1312   PREFIX_EVEX_0F5D,
1313   PREFIX_EVEX_0F5E,
1314   PREFIX_EVEX_0F5F,
1315   PREFIX_EVEX_0F60,
1316   PREFIX_EVEX_0F61,
1317   PREFIX_EVEX_0F62,
1318   PREFIX_EVEX_0F63,
1319   PREFIX_EVEX_0F64,
1320   PREFIX_EVEX_0F65,
1321   PREFIX_EVEX_0F66,
1322   PREFIX_EVEX_0F67,
1323   PREFIX_EVEX_0F68,
1324   PREFIX_EVEX_0F69,
1325   PREFIX_EVEX_0F6A,
1326   PREFIX_EVEX_0F6B,
1327   PREFIX_EVEX_0F6C,
1328   PREFIX_EVEX_0F6D,
1329   PREFIX_EVEX_0F6E,
1330   PREFIX_EVEX_0F6F,
1331   PREFIX_EVEX_0F70,
1332   PREFIX_EVEX_0F71_REG_2,
1333   PREFIX_EVEX_0F71_REG_4,
1334   PREFIX_EVEX_0F71_REG_6,
1335   PREFIX_EVEX_0F72_REG_0,
1336   PREFIX_EVEX_0F72_REG_1,
1337   PREFIX_EVEX_0F72_REG_2,
1338   PREFIX_EVEX_0F72_REG_4,
1339   PREFIX_EVEX_0F72_REG_6,
1340   PREFIX_EVEX_0F73_REG_2,
1341   PREFIX_EVEX_0F73_REG_3,
1342   PREFIX_EVEX_0F73_REG_6,
1343   PREFIX_EVEX_0F73_REG_7,
1344   PREFIX_EVEX_0F74,
1345   PREFIX_EVEX_0F75,
1346   PREFIX_EVEX_0F76,
1347   PREFIX_EVEX_0F78,
1348   PREFIX_EVEX_0F79,
1349   PREFIX_EVEX_0F7A,
1350   PREFIX_EVEX_0F7B,
1351   PREFIX_EVEX_0F7E,
1352   PREFIX_EVEX_0F7F,
1353   PREFIX_EVEX_0FC2,
1354   PREFIX_EVEX_0FC4,
1355   PREFIX_EVEX_0FC5,
1356   PREFIX_EVEX_0FC6,
1357   PREFIX_EVEX_0FD1,
1358   PREFIX_EVEX_0FD2,
1359   PREFIX_EVEX_0FD3,
1360   PREFIX_EVEX_0FD4,
1361   PREFIX_EVEX_0FD5,
1362   PREFIX_EVEX_0FD6,
1363   PREFIX_EVEX_0FD8,
1364   PREFIX_EVEX_0FD9,
1365   PREFIX_EVEX_0FDA,
1366   PREFIX_EVEX_0FDB,
1367   PREFIX_EVEX_0FDC,
1368   PREFIX_EVEX_0FDD,
1369   PREFIX_EVEX_0FDE,
1370   PREFIX_EVEX_0FDF,
1371   PREFIX_EVEX_0FE0,
1372   PREFIX_EVEX_0FE1,
1373   PREFIX_EVEX_0FE2,
1374   PREFIX_EVEX_0FE3,
1375   PREFIX_EVEX_0FE4,
1376   PREFIX_EVEX_0FE5,
1377   PREFIX_EVEX_0FE6,
1378   PREFIX_EVEX_0FE7,
1379   PREFIX_EVEX_0FE8,
1380   PREFIX_EVEX_0FE9,
1381   PREFIX_EVEX_0FEA,
1382   PREFIX_EVEX_0FEB,
1383   PREFIX_EVEX_0FEC,
1384   PREFIX_EVEX_0FED,
1385   PREFIX_EVEX_0FEE,
1386   PREFIX_EVEX_0FEF,
1387   PREFIX_EVEX_0FF1,
1388   PREFIX_EVEX_0FF2,
1389   PREFIX_EVEX_0FF3,
1390   PREFIX_EVEX_0FF4,
1391   PREFIX_EVEX_0FF5,
1392   PREFIX_EVEX_0FF6,
1393   PREFIX_EVEX_0FF8,
1394   PREFIX_EVEX_0FF9,
1395   PREFIX_EVEX_0FFA,
1396   PREFIX_EVEX_0FFB,
1397   PREFIX_EVEX_0FFC,
1398   PREFIX_EVEX_0FFD,
1399   PREFIX_EVEX_0FFE,
1400   PREFIX_EVEX_0F3800,
1401   PREFIX_EVEX_0F3804,
1402   PREFIX_EVEX_0F380B,
1403   PREFIX_EVEX_0F380C,
1404   PREFIX_EVEX_0F380D,
1405   PREFIX_EVEX_0F3810,
1406   PREFIX_EVEX_0F3811,
1407   PREFIX_EVEX_0F3812,
1408   PREFIX_EVEX_0F3813,
1409   PREFIX_EVEX_0F3814,
1410   PREFIX_EVEX_0F3815,
1411   PREFIX_EVEX_0F3816,
1412   PREFIX_EVEX_0F3818,
1413   PREFIX_EVEX_0F3819,
1414   PREFIX_EVEX_0F381A,
1415   PREFIX_EVEX_0F381B,
1416   PREFIX_EVEX_0F381C,
1417   PREFIX_EVEX_0F381D,
1418   PREFIX_EVEX_0F381E,
1419   PREFIX_EVEX_0F381F,
1420   PREFIX_EVEX_0F3820,
1421   PREFIX_EVEX_0F3821,
1422   PREFIX_EVEX_0F3822,
1423   PREFIX_EVEX_0F3823,
1424   PREFIX_EVEX_0F3824,
1425   PREFIX_EVEX_0F3825,
1426   PREFIX_EVEX_0F3826,
1427   PREFIX_EVEX_0F3827,
1428   PREFIX_EVEX_0F3828,
1429   PREFIX_EVEX_0F3829,
1430   PREFIX_EVEX_0F382A,
1431   PREFIX_EVEX_0F382B,
1432   PREFIX_EVEX_0F382C,
1433   PREFIX_EVEX_0F382D,
1434   PREFIX_EVEX_0F3830,
1435   PREFIX_EVEX_0F3831,
1436   PREFIX_EVEX_0F3832,
1437   PREFIX_EVEX_0F3833,
1438   PREFIX_EVEX_0F3834,
1439   PREFIX_EVEX_0F3835,
1440   PREFIX_EVEX_0F3836,
1441   PREFIX_EVEX_0F3837,
1442   PREFIX_EVEX_0F3838,
1443   PREFIX_EVEX_0F3839,
1444   PREFIX_EVEX_0F383A,
1445   PREFIX_EVEX_0F383B,
1446   PREFIX_EVEX_0F383C,
1447   PREFIX_EVEX_0F383D,
1448   PREFIX_EVEX_0F383E,
1449   PREFIX_EVEX_0F383F,
1450   PREFIX_EVEX_0F3840,
1451   PREFIX_EVEX_0F3842,
1452   PREFIX_EVEX_0F3843,
1453   PREFIX_EVEX_0F3844,
1454   PREFIX_EVEX_0F3845,
1455   PREFIX_EVEX_0F3846,
1456   PREFIX_EVEX_0F3847,
1457   PREFIX_EVEX_0F384C,
1458   PREFIX_EVEX_0F384D,
1459   PREFIX_EVEX_0F384E,
1460   PREFIX_EVEX_0F384F,
1461   PREFIX_EVEX_0F3858,
1462   PREFIX_EVEX_0F3859,
1463   PREFIX_EVEX_0F385A,
1464   PREFIX_EVEX_0F385B,
1465   PREFIX_EVEX_0F3864,
1466   PREFIX_EVEX_0F3865,
1467   PREFIX_EVEX_0F3866,
1468   PREFIX_EVEX_0F3875,
1469   PREFIX_EVEX_0F3876,
1470   PREFIX_EVEX_0F3877,
1471   PREFIX_EVEX_0F3878,
1472   PREFIX_EVEX_0F3879,
1473   PREFIX_EVEX_0F387A,
1474   PREFIX_EVEX_0F387B,
1475   PREFIX_EVEX_0F387C,
1476   PREFIX_EVEX_0F387D,
1477   PREFIX_EVEX_0F387E,
1478   PREFIX_EVEX_0F387F,
1479   PREFIX_EVEX_0F3888,
1480   PREFIX_EVEX_0F3889,
1481   PREFIX_EVEX_0F388A,
1482   PREFIX_EVEX_0F388B,
1483   PREFIX_EVEX_0F388D,
1484   PREFIX_EVEX_0F3890,
1485   PREFIX_EVEX_0F3891,
1486   PREFIX_EVEX_0F3892,
1487   PREFIX_EVEX_0F3893,
1488   PREFIX_EVEX_0F3896,
1489   PREFIX_EVEX_0F3897,
1490   PREFIX_EVEX_0F3898,
1491   PREFIX_EVEX_0F3899,
1492   PREFIX_EVEX_0F389A,
1493   PREFIX_EVEX_0F389B,
1494   PREFIX_EVEX_0F389C,
1495   PREFIX_EVEX_0F389D,
1496   PREFIX_EVEX_0F389E,
1497   PREFIX_EVEX_0F389F,
1498   PREFIX_EVEX_0F38A0,
1499   PREFIX_EVEX_0F38A1,
1500   PREFIX_EVEX_0F38A2,
1501   PREFIX_EVEX_0F38A3,
1502   PREFIX_EVEX_0F38A6,
1503   PREFIX_EVEX_0F38A7,
1504   PREFIX_EVEX_0F38A8,
1505   PREFIX_EVEX_0F38A9,
1506   PREFIX_EVEX_0F38AA,
1507   PREFIX_EVEX_0F38AB,
1508   PREFIX_EVEX_0F38AC,
1509   PREFIX_EVEX_0F38AD,
1510   PREFIX_EVEX_0F38AE,
1511   PREFIX_EVEX_0F38AF,
1512   PREFIX_EVEX_0F38B6,
1513   PREFIX_EVEX_0F38B7,
1514   PREFIX_EVEX_0F38B8,
1515   PREFIX_EVEX_0F38B9,
1516   PREFIX_EVEX_0F38BA,
1517   PREFIX_EVEX_0F38BB,
1518   PREFIX_EVEX_0F38BC,
1519   PREFIX_EVEX_0F38BD,
1520   PREFIX_EVEX_0F38BE,
1521   PREFIX_EVEX_0F38BF,
1522   PREFIX_EVEX_0F38C4,
1523   PREFIX_EVEX_0F38C6_REG_1,
1524   PREFIX_EVEX_0F38C6_REG_2,
1525   PREFIX_EVEX_0F38C6_REG_5,
1526   PREFIX_EVEX_0F38C6_REG_6,
1527   PREFIX_EVEX_0F38C7_REG_1,
1528   PREFIX_EVEX_0F38C7_REG_2,
1529   PREFIX_EVEX_0F38C7_REG_5,
1530   PREFIX_EVEX_0F38C7_REG_6,
1531   PREFIX_EVEX_0F38C8,
1532   PREFIX_EVEX_0F38CA,
1533   PREFIX_EVEX_0F38CB,
1534   PREFIX_EVEX_0F38CC,
1535   PREFIX_EVEX_0F38CD,
1536
1537   PREFIX_EVEX_0F3A00,
1538   PREFIX_EVEX_0F3A01,
1539   PREFIX_EVEX_0F3A03,
1540   PREFIX_EVEX_0F3A04,
1541   PREFIX_EVEX_0F3A05,
1542   PREFIX_EVEX_0F3A08,
1543   PREFIX_EVEX_0F3A09,
1544   PREFIX_EVEX_0F3A0A,
1545   PREFIX_EVEX_0F3A0B,
1546   PREFIX_EVEX_0F3A0F,
1547   PREFIX_EVEX_0F3A14,
1548   PREFIX_EVEX_0F3A15,
1549   PREFIX_EVEX_0F3A16,
1550   PREFIX_EVEX_0F3A17,
1551   PREFIX_EVEX_0F3A18,
1552   PREFIX_EVEX_0F3A19,
1553   PREFIX_EVEX_0F3A1A,
1554   PREFIX_EVEX_0F3A1B,
1555   PREFIX_EVEX_0F3A1D,
1556   PREFIX_EVEX_0F3A1E,
1557   PREFIX_EVEX_0F3A1F,
1558   PREFIX_EVEX_0F3A20,
1559   PREFIX_EVEX_0F3A21,
1560   PREFIX_EVEX_0F3A22,
1561   PREFIX_EVEX_0F3A23,
1562   PREFIX_EVEX_0F3A25,
1563   PREFIX_EVEX_0F3A26,
1564   PREFIX_EVEX_0F3A27,
1565   PREFIX_EVEX_0F3A38,
1566   PREFIX_EVEX_0F3A39,
1567   PREFIX_EVEX_0F3A3A,
1568   PREFIX_EVEX_0F3A3B,
1569   PREFIX_EVEX_0F3A3E,
1570   PREFIX_EVEX_0F3A3F,
1571   PREFIX_EVEX_0F3A42,
1572   PREFIX_EVEX_0F3A43,
1573   PREFIX_EVEX_0F3A50,
1574   PREFIX_EVEX_0F3A51,
1575   PREFIX_EVEX_0F3A54,
1576   PREFIX_EVEX_0F3A55,
1577   PREFIX_EVEX_0F3A56,
1578   PREFIX_EVEX_0F3A57,
1579   PREFIX_EVEX_0F3A66,
1580   PREFIX_EVEX_0F3A67
1581 };
1582
1583 enum
1584 {
1585   X86_64_06 = 0,
1586   X86_64_07,
1587   X86_64_0D,
1588   X86_64_16,
1589   X86_64_17,
1590   X86_64_1E,
1591   X86_64_1F,
1592   X86_64_27,
1593   X86_64_2F,
1594   X86_64_37,
1595   X86_64_3F,
1596   X86_64_60,
1597   X86_64_61,
1598   X86_64_62,
1599   X86_64_63,
1600   X86_64_6D,
1601   X86_64_6F,
1602   X86_64_9A,
1603   X86_64_C4,
1604   X86_64_C5,
1605   X86_64_CE,
1606   X86_64_D4,
1607   X86_64_D5,
1608   X86_64_EA,
1609   X86_64_0F01_REG_0,
1610   X86_64_0F01_REG_1,
1611   X86_64_0F01_REG_2,
1612   X86_64_0F01_REG_3
1613 };
1614
1615 enum
1616 {
1617   THREE_BYTE_0F38 = 0,
1618   THREE_BYTE_0F3A,
1619   THREE_BYTE_0F7A
1620 };
1621
1622 enum
1623 {
1624   XOP_08 = 0,
1625   XOP_09,
1626   XOP_0A
1627 };
1628
1629 enum
1630 {
1631   VEX_0F = 0,
1632   VEX_0F38,
1633   VEX_0F3A
1634 };
1635
1636 enum
1637 {
1638   EVEX_0F = 0,
1639   EVEX_0F38,
1640   EVEX_0F3A
1641 };
1642
1643 enum
1644 {
1645   VEX_LEN_0F10_P_1 = 0,
1646   VEX_LEN_0F10_P_3,
1647   VEX_LEN_0F11_P_1,
1648   VEX_LEN_0F11_P_3,
1649   VEX_LEN_0F12_P_0_M_0,
1650   VEX_LEN_0F12_P_0_M_1,
1651   VEX_LEN_0F12_P_2,
1652   VEX_LEN_0F13_M_0,
1653   VEX_LEN_0F16_P_0_M_0,
1654   VEX_LEN_0F16_P_0_M_1,
1655   VEX_LEN_0F16_P_2,
1656   VEX_LEN_0F17_M_0,
1657   VEX_LEN_0F2A_P_1,
1658   VEX_LEN_0F2A_P_3,
1659   VEX_LEN_0F2C_P_1,
1660   VEX_LEN_0F2C_P_3,
1661   VEX_LEN_0F2D_P_1,
1662   VEX_LEN_0F2D_P_3,
1663   VEX_LEN_0F2E_P_0,
1664   VEX_LEN_0F2E_P_2,
1665   VEX_LEN_0F2F_P_0,
1666   VEX_LEN_0F2F_P_2,
1667   VEX_LEN_0F41_P_0,
1668   VEX_LEN_0F41_P_2,
1669   VEX_LEN_0F42_P_0,
1670   VEX_LEN_0F42_P_2,
1671   VEX_LEN_0F44_P_0,
1672   VEX_LEN_0F44_P_2,
1673   VEX_LEN_0F45_P_0,
1674   VEX_LEN_0F45_P_2,
1675   VEX_LEN_0F46_P_0,
1676   VEX_LEN_0F46_P_2,
1677   VEX_LEN_0F47_P_0,
1678   VEX_LEN_0F47_P_2,
1679   VEX_LEN_0F4A_P_0,
1680   VEX_LEN_0F4A_P_2,
1681   VEX_LEN_0F4B_P_0,
1682   VEX_LEN_0F4B_P_2,
1683   VEX_LEN_0F51_P_1,
1684   VEX_LEN_0F51_P_3,
1685   VEX_LEN_0F52_P_1,
1686   VEX_LEN_0F53_P_1,
1687   VEX_LEN_0F58_P_1,
1688   VEX_LEN_0F58_P_3,
1689   VEX_LEN_0F59_P_1,
1690   VEX_LEN_0F59_P_3,
1691   VEX_LEN_0F5A_P_1,
1692   VEX_LEN_0F5A_P_3,
1693   VEX_LEN_0F5C_P_1,
1694   VEX_LEN_0F5C_P_3,
1695   VEX_LEN_0F5D_P_1,
1696   VEX_LEN_0F5D_P_3,
1697   VEX_LEN_0F5E_P_1,
1698   VEX_LEN_0F5E_P_3,
1699   VEX_LEN_0F5F_P_1,
1700   VEX_LEN_0F5F_P_3,
1701   VEX_LEN_0F6E_P_2,
1702   VEX_LEN_0F7E_P_1,
1703   VEX_LEN_0F7E_P_2,
1704   VEX_LEN_0F90_P_0,
1705   VEX_LEN_0F90_P_2,
1706   VEX_LEN_0F91_P_0,
1707   VEX_LEN_0F91_P_2,
1708   VEX_LEN_0F92_P_0,
1709   VEX_LEN_0F92_P_2,
1710   VEX_LEN_0F92_P_3,
1711   VEX_LEN_0F93_P_0,
1712   VEX_LEN_0F93_P_2,
1713   VEX_LEN_0F93_P_3,
1714   VEX_LEN_0F98_P_0,
1715   VEX_LEN_0F98_P_2,
1716   VEX_LEN_0F99_P_0,
1717   VEX_LEN_0F99_P_2,
1718   VEX_LEN_0FAE_R_2_M_0,
1719   VEX_LEN_0FAE_R_3_M_0,
1720   VEX_LEN_0FC2_P_1,
1721   VEX_LEN_0FC2_P_3,
1722   VEX_LEN_0FC4_P_2,
1723   VEX_LEN_0FC5_P_2,
1724   VEX_LEN_0FD6_P_2,
1725   VEX_LEN_0FF7_P_2,
1726   VEX_LEN_0F3816_P_2,
1727   VEX_LEN_0F3819_P_2,
1728   VEX_LEN_0F381A_P_2_M_0,
1729   VEX_LEN_0F3836_P_2,
1730   VEX_LEN_0F3841_P_2,
1731   VEX_LEN_0F385A_P_2_M_0,
1732   VEX_LEN_0F38DB_P_2,
1733   VEX_LEN_0F38DC_P_2,
1734   VEX_LEN_0F38DD_P_2,
1735   VEX_LEN_0F38DE_P_2,
1736   VEX_LEN_0F38DF_P_2,
1737   VEX_LEN_0F38F2_P_0,
1738   VEX_LEN_0F38F3_R_1_P_0,
1739   VEX_LEN_0F38F3_R_2_P_0,
1740   VEX_LEN_0F38F3_R_3_P_0,
1741   VEX_LEN_0F38F5_P_0,
1742   VEX_LEN_0F38F5_P_1,
1743   VEX_LEN_0F38F5_P_3,
1744   VEX_LEN_0F38F6_P_3,
1745   VEX_LEN_0F38F7_P_0,
1746   VEX_LEN_0F38F7_P_1,
1747   VEX_LEN_0F38F7_P_2,
1748   VEX_LEN_0F38F7_P_3,
1749   VEX_LEN_0F3A00_P_2,
1750   VEX_LEN_0F3A01_P_2,
1751   VEX_LEN_0F3A06_P_2,
1752   VEX_LEN_0F3A0A_P_2,
1753   VEX_LEN_0F3A0B_P_2,
1754   VEX_LEN_0F3A14_P_2,
1755   VEX_LEN_0F3A15_P_2,
1756   VEX_LEN_0F3A16_P_2,
1757   VEX_LEN_0F3A17_P_2,
1758   VEX_LEN_0F3A18_P_2,
1759   VEX_LEN_0F3A19_P_2,
1760   VEX_LEN_0F3A20_P_2,
1761   VEX_LEN_0F3A21_P_2,
1762   VEX_LEN_0F3A22_P_2,
1763   VEX_LEN_0F3A30_P_2,
1764   VEX_LEN_0F3A31_P_2,
1765   VEX_LEN_0F3A32_P_2,
1766   VEX_LEN_0F3A33_P_2,
1767   VEX_LEN_0F3A38_P_2,
1768   VEX_LEN_0F3A39_P_2,
1769   VEX_LEN_0F3A41_P_2,
1770   VEX_LEN_0F3A44_P_2,
1771   VEX_LEN_0F3A46_P_2,
1772   VEX_LEN_0F3A60_P_2,
1773   VEX_LEN_0F3A61_P_2,
1774   VEX_LEN_0F3A62_P_2,
1775   VEX_LEN_0F3A63_P_2,
1776   VEX_LEN_0F3A6A_P_2,
1777   VEX_LEN_0F3A6B_P_2,
1778   VEX_LEN_0F3A6E_P_2,
1779   VEX_LEN_0F3A6F_P_2,
1780   VEX_LEN_0F3A7A_P_2,
1781   VEX_LEN_0F3A7B_P_2,
1782   VEX_LEN_0F3A7E_P_2,
1783   VEX_LEN_0F3A7F_P_2,
1784   VEX_LEN_0F3ADF_P_2,
1785   VEX_LEN_0F3AF0_P_3,
1786   VEX_LEN_0FXOP_08_CC,
1787   VEX_LEN_0FXOP_08_CD,
1788   VEX_LEN_0FXOP_08_CE,
1789   VEX_LEN_0FXOP_08_CF,
1790   VEX_LEN_0FXOP_08_EC,
1791   VEX_LEN_0FXOP_08_ED,
1792   VEX_LEN_0FXOP_08_EE,
1793   VEX_LEN_0FXOP_08_EF,
1794   VEX_LEN_0FXOP_09_80,
1795   VEX_LEN_0FXOP_09_81
1796 };
1797
1798 enum
1799 {
1800   VEX_W_0F10_P_0 = 0,
1801   VEX_W_0F10_P_1,
1802   VEX_W_0F10_P_2,
1803   VEX_W_0F10_P_3,
1804   VEX_W_0F11_P_0,
1805   VEX_W_0F11_P_1,
1806   VEX_W_0F11_P_2,
1807   VEX_W_0F11_P_3,
1808   VEX_W_0F12_P_0_M_0,
1809   VEX_W_0F12_P_0_M_1,
1810   VEX_W_0F12_P_1,
1811   VEX_W_0F12_P_2,
1812   VEX_W_0F12_P_3,
1813   VEX_W_0F13_M_0,
1814   VEX_W_0F14,
1815   VEX_W_0F15,
1816   VEX_W_0F16_P_0_M_0,
1817   VEX_W_0F16_P_0_M_1,
1818   VEX_W_0F16_P_1,
1819   VEX_W_0F16_P_2,
1820   VEX_W_0F17_M_0,
1821   VEX_W_0F28,
1822   VEX_W_0F29,
1823   VEX_W_0F2B_M_0,
1824   VEX_W_0F2E_P_0,
1825   VEX_W_0F2E_P_2,
1826   VEX_W_0F2F_P_0,
1827   VEX_W_0F2F_P_2,
1828   VEX_W_0F41_P_0_LEN_1,
1829   VEX_W_0F41_P_2_LEN_1,
1830   VEX_W_0F42_P_0_LEN_1,
1831   VEX_W_0F42_P_2_LEN_1,
1832   VEX_W_0F44_P_0_LEN_0,
1833   VEX_W_0F44_P_2_LEN_0,
1834   VEX_W_0F45_P_0_LEN_1,
1835   VEX_W_0F45_P_2_LEN_1,
1836   VEX_W_0F46_P_0_LEN_1,
1837   VEX_W_0F46_P_2_LEN_1,
1838   VEX_W_0F47_P_0_LEN_1,
1839   VEX_W_0F47_P_2_LEN_1,
1840   VEX_W_0F4A_P_0_LEN_1,
1841   VEX_W_0F4A_P_2_LEN_1,
1842   VEX_W_0F4B_P_0_LEN_1,
1843   VEX_W_0F4B_P_2_LEN_1,
1844   VEX_W_0F50_M_0,
1845   VEX_W_0F51_P_0,
1846   VEX_W_0F51_P_1,
1847   VEX_W_0F51_P_2,
1848   VEX_W_0F51_P_3,
1849   VEX_W_0F52_P_0,
1850   VEX_W_0F52_P_1,
1851   VEX_W_0F53_P_0,
1852   VEX_W_0F53_P_1,
1853   VEX_W_0F58_P_0,
1854   VEX_W_0F58_P_1,
1855   VEX_W_0F58_P_2,
1856   VEX_W_0F58_P_3,
1857   VEX_W_0F59_P_0,
1858   VEX_W_0F59_P_1,
1859   VEX_W_0F59_P_2,
1860   VEX_W_0F59_P_3,
1861   VEX_W_0F5A_P_0,
1862   VEX_W_0F5A_P_1,
1863   VEX_W_0F5A_P_3,
1864   VEX_W_0F5B_P_0,
1865   VEX_W_0F5B_P_1,
1866   VEX_W_0F5B_P_2,
1867   VEX_W_0F5C_P_0,
1868   VEX_W_0F5C_P_1,
1869   VEX_W_0F5C_P_2,
1870   VEX_W_0F5C_P_3,
1871   VEX_W_0F5D_P_0,
1872   VEX_W_0F5D_P_1,
1873   VEX_W_0F5D_P_2,
1874   VEX_W_0F5D_P_3,
1875   VEX_W_0F5E_P_0,
1876   VEX_W_0F5E_P_1,
1877   VEX_W_0F5E_P_2,
1878   VEX_W_0F5E_P_3,
1879   VEX_W_0F5F_P_0,
1880   VEX_W_0F5F_P_1,
1881   VEX_W_0F5F_P_2,
1882   VEX_W_0F5F_P_3,
1883   VEX_W_0F60_P_2,
1884   VEX_W_0F61_P_2,
1885   VEX_W_0F62_P_2,
1886   VEX_W_0F63_P_2,
1887   VEX_W_0F64_P_2,
1888   VEX_W_0F65_P_2,
1889   VEX_W_0F66_P_2,
1890   VEX_W_0F67_P_2,
1891   VEX_W_0F68_P_2,
1892   VEX_W_0F69_P_2,
1893   VEX_W_0F6A_P_2,
1894   VEX_W_0F6B_P_2,
1895   VEX_W_0F6C_P_2,
1896   VEX_W_0F6D_P_2,
1897   VEX_W_0F6F_P_1,
1898   VEX_W_0F6F_P_2,
1899   VEX_W_0F70_P_1,
1900   VEX_W_0F70_P_2,
1901   VEX_W_0F70_P_3,
1902   VEX_W_0F71_R_2_P_2,
1903   VEX_W_0F71_R_4_P_2,
1904   VEX_W_0F71_R_6_P_2,
1905   VEX_W_0F72_R_2_P_2,
1906   VEX_W_0F72_R_4_P_2,
1907   VEX_W_0F72_R_6_P_2,
1908   VEX_W_0F73_R_2_P_2,
1909   VEX_W_0F73_R_3_P_2,
1910   VEX_W_0F73_R_6_P_2,
1911   VEX_W_0F73_R_7_P_2,
1912   VEX_W_0F74_P_2,
1913   VEX_W_0F75_P_2,
1914   VEX_W_0F76_P_2,
1915   VEX_W_0F77_P_0,
1916   VEX_W_0F7C_P_2,
1917   VEX_W_0F7C_P_3,
1918   VEX_W_0F7D_P_2,
1919   VEX_W_0F7D_P_3,
1920   VEX_W_0F7E_P_1,
1921   VEX_W_0F7F_P_1,
1922   VEX_W_0F7F_P_2,
1923   VEX_W_0F90_P_0_LEN_0,
1924   VEX_W_0F90_P_2_LEN_0,
1925   VEX_W_0F91_P_0_LEN_0,
1926   VEX_W_0F91_P_2_LEN_0,
1927   VEX_W_0F92_P_0_LEN_0,
1928   VEX_W_0F92_P_2_LEN_0,
1929   VEX_W_0F92_P_3_LEN_0,
1930   VEX_W_0F93_P_0_LEN_0,
1931   VEX_W_0F93_P_2_LEN_0,
1932   VEX_W_0F93_P_3_LEN_0,
1933   VEX_W_0F98_P_0_LEN_0,
1934   VEX_W_0F98_P_2_LEN_0,
1935   VEX_W_0F99_P_0_LEN_0,
1936   VEX_W_0F99_P_2_LEN_0,
1937   VEX_W_0FAE_R_2_M_0,
1938   VEX_W_0FAE_R_3_M_0,
1939   VEX_W_0FC2_P_0,
1940   VEX_W_0FC2_P_1,
1941   VEX_W_0FC2_P_2,
1942   VEX_W_0FC2_P_3,
1943   VEX_W_0FC4_P_2,
1944   VEX_W_0FC5_P_2,
1945   VEX_W_0FD0_P_2,
1946   VEX_W_0FD0_P_3,
1947   VEX_W_0FD1_P_2,
1948   VEX_W_0FD2_P_2,
1949   VEX_W_0FD3_P_2,
1950   VEX_W_0FD4_P_2,
1951   VEX_W_0FD5_P_2,
1952   VEX_W_0FD6_P_2,
1953   VEX_W_0FD7_P_2_M_1,
1954   VEX_W_0FD8_P_2,
1955   VEX_W_0FD9_P_2,
1956   VEX_W_0FDA_P_2,
1957   VEX_W_0FDB_P_2,
1958   VEX_W_0FDC_P_2,
1959   VEX_W_0FDD_P_2,
1960   VEX_W_0FDE_P_2,
1961   VEX_W_0FDF_P_2,
1962   VEX_W_0FE0_P_2,
1963   VEX_W_0FE1_P_2,
1964   VEX_W_0FE2_P_2,
1965   VEX_W_0FE3_P_2,
1966   VEX_W_0FE4_P_2,
1967   VEX_W_0FE5_P_2,
1968   VEX_W_0FE6_P_1,
1969   VEX_W_0FE6_P_2,
1970   VEX_W_0FE6_P_3,
1971   VEX_W_0FE7_P_2_M_0,
1972   VEX_W_0FE8_P_2,
1973   VEX_W_0FE9_P_2,
1974   VEX_W_0FEA_P_2,
1975   VEX_W_0FEB_P_2,
1976   VEX_W_0FEC_P_2,
1977   VEX_W_0FED_P_2,
1978   VEX_W_0FEE_P_2,
1979   VEX_W_0FEF_P_2,
1980   VEX_W_0FF0_P_3_M_0,
1981   VEX_W_0FF1_P_2,
1982   VEX_W_0FF2_P_2,
1983   VEX_W_0FF3_P_2,
1984   VEX_W_0FF4_P_2,
1985   VEX_W_0FF5_P_2,
1986   VEX_W_0FF6_P_2,
1987   VEX_W_0FF7_P_2,
1988   VEX_W_0FF8_P_2,
1989   VEX_W_0FF9_P_2,
1990   VEX_W_0FFA_P_2,
1991   VEX_W_0FFB_P_2,
1992   VEX_W_0FFC_P_2,
1993   VEX_W_0FFD_P_2,
1994   VEX_W_0FFE_P_2,
1995   VEX_W_0F3800_P_2,
1996   VEX_W_0F3801_P_2,
1997   VEX_W_0F3802_P_2,
1998   VEX_W_0F3803_P_2,
1999   VEX_W_0F3804_P_2,
2000   VEX_W_0F3805_P_2,
2001   VEX_W_0F3806_P_2,
2002   VEX_W_0F3807_P_2,
2003   VEX_W_0F3808_P_2,
2004   VEX_W_0F3809_P_2,
2005   VEX_W_0F380A_P_2,
2006   VEX_W_0F380B_P_2,
2007   VEX_W_0F380C_P_2,
2008   VEX_W_0F380D_P_2,
2009   VEX_W_0F380E_P_2,
2010   VEX_W_0F380F_P_2,
2011   VEX_W_0F3816_P_2,
2012   VEX_W_0F3817_P_2,
2013   VEX_W_0F3818_P_2,
2014   VEX_W_0F3819_P_2,
2015   VEX_W_0F381A_P_2_M_0,
2016   VEX_W_0F381C_P_2,
2017   VEX_W_0F381D_P_2,
2018   VEX_W_0F381E_P_2,
2019   VEX_W_0F3820_P_2,
2020   VEX_W_0F3821_P_2,
2021   VEX_W_0F3822_P_2,
2022   VEX_W_0F3823_P_2,
2023   VEX_W_0F3824_P_2,
2024   VEX_W_0F3825_P_2,
2025   VEX_W_0F3828_P_2,
2026   VEX_W_0F3829_P_2,
2027   VEX_W_0F382A_P_2_M_0,
2028   VEX_W_0F382B_P_2,
2029   VEX_W_0F382C_P_2_M_0,
2030   VEX_W_0F382D_P_2_M_0,
2031   VEX_W_0F382E_P_2_M_0,
2032   VEX_W_0F382F_P_2_M_0,
2033   VEX_W_0F3830_P_2,
2034   VEX_W_0F3831_P_2,
2035   VEX_W_0F3832_P_2,
2036   VEX_W_0F3833_P_2,
2037   VEX_W_0F3834_P_2,
2038   VEX_W_0F3835_P_2,
2039   VEX_W_0F3836_P_2,
2040   VEX_W_0F3837_P_2,
2041   VEX_W_0F3838_P_2,
2042   VEX_W_0F3839_P_2,
2043   VEX_W_0F383A_P_2,
2044   VEX_W_0F383B_P_2,
2045   VEX_W_0F383C_P_2,
2046   VEX_W_0F383D_P_2,
2047   VEX_W_0F383E_P_2,
2048   VEX_W_0F383F_P_2,
2049   VEX_W_0F3840_P_2,
2050   VEX_W_0F3841_P_2,
2051   VEX_W_0F3846_P_2,
2052   VEX_W_0F3858_P_2,
2053   VEX_W_0F3859_P_2,
2054   VEX_W_0F385A_P_2_M_0,
2055   VEX_W_0F3878_P_2,
2056   VEX_W_0F3879_P_2,
2057   VEX_W_0F38DB_P_2,
2058   VEX_W_0F38DC_P_2,
2059   VEX_W_0F38DD_P_2,
2060   VEX_W_0F38DE_P_2,
2061   VEX_W_0F38DF_P_2,
2062   VEX_W_0F3A00_P_2,
2063   VEX_W_0F3A01_P_2,
2064   VEX_W_0F3A02_P_2,
2065   VEX_W_0F3A04_P_2,
2066   VEX_W_0F3A05_P_2,
2067   VEX_W_0F3A06_P_2,
2068   VEX_W_0F3A08_P_2,
2069   VEX_W_0F3A09_P_2,
2070   VEX_W_0F3A0A_P_2,
2071   VEX_W_0F3A0B_P_2,
2072   VEX_W_0F3A0C_P_2,
2073   VEX_W_0F3A0D_P_2,
2074   VEX_W_0F3A0E_P_2,
2075   VEX_W_0F3A0F_P_2,
2076   VEX_W_0F3A14_P_2,
2077   VEX_W_0F3A15_P_2,
2078   VEX_W_0F3A18_P_2,
2079   VEX_W_0F3A19_P_2,
2080   VEX_W_0F3A20_P_2,
2081   VEX_W_0F3A21_P_2,
2082   VEX_W_0F3A30_P_2_LEN_0,
2083   VEX_W_0F3A31_P_2_LEN_0,
2084   VEX_W_0F3A32_P_2_LEN_0,
2085   VEX_W_0F3A33_P_2_LEN_0,
2086   VEX_W_0F3A38_P_2,
2087   VEX_W_0F3A39_P_2,
2088   VEX_W_0F3A40_P_2,
2089   VEX_W_0F3A41_P_2,
2090   VEX_W_0F3A42_P_2,
2091   VEX_W_0F3A44_P_2,
2092   VEX_W_0F3A46_P_2,
2093   VEX_W_0F3A48_P_2,
2094   VEX_W_0F3A49_P_2,
2095   VEX_W_0F3A4A_P_2,
2096   VEX_W_0F3A4B_P_2,
2097   VEX_W_0F3A4C_P_2,
2098   VEX_W_0F3A60_P_2,
2099   VEX_W_0F3A61_P_2,
2100   VEX_W_0F3A62_P_2,
2101   VEX_W_0F3A63_P_2,
2102   VEX_W_0F3ADF_P_2,
2103
2104   EVEX_W_0F10_P_0,
2105   EVEX_W_0F10_P_1_M_0,
2106   EVEX_W_0F10_P_1_M_1,
2107   EVEX_W_0F10_P_2,
2108   EVEX_W_0F10_P_3_M_0,
2109   EVEX_W_0F10_P_3_M_1,
2110   EVEX_W_0F11_P_0,
2111   EVEX_W_0F11_P_1_M_0,
2112   EVEX_W_0F11_P_1_M_1,
2113   EVEX_W_0F11_P_2,
2114   EVEX_W_0F11_P_3_M_0,
2115   EVEX_W_0F11_P_3_M_1,
2116   EVEX_W_0F12_P_0_M_0,
2117   EVEX_W_0F12_P_0_M_1,
2118   EVEX_W_0F12_P_1,
2119   EVEX_W_0F12_P_2,
2120   EVEX_W_0F12_P_3,
2121   EVEX_W_0F13_P_0,
2122   EVEX_W_0F13_P_2,
2123   EVEX_W_0F14_P_0,
2124   EVEX_W_0F14_P_2,
2125   EVEX_W_0F15_P_0,
2126   EVEX_W_0F15_P_2,
2127   EVEX_W_0F16_P_0_M_0,
2128   EVEX_W_0F16_P_0_M_1,
2129   EVEX_W_0F16_P_1,
2130   EVEX_W_0F16_P_2,
2131   EVEX_W_0F17_P_0,
2132   EVEX_W_0F17_P_2,
2133   EVEX_W_0F28_P_0,
2134   EVEX_W_0F28_P_2,
2135   EVEX_W_0F29_P_0,
2136   EVEX_W_0F29_P_2,
2137   EVEX_W_0F2A_P_1,
2138   EVEX_W_0F2A_P_3,
2139   EVEX_W_0F2B_P_0,
2140   EVEX_W_0F2B_P_2,
2141   EVEX_W_0F2E_P_0,
2142   EVEX_W_0F2E_P_2,
2143   EVEX_W_0F2F_P_0,
2144   EVEX_W_0F2F_P_2,
2145   EVEX_W_0F51_P_0,
2146   EVEX_W_0F51_P_1,
2147   EVEX_W_0F51_P_2,
2148   EVEX_W_0F51_P_3,
2149   EVEX_W_0F54_P_0,
2150   EVEX_W_0F54_P_2,
2151   EVEX_W_0F55_P_0,
2152   EVEX_W_0F55_P_2,
2153   EVEX_W_0F56_P_0,
2154   EVEX_W_0F56_P_2,
2155   EVEX_W_0F57_P_0,
2156   EVEX_W_0F57_P_2,
2157   EVEX_W_0F58_P_0,
2158   EVEX_W_0F58_P_1,
2159   EVEX_W_0F58_P_2,
2160   EVEX_W_0F58_P_3,
2161   EVEX_W_0F59_P_0,
2162   EVEX_W_0F59_P_1,
2163   EVEX_W_0F59_P_2,
2164   EVEX_W_0F59_P_3,
2165   EVEX_W_0F5A_P_0,
2166   EVEX_W_0F5A_P_1,
2167   EVEX_W_0F5A_P_2,
2168   EVEX_W_0F5A_P_3,
2169   EVEX_W_0F5B_P_0,
2170   EVEX_W_0F5B_P_1,
2171   EVEX_W_0F5B_P_2,
2172   EVEX_W_0F5C_P_0,
2173   EVEX_W_0F5C_P_1,
2174   EVEX_W_0F5C_P_2,
2175   EVEX_W_0F5C_P_3,
2176   EVEX_W_0F5D_P_0,
2177   EVEX_W_0F5D_P_1,
2178   EVEX_W_0F5D_P_2,
2179   EVEX_W_0F5D_P_3,
2180   EVEX_W_0F5E_P_0,
2181   EVEX_W_0F5E_P_1,
2182   EVEX_W_0F5E_P_2,
2183   EVEX_W_0F5E_P_3,
2184   EVEX_W_0F5F_P_0,
2185   EVEX_W_0F5F_P_1,
2186   EVEX_W_0F5F_P_2,
2187   EVEX_W_0F5F_P_3,
2188   EVEX_W_0F62_P_2,
2189   EVEX_W_0F66_P_2,
2190   EVEX_W_0F6A_P_2,
2191   EVEX_W_0F6B_P_2,
2192   EVEX_W_0F6C_P_2,
2193   EVEX_W_0F6D_P_2,
2194   EVEX_W_0F6E_P_2,
2195   EVEX_W_0F6F_P_1,
2196   EVEX_W_0F6F_P_2,
2197   EVEX_W_0F6F_P_3,
2198   EVEX_W_0F70_P_2,
2199   EVEX_W_0F72_R_2_P_2,
2200   EVEX_W_0F72_R_6_P_2,
2201   EVEX_W_0F73_R_2_P_2,
2202   EVEX_W_0F73_R_6_P_2,
2203   EVEX_W_0F76_P_2,
2204   EVEX_W_0F78_P_0,
2205   EVEX_W_0F78_P_2,
2206   EVEX_W_0F79_P_0,
2207   EVEX_W_0F79_P_2,
2208   EVEX_W_0F7A_P_1,
2209   EVEX_W_0F7A_P_2,
2210   EVEX_W_0F7A_P_3,
2211   EVEX_W_0F7B_P_1,
2212   EVEX_W_0F7B_P_2,
2213   EVEX_W_0F7B_P_3,
2214   EVEX_W_0F7E_P_1,
2215   EVEX_W_0F7E_P_2,
2216   EVEX_W_0F7F_P_1,
2217   EVEX_W_0F7F_P_2,
2218   EVEX_W_0F7F_P_3,
2219   EVEX_W_0FC2_P_0,
2220   EVEX_W_0FC2_P_1,
2221   EVEX_W_0FC2_P_2,
2222   EVEX_W_0FC2_P_3,
2223   EVEX_W_0FC6_P_0,
2224   EVEX_W_0FC6_P_2,
2225   EVEX_W_0FD2_P_2,
2226   EVEX_W_0FD3_P_2,
2227   EVEX_W_0FD4_P_2,
2228   EVEX_W_0FD6_P_2,
2229   EVEX_W_0FE6_P_1,
2230   EVEX_W_0FE6_P_2,
2231   EVEX_W_0FE6_P_3,
2232   EVEX_W_0FE7_P_2,
2233   EVEX_W_0FF2_P_2,
2234   EVEX_W_0FF3_P_2,
2235   EVEX_W_0FF4_P_2,
2236   EVEX_W_0FFA_P_2,
2237   EVEX_W_0FFB_P_2,
2238   EVEX_W_0FFE_P_2,
2239   EVEX_W_0F380C_P_2,
2240   EVEX_W_0F380D_P_2,
2241   EVEX_W_0F3810_P_1,
2242   EVEX_W_0F3810_P_2,
2243   EVEX_W_0F3811_P_1,
2244   EVEX_W_0F3811_P_2,
2245   EVEX_W_0F3812_P_1,
2246   EVEX_W_0F3812_P_2,
2247   EVEX_W_0F3813_P_1,
2248   EVEX_W_0F3813_P_2,
2249   EVEX_W_0F3814_P_1,
2250   EVEX_W_0F3815_P_1,
2251   EVEX_W_0F3818_P_2,
2252   EVEX_W_0F3819_P_2,
2253   EVEX_W_0F381A_P_2,
2254   EVEX_W_0F381B_P_2,
2255   EVEX_W_0F381E_P_2,
2256   EVEX_W_0F381F_P_2,
2257   EVEX_W_0F3820_P_1,
2258   EVEX_W_0F3821_P_1,
2259   EVEX_W_0F3822_P_1,
2260   EVEX_W_0F3823_P_1,
2261   EVEX_W_0F3824_P_1,
2262   EVEX_W_0F3825_P_1,
2263   EVEX_W_0F3825_P_2,
2264   EVEX_W_0F3826_P_1,
2265   EVEX_W_0F3826_P_2,
2266   EVEX_W_0F3828_P_1,
2267   EVEX_W_0F3828_P_2,
2268   EVEX_W_0F3829_P_1,
2269   EVEX_W_0F3829_P_2,
2270   EVEX_W_0F382A_P_1,
2271   EVEX_W_0F382A_P_2,
2272   EVEX_W_0F382B_P_2,
2273   EVEX_W_0F3830_P_1,
2274   EVEX_W_0F3831_P_1,
2275   EVEX_W_0F3832_P_1,
2276   EVEX_W_0F3833_P_1,
2277   EVEX_W_0F3834_P_1,
2278   EVEX_W_0F3835_P_1,
2279   EVEX_W_0F3835_P_2,
2280   EVEX_W_0F3837_P_2,
2281   EVEX_W_0F3838_P_1,
2282   EVEX_W_0F3839_P_1,
2283   EVEX_W_0F383A_P_1,
2284   EVEX_W_0F3840_P_2,
2285   EVEX_W_0F3858_P_2,
2286   EVEX_W_0F3859_P_2,
2287   EVEX_W_0F385A_P_2,
2288   EVEX_W_0F385B_P_2,
2289   EVEX_W_0F3866_P_2,
2290   EVEX_W_0F3875_P_2,
2291   EVEX_W_0F3878_P_2,
2292   EVEX_W_0F3879_P_2,
2293   EVEX_W_0F387A_P_2,
2294   EVEX_W_0F387B_P_2,
2295   EVEX_W_0F387D_P_2,
2296   EVEX_W_0F388D_P_2,
2297   EVEX_W_0F3891_P_2,
2298   EVEX_W_0F3893_P_2,
2299   EVEX_W_0F38A1_P_2,
2300   EVEX_W_0F38A3_P_2,
2301   EVEX_W_0F38C7_R_1_P_2,
2302   EVEX_W_0F38C7_R_2_P_2,
2303   EVEX_W_0F38C7_R_5_P_2,
2304   EVEX_W_0F38C7_R_6_P_2,
2305
2306   EVEX_W_0F3A00_P_2,
2307   EVEX_W_0F3A01_P_2,
2308   EVEX_W_0F3A04_P_2,
2309   EVEX_W_0F3A05_P_2,
2310   EVEX_W_0F3A08_P_2,
2311   EVEX_W_0F3A09_P_2,
2312   EVEX_W_0F3A0A_P_2,
2313   EVEX_W_0F3A0B_P_2,
2314   EVEX_W_0F3A16_P_2,
2315   EVEX_W_0F3A18_P_2,
2316   EVEX_W_0F3A19_P_2,
2317   EVEX_W_0F3A1A_P_2,
2318   EVEX_W_0F3A1B_P_2,
2319   EVEX_W_0F3A1D_P_2,
2320   EVEX_W_0F3A21_P_2,
2321   EVEX_W_0F3A22_P_2,
2322   EVEX_W_0F3A23_P_2,
2323   EVEX_W_0F3A38_P_2,
2324   EVEX_W_0F3A39_P_2,
2325   EVEX_W_0F3A3A_P_2,
2326   EVEX_W_0F3A3B_P_2,
2327   EVEX_W_0F3A3E_P_2,
2328   EVEX_W_0F3A3F_P_2,
2329   EVEX_W_0F3A42_P_2,
2330   EVEX_W_0F3A43_P_2,
2331   EVEX_W_0F3A50_P_2,
2332   EVEX_W_0F3A51_P_2,
2333   EVEX_W_0F3A56_P_2,
2334   EVEX_W_0F3A57_P_2,
2335   EVEX_W_0F3A66_P_2,
2336   EVEX_W_0F3A67_P_2
2337 };
2338
2339 typedef void (*op_rtn) (int bytemode, int sizeflag);
2340
2341 struct dis386 {
2342   const char *name;
2343   struct
2344     {
2345       op_rtn rtn;
2346       int bytemode;
2347     } op[MAX_OPERANDS];
2348 };
2349
2350 /* Upper case letters in the instruction names here are macros.
2351    'A' => print 'b' if no register operands or suffix_always is true
2352    'B' => print 'b' if suffix_always is true
2353    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2354           size prefix
2355    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2356           suffix_always is true
2357    'E' => print 'e' if 32-bit form of jcxz
2358    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2359    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2360    'H' => print ",pt" or ",pn" branch hint
2361    'I' => honor following macro letter even in Intel mode (implemented only
2362           for some of the macro letters)
2363    'J' => print 'l'
2364    'K' => print 'd' or 'q' if rex prefix is present.
2365    'L' => print 'l' if suffix_always is true
2366    'M' => print 'r' if intel_mnemonic is false.
2367    'N' => print 'n' if instruction has no wait "prefix"
2368    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2369    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2370           or suffix_always is true.  print 'q' if rex prefix is present.
2371    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2372           is true
2373    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2374    'S' => print 'w', 'l' or 'q' if suffix_always is true
2375    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2376    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2377    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2378    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2379    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2380    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2381           suffix_always is true.
2382    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2383    '!' => change condition from true to false or from false to true.
2384    '%' => add 1 upper case letter to the macro.
2385
2386    2 upper case letter macros:
2387    "XY" => print 'x' or 'y' if no register operands or suffix_always
2388            is true.
2389    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2390    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2391            or suffix_always is true
2392    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2393    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2394    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2395    "LW" => print 'd', 'q' depending on the VEX.W bit
2396    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2397            an operand size prefix, or suffix_always is true.  print
2398            'q' if rex prefix is present.
2399
2400    Many of the above letters print nothing in Intel mode.  See "putop"
2401    for the details.
2402
2403    Braces '{' and '}', and vertical bars '|', indicate alternative
2404    mnemonic strings for AT&T and Intel.  */
2405
2406 static const struct dis386 dis386[] = {
2407   /* 00 */
2408   { "addB",             { Ebh1, Gb } },
2409   { "addS",             { Evh1, Gv } },
2410   { "addB",             { Gb, EbS } },
2411   { "addS",             { Gv, EvS } },
2412   { "addB",             { AL, Ib } },
2413   { "addS",             { eAX, Iv } },
2414   { X86_64_TABLE (X86_64_06) },
2415   { X86_64_TABLE (X86_64_07) },
2416   /* 08 */
2417   { "orB",              { Ebh1, Gb } },
2418   { "orS",              { Evh1, Gv } },
2419   { "orB",              { Gb, EbS } },
2420   { "orS",              { Gv, EvS } },
2421   { "orB",              { AL, Ib } },
2422   { "orS",              { eAX, Iv } },
2423   { X86_64_TABLE (X86_64_0D) },
2424   { Bad_Opcode },       /* 0x0f extended opcode escape */
2425   /* 10 */
2426   { "adcB",             { Ebh1, Gb } },
2427   { "adcS",             { Evh1, Gv } },
2428   { "adcB",             { Gb, EbS } },
2429   { "adcS",             { Gv, EvS } },
2430   { "adcB",             { AL, Ib } },
2431   { "adcS",             { eAX, Iv } },
2432   { X86_64_TABLE (X86_64_16) },
2433   { X86_64_TABLE (X86_64_17) },
2434   /* 18 */
2435   { "sbbB",             { Ebh1, Gb } },
2436   { "sbbS",             { Evh1, Gv } },
2437   { "sbbB",             { Gb, EbS } },
2438   { "sbbS",             { Gv, EvS } },
2439   { "sbbB",             { AL, Ib } },
2440   { "sbbS",             { eAX, Iv } },
2441   { X86_64_TABLE (X86_64_1E) },
2442   { X86_64_TABLE (X86_64_1F) },
2443   /* 20 */
2444   { "andB",             { Ebh1, Gb } },
2445   { "andS",             { Evh1, Gv } },
2446   { "andB",             { Gb, EbS } },
2447   { "andS",             { Gv, EvS } },
2448   { "andB",             { AL, Ib } },
2449   { "andS",             { eAX, Iv } },
2450   { Bad_Opcode },       /* SEG ES prefix */
2451   { X86_64_TABLE (X86_64_27) },
2452   /* 28 */
2453   { "subB",             { Ebh1, Gb } },
2454   { "subS",             { Evh1, Gv } },
2455   { "subB",             { Gb, EbS } },
2456   { "subS",             { Gv, EvS } },
2457   { "subB",             { AL, Ib } },
2458   { "subS",             { eAX, Iv } },
2459   { Bad_Opcode },       /* SEG CS prefix */
2460   { X86_64_TABLE (X86_64_2F) },
2461   /* 30 */
2462   { "xorB",             { Ebh1, Gb } },
2463   { "xorS",             { Evh1, Gv } },
2464   { "xorB",             { Gb, EbS } },
2465   { "xorS",             { Gv, EvS } },
2466   { "xorB",             { AL, Ib } },
2467   { "xorS",             { eAX, Iv } },
2468   { Bad_Opcode },       /* SEG SS prefix */
2469   { X86_64_TABLE (X86_64_37) },
2470   /* 38 */
2471   { "cmpB",             { Eb, Gb } },
2472   { "cmpS",             { Ev, Gv } },
2473   { "cmpB",             { Gb, EbS } },
2474   { "cmpS",             { Gv, EvS } },
2475   { "cmpB",             { AL, Ib } },
2476   { "cmpS",             { eAX, Iv } },
2477   { Bad_Opcode },       /* SEG DS prefix */
2478   { X86_64_TABLE (X86_64_3F) },
2479   /* 40 */
2480   { "inc{S|}",          { RMeAX } },
2481   { "inc{S|}",          { RMeCX } },
2482   { "inc{S|}",          { RMeDX } },
2483   { "inc{S|}",          { RMeBX } },
2484   { "inc{S|}",          { RMeSP } },
2485   { "inc{S|}",          { RMeBP } },
2486   { "inc{S|}",          { RMeSI } },
2487   { "inc{S|}",          { RMeDI } },
2488   /* 48 */
2489   { "dec{S|}",          { RMeAX } },
2490   { "dec{S|}",          { RMeCX } },
2491   { "dec{S|}",          { RMeDX } },
2492   { "dec{S|}",          { RMeBX } },
2493   { "dec{S|}",          { RMeSP } },
2494   { "dec{S|}",          { RMeBP } },
2495   { "dec{S|}",          { RMeSI } },
2496   { "dec{S|}",          { RMeDI } },
2497   /* 50 */
2498   { "pushV",            { RMrAX } },
2499   { "pushV",            { RMrCX } },
2500   { "pushV",            { RMrDX } },
2501   { "pushV",            { RMrBX } },
2502   { "pushV",            { RMrSP } },
2503   { "pushV",            { RMrBP } },
2504   { "pushV",            { RMrSI } },
2505   { "pushV",            { RMrDI } },
2506   /* 58 */
2507   { "popV",             { RMrAX } },
2508   { "popV",             { RMrCX } },
2509   { "popV",             { RMrDX } },
2510   { "popV",             { RMrBX } },
2511   { "popV",             { RMrSP } },
2512   { "popV",             { RMrBP } },
2513   { "popV",             { RMrSI } },
2514   { "popV",             { RMrDI } },
2515   /* 60 */
2516   { X86_64_TABLE (X86_64_60) },
2517   { X86_64_TABLE (X86_64_61) },
2518   { X86_64_TABLE (X86_64_62) },
2519   { X86_64_TABLE (X86_64_63) },
2520   { Bad_Opcode },       /* seg fs */
2521   { Bad_Opcode },       /* seg gs */
2522   { Bad_Opcode },       /* op size prefix */
2523   { Bad_Opcode },       /* adr size prefix */
2524   /* 68 */
2525   { "pushT",            { sIv } },
2526   { "imulS",            { Gv, Ev, Iv } },
2527   { "pushT",            { sIbT } },
2528   { "imulS",            { Gv, Ev, sIb } },
2529   { "ins{b|}",          { Ybr, indirDX } },
2530   { X86_64_TABLE (X86_64_6D) },
2531   { "outs{b|}",         { indirDXr, Xb } },
2532   { X86_64_TABLE (X86_64_6F) },
2533   /* 70 */
2534   { "joH",              { Jb, BND, cond_jump_flag } },
2535   { "jnoH",             { Jb, BND, cond_jump_flag } },
2536   { "jbH",              { Jb, BND, cond_jump_flag } },
2537   { "jaeH",             { Jb, BND, cond_jump_flag } },
2538   { "jeH",              { Jb, BND, cond_jump_flag } },
2539   { "jneH",             { Jb, BND, cond_jump_flag } },
2540   { "jbeH",             { Jb, BND, cond_jump_flag } },
2541   { "jaH",              { Jb, BND, cond_jump_flag } },
2542   /* 78 */
2543   { "jsH",              { Jb, BND, cond_jump_flag } },
2544   { "jnsH",             { Jb, BND, cond_jump_flag } },
2545   { "jpH",              { Jb, BND, cond_jump_flag } },
2546   { "jnpH",             { Jb, BND, cond_jump_flag } },
2547   { "jlH",              { Jb, BND, cond_jump_flag } },
2548   { "jgeH",             { Jb, BND, cond_jump_flag } },
2549   { "jleH",             { Jb, BND, cond_jump_flag } },
2550   { "jgH",              { Jb, BND, cond_jump_flag } },
2551   /* 80 */
2552   { REG_TABLE (REG_80) },
2553   { REG_TABLE (REG_81) },
2554   { Bad_Opcode },
2555   { REG_TABLE (REG_82) },
2556   { "testB",            { Eb, Gb } },
2557   { "testS",            { Ev, Gv } },
2558   { "xchgB",            { Ebh2, Gb } },
2559   { "xchgS",            { Evh2, Gv } },
2560   /* 88 */
2561   { "movB",             { Ebh3, Gb } },
2562   { "movS",             { Evh3, Gv } },
2563   { "movB",             { Gb, EbS } },
2564   { "movS",             { Gv, EvS } },
2565   { "movD",             { Sv, Sw } },
2566   { MOD_TABLE (MOD_8D) },
2567   { "movD",             { Sw, Sv } },
2568   { REG_TABLE (REG_8F) },
2569   /* 90 */
2570   { PREFIX_TABLE (PREFIX_90) },
2571   { "xchgS",            { RMeCX, eAX } },
2572   { "xchgS",            { RMeDX, eAX } },
2573   { "xchgS",            { RMeBX, eAX } },
2574   { "xchgS",            { RMeSP, eAX } },
2575   { "xchgS",            { RMeBP, eAX } },
2576   { "xchgS",            { RMeSI, eAX } },
2577   { "xchgS",            { RMeDI, eAX } },
2578   /* 98 */
2579   { "cW{t|}R",          { XX } },
2580   { "cR{t|}O",          { XX } },
2581   { X86_64_TABLE (X86_64_9A) },
2582   { Bad_Opcode },       /* fwait */
2583   { "pushfT",           { XX } },
2584   { "popfT",            { XX } },
2585   { "sahf",             { XX } },
2586   { "lahf",             { XX } },
2587   /* a0 */
2588   { "mov%LB",           { AL, Ob } },
2589   { "mov%LS",           { eAX, Ov } },
2590   { "mov%LB",           { Ob, AL } },
2591   { "mov%LS",           { Ov, eAX } },
2592   { "movs{b|}",         { Ybr, Xb } },
2593   { "movs{R|}",         { Yvr, Xv } },
2594   { "cmps{b|}",         { Xb, Yb } },
2595   { "cmps{R|}",         { Xv, Yv } },
2596   /* a8 */
2597   { "testB",            { AL, Ib } },
2598   { "testS",            { eAX, Iv } },
2599   { "stosB",            { Ybr, AL } },
2600   { "stosS",            { Yvr, eAX } },
2601   { "lodsB",            { ALr, Xb } },
2602   { "lodsS",            { eAXr, Xv } },
2603   { "scasB",            { AL, Yb } },
2604   { "scasS",            { eAX, Yv } },
2605   /* b0 */
2606   { "movB",             { RMAL, Ib } },
2607   { "movB",             { RMCL, Ib } },
2608   { "movB",             { RMDL, Ib } },
2609   { "movB",             { RMBL, Ib } },
2610   { "movB",             { RMAH, Ib } },
2611   { "movB",             { RMCH, Ib } },
2612   { "movB",             { RMDH, Ib } },
2613   { "movB",             { RMBH, Ib } },
2614   /* b8 */
2615   { "mov%LV",           { RMeAX, Iv64 } },
2616   { "mov%LV",           { RMeCX, Iv64 } },
2617   { "mov%LV",           { RMeDX, Iv64 } },
2618   { "mov%LV",           { RMeBX, Iv64 } },
2619   { "mov%LV",           { RMeSP, Iv64 } },
2620   { "mov%LV",           { RMeBP, Iv64 } },
2621   { "mov%LV",           { RMeSI, Iv64 } },
2622   { "mov%LV",           { RMeDI, Iv64 } },
2623   /* c0 */
2624   { REG_TABLE (REG_C0) },
2625   { REG_TABLE (REG_C1) },
2626   { "retT",             { Iw, BND } },
2627   { "retT",             { BND } },
2628   { X86_64_TABLE (X86_64_C4) },
2629   { X86_64_TABLE (X86_64_C5) },
2630   { REG_TABLE (REG_C6) },
2631   { REG_TABLE (REG_C7) },
2632   /* c8 */
2633   { "enterT",           { Iw, Ib } },
2634   { "leaveT",           { XX } },
2635   { "Jret{|f}P",        { Iw } },
2636   { "Jret{|f}P",        { XX } },
2637   { "int3",             { XX } },
2638   { "int",              { Ib } },
2639   { X86_64_TABLE (X86_64_CE) },
2640   { "iret%LP",          { XX } },
2641   /* d0 */
2642   { REG_TABLE (REG_D0) },
2643   { REG_TABLE (REG_D1) },
2644   { REG_TABLE (REG_D2) },
2645   { REG_TABLE (REG_D3) },
2646   { X86_64_TABLE (X86_64_D4) },
2647   { X86_64_TABLE (X86_64_D5) },
2648   { Bad_Opcode },
2649   { "xlat",             { DSBX } },
2650   /* d8 */
2651   { FLOAT },
2652   { FLOAT },
2653   { FLOAT },
2654   { FLOAT },
2655   { FLOAT },
2656   { FLOAT },
2657   { FLOAT },
2658   { FLOAT },
2659   /* e0 */
2660   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
2661   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
2662   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
2663   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
2664   { "inB",              { AL, Ib } },
2665   { "inG",              { zAX, Ib } },
2666   { "outB",             { Ib, AL } },
2667   { "outG",             { Ib, zAX } },
2668   /* e8 */
2669   { "callT",            { Jv, BND } },
2670   { "jmpT",             { Jv, BND } },
2671   { X86_64_TABLE (X86_64_EA) },
2672   { "jmp",              { Jb, BND } },
2673   { "inB",              { AL, indirDX } },
2674   { "inG",              { zAX, indirDX } },
2675   { "outB",             { indirDX, AL } },
2676   { "outG",             { indirDX, zAX } },
2677   /* f0 */
2678   { Bad_Opcode },       /* lock prefix */
2679   { "icebp",            { XX } },
2680   { Bad_Opcode },       /* repne */
2681   { Bad_Opcode },       /* repz */
2682   { "hlt",              { XX } },
2683   { "cmc",              { XX } },
2684   { REG_TABLE (REG_F6) },
2685   { REG_TABLE (REG_F7) },
2686   /* f8 */
2687   { "clc",              { XX } },
2688   { "stc",              { XX } },
2689   { "cli",              { XX } },
2690   { "sti",              { XX } },
2691   { "cld",              { XX } },
2692   { "std",              { XX } },
2693   { REG_TABLE (REG_FE) },
2694   { REG_TABLE (REG_FF) },
2695 };
2696
2697 static const struct dis386 dis386_twobyte[] = {
2698   /* 00 */
2699   { REG_TABLE (REG_0F00 ) },
2700   { REG_TABLE (REG_0F01 ) },
2701   { "larS",             { Gv, Ew } },
2702   { "lslS",             { Gv, Ew } },
2703   { Bad_Opcode },
2704   { "syscall",          { XX } },
2705   { "clts",             { XX } },
2706   { "sysret%LP",                { XX } },
2707   /* 08 */
2708   { "invd",             { XX } },
2709   { "wbinvd",           { XX } },
2710   { Bad_Opcode },
2711   { "ud2",              { XX } },
2712   { Bad_Opcode },
2713   { REG_TABLE (REG_0F0D) },
2714   { "femms",            { XX } },
2715   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
2716   /* 10 */
2717   { PREFIX_TABLE (PREFIX_0F10) },
2718   { PREFIX_TABLE (PREFIX_0F11) },
2719   { PREFIX_TABLE (PREFIX_0F12) },
2720   { MOD_TABLE (MOD_0F13) },
2721   { "unpcklpX",         { XM, EXx } },
2722   { "unpckhpX",         { XM, EXx } },
2723   { PREFIX_TABLE (PREFIX_0F16) },
2724   { MOD_TABLE (MOD_0F17) },
2725   /* 18 */
2726   { REG_TABLE (REG_0F18) },
2727   { "nopQ",             { Ev } },
2728   { PREFIX_TABLE (PREFIX_0F1A) },
2729   { PREFIX_TABLE (PREFIX_0F1B) },
2730   { "nopQ",             { Ev } },
2731   { "nopQ",             { Ev } },
2732   { "nopQ",             { Ev } },
2733   { "nopQ",             { Ev } },
2734   /* 20 */
2735   { "movZ",             { Rm, Cm } },
2736   { "movZ",             { Rm, Dm } },
2737   { "movZ",             { Cm, Rm } },
2738   { "movZ",             { Dm, Rm } },
2739   { MOD_TABLE (MOD_0F24) },
2740   { Bad_Opcode },
2741   { MOD_TABLE (MOD_0F26) },
2742   { Bad_Opcode },
2743   /* 28 */
2744   { "movapX",           { XM, EXx } },
2745   { "movapX",           { EXxS, XM } },
2746   { PREFIX_TABLE (PREFIX_0F2A) },
2747   { PREFIX_TABLE (PREFIX_0F2B) },
2748   { PREFIX_TABLE (PREFIX_0F2C) },
2749   { PREFIX_TABLE (PREFIX_0F2D) },
2750   { PREFIX_TABLE (PREFIX_0F2E) },
2751   { PREFIX_TABLE (PREFIX_0F2F) },
2752   /* 30 */
2753   { "wrmsr",            { XX } },
2754   { "rdtsc",            { XX } },
2755   { "rdmsr",            { XX } },
2756   { "rdpmc",            { XX } },
2757   { "sysenter",         { XX } },
2758   { "sysexit",          { XX } },
2759   { Bad_Opcode },
2760   { "getsec",           { XX } },
2761   /* 38 */
2762   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2763   { Bad_Opcode },
2764   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2765   { Bad_Opcode },
2766   { Bad_Opcode },
2767   { Bad_Opcode },
2768   { Bad_Opcode },
2769   { Bad_Opcode },
2770   /* 40 */
2771   { "cmovoS",           { Gv, Ev } },
2772   { "cmovnoS",          { Gv, Ev } },
2773   { "cmovbS",           { Gv, Ev } },
2774   { "cmovaeS",          { Gv, Ev } },
2775   { "cmoveS",           { Gv, Ev } },
2776   { "cmovneS",          { Gv, Ev } },
2777   { "cmovbeS",          { Gv, Ev } },
2778   { "cmovaS",           { Gv, Ev } },
2779   /* 48 */
2780   { "cmovsS",           { Gv, Ev } },
2781   { "cmovnsS",          { Gv, Ev } },
2782   { "cmovpS",           { Gv, Ev } },
2783   { "cmovnpS",          { Gv, Ev } },
2784   { "cmovlS",           { Gv, Ev } },
2785   { "cmovgeS",          { Gv, Ev } },
2786   { "cmovleS",          { Gv, Ev } },
2787   { "cmovgS",           { Gv, Ev } },
2788   /* 50 */
2789   { MOD_TABLE (MOD_0F51) },
2790   { PREFIX_TABLE (PREFIX_0F51) },
2791   { PREFIX_TABLE (PREFIX_0F52) },
2792   { PREFIX_TABLE (PREFIX_0F53) },
2793   { "andpX",            { XM, EXx } },
2794   { "andnpX",           { XM, EXx } },
2795   { "orpX",             { XM, EXx } },
2796   { "xorpX",            { XM, EXx } },
2797   /* 58 */
2798   { PREFIX_TABLE (PREFIX_0F58) },
2799   { PREFIX_TABLE (PREFIX_0F59) },
2800   { PREFIX_TABLE (PREFIX_0F5A) },
2801   { PREFIX_TABLE (PREFIX_0F5B) },
2802   { PREFIX_TABLE (PREFIX_0F5C) },
2803   { PREFIX_TABLE (PREFIX_0F5D) },
2804   { PREFIX_TABLE (PREFIX_0F5E) },
2805   { PREFIX_TABLE (PREFIX_0F5F) },
2806   /* 60 */
2807   { PREFIX_TABLE (PREFIX_0F60) },
2808   { PREFIX_TABLE (PREFIX_0F61) },
2809   { PREFIX_TABLE (PREFIX_0F62) },
2810   { "packsswb",         { MX, EM } },
2811   { "pcmpgtb",          { MX, EM } },
2812   { "pcmpgtw",          { MX, EM } },
2813   { "pcmpgtd",          { MX, EM } },
2814   { "packuswb",         { MX, EM } },
2815   /* 68 */
2816   { "punpckhbw",        { MX, EM } },
2817   { "punpckhwd",        { MX, EM } },
2818   { "punpckhdq",        { MX, EM } },
2819   { "packssdw",         { MX, EM } },
2820   { PREFIX_TABLE (PREFIX_0F6C) },
2821   { PREFIX_TABLE (PREFIX_0F6D) },
2822   { "movK",             { MX, Edq } },
2823   { PREFIX_TABLE (PREFIX_0F6F) },
2824   /* 70 */
2825   { PREFIX_TABLE (PREFIX_0F70) },
2826   { REG_TABLE (REG_0F71) },
2827   { REG_TABLE (REG_0F72) },
2828   { REG_TABLE (REG_0F73) },
2829   { "pcmpeqb",          { MX, EM } },
2830   { "pcmpeqw",          { MX, EM } },
2831   { "pcmpeqd",          { MX, EM } },
2832   { "emms",             { XX } },
2833   /* 78 */
2834   { PREFIX_TABLE (PREFIX_0F78) },
2835   { PREFIX_TABLE (PREFIX_0F79) },
2836   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2837   { Bad_Opcode },
2838   { PREFIX_TABLE (PREFIX_0F7C) },
2839   { PREFIX_TABLE (PREFIX_0F7D) },
2840   { PREFIX_TABLE (PREFIX_0F7E) },
2841   { PREFIX_TABLE (PREFIX_0F7F) },
2842   /* 80 */
2843   { "joH",              { Jv, BND, cond_jump_flag } },
2844   { "jnoH",             { Jv, BND, cond_jump_flag } },
2845   { "jbH",              { Jv, BND, cond_jump_flag } },
2846   { "jaeH",             { Jv, BND, cond_jump_flag } },
2847   { "jeH",              { Jv, BND, cond_jump_flag } },
2848   { "jneH",             { Jv, BND, cond_jump_flag } },
2849   { "jbeH",             { Jv, BND, cond_jump_flag } },
2850   { "jaH",              { Jv, BND, cond_jump_flag } },
2851   /* 88 */
2852   { "jsH",              { Jv, BND, cond_jump_flag } },
2853   { "jnsH",             { Jv, BND, cond_jump_flag } },
2854   { "jpH",              { Jv, BND, cond_jump_flag } },
2855   { "jnpH",             { Jv, BND, cond_jump_flag } },
2856   { "jlH",              { Jv, BND, cond_jump_flag } },
2857   { "jgeH",             { Jv, BND, cond_jump_flag } },
2858   { "jleH",             { Jv, BND, cond_jump_flag } },
2859   { "jgH",              { Jv, BND, cond_jump_flag } },
2860   /* 90 */
2861   { "seto",             { Eb } },
2862   { "setno",            { Eb } },
2863   { "setb",             { Eb } },
2864   { "setae",            { Eb } },
2865   { "sete",             { Eb } },
2866   { "setne",            { Eb } },
2867   { "setbe",            { Eb } },
2868   { "seta",             { Eb } },
2869   /* 98 */
2870   { "sets",             { Eb } },
2871   { "setns",            { Eb } },
2872   { "setp",             { Eb } },
2873   { "setnp",            { Eb } },
2874   { "setl",             { Eb } },
2875   { "setge",            { Eb } },
2876   { "setle",            { Eb } },
2877   { "setg",             { Eb } },
2878   /* a0 */
2879   { "pushT",            { fs } },
2880   { "popT",             { fs } },
2881   { "cpuid",            { XX } },
2882   { "btS",              { Ev, Gv } },
2883   { "shldS",            { Ev, Gv, Ib } },
2884   { "shldS",            { Ev, Gv, CL } },
2885   { REG_TABLE (REG_0FA6) },
2886   { REG_TABLE (REG_0FA7) },
2887   /* a8 */
2888   { "pushT",            { gs } },
2889   { "popT",             { gs } },
2890   { "rsm",              { XX } },
2891   { "btsS",             { Evh1, Gv } },
2892   { "shrdS",            { Ev, Gv, Ib } },
2893   { "shrdS",            { Ev, Gv, CL } },
2894   { REG_TABLE (REG_0FAE) },
2895   { "imulS",            { Gv, Ev } },
2896   /* b0 */
2897   { "cmpxchgB",         { Ebh1, Gb } },
2898   { "cmpxchgS",         { Evh1, Gv } },
2899   { MOD_TABLE (MOD_0FB2) },
2900   { "btrS",             { Evh1, Gv } },
2901   { MOD_TABLE (MOD_0FB4) },
2902   { MOD_TABLE (MOD_0FB5) },
2903   { "movz{bR|x}",       { Gv, Eb } },
2904   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2905   /* b8 */
2906   { PREFIX_TABLE (PREFIX_0FB8) },
2907   { "ud1",              { XX } },
2908   { REG_TABLE (REG_0FBA) },
2909   { "btcS",             { Evh1, Gv } },
2910   { PREFIX_TABLE (PREFIX_0FBC) },
2911   { PREFIX_TABLE (PREFIX_0FBD) },
2912   { "movs{bR|x}",       { Gv, Eb } },
2913   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2914   /* c0 */
2915   { "xaddB",            { Ebh1, Gb } },
2916   { "xaddS",            { Evh1, Gv } },
2917   { PREFIX_TABLE (PREFIX_0FC2) },
2918   { PREFIX_TABLE (PREFIX_0FC3) },
2919   { "pinsrw",           { MX, Edqw, Ib } },
2920   { "pextrw",           { Gdq, MS, Ib } },
2921   { "shufpX",           { XM, EXx, Ib } },
2922   { REG_TABLE (REG_0FC7) },
2923   /* c8 */
2924   { "bswap",            { RMeAX } },
2925   { "bswap",            { RMeCX } },
2926   { "bswap",            { RMeDX } },
2927   { "bswap",            { RMeBX } },
2928   { "bswap",            { RMeSP } },
2929   { "bswap",            { RMeBP } },
2930   { "bswap",            { RMeSI } },
2931   { "bswap",            { RMeDI } },
2932   /* d0 */
2933   { PREFIX_TABLE (PREFIX_0FD0) },
2934   { "psrlw",            { MX, EM } },
2935   { "psrld",            { MX, EM } },
2936   { "psrlq",            { MX, EM } },
2937   { "paddq",            { MX, EM } },
2938   { "pmullw",           { MX, EM } },
2939   { PREFIX_TABLE (PREFIX_0FD6) },
2940   { MOD_TABLE (MOD_0FD7) },
2941   /* d8 */
2942   { "psubusb",          { MX, EM } },
2943   { "psubusw",          { MX, EM } },
2944   { "pminub",           { MX, EM } },
2945   { "pand",             { MX, EM } },
2946   { "paddusb",          { MX, EM } },
2947   { "paddusw",          { MX, EM } },
2948   { "pmaxub",           { MX, EM } },
2949   { "pandn",            { MX, EM } },
2950   /* e0 */
2951   { "pavgb",            { MX, EM } },
2952   { "psraw",            { MX, EM } },
2953   { "psrad",            { MX, EM } },
2954   { "pavgw",            { MX, EM } },
2955   { "pmulhuw",          { MX, EM } },
2956   { "pmulhw",           { MX, EM } },
2957   { PREFIX_TABLE (PREFIX_0FE6) },
2958   { PREFIX_TABLE (PREFIX_0FE7) },
2959   /* e8 */
2960   { "psubsb",           { MX, EM } },
2961   { "psubsw",           { MX, EM } },
2962   { "pminsw",           { MX, EM } },
2963   { "por",              { MX, EM } },
2964   { "paddsb",           { MX, EM } },
2965   { "paddsw",           { MX, EM } },
2966   { "pmaxsw",           { MX, EM } },
2967   { "pxor",             { MX, EM } },
2968   /* f0 */
2969   { PREFIX_TABLE (PREFIX_0FF0) },
2970   { "psllw",            { MX, EM } },
2971   { "pslld",            { MX, EM } },
2972   { "psllq",            { MX, EM } },
2973   { "pmuludq",          { MX, EM } },
2974   { "pmaddwd",          { MX, EM } },
2975   { "psadbw",           { MX, EM } },
2976   { PREFIX_TABLE (PREFIX_0FF7) },
2977   /* f8 */
2978   { "psubb",            { MX, EM } },
2979   { "psubw",            { MX, EM } },
2980   { "psubd",            { MX, EM } },
2981   { "psubq",            { MX, EM } },
2982   { "paddb",            { MX, EM } },
2983   { "paddw",            { MX, EM } },
2984   { "paddd",            { MX, EM } },
2985   { Bad_Opcode },
2986 };
2987
2988 static const unsigned char onebyte_has_modrm[256] = {
2989   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2990   /*       -------------------------------        */
2991   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2992   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2993   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2994   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2995   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2996   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2997   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2998   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2999   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3000   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3001   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3002   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3003   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3004   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3005   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3006   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3007   /*       -------------------------------        */
3008   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3009 };
3010
3011 static const unsigned char twobyte_has_modrm[256] = {
3012   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3013   /*       -------------------------------        */
3014   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3015   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3016   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3017   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3018   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3019   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3020   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3021   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3022   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3023   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3024   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3025   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3026   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3027   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3028   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3029   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3030   /*       -------------------------------        */
3031   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3032 };
3033
3034 static const unsigned char twobyte_has_mandatory_prefix[256] = {
3035   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3036   /*       -------------------------------        */
3037   /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
3038   /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
3039   /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */
3040   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3041   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
3042   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3043   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3044   /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */
3045   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3046   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
3047   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
3048   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
3049   /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */
3050   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3051   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3052   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3053   /*       -------------------------------        */
3054   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3055 };
3056
3057 static char obuf[100];
3058 static char *obufp;
3059 static char *mnemonicendp;
3060 static char scratchbuf[100];
3061 static unsigned char *start_codep;
3062 static unsigned char *insn_codep;
3063 static unsigned char *codep;
3064 static unsigned char *end_codep;
3065 static int last_lock_prefix;
3066 static int last_repz_prefix;
3067 static int last_repnz_prefix;
3068 static int last_data_prefix;
3069 static int last_addr_prefix;
3070 static int last_rex_prefix;
3071 static int last_seg_prefix;
3072 static int fwait_prefix;
3073 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory.  */
3074 static int mandatory_prefix;
3075 /* The active segment register prefix.  */
3076 static int active_seg_prefix;
3077 #define MAX_CODE_LENGTH 15
3078 /* We can up to 14 prefixes since the maximum instruction length is
3079    15bytes.  */
3080 static int all_prefixes[MAX_CODE_LENGTH - 1];
3081 static disassemble_info *the_info;
3082 static struct
3083   {
3084     int mod;
3085     int reg;
3086     int rm;
3087   }
3088 modrm;
3089 static unsigned char need_modrm;
3090 static struct
3091   {
3092     int scale;
3093     int index;
3094     int base;
3095   }
3096 sib;
3097 static struct
3098   {
3099     int register_specifier;
3100     int length;
3101     int prefix;
3102     int w;
3103     int evex;
3104     int r;
3105     int v;
3106     int mask_register_specifier;
3107     int zeroing;
3108     int ll;
3109     int b;
3110   }
3111 vex;
3112 static unsigned char need_vex;
3113 static unsigned char need_vex_reg;
3114 static unsigned char vex_w_done;
3115
3116 struct op
3117   {
3118     const char *name;
3119     unsigned int len;
3120   };
3121
3122 /* If we are accessing mod/rm/reg without need_modrm set, then the
3123    values are stale.  Hitting this abort likely indicates that you
3124    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3125 #define MODRM_CHECK  if (!need_modrm) abort ()
3126
3127 static const char **names64;
3128 static const char **names32;
3129 static const char **names16;
3130 static const char **names8;
3131 static const char **names8rex;
3132 static const char **names_seg;
3133 static const char *index64;
3134 static const char *index32;
3135 static const char **index16;
3136 static const char **names_bnd;
3137
3138 static const char *intel_names64[] = {
3139   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3140   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3141 };
3142 static const char *intel_names32[] = {
3143   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3144   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3145 };
3146 static const char *intel_names16[] = {
3147   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3148   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3149 };
3150 static const char *intel_names8[] = {
3151   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3152 };
3153 static const char *intel_names8rex[] = {
3154   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3155   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3156 };
3157 static const char *intel_names_seg[] = {
3158   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3159 };
3160 static const char *intel_index64 = "riz";
3161 static const char *intel_index32 = "eiz";
3162 static const char *intel_index16[] = {
3163   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3164 };
3165
3166 static const char *att_names64[] = {
3167   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3168   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3169 };
3170 static const char *att_names32[] = {
3171   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3172   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3173 };
3174 static const char *att_names16[] = {
3175   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3176   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3177 };
3178 static const char *att_names8[] = {
3179   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3180 };
3181 static const char *att_names8rex[] = {
3182   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3183   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3184 };
3185 static const char *att_names_seg[] = {
3186   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3187 };
3188 static const char *att_index64 = "%riz";
3189 static const char *att_index32 = "%eiz";
3190 static const char *att_index16[] = {
3191   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3192 };
3193
3194 static const char **names_mm;
3195 static const char *intel_names_mm[] = {
3196   "mm0", "mm1", "mm2", "mm3",
3197   "mm4", "mm5", "mm6", "mm7"
3198 };
3199 static const char *att_names_mm[] = {
3200   "%mm0", "%mm1", "%mm2", "%mm3",
3201   "%mm4", "%mm5", "%mm6", "%mm7"
3202 };
3203
3204 static const char *intel_names_bnd[] = {
3205   "bnd0", "bnd1", "bnd2", "bnd3"
3206 };
3207
3208 static const char *att_names_bnd[] = {
3209   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3210 };
3211
3212 static const char **names_xmm;
3213 static const char *intel_names_xmm[] = {
3214   "xmm0", "xmm1", "xmm2", "xmm3",
3215   "xmm4", "xmm5", "xmm6", "xmm7",
3216   "xmm8", "xmm9", "xmm10", "xmm11",
3217   "xmm12", "xmm13", "xmm14", "xmm15",
3218   "xmm16", "xmm17", "xmm18", "xmm19",
3219   "xmm20", "xmm21", "xmm22", "xmm23",
3220   "xmm24", "xmm25", "xmm26", "xmm27",
3221   "xmm28", "xmm29", "xmm30", "xmm31"
3222 };
3223 static const char *att_names_xmm[] = {
3224   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3225   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3226   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3227   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3228   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3229   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3230   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3231   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3232 };
3233
3234 static const char **names_ymm;
3235 static const char *intel_names_ymm[] = {
3236   "ymm0", "ymm1", "ymm2", "ymm3",
3237   "ymm4", "ymm5", "ymm6", "ymm7",
3238   "ymm8", "ymm9", "ymm10", "ymm11",
3239   "ymm12", "ymm13", "ymm14", "ymm15",
3240   "ymm16", "ymm17", "ymm18", "ymm19",
3241   "ymm20", "ymm21", "ymm22", "ymm23",
3242   "ymm24", "ymm25", "ymm26", "ymm27",
3243   "ymm28", "ymm29", "ymm30", "ymm31"
3244 };
3245 static const char *att_names_ymm[] = {
3246   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3247   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3248   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3249   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3250   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3251   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3252   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3253   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3254 };
3255
3256 static const char **names_zmm;
3257 static const char *intel_names_zmm[] = {
3258   "zmm0", "zmm1", "zmm2", "zmm3",
3259   "zmm4", "zmm5", "zmm6", "zmm7",
3260   "zmm8", "zmm9", "zmm10", "zmm11",
3261   "zmm12", "zmm13", "zmm14", "zmm15",
3262   "zmm16", "zmm17", "zmm18", "zmm19",
3263   "zmm20", "zmm21", "zmm22", "zmm23",
3264   "zmm24", "zmm25", "zmm26", "zmm27",
3265   "zmm28", "zmm29", "zmm30", "zmm31"
3266 };
3267 static const char *att_names_zmm[] = {
3268   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3269   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3270   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3271   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3272   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3273   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3274   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3275   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3276 };
3277
3278 static const char **names_mask;
3279 static const char *intel_names_mask[] = {
3280   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3281 };
3282 static const char *att_names_mask[] = {
3283   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3284 };
3285
3286 static const char *names_rounding[] =
3287 {
3288   "{rn-sae}",
3289   "{rd-sae}",
3290   "{ru-sae}",
3291   "{rz-sae}"
3292 };
3293
3294 static const struct dis386 reg_table[][8] = {
3295   /* REG_80 */
3296   {
3297     { "addA",   { Ebh1, Ib } },
3298     { "orA",    { Ebh1, Ib } },
3299     { "adcA",   { Ebh1, Ib } },
3300     { "sbbA",   { Ebh1, Ib } },
3301     { "andA",   { Ebh1, Ib } },
3302     { "subA",   { Ebh1, Ib } },
3303     { "xorA",   { Ebh1, Ib } },
3304     { "cmpA",   { Eb, Ib } },
3305   },
3306   /* REG_81 */
3307   {
3308     { "addQ",   { Evh1, Iv } },
3309     { "orQ",    { Evh1, Iv } },
3310     { "adcQ",   { Evh1, Iv } },
3311     { "sbbQ",   { Evh1, Iv } },
3312     { "andQ",   { Evh1, Iv } },
3313     { "subQ",   { Evh1, Iv } },
3314     { "xorQ",   { Evh1, Iv } },
3315     { "cmpQ",   { Ev, Iv } },
3316   },
3317   /* REG_82 */
3318   {
3319     { "addQ",   { Evh1, sIb } },
3320     { "orQ",    { Evh1, sIb } },
3321     { "adcQ",   { Evh1, sIb } },
3322     { "sbbQ",   { Evh1, sIb } },
3323     { "andQ",   { Evh1, sIb } },
3324     { "subQ",   { Evh1, sIb } },
3325     { "xorQ",   { Evh1, sIb } },
3326     { "cmpQ",   { Ev, sIb } },
3327   },
3328   /* REG_8F */
3329   {
3330     { "popU",   { stackEv } },
3331     { XOP_8F_TABLE (XOP_09) },
3332     { Bad_Opcode },
3333     { Bad_Opcode },
3334     { Bad_Opcode },
3335     { XOP_8F_TABLE (XOP_09) },
3336   },
3337   /* REG_C0 */
3338   {
3339     { "rolA",   { Eb, Ib } },
3340     { "rorA",   { Eb, Ib } },
3341     { "rclA",   { Eb, Ib } },
3342     { "rcrA",   { Eb, Ib } },
3343     { "shlA",   { Eb, Ib } },
3344     { "shrA",   { Eb, Ib } },
3345     { Bad_Opcode },
3346     { "sarA",   { Eb, Ib } },
3347   },
3348   /* REG_C1 */
3349   {
3350     { "rolQ",   { Ev, Ib } },
3351     { "rorQ",   { Ev, Ib } },
3352     { "rclQ",   { Ev, Ib } },
3353     { "rcrQ",   { Ev, Ib } },
3354     { "shlQ",   { Ev, Ib } },
3355     { "shrQ",   { Ev, Ib } },
3356     { Bad_Opcode },
3357     { "sarQ",   { Ev, Ib } },
3358   },
3359   /* REG_C6 */
3360   {
3361     { "movA",   { Ebh3, Ib } },
3362     { Bad_Opcode },
3363     { Bad_Opcode },
3364     { Bad_Opcode },
3365     { Bad_Opcode },
3366     { Bad_Opcode },
3367     { Bad_Opcode },
3368     { MOD_TABLE (MOD_C6_REG_7) },
3369   },
3370   /* REG_C7 */
3371   {
3372     { "movQ",   { Evh3, Iv } },
3373     { Bad_Opcode },
3374     { Bad_Opcode },
3375     { Bad_Opcode },
3376     { Bad_Opcode },
3377     { Bad_Opcode },
3378     { Bad_Opcode },
3379     { MOD_TABLE (MOD_C7_REG_7) },
3380   },
3381   /* REG_D0 */
3382   {
3383     { "rolA",   { Eb, I1 } },
3384     { "rorA",   { Eb, I1 } },
3385     { "rclA",   { Eb, I1 } },
3386     { "rcrA",   { Eb, I1 } },
3387     { "shlA",   { Eb, I1 } },
3388     { "shrA",   { Eb, I1 } },
3389     { Bad_Opcode },
3390     { "sarA",   { Eb, I1 } },
3391   },
3392   /* REG_D1 */
3393   {
3394     { "rolQ",   { Ev, I1 } },
3395     { "rorQ",   { Ev, I1 } },
3396     { "rclQ",   { Ev, I1 } },
3397     { "rcrQ",   { Ev, I1 } },
3398     { "shlQ",   { Ev, I1 } },
3399     { "shrQ",   { Ev, I1 } },
3400     { Bad_Opcode },
3401     { "sarQ",   { Ev, I1 } },
3402   },
3403   /* REG_D2 */
3404   {
3405     { "rolA",   { Eb, CL } },
3406     { "rorA",   { Eb, CL } },
3407     { "rclA",   { Eb, CL } },
3408     { "rcrA",   { Eb, CL } },
3409     { "shlA",   { Eb, CL } },
3410     { "shrA",   { Eb, CL } },
3411     { Bad_Opcode },
3412     { "sarA",   { Eb, CL } },
3413   },
3414   /* REG_D3 */
3415   {
3416     { "rolQ",   { Ev, CL } },
3417     { "rorQ",   { Ev, CL } },
3418     { "rclQ",   { Ev, CL } },
3419     { "rcrQ",   { Ev, CL } },
3420     { "shlQ",   { Ev, CL } },
3421     { "shrQ",   { Ev, CL } },
3422     { Bad_Opcode },
3423     { "sarQ",   { Ev, CL } },
3424   },
3425   /* REG_F6 */
3426   {
3427     { "testA",  { Eb, Ib } },
3428     { Bad_Opcode },
3429     { "notA",   { Ebh1 } },
3430     { "negA",   { Ebh1 } },
3431     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
3432     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
3433     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
3434     { "idivA",  { Eb } },       /* and idiv for consistency.               */
3435   },
3436   /* REG_F7 */
3437   {
3438     { "testQ",  { Ev, Iv } },
3439     { Bad_Opcode },
3440     { "notQ",   { Evh1 } },
3441     { "negQ",   { Evh1 } },
3442     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
3443     { "imulQ",  { Ev } },
3444     { "divQ",   { Ev } },
3445     { "idivQ",  { Ev } },
3446   },
3447   /* REG_FE */
3448   {
3449     { "incA",   { Ebh1 } },
3450     { "decA",   { Ebh1 } },
3451   },
3452   /* REG_FF */
3453   {
3454     { "incQ",   { Evh1 } },
3455     { "decQ",   { Evh1 } },
3456     { "call{T|}", { indirEv, BND } },
3457     { MOD_TABLE (MOD_FF_REG_3) },
3458     { "jmp{T|}", { indirEv, BND } },
3459     { MOD_TABLE (MOD_FF_REG_5) },
3460     { "pushU",  { stackEv } },
3461     { Bad_Opcode },
3462   },
3463   /* REG_0F00 */
3464   {
3465     { "sldtD",  { Sv } },
3466     { "strD",   { Sv } },
3467     { "lldt",   { Ew } },
3468     { "ltr",    { Ew } },
3469     { "verr",   { Ew } },
3470     { "verw",   { Ew } },
3471     { Bad_Opcode },
3472     { Bad_Opcode },
3473   },
3474   /* REG_0F01 */
3475   {
3476     { MOD_TABLE (MOD_0F01_REG_0) },
3477     { MOD_TABLE (MOD_0F01_REG_1) },
3478     { MOD_TABLE (MOD_0F01_REG_2) },
3479     { MOD_TABLE (MOD_0F01_REG_3) },
3480     { "smswD",  { Sv } },
3481     { Bad_Opcode },
3482     { "lmsw",   { Ew } },
3483     { MOD_TABLE (MOD_0F01_REG_7) },
3484   },
3485   /* REG_0F0D */
3486   {
3487     { "prefetch",       { Mb } },
3488     { "prefetchw",      { Mb } },
3489     { "prefetchwt1",    { Mb } },
3490     { "prefetch",       { Mb } },
3491     { "prefetch",       { Mb } },
3492     { "prefetch",       { Mb } },
3493     { "prefetch",       { Mb } },
3494     { "prefetch",       { Mb } },
3495   },
3496   /* REG_0F18 */
3497   {
3498     { MOD_TABLE (MOD_0F18_REG_0) },
3499     { MOD_TABLE (MOD_0F18_REG_1) },
3500     { MOD_TABLE (MOD_0F18_REG_2) },
3501     { MOD_TABLE (MOD_0F18_REG_3) },
3502     { MOD_TABLE (MOD_0F18_REG_4) },
3503     { MOD_TABLE (MOD_0F18_REG_5) },
3504     { MOD_TABLE (MOD_0F18_REG_6) },
3505     { MOD_TABLE (MOD_0F18_REG_7) },
3506   },
3507   /* REG_0F71 */
3508   {
3509     { Bad_Opcode },
3510     { Bad_Opcode },
3511     { MOD_TABLE (MOD_0F71_REG_2) },
3512     { Bad_Opcode },
3513     { MOD_TABLE (MOD_0F71_REG_4) },
3514     { Bad_Opcode },
3515     { MOD_TABLE (MOD_0F71_REG_6) },
3516   },
3517   /* REG_0F72 */
3518   {
3519     { Bad_Opcode },
3520     { Bad_Opcode },
3521     { MOD_TABLE (MOD_0F72_REG_2) },
3522     { Bad_Opcode },
3523     { MOD_TABLE (MOD_0F72_REG_4) },
3524     { Bad_Opcode },
3525     { MOD_TABLE (MOD_0F72_REG_6) },
3526   },
3527   /* REG_0F73 */
3528   {
3529     { Bad_Opcode },
3530     { Bad_Opcode },
3531     { MOD_TABLE (MOD_0F73_REG_2) },
3532     { MOD_TABLE (MOD_0F73_REG_3) },
3533     { Bad_Opcode },
3534     { Bad_Opcode },
3535     { MOD_TABLE (MOD_0F73_REG_6) },
3536     { MOD_TABLE (MOD_0F73_REG_7) },
3537   },
3538   /* REG_0FA6 */
3539   {
3540     { "montmul",        { { OP_0f07, 0 } } },
3541     { "xsha1",          { { OP_0f07, 0 } } },
3542     { "xsha256",        { { OP_0f07, 0 } } },
3543   },
3544   /* REG_0FA7 */
3545   {
3546     { "xstore-rng",     { { OP_0f07, 0 } } },
3547     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
3548     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
3549     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
3550     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
3551     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
3552   },
3553   /* REG_0FAE */
3554   {
3555     { MOD_TABLE (MOD_0FAE_REG_0) },
3556     { MOD_TABLE (MOD_0FAE_REG_1) },
3557     { MOD_TABLE (MOD_0FAE_REG_2) },
3558     { MOD_TABLE (MOD_0FAE_REG_3) },
3559     { MOD_TABLE (MOD_0FAE_REG_4) },
3560     { MOD_TABLE (MOD_0FAE_REG_5) },
3561     { MOD_TABLE (MOD_0FAE_REG_6) },
3562     { MOD_TABLE (MOD_0FAE_REG_7) },
3563   },
3564   /* REG_0FBA */
3565   {
3566     { Bad_Opcode },
3567     { Bad_Opcode },
3568     { Bad_Opcode },
3569     { Bad_Opcode },
3570     { "btQ",    { Ev, Ib } },
3571     { "btsQ",   { Evh1, Ib } },
3572     { "btrQ",   { Evh1, Ib } },
3573     { "btcQ",   { Evh1, Ib } },
3574   },
3575   /* REG_0FC7 */
3576   {
3577     { Bad_Opcode },
3578     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3579     { Bad_Opcode },
3580     { MOD_TABLE (MOD_0FC7_REG_3) },
3581     { MOD_TABLE (MOD_0FC7_REG_4) },
3582     { MOD_TABLE (MOD_0FC7_REG_5) },
3583     { MOD_TABLE (MOD_0FC7_REG_6) },
3584     { MOD_TABLE (MOD_0FC7_REG_7) },
3585   },
3586   /* REG_VEX_0F71 */
3587   {
3588     { Bad_Opcode },
3589     { Bad_Opcode },
3590     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3591     { Bad_Opcode },
3592     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3593     { Bad_Opcode },
3594     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3595   },
3596   /* REG_VEX_0F72 */
3597   {
3598     { Bad_Opcode },
3599     { Bad_Opcode },
3600     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3601     { Bad_Opcode },
3602     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3603     { Bad_Opcode },
3604     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3605   },
3606   /* REG_VEX_0F73 */
3607   {
3608     { Bad_Opcode },
3609     { Bad_Opcode },
3610     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3611     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3612     { Bad_Opcode },
3613     { Bad_Opcode },
3614     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3615     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3616   },
3617   /* REG_VEX_0FAE */
3618   {
3619     { Bad_Opcode },
3620     { Bad_Opcode },
3621     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3622     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3623   },
3624   /* REG_VEX_0F38F3 */
3625   {
3626     { Bad_Opcode },
3627     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3628     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3629     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3630   },
3631   /* REG_XOP_LWPCB */
3632   {
3633     { "llwpcb", { { OP_LWPCB_E, 0 } } },
3634     { "slwpcb", { { OP_LWPCB_E, 0 } } },
3635   },
3636   /* REG_XOP_LWP */
3637   {
3638     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3639     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3640   },
3641   /* REG_XOP_TBM_01 */
3642   {
3643     { Bad_Opcode },
3644     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
3645     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
3646     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
3647     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
3648     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
3649     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
3650     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3651   },
3652   /* REG_XOP_TBM_02 */
3653   {
3654     { Bad_Opcode },
3655     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3656     { Bad_Opcode },
3657     { Bad_Opcode },
3658     { Bad_Opcode },
3659     { Bad_Opcode },
3660     { "blci",   { { OP_LWP_E, 0 }, Ev } },
3661   },
3662 #define NEED_REG_TABLE
3663 #include "i386-dis-evex.h"
3664 #undef NEED_REG_TABLE
3665 };
3666
3667 static const struct dis386 prefix_table[][4] = {
3668   /* PREFIX_90 */
3669   {
3670     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3671     { "pause", { XX } },
3672     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3673   },
3674
3675   /* PREFIX_0F10 */
3676   {
3677     { "movups", { XM, EXx } },
3678     { "movss",  { XM, EXd } },
3679     { "movupd", { XM, EXx } },
3680     { "movsd",  { XM, EXq } },
3681   },
3682
3683   /* PREFIX_0F11 */
3684   {
3685     { "movups", { EXxS, XM } },
3686     { "movss",  { EXdS, XM } },
3687     { "movupd", { EXxS, XM } },
3688     { "movsd",  { EXqS, XM } },
3689   },
3690
3691   /* PREFIX_0F12 */
3692   {
3693     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3694     { "movsldup", { XM, EXx } },
3695     { "movlpd", { XM, EXq } },
3696     { "movddup", { XM, EXq } },
3697   },
3698
3699   /* PREFIX_0F16 */
3700   {
3701     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3702     { "movshdup", { XM, EXx } },
3703     { "movhpd", { XM, EXq } },
3704   },
3705
3706   /* PREFIX_0F1A */
3707   {
3708     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3709     { "bndcl",  { Gbnd, Ev_bnd } },
3710     { "bndmov", { Gbnd, Ebnd } },
3711     { "bndcu",  { Gbnd, Ev_bnd } },
3712   },
3713
3714   /* PREFIX_0F1B */
3715   {
3716     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3717     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3718     { "bndmov", { Ebnd, Gbnd } },
3719     { "bndcn",  { Gbnd, Ev_bnd } },
3720   },
3721
3722   /* PREFIX_0F2A */
3723   {
3724     { "cvtpi2ps", { XM, EMCq } },
3725     { "cvtsi2ss%LQ", { XM, Ev } },
3726     { "cvtpi2pd", { XM, EMCq } },
3727     { "cvtsi2sd%LQ", { XM, Ev } },
3728   },
3729
3730   /* PREFIX_0F2B */
3731   {
3732     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3733     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3734     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3735     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3736   },
3737
3738   /* PREFIX_0F2C */
3739   {
3740     { "cvttps2pi", { MXC, EXq } },
3741     { "cvttss2siY", { Gv, EXd } },
3742     { "cvttpd2pi", { MXC, EXx } },
3743     { "cvttsd2siY", { Gv, EXq } },
3744   },
3745
3746   /* PREFIX_0F2D */
3747   {
3748     { "cvtps2pi", { MXC, EXq } },
3749     { "cvtss2siY", { Gv, EXd } },
3750     { "cvtpd2pi", { MXC, EXx } },
3751     { "cvtsd2siY", { Gv, EXq } },
3752   },
3753
3754   /* PREFIX_0F2E */
3755   {
3756     { "ucomiss",{ XM, EXd } },
3757     { Bad_Opcode },
3758     { "ucomisd",{ XM, EXq } },
3759   },
3760
3761   /* PREFIX_0F2F */
3762   {
3763     { "comiss", { XM, EXd } },
3764     { Bad_Opcode },
3765     { "comisd", { XM, EXq } },
3766   },
3767
3768   /* PREFIX_0F51 */
3769   {
3770     { "sqrtps", { XM, EXx } },
3771     { "sqrtss", { XM, EXd } },
3772     { "sqrtpd", { XM, EXx } },
3773     { "sqrtsd", { XM, EXq } },
3774   },
3775
3776   /* PREFIX_0F52 */
3777   {
3778     { "rsqrtps",{ XM, EXx } },
3779     { "rsqrtss",{ XM, EXd } },
3780   },
3781
3782   /* PREFIX_0F53 */
3783   {
3784     { "rcpps",  { XM, EXx } },
3785     { "rcpss",  { XM, EXd } },
3786   },
3787
3788   /* PREFIX_0F58 */
3789   {
3790     { "addps", { XM, EXx } },
3791     { "addss", { XM, EXd } },
3792     { "addpd", { XM, EXx } },
3793     { "addsd", { XM, EXq } },
3794   },
3795
3796   /* PREFIX_0F59 */
3797   {
3798     { "mulps",  { XM, EXx } },
3799     { "mulss",  { XM, EXd } },
3800     { "mulpd",  { XM, EXx } },
3801     { "mulsd",  { XM, EXq } },
3802   },
3803
3804   /* PREFIX_0F5A */
3805   {
3806     { "cvtps2pd", { XM, EXq } },
3807     { "cvtss2sd", { XM, EXd } },
3808     { "cvtpd2ps", { XM, EXx } },
3809     { "cvtsd2ss", { XM, EXq } },
3810   },
3811
3812   /* PREFIX_0F5B */
3813   {
3814     { "cvtdq2ps", { XM, EXx } },
3815     { "cvttps2dq", { XM, EXx } },
3816     { "cvtps2dq", { XM, EXx } },
3817   },
3818
3819   /* PREFIX_0F5C */
3820   {
3821     { "subps",  { XM, EXx } },
3822     { "subss",  { XM, EXd } },
3823     { "subpd",  { XM, EXx } },
3824     { "subsd",  { XM, EXq } },
3825   },
3826
3827   /* PREFIX_0F5D */
3828   {
3829     { "minps",  { XM, EXx } },
3830     { "minss",  { XM, EXd } },
3831     { "minpd",  { XM, EXx } },
3832     { "minsd",  { XM, EXq } },
3833   },
3834
3835   /* PREFIX_0F5E */
3836   {
3837     { "divps",  { XM, EXx } },
3838     { "divss",  { XM, EXd } },
3839     { "divpd",  { XM, EXx } },
3840     { "divsd",  { XM, EXq } },
3841   },
3842
3843   /* PREFIX_0F5F */
3844   {
3845     { "maxps",  { XM, EXx } },
3846     { "maxss",  { XM, EXd } },
3847     { "maxpd",  { XM, EXx } },
3848     { "maxsd",  { XM, EXq } },
3849   },
3850
3851   /* PREFIX_0F60 */
3852   {
3853     { "punpcklbw",{ MX, EMd } },
3854     { Bad_Opcode },
3855     { "punpcklbw",{ MX, EMx } },
3856   },
3857
3858   /* PREFIX_0F61 */
3859   {
3860     { "punpcklwd",{ MX, EMd } },
3861     { Bad_Opcode },
3862     { "punpcklwd",{ MX, EMx } },
3863   },
3864
3865   /* PREFIX_0F62 */
3866   {
3867     { "punpckldq",{ MX, EMd } },
3868     { Bad_Opcode },
3869     { "punpckldq",{ MX, EMx } },
3870   },
3871
3872   /* PREFIX_0F6C */
3873   {
3874     { Bad_Opcode },
3875     { Bad_Opcode },
3876     { "punpcklqdq", { XM, EXx } },
3877   },
3878
3879   /* PREFIX_0F6D */
3880   {
3881     { Bad_Opcode },
3882     { Bad_Opcode },
3883     { "punpckhqdq", { XM, EXx } },
3884   },
3885
3886   /* PREFIX_0F6F */
3887   {
3888     { "movq",   { MX, EM } },
3889     { "movdqu", { XM, EXx } },
3890     { "movdqa", { XM, EXx } },
3891   },
3892
3893   /* PREFIX_0F70 */
3894   {
3895     { "pshufw", { MX, EM, Ib } },
3896     { "pshufhw",{ XM, EXx, Ib } },
3897     { "pshufd", { XM, EXx, Ib } },
3898     { "pshuflw",{ XM, EXx, Ib } },
3899   },
3900
3901   /* PREFIX_0F73_REG_3 */
3902   {
3903     { Bad_Opcode },
3904     { Bad_Opcode },
3905     { "psrldq", { XS, Ib } },
3906   },
3907
3908   /* PREFIX_0F73_REG_7 */
3909   {
3910     { Bad_Opcode },
3911     { Bad_Opcode },
3912     { "pslldq", { XS, Ib } },
3913   },
3914
3915   /* PREFIX_0F78 */
3916   {
3917     {"vmread",  { Em, Gm } },
3918     { Bad_Opcode },
3919     {"extrq",   { XS, Ib, Ib } },
3920     {"insertq", { XM, XS, Ib, Ib } },
3921   },
3922
3923   /* PREFIX_0F79 */
3924   {
3925     {"vmwrite", { Gm, Em } },
3926     { Bad_Opcode },
3927     {"extrq",   { XM, XS } },
3928     {"insertq", { XM, XS } },
3929   },
3930
3931   /* PREFIX_0F7C */
3932   {
3933     { Bad_Opcode },
3934     { Bad_Opcode },
3935     { "haddpd", { XM, EXx } },
3936     { "haddps", { XM, EXx } },
3937   },
3938
3939   /* PREFIX_0F7D */
3940   {
3941     { Bad_Opcode },
3942     { Bad_Opcode },
3943     { "hsubpd", { XM, EXx } },
3944     { "hsubps", { XM, EXx } },
3945   },
3946
3947   /* PREFIX_0F7E */
3948   {
3949     { "movK",   { Edq, MX } },
3950     { "movq",   { XM, EXq } },
3951     { "movK",   { Edq, XM } },
3952   },
3953
3954   /* PREFIX_0F7F */
3955   {
3956     { "movq",   { EMS, MX } },
3957     { "movdqu", { EXxS, XM } },
3958     { "movdqa", { EXxS, XM } },
3959   },
3960
3961   /* PREFIX_0FAE_REG_0 */
3962   {
3963     { Bad_Opcode },
3964     { "rdfsbase", { Ev } },
3965   },
3966
3967   /* PREFIX_0FAE_REG_1 */
3968   {
3969     { Bad_Opcode },
3970     { "rdgsbase", { Ev } },
3971   },
3972
3973   /* PREFIX_0FAE_REG_2 */
3974   {
3975     { Bad_Opcode },
3976     { "wrfsbase", { Ev } },
3977   },
3978
3979   /* PREFIX_0FAE_REG_3 */
3980   {
3981     { Bad_Opcode },
3982     { "wrgsbase", { Ev } },
3983   },
3984
3985   /* PREFIX_0FAE_REG_7 */
3986   {
3987     { "clflush",        { Mb } },
3988     { Bad_Opcode },
3989     { "clflushopt",     { Mb } },
3990   },
3991
3992   /* PREFIX_0FB8 */
3993   {
3994     { Bad_Opcode },
3995     { "popcntS", { Gv, Ev } },
3996   },
3997
3998   /* PREFIX_0FBC */
3999   {
4000     { "bsfS",   { Gv, Ev } },
4001     { "tzcntS", { Gv, Ev } },
4002     { "bsfS",   { Gv, Ev } },
4003   },
4004
4005   /* PREFIX_0FBD */
4006   {
4007     { "bsrS",   { Gv, Ev } },
4008     { "lzcntS", { Gv, Ev } },
4009     { "bsrS",   { Gv, Ev } },
4010   },
4011
4012   /* PREFIX_0FC2 */
4013   {
4014     { "cmpps",  { XM, EXx, CMP } },
4015     { "cmpss",  { XM, EXd, CMP } },
4016     { "cmppd",  { XM, EXx, CMP } },
4017     { "cmpsd",  { XM, EXq, CMP } },
4018   },
4019
4020   /* PREFIX_0FC3 */
4021   {
4022     { "movntiS", { Ma, Gv } },
4023   },
4024
4025   /* PREFIX_0FC7_REG_6 */
4026   {
4027     { "vmptrld",{ Mq } },
4028     { "vmxon",  { Mq } },
4029     { "vmclear",{ Mq } },
4030   },
4031
4032   /* PREFIX_0FD0 */
4033   {
4034     { Bad_Opcode },
4035     { Bad_Opcode },
4036     { "addsubpd", { XM, EXx } },
4037     { "addsubps", { XM, EXx } },
4038   },
4039
4040   /* PREFIX_0FD6 */
4041   {
4042     { Bad_Opcode },
4043     { "movq2dq",{ XM, MS } },
4044     { "movq",   { EXqS, XM } },
4045     { "movdq2q",{ MX, XS } },
4046   },
4047
4048   /* PREFIX_0FE6 */
4049   {
4050     { Bad_Opcode },
4051     { "cvtdq2pd", { XM, EXq } },
4052     { "cvttpd2dq", { XM, EXx } },
4053     { "cvtpd2dq", { XM, EXx } },
4054   },
4055
4056   /* PREFIX_0FE7 */
4057   {
4058     { "movntq", { Mq, MX } },
4059     { Bad_Opcode },
4060     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4061   },
4062
4063   /* PREFIX_0FF0 */
4064   {
4065     { Bad_Opcode },
4066     { Bad_Opcode },
4067     { Bad_Opcode },
4068     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4069   },
4070
4071   /* PREFIX_0FF7 */
4072   {
4073     { "maskmovq", { MX, MS } },
4074     { Bad_Opcode },
4075     { "maskmovdqu", { XM, XS } },
4076   },
4077
4078   /* PREFIX_0F3810 */
4079   {
4080     { Bad_Opcode },
4081     { Bad_Opcode },
4082     { "pblendvb", { XM, EXx, XMM0 } },
4083   },
4084
4085   /* PREFIX_0F3814 */
4086   {
4087     { Bad_Opcode },
4088     { Bad_Opcode },
4089     { "blendvps", { XM, EXx, XMM0 } },
4090   },
4091
4092   /* PREFIX_0F3815 */
4093   {
4094     { Bad_Opcode },
4095     { Bad_Opcode },
4096     { "blendvpd", { XM, EXx, XMM0 } },
4097   },
4098
4099   /* PREFIX_0F3817 */
4100   {
4101     { Bad_Opcode },
4102     { Bad_Opcode },
4103     { "ptest",  { XM, EXx } },
4104   },
4105
4106   /* PREFIX_0F3820 */
4107   {
4108     { Bad_Opcode },
4109     { Bad_Opcode },
4110     { "pmovsxbw", { XM, EXq } },
4111   },
4112
4113   /* PREFIX_0F3821 */
4114   {
4115     { Bad_Opcode },
4116     { Bad_Opcode },
4117     { "pmovsxbd", { XM, EXd } },
4118   },
4119
4120   /* PREFIX_0F3822 */
4121   {
4122     { Bad_Opcode },
4123     { Bad_Opcode },
4124     { "pmovsxbq", { XM, EXw } },
4125   },
4126
4127   /* PREFIX_0F3823 */
4128   {
4129     { Bad_Opcode },
4130     { Bad_Opcode },
4131     { "pmovsxwd", { XM, EXq } },
4132   },
4133
4134   /* PREFIX_0F3824 */
4135   {
4136     { Bad_Opcode },
4137     { Bad_Opcode },
4138     { "pmovsxwq", { XM, EXd } },
4139   },
4140
4141   /* PREFIX_0F3825 */
4142   {
4143     { Bad_Opcode },
4144     { Bad_Opcode },
4145     { "pmovsxdq", { XM, EXq } },
4146   },
4147
4148   /* PREFIX_0F3828 */
4149   {
4150     { Bad_Opcode },
4151     { Bad_Opcode },
4152     { "pmuldq", { XM, EXx } },
4153   },
4154
4155   /* PREFIX_0F3829 */
4156   {
4157     { Bad_Opcode },
4158     { Bad_Opcode },
4159     { "pcmpeqq", { XM, EXx } },
4160   },
4161
4162   /* PREFIX_0F382A */
4163   {
4164     { Bad_Opcode },
4165     { Bad_Opcode },
4166     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4167   },
4168
4169   /* PREFIX_0F382B */
4170   {
4171     { Bad_Opcode },
4172     { Bad_Opcode },
4173     { "packusdw", { XM, EXx } },
4174   },
4175
4176   /* PREFIX_0F3830 */
4177   {
4178     { Bad_Opcode },
4179     { Bad_Opcode },
4180     { "pmovzxbw", { XM, EXq } },
4181   },
4182
4183   /* PREFIX_0F3831 */
4184   {
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { "pmovzxbd", { XM, EXd } },
4188   },
4189
4190   /* PREFIX_0F3832 */
4191   {
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { "pmovzxbq", { XM, EXw } },
4195   },
4196
4197   /* PREFIX_0F3833 */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { "pmovzxwd", { XM, EXq } },
4202   },
4203
4204   /* PREFIX_0F3834 */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { "pmovzxwq", { XM, EXd } },
4209   },
4210
4211   /* PREFIX_0F3835 */
4212   {
4213     { Bad_Opcode },
4214     { Bad_Opcode },
4215     { "pmovzxdq", { XM, EXq } },
4216   },
4217
4218   /* PREFIX_0F3837 */
4219   {
4220     { Bad_Opcode },
4221     { Bad_Opcode },
4222     { "pcmpgtq", { XM, EXx } },
4223   },
4224
4225   /* PREFIX_0F3838 */
4226   {
4227     { Bad_Opcode },
4228     { Bad_Opcode },
4229     { "pminsb", { XM, EXx } },
4230   },
4231
4232   /* PREFIX_0F3839 */
4233   {
4234     { Bad_Opcode },
4235     { Bad_Opcode },
4236     { "pminsd", { XM, EXx } },
4237   },
4238
4239   /* PREFIX_0F383A */
4240   {
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     { "pminuw", { XM, EXx } },
4244   },
4245
4246   /* PREFIX_0F383B */
4247   {
4248     { Bad_Opcode },
4249     { Bad_Opcode },
4250     { "pminud", { XM, EXx } },
4251   },
4252
4253   /* PREFIX_0F383C */
4254   {
4255     { Bad_Opcode },
4256     { Bad_Opcode },
4257     { "pmaxsb", { XM, EXx } },
4258   },
4259
4260   /* PREFIX_0F383D */
4261   {
4262     { Bad_Opcode },
4263     { Bad_Opcode },
4264     { "pmaxsd", { XM, EXx } },
4265   },
4266
4267   /* PREFIX_0F383E */
4268   {
4269     { Bad_Opcode },
4270     { Bad_Opcode },
4271     { "pmaxuw", { XM, EXx } },
4272   },
4273
4274   /* PREFIX_0F383F */
4275   {
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { "pmaxud", { XM, EXx } },
4279   },
4280
4281   /* PREFIX_0F3840 */
4282   {
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { "pmulld", { XM, EXx } },
4286   },
4287
4288   /* PREFIX_0F3841 */
4289   {
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { "phminposuw", { XM, EXx } },
4293   },
4294
4295   /* PREFIX_0F3880 */
4296   {
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { "invept", { Gm, Mo } },
4300   },
4301
4302   /* PREFIX_0F3881 */
4303   {
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     { "invvpid", { Gm, Mo } },
4307   },
4308
4309   /* PREFIX_0F3882 */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { "invpcid", { Gm, M } },
4314   },
4315
4316   /* PREFIX_0F38C8 */
4317   {
4318     { "sha1nexte", { XM, EXxmm } },
4319   },
4320
4321   /* PREFIX_0F38C9 */
4322   {
4323     { "sha1msg1", { XM, EXxmm } },
4324   },
4325
4326   /* PREFIX_0F38CA */
4327   {
4328     { "sha1msg2", { XM, EXxmm } },
4329   },
4330
4331   /* PREFIX_0F38CB */
4332   {
4333     { "sha256rnds2", { XM, EXxmm, XMM0 } },
4334   },
4335
4336   /* PREFIX_0F38CC */
4337   {
4338     { "sha256msg1", { XM, EXxmm } },
4339   },
4340
4341   /* PREFIX_0F38CD */
4342   {
4343     { "sha256msg2", { XM, EXxmm } },
4344   },
4345
4346   /* PREFIX_0F38DB */
4347   {
4348     { Bad_Opcode },
4349     { Bad_Opcode },
4350     { "aesimc", { XM, EXx } },
4351   },
4352
4353   /* PREFIX_0F38DC */
4354   {
4355     { Bad_Opcode },
4356     { Bad_Opcode },
4357     { "aesenc", { XM, EXx } },
4358   },
4359
4360   /* PREFIX_0F38DD */
4361   {
4362     { Bad_Opcode },
4363     { Bad_Opcode },
4364     { "aesenclast", { XM, EXx } },
4365   },
4366
4367   /* PREFIX_0F38DE */
4368   {
4369     { Bad_Opcode },
4370     { Bad_Opcode },
4371     { "aesdec", { XM, EXx } },
4372   },
4373
4374   /* PREFIX_0F38DF */
4375   {
4376     { Bad_Opcode },
4377     { Bad_Opcode },
4378     { "aesdeclast", { XM, EXx } },
4379   },
4380
4381   /* PREFIX_0F38F0 */
4382   {
4383     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4384     { Bad_Opcode },
4385     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4386     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
4387   },
4388
4389   /* PREFIX_0F38F1 */
4390   {
4391     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4392     { Bad_Opcode },
4393     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4394     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
4395   },
4396
4397   /* PREFIX_0F38F6 */
4398   {
4399     { Bad_Opcode },
4400     { "adoxS",  { Gdq, Edq} },
4401     { "adcxS",  { Gdq, Edq} },
4402     { Bad_Opcode },
4403   },
4404
4405   /* PREFIX_0F3A08 */
4406   {
4407     { Bad_Opcode },
4408     { Bad_Opcode },
4409     { "roundps", { XM, EXx, Ib } },
4410   },
4411
4412   /* PREFIX_0F3A09 */
4413   {
4414     { Bad_Opcode },
4415     { Bad_Opcode },
4416     { "roundpd", { XM, EXx, Ib } },
4417   },
4418
4419   /* PREFIX_0F3A0A */
4420   {
4421     { Bad_Opcode },
4422     { Bad_Opcode },
4423     { "roundss", { XM, EXd, Ib } },
4424   },
4425
4426   /* PREFIX_0F3A0B */
4427   {
4428     { Bad_Opcode },
4429     { Bad_Opcode },
4430     { "roundsd", { XM, EXq, Ib } },
4431   },
4432
4433   /* PREFIX_0F3A0C */
4434   {
4435     { Bad_Opcode },
4436     { Bad_Opcode },
4437     { "blendps", { XM, EXx, Ib } },
4438   },
4439
4440   /* PREFIX_0F3A0D */
4441   {
4442     { Bad_Opcode },
4443     { Bad_Opcode },
4444     { "blendpd", { XM, EXx, Ib } },
4445   },
4446
4447   /* PREFIX_0F3A0E */
4448   {
4449     { Bad_Opcode },
4450     { Bad_Opcode },
4451     { "pblendw", { XM, EXx, Ib } },
4452   },
4453
4454   /* PREFIX_0F3A14 */
4455   {
4456     { Bad_Opcode },
4457     { Bad_Opcode },
4458     { "pextrb", { Edqb, XM, Ib } },
4459   },
4460
4461   /* PREFIX_0F3A15 */
4462   {
4463     { Bad_Opcode },
4464     { Bad_Opcode },
4465     { "pextrw", { Edqw, XM, Ib } },
4466   },
4467
4468   /* PREFIX_0F3A16 */
4469   {
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { "pextrK", { Edq, XM, Ib } },
4473   },
4474
4475   /* PREFIX_0F3A17 */
4476   {
4477     { Bad_Opcode },
4478     { Bad_Opcode },
4479     { "extractps", { Edqd, XM, Ib } },
4480   },
4481
4482   /* PREFIX_0F3A20 */
4483   {
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { "pinsrb", { XM, Edqb, Ib } },
4487   },
4488
4489   /* PREFIX_0F3A21 */
4490   {
4491     { Bad_Opcode },
4492     { Bad_Opcode },
4493     { "insertps", { XM, EXd, Ib } },
4494   },
4495
4496   /* PREFIX_0F3A22 */
4497   {
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     { "pinsrK", { XM, Edq, Ib } },
4501   },
4502
4503   /* PREFIX_0F3A40 */
4504   {
4505     { Bad_Opcode },
4506     { Bad_Opcode },
4507     { "dpps",   { XM, EXx, Ib } },
4508   },
4509
4510   /* PREFIX_0F3A41 */
4511   {
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { "dppd",   { XM, EXx, Ib } },
4515   },
4516
4517   /* PREFIX_0F3A42 */
4518   {
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { "mpsadbw", { XM, EXx, Ib } },
4522   },
4523
4524   /* PREFIX_0F3A44 */
4525   {
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { "pclmulqdq", { XM, EXx, PCLMUL } },
4529   },
4530
4531   /* PREFIX_0F3A60 */
4532   {
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { "pcmpestrm", { XM, EXx, Ib } },
4536   },
4537
4538   /* PREFIX_0F3A61 */
4539   {
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { "pcmpestri", { XM, EXx, Ib } },
4543   },
4544
4545   /* PREFIX_0F3A62 */
4546   {
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { "pcmpistrm", { XM, EXx, Ib } },
4550   },
4551
4552   /* PREFIX_0F3A63 */
4553   {
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { "pcmpistri", { XM, EXx, Ib } },
4557   },
4558
4559   /* PREFIX_0F3ACC */
4560   {
4561     { "sha1rnds4", { XM, EXxmm, Ib } },
4562   },
4563
4564   /* PREFIX_0F3ADF */
4565   {
4566     { Bad_Opcode },
4567     { Bad_Opcode },
4568     { "aeskeygenassist", { XM, EXx, Ib } },
4569   },
4570
4571   /* PREFIX_VEX_0F10 */
4572   {
4573     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4574     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4575     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4576     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4577   },
4578
4579   /* PREFIX_VEX_0F11 */
4580   {
4581     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4582     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4583     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4584     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4585   },
4586
4587   /* PREFIX_VEX_0F12 */
4588   {
4589     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4590     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4591     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4592     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4593   },
4594
4595   /* PREFIX_VEX_0F16 */
4596   {
4597     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4598     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4599     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4600   },
4601
4602   /* PREFIX_VEX_0F2A */
4603   {
4604     { Bad_Opcode },
4605     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4606     { Bad_Opcode },
4607     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4608   },
4609
4610   /* PREFIX_VEX_0F2C */
4611   {
4612     { Bad_Opcode },
4613     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4614     { Bad_Opcode },
4615     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4616   },
4617
4618   /* PREFIX_VEX_0F2D */
4619   {
4620     { Bad_Opcode },
4621     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4622     { Bad_Opcode },
4623     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4624   },
4625
4626   /* PREFIX_VEX_0F2E */
4627   {
4628     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4629     { Bad_Opcode },
4630     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4631   },
4632
4633   /* PREFIX_VEX_0F2F */
4634   {
4635     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4636     { Bad_Opcode },
4637     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4638   },
4639
4640   /* PREFIX_VEX_0F41 */
4641   {
4642     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4643     { Bad_Opcode },
4644     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4645   },
4646
4647   /* PREFIX_VEX_0F42 */
4648   {
4649     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4650     { Bad_Opcode },
4651     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4652   },
4653
4654   /* PREFIX_VEX_0F44 */
4655   {
4656     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4657     { Bad_Opcode },
4658     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4659   },
4660
4661   /* PREFIX_VEX_0F45 */
4662   {
4663     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4664     { Bad_Opcode },
4665     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4666   },
4667
4668   /* PREFIX_VEX_0F46 */
4669   {
4670     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4671     { Bad_Opcode },
4672     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4673   },
4674
4675   /* PREFIX_VEX_0F47 */
4676   {
4677     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4678     { Bad_Opcode },
4679     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4680   },
4681
4682   /* PREFIX_VEX_0F4A */
4683   {
4684     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4685     { Bad_Opcode },
4686     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4687   },
4688
4689   /* PREFIX_VEX_0F4B */
4690   {
4691     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4692     { Bad_Opcode },
4693     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4694   },
4695
4696   /* PREFIX_VEX_0F51 */
4697   {
4698     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4699     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4700     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4701     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4702   },
4703
4704   /* PREFIX_VEX_0F52 */
4705   {
4706     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4707     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4708   },
4709
4710   /* PREFIX_VEX_0F53 */
4711   {
4712     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4713     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4714   },
4715
4716   /* PREFIX_VEX_0F58 */
4717   {
4718     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4719     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4720     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4721     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4722   },
4723
4724   /* PREFIX_VEX_0F59 */
4725   {
4726     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4727     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4728     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4729     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4730   },
4731
4732   /* PREFIX_VEX_0F5A */
4733   {
4734     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4735     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4736     { "vcvtpd2ps%XY", { XMM, EXx } },
4737     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4738   },
4739
4740   /* PREFIX_VEX_0F5B */
4741   {
4742     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4743     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4744     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4745   },
4746
4747   /* PREFIX_VEX_0F5C */
4748   {
4749     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4750     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4751     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4752     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4753   },
4754
4755   /* PREFIX_VEX_0F5D */
4756   {
4757     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4758     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4759     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4760     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4761   },
4762
4763   /* PREFIX_VEX_0F5E */
4764   {
4765     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4766     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4767     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4768     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4769   },
4770
4771   /* PREFIX_VEX_0F5F */
4772   {
4773     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4774     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4775     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4776     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4777   },
4778
4779   /* PREFIX_VEX_0F60 */
4780   {
4781     { Bad_Opcode },
4782     { Bad_Opcode },
4783     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4784   },
4785
4786   /* PREFIX_VEX_0F61 */
4787   {
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4791   },
4792
4793   /* PREFIX_VEX_0F62 */
4794   {
4795     { Bad_Opcode },
4796     { Bad_Opcode },
4797     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4798   },
4799
4800   /* PREFIX_VEX_0F63 */
4801   {
4802     { Bad_Opcode },
4803     { Bad_Opcode },
4804     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4805   },
4806
4807   /* PREFIX_VEX_0F64 */
4808   {
4809     { Bad_Opcode },
4810     { Bad_Opcode },
4811     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4812   },
4813
4814   /* PREFIX_VEX_0F65 */
4815   {
4816     { Bad_Opcode },
4817     { Bad_Opcode },
4818     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4819   },
4820
4821   /* PREFIX_VEX_0F66 */
4822   {
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4826   },
4827
4828   /* PREFIX_VEX_0F67 */
4829   {
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4833   },
4834
4835   /* PREFIX_VEX_0F68 */
4836   {
4837     { Bad_Opcode },
4838     { Bad_Opcode },
4839     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4840   },
4841
4842   /* PREFIX_VEX_0F69 */
4843   {
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4847   },
4848
4849   /* PREFIX_VEX_0F6A */
4850   {
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4854   },
4855
4856   /* PREFIX_VEX_0F6B */
4857   {
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4861   },
4862
4863   /* PREFIX_VEX_0F6C */
4864   {
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4868   },
4869
4870   /* PREFIX_VEX_0F6D */
4871   {
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4875   },
4876
4877   /* PREFIX_VEX_0F6E */
4878   {
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4882   },
4883
4884   /* PREFIX_VEX_0F6F */
4885   {
4886     { Bad_Opcode },
4887     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4888     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4889   },
4890
4891   /* PREFIX_VEX_0F70 */
4892   {
4893     { Bad_Opcode },
4894     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4895     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4896     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4897   },
4898
4899   /* PREFIX_VEX_0F71_REG_2 */
4900   {
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4904   },
4905
4906   /* PREFIX_VEX_0F71_REG_4 */
4907   {
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4911   },
4912
4913   /* PREFIX_VEX_0F71_REG_6 */
4914   {
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4918   },
4919
4920   /* PREFIX_VEX_0F72_REG_2 */
4921   {
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4925   },
4926
4927   /* PREFIX_VEX_0F72_REG_4 */
4928   {
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4932   },
4933
4934   /* PREFIX_VEX_0F72_REG_6 */
4935   {
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4939   },
4940
4941   /* PREFIX_VEX_0F73_REG_2 */
4942   {
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4946   },
4947
4948   /* PREFIX_VEX_0F73_REG_3 */
4949   {
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4953   },
4954
4955   /* PREFIX_VEX_0F73_REG_6 */
4956   {
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4960   },
4961
4962   /* PREFIX_VEX_0F73_REG_7 */
4963   {
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4967   },
4968
4969   /* PREFIX_VEX_0F74 */
4970   {
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { VEX_W_TABLE (VEX_W_0F74_P_2) },
4974   },
4975
4976   /* PREFIX_VEX_0F75 */
4977   {
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { VEX_W_TABLE (VEX_W_0F75_P_2) },
4981   },
4982
4983   /* PREFIX_VEX_0F76 */
4984   {
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { VEX_W_TABLE (VEX_W_0F76_P_2) },
4988   },
4989
4990   /* PREFIX_VEX_0F77 */
4991   {
4992     { VEX_W_TABLE (VEX_W_0F77_P_0) },
4993   },
4994
4995   /* PREFIX_VEX_0F7C */
4996   {
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5000     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5001   },
5002
5003   /* PREFIX_VEX_0F7D */
5004   {
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5008     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5009   },
5010
5011   /* PREFIX_VEX_0F7E */
5012   {
5013     { Bad_Opcode },
5014     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5015     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5016   },
5017
5018   /* PREFIX_VEX_0F7F */
5019   {
5020     { Bad_Opcode },
5021     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5022     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5023   },
5024
5025   /* PREFIX_VEX_0F90 */
5026   {
5027     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5028     { Bad_Opcode },
5029     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5030   },
5031
5032   /* PREFIX_VEX_0F91 */
5033   {
5034     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5035     { Bad_Opcode },
5036     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5037   },
5038
5039   /* PREFIX_VEX_0F92 */
5040   {
5041     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5042     { Bad_Opcode },
5043     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5044     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5045   },
5046
5047   /* PREFIX_VEX_0F93 */
5048   {
5049     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5050     { Bad_Opcode },
5051     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5052     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5053   },
5054
5055   /* PREFIX_VEX_0F98 */
5056   {
5057     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5058     { Bad_Opcode },
5059     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5060   },
5061
5062   /* PREFIX_VEX_0F99 */
5063   {
5064     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5065     { Bad_Opcode },
5066     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5067   },
5068
5069   /* PREFIX_VEX_0FC2 */
5070   {
5071     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5072     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5073     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5074     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5075   },
5076
5077   /* PREFIX_VEX_0FC4 */
5078   {
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5082   },
5083
5084   /* PREFIX_VEX_0FC5 */
5085   {
5086     { Bad_Opcode },
5087     { Bad_Opcode },
5088     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5089   },
5090
5091   /* PREFIX_VEX_0FD0 */
5092   {
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5096     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5097   },
5098
5099   /* PREFIX_VEX_0FD1 */
5100   {
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5104   },
5105
5106   /* PREFIX_VEX_0FD2 */
5107   {
5108     { Bad_Opcode },
5109     { Bad_Opcode },
5110     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5111   },
5112
5113   /* PREFIX_VEX_0FD3 */
5114   {
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5118   },
5119
5120   /* PREFIX_VEX_0FD4 */
5121   {
5122     { Bad_Opcode },
5123     { Bad_Opcode },
5124     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5125   },
5126
5127   /* PREFIX_VEX_0FD5 */
5128   {
5129     { Bad_Opcode },
5130     { Bad_Opcode },
5131     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5132   },
5133
5134   /* PREFIX_VEX_0FD6 */
5135   {
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5139   },
5140
5141   /* PREFIX_VEX_0FD7 */
5142   {
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5146   },
5147
5148   /* PREFIX_VEX_0FD8 */
5149   {
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5153   },
5154
5155   /* PREFIX_VEX_0FD9 */
5156   {
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5160   },
5161
5162   /* PREFIX_VEX_0FDA */
5163   {
5164     { Bad_Opcode },
5165     { Bad_Opcode },
5166     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5167   },
5168
5169   /* PREFIX_VEX_0FDB */
5170   {
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5174   },
5175
5176   /* PREFIX_VEX_0FDC */
5177   {
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5181   },
5182
5183   /* PREFIX_VEX_0FDD */
5184   {
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5188   },
5189
5190   /* PREFIX_VEX_0FDE */
5191   {
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5195   },
5196
5197   /* PREFIX_VEX_0FDF */
5198   {
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5202   },
5203
5204   /* PREFIX_VEX_0FE0 */
5205   {
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5209   },
5210
5211   /* PREFIX_VEX_0FE1 */
5212   {
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5216   },
5217
5218   /* PREFIX_VEX_0FE2 */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5223   },
5224
5225   /* PREFIX_VEX_0FE3 */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5230   },
5231
5232   /* PREFIX_VEX_0FE4 */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5237   },
5238
5239   /* PREFIX_VEX_0FE5 */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5244   },
5245
5246   /* PREFIX_VEX_0FE6 */
5247   {
5248     { Bad_Opcode },
5249     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5250     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5251     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5252   },
5253
5254   /* PREFIX_VEX_0FE7 */
5255   {
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5259   },
5260
5261   /* PREFIX_VEX_0FE8 */
5262   {
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5266   },
5267
5268   /* PREFIX_VEX_0FE9 */
5269   {
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5273   },
5274
5275   /* PREFIX_VEX_0FEA */
5276   {
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5280   },
5281
5282   /* PREFIX_VEX_0FEB */
5283   {
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5287   },
5288
5289   /* PREFIX_VEX_0FEC */
5290   {
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5294   },
5295
5296   /* PREFIX_VEX_0FED */
5297   {
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5301   },
5302
5303   /* PREFIX_VEX_0FEE */
5304   {
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5308   },
5309
5310   /* PREFIX_VEX_0FEF */
5311   {
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5315   },
5316
5317   /* PREFIX_VEX_0FF0 */
5318   {
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5323   },
5324
5325   /* PREFIX_VEX_0FF1 */
5326   {
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5330   },
5331
5332   /* PREFIX_VEX_0FF2 */
5333   {
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5337   },
5338
5339   /* PREFIX_VEX_0FF3 */
5340   {
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5344   },
5345
5346   /* PREFIX_VEX_0FF4 */
5347   {
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5351   },
5352
5353   /* PREFIX_VEX_0FF5 */
5354   {
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5358   },
5359
5360   /* PREFIX_VEX_0FF6 */
5361   {
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5365   },
5366
5367   /* PREFIX_VEX_0FF7 */
5368   {
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5372   },
5373
5374   /* PREFIX_VEX_0FF8 */
5375   {
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5379   },
5380
5381   /* PREFIX_VEX_0FF9 */
5382   {
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5386   },
5387
5388   /* PREFIX_VEX_0FFA */
5389   {
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5393   },
5394
5395   /* PREFIX_VEX_0FFB */
5396   {
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5400   },
5401
5402   /* PREFIX_VEX_0FFC */
5403   {
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5407   },
5408
5409   /* PREFIX_VEX_0FFD */
5410   {
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5414   },
5415
5416   /* PREFIX_VEX_0FFE */
5417   {
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5421   },
5422
5423   /* PREFIX_VEX_0F3800 */
5424   {
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5428   },
5429
5430   /* PREFIX_VEX_0F3801 */
5431   {
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5435   },
5436
5437   /* PREFIX_VEX_0F3802 */
5438   {
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5442   },
5443
5444   /* PREFIX_VEX_0F3803 */
5445   {
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5449   },
5450
5451   /* PREFIX_VEX_0F3804 */
5452   {
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5456   },
5457
5458   /* PREFIX_VEX_0F3805 */
5459   {
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5463   },
5464
5465   /* PREFIX_VEX_0F3806 */
5466   {
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5470   },
5471
5472   /* PREFIX_VEX_0F3807 */
5473   {
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5477   },
5478
5479   /* PREFIX_VEX_0F3808 */
5480   {
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5484   },
5485
5486   /* PREFIX_VEX_0F3809 */
5487   {
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5491   },
5492
5493   /* PREFIX_VEX_0F380A */
5494   {
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5498   },
5499
5500   /* PREFIX_VEX_0F380B */
5501   {
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5505   },
5506
5507   /* PREFIX_VEX_0F380C */
5508   {
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5512   },
5513
5514   /* PREFIX_VEX_0F380D */
5515   {
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5519   },
5520
5521   /* PREFIX_VEX_0F380E */
5522   {
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5526   },
5527
5528   /* PREFIX_VEX_0F380F */
5529   {
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5533   },
5534
5535   /* PREFIX_VEX_0F3813 */
5536   {
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { "vcvtph2ps", { XM, EXxmmq } },
5540   },
5541
5542   /* PREFIX_VEX_0F3816 */
5543   {
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5547   },
5548
5549   /* PREFIX_VEX_0F3817 */
5550   {
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5554   },
5555
5556   /* PREFIX_VEX_0F3818 */
5557   {
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5561   },
5562
5563   /* PREFIX_VEX_0F3819 */
5564   {
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5568   },
5569
5570   /* PREFIX_VEX_0F381A */
5571   {
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5575   },
5576
5577   /* PREFIX_VEX_0F381C */
5578   {
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5582   },
5583
5584   /* PREFIX_VEX_0F381D */
5585   {
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5589   },
5590
5591   /* PREFIX_VEX_0F381E */
5592   {
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5596   },
5597
5598   /* PREFIX_VEX_0F3820 */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5603   },
5604
5605   /* PREFIX_VEX_0F3821 */
5606   {
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5610   },
5611
5612   /* PREFIX_VEX_0F3822 */
5613   {
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5617   },
5618
5619   /* PREFIX_VEX_0F3823 */
5620   {
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5624   },
5625
5626   /* PREFIX_VEX_0F3824 */
5627   {
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5631   },
5632
5633   /* PREFIX_VEX_0F3825 */
5634   {
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5638   },
5639
5640   /* PREFIX_VEX_0F3828 */
5641   {
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5645   },
5646
5647   /* PREFIX_VEX_0F3829 */
5648   {
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5652   },
5653
5654   /* PREFIX_VEX_0F382A */
5655   {
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5659   },
5660
5661   /* PREFIX_VEX_0F382B */
5662   {
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5666   },
5667
5668   /* PREFIX_VEX_0F382C */
5669   {
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5673   },
5674
5675   /* PREFIX_VEX_0F382D */
5676   {
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5680   },
5681
5682   /* PREFIX_VEX_0F382E */
5683   {
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5687   },
5688
5689   /* PREFIX_VEX_0F382F */
5690   {
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5694   },
5695
5696   /* PREFIX_VEX_0F3830 */
5697   {
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5701   },
5702
5703   /* PREFIX_VEX_0F3831 */
5704   {
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5708   },
5709
5710   /* PREFIX_VEX_0F3832 */
5711   {
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5715   },
5716
5717   /* PREFIX_VEX_0F3833 */
5718   {
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5722   },
5723
5724   /* PREFIX_VEX_0F3834 */
5725   {
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5729   },
5730
5731   /* PREFIX_VEX_0F3835 */
5732   {
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5736   },
5737
5738   /* PREFIX_VEX_0F3836 */
5739   {
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5743   },
5744
5745   /* PREFIX_VEX_0F3837 */
5746   {
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5750   },
5751
5752   /* PREFIX_VEX_0F3838 */
5753   {
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5757   },
5758
5759   /* PREFIX_VEX_0F3839 */
5760   {
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5764   },
5765
5766   /* PREFIX_VEX_0F383A */
5767   {
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5771   },
5772
5773   /* PREFIX_VEX_0F383B */
5774   {
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5778   },
5779
5780   /* PREFIX_VEX_0F383C */
5781   {
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5785   },
5786
5787   /* PREFIX_VEX_0F383D */
5788   {
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5792   },
5793
5794   /* PREFIX_VEX_0F383E */
5795   {
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5799   },
5800
5801   /* PREFIX_VEX_0F383F */
5802   {
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5806   },
5807
5808   /* PREFIX_VEX_0F3840 */
5809   {
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5813   },
5814
5815   /* PREFIX_VEX_0F3841 */
5816   {
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5820   },
5821
5822   /* PREFIX_VEX_0F3845 */
5823   {
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { "vpsrlv%LW", { XM, Vex, EXx } },
5827   },
5828
5829   /* PREFIX_VEX_0F3846 */
5830   {
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5834   },
5835
5836   /* PREFIX_VEX_0F3847 */
5837   {
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { "vpsllv%LW", { XM, Vex, EXx } },
5841   },
5842
5843   /* PREFIX_VEX_0F3858 */
5844   {
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5848   },
5849
5850   /* PREFIX_VEX_0F3859 */
5851   {
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5855   },
5856
5857   /* PREFIX_VEX_0F385A */
5858   {
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5862   },
5863
5864   /* PREFIX_VEX_0F3878 */
5865   {
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5869   },
5870
5871   /* PREFIX_VEX_0F3879 */
5872   {
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5876   },
5877
5878   /* PREFIX_VEX_0F388C */
5879   {
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5883   },
5884
5885   /* PREFIX_VEX_0F388E */
5886   {
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5890   },
5891
5892   /* PREFIX_VEX_0F3890 */
5893   {
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5897   },
5898
5899   /* PREFIX_VEX_0F3891 */
5900   {
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5904   },
5905
5906   /* PREFIX_VEX_0F3892 */
5907   {
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5911   },
5912
5913   /* PREFIX_VEX_0F3893 */
5914   {
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5918   },
5919
5920   /* PREFIX_VEX_0F3896 */
5921   {
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5925   },
5926
5927   /* PREFIX_VEX_0F3897 */
5928   {
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5932   },
5933
5934   /* PREFIX_VEX_0F3898 */
5935   {
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { "vfmadd132p%XW", { XM, Vex, EXx } },
5939   },
5940
5941   /* PREFIX_VEX_0F3899 */
5942   {
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5946   },
5947
5948   /* PREFIX_VEX_0F389A */
5949   {
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { "vfmsub132p%XW", { XM, Vex, EXx } },
5953   },
5954
5955   /* PREFIX_VEX_0F389B */
5956   {
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5960   },
5961
5962   /* PREFIX_VEX_0F389C */
5963   {
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { "vfnmadd132p%XW", { XM, Vex, EXx } },
5967   },
5968
5969   /* PREFIX_VEX_0F389D */
5970   {
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5974   },
5975
5976   /* PREFIX_VEX_0F389E */
5977   {
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { "vfnmsub132p%XW", { XM, Vex, EXx } },
5981   },
5982
5983   /* PREFIX_VEX_0F389F */
5984   {
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5988   },
5989
5990   /* PREFIX_VEX_0F38A6 */
5991   {
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
5995     { Bad_Opcode },
5996   },
5997
5998   /* PREFIX_VEX_0F38A7 */
5999   {
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
6003   },
6004
6005   /* PREFIX_VEX_0F38A8 */
6006   {
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { "vfmadd213p%XW", { XM, Vex, EXx } },
6010   },
6011
6012   /* PREFIX_VEX_0F38A9 */
6013   {
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6017   },
6018
6019   /* PREFIX_VEX_0F38AA */
6020   {
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { "vfmsub213p%XW", { XM, Vex, EXx } },
6024   },
6025
6026   /* PREFIX_VEX_0F38AB */
6027   {
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6031   },
6032
6033   /* PREFIX_VEX_0F38AC */
6034   {
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { "vfnmadd213p%XW", { XM, Vex, EXx } },
6038   },
6039
6040   /* PREFIX_VEX_0F38AD */
6041   {
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6045   },
6046
6047   /* PREFIX_VEX_0F38AE */
6048   {
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { "vfnmsub213p%XW", { XM, Vex, EXx } },
6052   },
6053
6054   /* PREFIX_VEX_0F38AF */
6055   {
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6059   },
6060
6061   /* PREFIX_VEX_0F38B6 */
6062   {
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
6066   },
6067
6068   /* PREFIX_VEX_0F38B7 */
6069   {
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
6073   },
6074
6075   /* PREFIX_VEX_0F38B8 */
6076   {
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { "vfmadd231p%XW", { XM, Vex, EXx } },
6080   },
6081
6082   /* PREFIX_VEX_0F38B9 */
6083   {
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6087   },
6088
6089   /* PREFIX_VEX_0F38BA */
6090   {
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { "vfmsub231p%XW", { XM, Vex, EXx } },
6094   },
6095
6096   /* PREFIX_VEX_0F38BB */
6097   {
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6101   },
6102
6103   /* PREFIX_VEX_0F38BC */
6104   {
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { "vfnmadd231p%XW", { XM, Vex, EXx } },
6108   },
6109
6110   /* PREFIX_VEX_0F38BD */
6111   {
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6115   },
6116
6117   /* PREFIX_VEX_0F38BE */
6118   {
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { "vfnmsub231p%XW", { XM, Vex, EXx } },
6122   },
6123
6124   /* PREFIX_VEX_0F38BF */
6125   {
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6129   },
6130
6131   /* PREFIX_VEX_0F38DB */
6132   {
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6136   },
6137
6138   /* PREFIX_VEX_0F38DC */
6139   {
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6143   },
6144
6145   /* PREFIX_VEX_0F38DD */
6146   {
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6150   },
6151
6152   /* PREFIX_VEX_0F38DE */
6153   {
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6157   },
6158
6159   /* PREFIX_VEX_0F38DF */
6160   {
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6164   },
6165
6166   /* PREFIX_VEX_0F38F2 */
6167   {
6168     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6169   },
6170
6171   /* PREFIX_VEX_0F38F3_REG_1 */
6172   {
6173     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6174   },
6175
6176   /* PREFIX_VEX_0F38F3_REG_2 */
6177   {
6178     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6179   },
6180
6181   /* PREFIX_VEX_0F38F3_REG_3 */
6182   {
6183     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6184   },
6185
6186   /* PREFIX_VEX_0F38F5 */
6187   {
6188     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6189     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6190     { Bad_Opcode },
6191     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6192   },
6193
6194   /* PREFIX_VEX_0F38F6 */
6195   {
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6200   },
6201
6202   /* PREFIX_VEX_0F38F7 */
6203   {
6204     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6205     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6206     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6207     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6208   },
6209
6210   /* PREFIX_VEX_0F3A00 */
6211   {
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6215   },
6216
6217   /* PREFIX_VEX_0F3A01 */
6218   {
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6222   },
6223
6224   /* PREFIX_VEX_0F3A02 */
6225   {
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6229   },
6230
6231   /* PREFIX_VEX_0F3A04 */
6232   {
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6236   },
6237
6238   /* PREFIX_VEX_0F3A05 */
6239   {
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6243   },
6244
6245   /* PREFIX_VEX_0F3A06 */
6246   {
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6250   },
6251
6252   /* PREFIX_VEX_0F3A08 */
6253   {
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6257   },
6258
6259   /* PREFIX_VEX_0F3A09 */
6260   {
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6264   },
6265
6266   /* PREFIX_VEX_0F3A0A */
6267   {
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6271   },
6272
6273   /* PREFIX_VEX_0F3A0B */
6274   {
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6278   },
6279
6280   /* PREFIX_VEX_0F3A0C */
6281   {
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6285   },
6286
6287   /* PREFIX_VEX_0F3A0D */
6288   {
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6292   },
6293
6294   /* PREFIX_VEX_0F3A0E */
6295   {
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6299   },
6300
6301   /* PREFIX_VEX_0F3A0F */
6302   {
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6306   },
6307
6308   /* PREFIX_VEX_0F3A14 */
6309   {
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6313   },
6314
6315   /* PREFIX_VEX_0F3A15 */
6316   {
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6320   },
6321
6322   /* PREFIX_VEX_0F3A16 */
6323   {
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6327   },
6328
6329   /* PREFIX_VEX_0F3A17 */
6330   {
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6334   },
6335
6336   /* PREFIX_VEX_0F3A18 */
6337   {
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6341   },
6342
6343   /* PREFIX_VEX_0F3A19 */
6344   {
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6348   },
6349
6350   /* PREFIX_VEX_0F3A1D */
6351   {
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { "vcvtps2ph", { EXxmmq, XM, Ib } },
6355   },
6356
6357   /* PREFIX_VEX_0F3A20 */
6358   {
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6362   },
6363
6364   /* PREFIX_VEX_0F3A21 */
6365   {
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6369   },
6370
6371   /* PREFIX_VEX_0F3A22 */
6372   {
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6376   },
6377
6378   /* PREFIX_VEX_0F3A30 */
6379   {
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6383   },
6384
6385   /* PREFIX_VEX_0F3A31 */
6386   {
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6390   },
6391
6392   /* PREFIX_VEX_0F3A32 */
6393   {
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6397   },
6398
6399   /* PREFIX_VEX_0F3A33 */
6400   {
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6404   },
6405
6406   /* PREFIX_VEX_0F3A38 */
6407   {
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6411   },
6412
6413   /* PREFIX_VEX_0F3A39 */
6414   {
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6418   },
6419
6420   /* PREFIX_VEX_0F3A40 */
6421   {
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6425   },
6426
6427   /* PREFIX_VEX_0F3A41 */
6428   {
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6432   },
6433
6434   /* PREFIX_VEX_0F3A42 */
6435   {
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6439   },
6440
6441   /* PREFIX_VEX_0F3A44 */
6442   {
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6446   },
6447
6448   /* PREFIX_VEX_0F3A46 */
6449   {
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6453   },
6454
6455   /* PREFIX_VEX_0F3A48 */
6456   {
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6460   },
6461
6462   /* PREFIX_VEX_0F3A49 */
6463   {
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6467   },
6468
6469   /* PREFIX_VEX_0F3A4A */
6470   {
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6474   },
6475
6476   /* PREFIX_VEX_0F3A4B */
6477   {
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6481   },
6482
6483   /* PREFIX_VEX_0F3A4C */
6484   {
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6488   },
6489
6490   /* PREFIX_VEX_0F3A5C */
6491   {
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6495   },
6496
6497   /* PREFIX_VEX_0F3A5D */
6498   {
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6502   },
6503
6504   /* PREFIX_VEX_0F3A5E */
6505   {
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6509   },
6510
6511   /* PREFIX_VEX_0F3A5F */
6512   {
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6516   },
6517
6518   /* PREFIX_VEX_0F3A60 */
6519   {
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6523     { Bad_Opcode },
6524   },
6525
6526   /* PREFIX_VEX_0F3A61 */
6527   {
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6531   },
6532
6533   /* PREFIX_VEX_0F3A62 */
6534   {
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6538   },
6539
6540   /* PREFIX_VEX_0F3A63 */
6541   {
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6545   },
6546
6547   /* PREFIX_VEX_0F3A68 */
6548   {
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6552   },
6553
6554   /* PREFIX_VEX_0F3A69 */
6555   {
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6559   },
6560
6561   /* PREFIX_VEX_0F3A6A */
6562   {
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6566   },
6567
6568   /* PREFIX_VEX_0F3A6B */
6569   {
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6573   },
6574
6575   /* PREFIX_VEX_0F3A6C */
6576   {
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6580   },
6581
6582   /* PREFIX_VEX_0F3A6D */
6583   {
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6587   },
6588
6589   /* PREFIX_VEX_0F3A6E */
6590   {
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6594   },
6595
6596   /* PREFIX_VEX_0F3A6F */
6597   {
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6601   },
6602
6603   /* PREFIX_VEX_0F3A78 */
6604   {
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6608   },
6609
6610   /* PREFIX_VEX_0F3A79 */
6611   {
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6615   },
6616
6617   /* PREFIX_VEX_0F3A7A */
6618   {
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6622   },
6623
6624   /* PREFIX_VEX_0F3A7B */
6625   {
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6629   },
6630
6631   /* PREFIX_VEX_0F3A7C */
6632   {
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6636     { Bad_Opcode },
6637   },
6638
6639   /* PREFIX_VEX_0F3A7D */
6640   {
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6644   },
6645
6646   /* PREFIX_VEX_0F3A7E */
6647   {
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6651   },
6652
6653   /* PREFIX_VEX_0F3A7F */
6654   {
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6658   },
6659
6660   /* PREFIX_VEX_0F3ADF */
6661   {
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6665   },
6666
6667   /* PREFIX_VEX_0F3AF0 */
6668   {
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6673   },
6674
6675 #define NEED_PREFIX_TABLE
6676 #include "i386-dis-evex.h"
6677 #undef NEED_PREFIX_TABLE
6678 };
6679
6680 static const struct dis386 x86_64_table[][2] = {
6681   /* X86_64_06 */
6682   {
6683     { "pushP", { es } },
6684   },
6685
6686   /* X86_64_07 */
6687   {
6688     { "popP", { es } },
6689   },
6690
6691   /* X86_64_0D */
6692   {
6693     { "pushP", { cs } },
6694   },
6695
6696   /* X86_64_16 */
6697   {
6698     { "pushP", { ss } },
6699   },
6700
6701   /* X86_64_17 */
6702   {
6703     { "popP", { ss } },
6704   },
6705
6706   /* X86_64_1E */
6707   {
6708     { "pushP", { ds } },
6709   },
6710
6711   /* X86_64_1F */
6712   {
6713     { "popP", { ds } },
6714   },
6715
6716   /* X86_64_27 */
6717   {
6718     { "daa", { XX } },
6719   },
6720
6721   /* X86_64_2F */
6722   {
6723     { "das", { XX } },
6724   },
6725
6726   /* X86_64_37 */
6727   {
6728     { "aaa", { XX } },
6729   },
6730
6731   /* X86_64_3F */
6732   {
6733     { "aas", { XX } },
6734   },
6735
6736   /* X86_64_60 */
6737   {
6738     { "pushaP", { XX } },
6739   },
6740
6741   /* X86_64_61 */
6742   {
6743     { "popaP", { XX } },
6744   },
6745
6746   /* X86_64_62 */
6747   {
6748     { MOD_TABLE (MOD_62_32BIT) },
6749     { EVEX_TABLE (EVEX_0F) },
6750   },
6751
6752   /* X86_64_63 */
6753   {
6754     { "arpl", { Ew, Gw } },
6755     { "movs{lq|xd}", { Gv, Ed } },
6756   },
6757
6758   /* X86_64_6D */
6759   {
6760     { "ins{R|}", { Yzr, indirDX } },
6761     { "ins{G|}", { Yzr, indirDX } },
6762   },
6763
6764   /* X86_64_6F */
6765   {
6766     { "outs{R|}", { indirDXr, Xz } },
6767     { "outs{G|}", { indirDXr, Xz } },
6768   },
6769
6770   /* X86_64_9A */
6771   {
6772     { "Jcall{T|}", { Ap } },
6773   },
6774
6775   /* X86_64_C4 */
6776   {
6777     { MOD_TABLE (MOD_C4_32BIT) },
6778     { VEX_C4_TABLE (VEX_0F) },
6779   },
6780
6781   /* X86_64_C5 */
6782   {
6783     { MOD_TABLE (MOD_C5_32BIT) },
6784     { VEX_C5_TABLE (VEX_0F) },
6785   },
6786
6787   /* X86_64_CE */
6788   {
6789     { "into", { XX } },
6790   },
6791
6792   /* X86_64_D4 */
6793   {
6794     { "aam", { Ib } },
6795   },
6796
6797   /* X86_64_D5 */
6798   {
6799     { "aad", { Ib } },
6800   },
6801
6802   /* X86_64_EA */
6803   {
6804     { "Jjmp{T|}", { Ap } },
6805   },
6806
6807   /* X86_64_0F01_REG_0 */
6808   {
6809     { "sgdt{Q|IQ}", { M } },
6810     { "sgdt", { M } },
6811   },
6812
6813   /* X86_64_0F01_REG_1 */
6814   {
6815     { "sidt{Q|IQ}", { M } },
6816     { "sidt", { M } },
6817   },
6818
6819   /* X86_64_0F01_REG_2 */
6820   {
6821     { "lgdt{Q|Q}", { M } },
6822     { "lgdt", { M } },
6823   },
6824
6825   /* X86_64_0F01_REG_3 */
6826   {
6827     { "lidt{Q|Q}", { M } },
6828     { "lidt", { M } },
6829   },
6830 };
6831
6832 static const struct dis386 three_byte_table[][256] = {
6833
6834   /* THREE_BYTE_0F38 */
6835   {
6836     /* 00 */
6837     { "pshufb",         { MX, EM } },
6838     { "phaddw",         { MX, EM } },
6839     { "phaddd",         { MX, EM } },
6840     { "phaddsw",        { MX, EM } },
6841     { "pmaddubsw",      { MX, EM } },
6842     { "phsubw",         { MX, EM } },
6843     { "phsubd",         { MX, EM } },
6844     { "phsubsw",        { MX, EM } },
6845     /* 08 */
6846     { "psignb",         { MX, EM } },
6847     { "psignw",         { MX, EM } },
6848     { "psignd",         { MX, EM } },
6849     { "pmulhrsw",       { MX, EM } },
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     /* 10 */
6855     { PREFIX_TABLE (PREFIX_0F3810) },
6856     { Bad_Opcode },
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { PREFIX_TABLE (PREFIX_0F3814) },
6860     { PREFIX_TABLE (PREFIX_0F3815) },
6861     { Bad_Opcode },
6862     { PREFIX_TABLE (PREFIX_0F3817) },
6863     /* 18 */
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     { "pabsb",          { MX, EM } },
6869     { "pabsw",          { MX, EM } },
6870     { "pabsd",          { MX, EM } },
6871     { Bad_Opcode },
6872     /* 20 */
6873     { PREFIX_TABLE (PREFIX_0F3820) },
6874     { PREFIX_TABLE (PREFIX_0F3821) },
6875     { PREFIX_TABLE (PREFIX_0F3822) },
6876     { PREFIX_TABLE (PREFIX_0F3823) },
6877     { PREFIX_TABLE (PREFIX_0F3824) },
6878     { PREFIX_TABLE (PREFIX_0F3825) },
6879     { Bad_Opcode },
6880     { Bad_Opcode },
6881     /* 28 */
6882     { PREFIX_TABLE (PREFIX_0F3828) },
6883     { PREFIX_TABLE (PREFIX_0F3829) },
6884     { PREFIX_TABLE (PREFIX_0F382A) },
6885     { PREFIX_TABLE (PREFIX_0F382B) },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     /* 30 */
6891     { PREFIX_TABLE (PREFIX_0F3830) },
6892     { PREFIX_TABLE (PREFIX_0F3831) },
6893     { PREFIX_TABLE (PREFIX_0F3832) },
6894     { PREFIX_TABLE (PREFIX_0F3833) },
6895     { PREFIX_TABLE (PREFIX_0F3834) },
6896     { PREFIX_TABLE (PREFIX_0F3835) },
6897     { Bad_Opcode },
6898     { PREFIX_TABLE (PREFIX_0F3837) },
6899     /* 38 */
6900     { PREFIX_TABLE (PREFIX_0F3838) },
6901     { PREFIX_TABLE (PREFIX_0F3839) },
6902     { PREFIX_TABLE (PREFIX_0F383A) },
6903     { PREFIX_TABLE (PREFIX_0F383B) },
6904     { PREFIX_TABLE (PREFIX_0F383C) },
6905     { PREFIX_TABLE (PREFIX_0F383D) },
6906     { PREFIX_TABLE (PREFIX_0F383E) },
6907     { PREFIX_TABLE (PREFIX_0F383F) },
6908     /* 40 */
6909     { PREFIX_TABLE (PREFIX_0F3840) },
6910     { PREFIX_TABLE (PREFIX_0F3841) },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     /* 48 */
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     /* 50 */
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     /* 58 */
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     /* 60 */
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     /* 68 */
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     /* 70 */
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     /* 78 */
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     /* 80 */
6981     { PREFIX_TABLE (PREFIX_0F3880) },
6982     { PREFIX_TABLE (PREFIX_0F3881) },
6983     { PREFIX_TABLE (PREFIX_0F3882) },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     /* 88 */
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     /* 90 */
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     /* 98 */
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     /* a0 */
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     /* a8 */
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     /* b0 */
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     /* b8 */
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     /* c0 */
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     /* c8 */
7062     { PREFIX_TABLE (PREFIX_0F38C8) },
7063     { PREFIX_TABLE (PREFIX_0F38C9) },
7064     { PREFIX_TABLE (PREFIX_0F38CA) },
7065     { PREFIX_TABLE (PREFIX_0F38CB) },
7066     { PREFIX_TABLE (PREFIX_0F38CC) },
7067     { PREFIX_TABLE (PREFIX_0F38CD) },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     /* d0 */
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     /* d8 */
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { PREFIX_TABLE (PREFIX_0F38DB) },
7084     { PREFIX_TABLE (PREFIX_0F38DC) },
7085     { PREFIX_TABLE (PREFIX_0F38DD) },
7086     { PREFIX_TABLE (PREFIX_0F38DE) },
7087     { PREFIX_TABLE (PREFIX_0F38DF) },
7088     /* e0 */
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     /* e8 */
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     /* f0 */
7107     { PREFIX_TABLE (PREFIX_0F38F0) },
7108     { PREFIX_TABLE (PREFIX_0F38F1) },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { PREFIX_TABLE (PREFIX_0F38F6) },
7114     { Bad_Opcode },
7115     /* f8 */
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124   },
7125   /* THREE_BYTE_0F3A */
7126   {
7127     /* 00 */
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     /* 08 */
7137     { PREFIX_TABLE (PREFIX_0F3A08) },
7138     { PREFIX_TABLE (PREFIX_0F3A09) },
7139     { PREFIX_TABLE (PREFIX_0F3A0A) },
7140     { PREFIX_TABLE (PREFIX_0F3A0B) },
7141     { PREFIX_TABLE (PREFIX_0F3A0C) },
7142     { PREFIX_TABLE (PREFIX_0F3A0D) },
7143     { PREFIX_TABLE (PREFIX_0F3A0E) },
7144     { "palignr",        { MX, EM, Ib } },
7145     /* 10 */
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { PREFIX_TABLE (PREFIX_0F3A14) },
7151     { PREFIX_TABLE (PREFIX_0F3A15) },
7152     { PREFIX_TABLE (PREFIX_0F3A16) },
7153     { PREFIX_TABLE (PREFIX_0F3A17) },
7154     /* 18 */
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     /* 20 */
7164     { PREFIX_TABLE (PREFIX_0F3A20) },
7165     { PREFIX_TABLE (PREFIX_0F3A21) },
7166     { PREFIX_TABLE (PREFIX_0F3A22) },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     /* 28 */
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     /* 30 */
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     /* 38 */
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     /* 40 */
7200     { PREFIX_TABLE (PREFIX_0F3A40) },
7201     { PREFIX_TABLE (PREFIX_0F3A41) },
7202     { PREFIX_TABLE (PREFIX_0F3A42) },
7203     { Bad_Opcode },
7204     { PREFIX_TABLE (PREFIX_0F3A44) },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     /* 48 */
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     /* 50 */
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     /* 58 */
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     /* 60 */
7236     { PREFIX_TABLE (PREFIX_0F3A60) },
7237     { PREFIX_TABLE (PREFIX_0F3A61) },
7238     { PREFIX_TABLE (PREFIX_0F3A62) },
7239     { PREFIX_TABLE (PREFIX_0F3A63) },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     /* 68 */
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     /* 70 */
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     /* 78 */
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     /* 80 */
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     /* 88 */
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     /* 90 */
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     /* 98 */
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     /* a0 */
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     /* a8 */
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     /* b0 */
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     /* b8 */
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     /* c0 */
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     /* c8 */
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { PREFIX_TABLE (PREFIX_0F3ACC) },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     /* d0 */
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     /* d8 */
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { PREFIX_TABLE (PREFIX_0F3ADF) },
7379     /* e0 */
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     /* e8 */
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     /* f0 */
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     /* f8 */
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415   },
7416
7417   /* THREE_BYTE_0F7A */
7418   {
7419     /* 00 */
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     /* 08 */
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     /* 10 */
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     /* 18 */
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     /* 20 */
7456     { "ptest",          { XX } },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     /* 28 */
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     /* 30 */
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     /* 38 */
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     /* 40 */
7492     { Bad_Opcode },
7493     { "phaddbw",        { XM, EXq } },
7494     { "phaddbd",        { XM, EXq } },
7495     { "phaddbq",        { XM, EXq } },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { "phaddwd",        { XM, EXq } },
7499     { "phaddwq",        { XM, EXq } },
7500     /* 48 */
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { "phadddq",        { XM, EXq } },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     /* 50 */
7510     { Bad_Opcode },
7511     { "phaddubw",       { XM, EXq } },
7512     { "phaddubd",       { XM, EXq } },
7513     { "phaddubq",       { XM, EXq } },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { "phadduwd",       { XM, EXq } },
7517     { "phadduwq",       { XM, EXq } },
7518     /* 58 */
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { "phaddudq",       { XM, EXq } },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     /* 60 */
7528     { Bad_Opcode },
7529     { "phsubbw",        { XM, EXq } },
7530     { "phsubbd",        { XM, EXq } },
7531     { "phsubbq",        { XM, EXq } },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     /* 68 */
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     /* 70 */
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     /* 78 */
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     /* 80 */
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     /* 88 */
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     /* 90 */
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     /* 98 */
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     /* a0 */
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     /* a8 */
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     /* b0 */
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     /* b8 */
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     /* c0 */
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     /* c8 */
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     /* d0 */
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     /* d8 */
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     /* e0 */
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     /* e8 */
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     /* f0 */
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     /* f8 */
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707   },
7708 };
7709
7710 static const struct dis386 xop_table[][256] = {
7711   /* XOP_08 */
7712   {
7713     /* 00 */
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     /* 08 */
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     /* 10 */
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     /* 18 */
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     /* 20 */
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     /* 28 */
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     /* 30 */
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     /* 38 */
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     /* 40 */
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     /* 48 */
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     /* 50 */
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     /* 58 */
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     /* 60 */
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     /* 68 */
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     /* 70 */
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     /* 78 */
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     /* 80 */
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7864     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7865     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7866     /* 88 */
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7874     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7875     /* 90 */
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7882     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7883     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7884     /* 98 */
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7892     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7893     /* a0 */
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7897     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7901     { Bad_Opcode },
7902     /* a8 */
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     /* b0 */
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7919     { Bad_Opcode },
7920     /* b8 */
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     /* c0 */
7930     { "vprotb",         { XM, Vex_2src_1, Ib } },
7931     { "vprotw",         { XM, Vex_2src_1, Ib } },
7932     { "vprotd",         { XM, Vex_2src_1, Ib } },
7933     { "vprotq",         { XM, Vex_2src_1, Ib } },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     /* c8 */
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7944     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7945     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7946     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7947     /* d0 */
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     /* d8 */
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     /* e0 */
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     /* e8 */
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7980     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7981     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7982     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7983     /* f0 */
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     /* f8 */
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001   },
8002   /* XOP_09 */
8003   {
8004     /* 00 */
8005     { Bad_Opcode },
8006     { REG_TABLE (REG_XOP_TBM_01) },
8007     { REG_TABLE (REG_XOP_TBM_02) },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     /* 08 */
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     /* 10 */
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { REG_TABLE (REG_XOP_LWPCB) },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     /* 18 */
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     /* 20 */
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     /* 28 */
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     /* 30 */
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     /* 38 */
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     /* 40 */
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     /* 48 */
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     /* 50 */
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     /* 58 */
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     /* 60 */
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     /* 68 */
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     /* 70 */
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     /* 78 */
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     /* 80 */
8149     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8150     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8151     { "vfrczss",        { XM, EXd } },
8152     { "vfrczsd",        { XM, EXq } },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     /* 88 */
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     /* 90 */
8167     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
8168     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
8169     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
8170     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
8171     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
8172     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
8173     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
8174     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
8175     /* 98 */
8176     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
8177     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
8178     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
8179     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     /* a0 */
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     /* a8 */
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     /* b0 */
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     /* b8 */
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     /* c0 */
8221     { Bad_Opcode },
8222     { "vphaddbw",       { XM, EXxmm } },
8223     { "vphaddbd",       { XM, EXxmm } },
8224     { "vphaddbq",       { XM, EXxmm } },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { "vphaddwd",       { XM, EXxmm } },
8228     { "vphaddwq",       { XM, EXxmm } },
8229     /* c8 */
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { "vphadddq",       { XM, EXxmm } },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     /* d0 */
8239     { Bad_Opcode },
8240     { "vphaddubw",      { XM, EXxmm } },
8241     { "vphaddubd",      { XM, EXxmm } },
8242     { "vphaddubq",      { XM, EXxmm } },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { "vphadduwd",      { XM, EXxmm } },
8246     { "vphadduwq",      { XM, EXxmm } },
8247     /* d8 */
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { "vphaddudq",      { XM, EXxmm } },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     /* e0 */
8257     { Bad_Opcode },
8258     { "vphsubbw",       { XM, EXxmm } },
8259     { "vphsubwd",       { XM, EXxmm } },
8260     { "vphsubdq",       { XM, EXxmm } },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     /* e8 */
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     /* f0 */
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     /* f8 */
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292   },
8293   /* XOP_0A */
8294   {
8295     /* 00 */
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     /* 08 */
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     /* 10 */
8314     { "bextr",  { Gv, Ev, Iq } },
8315     { Bad_Opcode },
8316     { REG_TABLE (REG_XOP_LWP) },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     /* 18 */
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     /* 20 */
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     /* 28 */
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     /* 30 */
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     /* 38 */
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     /* 40 */
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     /* 48 */
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     /* 50 */
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     /* 58 */
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     /* 60 */
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     /* 68 */
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     /* 70 */
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     /* 78 */
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     /* 80 */
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     /* 88 */
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     /* 90 */
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     /* 98 */
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     /* a0 */
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     /* a8 */
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     /* b0 */
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     /* b8 */
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     /* c0 */
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     /* c8 */
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     /* d0 */
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     /* d8 */
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     /* e0 */
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     /* e8 */
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     /* f0 */
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     /* f8 */
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583   },
8584 };
8585
8586 static const struct dis386 vex_table[][256] = {
8587   /* VEX_0F */
8588   {
8589     /* 00 */
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     /* 08 */
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     /* 10 */
8608     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8609     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8610     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8611     { MOD_TABLE (MOD_VEX_0F13) },
8612     { VEX_W_TABLE (VEX_W_0F14) },
8613     { VEX_W_TABLE (VEX_W_0F15) },
8614     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8615     { MOD_TABLE (MOD_VEX_0F17) },
8616     /* 18 */
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     /* 20 */
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     /* 28 */
8635     { VEX_W_TABLE (VEX_W_0F28) },
8636     { VEX_W_TABLE (VEX_W_0F29) },
8637     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8638     { MOD_TABLE (MOD_VEX_0F2B) },
8639     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8640     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8641     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8642     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8643     /* 30 */
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     /* 38 */
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     /* 40 */
8662     { Bad_Opcode },
8663     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8664     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8665     { Bad_Opcode },
8666     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8667     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8668     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8669     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8670     /* 48 */
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8674     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8675     { Bad_Opcode },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     /* 50 */
8680     { MOD_TABLE (MOD_VEX_0F50) },
8681     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8682     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8683     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8684     { "vandpX",         { XM, Vex, EXx } },
8685     { "vandnpX",        { XM, Vex, EXx } },
8686     { "vorpX",          { XM, Vex, EXx } },
8687     { "vxorpX",         { XM, Vex, EXx } },
8688     /* 58 */
8689     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8690     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8691     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8692     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8693     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8694     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8695     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8696     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8697     /* 60 */
8698     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8706     /* 68 */
8707     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8712     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8713     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8714     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8715     /* 70 */
8716     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8717     { REG_TABLE (REG_VEX_0F71) },
8718     { REG_TABLE (REG_VEX_0F72) },
8719     { REG_TABLE (REG_VEX_0F73) },
8720     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8721     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8723     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8724     /* 78 */
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8733     /* 80 */
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     /* 88 */
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     /* 90 */
8752     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     /* 98 */
8761     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     /* a0 */
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     /* a8 */
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { REG_TABLE (REG_VEX_0FAE) },
8786     { Bad_Opcode },
8787     /* b0 */
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     /* b8 */
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     /* c0 */
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8809     { Bad_Opcode },
8810     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8811     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8812     { "vshufpX",        { XM, Vex, EXx, Ib } },
8813     { Bad_Opcode },
8814     /* c8 */
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     /* d0 */
8824     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8825     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8826     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8827     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8828     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8829     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8830     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8831     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8832     /* d8 */
8833     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8834     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8835     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8836     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8837     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8838     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8839     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8840     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8841     /* e0 */
8842     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8843     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8844     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8845     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8846     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8847     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8848     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8849     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8850     /* e8 */
8851     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8852     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8853     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8854     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8855     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8856     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8857     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8858     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8859     /* f0 */
8860     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8861     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8862     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8863     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8864     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8865     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8866     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8867     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8868     /* f8 */
8869     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8870     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8871     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8872     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8873     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8874     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8875     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8876     { Bad_Opcode },
8877   },
8878   /* VEX_0F38 */
8879   {
8880     /* 00 */
8881     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8882     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8883     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8889     /* 08 */
8890     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8898     /* 10 */
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8907     /* 18 */
8908     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8909     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8911     { Bad_Opcode },
8912     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8915     { Bad_Opcode },
8916     /* 20 */
8917     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     /* 28 */
8926     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8934     /* 30 */
8935     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8943     /* 38 */
8944     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8952     /* 40 */
8953     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8960     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8961     /* 48 */
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     /* 50 */
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     /* 58 */
8980     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8981     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8982     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     /* 60 */
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     /* 68 */
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     /* 70 */
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     /* 78 */
9016     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     /* 80 */
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     /* 88 */
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9039     { Bad_Opcode },
9040     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9041     { Bad_Opcode },
9042     /* 90 */
9043     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9045     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9046     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9051     /* 98 */
9052     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9054     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9055     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9060     /* a0 */
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9068     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9069     /* a8 */
9070     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9078     /* b0 */
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9086     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9087     /* b8 */
9088     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9096     /* c0 */
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     /* c8 */
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     /* d0 */
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     /* d8 */
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9129     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9132     /* e0 */
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     /* e8 */
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     /* f0 */
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9154     { REG_TABLE (REG_VEX_0F38F3) },
9155     { Bad_Opcode },
9156     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9158     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9159     /* f8 */
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168   },
9169   /* VEX_0F3A */
9170   {
9171     /* 00 */
9172     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9173     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9174     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9175     { Bad_Opcode },
9176     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9177     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9178     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9179     { Bad_Opcode },
9180     /* 08 */
9181     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9182     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9183     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9184     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9185     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9186     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9187     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9188     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9189     /* 10 */
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9195     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9196     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9197     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9198     /* 18 */
9199     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9200     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     /* 20 */
9208     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9209     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9210     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     /* 28 */
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     /* 30 */
9226     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9227     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9228     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9229     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     /* 38 */
9235     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9236     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     /* 40 */
9244     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9245     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9246     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9247     { Bad_Opcode },
9248     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9249     { Bad_Opcode },
9250     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9251     { Bad_Opcode },
9252     /* 48 */
9253     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9254     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9255     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9256     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9257     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     /* 50 */
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     /* 58 */
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9276     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9277     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9278     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9279     /* 60 */
9280     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9281     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9282     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9283     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     /* 68 */
9289     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9290     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9291     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9292     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9293     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9294     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9295     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9296     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9297     /* 70 */
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     /* 78 */
9307     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9308     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9309     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9310     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9311     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9312     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9313     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9314     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9315     /* 80 */
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     /* 88 */
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     /* 90 */
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     /* 98 */
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347     { Bad_Opcode },
9348     { Bad_Opcode },
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     /* a0 */
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     /* a8 */
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     { Bad_Opcode },
9369     /* b0 */
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     { Bad_Opcode },
9373     { Bad_Opcode },
9374     { Bad_Opcode },
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     /* b8 */
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     /* c0 */
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     /* c8 */
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     /* d0 */
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     { Bad_Opcode },
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     /* d8 */
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9423     /* e0 */
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     { Bad_Opcode },
9427     { Bad_Opcode },
9428     { Bad_Opcode },
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     /* e8 */
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     /* f0 */
9442     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9443     { Bad_Opcode },
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     /* f8 */
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459   },
9460 };
9461
9462 #define NEED_OPCODE_TABLE
9463 #include "i386-dis-evex.h"
9464 #undef NEED_OPCODE_TABLE
9465 static const struct dis386 vex_len_table[][2] = {
9466   /* VEX_LEN_0F10_P_1 */
9467   {
9468     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9469     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9470   },
9471
9472   /* VEX_LEN_0F10_P_3 */
9473   {
9474     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9475     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9476   },
9477
9478   /* VEX_LEN_0F11_P_1 */
9479   {
9480     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9481     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9482   },
9483
9484   /* VEX_LEN_0F11_P_3 */
9485   {
9486     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9487     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9488   },
9489
9490   /* VEX_LEN_0F12_P_0_M_0 */
9491   {
9492     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9493   },
9494
9495   /* VEX_LEN_0F12_P_0_M_1 */
9496   {
9497     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9498   },
9499
9500   /* VEX_LEN_0F12_P_2 */
9501   {
9502     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9503   },
9504
9505   /* VEX_LEN_0F13_M_0 */
9506   {
9507     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9508   },
9509
9510   /* VEX_LEN_0F16_P_0_M_0 */
9511   {
9512     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9513   },
9514
9515   /* VEX_LEN_0F16_P_0_M_1 */
9516   {
9517     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9518   },
9519
9520   /* VEX_LEN_0F16_P_2 */
9521   {
9522     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9523   },
9524
9525   /* VEX_LEN_0F17_M_0 */
9526   {
9527     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9528   },
9529
9530   /* VEX_LEN_0F2A_P_1 */
9531   {
9532     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9533     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9534   },
9535
9536   /* VEX_LEN_0F2A_P_3 */
9537   {
9538     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9539     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9540   },
9541
9542   /* VEX_LEN_0F2C_P_1 */
9543   {
9544     { "vcvttss2siY",    { Gv, EXdScalar } },
9545     { "vcvttss2siY",    { Gv, EXdScalar } },
9546   },
9547
9548   /* VEX_LEN_0F2C_P_3 */
9549   {
9550     { "vcvttsd2siY",    { Gv, EXqScalar } },
9551     { "vcvttsd2siY",    { Gv, EXqScalar } },
9552   },
9553
9554   /* VEX_LEN_0F2D_P_1 */
9555   {
9556     { "vcvtss2siY",     { Gv, EXdScalar } },
9557     { "vcvtss2siY",     { Gv, EXdScalar } },
9558   },
9559
9560   /* VEX_LEN_0F2D_P_3 */
9561   {
9562     { "vcvtsd2siY",     { Gv, EXqScalar } },
9563     { "vcvtsd2siY",     { Gv, EXqScalar } },
9564   },
9565
9566   /* VEX_LEN_0F2E_P_0 */
9567   {
9568     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9569     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9570   },
9571
9572   /* VEX_LEN_0F2E_P_2 */
9573   {
9574     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9575     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9576   },
9577
9578   /* VEX_LEN_0F2F_P_0 */
9579   {
9580     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9581     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9582   },
9583
9584   /* VEX_LEN_0F2F_P_2 */
9585   {
9586     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9587     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9588   },
9589
9590   /* VEX_LEN_0F41_P_0 */
9591   {
9592     { Bad_Opcode },
9593     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9594   },
9595   /* VEX_LEN_0F41_P_2 */
9596   {
9597     { Bad_Opcode },
9598     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9599   },
9600   /* VEX_LEN_0F42_P_0 */
9601   {
9602     { Bad_Opcode },
9603     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9604   },
9605   /* VEX_LEN_0F42_P_2 */
9606   {
9607     { Bad_Opcode },
9608     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9609   },
9610   /* VEX_LEN_0F44_P_0 */
9611   {
9612     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9613   },
9614   /* VEX_LEN_0F44_P_2 */
9615   {
9616     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9617   },
9618   /* VEX_LEN_0F45_P_0 */
9619   {
9620     { Bad_Opcode },
9621     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9622   },
9623   /* VEX_LEN_0F45_P_2 */
9624   {
9625     { Bad_Opcode },
9626     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9627   },
9628   /* VEX_LEN_0F46_P_0 */
9629   {
9630     { Bad_Opcode },
9631     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9632   },
9633   /* VEX_LEN_0F46_P_2 */
9634   {
9635     { Bad_Opcode },
9636     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9637   },
9638   /* VEX_LEN_0F47_P_0 */
9639   {
9640     { Bad_Opcode },
9641     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9642   },
9643   /* VEX_LEN_0F47_P_2 */
9644   {
9645     { Bad_Opcode },
9646     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9647   },
9648   /* VEX_LEN_0F4A_P_0 */
9649   {
9650     { Bad_Opcode },
9651     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9652   },
9653   /* VEX_LEN_0F4A_P_2 */
9654   {
9655     { Bad_Opcode },
9656     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9657   },
9658   /* VEX_LEN_0F4B_P_0 */
9659   {
9660     { Bad_Opcode },
9661     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9662   },
9663   /* VEX_LEN_0F4B_P_2 */
9664   {
9665     { Bad_Opcode },
9666     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9667   },
9668
9669   /* VEX_LEN_0F51_P_1 */
9670   {
9671     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9672     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9673   },
9674
9675   /* VEX_LEN_0F51_P_3 */
9676   {
9677     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9678     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9679   },
9680
9681   /* VEX_LEN_0F52_P_1 */
9682   {
9683     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9684     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9685   },
9686
9687   /* VEX_LEN_0F53_P_1 */
9688   {
9689     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9690     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9691   },
9692
9693   /* VEX_LEN_0F58_P_1 */
9694   {
9695     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9696     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9697   },
9698
9699   /* VEX_LEN_0F58_P_3 */
9700   {
9701     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9702     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9703   },
9704
9705   /* VEX_LEN_0F59_P_1 */
9706   {
9707     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9708     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9709   },
9710
9711   /* VEX_LEN_0F59_P_3 */
9712   {
9713     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9714     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9715   },
9716
9717   /* VEX_LEN_0F5A_P_1 */
9718   {
9719     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9720     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9721   },
9722
9723   /* VEX_LEN_0F5A_P_3 */
9724   {
9725     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9726     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9727   },
9728
9729   /* VEX_LEN_0F5C_P_1 */
9730   {
9731     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9732     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9733   },
9734
9735   /* VEX_LEN_0F5C_P_3 */
9736   {
9737     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9738     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9739   },
9740
9741   /* VEX_LEN_0F5D_P_1 */
9742   {
9743     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9744     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9745   },
9746
9747   /* VEX_LEN_0F5D_P_3 */
9748   {
9749     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9750     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9751   },
9752
9753   /* VEX_LEN_0F5E_P_1 */
9754   {
9755     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9756     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9757   },
9758
9759   /* VEX_LEN_0F5E_P_3 */
9760   {
9761     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9762     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9763   },
9764
9765   /* VEX_LEN_0F5F_P_1 */
9766   {
9767     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9768     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9769   },
9770
9771   /* VEX_LEN_0F5F_P_3 */
9772   {
9773     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9774     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9775   },
9776
9777   /* VEX_LEN_0F6E_P_2 */
9778   {
9779     { "vmovK",          { XMScalar, Edq } },
9780     { "vmovK",          { XMScalar, Edq } },
9781   },
9782
9783   /* VEX_LEN_0F7E_P_1 */
9784   {
9785     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9786     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9787   },
9788
9789   /* VEX_LEN_0F7E_P_2 */
9790   {
9791     { "vmovK",          { Edq, XMScalar } },
9792     { "vmovK",          { Edq, XMScalar } },
9793   },
9794
9795   /* VEX_LEN_0F90_P_0 */
9796   {
9797     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9798   },
9799
9800   /* VEX_LEN_0F90_P_2 */
9801   {
9802     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9803   },
9804
9805   /* VEX_LEN_0F91_P_0 */
9806   {
9807     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9808   },
9809
9810   /* VEX_LEN_0F91_P_2 */
9811   {
9812     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9813   },
9814
9815   /* VEX_LEN_0F92_P_0 */
9816   {
9817     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9818   },
9819
9820   /* VEX_LEN_0F92_P_2 */
9821   {
9822     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9823   },
9824
9825   /* VEX_LEN_0F92_P_3 */
9826   {
9827     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9828   },
9829
9830   /* VEX_LEN_0F93_P_0 */
9831   {
9832     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9833   },
9834
9835   /* VEX_LEN_0F93_P_2 */
9836   {
9837     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9838   },
9839
9840   /* VEX_LEN_0F93_P_3 */
9841   {
9842     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9843   },
9844
9845   /* VEX_LEN_0F98_P_0 */
9846   {
9847     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9848   },
9849
9850   /* VEX_LEN_0F98_P_2 */
9851   {
9852     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9853   },
9854
9855   /* VEX_LEN_0F99_P_0 */
9856   {
9857     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9858   },
9859
9860   /* VEX_LEN_0F99_P_2 */
9861   {
9862     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9863   },
9864
9865   /* VEX_LEN_0FAE_R_2_M_0 */
9866   {
9867     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9868   },
9869
9870   /* VEX_LEN_0FAE_R_3_M_0 */
9871   {
9872     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9873   },
9874
9875   /* VEX_LEN_0FC2_P_1 */
9876   {
9877     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9878     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9879   },
9880
9881   /* VEX_LEN_0FC2_P_3 */
9882   {
9883     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9884     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9885   },
9886
9887   /* VEX_LEN_0FC4_P_2 */
9888   {
9889     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9890   },
9891
9892   /* VEX_LEN_0FC5_P_2 */
9893   {
9894     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9895   },
9896
9897   /* VEX_LEN_0FD6_P_2 */
9898   {
9899     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9900     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9901   },
9902
9903   /* VEX_LEN_0FF7_P_2 */
9904   {
9905     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9906   },
9907
9908   /* VEX_LEN_0F3816_P_2 */
9909   {
9910     { Bad_Opcode },
9911     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9912   },
9913
9914   /* VEX_LEN_0F3819_P_2 */
9915   {
9916     { Bad_Opcode },
9917     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9918   },
9919
9920   /* VEX_LEN_0F381A_P_2_M_0 */
9921   {
9922     { Bad_Opcode },
9923     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9924   },
9925
9926   /* VEX_LEN_0F3836_P_2 */
9927   {
9928     { Bad_Opcode },
9929     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9930   },
9931
9932   /* VEX_LEN_0F3841_P_2 */
9933   {
9934     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9935   },
9936
9937   /* VEX_LEN_0F385A_P_2_M_0 */
9938   {
9939     { Bad_Opcode },
9940     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9941   },
9942
9943   /* VEX_LEN_0F38DB_P_2 */
9944   {
9945     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9946   },
9947
9948   /* VEX_LEN_0F38DC_P_2 */
9949   {
9950     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9951   },
9952
9953   /* VEX_LEN_0F38DD_P_2 */
9954   {
9955     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9956   },
9957
9958   /* VEX_LEN_0F38DE_P_2 */
9959   {
9960     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9961   },
9962
9963   /* VEX_LEN_0F38DF_P_2 */
9964   {
9965     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9966   },
9967
9968   /* VEX_LEN_0F38F2_P_0 */
9969   {
9970     { "andnS",          { Gdq, VexGdq, Edq } },
9971   },
9972
9973   /* VEX_LEN_0F38F3_R_1_P_0 */
9974   {
9975     { "blsrS",          { VexGdq, Edq } },
9976   },
9977
9978   /* VEX_LEN_0F38F3_R_2_P_0 */
9979   {
9980     { "blsmskS",        { VexGdq, Edq } },
9981   },
9982
9983   /* VEX_LEN_0F38F3_R_3_P_0 */
9984   {
9985     { "blsiS",          { VexGdq, Edq } },
9986   },
9987
9988   /* VEX_LEN_0F38F5_P_0 */
9989   {
9990     { "bzhiS",          { Gdq, Edq, VexGdq } },
9991   },
9992
9993   /* VEX_LEN_0F38F5_P_1 */
9994   {
9995     { "pextS",          { Gdq, VexGdq, Edq } },
9996   },
9997
9998   /* VEX_LEN_0F38F5_P_3 */
9999   {
10000     { "pdepS",          { Gdq, VexGdq, Edq } },
10001   },
10002
10003   /* VEX_LEN_0F38F6_P_3 */
10004   {
10005     { "mulxS",          { Gdq, VexGdq, Edq } },
10006   },
10007
10008   /* VEX_LEN_0F38F7_P_0 */
10009   {
10010     { "bextrS",         { Gdq, Edq, VexGdq } },
10011   },
10012
10013   /* VEX_LEN_0F38F7_P_1 */
10014   {
10015     { "sarxS",          { Gdq, Edq, VexGdq } },
10016   },
10017
10018   /* VEX_LEN_0F38F7_P_2 */
10019   {
10020     { "shlxS",          { Gdq, Edq, VexGdq } },
10021   },
10022
10023   /* VEX_LEN_0F38F7_P_3 */
10024   {
10025     { "shrxS",          { Gdq, Edq, VexGdq } },
10026   },
10027
10028   /* VEX_LEN_0F3A00_P_2 */
10029   {
10030     { Bad_Opcode },
10031     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10032   },
10033
10034   /* VEX_LEN_0F3A01_P_2 */
10035   {
10036     { Bad_Opcode },
10037     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10038   },
10039
10040   /* VEX_LEN_0F3A06_P_2 */
10041   {
10042     { Bad_Opcode },
10043     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10044   },
10045
10046   /* VEX_LEN_0F3A0A_P_2 */
10047   {
10048     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10049     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10050   },
10051
10052   /* VEX_LEN_0F3A0B_P_2 */
10053   {
10054     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10055     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10056   },
10057
10058   /* VEX_LEN_0F3A14_P_2 */
10059   {
10060     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10061   },
10062
10063   /* VEX_LEN_0F3A15_P_2 */
10064   {
10065     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10066   },
10067
10068   /* VEX_LEN_0F3A16_P_2  */
10069   {
10070     { "vpextrK",        { Edq, XM, Ib } },
10071   },
10072
10073   /* VEX_LEN_0F3A17_P_2 */
10074   {
10075     { "vextractps",     { Edqd, XM, Ib } },
10076   },
10077
10078   /* VEX_LEN_0F3A18_P_2 */
10079   {
10080     { Bad_Opcode },
10081     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10082   },
10083
10084   /* VEX_LEN_0F3A19_P_2 */
10085   {
10086     { Bad_Opcode },
10087     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10088   },
10089
10090   /* VEX_LEN_0F3A20_P_2 */
10091   {
10092     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10093   },
10094
10095   /* VEX_LEN_0F3A21_P_2 */
10096   {
10097     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10098   },
10099
10100   /* VEX_LEN_0F3A22_P_2 */
10101   {
10102     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
10103   },
10104
10105   /* VEX_LEN_0F3A30_P_2 */
10106   {
10107     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10108   },
10109
10110   /* VEX_LEN_0F3A31_P_2 */
10111   {
10112     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10113   },
10114
10115   /* VEX_LEN_0F3A32_P_2 */
10116   {
10117     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10118   },
10119
10120   /* VEX_LEN_0F3A33_P_2 */
10121   {
10122     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10123   },
10124
10125   /* VEX_LEN_0F3A38_P_2 */
10126   {
10127     { Bad_Opcode },
10128     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10129   },
10130
10131   /* VEX_LEN_0F3A39_P_2 */
10132   {
10133     { Bad_Opcode },
10134     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10135   },
10136
10137   /* VEX_LEN_0F3A41_P_2 */
10138   {
10139     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10140   },
10141
10142   /* VEX_LEN_0F3A44_P_2 */
10143   {
10144     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10145   },
10146
10147   /* VEX_LEN_0F3A46_P_2 */
10148   {
10149     { Bad_Opcode },
10150     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10151   },
10152
10153   /* VEX_LEN_0F3A60_P_2 */
10154   {
10155     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10156   },
10157
10158   /* VEX_LEN_0F3A61_P_2 */
10159   {
10160     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10161   },
10162
10163   /* VEX_LEN_0F3A62_P_2 */
10164   {
10165     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10166   },
10167
10168   /* VEX_LEN_0F3A63_P_2 */
10169   {
10170     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10171   },
10172
10173   /* VEX_LEN_0F3A6A_P_2 */
10174   {
10175     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10176   },
10177
10178   /* VEX_LEN_0F3A6B_P_2 */
10179   {
10180     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10181   },
10182
10183   /* VEX_LEN_0F3A6E_P_2 */
10184   {
10185     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10186   },
10187
10188   /* VEX_LEN_0F3A6F_P_2 */
10189   {
10190     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10191   },
10192
10193   /* VEX_LEN_0F3A7A_P_2 */
10194   {
10195     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10196   },
10197
10198   /* VEX_LEN_0F3A7B_P_2 */
10199   {
10200     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10201   },
10202
10203   /* VEX_LEN_0F3A7E_P_2 */
10204   {
10205     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10206   },
10207
10208   /* VEX_LEN_0F3A7F_P_2 */
10209   {
10210     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10211   },
10212
10213   /* VEX_LEN_0F3ADF_P_2 */
10214   {
10215     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10216   },
10217
10218   /* VEX_LEN_0F3AF0_P_3 */
10219   {
10220     { "rorxS",          { Gdq, Edq, Ib } },
10221   },
10222
10223   /* VEX_LEN_0FXOP_08_CC */
10224   {
10225      { "vpcomb",        { XM, Vex128, EXx, Ib } },
10226   },
10227
10228   /* VEX_LEN_0FXOP_08_CD */
10229   {
10230      { "vpcomw",        { XM, Vex128, EXx, Ib } },
10231   },
10232
10233   /* VEX_LEN_0FXOP_08_CE */
10234   {
10235      { "vpcomd",        { XM, Vex128, EXx, Ib } },
10236   },
10237
10238   /* VEX_LEN_0FXOP_08_CF */
10239   {
10240      { "vpcomq",        { XM, Vex128, EXx, Ib } },
10241   },
10242
10243   /* VEX_LEN_0FXOP_08_EC */
10244   {
10245      { "vpcomub",       { XM, Vex128, EXx, Ib } },
10246   },
10247
10248   /* VEX_LEN_0FXOP_08_ED */
10249   {
10250      { "vpcomuw",       { XM, Vex128, EXx, Ib } },
10251   },
10252
10253   /* VEX_LEN_0FXOP_08_EE */
10254   {
10255      { "vpcomud",       { XM, Vex128, EXx, Ib } },
10256   },
10257
10258   /* VEX_LEN_0FXOP_08_EF */
10259   {
10260      { "vpcomuq",       { XM, Vex128, EXx, Ib } },
10261   },
10262
10263   /* VEX_LEN_0FXOP_09_80 */
10264   {
10265     { "vfrczps",        { XM, EXxmm } },
10266     { "vfrczps",        { XM, EXymmq } },
10267   },
10268
10269   /* VEX_LEN_0FXOP_09_81 */
10270   {
10271     { "vfrczpd",        { XM, EXxmm } },
10272     { "vfrczpd",        { XM, EXymmq } },
10273   },
10274 };
10275
10276 static const struct dis386 vex_w_table[][2] = {
10277   {
10278     /* VEX_W_0F10_P_0 */
10279     { "vmovups",        { XM, EXx } },
10280   },
10281   {
10282     /* VEX_W_0F10_P_1 */
10283     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
10284   },
10285   {
10286     /* VEX_W_0F10_P_2 */
10287     { "vmovupd",        { XM, EXx } },
10288   },
10289   {
10290     /* VEX_W_0F10_P_3 */
10291     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
10292   },
10293   {
10294     /* VEX_W_0F11_P_0 */
10295     { "vmovups",        { EXxS, XM } },
10296   },
10297   {
10298     /* VEX_W_0F11_P_1 */
10299     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
10300   },
10301   {
10302     /* VEX_W_0F11_P_2 */
10303     { "vmovupd",        { EXxS, XM } },
10304   },
10305   {
10306     /* VEX_W_0F11_P_3 */
10307     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
10308   },
10309   {
10310     /* VEX_W_0F12_P_0_M_0 */
10311     { "vmovlps",        { XM, Vex128, EXq } },
10312   },
10313   {
10314     /* VEX_W_0F12_P_0_M_1 */
10315     { "vmovhlps",       { XM, Vex128, EXq } },
10316   },
10317   {
10318     /* VEX_W_0F12_P_1 */
10319     { "vmovsldup",      { XM, EXx } },
10320   },
10321   {
10322     /* VEX_W_0F12_P_2 */
10323     { "vmovlpd",        { XM, Vex128, EXq } },
10324   },
10325   {
10326     /* VEX_W_0F12_P_3 */
10327     { "vmovddup",       { XM, EXymmq } },
10328   },
10329   {
10330     /* VEX_W_0F13_M_0 */
10331     { "vmovlpX",        { EXq, XM } },
10332   },
10333   {
10334     /* VEX_W_0F14 */
10335     { "vunpcklpX",      { XM, Vex, EXx } },
10336   },
10337   {
10338     /* VEX_W_0F15 */
10339     { "vunpckhpX",      { XM, Vex, EXx } },
10340   },
10341   {
10342     /* VEX_W_0F16_P_0_M_0 */
10343     { "vmovhps",        { XM, Vex128, EXq } },
10344   },
10345   {
10346     /* VEX_W_0F16_P_0_M_1 */
10347     { "vmovlhps",       { XM, Vex128, EXq } },
10348   },
10349   {
10350     /* VEX_W_0F16_P_1 */
10351     { "vmovshdup",      { XM, EXx } },
10352   },
10353   {
10354     /* VEX_W_0F16_P_2 */
10355     { "vmovhpd",        { XM, Vex128, EXq } },
10356   },
10357   {
10358     /* VEX_W_0F17_M_0 */
10359     { "vmovhpX",        { EXq, XM } },
10360   },
10361   {
10362     /* VEX_W_0F28 */
10363     { "vmovapX",        { XM, EXx } },
10364   },
10365   {
10366     /* VEX_W_0F29 */
10367     { "vmovapX",        { EXxS, XM } },
10368   },
10369   {
10370     /* VEX_W_0F2B_M_0 */
10371     { "vmovntpX",       { Mx, XM } },
10372   },
10373   {
10374     /* VEX_W_0F2E_P_0 */
10375     { "vucomiss",       { XMScalar, EXdScalar } },
10376   },
10377   {
10378     /* VEX_W_0F2E_P_2 */
10379     { "vucomisd",       { XMScalar, EXqScalar } },
10380   },
10381   {
10382     /* VEX_W_0F2F_P_0 */
10383     { "vcomiss",        { XMScalar, EXdScalar } },
10384   },
10385   {
10386     /* VEX_W_0F2F_P_2 */
10387     { "vcomisd",        { XMScalar, EXqScalar } },
10388   },
10389   {
10390     /* VEX_W_0F41_P_0_LEN_1 */
10391     { "kandw",          { MaskG, MaskVex, MaskR } },
10392     { "kandq",          { MaskG, MaskVex, MaskR } },
10393   },
10394   {
10395     /* VEX_W_0F41_P_2_LEN_1 */
10396     { "kandb",          { MaskG, MaskVex, MaskR } },
10397     { "kandd",          { MaskG, MaskVex, MaskR } },
10398   },
10399   {
10400     /* VEX_W_0F42_P_0_LEN_1 */
10401     { "kandnw",         { MaskG, MaskVex, MaskR } },
10402     { "kandnq",         { MaskG, MaskVex, MaskR } },
10403   },
10404   {
10405     /* VEX_W_0F42_P_2_LEN_1 */
10406     { "kandnb",         { MaskG, MaskVex, MaskR } },
10407     { "kandnd",         { MaskG, MaskVex, MaskR } },
10408   },
10409   {
10410     /* VEX_W_0F44_P_0_LEN_0 */
10411     { "knotw",          { MaskG, MaskR } },
10412     { "knotq",          { MaskG, MaskR } },
10413   },
10414   {
10415     /* VEX_W_0F44_P_2_LEN_0 */
10416     { "knotb",          { MaskG, MaskR } },
10417     { "knotd",          { MaskG, MaskR } },
10418   },
10419   {
10420     /* VEX_W_0F45_P_0_LEN_1 */
10421     { "korw",           { MaskG, MaskVex, MaskR } },
10422     { "korq",           { MaskG, MaskVex, MaskR } },
10423   },
10424   {
10425     /* VEX_W_0F45_P_2_LEN_1 */
10426     { "korb",           { MaskG, MaskVex, MaskR } },
10427     { "kord",           { MaskG, MaskVex, MaskR } },
10428   },
10429   {
10430     /* VEX_W_0F46_P_0_LEN_1 */
10431     { "kxnorw",         { MaskG, MaskVex, MaskR } },
10432     { "kxnorq",         { MaskG, MaskVex, MaskR } },
10433   },
10434   {
10435     /* VEX_W_0F46_P_2_LEN_1 */
10436     { "kxnorb",         { MaskG, MaskVex, MaskR } },
10437     { "kxnord",         { MaskG, MaskVex, MaskR } },
10438   },
10439   {
10440     /* VEX_W_0F47_P_0_LEN_1 */
10441     { "kxorw",          { MaskG, MaskVex, MaskR } },
10442     { "kxorq",          { MaskG, MaskVex, MaskR } },
10443   },
10444   {
10445     /* VEX_W_0F47_P_2_LEN_1 */
10446     { "kxorb",          { MaskG, MaskVex, MaskR } },
10447     { "kxord",          { MaskG, MaskVex, MaskR } },
10448   },
10449   {
10450     /* VEX_W_0F4A_P_0_LEN_1 */
10451     { "kaddw",          { MaskG, MaskVex, MaskR } },
10452     { "kaddq",          { MaskG, MaskVex, MaskR } },
10453   },
10454   {
10455     /* VEX_W_0F4A_P_2_LEN_1 */
10456     { "kaddb",          { MaskG, MaskVex, MaskR } },
10457     { "kaddd",          { MaskG, MaskVex, MaskR } },
10458   },
10459   {
10460     /* VEX_W_0F4B_P_0_LEN_1 */
10461     { "kunpckwd",       { MaskG, MaskVex, MaskR } },
10462     { "kunpckdq",       { MaskG, MaskVex, MaskR } },
10463   },
10464   {
10465     /* VEX_W_0F4B_P_2_LEN_1 */
10466     { "kunpckbw",       { MaskG, MaskVex, MaskR } },
10467   },
10468   {
10469     /* VEX_W_0F50_M_0 */
10470     { "vmovmskpX",      { Gdq, XS } },
10471   },
10472   {
10473     /* VEX_W_0F51_P_0 */
10474     { "vsqrtps",        { XM, EXx } },
10475   },
10476   {
10477     /* VEX_W_0F51_P_1 */
10478     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
10479   },
10480   {
10481     /* VEX_W_0F51_P_2  */
10482     { "vsqrtpd",        { XM, EXx } },
10483   },
10484   {
10485     /* VEX_W_0F51_P_3 */
10486     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
10487   },
10488   {
10489     /* VEX_W_0F52_P_0 */
10490     { "vrsqrtps",       { XM, EXx } },
10491   },
10492   {
10493     /* VEX_W_0F52_P_1 */
10494     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
10495   },
10496   {
10497     /* VEX_W_0F53_P_0  */
10498     { "vrcpps",         { XM, EXx } },
10499   },
10500   {
10501     /* VEX_W_0F53_P_1  */
10502     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
10503   },
10504   {
10505     /* VEX_W_0F58_P_0  */
10506     { "vaddps",         { XM, Vex, EXx } },
10507   },
10508   {
10509     /* VEX_W_0F58_P_1  */
10510     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
10511   },
10512   {
10513     /* VEX_W_0F58_P_2  */
10514     { "vaddpd",         { XM, Vex, EXx } },
10515   },
10516   {
10517     /* VEX_W_0F58_P_3  */
10518     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
10519   },
10520   {
10521     /* VEX_W_0F59_P_0  */
10522     { "vmulps",         { XM, Vex, EXx } },
10523   },
10524   {
10525     /* VEX_W_0F59_P_1  */
10526     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
10527   },
10528   {
10529     /* VEX_W_0F59_P_2  */
10530     { "vmulpd",         { XM, Vex, EXx } },
10531   },
10532   {
10533     /* VEX_W_0F59_P_3  */
10534     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
10535   },
10536   {
10537     /* VEX_W_0F5A_P_0  */
10538     { "vcvtps2pd",      { XM, EXxmmq } },
10539   },
10540   {
10541     /* VEX_W_0F5A_P_1  */
10542     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
10543   },
10544   {
10545     /* VEX_W_0F5A_P_3  */
10546     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
10547   },
10548   {
10549     /* VEX_W_0F5B_P_0  */
10550     { "vcvtdq2ps",      { XM, EXx } },
10551   },
10552   {
10553     /* VEX_W_0F5B_P_1  */
10554     { "vcvttps2dq",     { XM, EXx } },
10555   },
10556   {
10557     /* VEX_W_0F5B_P_2  */
10558     { "vcvtps2dq",      { XM, EXx } },
10559   },
10560   {
10561     /* VEX_W_0F5C_P_0  */
10562     { "vsubps",         { XM, Vex, EXx } },
10563   },
10564   {
10565     /* VEX_W_0F5C_P_1  */
10566     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
10567   },
10568   {
10569     /* VEX_W_0F5C_P_2  */
10570     { "vsubpd",         { XM, Vex, EXx } },
10571   },
10572   {
10573     /* VEX_W_0F5C_P_3  */
10574     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
10575   },
10576   {
10577     /* VEX_W_0F5D_P_0  */
10578     { "vminps",         { XM, Vex, EXx } },
10579   },
10580   {
10581     /* VEX_W_0F5D_P_1  */
10582     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
10583   },
10584   {
10585     /* VEX_W_0F5D_P_2  */
10586     { "vminpd",         { XM, Vex, EXx } },
10587   },
10588   {
10589     /* VEX_W_0F5D_P_3  */
10590     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
10591   },
10592   {
10593     /* VEX_W_0F5E_P_0  */
10594     { "vdivps",         { XM, Vex, EXx } },
10595   },
10596   {
10597     /* VEX_W_0F5E_P_1  */
10598     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
10599   },
10600   {
10601     /* VEX_W_0F5E_P_2  */
10602     { "vdivpd",         { XM, Vex, EXx } },
10603   },
10604   {
10605     /* VEX_W_0F5E_P_3  */
10606     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
10607   },
10608   {
10609     /* VEX_W_0F5F_P_0  */
10610     { "vmaxps",         { XM, Vex, EXx } },
10611   },
10612   {
10613     /* VEX_W_0F5F_P_1  */
10614     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
10615   },
10616   {
10617     /* VEX_W_0F5F_P_2  */
10618     { "vmaxpd",         { XM, Vex, EXx } },
10619   },
10620   {
10621     /* VEX_W_0F5F_P_3  */
10622     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
10623   },
10624   {
10625     /* VEX_W_0F60_P_2  */
10626     { "vpunpcklbw",     { XM, Vex, EXx } },
10627   },
10628   {
10629     /* VEX_W_0F61_P_2  */
10630     { "vpunpcklwd",     { XM, Vex, EXx } },
10631   },
10632   {
10633     /* VEX_W_0F62_P_2  */
10634     { "vpunpckldq",     { XM, Vex, EXx } },
10635   },
10636   {
10637     /* VEX_W_0F63_P_2  */
10638     { "vpacksswb",      { XM, Vex, EXx } },
10639   },
10640   {
10641     /* VEX_W_0F64_P_2  */
10642     { "vpcmpgtb",       { XM, Vex, EXx } },
10643   },
10644   {
10645     /* VEX_W_0F65_P_2  */
10646     { "vpcmpgtw",       { XM, Vex, EXx } },
10647   },
10648   {
10649     /* VEX_W_0F66_P_2  */
10650     { "vpcmpgtd",       { XM, Vex, EXx } },
10651   },
10652   {
10653     /* VEX_W_0F67_P_2  */
10654     { "vpackuswb",      { XM, Vex, EXx } },
10655   },
10656   {
10657     /* VEX_W_0F68_P_2  */
10658     { "vpunpckhbw",     { XM, Vex, EXx } },
10659   },
10660   {
10661     /* VEX_W_0F69_P_2  */
10662     { "vpunpckhwd",     { XM, Vex, EXx } },
10663   },
10664   {
10665     /* VEX_W_0F6A_P_2  */
10666     { "vpunpckhdq",     { XM, Vex, EXx } },
10667   },
10668   {
10669     /* VEX_W_0F6B_P_2  */
10670     { "vpackssdw",      { XM, Vex, EXx } },
10671   },
10672   {
10673     /* VEX_W_0F6C_P_2  */
10674     { "vpunpcklqdq",    { XM, Vex, EXx } },
10675   },
10676   {
10677     /* VEX_W_0F6D_P_2  */
10678     { "vpunpckhqdq",    { XM, Vex, EXx } },
10679   },
10680   {
10681     /* VEX_W_0F6F_P_1  */
10682     { "vmovdqu",        { XM, EXx } },
10683   },
10684   {
10685     /* VEX_W_0F6F_P_2  */
10686     { "vmovdqa",        { XM, EXx } },
10687   },
10688   {
10689     /* VEX_W_0F70_P_1 */
10690     { "vpshufhw",       { XM, EXx, Ib } },
10691   },
10692   {
10693     /* VEX_W_0F70_P_2 */
10694     { "vpshufd",        { XM, EXx, Ib } },
10695   },
10696   {
10697     /* VEX_W_0F70_P_3 */
10698     { "vpshuflw",       { XM, EXx, Ib } },
10699   },
10700   {
10701     /* VEX_W_0F71_R_2_P_2  */
10702     { "vpsrlw",         { Vex, XS, Ib } },
10703   },
10704   {
10705     /* VEX_W_0F71_R_4_P_2  */
10706     { "vpsraw",         { Vex, XS, Ib } },
10707   },
10708   {
10709     /* VEX_W_0F71_R_6_P_2  */
10710     { "vpsllw",         { Vex, XS, Ib } },
10711   },
10712   {
10713     /* VEX_W_0F72_R_2_P_2  */
10714     { "vpsrld",         { Vex, XS, Ib } },
10715   },
10716   {
10717     /* VEX_W_0F72_R_4_P_2  */
10718     { "vpsrad",         { Vex, XS, Ib } },
10719   },
10720   {
10721     /* VEX_W_0F72_R_6_P_2  */
10722     { "vpslld",         { Vex, XS, Ib } },
10723   },
10724   {
10725     /* VEX_W_0F73_R_2_P_2  */
10726     { "vpsrlq",         { Vex, XS, Ib } },
10727   },
10728   {
10729     /* VEX_W_0F73_R_3_P_2  */
10730     { "vpsrldq",        { Vex, XS, Ib } },
10731   },
10732   {
10733     /* VEX_W_0F73_R_6_P_2  */
10734     { "vpsllq",         { Vex, XS, Ib } },
10735   },
10736   {
10737     /* VEX_W_0F73_R_7_P_2  */
10738     { "vpslldq",        { Vex, XS, Ib } },
10739   },
10740   {
10741     /* VEX_W_0F74_P_2 */
10742     { "vpcmpeqb",       { XM, Vex, EXx } },
10743   },
10744   {
10745     /* VEX_W_0F75_P_2 */
10746     { "vpcmpeqw",       { XM, Vex, EXx } },
10747   },
10748   {
10749     /* VEX_W_0F76_P_2 */
10750     { "vpcmpeqd",       { XM, Vex, EXx } },
10751   },
10752   {
10753     /* VEX_W_0F77_P_0 */
10754     { "",               { VZERO } },
10755   },
10756   {
10757     /* VEX_W_0F7C_P_2 */
10758     { "vhaddpd",        { XM, Vex, EXx } },
10759   },
10760   {
10761     /* VEX_W_0F7C_P_3 */
10762     { "vhaddps",        { XM, Vex, EXx } },
10763   },
10764   {
10765     /* VEX_W_0F7D_P_2 */
10766     { "vhsubpd",        { XM, Vex, EXx } },
10767   },
10768   {
10769     /* VEX_W_0F7D_P_3 */
10770     { "vhsubps",        { XM, Vex, EXx } },
10771   },
10772   {
10773     /* VEX_W_0F7E_P_1 */
10774     { "vmovq",          { XMScalar, EXqScalar } },
10775   },
10776   {
10777     /* VEX_W_0F7F_P_1 */
10778     { "vmovdqu",        { EXxS, XM } },
10779   },
10780   {
10781     /* VEX_W_0F7F_P_2 */
10782     { "vmovdqa",        { EXxS, XM } },
10783   },
10784   {
10785     /* VEX_W_0F90_P_0_LEN_0 */
10786     { "kmovw",          { MaskG, MaskE } },
10787     { "kmovq",          { MaskG, MaskE } },
10788   },
10789   {
10790     /* VEX_W_0F90_P_2_LEN_0 */
10791     { "kmovb",          { MaskG, MaskBDE } },
10792     { "kmovd",          { MaskG, MaskBDE } },
10793   },
10794   {
10795     /* VEX_W_0F91_P_0_LEN_0 */
10796     { "kmovw",          { Ew, MaskG } },
10797     { "kmovq",          { Eq, MaskG } },
10798   },
10799   {
10800     /* VEX_W_0F91_P_2_LEN_0 */
10801     { "kmovb",          { Eb, MaskG } },
10802     { "kmovd",          { Ed, MaskG } },
10803   },
10804   {
10805     /* VEX_W_0F92_P_0_LEN_0 */
10806     { "kmovw",          { MaskG, Rdq } },
10807   },
10808   {
10809     /* VEX_W_0F92_P_2_LEN_0 */
10810     { "kmovb",          { MaskG, Rdq } },
10811   },
10812   {
10813     /* VEX_W_0F92_P_3_LEN_0 */
10814     { "kmovd",          { MaskG, Rdq } },
10815     { "kmovq",          { MaskG, Rdq } },
10816   },
10817   {
10818     /* VEX_W_0F93_P_0_LEN_0 */
10819     { "kmovw",          { Gdq, MaskR } },
10820   },
10821   {
10822     /* VEX_W_0F93_P_2_LEN_0 */
10823     { "kmovb",          { Gdq, MaskR } },
10824   },
10825   {
10826     /* VEX_W_0F93_P_3_LEN_0 */
10827     { "kmovd",          { Gdq, MaskR } },
10828     { "kmovq",          { Gdq, MaskR } },
10829   },
10830   {
10831     /* VEX_W_0F98_P_0_LEN_0 */
10832     { "kortestw",       { MaskG, MaskR } },
10833     { "kortestq",       { MaskG, MaskR } },
10834   },
10835   {
10836     /* VEX_W_0F98_P_2_LEN_0 */
10837     { "kortestb",       { MaskG, MaskR } },
10838     { "kortestd",       { MaskG, MaskR } },
10839   },
10840   {
10841     /* VEX_W_0F99_P_0_LEN_0 */
10842     { "ktestw", { MaskG, MaskR } },
10843     { "ktestq", { MaskG, MaskR } },
10844   },
10845   {
10846     /* VEX_W_0F99_P_2_LEN_0 */
10847     { "ktestb", { MaskG, MaskR } },
10848     { "ktestd", { MaskG, MaskR } },
10849   },
10850   {
10851     /* VEX_W_0FAE_R_2_M_0 */
10852     { "vldmxcsr",       { Md } },
10853   },
10854   {
10855     /* VEX_W_0FAE_R_3_M_0 */
10856     { "vstmxcsr",       { Md } },
10857   },
10858   {
10859     /* VEX_W_0FC2_P_0 */
10860     { "vcmpps",         { XM, Vex, EXx, VCMP } },
10861   },
10862   {
10863     /* VEX_W_0FC2_P_1 */
10864     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
10865   },
10866   {
10867     /* VEX_W_0FC2_P_2 */
10868     { "vcmppd",         { XM, Vex, EXx, VCMP } },
10869   },
10870   {
10871     /* VEX_W_0FC2_P_3 */
10872     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
10873   },
10874   {
10875     /* VEX_W_0FC4_P_2 */
10876     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
10877   },
10878   {
10879     /* VEX_W_0FC5_P_2 */
10880     { "vpextrw",        { Gdq, XS, Ib } },
10881   },
10882   {
10883     /* VEX_W_0FD0_P_2 */
10884     { "vaddsubpd",      { XM, Vex, EXx } },
10885   },
10886   {
10887     /* VEX_W_0FD0_P_3 */
10888     { "vaddsubps",      { XM, Vex, EXx } },
10889   },
10890   {
10891     /* VEX_W_0FD1_P_2 */
10892     { "vpsrlw",         { XM, Vex, EXxmm } },
10893   },
10894   {
10895     /* VEX_W_0FD2_P_2 */
10896     { "vpsrld",         { XM, Vex, EXxmm } },
10897   },
10898   {
10899     /* VEX_W_0FD3_P_2 */
10900     { "vpsrlq",         { XM, Vex, EXxmm } },
10901   },
10902   {
10903     /* VEX_W_0FD4_P_2 */
10904     { "vpaddq",         { XM, Vex, EXx } },
10905   },
10906   {
10907     /* VEX_W_0FD5_P_2 */
10908     { "vpmullw",        { XM, Vex, EXx } },
10909   },
10910   {
10911     /* VEX_W_0FD6_P_2 */
10912     { "vmovq",          { EXqScalarS, XMScalar } },
10913   },
10914   {
10915     /* VEX_W_0FD7_P_2_M_1 */
10916     { "vpmovmskb",      { Gdq, XS } },
10917   },
10918   {
10919     /* VEX_W_0FD8_P_2 */
10920     { "vpsubusb",       { XM, Vex, EXx } },
10921   },
10922   {
10923     /* VEX_W_0FD9_P_2 */
10924     { "vpsubusw",       { XM, Vex, EXx } },
10925   },
10926   {
10927     /* VEX_W_0FDA_P_2 */
10928     { "vpminub",        { XM, Vex, EXx } },
10929   },
10930   {
10931     /* VEX_W_0FDB_P_2 */
10932     { "vpand",          { XM, Vex, EXx } },
10933   },
10934   {
10935     /* VEX_W_0FDC_P_2 */
10936     { "vpaddusb",       { XM, Vex, EXx } },
10937   },
10938   {
10939     /* VEX_W_0FDD_P_2 */
10940     { "vpaddusw",       { XM, Vex, EXx } },
10941   },
10942   {
10943     /* VEX_W_0FDE_P_2 */
10944     { "vpmaxub",        { XM, Vex, EXx } },
10945   },
10946   {
10947     /* VEX_W_0FDF_P_2 */
10948     { "vpandn",         { XM, Vex, EXx } },
10949   },
10950   {
10951     /* VEX_W_0FE0_P_2  */
10952     { "vpavgb",         { XM, Vex, EXx } },
10953   },
10954   {
10955     /* VEX_W_0FE1_P_2  */
10956     { "vpsraw",         { XM, Vex, EXxmm } },
10957   },
10958   {
10959     /* VEX_W_0FE2_P_2  */
10960     { "vpsrad",         { XM, Vex, EXxmm } },
10961   },
10962   {
10963     /* VEX_W_0FE3_P_2  */
10964     { "vpavgw",         { XM, Vex, EXx } },
10965   },
10966   {
10967     /* VEX_W_0FE4_P_2  */
10968     { "vpmulhuw",       { XM, Vex, EXx } },
10969   },
10970   {
10971     /* VEX_W_0FE5_P_2  */
10972     { "vpmulhw",        { XM, Vex, EXx } },
10973   },
10974   {
10975     /* VEX_W_0FE6_P_1  */
10976     { "vcvtdq2pd",      { XM, EXxmmq } },
10977   },
10978   {
10979     /* VEX_W_0FE6_P_2  */
10980     { "vcvttpd2dq%XY",  { XMM, EXx } },
10981   },
10982   {
10983     /* VEX_W_0FE6_P_3  */
10984     { "vcvtpd2dq%XY",   { XMM, EXx } },
10985   },
10986   {
10987     /* VEX_W_0FE7_P_2_M_0 */
10988     { "vmovntdq",       { Mx, XM } },
10989   },
10990   {
10991     /* VEX_W_0FE8_P_2  */
10992     { "vpsubsb",        { XM, Vex, EXx } },
10993   },
10994   {
10995     /* VEX_W_0FE9_P_2  */
10996     { "vpsubsw",        { XM, Vex, EXx } },
10997   },
10998   {
10999     /* VEX_W_0FEA_P_2  */
11000     { "vpminsw",        { XM, Vex, EXx } },
11001   },
11002   {
11003     /* VEX_W_0FEB_P_2  */
11004     { "vpor",           { XM, Vex, EXx } },
11005   },
11006   {
11007     /* VEX_W_0FEC_P_2  */
11008     { "vpaddsb",        { XM, Vex, EXx } },
11009   },
11010   {
11011     /* VEX_W_0FED_P_2  */
11012     { "vpaddsw",        { XM, Vex, EXx } },
11013   },
11014   {
11015     /* VEX_W_0FEE_P_2  */
11016     { "vpmaxsw",        { XM, Vex, EXx } },
11017   },
11018   {
11019     /* VEX_W_0FEF_P_2  */
11020     { "vpxor",          { XM, Vex, EXx } },
11021   },
11022   {
11023     /* VEX_W_0FF0_P_3_M_0 */
11024     { "vlddqu",         { XM, M } },
11025   },
11026   {
11027     /* VEX_W_0FF1_P_2 */
11028     { "vpsllw",         { XM, Vex, EXxmm } },
11029   },
11030   {
11031     /* VEX_W_0FF2_P_2 */
11032     { "vpslld",         { XM, Vex, EXxmm } },
11033   },
11034   {
11035     /* VEX_W_0FF3_P_2 */
11036     { "vpsllq",         { XM, Vex, EXxmm } },
11037   },
11038   {
11039     /* VEX_W_0FF4_P_2 */
11040     { "vpmuludq",       { XM, Vex, EXx } },
11041   },
11042   {
11043     /* VEX_W_0FF5_P_2 */
11044     { "vpmaddwd",       { XM, Vex, EXx } },
11045   },
11046   {
11047     /* VEX_W_0FF6_P_2 */
11048     { "vpsadbw",        { XM, Vex, EXx } },
11049   },
11050   {
11051     /* VEX_W_0FF7_P_2 */
11052     { "vmaskmovdqu",    { XM, XS } },
11053   },
11054   {
11055     /* VEX_W_0FF8_P_2 */
11056     { "vpsubb",         { XM, Vex, EXx } },
11057   },
11058   {
11059     /* VEX_W_0FF9_P_2 */
11060     { "vpsubw",         { XM, Vex, EXx } },
11061   },
11062   {
11063     /* VEX_W_0FFA_P_2 */
11064     { "vpsubd",         { XM, Vex, EXx } },
11065   },
11066   {
11067     /* VEX_W_0FFB_P_2 */
11068     { "vpsubq",         { XM, Vex, EXx } },
11069   },
11070   {
11071     /* VEX_W_0FFC_P_2 */
11072     { "vpaddb",         { XM, Vex, EXx } },
11073   },
11074   {
11075     /* VEX_W_0FFD_P_2 */
11076     { "vpaddw",         { XM, Vex, EXx } },
11077   },
11078   {
11079     /* VEX_W_0FFE_P_2 */
11080     { "vpaddd",         { XM, Vex, EXx } },
11081   },
11082   {
11083     /* VEX_W_0F3800_P_2  */
11084     { "vpshufb",        { XM, Vex, EXx } },
11085   },
11086   {
11087     /* VEX_W_0F3801_P_2  */
11088     { "vphaddw",        { XM, Vex, EXx } },
11089   },
11090   {
11091     /* VEX_W_0F3802_P_2  */
11092     { "vphaddd",        { XM, Vex, EXx } },
11093   },
11094   {
11095     /* VEX_W_0F3803_P_2  */
11096     { "vphaddsw",       { XM, Vex, EXx } },
11097   },
11098   {
11099     /* VEX_W_0F3804_P_2  */
11100     { "vpmaddubsw",     { XM, Vex, EXx } },
11101   },
11102   {
11103     /* VEX_W_0F3805_P_2  */
11104     { "vphsubw",        { XM, Vex, EXx } },
11105   },
11106   {
11107     /* VEX_W_0F3806_P_2  */
11108     { "vphsubd",        { XM, Vex, EXx } },
11109   },
11110   {
11111     /* VEX_W_0F3807_P_2  */
11112     { "vphsubsw",       { XM, Vex, EXx } },
11113   },
11114   {
11115     /* VEX_W_0F3808_P_2  */
11116     { "vpsignb",        { XM, Vex, EXx } },
11117   },
11118   {
11119     /* VEX_W_0F3809_P_2  */
11120     { "vpsignw",        { XM, Vex, EXx } },
11121   },
11122   {
11123     /* VEX_W_0F380A_P_2  */
11124     { "vpsignd",        { XM, Vex, EXx } },
11125   },
11126   {
11127     /* VEX_W_0F380B_P_2  */
11128     { "vpmulhrsw",      { XM, Vex, EXx } },
11129   },
11130   {
11131     /* VEX_W_0F380C_P_2  */
11132     { "vpermilps",      { XM, Vex, EXx } },
11133   },
11134   {
11135     /* VEX_W_0F380D_P_2  */
11136     { "vpermilpd",      { XM, Vex, EXx } },
11137   },
11138   {
11139     /* VEX_W_0F380E_P_2  */
11140     { "vtestps",        { XM, EXx } },
11141   },
11142   {
11143     /* VEX_W_0F380F_P_2  */
11144     { "vtestpd",        { XM, EXx } },
11145   },
11146   {
11147     /* VEX_W_0F3816_P_2  */
11148     { "vpermps",        { XM, Vex, EXx } },
11149   },
11150   {
11151     /* VEX_W_0F3817_P_2 */
11152     { "vptest",         { XM, EXx } },
11153   },
11154   {
11155     /* VEX_W_0F3818_P_2 */
11156     { "vbroadcastss",   { XM, EXxmm_md } },
11157   },
11158   {
11159     /* VEX_W_0F3819_P_2 */
11160     { "vbroadcastsd",   { XM, EXxmm_mq } },
11161   },
11162   {
11163     /* VEX_W_0F381A_P_2_M_0 */
11164     { "vbroadcastf128", { XM, Mxmm } },
11165   },
11166   {
11167     /* VEX_W_0F381C_P_2 */
11168     { "vpabsb",         { XM, EXx } },
11169   },
11170   {
11171     /* VEX_W_0F381D_P_2 */
11172     { "vpabsw",         { XM, EXx } },
11173   },
11174   {
11175     /* VEX_W_0F381E_P_2 */
11176     { "vpabsd",         { XM, EXx } },
11177   },
11178   {
11179     /* VEX_W_0F3820_P_2 */
11180     { "vpmovsxbw",      { XM, EXxmmq } },
11181   },
11182   {
11183     /* VEX_W_0F3821_P_2 */
11184     { "vpmovsxbd",      { XM, EXxmmqd } },
11185   },
11186   {
11187     /* VEX_W_0F3822_P_2 */
11188     { "vpmovsxbq",      { XM, EXxmmdw } },
11189   },
11190   {
11191     /* VEX_W_0F3823_P_2 */
11192     { "vpmovsxwd",      { XM, EXxmmq } },
11193   },
11194   {
11195     /* VEX_W_0F3824_P_2 */
11196     { "vpmovsxwq",      { XM, EXxmmqd } },
11197   },
11198   {
11199     /* VEX_W_0F3825_P_2 */
11200     { "vpmovsxdq",      { XM, EXxmmq } },
11201   },
11202   {
11203     /* VEX_W_0F3828_P_2 */
11204     { "vpmuldq",        { XM, Vex, EXx } },
11205   },
11206   {
11207     /* VEX_W_0F3829_P_2 */
11208     { "vpcmpeqq",       { XM, Vex, EXx } },
11209   },
11210   {
11211     /* VEX_W_0F382A_P_2_M_0 */
11212     { "vmovntdqa",      { XM, Mx } },
11213   },
11214   {
11215     /* VEX_W_0F382B_P_2 */
11216     { "vpackusdw",      { XM, Vex, EXx } },
11217   },
11218   {
11219     /* VEX_W_0F382C_P_2_M_0 */
11220     { "vmaskmovps",     { XM, Vex, Mx } },
11221   },
11222   {
11223     /* VEX_W_0F382D_P_2_M_0 */
11224     { "vmaskmovpd",     { XM, Vex, Mx } },
11225   },
11226   {
11227     /* VEX_W_0F382E_P_2_M_0 */
11228     { "vmaskmovps",     { Mx, Vex, XM } },
11229   },
11230   {
11231     /* VEX_W_0F382F_P_2_M_0 */
11232     { "vmaskmovpd",     { Mx, Vex, XM } },
11233   },
11234   {
11235     /* VEX_W_0F3830_P_2 */
11236     { "vpmovzxbw",      { XM, EXxmmq } },
11237   },
11238   {
11239     /* VEX_W_0F3831_P_2 */
11240     { "vpmovzxbd",      { XM, EXxmmqd } },
11241   },
11242   {
11243     /* VEX_W_0F3832_P_2 */
11244     { "vpmovzxbq",      { XM, EXxmmdw } },
11245   },
11246   {
11247     /* VEX_W_0F3833_P_2 */
11248     { "vpmovzxwd",      { XM, EXxmmq } },
11249   },
11250   {
11251     /* VEX_W_0F3834_P_2 */
11252     { "vpmovzxwq",      { XM, EXxmmqd } },
11253   },
11254   {
11255     /* VEX_W_0F3835_P_2 */
11256     { "vpmovzxdq",      { XM, EXxmmq } },
11257   },
11258   {
11259     /* VEX_W_0F3836_P_2  */
11260     { "vpermd",         { XM, Vex, EXx } },
11261   },
11262   {
11263     /* VEX_W_0F3837_P_2 */
11264     { "vpcmpgtq",       { XM, Vex, EXx } },
11265   },
11266   {
11267     /* VEX_W_0F3838_P_2 */
11268     { "vpminsb",        { XM, Vex, EXx } },
11269   },
11270   {
11271     /* VEX_W_0F3839_P_2 */
11272     { "vpminsd",        { XM, Vex, EXx } },
11273   },
11274   {
11275     /* VEX_W_0F383A_P_2 */
11276     { "vpminuw",        { XM, Vex, EXx } },
11277   },
11278   {
11279     /* VEX_W_0F383B_P_2 */
11280     { "vpminud",        { XM, Vex, EXx } },
11281   },
11282   {
11283     /* VEX_W_0F383C_P_2 */
11284     { "vpmaxsb",        { XM, Vex, EXx } },
11285   },
11286   {
11287     /* VEX_W_0F383D_P_2 */
11288     { "vpmaxsd",        { XM, Vex, EXx } },
11289   },
11290   {
11291     /* VEX_W_0F383E_P_2 */
11292     { "vpmaxuw",        { XM, Vex, EXx } },
11293   },
11294   {
11295     /* VEX_W_0F383F_P_2 */
11296     { "vpmaxud",        { XM, Vex, EXx } },
11297   },
11298   {
11299     /* VEX_W_0F3840_P_2 */
11300     { "vpmulld",        { XM, Vex, EXx } },
11301   },
11302   {
11303     /* VEX_W_0F3841_P_2 */
11304     { "vphminposuw",    { XM, EXx } },
11305   },
11306   {
11307     /* VEX_W_0F3846_P_2 */
11308     { "vpsravd",        { XM, Vex, EXx } },
11309   },
11310   {
11311     /* VEX_W_0F3858_P_2 */
11312     { "vpbroadcastd", { XM, EXxmm_md } },
11313   },
11314   {
11315     /* VEX_W_0F3859_P_2 */
11316     { "vpbroadcastq",   { XM, EXxmm_mq } },
11317   },
11318   {
11319     /* VEX_W_0F385A_P_2_M_0 */
11320     { "vbroadcasti128", { XM, Mxmm } },
11321   },
11322   {
11323     /* VEX_W_0F3878_P_2 */
11324     { "vpbroadcastb",   { XM, EXxmm_mb } },
11325   },
11326   {
11327     /* VEX_W_0F3879_P_2 */
11328     { "vpbroadcastw",   { XM, EXxmm_mw } },
11329   },
11330   {
11331     /* VEX_W_0F38DB_P_2 */
11332     { "vaesimc",        { XM, EXx } },
11333   },
11334   {
11335     /* VEX_W_0F38DC_P_2 */
11336     { "vaesenc",        { XM, Vex128, EXx } },
11337   },
11338   {
11339     /* VEX_W_0F38DD_P_2 */
11340     { "vaesenclast",    { XM, Vex128, EXx } },
11341   },
11342   {
11343     /* VEX_W_0F38DE_P_2 */
11344     { "vaesdec",        { XM, Vex128, EXx } },
11345   },
11346   {
11347     /* VEX_W_0F38DF_P_2 */
11348     { "vaesdeclast",    { XM, Vex128, EXx } },
11349   },
11350   {
11351     /* VEX_W_0F3A00_P_2 */
11352     { Bad_Opcode },
11353     { "vpermq",         { XM, EXx, Ib } },
11354   },
11355   {
11356     /* VEX_W_0F3A01_P_2 */
11357     { Bad_Opcode },
11358     { "vpermpd",        { XM, EXx, Ib } },
11359   },
11360   {
11361     /* VEX_W_0F3A02_P_2 */
11362     { "vpblendd",       { XM, Vex, EXx, Ib } },
11363   },
11364   {
11365     /* VEX_W_0F3A04_P_2 */
11366     { "vpermilps",      { XM, EXx, Ib } },
11367   },
11368   {
11369     /* VEX_W_0F3A05_P_2 */
11370     { "vpermilpd",      { XM, EXx, Ib } },
11371   },
11372   {
11373     /* VEX_W_0F3A06_P_2 */
11374     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
11375   },
11376   {
11377     /* VEX_W_0F3A08_P_2 */
11378     { "vroundps",       { XM, EXx, Ib } },
11379   },
11380   {
11381     /* VEX_W_0F3A09_P_2 */
11382     { "vroundpd",       { XM, EXx, Ib } },
11383   },
11384   {
11385     /* VEX_W_0F3A0A_P_2 */
11386     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
11387   },
11388   {
11389     /* VEX_W_0F3A0B_P_2 */
11390     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
11391   },
11392   {
11393     /* VEX_W_0F3A0C_P_2 */
11394     { "vblendps",       { XM, Vex, EXx, Ib } },
11395   },
11396   {
11397     /* VEX_W_0F3A0D_P_2 */
11398     { "vblendpd",       { XM, Vex, EXx, Ib } },
11399   },
11400   {
11401     /* VEX_W_0F3A0E_P_2 */
11402     { "vpblendw",       { XM, Vex, EXx, Ib } },
11403   },
11404   {
11405     /* VEX_W_0F3A0F_P_2 */
11406     { "vpalignr",       { XM, Vex, EXx, Ib } },
11407   },
11408   {
11409     /* VEX_W_0F3A14_P_2 */
11410     { "vpextrb",        { Edqb, XM, Ib } },
11411   },
11412   {
11413     /* VEX_W_0F3A15_P_2 */
11414     { "vpextrw",        { Edqw, XM, Ib } },
11415   },
11416   {
11417     /* VEX_W_0F3A18_P_2 */
11418     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
11419   },
11420   {
11421     /* VEX_W_0F3A19_P_2 */
11422     { "vextractf128",   { EXxmm, XM, Ib } },
11423   },
11424   {
11425     /* VEX_W_0F3A20_P_2 */
11426     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
11427   },
11428   {
11429     /* VEX_W_0F3A21_P_2 */
11430     { "vinsertps",      { XM, Vex128, EXd, Ib } },
11431   },
11432   {
11433     /* VEX_W_0F3A30_P_2_LEN_0 */
11434     { "kshiftrb",       { MaskG, MaskR, Ib } },
11435     { "kshiftrw",       { MaskG, MaskR, Ib } },
11436   },
11437   {
11438     /* VEX_W_0F3A31_P_2_LEN_0 */
11439     { "kshiftrd",       { MaskG, MaskR, Ib } },
11440     { "kshiftrq",       { MaskG, MaskR, Ib } },
11441   },
11442   {
11443     /* VEX_W_0F3A32_P_2_LEN_0 */
11444     { "kshiftlb",       { MaskG, MaskR, Ib } },
11445     { "kshiftlw",       { MaskG, MaskR, Ib } },
11446   },
11447   {
11448     /* VEX_W_0F3A33_P_2_LEN_0 */
11449     { "kshiftld",       { MaskG, MaskR, Ib } },
11450     { "kshiftlq",       { MaskG, MaskR, Ib } },
11451   },
11452   {
11453     /* VEX_W_0F3A38_P_2 */
11454     { "vinserti128",    { XM, Vex256, EXxmm, Ib } },
11455   },
11456   {
11457     /* VEX_W_0F3A39_P_2 */
11458     { "vextracti128",   { EXxmm, XM, Ib } },
11459   },
11460   {
11461     /* VEX_W_0F3A40_P_2 */
11462     { "vdpps",          { XM, Vex, EXx, Ib } },
11463   },
11464   {
11465     /* VEX_W_0F3A41_P_2 */
11466     { "vdppd",          { XM, Vex128, EXx, Ib } },
11467   },
11468   {
11469     /* VEX_W_0F3A42_P_2 */
11470     { "vmpsadbw",       { XM, Vex, EXx, Ib } },
11471   },
11472   {
11473     /* VEX_W_0F3A44_P_2 */
11474     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
11475   },
11476   {
11477     /* VEX_W_0F3A46_P_2 */
11478     { "vperm2i128",     { XM, Vex256, EXx, Ib } },
11479   },
11480   {
11481     /* VEX_W_0F3A48_P_2 */
11482     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11483     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11484   },
11485   {
11486     /* VEX_W_0F3A49_P_2 */
11487     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11488     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11489   },
11490   {
11491     /* VEX_W_0F3A4A_P_2 */
11492     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
11493   },
11494   {
11495     /* VEX_W_0F3A4B_P_2 */
11496     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
11497   },
11498   {
11499     /* VEX_W_0F3A4C_P_2 */
11500     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 } },
11501   },
11502   {
11503     /* VEX_W_0F3A60_P_2 */
11504     { "vpcmpestrm",     { XM, EXx, Ib } },
11505   },
11506   {
11507     /* VEX_W_0F3A61_P_2 */
11508     { "vpcmpestri",     { XM, EXx, Ib } },
11509   },
11510   {
11511     /* VEX_W_0F3A62_P_2 */
11512     { "vpcmpistrm",     { XM, EXx, Ib } },
11513   },
11514   {
11515     /* VEX_W_0F3A63_P_2 */
11516     { "vpcmpistri",     { XM, EXx, Ib } },
11517   },
11518   {
11519     /* VEX_W_0F3ADF_P_2 */
11520     { "vaeskeygenassist", { XM, EXx, Ib } },
11521   },
11522 #define NEED_VEX_W_TABLE
11523 #include "i386-dis-evex.h"
11524 #undef NEED_VEX_W_TABLE
11525 };
11526
11527 static const struct dis386 mod_table[][2] = {
11528   {
11529     /* MOD_8D */
11530     { "leaS",           { Gv, M } },
11531   },
11532   {
11533     /* MOD_C6_REG_7 */
11534     { Bad_Opcode },
11535     { RM_TABLE (RM_C6_REG_7) },
11536   },
11537   {
11538     /* MOD_C7_REG_7 */
11539     { Bad_Opcode },
11540     { RM_TABLE (RM_C7_REG_7) },
11541   },
11542   {
11543     /* MOD_FF_REG_3 */
11544     { "Jcall{T|}", { indirEp } },
11545   },
11546   {
11547     /* MOD_FF_REG_5 */
11548     { "Jjmp{T|}", { indirEp } },
11549   },
11550   {
11551     /* MOD_0F01_REG_0 */
11552     { X86_64_TABLE (X86_64_0F01_REG_0) },
11553     { RM_TABLE (RM_0F01_REG_0) },
11554   },
11555   {
11556     /* MOD_0F01_REG_1 */
11557     { X86_64_TABLE (X86_64_0F01_REG_1) },
11558     { RM_TABLE (RM_0F01_REG_1) },
11559   },
11560   {
11561     /* MOD_0F01_REG_2 */
11562     { X86_64_TABLE (X86_64_0F01_REG_2) },
11563     { RM_TABLE (RM_0F01_REG_2) },
11564   },
11565   {
11566     /* MOD_0F01_REG_3 */
11567     { X86_64_TABLE (X86_64_0F01_REG_3) },
11568     { RM_TABLE (RM_0F01_REG_3) },
11569   },
11570   {
11571     /* MOD_0F01_REG_7 */
11572     { "invlpg",         { Mb } },
11573     { RM_TABLE (RM_0F01_REG_7) },
11574   },
11575   {
11576     /* MOD_0F12_PREFIX_0 */
11577     { "movlps",         { XM, EXq } },
11578     { "movhlps",        { XM, EXq } },
11579   },
11580   {
11581     /* MOD_0F13 */
11582     { "movlpX",         { EXq, XM } },
11583   },
11584   {
11585     /* MOD_0F16_PREFIX_0 */
11586     { "movhps",         { XM, EXq } },
11587     { "movlhps",        { XM, EXq } },
11588   },
11589   {
11590     /* MOD_0F17 */
11591     { "movhpX",         { EXq, XM } },
11592   },
11593   {
11594     /* MOD_0F18_REG_0 */
11595     { "prefetchnta",    { Mb } },
11596   },
11597   {
11598     /* MOD_0F18_REG_1 */
11599     { "prefetcht0",     { Mb } },
11600   },
11601   {
11602     /* MOD_0F18_REG_2 */
11603     { "prefetcht1",     { Mb } },
11604   },
11605   {
11606     /* MOD_0F18_REG_3 */
11607     { "prefetcht2",     { Mb } },
11608   },
11609   {
11610     /* MOD_0F18_REG_4 */
11611     { "nop/reserved",   { Mb } },
11612   },
11613   {
11614     /* MOD_0F18_REG_5 */
11615     { "nop/reserved",   { Mb } },
11616   },
11617   {
11618     /* MOD_0F18_REG_6 */
11619     { "nop/reserved",   { Mb } },
11620   },
11621   {
11622     /* MOD_0F18_REG_7 */
11623     { "nop/reserved",   { Mb } },
11624   },
11625   {
11626     /* MOD_0F1A_PREFIX_0 */
11627     { "bndldx",         { Gbnd, Ev_bnd } },
11628     { "nopQ",           { Ev } },
11629   },
11630   {
11631     /* MOD_0F1B_PREFIX_0 */
11632     { "bndstx",         { Ev_bnd, Gbnd } },
11633     { "nopQ",           { Ev } },
11634   },
11635   {
11636     /* MOD_0F1B_PREFIX_1 */
11637     { "bndmk",          { Gbnd, Ev_bnd } },
11638     { "nopQ",           { Ev } },
11639   },
11640   {
11641     /* MOD_0F24 */
11642     { Bad_Opcode },
11643     { "movL",           { Rd, Td } },
11644   },
11645   {
11646     /* MOD_0F26 */
11647     { Bad_Opcode },
11648     { "movL",           { Td, Rd } },
11649   },
11650   {
11651     /* MOD_0F2B_PREFIX_0 */
11652     {"movntps",         { Mx, XM } },
11653   },
11654   {
11655     /* MOD_0F2B_PREFIX_1 */
11656     {"movntss",         { Md, XM } },
11657   },
11658   {
11659     /* MOD_0F2B_PREFIX_2 */
11660     {"movntpd",         { Mx, XM } },
11661   },
11662   {
11663     /* MOD_0F2B_PREFIX_3 */
11664     {"movntsd",         { Mq, XM } },
11665   },
11666   {
11667     /* MOD_0F51 */
11668     { Bad_Opcode },
11669     { "movmskpX",       { Gdq, XS } },
11670   },
11671   {
11672     /* MOD_0F71_REG_2 */
11673     { Bad_Opcode },
11674     { "psrlw",          { MS, Ib } },
11675   },
11676   {
11677     /* MOD_0F71_REG_4 */
11678     { Bad_Opcode },
11679     { "psraw",          { MS, Ib } },
11680   },
11681   {
11682     /* MOD_0F71_REG_6 */
11683     { Bad_Opcode },
11684     { "psllw",          { MS, Ib } },
11685   },
11686   {
11687     /* MOD_0F72_REG_2 */
11688     { Bad_Opcode },
11689     { "psrld",          { MS, Ib } },
11690   },
11691   {
11692     /* MOD_0F72_REG_4 */
11693     { Bad_Opcode },
11694     { "psrad",          { MS, Ib } },
11695   },
11696   {
11697     /* MOD_0F72_REG_6 */
11698     { Bad_Opcode },
11699     { "pslld",          { MS, Ib } },
11700   },
11701   {
11702     /* MOD_0F73_REG_2 */
11703     { Bad_Opcode },
11704     { "psrlq",          { MS, Ib } },
11705   },
11706   {
11707     /* MOD_0F73_REG_3 */
11708     { Bad_Opcode },
11709     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11710   },
11711   {
11712     /* MOD_0F73_REG_6 */
11713     { Bad_Opcode },
11714     { "psllq",          { MS, Ib } },
11715   },
11716   {
11717     /* MOD_0F73_REG_7 */
11718     { Bad_Opcode },
11719     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11720   },
11721   {
11722     /* MOD_0FAE_REG_0 */
11723     { "fxsave",         { FXSAVE } },
11724     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11725   },
11726   {
11727     /* MOD_0FAE_REG_1 */
11728     { "fxrstor",        { FXSAVE } },
11729     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11730   },
11731   {
11732     /* MOD_0FAE_REG_2 */
11733     { "ldmxcsr",        { Md } },
11734     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11735   },
11736   {
11737     /* MOD_0FAE_REG_3 */
11738     { "stmxcsr",        { Md } },
11739     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11740   },
11741   {
11742     /* MOD_0FAE_REG_4 */
11743     { "xsave",          { FXSAVE } },
11744   },
11745   {
11746     /* MOD_0FAE_REG_5 */
11747     { "xrstor",         { FXSAVE } },
11748     { RM_TABLE (RM_0FAE_REG_5) },
11749   },
11750   {
11751     /* MOD_0FAE_REG_6 */
11752     { "xsaveopt",       { FXSAVE } },
11753     { RM_TABLE (RM_0FAE_REG_6) },
11754   },
11755   {
11756     /* MOD_0FAE_REG_7 */
11757     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11758     { RM_TABLE (RM_0FAE_REG_7) },
11759   },
11760   {
11761     /* MOD_0FB2 */
11762     { "lssS",           { Gv, Mp } },
11763   },
11764   {
11765     /* MOD_0FB4 */
11766     { "lfsS",           { Gv, Mp } },
11767   },
11768   {
11769     /* MOD_0FB5 */
11770     { "lgsS",           { Gv, Mp } },
11771   },
11772   {
11773     /* MOD_0FC7_REG_3 */
11774     { "xrstors",                { FXSAVE } },
11775   },
11776   {
11777     /* MOD_0FC7_REG_4 */
11778     { "xsavec",         { FXSAVE } },
11779   },
11780   {
11781     /* MOD_0FC7_REG_5 */
11782     { "xsaves",         { FXSAVE } },
11783   },
11784   {
11785     /* MOD_0FC7_REG_6 */
11786     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11787     { "rdrand",         { Ev } },
11788   },
11789   {
11790     /* MOD_0FC7_REG_7 */
11791     { "vmptrst",        { Mq } },
11792     { "rdseed",         { Ev } },
11793   },
11794   {
11795     /* MOD_0FD7 */
11796     { Bad_Opcode },
11797     { "pmovmskb",       { Gdq, MS } },
11798   },
11799   {
11800     /* MOD_0FE7_PREFIX_2 */
11801     { "movntdq",        { Mx, XM } },
11802   },
11803   {
11804     /* MOD_0FF0_PREFIX_3 */
11805     { "lddqu",          { XM, M } },
11806   },
11807   {
11808     /* MOD_0F382A_PREFIX_2 */
11809     { "movntdqa",       { XM, Mx } },
11810   },
11811   {
11812     /* MOD_62_32BIT */
11813     { "bound{S|}",      { Gv, Ma } },
11814     { EVEX_TABLE (EVEX_0F) },
11815   },
11816   {
11817     /* MOD_C4_32BIT */
11818     { "lesS",           { Gv, Mp } },
11819     { VEX_C4_TABLE (VEX_0F) },
11820   },
11821   {
11822     /* MOD_C5_32BIT */
11823     { "ldsS",           { Gv, Mp } },
11824     { VEX_C5_TABLE (VEX_0F) },
11825   },
11826   {
11827     /* MOD_VEX_0F12_PREFIX_0 */
11828     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11829     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11830   },
11831   {
11832     /* MOD_VEX_0F13 */
11833     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11834   },
11835   {
11836     /* MOD_VEX_0F16_PREFIX_0 */
11837     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11838     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11839   },
11840   {
11841     /* MOD_VEX_0F17 */
11842     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11843   },
11844   {
11845     /* MOD_VEX_0F2B */
11846     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11847   },
11848   {
11849     /* MOD_VEX_0F50 */
11850     { Bad_Opcode },
11851     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11852   },
11853   {
11854     /* MOD_VEX_0F71_REG_2 */
11855     { Bad_Opcode },
11856     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11857   },
11858   {
11859     /* MOD_VEX_0F71_REG_4 */
11860     { Bad_Opcode },
11861     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11862   },
11863   {
11864     /* MOD_VEX_0F71_REG_6 */
11865     { Bad_Opcode },
11866     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11867   },
11868   {
11869     /* MOD_VEX_0F72_REG_2 */
11870     { Bad_Opcode },
11871     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11872   },
11873   {
11874     /* MOD_VEX_0F72_REG_4 */
11875     { Bad_Opcode },
11876     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11877   },
11878   {
11879     /* MOD_VEX_0F72_REG_6 */
11880     { Bad_Opcode },
11881     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11882   },
11883   {
11884     /* MOD_VEX_0F73_REG_2 */
11885     { Bad_Opcode },
11886     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11887   },
11888   {
11889     /* MOD_VEX_0F73_REG_3 */
11890     { Bad_Opcode },
11891     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11892   },
11893   {
11894     /* MOD_VEX_0F73_REG_6 */
11895     { Bad_Opcode },
11896     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11897   },
11898   {
11899     /* MOD_VEX_0F73_REG_7 */
11900     { Bad_Opcode },
11901     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11902   },
11903   {
11904     /* MOD_VEX_0FAE_REG_2 */
11905     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11906   },
11907   {
11908     /* MOD_VEX_0FAE_REG_3 */
11909     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11910   },
11911   {
11912     /* MOD_VEX_0FD7_PREFIX_2 */
11913     { Bad_Opcode },
11914     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11915   },
11916   {
11917     /* MOD_VEX_0FE7_PREFIX_2 */
11918     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11919   },
11920   {
11921     /* MOD_VEX_0FF0_PREFIX_3 */
11922     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11923   },
11924   {
11925     /* MOD_VEX_0F381A_PREFIX_2 */
11926     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11927   },
11928   {
11929     /* MOD_VEX_0F382A_PREFIX_2 */
11930     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11931   },
11932   {
11933     /* MOD_VEX_0F382C_PREFIX_2 */
11934     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11935   },
11936   {
11937     /* MOD_VEX_0F382D_PREFIX_2 */
11938     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11939   },
11940   {
11941     /* MOD_VEX_0F382E_PREFIX_2 */
11942     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11943   },
11944   {
11945     /* MOD_VEX_0F382F_PREFIX_2 */
11946     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11947   },
11948   {
11949     /* MOD_VEX_0F385A_PREFIX_2 */
11950     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11951   },
11952   {
11953     /* MOD_VEX_0F388C_PREFIX_2 */
11954     { "vpmaskmov%LW",   { XM, Vex, Mx } },
11955   },
11956   {
11957     /* MOD_VEX_0F388E_PREFIX_2 */
11958     { "vpmaskmov%LW",   { Mx, Vex, XM } },
11959   },
11960 #define NEED_MOD_TABLE
11961 #include "i386-dis-evex.h"
11962 #undef NEED_MOD_TABLE
11963 };
11964
11965 static const struct dis386 rm_table[][8] = {
11966   {
11967     /* RM_C6_REG_7 */
11968     { "xabort",         { Skip_MODRM, Ib } },
11969   },
11970   {
11971     /* RM_C7_REG_7 */
11972     { "xbeginT",        { Skip_MODRM, Jv } },
11973   },
11974   {
11975     /* RM_0F01_REG_0 */
11976     { Bad_Opcode },
11977     { "vmcall",         { Skip_MODRM } },
11978     { "vmlaunch",       { Skip_MODRM } },
11979     { "vmresume",       { Skip_MODRM } },
11980     { "vmxoff",         { Skip_MODRM } },
11981   },
11982   {
11983     /* RM_0F01_REG_1 */
11984     { "monitor",        { { OP_Monitor, 0 } } },
11985     { "mwait",          { { OP_Mwait, 0 } } },
11986     { "clac",           { Skip_MODRM } },
11987     { "stac",           { Skip_MODRM } },
11988     { Bad_Opcode },
11989     { Bad_Opcode },
11990     { Bad_Opcode },
11991     { "encls",          { Skip_MODRM } },
11992   },
11993   {
11994     /* RM_0F01_REG_2 */
11995     { "xgetbv",         { Skip_MODRM } },
11996     { "xsetbv",         { Skip_MODRM } },
11997     { Bad_Opcode },
11998     { Bad_Opcode },
11999     { "vmfunc",         { Skip_MODRM } },
12000     { "xend",           { Skip_MODRM } },
12001     { "xtest",          { Skip_MODRM } },
12002     { "enclu",          { Skip_MODRM } },
12003   },
12004   {
12005     /* RM_0F01_REG_3 */
12006     { "vmrun",          { Skip_MODRM } },
12007     { "vmmcall",        { Skip_MODRM } },
12008     { "vmload",         { Skip_MODRM } },
12009     { "vmsave",         { Skip_MODRM } },
12010     { "stgi",           { Skip_MODRM } },
12011     { "clgi",           { Skip_MODRM } },
12012     { "skinit",         { Skip_MODRM } },
12013     { "invlpga",        { Skip_MODRM } },
12014   },
12015   {
12016     /* RM_0F01_REG_7 */
12017     { "swapgs",         { Skip_MODRM } },
12018     { "rdtscp",         { Skip_MODRM } },
12019   },
12020   {
12021     /* RM_0FAE_REG_5 */
12022     { "lfence",         { Skip_MODRM } },
12023   },
12024   {
12025     /* RM_0FAE_REG_6 */
12026     { "mfence",         { Skip_MODRM } },
12027   },
12028   {
12029     /* RM_0FAE_REG_7 */
12030     { "sfence",         { Skip_MODRM } },
12031   },
12032 };
12033
12034 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12035
12036 /* We use the high bit to indicate different name for the same
12037    prefix.  */
12038 #define REP_PREFIX      (0xf3 | 0x100)
12039 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12040 #define XRELEASE_PREFIX (0xf3 | 0x400)
12041 #define BND_PREFIX      (0xf2 | 0x400)
12042
12043 static int
12044 ckprefix (void)
12045 {
12046   int newrex, i, length;
12047   rex = 0;
12048   rex_ignored = 0;
12049   prefixes = 0;
12050   used_prefixes = 0;
12051   rex_used = 0;
12052   last_lock_prefix = -1;
12053   last_repz_prefix = -1;
12054   last_repnz_prefix = -1;
12055   last_data_prefix = -1;
12056   last_addr_prefix = -1;
12057   last_rex_prefix = -1;
12058   last_seg_prefix = -1;
12059   fwait_prefix = -1;
12060   active_seg_prefix = 0;
12061   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12062     all_prefixes[i] = 0;
12063   i = 0;
12064   length = 0;
12065   /* The maximum instruction length is 15bytes.  */
12066   while (length < MAX_CODE_LENGTH - 1)
12067     {
12068       FETCH_DATA (the_info, codep + 1);
12069       newrex = 0;
12070       switch (*codep)
12071         {
12072         /* REX prefixes family.  */
12073         case 0x40:
12074         case 0x41:
12075         case 0x42:
12076         case 0x43:
12077         case 0x44:
12078         case 0x45:
12079         case 0x46:
12080         case 0x47:
12081         case 0x48:
12082         case 0x49:
12083         case 0x4a:
12084         case 0x4b:
12085         case 0x4c:
12086         case 0x4d:
12087         case 0x4e:
12088         case 0x4f:
12089           if (address_mode == mode_64bit)
12090             newrex = *codep;
12091           else
12092             return 1;
12093           last_rex_prefix = i;
12094           break;
12095         case 0xf3:
12096           prefixes |= PREFIX_REPZ;
12097           last_repz_prefix = i;
12098           break;
12099         case 0xf2:
12100           prefixes |= PREFIX_REPNZ;
12101           last_repnz_prefix = i;
12102           break;
12103         case 0xf0:
12104           prefixes |= PREFIX_LOCK;
12105           last_lock_prefix = i;
12106           break;
12107         case 0x2e:
12108           prefixes |= PREFIX_CS;
12109           last_seg_prefix = i;
12110           active_seg_prefix = PREFIX_CS;
12111           break;
12112         case 0x36:
12113           prefixes |= PREFIX_SS;
12114           last_seg_prefix = i;
12115           active_seg_prefix = PREFIX_SS;
12116           break;
12117         case 0x3e:
12118           prefixes |= PREFIX_DS;
12119           last_seg_prefix = i;
12120           active_seg_prefix = PREFIX_DS;
12121           break;
12122         case 0x26:
12123           prefixes |= PREFIX_ES;
12124           last_seg_prefix = i;
12125           active_seg_prefix = PREFIX_ES;
12126           break;
12127         case 0x64:
12128           prefixes |= PREFIX_FS;
12129           last_seg_prefix = i;
12130           active_seg_prefix = PREFIX_FS;
12131           break;
12132         case 0x65:
12133           prefixes |= PREFIX_GS;
12134           last_seg_prefix = i;
12135           active_seg_prefix = PREFIX_GS;
12136           break;
12137         case 0x66:
12138           prefixes |= PREFIX_DATA;
12139           last_data_prefix = i;
12140           break;
12141         case 0x67:
12142           prefixes |= PREFIX_ADDR;
12143           last_addr_prefix = i;
12144           break;
12145         case FWAIT_OPCODE:
12146           /* fwait is really an instruction.  If there are prefixes
12147              before the fwait, they belong to the fwait, *not* to the
12148              following instruction.  */
12149           fwait_prefix = i;
12150           if (prefixes || rex)
12151             {
12152               prefixes |= PREFIX_FWAIT;
12153               codep++;
12154               /* This ensures that the previous REX prefixes are noticed
12155                  as unused prefixes, as in the return case below.  */
12156               rex_used = rex;
12157               return 1;
12158             }
12159           prefixes = PREFIX_FWAIT;
12160           break;
12161         default:
12162           return 1;
12163         }
12164       /* Rex is ignored when followed by another prefix.  */
12165       if (rex)
12166         {
12167           rex_used = rex;
12168           return 1;
12169         }
12170       if (*codep != FWAIT_OPCODE)
12171         all_prefixes[i++] = *codep;
12172       rex = newrex;
12173       codep++;
12174       length++;
12175     }
12176   return 0;
12177 }
12178
12179 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12180    prefix byte.  */
12181
12182 static const char *
12183 prefix_name (int pref, int sizeflag)
12184 {
12185   static const char *rexes [16] =
12186     {
12187       "rex",            /* 0x40 */
12188       "rex.B",          /* 0x41 */
12189       "rex.X",          /* 0x42 */
12190       "rex.XB",         /* 0x43 */
12191       "rex.R",          /* 0x44 */
12192       "rex.RB",         /* 0x45 */
12193       "rex.RX",         /* 0x46 */
12194       "rex.RXB",        /* 0x47 */
12195       "rex.W",          /* 0x48 */
12196       "rex.WB",         /* 0x49 */
12197       "rex.WX",         /* 0x4a */
12198       "rex.WXB",        /* 0x4b */
12199       "rex.WR",         /* 0x4c */
12200       "rex.WRB",        /* 0x4d */
12201       "rex.WRX",        /* 0x4e */
12202       "rex.WRXB",       /* 0x4f */
12203     };
12204
12205   switch (pref)
12206     {
12207     /* REX prefixes family.  */
12208     case 0x40:
12209     case 0x41:
12210     case 0x42:
12211     case 0x43:
12212     case 0x44:
12213     case 0x45:
12214     case 0x46:
12215     case 0x47:
12216     case 0x48:
12217     case 0x49:
12218     case 0x4a:
12219     case 0x4b:
12220     case 0x4c:
12221     case 0x4d:
12222     case 0x4e:
12223     case 0x4f:
12224       return rexes [pref - 0x40];
12225     case 0xf3:
12226       return "repz";
12227     case 0xf2:
12228       return "repnz";
12229     case 0xf0:
12230       return "lock";
12231     case 0x2e:
12232       return "cs";
12233     case 0x36:
12234       return "ss";
12235     case 0x3e:
12236       return "ds";
12237     case 0x26:
12238       return "es";
12239     case 0x64:
12240       return "fs";
12241     case 0x65:
12242       return "gs";
12243     case 0x66:
12244       return (sizeflag & DFLAG) ? "data16" : "data32";
12245     case 0x67:
12246       if (address_mode == mode_64bit)
12247         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12248       else
12249         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12250     case FWAIT_OPCODE:
12251       return "fwait";
12252     case REP_PREFIX:
12253       return "rep";
12254     case XACQUIRE_PREFIX:
12255       return "xacquire";
12256     case XRELEASE_PREFIX:
12257       return "xrelease";
12258     case BND_PREFIX:
12259       return "bnd";
12260     default:
12261       return NULL;
12262     }
12263 }
12264
12265 static char op_out[MAX_OPERANDS][100];
12266 static int op_ad, op_index[MAX_OPERANDS];
12267 static int two_source_ops;
12268 static bfd_vma op_address[MAX_OPERANDS];
12269 static bfd_vma op_riprel[MAX_OPERANDS];
12270 static bfd_vma start_pc;
12271
12272 /*
12273  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12274  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12275  *   section of the "Virtual 8086 Mode" chapter.)
12276  * 'pc' should be the address of this instruction, it will
12277  *   be used to print the target address if this is a relative jump or call
12278  * The function returns the length of this instruction in bytes.
12279  */
12280
12281 static char intel_syntax;
12282 static char intel_mnemonic = !SYSV386_COMPAT;
12283 static char open_char;
12284 static char close_char;
12285 static char separator_char;
12286 static char scale_char;
12287
12288 /* Here for backwards compatibility.  When gdb stops using
12289    print_insn_i386_att and print_insn_i386_intel these functions can
12290    disappear, and print_insn_i386 be merged into print_insn.  */
12291 int
12292 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12293 {
12294   intel_syntax = 0;
12295
12296   return print_insn (pc, info);
12297 }
12298
12299 int
12300 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12301 {
12302   intel_syntax = 1;
12303
12304   return print_insn (pc, info);
12305 }
12306
12307 int
12308 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12309 {
12310   intel_syntax = -1;
12311
12312   return print_insn (pc, info);
12313 }
12314
12315 void
12316 print_i386_disassembler_options (FILE *stream)
12317 {
12318   fprintf (stream, _("\n\
12319 The following i386/x86-64 specific disassembler options are supported for use\n\
12320 with the -M switch (multiple options should be separated by commas):\n"));
12321
12322   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12323   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12324   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12325   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12326   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12327   fprintf (stream, _("  att-mnemonic\n"
12328                      "              Display instruction in AT&T mnemonic\n"));
12329   fprintf (stream, _("  intel-mnemonic\n"
12330                      "              Display instruction in Intel mnemonic\n"));
12331   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12332   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12333   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12334   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12335   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12336   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12337 }
12338
12339 /* Bad opcode.  */
12340 static const struct dis386 bad_opcode = { "(bad)", { XX } };
12341
12342 /* Get a pointer to struct dis386 with a valid name.  */
12343
12344 static const struct dis386 *
12345 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12346 {
12347   int vindex, vex_table_index;
12348
12349   if (dp->name != NULL)
12350     return dp;
12351
12352   switch (dp->op[0].bytemode)
12353     {
12354     case USE_REG_TABLE:
12355       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12356       break;
12357
12358     case USE_MOD_TABLE:
12359       vindex = modrm.mod == 0x3 ? 1 : 0;
12360       dp = &mod_table[dp->op[1].bytemode][vindex];
12361       break;
12362
12363     case USE_RM_TABLE:
12364       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12365       break;
12366
12367     case USE_PREFIX_TABLE:
12368       if (need_vex)
12369         {
12370           /* The prefix in VEX is implicit.  */
12371           switch (vex.prefix)
12372             {
12373             case 0:
12374               vindex = 0;
12375               break;
12376             case REPE_PREFIX_OPCODE:
12377               vindex = 1;
12378               break;
12379             case DATA_PREFIX_OPCODE:
12380               vindex = 2;
12381               break;
12382             case REPNE_PREFIX_OPCODE:
12383               vindex = 3;
12384               break;
12385             default:
12386               abort ();
12387               break;
12388             }
12389         }
12390       else
12391         {
12392           int last_prefix = -1;
12393           int prefix = 0;
12394           vindex = 0;
12395           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12396              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12397              last one wins.  */
12398           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12399             {
12400               if (last_repz_prefix > last_repnz_prefix)
12401                 {
12402                   vindex = 1;
12403                   prefix = PREFIX_REPZ;
12404                   last_prefix = last_repz_prefix;
12405                 }
12406               else
12407                 {
12408                   vindex = 3;
12409                   prefix = PREFIX_REPNZ;
12410                   last_prefix = last_repnz_prefix;
12411                 }
12412
12413               /* Ignore the invalid index if it isn't mandatory.  */
12414               if (!mandatory_prefix
12415                   && (prefix_table[dp->op[1].bytemode][vindex].name
12416                       == NULL)
12417                   && (prefix_table[dp->op[1].bytemode][vindex].op[0].bytemode
12418                       == 0))
12419                 vindex = 0;
12420             }
12421
12422           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12423             {
12424               vindex = 2;
12425               prefix = PREFIX_DATA;
12426               last_prefix = last_data_prefix;
12427             }
12428
12429           if (vindex != 0)
12430             {
12431               used_prefixes |= prefix;
12432               all_prefixes[last_prefix] = 0;
12433             }
12434         }
12435       dp = &prefix_table[dp->op[1].bytemode][vindex];
12436       break;
12437
12438     case USE_X86_64_TABLE:
12439       vindex = address_mode == mode_64bit ? 1 : 0;
12440       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12441       break;
12442
12443     case USE_3BYTE_TABLE:
12444       FETCH_DATA (info, codep + 2);
12445       vindex = *codep++;
12446       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12447       end_codep = codep;
12448       modrm.mod = (*codep >> 6) & 3;
12449       modrm.reg = (*codep >> 3) & 7;
12450       modrm.rm = *codep & 7;
12451       break;
12452
12453     case USE_VEX_LEN_TABLE:
12454       if (!need_vex)
12455         abort ();
12456
12457       switch (vex.length)
12458         {
12459         case 128:
12460           vindex = 0;
12461           break;
12462         case 256:
12463           vindex = 1;
12464           break;
12465         default:
12466           abort ();
12467           break;
12468         }
12469
12470       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12471       break;
12472
12473     case USE_XOP_8F_TABLE:
12474       FETCH_DATA (info, codep + 3);
12475       /* All bits in the REX prefix are ignored.  */
12476       rex_ignored = rex;
12477       rex = ~(*codep >> 5) & 0x7;
12478
12479       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12480       switch ((*codep & 0x1f))
12481         {
12482         default:
12483           dp = &bad_opcode;
12484           return dp;
12485         case 0x8:
12486           vex_table_index = XOP_08;
12487           break;
12488         case 0x9:
12489           vex_table_index = XOP_09;
12490           break;
12491         case 0xa:
12492           vex_table_index = XOP_0A;
12493           break;
12494         }
12495       codep++;
12496       vex.w = *codep & 0x80;
12497       if (vex.w && address_mode == mode_64bit)
12498         rex |= REX_W;
12499
12500       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12501       if (address_mode != mode_64bit
12502           && vex.register_specifier > 0x7)
12503         {
12504           dp = &bad_opcode;
12505           return dp;
12506         }
12507
12508       vex.length = (*codep & 0x4) ? 256 : 128;
12509       switch ((*codep & 0x3))
12510         {
12511         case 0:
12512           vex.prefix = 0;
12513           break;
12514         case 1:
12515           vex.prefix = DATA_PREFIX_OPCODE;
12516           break;
12517         case 2:
12518           vex.prefix = REPE_PREFIX_OPCODE;
12519           break;
12520         case 3:
12521           vex.prefix = REPNE_PREFIX_OPCODE;
12522           break;
12523         }
12524       need_vex = 1;
12525       need_vex_reg = 1;
12526       codep++;
12527       vindex = *codep++;
12528       dp = &xop_table[vex_table_index][vindex];
12529
12530       end_codep = codep;
12531       FETCH_DATA (info, codep + 1);
12532       modrm.mod = (*codep >> 6) & 3;
12533       modrm.reg = (*codep >> 3) & 7;
12534       modrm.rm = *codep & 7;
12535       break;
12536
12537     case USE_VEX_C4_TABLE:
12538       /* VEX prefix.  */
12539       FETCH_DATA (info, codep + 3);
12540       /* All bits in the REX prefix are ignored.  */
12541       rex_ignored = rex;
12542       rex = ~(*codep >> 5) & 0x7;
12543       switch ((*codep & 0x1f))
12544         {
12545         default:
12546           dp = &bad_opcode;
12547           return dp;
12548         case 0x1:
12549           vex_table_index = VEX_0F;
12550           break;
12551         case 0x2:
12552           vex_table_index = VEX_0F38;
12553           break;
12554         case 0x3:
12555           vex_table_index = VEX_0F3A;
12556           break;
12557         }
12558       codep++;
12559       vex.w = *codep & 0x80;
12560       if (vex.w && address_mode == mode_64bit)
12561         rex |= REX_W;
12562
12563       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12564       if (address_mode != mode_64bit
12565           && vex.register_specifier > 0x7)
12566         {
12567           dp = &bad_opcode;
12568           return dp;
12569         }
12570
12571       vex.length = (*codep & 0x4) ? 256 : 128;
12572       switch ((*codep & 0x3))
12573         {
12574         case 0:
12575           vex.prefix = 0;
12576           break;
12577         case 1:
12578           vex.prefix = DATA_PREFIX_OPCODE;
12579           break;
12580         case 2:
12581           vex.prefix = REPE_PREFIX_OPCODE;
12582           break;
12583         case 3:
12584           vex.prefix = REPNE_PREFIX_OPCODE;
12585           break;
12586         }
12587       need_vex = 1;
12588       need_vex_reg = 1;
12589       codep++;
12590       vindex = *codep++;
12591       dp = &vex_table[vex_table_index][vindex];
12592       end_codep = codep;
12593       /* There is no MODRM byte for VEX [82|77].  */
12594       if (vindex != 0x77 && vindex != 0x82)
12595         {
12596           FETCH_DATA (info, codep + 1);
12597           modrm.mod = (*codep >> 6) & 3;
12598           modrm.reg = (*codep >> 3) & 7;
12599           modrm.rm = *codep & 7;
12600         }
12601       break;
12602
12603     case USE_VEX_C5_TABLE:
12604       /* VEX prefix.  */
12605       FETCH_DATA (info, codep + 2);
12606       /* All bits in the REX prefix are ignored.  */
12607       rex_ignored = rex;
12608       rex = (*codep & 0x80) ? 0 : REX_R;
12609
12610       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12611       if (address_mode != mode_64bit
12612           && vex.register_specifier > 0x7)
12613         {
12614           dp = &bad_opcode;
12615           return dp;
12616         }
12617
12618       vex.w = 0;
12619
12620       vex.length = (*codep & 0x4) ? 256 : 128;
12621       switch ((*codep & 0x3))
12622         {
12623         case 0:
12624           vex.prefix = 0;
12625           break;
12626         case 1:
12627           vex.prefix = DATA_PREFIX_OPCODE;
12628           break;
12629         case 2:
12630           vex.prefix = REPE_PREFIX_OPCODE;
12631           break;
12632         case 3:
12633           vex.prefix = REPNE_PREFIX_OPCODE;
12634           break;
12635         }
12636       need_vex = 1;
12637       need_vex_reg = 1;
12638       codep++;
12639       vindex = *codep++;
12640       dp = &vex_table[dp->op[1].bytemode][vindex];
12641       end_codep = codep;
12642       /* There is no MODRM byte for VEX [82|77].  */
12643       if (vindex != 0x77 && vindex != 0x82)
12644         {
12645           FETCH_DATA (info, codep + 1);
12646           modrm.mod = (*codep >> 6) & 3;
12647           modrm.reg = (*codep >> 3) & 7;
12648           modrm.rm = *codep & 7;
12649         }
12650       break;
12651
12652     case USE_VEX_W_TABLE:
12653       if (!need_vex)
12654         abort ();
12655
12656       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12657       break;
12658
12659     case USE_EVEX_TABLE:
12660       two_source_ops = 0;
12661       /* EVEX prefix.  */
12662       vex.evex = 1;
12663       FETCH_DATA (info, codep + 4);
12664       /* All bits in the REX prefix are ignored.  */
12665       rex_ignored = rex;
12666       /* The first byte after 0x62.  */
12667       rex = ~(*codep >> 5) & 0x7;
12668       vex.r = *codep & 0x10;
12669       switch ((*codep & 0xf))
12670         {
12671         default:
12672           return &bad_opcode;
12673         case 0x1:
12674           vex_table_index = EVEX_0F;
12675           break;
12676         case 0x2:
12677           vex_table_index = EVEX_0F38;
12678           break;
12679         case 0x3:
12680           vex_table_index = EVEX_0F3A;
12681           break;
12682         }
12683
12684       /* The second byte after 0x62.  */
12685       codep++;
12686       vex.w = *codep & 0x80;
12687       if (vex.w && address_mode == mode_64bit)
12688         rex |= REX_W;
12689
12690       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12691       if (address_mode != mode_64bit)
12692         {
12693           /* In 16/32-bit mode silently ignore following bits.  */
12694           rex &= ~REX_B;
12695           vex.r = 1;
12696           vex.v = 1;
12697           vex.register_specifier &= 0x7;
12698         }
12699
12700       /* The U bit.  */
12701       if (!(*codep & 0x4))
12702         return &bad_opcode;
12703
12704       switch ((*codep & 0x3))
12705         {
12706         case 0:
12707           vex.prefix = 0;
12708           break;
12709         case 1:
12710           vex.prefix = DATA_PREFIX_OPCODE;
12711           break;
12712         case 2:
12713           vex.prefix = REPE_PREFIX_OPCODE;
12714           break;
12715         case 3:
12716           vex.prefix = REPNE_PREFIX_OPCODE;
12717           break;
12718         }
12719
12720       /* The third byte after 0x62.  */
12721       codep++;
12722
12723       /* Remember the static rounding bits.  */
12724       vex.ll = (*codep >> 5) & 3;
12725       vex.b = (*codep & 0x10) != 0;
12726
12727       vex.v = *codep & 0x8;
12728       vex.mask_register_specifier = *codep & 0x7;
12729       vex.zeroing = *codep & 0x80;
12730
12731       need_vex = 1;
12732       need_vex_reg = 1;
12733       codep++;
12734       vindex = *codep++;
12735       dp = &evex_table[vex_table_index][vindex];
12736       end_codep = codep;
12737       FETCH_DATA (info, codep + 1);
12738       modrm.mod = (*codep >> 6) & 3;
12739       modrm.reg = (*codep >> 3) & 7;
12740       modrm.rm = *codep & 7;
12741
12742       /* Set vector length.  */
12743       if (modrm.mod == 3 && vex.b)
12744         vex.length = 512;
12745       else
12746         {
12747           switch (vex.ll)
12748             {
12749             case 0x0:
12750               vex.length = 128;
12751               break;
12752             case 0x1:
12753               vex.length = 256;
12754               break;
12755             case 0x2:
12756               vex.length = 512;
12757               break;
12758             default:
12759               return &bad_opcode;
12760             }
12761         }
12762       break;
12763
12764     case 0:
12765       dp = &bad_opcode;
12766       break;
12767
12768     default:
12769       abort ();
12770     }
12771
12772   if (dp->name != NULL)
12773     return dp;
12774   else
12775     return get_valid_dis386 (dp, info);
12776 }
12777
12778 static void
12779 get_sib (disassemble_info *info, int sizeflag)
12780 {
12781   /* If modrm.mod == 3, operand must be register.  */
12782   if (need_modrm
12783       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12784       && modrm.mod != 3
12785       && modrm.rm == 4)
12786     {
12787       FETCH_DATA (info, codep + 2);
12788       sib.index = (codep [1] >> 3) & 7;
12789       sib.scale = (codep [1] >> 6) & 3;
12790       sib.base = codep [1] & 7;
12791     }
12792 }
12793
12794 static int
12795 print_insn (bfd_vma pc, disassemble_info *info)
12796 {
12797   const struct dis386 *dp;
12798   int i;
12799   char *op_txt[MAX_OPERANDS];
12800   int needcomma;
12801   int sizeflag, orig_sizeflag;
12802   const char *p;
12803   struct dis_private priv;
12804   int prefix_length;
12805
12806   priv.orig_sizeflag = AFLAG | DFLAG;
12807   if ((info->mach & bfd_mach_i386_i386) != 0)
12808     address_mode = mode_32bit;
12809   else if (info->mach == bfd_mach_i386_i8086)
12810     {
12811       address_mode = mode_16bit;
12812       priv.orig_sizeflag = 0;
12813     }
12814   else
12815     address_mode = mode_64bit;
12816
12817   if (intel_syntax == (char) -1)
12818     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12819
12820   for (p = info->disassembler_options; p != NULL; )
12821     {
12822       if (CONST_STRNEQ (p, "x86-64"))
12823         {
12824           address_mode = mode_64bit;
12825           priv.orig_sizeflag = AFLAG | DFLAG;
12826         }
12827       else if (CONST_STRNEQ (p, "i386"))
12828         {
12829           address_mode = mode_32bit;
12830           priv.orig_sizeflag = AFLAG | DFLAG;
12831         }
12832       else if (CONST_STRNEQ (p, "i8086"))
12833         {
12834           address_mode = mode_16bit;
12835           priv.orig_sizeflag = 0;
12836         }
12837       else if (CONST_STRNEQ (p, "intel"))
12838         {
12839           intel_syntax = 1;
12840           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12841             intel_mnemonic = 1;
12842         }
12843       else if (CONST_STRNEQ (p, "att"))
12844         {
12845           intel_syntax = 0;
12846           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12847             intel_mnemonic = 0;
12848         }
12849       else if (CONST_STRNEQ (p, "addr"))
12850         {
12851           if (address_mode == mode_64bit)
12852             {
12853               if (p[4] == '3' && p[5] == '2')
12854                 priv.orig_sizeflag &= ~AFLAG;
12855               else if (p[4] == '6' && p[5] == '4')
12856                 priv.orig_sizeflag |= AFLAG;
12857             }
12858           else
12859             {
12860               if (p[4] == '1' && p[5] == '6')
12861                 priv.orig_sizeflag &= ~AFLAG;
12862               else if (p[4] == '3' && p[5] == '2')
12863                 priv.orig_sizeflag |= AFLAG;
12864             }
12865         }
12866       else if (CONST_STRNEQ (p, "data"))
12867         {
12868           if (p[4] == '1' && p[5] == '6')
12869             priv.orig_sizeflag &= ~DFLAG;
12870           else if (p[4] == '3' && p[5] == '2')
12871             priv.orig_sizeflag |= DFLAG;
12872         }
12873       else if (CONST_STRNEQ (p, "suffix"))
12874         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12875
12876       p = strchr (p, ',');
12877       if (p != NULL)
12878         p++;
12879     }
12880
12881   if (intel_syntax)
12882     {
12883       names64 = intel_names64;
12884       names32 = intel_names32;
12885       names16 = intel_names16;
12886       names8 = intel_names8;
12887       names8rex = intel_names8rex;
12888       names_seg = intel_names_seg;
12889       names_mm = intel_names_mm;
12890       names_bnd = intel_names_bnd;
12891       names_xmm = intel_names_xmm;
12892       names_ymm = intel_names_ymm;
12893       names_zmm = intel_names_zmm;
12894       index64 = intel_index64;
12895       index32 = intel_index32;
12896       names_mask = intel_names_mask;
12897       index16 = intel_index16;
12898       open_char = '[';
12899       close_char = ']';
12900       separator_char = '+';
12901       scale_char = '*';
12902     }
12903   else
12904     {
12905       names64 = att_names64;
12906       names32 = att_names32;
12907       names16 = att_names16;
12908       names8 = att_names8;
12909       names8rex = att_names8rex;
12910       names_seg = att_names_seg;
12911       names_mm = att_names_mm;
12912       names_bnd = att_names_bnd;
12913       names_xmm = att_names_xmm;
12914       names_ymm = att_names_ymm;
12915       names_zmm = att_names_zmm;
12916       index64 = att_index64;
12917       index32 = att_index32;
12918       names_mask = att_names_mask;
12919       index16 = att_index16;
12920       open_char = '(';
12921       close_char =  ')';
12922       separator_char = ',';
12923       scale_char = ',';
12924     }
12925
12926   /* The output looks better if we put 7 bytes on a line, since that
12927      puts most long word instructions on a single line.  Use 8 bytes
12928      for Intel L1OM.  */
12929   if ((info->mach & bfd_mach_l1om) != 0)
12930     info->bytes_per_line = 8;
12931   else
12932     info->bytes_per_line = 7;
12933
12934   info->private_data = &priv;
12935   priv.max_fetched = priv.the_buffer;
12936   priv.insn_start = pc;
12937
12938   obuf[0] = 0;
12939   for (i = 0; i < MAX_OPERANDS; ++i)
12940     {
12941       op_out[i][0] = 0;
12942       op_index[i] = -1;
12943     }
12944
12945   the_info = info;
12946   start_pc = pc;
12947   start_codep = priv.the_buffer;
12948   codep = priv.the_buffer;
12949
12950   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12951     {
12952       const char *name;
12953
12954       /* Getting here means we tried for data but didn't get it.  That
12955          means we have an incomplete instruction of some sort.  Just
12956          print the first byte as a prefix or a .byte pseudo-op.  */
12957       if (codep > priv.the_buffer)
12958         {
12959           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12960           if (name != NULL)
12961             (*info->fprintf_func) (info->stream, "%s", name);
12962           else
12963             {
12964               /* Just print the first byte as a .byte instruction.  */
12965               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12966                                      (unsigned int) priv.the_buffer[0]);
12967             }
12968
12969           return 1;
12970         }
12971
12972       return -1;
12973     }
12974
12975   obufp = obuf;
12976   sizeflag = priv.orig_sizeflag;
12977
12978   if (!ckprefix () || rex_used)
12979     {
12980       /* Too many prefixes or unused REX prefixes.  */
12981       for (i = 0;
12982            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12983            i++)
12984         (*info->fprintf_func) (info->stream, "%s%s",
12985                                i == 0 ? "" : " ",
12986                                prefix_name (all_prefixes[i], sizeflag));
12987       return i;
12988     }
12989
12990   insn_codep = codep;
12991
12992   FETCH_DATA (info, codep + 1);
12993   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12994
12995   if (((prefixes & PREFIX_FWAIT)
12996        && ((*codep < 0xd8) || (*codep > 0xdf))))
12997     {
12998       /* Handle prefixes before fwait.  */
12999       for (i = 0; i < fwait_prefix && all_prefixes[i];
13000            i++)
13001         (*info->fprintf_func) (info->stream, "%s ",
13002                                prefix_name (all_prefixes[i], sizeflag));
13003       (*info->fprintf_func) (info->stream, "fwait");
13004       return i + 1;
13005     }
13006
13007   if (*codep == 0x0f)
13008     {
13009       unsigned char threebyte;
13010       FETCH_DATA (info, codep + 2);
13011       threebyte = *++codep;
13012       dp = &dis386_twobyte[threebyte];
13013       need_modrm = twobyte_has_modrm[*codep];
13014       mandatory_prefix = twobyte_has_mandatory_prefix[*codep];
13015       codep++;
13016     }
13017   else
13018     {
13019       dp = &dis386[*codep];
13020       need_modrm = onebyte_has_modrm[*codep];
13021       mandatory_prefix = 0;
13022       codep++;
13023     }
13024
13025   /* Save sizeflag for printing the extra prefixes later before updating
13026      it for mnemonic and operand processing.  The prefix names depend
13027      only on the address mode.  */
13028   orig_sizeflag = sizeflag;
13029   if (prefixes & PREFIX_ADDR)
13030     sizeflag ^= AFLAG;
13031   if ((prefixes & PREFIX_DATA))
13032     sizeflag ^= DFLAG;
13033
13034   end_codep = codep;
13035   if (need_modrm)
13036     {
13037       FETCH_DATA (info, codep + 1);
13038       modrm.mod = (*codep >> 6) & 3;
13039       modrm.reg = (*codep >> 3) & 7;
13040       modrm.rm = *codep & 7;
13041     }
13042
13043   need_vex = 0;
13044   need_vex_reg = 0;
13045   vex_w_done = 0;
13046   vex.evex = 0;
13047
13048   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13049     {
13050       get_sib (info, sizeflag);
13051       dofloat (sizeflag);
13052     }
13053   else
13054     {
13055       dp = get_valid_dis386 (dp, info);
13056       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13057         {
13058           get_sib (info, sizeflag);
13059           for (i = 0; i < MAX_OPERANDS; ++i)
13060             {
13061               obufp = op_out[i];
13062               op_ad = MAX_OPERANDS - 1 - i;
13063               if (dp->op[i].rtn)
13064                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13065               /* For EVEX instruction after the last operand masking
13066                  should be printed.  */
13067               if (i == 0 && vex.evex)
13068                 {
13069                   /* Don't print {%k0}.  */
13070                   if (vex.mask_register_specifier)
13071                     {
13072                       oappend ("{");
13073                       oappend (names_mask[vex.mask_register_specifier]);
13074                       oappend ("}");
13075                     }
13076                   if (vex.zeroing)
13077                     oappend ("{z}");
13078                 }
13079             }
13080         }
13081     }
13082
13083   /* Check if the REX prefix is used.  */
13084   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13085     all_prefixes[last_rex_prefix] = 0;
13086
13087   /* Check if the SEG prefix is used.  */
13088   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13089                    | PREFIX_FS | PREFIX_GS)) != 0
13090       && (used_prefixes & active_seg_prefix) != 0)
13091     all_prefixes[last_seg_prefix] = 0;
13092
13093   /* Check if the ADDR prefix is used.  */
13094   if ((prefixes & PREFIX_ADDR) != 0
13095       && (used_prefixes & PREFIX_ADDR) != 0)
13096     all_prefixes[last_addr_prefix] = 0;
13097
13098   /* Check if the DATA prefix is used.  */
13099   if ((prefixes & PREFIX_DATA) != 0
13100       && (used_prefixes & PREFIX_DATA) != 0)
13101     all_prefixes[last_data_prefix] = 0;
13102
13103   /* Print the extra prefixes.  */
13104   prefix_length = 0;
13105   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13106     if (all_prefixes[i])
13107       {
13108         const char *name;
13109         name = prefix_name (all_prefixes[i], orig_sizeflag);
13110         if (name == NULL)
13111           abort ();
13112         prefix_length += strlen (name) + 1;
13113         (*info->fprintf_func) (info->stream, "%s ", name);
13114       }
13115
13116   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13117      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13118      used by putop and MMX/SSE operand and may be overriden by the
13119      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13120      separately.  */
13121   if (mandatory_prefix
13122       && dp != &bad_opcode
13123       && (((prefixes
13124             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13125            && (used_prefixes
13126                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13127           || ((((prefixes
13128                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13129                 == PREFIX_DATA)
13130                && (used_prefixes & PREFIX_DATA) == 0))))
13131     {
13132       (*info->fprintf_func) (info->stream, "(bad)");
13133       return end_codep - priv.the_buffer;
13134     }
13135
13136   /* Check maximum code length.  */
13137   if ((codep - start_codep) > MAX_CODE_LENGTH)
13138     {
13139       (*info->fprintf_func) (info->stream, "(bad)");
13140       return MAX_CODE_LENGTH;
13141     }
13142
13143   obufp = mnemonicendp;
13144   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13145     oappend (" ");
13146   oappend (" ");
13147   (*info->fprintf_func) (info->stream, "%s", obuf);
13148
13149   /* The enter and bound instructions are printed with operands in the same
13150      order as the intel book; everything else is printed in reverse order.  */
13151   if (intel_syntax || two_source_ops)
13152     {
13153       bfd_vma riprel;
13154
13155       for (i = 0; i < MAX_OPERANDS; ++i)
13156         op_txt[i] = op_out[i];
13157
13158       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13159         {
13160           op_ad = op_index[i];
13161           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13162           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13163           riprel = op_riprel[i];
13164           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13165           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13166         }
13167     }
13168   else
13169     {
13170       for (i = 0; i < MAX_OPERANDS; ++i)
13171         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13172     }
13173
13174   needcomma = 0;
13175   for (i = 0; i < MAX_OPERANDS; ++i)
13176     if (*op_txt[i])
13177       {
13178         if (needcomma)
13179           (*info->fprintf_func) (info->stream, ",");
13180         if (op_index[i] != -1 && !op_riprel[i])
13181           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13182         else
13183           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13184         needcomma = 1;
13185       }
13186
13187   for (i = 0; i < MAX_OPERANDS; i++)
13188     if (op_index[i] != -1 && op_riprel[i])
13189       {
13190         (*info->fprintf_func) (info->stream, "        # ");
13191         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13192                                                 + op_address[op_index[i]]), info);
13193         break;
13194       }
13195   return codep - priv.the_buffer;
13196 }
13197
13198 static const char *float_mem[] = {
13199   /* d8 */
13200   "fadd{s|}",
13201   "fmul{s|}",
13202   "fcom{s|}",
13203   "fcomp{s|}",
13204   "fsub{s|}",
13205   "fsubr{s|}",
13206   "fdiv{s|}",
13207   "fdivr{s|}",
13208   /* d9 */
13209   "fld{s|}",
13210   "(bad)",
13211   "fst{s|}",
13212   "fstp{s|}",
13213   "fldenvIC",
13214   "fldcw",
13215   "fNstenvIC",
13216   "fNstcw",
13217   /* da */
13218   "fiadd{l|}",
13219   "fimul{l|}",
13220   "ficom{l|}",
13221   "ficomp{l|}",
13222   "fisub{l|}",
13223   "fisubr{l|}",
13224   "fidiv{l|}",
13225   "fidivr{l|}",
13226   /* db */
13227   "fild{l|}",
13228   "fisttp{l|}",
13229   "fist{l|}",
13230   "fistp{l|}",
13231   "(bad)",
13232   "fld{t||t|}",
13233   "(bad)",
13234   "fstp{t||t|}",
13235   /* dc */
13236   "fadd{l|}",
13237   "fmul{l|}",
13238   "fcom{l|}",
13239   "fcomp{l|}",
13240   "fsub{l|}",
13241   "fsubr{l|}",
13242   "fdiv{l|}",
13243   "fdivr{l|}",
13244   /* dd */
13245   "fld{l|}",
13246   "fisttp{ll|}",
13247   "fst{l||}",
13248   "fstp{l|}",
13249   "frstorIC",
13250   "(bad)",
13251   "fNsaveIC",
13252   "fNstsw",
13253   /* de */
13254   "fiadd",
13255   "fimul",
13256   "ficom",
13257   "ficomp",
13258   "fisub",
13259   "fisubr",
13260   "fidiv",
13261   "fidivr",
13262   /* df */
13263   "fild",
13264   "fisttp",
13265   "fist",
13266   "fistp",
13267   "fbld",
13268   "fild{ll|}",
13269   "fbstp",
13270   "fistp{ll|}",
13271 };
13272
13273 static const unsigned char float_mem_mode[] = {
13274   /* d8 */
13275   d_mode,
13276   d_mode,
13277   d_mode,
13278   d_mode,
13279   d_mode,
13280   d_mode,
13281   d_mode,
13282   d_mode,
13283   /* d9 */
13284   d_mode,
13285   0,
13286   d_mode,
13287   d_mode,
13288   0,
13289   w_mode,
13290   0,
13291   w_mode,
13292   /* da */
13293   d_mode,
13294   d_mode,
13295   d_mode,
13296   d_mode,
13297   d_mode,
13298   d_mode,
13299   d_mode,
13300   d_mode,
13301   /* db */
13302   d_mode,
13303   d_mode,
13304   d_mode,
13305   d_mode,
13306   0,
13307   t_mode,
13308   0,
13309   t_mode,
13310   /* dc */
13311   q_mode,
13312   q_mode,
13313   q_mode,
13314   q_mode,
13315   q_mode,
13316   q_mode,
13317   q_mode,
13318   q_mode,
13319   /* dd */
13320   q_mode,
13321   q_mode,
13322   q_mode,
13323   q_mode,
13324   0,
13325   0,
13326   0,
13327   w_mode,
13328   /* de */
13329   w_mode,
13330   w_mode,
13331   w_mode,
13332   w_mode,
13333   w_mode,
13334   w_mode,
13335   w_mode,
13336   w_mode,
13337   /* df */
13338   w_mode,
13339   w_mode,
13340   w_mode,
13341   w_mode,
13342   t_mode,
13343   q_mode,
13344   t_mode,
13345   q_mode
13346 };
13347
13348 #define ST { OP_ST, 0 }
13349 #define STi { OP_STi, 0 }
13350
13351 #define FGRPd9_2 NULL, { { NULL, 0 } }
13352 #define FGRPd9_4 NULL, { { NULL, 1 } }
13353 #define FGRPd9_5 NULL, { { NULL, 2 } }
13354 #define FGRPd9_6 NULL, { { NULL, 3 } }
13355 #define FGRPd9_7 NULL, { { NULL, 4 } }
13356 #define FGRPda_5 NULL, { { NULL, 5 } }
13357 #define FGRPdb_4 NULL, { { NULL, 6 } }
13358 #define FGRPde_3 NULL, { { NULL, 7 } }
13359 #define FGRPdf_4 NULL, { { NULL, 8 } }
13360
13361 static const struct dis386 float_reg[][8] = {
13362   /* d8 */
13363   {
13364     { "fadd",   { ST, STi } },
13365     { "fmul",   { ST, STi } },
13366     { "fcom",   { STi } },
13367     { "fcomp",  { STi } },
13368     { "fsub",   { ST, STi } },
13369     { "fsubr",  { ST, STi } },
13370     { "fdiv",   { ST, STi } },
13371     { "fdivr",  { ST, STi } },
13372   },
13373   /* d9 */
13374   {
13375     { "fld",    { STi } },
13376     { "fxch",   { STi } },
13377     { FGRPd9_2 },
13378     { Bad_Opcode },
13379     { FGRPd9_4 },
13380     { FGRPd9_5 },
13381     { FGRPd9_6 },
13382     { FGRPd9_7 },
13383   },
13384   /* da */
13385   {
13386     { "fcmovb", { ST, STi } },
13387     { "fcmove", { ST, STi } },
13388     { "fcmovbe",{ ST, STi } },
13389     { "fcmovu", { ST, STi } },
13390     { Bad_Opcode },
13391     { FGRPda_5 },
13392     { Bad_Opcode },
13393     { Bad_Opcode },
13394   },
13395   /* db */
13396   {
13397     { "fcmovnb",{ ST, STi } },
13398     { "fcmovne",{ ST, STi } },
13399     { "fcmovnbe",{ ST, STi } },
13400     { "fcmovnu",{ ST, STi } },
13401     { FGRPdb_4 },
13402     { "fucomi", { ST, STi } },
13403     { "fcomi",  { ST, STi } },
13404     { Bad_Opcode },
13405   },
13406   /* dc */
13407   {
13408     { "fadd",   { STi, ST } },
13409     { "fmul",   { STi, ST } },
13410     { Bad_Opcode },
13411     { Bad_Opcode },
13412     { "fsub!M", { STi, ST } },
13413     { "fsubM",  { STi, ST } },
13414     { "fdiv!M", { STi, ST } },
13415     { "fdivM",  { STi, ST } },
13416   },
13417   /* dd */
13418   {
13419     { "ffree",  { STi } },
13420     { Bad_Opcode },
13421     { "fst",    { STi } },
13422     { "fstp",   { STi } },
13423     { "fucom",  { STi } },
13424     { "fucomp", { STi } },
13425     { Bad_Opcode },
13426     { Bad_Opcode },
13427   },
13428   /* de */
13429   {
13430     { "faddp",  { STi, ST } },
13431     { "fmulp",  { STi, ST } },
13432     { Bad_Opcode },
13433     { FGRPde_3 },
13434     { "fsub!Mp", { STi, ST } },
13435     { "fsubMp", { STi, ST } },
13436     { "fdiv!Mp", { STi, ST } },
13437     { "fdivMp", { STi, ST } },
13438   },
13439   /* df */
13440   {
13441     { "ffreep", { STi } },
13442     { Bad_Opcode },
13443     { Bad_Opcode },
13444     { Bad_Opcode },
13445     { FGRPdf_4 },
13446     { "fucomip", { ST, STi } },
13447     { "fcomip", { ST, STi } },
13448     { Bad_Opcode },
13449   },
13450 };
13451
13452 static char *fgrps[][8] = {
13453   /* d9_2  0 */
13454   {
13455     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13456   },
13457
13458   /* d9_4  1 */
13459   {
13460     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13461   },
13462
13463   /* d9_5  2 */
13464   {
13465     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13466   },
13467
13468   /* d9_6  3 */
13469   {
13470     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13471   },
13472
13473   /* d9_7  4 */
13474   {
13475     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13476   },
13477
13478   /* da_5  5 */
13479   {
13480     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13481   },
13482
13483   /* db_4  6 */
13484   {
13485     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13486     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13487   },
13488
13489   /* de_3  7 */
13490   {
13491     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13492   },
13493
13494   /* df_4  8 */
13495   {
13496     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13497   },
13498 };
13499
13500 static void
13501 swap_operand (void)
13502 {
13503   mnemonicendp[0] = '.';
13504   mnemonicendp[1] = 's';
13505   mnemonicendp += 2;
13506 }
13507
13508 static void
13509 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13510                int sizeflag ATTRIBUTE_UNUSED)
13511 {
13512   /* Skip mod/rm byte.  */
13513   MODRM_CHECK;
13514   codep++;
13515 }
13516
13517 static void
13518 dofloat (int sizeflag)
13519 {
13520   const struct dis386 *dp;
13521   unsigned char floatop;
13522
13523   floatop = codep[-1];
13524
13525   if (modrm.mod != 3)
13526     {
13527       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13528
13529       putop (float_mem[fp_indx], sizeflag);
13530       obufp = op_out[0];
13531       op_ad = 2;
13532       OP_E (float_mem_mode[fp_indx], sizeflag);
13533       return;
13534     }
13535   /* Skip mod/rm byte.  */
13536   MODRM_CHECK;
13537   codep++;
13538
13539   dp = &float_reg[floatop - 0xd8][modrm.reg];
13540   if (dp->name == NULL)
13541     {
13542       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13543
13544       /* Instruction fnstsw is only one with strange arg.  */
13545       if (floatop == 0xdf && codep[-1] == 0xe0)
13546         strcpy (op_out[0], names16[0]);
13547     }
13548   else
13549     {
13550       putop (dp->name, sizeflag);
13551
13552       obufp = op_out[0];
13553       op_ad = 2;
13554       if (dp->op[0].rtn)
13555         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13556
13557       obufp = op_out[1];
13558       op_ad = 1;
13559       if (dp->op[1].rtn)
13560         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13561     }
13562 }
13563
13564 /* Like oappend (below), but S is a string starting with '%'.
13565    In Intel syntax, the '%' is elided.  */
13566 static void
13567 oappend_maybe_intel (const char *s)
13568 {
13569   oappend (s + intel_syntax);
13570 }
13571
13572 static void
13573 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13574 {
13575   oappend_maybe_intel ("%st");
13576 }
13577
13578 static void
13579 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13580 {
13581   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13582   oappend_maybe_intel (scratchbuf);
13583 }
13584
13585 /* Capital letters in template are macros.  */
13586 static int
13587 putop (const char *in_template, int sizeflag)
13588 {
13589   const char *p;
13590   int alt = 0;
13591   int cond = 1;
13592   unsigned int l = 0, len = 1;
13593   char last[4];
13594
13595 #define SAVE_LAST(c)                    \
13596   if (l < len && l < sizeof (last))     \
13597     last[l++] = c;                      \
13598   else                                  \
13599     abort ();
13600
13601   for (p = in_template; *p; p++)
13602     {
13603       switch (*p)
13604         {
13605         default:
13606           *obufp++ = *p;
13607           break;
13608         case '%':
13609           len++;
13610           break;
13611         case '!':
13612           cond = 0;
13613           break;
13614         case '{':
13615           alt = 0;
13616           if (intel_syntax)
13617             {
13618               while (*++p != '|')
13619                 if (*p == '}' || *p == '\0')
13620                   abort ();
13621             }
13622           /* Fall through.  */
13623         case 'I':
13624           alt = 1;
13625           continue;
13626         case '|':
13627           while (*++p != '}')
13628             {
13629               if (*p == '\0')
13630                 abort ();
13631             }
13632           break;
13633         case '}':
13634           break;
13635         case 'A':
13636           if (intel_syntax)
13637             break;
13638           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13639             *obufp++ = 'b';
13640           break;
13641         case 'B':
13642           if (l == 0 && len == 1)
13643             {
13644 case_B:
13645               if (intel_syntax)
13646                 break;
13647               if (sizeflag & SUFFIX_ALWAYS)
13648                 *obufp++ = 'b';
13649             }
13650           else
13651             {
13652               if (l != 1
13653                   || len != 2
13654                   || last[0] != 'L')
13655                 {
13656                   SAVE_LAST (*p);
13657                   break;
13658                 }
13659
13660               if (address_mode == mode_64bit
13661                   && !(prefixes & PREFIX_ADDR))
13662                 {
13663                   *obufp++ = 'a';
13664                   *obufp++ = 'b';
13665                   *obufp++ = 's';
13666                 }
13667
13668               goto case_B;
13669             }
13670           break;
13671         case 'C':
13672           if (intel_syntax && !alt)
13673             break;
13674           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13675             {
13676               if (sizeflag & DFLAG)
13677                 *obufp++ = intel_syntax ? 'd' : 'l';
13678               else
13679                 *obufp++ = intel_syntax ? 'w' : 's';
13680               used_prefixes |= (prefixes & PREFIX_DATA);
13681             }
13682           break;
13683         case 'D':
13684           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13685             break;
13686           USED_REX (REX_W);
13687           if (modrm.mod == 3)
13688             {
13689               if (rex & REX_W)
13690                 *obufp++ = 'q';
13691               else
13692                 {
13693                   if (sizeflag & DFLAG)
13694                     *obufp++ = intel_syntax ? 'd' : 'l';
13695                   else
13696                     *obufp++ = 'w';
13697                   used_prefixes |= (prefixes & PREFIX_DATA);
13698                 }
13699             }
13700           else
13701             *obufp++ = 'w';
13702           break;
13703         case 'E':               /* For jcxz/jecxz */
13704           if (address_mode == mode_64bit)
13705             {
13706               if (sizeflag & AFLAG)
13707                 *obufp++ = 'r';
13708               else
13709                 *obufp++ = 'e';
13710             }
13711           else
13712             if (sizeflag & AFLAG)
13713               *obufp++ = 'e';
13714           used_prefixes |= (prefixes & PREFIX_ADDR);
13715           break;
13716         case 'F':
13717           if (intel_syntax)
13718             break;
13719           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13720             {
13721               if (sizeflag & AFLAG)
13722                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13723               else
13724                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13725               used_prefixes |= (prefixes & PREFIX_ADDR);
13726             }
13727           break;
13728         case 'G':
13729           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13730             break;
13731           if ((rex & REX_W) || (sizeflag & DFLAG))
13732             *obufp++ = 'l';
13733           else
13734             *obufp++ = 'w';
13735           if (!(rex & REX_W))
13736             used_prefixes |= (prefixes & PREFIX_DATA);
13737           break;
13738         case 'H':
13739           if (intel_syntax)
13740             break;
13741           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13742               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13743             {
13744               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13745               *obufp++ = ',';
13746               *obufp++ = 'p';
13747               if (prefixes & PREFIX_DS)
13748                 *obufp++ = 't';
13749               else
13750                 *obufp++ = 'n';
13751             }
13752           break;
13753         case 'J':
13754           if (intel_syntax)
13755             break;
13756           *obufp++ = 'l';
13757           break;
13758         case 'K':
13759           USED_REX (REX_W);
13760           if (rex & REX_W)
13761             *obufp++ = 'q';
13762           else
13763             *obufp++ = 'd';
13764           break;
13765         case 'Z':
13766           if (intel_syntax)
13767             break;
13768           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13769             {
13770               *obufp++ = 'q';
13771               break;
13772             }
13773           /* Fall through.  */
13774           goto case_L;
13775         case 'L':
13776           if (l != 0 || len != 1)
13777             {
13778               SAVE_LAST (*p);
13779               break;
13780             }
13781 case_L:
13782           if (intel_syntax)
13783             break;
13784           if (sizeflag & SUFFIX_ALWAYS)
13785             *obufp++ = 'l';
13786           break;
13787         case 'M':
13788           if (intel_mnemonic != cond)
13789             *obufp++ = 'r';
13790           break;
13791         case 'N':
13792           if ((prefixes & PREFIX_FWAIT) == 0)
13793             *obufp++ = 'n';
13794           else
13795             used_prefixes |= PREFIX_FWAIT;
13796           break;
13797         case 'O':
13798           USED_REX (REX_W);
13799           if (rex & REX_W)
13800             *obufp++ = 'o';
13801           else if (intel_syntax && (sizeflag & DFLAG))
13802             *obufp++ = 'q';
13803           else
13804             *obufp++ = 'd';
13805           if (!(rex & REX_W))
13806             used_prefixes |= (prefixes & PREFIX_DATA);
13807           break;
13808         case 'T':
13809           if (!intel_syntax
13810               && address_mode == mode_64bit
13811               && ((sizeflag & DFLAG) || (rex & REX_W)))
13812             {
13813               *obufp++ = 'q';
13814               break;
13815             }
13816           /* Fall through.  */
13817           goto case_P;
13818         case 'P':
13819           if (l == 0 && len == 1)
13820             {
13821 case_P:
13822               if (intel_syntax)
13823                 {
13824                   if ((rex & REX_W) == 0
13825                       && (prefixes & PREFIX_DATA))
13826                     {
13827                       if ((sizeflag & DFLAG) == 0)
13828                         *obufp++ = 'w';
13829                       used_prefixes |= (prefixes & PREFIX_DATA);
13830                     }
13831                   break;
13832                 }
13833               if ((prefixes & PREFIX_DATA)
13834                   || (rex & REX_W)
13835                   || (sizeflag & SUFFIX_ALWAYS))
13836                 {
13837                   USED_REX (REX_W);
13838                   if (rex & REX_W)
13839                     *obufp++ = 'q';
13840                   else
13841                     {
13842                       if (sizeflag & DFLAG)
13843                         *obufp++ = 'l';
13844                       else
13845                         *obufp++ = 'w';
13846                       used_prefixes |= (prefixes & PREFIX_DATA);
13847                     }
13848                 }
13849             }
13850           else
13851             {
13852               if (l != 1 || len != 2 || last[0] != 'L')
13853                 {
13854                   SAVE_LAST (*p);
13855                   break;
13856                 }
13857
13858               if ((prefixes & PREFIX_DATA)
13859                   || (rex & REX_W)
13860                   || (sizeflag & SUFFIX_ALWAYS))
13861                 {
13862                   USED_REX (REX_W);
13863                   if (rex & REX_W)
13864                     *obufp++ = 'q';
13865                   else
13866                     {
13867                       if (sizeflag & DFLAG)
13868                         *obufp++ = intel_syntax ? 'd' : 'l';
13869                       else
13870                         *obufp++ = 'w';
13871                       used_prefixes |= (prefixes & PREFIX_DATA);
13872                     }
13873                 }
13874             }
13875           break;
13876         case 'U':
13877           if (intel_syntax)
13878             break;
13879           if (address_mode == mode_64bit
13880               && ((sizeflag & DFLAG) || (rex & REX_W)))
13881             {
13882               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13883                 *obufp++ = 'q';
13884               break;
13885             }
13886           /* Fall through.  */
13887           goto case_Q;
13888         case 'Q':
13889           if (l == 0 && len == 1)
13890             {
13891 case_Q:
13892               if (intel_syntax && !alt)
13893                 break;
13894               USED_REX (REX_W);
13895               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13896                 {
13897                   if (rex & REX_W)
13898                     *obufp++ = 'q';
13899                   else
13900                     {
13901                       if (sizeflag & DFLAG)
13902                         *obufp++ = intel_syntax ? 'd' : 'l';
13903                       else
13904                         *obufp++ = 'w';
13905                       used_prefixes |= (prefixes & PREFIX_DATA);
13906                     }
13907                 }
13908             }
13909           else
13910             {
13911               if (l != 1 || len != 2 || last[0] != 'L')
13912                 {
13913                   SAVE_LAST (*p);
13914                   break;
13915                 }
13916               if (intel_syntax
13917                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13918                 break;
13919               if ((rex & REX_W))
13920                 {
13921                   USED_REX (REX_W);
13922                   *obufp++ = 'q';
13923                 }
13924               else
13925                 *obufp++ = 'l';
13926             }
13927           break;
13928         case 'R':
13929           USED_REX (REX_W);
13930           if (rex & REX_W)
13931             *obufp++ = 'q';
13932           else if (sizeflag & DFLAG)
13933             {
13934               if (intel_syntax)
13935                   *obufp++ = 'd';
13936               else
13937                   *obufp++ = 'l';
13938             }
13939           else
13940             *obufp++ = 'w';
13941           if (intel_syntax && !p[1]
13942               && ((rex & REX_W) || (sizeflag & DFLAG)))
13943             *obufp++ = 'e';
13944           if (!(rex & REX_W))
13945             used_prefixes |= (prefixes & PREFIX_DATA);
13946           break;
13947         case 'V':
13948           if (l == 0 && len == 1)
13949             {
13950               if (intel_syntax)
13951                 break;
13952               if (address_mode == mode_64bit
13953                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13954                 {
13955                   if (sizeflag & SUFFIX_ALWAYS)
13956                     *obufp++ = 'q';
13957                   break;
13958                 }
13959             }
13960           else
13961             {
13962               if (l != 1
13963                   || len != 2
13964                   || last[0] != 'L')
13965                 {
13966                   SAVE_LAST (*p);
13967                   break;
13968                 }
13969
13970               if (rex & REX_W)
13971                 {
13972                   *obufp++ = 'a';
13973                   *obufp++ = 'b';
13974                   *obufp++ = 's';
13975                 }
13976             }
13977           /* Fall through.  */
13978           goto case_S;
13979         case 'S':
13980           if (l == 0 && len == 1)
13981             {
13982 case_S:
13983               if (intel_syntax)
13984                 break;
13985               if (sizeflag & SUFFIX_ALWAYS)
13986                 {
13987                   if (rex & REX_W)
13988                     *obufp++ = 'q';
13989                   else
13990                     {
13991                       if (sizeflag & DFLAG)
13992                         *obufp++ = 'l';
13993                       else
13994                         *obufp++ = 'w';
13995                       used_prefixes |= (prefixes & PREFIX_DATA);
13996                     }
13997                 }
13998             }
13999           else
14000             {
14001               if (l != 1
14002                   || len != 2
14003                   || last[0] != 'L')
14004                 {
14005                   SAVE_LAST (*p);
14006                   break;
14007                 }
14008
14009               if (address_mode == mode_64bit
14010                   && !(prefixes & PREFIX_ADDR))
14011                 {
14012                   *obufp++ = 'a';
14013                   *obufp++ = 'b';
14014                   *obufp++ = 's';
14015                 }
14016
14017               goto case_S;
14018             }
14019           break;
14020         case 'X':
14021           if (l != 0 || len != 1)
14022             {
14023               SAVE_LAST (*p);
14024               break;
14025             }
14026           if (need_vex && vex.prefix)
14027             {
14028               if (vex.prefix == DATA_PREFIX_OPCODE)
14029                 *obufp++ = 'd';
14030               else
14031                 *obufp++ = 's';
14032             }
14033           else
14034             {
14035               if (prefixes & PREFIX_DATA)
14036                 *obufp++ = 'd';
14037               else
14038                 *obufp++ = 's';
14039               used_prefixes |= (prefixes & PREFIX_DATA);
14040             }
14041           break;
14042         case 'Y':
14043           if (l == 0 && len == 1)
14044             {
14045               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14046                 break;
14047               if (rex & REX_W)
14048                 {
14049                   USED_REX (REX_W);
14050                   *obufp++ = 'q';
14051                 }
14052               break;
14053             }
14054           else
14055             {
14056               if (l != 1 || len != 2 || last[0] != 'X')
14057                 {
14058                   SAVE_LAST (*p);
14059                   break;
14060                 }
14061               if (!need_vex)
14062                 abort ();
14063               if (intel_syntax
14064                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14065                 break;
14066               switch (vex.length)
14067                 {
14068                 case 128:
14069                   *obufp++ = 'x';
14070                   break;
14071                 case 256:
14072                   *obufp++ = 'y';
14073                   break;
14074                 default:
14075                   abort ();
14076                 }
14077             }
14078           break;
14079         case 'W':
14080           if (l == 0 && len == 1)
14081             {
14082               /* operand size flag for cwtl, cbtw */
14083               USED_REX (REX_W);
14084               if (rex & REX_W)
14085                 {
14086                   if (intel_syntax)
14087                     *obufp++ = 'd';
14088                   else
14089                     *obufp++ = 'l';
14090                 }
14091               else if (sizeflag & DFLAG)
14092                 *obufp++ = 'w';
14093               else
14094                 *obufp++ = 'b';
14095               if (!(rex & REX_W))
14096                 used_prefixes |= (prefixes & PREFIX_DATA);
14097             }
14098           else
14099             {
14100               if (l != 1
14101                   || len != 2
14102                   || (last[0] != 'X'
14103                       && last[0] != 'L'))
14104                 {
14105                   SAVE_LAST (*p);
14106                   break;
14107                 }
14108               if (!need_vex)
14109                 abort ();
14110               if (last[0] == 'X')
14111                 *obufp++ = vex.w ? 'd': 's';
14112               else
14113                 *obufp++ = vex.w ? 'q': 'd';
14114             }
14115           break;
14116         }
14117       alt = 0;
14118     }
14119   *obufp = 0;
14120   mnemonicendp = obufp;
14121   return 0;
14122 }
14123
14124 static void
14125 oappend (const char *s)
14126 {
14127   obufp = stpcpy (obufp, s);
14128 }
14129
14130 static void
14131 append_seg (void)
14132 {
14133   /* Only print the active segment register.  */
14134   if (!active_seg_prefix)
14135     return;
14136
14137   used_prefixes |= active_seg_prefix;
14138   switch (active_seg_prefix)
14139     {
14140     case PREFIX_CS:
14141       oappend_maybe_intel ("%cs:");
14142       break;
14143     case PREFIX_DS:
14144       oappend_maybe_intel ("%ds:");
14145       break;
14146     case PREFIX_SS:
14147       oappend_maybe_intel ("%ss:");
14148       break;
14149     case PREFIX_ES:
14150       oappend_maybe_intel ("%es:");
14151       break;
14152     case PREFIX_FS:
14153       oappend_maybe_intel ("%fs:");
14154       break;
14155     case PREFIX_GS:
14156       oappend_maybe_intel ("%gs:");
14157       break;
14158     default:
14159       break;
14160     }
14161 }
14162
14163 static void
14164 OP_indirE (int bytemode, int sizeflag)
14165 {
14166   if (!intel_syntax)
14167     oappend ("*");
14168   OP_E (bytemode, sizeflag);
14169 }
14170
14171 static void
14172 print_operand_value (char *buf, int hex, bfd_vma disp)
14173 {
14174   if (address_mode == mode_64bit)
14175     {
14176       if (hex)
14177         {
14178           char tmp[30];
14179           int i;
14180           buf[0] = '0';
14181           buf[1] = 'x';
14182           sprintf_vma (tmp, disp);
14183           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14184           strcpy (buf + 2, tmp + i);
14185         }
14186       else
14187         {
14188           bfd_signed_vma v = disp;
14189           char tmp[30];
14190           int i;
14191           if (v < 0)
14192             {
14193               *(buf++) = '-';
14194               v = -disp;
14195               /* Check for possible overflow on 0x8000000000000000.  */
14196               if (v < 0)
14197                 {
14198                   strcpy (buf, "9223372036854775808");
14199                   return;
14200                 }
14201             }
14202           if (!v)
14203             {
14204               strcpy (buf, "0");
14205               return;
14206             }
14207
14208           i = 0;
14209           tmp[29] = 0;
14210           while (v)
14211             {
14212               tmp[28 - i] = (v % 10) + '0';
14213               v /= 10;
14214               i++;
14215             }
14216           strcpy (buf, tmp + 29 - i);
14217         }
14218     }
14219   else
14220     {
14221       if (hex)
14222         sprintf (buf, "0x%x", (unsigned int) disp);
14223       else
14224         sprintf (buf, "%d", (int) disp);
14225     }
14226 }
14227
14228 /* Put DISP in BUF as signed hex number.  */
14229
14230 static void
14231 print_displacement (char *buf, bfd_vma disp)
14232 {
14233   bfd_signed_vma val = disp;
14234   char tmp[30];
14235   int i, j = 0;
14236
14237   if (val < 0)
14238     {
14239       buf[j++] = '-';
14240       val = -disp;
14241
14242       /* Check for possible overflow.  */
14243       if (val < 0)
14244         {
14245           switch (address_mode)
14246             {
14247             case mode_64bit:
14248               strcpy (buf + j, "0x8000000000000000");
14249               break;
14250             case mode_32bit:
14251               strcpy (buf + j, "0x80000000");
14252               break;
14253             case mode_16bit:
14254               strcpy (buf + j, "0x8000");
14255               break;
14256             }
14257           return;
14258         }
14259     }
14260
14261   buf[j++] = '0';
14262   buf[j++] = 'x';
14263
14264   sprintf_vma (tmp, (bfd_vma) val);
14265   for (i = 0; tmp[i] == '0'; i++)
14266     continue;
14267   if (tmp[i] == '\0')
14268     i--;
14269   strcpy (buf + j, tmp + i);
14270 }
14271
14272 static void
14273 intel_operand_size (int bytemode, int sizeflag)
14274 {
14275   if (vex.evex
14276       && vex.b
14277       && (bytemode == x_mode
14278           || bytemode == evex_half_bcst_xmmq_mode))
14279     {
14280       if (vex.w)
14281         oappend ("QWORD PTR ");
14282       else
14283         oappend ("DWORD PTR ");
14284       return;
14285     }
14286   switch (bytemode)
14287     {
14288     case b_mode:
14289     case b_swap_mode:
14290     case dqb_mode:
14291     case db_mode:
14292       oappend ("BYTE PTR ");
14293       break;
14294     case w_mode:
14295     case dw_mode:
14296     case dqw_mode:
14297     case dqw_swap_mode:
14298       oappend ("WORD PTR ");
14299       break;
14300     case stack_v_mode:
14301       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14302         {
14303           oappend ("QWORD PTR ");
14304           break;
14305         }
14306       /* FALLTHRU */
14307     case v_mode:
14308     case v_swap_mode:
14309     case dq_mode:
14310       USED_REX (REX_W);
14311       if (rex & REX_W)
14312         oappend ("QWORD PTR ");
14313       else
14314         {
14315           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14316             oappend ("DWORD PTR ");
14317           else
14318             oappend ("WORD PTR ");
14319           used_prefixes |= (prefixes & PREFIX_DATA);
14320         }
14321       break;
14322     case z_mode:
14323       if ((rex & REX_W) || (sizeflag & DFLAG))
14324         *obufp++ = 'D';
14325       oappend ("WORD PTR ");
14326       if (!(rex & REX_W))
14327         used_prefixes |= (prefixes & PREFIX_DATA);
14328       break;
14329     case a_mode:
14330       if (sizeflag & DFLAG)
14331         oappend ("QWORD PTR ");
14332       else
14333         oappend ("DWORD PTR ");
14334       used_prefixes |= (prefixes & PREFIX_DATA);
14335       break;
14336     case d_mode:
14337     case d_scalar_mode:
14338     case d_scalar_swap_mode:
14339     case d_swap_mode:
14340     case dqd_mode:
14341       oappend ("DWORD PTR ");
14342       break;
14343     case q_mode:
14344     case q_scalar_mode:
14345     case q_scalar_swap_mode:
14346     case q_swap_mode:
14347       oappend ("QWORD PTR ");
14348       break;
14349     case m_mode:
14350       if (address_mode == mode_64bit)
14351         oappend ("QWORD PTR ");
14352       else
14353         oappend ("DWORD PTR ");
14354       break;
14355     case f_mode:
14356       if (sizeflag & DFLAG)
14357         oappend ("FWORD PTR ");
14358       else
14359         oappend ("DWORD PTR ");
14360       used_prefixes |= (prefixes & PREFIX_DATA);
14361       break;
14362     case t_mode:
14363       oappend ("TBYTE PTR ");
14364       break;
14365     case x_mode:
14366     case x_swap_mode:
14367     case evex_x_gscat_mode:
14368     case evex_x_nobcst_mode:
14369       if (need_vex)
14370         {
14371           switch (vex.length)
14372             {
14373             case 128:
14374               oappend ("XMMWORD PTR ");
14375               break;
14376             case 256:
14377               oappend ("YMMWORD PTR ");
14378               break;
14379             case 512:
14380               oappend ("ZMMWORD PTR ");
14381               break;
14382             default:
14383               abort ();
14384             }
14385         }
14386       else
14387         oappend ("XMMWORD PTR ");
14388       break;
14389     case xmm_mode:
14390       oappend ("XMMWORD PTR ");
14391       break;
14392     case ymm_mode:
14393       oappend ("YMMWORD PTR ");
14394       break;
14395     case xmmq_mode:
14396     case evex_half_bcst_xmmq_mode:
14397       if (!need_vex)
14398         abort ();
14399
14400       switch (vex.length)
14401         {
14402         case 128:
14403           oappend ("QWORD PTR ");
14404           break;
14405         case 256:
14406           oappend ("XMMWORD PTR ");
14407           break;
14408         case 512:
14409           oappend ("YMMWORD PTR ");
14410           break;
14411         default:
14412           abort ();
14413         }
14414       break;
14415     case xmm_mb_mode:
14416       if (!need_vex)
14417         abort ();
14418
14419       switch (vex.length)
14420         {
14421         case 128:
14422         case 256:
14423         case 512:
14424           oappend ("BYTE PTR ");
14425           break;
14426         default:
14427           abort ();
14428         }
14429       break;
14430     case xmm_mw_mode:
14431       if (!need_vex)
14432         abort ();
14433
14434       switch (vex.length)
14435         {
14436         case 128:
14437         case 256:
14438         case 512:
14439           oappend ("WORD PTR ");
14440           break;
14441         default:
14442           abort ();
14443         }
14444       break;
14445     case xmm_md_mode:
14446       if (!need_vex)
14447         abort ();
14448
14449       switch (vex.length)
14450         {
14451         case 128:
14452         case 256:
14453         case 512:
14454           oappend ("DWORD PTR ");
14455           break;
14456         default:
14457           abort ();
14458         }
14459       break;
14460     case xmm_mq_mode:
14461       if (!need_vex)
14462         abort ();
14463
14464       switch (vex.length)
14465         {
14466         case 128:
14467         case 256:
14468         case 512:
14469           oappend ("QWORD PTR ");
14470           break;
14471         default:
14472           abort ();
14473         }
14474       break;
14475     case xmmdw_mode:
14476       if (!need_vex)
14477         abort ();
14478
14479       switch (vex.length)
14480         {
14481         case 128:
14482           oappend ("WORD PTR ");
14483           break;
14484         case 256:
14485           oappend ("DWORD PTR ");
14486           break;
14487         case 512:
14488           oappend ("QWORD PTR ");
14489           break;
14490         default:
14491           abort ();
14492         }
14493       break;
14494     case xmmqd_mode:
14495       if (!need_vex)
14496         abort ();
14497
14498       switch (vex.length)
14499         {
14500         case 128:
14501           oappend ("DWORD PTR ");
14502           break;
14503         case 256:
14504           oappend ("QWORD PTR ");
14505           break;
14506         case 512:
14507           oappend ("XMMWORD PTR ");
14508           break;
14509         default:
14510           abort ();
14511         }
14512       break;
14513     case ymmq_mode:
14514       if (!need_vex)
14515         abort ();
14516
14517       switch (vex.length)
14518         {
14519         case 128:
14520           oappend ("QWORD PTR ");
14521           break;
14522         case 256:
14523           oappend ("YMMWORD PTR ");
14524           break;
14525         case 512:
14526           oappend ("ZMMWORD PTR ");
14527           break;
14528         default:
14529           abort ();
14530         }
14531       break;
14532     case ymmxmm_mode:
14533       if (!need_vex)
14534         abort ();
14535
14536       switch (vex.length)
14537         {
14538         case 128:
14539         case 256:
14540           oappend ("XMMWORD PTR ");
14541           break;
14542         default:
14543           abort ();
14544         }
14545       break;
14546     case o_mode:
14547       oappend ("OWORD PTR ");
14548       break;
14549     case xmm_mdq_mode:
14550     case vex_w_dq_mode:
14551     case vex_scalar_w_dq_mode:
14552       if (!need_vex)
14553         abort ();
14554
14555       if (vex.w)
14556         oappend ("QWORD PTR ");
14557       else
14558         oappend ("DWORD PTR ");
14559       break;
14560     case vex_vsib_d_w_dq_mode:
14561     case vex_vsib_q_w_dq_mode:
14562       if (!need_vex)
14563         abort ();
14564
14565       if (!vex.evex)
14566         {
14567           if (vex.w)
14568             oappend ("QWORD PTR ");
14569           else
14570             oappend ("DWORD PTR ");
14571         }
14572       else
14573         {
14574           switch (vex.length)
14575             {
14576             case 128:
14577               oappend ("XMMWORD PTR ");
14578               break;
14579             case 256:
14580               oappend ("YMMWORD PTR ");
14581               break;
14582             case 512:
14583               oappend ("ZMMWORD PTR ");
14584               break;
14585             default:
14586               abort ();
14587             }
14588         }
14589       break;
14590     case vex_vsib_q_w_d_mode:
14591     case vex_vsib_d_w_d_mode:
14592       if (!need_vex || !vex.evex)
14593         abort ();
14594
14595       switch (vex.length)
14596         {
14597         case 128:
14598           oappend ("QWORD PTR ");
14599           break;
14600         case 256:
14601           oappend ("XMMWORD PTR ");
14602           break;
14603         case 512:
14604           oappend ("YMMWORD PTR ");
14605           break;
14606         default:
14607           abort ();
14608         }
14609
14610       break;
14611     case mask_bd_mode:
14612       if (!need_vex || vex.length != 128)
14613         abort ();
14614       if (vex.w)
14615         oappend ("DWORD PTR ");
14616       else
14617         oappend ("BYTE PTR ");
14618       break;
14619     case mask_mode:
14620       if (!need_vex)
14621         abort ();
14622       if (vex.w)
14623         oappend ("QWORD PTR ");
14624       else
14625         oappend ("WORD PTR ");
14626       break;
14627     case v_bnd_mode:
14628     default:
14629       break;
14630     }
14631 }
14632
14633 static void
14634 OP_E_register (int bytemode, int sizeflag)
14635 {
14636   int reg = modrm.rm;
14637   const char **names;
14638
14639   USED_REX (REX_B);
14640   if ((rex & REX_B))
14641     reg += 8;
14642
14643   if ((sizeflag & SUFFIX_ALWAYS)
14644       && (bytemode == b_swap_mode
14645           || bytemode == v_swap_mode
14646           || bytemode == dqw_swap_mode))
14647     swap_operand ();
14648
14649   switch (bytemode)
14650     {
14651     case b_mode:
14652     case b_swap_mode:
14653       USED_REX (0);
14654       if (rex)
14655         names = names8rex;
14656       else
14657         names = names8;
14658       break;
14659     case w_mode:
14660       names = names16;
14661       break;
14662     case d_mode:
14663     case dw_mode:
14664     case db_mode:
14665       names = names32;
14666       break;
14667     case q_mode:
14668       names = names64;
14669       break;
14670     case m_mode:
14671     case v_bnd_mode:
14672       names = address_mode == mode_64bit ? names64 : names32;
14673       break;
14674     case bnd_mode:
14675       names = names_bnd;
14676       break;
14677     case stack_v_mode:
14678       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14679         {
14680           names = names64;
14681           break;
14682         }
14683       bytemode = v_mode;
14684       /* FALLTHRU */
14685     case v_mode:
14686     case v_swap_mode:
14687     case dq_mode:
14688     case dqb_mode:
14689     case dqd_mode:
14690     case dqw_mode:
14691     case dqw_swap_mode:
14692       USED_REX (REX_W);
14693       if (rex & REX_W)
14694         names = names64;
14695       else
14696         {
14697           if ((sizeflag & DFLAG)
14698               || (bytemode != v_mode
14699                   && bytemode != v_swap_mode))
14700             names = names32;
14701           else
14702             names = names16;
14703           used_prefixes |= (prefixes & PREFIX_DATA);
14704         }
14705       break;
14706     case mask_bd_mode:
14707     case mask_mode:
14708       names = names_mask;
14709       break;
14710     case 0:
14711       return;
14712     default:
14713       oappend (INTERNAL_DISASSEMBLER_ERROR);
14714       return;
14715     }
14716   oappend (names[reg]);
14717 }
14718
14719 static void
14720 OP_E_memory (int bytemode, int sizeflag)
14721 {
14722   bfd_vma disp = 0;
14723   int add = (rex & REX_B) ? 8 : 0;
14724   int riprel = 0;
14725   int shift;
14726
14727   if (vex.evex)
14728     {
14729       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14730       if (vex.b
14731           && bytemode != x_mode
14732           && bytemode != xmmq_mode
14733           && bytemode != evex_half_bcst_xmmq_mode)
14734         {
14735           BadOp ();
14736           return;
14737         }
14738       switch (bytemode)
14739         {
14740         case dqw_mode:
14741         case dw_mode:
14742         case dqw_swap_mode:
14743           shift = 1;
14744           break;
14745         case dqb_mode:
14746         case db_mode:
14747           shift = 0;
14748           break;
14749         case vex_vsib_d_w_dq_mode:
14750         case vex_vsib_d_w_d_mode:
14751         case vex_vsib_q_w_dq_mode:
14752         case vex_vsib_q_w_d_mode:
14753         case evex_x_gscat_mode:
14754         case xmm_mdq_mode:
14755           shift = vex.w ? 3 : 2;
14756           break;
14757         case x_mode:
14758         case evex_half_bcst_xmmq_mode:
14759         case xmmq_mode:
14760           if (vex.b)
14761             {
14762               shift = vex.w ? 3 : 2;
14763               break;
14764             }
14765           /* Fall through if vex.b == 0.  */
14766         case xmmqd_mode:
14767         case xmmdw_mode:
14768         case ymmq_mode:
14769         case evex_x_nobcst_mode:
14770         case x_swap_mode:
14771           switch (vex.length)
14772             {
14773             case 128:
14774               shift = 4;
14775               break;
14776             case 256:
14777               shift = 5;
14778               break;
14779             case 512:
14780               shift = 6;
14781               break;
14782             default:
14783               abort ();
14784             }
14785           break;
14786         case ymm_mode:
14787           shift = 5;
14788           break;
14789         case xmm_mode:
14790           shift = 4;
14791           break;
14792         case xmm_mq_mode:
14793         case q_mode:
14794         case q_scalar_mode:
14795         case q_swap_mode:
14796         case q_scalar_swap_mode:
14797           shift = 3;
14798           break;
14799         case dqd_mode:
14800         case xmm_md_mode:
14801         case d_mode:
14802         case d_scalar_mode:
14803         case d_swap_mode:
14804         case d_scalar_swap_mode:
14805           shift = 2;
14806           break;
14807         case xmm_mw_mode:
14808           shift = 1;
14809           break;
14810         case xmm_mb_mode:
14811           shift = 0;
14812           break;
14813         default:
14814           abort ();
14815         }
14816       /* Make necessary corrections to shift for modes that need it.
14817          For these modes we currently have shift 4, 5 or 6 depending on
14818          vex.length (it corresponds to xmmword, ymmword or zmmword
14819          operand).  We might want to make it 3, 4 or 5 (e.g. for
14820          xmmq_mode).  In case of broadcast enabled the corrections
14821          aren't needed, as element size is always 32 or 64 bits.  */
14822       if (!vex.b
14823           && (bytemode == xmmq_mode
14824               || bytemode == evex_half_bcst_xmmq_mode))
14825         shift -= 1;
14826       else if (bytemode == xmmqd_mode)
14827         shift -= 2;
14828       else if (bytemode == xmmdw_mode)
14829         shift -= 3;
14830       else if (bytemode == ymmq_mode && vex.length == 128)
14831         shift -= 1;
14832     }
14833   else
14834     shift = 0;
14835
14836   USED_REX (REX_B);
14837   if (intel_syntax)
14838     intel_operand_size (bytemode, sizeflag);
14839   append_seg ();
14840
14841   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14842     {
14843       /* 32/64 bit address mode */
14844       int havedisp;
14845       int havesib;
14846       int havebase;
14847       int haveindex;
14848       int needindex;
14849       int base, rbase;
14850       int vindex = 0;
14851       int scale = 0;
14852       int addr32flag = !((sizeflag & AFLAG)
14853                          || bytemode == v_bnd_mode
14854                          || bytemode == bnd_mode);
14855       const char **indexes64 = names64;
14856       const char **indexes32 = names32;
14857
14858       havesib = 0;
14859       havebase = 1;
14860       haveindex = 0;
14861       base = modrm.rm;
14862
14863       if (base == 4)
14864         {
14865           havesib = 1;
14866           vindex = sib.index;
14867           USED_REX (REX_X);
14868           if (rex & REX_X)
14869             vindex += 8;
14870           switch (bytemode)
14871             {
14872             case vex_vsib_d_w_dq_mode:
14873             case vex_vsib_d_w_d_mode:
14874             case vex_vsib_q_w_dq_mode:
14875             case vex_vsib_q_w_d_mode:
14876               if (!need_vex)
14877                 abort ();
14878               if (vex.evex)
14879                 {
14880                   if (!vex.v)
14881                     vindex += 16;
14882                 }
14883
14884               haveindex = 1;
14885               switch (vex.length)
14886                 {
14887                 case 128:
14888                   indexes64 = indexes32 = names_xmm;
14889                   break;
14890                 case 256:
14891                   if (!vex.w
14892                       || bytemode == vex_vsib_q_w_dq_mode
14893                       || bytemode == vex_vsib_q_w_d_mode)
14894                     indexes64 = indexes32 = names_ymm;
14895                   else
14896                     indexes64 = indexes32 = names_xmm;
14897                   break;
14898                 case 512:
14899                   if (!vex.w
14900                       || bytemode == vex_vsib_q_w_dq_mode
14901                       || bytemode == vex_vsib_q_w_d_mode)
14902                     indexes64 = indexes32 = names_zmm;
14903                   else
14904                     indexes64 = indexes32 = names_ymm;
14905                   break;
14906                 default:
14907                   abort ();
14908                 }
14909               break;
14910             default:
14911               haveindex = vindex != 4;
14912               break;
14913             }
14914           scale = sib.scale;
14915           base = sib.base;
14916           codep++;
14917         }
14918       rbase = base + add;
14919
14920       switch (modrm.mod)
14921         {
14922         case 0:
14923           if (base == 5)
14924             {
14925               havebase = 0;
14926               if (address_mode == mode_64bit && !havesib)
14927                 riprel = 1;
14928               disp = get32s ();
14929             }
14930           break;
14931         case 1:
14932           FETCH_DATA (the_info, codep + 1);
14933           disp = *codep++;
14934           if ((disp & 0x80) != 0)
14935             disp -= 0x100;
14936           if (vex.evex && shift > 0)
14937             disp <<= shift;
14938           break;
14939         case 2:
14940           disp = get32s ();
14941           break;
14942         }
14943
14944       /* In 32bit mode, we need index register to tell [offset] from
14945          [eiz*1 + offset].  */
14946       needindex = (havesib
14947                    && !havebase
14948                    && !haveindex
14949                    && address_mode == mode_32bit);
14950       havedisp = (havebase
14951                   || needindex
14952                   || (havesib && (haveindex || scale != 0)));
14953
14954       if (!intel_syntax)
14955         if (modrm.mod != 0 || base == 5)
14956           {
14957             if (havedisp || riprel)
14958               print_displacement (scratchbuf, disp);
14959             else
14960               print_operand_value (scratchbuf, 1, disp);
14961             oappend (scratchbuf);
14962             if (riprel)
14963               {
14964                 set_op (disp, 1);
14965                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14966               }
14967           }
14968
14969       if ((havebase || haveindex || riprel)
14970           && (bytemode != v_bnd_mode)
14971           && (bytemode != bnd_mode))
14972         used_prefixes |= PREFIX_ADDR;
14973
14974       if (havedisp || (intel_syntax && riprel))
14975         {
14976           *obufp++ = open_char;
14977           if (intel_syntax && riprel)
14978             {
14979               set_op (disp, 1);
14980               oappend (sizeflag & AFLAG ? "rip" : "eip");
14981             }
14982           *obufp = '\0';
14983           if (havebase)
14984             oappend (address_mode == mode_64bit && !addr32flag
14985                      ? names64[rbase] : names32[rbase]);
14986           if (havesib)
14987             {
14988               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14989                  print index to tell base + index from base.  */
14990               if (scale != 0
14991                   || needindex
14992                   || haveindex
14993                   || (havebase && base != ESP_REG_NUM))
14994                 {
14995                   if (!intel_syntax || havebase)
14996                     {
14997                       *obufp++ = separator_char;
14998                       *obufp = '\0';
14999                     }
15000                   if (haveindex)
15001                     oappend (address_mode == mode_64bit && !addr32flag
15002                              ? indexes64[vindex] : indexes32[vindex]);
15003                   else
15004                     oappend (address_mode == mode_64bit && !addr32flag
15005                              ? index64 : index32);
15006
15007                   *obufp++ = scale_char;
15008                   *obufp = '\0';
15009                   sprintf (scratchbuf, "%d", 1 << scale);
15010                   oappend (scratchbuf);
15011                 }
15012             }
15013           if (intel_syntax
15014               && (disp || modrm.mod != 0 || base == 5))
15015             {
15016               if (!havedisp || (bfd_signed_vma) disp >= 0)
15017                 {
15018                   *obufp++ = '+';
15019                   *obufp = '\0';
15020                 }
15021               else if (modrm.mod != 1 && disp != -disp)
15022                 {
15023                   *obufp++ = '-';
15024                   *obufp = '\0';
15025                   disp = - (bfd_signed_vma) disp;
15026                 }
15027
15028               if (havedisp)
15029                 print_displacement (scratchbuf, disp);
15030               else
15031                 print_operand_value (scratchbuf, 1, disp);
15032               oappend (scratchbuf);
15033             }
15034
15035           *obufp++ = close_char;
15036           *obufp = '\0';
15037         }
15038       else if (intel_syntax)
15039         {
15040           if (modrm.mod != 0 || base == 5)
15041             {
15042               if (!active_seg_prefix)
15043                 {
15044                   oappend (names_seg[ds_reg - es_reg]);
15045                   oappend (":");
15046                 }
15047               print_operand_value (scratchbuf, 1, disp);
15048               oappend (scratchbuf);
15049             }
15050         }
15051     }
15052   else
15053     {
15054       /* 16 bit address mode */
15055       used_prefixes |= prefixes & PREFIX_ADDR;
15056       switch (modrm.mod)
15057         {
15058         case 0:
15059           if (modrm.rm == 6)
15060             {
15061               disp = get16 ();
15062               if ((disp & 0x8000) != 0)
15063                 disp -= 0x10000;
15064             }
15065           break;
15066         case 1:
15067           FETCH_DATA (the_info, codep + 1);
15068           disp = *codep++;
15069           if ((disp & 0x80) != 0)
15070             disp -= 0x100;
15071           break;
15072         case 2:
15073           disp = get16 ();
15074           if ((disp & 0x8000) != 0)
15075             disp -= 0x10000;
15076           break;
15077         }
15078
15079       if (!intel_syntax)
15080         if (modrm.mod != 0 || modrm.rm == 6)
15081           {
15082             print_displacement (scratchbuf, disp);
15083             oappend (scratchbuf);
15084           }
15085
15086       if (modrm.mod != 0 || modrm.rm != 6)
15087         {
15088           *obufp++ = open_char;
15089           *obufp = '\0';
15090           oappend (index16[modrm.rm]);
15091           if (intel_syntax
15092               && (disp || modrm.mod != 0 || modrm.rm == 6))
15093             {
15094               if ((bfd_signed_vma) disp >= 0)
15095                 {
15096                   *obufp++ = '+';
15097                   *obufp = '\0';
15098                 }
15099               else if (modrm.mod != 1)
15100                 {
15101                   *obufp++ = '-';
15102                   *obufp = '\0';
15103                   disp = - (bfd_signed_vma) disp;
15104                 }
15105
15106               print_displacement (scratchbuf, disp);
15107               oappend (scratchbuf);
15108             }
15109
15110           *obufp++ = close_char;
15111           *obufp = '\0';
15112         }
15113       else if (intel_syntax)
15114         {
15115           if (!active_seg_prefix)
15116             {
15117               oappend (names_seg[ds_reg - es_reg]);
15118               oappend (":");
15119             }
15120           print_operand_value (scratchbuf, 1, disp & 0xffff);
15121           oappend (scratchbuf);
15122         }
15123     }
15124   if (vex.evex && vex.b
15125       && (bytemode == x_mode
15126           || bytemode == xmmq_mode
15127           || bytemode == evex_half_bcst_xmmq_mode))
15128     {
15129       if (vex.w
15130           || bytemode == xmmq_mode
15131           || bytemode == evex_half_bcst_xmmq_mode)
15132         {
15133           switch (vex.length)
15134             {
15135             case 128:
15136               oappend ("{1to2}");
15137               break;
15138             case 256:
15139               oappend ("{1to4}");
15140               break;
15141             case 512:
15142               oappend ("{1to8}");
15143               break;
15144             default:
15145               abort ();
15146             }
15147         }
15148       else
15149         {
15150           switch (vex.length)
15151             {
15152             case 128:
15153               oappend ("{1to4}");
15154               break;
15155             case 256:
15156               oappend ("{1to8}");
15157               break;
15158             case 512:
15159               oappend ("{1to16}");
15160               break;
15161             default:
15162               abort ();
15163             }
15164         }
15165     }
15166 }
15167
15168 static void
15169 OP_E (int bytemode, int sizeflag)
15170 {
15171   /* Skip mod/rm byte.  */
15172   MODRM_CHECK;
15173   codep++;
15174
15175   if (modrm.mod == 3)
15176     OP_E_register (bytemode, sizeflag);
15177   else
15178     OP_E_memory (bytemode, sizeflag);
15179 }
15180
15181 static void
15182 OP_G (int bytemode, int sizeflag)
15183 {
15184   int add = 0;
15185   USED_REX (REX_R);
15186   if (rex & REX_R)
15187     add += 8;
15188   switch (bytemode)
15189     {
15190     case b_mode:
15191       USED_REX (0);
15192       if (rex)
15193         oappend (names8rex[modrm.reg + add]);
15194       else
15195         oappend (names8[modrm.reg + add]);
15196       break;
15197     case w_mode:
15198       oappend (names16[modrm.reg + add]);
15199       break;
15200     case d_mode:
15201     case db_mode:
15202     case dw_mode:
15203       oappend (names32[modrm.reg + add]);
15204       break;
15205     case q_mode:
15206       oappend (names64[modrm.reg + add]);
15207       break;
15208     case bnd_mode:
15209       oappend (names_bnd[modrm.reg]);
15210       break;
15211     case v_mode:
15212     case dq_mode:
15213     case dqb_mode:
15214     case dqd_mode:
15215     case dqw_mode:
15216     case dqw_swap_mode:
15217       USED_REX (REX_W);
15218       if (rex & REX_W)
15219         oappend (names64[modrm.reg + add]);
15220       else
15221         {
15222           if ((sizeflag & DFLAG) || bytemode != v_mode)
15223             oappend (names32[modrm.reg + add]);
15224           else
15225             oappend (names16[modrm.reg + add]);
15226           used_prefixes |= (prefixes & PREFIX_DATA);
15227         }
15228       break;
15229     case m_mode:
15230       if (address_mode == mode_64bit)
15231         oappend (names64[modrm.reg + add]);
15232       else
15233         oappend (names32[modrm.reg + add]);
15234       break;
15235     case mask_bd_mode:
15236     case mask_mode:
15237       oappend (names_mask[modrm.reg + add]);
15238       break;
15239     default:
15240       oappend (INTERNAL_DISASSEMBLER_ERROR);
15241       break;
15242     }
15243 }
15244
15245 static bfd_vma
15246 get64 (void)
15247 {
15248   bfd_vma x;
15249 #ifdef BFD64
15250   unsigned int a;
15251   unsigned int b;
15252
15253   FETCH_DATA (the_info, codep + 8);
15254   a = *codep++ & 0xff;
15255   a |= (*codep++ & 0xff) << 8;
15256   a |= (*codep++ & 0xff) << 16;
15257   a |= (*codep++ & 0xff) << 24;
15258   b = *codep++ & 0xff;
15259   b |= (*codep++ & 0xff) << 8;
15260   b |= (*codep++ & 0xff) << 16;
15261   b |= (*codep++ & 0xff) << 24;
15262   x = a + ((bfd_vma) b << 32);
15263 #else
15264   abort ();
15265   x = 0;
15266 #endif
15267   return x;
15268 }
15269
15270 static bfd_signed_vma
15271 get32 (void)
15272 {
15273   bfd_signed_vma x = 0;
15274
15275   FETCH_DATA (the_info, codep + 4);
15276   x = *codep++ & (bfd_signed_vma) 0xff;
15277   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15278   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15279   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15280   return x;
15281 }
15282
15283 static bfd_signed_vma
15284 get32s (void)
15285 {
15286   bfd_signed_vma x = 0;
15287
15288   FETCH_DATA (the_info, codep + 4);
15289   x = *codep++ & (bfd_signed_vma) 0xff;
15290   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15291   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15292   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15293
15294   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15295
15296   return x;
15297 }
15298
15299 static int
15300 get16 (void)
15301 {
15302   int x = 0;
15303
15304   FETCH_DATA (the_info, codep + 2);
15305   x = *codep++ & 0xff;
15306   x |= (*codep++ & 0xff) << 8;
15307   return x;
15308 }
15309
15310 static void
15311 set_op (bfd_vma op, int riprel)
15312 {
15313   op_index[op_ad] = op_ad;
15314   if (address_mode == mode_64bit)
15315     {
15316       op_address[op_ad] = op;
15317       op_riprel[op_ad] = riprel;
15318     }
15319   else
15320     {
15321       /* Mask to get a 32-bit address.  */
15322       op_address[op_ad] = op & 0xffffffff;
15323       op_riprel[op_ad] = riprel & 0xffffffff;
15324     }
15325 }
15326
15327 static void
15328 OP_REG (int code, int sizeflag)
15329 {
15330   const char *s;
15331   int add;
15332
15333   switch (code)
15334     {
15335     case es_reg: case ss_reg: case cs_reg:
15336     case ds_reg: case fs_reg: case gs_reg:
15337       oappend (names_seg[code - es_reg]);
15338       return;
15339     }
15340
15341   USED_REX (REX_B);
15342   if (rex & REX_B)
15343     add = 8;
15344   else
15345     add = 0;
15346
15347   switch (code)
15348     {
15349     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15350     case sp_reg: case bp_reg: case si_reg: case di_reg:
15351       s = names16[code - ax_reg + add];
15352       break;
15353     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15354     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15355       USED_REX (0);
15356       if (rex)
15357         s = names8rex[code - al_reg + add];
15358       else
15359         s = names8[code - al_reg];
15360       break;
15361     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15362     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15363       if (address_mode == mode_64bit
15364           && ((sizeflag & DFLAG) || (rex & REX_W)))
15365         {
15366           s = names64[code - rAX_reg + add];
15367           break;
15368         }
15369       code += eAX_reg - rAX_reg;
15370       /* Fall through.  */
15371     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15372     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15373       USED_REX (REX_W);
15374       if (rex & REX_W)
15375         s = names64[code - eAX_reg + add];
15376       else
15377         {
15378           if (sizeflag & DFLAG)
15379             s = names32[code - eAX_reg + add];
15380           else
15381             s = names16[code - eAX_reg + add];
15382           used_prefixes |= (prefixes & PREFIX_DATA);
15383         }
15384       break;
15385     default:
15386       s = INTERNAL_DISASSEMBLER_ERROR;
15387       break;
15388     }
15389   oappend (s);
15390 }
15391
15392 static void
15393 OP_IMREG (int code, int sizeflag)
15394 {
15395   const char *s;
15396
15397   switch (code)
15398     {
15399     case indir_dx_reg:
15400       if (intel_syntax)
15401         s = "dx";
15402       else
15403         s = "(%dx)";
15404       break;
15405     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15406     case sp_reg: case bp_reg: case si_reg: case di_reg:
15407       s = names16[code - ax_reg];
15408       break;
15409     case es_reg: case ss_reg: case cs_reg:
15410     case ds_reg: case fs_reg: case gs_reg:
15411       s = names_seg[code - es_reg];
15412       break;
15413     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15414     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15415       USED_REX (0);
15416       if (rex)
15417         s = names8rex[code - al_reg];
15418       else
15419         s = names8[code - al_reg];
15420       break;
15421     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15422     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15423       USED_REX (REX_W);
15424       if (rex & REX_W)
15425         s = names64[code - eAX_reg];
15426       else
15427         {
15428           if (sizeflag & DFLAG)
15429             s = names32[code - eAX_reg];
15430           else
15431             s = names16[code - eAX_reg];
15432           used_prefixes |= (prefixes & PREFIX_DATA);
15433         }
15434       break;
15435     case z_mode_ax_reg:
15436       if ((rex & REX_W) || (sizeflag & DFLAG))
15437         s = *names32;
15438       else
15439         s = *names16;
15440       if (!(rex & REX_W))
15441         used_prefixes |= (prefixes & PREFIX_DATA);
15442       break;
15443     default:
15444       s = INTERNAL_DISASSEMBLER_ERROR;
15445       break;
15446     }
15447   oappend (s);
15448 }
15449
15450 static void
15451 OP_I (int bytemode, int sizeflag)
15452 {
15453   bfd_signed_vma op;
15454   bfd_signed_vma mask = -1;
15455
15456   switch (bytemode)
15457     {
15458     case b_mode:
15459       FETCH_DATA (the_info, codep + 1);
15460       op = *codep++;
15461       mask = 0xff;
15462       break;
15463     case q_mode:
15464       if (address_mode == mode_64bit)
15465         {
15466           op = get32s ();
15467           break;
15468         }
15469       /* Fall through.  */
15470     case v_mode:
15471       USED_REX (REX_W);
15472       if (rex & REX_W)
15473         op = get32s ();
15474       else
15475         {
15476           if (sizeflag & DFLAG)
15477             {
15478               op = get32 ();
15479               mask = 0xffffffff;
15480             }
15481           else
15482             {
15483               op = get16 ();
15484               mask = 0xfffff;
15485             }
15486           used_prefixes |= (prefixes & PREFIX_DATA);
15487         }
15488       break;
15489     case w_mode:
15490       mask = 0xfffff;
15491       op = get16 ();
15492       break;
15493     case const_1_mode:
15494       if (intel_syntax)
15495         oappend ("1");
15496       return;
15497     default:
15498       oappend (INTERNAL_DISASSEMBLER_ERROR);
15499       return;
15500     }
15501
15502   op &= mask;
15503   scratchbuf[0] = '$';
15504   print_operand_value (scratchbuf + 1, 1, op);
15505   oappend_maybe_intel (scratchbuf);
15506   scratchbuf[0] = '\0';
15507 }
15508
15509 static void
15510 OP_I64 (int bytemode, int sizeflag)
15511 {
15512   bfd_signed_vma op;
15513   bfd_signed_vma mask = -1;
15514
15515   if (address_mode != mode_64bit)
15516     {
15517       OP_I (bytemode, sizeflag);
15518       return;
15519     }
15520
15521   switch (bytemode)
15522     {
15523     case b_mode:
15524       FETCH_DATA (the_info, codep + 1);
15525       op = *codep++;
15526       mask = 0xff;
15527       break;
15528     case v_mode:
15529       USED_REX (REX_W);
15530       if (rex & REX_W)
15531         op = get64 ();
15532       else
15533         {
15534           if (sizeflag & DFLAG)
15535             {
15536               op = get32 ();
15537               mask = 0xffffffff;
15538             }
15539           else
15540             {
15541               op = get16 ();
15542               mask = 0xfffff;
15543             }
15544           used_prefixes |= (prefixes & PREFIX_DATA);
15545         }
15546       break;
15547     case w_mode:
15548       mask = 0xfffff;
15549       op = get16 ();
15550       break;
15551     default:
15552       oappend (INTERNAL_DISASSEMBLER_ERROR);
15553       return;
15554     }
15555
15556   op &= mask;
15557   scratchbuf[0] = '$';
15558   print_operand_value (scratchbuf + 1, 1, op);
15559   oappend_maybe_intel (scratchbuf);
15560   scratchbuf[0] = '\0';
15561 }
15562
15563 static void
15564 OP_sI (int bytemode, int sizeflag)
15565 {
15566   bfd_signed_vma op;
15567
15568   switch (bytemode)
15569     {
15570     case b_mode:
15571     case b_T_mode:
15572       FETCH_DATA (the_info, codep + 1);
15573       op = *codep++;
15574       if ((op & 0x80) != 0)
15575         op -= 0x100;
15576       if (bytemode == b_T_mode)
15577         {
15578           if (address_mode != mode_64bit
15579               || !((sizeflag & DFLAG) || (rex & REX_W)))
15580             {
15581               /* The operand-size prefix is overridden by a REX prefix.  */
15582               if ((sizeflag & DFLAG) || (rex & REX_W))
15583                 op &= 0xffffffff;
15584               else
15585                 op &= 0xffff;
15586           }
15587         }
15588       else
15589         {
15590           if (!(rex & REX_W))
15591             {
15592               if (sizeflag & DFLAG)
15593                 op &= 0xffffffff;
15594               else
15595                 op &= 0xffff;
15596             }
15597         }
15598       break;
15599     case v_mode:
15600       /* The operand-size prefix is overridden by a REX prefix.  */
15601       if ((sizeflag & DFLAG) || (rex & REX_W))
15602         op = get32s ();
15603       else
15604         op = get16 ();
15605       break;
15606     default:
15607       oappend (INTERNAL_DISASSEMBLER_ERROR);
15608       return;
15609     }
15610
15611   scratchbuf[0] = '$';
15612   print_operand_value (scratchbuf + 1, 1, op);
15613   oappend_maybe_intel (scratchbuf);
15614 }
15615
15616 static void
15617 OP_J (int bytemode, int sizeflag)
15618 {
15619   bfd_vma disp;
15620   bfd_vma mask = -1;
15621   bfd_vma segment = 0;
15622
15623   switch (bytemode)
15624     {
15625     case b_mode:
15626       FETCH_DATA (the_info, codep + 1);
15627       disp = *codep++;
15628       if ((disp & 0x80) != 0)
15629         disp -= 0x100;
15630       break;
15631     case v_mode:
15632       USED_REX (REX_W);
15633       if ((sizeflag & DFLAG) || (rex & REX_W))
15634         disp = get32s ();
15635       else
15636         {
15637           disp = get16 ();
15638           if ((disp & 0x8000) != 0)
15639             disp -= 0x10000;
15640           /* In 16bit mode, address is wrapped around at 64k within
15641              the same segment.  Otherwise, a data16 prefix on a jump
15642              instruction means that the pc is masked to 16 bits after
15643              the displacement is added!  */
15644           mask = 0xffff;
15645           if ((prefixes & PREFIX_DATA) == 0)
15646             segment = ((start_pc + codep - start_codep)
15647                        & ~((bfd_vma) 0xffff));
15648         }
15649       if (!(rex & REX_W))
15650         used_prefixes |= (prefixes & PREFIX_DATA);
15651       break;
15652     default:
15653       oappend (INTERNAL_DISASSEMBLER_ERROR);
15654       return;
15655     }
15656   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15657   set_op (disp, 0);
15658   print_operand_value (scratchbuf, 1, disp);
15659   oappend (scratchbuf);
15660 }
15661
15662 static void
15663 OP_SEG (int bytemode, int sizeflag)
15664 {
15665   if (bytemode == w_mode)
15666     oappend (names_seg[modrm.reg]);
15667   else
15668     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15669 }
15670
15671 static void
15672 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15673 {
15674   int seg, offset;
15675
15676   if (sizeflag & DFLAG)
15677     {
15678       offset = get32 ();
15679       seg = get16 ();
15680     }
15681   else
15682     {
15683       offset = get16 ();
15684       seg = get16 ();
15685     }
15686   used_prefixes |= (prefixes & PREFIX_DATA);
15687   if (intel_syntax)
15688     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15689   else
15690     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15691   oappend (scratchbuf);
15692 }
15693
15694 static void
15695 OP_OFF (int bytemode, int sizeflag)
15696 {
15697   bfd_vma off;
15698
15699   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15700     intel_operand_size (bytemode, sizeflag);
15701   append_seg ();
15702
15703   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15704     off = get32 ();
15705   else
15706     off = get16 ();
15707
15708   if (intel_syntax)
15709     {
15710       if (!active_seg_prefix)
15711         {
15712           oappend (names_seg[ds_reg - es_reg]);
15713           oappend (":");
15714         }
15715     }
15716   print_operand_value (scratchbuf, 1, off);
15717   oappend (scratchbuf);
15718 }
15719
15720 static void
15721 OP_OFF64 (int bytemode, int sizeflag)
15722 {
15723   bfd_vma off;
15724
15725   if (address_mode != mode_64bit
15726       || (prefixes & PREFIX_ADDR))
15727     {
15728       OP_OFF (bytemode, sizeflag);
15729       return;
15730     }
15731
15732   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15733     intel_operand_size (bytemode, sizeflag);
15734   append_seg ();
15735
15736   off = get64 ();
15737
15738   if (intel_syntax)
15739     {
15740       if (!active_seg_prefix)
15741         {
15742           oappend (names_seg[ds_reg - es_reg]);
15743           oappend (":");
15744         }
15745     }
15746   print_operand_value (scratchbuf, 1, off);
15747   oappend (scratchbuf);
15748 }
15749
15750 static void
15751 ptr_reg (int code, int sizeflag)
15752 {
15753   const char *s;
15754
15755   *obufp++ = open_char;
15756   used_prefixes |= (prefixes & PREFIX_ADDR);
15757   if (address_mode == mode_64bit)
15758     {
15759       if (!(sizeflag & AFLAG))
15760         s = names32[code - eAX_reg];
15761       else
15762         s = names64[code - eAX_reg];
15763     }
15764   else if (sizeflag & AFLAG)
15765     s = names32[code - eAX_reg];
15766   else
15767     s = names16[code - eAX_reg];
15768   oappend (s);
15769   *obufp++ = close_char;
15770   *obufp = 0;
15771 }
15772
15773 static void
15774 OP_ESreg (int code, int sizeflag)
15775 {
15776   if (intel_syntax)
15777     {
15778       switch (codep[-1])
15779         {
15780         case 0x6d:      /* insw/insl */
15781           intel_operand_size (z_mode, sizeflag);
15782           break;
15783         case 0xa5:      /* movsw/movsl/movsq */
15784         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15785         case 0xab:      /* stosw/stosl */
15786         case 0xaf:      /* scasw/scasl */
15787           intel_operand_size (v_mode, sizeflag);
15788           break;
15789         default:
15790           intel_operand_size (b_mode, sizeflag);
15791         }
15792     }
15793   oappend_maybe_intel ("%es:");
15794   ptr_reg (code, sizeflag);
15795 }
15796
15797 static void
15798 OP_DSreg (int code, int sizeflag)
15799 {
15800   if (intel_syntax)
15801     {
15802       switch (codep[-1])
15803         {
15804         case 0x6f:      /* outsw/outsl */
15805           intel_operand_size (z_mode, sizeflag);
15806           break;
15807         case 0xa5:      /* movsw/movsl/movsq */
15808         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15809         case 0xad:      /* lodsw/lodsl/lodsq */
15810           intel_operand_size (v_mode, sizeflag);
15811           break;
15812         default:
15813           intel_operand_size (b_mode, sizeflag);
15814         }
15815     }
15816   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15817      default segment register DS is printed.  */
15818   if (!active_seg_prefix)
15819     active_seg_prefix = PREFIX_DS;
15820   append_seg ();
15821   ptr_reg (code, sizeflag);
15822 }
15823
15824 static void
15825 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15826 {
15827   int add;
15828   if (rex & REX_R)
15829     {
15830       USED_REX (REX_R);
15831       add = 8;
15832     }
15833   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15834     {
15835       all_prefixes[last_lock_prefix] = 0;
15836       used_prefixes |= PREFIX_LOCK;
15837       add = 8;
15838     }
15839   else
15840     add = 0;
15841   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15842   oappend_maybe_intel (scratchbuf);
15843 }
15844
15845 static void
15846 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15847 {
15848   int add;
15849   USED_REX (REX_R);
15850   if (rex & REX_R)
15851     add = 8;
15852   else
15853     add = 0;
15854   if (intel_syntax)
15855     sprintf (scratchbuf, "db%d", modrm.reg + add);
15856   else
15857     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15858   oappend (scratchbuf);
15859 }
15860
15861 static void
15862 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15863 {
15864   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15865   oappend_maybe_intel (scratchbuf);
15866 }
15867
15868 static void
15869 OP_R (int bytemode, int sizeflag)
15870 {
15871   /* Skip mod/rm byte.  */
15872   MODRM_CHECK;
15873   codep++;
15874   OP_E_register (bytemode, sizeflag);
15875 }
15876
15877 static void
15878 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15879 {
15880   int reg = modrm.reg;
15881   const char **names;
15882
15883   used_prefixes |= (prefixes & PREFIX_DATA);
15884   if (prefixes & PREFIX_DATA)
15885     {
15886       names = names_xmm;
15887       USED_REX (REX_R);
15888       if (rex & REX_R)
15889         reg += 8;
15890     }
15891   else
15892     names = names_mm;
15893   oappend (names[reg]);
15894 }
15895
15896 static void
15897 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15898 {
15899   int reg = modrm.reg;
15900   const char **names;
15901
15902   USED_REX (REX_R);
15903   if (rex & REX_R)
15904     reg += 8;
15905   if (vex.evex)
15906     {
15907       if (!vex.r)
15908         reg += 16;
15909     }
15910
15911   if (need_vex
15912       && bytemode != xmm_mode
15913       && bytemode != xmmq_mode
15914       && bytemode != evex_half_bcst_xmmq_mode
15915       && bytemode != ymm_mode
15916       && bytemode != scalar_mode)
15917     {
15918       switch (vex.length)
15919         {
15920         case 128:
15921           names = names_xmm;
15922           break;
15923         case 256:
15924           if (vex.w
15925               || (bytemode != vex_vsib_q_w_dq_mode
15926                   && bytemode != vex_vsib_q_w_d_mode))
15927             names = names_ymm;
15928           else
15929             names = names_xmm;
15930           break;
15931         case 512:
15932           names = names_zmm;
15933           break;
15934         default:
15935           abort ();
15936         }
15937     }
15938   else if (bytemode == xmmq_mode
15939            || bytemode == evex_half_bcst_xmmq_mode)
15940     {
15941       switch (vex.length)
15942         {
15943         case 128:
15944         case 256:
15945           names = names_xmm;
15946           break;
15947         case 512:
15948           names = names_ymm;
15949           break;
15950         default:
15951           abort ();
15952         }
15953     }
15954   else if (bytemode == ymm_mode)
15955     names = names_ymm;
15956   else
15957     names = names_xmm;
15958   oappend (names[reg]);
15959 }
15960
15961 static void
15962 OP_EM (int bytemode, int sizeflag)
15963 {
15964   int reg;
15965   const char **names;
15966
15967   if (modrm.mod != 3)
15968     {
15969       if (intel_syntax
15970           && (bytemode == v_mode || bytemode == v_swap_mode))
15971         {
15972           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15973           used_prefixes |= (prefixes & PREFIX_DATA);
15974         }
15975       OP_E (bytemode, sizeflag);
15976       return;
15977     }
15978
15979   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15980     swap_operand ();
15981
15982   /* Skip mod/rm byte.  */
15983   MODRM_CHECK;
15984   codep++;
15985   used_prefixes |= (prefixes & PREFIX_DATA);
15986   reg = modrm.rm;
15987   if (prefixes & PREFIX_DATA)
15988     {
15989       names = names_xmm;
15990       USED_REX (REX_B);
15991       if (rex & REX_B)
15992         reg += 8;
15993     }
15994   else
15995     names = names_mm;
15996   oappend (names[reg]);
15997 }
15998
15999 /* cvt* are the only instructions in sse2 which have
16000    both SSE and MMX operands and also have 0x66 prefix
16001    in their opcode. 0x66 was originally used to differentiate
16002    between SSE and MMX instruction(operands). So we have to handle the
16003    cvt* separately using OP_EMC and OP_MXC */
16004 static void
16005 OP_EMC (int bytemode, int sizeflag)
16006 {
16007   if (modrm.mod != 3)
16008     {
16009       if (intel_syntax && bytemode == v_mode)
16010         {
16011           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16012           used_prefixes |= (prefixes & PREFIX_DATA);
16013         }
16014       OP_E (bytemode, sizeflag);
16015       return;
16016     }
16017
16018   /* Skip mod/rm byte.  */
16019   MODRM_CHECK;
16020   codep++;
16021   used_prefixes |= (prefixes & PREFIX_DATA);
16022   oappend (names_mm[modrm.rm]);
16023 }
16024
16025 static void
16026 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16027 {
16028   used_prefixes |= (prefixes & PREFIX_DATA);
16029   oappend (names_mm[modrm.reg]);
16030 }
16031
16032 static void
16033 OP_EX (int bytemode, int sizeflag)
16034 {
16035   int reg;
16036   const char **names;
16037
16038   /* Skip mod/rm byte.  */
16039   MODRM_CHECK;
16040   codep++;
16041
16042   if (modrm.mod != 3)
16043     {
16044       OP_E_memory (bytemode, sizeflag);
16045       return;
16046     }
16047
16048   reg = modrm.rm;
16049   USED_REX (REX_B);
16050   if (rex & REX_B)
16051     reg += 8;
16052   if (vex.evex)
16053     {
16054       USED_REX (REX_X);
16055       if ((rex & REX_X))
16056         reg += 16;
16057     }
16058
16059   if ((sizeflag & SUFFIX_ALWAYS)
16060       && (bytemode == x_swap_mode
16061           || bytemode == d_swap_mode
16062           || bytemode == dqw_swap_mode
16063           || bytemode == d_scalar_swap_mode
16064           || bytemode == q_swap_mode
16065           || bytemode == q_scalar_swap_mode))
16066     swap_operand ();
16067
16068   if (need_vex
16069       && bytemode != xmm_mode
16070       && bytemode != xmmdw_mode
16071       && bytemode != xmmqd_mode
16072       && bytemode != xmm_mb_mode
16073       && bytemode != xmm_mw_mode
16074       && bytemode != xmm_md_mode
16075       && bytemode != xmm_mq_mode
16076       && bytemode != xmm_mdq_mode
16077       && bytemode != xmmq_mode
16078       && bytemode != evex_half_bcst_xmmq_mode
16079       && bytemode != ymm_mode
16080       && bytemode != d_scalar_mode
16081       && bytemode != d_scalar_swap_mode
16082       && bytemode != q_scalar_mode
16083       && bytemode != q_scalar_swap_mode
16084       && bytemode != vex_scalar_w_dq_mode)
16085     {
16086       switch (vex.length)
16087         {
16088         case 128:
16089           names = names_xmm;
16090           break;
16091         case 256:
16092           names = names_ymm;
16093           break;
16094         case 512:
16095           names = names_zmm;
16096           break;
16097         default:
16098           abort ();
16099         }
16100     }
16101   else if (bytemode == xmmq_mode
16102            || bytemode == evex_half_bcst_xmmq_mode)
16103     {
16104       switch (vex.length)
16105         {
16106         case 128:
16107         case 256:
16108           names = names_xmm;
16109           break;
16110         case 512:
16111           names = names_ymm;
16112           break;
16113         default:
16114           abort ();
16115         }
16116     }
16117   else if (bytemode == ymm_mode)
16118     names = names_ymm;
16119   else
16120     names = names_xmm;
16121   oappend (names[reg]);
16122 }
16123
16124 static void
16125 OP_MS (int bytemode, int sizeflag)
16126 {
16127   if (modrm.mod == 3)
16128     OP_EM (bytemode, sizeflag);
16129   else
16130     BadOp ();
16131 }
16132
16133 static void
16134 OP_XS (int bytemode, int sizeflag)
16135 {
16136   if (modrm.mod == 3)
16137     OP_EX (bytemode, sizeflag);
16138   else
16139     BadOp ();
16140 }
16141
16142 static void
16143 OP_M (int bytemode, int sizeflag)
16144 {
16145   if (modrm.mod == 3)
16146     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16147     BadOp ();
16148   else
16149     OP_E (bytemode, sizeflag);
16150 }
16151
16152 static void
16153 OP_0f07 (int bytemode, int sizeflag)
16154 {
16155   if (modrm.mod != 3 || modrm.rm != 0)
16156     BadOp ();
16157   else
16158     OP_E (bytemode, sizeflag);
16159 }
16160
16161 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16162    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16163
16164 static void
16165 NOP_Fixup1 (int bytemode, int sizeflag)
16166 {
16167   if ((prefixes & PREFIX_DATA) != 0
16168       || (rex != 0
16169           && rex != 0x48
16170           && address_mode == mode_64bit))
16171     OP_REG (bytemode, sizeflag);
16172   else
16173     strcpy (obuf, "nop");
16174 }
16175
16176 static void
16177 NOP_Fixup2 (int bytemode, int sizeflag)
16178 {
16179   if ((prefixes & PREFIX_DATA) != 0
16180       || (rex != 0
16181           && rex != 0x48
16182           && address_mode == mode_64bit))
16183     OP_IMREG (bytemode, sizeflag);
16184 }
16185
16186 static const char *const Suffix3DNow[] = {
16187 /* 00 */        NULL,           NULL,           NULL,           NULL,
16188 /* 04 */        NULL,           NULL,           NULL,           NULL,
16189 /* 08 */        NULL,           NULL,           NULL,           NULL,
16190 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16191 /* 10 */        NULL,           NULL,           NULL,           NULL,
16192 /* 14 */        NULL,           NULL,           NULL,           NULL,
16193 /* 18 */        NULL,           NULL,           NULL,           NULL,
16194 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16195 /* 20 */        NULL,           NULL,           NULL,           NULL,
16196 /* 24 */        NULL,           NULL,           NULL,           NULL,
16197 /* 28 */        NULL,           NULL,           NULL,           NULL,
16198 /* 2C */        NULL,           NULL,           NULL,           NULL,
16199 /* 30 */        NULL,           NULL,           NULL,           NULL,
16200 /* 34 */        NULL,           NULL,           NULL,           NULL,
16201 /* 38 */        NULL,           NULL,           NULL,           NULL,
16202 /* 3C */        NULL,           NULL,           NULL,           NULL,
16203 /* 40 */        NULL,           NULL,           NULL,           NULL,
16204 /* 44 */        NULL,           NULL,           NULL,           NULL,
16205 /* 48 */        NULL,           NULL,           NULL,           NULL,
16206 /* 4C */        NULL,           NULL,           NULL,           NULL,
16207 /* 50 */        NULL,           NULL,           NULL,           NULL,
16208 /* 54 */        NULL,           NULL,           NULL,           NULL,
16209 /* 58 */        NULL,           NULL,           NULL,           NULL,
16210 /* 5C */        NULL,           NULL,           NULL,           NULL,
16211 /* 60 */        NULL,           NULL,           NULL,           NULL,
16212 /* 64 */        NULL,           NULL,           NULL,           NULL,
16213 /* 68 */        NULL,           NULL,           NULL,           NULL,
16214 /* 6C */        NULL,           NULL,           NULL,           NULL,
16215 /* 70 */        NULL,           NULL,           NULL,           NULL,
16216 /* 74 */        NULL,           NULL,           NULL,           NULL,
16217 /* 78 */        NULL,           NULL,           NULL,           NULL,
16218 /* 7C */        NULL,           NULL,           NULL,           NULL,
16219 /* 80 */        NULL,           NULL,           NULL,           NULL,
16220 /* 84 */        NULL,           NULL,           NULL,           NULL,
16221 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16222 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16223 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16224 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16225 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16226 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16227 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16228 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16229 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16230 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16231 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16232 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16233 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16234 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16235 /* C0 */        NULL,           NULL,           NULL,           NULL,
16236 /* C4 */        NULL,           NULL,           NULL,           NULL,
16237 /* C8 */        NULL,           NULL,           NULL,           NULL,
16238 /* CC */        NULL,           NULL,           NULL,           NULL,
16239 /* D0 */        NULL,           NULL,           NULL,           NULL,
16240 /* D4 */        NULL,           NULL,           NULL,           NULL,
16241 /* D8 */        NULL,           NULL,           NULL,           NULL,
16242 /* DC */        NULL,           NULL,           NULL,           NULL,
16243 /* E0 */        NULL,           NULL,           NULL,           NULL,
16244 /* E4 */        NULL,           NULL,           NULL,           NULL,
16245 /* E8 */        NULL,           NULL,           NULL,           NULL,
16246 /* EC */        NULL,           NULL,           NULL,           NULL,
16247 /* F0 */        NULL,           NULL,           NULL,           NULL,
16248 /* F4 */        NULL,           NULL,           NULL,           NULL,
16249 /* F8 */        NULL,           NULL,           NULL,           NULL,
16250 /* FC */        NULL,           NULL,           NULL,           NULL,
16251 };
16252
16253 static void
16254 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16255 {
16256   const char *mnemonic;
16257
16258   FETCH_DATA (the_info, codep + 1);
16259   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16260      place where an 8-bit immediate would normally go.  ie. the last
16261      byte of the instruction.  */
16262   obufp = mnemonicendp;
16263   mnemonic = Suffix3DNow[*codep++ & 0xff];
16264   if (mnemonic)
16265     oappend (mnemonic);
16266   else
16267     {
16268       /* Since a variable sized modrm/sib chunk is between the start
16269          of the opcode (0x0f0f) and the opcode suffix, we need to do
16270          all the modrm processing first, and don't know until now that
16271          we have a bad opcode.  This necessitates some cleaning up.  */
16272       op_out[0][0] = '\0';
16273       op_out[1][0] = '\0';
16274       BadOp ();
16275     }
16276   mnemonicendp = obufp;
16277 }
16278
16279 static struct op simd_cmp_op[] =
16280 {
16281   { STRING_COMMA_LEN ("eq") },
16282   { STRING_COMMA_LEN ("lt") },
16283   { STRING_COMMA_LEN ("le") },
16284   { STRING_COMMA_LEN ("unord") },
16285   { STRING_COMMA_LEN ("neq") },
16286   { STRING_COMMA_LEN ("nlt") },
16287   { STRING_COMMA_LEN ("nle") },
16288   { STRING_COMMA_LEN ("ord") }
16289 };
16290
16291 static void
16292 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16293 {
16294   unsigned int cmp_type;
16295
16296   FETCH_DATA (the_info, codep + 1);
16297   cmp_type = *codep++ & 0xff;
16298   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16299     {
16300       char suffix [3];
16301       char *p = mnemonicendp - 2;
16302       suffix[0] = p[0];
16303       suffix[1] = p[1];
16304       suffix[2] = '\0';
16305       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16306       mnemonicendp += simd_cmp_op[cmp_type].len;
16307     }
16308   else
16309     {
16310       /* We have a reserved extension byte.  Output it directly.  */
16311       scratchbuf[0] = '$';
16312       print_operand_value (scratchbuf + 1, 1, cmp_type);
16313       oappend_maybe_intel (scratchbuf);
16314       scratchbuf[0] = '\0';
16315     }
16316 }
16317
16318 static void
16319 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16320           int sizeflag ATTRIBUTE_UNUSED)
16321 {
16322   /* mwait %eax,%ecx  */
16323   if (!intel_syntax)
16324     {
16325       const char **names = (address_mode == mode_64bit
16326                             ? names64 : names32);
16327       strcpy (op_out[0], names[0]);
16328       strcpy (op_out[1], names[1]);
16329       two_source_ops = 1;
16330     }
16331   /* Skip mod/rm byte.  */
16332   MODRM_CHECK;
16333   codep++;
16334 }
16335
16336 static void
16337 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16338             int sizeflag ATTRIBUTE_UNUSED)
16339 {
16340   /* monitor %eax,%ecx,%edx"  */
16341   if (!intel_syntax)
16342     {
16343       const char **op1_names;
16344       const char **names = (address_mode == mode_64bit
16345                             ? names64 : names32);
16346
16347       if (!(prefixes & PREFIX_ADDR))
16348         op1_names = (address_mode == mode_16bit
16349                      ? names16 : names);
16350       else
16351         {
16352           /* Remove "addr16/addr32".  */
16353           all_prefixes[last_addr_prefix] = 0;
16354           op1_names = (address_mode != mode_32bit
16355                        ? names32 : names16);
16356           used_prefixes |= PREFIX_ADDR;
16357         }
16358       strcpy (op_out[0], op1_names[0]);
16359       strcpy (op_out[1], names[1]);
16360       strcpy (op_out[2], names[2]);
16361       two_source_ops = 1;
16362     }
16363   /* Skip mod/rm byte.  */
16364   MODRM_CHECK;
16365   codep++;
16366 }
16367
16368 static void
16369 BadOp (void)
16370 {
16371   /* Throw away prefixes and 1st. opcode byte.  */
16372   codep = insn_codep + 1;
16373   oappend ("(bad)");
16374 }
16375
16376 static void
16377 REP_Fixup (int bytemode, int sizeflag)
16378 {
16379   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16380      lods and stos.  */
16381   if (prefixes & PREFIX_REPZ)
16382     all_prefixes[last_repz_prefix] = REP_PREFIX;
16383
16384   switch (bytemode)
16385     {
16386     case al_reg:
16387     case eAX_reg:
16388     case indir_dx_reg:
16389       OP_IMREG (bytemode, sizeflag);
16390       break;
16391     case eDI_reg:
16392       OP_ESreg (bytemode, sizeflag);
16393       break;
16394     case eSI_reg:
16395       OP_DSreg (bytemode, sizeflag);
16396       break;
16397     default:
16398       abort ();
16399       break;
16400     }
16401 }
16402
16403 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16404    "bnd".  */
16405
16406 static void
16407 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16408 {
16409   if (prefixes & PREFIX_REPNZ)
16410     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16411 }
16412
16413 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16414    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16415  */
16416
16417 static void
16418 HLE_Fixup1 (int bytemode, int sizeflag)
16419 {
16420   if (modrm.mod != 3
16421       && (prefixes & PREFIX_LOCK) != 0)
16422     {
16423       if (prefixes & PREFIX_REPZ)
16424         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16425       if (prefixes & PREFIX_REPNZ)
16426         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16427     }
16428
16429   OP_E (bytemode, sizeflag);
16430 }
16431
16432 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16433    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16434  */
16435
16436 static void
16437 HLE_Fixup2 (int bytemode, int sizeflag)
16438 {
16439   if (modrm.mod != 3)
16440     {
16441       if (prefixes & PREFIX_REPZ)
16442         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16443       if (prefixes & PREFIX_REPNZ)
16444         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16445     }
16446
16447   OP_E (bytemode, sizeflag);
16448 }
16449
16450 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16451    "xrelease" for memory operand.  No check for LOCK prefix.   */
16452
16453 static void
16454 HLE_Fixup3 (int bytemode, int sizeflag)
16455 {
16456   if (modrm.mod != 3
16457       && last_repz_prefix > last_repnz_prefix
16458       && (prefixes & PREFIX_REPZ) != 0)
16459     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16460
16461   OP_E (bytemode, sizeflag);
16462 }
16463
16464 static void
16465 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16466 {
16467   USED_REX (REX_W);
16468   if (rex & REX_W)
16469     {
16470       /* Change cmpxchg8b to cmpxchg16b.  */
16471       char *p = mnemonicendp - 2;
16472       mnemonicendp = stpcpy (p, "16b");
16473       bytemode = o_mode;
16474     }
16475   else if ((prefixes & PREFIX_LOCK) != 0)
16476     {
16477       if (prefixes & PREFIX_REPZ)
16478         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16479       if (prefixes & PREFIX_REPNZ)
16480         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16481     }
16482
16483   OP_M (bytemode, sizeflag);
16484 }
16485
16486 static void
16487 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16488 {
16489   const char **names;
16490
16491   if (need_vex)
16492     {
16493       switch (vex.length)
16494         {
16495         case 128:
16496           names = names_xmm;
16497           break;
16498         case 256:
16499           names = names_ymm;
16500           break;
16501         default:
16502           abort ();
16503         }
16504     }
16505   else
16506     names = names_xmm;
16507   oappend (names[reg]);
16508 }
16509
16510 static void
16511 CRC32_Fixup (int bytemode, int sizeflag)
16512 {
16513   /* Add proper suffix to "crc32".  */
16514   char *p = mnemonicendp;
16515
16516   switch (bytemode)
16517     {
16518     case b_mode:
16519       if (intel_syntax)
16520         goto skip;
16521
16522       *p++ = 'b';
16523       break;
16524     case v_mode:
16525       if (intel_syntax)
16526         goto skip;
16527
16528       USED_REX (REX_W);
16529       if (rex & REX_W)
16530         *p++ = 'q';
16531       else
16532         {
16533           if (sizeflag & DFLAG)
16534             *p++ = 'l';
16535           else
16536             *p++ = 'w';
16537           used_prefixes |= (prefixes & PREFIX_DATA);
16538         }
16539       break;
16540     default:
16541       oappend (INTERNAL_DISASSEMBLER_ERROR);
16542       break;
16543     }
16544   mnemonicendp = p;
16545   *p = '\0';
16546
16547 skip:
16548   if (modrm.mod == 3)
16549     {
16550       int add;
16551
16552       /* Skip mod/rm byte.  */
16553       MODRM_CHECK;
16554       codep++;
16555
16556       USED_REX (REX_B);
16557       add = (rex & REX_B) ? 8 : 0;
16558       if (bytemode == b_mode)
16559         {
16560           USED_REX (0);
16561           if (rex)
16562             oappend (names8rex[modrm.rm + add]);
16563           else
16564             oappend (names8[modrm.rm + add]);
16565         }
16566       else
16567         {
16568           USED_REX (REX_W);
16569           if (rex & REX_W)
16570             oappend (names64[modrm.rm + add]);
16571           else if ((prefixes & PREFIX_DATA))
16572             oappend (names16[modrm.rm + add]);
16573           else
16574             oappend (names32[modrm.rm + add]);
16575         }
16576     }
16577   else
16578     OP_E (bytemode, sizeflag);
16579 }
16580
16581 static void
16582 FXSAVE_Fixup (int bytemode, int sizeflag)
16583 {
16584   /* Add proper suffix to "fxsave" and "fxrstor".  */
16585   USED_REX (REX_W);
16586   if (rex & REX_W)
16587     {
16588       char *p = mnemonicendp;
16589       *p++ = '6';
16590       *p++ = '4';
16591       *p = '\0';
16592       mnemonicendp = p;
16593     }
16594   OP_M (bytemode, sizeflag);
16595 }
16596
16597 /* Display the destination register operand for instructions with
16598    VEX. */
16599
16600 static void
16601 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16602 {
16603   int reg;
16604   const char **names;
16605
16606   if (!need_vex)
16607     abort ();
16608
16609   if (!need_vex_reg)
16610     return;
16611
16612   reg = vex.register_specifier;
16613   if (vex.evex)
16614     {
16615       if (!vex.v)
16616         reg += 16;
16617     }
16618
16619   if (bytemode == vex_scalar_mode)
16620     {
16621       oappend (names_xmm[reg]);
16622       return;
16623     }
16624
16625   switch (vex.length)
16626     {
16627     case 128:
16628       switch (bytemode)
16629         {
16630         case vex_mode:
16631         case vex128_mode:
16632         case vex_vsib_q_w_dq_mode:
16633         case vex_vsib_q_w_d_mode:
16634           names = names_xmm;
16635           break;
16636         case dq_mode:
16637           if (vex.w)
16638             names = names64;
16639           else
16640             names = names32;
16641           break;
16642         case mask_bd_mode:
16643         case mask_mode:
16644           names = names_mask;
16645           break;
16646         default:
16647           abort ();
16648           return;
16649         }
16650       break;
16651     case 256:
16652       switch (bytemode)
16653         {
16654         case vex_mode:
16655         case vex256_mode:
16656           names = names_ymm;
16657           break;
16658         case vex_vsib_q_w_dq_mode:
16659         case vex_vsib_q_w_d_mode:
16660           names = vex.w ? names_ymm : names_xmm;
16661           break;
16662         case mask_bd_mode:
16663         case mask_mode:
16664           names = names_mask;
16665           break;
16666         default:
16667           abort ();
16668           return;
16669         }
16670       break;
16671     case 512:
16672       names = names_zmm;
16673       break;
16674     default:
16675       abort ();
16676       break;
16677     }
16678   oappend (names[reg]);
16679 }
16680
16681 /* Get the VEX immediate byte without moving codep.  */
16682
16683 static unsigned char
16684 get_vex_imm8 (int sizeflag, int opnum)
16685 {
16686   int bytes_before_imm = 0;
16687
16688   if (modrm.mod != 3)
16689     {
16690       /* There are SIB/displacement bytes.  */
16691       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16692         {
16693           /* 32/64 bit address mode */
16694           int base = modrm.rm;
16695
16696           /* Check SIB byte.  */
16697           if (base == 4)
16698             {
16699               FETCH_DATA (the_info, codep + 1);
16700               base = *codep & 7;
16701               /* When decoding the third source, don't increase
16702                  bytes_before_imm as this has already been incremented
16703                  by one in OP_E_memory while decoding the second
16704                  source operand.  */
16705               if (opnum == 0)
16706                 bytes_before_imm++;
16707             }
16708
16709           /* Don't increase bytes_before_imm when decoding the third source,
16710              it has already been incremented by OP_E_memory while decoding
16711              the second source operand.  */
16712           if (opnum == 0)
16713             {
16714               switch (modrm.mod)
16715                 {
16716                   case 0:
16717                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16718                        SIB == 5, there is a 4 byte displacement.  */
16719                     if (base != 5)
16720                       /* No displacement. */
16721                       break;
16722                   case 2:
16723                     /* 4 byte displacement.  */
16724                     bytes_before_imm += 4;
16725                     break;
16726                   case 1:
16727                     /* 1 byte displacement.  */
16728                     bytes_before_imm++;
16729                     break;
16730                 }
16731             }
16732         }
16733       else
16734         {
16735           /* 16 bit address mode */
16736           /* Don't increase bytes_before_imm when decoding the third source,
16737              it has already been incremented by OP_E_memory while decoding
16738              the second source operand.  */
16739           if (opnum == 0)
16740             {
16741               switch (modrm.mod)
16742                 {
16743                 case 0:
16744                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16745                   if (modrm.rm != 6)
16746                     /* No displacement. */
16747                     break;
16748                 case 2:
16749                   /* 2 byte displacement.  */
16750                   bytes_before_imm += 2;
16751                   break;
16752                 case 1:
16753                   /* 1 byte displacement: when decoding the third source,
16754                      don't increase bytes_before_imm as this has already
16755                      been incremented by one in OP_E_memory while decoding
16756                      the second source operand.  */
16757                   if (opnum == 0)
16758                     bytes_before_imm++;
16759
16760                   break;
16761                 }
16762             }
16763         }
16764     }
16765
16766   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16767   return codep [bytes_before_imm];
16768 }
16769
16770 static void
16771 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16772 {
16773   const char **names;
16774
16775   if (reg == -1 && modrm.mod != 3)
16776     {
16777       OP_E_memory (bytemode, sizeflag);
16778       return;
16779     }
16780   else
16781     {
16782       if (reg == -1)
16783         {
16784           reg = modrm.rm;
16785           USED_REX (REX_B);
16786           if (rex & REX_B)
16787             reg += 8;
16788         }
16789       else if (reg > 7 && address_mode != mode_64bit)
16790         BadOp ();
16791     }
16792
16793   switch (vex.length)
16794     {
16795     case 128:
16796       names = names_xmm;
16797       break;
16798     case 256:
16799       names = names_ymm;
16800       break;
16801     default:
16802       abort ();
16803     }
16804   oappend (names[reg]);
16805 }
16806
16807 static void
16808 OP_EX_VexImmW (int bytemode, int sizeflag)
16809 {
16810   int reg = -1;
16811   static unsigned char vex_imm8;
16812
16813   if (vex_w_done == 0)
16814     {
16815       vex_w_done = 1;
16816
16817       /* Skip mod/rm byte.  */
16818       MODRM_CHECK;
16819       codep++;
16820
16821       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16822
16823       if (vex.w)
16824           reg = vex_imm8 >> 4;
16825
16826       OP_EX_VexReg (bytemode, sizeflag, reg);
16827     }
16828   else if (vex_w_done == 1)
16829     {
16830       vex_w_done = 2;
16831
16832       if (!vex.w)
16833           reg = vex_imm8 >> 4;
16834
16835       OP_EX_VexReg (bytemode, sizeflag, reg);
16836     }
16837   else
16838     {
16839       /* Output the imm8 directly.  */
16840       scratchbuf[0] = '$';
16841       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16842       oappend_maybe_intel (scratchbuf);
16843       scratchbuf[0] = '\0';
16844       codep++;
16845     }
16846 }
16847
16848 static void
16849 OP_Vex_2src (int bytemode, int sizeflag)
16850 {
16851   if (modrm.mod == 3)
16852     {
16853       int reg = modrm.rm;
16854       USED_REX (REX_B);
16855       if (rex & REX_B)
16856         reg += 8;
16857       oappend (names_xmm[reg]);
16858     }
16859   else
16860     {
16861       if (intel_syntax
16862           && (bytemode == v_mode || bytemode == v_swap_mode))
16863         {
16864           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16865           used_prefixes |= (prefixes & PREFIX_DATA);
16866         }
16867       OP_E (bytemode, sizeflag);
16868     }
16869 }
16870
16871 static void
16872 OP_Vex_2src_1 (int bytemode, int sizeflag)
16873 {
16874   if (modrm.mod == 3)
16875     {
16876       /* Skip mod/rm byte.   */
16877       MODRM_CHECK;
16878       codep++;
16879     }
16880
16881   if (vex.w)
16882     oappend (names_xmm[vex.register_specifier]);
16883   else
16884     OP_Vex_2src (bytemode, sizeflag);
16885 }
16886
16887 static void
16888 OP_Vex_2src_2 (int bytemode, int sizeflag)
16889 {
16890   if (vex.w)
16891     OP_Vex_2src (bytemode, sizeflag);
16892   else
16893     oappend (names_xmm[vex.register_specifier]);
16894 }
16895
16896 static void
16897 OP_EX_VexW (int bytemode, int sizeflag)
16898 {
16899   int reg = -1;
16900
16901   if (!vex_w_done)
16902     {
16903       vex_w_done = 1;
16904
16905       /* Skip mod/rm byte.  */
16906       MODRM_CHECK;
16907       codep++;
16908
16909       if (vex.w)
16910         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16911     }
16912   else
16913     {
16914       if (!vex.w)
16915         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16916     }
16917
16918   OP_EX_VexReg (bytemode, sizeflag, reg);
16919 }
16920
16921 static void
16922 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16923              int sizeflag ATTRIBUTE_UNUSED)
16924 {
16925   /* Skip the immediate byte and check for invalid bits.  */
16926   FETCH_DATA (the_info, codep + 1);
16927   if (*codep++ & 0xf)
16928     BadOp ();
16929 }
16930
16931 static void
16932 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16933 {
16934   int reg;
16935   const char **names;
16936
16937   FETCH_DATA (the_info, codep + 1);
16938   reg = *codep++;
16939
16940   if (bytemode != x_mode)
16941     abort ();
16942
16943   if (reg & 0xf)
16944       BadOp ();
16945
16946   reg >>= 4;
16947   if (reg > 7 && address_mode != mode_64bit)
16948     BadOp ();
16949
16950   switch (vex.length)
16951     {
16952     case 128:
16953       names = names_xmm;
16954       break;
16955     case 256:
16956       names = names_ymm;
16957       break;
16958     default:
16959       abort ();
16960     }
16961   oappend (names[reg]);
16962 }
16963
16964 static void
16965 OP_XMM_VexW (int bytemode, int sizeflag)
16966 {
16967   /* Turn off the REX.W bit since it is used for swapping operands
16968      now.  */
16969   rex &= ~REX_W;
16970   OP_XMM (bytemode, sizeflag);
16971 }
16972
16973 static void
16974 OP_EX_Vex (int bytemode, int sizeflag)
16975 {
16976   if (modrm.mod != 3)
16977     {
16978       if (vex.register_specifier != 0)
16979         BadOp ();
16980       need_vex_reg = 0;
16981     }
16982   OP_EX (bytemode, sizeflag);
16983 }
16984
16985 static void
16986 OP_XMM_Vex (int bytemode, int sizeflag)
16987 {
16988   if (modrm.mod != 3)
16989     {
16990       if (vex.register_specifier != 0)
16991         BadOp ();
16992       need_vex_reg = 0;
16993     }
16994   OP_XMM (bytemode, sizeflag);
16995 }
16996
16997 static void
16998 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16999 {
17000   switch (vex.length)
17001     {
17002     case 128:
17003       mnemonicendp = stpcpy (obuf, "vzeroupper");
17004       break;
17005     case 256:
17006       mnemonicendp = stpcpy (obuf, "vzeroall");
17007       break;
17008     default:
17009       abort ();
17010     }
17011 }
17012
17013 static struct op vex_cmp_op[] =
17014 {
17015   { STRING_COMMA_LEN ("eq") },
17016   { STRING_COMMA_LEN ("lt") },
17017   { STRING_COMMA_LEN ("le") },
17018   { STRING_COMMA_LEN ("unord") },
17019   { STRING_COMMA_LEN ("neq") },
17020   { STRING_COMMA_LEN ("nlt") },
17021   { STRING_COMMA_LEN ("nle") },
17022   { STRING_COMMA_LEN ("ord") },
17023   { STRING_COMMA_LEN ("eq_uq") },
17024   { STRING_COMMA_LEN ("nge") },
17025   { STRING_COMMA_LEN ("ngt") },
17026   { STRING_COMMA_LEN ("false") },
17027   { STRING_COMMA_LEN ("neq_oq") },
17028   { STRING_COMMA_LEN ("ge") },
17029   { STRING_COMMA_LEN ("gt") },
17030   { STRING_COMMA_LEN ("true") },
17031   { STRING_COMMA_LEN ("eq_os") },
17032   { STRING_COMMA_LEN ("lt_oq") },
17033   { STRING_COMMA_LEN ("le_oq") },
17034   { STRING_COMMA_LEN ("unord_s") },
17035   { STRING_COMMA_LEN ("neq_us") },
17036   { STRING_COMMA_LEN ("nlt_uq") },
17037   { STRING_COMMA_LEN ("nle_uq") },
17038   { STRING_COMMA_LEN ("ord_s") },
17039   { STRING_COMMA_LEN ("eq_us") },
17040   { STRING_COMMA_LEN ("nge_uq") },
17041   { STRING_COMMA_LEN ("ngt_uq") },
17042   { STRING_COMMA_LEN ("false_os") },
17043   { STRING_COMMA_LEN ("neq_os") },
17044   { STRING_COMMA_LEN ("ge_oq") },
17045   { STRING_COMMA_LEN ("gt_oq") },
17046   { STRING_COMMA_LEN ("true_us") },
17047 };
17048
17049 static void
17050 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17051 {
17052   unsigned int cmp_type;
17053
17054   FETCH_DATA (the_info, codep + 1);
17055   cmp_type = *codep++ & 0xff;
17056   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17057     {
17058       char suffix [3];
17059       char *p = mnemonicendp - 2;
17060       suffix[0] = p[0];
17061       suffix[1] = p[1];
17062       suffix[2] = '\0';
17063       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17064       mnemonicendp += vex_cmp_op[cmp_type].len;
17065     }
17066   else
17067     {
17068       /* We have a reserved extension byte.  Output it directly.  */
17069       scratchbuf[0] = '$';
17070       print_operand_value (scratchbuf + 1, 1, cmp_type);
17071       oappend_maybe_intel (scratchbuf);
17072       scratchbuf[0] = '\0';
17073     }
17074 }
17075
17076 static void
17077 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17078              int sizeflag ATTRIBUTE_UNUSED)
17079 {
17080   unsigned int cmp_type;
17081
17082   if (!vex.evex)
17083     abort ();
17084
17085   FETCH_DATA (the_info, codep + 1);
17086   cmp_type = *codep++ & 0xff;
17087   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17088      If it's the case, print suffix, otherwise - print the immediate.  */
17089   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17090       && cmp_type != 3
17091       && cmp_type != 7)
17092     {
17093       char suffix [3];
17094       char *p = mnemonicendp - 2;
17095
17096       /* vpcmp* can have both one- and two-lettered suffix.  */
17097       if (p[0] == 'p')
17098         {
17099           p++;
17100           suffix[0] = p[0];
17101           suffix[1] = '\0';
17102         }
17103       else
17104         {
17105           suffix[0] = p[0];
17106           suffix[1] = p[1];
17107           suffix[2] = '\0';
17108         }
17109
17110       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17111       mnemonicendp += simd_cmp_op[cmp_type].len;
17112     }
17113   else
17114     {
17115       /* We have a reserved extension byte.  Output it directly.  */
17116       scratchbuf[0] = '$';
17117       print_operand_value (scratchbuf + 1, 1, cmp_type);
17118       oappend_maybe_intel (scratchbuf);
17119       scratchbuf[0] = '\0';
17120     }
17121 }
17122
17123 static const struct op pclmul_op[] =
17124 {
17125   { STRING_COMMA_LEN ("lql") },
17126   { STRING_COMMA_LEN ("hql") },
17127   { STRING_COMMA_LEN ("lqh") },
17128   { STRING_COMMA_LEN ("hqh") }
17129 };
17130
17131 static void
17132 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17133               int sizeflag ATTRIBUTE_UNUSED)
17134 {
17135   unsigned int pclmul_type;
17136
17137   FETCH_DATA (the_info, codep + 1);
17138   pclmul_type = *codep++ & 0xff;
17139   switch (pclmul_type)
17140     {
17141     case 0x10:
17142       pclmul_type = 2;
17143       break;
17144     case 0x11:
17145       pclmul_type = 3;
17146       break;
17147     default:
17148       break;
17149     }
17150   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17151     {
17152       char suffix [4];
17153       char *p = mnemonicendp - 3;
17154       suffix[0] = p[0];
17155       suffix[1] = p[1];
17156       suffix[2] = p[2];
17157       suffix[3] = '\0';
17158       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17159       mnemonicendp += pclmul_op[pclmul_type].len;
17160     }
17161   else
17162     {
17163       /* We have a reserved extension byte.  Output it directly.  */
17164       scratchbuf[0] = '$';
17165       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17166       oappend_maybe_intel (scratchbuf);
17167       scratchbuf[0] = '\0';
17168     }
17169 }
17170
17171 static void
17172 MOVBE_Fixup (int bytemode, int sizeflag)
17173 {
17174   /* Add proper suffix to "movbe".  */
17175   char *p = mnemonicendp;
17176
17177   switch (bytemode)
17178     {
17179     case v_mode:
17180       if (intel_syntax)
17181         goto skip;
17182
17183       USED_REX (REX_W);
17184       if (sizeflag & SUFFIX_ALWAYS)
17185         {
17186           if (rex & REX_W)
17187             *p++ = 'q';
17188           else
17189             {
17190               if (sizeflag & DFLAG)
17191                 *p++ = 'l';
17192               else
17193                 *p++ = 'w';
17194               used_prefixes |= (prefixes & PREFIX_DATA);
17195             }
17196         }
17197       break;
17198     default:
17199       oappend (INTERNAL_DISASSEMBLER_ERROR);
17200       break;
17201     }
17202   mnemonicendp = p;
17203   *p = '\0';
17204
17205 skip:
17206   OP_M (bytemode, sizeflag);
17207 }
17208
17209 static void
17210 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17211 {
17212   int reg;
17213   const char **names;
17214
17215   /* Skip mod/rm byte.  */
17216   MODRM_CHECK;
17217   codep++;
17218
17219   if (vex.w)
17220     names = names64;
17221   else
17222     names = names32;
17223
17224   reg = modrm.rm;
17225   USED_REX (REX_B);
17226   if (rex & REX_B)
17227     reg += 8;
17228
17229   oappend (names[reg]);
17230 }
17231
17232 static void
17233 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17234 {
17235   const char **names;
17236
17237   if (vex.w)
17238     names = names64;
17239   else
17240     names = names32;
17241
17242   oappend (names[vex.register_specifier]);
17243 }
17244
17245 static void
17246 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17247 {
17248   if (!vex.evex
17249       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17250     abort ();
17251
17252   USED_REX (REX_R);
17253   if ((rex & REX_R) != 0 || !vex.r)
17254     {
17255       BadOp ();
17256       return;
17257     }
17258
17259   oappend (names_mask [modrm.reg]);
17260 }
17261
17262 static void
17263 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17264 {
17265   if (!vex.evex
17266       || (bytemode != evex_rounding_mode
17267           && bytemode != evex_sae_mode))
17268     abort ();
17269   if (modrm.mod == 3 && vex.b)
17270     switch (bytemode)
17271       {
17272       case evex_rounding_mode:
17273         oappend (names_rounding[vex.ll]);
17274         break;
17275       case evex_sae_mode:
17276         oappend ("{sae}");
17277         break;
17278       default:
17279         break;
17280       }
17281 }