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x86: simplify decode of opcodes valid with (embedded) 66 prefix only
[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 July 1988
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
34
35 #include "sysdep.h"
36 #include "disassemble.h"
37 #include "opintl.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
41
42 #include <setjmp.h>
43
44 static int print_insn (bfd_vma, disassemble_info *);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma get64 (void);
59 static bfd_signed_vma get32 (void);
60 static bfd_signed_vma get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_R (int, int);
81 static void OP_MMX (int, int);
82 static void OP_XMM (int, int);
83 static void OP_EM (int, int);
84 static void OP_EX (int, int);
85 static void OP_EMC (int,int);
86 static void OP_MXC (int,int);
87 static void OP_MS (int, int);
88 static void OP_XS (int, int);
89 static void OP_M (int, int);
90 static void OP_VEX (int, int);
91 static void OP_VexR (int, int);
92 static void OP_VexW (int, int);
93 static void OP_Rounding (int, int);
94 static void OP_REG_VexI4 (int, int);
95 static void OP_VexI4 (int, int);
96 static void PCLMUL_Fixup (int, int);
97 static void VPCMP_Fixup (int, int);
98 static void VPCOM_Fixup (int, int);
99 static void OP_0f07 (int, int);
100 static void OP_Monitor (int, int);
101 static void OP_Mwait (int, int);
102 static void NOP_Fixup1 (int, int);
103 static void NOP_Fixup2 (int, int);
104 static void OP_3DNowSuffix (int, int);
105 static void CMP_Fixup (int, int);
106 static void BadOp (void);
107 static void REP_Fixup (int, int);
108 static void SEP_Fixup (int, int);
109 static void BND_Fixup (int, int);
110 static void NOTRACK_Fixup (int, int);
111 static void HLE_Fixup1 (int, int);
112 static void HLE_Fixup2 (int, int);
113 static void HLE_Fixup3 (int, int);
114 static void CMPXCHG8B_Fixup (int, int);
115 static void XMM_Fixup (int, int);
116 static void FXSAVE_Fixup (int, int);
117
118 static void MOVSXD_Fixup (int, int);
119
120 static void OP_Mask (int, int);
121
122 struct dis_private {
123 /* Points to first byte not fetched. */
124 bfd_byte *max_fetched;
125 bfd_byte the_buffer[MAX_MNEM_SIZE];
126 bfd_vma insn_start;
127 int orig_sizeflag;
128 OPCODES_SIGJMP_BUF bailout;
129 };
130
131 enum address_mode
132 {
133 mode_16bit,
134 mode_32bit,
135 mode_64bit
136 };
137
138 enum address_mode address_mode;
139
140 /* Flags for the prefixes for the current instruction. See below. */
141 static int prefixes;
142
143 /* REX prefix the current instruction. See below. */
144 static int rex;
145 /* Bits of REX we've already used. */
146 static int rex_used;
147 /* Mark parts used in the REX prefix. When we are testing for
148 empty prefix (for 8bit register REX extension), just mask it
149 out. Otherwise test for REX bit is excuse for existence of REX
150 only in case value is nonzero. */
151 #define USED_REX(value) \
152 { \
153 if (value) \
154 { \
155 if ((rex & value)) \
156 rex_used |= (value) | REX_OPCODE; \
157 } \
158 else \
159 rex_used |= REX_OPCODE; \
160 }
161
162 /* Flags for prefixes which we somehow handled when printing the
163 current instruction. */
164 static int used_prefixes;
165
166 /* Flags stored in PREFIXES. */
167 #define PREFIX_REPZ 1
168 #define PREFIX_REPNZ 2
169 #define PREFIX_LOCK 4
170 #define PREFIX_CS 8
171 #define PREFIX_SS 0x10
172 #define PREFIX_DS 0x20
173 #define PREFIX_ES 0x40
174 #define PREFIX_FS 0x80
175 #define PREFIX_GS 0x100
176 #define PREFIX_DATA 0x200
177 #define PREFIX_ADDR 0x400
178 #define PREFIX_FWAIT 0x800
179
180 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
181 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
182 on error. */
183 #define FETCH_DATA(info, addr) \
184 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
185 ? 1 : fetch_data ((info), (addr)))
186
187 static int
188 fetch_data (struct disassemble_info *info, bfd_byte *addr)
189 {
190 int status;
191 struct dis_private *priv = (struct dis_private *) info->private_data;
192 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
193
194 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
195 status = (*info->read_memory_func) (start,
196 priv->max_fetched,
197 addr - priv->max_fetched,
198 info);
199 else
200 status = -1;
201 if (status != 0)
202 {
203 /* If we did manage to read at least one byte, then
204 print_insn_i386 will do something sensible. Otherwise, print
205 an error. We do that here because this is where we know
206 STATUS. */
207 if (priv->max_fetched == priv->the_buffer)
208 (*info->memory_error_func) (status, start, info);
209 OPCODES_SIGLONGJMP (priv->bailout, 1);
210 }
211 else
212 priv->max_fetched = addr;
213 return 1;
214 }
215
216 /* Possible values for prefix requirement. */
217 #define PREFIX_IGNORED_SHIFT 16
218 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
219 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
220 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
221 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
222 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
223
224 /* Opcode prefixes. */
225 #define PREFIX_OPCODE (PREFIX_REPZ \
226 | PREFIX_REPNZ \
227 | PREFIX_DATA)
228
229 /* Prefixes ignored. */
230 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
231 | PREFIX_IGNORED_REPNZ \
232 | PREFIX_IGNORED_DATA)
233
234 #define XX { NULL, 0 }
235 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
236
237 #define Eb { OP_E, b_mode }
238 #define Ebnd { OP_E, bnd_mode }
239 #define EbS { OP_E, b_swap_mode }
240 #define EbndS { OP_E, bnd_swap_mode }
241 #define Ev { OP_E, v_mode }
242 #define Eva { OP_E, va_mode }
243 #define Ev_bnd { OP_E, v_bnd_mode }
244 #define EvS { OP_E, v_swap_mode }
245 #define Ed { OP_E, d_mode }
246 #define Edq { OP_E, dq_mode }
247 #define Edqw { OP_E, dqw_mode }
248 #define Edqb { OP_E, dqb_mode }
249 #define Edb { OP_E, db_mode }
250 #define Edw { OP_E, dw_mode }
251 #define Edqd { OP_E, dqd_mode }
252 #define Eq { OP_E, q_mode }
253 #define indirEv { OP_indirE, indir_v_mode }
254 #define indirEp { OP_indirE, f_mode }
255 #define stackEv { OP_E, stack_v_mode }
256 #define Em { OP_E, m_mode }
257 #define Ew { OP_E, w_mode }
258 #define M { OP_M, 0 } /* lea, lgdt, etc. */
259 #define Ma { OP_M, a_mode }
260 #define Mb { OP_M, b_mode }
261 #define Md { OP_M, d_mode }
262 #define Mo { OP_M, o_mode }
263 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
264 #define Mq { OP_M, q_mode }
265 #define Mv { OP_M, v_mode }
266 #define Mv_bnd { OP_M, v_bndmk_mode }
267 #define Mx { OP_M, x_mode }
268 #define Mxmm { OP_M, xmm_mode }
269 #define Gb { OP_G, b_mode }
270 #define Gbnd { OP_G, bnd_mode }
271 #define Gv { OP_G, v_mode }
272 #define Gd { OP_G, d_mode }
273 #define Gdq { OP_G, dq_mode }
274 #define Gm { OP_G, m_mode }
275 #define Gva { OP_G, va_mode }
276 #define Gw { OP_G, w_mode }
277 #define Rd { OP_R, d_mode }
278 #define Rdq { OP_R, dq_mode }
279 #define Rm { OP_R, m_mode }
280 #define Ib { OP_I, b_mode }
281 #define sIb { OP_sI, b_mode } /* sign extened byte */
282 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
283 #define Iv { OP_I, v_mode }
284 #define sIv { OP_sI, v_mode }
285 #define Iv64 { OP_I64, v_mode }
286 #define Id { OP_I, d_mode }
287 #define Iw { OP_I, w_mode }
288 #define I1 { OP_I, const_1_mode }
289 #define Jb { OP_J, b_mode }
290 #define Jv { OP_J, v_mode }
291 #define Jdqw { OP_J, dqw_mode }
292 #define Cm { OP_C, m_mode }
293 #define Dm { OP_D, m_mode }
294 #define Td { OP_T, d_mode }
295 #define Skip_MODRM { OP_Skip_MODRM, 0 }
296
297 #define RMeAX { OP_REG, eAX_reg }
298 #define RMeBX { OP_REG, eBX_reg }
299 #define RMeCX { OP_REG, eCX_reg }
300 #define RMeDX { OP_REG, eDX_reg }
301 #define RMeSP { OP_REG, eSP_reg }
302 #define RMeBP { OP_REG, eBP_reg }
303 #define RMeSI { OP_REG, eSI_reg }
304 #define RMeDI { OP_REG, eDI_reg }
305 #define RMrAX { OP_REG, rAX_reg }
306 #define RMrBX { OP_REG, rBX_reg }
307 #define RMrCX { OP_REG, rCX_reg }
308 #define RMrDX { OP_REG, rDX_reg }
309 #define RMrSP { OP_REG, rSP_reg }
310 #define RMrBP { OP_REG, rBP_reg }
311 #define RMrSI { OP_REG, rSI_reg }
312 #define RMrDI { OP_REG, rDI_reg }
313 #define RMAL { OP_REG, al_reg }
314 #define RMCL { OP_REG, cl_reg }
315 #define RMDL { OP_REG, dl_reg }
316 #define RMBL { OP_REG, bl_reg }
317 #define RMAH { OP_REG, ah_reg }
318 #define RMCH { OP_REG, ch_reg }
319 #define RMDH { OP_REG, dh_reg }
320 #define RMBH { OP_REG, bh_reg }
321 #define RMAX { OP_REG, ax_reg }
322 #define RMDX { OP_REG, dx_reg }
323
324 #define eAX { OP_IMREG, eAX_reg }
325 #define AL { OP_IMREG, al_reg }
326 #define CL { OP_IMREG, cl_reg }
327 #define zAX { OP_IMREG, z_mode_ax_reg }
328 #define indirDX { OP_IMREG, indir_dx_reg }
329
330 #define Sw { OP_SEG, w_mode }
331 #define Sv { OP_SEG, v_mode }
332 #define Ap { OP_DIR, 0 }
333 #define Ob { OP_OFF64, b_mode }
334 #define Ov { OP_OFF64, v_mode }
335 #define Xb { OP_DSreg, eSI_reg }
336 #define Xv { OP_DSreg, eSI_reg }
337 #define Xz { OP_DSreg, eSI_reg }
338 #define Yb { OP_ESreg, eDI_reg }
339 #define Yv { OP_ESreg, eDI_reg }
340 #define DSBX { OP_DSreg, eBX_reg }
341
342 #define es { OP_REG, es_reg }
343 #define ss { OP_REG, ss_reg }
344 #define cs { OP_REG, cs_reg }
345 #define ds { OP_REG, ds_reg }
346 #define fs { OP_REG, fs_reg }
347 #define gs { OP_REG, gs_reg }
348
349 #define MX { OP_MMX, 0 }
350 #define XM { OP_XMM, 0 }
351 #define XMScalar { OP_XMM, scalar_mode }
352 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
353 #define XMM { OP_XMM, xmm_mode }
354 #define TMM { OP_XMM, tmm_mode }
355 #define XMxmmq { OP_XMM, xmmq_mode }
356 #define EM { OP_EM, v_mode }
357 #define EMS { OP_EM, v_swap_mode }
358 #define EMd { OP_EM, d_mode }
359 #define EMx { OP_EM, x_mode }
360 #define EXbwUnit { OP_EX, bw_unit_mode }
361 #define EXw { OP_EX, w_mode }
362 #define EXd { OP_EX, d_mode }
363 #define EXdS { OP_EX, d_swap_mode }
364 #define EXq { OP_EX, q_mode }
365 #define EXqS { OP_EX, q_swap_mode }
366 #define EXx { OP_EX, x_mode }
367 #define EXxS { OP_EX, x_swap_mode }
368 #define EXxmm { OP_EX, xmm_mode }
369 #define EXymm { OP_EX, ymm_mode }
370 #define EXtmm { OP_EX, tmm_mode }
371 #define EXxmmq { OP_EX, xmmq_mode }
372 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
373 #define EXxmm_mb { OP_EX, xmm_mb_mode }
374 #define EXxmm_mw { OP_EX, xmm_mw_mode }
375 #define EXxmm_md { OP_EX, xmm_md_mode }
376 #define EXxmm_mq { OP_EX, xmm_mq_mode }
377 #define EXxmmdw { OP_EX, xmmdw_mode }
378 #define EXxmmqd { OP_EX, xmmqd_mode }
379 #define EXymmq { OP_EX, ymmq_mode }
380 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
381 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
382 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
383 #define MS { OP_MS, v_mode }
384 #define XS { OP_XS, v_mode }
385 #define EMCq { OP_EMC, q_mode }
386 #define MXC { OP_MXC, 0 }
387 #define OPSUF { OP_3DNowSuffix, 0 }
388 #define SEP { SEP_Fixup, 0 }
389 #define CMP { CMP_Fixup, 0 }
390 #define XMM0 { XMM_Fixup, 0 }
391 #define FXSAVE { FXSAVE_Fixup, 0 }
392
393 #define Vex { OP_VEX, vex_mode }
394 #define VexW { OP_VexW, vex_mode }
395 #define VexScalar { OP_VEX, vex_scalar_mode }
396 #define VexScalarR { OP_VexR, vex_scalar_mode }
397 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
398 #define VexGdq { OP_VEX, dq_mode }
399 #define VexTmm { OP_VEX, tmm_mode }
400 #define XMVexI4 { OP_REG_VexI4, x_mode }
401 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
402 #define VexI4 { OP_VexI4, 0 }
403 #define PCLMUL { PCLMUL_Fixup, 0 }
404 #define VPCMP { VPCMP_Fixup, 0 }
405 #define VPCOM { VPCOM_Fixup, 0 }
406
407 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
408 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
409 #define EXxEVexS { OP_Rounding, evex_sae_mode }
410
411 #define XMask { OP_Mask, mask_mode }
412 #define MaskG { OP_G, mask_mode }
413 #define MaskE { OP_E, mask_mode }
414 #define MaskBDE { OP_E, mask_bd_mode }
415 #define MaskR { OP_R, mask_mode }
416 #define MaskVex { OP_VEX, mask_mode }
417
418 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
419 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
420 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
421 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
422
423 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
424
425 /* Used handle "rep" prefix for string instructions. */
426 #define Xbr { REP_Fixup, eSI_reg }
427 #define Xvr { REP_Fixup, eSI_reg }
428 #define Ybr { REP_Fixup, eDI_reg }
429 #define Yvr { REP_Fixup, eDI_reg }
430 #define Yzr { REP_Fixup, eDI_reg }
431 #define indirDXr { REP_Fixup, indir_dx_reg }
432 #define ALr { REP_Fixup, al_reg }
433 #define eAXr { REP_Fixup, eAX_reg }
434
435 /* Used handle HLE prefix for lockable instructions. */
436 #define Ebh1 { HLE_Fixup1, b_mode }
437 #define Evh1 { HLE_Fixup1, v_mode }
438 #define Ebh2 { HLE_Fixup2, b_mode }
439 #define Evh2 { HLE_Fixup2, v_mode }
440 #define Ebh3 { HLE_Fixup3, b_mode }
441 #define Evh3 { HLE_Fixup3, v_mode }
442
443 #define BND { BND_Fixup, 0 }
444 #define NOTRACK { NOTRACK_Fixup, 0 }
445
446 #define cond_jump_flag { NULL, cond_jump_mode }
447 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
448
449 /* bits in sizeflag */
450 #define SUFFIX_ALWAYS 4
451 #define AFLAG 2
452 #define DFLAG 1
453
454 enum
455 {
456 /* byte operand */
457 b_mode = 1,
458 /* byte operand with operand swapped */
459 b_swap_mode,
460 /* byte operand, sign extend like 'T' suffix */
461 b_T_mode,
462 /* operand size depends on prefixes */
463 v_mode,
464 /* operand size depends on prefixes with operand swapped */
465 v_swap_mode,
466 /* operand size depends on address prefix */
467 va_mode,
468 /* word operand */
469 w_mode,
470 /* double word operand */
471 d_mode,
472 /* double word operand with operand swapped */
473 d_swap_mode,
474 /* quad word operand */
475 q_mode,
476 /* quad word operand with operand swapped */
477 q_swap_mode,
478 /* ten-byte operand */
479 t_mode,
480 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
481 broadcast enabled. */
482 x_mode,
483 /* Similar to x_mode, but with different EVEX mem shifts. */
484 evex_x_gscat_mode,
485 /* Similar to x_mode, but with yet different EVEX mem shifts. */
486 bw_unit_mode,
487 /* Similar to x_mode, but with disabled broadcast. */
488 evex_x_nobcst_mode,
489 /* Similar to x_mode, but with operands swapped and disabled broadcast
490 in EVEX. */
491 x_swap_mode,
492 /* 16-byte XMM operand */
493 xmm_mode,
494 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
495 memory operand (depending on vector length). Broadcast isn't
496 allowed. */
497 xmmq_mode,
498 /* Same as xmmq_mode, but broadcast is allowed. */
499 evex_half_bcst_xmmq_mode,
500 /* XMM register or byte memory operand */
501 xmm_mb_mode,
502 /* XMM register or word memory operand */
503 xmm_mw_mode,
504 /* XMM register or double word memory operand */
505 xmm_md_mode,
506 /* XMM register or quad word memory operand */
507 xmm_mq_mode,
508 /* 16-byte XMM, word, double word or quad word operand. */
509 xmmdw_mode,
510 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
511 xmmqd_mode,
512 /* 32-byte YMM operand */
513 ymm_mode,
514 /* quad word, ymmword or zmmword memory operand. */
515 ymmq_mode,
516 /* 32-byte YMM or 16-byte word operand */
517 ymmxmm_mode,
518 /* TMM operand */
519 tmm_mode,
520 /* d_mode in 32bit, q_mode in 64bit mode. */
521 m_mode,
522 /* pair of v_mode operands */
523 a_mode,
524 cond_jump_mode,
525 loop_jcxz_mode,
526 movsxd_mode,
527 v_bnd_mode,
528 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
529 v_bndmk_mode,
530 /* operand size depends on REX prefixes. */
531 dq_mode,
532 /* registers like dq_mode, memory like w_mode, displacements like
533 v_mode without considering Intel64 ISA. */
534 dqw_mode,
535 /* bounds operand */
536 bnd_mode,
537 /* bounds operand with operand swapped */
538 bnd_swap_mode,
539 /* 4- or 6-byte pointer operand */
540 f_mode,
541 const_1_mode,
542 /* v_mode for indirect branch opcodes. */
543 indir_v_mode,
544 /* v_mode for stack-related opcodes. */
545 stack_v_mode,
546 /* non-quad operand size depends on prefixes */
547 z_mode,
548 /* 16-byte operand */
549 o_mode,
550 /* registers like dq_mode, memory like b_mode. */
551 dqb_mode,
552 /* registers like d_mode, memory like b_mode. */
553 db_mode,
554 /* registers like d_mode, memory like w_mode. */
555 dw_mode,
556 /* registers like dq_mode, memory like d_mode. */
557 dqd_mode,
558 /* normal vex mode */
559 vex_mode,
560
561 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
562 vex_vsib_d_w_dq_mode,
563 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
564 vex_vsib_d_w_d_mode,
565 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
566 vex_vsib_q_w_dq_mode,
567 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
568 vex_vsib_q_w_d_mode,
569 /* mandatory non-vector SIB. */
570 vex_sibmem_mode,
571
572 /* scalar, ignore vector length. */
573 scalar_mode,
574 /* like vex_mode, ignore vector length. */
575 vex_scalar_mode,
576 /* Operand size depends on the VEX.W bit, ignore vector length. */
577 vex_scalar_w_dq_mode,
578
579 /* Static rounding. */
580 evex_rounding_mode,
581 /* Static rounding, 64-bit mode only. */
582 evex_rounding_64_mode,
583 /* Supress all exceptions. */
584 evex_sae_mode,
585
586 /* Mask register operand. */
587 mask_mode,
588 /* Mask register operand. */
589 mask_bd_mode,
590
591 es_reg,
592 cs_reg,
593 ss_reg,
594 ds_reg,
595 fs_reg,
596 gs_reg,
597
598 eAX_reg,
599 eCX_reg,
600 eDX_reg,
601 eBX_reg,
602 eSP_reg,
603 eBP_reg,
604 eSI_reg,
605 eDI_reg,
606
607 al_reg,
608 cl_reg,
609 dl_reg,
610 bl_reg,
611 ah_reg,
612 ch_reg,
613 dh_reg,
614 bh_reg,
615
616 ax_reg,
617 cx_reg,
618 dx_reg,
619 bx_reg,
620 sp_reg,
621 bp_reg,
622 si_reg,
623 di_reg,
624
625 rAX_reg,
626 rCX_reg,
627 rDX_reg,
628 rBX_reg,
629 rSP_reg,
630 rBP_reg,
631 rSI_reg,
632 rDI_reg,
633
634 z_mode_ax_reg,
635 indir_dx_reg
636 };
637
638 enum
639 {
640 FLOATCODE = 1,
641 USE_REG_TABLE,
642 USE_MOD_TABLE,
643 USE_RM_TABLE,
644 USE_PREFIX_TABLE,
645 USE_X86_64_TABLE,
646 USE_3BYTE_TABLE,
647 USE_XOP_8F_TABLE,
648 USE_VEX_C4_TABLE,
649 USE_VEX_C5_TABLE,
650 USE_VEX_LEN_TABLE,
651 USE_VEX_W_TABLE,
652 USE_EVEX_TABLE,
653 USE_EVEX_LEN_TABLE
654 };
655
656 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
657
658 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
659 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
660 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
661 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
662 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
663 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
664 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
665 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
666 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
667 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
668 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
669 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
670 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
671 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
672 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
673 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
674
675 enum
676 {
677 REG_80 = 0,
678 REG_81,
679 REG_83,
680 REG_8F,
681 REG_C0,
682 REG_C1,
683 REG_C6,
684 REG_C7,
685 REG_D0,
686 REG_D1,
687 REG_D2,
688 REG_D3,
689 REG_F6,
690 REG_F7,
691 REG_FE,
692 REG_FF,
693 REG_0F00,
694 REG_0F01,
695 REG_0F0D,
696 REG_0F18,
697 REG_0F1C_P_0_MOD_0,
698 REG_0F1E_P_1_MOD_3,
699 REG_0F71,
700 REG_0F72,
701 REG_0F73,
702 REG_0FA6,
703 REG_0FA7,
704 REG_0FAE,
705 REG_0FBA,
706 REG_0FC7,
707 REG_VEX_0F71,
708 REG_VEX_0F72,
709 REG_VEX_0F73,
710 REG_VEX_0FAE,
711 REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
712 REG_VEX_0F38F3,
713
714 REG_0FXOP_09_01_L_0,
715 REG_0FXOP_09_02_L_0,
716 REG_0FXOP_09_12_M_1_L_0,
717 REG_0FXOP_0A_12_L_0,
718
719 REG_EVEX_0F71,
720 REG_EVEX_0F72,
721 REG_EVEX_0F73,
722 REG_EVEX_0F38C6,
723 REG_EVEX_0F38C7
724 };
725
726 enum
727 {
728 MOD_8D = 0,
729 MOD_C6_REG_7,
730 MOD_C7_REG_7,
731 MOD_FF_REG_3,
732 MOD_FF_REG_5,
733 MOD_0F01_REG_0,
734 MOD_0F01_REG_1,
735 MOD_0F01_REG_2,
736 MOD_0F01_REG_3,
737 MOD_0F01_REG_5,
738 MOD_0F01_REG_7,
739 MOD_0F12_PREFIX_0,
740 MOD_0F12_PREFIX_2,
741 MOD_0F13,
742 MOD_0F16_PREFIX_0,
743 MOD_0F16_PREFIX_2,
744 MOD_0F17,
745 MOD_0F18_REG_0,
746 MOD_0F18_REG_1,
747 MOD_0F18_REG_2,
748 MOD_0F18_REG_3,
749 MOD_0F18_REG_4,
750 MOD_0F18_REG_5,
751 MOD_0F18_REG_6,
752 MOD_0F18_REG_7,
753 MOD_0F1A_PREFIX_0,
754 MOD_0F1B_PREFIX_0,
755 MOD_0F1B_PREFIX_1,
756 MOD_0F1C_PREFIX_0,
757 MOD_0F1E_PREFIX_1,
758 MOD_0F24,
759 MOD_0F26,
760 MOD_0F2B_PREFIX_0,
761 MOD_0F2B_PREFIX_1,
762 MOD_0F2B_PREFIX_2,
763 MOD_0F2B_PREFIX_3,
764 MOD_0F50,
765 MOD_0F71_REG_2,
766 MOD_0F71_REG_4,
767 MOD_0F71_REG_6,
768 MOD_0F72_REG_2,
769 MOD_0F72_REG_4,
770 MOD_0F72_REG_6,
771 MOD_0F73_REG_2,
772 MOD_0F73_REG_3,
773 MOD_0F73_REG_6,
774 MOD_0F73_REG_7,
775 MOD_0FAE_REG_0,
776 MOD_0FAE_REG_1,
777 MOD_0FAE_REG_2,
778 MOD_0FAE_REG_3,
779 MOD_0FAE_REG_4,
780 MOD_0FAE_REG_5,
781 MOD_0FAE_REG_6,
782 MOD_0FAE_REG_7,
783 MOD_0FB2,
784 MOD_0FB4,
785 MOD_0FB5,
786 MOD_0FC3,
787 MOD_0FC7_REG_3,
788 MOD_0FC7_REG_4,
789 MOD_0FC7_REG_5,
790 MOD_0FC7_REG_6,
791 MOD_0FC7_REG_7,
792 MOD_0FD7,
793 MOD_0FE7_PREFIX_2,
794 MOD_0FF0_PREFIX_3,
795 MOD_0F382A,
796 MOD_VEX_0F3849_X86_64_P_0_W_0,
797 MOD_VEX_0F3849_X86_64_P_2_W_0,
798 MOD_VEX_0F3849_X86_64_P_3_W_0,
799 MOD_VEX_0F384B_X86_64_P_1_W_0,
800 MOD_VEX_0F384B_X86_64_P_2_W_0,
801 MOD_VEX_0F384B_X86_64_P_3_W_0,
802 MOD_VEX_0F385C_X86_64_P_1_W_0,
803 MOD_VEX_0F385E_X86_64_P_0_W_0,
804 MOD_VEX_0F385E_X86_64_P_1_W_0,
805 MOD_VEX_0F385E_X86_64_P_2_W_0,
806 MOD_VEX_0F385E_X86_64_P_3_W_0,
807 MOD_0F38F5,
808 MOD_0F38F6_PREFIX_0,
809 MOD_0F38F8_PREFIX_1,
810 MOD_0F38F8_PREFIX_2,
811 MOD_0F38F8_PREFIX_3,
812 MOD_0F38F9_PREFIX_0,
813 MOD_62_32BIT,
814 MOD_C4_32BIT,
815 MOD_C5_32BIT,
816 MOD_VEX_0F12_PREFIX_0,
817 MOD_VEX_0F12_PREFIX_2,
818 MOD_VEX_0F13,
819 MOD_VEX_0F16_PREFIX_0,
820 MOD_VEX_0F16_PREFIX_2,
821 MOD_VEX_0F17,
822 MOD_VEX_0F2B,
823 MOD_VEX_W_0_0F41_P_0_LEN_1,
824 MOD_VEX_W_1_0F41_P_0_LEN_1,
825 MOD_VEX_W_0_0F41_P_2_LEN_1,
826 MOD_VEX_W_1_0F41_P_2_LEN_1,
827 MOD_VEX_W_0_0F42_P_0_LEN_1,
828 MOD_VEX_W_1_0F42_P_0_LEN_1,
829 MOD_VEX_W_0_0F42_P_2_LEN_1,
830 MOD_VEX_W_1_0F42_P_2_LEN_1,
831 MOD_VEX_W_0_0F44_P_0_LEN_1,
832 MOD_VEX_W_1_0F44_P_0_LEN_1,
833 MOD_VEX_W_0_0F44_P_2_LEN_1,
834 MOD_VEX_W_1_0F44_P_2_LEN_1,
835 MOD_VEX_W_0_0F45_P_0_LEN_1,
836 MOD_VEX_W_1_0F45_P_0_LEN_1,
837 MOD_VEX_W_0_0F45_P_2_LEN_1,
838 MOD_VEX_W_1_0F45_P_2_LEN_1,
839 MOD_VEX_W_0_0F46_P_0_LEN_1,
840 MOD_VEX_W_1_0F46_P_0_LEN_1,
841 MOD_VEX_W_0_0F46_P_2_LEN_1,
842 MOD_VEX_W_1_0F46_P_2_LEN_1,
843 MOD_VEX_W_0_0F47_P_0_LEN_1,
844 MOD_VEX_W_1_0F47_P_0_LEN_1,
845 MOD_VEX_W_0_0F47_P_2_LEN_1,
846 MOD_VEX_W_1_0F47_P_2_LEN_1,
847 MOD_VEX_W_0_0F4A_P_0_LEN_1,
848 MOD_VEX_W_1_0F4A_P_0_LEN_1,
849 MOD_VEX_W_0_0F4A_P_2_LEN_1,
850 MOD_VEX_W_1_0F4A_P_2_LEN_1,
851 MOD_VEX_W_0_0F4B_P_0_LEN_1,
852 MOD_VEX_W_1_0F4B_P_0_LEN_1,
853 MOD_VEX_W_0_0F4B_P_2_LEN_1,
854 MOD_VEX_0F50,
855 MOD_VEX_0F71_REG_2,
856 MOD_VEX_0F71_REG_4,
857 MOD_VEX_0F71_REG_6,
858 MOD_VEX_0F72_REG_2,
859 MOD_VEX_0F72_REG_4,
860 MOD_VEX_0F72_REG_6,
861 MOD_VEX_0F73_REG_2,
862 MOD_VEX_0F73_REG_3,
863 MOD_VEX_0F73_REG_6,
864 MOD_VEX_0F73_REG_7,
865 MOD_VEX_W_0_0F91_P_0_LEN_0,
866 MOD_VEX_W_1_0F91_P_0_LEN_0,
867 MOD_VEX_W_0_0F91_P_2_LEN_0,
868 MOD_VEX_W_1_0F91_P_2_LEN_0,
869 MOD_VEX_W_0_0F92_P_0_LEN_0,
870 MOD_VEX_W_0_0F92_P_2_LEN_0,
871 MOD_VEX_0F92_P_3_LEN_0,
872 MOD_VEX_W_0_0F93_P_0_LEN_0,
873 MOD_VEX_W_0_0F93_P_2_LEN_0,
874 MOD_VEX_0F93_P_3_LEN_0,
875 MOD_VEX_W_0_0F98_P_0_LEN_0,
876 MOD_VEX_W_1_0F98_P_0_LEN_0,
877 MOD_VEX_W_0_0F98_P_2_LEN_0,
878 MOD_VEX_W_1_0F98_P_2_LEN_0,
879 MOD_VEX_W_0_0F99_P_0_LEN_0,
880 MOD_VEX_W_1_0F99_P_0_LEN_0,
881 MOD_VEX_W_0_0F99_P_2_LEN_0,
882 MOD_VEX_W_1_0F99_P_2_LEN_0,
883 MOD_VEX_0FAE_REG_2,
884 MOD_VEX_0FAE_REG_3,
885 MOD_VEX_0FD7,
886 MOD_VEX_0FE7,
887 MOD_VEX_0FF0_PREFIX_3,
888 MOD_VEX_0F381A,
889 MOD_VEX_0F382A,
890 MOD_VEX_0F382C,
891 MOD_VEX_0F382D,
892 MOD_VEX_0F382E,
893 MOD_VEX_0F382F,
894 MOD_VEX_0F385A,
895 MOD_VEX_0F388C,
896 MOD_VEX_0F388E,
897 MOD_VEX_0F3A30_L_0_W_0,
898 MOD_VEX_0F3A30_L_0_W_1,
899 MOD_VEX_0F3A31_L_0_W_0,
900 MOD_VEX_0F3A31_L_0_W_1,
901 MOD_VEX_0F3A32_L_0_W_0,
902 MOD_VEX_0F3A32_L_0_W_1,
903 MOD_VEX_0F3A33_L_0_W_0,
904 MOD_VEX_0F3A33_L_0_W_1,
905
906 MOD_VEX_0FXOP_09_12,
907
908 MOD_EVEX_0F12_PREFIX_0,
909 MOD_EVEX_0F12_PREFIX_2,
910 MOD_EVEX_0F13,
911 MOD_EVEX_0F16_PREFIX_0,
912 MOD_EVEX_0F16_PREFIX_2,
913 MOD_EVEX_0F17,
914 MOD_EVEX_0F2B,
915 MOD_EVEX_0F381A_W_0,
916 MOD_EVEX_0F381A_W_1,
917 MOD_EVEX_0F381B_W_0,
918 MOD_EVEX_0F381B_W_1,
919 MOD_EVEX_0F385A_W_0,
920 MOD_EVEX_0F385A_W_1,
921 MOD_EVEX_0F385B_W_0,
922 MOD_EVEX_0F385B_W_1,
923 MOD_EVEX_0F38C6_REG_1,
924 MOD_EVEX_0F38C6_REG_2,
925 MOD_EVEX_0F38C6_REG_5,
926 MOD_EVEX_0F38C6_REG_6,
927 MOD_EVEX_0F38C7_REG_1,
928 MOD_EVEX_0F38C7_REG_2,
929 MOD_EVEX_0F38C7_REG_5,
930 MOD_EVEX_0F38C7_REG_6
931 };
932
933 enum
934 {
935 RM_C6_REG_7 = 0,
936 RM_C7_REG_7,
937 RM_0F01_REG_0,
938 RM_0F01_REG_1,
939 RM_0F01_REG_2,
940 RM_0F01_REG_3,
941 RM_0F01_REG_5_MOD_3,
942 RM_0F01_REG_7_MOD_3,
943 RM_0F1E_P_1_MOD_3_REG_7,
944 RM_0FAE_REG_6_MOD_3_P_0,
945 RM_0FAE_REG_7_MOD_3,
946 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
947 };
948
949 enum
950 {
951 PREFIX_90 = 0,
952 PREFIX_0F01_REG_3_RM_1,
953 PREFIX_0F01_REG_5_MOD_0,
954 PREFIX_0F01_REG_5_MOD_3_RM_0,
955 PREFIX_0F01_REG_5_MOD_3_RM_1,
956 PREFIX_0F01_REG_5_MOD_3_RM_2,
957 PREFIX_0F01_REG_7_MOD_3_RM_2,
958 PREFIX_0F01_REG_7_MOD_3_RM_3,
959 PREFIX_0F09,
960 PREFIX_0F10,
961 PREFIX_0F11,
962 PREFIX_0F12,
963 PREFIX_0F16,
964 PREFIX_0F1A,
965 PREFIX_0F1B,
966 PREFIX_0F1C,
967 PREFIX_0F1E,
968 PREFIX_0F2A,
969 PREFIX_0F2B,
970 PREFIX_0F2C,
971 PREFIX_0F2D,
972 PREFIX_0F2E,
973 PREFIX_0F2F,
974 PREFIX_0F51,
975 PREFIX_0F52,
976 PREFIX_0F53,
977 PREFIX_0F58,
978 PREFIX_0F59,
979 PREFIX_0F5A,
980 PREFIX_0F5B,
981 PREFIX_0F5C,
982 PREFIX_0F5D,
983 PREFIX_0F5E,
984 PREFIX_0F5F,
985 PREFIX_0F60,
986 PREFIX_0F61,
987 PREFIX_0F62,
988 PREFIX_0F6F,
989 PREFIX_0F70,
990 PREFIX_0F78,
991 PREFIX_0F79,
992 PREFIX_0F7C,
993 PREFIX_0F7D,
994 PREFIX_0F7E,
995 PREFIX_0F7F,
996 PREFIX_0FAE_REG_0_MOD_3,
997 PREFIX_0FAE_REG_1_MOD_3,
998 PREFIX_0FAE_REG_2_MOD_3,
999 PREFIX_0FAE_REG_3_MOD_3,
1000 PREFIX_0FAE_REG_4_MOD_0,
1001 PREFIX_0FAE_REG_4_MOD_3,
1002 PREFIX_0FAE_REG_5_MOD_0,
1003 PREFIX_0FAE_REG_5_MOD_3,
1004 PREFIX_0FAE_REG_6_MOD_0,
1005 PREFIX_0FAE_REG_6_MOD_3,
1006 PREFIX_0FAE_REG_7_MOD_0,
1007 PREFIX_0FB8,
1008 PREFIX_0FBC,
1009 PREFIX_0FBD,
1010 PREFIX_0FC2,
1011 PREFIX_0FC3_MOD_0,
1012 PREFIX_0FC7_REG_6_MOD_0,
1013 PREFIX_0FC7_REG_6_MOD_3,
1014 PREFIX_0FC7_REG_7_MOD_3,
1015 PREFIX_0FD0,
1016 PREFIX_0FD6,
1017 PREFIX_0FE6,
1018 PREFIX_0FE7,
1019 PREFIX_0FF0,
1020 PREFIX_0FF7,
1021 PREFIX_0F38C8,
1022 PREFIX_0F38C9,
1023 PREFIX_0F38CA,
1024 PREFIX_0F38CB,
1025 PREFIX_0F38CC,
1026 PREFIX_0F38CD,
1027 PREFIX_0F38F0,
1028 PREFIX_0F38F1,
1029 PREFIX_0F38F6,
1030 PREFIX_0F38F8,
1031 PREFIX_0F38F9,
1032 PREFIX_0F3ACC,
1033 PREFIX_VEX_0F10,
1034 PREFIX_VEX_0F11,
1035 PREFIX_VEX_0F12,
1036 PREFIX_VEX_0F16,
1037 PREFIX_VEX_0F2A,
1038 PREFIX_VEX_0F2C,
1039 PREFIX_VEX_0F2D,
1040 PREFIX_VEX_0F2E,
1041 PREFIX_VEX_0F2F,
1042 PREFIX_VEX_0F41,
1043 PREFIX_VEX_0F42,
1044 PREFIX_VEX_0F44,
1045 PREFIX_VEX_0F45,
1046 PREFIX_VEX_0F46,
1047 PREFIX_VEX_0F47,
1048 PREFIX_VEX_0F4A,
1049 PREFIX_VEX_0F4B,
1050 PREFIX_VEX_0F51,
1051 PREFIX_VEX_0F52,
1052 PREFIX_VEX_0F53,
1053 PREFIX_VEX_0F58,
1054 PREFIX_VEX_0F59,
1055 PREFIX_VEX_0F5A,
1056 PREFIX_VEX_0F5B,
1057 PREFIX_VEX_0F5C,
1058 PREFIX_VEX_0F5D,
1059 PREFIX_VEX_0F5E,
1060 PREFIX_VEX_0F5F,
1061 PREFIX_VEX_0F6F,
1062 PREFIX_VEX_0F70,
1063 PREFIX_VEX_0F77,
1064 PREFIX_VEX_0F7C,
1065 PREFIX_VEX_0F7D,
1066 PREFIX_VEX_0F7E,
1067 PREFIX_VEX_0F7F,
1068 PREFIX_VEX_0F90,
1069 PREFIX_VEX_0F91,
1070 PREFIX_VEX_0F92,
1071 PREFIX_VEX_0F93,
1072 PREFIX_VEX_0F98,
1073 PREFIX_VEX_0F99,
1074 PREFIX_VEX_0FC2,
1075 PREFIX_VEX_0FD0,
1076 PREFIX_VEX_0FE6,
1077 PREFIX_VEX_0FF0,
1078 PREFIX_VEX_0F3849_X86_64,
1079 PREFIX_VEX_0F384B_X86_64,
1080 PREFIX_VEX_0F385C_X86_64,
1081 PREFIX_VEX_0F385E_X86_64,
1082 PREFIX_VEX_0F38F2,
1083 PREFIX_VEX_0F38F3_REG_1,
1084 PREFIX_VEX_0F38F3_REG_2,
1085 PREFIX_VEX_0F38F3_REG_3,
1086 PREFIX_VEX_0F38F5,
1087 PREFIX_VEX_0F38F6,
1088 PREFIX_VEX_0F38F7,
1089 PREFIX_VEX_0F3AF0,
1090
1091 PREFIX_EVEX_0F10,
1092 PREFIX_EVEX_0F11,
1093 PREFIX_EVEX_0F12,
1094 PREFIX_EVEX_0F16,
1095 PREFIX_EVEX_0F2A,
1096 PREFIX_EVEX_0F51,
1097 PREFIX_EVEX_0F58,
1098 PREFIX_EVEX_0F59,
1099 PREFIX_EVEX_0F5A,
1100 PREFIX_EVEX_0F5B,
1101 PREFIX_EVEX_0F5C,
1102 PREFIX_EVEX_0F5D,
1103 PREFIX_EVEX_0F5E,
1104 PREFIX_EVEX_0F5F,
1105 PREFIX_EVEX_0F6F,
1106 PREFIX_EVEX_0F70,
1107 PREFIX_EVEX_0F78,
1108 PREFIX_EVEX_0F79,
1109 PREFIX_EVEX_0F7A,
1110 PREFIX_EVEX_0F7B,
1111 PREFIX_EVEX_0F7E,
1112 PREFIX_EVEX_0F7F,
1113 PREFIX_EVEX_0FC2,
1114 PREFIX_EVEX_0FE6,
1115 PREFIX_EVEX_0F3810,
1116 PREFIX_EVEX_0F3811,
1117 PREFIX_EVEX_0F3812,
1118 PREFIX_EVEX_0F3813,
1119 PREFIX_EVEX_0F3814,
1120 PREFIX_EVEX_0F3815,
1121 PREFIX_EVEX_0F3820,
1122 PREFIX_EVEX_0F3821,
1123 PREFIX_EVEX_0F3822,
1124 PREFIX_EVEX_0F3823,
1125 PREFIX_EVEX_0F3824,
1126 PREFIX_EVEX_0F3825,
1127 PREFIX_EVEX_0F3826,
1128 PREFIX_EVEX_0F3827,
1129 PREFIX_EVEX_0F3828,
1130 PREFIX_EVEX_0F3829,
1131 PREFIX_EVEX_0F382A,
1132 PREFIX_EVEX_0F3830,
1133 PREFIX_EVEX_0F3831,
1134 PREFIX_EVEX_0F3832,
1135 PREFIX_EVEX_0F3833,
1136 PREFIX_EVEX_0F3834,
1137 PREFIX_EVEX_0F3835,
1138 PREFIX_EVEX_0F3838,
1139 PREFIX_EVEX_0F3839,
1140 PREFIX_EVEX_0F383A,
1141 PREFIX_EVEX_0F3852,
1142 PREFIX_EVEX_0F3853,
1143 PREFIX_EVEX_0F3868,
1144 PREFIX_EVEX_0F3872,
1145 PREFIX_EVEX_0F389A,
1146 PREFIX_EVEX_0F389B,
1147 PREFIX_EVEX_0F38AA,
1148 PREFIX_EVEX_0F38AB,
1149 };
1150
1151 enum
1152 {
1153 X86_64_06 = 0,
1154 X86_64_07,
1155 X86_64_0E,
1156 X86_64_16,
1157 X86_64_17,
1158 X86_64_1E,
1159 X86_64_1F,
1160 X86_64_27,
1161 X86_64_2F,
1162 X86_64_37,
1163 X86_64_3F,
1164 X86_64_60,
1165 X86_64_61,
1166 X86_64_62,
1167 X86_64_63,
1168 X86_64_6D,
1169 X86_64_6F,
1170 X86_64_82,
1171 X86_64_9A,
1172 X86_64_C2,
1173 X86_64_C3,
1174 X86_64_C4,
1175 X86_64_C5,
1176 X86_64_CE,
1177 X86_64_D4,
1178 X86_64_D5,
1179 X86_64_E8,
1180 X86_64_E9,
1181 X86_64_EA,
1182 X86_64_0F01_REG_0,
1183 X86_64_0F01_REG_1,
1184 X86_64_0F01_REG_2,
1185 X86_64_0F01_REG_3,
1186 X86_64_VEX_0F3849,
1187 X86_64_VEX_0F384B,
1188 X86_64_VEX_0F385C,
1189 X86_64_VEX_0F385E
1190 };
1191
1192 enum
1193 {
1194 THREE_BYTE_0F38 = 0,
1195 THREE_BYTE_0F3A
1196 };
1197
1198 enum
1199 {
1200 XOP_08 = 0,
1201 XOP_09,
1202 XOP_0A
1203 };
1204
1205 enum
1206 {
1207 VEX_0F = 0,
1208 VEX_0F38,
1209 VEX_0F3A
1210 };
1211
1212 enum
1213 {
1214 EVEX_0F = 0,
1215 EVEX_0F38,
1216 EVEX_0F3A
1217 };
1218
1219 enum
1220 {
1221 VEX_LEN_0F12_P_0_M_0 = 0,
1222 VEX_LEN_0F12_P_0_M_1,
1223 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1224 VEX_LEN_0F13_M_0,
1225 VEX_LEN_0F16_P_0_M_0,
1226 VEX_LEN_0F16_P_0_M_1,
1227 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1228 VEX_LEN_0F17_M_0,
1229 VEX_LEN_0F41_P_0,
1230 VEX_LEN_0F41_P_2,
1231 VEX_LEN_0F42_P_0,
1232 VEX_LEN_0F42_P_2,
1233 VEX_LEN_0F44_P_0,
1234 VEX_LEN_0F44_P_2,
1235 VEX_LEN_0F45_P_0,
1236 VEX_LEN_0F45_P_2,
1237 VEX_LEN_0F46_P_0,
1238 VEX_LEN_0F46_P_2,
1239 VEX_LEN_0F47_P_0,
1240 VEX_LEN_0F47_P_2,
1241 VEX_LEN_0F4A_P_0,
1242 VEX_LEN_0F4A_P_2,
1243 VEX_LEN_0F4B_P_0,
1244 VEX_LEN_0F4B_P_2,
1245 VEX_LEN_0F6E,
1246 VEX_LEN_0F77_P_0,
1247 VEX_LEN_0F7E_P_1,
1248 VEX_LEN_0F7E_P_2,
1249 VEX_LEN_0F90_P_0,
1250 VEX_LEN_0F90_P_2,
1251 VEX_LEN_0F91_P_0,
1252 VEX_LEN_0F91_P_2,
1253 VEX_LEN_0F92_P_0,
1254 VEX_LEN_0F92_P_2,
1255 VEX_LEN_0F92_P_3,
1256 VEX_LEN_0F93_P_0,
1257 VEX_LEN_0F93_P_2,
1258 VEX_LEN_0F93_P_3,
1259 VEX_LEN_0F98_P_0,
1260 VEX_LEN_0F98_P_2,
1261 VEX_LEN_0F99_P_0,
1262 VEX_LEN_0F99_P_2,
1263 VEX_LEN_0FAE_R_2_M_0,
1264 VEX_LEN_0FAE_R_3_M_0,
1265 VEX_LEN_0FC4,
1266 VEX_LEN_0FC5,
1267 VEX_LEN_0FD6,
1268 VEX_LEN_0FF7,
1269 VEX_LEN_0F3816,
1270 VEX_LEN_0F3819,
1271 VEX_LEN_0F381A_M_0,
1272 VEX_LEN_0F3836,
1273 VEX_LEN_0F3841,
1274 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1275 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1276 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1277 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1278 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1279 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1280 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1281 VEX_LEN_0F385A_M_0,
1282 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1283 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1284 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1285 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1286 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1287 VEX_LEN_0F38DB,
1288 VEX_LEN_0F38F2_P_0,
1289 VEX_LEN_0F38F3_R_1_P_0,
1290 VEX_LEN_0F38F3_R_2_P_0,
1291 VEX_LEN_0F38F3_R_3_P_0,
1292 VEX_LEN_0F38F5_P_0,
1293 VEX_LEN_0F38F5_P_1,
1294 VEX_LEN_0F38F5_P_3,
1295 VEX_LEN_0F38F6_P_3,
1296 VEX_LEN_0F38F7_P_0,
1297 VEX_LEN_0F38F7_P_1,
1298 VEX_LEN_0F38F7_P_2,
1299 VEX_LEN_0F38F7_P_3,
1300 VEX_LEN_0F3A00,
1301 VEX_LEN_0F3A01,
1302 VEX_LEN_0F3A06,
1303 VEX_LEN_0F3A14,
1304 VEX_LEN_0F3A15,
1305 VEX_LEN_0F3A16,
1306 VEX_LEN_0F3A17,
1307 VEX_LEN_0F3A18,
1308 VEX_LEN_0F3A19,
1309 VEX_LEN_0F3A20,
1310 VEX_LEN_0F3A21,
1311 VEX_LEN_0F3A22,
1312 VEX_LEN_0F3A30,
1313 VEX_LEN_0F3A31,
1314 VEX_LEN_0F3A32,
1315 VEX_LEN_0F3A33,
1316 VEX_LEN_0F3A38,
1317 VEX_LEN_0F3A39,
1318 VEX_LEN_0F3A41,
1319 VEX_LEN_0F3A46,
1320 VEX_LEN_0F3A60,
1321 VEX_LEN_0F3A61,
1322 VEX_LEN_0F3A62,
1323 VEX_LEN_0F3A63,
1324 VEX_LEN_0F3ADF,
1325 VEX_LEN_0F3AF0_P_3,
1326 VEX_LEN_0FXOP_08_85,
1327 VEX_LEN_0FXOP_08_86,
1328 VEX_LEN_0FXOP_08_87,
1329 VEX_LEN_0FXOP_08_8E,
1330 VEX_LEN_0FXOP_08_8F,
1331 VEX_LEN_0FXOP_08_95,
1332 VEX_LEN_0FXOP_08_96,
1333 VEX_LEN_0FXOP_08_97,
1334 VEX_LEN_0FXOP_08_9E,
1335 VEX_LEN_0FXOP_08_9F,
1336 VEX_LEN_0FXOP_08_A3,
1337 VEX_LEN_0FXOP_08_A6,
1338 VEX_LEN_0FXOP_08_B6,
1339 VEX_LEN_0FXOP_08_C0,
1340 VEX_LEN_0FXOP_08_C1,
1341 VEX_LEN_0FXOP_08_C2,
1342 VEX_LEN_0FXOP_08_C3,
1343 VEX_LEN_0FXOP_08_CC,
1344 VEX_LEN_0FXOP_08_CD,
1345 VEX_LEN_0FXOP_08_CE,
1346 VEX_LEN_0FXOP_08_CF,
1347 VEX_LEN_0FXOP_08_EC,
1348 VEX_LEN_0FXOP_08_ED,
1349 VEX_LEN_0FXOP_08_EE,
1350 VEX_LEN_0FXOP_08_EF,
1351 VEX_LEN_0FXOP_09_01,
1352 VEX_LEN_0FXOP_09_02,
1353 VEX_LEN_0FXOP_09_12_M_1,
1354 VEX_LEN_0FXOP_09_82_W_0,
1355 VEX_LEN_0FXOP_09_83_W_0,
1356 VEX_LEN_0FXOP_09_90,
1357 VEX_LEN_0FXOP_09_91,
1358 VEX_LEN_0FXOP_09_92,
1359 VEX_LEN_0FXOP_09_93,
1360 VEX_LEN_0FXOP_09_94,
1361 VEX_LEN_0FXOP_09_95,
1362 VEX_LEN_0FXOP_09_96,
1363 VEX_LEN_0FXOP_09_97,
1364 VEX_LEN_0FXOP_09_98,
1365 VEX_LEN_0FXOP_09_99,
1366 VEX_LEN_0FXOP_09_9A,
1367 VEX_LEN_0FXOP_09_9B,
1368 VEX_LEN_0FXOP_09_C1,
1369 VEX_LEN_0FXOP_09_C2,
1370 VEX_LEN_0FXOP_09_C3,
1371 VEX_LEN_0FXOP_09_C6,
1372 VEX_LEN_0FXOP_09_C7,
1373 VEX_LEN_0FXOP_09_CB,
1374 VEX_LEN_0FXOP_09_D1,
1375 VEX_LEN_0FXOP_09_D2,
1376 VEX_LEN_0FXOP_09_D3,
1377 VEX_LEN_0FXOP_09_D6,
1378 VEX_LEN_0FXOP_09_D7,
1379 VEX_LEN_0FXOP_09_DB,
1380 VEX_LEN_0FXOP_09_E1,
1381 VEX_LEN_0FXOP_09_E2,
1382 VEX_LEN_0FXOP_09_E3,
1383 VEX_LEN_0FXOP_0A_12,
1384 };
1385
1386 enum
1387 {
1388 EVEX_LEN_0F6E = 0,
1389 EVEX_LEN_0F7E_P_1,
1390 EVEX_LEN_0F7E_P_2,
1391 EVEX_LEN_0FC4,
1392 EVEX_LEN_0FC5,
1393 EVEX_LEN_0FD6,
1394 EVEX_LEN_0F3816,
1395 EVEX_LEN_0F3819_W_0,
1396 EVEX_LEN_0F3819_W_1,
1397 EVEX_LEN_0F381A_W_0_M_0,
1398 EVEX_LEN_0F381A_W_1_M_0,
1399 EVEX_LEN_0F381B_W_0_M_0,
1400 EVEX_LEN_0F381B_W_1_M_0,
1401 EVEX_LEN_0F3836,
1402 EVEX_LEN_0F385A_W_0_M_0,
1403 EVEX_LEN_0F385A_W_1_M_0,
1404 EVEX_LEN_0F385B_W_0_M_0,
1405 EVEX_LEN_0F385B_W_1_M_0,
1406 EVEX_LEN_0F38C6_R_1_M_0,
1407 EVEX_LEN_0F38C6_R_2_M_0,
1408 EVEX_LEN_0F38C6_R_5_M_0,
1409 EVEX_LEN_0F38C6_R_6_M_0,
1410 EVEX_LEN_0F38C7_R_1_M_0_W_0,
1411 EVEX_LEN_0F38C7_R_1_M_0_W_1,
1412 EVEX_LEN_0F38C7_R_2_M_0_W_0,
1413 EVEX_LEN_0F38C7_R_2_M_0_W_1,
1414 EVEX_LEN_0F38C7_R_5_M_0_W_0,
1415 EVEX_LEN_0F38C7_R_5_M_0_W_1,
1416 EVEX_LEN_0F38C7_R_6_M_0_W_0,
1417 EVEX_LEN_0F38C7_R_6_M_0_W_1,
1418 EVEX_LEN_0F3A00_W_1,
1419 EVEX_LEN_0F3A01_W_1,
1420 EVEX_LEN_0F3A14,
1421 EVEX_LEN_0F3A15,
1422 EVEX_LEN_0F3A16,
1423 EVEX_LEN_0F3A17,
1424 EVEX_LEN_0F3A18_W_0,
1425 EVEX_LEN_0F3A18_W_1,
1426 EVEX_LEN_0F3A19_W_0,
1427 EVEX_LEN_0F3A19_W_1,
1428 EVEX_LEN_0F3A1A_W_0,
1429 EVEX_LEN_0F3A1A_W_1,
1430 EVEX_LEN_0F3A1B_W_0,
1431 EVEX_LEN_0F3A1B_W_1,
1432 EVEX_LEN_0F3A20,
1433 EVEX_LEN_0F3A21_W_0,
1434 EVEX_LEN_0F3A22,
1435 EVEX_LEN_0F3A23_W_0,
1436 EVEX_LEN_0F3A23_W_1,
1437 EVEX_LEN_0F3A38_W_0,
1438 EVEX_LEN_0F3A38_W_1,
1439 EVEX_LEN_0F3A39_W_0,
1440 EVEX_LEN_0F3A39_W_1,
1441 EVEX_LEN_0F3A3A_W_0,
1442 EVEX_LEN_0F3A3A_W_1,
1443 EVEX_LEN_0F3A3B_W_0,
1444 EVEX_LEN_0F3A3B_W_1,
1445 EVEX_LEN_0F3A43_W_0,
1446 EVEX_LEN_0F3A43_W_1
1447 };
1448
1449 enum
1450 {
1451 VEX_W_0F41_P_0_LEN_1 = 0,
1452 VEX_W_0F41_P_2_LEN_1,
1453 VEX_W_0F42_P_0_LEN_1,
1454 VEX_W_0F42_P_2_LEN_1,
1455 VEX_W_0F44_P_0_LEN_0,
1456 VEX_W_0F44_P_2_LEN_0,
1457 VEX_W_0F45_P_0_LEN_1,
1458 VEX_W_0F45_P_2_LEN_1,
1459 VEX_W_0F46_P_0_LEN_1,
1460 VEX_W_0F46_P_2_LEN_1,
1461 VEX_W_0F47_P_0_LEN_1,
1462 VEX_W_0F47_P_2_LEN_1,
1463 VEX_W_0F4A_P_0_LEN_1,
1464 VEX_W_0F4A_P_2_LEN_1,
1465 VEX_W_0F4B_P_0_LEN_1,
1466 VEX_W_0F4B_P_2_LEN_1,
1467 VEX_W_0F90_P_0_LEN_0,
1468 VEX_W_0F90_P_2_LEN_0,
1469 VEX_W_0F91_P_0_LEN_0,
1470 VEX_W_0F91_P_2_LEN_0,
1471 VEX_W_0F92_P_0_LEN_0,
1472 VEX_W_0F92_P_2_LEN_0,
1473 VEX_W_0F93_P_0_LEN_0,
1474 VEX_W_0F93_P_2_LEN_0,
1475 VEX_W_0F98_P_0_LEN_0,
1476 VEX_W_0F98_P_2_LEN_0,
1477 VEX_W_0F99_P_0_LEN_0,
1478 VEX_W_0F99_P_2_LEN_0,
1479 VEX_W_0F380C,
1480 VEX_W_0F380D,
1481 VEX_W_0F380E,
1482 VEX_W_0F380F,
1483 VEX_W_0F3813,
1484 VEX_W_0F3816_L_1,
1485 VEX_W_0F3818,
1486 VEX_W_0F3819_L_1,
1487 VEX_W_0F381A_M_0_L_1,
1488 VEX_W_0F382C_M_0,
1489 VEX_W_0F382D_M_0,
1490 VEX_W_0F382E_M_0,
1491 VEX_W_0F382F_M_0,
1492 VEX_W_0F3836,
1493 VEX_W_0F3846,
1494 VEX_W_0F3849_X86_64_P_0,
1495 VEX_W_0F3849_X86_64_P_2,
1496 VEX_W_0F3849_X86_64_P_3,
1497 VEX_W_0F384B_X86_64_P_1,
1498 VEX_W_0F384B_X86_64_P_2,
1499 VEX_W_0F384B_X86_64_P_3,
1500 VEX_W_0F3858,
1501 VEX_W_0F3859,
1502 VEX_W_0F385A_M_0_L_0,
1503 VEX_W_0F385C_X86_64_P_1,
1504 VEX_W_0F385E_X86_64_P_0,
1505 VEX_W_0F385E_X86_64_P_1,
1506 VEX_W_0F385E_X86_64_P_2,
1507 VEX_W_0F385E_X86_64_P_3,
1508 VEX_W_0F3878,
1509 VEX_W_0F3879,
1510 VEX_W_0F38CF,
1511 VEX_W_0F3A00_L_1,
1512 VEX_W_0F3A01_L_1,
1513 VEX_W_0F3A02,
1514 VEX_W_0F3A04,
1515 VEX_W_0F3A05,
1516 VEX_W_0F3A06_L_1,
1517 VEX_W_0F3A18_L_1,
1518 VEX_W_0F3A19_L_1,
1519 VEX_W_0F3A1D,
1520 VEX_W_0F3A30_L_0,
1521 VEX_W_0F3A31_L_0,
1522 VEX_W_0F3A32_L_0,
1523 VEX_W_0F3A33_L_0,
1524 VEX_W_0F3A38_L_1,
1525 VEX_W_0F3A39_L_1,
1526 VEX_W_0F3A46_L_1,
1527 VEX_W_0F3A4A,
1528 VEX_W_0F3A4B,
1529 VEX_W_0F3A4C,
1530 VEX_W_0F3ACE,
1531 VEX_W_0F3ACF,
1532
1533 VEX_W_0FXOP_08_85_L_0,
1534 VEX_W_0FXOP_08_86_L_0,
1535 VEX_W_0FXOP_08_87_L_0,
1536 VEX_W_0FXOP_08_8E_L_0,
1537 VEX_W_0FXOP_08_8F_L_0,
1538 VEX_W_0FXOP_08_95_L_0,
1539 VEX_W_0FXOP_08_96_L_0,
1540 VEX_W_0FXOP_08_97_L_0,
1541 VEX_W_0FXOP_08_9E_L_0,
1542 VEX_W_0FXOP_08_9F_L_0,
1543 VEX_W_0FXOP_08_A6_L_0,
1544 VEX_W_0FXOP_08_B6_L_0,
1545 VEX_W_0FXOP_08_C0_L_0,
1546 VEX_W_0FXOP_08_C1_L_0,
1547 VEX_W_0FXOP_08_C2_L_0,
1548 VEX_W_0FXOP_08_C3_L_0,
1549 VEX_W_0FXOP_08_CC_L_0,
1550 VEX_W_0FXOP_08_CD_L_0,
1551 VEX_W_0FXOP_08_CE_L_0,
1552 VEX_W_0FXOP_08_CF_L_0,
1553 VEX_W_0FXOP_08_EC_L_0,
1554 VEX_W_0FXOP_08_ED_L_0,
1555 VEX_W_0FXOP_08_EE_L_0,
1556 VEX_W_0FXOP_08_EF_L_0,
1557
1558 VEX_W_0FXOP_09_80,
1559 VEX_W_0FXOP_09_81,
1560 VEX_W_0FXOP_09_82,
1561 VEX_W_0FXOP_09_83,
1562 VEX_W_0FXOP_09_C1_L_0,
1563 VEX_W_0FXOP_09_C2_L_0,
1564 VEX_W_0FXOP_09_C3_L_0,
1565 VEX_W_0FXOP_09_C6_L_0,
1566 VEX_W_0FXOP_09_C7_L_0,
1567 VEX_W_0FXOP_09_CB_L_0,
1568 VEX_W_0FXOP_09_D1_L_0,
1569 VEX_W_0FXOP_09_D2_L_0,
1570 VEX_W_0FXOP_09_D3_L_0,
1571 VEX_W_0FXOP_09_D6_L_0,
1572 VEX_W_0FXOP_09_D7_L_0,
1573 VEX_W_0FXOP_09_DB_L_0,
1574 VEX_W_0FXOP_09_E1_L_0,
1575 VEX_W_0FXOP_09_E2_L_0,
1576 VEX_W_0FXOP_09_E3_L_0,
1577
1578 EVEX_W_0F10_P_1,
1579 EVEX_W_0F10_P_3,
1580 EVEX_W_0F11_P_1,
1581 EVEX_W_0F11_P_3,
1582 EVEX_W_0F12_P_0_M_1,
1583 EVEX_W_0F12_P_1,
1584 EVEX_W_0F12_P_3,
1585 EVEX_W_0F16_P_0_M_1,
1586 EVEX_W_0F16_P_1,
1587 EVEX_W_0F2A_P_3,
1588 EVEX_W_0F51_P_1,
1589 EVEX_W_0F51_P_3,
1590 EVEX_W_0F58_P_1,
1591 EVEX_W_0F58_P_3,
1592 EVEX_W_0F59_P_1,
1593 EVEX_W_0F59_P_3,
1594 EVEX_W_0F5A_P_0,
1595 EVEX_W_0F5A_P_1,
1596 EVEX_W_0F5A_P_2,
1597 EVEX_W_0F5A_P_3,
1598 EVEX_W_0F5B_P_0,
1599 EVEX_W_0F5B_P_1,
1600 EVEX_W_0F5B_P_2,
1601 EVEX_W_0F5C_P_1,
1602 EVEX_W_0F5C_P_3,
1603 EVEX_W_0F5D_P_1,
1604 EVEX_W_0F5D_P_3,
1605 EVEX_W_0F5E_P_1,
1606 EVEX_W_0F5E_P_3,
1607 EVEX_W_0F5F_P_1,
1608 EVEX_W_0F5F_P_3,
1609 EVEX_W_0F62,
1610 EVEX_W_0F66,
1611 EVEX_W_0F6A,
1612 EVEX_W_0F6B,
1613 EVEX_W_0F6C,
1614 EVEX_W_0F6D,
1615 EVEX_W_0F6F_P_1,
1616 EVEX_W_0F6F_P_2,
1617 EVEX_W_0F6F_P_3,
1618 EVEX_W_0F70_P_2,
1619 EVEX_W_0F72_R_2,
1620 EVEX_W_0F72_R_6,
1621 EVEX_W_0F73_R_2,
1622 EVEX_W_0F73_R_6,
1623 EVEX_W_0F76,
1624 EVEX_W_0F78_P_0,
1625 EVEX_W_0F78_P_2,
1626 EVEX_W_0F79_P_0,
1627 EVEX_W_0F79_P_2,
1628 EVEX_W_0F7A_P_1,
1629 EVEX_W_0F7A_P_2,
1630 EVEX_W_0F7A_P_3,
1631 EVEX_W_0F7B_P_2,
1632 EVEX_W_0F7B_P_3,
1633 EVEX_W_0F7E_P_1,
1634 EVEX_W_0F7F_P_1,
1635 EVEX_W_0F7F_P_2,
1636 EVEX_W_0F7F_P_3,
1637 EVEX_W_0FC2_P_1,
1638 EVEX_W_0FC2_P_3,
1639 EVEX_W_0FD2,
1640 EVEX_W_0FD3,
1641 EVEX_W_0FD4,
1642 EVEX_W_0FD6_L_0,
1643 EVEX_W_0FE6_P_1,
1644 EVEX_W_0FE6_P_2,
1645 EVEX_W_0FE6_P_3,
1646 EVEX_W_0FE7,
1647 EVEX_W_0FF2,
1648 EVEX_W_0FF3,
1649 EVEX_W_0FF4,
1650 EVEX_W_0FFA,
1651 EVEX_W_0FFB,
1652 EVEX_W_0FFE,
1653 EVEX_W_0F380D,
1654 EVEX_W_0F3810_P_1,
1655 EVEX_W_0F3810_P_2,
1656 EVEX_W_0F3811_P_1,
1657 EVEX_W_0F3811_P_2,
1658 EVEX_W_0F3812_P_1,
1659 EVEX_W_0F3812_P_2,
1660 EVEX_W_0F3813_P_1,
1661 EVEX_W_0F3813_P_2,
1662 EVEX_W_0F3814_P_1,
1663 EVEX_W_0F3815_P_1,
1664 EVEX_W_0F3819,
1665 EVEX_W_0F381A,
1666 EVEX_W_0F381B,
1667 EVEX_W_0F381E,
1668 EVEX_W_0F381F,
1669 EVEX_W_0F3820_P_1,
1670 EVEX_W_0F3821_P_1,
1671 EVEX_W_0F3822_P_1,
1672 EVEX_W_0F3823_P_1,
1673 EVEX_W_0F3824_P_1,
1674 EVEX_W_0F3825_P_1,
1675 EVEX_W_0F3825_P_2,
1676 EVEX_W_0F3828_P_2,
1677 EVEX_W_0F3829_P_2,
1678 EVEX_W_0F382A_P_1,
1679 EVEX_W_0F382A_P_2,
1680 EVEX_W_0F382B,
1681 EVEX_W_0F3830_P_1,
1682 EVEX_W_0F3831_P_1,
1683 EVEX_W_0F3832_P_1,
1684 EVEX_W_0F3833_P_1,
1685 EVEX_W_0F3834_P_1,
1686 EVEX_W_0F3835_P_1,
1687 EVEX_W_0F3835_P_2,
1688 EVEX_W_0F3837,
1689 EVEX_W_0F383A_P_1,
1690 EVEX_W_0F3852_P_1,
1691 EVEX_W_0F3859,
1692 EVEX_W_0F385A,
1693 EVEX_W_0F385B,
1694 EVEX_W_0F3870,
1695 EVEX_W_0F3872_P_1,
1696 EVEX_W_0F3872_P_2,
1697 EVEX_W_0F3872_P_3,
1698 EVEX_W_0F387A,
1699 EVEX_W_0F387B,
1700 EVEX_W_0F3883,
1701 EVEX_W_0F3891,
1702 EVEX_W_0F3893,
1703 EVEX_W_0F38A1,
1704 EVEX_W_0F38A3,
1705 EVEX_W_0F38C7_R_1_M_0,
1706 EVEX_W_0F38C7_R_2_M_0,
1707 EVEX_W_0F38C7_R_5_M_0,
1708 EVEX_W_0F38C7_R_6_M_0,
1709
1710 EVEX_W_0F3A00,
1711 EVEX_W_0F3A01,
1712 EVEX_W_0F3A05,
1713 EVEX_W_0F3A08,
1714 EVEX_W_0F3A09,
1715 EVEX_W_0F3A0A,
1716 EVEX_W_0F3A0B,
1717 EVEX_W_0F3A18,
1718 EVEX_W_0F3A19,
1719 EVEX_W_0F3A1A,
1720 EVEX_W_0F3A1B,
1721 EVEX_W_0F3A21,
1722 EVEX_W_0F3A23,
1723 EVEX_W_0F3A38,
1724 EVEX_W_0F3A39,
1725 EVEX_W_0F3A3A,
1726 EVEX_W_0F3A3B,
1727 EVEX_W_0F3A42,
1728 EVEX_W_0F3A43,
1729 EVEX_W_0F3A70,
1730 EVEX_W_0F3A72,
1731 };
1732
1733 typedef void (*op_rtn) (int bytemode, int sizeflag);
1734
1735 struct dis386 {
1736 const char *name;
1737 struct
1738 {
1739 op_rtn rtn;
1740 int bytemode;
1741 } op[MAX_OPERANDS];
1742 unsigned int prefix_requirement;
1743 };
1744
1745 /* Upper case letters in the instruction names here are macros.
1746 'A' => print 'b' if no register operands or suffix_always is true
1747 'B' => print 'b' if suffix_always is true
1748 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1749 size prefix
1750 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1751 suffix_always is true
1752 'E' => print 'e' if 32-bit form of jcxz
1753 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1754 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1755 'H' => print ",pt" or ",pn" branch hint
1756 'I' unused.
1757 'J' unused.
1758 'K' => print 'd' or 'q' if rex prefix is present.
1759 'L' => print 'l' if suffix_always is true
1760 'M' => print 'r' if intel_mnemonic is false.
1761 'N' => print 'n' if instruction has no wait "prefix"
1762 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1763 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1764 or suffix_always is true. print 'q' if rex prefix is present.
1765 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1766 is true
1767 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1768 'S' => print 'w', 'l' or 'q' if suffix_always is true
1769 'T' => print 'q' in 64bit mode if instruction has no operand size
1770 prefix and behave as 'P' otherwise
1771 'U' => print 'q' in 64bit mode if instruction has no operand size
1772 prefix and behave as 'Q' otherwise
1773 'V' => print 'q' in 64bit mode if instruction has no operand size
1774 prefix and behave as 'S' otherwise
1775 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1776 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1777 'Y' unused.
1778 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1779 '!' => change condition from true to false or from false to true.
1780 '%' => add 1 upper case letter to the macro.
1781 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1782 prefix or suffix_always is true (lcall/ljmp).
1783 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
1784 on operand size prefix.
1785 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
1786 has no operand size prefix for AMD64 ISA, behave as 'P'
1787 otherwise
1788
1789 2 upper case letter macros:
1790 "XY" => print 'x' or 'y' if suffix_always is true or no register
1791 operands and no broadcast.
1792 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1793 register operands and no broadcast.
1794 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1795 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1796 being false, or no operand at all in 64bit mode, or if suffix_always
1797 is true.
1798 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1799 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1800 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1801 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1802 "BW" => print 'b' or 'w' depending on the EVEX.W bit
1803 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1804 an operand size prefix, or suffix_always is true. print
1805 'q' if rex prefix is present.
1806
1807 Many of the above letters print nothing in Intel mode. See "putop"
1808 for the details.
1809
1810 Braces '{' and '}', and vertical bars '|', indicate alternative
1811 mnemonic strings for AT&T and Intel. */
1812
1813 static const struct dis386 dis386[] = {
1814 /* 00 */
1815 { "addB", { Ebh1, Gb }, 0 },
1816 { "addS", { Evh1, Gv }, 0 },
1817 { "addB", { Gb, EbS }, 0 },
1818 { "addS", { Gv, EvS }, 0 },
1819 { "addB", { AL, Ib }, 0 },
1820 { "addS", { eAX, Iv }, 0 },
1821 { X86_64_TABLE (X86_64_06) },
1822 { X86_64_TABLE (X86_64_07) },
1823 /* 08 */
1824 { "orB", { Ebh1, Gb }, 0 },
1825 { "orS", { Evh1, Gv }, 0 },
1826 { "orB", { Gb, EbS }, 0 },
1827 { "orS", { Gv, EvS }, 0 },
1828 { "orB", { AL, Ib }, 0 },
1829 { "orS", { eAX, Iv }, 0 },
1830 { X86_64_TABLE (X86_64_0E) },
1831 { Bad_Opcode }, /* 0x0f extended opcode escape */
1832 /* 10 */
1833 { "adcB", { Ebh1, Gb }, 0 },
1834 { "adcS", { Evh1, Gv }, 0 },
1835 { "adcB", { Gb, EbS }, 0 },
1836 { "adcS", { Gv, EvS }, 0 },
1837 { "adcB", { AL, Ib }, 0 },
1838 { "adcS", { eAX, Iv }, 0 },
1839 { X86_64_TABLE (X86_64_16) },
1840 { X86_64_TABLE (X86_64_17) },
1841 /* 18 */
1842 { "sbbB", { Ebh1, Gb }, 0 },
1843 { "sbbS", { Evh1, Gv }, 0 },
1844 { "sbbB", { Gb, EbS }, 0 },
1845 { "sbbS", { Gv, EvS }, 0 },
1846 { "sbbB", { AL, Ib }, 0 },
1847 { "sbbS", { eAX, Iv }, 0 },
1848 { X86_64_TABLE (X86_64_1E) },
1849 { X86_64_TABLE (X86_64_1F) },
1850 /* 20 */
1851 { "andB", { Ebh1, Gb }, 0 },
1852 { "andS", { Evh1, Gv }, 0 },
1853 { "andB", { Gb, EbS }, 0 },
1854 { "andS", { Gv, EvS }, 0 },
1855 { "andB", { AL, Ib }, 0 },
1856 { "andS", { eAX, Iv }, 0 },
1857 { Bad_Opcode }, /* SEG ES prefix */
1858 { X86_64_TABLE (X86_64_27) },
1859 /* 28 */
1860 { "subB", { Ebh1, Gb }, 0 },
1861 { "subS", { Evh1, Gv }, 0 },
1862 { "subB", { Gb, EbS }, 0 },
1863 { "subS", { Gv, EvS }, 0 },
1864 { "subB", { AL, Ib }, 0 },
1865 { "subS", { eAX, Iv }, 0 },
1866 { Bad_Opcode }, /* SEG CS prefix */
1867 { X86_64_TABLE (X86_64_2F) },
1868 /* 30 */
1869 { "xorB", { Ebh1, Gb }, 0 },
1870 { "xorS", { Evh1, Gv }, 0 },
1871 { "xorB", { Gb, EbS }, 0 },
1872 { "xorS", { Gv, EvS }, 0 },
1873 { "xorB", { AL, Ib }, 0 },
1874 { "xorS", { eAX, Iv }, 0 },
1875 { Bad_Opcode }, /* SEG SS prefix */
1876 { X86_64_TABLE (X86_64_37) },
1877 /* 38 */
1878 { "cmpB", { Eb, Gb }, 0 },
1879 { "cmpS", { Ev, Gv }, 0 },
1880 { "cmpB", { Gb, EbS }, 0 },
1881 { "cmpS", { Gv, EvS }, 0 },
1882 { "cmpB", { AL, Ib }, 0 },
1883 { "cmpS", { eAX, Iv }, 0 },
1884 { Bad_Opcode }, /* SEG DS prefix */
1885 { X86_64_TABLE (X86_64_3F) },
1886 /* 40 */
1887 { "inc{S|}", { RMeAX }, 0 },
1888 { "inc{S|}", { RMeCX }, 0 },
1889 { "inc{S|}", { RMeDX }, 0 },
1890 { "inc{S|}", { RMeBX }, 0 },
1891 { "inc{S|}", { RMeSP }, 0 },
1892 { "inc{S|}", { RMeBP }, 0 },
1893 { "inc{S|}", { RMeSI }, 0 },
1894 { "inc{S|}", { RMeDI }, 0 },
1895 /* 48 */
1896 { "dec{S|}", { RMeAX }, 0 },
1897 { "dec{S|}", { RMeCX }, 0 },
1898 { "dec{S|}", { RMeDX }, 0 },
1899 { "dec{S|}", { RMeBX }, 0 },
1900 { "dec{S|}", { RMeSP }, 0 },
1901 { "dec{S|}", { RMeBP }, 0 },
1902 { "dec{S|}", { RMeSI }, 0 },
1903 { "dec{S|}", { RMeDI }, 0 },
1904 /* 50 */
1905 { "pushV", { RMrAX }, 0 },
1906 { "pushV", { RMrCX }, 0 },
1907 { "pushV", { RMrDX }, 0 },
1908 { "pushV", { RMrBX }, 0 },
1909 { "pushV", { RMrSP }, 0 },
1910 { "pushV", { RMrBP }, 0 },
1911 { "pushV", { RMrSI }, 0 },
1912 { "pushV", { RMrDI }, 0 },
1913 /* 58 */
1914 { "popV", { RMrAX }, 0 },
1915 { "popV", { RMrCX }, 0 },
1916 { "popV", { RMrDX }, 0 },
1917 { "popV", { RMrBX }, 0 },
1918 { "popV", { RMrSP }, 0 },
1919 { "popV", { RMrBP }, 0 },
1920 { "popV", { RMrSI }, 0 },
1921 { "popV", { RMrDI }, 0 },
1922 /* 60 */
1923 { X86_64_TABLE (X86_64_60) },
1924 { X86_64_TABLE (X86_64_61) },
1925 { X86_64_TABLE (X86_64_62) },
1926 { X86_64_TABLE (X86_64_63) },
1927 { Bad_Opcode }, /* seg fs */
1928 { Bad_Opcode }, /* seg gs */
1929 { Bad_Opcode }, /* op size prefix */
1930 { Bad_Opcode }, /* adr size prefix */
1931 /* 68 */
1932 { "pushT", { sIv }, 0 },
1933 { "imulS", { Gv, Ev, Iv }, 0 },
1934 { "pushT", { sIbT }, 0 },
1935 { "imulS", { Gv, Ev, sIb }, 0 },
1936 { "ins{b|}", { Ybr, indirDX }, 0 },
1937 { X86_64_TABLE (X86_64_6D) },
1938 { "outs{b|}", { indirDXr, Xb }, 0 },
1939 { X86_64_TABLE (X86_64_6F) },
1940 /* 70 */
1941 { "joH", { Jb, BND, cond_jump_flag }, 0 },
1942 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
1943 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
1944 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
1945 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
1946 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
1947 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
1948 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
1949 /* 78 */
1950 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
1951 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
1952 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
1953 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
1954 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
1955 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
1956 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
1957 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
1958 /* 80 */
1959 { REG_TABLE (REG_80) },
1960 { REG_TABLE (REG_81) },
1961 { X86_64_TABLE (X86_64_82) },
1962 { REG_TABLE (REG_83) },
1963 { "testB", { Eb, Gb }, 0 },
1964 { "testS", { Ev, Gv }, 0 },
1965 { "xchgB", { Ebh2, Gb }, 0 },
1966 { "xchgS", { Evh2, Gv }, 0 },
1967 /* 88 */
1968 { "movB", { Ebh3, Gb }, 0 },
1969 { "movS", { Evh3, Gv }, 0 },
1970 { "movB", { Gb, EbS }, 0 },
1971 { "movS", { Gv, EvS }, 0 },
1972 { "movD", { Sv, Sw }, 0 },
1973 { MOD_TABLE (MOD_8D) },
1974 { "movD", { Sw, Sv }, 0 },
1975 { REG_TABLE (REG_8F) },
1976 /* 90 */
1977 { PREFIX_TABLE (PREFIX_90) },
1978 { "xchgS", { RMeCX, eAX }, 0 },
1979 { "xchgS", { RMeDX, eAX }, 0 },
1980 { "xchgS", { RMeBX, eAX }, 0 },
1981 { "xchgS", { RMeSP, eAX }, 0 },
1982 { "xchgS", { RMeBP, eAX }, 0 },
1983 { "xchgS", { RMeSI, eAX }, 0 },
1984 { "xchgS", { RMeDI, eAX }, 0 },
1985 /* 98 */
1986 { "cW{t|}R", { XX }, 0 },
1987 { "cR{t|}O", { XX }, 0 },
1988 { X86_64_TABLE (X86_64_9A) },
1989 { Bad_Opcode }, /* fwait */
1990 { "pushfT", { XX }, 0 },
1991 { "popfT", { XX }, 0 },
1992 { "sahf", { XX }, 0 },
1993 { "lahf", { XX }, 0 },
1994 /* a0 */
1995 { "mov%LB", { AL, Ob }, 0 },
1996 { "mov%LS", { eAX, Ov }, 0 },
1997 { "mov%LB", { Ob, AL }, 0 },
1998 { "mov%LS", { Ov, eAX }, 0 },
1999 { "movs{b|}", { Ybr, Xb }, 0 },
2000 { "movs{R|}", { Yvr, Xv }, 0 },
2001 { "cmps{b|}", { Xb, Yb }, 0 },
2002 { "cmps{R|}", { Xv, Yv }, 0 },
2003 /* a8 */
2004 { "testB", { AL, Ib }, 0 },
2005 { "testS", { eAX, Iv }, 0 },
2006 { "stosB", { Ybr, AL }, 0 },
2007 { "stosS", { Yvr, eAX }, 0 },
2008 { "lodsB", { ALr, Xb }, 0 },
2009 { "lodsS", { eAXr, Xv }, 0 },
2010 { "scasB", { AL, Yb }, 0 },
2011 { "scasS", { eAX, Yv }, 0 },
2012 /* b0 */
2013 { "movB", { RMAL, Ib }, 0 },
2014 { "movB", { RMCL, Ib }, 0 },
2015 { "movB", { RMDL, Ib }, 0 },
2016 { "movB", { RMBL, Ib }, 0 },
2017 { "movB", { RMAH, Ib }, 0 },
2018 { "movB", { RMCH, Ib }, 0 },
2019 { "movB", { RMDH, Ib }, 0 },
2020 { "movB", { RMBH, Ib }, 0 },
2021 /* b8 */
2022 { "mov%LV", { RMeAX, Iv64 }, 0 },
2023 { "mov%LV", { RMeCX, Iv64 }, 0 },
2024 { "mov%LV", { RMeDX, Iv64 }, 0 },
2025 { "mov%LV", { RMeBX, Iv64 }, 0 },
2026 { "mov%LV", { RMeSP, Iv64 }, 0 },
2027 { "mov%LV", { RMeBP, Iv64 }, 0 },
2028 { "mov%LV", { RMeSI, Iv64 }, 0 },
2029 { "mov%LV", { RMeDI, Iv64 }, 0 },
2030 /* c0 */
2031 { REG_TABLE (REG_C0) },
2032 { REG_TABLE (REG_C1) },
2033 { X86_64_TABLE (X86_64_C2) },
2034 { X86_64_TABLE (X86_64_C3) },
2035 { X86_64_TABLE (X86_64_C4) },
2036 { X86_64_TABLE (X86_64_C5) },
2037 { REG_TABLE (REG_C6) },
2038 { REG_TABLE (REG_C7) },
2039 /* c8 */
2040 { "enterT", { Iw, Ib }, 0 },
2041 { "leaveT", { XX }, 0 },
2042 { "{l|}ret{|f}P", { Iw }, 0 },
2043 { "{l|}ret{|f}P", { XX }, 0 },
2044 { "int3", { XX }, 0 },
2045 { "int", { Ib }, 0 },
2046 { X86_64_TABLE (X86_64_CE) },
2047 { "iret%LP", { XX }, 0 },
2048 /* d0 */
2049 { REG_TABLE (REG_D0) },
2050 { REG_TABLE (REG_D1) },
2051 { REG_TABLE (REG_D2) },
2052 { REG_TABLE (REG_D3) },
2053 { X86_64_TABLE (X86_64_D4) },
2054 { X86_64_TABLE (X86_64_D5) },
2055 { Bad_Opcode },
2056 { "xlat", { DSBX }, 0 },
2057 /* d8 */
2058 { FLOAT },
2059 { FLOAT },
2060 { FLOAT },
2061 { FLOAT },
2062 { FLOAT },
2063 { FLOAT },
2064 { FLOAT },
2065 { FLOAT },
2066 /* e0 */
2067 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2068 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2069 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2070 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2071 { "inB", { AL, Ib }, 0 },
2072 { "inG", { zAX, Ib }, 0 },
2073 { "outB", { Ib, AL }, 0 },
2074 { "outG", { Ib, zAX }, 0 },
2075 /* e8 */
2076 { X86_64_TABLE (X86_64_E8) },
2077 { X86_64_TABLE (X86_64_E9) },
2078 { X86_64_TABLE (X86_64_EA) },
2079 { "jmp", { Jb, BND }, 0 },
2080 { "inB", { AL, indirDX }, 0 },
2081 { "inG", { zAX, indirDX }, 0 },
2082 { "outB", { indirDX, AL }, 0 },
2083 { "outG", { indirDX, zAX }, 0 },
2084 /* f0 */
2085 { Bad_Opcode }, /* lock prefix */
2086 { "icebp", { XX }, 0 },
2087 { Bad_Opcode }, /* repne */
2088 { Bad_Opcode }, /* repz */
2089 { "hlt", { XX }, 0 },
2090 { "cmc", { XX }, 0 },
2091 { REG_TABLE (REG_F6) },
2092 { REG_TABLE (REG_F7) },
2093 /* f8 */
2094 { "clc", { XX }, 0 },
2095 { "stc", { XX }, 0 },
2096 { "cli", { XX }, 0 },
2097 { "sti", { XX }, 0 },
2098 { "cld", { XX }, 0 },
2099 { "std", { XX }, 0 },
2100 { REG_TABLE (REG_FE) },
2101 { REG_TABLE (REG_FF) },
2102 };
2103
2104 static const struct dis386 dis386_twobyte[] = {
2105 /* 00 */
2106 { REG_TABLE (REG_0F00 ) },
2107 { REG_TABLE (REG_0F01 ) },
2108 { "larS", { Gv, Ew }, 0 },
2109 { "lslS", { Gv, Ew }, 0 },
2110 { Bad_Opcode },
2111 { "syscall", { XX }, 0 },
2112 { "clts", { XX }, 0 },
2113 { "sysret%LQ", { XX }, 0 },
2114 /* 08 */
2115 { "invd", { XX }, 0 },
2116 { PREFIX_TABLE (PREFIX_0F09) },
2117 { Bad_Opcode },
2118 { "ud2", { XX }, 0 },
2119 { Bad_Opcode },
2120 { REG_TABLE (REG_0F0D) },
2121 { "femms", { XX }, 0 },
2122 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2123 /* 10 */
2124 { PREFIX_TABLE (PREFIX_0F10) },
2125 { PREFIX_TABLE (PREFIX_0F11) },
2126 { PREFIX_TABLE (PREFIX_0F12) },
2127 { MOD_TABLE (MOD_0F13) },
2128 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2129 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2130 { PREFIX_TABLE (PREFIX_0F16) },
2131 { MOD_TABLE (MOD_0F17) },
2132 /* 18 */
2133 { REG_TABLE (REG_0F18) },
2134 { "nopQ", { Ev }, 0 },
2135 { PREFIX_TABLE (PREFIX_0F1A) },
2136 { PREFIX_TABLE (PREFIX_0F1B) },
2137 { PREFIX_TABLE (PREFIX_0F1C) },
2138 { "nopQ", { Ev }, 0 },
2139 { PREFIX_TABLE (PREFIX_0F1E) },
2140 { "nopQ", { Ev }, 0 },
2141 /* 20 */
2142 { "movZ", { Rm, Cm }, 0 },
2143 { "movZ", { Rm, Dm }, 0 },
2144 { "movZ", { Cm, Rm }, 0 },
2145 { "movZ", { Dm, Rm }, 0 },
2146 { MOD_TABLE (MOD_0F24) },
2147 { Bad_Opcode },
2148 { MOD_TABLE (MOD_0F26) },
2149 { Bad_Opcode },
2150 /* 28 */
2151 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2152 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2153 { PREFIX_TABLE (PREFIX_0F2A) },
2154 { PREFIX_TABLE (PREFIX_0F2B) },
2155 { PREFIX_TABLE (PREFIX_0F2C) },
2156 { PREFIX_TABLE (PREFIX_0F2D) },
2157 { PREFIX_TABLE (PREFIX_0F2E) },
2158 { PREFIX_TABLE (PREFIX_0F2F) },
2159 /* 30 */
2160 { "wrmsr", { XX }, 0 },
2161 { "rdtsc", { XX }, 0 },
2162 { "rdmsr", { XX }, 0 },
2163 { "rdpmc", { XX }, 0 },
2164 { "sysenter", { SEP }, 0 },
2165 { "sysexit", { SEP }, 0 },
2166 { Bad_Opcode },
2167 { "getsec", { XX }, 0 },
2168 /* 38 */
2169 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2170 { Bad_Opcode },
2171 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2172 { Bad_Opcode },
2173 { Bad_Opcode },
2174 { Bad_Opcode },
2175 { Bad_Opcode },
2176 { Bad_Opcode },
2177 /* 40 */
2178 { "cmovoS", { Gv, Ev }, 0 },
2179 { "cmovnoS", { Gv, Ev }, 0 },
2180 { "cmovbS", { Gv, Ev }, 0 },
2181 { "cmovaeS", { Gv, Ev }, 0 },
2182 { "cmoveS", { Gv, Ev }, 0 },
2183 { "cmovneS", { Gv, Ev }, 0 },
2184 { "cmovbeS", { Gv, Ev }, 0 },
2185 { "cmovaS", { Gv, Ev }, 0 },
2186 /* 48 */
2187 { "cmovsS", { Gv, Ev }, 0 },
2188 { "cmovnsS", { Gv, Ev }, 0 },
2189 { "cmovpS", { Gv, Ev }, 0 },
2190 { "cmovnpS", { Gv, Ev }, 0 },
2191 { "cmovlS", { Gv, Ev }, 0 },
2192 { "cmovgeS", { Gv, Ev }, 0 },
2193 { "cmovleS", { Gv, Ev }, 0 },
2194 { "cmovgS", { Gv, Ev }, 0 },
2195 /* 50 */
2196 { MOD_TABLE (MOD_0F50) },
2197 { PREFIX_TABLE (PREFIX_0F51) },
2198 { PREFIX_TABLE (PREFIX_0F52) },
2199 { PREFIX_TABLE (PREFIX_0F53) },
2200 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2201 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2202 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2203 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2204 /* 58 */
2205 { PREFIX_TABLE (PREFIX_0F58) },
2206 { PREFIX_TABLE (PREFIX_0F59) },
2207 { PREFIX_TABLE (PREFIX_0F5A) },
2208 { PREFIX_TABLE (PREFIX_0F5B) },
2209 { PREFIX_TABLE (PREFIX_0F5C) },
2210 { PREFIX_TABLE (PREFIX_0F5D) },
2211 { PREFIX_TABLE (PREFIX_0F5E) },
2212 { PREFIX_TABLE (PREFIX_0F5F) },
2213 /* 60 */
2214 { PREFIX_TABLE (PREFIX_0F60) },
2215 { PREFIX_TABLE (PREFIX_0F61) },
2216 { PREFIX_TABLE (PREFIX_0F62) },
2217 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2218 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2219 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2220 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2221 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2222 /* 68 */
2223 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2224 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2225 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2226 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2227 { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2228 { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2229 { "movK", { MX, Edq }, PREFIX_OPCODE },
2230 { PREFIX_TABLE (PREFIX_0F6F) },
2231 /* 70 */
2232 { PREFIX_TABLE (PREFIX_0F70) },
2233 { REG_TABLE (REG_0F71) },
2234 { REG_TABLE (REG_0F72) },
2235 { REG_TABLE (REG_0F73) },
2236 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2237 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2238 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2239 { "emms", { XX }, PREFIX_OPCODE },
2240 /* 78 */
2241 { PREFIX_TABLE (PREFIX_0F78) },
2242 { PREFIX_TABLE (PREFIX_0F79) },
2243 { Bad_Opcode },
2244 { Bad_Opcode },
2245 { PREFIX_TABLE (PREFIX_0F7C) },
2246 { PREFIX_TABLE (PREFIX_0F7D) },
2247 { PREFIX_TABLE (PREFIX_0F7E) },
2248 { PREFIX_TABLE (PREFIX_0F7F) },
2249 /* 80 */
2250 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2251 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2252 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2253 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2254 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2255 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2256 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2257 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2258 /* 88 */
2259 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2260 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2261 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2262 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2263 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2264 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2265 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2266 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2267 /* 90 */
2268 { "seto", { Eb }, 0 },
2269 { "setno", { Eb }, 0 },
2270 { "setb", { Eb }, 0 },
2271 { "setae", { Eb }, 0 },
2272 { "sete", { Eb }, 0 },
2273 { "setne", { Eb }, 0 },
2274 { "setbe", { Eb }, 0 },
2275 { "seta", { Eb }, 0 },
2276 /* 98 */
2277 { "sets", { Eb }, 0 },
2278 { "setns", { Eb }, 0 },
2279 { "setp", { Eb }, 0 },
2280 { "setnp", { Eb }, 0 },
2281 { "setl", { Eb }, 0 },
2282 { "setge", { Eb }, 0 },
2283 { "setle", { Eb }, 0 },
2284 { "setg", { Eb }, 0 },
2285 /* a0 */
2286 { "pushT", { fs }, 0 },
2287 { "popT", { fs }, 0 },
2288 { "cpuid", { XX }, 0 },
2289 { "btS", { Ev, Gv }, 0 },
2290 { "shldS", { Ev, Gv, Ib }, 0 },
2291 { "shldS", { Ev, Gv, CL }, 0 },
2292 { REG_TABLE (REG_0FA6) },
2293 { REG_TABLE (REG_0FA7) },
2294 /* a8 */
2295 { "pushT", { gs }, 0 },
2296 { "popT", { gs }, 0 },
2297 { "rsm", { XX }, 0 },
2298 { "btsS", { Evh1, Gv }, 0 },
2299 { "shrdS", { Ev, Gv, Ib }, 0 },
2300 { "shrdS", { Ev, Gv, CL }, 0 },
2301 { REG_TABLE (REG_0FAE) },
2302 { "imulS", { Gv, Ev }, 0 },
2303 /* b0 */
2304 { "cmpxchgB", { Ebh1, Gb }, 0 },
2305 { "cmpxchgS", { Evh1, Gv }, 0 },
2306 { MOD_TABLE (MOD_0FB2) },
2307 { "btrS", { Evh1, Gv }, 0 },
2308 { MOD_TABLE (MOD_0FB4) },
2309 { MOD_TABLE (MOD_0FB5) },
2310 { "movz{bR|x}", { Gv, Eb }, 0 },
2311 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2312 /* b8 */
2313 { PREFIX_TABLE (PREFIX_0FB8) },
2314 { "ud1S", { Gv, Ev }, 0 },
2315 { REG_TABLE (REG_0FBA) },
2316 { "btcS", { Evh1, Gv }, 0 },
2317 { PREFIX_TABLE (PREFIX_0FBC) },
2318 { PREFIX_TABLE (PREFIX_0FBD) },
2319 { "movs{bR|x}", { Gv, Eb }, 0 },
2320 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2321 /* c0 */
2322 { "xaddB", { Ebh1, Gb }, 0 },
2323 { "xaddS", { Evh1, Gv }, 0 },
2324 { PREFIX_TABLE (PREFIX_0FC2) },
2325 { MOD_TABLE (MOD_0FC3) },
2326 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
2327 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
2328 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2329 { REG_TABLE (REG_0FC7) },
2330 /* c8 */
2331 { "bswap", { RMeAX }, 0 },
2332 { "bswap", { RMeCX }, 0 },
2333 { "bswap", { RMeDX }, 0 },
2334 { "bswap", { RMeBX }, 0 },
2335 { "bswap", { RMeSP }, 0 },
2336 { "bswap", { RMeBP }, 0 },
2337 { "bswap", { RMeSI }, 0 },
2338 { "bswap", { RMeDI }, 0 },
2339 /* d0 */
2340 { PREFIX_TABLE (PREFIX_0FD0) },
2341 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2342 { "psrld", { MX, EM }, PREFIX_OPCODE },
2343 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2344 { "paddq", { MX, EM }, PREFIX_OPCODE },
2345 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2346 { PREFIX_TABLE (PREFIX_0FD6) },
2347 { MOD_TABLE (MOD_0FD7) },
2348 /* d8 */
2349 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2350 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2351 { "pminub", { MX, EM }, PREFIX_OPCODE },
2352 { "pand", { MX, EM }, PREFIX_OPCODE },
2353 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2354 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2355 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2356 { "pandn", { MX, EM }, PREFIX_OPCODE },
2357 /* e0 */
2358 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2359 { "psraw", { MX, EM }, PREFIX_OPCODE },
2360 { "psrad", { MX, EM }, PREFIX_OPCODE },
2361 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2362 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2363 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2364 { PREFIX_TABLE (PREFIX_0FE6) },
2365 { PREFIX_TABLE (PREFIX_0FE7) },
2366 /* e8 */
2367 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2368 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2369 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2370 { "por", { MX, EM }, PREFIX_OPCODE },
2371 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2372 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2373 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2374 { "pxor", { MX, EM }, PREFIX_OPCODE },
2375 /* f0 */
2376 { PREFIX_TABLE (PREFIX_0FF0) },
2377 { "psllw", { MX, EM }, PREFIX_OPCODE },
2378 { "pslld", { MX, EM }, PREFIX_OPCODE },
2379 { "psllq", { MX, EM }, PREFIX_OPCODE },
2380 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2381 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2382 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2383 { PREFIX_TABLE (PREFIX_0FF7) },
2384 /* f8 */
2385 { "psubb", { MX, EM }, PREFIX_OPCODE },
2386 { "psubw", { MX, EM }, PREFIX_OPCODE },
2387 { "psubd", { MX, EM }, PREFIX_OPCODE },
2388 { "psubq", { MX, EM }, PREFIX_OPCODE },
2389 { "paddb", { MX, EM }, PREFIX_OPCODE },
2390 { "paddw", { MX, EM }, PREFIX_OPCODE },
2391 { "paddd", { MX, EM }, PREFIX_OPCODE },
2392 { "ud0S", { Gv, Ev }, 0 },
2393 };
2394
2395 static const unsigned char onebyte_has_modrm[256] = {
2396 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2397 /* ------------------------------- */
2398 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2399 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2400 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2401 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2402 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2403 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2404 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2405 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2406 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2407 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2408 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2409 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2410 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2411 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2412 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2413 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2414 /* ------------------------------- */
2415 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2416 };
2417
2418 static const unsigned char twobyte_has_modrm[256] = {
2419 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2420 /* ------------------------------- */
2421 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2422 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2423 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2424 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2425 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2426 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2427 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2428 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2429 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2430 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2431 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2432 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2433 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2434 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2435 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2436 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2437 /* ------------------------------- */
2438 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2439 };
2440
2441 static char obuf[100];
2442 static char *obufp;
2443 static char *mnemonicendp;
2444 static char scratchbuf[100];
2445 static unsigned char *start_codep;
2446 static unsigned char *insn_codep;
2447 static unsigned char *codep;
2448 static unsigned char *end_codep;
2449 static int last_lock_prefix;
2450 static int last_repz_prefix;
2451 static int last_repnz_prefix;
2452 static int last_data_prefix;
2453 static int last_addr_prefix;
2454 static int last_rex_prefix;
2455 static int last_seg_prefix;
2456 static int fwait_prefix;
2457 /* The active segment register prefix. */
2458 static int active_seg_prefix;
2459 #define MAX_CODE_LENGTH 15
2460 /* We can up to 14 prefixes since the maximum instruction length is
2461 15bytes. */
2462 static int all_prefixes[MAX_CODE_LENGTH - 1];
2463 static disassemble_info *the_info;
2464 static struct
2465 {
2466 int mod;
2467 int reg;
2468 int rm;
2469 }
2470 modrm;
2471 static unsigned char need_modrm;
2472 static struct
2473 {
2474 int scale;
2475 int index;
2476 int base;
2477 }
2478 sib;
2479 static struct
2480 {
2481 int register_specifier;
2482 int length;
2483 int prefix;
2484 int w;
2485 int evex;
2486 int r;
2487 int v;
2488 int mask_register_specifier;
2489 int zeroing;
2490 int ll;
2491 int b;
2492 }
2493 vex;
2494 static unsigned char need_vex;
2495
2496 struct op
2497 {
2498 const char *name;
2499 unsigned int len;
2500 };
2501
2502 /* If we are accessing mod/rm/reg without need_modrm set, then the
2503 values are stale. Hitting this abort likely indicates that you
2504 need to update onebyte_has_modrm or twobyte_has_modrm. */
2505 #define MODRM_CHECK if (!need_modrm) abort ()
2506
2507 static const char **names64;
2508 static const char **names32;
2509 static const char **names16;
2510 static const char **names8;
2511 static const char **names8rex;
2512 static const char **names_seg;
2513 static const char *index64;
2514 static const char *index32;
2515 static const char **index16;
2516 static const char **names_bnd;
2517
2518 static const char *intel_names64[] = {
2519 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2520 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2521 };
2522 static const char *intel_names32[] = {
2523 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2524 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2525 };
2526 static const char *intel_names16[] = {
2527 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2528 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2529 };
2530 static const char *intel_names8[] = {
2531 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2532 };
2533 static const char *intel_names8rex[] = {
2534 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2535 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2536 };
2537 static const char *intel_names_seg[] = {
2538 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2539 };
2540 static const char *intel_index64 = "riz";
2541 static const char *intel_index32 = "eiz";
2542 static const char *intel_index16[] = {
2543 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2544 };
2545
2546 static const char *att_names64[] = {
2547 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2548 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2549 };
2550 static const char *att_names32[] = {
2551 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2552 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2553 };
2554 static const char *att_names16[] = {
2555 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2556 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2557 };
2558 static const char *att_names8[] = {
2559 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2560 };
2561 static const char *att_names8rex[] = {
2562 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2563 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2564 };
2565 static const char *att_names_seg[] = {
2566 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2567 };
2568 static const char *att_index64 = "%riz";
2569 static const char *att_index32 = "%eiz";
2570 static const char *att_index16[] = {
2571 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2572 };
2573
2574 static const char **names_mm;
2575 static const char *intel_names_mm[] = {
2576 "mm0", "mm1", "mm2", "mm3",
2577 "mm4", "mm5", "mm6", "mm7"
2578 };
2579 static const char *att_names_mm[] = {
2580 "%mm0", "%mm1", "%mm2", "%mm3",
2581 "%mm4", "%mm5", "%mm6", "%mm7"
2582 };
2583
2584 static const char *intel_names_bnd[] = {
2585 "bnd0", "bnd1", "bnd2", "bnd3"
2586 };
2587
2588 static const char *att_names_bnd[] = {
2589 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2590 };
2591
2592 static const char **names_xmm;
2593 static const char *intel_names_xmm[] = {
2594 "xmm0", "xmm1", "xmm2", "xmm3",
2595 "xmm4", "xmm5", "xmm6", "xmm7",
2596 "xmm8", "xmm9", "xmm10", "xmm11",
2597 "xmm12", "xmm13", "xmm14", "xmm15",
2598 "xmm16", "xmm17", "xmm18", "xmm19",
2599 "xmm20", "xmm21", "xmm22", "xmm23",
2600 "xmm24", "xmm25", "xmm26", "xmm27",
2601 "xmm28", "xmm29", "xmm30", "xmm31"
2602 };
2603 static const char *att_names_xmm[] = {
2604 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2605 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2606 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2607 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2608 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2609 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2610 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2611 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2612 };
2613
2614 static const char **names_ymm;
2615 static const char *intel_names_ymm[] = {
2616 "ymm0", "ymm1", "ymm2", "ymm3",
2617 "ymm4", "ymm5", "ymm6", "ymm7",
2618 "ymm8", "ymm9", "ymm10", "ymm11",
2619 "ymm12", "ymm13", "ymm14", "ymm15",
2620 "ymm16", "ymm17", "ymm18", "ymm19",
2621 "ymm20", "ymm21", "ymm22", "ymm23",
2622 "ymm24", "ymm25", "ymm26", "ymm27",
2623 "ymm28", "ymm29", "ymm30", "ymm31"
2624 };
2625 static const char *att_names_ymm[] = {
2626 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2627 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2628 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2629 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2630 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2631 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2632 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2633 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2634 };
2635
2636 static const char **names_zmm;
2637 static const char *intel_names_zmm[] = {
2638 "zmm0", "zmm1", "zmm2", "zmm3",
2639 "zmm4", "zmm5", "zmm6", "zmm7",
2640 "zmm8", "zmm9", "zmm10", "zmm11",
2641 "zmm12", "zmm13", "zmm14", "zmm15",
2642 "zmm16", "zmm17", "zmm18", "zmm19",
2643 "zmm20", "zmm21", "zmm22", "zmm23",
2644 "zmm24", "zmm25", "zmm26", "zmm27",
2645 "zmm28", "zmm29", "zmm30", "zmm31"
2646 };
2647 static const char *att_names_zmm[] = {
2648 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2649 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2650 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2651 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2652 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2653 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2654 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2655 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2656 };
2657
2658 static const char **names_tmm;
2659 static const char *intel_names_tmm[] = {
2660 "tmm0", "tmm1", "tmm2", "tmm3",
2661 "tmm4", "tmm5", "tmm6", "tmm7"
2662 };
2663 static const char *att_names_tmm[] = {
2664 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2665 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2666 };
2667
2668 static const char **names_mask;
2669 static const char *intel_names_mask[] = {
2670 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2671 };
2672 static const char *att_names_mask[] = {
2673 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2674 };
2675
2676 static const char *names_rounding[] =
2677 {
2678 "{rn-sae}",
2679 "{rd-sae}",
2680 "{ru-sae}",
2681 "{rz-sae}"
2682 };
2683
2684 static const struct dis386 reg_table[][8] = {
2685 /* REG_80 */
2686 {
2687 { "addA", { Ebh1, Ib }, 0 },
2688 { "orA", { Ebh1, Ib }, 0 },
2689 { "adcA", { Ebh1, Ib }, 0 },
2690 { "sbbA", { Ebh1, Ib }, 0 },
2691 { "andA", { Ebh1, Ib }, 0 },
2692 { "subA", { Ebh1, Ib }, 0 },
2693 { "xorA", { Ebh1, Ib }, 0 },
2694 { "cmpA", { Eb, Ib }, 0 },
2695 },
2696 /* REG_81 */
2697 {
2698 { "addQ", { Evh1, Iv }, 0 },
2699 { "orQ", { Evh1, Iv }, 0 },
2700 { "adcQ", { Evh1, Iv }, 0 },
2701 { "sbbQ", { Evh1, Iv }, 0 },
2702 { "andQ", { Evh1, Iv }, 0 },
2703 { "subQ", { Evh1, Iv }, 0 },
2704 { "xorQ", { Evh1, Iv }, 0 },
2705 { "cmpQ", { Ev, Iv }, 0 },
2706 },
2707 /* REG_83 */
2708 {
2709 { "addQ", { Evh1, sIb }, 0 },
2710 { "orQ", { Evh1, sIb }, 0 },
2711 { "adcQ", { Evh1, sIb }, 0 },
2712 { "sbbQ", { Evh1, sIb }, 0 },
2713 { "andQ", { Evh1, sIb }, 0 },
2714 { "subQ", { Evh1, sIb }, 0 },
2715 { "xorQ", { Evh1, sIb }, 0 },
2716 { "cmpQ", { Ev, sIb }, 0 },
2717 },
2718 /* REG_8F */
2719 {
2720 { "popU", { stackEv }, 0 },
2721 { XOP_8F_TABLE (XOP_09) },
2722 { Bad_Opcode },
2723 { Bad_Opcode },
2724 { Bad_Opcode },
2725 { XOP_8F_TABLE (XOP_09) },
2726 },
2727 /* REG_C0 */
2728 {
2729 { "rolA", { Eb, Ib }, 0 },
2730 { "rorA", { Eb, Ib }, 0 },
2731 { "rclA", { Eb, Ib }, 0 },
2732 { "rcrA", { Eb, Ib }, 0 },
2733 { "shlA", { Eb, Ib }, 0 },
2734 { "shrA", { Eb, Ib }, 0 },
2735 { "shlA", { Eb, Ib }, 0 },
2736 { "sarA", { Eb, Ib }, 0 },
2737 },
2738 /* REG_C1 */
2739 {
2740 { "rolQ", { Ev, Ib }, 0 },
2741 { "rorQ", { Ev, Ib }, 0 },
2742 { "rclQ", { Ev, Ib }, 0 },
2743 { "rcrQ", { Ev, Ib }, 0 },
2744 { "shlQ", { Ev, Ib }, 0 },
2745 { "shrQ", { Ev, Ib }, 0 },
2746 { "shlQ", { Ev, Ib }, 0 },
2747 { "sarQ", { Ev, Ib }, 0 },
2748 },
2749 /* REG_C6 */
2750 {
2751 { "movA", { Ebh3, Ib }, 0 },
2752 { Bad_Opcode },
2753 { Bad_Opcode },
2754 { Bad_Opcode },
2755 { Bad_Opcode },
2756 { Bad_Opcode },
2757 { Bad_Opcode },
2758 { MOD_TABLE (MOD_C6_REG_7) },
2759 },
2760 /* REG_C7 */
2761 {
2762 { "movQ", { Evh3, Iv }, 0 },
2763 { Bad_Opcode },
2764 { Bad_Opcode },
2765 { Bad_Opcode },
2766 { Bad_Opcode },
2767 { Bad_Opcode },
2768 { Bad_Opcode },
2769 { MOD_TABLE (MOD_C7_REG_7) },
2770 },
2771 /* REG_D0 */
2772 {
2773 { "rolA", { Eb, I1 }, 0 },
2774 { "rorA", { Eb, I1 }, 0 },
2775 { "rclA", { Eb, I1 }, 0 },
2776 { "rcrA", { Eb, I1 }, 0 },
2777 { "shlA", { Eb, I1 }, 0 },
2778 { "shrA", { Eb, I1 }, 0 },
2779 { "shlA", { Eb, I1 }, 0 },
2780 { "sarA", { Eb, I1 }, 0 },
2781 },
2782 /* REG_D1 */
2783 {
2784 { "rolQ", { Ev, I1 }, 0 },
2785 { "rorQ", { Ev, I1 }, 0 },
2786 { "rclQ", { Ev, I1 }, 0 },
2787 { "rcrQ", { Ev, I1 }, 0 },
2788 { "shlQ", { Ev, I1 }, 0 },
2789 { "shrQ", { Ev, I1 }, 0 },
2790 { "shlQ", { Ev, I1 }, 0 },
2791 { "sarQ", { Ev, I1 }, 0 },
2792 },
2793 /* REG_D2 */
2794 {
2795 { "rolA", { Eb, CL }, 0 },
2796 { "rorA", { Eb, CL }, 0 },
2797 { "rclA", { Eb, CL }, 0 },
2798 { "rcrA", { Eb, CL }, 0 },
2799 { "shlA", { Eb, CL }, 0 },
2800 { "shrA", { Eb, CL }, 0 },
2801 { "shlA", { Eb, CL }, 0 },
2802 { "sarA", { Eb, CL }, 0 },
2803 },
2804 /* REG_D3 */
2805 {
2806 { "rolQ", { Ev, CL }, 0 },
2807 { "rorQ", { Ev, CL }, 0 },
2808 { "rclQ", { Ev, CL }, 0 },
2809 { "rcrQ", { Ev, CL }, 0 },
2810 { "shlQ", { Ev, CL }, 0 },
2811 { "shrQ", { Ev, CL }, 0 },
2812 { "shlQ", { Ev, CL }, 0 },
2813 { "sarQ", { Ev, CL }, 0 },
2814 },
2815 /* REG_F6 */
2816 {
2817 { "testA", { Eb, Ib }, 0 },
2818 { "testA", { Eb, Ib }, 0 },
2819 { "notA", { Ebh1 }, 0 },
2820 { "negA", { Ebh1 }, 0 },
2821 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
2822 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
2823 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
2824 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
2825 },
2826 /* REG_F7 */
2827 {
2828 { "testQ", { Ev, Iv }, 0 },
2829 { "testQ", { Ev, Iv }, 0 },
2830 { "notQ", { Evh1 }, 0 },
2831 { "negQ", { Evh1 }, 0 },
2832 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
2833 { "imulQ", { Ev }, 0 },
2834 { "divQ", { Ev }, 0 },
2835 { "idivQ", { Ev }, 0 },
2836 },
2837 /* REG_FE */
2838 {
2839 { "incA", { Ebh1 }, 0 },
2840 { "decA", { Ebh1 }, 0 },
2841 },
2842 /* REG_FF */
2843 {
2844 { "incQ", { Evh1 }, 0 },
2845 { "decQ", { Evh1 }, 0 },
2846 { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
2847 { MOD_TABLE (MOD_FF_REG_3) },
2848 { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
2849 { MOD_TABLE (MOD_FF_REG_5) },
2850 { "pushU", { stackEv }, 0 },
2851 { Bad_Opcode },
2852 },
2853 /* REG_0F00 */
2854 {
2855 { "sldtD", { Sv }, 0 },
2856 { "strD", { Sv }, 0 },
2857 { "lldt", { Ew }, 0 },
2858 { "ltr", { Ew }, 0 },
2859 { "verr", { Ew }, 0 },
2860 { "verw", { Ew }, 0 },
2861 { Bad_Opcode },
2862 { Bad_Opcode },
2863 },
2864 /* REG_0F01 */
2865 {
2866 { MOD_TABLE (MOD_0F01_REG_0) },
2867 { MOD_TABLE (MOD_0F01_REG_1) },
2868 { MOD_TABLE (MOD_0F01_REG_2) },
2869 { MOD_TABLE (MOD_0F01_REG_3) },
2870 { "smswD", { Sv }, 0 },
2871 { MOD_TABLE (MOD_0F01_REG_5) },
2872 { "lmsw", { Ew }, 0 },
2873 { MOD_TABLE (MOD_0F01_REG_7) },
2874 },
2875 /* REG_0F0D */
2876 {
2877 { "prefetch", { Mb }, 0 },
2878 { "prefetchw", { Mb }, 0 },
2879 { "prefetchwt1", { Mb }, 0 },
2880 { "prefetch", { Mb }, 0 },
2881 { "prefetch", { Mb }, 0 },
2882 { "prefetch", { Mb }, 0 },
2883 { "prefetch", { Mb }, 0 },
2884 { "prefetch", { Mb }, 0 },
2885 },
2886 /* REG_0F18 */
2887 {
2888 { MOD_TABLE (MOD_0F18_REG_0) },
2889 { MOD_TABLE (MOD_0F18_REG_1) },
2890 { MOD_TABLE (MOD_0F18_REG_2) },
2891 { MOD_TABLE (MOD_0F18_REG_3) },
2892 { MOD_TABLE (MOD_0F18_REG_4) },
2893 { MOD_TABLE (MOD_0F18_REG_5) },
2894 { MOD_TABLE (MOD_0F18_REG_6) },
2895 { MOD_TABLE (MOD_0F18_REG_7) },
2896 },
2897 /* REG_0F1C_P_0_MOD_0 */
2898 {
2899 { "cldemote", { Mb }, 0 },
2900 { "nopQ", { Ev }, 0 },
2901 { "nopQ", { Ev }, 0 },
2902 { "nopQ", { Ev }, 0 },
2903 { "nopQ", { Ev }, 0 },
2904 { "nopQ", { Ev }, 0 },
2905 { "nopQ", { Ev }, 0 },
2906 { "nopQ", { Ev }, 0 },
2907 },
2908 /* REG_0F1E_P_1_MOD_3 */
2909 {
2910 { "nopQ", { Ev }, 0 },
2911 { "rdsspK", { Rdq }, PREFIX_OPCODE },
2912 { "nopQ", { Ev }, 0 },
2913 { "nopQ", { Ev }, 0 },
2914 { "nopQ", { Ev }, 0 },
2915 { "nopQ", { Ev }, 0 },
2916 { "nopQ", { Ev }, 0 },
2917 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2918 },
2919 /* REG_0F71 */
2920 {
2921 { Bad_Opcode },
2922 { Bad_Opcode },
2923 { MOD_TABLE (MOD_0F71_REG_2) },
2924 { Bad_Opcode },
2925 { MOD_TABLE (MOD_0F71_REG_4) },
2926 { Bad_Opcode },
2927 { MOD_TABLE (MOD_0F71_REG_6) },
2928 },
2929 /* REG_0F72 */
2930 {
2931 { Bad_Opcode },
2932 { Bad_Opcode },
2933 { MOD_TABLE (MOD_0F72_REG_2) },
2934 { Bad_Opcode },
2935 { MOD_TABLE (MOD_0F72_REG_4) },
2936 { Bad_Opcode },
2937 { MOD_TABLE (MOD_0F72_REG_6) },
2938 },
2939 /* REG_0F73 */
2940 {
2941 { Bad_Opcode },
2942 { Bad_Opcode },
2943 { MOD_TABLE (MOD_0F73_REG_2) },
2944 { MOD_TABLE (MOD_0F73_REG_3) },
2945 { Bad_Opcode },
2946 { Bad_Opcode },
2947 { MOD_TABLE (MOD_0F73_REG_6) },
2948 { MOD_TABLE (MOD_0F73_REG_7) },
2949 },
2950 /* REG_0FA6 */
2951 {
2952 { "montmul", { { OP_0f07, 0 } }, 0 },
2953 { "xsha1", { { OP_0f07, 0 } }, 0 },
2954 { "xsha256", { { OP_0f07, 0 } }, 0 },
2955 },
2956 /* REG_0FA7 */
2957 {
2958 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2959 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2960 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2961 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2962 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2963 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2964 },
2965 /* REG_0FAE */
2966 {
2967 { MOD_TABLE (MOD_0FAE_REG_0) },
2968 { MOD_TABLE (MOD_0FAE_REG_1) },
2969 { MOD_TABLE (MOD_0FAE_REG_2) },
2970 { MOD_TABLE (MOD_0FAE_REG_3) },
2971 { MOD_TABLE (MOD_0FAE_REG_4) },
2972 { MOD_TABLE (MOD_0FAE_REG_5) },
2973 { MOD_TABLE (MOD_0FAE_REG_6) },
2974 { MOD_TABLE (MOD_0FAE_REG_7) },
2975 },
2976 /* REG_0FBA */
2977 {
2978 { Bad_Opcode },
2979 { Bad_Opcode },
2980 { Bad_Opcode },
2981 { Bad_Opcode },
2982 { "btQ", { Ev, Ib }, 0 },
2983 { "btsQ", { Evh1, Ib }, 0 },
2984 { "btrQ", { Evh1, Ib }, 0 },
2985 { "btcQ", { Evh1, Ib }, 0 },
2986 },
2987 /* REG_0FC7 */
2988 {
2989 { Bad_Opcode },
2990 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2991 { Bad_Opcode },
2992 { MOD_TABLE (MOD_0FC7_REG_3) },
2993 { MOD_TABLE (MOD_0FC7_REG_4) },
2994 { MOD_TABLE (MOD_0FC7_REG_5) },
2995 { MOD_TABLE (MOD_0FC7_REG_6) },
2996 { MOD_TABLE (MOD_0FC7_REG_7) },
2997 },
2998 /* REG_VEX_0F71 */
2999 {
3000 { Bad_Opcode },
3001 { Bad_Opcode },
3002 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3003 { Bad_Opcode },
3004 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3005 { Bad_Opcode },
3006 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3007 },
3008 /* REG_VEX_0F72 */
3009 {
3010 { Bad_Opcode },
3011 { Bad_Opcode },
3012 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3013 { Bad_Opcode },
3014 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3015 { Bad_Opcode },
3016 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3017 },
3018 /* REG_VEX_0F73 */
3019 {
3020 { Bad_Opcode },
3021 { Bad_Opcode },
3022 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3023 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3024 { Bad_Opcode },
3025 { Bad_Opcode },
3026 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3027 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3028 },
3029 /* REG_VEX_0FAE */
3030 {
3031 { Bad_Opcode },
3032 { Bad_Opcode },
3033 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3034 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3035 },
3036 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3037 {
3038 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
3039 },
3040 /* REG_VEX_0F38F3 */
3041 {
3042 { Bad_Opcode },
3043 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3044 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3045 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3046 },
3047 /* REG_0FXOP_09_01_L_0 */
3048 {
3049 { Bad_Opcode },
3050 { "blcfill", { VexGdq, Edq }, 0 },
3051 { "blsfill", { VexGdq, Edq }, 0 },
3052 { "blcs", { VexGdq, Edq }, 0 },
3053 { "tzmsk", { VexGdq, Edq }, 0 },
3054 { "blcic", { VexGdq, Edq }, 0 },
3055 { "blsic", { VexGdq, Edq }, 0 },
3056 { "t1mskc", { VexGdq, Edq }, 0 },
3057 },
3058 /* REG_0FXOP_09_02_L_0 */
3059 {
3060 { Bad_Opcode },
3061 { "blcmsk", { VexGdq, Edq }, 0 },
3062 { Bad_Opcode },
3063 { Bad_Opcode },
3064 { Bad_Opcode },
3065 { Bad_Opcode },
3066 { "blci", { VexGdq, Edq }, 0 },
3067 },
3068 /* REG_0FXOP_09_12_M_1_L_0 */
3069 {
3070 { "llwpcb", { Edq }, 0 },
3071 { "slwpcb", { Edq }, 0 },
3072 },
3073 /* REG_0FXOP_0A_12_L_0 */
3074 {
3075 { "lwpins", { VexGdq, Ed, Id }, 0 },
3076 { "lwpval", { VexGdq, Ed, Id }, 0 },
3077 },
3078
3079 #include "i386-dis-evex-reg.h"
3080 };
3081
3082 static const struct dis386 prefix_table[][4] = {
3083 /* PREFIX_90 */
3084 {
3085 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3086 { "pause", { XX }, 0 },
3087 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3088 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3089 },
3090
3091 /* PREFIX_0F01_REG_3_RM_1 */
3092 {
3093 { "vmmcall", { Skip_MODRM }, 0 },
3094 { "vmgexit", { Skip_MODRM }, 0 },
3095 { Bad_Opcode },
3096 { "vmgexit", { Skip_MODRM }, 0 },
3097 },
3098
3099 /* PREFIX_0F01_REG_5_MOD_0 */
3100 {
3101 { Bad_Opcode },
3102 { "rstorssp", { Mq }, PREFIX_OPCODE },
3103 },
3104
3105 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3106 {
3107 { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
3108 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3109 { Bad_Opcode },
3110 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3111 },
3112
3113 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3114 {
3115 { Bad_Opcode },
3116 { Bad_Opcode },
3117 { Bad_Opcode },
3118 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3119 },
3120
3121 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3122 {
3123 { Bad_Opcode },
3124 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3125 },
3126
3127 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3128 {
3129 { "monitorx", { { OP_Monitor, 0 } }, 0 },
3130 { "mcommit", { Skip_MODRM }, 0 },
3131 },
3132
3133 /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3134 {
3135 { "mwaitx", { { OP_Mwait, eBX_reg } }, 0 },
3136 },
3137
3138 /* PREFIX_0F09 */
3139 {
3140 { "wbinvd", { XX }, 0 },
3141 { "wbnoinvd", { XX }, 0 },
3142 },
3143
3144 /* PREFIX_0F10 */
3145 {
3146 { "movups", { XM, EXx }, PREFIX_OPCODE },
3147 { "movss", { XM, EXd }, PREFIX_OPCODE },
3148 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3149 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3150 },
3151
3152 /* PREFIX_0F11 */
3153 {
3154 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3155 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3156 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3157 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3158 },
3159
3160 /* PREFIX_0F12 */
3161 {
3162 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3163 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3164 { MOD_TABLE (MOD_0F12_PREFIX_2) },
3165 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3166 },
3167
3168 /* PREFIX_0F16 */
3169 {
3170 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3171 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3172 { MOD_TABLE (MOD_0F16_PREFIX_2) },
3173 },
3174
3175 /* PREFIX_0F1A */
3176 {
3177 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3178 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3179 { "bndmov", { Gbnd, Ebnd }, 0 },
3180 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3181 },
3182
3183 /* PREFIX_0F1B */
3184 {
3185 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3186 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3187 { "bndmov", { EbndS, Gbnd }, 0 },
3188 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3189 },
3190
3191 /* PREFIX_0F1C */
3192 {
3193 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3194 { "nopQ", { Ev }, PREFIX_OPCODE },
3195 { "nopQ", { Ev }, PREFIX_OPCODE },
3196 { "nopQ", { Ev }, PREFIX_OPCODE },
3197 },
3198
3199 /* PREFIX_0F1E */
3200 {
3201 { "nopQ", { Ev }, PREFIX_OPCODE },
3202 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3203 { "nopQ", { Ev }, PREFIX_OPCODE },
3204 { "nopQ", { Ev }, PREFIX_OPCODE },
3205 },
3206
3207 /* PREFIX_0F2A */
3208 {
3209 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3210 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3211 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3212 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3213 },
3214
3215 /* PREFIX_0F2B */
3216 {
3217 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3218 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3219 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3220 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3221 },
3222
3223 /* PREFIX_0F2C */
3224 {
3225 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3226 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3227 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3228 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3229 },
3230
3231 /* PREFIX_0F2D */
3232 {
3233 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3234 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3235 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3236 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3237 },
3238
3239 /* PREFIX_0F2E */
3240 {
3241 { "ucomiss",{ XM, EXd }, 0 },
3242 { Bad_Opcode },
3243 { "ucomisd",{ XM, EXq }, 0 },
3244 },
3245
3246 /* PREFIX_0F2F */
3247 {
3248 { "comiss", { XM, EXd }, 0 },
3249 { Bad_Opcode },
3250 { "comisd", { XM, EXq }, 0 },
3251 },
3252
3253 /* PREFIX_0F51 */
3254 {
3255 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3256 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3257 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3258 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3259 },
3260
3261 /* PREFIX_0F52 */
3262 {
3263 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3264 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3265 },
3266
3267 /* PREFIX_0F53 */
3268 {
3269 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3270 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3271 },
3272
3273 /* PREFIX_0F58 */
3274 {
3275 { "addps", { XM, EXx }, PREFIX_OPCODE },
3276 { "addss", { XM, EXd }, PREFIX_OPCODE },
3277 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3278 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3279 },
3280
3281 /* PREFIX_0F59 */
3282 {
3283 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3284 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3285 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3286 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3287 },
3288
3289 /* PREFIX_0F5A */
3290 {
3291 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3292 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3293 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3294 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3295 },
3296
3297 /* PREFIX_0F5B */
3298 {
3299 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3300 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3301 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3302 },
3303
3304 /* PREFIX_0F5C */
3305 {
3306 { "subps", { XM, EXx }, PREFIX_OPCODE },
3307 { "subss", { XM, EXd }, PREFIX_OPCODE },
3308 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3309 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3310 },
3311
3312 /* PREFIX_0F5D */
3313 {
3314 { "minps", { XM, EXx }, PREFIX_OPCODE },
3315 { "minss", { XM, EXd }, PREFIX_OPCODE },
3316 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3317 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3318 },
3319
3320 /* PREFIX_0F5E */
3321 {
3322 { "divps", { XM, EXx }, PREFIX_OPCODE },
3323 { "divss", { XM, EXd }, PREFIX_OPCODE },
3324 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3325 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3326 },
3327
3328 /* PREFIX_0F5F */
3329 {
3330 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3331 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3332 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3333 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3334 },
3335
3336 /* PREFIX_0F60 */
3337 {
3338 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3339 { Bad_Opcode },
3340 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3341 },
3342
3343 /* PREFIX_0F61 */
3344 {
3345 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3346 { Bad_Opcode },
3347 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3348 },
3349
3350 /* PREFIX_0F62 */
3351 {
3352 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3353 { Bad_Opcode },
3354 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3355 },
3356
3357 /* PREFIX_0F6F */
3358 {
3359 { "movq", { MX, EM }, PREFIX_OPCODE },
3360 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3361 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3362 },
3363
3364 /* PREFIX_0F70 */
3365 {
3366 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3367 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3368 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3369 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3370 },
3371
3372 /* PREFIX_0F78 */
3373 {
3374 {"vmread", { Em, Gm }, 0 },
3375 { Bad_Opcode },
3376 {"extrq", { XS, Ib, Ib }, 0 },
3377 {"insertq", { XM, XS, Ib, Ib }, 0 },
3378 },
3379
3380 /* PREFIX_0F79 */
3381 {
3382 {"vmwrite", { Gm, Em }, 0 },
3383 { Bad_Opcode },
3384 {"extrq", { XM, XS }, 0 },
3385 {"insertq", { XM, XS }, 0 },
3386 },
3387
3388 /* PREFIX_0F7C */
3389 {
3390 { Bad_Opcode },
3391 { Bad_Opcode },
3392 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3393 { "haddps", { XM, EXx }, PREFIX_OPCODE },
3394 },
3395
3396 /* PREFIX_0F7D */
3397 {
3398 { Bad_Opcode },
3399 { Bad_Opcode },
3400 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3401 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3402 },
3403
3404 /* PREFIX_0F7E */
3405 {
3406 { "movK", { Edq, MX }, PREFIX_OPCODE },
3407 { "movq", { XM, EXq }, PREFIX_OPCODE },
3408 { "movK", { Edq, XM }, PREFIX_OPCODE },
3409 },
3410
3411 /* PREFIX_0F7F */
3412 {
3413 { "movq", { EMS, MX }, PREFIX_OPCODE },
3414 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3415 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3416 },
3417
3418 /* PREFIX_0FAE_REG_0_MOD_3 */
3419 {
3420 { Bad_Opcode },
3421 { "rdfsbase", { Ev }, 0 },
3422 },
3423
3424 /* PREFIX_0FAE_REG_1_MOD_3 */
3425 {
3426 { Bad_Opcode },
3427 { "rdgsbase", { Ev }, 0 },
3428 },
3429
3430 /* PREFIX_0FAE_REG_2_MOD_3 */
3431 {
3432 { Bad_Opcode },
3433 { "wrfsbase", { Ev }, 0 },
3434 },
3435
3436 /* PREFIX_0FAE_REG_3_MOD_3 */
3437 {
3438 { Bad_Opcode },
3439 { "wrgsbase", { Ev }, 0 },
3440 },
3441
3442 /* PREFIX_0FAE_REG_4_MOD_0 */
3443 {
3444 { "xsave", { FXSAVE }, 0 },
3445 { "ptwrite{%LQ|}", { Edq }, 0 },
3446 },
3447
3448 /* PREFIX_0FAE_REG_4_MOD_3 */
3449 {
3450 { Bad_Opcode },
3451 { "ptwrite{%LQ|}", { Edq }, 0 },
3452 },
3453
3454 /* PREFIX_0FAE_REG_5_MOD_0 */
3455 {
3456 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
3457 },
3458
3459 /* PREFIX_0FAE_REG_5_MOD_3 */
3460 {
3461 { "lfence", { Skip_MODRM }, 0 },
3462 { "incsspK", { Rdq }, PREFIX_OPCODE },
3463 },
3464
3465 /* PREFIX_0FAE_REG_6_MOD_0 */
3466 {
3467 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
3468 { "clrssbsy", { Mq }, PREFIX_OPCODE },
3469 { "clwb", { Mb }, PREFIX_OPCODE },
3470 },
3471
3472 /* PREFIX_0FAE_REG_6_MOD_3 */
3473 {
3474 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3475 { "umonitor", { Eva }, PREFIX_OPCODE },
3476 { "tpause", { Edq }, PREFIX_OPCODE },
3477 { "umwait", { Edq }, PREFIX_OPCODE },
3478 },
3479
3480 /* PREFIX_0FAE_REG_7_MOD_0 */
3481 {
3482 { "clflush", { Mb }, 0 },
3483 { Bad_Opcode },
3484 { "clflushopt", { Mb }, 0 },
3485 },
3486
3487 /* PREFIX_0FB8 */
3488 {
3489 { Bad_Opcode },
3490 { "popcntS", { Gv, Ev }, 0 },
3491 },
3492
3493 /* PREFIX_0FBC */
3494 {
3495 { "bsfS", { Gv, Ev }, 0 },
3496 { "tzcntS", { Gv, Ev }, 0 },
3497 { "bsfS", { Gv, Ev }, 0 },
3498 },
3499
3500 /* PREFIX_0FBD */
3501 {
3502 { "bsrS", { Gv, Ev }, 0 },
3503 { "lzcntS", { Gv, Ev }, 0 },
3504 { "bsrS", { Gv, Ev }, 0 },
3505 },
3506
3507 /* PREFIX_0FC2 */
3508 {
3509 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
3510 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
3511 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
3512 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
3513 },
3514
3515 /* PREFIX_0FC3_MOD_0 */
3516 {
3517 { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
3518 },
3519
3520 /* PREFIX_0FC7_REG_6_MOD_0 */
3521 {
3522 { "vmptrld",{ Mq }, 0 },
3523 { "vmxon", { Mq }, 0 },
3524 { "vmclear",{ Mq }, 0 },
3525 },
3526
3527 /* PREFIX_0FC7_REG_6_MOD_3 */
3528 {
3529 { "rdrand", { Ev }, 0 },
3530 { Bad_Opcode },
3531 { "rdrand", { Ev }, 0 }
3532 },
3533
3534 /* PREFIX_0FC7_REG_7_MOD_3 */
3535 {
3536 { "rdseed", { Ev }, 0 },
3537 { "rdpid", { Em }, 0 },
3538 { "rdseed", { Ev }, 0 },
3539 },
3540
3541 /* PREFIX_0FD0 */
3542 {
3543 { Bad_Opcode },
3544 { Bad_Opcode },
3545 { "addsubpd", { XM, EXx }, 0 },
3546 { "addsubps", { XM, EXx }, 0 },
3547 },
3548
3549 /* PREFIX_0FD6 */
3550 {
3551 { Bad_Opcode },
3552 { "movq2dq",{ XM, MS }, 0 },
3553 { "movq", { EXqS, XM }, 0 },
3554 { "movdq2q",{ MX, XS }, 0 },
3555 },
3556
3557 /* PREFIX_0FE6 */
3558 {
3559 { Bad_Opcode },
3560 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3561 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3562 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3563 },
3564
3565 /* PREFIX_0FE7 */
3566 {
3567 { "movntq", { Mq, MX }, PREFIX_OPCODE },
3568 { Bad_Opcode },
3569 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3570 },
3571
3572 /* PREFIX_0FF0 */
3573 {
3574 { Bad_Opcode },
3575 { Bad_Opcode },
3576 { Bad_Opcode },
3577 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3578 },
3579
3580 /* PREFIX_0FF7 */
3581 {
3582 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3583 { Bad_Opcode },
3584 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3585 },
3586
3587 /* PREFIX_0F38C8 */
3588 {
3589 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
3590 },
3591
3592 /* PREFIX_0F38C9 */
3593 {
3594 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
3595 },
3596
3597 /* PREFIX_0F38CA */
3598 {
3599 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
3600 },
3601
3602 /* PREFIX_0F38CB */
3603 {
3604 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
3605 },
3606
3607 /* PREFIX_0F38CC */
3608 {
3609 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
3610 },
3611
3612 /* PREFIX_0F38CD */
3613 {
3614 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
3615 },
3616
3617 /* PREFIX_0F38F0 */
3618 {
3619 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3620 { Bad_Opcode },
3621 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3622 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3623 },
3624
3625 /* PREFIX_0F38F1 */
3626 {
3627 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3628 { Bad_Opcode },
3629 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3630 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3631 },
3632
3633 /* PREFIX_0F38F6 */
3634 {
3635 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3636 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
3637 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
3638 { Bad_Opcode },
3639 },
3640
3641 /* PREFIX_0F38F8 */
3642 {
3643 { Bad_Opcode },
3644 { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3645 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3646 { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3647 },
3648
3649 /* PREFIX_0F38F9 */
3650 {
3651 { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
3652 },
3653
3654 /* PREFIX_0F3ACC */
3655 {
3656 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
3657 },
3658
3659 /* PREFIX_VEX_0F10 */
3660 {
3661 { "vmovups", { XM, EXx }, 0 },
3662 { "vmovss", { XMScalar, VexScalarR, EXxmm_md }, 0 },
3663 { "vmovupd", { XM, EXx }, 0 },
3664 { "vmovsd", { XMScalar, VexScalarR, EXxmm_mq }, 0 },
3665 },
3666
3667 /* PREFIX_VEX_0F11 */
3668 {
3669 { "vmovups", { EXxS, XM }, 0 },
3670 { "vmovss", { EXdS, VexScalarR, XMScalar }, 0 },
3671 { "vmovupd", { EXxS, XM }, 0 },
3672 { "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 },
3673 },
3674
3675 /* PREFIX_VEX_0F12 */
3676 {
3677 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3678 { "vmovsldup", { XM, EXx }, 0 },
3679 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3680 { "vmovddup", { XM, EXymmq }, 0 },
3681 },
3682
3683 /* PREFIX_VEX_0F16 */
3684 {
3685 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3686 { "vmovshdup", { XM, EXx }, 0 },
3687 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3688 },
3689
3690 /* PREFIX_VEX_0F2A */
3691 {
3692 { Bad_Opcode },
3693 { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
3694 { Bad_Opcode },
3695 { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
3696 },
3697
3698 /* PREFIX_VEX_0F2C */
3699 {
3700 { Bad_Opcode },
3701 { "vcvttss2si", { Gdq, EXxmm_md, EXxEVexS }, 0 },
3702 { Bad_Opcode },
3703 { "vcvttsd2si", { Gdq, EXxmm_mq, EXxEVexS }, 0 },
3704 },
3705
3706 /* PREFIX_VEX_0F2D */
3707 {
3708 { Bad_Opcode },
3709 { "vcvtss2si", { Gdq, EXxmm_md, EXxEVexR }, 0 },
3710 { Bad_Opcode },
3711 { "vcvtsd2si", { Gdq, EXxmm_mq, EXxEVexR }, 0 },
3712 },
3713
3714 /* PREFIX_VEX_0F2E */
3715 {
3716 { "vucomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3717 { Bad_Opcode },
3718 { "vucomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3719 },
3720
3721 /* PREFIX_VEX_0F2F */
3722 {
3723 { "vcomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3724 { Bad_Opcode },
3725 { "vcomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3726 },
3727
3728 /* PREFIX_VEX_0F41 */
3729 {
3730 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
3731 { Bad_Opcode },
3732 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
3733 },
3734
3735 /* PREFIX_VEX_0F42 */
3736 {
3737 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
3738 { Bad_Opcode },
3739 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
3740 },
3741
3742 /* PREFIX_VEX_0F44 */
3743 {
3744 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
3745 { Bad_Opcode },
3746 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
3747 },
3748
3749 /* PREFIX_VEX_0F45 */
3750 {
3751 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
3752 { Bad_Opcode },
3753 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
3754 },
3755
3756 /* PREFIX_VEX_0F46 */
3757 {
3758 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
3759 { Bad_Opcode },
3760 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
3761 },
3762
3763 /* PREFIX_VEX_0F47 */
3764 {
3765 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
3766 { Bad_Opcode },
3767 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
3768 },
3769
3770 /* PREFIX_VEX_0F4A */
3771 {
3772 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
3773 { Bad_Opcode },
3774 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
3775 },
3776
3777 /* PREFIX_VEX_0F4B */
3778 {
3779 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
3780 { Bad_Opcode },
3781 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
3782 },
3783
3784 /* PREFIX_VEX_0F51 */
3785 {
3786 { "vsqrtps", { XM, EXx }, 0 },
3787 { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3788 { "vsqrtpd", { XM, EXx }, 0 },
3789 { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3790 },
3791
3792 /* PREFIX_VEX_0F52 */
3793 {
3794 { "vrsqrtps", { XM, EXx }, 0 },
3795 { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3796 },
3797
3798 /* PREFIX_VEX_0F53 */
3799 {
3800 { "vrcpps", { XM, EXx }, 0 },
3801 { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3802 },
3803
3804 /* PREFIX_VEX_0F58 */
3805 {
3806 { "vaddps", { XM, Vex, EXx }, 0 },
3807 { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3808 { "vaddpd", { XM, Vex, EXx }, 0 },
3809 { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3810 },
3811
3812 /* PREFIX_VEX_0F59 */
3813 {
3814 { "vmulps", { XM, Vex, EXx }, 0 },
3815 { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3816 { "vmulpd", { XM, Vex, EXx }, 0 },
3817 { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3818 },
3819
3820 /* PREFIX_VEX_0F5A */
3821 {
3822 { "vcvtps2pd", { XM, EXxmmq }, 0 },
3823 { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 },
3824 { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
3825 { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3826 },
3827
3828 /* PREFIX_VEX_0F5B */
3829 {
3830 { "vcvtdq2ps", { XM, EXx }, 0 },
3831 { "vcvttps2dq", { XM, EXx }, 0 },
3832 { "vcvtps2dq", { XM, EXx }, 0 },
3833 },
3834
3835 /* PREFIX_VEX_0F5C */
3836 {
3837 { "vsubps", { XM, Vex, EXx }, 0 },
3838 { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3839 { "vsubpd", { XM, Vex, EXx }, 0 },
3840 { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3841 },
3842
3843 /* PREFIX_VEX_0F5D */
3844 {
3845 { "vminps", { XM, Vex, EXx }, 0 },
3846 { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3847 { "vminpd", { XM, Vex, EXx }, 0 },
3848 { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3849 },
3850
3851 /* PREFIX_VEX_0F5E */
3852 {
3853 { "vdivps", { XM, Vex, EXx }, 0 },
3854 { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3855 { "vdivpd", { XM, Vex, EXx }, 0 },
3856 { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3857 },
3858
3859 /* PREFIX_VEX_0F5F */
3860 {
3861 { "vmaxps", { XM, Vex, EXx }, 0 },
3862 { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3863 { "vmaxpd", { XM, Vex, EXx }, 0 },
3864 { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3865 },
3866
3867 /* PREFIX_VEX_0F6F */
3868 {
3869 { Bad_Opcode },
3870 { "vmovdqu", { XM, EXx }, 0 },
3871 { "vmovdqa", { XM, EXx }, 0 },
3872 },
3873
3874 /* PREFIX_VEX_0F70 */
3875 {
3876 { Bad_Opcode },
3877 { "vpshufhw", { XM, EXx, Ib }, 0 },
3878 { "vpshufd", { XM, EXx, Ib }, 0 },
3879 { "vpshuflw", { XM, EXx, Ib }, 0 },
3880 },
3881
3882 /* PREFIX_VEX_0F77 */
3883 {
3884 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
3885 },
3886
3887 /* PREFIX_VEX_0F7C */
3888 {
3889 { Bad_Opcode },
3890 { Bad_Opcode },
3891 { "vhaddpd", { XM, Vex, EXx }, 0 },
3892 { "vhaddps", { XM, Vex, EXx }, 0 },
3893 },
3894
3895 /* PREFIX_VEX_0F7D */
3896 {
3897 { Bad_Opcode },
3898 { Bad_Opcode },
3899 { "vhsubpd", { XM, Vex, EXx }, 0 },
3900 { "vhsubps", { XM, Vex, EXx }, 0 },
3901 },
3902
3903 /* PREFIX_VEX_0F7E */
3904 {
3905 { Bad_Opcode },
3906 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3907 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3908 },
3909
3910 /* PREFIX_VEX_0F7F */
3911 {
3912 { Bad_Opcode },
3913 { "vmovdqu", { EXxS, XM }, 0 },
3914 { "vmovdqa", { EXxS, XM }, 0 },
3915 },
3916
3917 /* PREFIX_VEX_0F90 */
3918 {
3919 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
3920 { Bad_Opcode },
3921 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
3922 },
3923
3924 /* PREFIX_VEX_0F91 */
3925 {
3926 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
3927 { Bad_Opcode },
3928 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
3929 },
3930
3931 /* PREFIX_VEX_0F92 */
3932 {
3933 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
3934 { Bad_Opcode },
3935 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
3936 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
3937 },
3938
3939 /* PREFIX_VEX_0F93 */
3940 {
3941 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
3942 { Bad_Opcode },
3943 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
3944 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
3945 },
3946
3947 /* PREFIX_VEX_0F98 */
3948 {
3949 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
3950 { Bad_Opcode },
3951 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
3952 },
3953
3954 /* PREFIX_VEX_0F99 */
3955 {
3956 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
3957 { Bad_Opcode },
3958 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
3959 },
3960
3961 /* PREFIX_VEX_0FC2 */
3962 {
3963 { "vcmpps", { XM, Vex, EXx, CMP }, 0 },
3964 { "vcmpss", { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
3965 { "vcmppd", { XM, Vex, EXx, CMP }, 0 },
3966 { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
3967 },
3968
3969 /* PREFIX_VEX_0FD0 */
3970 {
3971 { Bad_Opcode },
3972 { Bad_Opcode },
3973 { "vaddsubpd", { XM, Vex, EXx }, 0 },
3974 { "vaddsubps", { XM, Vex, EXx }, 0 },
3975 },
3976
3977 /* PREFIX_VEX_0FE6 */
3978 {
3979 { Bad_Opcode },
3980 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
3981 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
3982 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
3983 },
3984
3985 /* PREFIX_VEX_0FF0 */
3986 {
3987 { Bad_Opcode },
3988 { Bad_Opcode },
3989 { Bad_Opcode },
3990 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
3991 },
3992
3993 /* PREFIX_VEX_0F3849_X86_64 */
3994 {
3995 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
3996 { Bad_Opcode },
3997 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
3998 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
3999 },
4000
4001 /* PREFIX_VEX_0F384B_X86_64 */
4002 {
4003 { Bad_Opcode },
4004 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4005 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4006 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4007 },
4008
4009 /* PREFIX_VEX_0F385C_X86_64 */
4010 {
4011 { Bad_Opcode },
4012 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4013 { Bad_Opcode },
4014 },
4015
4016 /* PREFIX_VEX_0F385E_X86_64 */
4017 {
4018 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4019 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4020 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4021 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4022 },
4023
4024 /* PREFIX_VEX_0F38F2 */
4025 {
4026 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
4027 },
4028
4029 /* PREFIX_VEX_0F38F3_REG_1 */
4030 {
4031 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
4032 },
4033
4034 /* PREFIX_VEX_0F38F3_REG_2 */
4035 {
4036 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
4037 },
4038
4039 /* PREFIX_VEX_0F38F3_REG_3 */
4040 {
4041 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
4042 },
4043
4044 /* PREFIX_VEX_0F38F5 */
4045 {
4046 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
4047 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
4048 { Bad_Opcode },
4049 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
4050 },
4051
4052 /* PREFIX_VEX_0F38F6 */
4053 {
4054 { Bad_Opcode },
4055 { Bad_Opcode },
4056 { Bad_Opcode },
4057 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
4058 },
4059
4060 /* PREFIX_VEX_0F38F7 */
4061 {
4062 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
4063 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
4064 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
4065 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
4066 },
4067
4068 /* PREFIX_VEX_0F3AF0 */
4069 {
4070 { Bad_Opcode },
4071 { Bad_Opcode },
4072 { Bad_Opcode },
4073 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
4074 },
4075
4076 #include "i386-dis-evex-prefix.h"
4077 };
4078
4079 static const struct dis386 x86_64_table[][2] = {
4080 /* X86_64_06 */
4081 {
4082 { "pushP", { es }, 0 },
4083 },
4084
4085 /* X86_64_07 */
4086 {
4087 { "popP", { es }, 0 },
4088 },
4089
4090 /* X86_64_0E */
4091 {
4092 { "pushP", { cs }, 0 },
4093 },
4094
4095 /* X86_64_16 */
4096 {
4097 { "pushP", { ss }, 0 },
4098 },
4099
4100 /* X86_64_17 */
4101 {
4102 { "popP", { ss }, 0 },
4103 },
4104
4105 /* X86_64_1E */
4106 {
4107 { "pushP", { ds }, 0 },
4108 },
4109
4110 /* X86_64_1F */
4111 {
4112 { "popP", { ds }, 0 },
4113 },
4114
4115 /* X86_64_27 */
4116 {
4117 { "daa", { XX }, 0 },
4118 },
4119
4120 /* X86_64_2F */
4121 {
4122 { "das", { XX }, 0 },
4123 },
4124
4125 /* X86_64_37 */
4126 {
4127 { "aaa", { XX }, 0 },
4128 },
4129
4130 /* X86_64_3F */
4131 {
4132 { "aas", { XX }, 0 },
4133 },
4134
4135 /* X86_64_60 */
4136 {
4137 { "pushaP", { XX }, 0 },
4138 },
4139
4140 /* X86_64_61 */
4141 {
4142 { "popaP", { XX }, 0 },
4143 },
4144
4145 /* X86_64_62 */
4146 {
4147 { MOD_TABLE (MOD_62_32BIT) },
4148 { EVEX_TABLE (EVEX_0F) },
4149 },
4150
4151 /* X86_64_63 */
4152 {
4153 { "arpl", { Ew, Gw }, 0 },
4154 { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4155 },
4156
4157 /* X86_64_6D */
4158 {
4159 { "ins{R|}", { Yzr, indirDX }, 0 },
4160 { "ins{G|}", { Yzr, indirDX }, 0 },
4161 },
4162
4163 /* X86_64_6F */
4164 {
4165 { "outs{R|}", { indirDXr, Xz }, 0 },
4166 { "outs{G|}", { indirDXr, Xz }, 0 },
4167 },
4168
4169 /* X86_64_82 */
4170 {
4171 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4172 { REG_TABLE (REG_80) },
4173 },
4174
4175 /* X86_64_9A */
4176 {
4177 { "{l|}call{T|}", { Ap }, 0 },
4178 },
4179
4180 /* X86_64_C2 */
4181 {
4182 { "retP", { Iw, BND }, 0 },
4183 { "ret@", { Iw, BND }, 0 },
4184 },
4185
4186 /* X86_64_C3 */
4187 {
4188 { "retP", { BND }, 0 },
4189 { "ret@", { BND }, 0 },
4190 },
4191
4192 /* X86_64_C4 */
4193 {
4194 { MOD_TABLE (MOD_C4_32BIT) },
4195 { VEX_C4_TABLE (VEX_0F) },
4196 },
4197
4198 /* X86_64_C5 */
4199 {
4200 { MOD_TABLE (MOD_C5_32BIT) },
4201 { VEX_C5_TABLE (VEX_0F) },
4202 },
4203
4204 /* X86_64_CE */
4205 {
4206 { "into", { XX }, 0 },
4207 },
4208
4209 /* X86_64_D4 */
4210 {
4211 { "aam", { Ib }, 0 },
4212 },
4213
4214 /* X86_64_D5 */
4215 {
4216 { "aad", { Ib }, 0 },
4217 },
4218
4219 /* X86_64_E8 */
4220 {
4221 { "callP", { Jv, BND }, 0 },
4222 { "call@", { Jv, BND }, 0 }
4223 },
4224
4225 /* X86_64_E9 */
4226 {
4227 { "jmpP", { Jv, BND }, 0 },
4228 { "jmp@", { Jv, BND }, 0 }
4229 },
4230
4231 /* X86_64_EA */
4232 {
4233 { "{l|}jmp{T|}", { Ap }, 0 },
4234 },
4235
4236 /* X86_64_0F01_REG_0 */
4237 {
4238 { "sgdt{Q|Q}", { M }, 0 },
4239 { "sgdt", { M }, 0 },
4240 },
4241
4242 /* X86_64_0F01_REG_1 */
4243 {
4244 { "sidt{Q|Q}", { M }, 0 },
4245 { "sidt", { M }, 0 },
4246 },
4247
4248 /* X86_64_0F01_REG_2 */
4249 {
4250 { "lgdt{Q|Q}", { M }, 0 },
4251 { "lgdt", { M }, 0 },
4252 },
4253
4254 /* X86_64_0F01_REG_3 */
4255 {
4256 { "lidt{Q|Q}", { M }, 0 },
4257 { "lidt", { M }, 0 },
4258 },
4259
4260 /* X86_64_VEX_0F3849 */
4261 {
4262 { Bad_Opcode },
4263 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4264 },
4265
4266 /* X86_64_VEX_0F384B */
4267 {
4268 { Bad_Opcode },
4269 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4270 },
4271
4272 /* X86_64_VEX_0F385C */
4273 {
4274 { Bad_Opcode },
4275 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4276 },
4277
4278 /* X86_64_VEX_0F385E */
4279 {
4280 { Bad_Opcode },
4281 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4282 },
4283 };
4284
4285 static const struct dis386 three_byte_table[][256] = {
4286
4287 /* THREE_BYTE_0F38 */
4288 {
4289 /* 00 */
4290 { "pshufb", { MX, EM }, PREFIX_OPCODE },
4291 { "phaddw", { MX, EM }, PREFIX_OPCODE },
4292 { "phaddd", { MX, EM }, PREFIX_OPCODE },
4293 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
4294 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
4295 { "phsubw", { MX, EM }, PREFIX_OPCODE },
4296 { "phsubd", { MX, EM }, PREFIX_OPCODE },
4297 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
4298 /* 08 */
4299 { "psignb", { MX, EM }, PREFIX_OPCODE },
4300 { "psignw", { MX, EM }, PREFIX_OPCODE },
4301 { "psignd", { MX, EM }, PREFIX_OPCODE },
4302 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4303 { Bad_Opcode },
4304 { Bad_Opcode },
4305 { Bad_Opcode },
4306 { Bad_Opcode },
4307 /* 10 */
4308 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4309 { Bad_Opcode },
4310 { Bad_Opcode },
4311 { Bad_Opcode },
4312 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4313 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4314 { Bad_Opcode },
4315 { "ptest", { XM, EXx }, PREFIX_DATA },
4316 /* 18 */
4317 { Bad_Opcode },
4318 { Bad_Opcode },
4319 { Bad_Opcode },
4320 { Bad_Opcode },
4321 { "pabsb", { MX, EM }, PREFIX_OPCODE },
4322 { "pabsw", { MX, EM }, PREFIX_OPCODE },
4323 { "pabsd", { MX, EM }, PREFIX_OPCODE },
4324 { Bad_Opcode },
4325 /* 20 */
4326 { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4327 { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4328 { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4329 { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4330 { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4331 { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4332 { Bad_Opcode },
4333 { Bad_Opcode },
4334 /* 28 */
4335 { "pmuldq", { XM, EXx }, PREFIX_DATA },
4336 { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4337 { MOD_TABLE (MOD_0F382A) },
4338 { "packusdw", { XM, EXx }, PREFIX_DATA },
4339 { Bad_Opcode },
4340 { Bad_Opcode },
4341 { Bad_Opcode },
4342 { Bad_Opcode },
4343 /* 30 */
4344 { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4345 { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4346 { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4347 { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4348 { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4349 { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4350 { Bad_Opcode },
4351 { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4352 /* 38 */
4353 { "pminsb", { XM, EXx }, PREFIX_DATA },
4354 { "pminsd", { XM, EXx }, PREFIX_DATA },
4355 { "pminuw", { XM, EXx }, PREFIX_DATA },
4356 { "pminud", { XM, EXx }, PREFIX_DATA },
4357 { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4358 { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4359 { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4360 { "pmaxud", { XM, EXx }, PREFIX_DATA },
4361 /* 40 */
4362 { "pmulld", { XM, EXx }, PREFIX_DATA },
4363 { "phminposuw", { XM, EXx }, PREFIX_DATA },
4364 { Bad_Opcode },
4365 { Bad_Opcode },
4366 { Bad_Opcode },
4367 { Bad_Opcode },
4368 { Bad_Opcode },
4369 { Bad_Opcode },
4370 /* 48 */
4371 { Bad_Opcode },
4372 { Bad_Opcode },
4373 { Bad_Opcode },
4374 { Bad_Opcode },
4375 { Bad_Opcode },
4376 { Bad_Opcode },
4377 { Bad_Opcode },
4378 { Bad_Opcode },
4379 /* 50 */
4380 { Bad_Opcode },
4381 { Bad_Opcode },
4382 { Bad_Opcode },
4383 { Bad_Opcode },
4384 { Bad_Opcode },
4385 { Bad_Opcode },
4386 { Bad_Opcode },
4387 { Bad_Opcode },
4388 /* 58 */
4389 { Bad_Opcode },
4390 { Bad_Opcode },
4391 { Bad_Opcode },
4392 { Bad_Opcode },
4393 { Bad_Opcode },
4394 { Bad_Opcode },
4395 { Bad_Opcode },
4396 { Bad_Opcode },
4397 /* 60 */
4398 { Bad_Opcode },
4399 { Bad_Opcode },
4400 { Bad_Opcode },
4401 { Bad_Opcode },
4402 { Bad_Opcode },
4403 { Bad_Opcode },
4404 { Bad_Opcode },
4405 { Bad_Opcode },
4406 /* 68 */
4407 { Bad_Opcode },
4408 { Bad_Opcode },
4409 { Bad_Opcode },
4410 { Bad_Opcode },
4411 { Bad_Opcode },
4412 { Bad_Opcode },
4413 { Bad_Opcode },
4414 { Bad_Opcode },
4415 /* 70 */
4416 { Bad_Opcode },
4417 { Bad_Opcode },
4418 { Bad_Opcode },
4419 { Bad_Opcode },
4420 { Bad_Opcode },
4421 { Bad_Opcode },
4422 { Bad_Opcode },
4423 { Bad_Opcode },
4424 /* 78 */
4425 { Bad_Opcode },
4426 { Bad_Opcode },
4427 { Bad_Opcode },
4428 { Bad_Opcode },
4429 { Bad_Opcode },
4430 { Bad_Opcode },
4431 { Bad_Opcode },
4432 { Bad_Opcode },
4433 /* 80 */
4434 { "invept", { Gm, Mo }, PREFIX_DATA },
4435 { "invvpid", { Gm, Mo }, PREFIX_DATA },
4436 { "invpcid", { Gm, M }, PREFIX_DATA },
4437 { Bad_Opcode },
4438 { Bad_Opcode },
4439 { Bad_Opcode },
4440 { Bad_Opcode },
4441 { Bad_Opcode },
4442 /* 88 */
4443 { Bad_Opcode },
4444 { Bad_Opcode },
4445 { Bad_Opcode },
4446 { Bad_Opcode },
4447 { Bad_Opcode },
4448 { Bad_Opcode },
4449 { Bad_Opcode },
4450 { Bad_Opcode },
4451 /* 90 */
4452 { Bad_Opcode },
4453 { Bad_Opcode },
4454 { Bad_Opcode },
4455 { Bad_Opcode },
4456 { Bad_Opcode },
4457 { Bad_Opcode },
4458 { Bad_Opcode },
4459 { Bad_Opcode },
4460 /* 98 */
4461 { Bad_Opcode },
4462 { Bad_Opcode },
4463 { Bad_Opcode },
4464 { Bad_Opcode },
4465 { Bad_Opcode },
4466 { Bad_Opcode },
4467 { Bad_Opcode },
4468 { Bad_Opcode },
4469 /* a0 */
4470 { Bad_Opcode },
4471 { Bad_Opcode },
4472 { Bad_Opcode },
4473 { Bad_Opcode },
4474 { Bad_Opcode },
4475 { Bad_Opcode },
4476 { Bad_Opcode },
4477 { Bad_Opcode },
4478 /* a8 */
4479 { Bad_Opcode },
4480 { Bad_Opcode },
4481 { Bad_Opcode },
4482 { Bad_Opcode },
4483 { Bad_Opcode },
4484 { Bad_Opcode },
4485 { Bad_Opcode },
4486 { Bad_Opcode },
4487 /* b0 */
4488 { Bad_Opcode },
4489 { Bad_Opcode },
4490 { Bad_Opcode },
4491 { Bad_Opcode },
4492 { Bad_Opcode },
4493 { Bad_Opcode },
4494 { Bad_Opcode },
4495 { Bad_Opcode },
4496 /* b8 */
4497 { Bad_Opcode },
4498 { Bad_Opcode },
4499 { Bad_Opcode },
4500 { Bad_Opcode },
4501 { Bad_Opcode },
4502 { Bad_Opcode },
4503 { Bad_Opcode },
4504 { Bad_Opcode },
4505 /* c0 */
4506 { Bad_Opcode },
4507 { Bad_Opcode },
4508 { Bad_Opcode },
4509 { Bad_Opcode },
4510 { Bad_Opcode },
4511 { Bad_Opcode },
4512 { Bad_Opcode },
4513 { Bad_Opcode },
4514 /* c8 */
4515 { PREFIX_TABLE (PREFIX_0F38C8) },
4516 { PREFIX_TABLE (PREFIX_0F38C9) },
4517 { PREFIX_TABLE (PREFIX_0F38CA) },
4518 { PREFIX_TABLE (PREFIX_0F38CB) },
4519 { PREFIX_TABLE (PREFIX_0F38CC) },
4520 { PREFIX_TABLE (PREFIX_0F38CD) },
4521 { Bad_Opcode },
4522 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4523 /* d0 */
4524 { Bad_Opcode },
4525 { Bad_Opcode },
4526 { Bad_Opcode },
4527 { Bad_Opcode },
4528 { Bad_Opcode },
4529 { Bad_Opcode },
4530 { Bad_Opcode },
4531 { Bad_Opcode },
4532 /* d8 */
4533 { Bad_Opcode },
4534 { Bad_Opcode },
4535 { Bad_Opcode },
4536 { "aesimc", { XM, EXx }, PREFIX_DATA },
4537 { "aesenc", { XM, EXx }, PREFIX_DATA },
4538 { "aesenclast", { XM, EXx }, PREFIX_DATA },
4539 { "aesdec", { XM, EXx }, PREFIX_DATA },
4540 { "aesdeclast", { XM, EXx }, PREFIX_DATA },
4541 /* e0 */
4542 { Bad_Opcode },
4543 { Bad_Opcode },
4544 { Bad_Opcode },
4545 { Bad_Opcode },
4546 { Bad_Opcode },
4547 { Bad_Opcode },
4548 { Bad_Opcode },
4549 { Bad_Opcode },
4550 /* e8 */
4551 { Bad_Opcode },
4552 { Bad_Opcode },
4553 { Bad_Opcode },
4554 { Bad_Opcode },
4555 { Bad_Opcode },
4556 { Bad_Opcode },
4557 { Bad_Opcode },
4558 { Bad_Opcode },
4559 /* f0 */
4560 { PREFIX_TABLE (PREFIX_0F38F0) },
4561 { PREFIX_TABLE (PREFIX_0F38F1) },
4562 { Bad_Opcode },
4563 { Bad_Opcode },
4564 { Bad_Opcode },
4565 { MOD_TABLE (MOD_0F38F5) },
4566 { PREFIX_TABLE (PREFIX_0F38F6) },
4567 { Bad_Opcode },
4568 /* f8 */
4569 { PREFIX_TABLE (PREFIX_0F38F8) },
4570 { PREFIX_TABLE (PREFIX_0F38F9) },
4571 { Bad_Opcode },
4572 { Bad_Opcode },
4573 { Bad_Opcode },
4574 { Bad_Opcode },
4575 { Bad_Opcode },
4576 { Bad_Opcode },
4577 },
4578 /* THREE_BYTE_0F3A */
4579 {
4580 /* 00 */
4581 { Bad_Opcode },
4582 { Bad_Opcode },
4583 { Bad_Opcode },
4584 { Bad_Opcode },
4585 { Bad_Opcode },
4586 { Bad_Opcode },
4587 { Bad_Opcode },
4588 { Bad_Opcode },
4589 /* 08 */
4590 { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4591 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4592 { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4593 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4594 { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4595 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4596 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4597 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
4598 /* 10 */
4599 { Bad_Opcode },
4600 { Bad_Opcode },
4601 { Bad_Opcode },
4602 { Bad_Opcode },
4603 { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA },
4604 { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA },
4605 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4606 { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
4607 /* 18 */
4608 { Bad_Opcode },
4609 { Bad_Opcode },
4610 { Bad_Opcode },
4611 { Bad_Opcode },
4612 { Bad_Opcode },
4613 { Bad_Opcode },
4614 { Bad_Opcode },
4615 { Bad_Opcode },
4616 /* 20 */
4617 { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA },
4618 { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4619 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4620 { Bad_Opcode },
4621 { Bad_Opcode },
4622 { Bad_Opcode },
4623 { Bad_Opcode },
4624 { Bad_Opcode },
4625 /* 28 */
4626 { Bad_Opcode },
4627 { Bad_Opcode },
4628 { Bad_Opcode },
4629 { Bad_Opcode },
4630 { Bad_Opcode },
4631 { Bad_Opcode },
4632 { Bad_Opcode },
4633 { Bad_Opcode },
4634 /* 30 */
4635 { Bad_Opcode },
4636 { Bad_Opcode },
4637 { Bad_Opcode },
4638 { Bad_Opcode },
4639 { Bad_Opcode },
4640 { Bad_Opcode },
4641 { Bad_Opcode },
4642 { Bad_Opcode },
4643 /* 38 */
4644 { Bad_Opcode },
4645 { Bad_Opcode },
4646 { Bad_Opcode },
4647 { Bad_Opcode },
4648 { Bad_Opcode },
4649 { Bad_Opcode },
4650 { Bad_Opcode },
4651 { Bad_Opcode },
4652 /* 40 */
4653 { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
4654 { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
4655 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4656 { Bad_Opcode },
4657 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4658 { Bad_Opcode },
4659 { Bad_Opcode },
4660 { Bad_Opcode },
4661 /* 48 */
4662 { Bad_Opcode },
4663 { Bad_Opcode },
4664 { Bad_Opcode },
4665 { Bad_Opcode },
4666 { Bad_Opcode },
4667 { Bad_Opcode },
4668 { Bad_Opcode },
4669 { Bad_Opcode },
4670 /* 50 */
4671 { Bad_Opcode },
4672 { Bad_Opcode },
4673 { Bad_Opcode },
4674 { Bad_Opcode },
4675 { Bad_Opcode },
4676 { Bad_Opcode },
4677 { Bad_Opcode },
4678 { Bad_Opcode },
4679 /* 58 */
4680 { Bad_Opcode },
4681 { Bad_Opcode },
4682 { Bad_Opcode },
4683 { Bad_Opcode },
4684 { Bad_Opcode },
4685 { Bad_Opcode },
4686 { Bad_Opcode },
4687 { Bad_Opcode },
4688 /* 60 */
4689 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4690 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4691 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4692 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4693 { Bad_Opcode },
4694 { Bad_Opcode },
4695 { Bad_Opcode },
4696 { Bad_Opcode },
4697 /* 68 */
4698 { Bad_Opcode },
4699 { Bad_Opcode },
4700 { Bad_Opcode },
4701 { Bad_Opcode },
4702 { Bad_Opcode },
4703 { Bad_Opcode },
4704 { Bad_Opcode },
4705 { Bad_Opcode },
4706 /* 70 */
4707 { Bad_Opcode },
4708 { Bad_Opcode },
4709 { Bad_Opcode },
4710 { Bad_Opcode },
4711 { Bad_Opcode },
4712 { Bad_Opcode },
4713 { Bad_Opcode },
4714 { Bad_Opcode },
4715 /* 78 */
4716 { Bad_Opcode },
4717 { Bad_Opcode },
4718 { Bad_Opcode },
4719 { Bad_Opcode },
4720 { Bad_Opcode },
4721 { Bad_Opcode },
4722 { Bad_Opcode },
4723 { Bad_Opcode },
4724 /* 80 */
4725 { Bad_Opcode },
4726 { Bad_Opcode },
4727 { Bad_Opcode },
4728 { Bad_Opcode },
4729 { Bad_Opcode },
4730 { Bad_Opcode },
4731 { Bad_Opcode },
4732 { Bad_Opcode },
4733 /* 88 */
4734 { Bad_Opcode },
4735 { Bad_Opcode },
4736 { Bad_Opcode },
4737 { Bad_Opcode },
4738 { Bad_Opcode },
4739 { Bad_Opcode },
4740 { Bad_Opcode },
4741 { Bad_Opcode },
4742 /* 90 */
4743 { Bad_Opcode },
4744 { Bad_Opcode },
4745 { Bad_Opcode },
4746 { Bad_Opcode },
4747 { Bad_Opcode },
4748 { Bad_Opcode },
4749 { Bad_Opcode },
4750 { Bad_Opcode },
4751 /* 98 */
4752 { Bad_Opcode },
4753 { Bad_Opcode },
4754 { Bad_Opcode },
4755 { Bad_Opcode },
4756 { Bad_Opcode },
4757 { Bad_Opcode },
4758 { Bad_Opcode },
4759 { Bad_Opcode },
4760 /* a0 */
4761 { Bad_Opcode },
4762 { Bad_Opcode },
4763 { Bad_Opcode },
4764 { Bad_Opcode },
4765 { Bad_Opcode },
4766 { Bad_Opcode },
4767 { Bad_Opcode },
4768 { Bad_Opcode },
4769 /* a8 */
4770 { Bad_Opcode },
4771 { Bad_Opcode },
4772 { Bad_Opcode },
4773 { Bad_Opcode },
4774 { Bad_Opcode },
4775 { Bad_Opcode },
4776 { Bad_Opcode },
4777 { Bad_Opcode },
4778 /* b0 */
4779 { Bad_Opcode },
4780 { Bad_Opcode },
4781 { Bad_Opcode },
4782 { Bad_Opcode },
4783 { Bad_Opcode },
4784 { Bad_Opcode },
4785 { Bad_Opcode },
4786 { Bad_Opcode },
4787 /* b8 */
4788 { Bad_Opcode },
4789 { Bad_Opcode },
4790 { Bad_Opcode },
4791 { Bad_Opcode },
4792 { Bad_Opcode },
4793 { Bad_Opcode },
4794 { Bad_Opcode },
4795 { Bad_Opcode },
4796 /* c0 */
4797 { Bad_Opcode },
4798 { Bad_Opcode },
4799 { Bad_Opcode },
4800 { Bad_Opcode },
4801 { Bad_Opcode },
4802 { Bad_Opcode },
4803 { Bad_Opcode },
4804 { Bad_Opcode },
4805 /* c8 */
4806 { Bad_Opcode },
4807 { Bad_Opcode },
4808 { Bad_Opcode },
4809 { Bad_Opcode },
4810 { PREFIX_TABLE (PREFIX_0F3ACC) },
4811 { Bad_Opcode },
4812 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4813 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4814 /* d0 */
4815 { Bad_Opcode },
4816 { Bad_Opcode },
4817 { Bad_Opcode },
4818 { Bad_Opcode },
4819 { Bad_Opcode },
4820 { Bad_Opcode },
4821 { Bad_Opcode },
4822 { Bad_Opcode },
4823 /* d8 */
4824 { Bad_Opcode },
4825 { Bad_Opcode },
4826 { Bad_Opcode },
4827 { Bad_Opcode },
4828 { Bad_Opcode },
4829 { Bad_Opcode },
4830 { Bad_Opcode },
4831 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4832 /* e0 */
4833 { Bad_Opcode },
4834 { Bad_Opcode },
4835 { Bad_Opcode },
4836 { Bad_Opcode },
4837 { Bad_Opcode },
4838 { Bad_Opcode },
4839 { Bad_Opcode },
4840 { Bad_Opcode },
4841 /* e8 */
4842 { Bad_Opcode },
4843 { Bad_Opcode },
4844 { Bad_Opcode },
4845 { Bad_Opcode },
4846 { Bad_Opcode },
4847 { Bad_Opcode },
4848 { Bad_Opcode },
4849 { Bad_Opcode },
4850 /* f0 */
4851 { Bad_Opcode },
4852 { Bad_Opcode },
4853 { Bad_Opcode },
4854 { Bad_Opcode },
4855 { Bad_Opcode },
4856 { Bad_Opcode },
4857 { Bad_Opcode },
4858 { Bad_Opcode },
4859 /* f8 */
4860 { Bad_Opcode },
4861 { Bad_Opcode },
4862 { Bad_Opcode },
4863 { Bad_Opcode },
4864 { Bad_Opcode },
4865 { Bad_Opcode },
4866 { Bad_Opcode },
4867 { Bad_Opcode },
4868 },
4869 };
4870
4871 static const struct dis386 xop_table[][256] = {
4872 /* XOP_08 */
4873 {
4874 /* 00 */
4875 { Bad_Opcode },
4876 { Bad_Opcode },
4877 { Bad_Opcode },
4878 { Bad_Opcode },
4879 { Bad_Opcode },
4880 { Bad_Opcode },
4881 { Bad_Opcode },
4882 { Bad_Opcode },
4883 /* 08 */
4884 { Bad_Opcode },
4885 { Bad_Opcode },
4886 { Bad_Opcode },
4887 { Bad_Opcode },
4888 { Bad_Opcode },
4889 { Bad_Opcode },
4890 { Bad_Opcode },
4891 { Bad_Opcode },
4892 /* 10 */
4893 { Bad_Opcode },
4894 { Bad_Opcode },
4895 { Bad_Opcode },
4896 { Bad_Opcode },
4897 { Bad_Opcode },
4898 { Bad_Opcode },
4899 { Bad_Opcode },
4900 { Bad_Opcode },
4901 /* 18 */
4902 { Bad_Opcode },
4903 { Bad_Opcode },
4904 { Bad_Opcode },
4905 { Bad_Opcode },
4906 { Bad_Opcode },
4907 { Bad_Opcode },
4908 { Bad_Opcode },
4909 { Bad_Opcode },
4910 /* 20 */
4911 { Bad_Opcode },
4912 { Bad_Opcode },
4913 { Bad_Opcode },
4914 { Bad_Opcode },
4915 { Bad_Opcode },
4916 { Bad_Opcode },
4917 { Bad_Opcode },
4918 { Bad_Opcode },
4919 /* 28 */
4920 { Bad_Opcode },
4921 { Bad_Opcode },
4922 { Bad_Opcode },
4923 { Bad_Opcode },
4924 { Bad_Opcode },
4925 { Bad_Opcode },
4926 { Bad_Opcode },
4927 { Bad_Opcode },
4928 /* 30 */
4929 { Bad_Opcode },
4930 { Bad_Opcode },
4931 { Bad_Opcode },
4932 { Bad_Opcode },
4933 { Bad_Opcode },
4934 { Bad_Opcode },
4935 { Bad_Opcode },
4936 { Bad_Opcode },
4937 /* 38 */
4938 { Bad_Opcode },
4939 { Bad_Opcode },
4940 { Bad_Opcode },
4941 { Bad_Opcode },
4942 { Bad_Opcode },
4943 { Bad_Opcode },
4944 { Bad_Opcode },
4945 { Bad_Opcode },
4946 /* 40 */
4947 { Bad_Opcode },
4948 { Bad_Opcode },
4949 { Bad_Opcode },
4950 { Bad_Opcode },
4951 { Bad_Opcode },
4952 { Bad_Opcode },
4953 { Bad_Opcode },
4954 { Bad_Opcode },
4955 /* 48 */
4956 { Bad_Opcode },
4957 { Bad_Opcode },
4958 { Bad_Opcode },
4959 { Bad_Opcode },
4960 { Bad_Opcode },
4961 { Bad_Opcode },
4962 { Bad_Opcode },
4963 { Bad_Opcode },
4964 /* 50 */
4965 { Bad_Opcode },
4966 { Bad_Opcode },
4967 { Bad_Opcode },
4968 { Bad_Opcode },
4969 { Bad_Opcode },
4970 { Bad_Opcode },
4971 { Bad_Opcode },
4972 { Bad_Opcode },
4973 /* 58 */
4974 { Bad_Opcode },
4975 { Bad_Opcode },
4976 { Bad_Opcode },
4977 { Bad_Opcode },
4978 { Bad_Opcode },
4979 { Bad_Opcode },
4980 { Bad_Opcode },
4981 { Bad_Opcode },
4982 /* 60 */
4983 { Bad_Opcode },
4984 { Bad_Opcode },
4985 { Bad_Opcode },
4986 { Bad_Opcode },
4987 { Bad_Opcode },
4988 { Bad_Opcode },
4989 { Bad_Opcode },
4990 { Bad_Opcode },
4991 /* 68 */
4992 { Bad_Opcode },
4993 { Bad_Opcode },
4994 { Bad_Opcode },
4995 { Bad_Opcode },
4996 { Bad_Opcode },
4997 { Bad_Opcode },
4998 { Bad_Opcode },
4999 { Bad_Opcode },
5000 /* 70 */
5001 { Bad_Opcode },
5002 { Bad_Opcode },
5003 { Bad_Opcode },
5004 { Bad_Opcode },
5005 { Bad_Opcode },
5006 { Bad_Opcode },
5007 { Bad_Opcode },
5008 { Bad_Opcode },
5009 /* 78 */
5010 { Bad_Opcode },
5011 { Bad_Opcode },
5012 { Bad_Opcode },
5013 { Bad_Opcode },
5014 { Bad_Opcode },
5015 { Bad_Opcode },
5016 { Bad_Opcode },
5017 { Bad_Opcode },
5018 /* 80 */
5019 { Bad_Opcode },
5020 { Bad_Opcode },
5021 { Bad_Opcode },
5022 { Bad_Opcode },
5023 { Bad_Opcode },
5024 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5025 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5026 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5027 /* 88 */
5028 { Bad_Opcode },
5029 { Bad_Opcode },
5030 { Bad_Opcode },
5031 { Bad_Opcode },
5032 { Bad_Opcode },
5033 { Bad_Opcode },
5034 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5035 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5036 /* 90 */
5037 { Bad_Opcode },
5038 { Bad_Opcode },
5039 { Bad_Opcode },
5040 { Bad_Opcode },
5041 { Bad_Opcode },
5042 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5043 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5044 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5045 /* 98 */
5046 { Bad_Opcode },
5047 { Bad_Opcode },
5048 { Bad_Opcode },
5049 { Bad_Opcode },
5050 { Bad_Opcode },
5051 { Bad_Opcode },
5052 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5053 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5054 /* a0 */
5055 { Bad_Opcode },
5056 { Bad_Opcode },
5057 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
5058 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5059 { Bad_Opcode },
5060 { Bad_Opcode },
5061 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5062 { Bad_Opcode },
5063 /* a8 */
5064 { Bad_Opcode },
5065 { Bad_Opcode },
5066 { Bad_Opcode },
5067 { Bad_Opcode },
5068 { Bad_Opcode },
5069 { Bad_Opcode },
5070 { Bad_Opcode },
5071 { Bad_Opcode },
5072 /* b0 */
5073 { Bad_Opcode },
5074 { Bad_Opcode },
5075 { Bad_Opcode },
5076 { Bad_Opcode },
5077 { Bad_Opcode },
5078 { Bad_Opcode },
5079 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5080 { Bad_Opcode },
5081 /* b8 */
5082 { Bad_Opcode },
5083 { Bad_Opcode },
5084 { Bad_Opcode },
5085 { Bad_Opcode },
5086 { Bad_Opcode },
5087 { Bad_Opcode },
5088 { Bad_Opcode },
5089 { Bad_Opcode },
5090 /* c0 */
5091 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5092 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5093 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5094 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5095 { Bad_Opcode },
5096 { Bad_Opcode },
5097 { Bad_Opcode },
5098 { Bad_Opcode },
5099 /* c8 */
5100 { Bad_Opcode },
5101 { Bad_Opcode },
5102 { Bad_Opcode },
5103 { Bad_Opcode },
5104 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5105 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5106 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5107 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5108 /* d0 */
5109 { Bad_Opcode },
5110 { Bad_Opcode },
5111 { Bad_Opcode },
5112 { Bad_Opcode },
5113 { Bad_Opcode },
5114 { Bad_Opcode },
5115 { Bad_Opcode },
5116 { Bad_Opcode },
5117 /* d8 */
5118 { Bad_Opcode },
5119 { Bad_Opcode },
5120 { Bad_Opcode },
5121 { Bad_Opcode },
5122 { Bad_Opcode },
5123 { Bad_Opcode },
5124 { Bad_Opcode },
5125 { Bad_Opcode },
5126 /* e0 */
5127 { Bad_Opcode },
5128 { Bad_Opcode },
5129 { Bad_Opcode },
5130 { Bad_Opcode },
5131 { Bad_Opcode },
5132 { Bad_Opcode },
5133 { Bad_Opcode },
5134 { Bad_Opcode },
5135 /* e8 */
5136 { Bad_Opcode },
5137 { Bad_Opcode },
5138 { Bad_Opcode },
5139 { Bad_Opcode },
5140 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5141 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5142 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5143 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5144 /* f0 */
5145 { Bad_Opcode },
5146 { Bad_Opcode },
5147 { Bad_Opcode },
5148 { Bad_Opcode },
5149 { Bad_Opcode },
5150 { Bad_Opcode },
5151 { Bad_Opcode },
5152 { Bad_Opcode },
5153 /* f8 */
5154 { Bad_Opcode },
5155 { Bad_Opcode },
5156 { Bad_Opcode },
5157 { Bad_Opcode },
5158 { Bad_Opcode },
5159 { Bad_Opcode },
5160 { Bad_Opcode },
5161 { Bad_Opcode },
5162 },
5163 /* XOP_09 */
5164 {
5165 /* 00 */
5166 { Bad_Opcode },
5167 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5168 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5169 { Bad_Opcode },
5170 { Bad_Opcode },
5171 { Bad_Opcode },
5172 { Bad_Opcode },
5173 { Bad_Opcode },
5174 /* 08 */
5175 { Bad_Opcode },
5176 { Bad_Opcode },
5177 { Bad_Opcode },
5178 { Bad_Opcode },
5179 { Bad_Opcode },
5180 { Bad_Opcode },
5181 { Bad_Opcode },
5182 { Bad_Opcode },
5183 /* 10 */
5184 { Bad_Opcode },
5185 { Bad_Opcode },
5186 { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
5187 { Bad_Opcode },
5188 { Bad_Opcode },
5189 { Bad_Opcode },
5190 { Bad_Opcode },
5191 { Bad_Opcode },
5192 /* 18 */
5193 { Bad_Opcode },
5194 { Bad_Opcode },
5195 { Bad_Opcode },
5196 { Bad_Opcode },
5197 { Bad_Opcode },
5198 { Bad_Opcode },
5199 { Bad_Opcode },
5200 { Bad_Opcode },
5201 /* 20 */
5202 { Bad_Opcode },
5203 { Bad_Opcode },
5204 { Bad_Opcode },
5205 { Bad_Opcode },
5206 { Bad_Opcode },
5207 { Bad_Opcode },
5208 { Bad_Opcode },
5209 { Bad_Opcode },
5210 /* 28 */
5211 { Bad_Opcode },
5212 { Bad_Opcode },
5213 { Bad_Opcode },
5214 { Bad_Opcode },
5215 { Bad_Opcode },
5216 { Bad_Opcode },
5217 { Bad_Opcode },
5218 { Bad_Opcode },
5219 /* 30 */
5220 { Bad_Opcode },
5221 { Bad_Opcode },
5222 { Bad_Opcode },
5223 { Bad_Opcode },
5224 { Bad_Opcode },
5225 { Bad_Opcode },
5226 { Bad_Opcode },
5227 { Bad_Opcode },
5228 /* 38 */
5229 { Bad_Opcode },
5230 { Bad_Opcode },
5231 { Bad_Opcode },
5232 { Bad_Opcode },
5233 { Bad_Opcode },
5234 { Bad_Opcode },
5235 { Bad_Opcode },
5236 { Bad_Opcode },
5237 /* 40 */
5238 { Bad_Opcode },
5239 { Bad_Opcode },
5240 { Bad_Opcode },
5241 { Bad_Opcode },
5242 { Bad_Opcode },
5243 { Bad_Opcode },
5244 { Bad_Opcode },
5245 { Bad_Opcode },
5246 /* 48 */
5247 { Bad_Opcode },
5248 { Bad_Opcode },
5249 { Bad_Opcode },
5250 { Bad_Opcode },
5251 { Bad_Opcode },
5252 { Bad_Opcode },
5253 { Bad_Opcode },
5254 { Bad_Opcode },
5255 /* 50 */
5256 { Bad_Opcode },
5257 { Bad_Opcode },
5258 { Bad_Opcode },
5259 { Bad_Opcode },
5260 { Bad_Opcode },
5261 { Bad_Opcode },
5262 { Bad_Opcode },
5263 { Bad_Opcode },
5264 /* 58 */
5265 { Bad_Opcode },
5266 { Bad_Opcode },
5267 { Bad_Opcode },
5268 { Bad_Opcode },
5269 { Bad_Opcode },
5270 { Bad_Opcode },
5271 { Bad_Opcode },
5272 { Bad_Opcode },
5273 /* 60 */
5274 { Bad_Opcode },
5275 { Bad_Opcode },
5276 { Bad_Opcode },
5277 { Bad_Opcode },
5278 { Bad_Opcode },
5279 { Bad_Opcode },
5280 { Bad_Opcode },
5281 { Bad_Opcode },
5282 /* 68 */
5283 { Bad_Opcode },
5284 { Bad_Opcode },
5285 { Bad_Opcode },
5286 { Bad_Opcode },
5287 { Bad_Opcode },
5288 { Bad_Opcode },
5289 { Bad_Opcode },
5290 { Bad_Opcode },
5291 /* 70 */
5292 { Bad_Opcode },
5293 { Bad_Opcode },
5294 { Bad_Opcode },
5295 { Bad_Opcode },
5296 { Bad_Opcode },
5297 { Bad_Opcode },
5298 { Bad_Opcode },
5299 { Bad_Opcode },
5300 /* 78 */
5301 { Bad_Opcode },
5302 { Bad_Opcode },
5303 { Bad_Opcode },
5304 { Bad_Opcode },
5305 { Bad_Opcode },
5306 { Bad_Opcode },
5307 { Bad_Opcode },
5308 { Bad_Opcode },
5309 /* 80 */
5310 { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5311 { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5312 { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5313 { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5314 { Bad_Opcode },
5315 { Bad_Opcode },
5316 { Bad_Opcode },
5317 { Bad_Opcode },
5318 /* 88 */
5319 { Bad_Opcode },
5320 { Bad_Opcode },
5321 { Bad_Opcode },
5322 { Bad_Opcode },
5323 { Bad_Opcode },
5324 { Bad_Opcode },
5325 { Bad_Opcode },
5326 { Bad_Opcode },
5327 /* 90 */
5328 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5329 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5330 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5331 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5332 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5333 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5334 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5335 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5336 /* 98 */
5337 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5338 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5339 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5340 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5341 { Bad_Opcode },
5342 { Bad_Opcode },
5343 { Bad_Opcode },
5344 { Bad_Opcode },
5345 /* a0 */
5346 { Bad_Opcode },
5347 { Bad_Opcode },
5348 { Bad_Opcode },
5349 { Bad_Opcode },
5350 { Bad_Opcode },
5351 { Bad_Opcode },
5352 { Bad_Opcode },
5353 { Bad_Opcode },
5354 /* a8 */
5355 { Bad_Opcode },
5356 { Bad_Opcode },
5357 { Bad_Opcode },
5358 { Bad_Opcode },
5359 { Bad_Opcode },
5360 { Bad_Opcode },
5361 { Bad_Opcode },
5362 { Bad_Opcode },
5363 /* b0 */
5364 { Bad_Opcode },
5365 { Bad_Opcode },
5366 { Bad_Opcode },
5367 { Bad_Opcode },
5368 { Bad_Opcode },
5369 { Bad_Opcode },
5370 { Bad_Opcode },
5371 { Bad_Opcode },
5372 /* b8 */
5373 { Bad_Opcode },
5374 { Bad_Opcode },
5375 { Bad_Opcode },
5376 { Bad_Opcode },
5377 { Bad_Opcode },
5378 { Bad_Opcode },
5379 { Bad_Opcode },
5380 { Bad_Opcode },
5381 /* c0 */
5382 { Bad_Opcode },
5383 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5384 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5385 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5386 { Bad_Opcode },
5387 { Bad_Opcode },
5388 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5389 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5390 /* c8 */
5391 { Bad_Opcode },
5392 { Bad_Opcode },
5393 { Bad_Opcode },
5394 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5395 { Bad_Opcode },
5396 { Bad_Opcode },
5397 { Bad_Opcode },
5398 { Bad_Opcode },
5399 /* d0 */
5400 { Bad_Opcode },
5401 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5402 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5403 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5404 { Bad_Opcode },
5405 { Bad_Opcode },
5406 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5407 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5408 /* d8 */
5409 { Bad_Opcode },
5410 { Bad_Opcode },
5411 { Bad_Opcode },
5412 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5413 { Bad_Opcode },
5414 { Bad_Opcode },
5415 { Bad_Opcode },
5416 { Bad_Opcode },
5417 /* e0 */
5418 { Bad_Opcode },
5419 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5420 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5421 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5422 { Bad_Opcode },
5423 { Bad_Opcode },
5424 { Bad_Opcode },
5425 { Bad_Opcode },
5426 /* e8 */
5427 { Bad_Opcode },
5428 { Bad_Opcode },
5429 { Bad_Opcode },
5430 { Bad_Opcode },
5431 { Bad_Opcode },
5432 { Bad_Opcode },
5433 { Bad_Opcode },
5434 { Bad_Opcode },
5435 /* f0 */
5436 { Bad_Opcode },
5437 { Bad_Opcode },
5438 { Bad_Opcode },
5439 { Bad_Opcode },
5440 { Bad_Opcode },
5441 { Bad_Opcode },
5442 { Bad_Opcode },
5443 { Bad_Opcode },
5444 /* f8 */
5445 { Bad_Opcode },
5446 { Bad_Opcode },
5447 { Bad_Opcode },
5448 { Bad_Opcode },
5449 { Bad_Opcode },
5450 { Bad_Opcode },
5451 { Bad_Opcode },
5452 { Bad_Opcode },
5453 },
5454 /* XOP_0A */
5455 {
5456 /* 00 */
5457 { Bad_Opcode },
5458 { Bad_Opcode },
5459 { Bad_Opcode },
5460 { Bad_Opcode },
5461 { Bad_Opcode },
5462 { Bad_Opcode },
5463 { Bad_Opcode },
5464 { Bad_Opcode },
5465 /* 08 */
5466 { Bad_Opcode },
5467 { Bad_Opcode },
5468 { Bad_Opcode },
5469 { Bad_Opcode },
5470 { Bad_Opcode },
5471 { Bad_Opcode },
5472 { Bad_Opcode },
5473 { Bad_Opcode },
5474 /* 10 */
5475 { "bextrS", { Gdq, Edq, Id }, 0 },
5476 { Bad_Opcode },
5477 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5478 { Bad_Opcode },
5479 { Bad_Opcode },
5480 { Bad_Opcode },
5481 { Bad_Opcode },
5482 { Bad_Opcode },
5483 /* 18 */
5484 { Bad_Opcode },
5485 { Bad_Opcode },
5486 { Bad_Opcode },
5487 { Bad_Opcode },
5488 { Bad_Opcode },
5489 { Bad_Opcode },
5490 { Bad_Opcode },
5491 { Bad_Opcode },
5492 /* 20 */
5493 { Bad_Opcode },
5494 { Bad_Opcode },
5495 { Bad_Opcode },
5496 { Bad_Opcode },
5497 { Bad_Opcode },
5498 { Bad_Opcode },
5499 { Bad_Opcode },
5500 { Bad_Opcode },
5501 /* 28 */
5502 { Bad_Opcode },
5503 { Bad_Opcode },
5504 { Bad_Opcode },
5505 { Bad_Opcode },
5506 { Bad_Opcode },
5507 { Bad_Opcode },
5508 { Bad_Opcode },
5509 { Bad_Opcode },
5510 /* 30 */
5511 { Bad_Opcode },
5512 { Bad_Opcode },
5513 { Bad_Opcode },
5514 { Bad_Opcode },
5515 { Bad_Opcode },
5516 { Bad_Opcode },
5517 { Bad_Opcode },
5518 { Bad_Opcode },
5519 /* 38 */
5520 { Bad_Opcode },
5521 { Bad_Opcode },
5522 { Bad_Opcode },
5523 { Bad_Opcode },
5524 { Bad_Opcode },
5525 { Bad_Opcode },
5526 { Bad_Opcode },
5527 { Bad_Opcode },
5528 /* 40 */
5529 { Bad_Opcode },
5530 { Bad_Opcode },
5531 { Bad_Opcode },
5532 { Bad_Opcode },
5533 { Bad_Opcode },
5534 { Bad_Opcode },
5535 { Bad_Opcode },
5536 { Bad_Opcode },
5537 /* 48 */
5538 { Bad_Opcode },
5539 { Bad_Opcode },
5540 { Bad_Opcode },
5541 { Bad_Opcode },
5542 { Bad_Opcode },
5543 { Bad_Opcode },
5544 { Bad_Opcode },
5545 { Bad_Opcode },
5546 /* 50 */
5547 { Bad_Opcode },
5548 { Bad_Opcode },
5549 { Bad_Opcode },
5550 { Bad_Opcode },
5551 { Bad_Opcode },
5552 { Bad_Opcode },
5553 { Bad_Opcode },
5554 { Bad_Opcode },
5555 /* 58 */
5556 { Bad_Opcode },
5557 { Bad_Opcode },
5558 { Bad_Opcode },
5559 { Bad_Opcode },
5560 { Bad_Opcode },
5561 { Bad_Opcode },
5562 { Bad_Opcode },
5563 { Bad_Opcode },
5564 /* 60 */
5565 { Bad_Opcode },
5566 { Bad_Opcode },
5567 { Bad_Opcode },
5568 { Bad_Opcode },
5569 { Bad_Opcode },
5570 { Bad_Opcode },
5571 { Bad_Opcode },
5572 { Bad_Opcode },
5573 /* 68 */
5574 { Bad_Opcode },
5575 { Bad_Opcode },
5576 { Bad_Opcode },
5577 { Bad_Opcode },
5578 { Bad_Opcode },
5579 { Bad_Opcode },
5580 { Bad_Opcode },
5581 { Bad_Opcode },
5582 /* 70 */
5583 { Bad_Opcode },
5584 { Bad_Opcode },
5585 { Bad_Opcode },
5586 { Bad_Opcode },
5587 { Bad_Opcode },
5588 { Bad_Opcode },
5589 { Bad_Opcode },
5590 { Bad_Opcode },
5591 /* 78 */
5592 { Bad_Opcode },
5593 { Bad_Opcode },
5594 { Bad_Opcode },
5595 { Bad_Opcode },
5596 { Bad_Opcode },
5597 { Bad_Opcode },
5598 { Bad_Opcode },
5599 { Bad_Opcode },
5600 /* 80 */
5601 { Bad_Opcode },
5602 { Bad_Opcode },
5603 { Bad_Opcode },
5604 { Bad_Opcode },
5605 { Bad_Opcode },
5606 { Bad_Opcode },
5607 { Bad_Opcode },
5608 { Bad_Opcode },
5609 /* 88 */
5610 { Bad_Opcode },
5611 { Bad_Opcode },
5612 { Bad_Opcode },
5613 { Bad_Opcode },
5614 { Bad_Opcode },
5615 { Bad_Opcode },
5616 { Bad_Opcode },
5617 { Bad_Opcode },
5618 /* 90 */
5619 { Bad_Opcode },
5620 { Bad_Opcode },
5621 { Bad_Opcode },
5622 { Bad_Opcode },
5623 { Bad_Opcode },
5624 { Bad_Opcode },
5625 { Bad_Opcode },
5626 { Bad_Opcode },
5627 /* 98 */
5628 { Bad_Opcode },
5629 { Bad_Opcode },
5630 { Bad_Opcode },
5631 { Bad_Opcode },
5632 { Bad_Opcode },
5633 { Bad_Opcode },
5634 { Bad_Opcode },
5635 { Bad_Opcode },
5636 /* a0 */
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 { Bad_Opcode },
5640 { Bad_Opcode },
5641 { Bad_Opcode },
5642 { Bad_Opcode },
5643 { Bad_Opcode },
5644 { Bad_Opcode },
5645 /* a8 */
5646 { Bad_Opcode },
5647 { Bad_Opcode },
5648 { Bad_Opcode },
5649 { Bad_Opcode },
5650 { Bad_Opcode },
5651 { Bad_Opcode },
5652 { Bad_Opcode },
5653 { Bad_Opcode },
5654 /* b0 */
5655 { Bad_Opcode },
5656 { Bad_Opcode },
5657 { Bad_Opcode },
5658 { Bad_Opcode },
5659 { Bad_Opcode },
5660 { Bad_Opcode },
5661 { Bad_Opcode },
5662 { Bad_Opcode },
5663 /* b8 */
5664 { Bad_Opcode },
5665 { Bad_Opcode },
5666 { Bad_Opcode },
5667 { Bad_Opcode },
5668 { Bad_Opcode },
5669 { Bad_Opcode },
5670 { Bad_Opcode },
5671 { Bad_Opcode },
5672 /* c0 */
5673 { Bad_Opcode },
5674 { Bad_Opcode },
5675 { Bad_Opcode },
5676 { Bad_Opcode },
5677 { Bad_Opcode },
5678 { Bad_Opcode },
5679 { Bad_Opcode },
5680 { Bad_Opcode },
5681 /* c8 */
5682 { Bad_Opcode },
5683 { Bad_Opcode },
5684 { Bad_Opcode },
5685 { Bad_Opcode },
5686 { Bad_Opcode },
5687 { Bad_Opcode },
5688 { Bad_Opcode },
5689 { Bad_Opcode },
5690 /* d0 */
5691 { Bad_Opcode },
5692 { Bad_Opcode },
5693 { Bad_Opcode },
5694 { Bad_Opcode },
5695 { Bad_Opcode },
5696 { Bad_Opcode },
5697 { Bad_Opcode },
5698 { Bad_Opcode },
5699 /* d8 */
5700 { Bad_Opcode },
5701 { Bad_Opcode },
5702 { Bad_Opcode },
5703 { Bad_Opcode },
5704 { Bad_Opcode },
5705 { Bad_Opcode },
5706 { Bad_Opcode },
5707 { Bad_Opcode },
5708 /* e0 */
5709 { Bad_Opcode },
5710 { Bad_Opcode },
5711 { Bad_Opcode },
5712 { Bad_Opcode },
5713 { Bad_Opcode },
5714 { Bad_Opcode },
5715 { Bad_Opcode },
5716 { Bad_Opcode },
5717 /* e8 */
5718 { Bad_Opcode },
5719 { Bad_Opcode },
5720 { Bad_Opcode },
5721 { Bad_Opcode },
5722 { Bad_Opcode },
5723 { Bad_Opcode },
5724 { Bad_Opcode },
5725 { Bad_Opcode },
5726 /* f0 */
5727 { Bad_Opcode },
5728 { Bad_Opcode },
5729 { Bad_Opcode },
5730 { Bad_Opcode },
5731 { Bad_Opcode },
5732 { Bad_Opcode },
5733 { Bad_Opcode },
5734 { Bad_Opcode },
5735 /* f8 */
5736 { Bad_Opcode },
5737 { Bad_Opcode },
5738 { Bad_Opcode },
5739 { Bad_Opcode },
5740 { Bad_Opcode },
5741 { Bad_Opcode },
5742 { Bad_Opcode },
5743 { Bad_Opcode },
5744 },
5745 };
5746
5747 static const struct dis386 vex_table[][256] = {
5748 /* VEX_0F */
5749 {
5750 /* 00 */
5751 { Bad_Opcode },
5752 { Bad_Opcode },
5753 { Bad_Opcode },
5754 { Bad_Opcode },
5755 { Bad_Opcode },
5756 { Bad_Opcode },
5757 { Bad_Opcode },
5758 { Bad_Opcode },
5759 /* 08 */
5760 { Bad_Opcode },
5761 { Bad_Opcode },
5762 { Bad_Opcode },
5763 { Bad_Opcode },
5764 { Bad_Opcode },
5765 { Bad_Opcode },
5766 { Bad_Opcode },
5767 { Bad_Opcode },
5768 /* 10 */
5769 { PREFIX_TABLE (PREFIX_VEX_0F10) },
5770 { PREFIX_TABLE (PREFIX_VEX_0F11) },
5771 { PREFIX_TABLE (PREFIX_VEX_0F12) },
5772 { MOD_TABLE (MOD_VEX_0F13) },
5773 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5774 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5775 { PREFIX_TABLE (PREFIX_VEX_0F16) },
5776 { MOD_TABLE (MOD_VEX_0F17) },
5777 /* 18 */
5778 { Bad_Opcode },
5779 { Bad_Opcode },
5780 { Bad_Opcode },
5781 { Bad_Opcode },
5782 { Bad_Opcode },
5783 { Bad_Opcode },
5784 { Bad_Opcode },
5785 { Bad_Opcode },
5786 /* 20 */
5787 { Bad_Opcode },
5788 { Bad_Opcode },
5789 { Bad_Opcode },
5790 { Bad_Opcode },
5791 { Bad_Opcode },
5792 { Bad_Opcode },
5793 { Bad_Opcode },
5794 { Bad_Opcode },
5795 /* 28 */
5796 { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
5797 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
5798 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5799 { MOD_TABLE (MOD_VEX_0F2B) },
5800 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5801 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5802 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5803 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5804 /* 30 */
5805 { Bad_Opcode },
5806 { Bad_Opcode },
5807 { Bad_Opcode },
5808 { Bad_Opcode },
5809 { Bad_Opcode },
5810 { Bad_Opcode },
5811 { Bad_Opcode },
5812 { Bad_Opcode },
5813 /* 38 */
5814 { Bad_Opcode },
5815 { Bad_Opcode },
5816 { Bad_Opcode },
5817 { Bad_Opcode },
5818 { Bad_Opcode },
5819 { Bad_Opcode },
5820 { Bad_Opcode },
5821 { Bad_Opcode },
5822 /* 40 */
5823 { Bad_Opcode },
5824 { PREFIX_TABLE (PREFIX_VEX_0F41) },
5825 { PREFIX_TABLE (PREFIX_VEX_0F42) },
5826 { Bad_Opcode },
5827 { PREFIX_TABLE (PREFIX_VEX_0F44) },
5828 { PREFIX_TABLE (PREFIX_VEX_0F45) },
5829 { PREFIX_TABLE (PREFIX_VEX_0F46) },
5830 { PREFIX_TABLE (PREFIX_VEX_0F47) },
5831 /* 48 */
5832 { Bad_Opcode },
5833 { Bad_Opcode },
5834 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
5835 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 { Bad_Opcode },
5839 { Bad_Opcode },
5840 /* 50 */
5841 { MOD_TABLE (MOD_VEX_0F50) },
5842 { PREFIX_TABLE (PREFIX_VEX_0F51) },
5843 { PREFIX_TABLE (PREFIX_VEX_0F52) },
5844 { PREFIX_TABLE (PREFIX_VEX_0F53) },
5845 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5846 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5847 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5848 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5849 /* 58 */
5850 { PREFIX_TABLE (PREFIX_VEX_0F58) },
5851 { PREFIX_TABLE (PREFIX_VEX_0F59) },
5852 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5853 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5854 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5855 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5856 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5857 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5858 /* 60 */
5859 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
5860 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
5861 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
5862 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
5863 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
5864 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
5865 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
5866 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
5867 /* 68 */
5868 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
5869 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
5870 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
5871 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
5872 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
5873 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
5874 { VEX_LEN_TABLE (VEX_LEN_0F6E) },
5875 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
5876 /* 70 */
5877 { PREFIX_TABLE (PREFIX_VEX_0F70) },
5878 { REG_TABLE (REG_VEX_0F71) },
5879 { REG_TABLE (REG_VEX_0F72) },
5880 { REG_TABLE (REG_VEX_0F73) },
5881 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
5882 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
5883 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
5884 { PREFIX_TABLE (PREFIX_VEX_0F77) },
5885 /* 78 */
5886 { Bad_Opcode },
5887 { Bad_Opcode },
5888 { Bad_Opcode },
5889 { Bad_Opcode },
5890 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
5891 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
5892 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
5893 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
5894 /* 80 */
5895 { Bad_Opcode },
5896 { Bad_Opcode },
5897 { Bad_Opcode },
5898 { Bad_Opcode },
5899 { Bad_Opcode },
5900 { Bad_Opcode },
5901 { Bad_Opcode },
5902 { Bad_Opcode },
5903 /* 88 */
5904 { Bad_Opcode },
5905 { Bad_Opcode },
5906 { Bad_Opcode },
5907 { Bad_Opcode },
5908 { Bad_Opcode },
5909 { Bad_Opcode },
5910 { Bad_Opcode },
5911 { Bad_Opcode },
5912 /* 90 */
5913 { PREFIX_TABLE (PREFIX_VEX_0F90) },
5914 { PREFIX_TABLE (PREFIX_VEX_0F91) },
5915 { PREFIX_TABLE (PREFIX_VEX_0F92) },
5916 { PREFIX_TABLE (PREFIX_VEX_0F93) },
5917 { Bad_Opcode },
5918 { Bad_Opcode },
5919 { Bad_Opcode },
5920 { Bad_Opcode },
5921 /* 98 */
5922 { PREFIX_TABLE (PREFIX_VEX_0F98) },
5923 { PREFIX_TABLE (PREFIX_VEX_0F99) },
5924 { Bad_Opcode },
5925 { Bad_Opcode },
5926 { Bad_Opcode },
5927 { Bad_Opcode },
5928 { Bad_Opcode },
5929 { Bad_Opcode },
5930 /* a0 */
5931 { Bad_Opcode },
5932 { Bad_Opcode },
5933 { Bad_Opcode },
5934 { Bad_Opcode },
5935 { Bad_Opcode },
5936 { Bad_Opcode },
5937 { Bad_Opcode },
5938 { Bad_Opcode },
5939 /* a8 */
5940 { Bad_Opcode },
5941 { Bad_Opcode },
5942 { Bad_Opcode },
5943 { Bad_Opcode },
5944 { Bad_Opcode },
5945 { Bad_Opcode },
5946 { REG_TABLE (REG_VEX_0FAE) },
5947 { Bad_Opcode },
5948 /* b0 */
5949 { Bad_Opcode },
5950 { Bad_Opcode },
5951 { Bad_Opcode },
5952 { Bad_Opcode },
5953 { Bad_Opcode },
5954 { Bad_Opcode },
5955 { Bad_Opcode },
5956 { Bad_Opcode },
5957 /* b8 */
5958 { Bad_Opcode },
5959 { Bad_Opcode },
5960 { Bad_Opcode },
5961 { Bad_Opcode },
5962 { Bad_Opcode },
5963 { Bad_Opcode },
5964 { Bad_Opcode },
5965 { Bad_Opcode },
5966 /* c0 */
5967 { Bad_Opcode },
5968 { Bad_Opcode },
5969 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
5970 { Bad_Opcode },
5971 { VEX_LEN_TABLE (VEX_LEN_0FC4) },
5972 { VEX_LEN_TABLE (VEX_LEN_0FC5) },
5973 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
5974 { Bad_Opcode },
5975 /* c8 */
5976 { Bad_Opcode },
5977 { Bad_Opcode },
5978 { Bad_Opcode },
5979 { Bad_Opcode },
5980 { Bad_Opcode },
5981 { Bad_Opcode },
5982 { Bad_Opcode },
5983 { Bad_Opcode },
5984 /* d0 */
5985 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
5986 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
5987 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
5988 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
5989 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
5990 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
5991 { VEX_LEN_TABLE (VEX_LEN_0FD6) },
5992 { MOD_TABLE (MOD_VEX_0FD7) },
5993 /* d8 */
5994 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
5995 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
5996 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
5997 { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
5998 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
5999 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
6000 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
6001 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
6002 /* e0 */
6003 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
6004 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
6005 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
6006 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
6007 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
6008 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
6009 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6010 { MOD_TABLE (MOD_VEX_0FE7) },
6011 /* e8 */
6012 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
6013 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6014 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
6015 { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
6016 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
6017 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6018 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
6019 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
6020 /* f0 */
6021 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6022 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
6023 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
6024 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
6025 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
6026 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
6027 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
6028 { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6029 /* f8 */
6030 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
6031 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
6032 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
6033 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
6034 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
6035 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
6036 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
6037 { Bad_Opcode },
6038 },
6039 /* VEX_0F38 */
6040 {
6041 /* 00 */
6042 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
6043 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
6044 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
6045 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6046 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
6047 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
6048 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
6049 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6050 /* 08 */
6051 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
6052 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
6053 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
6054 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
6055 { VEX_W_TABLE (VEX_W_0F380C) },
6056 { VEX_W_TABLE (VEX_W_0F380D) },
6057 { VEX_W_TABLE (VEX_W_0F380E) },
6058 { VEX_W_TABLE (VEX_W_0F380F) },
6059 /* 10 */
6060 { Bad_Opcode },
6061 { Bad_Opcode },
6062 { Bad_Opcode },
6063 { VEX_W_TABLE (VEX_W_0F3813) },
6064 { Bad_Opcode },
6065 { Bad_Opcode },
6066 { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6067 { "vptest", { XM, EXx }, PREFIX_DATA },
6068 /* 18 */
6069 { VEX_W_TABLE (VEX_W_0F3818) },
6070 { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6071 { MOD_TABLE (MOD_VEX_0F381A) },
6072 { Bad_Opcode },
6073 { "vpabsb", { XM, EXx }, PREFIX_DATA },
6074 { "vpabsw", { XM, EXx }, PREFIX_DATA },
6075 { "vpabsd", { XM, EXx }, PREFIX_DATA },
6076 { Bad_Opcode },
6077 /* 20 */
6078 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA },
6079 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA },
6080 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA },
6081 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA },
6082 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA },
6083 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA },
6084 { Bad_Opcode },
6085 { Bad_Opcode },
6086 /* 28 */
6087 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
6088 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
6089 { MOD_TABLE (MOD_VEX_0F382A) },
6090 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
6091 { MOD_TABLE (MOD_VEX_0F382C) },
6092 { MOD_TABLE (MOD_VEX_0F382D) },
6093 { MOD_TABLE (MOD_VEX_0F382E) },
6094 { MOD_TABLE (MOD_VEX_0F382F) },
6095 /* 30 */
6096 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
6097 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
6098 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA },
6099 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA },
6100 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA },
6101 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA },
6102 { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6103 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6104 /* 38 */
6105 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
6106 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
6107 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
6108 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
6109 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
6110 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
6111 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
6112 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
6113 /* 40 */
6114 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
6115 { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6116 { Bad_Opcode },
6117 { Bad_Opcode },
6118 { Bad_Opcode },
6119 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6120 { VEX_W_TABLE (VEX_W_0F3846) },
6121 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6122 /* 48 */
6123 { Bad_Opcode },
6124 { X86_64_TABLE (X86_64_VEX_0F3849) },
6125 { Bad_Opcode },
6126 { X86_64_TABLE (X86_64_VEX_0F384B) },
6127 { Bad_Opcode },
6128 { Bad_Opcode },
6129 { Bad_Opcode },
6130 { Bad_Opcode },
6131 /* 50 */
6132 { Bad_Opcode },
6133 { Bad_Opcode },
6134 { Bad_Opcode },
6135 { Bad_Opcode },
6136 { Bad_Opcode },
6137 { Bad_Opcode },
6138 { Bad_Opcode },
6139 { Bad_Opcode },
6140 /* 58 */
6141 { VEX_W_TABLE (VEX_W_0F3858) },
6142 { VEX_W_TABLE (VEX_W_0F3859) },
6143 { MOD_TABLE (MOD_VEX_0F385A) },
6144 { Bad_Opcode },
6145 { X86_64_TABLE (X86_64_VEX_0F385C) },
6146 { Bad_Opcode },
6147 { X86_64_TABLE (X86_64_VEX_0F385E) },
6148 { Bad_Opcode },
6149 /* 60 */
6150 { Bad_Opcode },
6151 { Bad_Opcode },
6152 { Bad_Opcode },
6153 { Bad_Opcode },
6154 { Bad_Opcode },
6155 { Bad_Opcode },
6156 { Bad_Opcode },
6157 { Bad_Opcode },
6158 /* 68 */
6159 { Bad_Opcode },
6160 { Bad_Opcode },
6161 { Bad_Opcode },
6162 { Bad_Opcode },
6163 { Bad_Opcode },
6164 { Bad_Opcode },
6165 { Bad_Opcode },
6166 { Bad_Opcode },
6167 /* 70 */
6168 { Bad_Opcode },
6169 { Bad_Opcode },
6170 { Bad_Opcode },
6171 { Bad_Opcode },
6172 { Bad_Opcode },
6173 { Bad_Opcode },
6174 { Bad_Opcode },
6175 { Bad_Opcode },
6176 /* 78 */
6177 { VEX_W_TABLE (VEX_W_0F3878) },
6178 { VEX_W_TABLE (VEX_W_0F3879) },
6179 { Bad_Opcode },
6180 { Bad_Opcode },
6181 { Bad_Opcode },
6182 { Bad_Opcode },
6183 { Bad_Opcode },
6184 { Bad_Opcode },
6185 /* 80 */
6186 { Bad_Opcode },
6187 { Bad_Opcode },
6188 { Bad_Opcode },
6189 { Bad_Opcode },
6190 { Bad_Opcode },
6191 { Bad_Opcode },
6192 { Bad_Opcode },
6193 { Bad_Opcode },
6194 /* 88 */
6195 { Bad_Opcode },
6196 { Bad_Opcode },
6197 { Bad_Opcode },
6198 { Bad_Opcode },
6199 { MOD_TABLE (MOD_VEX_0F388C) },
6200 { Bad_Opcode },
6201 { MOD_TABLE (MOD_VEX_0F388E) },
6202 { Bad_Opcode },
6203 /* 90 */
6204 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6205 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6206 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6207 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6208 { Bad_Opcode },
6209 { Bad_Opcode },
6210 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6211 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6212 /* 98 */
6213 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6214 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6215 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6216 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6217 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6218 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6219 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6220 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6221 /* a0 */
6222 { Bad_Opcode },
6223 { Bad_Opcode },
6224 { Bad_Opcode },
6225 { Bad_Opcode },
6226 { Bad_Opcode },
6227 { Bad_Opcode },
6228 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6229 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6230 /* a8 */
6231 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6232 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6233 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6234 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6235 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6236 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6237 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6238 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6239 /* b0 */
6240 { Bad_Opcode },
6241 { Bad_Opcode },
6242 { Bad_Opcode },
6243 { Bad_Opcode },
6244 { Bad_Opcode },
6245 { Bad_Opcode },
6246 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6247 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6248 /* b8 */
6249 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6250 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6251 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6252 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6253 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6254 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6255 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6256 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6257 /* c0 */
6258 { Bad_Opcode },
6259 { Bad_Opcode },
6260 { Bad_Opcode },
6261 { Bad_Opcode },
6262 { Bad_Opcode },
6263 { Bad_Opcode },
6264 { Bad_Opcode },
6265 { Bad_Opcode },
6266 /* c8 */
6267 { Bad_Opcode },
6268 { Bad_Opcode },
6269 { Bad_Opcode },
6270 { Bad_Opcode },
6271 { Bad_Opcode },
6272 { Bad_Opcode },
6273 { Bad_Opcode },
6274 { VEX_W_TABLE (VEX_W_0F38CF) },
6275 /* d0 */
6276 { Bad_Opcode },
6277 { Bad_Opcode },
6278 { Bad_Opcode },
6279 { Bad_Opcode },
6280 { Bad_Opcode },
6281 { Bad_Opcode },
6282 { Bad_Opcode },
6283 { Bad_Opcode },
6284 /* d8 */
6285 { Bad_Opcode },
6286 { Bad_Opcode },
6287 { Bad_Opcode },
6288 { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6289 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
6290 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
6291 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
6292 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
6293 /* e0 */
6294 { Bad_Opcode },
6295 { Bad_Opcode },
6296 { Bad_Opcode },
6297 { Bad_Opcode },
6298 { Bad_Opcode },
6299 { Bad_Opcode },
6300 { Bad_Opcode },
6301 { Bad_Opcode },
6302 /* e8 */
6303 { Bad_Opcode },
6304 { Bad_Opcode },
6305 { Bad_Opcode },
6306 { Bad_Opcode },
6307 { Bad_Opcode },
6308 { Bad_Opcode },
6309 { Bad_Opcode },
6310 { Bad_Opcode },
6311 /* f0 */
6312 { Bad_Opcode },
6313 { Bad_Opcode },
6314 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
6315 { REG_TABLE (REG_VEX_0F38F3) },
6316 { Bad_Opcode },
6317 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
6318 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
6319 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
6320 /* f8 */
6321 { Bad_Opcode },
6322 { Bad_Opcode },
6323 { Bad_Opcode },
6324 { Bad_Opcode },
6325 { Bad_Opcode },
6326 { Bad_Opcode },
6327 { Bad_Opcode },
6328 { Bad_Opcode },
6329 },
6330 /* VEX_0F3A */
6331 {
6332 /* 00 */
6333 { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6334 { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6335 { VEX_W_TABLE (VEX_W_0F3A02) },
6336 { Bad_Opcode },
6337 { VEX_W_TABLE (VEX_W_0F3A04) },
6338 { VEX_W_TABLE (VEX_W_0F3A05) },
6339 { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6340 { Bad_Opcode },
6341 /* 08 */
6342 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6343 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6344 { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
6345 { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
6346 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6347 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6348 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6349 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6350 /* 10 */
6351 { Bad_Opcode },
6352 { Bad_Opcode },
6353 { Bad_Opcode },
6354 { Bad_Opcode },
6355 { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6356 { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6357 { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6358 { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6359 /* 18 */
6360 { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6361 { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6362 { Bad_Opcode },
6363 { Bad_Opcode },
6364 { Bad_Opcode },
6365 { VEX_W_TABLE (VEX_W_0F3A1D) },
6366 { Bad_Opcode },
6367 { Bad_Opcode },
6368 /* 20 */
6369 { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6370 { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6371 { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6372 { Bad_Opcode },
6373 { Bad_Opcode },
6374 { Bad_Opcode },
6375 { Bad_Opcode },
6376 { Bad_Opcode },
6377 /* 28 */
6378 { Bad_Opcode },
6379 { Bad_Opcode },
6380 { Bad_Opcode },
6381 { Bad_Opcode },
6382 { Bad_Opcode },
6383 { Bad_Opcode },
6384 { Bad_Opcode },
6385 { Bad_Opcode },
6386 /* 30 */
6387 { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6388 { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6389 { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6390 { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6391 { Bad_Opcode },
6392 { Bad_Opcode },
6393 { Bad_Opcode },
6394 { Bad_Opcode },
6395 /* 38 */
6396 { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6397 { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6398 { Bad_Opcode },
6399 { Bad_Opcode },
6400 { Bad_Opcode },
6401 { Bad_Opcode },
6402 { Bad_Opcode },
6403 { Bad_Opcode },
6404 /* 40 */
6405 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6406 { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6407 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6408 { Bad_Opcode },
6409 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6410 { Bad_Opcode },
6411 { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6412 { Bad_Opcode },
6413 /* 48 */
6414 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6415 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6416 { VEX_W_TABLE (VEX_W_0F3A4A) },
6417 { VEX_W_TABLE (VEX_W_0F3A4B) },
6418 { VEX_W_TABLE (VEX_W_0F3A4C) },
6419 { Bad_Opcode },
6420 { Bad_Opcode },
6421 { Bad_Opcode },
6422 /* 50 */
6423 { Bad_Opcode },
6424 { Bad_Opcode },
6425 { Bad_Opcode },
6426 { Bad_Opcode },
6427 { Bad_Opcode },
6428 { Bad_Opcode },
6429 { Bad_Opcode },
6430 { Bad_Opcode },
6431 /* 58 */
6432 { Bad_Opcode },
6433 { Bad_Opcode },
6434 { Bad_Opcode },
6435 { Bad_Opcode },
6436 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6437 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6438 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6439 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6440 /* 60 */
6441 { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6442 { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6443 { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6444 { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6445 { Bad_Opcode },
6446 { Bad_Opcode },
6447 { Bad_Opcode },
6448 { Bad_Opcode },
6449 /* 68 */
6450 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6451 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6452 { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6453 { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6454 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6455 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6456 { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6457 { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6458 /* 70 */
6459 { Bad_Opcode },
6460 { Bad_Opcode },
6461 { Bad_Opcode },
6462 { Bad_Opcode },
6463 { Bad_Opcode },
6464 { Bad_Opcode },
6465 { Bad_Opcode },
6466 { Bad_Opcode },
6467 /* 78 */
6468 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6469 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6470 { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6471 { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6472 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6473 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6474 { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6475 { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6476 /* 80 */
6477 { Bad_Opcode },
6478 { Bad_Opcode },
6479 { Bad_Opcode },
6480 { Bad_Opcode },
6481 { Bad_Opcode },
6482 { Bad_Opcode },
6483 { Bad_Opcode },
6484 { Bad_Opcode },
6485 /* 88 */
6486 { Bad_Opcode },
6487 { Bad_Opcode },
6488 { Bad_Opcode },
6489 { Bad_Opcode },
6490 { Bad_Opcode },
6491 { Bad_Opcode },
6492 { Bad_Opcode },
6493 { Bad_Opcode },
6494 /* 90 */
6495 { Bad_Opcode },
6496 { Bad_Opcode },
6497 { Bad_Opcode },
6498 { Bad_Opcode },
6499 { Bad_Opcode },
6500 { Bad_Opcode },
6501 { Bad_Opcode },
6502 { Bad_Opcode },
6503 /* 98 */
6504 { Bad_Opcode },
6505 { Bad_Opcode },
6506 { Bad_Opcode },
6507 { Bad_Opcode },
6508 { Bad_Opcode },
6509 { Bad_Opcode },
6510 { Bad_Opcode },
6511 { Bad_Opcode },
6512 /* a0 */
6513 { Bad_Opcode },
6514 { Bad_Opcode },
6515 { Bad_Opcode },
6516 { Bad_Opcode },
6517 { Bad_Opcode },
6518 { Bad_Opcode },
6519 { Bad_Opcode },
6520 { Bad_Opcode },
6521 /* a8 */
6522 { Bad_Opcode },
6523 { Bad_Opcode },
6524 { Bad_Opcode },
6525 { Bad_Opcode },
6526 { Bad_Opcode },
6527 { Bad_Opcode },
6528 { Bad_Opcode },
6529 { Bad_Opcode },
6530 /* b0 */
6531 { Bad_Opcode },
6532 { Bad_Opcode },
6533 { Bad_Opcode },
6534 { Bad_Opcode },
6535 { Bad_Opcode },
6536 { Bad_Opcode },
6537 { Bad_Opcode },
6538 { Bad_Opcode },
6539 /* b8 */
6540 { Bad_Opcode },
6541 { Bad_Opcode },
6542 { Bad_Opcode },
6543 { Bad_Opcode },
6544 { Bad_Opcode },
6545 { Bad_Opcode },
6546 { Bad_Opcode },
6547 { Bad_Opcode },
6548 /* c0 */
6549 { Bad_Opcode },
6550 { Bad_Opcode },
6551 { Bad_Opcode },
6552 { Bad_Opcode },
6553 { Bad_Opcode },
6554 { Bad_Opcode },
6555 { Bad_Opcode },
6556 { Bad_Opcode },
6557 /* c8 */
6558 { Bad_Opcode },
6559 { Bad_Opcode },
6560 { Bad_Opcode },
6561 { Bad_Opcode },
6562 { Bad_Opcode },
6563 { Bad_Opcode },
6564 { VEX_W_TABLE (VEX_W_0F3ACE) },
6565 { VEX_W_TABLE (VEX_W_0F3ACF) },
6566 /* d0 */
6567 { Bad_Opcode },
6568 { Bad_Opcode },
6569 { Bad_Opcode },
6570 { Bad_Opcode },
6571 { Bad_Opcode },
6572 { Bad_Opcode },
6573 { Bad_Opcode },
6574 { Bad_Opcode },
6575 /* d8 */
6576 { Bad_Opcode },
6577 { Bad_Opcode },
6578 { Bad_Opcode },
6579 { Bad_Opcode },
6580 { Bad_Opcode },
6581 { Bad_Opcode },
6582 { Bad_Opcode },
6583 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6584 /* e0 */
6585 { Bad_Opcode },
6586 { Bad_Opcode },
6587 { Bad_Opcode },
6588 { Bad_Opcode },
6589 { Bad_Opcode },
6590 { Bad_Opcode },
6591 { Bad_Opcode },
6592 { Bad_Opcode },
6593 /* e8 */
6594 { Bad_Opcode },
6595 { Bad_Opcode },
6596 { Bad_Opcode },
6597 { Bad_Opcode },
6598 { Bad_Opcode },
6599 { Bad_Opcode },
6600 { Bad_Opcode },
6601 { Bad_Opcode },
6602 /* f0 */
6603 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
6604 { Bad_Opcode },
6605 { Bad_Opcode },
6606 { Bad_Opcode },
6607 { Bad_Opcode },
6608 { Bad_Opcode },
6609 { Bad_Opcode },
6610 { Bad_Opcode },
6611 /* f8 */
6612 { Bad_Opcode },
6613 { Bad_Opcode },
6614 { Bad_Opcode },
6615 { Bad_Opcode },
6616 { Bad_Opcode },
6617 { Bad_Opcode },
6618 { Bad_Opcode },
6619 { Bad_Opcode },
6620 },
6621 };
6622
6623 #include "i386-dis-evex.h"
6624
6625 static const struct dis386 vex_len_table[][2] = {
6626 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6627 {
6628 { "vmovlpX", { XM, Vex, EXq }, 0 },
6629 },
6630
6631 /* VEX_LEN_0F12_P_0_M_1 */
6632 {
6633 { "vmovhlps", { XM, Vex, EXq }, 0 },
6634 },
6635
6636 /* VEX_LEN_0F13_M_0 */
6637 {
6638 { "vmovlpX", { EXq, XM }, PREFIX_OPCODE },
6639 },
6640
6641 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6642 {
6643 { "vmovhpX", { XM, Vex, EXq }, 0 },
6644 },
6645
6646 /* VEX_LEN_0F16_P_0_M_1 */
6647 {
6648 { "vmovlhps", { XM, Vex, EXq }, 0 },
6649 },
6650
6651 /* VEX_LEN_0F17_M_0 */
6652 {
6653 { "vmovhpX", { EXq, XM }, PREFIX_OPCODE },
6654 },
6655
6656 /* VEX_LEN_0F41_P_0 */
6657 {
6658 { Bad_Opcode },
6659 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
6660 },
6661 /* VEX_LEN_0F41_P_2 */
6662 {
6663 { Bad_Opcode },
6664 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
6665 },
6666 /* VEX_LEN_0F42_P_0 */
6667 {
6668 { Bad_Opcode },
6669 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
6670 },
6671 /* VEX_LEN_0F42_P_2 */
6672 {
6673 { Bad_Opcode },
6674 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
6675 },
6676 /* VEX_LEN_0F44_P_0 */
6677 {
6678 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
6679 },
6680 /* VEX_LEN_0F44_P_2 */
6681 {
6682 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
6683 },
6684 /* VEX_LEN_0F45_P_0 */
6685 {
6686 { Bad_Opcode },
6687 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
6688 },
6689 /* VEX_LEN_0F45_P_2 */
6690 {
6691 { Bad_Opcode },
6692 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
6693 },
6694 /* VEX_LEN_0F46_P_0 */
6695 {
6696 { Bad_Opcode },
6697 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
6698 },
6699 /* VEX_LEN_0F46_P_2 */
6700 {
6701 { Bad_Opcode },
6702 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
6703 },
6704 /* VEX_LEN_0F47_P_0 */
6705 {
6706 { Bad_Opcode },
6707 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
6708 },
6709 /* VEX_LEN_0F47_P_2 */
6710 {
6711 { Bad_Opcode },
6712 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
6713 },
6714 /* VEX_LEN_0F4A_P_0 */
6715 {
6716 { Bad_Opcode },
6717 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
6718 },
6719 /* VEX_LEN_0F4A_P_2 */
6720 {
6721 { Bad_Opcode },
6722 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
6723 },
6724 /* VEX_LEN_0F4B_P_0 */
6725 {
6726 { Bad_Opcode },
6727 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
6728 },
6729 /* VEX_LEN_0F4B_P_2 */
6730 {
6731 { Bad_Opcode },
6732 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
6733 },
6734
6735 /* VEX_LEN_0F6E */
6736 {
6737 { "vmovK", { XMScalar, Edq }, PREFIX_DATA },
6738 },
6739
6740 /* VEX_LEN_0F77_P_1 */
6741 {
6742 { "vzeroupper", { XX }, 0 },
6743 { "vzeroall", { XX }, 0 },
6744 },
6745
6746 /* VEX_LEN_0F7E_P_1 */
6747 {
6748 { "vmovq", { XMScalar, EXxmm_mq }, 0 },
6749 },
6750
6751 /* VEX_LEN_0F7E_P_2 */
6752 {
6753 { "vmovK", { Edq, XMScalar }, 0 },
6754 },
6755
6756 /* VEX_LEN_0F90_P_0 */
6757 {
6758 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
6759 },
6760
6761 /* VEX_LEN_0F90_P_2 */
6762 {
6763 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
6764 },
6765
6766 /* VEX_LEN_0F91_P_0 */
6767 {
6768 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
6769 },
6770
6771 /* VEX_LEN_0F91_P_2 */
6772 {
6773 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
6774 },
6775
6776 /* VEX_LEN_0F92_P_0 */
6777 {
6778 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
6779 },
6780
6781 /* VEX_LEN_0F92_P_2 */
6782 {
6783 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
6784 },
6785
6786 /* VEX_LEN_0F92_P_3 */
6787 {
6788 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
6789 },
6790
6791 /* VEX_LEN_0F93_P_0 */
6792 {
6793 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
6794 },
6795
6796 /* VEX_LEN_0F93_P_2 */
6797 {
6798 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
6799 },
6800
6801 /* VEX_LEN_0F93_P_3 */
6802 {
6803 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
6804 },
6805
6806 /* VEX_LEN_0F98_P_0 */
6807 {
6808 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
6809 },
6810
6811 /* VEX_LEN_0F98_P_2 */
6812 {
6813 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
6814 },
6815
6816 /* VEX_LEN_0F99_P_0 */
6817 {
6818 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
6819 },
6820
6821 /* VEX_LEN_0F99_P_2 */
6822 {
6823 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
6824 },
6825
6826 /* VEX_LEN_0FAE_R_2_M_0 */
6827 {
6828 { "vldmxcsr", { Md }, 0 },
6829 },
6830
6831 /* VEX_LEN_0FAE_R_3_M_0 */
6832 {
6833 { "vstmxcsr", { Md }, 0 },
6834 },
6835
6836 /* VEX_LEN_0FC4 */
6837 {
6838 { "vpinsrw", { XM, Vex, Edqw, Ib }, PREFIX_DATA },
6839 },
6840
6841 /* VEX_LEN_0FC5 */
6842 {
6843 { "vpextrw", { Gdq, XS, Ib }, PREFIX_DATA },
6844 },
6845
6846 /* VEX_LEN_0FD6 */
6847 {
6848 { "vmovq", { EXqS, XMScalar }, PREFIX_DATA },
6849 },
6850
6851 /* VEX_LEN_0FF7 */
6852 {
6853 { "vmaskmovdqu", { XM, XS }, PREFIX_DATA },
6854 },
6855
6856 /* VEX_LEN_0F3816 */
6857 {
6858 { Bad_Opcode },
6859 { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6860 },
6861
6862 /* VEX_LEN_0F3819 */
6863 {
6864 { Bad_Opcode },
6865 { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6866 },
6867
6868 /* VEX_LEN_0F381A_M_0 */
6869 {
6870 { Bad_Opcode },
6871 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6872 },
6873
6874 /* VEX_LEN_0F3836 */
6875 {
6876 { Bad_Opcode },
6877 { VEX_W_TABLE (VEX_W_0F3836) },
6878 },
6879
6880 /* VEX_LEN_0F3841 */
6881 {
6882 { "vphminposuw", { XM, EXx }, PREFIX_DATA },
6883 },
6884
6885 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6886 {
6887 { "ldtilecfg", { M }, 0 },
6888 },
6889
6890 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6891 {
6892 { "tilerelease", { Skip_MODRM }, 0 },
6893 },
6894
6895 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6896 {
6897 { "sttilecfg", { M }, 0 },
6898 },
6899
6900 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6901 {
6902 { "tilezero", { TMM, Skip_MODRM }, 0 },
6903 },
6904
6905 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6906 {
6907 { "tilestored", { MVexSIBMEM, TMM }, 0 },
6908 },
6909 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6910 {
6911 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
6912 },
6913
6914 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6915 {
6916 { "tileloadd", { TMM, MVexSIBMEM }, 0 },
6917 },
6918
6919 /* VEX_LEN_0F385A_M_0 */
6920 {
6921 { Bad_Opcode },
6922 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
6923 },
6924
6925 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6926 {
6927 { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
6928 },
6929
6930 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6931 {
6932 { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
6933 },
6934
6935 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6936 {
6937 { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
6938 },
6939
6940 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6941 {
6942 { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
6943 },
6944
6945 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6946 {
6947 { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
6948 },
6949
6950 /* VEX_LEN_0F38DB */
6951 {
6952 { "vaesimc", { XM, EXx }, PREFIX_DATA },
6953 },
6954
6955 /* VEX_LEN_0F38F2_P_0 */
6956 {
6957 { "andnS", { Gdq, VexGdq, Edq }, 0 },
6958 },
6959
6960 /* VEX_LEN_0F38F3_R_1_P_0 */
6961 {
6962 { "blsrS", { VexGdq, Edq }, 0 },
6963 },
6964
6965 /* VEX_LEN_0F38F3_R_2_P_0 */
6966 {
6967 { "blsmskS", { VexGdq, Edq }, 0 },
6968 },
6969
6970 /* VEX_LEN_0F38F3_R_3_P_0 */
6971 {
6972 { "blsiS", { VexGdq, Edq }, 0 },
6973 },
6974
6975 /* VEX_LEN_0F38F5_P_0 */
6976 {
6977 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
6978 },
6979
6980 /* VEX_LEN_0F38F5_P_1 */
6981 {
6982 { "pextS", { Gdq, VexGdq, Edq }, 0 },
6983 },
6984
6985 /* VEX_LEN_0F38F5_P_3 */
6986 {
6987 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
6988 },
6989
6990 /* VEX_LEN_0F38F6_P_3 */
6991 {
6992 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
6993 },
6994
6995 /* VEX_LEN_0F38F7_P_0 */
6996 {
6997 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
6998 },
6999
7000 /* VEX_LEN_0F38F7_P_1 */
7001 {
7002 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
7003 },
7004
7005 /* VEX_LEN_0F38F7_P_2 */
7006 {
7007 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
7008 },
7009
7010 /* VEX_LEN_0F38F7_P_3 */
7011 {
7012 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
7013 },
7014
7015 /* VEX_LEN_0F3A00 */
7016 {
7017 { Bad_Opcode },
7018 { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7019 },
7020
7021 /* VEX_LEN_0F3A01 */
7022 {
7023 { Bad_Opcode },
7024 { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7025 },
7026
7027 /* VEX_LEN_0F3A06 */
7028 {
7029 { Bad_Opcode },
7030 { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7031 },
7032
7033 /* VEX_LEN_0F3A14 */
7034 {
7035 { "vpextrb", { Edqb, XM, Ib }, PREFIX_DATA },
7036 },
7037
7038 /* VEX_LEN_0F3A15 */
7039 {
7040 { "vpextrw", { Edqw, XM, Ib }, PREFIX_DATA },
7041 },
7042
7043 /* VEX_LEN_0F3A16 */
7044 {
7045 { "vpextrK", { Edq, XM, Ib }, PREFIX_DATA },
7046 },
7047
7048 /* VEX_LEN_0F3A17 */
7049 {
7050 { "vextractps", { Edqd, XM, Ib }, PREFIX_DATA },
7051 },
7052
7053 /* VEX_LEN_0F3A18 */
7054 {
7055 { Bad_Opcode },
7056 { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7057 },
7058
7059 /* VEX_LEN_0F3A19 */
7060 {
7061 { Bad_Opcode },
7062 { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7063 },
7064
7065 /* VEX_LEN_0F3A20 */
7066 {
7067 { "vpinsrb", { XM, Vex, Edqb, Ib }, PREFIX_DATA },
7068 },
7069
7070 /* VEX_LEN_0F3A21 */
7071 {
7072 { "vinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA },
7073 },
7074
7075 /* VEX_LEN_0F3A22 */
7076 {
7077 { "vpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
7078 },
7079
7080 /* VEX_LEN_0F3A30 */
7081 {
7082 { VEX_W_TABLE (VEX_W_0F3A30_L_0) },
7083 },
7084
7085 /* VEX_LEN_0F3A31 */
7086 {
7087 { VEX_W_TABLE (VEX_W_0F3A31_L_0) },
7088 },
7089
7090 /* VEX_LEN_0F3A32 */
7091 {
7092 { VEX_W_TABLE (VEX_W_0F3A32_L_0) },
7093 },
7094
7095 /* VEX_LEN_0F3A33 */
7096 {
7097 { VEX_W_TABLE (VEX_W_0F3A33_L_0) },
7098 },
7099
7100 /* VEX_LEN_0F3A38 */
7101 {
7102 { Bad_Opcode },
7103 { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7104 },
7105
7106 /* VEX_LEN_0F3A39 */
7107 {
7108 { Bad_Opcode },
7109 { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7110 },
7111
7112 /* VEX_LEN_0F3A41 */
7113 {
7114 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7115 },
7116
7117 /* VEX_LEN_0F3A46 */
7118 {
7119 { Bad_Opcode },
7120 { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7121 },
7122
7123 /* VEX_LEN_0F3A60 */
7124 {
7125 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7126 },
7127
7128 /* VEX_LEN_0F3A61 */
7129 {
7130 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7131 },
7132
7133 /* VEX_LEN_0F3A62 */
7134 {
7135 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7136 },
7137
7138 /* VEX_LEN_0F3A63 */
7139 {
7140 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7141 },
7142
7143 /* VEX_LEN_0F3ADF */
7144 {
7145 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7146 },
7147
7148 /* VEX_LEN_0F3AF0_P_3 */
7149 {
7150 { "rorxS", { Gdq, Edq, Ib }, 0 },
7151 },
7152
7153 /* VEX_LEN_0FXOP_08_85 */
7154 {
7155 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7156 },
7157
7158 /* VEX_LEN_0FXOP_08_86 */
7159 {
7160 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7161 },
7162
7163 /* VEX_LEN_0FXOP_08_87 */
7164 {
7165 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7166 },
7167
7168 /* VEX_LEN_0FXOP_08_8E */
7169 {
7170 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7171 },
7172
7173 /* VEX_LEN_0FXOP_08_8F */
7174 {
7175 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7176 },
7177
7178 /* VEX_LEN_0FXOP_08_95 */
7179 {
7180 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7181 },
7182
7183 /* VEX_LEN_0FXOP_08_96 */
7184 {
7185 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7186 },
7187
7188 /* VEX_LEN_0FXOP_08_97 */
7189 {
7190 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7191 },
7192
7193 /* VEX_LEN_0FXOP_08_9E */
7194 {
7195 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7196 },
7197
7198 /* VEX_LEN_0FXOP_08_9F */
7199 {
7200 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7201 },
7202
7203 /* VEX_LEN_0FXOP_08_A3 */
7204 {
7205 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
7206 },
7207
7208 /* VEX_LEN_0FXOP_08_A6 */
7209 {
7210 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7211 },
7212
7213 /* VEX_LEN_0FXOP_08_B6 */
7214 {
7215 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7216 },
7217
7218 /* VEX_LEN_0FXOP_08_C0 */
7219 {
7220 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7221 },
7222
7223 /* VEX_LEN_0FXOP_08_C1 */
7224 {
7225 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7226 },
7227
7228 /* VEX_LEN_0FXOP_08_C2 */
7229 {
7230 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7231 },
7232
7233 /* VEX_LEN_0FXOP_08_C3 */
7234 {
7235 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7236 },
7237
7238 /* VEX_LEN_0FXOP_08_CC */
7239 {
7240 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7241 },
7242
7243 /* VEX_LEN_0FXOP_08_CD */
7244 {
7245 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7246 },
7247
7248 /* VEX_LEN_0FXOP_08_CE */
7249 {
7250 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7251 },
7252
7253 /* VEX_LEN_0FXOP_08_CF */
7254 {
7255 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7256 },
7257
7258 /* VEX_LEN_0FXOP_08_EC */
7259 {
7260 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7261 },
7262
7263 /* VEX_LEN_0FXOP_08_ED */
7264 {
7265 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7266 },
7267
7268 /* VEX_LEN_0FXOP_08_EE */
7269 {
7270 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7271 },
7272
7273 /* VEX_LEN_0FXOP_08_EF */
7274 {
7275 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7276 },
7277
7278 /* VEX_LEN_0FXOP_09_01 */
7279 {
7280 { REG_TABLE (REG_0FXOP_09_01_L_0) },
7281 },
7282
7283 /* VEX_LEN_0FXOP_09_02 */
7284 {
7285 { REG_TABLE (REG_0FXOP_09_02_L_0) },
7286 },
7287
7288 /* VEX_LEN_0FXOP_09_12_M_1 */
7289 {
7290 { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
7291 },
7292
7293 /* VEX_LEN_0FXOP_09_82_W_0 */
7294 {
7295 { "vfrczss", { XM, EXd }, 0 },
7296 },
7297
7298 /* VEX_LEN_0FXOP_09_83_W_0 */
7299 {
7300 { "vfrczsd", { XM, EXq }, 0 },
7301 },
7302
7303 /* VEX_LEN_0FXOP_09_90 */
7304 {
7305 { "vprotb", { XM, EXx, VexW }, 0 },
7306 },
7307
7308 /* VEX_LEN_0FXOP_09_91 */
7309 {
7310 { "vprotw", { XM, EXx, VexW }, 0 },
7311 },
7312
7313 /* VEX_LEN_0FXOP_09_92 */
7314 {
7315 { "vprotd", { XM, EXx, VexW }, 0 },
7316 },
7317
7318 /* VEX_LEN_0FXOP_09_93 */
7319 {
7320 { "vprotq", { XM, EXx, VexW }, 0 },
7321 },
7322
7323 /* VEX_LEN_0FXOP_09_94 */
7324 {
7325 { "vpshlb", { XM, EXx, VexW }, 0 },
7326 },
7327
7328 /* VEX_LEN_0FXOP_09_95 */
7329 {
7330 { "vpshlw", { XM, EXx, VexW }, 0 },
7331 },
7332
7333 /* VEX_LEN_0FXOP_09_96 */
7334 {
7335 { "vpshld", { XM, EXx, VexW }, 0 },
7336 },
7337
7338 /* VEX_LEN_0FXOP_09_97 */
7339 {
7340 { "vpshlq", { XM, EXx, VexW }, 0 },
7341 },
7342
7343 /* VEX_LEN_0FXOP_09_98 */
7344 {
7345 { "vpshab", { XM, EXx, VexW }, 0 },
7346 },
7347
7348 /* VEX_LEN_0FXOP_09_99 */
7349 {
7350 { "vpshaw", { XM, EXx, VexW }, 0 },
7351 },
7352
7353 /* VEX_LEN_0FXOP_09_9A */
7354 {
7355 { "vpshad", { XM, EXx, VexW }, 0 },
7356 },
7357
7358 /* VEX_LEN_0FXOP_09_9B */
7359 {
7360 { "vpshaq", { XM, EXx, VexW }, 0 },
7361 },
7362
7363 /* VEX_LEN_0FXOP_09_C1 */
7364 {
7365 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7366 },
7367
7368 /* VEX_LEN_0FXOP_09_C2 */
7369 {
7370 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7371 },
7372
7373 /* VEX_LEN_0FXOP_09_C3 */
7374 {
7375 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7376 },
7377
7378 /* VEX_LEN_0FXOP_09_C6 */
7379 {
7380 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7381 },
7382
7383 /* VEX_LEN_0FXOP_09_C7 */
7384 {
7385 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7386 },
7387
7388 /* VEX_LEN_0FXOP_09_CB */
7389 {
7390 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7391 },
7392
7393 /* VEX_LEN_0FXOP_09_D1 */
7394 {
7395 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7396 },
7397
7398 /* VEX_LEN_0FXOP_09_D2 */
7399 {
7400 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7401 },
7402
7403 /* VEX_LEN_0FXOP_09_D3 */
7404 {
7405 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7406 },
7407
7408 /* VEX_LEN_0FXOP_09_D6 */
7409 {
7410 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7411 },
7412
7413 /* VEX_LEN_0FXOP_09_D7 */
7414 {
7415 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7416 },
7417
7418 /* VEX_LEN_0FXOP_09_DB */
7419 {
7420 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7421 },
7422
7423 /* VEX_LEN_0FXOP_09_E1 */
7424 {
7425 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7426 },
7427
7428 /* VEX_LEN_0FXOP_09_E2 */
7429 {
7430 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7431 },
7432
7433 /* VEX_LEN_0FXOP_09_E3 */
7434 {
7435 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7436 },
7437
7438 /* VEX_LEN_0FXOP_0A_12 */
7439 {
7440 { REG_TABLE (REG_0FXOP_0A_12_L_0) },
7441 },
7442 };
7443
7444 #include "i386-dis-evex-len.h"
7445
7446 static const struct dis386 vex_w_table[][2] = {
7447 {
7448 /* VEX_W_0F41_P_0_LEN_1 */
7449 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
7450 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
7451 },
7452 {
7453 /* VEX_W_0F41_P_2_LEN_1 */
7454 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
7455 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
7456 },
7457 {
7458 /* VEX_W_0F42_P_0_LEN_1 */
7459 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
7460 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
7461 },
7462 {
7463 /* VEX_W_0F42_P_2_LEN_1 */
7464 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
7465 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
7466 },
7467 {
7468 /* VEX_W_0F44_P_0_LEN_0 */
7469 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
7470 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
7471 },
7472 {
7473 /* VEX_W_0F44_P_2_LEN_0 */
7474 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
7475 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
7476 },
7477 {
7478 /* VEX_W_0F45_P_0_LEN_1 */
7479 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
7480 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
7481 },
7482 {
7483 /* VEX_W_0F45_P_2_LEN_1 */
7484 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
7485 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
7486 },
7487 {
7488 /* VEX_W_0F46_P_0_LEN_1 */
7489 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
7490 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
7491 },
7492 {
7493 /* VEX_W_0F46_P_2_LEN_1 */
7494 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
7495 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
7496 },
7497 {
7498 /* VEX_W_0F47_P_0_LEN_1 */
7499 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
7500 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
7501 },
7502 {
7503 /* VEX_W_0F47_P_2_LEN_1 */
7504 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
7505 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
7506 },
7507 {
7508 /* VEX_W_0F4A_P_0_LEN_1 */
7509 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
7510 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
7511 },
7512 {
7513 /* VEX_W_0F4A_P_2_LEN_1 */
7514 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
7515 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
7516 },
7517 {
7518 /* VEX_W_0F4B_P_0_LEN_1 */
7519 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
7520 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
7521 },
7522 {
7523 /* VEX_W_0F4B_P_2_LEN_1 */
7524 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
7525 },
7526 {
7527 /* VEX_W_0F90_P_0_LEN_0 */
7528 { "kmovw", { MaskG, MaskE }, 0 },
7529 { "kmovq", { MaskG, MaskE }, 0 },
7530 },
7531 {
7532 /* VEX_W_0F90_P_2_LEN_0 */
7533 { "kmovb", { MaskG, MaskBDE }, 0 },
7534 { "kmovd", { MaskG, MaskBDE }, 0 },
7535 },
7536 {
7537 /* VEX_W_0F91_P_0_LEN_0 */
7538 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
7539 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
7540 },
7541 {
7542 /* VEX_W_0F91_P_2_LEN_0 */
7543 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
7544 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
7545 },
7546 {
7547 /* VEX_W_0F92_P_0_LEN_0 */
7548 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
7549 },
7550 {
7551 /* VEX_W_0F92_P_2_LEN_0 */
7552 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
7553 },
7554 {
7555 /* VEX_W_0F93_P_0_LEN_0 */
7556 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
7557 },
7558 {
7559 /* VEX_W_0F93_P_2_LEN_0 */
7560 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
7561 },
7562 {
7563 /* VEX_W_0F98_P_0_LEN_0 */
7564 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
7565 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
7566 },
7567 {
7568 /* VEX_W_0F98_P_2_LEN_0 */
7569 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
7570 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
7571 },
7572 {
7573 /* VEX_W_0F99_P_0_LEN_0 */
7574 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
7575 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
7576 },
7577 {
7578 /* VEX_W_0F99_P_2_LEN_0 */
7579 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
7580 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
7581 },
7582 {
7583 /* VEX_W_0F380C */
7584 { "vpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7585 },
7586 {
7587 /* VEX_W_0F380D */
7588 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
7589 },
7590 {
7591 /* VEX_W_0F380E */
7592 { "vtestps", { XM, EXx }, PREFIX_DATA },
7593 },
7594 {
7595 /* VEX_W_0F380F */
7596 { "vtestpd", { XM, EXx }, PREFIX_DATA },
7597 },
7598 {
7599 /* VEX_W_0F3813 */
7600 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7601 },
7602 {
7603 /* VEX_W_0F3816_L_1 */
7604 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
7605 },
7606 {
7607 /* VEX_W_0F3818 */
7608 { "vbroadcastss", { XM, EXxmm_md }, PREFIX_DATA },
7609 },
7610 {
7611 /* VEX_W_0F3819_L_1 */
7612 { "vbroadcastsd", { XM, EXxmm_mq }, PREFIX_DATA },
7613 },
7614 {
7615 /* VEX_W_0F381A_M_0_L_1 */
7616 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7617 },
7618 {
7619 /* VEX_W_0F382C_M_0 */
7620 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
7621 },
7622 {
7623 /* VEX_W_0F382D_M_0 */
7624 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
7625 },
7626 {
7627 /* VEX_W_0F382E_M_0 */
7628 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
7629 },
7630 {
7631 /* VEX_W_0F382F_M_0 */
7632 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
7633 },
7634 {
7635 /* VEX_W_0F3836 */
7636 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
7637 },
7638 {
7639 /* VEX_W_0F3846 */
7640 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
7641 },
7642 {
7643 /* VEX_W_0F3849_X86_64_P_0 */
7644 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7645 },
7646 {
7647 /* VEX_W_0F3849_X86_64_P_2 */
7648 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7649 },
7650 {
7651 /* VEX_W_0F3849_X86_64_P_3 */
7652 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7653 },
7654 {
7655 /* VEX_W_0F384B_X86_64_P_1 */
7656 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7657 },
7658 {
7659 /* VEX_W_0F384B_X86_64_P_2 */
7660 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7661 },
7662 {
7663 /* VEX_W_0F384B_X86_64_P_3 */
7664 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7665 },
7666 {
7667 /* VEX_W_0F3858 */
7668 { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
7669 },
7670 {
7671 /* VEX_W_0F3859 */
7672 { "vpbroadcastq", { XM, EXxmm_mq }, PREFIX_DATA },
7673 },
7674 {
7675 /* VEX_W_0F385A_M_0_L_0 */
7676 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7677 },
7678 {
7679 /* VEX_W_0F385C_X86_64_P_1 */
7680 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7681 },
7682 {
7683 /* VEX_W_0F385E_X86_64_P_0 */
7684 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7685 },
7686 {
7687 /* VEX_W_0F385E_X86_64_P_1 */
7688 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7689 },
7690 {
7691 /* VEX_W_0F385E_X86_64_P_2 */
7692 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7693 },
7694 {
7695 /* VEX_W_0F385E_X86_64_P_3 */
7696 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7697 },
7698 {
7699 /* VEX_W_0F3878 */
7700 { "vpbroadcastb", { XM, EXxmm_mb }, PREFIX_DATA },
7701 },
7702 {
7703 /* VEX_W_0F3879 */
7704 { "vpbroadcastw", { XM, EXxmm_mw }, PREFIX_DATA },
7705 },
7706 {
7707 /* VEX_W_0F38CF */
7708 { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7709 },
7710 {
7711 /* VEX_W_0F3A00_L_1 */
7712 { Bad_Opcode },
7713 { "vpermq", { XM, EXx, Ib }, PREFIX_DATA },
7714 },
7715 {
7716 /* VEX_W_0F3A01_L_1 */
7717 { Bad_Opcode },
7718 { "vpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7719 },
7720 {
7721 /* VEX_W_0F3A02 */
7722 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7723 },
7724 {
7725 /* VEX_W_0F3A04 */
7726 { "vpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7727 },
7728 {
7729 /* VEX_W_0F3A05 */
7730 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
7731 },
7732 {
7733 /* VEX_W_0F3A06_L_1 */
7734 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7735 },
7736 {
7737 /* VEX_W_0F3A18_L_1 */
7738 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7739 },
7740 {
7741 /* VEX_W_0F3A19_L_1 */
7742 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
7743 },
7744 {
7745 /* VEX_W_0F3A1D */
7746 { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7747 },
7748 {
7749 /* VEX_W_0F3A30_L_0 */
7750 { MOD_TABLE (MOD_VEX_0F3A30_L_0_W_0) },
7751 { MOD_TABLE (MOD_VEX_0F3A30_L_0_W_1) },
7752 },
7753 {
7754 /* VEX_W_0F3A31_L_0 */
7755 { MOD_TABLE (MOD_VEX_0F3A31_L_0_W_0) },
7756 { MOD_TABLE (MOD_VEX_0F3A31_L_0_W_1) },
7757 },
7758 {
7759 /* VEX_W_0F3A32_L_0 */
7760 { MOD_TABLE (MOD_VEX_0F3A32_L_0_W_0) },
7761 { MOD_TABLE (MOD_VEX_0F3A32_L_0_W_1) },
7762 },
7763 {
7764 /* VEX_W_0F3A33_L_0 */
7765 { MOD_TABLE (MOD_VEX_0F3A33_L_0_W_0) },
7766 { MOD_TABLE (MOD_VEX_0F3A33_L_0_W_1) },
7767 },
7768 {
7769 /* VEX_W_0F3A38_L_1 */
7770 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7771 },
7772 {
7773 /* VEX_W_0F3A39_L_1 */
7774 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
7775 },
7776 {
7777 /* VEX_W_0F3A46_L_1 */
7778 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7779 },
7780 {
7781 /* VEX_W_0F3A4A */
7782 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7783 },
7784 {
7785 /* VEX_W_0F3A4B */
7786 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7787 },
7788 {
7789 /* VEX_W_0F3A4C */
7790 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7791 },
7792 {
7793 /* VEX_W_0F3ACE */
7794 { Bad_Opcode },
7795 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7796 },
7797 {
7798 /* VEX_W_0F3ACF */
7799 { Bad_Opcode },
7800 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7801 },
7802 /* VEX_W_0FXOP_08_85_L_0 */
7803 {
7804 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
7805 },
7806 /* VEX_W_0FXOP_08_86_L_0 */
7807 {
7808 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7809 },
7810 /* VEX_W_0FXOP_08_87_L_0 */
7811 {
7812 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7813 },
7814 /* VEX_W_0FXOP_08_8E_L_0 */
7815 {
7816 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7817 },
7818 /* VEX_W_0FXOP_08_8F_L_0 */
7819 {
7820 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7821 },
7822 /* VEX_W_0FXOP_08_95_L_0 */
7823 {
7824 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
7825 },
7826 /* VEX_W_0FXOP_08_96_L_0 */
7827 {
7828 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7829 },
7830 /* VEX_W_0FXOP_08_97_L_0 */
7831 {
7832 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7833 },
7834 /* VEX_W_0FXOP_08_9E_L_0 */
7835 {
7836 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7837 },
7838 /* VEX_W_0FXOP_08_9F_L_0 */
7839 {
7840 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7841 },
7842 /* VEX_W_0FXOP_08_A6_L_0 */
7843 {
7844 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7845 },
7846 /* VEX_W_0FXOP_08_B6_L_0 */
7847 {
7848 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7849 },
7850 /* VEX_W_0FXOP_08_C0_L_0 */
7851 {
7852 { "vprotb", { XM, EXx, Ib }, 0 },
7853 },
7854 /* VEX_W_0FXOP_08_C1_L_0 */
7855 {
7856 { "vprotw", { XM, EXx, Ib }, 0 },
7857 },
7858 /* VEX_W_0FXOP_08_C2_L_0 */
7859 {
7860 { "vprotd", { XM, EXx, Ib }, 0 },
7861 },
7862 /* VEX_W_0FXOP_08_C3_L_0 */
7863 {
7864 { "vprotq", { XM, EXx, Ib }, 0 },
7865 },
7866 /* VEX_W_0FXOP_08_CC_L_0 */
7867 {
7868 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
7869 },
7870 /* VEX_W_0FXOP_08_CD_L_0 */
7871 {
7872 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
7873 },
7874 /* VEX_W_0FXOP_08_CE_L_0 */
7875 {
7876 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
7877 },
7878 /* VEX_W_0FXOP_08_CF_L_0 */
7879 {
7880 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
7881 },
7882 /* VEX_W_0FXOP_08_EC_L_0 */
7883 {
7884 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
7885 },
7886 /* VEX_W_0FXOP_08_ED_L_0 */
7887 {
7888 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
7889 },
7890 /* VEX_W_0FXOP_08_EE_L_0 */
7891 {
7892 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
7893 },
7894 /* VEX_W_0FXOP_08_EF_L_0 */
7895 {
7896 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
7897 },
7898 /* VEX_W_0FXOP_09_80 */
7899 {
7900 { "vfrczps", { XM, EXx }, 0 },
7901 },
7902 /* VEX_W_0FXOP_09_81 */
7903 {
7904 { "vfrczpd", { XM, EXx }, 0 },
7905 },
7906 /* VEX_W_0FXOP_09_82 */
7907 {
7908 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7909 },
7910 /* VEX_W_0FXOP_09_83 */
7911 {
7912 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7913 },
7914 /* VEX_W_0FXOP_09_C1_L_0 */
7915 {
7916 { "vphaddbw", { XM, EXxmm }, 0 },
7917 },
7918 /* VEX_W_0FXOP_09_C2_L_0 */
7919 {
7920 { "vphaddbd", { XM, EXxmm }, 0 },
7921 },
7922 /* VEX_W_0FXOP_09_C3_L_0 */
7923 {
7924 { "vphaddbq", { XM, EXxmm }, 0 },
7925 },
7926 /* VEX_W_0FXOP_09_C6_L_0 */
7927 {
7928 { "vphaddwd", { XM, EXxmm }, 0 },
7929 },
7930 /* VEX_W_0FXOP_09_C7_L_0 */
7931 {
7932 { "vphaddwq", { XM, EXxmm }, 0 },
7933 },
7934 /* VEX_W_0FXOP_09_CB_L_0 */
7935 {
7936 { "vphadddq", { XM, EXxmm }, 0 },
7937 },
7938 /* VEX_W_0FXOP_09_D1_L_0 */
7939 {
7940 { "vphaddubw", { XM, EXxmm }, 0 },
7941 },
7942 /* VEX_W_0FXOP_09_D2_L_0 */
7943 {
7944 { "vphaddubd", { XM, EXxmm }, 0 },
7945 },
7946 /* VEX_W_0FXOP_09_D3_L_0 */
7947 {
7948 { "vphaddubq", { XM, EXxmm }, 0 },
7949 },
7950 /* VEX_W_0FXOP_09_D6_L_0 */
7951 {
7952 { "vphadduwd", { XM, EXxmm }, 0 },
7953 },
7954 /* VEX_W_0FXOP_09_D7_L_0 */
7955 {
7956 { "vphadduwq", { XM, EXxmm }, 0 },
7957 },
7958 /* VEX_W_0FXOP_09_DB_L_0 */
7959 {
7960 { "vphaddudq", { XM, EXxmm }, 0 },
7961 },
7962 /* VEX_W_0FXOP_09_E1_L_0 */
7963 {
7964 { "vphsubbw", { XM, EXxmm }, 0 },
7965 },
7966 /* VEX_W_0FXOP_09_E2_L_0 */
7967 {
7968 { "vphsubwd", { XM, EXxmm }, 0 },
7969 },
7970 /* VEX_W_0FXOP_09_E3_L_0 */
7971 {
7972 { "vphsubdq", { XM, EXxmm }, 0 },
7973 },
7974
7975 #include "i386-dis-evex-w.h"
7976 };
7977
7978 static const struct dis386 mod_table[][2] = {
7979 {
7980 /* MOD_8D */
7981 { "leaS", { Gv, M }, 0 },
7982 },
7983 {
7984 /* MOD_C6_REG_7 */
7985 { Bad_Opcode },
7986 { RM_TABLE (RM_C6_REG_7) },
7987 },
7988 {
7989 /* MOD_C7_REG_7 */
7990 { Bad_Opcode },
7991 { RM_TABLE (RM_C7_REG_7) },
7992 },
7993 {
7994 /* MOD_FF_REG_3 */
7995 { "{l|}call^", { indirEp }, 0 },
7996 },
7997 {
7998 /* MOD_FF_REG_5 */
7999 { "{l|}jmp^", { indirEp }, 0 },
8000 },
8001 {
8002 /* MOD_0F01_REG_0 */
8003 { X86_64_TABLE (X86_64_0F01_REG_0) },
8004 { RM_TABLE (RM_0F01_REG_0) },
8005 },
8006 {
8007 /* MOD_0F01_REG_1 */
8008 { X86_64_TABLE (X86_64_0F01_REG_1) },
8009 { RM_TABLE (RM_0F01_REG_1) },
8010 },
8011 {
8012 /* MOD_0F01_REG_2 */
8013 { X86_64_TABLE (X86_64_0F01_REG_2) },
8014 { RM_TABLE (RM_0F01_REG_2) },
8015 },
8016 {
8017 /* MOD_0F01_REG_3 */
8018 { X86_64_TABLE (X86_64_0F01_REG_3) },
8019 { RM_TABLE (RM_0F01_REG_3) },
8020 },
8021 {
8022 /* MOD_0F01_REG_5 */
8023 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8024 { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8025 },
8026 {
8027 /* MOD_0F01_REG_7 */
8028 { "invlpg", { Mb }, 0 },
8029 { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8030 },
8031 {
8032 /* MOD_0F12_PREFIX_0 */
8033 { "movlpX", { XM, EXq }, 0 },
8034 { "movhlps", { XM, EXq }, 0 },
8035 },
8036 {
8037 /* MOD_0F12_PREFIX_2 */
8038 { "movlpX", { XM, EXq }, 0 },
8039 },
8040 {
8041 /* MOD_0F13 */
8042 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
8043 },
8044 {
8045 /* MOD_0F16_PREFIX_0 */
8046 { "movhpX", { XM, EXq }, 0 },
8047 { "movlhps", { XM, EXq }, 0 },
8048 },
8049 {
8050 /* MOD_0F16_PREFIX_2 */
8051 { "movhpX", { XM, EXq }, 0 },
8052 },
8053 {
8054 /* MOD_0F17 */
8055 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
8056 },
8057 {
8058 /* MOD_0F18_REG_0 */
8059 { "prefetchnta", { Mb }, 0 },
8060 },
8061 {
8062 /* MOD_0F18_REG_1 */
8063 { "prefetcht0", { Mb }, 0 },
8064 },
8065 {
8066 /* MOD_0F18_REG_2 */
8067 { "prefetcht1", { Mb }, 0 },
8068 },
8069 {
8070 /* MOD_0F18_REG_3 */
8071 { "prefetcht2", { Mb }, 0 },
8072 },
8073 {
8074 /* MOD_0F18_REG_4 */
8075 { "nop/reserved", { Mb }, 0 },
8076 },
8077 {
8078 /* MOD_0F18_REG_5 */
8079 { "nop/reserved", { Mb }, 0 },
8080 },
8081 {
8082 /* MOD_0F18_REG_6 */
8083 { "nop/reserved", { Mb }, 0 },
8084 },
8085 {
8086 /* MOD_0F18_REG_7 */
8087 { "nop/reserved", { Mb }, 0 },
8088 },
8089 {
8090 /* MOD_0F1A_PREFIX_0 */
8091 { "bndldx", { Gbnd, Mv_bnd }, 0 },
8092 { "nopQ", { Ev }, 0 },
8093 },
8094 {
8095 /* MOD_0F1B_PREFIX_0 */
8096 { "bndstx", { Mv_bnd, Gbnd }, 0 },
8097 { "nopQ", { Ev }, 0 },
8098 },
8099 {
8100 /* MOD_0F1B_PREFIX_1 */
8101 { "bndmk", { Gbnd, Mv_bnd }, 0 },
8102 { "nopQ", { Ev }, 0 },
8103 },
8104 {
8105 /* MOD_0F1C_PREFIX_0 */
8106 { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8107 { "nopQ", { Ev }, 0 },
8108 },
8109 {
8110 /* MOD_0F1E_PREFIX_1 */
8111 { "nopQ", { Ev }, 0 },
8112 { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8113 },
8114 {
8115 /* MOD_0F24 */
8116 { Bad_Opcode },
8117 { "movL", { Rd, Td }, 0 },
8118 },
8119 {
8120 /* MOD_0F26 */
8121 { Bad_Opcode },
8122 { "movL", { Td, Rd }, 0 },
8123 },
8124 {
8125 /* MOD_0F2B_PREFIX_0 */
8126 {"movntps", { Mx, XM }, PREFIX_OPCODE },
8127 },
8128 {
8129 /* MOD_0F2B_PREFIX_1 */
8130 {"movntss", { Md, XM }, PREFIX_OPCODE },
8131 },
8132 {
8133 /* MOD_0F2B_PREFIX_2 */
8134 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
8135 },
8136 {
8137 /* MOD_0F2B_PREFIX_3 */
8138 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
8139 },
8140 {
8141 /* MOD_0F50 */
8142 { Bad_Opcode },
8143 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
8144 },
8145 {
8146 /* MOD_0F71_REG_2 */
8147 { Bad_Opcode },
8148 { "psrlw", { MS, Ib }, PREFIX_OPCODE },
8149 },
8150 {
8151 /* MOD_0F71_REG_4 */
8152 { Bad_Opcode },
8153 { "psraw", { MS, Ib }, PREFIX_OPCODE },
8154 },
8155 {
8156 /* MOD_0F71_REG_6 */
8157 { Bad_Opcode },
8158 { "psllw", { MS, Ib }, PREFIX_OPCODE },
8159 },
8160 {
8161 /* MOD_0F72_REG_2 */
8162 { Bad_Opcode },
8163 { "psrld", { MS, Ib }, PREFIX_OPCODE },
8164 },
8165 {
8166 /* MOD_0F72_REG_4 */
8167 { Bad_Opcode },
8168 { "psrad", { MS, Ib }, PREFIX_OPCODE },
8169 },
8170 {
8171 /* MOD_0F72_REG_6 */
8172 { Bad_Opcode },
8173 { "pslld", { MS, Ib }, PREFIX_OPCODE },
8174 },
8175 {
8176 /* MOD_0F73_REG_2 */
8177 { Bad_Opcode },
8178 { "psrlq", { MS, Ib }, PREFIX_OPCODE },
8179 },
8180 {
8181 /* MOD_0F73_REG_3 */
8182 { Bad_Opcode },
8183 { "psrldq", { XS, Ib }, PREFIX_DATA },
8184 },
8185 {
8186 /* MOD_0F73_REG_6 */
8187 { Bad_Opcode },
8188 { "psllq", { MS, Ib }, PREFIX_OPCODE },
8189 },
8190 {
8191 /* MOD_0F73_REG_7 */
8192 { Bad_Opcode },
8193 { "pslldq", { XS, Ib }, PREFIX_DATA },
8194 },
8195 {
8196 /* MOD_0FAE_REG_0 */
8197 { "fxsave", { FXSAVE }, 0 },
8198 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8199 },
8200 {
8201 /* MOD_0FAE_REG_1 */
8202 { "fxrstor", { FXSAVE }, 0 },
8203 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8204 },
8205 {
8206 /* MOD_0FAE_REG_2 */
8207 { "ldmxcsr", { Md }, 0 },
8208 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8209 },
8210 {
8211 /* MOD_0FAE_REG_3 */
8212 { "stmxcsr", { Md }, 0 },
8213 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8214 },
8215 {
8216 /* MOD_0FAE_REG_4 */
8217 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8218 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8219 },
8220 {
8221 /* MOD_0FAE_REG_5 */
8222 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
8223 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8224 },
8225 {
8226 /* MOD_0FAE_REG_6 */
8227 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8228 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8229 },
8230 {
8231 /* MOD_0FAE_REG_7 */
8232 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8233 { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8234 },
8235 {
8236 /* MOD_0FB2 */
8237 { "lssS", { Gv, Mp }, 0 },
8238 },
8239 {
8240 /* MOD_0FB4 */
8241 { "lfsS", { Gv, Mp }, 0 },
8242 },
8243 {
8244 /* MOD_0FB5 */
8245 { "lgsS", { Gv, Mp }, 0 },
8246 },
8247 {
8248 /* MOD_0FC3 */
8249 { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
8250 },
8251 {
8252 /* MOD_0FC7_REG_3 */
8253 { "xrstors", { FXSAVE }, 0 },
8254 },
8255 {
8256 /* MOD_0FC7_REG_4 */
8257 { "xsavec", { FXSAVE }, 0 },
8258 },
8259 {
8260 /* MOD_0FC7_REG_5 */
8261 { "xsaves", { FXSAVE }, 0 },
8262 },
8263 {
8264 /* MOD_0FC7_REG_6 */
8265 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8266 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8267 },
8268 {
8269 /* MOD_0FC7_REG_7 */
8270 { "vmptrst", { Mq }, 0 },
8271 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8272 },
8273 {
8274 /* MOD_0FD7 */
8275 { Bad_Opcode },
8276 { "pmovmskb", { Gdq, MS }, 0 },
8277 },
8278 {
8279 /* MOD_0FE7_PREFIX_2 */
8280 { "movntdq", { Mx, XM }, 0 },
8281 },
8282 {
8283 /* MOD_0FF0_PREFIX_3 */
8284 { "lddqu", { XM, M }, 0 },
8285 },
8286 {
8287 /* MOD_0F382A */
8288 { "movntdqa", { XM, Mx }, PREFIX_DATA },
8289 },
8290 {
8291 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8292 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8293 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8294 },
8295 {
8296 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8297 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8298 },
8299 {
8300 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8301 { Bad_Opcode },
8302 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8303 },
8304 {
8305 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8306 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8307 },
8308 {
8309 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8310 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8311 },
8312 {
8313 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8314 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8315 },
8316 {
8317 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8318 { Bad_Opcode },
8319 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8320 },
8321 {
8322 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8323 { Bad_Opcode },
8324 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8325 },
8326 {
8327 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8328 { Bad_Opcode },
8329 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8330 },
8331 {
8332 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8333 { Bad_Opcode },
8334 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8335 },
8336 {
8337 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8338 { Bad_Opcode },
8339 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8340 },
8341 {
8342 /* MOD_0F38F5 */
8343 { "wrussK", { M, Gdq }, PREFIX_DATA },
8344 },
8345 {
8346 /* MOD_0F38F6_PREFIX_0 */
8347 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
8348 },
8349 {
8350 /* MOD_0F38F8_PREFIX_1 */
8351 { "enqcmds", { Gva, M }, PREFIX_OPCODE },
8352 },
8353 {
8354 /* MOD_0F38F8_PREFIX_2 */
8355 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
8356 },
8357 {
8358 /* MOD_0F38F8_PREFIX_3 */
8359 { "enqcmd", { Gva, M }, PREFIX_OPCODE },
8360 },
8361 {
8362 /* MOD_0F38F9_PREFIX_0 */
8363 { "movdiri", { Ev, Gv }, PREFIX_OPCODE },
8364 },
8365 {
8366 /* MOD_62_32BIT */
8367 { "bound{S|}", { Gv, Ma }, 0 },
8368 { EVEX_TABLE (EVEX_0F) },
8369 },
8370 {
8371 /* MOD_C4_32BIT */
8372 { "lesS", { Gv, Mp }, 0 },
8373 { VEX_C4_TABLE (VEX_0F) },
8374 },
8375 {
8376 /* MOD_C5_32BIT */
8377 { "ldsS", { Gv, Mp }, 0 },
8378 { VEX_C5_TABLE (VEX_0F) },
8379 },
8380 {
8381 /* MOD_VEX_0F12_PREFIX_0 */
8382 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8383 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8384 },
8385 {
8386 /* MOD_VEX_0F12_PREFIX_2 */
8387 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8388 },
8389 {
8390 /* MOD_VEX_0F13 */
8391 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8392 },
8393 {
8394 /* MOD_VEX_0F16_PREFIX_0 */
8395 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8396 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8397 },
8398 {
8399 /* MOD_VEX_0F16_PREFIX_2 */
8400 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8401 },
8402 {
8403 /* MOD_VEX_0F17 */
8404 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8405 },
8406 {
8407 /* MOD_VEX_0F2B */
8408 { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
8409 },
8410 {
8411 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
8412 { Bad_Opcode },
8413 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
8414 },
8415 {
8416 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
8417 { Bad_Opcode },
8418 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
8419 },
8420 {
8421 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
8422 { Bad_Opcode },
8423 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
8424 },
8425 {
8426 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
8427 { Bad_Opcode },
8428 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
8429 },
8430 {
8431 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
8432 { Bad_Opcode },
8433 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
8434 },
8435 {
8436 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
8437 { Bad_Opcode },
8438 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
8439 },
8440 {
8441 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
8442 { Bad_Opcode },
8443 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
8444 },
8445 {
8446 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
8447 { Bad_Opcode },
8448 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
8449 },
8450 {
8451 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
8452 { Bad_Opcode },
8453 { "knotw", { MaskG, MaskR }, 0 },
8454 },
8455 {
8456 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
8457 { Bad_Opcode },
8458 { "knotq", { MaskG, MaskR }, 0 },
8459 },
8460 {
8461 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
8462 { Bad_Opcode },
8463 { "knotb", { MaskG, MaskR }, 0 },
8464 },
8465 {
8466 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
8467 { Bad_Opcode },
8468 { "knotd", { MaskG, MaskR }, 0 },
8469 },
8470 {
8471 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
8472 { Bad_Opcode },
8473 { "korw", { MaskG, MaskVex, MaskR }, 0 },
8474 },
8475 {
8476 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
8477 { Bad_Opcode },
8478 { "korq", { MaskG, MaskVex, MaskR }, 0 },
8479 },
8480 {
8481 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
8482 { Bad_Opcode },
8483 { "korb", { MaskG, MaskVex, MaskR }, 0 },
8484 },
8485 {
8486 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
8487 { Bad_Opcode },
8488 { "kord", { MaskG, MaskVex, MaskR }, 0 },
8489 },
8490 {
8491 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
8492 { Bad_Opcode },
8493 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
8494 },
8495 {
8496 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
8497 { Bad_Opcode },
8498 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
8499 },
8500 {
8501 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
8502 { Bad_Opcode },
8503 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
8504 },
8505 {
8506 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
8507 { Bad_Opcode },
8508 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
8509 },
8510 {
8511 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
8512 { Bad_Opcode },
8513 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
8514 },
8515 {
8516 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
8517 { Bad_Opcode },
8518 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
8519 },
8520 {
8521 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
8522 { Bad_Opcode },
8523 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
8524 },
8525 {
8526 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
8527 { Bad_Opcode },
8528 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
8529 },
8530 {
8531 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
8532 { Bad_Opcode },
8533 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
8534 },
8535 {
8536 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
8537 { Bad_Opcode },
8538 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
8539 },
8540 {
8541 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
8542 { Bad_Opcode },
8543 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
8544 },
8545 {
8546 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
8547 { Bad_Opcode },
8548 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
8549 },
8550 {
8551 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
8552 { Bad_Opcode },
8553 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
8554 },
8555 {
8556 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
8557 { Bad_Opcode },
8558 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
8559 },
8560 {
8561 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
8562 { Bad_Opcode },
8563 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
8564 },
8565 {
8566 /* MOD_VEX_0F50 */
8567 { Bad_Opcode },
8568 { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
8569 },
8570 {
8571 /* MOD_VEX_0F71_REG_2 */
8572 { Bad_Opcode },
8573 { "vpsrlw", { Vex, XS, Ib }, PREFIX_DATA },
8574 },
8575 {
8576 /* MOD_VEX_0F71_REG_4 */
8577 { Bad_Opcode },
8578 { "vpsraw", { Vex, XS, Ib }, PREFIX_DATA },
8579 },
8580 {
8581 /* MOD_VEX_0F71_REG_6 */
8582 { Bad_Opcode },
8583 { "vpsllw", { Vex, XS, Ib }, PREFIX_DATA },
8584 },
8585 {
8586 /* MOD_VEX_0F72_REG_2 */
8587 { Bad_Opcode },
8588 { "vpsrld", { Vex, XS, Ib }, PREFIX_DATA },
8589 },
8590 {
8591 /* MOD_VEX_0F72_REG_4 */
8592 { Bad_Opcode },
8593 { "vpsrad", { Vex, XS, Ib }, PREFIX_DATA },
8594 },
8595 {
8596 /* MOD_VEX_0F72_REG_6 */
8597 { Bad_Opcode },
8598 { "vpslld", { Vex, XS, Ib }, PREFIX_DATA },
8599 },
8600 {
8601 /* MOD_VEX_0F73_REG_2 */
8602 { Bad_Opcode },
8603 { "vpsrlq", { Vex, XS, Ib }, PREFIX_DATA },
8604 },
8605 {
8606 /* MOD_VEX_0F73_REG_3 */
8607 { Bad_Opcode },
8608 { "vpsrldq", { Vex, XS, Ib }, PREFIX_DATA },
8609 },
8610 {
8611 /* MOD_VEX_0F73_REG_6 */
8612 { Bad_Opcode },
8613 { "vpsllq", { Vex, XS, Ib }, PREFIX_DATA },
8614 },
8615 {
8616 /* MOD_VEX_0F73_REG_7 */
8617 { Bad_Opcode },
8618 { "vpslldq", { Vex, XS, Ib }, PREFIX_DATA },
8619 },
8620 {
8621 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8622 { "kmovw", { Ew, MaskG }, 0 },
8623 { Bad_Opcode },
8624 },
8625 {
8626 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8627 { "kmovq", { Eq, MaskG }, 0 },
8628 { Bad_Opcode },
8629 },
8630 {
8631 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8632 { "kmovb", { Eb, MaskG }, 0 },
8633 { Bad_Opcode },
8634 },
8635 {
8636 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8637 { "kmovd", { Ed, MaskG }, 0 },
8638 { Bad_Opcode },
8639 },
8640 {
8641 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
8642 { Bad_Opcode },
8643 { "kmovw", { MaskG, Rdq }, 0 },
8644 },
8645 {
8646 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
8647 { Bad_Opcode },
8648 { "kmovb", { MaskG, Rdq }, 0 },
8649 },
8650 {
8651 /* MOD_VEX_0F92_P_3_LEN_0 */
8652 { Bad_Opcode },
8653 { "kmovK", { MaskG, Rdq }, 0 },
8654 },
8655 {
8656 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
8657 { Bad_Opcode },
8658 { "kmovw", { Gdq, MaskR }, 0 },
8659 },
8660 {
8661 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
8662 { Bad_Opcode },
8663 { "kmovb", { Gdq, MaskR }, 0 },
8664 },
8665 {
8666 /* MOD_VEX_0F93_P_3_LEN_0 */
8667 { Bad_Opcode },
8668 { "kmovK", { Gdq, MaskR }, 0 },
8669 },
8670 {
8671 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
8672 { Bad_Opcode },
8673 { "kortestw", { MaskG, MaskR }, 0 },
8674 },
8675 {
8676 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
8677 { Bad_Opcode },
8678 { "kortestq", { MaskG, MaskR }, 0 },
8679 },
8680 {
8681 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
8682 { Bad_Opcode },
8683 { "kortestb", { MaskG, MaskR }, 0 },
8684 },
8685 {
8686 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
8687 { Bad_Opcode },
8688 { "kortestd", { MaskG, MaskR }, 0 },
8689 },
8690 {
8691 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
8692 { Bad_Opcode },
8693 { "ktestw", { MaskG, MaskR }, 0 },
8694 },
8695 {
8696 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
8697 { Bad_Opcode },
8698 { "ktestq", { MaskG, MaskR }, 0 },
8699 },
8700 {
8701 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
8702 { Bad_Opcode },
8703 { "ktestb", { MaskG, MaskR }, 0 },
8704 },
8705 {
8706 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
8707 { Bad_Opcode },
8708 { "ktestd", { MaskG, MaskR }, 0 },
8709 },
8710 {
8711 /* MOD_VEX_0FAE_REG_2 */
8712 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8713 },
8714 {
8715 /* MOD_VEX_0FAE_REG_3 */
8716 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8717 },
8718 {
8719 /* MOD_VEX_0FD7 */
8720 { Bad_Opcode },
8721 { "vpmovmskb", { Gdq, XS }, PREFIX_DATA },
8722 },
8723 {
8724 /* MOD_VEX_0FE7 */
8725 { "vmovntdq", { Mx, XM }, PREFIX_DATA },
8726 },
8727 {
8728 /* MOD_VEX_0FF0_PREFIX_3 */
8729 { "vlddqu", { XM, M }, 0 },
8730 },
8731 {
8732 /* MOD_VEX_0F381A */
8733 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8734 },
8735 {
8736 /* MOD_VEX_0F382A */
8737 { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
8738 },
8739 {
8740 /* MOD_VEX_0F382C */
8741 { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8742 },
8743 {
8744 /* MOD_VEX_0F382D */
8745 { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8746 },
8747 {
8748 /* MOD_VEX_0F382E */
8749 { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8750 },
8751 {
8752 /* MOD_VEX_0F382F */
8753 { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8754 },
8755 {
8756 /* MOD_VEX_0F385A */
8757 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8758 },
8759 {
8760 /* MOD_VEX_0F388C */
8761 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
8762 },
8763 {
8764 /* MOD_VEX_0F388E */
8765 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
8766 },
8767 {
8768 /* MOD_VEX_0F3A30_L_0_W_0 */
8769 { Bad_Opcode },
8770 { "kshiftrb", { MaskG, MaskR, Ib }, PREFIX_DATA },
8771 },
8772 {
8773 /* MOD_VEX_0F3A30_L_0_W_1 */
8774 { Bad_Opcode },
8775 { "kshiftrw", { MaskG, MaskR, Ib }, PREFIX_DATA },
8776 },
8777 {
8778 /* MOD_VEX_0F3A31_L_0_W_0 */
8779 { Bad_Opcode },
8780 { "kshiftrd", { MaskG, MaskR, Ib }, PREFIX_DATA },
8781 },
8782 {
8783 /* MOD_VEX_0F3A31_L_0_W_1 */
8784 { Bad_Opcode },
8785 { "kshiftrq", { MaskG, MaskR, Ib }, PREFIX_DATA },
8786 },
8787 {
8788 /* MOD_VEX_0F3A32_L_0_W_0 */
8789 { Bad_Opcode },
8790 { "kshiftlb", { MaskG, MaskR, Ib }, PREFIX_DATA },
8791 },
8792 {
8793 /* MOD_VEX_0F3A32_L_0_W_1 */
8794 { Bad_Opcode },
8795 { "kshiftlw", { MaskG, MaskR, Ib }, PREFIX_DATA },
8796 },
8797 {
8798 /* MOD_VEX_0F3A33_L_0_W_0 */
8799 { Bad_Opcode },
8800 { "kshiftld", { MaskG, MaskR, Ib }, PREFIX_DATA },
8801 },
8802 {
8803 /* MOD_VEX_0F3A33_L_0_W_1 */
8804 { Bad_Opcode },
8805 { "kshiftlq", { MaskG, MaskR, Ib }, PREFIX_DATA },
8806 },
8807 {
8808 /* MOD_VEX_0FXOP_09_12 */
8809 { Bad_Opcode },
8810 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8811 },
8812
8813 #include "i386-dis-evex-mod.h"
8814 };
8815
8816 static const struct dis386 rm_table[][8] = {
8817 {
8818 /* RM_C6_REG_7 */
8819 { "xabort", { Skip_MODRM, Ib }, 0 },
8820 },
8821 {
8822 /* RM_C7_REG_7 */
8823 { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
8824 },
8825 {
8826 /* RM_0F01_REG_0 */
8827 { "enclv", { Skip_MODRM }, 0 },
8828 { "vmcall", { Skip_MODRM }, 0 },
8829 { "vmlaunch", { Skip_MODRM }, 0 },
8830 { "vmresume", { Skip_MODRM }, 0 },
8831 { "vmxoff", { Skip_MODRM }, 0 },
8832 { "pconfig", { Skip_MODRM }, 0 },
8833 },
8834 {
8835 /* RM_0F01_REG_1 */
8836 { "monitor", { { OP_Monitor, 0 } }, 0 },
8837 { "mwait", { { OP_Mwait, 0 } }, 0 },
8838 { "clac", { Skip_MODRM }, 0 },
8839 { "stac", { Skip_MODRM }, 0 },
8840 { Bad_Opcode },
8841 { Bad_Opcode },
8842 { Bad_Opcode },
8843 { "encls", { Skip_MODRM }, 0 },
8844 },
8845 {
8846 /* RM_0F01_REG_2 */
8847 { "xgetbv", { Skip_MODRM }, 0 },
8848 { "xsetbv", { Skip_MODRM }, 0 },
8849 { Bad_Opcode },
8850 { Bad_Opcode },
8851 { "vmfunc", { Skip_MODRM }, 0 },
8852 { "xend", { Skip_MODRM }, 0 },
8853 { "xtest", { Skip_MODRM }, 0 },
8854 { "enclu", { Skip_MODRM }, 0 },
8855 },
8856 {
8857 /* RM_0F01_REG_3 */
8858 { "vmrun", { Skip_MODRM }, 0 },
8859 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8860 { "vmload", { Skip_MODRM }, 0 },
8861 { "vmsave", { Skip_MODRM }, 0 },
8862 { "stgi", { Skip_MODRM }, 0 },
8863 { "clgi", { Skip_MODRM }, 0 },
8864 { "skinit", { Skip_MODRM }, 0 },
8865 { "invlpga", { Skip_MODRM }, 0 },
8866 },
8867 {
8868 /* RM_0F01_REG_5_MOD_3 */
8869 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8870 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8871 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8872 { Bad_Opcode },
8873 { Bad_Opcode },
8874 { Bad_Opcode },
8875 { "rdpkru", { Skip_MODRM }, 0 },
8876 { "wrpkru", { Skip_MODRM }, 0 },
8877 },
8878 {
8879 /* RM_0F01_REG_7_MOD_3 */
8880 { "swapgs", { Skip_MODRM }, 0 },
8881 { "rdtscp", { Skip_MODRM }, 0 },
8882 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8883 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
8884 { "clzero", { Skip_MODRM }, 0 },
8885 { "rdpru", { Skip_MODRM }, 0 },
8886 },
8887 {
8888 /* RM_0F1E_P_1_MOD_3_REG_7 */
8889 { "nopQ", { Ev }, 0 },
8890 { "nopQ", { Ev }, 0 },
8891 { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
8892 { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
8893 { "nopQ", { Ev }, 0 },
8894 { "nopQ", { Ev }, 0 },
8895 { "nopQ", { Ev }, 0 },
8896 { "nopQ", { Ev }, 0 },
8897 },
8898 {
8899 /* RM_0FAE_REG_6_MOD_3 */
8900 { "mfence", { Skip_MODRM }, 0 },
8901 },
8902 {
8903 /* RM_0FAE_REG_7_MOD_3 */
8904 { "sfence", { Skip_MODRM }, 0 },
8905
8906 },
8907 {
8908 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8909 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8910 },
8911 };
8912
8913 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8914
8915 /* We use the high bit to indicate different name for the same
8916 prefix. */
8917 #define REP_PREFIX (0xf3 | 0x100)
8918 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8919 #define XRELEASE_PREFIX (0xf3 | 0x400)
8920 #define BND_PREFIX (0xf2 | 0x400)
8921 #define NOTRACK_PREFIX (0x3e | 0x100)
8922
8923 /* Remember if the current op is a jump instruction. */
8924 static bfd_boolean op_is_jump = FALSE;
8925
8926 static int
8927 ckprefix (void)
8928 {
8929 int newrex, i, length;
8930 rex = 0;
8931 prefixes = 0;
8932 used_prefixes = 0;
8933 rex_used = 0;
8934 last_lock_prefix = -1;
8935 last_repz_prefix = -1;
8936 last_repnz_prefix = -1;
8937 last_data_prefix = -1;
8938 last_addr_prefix = -1;
8939 last_rex_prefix = -1;
8940 last_seg_prefix = -1;
8941 fwait_prefix = -1;
8942 active_seg_prefix = 0;
8943 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
8944 all_prefixes[i] = 0;
8945 i = 0;
8946 length = 0;
8947 /* The maximum instruction length is 15bytes. */
8948 while (length < MAX_CODE_LENGTH - 1)
8949 {
8950 FETCH_DATA (the_info, codep + 1);
8951 newrex = 0;
8952 switch (*codep)
8953 {
8954 /* REX prefixes family. */
8955 case 0x40:
8956 case 0x41:
8957 case 0x42:
8958 case 0x43:
8959 case 0x44:
8960 case 0x45:
8961 case 0x46:
8962 case 0x47:
8963 case 0x48:
8964 case 0x49:
8965 case 0x4a:
8966 case 0x4b:
8967 case 0x4c:
8968 case 0x4d:
8969 case 0x4e:
8970 case 0x4f:
8971 if (address_mode == mode_64bit)
8972 newrex = *codep;
8973 else
8974 return 1;
8975 last_rex_prefix = i;
8976 break;
8977 case 0xf3:
8978 prefixes |= PREFIX_REPZ;
8979 last_repz_prefix = i;
8980 break;
8981 case 0xf2:
8982 prefixes |= PREFIX_REPNZ;
8983 last_repnz_prefix = i;
8984 break;
8985 case 0xf0:
8986 prefixes |= PREFIX_LOCK;
8987 last_lock_prefix = i;
8988 break;
8989 case 0x2e:
8990 prefixes |= PREFIX_CS;
8991 last_seg_prefix = i;
8992 active_seg_prefix = PREFIX_CS;
8993 break;
8994 case 0x36:
8995 prefixes |= PREFIX_SS;
8996 last_seg_prefix = i;
8997 active_seg_prefix = PREFIX_SS;
8998 break;
8999 case 0x3e:
9000 prefixes |= PREFIX_DS;
9001 last_seg_prefix = i;
9002 active_seg_prefix = PREFIX_DS;
9003 break;
9004 case 0x26:
9005 prefixes |= PREFIX_ES;
9006 last_seg_prefix = i;
9007 active_seg_prefix = PREFIX_ES;
9008 break;
9009 case 0x64:
9010 prefixes |= PREFIX_FS;
9011 last_seg_prefix = i;
9012 active_seg_prefix = PREFIX_FS;
9013 break;
9014 case 0x65:
9015 prefixes |= PREFIX_GS;
9016 last_seg_prefix = i;
9017 active_seg_prefix = PREFIX_GS;
9018 break;
9019 case 0x66:
9020 prefixes |= PREFIX_DATA;
9021 last_data_prefix = i;
9022 break;
9023 case 0x67:
9024 prefixes |= PREFIX_ADDR;
9025 last_addr_prefix = i;
9026 break;
9027 case FWAIT_OPCODE:
9028 /* fwait is really an instruction. If there are prefixes
9029 before the fwait, they belong to the fwait, *not* to the
9030 following instruction. */
9031 fwait_prefix = i;
9032 if (prefixes || rex)
9033 {
9034 prefixes |= PREFIX_FWAIT;
9035 codep++;
9036 /* This ensures that the previous REX prefixes are noticed
9037 as unused prefixes, as in the return case below. */
9038 rex_used = rex;
9039 return 1;
9040 }
9041 prefixes = PREFIX_FWAIT;
9042 break;
9043 default:
9044 return 1;
9045 }
9046 /* Rex is ignored when followed by another prefix. */
9047 if (rex)
9048 {
9049 rex_used = rex;
9050 return 1;
9051 }
9052 if (*codep != FWAIT_OPCODE)
9053 all_prefixes[i++] = *codep;
9054 rex = newrex;
9055 codep++;
9056 length++;
9057 }
9058 return 0;
9059 }
9060
9061 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9062 prefix byte. */
9063
9064 static const char *
9065 prefix_name (int pref, int sizeflag)
9066 {
9067 static const char *rexes [16] =
9068 {
9069 "rex", /* 0x40 */
9070 "rex.B", /* 0x41 */
9071 "rex.X", /* 0x42 */
9072 "rex.XB", /* 0x43 */
9073 "rex.R", /* 0x44 */
9074 "rex.RB", /* 0x45 */
9075 "rex.RX", /* 0x46 */
9076 "rex.RXB", /* 0x47 */
9077 "rex.W", /* 0x48 */
9078 "rex.WB", /* 0x49 */
9079 "rex.WX", /* 0x4a */
9080 "rex.WXB", /* 0x4b */
9081 "rex.WR", /* 0x4c */
9082 "rex.WRB", /* 0x4d */
9083 "rex.WRX", /* 0x4e */
9084 "rex.WRXB", /* 0x4f */
9085 };
9086
9087 switch (pref)
9088 {
9089 /* REX prefixes family. */
9090 case 0x40:
9091 case 0x41:
9092 case 0x42:
9093 case 0x43:
9094 case 0x44:
9095 case 0x45:
9096 case 0x46:
9097 case 0x47:
9098 case 0x48:
9099 case 0x49:
9100 case 0x4a:
9101 case 0x4b:
9102 case 0x4c:
9103 case 0x4d:
9104 case 0x4e:
9105 case 0x4f:
9106 return rexes [pref - 0x40];
9107 case 0xf3:
9108 return "repz";
9109 case 0xf2:
9110 return "repnz";
9111 case 0xf0:
9112 return "lock";
9113 case 0x2e:
9114 return "cs";
9115 case 0x36:
9116 return "ss";
9117 case 0x3e:
9118 return "ds";
9119 case 0x26:
9120 return "es";
9121 case 0x64:
9122 return "fs";
9123 case 0x65:
9124 return "gs";
9125 case 0x66:
9126 return (sizeflag & DFLAG) ? "data16" : "data32";
9127 case 0x67:
9128 if (address_mode == mode_64bit)
9129 return (sizeflag & AFLAG) ? "addr32" : "addr64";
9130 else
9131 return (sizeflag & AFLAG) ? "addr16" : "addr32";
9132 case FWAIT_OPCODE:
9133 return "fwait";
9134 case REP_PREFIX:
9135 return "rep";
9136 case XACQUIRE_PREFIX:
9137 return "xacquire";
9138 case XRELEASE_PREFIX:
9139 return "xrelease";
9140 case BND_PREFIX:
9141 return "bnd";
9142 case NOTRACK_PREFIX:
9143 return "notrack";
9144 default:
9145 return NULL;
9146 }
9147 }
9148
9149 static char op_out[MAX_OPERANDS][100];
9150 static int op_ad, op_index[MAX_OPERANDS];
9151 static int two_source_ops;
9152 static bfd_vma op_address[MAX_OPERANDS];
9153 static bfd_vma op_riprel[MAX_OPERANDS];
9154 static bfd_vma start_pc;
9155
9156 /*
9157 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9158 * (see topic "Redundant prefixes" in the "Differences from 8086"
9159 * section of the "Virtual 8086 Mode" chapter.)
9160 * 'pc' should be the address of this instruction, it will
9161 * be used to print the target address if this is a relative jump or call
9162 * The function returns the length of this instruction in bytes.
9163 */
9164
9165 static char intel_syntax;
9166 static char intel_mnemonic = !SYSV386_COMPAT;
9167 static char open_char;
9168 static char close_char;
9169 static char separator_char;
9170 static char scale_char;
9171
9172 enum x86_64_isa
9173 {
9174 amd64 = 1,
9175 intel64
9176 };
9177
9178 static enum x86_64_isa isa64;
9179
9180 /* Here for backwards compatibility. When gdb stops using
9181 print_insn_i386_att and print_insn_i386_intel these functions can
9182 disappear, and print_insn_i386 be merged into print_insn. */
9183 int
9184 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9185 {
9186 intel_syntax = 0;
9187
9188 return print_insn (pc, info);
9189 }
9190
9191 int
9192 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9193 {
9194 intel_syntax = 1;
9195
9196 return print_insn (pc, info);
9197 }
9198
9199 int
9200 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9201 {
9202 intel_syntax = -1;
9203
9204 return print_insn (pc, info);
9205 }
9206
9207 void
9208 print_i386_disassembler_options (FILE *stream)
9209 {
9210 fprintf (stream, _("\n\
9211 The following i386/x86-64 specific disassembler options are supported for use\n\
9212 with the -M switch (multiple options should be separated by commas):\n"));
9213
9214 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
9215 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
9216 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
9217 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
9218 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9219 fprintf (stream, _(" att-mnemonic\n"
9220 " Display instruction in AT&T mnemonic\n"));
9221 fprintf (stream, _(" intel-mnemonic\n"
9222 " Display instruction in Intel mnemonic\n"));
9223 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
9224 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
9225 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
9226 fprintf (stream, _(" data32 Assume 32bit data size\n"));
9227 fprintf (stream, _(" data16 Assume 16bit data size\n"));
9228 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9229 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
9230 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
9231 }
9232
9233 /* Bad opcode. */
9234 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
9235
9236 /* Get a pointer to struct dis386 with a valid name. */
9237
9238 static const struct dis386 *
9239 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9240 {
9241 int vindex, vex_table_index;
9242
9243 if (dp->name != NULL)
9244 return dp;
9245
9246 switch (dp->op[0].bytemode)
9247 {
9248 case USE_REG_TABLE:
9249 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9250 break;
9251
9252 case USE_MOD_TABLE:
9253 vindex = modrm.mod == 0x3 ? 1 : 0;
9254 dp = &mod_table[dp->op[1].bytemode][vindex];
9255 break;
9256
9257 case USE_RM_TABLE:
9258 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9259 break;
9260
9261 case USE_PREFIX_TABLE:
9262 if (need_vex)
9263 {
9264 /* The prefix in VEX is implicit. */
9265 switch (vex.prefix)
9266 {
9267 case 0:
9268 vindex = 0;
9269 break;
9270 case REPE_PREFIX_OPCODE:
9271 vindex = 1;
9272 break;
9273 case DATA_PREFIX_OPCODE:
9274 vindex = 2;
9275 break;
9276 case REPNE_PREFIX_OPCODE:
9277 vindex = 3;
9278 break;
9279 default:
9280 abort ();
9281 break;
9282 }
9283 }
9284 else
9285 {
9286 int last_prefix = -1;
9287 int prefix = 0;
9288 vindex = 0;
9289 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9290 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9291 last one wins. */
9292 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9293 {
9294 if (last_repz_prefix > last_repnz_prefix)
9295 {
9296 vindex = 1;
9297 prefix = PREFIX_REPZ;
9298 last_prefix = last_repz_prefix;
9299 }
9300 else
9301 {
9302 vindex = 3;
9303 prefix = PREFIX_REPNZ;
9304 last_prefix = last_repnz_prefix;
9305 }
9306
9307 /* Check if prefix should be ignored. */
9308 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9309 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9310 & prefix) != 0)
9311 vindex = 0;
9312 }
9313
9314 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
9315 {
9316 vindex = 2;
9317 prefix = PREFIX_DATA;
9318 last_prefix = last_data_prefix;
9319 }
9320
9321 if (vindex != 0)
9322 {
9323 used_prefixes |= prefix;
9324 all_prefixes[last_prefix] = 0;
9325 }
9326 }
9327 dp = &prefix_table[dp->op[1].bytemode][vindex];
9328 break;
9329
9330 case USE_X86_64_TABLE:
9331 vindex = address_mode == mode_64bit ? 1 : 0;
9332 dp = &x86_64_table[dp->op[1].bytemode][vindex];
9333 break;
9334
9335 case USE_3BYTE_TABLE:
9336 FETCH_DATA (info, codep + 2);
9337 vindex = *codep++;
9338 dp = &three_byte_table[dp->op[1].bytemode][vindex];
9339 end_codep = codep;
9340 modrm.mod = (*codep >> 6) & 3;
9341 modrm.reg = (*codep >> 3) & 7;
9342 modrm.rm = *codep & 7;
9343 break;
9344
9345 case USE_VEX_LEN_TABLE:
9346 if (!need_vex)
9347 abort ();
9348
9349 switch (vex.length)
9350 {
9351 case 128:
9352 vindex = 0;
9353 break;
9354 case 256:
9355 vindex = 1;
9356 break;
9357 default:
9358 abort ();
9359 break;
9360 }
9361
9362 dp = &vex_len_table[dp->op[1].bytemode][vindex];
9363 break;
9364
9365 case USE_EVEX_LEN_TABLE:
9366 if (!vex.evex)
9367 abort ();
9368
9369 switch (vex.length)
9370 {
9371 case 128:
9372 vindex = 0;
9373 break;
9374 case 256:
9375 vindex = 1;
9376 break;
9377 case 512:
9378 vindex = 2;
9379 break;
9380 default:
9381 abort ();
9382 break;
9383 }
9384
9385 dp = &evex_len_table[dp->op[1].bytemode][vindex];
9386 break;
9387
9388 case USE_XOP_8F_TABLE:
9389 FETCH_DATA (info, codep + 3);
9390 rex = ~(*codep >> 5) & 0x7;
9391
9392 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9393 switch ((*codep & 0x1f))
9394 {
9395 default:
9396 dp = &bad_opcode;
9397 return dp;
9398 case 0x8:
9399 vex_table_index = XOP_08;
9400 break;
9401 case 0x9:
9402 vex_table_index = XOP_09;
9403 break;
9404 case 0xa:
9405 vex_table_index = XOP_0A;
9406 break;
9407 }
9408 codep++;
9409 vex.w = *codep & 0x80;
9410 if (vex.w && address_mode == mode_64bit)
9411 rex |= REX_W;
9412
9413 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9414 if (address_mode != mode_64bit)
9415 {
9416 /* In 16/32-bit mode REX_B is silently ignored. */
9417 rex &= ~REX_B;
9418 }
9419
9420 vex.length = (*codep & 0x4) ? 256 : 128;
9421 switch ((*codep & 0x3))
9422 {
9423 case 0:
9424 break;
9425 case 1:
9426 vex.prefix = DATA_PREFIX_OPCODE;
9427 break;
9428 case 2:
9429 vex.prefix = REPE_PREFIX_OPCODE;
9430 break;
9431 case 3:
9432 vex.prefix = REPNE_PREFIX_OPCODE;
9433 break;
9434 }
9435 need_vex = 1;
9436 codep++;
9437 vindex = *codep++;
9438 dp = &xop_table[vex_table_index][vindex];
9439
9440 end_codep = codep;
9441 FETCH_DATA (info, codep + 1);
9442 modrm.mod = (*codep >> 6) & 3;
9443 modrm.reg = (*codep >> 3) & 7;
9444 modrm.rm = *codep & 7;
9445
9446 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9447 having to decode the bits for every otherwise valid encoding. */
9448 if (vex.prefix)
9449 return &bad_opcode;
9450 break;
9451
9452 case USE_VEX_C4_TABLE:
9453 /* VEX prefix. */
9454 FETCH_DATA (info, codep + 3);
9455 rex = ~(*codep >> 5) & 0x7;
9456 switch ((*codep & 0x1f))
9457 {
9458 default:
9459 dp = &bad_opcode;
9460 return dp;
9461 case 0x1:
9462 vex_table_index = VEX_0F;
9463 break;
9464 case 0x2:
9465 vex_table_index = VEX_0F38;
9466 break;
9467 case 0x3:
9468 vex_table_index = VEX_0F3A;
9469 break;
9470 }
9471 codep++;
9472 vex.w = *codep & 0x80;
9473 if (address_mode == mode_64bit)
9474 {
9475 if (vex.w)
9476 rex |= REX_W;
9477 }
9478 else
9479 {
9480 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9481 is ignored, other REX bits are 0 and the highest bit in
9482 VEX.vvvv is also ignored (but we mustn't clear it here). */
9483 rex = 0;
9484 }
9485 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9486 vex.length = (*codep & 0x4) ? 256 : 128;
9487 switch ((*codep & 0x3))
9488 {
9489 case 0:
9490 break;
9491 case 1:
9492 vex.prefix = DATA_PREFIX_OPCODE;
9493 break;
9494 case 2:
9495 vex.prefix = REPE_PREFIX_OPCODE;
9496 break;
9497 case 3:
9498 vex.prefix = REPNE_PREFIX_OPCODE;
9499 break;
9500 }
9501 need_vex = 1;
9502 codep++;
9503 vindex = *codep++;
9504 dp = &vex_table[vex_table_index][vindex];
9505 end_codep = codep;
9506 /* There is no MODRM byte for VEX0F 77. */
9507 if (vex_table_index != VEX_0F || vindex != 0x77)
9508 {
9509 FETCH_DATA (info, codep + 1);
9510 modrm.mod = (*codep >> 6) & 3;
9511 modrm.reg = (*codep >> 3) & 7;
9512 modrm.rm = *codep & 7;
9513 }
9514 break;
9515
9516 case USE_VEX_C5_TABLE:
9517 /* VEX prefix. */
9518 FETCH_DATA (info, codep + 2);
9519 rex = (*codep & 0x80) ? 0 : REX_R;
9520
9521 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9522 VEX.vvvv is 1. */
9523 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9524 vex.length = (*codep & 0x4) ? 256 : 128;
9525 switch ((*codep & 0x3))
9526 {
9527 case 0:
9528 break;
9529 case 1:
9530 vex.prefix = DATA_PREFIX_OPCODE;
9531 break;
9532 case 2:
9533 vex.prefix = REPE_PREFIX_OPCODE;
9534 break;
9535 case 3:
9536 vex.prefix = REPNE_PREFIX_OPCODE;
9537 break;
9538 }
9539 need_vex = 1;
9540 codep++;
9541 vindex = *codep++;
9542 dp = &vex_table[dp->op[1].bytemode][vindex];
9543 end_codep = codep;
9544 /* There is no MODRM byte for VEX 77. */
9545 if (vindex != 0x77)
9546 {
9547 FETCH_DATA (info, codep + 1);
9548 modrm.mod = (*codep >> 6) & 3;
9549 modrm.reg = (*codep >> 3) & 7;
9550 modrm.rm = *codep & 7;
9551 }
9552 break;
9553
9554 case USE_VEX_W_TABLE:
9555 if (!need_vex)
9556 abort ();
9557
9558 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
9559 break;
9560
9561 case USE_EVEX_TABLE:
9562 two_source_ops = 0;
9563 /* EVEX prefix. */
9564 vex.evex = 1;
9565 FETCH_DATA (info, codep + 4);
9566 /* The first byte after 0x62. */
9567 rex = ~(*codep >> 5) & 0x7;
9568 vex.r = *codep & 0x10;
9569 switch ((*codep & 0xf))
9570 {
9571 default:
9572 return &bad_opcode;
9573 case 0x1:
9574 vex_table_index = EVEX_0F;
9575 break;
9576 case 0x2:
9577 vex_table_index = EVEX_0F38;
9578 break;
9579 case 0x3:
9580 vex_table_index = EVEX_0F3A;
9581 break;
9582 }
9583
9584 /* The second byte after 0x62. */
9585 codep++;
9586 vex.w = *codep & 0x80;
9587 if (vex.w && address_mode == mode_64bit)
9588 rex |= REX_W;
9589
9590 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9591
9592 /* The U bit. */
9593 if (!(*codep & 0x4))
9594 return &bad_opcode;
9595
9596 switch ((*codep & 0x3))
9597 {
9598 case 0:
9599 break;
9600 case 1:
9601 vex.prefix = DATA_PREFIX_OPCODE;
9602 break;
9603 case 2:
9604 vex.prefix = REPE_PREFIX_OPCODE;
9605 break;
9606 case 3:
9607 vex.prefix = REPNE_PREFIX_OPCODE;
9608 break;
9609 }
9610
9611 /* The third byte after 0x62. */
9612 codep++;
9613
9614 /* Remember the static rounding bits. */
9615 vex.ll = (*codep >> 5) & 3;
9616 vex.b = (*codep & 0x10) != 0;
9617
9618 vex.v = *codep & 0x8;
9619 vex.mask_register_specifier = *codep & 0x7;
9620 vex.zeroing = *codep & 0x80;
9621
9622 if (address_mode != mode_64bit)
9623 {
9624 /* In 16/32-bit mode silently ignore following bits. */
9625 rex &= ~REX_B;
9626 vex.r = 1;
9627 vex.v = 1;
9628 }
9629
9630 need_vex = 1;
9631 codep++;
9632 vindex = *codep++;
9633 dp = &evex_table[vex_table_index][vindex];
9634 end_codep = codep;
9635 FETCH_DATA (info, codep + 1);
9636 modrm.mod = (*codep >> 6) & 3;
9637 modrm.reg = (*codep >> 3) & 7;
9638 modrm.rm = *codep & 7;
9639
9640 /* Set vector length. */
9641 if (modrm.mod == 3 && vex.b)
9642 vex.length = 512;
9643 else
9644 {
9645 switch (vex.ll)
9646 {
9647 case 0x0:
9648 vex.length = 128;
9649 break;
9650 case 0x1:
9651 vex.length = 256;
9652 break;
9653 case 0x2:
9654 vex.length = 512;
9655 break;
9656 default:
9657 return &bad_opcode;
9658 }
9659 }
9660 break;
9661
9662 case 0:
9663 dp = &bad_opcode;
9664 break;
9665
9666 default:
9667 abort ();
9668 }
9669
9670 if (dp->name != NULL)
9671 return dp;
9672 else
9673 return get_valid_dis386 (dp, info);
9674 }
9675
9676 static void
9677 get_sib (disassemble_info *info, int sizeflag)
9678 {
9679 /* If modrm.mod == 3, operand must be register. */
9680 if (need_modrm
9681 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
9682 && modrm.mod != 3
9683 && modrm.rm == 4)
9684 {
9685 FETCH_DATA (info, codep + 2);
9686 sib.index = (codep [1] >> 3) & 7;
9687 sib.scale = (codep [1] >> 6) & 3;
9688 sib.base = codep [1] & 7;
9689 }
9690 }
9691
9692 static int
9693 print_insn (bfd_vma pc, disassemble_info *info)
9694 {
9695 const struct dis386 *dp;
9696 int i;
9697 char *op_txt[MAX_OPERANDS];
9698 int needcomma;
9699 int sizeflag, orig_sizeflag;
9700 const char *p;
9701 struct dis_private priv;
9702 int prefix_length;
9703
9704 priv.orig_sizeflag = AFLAG | DFLAG;
9705 if ((info->mach & bfd_mach_i386_i386) != 0)
9706 address_mode = mode_32bit;
9707 else if (info->mach == bfd_mach_i386_i8086)
9708 {
9709 address_mode = mode_16bit;
9710 priv.orig_sizeflag = 0;
9711 }
9712 else
9713 address_mode = mode_64bit;
9714
9715 if (intel_syntax == (char) -1)
9716 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
9717
9718 for (p = info->disassembler_options; p != NULL; )
9719 {
9720 if (CONST_STRNEQ (p, "amd64"))
9721 isa64 = amd64;
9722 else if (CONST_STRNEQ (p, "intel64"))
9723 isa64 = intel64;
9724 else if (CONST_STRNEQ (p, "x86-64"))
9725 {
9726 address_mode = mode_64bit;
9727 priv.orig_sizeflag |= AFLAG | DFLAG;
9728 }
9729 else if (CONST_STRNEQ (p, "i386"))
9730 {
9731 address_mode = mode_32bit;
9732 priv.orig_sizeflag |= AFLAG | DFLAG;
9733 }
9734 else if (CONST_STRNEQ (p, "i8086"))
9735 {
9736 address_mode = mode_16bit;
9737 priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9738 }
9739 else if (CONST_STRNEQ (p, "intel"))
9740 {
9741 intel_syntax = 1;
9742 if (CONST_STRNEQ (p + 5, "-mnemonic"))
9743 intel_mnemonic = 1;
9744 }
9745 else if (CONST_STRNEQ (p, "att"))
9746 {
9747 intel_syntax = 0;
9748 if (CONST_STRNEQ (p + 3, "-mnemonic"))
9749 intel_mnemonic = 0;
9750 }
9751 else if (CONST_STRNEQ (p, "addr"))
9752 {
9753 if (address_mode == mode_64bit)
9754 {
9755 if (p[4] == '3' && p[5] == '2')
9756 priv.orig_sizeflag &= ~AFLAG;
9757 else if (p[4] == '6' && p[5] == '4')
9758 priv.orig_sizeflag |= AFLAG;
9759 }
9760 else
9761 {
9762 if (p[4] == '1' && p[5] == '6')
9763 priv.orig_sizeflag &= ~AFLAG;
9764 else if (p[4] == '3' && p[5] == '2')
9765 priv.orig_sizeflag |= AFLAG;
9766 }
9767 }
9768 else if (CONST_STRNEQ (p, "data"))
9769 {
9770 if (p[4] == '1' && p[5] == '6')
9771 priv.orig_sizeflag &= ~DFLAG;
9772 else if (p[4] == '3' && p[5] == '2')
9773 priv.orig_sizeflag |= DFLAG;
9774 }
9775 else if (CONST_STRNEQ (p, "suffix"))
9776 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9777
9778 p = strchr (p, ',');
9779 if (p != NULL)
9780 p++;
9781 }
9782
9783 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9784 {
9785 (*info->fprintf_func) (info->stream,
9786 _("64-bit address is disabled"));
9787 return -1;
9788 }
9789
9790 if (intel_syntax)
9791 {
9792 names64 = intel_names64;
9793 names32 = intel_names32;
9794 names16 = intel_names16;
9795 names8 = intel_names8;
9796 names8rex = intel_names8rex;
9797 names_seg = intel_names_seg;
9798 names_mm = intel_names_mm;
9799 names_bnd = intel_names_bnd;
9800 names_xmm = intel_names_xmm;
9801 names_ymm = intel_names_ymm;
9802 names_zmm = intel_names_zmm;
9803 names_tmm = intel_names_tmm;
9804 index64 = intel_index64;
9805 index32 = intel_index32;
9806 names_mask = intel_names_mask;
9807 index16 = intel_index16;
9808 open_char = '[';
9809 close_char = ']';
9810 separator_char = '+';
9811 scale_char = '*';
9812 }
9813 else
9814 {
9815 names64 = att_names64;
9816 names32 = att_names32;
9817 names16 = att_names16;
9818 names8 = att_names8;
9819 names8rex = att_names8rex;
9820 names_seg = att_names_seg;
9821 names_mm = att_names_mm;
9822 names_bnd = att_names_bnd;
9823 names_xmm = att_names_xmm;
9824 names_ymm = att_names_ymm;
9825 names_zmm = att_names_zmm;
9826 names_tmm = att_names_tmm;
9827 index64 = att_index64;
9828 index32 = att_index32;
9829 names_mask = att_names_mask;
9830 index16 = att_index16;
9831 open_char = '(';
9832 close_char = ')';
9833 separator_char = ',';
9834 scale_char = ',';
9835 }
9836
9837 /* The output looks better if we put 7 bytes on a line, since that
9838 puts most long word instructions on a single line. Use 8 bytes
9839 for Intel L1OM. */
9840 if ((info->mach & bfd_mach_l1om) != 0)
9841 info->bytes_per_line = 8;
9842 else
9843 info->bytes_per_line = 7;
9844
9845 info->private_data = &priv;
9846 priv.max_fetched = priv.the_buffer;
9847 priv.insn_start = pc;
9848
9849 obuf[0] = 0;
9850 for (i = 0; i < MAX_OPERANDS; ++i)
9851 {
9852 op_out[i][0] = 0;
9853 op_index[i] = -1;
9854 }
9855
9856 the_info = info;
9857 start_pc = pc;
9858 start_codep = priv.the_buffer;
9859 codep = priv.the_buffer;
9860
9861 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9862 {
9863 const char *name;
9864
9865 /* Getting here means we tried for data but didn't get it. That
9866 means we have an incomplete instruction of some sort. Just
9867 print the first byte as a prefix or a .byte pseudo-op. */
9868 if (codep > priv.the_buffer)
9869 {
9870 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9871 if (name != NULL)
9872 (*info->fprintf_func) (info->stream, "%s", name);
9873 else
9874 {
9875 /* Just print the first byte as a .byte instruction. */
9876 (*info->fprintf_func) (info->stream, ".byte 0x%x",
9877 (unsigned int) priv.the_buffer[0]);
9878 }
9879
9880 return 1;
9881 }
9882
9883 return -1;
9884 }
9885
9886 obufp = obuf;
9887 sizeflag = priv.orig_sizeflag;
9888
9889 if (!ckprefix () || rex_used)
9890 {
9891 /* Too many prefixes or unused REX prefixes. */
9892 for (i = 0;
9893 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
9894 i++)
9895 (*info->fprintf_func) (info->stream, "%s%s",
9896 i == 0 ? "" : " ",
9897 prefix_name (all_prefixes[i], sizeflag));
9898 return i;
9899 }
9900
9901 insn_codep = codep;
9902
9903 FETCH_DATA (info, codep + 1);
9904 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9905
9906 if (((prefixes & PREFIX_FWAIT)
9907 && ((*codep < 0xd8) || (*codep > 0xdf))))
9908 {
9909 /* Handle prefixes before fwait. */
9910 for (i = 0; i < fwait_prefix && all_prefixes[i];
9911 i++)
9912 (*info->fprintf_func) (info->stream, "%s ",
9913 prefix_name (all_prefixes[i], sizeflag));
9914 (*info->fprintf_func) (info->stream, "fwait");
9915 return i + 1;
9916 }
9917
9918 if (*codep == 0x0f)
9919 {
9920 unsigned char threebyte;
9921
9922 codep++;
9923 FETCH_DATA (info, codep + 1);
9924 threebyte = *codep;
9925 dp = &dis386_twobyte[threebyte];
9926 need_modrm = twobyte_has_modrm[*codep];
9927 codep++;
9928 }
9929 else
9930 {
9931 dp = &dis386[*codep];
9932 need_modrm = onebyte_has_modrm[*codep];
9933 codep++;
9934 }
9935
9936 /* Save sizeflag for printing the extra prefixes later before updating
9937 it for mnemonic and operand processing. The prefix names depend
9938 only on the address mode. */
9939 orig_sizeflag = sizeflag;
9940 if (prefixes & PREFIX_ADDR)
9941 sizeflag ^= AFLAG;
9942 if ((prefixes & PREFIX_DATA))
9943 sizeflag ^= DFLAG;
9944
9945 end_codep = codep;
9946 if (need_modrm)
9947 {
9948 FETCH_DATA (info, codep + 1);
9949 modrm.mod = (*codep >> 6) & 3;
9950 modrm.reg = (*codep >> 3) & 7;
9951 modrm.rm = *codep & 7;
9952 }
9953
9954 need_vex = 0;
9955 memset (&vex, 0, sizeof (vex));
9956
9957 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9958 {
9959 get_sib (info, sizeflag);
9960 dofloat (sizeflag);
9961 }
9962 else
9963 {
9964 dp = get_valid_dis386 (dp, info);
9965 if (dp != NULL && putop (dp->name, sizeflag) == 0)
9966 {
9967 get_sib (info, sizeflag);
9968 for (i = 0; i < MAX_OPERANDS; ++i)
9969 {
9970 obufp = op_out[i];
9971 op_ad = MAX_OPERANDS - 1 - i;
9972 if (dp->op[i].rtn)
9973 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
9974 /* For EVEX instruction after the last operand masking
9975 should be printed. */
9976 if (i == 0 && vex.evex)
9977 {
9978 /* Don't print {%k0}. */
9979 if (vex.mask_register_specifier)
9980 {
9981 oappend ("{");
9982 oappend (names_mask[vex.mask_register_specifier]);
9983 oappend ("}");
9984 }
9985 if (vex.zeroing)
9986 oappend ("{z}");
9987 }
9988 }
9989 }
9990 }
9991
9992 /* Clear instruction information. */
9993 if (the_info)
9994 {
9995 the_info->insn_info_valid = 0;
9996 the_info->branch_delay_insns = 0;
9997 the_info->data_size = 0;
9998 the_info->insn_type = dis_noninsn;
9999 the_info->target = 0;
10000 the_info->target2 = 0;
10001 }
10002
10003 /* Reset jump operation indicator. */
10004 op_is_jump = FALSE;
10005
10006 {
10007 int jump_detection = 0;
10008
10009 /* Extract flags. */
10010 for (i = 0; i < MAX_OPERANDS; ++i)
10011 {
10012 if ((dp->op[i].rtn == OP_J)
10013 || (dp->op[i].rtn == OP_indirE))
10014 jump_detection |= 1;
10015 else if ((dp->op[i].rtn == BND_Fixup)
10016 || (!dp->op[i].rtn && !dp->op[i].bytemode))
10017 jump_detection |= 2;
10018 else if ((dp->op[i].bytemode == cond_jump_mode)
10019 || (dp->op[i].bytemode == loop_jcxz_mode))
10020 jump_detection |= 4;
10021 }
10022
10023 /* Determine if this is a jump or branch. */
10024 if ((jump_detection & 0x3) == 0x3)
10025 {
10026 op_is_jump = TRUE;
10027 if (jump_detection & 0x4)
10028 the_info->insn_type = dis_condbranch;
10029 else
10030 the_info->insn_type =
10031 (dp->name && !strncmp(dp->name, "call", 4))
10032 ? dis_jsr : dis_branch;
10033 }
10034 }
10035
10036 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
10037 are all 0s in inverted form. */
10038 if (need_vex && vex.register_specifier != 0)
10039 {
10040 (*info->fprintf_func) (info->stream, "(bad)");
10041 return end_codep - priv.the_buffer;
10042 }
10043
10044 switch (dp->prefix_requirement)
10045 {
10046 case PREFIX_DATA:
10047 /* If only the data prefix is marked as mandatory, its absence renders
10048 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
10049 if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA))
10050 {
10051 (*info->fprintf_func) (info->stream, "(bad)");
10052 return end_codep - priv.the_buffer;
10053 }
10054 used_prefixes |= PREFIX_DATA;
10055 /* Fall through. */
10056 case PREFIX_OPCODE:
10057 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
10058 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
10059 used by putop and MMX/SSE operand and may be overridden by the
10060 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
10061 separately. */
10062 if (((need_vex
10063 ? vex.prefix == REPE_PREFIX_OPCODE
10064 || vex.prefix == REPNE_PREFIX_OPCODE
10065 : (prefixes
10066 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
10067 && (used_prefixes
10068 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
10069 || (((need_vex
10070 ? vex.prefix == DATA_PREFIX_OPCODE
10071 : ((prefixes
10072 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
10073 == PREFIX_DATA))
10074 && (used_prefixes & PREFIX_DATA) == 0))
10075 || (vex.evex && dp->prefix_requirement != PREFIX_DATA
10076 && !vex.w != !(used_prefixes & PREFIX_DATA)))
10077 {
10078 (*info->fprintf_func) (info->stream, "(bad)");
10079 return end_codep - priv.the_buffer;
10080 }
10081 break;
10082 }
10083
10084 /* Check if the REX prefix is used. */
10085 if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
10086 all_prefixes[last_rex_prefix] = 0;
10087
10088 /* Check if the SEG prefix is used. */
10089 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
10090 | PREFIX_FS | PREFIX_GS)) != 0
10091 && (used_prefixes & active_seg_prefix) != 0)
10092 all_prefixes[last_seg_prefix] = 0;
10093
10094 /* Check if the ADDR prefix is used. */
10095 if ((prefixes & PREFIX_ADDR) != 0
10096 && (used_prefixes & PREFIX_ADDR) != 0)
10097 all_prefixes[last_addr_prefix] = 0;
10098
10099 /* Check if the DATA prefix is used. */
10100 if ((prefixes & PREFIX_DATA) != 0
10101 && (used_prefixes & PREFIX_DATA) != 0
10102 && !need_vex)
10103 all_prefixes[last_data_prefix] = 0;
10104
10105 /* Print the extra prefixes. */
10106 prefix_length = 0;
10107 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10108 if (all_prefixes[i])
10109 {
10110 const char *name;
10111 name = prefix_name (all_prefixes[i], orig_sizeflag);
10112 if (name == NULL)
10113 abort ();
10114 prefix_length += strlen (name) + 1;
10115 (*info->fprintf_func) (info->stream, "%s ", name);
10116 }
10117
10118 /* Check maximum code length. */
10119 if ((codep - start_codep) > MAX_CODE_LENGTH)
10120 {
10121 (*info->fprintf_func) (info->stream, "(bad)");
10122 return MAX_CODE_LENGTH;
10123 }
10124
10125 obufp = mnemonicendp;
10126 for (i = strlen (obuf) + prefix_length; i < 6; i++)
10127 oappend (" ");
10128 oappend (" ");
10129 (*info->fprintf_func) (info->stream, "%s", obuf);
10130
10131 /* The enter and bound instructions are printed with operands in the same
10132 order as the intel book; everything else is printed in reverse order. */
10133 if (intel_syntax || two_source_ops)
10134 {
10135 bfd_vma riprel;
10136
10137 for (i = 0; i < MAX_OPERANDS; ++i)
10138 op_txt[i] = op_out[i];
10139
10140 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
10141 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
10142 {
10143 op_txt[2] = op_out[3];
10144 op_txt[3] = op_out[2];
10145 }
10146
10147 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10148 {
10149 op_ad = op_index[i];
10150 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10151 op_index[MAX_OPERANDS - 1 - i] = op_ad;
10152 riprel = op_riprel[i];
10153 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10154 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10155 }
10156 }
10157 else
10158 {
10159 for (i = 0; i < MAX_OPERANDS; ++i)
10160 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10161 }
10162
10163 needcomma = 0;
10164 for (i = 0; i < MAX_OPERANDS; ++i)
10165 if (*op_txt[i])
10166 {
10167 if (needcomma)
10168 (*info->fprintf_func) (info->stream, ",");
10169 if (op_index[i] != -1 && !op_riprel[i])
10170 {
10171 bfd_vma target = (bfd_vma) op_address[op_index[i]];
10172
10173 if (the_info && op_is_jump)
10174 {
10175 the_info->insn_info_valid = 1;
10176 the_info->branch_delay_insns = 0;
10177 the_info->data_size = 0;
10178 the_info->target = target;
10179 the_info->target2 = 0;
10180 }
10181 (*info->print_address_func) (target, info);
10182 }
10183 else
10184 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10185 needcomma = 1;
10186 }
10187
10188 for (i = 0; i < MAX_OPERANDS; i++)
10189 if (op_index[i] != -1 && op_riprel[i])
10190 {
10191 (*info->fprintf_func) (info->stream, " # ");
10192 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
10193 + op_address[op_index[i]]), info);
10194 break;
10195 }
10196 return codep - priv.the_buffer;
10197 }
10198
10199 static const char *float_mem[] = {
10200 /* d8 */
10201 "fadd{s|}",
10202 "fmul{s|}",
10203 "fcom{s|}",
10204 "fcomp{s|}",
10205 "fsub{s|}",
10206 "fsubr{s|}",
10207 "fdiv{s|}",
10208 "fdivr{s|}",
10209 /* d9 */
10210 "fld{s|}",
10211 "(bad)",
10212 "fst{s|}",
10213 "fstp{s|}",
10214 "fldenv{C|C}",
10215 "fldcw",
10216 "fNstenv{C|C}",
10217 "fNstcw",
10218 /* da */
10219 "fiadd{l|}",
10220 "fimul{l|}",
10221 "ficom{l|}",
10222 "ficomp{l|}",
10223 "fisub{l|}",
10224 "fisubr{l|}",
10225 "fidiv{l|}",
10226 "fidivr{l|}",
10227 /* db */
10228 "fild{l|}",
10229 "fisttp{l|}",
10230 "fist{l|}",
10231 "fistp{l|}",
10232 "(bad)",
10233 "fld{t|}",
10234 "(bad)",
10235 "fstp{t|}",
10236 /* dc */
10237 "fadd{l|}",
10238 "fmul{l|}",
10239 "fcom{l|}",
10240 "fcomp{l|}",
10241 "fsub{l|}",
10242 "fsubr{l|}",
10243 "fdiv{l|}",
10244 "fdivr{l|}",
10245 /* dd */
10246 "fld{l|}",
10247 "fisttp{ll|}",
10248 "fst{l||}",
10249 "fstp{l|}",
10250 "frstor{C|C}",
10251 "(bad)",
10252 "fNsave{C|C}",
10253 "fNstsw",
10254 /* de */
10255 "fiadd{s|}",
10256 "fimul{s|}",
10257 "ficom{s|}",
10258 "ficomp{s|}",
10259 "fisub{s|}",
10260 "fisubr{s|}",
10261 "fidiv{s|}",
10262 "fidivr{s|}",
10263 /* df */
10264 "fild{s|}",
10265 "fisttp{s|}",
10266 "fist{s|}",
10267 "fistp{s|}",
10268 "fbld",
10269 "fild{ll|}",
10270 "fbstp",
10271 "fistp{ll|}",
10272 };
10273
10274 static const unsigned char float_mem_mode[] = {
10275 /* d8 */
10276 d_mode,
10277 d_mode,
10278 d_mode,
10279 d_mode,
10280 d_mode,
10281 d_mode,
10282 d_mode,
10283 d_mode,
10284 /* d9 */
10285 d_mode,
10286 0,
10287 d_mode,
10288 d_mode,
10289 0,
10290 w_mode,
10291 0,
10292 w_mode,
10293 /* da */
10294 d_mode,
10295 d_mode,
10296 d_mode,
10297 d_mode,
10298 d_mode,
10299 d_mode,
10300 d_mode,
10301 d_mode,
10302 /* db */
10303 d_mode,
10304 d_mode,
10305 d_mode,
10306 d_mode,
10307 0,
10308 t_mode,
10309 0,
10310 t_mode,
10311 /* dc */
10312 q_mode,
10313 q_mode,
10314 q_mode,
10315 q_mode,
10316 q_mode,
10317 q_mode,
10318 q_mode,
10319 q_mode,
10320 /* dd */
10321 q_mode,
10322 q_mode,
10323 q_mode,
10324 q_mode,
10325 0,
10326 0,
10327 0,
10328 w_mode,
10329 /* de */
10330 w_mode,
10331 w_mode,
10332 w_mode,
10333 w_mode,
10334 w_mode,
10335 w_mode,
10336 w_mode,
10337 w_mode,
10338 /* df */
10339 w_mode,
10340 w_mode,
10341 w_mode,
10342 w_mode,
10343 t_mode,
10344 q_mode,
10345 t_mode,
10346 q_mode
10347 };
10348
10349 #define ST { OP_ST, 0 }
10350 #define STi { OP_STi, 0 }
10351
10352 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10353 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10354 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10355 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10356 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10357 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10358 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10359 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10360 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10361
10362 static const struct dis386 float_reg[][8] = {
10363 /* d8 */
10364 {
10365 { "fadd", { ST, STi }, 0 },
10366 { "fmul", { ST, STi }, 0 },
10367 { "fcom", { STi }, 0 },
10368 { "fcomp", { STi }, 0 },
10369 { "fsub", { ST, STi }, 0 },
10370 { "fsubr", { ST, STi }, 0 },
10371 { "fdiv", { ST, STi }, 0 },
10372 { "fdivr", { ST, STi }, 0 },
10373 },
10374 /* d9 */
10375 {
10376 { "fld", { STi }, 0 },
10377 { "fxch", { STi }, 0 },
10378 { FGRPd9_2 },
10379 { Bad_Opcode },
10380 { FGRPd9_4 },
10381 { FGRPd9_5 },
10382 { FGRPd9_6 },
10383 { FGRPd9_7 },
10384 },
10385 /* da */
10386 {
10387 { "fcmovb", { ST, STi }, 0 },
10388 { "fcmove", { ST, STi }, 0 },
10389 { "fcmovbe",{ ST, STi }, 0 },
10390 { "fcmovu", { ST, STi }, 0 },
10391 { Bad_Opcode },
10392 { FGRPda_5 },
10393 { Bad_Opcode },
10394 { Bad_Opcode },
10395 },
10396 /* db */
10397 {
10398 { "fcmovnb",{ ST, STi }, 0 },
10399 { "fcmovne",{ ST, STi }, 0 },
10400 { "fcmovnbe",{ ST, STi }, 0 },
10401 { "fcmovnu",{ ST, STi }, 0 },
10402 { FGRPdb_4 },
10403 { "fucomi", { ST, STi }, 0 },
10404 { "fcomi", { ST, STi }, 0 },
10405 { Bad_Opcode },
10406 },
10407 /* dc */
10408 {
10409 { "fadd", { STi, ST }, 0 },
10410 { "fmul", { STi, ST }, 0 },
10411 { Bad_Opcode },
10412 { Bad_Opcode },
10413 { "fsub{!M|r}", { STi, ST }, 0 },
10414 { "fsub{M|}", { STi, ST }, 0 },
10415 { "fdiv{!M|r}", { STi, ST }, 0 },
10416 { "fdiv{M|}", { STi, ST }, 0 },
10417 },
10418 /* dd */
10419 {
10420 { "ffree", { STi }, 0 },
10421 { Bad_Opcode },
10422 { "fst", { STi }, 0 },
10423 { "fstp", { STi }, 0 },
10424 { "fucom", { STi }, 0 },
10425 { "fucomp", { STi }, 0 },
10426 { Bad_Opcode },
10427 { Bad_Opcode },
10428 },
10429 /* de */
10430 {
10431 { "faddp", { STi, ST }, 0 },
10432 { "fmulp", { STi, ST }, 0 },
10433 { Bad_Opcode },
10434 { FGRPde_3 },
10435 { "fsub{!M|r}p", { STi, ST }, 0 },
10436 { "fsub{M|}p", { STi, ST }, 0 },
10437 { "fdiv{!M|r}p", { STi, ST }, 0 },
10438 { "fdiv{M|}p", { STi, ST }, 0 },
10439 },
10440 /* df */
10441 {
10442 { "ffreep", { STi }, 0 },
10443 { Bad_Opcode },
10444 { Bad_Opcode },
10445 { Bad_Opcode },
10446 { FGRPdf_4 },
10447 { "fucomip", { ST, STi }, 0 },
10448 { "fcomip", { ST, STi }, 0 },
10449 { Bad_Opcode },
10450 },
10451 };
10452
10453 static char *fgrps[][8] = {
10454 /* Bad opcode 0 */
10455 {
10456 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10457 },
10458
10459 /* d9_2 1 */
10460 {
10461 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10462 },
10463
10464 /* d9_4 2 */
10465 {
10466 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10467 },
10468
10469 /* d9_5 3 */
10470 {
10471 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10472 },
10473
10474 /* d9_6 4 */
10475 {
10476 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10477 },
10478
10479 /* d9_7 5 */
10480 {
10481 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10482 },
10483
10484 /* da_5 6 */
10485 {
10486 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10487 },
10488
10489 /* db_4 7 */
10490 {
10491 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10492 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10493 },
10494
10495 /* de_3 8 */
10496 {
10497 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10498 },
10499
10500 /* df_4 9 */
10501 {
10502 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10503 },
10504 };
10505
10506 static void
10507 swap_operand (void)
10508 {
10509 mnemonicendp[0] = '.';
10510 mnemonicendp[1] = 's';
10511 mnemonicendp += 2;
10512 }
10513
10514 static void
10515 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10516 int sizeflag ATTRIBUTE_UNUSED)
10517 {
10518 /* Skip mod/rm byte. */
10519 MODRM_CHECK;
10520 codep++;
10521 }
10522
10523 static void
10524 dofloat (int sizeflag)
10525 {
10526 const struct dis386 *dp;
10527 unsigned char floatop;
10528
10529 floatop = codep[-1];
10530
10531 if (modrm.mod != 3)
10532 {
10533 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10534
10535 putop (float_mem[fp_indx], sizeflag);
10536 obufp = op_out[0];
10537 op_ad = 2;
10538 OP_E (float_mem_mode[fp_indx], sizeflag);
10539 return;
10540 }
10541 /* Skip mod/rm byte. */
10542 MODRM_CHECK;
10543 codep++;
10544
10545 dp = &float_reg[floatop - 0xd8][modrm.reg];
10546 if (dp->name == NULL)
10547 {
10548 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10549
10550 /* Instruction fnstsw is only one with strange arg. */
10551 if (floatop == 0xdf && codep[-1] == 0xe0)
10552 strcpy (op_out[0], names16[0]);
10553 }
10554 else
10555 {
10556 putop (dp->name, sizeflag);
10557
10558 obufp = op_out[0];
10559 op_ad = 2;
10560 if (dp->op[0].rtn)
10561 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10562
10563 obufp = op_out[1];
10564 op_ad = 1;
10565 if (dp->op[1].rtn)
10566 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10567 }
10568 }
10569
10570 /* Like oappend (below), but S is a string starting with '%'.
10571 In Intel syntax, the '%' is elided. */
10572 static void
10573 oappend_maybe_intel (const char *s)
10574 {
10575 oappend (s + intel_syntax);
10576 }
10577
10578 static void
10579 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10580 {
10581 oappend_maybe_intel ("%st");
10582 }
10583
10584 static void
10585 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10586 {
10587 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10588 oappend_maybe_intel (scratchbuf);
10589 }
10590
10591 /* Capital letters in template are macros. */
10592 static int
10593 putop (const char *in_template, int sizeflag)
10594 {
10595 const char *p;
10596 int alt = 0;
10597 int cond = 1;
10598 unsigned int l = 0, len = 0;
10599 char last[4];
10600
10601 for (p = in_template; *p; p++)
10602 {
10603 if (len > l)
10604 {
10605 if (l >= sizeof (last) || !ISUPPER (*p))
10606 abort ();
10607 last[l++] = *p;
10608 continue;
10609 }
10610 switch (*p)
10611 {
10612 default:
10613 *obufp++ = *p;
10614 break;
10615 case '%':
10616 len++;
10617 break;
10618 case '!':
10619 cond = 0;
10620 break;
10621 case '{':
10622 if (intel_syntax)
10623 {
10624 while (*++p != '|')
10625 if (*p == '}' || *p == '\0')
10626 abort ();
10627 alt = 1;
10628 }
10629 break;
10630 case '|':
10631 while (*++p != '}')
10632 {
10633 if (*p == '\0')
10634 abort ();
10635 }
10636 break;
10637 case '}':
10638 alt = 0;
10639 break;
10640 case 'A':
10641 if (intel_syntax)
10642 break;
10643 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10644 *obufp++ = 'b';
10645 break;
10646 case 'B':
10647 if (l == 0)
10648 {
10649 case_B:
10650 if (intel_syntax)
10651 break;
10652 if (sizeflag & SUFFIX_ALWAYS)
10653 *obufp++ = 'b';
10654 }
10655 else if (l == 1 && last[0] == 'L')
10656 {
10657 if (address_mode == mode_64bit
10658 && !(prefixes & PREFIX_ADDR))
10659 {
10660 *obufp++ = 'a';
10661 *obufp++ = 'b';
10662 *obufp++ = 's';
10663 }
10664
10665 goto case_B;
10666 }
10667 else
10668 abort ();
10669 break;
10670 case 'C':
10671 if (intel_syntax && !alt)
10672 break;
10673 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10674 {
10675 if (sizeflag & DFLAG)
10676 *obufp++ = intel_syntax ? 'd' : 'l';
10677 else
10678 *obufp++ = intel_syntax ? 'w' : 's';
10679 used_prefixes |= (prefixes & PREFIX_DATA);
10680 }
10681 break;
10682 case 'D':
10683 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10684 break;
10685 USED_REX (REX_W);
10686 if (modrm.mod == 3)
10687 {
10688 if (rex & REX_W)
10689 *obufp++ = 'q';
10690 else
10691 {
10692 if (sizeflag & DFLAG)
10693 *obufp++ = intel_syntax ? 'd' : 'l';
10694 else
10695 *obufp++ = 'w';
10696 used_prefixes |= (prefixes & PREFIX_DATA);
10697 }
10698 }
10699 else
10700 *obufp++ = 'w';
10701 break;
10702 case 'E': /* For jcxz/jecxz */
10703 if (address_mode == mode_64bit)
10704 {
10705 if (sizeflag & AFLAG)
10706 *obufp++ = 'r';
10707 else
10708 *obufp++ = 'e';
10709 }
10710 else
10711 if (sizeflag & AFLAG)
10712 *obufp++ = 'e';
10713 used_prefixes |= (prefixes & PREFIX_ADDR);
10714 break;
10715 case 'F':
10716 if (intel_syntax)
10717 break;
10718 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10719 {
10720 if (sizeflag & AFLAG)
10721 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10722 else
10723 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10724 used_prefixes |= (prefixes & PREFIX_ADDR);
10725 }
10726 break;
10727 case 'G':
10728 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10729 break;
10730 if ((rex & REX_W) || (sizeflag & DFLAG))
10731 *obufp++ = 'l';
10732 else
10733 *obufp++ = 'w';
10734 if (!(rex & REX_W))
10735 used_prefixes |= (prefixes & PREFIX_DATA);
10736 break;
10737 case 'H':
10738 if (intel_syntax)
10739 break;
10740 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10741 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10742 {
10743 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10744 *obufp++ = ',';
10745 *obufp++ = 'p';
10746 if (prefixes & PREFIX_DS)
10747 *obufp++ = 't';
10748 else
10749 *obufp++ = 'n';
10750 }
10751 break;
10752 case 'K':
10753 USED_REX (REX_W);
10754 if (rex & REX_W)
10755 *obufp++ = 'q';
10756 else
10757 *obufp++ = 'd';
10758 break;
10759 case 'Z':
10760 if (l != 0)
10761 {
10762 if (l != 1 || last[0] != 'X')
10763 abort ();
10764 if (!need_vex || !vex.evex)
10765 abort ();
10766 if (intel_syntax
10767 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10768 break;
10769 switch (vex.length)
10770 {
10771 case 128:
10772 *obufp++ = 'x';
10773 break;
10774 case 256:
10775 *obufp++ = 'y';
10776 break;
10777 case 512:
10778 *obufp++ = 'z';
10779 break;
10780 default:
10781 abort ();
10782 }
10783 break;
10784 }
10785 if (intel_syntax)
10786 break;
10787 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
10788 {
10789 *obufp++ = 'q';
10790 break;
10791 }
10792 /* Fall through. */
10793 goto case_L;
10794 case 'L':
10795 if (l != 0)
10796 abort ();
10797 case_L:
10798 if (intel_syntax)
10799 break;
10800 if (sizeflag & SUFFIX_ALWAYS)
10801 *obufp++ = 'l';
10802 break;
10803 case 'M':
10804 if (intel_mnemonic != cond)
10805 *obufp++ = 'r';
10806 break;
10807 case 'N':
10808 if ((prefixes & PREFIX_FWAIT) == 0)
10809 *obufp++ = 'n';
10810 else
10811 used_prefixes |= PREFIX_FWAIT;
10812 break;
10813 case 'O':
10814 USED_REX (REX_W);
10815 if (rex & REX_W)
10816 *obufp++ = 'o';
10817 else if (intel_syntax && (sizeflag & DFLAG))
10818 *obufp++ = 'q';
10819 else
10820 *obufp++ = 'd';
10821 if (!(rex & REX_W))
10822 used_prefixes |= (prefixes & PREFIX_DATA);
10823 break;
10824 case '&':
10825 if (!intel_syntax
10826 && address_mode == mode_64bit
10827 && isa64 == intel64)
10828 {
10829 *obufp++ = 'q';
10830 break;
10831 }
10832 /* Fall through. */
10833 case 'T':
10834 if (!intel_syntax
10835 && address_mode == mode_64bit
10836 && ((sizeflag & DFLAG) || (rex & REX_W)))
10837 {
10838 *obufp++ = 'q';
10839 break;
10840 }
10841 /* Fall through. */
10842 goto case_P;
10843 case 'P':
10844 if (l == 0)
10845 {
10846 case_P:
10847 if (intel_syntax)
10848 {
10849 if ((rex & REX_W) == 0
10850 && (prefixes & PREFIX_DATA))
10851 {
10852 if ((sizeflag & DFLAG) == 0)
10853 *obufp++ = 'w';
10854 used_prefixes |= (prefixes & PREFIX_DATA);
10855 }
10856 break;
10857 }
10858 if ((prefixes & PREFIX_DATA)
10859 || (rex & REX_W)
10860 || (sizeflag & SUFFIX_ALWAYS))
10861 {
10862 USED_REX (REX_W);
10863 if (rex & REX_W)
10864 *obufp++ = 'q';
10865 else
10866 {
10867 if (sizeflag & DFLAG)
10868 *obufp++ = 'l';
10869 else
10870 *obufp++ = 'w';
10871 used_prefixes |= (prefixes & PREFIX_DATA);
10872 }
10873 }
10874 }
10875 else if (l == 1 && last[0] == 'L')
10876 {
10877 if ((prefixes & PREFIX_DATA)
10878 || (rex & REX_W)
10879 || (sizeflag & SUFFIX_ALWAYS))
10880 {
10881 USED_REX (REX_W);
10882 if (rex & REX_W)
10883 *obufp++ = 'q';
10884 else
10885 {
10886 if (sizeflag & DFLAG)
10887 *obufp++ = intel_syntax ? 'd' : 'l';
10888 else
10889 *obufp++ = 'w';
10890 used_prefixes |= (prefixes & PREFIX_DATA);
10891 }
10892 }
10893 }
10894 else
10895 abort ();
10896 break;
10897 case 'U':
10898 if (intel_syntax)
10899 break;
10900 if (address_mode == mode_64bit
10901 && ((sizeflag & DFLAG) || (rex & REX_W)))
10902 {
10903 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10904 *obufp++ = 'q';
10905 break;
10906 }
10907 /* Fall through. */
10908 goto case_Q;
10909 case 'Q':
10910 if (l == 0)
10911 {
10912 case_Q:
10913 if (intel_syntax && !alt)
10914 break;
10915 USED_REX (REX_W);
10916 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10917 {
10918 if (rex & REX_W)
10919 *obufp++ = 'q';
10920 else
10921 {
10922 if (sizeflag & DFLAG)
10923 *obufp++ = intel_syntax ? 'd' : 'l';
10924 else
10925 *obufp++ = 'w';
10926 used_prefixes |= (prefixes & PREFIX_DATA);
10927 }
10928 }
10929 }
10930 else if (l == 1 && last[0] == 'D')
10931 *obufp++ = vex.w ? 'q' : 'd';
10932 else if (l == 1 && last[0] == 'L')
10933 {
10934 if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10935 : address_mode != mode_64bit)
10936 break;
10937 if ((rex & REX_W))
10938 {
10939 USED_REX (REX_W);
10940 *obufp++ = 'q';
10941 }
10942 else if((address_mode == mode_64bit && need_modrm && cond)
10943 || (sizeflag & SUFFIX_ALWAYS))
10944 *obufp++ = intel_syntax? 'd' : 'l';
10945 }
10946 else
10947 abort ();
10948 break;
10949 case 'R':
10950 USED_REX (REX_W);
10951 if (rex & REX_W)
10952 *obufp++ = 'q';
10953 else if (sizeflag & DFLAG)
10954 {
10955 if (intel_syntax)
10956 *obufp++ = 'd';
10957 else
10958 *obufp++ = 'l';
10959 }
10960 else
10961 *obufp++ = 'w';
10962 if (intel_syntax && !p[1]
10963 && ((rex & REX_W) || (sizeflag & DFLAG)))
10964 *obufp++ = 'e';
10965 if (!(rex & REX_W))
10966 used_prefixes |= (prefixes & PREFIX_DATA);
10967 break;
10968 case 'V':
10969 if (l == 0)
10970 {
10971 if (intel_syntax)
10972 break;
10973 if (address_mode == mode_64bit
10974 && ((sizeflag & DFLAG) || (rex & REX_W)))
10975 {
10976 if (sizeflag & SUFFIX_ALWAYS)
10977 *obufp++ = 'q';
10978 break;
10979 }
10980 }
10981 else if (l == 1 && last[0] == 'L')
10982 {
10983 if (rex & REX_W)
10984 {
10985 *obufp++ = 'a';
10986 *obufp++ = 'b';
10987 *obufp++ = 's';
10988 }
10989 }
10990 else
10991 abort ();
10992 /* Fall through. */
10993 goto case_S;
10994 case 'S':
10995 if (l == 0)
10996 {
10997 case_S:
10998 if (intel_syntax)
10999 break;
11000 if (sizeflag & SUFFIX_ALWAYS)
11001 {
11002 if (rex & REX_W)
11003 *obufp++ = 'q';
11004 else
11005 {
11006 if (sizeflag & DFLAG)
11007 *obufp++ = 'l';
11008 else
11009 *obufp++ = 'w';
11010 used_prefixes |= (prefixes & PREFIX_DATA);
11011 }
11012 }
11013 }
11014 else if (l == 1 && last[0] == 'L')
11015 {
11016 if (address_mode == mode_64bit
11017 && !(prefixes & PREFIX_ADDR))
11018 {
11019 *obufp++ = 'a';
11020 *obufp++ = 'b';
11021 *obufp++ = 's';
11022 }
11023
11024 goto case_S;
11025 }
11026 else
11027 abort ();
11028 break;
11029 case 'X':
11030 if (l != 0)
11031 abort ();
11032 if (need_vex
11033 ? vex.prefix == DATA_PREFIX_OPCODE
11034 : prefixes & PREFIX_DATA)
11035 {
11036 *obufp++ = 'd';
11037 used_prefixes |= PREFIX_DATA;
11038 }
11039 else
11040 *obufp++ = 's';
11041 break;
11042 case 'Y':
11043 if (l == 1 && last[0] == 'X')
11044 {
11045 if (!need_vex)
11046 abort ();
11047 if (intel_syntax
11048 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
11049 break;
11050 switch (vex.length)
11051 {
11052 case 128:
11053 *obufp++ = 'x';
11054 break;
11055 case 256:
11056 *obufp++ = 'y';
11057 break;
11058 case 512:
11059 if (!vex.evex)
11060 default:
11061 abort ();
11062 }
11063 }
11064 else
11065 abort ();
11066 break;
11067 case 'W':
11068 if (l == 0)
11069 {
11070 /* operand size flag for cwtl, cbtw */
11071 USED_REX (REX_W);
11072 if (rex & REX_W)
11073 {
11074 if (intel_syntax)
11075 *obufp++ = 'd';
11076 else
11077 *obufp++ = 'l';
11078 }
11079 else if (sizeflag & DFLAG)
11080 *obufp++ = 'w';
11081 else
11082 *obufp++ = 'b';
11083 if (!(rex & REX_W))
11084 used_prefixes |= (prefixes & PREFIX_DATA);
11085 }
11086 else if (l == 1)
11087 {
11088 if (!need_vex)
11089 abort ();
11090 if (last[0] == 'X')
11091 *obufp++ = vex.w ? 'd': 's';
11092 else if (last[0] == 'B')
11093 *obufp++ = vex.w ? 'w': 'b';
11094 else
11095 abort ();
11096 }
11097 else
11098 abort ();
11099 break;
11100 case '^':
11101 if (intel_syntax)
11102 break;
11103 if (isa64 == intel64 && (rex & REX_W))
11104 {
11105 USED_REX (REX_W);
11106 *obufp++ = 'q';
11107 break;
11108 }
11109 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11110 {
11111 if (sizeflag & DFLAG)
11112 *obufp++ = 'l';
11113 else
11114 *obufp++ = 'w';
11115 used_prefixes |= (prefixes & PREFIX_DATA);
11116 }
11117 break;
11118 case '@':
11119 if (intel_syntax)
11120 break;
11121 if (address_mode == mode_64bit
11122 && (isa64 == intel64
11123 || ((sizeflag & DFLAG) || (rex & REX_W))))
11124 *obufp++ = 'q';
11125 else if ((prefixes & PREFIX_DATA))
11126 {
11127 if (!(sizeflag & DFLAG))
11128 *obufp++ = 'w';
11129 used_prefixes |= (prefixes & PREFIX_DATA);
11130 }
11131 break;
11132 }
11133
11134 if (len == l)
11135 len = l = 0;
11136 }
11137 *obufp = 0;
11138 mnemonicendp = obufp;
11139 return 0;
11140 }
11141
11142 static void
11143 oappend (const char *s)
11144 {
11145 obufp = stpcpy (obufp, s);
11146 }
11147
11148 static void
11149 append_seg (void)
11150 {
11151 /* Only print the active segment register. */
11152 if (!active_seg_prefix)
11153 return;
11154
11155 used_prefixes |= active_seg_prefix;
11156 switch (active_seg_prefix)
11157 {
11158 case PREFIX_CS:
11159 oappend_maybe_intel ("%cs:");
11160 break;
11161 case PREFIX_DS:
11162 oappend_maybe_intel ("%ds:");
11163 break;
11164 case PREFIX_SS:
11165 oappend_maybe_intel ("%ss:");
11166 break;
11167 case PREFIX_ES:
11168 oappend_maybe_intel ("%es:");
11169 break;
11170 case PREFIX_FS:
11171 oappend_maybe_intel ("%fs:");
11172 break;
11173 case PREFIX_GS:
11174 oappend_maybe_intel ("%gs:");
11175 break;
11176 default:
11177 break;
11178 }
11179 }
11180
11181 static void
11182 OP_indirE (int bytemode, int sizeflag)
11183 {
11184 if (!intel_syntax)
11185 oappend ("*");
11186 OP_E (bytemode, sizeflag);
11187 }
11188
11189 static void
11190 print_operand_value (char *buf, int hex, bfd_vma disp)
11191 {
11192 if (address_mode == mode_64bit)
11193 {
11194 if (hex)
11195 {
11196 char tmp[30];
11197 int i;
11198 buf[0] = '0';
11199 buf[1] = 'x';
11200 sprintf_vma (tmp, disp);
11201 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11202 strcpy (buf + 2, tmp + i);
11203 }
11204 else
11205 {
11206 bfd_signed_vma v = disp;
11207 char tmp[30];
11208 int i;
11209 if (v < 0)
11210 {
11211 *(buf++) = '-';
11212 v = -disp;
11213 /* Check for possible overflow on 0x8000000000000000. */
11214 if (v < 0)
11215 {
11216 strcpy (buf, "9223372036854775808");
11217 return;
11218 }
11219 }
11220 if (!v)
11221 {
11222 strcpy (buf, "0");
11223 return;
11224 }
11225
11226 i = 0;
11227 tmp[29] = 0;
11228 while (v)
11229 {
11230 tmp[28 - i] = (v % 10) + '0';
11231 v /= 10;
11232 i++;
11233 }
11234 strcpy (buf, tmp + 29 - i);
11235 }
11236 }
11237 else
11238 {
11239 if (hex)
11240 sprintf (buf, "0x%x", (unsigned int) disp);
11241 else
11242 sprintf (buf, "%d", (int) disp);
11243 }
11244 }
11245
11246 /* Put DISP in BUF as signed hex number. */
11247
11248 static void
11249 print_displacement (char *buf, bfd_vma disp)
11250 {
11251 bfd_signed_vma val = disp;
11252 char tmp[30];
11253 int i, j = 0;
11254
11255 if (val < 0)
11256 {
11257 buf[j++] = '-';
11258 val = -disp;
11259
11260 /* Check for possible overflow. */
11261 if (val < 0)
11262 {
11263 switch (address_mode)
11264 {
11265 case mode_64bit:
11266 strcpy (buf + j, "0x8000000000000000");
11267 break;
11268 case mode_32bit:
11269 strcpy (buf + j, "0x80000000");
11270 break;
11271 case mode_16bit:
11272 strcpy (buf + j, "0x8000");
11273 break;
11274 }
11275 return;
11276 }
11277 }
11278
11279 buf[j++] = '0';
11280 buf[j++] = 'x';
11281
11282 sprintf_vma (tmp, (bfd_vma) val);
11283 for (i = 0; tmp[i] == '0'; i++)
11284 continue;
11285 if (tmp[i] == '\0')
11286 i--;
11287 strcpy (buf + j, tmp + i);
11288 }
11289
11290 static void
11291 intel_operand_size (int bytemode, int sizeflag)
11292 {
11293 if (vex.evex
11294 && vex.b
11295 && (bytemode == x_mode
11296 || bytemode == evex_half_bcst_xmmq_mode))
11297 {
11298 if (vex.w)
11299 oappend ("QWORD PTR ");
11300 else
11301 oappend ("DWORD PTR ");
11302 return;
11303 }
11304 switch (bytemode)
11305 {
11306 case b_mode:
11307 case b_swap_mode:
11308 case dqb_mode:
11309 case db_mode:
11310 oappend ("BYTE PTR ");
11311 break;
11312 case w_mode:
11313 case dw_mode:
11314 case dqw_mode:
11315 oappend ("WORD PTR ");
11316 break;
11317 case indir_v_mode:
11318 if (address_mode == mode_64bit && isa64 == intel64)
11319 {
11320 oappend ("QWORD PTR ");
11321 break;
11322 }
11323 /* Fall through. */
11324 case stack_v_mode:
11325 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11326 {
11327 oappend ("QWORD PTR ");
11328 break;
11329 }
11330 /* Fall through. */
11331 case v_mode:
11332 case v_swap_mode:
11333 case dq_mode:
11334 USED_REX (REX_W);
11335 if (rex & REX_W)
11336 oappend ("QWORD PTR ");
11337 else
11338 {
11339 if ((sizeflag & DFLAG) || bytemode == dq_mode)
11340 oappend ("DWORD PTR ");
11341 else
11342 oappend ("WORD PTR ");
11343 used_prefixes |= (prefixes & PREFIX_DATA);
11344 }
11345 break;
11346 case z_mode:
11347 if ((rex & REX_W) || (sizeflag & DFLAG))
11348 *obufp++ = 'D';
11349 oappend ("WORD PTR ");
11350 if (!(rex & REX_W))
11351 used_prefixes |= (prefixes & PREFIX_DATA);
11352 break;
11353 case a_mode:
11354 if (sizeflag & DFLAG)
11355 oappend ("QWORD PTR ");
11356 else
11357 oappend ("DWORD PTR ");
11358 used_prefixes |= (prefixes & PREFIX_DATA);
11359 break;
11360 case movsxd_mode:
11361 if (!(sizeflag & DFLAG) && isa64 == intel64)
11362 oappend ("WORD PTR ");
11363 else
11364 oappend ("DWORD PTR ");
11365 used_prefixes |= (prefixes & PREFIX_DATA);
11366 break;
11367 case d_mode:
11368 case d_swap_mode:
11369 case dqd_mode:
11370 oappend ("DWORD PTR ");
11371 break;
11372 case q_mode:
11373 case q_swap_mode:
11374 oappend ("QWORD PTR ");
11375 break;
11376 case m_mode:
11377 if (address_mode == mode_64bit)
11378 oappend ("QWORD PTR ");
11379 else
11380 oappend ("DWORD PTR ");
11381 break;
11382 case f_mode:
11383 if (sizeflag & DFLAG)
11384 oappend ("FWORD PTR ");
11385 else
11386 oappend ("DWORD PTR ");
11387 used_prefixes |= (prefixes & PREFIX_DATA);
11388 break;
11389 case t_mode:
11390 oappend ("TBYTE PTR ");
11391 break;
11392 case x_mode:
11393 case x_swap_mode:
11394 case evex_x_gscat_mode:
11395 case evex_x_nobcst_mode:
11396 case bw_unit_mode:
11397 if (need_vex)
11398 {
11399 switch (vex.length)
11400 {
11401 case 128:
11402 oappend ("XMMWORD PTR ");
11403 break;
11404 case 256:
11405 oappend ("YMMWORD PTR ");
11406 break;
11407 case 512:
11408 oappend ("ZMMWORD PTR ");
11409 break;
11410 default:
11411 abort ();
11412 }
11413 }
11414 else
11415 oappend ("XMMWORD PTR ");
11416 break;
11417 case xmm_mode:
11418 oappend ("XMMWORD PTR ");
11419 break;
11420 case ymm_mode:
11421 oappend ("YMMWORD PTR ");
11422 break;
11423 case xmmq_mode:
11424 case evex_half_bcst_xmmq_mode:
11425 if (!need_vex)
11426 abort ();
11427
11428 switch (vex.length)
11429 {
11430 case 128:
11431 oappend ("QWORD PTR ");
11432 break;
11433 case 256:
11434 oappend ("XMMWORD PTR ");
11435 break;
11436 case 512:
11437 oappend ("YMMWORD PTR ");
11438 break;
11439 default:
11440 abort ();
11441 }
11442 break;
11443 case xmm_mb_mode:
11444 if (!need_vex)
11445 abort ();
11446
11447 switch (vex.length)
11448 {
11449 case 128:
11450 case 256:
11451 case 512:
11452 oappend ("BYTE PTR ");
11453 break;
11454 default:
11455 abort ();
11456 }
11457 break;
11458 case xmm_mw_mode:
11459 if (!need_vex)
11460 abort ();
11461
11462 switch (vex.length)
11463 {
11464 case 128:
11465 case 256:
11466 case 512:
11467 oappend ("WORD PTR ");
11468 break;
11469 default:
11470 abort ();
11471 }
11472 break;
11473 case xmm_md_mode:
11474 if (!need_vex)
11475 abort ();
11476
11477 switch (vex.length)
11478 {
11479 case 128:
11480 case 256:
11481 case 512:
11482 oappend ("DWORD PTR ");
11483 break;
11484 default:
11485 abort ();
11486 }
11487 break;
11488 case xmm_mq_mode:
11489 if (!need_vex)
11490 abort ();
11491
11492 switch (vex.length)
11493 {
11494 case 128:
11495 case 256:
11496 case 512:
11497 oappend ("QWORD PTR ");
11498 break;
11499 default:
11500 abort ();
11501 }
11502 break;
11503 case xmmdw_mode:
11504 if (!need_vex)
11505 abort ();
11506
11507 switch (vex.length)
11508 {
11509 case 128:
11510 oappend ("WORD PTR ");
11511 break;
11512 case 256:
11513 oappend ("DWORD PTR ");
11514 break;
11515 case 512:
11516 oappend ("QWORD PTR ");
11517 break;
11518 default:
11519 abort ();
11520 }
11521 break;
11522 case xmmqd_mode:
11523 if (!need_vex)
11524 abort ();
11525
11526 switch (vex.length)
11527 {
11528 case 128:
11529 oappend ("DWORD PTR ");
11530 break;
11531 case 256:
11532 oappend ("QWORD PTR ");
11533 break;
11534 case 512:
11535 oappend ("XMMWORD PTR ");
11536 break;
11537 default:
11538 abort ();
11539 }
11540 break;
11541 case ymmq_mode:
11542 if (!need_vex)
11543 abort ();
11544
11545 switch (vex.length)
11546 {
11547 case 128:
11548 oappend ("QWORD PTR ");
11549 break;
11550 case 256:
11551 oappend ("YMMWORD PTR ");
11552 break;
11553 case 512:
11554 oappend ("ZMMWORD PTR ");
11555 break;
11556 default:
11557 abort ();
11558 }
11559 break;
11560 case ymmxmm_mode:
11561 if (!need_vex)
11562 abort ();
11563
11564 switch (vex.length)
11565 {
11566 case 128:
11567 case 256:
11568 oappend ("XMMWORD PTR ");
11569 break;
11570 default:
11571 abort ();
11572 }
11573 break;
11574 case o_mode:
11575 oappend ("OWORD PTR ");
11576 break;
11577 case vex_scalar_w_dq_mode:
11578 if (!need_vex)
11579 abort ();
11580
11581 if (vex.w)
11582 oappend ("QWORD PTR ");
11583 else
11584 oappend ("DWORD PTR ");
11585 break;
11586 case vex_vsib_d_w_dq_mode:
11587 case vex_vsib_q_w_dq_mode:
11588 if (!need_vex)
11589 abort ();
11590
11591 if (!vex.evex)
11592 {
11593 if (vex.w)
11594 oappend ("QWORD PTR ");
11595 else
11596 oappend ("DWORD PTR ");
11597 }
11598 else
11599 {
11600 switch (vex.length)
11601 {
11602 case 128:
11603 oappend ("XMMWORD PTR ");
11604 break;
11605 case 256:
11606 oappend ("YMMWORD PTR ");
11607 break;
11608 case 512:
11609 oappend ("ZMMWORD PTR ");
11610 break;
11611 default:
11612 abort ();
11613 }
11614 }
11615 break;
11616 case vex_vsib_q_w_d_mode:
11617 case vex_vsib_d_w_d_mode:
11618 if (!need_vex || !vex.evex)
11619 abort ();
11620
11621 switch (vex.length)
11622 {
11623 case 128:
11624 oappend ("QWORD PTR ");
11625 break;
11626 case 256:
11627 oappend ("XMMWORD PTR ");
11628 break;
11629 case 512:
11630 oappend ("YMMWORD PTR ");
11631 break;
11632 default:
11633 abort ();
11634 }
11635
11636 break;
11637 case mask_bd_mode:
11638 if (!need_vex || vex.length != 128)
11639 abort ();
11640 if (vex.w)
11641 oappend ("DWORD PTR ");
11642 else
11643 oappend ("BYTE PTR ");
11644 break;
11645 case mask_mode:
11646 if (!need_vex)
11647 abort ();
11648 if (vex.w)
11649 oappend ("QWORD PTR ");
11650 else
11651 oappend ("WORD PTR ");
11652 break;
11653 case v_bnd_mode:
11654 case v_bndmk_mode:
11655 default:
11656 break;
11657 }
11658 }
11659
11660 static void
11661 OP_E_register (int bytemode, int sizeflag)
11662 {
11663 int reg = modrm.rm;
11664 const char **names;
11665
11666 USED_REX (REX_B);
11667 if ((rex & REX_B))
11668 reg += 8;
11669
11670 if ((sizeflag & SUFFIX_ALWAYS)
11671 && (bytemode == b_swap_mode
11672 || bytemode == bnd_swap_mode
11673 || bytemode == v_swap_mode))
11674 swap_operand ();
11675
11676 switch (bytemode)
11677 {
11678 case b_mode:
11679 case b_swap_mode:
11680 if (reg & 4)
11681 USED_REX (0);
11682 if (rex)
11683 names = names8rex;
11684 else
11685 names = names8;
11686 break;
11687 case w_mode:
11688 names = names16;
11689 break;
11690 case d_mode:
11691 case dw_mode:
11692 case db_mode:
11693 names = names32;
11694 break;
11695 case q_mode:
11696 names = names64;
11697 break;
11698 case m_mode:
11699 case v_bnd_mode:
11700 names = address_mode == mode_64bit ? names64 : names32;
11701 break;
11702 case bnd_mode:
11703 case bnd_swap_mode:
11704 if (reg > 0x3)
11705 {
11706 oappend ("(bad)");
11707 return;
11708 }
11709 names = names_bnd;
11710 break;
11711 case indir_v_mode:
11712 if (address_mode == mode_64bit && isa64 == intel64)
11713 {
11714 names = names64;
11715 break;
11716 }
11717 /* Fall through. */
11718 case stack_v_mode:
11719 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11720 {
11721 names = names64;
11722 break;
11723 }
11724 bytemode = v_mode;
11725 /* Fall through. */
11726 case v_mode:
11727 case v_swap_mode:
11728 case dq_mode:
11729 case dqb_mode:
11730 case dqd_mode:
11731 case dqw_mode:
11732 USED_REX (REX_W);
11733 if (rex & REX_W)
11734 names = names64;
11735 else
11736 {
11737 if ((sizeflag & DFLAG)
11738 || (bytemode != v_mode
11739 && bytemode != v_swap_mode))
11740 names = names32;
11741 else
11742 names = names16;
11743 used_prefixes |= (prefixes & PREFIX_DATA);
11744 }
11745 break;
11746 case movsxd_mode:
11747 if (!(sizeflag & DFLAG) && isa64 == intel64)
11748 names = names16;
11749 else
11750 names = names32;
11751 used_prefixes |= (prefixes & PREFIX_DATA);
11752 break;
11753 case va_mode:
11754 names = (address_mode == mode_64bit
11755 ? names64 : names32);
11756 if (!(prefixes & PREFIX_ADDR))
11757 names = (address_mode == mode_16bit
11758 ? names16 : names);
11759 else
11760 {
11761 /* Remove "addr16/addr32". */
11762 all_prefixes[last_addr_prefix] = 0;
11763 names = (address_mode != mode_32bit
11764 ? names32 : names16);
11765 used_prefixes |= PREFIX_ADDR;
11766 }
11767 break;
11768 case mask_bd_mode:
11769 case mask_mode:
11770 if (reg > 0x7)
11771 {
11772 oappend ("(bad)");
11773 return;
11774 }
11775 names = names_mask;
11776 break;
11777 case 0:
11778 return;
11779 default:
11780 oappend (INTERNAL_DISASSEMBLER_ERROR);
11781 return;
11782 }
11783 oappend (names[reg]);
11784 }
11785
11786 static void
11787 OP_E_memory (int bytemode, int sizeflag)
11788 {
11789 bfd_vma disp = 0;
11790 int add = (rex & REX_B) ? 8 : 0;
11791 int riprel = 0;
11792 int shift;
11793
11794 if (vex.evex)
11795 {
11796 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
11797 if (vex.b
11798 && bytemode != x_mode
11799 && bytemode != xmmq_mode
11800 && bytemode != evex_half_bcst_xmmq_mode)
11801 {
11802 BadOp ();
11803 return;
11804 }
11805 switch (bytemode)
11806 {
11807 case dqw_mode:
11808 case dw_mode:
11809 case xmm_mw_mode:
11810 shift = 1;
11811 break;
11812 case dqb_mode:
11813 case db_mode:
11814 case xmm_mb_mode:
11815 shift = 0;
11816 break;
11817 case dq_mode:
11818 if (address_mode != mode_64bit)
11819 {
11820 case dqd_mode:
11821 case xmm_md_mode:
11822 case d_mode:
11823 case d_swap_mode:
11824 shift = 2;
11825 break;
11826 }
11827 /* fall through */
11828 case vex_scalar_w_dq_mode:
11829 case vex_vsib_d_w_dq_mode:
11830 case vex_vsib_d_w_d_mode:
11831 case vex_vsib_q_w_dq_mode:
11832 case vex_vsib_q_w_d_mode:
11833 case evex_x_gscat_mode:
11834 shift = vex.w ? 3 : 2;
11835 break;
11836 case x_mode:
11837 case evex_half_bcst_xmmq_mode:
11838 case xmmq_mode:
11839 if (vex.b)
11840 {
11841 shift = vex.w ? 3 : 2;
11842 break;
11843 }
11844 /* Fall through. */
11845 case xmmqd_mode:
11846 case xmmdw_mode:
11847 case ymmq_mode:
11848 case evex_x_nobcst_mode:
11849 case x_swap_mode:
11850 switch (vex.length)
11851 {
11852 case 128:
11853 shift = 4;
11854 break;
11855 case 256:
11856 shift = 5;
11857 break;
11858 case 512:
11859 shift = 6;
11860 break;
11861 default:
11862 abort ();
11863 }
11864 /* Make necessary corrections to shift for modes that need it. */
11865 if (bytemode == xmmq_mode
11866 || bytemode == evex_half_bcst_xmmq_mode
11867 || (bytemode == ymmq_mode && vex.length == 128))
11868 shift -= 1;
11869 else if (bytemode == xmmqd_mode)
11870 shift -= 2;
11871 else if (bytemode == xmmdw_mode)
11872 shift -= 3;
11873 break;
11874 case ymm_mode:
11875 shift = 5;
11876 break;
11877 case xmm_mode:
11878 shift = 4;
11879 break;
11880 case xmm_mq_mode:
11881 case q_mode:
11882 case q_swap_mode:
11883 shift = 3;
11884 break;
11885 case bw_unit_mode:
11886 shift = vex.w ? 1 : 0;
11887 break;
11888 default:
11889 abort ();
11890 }
11891 }
11892 else
11893 shift = 0;
11894
11895 USED_REX (REX_B);
11896 if (intel_syntax)
11897 intel_operand_size (bytemode, sizeflag);
11898 append_seg ();
11899
11900 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11901 {
11902 /* 32/64 bit address mode */
11903 int havedisp;
11904 int havesib;
11905 int havebase;
11906 int haveindex;
11907 int needindex;
11908 int needaddr32;
11909 int base, rbase;
11910 int vindex = 0;
11911 int scale = 0;
11912 int addr32flag = !((sizeflag & AFLAG)
11913 || bytemode == v_bnd_mode
11914 || bytemode == v_bndmk_mode
11915 || bytemode == bnd_mode
11916 || bytemode == bnd_swap_mode);
11917 const char **indexes64 = names64;
11918 const char **indexes32 = names32;
11919
11920 havesib = 0;
11921 havebase = 1;
11922 haveindex = 0;
11923 base = modrm.rm;
11924
11925 if (base == 4)
11926 {
11927 havesib = 1;
11928 vindex = sib.index;
11929 USED_REX (REX_X);
11930 if (rex & REX_X)
11931 vindex += 8;
11932 switch (bytemode)
11933 {
11934 case vex_vsib_d_w_dq_mode:
11935 case vex_vsib_d_w_d_mode:
11936 case vex_vsib_q_w_dq_mode:
11937 case vex_vsib_q_w_d_mode:
11938 if (!need_vex)
11939 abort ();
11940 if (vex.evex)
11941 {
11942 if (!vex.v)
11943 vindex += 16;
11944 }
11945
11946 haveindex = 1;
11947 switch (vex.length)
11948 {
11949 case 128:
11950 indexes64 = indexes32 = names_xmm;
11951 break;
11952 case 256:
11953 if (!vex.w
11954 || bytemode == vex_vsib_q_w_dq_mode
11955 || bytemode == vex_vsib_q_w_d_mode)
11956 indexes64 = indexes32 = names_ymm;
11957 else
11958 indexes64 = indexes32 = names_xmm;
11959 break;
11960 case 512:
11961 if (!vex.w
11962 || bytemode == vex_vsib_q_w_dq_mode
11963 || bytemode == vex_vsib_q_w_d_mode)
11964 indexes64 = indexes32 = names_zmm;
11965 else
11966 indexes64 = indexes32 = names_ymm;
11967 break;
11968 default:
11969 abort ();
11970 }
11971 break;
11972 default:
11973 haveindex = vindex != 4;
11974 break;
11975 }
11976 scale = sib.scale;
11977 base = sib.base;
11978 codep++;
11979 }
11980 else
11981 {
11982 /* mandatory non-vector SIB must have sib */
11983 if (bytemode == vex_sibmem_mode)
11984 {
11985 oappend ("(bad)");
11986 return;
11987 }
11988 }
11989 rbase = base + add;
11990
11991 switch (modrm.mod)
11992 {
11993 case 0:
11994 if (base == 5)
11995 {
11996 havebase = 0;
11997 if (address_mode == mode_64bit && !havesib)
11998 riprel = 1;
11999 disp = get32s ();
12000 if (riprel && bytemode == v_bndmk_mode)
12001 {
12002 oappend ("(bad)");
12003 return;
12004 }
12005 }
12006 break;
12007 case 1:
12008 FETCH_DATA (the_info, codep + 1);
12009 disp = *codep++;
12010 if ((disp & 0x80) != 0)
12011 disp -= 0x100;
12012 if (vex.evex && shift > 0)
12013 disp <<= shift;
12014 break;
12015 case 2:
12016 disp = get32s ();
12017 break;
12018 }
12019
12020 needindex = 0;
12021 needaddr32 = 0;
12022 if (havesib
12023 && !havebase
12024 && !haveindex
12025 && address_mode != mode_16bit)
12026 {
12027 if (address_mode == mode_64bit)
12028 {
12029 /* Display eiz instead of addr32. */
12030 needindex = addr32flag;
12031 needaddr32 = 1;
12032 }
12033 else
12034 {
12035 /* In 32-bit mode, we need index register to tell [offset]
12036 from [eiz*1 + offset]. */
12037 needindex = 1;
12038 }
12039 }
12040
12041 havedisp = (havebase
12042 || needindex
12043 || (havesib && (haveindex || scale != 0)));
12044
12045 if (!intel_syntax)
12046 if (modrm.mod != 0 || base == 5)
12047 {
12048 if (havedisp || riprel)
12049 print_displacement (scratchbuf, disp);
12050 else
12051 print_operand_value (scratchbuf, 1, disp);
12052 oappend (scratchbuf);
12053 if (riprel)
12054 {
12055 set_op (disp, 1);
12056 oappend (!addr32flag ? "(%rip)" : "(%eip)");
12057 }
12058 }
12059
12060 if ((havebase || haveindex || needindex || needaddr32 || riprel)
12061 && (address_mode != mode_64bit
12062 || ((bytemode != v_bnd_mode)
12063 && (bytemode != v_bndmk_mode)
12064 && (bytemode != bnd_mode)
12065 && (bytemode != bnd_swap_mode))))
12066 used_prefixes |= PREFIX_ADDR;
12067
12068 if (havedisp || (intel_syntax && riprel))
12069 {
12070 *obufp++ = open_char;
12071 if (intel_syntax && riprel)
12072 {
12073 set_op (disp, 1);
12074 oappend (!addr32flag ? "rip" : "eip");
12075 }
12076 *obufp = '\0';
12077 if (havebase)
12078 oappend (address_mode == mode_64bit && !addr32flag
12079 ? names64[rbase] : names32[rbase]);
12080 if (havesib)
12081 {
12082 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
12083 print index to tell base + index from base. */
12084 if (scale != 0
12085 || needindex
12086 || haveindex
12087 || (havebase && base != ESP_REG_NUM))
12088 {
12089 if (!intel_syntax || havebase)
12090 {
12091 *obufp++ = separator_char;
12092 *obufp = '\0';
12093 }
12094 if (haveindex)
12095 oappend (address_mode == mode_64bit && !addr32flag
12096 ? indexes64[vindex] : indexes32[vindex]);
12097 else
12098 oappend (address_mode == mode_64bit && !addr32flag
12099 ? index64 : index32);
12100
12101 *obufp++ = scale_char;
12102 *obufp = '\0';
12103 sprintf (scratchbuf, "%d", 1 << scale);
12104 oappend (scratchbuf);
12105 }
12106 }
12107 if (intel_syntax
12108 && (disp || modrm.mod != 0 || base == 5))
12109 {
12110 if (!havedisp || (bfd_signed_vma) disp >= 0)
12111 {
12112 *obufp++ = '+';
12113 *obufp = '\0';
12114 }
12115 else if (modrm.mod != 1 && disp != -disp)
12116 {
12117 *obufp++ = '-';
12118 *obufp = '\0';
12119 disp = - (bfd_signed_vma) disp;
12120 }
12121
12122 if (havedisp)
12123 print_displacement (scratchbuf, disp);
12124 else
12125 print_operand_value (scratchbuf, 1, disp);
12126 oappend (scratchbuf);
12127 }
12128
12129 *obufp++ = close_char;
12130 *obufp = '\0';
12131 }
12132 else if (intel_syntax)
12133 {
12134 if (modrm.mod != 0 || base == 5)
12135 {
12136 if (!active_seg_prefix)
12137 {
12138 oappend (names_seg[ds_reg - es_reg]);
12139 oappend (":");
12140 }
12141 print_operand_value (scratchbuf, 1, disp);
12142 oappend (scratchbuf);
12143 }
12144 }
12145 }
12146 else if (bytemode == v_bnd_mode
12147 || bytemode == v_bndmk_mode
12148 || bytemode == bnd_mode
12149 || bytemode == bnd_swap_mode)
12150 {
12151 oappend ("(bad)");
12152 return;
12153 }
12154 else
12155 {
12156 /* 16 bit address mode */
12157 used_prefixes |= prefixes & PREFIX_ADDR;
12158 switch (modrm.mod)
12159 {
12160 case 0:
12161 if (modrm.rm == 6)
12162 {
12163 disp = get16 ();
12164 if ((disp & 0x8000) != 0)
12165 disp -= 0x10000;
12166 }
12167 break;
12168 case 1:
12169 FETCH_DATA (the_info, codep + 1);
12170 disp = *codep++;
12171 if ((disp & 0x80) != 0)
12172 disp -= 0x100;
12173 if (vex.evex && shift > 0)
12174 disp <<= shift;
12175 break;
12176 case 2:
12177 disp = get16 ();
12178 if ((disp & 0x8000) != 0)
12179 disp -= 0x10000;
12180 break;
12181 }
12182
12183 if (!intel_syntax)
12184 if (modrm.mod != 0 || modrm.rm == 6)
12185 {
12186 print_displacement (scratchbuf, disp);
12187 oappend (scratchbuf);
12188 }
12189
12190 if (modrm.mod != 0 || modrm.rm != 6)
12191 {
12192 *obufp++ = open_char;
12193 *obufp = '\0';
12194 oappend (index16[modrm.rm]);
12195 if (intel_syntax
12196 && (disp || modrm.mod != 0 || modrm.rm == 6))
12197 {
12198 if ((bfd_signed_vma) disp >= 0)
12199 {
12200 *obufp++ = '+';
12201 *obufp = '\0';
12202 }
12203 else if (modrm.mod != 1)
12204 {
12205 *obufp++ = '-';
12206 *obufp = '\0';
12207 disp = - (bfd_signed_vma) disp;
12208 }
12209
12210 print_displacement (scratchbuf, disp);
12211 oappend (scratchbuf);
12212 }
12213
12214 *obufp++ = close_char;
12215 *obufp = '\0';
12216 }
12217 else if (intel_syntax)
12218 {
12219 if (!active_seg_prefix)
12220 {
12221 oappend (names_seg[ds_reg - es_reg]);
12222 oappend (":");
12223 }
12224 print_operand_value (scratchbuf, 1, disp & 0xffff);
12225 oappend (scratchbuf);
12226 }
12227 }
12228 if (vex.evex && vex.b
12229 && (bytemode == x_mode
12230 || bytemode == xmmq_mode
12231 || bytemode == evex_half_bcst_xmmq_mode))
12232 {
12233 if (vex.w
12234 || bytemode == xmmq_mode
12235 || bytemode == evex_half_bcst_xmmq_mode)
12236 {
12237 switch (vex.length)
12238 {
12239 case 128:
12240 oappend ("{1to2}");
12241 break;
12242 case 256:
12243 oappend ("{1to4}");
12244 break;
12245 case 512:
12246 oappend ("{1to8}");
12247 break;
12248 default:
12249 abort ();
12250 }
12251 }
12252 else
12253 {
12254 switch (vex.length)
12255 {
12256 case 128:
12257 oappend ("{1to4}");
12258 break;
12259 case 256:
12260 oappend ("{1to8}");
12261 break;
12262 case 512:
12263 oappend ("{1to16}");
12264 break;
12265 default:
12266 abort ();
12267 }
12268 }
12269 }
12270 }
12271
12272 static void
12273 OP_E (int bytemode, int sizeflag)
12274 {
12275 /* Skip mod/rm byte. */
12276 MODRM_CHECK;
12277 codep++;
12278
12279 if (modrm.mod == 3)
12280 OP_E_register (bytemode, sizeflag);
12281 else
12282 OP_E_memory (bytemode, sizeflag);
12283 }
12284
12285 static void
12286 OP_G (int bytemode, int sizeflag)
12287 {
12288 int add = 0;
12289 const char **names;
12290 USED_REX (REX_R);
12291 if (rex & REX_R)
12292 add += 8;
12293 switch (bytemode)
12294 {
12295 case b_mode:
12296 if (modrm.reg & 4)
12297 USED_REX (0);
12298 if (rex)
12299 oappend (names8rex[modrm.reg + add]);
12300 else
12301 oappend (names8[modrm.reg + add]);
12302 break;
12303 case w_mode:
12304 oappend (names16[modrm.reg + add]);
12305 break;
12306 case d_mode:
12307 case db_mode:
12308 case dw_mode:
12309 oappend (names32[modrm.reg + add]);
12310 break;
12311 case q_mode:
12312 oappend (names64[modrm.reg + add]);
12313 break;
12314 case bnd_mode:
12315 if (modrm.reg > 0x3)
12316 {
12317 oappend ("(bad)");
12318 return;
12319 }
12320 oappend (names_bnd[modrm.reg]);
12321 break;
12322 case v_mode:
12323 case dq_mode:
12324 case dqb_mode:
12325 case dqd_mode:
12326 case dqw_mode:
12327 case movsxd_mode:
12328 USED_REX (REX_W);
12329 if (rex & REX_W)
12330 oappend (names64[modrm.reg + add]);
12331 else
12332 {
12333 if ((sizeflag & DFLAG)
12334 || (bytemode != v_mode && bytemode != movsxd_mode))
12335 oappend (names32[modrm.reg + add]);
12336 else
12337 oappend (names16[modrm.reg + add]);
12338 used_prefixes |= (prefixes & PREFIX_DATA);
12339 }
12340 break;
12341 case va_mode:
12342 names = (address_mode == mode_64bit
12343 ? names64 : names32);
12344 if (!(prefixes & PREFIX_ADDR))
12345 {
12346 if (address_mode == mode_16bit)
12347 names = names16;
12348 }
12349 else
12350 {
12351 /* Remove "addr16/addr32". */
12352 all_prefixes[last_addr_prefix] = 0;
12353 names = (address_mode != mode_32bit
12354 ? names32 : names16);
12355 used_prefixes |= PREFIX_ADDR;
12356 }
12357 oappend (names[modrm.reg + add]);
12358 break;
12359 case m_mode:
12360 if (address_mode == mode_64bit)
12361 oappend (names64[modrm.reg + add]);
12362 else
12363 oappend (names32[modrm.reg + add]);
12364 break;
12365 case mask_bd_mode:
12366 case mask_mode:
12367 if ((modrm.reg + add) > 0x7)
12368 {
12369 oappend ("(bad)");
12370 return;
12371 }
12372 oappend (names_mask[modrm.reg + add]);
12373 break;
12374 default:
12375 oappend (INTERNAL_DISASSEMBLER_ERROR);
12376 break;
12377 }
12378 }
12379
12380 static bfd_vma
12381 get64 (void)
12382 {
12383 bfd_vma x;
12384 #ifdef BFD64
12385 unsigned int a;
12386 unsigned int b;
12387
12388 FETCH_DATA (the_info, codep + 8);
12389 a = *codep++ & 0xff;
12390 a |= (*codep++ & 0xff) << 8;
12391 a |= (*codep++ & 0xff) << 16;
12392 a |= (*codep++ & 0xffu) << 24;
12393 b = *codep++ & 0xff;
12394 b |= (*codep++ & 0xff) << 8;
12395 b |= (*codep++ & 0xff) << 16;
12396 b |= (*codep++ & 0xffu) << 24;
12397 x = a + ((bfd_vma) b << 32);
12398 #else
12399 abort ();
12400 x = 0;
12401 #endif
12402 return x;
12403 }
12404
12405 static bfd_signed_vma
12406 get32 (void)
12407 {
12408 bfd_signed_vma x = 0;
12409
12410 FETCH_DATA (the_info, codep + 4);
12411 x = *codep++ & (bfd_signed_vma) 0xff;
12412 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12413 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12414 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12415 return x;
12416 }
12417
12418 static bfd_signed_vma
12419 get32s (void)
12420 {
12421 bfd_signed_vma x = 0;
12422
12423 FETCH_DATA (the_info, codep + 4);
12424 x = *codep++ & (bfd_signed_vma) 0xff;
12425 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12426 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12427 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12428
12429 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
12430
12431 return x;
12432 }
12433
12434 static int
12435 get16 (void)
12436 {
12437 int x = 0;
12438
12439 FETCH_DATA (the_info, codep + 2);
12440 x = *codep++ & 0xff;
12441 x |= (*codep++ & 0xff) << 8;
12442 return x;
12443 }
12444
12445 static void
12446 set_op (bfd_vma op, int riprel)
12447 {
12448 op_index[op_ad] = op_ad;
12449 if (address_mode == mode_64bit)
12450 {
12451 op_address[op_ad] = op;
12452 op_riprel[op_ad] = riprel;
12453 }
12454 else
12455 {
12456 /* Mask to get a 32-bit address. */
12457 op_address[op_ad] = op & 0xffffffff;
12458 op_riprel[op_ad] = riprel & 0xffffffff;
12459 }
12460 }
12461
12462 static void
12463 OP_REG (int code, int sizeflag)
12464 {
12465 const char *s;
12466 int add;
12467
12468 switch (code)
12469 {
12470 case es_reg: case ss_reg: case cs_reg:
12471 case ds_reg: case fs_reg: case gs_reg:
12472 oappend (names_seg[code - es_reg]);
12473 return;
12474 }
12475
12476 USED_REX (REX_B);
12477 if (rex & REX_B)
12478 add = 8;
12479 else
12480 add = 0;
12481
12482 switch (code)
12483 {
12484 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12485 case sp_reg: case bp_reg: case si_reg: case di_reg:
12486 s = names16[code - ax_reg + add];
12487 break;
12488 case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12489 USED_REX (0);
12490 /* Fall through. */
12491 case al_reg: case cl_reg: case dl_reg: case bl_reg:
12492 if (rex)
12493 s = names8rex[code - al_reg + add];
12494 else
12495 s = names8[code - al_reg];
12496 break;
12497 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12498 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12499 if (address_mode == mode_64bit
12500 && ((sizeflag & DFLAG) || (rex & REX_W)))
12501 {
12502 s = names64[code - rAX_reg + add];
12503 break;
12504 }
12505 code += eAX_reg - rAX_reg;
12506 /* Fall through. */
12507 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12508 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12509 USED_REX (REX_W);
12510 if (rex & REX_W)
12511 s = names64[code - eAX_reg + add];
12512 else
12513 {
12514 if (sizeflag & DFLAG)
12515 s = names32[code - eAX_reg + add];
12516 else
12517 s = names16[code - eAX_reg + add];
12518 used_prefixes |= (prefixes & PREFIX_DATA);
12519 }
12520 break;
12521 default:
12522 s = INTERNAL_DISASSEMBLER_ERROR;
12523 break;
12524 }
12525 oappend (s);
12526 }
12527
12528 static void
12529 OP_IMREG (int code, int sizeflag)
12530 {
12531 const char *s;
12532
12533 switch (code)
12534 {
12535 case indir_dx_reg:
12536 if (intel_syntax)
12537 s = "dx";
12538 else
12539 s = "(%dx)";
12540 break;
12541 case al_reg: case cl_reg:
12542 s = names8[code - al_reg];
12543 break;
12544 case eAX_reg:
12545 USED_REX (REX_W);
12546 if (rex & REX_W)
12547 {
12548 s = *names64;
12549 break;
12550 }
12551 /* Fall through. */
12552 case z_mode_ax_reg:
12553 if ((rex & REX_W) || (sizeflag & DFLAG))
12554 s = *names32;
12555 else
12556 s = *names16;
12557 if (!(rex & REX_W))
12558 used_prefixes |= (prefixes & PREFIX_DATA);
12559 break;
12560 default:
12561 s = INTERNAL_DISASSEMBLER_ERROR;
12562 break;
12563 }
12564 oappend (s);
12565 }
12566
12567 static void
12568 OP_I (int bytemode, int sizeflag)
12569 {
12570 bfd_signed_vma op;
12571 bfd_signed_vma mask = -1;
12572
12573 switch (bytemode)
12574 {
12575 case b_mode:
12576 FETCH_DATA (the_info, codep + 1);
12577 op = *codep++;
12578 mask = 0xff;
12579 break;
12580 case v_mode:
12581 USED_REX (REX_W);
12582 if (rex & REX_W)
12583 op = get32s ();
12584 else
12585 {
12586 if (sizeflag & DFLAG)
12587 {
12588 op = get32 ();
12589 mask = 0xffffffff;
12590 }
12591 else
12592 {
12593 op = get16 ();
12594 mask = 0xfffff;
12595 }
12596 used_prefixes |= (prefixes & PREFIX_DATA);
12597 }
12598 break;
12599 case d_mode:
12600 mask = 0xffffffff;
12601 op = get32 ();
12602 break;
12603 case w_mode:
12604 mask = 0xfffff;
12605 op = get16 ();
12606 break;
12607 case const_1_mode:
12608 if (intel_syntax)
12609 oappend ("1");
12610 return;
12611 default:
12612 oappend (INTERNAL_DISASSEMBLER_ERROR);
12613 return;
12614 }
12615
12616 op &= mask;
12617 scratchbuf[0] = '$';
12618 print_operand_value (scratchbuf + 1, 1, op);
12619 oappend_maybe_intel (scratchbuf);
12620 scratchbuf[0] = '\0';
12621 }
12622
12623 static void
12624 OP_I64 (int bytemode, int sizeflag)
12625 {
12626 if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
12627 {
12628 OP_I (bytemode, sizeflag);
12629 return;
12630 }
12631
12632 USED_REX (REX_W);
12633
12634 scratchbuf[0] = '$';
12635 print_operand_value (scratchbuf + 1, 1, get64 ());
12636 oappend_maybe_intel (scratchbuf);
12637 scratchbuf[0] = '\0';
12638 }
12639
12640 static void
12641 OP_sI (int bytemode, int sizeflag)
12642 {
12643 bfd_signed_vma op;
12644
12645 switch (bytemode)
12646 {
12647 case b_mode:
12648 case b_T_mode:
12649 FETCH_DATA (the_info, codep + 1);
12650 op = *codep++;
12651 if ((op & 0x80) != 0)
12652 op -= 0x100;
12653 if (bytemode == b_T_mode)
12654 {
12655 if (address_mode != mode_64bit
12656 || !((sizeflag & DFLAG) || (rex & REX_W)))
12657 {
12658 /* The operand-size prefix is overridden by a REX prefix. */
12659 if ((sizeflag & DFLAG) || (rex & REX_W))
12660 op &= 0xffffffff;
12661 else
12662 op &= 0xffff;
12663 }
12664 }
12665 else
12666 {
12667 if (!(rex & REX_W))
12668 {
12669 if (sizeflag & DFLAG)
12670 op &= 0xffffffff;
12671 else
12672 op &= 0xffff;
12673 }
12674 }
12675 break;
12676 case v_mode:
12677 /* The operand-size prefix is overridden by a REX prefix. */
12678 if ((sizeflag & DFLAG) || (rex & REX_W))
12679 op = get32s ();
12680 else
12681 op = get16 ();
12682 break;
12683 default:
12684 oappend (INTERNAL_DISASSEMBLER_ERROR);
12685 return;
12686 }
12687
12688 scratchbuf[0] = '$';
12689 print_operand_value (scratchbuf + 1, 1, op);
12690 oappend_maybe_intel (scratchbuf);
12691 }
12692
12693 static void
12694 OP_J (int bytemode, int sizeflag)
12695 {
12696 bfd_vma disp;
12697 bfd_vma mask = -1;
12698 bfd_vma segment = 0;
12699
12700 switch (bytemode)
12701 {
12702 case b_mode:
12703 FETCH_DATA (the_info, codep + 1);
12704 disp = *codep++;
12705 if ((disp & 0x80) != 0)
12706 disp -= 0x100;
12707 break;
12708 case v_mode:
12709 if (isa64 != intel64)
12710 case dqw_mode:
12711 USED_REX (REX_W);
12712 if ((sizeflag & DFLAG)
12713 || (address_mode == mode_64bit
12714 && ((isa64 == intel64 && bytemode != dqw_mode)
12715 || (rex & REX_W))))
12716 disp = get32s ();
12717 else
12718 {
12719 disp = get16 ();
12720 if ((disp & 0x8000) != 0)
12721 disp -= 0x10000;
12722 /* In 16bit mode, address is wrapped around at 64k within
12723 the same segment. Otherwise, a data16 prefix on a jump
12724 instruction means that the pc is masked to 16 bits after
12725 the displacement is added! */
12726 mask = 0xffff;
12727 if ((prefixes & PREFIX_DATA) == 0)
12728 segment = ((start_pc + (codep - start_codep))
12729 & ~((bfd_vma) 0xffff));
12730 }
12731 if (address_mode != mode_64bit
12732 || (isa64 != intel64 && !(rex & REX_W)))
12733 used_prefixes |= (prefixes & PREFIX_DATA);
12734 break;
12735 default:
12736 oappend (INTERNAL_DISASSEMBLER_ERROR);
12737 return;
12738 }
12739 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
12740 set_op (disp, 0);
12741 print_operand_value (scratchbuf, 1, disp);
12742 oappend (scratchbuf);
12743 }
12744
12745 static void
12746 OP_SEG (int bytemode, int sizeflag)
12747 {
12748 if (bytemode == w_mode)
12749 oappend (names_seg[modrm.reg]);
12750 else
12751 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12752 }
12753
12754 static void
12755 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12756 {
12757 int seg, offset;
12758
12759 if (sizeflag & DFLAG)
12760 {
12761 offset = get32 ();
12762 seg = get16 ();
12763 }
12764 else
12765 {
12766 offset = get16 ();
12767 seg = get16 ();
12768 }
12769 used_prefixes |= (prefixes & PREFIX_DATA);
12770 if (intel_syntax)
12771 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12772 else
12773 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12774 oappend (scratchbuf);
12775 }
12776
12777 static void
12778 OP_OFF (int bytemode, int sizeflag)
12779 {
12780 bfd_vma off;
12781
12782 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12783 intel_operand_size (bytemode, sizeflag);
12784 append_seg ();
12785
12786 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12787 off = get32 ();
12788 else
12789 off = get16 ();
12790
12791 if (intel_syntax)
12792 {
12793 if (!active_seg_prefix)
12794 {
12795 oappend (names_seg[ds_reg - es_reg]);
12796 oappend (":");
12797 }
12798 }
12799 print_operand_value (scratchbuf, 1, off);
12800 oappend (scratchbuf);
12801 }
12802
12803 static void
12804 OP_OFF64 (int bytemode, int sizeflag)
12805 {
12806 bfd_vma off;
12807
12808 if (address_mode != mode_64bit
12809 || (prefixes & PREFIX_ADDR))
12810 {
12811 OP_OFF (bytemode, sizeflag);
12812 return;
12813 }
12814
12815 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12816 intel_operand_size (bytemode, sizeflag);
12817 append_seg ();
12818
12819 off = get64 ();
12820
12821 if (intel_syntax)
12822 {
12823 if (!active_seg_prefix)
12824 {
12825 oappend (names_seg[ds_reg - es_reg]);
12826 oappend (":");
12827 }
12828 }
12829 print_operand_value (scratchbuf, 1, off);
12830 oappend (scratchbuf);
12831 }
12832
12833 static void
12834 ptr_reg (int code, int sizeflag)
12835 {
12836 const char *s;
12837
12838 *obufp++ = open_char;
12839 used_prefixes |= (prefixes & PREFIX_ADDR);
12840 if (address_mode == mode_64bit)
12841 {
12842 if (!(sizeflag & AFLAG))
12843 s = names32[code - eAX_reg];
12844 else
12845 s = names64[code - eAX_reg];
12846 }
12847 else if (sizeflag & AFLAG)
12848 s = names32[code - eAX_reg];
12849 else
12850 s = names16[code - eAX_reg];
12851 oappend (s);
12852 *obufp++ = close_char;
12853 *obufp = 0;
12854 }
12855
12856 static void
12857 OP_ESreg (int code, int sizeflag)
12858 {
12859 if (intel_syntax)
12860 {
12861 switch (codep[-1])
12862 {
12863 case 0x6d: /* insw/insl */
12864 intel_operand_size (z_mode, sizeflag);
12865 break;
12866 case 0xa5: /* movsw/movsl/movsq */
12867 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12868 case 0xab: /* stosw/stosl */
12869 case 0xaf: /* scasw/scasl */
12870 intel_operand_size (v_mode, sizeflag);
12871 break;
12872 default:
12873 intel_operand_size (b_mode, sizeflag);
12874 }
12875 }
12876 oappend_maybe_intel ("%es:");
12877 ptr_reg (code, sizeflag);
12878 }
12879
12880 static void
12881 OP_DSreg (int code, int sizeflag)
12882 {
12883 if (intel_syntax)
12884 {
12885 switch (codep[-1])
12886 {
12887 case 0x6f: /* outsw/outsl */
12888 intel_operand_size (z_mode, sizeflag);
12889 break;
12890 case 0xa5: /* movsw/movsl/movsq */
12891 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12892 case 0xad: /* lodsw/lodsl/lodsq */
12893 intel_operand_size (v_mode, sizeflag);
12894 break;
12895 default:
12896 intel_operand_size (b_mode, sizeflag);
12897 }
12898 }
12899 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12900 default segment register DS is printed. */
12901 if (!active_seg_prefix)
12902 active_seg_prefix = PREFIX_DS;
12903 append_seg ();
12904 ptr_reg (code, sizeflag);
12905 }
12906
12907 static void
12908 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12909 {
12910 int add;
12911 if (rex & REX_R)
12912 {
12913 USED_REX (REX_R);
12914 add = 8;
12915 }
12916 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12917 {
12918 all_prefixes[last_lock_prefix] = 0;
12919 used_prefixes |= PREFIX_LOCK;
12920 add = 8;
12921 }
12922 else
12923 add = 0;
12924 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12925 oappend_maybe_intel (scratchbuf);
12926 }
12927
12928 static void
12929 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12930 {
12931 int add;
12932 USED_REX (REX_R);
12933 if (rex & REX_R)
12934 add = 8;
12935 else
12936 add = 0;
12937 if (intel_syntax)
12938 sprintf (scratchbuf, "db%d", modrm.reg + add);
12939 else
12940 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12941 oappend (scratchbuf);
12942 }
12943
12944 static void
12945 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12946 {
12947 sprintf (scratchbuf, "%%tr%d", modrm.reg);
12948 oappend_maybe_intel (scratchbuf);
12949 }
12950
12951 static void
12952 OP_R (int bytemode, int sizeflag)
12953 {
12954 /* Skip mod/rm byte. */
12955 MODRM_CHECK;
12956 codep++;
12957 OP_E_register (bytemode, sizeflag);
12958 }
12959
12960 static void
12961 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12962 {
12963 int reg = modrm.reg;
12964 const char **names;
12965
12966 used_prefixes |= (prefixes & PREFIX_DATA);
12967 if (prefixes & PREFIX_DATA)
12968 {
12969 names = names_xmm;
12970 USED_REX (REX_R);
12971 if (rex & REX_R)
12972 reg += 8;
12973 }
12974 else
12975 names = names_mm;
12976 oappend (names[reg]);
12977 }
12978
12979 static void
12980 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12981 {
12982 int reg = modrm.reg;
12983 const char **names;
12984
12985 USED_REX (REX_R);
12986 if (rex & REX_R)
12987 reg += 8;
12988 if (vex.evex)
12989 {
12990 if (!vex.r)
12991 reg += 16;
12992 }
12993
12994 if (need_vex
12995 && bytemode != xmm_mode
12996 && bytemode != xmmq_mode
12997 && bytemode != evex_half_bcst_xmmq_mode
12998 && bytemode != ymm_mode
12999 && bytemode != tmm_mode
13000 && bytemode != scalar_mode)
13001 {
13002 switch (vex.length)
13003 {
13004 case 128:
13005 names = names_xmm;
13006 break;
13007 case 256:
13008 if (vex.w
13009 || (bytemode != vex_vsib_q_w_dq_mode
13010 && bytemode != vex_vsib_q_w_d_mode))
13011 names = names_ymm;
13012 else
13013 names = names_xmm;
13014 break;
13015 case 512:
13016 names = names_zmm;
13017 break;
13018 default:
13019 abort ();
13020 }
13021 }
13022 else if (bytemode == xmmq_mode
13023 || bytemode == evex_half_bcst_xmmq_mode)
13024 {
13025 switch (vex.length)
13026 {
13027 case 128:
13028 case 256:
13029 names = names_xmm;
13030 break;
13031 case 512:
13032 names = names_ymm;
13033 break;
13034 default:
13035 abort ();
13036 }
13037 }
13038 else if (bytemode == tmm_mode)
13039 {
13040 modrm.reg = reg;
13041 if (reg >= 8)
13042 {
13043 oappend ("(bad)");
13044 return;
13045 }
13046 names = names_tmm;
13047 }
13048 else if (bytemode == ymm_mode)
13049 names = names_ymm;
13050 else
13051 names = names_xmm;
13052 oappend (names[reg]);
13053 }
13054
13055 static void
13056 OP_EM (int bytemode, int sizeflag)
13057 {
13058 int reg;
13059 const char **names;
13060
13061 if (modrm.mod != 3)
13062 {
13063 if (intel_syntax
13064 && (bytemode == v_mode || bytemode == v_swap_mode))
13065 {
13066 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13067 used_prefixes |= (prefixes & PREFIX_DATA);
13068 }
13069 OP_E (bytemode, sizeflag);
13070 return;
13071 }
13072
13073 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13074 swap_operand ();
13075
13076 /* Skip mod/rm byte. */
13077 MODRM_CHECK;
13078 codep++;
13079 used_prefixes |= (prefixes & PREFIX_DATA);
13080 reg = modrm.rm;
13081 if (prefixes & PREFIX_DATA)
13082 {
13083 names = names_xmm;
13084 USED_REX (REX_B);
13085 if (rex & REX_B)
13086 reg += 8;
13087 }
13088 else
13089 names = names_mm;
13090 oappend (names[reg]);
13091 }
13092
13093 /* cvt* are the only instructions in sse2 which have
13094 both SSE and MMX operands and also have 0x66 prefix
13095 in their opcode. 0x66 was originally used to differentiate
13096 between SSE and MMX instruction(operands). So we have to handle the
13097 cvt* separately using OP_EMC and OP_MXC */
13098 static void
13099 OP_EMC (int bytemode, int sizeflag)
13100 {
13101 if (modrm.mod != 3)
13102 {
13103 if (intel_syntax && bytemode == v_mode)
13104 {
13105 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13106 used_prefixes |= (prefixes & PREFIX_DATA);
13107 }
13108 OP_E (bytemode, sizeflag);
13109 return;
13110 }
13111
13112 /* Skip mod/rm byte. */
13113 MODRM_CHECK;
13114 codep++;
13115 used_prefixes |= (prefixes & PREFIX_DATA);
13116 oappend (names_mm[modrm.rm]);
13117 }
13118
13119 static void
13120 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13121 {
13122 used_prefixes |= (prefixes & PREFIX_DATA);
13123 oappend (names_mm[modrm.reg]);
13124 }
13125
13126 static void
13127 OP_EX (int bytemode, int sizeflag)
13128 {
13129 int reg;
13130 const char **names;
13131
13132 /* Skip mod/rm byte. */
13133 MODRM_CHECK;
13134 codep++;
13135
13136 if (modrm.mod != 3)
13137 {
13138 OP_E_memory (bytemode, sizeflag);
13139 return;
13140 }
13141
13142 reg = modrm.rm;
13143 USED_REX (REX_B);
13144 if (rex & REX_B)
13145 reg += 8;
13146 if (vex.evex)
13147 {
13148 USED_REX (REX_X);
13149 if ((rex & REX_X))
13150 reg += 16;
13151 }
13152
13153 if ((sizeflag & SUFFIX_ALWAYS)
13154 && (bytemode == x_swap_mode
13155 || bytemode == d_swap_mode
13156 || bytemode == q_swap_mode))
13157 swap_operand ();
13158
13159 if (need_vex
13160 && bytemode != xmm_mode
13161 && bytemode != xmmdw_mode
13162 && bytemode != xmmqd_mode
13163 && bytemode != xmm_mb_mode
13164 && bytemode != xmm_mw_mode
13165 && bytemode != xmm_md_mode
13166 && bytemode != xmm_mq_mode
13167 && bytemode != xmmq_mode
13168 && bytemode != evex_half_bcst_xmmq_mode
13169 && bytemode != ymm_mode
13170 && bytemode != tmm_mode
13171 && bytemode != vex_scalar_w_dq_mode)
13172 {
13173 switch (vex.length)
13174 {
13175 case 128:
13176 names = names_xmm;
13177 break;
13178 case 256:
13179 names = names_ymm;
13180 break;
13181 case 512:
13182 names = names_zmm;
13183 break;
13184 default:
13185 abort ();
13186 }
13187 }
13188 else if (bytemode == xmmq_mode
13189 || bytemode == evex_half_bcst_xmmq_mode)
13190 {
13191 switch (vex.length)
13192 {
13193 case 128:
13194 case 256:
13195 names = names_xmm;
13196 break;
13197 case 512:
13198 names = names_ymm;
13199 break;
13200 default:
13201 abort ();
13202 }
13203 }
13204 else if (bytemode == tmm_mode)
13205 {
13206 modrm.rm = reg;
13207 if (reg >= 8)
13208 {
13209 oappend ("(bad)");
13210 return;
13211 }
13212 names = names_tmm;
13213 }
13214 else if (bytemode == ymm_mode)
13215 names = names_ymm;
13216 else
13217 names = names_xmm;
13218 oappend (names[reg]);
13219 }
13220
13221 static void
13222 OP_MS (int bytemode, int sizeflag)
13223 {
13224 if (modrm.mod == 3)
13225 OP_EM (bytemode, sizeflag);
13226 else
13227 BadOp ();
13228 }
13229
13230 static void
13231 OP_XS (int bytemode, int sizeflag)
13232 {
13233 if (modrm.mod == 3)
13234 OP_EX (bytemode, sizeflag);
13235 else
13236 BadOp ();
13237 }
13238
13239 static void
13240 OP_M (int bytemode, int sizeflag)
13241 {
13242 if (modrm.mod == 3)
13243 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13244 BadOp ();
13245 else
13246 OP_E (bytemode, sizeflag);
13247 }
13248
13249 static void
13250 OP_0f07 (int bytemode, int sizeflag)
13251 {
13252 if (modrm.mod != 3 || modrm.rm != 0)
13253 BadOp ();
13254 else
13255 OP_E (bytemode, sizeflag);
13256 }
13257
13258 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13259 32bit mode and "xchg %rax,%rax" in 64bit mode. */
13260
13261 static void
13262 NOP_Fixup1 (int bytemode, int sizeflag)
13263 {
13264 if ((prefixes & PREFIX_DATA) != 0
13265 || (rex != 0
13266 && rex != 0x48
13267 && address_mode == mode_64bit))
13268 OP_REG (bytemode, sizeflag);
13269 else
13270 strcpy (obuf, "nop");
13271 }
13272
13273 static void
13274 NOP_Fixup2 (int bytemode, int sizeflag)
13275 {
13276 if ((prefixes & PREFIX_DATA) != 0
13277 || (rex != 0
13278 && rex != 0x48
13279 && address_mode == mode_64bit))
13280 OP_IMREG (bytemode, sizeflag);
13281 }
13282
13283 static const char *const Suffix3DNow[] = {
13284 /* 00 */ NULL, NULL, NULL, NULL,
13285 /* 04 */ NULL, NULL, NULL, NULL,
13286 /* 08 */ NULL, NULL, NULL, NULL,
13287 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
13288 /* 10 */ NULL, NULL, NULL, NULL,
13289 /* 14 */ NULL, NULL, NULL, NULL,
13290 /* 18 */ NULL, NULL, NULL, NULL,
13291 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
13292 /* 20 */ NULL, NULL, NULL, NULL,
13293 /* 24 */ NULL, NULL, NULL, NULL,
13294 /* 28 */ NULL, NULL, NULL, NULL,
13295 /* 2C */ NULL, NULL, NULL, NULL,
13296 /* 30 */ NULL, NULL, NULL, NULL,
13297 /* 34 */ NULL, NULL, NULL, NULL,
13298 /* 38 */ NULL, NULL, NULL, NULL,
13299 /* 3C */ NULL, NULL, NULL, NULL,
13300 /* 40 */ NULL, NULL, NULL, NULL,
13301 /* 44 */ NULL, NULL, NULL, NULL,
13302 /* 48 */ NULL, NULL, NULL, NULL,
13303 /* 4C */ NULL, NULL, NULL, NULL,
13304 /* 50 */ NULL, NULL, NULL, NULL,
13305 /* 54 */ NULL, NULL, NULL, NULL,
13306 /* 58 */ NULL, NULL, NULL, NULL,
13307 /* 5C */ NULL, NULL, NULL, NULL,
13308 /* 60 */ NULL, NULL, NULL, NULL,
13309 /* 64 */ NULL, NULL, NULL, NULL,
13310 /* 68 */ NULL, NULL, NULL, NULL,
13311 /* 6C */ NULL, NULL, NULL, NULL,
13312 /* 70 */ NULL, NULL, NULL, NULL,
13313 /* 74 */ NULL, NULL, NULL, NULL,
13314 /* 78 */ NULL, NULL, NULL, NULL,
13315 /* 7C */ NULL, NULL, NULL, NULL,
13316 /* 80 */ NULL, NULL, NULL, NULL,
13317 /* 84 */ NULL, NULL, NULL, NULL,
13318 /* 88 */ NULL, NULL, "pfnacc", NULL,
13319 /* 8C */ NULL, NULL, "pfpnacc", NULL,
13320 /* 90 */ "pfcmpge", NULL, NULL, NULL,
13321 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
13322 /* 98 */ NULL, NULL, "pfsub", NULL,
13323 /* 9C */ NULL, NULL, "pfadd", NULL,
13324 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
13325 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
13326 /* A8 */ NULL, NULL, "pfsubr", NULL,
13327 /* AC */ NULL, NULL, "pfacc", NULL,
13328 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
13329 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
13330 /* B8 */ NULL, NULL, NULL, "pswapd",
13331 /* BC */ NULL, NULL, NULL, "pavgusb",
13332 /* C0 */ NULL, NULL, NULL, NULL,
13333 /* C4 */ NULL, NULL, NULL, NULL,
13334 /* C8 */ NULL, NULL, NULL, NULL,
13335 /* CC */ NULL, NULL, NULL, NULL,
13336 /* D0 */ NULL, NULL, NULL, NULL,
13337 /* D4 */ NULL, NULL, NULL, NULL,
13338 /* D8 */ NULL, NULL, NULL, NULL,
13339 /* DC */ NULL, NULL, NULL, NULL,
13340 /* E0 */ NULL, NULL, NULL, NULL,
13341 /* E4 */ NULL, NULL, NULL, NULL,
13342 /* E8 */ NULL, NULL, NULL, NULL,
13343 /* EC */ NULL, NULL, NULL, NULL,
13344 /* F0 */ NULL, NULL, NULL, NULL,
13345 /* F4 */ NULL, NULL, NULL, NULL,
13346 /* F8 */ NULL, NULL, NULL, NULL,
13347 /* FC */ NULL, NULL, NULL, NULL,
13348 };
13349
13350 static void
13351 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13352 {
13353 const char *mnemonic;
13354
13355 FETCH_DATA (the_info, codep + 1);
13356 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13357 place where an 8-bit immediate would normally go. ie. the last
13358 byte of the instruction. */
13359 obufp = mnemonicendp;
13360 mnemonic = Suffix3DNow[*codep++ & 0xff];
13361 if (mnemonic)
13362 oappend (mnemonic);
13363 else
13364 {
13365 /* Since a variable sized modrm/sib chunk is between the start
13366 of the opcode (0x0f0f) and the opcode suffix, we need to do
13367 all the modrm processing first, and don't know until now that
13368 we have a bad opcode. This necessitates some cleaning up. */
13369 op_out[0][0] = '\0';
13370 op_out[1][0] = '\0';
13371 BadOp ();
13372 }
13373 mnemonicendp = obufp;
13374 }
13375
13376 static const struct op simd_cmp_op[] =
13377 {
13378 { STRING_COMMA_LEN ("eq") },
13379 { STRING_COMMA_LEN ("lt") },
13380 { STRING_COMMA_LEN ("le") },
13381 { STRING_COMMA_LEN ("unord") },
13382 { STRING_COMMA_LEN ("neq") },
13383 { STRING_COMMA_LEN ("nlt") },
13384 { STRING_COMMA_LEN ("nle") },
13385 { STRING_COMMA_LEN ("ord") }
13386 };
13387
13388 static const struct op vex_cmp_op[] =
13389 {
13390 { STRING_COMMA_LEN ("eq_uq") },
13391 { STRING_COMMA_LEN ("nge") },
13392 { STRING_COMMA_LEN ("ngt") },
13393 { STRING_COMMA_LEN ("false") },
13394 { STRING_COMMA_LEN ("neq_oq") },
13395 { STRING_COMMA_LEN ("ge") },
13396 { STRING_COMMA_LEN ("gt") },
13397 { STRING_COMMA_LEN ("true") },
13398 { STRING_COMMA_LEN ("eq_os") },
13399 { STRING_COMMA_LEN ("lt_oq") },
13400 { STRING_COMMA_LEN ("le_oq") },
13401 { STRING_COMMA_LEN ("unord_s") },
13402 { STRING_COMMA_LEN ("neq_us") },
13403 { STRING_COMMA_LEN ("nlt_uq") },
13404 { STRING_COMMA_LEN ("nle_uq") },
13405 { STRING_COMMA_LEN ("ord_s") },
13406 { STRING_COMMA_LEN ("eq_us") },
13407 { STRING_COMMA_LEN ("nge_uq") },
13408 { STRING_COMMA_LEN ("ngt_uq") },
13409 { STRING_COMMA_LEN ("false_os") },
13410 { STRING_COMMA_LEN ("neq_os") },
13411 { STRING_COMMA_LEN ("ge_oq") },
13412 { STRING_COMMA_LEN ("gt_oq") },
13413 { STRING_COMMA_LEN ("true_us") },
13414 };
13415
13416 static void
13417 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13418 {
13419 unsigned int cmp_type;
13420
13421 FETCH_DATA (the_info, codep + 1);
13422 cmp_type = *codep++ & 0xff;
13423 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13424 {
13425 char suffix [3];
13426 char *p = mnemonicendp - 2;
13427 suffix[0] = p[0];
13428 suffix[1] = p[1];
13429 suffix[2] = '\0';
13430 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13431 mnemonicendp += simd_cmp_op[cmp_type].len;
13432 }
13433 else if (need_vex
13434 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13435 {
13436 char suffix [3];
13437 char *p = mnemonicendp - 2;
13438 suffix[0] = p[0];
13439 suffix[1] = p[1];
13440 suffix[2] = '\0';
13441 cmp_type -= ARRAY_SIZE (simd_cmp_op);
13442 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13443 mnemonicendp += vex_cmp_op[cmp_type].len;
13444 }
13445 else
13446 {
13447 /* We have a reserved extension byte. Output it directly. */
13448 scratchbuf[0] = '$';
13449 print_operand_value (scratchbuf + 1, 1, cmp_type);
13450 oappend_maybe_intel (scratchbuf);
13451 scratchbuf[0] = '\0';
13452 }
13453 }
13454
13455 static void
13456 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13457 {
13458 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13459 if (!intel_syntax)
13460 {
13461 strcpy (op_out[0], names32[0]);
13462 strcpy (op_out[1], names32[1]);
13463 if (bytemode == eBX_reg)
13464 strcpy (op_out[2], names32[3]);
13465 two_source_ops = 1;
13466 }
13467 /* Skip mod/rm byte. */
13468 MODRM_CHECK;
13469 codep++;
13470 }
13471
13472 static void
13473 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13474 int sizeflag ATTRIBUTE_UNUSED)
13475 {
13476 /* monitor %{e,r,}ax,%ecx,%edx" */
13477 if (!intel_syntax)
13478 {
13479 const char **names = (address_mode == mode_64bit
13480 ? names64 : names32);
13481
13482 if (prefixes & PREFIX_ADDR)
13483 {
13484 /* Remove "addr16/addr32". */
13485 all_prefixes[last_addr_prefix] = 0;
13486 names = (address_mode != mode_32bit
13487 ? names32 : names16);
13488 used_prefixes |= PREFIX_ADDR;
13489 }
13490 else if (address_mode == mode_16bit)
13491 names = names16;
13492 strcpy (op_out[0], names[0]);
13493 strcpy (op_out[1], names32[1]);
13494 strcpy (op_out[2], names32[2]);
13495 two_source_ops = 1;
13496 }
13497 /* Skip mod/rm byte. */
13498 MODRM_CHECK;
13499 codep++;
13500 }
13501
13502 static void
13503 BadOp (void)
13504 {
13505 /* Throw away prefixes and 1st. opcode byte. */
13506 codep = insn_codep + 1;
13507 oappend ("(bad)");
13508 }
13509
13510 static void
13511 REP_Fixup (int bytemode, int sizeflag)
13512 {
13513 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13514 lods and stos. */
13515 if (prefixes & PREFIX_REPZ)
13516 all_prefixes[last_repz_prefix] = REP_PREFIX;
13517
13518 switch (bytemode)
13519 {
13520 case al_reg:
13521 case eAX_reg:
13522 case indir_dx_reg:
13523 OP_IMREG (bytemode, sizeflag);
13524 break;
13525 case eDI_reg:
13526 OP_ESreg (bytemode, sizeflag);
13527 break;
13528 case eSI_reg:
13529 OP_DSreg (bytemode, sizeflag);
13530 break;
13531 default:
13532 abort ();
13533 break;
13534 }
13535 }
13536
13537 static void
13538 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13539 {
13540 if ( isa64 != amd64 )
13541 return;
13542
13543 obufp = obuf;
13544 BadOp ();
13545 mnemonicendp = obufp;
13546 ++codep;
13547 }
13548
13549 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13550 "bnd". */
13551
13552 static void
13553 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13554 {
13555 if (prefixes & PREFIX_REPNZ)
13556 all_prefixes[last_repnz_prefix] = BND_PREFIX;
13557 }
13558
13559 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13560 "notrack". */
13561
13562 static void
13563 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
13564 int sizeflag ATTRIBUTE_UNUSED)
13565 {
13566 if (active_seg_prefix == PREFIX_DS
13567 && (address_mode != mode_64bit || last_data_prefix < 0))
13568 {
13569 /* NOTRACK prefix is only valid on indirect branch instructions.
13570 NB: DATA prefix is unsupported for Intel64. */
13571 active_seg_prefix = 0;
13572 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
13573 }
13574 }
13575
13576 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13577 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13578 */
13579
13580 static void
13581 HLE_Fixup1 (int bytemode, int sizeflag)
13582 {
13583 if (modrm.mod != 3
13584 && (prefixes & PREFIX_LOCK) != 0)
13585 {
13586 if (prefixes & PREFIX_REPZ)
13587 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13588 if (prefixes & PREFIX_REPNZ)
13589 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13590 }
13591
13592 OP_E (bytemode, sizeflag);
13593 }
13594
13595 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13596 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13597 */
13598
13599 static void
13600 HLE_Fixup2 (int bytemode, int sizeflag)
13601 {
13602 if (modrm.mod != 3)
13603 {
13604 if (prefixes & PREFIX_REPZ)
13605 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13606 if (prefixes & PREFIX_REPNZ)
13607 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13608 }
13609
13610 OP_E (bytemode, sizeflag);
13611 }
13612
13613 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13614 "xrelease" for memory operand. No check for LOCK prefix. */
13615
13616 static void
13617 HLE_Fixup3 (int bytemode, int sizeflag)
13618 {
13619 if (modrm.mod != 3
13620 && last_repz_prefix > last_repnz_prefix
13621 && (prefixes & PREFIX_REPZ) != 0)
13622 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13623
13624 OP_E (bytemode, sizeflag);
13625 }
13626
13627 static void
13628 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13629 {
13630 USED_REX (REX_W);
13631 if (rex & REX_W)
13632 {
13633 /* Change cmpxchg8b to cmpxchg16b. */
13634 char *p = mnemonicendp - 2;
13635 mnemonicendp = stpcpy (p, "16b");
13636 bytemode = o_mode;
13637 }
13638 else if ((prefixes & PREFIX_LOCK) != 0)
13639 {
13640 if (prefixes & PREFIX_REPZ)
13641 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13642 if (prefixes & PREFIX_REPNZ)
13643 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13644 }
13645
13646 OP_M (bytemode, sizeflag);
13647 }
13648
13649 static void
13650 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13651 {
13652 const char **names;
13653
13654 if (need_vex)
13655 {
13656 switch (vex.length)
13657 {
13658 case 128:
13659 names = names_xmm;
13660 break;
13661 case 256:
13662 names = names_ymm;
13663 break;
13664 default:
13665 abort ();
13666 }
13667 }
13668 else
13669 names = names_xmm;
13670 oappend (names[reg]);
13671 }
13672
13673 static void
13674 FXSAVE_Fixup (int bytemode, int sizeflag)
13675 {
13676 /* Add proper suffix to "fxsave" and "fxrstor". */
13677 USED_REX (REX_W);
13678 if (rex & REX_W)
13679 {
13680 char *p = mnemonicendp;
13681 *p++ = '6';
13682 *p++ = '4';
13683 *p = '\0';
13684 mnemonicendp = p;
13685 }
13686 OP_M (bytemode, sizeflag);
13687 }
13688
13689 /* Display the destination register operand for instructions with
13690 VEX. */
13691
13692 static void
13693 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13694 {
13695 int reg;
13696 const char **names;
13697
13698 if (!need_vex)
13699 abort ();
13700
13701 reg = vex.register_specifier;
13702 vex.register_specifier = 0;
13703 if (address_mode != mode_64bit)
13704 reg &= 7;
13705 else if (vex.evex && !vex.v)
13706 reg += 16;
13707
13708 if (bytemode == vex_scalar_mode)
13709 {
13710 oappend (names_xmm[reg]);
13711 return;
13712 }
13713
13714 if (bytemode == tmm_mode)
13715 {
13716 /* All 3 TMM registers must be distinct. */
13717 if (reg >= 8)
13718 oappend ("(bad)");
13719 else
13720 {
13721 /* This must be the 3rd operand. */
13722 if (obufp != op_out[2])
13723 abort ();
13724 oappend (names_tmm[reg]);
13725 if (reg == modrm.reg || reg == modrm.rm)
13726 strcpy (obufp, "/(bad)");
13727 }
13728
13729 if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
13730 {
13731 if (modrm.reg <= 8
13732 && (modrm.reg == modrm.rm || modrm.reg == reg))
13733 strcat (op_out[0], "/(bad)");
13734 if (modrm.rm <= 8
13735 && (modrm.rm == modrm.reg || modrm.rm == reg))
13736 strcat (op_out[1], "/(bad)");
13737 }
13738
13739 return;
13740 }
13741
13742 switch (vex.length)
13743 {
13744 case 128:
13745 switch (bytemode)
13746 {
13747 case vex_mode:
13748 case vex_vsib_q_w_dq_mode:
13749 case vex_vsib_q_w_d_mode:
13750 names = names_xmm;
13751 break;
13752 case dq_mode:
13753 if (rex & REX_W)
13754 names = names64;
13755 else
13756 names = names32;
13757 break;
13758 case mask_bd_mode:
13759 case mask_mode:
13760 if (reg > 0x7)
13761 {
13762 oappend ("(bad)");
13763 return;
13764 }
13765 names = names_mask;
13766 break;
13767 default:
13768 abort ();
13769 return;
13770 }
13771 break;
13772 case 256:
13773 switch (bytemode)
13774 {
13775 case vex_mode:
13776 names = names_ymm;
13777 break;
13778 case vex_vsib_q_w_dq_mode:
13779 case vex_vsib_q_w_d_mode:
13780 names = vex.w ? names_ymm : names_xmm;
13781 break;
13782 case mask_bd_mode:
13783 case mask_mode:
13784 if (reg > 0x7)
13785 {
13786 oappend ("(bad)");
13787 return;
13788 }
13789 names = names_mask;
13790 break;
13791 default:
13792 /* See PR binutils/20893 for a reproducer. */
13793 oappend ("(bad)");
13794 return;
13795 }
13796 break;
13797 case 512:
13798 names = names_zmm;
13799 break;
13800 default:
13801 abort ();
13802 break;
13803 }
13804 oappend (names[reg]);
13805 }
13806
13807 static void
13808 OP_VexR (int bytemode, int sizeflag)
13809 {
13810 if (modrm.mod == 3)
13811 OP_VEX (bytemode, sizeflag);
13812 }
13813
13814 static void
13815 OP_VexW (int bytemode, int sizeflag)
13816 {
13817 OP_VEX (bytemode, sizeflag);
13818
13819 if (vex.w)
13820 {
13821 /* Swap 2nd and 3rd operands. */
13822 strcpy (scratchbuf, op_out[2]);
13823 strcpy (op_out[2], op_out[1]);
13824 strcpy (op_out[1], scratchbuf);
13825 }
13826 }
13827
13828 static void
13829 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13830 {
13831 int reg;
13832 const char **names = names_xmm;
13833
13834 FETCH_DATA (the_info, codep + 1);
13835 reg = *codep++;
13836
13837 if (bytemode != x_mode && bytemode != scalar_mode)
13838 abort ();
13839
13840 reg >>= 4;
13841 if (address_mode != mode_64bit)
13842 reg &= 7;
13843
13844 if (bytemode == x_mode && vex.length == 256)
13845 names = names_ymm;
13846
13847 oappend (names[reg]);
13848
13849 if (vex.w)
13850 {
13851 /* Swap 3rd and 4th operands. */
13852 strcpy (scratchbuf, op_out[3]);
13853 strcpy (op_out[3], op_out[2]);
13854 strcpy (op_out[2], scratchbuf);
13855 }
13856 }
13857
13858 static void
13859 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
13860 int sizeflag ATTRIBUTE_UNUSED)
13861 {
13862 scratchbuf[0] = '$';
13863 print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
13864 oappend_maybe_intel (scratchbuf);
13865 }
13866
13867 static void
13868 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
13869 int sizeflag ATTRIBUTE_UNUSED)
13870 {
13871 unsigned int cmp_type;
13872
13873 if (!vex.evex)
13874 abort ();
13875
13876 FETCH_DATA (the_info, codep + 1);
13877 cmp_type = *codep++ & 0xff;
13878 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13879 If it's the case, print suffix, otherwise - print the immediate. */
13880 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13881 && cmp_type != 3
13882 && cmp_type != 7)
13883 {
13884 char suffix [3];
13885 char *p = mnemonicendp - 2;
13886
13887 /* vpcmp* can have both one- and two-lettered suffix. */
13888 if (p[0] == 'p')
13889 {
13890 p++;
13891 suffix[0] = p[0];
13892 suffix[1] = '\0';
13893 }
13894 else
13895 {
13896 suffix[0] = p[0];
13897 suffix[1] = p[1];
13898 suffix[2] = '\0';
13899 }
13900
13901 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13902 mnemonicendp += simd_cmp_op[cmp_type].len;
13903 }
13904 else
13905 {
13906 /* We have a reserved extension byte. Output it directly. */
13907 scratchbuf[0] = '$';
13908 print_operand_value (scratchbuf + 1, 1, cmp_type);
13909 oappend_maybe_intel (scratchbuf);
13910 scratchbuf[0] = '\0';
13911 }
13912 }
13913
13914 static const struct op xop_cmp_op[] =
13915 {
13916 { STRING_COMMA_LEN ("lt") },
13917 { STRING_COMMA_LEN ("le") },
13918 { STRING_COMMA_LEN ("gt") },
13919 { STRING_COMMA_LEN ("ge") },
13920 { STRING_COMMA_LEN ("eq") },
13921 { STRING_COMMA_LEN ("neq") },
13922 { STRING_COMMA_LEN ("false") },
13923 { STRING_COMMA_LEN ("true") }
13924 };
13925
13926 static void
13927 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
13928 int sizeflag ATTRIBUTE_UNUSED)
13929 {
13930 unsigned int cmp_type;
13931
13932 FETCH_DATA (the_info, codep + 1);
13933 cmp_type = *codep++ & 0xff;
13934 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13935 {
13936 char suffix[3];
13937 char *p = mnemonicendp - 2;
13938
13939 /* vpcom* can have both one- and two-lettered suffix. */
13940 if (p[0] == 'm')
13941 {
13942 p++;
13943 suffix[0] = p[0];
13944 suffix[1] = '\0';
13945 }
13946 else
13947 {
13948 suffix[0] = p[0];
13949 suffix[1] = p[1];
13950 suffix[2] = '\0';
13951 }
13952
13953 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13954 mnemonicendp += xop_cmp_op[cmp_type].len;
13955 }
13956 else
13957 {
13958 /* We have a reserved extension byte. Output it directly. */
13959 scratchbuf[0] = '$';
13960 print_operand_value (scratchbuf + 1, 1, cmp_type);
13961 oappend_maybe_intel (scratchbuf);
13962 scratchbuf[0] = '\0';
13963 }
13964 }
13965
13966 static const struct op pclmul_op[] =
13967 {
13968 { STRING_COMMA_LEN ("lql") },
13969 { STRING_COMMA_LEN ("hql") },
13970 { STRING_COMMA_LEN ("lqh") },
13971 { STRING_COMMA_LEN ("hqh") }
13972 };
13973
13974 static void
13975 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13976 int sizeflag ATTRIBUTE_UNUSED)
13977 {
13978 unsigned int pclmul_type;
13979
13980 FETCH_DATA (the_info, codep + 1);
13981 pclmul_type = *codep++ & 0xff;
13982 switch (pclmul_type)
13983 {
13984 case 0x10:
13985 pclmul_type = 2;
13986 break;
13987 case 0x11:
13988 pclmul_type = 3;
13989 break;
13990 default:
13991 break;
13992 }
13993 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13994 {
13995 char suffix [4];
13996 char *p = mnemonicendp - 3;
13997 suffix[0] = p[0];
13998 suffix[1] = p[1];
13999 suffix[2] = p[2];
14000 suffix[3] = '\0';
14001 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14002 mnemonicendp += pclmul_op[pclmul_type].len;
14003 }
14004 else
14005 {
14006 /* We have a reserved extension byte. Output it directly. */
14007 scratchbuf[0] = '$';
14008 print_operand_value (scratchbuf + 1, 1, pclmul_type);
14009 oappend_maybe_intel (scratchbuf);
14010 scratchbuf[0] = '\0';
14011 }
14012 }
14013
14014 static void
14015 MOVSXD_Fixup (int bytemode, int sizeflag)
14016 {
14017 /* Add proper suffix to "movsxd". */
14018 char *p = mnemonicendp;
14019
14020 switch (bytemode)
14021 {
14022 case movsxd_mode:
14023 if (intel_syntax)
14024 {
14025 *p++ = 'x';
14026 *p++ = 'd';
14027 goto skip;
14028 }
14029
14030 USED_REX (REX_W);
14031 if (rex & REX_W)
14032 {
14033 *p++ = 'l';
14034 *p++ = 'q';
14035 }
14036 else
14037 {
14038 *p++ = 'x';
14039 *p++ = 'd';
14040 }
14041 break;
14042 default:
14043 oappend (INTERNAL_DISASSEMBLER_ERROR);
14044 break;
14045 }
14046
14047 skip:
14048 mnemonicendp = p;
14049 *p = '\0';
14050 OP_E (bytemode, sizeflag);
14051 }
14052
14053 static void
14054 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14055 {
14056 if (!vex.evex
14057 || (bytemode != mask_mode && bytemode != mask_bd_mode))
14058 abort ();
14059
14060 USED_REX (REX_R);
14061 if ((rex & REX_R) != 0 || !vex.r)
14062 {
14063 BadOp ();
14064 return;
14065 }
14066
14067 oappend (names_mask [modrm.reg]);
14068 }
14069
14070 static void
14071 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14072 {
14073 if (modrm.mod == 3 && vex.b)
14074 switch (bytemode)
14075 {
14076 case evex_rounding_64_mode:
14077 if (address_mode != mode_64bit)
14078 {
14079 oappend ("(bad)");
14080 break;
14081 }
14082 /* Fall through. */
14083 case evex_rounding_mode:
14084 oappend (names_rounding[vex.ll]);
14085 break;
14086 case evex_sae_mode:
14087 oappend ("{sae}");
14088 break;
14089 default:
14090 abort ();
14091 break;
14092 }
14093 }
GDB Binutils - Deliverables
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