opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_R (int, int);
  81 static void OP_MMX (int, int);
  82 static void OP_XMM (int, int);
  83 static void OP_EM (int, int);
  84 static void OP_EX (int, int);
  85 static void OP_EMC (int,int);
  86 static void OP_MXC (int,int);
  87 static void OP_MS (int, int);
  88 static void OP_XS (int, int);
  89 static void OP_M (int, int);
  90 static void OP_VEX (int, int);
  91 static void OP_VexW (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_Rounding (int, int);
  95 static void OP_REG_VexI4 (int, int);
  96 static void OP_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VPCMP_Fixup (int, int);
  99 static void VPCOM_Fixup (int, int);
 100 static void OP_0f07 (int, int);
 101 static void OP_Monitor (int, int);
 102 static void OP_Mwait (int, int);
 103 static void NOP_Fixup1 (int, int);
 104 static void NOP_Fixup2 (int, int);
 105 static void OP_3DNowSuffix (int, int);
 106 static void CMP_Fixup (int, int);
 107 static void BadOp (void);
 108 static void REP_Fixup (int, int);
 109 static void SEP_Fixup (int, int);
 110 static void BND_Fixup (int, int);
 111 static void NOTRACK_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void FXSAVE_Fixup (int, int);
 118
 119 static void MOVSXD_Fixup (int, int);
 120
 121 static void OP_Mask (int, int);
 122
 123 struct dis_private {
 124   /* Points to first byte not fetched.  */
 125   bfd_byte *max_fetched;
 126   bfd_byte the_buffer[MAX_MNEM_SIZE];
 127   bfd_vma insn_start;
 128   int orig_sizeflag;
 129   OPCODES_SIGJMP_BUF bailout;
 130 };
 131
 132 enum address_mode
 133 {
 134   mode_16bit,
 135   mode_32bit,
 136   mode_64bit
 137 };
 138
 139 enum address_mode address_mode;
 140
 141 /* Flags for the prefixes for the current instruction.  See below.  */
 142 static int prefixes;
 143
 144 /* REX prefix the current instruction.  See below.  */
 145 static int rex;
 146 /* Bits of REX we've already used.  */
 147 static int rex_used;
 148 /* Mark parts used in the REX prefix.  When we are testing for
 149    empty prefix (for 8bit register REX extension), just mask it
 150    out.  Otherwise test for REX bit is excuse for existence of REX
 151    only in case value is nonzero.  */
 152 #define USED_REX(value)                                 \
 153   {                                                     \
 154     if (value)                                          \
 155       {                                                 \
 156         if ((rex & value))                              \
 157           rex_used |= (value) | REX_OPCODE;             \
 158       }                                                 \
 159     else                                                \
 160       rex_used |= REX_OPCODE;                           \
 161   }
 162
 163 /* Flags for prefixes which we somehow handled when printing the
 164    current instruction.  */
 165 static int used_prefixes;
 166
 167 /* Flags stored in PREFIXES.  */
 168 #define PREFIX_REPZ 1
 169 #define PREFIX_REPNZ 2
 170 #define PREFIX_LOCK 4
 171 #define PREFIX_CS 8
 172 #define PREFIX_SS 0x10
 173 #define PREFIX_DS 0x20
 174 #define PREFIX_ES 0x40
 175 #define PREFIX_FS 0x80
 176 #define PREFIX_GS 0x100
 177 #define PREFIX_DATA 0x200
 178 #define PREFIX_ADDR 0x400
 179 #define PREFIX_FWAIT 0x800
 180
 181 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 182    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 183    on error.  */
 184 #define FETCH_DATA(info, addr) \
 185   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 186    ? 1 : fetch_data ((info), (addr)))
 187
 188 static int
 189 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 190 {
 191   int status;
 192   struct dis_private *priv = (struct dis_private *) info->private_data;
 193   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 194
 195   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 196     status = (*info->read_memory_func) (start,
 197                                         priv->max_fetched,
 198                                         addr - priv->max_fetched,
 199                                         info);
 200   else
 201     status = -1;
 202   if (status != 0)
 203     {
 204       /* If we did manage to read at least one byte, then
 205          print_insn_i386 will do something sensible.  Otherwise, print
 206          an error.  We do that here because this is where we know
 207          STATUS.  */
 208       if (priv->max_fetched == priv->the_buffer)
 209         (*info->memory_error_func) (status, start, info);
 210       OPCODES_SIGLONGJMP (priv->bailout, 1);
 211     }
 212   else
 213     priv->max_fetched = addr;
 214   return 1;
 215 }
 216
 217 /* Possible values for prefix requirement.  */
 218 #define PREFIX_IGNORED_SHIFT    16
 219 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 220 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 221 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 222 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 223 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 224
 225 /* Opcode prefixes.  */
 226 #define PREFIX_OPCODE           (PREFIX_REPZ \
 227                                  | PREFIX_REPNZ \
 228                                  | PREFIX_DATA)
 229
 230 /* Prefixes ignored.  */
 231 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 232                                  | PREFIX_IGNORED_REPNZ \
 233                                  | PREFIX_IGNORED_DATA)
 234
 235 #define XX { NULL, 0 }
 236 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 237
 238 #define Eb { OP_E, b_mode }
 239 #define Ebnd { OP_E, bnd_mode }
 240 #define EbS { OP_E, b_swap_mode }
 241 #define EbndS { OP_E, bnd_swap_mode }
 242 #define Ev { OP_E, v_mode }
 243 #define Eva { OP_E, va_mode }
 244 #define Ev_bnd { OP_E, v_bnd_mode }
 245 #define EvS { OP_E, v_swap_mode }
 246 #define Ed { OP_E, d_mode }
 247 #define Edq { OP_E, dq_mode }
 248 #define Edqw { OP_E, dqw_mode }
 249 #define Edqb { OP_E, dqb_mode }
 250 #define Edb { OP_E, db_mode }
 251 #define Edw { OP_E, dw_mode }
 252 #define Edqd { OP_E, dqd_mode }
 253 #define Eq { OP_E, q_mode }
 254 #define indirEv { OP_indirE, indir_v_mode }
 255 #define indirEp { OP_indirE, f_mode }
 256 #define stackEv { OP_E, stack_v_mode }
 257 #define Em { OP_E, m_mode }
 258 #define Ew { OP_E, w_mode }
 259 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 260 #define Ma { OP_M, a_mode }
 261 #define Mb { OP_M, b_mode }
 262 #define Md { OP_M, d_mode }
 263 #define Mo { OP_M, o_mode }
 264 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 265 #define Mq { OP_M, q_mode }
 266 #define Mv { OP_M, v_mode }
 267 #define Mv_bnd { OP_M, v_bndmk_mode }
 268 #define Mx { OP_M, x_mode }
 269 #define Mxmm { OP_M, xmm_mode }
 270 #define Gb { OP_G, b_mode }
 271 #define Gbnd { OP_G, bnd_mode }
 272 #define Gv { OP_G, v_mode }
 273 #define Gd { OP_G, d_mode }
 274 #define Gdq { OP_G, dq_mode }
 275 #define Gm { OP_G, m_mode }
 276 #define Gva { OP_G, va_mode }
 277 #define Gw { OP_G, w_mode }
 278 #define Rd { OP_R, d_mode }
 279 #define Rdq { OP_R, dq_mode }
 280 #define Rm { OP_R, m_mode }
 281 #define Ib { OP_I, b_mode }
 282 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 283 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 284 #define Iv { OP_I, v_mode }
 285 #define sIv { OP_sI, v_mode }
 286 #define Iv64 { OP_I64, v_mode }
 287 #define Id { OP_I, d_mode }
 288 #define Iw { OP_I, w_mode }
 289 #define I1 { OP_I, const_1_mode }
 290 #define Jb { OP_J, b_mode }
 291 #define Jv { OP_J, v_mode }
 292 #define Jdqw { OP_J, dqw_mode }
 293 #define Cm { OP_C, m_mode }
 294 #define Dm { OP_D, m_mode }
 295 #define Td { OP_T, d_mode }
 296 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 297
 298 #define RMeAX { OP_REG, eAX_reg }
 299 #define RMeBX { OP_REG, eBX_reg }
 300 #define RMeCX { OP_REG, eCX_reg }
 301 #define RMeDX { OP_REG, eDX_reg }
 302 #define RMeSP { OP_REG, eSP_reg }
 303 #define RMeBP { OP_REG, eBP_reg }
 304 #define RMeSI { OP_REG, eSI_reg }
 305 #define RMeDI { OP_REG, eDI_reg }
 306 #define RMrAX { OP_REG, rAX_reg }
 307 #define RMrBX { OP_REG, rBX_reg }
 308 #define RMrCX { OP_REG, rCX_reg }
 309 #define RMrDX { OP_REG, rDX_reg }
 310 #define RMrSP { OP_REG, rSP_reg }
 311 #define RMrBP { OP_REG, rBP_reg }
 312 #define RMrSI { OP_REG, rSI_reg }
 313 #define RMrDI { OP_REG, rDI_reg }
 314 #define RMAL { OP_REG, al_reg }
 315 #define RMCL { OP_REG, cl_reg }
 316 #define RMDL { OP_REG, dl_reg }
 317 #define RMBL { OP_REG, bl_reg }
 318 #define RMAH { OP_REG, ah_reg }
 319 #define RMCH { OP_REG, ch_reg }
 320 #define RMDH { OP_REG, dh_reg }
 321 #define RMBH { OP_REG, bh_reg }
 322 #define RMAX { OP_REG, ax_reg }
 323 #define RMDX { OP_REG, dx_reg }
 324
 325 #define eAX { OP_IMREG, eAX_reg }
 326 #define AL { OP_IMREG, al_reg }
 327 #define CL { OP_IMREG, cl_reg }
 328 #define zAX { OP_IMREG, z_mode_ax_reg }
 329 #define indirDX { OP_IMREG, indir_dx_reg }
 330
 331 #define Sw { OP_SEG, w_mode }
 332 #define Sv { OP_SEG, v_mode }
 333 #define Ap { OP_DIR, 0 }
 334 #define Ob { OP_OFF64, b_mode }
 335 #define Ov { OP_OFF64, v_mode }
 336 #define Xb { OP_DSreg, eSI_reg }
 337 #define Xv { OP_DSreg, eSI_reg }
 338 #define Xz { OP_DSreg, eSI_reg }
 339 #define Yb { OP_ESreg, eDI_reg }
 340 #define Yv { OP_ESreg, eDI_reg }
 341 #define DSBX { OP_DSreg, eBX_reg }
 342
 343 #define es { OP_REG, es_reg }
 344 #define ss { OP_REG, ss_reg }
 345 #define cs { OP_REG, cs_reg }
 346 #define ds { OP_REG, ds_reg }
 347 #define fs { OP_REG, fs_reg }
 348 #define gs { OP_REG, gs_reg }
 349
 350 #define MX { OP_MMX, 0 }
 351 #define XM { OP_XMM, 0 }
 352 #define XMScalar { OP_XMM, scalar_mode }
 353 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 354 #define XMM { OP_XMM, xmm_mode }
 355 #define TMM { OP_XMM, tmm_mode }
 356 #define XMxmmq { OP_XMM, xmmq_mode }
 357 #define EM { OP_EM, v_mode }
 358 #define EMS { OP_EM, v_swap_mode }
 359 #define EMd { OP_EM, d_mode }
 360 #define EMx { OP_EM, x_mode }
 361 #define EXbwUnit { OP_EX, bw_unit_mode }
 362 #define EXw { OP_EX, w_mode }
 363 #define EXd { OP_EX, d_mode }
 364 #define EXdS { OP_EX, d_swap_mode }
 365 #define EXq { OP_EX, q_mode }
 366 #define EXqS { OP_EX, q_swap_mode }
 367 #define EXx { OP_EX, x_mode }
 368 #define EXxS { OP_EX, x_swap_mode }
 369 #define EXxmm { OP_EX, xmm_mode }
 370 #define EXymm { OP_EX, ymm_mode }
 371 #define EXtmm { OP_EX, tmm_mode }
 372 #define EXxmmq { OP_EX, xmmq_mode }
 373 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 374 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 375 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 376 #define EXxmm_md { OP_EX, xmm_md_mode }
 377 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 378 #define EXxmmdw { OP_EX, xmmdw_mode }
 379 #define EXxmmqd { OP_EX, xmmqd_mode }
 380 #define EXymmq { OP_EX, ymmq_mode }
 381 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 382 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 383 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 384 #define MS { OP_MS, v_mode }
 385 #define XS { OP_XS, v_mode }
 386 #define EMCq { OP_EMC, q_mode }
 387 #define MXC { OP_MXC, 0 }
 388 #define OPSUF { OP_3DNowSuffix, 0 }
 389 #define SEP { SEP_Fixup, 0 }
 390 #define CMP { CMP_Fixup, 0 }
 391 #define XMM0 { XMM_Fixup, 0 }
 392 #define FXSAVE { FXSAVE_Fixup, 0 }
 393
 394 #define Vex { OP_VEX, vex_mode }
 395 #define VexW { OP_VexW, vex_mode }
 396 #define VexScalar { OP_VEX, vex_scalar_mode }
 397 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 398 #define VexGdq { OP_VEX, dq_mode }
 399 #define VexTmm { OP_VEX, tmm_mode }
 400 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 401 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 402 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 403 #define XMVexI4 { OP_REG_VexI4, x_mode }
 404 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 405 #define VexI4 { OP_VexI4, 0 }
 406 #define PCLMUL { PCLMUL_Fixup, 0 }
 407 #define VPCMP { VPCMP_Fixup, 0 }
 408 #define VPCOM { VPCOM_Fixup, 0 }
 409
 410 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 411 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 412 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 413
 414 #define XMask { OP_Mask, mask_mode }
 415 #define MaskG { OP_G, mask_mode }
 416 #define MaskE { OP_E, mask_mode }
 417 #define MaskBDE { OP_E, mask_bd_mode }
 418 #define MaskR { OP_R, mask_mode }
 419 #define MaskVex { OP_VEX, mask_mode }
 420
 421 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 422 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 423 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 424 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 425
 426 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 427
 428 /* Used handle "rep" prefix for string instructions.  */
 429 #define Xbr { REP_Fixup, eSI_reg }
 430 #define Xvr { REP_Fixup, eSI_reg }
 431 #define Ybr { REP_Fixup, eDI_reg }
 432 #define Yvr { REP_Fixup, eDI_reg }
 433 #define Yzr { REP_Fixup, eDI_reg }
 434 #define indirDXr { REP_Fixup, indir_dx_reg }
 435 #define ALr { REP_Fixup, al_reg }
 436 #define eAXr { REP_Fixup, eAX_reg }
 437
 438 /* Used handle HLE prefix for lockable instructions.  */
 439 #define Ebh1 { HLE_Fixup1, b_mode }
 440 #define Evh1 { HLE_Fixup1, v_mode }
 441 #define Ebh2 { HLE_Fixup2, b_mode }
 442 #define Evh2 { HLE_Fixup2, v_mode }
 443 #define Ebh3 { HLE_Fixup3, b_mode }
 444 #define Evh3 { HLE_Fixup3, v_mode }
 445
 446 #define BND { BND_Fixup, 0 }
 447 #define NOTRACK { NOTRACK_Fixup, 0 }
 448
 449 #define cond_jump_flag { NULL, cond_jump_mode }
 450 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 451
 452 /* bits in sizeflag */
 453 #define SUFFIX_ALWAYS 4
 454 #define AFLAG 2
 455 #define DFLAG 1
 456
 457 enum
 458 {
 459   /* byte operand */
 460   b_mode = 1,
 461   /* byte operand with operand swapped */
 462   b_swap_mode,
 463   /* byte operand, sign extend like 'T' suffix */
 464   b_T_mode,
 465   /* operand size depends on prefixes */
 466   v_mode,
 467   /* operand size depends on prefixes with operand swapped */
 468   v_swap_mode,
 469   /* operand size depends on address prefix */
 470   va_mode,
 471   /* word operand */
 472   w_mode,
 473   /* double word operand  */
 474   d_mode,
 475   /* double word operand with operand swapped */
 476   d_swap_mode,
 477   /* quad word operand */
 478   q_mode,
 479   /* quad word operand with operand swapped */
 480   q_swap_mode,
 481   /* ten-byte operand */
 482   t_mode,
 483   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 484      broadcast enabled.  */
 485   x_mode,
 486   /* Similar to x_mode, but with different EVEX mem shifts.  */
 487   evex_x_gscat_mode,
 488   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 489   bw_unit_mode,
 490   /* Similar to x_mode, but with disabled broadcast.  */
 491   evex_x_nobcst_mode,
 492   /* Similar to x_mode, but with operands swapped and disabled broadcast
 493      in EVEX.  */
 494   x_swap_mode,
 495   /* 16-byte XMM operand */
 496   xmm_mode,
 497   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 498      memory operand (depending on vector length).  Broadcast isn't
 499      allowed.  */
 500   xmmq_mode,
 501   /* Same as xmmq_mode, but broadcast is allowed.  */
 502   evex_half_bcst_xmmq_mode,
 503   /* XMM register or byte memory operand */
 504   xmm_mb_mode,
 505   /* XMM register or word memory operand */
 506   xmm_mw_mode,
 507   /* XMM register or double word memory operand */
 508   xmm_md_mode,
 509   /* XMM register or quad word memory operand */
 510   xmm_mq_mode,
 511   /* 16-byte XMM, word, double word or quad word operand.  */
 512   xmmdw_mode,
 513   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 514   xmmqd_mode,
 515   /* 32-byte YMM operand */
 516   ymm_mode,
 517   /* quad word, ymmword or zmmword memory operand.  */
 518   ymmq_mode,
 519   /* 32-byte YMM or 16-byte word operand */
 520   ymmxmm_mode,
 521   /* TMM operand */
 522   tmm_mode,
 523   /* d_mode in 32bit, q_mode in 64bit mode.  */
 524   m_mode,
 525   /* pair of v_mode operands */
 526   a_mode,
 527   cond_jump_mode,
 528   loop_jcxz_mode,
 529   movsxd_mode,
 530   v_bnd_mode,
 531   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 532   v_bndmk_mode,
 533   /* operand size depends on REX prefixes.  */
 534   dq_mode,
 535   /* registers like dq_mode, memory like w_mode, displacements like
 536      v_mode without considering Intel64 ISA.  */
 537   dqw_mode,
 538   /* bounds operand */
 539   bnd_mode,
 540   /* bounds operand with operand swapped */
 541   bnd_swap_mode,
 542   /* 4- or 6-byte pointer operand */
 543   f_mode,
 544   const_1_mode,
 545   /* v_mode for indirect branch opcodes.  */
 546   indir_v_mode,
 547   /* v_mode for stack-related opcodes.  */
 548   stack_v_mode,
 549   /* non-quad operand size depends on prefixes */
 550   z_mode,
 551   /* 16-byte operand */
 552   o_mode,
 553   /* registers like dq_mode, memory like b_mode.  */
 554   dqb_mode,
 555   /* registers like d_mode, memory like b_mode.  */
 556   db_mode,
 557   /* registers like d_mode, memory like w_mode.  */
 558   dw_mode,
 559   /* registers like dq_mode, memory like d_mode.  */
 560   dqd_mode,
 561   /* normal vex mode */
 562   vex_mode,
 563
 564   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 565   vex_vsib_d_w_dq_mode,
 566   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 567   vex_vsib_d_w_d_mode,
 568   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 569   vex_vsib_q_w_dq_mode,
 570   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 571   vex_vsib_q_w_d_mode,
 572   /* mandatory non-vector SIB.  */
 573   vex_sibmem_mode,
 574
 575   /* scalar, ignore vector length.  */
 576   scalar_mode,
 577   /* like d_swap_mode, ignore vector length.  */
 578   d_scalar_swap_mode,
 579   /* like q_swap_mode, ignore vector length.  */
 580   q_scalar_swap_mode,
 581   /* like vex_mode, ignore vector length.  */
 582   vex_scalar_mode,
 583   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 584   vex_scalar_w_dq_mode,
 585
 586   /* Static rounding.  */
 587   evex_rounding_mode,
 588   /* Static rounding, 64-bit mode only.  */
 589   evex_rounding_64_mode,
 590   /* Supress all exceptions.  */
 591   evex_sae_mode,
 592
 593   /* Mask register operand.  */
 594   mask_mode,
 595   /* Mask register operand.  */
 596   mask_bd_mode,
 597
 598   es_reg,
 599   cs_reg,
 600   ss_reg,
 601   ds_reg,
 602   fs_reg,
 603   gs_reg,
 604
 605   eAX_reg,
 606   eCX_reg,
 607   eDX_reg,
 608   eBX_reg,
 609   eSP_reg,
 610   eBP_reg,
 611   eSI_reg,
 612   eDI_reg,
 613
 614   al_reg,
 615   cl_reg,
 616   dl_reg,
 617   bl_reg,
 618   ah_reg,
 619   ch_reg,
 620   dh_reg,
 621   bh_reg,
 622
 623   ax_reg,
 624   cx_reg,
 625   dx_reg,
 626   bx_reg,
 627   sp_reg,
 628   bp_reg,
 629   si_reg,
 630   di_reg,
 631
 632   rAX_reg,
 633   rCX_reg,
 634   rDX_reg,
 635   rBX_reg,
 636   rSP_reg,
 637   rBP_reg,
 638   rSI_reg,
 639   rDI_reg,
 640
 641   z_mode_ax_reg,
 642   indir_dx_reg
 643 };
 644
 645 enum
 646 {
 647   FLOATCODE = 1,
 648   USE_REG_TABLE,
 649   USE_MOD_TABLE,
 650   USE_RM_TABLE,
 651   USE_PREFIX_TABLE,
 652   USE_X86_64_TABLE,
 653   USE_3BYTE_TABLE,
 654   USE_XOP_8F_TABLE,
 655   USE_VEX_C4_TABLE,
 656   USE_VEX_C5_TABLE,
 657   USE_VEX_LEN_TABLE,
 658   USE_VEX_W_TABLE,
 659   USE_EVEX_TABLE,
 660   USE_EVEX_LEN_TABLE
 661 };
 662
 663 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 664
 665 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 666 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 667 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 668 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 669 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 670 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 671 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 672 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 673 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 674 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 675 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 676 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 677 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 678 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 679 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 680 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 681
 682 enum
 683 {
 684   REG_80 = 0,
 685   REG_81,
 686   REG_83,
 687   REG_8F,
 688   REG_C0,
 689   REG_C1,
 690   REG_C6,
 691   REG_C7,
 692   REG_D0,
 693   REG_D1,
 694   REG_D2,
 695   REG_D3,
 696   REG_F6,
 697   REG_F7,
 698   REG_FE,
 699   REG_FF,
 700   REG_0F00,
 701   REG_0F01,
 702   REG_0F0D,
 703   REG_0F18,
 704   REG_0F1C_P_0_MOD_0,
 705   REG_0F1E_P_1_MOD_3,
 706   REG_0F71,
 707   REG_0F72,
 708   REG_0F73,
 709   REG_0FA6,
 710   REG_0FA7,
 711   REG_0FAE,
 712   REG_0FBA,
 713   REG_0FC7,
 714   REG_VEX_0F71,
 715   REG_VEX_0F72,
 716   REG_VEX_0F73,
 717   REG_VEX_0FAE,
 718   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 719   REG_VEX_0F38F3,
 720
 721   REG_0FXOP_09_01_L_0,
 722   REG_0FXOP_09_02_L_0,
 723   REG_0FXOP_09_12_M_1_L_0,
 724   REG_0FXOP_0A_12_L_0,
 725
 726   REG_EVEX_0F71,
 727   REG_EVEX_0F72,
 728   REG_EVEX_0F73,
 729   REG_EVEX_0F38C6,
 730   REG_EVEX_0F38C7
 731 };
 732
 733 enum
 734 {
 735   MOD_8D = 0,
 736   MOD_C6_REG_7,
 737   MOD_C7_REG_7,
 738   MOD_FF_REG_3,
 739   MOD_FF_REG_5,
 740   MOD_0F01_REG_0,
 741   MOD_0F01_REG_1,
 742   MOD_0F01_REG_2,
 743   MOD_0F01_REG_3,
 744   MOD_0F01_REG_5,
 745   MOD_0F01_REG_7,
 746   MOD_0F12_PREFIX_0,
 747   MOD_0F12_PREFIX_2,
 748   MOD_0F13,
 749   MOD_0F16_PREFIX_0,
 750   MOD_0F16_PREFIX_2,
 751   MOD_0F17,
 752   MOD_0F18_REG_0,
 753   MOD_0F18_REG_1,
 754   MOD_0F18_REG_2,
 755   MOD_0F18_REG_3,
 756   MOD_0F18_REG_4,
 757   MOD_0F18_REG_5,
 758   MOD_0F18_REG_6,
 759   MOD_0F18_REG_7,
 760   MOD_0F1A_PREFIX_0,
 761   MOD_0F1B_PREFIX_0,
 762   MOD_0F1B_PREFIX_1,
 763   MOD_0F1C_PREFIX_0,
 764   MOD_0F1E_PREFIX_1,
 765   MOD_0F24,
 766   MOD_0F26,
 767   MOD_0F2B_PREFIX_0,
 768   MOD_0F2B_PREFIX_1,
 769   MOD_0F2B_PREFIX_2,
 770   MOD_0F2B_PREFIX_3,
 771   MOD_0F50,
 772   MOD_0F71_REG_2,
 773   MOD_0F71_REG_4,
 774   MOD_0F71_REG_6,
 775   MOD_0F72_REG_2,
 776   MOD_0F72_REG_4,
 777   MOD_0F72_REG_6,
 778   MOD_0F73_REG_2,
 779   MOD_0F73_REG_3,
 780   MOD_0F73_REG_6,
 781   MOD_0F73_REG_7,
 782   MOD_0FAE_REG_0,
 783   MOD_0FAE_REG_1,
 784   MOD_0FAE_REG_2,
 785   MOD_0FAE_REG_3,
 786   MOD_0FAE_REG_4,
 787   MOD_0FAE_REG_5,
 788   MOD_0FAE_REG_6,
 789   MOD_0FAE_REG_7,
 790   MOD_0FB2,
 791   MOD_0FB4,
 792   MOD_0FB5,
 793   MOD_0FC3,
 794   MOD_0FC7_REG_3,
 795   MOD_0FC7_REG_4,
 796   MOD_0FC7_REG_5,
 797   MOD_0FC7_REG_6,
 798   MOD_0FC7_REG_7,
 799   MOD_0FD7,
 800   MOD_0FE7_PREFIX_2,
 801   MOD_0FF0_PREFIX_3,
 802   MOD_0F382A_PREFIX_2,
 803   MOD_VEX_0F3849_X86_64_P_0_W_0,
 804   MOD_VEX_0F3849_X86_64_P_2_W_0,
 805   MOD_VEX_0F3849_X86_64_P_3_W_0,
 806   MOD_VEX_0F384B_X86_64_P_1_W_0,
 807   MOD_VEX_0F384B_X86_64_P_2_W_0,
 808   MOD_VEX_0F384B_X86_64_P_3_W_0,
 809   MOD_VEX_0F385C_X86_64_P_1_W_0,
 810   MOD_VEX_0F385E_X86_64_P_0_W_0,
 811   MOD_VEX_0F385E_X86_64_P_1_W_0,
 812   MOD_VEX_0F385E_X86_64_P_2_W_0,
 813   MOD_VEX_0F385E_X86_64_P_3_W_0,
 814   MOD_0F38F5_PREFIX_2,
 815   MOD_0F38F6_PREFIX_0,
 816   MOD_0F38F8_PREFIX_1,
 817   MOD_0F38F8_PREFIX_2,
 818   MOD_0F38F8_PREFIX_3,
 819   MOD_0F38F9_PREFIX_0,
 820   MOD_62_32BIT,
 821   MOD_C4_32BIT,
 822   MOD_C5_32BIT,
 823   MOD_VEX_0F12_PREFIX_0,
 824   MOD_VEX_0F12_PREFIX_2,
 825   MOD_VEX_0F13,
 826   MOD_VEX_0F16_PREFIX_0,
 827   MOD_VEX_0F16_PREFIX_2,
 828   MOD_VEX_0F17,
 829   MOD_VEX_0F2B,
 830   MOD_VEX_W_0_0F41_P_0_LEN_1,
 831   MOD_VEX_W_1_0F41_P_0_LEN_1,
 832   MOD_VEX_W_0_0F41_P_2_LEN_1,
 833   MOD_VEX_W_1_0F41_P_2_LEN_1,
 834   MOD_VEX_W_0_0F42_P_0_LEN_1,
 835   MOD_VEX_W_1_0F42_P_0_LEN_1,
 836   MOD_VEX_W_0_0F42_P_2_LEN_1,
 837   MOD_VEX_W_1_0F42_P_2_LEN_1,
 838   MOD_VEX_W_0_0F44_P_0_LEN_1,
 839   MOD_VEX_W_1_0F44_P_0_LEN_1,
 840   MOD_VEX_W_0_0F44_P_2_LEN_1,
 841   MOD_VEX_W_1_0F44_P_2_LEN_1,
 842   MOD_VEX_W_0_0F45_P_0_LEN_1,
 843   MOD_VEX_W_1_0F45_P_0_LEN_1,
 844   MOD_VEX_W_0_0F45_P_2_LEN_1,
 845   MOD_VEX_W_1_0F45_P_2_LEN_1,
 846   MOD_VEX_W_0_0F46_P_0_LEN_1,
 847   MOD_VEX_W_1_0F46_P_0_LEN_1,
 848   MOD_VEX_W_0_0F46_P_2_LEN_1,
 849   MOD_VEX_W_1_0F46_P_2_LEN_1,
 850   MOD_VEX_W_0_0F47_P_0_LEN_1,
 851   MOD_VEX_W_1_0F47_P_0_LEN_1,
 852   MOD_VEX_W_0_0F47_P_2_LEN_1,
 853   MOD_VEX_W_1_0F47_P_2_LEN_1,
 854   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 855   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 856   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 857   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 858   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 859   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 860   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 861   MOD_VEX_0F50,
 862   MOD_VEX_0F71_REG_2,
 863   MOD_VEX_0F71_REG_4,
 864   MOD_VEX_0F71_REG_6,
 865   MOD_VEX_0F72_REG_2,
 866   MOD_VEX_0F72_REG_4,
 867   MOD_VEX_0F72_REG_6,
 868   MOD_VEX_0F73_REG_2,
 869   MOD_VEX_0F73_REG_3,
 870   MOD_VEX_0F73_REG_6,
 871   MOD_VEX_0F73_REG_7,
 872   MOD_VEX_W_0_0F91_P_0_LEN_0,
 873   MOD_VEX_W_1_0F91_P_0_LEN_0,
 874   MOD_VEX_W_0_0F91_P_2_LEN_0,
 875   MOD_VEX_W_1_0F91_P_2_LEN_0,
 876   MOD_VEX_W_0_0F92_P_0_LEN_0,
 877   MOD_VEX_W_0_0F92_P_2_LEN_0,
 878   MOD_VEX_0F92_P_3_LEN_0,
 879   MOD_VEX_W_0_0F93_P_0_LEN_0,
 880   MOD_VEX_W_0_0F93_P_2_LEN_0,
 881   MOD_VEX_0F93_P_3_LEN_0,
 882   MOD_VEX_W_0_0F98_P_0_LEN_0,
 883   MOD_VEX_W_1_0F98_P_0_LEN_0,
 884   MOD_VEX_W_0_0F98_P_2_LEN_0,
 885   MOD_VEX_W_1_0F98_P_2_LEN_0,
 886   MOD_VEX_W_0_0F99_P_0_LEN_0,
 887   MOD_VEX_W_1_0F99_P_0_LEN_0,
 888   MOD_VEX_W_0_0F99_P_2_LEN_0,
 889   MOD_VEX_W_1_0F99_P_2_LEN_0,
 890   MOD_VEX_0FAE_REG_2,
 891   MOD_VEX_0FAE_REG_3,
 892   MOD_VEX_0FD7_PREFIX_2,
 893   MOD_VEX_0FE7_PREFIX_2,
 894   MOD_VEX_0FF0_PREFIX_3,
 895   MOD_VEX_0F381A_PREFIX_2,
 896   MOD_VEX_0F382A_PREFIX_2,
 897   MOD_VEX_0F382C_PREFIX_2,
 898   MOD_VEX_0F382D_PREFIX_2,
 899   MOD_VEX_0F382E_PREFIX_2,
 900   MOD_VEX_0F382F_PREFIX_2,
 901   MOD_VEX_0F385A_PREFIX_2,
 902   MOD_VEX_0F388C_PREFIX_2,
 903   MOD_VEX_0F388E_PREFIX_2,
 904   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 905   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 906   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 907   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 908   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 909   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 910   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 911   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 912
 913   MOD_VEX_0FXOP_09_12,
 914
 915   MOD_EVEX_0F12_PREFIX_0,
 916   MOD_EVEX_0F12_PREFIX_2,
 917   MOD_EVEX_0F13,
 918   MOD_EVEX_0F16_PREFIX_0,
 919   MOD_EVEX_0F16_PREFIX_2,
 920   MOD_EVEX_0F17,
 921   MOD_EVEX_0F2B,
 922   MOD_EVEX_0F381A_P_2_W_0,
 923   MOD_EVEX_0F381A_P_2_W_1,
 924   MOD_EVEX_0F381B_P_2_W_0,
 925   MOD_EVEX_0F381B_P_2_W_1,
 926   MOD_EVEX_0F385A_P_2_W_0,
 927   MOD_EVEX_0F385A_P_2_W_1,
 928   MOD_EVEX_0F385B_P_2_W_0,
 929   MOD_EVEX_0F385B_P_2_W_1,
 930   MOD_EVEX_0F38C6_REG_1,
 931   MOD_EVEX_0F38C6_REG_2,
 932   MOD_EVEX_0F38C6_REG_5,
 933   MOD_EVEX_0F38C6_REG_6,
 934   MOD_EVEX_0F38C7_REG_1,
 935   MOD_EVEX_0F38C7_REG_2,
 936   MOD_EVEX_0F38C7_REG_5,
 937   MOD_EVEX_0F38C7_REG_6
 938 };
 939
 940 enum
 941 {
 942   RM_C6_REG_7 = 0,
 943   RM_C7_REG_7,
 944   RM_0F01_REG_0,
 945   RM_0F01_REG_1,
 946   RM_0F01_REG_2,
 947   RM_0F01_REG_3,
 948   RM_0F01_REG_5_MOD_3,
 949   RM_0F01_REG_7_MOD_3,
 950   RM_0F1E_P_1_MOD_3_REG_7,
 951   RM_0FAE_REG_6_MOD_3_P_0,
 952   RM_0FAE_REG_7_MOD_3,
 953   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 954 };
 955
 956 enum
 957 {
 958   PREFIX_90 = 0,
 959   PREFIX_0F01_REG_3_RM_1,
 960   PREFIX_0F01_REG_5_MOD_0,
 961   PREFIX_0F01_REG_5_MOD_3_RM_0,
 962   PREFIX_0F01_REG_5_MOD_3_RM_1,
 963   PREFIX_0F01_REG_5_MOD_3_RM_2,
 964   PREFIX_0F01_REG_7_MOD_3_RM_2,
 965   PREFIX_0F01_REG_7_MOD_3_RM_3,
 966   PREFIX_0F09,
 967   PREFIX_0F10,
 968   PREFIX_0F11,
 969   PREFIX_0F12,
 970   PREFIX_0F16,
 971   PREFIX_0F1A,
 972   PREFIX_0F1B,
 973   PREFIX_0F1C,
 974   PREFIX_0F1E,
 975   PREFIX_0F2A,
 976   PREFIX_0F2B,
 977   PREFIX_0F2C,
 978   PREFIX_0F2D,
 979   PREFIX_0F2E,
 980   PREFIX_0F2F,
 981   PREFIX_0F51,
 982   PREFIX_0F52,
 983   PREFIX_0F53,
 984   PREFIX_0F58,
 985   PREFIX_0F59,
 986   PREFIX_0F5A,
 987   PREFIX_0F5B,
 988   PREFIX_0F5C,
 989   PREFIX_0F5D,
 990   PREFIX_0F5E,
 991   PREFIX_0F5F,
 992   PREFIX_0F60,
 993   PREFIX_0F61,
 994   PREFIX_0F62,
 995   PREFIX_0F6C,
 996   PREFIX_0F6D,
 997   PREFIX_0F6F,
 998   PREFIX_0F70,
 999   PREFIX_0F73_REG_3,
1000   PREFIX_0F73_REG_7,
1001   PREFIX_0F78,
1002   PREFIX_0F79,
1003   PREFIX_0F7C,
1004   PREFIX_0F7D,
1005   PREFIX_0F7E,
1006   PREFIX_0F7F,
1007   PREFIX_0FAE_REG_0_MOD_3,
1008   PREFIX_0FAE_REG_1_MOD_3,
1009   PREFIX_0FAE_REG_2_MOD_3,
1010   PREFIX_0FAE_REG_3_MOD_3,
1011   PREFIX_0FAE_REG_4_MOD_0,
1012   PREFIX_0FAE_REG_4_MOD_3,
1013   PREFIX_0FAE_REG_5_MOD_0,
1014   PREFIX_0FAE_REG_5_MOD_3,
1015   PREFIX_0FAE_REG_6_MOD_0,
1016   PREFIX_0FAE_REG_6_MOD_3,
1017   PREFIX_0FAE_REG_7_MOD_0,
1018   PREFIX_0FB8,
1019   PREFIX_0FBC,
1020   PREFIX_0FBD,
1021   PREFIX_0FC2,
1022   PREFIX_0FC3_MOD_0,
1023   PREFIX_0FC7_REG_6_MOD_0,
1024   PREFIX_0FC7_REG_6_MOD_3,
1025   PREFIX_0FC7_REG_7_MOD_3,
1026   PREFIX_0FD0,
1027   PREFIX_0FD6,
1028   PREFIX_0FE6,
1029   PREFIX_0FE7,
1030   PREFIX_0FF0,
1031   PREFIX_0FF7,
1032   PREFIX_0F3810,
1033   PREFIX_0F3814,
1034   PREFIX_0F3815,
1035   PREFIX_0F3817,
1036   PREFIX_0F3820,
1037   PREFIX_0F3821,
1038   PREFIX_0F3822,
1039   PREFIX_0F3823,
1040   PREFIX_0F3824,
1041   PREFIX_0F3825,
1042   PREFIX_0F3828,
1043   PREFIX_0F3829,
1044   PREFIX_0F382A,
1045   PREFIX_0F382B,
1046   PREFIX_0F3830,
1047   PREFIX_0F3831,
1048   PREFIX_0F3832,
1049   PREFIX_0F3833,
1050   PREFIX_0F3834,
1051   PREFIX_0F3835,
1052   PREFIX_0F3837,
1053   PREFIX_0F3838,
1054   PREFIX_0F3839,
1055   PREFIX_0F383A,
1056   PREFIX_0F383B,
1057   PREFIX_0F383C,
1058   PREFIX_0F383D,
1059   PREFIX_0F383E,
1060   PREFIX_0F383F,
1061   PREFIX_0F3840,
1062   PREFIX_0F3841,
1063   PREFIX_0F3880,
1064   PREFIX_0F3881,
1065   PREFIX_0F3882,
1066   PREFIX_0F38C8,
1067   PREFIX_0F38C9,
1068   PREFIX_0F38CA,
1069   PREFIX_0F38CB,
1070   PREFIX_0F38CC,
1071   PREFIX_0F38CD,
1072   PREFIX_0F38CF,
1073   PREFIX_0F38DB,
1074   PREFIX_0F38DC,
1075   PREFIX_0F38DD,
1076   PREFIX_0F38DE,
1077   PREFIX_0F38DF,
1078   PREFIX_0F38F0,
1079   PREFIX_0F38F1,
1080   PREFIX_0F38F5,
1081   PREFIX_0F38F6,
1082   PREFIX_0F38F8,
1083   PREFIX_0F38F9,
1084   PREFIX_0F3A08,
1085   PREFIX_0F3A09,
1086   PREFIX_0F3A0A,
1087   PREFIX_0F3A0B,
1088   PREFIX_0F3A0C,
1089   PREFIX_0F3A0D,
1090   PREFIX_0F3A0E,
1091   PREFIX_0F3A14,
1092   PREFIX_0F3A15,
1093   PREFIX_0F3A16,
1094   PREFIX_0F3A17,
1095   PREFIX_0F3A20,
1096   PREFIX_0F3A21,
1097   PREFIX_0F3A22,
1098   PREFIX_0F3A40,
1099   PREFIX_0F3A41,
1100   PREFIX_0F3A42,
1101   PREFIX_0F3A44,
1102   PREFIX_0F3A60,
1103   PREFIX_0F3A61,
1104   PREFIX_0F3A62,
1105   PREFIX_0F3A63,
1106   PREFIX_0F3ACC,
1107   PREFIX_0F3ACE,
1108   PREFIX_0F3ACF,
1109   PREFIX_0F3ADF,
1110   PREFIX_VEX_0F10,
1111   PREFIX_VEX_0F11,
1112   PREFIX_VEX_0F12,
1113   PREFIX_VEX_0F16,
1114   PREFIX_VEX_0F2A,
1115   PREFIX_VEX_0F2C,
1116   PREFIX_VEX_0F2D,
1117   PREFIX_VEX_0F2E,
1118   PREFIX_VEX_0F2F,
1119   PREFIX_VEX_0F41,
1120   PREFIX_VEX_0F42,
1121   PREFIX_VEX_0F44,
1122   PREFIX_VEX_0F45,
1123   PREFIX_VEX_0F46,
1124   PREFIX_VEX_0F47,
1125   PREFIX_VEX_0F4A,
1126   PREFIX_VEX_0F4B,
1127   PREFIX_VEX_0F51,
1128   PREFIX_VEX_0F52,
1129   PREFIX_VEX_0F53,
1130   PREFIX_VEX_0F58,
1131   PREFIX_VEX_0F59,
1132   PREFIX_VEX_0F5A,
1133   PREFIX_VEX_0F5B,
1134   PREFIX_VEX_0F5C,
1135   PREFIX_VEX_0F5D,
1136   PREFIX_VEX_0F5E,
1137   PREFIX_VEX_0F5F,
1138   PREFIX_VEX_0F60,
1139   PREFIX_VEX_0F61,
1140   PREFIX_VEX_0F62,
1141   PREFIX_VEX_0F63,
1142   PREFIX_VEX_0F64,
1143   PREFIX_VEX_0F65,
1144   PREFIX_VEX_0F66,
1145   PREFIX_VEX_0F67,
1146   PREFIX_VEX_0F68,
1147   PREFIX_VEX_0F69,
1148   PREFIX_VEX_0F6A,
1149   PREFIX_VEX_0F6B,
1150   PREFIX_VEX_0F6C,
1151   PREFIX_VEX_0F6D,
1152   PREFIX_VEX_0F6E,
1153   PREFIX_VEX_0F6F,
1154   PREFIX_VEX_0F70,
1155   PREFIX_VEX_0F71_REG_2,
1156   PREFIX_VEX_0F71_REG_4,
1157   PREFIX_VEX_0F71_REG_6,
1158   PREFIX_VEX_0F72_REG_2,
1159   PREFIX_VEX_0F72_REG_4,
1160   PREFIX_VEX_0F72_REG_6,
1161   PREFIX_VEX_0F73_REG_2,
1162   PREFIX_VEX_0F73_REG_3,
1163   PREFIX_VEX_0F73_REG_6,
1164   PREFIX_VEX_0F73_REG_7,
1165   PREFIX_VEX_0F74,
1166   PREFIX_VEX_0F75,
1167   PREFIX_VEX_0F76,
1168   PREFIX_VEX_0F77,
1169   PREFIX_VEX_0F7C,
1170   PREFIX_VEX_0F7D,
1171   PREFIX_VEX_0F7E,
1172   PREFIX_VEX_0F7F,
1173   PREFIX_VEX_0F90,
1174   PREFIX_VEX_0F91,
1175   PREFIX_VEX_0F92,
1176   PREFIX_VEX_0F93,
1177   PREFIX_VEX_0F98,
1178   PREFIX_VEX_0F99,
1179   PREFIX_VEX_0FC2,
1180   PREFIX_VEX_0FC4,
1181   PREFIX_VEX_0FC5,
1182   PREFIX_VEX_0FD0,
1183   PREFIX_VEX_0FD1,
1184   PREFIX_VEX_0FD2,
1185   PREFIX_VEX_0FD3,
1186   PREFIX_VEX_0FD4,
1187   PREFIX_VEX_0FD5,
1188   PREFIX_VEX_0FD6,
1189   PREFIX_VEX_0FD7,
1190   PREFIX_VEX_0FD8,
1191   PREFIX_VEX_0FD9,
1192   PREFIX_VEX_0FDA,
1193   PREFIX_VEX_0FDB,
1194   PREFIX_VEX_0FDC,
1195   PREFIX_VEX_0FDD,
1196   PREFIX_VEX_0FDE,
1197   PREFIX_VEX_0FDF,
1198   PREFIX_VEX_0FE0,
1199   PREFIX_VEX_0FE1,
1200   PREFIX_VEX_0FE2,
1201   PREFIX_VEX_0FE3,
1202   PREFIX_VEX_0FE4,
1203   PREFIX_VEX_0FE5,
1204   PREFIX_VEX_0FE6,
1205   PREFIX_VEX_0FE7,
1206   PREFIX_VEX_0FE8,
1207   PREFIX_VEX_0FE9,
1208   PREFIX_VEX_0FEA,
1209   PREFIX_VEX_0FEB,
1210   PREFIX_VEX_0FEC,
1211   PREFIX_VEX_0FED,
1212   PREFIX_VEX_0FEE,
1213   PREFIX_VEX_0FEF,
1214   PREFIX_VEX_0FF0,
1215   PREFIX_VEX_0FF1,
1216   PREFIX_VEX_0FF2,
1217   PREFIX_VEX_0FF3,
1218   PREFIX_VEX_0FF4,
1219   PREFIX_VEX_0FF5,
1220   PREFIX_VEX_0FF6,
1221   PREFIX_VEX_0FF7,
1222   PREFIX_VEX_0FF8,
1223   PREFIX_VEX_0FF9,
1224   PREFIX_VEX_0FFA,
1225   PREFIX_VEX_0FFB,
1226   PREFIX_VEX_0FFC,
1227   PREFIX_VEX_0FFD,
1228   PREFIX_VEX_0FFE,
1229   PREFIX_VEX_0F3800,
1230   PREFIX_VEX_0F3801,
1231   PREFIX_VEX_0F3802,
1232   PREFIX_VEX_0F3803,
1233   PREFIX_VEX_0F3804,
1234   PREFIX_VEX_0F3805,
1235   PREFIX_VEX_0F3806,
1236   PREFIX_VEX_0F3807,
1237   PREFIX_VEX_0F3808,
1238   PREFIX_VEX_0F3809,
1239   PREFIX_VEX_0F380A,
1240   PREFIX_VEX_0F380B,
1241   PREFIX_VEX_0F380C,
1242   PREFIX_VEX_0F380D,
1243   PREFIX_VEX_0F380E,
1244   PREFIX_VEX_0F380F,
1245   PREFIX_VEX_0F3813,
1246   PREFIX_VEX_0F3816,
1247   PREFIX_VEX_0F3817,
1248   PREFIX_VEX_0F3818,
1249   PREFIX_VEX_0F3819,
1250   PREFIX_VEX_0F381A,
1251   PREFIX_VEX_0F381C,
1252   PREFIX_VEX_0F381D,
1253   PREFIX_VEX_0F381E,
1254   PREFIX_VEX_0F3820,
1255   PREFIX_VEX_0F3821,
1256   PREFIX_VEX_0F3822,
1257   PREFIX_VEX_0F3823,
1258   PREFIX_VEX_0F3824,
1259   PREFIX_VEX_0F3825,
1260   PREFIX_VEX_0F3828,
1261   PREFIX_VEX_0F3829,
1262   PREFIX_VEX_0F382A,
1263   PREFIX_VEX_0F382B,
1264   PREFIX_VEX_0F382C,
1265   PREFIX_VEX_0F382D,
1266   PREFIX_VEX_0F382E,
1267   PREFIX_VEX_0F382F,
1268   PREFIX_VEX_0F3830,
1269   PREFIX_VEX_0F3831,
1270   PREFIX_VEX_0F3832,
1271   PREFIX_VEX_0F3833,
1272   PREFIX_VEX_0F3834,
1273   PREFIX_VEX_0F3835,
1274   PREFIX_VEX_0F3836,
1275   PREFIX_VEX_0F3837,
1276   PREFIX_VEX_0F3838,
1277   PREFIX_VEX_0F3839,
1278   PREFIX_VEX_0F383A,
1279   PREFIX_VEX_0F383B,
1280   PREFIX_VEX_0F383C,
1281   PREFIX_VEX_0F383D,
1282   PREFIX_VEX_0F383E,
1283   PREFIX_VEX_0F383F,
1284   PREFIX_VEX_0F3840,
1285   PREFIX_VEX_0F3841,
1286   PREFIX_VEX_0F3845,
1287   PREFIX_VEX_0F3846,
1288   PREFIX_VEX_0F3847,
1289   PREFIX_VEX_0F3849_X86_64,
1290   PREFIX_VEX_0F384B_X86_64,
1291   PREFIX_VEX_0F3858,
1292   PREFIX_VEX_0F3859,
1293   PREFIX_VEX_0F385A,
1294   PREFIX_VEX_0F385C_X86_64,
1295   PREFIX_VEX_0F385E_X86_64,
1296   PREFIX_VEX_0F3878,
1297   PREFIX_VEX_0F3879,
1298   PREFIX_VEX_0F388C,
1299   PREFIX_VEX_0F388E,
1300   PREFIX_VEX_0F3890,
1301   PREFIX_VEX_0F3891,
1302   PREFIX_VEX_0F3892,
1303   PREFIX_VEX_0F3893,
1304   PREFIX_VEX_0F3896,
1305   PREFIX_VEX_0F3897,
1306   PREFIX_VEX_0F3898,
1307   PREFIX_VEX_0F3899,
1308   PREFIX_VEX_0F389A,
1309   PREFIX_VEX_0F389B,
1310   PREFIX_VEX_0F389C,
1311   PREFIX_VEX_0F389D,
1312   PREFIX_VEX_0F389E,
1313   PREFIX_VEX_0F389F,
1314   PREFIX_VEX_0F38A6,
1315   PREFIX_VEX_0F38A7,
1316   PREFIX_VEX_0F38A8,
1317   PREFIX_VEX_0F38A9,
1318   PREFIX_VEX_0F38AA,
1319   PREFIX_VEX_0F38AB,
1320   PREFIX_VEX_0F38AC,
1321   PREFIX_VEX_0F38AD,
1322   PREFIX_VEX_0F38AE,
1323   PREFIX_VEX_0F38AF,
1324   PREFIX_VEX_0F38B6,
1325   PREFIX_VEX_0F38B7,
1326   PREFIX_VEX_0F38B8,
1327   PREFIX_VEX_0F38B9,
1328   PREFIX_VEX_0F38BA,
1329   PREFIX_VEX_0F38BB,
1330   PREFIX_VEX_0F38BC,
1331   PREFIX_VEX_0F38BD,
1332   PREFIX_VEX_0F38BE,
1333   PREFIX_VEX_0F38BF,
1334   PREFIX_VEX_0F38CF,
1335   PREFIX_VEX_0F38DB,
1336   PREFIX_VEX_0F38DC,
1337   PREFIX_VEX_0F38DD,
1338   PREFIX_VEX_0F38DE,
1339   PREFIX_VEX_0F38DF,
1340   PREFIX_VEX_0F38F2,
1341   PREFIX_VEX_0F38F3_REG_1,
1342   PREFIX_VEX_0F38F3_REG_2,
1343   PREFIX_VEX_0F38F3_REG_3,
1344   PREFIX_VEX_0F38F5,
1345   PREFIX_VEX_0F38F6,
1346   PREFIX_VEX_0F38F7,
1347   PREFIX_VEX_0F3A00,
1348   PREFIX_VEX_0F3A01,
1349   PREFIX_VEX_0F3A02,
1350   PREFIX_VEX_0F3A04,
1351   PREFIX_VEX_0F3A05,
1352   PREFIX_VEX_0F3A06,
1353   PREFIX_VEX_0F3A08,
1354   PREFIX_VEX_0F3A09,
1355   PREFIX_VEX_0F3A0A,
1356   PREFIX_VEX_0F3A0B,
1357   PREFIX_VEX_0F3A0C,
1358   PREFIX_VEX_0F3A0D,
1359   PREFIX_VEX_0F3A0E,
1360   PREFIX_VEX_0F3A0F,
1361   PREFIX_VEX_0F3A14,
1362   PREFIX_VEX_0F3A15,
1363   PREFIX_VEX_0F3A16,
1364   PREFIX_VEX_0F3A17,
1365   PREFIX_VEX_0F3A18,
1366   PREFIX_VEX_0F3A19,
1367   PREFIX_VEX_0F3A1D,
1368   PREFIX_VEX_0F3A20,
1369   PREFIX_VEX_0F3A21,
1370   PREFIX_VEX_0F3A22,
1371   PREFIX_VEX_0F3A30,
1372   PREFIX_VEX_0F3A31,
1373   PREFIX_VEX_0F3A32,
1374   PREFIX_VEX_0F3A33,
1375   PREFIX_VEX_0F3A38,
1376   PREFIX_VEX_0F3A39,
1377   PREFIX_VEX_0F3A40,
1378   PREFIX_VEX_0F3A41,
1379   PREFIX_VEX_0F3A42,
1380   PREFIX_VEX_0F3A44,
1381   PREFIX_VEX_0F3A46,
1382   PREFIX_VEX_0F3A48,
1383   PREFIX_VEX_0F3A49,
1384   PREFIX_VEX_0F3A4A,
1385   PREFIX_VEX_0F3A4B,
1386   PREFIX_VEX_0F3A4C,
1387   PREFIX_VEX_0F3A5C,
1388   PREFIX_VEX_0F3A5D,
1389   PREFIX_VEX_0F3A5E,
1390   PREFIX_VEX_0F3A5F,
1391   PREFIX_VEX_0F3A60,
1392   PREFIX_VEX_0F3A61,
1393   PREFIX_VEX_0F3A62,
1394   PREFIX_VEX_0F3A63,
1395   PREFIX_VEX_0F3A68,
1396   PREFIX_VEX_0F3A69,
1397   PREFIX_VEX_0F3A6A,
1398   PREFIX_VEX_0F3A6B,
1399   PREFIX_VEX_0F3A6C,
1400   PREFIX_VEX_0F3A6D,
1401   PREFIX_VEX_0F3A6E,
1402   PREFIX_VEX_0F3A6F,
1403   PREFIX_VEX_0F3A78,
1404   PREFIX_VEX_0F3A79,
1405   PREFIX_VEX_0F3A7A,
1406   PREFIX_VEX_0F3A7B,
1407   PREFIX_VEX_0F3A7C,
1408   PREFIX_VEX_0F3A7D,
1409   PREFIX_VEX_0F3A7E,
1410   PREFIX_VEX_0F3A7F,
1411   PREFIX_VEX_0F3ACE,
1412   PREFIX_VEX_0F3ACF,
1413   PREFIX_VEX_0F3ADF,
1414   PREFIX_VEX_0F3AF0,
1415
1416   PREFIX_EVEX_0F10,
1417   PREFIX_EVEX_0F11,
1418   PREFIX_EVEX_0F12,
1419   PREFIX_EVEX_0F16,
1420   PREFIX_EVEX_0F2A,
1421   PREFIX_EVEX_0F2C,
1422   PREFIX_EVEX_0F2D,
1423   PREFIX_EVEX_0F2E,
1424   PREFIX_EVEX_0F2F,
1425   PREFIX_EVEX_0F51,
1426   PREFIX_EVEX_0F58,
1427   PREFIX_EVEX_0F59,
1428   PREFIX_EVEX_0F5A,
1429   PREFIX_EVEX_0F5B,
1430   PREFIX_EVEX_0F5C,
1431   PREFIX_EVEX_0F5D,
1432   PREFIX_EVEX_0F5E,
1433   PREFIX_EVEX_0F5F,
1434   PREFIX_EVEX_0F64,
1435   PREFIX_EVEX_0F65,
1436   PREFIX_EVEX_0F66,
1437   PREFIX_EVEX_0F6E,
1438   PREFIX_EVEX_0F6F,
1439   PREFIX_EVEX_0F70,
1440   PREFIX_EVEX_0F71_REG_2,
1441   PREFIX_EVEX_0F71_REG_4,
1442   PREFIX_EVEX_0F71_REG_6,
1443   PREFIX_EVEX_0F72_REG_0,
1444   PREFIX_EVEX_0F72_REG_1,
1445   PREFIX_EVEX_0F72_REG_2,
1446   PREFIX_EVEX_0F72_REG_4,
1447   PREFIX_EVEX_0F72_REG_6,
1448   PREFIX_EVEX_0F73_REG_2,
1449   PREFIX_EVEX_0F73_REG_3,
1450   PREFIX_EVEX_0F73_REG_6,
1451   PREFIX_EVEX_0F73_REG_7,
1452   PREFIX_EVEX_0F74,
1453   PREFIX_EVEX_0F75,
1454   PREFIX_EVEX_0F76,
1455   PREFIX_EVEX_0F78,
1456   PREFIX_EVEX_0F79,
1457   PREFIX_EVEX_0F7A,
1458   PREFIX_EVEX_0F7B,
1459   PREFIX_EVEX_0F7E,
1460   PREFIX_EVEX_0F7F,
1461   PREFIX_EVEX_0FC2,
1462   PREFIX_EVEX_0FC4,
1463   PREFIX_EVEX_0FC5,
1464   PREFIX_EVEX_0FD6,
1465   PREFIX_EVEX_0FDB,
1466   PREFIX_EVEX_0FDF,
1467   PREFIX_EVEX_0FE2,
1468   PREFIX_EVEX_0FE6,
1469   PREFIX_EVEX_0FE7,
1470   PREFIX_EVEX_0FEB,
1471   PREFIX_EVEX_0FEF,
1472   PREFIX_EVEX_0F380D,
1473   PREFIX_EVEX_0F3810,
1474   PREFIX_EVEX_0F3811,
1475   PREFIX_EVEX_0F3812,
1476   PREFIX_EVEX_0F3813,
1477   PREFIX_EVEX_0F3814,
1478   PREFIX_EVEX_0F3815,
1479   PREFIX_EVEX_0F3816,
1480   PREFIX_EVEX_0F3819,
1481   PREFIX_EVEX_0F381A,
1482   PREFIX_EVEX_0F381B,
1483   PREFIX_EVEX_0F381E,
1484   PREFIX_EVEX_0F381F,
1485   PREFIX_EVEX_0F3820,
1486   PREFIX_EVEX_0F3821,
1487   PREFIX_EVEX_0F3822,
1488   PREFIX_EVEX_0F3823,
1489   PREFIX_EVEX_0F3824,
1490   PREFIX_EVEX_0F3825,
1491   PREFIX_EVEX_0F3826,
1492   PREFIX_EVEX_0F3827,
1493   PREFIX_EVEX_0F3828,
1494   PREFIX_EVEX_0F3829,
1495   PREFIX_EVEX_0F382A,
1496   PREFIX_EVEX_0F382C,
1497   PREFIX_EVEX_0F382D,
1498   PREFIX_EVEX_0F3830,
1499   PREFIX_EVEX_0F3831,
1500   PREFIX_EVEX_0F3832,
1501   PREFIX_EVEX_0F3833,
1502   PREFIX_EVEX_0F3834,
1503   PREFIX_EVEX_0F3835,
1504   PREFIX_EVEX_0F3836,
1505   PREFIX_EVEX_0F3837,
1506   PREFIX_EVEX_0F3838,
1507   PREFIX_EVEX_0F3839,
1508   PREFIX_EVEX_0F383A,
1509   PREFIX_EVEX_0F383B,
1510   PREFIX_EVEX_0F383D,
1511   PREFIX_EVEX_0F383F,
1512   PREFIX_EVEX_0F3840,
1513   PREFIX_EVEX_0F3842,
1514   PREFIX_EVEX_0F3843,
1515   PREFIX_EVEX_0F3844,
1516   PREFIX_EVEX_0F3845,
1517   PREFIX_EVEX_0F3846,
1518   PREFIX_EVEX_0F3847,
1519   PREFIX_EVEX_0F384C,
1520   PREFIX_EVEX_0F384D,
1521   PREFIX_EVEX_0F384E,
1522   PREFIX_EVEX_0F384F,
1523   PREFIX_EVEX_0F3850,
1524   PREFIX_EVEX_0F3851,
1525   PREFIX_EVEX_0F3852,
1526   PREFIX_EVEX_0F3853,
1527   PREFIX_EVEX_0F3854,
1528   PREFIX_EVEX_0F3855,
1529   PREFIX_EVEX_0F3859,
1530   PREFIX_EVEX_0F385A,
1531   PREFIX_EVEX_0F385B,
1532   PREFIX_EVEX_0F3862,
1533   PREFIX_EVEX_0F3863,
1534   PREFIX_EVEX_0F3864,
1535   PREFIX_EVEX_0F3865,
1536   PREFIX_EVEX_0F3866,
1537   PREFIX_EVEX_0F3868,
1538   PREFIX_EVEX_0F3870,
1539   PREFIX_EVEX_0F3871,
1540   PREFIX_EVEX_0F3872,
1541   PREFIX_EVEX_0F3873,
1542   PREFIX_EVEX_0F3875,
1543   PREFIX_EVEX_0F3876,
1544   PREFIX_EVEX_0F3877,
1545   PREFIX_EVEX_0F387A,
1546   PREFIX_EVEX_0F387B,
1547   PREFIX_EVEX_0F387C,
1548   PREFIX_EVEX_0F387D,
1549   PREFIX_EVEX_0F387E,
1550   PREFIX_EVEX_0F387F,
1551   PREFIX_EVEX_0F3883,
1552   PREFIX_EVEX_0F3888,
1553   PREFIX_EVEX_0F3889,
1554   PREFIX_EVEX_0F388A,
1555   PREFIX_EVEX_0F388B,
1556   PREFIX_EVEX_0F388D,
1557   PREFIX_EVEX_0F388F,
1558   PREFIX_EVEX_0F3890,
1559   PREFIX_EVEX_0F3891,
1560   PREFIX_EVEX_0F3892,
1561   PREFIX_EVEX_0F3893,
1562   PREFIX_EVEX_0F389A,
1563   PREFIX_EVEX_0F389B,
1564   PREFIX_EVEX_0F38A0,
1565   PREFIX_EVEX_0F38A1,
1566   PREFIX_EVEX_0F38A2,
1567   PREFIX_EVEX_0F38A3,
1568   PREFIX_EVEX_0F38AA,
1569   PREFIX_EVEX_0F38AB,
1570   PREFIX_EVEX_0F38B4,
1571   PREFIX_EVEX_0F38B5,
1572   PREFIX_EVEX_0F38C4,
1573   PREFIX_EVEX_0F38C6_REG_1,
1574   PREFIX_EVEX_0F38C6_REG_2,
1575   PREFIX_EVEX_0F38C6_REG_5,
1576   PREFIX_EVEX_0F38C6_REG_6,
1577   PREFIX_EVEX_0F38C7_REG_1,
1578   PREFIX_EVEX_0F38C7_REG_2,
1579   PREFIX_EVEX_0F38C7_REG_5,
1580   PREFIX_EVEX_0F38C7_REG_6,
1581   PREFIX_EVEX_0F38C8,
1582   PREFIX_EVEX_0F38CA,
1583   PREFIX_EVEX_0F38CB,
1584   PREFIX_EVEX_0F38CC,
1585   PREFIX_EVEX_0F38CD,
1586
1587   PREFIX_EVEX_0F3A00,
1588   PREFIX_EVEX_0F3A01,
1589   PREFIX_EVEX_0F3A03,
1590   PREFIX_EVEX_0F3A05,
1591   PREFIX_EVEX_0F3A08,
1592   PREFIX_EVEX_0F3A09,
1593   PREFIX_EVEX_0F3A0A,
1594   PREFIX_EVEX_0F3A0B,
1595   PREFIX_EVEX_0F3A14,
1596   PREFIX_EVEX_0F3A15,
1597   PREFIX_EVEX_0F3A16,
1598   PREFIX_EVEX_0F3A17,
1599   PREFIX_EVEX_0F3A18,
1600   PREFIX_EVEX_0F3A19,
1601   PREFIX_EVEX_0F3A1A,
1602   PREFIX_EVEX_0F3A1B,
1603   PREFIX_EVEX_0F3A1E,
1604   PREFIX_EVEX_0F3A1F,
1605   PREFIX_EVEX_0F3A20,
1606   PREFIX_EVEX_0F3A21,
1607   PREFIX_EVEX_0F3A22,
1608   PREFIX_EVEX_0F3A23,
1609   PREFIX_EVEX_0F3A25,
1610   PREFIX_EVEX_0F3A26,
1611   PREFIX_EVEX_0F3A27,
1612   PREFIX_EVEX_0F3A38,
1613   PREFIX_EVEX_0F3A39,
1614   PREFIX_EVEX_0F3A3A,
1615   PREFIX_EVEX_0F3A3B,
1616   PREFIX_EVEX_0F3A3E,
1617   PREFIX_EVEX_0F3A3F,
1618   PREFIX_EVEX_0F3A42,
1619   PREFIX_EVEX_0F3A43,
1620   PREFIX_EVEX_0F3A50,
1621   PREFIX_EVEX_0F3A51,
1622   PREFIX_EVEX_0F3A54,
1623   PREFIX_EVEX_0F3A55,
1624   PREFIX_EVEX_0F3A56,
1625   PREFIX_EVEX_0F3A57,
1626   PREFIX_EVEX_0F3A66,
1627   PREFIX_EVEX_0F3A67,
1628   PREFIX_EVEX_0F3A70,
1629   PREFIX_EVEX_0F3A71,
1630   PREFIX_EVEX_0F3A72,
1631   PREFIX_EVEX_0F3A73,
1632 };
1633
1634 enum
1635 {
1636   X86_64_06 = 0,
1637   X86_64_07,
1638   X86_64_0E,
1639   X86_64_16,
1640   X86_64_17,
1641   X86_64_1E,
1642   X86_64_1F,
1643   X86_64_27,
1644   X86_64_2F,
1645   X86_64_37,
1646   X86_64_3F,
1647   X86_64_60,
1648   X86_64_61,
1649   X86_64_62,
1650   X86_64_63,
1651   X86_64_6D,
1652   X86_64_6F,
1653   X86_64_82,
1654   X86_64_9A,
1655   X86_64_C2,
1656   X86_64_C3,
1657   X86_64_C4,
1658   X86_64_C5,
1659   X86_64_CE,
1660   X86_64_D4,
1661   X86_64_D5,
1662   X86_64_E8,
1663   X86_64_E9,
1664   X86_64_EA,
1665   X86_64_0F01_REG_0,
1666   X86_64_0F01_REG_1,
1667   X86_64_0F01_REG_2,
1668   X86_64_0F01_REG_3,
1669   X86_64_VEX_0F3849,
1670   X86_64_VEX_0F384B,
1671   X86_64_VEX_0F385C,
1672   X86_64_VEX_0F385E
1673 };
1674
1675 enum
1676 {
1677   THREE_BYTE_0F38 = 0,
1678   THREE_BYTE_0F3A
1679 };
1680
1681 enum
1682 {
1683   XOP_08 = 0,
1684   XOP_09,
1685   XOP_0A
1686 };
1687
1688 enum
1689 {
1690   VEX_0F = 0,
1691   VEX_0F38,
1692   VEX_0F3A
1693 };
1694
1695 enum
1696 {
1697   EVEX_0F = 0,
1698   EVEX_0F38,
1699   EVEX_0F3A
1700 };
1701
1702 enum
1703 {
1704   VEX_LEN_0F12_P_0_M_0 = 0,
1705   VEX_LEN_0F12_P_0_M_1,
1706 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1707   VEX_LEN_0F13_M_0,
1708   VEX_LEN_0F16_P_0_M_0,
1709   VEX_LEN_0F16_P_0_M_1,
1710 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1711   VEX_LEN_0F17_M_0,
1712   VEX_LEN_0F41_P_0,
1713   VEX_LEN_0F41_P_2,
1714   VEX_LEN_0F42_P_0,
1715   VEX_LEN_0F42_P_2,
1716   VEX_LEN_0F44_P_0,
1717   VEX_LEN_0F44_P_2,
1718   VEX_LEN_0F45_P_0,
1719   VEX_LEN_0F45_P_2,
1720   VEX_LEN_0F46_P_0,
1721   VEX_LEN_0F46_P_2,
1722   VEX_LEN_0F47_P_0,
1723   VEX_LEN_0F47_P_2,
1724   VEX_LEN_0F4A_P_0,
1725   VEX_LEN_0F4A_P_2,
1726   VEX_LEN_0F4B_P_0,
1727   VEX_LEN_0F4B_P_2,
1728   VEX_LEN_0F6E_P_2,
1729   VEX_LEN_0F77_P_0,
1730   VEX_LEN_0F7E_P_1,
1731   VEX_LEN_0F7E_P_2,
1732   VEX_LEN_0F90_P_0,
1733   VEX_LEN_0F90_P_2,
1734   VEX_LEN_0F91_P_0,
1735   VEX_LEN_0F91_P_2,
1736   VEX_LEN_0F92_P_0,
1737   VEX_LEN_0F92_P_2,
1738   VEX_LEN_0F92_P_3,
1739   VEX_LEN_0F93_P_0,
1740   VEX_LEN_0F93_P_2,
1741   VEX_LEN_0F93_P_3,
1742   VEX_LEN_0F98_P_0,
1743   VEX_LEN_0F98_P_2,
1744   VEX_LEN_0F99_P_0,
1745   VEX_LEN_0F99_P_2,
1746   VEX_LEN_0FAE_R_2_M_0,
1747   VEX_LEN_0FAE_R_3_M_0,
1748   VEX_LEN_0FC4_P_2,
1749   VEX_LEN_0FC5_P_2,
1750   VEX_LEN_0FD6_P_2,
1751   VEX_LEN_0FF7_P_2,
1752   VEX_LEN_0F3816_P_2,
1753   VEX_LEN_0F3819_P_2,
1754   VEX_LEN_0F381A_P_2_M_0,
1755   VEX_LEN_0F3836_P_2,
1756   VEX_LEN_0F3841_P_2,
1757   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1758   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1759   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1760   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1761   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1762   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1763   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1764   VEX_LEN_0F385A_P_2_M_0,
1765   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1766   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1767   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1768   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1769   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1770   VEX_LEN_0F38DB_P_2,
1771   VEX_LEN_0F38F2_P_0,
1772   VEX_LEN_0F38F3_R_1_P_0,
1773   VEX_LEN_0F38F3_R_2_P_0,
1774   VEX_LEN_0F38F3_R_3_P_0,
1775   VEX_LEN_0F38F5_P_0,
1776   VEX_LEN_0F38F5_P_1,
1777   VEX_LEN_0F38F5_P_3,
1778   VEX_LEN_0F38F6_P_3,
1779   VEX_LEN_0F38F7_P_0,
1780   VEX_LEN_0F38F7_P_1,
1781   VEX_LEN_0F38F7_P_2,
1782   VEX_LEN_0F38F7_P_3,
1783   VEX_LEN_0F3A00_P_2,
1784   VEX_LEN_0F3A01_P_2,
1785   VEX_LEN_0F3A06_P_2,
1786   VEX_LEN_0F3A14_P_2,
1787   VEX_LEN_0F3A15_P_2,
1788   VEX_LEN_0F3A16_P_2,
1789   VEX_LEN_0F3A17_P_2,
1790   VEX_LEN_0F3A18_P_2,
1791   VEX_LEN_0F3A19_P_2,
1792   VEX_LEN_0F3A20_P_2,
1793   VEX_LEN_0F3A21_P_2,
1794   VEX_LEN_0F3A22_P_2,
1795   VEX_LEN_0F3A30_P_2,
1796   VEX_LEN_0F3A31_P_2,
1797   VEX_LEN_0F3A32_P_2,
1798   VEX_LEN_0F3A33_P_2,
1799   VEX_LEN_0F3A38_P_2,
1800   VEX_LEN_0F3A39_P_2,
1801   VEX_LEN_0F3A41_P_2,
1802   VEX_LEN_0F3A46_P_2,
1803   VEX_LEN_0F3A60_P_2,
1804   VEX_LEN_0F3A61_P_2,
1805   VEX_LEN_0F3A62_P_2,
1806   VEX_LEN_0F3A63_P_2,
1807   VEX_LEN_0F3ADF_P_2,
1808   VEX_LEN_0F3AF0_P_3,
1809   VEX_LEN_0FXOP_08_85,
1810   VEX_LEN_0FXOP_08_86,
1811   VEX_LEN_0FXOP_08_87,
1812   VEX_LEN_0FXOP_08_8E,
1813   VEX_LEN_0FXOP_08_8F,
1814   VEX_LEN_0FXOP_08_95,
1815   VEX_LEN_0FXOP_08_96,
1816   VEX_LEN_0FXOP_08_97,
1817   VEX_LEN_0FXOP_08_9E,
1818   VEX_LEN_0FXOP_08_9F,
1819   VEX_LEN_0FXOP_08_A3,
1820   VEX_LEN_0FXOP_08_A6,
1821   VEX_LEN_0FXOP_08_B6,
1822   VEX_LEN_0FXOP_08_C0,
1823   VEX_LEN_0FXOP_08_C1,
1824   VEX_LEN_0FXOP_08_C2,
1825   VEX_LEN_0FXOP_08_C3,
1826   VEX_LEN_0FXOP_08_CC,
1827   VEX_LEN_0FXOP_08_CD,
1828   VEX_LEN_0FXOP_08_CE,
1829   VEX_LEN_0FXOP_08_CF,
1830   VEX_LEN_0FXOP_08_EC,
1831   VEX_LEN_0FXOP_08_ED,
1832   VEX_LEN_0FXOP_08_EE,
1833   VEX_LEN_0FXOP_08_EF,
1834   VEX_LEN_0FXOP_09_01,
1835   VEX_LEN_0FXOP_09_02,
1836   VEX_LEN_0FXOP_09_12_M_1,
1837   VEX_LEN_0FXOP_09_82_W_0,
1838   VEX_LEN_0FXOP_09_83_W_0,
1839   VEX_LEN_0FXOP_09_90,
1840   VEX_LEN_0FXOP_09_91,
1841   VEX_LEN_0FXOP_09_92,
1842   VEX_LEN_0FXOP_09_93,
1843   VEX_LEN_0FXOP_09_94,
1844   VEX_LEN_0FXOP_09_95,
1845   VEX_LEN_0FXOP_09_96,
1846   VEX_LEN_0FXOP_09_97,
1847   VEX_LEN_0FXOP_09_98,
1848   VEX_LEN_0FXOP_09_99,
1849   VEX_LEN_0FXOP_09_9A,
1850   VEX_LEN_0FXOP_09_9B,
1851   VEX_LEN_0FXOP_09_C1,
1852   VEX_LEN_0FXOP_09_C2,
1853   VEX_LEN_0FXOP_09_C3,
1854   VEX_LEN_0FXOP_09_C6,
1855   VEX_LEN_0FXOP_09_C7,
1856   VEX_LEN_0FXOP_09_CB,
1857   VEX_LEN_0FXOP_09_D1,
1858   VEX_LEN_0FXOP_09_D2,
1859   VEX_LEN_0FXOP_09_D3,
1860   VEX_LEN_0FXOP_09_D6,
1861   VEX_LEN_0FXOP_09_D7,
1862   VEX_LEN_0FXOP_09_DB,
1863   VEX_LEN_0FXOP_09_E1,
1864   VEX_LEN_0FXOP_09_E2,
1865   VEX_LEN_0FXOP_09_E3,
1866   VEX_LEN_0FXOP_0A_12,
1867 };
1868
1869 enum
1870 {
1871   EVEX_LEN_0F6E_P_2 = 0,
1872   EVEX_LEN_0F7E_P_1,
1873   EVEX_LEN_0F7E_P_2,
1874   EVEX_LEN_0FC4_P_2,
1875   EVEX_LEN_0FC5_P_2,
1876   EVEX_LEN_0FD6_P_2,
1877   EVEX_LEN_0F3816_P_2,
1878   EVEX_LEN_0F3819_P_2_W_0,
1879   EVEX_LEN_0F3819_P_2_W_1,
1880   EVEX_LEN_0F381A_P_2_W_0_M_0,
1881   EVEX_LEN_0F381A_P_2_W_1_M_0,
1882   EVEX_LEN_0F381B_P_2_W_0_M_0,
1883   EVEX_LEN_0F381B_P_2_W_1_M_0,
1884   EVEX_LEN_0F3836_P_2,
1885   EVEX_LEN_0F385A_P_2_W_0_M_0,
1886   EVEX_LEN_0F385A_P_2_W_1_M_0,
1887   EVEX_LEN_0F385B_P_2_W_0_M_0,
1888   EVEX_LEN_0F385B_P_2_W_1_M_0,
1889   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1890   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1891   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1892   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1893   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1894   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1895   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1896   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1897   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1898   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1899   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1900   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1901   EVEX_LEN_0F3A00_P_2_W_1,
1902   EVEX_LEN_0F3A01_P_2_W_1,
1903   EVEX_LEN_0F3A14_P_2,
1904   EVEX_LEN_0F3A15_P_2,
1905   EVEX_LEN_0F3A16_P_2,
1906   EVEX_LEN_0F3A17_P_2,
1907   EVEX_LEN_0F3A18_P_2_W_0,
1908   EVEX_LEN_0F3A18_P_2_W_1,
1909   EVEX_LEN_0F3A19_P_2_W_0,
1910   EVEX_LEN_0F3A19_P_2_W_1,
1911   EVEX_LEN_0F3A1A_P_2_W_0,
1912   EVEX_LEN_0F3A1A_P_2_W_1,
1913   EVEX_LEN_0F3A1B_P_2_W_0,
1914   EVEX_LEN_0F3A1B_P_2_W_1,
1915   EVEX_LEN_0F3A20_P_2,
1916   EVEX_LEN_0F3A21_P_2_W_0,
1917   EVEX_LEN_0F3A22_P_2,
1918   EVEX_LEN_0F3A23_P_2_W_0,
1919   EVEX_LEN_0F3A23_P_2_W_1,
1920   EVEX_LEN_0F3A38_P_2_W_0,
1921   EVEX_LEN_0F3A38_P_2_W_1,
1922   EVEX_LEN_0F3A39_P_2_W_0,
1923   EVEX_LEN_0F3A39_P_2_W_1,
1924   EVEX_LEN_0F3A3A_P_2_W_0,
1925   EVEX_LEN_0F3A3A_P_2_W_1,
1926   EVEX_LEN_0F3A3B_P_2_W_0,
1927   EVEX_LEN_0F3A3B_P_2_W_1,
1928   EVEX_LEN_0F3A43_P_2_W_0,
1929   EVEX_LEN_0F3A43_P_2_W_1
1930 };
1931
1932 enum
1933 {
1934   VEX_W_0F41_P_0_LEN_1 = 0,
1935   VEX_W_0F41_P_2_LEN_1,
1936   VEX_W_0F42_P_0_LEN_1,
1937   VEX_W_0F42_P_2_LEN_1,
1938   VEX_W_0F44_P_0_LEN_0,
1939   VEX_W_0F44_P_2_LEN_0,
1940   VEX_W_0F45_P_0_LEN_1,
1941   VEX_W_0F45_P_2_LEN_1,
1942   VEX_W_0F46_P_0_LEN_1,
1943   VEX_W_0F46_P_2_LEN_1,
1944   VEX_W_0F47_P_0_LEN_1,
1945   VEX_W_0F47_P_2_LEN_1,
1946   VEX_W_0F4A_P_0_LEN_1,
1947   VEX_W_0F4A_P_2_LEN_1,
1948   VEX_W_0F4B_P_0_LEN_1,
1949   VEX_W_0F4B_P_2_LEN_1,
1950   VEX_W_0F90_P_0_LEN_0,
1951   VEX_W_0F90_P_2_LEN_0,
1952   VEX_W_0F91_P_0_LEN_0,
1953   VEX_W_0F91_P_2_LEN_0,
1954   VEX_W_0F92_P_0_LEN_0,
1955   VEX_W_0F92_P_2_LEN_0,
1956   VEX_W_0F93_P_0_LEN_0,
1957   VEX_W_0F93_P_2_LEN_0,
1958   VEX_W_0F98_P_0_LEN_0,
1959   VEX_W_0F98_P_2_LEN_0,
1960   VEX_W_0F99_P_0_LEN_0,
1961   VEX_W_0F99_P_2_LEN_0,
1962   VEX_W_0F380C_P_2,
1963   VEX_W_0F380D_P_2,
1964   VEX_W_0F380E_P_2,
1965   VEX_W_0F380F_P_2,
1966   VEX_W_0F3813_P_2,
1967   VEX_W_0F3816_P_2,
1968   VEX_W_0F3818_P_2,
1969   VEX_W_0F3819_P_2,
1970   VEX_W_0F381A_P_2_M_0_L_0,
1971   VEX_W_0F382C_P_2_M_0,
1972   VEX_W_0F382D_P_2_M_0,
1973   VEX_W_0F382E_P_2_M_0,
1974   VEX_W_0F382F_P_2_M_0,
1975   VEX_W_0F3836_P_2,
1976   VEX_W_0F3846_P_2,
1977   VEX_W_0F3849_X86_64_P_0,
1978   VEX_W_0F3849_X86_64_P_2,
1979   VEX_W_0F3849_X86_64_P_3,
1980   VEX_W_0F384B_X86_64_P_1,
1981   VEX_W_0F384B_X86_64_P_2,
1982   VEX_W_0F384B_X86_64_P_3,
1983   VEX_W_0F3858_P_2,
1984   VEX_W_0F3859_P_2,
1985   VEX_W_0F385A_P_2_M_0_L_0,
1986   VEX_W_0F385C_X86_64_P_1,
1987   VEX_W_0F385E_X86_64_P_0,
1988   VEX_W_0F385E_X86_64_P_1,
1989   VEX_W_0F385E_X86_64_P_2,
1990   VEX_W_0F385E_X86_64_P_3,
1991   VEX_W_0F3878_P_2,
1992   VEX_W_0F3879_P_2,
1993   VEX_W_0F38CF_P_2,
1994   VEX_W_0F3A00_P_2,
1995   VEX_W_0F3A01_P_2,
1996   VEX_W_0F3A02_P_2,
1997   VEX_W_0F3A04_P_2,
1998   VEX_W_0F3A05_P_2,
1999   VEX_W_0F3A06_P_2_L_0,
2000   VEX_W_0F3A18_P_2_L_0,
2001   VEX_W_0F3A19_P_2_L_0,
2002   VEX_W_0F3A1D_P_2,
2003   VEX_W_0F3A30_P_2_LEN_0,
2004   VEX_W_0F3A31_P_2_LEN_0,
2005   VEX_W_0F3A32_P_2_LEN_0,
2006   VEX_W_0F3A33_P_2_LEN_0,
2007   VEX_W_0F3A38_P_2_L_0,
2008   VEX_W_0F3A39_P_2_L_0,
2009   VEX_W_0F3A46_P_2_L_0,
2010   VEX_W_0F3A4A_P_2,
2011   VEX_W_0F3A4B_P_2,
2012   VEX_W_0F3A4C_P_2,
2013   VEX_W_0F3ACE_P_2,
2014   VEX_W_0F3ACF_P_2,
2015
2016   VEX_W_0FXOP_08_85_L_0,
2017   VEX_W_0FXOP_08_86_L_0,
2018   VEX_W_0FXOP_08_87_L_0,
2019   VEX_W_0FXOP_08_8E_L_0,
2020   VEX_W_0FXOP_08_8F_L_0,
2021   VEX_W_0FXOP_08_95_L_0,
2022   VEX_W_0FXOP_08_96_L_0,
2023   VEX_W_0FXOP_08_97_L_0,
2024   VEX_W_0FXOP_08_9E_L_0,
2025   VEX_W_0FXOP_08_9F_L_0,
2026   VEX_W_0FXOP_08_A6_L_0,
2027   VEX_W_0FXOP_08_B6_L_0,
2028   VEX_W_0FXOP_08_C0_L_0,
2029   VEX_W_0FXOP_08_C1_L_0,
2030   VEX_W_0FXOP_08_C2_L_0,
2031   VEX_W_0FXOP_08_C3_L_0,
2032   VEX_W_0FXOP_08_CC_L_0,
2033   VEX_W_0FXOP_08_CD_L_0,
2034   VEX_W_0FXOP_08_CE_L_0,
2035   VEX_W_0FXOP_08_CF_L_0,
2036   VEX_W_0FXOP_08_EC_L_0,
2037   VEX_W_0FXOP_08_ED_L_0,
2038   VEX_W_0FXOP_08_EE_L_0,
2039   VEX_W_0FXOP_08_EF_L_0,
2040
2041   VEX_W_0FXOP_09_80,
2042   VEX_W_0FXOP_09_81,
2043   VEX_W_0FXOP_09_82,
2044   VEX_W_0FXOP_09_83,
2045   VEX_W_0FXOP_09_C1_L_0,
2046   VEX_W_0FXOP_09_C2_L_0,
2047   VEX_W_0FXOP_09_C3_L_0,
2048   VEX_W_0FXOP_09_C6_L_0,
2049   VEX_W_0FXOP_09_C7_L_0,
2050   VEX_W_0FXOP_09_CB_L_0,
2051   VEX_W_0FXOP_09_D1_L_0,
2052   VEX_W_0FXOP_09_D2_L_0,
2053   VEX_W_0FXOP_09_D3_L_0,
2054   VEX_W_0FXOP_09_D6_L_0,
2055   VEX_W_0FXOP_09_D7_L_0,
2056   VEX_W_0FXOP_09_DB_L_0,
2057   VEX_W_0FXOP_09_E1_L_0,
2058   VEX_W_0FXOP_09_E2_L_0,
2059   VEX_W_0FXOP_09_E3_L_0,
2060
2061   EVEX_W_0F10_P_1,
2062   EVEX_W_0F10_P_3,
2063   EVEX_W_0F11_P_1,
2064   EVEX_W_0F11_P_3,
2065   EVEX_W_0F12_P_0_M_1,
2066   EVEX_W_0F12_P_1,
2067   EVEX_W_0F12_P_3,
2068   EVEX_W_0F16_P_0_M_1,
2069   EVEX_W_0F16_P_1,
2070   EVEX_W_0F2A_P_3,
2071   EVEX_W_0F51_P_1,
2072   EVEX_W_0F51_P_3,
2073   EVEX_W_0F58_P_1,
2074   EVEX_W_0F58_P_3,
2075   EVEX_W_0F59_P_1,
2076   EVEX_W_0F59_P_3,
2077   EVEX_W_0F5A_P_0,
2078   EVEX_W_0F5A_P_1,
2079   EVEX_W_0F5A_P_2,
2080   EVEX_W_0F5A_P_3,
2081   EVEX_W_0F5B_P_0,
2082   EVEX_W_0F5B_P_1,
2083   EVEX_W_0F5B_P_2,
2084   EVEX_W_0F5C_P_1,
2085   EVEX_W_0F5C_P_3,
2086   EVEX_W_0F5D_P_1,
2087   EVEX_W_0F5D_P_3,
2088   EVEX_W_0F5E_P_1,
2089   EVEX_W_0F5E_P_3,
2090   EVEX_W_0F5F_P_1,
2091   EVEX_W_0F5F_P_3,
2092   EVEX_W_0F62,
2093   EVEX_W_0F66_P_2,
2094   EVEX_W_0F6A,
2095   EVEX_W_0F6B,
2096   EVEX_W_0F6C,
2097   EVEX_W_0F6D,
2098   EVEX_W_0F6F_P_1,
2099   EVEX_W_0F6F_P_2,
2100   EVEX_W_0F6F_P_3,
2101   EVEX_W_0F70_P_2,
2102   EVEX_W_0F72_R_2_P_2,
2103   EVEX_W_0F72_R_6_P_2,
2104   EVEX_W_0F73_R_2_P_2,
2105   EVEX_W_0F73_R_6_P_2,
2106   EVEX_W_0F76_P_2,
2107   EVEX_W_0F78_P_0,
2108   EVEX_W_0F78_P_2,
2109   EVEX_W_0F79_P_0,
2110   EVEX_W_0F79_P_2,
2111   EVEX_W_0F7A_P_1,
2112   EVEX_W_0F7A_P_2,
2113   EVEX_W_0F7A_P_3,
2114   EVEX_W_0F7B_P_2,
2115   EVEX_W_0F7B_P_3,
2116   EVEX_W_0F7E_P_1,
2117   EVEX_W_0F7F_P_1,
2118   EVEX_W_0F7F_P_2,
2119   EVEX_W_0F7F_P_3,
2120   EVEX_W_0FC2_P_1,
2121   EVEX_W_0FC2_P_3,
2122   EVEX_W_0FD2,
2123   EVEX_W_0FD3,
2124   EVEX_W_0FD4,
2125   EVEX_W_0FD6_P_2,
2126   EVEX_W_0FE6_P_1,
2127   EVEX_W_0FE6_P_2,
2128   EVEX_W_0FE6_P_3,
2129   EVEX_W_0FE7_P_2,
2130   EVEX_W_0FF2,
2131   EVEX_W_0FF3,
2132   EVEX_W_0FF4,
2133   EVEX_W_0FFA,
2134   EVEX_W_0FFB,
2135   EVEX_W_0FFE,
2136   EVEX_W_0F380D_P_2,
2137   EVEX_W_0F3810_P_1,
2138   EVEX_W_0F3810_P_2,
2139   EVEX_W_0F3811_P_1,
2140   EVEX_W_0F3811_P_2,
2141   EVEX_W_0F3812_P_1,
2142   EVEX_W_0F3812_P_2,
2143   EVEX_W_0F3813_P_1,
2144   EVEX_W_0F3813_P_2,
2145   EVEX_W_0F3814_P_1,
2146   EVEX_W_0F3815_P_1,
2147   EVEX_W_0F3819_P_2,
2148   EVEX_W_0F381A_P_2,
2149   EVEX_W_0F381B_P_2,
2150   EVEX_W_0F381E_P_2,
2151   EVEX_W_0F381F_P_2,
2152   EVEX_W_0F3820_P_1,
2153   EVEX_W_0F3821_P_1,
2154   EVEX_W_0F3822_P_1,
2155   EVEX_W_0F3823_P_1,
2156   EVEX_W_0F3824_P_1,
2157   EVEX_W_0F3825_P_1,
2158   EVEX_W_0F3825_P_2,
2159   EVEX_W_0F3828_P_2,
2160   EVEX_W_0F3829_P_2,
2161   EVEX_W_0F382A_P_1,
2162   EVEX_W_0F382A_P_2,
2163   EVEX_W_0F382B,
2164   EVEX_W_0F3830_P_1,
2165   EVEX_W_0F3831_P_1,
2166   EVEX_W_0F3832_P_1,
2167   EVEX_W_0F3833_P_1,
2168   EVEX_W_0F3834_P_1,
2169   EVEX_W_0F3835_P_1,
2170   EVEX_W_0F3835_P_2,
2171   EVEX_W_0F3837_P_2,
2172   EVEX_W_0F383A_P_1,
2173   EVEX_W_0F3852_P_1,
2174   EVEX_W_0F3859_P_2,
2175   EVEX_W_0F385A_P_2,
2176   EVEX_W_0F385B_P_2,
2177   EVEX_W_0F3870_P_2,
2178   EVEX_W_0F3872_P_1,
2179   EVEX_W_0F3872_P_2,
2180   EVEX_W_0F3872_P_3,
2181   EVEX_W_0F387A_P_2,
2182   EVEX_W_0F387B_P_2,
2183   EVEX_W_0F3883_P_2,
2184   EVEX_W_0F3891_P_2,
2185   EVEX_W_0F3893_P_2,
2186   EVEX_W_0F38A1_P_2,
2187   EVEX_W_0F38A3_P_2,
2188   EVEX_W_0F38C7_R_1_P_2,
2189   EVEX_W_0F38C7_R_2_P_2,
2190   EVEX_W_0F38C7_R_5_P_2,
2191   EVEX_W_0F38C7_R_6_P_2,
2192
2193   EVEX_W_0F3A00_P_2,
2194   EVEX_W_0F3A01_P_2,
2195   EVEX_W_0F3A05_P_2,
2196   EVEX_W_0F3A08_P_2,
2197   EVEX_W_0F3A09_P_2,
2198   EVEX_W_0F3A0A_P_2,
2199   EVEX_W_0F3A0B_P_2,
2200   EVEX_W_0F3A18_P_2,
2201   EVEX_W_0F3A19_P_2,
2202   EVEX_W_0F3A1A_P_2,
2203   EVEX_W_0F3A1B_P_2,
2204   EVEX_W_0F3A21_P_2,
2205   EVEX_W_0F3A23_P_2,
2206   EVEX_W_0F3A38_P_2,
2207   EVEX_W_0F3A39_P_2,
2208   EVEX_W_0F3A3A_P_2,
2209   EVEX_W_0F3A3B_P_2,
2210   EVEX_W_0F3A42_P_2,
2211   EVEX_W_0F3A43_P_2,
2212   EVEX_W_0F3A70_P_2,
2213   EVEX_W_0F3A72_P_2,
2214 };
2215
2216 typedef void (*op_rtn) (int bytemode, int sizeflag);
2217
2218 struct dis386 {
2219   const char *name;
2220   struct
2221     {
2222       op_rtn rtn;
2223       int bytemode;
2224     } op[MAX_OPERANDS];
2225   unsigned int prefix_requirement;
2226 };
2227
2228 /* Upper case letters in the instruction names here are macros.
2229    'A' => print 'b' if no register operands or suffix_always is true
2230    'B' => print 'b' if suffix_always is true
2231    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2232           size prefix
2233    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2234           suffix_always is true
2235    'E' => print 'e' if 32-bit form of jcxz
2236    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2237    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2238    'H' => print ",pt" or ",pn" branch hint
2239    'I' unused.
2240    'J' unused.
2241    'K' => print 'd' or 'q' if rex prefix is present.
2242    'L' => print 'l' if suffix_always is true
2243    'M' => print 'r' if intel_mnemonic is false.
2244    'N' => print 'n' if instruction has no wait "prefix"
2245    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2246    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2247           or suffix_always is true.  print 'q' if rex prefix is present.
2248    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2249           is true
2250    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2251    'S' => print 'w', 'l' or 'q' if suffix_always is true
2252    'T' => print 'q' in 64bit mode if instruction has no operand size
2253           prefix and behave as 'P' otherwise
2254    'U' => print 'q' in 64bit mode if instruction has no operand size
2255           prefix and behave as 'Q' otherwise
2256    'V' => print 'q' in 64bit mode if instruction has no operand size
2257           prefix and behave as 'S' otherwise
2258    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2259    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2260    'Y' unused.
2261    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2262    '!' => change condition from true to false or from false to true.
2263    '%' => add 1 upper case letter to the macro.
2264    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2265           prefix or suffix_always is true (lcall/ljmp).
2266    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2267           on operand size prefix.
2268    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2269           has no operand size prefix for AMD64 ISA, behave as 'P'
2270           otherwise
2271
2272    2 upper case letter macros:
2273    "XY" => print 'x' or 'y' if suffix_always is true or no register
2274            operands and no broadcast.
2275    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2276            register operands and no broadcast.
2277    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2278    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
2279            being false, or no operand at all in 64bit mode, or if suffix_always
2280            is true.
2281    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2282    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2283    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2284    "DQ" => print 'd' or 'q' depending on the VEX.W bit
2285    "BW" => print 'b' or 'w' depending on the EVEX.W bit
2286    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2287            an operand size prefix, or suffix_always is true.  print
2288            'q' if rex prefix is present.
2289
2290    Many of the above letters print nothing in Intel mode.  See "putop"
2291    for the details.
2292
2293    Braces '{' and '}', and vertical bars '|', indicate alternative
2294    mnemonic strings for AT&T and Intel.  */
2295
2296 static const struct dis386 dis386[] = {
2297   /* 00 */
2298   { "addB",             { Ebh1, Gb }, 0 },
2299   { "addS",             { Evh1, Gv }, 0 },
2300   { "addB",             { Gb, EbS }, 0 },
2301   { "addS",             { Gv, EvS }, 0 },
2302   { "addB",             { AL, Ib }, 0 },
2303   { "addS",             { eAX, Iv }, 0 },
2304   { X86_64_TABLE (X86_64_06) },
2305   { X86_64_TABLE (X86_64_07) },
2306   /* 08 */
2307   { "orB",              { Ebh1, Gb }, 0 },
2308   { "orS",              { Evh1, Gv }, 0 },
2309   { "orB",              { Gb, EbS }, 0 },
2310   { "orS",              { Gv, EvS }, 0 },
2311   { "orB",              { AL, Ib }, 0 },
2312   { "orS",              { eAX, Iv }, 0 },
2313   { X86_64_TABLE (X86_64_0E) },
2314   { Bad_Opcode },       /* 0x0f extended opcode escape */
2315   /* 10 */
2316   { "adcB",             { Ebh1, Gb }, 0 },
2317   { "adcS",             { Evh1, Gv }, 0 },
2318   { "adcB",             { Gb, EbS }, 0 },
2319   { "adcS",             { Gv, EvS }, 0 },
2320   { "adcB",             { AL, Ib }, 0 },
2321   { "adcS",             { eAX, Iv }, 0 },
2322   { X86_64_TABLE (X86_64_16) },
2323   { X86_64_TABLE (X86_64_17) },
2324   /* 18 */
2325   { "sbbB",             { Ebh1, Gb }, 0 },
2326   { "sbbS",             { Evh1, Gv }, 0 },
2327   { "sbbB",             { Gb, EbS }, 0 },
2328   { "sbbS",             { Gv, EvS }, 0 },
2329   { "sbbB",             { AL, Ib }, 0 },
2330   { "sbbS",             { eAX, Iv }, 0 },
2331   { X86_64_TABLE (X86_64_1E) },
2332   { X86_64_TABLE (X86_64_1F) },
2333   /* 20 */
2334   { "andB",             { Ebh1, Gb }, 0 },
2335   { "andS",             { Evh1, Gv }, 0 },
2336   { "andB",             { Gb, EbS }, 0 },
2337   { "andS",             { Gv, EvS }, 0 },
2338   { "andB",             { AL, Ib }, 0 },
2339   { "andS",             { eAX, Iv }, 0 },
2340   { Bad_Opcode },       /* SEG ES prefix */
2341   { X86_64_TABLE (X86_64_27) },
2342   /* 28 */
2343   { "subB",             { Ebh1, Gb }, 0 },
2344   { "subS",             { Evh1, Gv }, 0 },
2345   { "subB",             { Gb, EbS }, 0 },
2346   { "subS",             { Gv, EvS }, 0 },
2347   { "subB",             { AL, Ib }, 0 },
2348   { "subS",             { eAX, Iv }, 0 },
2349   { Bad_Opcode },       /* SEG CS prefix */
2350   { X86_64_TABLE (X86_64_2F) },
2351   /* 30 */
2352   { "xorB",             { Ebh1, Gb }, 0 },
2353   { "xorS",             { Evh1, Gv }, 0 },
2354   { "xorB",             { Gb, EbS }, 0 },
2355   { "xorS",             { Gv, EvS }, 0 },
2356   { "xorB",             { AL, Ib }, 0 },
2357   { "xorS",             { eAX, Iv }, 0 },
2358   { Bad_Opcode },       /* SEG SS prefix */
2359   { X86_64_TABLE (X86_64_37) },
2360   /* 38 */
2361   { "cmpB",             { Eb, Gb }, 0 },
2362   { "cmpS",             { Ev, Gv }, 0 },
2363   { "cmpB",             { Gb, EbS }, 0 },
2364   { "cmpS",             { Gv, EvS }, 0 },
2365   { "cmpB",             { AL, Ib }, 0 },
2366   { "cmpS",             { eAX, Iv }, 0 },
2367   { Bad_Opcode },       /* SEG DS prefix */
2368   { X86_64_TABLE (X86_64_3F) },
2369   /* 40 */
2370   { "inc{S|}",          { RMeAX }, 0 },
2371   { "inc{S|}",          { RMeCX }, 0 },
2372   { "inc{S|}",          { RMeDX }, 0 },
2373   { "inc{S|}",          { RMeBX }, 0 },
2374   { "inc{S|}",          { RMeSP }, 0 },
2375   { "inc{S|}",          { RMeBP }, 0 },
2376   { "inc{S|}",          { RMeSI }, 0 },
2377   { "inc{S|}",          { RMeDI }, 0 },
2378   /* 48 */
2379   { "dec{S|}",          { RMeAX }, 0 },
2380   { "dec{S|}",          { RMeCX }, 0 },
2381   { "dec{S|}",          { RMeDX }, 0 },
2382   { "dec{S|}",          { RMeBX }, 0 },
2383   { "dec{S|}",          { RMeSP }, 0 },
2384   { "dec{S|}",          { RMeBP }, 0 },
2385   { "dec{S|}",          { RMeSI }, 0 },
2386   { "dec{S|}",          { RMeDI }, 0 },
2387   /* 50 */
2388   { "pushV",            { RMrAX }, 0 },
2389   { "pushV",            { RMrCX }, 0 },
2390   { "pushV",            { RMrDX }, 0 },
2391   { "pushV",            { RMrBX }, 0 },
2392   { "pushV",            { RMrSP }, 0 },
2393   { "pushV",            { RMrBP }, 0 },
2394   { "pushV",            { RMrSI }, 0 },
2395   { "pushV",            { RMrDI }, 0 },
2396   /* 58 */
2397   { "popV",             { RMrAX }, 0 },
2398   { "popV",             { RMrCX }, 0 },
2399   { "popV",             { RMrDX }, 0 },
2400   { "popV",             { RMrBX }, 0 },
2401   { "popV",             { RMrSP }, 0 },
2402   { "popV",             { RMrBP }, 0 },
2403   { "popV",             { RMrSI }, 0 },
2404   { "popV",             { RMrDI }, 0 },
2405   /* 60 */
2406   { X86_64_TABLE (X86_64_60) },
2407   { X86_64_TABLE (X86_64_61) },
2408   { X86_64_TABLE (X86_64_62) },
2409   { X86_64_TABLE (X86_64_63) },
2410   { Bad_Opcode },       /* seg fs */
2411   { Bad_Opcode },       /* seg gs */
2412   { Bad_Opcode },       /* op size prefix */
2413   { Bad_Opcode },       /* adr size prefix */
2414   /* 68 */
2415   { "pushT",            { sIv }, 0 },
2416   { "imulS",            { Gv, Ev, Iv }, 0 },
2417   { "pushT",            { sIbT }, 0 },
2418   { "imulS",            { Gv, Ev, sIb }, 0 },
2419   { "ins{b|}",          { Ybr, indirDX }, 0 },
2420   { X86_64_TABLE (X86_64_6D) },
2421   { "outs{b|}",         { indirDXr, Xb }, 0 },
2422   { X86_64_TABLE (X86_64_6F) },
2423   /* 70 */
2424   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2425   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2426   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2427   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2428   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2429   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2430   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2431   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2432   /* 78 */
2433   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2434   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2435   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2436   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2437   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2438   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2439   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2440   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2441   /* 80 */
2442   { REG_TABLE (REG_80) },
2443   { REG_TABLE (REG_81) },
2444   { X86_64_TABLE (X86_64_82) },
2445   { REG_TABLE (REG_83) },
2446   { "testB",            { Eb, Gb }, 0 },
2447   { "testS",            { Ev, Gv }, 0 },
2448   { "xchgB",            { Ebh2, Gb }, 0 },
2449   { "xchgS",            { Evh2, Gv }, 0 },
2450   /* 88 */
2451   { "movB",             { Ebh3, Gb }, 0 },
2452   { "movS",             { Evh3, Gv }, 0 },
2453   { "movB",             { Gb, EbS }, 0 },
2454   { "movS",             { Gv, EvS }, 0 },
2455   { "movD",             { Sv, Sw }, 0 },
2456   { MOD_TABLE (MOD_8D) },
2457   { "movD",             { Sw, Sv }, 0 },
2458   { REG_TABLE (REG_8F) },
2459   /* 90 */
2460   { PREFIX_TABLE (PREFIX_90) },
2461   { "xchgS",            { RMeCX, eAX }, 0 },
2462   { "xchgS",            { RMeDX, eAX }, 0 },
2463   { "xchgS",            { RMeBX, eAX }, 0 },
2464   { "xchgS",            { RMeSP, eAX }, 0 },
2465   { "xchgS",            { RMeBP, eAX }, 0 },
2466   { "xchgS",            { RMeSI, eAX }, 0 },
2467   { "xchgS",            { RMeDI, eAX }, 0 },
2468   /* 98 */
2469   { "cW{t|}R",          { XX }, 0 },
2470   { "cR{t|}O",          { XX }, 0 },
2471   { X86_64_TABLE (X86_64_9A) },
2472   { Bad_Opcode },       /* fwait */
2473   { "pushfT",           { XX }, 0 },
2474   { "popfT",            { XX }, 0 },
2475   { "sahf",             { XX }, 0 },
2476   { "lahf",             { XX }, 0 },
2477   /* a0 */
2478   { "mov%LB",           { AL, Ob }, 0 },
2479   { "mov%LS",           { eAX, Ov }, 0 },
2480   { "mov%LB",           { Ob, AL }, 0 },
2481   { "mov%LS",           { Ov, eAX }, 0 },
2482   { "movs{b|}",         { Ybr, Xb }, 0 },
2483   { "movs{R|}",         { Yvr, Xv }, 0 },
2484   { "cmps{b|}",         { Xb, Yb }, 0 },
2485   { "cmps{R|}",         { Xv, Yv }, 0 },
2486   /* a8 */
2487   { "testB",            { AL, Ib }, 0 },
2488   { "testS",            { eAX, Iv }, 0 },
2489   { "stosB",            { Ybr, AL }, 0 },
2490   { "stosS",            { Yvr, eAX }, 0 },
2491   { "lodsB",            { ALr, Xb }, 0 },
2492   { "lodsS",            { eAXr, Xv }, 0 },
2493   { "scasB",            { AL, Yb }, 0 },
2494   { "scasS",            { eAX, Yv }, 0 },
2495   /* b0 */
2496   { "movB",             { RMAL, Ib }, 0 },
2497   { "movB",             { RMCL, Ib }, 0 },
2498   { "movB",             { RMDL, Ib }, 0 },
2499   { "movB",             { RMBL, Ib }, 0 },
2500   { "movB",             { RMAH, Ib }, 0 },
2501   { "movB",             { RMCH, Ib }, 0 },
2502   { "movB",             { RMDH, Ib }, 0 },
2503   { "movB",             { RMBH, Ib }, 0 },
2504   /* b8 */
2505   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2506   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2507   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2508   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2509   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2510   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2511   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2512   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2513   /* c0 */
2514   { REG_TABLE (REG_C0) },
2515   { REG_TABLE (REG_C1) },
2516   { X86_64_TABLE (X86_64_C2) },
2517   { X86_64_TABLE (X86_64_C3) },
2518   { X86_64_TABLE (X86_64_C4) },
2519   { X86_64_TABLE (X86_64_C5) },
2520   { REG_TABLE (REG_C6) },
2521   { REG_TABLE (REG_C7) },
2522   /* c8 */
2523   { "enterT",           { Iw, Ib }, 0 },
2524   { "leaveT",           { XX }, 0 },
2525   { "{l|}ret{|f}P",     { Iw }, 0 },
2526   { "{l|}ret{|f}P",     { XX }, 0 },
2527   { "int3",             { XX }, 0 },
2528   { "int",              { Ib }, 0 },
2529   { X86_64_TABLE (X86_64_CE) },
2530   { "iret%LP",          { XX }, 0 },
2531   /* d0 */
2532   { REG_TABLE (REG_D0) },
2533   { REG_TABLE (REG_D1) },
2534   { REG_TABLE (REG_D2) },
2535   { REG_TABLE (REG_D3) },
2536   { X86_64_TABLE (X86_64_D4) },
2537   { X86_64_TABLE (X86_64_D5) },
2538   { Bad_Opcode },
2539   { "xlat",             { DSBX }, 0 },
2540   /* d8 */
2541   { FLOAT },
2542   { FLOAT },
2543   { FLOAT },
2544   { FLOAT },
2545   { FLOAT },
2546   { FLOAT },
2547   { FLOAT },
2548   { FLOAT },
2549   /* e0 */
2550   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2551   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2552   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2553   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2554   { "inB",              { AL, Ib }, 0 },
2555   { "inG",              { zAX, Ib }, 0 },
2556   { "outB",             { Ib, AL }, 0 },
2557   { "outG",             { Ib, zAX }, 0 },
2558   /* e8 */
2559   { X86_64_TABLE (X86_64_E8) },
2560   { X86_64_TABLE (X86_64_E9) },
2561   { X86_64_TABLE (X86_64_EA) },
2562   { "jmp",              { Jb, BND }, 0 },
2563   { "inB",              { AL, indirDX }, 0 },
2564   { "inG",              { zAX, indirDX }, 0 },
2565   { "outB",             { indirDX, AL }, 0 },
2566   { "outG",             { indirDX, zAX }, 0 },
2567   /* f0 */
2568   { Bad_Opcode },       /* lock prefix */
2569   { "icebp",            { XX }, 0 },
2570   { Bad_Opcode },       /* repne */
2571   { Bad_Opcode },       /* repz */
2572   { "hlt",              { XX }, 0 },
2573   { "cmc",              { XX }, 0 },
2574   { REG_TABLE (REG_F6) },
2575   { REG_TABLE (REG_F7) },
2576   /* f8 */
2577   { "clc",              { XX }, 0 },
2578   { "stc",              { XX }, 0 },
2579   { "cli",              { XX }, 0 },
2580   { "sti",              { XX }, 0 },
2581   { "cld",              { XX }, 0 },
2582   { "std",              { XX }, 0 },
2583   { REG_TABLE (REG_FE) },
2584   { REG_TABLE (REG_FF) },
2585 };
2586
2587 static const struct dis386 dis386_twobyte[] = {
2588   /* 00 */
2589   { REG_TABLE (REG_0F00 ) },
2590   { REG_TABLE (REG_0F01 ) },
2591   { "larS",             { Gv, Ew }, 0 },
2592   { "lslS",             { Gv, Ew }, 0 },
2593   { Bad_Opcode },
2594   { "syscall",          { XX }, 0 },
2595   { "clts",             { XX }, 0 },
2596   { "sysret%LQ",                { XX }, 0 },
2597   /* 08 */
2598   { "invd",             { XX }, 0 },
2599   { PREFIX_TABLE (PREFIX_0F09) },
2600   { Bad_Opcode },
2601   { "ud2",              { XX }, 0 },
2602   { Bad_Opcode },
2603   { REG_TABLE (REG_0F0D) },
2604   { "femms",            { XX }, 0 },
2605   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2606   /* 10 */
2607   { PREFIX_TABLE (PREFIX_0F10) },
2608   { PREFIX_TABLE (PREFIX_0F11) },
2609   { PREFIX_TABLE (PREFIX_0F12) },
2610   { MOD_TABLE (MOD_0F13) },
2611   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2612   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2613   { PREFIX_TABLE (PREFIX_0F16) },
2614   { MOD_TABLE (MOD_0F17) },
2615   /* 18 */
2616   { REG_TABLE (REG_0F18) },
2617   { "nopQ",             { Ev }, 0 },
2618   { PREFIX_TABLE (PREFIX_0F1A) },
2619   { PREFIX_TABLE (PREFIX_0F1B) },
2620   { PREFIX_TABLE (PREFIX_0F1C) },
2621   { "nopQ",             { Ev }, 0 },
2622   { PREFIX_TABLE (PREFIX_0F1E) },
2623   { "nopQ",             { Ev }, 0 },
2624   /* 20 */
2625   { "movZ",             { Rm, Cm }, 0 },
2626   { "movZ",             { Rm, Dm }, 0 },
2627   { "movZ",             { Cm, Rm }, 0 },
2628   { "movZ",             { Dm, Rm }, 0 },
2629   { MOD_TABLE (MOD_0F24) },
2630   { Bad_Opcode },
2631   { MOD_TABLE (MOD_0F26) },
2632   { Bad_Opcode },
2633   /* 28 */
2634   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2635   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2636   { PREFIX_TABLE (PREFIX_0F2A) },
2637   { PREFIX_TABLE (PREFIX_0F2B) },
2638   { PREFIX_TABLE (PREFIX_0F2C) },
2639   { PREFIX_TABLE (PREFIX_0F2D) },
2640   { PREFIX_TABLE (PREFIX_0F2E) },
2641   { PREFIX_TABLE (PREFIX_0F2F) },
2642   /* 30 */
2643   { "wrmsr",            { XX }, 0 },
2644   { "rdtsc",            { XX }, 0 },
2645   { "rdmsr",            { XX }, 0 },
2646   { "rdpmc",            { XX }, 0 },
2647   { "sysenter",         { SEP }, 0 },
2648   { "sysexit",          { SEP }, 0 },
2649   { Bad_Opcode },
2650   { "getsec",           { XX }, 0 },
2651   /* 38 */
2652   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2653   { Bad_Opcode },
2654   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2655   { Bad_Opcode },
2656   { Bad_Opcode },
2657   { Bad_Opcode },
2658   { Bad_Opcode },
2659   { Bad_Opcode },
2660   /* 40 */
2661   { "cmovoS",           { Gv, Ev }, 0 },
2662   { "cmovnoS",          { Gv, Ev }, 0 },
2663   { "cmovbS",           { Gv, Ev }, 0 },
2664   { "cmovaeS",          { Gv, Ev }, 0 },
2665   { "cmoveS",           { Gv, Ev }, 0 },
2666   { "cmovneS",          { Gv, Ev }, 0 },
2667   { "cmovbeS",          { Gv, Ev }, 0 },
2668   { "cmovaS",           { Gv, Ev }, 0 },
2669   /* 48 */
2670   { "cmovsS",           { Gv, Ev }, 0 },
2671   { "cmovnsS",          { Gv, Ev }, 0 },
2672   { "cmovpS",           { Gv, Ev }, 0 },
2673   { "cmovnpS",          { Gv, Ev }, 0 },
2674   { "cmovlS",           { Gv, Ev }, 0 },
2675   { "cmovgeS",          { Gv, Ev }, 0 },
2676   { "cmovleS",          { Gv, Ev }, 0 },
2677   { "cmovgS",           { Gv, Ev }, 0 },
2678   /* 50 */
2679   { MOD_TABLE (MOD_0F50) },
2680   { PREFIX_TABLE (PREFIX_0F51) },
2681   { PREFIX_TABLE (PREFIX_0F52) },
2682   { PREFIX_TABLE (PREFIX_0F53) },
2683   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2684   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2685   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2686   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2687   /* 58 */
2688   { PREFIX_TABLE (PREFIX_0F58) },
2689   { PREFIX_TABLE (PREFIX_0F59) },
2690   { PREFIX_TABLE (PREFIX_0F5A) },
2691   { PREFIX_TABLE (PREFIX_0F5B) },
2692   { PREFIX_TABLE (PREFIX_0F5C) },
2693   { PREFIX_TABLE (PREFIX_0F5D) },
2694   { PREFIX_TABLE (PREFIX_0F5E) },
2695   { PREFIX_TABLE (PREFIX_0F5F) },
2696   /* 60 */
2697   { PREFIX_TABLE (PREFIX_0F60) },
2698   { PREFIX_TABLE (PREFIX_0F61) },
2699   { PREFIX_TABLE (PREFIX_0F62) },
2700   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2701   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2702   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2703   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2704   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2705   /* 68 */
2706   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2707   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2708   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2709   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2710   { PREFIX_TABLE (PREFIX_0F6C) },
2711   { PREFIX_TABLE (PREFIX_0F6D) },
2712   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2713   { PREFIX_TABLE (PREFIX_0F6F) },
2714   /* 70 */
2715   { PREFIX_TABLE (PREFIX_0F70) },
2716   { REG_TABLE (REG_0F71) },
2717   { REG_TABLE (REG_0F72) },
2718   { REG_TABLE (REG_0F73) },
2719   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2720   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2721   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2722   { "emms",             { XX }, PREFIX_OPCODE },
2723   /* 78 */
2724   { PREFIX_TABLE (PREFIX_0F78) },
2725   { PREFIX_TABLE (PREFIX_0F79) },
2726   { Bad_Opcode },
2727   { Bad_Opcode },
2728   { PREFIX_TABLE (PREFIX_0F7C) },
2729   { PREFIX_TABLE (PREFIX_0F7D) },
2730   { PREFIX_TABLE (PREFIX_0F7E) },
2731   { PREFIX_TABLE (PREFIX_0F7F) },
2732   /* 80 */
2733   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2734   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2735   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2736   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2737   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2738   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2739   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2740   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2741   /* 88 */
2742   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2743   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2744   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2745   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2746   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2747   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2748   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2749   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2750   /* 90 */
2751   { "seto",             { Eb }, 0 },
2752   { "setno",            { Eb }, 0 },
2753   { "setb",             { Eb }, 0 },
2754   { "setae",            { Eb }, 0 },
2755   { "sete",             { Eb }, 0 },
2756   { "setne",            { Eb }, 0 },
2757   { "setbe",            { Eb }, 0 },
2758   { "seta",             { Eb }, 0 },
2759   /* 98 */
2760   { "sets",             { Eb }, 0 },
2761   { "setns",            { Eb }, 0 },
2762   { "setp",             { Eb }, 0 },
2763   { "setnp",            { Eb }, 0 },
2764   { "setl",             { Eb }, 0 },
2765   { "setge",            { Eb }, 0 },
2766   { "setle",            { Eb }, 0 },
2767   { "setg",             { Eb }, 0 },
2768   /* a0 */
2769   { "pushT",            { fs }, 0 },
2770   { "popT",             { fs }, 0 },
2771   { "cpuid",            { XX }, 0 },
2772   { "btS",              { Ev, Gv }, 0 },
2773   { "shldS",            { Ev, Gv, Ib }, 0 },
2774   { "shldS",            { Ev, Gv, CL }, 0 },
2775   { REG_TABLE (REG_0FA6) },
2776   { REG_TABLE (REG_0FA7) },
2777   /* a8 */
2778   { "pushT",            { gs }, 0 },
2779   { "popT",             { gs }, 0 },
2780   { "rsm",              { XX }, 0 },
2781   { "btsS",             { Evh1, Gv }, 0 },
2782   { "shrdS",            { Ev, Gv, Ib }, 0 },
2783   { "shrdS",            { Ev, Gv, CL }, 0 },
2784   { REG_TABLE (REG_0FAE) },
2785   { "imulS",            { Gv, Ev }, 0 },
2786   /* b0 */
2787   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2788   { "cmpxchgS",         { Evh1, Gv }, 0 },
2789   { MOD_TABLE (MOD_0FB2) },
2790   { "btrS",             { Evh1, Gv }, 0 },
2791   { MOD_TABLE (MOD_0FB4) },
2792   { MOD_TABLE (MOD_0FB5) },
2793   { "movz{bR|x}",       { Gv, Eb }, 0 },
2794   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2795   /* b8 */
2796   { PREFIX_TABLE (PREFIX_0FB8) },
2797   { "ud1S",             { Gv, Ev }, 0 },
2798   { REG_TABLE (REG_0FBA) },
2799   { "btcS",             { Evh1, Gv }, 0 },
2800   { PREFIX_TABLE (PREFIX_0FBC) },
2801   { PREFIX_TABLE (PREFIX_0FBD) },
2802   { "movs{bR|x}",       { Gv, Eb }, 0 },
2803   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2804   /* c0 */
2805   { "xaddB",            { Ebh1, Gb }, 0 },
2806   { "xaddS",            { Evh1, Gv }, 0 },
2807   { PREFIX_TABLE (PREFIX_0FC2) },
2808   { MOD_TABLE (MOD_0FC3) },
2809   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2810   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2811   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2812   { REG_TABLE (REG_0FC7) },
2813   /* c8 */
2814   { "bswap",            { RMeAX }, 0 },
2815   { "bswap",            { RMeCX }, 0 },
2816   { "bswap",            { RMeDX }, 0 },
2817   { "bswap",            { RMeBX }, 0 },
2818   { "bswap",            { RMeSP }, 0 },
2819   { "bswap",            { RMeBP }, 0 },
2820   { "bswap",            { RMeSI }, 0 },
2821   { "bswap",            { RMeDI }, 0 },
2822   /* d0 */
2823   { PREFIX_TABLE (PREFIX_0FD0) },
2824   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2825   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2826   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2827   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2828   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2829   { PREFIX_TABLE (PREFIX_0FD6) },
2830   { MOD_TABLE (MOD_0FD7) },
2831   /* d8 */
2832   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2833   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2834   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2835   { "pand",             { MX, EM }, PREFIX_OPCODE },
2836   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2837   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2838   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2839   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2840   /* e0 */
2841   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2842   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2843   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2844   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2845   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2846   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2847   { PREFIX_TABLE (PREFIX_0FE6) },
2848   { PREFIX_TABLE (PREFIX_0FE7) },
2849   /* e8 */
2850   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2851   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2852   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2853   { "por",              { MX, EM }, PREFIX_OPCODE },
2854   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2855   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2856   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2857   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2858   /* f0 */
2859   { PREFIX_TABLE (PREFIX_0FF0) },
2860   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2861   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2862   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2863   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2864   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2865   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2866   { PREFIX_TABLE (PREFIX_0FF7) },
2867   /* f8 */
2868   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2869   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2870   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2871   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2872   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2873   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2874   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2875   { "ud0S",             { Gv, Ev }, 0 },
2876 };
2877
2878 static const unsigned char onebyte_has_modrm[256] = {
2879   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2880   /*       -------------------------------        */
2881   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2882   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2883   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2884   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2885   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2886   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2887   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2888   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2889   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2890   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2891   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2892   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2893   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2894   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2895   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2896   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2897   /*       -------------------------------        */
2898   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2899 };
2900
2901 static const unsigned char twobyte_has_modrm[256] = {
2902   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2903   /*       -------------------------------        */
2904   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2905   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2906   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2907   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2908   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2909   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2910   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2911   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2912   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2913   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2914   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2915   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2916   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2917   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2918   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2919   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2920   /*       -------------------------------        */
2921   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2922 };
2923
2924 static char obuf[100];
2925 static char *obufp;
2926 static char *mnemonicendp;
2927 static char scratchbuf[100];
2928 static unsigned char *start_codep;
2929 static unsigned char *insn_codep;
2930 static unsigned char *codep;
2931 static unsigned char *end_codep;
2932 static int last_lock_prefix;
2933 static int last_repz_prefix;
2934 static int last_repnz_prefix;
2935 static int last_data_prefix;
2936 static int last_addr_prefix;
2937 static int last_rex_prefix;
2938 static int last_seg_prefix;
2939 static int fwait_prefix;
2940 /* The active segment register prefix.  */
2941 static int active_seg_prefix;
2942 #define MAX_CODE_LENGTH 15
2943 /* We can up to 14 prefixes since the maximum instruction length is
2944    15bytes.  */
2945 static int all_prefixes[MAX_CODE_LENGTH - 1];
2946 static disassemble_info *the_info;
2947 static struct
2948   {
2949     int mod;
2950     int reg;
2951     int rm;
2952   }
2953 modrm;
2954 static unsigned char need_modrm;
2955 static struct
2956   {
2957     int scale;
2958     int index;
2959     int base;
2960   }
2961 sib;
2962 static struct
2963   {
2964     int register_specifier;
2965     int length;
2966     int prefix;
2967     int w;
2968     int evex;
2969     int r;
2970     int v;
2971     int mask_register_specifier;
2972     int zeroing;
2973     int ll;
2974     int b;
2975   }
2976 vex;
2977 static unsigned char need_vex;
2978 static unsigned char need_vex_reg;
2979
2980 struct op
2981   {
2982     const char *name;
2983     unsigned int len;
2984   };
2985
2986 /* If we are accessing mod/rm/reg without need_modrm set, then the
2987    values are stale.  Hitting this abort likely indicates that you
2988    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2989 #define MODRM_CHECK  if (!need_modrm) abort ()
2990
2991 static const char **names64;
2992 static const char **names32;
2993 static const char **names16;
2994 static const char **names8;
2995 static const char **names8rex;
2996 static const char **names_seg;
2997 static const char *index64;
2998 static const char *index32;
2999 static const char **index16;
3000 static const char **names_bnd;
3001
3002 static const char *intel_names64[] = {
3003   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3004   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3005 };
3006 static const char *intel_names32[] = {
3007   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3008   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3009 };
3010 static const char *intel_names16[] = {
3011   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3012   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3013 };
3014 static const char *intel_names8[] = {
3015   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3016 };
3017 static const char *intel_names8rex[] = {
3018   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3019   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3020 };
3021 static const char *intel_names_seg[] = {
3022   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3023 };
3024 static const char *intel_index64 = "riz";
3025 static const char *intel_index32 = "eiz";
3026 static const char *intel_index16[] = {
3027   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3028 };
3029
3030 static const char *att_names64[] = {
3031   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3032   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3033 };
3034 static const char *att_names32[] = {
3035   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3036   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3037 };
3038 static const char *att_names16[] = {
3039   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3040   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3041 };
3042 static const char *att_names8[] = {
3043   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3044 };
3045 static const char *att_names8rex[] = {
3046   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3047   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3048 };
3049 static const char *att_names_seg[] = {
3050   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3051 };
3052 static const char *att_index64 = "%riz";
3053 static const char *att_index32 = "%eiz";
3054 static const char *att_index16[] = {
3055   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3056 };
3057
3058 static const char **names_mm;
3059 static const char *intel_names_mm[] = {
3060   "mm0", "mm1", "mm2", "mm3",
3061   "mm4", "mm5", "mm6", "mm7"
3062 };
3063 static const char *att_names_mm[] = {
3064   "%mm0", "%mm1", "%mm2", "%mm3",
3065   "%mm4", "%mm5", "%mm6", "%mm7"
3066 };
3067
3068 static const char *intel_names_bnd[] = {
3069   "bnd0", "bnd1", "bnd2", "bnd3"
3070 };
3071
3072 static const char *att_names_bnd[] = {
3073   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3074 };
3075
3076 static const char **names_xmm;
3077 static const char *intel_names_xmm[] = {
3078   "xmm0", "xmm1", "xmm2", "xmm3",
3079   "xmm4", "xmm5", "xmm6", "xmm7",
3080   "xmm8", "xmm9", "xmm10", "xmm11",
3081   "xmm12", "xmm13", "xmm14", "xmm15",
3082   "xmm16", "xmm17", "xmm18", "xmm19",
3083   "xmm20", "xmm21", "xmm22", "xmm23",
3084   "xmm24", "xmm25", "xmm26", "xmm27",
3085   "xmm28", "xmm29", "xmm30", "xmm31"
3086 };
3087 static const char *att_names_xmm[] = {
3088   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3089   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3090   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3091   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3092   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3093   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3094   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3095   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3096 };
3097
3098 static const char **names_ymm;
3099 static const char *intel_names_ymm[] = {
3100   "ymm0", "ymm1", "ymm2", "ymm3",
3101   "ymm4", "ymm5", "ymm6", "ymm7",
3102   "ymm8", "ymm9", "ymm10", "ymm11",
3103   "ymm12", "ymm13", "ymm14", "ymm15",
3104   "ymm16", "ymm17", "ymm18", "ymm19",
3105   "ymm20", "ymm21", "ymm22", "ymm23",
3106   "ymm24", "ymm25", "ymm26", "ymm27",
3107   "ymm28", "ymm29", "ymm30", "ymm31"
3108 };
3109 static const char *att_names_ymm[] = {
3110   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3111   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3112   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3113   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3114   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3115   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3116   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3117   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3118 };
3119
3120 static const char **names_zmm;
3121 static const char *intel_names_zmm[] = {
3122   "zmm0", "zmm1", "zmm2", "zmm3",
3123   "zmm4", "zmm5", "zmm6", "zmm7",
3124   "zmm8", "zmm9", "zmm10", "zmm11",
3125   "zmm12", "zmm13", "zmm14", "zmm15",
3126   "zmm16", "zmm17", "zmm18", "zmm19",
3127   "zmm20", "zmm21", "zmm22", "zmm23",
3128   "zmm24", "zmm25", "zmm26", "zmm27",
3129   "zmm28", "zmm29", "zmm30", "zmm31"
3130 };
3131 static const char *att_names_zmm[] = {
3132   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3133   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3134   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3135   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3136   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3137   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3138   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3139   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3140 };
3141
3142 static const char **names_tmm;
3143 static const char *intel_names_tmm[] = {
3144   "tmm0", "tmm1", "tmm2", "tmm3",
3145   "tmm4", "tmm5", "tmm6", "tmm7"
3146 };
3147 static const char *att_names_tmm[] = {
3148   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
3149   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
3150 };
3151
3152 static const char **names_mask;
3153 static const char *intel_names_mask[] = {
3154   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3155 };
3156 static const char *att_names_mask[] = {
3157   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3158 };
3159
3160 static const char *names_rounding[] =
3161 {
3162   "{rn-sae}",
3163   "{rd-sae}",
3164   "{ru-sae}",
3165   "{rz-sae}"
3166 };
3167
3168 static const struct dis386 reg_table[][8] = {
3169   /* REG_80 */
3170   {
3171     { "addA",   { Ebh1, Ib }, 0 },
3172     { "orA",    { Ebh1, Ib }, 0 },
3173     { "adcA",   { Ebh1, Ib }, 0 },
3174     { "sbbA",   { Ebh1, Ib }, 0 },
3175     { "andA",   { Ebh1, Ib }, 0 },
3176     { "subA",   { Ebh1, Ib }, 0 },
3177     { "xorA",   { Ebh1, Ib }, 0 },
3178     { "cmpA",   { Eb, Ib }, 0 },
3179   },
3180   /* REG_81 */
3181   {
3182     { "addQ",   { Evh1, Iv }, 0 },
3183     { "orQ",    { Evh1, Iv }, 0 },
3184     { "adcQ",   { Evh1, Iv }, 0 },
3185     { "sbbQ",   { Evh1, Iv }, 0 },
3186     { "andQ",   { Evh1, Iv }, 0 },
3187     { "subQ",   { Evh1, Iv }, 0 },
3188     { "xorQ",   { Evh1, Iv }, 0 },
3189     { "cmpQ",   { Ev, Iv }, 0 },
3190   },
3191   /* REG_83 */
3192   {
3193     { "addQ",   { Evh1, sIb }, 0 },
3194     { "orQ",    { Evh1, sIb }, 0 },
3195     { "adcQ",   { Evh1, sIb }, 0 },
3196     { "sbbQ",   { Evh1, sIb }, 0 },
3197     { "andQ",   { Evh1, sIb }, 0 },
3198     { "subQ",   { Evh1, sIb }, 0 },
3199     { "xorQ",   { Evh1, sIb }, 0 },
3200     { "cmpQ",   { Ev, sIb }, 0 },
3201   },
3202   /* REG_8F */
3203   {
3204     { "popU",   { stackEv }, 0 },
3205     { XOP_8F_TABLE (XOP_09) },
3206     { Bad_Opcode },
3207     { Bad_Opcode },
3208     { Bad_Opcode },
3209     { XOP_8F_TABLE (XOP_09) },
3210   },
3211   /* REG_C0 */
3212   {
3213     { "rolA",   { Eb, Ib }, 0 },
3214     { "rorA",   { Eb, Ib }, 0 },
3215     { "rclA",   { Eb, Ib }, 0 },
3216     { "rcrA",   { Eb, Ib }, 0 },
3217     { "shlA",   { Eb, Ib }, 0 },
3218     { "shrA",   { Eb, Ib }, 0 },
3219     { "shlA",   { Eb, Ib }, 0 },
3220     { "sarA",   { Eb, Ib }, 0 },
3221   },
3222   /* REG_C1 */
3223   {
3224     { "rolQ",   { Ev, Ib }, 0 },
3225     { "rorQ",   { Ev, Ib }, 0 },
3226     { "rclQ",   { Ev, Ib }, 0 },
3227     { "rcrQ",   { Ev, Ib }, 0 },
3228     { "shlQ",   { Ev, Ib }, 0 },
3229     { "shrQ",   { Ev, Ib }, 0 },
3230     { "shlQ",   { Ev, Ib }, 0 },
3231     { "sarQ",   { Ev, Ib }, 0 },
3232   },
3233   /* REG_C6 */
3234   {
3235     { "movA",   { Ebh3, Ib }, 0 },
3236     { Bad_Opcode },
3237     { Bad_Opcode },
3238     { Bad_Opcode },
3239     { Bad_Opcode },
3240     { Bad_Opcode },
3241     { Bad_Opcode },
3242     { MOD_TABLE (MOD_C6_REG_7) },
3243   },
3244   /* REG_C7 */
3245   {
3246     { "movQ",   { Evh3, Iv }, 0 },
3247     { Bad_Opcode },
3248     { Bad_Opcode },
3249     { Bad_Opcode },
3250     { Bad_Opcode },
3251     { Bad_Opcode },
3252     { Bad_Opcode },
3253     { MOD_TABLE (MOD_C7_REG_7) },
3254   },
3255   /* REG_D0 */
3256   {
3257     { "rolA",   { Eb, I1 }, 0 },
3258     { "rorA",   { Eb, I1 }, 0 },
3259     { "rclA",   { Eb, I1 }, 0 },
3260     { "rcrA",   { Eb, I1 }, 0 },
3261     { "shlA",   { Eb, I1 }, 0 },
3262     { "shrA",   { Eb, I1 }, 0 },
3263     { "shlA",   { Eb, I1 }, 0 },
3264     { "sarA",   { Eb, I1 }, 0 },
3265   },
3266   /* REG_D1 */
3267   {
3268     { "rolQ",   { Ev, I1 }, 0 },
3269     { "rorQ",   { Ev, I1 }, 0 },
3270     { "rclQ",   { Ev, I1 }, 0 },
3271     { "rcrQ",   { Ev, I1 }, 0 },
3272     { "shlQ",   { Ev, I1 }, 0 },
3273     { "shrQ",   { Ev, I1 }, 0 },
3274     { "shlQ",   { Ev, I1 }, 0 },
3275     { "sarQ",   { Ev, I1 }, 0 },
3276   },
3277   /* REG_D2 */
3278   {
3279     { "rolA",   { Eb, CL }, 0 },
3280     { "rorA",   { Eb, CL }, 0 },
3281     { "rclA",   { Eb, CL }, 0 },
3282     { "rcrA",   { Eb, CL }, 0 },
3283     { "shlA",   { Eb, CL }, 0 },
3284     { "shrA",   { Eb, CL }, 0 },
3285     { "shlA",   { Eb, CL }, 0 },
3286     { "sarA",   { Eb, CL }, 0 },
3287   },
3288   /* REG_D3 */
3289   {
3290     { "rolQ",   { Ev, CL }, 0 },
3291     { "rorQ",   { Ev, CL }, 0 },
3292     { "rclQ",   { Ev, CL }, 0 },
3293     { "rcrQ",   { Ev, CL }, 0 },
3294     { "shlQ",   { Ev, CL }, 0 },
3295     { "shrQ",   { Ev, CL }, 0 },
3296     { "shlQ",   { Ev, CL }, 0 },
3297     { "sarQ",   { Ev, CL }, 0 },
3298   },
3299   /* REG_F6 */
3300   {
3301     { "testA",  { Eb, Ib }, 0 },
3302     { "testA",  { Eb, Ib }, 0 },
3303     { "notA",   { Ebh1 }, 0 },
3304     { "negA",   { Ebh1 }, 0 },
3305     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3306     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3307     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3308     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3309   },
3310   /* REG_F7 */
3311   {
3312     { "testQ",  { Ev, Iv }, 0 },
3313     { "testQ",  { Ev, Iv }, 0 },
3314     { "notQ",   { Evh1 }, 0 },
3315     { "negQ",   { Evh1 }, 0 },
3316     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3317     { "imulQ",  { Ev }, 0 },
3318     { "divQ",   { Ev }, 0 },
3319     { "idivQ",  { Ev }, 0 },
3320   },
3321   /* REG_FE */
3322   {
3323     { "incA",   { Ebh1 }, 0 },
3324     { "decA",   { Ebh1 }, 0 },
3325   },
3326   /* REG_FF */
3327   {
3328     { "incQ",   { Evh1 }, 0 },
3329     { "decQ",   { Evh1 }, 0 },
3330     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3331     { MOD_TABLE (MOD_FF_REG_3) },
3332     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3333     { MOD_TABLE (MOD_FF_REG_5) },
3334     { "pushU",  { stackEv }, 0 },
3335     { Bad_Opcode },
3336   },
3337   /* REG_0F00 */
3338   {
3339     { "sldtD",  { Sv }, 0 },
3340     { "strD",   { Sv }, 0 },
3341     { "lldt",   { Ew }, 0 },
3342     { "ltr",    { Ew }, 0 },
3343     { "verr",   { Ew }, 0 },
3344     { "verw",   { Ew }, 0 },
3345     { Bad_Opcode },
3346     { Bad_Opcode },
3347   },
3348   /* REG_0F01 */
3349   {
3350     { MOD_TABLE (MOD_0F01_REG_0) },
3351     { MOD_TABLE (MOD_0F01_REG_1) },
3352     { MOD_TABLE (MOD_0F01_REG_2) },
3353     { MOD_TABLE (MOD_0F01_REG_3) },
3354     { "smswD",  { Sv }, 0 },
3355     { MOD_TABLE (MOD_0F01_REG_5) },
3356     { "lmsw",   { Ew }, 0 },
3357     { MOD_TABLE (MOD_0F01_REG_7) },
3358   },
3359   /* REG_0F0D */
3360   {
3361     { "prefetch",       { Mb }, 0 },
3362     { "prefetchw",      { Mb }, 0 },
3363     { "prefetchwt1",    { Mb }, 0 },
3364     { "prefetch",       { Mb }, 0 },
3365     { "prefetch",       { Mb }, 0 },
3366     { "prefetch",       { Mb }, 0 },
3367     { "prefetch",       { Mb }, 0 },
3368     { "prefetch",       { Mb }, 0 },
3369   },
3370   /* REG_0F18 */
3371   {
3372     { MOD_TABLE (MOD_0F18_REG_0) },
3373     { MOD_TABLE (MOD_0F18_REG_1) },
3374     { MOD_TABLE (MOD_0F18_REG_2) },
3375     { MOD_TABLE (MOD_0F18_REG_3) },
3376     { MOD_TABLE (MOD_0F18_REG_4) },
3377     { MOD_TABLE (MOD_0F18_REG_5) },
3378     { MOD_TABLE (MOD_0F18_REG_6) },
3379     { MOD_TABLE (MOD_0F18_REG_7) },
3380   },
3381   /* REG_0F1C_P_0_MOD_0 */
3382   {
3383     { "cldemote",       { Mb }, 0 },
3384     { "nopQ",           { Ev }, 0 },
3385     { "nopQ",           { Ev }, 0 },
3386     { "nopQ",           { Ev }, 0 },
3387     { "nopQ",           { Ev }, 0 },
3388     { "nopQ",           { Ev }, 0 },
3389     { "nopQ",           { Ev }, 0 },
3390     { "nopQ",           { Ev }, 0 },
3391   },
3392   /* REG_0F1E_P_1_MOD_3 */
3393   {
3394     { "nopQ",           { Ev }, 0 },
3395     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3396     { "nopQ",           { Ev }, 0 },
3397     { "nopQ",           { Ev }, 0 },
3398     { "nopQ",           { Ev }, 0 },
3399     { "nopQ",           { Ev }, 0 },
3400     { "nopQ",           { Ev }, 0 },
3401     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3402   },
3403   /* REG_0F71 */
3404   {
3405     { Bad_Opcode },
3406     { Bad_Opcode },
3407     { MOD_TABLE (MOD_0F71_REG_2) },
3408     { Bad_Opcode },
3409     { MOD_TABLE (MOD_0F71_REG_4) },
3410     { Bad_Opcode },
3411     { MOD_TABLE (MOD_0F71_REG_6) },
3412   },
3413   /* REG_0F72 */
3414   {
3415     { Bad_Opcode },
3416     { Bad_Opcode },
3417     { MOD_TABLE (MOD_0F72_REG_2) },
3418     { Bad_Opcode },
3419     { MOD_TABLE (MOD_0F72_REG_4) },
3420     { Bad_Opcode },
3421     { MOD_TABLE (MOD_0F72_REG_6) },
3422   },
3423   /* REG_0F73 */
3424   {
3425     { Bad_Opcode },
3426     { Bad_Opcode },
3427     { MOD_TABLE (MOD_0F73_REG_2) },
3428     { MOD_TABLE (MOD_0F73_REG_3) },
3429     { Bad_Opcode },
3430     { Bad_Opcode },
3431     { MOD_TABLE (MOD_0F73_REG_6) },
3432     { MOD_TABLE (MOD_0F73_REG_7) },
3433   },
3434   /* REG_0FA6 */
3435   {
3436     { "montmul",        { { OP_0f07, 0 } }, 0 },
3437     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3438     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3439   },
3440   /* REG_0FA7 */
3441   {
3442     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3443     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3444     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3445     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3446     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3447     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3448   },
3449   /* REG_0FAE */
3450   {
3451     { MOD_TABLE (MOD_0FAE_REG_0) },
3452     { MOD_TABLE (MOD_0FAE_REG_1) },
3453     { MOD_TABLE (MOD_0FAE_REG_2) },
3454     { MOD_TABLE (MOD_0FAE_REG_3) },
3455     { MOD_TABLE (MOD_0FAE_REG_4) },
3456     { MOD_TABLE (MOD_0FAE_REG_5) },
3457     { MOD_TABLE (MOD_0FAE_REG_6) },
3458     { MOD_TABLE (MOD_0FAE_REG_7) },
3459   },
3460   /* REG_0FBA */
3461   {
3462     { Bad_Opcode },
3463     { Bad_Opcode },
3464     { Bad_Opcode },
3465     { Bad_Opcode },
3466     { "btQ",    { Ev, Ib }, 0 },
3467     { "btsQ",   { Evh1, Ib }, 0 },
3468     { "btrQ",   { Evh1, Ib }, 0 },
3469     { "btcQ",   { Evh1, Ib }, 0 },
3470   },
3471   /* REG_0FC7 */
3472   {
3473     { Bad_Opcode },
3474     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3475     { Bad_Opcode },
3476     { MOD_TABLE (MOD_0FC7_REG_3) },
3477     { MOD_TABLE (MOD_0FC7_REG_4) },
3478     { MOD_TABLE (MOD_0FC7_REG_5) },
3479     { MOD_TABLE (MOD_0FC7_REG_6) },
3480     { MOD_TABLE (MOD_0FC7_REG_7) },
3481   },
3482   /* REG_VEX_0F71 */
3483   {
3484     { Bad_Opcode },
3485     { Bad_Opcode },
3486     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3487     { Bad_Opcode },
3488     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3489     { Bad_Opcode },
3490     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3491   },
3492   /* REG_VEX_0F72 */
3493   {
3494     { Bad_Opcode },
3495     { Bad_Opcode },
3496     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3497     { Bad_Opcode },
3498     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3499     { Bad_Opcode },
3500     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3501   },
3502   /* REG_VEX_0F73 */
3503   {
3504     { Bad_Opcode },
3505     { Bad_Opcode },
3506     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3507     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3508     { Bad_Opcode },
3509     { Bad_Opcode },
3510     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3511     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3512   },
3513   /* REG_VEX_0FAE */
3514   {
3515     { Bad_Opcode },
3516     { Bad_Opcode },
3517     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3518     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3519   },
3520   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3521   {
3522     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
3523   },
3524   /* REG_VEX_0F38F3 */
3525   {
3526     { Bad_Opcode },
3527     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3528     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3529     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3530   },
3531   /* REG_0FXOP_09_01_L_0 */
3532   {
3533     { Bad_Opcode },
3534     { "blcfill",        { VexGdq, Edq }, 0 },
3535     { "blsfill",        { VexGdq, Edq }, 0 },
3536     { "blcs",   { VexGdq, Edq }, 0 },
3537     { "tzmsk",  { VexGdq, Edq }, 0 },
3538     { "blcic",  { VexGdq, Edq }, 0 },
3539     { "blsic",  { VexGdq, Edq }, 0 },
3540     { "t1mskc", { VexGdq, Edq }, 0 },
3541   },
3542   /* REG_0FXOP_09_02_L_0 */
3543   {
3544     { Bad_Opcode },
3545     { "blcmsk", { VexGdq, Edq }, 0 },
3546     { Bad_Opcode },
3547     { Bad_Opcode },
3548     { Bad_Opcode },
3549     { Bad_Opcode },
3550     { "blci",   { VexGdq, Edq }, 0 },
3551   },
3552   /* REG_0FXOP_09_12_M_1_L_0 */
3553   {
3554     { "llwpcb", { Edq }, 0 },
3555     { "slwpcb", { Edq }, 0 },
3556   },
3557   /* REG_0FXOP_0A_12_L_0 */
3558   {
3559     { "lwpins", { VexGdq, Ed, Id }, 0 },
3560     { "lwpval", { VexGdq, Ed, Id }, 0 },
3561   },
3562
3563 #include "i386-dis-evex-reg.h"
3564 };
3565
3566 static const struct dis386 prefix_table[][4] = {
3567   /* PREFIX_90 */
3568   {
3569     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3570     { "pause", { XX }, 0 },
3571     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3572     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3573   },
3574
3575   /* PREFIX_0F01_REG_3_RM_1 */
3576   {
3577     { "vmmcall",        { Skip_MODRM }, 0 },
3578     { "vmgexit",        { Skip_MODRM }, 0 },
3579     { Bad_Opcode },
3580     { "vmgexit",        { Skip_MODRM }, 0 },
3581   },
3582
3583   /* PREFIX_0F01_REG_5_MOD_0 */
3584   {
3585     { Bad_Opcode },
3586     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3587   },
3588
3589   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3590   {
3591     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3592     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3593     { Bad_Opcode },
3594     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3595   },
3596
3597   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3598   {
3599     { Bad_Opcode },
3600     { Bad_Opcode },
3601     { Bad_Opcode },
3602     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3603   },
3604
3605   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3606   {
3607     { Bad_Opcode },
3608     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3609   },
3610
3611   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3612   {
3613     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3614     { "mcommit",        { Skip_MODRM }, 0 },
3615   },
3616
3617   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3618   {
3619     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3620   },
3621
3622   /* PREFIX_0F09 */
3623   {
3624     { "wbinvd",   { XX }, 0 },
3625     { "wbnoinvd", { XX }, 0 },
3626   },
3627
3628   /* PREFIX_0F10 */
3629   {
3630     { "movups", { XM, EXx }, PREFIX_OPCODE },
3631     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3632     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3633     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3634   },
3635
3636   /* PREFIX_0F11 */
3637   {
3638     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3639     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3640     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3641     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3642   },
3643
3644   /* PREFIX_0F12 */
3645   {
3646     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3647     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3648     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3649     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3650   },
3651
3652   /* PREFIX_0F16 */
3653   {
3654     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3655     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3656     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3657   },
3658
3659   /* PREFIX_0F1A */
3660   {
3661     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3662     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3663     { "bndmov", { Gbnd, Ebnd }, 0 },
3664     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3665   },
3666
3667   /* PREFIX_0F1B */
3668   {
3669     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3670     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3671     { "bndmov", { EbndS, Gbnd }, 0 },
3672     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3673   },
3674
3675   /* PREFIX_0F1C */
3676   {
3677     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3678     { "nopQ",   { Ev }, PREFIX_OPCODE },
3679     { "nopQ",   { Ev }, PREFIX_OPCODE },
3680     { "nopQ",   { Ev }, PREFIX_OPCODE },
3681   },
3682
3683   /* PREFIX_0F1E */
3684   {
3685     { "nopQ",   { Ev }, PREFIX_OPCODE },
3686     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3687     { "nopQ",   { Ev }, PREFIX_OPCODE },
3688     { "nopQ",   { Ev }, PREFIX_OPCODE },
3689   },
3690
3691   /* PREFIX_0F2A */
3692   {
3693     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3694     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3695     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3696     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3697   },
3698
3699   /* PREFIX_0F2B */
3700   {
3701     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3702     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3703     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3704     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3705   },
3706
3707   /* PREFIX_0F2C */
3708   {
3709     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3710     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3711     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3712     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3713   },
3714
3715   /* PREFIX_0F2D */
3716   {
3717     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3718     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3719     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3720     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3721   },
3722
3723   /* PREFIX_0F2E */
3724   {
3725     { "ucomiss",{ XM, EXd }, 0 },
3726     { Bad_Opcode },
3727     { "ucomisd",{ XM, EXq }, 0 },
3728   },
3729
3730   /* PREFIX_0F2F */
3731   {
3732     { "comiss", { XM, EXd }, 0 },
3733     { Bad_Opcode },
3734     { "comisd", { XM, EXq }, 0 },
3735   },
3736
3737   /* PREFIX_0F51 */
3738   {
3739     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3740     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3741     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3742     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3743   },
3744
3745   /* PREFIX_0F52 */
3746   {
3747     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3748     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3749   },
3750
3751   /* PREFIX_0F53 */
3752   {
3753     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3754     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3755   },
3756
3757   /* PREFIX_0F58 */
3758   {
3759     { "addps", { XM, EXx }, PREFIX_OPCODE },
3760     { "addss", { XM, EXd }, PREFIX_OPCODE },
3761     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3762     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3763   },
3764
3765   /* PREFIX_0F59 */
3766   {
3767     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3768     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3769     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3770     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3771   },
3772
3773   /* PREFIX_0F5A */
3774   {
3775     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3776     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3777     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3778     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3779   },
3780
3781   /* PREFIX_0F5B */
3782   {
3783     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3784     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3785     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3786   },
3787
3788   /* PREFIX_0F5C */
3789   {
3790     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3791     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3792     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3793     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3794   },
3795
3796   /* PREFIX_0F5D */
3797   {
3798     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3799     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3800     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3801     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3802   },
3803
3804   /* PREFIX_0F5E */
3805   {
3806     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3807     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3808     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3809     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3810   },
3811
3812   /* PREFIX_0F5F */
3813   {
3814     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3815     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3816     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3817     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3818   },
3819
3820   /* PREFIX_0F60 */
3821   {
3822     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3823     { Bad_Opcode },
3824     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3825   },
3826
3827   /* PREFIX_0F61 */
3828   {
3829     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3830     { Bad_Opcode },
3831     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3832   },
3833
3834   /* PREFIX_0F62 */
3835   {
3836     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3837     { Bad_Opcode },
3838     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3839   },
3840
3841   /* PREFIX_0F6C */
3842   {
3843     { Bad_Opcode },
3844     { Bad_Opcode },
3845     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3846   },
3847
3848   /* PREFIX_0F6D */
3849   {
3850     { Bad_Opcode },
3851     { Bad_Opcode },
3852     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3853   },
3854
3855   /* PREFIX_0F6F */
3856   {
3857     { "movq",   { MX, EM }, PREFIX_OPCODE },
3858     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3859     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3860   },
3861
3862   /* PREFIX_0F70 */
3863   {
3864     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3865     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3866     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3867     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3868   },
3869
3870   /* PREFIX_0F73_REG_3 */
3871   {
3872     { Bad_Opcode },
3873     { Bad_Opcode },
3874     { "psrldq", { XS, Ib }, 0 },
3875   },
3876
3877   /* PREFIX_0F73_REG_7 */
3878   {
3879     { Bad_Opcode },
3880     { Bad_Opcode },
3881     { "pslldq", { XS, Ib }, 0 },
3882   },
3883
3884   /* PREFIX_0F78 */
3885   {
3886     {"vmread",  { Em, Gm }, 0 },
3887     { Bad_Opcode },
3888     {"extrq",   { XS, Ib, Ib }, 0 },
3889     {"insertq", { XM, XS, Ib, Ib }, 0 },
3890   },
3891
3892   /* PREFIX_0F79 */
3893   {
3894     {"vmwrite", { Gm, Em }, 0 },
3895     { Bad_Opcode },
3896     {"extrq",   { XM, XS }, 0 },
3897     {"insertq", { XM, XS }, 0 },
3898   },
3899
3900   /* PREFIX_0F7C */
3901   {
3902     { Bad_Opcode },
3903     { Bad_Opcode },
3904     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3905     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3906   },
3907
3908   /* PREFIX_0F7D */
3909   {
3910     { Bad_Opcode },
3911     { Bad_Opcode },
3912     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3913     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3914   },
3915
3916   /* PREFIX_0F7E */
3917   {
3918     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3919     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3920     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3921   },
3922
3923   /* PREFIX_0F7F */
3924   {
3925     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3926     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3927     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3928   },
3929
3930   /* PREFIX_0FAE_REG_0_MOD_3 */
3931   {
3932     { Bad_Opcode },
3933     { "rdfsbase", { Ev }, 0 },
3934   },
3935
3936   /* PREFIX_0FAE_REG_1_MOD_3 */
3937   {
3938     { Bad_Opcode },
3939     { "rdgsbase", { Ev }, 0 },
3940   },
3941
3942   /* PREFIX_0FAE_REG_2_MOD_3 */
3943   {
3944     { Bad_Opcode },
3945     { "wrfsbase", { Ev }, 0 },
3946   },
3947
3948   /* PREFIX_0FAE_REG_3_MOD_3 */
3949   {
3950     { Bad_Opcode },
3951     { "wrgsbase", { Ev }, 0 },
3952   },
3953
3954   /* PREFIX_0FAE_REG_4_MOD_0 */
3955   {
3956     { "xsave",  { FXSAVE }, 0 },
3957     { "ptwrite{%LQ|}", { Edq }, 0 },
3958   },
3959
3960   /* PREFIX_0FAE_REG_4_MOD_3 */
3961   {
3962     { Bad_Opcode },
3963     { "ptwrite{%LQ|}", { Edq }, 0 },
3964   },
3965
3966   /* PREFIX_0FAE_REG_5_MOD_0 */
3967   {
3968     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3969   },
3970
3971   /* PREFIX_0FAE_REG_5_MOD_3 */
3972   {
3973     { "lfence",         { Skip_MODRM }, 0 },
3974     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3975   },
3976
3977   /* PREFIX_0FAE_REG_6_MOD_0 */
3978   {
3979     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3980     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3981     { "clwb",   { Mb }, PREFIX_OPCODE },
3982   },
3983
3984   /* PREFIX_0FAE_REG_6_MOD_3 */
3985   {
3986     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3987     { "umonitor",       { Eva }, PREFIX_OPCODE },
3988     { "tpause", { Edq }, PREFIX_OPCODE },
3989     { "umwait", { Edq }, PREFIX_OPCODE },
3990   },
3991
3992   /* PREFIX_0FAE_REG_7_MOD_0 */
3993   {
3994     { "clflush",        { Mb }, 0 },
3995     { Bad_Opcode },
3996     { "clflushopt",     { Mb }, 0 },
3997   },
3998
3999   /* PREFIX_0FB8 */
4000   {
4001     { Bad_Opcode },
4002     { "popcntS", { Gv, Ev }, 0 },
4003   },
4004
4005   /* PREFIX_0FBC */
4006   {
4007     { "bsfS",   { Gv, Ev }, 0 },
4008     { "tzcntS", { Gv, Ev }, 0 },
4009     { "bsfS",   { Gv, Ev }, 0 },
4010   },
4011
4012   /* PREFIX_0FBD */
4013   {
4014     { "bsrS",   { Gv, Ev }, 0 },
4015     { "lzcntS", { Gv, Ev }, 0 },
4016     { "bsrS",   { Gv, Ev }, 0 },
4017   },
4018
4019   /* PREFIX_0FC2 */
4020   {
4021     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4022     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4023     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4024     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4025   },
4026
4027   /* PREFIX_0FC3_MOD_0 */
4028   {
4029     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4030   },
4031
4032   /* PREFIX_0FC7_REG_6_MOD_0 */
4033   {
4034     { "vmptrld",{ Mq }, 0 },
4035     { "vmxon",  { Mq }, 0 },
4036     { "vmclear",{ Mq }, 0 },
4037   },
4038
4039   /* PREFIX_0FC7_REG_6_MOD_3 */
4040   {
4041     { "rdrand", { Ev }, 0 },
4042     { Bad_Opcode },
4043     { "rdrand", { Ev }, 0 }
4044   },
4045
4046   /* PREFIX_0FC7_REG_7_MOD_3 */
4047   {
4048     { "rdseed", { Ev }, 0 },
4049     { "rdpid",  { Em }, 0 },
4050     { "rdseed", { Ev }, 0 },
4051   },
4052
4053   /* PREFIX_0FD0 */
4054   {
4055     { Bad_Opcode },
4056     { Bad_Opcode },
4057     { "addsubpd", { XM, EXx }, 0 },
4058     { "addsubps", { XM, EXx }, 0 },
4059   },
4060
4061   /* PREFIX_0FD6 */
4062   {
4063     { Bad_Opcode },
4064     { "movq2dq",{ XM, MS }, 0 },
4065     { "movq",   { EXqS, XM }, 0 },
4066     { "movdq2q",{ MX, XS }, 0 },
4067   },
4068
4069   /* PREFIX_0FE6 */
4070   {
4071     { Bad_Opcode },
4072     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4073     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4074     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4075   },
4076
4077   /* PREFIX_0FE7 */
4078   {
4079     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4080     { Bad_Opcode },
4081     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4082   },
4083
4084   /* PREFIX_0FF0 */
4085   {
4086     { Bad_Opcode },
4087     { Bad_Opcode },
4088     { Bad_Opcode },
4089     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4090   },
4091
4092   /* PREFIX_0FF7 */
4093   {
4094     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4095     { Bad_Opcode },
4096     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4097   },
4098
4099   /* PREFIX_0F3810 */
4100   {
4101     { Bad_Opcode },
4102     { Bad_Opcode },
4103     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4104   },
4105
4106   /* PREFIX_0F3814 */
4107   {
4108     { Bad_Opcode },
4109     { Bad_Opcode },
4110     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4111   },
4112
4113   /* PREFIX_0F3815 */
4114   {
4115     { Bad_Opcode },
4116     { Bad_Opcode },
4117     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4118   },
4119
4120   /* PREFIX_0F3817 */
4121   {
4122     { Bad_Opcode },
4123     { Bad_Opcode },
4124     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4125   },
4126
4127   /* PREFIX_0F3820 */
4128   {
4129     { Bad_Opcode },
4130     { Bad_Opcode },
4131     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4132   },
4133
4134   /* PREFIX_0F3821 */
4135   {
4136     { Bad_Opcode },
4137     { Bad_Opcode },
4138     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4139   },
4140
4141   /* PREFIX_0F3822 */
4142   {
4143     { Bad_Opcode },
4144     { Bad_Opcode },
4145     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4146   },
4147
4148   /* PREFIX_0F3823 */
4149   {
4150     { Bad_Opcode },
4151     { Bad_Opcode },
4152     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4153   },
4154
4155   /* PREFIX_0F3824 */
4156   {
4157     { Bad_Opcode },
4158     { Bad_Opcode },
4159     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4160   },
4161
4162   /* PREFIX_0F3825 */
4163   {
4164     { Bad_Opcode },
4165     { Bad_Opcode },
4166     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4167   },
4168
4169   /* PREFIX_0F3828 */
4170   {
4171     { Bad_Opcode },
4172     { Bad_Opcode },
4173     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4174   },
4175
4176   /* PREFIX_0F3829 */
4177   {
4178     { Bad_Opcode },
4179     { Bad_Opcode },
4180     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4181   },
4182
4183   /* PREFIX_0F382A */
4184   {
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4188   },
4189
4190   /* PREFIX_0F382B */
4191   {
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4195   },
4196
4197   /* PREFIX_0F3830 */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4202   },
4203
4204   /* PREFIX_0F3831 */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4209   },
4210
4211   /* PREFIX_0F3832 */
4212   {
4213     { Bad_Opcode },
4214     { Bad_Opcode },
4215     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4216   },
4217
4218   /* PREFIX_0F3833 */
4219   {
4220     { Bad_Opcode },
4221     { Bad_Opcode },
4222     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4223   },
4224
4225   /* PREFIX_0F3834 */
4226   {
4227     { Bad_Opcode },
4228     { Bad_Opcode },
4229     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4230   },
4231
4232   /* PREFIX_0F3835 */
4233   {
4234     { Bad_Opcode },
4235     { Bad_Opcode },
4236     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4237   },
4238
4239   /* PREFIX_0F3837 */
4240   {
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4244   },
4245
4246   /* PREFIX_0F3838 */
4247   {
4248     { Bad_Opcode },
4249     { Bad_Opcode },
4250     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4251   },
4252
4253   /* PREFIX_0F3839 */
4254   {
4255     { Bad_Opcode },
4256     { Bad_Opcode },
4257     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4258   },
4259
4260   /* PREFIX_0F383A */
4261   {
4262     { Bad_Opcode },
4263     { Bad_Opcode },
4264     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4265   },
4266
4267   /* PREFIX_0F383B */
4268   {
4269     { Bad_Opcode },
4270     { Bad_Opcode },
4271     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4272   },
4273
4274   /* PREFIX_0F383C */
4275   {
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4279   },
4280
4281   /* PREFIX_0F383D */
4282   {
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4286   },
4287
4288   /* PREFIX_0F383E */
4289   {
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4293   },
4294
4295   /* PREFIX_0F383F */
4296   {
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4300   },
4301
4302   /* PREFIX_0F3840 */
4303   {
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4307   },
4308
4309   /* PREFIX_0F3841 */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4314   },
4315
4316   /* PREFIX_0F3880 */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4321   },
4322
4323   /* PREFIX_0F3881 */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4328   },
4329
4330   /* PREFIX_0F3882 */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4335   },
4336
4337   /* PREFIX_0F38C8 */
4338   {
4339     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4340   },
4341
4342   /* PREFIX_0F38C9 */
4343   {
4344     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4345   },
4346
4347   /* PREFIX_0F38CA */
4348   {
4349     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4350   },
4351
4352   /* PREFIX_0F38CB */
4353   {
4354     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4355   },
4356
4357   /* PREFIX_0F38CC */
4358   {
4359     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4360   },
4361
4362   /* PREFIX_0F38CD */
4363   {
4364     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4365   },
4366
4367   /* PREFIX_0F38CF */
4368   {
4369     { Bad_Opcode },
4370     { Bad_Opcode },
4371     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4372   },
4373
4374   /* PREFIX_0F38DB */
4375   {
4376     { Bad_Opcode },
4377     { Bad_Opcode },
4378     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4379   },
4380
4381   /* PREFIX_0F38DC */
4382   {
4383     { Bad_Opcode },
4384     { Bad_Opcode },
4385     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4386   },
4387
4388   /* PREFIX_0F38DD */
4389   {
4390     { Bad_Opcode },
4391     { Bad_Opcode },
4392     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4393   },
4394
4395   /* PREFIX_0F38DE */
4396   {
4397     { Bad_Opcode },
4398     { Bad_Opcode },
4399     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4400   },
4401
4402   /* PREFIX_0F38DF */
4403   {
4404     { Bad_Opcode },
4405     { Bad_Opcode },
4406     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4407   },
4408
4409   /* PREFIX_0F38F0 */
4410   {
4411     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
4412     { Bad_Opcode },
4413     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
4414     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
4415   },
4416
4417   /* PREFIX_0F38F1 */
4418   {
4419     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
4420     { Bad_Opcode },
4421     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
4422     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
4423   },
4424
4425   /* PREFIX_0F38F5 */
4426   {
4427     { Bad_Opcode },
4428     { Bad_Opcode },
4429     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4430   },
4431
4432   /* PREFIX_0F38F6 */
4433   {
4434     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4435     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4436     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4437     { Bad_Opcode },
4438   },
4439
4440   /* PREFIX_0F38F8 */
4441   {
4442     { Bad_Opcode },
4443     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4444     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4445     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4446   },
4447
4448   /* PREFIX_0F38F9 */
4449   {
4450     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4451   },
4452
4453   /* PREFIX_0F3A08 */
4454   {
4455     { Bad_Opcode },
4456     { Bad_Opcode },
4457     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4458   },
4459
4460   /* PREFIX_0F3A09 */
4461   {
4462     { Bad_Opcode },
4463     { Bad_Opcode },
4464     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4465   },
4466
4467   /* PREFIX_0F3A0A */
4468   {
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4472   },
4473
4474   /* PREFIX_0F3A0B */
4475   {
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4479   },
4480
4481   /* PREFIX_0F3A0C */
4482   {
4483     { Bad_Opcode },
4484     { Bad_Opcode },
4485     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4486   },
4487
4488   /* PREFIX_0F3A0D */
4489   {
4490     { Bad_Opcode },
4491     { Bad_Opcode },
4492     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4493   },
4494
4495   /* PREFIX_0F3A0E */
4496   {
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4500   },
4501
4502   /* PREFIX_0F3A14 */
4503   {
4504     { Bad_Opcode },
4505     { Bad_Opcode },
4506     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4507   },
4508
4509   /* PREFIX_0F3A15 */
4510   {
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4514   },
4515
4516   /* PREFIX_0F3A16 */
4517   {
4518     { Bad_Opcode },
4519     { Bad_Opcode },
4520     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4521   },
4522
4523   /* PREFIX_0F3A17 */
4524   {
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4528   },
4529
4530   /* PREFIX_0F3A20 */
4531   {
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4535   },
4536
4537   /* PREFIX_0F3A21 */
4538   {
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4542   },
4543
4544   /* PREFIX_0F3A22 */
4545   {
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4549   },
4550
4551   /* PREFIX_0F3A40 */
4552   {
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4556   },
4557
4558   /* PREFIX_0F3A41 */
4559   {
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4563   },
4564
4565   /* PREFIX_0F3A42 */
4566   {
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4570   },
4571
4572   /* PREFIX_0F3A44 */
4573   {
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4577   },
4578
4579   /* PREFIX_0F3A60 */
4580   {
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_OPCODE },
4584   },
4585
4586   /* PREFIX_0F3A61 */
4587   {
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_OPCODE },
4591   },
4592
4593   /* PREFIX_0F3A62 */
4594   {
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4598   },
4599
4600   /* PREFIX_0F3A63 */
4601   {
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4605   },
4606
4607   /* PREFIX_0F3ACC */
4608   {
4609     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4610   },
4611
4612   /* PREFIX_0F3ACE */
4613   {
4614     { Bad_Opcode },
4615     { Bad_Opcode },
4616     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4617   },
4618
4619   /* PREFIX_0F3ACF */
4620   {
4621     { Bad_Opcode },
4622     { Bad_Opcode },
4623     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4624   },
4625
4626   /* PREFIX_0F3ADF */
4627   {
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4631   },
4632
4633   /* PREFIX_VEX_0F10 */
4634   {
4635     { "vmovups",        { XM, EXx }, 0 },
4636     { "vmovss",         { XMVexScalar, VexScalar, EXxmm_md }, 0 },
4637     { "vmovupd",        { XM, EXx }, 0 },
4638     { "vmovsd",         { XMVexScalar, VexScalar, EXxmm_mq }, 0 },
4639   },
4640
4641   /* PREFIX_VEX_0F11 */
4642   {
4643     { "vmovups",        { EXxS, XM }, 0 },
4644     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4645     { "vmovupd",        { EXxS, XM }, 0 },
4646     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4647   },
4648
4649   /* PREFIX_VEX_0F12 */
4650   {
4651     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4652     { "vmovsldup",      { XM, EXx }, 0 },
4653     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4654     { "vmovddup",       { XM, EXymmq }, 0 },
4655   },
4656
4657   /* PREFIX_VEX_0F16 */
4658   {
4659     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4660     { "vmovshdup",      { XM, EXx }, 0 },
4661     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4662   },
4663
4664   /* PREFIX_VEX_0F2A */
4665   {
4666     { Bad_Opcode },
4667     { "vcvtsi2ss{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
4668     { Bad_Opcode },
4669     { "vcvtsi2sd{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
4670   },
4671
4672   /* PREFIX_VEX_0F2C */
4673   {
4674     { Bad_Opcode },
4675     { "vcvttss2si",     { Gdq, EXxmm_md }, 0 },
4676     { Bad_Opcode },
4677     { "vcvttsd2si",     { Gdq, EXxmm_mq }, 0 },
4678   },
4679
4680   /* PREFIX_VEX_0F2D */
4681   {
4682     { Bad_Opcode },
4683     { "vcvtss2si",      { Gdq, EXxmm_md }, 0 },
4684     { Bad_Opcode },
4685     { "vcvtsd2si",      { Gdq, EXxmm_mq }, 0 },
4686   },
4687
4688   /* PREFIX_VEX_0F2E */
4689   {
4690     { "vucomiss",       { XMScalar, EXxmm_md }, 0 },
4691     { Bad_Opcode },
4692     { "vucomisd",       { XMScalar, EXxmm_mq }, 0 },
4693   },
4694
4695   /* PREFIX_VEX_0F2F */
4696   {
4697     { "vcomiss",        { XMScalar, EXxmm_md }, 0 },
4698     { Bad_Opcode },
4699     { "vcomisd",        { XMScalar, EXxmm_mq }, 0 },
4700   },
4701
4702   /* PREFIX_VEX_0F41 */
4703   {
4704     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4705     { Bad_Opcode },
4706     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4707   },
4708
4709   /* PREFIX_VEX_0F42 */
4710   {
4711     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4712     { Bad_Opcode },
4713     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4714   },
4715
4716   /* PREFIX_VEX_0F44 */
4717   {
4718     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4719     { Bad_Opcode },
4720     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4721   },
4722
4723   /* PREFIX_VEX_0F45 */
4724   {
4725     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4726     { Bad_Opcode },
4727     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4728   },
4729
4730   /* PREFIX_VEX_0F46 */
4731   {
4732     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4733     { Bad_Opcode },
4734     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4735   },
4736
4737   /* PREFIX_VEX_0F47 */
4738   {
4739     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4740     { Bad_Opcode },
4741     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4742   },
4743
4744   /* PREFIX_VEX_0F4A */
4745   {
4746     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4747     { Bad_Opcode },
4748     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4749   },
4750
4751   /* PREFIX_VEX_0F4B */
4752   {
4753     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4754     { Bad_Opcode },
4755     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4756   },
4757
4758   /* PREFIX_VEX_0F51 */
4759   {
4760     { "vsqrtps",        { XM, EXx }, 0 },
4761     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
4762     { "vsqrtpd",        { XM, EXx }, 0 },
4763     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
4764   },
4765
4766   /* PREFIX_VEX_0F52 */
4767   {
4768     { "vrsqrtps",       { XM, EXx }, 0 },
4769     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
4770   },
4771
4772   /* PREFIX_VEX_0F53 */
4773   {
4774     { "vrcpps",         { XM, EXx }, 0 },
4775     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4776   },
4777
4778   /* PREFIX_VEX_0F58 */
4779   {
4780     { "vaddps",         { XM, Vex, EXx }, 0 },
4781     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4782     { "vaddpd",         { XM, Vex, EXx }, 0 },
4783     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4784   },
4785
4786   /* PREFIX_VEX_0F59 */
4787   {
4788     { "vmulps",         { XM, Vex, EXx }, 0 },
4789     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4790     { "vmulpd",         { XM, Vex, EXx }, 0 },
4791     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4792   },
4793
4794   /* PREFIX_VEX_0F5A */
4795   {
4796     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4797     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
4798     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4799     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
4800   },
4801
4802   /* PREFIX_VEX_0F5B */
4803   {
4804     { "vcvtdq2ps",      { XM, EXx }, 0 },
4805     { "vcvttps2dq",     { XM, EXx }, 0 },
4806     { "vcvtps2dq",      { XM, EXx }, 0 },
4807   },
4808
4809   /* PREFIX_VEX_0F5C */
4810   {
4811     { "vsubps",         { XM, Vex, EXx }, 0 },
4812     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4813     { "vsubpd",         { XM, Vex, EXx }, 0 },
4814     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4815   },
4816
4817   /* PREFIX_VEX_0F5D */
4818   {
4819     { "vminps",         { XM, Vex, EXx }, 0 },
4820     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4821     { "vminpd",         { XM, Vex, EXx }, 0 },
4822     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4823   },
4824
4825   /* PREFIX_VEX_0F5E */
4826   {
4827     { "vdivps",         { XM, Vex, EXx }, 0 },
4828     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4829     { "vdivpd",         { XM, Vex, EXx }, 0 },
4830     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4831   },
4832
4833   /* PREFIX_VEX_0F5F */
4834   {
4835     { "vmaxps",         { XM, Vex, EXx }, 0 },
4836     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4837     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4838     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4839   },
4840
4841   /* PREFIX_VEX_0F60 */
4842   {
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4846   },
4847
4848   /* PREFIX_VEX_0F61 */
4849   {
4850     { Bad_Opcode },
4851     { Bad_Opcode },
4852     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4853   },
4854
4855   /* PREFIX_VEX_0F62 */
4856   {
4857     { Bad_Opcode },
4858     { Bad_Opcode },
4859     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4860   },
4861
4862   /* PREFIX_VEX_0F63 */
4863   {
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4867   },
4868
4869   /* PREFIX_VEX_0F64 */
4870   {
4871     { Bad_Opcode },
4872     { Bad_Opcode },
4873     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4874   },
4875
4876   /* PREFIX_VEX_0F65 */
4877   {
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4881   },
4882
4883   /* PREFIX_VEX_0F66 */
4884   {
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4888   },
4889
4890   /* PREFIX_VEX_0F67 */
4891   {
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4895   },
4896
4897   /* PREFIX_VEX_0F68 */
4898   {
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4902   },
4903
4904   /* PREFIX_VEX_0F69 */
4905   {
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4909   },
4910
4911   /* PREFIX_VEX_0F6A */
4912   {
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4916   },
4917
4918   /* PREFIX_VEX_0F6B */
4919   {
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4923   },
4924
4925   /* PREFIX_VEX_0F6C */
4926   {
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4930   },
4931
4932   /* PREFIX_VEX_0F6D */
4933   {
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4937   },
4938
4939   /* PREFIX_VEX_0F6E */
4940   {
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4944   },
4945
4946   /* PREFIX_VEX_0F6F */
4947   {
4948     { Bad_Opcode },
4949     { "vmovdqu",        { XM, EXx }, 0 },
4950     { "vmovdqa",        { XM, EXx }, 0 },
4951   },
4952
4953   /* PREFIX_VEX_0F70 */
4954   {
4955     { Bad_Opcode },
4956     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4957     { "vpshufd",        { XM, EXx, Ib }, 0 },
4958     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4959   },
4960
4961   /* PREFIX_VEX_0F71_REG_2 */
4962   {
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4966   },
4967
4968   /* PREFIX_VEX_0F71_REG_4 */
4969   {
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { "vpsraw",         { Vex, XS, Ib }, 0 },
4973   },
4974
4975   /* PREFIX_VEX_0F71_REG_6 */
4976   {
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { "vpsllw",         { Vex, XS, Ib }, 0 },
4980   },
4981
4982   /* PREFIX_VEX_0F72_REG_2 */
4983   {
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { "vpsrld",         { Vex, XS, Ib }, 0 },
4987   },
4988
4989   /* PREFIX_VEX_0F72_REG_4 */
4990   {
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { "vpsrad",         { Vex, XS, Ib }, 0 },
4994   },
4995
4996   /* PREFIX_VEX_0F72_REG_6 */
4997   {
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { "vpslld",         { Vex, XS, Ib }, 0 },
5001   },
5002
5003   /* PREFIX_VEX_0F73_REG_2 */
5004   {
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5008   },
5009
5010   /* PREFIX_VEX_0F73_REG_3 */
5011   {
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5015   },
5016
5017   /* PREFIX_VEX_0F73_REG_6 */
5018   {
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { "vpsllq",         { Vex, XS, Ib }, 0 },
5022   },
5023
5024   /* PREFIX_VEX_0F73_REG_7 */
5025   {
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { "vpslldq",        { Vex, XS, Ib }, 0 },
5029   },
5030
5031   /* PREFIX_VEX_0F74 */
5032   {
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5036   },
5037
5038   /* PREFIX_VEX_0F75 */
5039   {
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5043   },
5044
5045   /* PREFIX_VEX_0F76 */
5046   {
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5050   },
5051
5052   /* PREFIX_VEX_0F77 */
5053   {
5054     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5055   },
5056
5057   /* PREFIX_VEX_0F7C */
5058   {
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5062     { "vhaddps",        { XM, Vex, EXx }, 0 },
5063   },
5064
5065   /* PREFIX_VEX_0F7D */
5066   {
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5070     { "vhsubps",        { XM, Vex, EXx }, 0 },
5071   },
5072
5073   /* PREFIX_VEX_0F7E */
5074   {
5075     { Bad_Opcode },
5076     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5077     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5078   },
5079
5080   /* PREFIX_VEX_0F7F */
5081   {
5082     { Bad_Opcode },
5083     { "vmovdqu",        { EXxS, XM }, 0 },
5084     { "vmovdqa",        { EXxS, XM }, 0 },
5085   },
5086
5087   /* PREFIX_VEX_0F90 */
5088   {
5089     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5090     { Bad_Opcode },
5091     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5092   },
5093
5094   /* PREFIX_VEX_0F91 */
5095   {
5096     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5097     { Bad_Opcode },
5098     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5099   },
5100
5101   /* PREFIX_VEX_0F92 */
5102   {
5103     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5104     { Bad_Opcode },
5105     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5106     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5107   },
5108
5109   /* PREFIX_VEX_0F93 */
5110   {
5111     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5112     { Bad_Opcode },
5113     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5114     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5115   },
5116
5117   /* PREFIX_VEX_0F98 */
5118   {
5119     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5120     { Bad_Opcode },
5121     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5122   },
5123
5124   /* PREFIX_VEX_0F99 */
5125   {
5126     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5127     { Bad_Opcode },
5128     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5129   },
5130
5131   /* PREFIX_VEX_0FC2 */
5132   {
5133     { "vcmpps",         { XM, Vex, EXx, CMP }, 0 },
5134     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
5135     { "vcmppd",         { XM, Vex, EXx, CMP }, 0 },
5136     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
5137   },
5138
5139   /* PREFIX_VEX_0FC4 */
5140   {
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5144   },
5145
5146   /* PREFIX_VEX_0FC5 */
5147   {
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5151   },
5152
5153   /* PREFIX_VEX_0FD0 */
5154   {
5155     { Bad_Opcode },
5156     { Bad_Opcode },
5157     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5158     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5159   },
5160
5161   /* PREFIX_VEX_0FD1 */
5162   {
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5166   },
5167
5168   /* PREFIX_VEX_0FD2 */
5169   {
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5173   },
5174
5175   /* PREFIX_VEX_0FD3 */
5176   {
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5180   },
5181
5182   /* PREFIX_VEX_0FD4 */
5183   {
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { "vpaddq",         { XM, Vex, EXx }, 0 },
5187   },
5188
5189   /* PREFIX_VEX_0FD5 */
5190   {
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { "vpmullw",        { XM, Vex, EXx }, 0 },
5194   },
5195
5196   /* PREFIX_VEX_0FD6 */
5197   {
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5201   },
5202
5203   /* PREFIX_VEX_0FD7 */
5204   {
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5208   },
5209
5210   /* PREFIX_VEX_0FD8 */
5211   {
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5215   },
5216
5217   /* PREFIX_VEX_0FD9 */
5218   {
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5222   },
5223
5224   /* PREFIX_VEX_0FDA */
5225   {
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { "vpminub",        { XM, Vex, EXx }, 0 },
5229   },
5230
5231   /* PREFIX_VEX_0FDB */
5232   {
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { "vpand",          { XM, Vex, EXx }, 0 },
5236   },
5237
5238   /* PREFIX_VEX_0FDC */
5239   {
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5243   },
5244
5245   /* PREFIX_VEX_0FDD */
5246   {
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5250   },
5251
5252   /* PREFIX_VEX_0FDE */
5253   {
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5257   },
5258
5259   /* PREFIX_VEX_0FDF */
5260   {
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { "vpandn",         { XM, Vex, EXx }, 0 },
5264   },
5265
5266   /* PREFIX_VEX_0FE0 */
5267   {
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { "vpavgb",         { XM, Vex, EXx }, 0 },
5271   },
5272
5273   /* PREFIX_VEX_0FE1 */
5274   {
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5278   },
5279
5280   /* PREFIX_VEX_0FE2 */
5281   {
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5285   },
5286
5287   /* PREFIX_VEX_0FE3 */
5288   {
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { "vpavgw",         { XM, Vex, EXx }, 0 },
5292   },
5293
5294   /* PREFIX_VEX_0FE4 */
5295   {
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5299   },
5300
5301   /* PREFIX_VEX_0FE5 */
5302   {
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5306   },
5307
5308   /* PREFIX_VEX_0FE6 */
5309   {
5310     { Bad_Opcode },
5311     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5312     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5313     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5314   },
5315
5316   /* PREFIX_VEX_0FE7 */
5317   {
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5321   },
5322
5323   /* PREFIX_VEX_0FE8 */
5324   {
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5328   },
5329
5330   /* PREFIX_VEX_0FE9 */
5331   {
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5335   },
5336
5337   /* PREFIX_VEX_0FEA */
5338   {
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { "vpminsw",        { XM, Vex, EXx }, 0 },
5342   },
5343
5344   /* PREFIX_VEX_0FEB */
5345   {
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { "vpor",           { XM, Vex, EXx }, 0 },
5349   },
5350
5351   /* PREFIX_VEX_0FEC */
5352   {
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5356   },
5357
5358   /* PREFIX_VEX_0FED */
5359   {
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5363   },
5364
5365   /* PREFIX_VEX_0FEE */
5366   {
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5370   },
5371
5372   /* PREFIX_VEX_0FEF */
5373   {
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { "vpxor",          { XM, Vex, EXx }, 0 },
5377   },
5378
5379   /* PREFIX_VEX_0FF0 */
5380   {
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5385   },
5386
5387   /* PREFIX_VEX_0FF1 */
5388   {
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5392   },
5393
5394   /* PREFIX_VEX_0FF2 */
5395   {
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5399   },
5400
5401   /* PREFIX_VEX_0FF3 */
5402   {
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5406   },
5407
5408   /* PREFIX_VEX_0FF4 */
5409   {
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5413   },
5414
5415   /* PREFIX_VEX_0FF5 */
5416   {
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5420   },
5421
5422   /* PREFIX_VEX_0FF6 */
5423   {
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5427   },
5428
5429   /* PREFIX_VEX_0FF7 */
5430   {
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5434   },
5435
5436   /* PREFIX_VEX_0FF8 */
5437   {
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { "vpsubb",         { XM, Vex, EXx }, 0 },
5441   },
5442
5443   /* PREFIX_VEX_0FF9 */
5444   {
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { "vpsubw",         { XM, Vex, EXx }, 0 },
5448   },
5449
5450   /* PREFIX_VEX_0FFA */
5451   {
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { "vpsubd",         { XM, Vex, EXx }, 0 },
5455   },
5456
5457   /* PREFIX_VEX_0FFB */
5458   {
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { "vpsubq",         { XM, Vex, EXx }, 0 },
5462   },
5463
5464   /* PREFIX_VEX_0FFC */
5465   {
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { "vpaddb",         { XM, Vex, EXx }, 0 },
5469   },
5470
5471   /* PREFIX_VEX_0FFD */
5472   {
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { "vpaddw",         { XM, Vex, EXx }, 0 },
5476   },
5477
5478   /* PREFIX_VEX_0FFE */
5479   {
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { "vpaddd",         { XM, Vex, EXx }, 0 },
5483   },
5484
5485   /* PREFIX_VEX_0F3800 */
5486   {
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { "vpshufb",        { XM, Vex, EXx }, 0 },
5490   },
5491
5492   /* PREFIX_VEX_0F3801 */
5493   {
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { "vphaddw",        { XM, Vex, EXx }, 0 },
5497   },
5498
5499   /* PREFIX_VEX_0F3802 */
5500   {
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { "vphaddd",        { XM, Vex, EXx }, 0 },
5504   },
5505
5506   /* PREFIX_VEX_0F3803 */
5507   {
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5511   },
5512
5513   /* PREFIX_VEX_0F3804 */
5514   {
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5518   },
5519
5520   /* PREFIX_VEX_0F3805 */
5521   {
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { "vphsubw",        { XM, Vex, EXx }, 0 },
5525   },
5526
5527   /* PREFIX_VEX_0F3806 */
5528   {
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { "vphsubd",        { XM, Vex, EXx }, 0 },
5532   },
5533
5534   /* PREFIX_VEX_0F3807 */
5535   {
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5539   },
5540
5541   /* PREFIX_VEX_0F3808 */
5542   {
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { "vpsignb",        { XM, Vex, EXx }, 0 },
5546   },
5547
5548   /* PREFIX_VEX_0F3809 */
5549   {
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { "vpsignw",        { XM, Vex, EXx }, 0 },
5553   },
5554
5555   /* PREFIX_VEX_0F380A */
5556   {
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { "vpsignd",        { XM, Vex, EXx }, 0 },
5560   },
5561
5562   /* PREFIX_VEX_0F380B */
5563   {
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5567   },
5568
5569   /* PREFIX_VEX_0F380C */
5570   {
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5574   },
5575
5576   /* PREFIX_VEX_0F380D */
5577   {
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5581   },
5582
5583   /* PREFIX_VEX_0F380E */
5584   {
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5588   },
5589
5590   /* PREFIX_VEX_0F380F */
5591   {
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5595   },
5596
5597   /* PREFIX_VEX_0F3813 */
5598   {
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { VEX_W_TABLE (VEX_W_0F3813_P_2) },
5602   },
5603
5604   /* PREFIX_VEX_0F3816 */
5605   {
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5609   },
5610
5611   /* PREFIX_VEX_0F3817 */
5612   {
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { "vptest",         { XM, EXx }, 0 },
5616   },
5617
5618   /* PREFIX_VEX_0F3818 */
5619   {
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5623   },
5624
5625   /* PREFIX_VEX_0F3819 */
5626   {
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5630   },
5631
5632   /* PREFIX_VEX_0F381A */
5633   {
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5637   },
5638
5639   /* PREFIX_VEX_0F381C */
5640   {
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { "vpabsb",         { XM, EXx }, 0 },
5644   },
5645
5646   /* PREFIX_VEX_0F381D */
5647   {
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { "vpabsw",         { XM, EXx }, 0 },
5651   },
5652
5653   /* PREFIX_VEX_0F381E */
5654   {
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { "vpabsd",         { XM, EXx }, 0 },
5658   },
5659
5660   /* PREFIX_VEX_0F3820 */
5661   {
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5665   },
5666
5667   /* PREFIX_VEX_0F3821 */
5668   {
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5672   },
5673
5674   /* PREFIX_VEX_0F3822 */
5675   {
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5679   },
5680
5681   /* PREFIX_VEX_0F3823 */
5682   {
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5686   },
5687
5688   /* PREFIX_VEX_0F3824 */
5689   {
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5693   },
5694
5695   /* PREFIX_VEX_0F3825 */
5696   {
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5700   },
5701
5702   /* PREFIX_VEX_0F3828 */
5703   {
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5707   },
5708
5709   /* PREFIX_VEX_0F3829 */
5710   {
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5714   },
5715
5716   /* PREFIX_VEX_0F382A */
5717   {
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5721   },
5722
5723   /* PREFIX_VEX_0F382B */
5724   {
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5728   },
5729
5730   /* PREFIX_VEX_0F382C */
5731   {
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5735   },
5736
5737   /* PREFIX_VEX_0F382D */
5738   {
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5742   },
5743
5744   /* PREFIX_VEX_0F382E */
5745   {
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5749   },
5750
5751   /* PREFIX_VEX_0F382F */
5752   {
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5756   },
5757
5758   /* PREFIX_VEX_0F3830 */
5759   {
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5763   },
5764
5765   /* PREFIX_VEX_0F3831 */
5766   {
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5770   },
5771
5772   /* PREFIX_VEX_0F3832 */
5773   {
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5777   },
5778
5779   /* PREFIX_VEX_0F3833 */
5780   {
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5784   },
5785
5786   /* PREFIX_VEX_0F3834 */
5787   {
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5791   },
5792
5793   /* PREFIX_VEX_0F3835 */
5794   {
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5798   },
5799
5800   /* PREFIX_VEX_0F3836 */
5801   {
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5805   },
5806
5807   /* PREFIX_VEX_0F3837 */
5808   {
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5812   },
5813
5814   /* PREFIX_VEX_0F3838 */
5815   {
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { "vpminsb",        { XM, Vex, EXx }, 0 },
5819   },
5820
5821   /* PREFIX_VEX_0F3839 */
5822   {
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { "vpminsd",        { XM, Vex, EXx }, 0 },
5826   },
5827
5828   /* PREFIX_VEX_0F383A */
5829   {
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { "vpminuw",        { XM, Vex, EXx }, 0 },
5833   },
5834
5835   /* PREFIX_VEX_0F383B */
5836   {
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { "vpminud",        { XM, Vex, EXx }, 0 },
5840   },
5841
5842   /* PREFIX_VEX_0F383C */
5843   {
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5847   },
5848
5849   /* PREFIX_VEX_0F383D */
5850   {
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5854   },
5855
5856   /* PREFIX_VEX_0F383E */
5857   {
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5861   },
5862
5863   /* PREFIX_VEX_0F383F */
5864   {
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5868   },
5869
5870   /* PREFIX_VEX_0F3840 */
5871   {
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { "vpmulld",        { XM, Vex, EXx }, 0 },
5875   },
5876
5877   /* PREFIX_VEX_0F3841 */
5878   {
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5882   },
5883
5884   /* PREFIX_VEX_0F3845 */
5885   {
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { "vpsrlv%DQ", { XM, Vex, EXx }, 0 },
5889   },
5890
5891   /* PREFIX_VEX_0F3846 */
5892   {
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5896   },
5897
5898   /* PREFIX_VEX_0F3847 */
5899   {
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { "vpsllv%DQ", { XM, Vex, EXx }, 0 },
5903   },
5904
5905   /* PREFIX_VEX_0F3849_X86_64 */
5906   {
5907     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
5908     { Bad_Opcode },
5909     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
5910     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
5911   },
5912
5913   /* PREFIX_VEX_0F384B_X86_64 */
5914   {
5915     { Bad_Opcode },
5916     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
5917     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
5918     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
5919   },
5920
5921   /* PREFIX_VEX_0F3858 */
5922   {
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5926   },
5927
5928   /* PREFIX_VEX_0F3859 */
5929   {
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5933   },
5934
5935   /* PREFIX_VEX_0F385A */
5936   {
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5940   },
5941
5942   /* PREFIX_VEX_0F385C_X86_64 */
5943   {
5944     { Bad_Opcode },
5945     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
5946     { Bad_Opcode },
5947   },
5948
5949   /* PREFIX_VEX_0F385E_X86_64 */
5950   {
5951     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
5952     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
5953     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
5954     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
5955   },
5956
5957   /* PREFIX_VEX_0F3878 */
5958   {
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5962   },
5963
5964   /* PREFIX_VEX_0F3879 */
5965   {
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5969   },
5970
5971   /* PREFIX_VEX_0F388C */
5972   {
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5976   },
5977
5978   /* PREFIX_VEX_0F388E */
5979   {
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5983   },
5984
5985   /* PREFIX_VEX_0F3890 */
5986   {
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, 0 },
5990   },
5991
5992   /* PREFIX_VEX_0F3891 */
5993   {
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5997   },
5998
5999   /* PREFIX_VEX_0F3892 */
6000   {
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6004   },
6005
6006   /* PREFIX_VEX_0F3893 */
6007   {
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6011   },
6012
6013   /* PREFIX_VEX_0F3896 */
6014   {
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6018   },
6019
6020   /* PREFIX_VEX_0F3897 */
6021   {
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6025   },
6026
6027   /* PREFIX_VEX_0F3898 */
6028   {
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6032   },
6033
6034   /* PREFIX_VEX_0F3899 */
6035   {
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6039   },
6040
6041   /* PREFIX_VEX_0F389A */
6042   {
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6046   },
6047
6048   /* PREFIX_VEX_0F389B */
6049   {
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6053   },
6054
6055   /* PREFIX_VEX_0F389C */
6056   {
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6060   },
6061
6062   /* PREFIX_VEX_0F389D */
6063   {
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6067   },
6068
6069   /* PREFIX_VEX_0F389E */
6070   {
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6074   },
6075
6076   /* PREFIX_VEX_0F389F */
6077   {
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6081   },
6082
6083   /* PREFIX_VEX_0F38A6 */
6084   {
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6088     { Bad_Opcode },
6089   },
6090
6091   /* PREFIX_VEX_0F38A7 */
6092   {
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6096   },
6097
6098   /* PREFIX_VEX_0F38A8 */
6099   {
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6103   },
6104
6105   /* PREFIX_VEX_0F38A9 */
6106   {
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6110   },
6111
6112   /* PREFIX_VEX_0F38AA */
6113   {
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6117   },
6118
6119   /* PREFIX_VEX_0F38AB */
6120   {
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6124   },
6125
6126   /* PREFIX_VEX_0F38AC */
6127   {
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6131   },
6132
6133   /* PREFIX_VEX_0F38AD */
6134   {
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6138   },
6139
6140   /* PREFIX_VEX_0F38AE */
6141   {
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6145   },
6146
6147   /* PREFIX_VEX_0F38AF */
6148   {
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6152   },
6153
6154   /* PREFIX_VEX_0F38B6 */
6155   {
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6159   },
6160
6161   /* PREFIX_VEX_0F38B7 */
6162   {
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6166   },
6167
6168   /* PREFIX_VEX_0F38B8 */
6169   {
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6173   },
6174
6175   /* PREFIX_VEX_0F38B9 */
6176   {
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6180   },
6181
6182   /* PREFIX_VEX_0F38BA */
6183   {
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6187   },
6188
6189   /* PREFIX_VEX_0F38BB */
6190   {
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6194   },
6195
6196   /* PREFIX_VEX_0F38BC */
6197   {
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6201   },
6202
6203   /* PREFIX_VEX_0F38BD */
6204   {
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6208   },
6209
6210   /* PREFIX_VEX_0F38BE */
6211   {
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6215   },
6216
6217   /* PREFIX_VEX_0F38BF */
6218   {
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6222   },
6223
6224   /* PREFIX_VEX_0F38CF */
6225   {
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6229   },
6230
6231   /* PREFIX_VEX_0F38DB */
6232   {
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6236   },
6237
6238   /* PREFIX_VEX_0F38DC */
6239   {
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { "vaesenc",        { XM, Vex, EXx }, 0 },
6243   },
6244
6245   /* PREFIX_VEX_0F38DD */
6246   {
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6250   },
6251
6252   /* PREFIX_VEX_0F38DE */
6253   {
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { "vaesdec",        { XM, Vex, EXx }, 0 },
6257   },
6258
6259   /* PREFIX_VEX_0F38DF */
6260   {
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6264   },
6265
6266   /* PREFIX_VEX_0F38F2 */
6267   {
6268     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6269   },
6270
6271   /* PREFIX_VEX_0F38F3_REG_1 */
6272   {
6273     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6274   },
6275
6276   /* PREFIX_VEX_0F38F3_REG_2 */
6277   {
6278     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6279   },
6280
6281   /* PREFIX_VEX_0F38F3_REG_3 */
6282   {
6283     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6284   },
6285
6286   /* PREFIX_VEX_0F38F5 */
6287   {
6288     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6289     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6290     { Bad_Opcode },
6291     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6292   },
6293
6294   /* PREFIX_VEX_0F38F6 */
6295   {
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6300   },
6301
6302   /* PREFIX_VEX_0F38F7 */
6303   {
6304     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6305     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6306     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6307     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6308   },
6309
6310   /* PREFIX_VEX_0F3A00 */
6311   {
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6315   },
6316
6317   /* PREFIX_VEX_0F3A01 */
6318   {
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6322   },
6323
6324   /* PREFIX_VEX_0F3A02 */
6325   {
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6329   },
6330
6331   /* PREFIX_VEX_0F3A04 */
6332   {
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6336   },
6337
6338   /* PREFIX_VEX_0F3A05 */
6339   {
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6343   },
6344
6345   /* PREFIX_VEX_0F3A06 */
6346   {
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6350   },
6351
6352   /* PREFIX_VEX_0F3A08 */
6353   {
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { "vroundps",       { XM, EXx, Ib }, 0 },
6357   },
6358
6359   /* PREFIX_VEX_0F3A09 */
6360   {
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { "vroundpd",       { XM, EXx, Ib }, 0 },
6364   },
6365
6366   /* PREFIX_VEX_0F3A0A */
6367   {
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
6371   },
6372
6373   /* PREFIX_VEX_0F3A0B */
6374   {
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
6378   },
6379
6380   /* PREFIX_VEX_0F3A0C */
6381   {
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6385   },
6386
6387   /* PREFIX_VEX_0F3A0D */
6388   {
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6392   },
6393
6394   /* PREFIX_VEX_0F3A0E */
6395   {
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6399   },
6400
6401   /* PREFIX_VEX_0F3A0F */
6402   {
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6406   },
6407
6408   /* PREFIX_VEX_0F3A14 */
6409   {
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6413   },
6414
6415   /* PREFIX_VEX_0F3A15 */
6416   {
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6420   },
6421
6422   /* PREFIX_VEX_0F3A16 */
6423   {
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6427   },
6428
6429   /* PREFIX_VEX_0F3A17 */
6430   {
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6434   },
6435
6436   /* PREFIX_VEX_0F3A18 */
6437   {
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6441   },
6442
6443   /* PREFIX_VEX_0F3A19 */
6444   {
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6448   },
6449
6450   /* PREFIX_VEX_0F3A1D */
6451   {
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { VEX_W_TABLE (VEX_W_0F3A1D_P_2) },
6455   },
6456
6457   /* PREFIX_VEX_0F3A20 */
6458   {
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6462   },
6463
6464   /* PREFIX_VEX_0F3A21 */
6465   {
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6469   },
6470
6471   /* PREFIX_VEX_0F3A22 */
6472   {
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6476   },
6477
6478   /* PREFIX_VEX_0F3A30 */
6479   {
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6483   },
6484
6485   /* PREFIX_VEX_0F3A31 */
6486   {
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6490   },
6491
6492   /* PREFIX_VEX_0F3A32 */
6493   {
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6497   },
6498
6499   /* PREFIX_VEX_0F3A33 */
6500   {
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6504   },
6505
6506   /* PREFIX_VEX_0F3A38 */
6507   {
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6511   },
6512
6513   /* PREFIX_VEX_0F3A39 */
6514   {
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6518   },
6519
6520   /* PREFIX_VEX_0F3A40 */
6521   {
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6525   },
6526
6527   /* PREFIX_VEX_0F3A41 */
6528   {
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6532   },
6533
6534   /* PREFIX_VEX_0F3A42 */
6535   {
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6539   },
6540
6541   /* PREFIX_VEX_0F3A44 */
6542   {
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6546   },
6547
6548   /* PREFIX_VEX_0F3A46 */
6549   {
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6553   },
6554
6555   /* PREFIX_VEX_0F3A48 */
6556   {
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6560   },
6561
6562   /* PREFIX_VEX_0F3A49 */
6563   {
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6567   },
6568
6569   /* PREFIX_VEX_0F3A4A */
6570   {
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6574   },
6575
6576   /* PREFIX_VEX_0F3A4B */
6577   {
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6581   },
6582
6583   /* PREFIX_VEX_0F3A4C */
6584   {
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6588   },
6589
6590   /* PREFIX_VEX_0F3A5C */
6591   {
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6595   },
6596
6597   /* PREFIX_VEX_0F3A5D */
6598   {
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6602   },
6603
6604   /* PREFIX_VEX_0F3A5E */
6605   {
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6609   },
6610
6611   /* PREFIX_VEX_0F3A5F */
6612   {
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6616   },
6617
6618   /* PREFIX_VEX_0F3A60 */
6619   {
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6623     { Bad_Opcode },
6624   },
6625
6626   /* PREFIX_VEX_0F3A61 */
6627   {
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6631   },
6632
6633   /* PREFIX_VEX_0F3A62 */
6634   {
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6638   },
6639
6640   /* PREFIX_VEX_0F3A63 */
6641   {
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6645   },
6646
6647   /* PREFIX_VEX_0F3A68 */
6648   {
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6652   },
6653
6654   /* PREFIX_VEX_0F3A69 */
6655   {
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6659   },
6660
6661   /* PREFIX_VEX_0F3A6A */
6662   {
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { "vfmaddss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6666   },
6667
6668   /* PREFIX_VEX_0F3A6B */
6669   {
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { "vfmaddsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6673   },
6674
6675   /* PREFIX_VEX_0F3A6C */
6676   {
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6680   },
6681
6682   /* PREFIX_VEX_0F3A6D */
6683   {
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6687   },
6688
6689   /* PREFIX_VEX_0F3A6E */
6690   {
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { "vfmsubss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6694   },
6695
6696   /* PREFIX_VEX_0F3A6F */
6697   {
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { "vfmsubsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6701   },
6702
6703   /* PREFIX_VEX_0F3A78 */
6704   {
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6708   },
6709
6710   /* PREFIX_VEX_0F3A79 */
6711   {
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6715   },
6716
6717   /* PREFIX_VEX_0F3A7A */
6718   {
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { "vfnmaddss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6722   },
6723
6724   /* PREFIX_VEX_0F3A7B */
6725   {
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { "vfnmaddsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6729   },
6730
6731   /* PREFIX_VEX_0F3A7C */
6732   {
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6736     { Bad_Opcode },
6737   },
6738
6739   /* PREFIX_VEX_0F3A7D */
6740   {
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6744   },
6745
6746   /* PREFIX_VEX_0F3A7E */
6747   {
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { "vfnmsubss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6751   },
6752
6753   /* PREFIX_VEX_0F3A7F */
6754   {
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { "vfnmsubsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6758   },
6759
6760   /* PREFIX_VEX_0F3ACE */
6761   {
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6765   },
6766
6767   /* PREFIX_VEX_0F3ACF */
6768   {
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6772   },
6773
6774   /* PREFIX_VEX_0F3ADF */
6775   {
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6779   },
6780
6781   /* PREFIX_VEX_0F3AF0 */
6782   {
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6787   },
6788
6789 #include "i386-dis-evex-prefix.h"
6790 };
6791
6792 static const struct dis386 x86_64_table[][2] = {
6793   /* X86_64_06 */
6794   {
6795     { "pushP", { es }, 0 },
6796   },
6797
6798   /* X86_64_07 */
6799   {
6800     { "popP", { es }, 0 },
6801   },
6802
6803   /* X86_64_0E */
6804   {
6805     { "pushP", { cs }, 0 },
6806   },
6807
6808   /* X86_64_16 */
6809   {
6810     { "pushP", { ss }, 0 },
6811   },
6812
6813   /* X86_64_17 */
6814   {
6815     { "popP", { ss }, 0 },
6816   },
6817
6818   /* X86_64_1E */
6819   {
6820     { "pushP", { ds }, 0 },
6821   },
6822
6823   /* X86_64_1F */
6824   {
6825     { "popP", { ds }, 0 },
6826   },
6827
6828   /* X86_64_27 */
6829   {
6830     { "daa", { XX }, 0 },
6831   },
6832
6833   /* X86_64_2F */
6834   {
6835     { "das", { XX }, 0 },
6836   },
6837
6838   /* X86_64_37 */
6839   {
6840     { "aaa", { XX }, 0 },
6841   },
6842
6843   /* X86_64_3F */
6844   {
6845     { "aas", { XX }, 0 },
6846   },
6847
6848   /* X86_64_60 */
6849   {
6850     { "pushaP", { XX }, 0 },
6851   },
6852
6853   /* X86_64_61 */
6854   {
6855     { "popaP", { XX }, 0 },
6856   },
6857
6858   /* X86_64_62 */
6859   {
6860     { MOD_TABLE (MOD_62_32BIT) },
6861     { EVEX_TABLE (EVEX_0F) },
6862   },
6863
6864   /* X86_64_63 */
6865   {
6866     { "arpl", { Ew, Gw }, 0 },
6867     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6868   },
6869
6870   /* X86_64_6D */
6871   {
6872     { "ins{R|}", { Yzr, indirDX }, 0 },
6873     { "ins{G|}", { Yzr, indirDX }, 0 },
6874   },
6875
6876   /* X86_64_6F */
6877   {
6878     { "outs{R|}", { indirDXr, Xz }, 0 },
6879     { "outs{G|}", { indirDXr, Xz }, 0 },
6880   },
6881
6882   /* X86_64_82 */
6883   {
6884     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6885     { REG_TABLE (REG_80) },
6886   },
6887
6888   /* X86_64_9A */
6889   {
6890     { "{l|}call{T|}", { Ap }, 0 },
6891   },
6892
6893   /* X86_64_C2 */
6894   {
6895     { "retP",           { Iw, BND }, 0 },
6896     { "ret@",           { Iw, BND }, 0 },
6897   },
6898
6899   /* X86_64_C3 */
6900   {
6901     { "retP",           { BND }, 0 },
6902     { "ret@",           { BND }, 0 },
6903   },
6904
6905   /* X86_64_C4 */
6906   {
6907     { MOD_TABLE (MOD_C4_32BIT) },
6908     { VEX_C4_TABLE (VEX_0F) },
6909   },
6910
6911   /* X86_64_C5 */
6912   {
6913     { MOD_TABLE (MOD_C5_32BIT) },
6914     { VEX_C5_TABLE (VEX_0F) },
6915   },
6916
6917   /* X86_64_CE */
6918   {
6919     { "into", { XX }, 0 },
6920   },
6921
6922   /* X86_64_D4 */
6923   {
6924     { "aam", { Ib }, 0 },
6925   },
6926
6927   /* X86_64_D5 */
6928   {
6929     { "aad", { Ib }, 0 },
6930   },
6931
6932   /* X86_64_E8 */
6933   {
6934     { "callP",          { Jv, BND }, 0 },
6935     { "call@",          { Jv, BND }, 0 }
6936   },
6937
6938   /* X86_64_E9 */
6939   {
6940     { "jmpP",           { Jv, BND }, 0 },
6941     { "jmp@",           { Jv, BND }, 0 }
6942   },
6943
6944   /* X86_64_EA */
6945   {
6946     { "{l|}jmp{T|}", { Ap }, 0 },
6947   },
6948
6949   /* X86_64_0F01_REG_0 */
6950   {
6951     { "sgdt{Q|Q}", { M }, 0 },
6952     { "sgdt", { M }, 0 },
6953   },
6954
6955   /* X86_64_0F01_REG_1 */
6956   {
6957     { "sidt{Q|Q}", { M }, 0 },
6958     { "sidt", { M }, 0 },
6959   },
6960
6961   /* X86_64_0F01_REG_2 */
6962   {
6963     { "lgdt{Q|Q}", { M }, 0 },
6964     { "lgdt", { M }, 0 },
6965   },
6966
6967   /* X86_64_0F01_REG_3 */
6968   {
6969     { "lidt{Q|Q}", { M }, 0 },
6970     { "lidt", { M }, 0 },
6971   },
6972
6973   /* X86_64_VEX_0F3849 */
6974   {
6975     { Bad_Opcode },
6976     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
6977   },
6978
6979   /* X86_64_VEX_0F384B */
6980   {
6981     { Bad_Opcode },
6982     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
6983   },
6984
6985   /* X86_64_VEX_0F385C */
6986   {
6987     { Bad_Opcode },
6988     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
6989   },
6990
6991   /* X86_64_VEX_0F385E */
6992   {
6993     { Bad_Opcode },
6994     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
6995   },
6996 };
6997
6998 static const struct dis386 three_byte_table[][256] = {
6999
7000   /* THREE_BYTE_0F38 */
7001   {
7002     /* 00 */
7003     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7004     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7005     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7006     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7007     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7008     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7009     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7010     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7011     /* 08 */
7012     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7013     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7014     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7015     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     /* 10 */
7021     { PREFIX_TABLE (PREFIX_0F3810) },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { PREFIX_TABLE (PREFIX_0F3814) },
7026     { PREFIX_TABLE (PREFIX_0F3815) },
7027     { Bad_Opcode },
7028     { PREFIX_TABLE (PREFIX_0F3817) },
7029     /* 18 */
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7035     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7036     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7037     { Bad_Opcode },
7038     /* 20 */
7039     { PREFIX_TABLE (PREFIX_0F3820) },
7040     { PREFIX_TABLE (PREFIX_0F3821) },
7041     { PREFIX_TABLE (PREFIX_0F3822) },
7042     { PREFIX_TABLE (PREFIX_0F3823) },
7043     { PREFIX_TABLE (PREFIX_0F3824) },
7044     { PREFIX_TABLE (PREFIX_0F3825) },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     /* 28 */
7048     { PREFIX_TABLE (PREFIX_0F3828) },
7049     { PREFIX_TABLE (PREFIX_0F3829) },
7050     { PREFIX_TABLE (PREFIX_0F382A) },
7051     { PREFIX_TABLE (PREFIX_0F382B) },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     /* 30 */
7057     { PREFIX_TABLE (PREFIX_0F3830) },
7058     { PREFIX_TABLE (PREFIX_0F3831) },
7059     { PREFIX_TABLE (PREFIX_0F3832) },
7060     { PREFIX_TABLE (PREFIX_0F3833) },
7061     { PREFIX_TABLE (PREFIX_0F3834) },
7062     { PREFIX_TABLE (PREFIX_0F3835) },
7063     { Bad_Opcode },
7064     { PREFIX_TABLE (PREFIX_0F3837) },
7065     /* 38 */
7066     { PREFIX_TABLE (PREFIX_0F3838) },
7067     { PREFIX_TABLE (PREFIX_0F3839) },
7068     { PREFIX_TABLE (PREFIX_0F383A) },
7069     { PREFIX_TABLE (PREFIX_0F383B) },
7070     { PREFIX_TABLE (PREFIX_0F383C) },
7071     { PREFIX_TABLE (PREFIX_0F383D) },
7072     { PREFIX_TABLE (PREFIX_0F383E) },
7073     { PREFIX_TABLE (PREFIX_0F383F) },
7074     /* 40 */
7075     { PREFIX_TABLE (PREFIX_0F3840) },
7076     { PREFIX_TABLE (PREFIX_0F3841) },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     /* 48 */
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     /* 50 */
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     /* 58 */
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     /* 60 */
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     /* 68 */
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     /* 70 */
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     /* 78 */
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     /* 80 */
7147     { PREFIX_TABLE (PREFIX_0F3880) },
7148     { PREFIX_TABLE (PREFIX_0F3881) },
7149     { PREFIX_TABLE (PREFIX_0F3882) },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     /* 88 */
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     /* 90 */
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     /* 98 */
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     /* a0 */
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     /* a8 */
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     /* b0 */
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     /* b8 */
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     /* c0 */
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     /* c8 */
7228     { PREFIX_TABLE (PREFIX_0F38C8) },
7229     { PREFIX_TABLE (PREFIX_0F38C9) },
7230     { PREFIX_TABLE (PREFIX_0F38CA) },
7231     { PREFIX_TABLE (PREFIX_0F38CB) },
7232     { PREFIX_TABLE (PREFIX_0F38CC) },
7233     { PREFIX_TABLE (PREFIX_0F38CD) },
7234     { Bad_Opcode },
7235     { PREFIX_TABLE (PREFIX_0F38CF) },
7236     /* d0 */
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     /* d8 */
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { PREFIX_TABLE (PREFIX_0F38DB) },
7250     { PREFIX_TABLE (PREFIX_0F38DC) },
7251     { PREFIX_TABLE (PREFIX_0F38DD) },
7252     { PREFIX_TABLE (PREFIX_0F38DE) },
7253     { PREFIX_TABLE (PREFIX_0F38DF) },
7254     /* e0 */
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     /* e8 */
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     /* f0 */
7273     { PREFIX_TABLE (PREFIX_0F38F0) },
7274     { PREFIX_TABLE (PREFIX_0F38F1) },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { PREFIX_TABLE (PREFIX_0F38F5) },
7279     { PREFIX_TABLE (PREFIX_0F38F6) },
7280     { Bad_Opcode },
7281     /* f8 */
7282     { PREFIX_TABLE (PREFIX_0F38F8) },
7283     { PREFIX_TABLE (PREFIX_0F38F9) },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290   },
7291   /* THREE_BYTE_0F3A */
7292   {
7293     /* 00 */
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     /* 08 */
7303     { PREFIX_TABLE (PREFIX_0F3A08) },
7304     { PREFIX_TABLE (PREFIX_0F3A09) },
7305     { PREFIX_TABLE (PREFIX_0F3A0A) },
7306     { PREFIX_TABLE (PREFIX_0F3A0B) },
7307     { PREFIX_TABLE (PREFIX_0F3A0C) },
7308     { PREFIX_TABLE (PREFIX_0F3A0D) },
7309     { PREFIX_TABLE (PREFIX_0F3A0E) },
7310     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7311     /* 10 */
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { PREFIX_TABLE (PREFIX_0F3A14) },
7317     { PREFIX_TABLE (PREFIX_0F3A15) },
7318     { PREFIX_TABLE (PREFIX_0F3A16) },
7319     { PREFIX_TABLE (PREFIX_0F3A17) },
7320     /* 18 */
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     /* 20 */
7330     { PREFIX_TABLE (PREFIX_0F3A20) },
7331     { PREFIX_TABLE (PREFIX_0F3A21) },
7332     { PREFIX_TABLE (PREFIX_0F3A22) },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     /* 28 */
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     /* 30 */
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     /* 38 */
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     /* 40 */
7366     { PREFIX_TABLE (PREFIX_0F3A40) },
7367     { PREFIX_TABLE (PREFIX_0F3A41) },
7368     { PREFIX_TABLE (PREFIX_0F3A42) },
7369     { Bad_Opcode },
7370     { PREFIX_TABLE (PREFIX_0F3A44) },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     /* 48 */
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     /* 50 */
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     /* 58 */
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     /* 60 */
7402     { PREFIX_TABLE (PREFIX_0F3A60) },
7403     { PREFIX_TABLE (PREFIX_0F3A61) },
7404     { PREFIX_TABLE (PREFIX_0F3A62) },
7405     { PREFIX_TABLE (PREFIX_0F3A63) },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     /* 68 */
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     /* 70 */
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     /* 78 */
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     /* 80 */
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     /* 88 */
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     /* 90 */
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     /* 98 */
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     /* a0 */
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     /* a8 */
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     /* b0 */
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     /* b8 */
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     /* c0 */
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     /* c8 */
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { PREFIX_TABLE (PREFIX_0F3ACC) },
7524     { Bad_Opcode },
7525     { PREFIX_TABLE (PREFIX_0F3ACE) },
7526     { PREFIX_TABLE (PREFIX_0F3ACF) },
7527     /* d0 */
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     /* d8 */
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { PREFIX_TABLE (PREFIX_0F3ADF) },
7545     /* e0 */
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     /* e8 */
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     /* f0 */
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     /* f8 */
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581   },
7582 };
7583
7584 static const struct dis386 xop_table[][256] = {
7585   /* XOP_08 */
7586   {
7587     /* 00 */
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     /* 08 */
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     /* 10 */
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     /* 18 */
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     /* 20 */
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     /* 28 */
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     /* 30 */
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     /* 38 */
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     /* 40 */
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     /* 48 */
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     /* 50 */
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     /* 58 */
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     /* 60 */
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     /* 68 */
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     /* 70 */
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     /* 78 */
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     /* 80 */
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
7738     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
7739     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
7740     /* 88 */
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
7748     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
7749     /* 90 */
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
7756     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
7757     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
7758     /* 98 */
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
7766     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
7767     /* a0 */
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
7771     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
7775     { Bad_Opcode },
7776     /* a8 */
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     /* b0 */
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
7793     { Bad_Opcode },
7794     /* b8 */
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     /* c0 */
7804     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
7805     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
7806     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
7807     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     /* c8 */
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7818     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7819     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7820     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7821     /* d0 */
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     /* d8 */
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     /* e0 */
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     /* e8 */
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7854     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7855     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7856     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7857     /* f0 */
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     /* f8 */
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875   },
7876   /* XOP_09 */
7877   {
7878     /* 00 */
7879     { Bad_Opcode },
7880     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
7881     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     /* 08 */
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     /* 10 */
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     /* 18 */
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     /* 20 */
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     /* 28 */
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     /* 30 */
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     /* 38 */
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     /* 40 */
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     /* 48 */
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     /* 50 */
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     /* 58 */
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     /* 60 */
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     /* 68 */
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     /* 70 */
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     /* 78 */
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     /* 80 */
8023     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
8024     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
8025     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
8026     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     /* 88 */
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     /* 90 */
8041     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
8042     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
8043     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
8044     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
8045     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
8046     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
8047     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
8048     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
8049     /* 98 */
8050     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
8051     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
8052     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
8053     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     /* a0 */
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     /* a8 */
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     /* b0 */
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     /* b8 */
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     /* c0 */
8095     { Bad_Opcode },
8096     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
8097     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
8098     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
8102     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
8103     /* c8 */
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     /* d0 */
8113     { Bad_Opcode },
8114     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
8115     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
8116     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
8120     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
8121     /* d8 */
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     /* e0 */
8131     { Bad_Opcode },
8132     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
8133     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
8134     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     /* e8 */
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     /* f0 */
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     /* f8 */
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166   },
8167   /* XOP_0A */
8168   {
8169     /* 00 */
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     /* 08 */
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     /* 10 */
8188     { "bextrS", { Gdq, Edq, Id }, 0 },
8189     { Bad_Opcode },
8190     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     /* 18 */
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     /* 20 */
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     /* 28 */
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     /* 30 */
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     /* 38 */
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     /* 40 */
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     /* 48 */
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     /* 50 */
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     /* 58 */
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     /* 60 */
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     /* 68 */
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     /* 70 */
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     /* 78 */
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     /* 80 */
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     /* 88 */
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     /* 90 */
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     /* 98 */
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     /* a0 */
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     /* a8 */
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     /* b0 */
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     /* b8 */
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     /* c0 */
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     /* c8 */
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     /* d0 */
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     /* d8 */
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     /* e0 */
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     /* e8 */
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     /* f0 */
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     /* f8 */
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457   },
8458 };
8459
8460 static const struct dis386 vex_table[][256] = {
8461   /* VEX_0F */
8462   {
8463     /* 00 */
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     /* 08 */
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     /* 10 */
8482     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8483     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8484     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8485     { MOD_TABLE (MOD_VEX_0F13) },
8486     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8487     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8488     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8489     { MOD_TABLE (MOD_VEX_0F17) },
8490     /* 18 */
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     /* 20 */
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     /* 28 */
8509     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8510     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8511     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8512     { MOD_TABLE (MOD_VEX_0F2B) },
8513     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8515     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8516     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8517     /* 30 */
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     /* 38 */
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     /* 40 */
8536     { Bad_Opcode },
8537     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8538     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8539     { Bad_Opcode },
8540     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8541     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8542     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8544     /* 48 */
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     /* 50 */
8554     { MOD_TABLE (MOD_VEX_0F50) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8558     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8559     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8560     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8561     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8562     /* 58 */
8563     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8564     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8565     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8566     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8567     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8568     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8569     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8570     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8571     /* 60 */
8572     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8573     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8574     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8577     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8578     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8579     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8580     /* 68 */
8581     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8582     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8583     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8584     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8585     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8586     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8587     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8588     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8589     /* 70 */
8590     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8591     { REG_TABLE (REG_VEX_0F71) },
8592     { REG_TABLE (REG_VEX_0F72) },
8593     { REG_TABLE (REG_VEX_0F73) },
8594     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8595     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8596     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8597     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8598     /* 78 */
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8604     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8605     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8606     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8607     /* 80 */
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     /* 88 */
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     /* 90 */
8626     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8627     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8628     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8629     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     /* 98 */
8635     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8636     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     /* a0 */
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     /* a8 */
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { REG_TABLE (REG_VEX_0FAE) },
8660     { Bad_Opcode },
8661     /* b0 */
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     /* b8 */
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     /* c0 */
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8683     { Bad_Opcode },
8684     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8686     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8687     { Bad_Opcode },
8688     /* c8 */
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     /* d0 */
8698     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8702     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8703     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8704     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8705     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8706     /* d8 */
8707     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8708     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8711     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8712     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8713     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8714     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8715     /* e0 */
8716     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8719     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8720     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8721     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8722     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8723     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8724     /* e8 */
8725     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8726     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8727     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8728     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8729     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8730     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8731     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8732     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8733     /* f0 */
8734     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8735     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8736     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8737     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8738     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8739     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8740     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8741     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8742     /* f8 */
8743     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8744     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8745     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8746     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8747     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8748     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8749     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8750     { Bad_Opcode },
8751   },
8752   /* VEX_0F38 */
8753   {
8754     /* 00 */
8755     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8763     /* 08 */
8764     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8772     /* 10 */
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8781     /* 18 */
8782     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8785     { Bad_Opcode },
8786     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8789     { Bad_Opcode },
8790     /* 20 */
8791     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     /* 28 */
8800     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8808     /* 30 */
8809     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8813     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8814     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8815     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8816     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8817     /* 38 */
8818     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8819     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8821     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8822     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8823     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8824     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8825     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8826     /* 40 */
8827     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8828     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8833     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8834     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8835     /* 48 */
8836     { Bad_Opcode },
8837     { X86_64_TABLE (X86_64_VEX_0F3849) },
8838     { Bad_Opcode },
8839     { X86_64_TABLE (X86_64_VEX_0F384B) },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     /* 50 */
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     /* 58 */
8854     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8855     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8856     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8857     { Bad_Opcode },
8858     { X86_64_TABLE (X86_64_VEX_0F385C) },
8859     { Bad_Opcode },
8860     { X86_64_TABLE (X86_64_VEX_0F385E) },
8861     { Bad_Opcode },
8862     /* 60 */
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     /* 68 */
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     /* 70 */
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     /* 78 */
8890     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     /* 80 */
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     /* 88 */
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8913     { Bad_Opcode },
8914     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8915     { Bad_Opcode },
8916     /* 90 */
8917     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8925     /* 98 */
8926     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8934     /* a0 */
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8943     /* a8 */
8944     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8952     /* b0 */
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8960     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8961     /* b8 */
8962     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8963     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8964     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8965     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8969     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8970     /* c0 */
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     /* c8 */
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8988     /* d0 */
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     /* d8 */
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9006     /* e0 */
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     /* e8 */
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     /* f0 */
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9028     { REG_TABLE (REG_VEX_0F38F3) },
9029     { Bad_Opcode },
9030     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9032     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9033     /* f8 */
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042   },
9043   /* VEX_0F3A */
9044   {
9045     /* 00 */
9046     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9049     { Bad_Opcode },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9051     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9053     { Bad_Opcode },
9054     /* 08 */
9055     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9061     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9062     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9063     /* 10 */
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9069     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9072     /* 18 */
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     /* 20 */
9082     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9083     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9084     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     /* 28 */
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     /* 30 */
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9103     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     /* 38 */
9109     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     /* 40 */
9118     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9119     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9121     { Bad_Opcode },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9123     { Bad_Opcode },
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9125     { Bad_Opcode },
9126     /* 48 */
9127     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9129     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     /* 50 */
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     /* 58 */
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9150     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9151     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9152     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9153     /* 60 */
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     /* 68 */
9163     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9164     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9165     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9166     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9167     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9168     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9169     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9170     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9171     /* 70 */
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     /* 78 */
9181     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9182     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9183     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9184     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9185     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9186     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9187     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9188     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9189     /* 80 */
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     /* 88 */
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     /* 90 */
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     /* 98 */
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     /* a0 */
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     /* a8 */
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     /* b0 */
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     /* b8 */
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     /* c0 */
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     /* c8 */
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9278     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9279     /* d0 */
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     /* d8 */
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9297     /* e0 */
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     /* e8 */
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     { Bad_Opcode },
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315     /* f0 */
9316     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     /* f8 */
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333   },
9334 };
9335
9336 #include "i386-dis-evex.h"
9337
9338 static const struct dis386 vex_len_table[][2] = {
9339   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9340   {
9341     { "vmovlpX",        { XM, Vex, EXq }, 0 },
9342   },
9343
9344   /* VEX_LEN_0F12_P_0_M_1 */
9345   {
9346     { "vmovhlps",       { XM, Vex, EXq }, 0 },
9347   },
9348
9349   /* VEX_LEN_0F13_M_0 */
9350   {
9351     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9352   },
9353
9354   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9355   {
9356     { "vmovhpX",        { XM, Vex, EXq }, 0 },
9357   },
9358
9359   /* VEX_LEN_0F16_P_0_M_1 */
9360   {
9361     { "vmovlhps",       { XM, Vex, EXq }, 0 },
9362   },
9363
9364   /* VEX_LEN_0F17_M_0 */
9365   {
9366     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9367   },
9368
9369   /* VEX_LEN_0F41_P_0 */
9370   {
9371     { Bad_Opcode },
9372     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9373   },
9374   /* VEX_LEN_0F41_P_2 */
9375   {
9376     { Bad_Opcode },
9377     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9378   },
9379   /* VEX_LEN_0F42_P_0 */
9380   {
9381     { Bad_Opcode },
9382     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9383   },
9384   /* VEX_LEN_0F42_P_2 */
9385   {
9386     { Bad_Opcode },
9387     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9388   },
9389   /* VEX_LEN_0F44_P_0 */
9390   {
9391     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9392   },
9393   /* VEX_LEN_0F44_P_2 */
9394   {
9395     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9396   },
9397   /* VEX_LEN_0F45_P_0 */
9398   {
9399     { Bad_Opcode },
9400     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9401   },
9402   /* VEX_LEN_0F45_P_2 */
9403   {
9404     { Bad_Opcode },
9405     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9406   },
9407   /* VEX_LEN_0F46_P_0 */
9408   {
9409     { Bad_Opcode },
9410     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9411   },
9412   /* VEX_LEN_0F46_P_2 */
9413   {
9414     { Bad_Opcode },
9415     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9416   },
9417   /* VEX_LEN_0F47_P_0 */
9418   {
9419     { Bad_Opcode },
9420     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9421   },
9422   /* VEX_LEN_0F47_P_2 */
9423   {
9424     { Bad_Opcode },
9425     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9426   },
9427   /* VEX_LEN_0F4A_P_0 */
9428   {
9429     { Bad_Opcode },
9430     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9431   },
9432   /* VEX_LEN_0F4A_P_2 */
9433   {
9434     { Bad_Opcode },
9435     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9436   },
9437   /* VEX_LEN_0F4B_P_0 */
9438   {
9439     { Bad_Opcode },
9440     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9441   },
9442   /* VEX_LEN_0F4B_P_2 */
9443   {
9444     { Bad_Opcode },
9445     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9446   },
9447
9448   /* VEX_LEN_0F6E_P_2 */
9449   {
9450     { "vmovK",          { XMScalar, Edq }, 0 },
9451   },
9452
9453   /* VEX_LEN_0F77_P_1 */
9454   {
9455     { "vzeroupper",     { XX }, 0 },
9456     { "vzeroall",       { XX }, 0 },
9457   },
9458
9459   /* VEX_LEN_0F7E_P_1 */
9460   {
9461     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
9462   },
9463
9464   /* VEX_LEN_0F7E_P_2 */
9465   {
9466     { "vmovK",          { Edq, XMScalar }, 0 },
9467   },
9468
9469   /* VEX_LEN_0F90_P_0 */
9470   {
9471     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9472   },
9473
9474   /* VEX_LEN_0F90_P_2 */
9475   {
9476     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9477   },
9478
9479   /* VEX_LEN_0F91_P_0 */
9480   {
9481     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9482   },
9483
9484   /* VEX_LEN_0F91_P_2 */
9485   {
9486     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9487   },
9488
9489   /* VEX_LEN_0F92_P_0 */
9490   {
9491     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9492   },
9493
9494   /* VEX_LEN_0F92_P_2 */
9495   {
9496     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9497   },
9498
9499   /* VEX_LEN_0F92_P_3 */
9500   {
9501     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9502   },
9503
9504   /* VEX_LEN_0F93_P_0 */
9505   {
9506     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9507   },
9508
9509   /* VEX_LEN_0F93_P_2 */
9510   {
9511     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9512   },
9513
9514   /* VEX_LEN_0F93_P_3 */
9515   {
9516     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9517   },
9518
9519   /* VEX_LEN_0F98_P_0 */
9520   {
9521     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9522   },
9523
9524   /* VEX_LEN_0F98_P_2 */
9525   {
9526     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9527   },
9528
9529   /* VEX_LEN_0F99_P_0 */
9530   {
9531     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9532   },
9533
9534   /* VEX_LEN_0F99_P_2 */
9535   {
9536     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9537   },
9538
9539   /* VEX_LEN_0FAE_R_2_M_0 */
9540   {
9541     { "vldmxcsr",       { Md }, 0 },
9542   },
9543
9544   /* VEX_LEN_0FAE_R_3_M_0 */
9545   {
9546     { "vstmxcsr",       { Md }, 0 },
9547   },
9548
9549   /* VEX_LEN_0FC4_P_2 */
9550   {
9551     { "vpinsrw",        { XM, Vex, Edqw, Ib }, 0 },
9552   },
9553
9554   /* VEX_LEN_0FC5_P_2 */
9555   {
9556     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9557   },
9558
9559   /* VEX_LEN_0FD6_P_2 */
9560   {
9561     { "vmovq",          { EXqVexScalarS, XMScalar }, 0 },
9562   },
9563
9564   /* VEX_LEN_0FF7_P_2 */
9565   {
9566     { "vmaskmovdqu",    { XM, XS }, 0 },
9567   },
9568
9569   /* VEX_LEN_0F3816_P_2 */
9570   {
9571     { Bad_Opcode },
9572     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9573   },
9574
9575   /* VEX_LEN_0F3819_P_2 */
9576   {
9577     { Bad_Opcode },
9578     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9579   },
9580
9581   /* VEX_LEN_0F381A_P_2_M_0 */
9582   {
9583     { Bad_Opcode },
9584     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0_L_0) },
9585   },
9586
9587   /* VEX_LEN_0F3836_P_2 */
9588   {
9589     { Bad_Opcode },
9590     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9591   },
9592
9593   /* VEX_LEN_0F3841_P_2 */
9594   {
9595     { "vphminposuw",    { XM, EXx }, 0 },
9596   },
9597
9598    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
9599   {
9600     { "ldtilecfg", { M }, 0 },
9601   },
9602
9603   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
9604   {
9605     { "tilerelease", { Skip_MODRM }, 0 },
9606   },
9607
9608   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
9609   {
9610     { "sttilecfg", { M }, 0 },
9611   },
9612
9613   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
9614   {
9615     { "tilezero", { TMM, Skip_MODRM }, 0 },
9616   },
9617
9618   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
9619   {
9620     { "tilestored", { MVexSIBMEM, TMM }, 0 },
9621   },
9622   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
9623   {
9624     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
9625   },
9626
9627   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
9628   {
9629     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
9630   },
9631
9632   /* VEX_LEN_0F385A_P_2_M_0 */
9633   {
9634     { Bad_Opcode },
9635     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0_L_0) },
9636   },
9637
9638   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
9639   {
9640     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
9641   },
9642
9643   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
9644   {
9645     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
9646   },
9647
9648   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
9649   {
9650     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
9651   },
9652
9653   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
9654   {
9655     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
9656   },
9657
9658   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
9659   {
9660     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
9661   },
9662
9663   /* VEX_LEN_0F38DB_P_2 */
9664   {
9665     { "vaesimc",        { XM, EXx }, 0 },
9666   },
9667
9668   /* VEX_LEN_0F38F2_P_0 */
9669   {
9670     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9671   },
9672
9673   /* VEX_LEN_0F38F3_R_1_P_0 */
9674   {
9675     { "blsrS",          { VexGdq, Edq }, 0 },
9676   },
9677
9678   /* VEX_LEN_0F38F3_R_2_P_0 */
9679   {
9680     { "blsmskS",        { VexGdq, Edq }, 0 },
9681   },
9682
9683   /* VEX_LEN_0F38F3_R_3_P_0 */
9684   {
9685     { "blsiS",          { VexGdq, Edq }, 0 },
9686   },
9687
9688   /* VEX_LEN_0F38F5_P_0 */
9689   {
9690     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9691   },
9692
9693   /* VEX_LEN_0F38F5_P_1 */
9694   {
9695     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9696   },
9697
9698   /* VEX_LEN_0F38F5_P_3 */
9699   {
9700     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9701   },
9702
9703   /* VEX_LEN_0F38F6_P_3 */
9704   {
9705     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9706   },
9707
9708   /* VEX_LEN_0F38F7_P_0 */
9709   {
9710     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9711   },
9712
9713   /* VEX_LEN_0F38F7_P_1 */
9714   {
9715     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9716   },
9717
9718   /* VEX_LEN_0F38F7_P_2 */
9719   {
9720     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9721   },
9722
9723   /* VEX_LEN_0F38F7_P_3 */
9724   {
9725     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9726   },
9727
9728   /* VEX_LEN_0F3A00_P_2 */
9729   {
9730     { Bad_Opcode },
9731     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9732   },
9733
9734   /* VEX_LEN_0F3A01_P_2 */
9735   {
9736     { Bad_Opcode },
9737     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9738   },
9739
9740   /* VEX_LEN_0F3A06_P_2 */
9741   {
9742     { Bad_Opcode },
9743     { VEX_W_TABLE (VEX_W_0F3A06_P_2_L_0) },
9744   },
9745
9746   /* VEX_LEN_0F3A14_P_2 */
9747   {
9748     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9749   },
9750
9751   /* VEX_LEN_0F3A15_P_2 */
9752   {
9753     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9754   },
9755
9756   /* VEX_LEN_0F3A16_P_2  */
9757   {
9758     { "vpextrK",        { Edq, XM, Ib }, 0 },
9759   },
9760
9761   /* VEX_LEN_0F3A17_P_2 */
9762   {
9763     { "vextractps",     { Edqd, XM, Ib }, 0 },
9764   },
9765
9766   /* VEX_LEN_0F3A18_P_2 */
9767   {
9768     { Bad_Opcode },
9769     { VEX_W_TABLE (VEX_W_0F3A18_P_2_L_0) },
9770   },
9771
9772   /* VEX_LEN_0F3A19_P_2 */
9773   {
9774     { Bad_Opcode },
9775     { VEX_W_TABLE (VEX_W_0F3A19_P_2_L_0) },
9776   },
9777
9778   /* VEX_LEN_0F3A20_P_2 */
9779   {
9780     { "vpinsrb",        { XM, Vex, Edqb, Ib }, 0 },
9781   },
9782
9783   /* VEX_LEN_0F3A21_P_2 */
9784   {
9785     { "vinsertps",      { XM, Vex, EXd, Ib }, 0 },
9786   },
9787
9788   /* VEX_LEN_0F3A22_P_2 */
9789   {
9790     { "vpinsrK",        { XM, Vex, Edq, Ib }, 0 },
9791   },
9792
9793   /* VEX_LEN_0F3A30_P_2 */
9794   {
9795     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9796   },
9797
9798   /* VEX_LEN_0F3A31_P_2 */
9799   {
9800     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9801   },
9802
9803   /* VEX_LEN_0F3A32_P_2 */
9804   {
9805     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9806   },
9807
9808   /* VEX_LEN_0F3A33_P_2 */
9809   {
9810     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9811   },
9812
9813   /* VEX_LEN_0F3A38_P_2 */
9814   {
9815     { Bad_Opcode },
9816     { VEX_W_TABLE (VEX_W_0F3A38_P_2_L_0) },
9817   },
9818
9819   /* VEX_LEN_0F3A39_P_2 */
9820   {
9821     { Bad_Opcode },
9822     { VEX_W_TABLE (VEX_W_0F3A39_P_2_L_0) },
9823   },
9824
9825   /* VEX_LEN_0F3A41_P_2 */
9826   {
9827     { "vdppd",          { XM, Vex, EXx, Ib }, 0 },
9828   },
9829
9830   /* VEX_LEN_0F3A46_P_2 */
9831   {
9832     { Bad_Opcode },
9833     { VEX_W_TABLE (VEX_W_0F3A46_P_2_L_0) },
9834   },
9835
9836   /* VEX_LEN_0F3A60_P_2 */
9837   {
9838     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, 0 },
9839   },
9840
9841   /* VEX_LEN_0F3A61_P_2 */
9842   {
9843     { "vpcmpestri!%LQ", { XM, EXx, Ib }, 0 },
9844   },
9845
9846   /* VEX_LEN_0F3A62_P_2 */
9847   {
9848     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9849   },
9850
9851   /* VEX_LEN_0F3A63_P_2 */
9852   {
9853     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9854   },
9855
9856   /* VEX_LEN_0F3ADF_P_2 */
9857   {
9858     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9859   },
9860
9861   /* VEX_LEN_0F3AF0_P_3 */
9862   {
9863     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9864   },
9865
9866   /* VEX_LEN_0FXOP_08_85 */
9867   {
9868     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
9869   },
9870
9871   /* VEX_LEN_0FXOP_08_86 */
9872   {
9873     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
9874   },
9875
9876   /* VEX_LEN_0FXOP_08_87 */
9877   {
9878     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
9879   },
9880
9881   /* VEX_LEN_0FXOP_08_8E */
9882   {
9883     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
9884   },
9885
9886   /* VEX_LEN_0FXOP_08_8F */
9887   {
9888     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
9889   },
9890
9891   /* VEX_LEN_0FXOP_08_95 */
9892   {
9893     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
9894   },
9895
9896   /* VEX_LEN_0FXOP_08_96 */
9897   {
9898     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
9899   },
9900
9901   /* VEX_LEN_0FXOP_08_97 */
9902   {
9903     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
9904   },
9905
9906   /* VEX_LEN_0FXOP_08_9E */
9907   {
9908     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
9909   },
9910
9911   /* VEX_LEN_0FXOP_08_9F */
9912   {
9913     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
9914   },
9915
9916   /* VEX_LEN_0FXOP_08_A3 */
9917   {
9918     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
9919   },
9920
9921   /* VEX_LEN_0FXOP_08_A6 */
9922   {
9923     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
9924   },
9925
9926   /* VEX_LEN_0FXOP_08_B6 */
9927   {
9928     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
9929   },
9930
9931   /* VEX_LEN_0FXOP_08_C0 */
9932   {
9933     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
9934   },
9935
9936   /* VEX_LEN_0FXOP_08_C1 */
9937   {
9938     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
9939   },
9940
9941   /* VEX_LEN_0FXOP_08_C2 */
9942   {
9943     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
9944   },
9945
9946   /* VEX_LEN_0FXOP_08_C3 */
9947   {
9948     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
9949   },
9950
9951   /* VEX_LEN_0FXOP_08_CC */
9952   {
9953     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
9954   },
9955
9956   /* VEX_LEN_0FXOP_08_CD */
9957   {
9958     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
9959   },
9960
9961   /* VEX_LEN_0FXOP_08_CE */
9962   {
9963     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
9964   },
9965
9966   /* VEX_LEN_0FXOP_08_CF */
9967   {
9968     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
9969   },
9970
9971   /* VEX_LEN_0FXOP_08_EC */
9972   {
9973     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
9974   },
9975
9976   /* VEX_LEN_0FXOP_08_ED */
9977   {
9978     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
9979   },
9980
9981   /* VEX_LEN_0FXOP_08_EE */
9982   {
9983     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
9984   },
9985
9986   /* VEX_LEN_0FXOP_08_EF */
9987   {
9988     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
9989   },
9990
9991   /* VEX_LEN_0FXOP_09_01 */
9992   {
9993     { REG_TABLE (REG_0FXOP_09_01_L_0) },
9994   },
9995
9996   /* VEX_LEN_0FXOP_09_02 */
9997   {
9998     { REG_TABLE (REG_0FXOP_09_02_L_0) },
9999   },
10000
10001   /* VEX_LEN_0FXOP_09_12_M_1 */
10002   {
10003     { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
10004   },
10005
10006   /* VEX_LEN_0FXOP_09_82_W_0 */
10007   {
10008     { "vfrczss",        { XM, EXd }, 0 },
10009   },
10010
10011   /* VEX_LEN_0FXOP_09_83_W_0 */
10012   {
10013     { "vfrczsd",        { XM, EXq }, 0 },
10014   },
10015
10016   /* VEX_LEN_0FXOP_09_90 */
10017   {
10018     { "vprotb",         { XM, EXx, VexW }, 0 },
10019   },
10020
10021   /* VEX_LEN_0FXOP_09_91 */
10022   {
10023     { "vprotw",         { XM, EXx, VexW }, 0 },
10024   },
10025
10026   /* VEX_LEN_0FXOP_09_92 */
10027   {
10028     { "vprotd",         { XM, EXx, VexW }, 0 },
10029   },
10030
10031   /* VEX_LEN_0FXOP_09_93 */
10032   {
10033     { "vprotq",         { XM, EXx, VexW }, 0 },
10034   },
10035
10036   /* VEX_LEN_0FXOP_09_94 */
10037   {
10038     { "vpshlb",         { XM, EXx, VexW }, 0 },
10039   },
10040
10041   /* VEX_LEN_0FXOP_09_95 */
10042   {
10043     { "vpshlw",         { XM, EXx, VexW }, 0 },
10044   },
10045
10046   /* VEX_LEN_0FXOP_09_96 */
10047   {
10048     { "vpshld",         { XM, EXx, VexW }, 0 },
10049   },
10050
10051   /* VEX_LEN_0FXOP_09_97 */
10052   {
10053     { "vpshlq",         { XM, EXx, VexW }, 0 },
10054   },
10055
10056   /* VEX_LEN_0FXOP_09_98 */
10057   {
10058     { "vpshab",         { XM, EXx, VexW }, 0 },
10059   },
10060
10061   /* VEX_LEN_0FXOP_09_99 */
10062   {
10063     { "vpshaw",         { XM, EXx, VexW }, 0 },
10064   },
10065
10066   /* VEX_LEN_0FXOP_09_9A */
10067   {
10068     { "vpshad",         { XM, EXx, VexW }, 0 },
10069   },
10070
10071   /* VEX_LEN_0FXOP_09_9B */
10072   {
10073     { "vpshaq",         { XM, EXx, VexW }, 0 },
10074   },
10075
10076   /* VEX_LEN_0FXOP_09_C1 */
10077   {
10078     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
10079   },
10080
10081   /* VEX_LEN_0FXOP_09_C2 */
10082   {
10083     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
10084   },
10085
10086   /* VEX_LEN_0FXOP_09_C3 */
10087   {
10088     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
10089   },
10090
10091   /* VEX_LEN_0FXOP_09_C6 */
10092   {
10093     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
10094   },
10095
10096   /* VEX_LEN_0FXOP_09_C7 */
10097   {
10098     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
10099   },
10100
10101   /* VEX_LEN_0FXOP_09_CB */
10102   {
10103     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
10104   },
10105
10106   /* VEX_LEN_0FXOP_09_D1 */
10107   {
10108     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
10109   },
10110
10111   /* VEX_LEN_0FXOP_09_D2 */
10112   {
10113     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
10114   },
10115
10116   /* VEX_LEN_0FXOP_09_D3 */
10117   {
10118     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
10119   },
10120
10121   /* VEX_LEN_0FXOP_09_D6 */
10122   {
10123     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
10124   },
10125
10126   /* VEX_LEN_0FXOP_09_D7 */
10127   {
10128     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
10129   },
10130
10131   /* VEX_LEN_0FXOP_09_DB */
10132   {
10133     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
10134   },
10135
10136   /* VEX_LEN_0FXOP_09_E1 */
10137   {
10138     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
10139   },
10140
10141   /* VEX_LEN_0FXOP_09_E2 */
10142   {
10143     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
10144   },
10145
10146   /* VEX_LEN_0FXOP_09_E3 */
10147   {
10148     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
10149   },
10150
10151   /* VEX_LEN_0FXOP_0A_12 */
10152   {
10153     { REG_TABLE (REG_0FXOP_0A_12_L_0) },
10154   },
10155 };
10156
10157 #include "i386-dis-evex-len.h"
10158
10159 static const struct dis386 vex_w_table[][2] = {
10160   {
10161     /* VEX_W_0F41_P_0_LEN_1 */
10162     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10163     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10164   },
10165   {
10166     /* VEX_W_0F41_P_2_LEN_1 */
10167     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10168     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10169   },
10170   {
10171     /* VEX_W_0F42_P_0_LEN_1 */
10172     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10173     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10174   },
10175   {
10176     /* VEX_W_0F42_P_2_LEN_1 */
10177     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10178     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10179   },
10180   {
10181     /* VEX_W_0F44_P_0_LEN_0 */
10182     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10183     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10184   },
10185   {
10186     /* VEX_W_0F44_P_2_LEN_0 */
10187     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10188     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10189   },
10190   {
10191     /* VEX_W_0F45_P_0_LEN_1 */
10192     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10193     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10194   },
10195   {
10196     /* VEX_W_0F45_P_2_LEN_1 */
10197     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10198     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10199   },
10200   {
10201     /* VEX_W_0F46_P_0_LEN_1 */
10202     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10203     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10204   },
10205   {
10206     /* VEX_W_0F46_P_2_LEN_1 */
10207     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10208     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10209   },
10210   {
10211     /* VEX_W_0F47_P_0_LEN_1 */
10212     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10213     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10214   },
10215   {
10216     /* VEX_W_0F47_P_2_LEN_1 */
10217     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10218     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10219   },
10220   {
10221     /* VEX_W_0F4A_P_0_LEN_1 */
10222     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10223     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10224   },
10225   {
10226     /* VEX_W_0F4A_P_2_LEN_1 */
10227     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10228     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10229   },
10230   {
10231     /* VEX_W_0F4B_P_0_LEN_1 */
10232     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10233     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10234   },
10235   {
10236     /* VEX_W_0F4B_P_2_LEN_1 */
10237     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10238   },
10239   {
10240     /* VEX_W_0F90_P_0_LEN_0 */
10241     { "kmovw",          { MaskG, MaskE }, 0 },
10242     { "kmovq",          { MaskG, MaskE }, 0 },
10243   },
10244   {
10245     /* VEX_W_0F90_P_2_LEN_0 */
10246     { "kmovb",          { MaskG, MaskBDE }, 0 },
10247     { "kmovd",          { MaskG, MaskBDE }, 0 },
10248   },
10249   {
10250     /* VEX_W_0F91_P_0_LEN_0 */
10251     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10252     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10253   },
10254   {
10255     /* VEX_W_0F91_P_2_LEN_0 */
10256     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10257     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10258   },
10259   {
10260     /* VEX_W_0F92_P_0_LEN_0 */
10261     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10262   },
10263   {
10264     /* VEX_W_0F92_P_2_LEN_0 */
10265     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10266   },
10267   {
10268     /* VEX_W_0F93_P_0_LEN_0 */
10269     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10270   },
10271   {
10272     /* VEX_W_0F93_P_2_LEN_0 */
10273     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10274   },
10275   {
10276     /* VEX_W_0F98_P_0_LEN_0 */
10277     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10278     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10279   },
10280   {
10281     /* VEX_W_0F98_P_2_LEN_0 */
10282     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10283     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10284   },
10285   {
10286     /* VEX_W_0F99_P_0_LEN_0 */
10287     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10288     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10289   },
10290   {
10291     /* VEX_W_0F99_P_2_LEN_0 */
10292     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10293     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10294   },
10295   {
10296     /* VEX_W_0F380C_P_2  */
10297     { "vpermilps",      { XM, Vex, EXx }, 0 },
10298   },
10299   {
10300     /* VEX_W_0F380D_P_2  */
10301     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10302   },
10303   {
10304     /* VEX_W_0F380E_P_2  */
10305     { "vtestps",        { XM, EXx }, 0 },
10306   },
10307   {
10308     /* VEX_W_0F380F_P_2  */
10309     { "vtestpd",        { XM, EXx }, 0 },
10310   },
10311   {
10312     /* VEX_W_0F3813_P_2 */
10313     { "vcvtph2ps", { XM, EXxmmq }, 0 },
10314   },
10315   {
10316     /* VEX_W_0F3816_P_2  */
10317     { "vpermps",        { XM, Vex, EXx }, 0 },
10318   },
10319   {
10320     /* VEX_W_0F3818_P_2 */
10321     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10322   },
10323   {
10324     /* VEX_W_0F3819_P_2 */
10325     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10326   },
10327   {
10328     /* VEX_W_0F381A_P_2_M_0_L_0 */
10329     { "vbroadcastf128", { XM, Mxmm }, 0 },
10330   },
10331   {
10332     /* VEX_W_0F382C_P_2_M_0 */
10333     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10334   },
10335   {
10336     /* VEX_W_0F382D_P_2_M_0 */
10337     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10338   },
10339   {
10340     /* VEX_W_0F382E_P_2_M_0 */
10341     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10342   },
10343   {
10344     /* VEX_W_0F382F_P_2_M_0 */
10345     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10346   },
10347   {
10348     /* VEX_W_0F3836_P_2  */
10349     { "vpermd",         { XM, Vex, EXx }, 0 },
10350   },
10351   {
10352     /* VEX_W_0F3846_P_2 */
10353     { "vpsravd",        { XM, Vex, EXx }, 0 },
10354   },
10355   {
10356     /* VEX_W_0F3849_X86_64_P_0 */
10357     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
10358   },
10359   {
10360     /* VEX_W_0F3849_X86_64_P_2 */
10361     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
10362   },
10363   {
10364     /* VEX_W_0F3849_X86_64_P_3 */
10365     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
10366   },
10367   {
10368     /* VEX_W_0F384B_X86_64_P_1 */
10369     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
10370   },
10371   {
10372     /* VEX_W_0F384B_X86_64_P_2 */
10373     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
10374   },
10375   {
10376     /* VEX_W_0F384B_X86_64_P_3 */
10377     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
10378   },
10379   {
10380     /* VEX_W_0F3858_P_2 */
10381     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10382   },
10383   {
10384     /* VEX_W_0F3859_P_2 */
10385     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10386   },
10387   {
10388     /* VEX_W_0F385A_P_2_M_0_L_0 */
10389     { "vbroadcasti128", { XM, Mxmm }, 0 },
10390   },
10391   {
10392     /* VEX_W_0F385C_X86_64_P_1 */
10393     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
10394   },
10395   {
10396     /* VEX_W_0F385E_X86_64_P_0 */
10397     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
10398   },
10399   {
10400     /* VEX_W_0F385E_X86_64_P_1 */
10401     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
10402   },
10403   {
10404     /* VEX_W_0F385E_X86_64_P_2 */
10405     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
10406   },
10407   {
10408     /* VEX_W_0F385E_X86_64_P_3 */
10409     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
10410   },
10411   {
10412     /* VEX_W_0F3878_P_2 */
10413     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10414   },
10415   {
10416     /* VEX_W_0F3879_P_2 */
10417     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10418   },
10419   {
10420     /* VEX_W_0F38CF_P_2 */
10421     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10422   },
10423   {
10424     /* VEX_W_0F3A00_P_2 */
10425     { Bad_Opcode },
10426     { "vpermq",         { XM, EXx, Ib }, 0 },
10427   },
10428   {
10429     /* VEX_W_0F3A01_P_2 */
10430     { Bad_Opcode },
10431     { "vpermpd",        { XM, EXx, Ib }, 0 },
10432   },
10433   {
10434     /* VEX_W_0F3A02_P_2 */
10435     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10436   },
10437   {
10438     /* VEX_W_0F3A04_P_2 */
10439     { "vpermilps",      { XM, EXx, Ib }, 0 },
10440   },
10441   {
10442     /* VEX_W_0F3A05_P_2 */
10443     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10444   },
10445   {
10446     /* VEX_W_0F3A06_P_2_L_0 */
10447     { "vperm2f128",     { XM, Vex, EXx, Ib }, 0 },
10448   },
10449   {
10450     /* VEX_W_0F3A18_P_2_L_0 */
10451     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, 0 },
10452   },
10453   {
10454     /* VEX_W_0F3A19_P_2_L_0 */
10455     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10456   },
10457   {
10458     /* VEX_W_0F3A1D_P_2 */
10459     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 },
10460   },
10461   {
10462     /* VEX_W_0F3A30_P_2_LEN_0 */
10463     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10464     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10465   },
10466   {
10467     /* VEX_W_0F3A31_P_2_LEN_0 */
10468     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10469     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10470   },
10471   {
10472     /* VEX_W_0F3A32_P_2_LEN_0 */
10473     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10474     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10475   },
10476   {
10477     /* VEX_W_0F3A33_P_2_LEN_0 */
10478     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10479     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10480   },
10481   {
10482     /* VEX_W_0F3A38_P_2_L_0 */
10483     { "vinserti128",    { XM, Vex, EXxmm, Ib }, 0 },
10484   },
10485   {
10486     /* VEX_W_0F3A39_P_2_L_0 */
10487     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10488   },
10489   {
10490     /* VEX_W_0F3A46_P_2_L_0 */
10491     { "vperm2i128",     { XM, Vex, EXx, Ib }, 0 },
10492   },
10493   {
10494     /* VEX_W_0F3A4A_P_2 */
10495     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10496   },
10497   {
10498     /* VEX_W_0F3A4B_P_2 */
10499     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10500   },
10501   {
10502     /* VEX_W_0F3A4C_P_2 */
10503     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10504   },
10505   {
10506     /* VEX_W_0F3ACE_P_2 */
10507     { Bad_Opcode },
10508     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10509   },
10510   {
10511     /* VEX_W_0F3ACF_P_2 */
10512     { Bad_Opcode },
10513     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10514   },
10515   /* VEX_W_0FXOP_08_85_L_0 */
10516   {
10517     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
10518   },
10519   /* VEX_W_0FXOP_08_86_L_0 */
10520   {
10521     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10522   },
10523   /* VEX_W_0FXOP_08_87_L_0 */
10524   {
10525     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
10526   },
10527   /* VEX_W_0FXOP_08_8E_L_0 */
10528   {
10529     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10530   },
10531   /* VEX_W_0FXOP_08_8F_L_0 */
10532   {
10533     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
10534   },
10535   /* VEX_W_0FXOP_08_95_L_0 */
10536   {
10537     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
10538   },
10539   /* VEX_W_0FXOP_08_96_L_0 */
10540   {
10541     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
10542   },
10543   /* VEX_W_0FXOP_08_97_L_0 */
10544   {
10545     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
10546   },
10547   /* VEX_W_0FXOP_08_9E_L_0 */
10548   {
10549     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
10550   },
10551   /* VEX_W_0FXOP_08_9F_L_0 */
10552   {
10553     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
10554   },
10555   /* VEX_W_0FXOP_08_A6_L_0 */
10556   {
10557     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
10558   },
10559   /* VEX_W_0FXOP_08_B6_L_0 */
10560   {
10561     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10562   },
10563   /* VEX_W_0FXOP_08_C0_L_0 */
10564   {
10565     { "vprotb",         { XM, EXx, Ib }, 0 },
10566   },
10567   /* VEX_W_0FXOP_08_C1_L_0 */
10568   {
10569     { "vprotw",         { XM, EXx, Ib }, 0 },
10570   },
10571   /* VEX_W_0FXOP_08_C2_L_0 */
10572   {
10573     { "vprotd",         { XM, EXx, Ib }, 0 },
10574   },
10575   /* VEX_W_0FXOP_08_C3_L_0 */
10576   {
10577     { "vprotq",         { XM, EXx, Ib }, 0 },
10578   },
10579   /* VEX_W_0FXOP_08_CC_L_0 */
10580   {
10581      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
10582   },
10583   /* VEX_W_0FXOP_08_CD_L_0 */
10584   {
10585      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
10586   },
10587   /* VEX_W_0FXOP_08_CE_L_0 */
10588   {
10589      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
10590   },
10591   /* VEX_W_0FXOP_08_CF_L_0 */
10592   {
10593      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
10594   },
10595   /* VEX_W_0FXOP_08_EC_L_0 */
10596   {
10597      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
10598   },
10599   /* VEX_W_0FXOP_08_ED_L_0 */
10600   {
10601      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
10602   },
10603   /* VEX_W_0FXOP_08_EE_L_0 */
10604   {
10605      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
10606   },
10607   /* VEX_W_0FXOP_08_EF_L_0 */
10608   {
10609      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
10610   },
10611   /* VEX_W_0FXOP_09_80 */
10612   {
10613     { "vfrczps",        { XM, EXx }, 0 },
10614   },
10615   /* VEX_W_0FXOP_09_81 */
10616   {
10617     { "vfrczpd",        { XM, EXx }, 0 },
10618   },
10619   /* VEX_W_0FXOP_09_82 */
10620   {
10621     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
10622   },
10623   /* VEX_W_0FXOP_09_83 */
10624   {
10625     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
10626   },
10627   /* VEX_W_0FXOP_09_C1_L_0 */
10628   {
10629     { "vphaddbw",       { XM, EXxmm }, 0 },
10630   },
10631   /* VEX_W_0FXOP_09_C2_L_0 */
10632   {
10633     { "vphaddbd",       { XM, EXxmm }, 0 },
10634   },
10635   /* VEX_W_0FXOP_09_C3_L_0 */
10636   {
10637     { "vphaddbq",       { XM, EXxmm }, 0 },
10638   },
10639   /* VEX_W_0FXOP_09_C6_L_0 */
10640   {
10641     { "vphaddwd",       { XM, EXxmm }, 0 },
10642   },
10643   /* VEX_W_0FXOP_09_C7_L_0 */
10644   {
10645     { "vphaddwq",       { XM, EXxmm }, 0 },
10646   },
10647   /* VEX_W_0FXOP_09_CB_L_0 */
10648   {
10649     { "vphadddq",       { XM, EXxmm }, 0 },
10650   },
10651   /* VEX_W_0FXOP_09_D1_L_0 */
10652   {
10653     { "vphaddubw",      { XM, EXxmm }, 0 },
10654   },
10655   /* VEX_W_0FXOP_09_D2_L_0 */
10656   {
10657     { "vphaddubd",      { XM, EXxmm }, 0 },
10658   },
10659   /* VEX_W_0FXOP_09_D3_L_0 */
10660   {
10661     { "vphaddubq",      { XM, EXxmm }, 0 },
10662   },
10663   /* VEX_W_0FXOP_09_D6_L_0 */
10664   {
10665     { "vphadduwd",      { XM, EXxmm }, 0 },
10666   },
10667   /* VEX_W_0FXOP_09_D7_L_0 */
10668   {
10669     { "vphadduwq",      { XM, EXxmm }, 0 },
10670   },
10671   /* VEX_W_0FXOP_09_DB_L_0 */
10672   {
10673     { "vphaddudq",      { XM, EXxmm }, 0 },
10674   },
10675   /* VEX_W_0FXOP_09_E1_L_0 */
10676   {
10677     { "vphsubbw",       { XM, EXxmm }, 0 },
10678   },
10679   /* VEX_W_0FXOP_09_E2_L_0 */
10680   {
10681     { "vphsubwd",       { XM, EXxmm }, 0 },
10682   },
10683   /* VEX_W_0FXOP_09_E3_L_0 */
10684   {
10685     { "vphsubdq",       { XM, EXxmm }, 0 },
10686   },
10687
10688 #include "i386-dis-evex-w.h"
10689 };
10690
10691 static const struct dis386 mod_table[][2] = {
10692   {
10693     /* MOD_8D */
10694     { "leaS",           { Gv, M }, 0 },
10695   },
10696   {
10697     /* MOD_C6_REG_7 */
10698     { Bad_Opcode },
10699     { RM_TABLE (RM_C6_REG_7) },
10700   },
10701   {
10702     /* MOD_C7_REG_7 */
10703     { Bad_Opcode },
10704     { RM_TABLE (RM_C7_REG_7) },
10705   },
10706   {
10707     /* MOD_FF_REG_3 */
10708     { "{l|}call^", { indirEp }, 0 },
10709   },
10710   {
10711     /* MOD_FF_REG_5 */
10712     { "{l|}jmp^", { indirEp }, 0 },
10713   },
10714   {
10715     /* MOD_0F01_REG_0 */
10716     { X86_64_TABLE (X86_64_0F01_REG_0) },
10717     { RM_TABLE (RM_0F01_REG_0) },
10718   },
10719   {
10720     /* MOD_0F01_REG_1 */
10721     { X86_64_TABLE (X86_64_0F01_REG_1) },
10722     { RM_TABLE (RM_0F01_REG_1) },
10723   },
10724   {
10725     /* MOD_0F01_REG_2 */
10726     { X86_64_TABLE (X86_64_0F01_REG_2) },
10727     { RM_TABLE (RM_0F01_REG_2) },
10728   },
10729   {
10730     /* MOD_0F01_REG_3 */
10731     { X86_64_TABLE (X86_64_0F01_REG_3) },
10732     { RM_TABLE (RM_0F01_REG_3) },
10733   },
10734   {
10735     /* MOD_0F01_REG_5 */
10736     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10737     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10738   },
10739   {
10740     /* MOD_0F01_REG_7 */
10741     { "invlpg",         { Mb }, 0 },
10742     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10743   },
10744   {
10745     /* MOD_0F12_PREFIX_0 */
10746     { "movlpX",         { XM, EXq }, 0 },
10747     { "movhlps",        { XM, EXq }, 0 },
10748   },
10749   {
10750     /* MOD_0F12_PREFIX_2 */
10751     { "movlpX", { XM, EXq }, 0 },
10752   },
10753   {
10754     /* MOD_0F13 */
10755     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10756   },
10757   {
10758     /* MOD_0F16_PREFIX_0 */
10759     { "movhpX",         { XM, EXq }, 0 },
10760     { "movlhps",        { XM, EXq }, 0 },
10761   },
10762   {
10763     /* MOD_0F16_PREFIX_2 */
10764     { "movhpX", { XM, EXq }, 0 },
10765   },
10766   {
10767     /* MOD_0F17 */
10768     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10769   },
10770   {
10771     /* MOD_0F18_REG_0 */
10772     { "prefetchnta",    { Mb }, 0 },
10773   },
10774   {
10775     /* MOD_0F18_REG_1 */
10776     { "prefetcht0",     { Mb }, 0 },
10777   },
10778   {
10779     /* MOD_0F18_REG_2 */
10780     { "prefetcht1",     { Mb }, 0 },
10781   },
10782   {
10783     /* MOD_0F18_REG_3 */
10784     { "prefetcht2",     { Mb }, 0 },
10785   },
10786   {
10787     /* MOD_0F18_REG_4 */
10788     { "nop/reserved",   { Mb }, 0 },
10789   },
10790   {
10791     /* MOD_0F18_REG_5 */
10792     { "nop/reserved",   { Mb }, 0 },
10793   },
10794   {
10795     /* MOD_0F18_REG_6 */
10796     { "nop/reserved",   { Mb }, 0 },
10797   },
10798   {
10799     /* MOD_0F18_REG_7 */
10800     { "nop/reserved",   { Mb }, 0 },
10801   },
10802   {
10803     /* MOD_0F1A_PREFIX_0 */
10804     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10805     { "nopQ",           { Ev }, 0 },
10806   },
10807   {
10808     /* MOD_0F1B_PREFIX_0 */
10809     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10810     { "nopQ",           { Ev }, 0 },
10811   },
10812   {
10813     /* MOD_0F1B_PREFIX_1 */
10814     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10815     { "nopQ",           { Ev }, 0 },
10816   },
10817   {
10818     /* MOD_0F1C_PREFIX_0 */
10819     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10820     { "nopQ",           { Ev }, 0 },
10821   },
10822   {
10823     /* MOD_0F1E_PREFIX_1 */
10824     { "nopQ",           { Ev }, 0 },
10825     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10826   },
10827   {
10828     /* MOD_0F24 */
10829     { Bad_Opcode },
10830     { "movL",           { Rd, Td }, 0 },
10831   },
10832   {
10833     /* MOD_0F26 */
10834     { Bad_Opcode },
10835     { "movL",           { Td, Rd }, 0 },
10836   },
10837   {
10838     /* MOD_0F2B_PREFIX_0 */
10839     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10840   },
10841   {
10842     /* MOD_0F2B_PREFIX_1 */
10843     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10844   },
10845   {
10846     /* MOD_0F2B_PREFIX_2 */
10847     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10848   },
10849   {
10850     /* MOD_0F2B_PREFIX_3 */
10851     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10852   },
10853   {
10854     /* MOD_0F50 */
10855     { Bad_Opcode },
10856     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10857   },
10858   {
10859     /* MOD_0F71_REG_2 */
10860     { Bad_Opcode },
10861     { "psrlw",          { MS, Ib }, 0 },
10862   },
10863   {
10864     /* MOD_0F71_REG_4 */
10865     { Bad_Opcode },
10866     { "psraw",          { MS, Ib }, 0 },
10867   },
10868   {
10869     /* MOD_0F71_REG_6 */
10870     { Bad_Opcode },
10871     { "psllw",          { MS, Ib }, 0 },
10872   },
10873   {
10874     /* MOD_0F72_REG_2 */
10875     { Bad_Opcode },
10876     { "psrld",          { MS, Ib }, 0 },
10877   },
10878   {
10879     /* MOD_0F72_REG_4 */
10880     { Bad_Opcode },
10881     { "psrad",          { MS, Ib }, 0 },
10882   },
10883   {
10884     /* MOD_0F72_REG_6 */
10885     { Bad_Opcode },
10886     { "pslld",          { MS, Ib }, 0 },
10887   },
10888   {
10889     /* MOD_0F73_REG_2 */
10890     { Bad_Opcode },
10891     { "psrlq",          { MS, Ib }, 0 },
10892   },
10893   {
10894     /* MOD_0F73_REG_3 */
10895     { Bad_Opcode },
10896     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10897   },
10898   {
10899     /* MOD_0F73_REG_6 */
10900     { Bad_Opcode },
10901     { "psllq",          { MS, Ib }, 0 },
10902   },
10903   {
10904     /* MOD_0F73_REG_7 */
10905     { Bad_Opcode },
10906     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10907   },
10908   {
10909     /* MOD_0FAE_REG_0 */
10910     { "fxsave",         { FXSAVE }, 0 },
10911     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10912   },
10913   {
10914     /* MOD_0FAE_REG_1 */
10915     { "fxrstor",        { FXSAVE }, 0 },
10916     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10917   },
10918   {
10919     /* MOD_0FAE_REG_2 */
10920     { "ldmxcsr",        { Md }, 0 },
10921     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10922   },
10923   {
10924     /* MOD_0FAE_REG_3 */
10925     { "stmxcsr",        { Md }, 0 },
10926     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10927   },
10928   {
10929     /* MOD_0FAE_REG_4 */
10930     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10931     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10932   },
10933   {
10934     /* MOD_0FAE_REG_5 */
10935     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10936     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10937   },
10938   {
10939     /* MOD_0FAE_REG_6 */
10940     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10941     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10942   },
10943   {
10944     /* MOD_0FAE_REG_7 */
10945     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10946     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10947   },
10948   {
10949     /* MOD_0FB2 */
10950     { "lssS",           { Gv, Mp }, 0 },
10951   },
10952   {
10953     /* MOD_0FB4 */
10954     { "lfsS",           { Gv, Mp }, 0 },
10955   },
10956   {
10957     /* MOD_0FB5 */
10958     { "lgsS",           { Gv, Mp }, 0 },
10959   },
10960   {
10961     /* MOD_0FC3 */
10962     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10963   },
10964   {
10965     /* MOD_0FC7_REG_3 */
10966     { "xrstors",        { FXSAVE }, 0 },
10967   },
10968   {
10969     /* MOD_0FC7_REG_4 */
10970     { "xsavec",         { FXSAVE }, 0 },
10971   },
10972   {
10973     /* MOD_0FC7_REG_5 */
10974     { "xsaves",         { FXSAVE }, 0 },
10975   },
10976   {
10977     /* MOD_0FC7_REG_6 */
10978     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10979     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10980   },
10981   {
10982     /* MOD_0FC7_REG_7 */
10983     { "vmptrst",        { Mq }, 0 },
10984     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10985   },
10986   {
10987     /* MOD_0FD7 */
10988     { Bad_Opcode },
10989     { "pmovmskb",       { Gdq, MS }, 0 },
10990   },
10991   {
10992     /* MOD_0FE7_PREFIX_2 */
10993     { "movntdq",        { Mx, XM }, 0 },
10994   },
10995   {
10996     /* MOD_0FF0_PREFIX_3 */
10997     { "lddqu",          { XM, M }, 0 },
10998   },
10999   {
11000     /* MOD_0F382A_PREFIX_2 */
11001     { "movntdqa",       { XM, Mx }, 0 },
11002   },
11003   {
11004     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
11005     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
11006     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
11007   },
11008   {
11009     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
11010     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
11011   },
11012   {
11013     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
11014     { Bad_Opcode },
11015     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
11016   },
11017   {
11018     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
11019     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
11020   },
11021   {
11022     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
11023     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
11024   },
11025   {
11026     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
11027     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
11028   },
11029   {
11030     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
11031     { Bad_Opcode },
11032     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
11033   },
11034   {
11035     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
11036     { Bad_Opcode },
11037     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
11038   },
11039   {
11040     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
11041     { Bad_Opcode },
11042     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
11043   },
11044   {
11045     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
11046     { Bad_Opcode },
11047     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
11048   },
11049   {
11050     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
11051     { Bad_Opcode },
11052     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
11053   },
11054   {
11055     /* MOD_0F38F5_PREFIX_2 */
11056     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11057   },
11058   {
11059     /* MOD_0F38F6_PREFIX_0 */
11060     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11061   },
11062   {
11063     /* MOD_0F38F8_PREFIX_1 */
11064     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
11065   },
11066   {
11067     /* MOD_0F38F8_PREFIX_2 */
11068     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
11069   },
11070   {
11071     /* MOD_0F38F8_PREFIX_3 */
11072     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
11073   },
11074   {
11075     /* MOD_0F38F9_PREFIX_0 */
11076     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
11077   },
11078   {
11079     /* MOD_62_32BIT */
11080     { "bound{S|}",      { Gv, Ma }, 0 },
11081     { EVEX_TABLE (EVEX_0F) },
11082   },
11083   {
11084     /* MOD_C4_32BIT */
11085     { "lesS",           { Gv, Mp }, 0 },
11086     { VEX_C4_TABLE (VEX_0F) },
11087   },
11088   {
11089     /* MOD_C5_32BIT */
11090     { "ldsS",           { Gv, Mp }, 0 },
11091     { VEX_C5_TABLE (VEX_0F) },
11092   },
11093   {
11094     /* MOD_VEX_0F12_PREFIX_0 */
11095     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11096     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11097   },
11098   {
11099     /* MOD_VEX_0F12_PREFIX_2 */
11100     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
11101   },
11102   {
11103     /* MOD_VEX_0F13 */
11104     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11105   },
11106   {
11107     /* MOD_VEX_0F16_PREFIX_0 */
11108     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11109     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11110   },
11111   {
11112     /* MOD_VEX_0F16_PREFIX_2 */
11113     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
11114   },
11115   {
11116     /* MOD_VEX_0F17 */
11117     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11118   },
11119   {
11120     /* MOD_VEX_0F2B */
11121     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
11122   },
11123   {
11124     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11125     { Bad_Opcode },
11126     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11127   },
11128   {
11129     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11130     { Bad_Opcode },
11131     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11132   },
11133   {
11134     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11135     { Bad_Opcode },
11136     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11137   },
11138   {
11139     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11140     { Bad_Opcode },
11141     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11142   },
11143   {
11144     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11145     { Bad_Opcode },
11146     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11147   },
11148   {
11149     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11150     { Bad_Opcode },
11151     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11152   },
11153   {
11154     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11155     { Bad_Opcode },
11156     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11157   },
11158   {
11159     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11160     { Bad_Opcode },
11161     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11162   },
11163   {
11164     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11165     { Bad_Opcode },
11166     { "knotw",          { MaskG, MaskR }, 0 },
11167   },
11168   {
11169     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11170     { Bad_Opcode },
11171     { "knotq",          { MaskG, MaskR }, 0 },
11172   },
11173   {
11174     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11175     { Bad_Opcode },
11176     { "knotb",          { MaskG, MaskR }, 0 },
11177   },
11178   {
11179     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11180     { Bad_Opcode },
11181     { "knotd",          { MaskG, MaskR }, 0 },
11182   },
11183   {
11184     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11185     { Bad_Opcode },
11186     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11187   },
11188   {
11189     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11190     { Bad_Opcode },
11191     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11192   },
11193   {
11194     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11195     { Bad_Opcode },
11196     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11197   },
11198   {
11199     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11200     { Bad_Opcode },
11201     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11202   },
11203  {
11204     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11205     { Bad_Opcode },
11206     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11207   },
11208   {
11209     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11210     { Bad_Opcode },
11211     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11212   },
11213   {
11214     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11215     { Bad_Opcode },
11216     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11217   },
11218   {
11219     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11220     { Bad_Opcode },
11221     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11222   },
11223   {
11224     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11225     { Bad_Opcode },
11226     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11227   },
11228   {
11229     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11230     { Bad_Opcode },
11231     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11232   },
11233   {
11234     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11235     { Bad_Opcode },
11236     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11237   },
11238   {
11239     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11240     { Bad_Opcode },
11241     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11242   },
11243   {
11244     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11245     { Bad_Opcode },
11246     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11247   },
11248   {
11249     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11250     { Bad_Opcode },
11251     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11252   },
11253   {
11254     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11255     { Bad_Opcode },
11256     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11257   },
11258   {
11259     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11260     { Bad_Opcode },
11261     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11262   },
11263   {
11264     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11265     { Bad_Opcode },
11266     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11267   },
11268   {
11269     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11270     { Bad_Opcode },
11271     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11272   },
11273   {
11274     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11275     { Bad_Opcode },
11276     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11277   },
11278   {
11279     /* MOD_VEX_0F50 */
11280     { Bad_Opcode },
11281     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
11282   },
11283   {
11284     /* MOD_VEX_0F71_REG_2 */
11285     { Bad_Opcode },
11286     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11287   },
11288   {
11289     /* MOD_VEX_0F71_REG_4 */
11290     { Bad_Opcode },
11291     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11292   },
11293   {
11294     /* MOD_VEX_0F71_REG_6 */
11295     { Bad_Opcode },
11296     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11297   },
11298   {
11299     /* MOD_VEX_0F72_REG_2 */
11300     { Bad_Opcode },
11301     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11302   },
11303   {
11304     /* MOD_VEX_0F72_REG_4 */
11305     { Bad_Opcode },
11306     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11307   },
11308   {
11309     /* MOD_VEX_0F72_REG_6 */
11310     { Bad_Opcode },
11311     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11312   },
11313   {
11314     /* MOD_VEX_0F73_REG_2 */
11315     { Bad_Opcode },
11316     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11317   },
11318   {
11319     /* MOD_VEX_0F73_REG_3 */
11320     { Bad_Opcode },
11321     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11322   },
11323   {
11324     /* MOD_VEX_0F73_REG_6 */
11325     { Bad_Opcode },
11326     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11327   },
11328   {
11329     /* MOD_VEX_0F73_REG_7 */
11330     { Bad_Opcode },
11331     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11332   },
11333   {
11334     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11335     { "kmovw",          { Ew, MaskG }, 0 },
11336     { Bad_Opcode },
11337   },
11338   {
11339     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11340     { "kmovq",          { Eq, MaskG }, 0 },
11341     { Bad_Opcode },
11342   },
11343   {
11344     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11345     { "kmovb",          { Eb, MaskG }, 0 },
11346     { Bad_Opcode },
11347   },
11348   {
11349     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11350     { "kmovd",          { Ed, MaskG }, 0 },
11351     { Bad_Opcode },
11352   },
11353   {
11354     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
11355     { Bad_Opcode },
11356     { "kmovw",          { MaskG, Rdq }, 0 },
11357   },
11358   {
11359     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
11360     { Bad_Opcode },
11361     { "kmovb",          { MaskG, Rdq }, 0 },
11362   },
11363   {
11364     /* MOD_VEX_0F92_P_3_LEN_0 */
11365     { Bad_Opcode },
11366     { "kmovK",          { MaskG, Rdq }, 0 },
11367   },
11368   {
11369     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
11370     { Bad_Opcode },
11371     { "kmovw",          { Gdq, MaskR }, 0 },
11372   },
11373   {
11374     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
11375     { Bad_Opcode },
11376     { "kmovb",          { Gdq, MaskR }, 0 },
11377   },
11378   {
11379     /* MOD_VEX_0F93_P_3_LEN_0 */
11380     { Bad_Opcode },
11381     { "kmovK",          { Gdq, MaskR }, 0 },
11382   },
11383   {
11384     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
11385     { Bad_Opcode },
11386     { "kortestw", { MaskG, MaskR }, 0 },
11387   },
11388   {
11389     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
11390     { Bad_Opcode },
11391     { "kortestq", { MaskG, MaskR }, 0 },
11392   },
11393   {
11394     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
11395     { Bad_Opcode },
11396     { "kortestb", { MaskG, MaskR }, 0 },
11397   },
11398   {
11399     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
11400     { Bad_Opcode },
11401     { "kortestd", { MaskG, MaskR }, 0 },
11402   },
11403   {
11404     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
11405     { Bad_Opcode },
11406     { "ktestw", { MaskG, MaskR }, 0 },
11407   },
11408   {
11409     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
11410     { Bad_Opcode },
11411     { "ktestq", { MaskG, MaskR }, 0 },
11412   },
11413   {
11414     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
11415     { Bad_Opcode },
11416     { "ktestb", { MaskG, MaskR }, 0 },
11417   },
11418   {
11419     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
11420     { Bad_Opcode },
11421     { "ktestd", { MaskG, MaskR }, 0 },
11422   },
11423   {
11424     /* MOD_VEX_0FAE_REG_2 */
11425     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11426   },
11427   {
11428     /* MOD_VEX_0FAE_REG_3 */
11429     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11430   },
11431   {
11432     /* MOD_VEX_0FD7_PREFIX_2 */
11433     { Bad_Opcode },
11434     { "vpmovmskb",      { Gdq, XS }, 0 },
11435   },
11436   {
11437     /* MOD_VEX_0FE7_PREFIX_2 */
11438     { "vmovntdq",       { Mx, XM }, 0 },
11439   },
11440   {
11441     /* MOD_VEX_0FF0_PREFIX_3 */
11442     { "vlddqu",         { XM, M }, 0 },
11443   },
11444   {
11445     /* MOD_VEX_0F381A_PREFIX_2 */
11446     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11447   },
11448   {
11449     /* MOD_VEX_0F382A_PREFIX_2 */
11450     { "vmovntdqa",      { XM, Mx }, 0 },
11451   },
11452   {
11453     /* MOD_VEX_0F382C_PREFIX_2 */
11454     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11455   },
11456   {
11457     /* MOD_VEX_0F382D_PREFIX_2 */
11458     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11459   },
11460   {
11461     /* MOD_VEX_0F382E_PREFIX_2 */
11462     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11463   },
11464   {
11465     /* MOD_VEX_0F382F_PREFIX_2 */
11466     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11467   },
11468   {
11469     /* MOD_VEX_0F385A_PREFIX_2 */
11470     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11471   },
11472   {
11473     /* MOD_VEX_0F388C_PREFIX_2 */
11474     { "vpmaskmov%DQ",   { XM, Vex, Mx }, 0 },
11475   },
11476   {
11477     /* MOD_VEX_0F388E_PREFIX_2 */
11478     { "vpmaskmov%DQ",   { Mx, Vex, XM }, 0 },
11479   },
11480   {
11481     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
11482     { Bad_Opcode },
11483     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
11484   },
11485   {
11486     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
11487     { Bad_Opcode },
11488     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
11489   },
11490   {
11491     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
11492     { Bad_Opcode },
11493     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
11494   },
11495   {
11496     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
11497     { Bad_Opcode },
11498     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
11499   },
11500   {
11501     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
11502     { Bad_Opcode },
11503     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
11504   },
11505   {
11506     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
11507     { Bad_Opcode },
11508     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
11509   },
11510   {
11511     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
11512     { Bad_Opcode },
11513     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
11514   },
11515   {
11516     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
11517     { Bad_Opcode },
11518     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
11519   },
11520   {
11521     /* MOD_VEX_0FXOP_09_12 */
11522     { Bad_Opcode },
11523     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
11524   },
11525
11526 #include "i386-dis-evex-mod.h"
11527 };
11528
11529 static const struct dis386 rm_table[][8] = {
11530   {
11531     /* RM_C6_REG_7 */
11532     { "xabort",         { Skip_MODRM, Ib }, 0 },
11533   },
11534   {
11535     /* RM_C7_REG_7 */
11536     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
11537   },
11538   {
11539     /* RM_0F01_REG_0 */
11540     { "enclv",          { Skip_MODRM }, 0 },
11541     { "vmcall",         { Skip_MODRM }, 0 },
11542     { "vmlaunch",       { Skip_MODRM }, 0 },
11543     { "vmresume",       { Skip_MODRM }, 0 },
11544     { "vmxoff",         { Skip_MODRM }, 0 },
11545     { "pconfig",        { Skip_MODRM }, 0 },
11546   },
11547   {
11548     /* RM_0F01_REG_1 */
11549     { "monitor",        { { OP_Monitor, 0 } }, 0 },
11550     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11551     { "clac",           { Skip_MODRM }, 0 },
11552     { "stac",           { Skip_MODRM }, 0 },
11553     { Bad_Opcode },
11554     { Bad_Opcode },
11555     { Bad_Opcode },
11556     { "encls",          { Skip_MODRM }, 0 },
11557   },
11558   {
11559     /* RM_0F01_REG_2 */
11560     { "xgetbv",         { Skip_MODRM }, 0 },
11561     { "xsetbv",         { Skip_MODRM }, 0 },
11562     { Bad_Opcode },
11563     { Bad_Opcode },
11564     { "vmfunc",         { Skip_MODRM }, 0 },
11565     { "xend",           { Skip_MODRM }, 0 },
11566     { "xtest",          { Skip_MODRM }, 0 },
11567     { "enclu",          { Skip_MODRM }, 0 },
11568   },
11569   {
11570     /* RM_0F01_REG_3 */
11571     { "vmrun",          { Skip_MODRM }, 0 },
11572     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
11573     { "vmload",         { Skip_MODRM }, 0 },
11574     { "vmsave",         { Skip_MODRM }, 0 },
11575     { "stgi",           { Skip_MODRM }, 0 },
11576     { "clgi",           { Skip_MODRM }, 0 },
11577     { "skinit",         { Skip_MODRM }, 0 },
11578     { "invlpga",        { Skip_MODRM }, 0 },
11579   },
11580   {
11581     /* RM_0F01_REG_5_MOD_3 */
11582     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11583     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
11584     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11585     { Bad_Opcode },
11586     { Bad_Opcode },
11587     { Bad_Opcode },
11588     { "rdpkru",         { Skip_MODRM }, 0 },
11589     { "wrpkru",         { Skip_MODRM }, 0 },
11590   },
11591   {
11592     /* RM_0F01_REG_7_MOD_3 */
11593     { "swapgs",         { Skip_MODRM }, 0  },
11594     { "rdtscp",         { Skip_MODRM }, 0  },
11595     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11596     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11597     { "clzero",         { Skip_MODRM }, 0  },
11598     { "rdpru",          { Skip_MODRM }, 0  },
11599   },
11600   {
11601     /* RM_0F1E_P_1_MOD_3_REG_7 */
11602     { "nopQ",           { Ev }, 0 },
11603     { "nopQ",           { Ev }, 0 },
11604     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11605     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11606     { "nopQ",           { Ev }, 0 },
11607     { "nopQ",           { Ev }, 0 },
11608     { "nopQ",           { Ev }, 0 },
11609     { "nopQ",           { Ev }, 0 },
11610   },
11611   {
11612     /* RM_0FAE_REG_6_MOD_3 */
11613     { "mfence",         { Skip_MODRM }, 0 },
11614   },
11615   {
11616     /* RM_0FAE_REG_7_MOD_3 */
11617     { "sfence",         { Skip_MODRM }, 0 },
11618
11619   },
11620   {
11621     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
11622     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
11623   },
11624 };
11625
11626 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11627
11628 /* We use the high bit to indicate different name for the same
11629    prefix.  */
11630 #define REP_PREFIX      (0xf3 | 0x100)
11631 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11632 #define XRELEASE_PREFIX (0xf3 | 0x400)
11633 #define BND_PREFIX      (0xf2 | 0x400)
11634 #define NOTRACK_PREFIX  (0x3e | 0x100)
11635
11636 /* Remember if the current op is a jump instruction.  */
11637 static bfd_boolean op_is_jump = FALSE;
11638
11639 static int
11640 ckprefix (void)
11641 {
11642   int newrex, i, length;
11643   rex = 0;
11644   prefixes = 0;
11645   used_prefixes = 0;
11646   rex_used = 0;
11647   last_lock_prefix = -1;
11648   last_repz_prefix = -1;
11649   last_repnz_prefix = -1;
11650   last_data_prefix = -1;
11651   last_addr_prefix = -1;
11652   last_rex_prefix = -1;
11653   last_seg_prefix = -1;
11654   fwait_prefix = -1;
11655   active_seg_prefix = 0;
11656   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11657     all_prefixes[i] = 0;
11658   i = 0;
11659   length = 0;
11660   /* The maximum instruction length is 15bytes.  */
11661   while (length < MAX_CODE_LENGTH - 1)
11662     {
11663       FETCH_DATA (the_info, codep + 1);
11664       newrex = 0;
11665       switch (*codep)
11666         {
11667         /* REX prefixes family.  */
11668         case 0x40:
11669         case 0x41:
11670         case 0x42:
11671         case 0x43:
11672         case 0x44:
11673         case 0x45:
11674         case 0x46:
11675         case 0x47:
11676         case 0x48:
11677         case 0x49:
11678         case 0x4a:
11679         case 0x4b:
11680         case 0x4c:
11681         case 0x4d:
11682         case 0x4e:
11683         case 0x4f:
11684           if (address_mode == mode_64bit)
11685             newrex = *codep;
11686           else
11687             return 1;
11688           last_rex_prefix = i;
11689           break;
11690         case 0xf3:
11691           prefixes |= PREFIX_REPZ;
11692           last_repz_prefix = i;
11693           break;
11694         case 0xf2:
11695           prefixes |= PREFIX_REPNZ;
11696           last_repnz_prefix = i;
11697           break;
11698         case 0xf0:
11699           prefixes |= PREFIX_LOCK;
11700           last_lock_prefix = i;
11701           break;
11702         case 0x2e:
11703           prefixes |= PREFIX_CS;
11704           last_seg_prefix = i;
11705           active_seg_prefix = PREFIX_CS;
11706           break;
11707         case 0x36:
11708           prefixes |= PREFIX_SS;
11709           last_seg_prefix = i;
11710           active_seg_prefix = PREFIX_SS;
11711           break;
11712         case 0x3e:
11713           prefixes |= PREFIX_DS;
11714           last_seg_prefix = i;
11715           active_seg_prefix = PREFIX_DS;
11716           break;
11717         case 0x26:
11718           prefixes |= PREFIX_ES;
11719           last_seg_prefix = i;
11720           active_seg_prefix = PREFIX_ES;
11721           break;
11722         case 0x64:
11723           prefixes |= PREFIX_FS;
11724           last_seg_prefix = i;
11725           active_seg_prefix = PREFIX_FS;
11726           break;
11727         case 0x65:
11728           prefixes |= PREFIX_GS;
11729           last_seg_prefix = i;
11730           active_seg_prefix = PREFIX_GS;
11731           break;
11732         case 0x66:
11733           prefixes |= PREFIX_DATA;
11734           last_data_prefix = i;
11735           break;
11736         case 0x67:
11737           prefixes |= PREFIX_ADDR;
11738           last_addr_prefix = i;
11739           break;
11740         case FWAIT_OPCODE:
11741           /* fwait is really an instruction.  If there are prefixes
11742              before the fwait, they belong to the fwait, *not* to the
11743              following instruction.  */
11744           fwait_prefix = i;
11745           if (prefixes || rex)
11746             {
11747               prefixes |= PREFIX_FWAIT;
11748               codep++;
11749               /* This ensures that the previous REX prefixes are noticed
11750                  as unused prefixes, as in the return case below.  */
11751               rex_used = rex;
11752               return 1;
11753             }
11754           prefixes = PREFIX_FWAIT;
11755           break;
11756         default:
11757           return 1;
11758         }
11759       /* Rex is ignored when followed by another prefix.  */
11760       if (rex)
11761         {
11762           rex_used = rex;
11763           return 1;
11764         }
11765       if (*codep != FWAIT_OPCODE)
11766         all_prefixes[i++] = *codep;
11767       rex = newrex;
11768       codep++;
11769       length++;
11770     }
11771   return 0;
11772 }
11773
11774 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11775    prefix byte.  */
11776
11777 static const char *
11778 prefix_name (int pref, int sizeflag)
11779 {
11780   static const char *rexes [16] =
11781     {
11782       "rex",            /* 0x40 */
11783       "rex.B",          /* 0x41 */
11784       "rex.X",          /* 0x42 */
11785       "rex.XB",         /* 0x43 */
11786       "rex.R",          /* 0x44 */
11787       "rex.RB",         /* 0x45 */
11788       "rex.RX",         /* 0x46 */
11789       "rex.RXB",        /* 0x47 */
11790       "rex.W",          /* 0x48 */
11791       "rex.WB",         /* 0x49 */
11792       "rex.WX",         /* 0x4a */
11793       "rex.WXB",        /* 0x4b */
11794       "rex.WR",         /* 0x4c */
11795       "rex.WRB",        /* 0x4d */
11796       "rex.WRX",        /* 0x4e */
11797       "rex.WRXB",       /* 0x4f */
11798     };
11799
11800   switch (pref)
11801     {
11802     /* REX prefixes family.  */
11803     case 0x40:
11804     case 0x41:
11805     case 0x42:
11806     case 0x43:
11807     case 0x44:
11808     case 0x45:
11809     case 0x46:
11810     case 0x47:
11811     case 0x48:
11812     case 0x49:
11813     case 0x4a:
11814     case 0x4b:
11815     case 0x4c:
11816     case 0x4d:
11817     case 0x4e:
11818     case 0x4f:
11819       return rexes [pref - 0x40];
11820     case 0xf3:
11821       return "repz";
11822     case 0xf2:
11823       return "repnz";
11824     case 0xf0:
11825       return "lock";
11826     case 0x2e:
11827       return "cs";
11828     case 0x36:
11829       return "ss";
11830     case 0x3e:
11831       return "ds";
11832     case 0x26:
11833       return "es";
11834     case 0x64:
11835       return "fs";
11836     case 0x65:
11837       return "gs";
11838     case 0x66:
11839       return (sizeflag & DFLAG) ? "data16" : "data32";
11840     case 0x67:
11841       if (address_mode == mode_64bit)
11842         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11843       else
11844         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11845     case FWAIT_OPCODE:
11846       return "fwait";
11847     case REP_PREFIX:
11848       return "rep";
11849     case XACQUIRE_PREFIX:
11850       return "xacquire";
11851     case XRELEASE_PREFIX:
11852       return "xrelease";
11853     case BND_PREFIX:
11854       return "bnd";
11855     case NOTRACK_PREFIX:
11856       return "notrack";
11857     default:
11858       return NULL;
11859     }
11860 }
11861
11862 static char op_out[MAX_OPERANDS][100];
11863 static int op_ad, op_index[MAX_OPERANDS];
11864 static int two_source_ops;
11865 static bfd_vma op_address[MAX_OPERANDS];
11866 static bfd_vma op_riprel[MAX_OPERANDS];
11867 static bfd_vma start_pc;
11868
11869 /*
11870  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11871  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11872  *   section of the "Virtual 8086 Mode" chapter.)
11873  * 'pc' should be the address of this instruction, it will
11874  *   be used to print the target address if this is a relative jump or call
11875  * The function returns the length of this instruction in bytes.
11876  */
11877
11878 static char intel_syntax;
11879 static char intel_mnemonic = !SYSV386_COMPAT;
11880 static char open_char;
11881 static char close_char;
11882 static char separator_char;
11883 static char scale_char;
11884
11885 enum x86_64_isa
11886 {
11887   amd64 = 1,
11888   intel64
11889 };
11890
11891 static enum x86_64_isa isa64;
11892
11893 /* Here for backwards compatibility.  When gdb stops using
11894    print_insn_i386_att and print_insn_i386_intel these functions can
11895    disappear, and print_insn_i386 be merged into print_insn.  */
11896 int
11897 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11898 {
11899   intel_syntax = 0;
11900
11901   return print_insn (pc, info);
11902 }
11903
11904 int
11905 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11906 {
11907   intel_syntax = 1;
11908
11909   return print_insn (pc, info);
11910 }
11911
11912 int
11913 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11914 {
11915   intel_syntax = -1;
11916
11917   return print_insn (pc, info);
11918 }
11919
11920 void
11921 print_i386_disassembler_options (FILE *stream)
11922 {
11923   fprintf (stream, _("\n\
11924 The following i386/x86-64 specific disassembler options are supported for use\n\
11925 with the -M switch (multiple options should be separated by commas):\n"));
11926
11927   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11928   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11929   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11930   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11931   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11932   fprintf (stream, _("  att-mnemonic\n"
11933                      "              Display instruction in AT&T mnemonic\n"));
11934   fprintf (stream, _("  intel-mnemonic\n"
11935                      "              Display instruction in Intel mnemonic\n"));
11936   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11937   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11938   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11939   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11940   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11941   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11942   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11943   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11944 }
11945
11946 /* Bad opcode.  */
11947 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11948
11949 /* Get a pointer to struct dis386 with a valid name.  */
11950
11951 static const struct dis386 *
11952 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11953 {
11954   int vindex, vex_table_index;
11955
11956   if (dp->name != NULL)
11957     return dp;
11958
11959   switch (dp->op[0].bytemode)
11960     {
11961     case USE_REG_TABLE:
11962       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11963       break;
11964
11965     case USE_MOD_TABLE:
11966       vindex = modrm.mod == 0x3 ? 1 : 0;
11967       dp = &mod_table[dp->op[1].bytemode][vindex];
11968       break;
11969
11970     case USE_RM_TABLE:
11971       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11972       break;
11973
11974     case USE_PREFIX_TABLE:
11975       if (need_vex)
11976         {
11977           /* The prefix in VEX is implicit.  */
11978           switch (vex.prefix)
11979             {
11980             case 0:
11981               vindex = 0;
11982               break;
11983             case REPE_PREFIX_OPCODE:
11984               vindex = 1;
11985               break;
11986             case DATA_PREFIX_OPCODE:
11987               vindex = 2;
11988               break;
11989             case REPNE_PREFIX_OPCODE:
11990               vindex = 3;
11991               break;
11992             default:
11993               abort ();
11994               break;
11995             }
11996         }
11997       else
11998         {
11999           int last_prefix = -1;
12000           int prefix = 0;
12001           vindex = 0;
12002           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12003              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12004              last one wins.  */
12005           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12006             {
12007               if (last_repz_prefix > last_repnz_prefix)
12008                 {
12009                   vindex = 1;
12010                   prefix = PREFIX_REPZ;
12011                   last_prefix = last_repz_prefix;
12012                 }
12013               else
12014                 {
12015                   vindex = 3;
12016                   prefix = PREFIX_REPNZ;
12017                   last_prefix = last_repnz_prefix;
12018                 }
12019
12020               /* Check if prefix should be ignored.  */
12021               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12022                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12023                    & prefix) != 0)
12024                 vindex = 0;
12025             }
12026
12027           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12028             {
12029               vindex = 2;
12030               prefix = PREFIX_DATA;
12031               last_prefix = last_data_prefix;
12032             }
12033
12034           if (vindex != 0)
12035             {
12036               used_prefixes |= prefix;
12037               all_prefixes[last_prefix] = 0;
12038             }
12039         }
12040       dp = &prefix_table[dp->op[1].bytemode][vindex];
12041       break;
12042
12043     case USE_X86_64_TABLE:
12044       vindex = address_mode == mode_64bit ? 1 : 0;
12045       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12046       break;
12047
12048     case USE_3BYTE_TABLE:
12049       FETCH_DATA (info, codep + 2);
12050       vindex = *codep++;
12051       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12052       end_codep = codep;
12053       modrm.mod = (*codep >> 6) & 3;
12054       modrm.reg = (*codep >> 3) & 7;
12055       modrm.rm = *codep & 7;
12056       break;
12057
12058     case USE_VEX_LEN_TABLE:
12059       if (!need_vex)
12060         abort ();
12061
12062       switch (vex.length)
12063         {
12064         case 128:
12065           vindex = 0;
12066           break;
12067         case 256:
12068           vindex = 1;
12069           break;
12070         default:
12071           abort ();
12072           break;
12073         }
12074
12075       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12076       break;
12077
12078     case USE_EVEX_LEN_TABLE:
12079       if (!vex.evex)
12080         abort ();
12081
12082       switch (vex.length)
12083         {
12084         case 128:
12085           vindex = 0;
12086           break;
12087         case 256:
12088           vindex = 1;
12089           break;
12090         case 512:
12091           vindex = 2;
12092           break;
12093         default:
12094           abort ();
12095           break;
12096         }
12097
12098       dp = &evex_len_table[dp->op[1].bytemode][vindex];
12099       break;
12100
12101     case USE_XOP_8F_TABLE:
12102       FETCH_DATA (info, codep + 3);
12103       rex = ~(*codep >> 5) & 0x7;
12104
12105       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12106       switch ((*codep & 0x1f))
12107         {
12108         default:
12109           dp = &bad_opcode;
12110           return dp;
12111         case 0x8:
12112           vex_table_index = XOP_08;
12113           break;
12114         case 0x9:
12115           vex_table_index = XOP_09;
12116           break;
12117         case 0xa:
12118           vex_table_index = XOP_0A;
12119           break;
12120         }
12121       codep++;
12122       vex.w = *codep & 0x80;
12123       if (vex.w && address_mode == mode_64bit)
12124         rex |= REX_W;
12125
12126       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12127       if (address_mode != mode_64bit)
12128         {
12129           /* In 16/32-bit mode REX_B is silently ignored.  */
12130           rex &= ~REX_B;
12131         }
12132
12133       vex.length = (*codep & 0x4) ? 256 : 128;
12134       switch ((*codep & 0x3))
12135         {
12136         case 0:
12137           break;
12138         case 1:
12139           vex.prefix = DATA_PREFIX_OPCODE;
12140           break;
12141         case 2:
12142           vex.prefix = REPE_PREFIX_OPCODE;
12143           break;
12144         case 3:
12145           vex.prefix = REPNE_PREFIX_OPCODE;
12146           break;
12147         }
12148       need_vex = 1;
12149       need_vex_reg = 1;
12150       codep++;
12151       vindex = *codep++;
12152       dp = &xop_table[vex_table_index][vindex];
12153
12154       end_codep = codep;
12155       FETCH_DATA (info, codep + 1);
12156       modrm.mod = (*codep >> 6) & 3;
12157       modrm.reg = (*codep >> 3) & 7;
12158       modrm.rm = *codep & 7;
12159
12160       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
12161          having to decode the bits for every otherwise valid encoding.  */
12162       if (vex.prefix)
12163         return &bad_opcode;
12164       break;
12165
12166     case USE_VEX_C4_TABLE:
12167       /* VEX prefix.  */
12168       FETCH_DATA (info, codep + 3);
12169       rex = ~(*codep >> 5) & 0x7;
12170       switch ((*codep & 0x1f))
12171         {
12172         default:
12173           dp = &bad_opcode;
12174           return dp;
12175         case 0x1:
12176           vex_table_index = VEX_0F;
12177           break;
12178         case 0x2:
12179           vex_table_index = VEX_0F38;
12180           break;
12181         case 0x3:
12182           vex_table_index = VEX_0F3A;
12183           break;
12184         }
12185       codep++;
12186       vex.w = *codep & 0x80;
12187       if (address_mode == mode_64bit)
12188         {
12189           if (vex.w)
12190             rex |= REX_W;
12191         }
12192       else
12193         {
12194           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12195              is ignored, other REX bits are 0 and the highest bit in
12196              VEX.vvvv is also ignored (but we mustn't clear it here).  */
12197           rex = 0;
12198         }
12199       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12200       vex.length = (*codep & 0x4) ? 256 : 128;
12201       switch ((*codep & 0x3))
12202         {
12203         case 0:
12204           break;
12205         case 1:
12206           vex.prefix = DATA_PREFIX_OPCODE;
12207           break;
12208         case 2:
12209           vex.prefix = REPE_PREFIX_OPCODE;
12210           break;
12211         case 3:
12212           vex.prefix = REPNE_PREFIX_OPCODE;
12213           break;
12214         }
12215       need_vex = 1;
12216       need_vex_reg = 1;
12217       codep++;
12218       vindex = *codep++;
12219       dp = &vex_table[vex_table_index][vindex];
12220       end_codep = codep;
12221       /* There is no MODRM byte for VEX0F 77.  */
12222       if (vex_table_index != VEX_0F || vindex != 0x77)
12223         {
12224           FETCH_DATA (info, codep + 1);
12225           modrm.mod = (*codep >> 6) & 3;
12226           modrm.reg = (*codep >> 3) & 7;
12227           modrm.rm = *codep & 7;
12228         }
12229       break;
12230
12231     case USE_VEX_C5_TABLE:
12232       /* VEX prefix.  */
12233       FETCH_DATA (info, codep + 2);
12234       rex = (*codep & 0x80) ? 0 : REX_R;
12235
12236       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12237          VEX.vvvv is 1.  */
12238       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12239       vex.length = (*codep & 0x4) ? 256 : 128;
12240       switch ((*codep & 0x3))
12241         {
12242         case 0:
12243           break;
12244         case 1:
12245           vex.prefix = DATA_PREFIX_OPCODE;
12246           break;
12247         case 2:
12248           vex.prefix = REPE_PREFIX_OPCODE;
12249           break;
12250         case 3:
12251           vex.prefix = REPNE_PREFIX_OPCODE;
12252           break;
12253         }
12254       need_vex = 1;
12255       need_vex_reg = 1;
12256       codep++;
12257       vindex = *codep++;
12258       dp = &vex_table[dp->op[1].bytemode][vindex];
12259       end_codep = codep;
12260       /* There is no MODRM byte for VEX 77.  */
12261       if (vindex != 0x77)
12262         {
12263           FETCH_DATA (info, codep + 1);
12264           modrm.mod = (*codep >> 6) & 3;
12265           modrm.reg = (*codep >> 3) & 7;
12266           modrm.rm = *codep & 7;
12267         }
12268       break;
12269
12270     case USE_VEX_W_TABLE:
12271       if (!need_vex)
12272         abort ();
12273
12274       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12275       break;
12276
12277     case USE_EVEX_TABLE:
12278       two_source_ops = 0;
12279       /* EVEX prefix.  */
12280       vex.evex = 1;
12281       FETCH_DATA (info, codep + 4);
12282       /* The first byte after 0x62.  */
12283       rex = ~(*codep >> 5) & 0x7;
12284       vex.r = *codep & 0x10;
12285       switch ((*codep & 0xf))
12286         {
12287         default:
12288           return &bad_opcode;
12289         case 0x1:
12290           vex_table_index = EVEX_0F;
12291           break;
12292         case 0x2:
12293           vex_table_index = EVEX_0F38;
12294           break;
12295         case 0x3:
12296           vex_table_index = EVEX_0F3A;
12297           break;
12298         }
12299
12300       /* The second byte after 0x62.  */
12301       codep++;
12302       vex.w = *codep & 0x80;
12303       if (vex.w && address_mode == mode_64bit)
12304         rex |= REX_W;
12305
12306       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12307
12308       /* The U bit.  */
12309       if (!(*codep & 0x4))
12310         return &bad_opcode;
12311
12312       switch ((*codep & 0x3))
12313         {
12314         case 0:
12315           break;
12316         case 1:
12317           vex.prefix = DATA_PREFIX_OPCODE;
12318           break;
12319         case 2:
12320           vex.prefix = REPE_PREFIX_OPCODE;
12321           break;
12322         case 3:
12323           vex.prefix = REPNE_PREFIX_OPCODE;
12324           break;
12325         }
12326
12327       /* The third byte after 0x62.  */
12328       codep++;
12329
12330       /* Remember the static rounding bits.  */
12331       vex.ll = (*codep >> 5) & 3;
12332       vex.b = (*codep & 0x10) != 0;
12333
12334       vex.v = *codep & 0x8;
12335       vex.mask_register_specifier = *codep & 0x7;
12336       vex.zeroing = *codep & 0x80;
12337
12338       if (address_mode != mode_64bit)
12339         {
12340           /* In 16/32-bit mode silently ignore following bits.  */
12341           rex &= ~REX_B;
12342           vex.r = 1;
12343           vex.v = 1;
12344         }
12345
12346       need_vex = 1;
12347       need_vex_reg = 1;
12348       codep++;
12349       vindex = *codep++;
12350       dp = &evex_table[vex_table_index][vindex];
12351       end_codep = codep;
12352       FETCH_DATA (info, codep + 1);
12353       modrm.mod = (*codep >> 6) & 3;
12354       modrm.reg = (*codep >> 3) & 7;
12355       modrm.rm = *codep & 7;
12356
12357       /* Set vector length.  */
12358       if (modrm.mod == 3 && vex.b)
12359         vex.length = 512;
12360       else
12361         {
12362           switch (vex.ll)
12363             {
12364             case 0x0:
12365               vex.length = 128;
12366               break;
12367             case 0x1:
12368               vex.length = 256;
12369               break;
12370             case 0x2:
12371               vex.length = 512;
12372               break;
12373             default:
12374               return &bad_opcode;
12375             }
12376         }
12377       break;
12378
12379     case 0:
12380       dp = &bad_opcode;
12381       break;
12382
12383     default:
12384       abort ();
12385     }
12386
12387   if (dp->name != NULL)
12388     return dp;
12389   else
12390     return get_valid_dis386 (dp, info);
12391 }
12392
12393 static void
12394 get_sib (disassemble_info *info, int sizeflag)
12395 {
12396   /* If modrm.mod == 3, operand must be register.  */
12397   if (need_modrm
12398       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12399       && modrm.mod != 3
12400       && modrm.rm == 4)
12401     {
12402       FETCH_DATA (info, codep + 2);
12403       sib.index = (codep [1] >> 3) & 7;
12404       sib.scale = (codep [1] >> 6) & 3;
12405       sib.base = codep [1] & 7;
12406     }
12407 }
12408
12409 static int
12410 print_insn (bfd_vma pc, disassemble_info *info)
12411 {
12412   const struct dis386 *dp;
12413   int i;
12414   char *op_txt[MAX_OPERANDS];
12415   int needcomma;
12416   int sizeflag, orig_sizeflag;
12417   const char *p;
12418   struct dis_private priv;
12419   int prefix_length;
12420
12421   priv.orig_sizeflag = AFLAG | DFLAG;
12422   if ((info->mach & bfd_mach_i386_i386) != 0)
12423     address_mode = mode_32bit;
12424   else if (info->mach == bfd_mach_i386_i8086)
12425     {
12426       address_mode = mode_16bit;
12427       priv.orig_sizeflag = 0;
12428     }
12429   else
12430     address_mode = mode_64bit;
12431
12432   if (intel_syntax == (char) -1)
12433     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12434
12435   for (p = info->disassembler_options; p != NULL; )
12436     {
12437       if (CONST_STRNEQ (p, "amd64"))
12438         isa64 = amd64;
12439       else if (CONST_STRNEQ (p, "intel64"))
12440         isa64 = intel64;
12441       else if (CONST_STRNEQ (p, "x86-64"))
12442         {
12443           address_mode = mode_64bit;
12444           priv.orig_sizeflag |= AFLAG | DFLAG;
12445         }
12446       else if (CONST_STRNEQ (p, "i386"))
12447         {
12448           address_mode = mode_32bit;
12449           priv.orig_sizeflag |= AFLAG | DFLAG;
12450         }
12451       else if (CONST_STRNEQ (p, "i8086"))
12452         {
12453           address_mode = mode_16bit;
12454           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
12455         }
12456       else if (CONST_STRNEQ (p, "intel"))
12457         {
12458           intel_syntax = 1;
12459           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12460             intel_mnemonic = 1;
12461         }
12462       else if (CONST_STRNEQ (p, "att"))
12463         {
12464           intel_syntax = 0;
12465           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12466             intel_mnemonic = 0;
12467         }
12468       else if (CONST_STRNEQ (p, "addr"))
12469         {
12470           if (address_mode == mode_64bit)
12471             {
12472               if (p[4] == '3' && p[5] == '2')
12473                 priv.orig_sizeflag &= ~AFLAG;
12474               else if (p[4] == '6' && p[5] == '4')
12475                 priv.orig_sizeflag |= AFLAG;
12476             }
12477           else
12478             {
12479               if (p[4] == '1' && p[5] == '6')
12480                 priv.orig_sizeflag &= ~AFLAG;
12481               else if (p[4] == '3' && p[5] == '2')
12482                 priv.orig_sizeflag |= AFLAG;
12483             }
12484         }
12485       else if (CONST_STRNEQ (p, "data"))
12486         {
12487           if (p[4] == '1' && p[5] == '6')
12488             priv.orig_sizeflag &= ~DFLAG;
12489           else if (p[4] == '3' && p[5] == '2')
12490             priv.orig_sizeflag |= DFLAG;
12491         }
12492       else if (CONST_STRNEQ (p, "suffix"))
12493         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12494
12495       p = strchr (p, ',');
12496       if (p != NULL)
12497         p++;
12498     }
12499
12500   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
12501     {
12502       (*info->fprintf_func) (info->stream,
12503                              _("64-bit address is disabled"));
12504       return -1;
12505     }
12506
12507   if (intel_syntax)
12508     {
12509       names64 = intel_names64;
12510       names32 = intel_names32;
12511       names16 = intel_names16;
12512       names8 = intel_names8;
12513       names8rex = intel_names8rex;
12514       names_seg = intel_names_seg;
12515       names_mm = intel_names_mm;
12516       names_bnd = intel_names_bnd;
12517       names_xmm = intel_names_xmm;
12518       names_ymm = intel_names_ymm;
12519       names_zmm = intel_names_zmm;
12520       names_tmm = intel_names_tmm;
12521       index64 = intel_index64;
12522       index32 = intel_index32;
12523       names_mask = intel_names_mask;
12524       index16 = intel_index16;
12525       open_char = '[';
12526       close_char = ']';
12527       separator_char = '+';
12528       scale_char = '*';
12529     }
12530   else
12531     {
12532       names64 = att_names64;
12533       names32 = att_names32;
12534       names16 = att_names16;
12535       names8 = att_names8;
12536       names8rex = att_names8rex;
12537       names_seg = att_names_seg;
12538       names_mm = att_names_mm;
12539       names_bnd = att_names_bnd;
12540       names_xmm = att_names_xmm;
12541       names_ymm = att_names_ymm;
12542       names_zmm = att_names_zmm;
12543       names_tmm = att_names_tmm;
12544       index64 = att_index64;
12545       index32 = att_index32;
12546       names_mask = att_names_mask;
12547       index16 = att_index16;
12548       open_char = '(';
12549       close_char =  ')';
12550       separator_char = ',';
12551       scale_char = ',';
12552     }
12553
12554   /* The output looks better if we put 7 bytes on a line, since that
12555      puts most long word instructions on a single line.  Use 8 bytes
12556      for Intel L1OM.  */
12557   if ((info->mach & bfd_mach_l1om) != 0)
12558     info->bytes_per_line = 8;
12559   else
12560     info->bytes_per_line = 7;
12561
12562   info->private_data = &priv;
12563   priv.max_fetched = priv.the_buffer;
12564   priv.insn_start = pc;
12565
12566   obuf[0] = 0;
12567   for (i = 0; i < MAX_OPERANDS; ++i)
12568     {
12569       op_out[i][0] = 0;
12570       op_index[i] = -1;
12571     }
12572
12573   the_info = info;
12574   start_pc = pc;
12575   start_codep = priv.the_buffer;
12576   codep = priv.the_buffer;
12577
12578   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12579     {
12580       const char *name;
12581
12582       /* Getting here means we tried for data but didn't get it.  That
12583          means we have an incomplete instruction of some sort.  Just
12584          print the first byte as a prefix or a .byte pseudo-op.  */
12585       if (codep > priv.the_buffer)
12586         {
12587           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12588           if (name != NULL)
12589             (*info->fprintf_func) (info->stream, "%s", name);
12590           else
12591             {
12592               /* Just print the first byte as a .byte instruction.  */
12593               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12594                                      (unsigned int) priv.the_buffer[0]);
12595             }
12596
12597           return 1;
12598         }
12599
12600       return -1;
12601     }
12602
12603   obufp = obuf;
12604   sizeflag = priv.orig_sizeflag;
12605
12606   if (!ckprefix () || rex_used)
12607     {
12608       /* Too many prefixes or unused REX prefixes.  */
12609       for (i = 0;
12610            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12611            i++)
12612         (*info->fprintf_func) (info->stream, "%s%s",
12613                                i == 0 ? "" : " ",
12614                                prefix_name (all_prefixes[i], sizeflag));
12615       return i;
12616     }
12617
12618   insn_codep = codep;
12619
12620   FETCH_DATA (info, codep + 1);
12621   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12622
12623   if (((prefixes & PREFIX_FWAIT)
12624        && ((*codep < 0xd8) || (*codep > 0xdf))))
12625     {
12626       /* Handle prefixes before fwait.  */
12627       for (i = 0; i < fwait_prefix && all_prefixes[i];
12628            i++)
12629         (*info->fprintf_func) (info->stream, "%s ",
12630                                prefix_name (all_prefixes[i], sizeflag));
12631       (*info->fprintf_func) (info->stream, "fwait");
12632       return i + 1;
12633     }
12634
12635   if (*codep == 0x0f)
12636     {
12637       unsigned char threebyte;
12638
12639       codep++;
12640       FETCH_DATA (info, codep + 1);
12641       threebyte = *codep;
12642       dp = &dis386_twobyte[threebyte];
12643       need_modrm = twobyte_has_modrm[*codep];
12644       codep++;
12645     }
12646   else
12647     {
12648       dp = &dis386[*codep];
12649       need_modrm = onebyte_has_modrm[*codep];
12650       codep++;
12651     }
12652
12653   /* Save sizeflag for printing the extra prefixes later before updating
12654      it for mnemonic and operand processing.  The prefix names depend
12655      only on the address mode.  */
12656   orig_sizeflag = sizeflag;
12657   if (prefixes & PREFIX_ADDR)
12658     sizeflag ^= AFLAG;
12659   if ((prefixes & PREFIX_DATA))
12660     sizeflag ^= DFLAG;
12661
12662   end_codep = codep;
12663   if (need_modrm)
12664     {
12665       FETCH_DATA (info, codep + 1);
12666       modrm.mod = (*codep >> 6) & 3;
12667       modrm.reg = (*codep >> 3) & 7;
12668       modrm.rm = *codep & 7;
12669     }
12670
12671   need_vex = 0;
12672   need_vex_reg = 0;
12673   memset (&vex, 0, sizeof (vex));
12674
12675   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12676     {
12677       get_sib (info, sizeflag);
12678       dofloat (sizeflag);
12679     }
12680   else
12681     {
12682       dp = get_valid_dis386 (dp, info);
12683       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12684         {
12685           get_sib (info, sizeflag);
12686           for (i = 0; i < MAX_OPERANDS; ++i)
12687             {
12688               obufp = op_out[i];
12689               op_ad = MAX_OPERANDS - 1 - i;
12690               if (dp->op[i].rtn)
12691                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12692               /* For EVEX instruction after the last operand masking
12693                  should be printed.  */
12694               if (i == 0 && vex.evex)
12695                 {
12696                   /* Don't print {%k0}.  */
12697                   if (vex.mask_register_specifier)
12698                     {
12699                       oappend ("{");
12700                       oappend (names_mask[vex.mask_register_specifier]);
12701                       oappend ("}");
12702                     }
12703                   if (vex.zeroing)
12704                     oappend ("{z}");
12705                 }
12706             }
12707         }
12708     }
12709
12710   /* Clear instruction information.  */
12711   if (the_info)
12712     {
12713       the_info->insn_info_valid = 0;
12714       the_info->branch_delay_insns = 0;
12715       the_info->data_size = 0;
12716       the_info->insn_type = dis_noninsn;
12717       the_info->target = 0;
12718       the_info->target2 = 0;
12719     }
12720
12721   /* Reset jump operation indicator.  */
12722   op_is_jump = FALSE;
12723
12724   {
12725     int jump_detection = 0;
12726
12727     /* Extract flags.  */
12728     for (i = 0; i < MAX_OPERANDS; ++i)
12729       {
12730         if ((dp->op[i].rtn == OP_J)
12731             || (dp->op[i].rtn == OP_indirE))
12732           jump_detection |= 1;
12733         else if ((dp->op[i].rtn == BND_Fixup)
12734                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12735           jump_detection |= 2;
12736         else if ((dp->op[i].bytemode == cond_jump_mode)
12737                  || (dp->op[i].bytemode == loop_jcxz_mode))
12738           jump_detection |= 4;
12739       }
12740
12741     /* Determine if this is a jump or branch.  */
12742     if ((jump_detection & 0x3) == 0x3)
12743       {
12744         op_is_jump = TRUE;
12745         if (jump_detection & 0x4)
12746           the_info->insn_type = dis_condbranch;
12747         else
12748           the_info->insn_type =
12749             (dp->name && !strncmp(dp->name, "call", 4))
12750             ? dis_jsr : dis_branch;
12751       }
12752   }
12753
12754   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12755      are all 0s in inverted form.  */
12756   if (need_vex && vex.register_specifier != 0)
12757     {
12758       (*info->fprintf_func) (info->stream, "(bad)");
12759       return end_codep - priv.the_buffer;
12760     }
12761
12762   /* Check if the REX prefix is used.  */
12763   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
12764     all_prefixes[last_rex_prefix] = 0;
12765
12766   /* Check if the SEG prefix is used.  */
12767   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12768                    | PREFIX_FS | PREFIX_GS)) != 0
12769       && (used_prefixes & active_seg_prefix) != 0)
12770     all_prefixes[last_seg_prefix] = 0;
12771
12772   /* Check if the ADDR prefix is used.  */
12773   if ((prefixes & PREFIX_ADDR) != 0
12774       && (used_prefixes & PREFIX_ADDR) != 0)
12775     all_prefixes[last_addr_prefix] = 0;
12776
12777   /* Check if the DATA prefix is used.  */
12778   if ((prefixes & PREFIX_DATA) != 0
12779       && (used_prefixes & PREFIX_DATA) != 0
12780       && !need_vex)
12781     all_prefixes[last_data_prefix] = 0;
12782
12783   /* Print the extra prefixes.  */
12784   prefix_length = 0;
12785   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12786     if (all_prefixes[i])
12787       {
12788         const char *name;
12789         name = prefix_name (all_prefixes[i], orig_sizeflag);
12790         if (name == NULL)
12791           abort ();
12792         prefix_length += strlen (name) + 1;
12793         (*info->fprintf_func) (info->stream, "%s ", name);
12794       }
12795
12796   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12797      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12798      used by putop and MMX/SSE operand and may be overriden by the
12799      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12800      separately.  */
12801   if (dp->prefix_requirement == PREFIX_OPCODE
12802       && (((need_vex
12803             ? vex.prefix == REPE_PREFIX_OPCODE
12804               || vex.prefix == REPNE_PREFIX_OPCODE
12805             : (prefixes
12806                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12807            && (used_prefixes
12808                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12809           || (((need_vex
12810                 ? vex.prefix == DATA_PREFIX_OPCODE
12811                 : ((prefixes
12812                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12813                    == PREFIX_DATA))
12814                && (used_prefixes & PREFIX_DATA) == 0))
12815           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12816     {
12817       (*info->fprintf_func) (info->stream, "(bad)");
12818       return end_codep - priv.the_buffer;
12819     }
12820
12821   /* Check maximum code length.  */
12822   if ((codep - start_codep) > MAX_CODE_LENGTH)
12823     {
12824       (*info->fprintf_func) (info->stream, "(bad)");
12825       return MAX_CODE_LENGTH;
12826     }
12827
12828   obufp = mnemonicendp;
12829   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12830     oappend (" ");
12831   oappend (" ");
12832   (*info->fprintf_func) (info->stream, "%s", obuf);
12833
12834   /* The enter and bound instructions are printed with operands in the same
12835      order as the intel book; everything else is printed in reverse order.  */
12836   if (intel_syntax || two_source_ops)
12837     {
12838       bfd_vma riprel;
12839
12840       for (i = 0; i < MAX_OPERANDS; ++i)
12841         op_txt[i] = op_out[i];
12842
12843       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12844           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12845         {
12846           op_txt[2] = op_out[3];
12847           op_txt[3] = op_out[2];
12848         }
12849
12850       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12851         {
12852           op_ad = op_index[i];
12853           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12854           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12855           riprel = op_riprel[i];
12856           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12857           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12858         }
12859     }
12860   else
12861     {
12862       for (i = 0; i < MAX_OPERANDS; ++i)
12863         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12864     }
12865
12866   needcomma = 0;
12867   for (i = 0; i < MAX_OPERANDS; ++i)
12868     if (*op_txt[i])
12869       {
12870         if (needcomma)
12871           (*info->fprintf_func) (info->stream, ",");
12872         if (op_index[i] != -1 && !op_riprel[i])
12873           {
12874             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12875
12876             if (the_info && op_is_jump)
12877               {
12878                 the_info->insn_info_valid = 1;
12879                 the_info->branch_delay_insns = 0;
12880                 the_info->data_size = 0;
12881                 the_info->target = target;
12882                 the_info->target2 = 0;
12883               }
12884             (*info->print_address_func) (target, info);
12885           }
12886         else
12887           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12888         needcomma = 1;
12889       }
12890
12891   for (i = 0; i < MAX_OPERANDS; i++)
12892     if (op_index[i] != -1 && op_riprel[i])
12893       {
12894         (*info->fprintf_func) (info->stream, "        # ");
12895         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12896                                                 + op_address[op_index[i]]), info);
12897         break;
12898       }
12899   return codep - priv.the_buffer;
12900 }
12901
12902 static const char *float_mem[] = {
12903   /* d8 */
12904   "fadd{s|}",
12905   "fmul{s|}",
12906   "fcom{s|}",
12907   "fcomp{s|}",
12908   "fsub{s|}",
12909   "fsubr{s|}",
12910   "fdiv{s|}",
12911   "fdivr{s|}",
12912   /* d9 */
12913   "fld{s|}",
12914   "(bad)",
12915   "fst{s|}",
12916   "fstp{s|}",
12917   "fldenv{C|C}",
12918   "fldcw",
12919   "fNstenv{C|C}",
12920   "fNstcw",
12921   /* da */
12922   "fiadd{l|}",
12923   "fimul{l|}",
12924   "ficom{l|}",
12925   "ficomp{l|}",
12926   "fisub{l|}",
12927   "fisubr{l|}",
12928   "fidiv{l|}",
12929   "fidivr{l|}",
12930   /* db */
12931   "fild{l|}",
12932   "fisttp{l|}",
12933   "fist{l|}",
12934   "fistp{l|}",
12935   "(bad)",
12936   "fld{t|}",
12937   "(bad)",
12938   "fstp{t|}",
12939   /* dc */
12940   "fadd{l|}",
12941   "fmul{l|}",
12942   "fcom{l|}",
12943   "fcomp{l|}",
12944   "fsub{l|}",
12945   "fsubr{l|}",
12946   "fdiv{l|}",
12947   "fdivr{l|}",
12948   /* dd */
12949   "fld{l|}",
12950   "fisttp{ll|}",
12951   "fst{l||}",
12952   "fstp{l|}",
12953   "frstor{C|C}",
12954   "(bad)",
12955   "fNsave{C|C}",
12956   "fNstsw",
12957   /* de */
12958   "fiadd{s|}",
12959   "fimul{s|}",
12960   "ficom{s|}",
12961   "ficomp{s|}",
12962   "fisub{s|}",
12963   "fisubr{s|}",
12964   "fidiv{s|}",
12965   "fidivr{s|}",
12966   /* df */
12967   "fild{s|}",
12968   "fisttp{s|}",
12969   "fist{s|}",
12970   "fistp{s|}",
12971   "fbld",
12972   "fild{ll|}",
12973   "fbstp",
12974   "fistp{ll|}",
12975 };
12976
12977 static const unsigned char float_mem_mode[] = {
12978   /* d8 */
12979   d_mode,
12980   d_mode,
12981   d_mode,
12982   d_mode,
12983   d_mode,
12984   d_mode,
12985   d_mode,
12986   d_mode,
12987   /* d9 */
12988   d_mode,
12989   0,
12990   d_mode,
12991   d_mode,
12992   0,
12993   w_mode,
12994   0,
12995   w_mode,
12996   /* da */
12997   d_mode,
12998   d_mode,
12999   d_mode,
13000   d_mode,
13001   d_mode,
13002   d_mode,
13003   d_mode,
13004   d_mode,
13005   /* db */
13006   d_mode,
13007   d_mode,
13008   d_mode,
13009   d_mode,
13010   0,
13011   t_mode,
13012   0,
13013   t_mode,
13014   /* dc */
13015   q_mode,
13016   q_mode,
13017   q_mode,
13018   q_mode,
13019   q_mode,
13020   q_mode,
13021   q_mode,
13022   q_mode,
13023   /* dd */
13024   q_mode,
13025   q_mode,
13026   q_mode,
13027   q_mode,
13028   0,
13029   0,
13030   0,
13031   w_mode,
13032   /* de */
13033   w_mode,
13034   w_mode,
13035   w_mode,
13036   w_mode,
13037   w_mode,
13038   w_mode,
13039   w_mode,
13040   w_mode,
13041   /* df */
13042   w_mode,
13043   w_mode,
13044   w_mode,
13045   w_mode,
13046   t_mode,
13047   q_mode,
13048   t_mode,
13049   q_mode
13050 };
13051
13052 #define ST { OP_ST, 0 }
13053 #define STi { OP_STi, 0 }
13054
13055 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13056 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13057 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13058 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13059 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13060 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13061 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13062 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13063 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13064
13065 static const struct dis386 float_reg[][8] = {
13066   /* d8 */
13067   {
13068     { "fadd",   { ST, STi }, 0 },
13069     { "fmul",   { ST, STi }, 0 },
13070     { "fcom",   { STi }, 0 },
13071     { "fcomp",  { STi }, 0 },
13072     { "fsub",   { ST, STi }, 0 },
13073     { "fsubr",  { ST, STi }, 0 },
13074     { "fdiv",   { ST, STi }, 0 },
13075     { "fdivr",  { ST, STi }, 0 },
13076   },
13077   /* d9 */
13078   {
13079     { "fld",    { STi }, 0 },
13080     { "fxch",   { STi }, 0 },
13081     { FGRPd9_2 },
13082     { Bad_Opcode },
13083     { FGRPd9_4 },
13084     { FGRPd9_5 },
13085     { FGRPd9_6 },
13086     { FGRPd9_7 },
13087   },
13088   /* da */
13089   {
13090     { "fcmovb", { ST, STi }, 0 },
13091     { "fcmove", { ST, STi }, 0 },
13092     { "fcmovbe",{ ST, STi }, 0 },
13093     { "fcmovu", { ST, STi }, 0 },
13094     { Bad_Opcode },
13095     { FGRPda_5 },
13096     { Bad_Opcode },
13097     { Bad_Opcode },
13098   },
13099   /* db */
13100   {
13101     { "fcmovnb",{ ST, STi }, 0 },
13102     { "fcmovne",{ ST, STi }, 0 },
13103     { "fcmovnbe",{ ST, STi }, 0 },
13104     { "fcmovnu",{ ST, STi }, 0 },
13105     { FGRPdb_4 },
13106     { "fucomi", { ST, STi }, 0 },
13107     { "fcomi",  { ST, STi }, 0 },
13108     { Bad_Opcode },
13109   },
13110   /* dc */
13111   {
13112     { "fadd",   { STi, ST }, 0 },
13113     { "fmul",   { STi, ST }, 0 },
13114     { Bad_Opcode },
13115     { Bad_Opcode },
13116     { "fsub{!M|r}",     { STi, ST }, 0 },
13117     { "fsub{M|}",       { STi, ST }, 0 },
13118     { "fdiv{!M|r}",     { STi, ST }, 0 },
13119     { "fdiv{M|}",       { STi, ST }, 0 },
13120   },
13121   /* dd */
13122   {
13123     { "ffree",  { STi }, 0 },
13124     { Bad_Opcode },
13125     { "fst",    { STi }, 0 },
13126     { "fstp",   { STi }, 0 },
13127     { "fucom",  { STi }, 0 },
13128     { "fucomp", { STi }, 0 },
13129     { Bad_Opcode },
13130     { Bad_Opcode },
13131   },
13132   /* de */
13133   {
13134     { "faddp",  { STi, ST }, 0 },
13135     { "fmulp",  { STi, ST }, 0 },
13136     { Bad_Opcode },
13137     { FGRPde_3 },
13138     { "fsub{!M|r}p",    { STi, ST }, 0 },
13139     { "fsub{M|}p",      { STi, ST }, 0 },
13140     { "fdiv{!M|r}p",    { STi, ST }, 0 },
13141     { "fdiv{M|}p",      { STi, ST }, 0 },
13142   },
13143   /* df */
13144   {
13145     { "ffreep", { STi }, 0 },
13146     { Bad_Opcode },
13147     { Bad_Opcode },
13148     { Bad_Opcode },
13149     { FGRPdf_4 },
13150     { "fucomip", { ST, STi }, 0 },
13151     { "fcomip", { ST, STi }, 0 },
13152     { Bad_Opcode },
13153   },
13154 };
13155
13156 static char *fgrps[][8] = {
13157   /* Bad opcode 0 */
13158   {
13159     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13160   },
13161
13162   /* d9_2  1 */
13163   {
13164     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13165   },
13166
13167   /* d9_4  2 */
13168   {
13169     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13170   },
13171
13172   /* d9_5  3 */
13173   {
13174     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13175   },
13176
13177   /* d9_6  4 */
13178   {
13179     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13180   },
13181
13182   /* d9_7  5 */
13183   {
13184     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13185   },
13186
13187   /* da_5  6 */
13188   {
13189     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13190   },
13191
13192   /* db_4  7 */
13193   {
13194     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13195     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13196   },
13197
13198   /* de_3  8 */
13199   {
13200     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13201   },
13202
13203   /* df_4  9 */
13204   {
13205     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13206   },
13207 };
13208
13209 static void
13210 swap_operand (void)
13211 {
13212   mnemonicendp[0] = '.';
13213   mnemonicendp[1] = 's';
13214   mnemonicendp += 2;
13215 }
13216
13217 static void
13218 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13219                int sizeflag ATTRIBUTE_UNUSED)
13220 {
13221   /* Skip mod/rm byte.  */
13222   MODRM_CHECK;
13223   codep++;
13224 }
13225
13226 static void
13227 dofloat (int sizeflag)
13228 {
13229   const struct dis386 *dp;
13230   unsigned char floatop;
13231
13232   floatop = codep[-1];
13233
13234   if (modrm.mod != 3)
13235     {
13236       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13237
13238       putop (float_mem[fp_indx], sizeflag);
13239       obufp = op_out[0];
13240       op_ad = 2;
13241       OP_E (float_mem_mode[fp_indx], sizeflag);
13242       return;
13243     }
13244   /* Skip mod/rm byte.  */
13245   MODRM_CHECK;
13246   codep++;
13247
13248   dp = &float_reg[floatop - 0xd8][modrm.reg];
13249   if (dp->name == NULL)
13250     {
13251       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13252
13253       /* Instruction fnstsw is only one with strange arg.  */
13254       if (floatop == 0xdf && codep[-1] == 0xe0)
13255         strcpy (op_out[0], names16[0]);
13256     }
13257   else
13258     {
13259       putop (dp->name, sizeflag);
13260
13261       obufp = op_out[0];
13262       op_ad = 2;
13263       if (dp->op[0].rtn)
13264         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13265
13266       obufp = op_out[1];
13267       op_ad = 1;
13268       if (dp->op[1].rtn)
13269         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13270     }
13271 }
13272
13273 /* Like oappend (below), but S is a string starting with '%'.
13274    In Intel syntax, the '%' is elided.  */
13275 static void
13276 oappend_maybe_intel (const char *s)
13277 {
13278   oappend (s + intel_syntax);
13279 }
13280
13281 static void
13282 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13283 {
13284   oappend_maybe_intel ("%st");
13285 }
13286
13287 static void
13288 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13289 {
13290   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13291   oappend_maybe_intel (scratchbuf);
13292 }
13293
13294 /* Capital letters in template are macros.  */
13295 static int
13296 putop (const char *in_template, int sizeflag)
13297 {
13298   const char *p;
13299   int alt = 0;
13300   int cond = 1;
13301   unsigned int l = 0, len = 0;
13302   char last[4];
13303
13304   for (p = in_template; *p; p++)
13305     {
13306       if (len > l)
13307         {
13308           if (l >= sizeof (last) || !ISUPPER (*p))
13309             abort ();
13310           last[l++] = *p;
13311           continue;
13312         }
13313       switch (*p)
13314         {
13315         default:
13316           *obufp++ = *p;
13317           break;
13318         case '%':
13319           len++;
13320           break;
13321         case '!':
13322           cond = 0;
13323           break;
13324         case '{':
13325           if (intel_syntax)
13326             {
13327               while (*++p != '|')
13328                 if (*p == '}' || *p == '\0')
13329                   abort ();
13330               alt = 1;
13331             }
13332           break;
13333         case '|':
13334           while (*++p != '}')
13335             {
13336               if (*p == '\0')
13337                 abort ();
13338             }
13339           break;
13340         case '}':
13341           alt = 0;
13342           break;
13343         case 'A':
13344           if (intel_syntax)
13345             break;
13346           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13347             *obufp++ = 'b';
13348           break;
13349         case 'B':
13350           if (l == 0)
13351             {
13352             case_B:
13353               if (intel_syntax)
13354                 break;
13355               if (sizeflag & SUFFIX_ALWAYS)
13356                 *obufp++ = 'b';
13357             }
13358           else if (l == 1 && last[0] == 'L')
13359             {
13360               if (address_mode == mode_64bit
13361                   && !(prefixes & PREFIX_ADDR))
13362                 {
13363                   *obufp++ = 'a';
13364                   *obufp++ = 'b';
13365                   *obufp++ = 's';
13366                 }
13367
13368               goto case_B;
13369             }
13370           else
13371             abort ();
13372           break;
13373         case 'C':
13374           if (intel_syntax && !alt)
13375             break;
13376           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13377             {
13378               if (sizeflag & DFLAG)
13379                 *obufp++ = intel_syntax ? 'd' : 'l';
13380               else
13381                 *obufp++ = intel_syntax ? 'w' : 's';
13382               used_prefixes |= (prefixes & PREFIX_DATA);
13383             }
13384           break;
13385         case 'D':
13386           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13387             break;
13388           USED_REX (REX_W);
13389           if (modrm.mod == 3)
13390             {
13391               if (rex & REX_W)
13392                 *obufp++ = 'q';
13393               else
13394                 {
13395                   if (sizeflag & DFLAG)
13396                     *obufp++ = intel_syntax ? 'd' : 'l';
13397                   else
13398                     *obufp++ = 'w';
13399                   used_prefixes |= (prefixes & PREFIX_DATA);
13400                 }
13401             }
13402           else
13403             *obufp++ = 'w';
13404           break;
13405         case 'E':               /* For jcxz/jecxz */
13406           if (address_mode == mode_64bit)
13407             {
13408               if (sizeflag & AFLAG)
13409                 *obufp++ = 'r';
13410               else
13411                 *obufp++ = 'e';
13412             }
13413           else
13414             if (sizeflag & AFLAG)
13415               *obufp++ = 'e';
13416           used_prefixes |= (prefixes & PREFIX_ADDR);
13417           break;
13418         case 'F':
13419           if (intel_syntax)
13420             break;
13421           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13422             {
13423               if (sizeflag & AFLAG)
13424                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13425               else
13426                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13427               used_prefixes |= (prefixes & PREFIX_ADDR);
13428             }
13429           break;
13430         case 'G':
13431           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13432             break;
13433           if ((rex & REX_W) || (sizeflag & DFLAG))
13434             *obufp++ = 'l';
13435           else
13436             *obufp++ = 'w';
13437           if (!(rex & REX_W))
13438             used_prefixes |= (prefixes & PREFIX_DATA);
13439           break;
13440         case 'H':
13441           if (intel_syntax)
13442             break;
13443           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13444               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13445             {
13446               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13447               *obufp++ = ',';
13448               *obufp++ = 'p';
13449               if (prefixes & PREFIX_DS)
13450                 *obufp++ = 't';
13451               else
13452                 *obufp++ = 'n';
13453             }
13454           break;
13455         case 'K':
13456           USED_REX (REX_W);
13457           if (rex & REX_W)
13458             *obufp++ = 'q';
13459           else
13460             *obufp++ = 'd';
13461           break;
13462         case 'Z':
13463           if (l != 0)
13464             {
13465               if (l != 1 || last[0] != 'X')
13466                 abort ();
13467               if (!need_vex || !vex.evex)
13468                 abort ();
13469               if (intel_syntax
13470                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13471                 break;
13472               switch (vex.length)
13473                 {
13474                 case 128:
13475                   *obufp++ = 'x';
13476                   break;
13477                 case 256:
13478                   *obufp++ = 'y';
13479                   break;
13480                 case 512:
13481                   *obufp++ = 'z';
13482                   break;
13483                 default:
13484                   abort ();
13485                 }
13486               break;
13487             }
13488           if (intel_syntax)
13489             break;
13490           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13491             {
13492               *obufp++ = 'q';
13493               break;
13494             }
13495           /* Fall through.  */
13496           goto case_L;
13497         case 'L':
13498           if (l != 0)
13499             abort ();
13500         case_L:
13501           if (intel_syntax)
13502             break;
13503           if (sizeflag & SUFFIX_ALWAYS)
13504             *obufp++ = 'l';
13505           break;
13506         case 'M':
13507           if (intel_mnemonic != cond)
13508             *obufp++ = 'r';
13509           break;
13510         case 'N':
13511           if ((prefixes & PREFIX_FWAIT) == 0)
13512             *obufp++ = 'n';
13513           else
13514             used_prefixes |= PREFIX_FWAIT;
13515           break;
13516         case 'O':
13517           USED_REX (REX_W);
13518           if (rex & REX_W)
13519             *obufp++ = 'o';
13520           else if (intel_syntax && (sizeflag & DFLAG))
13521             *obufp++ = 'q';
13522           else
13523             *obufp++ = 'd';
13524           if (!(rex & REX_W))
13525             used_prefixes |= (prefixes & PREFIX_DATA);
13526           break;
13527         case '&':
13528           if (!intel_syntax
13529               && address_mode == mode_64bit
13530               && isa64 == intel64)
13531             {
13532               *obufp++ = 'q';
13533               break;
13534             }
13535           /* Fall through.  */
13536         case 'T':
13537           if (!intel_syntax
13538               && address_mode == mode_64bit
13539               && ((sizeflag & DFLAG) || (rex & REX_W)))
13540             {
13541               *obufp++ = 'q';
13542               break;
13543             }
13544           /* Fall through.  */
13545           goto case_P;
13546         case 'P':
13547           if (l == 0)
13548             {
13549             case_P:
13550               if (intel_syntax)
13551                 {
13552                   if ((rex & REX_W) == 0
13553                       && (prefixes & PREFIX_DATA))
13554                     {
13555                       if ((sizeflag & DFLAG) == 0)
13556                         *obufp++ = 'w';
13557                       used_prefixes |= (prefixes & PREFIX_DATA);
13558                     }
13559                   break;
13560                 }
13561               if ((prefixes & PREFIX_DATA)
13562                   || (rex & REX_W)
13563                   || (sizeflag & SUFFIX_ALWAYS))
13564                 {
13565                   USED_REX (REX_W);
13566                   if (rex & REX_W)
13567                     *obufp++ = 'q';
13568                   else
13569                     {
13570                       if (sizeflag & DFLAG)
13571                         *obufp++ = 'l';
13572                       else
13573                         *obufp++ = 'w';
13574                       used_prefixes |= (prefixes & PREFIX_DATA);
13575                     }
13576                 }
13577             }
13578           else if (l == 1 && last[0] == 'L')
13579             {
13580               if ((prefixes & PREFIX_DATA)
13581                   || (rex & REX_W)
13582                   || (sizeflag & SUFFIX_ALWAYS))
13583                 {
13584                   USED_REX (REX_W);
13585                   if (rex & REX_W)
13586                     *obufp++ = 'q';
13587                   else
13588                     {
13589                       if (sizeflag & DFLAG)
13590                         *obufp++ = intel_syntax ? 'd' : 'l';
13591                       else
13592                         *obufp++ = 'w';
13593                       used_prefixes |= (prefixes & PREFIX_DATA);
13594                     }
13595                 }
13596             }
13597           else
13598             abort ();
13599           break;
13600         case 'U':
13601           if (intel_syntax)
13602             break;
13603           if (address_mode == mode_64bit
13604               && ((sizeflag & DFLAG) || (rex & REX_W)))
13605             {
13606               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13607                 *obufp++ = 'q';
13608               break;
13609             }
13610           /* Fall through.  */
13611           goto case_Q;
13612         case 'Q':
13613           if (l == 0)
13614             {
13615             case_Q:
13616               if (intel_syntax && !alt)
13617                 break;
13618               USED_REX (REX_W);
13619               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13620                 {
13621                   if (rex & REX_W)
13622                     *obufp++ = 'q';
13623                   else
13624                     {
13625                       if (sizeflag & DFLAG)
13626                         *obufp++ = intel_syntax ? 'd' : 'l';
13627                       else
13628                         *obufp++ = 'w';
13629                       used_prefixes |= (prefixes & PREFIX_DATA);
13630                     }
13631                 }
13632             }
13633           else if (l == 1 && last[0] == 'D')
13634             *obufp++ = vex.w ? 'q' : 'd';
13635           else if (l == 1 && last[0] == 'L')
13636             {
13637               if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
13638                        : address_mode != mode_64bit)
13639                 break;
13640               if ((rex & REX_W))
13641                 {
13642                   USED_REX (REX_W);
13643                   *obufp++ = 'q';
13644                 }
13645               else if((address_mode == mode_64bit && need_modrm && cond)
13646                       || (sizeflag & SUFFIX_ALWAYS))
13647                 *obufp++ = intel_syntax? 'd' : 'l';
13648             }
13649           else
13650             abort ();
13651           break;
13652         case 'R':
13653           USED_REX (REX_W);
13654           if (rex & REX_W)
13655             *obufp++ = 'q';
13656           else if (sizeflag & DFLAG)
13657             {
13658               if (intel_syntax)
13659                   *obufp++ = 'd';
13660               else
13661                   *obufp++ = 'l';
13662             }
13663           else
13664             *obufp++ = 'w';
13665           if (intel_syntax && !p[1]
13666               && ((rex & REX_W) || (sizeflag & DFLAG)))
13667             *obufp++ = 'e';
13668           if (!(rex & REX_W))
13669             used_prefixes |= (prefixes & PREFIX_DATA);
13670           break;
13671         case 'V':
13672           if (l == 0)
13673             {
13674               if (intel_syntax)
13675                 break;
13676               if (address_mode == mode_64bit
13677                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13678                 {
13679                   if (sizeflag & SUFFIX_ALWAYS)
13680                     *obufp++ = 'q';
13681                   break;
13682                 }
13683             }
13684           else if (l == 1 && last[0] == 'L')
13685             {
13686               if (rex & REX_W)
13687                 {
13688                   *obufp++ = 'a';
13689                   *obufp++ = 'b';
13690                   *obufp++ = 's';
13691                 }
13692             }
13693           else
13694             abort ();
13695           /* Fall through.  */
13696           goto case_S;
13697         case 'S':
13698           if (l == 0)
13699             {
13700             case_S:
13701               if (intel_syntax)
13702                 break;
13703               if (sizeflag & SUFFIX_ALWAYS)
13704                 {
13705                   if (rex & REX_W)
13706                     *obufp++ = 'q';
13707                   else
13708                     {
13709                       if (sizeflag & DFLAG)
13710                         *obufp++ = 'l';
13711                       else
13712                         *obufp++ = 'w';
13713                       used_prefixes |= (prefixes & PREFIX_DATA);
13714                     }
13715                 }
13716             }
13717           else if (l == 1 && last[0] == 'L')
13718             {
13719               if (address_mode == mode_64bit
13720                   && !(prefixes & PREFIX_ADDR))
13721                 {
13722                   *obufp++ = 'a';
13723                   *obufp++ = 'b';
13724                   *obufp++ = 's';
13725                 }
13726
13727               goto case_S;
13728             }
13729           else
13730             abort ();
13731           break;
13732         case 'X':
13733           if (l != 0)
13734             abort ();
13735           if (need_vex
13736               ? vex.prefix == DATA_PREFIX_OPCODE
13737               : prefixes & PREFIX_DATA)
13738             {
13739               *obufp++ = 'd';
13740               used_prefixes |= PREFIX_DATA;
13741             }
13742           else
13743             *obufp++ = 's';
13744           break;
13745         case 'Y':
13746           if (l == 1 && last[0] == 'X')
13747             {
13748               if (!need_vex)
13749                 abort ();
13750               if (intel_syntax
13751                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13752                 break;
13753               switch (vex.length)
13754                 {
13755                 case 128:
13756                   *obufp++ = 'x';
13757                   break;
13758                 case 256:
13759                   *obufp++ = 'y';
13760                   break;
13761                 case 512:
13762                   if (!vex.evex)
13763                 default:
13764                     abort ();
13765                 }
13766             }
13767           else
13768             abort ();
13769           break;
13770         case 'W':
13771           if (l == 0)
13772             {
13773               /* operand size flag for cwtl, cbtw */
13774               USED_REX (REX_W);
13775               if (rex & REX_W)
13776                 {
13777                   if (intel_syntax)
13778                     *obufp++ = 'd';
13779                   else
13780                     *obufp++ = 'l';
13781                 }
13782               else if (sizeflag & DFLAG)
13783                 *obufp++ = 'w';
13784               else
13785                 *obufp++ = 'b';
13786               if (!(rex & REX_W))
13787                 used_prefixes |= (prefixes & PREFIX_DATA);
13788             }
13789           else if (l == 1)
13790             {
13791               if (!need_vex)
13792                 abort ();
13793               if (last[0] == 'X')
13794                 *obufp++ = vex.w ? 'd': 's';
13795               else if (last[0] == 'B')
13796                 *obufp++ = vex.w ? 'w': 'b';
13797               else
13798                 abort ();
13799             }
13800           else
13801             abort ();
13802           break;
13803         case '^':
13804           if (intel_syntax)
13805             break;
13806           if (isa64 == intel64 && (rex & REX_W))
13807             {
13808               USED_REX (REX_W);
13809               *obufp++ = 'q';
13810               break;
13811             }
13812           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13813             {
13814               if (sizeflag & DFLAG)
13815                 *obufp++ = 'l';
13816               else
13817                 *obufp++ = 'w';
13818               used_prefixes |= (prefixes & PREFIX_DATA);
13819             }
13820           break;
13821         case '@':
13822           if (intel_syntax)
13823             break;
13824           if (address_mode == mode_64bit
13825               && (isa64 == intel64
13826                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13827               *obufp++ = 'q';
13828           else if ((prefixes & PREFIX_DATA))
13829             {
13830               if (!(sizeflag & DFLAG))
13831                 *obufp++ = 'w';
13832               used_prefixes |= (prefixes & PREFIX_DATA);
13833             }
13834           break;
13835         }
13836
13837       if (len == l)
13838         len = l = 0;
13839     }
13840   *obufp = 0;
13841   mnemonicendp = obufp;
13842   return 0;
13843 }
13844
13845 static void
13846 oappend (const char *s)
13847 {
13848   obufp = stpcpy (obufp, s);
13849 }
13850
13851 static void
13852 append_seg (void)
13853 {
13854   /* Only print the active segment register.  */
13855   if (!active_seg_prefix)
13856     return;
13857
13858   used_prefixes |= active_seg_prefix;
13859   switch (active_seg_prefix)
13860     {
13861     case PREFIX_CS:
13862       oappend_maybe_intel ("%cs:");
13863       break;
13864     case PREFIX_DS:
13865       oappend_maybe_intel ("%ds:");
13866       break;
13867     case PREFIX_SS:
13868       oappend_maybe_intel ("%ss:");
13869       break;
13870     case PREFIX_ES:
13871       oappend_maybe_intel ("%es:");
13872       break;
13873     case PREFIX_FS:
13874       oappend_maybe_intel ("%fs:");
13875       break;
13876     case PREFIX_GS:
13877       oappend_maybe_intel ("%gs:");
13878       break;
13879     default:
13880       break;
13881     }
13882 }
13883
13884 static void
13885 OP_indirE (int bytemode, int sizeflag)
13886 {
13887   if (!intel_syntax)
13888     oappend ("*");
13889   OP_E (bytemode, sizeflag);
13890 }
13891
13892 static void
13893 print_operand_value (char *buf, int hex, bfd_vma disp)
13894 {
13895   if (address_mode == mode_64bit)
13896     {
13897       if (hex)
13898         {
13899           char tmp[30];
13900           int i;
13901           buf[0] = '0';
13902           buf[1] = 'x';
13903           sprintf_vma (tmp, disp);
13904           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13905           strcpy (buf + 2, tmp + i);
13906         }
13907       else
13908         {
13909           bfd_signed_vma v = disp;
13910           char tmp[30];
13911           int i;
13912           if (v < 0)
13913             {
13914               *(buf++) = '-';
13915               v = -disp;
13916               /* Check for possible overflow on 0x8000000000000000.  */
13917               if (v < 0)
13918                 {
13919                   strcpy (buf, "9223372036854775808");
13920                   return;
13921                 }
13922             }
13923           if (!v)
13924             {
13925               strcpy (buf, "0");
13926               return;
13927             }
13928
13929           i = 0;
13930           tmp[29] = 0;
13931           while (v)
13932             {
13933               tmp[28 - i] = (v % 10) + '0';
13934               v /= 10;
13935               i++;
13936             }
13937           strcpy (buf, tmp + 29 - i);
13938         }
13939     }
13940   else
13941     {
13942       if (hex)
13943         sprintf (buf, "0x%x", (unsigned int) disp);
13944       else
13945         sprintf (buf, "%d", (int) disp);
13946     }
13947 }
13948
13949 /* Put DISP in BUF as signed hex number.  */
13950
13951 static void
13952 print_displacement (char *buf, bfd_vma disp)
13953 {
13954   bfd_signed_vma val = disp;
13955   char tmp[30];
13956   int i, j = 0;
13957
13958   if (val < 0)
13959     {
13960       buf[j++] = '-';
13961       val = -disp;
13962
13963       /* Check for possible overflow.  */
13964       if (val < 0)
13965         {
13966           switch (address_mode)
13967             {
13968             case mode_64bit:
13969               strcpy (buf + j, "0x8000000000000000");
13970               break;
13971             case mode_32bit:
13972               strcpy (buf + j, "0x80000000");
13973               break;
13974             case mode_16bit:
13975               strcpy (buf + j, "0x8000");
13976               break;
13977             }
13978           return;
13979         }
13980     }
13981
13982   buf[j++] = '0';
13983   buf[j++] = 'x';
13984
13985   sprintf_vma (tmp, (bfd_vma) val);
13986   for (i = 0; tmp[i] == '0'; i++)
13987     continue;
13988   if (tmp[i] == '\0')
13989     i--;
13990   strcpy (buf + j, tmp + i);
13991 }
13992
13993 static void
13994 intel_operand_size (int bytemode, int sizeflag)
13995 {
13996   if (vex.evex
13997       && vex.b
13998       && (bytemode == x_mode
13999           || bytemode == evex_half_bcst_xmmq_mode))
14000     {
14001       if (vex.w)
14002         oappend ("QWORD PTR ");
14003       else
14004         oappend ("DWORD PTR ");
14005       return;
14006     }
14007   switch (bytemode)
14008     {
14009     case b_mode:
14010     case b_swap_mode:
14011     case dqb_mode:
14012     case db_mode:
14013       oappend ("BYTE PTR ");
14014       break;
14015     case w_mode:
14016     case dw_mode:
14017     case dqw_mode:
14018       oappend ("WORD PTR ");
14019       break;
14020     case indir_v_mode:
14021       if (address_mode == mode_64bit && isa64 == intel64)
14022         {
14023           oappend ("QWORD PTR ");
14024           break;
14025         }
14026       /* Fall through.  */
14027     case stack_v_mode:
14028       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14029         {
14030           oappend ("QWORD PTR ");
14031           break;
14032         }
14033       /* Fall through.  */
14034     case v_mode:
14035     case v_swap_mode:
14036     case dq_mode:
14037       USED_REX (REX_W);
14038       if (rex & REX_W)
14039         oappend ("QWORD PTR ");
14040       else
14041         {
14042           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14043             oappend ("DWORD PTR ");
14044           else
14045             oappend ("WORD PTR ");
14046           used_prefixes |= (prefixes & PREFIX_DATA);
14047         }
14048       break;
14049     case z_mode:
14050       if ((rex & REX_W) || (sizeflag & DFLAG))
14051         *obufp++ = 'D';
14052       oappend ("WORD PTR ");
14053       if (!(rex & REX_W))
14054         used_prefixes |= (prefixes & PREFIX_DATA);
14055       break;
14056     case a_mode:
14057       if (sizeflag & DFLAG)
14058         oappend ("QWORD PTR ");
14059       else
14060         oappend ("DWORD PTR ");
14061       used_prefixes |= (prefixes & PREFIX_DATA);
14062       break;
14063     case movsxd_mode:
14064       if (!(sizeflag & DFLAG) && isa64 == intel64)
14065         oappend ("WORD PTR ");
14066       else
14067         oappend ("DWORD PTR ");
14068       used_prefixes |= (prefixes & PREFIX_DATA);
14069       break;
14070     case d_mode:
14071     case d_scalar_swap_mode:
14072     case d_swap_mode:
14073     case dqd_mode:
14074       oappend ("DWORD PTR ");
14075       break;
14076     case q_mode:
14077     case q_scalar_swap_mode:
14078     case q_swap_mode:
14079       oappend ("QWORD PTR ");
14080       break;
14081     case m_mode:
14082       if (address_mode == mode_64bit)
14083         oappend ("QWORD PTR ");
14084       else
14085         oappend ("DWORD PTR ");
14086       break;
14087     case f_mode:
14088       if (sizeflag & DFLAG)
14089         oappend ("FWORD PTR ");
14090       else
14091         oappend ("DWORD PTR ");
14092       used_prefixes |= (prefixes & PREFIX_DATA);
14093       break;
14094     case t_mode:
14095       oappend ("TBYTE PTR ");
14096       break;
14097     case x_mode:
14098     case x_swap_mode:
14099     case evex_x_gscat_mode:
14100     case evex_x_nobcst_mode:
14101     case bw_unit_mode:
14102       if (need_vex)
14103         {
14104           switch (vex.length)
14105             {
14106             case 128:
14107               oappend ("XMMWORD PTR ");
14108               break;
14109             case 256:
14110               oappend ("YMMWORD PTR ");
14111               break;
14112             case 512:
14113               oappend ("ZMMWORD PTR ");
14114               break;
14115             default:
14116               abort ();
14117             }
14118         }
14119       else
14120         oappend ("XMMWORD PTR ");
14121       break;
14122     case xmm_mode:
14123       oappend ("XMMWORD PTR ");
14124       break;
14125     case ymm_mode:
14126       oappend ("YMMWORD PTR ");
14127       break;
14128     case xmmq_mode:
14129     case evex_half_bcst_xmmq_mode:
14130       if (!need_vex)
14131         abort ();
14132
14133       switch (vex.length)
14134         {
14135         case 128:
14136           oappend ("QWORD PTR ");
14137           break;
14138         case 256:
14139           oappend ("XMMWORD PTR ");
14140           break;
14141         case 512:
14142           oappend ("YMMWORD PTR ");
14143           break;
14144         default:
14145           abort ();
14146         }
14147       break;
14148     case xmm_mb_mode:
14149       if (!need_vex)
14150         abort ();
14151
14152       switch (vex.length)
14153         {
14154         case 128:
14155         case 256:
14156         case 512:
14157           oappend ("BYTE PTR ");
14158           break;
14159         default:
14160           abort ();
14161         }
14162       break;
14163     case xmm_mw_mode:
14164       if (!need_vex)
14165         abort ();
14166
14167       switch (vex.length)
14168         {
14169         case 128:
14170         case 256:
14171         case 512:
14172           oappend ("WORD PTR ");
14173           break;
14174         default:
14175           abort ();
14176         }
14177       break;
14178     case xmm_md_mode:
14179       if (!need_vex)
14180         abort ();
14181
14182       switch (vex.length)
14183         {
14184         case 128:
14185         case 256:
14186         case 512:
14187           oappend ("DWORD PTR ");
14188           break;
14189         default:
14190           abort ();
14191         }
14192       break;
14193     case xmm_mq_mode:
14194       if (!need_vex)
14195         abort ();
14196
14197       switch (vex.length)
14198         {
14199         case 128:
14200         case 256:
14201         case 512:
14202           oappend ("QWORD PTR ");
14203           break;
14204         default:
14205           abort ();
14206         }
14207       break;
14208     case xmmdw_mode:
14209       if (!need_vex)
14210         abort ();
14211
14212       switch (vex.length)
14213         {
14214         case 128:
14215           oappend ("WORD PTR ");
14216           break;
14217         case 256:
14218           oappend ("DWORD PTR ");
14219           break;
14220         case 512:
14221           oappend ("QWORD PTR ");
14222           break;
14223         default:
14224           abort ();
14225         }
14226       break;
14227     case xmmqd_mode:
14228       if (!need_vex)
14229         abort ();
14230
14231       switch (vex.length)
14232         {
14233         case 128:
14234           oappend ("DWORD PTR ");
14235           break;
14236         case 256:
14237           oappend ("QWORD PTR ");
14238           break;
14239         case 512:
14240           oappend ("XMMWORD PTR ");
14241           break;
14242         default:
14243           abort ();
14244         }
14245       break;
14246     case ymmq_mode:
14247       if (!need_vex)
14248         abort ();
14249
14250       switch (vex.length)
14251         {
14252         case 128:
14253           oappend ("QWORD PTR ");
14254           break;
14255         case 256:
14256           oappend ("YMMWORD PTR ");
14257           break;
14258         case 512:
14259           oappend ("ZMMWORD PTR ");
14260           break;
14261         default:
14262           abort ();
14263         }
14264       break;
14265     case ymmxmm_mode:
14266       if (!need_vex)
14267         abort ();
14268
14269       switch (vex.length)
14270         {
14271         case 128:
14272         case 256:
14273           oappend ("XMMWORD PTR ");
14274           break;
14275         default:
14276           abort ();
14277         }
14278       break;
14279     case o_mode:
14280       oappend ("OWORD PTR ");
14281       break;
14282     case vex_scalar_w_dq_mode:
14283       if (!need_vex)
14284         abort ();
14285
14286       if (vex.w)
14287         oappend ("QWORD PTR ");
14288       else
14289         oappend ("DWORD PTR ");
14290       break;
14291     case vex_vsib_d_w_dq_mode:
14292     case vex_vsib_q_w_dq_mode:
14293       if (!need_vex)
14294         abort ();
14295
14296       if (!vex.evex)
14297         {
14298           if (vex.w)
14299             oappend ("QWORD PTR ");
14300           else
14301             oappend ("DWORD PTR ");
14302         }
14303       else
14304         {
14305           switch (vex.length)
14306             {
14307             case 128:
14308               oappend ("XMMWORD PTR ");
14309               break;
14310             case 256:
14311               oappend ("YMMWORD PTR ");
14312               break;
14313             case 512:
14314               oappend ("ZMMWORD PTR ");
14315               break;
14316             default:
14317               abort ();
14318             }
14319         }
14320       break;
14321     case vex_vsib_q_w_d_mode:
14322     case vex_vsib_d_w_d_mode:
14323       if (!need_vex || !vex.evex)
14324         abort ();
14325
14326       switch (vex.length)
14327         {
14328         case 128:
14329           oappend ("QWORD PTR ");
14330           break;
14331         case 256:
14332           oappend ("XMMWORD PTR ");
14333           break;
14334         case 512:
14335           oappend ("YMMWORD PTR ");
14336           break;
14337         default:
14338           abort ();
14339         }
14340
14341       break;
14342     case mask_bd_mode:
14343       if (!need_vex || vex.length != 128)
14344         abort ();
14345       if (vex.w)
14346         oappend ("DWORD PTR ");
14347       else
14348         oappend ("BYTE PTR ");
14349       break;
14350     case mask_mode:
14351       if (!need_vex)
14352         abort ();
14353       if (vex.w)
14354         oappend ("QWORD PTR ");
14355       else
14356         oappend ("WORD PTR ");
14357       break;
14358     case v_bnd_mode:
14359     case v_bndmk_mode:
14360     default:
14361       break;
14362     }
14363 }
14364
14365 static void
14366 OP_E_register (int bytemode, int sizeflag)
14367 {
14368   int reg = modrm.rm;
14369   const char **names;
14370
14371   USED_REX (REX_B);
14372   if ((rex & REX_B))
14373     reg += 8;
14374
14375   if ((sizeflag & SUFFIX_ALWAYS)
14376       && (bytemode == b_swap_mode
14377           || bytemode == bnd_swap_mode
14378           || bytemode == v_swap_mode))
14379     swap_operand ();
14380
14381   switch (bytemode)
14382     {
14383     case b_mode:
14384     case b_swap_mode:
14385       if (reg & 4)
14386         USED_REX (0);
14387       if (rex)
14388         names = names8rex;
14389       else
14390         names = names8;
14391       break;
14392     case w_mode:
14393       names = names16;
14394       break;
14395     case d_mode:
14396     case dw_mode:
14397     case db_mode:
14398       names = names32;
14399       break;
14400     case q_mode:
14401       names = names64;
14402       break;
14403     case m_mode:
14404     case v_bnd_mode:
14405       names = address_mode == mode_64bit ? names64 : names32;
14406       break;
14407     case bnd_mode:
14408     case bnd_swap_mode:
14409       if (reg > 0x3)
14410         {
14411           oappend ("(bad)");
14412           return;
14413         }
14414       names = names_bnd;
14415       break;
14416     case indir_v_mode:
14417       if (address_mode == mode_64bit && isa64 == intel64)
14418         {
14419           names = names64;
14420           break;
14421         }
14422       /* Fall through.  */
14423     case stack_v_mode:
14424       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14425         {
14426           names = names64;
14427           break;
14428         }
14429       bytemode = v_mode;
14430       /* Fall through.  */
14431     case v_mode:
14432     case v_swap_mode:
14433     case dq_mode:
14434     case dqb_mode:
14435     case dqd_mode:
14436     case dqw_mode:
14437       USED_REX (REX_W);
14438       if (rex & REX_W)
14439         names = names64;
14440       else
14441         {
14442           if ((sizeflag & DFLAG)
14443               || (bytemode != v_mode
14444                   && bytemode != v_swap_mode))
14445             names = names32;
14446           else
14447             names = names16;
14448           used_prefixes |= (prefixes & PREFIX_DATA);
14449         }
14450       break;
14451     case movsxd_mode:
14452       if (!(sizeflag & DFLAG) && isa64 == intel64)
14453         names = names16;
14454       else
14455         names = names32;
14456       used_prefixes |= (prefixes & PREFIX_DATA);
14457       break;
14458     case va_mode:
14459       names = (address_mode == mode_64bit
14460                ? names64 : names32);
14461       if (!(prefixes & PREFIX_ADDR))
14462         names = (address_mode == mode_16bit
14463                      ? names16 : names);
14464       else
14465         {
14466           /* Remove "addr16/addr32".  */
14467           all_prefixes[last_addr_prefix] = 0;
14468           names = (address_mode != mode_32bit
14469                        ? names32 : names16);
14470           used_prefixes |= PREFIX_ADDR;
14471         }
14472       break;
14473     case mask_bd_mode:
14474     case mask_mode:
14475       if (reg > 0x7)
14476         {
14477           oappend ("(bad)");
14478           return;
14479         }
14480       names = names_mask;
14481       break;
14482     case 0:
14483       return;
14484     default:
14485       oappend (INTERNAL_DISASSEMBLER_ERROR);
14486       return;
14487     }
14488   oappend (names[reg]);
14489 }
14490
14491 static void
14492 OP_E_memory (int bytemode, int sizeflag)
14493 {
14494   bfd_vma disp = 0;
14495   int add = (rex & REX_B) ? 8 : 0;
14496   int riprel = 0;
14497   int shift;
14498
14499   if (vex.evex)
14500     {
14501       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14502       if (vex.b
14503           && bytemode != x_mode
14504           && bytemode != xmmq_mode
14505           && bytemode != evex_half_bcst_xmmq_mode)
14506         {
14507           BadOp ();
14508           return;
14509         }
14510       switch (bytemode)
14511         {
14512         case dqw_mode:
14513         case dw_mode:
14514         case xmm_mw_mode:
14515           shift = 1;
14516           break;
14517         case dqb_mode:
14518         case db_mode:
14519         case xmm_mb_mode:
14520           shift = 0;
14521           break;
14522         case dq_mode:
14523           if (address_mode != mode_64bit)
14524             {
14525         case dqd_mode:
14526         case xmm_md_mode:
14527         case d_mode:
14528         case d_swap_mode:
14529         case d_scalar_swap_mode:
14530               shift = 2;
14531               break;
14532             }
14533             /* fall through */
14534         case vex_scalar_w_dq_mode:
14535         case vex_vsib_d_w_dq_mode:
14536         case vex_vsib_d_w_d_mode:
14537         case vex_vsib_q_w_dq_mode:
14538         case vex_vsib_q_w_d_mode:
14539         case evex_x_gscat_mode:
14540           shift = vex.w ? 3 : 2;
14541           break;
14542         case x_mode:
14543         case evex_half_bcst_xmmq_mode:
14544         case xmmq_mode:
14545           if (vex.b)
14546             {
14547               shift = vex.w ? 3 : 2;
14548               break;
14549             }
14550           /* Fall through.  */
14551         case xmmqd_mode:
14552         case xmmdw_mode:
14553         case ymmq_mode:
14554         case evex_x_nobcst_mode:
14555         case x_swap_mode:
14556           switch (vex.length)
14557             {
14558             case 128:
14559               shift = 4;
14560               break;
14561             case 256:
14562               shift = 5;
14563               break;
14564             case 512:
14565               shift = 6;
14566               break;
14567             default:
14568               abort ();
14569             }
14570           /* Make necessary corrections to shift for modes that need it.  */
14571           if (bytemode == xmmq_mode
14572               || bytemode == evex_half_bcst_xmmq_mode
14573               || (bytemode == ymmq_mode && vex.length == 128))
14574             shift -= 1;
14575           else if (bytemode == xmmqd_mode)
14576             shift -= 2;
14577           else if (bytemode == xmmdw_mode)
14578             shift -= 3;
14579           break;
14580         case ymm_mode:
14581           shift = 5;
14582           break;
14583         case xmm_mode:
14584           shift = 4;
14585           break;
14586         case xmm_mq_mode:
14587         case q_mode:
14588         case q_swap_mode:
14589         case q_scalar_swap_mode:
14590           shift = 3;
14591           break;
14592         case bw_unit_mode:
14593           shift = vex.w ? 1 : 0;
14594           break;
14595         default:
14596           abort ();
14597         }
14598     }
14599   else
14600     shift = 0;
14601
14602   USED_REX (REX_B);
14603   if (intel_syntax)
14604     intel_operand_size (bytemode, sizeflag);
14605   append_seg ();
14606
14607   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14608     {
14609       /* 32/64 bit address mode */
14610       int havedisp;
14611       int havesib;
14612       int havebase;
14613       int haveindex;
14614       int needindex;
14615       int needaddr32;
14616       int base, rbase;
14617       int vindex = 0;
14618       int scale = 0;
14619       int addr32flag = !((sizeflag & AFLAG)
14620                          || bytemode == v_bnd_mode
14621                          || bytemode == v_bndmk_mode
14622                          || bytemode == bnd_mode
14623                          || bytemode == bnd_swap_mode);
14624       const char **indexes64 = names64;
14625       const char **indexes32 = names32;
14626
14627       havesib = 0;
14628       havebase = 1;
14629       haveindex = 0;
14630       base = modrm.rm;
14631
14632       if (base == 4)
14633         {
14634           havesib = 1;
14635           vindex = sib.index;
14636           USED_REX (REX_X);
14637           if (rex & REX_X)
14638             vindex += 8;
14639           switch (bytemode)
14640             {
14641             case vex_vsib_d_w_dq_mode:
14642             case vex_vsib_d_w_d_mode:
14643             case vex_vsib_q_w_dq_mode:
14644             case vex_vsib_q_w_d_mode:
14645               if (!need_vex)
14646                 abort ();
14647               if (vex.evex)
14648                 {
14649                   if (!vex.v)
14650                     vindex += 16;
14651                 }
14652
14653               haveindex = 1;
14654               switch (vex.length)
14655                 {
14656                 case 128:
14657                   indexes64 = indexes32 = names_xmm;
14658                   break;
14659                 case 256:
14660                   if (!vex.w
14661                       || bytemode == vex_vsib_q_w_dq_mode
14662                       || bytemode == vex_vsib_q_w_d_mode)
14663                     indexes64 = indexes32 = names_ymm;
14664                   else
14665                     indexes64 = indexes32 = names_xmm;
14666                   break;
14667                 case 512:
14668                   if (!vex.w
14669                       || bytemode == vex_vsib_q_w_dq_mode
14670                       || bytemode == vex_vsib_q_w_d_mode)
14671                     indexes64 = indexes32 = names_zmm;
14672                   else
14673                     indexes64 = indexes32 = names_ymm;
14674                   break;
14675                 default:
14676                   abort ();
14677                 }
14678               break;
14679             default:
14680               haveindex = vindex != 4;
14681               break;
14682             }
14683           scale = sib.scale;
14684           base = sib.base;
14685           codep++;
14686         }
14687       else
14688         {
14689           /* mandatory non-vector SIB must have sib */
14690           if (bytemode == vex_sibmem_mode)
14691             {
14692               oappend ("(bad)");
14693               return;
14694             }
14695         }
14696       rbase = base + add;
14697
14698       switch (modrm.mod)
14699         {
14700         case 0:
14701           if (base == 5)
14702             {
14703               havebase = 0;
14704               if (address_mode == mode_64bit && !havesib)
14705                 riprel = 1;
14706               disp = get32s ();
14707               if (riprel && bytemode == v_bndmk_mode)
14708                 {
14709                   oappend ("(bad)");
14710                   return;
14711                 }
14712             }
14713           break;
14714         case 1:
14715           FETCH_DATA (the_info, codep + 1);
14716           disp = *codep++;
14717           if ((disp & 0x80) != 0)
14718             disp -= 0x100;
14719           if (vex.evex && shift > 0)
14720             disp <<= shift;
14721           break;
14722         case 2:
14723           disp = get32s ();
14724           break;
14725         }
14726
14727       needindex = 0;
14728       needaddr32 = 0;
14729       if (havesib
14730           && !havebase
14731           && !haveindex
14732           && address_mode != mode_16bit)
14733         {
14734           if (address_mode == mode_64bit)
14735             {
14736               /* Display eiz instead of addr32.  */
14737               needindex = addr32flag;
14738               needaddr32 = 1;
14739             }
14740           else
14741             {
14742               /* In 32-bit mode, we need index register to tell [offset]
14743                  from [eiz*1 + offset].  */
14744               needindex = 1;
14745             }
14746         }
14747
14748       havedisp = (havebase
14749                   || needindex
14750                   || (havesib && (haveindex || scale != 0)));
14751
14752       if (!intel_syntax)
14753         if (modrm.mod != 0 || base == 5)
14754           {
14755             if (havedisp || riprel)
14756               print_displacement (scratchbuf, disp);
14757             else
14758               print_operand_value (scratchbuf, 1, disp);
14759             oappend (scratchbuf);
14760             if (riprel)
14761               {
14762                 set_op (disp, 1);
14763                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14764               }
14765           }
14766
14767       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14768           && (address_mode != mode_64bit
14769               || ((bytemode != v_bnd_mode)
14770                   && (bytemode != v_bndmk_mode)
14771                   && (bytemode != bnd_mode)
14772                   && (bytemode != bnd_swap_mode))))
14773         used_prefixes |= PREFIX_ADDR;
14774
14775       if (havedisp || (intel_syntax && riprel))
14776         {
14777           *obufp++ = open_char;
14778           if (intel_syntax && riprel)
14779             {
14780               set_op (disp, 1);
14781               oappend (!addr32flag ? "rip" : "eip");
14782             }
14783           *obufp = '\0';
14784           if (havebase)
14785             oappend (address_mode == mode_64bit && !addr32flag
14786                      ? names64[rbase] : names32[rbase]);
14787           if (havesib)
14788             {
14789               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14790                  print index to tell base + index from base.  */
14791               if (scale != 0
14792                   || needindex
14793                   || haveindex
14794                   || (havebase && base != ESP_REG_NUM))
14795                 {
14796                   if (!intel_syntax || havebase)
14797                     {
14798                       *obufp++ = separator_char;
14799                       *obufp = '\0';
14800                     }
14801                   if (haveindex)
14802                     oappend (address_mode == mode_64bit && !addr32flag
14803                              ? indexes64[vindex] : indexes32[vindex]);
14804                   else
14805                     oappend (address_mode == mode_64bit && !addr32flag
14806                              ? index64 : index32);
14807
14808                   *obufp++ = scale_char;
14809                   *obufp = '\0';
14810                   sprintf (scratchbuf, "%d", 1 << scale);
14811                   oappend (scratchbuf);
14812                 }
14813             }
14814           if (intel_syntax
14815               && (disp || modrm.mod != 0 || base == 5))
14816             {
14817               if (!havedisp || (bfd_signed_vma) disp >= 0)
14818                 {
14819                   *obufp++ = '+';
14820                   *obufp = '\0';
14821                 }
14822               else if (modrm.mod != 1 && disp != -disp)
14823                 {
14824                   *obufp++ = '-';
14825                   *obufp = '\0';
14826                   disp = - (bfd_signed_vma) disp;
14827                 }
14828
14829               if (havedisp)
14830                 print_displacement (scratchbuf, disp);
14831               else
14832                 print_operand_value (scratchbuf, 1, disp);
14833               oappend (scratchbuf);
14834             }
14835
14836           *obufp++ = close_char;
14837           *obufp = '\0';
14838         }
14839       else if (intel_syntax)
14840         {
14841           if (modrm.mod != 0 || base == 5)
14842             {
14843               if (!active_seg_prefix)
14844                 {
14845                   oappend (names_seg[ds_reg - es_reg]);
14846                   oappend (":");
14847                 }
14848               print_operand_value (scratchbuf, 1, disp);
14849               oappend (scratchbuf);
14850             }
14851         }
14852     }
14853   else if (bytemode == v_bnd_mode
14854            || bytemode == v_bndmk_mode
14855            || bytemode == bnd_mode
14856            || bytemode == bnd_swap_mode)
14857     {
14858       oappend ("(bad)");
14859       return;
14860     }
14861   else
14862     {
14863       /* 16 bit address mode */
14864       used_prefixes |= prefixes & PREFIX_ADDR;
14865       switch (modrm.mod)
14866         {
14867         case 0:
14868           if (modrm.rm == 6)
14869             {
14870               disp = get16 ();
14871               if ((disp & 0x8000) != 0)
14872                 disp -= 0x10000;
14873             }
14874           break;
14875         case 1:
14876           FETCH_DATA (the_info, codep + 1);
14877           disp = *codep++;
14878           if ((disp & 0x80) != 0)
14879             disp -= 0x100;
14880           if (vex.evex && shift > 0)
14881             disp <<= shift;
14882           break;
14883         case 2:
14884           disp = get16 ();
14885           if ((disp & 0x8000) != 0)
14886             disp -= 0x10000;
14887           break;
14888         }
14889
14890       if (!intel_syntax)
14891         if (modrm.mod != 0 || modrm.rm == 6)
14892           {
14893             print_displacement (scratchbuf, disp);
14894             oappend (scratchbuf);
14895           }
14896
14897       if (modrm.mod != 0 || modrm.rm != 6)
14898         {
14899           *obufp++ = open_char;
14900           *obufp = '\0';
14901           oappend (index16[modrm.rm]);
14902           if (intel_syntax
14903               && (disp || modrm.mod != 0 || modrm.rm == 6))
14904             {
14905               if ((bfd_signed_vma) disp >= 0)
14906                 {
14907                   *obufp++ = '+';
14908                   *obufp = '\0';
14909                 }
14910               else if (modrm.mod != 1)
14911                 {
14912                   *obufp++ = '-';
14913                   *obufp = '\0';
14914                   disp = - (bfd_signed_vma) disp;
14915                 }
14916
14917               print_displacement (scratchbuf, disp);
14918               oappend (scratchbuf);
14919             }
14920
14921           *obufp++ = close_char;
14922           *obufp = '\0';
14923         }
14924       else if (intel_syntax)
14925         {
14926           if (!active_seg_prefix)
14927             {
14928               oappend (names_seg[ds_reg - es_reg]);
14929               oappend (":");
14930             }
14931           print_operand_value (scratchbuf, 1, disp & 0xffff);
14932           oappend (scratchbuf);
14933         }
14934     }
14935   if (vex.evex && vex.b
14936       && (bytemode == x_mode
14937           || bytemode == xmmq_mode
14938           || bytemode == evex_half_bcst_xmmq_mode))
14939     {
14940       if (vex.w
14941           || bytemode == xmmq_mode
14942           || bytemode == evex_half_bcst_xmmq_mode)
14943         {
14944           switch (vex.length)
14945             {
14946             case 128:
14947               oappend ("{1to2}");
14948               break;
14949             case 256:
14950               oappend ("{1to4}");
14951               break;
14952             case 512:
14953               oappend ("{1to8}");
14954               break;
14955             default:
14956               abort ();
14957             }
14958         }
14959       else
14960         {
14961           switch (vex.length)
14962             {
14963             case 128:
14964               oappend ("{1to4}");
14965               break;
14966             case 256:
14967               oappend ("{1to8}");
14968               break;
14969             case 512:
14970               oappend ("{1to16}");
14971               break;
14972             default:
14973               abort ();
14974             }
14975         }
14976     }
14977 }
14978
14979 static void
14980 OP_E (int bytemode, int sizeflag)
14981 {
14982   /* Skip mod/rm byte.  */
14983   MODRM_CHECK;
14984   codep++;
14985
14986   if (modrm.mod == 3)
14987     OP_E_register (bytemode, sizeflag);
14988   else
14989     OP_E_memory (bytemode, sizeflag);
14990 }
14991
14992 static void
14993 OP_G (int bytemode, int sizeflag)
14994 {
14995   int add = 0;
14996   const char **names;
14997   USED_REX (REX_R);
14998   if (rex & REX_R)
14999     add += 8;
15000   switch (bytemode)
15001     {
15002     case b_mode:
15003       if (modrm.reg & 4)
15004         USED_REX (0);
15005       if (rex)
15006         oappend (names8rex[modrm.reg + add]);
15007       else
15008         oappend (names8[modrm.reg + add]);
15009       break;
15010     case w_mode:
15011       oappend (names16[modrm.reg + add]);
15012       break;
15013     case d_mode:
15014     case db_mode:
15015     case dw_mode:
15016       oappend (names32[modrm.reg + add]);
15017       break;
15018     case q_mode:
15019       oappend (names64[modrm.reg + add]);
15020       break;
15021     case bnd_mode:
15022       if (modrm.reg > 0x3)
15023         {
15024           oappend ("(bad)");
15025           return;
15026         }
15027       oappend (names_bnd[modrm.reg]);
15028       break;
15029     case v_mode:
15030     case dq_mode:
15031     case dqb_mode:
15032     case dqd_mode:
15033     case dqw_mode:
15034     case movsxd_mode:
15035       USED_REX (REX_W);
15036       if (rex & REX_W)
15037         oappend (names64[modrm.reg + add]);
15038       else
15039         {
15040           if ((sizeflag & DFLAG)
15041               || (bytemode != v_mode && bytemode != movsxd_mode))
15042             oappend (names32[modrm.reg + add]);
15043           else
15044             oappend (names16[modrm.reg + add]);
15045           used_prefixes |= (prefixes & PREFIX_DATA);
15046         }
15047       break;
15048     case va_mode:
15049       names = (address_mode == mode_64bit
15050                ? names64 : names32);
15051       if (!(prefixes & PREFIX_ADDR))
15052         {
15053           if (address_mode == mode_16bit)
15054             names = names16;
15055         }
15056       else
15057         {
15058           /* Remove "addr16/addr32".  */
15059           all_prefixes[last_addr_prefix] = 0;
15060           names = (address_mode != mode_32bit
15061                        ? names32 : names16);
15062           used_prefixes |= PREFIX_ADDR;
15063         }
15064       oappend (names[modrm.reg + add]);
15065       break;
15066     case m_mode:
15067       if (address_mode == mode_64bit)
15068         oappend (names64[modrm.reg + add]);
15069       else
15070         oappend (names32[modrm.reg + add]);
15071       break;
15072     case mask_bd_mode:
15073     case mask_mode:
15074       if ((modrm.reg + add) > 0x7)
15075         {
15076           oappend ("(bad)");
15077           return;
15078         }
15079       oappend (names_mask[modrm.reg + add]);
15080       break;
15081     default:
15082       oappend (INTERNAL_DISASSEMBLER_ERROR);
15083       break;
15084     }
15085 }
15086
15087 static bfd_vma
15088 get64 (void)
15089 {
15090   bfd_vma x;
15091 #ifdef BFD64
15092   unsigned int a;
15093   unsigned int b;
15094
15095   FETCH_DATA (the_info, codep + 8);
15096   a = *codep++ & 0xff;
15097   a |= (*codep++ & 0xff) << 8;
15098   a |= (*codep++ & 0xff) << 16;
15099   a |= (*codep++ & 0xffu) << 24;
15100   b = *codep++ & 0xff;
15101   b |= (*codep++ & 0xff) << 8;
15102   b |= (*codep++ & 0xff) << 16;
15103   b |= (*codep++ & 0xffu) << 24;
15104   x = a + ((bfd_vma) b << 32);
15105 #else
15106   abort ();
15107   x = 0;
15108 #endif
15109   return x;
15110 }
15111
15112 static bfd_signed_vma
15113 get32 (void)
15114 {
15115   bfd_signed_vma x = 0;
15116
15117   FETCH_DATA (the_info, codep + 4);
15118   x = *codep++ & (bfd_signed_vma) 0xff;
15119   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15120   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15121   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15122   return x;
15123 }
15124
15125 static bfd_signed_vma
15126 get32s (void)
15127 {
15128   bfd_signed_vma x = 0;
15129
15130   FETCH_DATA (the_info, codep + 4);
15131   x = *codep++ & (bfd_signed_vma) 0xff;
15132   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15133   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15134   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15135
15136   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15137
15138   return x;
15139 }
15140
15141 static int
15142 get16 (void)
15143 {
15144   int x = 0;
15145
15146   FETCH_DATA (the_info, codep + 2);
15147   x = *codep++ & 0xff;
15148   x |= (*codep++ & 0xff) << 8;
15149   return x;
15150 }
15151
15152 static void
15153 set_op (bfd_vma op, int riprel)
15154 {
15155   op_index[op_ad] = op_ad;
15156   if (address_mode == mode_64bit)
15157     {
15158       op_address[op_ad] = op;
15159       op_riprel[op_ad] = riprel;
15160     }
15161   else
15162     {
15163       /* Mask to get a 32-bit address.  */
15164       op_address[op_ad] = op & 0xffffffff;
15165       op_riprel[op_ad] = riprel & 0xffffffff;
15166     }
15167 }
15168
15169 static void
15170 OP_REG (int code, int sizeflag)
15171 {
15172   const char *s;
15173   int add;
15174
15175   switch (code)
15176     {
15177     case es_reg: case ss_reg: case cs_reg:
15178     case ds_reg: case fs_reg: case gs_reg:
15179       oappend (names_seg[code - es_reg]);
15180       return;
15181     }
15182
15183   USED_REX (REX_B);
15184   if (rex & REX_B)
15185     add = 8;
15186   else
15187     add = 0;
15188
15189   switch (code)
15190     {
15191     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15192     case sp_reg: case bp_reg: case si_reg: case di_reg:
15193       s = names16[code - ax_reg + add];
15194       break;
15195     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
15196       USED_REX (0);
15197       /* Fall through.  */
15198     case al_reg: case cl_reg: case dl_reg: case bl_reg:
15199       if (rex)
15200         s = names8rex[code - al_reg + add];
15201       else
15202         s = names8[code - al_reg];
15203       break;
15204     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15205     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15206       if (address_mode == mode_64bit
15207           && ((sizeflag & DFLAG) || (rex & REX_W)))
15208         {
15209           s = names64[code - rAX_reg + add];
15210           break;
15211         }
15212       code += eAX_reg - rAX_reg;
15213       /* Fall through.  */
15214     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15215     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15216       USED_REX (REX_W);
15217       if (rex & REX_W)
15218         s = names64[code - eAX_reg + add];
15219       else
15220         {
15221           if (sizeflag & DFLAG)
15222             s = names32[code - eAX_reg + add];
15223           else
15224             s = names16[code - eAX_reg + add];
15225           used_prefixes |= (prefixes & PREFIX_DATA);
15226         }
15227       break;
15228     default:
15229       s = INTERNAL_DISASSEMBLER_ERROR;
15230       break;
15231     }
15232   oappend (s);
15233 }
15234
15235 static void
15236 OP_IMREG (int code, int sizeflag)
15237 {
15238   const char *s;
15239
15240   switch (code)
15241     {
15242     case indir_dx_reg:
15243       if (intel_syntax)
15244         s = "dx";
15245       else
15246         s = "(%dx)";
15247       break;
15248     case al_reg: case cl_reg:
15249       s = names8[code - al_reg];
15250       break;
15251     case eAX_reg:
15252       USED_REX (REX_W);
15253       if (rex & REX_W)
15254         {
15255           s = *names64;
15256           break;
15257         }
15258       /* Fall through.  */
15259     case z_mode_ax_reg:
15260       if ((rex & REX_W) || (sizeflag & DFLAG))
15261         s = *names32;
15262       else
15263         s = *names16;
15264       if (!(rex & REX_W))
15265         used_prefixes |= (prefixes & PREFIX_DATA);
15266       break;
15267     default:
15268       s = INTERNAL_DISASSEMBLER_ERROR;
15269       break;
15270     }
15271   oappend (s);
15272 }
15273
15274 static void
15275 OP_I (int bytemode, int sizeflag)
15276 {
15277   bfd_signed_vma op;
15278   bfd_signed_vma mask = -1;
15279
15280   switch (bytemode)
15281     {
15282     case b_mode:
15283       FETCH_DATA (the_info, codep + 1);
15284       op = *codep++;
15285       mask = 0xff;
15286       break;
15287     case v_mode:
15288       USED_REX (REX_W);
15289       if (rex & REX_W)
15290         op = get32s ();
15291       else
15292         {
15293           if (sizeflag & DFLAG)
15294             {
15295               op = get32 ();
15296               mask = 0xffffffff;
15297             }
15298           else
15299             {
15300               op = get16 ();
15301               mask = 0xfffff;
15302             }
15303           used_prefixes |= (prefixes & PREFIX_DATA);
15304         }
15305       break;
15306     case d_mode:
15307       mask = 0xffffffff;
15308       op = get32 ();
15309       break;
15310     case w_mode:
15311       mask = 0xfffff;
15312       op = get16 ();
15313       break;
15314     case const_1_mode:
15315       if (intel_syntax)
15316         oappend ("1");
15317       return;
15318     default:
15319       oappend (INTERNAL_DISASSEMBLER_ERROR);
15320       return;
15321     }
15322
15323   op &= mask;
15324   scratchbuf[0] = '$';
15325   print_operand_value (scratchbuf + 1, 1, op);
15326   oappend_maybe_intel (scratchbuf);
15327   scratchbuf[0] = '\0';
15328 }
15329
15330 static void
15331 OP_I64 (int bytemode, int sizeflag)
15332 {
15333   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
15334     {
15335       OP_I (bytemode, sizeflag);
15336       return;
15337     }
15338
15339   USED_REX (REX_W);
15340
15341   scratchbuf[0] = '$';
15342   print_operand_value (scratchbuf + 1, 1, get64 ());
15343   oappend_maybe_intel (scratchbuf);
15344   scratchbuf[0] = '\0';
15345 }
15346
15347 static void
15348 OP_sI (int bytemode, int sizeflag)
15349 {
15350   bfd_signed_vma op;
15351
15352   switch (bytemode)
15353     {
15354     case b_mode:
15355     case b_T_mode:
15356       FETCH_DATA (the_info, codep + 1);
15357       op = *codep++;
15358       if ((op & 0x80) != 0)
15359         op -= 0x100;
15360       if (bytemode == b_T_mode)
15361         {
15362           if (address_mode != mode_64bit
15363               || !((sizeflag & DFLAG) || (rex & REX_W)))
15364             {
15365               /* The operand-size prefix is overridden by a REX prefix.  */
15366               if ((sizeflag & DFLAG) || (rex & REX_W))
15367                 op &= 0xffffffff;
15368               else
15369                 op &= 0xffff;
15370           }
15371         }
15372       else
15373         {
15374           if (!(rex & REX_W))
15375             {
15376               if (sizeflag & DFLAG)
15377                 op &= 0xffffffff;
15378               else
15379                 op &= 0xffff;
15380             }
15381         }
15382       break;
15383     case v_mode:
15384       /* The operand-size prefix is overridden by a REX prefix.  */
15385       if ((sizeflag & DFLAG) || (rex & REX_W))
15386         op = get32s ();
15387       else
15388         op = get16 ();
15389       break;
15390     default:
15391       oappend (INTERNAL_DISASSEMBLER_ERROR);
15392       return;
15393     }
15394
15395   scratchbuf[0] = '$';
15396   print_operand_value (scratchbuf + 1, 1, op);
15397   oappend_maybe_intel (scratchbuf);
15398 }
15399
15400 static void
15401 OP_J (int bytemode, int sizeflag)
15402 {
15403   bfd_vma disp;
15404   bfd_vma mask = -1;
15405   bfd_vma segment = 0;
15406
15407   switch (bytemode)
15408     {
15409     case b_mode:
15410       FETCH_DATA (the_info, codep + 1);
15411       disp = *codep++;
15412       if ((disp & 0x80) != 0)
15413         disp -= 0x100;
15414       break;
15415     case v_mode:
15416       if (isa64 != intel64)
15417     case dqw_mode:
15418         USED_REX (REX_W);
15419       if ((sizeflag & DFLAG)
15420           || (address_mode == mode_64bit
15421               && ((isa64 == intel64 && bytemode != dqw_mode)
15422                   || (rex & REX_W))))
15423         disp = get32s ();
15424       else
15425         {
15426           disp = get16 ();
15427           if ((disp & 0x8000) != 0)
15428             disp -= 0x10000;
15429           /* In 16bit mode, address is wrapped around at 64k within
15430              the same segment.  Otherwise, a data16 prefix on a jump
15431              instruction means that the pc is masked to 16 bits after
15432              the displacement is added!  */
15433           mask = 0xffff;
15434           if ((prefixes & PREFIX_DATA) == 0)
15435             segment = ((start_pc + (codep - start_codep))
15436                        & ~((bfd_vma) 0xffff));
15437         }
15438       if (address_mode != mode_64bit
15439           || (isa64 != intel64 && !(rex & REX_W)))
15440         used_prefixes |= (prefixes & PREFIX_DATA);
15441       break;
15442     default:
15443       oappend (INTERNAL_DISASSEMBLER_ERROR);
15444       return;
15445     }
15446   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15447   set_op (disp, 0);
15448   print_operand_value (scratchbuf, 1, disp);
15449   oappend (scratchbuf);
15450 }
15451
15452 static void
15453 OP_SEG (int bytemode, int sizeflag)
15454 {
15455   if (bytemode == w_mode)
15456     oappend (names_seg[modrm.reg]);
15457   else
15458     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15459 }
15460
15461 static void
15462 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15463 {
15464   int seg, offset;
15465
15466   if (sizeflag & DFLAG)
15467     {
15468       offset = get32 ();
15469       seg = get16 ();
15470     }
15471   else
15472     {
15473       offset = get16 ();
15474       seg = get16 ();
15475     }
15476   used_prefixes |= (prefixes & PREFIX_DATA);
15477   if (intel_syntax)
15478     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15479   else
15480     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15481   oappend (scratchbuf);
15482 }
15483
15484 static void
15485 OP_OFF (int bytemode, int sizeflag)
15486 {
15487   bfd_vma off;
15488
15489   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15490     intel_operand_size (bytemode, sizeflag);
15491   append_seg ();
15492
15493   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15494     off = get32 ();
15495   else
15496     off = get16 ();
15497
15498   if (intel_syntax)
15499     {
15500       if (!active_seg_prefix)
15501         {
15502           oappend (names_seg[ds_reg - es_reg]);
15503           oappend (":");
15504         }
15505     }
15506   print_operand_value (scratchbuf, 1, off);
15507   oappend (scratchbuf);
15508 }
15509
15510 static void
15511 OP_OFF64 (int bytemode, int sizeflag)
15512 {
15513   bfd_vma off;
15514
15515   if (address_mode != mode_64bit
15516       || (prefixes & PREFIX_ADDR))
15517     {
15518       OP_OFF (bytemode, sizeflag);
15519       return;
15520     }
15521
15522   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15523     intel_operand_size (bytemode, sizeflag);
15524   append_seg ();
15525
15526   off = get64 ();
15527
15528   if (intel_syntax)
15529     {
15530       if (!active_seg_prefix)
15531         {
15532           oappend (names_seg[ds_reg - es_reg]);
15533           oappend (":");
15534         }
15535     }
15536   print_operand_value (scratchbuf, 1, off);
15537   oappend (scratchbuf);
15538 }
15539
15540 static void
15541 ptr_reg (int code, int sizeflag)
15542 {
15543   const char *s;
15544
15545   *obufp++ = open_char;
15546   used_prefixes |= (prefixes & PREFIX_ADDR);
15547   if (address_mode == mode_64bit)
15548     {
15549       if (!(sizeflag & AFLAG))
15550         s = names32[code - eAX_reg];
15551       else
15552         s = names64[code - eAX_reg];
15553     }
15554   else if (sizeflag & AFLAG)
15555     s = names32[code - eAX_reg];
15556   else
15557     s = names16[code - eAX_reg];
15558   oappend (s);
15559   *obufp++ = close_char;
15560   *obufp = 0;
15561 }
15562
15563 static void
15564 OP_ESreg (int code, int sizeflag)
15565 {
15566   if (intel_syntax)
15567     {
15568       switch (codep[-1])
15569         {
15570         case 0x6d:      /* insw/insl */
15571           intel_operand_size (z_mode, sizeflag);
15572           break;
15573         case 0xa5:      /* movsw/movsl/movsq */
15574         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15575         case 0xab:      /* stosw/stosl */
15576         case 0xaf:      /* scasw/scasl */
15577           intel_operand_size (v_mode, sizeflag);
15578           break;
15579         default:
15580           intel_operand_size (b_mode, sizeflag);
15581         }
15582     }
15583   oappend_maybe_intel ("%es:");
15584   ptr_reg (code, sizeflag);
15585 }
15586
15587 static void
15588 OP_DSreg (int code, int sizeflag)
15589 {
15590   if (intel_syntax)
15591     {
15592       switch (codep[-1])
15593         {
15594         case 0x6f:      /* outsw/outsl */
15595           intel_operand_size (z_mode, sizeflag);
15596           break;
15597         case 0xa5:      /* movsw/movsl/movsq */
15598         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15599         case 0xad:      /* lodsw/lodsl/lodsq */
15600           intel_operand_size (v_mode, sizeflag);
15601           break;
15602         default:
15603           intel_operand_size (b_mode, sizeflag);
15604         }
15605     }
15606   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15607      default segment register DS is printed.  */
15608   if (!active_seg_prefix)
15609     active_seg_prefix = PREFIX_DS;
15610   append_seg ();
15611   ptr_reg (code, sizeflag);
15612 }
15613
15614 static void
15615 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15616 {
15617   int add;
15618   if (rex & REX_R)
15619     {
15620       USED_REX (REX_R);
15621       add = 8;
15622     }
15623   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15624     {
15625       all_prefixes[last_lock_prefix] = 0;
15626       used_prefixes |= PREFIX_LOCK;
15627       add = 8;
15628     }
15629   else
15630     add = 0;
15631   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15632   oappend_maybe_intel (scratchbuf);
15633 }
15634
15635 static void
15636 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15637 {
15638   int add;
15639   USED_REX (REX_R);
15640   if (rex & REX_R)
15641     add = 8;
15642   else
15643     add = 0;
15644   if (intel_syntax)
15645     sprintf (scratchbuf, "db%d", modrm.reg + add);
15646   else
15647     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15648   oappend (scratchbuf);
15649 }
15650
15651 static void
15652 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15653 {
15654   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15655   oappend_maybe_intel (scratchbuf);
15656 }
15657
15658 static void
15659 OP_R (int bytemode, int sizeflag)
15660 {
15661   /* Skip mod/rm byte.  */
15662   MODRM_CHECK;
15663   codep++;
15664   OP_E_register (bytemode, sizeflag);
15665 }
15666
15667 static void
15668 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15669 {
15670   int reg = modrm.reg;
15671   const char **names;
15672
15673   used_prefixes |= (prefixes & PREFIX_DATA);
15674   if (prefixes & PREFIX_DATA)
15675     {
15676       names = names_xmm;
15677       USED_REX (REX_R);
15678       if (rex & REX_R)
15679         reg += 8;
15680     }
15681   else
15682     names = names_mm;
15683   oappend (names[reg]);
15684 }
15685
15686 static void
15687 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15688 {
15689   int reg = modrm.reg;
15690   const char **names;
15691
15692   USED_REX (REX_R);
15693   if (rex & REX_R)
15694     reg += 8;
15695   if (vex.evex)
15696     {
15697       if (!vex.r)
15698         reg += 16;
15699     }
15700
15701   if (need_vex
15702       && bytemode != xmm_mode
15703       && bytemode != xmmq_mode
15704       && bytemode != evex_half_bcst_xmmq_mode
15705       && bytemode != ymm_mode
15706       && bytemode != tmm_mode
15707       && bytemode != scalar_mode)
15708     {
15709       switch (vex.length)
15710         {
15711         case 128:
15712           names = names_xmm;
15713           break;
15714         case 256:
15715           if (vex.w
15716               || (bytemode != vex_vsib_q_w_dq_mode
15717                   && bytemode != vex_vsib_q_w_d_mode))
15718             names = names_ymm;
15719           else
15720             names = names_xmm;
15721           break;
15722         case 512:
15723           names = names_zmm;
15724           break;
15725         default:
15726           abort ();
15727         }
15728     }
15729   else if (bytemode == xmmq_mode
15730            || bytemode == evex_half_bcst_xmmq_mode)
15731     {
15732       switch (vex.length)
15733         {
15734         case 128:
15735         case 256:
15736           names = names_xmm;
15737           break;
15738         case 512:
15739           names = names_ymm;
15740           break;
15741         default:
15742           abort ();
15743         }
15744     }
15745   else if (bytemode == tmm_mode)
15746     {
15747       modrm.reg = reg;
15748       if (reg >= 8)
15749         {
15750           oappend ("(bad)");
15751           return;
15752         }
15753       names = names_tmm;
15754     }
15755   else if (bytemode == ymm_mode)
15756     names = names_ymm;
15757   else
15758     names = names_xmm;
15759   oappend (names[reg]);
15760 }
15761
15762 static void
15763 OP_EM (int bytemode, int sizeflag)
15764 {
15765   int reg;
15766   const char **names;
15767
15768   if (modrm.mod != 3)
15769     {
15770       if (intel_syntax
15771           && (bytemode == v_mode || bytemode == v_swap_mode))
15772         {
15773           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15774           used_prefixes |= (prefixes & PREFIX_DATA);
15775         }
15776       OP_E (bytemode, sizeflag);
15777       return;
15778     }
15779
15780   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15781     swap_operand ();
15782
15783   /* Skip mod/rm byte.  */
15784   MODRM_CHECK;
15785   codep++;
15786   used_prefixes |= (prefixes & PREFIX_DATA);
15787   reg = modrm.rm;
15788   if (prefixes & PREFIX_DATA)
15789     {
15790       names = names_xmm;
15791       USED_REX (REX_B);
15792       if (rex & REX_B)
15793         reg += 8;
15794     }
15795   else
15796     names = names_mm;
15797   oappend (names[reg]);
15798 }
15799
15800 /* cvt* are the only instructions in sse2 which have
15801    both SSE and MMX operands and also have 0x66 prefix
15802    in their opcode. 0x66 was originally used to differentiate
15803    between SSE and MMX instruction(operands). So we have to handle the
15804    cvt* separately using OP_EMC and OP_MXC */
15805 static void
15806 OP_EMC (int bytemode, int sizeflag)
15807 {
15808   if (modrm.mod != 3)
15809     {
15810       if (intel_syntax && bytemode == v_mode)
15811         {
15812           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15813           used_prefixes |= (prefixes & PREFIX_DATA);
15814         }
15815       OP_E (bytemode, sizeflag);
15816       return;
15817     }
15818
15819   /* Skip mod/rm byte.  */
15820   MODRM_CHECK;
15821   codep++;
15822   used_prefixes |= (prefixes & PREFIX_DATA);
15823   oappend (names_mm[modrm.rm]);
15824 }
15825
15826 static void
15827 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15828 {
15829   used_prefixes |= (prefixes & PREFIX_DATA);
15830   oappend (names_mm[modrm.reg]);
15831 }
15832
15833 static void
15834 OP_EX (int bytemode, int sizeflag)
15835 {
15836   int reg;
15837   const char **names;
15838
15839   /* Skip mod/rm byte.  */
15840   MODRM_CHECK;
15841   codep++;
15842
15843   if (modrm.mod != 3)
15844     {
15845       OP_E_memory (bytemode, sizeflag);
15846       return;
15847     }
15848
15849   reg = modrm.rm;
15850   USED_REX (REX_B);
15851   if (rex & REX_B)
15852     reg += 8;
15853   if (vex.evex)
15854     {
15855       USED_REX (REX_X);
15856       if ((rex & REX_X))
15857         reg += 16;
15858     }
15859
15860   if ((sizeflag & SUFFIX_ALWAYS)
15861       && (bytemode == x_swap_mode
15862           || bytemode == d_swap_mode
15863           || bytemode == d_scalar_swap_mode
15864           || bytemode == q_swap_mode
15865           || bytemode == q_scalar_swap_mode))
15866     swap_operand ();
15867
15868   if (need_vex
15869       && bytemode != xmm_mode
15870       && bytemode != xmmdw_mode
15871       && bytemode != xmmqd_mode
15872       && bytemode != xmm_mb_mode
15873       && bytemode != xmm_mw_mode
15874       && bytemode != xmm_md_mode
15875       && bytemode != xmm_mq_mode
15876       && bytemode != xmmq_mode
15877       && bytemode != evex_half_bcst_xmmq_mode
15878       && bytemode != ymm_mode
15879       && bytemode != tmm_mode
15880       && bytemode != d_scalar_swap_mode
15881       && bytemode != q_scalar_swap_mode
15882       && bytemode != vex_scalar_w_dq_mode)
15883     {
15884       switch (vex.length)
15885         {
15886         case 128:
15887           names = names_xmm;
15888           break;
15889         case 256:
15890           names = names_ymm;
15891           break;
15892         case 512:
15893           names = names_zmm;
15894           break;
15895         default:
15896           abort ();
15897         }
15898     }
15899   else if (bytemode == xmmq_mode
15900            || bytemode == evex_half_bcst_xmmq_mode)
15901     {
15902       switch (vex.length)
15903         {
15904         case 128:
15905         case 256:
15906           names = names_xmm;
15907           break;
15908         case 512:
15909           names = names_ymm;
15910           break;
15911         default:
15912           abort ();
15913         }
15914     }
15915   else if (bytemode == tmm_mode)
15916     {
15917       modrm.rm = reg;
15918       if (reg >= 8)
15919         {
15920           oappend ("(bad)");
15921           return;
15922         }
15923       names = names_tmm;
15924     }
15925   else if (bytemode == ymm_mode)
15926     names = names_ymm;
15927   else
15928     names = names_xmm;
15929   oappend (names[reg]);
15930 }
15931
15932 static void
15933 OP_MS (int bytemode, int sizeflag)
15934 {
15935   if (modrm.mod == 3)
15936     OP_EM (bytemode, sizeflag);
15937   else
15938     BadOp ();
15939 }
15940
15941 static void
15942 OP_XS (int bytemode, int sizeflag)
15943 {
15944   if (modrm.mod == 3)
15945     OP_EX (bytemode, sizeflag);
15946   else
15947     BadOp ();
15948 }
15949
15950 static void
15951 OP_M (int bytemode, int sizeflag)
15952 {
15953   if (modrm.mod == 3)
15954     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15955     BadOp ();
15956   else
15957     OP_E (bytemode, sizeflag);
15958 }
15959
15960 static void
15961 OP_0f07 (int bytemode, int sizeflag)
15962 {
15963   if (modrm.mod != 3 || modrm.rm != 0)
15964     BadOp ();
15965   else
15966     OP_E (bytemode, sizeflag);
15967 }
15968
15969 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15970    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15971
15972 static void
15973 NOP_Fixup1 (int bytemode, int sizeflag)
15974 {
15975   if ((prefixes & PREFIX_DATA) != 0
15976       || (rex != 0
15977           && rex != 0x48
15978           && address_mode == mode_64bit))
15979     OP_REG (bytemode, sizeflag);
15980   else
15981     strcpy (obuf, "nop");
15982 }
15983
15984 static void
15985 NOP_Fixup2 (int bytemode, int sizeflag)
15986 {
15987   if ((prefixes & PREFIX_DATA) != 0
15988       || (rex != 0
15989           && rex != 0x48
15990           && address_mode == mode_64bit))
15991     OP_IMREG (bytemode, sizeflag);
15992 }
15993
15994 static const char *const Suffix3DNow[] = {
15995 /* 00 */        NULL,           NULL,           NULL,           NULL,
15996 /* 04 */        NULL,           NULL,           NULL,           NULL,
15997 /* 08 */        NULL,           NULL,           NULL,           NULL,
15998 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15999 /* 10 */        NULL,           NULL,           NULL,           NULL,
16000 /* 14 */        NULL,           NULL,           NULL,           NULL,
16001 /* 18 */        NULL,           NULL,           NULL,           NULL,
16002 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16003 /* 20 */        NULL,           NULL,           NULL,           NULL,
16004 /* 24 */        NULL,           NULL,           NULL,           NULL,
16005 /* 28 */        NULL,           NULL,           NULL,           NULL,
16006 /* 2C */        NULL,           NULL,           NULL,           NULL,
16007 /* 30 */        NULL,           NULL,           NULL,           NULL,
16008 /* 34 */        NULL,           NULL,           NULL,           NULL,
16009 /* 38 */        NULL,           NULL,           NULL,           NULL,
16010 /* 3C */        NULL,           NULL,           NULL,           NULL,
16011 /* 40 */        NULL,           NULL,           NULL,           NULL,
16012 /* 44 */        NULL,           NULL,           NULL,           NULL,
16013 /* 48 */        NULL,           NULL,           NULL,           NULL,
16014 /* 4C */        NULL,           NULL,           NULL,           NULL,
16015 /* 50 */        NULL,           NULL,           NULL,           NULL,
16016 /* 54 */        NULL,           NULL,           NULL,           NULL,
16017 /* 58 */        NULL,           NULL,           NULL,           NULL,
16018 /* 5C */        NULL,           NULL,           NULL,           NULL,
16019 /* 60 */        NULL,           NULL,           NULL,           NULL,
16020 /* 64 */        NULL,           NULL,           NULL,           NULL,
16021 /* 68 */        NULL,           NULL,           NULL,           NULL,
16022 /* 6C */        NULL,           NULL,           NULL,           NULL,
16023 /* 70 */        NULL,           NULL,           NULL,           NULL,
16024 /* 74 */        NULL,           NULL,           NULL,           NULL,
16025 /* 78 */        NULL,           NULL,           NULL,           NULL,
16026 /* 7C */        NULL,           NULL,           NULL,           NULL,
16027 /* 80 */        NULL,           NULL,           NULL,           NULL,
16028 /* 84 */        NULL,           NULL,           NULL,           NULL,
16029 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16030 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16031 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16032 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16033 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16034 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16035 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16036 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16037 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16038 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16039 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16040 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16041 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16042 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16043 /* C0 */        NULL,           NULL,           NULL,           NULL,
16044 /* C4 */        NULL,           NULL,           NULL,           NULL,
16045 /* C8 */        NULL,           NULL,           NULL,           NULL,
16046 /* CC */        NULL,           NULL,           NULL,           NULL,
16047 /* D0 */        NULL,           NULL,           NULL,           NULL,
16048 /* D4 */        NULL,           NULL,           NULL,           NULL,
16049 /* D8 */        NULL,           NULL,           NULL,           NULL,
16050 /* DC */        NULL,           NULL,           NULL,           NULL,
16051 /* E0 */        NULL,           NULL,           NULL,           NULL,
16052 /* E4 */        NULL,           NULL,           NULL,           NULL,
16053 /* E8 */        NULL,           NULL,           NULL,           NULL,
16054 /* EC */        NULL,           NULL,           NULL,           NULL,
16055 /* F0 */        NULL,           NULL,           NULL,           NULL,
16056 /* F4 */        NULL,           NULL,           NULL,           NULL,
16057 /* F8 */        NULL,           NULL,           NULL,           NULL,
16058 /* FC */        NULL,           NULL,           NULL,           NULL,
16059 };
16060
16061 static void
16062 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16063 {
16064   const char *mnemonic;
16065
16066   FETCH_DATA (the_info, codep + 1);
16067   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16068      place where an 8-bit immediate would normally go.  ie. the last
16069      byte of the instruction.  */
16070   obufp = mnemonicendp;
16071   mnemonic = Suffix3DNow[*codep++ & 0xff];
16072   if (mnemonic)
16073     oappend (mnemonic);
16074   else
16075     {
16076       /* Since a variable sized modrm/sib chunk is between the start
16077          of the opcode (0x0f0f) and the opcode suffix, we need to do
16078          all the modrm processing first, and don't know until now that
16079          we have a bad opcode.  This necessitates some cleaning up.  */
16080       op_out[0][0] = '\0';
16081       op_out[1][0] = '\0';
16082       BadOp ();
16083     }
16084   mnemonicendp = obufp;
16085 }
16086
16087 static const struct op simd_cmp_op[] =
16088 {
16089   { STRING_COMMA_LEN ("eq") },
16090   { STRING_COMMA_LEN ("lt") },
16091   { STRING_COMMA_LEN ("le") },
16092   { STRING_COMMA_LEN ("unord") },
16093   { STRING_COMMA_LEN ("neq") },
16094   { STRING_COMMA_LEN ("nlt") },
16095   { STRING_COMMA_LEN ("nle") },
16096   { STRING_COMMA_LEN ("ord") }
16097 };
16098
16099 static const struct op vex_cmp_op[] =
16100 {
16101   { STRING_COMMA_LEN ("eq_uq") },
16102   { STRING_COMMA_LEN ("nge") },
16103   { STRING_COMMA_LEN ("ngt") },
16104   { STRING_COMMA_LEN ("false") },
16105   { STRING_COMMA_LEN ("neq_oq") },
16106   { STRING_COMMA_LEN ("ge") },
16107   { STRING_COMMA_LEN ("gt") },
16108   { STRING_COMMA_LEN ("true") },
16109   { STRING_COMMA_LEN ("eq_os") },
16110   { STRING_COMMA_LEN ("lt_oq") },
16111   { STRING_COMMA_LEN ("le_oq") },
16112   { STRING_COMMA_LEN ("unord_s") },
16113   { STRING_COMMA_LEN ("neq_us") },
16114   { STRING_COMMA_LEN ("nlt_uq") },
16115   { STRING_COMMA_LEN ("nle_uq") },
16116   { STRING_COMMA_LEN ("ord_s") },
16117   { STRING_COMMA_LEN ("eq_us") },
16118   { STRING_COMMA_LEN ("nge_uq") },
16119   { STRING_COMMA_LEN ("ngt_uq") },
16120   { STRING_COMMA_LEN ("false_os") },
16121   { STRING_COMMA_LEN ("neq_os") },
16122   { STRING_COMMA_LEN ("ge_oq") },
16123   { STRING_COMMA_LEN ("gt_oq") },
16124   { STRING_COMMA_LEN ("true_us") },
16125 };
16126
16127 static void
16128 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16129 {
16130   unsigned int cmp_type;
16131
16132   FETCH_DATA (the_info, codep + 1);
16133   cmp_type = *codep++ & 0xff;
16134   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16135     {
16136       char suffix [3];
16137       char *p = mnemonicendp - 2;
16138       suffix[0] = p[0];
16139       suffix[1] = p[1];
16140       suffix[2] = '\0';
16141       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16142       mnemonicendp += simd_cmp_op[cmp_type].len;
16143     }
16144   else if (need_vex
16145            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
16146     {
16147       char suffix [3];
16148       char *p = mnemonicendp - 2;
16149       suffix[0] = p[0];
16150       suffix[1] = p[1];
16151       suffix[2] = '\0';
16152       cmp_type -= ARRAY_SIZE (simd_cmp_op);
16153       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16154       mnemonicendp += vex_cmp_op[cmp_type].len;
16155     }
16156   else
16157     {
16158       /* We have a reserved extension byte.  Output it directly.  */
16159       scratchbuf[0] = '$';
16160       print_operand_value (scratchbuf + 1, 1, cmp_type);
16161       oappend_maybe_intel (scratchbuf);
16162       scratchbuf[0] = '\0';
16163     }
16164 }
16165
16166 static void
16167 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16168 {
16169   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
16170   if (!intel_syntax)
16171     {
16172       strcpy (op_out[0], names32[0]);
16173       strcpy (op_out[1], names32[1]);
16174       if (bytemode == eBX_reg)
16175         strcpy (op_out[2], names32[3]);
16176       two_source_ops = 1;
16177     }
16178   /* Skip mod/rm byte.  */
16179   MODRM_CHECK;
16180   codep++;
16181 }
16182
16183 static void
16184 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16185             int sizeflag ATTRIBUTE_UNUSED)
16186 {
16187   /* monitor %{e,r,}ax,%ecx,%edx"  */
16188   if (!intel_syntax)
16189     {
16190       const char **names = (address_mode == mode_64bit
16191                             ? names64 : names32);
16192
16193       if (prefixes & PREFIX_ADDR)
16194         {
16195           /* Remove "addr16/addr32".  */
16196           all_prefixes[last_addr_prefix] = 0;
16197           names = (address_mode != mode_32bit
16198                    ? names32 : names16);
16199           used_prefixes |= PREFIX_ADDR;
16200         }
16201       else if (address_mode == mode_16bit)
16202         names = names16;
16203       strcpy (op_out[0], names[0]);
16204       strcpy (op_out[1], names32[1]);
16205       strcpy (op_out[2], names32[2]);
16206       two_source_ops = 1;
16207     }
16208   /* Skip mod/rm byte.  */
16209   MODRM_CHECK;
16210   codep++;
16211 }
16212
16213 static void
16214 BadOp (void)
16215 {
16216   /* Throw away prefixes and 1st. opcode byte.  */
16217   codep = insn_codep + 1;
16218   oappend ("(bad)");
16219 }
16220
16221 static void
16222 REP_Fixup (int bytemode, int sizeflag)
16223 {
16224   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16225      lods and stos.  */
16226   if (prefixes & PREFIX_REPZ)
16227     all_prefixes[last_repz_prefix] = REP_PREFIX;
16228
16229   switch (bytemode)
16230     {
16231     case al_reg:
16232     case eAX_reg:
16233     case indir_dx_reg:
16234       OP_IMREG (bytemode, sizeflag);
16235       break;
16236     case eDI_reg:
16237       OP_ESreg (bytemode, sizeflag);
16238       break;
16239     case eSI_reg:
16240       OP_DSreg (bytemode, sizeflag);
16241       break;
16242     default:
16243       abort ();
16244       break;
16245     }
16246 }
16247
16248 static void
16249 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16250 {
16251   if ( isa64 != amd64 )
16252     return;
16253
16254   obufp = obuf;
16255   BadOp ();
16256   mnemonicendp = obufp;
16257   ++codep;
16258 }
16259
16260 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16261    "bnd".  */
16262
16263 static void
16264 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16265 {
16266   if (prefixes & PREFIX_REPNZ)
16267     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16268 }
16269
16270 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16271    "notrack".  */
16272
16273 static void
16274 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16275                int sizeflag ATTRIBUTE_UNUSED)
16276 {
16277   if (active_seg_prefix == PREFIX_DS
16278       && (address_mode != mode_64bit || last_data_prefix < 0))
16279     {
16280       /* NOTRACK prefix is only valid on indirect branch instructions.
16281          NB: DATA prefix is unsupported for Intel64.  */
16282       active_seg_prefix = 0;
16283       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16284     }
16285 }
16286
16287 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16288    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16289  */
16290
16291 static void
16292 HLE_Fixup1 (int bytemode, int sizeflag)
16293 {
16294   if (modrm.mod != 3
16295       && (prefixes & PREFIX_LOCK) != 0)
16296     {
16297       if (prefixes & PREFIX_REPZ)
16298         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16299       if (prefixes & PREFIX_REPNZ)
16300         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16301     }
16302
16303   OP_E (bytemode, sizeflag);
16304 }
16305
16306 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16307    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16308  */
16309
16310 static void
16311 HLE_Fixup2 (int bytemode, int sizeflag)
16312 {
16313   if (modrm.mod != 3)
16314     {
16315       if (prefixes & PREFIX_REPZ)
16316         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16317       if (prefixes & PREFIX_REPNZ)
16318         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16319     }
16320
16321   OP_E (bytemode, sizeflag);
16322 }
16323
16324 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16325    "xrelease" for memory operand.  No check for LOCK prefix.   */
16326
16327 static void
16328 HLE_Fixup3 (int bytemode, int sizeflag)
16329 {
16330   if (modrm.mod != 3
16331       && last_repz_prefix > last_repnz_prefix
16332       && (prefixes & PREFIX_REPZ) != 0)
16333     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16334
16335   OP_E (bytemode, sizeflag);
16336 }
16337
16338 static void
16339 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16340 {
16341   USED_REX (REX_W);
16342   if (rex & REX_W)
16343     {
16344       /* Change cmpxchg8b to cmpxchg16b.  */
16345       char *p = mnemonicendp - 2;
16346       mnemonicendp = stpcpy (p, "16b");
16347       bytemode = o_mode;
16348     }
16349   else if ((prefixes & PREFIX_LOCK) != 0)
16350     {
16351       if (prefixes & PREFIX_REPZ)
16352         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16353       if (prefixes & PREFIX_REPNZ)
16354         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16355     }
16356
16357   OP_M (bytemode, sizeflag);
16358 }
16359
16360 static void
16361 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16362 {
16363   const char **names;
16364
16365   if (need_vex)
16366     {
16367       switch (vex.length)
16368         {
16369         case 128:
16370           names = names_xmm;
16371           break;
16372         case 256:
16373           names = names_ymm;
16374           break;
16375         default:
16376           abort ();
16377         }
16378     }
16379   else
16380     names = names_xmm;
16381   oappend (names[reg]);
16382 }
16383
16384 static void
16385 FXSAVE_Fixup (int bytemode, int sizeflag)
16386 {
16387   /* Add proper suffix to "fxsave" and "fxrstor".  */
16388   USED_REX (REX_W);
16389   if (rex & REX_W)
16390     {
16391       char *p = mnemonicendp;
16392       *p++ = '6';
16393       *p++ = '4';
16394       *p = '\0';
16395       mnemonicendp = p;
16396     }
16397   OP_M (bytemode, sizeflag);
16398 }
16399
16400 /* Display the destination register operand for instructions with
16401    VEX. */
16402
16403 static void
16404 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16405 {
16406   int reg;
16407   const char **names;
16408
16409   if (!need_vex)
16410     abort ();
16411
16412   if (!need_vex_reg)
16413     return;
16414
16415   reg = vex.register_specifier;
16416   vex.register_specifier = 0;
16417   if (address_mode != mode_64bit)
16418     reg &= 7;
16419   else if (vex.evex && !vex.v)
16420     reg += 16;
16421
16422   if (bytemode == vex_scalar_mode)
16423     {
16424       oappend (names_xmm[reg]);
16425       return;
16426     }
16427
16428   if (bytemode == tmm_mode)
16429     {
16430       /* All 3 TMM registers must be distinct.  */
16431       if (reg >= 8)
16432         oappend ("(bad)");
16433       else
16434         {
16435           /* This must be the 3rd operand.  */
16436           if (obufp != op_out[2])
16437             abort ();
16438           oappend (names_tmm[reg]);
16439           if (reg == modrm.reg || reg == modrm.rm)
16440             strcpy (obufp, "/(bad)");
16441         }
16442
16443       if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
16444         {
16445           if (modrm.reg <= 8
16446               && (modrm.reg == modrm.rm || modrm.reg == reg))
16447             strcat (op_out[0], "/(bad)");
16448           if (modrm.rm <= 8
16449               && (modrm.rm == modrm.reg || modrm.rm == reg))
16450             strcat (op_out[1], "/(bad)");
16451         }
16452
16453       return;
16454     }
16455
16456   switch (vex.length)
16457     {
16458     case 128:
16459       switch (bytemode)
16460         {
16461         case vex_mode:
16462         case vex_vsib_q_w_dq_mode:
16463         case vex_vsib_q_w_d_mode:
16464           names = names_xmm;
16465           break;
16466         case dq_mode:
16467           if (rex & REX_W)
16468             names = names64;
16469           else
16470             names = names32;
16471           break;
16472         case mask_bd_mode:
16473         case mask_mode:
16474           if (reg > 0x7)
16475             {
16476               oappend ("(bad)");
16477               return;
16478             }
16479           names = names_mask;
16480           break;
16481         default:
16482           abort ();
16483           return;
16484         }
16485       break;
16486     case 256:
16487       switch (bytemode)
16488         {
16489         case vex_mode:
16490           names = names_ymm;
16491           break;
16492         case vex_vsib_q_w_dq_mode:
16493         case vex_vsib_q_w_d_mode:
16494           names = vex.w ? names_ymm : names_xmm;
16495           break;
16496         case mask_bd_mode:
16497         case mask_mode:
16498           if (reg > 0x7)
16499             {
16500               oappend ("(bad)");
16501               return;
16502             }
16503           names = names_mask;
16504           break;
16505         default:
16506           /* See PR binutils/20893 for a reproducer.  */
16507           oappend ("(bad)");
16508           return;
16509         }
16510       break;
16511     case 512:
16512       names = names_zmm;
16513       break;
16514     default:
16515       abort ();
16516       break;
16517     }
16518   oappend (names[reg]);
16519 }
16520
16521 static void
16522 OP_VexW (int bytemode, int sizeflag)
16523 {
16524   OP_VEX (bytemode, sizeflag);
16525
16526   if (vex.w)
16527     {
16528       /* Swap 2nd and 3rd operands.  */
16529       strcpy (scratchbuf, op_out[2]);
16530       strcpy (op_out[2], op_out[1]);
16531       strcpy (op_out[1], scratchbuf);
16532     }
16533 }
16534
16535 static void
16536 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16537 {
16538   int reg;
16539   const char **names = names_xmm;
16540
16541   FETCH_DATA (the_info, codep + 1);
16542   reg = *codep++;
16543
16544   if (bytemode != x_mode && bytemode != scalar_mode)
16545     abort ();
16546
16547   reg >>= 4;
16548   if (address_mode != mode_64bit)
16549     reg &= 7;
16550
16551   if (bytemode == x_mode && vex.length == 256)
16552     names = names_ymm;
16553
16554   oappend (names[reg]);
16555
16556   if (vex.w)
16557     {
16558       /* Swap 3rd and 4th operands.  */
16559       strcpy (scratchbuf, op_out[3]);
16560       strcpy (op_out[3], op_out[2]);
16561       strcpy (op_out[2], scratchbuf);
16562     }
16563 }
16564
16565 static void
16566 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
16567           int sizeflag ATTRIBUTE_UNUSED)
16568 {
16569   scratchbuf[0] = '$';
16570   print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
16571   oappend_maybe_intel (scratchbuf);
16572 }
16573
16574 static void
16575 OP_EX_Vex (int bytemode, int sizeflag)
16576 {
16577   if (modrm.mod != 3)
16578     need_vex_reg = 0;
16579   OP_EX (bytemode, sizeflag);
16580 }
16581
16582 static void
16583 OP_XMM_Vex (int bytemode, int sizeflag)
16584 {
16585   if (modrm.mod != 3)
16586     need_vex_reg = 0;
16587   OP_XMM (bytemode, sizeflag);
16588 }
16589
16590 static void
16591 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16592              int sizeflag ATTRIBUTE_UNUSED)
16593 {
16594   unsigned int cmp_type;
16595
16596   if (!vex.evex)
16597     abort ();
16598
16599   FETCH_DATA (the_info, codep + 1);
16600   cmp_type = *codep++ & 0xff;
16601   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16602      If it's the case, print suffix, otherwise - print the immediate.  */
16603   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16604       && cmp_type != 3
16605       && cmp_type != 7)
16606     {
16607       char suffix [3];
16608       char *p = mnemonicendp - 2;
16609
16610       /* vpcmp* can have both one- and two-lettered suffix.  */
16611       if (p[0] == 'p')
16612         {
16613           p++;
16614           suffix[0] = p[0];
16615           suffix[1] = '\0';
16616         }
16617       else
16618         {
16619           suffix[0] = p[0];
16620           suffix[1] = p[1];
16621           suffix[2] = '\0';
16622         }
16623
16624       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16625       mnemonicendp += simd_cmp_op[cmp_type].len;
16626     }
16627   else
16628     {
16629       /* We have a reserved extension byte.  Output it directly.  */
16630       scratchbuf[0] = '$';
16631       print_operand_value (scratchbuf + 1, 1, cmp_type);
16632       oappend_maybe_intel (scratchbuf);
16633       scratchbuf[0] = '\0';
16634     }
16635 }
16636
16637 static const struct op xop_cmp_op[] =
16638 {
16639   { STRING_COMMA_LEN ("lt") },
16640   { STRING_COMMA_LEN ("le") },
16641   { STRING_COMMA_LEN ("gt") },
16642   { STRING_COMMA_LEN ("ge") },
16643   { STRING_COMMA_LEN ("eq") },
16644   { STRING_COMMA_LEN ("neq") },
16645   { STRING_COMMA_LEN ("false") },
16646   { STRING_COMMA_LEN ("true") }
16647 };
16648
16649 static void
16650 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16651              int sizeflag ATTRIBUTE_UNUSED)
16652 {
16653   unsigned int cmp_type;
16654
16655   FETCH_DATA (the_info, codep + 1);
16656   cmp_type = *codep++ & 0xff;
16657   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16658     {
16659       char suffix[3];
16660       char *p = mnemonicendp - 2;
16661
16662       /* vpcom* can have both one- and two-lettered suffix.  */
16663       if (p[0] == 'm')
16664         {
16665           p++;
16666           suffix[0] = p[0];
16667           suffix[1] = '\0';
16668         }
16669       else
16670         {
16671           suffix[0] = p[0];
16672           suffix[1] = p[1];
16673           suffix[2] = '\0';
16674         }
16675
16676       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16677       mnemonicendp += xop_cmp_op[cmp_type].len;
16678     }
16679   else
16680     {
16681       /* We have a reserved extension byte.  Output it directly.  */
16682       scratchbuf[0] = '$';
16683       print_operand_value (scratchbuf + 1, 1, cmp_type);
16684       oappend_maybe_intel (scratchbuf);
16685       scratchbuf[0] = '\0';
16686     }
16687 }
16688
16689 static const struct op pclmul_op[] =
16690 {
16691   { STRING_COMMA_LEN ("lql") },
16692   { STRING_COMMA_LEN ("hql") },
16693   { STRING_COMMA_LEN ("lqh") },
16694   { STRING_COMMA_LEN ("hqh") }
16695 };
16696
16697 static void
16698 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16699               int sizeflag ATTRIBUTE_UNUSED)
16700 {
16701   unsigned int pclmul_type;
16702
16703   FETCH_DATA (the_info, codep + 1);
16704   pclmul_type = *codep++ & 0xff;
16705   switch (pclmul_type)
16706     {
16707     case 0x10:
16708       pclmul_type = 2;
16709       break;
16710     case 0x11:
16711       pclmul_type = 3;
16712       break;
16713     default:
16714       break;
16715     }
16716   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16717     {
16718       char suffix [4];
16719       char *p = mnemonicendp - 3;
16720       suffix[0] = p[0];
16721       suffix[1] = p[1];
16722       suffix[2] = p[2];
16723       suffix[3] = '\0';
16724       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16725       mnemonicendp += pclmul_op[pclmul_type].len;
16726     }
16727   else
16728     {
16729       /* We have a reserved extension byte.  Output it directly.  */
16730       scratchbuf[0] = '$';
16731       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16732       oappend_maybe_intel (scratchbuf);
16733       scratchbuf[0] = '\0';
16734     }
16735 }
16736
16737 static void
16738 MOVSXD_Fixup (int bytemode, int sizeflag)
16739 {
16740   /* Add proper suffix to "movsxd".  */
16741   char *p = mnemonicendp;
16742
16743   switch (bytemode)
16744     {
16745     case movsxd_mode:
16746       if (intel_syntax)
16747         {
16748           *p++ = 'x';
16749           *p++ = 'd';
16750           goto skip;
16751         }
16752
16753       USED_REX (REX_W);
16754       if (rex & REX_W)
16755         {
16756           *p++ = 'l';
16757           *p++ = 'q';
16758         }
16759       else
16760         {
16761           *p++ = 'x';
16762           *p++ = 'd';
16763         }
16764       break;
16765     default:
16766       oappend (INTERNAL_DISASSEMBLER_ERROR);
16767       break;
16768     }
16769
16770  skip:
16771   mnemonicendp = p;
16772   *p = '\0';
16773   OP_E (bytemode, sizeflag);
16774 }
16775
16776 static void
16777 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16778 {
16779   if (!vex.evex
16780       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16781     abort ();
16782
16783   USED_REX (REX_R);
16784   if ((rex & REX_R) != 0 || !vex.r)
16785     {
16786       BadOp ();
16787       return;
16788     }
16789
16790   oappend (names_mask [modrm.reg]);
16791 }
16792
16793 static void
16794 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16795 {
16796   if (modrm.mod == 3 && vex.b)
16797     switch (bytemode)
16798       {
16799       case evex_rounding_64_mode:
16800         if (address_mode != mode_64bit)
16801           {
16802             oappend ("(bad)");
16803             break;
16804           }
16805         /* Fall through.  */
16806       case evex_rounding_mode:
16807         oappend (names_rounding[vex.ll]);
16808         break;
16809       case evex_sae_mode:
16810         oappend ("{sae}");
16811         break;
16812       default:
16813         abort ();
16814         break;
16815       }
16816 }