opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2016 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void OP_LWPCB_E (int, int);
 121 static void OP_LWP_E (int, int);
 122 static void OP_Vex_2src_1 (int, int);
 123 static void OP_Vex_2src_2 (int, int);
 124
 125 static void MOVBE_Fixup (int, int);
 126
 127 static void OP_Mask (int, int);
 128
 129 struct dis_private {
 130   /* Points to first byte not fetched.  */
 131   bfd_byte *max_fetched;
 132   bfd_byte the_buffer[MAX_MNEM_SIZE];
 133   bfd_vma insn_start;
 134   int orig_sizeflag;
 135   OPCODES_SIGJMP_BUF bailout;
 136 };
 137
 138 enum address_mode
 139 {
 140   mode_16bit,
 141   mode_32bit,
 142   mode_64bit
 143 };
 144
 145 enum address_mode address_mode;
 146
 147 /* Flags for the prefixes for the current instruction.  See below.  */
 148 static int prefixes;
 149
 150 /* REX prefix the current instruction.  See below.  */
 151 static int rex;
 152 /* Bits of REX we've already used.  */
 153 static int rex_used;
 154 /* REX bits in original REX prefix ignored.  */
 155 static int rex_ignored;
 156 /* Mark parts used in the REX prefix.  When we are testing for
 157    empty prefix (for 8bit register REX extension), just mask it
 158    out.  Otherwise test for REX bit is excuse for existence of REX
 159    only in case value is nonzero.  */
 160 #define USED_REX(value)                                 \
 161   {                                                     \
 162     if (value)                                          \
 163       {                                                 \
 164         if ((rex & value))                              \
 165           rex_used |= (value) | REX_OPCODE;             \
 166       }                                                 \
 167     else                                                \
 168       rex_used |= REX_OPCODE;                           \
 169   }
 170
 171 /* Flags for prefixes which we somehow handled when printing the
 172    current instruction.  */
 173 static int used_prefixes;
 174
 175 /* Flags stored in PREFIXES.  */
 176 #define PREFIX_REPZ 1
 177 #define PREFIX_REPNZ 2
 178 #define PREFIX_LOCK 4
 179 #define PREFIX_CS 8
 180 #define PREFIX_SS 0x10
 181 #define PREFIX_DS 0x20
 182 #define PREFIX_ES 0x40
 183 #define PREFIX_FS 0x80
 184 #define PREFIX_GS 0x100
 185 #define PREFIX_DATA 0x200
 186 #define PREFIX_ADDR 0x400
 187 #define PREFIX_FWAIT 0x800
 188
 189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 190    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 191    on error.  */
 192 #define FETCH_DATA(info, addr) \
 193   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 194    ? 1 : fetch_data ((info), (addr)))
 195
 196 static int
 197 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 198 {
 199   int status;
 200   struct dis_private *priv = (struct dis_private *) info->private_data;
 201   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 202
 203   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 204     status = (*info->read_memory_func) (start,
 205                                         priv->max_fetched,
 206                                         addr - priv->max_fetched,
 207                                         info);
 208   else
 209     status = -1;
 210   if (status != 0)
 211     {
 212       /* If we did manage to read at least one byte, then
 213          print_insn_i386 will do something sensible.  Otherwise, print
 214          an error.  We do that here because this is where we know
 215          STATUS.  */
 216       if (priv->max_fetched == priv->the_buffer)
 217         (*info->memory_error_func) (status, start, info);
 218       OPCODES_SIGLONGJMP (priv->bailout, 1);
 219     }
 220   else
 221     priv->max_fetched = addr;
 222   return 1;
 223 }
 224
 225 /* Possible values for prefix requirement.  */
 226 #define PREFIX_IGNORED_SHIFT    16
 227 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 232
 233 /* Opcode prefixes.  */
 234 #define PREFIX_OPCODE           (PREFIX_REPZ \
 235                                  | PREFIX_REPNZ \
 236                                  | PREFIX_DATA)
 237
 238 /* Prefixes ignored.  */
 239 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 240                                  | PREFIX_IGNORED_REPNZ \
 241                                  | PREFIX_IGNORED_DATA)
 242
 243 #define XX { NULL, 0 }
 244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 245
 246 #define Eb { OP_E, b_mode }
 247 #define Ebnd { OP_E, bnd_mode }
 248 #define EbS { OP_E, b_swap_mode }
 249 #define Ev { OP_E, v_mode }
 250 #define Ev_bnd { OP_E, v_bnd_mode }
 251 #define EvS { OP_E, v_swap_mode }
 252 #define Ed { OP_E, d_mode }
 253 #define Edq { OP_E, dq_mode }
 254 #define Edqw { OP_E, dqw_mode }
 255 #define EdqwS { OP_E, dqw_swap_mode }
 256 #define Edqb { OP_E, dqb_mode }
 257 #define Edb { OP_E, db_mode }
 258 #define Edw { OP_E, dw_mode }
 259 #define Edqd { OP_E, dqd_mode }
 260 #define Eq { OP_E, q_mode }
 261 #define indirEv { OP_indirE, indir_v_mode }
 262 #define indirEp { OP_indirE, f_mode }
 263 #define stackEv { OP_E, stack_v_mode }
 264 #define Em { OP_E, m_mode }
 265 #define Ew { OP_E, w_mode }
 266 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 267 #define Ma { OP_M, a_mode }
 268 #define Mb { OP_M, b_mode }
 269 #define Md { OP_M, d_mode }
 270 #define Mo { OP_M, o_mode }
 271 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 272 #define Mq { OP_M, q_mode }
 273 #define Mx { OP_M, x_mode }
 274 #define Mxmm { OP_M, xmm_mode }
 275 #define Gb { OP_G, b_mode }
 276 #define Gbnd { OP_G, bnd_mode }
 277 #define Gv { OP_G, v_mode }
 278 #define Gd { OP_G, d_mode }
 279 #define Gdq { OP_G, dq_mode }
 280 #define Gm { OP_G, m_mode }
 281 #define Gw { OP_G, w_mode }
 282 #define Rd { OP_R, d_mode }
 283 #define Rdq { OP_R, dq_mode }
 284 #define Rm { OP_R, m_mode }
 285 #define Ib { OP_I, b_mode }
 286 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 288 #define Iv { OP_I, v_mode }
 289 #define sIv { OP_sI, v_mode }
 290 #define Iq { OP_I, q_mode }
 291 #define Iv64 { OP_I64, v_mode }
 292 #define Iw { OP_I, w_mode }
 293 #define I1 { OP_I, const_1_mode }
 294 #define Jb { OP_J, b_mode }
 295 #define Jv { OP_J, v_mode }
 296 #define Cm { OP_C, m_mode }
 297 #define Dm { OP_D, m_mode }
 298 #define Td { OP_T, d_mode }
 299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 300
 301 #define RMeAX { OP_REG, eAX_reg }
 302 #define RMeBX { OP_REG, eBX_reg }
 303 #define RMeCX { OP_REG, eCX_reg }
 304 #define RMeDX { OP_REG, eDX_reg }
 305 #define RMeSP { OP_REG, eSP_reg }
 306 #define RMeBP { OP_REG, eBP_reg }
 307 #define RMeSI { OP_REG, eSI_reg }
 308 #define RMeDI { OP_REG, eDI_reg }
 309 #define RMrAX { OP_REG, rAX_reg }
 310 #define RMrBX { OP_REG, rBX_reg }
 311 #define RMrCX { OP_REG, rCX_reg }
 312 #define RMrDX { OP_REG, rDX_reg }
 313 #define RMrSP { OP_REG, rSP_reg }
 314 #define RMrBP { OP_REG, rBP_reg }
 315 #define RMrSI { OP_REG, rSI_reg }
 316 #define RMrDI { OP_REG, rDI_reg }
 317 #define RMAL { OP_REG, al_reg }
 318 #define RMCL { OP_REG, cl_reg }
 319 #define RMDL { OP_REG, dl_reg }
 320 #define RMBL { OP_REG, bl_reg }
 321 #define RMAH { OP_REG, ah_reg }
 322 #define RMCH { OP_REG, ch_reg }
 323 #define RMDH { OP_REG, dh_reg }
 324 #define RMBH { OP_REG, bh_reg }
 325 #define RMAX { OP_REG, ax_reg }
 326 #define RMDX { OP_REG, dx_reg }
 327
 328 #define eAX { OP_IMREG, eAX_reg }
 329 #define eBX { OP_IMREG, eBX_reg }
 330 #define eCX { OP_IMREG, eCX_reg }
 331 #define eDX { OP_IMREG, eDX_reg }
 332 #define eSP { OP_IMREG, eSP_reg }
 333 #define eBP { OP_IMREG, eBP_reg }
 334 #define eSI { OP_IMREG, eSI_reg }
 335 #define eDI { OP_IMREG, eDI_reg }
 336 #define AL { OP_IMREG, al_reg }
 337 #define CL { OP_IMREG, cl_reg }
 338 #define DL { OP_IMREG, dl_reg }
 339 #define BL { OP_IMREG, bl_reg }
 340 #define AH { OP_IMREG, ah_reg }
 341 #define CH { OP_IMREG, ch_reg }
 342 #define DH { OP_IMREG, dh_reg }
 343 #define BH { OP_IMREG, bh_reg }
 344 #define AX { OP_IMREG, ax_reg }
 345 #define DX { OP_IMREG, dx_reg }
 346 #define zAX { OP_IMREG, z_mode_ax_reg }
 347 #define indirDX { OP_IMREG, indir_dx_reg }
 348
 349 #define Sw { OP_SEG, w_mode }
 350 #define Sv { OP_SEG, v_mode }
 351 #define Ap { OP_DIR, 0 }
 352 #define Ob { OP_OFF64, b_mode }
 353 #define Ov { OP_OFF64, v_mode }
 354 #define Xb { OP_DSreg, eSI_reg }
 355 #define Xv { OP_DSreg, eSI_reg }
 356 #define Xz { OP_DSreg, eSI_reg }
 357 #define Yb { OP_ESreg, eDI_reg }
 358 #define Yv { OP_ESreg, eDI_reg }
 359 #define DSBX { OP_DSreg, eBX_reg }
 360
 361 #define es { OP_REG, es_reg }
 362 #define ss { OP_REG, ss_reg }
 363 #define cs { OP_REG, cs_reg }
 364 #define ds { OP_REG, ds_reg }
 365 #define fs { OP_REG, fs_reg }
 366 #define gs { OP_REG, gs_reg }
 367
 368 #define MX { OP_MMX, 0 }
 369 #define XM { OP_XMM, 0 }
 370 #define XMScalar { OP_XMM, scalar_mode }
 371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 372 #define XMM { OP_XMM, xmm_mode }
 373 #define XMxmmq { OP_XMM, xmmq_mode }
 374 #define EM { OP_EM, v_mode }
 375 #define EMS { OP_EM, v_swap_mode }
 376 #define EMd { OP_EM, d_mode }
 377 #define EMx { OP_EM, x_mode }
 378 #define EXw { OP_EX, w_mode }
 379 #define EXd { OP_EX, d_mode }
 380 #define EXdScalar { OP_EX, d_scalar_mode }
 381 #define EXdS { OP_EX, d_swap_mode }
 382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 383 #define EXq { OP_EX, q_mode }
 384 #define EXqScalar { OP_EX, q_scalar_mode }
 385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 386 #define EXqS { OP_EX, q_swap_mode }
 387 #define EXx { OP_EX, x_mode }
 388 #define EXxS { OP_EX, x_swap_mode }
 389 #define EXxmm { OP_EX, xmm_mode }
 390 #define EXymm { OP_EX, ymm_mode }
 391 #define EXxmmq { OP_EX, xmmq_mode }
 392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 395 #define EXxmm_md { OP_EX, xmm_md_mode }
 396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 398 #define EXxmmdw { OP_EX, xmmdw_mode }
 399 #define EXxmmqd { OP_EX, xmmqd_mode }
 400 #define EXymmq { OP_EX, ymmq_mode }
 401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 405 #define MS { OP_MS, v_mode }
 406 #define XS { OP_XS, v_mode }
 407 #define EMCq { OP_EMC, q_mode }
 408 #define MXC { OP_MXC, 0 }
 409 #define OPSUF { OP_3DNowSuffix, 0 }
 410 #define CMP { CMP_Fixup, 0 }
 411 #define XMM0 { XMM_Fixup, 0 }
 412 #define FXSAVE { FXSAVE_Fixup, 0 }
 413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 415
 416 #define Vex { OP_VEX, vex_mode }
 417 #define VexScalar { OP_VEX, vex_scalar_mode }
 418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 419 #define Vex128 { OP_VEX, vex128_mode }
 420 #define Vex256 { OP_VEX, vex256_mode }
 421 #define VexGdq { OP_VEX, dq_mode }
 422 #define VexI4 { VEXI4_Fixup, 0}
 423 #define EXdVex { OP_EX_Vex, d_mode }
 424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 426 #define EXqVex { OP_EX_Vex, q_mode }
 427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 429 #define EXVexW { OP_EX_VexW, x_mode }
 430 #define EXdVexW { OP_EX_VexW, d_mode }
 431 #define EXqVexW { OP_EX_VexW, q_mode }
 432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 433 #define XMVex { OP_XMM_Vex, 0 }
 434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 435 #define XMVexW { OP_XMM_VexW, 0 }
 436 #define XMVexI4 { OP_REG_VexI4, x_mode }
 437 #define PCLMUL { PCLMUL_Fixup, 0 }
 438 #define VZERO { VZERO_Fixup, 0 }
 439 #define VCMP { VCMP_Fixup, 0 }
 440 #define VPCMP { VPCMP_Fixup, 0 }
 441
 442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 444
 445 #define XMask { OP_Mask, mask_mode }
 446 #define MaskG { OP_G, mask_mode }
 447 #define MaskE { OP_E, mask_mode }
 448 #define MaskBDE { OP_E, mask_bd_mode }
 449 #define MaskR { OP_R, mask_mode }
 450 #define MaskVex { OP_VEX, mask_mode }
 451
 452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 456
 457 /* Used handle "rep" prefix for string instructions.  */
 458 #define Xbr { REP_Fixup, eSI_reg }
 459 #define Xvr { REP_Fixup, eSI_reg }
 460 #define Ybr { REP_Fixup, eDI_reg }
 461 #define Yvr { REP_Fixup, eDI_reg }
 462 #define Yzr { REP_Fixup, eDI_reg }
 463 #define indirDXr { REP_Fixup, indir_dx_reg }
 464 #define ALr { REP_Fixup, al_reg }
 465 #define eAXr { REP_Fixup, eAX_reg }
 466
 467 /* Used handle HLE prefix for lockable instructions.  */
 468 #define Ebh1 { HLE_Fixup1, b_mode }
 469 #define Evh1 { HLE_Fixup1, v_mode }
 470 #define Ebh2 { HLE_Fixup2, b_mode }
 471 #define Evh2 { HLE_Fixup2, v_mode }
 472 #define Ebh3 { HLE_Fixup3, b_mode }
 473 #define Evh3 { HLE_Fixup3, v_mode }
 474
 475 #define BND { BND_Fixup, 0 }
 476
 477 #define cond_jump_flag { NULL, cond_jump_mode }
 478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 479
 480 /* bits in sizeflag */
 481 #define SUFFIX_ALWAYS 4
 482 #define AFLAG 2
 483 #define DFLAG 1
 484
 485 enum
 486 {
 487   /* byte operand */
 488   b_mode = 1,
 489   /* byte operand with operand swapped */
 490   b_swap_mode,
 491   /* byte operand, sign extend like 'T' suffix */
 492   b_T_mode,
 493   /* operand size depends on prefixes */
 494   v_mode,
 495   /* operand size depends on prefixes with operand swapped */
 496   v_swap_mode,
 497   /* word operand */
 498   w_mode,
 499   /* double word operand  */
 500   d_mode,
 501   /* double word operand with operand swapped */
 502   d_swap_mode,
 503   /* quad word operand */
 504   q_mode,
 505   /* quad word operand with operand swapped */
 506   q_swap_mode,
 507   /* ten-byte operand */
 508   t_mode,
 509   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 510      broadcast enabled.  */
 511   x_mode,
 512   /* Similar to x_mode, but with different EVEX mem shifts.  */
 513   evex_x_gscat_mode,
 514   /* Similar to x_mode, but with disabled broadcast.  */
 515   evex_x_nobcst_mode,
 516   /* Similar to x_mode, but with operands swapped and disabled broadcast
 517      in EVEX.  */
 518   x_swap_mode,
 519   /* 16-byte XMM operand */
 520   xmm_mode,
 521   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 522      memory operand (depending on vector length).  Broadcast isn't
 523      allowed.  */
 524   xmmq_mode,
 525   /* Same as xmmq_mode, but broadcast is allowed.  */
 526   evex_half_bcst_xmmq_mode,
 527   /* XMM register or byte memory operand */
 528   xmm_mb_mode,
 529   /* XMM register or word memory operand */
 530   xmm_mw_mode,
 531   /* XMM register or double word memory operand */
 532   xmm_md_mode,
 533   /* XMM register or quad word memory operand */
 534   xmm_mq_mode,
 535   /* XMM register or double/quad word memory operand, depending on
 536      VEX.W.  */
 537   xmm_mdq_mode,
 538   /* 16-byte XMM, word, double word or quad word operand.  */
 539   xmmdw_mode,
 540   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 541   xmmqd_mode,
 542   /* 32-byte YMM operand */
 543   ymm_mode,
 544   /* quad word, ymmword or zmmword memory operand.  */
 545   ymmq_mode,
 546   /* 32-byte YMM or 16-byte word operand */
 547   ymmxmm_mode,
 548   /* d_mode in 32bit, q_mode in 64bit mode.  */
 549   m_mode,
 550   /* pair of v_mode operands */
 551   a_mode,
 552   cond_jump_mode,
 553   loop_jcxz_mode,
 554   v_bnd_mode,
 555   /* operand size depends on REX prefixes.  */
 556   dq_mode,
 557   /* registers like dq_mode, memory like w_mode.  */
 558   dqw_mode,
 559   dqw_swap_mode,
 560   bnd_mode,
 561   /* 4- or 6-byte pointer operand */
 562   f_mode,
 563   const_1_mode,
 564   /* v_mode for indirect branch opcodes.  */
 565   indir_v_mode,
 566   /* v_mode for stack-related opcodes.  */
 567   stack_v_mode,
 568   /* non-quad operand size depends on prefixes */
 569   z_mode,
 570   /* 16-byte operand */
 571   o_mode,
 572   /* registers like dq_mode, memory like b_mode.  */
 573   dqb_mode,
 574   /* registers like d_mode, memory like b_mode.  */
 575   db_mode,
 576   /* registers like d_mode, memory like w_mode.  */
 577   dw_mode,
 578   /* registers like dq_mode, memory like d_mode.  */
 579   dqd_mode,
 580   /* normal vex mode */
 581   vex_mode,
 582   /* 128bit vex mode */
 583   vex128_mode,
 584   /* 256bit vex mode */
 585   vex256_mode,
 586   /* operand size depends on the VEX.W bit.  */
 587   vex_w_dq_mode,
 588
 589   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 590   vex_vsib_d_w_dq_mode,
 591   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 592   vex_vsib_d_w_d_mode,
 593   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 594   vex_vsib_q_w_dq_mode,
 595   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 596   vex_vsib_q_w_d_mode,
 597
 598   /* scalar, ignore vector length.  */
 599   scalar_mode,
 600   /* like d_mode, ignore vector length.  */
 601   d_scalar_mode,
 602   /* like d_swap_mode, ignore vector length.  */
 603   d_scalar_swap_mode,
 604   /* like q_mode, ignore vector length.  */
 605   q_scalar_mode,
 606   /* like q_swap_mode, ignore vector length.  */
 607   q_scalar_swap_mode,
 608   /* like vex_mode, ignore vector length.  */
 609   vex_scalar_mode,
 610   /* like vex_w_dq_mode, ignore vector length.  */
 611   vex_scalar_w_dq_mode,
 612
 613   /* Static rounding.  */
 614   evex_rounding_mode,
 615   /* Supress all exceptions.  */
 616   evex_sae_mode,
 617
 618   /* Mask register operand.  */
 619   mask_mode,
 620   /* Mask register operand.  */
 621   mask_bd_mode,
 622
 623   es_reg,
 624   cs_reg,
 625   ss_reg,
 626   ds_reg,
 627   fs_reg,
 628   gs_reg,
 629
 630   eAX_reg,
 631   eCX_reg,
 632   eDX_reg,
 633   eBX_reg,
 634   eSP_reg,
 635   eBP_reg,
 636   eSI_reg,
 637   eDI_reg,
 638
 639   al_reg,
 640   cl_reg,
 641   dl_reg,
 642   bl_reg,
 643   ah_reg,
 644   ch_reg,
 645   dh_reg,
 646   bh_reg,
 647
 648   ax_reg,
 649   cx_reg,
 650   dx_reg,
 651   bx_reg,
 652   sp_reg,
 653   bp_reg,
 654   si_reg,
 655   di_reg,
 656
 657   rAX_reg,
 658   rCX_reg,
 659   rDX_reg,
 660   rBX_reg,
 661   rSP_reg,
 662   rBP_reg,
 663   rSI_reg,
 664   rDI_reg,
 665
 666   z_mode_ax_reg,
 667   indir_dx_reg
 668 };
 669
 670 enum
 671 {
 672   FLOATCODE = 1,
 673   USE_REG_TABLE,
 674   USE_MOD_TABLE,
 675   USE_RM_TABLE,
 676   USE_PREFIX_TABLE,
 677   USE_X86_64_TABLE,
 678   USE_3BYTE_TABLE,
 679   USE_XOP_8F_TABLE,
 680   USE_VEX_C4_TABLE,
 681   USE_VEX_C5_TABLE,
 682   USE_VEX_LEN_TABLE,
 683   USE_VEX_W_TABLE,
 684   USE_EVEX_TABLE
 685 };
 686
 687 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 688
 689 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 690 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 691 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 692 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 693 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 694 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 695 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 696 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 697 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 698 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 699 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 700 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 701 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 702 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 703 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 704
 705 enum
 706 {
 707   REG_80 = 0,
 708   REG_81,
 709   REG_82,
 710   REG_83,
 711   REG_8F,
 712   REG_C0,
 713   REG_C1,
 714   REG_C6,
 715   REG_C7,
 716   REG_D0,
 717   REG_D1,
 718   REG_D2,
 719   REG_D3,
 720   REG_F6,
 721   REG_F7,
 722   REG_FE,
 723   REG_FF,
 724   REG_0F00,
 725   REG_0F01,
 726   REG_0F0D,
 727   REG_0F18,
 728   REG_0F71,
 729   REG_0F72,
 730   REG_0F73,
 731   REG_0FA6,
 732   REG_0FA7,
 733   REG_0FAE,
 734   REG_0FBA,
 735   REG_0FC7,
 736   REG_VEX_0F71,
 737   REG_VEX_0F72,
 738   REG_VEX_0F73,
 739   REG_VEX_0FAE,
 740   REG_VEX_0F38F3,
 741   REG_XOP_LWPCB,
 742   REG_XOP_LWP,
 743   REG_XOP_TBM_01,
 744   REG_XOP_TBM_02,
 745
 746   REG_EVEX_0F71,
 747   REG_EVEX_0F72,
 748   REG_EVEX_0F73,
 749   REG_EVEX_0F38C6,
 750   REG_EVEX_0F38C7
 751 };
 752
 753 enum
 754 {
 755   MOD_8D = 0,
 756   MOD_C6_REG_7,
 757   MOD_C7_REG_7,
 758   MOD_FF_REG_3,
 759   MOD_FF_REG_5,
 760   MOD_0F01_REG_0,
 761   MOD_0F01_REG_1,
 762   MOD_0F01_REG_2,
 763   MOD_0F01_REG_3,
 764   MOD_0F01_REG_5,
 765   MOD_0F01_REG_7,
 766   MOD_0F12_PREFIX_0,
 767   MOD_0F13,
 768   MOD_0F16_PREFIX_0,
 769   MOD_0F17,
 770   MOD_0F18_REG_0,
 771   MOD_0F18_REG_1,
 772   MOD_0F18_REG_2,
 773   MOD_0F18_REG_3,
 774   MOD_0F18_REG_4,
 775   MOD_0F18_REG_5,
 776   MOD_0F18_REG_6,
 777   MOD_0F18_REG_7,
 778   MOD_0F1A_PREFIX_0,
 779   MOD_0F1B_PREFIX_0,
 780   MOD_0F1B_PREFIX_1,
 781   MOD_0F24,
 782   MOD_0F26,
 783   MOD_0F2B_PREFIX_0,
 784   MOD_0F2B_PREFIX_1,
 785   MOD_0F2B_PREFIX_2,
 786   MOD_0F2B_PREFIX_3,
 787   MOD_0F51,
 788   MOD_0F71_REG_2,
 789   MOD_0F71_REG_4,
 790   MOD_0F71_REG_6,
 791   MOD_0F72_REG_2,
 792   MOD_0F72_REG_4,
 793   MOD_0F72_REG_6,
 794   MOD_0F73_REG_2,
 795   MOD_0F73_REG_3,
 796   MOD_0F73_REG_6,
 797   MOD_0F73_REG_7,
 798   MOD_0FAE_REG_0,
 799   MOD_0FAE_REG_1,
 800   MOD_0FAE_REG_2,
 801   MOD_0FAE_REG_3,
 802   MOD_0FAE_REG_4,
 803   MOD_0FAE_REG_5,
 804   MOD_0FAE_REG_6,
 805   MOD_0FAE_REG_7,
 806   MOD_0FB2,
 807   MOD_0FB4,
 808   MOD_0FB5,
 809   MOD_0FC3,
 810   MOD_0FC7_REG_3,
 811   MOD_0FC7_REG_4,
 812   MOD_0FC7_REG_5,
 813   MOD_0FC7_REG_6,
 814   MOD_0FC7_REG_7,
 815   MOD_0FD7,
 816   MOD_0FE7_PREFIX_2,
 817   MOD_0FF0_PREFIX_3,
 818   MOD_0F382A_PREFIX_2,
 819   MOD_62_32BIT,
 820   MOD_C4_32BIT,
 821   MOD_C5_32BIT,
 822   MOD_VEX_0F12_PREFIX_0,
 823   MOD_VEX_0F13,
 824   MOD_VEX_0F16_PREFIX_0,
 825   MOD_VEX_0F17,
 826   MOD_VEX_0F2B,
 827   MOD_VEX_W_0_0F41_P_0_LEN_1,
 828   MOD_VEX_W_1_0F41_P_0_LEN_1,
 829   MOD_VEX_W_0_0F41_P_2_LEN_1,
 830   MOD_VEX_W_1_0F41_P_2_LEN_1,
 831   MOD_VEX_W_0_0F42_P_0_LEN_1,
 832   MOD_VEX_W_1_0F42_P_0_LEN_1,
 833   MOD_VEX_W_0_0F42_P_2_LEN_1,
 834   MOD_VEX_W_1_0F42_P_2_LEN_1,
 835   MOD_VEX_W_0_0F44_P_0_LEN_1,
 836   MOD_VEX_W_1_0F44_P_0_LEN_1,
 837   MOD_VEX_W_0_0F44_P_2_LEN_1,
 838   MOD_VEX_W_1_0F44_P_2_LEN_1,
 839   MOD_VEX_W_0_0F45_P_0_LEN_1,
 840   MOD_VEX_W_1_0F45_P_0_LEN_1,
 841   MOD_VEX_W_0_0F45_P_2_LEN_1,
 842   MOD_VEX_W_1_0F45_P_2_LEN_1,
 843   MOD_VEX_W_0_0F46_P_0_LEN_1,
 844   MOD_VEX_W_1_0F46_P_0_LEN_1,
 845   MOD_VEX_W_0_0F46_P_2_LEN_1,
 846   MOD_VEX_W_1_0F46_P_2_LEN_1,
 847   MOD_VEX_W_0_0F47_P_0_LEN_1,
 848   MOD_VEX_W_1_0F47_P_0_LEN_1,
 849   MOD_VEX_W_0_0F47_P_2_LEN_1,
 850   MOD_VEX_W_1_0F47_P_2_LEN_1,
 851   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 852   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 853   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 854   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 855   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 856   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 857   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 858   MOD_VEX_0F50,
 859   MOD_VEX_0F71_REG_2,
 860   MOD_VEX_0F71_REG_4,
 861   MOD_VEX_0F71_REG_6,
 862   MOD_VEX_0F72_REG_2,
 863   MOD_VEX_0F72_REG_4,
 864   MOD_VEX_0F72_REG_6,
 865   MOD_VEX_0F73_REG_2,
 866   MOD_VEX_0F73_REG_3,
 867   MOD_VEX_0F73_REG_6,
 868   MOD_VEX_0F73_REG_7,
 869   MOD_VEX_W_0_0F91_P_0_LEN_0,
 870   MOD_VEX_W_1_0F91_P_0_LEN_0,
 871   MOD_VEX_W_0_0F91_P_2_LEN_0,
 872   MOD_VEX_W_1_0F91_P_2_LEN_0,
 873   MOD_VEX_W_0_0F92_P_0_LEN_0,
 874   MOD_VEX_W_0_0F92_P_2_LEN_0,
 875   MOD_VEX_W_0_0F92_P_3_LEN_0,
 876   MOD_VEX_W_1_0F92_P_3_LEN_0,
 877   MOD_VEX_W_0_0F93_P_0_LEN_0,
 878   MOD_VEX_W_0_0F93_P_2_LEN_0,
 879   MOD_VEX_W_0_0F93_P_3_LEN_0,
 880   MOD_VEX_W_1_0F93_P_3_LEN_0,
 881   MOD_VEX_W_0_0F98_P_0_LEN_0,
 882   MOD_VEX_W_1_0F98_P_0_LEN_0,
 883   MOD_VEX_W_0_0F98_P_2_LEN_0,
 884   MOD_VEX_W_1_0F98_P_2_LEN_0,
 885   MOD_VEX_W_0_0F99_P_0_LEN_0,
 886   MOD_VEX_W_1_0F99_P_0_LEN_0,
 887   MOD_VEX_W_0_0F99_P_2_LEN_0,
 888   MOD_VEX_W_1_0F99_P_2_LEN_0,
 889   MOD_VEX_0FAE_REG_2,
 890   MOD_VEX_0FAE_REG_3,
 891   MOD_VEX_0FD7_PREFIX_2,
 892   MOD_VEX_0FE7_PREFIX_2,
 893   MOD_VEX_0FF0_PREFIX_3,
 894   MOD_VEX_0F381A_PREFIX_2,
 895   MOD_VEX_0F382A_PREFIX_2,
 896   MOD_VEX_0F382C_PREFIX_2,
 897   MOD_VEX_0F382D_PREFIX_2,
 898   MOD_VEX_0F382E_PREFIX_2,
 899   MOD_VEX_0F382F_PREFIX_2,
 900   MOD_VEX_0F385A_PREFIX_2,
 901   MOD_VEX_0F388C_PREFIX_2,
 902   MOD_VEX_0F388E_PREFIX_2,
 903   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 904   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 905   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 906   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 907   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 908   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 909   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 910   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 911
 912   MOD_EVEX_0F10_PREFIX_1,
 913   MOD_EVEX_0F10_PREFIX_3,
 914   MOD_EVEX_0F11_PREFIX_1,
 915   MOD_EVEX_0F11_PREFIX_3,
 916   MOD_EVEX_0F12_PREFIX_0,
 917   MOD_EVEX_0F16_PREFIX_0,
 918   MOD_EVEX_0F38C6_REG_1,
 919   MOD_EVEX_0F38C6_REG_2,
 920   MOD_EVEX_0F38C6_REG_5,
 921   MOD_EVEX_0F38C6_REG_6,
 922   MOD_EVEX_0F38C7_REG_1,
 923   MOD_EVEX_0F38C7_REG_2,
 924   MOD_EVEX_0F38C7_REG_5,
 925   MOD_EVEX_0F38C7_REG_6
 926 };
 927
 928 enum
 929 {
 930   RM_C6_REG_7 = 0,
 931   RM_C7_REG_7,
 932   RM_0F01_REG_0,
 933   RM_0F01_REG_1,
 934   RM_0F01_REG_2,
 935   RM_0F01_REG_3,
 936   RM_0F01_REG_5,
 937   RM_0F01_REG_7,
 938   RM_0FAE_REG_5,
 939   RM_0FAE_REG_6,
 940   RM_0FAE_REG_7
 941 };
 942
 943 enum
 944 {
 945   PREFIX_90 = 0,
 946   PREFIX_0F10,
 947   PREFIX_0F11,
 948   PREFIX_0F12,
 949   PREFIX_0F16,
 950   PREFIX_0F1A,
 951   PREFIX_0F1B,
 952   PREFIX_0F2A,
 953   PREFIX_0F2B,
 954   PREFIX_0F2C,
 955   PREFIX_0F2D,
 956   PREFIX_0F2E,
 957   PREFIX_0F2F,
 958   PREFIX_0F51,
 959   PREFIX_0F52,
 960   PREFIX_0F53,
 961   PREFIX_0F58,
 962   PREFIX_0F59,
 963   PREFIX_0F5A,
 964   PREFIX_0F5B,
 965   PREFIX_0F5C,
 966   PREFIX_0F5D,
 967   PREFIX_0F5E,
 968   PREFIX_0F5F,
 969   PREFIX_0F60,
 970   PREFIX_0F61,
 971   PREFIX_0F62,
 972   PREFIX_0F6C,
 973   PREFIX_0F6D,
 974   PREFIX_0F6F,
 975   PREFIX_0F70,
 976   PREFIX_0F73_REG_3,
 977   PREFIX_0F73_REG_7,
 978   PREFIX_0F78,
 979   PREFIX_0F79,
 980   PREFIX_0F7C,
 981   PREFIX_0F7D,
 982   PREFIX_0F7E,
 983   PREFIX_0F7F,
 984   PREFIX_0FAE_REG_0,
 985   PREFIX_0FAE_REG_1,
 986   PREFIX_0FAE_REG_2,
 987   PREFIX_0FAE_REG_3,
 988   PREFIX_MOD_0_0FAE_REG_4,
 989   PREFIX_MOD_3_0FAE_REG_4,
 990   PREFIX_0FAE_REG_6,
 991   PREFIX_0FAE_REG_7,
 992   PREFIX_0FB8,
 993   PREFIX_0FBC,
 994   PREFIX_0FBD,
 995   PREFIX_0FC2,
 996   PREFIX_MOD_0_0FC3,
 997   PREFIX_MOD_0_0FC7_REG_6,
 998   PREFIX_MOD_3_0FC7_REG_6,
 999   PREFIX_MOD_3_0FC7_REG_7,
1000   PREFIX_0FD0,
1001   PREFIX_0FD6,
1002   PREFIX_0FE6,
1003   PREFIX_0FE7,
1004   PREFIX_0FF0,
1005   PREFIX_0FF7,
1006   PREFIX_0F3810,
1007   PREFIX_0F3814,
1008   PREFIX_0F3815,
1009   PREFIX_0F3817,
1010   PREFIX_0F3820,
1011   PREFIX_0F3821,
1012   PREFIX_0F3822,
1013   PREFIX_0F3823,
1014   PREFIX_0F3824,
1015   PREFIX_0F3825,
1016   PREFIX_0F3828,
1017   PREFIX_0F3829,
1018   PREFIX_0F382A,
1019   PREFIX_0F382B,
1020   PREFIX_0F3830,
1021   PREFIX_0F3831,
1022   PREFIX_0F3832,
1023   PREFIX_0F3833,
1024   PREFIX_0F3834,
1025   PREFIX_0F3835,
1026   PREFIX_0F3837,
1027   PREFIX_0F3838,
1028   PREFIX_0F3839,
1029   PREFIX_0F383A,
1030   PREFIX_0F383B,
1031   PREFIX_0F383C,
1032   PREFIX_0F383D,
1033   PREFIX_0F383E,
1034   PREFIX_0F383F,
1035   PREFIX_0F3840,
1036   PREFIX_0F3841,
1037   PREFIX_0F3880,
1038   PREFIX_0F3881,
1039   PREFIX_0F3882,
1040   PREFIX_0F38C8,
1041   PREFIX_0F38C9,
1042   PREFIX_0F38CA,
1043   PREFIX_0F38CB,
1044   PREFIX_0F38CC,
1045   PREFIX_0F38CD,
1046   PREFIX_0F38DB,
1047   PREFIX_0F38DC,
1048   PREFIX_0F38DD,
1049   PREFIX_0F38DE,
1050   PREFIX_0F38DF,
1051   PREFIX_0F38F0,
1052   PREFIX_0F38F1,
1053   PREFIX_0F38F6,
1054   PREFIX_0F3A08,
1055   PREFIX_0F3A09,
1056   PREFIX_0F3A0A,
1057   PREFIX_0F3A0B,
1058   PREFIX_0F3A0C,
1059   PREFIX_0F3A0D,
1060   PREFIX_0F3A0E,
1061   PREFIX_0F3A14,
1062   PREFIX_0F3A15,
1063   PREFIX_0F3A16,
1064   PREFIX_0F3A17,
1065   PREFIX_0F3A20,
1066   PREFIX_0F3A21,
1067   PREFIX_0F3A22,
1068   PREFIX_0F3A40,
1069   PREFIX_0F3A41,
1070   PREFIX_0F3A42,
1071   PREFIX_0F3A44,
1072   PREFIX_0F3A60,
1073   PREFIX_0F3A61,
1074   PREFIX_0F3A62,
1075   PREFIX_0F3A63,
1076   PREFIX_0F3ACC,
1077   PREFIX_0F3ADF,
1078   PREFIX_VEX_0F10,
1079   PREFIX_VEX_0F11,
1080   PREFIX_VEX_0F12,
1081   PREFIX_VEX_0F16,
1082   PREFIX_VEX_0F2A,
1083   PREFIX_VEX_0F2C,
1084   PREFIX_VEX_0F2D,
1085   PREFIX_VEX_0F2E,
1086   PREFIX_VEX_0F2F,
1087   PREFIX_VEX_0F41,
1088   PREFIX_VEX_0F42,
1089   PREFIX_VEX_0F44,
1090   PREFIX_VEX_0F45,
1091   PREFIX_VEX_0F46,
1092   PREFIX_VEX_0F47,
1093   PREFIX_VEX_0F4A,
1094   PREFIX_VEX_0F4B,
1095   PREFIX_VEX_0F51,
1096   PREFIX_VEX_0F52,
1097   PREFIX_VEX_0F53,
1098   PREFIX_VEX_0F58,
1099   PREFIX_VEX_0F59,
1100   PREFIX_VEX_0F5A,
1101   PREFIX_VEX_0F5B,
1102   PREFIX_VEX_0F5C,
1103   PREFIX_VEX_0F5D,
1104   PREFIX_VEX_0F5E,
1105   PREFIX_VEX_0F5F,
1106   PREFIX_VEX_0F60,
1107   PREFIX_VEX_0F61,
1108   PREFIX_VEX_0F62,
1109   PREFIX_VEX_0F63,
1110   PREFIX_VEX_0F64,
1111   PREFIX_VEX_0F65,
1112   PREFIX_VEX_0F66,
1113   PREFIX_VEX_0F67,
1114   PREFIX_VEX_0F68,
1115   PREFIX_VEX_0F69,
1116   PREFIX_VEX_0F6A,
1117   PREFIX_VEX_0F6B,
1118   PREFIX_VEX_0F6C,
1119   PREFIX_VEX_0F6D,
1120   PREFIX_VEX_0F6E,
1121   PREFIX_VEX_0F6F,
1122   PREFIX_VEX_0F70,
1123   PREFIX_VEX_0F71_REG_2,
1124   PREFIX_VEX_0F71_REG_4,
1125   PREFIX_VEX_0F71_REG_6,
1126   PREFIX_VEX_0F72_REG_2,
1127   PREFIX_VEX_0F72_REG_4,
1128   PREFIX_VEX_0F72_REG_6,
1129   PREFIX_VEX_0F73_REG_2,
1130   PREFIX_VEX_0F73_REG_3,
1131   PREFIX_VEX_0F73_REG_6,
1132   PREFIX_VEX_0F73_REG_7,
1133   PREFIX_VEX_0F74,
1134   PREFIX_VEX_0F75,
1135   PREFIX_VEX_0F76,
1136   PREFIX_VEX_0F77,
1137   PREFIX_VEX_0F7C,
1138   PREFIX_VEX_0F7D,
1139   PREFIX_VEX_0F7E,
1140   PREFIX_VEX_0F7F,
1141   PREFIX_VEX_0F90,
1142   PREFIX_VEX_0F91,
1143   PREFIX_VEX_0F92,
1144   PREFIX_VEX_0F93,
1145   PREFIX_VEX_0F98,
1146   PREFIX_VEX_0F99,
1147   PREFIX_VEX_0FC2,
1148   PREFIX_VEX_0FC4,
1149   PREFIX_VEX_0FC5,
1150   PREFIX_VEX_0FD0,
1151   PREFIX_VEX_0FD1,
1152   PREFIX_VEX_0FD2,
1153   PREFIX_VEX_0FD3,
1154   PREFIX_VEX_0FD4,
1155   PREFIX_VEX_0FD5,
1156   PREFIX_VEX_0FD6,
1157   PREFIX_VEX_0FD7,
1158   PREFIX_VEX_0FD8,
1159   PREFIX_VEX_0FD9,
1160   PREFIX_VEX_0FDA,
1161   PREFIX_VEX_0FDB,
1162   PREFIX_VEX_0FDC,
1163   PREFIX_VEX_0FDD,
1164   PREFIX_VEX_0FDE,
1165   PREFIX_VEX_0FDF,
1166   PREFIX_VEX_0FE0,
1167   PREFIX_VEX_0FE1,
1168   PREFIX_VEX_0FE2,
1169   PREFIX_VEX_0FE3,
1170   PREFIX_VEX_0FE4,
1171   PREFIX_VEX_0FE5,
1172   PREFIX_VEX_0FE6,
1173   PREFIX_VEX_0FE7,
1174   PREFIX_VEX_0FE8,
1175   PREFIX_VEX_0FE9,
1176   PREFIX_VEX_0FEA,
1177   PREFIX_VEX_0FEB,
1178   PREFIX_VEX_0FEC,
1179   PREFIX_VEX_0FED,
1180   PREFIX_VEX_0FEE,
1181   PREFIX_VEX_0FEF,
1182   PREFIX_VEX_0FF0,
1183   PREFIX_VEX_0FF1,
1184   PREFIX_VEX_0FF2,
1185   PREFIX_VEX_0FF3,
1186   PREFIX_VEX_0FF4,
1187   PREFIX_VEX_0FF5,
1188   PREFIX_VEX_0FF6,
1189   PREFIX_VEX_0FF7,
1190   PREFIX_VEX_0FF8,
1191   PREFIX_VEX_0FF9,
1192   PREFIX_VEX_0FFA,
1193   PREFIX_VEX_0FFB,
1194   PREFIX_VEX_0FFC,
1195   PREFIX_VEX_0FFD,
1196   PREFIX_VEX_0FFE,
1197   PREFIX_VEX_0F3800,
1198   PREFIX_VEX_0F3801,
1199   PREFIX_VEX_0F3802,
1200   PREFIX_VEX_0F3803,
1201   PREFIX_VEX_0F3804,
1202   PREFIX_VEX_0F3805,
1203   PREFIX_VEX_0F3806,
1204   PREFIX_VEX_0F3807,
1205   PREFIX_VEX_0F3808,
1206   PREFIX_VEX_0F3809,
1207   PREFIX_VEX_0F380A,
1208   PREFIX_VEX_0F380B,
1209   PREFIX_VEX_0F380C,
1210   PREFIX_VEX_0F380D,
1211   PREFIX_VEX_0F380E,
1212   PREFIX_VEX_0F380F,
1213   PREFIX_VEX_0F3813,
1214   PREFIX_VEX_0F3816,
1215   PREFIX_VEX_0F3817,
1216   PREFIX_VEX_0F3818,
1217   PREFIX_VEX_0F3819,
1218   PREFIX_VEX_0F381A,
1219   PREFIX_VEX_0F381C,
1220   PREFIX_VEX_0F381D,
1221   PREFIX_VEX_0F381E,
1222   PREFIX_VEX_0F3820,
1223   PREFIX_VEX_0F3821,
1224   PREFIX_VEX_0F3822,
1225   PREFIX_VEX_0F3823,
1226   PREFIX_VEX_0F3824,
1227   PREFIX_VEX_0F3825,
1228   PREFIX_VEX_0F3828,
1229   PREFIX_VEX_0F3829,
1230   PREFIX_VEX_0F382A,
1231   PREFIX_VEX_0F382B,
1232   PREFIX_VEX_0F382C,
1233   PREFIX_VEX_0F382D,
1234   PREFIX_VEX_0F382E,
1235   PREFIX_VEX_0F382F,
1236   PREFIX_VEX_0F3830,
1237   PREFIX_VEX_0F3831,
1238   PREFIX_VEX_0F3832,
1239   PREFIX_VEX_0F3833,
1240   PREFIX_VEX_0F3834,
1241   PREFIX_VEX_0F3835,
1242   PREFIX_VEX_0F3836,
1243   PREFIX_VEX_0F3837,
1244   PREFIX_VEX_0F3838,
1245   PREFIX_VEX_0F3839,
1246   PREFIX_VEX_0F383A,
1247   PREFIX_VEX_0F383B,
1248   PREFIX_VEX_0F383C,
1249   PREFIX_VEX_0F383D,
1250   PREFIX_VEX_0F383E,
1251   PREFIX_VEX_0F383F,
1252   PREFIX_VEX_0F3840,
1253   PREFIX_VEX_0F3841,
1254   PREFIX_VEX_0F3845,
1255   PREFIX_VEX_0F3846,
1256   PREFIX_VEX_0F3847,
1257   PREFIX_VEX_0F3858,
1258   PREFIX_VEX_0F3859,
1259   PREFIX_VEX_0F385A,
1260   PREFIX_VEX_0F3878,
1261   PREFIX_VEX_0F3879,
1262   PREFIX_VEX_0F388C,
1263   PREFIX_VEX_0F388E,
1264   PREFIX_VEX_0F3890,
1265   PREFIX_VEX_0F3891,
1266   PREFIX_VEX_0F3892,
1267   PREFIX_VEX_0F3893,
1268   PREFIX_VEX_0F3896,
1269   PREFIX_VEX_0F3897,
1270   PREFIX_VEX_0F3898,
1271   PREFIX_VEX_0F3899,
1272   PREFIX_VEX_0F389A,
1273   PREFIX_VEX_0F389B,
1274   PREFIX_VEX_0F389C,
1275   PREFIX_VEX_0F389D,
1276   PREFIX_VEX_0F389E,
1277   PREFIX_VEX_0F389F,
1278   PREFIX_VEX_0F38A6,
1279   PREFIX_VEX_0F38A7,
1280   PREFIX_VEX_0F38A8,
1281   PREFIX_VEX_0F38A9,
1282   PREFIX_VEX_0F38AA,
1283   PREFIX_VEX_0F38AB,
1284   PREFIX_VEX_0F38AC,
1285   PREFIX_VEX_0F38AD,
1286   PREFIX_VEX_0F38AE,
1287   PREFIX_VEX_0F38AF,
1288   PREFIX_VEX_0F38B6,
1289   PREFIX_VEX_0F38B7,
1290   PREFIX_VEX_0F38B8,
1291   PREFIX_VEX_0F38B9,
1292   PREFIX_VEX_0F38BA,
1293   PREFIX_VEX_0F38BB,
1294   PREFIX_VEX_0F38BC,
1295   PREFIX_VEX_0F38BD,
1296   PREFIX_VEX_0F38BE,
1297   PREFIX_VEX_0F38BF,
1298   PREFIX_VEX_0F38DB,
1299   PREFIX_VEX_0F38DC,
1300   PREFIX_VEX_0F38DD,
1301   PREFIX_VEX_0F38DE,
1302   PREFIX_VEX_0F38DF,
1303   PREFIX_VEX_0F38F2,
1304   PREFIX_VEX_0F38F3_REG_1,
1305   PREFIX_VEX_0F38F3_REG_2,
1306   PREFIX_VEX_0F38F3_REG_3,
1307   PREFIX_VEX_0F38F5,
1308   PREFIX_VEX_0F38F6,
1309   PREFIX_VEX_0F38F7,
1310   PREFIX_VEX_0F3A00,
1311   PREFIX_VEX_0F3A01,
1312   PREFIX_VEX_0F3A02,
1313   PREFIX_VEX_0F3A04,
1314   PREFIX_VEX_0F3A05,
1315   PREFIX_VEX_0F3A06,
1316   PREFIX_VEX_0F3A08,
1317   PREFIX_VEX_0F3A09,
1318   PREFIX_VEX_0F3A0A,
1319   PREFIX_VEX_0F3A0B,
1320   PREFIX_VEX_0F3A0C,
1321   PREFIX_VEX_0F3A0D,
1322   PREFIX_VEX_0F3A0E,
1323   PREFIX_VEX_0F3A0F,
1324   PREFIX_VEX_0F3A14,
1325   PREFIX_VEX_0F3A15,
1326   PREFIX_VEX_0F3A16,
1327   PREFIX_VEX_0F3A17,
1328   PREFIX_VEX_0F3A18,
1329   PREFIX_VEX_0F3A19,
1330   PREFIX_VEX_0F3A1D,
1331   PREFIX_VEX_0F3A20,
1332   PREFIX_VEX_0F3A21,
1333   PREFIX_VEX_0F3A22,
1334   PREFIX_VEX_0F3A30,
1335   PREFIX_VEX_0F3A31,
1336   PREFIX_VEX_0F3A32,
1337   PREFIX_VEX_0F3A33,
1338   PREFIX_VEX_0F3A38,
1339   PREFIX_VEX_0F3A39,
1340   PREFIX_VEX_0F3A40,
1341   PREFIX_VEX_0F3A41,
1342   PREFIX_VEX_0F3A42,
1343   PREFIX_VEX_0F3A44,
1344   PREFIX_VEX_0F3A46,
1345   PREFIX_VEX_0F3A48,
1346   PREFIX_VEX_0F3A49,
1347   PREFIX_VEX_0F3A4A,
1348   PREFIX_VEX_0F3A4B,
1349   PREFIX_VEX_0F3A4C,
1350   PREFIX_VEX_0F3A5C,
1351   PREFIX_VEX_0F3A5D,
1352   PREFIX_VEX_0F3A5E,
1353   PREFIX_VEX_0F3A5F,
1354   PREFIX_VEX_0F3A60,
1355   PREFIX_VEX_0F3A61,
1356   PREFIX_VEX_0F3A62,
1357   PREFIX_VEX_0F3A63,
1358   PREFIX_VEX_0F3A68,
1359   PREFIX_VEX_0F3A69,
1360   PREFIX_VEX_0F3A6A,
1361   PREFIX_VEX_0F3A6B,
1362   PREFIX_VEX_0F3A6C,
1363   PREFIX_VEX_0F3A6D,
1364   PREFIX_VEX_0F3A6E,
1365   PREFIX_VEX_0F3A6F,
1366   PREFIX_VEX_0F3A78,
1367   PREFIX_VEX_0F3A79,
1368   PREFIX_VEX_0F3A7A,
1369   PREFIX_VEX_0F3A7B,
1370   PREFIX_VEX_0F3A7C,
1371   PREFIX_VEX_0F3A7D,
1372   PREFIX_VEX_0F3A7E,
1373   PREFIX_VEX_0F3A7F,
1374   PREFIX_VEX_0F3ADF,
1375   PREFIX_VEX_0F3AF0,
1376
1377   PREFIX_EVEX_0F10,
1378   PREFIX_EVEX_0F11,
1379   PREFIX_EVEX_0F12,
1380   PREFIX_EVEX_0F13,
1381   PREFIX_EVEX_0F14,
1382   PREFIX_EVEX_0F15,
1383   PREFIX_EVEX_0F16,
1384   PREFIX_EVEX_0F17,
1385   PREFIX_EVEX_0F28,
1386   PREFIX_EVEX_0F29,
1387   PREFIX_EVEX_0F2A,
1388   PREFIX_EVEX_0F2B,
1389   PREFIX_EVEX_0F2C,
1390   PREFIX_EVEX_0F2D,
1391   PREFIX_EVEX_0F2E,
1392   PREFIX_EVEX_0F2F,
1393   PREFIX_EVEX_0F51,
1394   PREFIX_EVEX_0F54,
1395   PREFIX_EVEX_0F55,
1396   PREFIX_EVEX_0F56,
1397   PREFIX_EVEX_0F57,
1398   PREFIX_EVEX_0F58,
1399   PREFIX_EVEX_0F59,
1400   PREFIX_EVEX_0F5A,
1401   PREFIX_EVEX_0F5B,
1402   PREFIX_EVEX_0F5C,
1403   PREFIX_EVEX_0F5D,
1404   PREFIX_EVEX_0F5E,
1405   PREFIX_EVEX_0F5F,
1406   PREFIX_EVEX_0F60,
1407   PREFIX_EVEX_0F61,
1408   PREFIX_EVEX_0F62,
1409   PREFIX_EVEX_0F63,
1410   PREFIX_EVEX_0F64,
1411   PREFIX_EVEX_0F65,
1412   PREFIX_EVEX_0F66,
1413   PREFIX_EVEX_0F67,
1414   PREFIX_EVEX_0F68,
1415   PREFIX_EVEX_0F69,
1416   PREFIX_EVEX_0F6A,
1417   PREFIX_EVEX_0F6B,
1418   PREFIX_EVEX_0F6C,
1419   PREFIX_EVEX_0F6D,
1420   PREFIX_EVEX_0F6E,
1421   PREFIX_EVEX_0F6F,
1422   PREFIX_EVEX_0F70,
1423   PREFIX_EVEX_0F71_REG_2,
1424   PREFIX_EVEX_0F71_REG_4,
1425   PREFIX_EVEX_0F71_REG_6,
1426   PREFIX_EVEX_0F72_REG_0,
1427   PREFIX_EVEX_0F72_REG_1,
1428   PREFIX_EVEX_0F72_REG_2,
1429   PREFIX_EVEX_0F72_REG_4,
1430   PREFIX_EVEX_0F72_REG_6,
1431   PREFIX_EVEX_0F73_REG_2,
1432   PREFIX_EVEX_0F73_REG_3,
1433   PREFIX_EVEX_0F73_REG_6,
1434   PREFIX_EVEX_0F73_REG_7,
1435   PREFIX_EVEX_0F74,
1436   PREFIX_EVEX_0F75,
1437   PREFIX_EVEX_0F76,
1438   PREFIX_EVEX_0F78,
1439   PREFIX_EVEX_0F79,
1440   PREFIX_EVEX_0F7A,
1441   PREFIX_EVEX_0F7B,
1442   PREFIX_EVEX_0F7E,
1443   PREFIX_EVEX_0F7F,
1444   PREFIX_EVEX_0FC2,
1445   PREFIX_EVEX_0FC4,
1446   PREFIX_EVEX_0FC5,
1447   PREFIX_EVEX_0FC6,
1448   PREFIX_EVEX_0FD1,
1449   PREFIX_EVEX_0FD2,
1450   PREFIX_EVEX_0FD3,
1451   PREFIX_EVEX_0FD4,
1452   PREFIX_EVEX_0FD5,
1453   PREFIX_EVEX_0FD6,
1454   PREFIX_EVEX_0FD8,
1455   PREFIX_EVEX_0FD9,
1456   PREFIX_EVEX_0FDA,
1457   PREFIX_EVEX_0FDB,
1458   PREFIX_EVEX_0FDC,
1459   PREFIX_EVEX_0FDD,
1460   PREFIX_EVEX_0FDE,
1461   PREFIX_EVEX_0FDF,
1462   PREFIX_EVEX_0FE0,
1463   PREFIX_EVEX_0FE1,
1464   PREFIX_EVEX_0FE2,
1465   PREFIX_EVEX_0FE3,
1466   PREFIX_EVEX_0FE4,
1467   PREFIX_EVEX_0FE5,
1468   PREFIX_EVEX_0FE6,
1469   PREFIX_EVEX_0FE7,
1470   PREFIX_EVEX_0FE8,
1471   PREFIX_EVEX_0FE9,
1472   PREFIX_EVEX_0FEA,
1473   PREFIX_EVEX_0FEB,
1474   PREFIX_EVEX_0FEC,
1475   PREFIX_EVEX_0FED,
1476   PREFIX_EVEX_0FEE,
1477   PREFIX_EVEX_0FEF,
1478   PREFIX_EVEX_0FF1,
1479   PREFIX_EVEX_0FF2,
1480   PREFIX_EVEX_0FF3,
1481   PREFIX_EVEX_0FF4,
1482   PREFIX_EVEX_0FF5,
1483   PREFIX_EVEX_0FF6,
1484   PREFIX_EVEX_0FF8,
1485   PREFIX_EVEX_0FF9,
1486   PREFIX_EVEX_0FFA,
1487   PREFIX_EVEX_0FFB,
1488   PREFIX_EVEX_0FFC,
1489   PREFIX_EVEX_0FFD,
1490   PREFIX_EVEX_0FFE,
1491   PREFIX_EVEX_0F3800,
1492   PREFIX_EVEX_0F3804,
1493   PREFIX_EVEX_0F380B,
1494   PREFIX_EVEX_0F380C,
1495   PREFIX_EVEX_0F380D,
1496   PREFIX_EVEX_0F3810,
1497   PREFIX_EVEX_0F3811,
1498   PREFIX_EVEX_0F3812,
1499   PREFIX_EVEX_0F3813,
1500   PREFIX_EVEX_0F3814,
1501   PREFIX_EVEX_0F3815,
1502   PREFIX_EVEX_0F3816,
1503   PREFIX_EVEX_0F3818,
1504   PREFIX_EVEX_0F3819,
1505   PREFIX_EVEX_0F381A,
1506   PREFIX_EVEX_0F381B,
1507   PREFIX_EVEX_0F381C,
1508   PREFIX_EVEX_0F381D,
1509   PREFIX_EVEX_0F381E,
1510   PREFIX_EVEX_0F381F,
1511   PREFIX_EVEX_0F3820,
1512   PREFIX_EVEX_0F3821,
1513   PREFIX_EVEX_0F3822,
1514   PREFIX_EVEX_0F3823,
1515   PREFIX_EVEX_0F3824,
1516   PREFIX_EVEX_0F3825,
1517   PREFIX_EVEX_0F3826,
1518   PREFIX_EVEX_0F3827,
1519   PREFIX_EVEX_0F3828,
1520   PREFIX_EVEX_0F3829,
1521   PREFIX_EVEX_0F382A,
1522   PREFIX_EVEX_0F382B,
1523   PREFIX_EVEX_0F382C,
1524   PREFIX_EVEX_0F382D,
1525   PREFIX_EVEX_0F3830,
1526   PREFIX_EVEX_0F3831,
1527   PREFIX_EVEX_0F3832,
1528   PREFIX_EVEX_0F3833,
1529   PREFIX_EVEX_0F3834,
1530   PREFIX_EVEX_0F3835,
1531   PREFIX_EVEX_0F3836,
1532   PREFIX_EVEX_0F3837,
1533   PREFIX_EVEX_0F3838,
1534   PREFIX_EVEX_0F3839,
1535   PREFIX_EVEX_0F383A,
1536   PREFIX_EVEX_0F383B,
1537   PREFIX_EVEX_0F383C,
1538   PREFIX_EVEX_0F383D,
1539   PREFIX_EVEX_0F383E,
1540   PREFIX_EVEX_0F383F,
1541   PREFIX_EVEX_0F3840,
1542   PREFIX_EVEX_0F3842,
1543   PREFIX_EVEX_0F3843,
1544   PREFIX_EVEX_0F3844,
1545   PREFIX_EVEX_0F3845,
1546   PREFIX_EVEX_0F3846,
1547   PREFIX_EVEX_0F3847,
1548   PREFIX_EVEX_0F384C,
1549   PREFIX_EVEX_0F384D,
1550   PREFIX_EVEX_0F384E,
1551   PREFIX_EVEX_0F384F,
1552   PREFIX_EVEX_0F3852,
1553   PREFIX_EVEX_0F3853,
1554   PREFIX_EVEX_0F3858,
1555   PREFIX_EVEX_0F3859,
1556   PREFIX_EVEX_0F385A,
1557   PREFIX_EVEX_0F385B,
1558   PREFIX_EVEX_0F3864,
1559   PREFIX_EVEX_0F3865,
1560   PREFIX_EVEX_0F3866,
1561   PREFIX_EVEX_0F3875,
1562   PREFIX_EVEX_0F3876,
1563   PREFIX_EVEX_0F3877,
1564   PREFIX_EVEX_0F3878,
1565   PREFIX_EVEX_0F3879,
1566   PREFIX_EVEX_0F387A,
1567   PREFIX_EVEX_0F387B,
1568   PREFIX_EVEX_0F387C,
1569   PREFIX_EVEX_0F387D,
1570   PREFIX_EVEX_0F387E,
1571   PREFIX_EVEX_0F387F,
1572   PREFIX_EVEX_0F3883,
1573   PREFIX_EVEX_0F3888,
1574   PREFIX_EVEX_0F3889,
1575   PREFIX_EVEX_0F388A,
1576   PREFIX_EVEX_0F388B,
1577   PREFIX_EVEX_0F388D,
1578   PREFIX_EVEX_0F3890,
1579   PREFIX_EVEX_0F3891,
1580   PREFIX_EVEX_0F3892,
1581   PREFIX_EVEX_0F3893,
1582   PREFIX_EVEX_0F3896,
1583   PREFIX_EVEX_0F3897,
1584   PREFIX_EVEX_0F3898,
1585   PREFIX_EVEX_0F3899,
1586   PREFIX_EVEX_0F389A,
1587   PREFIX_EVEX_0F389B,
1588   PREFIX_EVEX_0F389C,
1589   PREFIX_EVEX_0F389D,
1590   PREFIX_EVEX_0F389E,
1591   PREFIX_EVEX_0F389F,
1592   PREFIX_EVEX_0F38A0,
1593   PREFIX_EVEX_0F38A1,
1594   PREFIX_EVEX_0F38A2,
1595   PREFIX_EVEX_0F38A3,
1596   PREFIX_EVEX_0F38A6,
1597   PREFIX_EVEX_0F38A7,
1598   PREFIX_EVEX_0F38A8,
1599   PREFIX_EVEX_0F38A9,
1600   PREFIX_EVEX_0F38AA,
1601   PREFIX_EVEX_0F38AB,
1602   PREFIX_EVEX_0F38AC,
1603   PREFIX_EVEX_0F38AD,
1604   PREFIX_EVEX_0F38AE,
1605   PREFIX_EVEX_0F38AF,
1606   PREFIX_EVEX_0F38B4,
1607   PREFIX_EVEX_0F38B5,
1608   PREFIX_EVEX_0F38B6,
1609   PREFIX_EVEX_0F38B7,
1610   PREFIX_EVEX_0F38B8,
1611   PREFIX_EVEX_0F38B9,
1612   PREFIX_EVEX_0F38BA,
1613   PREFIX_EVEX_0F38BB,
1614   PREFIX_EVEX_0F38BC,
1615   PREFIX_EVEX_0F38BD,
1616   PREFIX_EVEX_0F38BE,
1617   PREFIX_EVEX_0F38BF,
1618   PREFIX_EVEX_0F38C4,
1619   PREFIX_EVEX_0F38C6_REG_1,
1620   PREFIX_EVEX_0F38C6_REG_2,
1621   PREFIX_EVEX_0F38C6_REG_5,
1622   PREFIX_EVEX_0F38C6_REG_6,
1623   PREFIX_EVEX_0F38C7_REG_1,
1624   PREFIX_EVEX_0F38C7_REG_2,
1625   PREFIX_EVEX_0F38C7_REG_5,
1626   PREFIX_EVEX_0F38C7_REG_6,
1627   PREFIX_EVEX_0F38C8,
1628   PREFIX_EVEX_0F38CA,
1629   PREFIX_EVEX_0F38CB,
1630   PREFIX_EVEX_0F38CC,
1631   PREFIX_EVEX_0F38CD,
1632
1633   PREFIX_EVEX_0F3A00,
1634   PREFIX_EVEX_0F3A01,
1635   PREFIX_EVEX_0F3A03,
1636   PREFIX_EVEX_0F3A04,
1637   PREFIX_EVEX_0F3A05,
1638   PREFIX_EVEX_0F3A08,
1639   PREFIX_EVEX_0F3A09,
1640   PREFIX_EVEX_0F3A0A,
1641   PREFIX_EVEX_0F3A0B,
1642   PREFIX_EVEX_0F3A0F,
1643   PREFIX_EVEX_0F3A14,
1644   PREFIX_EVEX_0F3A15,
1645   PREFIX_EVEX_0F3A16,
1646   PREFIX_EVEX_0F3A17,
1647   PREFIX_EVEX_0F3A18,
1648   PREFIX_EVEX_0F3A19,
1649   PREFIX_EVEX_0F3A1A,
1650   PREFIX_EVEX_0F3A1B,
1651   PREFIX_EVEX_0F3A1D,
1652   PREFIX_EVEX_0F3A1E,
1653   PREFIX_EVEX_0F3A1F,
1654   PREFIX_EVEX_0F3A20,
1655   PREFIX_EVEX_0F3A21,
1656   PREFIX_EVEX_0F3A22,
1657   PREFIX_EVEX_0F3A23,
1658   PREFIX_EVEX_0F3A25,
1659   PREFIX_EVEX_0F3A26,
1660   PREFIX_EVEX_0F3A27,
1661   PREFIX_EVEX_0F3A38,
1662   PREFIX_EVEX_0F3A39,
1663   PREFIX_EVEX_0F3A3A,
1664   PREFIX_EVEX_0F3A3B,
1665   PREFIX_EVEX_0F3A3E,
1666   PREFIX_EVEX_0F3A3F,
1667   PREFIX_EVEX_0F3A42,
1668   PREFIX_EVEX_0F3A43,
1669   PREFIX_EVEX_0F3A50,
1670   PREFIX_EVEX_0F3A51,
1671   PREFIX_EVEX_0F3A54,
1672   PREFIX_EVEX_0F3A55,
1673   PREFIX_EVEX_0F3A56,
1674   PREFIX_EVEX_0F3A57,
1675   PREFIX_EVEX_0F3A66,
1676   PREFIX_EVEX_0F3A67
1677 };
1678
1679 enum
1680 {
1681   X86_64_06 = 0,
1682   X86_64_07,
1683   X86_64_0D,
1684   X86_64_16,
1685   X86_64_17,
1686   X86_64_1E,
1687   X86_64_1F,
1688   X86_64_27,
1689   X86_64_2F,
1690   X86_64_37,
1691   X86_64_3F,
1692   X86_64_60,
1693   X86_64_61,
1694   X86_64_62,
1695   X86_64_63,
1696   X86_64_6D,
1697   X86_64_6F,
1698   X86_64_82_REG_0,
1699   X86_64_82_REG_1,
1700   X86_64_82_REG_2,
1701   X86_64_82_REG_3,
1702   X86_64_82_REG_4,
1703   X86_64_82_REG_5,
1704   X86_64_82_REG_6,
1705   X86_64_82_REG_7,
1706   X86_64_9A,
1707   X86_64_C4,
1708   X86_64_C5,
1709   X86_64_CE,
1710   X86_64_D4,
1711   X86_64_D5,
1712   X86_64_E8,
1713   X86_64_E9,
1714   X86_64_EA,
1715   X86_64_0F01_REG_0,
1716   X86_64_0F01_REG_1,
1717   X86_64_0F01_REG_2,
1718   X86_64_0F01_REG_3
1719 };
1720
1721 enum
1722 {
1723   THREE_BYTE_0F38 = 0,
1724   THREE_BYTE_0F3A,
1725   THREE_BYTE_0F7A
1726 };
1727
1728 enum
1729 {
1730   XOP_08 = 0,
1731   XOP_09,
1732   XOP_0A
1733 };
1734
1735 enum
1736 {
1737   VEX_0F = 0,
1738   VEX_0F38,
1739   VEX_0F3A
1740 };
1741
1742 enum
1743 {
1744   EVEX_0F = 0,
1745   EVEX_0F38,
1746   EVEX_0F3A
1747 };
1748
1749 enum
1750 {
1751   VEX_LEN_0F10_P_1 = 0,
1752   VEX_LEN_0F10_P_3,
1753   VEX_LEN_0F11_P_1,
1754   VEX_LEN_0F11_P_3,
1755   VEX_LEN_0F12_P_0_M_0,
1756   VEX_LEN_0F12_P_0_M_1,
1757   VEX_LEN_0F12_P_2,
1758   VEX_LEN_0F13_M_0,
1759   VEX_LEN_0F16_P_0_M_0,
1760   VEX_LEN_0F16_P_0_M_1,
1761   VEX_LEN_0F16_P_2,
1762   VEX_LEN_0F17_M_0,
1763   VEX_LEN_0F2A_P_1,
1764   VEX_LEN_0F2A_P_3,
1765   VEX_LEN_0F2C_P_1,
1766   VEX_LEN_0F2C_P_3,
1767   VEX_LEN_0F2D_P_1,
1768   VEX_LEN_0F2D_P_3,
1769   VEX_LEN_0F2E_P_0,
1770   VEX_LEN_0F2E_P_2,
1771   VEX_LEN_0F2F_P_0,
1772   VEX_LEN_0F2F_P_2,
1773   VEX_LEN_0F41_P_0,
1774   VEX_LEN_0F41_P_2,
1775   VEX_LEN_0F42_P_0,
1776   VEX_LEN_0F42_P_2,
1777   VEX_LEN_0F44_P_0,
1778   VEX_LEN_0F44_P_2,
1779   VEX_LEN_0F45_P_0,
1780   VEX_LEN_0F45_P_2,
1781   VEX_LEN_0F46_P_0,
1782   VEX_LEN_0F46_P_2,
1783   VEX_LEN_0F47_P_0,
1784   VEX_LEN_0F47_P_2,
1785   VEX_LEN_0F4A_P_0,
1786   VEX_LEN_0F4A_P_2,
1787   VEX_LEN_0F4B_P_0,
1788   VEX_LEN_0F4B_P_2,
1789   VEX_LEN_0F51_P_1,
1790   VEX_LEN_0F51_P_3,
1791   VEX_LEN_0F52_P_1,
1792   VEX_LEN_0F53_P_1,
1793   VEX_LEN_0F58_P_1,
1794   VEX_LEN_0F58_P_3,
1795   VEX_LEN_0F59_P_1,
1796   VEX_LEN_0F59_P_3,
1797   VEX_LEN_0F5A_P_1,
1798   VEX_LEN_0F5A_P_3,
1799   VEX_LEN_0F5C_P_1,
1800   VEX_LEN_0F5C_P_3,
1801   VEX_LEN_0F5D_P_1,
1802   VEX_LEN_0F5D_P_3,
1803   VEX_LEN_0F5E_P_1,
1804   VEX_LEN_0F5E_P_3,
1805   VEX_LEN_0F5F_P_1,
1806   VEX_LEN_0F5F_P_3,
1807   VEX_LEN_0F6E_P_2,
1808   VEX_LEN_0F7E_P_1,
1809   VEX_LEN_0F7E_P_2,
1810   VEX_LEN_0F90_P_0,
1811   VEX_LEN_0F90_P_2,
1812   VEX_LEN_0F91_P_0,
1813   VEX_LEN_0F91_P_2,
1814   VEX_LEN_0F92_P_0,
1815   VEX_LEN_0F92_P_2,
1816   VEX_LEN_0F92_P_3,
1817   VEX_LEN_0F93_P_0,
1818   VEX_LEN_0F93_P_2,
1819   VEX_LEN_0F93_P_3,
1820   VEX_LEN_0F98_P_0,
1821   VEX_LEN_0F98_P_2,
1822   VEX_LEN_0F99_P_0,
1823   VEX_LEN_0F99_P_2,
1824   VEX_LEN_0FAE_R_2_M_0,
1825   VEX_LEN_0FAE_R_3_M_0,
1826   VEX_LEN_0FC2_P_1,
1827   VEX_LEN_0FC2_P_3,
1828   VEX_LEN_0FC4_P_2,
1829   VEX_LEN_0FC5_P_2,
1830   VEX_LEN_0FD6_P_2,
1831   VEX_LEN_0FF7_P_2,
1832   VEX_LEN_0F3816_P_2,
1833   VEX_LEN_0F3819_P_2,
1834   VEX_LEN_0F381A_P_2_M_0,
1835   VEX_LEN_0F3836_P_2,
1836   VEX_LEN_0F3841_P_2,
1837   VEX_LEN_0F385A_P_2_M_0,
1838   VEX_LEN_0F38DB_P_2,
1839   VEX_LEN_0F38DC_P_2,
1840   VEX_LEN_0F38DD_P_2,
1841   VEX_LEN_0F38DE_P_2,
1842   VEX_LEN_0F38DF_P_2,
1843   VEX_LEN_0F38F2_P_0,
1844   VEX_LEN_0F38F3_R_1_P_0,
1845   VEX_LEN_0F38F3_R_2_P_0,
1846   VEX_LEN_0F38F3_R_3_P_0,
1847   VEX_LEN_0F38F5_P_0,
1848   VEX_LEN_0F38F5_P_1,
1849   VEX_LEN_0F38F5_P_3,
1850   VEX_LEN_0F38F6_P_3,
1851   VEX_LEN_0F38F7_P_0,
1852   VEX_LEN_0F38F7_P_1,
1853   VEX_LEN_0F38F7_P_2,
1854   VEX_LEN_0F38F7_P_3,
1855   VEX_LEN_0F3A00_P_2,
1856   VEX_LEN_0F3A01_P_2,
1857   VEX_LEN_0F3A06_P_2,
1858   VEX_LEN_0F3A0A_P_2,
1859   VEX_LEN_0F3A0B_P_2,
1860   VEX_LEN_0F3A14_P_2,
1861   VEX_LEN_0F3A15_P_2,
1862   VEX_LEN_0F3A16_P_2,
1863   VEX_LEN_0F3A17_P_2,
1864   VEX_LEN_0F3A18_P_2,
1865   VEX_LEN_0F3A19_P_2,
1866   VEX_LEN_0F3A20_P_2,
1867   VEX_LEN_0F3A21_P_2,
1868   VEX_LEN_0F3A22_P_2,
1869   VEX_LEN_0F3A30_P_2,
1870   VEX_LEN_0F3A31_P_2,
1871   VEX_LEN_0F3A32_P_2,
1872   VEX_LEN_0F3A33_P_2,
1873   VEX_LEN_0F3A38_P_2,
1874   VEX_LEN_0F3A39_P_2,
1875   VEX_LEN_0F3A41_P_2,
1876   VEX_LEN_0F3A44_P_2,
1877   VEX_LEN_0F3A46_P_2,
1878   VEX_LEN_0F3A60_P_2,
1879   VEX_LEN_0F3A61_P_2,
1880   VEX_LEN_0F3A62_P_2,
1881   VEX_LEN_0F3A63_P_2,
1882   VEX_LEN_0F3A6A_P_2,
1883   VEX_LEN_0F3A6B_P_2,
1884   VEX_LEN_0F3A6E_P_2,
1885   VEX_LEN_0F3A6F_P_2,
1886   VEX_LEN_0F3A7A_P_2,
1887   VEX_LEN_0F3A7B_P_2,
1888   VEX_LEN_0F3A7E_P_2,
1889   VEX_LEN_0F3A7F_P_2,
1890   VEX_LEN_0F3ADF_P_2,
1891   VEX_LEN_0F3AF0_P_3,
1892   VEX_LEN_0FXOP_08_CC,
1893   VEX_LEN_0FXOP_08_CD,
1894   VEX_LEN_0FXOP_08_CE,
1895   VEX_LEN_0FXOP_08_CF,
1896   VEX_LEN_0FXOP_08_EC,
1897   VEX_LEN_0FXOP_08_ED,
1898   VEX_LEN_0FXOP_08_EE,
1899   VEX_LEN_0FXOP_08_EF,
1900   VEX_LEN_0FXOP_09_80,
1901   VEX_LEN_0FXOP_09_81
1902 };
1903
1904 enum
1905 {
1906   VEX_W_0F10_P_0 = 0,
1907   VEX_W_0F10_P_1,
1908   VEX_W_0F10_P_2,
1909   VEX_W_0F10_P_3,
1910   VEX_W_0F11_P_0,
1911   VEX_W_0F11_P_1,
1912   VEX_W_0F11_P_2,
1913   VEX_W_0F11_P_3,
1914   VEX_W_0F12_P_0_M_0,
1915   VEX_W_0F12_P_0_M_1,
1916   VEX_W_0F12_P_1,
1917   VEX_W_0F12_P_2,
1918   VEX_W_0F12_P_3,
1919   VEX_W_0F13_M_0,
1920   VEX_W_0F14,
1921   VEX_W_0F15,
1922   VEX_W_0F16_P_0_M_0,
1923   VEX_W_0F16_P_0_M_1,
1924   VEX_W_0F16_P_1,
1925   VEX_W_0F16_P_2,
1926   VEX_W_0F17_M_0,
1927   VEX_W_0F28,
1928   VEX_W_0F29,
1929   VEX_W_0F2B_M_0,
1930   VEX_W_0F2E_P_0,
1931   VEX_W_0F2E_P_2,
1932   VEX_W_0F2F_P_0,
1933   VEX_W_0F2F_P_2,
1934   VEX_W_0F41_P_0_LEN_1,
1935   VEX_W_0F41_P_2_LEN_1,
1936   VEX_W_0F42_P_0_LEN_1,
1937   VEX_W_0F42_P_2_LEN_1,
1938   VEX_W_0F44_P_0_LEN_0,
1939   VEX_W_0F44_P_2_LEN_0,
1940   VEX_W_0F45_P_0_LEN_1,
1941   VEX_W_0F45_P_2_LEN_1,
1942   VEX_W_0F46_P_0_LEN_1,
1943   VEX_W_0F46_P_2_LEN_1,
1944   VEX_W_0F47_P_0_LEN_1,
1945   VEX_W_0F47_P_2_LEN_1,
1946   VEX_W_0F4A_P_0_LEN_1,
1947   VEX_W_0F4A_P_2_LEN_1,
1948   VEX_W_0F4B_P_0_LEN_1,
1949   VEX_W_0F4B_P_2_LEN_1,
1950   VEX_W_0F50_M_0,
1951   VEX_W_0F51_P_0,
1952   VEX_W_0F51_P_1,
1953   VEX_W_0F51_P_2,
1954   VEX_W_0F51_P_3,
1955   VEX_W_0F52_P_0,
1956   VEX_W_0F52_P_1,
1957   VEX_W_0F53_P_0,
1958   VEX_W_0F53_P_1,
1959   VEX_W_0F58_P_0,
1960   VEX_W_0F58_P_1,
1961   VEX_W_0F58_P_2,
1962   VEX_W_0F58_P_3,
1963   VEX_W_0F59_P_0,
1964   VEX_W_0F59_P_1,
1965   VEX_W_0F59_P_2,
1966   VEX_W_0F59_P_3,
1967   VEX_W_0F5A_P_0,
1968   VEX_W_0F5A_P_1,
1969   VEX_W_0F5A_P_3,
1970   VEX_W_0F5B_P_0,
1971   VEX_W_0F5B_P_1,
1972   VEX_W_0F5B_P_2,
1973   VEX_W_0F5C_P_0,
1974   VEX_W_0F5C_P_1,
1975   VEX_W_0F5C_P_2,
1976   VEX_W_0F5C_P_3,
1977   VEX_W_0F5D_P_0,
1978   VEX_W_0F5D_P_1,
1979   VEX_W_0F5D_P_2,
1980   VEX_W_0F5D_P_3,
1981   VEX_W_0F5E_P_0,
1982   VEX_W_0F5E_P_1,
1983   VEX_W_0F5E_P_2,
1984   VEX_W_0F5E_P_3,
1985   VEX_W_0F5F_P_0,
1986   VEX_W_0F5F_P_1,
1987   VEX_W_0F5F_P_2,
1988   VEX_W_0F5F_P_3,
1989   VEX_W_0F60_P_2,
1990   VEX_W_0F61_P_2,
1991   VEX_W_0F62_P_2,
1992   VEX_W_0F63_P_2,
1993   VEX_W_0F64_P_2,
1994   VEX_W_0F65_P_2,
1995   VEX_W_0F66_P_2,
1996   VEX_W_0F67_P_2,
1997   VEX_W_0F68_P_2,
1998   VEX_W_0F69_P_2,
1999   VEX_W_0F6A_P_2,
2000   VEX_W_0F6B_P_2,
2001   VEX_W_0F6C_P_2,
2002   VEX_W_0F6D_P_2,
2003   VEX_W_0F6F_P_1,
2004   VEX_W_0F6F_P_2,
2005   VEX_W_0F70_P_1,
2006   VEX_W_0F70_P_2,
2007   VEX_W_0F70_P_3,
2008   VEX_W_0F71_R_2_P_2,
2009   VEX_W_0F71_R_4_P_2,
2010   VEX_W_0F71_R_6_P_2,
2011   VEX_W_0F72_R_2_P_2,
2012   VEX_W_0F72_R_4_P_2,
2013   VEX_W_0F72_R_6_P_2,
2014   VEX_W_0F73_R_2_P_2,
2015   VEX_W_0F73_R_3_P_2,
2016   VEX_W_0F73_R_6_P_2,
2017   VEX_W_0F73_R_7_P_2,
2018   VEX_W_0F74_P_2,
2019   VEX_W_0F75_P_2,
2020   VEX_W_0F76_P_2,
2021   VEX_W_0F77_P_0,
2022   VEX_W_0F7C_P_2,
2023   VEX_W_0F7C_P_3,
2024   VEX_W_0F7D_P_2,
2025   VEX_W_0F7D_P_3,
2026   VEX_W_0F7E_P_1,
2027   VEX_W_0F7F_P_1,
2028   VEX_W_0F7F_P_2,
2029   VEX_W_0F90_P_0_LEN_0,
2030   VEX_W_0F90_P_2_LEN_0,
2031   VEX_W_0F91_P_0_LEN_0,
2032   VEX_W_0F91_P_2_LEN_0,
2033   VEX_W_0F92_P_0_LEN_0,
2034   VEX_W_0F92_P_2_LEN_0,
2035   VEX_W_0F92_P_3_LEN_0,
2036   VEX_W_0F93_P_0_LEN_0,
2037   VEX_W_0F93_P_2_LEN_0,
2038   VEX_W_0F93_P_3_LEN_0,
2039   VEX_W_0F98_P_0_LEN_0,
2040   VEX_W_0F98_P_2_LEN_0,
2041   VEX_W_0F99_P_0_LEN_0,
2042   VEX_W_0F99_P_2_LEN_0,
2043   VEX_W_0FAE_R_2_M_0,
2044   VEX_W_0FAE_R_3_M_0,
2045   VEX_W_0FC2_P_0,
2046   VEX_W_0FC2_P_1,
2047   VEX_W_0FC2_P_2,
2048   VEX_W_0FC2_P_3,
2049   VEX_W_0FC4_P_2,
2050   VEX_W_0FC5_P_2,
2051   VEX_W_0FD0_P_2,
2052   VEX_W_0FD0_P_3,
2053   VEX_W_0FD1_P_2,
2054   VEX_W_0FD2_P_2,
2055   VEX_W_0FD3_P_2,
2056   VEX_W_0FD4_P_2,
2057   VEX_W_0FD5_P_2,
2058   VEX_W_0FD6_P_2,
2059   VEX_W_0FD7_P_2_M_1,
2060   VEX_W_0FD8_P_2,
2061   VEX_W_0FD9_P_2,
2062   VEX_W_0FDA_P_2,
2063   VEX_W_0FDB_P_2,
2064   VEX_W_0FDC_P_2,
2065   VEX_W_0FDD_P_2,
2066   VEX_W_0FDE_P_2,
2067   VEX_W_0FDF_P_2,
2068   VEX_W_0FE0_P_2,
2069   VEX_W_0FE1_P_2,
2070   VEX_W_0FE2_P_2,
2071   VEX_W_0FE3_P_2,
2072   VEX_W_0FE4_P_2,
2073   VEX_W_0FE5_P_2,
2074   VEX_W_0FE6_P_1,
2075   VEX_W_0FE6_P_2,
2076   VEX_W_0FE6_P_3,
2077   VEX_W_0FE7_P_2_M_0,
2078   VEX_W_0FE8_P_2,
2079   VEX_W_0FE9_P_2,
2080   VEX_W_0FEA_P_2,
2081   VEX_W_0FEB_P_2,
2082   VEX_W_0FEC_P_2,
2083   VEX_W_0FED_P_2,
2084   VEX_W_0FEE_P_2,
2085   VEX_W_0FEF_P_2,
2086   VEX_W_0FF0_P_3_M_0,
2087   VEX_W_0FF1_P_2,
2088   VEX_W_0FF2_P_2,
2089   VEX_W_0FF3_P_2,
2090   VEX_W_0FF4_P_2,
2091   VEX_W_0FF5_P_2,
2092   VEX_W_0FF6_P_2,
2093   VEX_W_0FF7_P_2,
2094   VEX_W_0FF8_P_2,
2095   VEX_W_0FF9_P_2,
2096   VEX_W_0FFA_P_2,
2097   VEX_W_0FFB_P_2,
2098   VEX_W_0FFC_P_2,
2099   VEX_W_0FFD_P_2,
2100   VEX_W_0FFE_P_2,
2101   VEX_W_0F3800_P_2,
2102   VEX_W_0F3801_P_2,
2103   VEX_W_0F3802_P_2,
2104   VEX_W_0F3803_P_2,
2105   VEX_W_0F3804_P_2,
2106   VEX_W_0F3805_P_2,
2107   VEX_W_0F3806_P_2,
2108   VEX_W_0F3807_P_2,
2109   VEX_W_0F3808_P_2,
2110   VEX_W_0F3809_P_2,
2111   VEX_W_0F380A_P_2,
2112   VEX_W_0F380B_P_2,
2113   VEX_W_0F380C_P_2,
2114   VEX_W_0F380D_P_2,
2115   VEX_W_0F380E_P_2,
2116   VEX_W_0F380F_P_2,
2117   VEX_W_0F3816_P_2,
2118   VEX_W_0F3817_P_2,
2119   VEX_W_0F3818_P_2,
2120   VEX_W_0F3819_P_2,
2121   VEX_W_0F381A_P_2_M_0,
2122   VEX_W_0F381C_P_2,
2123   VEX_W_0F381D_P_2,
2124   VEX_W_0F381E_P_2,
2125   VEX_W_0F3820_P_2,
2126   VEX_W_0F3821_P_2,
2127   VEX_W_0F3822_P_2,
2128   VEX_W_0F3823_P_2,
2129   VEX_W_0F3824_P_2,
2130   VEX_W_0F3825_P_2,
2131   VEX_W_0F3828_P_2,
2132   VEX_W_0F3829_P_2,
2133   VEX_W_0F382A_P_2_M_0,
2134   VEX_W_0F382B_P_2,
2135   VEX_W_0F382C_P_2_M_0,
2136   VEX_W_0F382D_P_2_M_0,
2137   VEX_W_0F382E_P_2_M_0,
2138   VEX_W_0F382F_P_2_M_0,
2139   VEX_W_0F3830_P_2,
2140   VEX_W_0F3831_P_2,
2141   VEX_W_0F3832_P_2,
2142   VEX_W_0F3833_P_2,
2143   VEX_W_0F3834_P_2,
2144   VEX_W_0F3835_P_2,
2145   VEX_W_0F3836_P_2,
2146   VEX_W_0F3837_P_2,
2147   VEX_W_0F3838_P_2,
2148   VEX_W_0F3839_P_2,
2149   VEX_W_0F383A_P_2,
2150   VEX_W_0F383B_P_2,
2151   VEX_W_0F383C_P_2,
2152   VEX_W_0F383D_P_2,
2153   VEX_W_0F383E_P_2,
2154   VEX_W_0F383F_P_2,
2155   VEX_W_0F3840_P_2,
2156   VEX_W_0F3841_P_2,
2157   VEX_W_0F3846_P_2,
2158   VEX_W_0F3858_P_2,
2159   VEX_W_0F3859_P_2,
2160   VEX_W_0F385A_P_2_M_0,
2161   VEX_W_0F3878_P_2,
2162   VEX_W_0F3879_P_2,
2163   VEX_W_0F38DB_P_2,
2164   VEX_W_0F38DC_P_2,
2165   VEX_W_0F38DD_P_2,
2166   VEX_W_0F38DE_P_2,
2167   VEX_W_0F38DF_P_2,
2168   VEX_W_0F3A00_P_2,
2169   VEX_W_0F3A01_P_2,
2170   VEX_W_0F3A02_P_2,
2171   VEX_W_0F3A04_P_2,
2172   VEX_W_0F3A05_P_2,
2173   VEX_W_0F3A06_P_2,
2174   VEX_W_0F3A08_P_2,
2175   VEX_W_0F3A09_P_2,
2176   VEX_W_0F3A0A_P_2,
2177   VEX_W_0F3A0B_P_2,
2178   VEX_W_0F3A0C_P_2,
2179   VEX_W_0F3A0D_P_2,
2180   VEX_W_0F3A0E_P_2,
2181   VEX_W_0F3A0F_P_2,
2182   VEX_W_0F3A14_P_2,
2183   VEX_W_0F3A15_P_2,
2184   VEX_W_0F3A18_P_2,
2185   VEX_W_0F3A19_P_2,
2186   VEX_W_0F3A20_P_2,
2187   VEX_W_0F3A21_P_2,
2188   VEX_W_0F3A30_P_2_LEN_0,
2189   VEX_W_0F3A31_P_2_LEN_0,
2190   VEX_W_0F3A32_P_2_LEN_0,
2191   VEX_W_0F3A33_P_2_LEN_0,
2192   VEX_W_0F3A38_P_2,
2193   VEX_W_0F3A39_P_2,
2194   VEX_W_0F3A40_P_2,
2195   VEX_W_0F3A41_P_2,
2196   VEX_W_0F3A42_P_2,
2197   VEX_W_0F3A44_P_2,
2198   VEX_W_0F3A46_P_2,
2199   VEX_W_0F3A48_P_2,
2200   VEX_W_0F3A49_P_2,
2201   VEX_W_0F3A4A_P_2,
2202   VEX_W_0F3A4B_P_2,
2203   VEX_W_0F3A4C_P_2,
2204   VEX_W_0F3A60_P_2,
2205   VEX_W_0F3A61_P_2,
2206   VEX_W_0F3A62_P_2,
2207   VEX_W_0F3A63_P_2,
2208   VEX_W_0F3ADF_P_2,
2209
2210   EVEX_W_0F10_P_0,
2211   EVEX_W_0F10_P_1_M_0,
2212   EVEX_W_0F10_P_1_M_1,
2213   EVEX_W_0F10_P_2,
2214   EVEX_W_0F10_P_3_M_0,
2215   EVEX_W_0F10_P_3_M_1,
2216   EVEX_W_0F11_P_0,
2217   EVEX_W_0F11_P_1_M_0,
2218   EVEX_W_0F11_P_1_M_1,
2219   EVEX_W_0F11_P_2,
2220   EVEX_W_0F11_P_3_M_0,
2221   EVEX_W_0F11_P_3_M_1,
2222   EVEX_W_0F12_P_0_M_0,
2223   EVEX_W_0F12_P_0_M_1,
2224   EVEX_W_0F12_P_1,
2225   EVEX_W_0F12_P_2,
2226   EVEX_W_0F12_P_3,
2227   EVEX_W_0F13_P_0,
2228   EVEX_W_0F13_P_2,
2229   EVEX_W_0F14_P_0,
2230   EVEX_W_0F14_P_2,
2231   EVEX_W_0F15_P_0,
2232   EVEX_W_0F15_P_2,
2233   EVEX_W_0F16_P_0_M_0,
2234   EVEX_W_0F16_P_0_M_1,
2235   EVEX_W_0F16_P_1,
2236   EVEX_W_0F16_P_2,
2237   EVEX_W_0F17_P_0,
2238   EVEX_W_0F17_P_2,
2239   EVEX_W_0F28_P_0,
2240   EVEX_W_0F28_P_2,
2241   EVEX_W_0F29_P_0,
2242   EVEX_W_0F29_P_2,
2243   EVEX_W_0F2A_P_1,
2244   EVEX_W_0F2A_P_3,
2245   EVEX_W_0F2B_P_0,
2246   EVEX_W_0F2B_P_2,
2247   EVEX_W_0F2E_P_0,
2248   EVEX_W_0F2E_P_2,
2249   EVEX_W_0F2F_P_0,
2250   EVEX_W_0F2F_P_2,
2251   EVEX_W_0F51_P_0,
2252   EVEX_W_0F51_P_1,
2253   EVEX_W_0F51_P_2,
2254   EVEX_W_0F51_P_3,
2255   EVEX_W_0F54_P_0,
2256   EVEX_W_0F54_P_2,
2257   EVEX_W_0F55_P_0,
2258   EVEX_W_0F55_P_2,
2259   EVEX_W_0F56_P_0,
2260   EVEX_W_0F56_P_2,
2261   EVEX_W_0F57_P_0,
2262   EVEX_W_0F57_P_2,
2263   EVEX_W_0F58_P_0,
2264   EVEX_W_0F58_P_1,
2265   EVEX_W_0F58_P_2,
2266   EVEX_W_0F58_P_3,
2267   EVEX_W_0F59_P_0,
2268   EVEX_W_0F59_P_1,
2269   EVEX_W_0F59_P_2,
2270   EVEX_W_0F59_P_3,
2271   EVEX_W_0F5A_P_0,
2272   EVEX_W_0F5A_P_1,
2273   EVEX_W_0F5A_P_2,
2274   EVEX_W_0F5A_P_3,
2275   EVEX_W_0F5B_P_0,
2276   EVEX_W_0F5B_P_1,
2277   EVEX_W_0F5B_P_2,
2278   EVEX_W_0F5C_P_0,
2279   EVEX_W_0F5C_P_1,
2280   EVEX_W_0F5C_P_2,
2281   EVEX_W_0F5C_P_3,
2282   EVEX_W_0F5D_P_0,
2283   EVEX_W_0F5D_P_1,
2284   EVEX_W_0F5D_P_2,
2285   EVEX_W_0F5D_P_3,
2286   EVEX_W_0F5E_P_0,
2287   EVEX_W_0F5E_P_1,
2288   EVEX_W_0F5E_P_2,
2289   EVEX_W_0F5E_P_3,
2290   EVEX_W_0F5F_P_0,
2291   EVEX_W_0F5F_P_1,
2292   EVEX_W_0F5F_P_2,
2293   EVEX_W_0F5F_P_3,
2294   EVEX_W_0F62_P_2,
2295   EVEX_W_0F66_P_2,
2296   EVEX_W_0F6A_P_2,
2297   EVEX_W_0F6B_P_2,
2298   EVEX_W_0F6C_P_2,
2299   EVEX_W_0F6D_P_2,
2300   EVEX_W_0F6E_P_2,
2301   EVEX_W_0F6F_P_1,
2302   EVEX_W_0F6F_P_2,
2303   EVEX_W_0F6F_P_3,
2304   EVEX_W_0F70_P_2,
2305   EVEX_W_0F72_R_2_P_2,
2306   EVEX_W_0F72_R_6_P_2,
2307   EVEX_W_0F73_R_2_P_2,
2308   EVEX_W_0F73_R_6_P_2,
2309   EVEX_W_0F76_P_2,
2310   EVEX_W_0F78_P_0,
2311   EVEX_W_0F78_P_2,
2312   EVEX_W_0F79_P_0,
2313   EVEX_W_0F79_P_2,
2314   EVEX_W_0F7A_P_1,
2315   EVEX_W_0F7A_P_2,
2316   EVEX_W_0F7A_P_3,
2317   EVEX_W_0F7B_P_1,
2318   EVEX_W_0F7B_P_2,
2319   EVEX_W_0F7B_P_3,
2320   EVEX_W_0F7E_P_1,
2321   EVEX_W_0F7E_P_2,
2322   EVEX_W_0F7F_P_1,
2323   EVEX_W_0F7F_P_2,
2324   EVEX_W_0F7F_P_3,
2325   EVEX_W_0FC2_P_0,
2326   EVEX_W_0FC2_P_1,
2327   EVEX_W_0FC2_P_2,
2328   EVEX_W_0FC2_P_3,
2329   EVEX_W_0FC6_P_0,
2330   EVEX_W_0FC6_P_2,
2331   EVEX_W_0FD2_P_2,
2332   EVEX_W_0FD3_P_2,
2333   EVEX_W_0FD4_P_2,
2334   EVEX_W_0FD6_P_2,
2335   EVEX_W_0FE6_P_1,
2336   EVEX_W_0FE6_P_2,
2337   EVEX_W_0FE6_P_3,
2338   EVEX_W_0FE7_P_2,
2339   EVEX_W_0FF2_P_2,
2340   EVEX_W_0FF3_P_2,
2341   EVEX_W_0FF4_P_2,
2342   EVEX_W_0FFA_P_2,
2343   EVEX_W_0FFB_P_2,
2344   EVEX_W_0FFE_P_2,
2345   EVEX_W_0F380C_P_2,
2346   EVEX_W_0F380D_P_2,
2347   EVEX_W_0F3810_P_1,
2348   EVEX_W_0F3810_P_2,
2349   EVEX_W_0F3811_P_1,
2350   EVEX_W_0F3811_P_2,
2351   EVEX_W_0F3812_P_1,
2352   EVEX_W_0F3812_P_2,
2353   EVEX_W_0F3813_P_1,
2354   EVEX_W_0F3813_P_2,
2355   EVEX_W_0F3814_P_1,
2356   EVEX_W_0F3815_P_1,
2357   EVEX_W_0F3818_P_2,
2358   EVEX_W_0F3819_P_2,
2359   EVEX_W_0F381A_P_2,
2360   EVEX_W_0F381B_P_2,
2361   EVEX_W_0F381E_P_2,
2362   EVEX_W_0F381F_P_2,
2363   EVEX_W_0F3820_P_1,
2364   EVEX_W_0F3821_P_1,
2365   EVEX_W_0F3822_P_1,
2366   EVEX_W_0F3823_P_1,
2367   EVEX_W_0F3824_P_1,
2368   EVEX_W_0F3825_P_1,
2369   EVEX_W_0F3825_P_2,
2370   EVEX_W_0F3826_P_1,
2371   EVEX_W_0F3826_P_2,
2372   EVEX_W_0F3828_P_1,
2373   EVEX_W_0F3828_P_2,
2374   EVEX_W_0F3829_P_1,
2375   EVEX_W_0F3829_P_2,
2376   EVEX_W_0F382A_P_1,
2377   EVEX_W_0F382A_P_2,
2378   EVEX_W_0F382B_P_2,
2379   EVEX_W_0F3830_P_1,
2380   EVEX_W_0F3831_P_1,
2381   EVEX_W_0F3832_P_1,
2382   EVEX_W_0F3833_P_1,
2383   EVEX_W_0F3834_P_1,
2384   EVEX_W_0F3835_P_1,
2385   EVEX_W_0F3835_P_2,
2386   EVEX_W_0F3837_P_2,
2387   EVEX_W_0F3838_P_1,
2388   EVEX_W_0F3839_P_1,
2389   EVEX_W_0F383A_P_1,
2390   EVEX_W_0F3840_P_2,
2391   EVEX_W_0F3858_P_2,
2392   EVEX_W_0F3859_P_2,
2393   EVEX_W_0F385A_P_2,
2394   EVEX_W_0F385B_P_2,
2395   EVEX_W_0F3866_P_2,
2396   EVEX_W_0F3875_P_2,
2397   EVEX_W_0F3878_P_2,
2398   EVEX_W_0F3879_P_2,
2399   EVEX_W_0F387A_P_2,
2400   EVEX_W_0F387B_P_2,
2401   EVEX_W_0F387D_P_2,
2402   EVEX_W_0F3883_P_2,
2403   EVEX_W_0F388D_P_2,
2404   EVEX_W_0F3891_P_2,
2405   EVEX_W_0F3893_P_2,
2406   EVEX_W_0F38A1_P_2,
2407   EVEX_W_0F38A3_P_2,
2408   EVEX_W_0F38C7_R_1_P_2,
2409   EVEX_W_0F38C7_R_2_P_2,
2410   EVEX_W_0F38C7_R_5_P_2,
2411   EVEX_W_0F38C7_R_6_P_2,
2412
2413   EVEX_W_0F3A00_P_2,
2414   EVEX_W_0F3A01_P_2,
2415   EVEX_W_0F3A04_P_2,
2416   EVEX_W_0F3A05_P_2,
2417   EVEX_W_0F3A08_P_2,
2418   EVEX_W_0F3A09_P_2,
2419   EVEX_W_0F3A0A_P_2,
2420   EVEX_W_0F3A0B_P_2,
2421   EVEX_W_0F3A16_P_2,
2422   EVEX_W_0F3A18_P_2,
2423   EVEX_W_0F3A19_P_2,
2424   EVEX_W_0F3A1A_P_2,
2425   EVEX_W_0F3A1B_P_2,
2426   EVEX_W_0F3A1D_P_2,
2427   EVEX_W_0F3A21_P_2,
2428   EVEX_W_0F3A22_P_2,
2429   EVEX_W_0F3A23_P_2,
2430   EVEX_W_0F3A38_P_2,
2431   EVEX_W_0F3A39_P_2,
2432   EVEX_W_0F3A3A_P_2,
2433   EVEX_W_0F3A3B_P_2,
2434   EVEX_W_0F3A3E_P_2,
2435   EVEX_W_0F3A3F_P_2,
2436   EVEX_W_0F3A42_P_2,
2437   EVEX_W_0F3A43_P_2,
2438   EVEX_W_0F3A50_P_2,
2439   EVEX_W_0F3A51_P_2,
2440   EVEX_W_0F3A56_P_2,
2441   EVEX_W_0F3A57_P_2,
2442   EVEX_W_0F3A66_P_2,
2443   EVEX_W_0F3A67_P_2
2444 };
2445
2446 typedef void (*op_rtn) (int bytemode, int sizeflag);
2447
2448 struct dis386 {
2449   const char *name;
2450   struct
2451     {
2452       op_rtn rtn;
2453       int bytemode;
2454     } op[MAX_OPERANDS];
2455   unsigned int prefix_requirement;
2456 };
2457
2458 /* Upper case letters in the instruction names here are macros.
2459    'A' => print 'b' if no register operands or suffix_always is true
2460    'B' => print 'b' if suffix_always is true
2461    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2462           size prefix
2463    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2464           suffix_always is true
2465    'E' => print 'e' if 32-bit form of jcxz
2466    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2467    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2468    'H' => print ",pt" or ",pn" branch hint
2469    'I' => honor following macro letter even in Intel mode (implemented only
2470           for some of the macro letters)
2471    'J' => print 'l'
2472    'K' => print 'd' or 'q' if rex prefix is present.
2473    'L' => print 'l' if suffix_always is true
2474    'M' => print 'r' if intel_mnemonic is false.
2475    'N' => print 'n' if instruction has no wait "prefix"
2476    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2477    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2478           or suffix_always is true.  print 'q' if rex prefix is present.
2479    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2480           is true
2481    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2482    'S' => print 'w', 'l' or 'q' if suffix_always is true
2483    'T' => print 'q' in 64bit mode if instruction has no operand size
2484           prefix and behave as 'P' otherwise
2485    'U' => print 'q' in 64bit mode if instruction has no operand size
2486           prefix and behave as 'Q' otherwise
2487    'V' => print 'q' in 64bit mode if instruction has no operand size
2488           prefix and behave as 'S' otherwise
2489    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2490    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2491    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2492           suffix_always is true.
2493    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2494    '!' => change condition from true to false or from false to true.
2495    '%' => add 1 upper case letter to the macro.
2496    '^' => print 'w' or 'l' depending on operand size prefix or
2497           suffix_always is true (lcall/ljmp).
2498    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2499           on operand size prefix.
2500    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2501           has no operand size prefix for AMD64 ISA, behave as 'P'
2502           otherwise
2503
2504    2 upper case letter macros:
2505    "XY" => print 'x' or 'y' if suffix_always is true or no register
2506            operands and no broadcast.
2507    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2508            register operands and no broadcast.
2509    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2510    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2511            or suffix_always is true
2512    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2513    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2514    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2515    "LW" => print 'd', 'q' depending on the VEX.W bit
2516    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2517            an operand size prefix, or suffix_always is true.  print
2518            'q' if rex prefix is present.
2519
2520    Many of the above letters print nothing in Intel mode.  See "putop"
2521    for the details.
2522
2523    Braces '{' and '}', and vertical bars '|', indicate alternative
2524    mnemonic strings for AT&T and Intel.  */
2525
2526 static const struct dis386 dis386[] = {
2527   /* 00 */
2528   { "addB",             { Ebh1, Gb }, 0 },
2529   { "addS",             { Evh1, Gv }, 0 },
2530   { "addB",             { Gb, EbS }, 0 },
2531   { "addS",             { Gv, EvS }, 0 },
2532   { "addB",             { AL, Ib }, 0 },
2533   { "addS",             { eAX, Iv }, 0 },
2534   { X86_64_TABLE (X86_64_06) },
2535   { X86_64_TABLE (X86_64_07) },
2536   /* 08 */
2537   { "orB",              { Ebh1, Gb }, 0 },
2538   { "orS",              { Evh1, Gv }, 0 },
2539   { "orB",              { Gb, EbS }, 0 },
2540   { "orS",              { Gv, EvS }, 0 },
2541   { "orB",              { AL, Ib }, 0 },
2542   { "orS",              { eAX, Iv }, 0 },
2543   { X86_64_TABLE (X86_64_0D) },
2544   { Bad_Opcode },       /* 0x0f extended opcode escape */
2545   /* 10 */
2546   { "adcB",             { Ebh1, Gb }, 0 },
2547   { "adcS",             { Evh1, Gv }, 0 },
2548   { "adcB",             { Gb, EbS }, 0 },
2549   { "adcS",             { Gv, EvS }, 0 },
2550   { "adcB",             { AL, Ib }, 0 },
2551   { "adcS",             { eAX, Iv }, 0 },
2552   { X86_64_TABLE (X86_64_16) },
2553   { X86_64_TABLE (X86_64_17) },
2554   /* 18 */
2555   { "sbbB",             { Ebh1, Gb }, 0 },
2556   { "sbbS",             { Evh1, Gv }, 0 },
2557   { "sbbB",             { Gb, EbS }, 0 },
2558   { "sbbS",             { Gv, EvS }, 0 },
2559   { "sbbB",             { AL, Ib }, 0 },
2560   { "sbbS",             { eAX, Iv }, 0 },
2561   { X86_64_TABLE (X86_64_1E) },
2562   { X86_64_TABLE (X86_64_1F) },
2563   /* 20 */
2564   { "andB",             { Ebh1, Gb }, 0 },
2565   { "andS",             { Evh1, Gv }, 0 },
2566   { "andB",             { Gb, EbS }, 0 },
2567   { "andS",             { Gv, EvS }, 0 },
2568   { "andB",             { AL, Ib }, 0 },
2569   { "andS",             { eAX, Iv }, 0 },
2570   { Bad_Opcode },       /* SEG ES prefix */
2571   { X86_64_TABLE (X86_64_27) },
2572   /* 28 */
2573   { "subB",             { Ebh1, Gb }, 0 },
2574   { "subS",             { Evh1, Gv }, 0 },
2575   { "subB",             { Gb, EbS }, 0 },
2576   { "subS",             { Gv, EvS }, 0 },
2577   { "subB",             { AL, Ib }, 0 },
2578   { "subS",             { eAX, Iv }, 0 },
2579   { Bad_Opcode },       /* SEG CS prefix */
2580   { X86_64_TABLE (X86_64_2F) },
2581   /* 30 */
2582   { "xorB",             { Ebh1, Gb }, 0 },
2583   { "xorS",             { Evh1, Gv }, 0 },
2584   { "xorB",             { Gb, EbS }, 0 },
2585   { "xorS",             { Gv, EvS }, 0 },
2586   { "xorB",             { AL, Ib }, 0 },
2587   { "xorS",             { eAX, Iv }, 0 },
2588   { Bad_Opcode },       /* SEG SS prefix */
2589   { X86_64_TABLE (X86_64_37) },
2590   /* 38 */
2591   { "cmpB",             { Eb, Gb }, 0 },
2592   { "cmpS",             { Ev, Gv }, 0 },
2593   { "cmpB",             { Gb, EbS }, 0 },
2594   { "cmpS",             { Gv, EvS }, 0 },
2595   { "cmpB",             { AL, Ib }, 0 },
2596   { "cmpS",             { eAX, Iv }, 0 },
2597   { Bad_Opcode },       /* SEG DS prefix */
2598   { X86_64_TABLE (X86_64_3F) },
2599   /* 40 */
2600   { "inc{S|}",          { RMeAX }, 0 },
2601   { "inc{S|}",          { RMeCX }, 0 },
2602   { "inc{S|}",          { RMeDX }, 0 },
2603   { "inc{S|}",          { RMeBX }, 0 },
2604   { "inc{S|}",          { RMeSP }, 0 },
2605   { "inc{S|}",          { RMeBP }, 0 },
2606   { "inc{S|}",          { RMeSI }, 0 },
2607   { "inc{S|}",          { RMeDI }, 0 },
2608   /* 48 */
2609   { "dec{S|}",          { RMeAX }, 0 },
2610   { "dec{S|}",          { RMeCX }, 0 },
2611   { "dec{S|}",          { RMeDX }, 0 },
2612   { "dec{S|}",          { RMeBX }, 0 },
2613   { "dec{S|}",          { RMeSP }, 0 },
2614   { "dec{S|}",          { RMeBP }, 0 },
2615   { "dec{S|}",          { RMeSI }, 0 },
2616   { "dec{S|}",          { RMeDI }, 0 },
2617   /* 50 */
2618   { "pushV",            { RMrAX }, 0 },
2619   { "pushV",            { RMrCX }, 0 },
2620   { "pushV",            { RMrDX }, 0 },
2621   { "pushV",            { RMrBX }, 0 },
2622   { "pushV",            { RMrSP }, 0 },
2623   { "pushV",            { RMrBP }, 0 },
2624   { "pushV",            { RMrSI }, 0 },
2625   { "pushV",            { RMrDI }, 0 },
2626   /* 58 */
2627   { "popV",             { RMrAX }, 0 },
2628   { "popV",             { RMrCX }, 0 },
2629   { "popV",             { RMrDX }, 0 },
2630   { "popV",             { RMrBX }, 0 },
2631   { "popV",             { RMrSP }, 0 },
2632   { "popV",             { RMrBP }, 0 },
2633   { "popV",             { RMrSI }, 0 },
2634   { "popV",             { RMrDI }, 0 },
2635   /* 60 */
2636   { X86_64_TABLE (X86_64_60) },
2637   { X86_64_TABLE (X86_64_61) },
2638   { X86_64_TABLE (X86_64_62) },
2639   { X86_64_TABLE (X86_64_63) },
2640   { Bad_Opcode },       /* seg fs */
2641   { Bad_Opcode },       /* seg gs */
2642   { Bad_Opcode },       /* op size prefix */
2643   { Bad_Opcode },       /* adr size prefix */
2644   /* 68 */
2645   { "pushT",            { sIv }, 0 },
2646   { "imulS",            { Gv, Ev, Iv }, 0 },
2647   { "pushT",            { sIbT }, 0 },
2648   { "imulS",            { Gv, Ev, sIb }, 0 },
2649   { "ins{b|}",          { Ybr, indirDX }, 0 },
2650   { X86_64_TABLE (X86_64_6D) },
2651   { "outs{b|}",         { indirDXr, Xb }, 0 },
2652   { X86_64_TABLE (X86_64_6F) },
2653   /* 70 */
2654   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2655   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2656   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2657   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2658   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2659   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2660   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2661   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2662   /* 78 */
2663   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2664   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2665   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2666   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2667   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2668   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2669   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2670   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2671   /* 80 */
2672   { REG_TABLE (REG_80) },
2673   { REG_TABLE (REG_81) },
2674   { REG_TABLE (REG_82) },
2675   { REG_TABLE (REG_83) },
2676   { "testB",            { Eb, Gb }, 0 },
2677   { "testS",            { Ev, Gv }, 0 },
2678   { "xchgB",            { Ebh2, Gb }, 0 },
2679   { "xchgS",            { Evh2, Gv }, 0 },
2680   /* 88 */
2681   { "movB",             { Ebh3, Gb }, 0 },
2682   { "movS",             { Evh3, Gv }, 0 },
2683   { "movB",             { Gb, EbS }, 0 },
2684   { "movS",             { Gv, EvS }, 0 },
2685   { "movD",             { Sv, Sw }, 0 },
2686   { MOD_TABLE (MOD_8D) },
2687   { "movD",             { Sw, Sv }, 0 },
2688   { REG_TABLE (REG_8F) },
2689   /* 90 */
2690   { PREFIX_TABLE (PREFIX_90) },
2691   { "xchgS",            { RMeCX, eAX }, 0 },
2692   { "xchgS",            { RMeDX, eAX }, 0 },
2693   { "xchgS",            { RMeBX, eAX }, 0 },
2694   { "xchgS",            { RMeSP, eAX }, 0 },
2695   { "xchgS",            { RMeBP, eAX }, 0 },
2696   { "xchgS",            { RMeSI, eAX }, 0 },
2697   { "xchgS",            { RMeDI, eAX }, 0 },
2698   /* 98 */
2699   { "cW{t|}R",          { XX }, 0 },
2700   { "cR{t|}O",          { XX }, 0 },
2701   { X86_64_TABLE (X86_64_9A) },
2702   { Bad_Opcode },       /* fwait */
2703   { "pushfT",           { XX }, 0 },
2704   { "popfT",            { XX }, 0 },
2705   { "sahf",             { XX }, 0 },
2706   { "lahf",             { XX }, 0 },
2707   /* a0 */
2708   { "mov%LB",           { AL, Ob }, 0 },
2709   { "mov%LS",           { eAX, Ov }, 0 },
2710   { "mov%LB",           { Ob, AL }, 0 },
2711   { "mov%LS",           { Ov, eAX }, 0 },
2712   { "movs{b|}",         { Ybr, Xb }, 0 },
2713   { "movs{R|}",         { Yvr, Xv }, 0 },
2714   { "cmps{b|}",         { Xb, Yb }, 0 },
2715   { "cmps{R|}",         { Xv, Yv }, 0 },
2716   /* a8 */
2717   { "testB",            { AL, Ib }, 0 },
2718   { "testS",            { eAX, Iv }, 0 },
2719   { "stosB",            { Ybr, AL }, 0 },
2720   { "stosS",            { Yvr, eAX }, 0 },
2721   { "lodsB",            { ALr, Xb }, 0 },
2722   { "lodsS",            { eAXr, Xv }, 0 },
2723   { "scasB",            { AL, Yb }, 0 },
2724   { "scasS",            { eAX, Yv }, 0 },
2725   /* b0 */
2726   { "movB",             { RMAL, Ib }, 0 },
2727   { "movB",             { RMCL, Ib }, 0 },
2728   { "movB",             { RMDL, Ib }, 0 },
2729   { "movB",             { RMBL, Ib }, 0 },
2730   { "movB",             { RMAH, Ib }, 0 },
2731   { "movB",             { RMCH, Ib }, 0 },
2732   { "movB",             { RMDH, Ib }, 0 },
2733   { "movB",             { RMBH, Ib }, 0 },
2734   /* b8 */
2735   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2736   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2737   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2738   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2739   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2740   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2741   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2742   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2743   /* c0 */
2744   { REG_TABLE (REG_C0) },
2745   { REG_TABLE (REG_C1) },
2746   { "retT",             { Iw, BND }, 0 },
2747   { "retT",             { BND }, 0 },
2748   { X86_64_TABLE (X86_64_C4) },
2749   { X86_64_TABLE (X86_64_C5) },
2750   { REG_TABLE (REG_C6) },
2751   { REG_TABLE (REG_C7) },
2752   /* c8 */
2753   { "enterT",           { Iw, Ib }, 0 },
2754   { "leaveT",           { XX }, 0 },
2755   { "Jret{|f}P",        { Iw }, 0 },
2756   { "Jret{|f}P",        { XX }, 0 },
2757   { "int3",             { XX }, 0 },
2758   { "int",              { Ib }, 0 },
2759   { X86_64_TABLE (X86_64_CE) },
2760   { "iret%LP",          { XX }, 0 },
2761   /* d0 */
2762   { REG_TABLE (REG_D0) },
2763   { REG_TABLE (REG_D1) },
2764   { REG_TABLE (REG_D2) },
2765   { REG_TABLE (REG_D3) },
2766   { X86_64_TABLE (X86_64_D4) },
2767   { X86_64_TABLE (X86_64_D5) },
2768   { Bad_Opcode },
2769   { "xlat",             { DSBX }, 0 },
2770   /* d8 */
2771   { FLOAT },
2772   { FLOAT },
2773   { FLOAT },
2774   { FLOAT },
2775   { FLOAT },
2776   { FLOAT },
2777   { FLOAT },
2778   { FLOAT },
2779   /* e0 */
2780   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2781   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2782   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2783   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2784   { "inB",              { AL, Ib }, 0 },
2785   { "inG",              { zAX, Ib }, 0 },
2786   { "outB",             { Ib, AL }, 0 },
2787   { "outG",             { Ib, zAX }, 0 },
2788   /* e8 */
2789   { X86_64_TABLE (X86_64_E8) },
2790   { X86_64_TABLE (X86_64_E9) },
2791   { X86_64_TABLE (X86_64_EA) },
2792   { "jmp",              { Jb, BND }, 0 },
2793   { "inB",              { AL, indirDX }, 0 },
2794   { "inG",              { zAX, indirDX }, 0 },
2795   { "outB",             { indirDX, AL }, 0 },
2796   { "outG",             { indirDX, zAX }, 0 },
2797   /* f0 */
2798   { Bad_Opcode },       /* lock prefix */
2799   { "icebp",            { XX }, 0 },
2800   { Bad_Opcode },       /* repne */
2801   { Bad_Opcode },       /* repz */
2802   { "hlt",              { XX }, 0 },
2803   { "cmc",              { XX }, 0 },
2804   { REG_TABLE (REG_F6) },
2805   { REG_TABLE (REG_F7) },
2806   /* f8 */
2807   { "clc",              { XX }, 0 },
2808   { "stc",              { XX }, 0 },
2809   { "cli",              { XX }, 0 },
2810   { "sti",              { XX }, 0 },
2811   { "cld",              { XX }, 0 },
2812   { "std",              { XX }, 0 },
2813   { REG_TABLE (REG_FE) },
2814   { REG_TABLE (REG_FF) },
2815 };
2816
2817 static const struct dis386 dis386_twobyte[] = {
2818   /* 00 */
2819   { REG_TABLE (REG_0F00 ) },
2820   { REG_TABLE (REG_0F01 ) },
2821   { "larS",             { Gv, Ew }, 0 },
2822   { "lslS",             { Gv, Ew }, 0 },
2823   { Bad_Opcode },
2824   { "syscall",          { XX }, 0 },
2825   { "clts",             { XX }, 0 },
2826   { "sysret%LP",                { XX }, 0 },
2827   /* 08 */
2828   { "invd",             { XX }, 0 },
2829   { "wbinvd",           { XX }, 0 },
2830   { Bad_Opcode },
2831   { "ud2",              { XX }, 0 },
2832   { Bad_Opcode },
2833   { REG_TABLE (REG_0F0D) },
2834   { "femms",            { XX }, 0 },
2835   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2836   /* 10 */
2837   { PREFIX_TABLE (PREFIX_0F10) },
2838   { PREFIX_TABLE (PREFIX_0F11) },
2839   { PREFIX_TABLE (PREFIX_0F12) },
2840   { MOD_TABLE (MOD_0F13) },
2841   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2842   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2843   { PREFIX_TABLE (PREFIX_0F16) },
2844   { MOD_TABLE (MOD_0F17) },
2845   /* 18 */
2846   { REG_TABLE (REG_0F18) },
2847   { "nopQ",             { Ev }, 0 },
2848   { PREFIX_TABLE (PREFIX_0F1A) },
2849   { PREFIX_TABLE (PREFIX_0F1B) },
2850   { "nopQ",             { Ev }, 0 },
2851   { "nopQ",             { Ev }, 0 },
2852   { "nopQ",             { Ev }, 0 },
2853   { "nopQ",             { Ev }, 0 },
2854   /* 20 */
2855   { "movZ",             { Rm, Cm }, 0 },
2856   { "movZ",             { Rm, Dm }, 0 },
2857   { "movZ",             { Cm, Rm }, 0 },
2858   { "movZ",             { Dm, Rm }, 0 },
2859   { MOD_TABLE (MOD_0F24) },
2860   { Bad_Opcode },
2861   { MOD_TABLE (MOD_0F26) },
2862   { Bad_Opcode },
2863   /* 28 */
2864   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2865   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2866   { PREFIX_TABLE (PREFIX_0F2A) },
2867   { PREFIX_TABLE (PREFIX_0F2B) },
2868   { PREFIX_TABLE (PREFIX_0F2C) },
2869   { PREFIX_TABLE (PREFIX_0F2D) },
2870   { PREFIX_TABLE (PREFIX_0F2E) },
2871   { PREFIX_TABLE (PREFIX_0F2F) },
2872   /* 30 */
2873   { "wrmsr",            { XX }, 0 },
2874   { "rdtsc",            { XX }, 0 },
2875   { "rdmsr",            { XX }, 0 },
2876   { "rdpmc",            { XX }, 0 },
2877   { "sysenter",         { XX }, 0 },
2878   { "sysexit",          { XX }, 0 },
2879   { Bad_Opcode },
2880   { "getsec",           { XX }, 0 },
2881   /* 38 */
2882   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2883   { Bad_Opcode },
2884   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2885   { Bad_Opcode },
2886   { Bad_Opcode },
2887   { Bad_Opcode },
2888   { Bad_Opcode },
2889   { Bad_Opcode },
2890   /* 40 */
2891   { "cmovoS",           { Gv, Ev }, 0 },
2892   { "cmovnoS",          { Gv, Ev }, 0 },
2893   { "cmovbS",           { Gv, Ev }, 0 },
2894   { "cmovaeS",          { Gv, Ev }, 0 },
2895   { "cmoveS",           { Gv, Ev }, 0 },
2896   { "cmovneS",          { Gv, Ev }, 0 },
2897   { "cmovbeS",          { Gv, Ev }, 0 },
2898   { "cmovaS",           { Gv, Ev }, 0 },
2899   /* 48 */
2900   { "cmovsS",           { Gv, Ev }, 0 },
2901   { "cmovnsS",          { Gv, Ev }, 0 },
2902   { "cmovpS",           { Gv, Ev }, 0 },
2903   { "cmovnpS",          { Gv, Ev }, 0 },
2904   { "cmovlS",           { Gv, Ev }, 0 },
2905   { "cmovgeS",          { Gv, Ev }, 0 },
2906   { "cmovleS",          { Gv, Ev }, 0 },
2907   { "cmovgS",           { Gv, Ev }, 0 },
2908   /* 50 */
2909   { MOD_TABLE (MOD_0F51) },
2910   { PREFIX_TABLE (PREFIX_0F51) },
2911   { PREFIX_TABLE (PREFIX_0F52) },
2912   { PREFIX_TABLE (PREFIX_0F53) },
2913   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2914   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2915   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2916   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2917   /* 58 */
2918   { PREFIX_TABLE (PREFIX_0F58) },
2919   { PREFIX_TABLE (PREFIX_0F59) },
2920   { PREFIX_TABLE (PREFIX_0F5A) },
2921   { PREFIX_TABLE (PREFIX_0F5B) },
2922   { PREFIX_TABLE (PREFIX_0F5C) },
2923   { PREFIX_TABLE (PREFIX_0F5D) },
2924   { PREFIX_TABLE (PREFIX_0F5E) },
2925   { PREFIX_TABLE (PREFIX_0F5F) },
2926   /* 60 */
2927   { PREFIX_TABLE (PREFIX_0F60) },
2928   { PREFIX_TABLE (PREFIX_0F61) },
2929   { PREFIX_TABLE (PREFIX_0F62) },
2930   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2931   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2932   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2933   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2934   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2935   /* 68 */
2936   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2937   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2938   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2939   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2940   { PREFIX_TABLE (PREFIX_0F6C) },
2941   { PREFIX_TABLE (PREFIX_0F6D) },
2942   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2943   { PREFIX_TABLE (PREFIX_0F6F) },
2944   /* 70 */
2945   { PREFIX_TABLE (PREFIX_0F70) },
2946   { REG_TABLE (REG_0F71) },
2947   { REG_TABLE (REG_0F72) },
2948   { REG_TABLE (REG_0F73) },
2949   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2950   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2951   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2952   { "emms",             { XX }, PREFIX_OPCODE },
2953   /* 78 */
2954   { PREFIX_TABLE (PREFIX_0F78) },
2955   { PREFIX_TABLE (PREFIX_0F79) },
2956   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2957   { Bad_Opcode },
2958   { PREFIX_TABLE (PREFIX_0F7C) },
2959   { PREFIX_TABLE (PREFIX_0F7D) },
2960   { PREFIX_TABLE (PREFIX_0F7E) },
2961   { PREFIX_TABLE (PREFIX_0F7F) },
2962   /* 80 */
2963   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2964   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2965   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2966   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2967   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2968   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2969   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2970   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2971   /* 88 */
2972   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2973   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2974   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2975   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2976   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2977   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2978   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2979   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2980   /* 90 */
2981   { "seto",             { Eb }, 0 },
2982   { "setno",            { Eb }, 0 },
2983   { "setb",             { Eb }, 0 },
2984   { "setae",            { Eb }, 0 },
2985   { "sete",             { Eb }, 0 },
2986   { "setne",            { Eb }, 0 },
2987   { "setbe",            { Eb }, 0 },
2988   { "seta",             { Eb }, 0 },
2989   /* 98 */
2990   { "sets",             { Eb }, 0 },
2991   { "setns",            { Eb }, 0 },
2992   { "setp",             { Eb }, 0 },
2993   { "setnp",            { Eb }, 0 },
2994   { "setl",             { Eb }, 0 },
2995   { "setge",            { Eb }, 0 },
2996   { "setle",            { Eb }, 0 },
2997   { "setg",             { Eb }, 0 },
2998   /* a0 */
2999   { "pushT",            { fs }, 0 },
3000   { "popT",             { fs }, 0 },
3001   { "cpuid",            { XX }, 0 },
3002   { "btS",              { Ev, Gv }, 0 },
3003   { "shldS",            { Ev, Gv, Ib }, 0 },
3004   { "shldS",            { Ev, Gv, CL }, 0 },
3005   { REG_TABLE (REG_0FA6) },
3006   { REG_TABLE (REG_0FA7) },
3007   /* a8 */
3008   { "pushT",            { gs }, 0 },
3009   { "popT",             { gs }, 0 },
3010   { "rsm",              { XX }, 0 },
3011   { "btsS",             { Evh1, Gv }, 0 },
3012   { "shrdS",            { Ev, Gv, Ib }, 0 },
3013   { "shrdS",            { Ev, Gv, CL }, 0 },
3014   { REG_TABLE (REG_0FAE) },
3015   { "imulS",            { Gv, Ev }, 0 },
3016   /* b0 */
3017   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3018   { "cmpxchgS",         { Evh1, Gv }, 0 },
3019   { MOD_TABLE (MOD_0FB2) },
3020   { "btrS",             { Evh1, Gv }, 0 },
3021   { MOD_TABLE (MOD_0FB4) },
3022   { MOD_TABLE (MOD_0FB5) },
3023   { "movz{bR|x}",       { Gv, Eb }, 0 },
3024   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3025   /* b8 */
3026   { PREFIX_TABLE (PREFIX_0FB8) },
3027   { "ud1",              { XX }, 0 },
3028   { REG_TABLE (REG_0FBA) },
3029   { "btcS",             { Evh1, Gv }, 0 },
3030   { PREFIX_TABLE (PREFIX_0FBC) },
3031   { PREFIX_TABLE (PREFIX_0FBD) },
3032   { "movs{bR|x}",       { Gv, Eb }, 0 },
3033   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3034   /* c0 */
3035   { "xaddB",            { Ebh1, Gb }, 0 },
3036   { "xaddS",            { Evh1, Gv }, 0 },
3037   { PREFIX_TABLE (PREFIX_0FC2) },
3038   { MOD_TABLE (MOD_0FC3) },
3039   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3040   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3041   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3042   { REG_TABLE (REG_0FC7) },
3043   /* c8 */
3044   { "bswap",            { RMeAX }, 0 },
3045   { "bswap",            { RMeCX }, 0 },
3046   { "bswap",            { RMeDX }, 0 },
3047   { "bswap",            { RMeBX }, 0 },
3048   { "bswap",            { RMeSP }, 0 },
3049   { "bswap",            { RMeBP }, 0 },
3050   { "bswap",            { RMeSI }, 0 },
3051   { "bswap",            { RMeDI }, 0 },
3052   /* d0 */
3053   { PREFIX_TABLE (PREFIX_0FD0) },
3054   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3055   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3056   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3057   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3058   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3059   { PREFIX_TABLE (PREFIX_0FD6) },
3060   { MOD_TABLE (MOD_0FD7) },
3061   /* d8 */
3062   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3063   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3064   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3065   { "pand",             { MX, EM }, PREFIX_OPCODE },
3066   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3067   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3068   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3069   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3070   /* e0 */
3071   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3072   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3073   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3074   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3075   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3076   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3077   { PREFIX_TABLE (PREFIX_0FE6) },
3078   { PREFIX_TABLE (PREFIX_0FE7) },
3079   /* e8 */
3080   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3081   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3082   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3083   { "por",              { MX, EM }, PREFIX_OPCODE },
3084   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3085   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3086   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3087   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3088   /* f0 */
3089   { PREFIX_TABLE (PREFIX_0FF0) },
3090   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3091   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3092   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3093   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3094   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3095   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3096   { PREFIX_TABLE (PREFIX_0FF7) },
3097   /* f8 */
3098   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3099   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3100   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3101   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3102   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3103   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3104   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3105   { Bad_Opcode },
3106 };
3107
3108 static const unsigned char onebyte_has_modrm[256] = {
3109   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3110   /*       -------------------------------        */
3111   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3112   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3113   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3114   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3115   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3116   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3117   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3118   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3119   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3120   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3121   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3122   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3123   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3124   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3125   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3126   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3127   /*       -------------------------------        */
3128   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3129 };
3130
3131 static const unsigned char twobyte_has_modrm[256] = {
3132   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3133   /*       -------------------------------        */
3134   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3135   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3136   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3137   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3138   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3139   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3140   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3141   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3142   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3143   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3144   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3145   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3146   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3147   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3148   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3149   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3150   /*       -------------------------------        */
3151   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3152 };
3153
3154 static char obuf[100];
3155 static char *obufp;
3156 static char *mnemonicendp;
3157 static char scratchbuf[100];
3158 static unsigned char *start_codep;
3159 static unsigned char *insn_codep;
3160 static unsigned char *codep;
3161 static unsigned char *end_codep;
3162 static int last_lock_prefix;
3163 static int last_repz_prefix;
3164 static int last_repnz_prefix;
3165 static int last_data_prefix;
3166 static int last_addr_prefix;
3167 static int last_rex_prefix;
3168 static int last_seg_prefix;
3169 static int fwait_prefix;
3170 /* The active segment register prefix.  */
3171 static int active_seg_prefix;
3172 #define MAX_CODE_LENGTH 15
3173 /* We can up to 14 prefixes since the maximum instruction length is
3174    15bytes.  */
3175 static int all_prefixes[MAX_CODE_LENGTH - 1];
3176 static disassemble_info *the_info;
3177 static struct
3178   {
3179     int mod;
3180     int reg;
3181     int rm;
3182   }
3183 modrm;
3184 static unsigned char need_modrm;
3185 static struct
3186   {
3187     int scale;
3188     int index;
3189     int base;
3190   }
3191 sib;
3192 static struct
3193   {
3194     int register_specifier;
3195     int length;
3196     int prefix;
3197     int w;
3198     int evex;
3199     int r;
3200     int v;
3201     int mask_register_specifier;
3202     int zeroing;
3203     int ll;
3204     int b;
3205   }
3206 vex;
3207 static unsigned char need_vex;
3208 static unsigned char need_vex_reg;
3209 static unsigned char vex_w_done;
3210
3211 struct op
3212   {
3213     const char *name;
3214     unsigned int len;
3215   };
3216
3217 /* If we are accessing mod/rm/reg without need_modrm set, then the
3218    values are stale.  Hitting this abort likely indicates that you
3219    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3220 #define MODRM_CHECK  if (!need_modrm) abort ()
3221
3222 static const char **names64;
3223 static const char **names32;
3224 static const char **names16;
3225 static const char **names8;
3226 static const char **names8rex;
3227 static const char **names_seg;
3228 static const char *index64;
3229 static const char *index32;
3230 static const char **index16;
3231 static const char **names_bnd;
3232
3233 static const char *intel_names64[] = {
3234   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3235   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3236 };
3237 static const char *intel_names32[] = {
3238   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3239   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3240 };
3241 static const char *intel_names16[] = {
3242   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3243   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3244 };
3245 static const char *intel_names8[] = {
3246   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3247 };
3248 static const char *intel_names8rex[] = {
3249   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3250   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3251 };
3252 static const char *intel_names_seg[] = {
3253   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3254 };
3255 static const char *intel_index64 = "riz";
3256 static const char *intel_index32 = "eiz";
3257 static const char *intel_index16[] = {
3258   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3259 };
3260
3261 static const char *att_names64[] = {
3262   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3263   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3264 };
3265 static const char *att_names32[] = {
3266   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3267   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3268 };
3269 static const char *att_names16[] = {
3270   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3271   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3272 };
3273 static const char *att_names8[] = {
3274   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3275 };
3276 static const char *att_names8rex[] = {
3277   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3278   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3279 };
3280 static const char *att_names_seg[] = {
3281   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3282 };
3283 static const char *att_index64 = "%riz";
3284 static const char *att_index32 = "%eiz";
3285 static const char *att_index16[] = {
3286   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3287 };
3288
3289 static const char **names_mm;
3290 static const char *intel_names_mm[] = {
3291   "mm0", "mm1", "mm2", "mm3",
3292   "mm4", "mm5", "mm6", "mm7"
3293 };
3294 static const char *att_names_mm[] = {
3295   "%mm0", "%mm1", "%mm2", "%mm3",
3296   "%mm4", "%mm5", "%mm6", "%mm7"
3297 };
3298
3299 static const char *intel_names_bnd[] = {
3300   "bnd0", "bnd1", "bnd2", "bnd3"
3301 };
3302
3303 static const char *att_names_bnd[] = {
3304   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3305 };
3306
3307 static const char **names_xmm;
3308 static const char *intel_names_xmm[] = {
3309   "xmm0", "xmm1", "xmm2", "xmm3",
3310   "xmm4", "xmm5", "xmm6", "xmm7",
3311   "xmm8", "xmm9", "xmm10", "xmm11",
3312   "xmm12", "xmm13", "xmm14", "xmm15",
3313   "xmm16", "xmm17", "xmm18", "xmm19",
3314   "xmm20", "xmm21", "xmm22", "xmm23",
3315   "xmm24", "xmm25", "xmm26", "xmm27",
3316   "xmm28", "xmm29", "xmm30", "xmm31"
3317 };
3318 static const char *att_names_xmm[] = {
3319   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3320   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3321   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3322   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3323   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3324   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3325   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3326   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3327 };
3328
3329 static const char **names_ymm;
3330 static const char *intel_names_ymm[] = {
3331   "ymm0", "ymm1", "ymm2", "ymm3",
3332   "ymm4", "ymm5", "ymm6", "ymm7",
3333   "ymm8", "ymm9", "ymm10", "ymm11",
3334   "ymm12", "ymm13", "ymm14", "ymm15",
3335   "ymm16", "ymm17", "ymm18", "ymm19",
3336   "ymm20", "ymm21", "ymm22", "ymm23",
3337   "ymm24", "ymm25", "ymm26", "ymm27",
3338   "ymm28", "ymm29", "ymm30", "ymm31"
3339 };
3340 static const char *att_names_ymm[] = {
3341   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3342   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3343   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3344   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3345   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3346   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3347   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3348   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3349 };
3350
3351 static const char **names_zmm;
3352 static const char *intel_names_zmm[] = {
3353   "zmm0", "zmm1", "zmm2", "zmm3",
3354   "zmm4", "zmm5", "zmm6", "zmm7",
3355   "zmm8", "zmm9", "zmm10", "zmm11",
3356   "zmm12", "zmm13", "zmm14", "zmm15",
3357   "zmm16", "zmm17", "zmm18", "zmm19",
3358   "zmm20", "zmm21", "zmm22", "zmm23",
3359   "zmm24", "zmm25", "zmm26", "zmm27",
3360   "zmm28", "zmm29", "zmm30", "zmm31"
3361 };
3362 static const char *att_names_zmm[] = {
3363   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3364   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3365   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3366   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3367   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3368   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3369   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3370   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3371 };
3372
3373 static const char **names_mask;
3374 static const char *intel_names_mask[] = {
3375   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3376 };
3377 static const char *att_names_mask[] = {
3378   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3379 };
3380
3381 static const char *names_rounding[] =
3382 {
3383   "{rn-sae}",
3384   "{rd-sae}",
3385   "{ru-sae}",
3386   "{rz-sae}"
3387 };
3388
3389 static const struct dis386 reg_table[][8] = {
3390   /* REG_80 */
3391   {
3392     { "addA",   { Ebh1, Ib }, 0 },
3393     { "orA",    { Ebh1, Ib }, 0 },
3394     { "adcA",   { Ebh1, Ib }, 0 },
3395     { "sbbA",   { Ebh1, Ib }, 0 },
3396     { "andA",   { Ebh1, Ib }, 0 },
3397     { "subA",   { Ebh1, Ib }, 0 },
3398     { "xorA",   { Ebh1, Ib }, 0 },
3399     { "cmpA",   { Eb, Ib }, 0 },
3400   },
3401   /* REG_81 */
3402   {
3403     { "addQ",   { Evh1, Iv }, 0 },
3404     { "orQ",    { Evh1, Iv }, 0 },
3405     { "adcQ",   { Evh1, Iv }, 0 },
3406     { "sbbQ",   { Evh1, Iv }, 0 },
3407     { "andQ",   { Evh1, Iv }, 0 },
3408     { "subQ",   { Evh1, Iv }, 0 },
3409     { "xorQ",   { Evh1, Iv }, 0 },
3410     { "cmpQ",   { Ev, Iv }, 0 },
3411   },
3412   /* REG_82 */
3413   {
3414     { X86_64_TABLE (X86_64_82_REG_0) },
3415     { X86_64_TABLE (X86_64_82_REG_1) },
3416     { X86_64_TABLE (X86_64_82_REG_2) },
3417     { X86_64_TABLE (X86_64_82_REG_3) },
3418     { X86_64_TABLE (X86_64_82_REG_4) },
3419     { X86_64_TABLE (X86_64_82_REG_5) },
3420     { X86_64_TABLE (X86_64_82_REG_6) },
3421     { X86_64_TABLE (X86_64_82_REG_7) },
3422   },
3423   /* REG_83 */
3424   {
3425     { "addQ",   { Evh1, sIb }, 0 },
3426     { "orQ",    { Evh1, sIb }, 0 },
3427     { "adcQ",   { Evh1, sIb }, 0 },
3428     { "sbbQ",   { Evh1, sIb }, 0 },
3429     { "andQ",   { Evh1, sIb }, 0 },
3430     { "subQ",   { Evh1, sIb }, 0 },
3431     { "xorQ",   { Evh1, sIb }, 0 },
3432     { "cmpQ",   { Ev, sIb }, 0 },
3433   },
3434   /* REG_8F */
3435   {
3436     { "popU",   { stackEv }, 0 },
3437     { XOP_8F_TABLE (XOP_09) },
3438     { Bad_Opcode },
3439     { Bad_Opcode },
3440     { Bad_Opcode },
3441     { XOP_8F_TABLE (XOP_09) },
3442   },
3443   /* REG_C0 */
3444   {
3445     { "rolA",   { Eb, Ib }, 0 },
3446     { "rorA",   { Eb, Ib }, 0 },
3447     { "rclA",   { Eb, Ib }, 0 },
3448     { "rcrA",   { Eb, Ib }, 0 },
3449     { "shlA",   { Eb, Ib }, 0 },
3450     { "shrA",   { Eb, Ib }, 0 },
3451     { Bad_Opcode },
3452     { "sarA",   { Eb, Ib }, 0 },
3453   },
3454   /* REG_C1 */
3455   {
3456     { "rolQ",   { Ev, Ib }, 0 },
3457     { "rorQ",   { Ev, Ib }, 0 },
3458     { "rclQ",   { Ev, Ib }, 0 },
3459     { "rcrQ",   { Ev, Ib }, 0 },
3460     { "shlQ",   { Ev, Ib }, 0 },
3461     { "shrQ",   { Ev, Ib }, 0 },
3462     { Bad_Opcode },
3463     { "sarQ",   { Ev, Ib }, 0 },
3464   },
3465   /* REG_C6 */
3466   {
3467     { "movA",   { Ebh3, Ib }, 0 },
3468     { Bad_Opcode },
3469     { Bad_Opcode },
3470     { Bad_Opcode },
3471     { Bad_Opcode },
3472     { Bad_Opcode },
3473     { Bad_Opcode },
3474     { MOD_TABLE (MOD_C6_REG_7) },
3475   },
3476   /* REG_C7 */
3477   {
3478     { "movQ",   { Evh3, Iv }, 0 },
3479     { Bad_Opcode },
3480     { Bad_Opcode },
3481     { Bad_Opcode },
3482     { Bad_Opcode },
3483     { Bad_Opcode },
3484     { Bad_Opcode },
3485     { MOD_TABLE (MOD_C7_REG_7) },
3486   },
3487   /* REG_D0 */
3488   {
3489     { "rolA",   { Eb, I1 }, 0 },
3490     { "rorA",   { Eb, I1 }, 0 },
3491     { "rclA",   { Eb, I1 }, 0 },
3492     { "rcrA",   { Eb, I1 }, 0 },
3493     { "shlA",   { Eb, I1 }, 0 },
3494     { "shrA",   { Eb, I1 }, 0 },
3495     { Bad_Opcode },
3496     { "sarA",   { Eb, I1 }, 0 },
3497   },
3498   /* REG_D1 */
3499   {
3500     { "rolQ",   { Ev, I1 }, 0 },
3501     { "rorQ",   { Ev, I1 }, 0 },
3502     { "rclQ",   { Ev, I1 }, 0 },
3503     { "rcrQ",   { Ev, I1 }, 0 },
3504     { "shlQ",   { Ev, I1 }, 0 },
3505     { "shrQ",   { Ev, I1 }, 0 },
3506     { Bad_Opcode },
3507     { "sarQ",   { Ev, I1 }, 0 },
3508   },
3509   /* REG_D2 */
3510   {
3511     { "rolA",   { Eb, CL }, 0 },
3512     { "rorA",   { Eb, CL }, 0 },
3513     { "rclA",   { Eb, CL }, 0 },
3514     { "rcrA",   { Eb, CL }, 0 },
3515     { "shlA",   { Eb, CL }, 0 },
3516     { "shrA",   { Eb, CL }, 0 },
3517     { Bad_Opcode },
3518     { "sarA",   { Eb, CL }, 0 },
3519   },
3520   /* REG_D3 */
3521   {
3522     { "rolQ",   { Ev, CL }, 0 },
3523     { "rorQ",   { Ev, CL }, 0 },
3524     { "rclQ",   { Ev, CL }, 0 },
3525     { "rcrQ",   { Ev, CL }, 0 },
3526     { "shlQ",   { Ev, CL }, 0 },
3527     { "shrQ",   { Ev, CL }, 0 },
3528     { Bad_Opcode },
3529     { "sarQ",   { Ev, CL }, 0 },
3530   },
3531   /* REG_F6 */
3532   {
3533     { "testA",  { Eb, Ib }, 0 },
3534     { Bad_Opcode },
3535     { "notA",   { Ebh1 }, 0 },
3536     { "negA",   { Ebh1 }, 0 },
3537     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3538     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3539     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3540     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3541   },
3542   /* REG_F7 */
3543   {
3544     { "testQ",  { Ev, Iv }, 0 },
3545     { Bad_Opcode },
3546     { "notQ",   { Evh1 }, 0 },
3547     { "negQ",   { Evh1 }, 0 },
3548     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3549     { "imulQ",  { Ev }, 0 },
3550     { "divQ",   { Ev }, 0 },
3551     { "idivQ",  { Ev }, 0 },
3552   },
3553   /* REG_FE */
3554   {
3555     { "incA",   { Ebh1 }, 0 },
3556     { "decA",   { Ebh1 }, 0 },
3557   },
3558   /* REG_FF */
3559   {
3560     { "incQ",   { Evh1 }, 0 },
3561     { "decQ",   { Evh1 }, 0 },
3562     { "call{&|}", { indirEv, BND }, 0 },
3563     { MOD_TABLE (MOD_FF_REG_3) },
3564     { "jmp{&|}", { indirEv, BND }, 0 },
3565     { MOD_TABLE (MOD_FF_REG_5) },
3566     { "pushU",  { stackEv }, 0 },
3567     { Bad_Opcode },
3568   },
3569   /* REG_0F00 */
3570   {
3571     { "sldtD",  { Sv }, 0 },
3572     { "strD",   { Sv }, 0 },
3573     { "lldt",   { Ew }, 0 },
3574     { "ltr",    { Ew }, 0 },
3575     { "verr",   { Ew }, 0 },
3576     { "verw",   { Ew }, 0 },
3577     { Bad_Opcode },
3578     { Bad_Opcode },
3579   },
3580   /* REG_0F01 */
3581   {
3582     { MOD_TABLE (MOD_0F01_REG_0) },
3583     { MOD_TABLE (MOD_0F01_REG_1) },
3584     { MOD_TABLE (MOD_0F01_REG_2) },
3585     { MOD_TABLE (MOD_0F01_REG_3) },
3586     { "smswD",  { Sv }, 0 },
3587     { MOD_TABLE (MOD_0F01_REG_5) },
3588     { "lmsw",   { Ew }, 0 },
3589     { MOD_TABLE (MOD_0F01_REG_7) },
3590   },
3591   /* REG_0F0D */
3592   {
3593     { "prefetch",       { Mb }, 0 },
3594     { "prefetchw",      { Mb }, 0 },
3595     { "prefetchwt1",    { Mb }, 0 },
3596     { "prefetch",       { Mb }, 0 },
3597     { "prefetch",       { Mb }, 0 },
3598     { "prefetch",       { Mb }, 0 },
3599     { "prefetch",       { Mb }, 0 },
3600     { "prefetch",       { Mb }, 0 },
3601   },
3602   /* REG_0F18 */
3603   {
3604     { MOD_TABLE (MOD_0F18_REG_0) },
3605     { MOD_TABLE (MOD_0F18_REG_1) },
3606     { MOD_TABLE (MOD_0F18_REG_2) },
3607     { MOD_TABLE (MOD_0F18_REG_3) },
3608     { MOD_TABLE (MOD_0F18_REG_4) },
3609     { MOD_TABLE (MOD_0F18_REG_5) },
3610     { MOD_TABLE (MOD_0F18_REG_6) },
3611     { MOD_TABLE (MOD_0F18_REG_7) },
3612   },
3613   /* REG_0F71 */
3614   {
3615     { Bad_Opcode },
3616     { Bad_Opcode },
3617     { MOD_TABLE (MOD_0F71_REG_2) },
3618     { Bad_Opcode },
3619     { MOD_TABLE (MOD_0F71_REG_4) },
3620     { Bad_Opcode },
3621     { MOD_TABLE (MOD_0F71_REG_6) },
3622   },
3623   /* REG_0F72 */
3624   {
3625     { Bad_Opcode },
3626     { Bad_Opcode },
3627     { MOD_TABLE (MOD_0F72_REG_2) },
3628     { Bad_Opcode },
3629     { MOD_TABLE (MOD_0F72_REG_4) },
3630     { Bad_Opcode },
3631     { MOD_TABLE (MOD_0F72_REG_6) },
3632   },
3633   /* REG_0F73 */
3634   {
3635     { Bad_Opcode },
3636     { Bad_Opcode },
3637     { MOD_TABLE (MOD_0F73_REG_2) },
3638     { MOD_TABLE (MOD_0F73_REG_3) },
3639     { Bad_Opcode },
3640     { Bad_Opcode },
3641     { MOD_TABLE (MOD_0F73_REG_6) },
3642     { MOD_TABLE (MOD_0F73_REG_7) },
3643   },
3644   /* REG_0FA6 */
3645   {
3646     { "montmul",        { { OP_0f07, 0 } }, 0 },
3647     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3648     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3649   },
3650   /* REG_0FA7 */
3651   {
3652     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3653     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3654     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3655     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3656     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3657     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3658   },
3659   /* REG_0FAE */
3660   {
3661     { MOD_TABLE (MOD_0FAE_REG_0) },
3662     { MOD_TABLE (MOD_0FAE_REG_1) },
3663     { MOD_TABLE (MOD_0FAE_REG_2) },
3664     { MOD_TABLE (MOD_0FAE_REG_3) },
3665     { MOD_TABLE (MOD_0FAE_REG_4) },
3666     { MOD_TABLE (MOD_0FAE_REG_5) },
3667     { MOD_TABLE (MOD_0FAE_REG_6) },
3668     { MOD_TABLE (MOD_0FAE_REG_7) },
3669   },
3670   /* REG_0FBA */
3671   {
3672     { Bad_Opcode },
3673     { Bad_Opcode },
3674     { Bad_Opcode },
3675     { Bad_Opcode },
3676     { "btQ",    { Ev, Ib }, 0 },
3677     { "btsQ",   { Evh1, Ib }, 0 },
3678     { "btrQ",   { Evh1, Ib }, 0 },
3679     { "btcQ",   { Evh1, Ib }, 0 },
3680   },
3681   /* REG_0FC7 */
3682   {
3683     { Bad_Opcode },
3684     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3685     { Bad_Opcode },
3686     { MOD_TABLE (MOD_0FC7_REG_3) },
3687     { MOD_TABLE (MOD_0FC7_REG_4) },
3688     { MOD_TABLE (MOD_0FC7_REG_5) },
3689     { MOD_TABLE (MOD_0FC7_REG_6) },
3690     { MOD_TABLE (MOD_0FC7_REG_7) },
3691   },
3692   /* REG_VEX_0F71 */
3693   {
3694     { Bad_Opcode },
3695     { Bad_Opcode },
3696     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3697     { Bad_Opcode },
3698     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3699     { Bad_Opcode },
3700     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3701   },
3702   /* REG_VEX_0F72 */
3703   {
3704     { Bad_Opcode },
3705     { Bad_Opcode },
3706     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3707     { Bad_Opcode },
3708     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3709     { Bad_Opcode },
3710     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3711   },
3712   /* REG_VEX_0F73 */
3713   {
3714     { Bad_Opcode },
3715     { Bad_Opcode },
3716     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3717     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3718     { Bad_Opcode },
3719     { Bad_Opcode },
3720     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3721     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3722   },
3723   /* REG_VEX_0FAE */
3724   {
3725     { Bad_Opcode },
3726     { Bad_Opcode },
3727     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3728     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3729   },
3730   /* REG_VEX_0F38F3 */
3731   {
3732     { Bad_Opcode },
3733     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3734     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3735     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3736   },
3737   /* REG_XOP_LWPCB */
3738   {
3739     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3740     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3741   },
3742   /* REG_XOP_LWP */
3743   {
3744     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3745     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3746   },
3747   /* REG_XOP_TBM_01 */
3748   {
3749     { Bad_Opcode },
3750     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3751     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3752     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3753     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3754     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3755     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3756     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3757   },
3758   /* REG_XOP_TBM_02 */
3759   {
3760     { Bad_Opcode },
3761     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3762     { Bad_Opcode },
3763     { Bad_Opcode },
3764     { Bad_Opcode },
3765     { Bad_Opcode },
3766     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3767   },
3768 #define NEED_REG_TABLE
3769 #include "i386-dis-evex.h"
3770 #undef NEED_REG_TABLE
3771 };
3772
3773 static const struct dis386 prefix_table[][4] = {
3774   /* PREFIX_90 */
3775   {
3776     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3777     { "pause", { XX }, 0 },
3778     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3779     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3780   },
3781
3782   /* PREFIX_0F10 */
3783   {
3784     { "movups", { XM, EXx }, PREFIX_OPCODE },
3785     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3786     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3787     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3788   },
3789
3790   /* PREFIX_0F11 */
3791   {
3792     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3793     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3794     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3795     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3796   },
3797
3798   /* PREFIX_0F12 */
3799   {
3800     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3801     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3802     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3803     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3804   },
3805
3806   /* PREFIX_0F16 */
3807   {
3808     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3809     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3810     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3811   },
3812
3813   /* PREFIX_0F1A */
3814   {
3815     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3816     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3817     { "bndmov", { Gbnd, Ebnd }, 0 },
3818     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3819   },
3820
3821   /* PREFIX_0F1B */
3822   {
3823     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3824     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3825     { "bndmov", { Ebnd, Gbnd }, 0 },
3826     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3827   },
3828
3829   /* PREFIX_0F2A */
3830   {
3831     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3832     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3833     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3834     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3835   },
3836
3837   /* PREFIX_0F2B */
3838   {
3839     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3840     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3841     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3842     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3843   },
3844
3845   /* PREFIX_0F2C */
3846   {
3847     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3848     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3849     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3850     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3851   },
3852
3853   /* PREFIX_0F2D */
3854   {
3855     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3856     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3857     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3858     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3859   },
3860
3861   /* PREFIX_0F2E */
3862   {
3863     { "ucomiss",{ XM, EXd }, 0 },
3864     { Bad_Opcode },
3865     { "ucomisd",{ XM, EXq }, 0 },
3866   },
3867
3868   /* PREFIX_0F2F */
3869   {
3870     { "comiss", { XM, EXd }, 0 },
3871     { Bad_Opcode },
3872     { "comisd", { XM, EXq }, 0 },
3873   },
3874
3875   /* PREFIX_0F51 */
3876   {
3877     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3878     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3879     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3880     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3881   },
3882
3883   /* PREFIX_0F52 */
3884   {
3885     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3886     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3887   },
3888
3889   /* PREFIX_0F53 */
3890   {
3891     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3892     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3893   },
3894
3895   /* PREFIX_0F58 */
3896   {
3897     { "addps", { XM, EXx }, PREFIX_OPCODE },
3898     { "addss", { XM, EXd }, PREFIX_OPCODE },
3899     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3900     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3901   },
3902
3903   /* PREFIX_0F59 */
3904   {
3905     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3906     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3907     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3908     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3909   },
3910
3911   /* PREFIX_0F5A */
3912   {
3913     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3914     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3915     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3916     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3917   },
3918
3919   /* PREFIX_0F5B */
3920   {
3921     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3922     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3923     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3924   },
3925
3926   /* PREFIX_0F5C */
3927   {
3928     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3929     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3930     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3931     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3932   },
3933
3934   /* PREFIX_0F5D */
3935   {
3936     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3937     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3938     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3939     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3940   },
3941
3942   /* PREFIX_0F5E */
3943   {
3944     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3945     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3946     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3947     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3948   },
3949
3950   /* PREFIX_0F5F */
3951   {
3952     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3953     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3954     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3955     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3956   },
3957
3958   /* PREFIX_0F60 */
3959   {
3960     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3961     { Bad_Opcode },
3962     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3963   },
3964
3965   /* PREFIX_0F61 */
3966   {
3967     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3968     { Bad_Opcode },
3969     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3970   },
3971
3972   /* PREFIX_0F62 */
3973   {
3974     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3975     { Bad_Opcode },
3976     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3977   },
3978
3979   /* PREFIX_0F6C */
3980   {
3981     { Bad_Opcode },
3982     { Bad_Opcode },
3983     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3984   },
3985
3986   /* PREFIX_0F6D */
3987   {
3988     { Bad_Opcode },
3989     { Bad_Opcode },
3990     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3991   },
3992
3993   /* PREFIX_0F6F */
3994   {
3995     { "movq",   { MX, EM }, PREFIX_OPCODE },
3996     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3997     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3998   },
3999
4000   /* PREFIX_0F70 */
4001   {
4002     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4003     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4004     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4005     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4006   },
4007
4008   /* PREFIX_0F73_REG_3 */
4009   {
4010     { Bad_Opcode },
4011     { Bad_Opcode },
4012     { "psrldq", { XS, Ib }, 0 },
4013   },
4014
4015   /* PREFIX_0F73_REG_7 */
4016   {
4017     { Bad_Opcode },
4018     { Bad_Opcode },
4019     { "pslldq", { XS, Ib }, 0 },
4020   },
4021
4022   /* PREFIX_0F78 */
4023   {
4024     {"vmread",  { Em, Gm }, 0 },
4025     { Bad_Opcode },
4026     {"extrq",   { XS, Ib, Ib }, 0 },
4027     {"insertq", { XM, XS, Ib, Ib }, 0 },
4028   },
4029
4030   /* PREFIX_0F79 */
4031   {
4032     {"vmwrite", { Gm, Em }, 0 },
4033     { Bad_Opcode },
4034     {"extrq",   { XM, XS }, 0 },
4035     {"insertq", { XM, XS }, 0 },
4036   },
4037
4038   /* PREFIX_0F7C */
4039   {
4040     { Bad_Opcode },
4041     { Bad_Opcode },
4042     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4043     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4044   },
4045
4046   /* PREFIX_0F7D */
4047   {
4048     { Bad_Opcode },
4049     { Bad_Opcode },
4050     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4051     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4052   },
4053
4054   /* PREFIX_0F7E */
4055   {
4056     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4057     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4058     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4059   },
4060
4061   /* PREFIX_0F7F */
4062   {
4063     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4064     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4065     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4066   },
4067
4068   /* PREFIX_0FAE_REG_0 */
4069   {
4070     { Bad_Opcode },
4071     { "rdfsbase", { Ev }, 0 },
4072   },
4073
4074   /* PREFIX_0FAE_REG_1 */
4075   {
4076     { Bad_Opcode },
4077     { "rdgsbase", { Ev }, 0 },
4078   },
4079
4080   /* PREFIX_0FAE_REG_2 */
4081   {
4082     { Bad_Opcode },
4083     { "wrfsbase", { Ev }, 0 },
4084   },
4085
4086   /* PREFIX_0FAE_REG_3 */
4087   {
4088     { Bad_Opcode },
4089     { "wrgsbase", { Ev }, 0 },
4090   },
4091
4092   /* PREFIX_MOD_0_0FAE_REG_4 */
4093   {
4094     { "xsave",  { FXSAVE }, 0 },
4095     { "ptwrite%LQ", { Edq }, 0 },
4096   },
4097
4098   /* PREFIX_MOD_3_0FAE_REG_4 */
4099   {
4100     { Bad_Opcode },
4101     { "ptwrite%LQ", { Edq }, 0 },
4102   },
4103
4104   /* PREFIX_0FAE_REG_6 */
4105   {
4106     { "xsaveopt",      { FXSAVE }, 0 },
4107     { Bad_Opcode },
4108     { "clwb",   { Mb }, 0 },
4109   },
4110
4111   /* PREFIX_0FAE_REG_7 */
4112   {
4113     { "clflush",        { Mb }, 0 },
4114     { Bad_Opcode },
4115     { "clflushopt",     { Mb }, 0 },
4116   },
4117
4118   /* PREFIX_0FB8 */
4119   {
4120     { Bad_Opcode },
4121     { "popcntS", { Gv, Ev }, 0 },
4122   },
4123
4124   /* PREFIX_0FBC */
4125   {
4126     { "bsfS",   { Gv, Ev }, 0 },
4127     { "tzcntS", { Gv, Ev }, 0 },
4128     { "bsfS",   { Gv, Ev }, 0 },
4129   },
4130
4131   /* PREFIX_0FBD */
4132   {
4133     { "bsrS",   { Gv, Ev }, 0 },
4134     { "lzcntS", { Gv, Ev }, 0 },
4135     { "bsrS",   { Gv, Ev }, 0 },
4136   },
4137
4138   /* PREFIX_0FC2 */
4139   {
4140     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4141     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4142     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4143     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4144   },
4145
4146   /* PREFIX_MOD_0_0FC3 */
4147   {
4148     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4149   },
4150
4151   /* PREFIX_MOD_0_0FC7_REG_6 */
4152   {
4153     { "vmptrld",{ Mq }, 0 },
4154     { "vmxon",  { Mq }, 0 },
4155     { "vmclear",{ Mq }, 0 },
4156   },
4157
4158   /* PREFIX_MOD_3_0FC7_REG_6 */
4159   {
4160     { "rdrand", { Ev }, 0 },
4161     { Bad_Opcode },
4162     { "rdrand", { Ev }, 0 }
4163   },
4164
4165   /* PREFIX_MOD_3_0FC7_REG_7 */
4166   {
4167     { "rdseed", { Ev }, 0 },
4168     { "rdpid",  { Em }, 0 },
4169     { "rdseed", { Ev }, 0 },
4170   },
4171
4172   /* PREFIX_0FD0 */
4173   {
4174     { Bad_Opcode },
4175     { Bad_Opcode },
4176     { "addsubpd", { XM, EXx }, 0 },
4177     { "addsubps", { XM, EXx }, 0 },
4178   },
4179
4180   /* PREFIX_0FD6 */
4181   {
4182     { Bad_Opcode },
4183     { "movq2dq",{ XM, MS }, 0 },
4184     { "movq",   { EXqS, XM }, 0 },
4185     { "movdq2q",{ MX, XS }, 0 },
4186   },
4187
4188   /* PREFIX_0FE6 */
4189   {
4190     { Bad_Opcode },
4191     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4192     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4193     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4194   },
4195
4196   /* PREFIX_0FE7 */
4197   {
4198     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4199     { Bad_Opcode },
4200     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4201   },
4202
4203   /* PREFIX_0FF0 */
4204   {
4205     { Bad_Opcode },
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4209   },
4210
4211   /* PREFIX_0FF7 */
4212   {
4213     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4214     { Bad_Opcode },
4215     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4216   },
4217
4218   /* PREFIX_0F3810 */
4219   {
4220     { Bad_Opcode },
4221     { Bad_Opcode },
4222     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4223   },
4224
4225   /* PREFIX_0F3814 */
4226   {
4227     { Bad_Opcode },
4228     { Bad_Opcode },
4229     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4230   },
4231
4232   /* PREFIX_0F3815 */
4233   {
4234     { Bad_Opcode },
4235     { Bad_Opcode },
4236     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4237   },
4238
4239   /* PREFIX_0F3817 */
4240   {
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4244   },
4245
4246   /* PREFIX_0F3820 */
4247   {
4248     { Bad_Opcode },
4249     { Bad_Opcode },
4250     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4251   },
4252
4253   /* PREFIX_0F3821 */
4254   {
4255     { Bad_Opcode },
4256     { Bad_Opcode },
4257     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4258   },
4259
4260   /* PREFIX_0F3822 */
4261   {
4262     { Bad_Opcode },
4263     { Bad_Opcode },
4264     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4265   },
4266
4267   /* PREFIX_0F3823 */
4268   {
4269     { Bad_Opcode },
4270     { Bad_Opcode },
4271     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4272   },
4273
4274   /* PREFIX_0F3824 */
4275   {
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4279   },
4280
4281   /* PREFIX_0F3825 */
4282   {
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4286   },
4287
4288   /* PREFIX_0F3828 */
4289   {
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4293   },
4294
4295   /* PREFIX_0F3829 */
4296   {
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4300   },
4301
4302   /* PREFIX_0F382A */
4303   {
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4307   },
4308
4309   /* PREFIX_0F382B */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4314   },
4315
4316   /* PREFIX_0F3830 */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4321   },
4322
4323   /* PREFIX_0F3831 */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4328   },
4329
4330   /* PREFIX_0F3832 */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4335   },
4336
4337   /* PREFIX_0F3833 */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4342   },
4343
4344   /* PREFIX_0F3834 */
4345   {
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4349   },
4350
4351   /* PREFIX_0F3835 */
4352   {
4353     { Bad_Opcode },
4354     { Bad_Opcode },
4355     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4356   },
4357
4358   /* PREFIX_0F3837 */
4359   {
4360     { Bad_Opcode },
4361     { Bad_Opcode },
4362     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4363   },
4364
4365   /* PREFIX_0F3838 */
4366   {
4367     { Bad_Opcode },
4368     { Bad_Opcode },
4369     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4370   },
4371
4372   /* PREFIX_0F3839 */
4373   {
4374     { Bad_Opcode },
4375     { Bad_Opcode },
4376     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4377   },
4378
4379   /* PREFIX_0F383A */
4380   {
4381     { Bad_Opcode },
4382     { Bad_Opcode },
4383     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4384   },
4385
4386   /* PREFIX_0F383B */
4387   {
4388     { Bad_Opcode },
4389     { Bad_Opcode },
4390     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4391   },
4392
4393   /* PREFIX_0F383C */
4394   {
4395     { Bad_Opcode },
4396     { Bad_Opcode },
4397     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4398   },
4399
4400   /* PREFIX_0F383D */
4401   {
4402     { Bad_Opcode },
4403     { Bad_Opcode },
4404     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4405   },
4406
4407   /* PREFIX_0F383E */
4408   {
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4412   },
4413
4414   /* PREFIX_0F383F */
4415   {
4416     { Bad_Opcode },
4417     { Bad_Opcode },
4418     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4419   },
4420
4421   /* PREFIX_0F3840 */
4422   {
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4426   },
4427
4428   /* PREFIX_0F3841 */
4429   {
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4433   },
4434
4435   /* PREFIX_0F3880 */
4436   {
4437     { Bad_Opcode },
4438     { Bad_Opcode },
4439     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4440   },
4441
4442   /* PREFIX_0F3881 */
4443   {
4444     { Bad_Opcode },
4445     { Bad_Opcode },
4446     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4447   },
4448
4449   /* PREFIX_0F3882 */
4450   {
4451     { Bad_Opcode },
4452     { Bad_Opcode },
4453     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4454   },
4455
4456   /* PREFIX_0F38C8 */
4457   {
4458     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4459   },
4460
4461   /* PREFIX_0F38C9 */
4462   {
4463     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4464   },
4465
4466   /* PREFIX_0F38CA */
4467   {
4468     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4469   },
4470
4471   /* PREFIX_0F38CB */
4472   {
4473     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4474   },
4475
4476   /* PREFIX_0F38CC */
4477   {
4478     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4479   },
4480
4481   /* PREFIX_0F38CD */
4482   {
4483     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4484   },
4485
4486   /* PREFIX_0F38DB */
4487   {
4488     { Bad_Opcode },
4489     { Bad_Opcode },
4490     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4491   },
4492
4493   /* PREFIX_0F38DC */
4494   {
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4498   },
4499
4500   /* PREFIX_0F38DD */
4501   {
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4505   },
4506
4507   /* PREFIX_0F38DE */
4508   {
4509     { Bad_Opcode },
4510     { Bad_Opcode },
4511     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4512   },
4513
4514   /* PREFIX_0F38DF */
4515   {
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4519   },
4520
4521   /* PREFIX_0F38F0 */
4522   {
4523     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4524     { Bad_Opcode },
4525     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4526     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4527   },
4528
4529   /* PREFIX_0F38F1 */
4530   {
4531     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4532     { Bad_Opcode },
4533     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4534     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4535   },
4536
4537   /* PREFIX_0F38F6 */
4538   {
4539     { Bad_Opcode },
4540     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4541     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4542     { Bad_Opcode },
4543   },
4544
4545   /* PREFIX_0F3A08 */
4546   {
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4550   },
4551
4552   /* PREFIX_0F3A09 */
4553   {
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4557   },
4558
4559   /* PREFIX_0F3A0A */
4560   {
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4564   },
4565
4566   /* PREFIX_0F3A0B */
4567   {
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F3A0C */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4578   },
4579
4580   /* PREFIX_0F3A0D */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4585   },
4586
4587   /* PREFIX_0F3A0E */
4588   {
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4592   },
4593
4594   /* PREFIX_0F3A14 */
4595   {
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4599   },
4600
4601   /* PREFIX_0F3A15 */
4602   {
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4606   },
4607
4608   /* PREFIX_0F3A16 */
4609   {
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4613   },
4614
4615   /* PREFIX_0F3A17 */
4616   {
4617     { Bad_Opcode },
4618     { Bad_Opcode },
4619     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4620   },
4621
4622   /* PREFIX_0F3A20 */
4623   {
4624     { Bad_Opcode },
4625     { Bad_Opcode },
4626     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4627   },
4628
4629   /* PREFIX_0F3A21 */
4630   {
4631     { Bad_Opcode },
4632     { Bad_Opcode },
4633     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4634   },
4635
4636   /* PREFIX_0F3A22 */
4637   {
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4641   },
4642
4643   /* PREFIX_0F3A40 */
4644   {
4645     { Bad_Opcode },
4646     { Bad_Opcode },
4647     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4648   },
4649
4650   /* PREFIX_0F3A41 */
4651   {
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4655   },
4656
4657   /* PREFIX_0F3A42 */
4658   {
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4662   },
4663
4664   /* PREFIX_0F3A44 */
4665   {
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4669   },
4670
4671   /* PREFIX_0F3A60 */
4672   {
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4676   },
4677
4678   /* PREFIX_0F3A61 */
4679   {
4680     { Bad_Opcode },
4681     { Bad_Opcode },
4682     { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4683   },
4684
4685   /* PREFIX_0F3A62 */
4686   {
4687     { Bad_Opcode },
4688     { Bad_Opcode },
4689     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4690   },
4691
4692   /* PREFIX_0F3A63 */
4693   {
4694     { Bad_Opcode },
4695     { Bad_Opcode },
4696     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4697   },
4698
4699   /* PREFIX_0F3ACC */
4700   {
4701     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4702   },
4703
4704   /* PREFIX_0F3ADF */
4705   {
4706     { Bad_Opcode },
4707     { Bad_Opcode },
4708     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4709   },
4710
4711   /* PREFIX_VEX_0F10 */
4712   {
4713     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4714     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4715     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4716     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4717   },
4718
4719   /* PREFIX_VEX_0F11 */
4720   {
4721     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4722     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4723     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4724     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4725   },
4726
4727   /* PREFIX_VEX_0F12 */
4728   {
4729     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4730     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4731     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4732     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4733   },
4734
4735   /* PREFIX_VEX_0F16 */
4736   {
4737     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4738     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4739     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4740   },
4741
4742   /* PREFIX_VEX_0F2A */
4743   {
4744     { Bad_Opcode },
4745     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4746     { Bad_Opcode },
4747     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4748   },
4749
4750   /* PREFIX_VEX_0F2C */
4751   {
4752     { Bad_Opcode },
4753     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4754     { Bad_Opcode },
4755     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4756   },
4757
4758   /* PREFIX_VEX_0F2D */
4759   {
4760     { Bad_Opcode },
4761     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4762     { Bad_Opcode },
4763     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4764   },
4765
4766   /* PREFIX_VEX_0F2E */
4767   {
4768     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4769     { Bad_Opcode },
4770     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4771   },
4772
4773   /* PREFIX_VEX_0F2F */
4774   {
4775     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4776     { Bad_Opcode },
4777     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4778   },
4779
4780   /* PREFIX_VEX_0F41 */
4781   {
4782     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4783     { Bad_Opcode },
4784     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4785   },
4786
4787   /* PREFIX_VEX_0F42 */
4788   {
4789     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4790     { Bad_Opcode },
4791     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4792   },
4793
4794   /* PREFIX_VEX_0F44 */
4795   {
4796     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4797     { Bad_Opcode },
4798     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4799   },
4800
4801   /* PREFIX_VEX_0F45 */
4802   {
4803     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4804     { Bad_Opcode },
4805     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4806   },
4807
4808   /* PREFIX_VEX_0F46 */
4809   {
4810     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4811     { Bad_Opcode },
4812     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4813   },
4814
4815   /* PREFIX_VEX_0F47 */
4816   {
4817     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4818     { Bad_Opcode },
4819     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4820   },
4821
4822   /* PREFIX_VEX_0F4A */
4823   {
4824     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4825     { Bad_Opcode },
4826     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4827   },
4828
4829   /* PREFIX_VEX_0F4B */
4830   {
4831     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4832     { Bad_Opcode },
4833     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4834   },
4835
4836   /* PREFIX_VEX_0F51 */
4837   {
4838     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4839     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4840     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4841     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4842   },
4843
4844   /* PREFIX_VEX_0F52 */
4845   {
4846     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4847     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4848   },
4849
4850   /* PREFIX_VEX_0F53 */
4851   {
4852     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4853     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4854   },
4855
4856   /* PREFIX_VEX_0F58 */
4857   {
4858     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4859     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4860     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4861     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4862   },
4863
4864   /* PREFIX_VEX_0F59 */
4865   {
4866     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4867     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4868     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4869     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4870   },
4871
4872   /* PREFIX_VEX_0F5A */
4873   {
4874     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4875     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4876     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4877     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4878   },
4879
4880   /* PREFIX_VEX_0F5B */
4881   {
4882     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4883     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4884     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4885   },
4886
4887   /* PREFIX_VEX_0F5C */
4888   {
4889     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4890     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4891     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4892     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4893   },
4894
4895   /* PREFIX_VEX_0F5D */
4896   {
4897     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4898     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4899     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4900     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4901   },
4902
4903   /* PREFIX_VEX_0F5E */
4904   {
4905     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4906     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4907     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4908     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4909   },
4910
4911   /* PREFIX_VEX_0F5F */
4912   {
4913     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4914     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4915     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4916     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4917   },
4918
4919   /* PREFIX_VEX_0F60 */
4920   {
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4924   },
4925
4926   /* PREFIX_VEX_0F61 */
4927   {
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4931   },
4932
4933   /* PREFIX_VEX_0F62 */
4934   {
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4938   },
4939
4940   /* PREFIX_VEX_0F63 */
4941   {
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4945   },
4946
4947   /* PREFIX_VEX_0F64 */
4948   {
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4952   },
4953
4954   /* PREFIX_VEX_0F65 */
4955   {
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4959   },
4960
4961   /* PREFIX_VEX_0F66 */
4962   {
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4966   },
4967
4968   /* PREFIX_VEX_0F67 */
4969   {
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4973   },
4974
4975   /* PREFIX_VEX_0F68 */
4976   {
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4980   },
4981
4982   /* PREFIX_VEX_0F69 */
4983   {
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4987   },
4988
4989   /* PREFIX_VEX_0F6A */
4990   {
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4994   },
4995
4996   /* PREFIX_VEX_0F6B */
4997   {
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5001   },
5002
5003   /* PREFIX_VEX_0F6C */
5004   {
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5008   },
5009
5010   /* PREFIX_VEX_0F6D */
5011   {
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5015   },
5016
5017   /* PREFIX_VEX_0F6E */
5018   {
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5022   },
5023
5024   /* PREFIX_VEX_0F6F */
5025   {
5026     { Bad_Opcode },
5027     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5028     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5029   },
5030
5031   /* PREFIX_VEX_0F70 */
5032   {
5033     { Bad_Opcode },
5034     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5035     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5036     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5037   },
5038
5039   /* PREFIX_VEX_0F71_REG_2 */
5040   {
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5044   },
5045
5046   /* PREFIX_VEX_0F71_REG_4 */
5047   {
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5051   },
5052
5053   /* PREFIX_VEX_0F71_REG_6 */
5054   {
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5058   },
5059
5060   /* PREFIX_VEX_0F72_REG_2 */
5061   {
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5065   },
5066
5067   /* PREFIX_VEX_0F72_REG_4 */
5068   {
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5072   },
5073
5074   /* PREFIX_VEX_0F72_REG_6 */
5075   {
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5079   },
5080
5081   /* PREFIX_VEX_0F73_REG_2 */
5082   {
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5086   },
5087
5088   /* PREFIX_VEX_0F73_REG_3 */
5089   {
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5093   },
5094
5095   /* PREFIX_VEX_0F73_REG_6 */
5096   {
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5100   },
5101
5102   /* PREFIX_VEX_0F73_REG_7 */
5103   {
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5107   },
5108
5109   /* PREFIX_VEX_0F74 */
5110   {
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5114   },
5115
5116   /* PREFIX_VEX_0F75 */
5117   {
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5121   },
5122
5123   /* PREFIX_VEX_0F76 */
5124   {
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5128   },
5129
5130   /* PREFIX_VEX_0F77 */
5131   {
5132     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5133   },
5134
5135   /* PREFIX_VEX_0F7C */
5136   {
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5140     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5141   },
5142
5143   /* PREFIX_VEX_0F7D */
5144   {
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5148     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5149   },
5150
5151   /* PREFIX_VEX_0F7E */
5152   {
5153     { Bad_Opcode },
5154     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5155     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5156   },
5157
5158   /* PREFIX_VEX_0F7F */
5159   {
5160     { Bad_Opcode },
5161     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5162     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5163   },
5164
5165   /* PREFIX_VEX_0F90 */
5166   {
5167     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5168     { Bad_Opcode },
5169     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5170   },
5171
5172   /* PREFIX_VEX_0F91 */
5173   {
5174     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5175     { Bad_Opcode },
5176     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5177   },
5178
5179   /* PREFIX_VEX_0F92 */
5180   {
5181     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5182     { Bad_Opcode },
5183     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5184     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5185   },
5186
5187   /* PREFIX_VEX_0F93 */
5188   {
5189     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5190     { Bad_Opcode },
5191     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5192     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5193   },
5194
5195   /* PREFIX_VEX_0F98 */
5196   {
5197     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5198     { Bad_Opcode },
5199     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5200   },
5201
5202   /* PREFIX_VEX_0F99 */
5203   {
5204     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5205     { Bad_Opcode },
5206     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5207   },
5208
5209   /* PREFIX_VEX_0FC2 */
5210   {
5211     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5212     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5213     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5214     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5215   },
5216
5217   /* PREFIX_VEX_0FC4 */
5218   {
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5222   },
5223
5224   /* PREFIX_VEX_0FC5 */
5225   {
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5229   },
5230
5231   /* PREFIX_VEX_0FD0 */
5232   {
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5236     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5237   },
5238
5239   /* PREFIX_VEX_0FD1 */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5244   },
5245
5246   /* PREFIX_VEX_0FD2 */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5251   },
5252
5253   /* PREFIX_VEX_0FD3 */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5258   },
5259
5260   /* PREFIX_VEX_0FD4 */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5265   },
5266
5267   /* PREFIX_VEX_0FD5 */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5272   },
5273
5274   /* PREFIX_VEX_0FD6 */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5279   },
5280
5281   /* PREFIX_VEX_0FD7 */
5282   {
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5286   },
5287
5288   /* PREFIX_VEX_0FD8 */
5289   {
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5293   },
5294
5295   /* PREFIX_VEX_0FD9 */
5296   {
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5300   },
5301
5302   /* PREFIX_VEX_0FDA */
5303   {
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5307   },
5308
5309   /* PREFIX_VEX_0FDB */
5310   {
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5314   },
5315
5316   /* PREFIX_VEX_0FDC */
5317   {
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5321   },
5322
5323   /* PREFIX_VEX_0FDD */
5324   {
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5328   },
5329
5330   /* PREFIX_VEX_0FDE */
5331   {
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5335   },
5336
5337   /* PREFIX_VEX_0FDF */
5338   {
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5342   },
5343
5344   /* PREFIX_VEX_0FE0 */
5345   {
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5349   },
5350
5351   /* PREFIX_VEX_0FE1 */
5352   {
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5356   },
5357
5358   /* PREFIX_VEX_0FE2 */
5359   {
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5363   },
5364
5365   /* PREFIX_VEX_0FE3 */
5366   {
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5370   },
5371
5372   /* PREFIX_VEX_0FE4 */
5373   {
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5377   },
5378
5379   /* PREFIX_VEX_0FE5 */
5380   {
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5384   },
5385
5386   /* PREFIX_VEX_0FE6 */
5387   {
5388     { Bad_Opcode },
5389     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5390     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5391     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5392   },
5393
5394   /* PREFIX_VEX_0FE7 */
5395   {
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5399   },
5400
5401   /* PREFIX_VEX_0FE8 */
5402   {
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5406   },
5407
5408   /* PREFIX_VEX_0FE9 */
5409   {
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5413   },
5414
5415   /* PREFIX_VEX_0FEA */
5416   {
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5420   },
5421
5422   /* PREFIX_VEX_0FEB */
5423   {
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5427   },
5428
5429   /* PREFIX_VEX_0FEC */
5430   {
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5434   },
5435
5436   /* PREFIX_VEX_0FED */
5437   {
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5441   },
5442
5443   /* PREFIX_VEX_0FEE */
5444   {
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5448   },
5449
5450   /* PREFIX_VEX_0FEF */
5451   {
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5455   },
5456
5457   /* PREFIX_VEX_0FF0 */
5458   {
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5463   },
5464
5465   /* PREFIX_VEX_0FF1 */
5466   {
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5470   },
5471
5472   /* PREFIX_VEX_0FF2 */
5473   {
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5477   },
5478
5479   /* PREFIX_VEX_0FF3 */
5480   {
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5484   },
5485
5486   /* PREFIX_VEX_0FF4 */
5487   {
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5491   },
5492
5493   /* PREFIX_VEX_0FF5 */
5494   {
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5498   },
5499
5500   /* PREFIX_VEX_0FF6 */
5501   {
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5505   },
5506
5507   /* PREFIX_VEX_0FF7 */
5508   {
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5512   },
5513
5514   /* PREFIX_VEX_0FF8 */
5515   {
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5519   },
5520
5521   /* PREFIX_VEX_0FF9 */
5522   {
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5526   },
5527
5528   /* PREFIX_VEX_0FFA */
5529   {
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5533   },
5534
5535   /* PREFIX_VEX_0FFB */
5536   {
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5540   },
5541
5542   /* PREFIX_VEX_0FFC */
5543   {
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5547   },
5548
5549   /* PREFIX_VEX_0FFD */
5550   {
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5554   },
5555
5556   /* PREFIX_VEX_0FFE */
5557   {
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5561   },
5562
5563   /* PREFIX_VEX_0F3800 */
5564   {
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5568   },
5569
5570   /* PREFIX_VEX_0F3801 */
5571   {
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5575   },
5576
5577   /* PREFIX_VEX_0F3802 */
5578   {
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5582   },
5583
5584   /* PREFIX_VEX_0F3803 */
5585   {
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5589   },
5590
5591   /* PREFIX_VEX_0F3804 */
5592   {
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5596   },
5597
5598   /* PREFIX_VEX_0F3805 */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5603   },
5604
5605   /* PREFIX_VEX_0F3806 */
5606   {
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5610   },
5611
5612   /* PREFIX_VEX_0F3807 */
5613   {
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5617   },
5618
5619   /* PREFIX_VEX_0F3808 */
5620   {
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5624   },
5625
5626   /* PREFIX_VEX_0F3809 */
5627   {
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5631   },
5632
5633   /* PREFIX_VEX_0F380A */
5634   {
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5638   },
5639
5640   /* PREFIX_VEX_0F380B */
5641   {
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5645   },
5646
5647   /* PREFIX_VEX_0F380C */
5648   {
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5652   },
5653
5654   /* PREFIX_VEX_0F380D */
5655   {
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5659   },
5660
5661   /* PREFIX_VEX_0F380E */
5662   {
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5666   },
5667
5668   /* PREFIX_VEX_0F380F */
5669   {
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5673   },
5674
5675   /* PREFIX_VEX_0F3813 */
5676   {
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5680   },
5681
5682   /* PREFIX_VEX_0F3816 */
5683   {
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5687   },
5688
5689   /* PREFIX_VEX_0F3817 */
5690   {
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5694   },
5695
5696   /* PREFIX_VEX_0F3818 */
5697   {
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5701   },
5702
5703   /* PREFIX_VEX_0F3819 */
5704   {
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5708   },
5709
5710   /* PREFIX_VEX_0F381A */
5711   {
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5715   },
5716
5717   /* PREFIX_VEX_0F381C */
5718   {
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5722   },
5723
5724   /* PREFIX_VEX_0F381D */
5725   {
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5729   },
5730
5731   /* PREFIX_VEX_0F381E */
5732   {
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5736   },
5737
5738   /* PREFIX_VEX_0F3820 */
5739   {
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5743   },
5744
5745   /* PREFIX_VEX_0F3821 */
5746   {
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5750   },
5751
5752   /* PREFIX_VEX_0F3822 */
5753   {
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5757   },
5758
5759   /* PREFIX_VEX_0F3823 */
5760   {
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5764   },
5765
5766   /* PREFIX_VEX_0F3824 */
5767   {
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5771   },
5772
5773   /* PREFIX_VEX_0F3825 */
5774   {
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5778   },
5779
5780   /* PREFIX_VEX_0F3828 */
5781   {
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5785   },
5786
5787   /* PREFIX_VEX_0F3829 */
5788   {
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5792   },
5793
5794   /* PREFIX_VEX_0F382A */
5795   {
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5799   },
5800
5801   /* PREFIX_VEX_0F382B */
5802   {
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5806   },
5807
5808   /* PREFIX_VEX_0F382C */
5809   {
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5813   },
5814
5815   /* PREFIX_VEX_0F382D */
5816   {
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5820   },
5821
5822   /* PREFIX_VEX_0F382E */
5823   {
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5827   },
5828
5829   /* PREFIX_VEX_0F382F */
5830   {
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5834   },
5835
5836   /* PREFIX_VEX_0F3830 */
5837   {
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5841   },
5842
5843   /* PREFIX_VEX_0F3831 */
5844   {
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5848   },
5849
5850   /* PREFIX_VEX_0F3832 */
5851   {
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5855   },
5856
5857   /* PREFIX_VEX_0F3833 */
5858   {
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5862   },
5863
5864   /* PREFIX_VEX_0F3834 */
5865   {
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5869   },
5870
5871   /* PREFIX_VEX_0F3835 */
5872   {
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5876   },
5877
5878   /* PREFIX_VEX_0F3836 */
5879   {
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5883   },
5884
5885   /* PREFIX_VEX_0F3837 */
5886   {
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5890   },
5891
5892   /* PREFIX_VEX_0F3838 */
5893   {
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5897   },
5898
5899   /* PREFIX_VEX_0F3839 */
5900   {
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5904   },
5905
5906   /* PREFIX_VEX_0F383A */
5907   {
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5911   },
5912
5913   /* PREFIX_VEX_0F383B */
5914   {
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5918   },
5919
5920   /* PREFIX_VEX_0F383C */
5921   {
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5925   },
5926
5927   /* PREFIX_VEX_0F383D */
5928   {
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5932   },
5933
5934   /* PREFIX_VEX_0F383E */
5935   {
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5939   },
5940
5941   /* PREFIX_VEX_0F383F */
5942   {
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5946   },
5947
5948   /* PREFIX_VEX_0F3840 */
5949   {
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5953   },
5954
5955   /* PREFIX_VEX_0F3841 */
5956   {
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5960   },
5961
5962   /* PREFIX_VEX_0F3845 */
5963   {
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5967   },
5968
5969   /* PREFIX_VEX_0F3846 */
5970   {
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5974   },
5975
5976   /* PREFIX_VEX_0F3847 */
5977   {
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5981   },
5982
5983   /* PREFIX_VEX_0F3858 */
5984   {
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5988   },
5989
5990   /* PREFIX_VEX_0F3859 */
5991   {
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5995   },
5996
5997   /* PREFIX_VEX_0F385A */
5998   {
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6002   },
6003
6004   /* PREFIX_VEX_0F3878 */
6005   {
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6009   },
6010
6011   /* PREFIX_VEX_0F3879 */
6012   {
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6016   },
6017
6018   /* PREFIX_VEX_0F388C */
6019   {
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6023   },
6024
6025   /* PREFIX_VEX_0F388E */
6026   {
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6030   },
6031
6032   /* PREFIX_VEX_0F3890 */
6033   {
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6037   },
6038
6039   /* PREFIX_VEX_0F3891 */
6040   {
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6044   },
6045
6046   /* PREFIX_VEX_0F3892 */
6047   {
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6051   },
6052
6053   /* PREFIX_VEX_0F3893 */
6054   {
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6058   },
6059
6060   /* PREFIX_VEX_0F3896 */
6061   {
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6065   },
6066
6067   /* PREFIX_VEX_0F3897 */
6068   {
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6072   },
6073
6074   /* PREFIX_VEX_0F3898 */
6075   {
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6079   },
6080
6081   /* PREFIX_VEX_0F3899 */
6082   {
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6086   },
6087
6088   /* PREFIX_VEX_0F389A */
6089   {
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6093   },
6094
6095   /* PREFIX_VEX_0F389B */
6096   {
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6100   },
6101
6102   /* PREFIX_VEX_0F389C */
6103   {
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6107   },
6108
6109   /* PREFIX_VEX_0F389D */
6110   {
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6114   },
6115
6116   /* PREFIX_VEX_0F389E */
6117   {
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6121   },
6122
6123   /* PREFIX_VEX_0F389F */
6124   {
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6128   },
6129
6130   /* PREFIX_VEX_0F38A6 */
6131   {
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6135     { Bad_Opcode },
6136   },
6137
6138   /* PREFIX_VEX_0F38A7 */
6139   {
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6143   },
6144
6145   /* PREFIX_VEX_0F38A8 */
6146   {
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6150   },
6151
6152   /* PREFIX_VEX_0F38A9 */
6153   {
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6157   },
6158
6159   /* PREFIX_VEX_0F38AA */
6160   {
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6164   },
6165
6166   /* PREFIX_VEX_0F38AB */
6167   {
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6171   },
6172
6173   /* PREFIX_VEX_0F38AC */
6174   {
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6178   },
6179
6180   /* PREFIX_VEX_0F38AD */
6181   {
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6185   },
6186
6187   /* PREFIX_VEX_0F38AE */
6188   {
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6192   },
6193
6194   /* PREFIX_VEX_0F38AF */
6195   {
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6199   },
6200
6201   /* PREFIX_VEX_0F38B6 */
6202   {
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6206   },
6207
6208   /* PREFIX_VEX_0F38B7 */
6209   {
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6213   },
6214
6215   /* PREFIX_VEX_0F38B8 */
6216   {
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6220   },
6221
6222   /* PREFIX_VEX_0F38B9 */
6223   {
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6227   },
6228
6229   /* PREFIX_VEX_0F38BA */
6230   {
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6234   },
6235
6236   /* PREFIX_VEX_0F38BB */
6237   {
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6241   },
6242
6243   /* PREFIX_VEX_0F38BC */
6244   {
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6248   },
6249
6250   /* PREFIX_VEX_0F38BD */
6251   {
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6255   },
6256
6257   /* PREFIX_VEX_0F38BE */
6258   {
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6262   },
6263
6264   /* PREFIX_VEX_0F38BF */
6265   {
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6269   },
6270
6271   /* PREFIX_VEX_0F38DB */
6272   {
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6276   },
6277
6278   /* PREFIX_VEX_0F38DC */
6279   {
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6283   },
6284
6285   /* PREFIX_VEX_0F38DD */
6286   {
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6290   },
6291
6292   /* PREFIX_VEX_0F38DE */
6293   {
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6297   },
6298
6299   /* PREFIX_VEX_0F38DF */
6300   {
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6304   },
6305
6306   /* PREFIX_VEX_0F38F2 */
6307   {
6308     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6309   },
6310
6311   /* PREFIX_VEX_0F38F3_REG_1 */
6312   {
6313     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6314   },
6315
6316   /* PREFIX_VEX_0F38F3_REG_2 */
6317   {
6318     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6319   },
6320
6321   /* PREFIX_VEX_0F38F3_REG_3 */
6322   {
6323     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6324   },
6325
6326   /* PREFIX_VEX_0F38F5 */
6327   {
6328     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6329     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6330     { Bad_Opcode },
6331     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6332   },
6333
6334   /* PREFIX_VEX_0F38F6 */
6335   {
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6340   },
6341
6342   /* PREFIX_VEX_0F38F7 */
6343   {
6344     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6345     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6346     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6347     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6348   },
6349
6350   /* PREFIX_VEX_0F3A00 */
6351   {
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6355   },
6356
6357   /* PREFIX_VEX_0F3A01 */
6358   {
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6362   },
6363
6364   /* PREFIX_VEX_0F3A02 */
6365   {
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6369   },
6370
6371   /* PREFIX_VEX_0F3A04 */
6372   {
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6376   },
6377
6378   /* PREFIX_VEX_0F3A05 */
6379   {
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6383   },
6384
6385   /* PREFIX_VEX_0F3A06 */
6386   {
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6390   },
6391
6392   /* PREFIX_VEX_0F3A08 */
6393   {
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6397   },
6398
6399   /* PREFIX_VEX_0F3A09 */
6400   {
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6404   },
6405
6406   /* PREFIX_VEX_0F3A0A */
6407   {
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6411   },
6412
6413   /* PREFIX_VEX_0F3A0B */
6414   {
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6418   },
6419
6420   /* PREFIX_VEX_0F3A0C */
6421   {
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6425   },
6426
6427   /* PREFIX_VEX_0F3A0D */
6428   {
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6432   },
6433
6434   /* PREFIX_VEX_0F3A0E */
6435   {
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6439   },
6440
6441   /* PREFIX_VEX_0F3A0F */
6442   {
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6446   },
6447
6448   /* PREFIX_VEX_0F3A14 */
6449   {
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6453   },
6454
6455   /* PREFIX_VEX_0F3A15 */
6456   {
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6460   },
6461
6462   /* PREFIX_VEX_0F3A16 */
6463   {
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6467   },
6468
6469   /* PREFIX_VEX_0F3A17 */
6470   {
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6474   },
6475
6476   /* PREFIX_VEX_0F3A18 */
6477   {
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6481   },
6482
6483   /* PREFIX_VEX_0F3A19 */
6484   {
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6488   },
6489
6490   /* PREFIX_VEX_0F3A1D */
6491   {
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6495   },
6496
6497   /* PREFIX_VEX_0F3A20 */
6498   {
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6502   },
6503
6504   /* PREFIX_VEX_0F3A21 */
6505   {
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6509   },
6510
6511   /* PREFIX_VEX_0F3A22 */
6512   {
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6516   },
6517
6518   /* PREFIX_VEX_0F3A30 */
6519   {
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6523   },
6524
6525   /* PREFIX_VEX_0F3A31 */
6526   {
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6530   },
6531
6532   /* PREFIX_VEX_0F3A32 */
6533   {
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6537   },
6538
6539   /* PREFIX_VEX_0F3A33 */
6540   {
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6544   },
6545
6546   /* PREFIX_VEX_0F3A38 */
6547   {
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6551   },
6552
6553   /* PREFIX_VEX_0F3A39 */
6554   {
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6558   },
6559
6560   /* PREFIX_VEX_0F3A40 */
6561   {
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6565   },
6566
6567   /* PREFIX_VEX_0F3A41 */
6568   {
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6572   },
6573
6574   /* PREFIX_VEX_0F3A42 */
6575   {
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6579   },
6580
6581   /* PREFIX_VEX_0F3A44 */
6582   {
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6586   },
6587
6588   /* PREFIX_VEX_0F3A46 */
6589   {
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6593   },
6594
6595   /* PREFIX_VEX_0F3A48 */
6596   {
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6600   },
6601
6602   /* PREFIX_VEX_0F3A49 */
6603   {
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6607   },
6608
6609   /* PREFIX_VEX_0F3A4A */
6610   {
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6614   },
6615
6616   /* PREFIX_VEX_0F3A4B */
6617   {
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6621   },
6622
6623   /* PREFIX_VEX_0F3A4C */
6624   {
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6628   },
6629
6630   /* PREFIX_VEX_0F3A5C */
6631   {
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6635   },
6636
6637   /* PREFIX_VEX_0F3A5D */
6638   {
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6642   },
6643
6644   /* PREFIX_VEX_0F3A5E */
6645   {
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6649   },
6650
6651   /* PREFIX_VEX_0F3A5F */
6652   {
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6656   },
6657
6658   /* PREFIX_VEX_0F3A60 */
6659   {
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6663     { Bad_Opcode },
6664   },
6665
6666   /* PREFIX_VEX_0F3A61 */
6667   {
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6671   },
6672
6673   /* PREFIX_VEX_0F3A62 */
6674   {
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6678   },
6679
6680   /* PREFIX_VEX_0F3A63 */
6681   {
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6685   },
6686
6687   /* PREFIX_VEX_0F3A68 */
6688   {
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6692   },
6693
6694   /* PREFIX_VEX_0F3A69 */
6695   {
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6699   },
6700
6701   /* PREFIX_VEX_0F3A6A */
6702   {
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6706   },
6707
6708   /* PREFIX_VEX_0F3A6B */
6709   {
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6713   },
6714
6715   /* PREFIX_VEX_0F3A6C */
6716   {
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6720   },
6721
6722   /* PREFIX_VEX_0F3A6D */
6723   {
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6727   },
6728
6729   /* PREFIX_VEX_0F3A6E */
6730   {
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6734   },
6735
6736   /* PREFIX_VEX_0F3A6F */
6737   {
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6741   },
6742
6743   /* PREFIX_VEX_0F3A78 */
6744   {
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6748   },
6749
6750   /* PREFIX_VEX_0F3A79 */
6751   {
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6755   },
6756
6757   /* PREFIX_VEX_0F3A7A */
6758   {
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6762   },
6763
6764   /* PREFIX_VEX_0F3A7B */
6765   {
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6769   },
6770
6771   /* PREFIX_VEX_0F3A7C */
6772   {
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6776     { Bad_Opcode },
6777   },
6778
6779   /* PREFIX_VEX_0F3A7D */
6780   {
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6784   },
6785
6786   /* PREFIX_VEX_0F3A7E */
6787   {
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6791   },
6792
6793   /* PREFIX_VEX_0F3A7F */
6794   {
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6798   },
6799
6800   /* PREFIX_VEX_0F3ADF */
6801   {
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6805   },
6806
6807   /* PREFIX_VEX_0F3AF0 */
6808   {
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6813   },
6814
6815 #define NEED_PREFIX_TABLE
6816 #include "i386-dis-evex.h"
6817 #undef NEED_PREFIX_TABLE
6818 };
6819
6820 static const struct dis386 x86_64_table[][2] = {
6821   /* X86_64_06 */
6822   {
6823     { "pushP", { es }, 0 },
6824   },
6825
6826   /* X86_64_07 */
6827   {
6828     { "popP", { es }, 0 },
6829   },
6830
6831   /* X86_64_0D */
6832   {
6833     { "pushP", { cs }, 0 },
6834   },
6835
6836   /* X86_64_16 */
6837   {
6838     { "pushP", { ss }, 0 },
6839   },
6840
6841   /* X86_64_17 */
6842   {
6843     { "popP", { ss }, 0 },
6844   },
6845
6846   /* X86_64_1E */
6847   {
6848     { "pushP", { ds }, 0 },
6849   },
6850
6851   /* X86_64_1F */
6852   {
6853     { "popP", { ds }, 0 },
6854   },
6855
6856   /* X86_64_27 */
6857   {
6858     { "daa", { XX }, 0 },
6859   },
6860
6861   /* X86_64_2F */
6862   {
6863     { "das", { XX }, 0 },
6864   },
6865
6866   /* X86_64_37 */
6867   {
6868     { "aaa", { XX }, 0 },
6869   },
6870
6871   /* X86_64_3F */
6872   {
6873     { "aas", { XX }, 0 },
6874   },
6875
6876   /* X86_64_60 */
6877   {
6878     { "pushaP", { XX }, 0 },
6879   },
6880
6881   /* X86_64_61 */
6882   {
6883     { "popaP", { XX }, 0 },
6884   },
6885
6886   /* X86_64_62 */
6887   {
6888     { MOD_TABLE (MOD_62_32BIT) },
6889     { EVEX_TABLE (EVEX_0F) },
6890   },
6891
6892   /* X86_64_63 */
6893   {
6894     { "arpl", { Ew, Gw }, 0 },
6895     { "movs{lq|xd}", { Gv, Ed }, 0 },
6896   },
6897
6898   /* X86_64_6D */
6899   {
6900     { "ins{R|}", { Yzr, indirDX }, 0 },
6901     { "ins{G|}", { Yzr, indirDX }, 0 },
6902   },
6903
6904   /* X86_64_6F */
6905   {
6906     { "outs{R|}", { indirDXr, Xz }, 0 },
6907     { "outs{G|}", { indirDXr, Xz }, 0 },
6908   },
6909
6910   /* X86_64_82_REG_0 */
6911   {
6912     { "addA",   { Ebh1, Ib }, 0 },
6913   },
6914
6915   /* X86_64_82_REG_1 */
6916   {
6917     { "orA",    { Ebh1, Ib }, 0 },
6918   },
6919
6920   /* X86_64_82_REG_2 */
6921   {
6922     { "adcA",   { Ebh1, Ib }, 0 },
6923   },
6924
6925   /* X86_64_82_REG_3 */
6926   {
6927     { "sbbA",   { Ebh1, Ib }, 0 },
6928   },
6929
6930   /* X86_64_82_REG_4 */
6931   {
6932     { "andA",   { Ebh1, Ib }, 0 },
6933   },
6934
6935   /* X86_64_82_REG_5 */
6936   {
6937     { "subA",   { Ebh1, Ib }, 0 },
6938   },
6939
6940   /* X86_64_82_REG_6 */
6941   {
6942     { "xorA",   { Ebh1, Ib }, 0 },
6943   },
6944
6945   /* X86_64_82_REG_7 */
6946   {
6947     { "cmpA",   { Eb, Ib }, 0 },
6948   },
6949
6950   /* X86_64_9A */
6951   {
6952     { "Jcall{T|}", { Ap }, 0 },
6953   },
6954
6955   /* X86_64_C4 */
6956   {
6957     { MOD_TABLE (MOD_C4_32BIT) },
6958     { VEX_C4_TABLE (VEX_0F) },
6959   },
6960
6961   /* X86_64_C5 */
6962   {
6963     { MOD_TABLE (MOD_C5_32BIT) },
6964     { VEX_C5_TABLE (VEX_0F) },
6965   },
6966
6967   /* X86_64_CE */
6968   {
6969     { "into", { XX }, 0 },
6970   },
6971
6972   /* X86_64_D4 */
6973   {
6974     { "aam", { Ib }, 0 },
6975   },
6976
6977   /* X86_64_D5 */
6978   {
6979     { "aad", { Ib }, 0 },
6980   },
6981
6982   /* X86_64_E8 */
6983   {
6984     { "callP",          { Jv, BND }, 0 },
6985     { "call@",          { Jv, BND }, 0 }
6986   },
6987
6988   /* X86_64_E9 */
6989   {
6990     { "jmpP",           { Jv, BND }, 0 },
6991     { "jmp@",           { Jv, BND }, 0 }
6992   },
6993
6994   /* X86_64_EA */
6995   {
6996     { "Jjmp{T|}", { Ap }, 0 },
6997   },
6998
6999   /* X86_64_0F01_REG_0 */
7000   {
7001     { "sgdt{Q|IQ}", { M }, 0 },
7002     { "sgdt", { M }, 0 },
7003   },
7004
7005   /* X86_64_0F01_REG_1 */
7006   {
7007     { "sidt{Q|IQ}", { M }, 0 },
7008     { "sidt", { M }, 0 },
7009   },
7010
7011   /* X86_64_0F01_REG_2 */
7012   {
7013     { "lgdt{Q|Q}", { M }, 0 },
7014     { "lgdt", { M }, 0 },
7015   },
7016
7017   /* X86_64_0F01_REG_3 */
7018   {
7019     { "lidt{Q|Q}", { M }, 0 },
7020     { "lidt", { M }, 0 },
7021   },
7022 };
7023
7024 static const struct dis386 three_byte_table[][256] = {
7025
7026   /* THREE_BYTE_0F38 */
7027   {
7028     /* 00 */
7029     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7030     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7031     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7032     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7033     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7034     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7035     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7036     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7037     /* 08 */
7038     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7039     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7040     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7041     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     /* 10 */
7047     { PREFIX_TABLE (PREFIX_0F3810) },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { PREFIX_TABLE (PREFIX_0F3814) },
7052     { PREFIX_TABLE (PREFIX_0F3815) },
7053     { Bad_Opcode },
7054     { PREFIX_TABLE (PREFIX_0F3817) },
7055     /* 18 */
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7061     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7062     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7063     { Bad_Opcode },
7064     /* 20 */
7065     { PREFIX_TABLE (PREFIX_0F3820) },
7066     { PREFIX_TABLE (PREFIX_0F3821) },
7067     { PREFIX_TABLE (PREFIX_0F3822) },
7068     { PREFIX_TABLE (PREFIX_0F3823) },
7069     { PREFIX_TABLE (PREFIX_0F3824) },
7070     { PREFIX_TABLE (PREFIX_0F3825) },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     /* 28 */
7074     { PREFIX_TABLE (PREFIX_0F3828) },
7075     { PREFIX_TABLE (PREFIX_0F3829) },
7076     { PREFIX_TABLE (PREFIX_0F382A) },
7077     { PREFIX_TABLE (PREFIX_0F382B) },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     /* 30 */
7083     { PREFIX_TABLE (PREFIX_0F3830) },
7084     { PREFIX_TABLE (PREFIX_0F3831) },
7085     { PREFIX_TABLE (PREFIX_0F3832) },
7086     { PREFIX_TABLE (PREFIX_0F3833) },
7087     { PREFIX_TABLE (PREFIX_0F3834) },
7088     { PREFIX_TABLE (PREFIX_0F3835) },
7089     { Bad_Opcode },
7090     { PREFIX_TABLE (PREFIX_0F3837) },
7091     /* 38 */
7092     { PREFIX_TABLE (PREFIX_0F3838) },
7093     { PREFIX_TABLE (PREFIX_0F3839) },
7094     { PREFIX_TABLE (PREFIX_0F383A) },
7095     { PREFIX_TABLE (PREFIX_0F383B) },
7096     { PREFIX_TABLE (PREFIX_0F383C) },
7097     { PREFIX_TABLE (PREFIX_0F383D) },
7098     { PREFIX_TABLE (PREFIX_0F383E) },
7099     { PREFIX_TABLE (PREFIX_0F383F) },
7100     /* 40 */
7101     { PREFIX_TABLE (PREFIX_0F3840) },
7102     { PREFIX_TABLE (PREFIX_0F3841) },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     /* 48 */
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     /* 50 */
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     /* 58 */
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     /* 60 */
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     /* 68 */
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     /* 70 */
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     /* 78 */
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     /* 80 */
7173     { PREFIX_TABLE (PREFIX_0F3880) },
7174     { PREFIX_TABLE (PREFIX_0F3881) },
7175     { PREFIX_TABLE (PREFIX_0F3882) },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     /* 88 */
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     /* 90 */
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     /* 98 */
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     /* a0 */
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     /* a8 */
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     /* b0 */
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     /* b8 */
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     /* c0 */
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     /* c8 */
7254     { PREFIX_TABLE (PREFIX_0F38C8) },
7255     { PREFIX_TABLE (PREFIX_0F38C9) },
7256     { PREFIX_TABLE (PREFIX_0F38CA) },
7257     { PREFIX_TABLE (PREFIX_0F38CB) },
7258     { PREFIX_TABLE (PREFIX_0F38CC) },
7259     { PREFIX_TABLE (PREFIX_0F38CD) },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     /* d0 */
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     /* d8 */
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { PREFIX_TABLE (PREFIX_0F38DB) },
7276     { PREFIX_TABLE (PREFIX_0F38DC) },
7277     { PREFIX_TABLE (PREFIX_0F38DD) },
7278     { PREFIX_TABLE (PREFIX_0F38DE) },
7279     { PREFIX_TABLE (PREFIX_0F38DF) },
7280     /* e0 */
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     /* e8 */
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     /* f0 */
7299     { PREFIX_TABLE (PREFIX_0F38F0) },
7300     { PREFIX_TABLE (PREFIX_0F38F1) },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { PREFIX_TABLE (PREFIX_0F38F6) },
7306     { Bad_Opcode },
7307     /* f8 */
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316   },
7317   /* THREE_BYTE_0F3A */
7318   {
7319     /* 00 */
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     /* 08 */
7329     { PREFIX_TABLE (PREFIX_0F3A08) },
7330     { PREFIX_TABLE (PREFIX_0F3A09) },
7331     { PREFIX_TABLE (PREFIX_0F3A0A) },
7332     { PREFIX_TABLE (PREFIX_0F3A0B) },
7333     { PREFIX_TABLE (PREFIX_0F3A0C) },
7334     { PREFIX_TABLE (PREFIX_0F3A0D) },
7335     { PREFIX_TABLE (PREFIX_0F3A0E) },
7336     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7337     /* 10 */
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { PREFIX_TABLE (PREFIX_0F3A14) },
7343     { PREFIX_TABLE (PREFIX_0F3A15) },
7344     { PREFIX_TABLE (PREFIX_0F3A16) },
7345     { PREFIX_TABLE (PREFIX_0F3A17) },
7346     /* 18 */
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     /* 20 */
7356     { PREFIX_TABLE (PREFIX_0F3A20) },
7357     { PREFIX_TABLE (PREFIX_0F3A21) },
7358     { PREFIX_TABLE (PREFIX_0F3A22) },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     /* 28 */
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     /* 30 */
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     /* 38 */
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     /* 40 */
7392     { PREFIX_TABLE (PREFIX_0F3A40) },
7393     { PREFIX_TABLE (PREFIX_0F3A41) },
7394     { PREFIX_TABLE (PREFIX_0F3A42) },
7395     { Bad_Opcode },
7396     { PREFIX_TABLE (PREFIX_0F3A44) },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     /* 48 */
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     /* 50 */
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     /* 58 */
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     /* 60 */
7428     { PREFIX_TABLE (PREFIX_0F3A60) },
7429     { PREFIX_TABLE (PREFIX_0F3A61) },
7430     { PREFIX_TABLE (PREFIX_0F3A62) },
7431     { PREFIX_TABLE (PREFIX_0F3A63) },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     /* 68 */
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     /* 70 */
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     /* 78 */
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     /* 80 */
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     /* 88 */
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     /* 90 */
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     /* 98 */
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     /* a0 */
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     /* a8 */
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     /* b0 */
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     /* b8 */
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     /* c0 */
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     /* c8 */
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { PREFIX_TABLE (PREFIX_0F3ACC) },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     /* d0 */
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     /* d8 */
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { PREFIX_TABLE (PREFIX_0F3ADF) },
7571     /* e0 */
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     /* e8 */
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     /* f0 */
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     /* f8 */
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607   },
7608
7609   /* THREE_BYTE_0F7A */
7610   {
7611     /* 00 */
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     /* 08 */
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     /* 10 */
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     /* 18 */
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     /* 20 */
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     /* 28 */
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     /* 30 */
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     /* 38 */
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     /* 40 */
7684     { Bad_Opcode },
7685     { "phaddbw",        { XM, EXq }, PREFIX_OPCODE },
7686     { "phaddbd",        { XM, EXq }, PREFIX_OPCODE },
7687     { "phaddbq",        { XM, EXq }, PREFIX_OPCODE },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { "phaddwd",        { XM, EXq }, PREFIX_OPCODE },
7691     { "phaddwq",        { XM, EXq }, PREFIX_OPCODE },
7692     /* 48 */
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { "phadddq",        { XM, EXq }, PREFIX_OPCODE },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     /* 50 */
7702     { Bad_Opcode },
7703     { "phaddubw",       { XM, EXq }, PREFIX_OPCODE },
7704     { "phaddubd",       { XM, EXq }, PREFIX_OPCODE },
7705     { "phaddubq",       { XM, EXq }, PREFIX_OPCODE },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { "phadduwd",       { XM, EXq }, PREFIX_OPCODE },
7709     { "phadduwq",       { XM, EXq }, PREFIX_OPCODE },
7710     /* 58 */
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { "phaddudq",       { XM, EXq }, PREFIX_OPCODE },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     /* 60 */
7720     { Bad_Opcode },
7721     { "phsubbw",        { XM, EXq }, PREFIX_OPCODE },
7722     { "phsubbd",        { XM, EXq }, PREFIX_OPCODE },
7723     { "phsubbq",        { XM, EXq }, PREFIX_OPCODE },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     /* 68 */
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     /* 70 */
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     /* 78 */
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     /* 80 */
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     /* 88 */
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     /* 90 */
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     /* 98 */
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     /* a0 */
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     /* a8 */
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     /* b0 */
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     /* b8 */
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     /* c0 */
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     /* c8 */
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     /* d0 */
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     /* d8 */
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     /* e0 */
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     /* e8 */
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     /* f0 */
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     /* f8 */
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899   },
7900 };
7901
7902 static const struct dis386 xop_table[][256] = {
7903   /* XOP_08 */
7904   {
7905     /* 00 */
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     /* 08 */
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     /* 10 */
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     /* 18 */
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     /* 20 */
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     /* 28 */
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     /* 30 */
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     /* 38 */
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     /* 40 */
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     /* 48 */
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     /* 50 */
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     /* 58 */
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     /* 60 */
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     /* 68 */
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     /* 70 */
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     /* 78 */
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     /* 80 */
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8056     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8057     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8058     /* 88 */
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8066     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8067     /* 90 */
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8074     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8075     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8076     /* 98 */
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8084     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8085     /* a0 */
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8089     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8093     { Bad_Opcode },
8094     /* a8 */
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     /* b0 */
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8111     { Bad_Opcode },
8112     /* b8 */
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     /* c0 */
8122     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
8123     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
8124     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
8125     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     /* c8 */
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
8136     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
8137     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
8138     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
8139     /* d0 */
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     /* d8 */
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     /* e0 */
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     /* e8 */
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8172     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8173     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8174     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8175     /* f0 */
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     /* f8 */
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193   },
8194   /* XOP_09 */
8195   {
8196     /* 00 */
8197     { Bad_Opcode },
8198     { REG_TABLE (REG_XOP_TBM_01) },
8199     { REG_TABLE (REG_XOP_TBM_02) },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     /* 08 */
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     /* 10 */
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { REG_TABLE (REG_XOP_LWPCB) },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     /* 18 */
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     /* 20 */
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     /* 28 */
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     /* 30 */
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     /* 38 */
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     /* 40 */
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     /* 48 */
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     /* 50 */
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     /* 58 */
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     /* 60 */
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     /* 68 */
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     /* 70 */
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     /* 78 */
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     /* 80 */
8341     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8342     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8343     { "vfrczss",        { XM, EXd }, 0 },
8344     { "vfrczsd",        { XM, EXq }, 0 },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     /* 88 */
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     /* 90 */
8359     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8360     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8361     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8362     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8363     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8364     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8365     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8366     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8367     /* 98 */
8368     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8369     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8370     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8371     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     /* a0 */
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     /* a8 */
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     /* b0 */
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     /* b8 */
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     /* c0 */
8413     { Bad_Opcode },
8414     { "vphaddbw",       { XM, EXxmm }, 0 },
8415     { "vphaddbd",       { XM, EXxmm }, 0 },
8416     { "vphaddbq",       { XM, EXxmm }, 0 },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { "vphaddwd",       { XM, EXxmm }, 0 },
8420     { "vphaddwq",       { XM, EXxmm }, 0 },
8421     /* c8 */
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { "vphadddq",       { XM, EXxmm }, 0 },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     /* d0 */
8431     { Bad_Opcode },
8432     { "vphaddubw",      { XM, EXxmm }, 0 },
8433     { "vphaddubd",      { XM, EXxmm }, 0 },
8434     { "vphaddubq",      { XM, EXxmm }, 0 },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { "vphadduwd",      { XM, EXxmm }, 0 },
8438     { "vphadduwq",      { XM, EXxmm }, 0 },
8439     /* d8 */
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { "vphaddudq",      { XM, EXxmm }, 0 },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     /* e0 */
8449     { Bad_Opcode },
8450     { "vphsubbw",       { XM, EXxmm }, 0 },
8451     { "vphsubwd",       { XM, EXxmm }, 0 },
8452     { "vphsubdq",       { XM, EXxmm }, 0 },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     /* e8 */
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     /* f0 */
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     /* f8 */
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484   },
8485   /* XOP_0A */
8486   {
8487     /* 00 */
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     /* 08 */
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     /* 10 */
8506     { "bextr",  { Gv, Ev, Iq }, 0 },
8507     { Bad_Opcode },
8508     { REG_TABLE (REG_XOP_LWP) },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     /* 18 */
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     /* 20 */
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     /* 28 */
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     /* 30 */
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     /* 38 */
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     /* 40 */
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     /* 48 */
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     /* 50 */
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     /* 58 */
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     /* 60 */
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     /* 68 */
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     /* 70 */
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     /* 78 */
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     /* 80 */
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     /* 88 */
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     /* 90 */
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     /* 98 */
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     /* a0 */
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     /* a8 */
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     /* b0 */
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     /* b8 */
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     /* c0 */
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     /* c8 */
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     /* d0 */
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     /* d8 */
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     /* e0 */
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     /* e8 */
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     /* f0 */
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     /* f8 */
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775   },
8776 };
8777
8778 static const struct dis386 vex_table[][256] = {
8779   /* VEX_0F */
8780   {
8781     /* 00 */
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     /* 08 */
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     /* 10 */
8800     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8803     { MOD_TABLE (MOD_VEX_0F13) },
8804     { VEX_W_TABLE (VEX_W_0F14) },
8805     { VEX_W_TABLE (VEX_W_0F15) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8807     { MOD_TABLE (MOD_VEX_0F17) },
8808     /* 18 */
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     /* 20 */
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     /* 28 */
8827     { VEX_W_TABLE (VEX_W_0F28) },
8828     { VEX_W_TABLE (VEX_W_0F29) },
8829     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8830     { MOD_TABLE (MOD_VEX_0F2B) },
8831     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8832     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8833     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8834     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8835     /* 30 */
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     /* 38 */
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     /* 40 */
8854     { Bad_Opcode },
8855     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8856     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8857     { Bad_Opcode },
8858     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8859     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8860     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8861     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8862     /* 48 */
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8866     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     /* 50 */
8872     { MOD_TABLE (MOD_VEX_0F50) },
8873     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8874     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8875     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8876     { "vandpX",         { XM, Vex, EXx }, 0 },
8877     { "vandnpX",        { XM, Vex, EXx }, 0 },
8878     { "vorpX",          { XM, Vex, EXx }, 0 },
8879     { "vxorpX",         { XM, Vex, EXx }, 0 },
8880     /* 58 */
8881     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8882     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8883     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8889     /* 60 */
8890     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8898     /* 68 */
8899     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8907     /* 70 */
8908     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8909     { REG_TABLE (REG_VEX_0F71) },
8910     { REG_TABLE (REG_VEX_0F72) },
8911     { REG_TABLE (REG_VEX_0F73) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8916     /* 78 */
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8925     /* 80 */
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     /* 88 */
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     /* 90 */
8944     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     /* 98 */
8953     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     /* a0 */
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     /* a8 */
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { REG_TABLE (REG_VEX_0FAE) },
8978     { Bad_Opcode },
8979     /* b0 */
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     /* b8 */
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     /* c0 */
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
9001     { Bad_Opcode },
9002     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
9003     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
9004     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
9005     { Bad_Opcode },
9006     /* c8 */
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     /* d0 */
9016     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
9017     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
9018     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
9019     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
9020     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
9021     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
9022     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
9023     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
9024     /* d8 */
9025     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
9026     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
9027     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
9028     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
9029     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
9030     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
9031     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
9032     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
9033     /* e0 */
9034     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
9035     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
9036     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
9037     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
9038     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
9039     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
9040     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
9041     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
9042     /* e8 */
9043     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
9044     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
9045     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
9046     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
9047     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
9048     { PREFIX_TABLE (PREFIX_VEX_0FED) },
9049     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
9050     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
9051     /* f0 */
9052     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
9053     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
9054     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
9055     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
9056     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
9057     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
9058     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
9059     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
9060     /* f8 */
9061     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
9062     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
9063     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
9064     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
9065     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
9066     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
9067     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
9068     { Bad_Opcode },
9069   },
9070   /* VEX_0F38 */
9071   {
9072     /* 00 */
9073     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
9078     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
9079     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
9080     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
9081     /* 08 */
9082     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
9083     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
9084     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
9085     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
9086     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
9087     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
9090     /* 10 */
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
9099     /* 18 */
9100     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
9103     { Bad_Opcode },
9104     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
9105     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
9106     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
9107     { Bad_Opcode },
9108     /* 20 */
9109     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
9113     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
9114     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     /* 28 */
9118     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
9119     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
9126     /* 30 */
9127     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
9129     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
9132     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
9135     /* 38 */
9136     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
9140     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
9141     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
9142     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
9143     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
9144     /* 40 */
9145     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
9146     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
9151     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
9152     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9153     /* 48 */
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     /* 50 */
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     /* 58 */
9172     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9173     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9174     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     /* 60 */
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     /* 68 */
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     /* 70 */
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     /* 78 */
9208     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9209     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     /* 80 */
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     /* 88 */
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9231     { Bad_Opcode },
9232     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9233     { Bad_Opcode },
9234     /* 90 */
9235     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9236     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9237     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9238     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9242     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9243     /* 98 */
9244     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9245     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9246     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9247     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9248     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9249     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9250     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9251     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9252     /* a0 */
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9260     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9261     /* a8 */
9262     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9263     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9264     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9265     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9266     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9267     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9268     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9269     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9270     /* b0 */
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9278     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9279     /* b8 */
9280     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9281     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9282     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9283     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9284     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9285     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9286     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9287     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9288     /* c0 */
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     /* c8 */
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     /* d0 */
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     { Bad_Opcode },
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315     /* d8 */
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9320     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9321     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9322     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9323     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9324     /* e0 */
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     /* e8 */
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     /* f0 */
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9346     { REG_TABLE (REG_VEX_0F38F3) },
9347     { Bad_Opcode },
9348     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9349     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9350     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9351     /* f8 */
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360   },
9361   /* VEX_0F3A */
9362   {
9363     /* 00 */
9364     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9365     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9366     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9367     { Bad_Opcode },
9368     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9369     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9370     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9371     { Bad_Opcode },
9372     /* 08 */
9373     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9374     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9375     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9376     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9377     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9378     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9379     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9380     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9381     /* 10 */
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9387     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9388     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9389     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9390     /* 18 */
9391     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9392     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     /* 20 */
9400     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9401     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9402     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     /* 28 */
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     /* 30 */
9418     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9419     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9420     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9421     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9422     { Bad_Opcode },
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     /* 38 */
9427     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9428     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     /* 40 */
9436     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9437     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9438     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9439     { Bad_Opcode },
9440     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9441     { Bad_Opcode },
9442     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9443     { Bad_Opcode },
9444     /* 48 */
9445     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9446     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9447     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9448     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9449     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     /* 50 */
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461     { Bad_Opcode },
9462     /* 58 */
9463     { Bad_Opcode },
9464     { Bad_Opcode },
9465     { Bad_Opcode },
9466     { Bad_Opcode },
9467     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9468     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9469     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9470     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9471     /* 60 */
9472     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9473     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9474     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9475     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9476     { Bad_Opcode },
9477     { Bad_Opcode },
9478     { Bad_Opcode },
9479     { Bad_Opcode },
9480     /* 68 */
9481     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9482     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9483     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9484     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9485     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9486     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9487     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9488     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9489     /* 70 */
9490     { Bad_Opcode },
9491     { Bad_Opcode },
9492     { Bad_Opcode },
9493     { Bad_Opcode },
9494     { Bad_Opcode },
9495     { Bad_Opcode },
9496     { Bad_Opcode },
9497     { Bad_Opcode },
9498     /* 78 */
9499     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9500     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9501     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9502     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9503     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9504     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9505     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9506     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9507     /* 80 */
9508     { Bad_Opcode },
9509     { Bad_Opcode },
9510     { Bad_Opcode },
9511     { Bad_Opcode },
9512     { Bad_Opcode },
9513     { Bad_Opcode },
9514     { Bad_Opcode },
9515     { Bad_Opcode },
9516     /* 88 */
9517     { Bad_Opcode },
9518     { Bad_Opcode },
9519     { Bad_Opcode },
9520     { Bad_Opcode },
9521     { Bad_Opcode },
9522     { Bad_Opcode },
9523     { Bad_Opcode },
9524     { Bad_Opcode },
9525     /* 90 */
9526     { Bad_Opcode },
9527     { Bad_Opcode },
9528     { Bad_Opcode },
9529     { Bad_Opcode },
9530     { Bad_Opcode },
9531     { Bad_Opcode },
9532     { Bad_Opcode },
9533     { Bad_Opcode },
9534     /* 98 */
9535     { Bad_Opcode },
9536     { Bad_Opcode },
9537     { Bad_Opcode },
9538     { Bad_Opcode },
9539     { Bad_Opcode },
9540     { Bad_Opcode },
9541     { Bad_Opcode },
9542     { Bad_Opcode },
9543     /* a0 */
9544     { Bad_Opcode },
9545     { Bad_Opcode },
9546     { Bad_Opcode },
9547     { Bad_Opcode },
9548     { Bad_Opcode },
9549     { Bad_Opcode },
9550     { Bad_Opcode },
9551     { Bad_Opcode },
9552     /* a8 */
9553     { Bad_Opcode },
9554     { Bad_Opcode },
9555     { Bad_Opcode },
9556     { Bad_Opcode },
9557     { Bad_Opcode },
9558     { Bad_Opcode },
9559     { Bad_Opcode },
9560     { Bad_Opcode },
9561     /* b0 */
9562     { Bad_Opcode },
9563     { Bad_Opcode },
9564     { Bad_Opcode },
9565     { Bad_Opcode },
9566     { Bad_Opcode },
9567     { Bad_Opcode },
9568     { Bad_Opcode },
9569     { Bad_Opcode },
9570     /* b8 */
9571     { Bad_Opcode },
9572     { Bad_Opcode },
9573     { Bad_Opcode },
9574     { Bad_Opcode },
9575     { Bad_Opcode },
9576     { Bad_Opcode },
9577     { Bad_Opcode },
9578     { Bad_Opcode },
9579     /* c0 */
9580     { Bad_Opcode },
9581     { Bad_Opcode },
9582     { Bad_Opcode },
9583     { Bad_Opcode },
9584     { Bad_Opcode },
9585     { Bad_Opcode },
9586     { Bad_Opcode },
9587     { Bad_Opcode },
9588     /* c8 */
9589     { Bad_Opcode },
9590     { Bad_Opcode },
9591     { Bad_Opcode },
9592     { Bad_Opcode },
9593     { Bad_Opcode },
9594     { Bad_Opcode },
9595     { Bad_Opcode },
9596     { Bad_Opcode },
9597     /* d0 */
9598     { Bad_Opcode },
9599     { Bad_Opcode },
9600     { Bad_Opcode },
9601     { Bad_Opcode },
9602     { Bad_Opcode },
9603     { Bad_Opcode },
9604     { Bad_Opcode },
9605     { Bad_Opcode },
9606     /* d8 */
9607     { Bad_Opcode },
9608     { Bad_Opcode },
9609     { Bad_Opcode },
9610     { Bad_Opcode },
9611     { Bad_Opcode },
9612     { Bad_Opcode },
9613     { Bad_Opcode },
9614     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9615     /* e0 */
9616     { Bad_Opcode },
9617     { Bad_Opcode },
9618     { Bad_Opcode },
9619     { Bad_Opcode },
9620     { Bad_Opcode },
9621     { Bad_Opcode },
9622     { Bad_Opcode },
9623     { Bad_Opcode },
9624     /* e8 */
9625     { Bad_Opcode },
9626     { Bad_Opcode },
9627     { Bad_Opcode },
9628     { Bad_Opcode },
9629     { Bad_Opcode },
9630     { Bad_Opcode },
9631     { Bad_Opcode },
9632     { Bad_Opcode },
9633     /* f0 */
9634     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9635     { Bad_Opcode },
9636     { Bad_Opcode },
9637     { Bad_Opcode },
9638     { Bad_Opcode },
9639     { Bad_Opcode },
9640     { Bad_Opcode },
9641     { Bad_Opcode },
9642     /* f8 */
9643     { Bad_Opcode },
9644     { Bad_Opcode },
9645     { Bad_Opcode },
9646     { Bad_Opcode },
9647     { Bad_Opcode },
9648     { Bad_Opcode },
9649     { Bad_Opcode },
9650     { Bad_Opcode },
9651   },
9652 };
9653
9654 #define NEED_OPCODE_TABLE
9655 #include "i386-dis-evex.h"
9656 #undef NEED_OPCODE_TABLE
9657 static const struct dis386 vex_len_table[][2] = {
9658   /* VEX_LEN_0F10_P_1 */
9659   {
9660     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9661     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9662   },
9663
9664   /* VEX_LEN_0F10_P_3 */
9665   {
9666     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9667     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9668   },
9669
9670   /* VEX_LEN_0F11_P_1 */
9671   {
9672     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9673     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9674   },
9675
9676   /* VEX_LEN_0F11_P_3 */
9677   {
9678     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9679     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9680   },
9681
9682   /* VEX_LEN_0F12_P_0_M_0 */
9683   {
9684     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9685   },
9686
9687   /* VEX_LEN_0F12_P_0_M_1 */
9688   {
9689     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9690   },
9691
9692   /* VEX_LEN_0F12_P_2 */
9693   {
9694     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9695   },
9696
9697   /* VEX_LEN_0F13_M_0 */
9698   {
9699     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9700   },
9701
9702   /* VEX_LEN_0F16_P_0_M_0 */
9703   {
9704     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9705   },
9706
9707   /* VEX_LEN_0F16_P_0_M_1 */
9708   {
9709     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9710   },
9711
9712   /* VEX_LEN_0F16_P_2 */
9713   {
9714     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9715   },
9716
9717   /* VEX_LEN_0F17_M_0 */
9718   {
9719     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9720   },
9721
9722   /* VEX_LEN_0F2A_P_1 */
9723   {
9724     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9725     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9726   },
9727
9728   /* VEX_LEN_0F2A_P_3 */
9729   {
9730     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9731     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9732   },
9733
9734   /* VEX_LEN_0F2C_P_1 */
9735   {
9736     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9737     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9738   },
9739
9740   /* VEX_LEN_0F2C_P_3 */
9741   {
9742     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9743     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9744   },
9745
9746   /* VEX_LEN_0F2D_P_1 */
9747   {
9748     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9749     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9750   },
9751
9752   /* VEX_LEN_0F2D_P_3 */
9753   {
9754     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9755     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9756   },
9757
9758   /* VEX_LEN_0F2E_P_0 */
9759   {
9760     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9761     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9762   },
9763
9764   /* VEX_LEN_0F2E_P_2 */
9765   {
9766     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9767     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9768   },
9769
9770   /* VEX_LEN_0F2F_P_0 */
9771   {
9772     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9773     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9774   },
9775
9776   /* VEX_LEN_0F2F_P_2 */
9777   {
9778     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9779     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9780   },
9781
9782   /* VEX_LEN_0F41_P_0 */
9783   {
9784     { Bad_Opcode },
9785     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9786   },
9787   /* VEX_LEN_0F41_P_2 */
9788   {
9789     { Bad_Opcode },
9790     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9791   },
9792   /* VEX_LEN_0F42_P_0 */
9793   {
9794     { Bad_Opcode },
9795     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9796   },
9797   /* VEX_LEN_0F42_P_2 */
9798   {
9799     { Bad_Opcode },
9800     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9801   },
9802   /* VEX_LEN_0F44_P_0 */
9803   {
9804     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9805   },
9806   /* VEX_LEN_0F44_P_2 */
9807   {
9808     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9809   },
9810   /* VEX_LEN_0F45_P_0 */
9811   {
9812     { Bad_Opcode },
9813     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9814   },
9815   /* VEX_LEN_0F45_P_2 */
9816   {
9817     { Bad_Opcode },
9818     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9819   },
9820   /* VEX_LEN_0F46_P_0 */
9821   {
9822     { Bad_Opcode },
9823     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9824   },
9825   /* VEX_LEN_0F46_P_2 */
9826   {
9827     { Bad_Opcode },
9828     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9829   },
9830   /* VEX_LEN_0F47_P_0 */
9831   {
9832     { Bad_Opcode },
9833     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9834   },
9835   /* VEX_LEN_0F47_P_2 */
9836   {
9837     { Bad_Opcode },
9838     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9839   },
9840   /* VEX_LEN_0F4A_P_0 */
9841   {
9842     { Bad_Opcode },
9843     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9844   },
9845   /* VEX_LEN_0F4A_P_2 */
9846   {
9847     { Bad_Opcode },
9848     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9849   },
9850   /* VEX_LEN_0F4B_P_0 */
9851   {
9852     { Bad_Opcode },
9853     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9854   },
9855   /* VEX_LEN_0F4B_P_2 */
9856   {
9857     { Bad_Opcode },
9858     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9859   },
9860
9861   /* VEX_LEN_0F51_P_1 */
9862   {
9863     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9864     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9865   },
9866
9867   /* VEX_LEN_0F51_P_3 */
9868   {
9869     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9870     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9871   },
9872
9873   /* VEX_LEN_0F52_P_1 */
9874   {
9875     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9876     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9877   },
9878
9879   /* VEX_LEN_0F53_P_1 */
9880   {
9881     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9882     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9883   },
9884
9885   /* VEX_LEN_0F58_P_1 */
9886   {
9887     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9888     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9889   },
9890
9891   /* VEX_LEN_0F58_P_3 */
9892   {
9893     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9894     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9895   },
9896
9897   /* VEX_LEN_0F59_P_1 */
9898   {
9899     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9900     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9901   },
9902
9903   /* VEX_LEN_0F59_P_3 */
9904   {
9905     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9906     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9907   },
9908
9909   /* VEX_LEN_0F5A_P_1 */
9910   {
9911     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9912     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9913   },
9914
9915   /* VEX_LEN_0F5A_P_3 */
9916   {
9917     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9918     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9919   },
9920
9921   /* VEX_LEN_0F5C_P_1 */
9922   {
9923     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9924     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9925   },
9926
9927   /* VEX_LEN_0F5C_P_3 */
9928   {
9929     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9930     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9931   },
9932
9933   /* VEX_LEN_0F5D_P_1 */
9934   {
9935     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9936     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9937   },
9938
9939   /* VEX_LEN_0F5D_P_3 */
9940   {
9941     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9942     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9943   },
9944
9945   /* VEX_LEN_0F5E_P_1 */
9946   {
9947     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9948     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9949   },
9950
9951   /* VEX_LEN_0F5E_P_3 */
9952   {
9953     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9954     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9955   },
9956
9957   /* VEX_LEN_0F5F_P_1 */
9958   {
9959     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9960     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9961   },
9962
9963   /* VEX_LEN_0F5F_P_3 */
9964   {
9965     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9966     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9967   },
9968
9969   /* VEX_LEN_0F6E_P_2 */
9970   {
9971     { "vmovK",          { XMScalar, Edq }, 0 },
9972     { "vmovK",          { XMScalar, Edq }, 0 },
9973   },
9974
9975   /* VEX_LEN_0F7E_P_1 */
9976   {
9977     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9978     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9979   },
9980
9981   /* VEX_LEN_0F7E_P_2 */
9982   {
9983     { "vmovK",          { Edq, XMScalar }, 0 },
9984     { "vmovK",          { Edq, XMScalar }, 0 },
9985   },
9986
9987   /* VEX_LEN_0F90_P_0 */
9988   {
9989     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9990   },
9991
9992   /* VEX_LEN_0F90_P_2 */
9993   {
9994     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9995   },
9996
9997   /* VEX_LEN_0F91_P_0 */
9998   {
9999     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
10000   },
10001
10002   /* VEX_LEN_0F91_P_2 */
10003   {
10004     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
10005   },
10006
10007   /* VEX_LEN_0F92_P_0 */
10008   {
10009     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
10010   },
10011
10012   /* VEX_LEN_0F92_P_2 */
10013   {
10014     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
10015   },
10016
10017   /* VEX_LEN_0F92_P_3 */
10018   {
10019     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
10020   },
10021
10022   /* VEX_LEN_0F93_P_0 */
10023   {
10024     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
10025   },
10026
10027   /* VEX_LEN_0F93_P_2 */
10028   {
10029     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
10030   },
10031
10032   /* VEX_LEN_0F93_P_3 */
10033   {
10034     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
10035   },
10036
10037   /* VEX_LEN_0F98_P_0 */
10038   {
10039     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
10040   },
10041
10042   /* VEX_LEN_0F98_P_2 */
10043   {
10044     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
10045   },
10046
10047   /* VEX_LEN_0F99_P_0 */
10048   {
10049     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
10050   },
10051
10052   /* VEX_LEN_0F99_P_2 */
10053   {
10054     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
10055   },
10056
10057   /* VEX_LEN_0FAE_R_2_M_0 */
10058   {
10059     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
10060   },
10061
10062   /* VEX_LEN_0FAE_R_3_M_0 */
10063   {
10064     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
10065   },
10066
10067   /* VEX_LEN_0FC2_P_1 */
10068   {
10069     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
10070     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
10071   },
10072
10073   /* VEX_LEN_0FC2_P_3 */
10074   {
10075     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
10076     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
10077   },
10078
10079   /* VEX_LEN_0FC4_P_2 */
10080   {
10081     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
10082   },
10083
10084   /* VEX_LEN_0FC5_P_2 */
10085   {
10086     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
10087   },
10088
10089   /* VEX_LEN_0FD6_P_2 */
10090   {
10091     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
10092     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
10093   },
10094
10095   /* VEX_LEN_0FF7_P_2 */
10096   {
10097     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
10098   },
10099
10100   /* VEX_LEN_0F3816_P_2 */
10101   {
10102     { Bad_Opcode },
10103     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
10104   },
10105
10106   /* VEX_LEN_0F3819_P_2 */
10107   {
10108     { Bad_Opcode },
10109     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
10110   },
10111
10112   /* VEX_LEN_0F381A_P_2_M_0 */
10113   {
10114     { Bad_Opcode },
10115     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
10116   },
10117
10118   /* VEX_LEN_0F3836_P_2 */
10119   {
10120     { Bad_Opcode },
10121     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
10122   },
10123
10124   /* VEX_LEN_0F3841_P_2 */
10125   {
10126     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
10127   },
10128
10129   /* VEX_LEN_0F385A_P_2_M_0 */
10130   {
10131     { Bad_Opcode },
10132     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
10133   },
10134
10135   /* VEX_LEN_0F38DB_P_2 */
10136   {
10137     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
10138   },
10139
10140   /* VEX_LEN_0F38DC_P_2 */
10141   {
10142     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
10143   },
10144
10145   /* VEX_LEN_0F38DD_P_2 */
10146   {
10147     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
10148   },
10149
10150   /* VEX_LEN_0F38DE_P_2 */
10151   {
10152     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
10153   },
10154
10155   /* VEX_LEN_0F38DF_P_2 */
10156   {
10157     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
10158   },
10159
10160   /* VEX_LEN_0F38F2_P_0 */
10161   {
10162     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
10163   },
10164
10165   /* VEX_LEN_0F38F3_R_1_P_0 */
10166   {
10167     { "blsrS",          { VexGdq, Edq }, 0 },
10168   },
10169
10170   /* VEX_LEN_0F38F3_R_2_P_0 */
10171   {
10172     { "blsmskS",        { VexGdq, Edq }, 0 },
10173   },
10174
10175   /* VEX_LEN_0F38F3_R_3_P_0 */
10176   {
10177     { "blsiS",          { VexGdq, Edq }, 0 },
10178   },
10179
10180   /* VEX_LEN_0F38F5_P_0 */
10181   {
10182     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
10183   },
10184
10185   /* VEX_LEN_0F38F5_P_1 */
10186   {
10187     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
10188   },
10189
10190   /* VEX_LEN_0F38F5_P_3 */
10191   {
10192     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
10193   },
10194
10195   /* VEX_LEN_0F38F6_P_3 */
10196   {
10197     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
10198   },
10199
10200   /* VEX_LEN_0F38F7_P_0 */
10201   {
10202     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
10203   },
10204
10205   /* VEX_LEN_0F38F7_P_1 */
10206   {
10207     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10208   },
10209
10210   /* VEX_LEN_0F38F7_P_2 */
10211   {
10212     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10213   },
10214
10215   /* VEX_LEN_0F38F7_P_3 */
10216   {
10217     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10218   },
10219
10220   /* VEX_LEN_0F3A00_P_2 */
10221   {
10222     { Bad_Opcode },
10223     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10224   },
10225
10226   /* VEX_LEN_0F3A01_P_2 */
10227   {
10228     { Bad_Opcode },
10229     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10230   },
10231
10232   /* VEX_LEN_0F3A06_P_2 */
10233   {
10234     { Bad_Opcode },
10235     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10236   },
10237
10238   /* VEX_LEN_0F3A0A_P_2 */
10239   {
10240     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10241     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10242   },
10243
10244   /* VEX_LEN_0F3A0B_P_2 */
10245   {
10246     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10247     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10248   },
10249
10250   /* VEX_LEN_0F3A14_P_2 */
10251   {
10252     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10253   },
10254
10255   /* VEX_LEN_0F3A15_P_2 */
10256   {
10257     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10258   },
10259
10260   /* VEX_LEN_0F3A16_P_2  */
10261   {
10262     { "vpextrK",        { Edq, XM, Ib }, 0 },
10263   },
10264
10265   /* VEX_LEN_0F3A17_P_2 */
10266   {
10267     { "vextractps",     { Edqd, XM, Ib }, 0 },
10268   },
10269
10270   /* VEX_LEN_0F3A18_P_2 */
10271   {
10272     { Bad_Opcode },
10273     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10274   },
10275
10276   /* VEX_LEN_0F3A19_P_2 */
10277   {
10278     { Bad_Opcode },
10279     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10280   },
10281
10282   /* VEX_LEN_0F3A20_P_2 */
10283   {
10284     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10285   },
10286
10287   /* VEX_LEN_0F3A21_P_2 */
10288   {
10289     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10290   },
10291
10292   /* VEX_LEN_0F3A22_P_2 */
10293   {
10294     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10295   },
10296
10297   /* VEX_LEN_0F3A30_P_2 */
10298   {
10299     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10300   },
10301
10302   /* VEX_LEN_0F3A31_P_2 */
10303   {
10304     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10305   },
10306
10307   /* VEX_LEN_0F3A32_P_2 */
10308   {
10309     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10310   },
10311
10312   /* VEX_LEN_0F3A33_P_2 */
10313   {
10314     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10315   },
10316
10317   /* VEX_LEN_0F3A38_P_2 */
10318   {
10319     { Bad_Opcode },
10320     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10321   },
10322
10323   /* VEX_LEN_0F3A39_P_2 */
10324   {
10325     { Bad_Opcode },
10326     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10327   },
10328
10329   /* VEX_LEN_0F3A41_P_2 */
10330   {
10331     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10332   },
10333
10334   /* VEX_LEN_0F3A44_P_2 */
10335   {
10336     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10337   },
10338
10339   /* VEX_LEN_0F3A46_P_2 */
10340   {
10341     { Bad_Opcode },
10342     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10343   },
10344
10345   /* VEX_LEN_0F3A60_P_2 */
10346   {
10347     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10348   },
10349
10350   /* VEX_LEN_0F3A61_P_2 */
10351   {
10352     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10353   },
10354
10355   /* VEX_LEN_0F3A62_P_2 */
10356   {
10357     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10358   },
10359
10360   /* VEX_LEN_0F3A63_P_2 */
10361   {
10362     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10363   },
10364
10365   /* VEX_LEN_0F3A6A_P_2 */
10366   {
10367     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10368   },
10369
10370   /* VEX_LEN_0F3A6B_P_2 */
10371   {
10372     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10373   },
10374
10375   /* VEX_LEN_0F3A6E_P_2 */
10376   {
10377     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10378   },
10379
10380   /* VEX_LEN_0F3A6F_P_2 */
10381   {
10382     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10383   },
10384
10385   /* VEX_LEN_0F3A7A_P_2 */
10386   {
10387     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10388   },
10389
10390   /* VEX_LEN_0F3A7B_P_2 */
10391   {
10392     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10393   },
10394
10395   /* VEX_LEN_0F3A7E_P_2 */
10396   {
10397     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10398   },
10399
10400   /* VEX_LEN_0F3A7F_P_2 */
10401   {
10402     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10403   },
10404
10405   /* VEX_LEN_0F3ADF_P_2 */
10406   {
10407     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10408   },
10409
10410   /* VEX_LEN_0F3AF0_P_3 */
10411   {
10412     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10413   },
10414
10415   /* VEX_LEN_0FXOP_08_CC */
10416   {
10417      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10418   },
10419
10420   /* VEX_LEN_0FXOP_08_CD */
10421   {
10422      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10423   },
10424
10425   /* VEX_LEN_0FXOP_08_CE */
10426   {
10427      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10428   },
10429
10430   /* VEX_LEN_0FXOP_08_CF */
10431   {
10432      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10433   },
10434
10435   /* VEX_LEN_0FXOP_08_EC */
10436   {
10437      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10438   },
10439
10440   /* VEX_LEN_0FXOP_08_ED */
10441   {
10442      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10443   },
10444
10445   /* VEX_LEN_0FXOP_08_EE */
10446   {
10447      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10448   },
10449
10450   /* VEX_LEN_0FXOP_08_EF */
10451   {
10452      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10453   },
10454
10455   /* VEX_LEN_0FXOP_09_80 */
10456   {
10457     { "vfrczps",        { XM, EXxmm }, 0 },
10458     { "vfrczps",        { XM, EXymmq }, 0 },
10459   },
10460
10461   /* VEX_LEN_0FXOP_09_81 */
10462   {
10463     { "vfrczpd",        { XM, EXxmm }, 0 },
10464     { "vfrczpd",        { XM, EXymmq }, 0 },
10465   },
10466 };
10467
10468 static const struct dis386 vex_w_table[][2] = {
10469   {
10470     /* VEX_W_0F10_P_0 */
10471     { "vmovups",        { XM, EXx }, 0 },
10472   },
10473   {
10474     /* VEX_W_0F10_P_1 */
10475     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10476   },
10477   {
10478     /* VEX_W_0F10_P_2 */
10479     { "vmovupd",        { XM, EXx }, 0 },
10480   },
10481   {
10482     /* VEX_W_0F10_P_3 */
10483     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10484   },
10485   {
10486     /* VEX_W_0F11_P_0 */
10487     { "vmovups",        { EXxS, XM }, 0 },
10488   },
10489   {
10490     /* VEX_W_0F11_P_1 */
10491     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10492   },
10493   {
10494     /* VEX_W_0F11_P_2 */
10495     { "vmovupd",        { EXxS, XM }, 0 },
10496   },
10497   {
10498     /* VEX_W_0F11_P_3 */
10499     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10500   },
10501   {
10502     /* VEX_W_0F12_P_0_M_0 */
10503     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10504   },
10505   {
10506     /* VEX_W_0F12_P_0_M_1 */
10507     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10508   },
10509   {
10510     /* VEX_W_0F12_P_1 */
10511     { "vmovsldup",      { XM, EXx }, 0 },
10512   },
10513   {
10514     /* VEX_W_0F12_P_2 */
10515     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10516   },
10517   {
10518     /* VEX_W_0F12_P_3 */
10519     { "vmovddup",       { XM, EXymmq }, 0 },
10520   },
10521   {
10522     /* VEX_W_0F13_M_0 */
10523     { "vmovlpX",        { EXq, XM }, 0 },
10524   },
10525   {
10526     /* VEX_W_0F14 */
10527     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10528   },
10529   {
10530     /* VEX_W_0F15 */
10531     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10532   },
10533   {
10534     /* VEX_W_0F16_P_0_M_0 */
10535     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10536   },
10537   {
10538     /* VEX_W_0F16_P_0_M_1 */
10539     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10540   },
10541   {
10542     /* VEX_W_0F16_P_1 */
10543     { "vmovshdup",      { XM, EXx }, 0 },
10544   },
10545   {
10546     /* VEX_W_0F16_P_2 */
10547     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10548   },
10549   {
10550     /* VEX_W_0F17_M_0 */
10551     { "vmovhpX",        { EXq, XM }, 0 },
10552   },
10553   {
10554     /* VEX_W_0F28 */
10555     { "vmovapX",        { XM, EXx }, 0 },
10556   },
10557   {
10558     /* VEX_W_0F29 */
10559     { "vmovapX",        { EXxS, XM }, 0 },
10560   },
10561   {
10562     /* VEX_W_0F2B_M_0 */
10563     { "vmovntpX",       { Mx, XM }, 0 },
10564   },
10565   {
10566     /* VEX_W_0F2E_P_0 */
10567     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10568   },
10569   {
10570     /* VEX_W_0F2E_P_2 */
10571     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10572   },
10573   {
10574     /* VEX_W_0F2F_P_0 */
10575     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10576   },
10577   {
10578     /* VEX_W_0F2F_P_2 */
10579     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10580   },
10581   {
10582     /* VEX_W_0F41_P_0_LEN_1 */
10583     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10584     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10585   },
10586   {
10587     /* VEX_W_0F41_P_2_LEN_1 */
10588     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10589     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10590   },
10591   {
10592     /* VEX_W_0F42_P_0_LEN_1 */
10593     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10594     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10595   },
10596   {
10597     /* VEX_W_0F42_P_2_LEN_1 */
10598     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10599     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10600   },
10601   {
10602     /* VEX_W_0F44_P_0_LEN_0 */
10603     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10604     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10605   },
10606   {
10607     /* VEX_W_0F44_P_2_LEN_0 */
10608     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10609     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10610   },
10611   {
10612     /* VEX_W_0F45_P_0_LEN_1 */
10613     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10614     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10615   },
10616   {
10617     /* VEX_W_0F45_P_2_LEN_1 */
10618     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10619     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10620   },
10621   {
10622     /* VEX_W_0F46_P_0_LEN_1 */
10623     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10624     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10625   },
10626   {
10627     /* VEX_W_0F46_P_2_LEN_1 */
10628     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10629     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10630   },
10631   {
10632     /* VEX_W_0F47_P_0_LEN_1 */
10633     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10634     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10635   },
10636   {
10637     /* VEX_W_0F47_P_2_LEN_1 */
10638     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10639     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10640   },
10641   {
10642     /* VEX_W_0F4A_P_0_LEN_1 */
10643     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10644     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10645   },
10646   {
10647     /* VEX_W_0F4A_P_2_LEN_1 */
10648     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10649     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10650   },
10651   {
10652     /* VEX_W_0F4B_P_0_LEN_1 */
10653     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10654     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10655   },
10656   {
10657     /* VEX_W_0F4B_P_2_LEN_1 */
10658     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10659   },
10660   {
10661     /* VEX_W_0F50_M_0 */
10662     { "vmovmskpX",      { Gdq, XS }, 0 },
10663   },
10664   {
10665     /* VEX_W_0F51_P_0 */
10666     { "vsqrtps",        { XM, EXx }, 0 },
10667   },
10668   {
10669     /* VEX_W_0F51_P_1 */
10670     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10671   },
10672   {
10673     /* VEX_W_0F51_P_2  */
10674     { "vsqrtpd",        { XM, EXx }, 0 },
10675   },
10676   {
10677     /* VEX_W_0F51_P_3 */
10678     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10679   },
10680   {
10681     /* VEX_W_0F52_P_0 */
10682     { "vrsqrtps",       { XM, EXx }, 0 },
10683   },
10684   {
10685     /* VEX_W_0F52_P_1 */
10686     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10687   },
10688   {
10689     /* VEX_W_0F53_P_0  */
10690     { "vrcpps",         { XM, EXx }, 0 },
10691   },
10692   {
10693     /* VEX_W_0F53_P_1  */
10694     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10695   },
10696   {
10697     /* VEX_W_0F58_P_0  */
10698     { "vaddps",         { XM, Vex, EXx }, 0 },
10699   },
10700   {
10701     /* VEX_W_0F58_P_1  */
10702     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10703   },
10704   {
10705     /* VEX_W_0F58_P_2  */
10706     { "vaddpd",         { XM, Vex, EXx }, 0 },
10707   },
10708   {
10709     /* VEX_W_0F58_P_3  */
10710     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10711   },
10712   {
10713     /* VEX_W_0F59_P_0  */
10714     { "vmulps",         { XM, Vex, EXx }, 0 },
10715   },
10716   {
10717     /* VEX_W_0F59_P_1  */
10718     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10719   },
10720   {
10721     /* VEX_W_0F59_P_2  */
10722     { "vmulpd",         { XM, Vex, EXx }, 0 },
10723   },
10724   {
10725     /* VEX_W_0F59_P_3  */
10726     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10727   },
10728   {
10729     /* VEX_W_0F5A_P_0  */
10730     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10731   },
10732   {
10733     /* VEX_W_0F5A_P_1  */
10734     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10735   },
10736   {
10737     /* VEX_W_0F5A_P_3  */
10738     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10739   },
10740   {
10741     /* VEX_W_0F5B_P_0  */
10742     { "vcvtdq2ps",      { XM, EXx }, 0 },
10743   },
10744   {
10745     /* VEX_W_0F5B_P_1  */
10746     { "vcvttps2dq",     { XM, EXx }, 0 },
10747   },
10748   {
10749     /* VEX_W_0F5B_P_2  */
10750     { "vcvtps2dq",      { XM, EXx }, 0 },
10751   },
10752   {
10753     /* VEX_W_0F5C_P_0  */
10754     { "vsubps",         { XM, Vex, EXx }, 0 },
10755   },
10756   {
10757     /* VEX_W_0F5C_P_1  */
10758     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10759   },
10760   {
10761     /* VEX_W_0F5C_P_2  */
10762     { "vsubpd",         { XM, Vex, EXx }, 0 },
10763   },
10764   {
10765     /* VEX_W_0F5C_P_3  */
10766     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10767   },
10768   {
10769     /* VEX_W_0F5D_P_0  */
10770     { "vminps",         { XM, Vex, EXx }, 0 },
10771   },
10772   {
10773     /* VEX_W_0F5D_P_1  */
10774     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10775   },
10776   {
10777     /* VEX_W_0F5D_P_2  */
10778     { "vminpd",         { XM, Vex, EXx }, 0 },
10779   },
10780   {
10781     /* VEX_W_0F5D_P_3  */
10782     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10783   },
10784   {
10785     /* VEX_W_0F5E_P_0  */
10786     { "vdivps",         { XM, Vex, EXx }, 0 },
10787   },
10788   {
10789     /* VEX_W_0F5E_P_1  */
10790     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10791   },
10792   {
10793     /* VEX_W_0F5E_P_2  */
10794     { "vdivpd",         { XM, Vex, EXx }, 0 },
10795   },
10796   {
10797     /* VEX_W_0F5E_P_3  */
10798     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10799   },
10800   {
10801     /* VEX_W_0F5F_P_0  */
10802     { "vmaxps",         { XM, Vex, EXx }, 0 },
10803   },
10804   {
10805     /* VEX_W_0F5F_P_1  */
10806     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10807   },
10808   {
10809     /* VEX_W_0F5F_P_2  */
10810     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10811   },
10812   {
10813     /* VEX_W_0F5F_P_3  */
10814     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10815   },
10816   {
10817     /* VEX_W_0F60_P_2  */
10818     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10819   },
10820   {
10821     /* VEX_W_0F61_P_2  */
10822     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10823   },
10824   {
10825     /* VEX_W_0F62_P_2  */
10826     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10827   },
10828   {
10829     /* VEX_W_0F63_P_2  */
10830     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10831   },
10832   {
10833     /* VEX_W_0F64_P_2  */
10834     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10835   },
10836   {
10837     /* VEX_W_0F65_P_2  */
10838     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10839   },
10840   {
10841     /* VEX_W_0F66_P_2  */
10842     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10843   },
10844   {
10845     /* VEX_W_0F67_P_2  */
10846     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10847   },
10848   {
10849     /* VEX_W_0F68_P_2  */
10850     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10851   },
10852   {
10853     /* VEX_W_0F69_P_2  */
10854     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10855   },
10856   {
10857     /* VEX_W_0F6A_P_2  */
10858     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10859   },
10860   {
10861     /* VEX_W_0F6B_P_2  */
10862     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10863   },
10864   {
10865     /* VEX_W_0F6C_P_2  */
10866     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10867   },
10868   {
10869     /* VEX_W_0F6D_P_2  */
10870     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10871   },
10872   {
10873     /* VEX_W_0F6F_P_1  */
10874     { "vmovdqu",        { XM, EXx }, 0 },
10875   },
10876   {
10877     /* VEX_W_0F6F_P_2  */
10878     { "vmovdqa",        { XM, EXx }, 0 },
10879   },
10880   {
10881     /* VEX_W_0F70_P_1 */
10882     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10883   },
10884   {
10885     /* VEX_W_0F70_P_2 */
10886     { "vpshufd",        { XM, EXx, Ib }, 0 },
10887   },
10888   {
10889     /* VEX_W_0F70_P_3 */
10890     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10891   },
10892   {
10893     /* VEX_W_0F71_R_2_P_2  */
10894     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10895   },
10896   {
10897     /* VEX_W_0F71_R_4_P_2  */
10898     { "vpsraw",         { Vex, XS, Ib }, 0 },
10899   },
10900   {
10901     /* VEX_W_0F71_R_6_P_2  */
10902     { "vpsllw",         { Vex, XS, Ib }, 0 },
10903   },
10904   {
10905     /* VEX_W_0F72_R_2_P_2  */
10906     { "vpsrld",         { Vex, XS, Ib }, 0 },
10907   },
10908   {
10909     /* VEX_W_0F72_R_4_P_2  */
10910     { "vpsrad",         { Vex, XS, Ib }, 0 },
10911   },
10912   {
10913     /* VEX_W_0F72_R_6_P_2  */
10914     { "vpslld",         { Vex, XS, Ib }, 0 },
10915   },
10916   {
10917     /* VEX_W_0F73_R_2_P_2  */
10918     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10919   },
10920   {
10921     /* VEX_W_0F73_R_3_P_2  */
10922     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10923   },
10924   {
10925     /* VEX_W_0F73_R_6_P_2  */
10926     { "vpsllq",         { Vex, XS, Ib }, 0 },
10927   },
10928   {
10929     /* VEX_W_0F73_R_7_P_2  */
10930     { "vpslldq",        { Vex, XS, Ib }, 0 },
10931   },
10932   {
10933     /* VEX_W_0F74_P_2 */
10934     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10935   },
10936   {
10937     /* VEX_W_0F75_P_2 */
10938     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10939   },
10940   {
10941     /* VEX_W_0F76_P_2 */
10942     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10943   },
10944   {
10945     /* VEX_W_0F77_P_0 */
10946     { "",               { VZERO }, 0 },
10947   },
10948   {
10949     /* VEX_W_0F7C_P_2 */
10950     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10951   },
10952   {
10953     /* VEX_W_0F7C_P_3 */
10954     { "vhaddps",        { XM, Vex, EXx }, 0 },
10955   },
10956   {
10957     /* VEX_W_0F7D_P_2 */
10958     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10959   },
10960   {
10961     /* VEX_W_0F7D_P_3 */
10962     { "vhsubps",        { XM, Vex, EXx }, 0 },
10963   },
10964   {
10965     /* VEX_W_0F7E_P_1 */
10966     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10967   },
10968   {
10969     /* VEX_W_0F7F_P_1 */
10970     { "vmovdqu",        { EXxS, XM }, 0 },
10971   },
10972   {
10973     /* VEX_W_0F7F_P_2 */
10974     { "vmovdqa",        { EXxS, XM }, 0 },
10975   },
10976   {
10977     /* VEX_W_0F90_P_0_LEN_0 */
10978     { "kmovw",          { MaskG, MaskE }, 0 },
10979     { "kmovq",          { MaskG, MaskE }, 0 },
10980   },
10981   {
10982     /* VEX_W_0F90_P_2_LEN_0 */
10983     { "kmovb",          { MaskG, MaskBDE }, 0 },
10984     { "kmovd",          { MaskG, MaskBDE }, 0 },
10985   },
10986   {
10987     /* VEX_W_0F91_P_0_LEN_0 */
10988     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10989     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10990   },
10991   {
10992     /* VEX_W_0F91_P_2_LEN_0 */
10993     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10994     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10995   },
10996   {
10997     /* VEX_W_0F92_P_0_LEN_0 */
10998     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10999   },
11000   {
11001     /* VEX_W_0F92_P_2_LEN_0 */
11002     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
11003   },
11004   {
11005     /* VEX_W_0F92_P_3_LEN_0 */
11006     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
11007     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
11008   },
11009   {
11010     /* VEX_W_0F93_P_0_LEN_0 */
11011     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
11012   },
11013   {
11014     /* VEX_W_0F93_P_2_LEN_0 */
11015     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
11016   },
11017   {
11018     /* VEX_W_0F93_P_3_LEN_0 */
11019     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
11020     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
11021   },
11022   {
11023     /* VEX_W_0F98_P_0_LEN_0 */
11024     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
11025     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
11026   },
11027   {
11028     /* VEX_W_0F98_P_2_LEN_0 */
11029     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
11030     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
11031   },
11032   {
11033     /* VEX_W_0F99_P_0_LEN_0 */
11034     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
11035     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
11036   },
11037   {
11038     /* VEX_W_0F99_P_2_LEN_0 */
11039     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
11040     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
11041   },
11042   {
11043     /* VEX_W_0FAE_R_2_M_0 */
11044     { "vldmxcsr",       { Md }, 0 },
11045   },
11046   {
11047     /* VEX_W_0FAE_R_3_M_0 */
11048     { "vstmxcsr",       { Md }, 0 },
11049   },
11050   {
11051     /* VEX_W_0FC2_P_0 */
11052     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
11053   },
11054   {
11055     /* VEX_W_0FC2_P_1 */
11056     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
11057   },
11058   {
11059     /* VEX_W_0FC2_P_2 */
11060     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
11061   },
11062   {
11063     /* VEX_W_0FC2_P_3 */
11064     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
11065   },
11066   {
11067     /* VEX_W_0FC4_P_2 */
11068     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
11069   },
11070   {
11071     /* VEX_W_0FC5_P_2 */
11072     { "vpextrw",        { Gdq, XS, Ib }, 0 },
11073   },
11074   {
11075     /* VEX_W_0FD0_P_2 */
11076     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
11077   },
11078   {
11079     /* VEX_W_0FD0_P_3 */
11080     { "vaddsubps",      { XM, Vex, EXx }, 0 },
11081   },
11082   {
11083     /* VEX_W_0FD1_P_2 */
11084     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
11085   },
11086   {
11087     /* VEX_W_0FD2_P_2 */
11088     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
11089   },
11090   {
11091     /* VEX_W_0FD3_P_2 */
11092     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
11093   },
11094   {
11095     /* VEX_W_0FD4_P_2 */
11096     { "vpaddq",         { XM, Vex, EXx }, 0 },
11097   },
11098   {
11099     /* VEX_W_0FD5_P_2 */
11100     { "vpmullw",        { XM, Vex, EXx }, 0 },
11101   },
11102   {
11103     /* VEX_W_0FD6_P_2 */
11104     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
11105   },
11106   {
11107     /* VEX_W_0FD7_P_2_M_1 */
11108     { "vpmovmskb",      { Gdq, XS }, 0 },
11109   },
11110   {
11111     /* VEX_W_0FD8_P_2 */
11112     { "vpsubusb",       { XM, Vex, EXx }, 0 },
11113   },
11114   {
11115     /* VEX_W_0FD9_P_2 */
11116     { "vpsubusw",       { XM, Vex, EXx }, 0 },
11117   },
11118   {
11119     /* VEX_W_0FDA_P_2 */
11120     { "vpminub",        { XM, Vex, EXx }, 0 },
11121   },
11122   {
11123     /* VEX_W_0FDB_P_2 */
11124     { "vpand",          { XM, Vex, EXx }, 0 },
11125   },
11126   {
11127     /* VEX_W_0FDC_P_2 */
11128     { "vpaddusb",       { XM, Vex, EXx }, 0 },
11129   },
11130   {
11131     /* VEX_W_0FDD_P_2 */
11132     { "vpaddusw",       { XM, Vex, EXx }, 0 },
11133   },
11134   {
11135     /* VEX_W_0FDE_P_2 */
11136     { "vpmaxub",        { XM, Vex, EXx }, 0 },
11137   },
11138   {
11139     /* VEX_W_0FDF_P_2 */
11140     { "vpandn",         { XM, Vex, EXx }, 0 },
11141   },
11142   {
11143     /* VEX_W_0FE0_P_2  */
11144     { "vpavgb",         { XM, Vex, EXx }, 0 },
11145   },
11146   {
11147     /* VEX_W_0FE1_P_2  */
11148     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
11149   },
11150   {
11151     /* VEX_W_0FE2_P_2  */
11152     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
11153   },
11154   {
11155     /* VEX_W_0FE3_P_2  */
11156     { "vpavgw",         { XM, Vex, EXx }, 0 },
11157   },
11158   {
11159     /* VEX_W_0FE4_P_2  */
11160     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
11161   },
11162   {
11163     /* VEX_W_0FE5_P_2  */
11164     { "vpmulhw",        { XM, Vex, EXx }, 0 },
11165   },
11166   {
11167     /* VEX_W_0FE6_P_1  */
11168     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
11169   },
11170   {
11171     /* VEX_W_0FE6_P_2  */
11172     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
11173   },
11174   {
11175     /* VEX_W_0FE6_P_3  */
11176     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
11177   },
11178   {
11179     /* VEX_W_0FE7_P_2_M_0 */
11180     { "vmovntdq",       { Mx, XM }, 0 },
11181   },
11182   {
11183     /* VEX_W_0FE8_P_2  */
11184     { "vpsubsb",        { XM, Vex, EXx }, 0 },
11185   },
11186   {
11187     /* VEX_W_0FE9_P_2  */
11188     { "vpsubsw",        { XM, Vex, EXx }, 0 },
11189   },
11190   {
11191     /* VEX_W_0FEA_P_2  */
11192     { "vpminsw",        { XM, Vex, EXx }, 0 },
11193   },
11194   {
11195     /* VEX_W_0FEB_P_2  */
11196     { "vpor",           { XM, Vex, EXx }, 0 },
11197   },
11198   {
11199     /* VEX_W_0FEC_P_2  */
11200     { "vpaddsb",        { XM, Vex, EXx }, 0 },
11201   },
11202   {
11203     /* VEX_W_0FED_P_2  */
11204     { "vpaddsw",        { XM, Vex, EXx }, 0 },
11205   },
11206   {
11207     /* VEX_W_0FEE_P_2  */
11208     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
11209   },
11210   {
11211     /* VEX_W_0FEF_P_2  */
11212     { "vpxor",          { XM, Vex, EXx }, 0 },
11213   },
11214   {
11215     /* VEX_W_0FF0_P_3_M_0 */
11216     { "vlddqu",         { XM, M }, 0 },
11217   },
11218   {
11219     /* VEX_W_0FF1_P_2 */
11220     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11221   },
11222   {
11223     /* VEX_W_0FF2_P_2 */
11224     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11225   },
11226   {
11227     /* VEX_W_0FF3_P_2 */
11228     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11229   },
11230   {
11231     /* VEX_W_0FF4_P_2 */
11232     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11233   },
11234   {
11235     /* VEX_W_0FF5_P_2 */
11236     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11237   },
11238   {
11239     /* VEX_W_0FF6_P_2 */
11240     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11241   },
11242   {
11243     /* VEX_W_0FF7_P_2 */
11244     { "vmaskmovdqu",    { XM, XS }, 0 },
11245   },
11246   {
11247     /* VEX_W_0FF8_P_2 */
11248     { "vpsubb",         { XM, Vex, EXx }, 0 },
11249   },
11250   {
11251     /* VEX_W_0FF9_P_2 */
11252     { "vpsubw",         { XM, Vex, EXx }, 0 },
11253   },
11254   {
11255     /* VEX_W_0FFA_P_2 */
11256     { "vpsubd",         { XM, Vex, EXx }, 0 },
11257   },
11258   {
11259     /* VEX_W_0FFB_P_2 */
11260     { "vpsubq",         { XM, Vex, EXx }, 0 },
11261   },
11262   {
11263     /* VEX_W_0FFC_P_2 */
11264     { "vpaddb",         { XM, Vex, EXx }, 0 },
11265   },
11266   {
11267     /* VEX_W_0FFD_P_2 */
11268     { "vpaddw",         { XM, Vex, EXx }, 0 },
11269   },
11270   {
11271     /* VEX_W_0FFE_P_2 */
11272     { "vpaddd",         { XM, Vex, EXx }, 0 },
11273   },
11274   {
11275     /* VEX_W_0F3800_P_2  */
11276     { "vpshufb",        { XM, Vex, EXx }, 0 },
11277   },
11278   {
11279     /* VEX_W_0F3801_P_2  */
11280     { "vphaddw",        { XM, Vex, EXx }, 0 },
11281   },
11282   {
11283     /* VEX_W_0F3802_P_2  */
11284     { "vphaddd",        { XM, Vex, EXx }, 0 },
11285   },
11286   {
11287     /* VEX_W_0F3803_P_2  */
11288     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11289   },
11290   {
11291     /* VEX_W_0F3804_P_2  */
11292     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11293   },
11294   {
11295     /* VEX_W_0F3805_P_2  */
11296     { "vphsubw",        { XM, Vex, EXx }, 0 },
11297   },
11298   {
11299     /* VEX_W_0F3806_P_2  */
11300     { "vphsubd",        { XM, Vex, EXx }, 0 },
11301   },
11302   {
11303     /* VEX_W_0F3807_P_2  */
11304     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11305   },
11306   {
11307     /* VEX_W_0F3808_P_2  */
11308     { "vpsignb",        { XM, Vex, EXx }, 0 },
11309   },
11310   {
11311     /* VEX_W_0F3809_P_2  */
11312     { "vpsignw",        { XM, Vex, EXx }, 0 },
11313   },
11314   {
11315     /* VEX_W_0F380A_P_2  */
11316     { "vpsignd",        { XM, Vex, EXx }, 0 },
11317   },
11318   {
11319     /* VEX_W_0F380B_P_2  */
11320     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11321   },
11322   {
11323     /* VEX_W_0F380C_P_2  */
11324     { "vpermilps",      { XM, Vex, EXx }, 0 },
11325   },
11326   {
11327     /* VEX_W_0F380D_P_2  */
11328     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11329   },
11330   {
11331     /* VEX_W_0F380E_P_2  */
11332     { "vtestps",        { XM, EXx }, 0 },
11333   },
11334   {
11335     /* VEX_W_0F380F_P_2  */
11336     { "vtestpd",        { XM, EXx }, 0 },
11337   },
11338   {
11339     /* VEX_W_0F3816_P_2  */
11340     { "vpermps",        { XM, Vex, EXx }, 0 },
11341   },
11342   {
11343     /* VEX_W_0F3817_P_2 */
11344     { "vptest",         { XM, EXx }, 0 },
11345   },
11346   {
11347     /* VEX_W_0F3818_P_2 */
11348     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11349   },
11350   {
11351     /* VEX_W_0F3819_P_2 */
11352     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11353   },
11354   {
11355     /* VEX_W_0F381A_P_2_M_0 */
11356     { "vbroadcastf128", { XM, Mxmm }, 0 },
11357   },
11358   {
11359     /* VEX_W_0F381C_P_2 */
11360     { "vpabsb",         { XM, EXx }, 0 },
11361   },
11362   {
11363     /* VEX_W_0F381D_P_2 */
11364     { "vpabsw",         { XM, EXx }, 0 },
11365   },
11366   {
11367     /* VEX_W_0F381E_P_2 */
11368     { "vpabsd",         { XM, EXx }, 0 },
11369   },
11370   {
11371     /* VEX_W_0F3820_P_2 */
11372     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11373   },
11374   {
11375     /* VEX_W_0F3821_P_2 */
11376     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11377   },
11378   {
11379     /* VEX_W_0F3822_P_2 */
11380     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11381   },
11382   {
11383     /* VEX_W_0F3823_P_2 */
11384     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11385   },
11386   {
11387     /* VEX_W_0F3824_P_2 */
11388     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11389   },
11390   {
11391     /* VEX_W_0F3825_P_2 */
11392     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11393   },
11394   {
11395     /* VEX_W_0F3828_P_2 */
11396     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11397   },
11398   {
11399     /* VEX_W_0F3829_P_2 */
11400     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11401   },
11402   {
11403     /* VEX_W_0F382A_P_2_M_0 */
11404     { "vmovntdqa",      { XM, Mx }, 0 },
11405   },
11406   {
11407     /* VEX_W_0F382B_P_2 */
11408     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11409   },
11410   {
11411     /* VEX_W_0F382C_P_2_M_0 */
11412     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11413   },
11414   {
11415     /* VEX_W_0F382D_P_2_M_0 */
11416     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11417   },
11418   {
11419     /* VEX_W_0F382E_P_2_M_0 */
11420     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11421   },
11422   {
11423     /* VEX_W_0F382F_P_2_M_0 */
11424     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11425   },
11426   {
11427     /* VEX_W_0F3830_P_2 */
11428     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11429   },
11430   {
11431     /* VEX_W_0F3831_P_2 */
11432     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11433   },
11434   {
11435     /* VEX_W_0F3832_P_2 */
11436     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11437   },
11438   {
11439     /* VEX_W_0F3833_P_2 */
11440     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11441   },
11442   {
11443     /* VEX_W_0F3834_P_2 */
11444     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11445   },
11446   {
11447     /* VEX_W_0F3835_P_2 */
11448     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11449   },
11450   {
11451     /* VEX_W_0F3836_P_2  */
11452     { "vpermd",         { XM, Vex, EXx }, 0 },
11453   },
11454   {
11455     /* VEX_W_0F3837_P_2 */
11456     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11457   },
11458   {
11459     /* VEX_W_0F3838_P_2 */
11460     { "vpminsb",        { XM, Vex, EXx }, 0 },
11461   },
11462   {
11463     /* VEX_W_0F3839_P_2 */
11464     { "vpminsd",        { XM, Vex, EXx }, 0 },
11465   },
11466   {
11467     /* VEX_W_0F383A_P_2 */
11468     { "vpminuw",        { XM, Vex, EXx }, 0 },
11469   },
11470   {
11471     /* VEX_W_0F383B_P_2 */
11472     { "vpminud",        { XM, Vex, EXx }, 0 },
11473   },
11474   {
11475     /* VEX_W_0F383C_P_2 */
11476     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11477   },
11478   {
11479     /* VEX_W_0F383D_P_2 */
11480     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11481   },
11482   {
11483     /* VEX_W_0F383E_P_2 */
11484     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11485   },
11486   {
11487     /* VEX_W_0F383F_P_2 */
11488     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11489   },
11490   {
11491     /* VEX_W_0F3840_P_2 */
11492     { "vpmulld",        { XM, Vex, EXx }, 0 },
11493   },
11494   {
11495     /* VEX_W_0F3841_P_2 */
11496     { "vphminposuw",    { XM, EXx }, 0 },
11497   },
11498   {
11499     /* VEX_W_0F3846_P_2 */
11500     { "vpsravd",        { XM, Vex, EXx }, 0 },
11501   },
11502   {
11503     /* VEX_W_0F3858_P_2 */
11504     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11505   },
11506   {
11507     /* VEX_W_0F3859_P_2 */
11508     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11509   },
11510   {
11511     /* VEX_W_0F385A_P_2_M_0 */
11512     { "vbroadcasti128", { XM, Mxmm }, 0 },
11513   },
11514   {
11515     /* VEX_W_0F3878_P_2 */
11516     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11517   },
11518   {
11519     /* VEX_W_0F3879_P_2 */
11520     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11521   },
11522   {
11523     /* VEX_W_0F38DB_P_2 */
11524     { "vaesimc",        { XM, EXx }, 0 },
11525   },
11526   {
11527     /* VEX_W_0F38DC_P_2 */
11528     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11529   },
11530   {
11531     /* VEX_W_0F38DD_P_2 */
11532     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11533   },
11534   {
11535     /* VEX_W_0F38DE_P_2 */
11536     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11537   },
11538   {
11539     /* VEX_W_0F38DF_P_2 */
11540     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11541   },
11542   {
11543     /* VEX_W_0F3A00_P_2 */
11544     { Bad_Opcode },
11545     { "vpermq",         { XM, EXx, Ib }, 0 },
11546   },
11547   {
11548     /* VEX_W_0F3A01_P_2 */
11549     { Bad_Opcode },
11550     { "vpermpd",        { XM, EXx, Ib }, 0 },
11551   },
11552   {
11553     /* VEX_W_0F3A02_P_2 */
11554     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11555   },
11556   {
11557     /* VEX_W_0F3A04_P_2 */
11558     { "vpermilps",      { XM, EXx, Ib }, 0 },
11559   },
11560   {
11561     /* VEX_W_0F3A05_P_2 */
11562     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11563   },
11564   {
11565     /* VEX_W_0F3A06_P_2 */
11566     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11567   },
11568   {
11569     /* VEX_W_0F3A08_P_2 */
11570     { "vroundps",       { XM, EXx, Ib }, 0 },
11571   },
11572   {
11573     /* VEX_W_0F3A09_P_2 */
11574     { "vroundpd",       { XM, EXx, Ib }, 0 },
11575   },
11576   {
11577     /* VEX_W_0F3A0A_P_2 */
11578     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11579   },
11580   {
11581     /* VEX_W_0F3A0B_P_2 */
11582     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11583   },
11584   {
11585     /* VEX_W_0F3A0C_P_2 */
11586     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11587   },
11588   {
11589     /* VEX_W_0F3A0D_P_2 */
11590     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11591   },
11592   {
11593     /* VEX_W_0F3A0E_P_2 */
11594     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11595   },
11596   {
11597     /* VEX_W_0F3A0F_P_2 */
11598     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11599   },
11600   {
11601     /* VEX_W_0F3A14_P_2 */
11602     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11603   },
11604   {
11605     /* VEX_W_0F3A15_P_2 */
11606     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11607   },
11608   {
11609     /* VEX_W_0F3A18_P_2 */
11610     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11611   },
11612   {
11613     /* VEX_W_0F3A19_P_2 */
11614     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11615   },
11616   {
11617     /* VEX_W_0F3A20_P_2 */
11618     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11619   },
11620   {
11621     /* VEX_W_0F3A21_P_2 */
11622     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11623   },
11624   {
11625     /* VEX_W_0F3A30_P_2_LEN_0 */
11626     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11627     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11628   },
11629   {
11630     /* VEX_W_0F3A31_P_2_LEN_0 */
11631     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11632     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11633   },
11634   {
11635     /* VEX_W_0F3A32_P_2_LEN_0 */
11636     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11637     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11638   },
11639   {
11640     /* VEX_W_0F3A33_P_2_LEN_0 */
11641     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11642     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11643   },
11644   {
11645     /* VEX_W_0F3A38_P_2 */
11646     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11647   },
11648   {
11649     /* VEX_W_0F3A39_P_2 */
11650     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11651   },
11652   {
11653     /* VEX_W_0F3A40_P_2 */
11654     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11655   },
11656   {
11657     /* VEX_W_0F3A41_P_2 */
11658     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11659   },
11660   {
11661     /* VEX_W_0F3A42_P_2 */
11662     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11663   },
11664   {
11665     /* VEX_W_0F3A44_P_2 */
11666     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11667   },
11668   {
11669     /* VEX_W_0F3A46_P_2 */
11670     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11671   },
11672   {
11673     /* VEX_W_0F3A48_P_2 */
11674     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11675     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11676   },
11677   {
11678     /* VEX_W_0F3A49_P_2 */
11679     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11680     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11681   },
11682   {
11683     /* VEX_W_0F3A4A_P_2 */
11684     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11685   },
11686   {
11687     /* VEX_W_0F3A4B_P_2 */
11688     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11689   },
11690   {
11691     /* VEX_W_0F3A4C_P_2 */
11692     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11693   },
11694   {
11695     /* VEX_W_0F3A60_P_2 */
11696     { "vpcmpestrm",     { XM, EXx, Ib }, 0 },
11697   },
11698   {
11699     /* VEX_W_0F3A61_P_2 */
11700     { "vpcmpestri",     { XM, EXx, Ib }, 0 },
11701   },
11702   {
11703     /* VEX_W_0F3A62_P_2 */
11704     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11705   },
11706   {
11707     /* VEX_W_0F3A63_P_2 */
11708     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11709   },
11710   {
11711     /* VEX_W_0F3ADF_P_2 */
11712     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11713   },
11714 #define NEED_VEX_W_TABLE
11715 #include "i386-dis-evex.h"
11716 #undef NEED_VEX_W_TABLE
11717 };
11718
11719 static const struct dis386 mod_table[][2] = {
11720   {
11721     /* MOD_8D */
11722     { "leaS",           { Gv, M }, 0 },
11723   },
11724   {
11725     /* MOD_C6_REG_7 */
11726     { Bad_Opcode },
11727     { RM_TABLE (RM_C6_REG_7) },
11728   },
11729   {
11730     /* MOD_C7_REG_7 */
11731     { Bad_Opcode },
11732     { RM_TABLE (RM_C7_REG_7) },
11733   },
11734   {
11735     /* MOD_FF_REG_3 */
11736     { "Jcall^", { indirEp }, 0 },
11737   },
11738   {
11739     /* MOD_FF_REG_5 */
11740     { "Jjmp^", { indirEp }, 0 },
11741   },
11742   {
11743     /* MOD_0F01_REG_0 */
11744     { X86_64_TABLE (X86_64_0F01_REG_0) },
11745     { RM_TABLE (RM_0F01_REG_0) },
11746   },
11747   {
11748     /* MOD_0F01_REG_1 */
11749     { X86_64_TABLE (X86_64_0F01_REG_1) },
11750     { RM_TABLE (RM_0F01_REG_1) },
11751   },
11752   {
11753     /* MOD_0F01_REG_2 */
11754     { X86_64_TABLE (X86_64_0F01_REG_2) },
11755     { RM_TABLE (RM_0F01_REG_2) },
11756   },
11757   {
11758     /* MOD_0F01_REG_3 */
11759     { X86_64_TABLE (X86_64_0F01_REG_3) },
11760     { RM_TABLE (RM_0F01_REG_3) },
11761   },
11762   {
11763     /* MOD_0F01_REG_5 */
11764     { Bad_Opcode },
11765     { RM_TABLE (RM_0F01_REG_5) },
11766   },
11767   {
11768     /* MOD_0F01_REG_7 */
11769     { "invlpg",         { Mb }, 0 },
11770     { RM_TABLE (RM_0F01_REG_7) },
11771   },
11772   {
11773     /* MOD_0F12_PREFIX_0 */
11774     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11775     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11776   },
11777   {
11778     /* MOD_0F13 */
11779     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11780   },
11781   {
11782     /* MOD_0F16_PREFIX_0 */
11783     { "movhps",         { XM, EXq }, 0 },
11784     { "movlhps",        { XM, EXq }, 0 },
11785   },
11786   {
11787     /* MOD_0F17 */
11788     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11789   },
11790   {
11791     /* MOD_0F18_REG_0 */
11792     { "prefetchnta",    { Mb }, 0 },
11793   },
11794   {
11795     /* MOD_0F18_REG_1 */
11796     { "prefetcht0",     { Mb }, 0 },
11797   },
11798   {
11799     /* MOD_0F18_REG_2 */
11800     { "prefetcht1",     { Mb }, 0 },
11801   },
11802   {
11803     /* MOD_0F18_REG_3 */
11804     { "prefetcht2",     { Mb }, 0 },
11805   },
11806   {
11807     /* MOD_0F18_REG_4 */
11808     { "nop/reserved",   { Mb }, 0 },
11809   },
11810   {
11811     /* MOD_0F18_REG_5 */
11812     { "nop/reserved",   { Mb }, 0 },
11813   },
11814   {
11815     /* MOD_0F18_REG_6 */
11816     { "nop/reserved",   { Mb }, 0 },
11817   },
11818   {
11819     /* MOD_0F18_REG_7 */
11820     { "nop/reserved",   { Mb }, 0 },
11821   },
11822   {
11823     /* MOD_0F1A_PREFIX_0 */
11824     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11825     { "nopQ",           { Ev }, 0 },
11826   },
11827   {
11828     /* MOD_0F1B_PREFIX_0 */
11829     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11830     { "nopQ",           { Ev }, 0 },
11831   },
11832   {
11833     /* MOD_0F1B_PREFIX_1 */
11834     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11835     { "nopQ",           { Ev }, 0 },
11836   },
11837   {
11838     /* MOD_0F24 */
11839     { Bad_Opcode },
11840     { "movL",           { Rd, Td }, 0 },
11841   },
11842   {
11843     /* MOD_0F26 */
11844     { Bad_Opcode },
11845     { "movL",           { Td, Rd }, 0 },
11846   },
11847   {
11848     /* MOD_0F2B_PREFIX_0 */
11849     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11850   },
11851   {
11852     /* MOD_0F2B_PREFIX_1 */
11853     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11854   },
11855   {
11856     /* MOD_0F2B_PREFIX_2 */
11857     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11858   },
11859   {
11860     /* MOD_0F2B_PREFIX_3 */
11861     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11862   },
11863   {
11864     /* MOD_0F51 */
11865     { Bad_Opcode },
11866     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11867   },
11868   {
11869     /* MOD_0F71_REG_2 */
11870     { Bad_Opcode },
11871     { "psrlw",          { MS, Ib }, 0 },
11872   },
11873   {
11874     /* MOD_0F71_REG_4 */
11875     { Bad_Opcode },
11876     { "psraw",          { MS, Ib }, 0 },
11877   },
11878   {
11879     /* MOD_0F71_REG_6 */
11880     { Bad_Opcode },
11881     { "psllw",          { MS, Ib }, 0 },
11882   },
11883   {
11884     /* MOD_0F72_REG_2 */
11885     { Bad_Opcode },
11886     { "psrld",          { MS, Ib }, 0 },
11887   },
11888   {
11889     /* MOD_0F72_REG_4 */
11890     { Bad_Opcode },
11891     { "psrad",          { MS, Ib }, 0 },
11892   },
11893   {
11894     /* MOD_0F72_REG_6 */
11895     { Bad_Opcode },
11896     { "pslld",          { MS, Ib }, 0 },
11897   },
11898   {
11899     /* MOD_0F73_REG_2 */
11900     { Bad_Opcode },
11901     { "psrlq",          { MS, Ib }, 0 },
11902   },
11903   {
11904     /* MOD_0F73_REG_3 */
11905     { Bad_Opcode },
11906     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11907   },
11908   {
11909     /* MOD_0F73_REG_6 */
11910     { Bad_Opcode },
11911     { "psllq",          { MS, Ib }, 0 },
11912   },
11913   {
11914     /* MOD_0F73_REG_7 */
11915     { Bad_Opcode },
11916     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11917   },
11918   {
11919     /* MOD_0FAE_REG_0 */
11920     { "fxsave",         { FXSAVE }, 0 },
11921     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11922   },
11923   {
11924     /* MOD_0FAE_REG_1 */
11925     { "fxrstor",        { FXSAVE }, 0 },
11926     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11927   },
11928   {
11929     /* MOD_0FAE_REG_2 */
11930     { "ldmxcsr",        { Md }, 0 },
11931     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11932   },
11933   {
11934     /* MOD_0FAE_REG_3 */
11935     { "stmxcsr",        { Md }, 0 },
11936     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11937   },
11938   {
11939     /* MOD_0FAE_REG_4 */
11940     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11941     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11942   },
11943   {
11944     /* MOD_0FAE_REG_5 */
11945     { "xrstor",         { FXSAVE }, 0 },
11946     { RM_TABLE (RM_0FAE_REG_5) },
11947   },
11948   {
11949     /* MOD_0FAE_REG_6 */
11950     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11951     { RM_TABLE (RM_0FAE_REG_6) },
11952   },
11953   {
11954     /* MOD_0FAE_REG_7 */
11955     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11956     { RM_TABLE (RM_0FAE_REG_7) },
11957   },
11958   {
11959     /* MOD_0FB2 */
11960     { "lssS",           { Gv, Mp }, 0 },
11961   },
11962   {
11963     /* MOD_0FB4 */
11964     { "lfsS",           { Gv, Mp }, 0 },
11965   },
11966   {
11967     /* MOD_0FB5 */
11968     { "lgsS",           { Gv, Mp }, 0 },
11969   },
11970   {
11971     /* MOD_0FC3 */
11972     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11973   },
11974   {
11975     /* MOD_0FC7_REG_3 */
11976     { "xrstors",        { FXSAVE }, 0 },
11977   },
11978   {
11979     /* MOD_0FC7_REG_4 */
11980     { "xsavec",         { FXSAVE }, 0 },
11981   },
11982   {
11983     /* MOD_0FC7_REG_5 */
11984     { "xsaves",         { FXSAVE }, 0 },
11985   },
11986   {
11987     /* MOD_0FC7_REG_6 */
11988     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11989     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11990   },
11991   {
11992     /* MOD_0FC7_REG_7 */
11993     { "vmptrst",        { Mq }, 0 },
11994     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11995   },
11996   {
11997     /* MOD_0FD7 */
11998     { Bad_Opcode },
11999     { "pmovmskb",       { Gdq, MS }, 0 },
12000   },
12001   {
12002     /* MOD_0FE7_PREFIX_2 */
12003     { "movntdq",        { Mx, XM }, 0 },
12004   },
12005   {
12006     /* MOD_0FF0_PREFIX_3 */
12007     { "lddqu",          { XM, M }, 0 },
12008   },
12009   {
12010     /* MOD_0F382A_PREFIX_2 */
12011     { "movntdqa",       { XM, Mx }, 0 },
12012   },
12013   {
12014     /* MOD_62_32BIT */
12015     { "bound{S|}",      { Gv, Ma }, 0 },
12016     { EVEX_TABLE (EVEX_0F) },
12017   },
12018   {
12019     /* MOD_C4_32BIT */
12020     { "lesS",           { Gv, Mp }, 0 },
12021     { VEX_C4_TABLE (VEX_0F) },
12022   },
12023   {
12024     /* MOD_C5_32BIT */
12025     { "ldsS",           { Gv, Mp }, 0 },
12026     { VEX_C5_TABLE (VEX_0F) },
12027   },
12028   {
12029     /* MOD_VEX_0F12_PREFIX_0 */
12030     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
12031     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
12032   },
12033   {
12034     /* MOD_VEX_0F13 */
12035     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
12036   },
12037   {
12038     /* MOD_VEX_0F16_PREFIX_0 */
12039     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
12040     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
12041   },
12042   {
12043     /* MOD_VEX_0F17 */
12044     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
12045   },
12046   {
12047     /* MOD_VEX_0F2B */
12048     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
12049   },
12050   {
12051     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
12052     { Bad_Opcode },
12053     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
12054   },
12055   {
12056     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
12057     { Bad_Opcode },
12058     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
12059   },
12060   {
12061     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
12062     { Bad_Opcode },
12063     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
12064   },
12065   {
12066     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
12067     { Bad_Opcode },
12068     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
12069   },
12070   {
12071     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
12072     { Bad_Opcode },
12073     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
12074   },
12075   {
12076     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
12077     { Bad_Opcode },
12078     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
12079   },
12080   {
12081     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
12082     { Bad_Opcode },
12083     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
12084   },
12085   {
12086     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
12087     { Bad_Opcode },
12088     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
12089   },
12090   {
12091     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
12092     { Bad_Opcode },
12093     { "knotw",          { MaskG, MaskR }, 0 },
12094   },
12095   {
12096     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
12097     { Bad_Opcode },
12098     { "knotq",          { MaskG, MaskR }, 0 },
12099   },
12100   {
12101     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
12102     { Bad_Opcode },
12103     { "knotb",          { MaskG, MaskR }, 0 },
12104   },
12105   {
12106     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
12107     { Bad_Opcode },
12108     { "knotd",          { MaskG, MaskR }, 0 },
12109   },
12110   {
12111     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
12112     { Bad_Opcode },
12113     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
12114   },
12115   {
12116     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
12117     { Bad_Opcode },
12118     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
12119   },
12120   {
12121     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
12122     { Bad_Opcode },
12123     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
12124   },
12125   {
12126     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
12127     { Bad_Opcode },
12128     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
12129   },
12130  {
12131     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
12132     { Bad_Opcode },
12133     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
12134   },
12135   {
12136     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
12137     { Bad_Opcode },
12138     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
12139   },
12140   {
12141     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
12142     { Bad_Opcode },
12143     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
12144   },
12145   {
12146     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
12147     { Bad_Opcode },
12148     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
12149   },
12150   {
12151     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12152     { Bad_Opcode },
12153     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
12154   },
12155   {
12156     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12157     { Bad_Opcode },
12158     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
12159   },
12160   {
12161     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12162     { Bad_Opcode },
12163     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
12164   },
12165   {
12166     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12167     { Bad_Opcode },
12168     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
12169   },
12170   {
12171     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12172     { Bad_Opcode },
12173     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
12174   },
12175   {
12176     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12177     { Bad_Opcode },
12178     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
12179   },
12180   {
12181     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12182     { Bad_Opcode },
12183     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
12184   },
12185   {
12186     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12187     { Bad_Opcode },
12188     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
12189   },
12190   {
12191     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12192     { Bad_Opcode },
12193     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
12194   },
12195   {
12196     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12197     { Bad_Opcode },
12198     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
12199   },
12200   {
12201     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12202     { Bad_Opcode },
12203     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
12204   },
12205   {
12206     /* MOD_VEX_0F50 */
12207     { Bad_Opcode },
12208     { VEX_W_TABLE (VEX_W_0F50_M_0) },
12209   },
12210   {
12211     /* MOD_VEX_0F71_REG_2 */
12212     { Bad_Opcode },
12213     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
12214   },
12215   {
12216     /* MOD_VEX_0F71_REG_4 */
12217     { Bad_Opcode },
12218     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12219   },
12220   {
12221     /* MOD_VEX_0F71_REG_6 */
12222     { Bad_Opcode },
12223     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12224   },
12225   {
12226     /* MOD_VEX_0F72_REG_2 */
12227     { Bad_Opcode },
12228     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12229   },
12230   {
12231     /* MOD_VEX_0F72_REG_4 */
12232     { Bad_Opcode },
12233     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12234   },
12235   {
12236     /* MOD_VEX_0F72_REG_6 */
12237     { Bad_Opcode },
12238     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12239   },
12240   {
12241     /* MOD_VEX_0F73_REG_2 */
12242     { Bad_Opcode },
12243     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12244   },
12245   {
12246     /* MOD_VEX_0F73_REG_3 */
12247     { Bad_Opcode },
12248     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12249   },
12250   {
12251     /* MOD_VEX_0F73_REG_6 */
12252     { Bad_Opcode },
12253     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12254   },
12255   {
12256     /* MOD_VEX_0F73_REG_7 */
12257     { Bad_Opcode },
12258     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12259   },
12260   {
12261     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12262     { "kmovw",          { Ew, MaskG }, 0 },
12263     { Bad_Opcode },
12264   },
12265   {
12266     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12267     { "kmovq",          { Eq, MaskG }, 0 },
12268     { Bad_Opcode },
12269   },
12270   {
12271     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12272     { "kmovb",          { Eb, MaskG }, 0 },
12273     { Bad_Opcode },
12274   },
12275   {
12276     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12277     { "kmovd",          { Ed, MaskG }, 0 },
12278     { Bad_Opcode },
12279   },
12280   {
12281     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12282     { Bad_Opcode },
12283     { "kmovw",          { MaskG, Rdq }, 0 },
12284   },
12285   {
12286     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12287     { Bad_Opcode },
12288     { "kmovb",          { MaskG, Rdq }, 0 },
12289   },
12290   {
12291     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12292     { Bad_Opcode },
12293     { "kmovd",          { MaskG, Rdq }, 0 },
12294   },
12295   {
12296     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12297     { Bad_Opcode },
12298     { "kmovq",          { MaskG, Rdq }, 0 },
12299   },
12300   {
12301     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12302     { Bad_Opcode },
12303     { "kmovw",          { Gdq, MaskR }, 0 },
12304   },
12305   {
12306     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12307     { Bad_Opcode },
12308     { "kmovb",          { Gdq, MaskR }, 0 },
12309   },
12310   {
12311     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12312     { Bad_Opcode },
12313     { "kmovd",          { Gdq, MaskR }, 0 },
12314   },
12315   {
12316     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12317     { Bad_Opcode },
12318     { "kmovq",          { Gdq, MaskR }, 0 },
12319   },
12320   {
12321     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12322     { Bad_Opcode },
12323     { "kortestw", { MaskG, MaskR }, 0 },
12324   },
12325   {
12326     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12327     { Bad_Opcode },
12328     { "kortestq", { MaskG, MaskR }, 0 },
12329   },
12330   {
12331     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12332     { Bad_Opcode },
12333     { "kortestb", { MaskG, MaskR }, 0 },
12334   },
12335   {
12336     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12337     { Bad_Opcode },
12338     { "kortestd", { MaskG, MaskR }, 0 },
12339   },
12340   {
12341     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12342     { Bad_Opcode },
12343     { "ktestw", { MaskG, MaskR }, 0 },
12344   },
12345   {
12346     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12347     { Bad_Opcode },
12348     { "ktestq", { MaskG, MaskR }, 0 },
12349   },
12350   {
12351     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12352     { Bad_Opcode },
12353     { "ktestb", { MaskG, MaskR }, 0 },
12354   },
12355   {
12356     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12357     { Bad_Opcode },
12358     { "ktestd", { MaskG, MaskR }, 0 },
12359   },
12360   {
12361     /* MOD_VEX_0FAE_REG_2 */
12362     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12363   },
12364   {
12365     /* MOD_VEX_0FAE_REG_3 */
12366     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12367   },
12368   {
12369     /* MOD_VEX_0FD7_PREFIX_2 */
12370     { Bad_Opcode },
12371     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12372   },
12373   {
12374     /* MOD_VEX_0FE7_PREFIX_2 */
12375     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12376   },
12377   {
12378     /* MOD_VEX_0FF0_PREFIX_3 */
12379     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12380   },
12381   {
12382     /* MOD_VEX_0F381A_PREFIX_2 */
12383     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12384   },
12385   {
12386     /* MOD_VEX_0F382A_PREFIX_2 */
12387     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12388   },
12389   {
12390     /* MOD_VEX_0F382C_PREFIX_2 */
12391     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12392   },
12393   {
12394     /* MOD_VEX_0F382D_PREFIX_2 */
12395     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12396   },
12397   {
12398     /* MOD_VEX_0F382E_PREFIX_2 */
12399     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12400   },
12401   {
12402     /* MOD_VEX_0F382F_PREFIX_2 */
12403     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12404   },
12405   {
12406     /* MOD_VEX_0F385A_PREFIX_2 */
12407     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12408   },
12409   {
12410     /* MOD_VEX_0F388C_PREFIX_2 */
12411     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12412   },
12413   {
12414     /* MOD_VEX_0F388E_PREFIX_2 */
12415     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12416   },
12417   {
12418     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12419     { Bad_Opcode },
12420     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12421   },
12422   {
12423     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12424     { Bad_Opcode },
12425     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12426   },
12427   {
12428     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12429     { Bad_Opcode },
12430     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12431   },
12432   {
12433     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12434     { Bad_Opcode },
12435     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12436   },
12437   {
12438     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12439     { Bad_Opcode },
12440     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12441   },
12442   {
12443     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12444     { Bad_Opcode },
12445     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12446   },
12447   {
12448     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12449     { Bad_Opcode },
12450     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12451   },
12452   {
12453     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12454     { Bad_Opcode },
12455     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12456   },
12457 #define NEED_MOD_TABLE
12458 #include "i386-dis-evex.h"
12459 #undef NEED_MOD_TABLE
12460 };
12461
12462 static const struct dis386 rm_table[][8] = {
12463   {
12464     /* RM_C6_REG_7 */
12465     { "xabort",         { Skip_MODRM, Ib }, 0 },
12466   },
12467   {
12468     /* RM_C7_REG_7 */
12469     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12470   },
12471   {
12472     /* RM_0F01_REG_0 */
12473     { Bad_Opcode },
12474     { "vmcall",         { Skip_MODRM }, 0 },
12475     { "vmlaunch",       { Skip_MODRM }, 0 },
12476     { "vmresume",       { Skip_MODRM }, 0 },
12477     { "vmxoff",         { Skip_MODRM }, 0 },
12478   },
12479   {
12480     /* RM_0F01_REG_1 */
12481     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12482     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12483     { "clac",           { Skip_MODRM }, 0 },
12484     { "stac",           { Skip_MODRM }, 0 },
12485     { Bad_Opcode },
12486     { Bad_Opcode },
12487     { Bad_Opcode },
12488     { "encls",          { Skip_MODRM }, 0 },
12489   },
12490   {
12491     /* RM_0F01_REG_2 */
12492     { "xgetbv",         { Skip_MODRM }, 0 },
12493     { "xsetbv",         { Skip_MODRM }, 0 },
12494     { Bad_Opcode },
12495     { Bad_Opcode },
12496     { "vmfunc",         { Skip_MODRM }, 0 },
12497     { "xend",           { Skip_MODRM }, 0 },
12498     { "xtest",          { Skip_MODRM }, 0 },
12499     { "enclu",          { Skip_MODRM }, 0 },
12500   },
12501   {
12502     /* RM_0F01_REG_3 */
12503     { "vmrun",          { Skip_MODRM }, 0 },
12504     { "vmmcall",        { Skip_MODRM }, 0 },
12505     { "vmload",         { Skip_MODRM }, 0 },
12506     { "vmsave",         { Skip_MODRM }, 0 },
12507     { "stgi",           { Skip_MODRM }, 0 },
12508     { "clgi",           { Skip_MODRM }, 0 },
12509     { "skinit",         { Skip_MODRM }, 0 },
12510     { "invlpga",        { Skip_MODRM }, 0 },
12511   },
12512   {
12513     /* RM_0F01_REG_5 */
12514     { Bad_Opcode },
12515     { Bad_Opcode },
12516     { Bad_Opcode },
12517     { Bad_Opcode },
12518     { Bad_Opcode },
12519     { Bad_Opcode },
12520     { "rdpkru",         { Skip_MODRM }, 0 },
12521     { "wrpkru",         { Skip_MODRM }, 0 },
12522   },
12523   {
12524     /* RM_0F01_REG_7 */
12525     { "swapgs",         { Skip_MODRM }, 0  },
12526     { "rdtscp",         { Skip_MODRM }, 0  },
12527     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12528     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12529     { "clzero",         { Skip_MODRM }, 0  },
12530   },
12531   {
12532     /* RM_0FAE_REG_5 */
12533     { "lfence",         { Skip_MODRM }, 0 },
12534   },
12535   {
12536     /* RM_0FAE_REG_6 */
12537     { "mfence",         { Skip_MODRM }, 0 },
12538   },
12539   {
12540     /* RM_0FAE_REG_7 */
12541     { "sfence",         { Skip_MODRM }, 0 },
12542
12543   },
12544 };
12545
12546 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12547
12548 /* We use the high bit to indicate different name for the same
12549    prefix.  */
12550 #define REP_PREFIX      (0xf3 | 0x100)
12551 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12552 #define XRELEASE_PREFIX (0xf3 | 0x400)
12553 #define BND_PREFIX      (0xf2 | 0x400)
12554
12555 static int
12556 ckprefix (void)
12557 {
12558   int newrex, i, length;
12559   rex = 0;
12560   rex_ignored = 0;
12561   prefixes = 0;
12562   used_prefixes = 0;
12563   rex_used = 0;
12564   last_lock_prefix = -1;
12565   last_repz_prefix = -1;
12566   last_repnz_prefix = -1;
12567   last_data_prefix = -1;
12568   last_addr_prefix = -1;
12569   last_rex_prefix = -1;
12570   last_seg_prefix = -1;
12571   fwait_prefix = -1;
12572   active_seg_prefix = 0;
12573   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12574     all_prefixes[i] = 0;
12575   i = 0;
12576   length = 0;
12577   /* The maximum instruction length is 15bytes.  */
12578   while (length < MAX_CODE_LENGTH - 1)
12579     {
12580       FETCH_DATA (the_info, codep + 1);
12581       newrex = 0;
12582       switch (*codep)
12583         {
12584         /* REX prefixes family.  */
12585         case 0x40:
12586         case 0x41:
12587         case 0x42:
12588         case 0x43:
12589         case 0x44:
12590         case 0x45:
12591         case 0x46:
12592         case 0x47:
12593         case 0x48:
12594         case 0x49:
12595         case 0x4a:
12596         case 0x4b:
12597         case 0x4c:
12598         case 0x4d:
12599         case 0x4e:
12600         case 0x4f:
12601           if (address_mode == mode_64bit)
12602             newrex = *codep;
12603           else
12604             return 1;
12605           last_rex_prefix = i;
12606           break;
12607         case 0xf3:
12608           prefixes |= PREFIX_REPZ;
12609           last_repz_prefix = i;
12610           break;
12611         case 0xf2:
12612           prefixes |= PREFIX_REPNZ;
12613           last_repnz_prefix = i;
12614           break;
12615         case 0xf0:
12616           prefixes |= PREFIX_LOCK;
12617           last_lock_prefix = i;
12618           break;
12619         case 0x2e:
12620           prefixes |= PREFIX_CS;
12621           last_seg_prefix = i;
12622           active_seg_prefix = PREFIX_CS;
12623           break;
12624         case 0x36:
12625           prefixes |= PREFIX_SS;
12626           last_seg_prefix = i;
12627           active_seg_prefix = PREFIX_SS;
12628           break;
12629         case 0x3e:
12630           prefixes |= PREFIX_DS;
12631           last_seg_prefix = i;
12632           active_seg_prefix = PREFIX_DS;
12633           break;
12634         case 0x26:
12635           prefixes |= PREFIX_ES;
12636           last_seg_prefix = i;
12637           active_seg_prefix = PREFIX_ES;
12638           break;
12639         case 0x64:
12640           prefixes |= PREFIX_FS;
12641           last_seg_prefix = i;
12642           active_seg_prefix = PREFIX_FS;
12643           break;
12644         case 0x65:
12645           prefixes |= PREFIX_GS;
12646           last_seg_prefix = i;
12647           active_seg_prefix = PREFIX_GS;
12648           break;
12649         case 0x66:
12650           prefixes |= PREFIX_DATA;
12651           last_data_prefix = i;
12652           break;
12653         case 0x67:
12654           prefixes |= PREFIX_ADDR;
12655           last_addr_prefix = i;
12656           break;
12657         case FWAIT_OPCODE:
12658           /* fwait is really an instruction.  If there are prefixes
12659              before the fwait, they belong to the fwait, *not* to the
12660              following instruction.  */
12661           fwait_prefix = i;
12662           if (prefixes || rex)
12663             {
12664               prefixes |= PREFIX_FWAIT;
12665               codep++;
12666               /* This ensures that the previous REX prefixes are noticed
12667                  as unused prefixes, as in the return case below.  */
12668               rex_used = rex;
12669               return 1;
12670             }
12671           prefixes = PREFIX_FWAIT;
12672           break;
12673         default:
12674           return 1;
12675         }
12676       /* Rex is ignored when followed by another prefix.  */
12677       if (rex)
12678         {
12679           rex_used = rex;
12680           return 1;
12681         }
12682       if (*codep != FWAIT_OPCODE)
12683         all_prefixes[i++] = *codep;
12684       rex = newrex;
12685       codep++;
12686       length++;
12687     }
12688   return 0;
12689 }
12690
12691 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12692    prefix byte.  */
12693
12694 static const char *
12695 prefix_name (int pref, int sizeflag)
12696 {
12697   static const char *rexes [16] =
12698     {
12699       "rex",            /* 0x40 */
12700       "rex.B",          /* 0x41 */
12701       "rex.X",          /* 0x42 */
12702       "rex.XB",         /* 0x43 */
12703       "rex.R",          /* 0x44 */
12704       "rex.RB",         /* 0x45 */
12705       "rex.RX",         /* 0x46 */
12706       "rex.RXB",        /* 0x47 */
12707       "rex.W",          /* 0x48 */
12708       "rex.WB",         /* 0x49 */
12709       "rex.WX",         /* 0x4a */
12710       "rex.WXB",        /* 0x4b */
12711       "rex.WR",         /* 0x4c */
12712       "rex.WRB",        /* 0x4d */
12713       "rex.WRX",        /* 0x4e */
12714       "rex.WRXB",       /* 0x4f */
12715     };
12716
12717   switch (pref)
12718     {
12719     /* REX prefixes family.  */
12720     case 0x40:
12721     case 0x41:
12722     case 0x42:
12723     case 0x43:
12724     case 0x44:
12725     case 0x45:
12726     case 0x46:
12727     case 0x47:
12728     case 0x48:
12729     case 0x49:
12730     case 0x4a:
12731     case 0x4b:
12732     case 0x4c:
12733     case 0x4d:
12734     case 0x4e:
12735     case 0x4f:
12736       return rexes [pref - 0x40];
12737     case 0xf3:
12738       return "repz";
12739     case 0xf2:
12740       return "repnz";
12741     case 0xf0:
12742       return "lock";
12743     case 0x2e:
12744       return "cs";
12745     case 0x36:
12746       return "ss";
12747     case 0x3e:
12748       return "ds";
12749     case 0x26:
12750       return "es";
12751     case 0x64:
12752       return "fs";
12753     case 0x65:
12754       return "gs";
12755     case 0x66:
12756       return (sizeflag & DFLAG) ? "data16" : "data32";
12757     case 0x67:
12758       if (address_mode == mode_64bit)
12759         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12760       else
12761         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12762     case FWAIT_OPCODE:
12763       return "fwait";
12764     case REP_PREFIX:
12765       return "rep";
12766     case XACQUIRE_PREFIX:
12767       return "xacquire";
12768     case XRELEASE_PREFIX:
12769       return "xrelease";
12770     case BND_PREFIX:
12771       return "bnd";
12772     default:
12773       return NULL;
12774     }
12775 }
12776
12777 static char op_out[MAX_OPERANDS][100];
12778 static int op_ad, op_index[MAX_OPERANDS];
12779 static int two_source_ops;
12780 static bfd_vma op_address[MAX_OPERANDS];
12781 static bfd_vma op_riprel[MAX_OPERANDS];
12782 static bfd_vma start_pc;
12783
12784 /*
12785  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12786  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12787  *   section of the "Virtual 8086 Mode" chapter.)
12788  * 'pc' should be the address of this instruction, it will
12789  *   be used to print the target address if this is a relative jump or call
12790  * The function returns the length of this instruction in bytes.
12791  */
12792
12793 static char intel_syntax;
12794 static char intel_mnemonic = !SYSV386_COMPAT;
12795 static char open_char;
12796 static char close_char;
12797 static char separator_char;
12798 static char scale_char;
12799
12800 enum x86_64_isa
12801 {
12802   amd64 = 0,
12803   intel64
12804 };
12805
12806 static enum x86_64_isa isa64;
12807
12808 /* Here for backwards compatibility.  When gdb stops using
12809    print_insn_i386_att and print_insn_i386_intel these functions can
12810    disappear, and print_insn_i386 be merged into print_insn.  */
12811 int
12812 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12813 {
12814   intel_syntax = 0;
12815
12816   return print_insn (pc, info);
12817 }
12818
12819 int
12820 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12821 {
12822   intel_syntax = 1;
12823
12824   return print_insn (pc, info);
12825 }
12826
12827 int
12828 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12829 {
12830   intel_syntax = -1;
12831
12832   return print_insn (pc, info);
12833 }
12834
12835 void
12836 print_i386_disassembler_options (FILE *stream)
12837 {
12838   fprintf (stream, _("\n\
12839 The following i386/x86-64 specific disassembler options are supported for use\n\
12840 with the -M switch (multiple options should be separated by commas):\n"));
12841
12842   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12843   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12844   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12845   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12846   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12847   fprintf (stream, _("  att-mnemonic\n"
12848                      "              Display instruction in AT&T mnemonic\n"));
12849   fprintf (stream, _("  intel-mnemonic\n"
12850                      "              Display instruction in Intel mnemonic\n"));
12851   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12852   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12853   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12854   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12855   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12856   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12857   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12858   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12859 }
12860
12861 /* Bad opcode.  */
12862 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12863
12864 /* Get a pointer to struct dis386 with a valid name.  */
12865
12866 static const struct dis386 *
12867 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12868 {
12869   int vindex, vex_table_index;
12870
12871   if (dp->name != NULL)
12872     return dp;
12873
12874   switch (dp->op[0].bytemode)
12875     {
12876     case USE_REG_TABLE:
12877       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12878       break;
12879
12880     case USE_MOD_TABLE:
12881       vindex = modrm.mod == 0x3 ? 1 : 0;
12882       dp = &mod_table[dp->op[1].bytemode][vindex];
12883       break;
12884
12885     case USE_RM_TABLE:
12886       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12887       break;
12888
12889     case USE_PREFIX_TABLE:
12890       if (need_vex)
12891         {
12892           /* The prefix in VEX is implicit.  */
12893           switch (vex.prefix)
12894             {
12895             case 0:
12896               vindex = 0;
12897               break;
12898             case REPE_PREFIX_OPCODE:
12899               vindex = 1;
12900               break;
12901             case DATA_PREFIX_OPCODE:
12902               vindex = 2;
12903               break;
12904             case REPNE_PREFIX_OPCODE:
12905               vindex = 3;
12906               break;
12907             default:
12908               abort ();
12909               break;
12910             }
12911         }
12912       else
12913         {
12914           int last_prefix = -1;
12915           int prefix = 0;
12916           vindex = 0;
12917           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12918              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12919              last one wins.  */
12920           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12921             {
12922               if (last_repz_prefix > last_repnz_prefix)
12923                 {
12924                   vindex = 1;
12925                   prefix = PREFIX_REPZ;
12926                   last_prefix = last_repz_prefix;
12927                 }
12928               else
12929                 {
12930                   vindex = 3;
12931                   prefix = PREFIX_REPNZ;
12932                   last_prefix = last_repnz_prefix;
12933                 }
12934
12935               /* Check if prefix should be ignored.  */
12936               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12937                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12938                    & prefix) != 0)
12939                 vindex = 0;
12940             }
12941
12942           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12943             {
12944               vindex = 2;
12945               prefix = PREFIX_DATA;
12946               last_prefix = last_data_prefix;
12947             }
12948
12949           if (vindex != 0)
12950             {
12951               used_prefixes |= prefix;
12952               all_prefixes[last_prefix] = 0;
12953             }
12954         }
12955       dp = &prefix_table[dp->op[1].bytemode][vindex];
12956       break;
12957
12958     case USE_X86_64_TABLE:
12959       vindex = address_mode == mode_64bit ? 1 : 0;
12960       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12961       break;
12962
12963     case USE_3BYTE_TABLE:
12964       FETCH_DATA (info, codep + 2);
12965       vindex = *codep++;
12966       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12967       end_codep = codep;
12968       modrm.mod = (*codep >> 6) & 3;
12969       modrm.reg = (*codep >> 3) & 7;
12970       modrm.rm = *codep & 7;
12971       break;
12972
12973     case USE_VEX_LEN_TABLE:
12974       if (!need_vex)
12975         abort ();
12976
12977       switch (vex.length)
12978         {
12979         case 128:
12980           vindex = 0;
12981           break;
12982         case 256:
12983           vindex = 1;
12984           break;
12985         default:
12986           abort ();
12987           break;
12988         }
12989
12990       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12991       break;
12992
12993     case USE_XOP_8F_TABLE:
12994       FETCH_DATA (info, codep + 3);
12995       /* All bits in the REX prefix are ignored.  */
12996       rex_ignored = rex;
12997       rex = ~(*codep >> 5) & 0x7;
12998
12999       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
13000       switch ((*codep & 0x1f))
13001         {
13002         default:
13003           dp = &bad_opcode;
13004           return dp;
13005         case 0x8:
13006           vex_table_index = XOP_08;
13007           break;
13008         case 0x9:
13009           vex_table_index = XOP_09;
13010           break;
13011         case 0xa:
13012           vex_table_index = XOP_0A;
13013           break;
13014         }
13015       codep++;
13016       vex.w = *codep & 0x80;
13017       if (vex.w && address_mode == mode_64bit)
13018         rex |= REX_W;
13019
13020       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13021       if (address_mode != mode_64bit
13022           && vex.register_specifier > 0x7)
13023         {
13024           dp = &bad_opcode;
13025           return dp;
13026         }
13027
13028       vex.length = (*codep & 0x4) ? 256 : 128;
13029       switch ((*codep & 0x3))
13030         {
13031         case 0:
13032           vex.prefix = 0;
13033           break;
13034         case 1:
13035           vex.prefix = DATA_PREFIX_OPCODE;
13036           break;
13037         case 2:
13038           vex.prefix = REPE_PREFIX_OPCODE;
13039           break;
13040         case 3:
13041           vex.prefix = REPNE_PREFIX_OPCODE;
13042           break;
13043         }
13044       need_vex = 1;
13045       need_vex_reg = 1;
13046       codep++;
13047       vindex = *codep++;
13048       dp = &xop_table[vex_table_index][vindex];
13049
13050       end_codep = codep;
13051       FETCH_DATA (info, codep + 1);
13052       modrm.mod = (*codep >> 6) & 3;
13053       modrm.reg = (*codep >> 3) & 7;
13054       modrm.rm = *codep & 7;
13055       break;
13056
13057     case USE_VEX_C4_TABLE:
13058       /* VEX prefix.  */
13059       FETCH_DATA (info, codep + 3);
13060       /* All bits in the REX prefix are ignored.  */
13061       rex_ignored = rex;
13062       rex = ~(*codep >> 5) & 0x7;
13063       switch ((*codep & 0x1f))
13064         {
13065         default:
13066           dp = &bad_opcode;
13067           return dp;
13068         case 0x1:
13069           vex_table_index = VEX_0F;
13070           break;
13071         case 0x2:
13072           vex_table_index = VEX_0F38;
13073           break;
13074         case 0x3:
13075           vex_table_index = VEX_0F3A;
13076           break;
13077         }
13078       codep++;
13079       vex.w = *codep & 0x80;
13080       if (address_mode == mode_64bit)
13081         {
13082           if (vex.w)
13083             rex |= REX_W;
13084           vex.register_specifier = (~(*codep >> 3)) & 0xf;
13085         }
13086       else
13087         {
13088           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
13089              is ignored, other REX bits are 0 and the highest bit in
13090              VEX.vvvv is also ignored.  */
13091           rex = 0;
13092           vex.register_specifier = (~(*codep >> 3)) & 0x7;
13093         }
13094       vex.length = (*codep & 0x4) ? 256 : 128;
13095       switch ((*codep & 0x3))
13096         {
13097         case 0:
13098           vex.prefix = 0;
13099           break;
13100         case 1:
13101           vex.prefix = DATA_PREFIX_OPCODE;
13102           break;
13103         case 2:
13104           vex.prefix = REPE_PREFIX_OPCODE;
13105           break;
13106         case 3:
13107           vex.prefix = REPNE_PREFIX_OPCODE;
13108           break;
13109         }
13110       need_vex = 1;
13111       need_vex_reg = 1;
13112       codep++;
13113       vindex = *codep++;
13114       dp = &vex_table[vex_table_index][vindex];
13115       end_codep = codep;
13116       /* There is no MODRM byte for VEX [82|77].  */
13117       if (vindex != 0x77 && vindex != 0x82)
13118         {
13119           FETCH_DATA (info, codep + 1);
13120           modrm.mod = (*codep >> 6) & 3;
13121           modrm.reg = (*codep >> 3) & 7;
13122           modrm.rm = *codep & 7;
13123         }
13124       break;
13125
13126     case USE_VEX_C5_TABLE:
13127       /* VEX prefix.  */
13128       FETCH_DATA (info, codep + 2);
13129       /* All bits in the REX prefix are ignored.  */
13130       rex_ignored = rex;
13131       rex = (*codep & 0x80) ? 0 : REX_R;
13132
13133       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
13134          VEX.vvvv is 1.  */
13135       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13136       vex.w = 0;
13137       vex.length = (*codep & 0x4) ? 256 : 128;
13138       switch ((*codep & 0x3))
13139         {
13140         case 0:
13141           vex.prefix = 0;
13142           break;
13143         case 1:
13144           vex.prefix = DATA_PREFIX_OPCODE;
13145           break;
13146         case 2:
13147           vex.prefix = REPE_PREFIX_OPCODE;
13148           break;
13149         case 3:
13150           vex.prefix = REPNE_PREFIX_OPCODE;
13151           break;
13152         }
13153       need_vex = 1;
13154       need_vex_reg = 1;
13155       codep++;
13156       vindex = *codep++;
13157       dp = &vex_table[dp->op[1].bytemode][vindex];
13158       end_codep = codep;
13159       /* There is no MODRM byte for VEX [82|77].  */
13160       if (vindex != 0x77 && vindex != 0x82)
13161         {
13162           FETCH_DATA (info, codep + 1);
13163           modrm.mod = (*codep >> 6) & 3;
13164           modrm.reg = (*codep >> 3) & 7;
13165           modrm.rm = *codep & 7;
13166         }
13167       break;
13168
13169     case USE_VEX_W_TABLE:
13170       if (!need_vex)
13171         abort ();
13172
13173       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
13174       break;
13175
13176     case USE_EVEX_TABLE:
13177       two_source_ops = 0;
13178       /* EVEX prefix.  */
13179       vex.evex = 1;
13180       FETCH_DATA (info, codep + 4);
13181       /* All bits in the REX prefix are ignored.  */
13182       rex_ignored = rex;
13183       /* The first byte after 0x62.  */
13184       rex = ~(*codep >> 5) & 0x7;
13185       vex.r = *codep & 0x10;
13186       switch ((*codep & 0xf))
13187         {
13188         default:
13189           return &bad_opcode;
13190         case 0x1:
13191           vex_table_index = EVEX_0F;
13192           break;
13193         case 0x2:
13194           vex_table_index = EVEX_0F38;
13195           break;
13196         case 0x3:
13197           vex_table_index = EVEX_0F3A;
13198           break;
13199         }
13200
13201       /* The second byte after 0x62.  */
13202       codep++;
13203       vex.w = *codep & 0x80;
13204       if (vex.w && address_mode == mode_64bit)
13205         rex |= REX_W;
13206
13207       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13208       if (address_mode != mode_64bit)
13209         {
13210           /* In 16/32-bit mode silently ignore following bits.  */
13211           rex &= ~REX_B;
13212           vex.r = 1;
13213           vex.v = 1;
13214           vex.register_specifier &= 0x7;
13215         }
13216
13217       /* The U bit.  */
13218       if (!(*codep & 0x4))
13219         return &bad_opcode;
13220
13221       switch ((*codep & 0x3))
13222         {
13223         case 0:
13224           vex.prefix = 0;
13225           break;
13226         case 1:
13227           vex.prefix = DATA_PREFIX_OPCODE;
13228           break;
13229         case 2:
13230           vex.prefix = REPE_PREFIX_OPCODE;
13231           break;
13232         case 3:
13233           vex.prefix = REPNE_PREFIX_OPCODE;
13234           break;
13235         }
13236
13237       /* The third byte after 0x62.  */
13238       codep++;
13239
13240       /* Remember the static rounding bits.  */
13241       vex.ll = (*codep >> 5) & 3;
13242       vex.b = (*codep & 0x10) != 0;
13243
13244       vex.v = *codep & 0x8;
13245       vex.mask_register_specifier = *codep & 0x7;
13246       vex.zeroing = *codep & 0x80;
13247
13248       need_vex = 1;
13249       need_vex_reg = 1;
13250       codep++;
13251       vindex = *codep++;
13252       dp = &evex_table[vex_table_index][vindex];
13253       end_codep = codep;
13254       FETCH_DATA (info, codep + 1);
13255       modrm.mod = (*codep >> 6) & 3;
13256       modrm.reg = (*codep >> 3) & 7;
13257       modrm.rm = *codep & 7;
13258
13259       /* Set vector length.  */
13260       if (modrm.mod == 3 && vex.b)
13261         vex.length = 512;
13262       else
13263         {
13264           switch (vex.ll)
13265             {
13266             case 0x0:
13267               vex.length = 128;
13268               break;
13269             case 0x1:
13270               vex.length = 256;
13271               break;
13272             case 0x2:
13273               vex.length = 512;
13274               break;
13275             default:
13276               return &bad_opcode;
13277             }
13278         }
13279       break;
13280
13281     case 0:
13282       dp = &bad_opcode;
13283       break;
13284
13285     default:
13286       abort ();
13287     }
13288
13289   if (dp->name != NULL)
13290     return dp;
13291   else
13292     return get_valid_dis386 (dp, info);
13293 }
13294
13295 static void
13296 get_sib (disassemble_info *info, int sizeflag)
13297 {
13298   /* If modrm.mod == 3, operand must be register.  */
13299   if (need_modrm
13300       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13301       && modrm.mod != 3
13302       && modrm.rm == 4)
13303     {
13304       FETCH_DATA (info, codep + 2);
13305       sib.index = (codep [1] >> 3) & 7;
13306       sib.scale = (codep [1] >> 6) & 3;
13307       sib.base = codep [1] & 7;
13308     }
13309 }
13310
13311 static int
13312 print_insn (bfd_vma pc, disassemble_info *info)
13313 {
13314   const struct dis386 *dp;
13315   int i;
13316   char *op_txt[MAX_OPERANDS];
13317   int needcomma;
13318   int sizeflag, orig_sizeflag;
13319   const char *p;
13320   struct dis_private priv;
13321   int prefix_length;
13322
13323   priv.orig_sizeflag = AFLAG | DFLAG;
13324   if ((info->mach & bfd_mach_i386_i386) != 0)
13325     address_mode = mode_32bit;
13326   else if (info->mach == bfd_mach_i386_i8086)
13327     {
13328       address_mode = mode_16bit;
13329       priv.orig_sizeflag = 0;
13330     }
13331   else
13332     address_mode = mode_64bit;
13333
13334   if (intel_syntax == (char) -1)
13335     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13336
13337   for (p = info->disassembler_options; p != NULL; )
13338     {
13339       if (CONST_STRNEQ (p, "amd64"))
13340         isa64 = amd64;
13341       else if (CONST_STRNEQ (p, "intel64"))
13342         isa64 = intel64;
13343       else if (CONST_STRNEQ (p, "x86-64"))
13344         {
13345           address_mode = mode_64bit;
13346           priv.orig_sizeflag = AFLAG | DFLAG;
13347         }
13348       else if (CONST_STRNEQ (p, "i386"))
13349         {
13350           address_mode = mode_32bit;
13351           priv.orig_sizeflag = AFLAG | DFLAG;
13352         }
13353       else if (CONST_STRNEQ (p, "i8086"))
13354         {
13355           address_mode = mode_16bit;
13356           priv.orig_sizeflag = 0;
13357         }
13358       else if (CONST_STRNEQ (p, "intel"))
13359         {
13360           intel_syntax = 1;
13361           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13362             intel_mnemonic = 1;
13363         }
13364       else if (CONST_STRNEQ (p, "att"))
13365         {
13366           intel_syntax = 0;
13367           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13368             intel_mnemonic = 0;
13369         }
13370       else if (CONST_STRNEQ (p, "addr"))
13371         {
13372           if (address_mode == mode_64bit)
13373             {
13374               if (p[4] == '3' && p[5] == '2')
13375                 priv.orig_sizeflag &= ~AFLAG;
13376               else if (p[4] == '6' && p[5] == '4')
13377                 priv.orig_sizeflag |= AFLAG;
13378             }
13379           else
13380             {
13381               if (p[4] == '1' && p[5] == '6')
13382                 priv.orig_sizeflag &= ~AFLAG;
13383               else if (p[4] == '3' && p[5] == '2')
13384                 priv.orig_sizeflag |= AFLAG;
13385             }
13386         }
13387       else if (CONST_STRNEQ (p, "data"))
13388         {
13389           if (p[4] == '1' && p[5] == '6')
13390             priv.orig_sizeflag &= ~DFLAG;
13391           else if (p[4] == '3' && p[5] == '2')
13392             priv.orig_sizeflag |= DFLAG;
13393         }
13394       else if (CONST_STRNEQ (p, "suffix"))
13395         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13396
13397       p = strchr (p, ',');
13398       if (p != NULL)
13399         p++;
13400     }
13401
13402   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13403     {
13404       (*info->fprintf_func) (info->stream,
13405                              _("64-bit address is disabled"));
13406       return -1;
13407     }
13408
13409   if (intel_syntax)
13410     {
13411       names64 = intel_names64;
13412       names32 = intel_names32;
13413       names16 = intel_names16;
13414       names8 = intel_names8;
13415       names8rex = intel_names8rex;
13416       names_seg = intel_names_seg;
13417       names_mm = intel_names_mm;
13418       names_bnd = intel_names_bnd;
13419       names_xmm = intel_names_xmm;
13420       names_ymm = intel_names_ymm;
13421       names_zmm = intel_names_zmm;
13422       index64 = intel_index64;
13423       index32 = intel_index32;
13424       names_mask = intel_names_mask;
13425       index16 = intel_index16;
13426       open_char = '[';
13427       close_char = ']';
13428       separator_char = '+';
13429       scale_char = '*';
13430     }
13431   else
13432     {
13433       names64 = att_names64;
13434       names32 = att_names32;
13435       names16 = att_names16;
13436       names8 = att_names8;
13437       names8rex = att_names8rex;
13438       names_seg = att_names_seg;
13439       names_mm = att_names_mm;
13440       names_bnd = att_names_bnd;
13441       names_xmm = att_names_xmm;
13442       names_ymm = att_names_ymm;
13443       names_zmm = att_names_zmm;
13444       index64 = att_index64;
13445       index32 = att_index32;
13446       names_mask = att_names_mask;
13447       index16 = att_index16;
13448       open_char = '(';
13449       close_char =  ')';
13450       separator_char = ',';
13451       scale_char = ',';
13452     }
13453
13454   /* The output looks better if we put 7 bytes on a line, since that
13455      puts most long word instructions on a single line.  Use 8 bytes
13456      for Intel L1OM.  */
13457   if ((info->mach & bfd_mach_l1om) != 0)
13458     info->bytes_per_line = 8;
13459   else
13460     info->bytes_per_line = 7;
13461
13462   info->private_data = &priv;
13463   priv.max_fetched = priv.the_buffer;
13464   priv.insn_start = pc;
13465
13466   obuf[0] = 0;
13467   for (i = 0; i < MAX_OPERANDS; ++i)
13468     {
13469       op_out[i][0] = 0;
13470       op_index[i] = -1;
13471     }
13472
13473   the_info = info;
13474   start_pc = pc;
13475   start_codep = priv.the_buffer;
13476   codep = priv.the_buffer;
13477
13478   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13479     {
13480       const char *name;
13481
13482       /* Getting here means we tried for data but didn't get it.  That
13483          means we have an incomplete instruction of some sort.  Just
13484          print the first byte as a prefix or a .byte pseudo-op.  */
13485       if (codep > priv.the_buffer)
13486         {
13487           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13488           if (name != NULL)
13489             (*info->fprintf_func) (info->stream, "%s", name);
13490           else
13491             {
13492               /* Just print the first byte as a .byte instruction.  */
13493               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13494                                      (unsigned int) priv.the_buffer[0]);
13495             }
13496
13497           return 1;
13498         }
13499
13500       return -1;
13501     }
13502
13503   obufp = obuf;
13504   sizeflag = priv.orig_sizeflag;
13505
13506   if (!ckprefix () || rex_used)
13507     {
13508       /* Too many prefixes or unused REX prefixes.  */
13509       for (i = 0;
13510            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13511            i++)
13512         (*info->fprintf_func) (info->stream, "%s%s",
13513                                i == 0 ? "" : " ",
13514                                prefix_name (all_prefixes[i], sizeflag));
13515       return i;
13516     }
13517
13518   insn_codep = codep;
13519
13520   FETCH_DATA (info, codep + 1);
13521   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13522
13523   if (((prefixes & PREFIX_FWAIT)
13524        && ((*codep < 0xd8) || (*codep > 0xdf))))
13525     {
13526       /* Handle prefixes before fwait.  */
13527       for (i = 0; i < fwait_prefix && all_prefixes[i];
13528            i++)
13529         (*info->fprintf_func) (info->stream, "%s ",
13530                                prefix_name (all_prefixes[i], sizeflag));
13531       (*info->fprintf_func) (info->stream, "fwait");
13532       return i + 1;
13533     }
13534
13535   if (*codep == 0x0f)
13536     {
13537       unsigned char threebyte;
13538
13539       codep++;
13540       FETCH_DATA (info, codep + 1);
13541       threebyte = *codep;
13542       dp = &dis386_twobyte[threebyte];
13543       need_modrm = twobyte_has_modrm[*codep];
13544       codep++;
13545     }
13546   else
13547     {
13548       dp = &dis386[*codep];
13549       need_modrm = onebyte_has_modrm[*codep];
13550       codep++;
13551     }
13552
13553   /* Save sizeflag for printing the extra prefixes later before updating
13554      it for mnemonic and operand processing.  The prefix names depend
13555      only on the address mode.  */
13556   orig_sizeflag = sizeflag;
13557   if (prefixes & PREFIX_ADDR)
13558     sizeflag ^= AFLAG;
13559   if ((prefixes & PREFIX_DATA))
13560     sizeflag ^= DFLAG;
13561
13562   end_codep = codep;
13563   if (need_modrm)
13564     {
13565       FETCH_DATA (info, codep + 1);
13566       modrm.mod = (*codep >> 6) & 3;
13567       modrm.reg = (*codep >> 3) & 7;
13568       modrm.rm = *codep & 7;
13569     }
13570
13571   need_vex = 0;
13572   need_vex_reg = 0;
13573   vex_w_done = 0;
13574   vex.evex = 0;
13575
13576   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13577     {
13578       get_sib (info, sizeflag);
13579       dofloat (sizeflag);
13580     }
13581   else
13582     {
13583       dp = get_valid_dis386 (dp, info);
13584       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13585         {
13586           get_sib (info, sizeflag);
13587           for (i = 0; i < MAX_OPERANDS; ++i)
13588             {
13589               obufp = op_out[i];
13590               op_ad = MAX_OPERANDS - 1 - i;
13591               if (dp->op[i].rtn)
13592                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13593               /* For EVEX instruction after the last operand masking
13594                  should be printed.  */
13595               if (i == 0 && vex.evex)
13596                 {
13597                   /* Don't print {%k0}.  */
13598                   if (vex.mask_register_specifier)
13599                     {
13600                       oappend ("{");
13601                       oappend (names_mask[vex.mask_register_specifier]);
13602                       oappend ("}");
13603                     }
13604                   if (vex.zeroing)
13605                     oappend ("{z}");
13606                 }
13607             }
13608         }
13609     }
13610
13611   /* Check if the REX prefix is used.  */
13612   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13613     all_prefixes[last_rex_prefix] = 0;
13614
13615   /* Check if the SEG prefix is used.  */
13616   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13617                    | PREFIX_FS | PREFIX_GS)) != 0
13618       && (used_prefixes & active_seg_prefix) != 0)
13619     all_prefixes[last_seg_prefix] = 0;
13620
13621   /* Check if the ADDR prefix is used.  */
13622   if ((prefixes & PREFIX_ADDR) != 0
13623       && (used_prefixes & PREFIX_ADDR) != 0)
13624     all_prefixes[last_addr_prefix] = 0;
13625
13626   /* Check if the DATA prefix is used.  */
13627   if ((prefixes & PREFIX_DATA) != 0
13628       && (used_prefixes & PREFIX_DATA) != 0)
13629     all_prefixes[last_data_prefix] = 0;
13630
13631   /* Print the extra prefixes.  */
13632   prefix_length = 0;
13633   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13634     if (all_prefixes[i])
13635       {
13636         const char *name;
13637         name = prefix_name (all_prefixes[i], orig_sizeflag);
13638         if (name == NULL)
13639           abort ();
13640         prefix_length += strlen (name) + 1;
13641         (*info->fprintf_func) (info->stream, "%s ", name);
13642       }
13643
13644   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13645      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13646      used by putop and MMX/SSE operand and may be overriden by the
13647      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13648      separately.  */
13649   if (dp->prefix_requirement == PREFIX_OPCODE
13650       && dp != &bad_opcode
13651       && (((prefixes
13652             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13653            && (used_prefixes
13654                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13655           || ((((prefixes
13656                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13657                 == PREFIX_DATA)
13658                && (used_prefixes & PREFIX_DATA) == 0))))
13659     {
13660       (*info->fprintf_func) (info->stream, "(bad)");
13661       return end_codep - priv.the_buffer;
13662     }
13663
13664   /* Check maximum code length.  */
13665   if ((codep - start_codep) > MAX_CODE_LENGTH)
13666     {
13667       (*info->fprintf_func) (info->stream, "(bad)");
13668       return MAX_CODE_LENGTH;
13669     }
13670
13671   obufp = mnemonicendp;
13672   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13673     oappend (" ");
13674   oappend (" ");
13675   (*info->fprintf_func) (info->stream, "%s", obuf);
13676
13677   /* The enter and bound instructions are printed with operands in the same
13678      order as the intel book; everything else is printed in reverse order.  */
13679   if (intel_syntax || two_source_ops)
13680     {
13681       bfd_vma riprel;
13682
13683       for (i = 0; i < MAX_OPERANDS; ++i)
13684         op_txt[i] = op_out[i];
13685
13686       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13687           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13688         {
13689           op_txt[2] = op_out[3];
13690           op_txt[3] = op_out[2];
13691         }
13692
13693       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13694         {
13695           op_ad = op_index[i];
13696           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13697           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13698           riprel = op_riprel[i];
13699           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13700           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13701         }
13702     }
13703   else
13704     {
13705       for (i = 0; i < MAX_OPERANDS; ++i)
13706         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13707     }
13708
13709   needcomma = 0;
13710   for (i = 0; i < MAX_OPERANDS; ++i)
13711     if (*op_txt[i])
13712       {
13713         if (needcomma)
13714           (*info->fprintf_func) (info->stream, ",");
13715         if (op_index[i] != -1 && !op_riprel[i])
13716           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13717         else
13718           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13719         needcomma = 1;
13720       }
13721
13722   for (i = 0; i < MAX_OPERANDS; i++)
13723     if (op_index[i] != -1 && op_riprel[i])
13724       {
13725         (*info->fprintf_func) (info->stream, "        # ");
13726         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13727                                                 + op_address[op_index[i]]), info);
13728         break;
13729       }
13730   return codep - priv.the_buffer;
13731 }
13732
13733 static const char *float_mem[] = {
13734   /* d8 */
13735   "fadd{s|}",
13736   "fmul{s|}",
13737   "fcom{s|}",
13738   "fcomp{s|}",
13739   "fsub{s|}",
13740   "fsubr{s|}",
13741   "fdiv{s|}",
13742   "fdivr{s|}",
13743   /* d9 */
13744   "fld{s|}",
13745   "(bad)",
13746   "fst{s|}",
13747   "fstp{s|}",
13748   "fldenvIC",
13749   "fldcw",
13750   "fNstenvIC",
13751   "fNstcw",
13752   /* da */
13753   "fiadd{l|}",
13754   "fimul{l|}",
13755   "ficom{l|}",
13756   "ficomp{l|}",
13757   "fisub{l|}",
13758   "fisubr{l|}",
13759   "fidiv{l|}",
13760   "fidivr{l|}",
13761   /* db */
13762   "fild{l|}",
13763   "fisttp{l|}",
13764   "fist{l|}",
13765   "fistp{l|}",
13766   "(bad)",
13767   "fld{t||t|}",
13768   "(bad)",
13769   "fstp{t||t|}",
13770   /* dc */
13771   "fadd{l|}",
13772   "fmul{l|}",
13773   "fcom{l|}",
13774   "fcomp{l|}",
13775   "fsub{l|}",
13776   "fsubr{l|}",
13777   "fdiv{l|}",
13778   "fdivr{l|}",
13779   /* dd */
13780   "fld{l|}",
13781   "fisttp{ll|}",
13782   "fst{l||}",
13783   "fstp{l|}",
13784   "frstorIC",
13785   "(bad)",
13786   "fNsaveIC",
13787   "fNstsw",
13788   /* de */
13789   "fiadd",
13790   "fimul",
13791   "ficom",
13792   "ficomp",
13793   "fisub",
13794   "fisubr",
13795   "fidiv",
13796   "fidivr",
13797   /* df */
13798   "fild",
13799   "fisttp",
13800   "fist",
13801   "fistp",
13802   "fbld",
13803   "fild{ll|}",
13804   "fbstp",
13805   "fistp{ll|}",
13806 };
13807
13808 static const unsigned char float_mem_mode[] = {
13809   /* d8 */
13810   d_mode,
13811   d_mode,
13812   d_mode,
13813   d_mode,
13814   d_mode,
13815   d_mode,
13816   d_mode,
13817   d_mode,
13818   /* d9 */
13819   d_mode,
13820   0,
13821   d_mode,
13822   d_mode,
13823   0,
13824   w_mode,
13825   0,
13826   w_mode,
13827   /* da */
13828   d_mode,
13829   d_mode,
13830   d_mode,
13831   d_mode,
13832   d_mode,
13833   d_mode,
13834   d_mode,
13835   d_mode,
13836   /* db */
13837   d_mode,
13838   d_mode,
13839   d_mode,
13840   d_mode,
13841   0,
13842   t_mode,
13843   0,
13844   t_mode,
13845   /* dc */
13846   q_mode,
13847   q_mode,
13848   q_mode,
13849   q_mode,
13850   q_mode,
13851   q_mode,
13852   q_mode,
13853   q_mode,
13854   /* dd */
13855   q_mode,
13856   q_mode,
13857   q_mode,
13858   q_mode,
13859   0,
13860   0,
13861   0,
13862   w_mode,
13863   /* de */
13864   w_mode,
13865   w_mode,
13866   w_mode,
13867   w_mode,
13868   w_mode,
13869   w_mode,
13870   w_mode,
13871   w_mode,
13872   /* df */
13873   w_mode,
13874   w_mode,
13875   w_mode,
13876   w_mode,
13877   t_mode,
13878   q_mode,
13879   t_mode,
13880   q_mode
13881 };
13882
13883 #define ST { OP_ST, 0 }
13884 #define STi { OP_STi, 0 }
13885
13886 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13887 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13888 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13889 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13890 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13891 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13892 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13893 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13894 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13895
13896 static const struct dis386 float_reg[][8] = {
13897   /* d8 */
13898   {
13899     { "fadd",   { ST, STi }, 0 },
13900     { "fmul",   { ST, STi }, 0 },
13901     { "fcom",   { STi }, 0 },
13902     { "fcomp",  { STi }, 0 },
13903     { "fsub",   { ST, STi }, 0 },
13904     { "fsubr",  { ST, STi }, 0 },
13905     { "fdiv",   { ST, STi }, 0 },
13906     { "fdivr",  { ST, STi }, 0 },
13907   },
13908   /* d9 */
13909   {
13910     { "fld",    { STi }, 0 },
13911     { "fxch",   { STi }, 0 },
13912     { FGRPd9_2 },
13913     { Bad_Opcode },
13914     { FGRPd9_4 },
13915     { FGRPd9_5 },
13916     { FGRPd9_6 },
13917     { FGRPd9_7 },
13918   },
13919   /* da */
13920   {
13921     { "fcmovb", { ST, STi }, 0 },
13922     { "fcmove", { ST, STi }, 0 },
13923     { "fcmovbe",{ ST, STi }, 0 },
13924     { "fcmovu", { ST, STi }, 0 },
13925     { Bad_Opcode },
13926     { FGRPda_5 },
13927     { Bad_Opcode },
13928     { Bad_Opcode },
13929   },
13930   /* db */
13931   {
13932     { "fcmovnb",{ ST, STi }, 0 },
13933     { "fcmovne",{ ST, STi }, 0 },
13934     { "fcmovnbe",{ ST, STi }, 0 },
13935     { "fcmovnu",{ ST, STi }, 0 },
13936     { FGRPdb_4 },
13937     { "fucomi", { ST, STi }, 0 },
13938     { "fcomi",  { ST, STi }, 0 },
13939     { Bad_Opcode },
13940   },
13941   /* dc */
13942   {
13943     { "fadd",   { STi, ST }, 0 },
13944     { "fmul",   { STi, ST }, 0 },
13945     { Bad_Opcode },
13946     { Bad_Opcode },
13947     { "fsub!M", { STi, ST }, 0 },
13948     { "fsubM",  { STi, ST }, 0 },
13949     { "fdiv!M", { STi, ST }, 0 },
13950     { "fdivM",  { STi, ST }, 0 },
13951   },
13952   /* dd */
13953   {
13954     { "ffree",  { STi }, 0 },
13955     { Bad_Opcode },
13956     { "fst",    { STi }, 0 },
13957     { "fstp",   { STi }, 0 },
13958     { "fucom",  { STi }, 0 },
13959     { "fucomp", { STi }, 0 },
13960     { Bad_Opcode },
13961     { Bad_Opcode },
13962   },
13963   /* de */
13964   {
13965     { "faddp",  { STi, ST }, 0 },
13966     { "fmulp",  { STi, ST }, 0 },
13967     { Bad_Opcode },
13968     { FGRPde_3 },
13969     { "fsub!Mp", { STi, ST }, 0 },
13970     { "fsubMp", { STi, ST }, 0 },
13971     { "fdiv!Mp", { STi, ST }, 0 },
13972     { "fdivMp", { STi, ST }, 0 },
13973   },
13974   /* df */
13975   {
13976     { "ffreep", { STi }, 0 },
13977     { Bad_Opcode },
13978     { Bad_Opcode },
13979     { Bad_Opcode },
13980     { FGRPdf_4 },
13981     { "fucomip", { ST, STi }, 0 },
13982     { "fcomip", { ST, STi }, 0 },
13983     { Bad_Opcode },
13984   },
13985 };
13986
13987 static char *fgrps[][8] = {
13988   /* d9_2  0 */
13989   {
13990     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13991   },
13992
13993   /* d9_4  1 */
13994   {
13995     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13996   },
13997
13998   /* d9_5  2 */
13999   {
14000     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
14001   },
14002
14003   /* d9_6  3 */
14004   {
14005     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
14006   },
14007
14008   /* d9_7  4 */
14009   {
14010     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
14011   },
14012
14013   /* da_5  5 */
14014   {
14015     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
14016   },
14017
14018   /* db_4  6 */
14019   {
14020     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
14021     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
14022   },
14023
14024   /* de_3  7 */
14025   {
14026     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
14027   },
14028
14029   /* df_4  8 */
14030   {
14031     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
14032   },
14033 };
14034
14035 static void
14036 swap_operand (void)
14037 {
14038   mnemonicendp[0] = '.';
14039   mnemonicendp[1] = 's';
14040   mnemonicendp += 2;
14041 }
14042
14043 static void
14044 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
14045                int sizeflag ATTRIBUTE_UNUSED)
14046 {
14047   /* Skip mod/rm byte.  */
14048   MODRM_CHECK;
14049   codep++;
14050 }
14051
14052 static void
14053 dofloat (int sizeflag)
14054 {
14055   const struct dis386 *dp;
14056   unsigned char floatop;
14057
14058   floatop = codep[-1];
14059
14060   if (modrm.mod != 3)
14061     {
14062       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
14063
14064       putop (float_mem[fp_indx], sizeflag);
14065       obufp = op_out[0];
14066       op_ad = 2;
14067       OP_E (float_mem_mode[fp_indx], sizeflag);
14068       return;
14069     }
14070   /* Skip mod/rm byte.  */
14071   MODRM_CHECK;
14072   codep++;
14073
14074   dp = &float_reg[floatop - 0xd8][modrm.reg];
14075   if (dp->name == NULL)
14076     {
14077       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
14078
14079       /* Instruction fnstsw is only one with strange arg.  */
14080       if (floatop == 0xdf && codep[-1] == 0xe0)
14081         strcpy (op_out[0], names16[0]);
14082     }
14083   else
14084     {
14085       putop (dp->name, sizeflag);
14086
14087       obufp = op_out[0];
14088       op_ad = 2;
14089       if (dp->op[0].rtn)
14090         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
14091
14092       obufp = op_out[1];
14093       op_ad = 1;
14094       if (dp->op[1].rtn)
14095         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
14096     }
14097 }
14098
14099 /* Like oappend (below), but S is a string starting with '%'.
14100    In Intel syntax, the '%' is elided.  */
14101 static void
14102 oappend_maybe_intel (const char *s)
14103 {
14104   oappend (s + intel_syntax);
14105 }
14106
14107 static void
14108 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14109 {
14110   oappend_maybe_intel ("%st");
14111 }
14112
14113 static void
14114 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14115 {
14116   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
14117   oappend_maybe_intel (scratchbuf);
14118 }
14119
14120 /* Capital letters in template are macros.  */
14121 static int
14122 putop (const char *in_template, int sizeflag)
14123 {
14124   const char *p;
14125   int alt = 0;
14126   int cond = 1;
14127   unsigned int l = 0, len = 1;
14128   char last[4];
14129
14130 #define SAVE_LAST(c)                    \
14131   if (l < len && l < sizeof (last))     \
14132     last[l++] = c;                      \
14133   else                                  \
14134     abort ();
14135
14136   for (p = in_template; *p; p++)
14137     {
14138       switch (*p)
14139         {
14140         default:
14141           *obufp++ = *p;
14142           break;
14143         case '%':
14144           len++;
14145           break;
14146         case '!':
14147           cond = 0;
14148           break;
14149         case '{':
14150           if (intel_syntax)
14151             {
14152               while (*++p != '|')
14153                 if (*p == '}' || *p == '\0')
14154                   abort ();
14155             }
14156           /* Fall through.  */
14157         case 'I':
14158           alt = 1;
14159           continue;
14160         case '|':
14161           while (*++p != '}')
14162             {
14163               if (*p == '\0')
14164                 abort ();
14165             }
14166           break;
14167         case '}':
14168           break;
14169         case 'A':
14170           if (intel_syntax)
14171             break;
14172           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14173             *obufp++ = 'b';
14174           break;
14175         case 'B':
14176           if (l == 0 && len == 1)
14177             {
14178 case_B:
14179               if (intel_syntax)
14180                 break;
14181               if (sizeflag & SUFFIX_ALWAYS)
14182                 *obufp++ = 'b';
14183             }
14184           else
14185             {
14186               if (l != 1
14187                   || len != 2
14188                   || last[0] != 'L')
14189                 {
14190                   SAVE_LAST (*p);
14191                   break;
14192                 }
14193
14194               if (address_mode == mode_64bit
14195                   && !(prefixes & PREFIX_ADDR))
14196                 {
14197                   *obufp++ = 'a';
14198                   *obufp++ = 'b';
14199                   *obufp++ = 's';
14200                 }
14201
14202               goto case_B;
14203             }
14204           break;
14205         case 'C':
14206           if (intel_syntax && !alt)
14207             break;
14208           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14209             {
14210               if (sizeflag & DFLAG)
14211                 *obufp++ = intel_syntax ? 'd' : 'l';
14212               else
14213                 *obufp++ = intel_syntax ? 'w' : 's';
14214               used_prefixes |= (prefixes & PREFIX_DATA);
14215             }
14216           break;
14217         case 'D':
14218           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14219             break;
14220           USED_REX (REX_W);
14221           if (modrm.mod == 3)
14222             {
14223               if (rex & REX_W)
14224                 *obufp++ = 'q';
14225               else
14226                 {
14227                   if (sizeflag & DFLAG)
14228                     *obufp++ = intel_syntax ? 'd' : 'l';
14229                   else
14230                     *obufp++ = 'w';
14231                   used_prefixes |= (prefixes & PREFIX_DATA);
14232                 }
14233             }
14234           else
14235             *obufp++ = 'w';
14236           break;
14237         case 'E':               /* For jcxz/jecxz */
14238           if (address_mode == mode_64bit)
14239             {
14240               if (sizeflag & AFLAG)
14241                 *obufp++ = 'r';
14242               else
14243                 *obufp++ = 'e';
14244             }
14245           else
14246             if (sizeflag & AFLAG)
14247               *obufp++ = 'e';
14248           used_prefixes |= (prefixes & PREFIX_ADDR);
14249           break;
14250         case 'F':
14251           if (intel_syntax)
14252             break;
14253           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14254             {
14255               if (sizeflag & AFLAG)
14256                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14257               else
14258                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14259               used_prefixes |= (prefixes & PREFIX_ADDR);
14260             }
14261           break;
14262         case 'G':
14263           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14264             break;
14265           if ((rex & REX_W) || (sizeflag & DFLAG))
14266             *obufp++ = 'l';
14267           else
14268             *obufp++ = 'w';
14269           if (!(rex & REX_W))
14270             used_prefixes |= (prefixes & PREFIX_DATA);
14271           break;
14272         case 'H':
14273           if (intel_syntax)
14274             break;
14275           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14276               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14277             {
14278               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14279               *obufp++ = ',';
14280               *obufp++ = 'p';
14281               if (prefixes & PREFIX_DS)
14282                 *obufp++ = 't';
14283               else
14284                 *obufp++ = 'n';
14285             }
14286           break;
14287         case 'J':
14288           if (intel_syntax)
14289             break;
14290           *obufp++ = 'l';
14291           break;
14292         case 'K':
14293           USED_REX (REX_W);
14294           if (rex & REX_W)
14295             *obufp++ = 'q';
14296           else
14297             *obufp++ = 'd';
14298           break;
14299         case 'Z':
14300           if (l != 0 || len != 1)
14301             {
14302               if (l != 1 || len != 2 || last[0] != 'X')
14303                 {
14304                   SAVE_LAST (*p);
14305                   break;
14306                 }
14307               if (!need_vex || !vex.evex)
14308                 abort ();
14309               if (intel_syntax
14310                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14311                 break;
14312               switch (vex.length)
14313                 {
14314                 case 128:
14315                   *obufp++ = 'x';
14316                   break;
14317                 case 256:
14318                   *obufp++ = 'y';
14319                   break;
14320                 case 512:
14321                   *obufp++ = 'z';
14322                   break;
14323                 default:
14324                   abort ();
14325                 }
14326               break;
14327             }
14328           if (intel_syntax)
14329             break;
14330           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14331             {
14332               *obufp++ = 'q';
14333               break;
14334             }
14335           /* Fall through.  */
14336           goto case_L;
14337         case 'L':
14338           if (l != 0 || len != 1)
14339             {
14340               SAVE_LAST (*p);
14341               break;
14342             }
14343 case_L:
14344           if (intel_syntax)
14345             break;
14346           if (sizeflag & SUFFIX_ALWAYS)
14347             *obufp++ = 'l';
14348           break;
14349         case 'M':
14350           if (intel_mnemonic != cond)
14351             *obufp++ = 'r';
14352           break;
14353         case 'N':
14354           if ((prefixes & PREFIX_FWAIT) == 0)
14355             *obufp++ = 'n';
14356           else
14357             used_prefixes |= PREFIX_FWAIT;
14358           break;
14359         case 'O':
14360           USED_REX (REX_W);
14361           if (rex & REX_W)
14362             *obufp++ = 'o';
14363           else if (intel_syntax && (sizeflag & DFLAG))
14364             *obufp++ = 'q';
14365           else
14366             *obufp++ = 'd';
14367           if (!(rex & REX_W))
14368             used_prefixes |= (prefixes & PREFIX_DATA);
14369           break;
14370         case '&':
14371           if (!intel_syntax
14372               && address_mode == mode_64bit
14373               && isa64 == intel64)
14374             {
14375               *obufp++ = 'q';
14376               break;
14377             }
14378           /* Fall through.  */
14379         case 'T':
14380           if (!intel_syntax
14381               && address_mode == mode_64bit
14382               && ((sizeflag & DFLAG) || (rex & REX_W)))
14383             {
14384               *obufp++ = 'q';
14385               break;
14386             }
14387           /* Fall through.  */
14388           goto case_P;
14389         case 'P':
14390           if (l == 0 && len == 1)
14391             {
14392 case_P:
14393               if (intel_syntax)
14394                 {
14395                   if ((rex & REX_W) == 0
14396                       && (prefixes & PREFIX_DATA))
14397                     {
14398                       if ((sizeflag & DFLAG) == 0)
14399                         *obufp++ = 'w';
14400                       used_prefixes |= (prefixes & PREFIX_DATA);
14401                     }
14402                   break;
14403                 }
14404               if ((prefixes & PREFIX_DATA)
14405                   || (rex & REX_W)
14406                   || (sizeflag & SUFFIX_ALWAYS))
14407                 {
14408                   USED_REX (REX_W);
14409                   if (rex & REX_W)
14410                     *obufp++ = 'q';
14411                   else
14412                     {
14413                       if (sizeflag & DFLAG)
14414                         *obufp++ = 'l';
14415                       else
14416                         *obufp++ = 'w';
14417                       used_prefixes |= (prefixes & PREFIX_DATA);
14418                     }
14419                 }
14420             }
14421           else
14422             {
14423               if (l != 1 || len != 2 || last[0] != 'L')
14424                 {
14425                   SAVE_LAST (*p);
14426                   break;
14427                 }
14428
14429               if ((prefixes & PREFIX_DATA)
14430                   || (rex & REX_W)
14431                   || (sizeflag & SUFFIX_ALWAYS))
14432                 {
14433                   USED_REX (REX_W);
14434                   if (rex & REX_W)
14435                     *obufp++ = 'q';
14436                   else
14437                     {
14438                       if (sizeflag & DFLAG)
14439                         *obufp++ = intel_syntax ? 'd' : 'l';
14440                       else
14441                         *obufp++ = 'w';
14442                       used_prefixes |= (prefixes & PREFIX_DATA);
14443                     }
14444                 }
14445             }
14446           break;
14447         case 'U':
14448           if (intel_syntax)
14449             break;
14450           if (address_mode == mode_64bit
14451               && ((sizeflag & DFLAG) || (rex & REX_W)))
14452             {
14453               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14454                 *obufp++ = 'q';
14455               break;
14456             }
14457           /* Fall through.  */
14458           goto case_Q;
14459         case 'Q':
14460           if (l == 0 && len == 1)
14461             {
14462 case_Q:
14463               if (intel_syntax && !alt)
14464                 break;
14465               USED_REX (REX_W);
14466               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14467                 {
14468                   if (rex & REX_W)
14469                     *obufp++ = 'q';
14470                   else
14471                     {
14472                       if (sizeflag & DFLAG)
14473                         *obufp++ = intel_syntax ? 'd' : 'l';
14474                       else
14475                         *obufp++ = 'w';
14476                       used_prefixes |= (prefixes & PREFIX_DATA);
14477                     }
14478                 }
14479             }
14480           else
14481             {
14482               if (l != 1 || len != 2 || last[0] != 'L')
14483                 {
14484                   SAVE_LAST (*p);
14485                   break;
14486                 }
14487               if (intel_syntax
14488                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14489                 break;
14490               if ((rex & REX_W))
14491                 {
14492                   USED_REX (REX_W);
14493                   *obufp++ = 'q';
14494                 }
14495               else
14496                 *obufp++ = 'l';
14497             }
14498           break;
14499         case 'R':
14500           USED_REX (REX_W);
14501           if (rex & REX_W)
14502             *obufp++ = 'q';
14503           else if (sizeflag & DFLAG)
14504             {
14505               if (intel_syntax)
14506                   *obufp++ = 'd';
14507               else
14508                   *obufp++ = 'l';
14509             }
14510           else
14511             *obufp++ = 'w';
14512           if (intel_syntax && !p[1]
14513               && ((rex & REX_W) || (sizeflag & DFLAG)))
14514             *obufp++ = 'e';
14515           if (!(rex & REX_W))
14516             used_prefixes |= (prefixes & PREFIX_DATA);
14517           break;
14518         case 'V':
14519           if (l == 0 && len == 1)
14520             {
14521               if (intel_syntax)
14522                 break;
14523               if (address_mode == mode_64bit
14524                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14525                 {
14526                   if (sizeflag & SUFFIX_ALWAYS)
14527                     *obufp++ = 'q';
14528                   break;
14529                 }
14530             }
14531           else
14532             {
14533               if (l != 1
14534                   || len != 2
14535                   || last[0] != 'L')
14536                 {
14537                   SAVE_LAST (*p);
14538                   break;
14539                 }
14540
14541               if (rex & REX_W)
14542                 {
14543                   *obufp++ = 'a';
14544                   *obufp++ = 'b';
14545                   *obufp++ = 's';
14546                 }
14547             }
14548           /* Fall through.  */
14549           goto case_S;
14550         case 'S':
14551           if (l == 0 && len == 1)
14552             {
14553 case_S:
14554               if (intel_syntax)
14555                 break;
14556               if (sizeflag & SUFFIX_ALWAYS)
14557                 {
14558                   if (rex & REX_W)
14559                     *obufp++ = 'q';
14560                   else
14561                     {
14562                       if (sizeflag & DFLAG)
14563                         *obufp++ = 'l';
14564                       else
14565                         *obufp++ = 'w';
14566                       used_prefixes |= (prefixes & PREFIX_DATA);
14567                     }
14568                 }
14569             }
14570           else
14571             {
14572               if (l != 1
14573                   || len != 2
14574                   || last[0] != 'L')
14575                 {
14576                   SAVE_LAST (*p);
14577                   break;
14578                 }
14579
14580               if (address_mode == mode_64bit
14581                   && !(prefixes & PREFIX_ADDR))
14582                 {
14583                   *obufp++ = 'a';
14584                   *obufp++ = 'b';
14585                   *obufp++ = 's';
14586                 }
14587
14588               goto case_S;
14589             }
14590           break;
14591         case 'X':
14592           if (l != 0 || len != 1)
14593             {
14594               SAVE_LAST (*p);
14595               break;
14596             }
14597           if (need_vex && vex.prefix)
14598             {
14599               if (vex.prefix == DATA_PREFIX_OPCODE)
14600                 *obufp++ = 'd';
14601               else
14602                 *obufp++ = 's';
14603             }
14604           else
14605             {
14606               if (prefixes & PREFIX_DATA)
14607                 *obufp++ = 'd';
14608               else
14609                 *obufp++ = 's';
14610               used_prefixes |= (prefixes & PREFIX_DATA);
14611             }
14612           break;
14613         case 'Y':
14614           if (l == 0 && len == 1)
14615             {
14616               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14617                 break;
14618               if (rex & REX_W)
14619                 {
14620                   USED_REX (REX_W);
14621                   *obufp++ = 'q';
14622                 }
14623               break;
14624             }
14625           else
14626             {
14627               if (l != 1 || len != 2 || last[0] != 'X')
14628                 {
14629                   SAVE_LAST (*p);
14630                   break;
14631                 }
14632               if (!need_vex)
14633                 abort ();
14634               if (intel_syntax
14635                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14636                 break;
14637               switch (vex.length)
14638                 {
14639                 case 128:
14640                   *obufp++ = 'x';
14641                   break;
14642                 case 256:
14643                   *obufp++ = 'y';
14644                   break;
14645                 case 512:
14646                   if (!vex.evex)
14647                 default:
14648                     abort ();
14649                 }
14650             }
14651           break;
14652         case 'W':
14653           if (l == 0 && len == 1)
14654             {
14655               /* operand size flag for cwtl, cbtw */
14656               USED_REX (REX_W);
14657               if (rex & REX_W)
14658                 {
14659                   if (intel_syntax)
14660                     *obufp++ = 'd';
14661                   else
14662                     *obufp++ = 'l';
14663                 }
14664               else if (sizeflag & DFLAG)
14665                 *obufp++ = 'w';
14666               else
14667                 *obufp++ = 'b';
14668               if (!(rex & REX_W))
14669                 used_prefixes |= (prefixes & PREFIX_DATA);
14670             }
14671           else
14672             {
14673               if (l != 1
14674                   || len != 2
14675                   || (last[0] != 'X'
14676                       && last[0] != 'L'))
14677                 {
14678                   SAVE_LAST (*p);
14679                   break;
14680                 }
14681               if (!need_vex)
14682                 abort ();
14683               if (last[0] == 'X')
14684                 *obufp++ = vex.w ? 'd': 's';
14685               else
14686                 *obufp++ = vex.w ? 'q': 'd';
14687             }
14688           break;
14689         case '^':
14690           if (intel_syntax)
14691             break;
14692           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14693             {
14694               if (sizeflag & DFLAG)
14695                 *obufp++ = 'l';
14696               else
14697                 *obufp++ = 'w';
14698               used_prefixes |= (prefixes & PREFIX_DATA);
14699             }
14700           break;
14701         case '@':
14702           if (intel_syntax)
14703             break;
14704           if (address_mode == mode_64bit
14705               && (isa64 == intel64
14706                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14707               *obufp++ = 'q';
14708           else if ((prefixes & PREFIX_DATA))
14709             {
14710               if (!(sizeflag & DFLAG))
14711                 *obufp++ = 'w';
14712               used_prefixes |= (prefixes & PREFIX_DATA);
14713             }
14714           break;
14715         }
14716       alt = 0;
14717     }
14718   *obufp = 0;
14719   mnemonicendp = obufp;
14720   return 0;
14721 }
14722
14723 static void
14724 oappend (const char *s)
14725 {
14726   obufp = stpcpy (obufp, s);
14727 }
14728
14729 static void
14730 append_seg (void)
14731 {
14732   /* Only print the active segment register.  */
14733   if (!active_seg_prefix)
14734     return;
14735
14736   used_prefixes |= active_seg_prefix;
14737   switch (active_seg_prefix)
14738     {
14739     case PREFIX_CS:
14740       oappend_maybe_intel ("%cs:");
14741       break;
14742     case PREFIX_DS:
14743       oappend_maybe_intel ("%ds:");
14744       break;
14745     case PREFIX_SS:
14746       oappend_maybe_intel ("%ss:");
14747       break;
14748     case PREFIX_ES:
14749       oappend_maybe_intel ("%es:");
14750       break;
14751     case PREFIX_FS:
14752       oappend_maybe_intel ("%fs:");
14753       break;
14754     case PREFIX_GS:
14755       oappend_maybe_intel ("%gs:");
14756       break;
14757     default:
14758       break;
14759     }
14760 }
14761
14762 static void
14763 OP_indirE (int bytemode, int sizeflag)
14764 {
14765   if (!intel_syntax)
14766     oappend ("*");
14767   OP_E (bytemode, sizeflag);
14768 }
14769
14770 static void
14771 print_operand_value (char *buf, int hex, bfd_vma disp)
14772 {
14773   if (address_mode == mode_64bit)
14774     {
14775       if (hex)
14776         {
14777           char tmp[30];
14778           int i;
14779           buf[0] = '0';
14780           buf[1] = 'x';
14781           sprintf_vma (tmp, disp);
14782           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14783           strcpy (buf + 2, tmp + i);
14784         }
14785       else
14786         {
14787           bfd_signed_vma v = disp;
14788           char tmp[30];
14789           int i;
14790           if (v < 0)
14791             {
14792               *(buf++) = '-';
14793               v = -disp;
14794               /* Check for possible overflow on 0x8000000000000000.  */
14795               if (v < 0)
14796                 {
14797                   strcpy (buf, "9223372036854775808");
14798                   return;
14799                 }
14800             }
14801           if (!v)
14802             {
14803               strcpy (buf, "0");
14804               return;
14805             }
14806
14807           i = 0;
14808           tmp[29] = 0;
14809           while (v)
14810             {
14811               tmp[28 - i] = (v % 10) + '0';
14812               v /= 10;
14813               i++;
14814             }
14815           strcpy (buf, tmp + 29 - i);
14816         }
14817     }
14818   else
14819     {
14820       if (hex)
14821         sprintf (buf, "0x%x", (unsigned int) disp);
14822       else
14823         sprintf (buf, "%d", (int) disp);
14824     }
14825 }
14826
14827 /* Put DISP in BUF as signed hex number.  */
14828
14829 static void
14830 print_displacement (char *buf, bfd_vma disp)
14831 {
14832   bfd_signed_vma val = disp;
14833   char tmp[30];
14834   int i, j = 0;
14835
14836   if (val < 0)
14837     {
14838       buf[j++] = '-';
14839       val = -disp;
14840
14841       /* Check for possible overflow.  */
14842       if (val < 0)
14843         {
14844           switch (address_mode)
14845             {
14846             case mode_64bit:
14847               strcpy (buf + j, "0x8000000000000000");
14848               break;
14849             case mode_32bit:
14850               strcpy (buf + j, "0x80000000");
14851               break;
14852             case mode_16bit:
14853               strcpy (buf + j, "0x8000");
14854               break;
14855             }
14856           return;
14857         }
14858     }
14859
14860   buf[j++] = '0';
14861   buf[j++] = 'x';
14862
14863   sprintf_vma (tmp, (bfd_vma) val);
14864   for (i = 0; tmp[i] == '0'; i++)
14865     continue;
14866   if (tmp[i] == '\0')
14867     i--;
14868   strcpy (buf + j, tmp + i);
14869 }
14870
14871 static void
14872 intel_operand_size (int bytemode, int sizeflag)
14873 {
14874   if (vex.evex
14875       && vex.b
14876       && (bytemode == x_mode
14877           || bytemode == evex_half_bcst_xmmq_mode))
14878     {
14879       if (vex.w)
14880         oappend ("QWORD PTR ");
14881       else
14882         oappend ("DWORD PTR ");
14883       return;
14884     }
14885   switch (bytemode)
14886     {
14887     case b_mode:
14888     case b_swap_mode:
14889     case dqb_mode:
14890     case db_mode:
14891       oappend ("BYTE PTR ");
14892       break;
14893     case w_mode:
14894     case dw_mode:
14895     case dqw_mode:
14896     case dqw_swap_mode:
14897       oappend ("WORD PTR ");
14898       break;
14899     case indir_v_mode:
14900       if (address_mode == mode_64bit && isa64 == intel64)
14901         {
14902           oappend ("QWORD PTR ");
14903           break;
14904         }
14905       /* Fall through.  */
14906     case stack_v_mode:
14907       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14908         {
14909           oappend ("QWORD PTR ");
14910           break;
14911         }
14912       /* Fall through.  */
14913     case v_mode:
14914     case v_swap_mode:
14915     case dq_mode:
14916       USED_REX (REX_W);
14917       if (rex & REX_W)
14918         oappend ("QWORD PTR ");
14919       else
14920         {
14921           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14922             oappend ("DWORD PTR ");
14923           else
14924             oappend ("WORD PTR ");
14925           used_prefixes |= (prefixes & PREFIX_DATA);
14926         }
14927       break;
14928     case z_mode:
14929       if ((rex & REX_W) || (sizeflag & DFLAG))
14930         *obufp++ = 'D';
14931       oappend ("WORD PTR ");
14932       if (!(rex & REX_W))
14933         used_prefixes |= (prefixes & PREFIX_DATA);
14934       break;
14935     case a_mode:
14936       if (sizeflag & DFLAG)
14937         oappend ("QWORD PTR ");
14938       else
14939         oappend ("DWORD PTR ");
14940       used_prefixes |= (prefixes & PREFIX_DATA);
14941       break;
14942     case d_mode:
14943     case d_scalar_mode:
14944     case d_scalar_swap_mode:
14945     case d_swap_mode:
14946     case dqd_mode:
14947       oappend ("DWORD PTR ");
14948       break;
14949     case q_mode:
14950     case q_scalar_mode:
14951     case q_scalar_swap_mode:
14952     case q_swap_mode:
14953       oappend ("QWORD PTR ");
14954       break;
14955     case m_mode:
14956       if (address_mode == mode_64bit)
14957         oappend ("QWORD PTR ");
14958       else
14959         oappend ("DWORD PTR ");
14960       break;
14961     case f_mode:
14962       if (sizeflag & DFLAG)
14963         oappend ("FWORD PTR ");
14964       else
14965         oappend ("DWORD PTR ");
14966       used_prefixes |= (prefixes & PREFIX_DATA);
14967       break;
14968     case t_mode:
14969       oappend ("TBYTE PTR ");
14970       break;
14971     case x_mode:
14972     case x_swap_mode:
14973     case evex_x_gscat_mode:
14974     case evex_x_nobcst_mode:
14975       if (need_vex)
14976         {
14977           switch (vex.length)
14978             {
14979             case 128:
14980               oappend ("XMMWORD PTR ");
14981               break;
14982             case 256:
14983               oappend ("YMMWORD PTR ");
14984               break;
14985             case 512:
14986               oappend ("ZMMWORD PTR ");
14987               break;
14988             default:
14989               abort ();
14990             }
14991         }
14992       else
14993         oappend ("XMMWORD PTR ");
14994       break;
14995     case xmm_mode:
14996       oappend ("XMMWORD PTR ");
14997       break;
14998     case ymm_mode:
14999       oappend ("YMMWORD PTR ");
15000       break;
15001     case xmmq_mode:
15002     case evex_half_bcst_xmmq_mode:
15003       if (!need_vex)
15004         abort ();
15005
15006       switch (vex.length)
15007         {
15008         case 128:
15009           oappend ("QWORD PTR ");
15010           break;
15011         case 256:
15012           oappend ("XMMWORD PTR ");
15013           break;
15014         case 512:
15015           oappend ("YMMWORD PTR ");
15016           break;
15017         default:
15018           abort ();
15019         }
15020       break;
15021     case xmm_mb_mode:
15022       if (!need_vex)
15023         abort ();
15024
15025       switch (vex.length)
15026         {
15027         case 128:
15028         case 256:
15029         case 512:
15030           oappend ("BYTE PTR ");
15031           break;
15032         default:
15033           abort ();
15034         }
15035       break;
15036     case xmm_mw_mode:
15037       if (!need_vex)
15038         abort ();
15039
15040       switch (vex.length)
15041         {
15042         case 128:
15043         case 256:
15044         case 512:
15045           oappend ("WORD PTR ");
15046           break;
15047         default:
15048           abort ();
15049         }
15050       break;
15051     case xmm_md_mode:
15052       if (!need_vex)
15053         abort ();
15054
15055       switch (vex.length)
15056         {
15057         case 128:
15058         case 256:
15059         case 512:
15060           oappend ("DWORD PTR ");
15061           break;
15062         default:
15063           abort ();
15064         }
15065       break;
15066     case xmm_mq_mode:
15067       if (!need_vex)
15068         abort ();
15069
15070       switch (vex.length)
15071         {
15072         case 128:
15073         case 256:
15074         case 512:
15075           oappend ("QWORD PTR ");
15076           break;
15077         default:
15078           abort ();
15079         }
15080       break;
15081     case xmmdw_mode:
15082       if (!need_vex)
15083         abort ();
15084
15085       switch (vex.length)
15086         {
15087         case 128:
15088           oappend ("WORD PTR ");
15089           break;
15090         case 256:
15091           oappend ("DWORD PTR ");
15092           break;
15093         case 512:
15094           oappend ("QWORD PTR ");
15095           break;
15096         default:
15097           abort ();
15098         }
15099       break;
15100     case xmmqd_mode:
15101       if (!need_vex)
15102         abort ();
15103
15104       switch (vex.length)
15105         {
15106         case 128:
15107           oappend ("DWORD PTR ");
15108           break;
15109         case 256:
15110           oappend ("QWORD PTR ");
15111           break;
15112         case 512:
15113           oappend ("XMMWORD PTR ");
15114           break;
15115         default:
15116           abort ();
15117         }
15118       break;
15119     case ymmq_mode:
15120       if (!need_vex)
15121         abort ();
15122
15123       switch (vex.length)
15124         {
15125         case 128:
15126           oappend ("QWORD PTR ");
15127           break;
15128         case 256:
15129           oappend ("YMMWORD PTR ");
15130           break;
15131         case 512:
15132           oappend ("ZMMWORD PTR ");
15133           break;
15134         default:
15135           abort ();
15136         }
15137       break;
15138     case ymmxmm_mode:
15139       if (!need_vex)
15140         abort ();
15141
15142       switch (vex.length)
15143         {
15144         case 128:
15145         case 256:
15146           oappend ("XMMWORD PTR ");
15147           break;
15148         default:
15149           abort ();
15150         }
15151       break;
15152     case o_mode:
15153       oappend ("OWORD PTR ");
15154       break;
15155     case xmm_mdq_mode:
15156     case vex_w_dq_mode:
15157     case vex_scalar_w_dq_mode:
15158       if (!need_vex)
15159         abort ();
15160
15161       if (vex.w)
15162         oappend ("QWORD PTR ");
15163       else
15164         oappend ("DWORD PTR ");
15165       break;
15166     case vex_vsib_d_w_dq_mode:
15167     case vex_vsib_q_w_dq_mode:
15168       if (!need_vex)
15169         abort ();
15170
15171       if (!vex.evex)
15172         {
15173           if (vex.w)
15174             oappend ("QWORD PTR ");
15175           else
15176             oappend ("DWORD PTR ");
15177         }
15178       else
15179         {
15180           switch (vex.length)
15181             {
15182             case 128:
15183               oappend ("XMMWORD PTR ");
15184               break;
15185             case 256:
15186               oappend ("YMMWORD PTR ");
15187               break;
15188             case 512:
15189               oappend ("ZMMWORD PTR ");
15190               break;
15191             default:
15192               abort ();
15193             }
15194         }
15195       break;
15196     case vex_vsib_q_w_d_mode:
15197     case vex_vsib_d_w_d_mode:
15198       if (!need_vex || !vex.evex)
15199         abort ();
15200
15201       switch (vex.length)
15202         {
15203         case 128:
15204           oappend ("QWORD PTR ");
15205           break;
15206         case 256:
15207           oappend ("XMMWORD PTR ");
15208           break;
15209         case 512:
15210           oappend ("YMMWORD PTR ");
15211           break;
15212         default:
15213           abort ();
15214         }
15215
15216       break;
15217     case mask_bd_mode:
15218       if (!need_vex || vex.length != 128)
15219         abort ();
15220       if (vex.w)
15221         oappend ("DWORD PTR ");
15222       else
15223         oappend ("BYTE PTR ");
15224       break;
15225     case mask_mode:
15226       if (!need_vex)
15227         abort ();
15228       if (vex.w)
15229         oappend ("QWORD PTR ");
15230       else
15231         oappend ("WORD PTR ");
15232       break;
15233     case v_bnd_mode:
15234     default:
15235       break;
15236     }
15237 }
15238
15239 static void
15240 OP_E_register (int bytemode, int sizeflag)
15241 {
15242   int reg = modrm.rm;
15243   const char **names;
15244
15245   USED_REX (REX_B);
15246   if ((rex & REX_B))
15247     reg += 8;
15248
15249   if ((sizeflag & SUFFIX_ALWAYS)
15250       && (bytemode == b_swap_mode
15251           || bytemode == v_swap_mode
15252           || bytemode == dqw_swap_mode))
15253     swap_operand ();
15254
15255   switch (bytemode)
15256     {
15257     case b_mode:
15258     case b_swap_mode:
15259       USED_REX (0);
15260       if (rex)
15261         names = names8rex;
15262       else
15263         names = names8;
15264       break;
15265     case w_mode:
15266       names = names16;
15267       break;
15268     case d_mode:
15269     case dw_mode:
15270     case db_mode:
15271       names = names32;
15272       break;
15273     case q_mode:
15274       names = names64;
15275       break;
15276     case m_mode:
15277     case v_bnd_mode:
15278       names = address_mode == mode_64bit ? names64 : names32;
15279       break;
15280     case bnd_mode:
15281       names = names_bnd;
15282       break;
15283     case indir_v_mode:
15284       if (address_mode == mode_64bit && isa64 == intel64)
15285         {
15286           names = names64;
15287           break;
15288         }
15289       /* Fall through.  */
15290     case stack_v_mode:
15291       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15292         {
15293           names = names64;
15294           break;
15295         }
15296       bytemode = v_mode;
15297       /* Fall through.  */
15298     case v_mode:
15299     case v_swap_mode:
15300     case dq_mode:
15301     case dqb_mode:
15302     case dqd_mode:
15303     case dqw_mode:
15304     case dqw_swap_mode:
15305       USED_REX (REX_W);
15306       if (rex & REX_W)
15307         names = names64;
15308       else
15309         {
15310           if ((sizeflag & DFLAG)
15311               || (bytemode != v_mode
15312                   && bytemode != v_swap_mode))
15313             names = names32;
15314           else
15315             names = names16;
15316           used_prefixes |= (prefixes & PREFIX_DATA);
15317         }
15318       break;
15319     case mask_bd_mode:
15320     case mask_mode:
15321       if (reg > 0x7)
15322         {
15323           oappend ("(bad)");
15324           return;
15325         }
15326       names = names_mask;
15327       break;
15328     case 0:
15329       return;
15330     default:
15331       oappend (INTERNAL_DISASSEMBLER_ERROR);
15332       return;
15333     }
15334   oappend (names[reg]);
15335 }
15336
15337 static void
15338 OP_E_memory (int bytemode, int sizeflag)
15339 {
15340   bfd_vma disp = 0;
15341   int add = (rex & REX_B) ? 8 : 0;
15342   int riprel = 0;
15343   int shift;
15344
15345   if (vex.evex)
15346     {
15347       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15348       if (vex.b
15349           && bytemode != x_mode
15350           && bytemode != xmmq_mode
15351           && bytemode != evex_half_bcst_xmmq_mode)
15352         {
15353           BadOp ();
15354           return;
15355         }
15356       switch (bytemode)
15357         {
15358         case dqw_mode:
15359         case dw_mode:
15360         case dqw_swap_mode:
15361           shift = 1;
15362           break;
15363         case dqb_mode:
15364         case db_mode:
15365           shift = 0;
15366           break;
15367         case vex_vsib_d_w_dq_mode:
15368         case vex_vsib_d_w_d_mode:
15369         case vex_vsib_q_w_dq_mode:
15370         case vex_vsib_q_w_d_mode:
15371         case evex_x_gscat_mode:
15372         case xmm_mdq_mode:
15373           shift = vex.w ? 3 : 2;
15374           break;
15375         case x_mode:
15376         case evex_half_bcst_xmmq_mode:
15377         case xmmq_mode:
15378           if (vex.b)
15379             {
15380               shift = vex.w ? 3 : 2;
15381               break;
15382             }
15383           /* Fall through.  */
15384         case xmmqd_mode:
15385         case xmmdw_mode:
15386         case ymmq_mode:
15387         case evex_x_nobcst_mode:
15388         case x_swap_mode:
15389           switch (vex.length)
15390             {
15391             case 128:
15392               shift = 4;
15393               break;
15394             case 256:
15395               shift = 5;
15396               break;
15397             case 512:
15398               shift = 6;
15399               break;
15400             default:
15401               abort ();
15402             }
15403           break;
15404         case ymm_mode:
15405           shift = 5;
15406           break;
15407         case xmm_mode:
15408           shift = 4;
15409           break;
15410         case xmm_mq_mode:
15411         case q_mode:
15412         case q_scalar_mode:
15413         case q_swap_mode:
15414         case q_scalar_swap_mode:
15415           shift = 3;
15416           break;
15417         case dqd_mode:
15418         case xmm_md_mode:
15419         case d_mode:
15420         case d_scalar_mode:
15421         case d_swap_mode:
15422         case d_scalar_swap_mode:
15423           shift = 2;
15424           break;
15425         case xmm_mw_mode:
15426           shift = 1;
15427           break;
15428         case xmm_mb_mode:
15429           shift = 0;
15430           break;
15431         default:
15432           abort ();
15433         }
15434       /* Make necessary corrections to shift for modes that need it.
15435          For these modes we currently have shift 4, 5 or 6 depending on
15436          vex.length (it corresponds to xmmword, ymmword or zmmword
15437          operand).  We might want to make it 3, 4 or 5 (e.g. for
15438          xmmq_mode).  In case of broadcast enabled the corrections
15439          aren't needed, as element size is always 32 or 64 bits.  */
15440       if (!vex.b
15441           && (bytemode == xmmq_mode
15442               || bytemode == evex_half_bcst_xmmq_mode))
15443         shift -= 1;
15444       else if (bytemode == xmmqd_mode)
15445         shift -= 2;
15446       else if (bytemode == xmmdw_mode)
15447         shift -= 3;
15448       else if (bytemode == ymmq_mode && vex.length == 128)
15449         shift -= 1;
15450     }
15451   else
15452     shift = 0;
15453
15454   USED_REX (REX_B);
15455   if (intel_syntax)
15456     intel_operand_size (bytemode, sizeflag);
15457   append_seg ();
15458
15459   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15460     {
15461       /* 32/64 bit address mode */
15462       int havedisp;
15463       int havesib;
15464       int havebase;
15465       int haveindex;
15466       int needindex;
15467       int base, rbase;
15468       int vindex = 0;
15469       int scale = 0;
15470       int addr32flag = !((sizeflag & AFLAG)
15471                          || bytemode == v_bnd_mode
15472                          || bytemode == bnd_mode);
15473       const char **indexes64 = names64;
15474       const char **indexes32 = names32;
15475
15476       havesib = 0;
15477       havebase = 1;
15478       haveindex = 0;
15479       base = modrm.rm;
15480
15481       if (base == 4)
15482         {
15483           havesib = 1;
15484           vindex = sib.index;
15485           USED_REX (REX_X);
15486           if (rex & REX_X)
15487             vindex += 8;
15488           switch (bytemode)
15489             {
15490             case vex_vsib_d_w_dq_mode:
15491             case vex_vsib_d_w_d_mode:
15492             case vex_vsib_q_w_dq_mode:
15493             case vex_vsib_q_w_d_mode:
15494               if (!need_vex)
15495                 abort ();
15496               if (vex.evex)
15497                 {
15498                   if (!vex.v)
15499                     vindex += 16;
15500                 }
15501
15502               haveindex = 1;
15503               switch (vex.length)
15504                 {
15505                 case 128:
15506                   indexes64 = indexes32 = names_xmm;
15507                   break;
15508                 case 256:
15509                   if (!vex.w
15510                       || bytemode == vex_vsib_q_w_dq_mode
15511                       || bytemode == vex_vsib_q_w_d_mode)
15512                     indexes64 = indexes32 = names_ymm;
15513                   else
15514                     indexes64 = indexes32 = names_xmm;
15515                   break;
15516                 case 512:
15517                   if (!vex.w
15518                       || bytemode == vex_vsib_q_w_dq_mode
15519                       || bytemode == vex_vsib_q_w_d_mode)
15520                     indexes64 = indexes32 = names_zmm;
15521                   else
15522                     indexes64 = indexes32 = names_ymm;
15523                   break;
15524                 default:
15525                   abort ();
15526                 }
15527               break;
15528             default:
15529               haveindex = vindex != 4;
15530               break;
15531             }
15532           scale = sib.scale;
15533           base = sib.base;
15534           codep++;
15535         }
15536       rbase = base + add;
15537
15538       switch (modrm.mod)
15539         {
15540         case 0:
15541           if (base == 5)
15542             {
15543               havebase = 0;
15544               if (address_mode == mode_64bit && !havesib)
15545                 riprel = 1;
15546               disp = get32s ();
15547             }
15548           break;
15549         case 1:
15550           FETCH_DATA (the_info, codep + 1);
15551           disp = *codep++;
15552           if ((disp & 0x80) != 0)
15553             disp -= 0x100;
15554           if (vex.evex && shift > 0)
15555             disp <<= shift;
15556           break;
15557         case 2:
15558           disp = get32s ();
15559           break;
15560         }
15561
15562       /* In 32bit mode, we need index register to tell [offset] from
15563          [eiz*1 + offset].  */
15564       needindex = (havesib
15565                    && !havebase
15566                    && !haveindex
15567                    && address_mode == mode_32bit);
15568       havedisp = (havebase
15569                   || needindex
15570                   || (havesib && (haveindex || scale != 0)));
15571
15572       if (!intel_syntax)
15573         if (modrm.mod != 0 || base == 5)
15574           {
15575             if (havedisp || riprel)
15576               print_displacement (scratchbuf, disp);
15577             else
15578               print_operand_value (scratchbuf, 1, disp);
15579             oappend (scratchbuf);
15580             if (riprel)
15581               {
15582                 set_op (disp, 1);
15583                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15584               }
15585           }
15586
15587       if ((havebase || haveindex || riprel)
15588           && (bytemode != v_bnd_mode)
15589           && (bytemode != bnd_mode))
15590         used_prefixes |= PREFIX_ADDR;
15591
15592       if (havedisp || (intel_syntax && riprel))
15593         {
15594           *obufp++ = open_char;
15595           if (intel_syntax && riprel)
15596             {
15597               set_op (disp, 1);
15598               oappend (!addr32flag ? "rip" : "eip");
15599             }
15600           *obufp = '\0';
15601           if (havebase)
15602             oappend (address_mode == mode_64bit && !addr32flag
15603                      ? names64[rbase] : names32[rbase]);
15604           if (havesib)
15605             {
15606               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15607                  print index to tell base + index from base.  */
15608               if (scale != 0
15609                   || needindex
15610                   || haveindex
15611                   || (havebase && base != ESP_REG_NUM))
15612                 {
15613                   if (!intel_syntax || havebase)
15614                     {
15615                       *obufp++ = separator_char;
15616                       *obufp = '\0';
15617                     }
15618                   if (haveindex)
15619                     oappend (address_mode == mode_64bit && !addr32flag
15620                              ? indexes64[vindex] : indexes32[vindex]);
15621                   else
15622                     oappend (address_mode == mode_64bit && !addr32flag
15623                              ? index64 : index32);
15624
15625                   *obufp++ = scale_char;
15626                   *obufp = '\0';
15627                   sprintf (scratchbuf, "%d", 1 << scale);
15628                   oappend (scratchbuf);
15629                 }
15630             }
15631           if (intel_syntax
15632               && (disp || modrm.mod != 0 || base == 5))
15633             {
15634               if (!havedisp || (bfd_signed_vma) disp >= 0)
15635                 {
15636                   *obufp++ = '+';
15637                   *obufp = '\0';
15638                 }
15639               else if (modrm.mod != 1 && disp != -disp)
15640                 {
15641                   *obufp++ = '-';
15642                   *obufp = '\0';
15643                   disp = - (bfd_signed_vma) disp;
15644                 }
15645
15646               if (havedisp)
15647                 print_displacement (scratchbuf, disp);
15648               else
15649                 print_operand_value (scratchbuf, 1, disp);
15650               oappend (scratchbuf);
15651             }
15652
15653           *obufp++ = close_char;
15654           *obufp = '\0';
15655         }
15656       else if (intel_syntax)
15657         {
15658           if (modrm.mod != 0 || base == 5)
15659             {
15660               if (!active_seg_prefix)
15661                 {
15662                   oappend (names_seg[ds_reg - es_reg]);
15663                   oappend (":");
15664                 }
15665               print_operand_value (scratchbuf, 1, disp);
15666               oappend (scratchbuf);
15667             }
15668         }
15669     }
15670   else
15671     {
15672       /* 16 bit address mode */
15673       used_prefixes |= prefixes & PREFIX_ADDR;
15674       switch (modrm.mod)
15675         {
15676         case 0:
15677           if (modrm.rm == 6)
15678             {
15679               disp = get16 ();
15680               if ((disp & 0x8000) != 0)
15681                 disp -= 0x10000;
15682             }
15683           break;
15684         case 1:
15685           FETCH_DATA (the_info, codep + 1);
15686           disp = *codep++;
15687           if ((disp & 0x80) != 0)
15688             disp -= 0x100;
15689           break;
15690         case 2:
15691           disp = get16 ();
15692           if ((disp & 0x8000) != 0)
15693             disp -= 0x10000;
15694           break;
15695         }
15696
15697       if (!intel_syntax)
15698         if (modrm.mod != 0 || modrm.rm == 6)
15699           {
15700             print_displacement (scratchbuf, disp);
15701             oappend (scratchbuf);
15702           }
15703
15704       if (modrm.mod != 0 || modrm.rm != 6)
15705         {
15706           *obufp++ = open_char;
15707           *obufp = '\0';
15708           oappend (index16[modrm.rm]);
15709           if (intel_syntax
15710               && (disp || modrm.mod != 0 || modrm.rm == 6))
15711             {
15712               if ((bfd_signed_vma) disp >= 0)
15713                 {
15714                   *obufp++ = '+';
15715                   *obufp = '\0';
15716                 }
15717               else if (modrm.mod != 1)
15718                 {
15719                   *obufp++ = '-';
15720                   *obufp = '\0';
15721                   disp = - (bfd_signed_vma) disp;
15722                 }
15723
15724               print_displacement (scratchbuf, disp);
15725               oappend (scratchbuf);
15726             }
15727
15728           *obufp++ = close_char;
15729           *obufp = '\0';
15730         }
15731       else if (intel_syntax)
15732         {
15733           if (!active_seg_prefix)
15734             {
15735               oappend (names_seg[ds_reg - es_reg]);
15736               oappend (":");
15737             }
15738           print_operand_value (scratchbuf, 1, disp & 0xffff);
15739           oappend (scratchbuf);
15740         }
15741     }
15742   if (vex.evex && vex.b
15743       && (bytemode == x_mode
15744           || bytemode == xmmq_mode
15745           || bytemode == evex_half_bcst_xmmq_mode))
15746     {
15747       if (vex.w
15748           || bytemode == xmmq_mode
15749           || bytemode == evex_half_bcst_xmmq_mode)
15750         {
15751           switch (vex.length)
15752             {
15753             case 128:
15754               oappend ("{1to2}");
15755               break;
15756             case 256:
15757               oappend ("{1to4}");
15758               break;
15759             case 512:
15760               oappend ("{1to8}");
15761               break;
15762             default:
15763               abort ();
15764             }
15765         }
15766       else
15767         {
15768           switch (vex.length)
15769             {
15770             case 128:
15771               oappend ("{1to4}");
15772               break;
15773             case 256:
15774               oappend ("{1to8}");
15775               break;
15776             case 512:
15777               oappend ("{1to16}");
15778               break;
15779             default:
15780               abort ();
15781             }
15782         }
15783     }
15784 }
15785
15786 static void
15787 OP_E (int bytemode, int sizeflag)
15788 {
15789   /* Skip mod/rm byte.  */
15790   MODRM_CHECK;
15791   codep++;
15792
15793   if (modrm.mod == 3)
15794     OP_E_register (bytemode, sizeflag);
15795   else
15796     OP_E_memory (bytemode, sizeflag);
15797 }
15798
15799 static void
15800 OP_G (int bytemode, int sizeflag)
15801 {
15802   int add = 0;
15803   USED_REX (REX_R);
15804   if (rex & REX_R)
15805     add += 8;
15806   switch (bytemode)
15807     {
15808     case b_mode:
15809       USED_REX (0);
15810       if (rex)
15811         oappend (names8rex[modrm.reg + add]);
15812       else
15813         oappend (names8[modrm.reg + add]);
15814       break;
15815     case w_mode:
15816       oappend (names16[modrm.reg + add]);
15817       break;
15818     case d_mode:
15819     case db_mode:
15820     case dw_mode:
15821       oappend (names32[modrm.reg + add]);
15822       break;
15823     case q_mode:
15824       oappend (names64[modrm.reg + add]);
15825       break;
15826     case bnd_mode:
15827       oappend (names_bnd[modrm.reg]);
15828       break;
15829     case v_mode:
15830     case dq_mode:
15831     case dqb_mode:
15832     case dqd_mode:
15833     case dqw_mode:
15834     case dqw_swap_mode:
15835       USED_REX (REX_W);
15836       if (rex & REX_W)
15837         oappend (names64[modrm.reg + add]);
15838       else
15839         {
15840           if ((sizeflag & DFLAG) || bytemode != v_mode)
15841             oappend (names32[modrm.reg + add]);
15842           else
15843             oappend (names16[modrm.reg + add]);
15844           used_prefixes |= (prefixes & PREFIX_DATA);
15845         }
15846       break;
15847     case m_mode:
15848       if (address_mode == mode_64bit)
15849         oappend (names64[modrm.reg + add]);
15850       else
15851         oappend (names32[modrm.reg + add]);
15852       break;
15853     case mask_bd_mode:
15854     case mask_mode:
15855       if ((modrm.reg + add) > 0x7)
15856         {
15857           oappend ("(bad)");
15858           return;
15859         }
15860       oappend (names_mask[modrm.reg + add]);
15861       break;
15862     default:
15863       oappend (INTERNAL_DISASSEMBLER_ERROR);
15864       break;
15865     }
15866 }
15867
15868 static bfd_vma
15869 get64 (void)
15870 {
15871   bfd_vma x;
15872 #ifdef BFD64
15873   unsigned int a;
15874   unsigned int b;
15875
15876   FETCH_DATA (the_info, codep + 8);
15877   a = *codep++ & 0xff;
15878   a |= (*codep++ & 0xff) << 8;
15879   a |= (*codep++ & 0xff) << 16;
15880   a |= (*codep++ & 0xffu) << 24;
15881   b = *codep++ & 0xff;
15882   b |= (*codep++ & 0xff) << 8;
15883   b |= (*codep++ & 0xff) << 16;
15884   b |= (*codep++ & 0xffu) << 24;
15885   x = a + ((bfd_vma) b << 32);
15886 #else
15887   abort ();
15888   x = 0;
15889 #endif
15890   return x;
15891 }
15892
15893 static bfd_signed_vma
15894 get32 (void)
15895 {
15896   bfd_signed_vma x = 0;
15897
15898   FETCH_DATA (the_info, codep + 4);
15899   x = *codep++ & (bfd_signed_vma) 0xff;
15900   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15901   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15902   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15903   return x;
15904 }
15905
15906 static bfd_signed_vma
15907 get32s (void)
15908 {
15909   bfd_signed_vma x = 0;
15910
15911   FETCH_DATA (the_info, codep + 4);
15912   x = *codep++ & (bfd_signed_vma) 0xff;
15913   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15914   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15915   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15916
15917   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15918
15919   return x;
15920 }
15921
15922 static int
15923 get16 (void)
15924 {
15925   int x = 0;
15926
15927   FETCH_DATA (the_info, codep + 2);
15928   x = *codep++ & 0xff;
15929   x |= (*codep++ & 0xff) << 8;
15930   return x;
15931 }
15932
15933 static void
15934 set_op (bfd_vma op, int riprel)
15935 {
15936   op_index[op_ad] = op_ad;
15937   if (address_mode == mode_64bit)
15938     {
15939       op_address[op_ad] = op;
15940       op_riprel[op_ad] = riprel;
15941     }
15942   else
15943     {
15944       /* Mask to get a 32-bit address.  */
15945       op_address[op_ad] = op & 0xffffffff;
15946       op_riprel[op_ad] = riprel & 0xffffffff;
15947     }
15948 }
15949
15950 static void
15951 OP_REG (int code, int sizeflag)
15952 {
15953   const char *s;
15954   int add;
15955
15956   switch (code)
15957     {
15958     case es_reg: case ss_reg: case cs_reg:
15959     case ds_reg: case fs_reg: case gs_reg:
15960       oappend (names_seg[code - es_reg]);
15961       return;
15962     }
15963
15964   USED_REX (REX_B);
15965   if (rex & REX_B)
15966     add = 8;
15967   else
15968     add = 0;
15969
15970   switch (code)
15971     {
15972     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15973     case sp_reg: case bp_reg: case si_reg: case di_reg:
15974       s = names16[code - ax_reg + add];
15975       break;
15976     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15977     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15978       USED_REX (0);
15979       if (rex)
15980         s = names8rex[code - al_reg + add];
15981       else
15982         s = names8[code - al_reg];
15983       break;
15984     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15985     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15986       if (address_mode == mode_64bit
15987           && ((sizeflag & DFLAG) || (rex & REX_W)))
15988         {
15989           s = names64[code - rAX_reg + add];
15990           break;
15991         }
15992       code += eAX_reg - rAX_reg;
15993       /* Fall through.  */
15994     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15995     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15996       USED_REX (REX_W);
15997       if (rex & REX_W)
15998         s = names64[code - eAX_reg + add];
15999       else
16000         {
16001           if (sizeflag & DFLAG)
16002             s = names32[code - eAX_reg + add];
16003           else
16004             s = names16[code - eAX_reg + add];
16005           used_prefixes |= (prefixes & PREFIX_DATA);
16006         }
16007       break;
16008     default:
16009       s = INTERNAL_DISASSEMBLER_ERROR;
16010       break;
16011     }
16012   oappend (s);
16013 }
16014
16015 static void
16016 OP_IMREG (int code, int sizeflag)
16017 {
16018   const char *s;
16019
16020   switch (code)
16021     {
16022     case indir_dx_reg:
16023       if (intel_syntax)
16024         s = "dx";
16025       else
16026         s = "(%dx)";
16027       break;
16028     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
16029     case sp_reg: case bp_reg: case si_reg: case di_reg:
16030       s = names16[code - ax_reg];
16031       break;
16032     case es_reg: case ss_reg: case cs_reg:
16033     case ds_reg: case fs_reg: case gs_reg:
16034       s = names_seg[code - es_reg];
16035       break;
16036     case al_reg: case ah_reg: case cl_reg: case ch_reg:
16037     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
16038       USED_REX (0);
16039       if (rex)
16040         s = names8rex[code - al_reg];
16041       else
16042         s = names8[code - al_reg];
16043       break;
16044     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
16045     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
16046       USED_REX (REX_W);
16047       if (rex & REX_W)
16048         s = names64[code - eAX_reg];
16049       else
16050         {
16051           if (sizeflag & DFLAG)
16052             s = names32[code - eAX_reg];
16053           else
16054             s = names16[code - eAX_reg];
16055           used_prefixes |= (prefixes & PREFIX_DATA);
16056         }
16057       break;
16058     case z_mode_ax_reg:
16059       if ((rex & REX_W) || (sizeflag & DFLAG))
16060         s = *names32;
16061       else
16062         s = *names16;
16063       if (!(rex & REX_W))
16064         used_prefixes |= (prefixes & PREFIX_DATA);
16065       break;
16066     default:
16067       s = INTERNAL_DISASSEMBLER_ERROR;
16068       break;
16069     }
16070   oappend (s);
16071 }
16072
16073 static void
16074 OP_I (int bytemode, int sizeflag)
16075 {
16076   bfd_signed_vma op;
16077   bfd_signed_vma mask = -1;
16078
16079   switch (bytemode)
16080     {
16081     case b_mode:
16082       FETCH_DATA (the_info, codep + 1);
16083       op = *codep++;
16084       mask = 0xff;
16085       break;
16086     case q_mode:
16087       if (address_mode == mode_64bit)
16088         {
16089           op = get32s ();
16090           break;
16091         }
16092       /* Fall through.  */
16093     case v_mode:
16094       USED_REX (REX_W);
16095       if (rex & REX_W)
16096         op = get32s ();
16097       else
16098         {
16099           if (sizeflag & DFLAG)
16100             {
16101               op = get32 ();
16102               mask = 0xffffffff;
16103             }
16104           else
16105             {
16106               op = get16 ();
16107               mask = 0xfffff;
16108             }
16109           used_prefixes |= (prefixes & PREFIX_DATA);
16110         }
16111       break;
16112     case w_mode:
16113       mask = 0xfffff;
16114       op = get16 ();
16115       break;
16116     case const_1_mode:
16117       if (intel_syntax)
16118         oappend ("1");
16119       return;
16120     default:
16121       oappend (INTERNAL_DISASSEMBLER_ERROR);
16122       return;
16123     }
16124
16125   op &= mask;
16126   scratchbuf[0] = '$';
16127   print_operand_value (scratchbuf + 1, 1, op);
16128   oappend_maybe_intel (scratchbuf);
16129   scratchbuf[0] = '\0';
16130 }
16131
16132 static void
16133 OP_I64 (int bytemode, int sizeflag)
16134 {
16135   bfd_signed_vma op;
16136   bfd_signed_vma mask = -1;
16137
16138   if (address_mode != mode_64bit)
16139     {
16140       OP_I (bytemode, sizeflag);
16141       return;
16142     }
16143
16144   switch (bytemode)
16145     {
16146     case b_mode:
16147       FETCH_DATA (the_info, codep + 1);
16148       op = *codep++;
16149       mask = 0xff;
16150       break;
16151     case v_mode:
16152       USED_REX (REX_W);
16153       if (rex & REX_W)
16154         op = get64 ();
16155       else
16156         {
16157           if (sizeflag & DFLAG)
16158             {
16159               op = get32 ();
16160               mask = 0xffffffff;
16161             }
16162           else
16163             {
16164               op = get16 ();
16165               mask = 0xfffff;
16166             }
16167           used_prefixes |= (prefixes & PREFIX_DATA);
16168         }
16169       break;
16170     case w_mode:
16171       mask = 0xfffff;
16172       op = get16 ();
16173       break;
16174     default:
16175       oappend (INTERNAL_DISASSEMBLER_ERROR);
16176       return;
16177     }
16178
16179   op &= mask;
16180   scratchbuf[0] = '$';
16181   print_operand_value (scratchbuf + 1, 1, op);
16182   oappend_maybe_intel (scratchbuf);
16183   scratchbuf[0] = '\0';
16184 }
16185
16186 static void
16187 OP_sI (int bytemode, int sizeflag)
16188 {
16189   bfd_signed_vma op;
16190
16191   switch (bytemode)
16192     {
16193     case b_mode:
16194     case b_T_mode:
16195       FETCH_DATA (the_info, codep + 1);
16196       op = *codep++;
16197       if ((op & 0x80) != 0)
16198         op -= 0x100;
16199       if (bytemode == b_T_mode)
16200         {
16201           if (address_mode != mode_64bit
16202               || !((sizeflag & DFLAG) || (rex & REX_W)))
16203             {
16204               /* The operand-size prefix is overridden by a REX prefix.  */
16205               if ((sizeflag & DFLAG) || (rex & REX_W))
16206                 op &= 0xffffffff;
16207               else
16208                 op &= 0xffff;
16209           }
16210         }
16211       else
16212         {
16213           if (!(rex & REX_W))
16214             {
16215               if (sizeflag & DFLAG)
16216                 op &= 0xffffffff;
16217               else
16218                 op &= 0xffff;
16219             }
16220         }
16221       break;
16222     case v_mode:
16223       /* The operand-size prefix is overridden by a REX prefix.  */
16224       if ((sizeflag & DFLAG) || (rex & REX_W))
16225         op = get32s ();
16226       else
16227         op = get16 ();
16228       break;
16229     default:
16230       oappend (INTERNAL_DISASSEMBLER_ERROR);
16231       return;
16232     }
16233
16234   scratchbuf[0] = '$';
16235   print_operand_value (scratchbuf + 1, 1, op);
16236   oappend_maybe_intel (scratchbuf);
16237 }
16238
16239 static void
16240 OP_J (int bytemode, int sizeflag)
16241 {
16242   bfd_vma disp;
16243   bfd_vma mask = -1;
16244   bfd_vma segment = 0;
16245
16246   switch (bytemode)
16247     {
16248     case b_mode:
16249       FETCH_DATA (the_info, codep + 1);
16250       disp = *codep++;
16251       if ((disp & 0x80) != 0)
16252         disp -= 0x100;
16253       break;
16254     case v_mode:
16255       if (isa64 == amd64)
16256         USED_REX (REX_W);
16257       if ((sizeflag & DFLAG)
16258           || (address_mode == mode_64bit
16259               && (isa64 != amd64 || (rex & REX_W))))
16260         disp = get32s ();
16261       else
16262         {
16263           disp = get16 ();
16264           if ((disp & 0x8000) != 0)
16265             disp -= 0x10000;
16266           /* In 16bit mode, address is wrapped around at 64k within
16267              the same segment.  Otherwise, a data16 prefix on a jump
16268              instruction means that the pc is masked to 16 bits after
16269              the displacement is added!  */
16270           mask = 0xffff;
16271           if ((prefixes & PREFIX_DATA) == 0)
16272             segment = ((start_pc + (codep - start_codep))
16273                        & ~((bfd_vma) 0xffff));
16274         }
16275       if (address_mode != mode_64bit
16276           || (isa64 == amd64 && !(rex & REX_W)))
16277         used_prefixes |= (prefixes & PREFIX_DATA);
16278       break;
16279     default:
16280       oappend (INTERNAL_DISASSEMBLER_ERROR);
16281       return;
16282     }
16283   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16284   set_op (disp, 0);
16285   print_operand_value (scratchbuf, 1, disp);
16286   oappend (scratchbuf);
16287 }
16288
16289 static void
16290 OP_SEG (int bytemode, int sizeflag)
16291 {
16292   if (bytemode == w_mode)
16293     oappend (names_seg[modrm.reg]);
16294   else
16295     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16296 }
16297
16298 static void
16299 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16300 {
16301   int seg, offset;
16302
16303   if (sizeflag & DFLAG)
16304     {
16305       offset = get32 ();
16306       seg = get16 ();
16307     }
16308   else
16309     {
16310       offset = get16 ();
16311       seg = get16 ();
16312     }
16313   used_prefixes |= (prefixes & PREFIX_DATA);
16314   if (intel_syntax)
16315     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16316   else
16317     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16318   oappend (scratchbuf);
16319 }
16320
16321 static void
16322 OP_OFF (int bytemode, int sizeflag)
16323 {
16324   bfd_vma off;
16325
16326   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16327     intel_operand_size (bytemode, sizeflag);
16328   append_seg ();
16329
16330   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16331     off = get32 ();
16332   else
16333     off = get16 ();
16334
16335   if (intel_syntax)
16336     {
16337       if (!active_seg_prefix)
16338         {
16339           oappend (names_seg[ds_reg - es_reg]);
16340           oappend (":");
16341         }
16342     }
16343   print_operand_value (scratchbuf, 1, off);
16344   oappend (scratchbuf);
16345 }
16346
16347 static void
16348 OP_OFF64 (int bytemode, int sizeflag)
16349 {
16350   bfd_vma off;
16351
16352   if (address_mode != mode_64bit
16353       || (prefixes & PREFIX_ADDR))
16354     {
16355       OP_OFF (bytemode, sizeflag);
16356       return;
16357     }
16358
16359   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16360     intel_operand_size (bytemode, sizeflag);
16361   append_seg ();
16362
16363   off = get64 ();
16364
16365   if (intel_syntax)
16366     {
16367       if (!active_seg_prefix)
16368         {
16369           oappend (names_seg[ds_reg - es_reg]);
16370           oappend (":");
16371         }
16372     }
16373   print_operand_value (scratchbuf, 1, off);
16374   oappend (scratchbuf);
16375 }
16376
16377 static void
16378 ptr_reg (int code, int sizeflag)
16379 {
16380   const char *s;
16381
16382   *obufp++ = open_char;
16383   used_prefixes |= (prefixes & PREFIX_ADDR);
16384   if (address_mode == mode_64bit)
16385     {
16386       if (!(sizeflag & AFLAG))
16387         s = names32[code - eAX_reg];
16388       else
16389         s = names64[code - eAX_reg];
16390     }
16391   else if (sizeflag & AFLAG)
16392     s = names32[code - eAX_reg];
16393   else
16394     s = names16[code - eAX_reg];
16395   oappend (s);
16396   *obufp++ = close_char;
16397   *obufp = 0;
16398 }
16399
16400 static void
16401 OP_ESreg (int code, int sizeflag)
16402 {
16403   if (intel_syntax)
16404     {
16405       switch (codep[-1])
16406         {
16407         case 0x6d:      /* insw/insl */
16408           intel_operand_size (z_mode, sizeflag);
16409           break;
16410         case 0xa5:      /* movsw/movsl/movsq */
16411         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16412         case 0xab:      /* stosw/stosl */
16413         case 0xaf:      /* scasw/scasl */
16414           intel_operand_size (v_mode, sizeflag);
16415           break;
16416         default:
16417           intel_operand_size (b_mode, sizeflag);
16418         }
16419     }
16420   oappend_maybe_intel ("%es:");
16421   ptr_reg (code, sizeflag);
16422 }
16423
16424 static void
16425 OP_DSreg (int code, int sizeflag)
16426 {
16427   if (intel_syntax)
16428     {
16429       switch (codep[-1])
16430         {
16431         case 0x6f:      /* outsw/outsl */
16432           intel_operand_size (z_mode, sizeflag);
16433           break;
16434         case 0xa5:      /* movsw/movsl/movsq */
16435         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16436         case 0xad:      /* lodsw/lodsl/lodsq */
16437           intel_operand_size (v_mode, sizeflag);
16438           break;
16439         default:
16440           intel_operand_size (b_mode, sizeflag);
16441         }
16442     }
16443   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16444      default segment register DS is printed.  */
16445   if (!active_seg_prefix)
16446     active_seg_prefix = PREFIX_DS;
16447   append_seg ();
16448   ptr_reg (code, sizeflag);
16449 }
16450
16451 static void
16452 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16453 {
16454   int add;
16455   if (rex & REX_R)
16456     {
16457       USED_REX (REX_R);
16458       add = 8;
16459     }
16460   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16461     {
16462       all_prefixes[last_lock_prefix] = 0;
16463       used_prefixes |= PREFIX_LOCK;
16464       add = 8;
16465     }
16466   else
16467     add = 0;
16468   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16469   oappend_maybe_intel (scratchbuf);
16470 }
16471
16472 static void
16473 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16474 {
16475   int add;
16476   USED_REX (REX_R);
16477   if (rex & REX_R)
16478     add = 8;
16479   else
16480     add = 0;
16481   if (intel_syntax)
16482     sprintf (scratchbuf, "db%d", modrm.reg + add);
16483   else
16484     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16485   oappend (scratchbuf);
16486 }
16487
16488 static void
16489 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16490 {
16491   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16492   oappend_maybe_intel (scratchbuf);
16493 }
16494
16495 static void
16496 OP_R (int bytemode, int sizeflag)
16497 {
16498   /* Skip mod/rm byte.  */
16499   MODRM_CHECK;
16500   codep++;
16501   OP_E_register (bytemode, sizeflag);
16502 }
16503
16504 static void
16505 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16506 {
16507   int reg = modrm.reg;
16508   const char **names;
16509
16510   used_prefixes |= (prefixes & PREFIX_DATA);
16511   if (prefixes & PREFIX_DATA)
16512     {
16513       names = names_xmm;
16514       USED_REX (REX_R);
16515       if (rex & REX_R)
16516         reg += 8;
16517     }
16518   else
16519     names = names_mm;
16520   oappend (names[reg]);
16521 }
16522
16523 static void
16524 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16525 {
16526   int reg = modrm.reg;
16527   const char **names;
16528
16529   USED_REX (REX_R);
16530   if (rex & REX_R)
16531     reg += 8;
16532   if (vex.evex)
16533     {
16534       if (!vex.r)
16535         reg += 16;
16536     }
16537
16538   if (need_vex
16539       && bytemode != xmm_mode
16540       && bytemode != xmmq_mode
16541       && bytemode != evex_half_bcst_xmmq_mode
16542       && bytemode != ymm_mode
16543       && bytemode != scalar_mode)
16544     {
16545       switch (vex.length)
16546         {
16547         case 128:
16548           names = names_xmm;
16549           break;
16550         case 256:
16551           if (vex.w
16552               || (bytemode != vex_vsib_q_w_dq_mode
16553                   && bytemode != vex_vsib_q_w_d_mode))
16554             names = names_ymm;
16555           else
16556             names = names_xmm;
16557           break;
16558         case 512:
16559           names = names_zmm;
16560           break;
16561         default:
16562           abort ();
16563         }
16564     }
16565   else if (bytemode == xmmq_mode
16566            || bytemode == evex_half_bcst_xmmq_mode)
16567     {
16568       switch (vex.length)
16569         {
16570         case 128:
16571         case 256:
16572           names = names_xmm;
16573           break;
16574         case 512:
16575           names = names_ymm;
16576           break;
16577         default:
16578           abort ();
16579         }
16580     }
16581   else if (bytemode == ymm_mode)
16582     names = names_ymm;
16583   else
16584     names = names_xmm;
16585   oappend (names[reg]);
16586 }
16587
16588 static void
16589 OP_EM (int bytemode, int sizeflag)
16590 {
16591   int reg;
16592   const char **names;
16593
16594   if (modrm.mod != 3)
16595     {
16596       if (intel_syntax
16597           && (bytemode == v_mode || bytemode == v_swap_mode))
16598         {
16599           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16600           used_prefixes |= (prefixes & PREFIX_DATA);
16601         }
16602       OP_E (bytemode, sizeflag);
16603       return;
16604     }
16605
16606   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16607     swap_operand ();
16608
16609   /* Skip mod/rm byte.  */
16610   MODRM_CHECK;
16611   codep++;
16612   used_prefixes |= (prefixes & PREFIX_DATA);
16613   reg = modrm.rm;
16614   if (prefixes & PREFIX_DATA)
16615     {
16616       names = names_xmm;
16617       USED_REX (REX_B);
16618       if (rex & REX_B)
16619         reg += 8;
16620     }
16621   else
16622     names = names_mm;
16623   oappend (names[reg]);
16624 }
16625
16626 /* cvt* are the only instructions in sse2 which have
16627    both SSE and MMX operands and also have 0x66 prefix
16628    in their opcode. 0x66 was originally used to differentiate
16629    between SSE and MMX instruction(operands). So we have to handle the
16630    cvt* separately using OP_EMC and OP_MXC */
16631 static void
16632 OP_EMC (int bytemode, int sizeflag)
16633 {
16634   if (modrm.mod != 3)
16635     {
16636       if (intel_syntax && bytemode == v_mode)
16637         {
16638           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16639           used_prefixes |= (prefixes & PREFIX_DATA);
16640         }
16641       OP_E (bytemode, sizeflag);
16642       return;
16643     }
16644
16645   /* Skip mod/rm byte.  */
16646   MODRM_CHECK;
16647   codep++;
16648   used_prefixes |= (prefixes & PREFIX_DATA);
16649   oappend (names_mm[modrm.rm]);
16650 }
16651
16652 static void
16653 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16654 {
16655   used_prefixes |= (prefixes & PREFIX_DATA);
16656   oappend (names_mm[modrm.reg]);
16657 }
16658
16659 static void
16660 OP_EX (int bytemode, int sizeflag)
16661 {
16662   int reg;
16663   const char **names;
16664
16665   /* Skip mod/rm byte.  */
16666   MODRM_CHECK;
16667   codep++;
16668
16669   if (modrm.mod != 3)
16670     {
16671       OP_E_memory (bytemode, sizeflag);
16672       return;
16673     }
16674
16675   reg = modrm.rm;
16676   USED_REX (REX_B);
16677   if (rex & REX_B)
16678     reg += 8;
16679   if (vex.evex)
16680     {
16681       USED_REX (REX_X);
16682       if ((rex & REX_X))
16683         reg += 16;
16684     }
16685
16686   if ((sizeflag & SUFFIX_ALWAYS)
16687       && (bytemode == x_swap_mode
16688           || bytemode == d_swap_mode
16689           || bytemode == dqw_swap_mode
16690           || bytemode == d_scalar_swap_mode
16691           || bytemode == q_swap_mode
16692           || bytemode == q_scalar_swap_mode))
16693     swap_operand ();
16694
16695   if (need_vex
16696       && bytemode != xmm_mode
16697       && bytemode != xmmdw_mode
16698       && bytemode != xmmqd_mode
16699       && bytemode != xmm_mb_mode
16700       && bytemode != xmm_mw_mode
16701       && bytemode != xmm_md_mode
16702       && bytemode != xmm_mq_mode
16703       && bytemode != xmm_mdq_mode
16704       && bytemode != xmmq_mode
16705       && bytemode != evex_half_bcst_xmmq_mode
16706       && bytemode != ymm_mode
16707       && bytemode != d_scalar_mode
16708       && bytemode != d_scalar_swap_mode
16709       && bytemode != q_scalar_mode
16710       && bytemode != q_scalar_swap_mode
16711       && bytemode != vex_scalar_w_dq_mode)
16712     {
16713       switch (vex.length)
16714         {
16715         case 128:
16716           names = names_xmm;
16717           break;
16718         case 256:
16719           names = names_ymm;
16720           break;
16721         case 512:
16722           names = names_zmm;
16723           break;
16724         default:
16725           abort ();
16726         }
16727     }
16728   else if (bytemode == xmmq_mode
16729            || bytemode == evex_half_bcst_xmmq_mode)
16730     {
16731       switch (vex.length)
16732         {
16733         case 128:
16734         case 256:
16735           names = names_xmm;
16736           break;
16737         case 512:
16738           names = names_ymm;
16739           break;
16740         default:
16741           abort ();
16742         }
16743     }
16744   else if (bytemode == ymm_mode)
16745     names = names_ymm;
16746   else
16747     names = names_xmm;
16748   oappend (names[reg]);
16749 }
16750
16751 static void
16752 OP_MS (int bytemode, int sizeflag)
16753 {
16754   if (modrm.mod == 3)
16755     OP_EM (bytemode, sizeflag);
16756   else
16757     BadOp ();
16758 }
16759
16760 static void
16761 OP_XS (int bytemode, int sizeflag)
16762 {
16763   if (modrm.mod == 3)
16764     OP_EX (bytemode, sizeflag);
16765   else
16766     BadOp ();
16767 }
16768
16769 static void
16770 OP_M (int bytemode, int sizeflag)
16771 {
16772   if (modrm.mod == 3)
16773     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16774     BadOp ();
16775   else
16776     OP_E (bytemode, sizeflag);
16777 }
16778
16779 static void
16780 OP_0f07 (int bytemode, int sizeflag)
16781 {
16782   if (modrm.mod != 3 || modrm.rm != 0)
16783     BadOp ();
16784   else
16785     OP_E (bytemode, sizeflag);
16786 }
16787
16788 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16789    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16790
16791 static void
16792 NOP_Fixup1 (int bytemode, int sizeflag)
16793 {
16794   if ((prefixes & PREFIX_DATA) != 0
16795       || (rex != 0
16796           && rex != 0x48
16797           && address_mode == mode_64bit))
16798     OP_REG (bytemode, sizeflag);
16799   else
16800     strcpy (obuf, "nop");
16801 }
16802
16803 static void
16804 NOP_Fixup2 (int bytemode, int sizeflag)
16805 {
16806   if ((prefixes & PREFIX_DATA) != 0
16807       || (rex != 0
16808           && rex != 0x48
16809           && address_mode == mode_64bit))
16810     OP_IMREG (bytemode, sizeflag);
16811 }
16812
16813 static const char *const Suffix3DNow[] = {
16814 /* 00 */        NULL,           NULL,           NULL,           NULL,
16815 /* 04 */        NULL,           NULL,           NULL,           NULL,
16816 /* 08 */        NULL,           NULL,           NULL,           NULL,
16817 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16818 /* 10 */        NULL,           NULL,           NULL,           NULL,
16819 /* 14 */        NULL,           NULL,           NULL,           NULL,
16820 /* 18 */        NULL,           NULL,           NULL,           NULL,
16821 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16822 /* 20 */        NULL,           NULL,           NULL,           NULL,
16823 /* 24 */        NULL,           NULL,           NULL,           NULL,
16824 /* 28 */        NULL,           NULL,           NULL,           NULL,
16825 /* 2C */        NULL,           NULL,           NULL,           NULL,
16826 /* 30 */        NULL,           NULL,           NULL,           NULL,
16827 /* 34 */        NULL,           NULL,           NULL,           NULL,
16828 /* 38 */        NULL,           NULL,           NULL,           NULL,
16829 /* 3C */        NULL,           NULL,           NULL,           NULL,
16830 /* 40 */        NULL,           NULL,           NULL,           NULL,
16831 /* 44 */        NULL,           NULL,           NULL,           NULL,
16832 /* 48 */        NULL,           NULL,           NULL,           NULL,
16833 /* 4C */        NULL,           NULL,           NULL,           NULL,
16834 /* 50 */        NULL,           NULL,           NULL,           NULL,
16835 /* 54 */        NULL,           NULL,           NULL,           NULL,
16836 /* 58 */        NULL,           NULL,           NULL,           NULL,
16837 /* 5C */        NULL,           NULL,           NULL,           NULL,
16838 /* 60 */        NULL,           NULL,           NULL,           NULL,
16839 /* 64 */        NULL,           NULL,           NULL,           NULL,
16840 /* 68 */        NULL,           NULL,           NULL,           NULL,
16841 /* 6C */        NULL,           NULL,           NULL,           NULL,
16842 /* 70 */        NULL,           NULL,           NULL,           NULL,
16843 /* 74 */        NULL,           NULL,           NULL,           NULL,
16844 /* 78 */        NULL,           NULL,           NULL,           NULL,
16845 /* 7C */        NULL,           NULL,           NULL,           NULL,
16846 /* 80 */        NULL,           NULL,           NULL,           NULL,
16847 /* 84 */        NULL,           NULL,           NULL,           NULL,
16848 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16849 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16850 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16851 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16852 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16853 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16854 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16855 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16856 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16857 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16858 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16859 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16860 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16861 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16862 /* C0 */        NULL,           NULL,           NULL,           NULL,
16863 /* C4 */        NULL,           NULL,           NULL,           NULL,
16864 /* C8 */        NULL,           NULL,           NULL,           NULL,
16865 /* CC */        NULL,           NULL,           NULL,           NULL,
16866 /* D0 */        NULL,           NULL,           NULL,           NULL,
16867 /* D4 */        NULL,           NULL,           NULL,           NULL,
16868 /* D8 */        NULL,           NULL,           NULL,           NULL,
16869 /* DC */        NULL,           NULL,           NULL,           NULL,
16870 /* E0 */        NULL,           NULL,           NULL,           NULL,
16871 /* E4 */        NULL,           NULL,           NULL,           NULL,
16872 /* E8 */        NULL,           NULL,           NULL,           NULL,
16873 /* EC */        NULL,           NULL,           NULL,           NULL,
16874 /* F0 */        NULL,           NULL,           NULL,           NULL,
16875 /* F4 */        NULL,           NULL,           NULL,           NULL,
16876 /* F8 */        NULL,           NULL,           NULL,           NULL,
16877 /* FC */        NULL,           NULL,           NULL,           NULL,
16878 };
16879
16880 static void
16881 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16882 {
16883   const char *mnemonic;
16884
16885   FETCH_DATA (the_info, codep + 1);
16886   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16887      place where an 8-bit immediate would normally go.  ie. the last
16888      byte of the instruction.  */
16889   obufp = mnemonicendp;
16890   mnemonic = Suffix3DNow[*codep++ & 0xff];
16891   if (mnemonic)
16892     oappend (mnemonic);
16893   else
16894     {
16895       /* Since a variable sized modrm/sib chunk is between the start
16896          of the opcode (0x0f0f) and the opcode suffix, we need to do
16897          all the modrm processing first, and don't know until now that
16898          we have a bad opcode.  This necessitates some cleaning up.  */
16899       op_out[0][0] = '\0';
16900       op_out[1][0] = '\0';
16901       BadOp ();
16902     }
16903   mnemonicendp = obufp;
16904 }
16905
16906 static struct op simd_cmp_op[] =
16907 {
16908   { STRING_COMMA_LEN ("eq") },
16909   { STRING_COMMA_LEN ("lt") },
16910   { STRING_COMMA_LEN ("le") },
16911   { STRING_COMMA_LEN ("unord") },
16912   { STRING_COMMA_LEN ("neq") },
16913   { STRING_COMMA_LEN ("nlt") },
16914   { STRING_COMMA_LEN ("nle") },
16915   { STRING_COMMA_LEN ("ord") }
16916 };
16917
16918 static void
16919 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16920 {
16921   unsigned int cmp_type;
16922
16923   FETCH_DATA (the_info, codep + 1);
16924   cmp_type = *codep++ & 0xff;
16925   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16926     {
16927       char suffix [3];
16928       char *p = mnemonicendp - 2;
16929       suffix[0] = p[0];
16930       suffix[1] = p[1];
16931       suffix[2] = '\0';
16932       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16933       mnemonicendp += simd_cmp_op[cmp_type].len;
16934     }
16935   else
16936     {
16937       /* We have a reserved extension byte.  Output it directly.  */
16938       scratchbuf[0] = '$';
16939       print_operand_value (scratchbuf + 1, 1, cmp_type);
16940       oappend_maybe_intel (scratchbuf);
16941       scratchbuf[0] = '\0';
16942     }
16943 }
16944
16945 static void
16946 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16947           int sizeflag ATTRIBUTE_UNUSED)
16948 {
16949   /* mwaitx %eax,%ecx,%ebx */
16950   if (!intel_syntax)
16951     {
16952       const char **names = (address_mode == mode_64bit
16953                             ? names64 : names32);
16954       strcpy (op_out[0], names[0]);
16955       strcpy (op_out[1], names[1]);
16956       strcpy (op_out[2], names[3]);
16957       two_source_ops = 1;
16958     }
16959   /* Skip mod/rm byte.  */
16960   MODRM_CHECK;
16961   codep++;
16962 }
16963
16964 static void
16965 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16966           int sizeflag ATTRIBUTE_UNUSED)
16967 {
16968   /* mwait %eax,%ecx  */
16969   if (!intel_syntax)
16970     {
16971       const char **names = (address_mode == mode_64bit
16972                             ? names64 : names32);
16973       strcpy (op_out[0], names[0]);
16974       strcpy (op_out[1], names[1]);
16975       two_source_ops = 1;
16976     }
16977   /* Skip mod/rm byte.  */
16978   MODRM_CHECK;
16979   codep++;
16980 }
16981
16982 static void
16983 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16984             int sizeflag ATTRIBUTE_UNUSED)
16985 {
16986   /* monitor %eax,%ecx,%edx"  */
16987   if (!intel_syntax)
16988     {
16989       const char **op1_names;
16990       const char **names = (address_mode == mode_64bit
16991                             ? names64 : names32);
16992
16993       if (!(prefixes & PREFIX_ADDR))
16994         op1_names = (address_mode == mode_16bit
16995                      ? names16 : names);
16996       else
16997         {
16998           /* Remove "addr16/addr32".  */
16999           all_prefixes[last_addr_prefix] = 0;
17000           op1_names = (address_mode != mode_32bit
17001                        ? names32 : names16);
17002           used_prefixes |= PREFIX_ADDR;
17003         }
17004       strcpy (op_out[0], op1_names[0]);
17005       strcpy (op_out[1], names[1]);
17006       strcpy (op_out[2], names[2]);
17007       two_source_ops = 1;
17008     }
17009   /* Skip mod/rm byte.  */
17010   MODRM_CHECK;
17011   codep++;
17012 }
17013
17014 static void
17015 BadOp (void)
17016 {
17017   /* Throw away prefixes and 1st. opcode byte.  */
17018   codep = insn_codep + 1;
17019   oappend ("(bad)");
17020 }
17021
17022 static void
17023 REP_Fixup (int bytemode, int sizeflag)
17024 {
17025   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
17026      lods and stos.  */
17027   if (prefixes & PREFIX_REPZ)
17028     all_prefixes[last_repz_prefix] = REP_PREFIX;
17029
17030   switch (bytemode)
17031     {
17032     case al_reg:
17033     case eAX_reg:
17034     case indir_dx_reg:
17035       OP_IMREG (bytemode, sizeflag);
17036       break;
17037     case eDI_reg:
17038       OP_ESreg (bytemode, sizeflag);
17039       break;
17040     case eSI_reg:
17041       OP_DSreg (bytemode, sizeflag);
17042       break;
17043     default:
17044       abort ();
17045       break;
17046     }
17047 }
17048
17049 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
17050    "bnd".  */
17051
17052 static void
17053 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17054 {
17055   if (prefixes & PREFIX_REPNZ)
17056     all_prefixes[last_repnz_prefix] = BND_PREFIX;
17057 }
17058
17059 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
17060    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
17061  */
17062
17063 static void
17064 HLE_Fixup1 (int bytemode, int sizeflag)
17065 {
17066   if (modrm.mod != 3
17067       && (prefixes & PREFIX_LOCK) != 0)
17068     {
17069       if (prefixes & PREFIX_REPZ)
17070         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17071       if (prefixes & PREFIX_REPNZ)
17072         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17073     }
17074
17075   OP_E (bytemode, sizeflag);
17076 }
17077
17078 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
17079    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
17080  */
17081
17082 static void
17083 HLE_Fixup2 (int bytemode, int sizeflag)
17084 {
17085   if (modrm.mod != 3)
17086     {
17087       if (prefixes & PREFIX_REPZ)
17088         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17089       if (prefixes & PREFIX_REPNZ)
17090         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17091     }
17092
17093   OP_E (bytemode, sizeflag);
17094 }
17095
17096 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
17097    "xrelease" for memory operand.  No check for LOCK prefix.   */
17098
17099 static void
17100 HLE_Fixup3 (int bytemode, int sizeflag)
17101 {
17102   if (modrm.mod != 3
17103       && last_repz_prefix > last_repnz_prefix
17104       && (prefixes & PREFIX_REPZ) != 0)
17105     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17106
17107   OP_E (bytemode, sizeflag);
17108 }
17109
17110 static void
17111 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
17112 {
17113   USED_REX (REX_W);
17114   if (rex & REX_W)
17115     {
17116       /* Change cmpxchg8b to cmpxchg16b.  */
17117       char *p = mnemonicendp - 2;
17118       mnemonicendp = stpcpy (p, "16b");
17119       bytemode = o_mode;
17120     }
17121   else if ((prefixes & PREFIX_LOCK) != 0)
17122     {
17123       if (prefixes & PREFIX_REPZ)
17124         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17125       if (prefixes & PREFIX_REPNZ)
17126         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17127     }
17128
17129   OP_M (bytemode, sizeflag);
17130 }
17131
17132 static void
17133 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
17134 {
17135   const char **names;
17136
17137   if (need_vex)
17138     {
17139       switch (vex.length)
17140         {
17141         case 128:
17142           names = names_xmm;
17143           break;
17144         case 256:
17145           names = names_ymm;
17146           break;
17147         default:
17148           abort ();
17149         }
17150     }
17151   else
17152     names = names_xmm;
17153   oappend (names[reg]);
17154 }
17155
17156 static void
17157 CRC32_Fixup (int bytemode, int sizeflag)
17158 {
17159   /* Add proper suffix to "crc32".  */
17160   char *p = mnemonicendp;
17161
17162   switch (bytemode)
17163     {
17164     case b_mode:
17165       if (intel_syntax)
17166         goto skip;
17167
17168       *p++ = 'b';
17169       break;
17170     case v_mode:
17171       if (intel_syntax)
17172         goto skip;
17173
17174       USED_REX (REX_W);
17175       if (rex & REX_W)
17176         *p++ = 'q';
17177       else
17178         {
17179           if (sizeflag & DFLAG)
17180             *p++ = 'l';
17181           else
17182             *p++ = 'w';
17183           used_prefixes |= (prefixes & PREFIX_DATA);
17184         }
17185       break;
17186     default:
17187       oappend (INTERNAL_DISASSEMBLER_ERROR);
17188       break;
17189     }
17190   mnemonicendp = p;
17191   *p = '\0';
17192
17193 skip:
17194   if (modrm.mod == 3)
17195     {
17196       int add;
17197
17198       /* Skip mod/rm byte.  */
17199       MODRM_CHECK;
17200       codep++;
17201
17202       USED_REX (REX_B);
17203       add = (rex & REX_B) ? 8 : 0;
17204       if (bytemode == b_mode)
17205         {
17206           USED_REX (0);
17207           if (rex)
17208             oappend (names8rex[modrm.rm + add]);
17209           else
17210             oappend (names8[modrm.rm + add]);
17211         }
17212       else
17213         {
17214           USED_REX (REX_W);
17215           if (rex & REX_W)
17216             oappend (names64[modrm.rm + add]);
17217           else if ((prefixes & PREFIX_DATA))
17218             oappend (names16[modrm.rm + add]);
17219           else
17220             oappend (names32[modrm.rm + add]);
17221         }
17222     }
17223   else
17224     OP_E (bytemode, sizeflag);
17225 }
17226
17227 static void
17228 FXSAVE_Fixup (int bytemode, int sizeflag)
17229 {
17230   /* Add proper suffix to "fxsave" and "fxrstor".  */
17231   USED_REX (REX_W);
17232   if (rex & REX_W)
17233     {
17234       char *p = mnemonicendp;
17235       *p++ = '6';
17236       *p++ = '4';
17237       *p = '\0';
17238       mnemonicendp = p;
17239     }
17240   OP_M (bytemode, sizeflag);
17241 }
17242
17243 /* Display the destination register operand for instructions with
17244    VEX. */
17245
17246 static void
17247 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17248 {
17249   int reg;
17250   const char **names;
17251
17252   if (!need_vex)
17253     abort ();
17254
17255   if (!need_vex_reg)
17256     return;
17257
17258   reg = vex.register_specifier;
17259   if (vex.evex)
17260     {
17261       if (!vex.v)
17262         reg += 16;
17263     }
17264
17265   if (bytemode == vex_scalar_mode)
17266     {
17267       oappend (names_xmm[reg]);
17268       return;
17269     }
17270
17271   switch (vex.length)
17272     {
17273     case 128:
17274       switch (bytemode)
17275         {
17276         case vex_mode:
17277         case vex128_mode:
17278         case vex_vsib_q_w_dq_mode:
17279         case vex_vsib_q_w_d_mode:
17280           names = names_xmm;
17281           break;
17282         case dq_mode:
17283           if (vex.w)
17284             names = names64;
17285           else
17286             names = names32;
17287           break;
17288         case mask_bd_mode:
17289         case mask_mode:
17290           if (reg > 0x7)
17291             {
17292               oappend ("(bad)");
17293               return;
17294             }
17295           names = names_mask;
17296           break;
17297         default:
17298           abort ();
17299           return;
17300         }
17301       break;
17302     case 256:
17303       switch (bytemode)
17304         {
17305         case vex_mode:
17306         case vex256_mode:
17307           names = names_ymm;
17308           break;
17309         case vex_vsib_q_w_dq_mode:
17310         case vex_vsib_q_w_d_mode:
17311           names = vex.w ? names_ymm : names_xmm;
17312           break;
17313         case mask_bd_mode:
17314         case mask_mode:
17315           if (reg > 0x7)
17316             {
17317               oappend ("(bad)");
17318               return;
17319             }
17320           names = names_mask;
17321           break;
17322         default:
17323           abort ();
17324           return;
17325         }
17326       break;
17327     case 512:
17328       names = names_zmm;
17329       break;
17330     default:
17331       abort ();
17332       break;
17333     }
17334   oappend (names[reg]);
17335 }
17336
17337 /* Get the VEX immediate byte without moving codep.  */
17338
17339 static unsigned char
17340 get_vex_imm8 (int sizeflag, int opnum)
17341 {
17342   int bytes_before_imm = 0;
17343
17344   if (modrm.mod != 3)
17345     {
17346       /* There are SIB/displacement bytes.  */
17347       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17348         {
17349           /* 32/64 bit address mode */
17350           int base = modrm.rm;
17351
17352           /* Check SIB byte.  */
17353           if (base == 4)
17354             {
17355               FETCH_DATA (the_info, codep + 1);
17356               base = *codep & 7;
17357               /* When decoding the third source, don't increase
17358                  bytes_before_imm as this has already been incremented
17359                  by one in OP_E_memory while decoding the second
17360                  source operand.  */
17361               if (opnum == 0)
17362                 bytes_before_imm++;
17363             }
17364
17365           /* Don't increase bytes_before_imm when decoding the third source,
17366              it has already been incremented by OP_E_memory while decoding
17367              the second source operand.  */
17368           if (opnum == 0)
17369             {
17370               switch (modrm.mod)
17371                 {
17372                   case 0:
17373                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17374                        SIB == 5, there is a 4 byte displacement.  */
17375                     if (base != 5)
17376                       /* No displacement. */
17377                       break;
17378                     /* Fall through.  */
17379                   case 2:
17380                     /* 4 byte displacement.  */
17381                     bytes_before_imm += 4;
17382                     break;
17383                   case 1:
17384                     /* 1 byte displacement.  */
17385                     bytes_before_imm++;
17386                     break;
17387                 }
17388             }
17389         }
17390       else
17391         {
17392           /* 16 bit address mode */
17393           /* Don't increase bytes_before_imm when decoding the third source,
17394              it has already been incremented by OP_E_memory while decoding
17395              the second source operand.  */
17396           if (opnum == 0)
17397             {
17398               switch (modrm.mod)
17399                 {
17400                 case 0:
17401                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17402                   if (modrm.rm != 6)
17403                     /* No displacement. */
17404                     break;
17405                   /* Fall through.  */
17406                 case 2:
17407                   /* 2 byte displacement.  */
17408                   bytes_before_imm += 2;
17409                   break;
17410                 case 1:
17411                   /* 1 byte displacement: when decoding the third source,
17412                      don't increase bytes_before_imm as this has already
17413                      been incremented by one in OP_E_memory while decoding
17414                      the second source operand.  */
17415                   if (opnum == 0)
17416                     bytes_before_imm++;
17417
17418                   break;
17419                 }
17420             }
17421         }
17422     }
17423
17424   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17425   return codep [bytes_before_imm];
17426 }
17427
17428 static void
17429 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17430 {
17431   const char **names;
17432
17433   if (reg == -1 && modrm.mod != 3)
17434     {
17435       OP_E_memory (bytemode, sizeflag);
17436       return;
17437     }
17438   else
17439     {
17440       if (reg == -1)
17441         {
17442           reg = modrm.rm;
17443           USED_REX (REX_B);
17444           if (rex & REX_B)
17445             reg += 8;
17446         }
17447       else if (reg > 7 && address_mode != mode_64bit)
17448         BadOp ();
17449     }
17450
17451   switch (vex.length)
17452     {
17453     case 128:
17454       names = names_xmm;
17455       break;
17456     case 256:
17457       names = names_ymm;
17458       break;
17459     default:
17460       abort ();
17461     }
17462   oappend (names[reg]);
17463 }
17464
17465 static void
17466 OP_EX_VexImmW (int bytemode, int sizeflag)
17467 {
17468   int reg = -1;
17469   static unsigned char vex_imm8;
17470
17471   if (vex_w_done == 0)
17472     {
17473       vex_w_done = 1;
17474
17475       /* Skip mod/rm byte.  */
17476       MODRM_CHECK;
17477       codep++;
17478
17479       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17480
17481       if (vex.w)
17482           reg = vex_imm8 >> 4;
17483
17484       OP_EX_VexReg (bytemode, sizeflag, reg);
17485     }
17486   else if (vex_w_done == 1)
17487     {
17488       vex_w_done = 2;
17489
17490       if (!vex.w)
17491           reg = vex_imm8 >> 4;
17492
17493       OP_EX_VexReg (bytemode, sizeflag, reg);
17494     }
17495   else
17496     {
17497       /* Output the imm8 directly.  */
17498       scratchbuf[0] = '$';
17499       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17500       oappend_maybe_intel (scratchbuf);
17501       scratchbuf[0] = '\0';
17502       codep++;
17503     }
17504 }
17505
17506 static void
17507 OP_Vex_2src (int bytemode, int sizeflag)
17508 {
17509   if (modrm.mod == 3)
17510     {
17511       int reg = modrm.rm;
17512       USED_REX (REX_B);
17513       if (rex & REX_B)
17514         reg += 8;
17515       oappend (names_xmm[reg]);
17516     }
17517   else
17518     {
17519       if (intel_syntax
17520           && (bytemode == v_mode || bytemode == v_swap_mode))
17521         {
17522           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17523           used_prefixes |= (prefixes & PREFIX_DATA);
17524         }
17525       OP_E (bytemode, sizeflag);
17526     }
17527 }
17528
17529 static void
17530 OP_Vex_2src_1 (int bytemode, int sizeflag)
17531 {
17532   if (modrm.mod == 3)
17533     {
17534       /* Skip mod/rm byte.   */
17535       MODRM_CHECK;
17536       codep++;
17537     }
17538
17539   if (vex.w)
17540     oappend (names_xmm[vex.register_specifier]);
17541   else
17542     OP_Vex_2src (bytemode, sizeflag);
17543 }
17544
17545 static void
17546 OP_Vex_2src_2 (int bytemode, int sizeflag)
17547 {
17548   if (vex.w)
17549     OP_Vex_2src (bytemode, sizeflag);
17550   else
17551     oappend (names_xmm[vex.register_specifier]);
17552 }
17553
17554 static void
17555 OP_EX_VexW (int bytemode, int sizeflag)
17556 {
17557   int reg = -1;
17558
17559   if (!vex_w_done)
17560     {
17561       vex_w_done = 1;
17562
17563       /* Skip mod/rm byte.  */
17564       MODRM_CHECK;
17565       codep++;
17566
17567       if (vex.w)
17568         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17569     }
17570   else
17571     {
17572       if (!vex.w)
17573         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17574     }
17575
17576   OP_EX_VexReg (bytemode, sizeflag, reg);
17577 }
17578
17579 static void
17580 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17581              int sizeflag ATTRIBUTE_UNUSED)
17582 {
17583   /* Skip the immediate byte and check for invalid bits.  */
17584   FETCH_DATA (the_info, codep + 1);
17585   if (*codep++ & 0xf)
17586     BadOp ();
17587 }
17588
17589 static void
17590 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17591 {
17592   int reg;
17593   const char **names;
17594
17595   FETCH_DATA (the_info, codep + 1);
17596   reg = *codep++;
17597
17598   if (bytemode != x_mode)
17599     abort ();
17600
17601   if (reg & 0xf)
17602       BadOp ();
17603
17604   reg >>= 4;
17605   if (reg > 7 && address_mode != mode_64bit)
17606     BadOp ();
17607
17608   switch (vex.length)
17609     {
17610     case 128:
17611       names = names_xmm;
17612       break;
17613     case 256:
17614       names = names_ymm;
17615       break;
17616     default:
17617       abort ();
17618     }
17619   oappend (names[reg]);
17620 }
17621
17622 static void
17623 OP_XMM_VexW (int bytemode, int sizeflag)
17624 {
17625   /* Turn off the REX.W bit since it is used for swapping operands
17626      now.  */
17627   rex &= ~REX_W;
17628   OP_XMM (bytemode, sizeflag);
17629 }
17630
17631 static void
17632 OP_EX_Vex (int bytemode, int sizeflag)
17633 {
17634   if (modrm.mod != 3)
17635     {
17636       if (vex.register_specifier != 0)
17637         BadOp ();
17638       need_vex_reg = 0;
17639     }
17640   OP_EX (bytemode, sizeflag);
17641 }
17642
17643 static void
17644 OP_XMM_Vex (int bytemode, int sizeflag)
17645 {
17646   if (modrm.mod != 3)
17647     {
17648       if (vex.register_specifier != 0)
17649         BadOp ();
17650       need_vex_reg = 0;
17651     }
17652   OP_XMM (bytemode, sizeflag);
17653 }
17654
17655 static void
17656 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17657 {
17658   switch (vex.length)
17659     {
17660     case 128:
17661       mnemonicendp = stpcpy (obuf, "vzeroupper");
17662       break;
17663     case 256:
17664       mnemonicendp = stpcpy (obuf, "vzeroall");
17665       break;
17666     default:
17667       abort ();
17668     }
17669 }
17670
17671 static struct op vex_cmp_op[] =
17672 {
17673   { STRING_COMMA_LEN ("eq") },
17674   { STRING_COMMA_LEN ("lt") },
17675   { STRING_COMMA_LEN ("le") },
17676   { STRING_COMMA_LEN ("unord") },
17677   { STRING_COMMA_LEN ("neq") },
17678   { STRING_COMMA_LEN ("nlt") },
17679   { STRING_COMMA_LEN ("nle") },
17680   { STRING_COMMA_LEN ("ord") },
17681   { STRING_COMMA_LEN ("eq_uq") },
17682   { STRING_COMMA_LEN ("nge") },
17683   { STRING_COMMA_LEN ("ngt") },
17684   { STRING_COMMA_LEN ("false") },
17685   { STRING_COMMA_LEN ("neq_oq") },
17686   { STRING_COMMA_LEN ("ge") },
17687   { STRING_COMMA_LEN ("gt") },
17688   { STRING_COMMA_LEN ("true") },
17689   { STRING_COMMA_LEN ("eq_os") },
17690   { STRING_COMMA_LEN ("lt_oq") },
17691   { STRING_COMMA_LEN ("le_oq") },
17692   { STRING_COMMA_LEN ("unord_s") },
17693   { STRING_COMMA_LEN ("neq_us") },
17694   { STRING_COMMA_LEN ("nlt_uq") },
17695   { STRING_COMMA_LEN ("nle_uq") },
17696   { STRING_COMMA_LEN ("ord_s") },
17697   { STRING_COMMA_LEN ("eq_us") },
17698   { STRING_COMMA_LEN ("nge_uq") },
17699   { STRING_COMMA_LEN ("ngt_uq") },
17700   { STRING_COMMA_LEN ("false_os") },
17701   { STRING_COMMA_LEN ("neq_os") },
17702   { STRING_COMMA_LEN ("ge_oq") },
17703   { STRING_COMMA_LEN ("gt_oq") },
17704   { STRING_COMMA_LEN ("true_us") },
17705 };
17706
17707 static void
17708 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17709 {
17710   unsigned int cmp_type;
17711
17712   FETCH_DATA (the_info, codep + 1);
17713   cmp_type = *codep++ & 0xff;
17714   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17715     {
17716       char suffix [3];
17717       char *p = mnemonicendp - 2;
17718       suffix[0] = p[0];
17719       suffix[1] = p[1];
17720       suffix[2] = '\0';
17721       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17722       mnemonicendp += vex_cmp_op[cmp_type].len;
17723     }
17724   else
17725     {
17726       /* We have a reserved extension byte.  Output it directly.  */
17727       scratchbuf[0] = '$';
17728       print_operand_value (scratchbuf + 1, 1, cmp_type);
17729       oappend_maybe_intel (scratchbuf);
17730       scratchbuf[0] = '\0';
17731     }
17732 }
17733
17734 static void
17735 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17736              int sizeflag ATTRIBUTE_UNUSED)
17737 {
17738   unsigned int cmp_type;
17739
17740   if (!vex.evex)
17741     abort ();
17742
17743   FETCH_DATA (the_info, codep + 1);
17744   cmp_type = *codep++ & 0xff;
17745   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17746      If it's the case, print suffix, otherwise - print the immediate.  */
17747   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17748       && cmp_type != 3
17749       && cmp_type != 7)
17750     {
17751       char suffix [3];
17752       char *p = mnemonicendp - 2;
17753
17754       /* vpcmp* can have both one- and two-lettered suffix.  */
17755       if (p[0] == 'p')
17756         {
17757           p++;
17758           suffix[0] = p[0];
17759           suffix[1] = '\0';
17760         }
17761       else
17762         {
17763           suffix[0] = p[0];
17764           suffix[1] = p[1];
17765           suffix[2] = '\0';
17766         }
17767
17768       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17769       mnemonicendp += simd_cmp_op[cmp_type].len;
17770     }
17771   else
17772     {
17773       /* We have a reserved extension byte.  Output it directly.  */
17774       scratchbuf[0] = '$';
17775       print_operand_value (scratchbuf + 1, 1, cmp_type);
17776       oappend_maybe_intel (scratchbuf);
17777       scratchbuf[0] = '\0';
17778     }
17779 }
17780
17781 static const struct op pclmul_op[] =
17782 {
17783   { STRING_COMMA_LEN ("lql") },
17784   { STRING_COMMA_LEN ("hql") },
17785   { STRING_COMMA_LEN ("lqh") },
17786   { STRING_COMMA_LEN ("hqh") }
17787 };
17788
17789 static void
17790 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17791               int sizeflag ATTRIBUTE_UNUSED)
17792 {
17793   unsigned int pclmul_type;
17794
17795   FETCH_DATA (the_info, codep + 1);
17796   pclmul_type = *codep++ & 0xff;
17797   switch (pclmul_type)
17798     {
17799     case 0x10:
17800       pclmul_type = 2;
17801       break;
17802     case 0x11:
17803       pclmul_type = 3;
17804       break;
17805     default:
17806       break;
17807     }
17808   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17809     {
17810       char suffix [4];
17811       char *p = mnemonicendp - 3;
17812       suffix[0] = p[0];
17813       suffix[1] = p[1];
17814       suffix[2] = p[2];
17815       suffix[3] = '\0';
17816       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17817       mnemonicendp += pclmul_op[pclmul_type].len;
17818     }
17819   else
17820     {
17821       /* We have a reserved extension byte.  Output it directly.  */
17822       scratchbuf[0] = '$';
17823       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17824       oappend_maybe_intel (scratchbuf);
17825       scratchbuf[0] = '\0';
17826     }
17827 }
17828
17829 static void
17830 MOVBE_Fixup (int bytemode, int sizeflag)
17831 {
17832   /* Add proper suffix to "movbe".  */
17833   char *p = mnemonicendp;
17834
17835   switch (bytemode)
17836     {
17837     case v_mode:
17838       if (intel_syntax)
17839         goto skip;
17840
17841       USED_REX (REX_W);
17842       if (sizeflag & SUFFIX_ALWAYS)
17843         {
17844           if (rex & REX_W)
17845             *p++ = 'q';
17846           else
17847             {
17848               if (sizeflag & DFLAG)
17849                 *p++ = 'l';
17850               else
17851                 *p++ = 'w';
17852               used_prefixes |= (prefixes & PREFIX_DATA);
17853             }
17854         }
17855       break;
17856     default:
17857       oappend (INTERNAL_DISASSEMBLER_ERROR);
17858       break;
17859     }
17860   mnemonicendp = p;
17861   *p = '\0';
17862
17863 skip:
17864   OP_M (bytemode, sizeflag);
17865 }
17866
17867 static void
17868 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17869 {
17870   int reg;
17871   const char **names;
17872
17873   /* Skip mod/rm byte.  */
17874   MODRM_CHECK;
17875   codep++;
17876
17877   if (vex.w)
17878     names = names64;
17879   else
17880     names = names32;
17881
17882   reg = modrm.rm;
17883   USED_REX (REX_B);
17884   if (rex & REX_B)
17885     reg += 8;
17886
17887   oappend (names[reg]);
17888 }
17889
17890 static void
17891 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17892 {
17893   const char **names;
17894
17895   if (vex.w)
17896     names = names64;
17897   else
17898     names = names32;
17899
17900   oappend (names[vex.register_specifier]);
17901 }
17902
17903 static void
17904 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17905 {
17906   if (!vex.evex
17907       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17908     abort ();
17909
17910   USED_REX (REX_R);
17911   if ((rex & REX_R) != 0 || !vex.r)
17912     {
17913       BadOp ();
17914       return;
17915     }
17916
17917   oappend (names_mask [modrm.reg]);
17918 }
17919
17920 static void
17921 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17922 {
17923   if (!vex.evex
17924       || (bytemode != evex_rounding_mode
17925           && bytemode != evex_sae_mode))
17926     abort ();
17927   if (modrm.mod == 3 && vex.b)
17928     switch (bytemode)
17929       {
17930       case evex_rounding_mode:
17931         oappend (names_rounding[vex.ll]);
17932         break;
17933       case evex_sae_mode:
17934         oappend ("{sae}");
17935         break;
17936       default:
17937         break;
17938       }
17939 }