opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2017 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Ev_bnd { OP_E, v_bnd_mode }
 253 #define EvS { OP_E, v_swap_mode }
 254 #define Ed { OP_E, d_mode }
 255 #define Edq { OP_E, dq_mode }
 256 #define Edqw { OP_E, dqw_mode }
 257 #define Edqb { OP_E, dqb_mode }
 258 #define Edb { OP_E, db_mode }
 259 #define Edw { OP_E, dw_mode }
 260 #define Edqd { OP_E, dqd_mode }
 261 #define Eq { OP_E, q_mode }
 262 #define indirEv { OP_indirE, indir_v_mode }
 263 #define indirEp { OP_indirE, f_mode }
 264 #define stackEv { OP_E, stack_v_mode }
 265 #define Em { OP_E, m_mode }
 266 #define Ew { OP_E, w_mode }
 267 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 268 #define Ma { OP_M, a_mode }
 269 #define Mb { OP_M, b_mode }
 270 #define Md { OP_M, d_mode }
 271 #define Mo { OP_M, o_mode }
 272 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 273 #define Mq { OP_M, q_mode }
 274 #define Mx { OP_M, x_mode }
 275 #define Mxmm { OP_M, xmm_mode }
 276 #define Gb { OP_G, b_mode }
 277 #define Gbnd { OP_G, bnd_mode }
 278 #define Gv { OP_G, v_mode }
 279 #define Gd { OP_G, d_mode }
 280 #define Gdq { OP_G, dq_mode }
 281 #define Gm { OP_G, m_mode }
 282 #define Gw { OP_G, w_mode }
 283 #define Rd { OP_R, d_mode }
 284 #define Rdq { OP_R, dq_mode }
 285 #define Rm { OP_R, m_mode }
 286 #define Ib { OP_I, b_mode }
 287 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 288 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 289 #define Iv { OP_I, v_mode }
 290 #define sIv { OP_sI, v_mode }
 291 #define Iq { OP_I, q_mode }
 292 #define Iv64 { OP_I64, v_mode }
 293 #define Iw { OP_I, w_mode }
 294 #define I1 { OP_I, const_1_mode }
 295 #define Jb { OP_J, b_mode }
 296 #define Jv { OP_J, v_mode }
 297 #define Cm { OP_C, m_mode }
 298 #define Dm { OP_D, m_mode }
 299 #define Td { OP_T, d_mode }
 300 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 301
 302 #define RMeAX { OP_REG, eAX_reg }
 303 #define RMeBX { OP_REG, eBX_reg }
 304 #define RMeCX { OP_REG, eCX_reg }
 305 #define RMeDX { OP_REG, eDX_reg }
 306 #define RMeSP { OP_REG, eSP_reg }
 307 #define RMeBP { OP_REG, eBP_reg }
 308 #define RMeSI { OP_REG, eSI_reg }
 309 #define RMeDI { OP_REG, eDI_reg }
 310 #define RMrAX { OP_REG, rAX_reg }
 311 #define RMrBX { OP_REG, rBX_reg }
 312 #define RMrCX { OP_REG, rCX_reg }
 313 #define RMrDX { OP_REG, rDX_reg }
 314 #define RMrSP { OP_REG, rSP_reg }
 315 #define RMrBP { OP_REG, rBP_reg }
 316 #define RMrSI { OP_REG, rSI_reg }
 317 #define RMrDI { OP_REG, rDI_reg }
 318 #define RMAL { OP_REG, al_reg }
 319 #define RMCL { OP_REG, cl_reg }
 320 #define RMDL { OP_REG, dl_reg }
 321 #define RMBL { OP_REG, bl_reg }
 322 #define RMAH { OP_REG, ah_reg }
 323 #define RMCH { OP_REG, ch_reg }
 324 #define RMDH { OP_REG, dh_reg }
 325 #define RMBH { OP_REG, bh_reg }
 326 #define RMAX { OP_REG, ax_reg }
 327 #define RMDX { OP_REG, dx_reg }
 328
 329 #define eAX { OP_IMREG, eAX_reg }
 330 #define eBX { OP_IMREG, eBX_reg }
 331 #define eCX { OP_IMREG, eCX_reg }
 332 #define eDX { OP_IMREG, eDX_reg }
 333 #define eSP { OP_IMREG, eSP_reg }
 334 #define eBP { OP_IMREG, eBP_reg }
 335 #define eSI { OP_IMREG, eSI_reg }
 336 #define eDI { OP_IMREG, eDI_reg }
 337 #define AL { OP_IMREG, al_reg }
 338 #define CL { OP_IMREG, cl_reg }
 339 #define DL { OP_IMREG, dl_reg }
 340 #define BL { OP_IMREG, bl_reg }
 341 #define AH { OP_IMREG, ah_reg }
 342 #define CH { OP_IMREG, ch_reg }
 343 #define DH { OP_IMREG, dh_reg }
 344 #define BH { OP_IMREG, bh_reg }
 345 #define AX { OP_IMREG, ax_reg }
 346 #define DX { OP_IMREG, dx_reg }
 347 #define zAX { OP_IMREG, z_mode_ax_reg }
 348 #define indirDX { OP_IMREG, indir_dx_reg }
 349
 350 #define Sw { OP_SEG, w_mode }
 351 #define Sv { OP_SEG, v_mode }
 352 #define Ap { OP_DIR, 0 }
 353 #define Ob { OP_OFF64, b_mode }
 354 #define Ov { OP_OFF64, v_mode }
 355 #define Xb { OP_DSreg, eSI_reg }
 356 #define Xv { OP_DSreg, eSI_reg }
 357 #define Xz { OP_DSreg, eSI_reg }
 358 #define Yb { OP_ESreg, eDI_reg }
 359 #define Yv { OP_ESreg, eDI_reg }
 360 #define DSBX { OP_DSreg, eBX_reg }
 361
 362 #define es { OP_REG, es_reg }
 363 #define ss { OP_REG, ss_reg }
 364 #define cs { OP_REG, cs_reg }
 365 #define ds { OP_REG, ds_reg }
 366 #define fs { OP_REG, fs_reg }
 367 #define gs { OP_REG, gs_reg }
 368
 369 #define MX { OP_MMX, 0 }
 370 #define XM { OP_XMM, 0 }
 371 #define XMScalar { OP_XMM, scalar_mode }
 372 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 373 #define XMM { OP_XMM, xmm_mode }
 374 #define XMxmmq { OP_XMM, xmmq_mode }
 375 #define EM { OP_EM, v_mode }
 376 #define EMS { OP_EM, v_swap_mode }
 377 #define EMd { OP_EM, d_mode }
 378 #define EMx { OP_EM, x_mode }
 379 #define EXbScalar { OP_EX, b_scalar_mode }
 380 #define EXw { OP_EX, w_mode }
 381 #define EXwScalar { OP_EX, w_scalar_mode }
 382 #define EXd { OP_EX, d_mode }
 383 #define EXdScalar { OP_EX, d_scalar_mode }
 384 #define EXdS { OP_EX, d_swap_mode }
 385 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 386 #define EXq { OP_EX, q_mode }
 387 #define EXqScalar { OP_EX, q_scalar_mode }
 388 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 389 #define EXqS { OP_EX, q_swap_mode }
 390 #define EXx { OP_EX, x_mode }
 391 #define EXxS { OP_EX, x_swap_mode }
 392 #define EXxmm { OP_EX, xmm_mode }
 393 #define EXymm { OP_EX, ymm_mode }
 394 #define EXxmmq { OP_EX, xmmq_mode }
 395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 398 #define EXxmm_md { OP_EX, xmm_md_mode }
 399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 400 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 401 #define EXxmmdw { OP_EX, xmmdw_mode }
 402 #define EXxmmqd { OP_EX, xmmqd_mode }
 403 #define EXymmq { OP_EX, ymmq_mode }
 404 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 405 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 406 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 407 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 408 #define MS { OP_MS, v_mode }
 409 #define XS { OP_XS, v_mode }
 410 #define EMCq { OP_EMC, q_mode }
 411 #define MXC { OP_MXC, 0 }
 412 #define OPSUF { OP_3DNowSuffix, 0 }
 413 #define CMP { CMP_Fixup, 0 }
 414 #define XMM0 { XMM_Fixup, 0 }
 415 #define FXSAVE { FXSAVE_Fixup, 0 }
 416 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 417 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 418
 419 #define Vex { OP_VEX, vex_mode }
 420 #define VexScalar { OP_VEX, vex_scalar_mode }
 421 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 422 #define Vex128 { OP_VEX, vex128_mode }
 423 #define Vex256 { OP_VEX, vex256_mode }
 424 #define VexGdq { OP_VEX, dq_mode }
 425 #define VexI4 { VEXI4_Fixup, 0}
 426 #define EXdVex { OP_EX_Vex, d_mode }
 427 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 428 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 429 #define EXqVex { OP_EX_Vex, q_mode }
 430 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 431 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 432 #define EXVexW { OP_EX_VexW, x_mode }
 433 #define EXdVexW { OP_EX_VexW, d_mode }
 434 #define EXqVexW { OP_EX_VexW, q_mode }
 435 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 436 #define XMVex { OP_XMM_Vex, 0 }
 437 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 438 #define XMVexW { OP_XMM_VexW, 0 }
 439 #define XMVexI4 { OP_REG_VexI4, x_mode }
 440 #define PCLMUL { PCLMUL_Fixup, 0 }
 441 #define VZERO { VZERO_Fixup, 0 }
 442 #define VCMP { VCMP_Fixup, 0 }
 443 #define VPCMP { VPCMP_Fixup, 0 }
 444
 445 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 446 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 447
 448 #define XMask { OP_Mask, mask_mode }
 449 #define MaskG { OP_G, mask_mode }
 450 #define MaskE { OP_E, mask_mode }
 451 #define MaskBDE { OP_E, mask_bd_mode }
 452 #define MaskR { OP_R, mask_mode }
 453 #define MaskVex { OP_VEX, mask_mode }
 454
 455 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 456 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 457 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 458 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 459
 460 /* Used handle "rep" prefix for string instructions.  */
 461 #define Xbr { REP_Fixup, eSI_reg }
 462 #define Xvr { REP_Fixup, eSI_reg }
 463 #define Ybr { REP_Fixup, eDI_reg }
 464 #define Yvr { REP_Fixup, eDI_reg }
 465 #define Yzr { REP_Fixup, eDI_reg }
 466 #define indirDXr { REP_Fixup, indir_dx_reg }
 467 #define ALr { REP_Fixup, al_reg }
 468 #define eAXr { REP_Fixup, eAX_reg }
 469
 470 /* Used handle HLE prefix for lockable instructions.  */
 471 #define Ebh1 { HLE_Fixup1, b_mode }
 472 #define Evh1 { HLE_Fixup1, v_mode }
 473 #define Ebh2 { HLE_Fixup2, b_mode }
 474 #define Evh2 { HLE_Fixup2, v_mode }
 475 #define Ebh3 { HLE_Fixup3, b_mode }
 476 #define Evh3 { HLE_Fixup3, v_mode }
 477
 478 #define BND { BND_Fixup, 0 }
 479 #define NOTRACK { NOTRACK_Fixup, 0 }
 480
 481 #define cond_jump_flag { NULL, cond_jump_mode }
 482 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 483
 484 /* bits in sizeflag */
 485 #define SUFFIX_ALWAYS 4
 486 #define AFLAG 2
 487 #define DFLAG 1
 488
 489 enum
 490 {
 491   /* byte operand */
 492   b_mode = 1,
 493   /* byte operand with operand swapped */
 494   b_swap_mode,
 495   /* byte operand, sign extend like 'T' suffix */
 496   b_T_mode,
 497   /* operand size depends on prefixes */
 498   v_mode,
 499   /* operand size depends on prefixes with operand swapped */
 500   v_swap_mode,
 501   /* word operand */
 502   w_mode,
 503   /* double word operand  */
 504   d_mode,
 505   /* double word operand with operand swapped */
 506   d_swap_mode,
 507   /* quad word operand */
 508   q_mode,
 509   /* quad word operand with operand swapped */
 510   q_swap_mode,
 511   /* ten-byte operand */
 512   t_mode,
 513   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 514      broadcast enabled.  */
 515   x_mode,
 516   /* Similar to x_mode, but with different EVEX mem shifts.  */
 517   evex_x_gscat_mode,
 518   /* Similar to x_mode, but with disabled broadcast.  */
 519   evex_x_nobcst_mode,
 520   /* Similar to x_mode, but with operands swapped and disabled broadcast
 521      in EVEX.  */
 522   x_swap_mode,
 523   /* 16-byte XMM operand */
 524   xmm_mode,
 525   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 526      memory operand (depending on vector length).  Broadcast isn't
 527      allowed.  */
 528   xmmq_mode,
 529   /* Same as xmmq_mode, but broadcast is allowed.  */
 530   evex_half_bcst_xmmq_mode,
 531   /* XMM register or byte memory operand */
 532   xmm_mb_mode,
 533   /* XMM register or word memory operand */
 534   xmm_mw_mode,
 535   /* XMM register or double word memory operand */
 536   xmm_md_mode,
 537   /* XMM register or quad word memory operand */
 538   xmm_mq_mode,
 539   /* XMM register or double/quad word memory operand, depending on
 540      VEX.W.  */
 541   xmm_mdq_mode,
 542   /* 16-byte XMM, word, double word or quad word operand.  */
 543   xmmdw_mode,
 544   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 545   xmmqd_mode,
 546   /* 32-byte YMM operand */
 547   ymm_mode,
 548   /* quad word, ymmword or zmmword memory operand.  */
 549   ymmq_mode,
 550   /* 32-byte YMM or 16-byte word operand */
 551   ymmxmm_mode,
 552   /* d_mode in 32bit, q_mode in 64bit mode.  */
 553   m_mode,
 554   /* pair of v_mode operands */
 555   a_mode,
 556   cond_jump_mode,
 557   loop_jcxz_mode,
 558   v_bnd_mode,
 559   /* operand size depends on REX prefixes.  */
 560   dq_mode,
 561   /* registers like dq_mode, memory like w_mode.  */
 562   dqw_mode,
 563   bnd_mode,
 564   /* 4- or 6-byte pointer operand */
 565   f_mode,
 566   const_1_mode,
 567   /* v_mode for indirect branch opcodes.  */
 568   indir_v_mode,
 569   /* v_mode for stack-related opcodes.  */
 570   stack_v_mode,
 571   /* non-quad operand size depends on prefixes */
 572   z_mode,
 573   /* 16-byte operand */
 574   o_mode,
 575   /* registers like dq_mode, memory like b_mode.  */
 576   dqb_mode,
 577   /* registers like d_mode, memory like b_mode.  */
 578   db_mode,
 579   /* registers like d_mode, memory like w_mode.  */
 580   dw_mode,
 581   /* registers like dq_mode, memory like d_mode.  */
 582   dqd_mode,
 583   /* normal vex mode */
 584   vex_mode,
 585   /* 128bit vex mode */
 586   vex128_mode,
 587   /* 256bit vex mode */
 588   vex256_mode,
 589   /* operand size depends on the VEX.W bit.  */
 590   vex_w_dq_mode,
 591
 592   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 593   vex_vsib_d_w_dq_mode,
 594   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 595   vex_vsib_d_w_d_mode,
 596   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 597   vex_vsib_q_w_dq_mode,
 598   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 599   vex_vsib_q_w_d_mode,
 600
 601   /* scalar, ignore vector length.  */
 602   scalar_mode,
 603   /* like b_mode, ignore vector length.  */
 604   b_scalar_mode,
 605   /* like w_mode, ignore vector length.  */
 606   w_scalar_mode,
 607   /* like d_mode, ignore vector length.  */
 608   d_scalar_mode,
 609   /* like d_swap_mode, ignore vector length.  */
 610   d_scalar_swap_mode,
 611   /* like q_mode, ignore vector length.  */
 612   q_scalar_mode,
 613   /* like q_swap_mode, ignore vector length.  */
 614   q_scalar_swap_mode,
 615   /* like vex_mode, ignore vector length.  */
 616   vex_scalar_mode,
 617   /* like vex_w_dq_mode, ignore vector length.  */
 618   vex_scalar_w_dq_mode,
 619
 620   /* Static rounding.  */
 621   evex_rounding_mode,
 622   /* Supress all exceptions.  */
 623   evex_sae_mode,
 624
 625   /* Mask register operand.  */
 626   mask_mode,
 627   /* Mask register operand.  */
 628   mask_bd_mode,
 629
 630   es_reg,
 631   cs_reg,
 632   ss_reg,
 633   ds_reg,
 634   fs_reg,
 635   gs_reg,
 636
 637   eAX_reg,
 638   eCX_reg,
 639   eDX_reg,
 640   eBX_reg,
 641   eSP_reg,
 642   eBP_reg,
 643   eSI_reg,
 644   eDI_reg,
 645
 646   al_reg,
 647   cl_reg,
 648   dl_reg,
 649   bl_reg,
 650   ah_reg,
 651   ch_reg,
 652   dh_reg,
 653   bh_reg,
 654
 655   ax_reg,
 656   cx_reg,
 657   dx_reg,
 658   bx_reg,
 659   sp_reg,
 660   bp_reg,
 661   si_reg,
 662   di_reg,
 663
 664   rAX_reg,
 665   rCX_reg,
 666   rDX_reg,
 667   rBX_reg,
 668   rSP_reg,
 669   rBP_reg,
 670   rSI_reg,
 671   rDI_reg,
 672
 673   z_mode_ax_reg,
 674   indir_dx_reg
 675 };
 676
 677 enum
 678 {
 679   FLOATCODE = 1,
 680   USE_REG_TABLE,
 681   USE_MOD_TABLE,
 682   USE_RM_TABLE,
 683   USE_PREFIX_TABLE,
 684   USE_X86_64_TABLE,
 685   USE_3BYTE_TABLE,
 686   USE_XOP_8F_TABLE,
 687   USE_VEX_C4_TABLE,
 688   USE_VEX_C5_TABLE,
 689   USE_VEX_LEN_TABLE,
 690   USE_VEX_W_TABLE,
 691   USE_EVEX_TABLE
 692 };
 693
 694 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 695
 696 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 697 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 698 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 699 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 700 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 701 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 702 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 703 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 704 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 705 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 706 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 707 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 708 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 709 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 710 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 711
 712 enum
 713 {
 714   REG_80 = 0,
 715   REG_81,
 716   REG_83,
 717   REG_8F,
 718   REG_C0,
 719   REG_C1,
 720   REG_C6,
 721   REG_C7,
 722   REG_D0,
 723   REG_D1,
 724   REG_D2,
 725   REG_D3,
 726   REG_F6,
 727   REG_F7,
 728   REG_FE,
 729   REG_FF,
 730   REG_0F00,
 731   REG_0F01,
 732   REG_0F0D,
 733   REG_0F18,
 734   REG_0F1E_MOD_3,
 735   REG_0F71,
 736   REG_0F72,
 737   REG_0F73,
 738   REG_0FA6,
 739   REG_0FA7,
 740   REG_0FAE,
 741   REG_0FBA,
 742   REG_0FC7,
 743   REG_VEX_0F71,
 744   REG_VEX_0F72,
 745   REG_VEX_0F73,
 746   REG_VEX_0FAE,
 747   REG_VEX_0F38F3,
 748   REG_XOP_LWPCB,
 749   REG_XOP_LWP,
 750   REG_XOP_TBM_01,
 751   REG_XOP_TBM_02,
 752
 753   REG_EVEX_0F71,
 754   REG_EVEX_0F72,
 755   REG_EVEX_0F73,
 756   REG_EVEX_0F38C6,
 757   REG_EVEX_0F38C7
 758 };
 759
 760 enum
 761 {
 762   MOD_8D = 0,
 763   MOD_C6_REG_7,
 764   MOD_C7_REG_7,
 765   MOD_FF_REG_3,
 766   MOD_FF_REG_5,
 767   MOD_0F01_REG_0,
 768   MOD_0F01_REG_1,
 769   MOD_0F01_REG_2,
 770   MOD_0F01_REG_3,
 771   MOD_0F01_REG_5,
 772   MOD_0F01_REG_7,
 773   MOD_0F12_PREFIX_0,
 774   MOD_0F13,
 775   MOD_0F16_PREFIX_0,
 776   MOD_0F17,
 777   MOD_0F18_REG_0,
 778   MOD_0F18_REG_1,
 779   MOD_0F18_REG_2,
 780   MOD_0F18_REG_3,
 781   MOD_0F18_REG_4,
 782   MOD_0F18_REG_5,
 783   MOD_0F18_REG_6,
 784   MOD_0F18_REG_7,
 785   MOD_0F1A_PREFIX_0,
 786   MOD_0F1B_PREFIX_0,
 787   MOD_0F1B_PREFIX_1,
 788   MOD_0F1E_PREFIX_1,
 789   MOD_0F24,
 790   MOD_0F26,
 791   MOD_0F2B_PREFIX_0,
 792   MOD_0F2B_PREFIX_1,
 793   MOD_0F2B_PREFIX_2,
 794   MOD_0F2B_PREFIX_3,
 795   MOD_0F51,
 796   MOD_0F71_REG_2,
 797   MOD_0F71_REG_4,
 798   MOD_0F71_REG_6,
 799   MOD_0F72_REG_2,
 800   MOD_0F72_REG_4,
 801   MOD_0F72_REG_6,
 802   MOD_0F73_REG_2,
 803   MOD_0F73_REG_3,
 804   MOD_0F73_REG_6,
 805   MOD_0F73_REG_7,
 806   MOD_0FAE_REG_0,
 807   MOD_0FAE_REG_1,
 808   MOD_0FAE_REG_2,
 809   MOD_0FAE_REG_3,
 810   MOD_0FAE_REG_4,
 811   MOD_0FAE_REG_5,
 812   MOD_0FAE_REG_6,
 813   MOD_0FAE_REG_7,
 814   MOD_0FB2,
 815   MOD_0FB4,
 816   MOD_0FB5,
 817   MOD_0FC3,
 818   MOD_0FC7_REG_3,
 819   MOD_0FC7_REG_4,
 820   MOD_0FC7_REG_5,
 821   MOD_0FC7_REG_6,
 822   MOD_0FC7_REG_7,
 823   MOD_0FD7,
 824   MOD_0FE7_PREFIX_2,
 825   MOD_0FF0_PREFIX_3,
 826   MOD_0F382A_PREFIX_2,
 827   MOD_0F38F5_PREFIX_2,
 828   MOD_0F38F6_PREFIX_0,
 829   MOD_62_32BIT,
 830   MOD_C4_32BIT,
 831   MOD_C5_32BIT,
 832   MOD_VEX_0F12_PREFIX_0,
 833   MOD_VEX_0F13,
 834   MOD_VEX_0F16_PREFIX_0,
 835   MOD_VEX_0F17,
 836   MOD_VEX_0F2B,
 837   MOD_VEX_W_0_0F41_P_0_LEN_1,
 838   MOD_VEX_W_1_0F41_P_0_LEN_1,
 839   MOD_VEX_W_0_0F41_P_2_LEN_1,
 840   MOD_VEX_W_1_0F41_P_2_LEN_1,
 841   MOD_VEX_W_0_0F42_P_0_LEN_1,
 842   MOD_VEX_W_1_0F42_P_0_LEN_1,
 843   MOD_VEX_W_0_0F42_P_2_LEN_1,
 844   MOD_VEX_W_1_0F42_P_2_LEN_1,
 845   MOD_VEX_W_0_0F44_P_0_LEN_1,
 846   MOD_VEX_W_1_0F44_P_0_LEN_1,
 847   MOD_VEX_W_0_0F44_P_2_LEN_1,
 848   MOD_VEX_W_1_0F44_P_2_LEN_1,
 849   MOD_VEX_W_0_0F45_P_0_LEN_1,
 850   MOD_VEX_W_1_0F45_P_0_LEN_1,
 851   MOD_VEX_W_0_0F45_P_2_LEN_1,
 852   MOD_VEX_W_1_0F45_P_2_LEN_1,
 853   MOD_VEX_W_0_0F46_P_0_LEN_1,
 854   MOD_VEX_W_1_0F46_P_0_LEN_1,
 855   MOD_VEX_W_0_0F46_P_2_LEN_1,
 856   MOD_VEX_W_1_0F46_P_2_LEN_1,
 857   MOD_VEX_W_0_0F47_P_0_LEN_1,
 858   MOD_VEX_W_1_0F47_P_0_LEN_1,
 859   MOD_VEX_W_0_0F47_P_2_LEN_1,
 860   MOD_VEX_W_1_0F47_P_2_LEN_1,
 861   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 862   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 863   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 864   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 865   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 866   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 867   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 868   MOD_VEX_0F50,
 869   MOD_VEX_0F71_REG_2,
 870   MOD_VEX_0F71_REG_4,
 871   MOD_VEX_0F71_REG_6,
 872   MOD_VEX_0F72_REG_2,
 873   MOD_VEX_0F72_REG_4,
 874   MOD_VEX_0F72_REG_6,
 875   MOD_VEX_0F73_REG_2,
 876   MOD_VEX_0F73_REG_3,
 877   MOD_VEX_0F73_REG_6,
 878   MOD_VEX_0F73_REG_7,
 879   MOD_VEX_W_0_0F91_P_0_LEN_0,
 880   MOD_VEX_W_1_0F91_P_0_LEN_0,
 881   MOD_VEX_W_0_0F91_P_2_LEN_0,
 882   MOD_VEX_W_1_0F91_P_2_LEN_0,
 883   MOD_VEX_W_0_0F92_P_0_LEN_0,
 884   MOD_VEX_W_0_0F92_P_2_LEN_0,
 885   MOD_VEX_W_0_0F92_P_3_LEN_0,
 886   MOD_VEX_W_1_0F92_P_3_LEN_0,
 887   MOD_VEX_W_0_0F93_P_0_LEN_0,
 888   MOD_VEX_W_0_0F93_P_2_LEN_0,
 889   MOD_VEX_W_0_0F93_P_3_LEN_0,
 890   MOD_VEX_W_1_0F93_P_3_LEN_0,
 891   MOD_VEX_W_0_0F98_P_0_LEN_0,
 892   MOD_VEX_W_1_0F98_P_0_LEN_0,
 893   MOD_VEX_W_0_0F98_P_2_LEN_0,
 894   MOD_VEX_W_1_0F98_P_2_LEN_0,
 895   MOD_VEX_W_0_0F99_P_0_LEN_0,
 896   MOD_VEX_W_1_0F99_P_0_LEN_0,
 897   MOD_VEX_W_0_0F99_P_2_LEN_0,
 898   MOD_VEX_W_1_0F99_P_2_LEN_0,
 899   MOD_VEX_0FAE_REG_2,
 900   MOD_VEX_0FAE_REG_3,
 901   MOD_VEX_0FD7_PREFIX_2,
 902   MOD_VEX_0FE7_PREFIX_2,
 903   MOD_VEX_0FF0_PREFIX_3,
 904   MOD_VEX_0F381A_PREFIX_2,
 905   MOD_VEX_0F382A_PREFIX_2,
 906   MOD_VEX_0F382C_PREFIX_2,
 907   MOD_VEX_0F382D_PREFIX_2,
 908   MOD_VEX_0F382E_PREFIX_2,
 909   MOD_VEX_0F382F_PREFIX_2,
 910   MOD_VEX_0F385A_PREFIX_2,
 911   MOD_VEX_0F388C_PREFIX_2,
 912   MOD_VEX_0F388E_PREFIX_2,
 913   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 914   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 915   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 916   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 917   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 918   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 919   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 920   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 921
 922   MOD_EVEX_0F10_PREFIX_1,
 923   MOD_EVEX_0F10_PREFIX_3,
 924   MOD_EVEX_0F11_PREFIX_1,
 925   MOD_EVEX_0F11_PREFIX_3,
 926   MOD_EVEX_0F12_PREFIX_0,
 927   MOD_EVEX_0F16_PREFIX_0,
 928   MOD_EVEX_0F38C6_REG_1,
 929   MOD_EVEX_0F38C6_REG_2,
 930   MOD_EVEX_0F38C6_REG_5,
 931   MOD_EVEX_0F38C6_REG_6,
 932   MOD_EVEX_0F38C7_REG_1,
 933   MOD_EVEX_0F38C7_REG_2,
 934   MOD_EVEX_0F38C7_REG_5,
 935   MOD_EVEX_0F38C7_REG_6
 936 };
 937
 938 enum
 939 {
 940   RM_C6_REG_7 = 0,
 941   RM_C7_REG_7,
 942   RM_0F01_REG_0,
 943   RM_0F01_REG_1,
 944   RM_0F01_REG_2,
 945   RM_0F01_REG_3,
 946   RM_0F01_REG_5,
 947   RM_0F01_REG_7,
 948   RM_0F1E_MOD_3_REG_7,
 949   RM_0FAE_REG_6,
 950   RM_0FAE_REG_7
 951 };
 952
 953 enum
 954 {
 955   PREFIX_90 = 0,
 956   PREFIX_MOD_0_0F01_REG_5,
 957   PREFIX_MOD_3_0F01_REG_5_RM_0,
 958   PREFIX_MOD_3_0F01_REG_5_RM_2,
 959   PREFIX_0F10,
 960   PREFIX_0F11,
 961   PREFIX_0F12,
 962   PREFIX_0F16,
 963   PREFIX_0F1A,
 964   PREFIX_0F1B,
 965   PREFIX_0F1E,
 966   PREFIX_0F2A,
 967   PREFIX_0F2B,
 968   PREFIX_0F2C,
 969   PREFIX_0F2D,
 970   PREFIX_0F2E,
 971   PREFIX_0F2F,
 972   PREFIX_0F51,
 973   PREFIX_0F52,
 974   PREFIX_0F53,
 975   PREFIX_0F58,
 976   PREFIX_0F59,
 977   PREFIX_0F5A,
 978   PREFIX_0F5B,
 979   PREFIX_0F5C,
 980   PREFIX_0F5D,
 981   PREFIX_0F5E,
 982   PREFIX_0F5F,
 983   PREFIX_0F60,
 984   PREFIX_0F61,
 985   PREFIX_0F62,
 986   PREFIX_0F6C,
 987   PREFIX_0F6D,
 988   PREFIX_0F6F,
 989   PREFIX_0F70,
 990   PREFIX_0F73_REG_3,
 991   PREFIX_0F73_REG_7,
 992   PREFIX_0F78,
 993   PREFIX_0F79,
 994   PREFIX_0F7C,
 995   PREFIX_0F7D,
 996   PREFIX_0F7E,
 997   PREFIX_0F7F,
 998   PREFIX_0FAE_REG_0,
 999   PREFIX_0FAE_REG_1,
1000   PREFIX_0FAE_REG_2,
1001   PREFIX_0FAE_REG_3,
1002   PREFIX_MOD_0_0FAE_REG_4,
1003   PREFIX_MOD_3_0FAE_REG_4,
1004   PREFIX_MOD_0_0FAE_REG_5,
1005   PREFIX_MOD_3_0FAE_REG_5,
1006   PREFIX_0FAE_REG_6,
1007   PREFIX_0FAE_REG_7,
1008   PREFIX_0FB8,
1009   PREFIX_0FBC,
1010   PREFIX_0FBD,
1011   PREFIX_0FC2,
1012   PREFIX_MOD_0_0FC3,
1013   PREFIX_MOD_0_0FC7_REG_6,
1014   PREFIX_MOD_3_0FC7_REG_6,
1015   PREFIX_MOD_3_0FC7_REG_7,
1016   PREFIX_0FD0,
1017   PREFIX_0FD6,
1018   PREFIX_0FE6,
1019   PREFIX_0FE7,
1020   PREFIX_0FF0,
1021   PREFIX_0FF7,
1022   PREFIX_0F3810,
1023   PREFIX_0F3814,
1024   PREFIX_0F3815,
1025   PREFIX_0F3817,
1026   PREFIX_0F3820,
1027   PREFIX_0F3821,
1028   PREFIX_0F3822,
1029   PREFIX_0F3823,
1030   PREFIX_0F3824,
1031   PREFIX_0F3825,
1032   PREFIX_0F3828,
1033   PREFIX_0F3829,
1034   PREFIX_0F382A,
1035   PREFIX_0F382B,
1036   PREFIX_0F3830,
1037   PREFIX_0F3831,
1038   PREFIX_0F3832,
1039   PREFIX_0F3833,
1040   PREFIX_0F3834,
1041   PREFIX_0F3835,
1042   PREFIX_0F3837,
1043   PREFIX_0F3838,
1044   PREFIX_0F3839,
1045   PREFIX_0F383A,
1046   PREFIX_0F383B,
1047   PREFIX_0F383C,
1048   PREFIX_0F383D,
1049   PREFIX_0F383E,
1050   PREFIX_0F383F,
1051   PREFIX_0F3840,
1052   PREFIX_0F3841,
1053   PREFIX_0F3880,
1054   PREFIX_0F3881,
1055   PREFIX_0F3882,
1056   PREFIX_0F38C8,
1057   PREFIX_0F38C9,
1058   PREFIX_0F38CA,
1059   PREFIX_0F38CB,
1060   PREFIX_0F38CC,
1061   PREFIX_0F38CD,
1062   PREFIX_0F38CF,
1063   PREFIX_0F38DB,
1064   PREFIX_0F38DC,
1065   PREFIX_0F38DD,
1066   PREFIX_0F38DE,
1067   PREFIX_0F38DF,
1068   PREFIX_0F38F0,
1069   PREFIX_0F38F1,
1070   PREFIX_0F38F5,
1071   PREFIX_0F38F6,
1072   PREFIX_0F3A08,
1073   PREFIX_0F3A09,
1074   PREFIX_0F3A0A,
1075   PREFIX_0F3A0B,
1076   PREFIX_0F3A0C,
1077   PREFIX_0F3A0D,
1078   PREFIX_0F3A0E,
1079   PREFIX_0F3A14,
1080   PREFIX_0F3A15,
1081   PREFIX_0F3A16,
1082   PREFIX_0F3A17,
1083   PREFIX_0F3A20,
1084   PREFIX_0F3A21,
1085   PREFIX_0F3A22,
1086   PREFIX_0F3A40,
1087   PREFIX_0F3A41,
1088   PREFIX_0F3A42,
1089   PREFIX_0F3A44,
1090   PREFIX_0F3A60,
1091   PREFIX_0F3A61,
1092   PREFIX_0F3A62,
1093   PREFIX_0F3A63,
1094   PREFIX_0F3ACC,
1095   PREFIX_0F3ACE,
1096   PREFIX_0F3ACF,
1097   PREFIX_0F3ADF,
1098   PREFIX_VEX_0F10,
1099   PREFIX_VEX_0F11,
1100   PREFIX_VEX_0F12,
1101   PREFIX_VEX_0F16,
1102   PREFIX_VEX_0F2A,
1103   PREFIX_VEX_0F2C,
1104   PREFIX_VEX_0F2D,
1105   PREFIX_VEX_0F2E,
1106   PREFIX_VEX_0F2F,
1107   PREFIX_VEX_0F41,
1108   PREFIX_VEX_0F42,
1109   PREFIX_VEX_0F44,
1110   PREFIX_VEX_0F45,
1111   PREFIX_VEX_0F46,
1112   PREFIX_VEX_0F47,
1113   PREFIX_VEX_0F4A,
1114   PREFIX_VEX_0F4B,
1115   PREFIX_VEX_0F51,
1116   PREFIX_VEX_0F52,
1117   PREFIX_VEX_0F53,
1118   PREFIX_VEX_0F58,
1119   PREFIX_VEX_0F59,
1120   PREFIX_VEX_0F5A,
1121   PREFIX_VEX_0F5B,
1122   PREFIX_VEX_0F5C,
1123   PREFIX_VEX_0F5D,
1124   PREFIX_VEX_0F5E,
1125   PREFIX_VEX_0F5F,
1126   PREFIX_VEX_0F60,
1127   PREFIX_VEX_0F61,
1128   PREFIX_VEX_0F62,
1129   PREFIX_VEX_0F63,
1130   PREFIX_VEX_0F64,
1131   PREFIX_VEX_0F65,
1132   PREFIX_VEX_0F66,
1133   PREFIX_VEX_0F67,
1134   PREFIX_VEX_0F68,
1135   PREFIX_VEX_0F69,
1136   PREFIX_VEX_0F6A,
1137   PREFIX_VEX_0F6B,
1138   PREFIX_VEX_0F6C,
1139   PREFIX_VEX_0F6D,
1140   PREFIX_VEX_0F6E,
1141   PREFIX_VEX_0F6F,
1142   PREFIX_VEX_0F70,
1143   PREFIX_VEX_0F71_REG_2,
1144   PREFIX_VEX_0F71_REG_4,
1145   PREFIX_VEX_0F71_REG_6,
1146   PREFIX_VEX_0F72_REG_2,
1147   PREFIX_VEX_0F72_REG_4,
1148   PREFIX_VEX_0F72_REG_6,
1149   PREFIX_VEX_0F73_REG_2,
1150   PREFIX_VEX_0F73_REG_3,
1151   PREFIX_VEX_0F73_REG_6,
1152   PREFIX_VEX_0F73_REG_7,
1153   PREFIX_VEX_0F74,
1154   PREFIX_VEX_0F75,
1155   PREFIX_VEX_0F76,
1156   PREFIX_VEX_0F77,
1157   PREFIX_VEX_0F7C,
1158   PREFIX_VEX_0F7D,
1159   PREFIX_VEX_0F7E,
1160   PREFIX_VEX_0F7F,
1161   PREFIX_VEX_0F90,
1162   PREFIX_VEX_0F91,
1163   PREFIX_VEX_0F92,
1164   PREFIX_VEX_0F93,
1165   PREFIX_VEX_0F98,
1166   PREFIX_VEX_0F99,
1167   PREFIX_VEX_0FC2,
1168   PREFIX_VEX_0FC4,
1169   PREFIX_VEX_0FC5,
1170   PREFIX_VEX_0FD0,
1171   PREFIX_VEX_0FD1,
1172   PREFIX_VEX_0FD2,
1173   PREFIX_VEX_0FD3,
1174   PREFIX_VEX_0FD4,
1175   PREFIX_VEX_0FD5,
1176   PREFIX_VEX_0FD6,
1177   PREFIX_VEX_0FD7,
1178   PREFIX_VEX_0FD8,
1179   PREFIX_VEX_0FD9,
1180   PREFIX_VEX_0FDA,
1181   PREFIX_VEX_0FDB,
1182   PREFIX_VEX_0FDC,
1183   PREFIX_VEX_0FDD,
1184   PREFIX_VEX_0FDE,
1185   PREFIX_VEX_0FDF,
1186   PREFIX_VEX_0FE0,
1187   PREFIX_VEX_0FE1,
1188   PREFIX_VEX_0FE2,
1189   PREFIX_VEX_0FE3,
1190   PREFIX_VEX_0FE4,
1191   PREFIX_VEX_0FE5,
1192   PREFIX_VEX_0FE6,
1193   PREFIX_VEX_0FE7,
1194   PREFIX_VEX_0FE8,
1195   PREFIX_VEX_0FE9,
1196   PREFIX_VEX_0FEA,
1197   PREFIX_VEX_0FEB,
1198   PREFIX_VEX_0FEC,
1199   PREFIX_VEX_0FED,
1200   PREFIX_VEX_0FEE,
1201   PREFIX_VEX_0FEF,
1202   PREFIX_VEX_0FF0,
1203   PREFIX_VEX_0FF1,
1204   PREFIX_VEX_0FF2,
1205   PREFIX_VEX_0FF3,
1206   PREFIX_VEX_0FF4,
1207   PREFIX_VEX_0FF5,
1208   PREFIX_VEX_0FF6,
1209   PREFIX_VEX_0FF7,
1210   PREFIX_VEX_0FF8,
1211   PREFIX_VEX_0FF9,
1212   PREFIX_VEX_0FFA,
1213   PREFIX_VEX_0FFB,
1214   PREFIX_VEX_0FFC,
1215   PREFIX_VEX_0FFD,
1216   PREFIX_VEX_0FFE,
1217   PREFIX_VEX_0F3800,
1218   PREFIX_VEX_0F3801,
1219   PREFIX_VEX_0F3802,
1220   PREFIX_VEX_0F3803,
1221   PREFIX_VEX_0F3804,
1222   PREFIX_VEX_0F3805,
1223   PREFIX_VEX_0F3806,
1224   PREFIX_VEX_0F3807,
1225   PREFIX_VEX_0F3808,
1226   PREFIX_VEX_0F3809,
1227   PREFIX_VEX_0F380A,
1228   PREFIX_VEX_0F380B,
1229   PREFIX_VEX_0F380C,
1230   PREFIX_VEX_0F380D,
1231   PREFIX_VEX_0F380E,
1232   PREFIX_VEX_0F380F,
1233   PREFIX_VEX_0F3813,
1234   PREFIX_VEX_0F3816,
1235   PREFIX_VEX_0F3817,
1236   PREFIX_VEX_0F3818,
1237   PREFIX_VEX_0F3819,
1238   PREFIX_VEX_0F381A,
1239   PREFIX_VEX_0F381C,
1240   PREFIX_VEX_0F381D,
1241   PREFIX_VEX_0F381E,
1242   PREFIX_VEX_0F3820,
1243   PREFIX_VEX_0F3821,
1244   PREFIX_VEX_0F3822,
1245   PREFIX_VEX_0F3823,
1246   PREFIX_VEX_0F3824,
1247   PREFIX_VEX_0F3825,
1248   PREFIX_VEX_0F3828,
1249   PREFIX_VEX_0F3829,
1250   PREFIX_VEX_0F382A,
1251   PREFIX_VEX_0F382B,
1252   PREFIX_VEX_0F382C,
1253   PREFIX_VEX_0F382D,
1254   PREFIX_VEX_0F382E,
1255   PREFIX_VEX_0F382F,
1256   PREFIX_VEX_0F3830,
1257   PREFIX_VEX_0F3831,
1258   PREFIX_VEX_0F3832,
1259   PREFIX_VEX_0F3833,
1260   PREFIX_VEX_0F3834,
1261   PREFIX_VEX_0F3835,
1262   PREFIX_VEX_0F3836,
1263   PREFIX_VEX_0F3837,
1264   PREFIX_VEX_0F3838,
1265   PREFIX_VEX_0F3839,
1266   PREFIX_VEX_0F383A,
1267   PREFIX_VEX_0F383B,
1268   PREFIX_VEX_0F383C,
1269   PREFIX_VEX_0F383D,
1270   PREFIX_VEX_0F383E,
1271   PREFIX_VEX_0F383F,
1272   PREFIX_VEX_0F3840,
1273   PREFIX_VEX_0F3841,
1274   PREFIX_VEX_0F3845,
1275   PREFIX_VEX_0F3846,
1276   PREFIX_VEX_0F3847,
1277   PREFIX_VEX_0F3858,
1278   PREFIX_VEX_0F3859,
1279   PREFIX_VEX_0F385A,
1280   PREFIX_VEX_0F3878,
1281   PREFIX_VEX_0F3879,
1282   PREFIX_VEX_0F388C,
1283   PREFIX_VEX_0F388E,
1284   PREFIX_VEX_0F3890,
1285   PREFIX_VEX_0F3891,
1286   PREFIX_VEX_0F3892,
1287   PREFIX_VEX_0F3893,
1288   PREFIX_VEX_0F3896,
1289   PREFIX_VEX_0F3897,
1290   PREFIX_VEX_0F3898,
1291   PREFIX_VEX_0F3899,
1292   PREFIX_VEX_0F389A,
1293   PREFIX_VEX_0F389B,
1294   PREFIX_VEX_0F389C,
1295   PREFIX_VEX_0F389D,
1296   PREFIX_VEX_0F389E,
1297   PREFIX_VEX_0F389F,
1298   PREFIX_VEX_0F38A6,
1299   PREFIX_VEX_0F38A7,
1300   PREFIX_VEX_0F38A8,
1301   PREFIX_VEX_0F38A9,
1302   PREFIX_VEX_0F38AA,
1303   PREFIX_VEX_0F38AB,
1304   PREFIX_VEX_0F38AC,
1305   PREFIX_VEX_0F38AD,
1306   PREFIX_VEX_0F38AE,
1307   PREFIX_VEX_0F38AF,
1308   PREFIX_VEX_0F38B6,
1309   PREFIX_VEX_0F38B7,
1310   PREFIX_VEX_0F38B8,
1311   PREFIX_VEX_0F38B9,
1312   PREFIX_VEX_0F38BA,
1313   PREFIX_VEX_0F38BB,
1314   PREFIX_VEX_0F38BC,
1315   PREFIX_VEX_0F38BD,
1316   PREFIX_VEX_0F38BE,
1317   PREFIX_VEX_0F38BF,
1318   PREFIX_VEX_0F38CF,
1319   PREFIX_VEX_0F38DB,
1320   PREFIX_VEX_0F38DC,
1321   PREFIX_VEX_0F38DD,
1322   PREFIX_VEX_0F38DE,
1323   PREFIX_VEX_0F38DF,
1324   PREFIX_VEX_0F38F2,
1325   PREFIX_VEX_0F38F3_REG_1,
1326   PREFIX_VEX_0F38F3_REG_2,
1327   PREFIX_VEX_0F38F3_REG_3,
1328   PREFIX_VEX_0F38F5,
1329   PREFIX_VEX_0F38F6,
1330   PREFIX_VEX_0F38F7,
1331   PREFIX_VEX_0F3A00,
1332   PREFIX_VEX_0F3A01,
1333   PREFIX_VEX_0F3A02,
1334   PREFIX_VEX_0F3A04,
1335   PREFIX_VEX_0F3A05,
1336   PREFIX_VEX_0F3A06,
1337   PREFIX_VEX_0F3A08,
1338   PREFIX_VEX_0F3A09,
1339   PREFIX_VEX_0F3A0A,
1340   PREFIX_VEX_0F3A0B,
1341   PREFIX_VEX_0F3A0C,
1342   PREFIX_VEX_0F3A0D,
1343   PREFIX_VEX_0F3A0E,
1344   PREFIX_VEX_0F3A0F,
1345   PREFIX_VEX_0F3A14,
1346   PREFIX_VEX_0F3A15,
1347   PREFIX_VEX_0F3A16,
1348   PREFIX_VEX_0F3A17,
1349   PREFIX_VEX_0F3A18,
1350   PREFIX_VEX_0F3A19,
1351   PREFIX_VEX_0F3A1D,
1352   PREFIX_VEX_0F3A20,
1353   PREFIX_VEX_0F3A21,
1354   PREFIX_VEX_0F3A22,
1355   PREFIX_VEX_0F3A30,
1356   PREFIX_VEX_0F3A31,
1357   PREFIX_VEX_0F3A32,
1358   PREFIX_VEX_0F3A33,
1359   PREFIX_VEX_0F3A38,
1360   PREFIX_VEX_0F3A39,
1361   PREFIX_VEX_0F3A40,
1362   PREFIX_VEX_0F3A41,
1363   PREFIX_VEX_0F3A42,
1364   PREFIX_VEX_0F3A44,
1365   PREFIX_VEX_0F3A46,
1366   PREFIX_VEX_0F3A48,
1367   PREFIX_VEX_0F3A49,
1368   PREFIX_VEX_0F3A4A,
1369   PREFIX_VEX_0F3A4B,
1370   PREFIX_VEX_0F3A4C,
1371   PREFIX_VEX_0F3A5C,
1372   PREFIX_VEX_0F3A5D,
1373   PREFIX_VEX_0F3A5E,
1374   PREFIX_VEX_0F3A5F,
1375   PREFIX_VEX_0F3A60,
1376   PREFIX_VEX_0F3A61,
1377   PREFIX_VEX_0F3A62,
1378   PREFIX_VEX_0F3A63,
1379   PREFIX_VEX_0F3A68,
1380   PREFIX_VEX_0F3A69,
1381   PREFIX_VEX_0F3A6A,
1382   PREFIX_VEX_0F3A6B,
1383   PREFIX_VEX_0F3A6C,
1384   PREFIX_VEX_0F3A6D,
1385   PREFIX_VEX_0F3A6E,
1386   PREFIX_VEX_0F3A6F,
1387   PREFIX_VEX_0F3A78,
1388   PREFIX_VEX_0F3A79,
1389   PREFIX_VEX_0F3A7A,
1390   PREFIX_VEX_0F3A7B,
1391   PREFIX_VEX_0F3A7C,
1392   PREFIX_VEX_0F3A7D,
1393   PREFIX_VEX_0F3A7E,
1394   PREFIX_VEX_0F3A7F,
1395   PREFIX_VEX_0F3ACE,
1396   PREFIX_VEX_0F3ACF,
1397   PREFIX_VEX_0F3ADF,
1398   PREFIX_VEX_0F3AF0,
1399
1400   PREFIX_EVEX_0F10,
1401   PREFIX_EVEX_0F11,
1402   PREFIX_EVEX_0F12,
1403   PREFIX_EVEX_0F13,
1404   PREFIX_EVEX_0F14,
1405   PREFIX_EVEX_0F15,
1406   PREFIX_EVEX_0F16,
1407   PREFIX_EVEX_0F17,
1408   PREFIX_EVEX_0F28,
1409   PREFIX_EVEX_0F29,
1410   PREFIX_EVEX_0F2A,
1411   PREFIX_EVEX_0F2B,
1412   PREFIX_EVEX_0F2C,
1413   PREFIX_EVEX_0F2D,
1414   PREFIX_EVEX_0F2E,
1415   PREFIX_EVEX_0F2F,
1416   PREFIX_EVEX_0F51,
1417   PREFIX_EVEX_0F54,
1418   PREFIX_EVEX_0F55,
1419   PREFIX_EVEX_0F56,
1420   PREFIX_EVEX_0F57,
1421   PREFIX_EVEX_0F58,
1422   PREFIX_EVEX_0F59,
1423   PREFIX_EVEX_0F5A,
1424   PREFIX_EVEX_0F5B,
1425   PREFIX_EVEX_0F5C,
1426   PREFIX_EVEX_0F5D,
1427   PREFIX_EVEX_0F5E,
1428   PREFIX_EVEX_0F5F,
1429   PREFIX_EVEX_0F60,
1430   PREFIX_EVEX_0F61,
1431   PREFIX_EVEX_0F62,
1432   PREFIX_EVEX_0F63,
1433   PREFIX_EVEX_0F64,
1434   PREFIX_EVEX_0F65,
1435   PREFIX_EVEX_0F66,
1436   PREFIX_EVEX_0F67,
1437   PREFIX_EVEX_0F68,
1438   PREFIX_EVEX_0F69,
1439   PREFIX_EVEX_0F6A,
1440   PREFIX_EVEX_0F6B,
1441   PREFIX_EVEX_0F6C,
1442   PREFIX_EVEX_0F6D,
1443   PREFIX_EVEX_0F6E,
1444   PREFIX_EVEX_0F6F,
1445   PREFIX_EVEX_0F70,
1446   PREFIX_EVEX_0F71_REG_2,
1447   PREFIX_EVEX_0F71_REG_4,
1448   PREFIX_EVEX_0F71_REG_6,
1449   PREFIX_EVEX_0F72_REG_0,
1450   PREFIX_EVEX_0F72_REG_1,
1451   PREFIX_EVEX_0F72_REG_2,
1452   PREFIX_EVEX_0F72_REG_4,
1453   PREFIX_EVEX_0F72_REG_6,
1454   PREFIX_EVEX_0F73_REG_2,
1455   PREFIX_EVEX_0F73_REG_3,
1456   PREFIX_EVEX_0F73_REG_6,
1457   PREFIX_EVEX_0F73_REG_7,
1458   PREFIX_EVEX_0F74,
1459   PREFIX_EVEX_0F75,
1460   PREFIX_EVEX_0F76,
1461   PREFIX_EVEX_0F78,
1462   PREFIX_EVEX_0F79,
1463   PREFIX_EVEX_0F7A,
1464   PREFIX_EVEX_0F7B,
1465   PREFIX_EVEX_0F7E,
1466   PREFIX_EVEX_0F7F,
1467   PREFIX_EVEX_0FC2,
1468   PREFIX_EVEX_0FC4,
1469   PREFIX_EVEX_0FC5,
1470   PREFIX_EVEX_0FC6,
1471   PREFIX_EVEX_0FD1,
1472   PREFIX_EVEX_0FD2,
1473   PREFIX_EVEX_0FD3,
1474   PREFIX_EVEX_0FD4,
1475   PREFIX_EVEX_0FD5,
1476   PREFIX_EVEX_0FD6,
1477   PREFIX_EVEX_0FD8,
1478   PREFIX_EVEX_0FD9,
1479   PREFIX_EVEX_0FDA,
1480   PREFIX_EVEX_0FDB,
1481   PREFIX_EVEX_0FDC,
1482   PREFIX_EVEX_0FDD,
1483   PREFIX_EVEX_0FDE,
1484   PREFIX_EVEX_0FDF,
1485   PREFIX_EVEX_0FE0,
1486   PREFIX_EVEX_0FE1,
1487   PREFIX_EVEX_0FE2,
1488   PREFIX_EVEX_0FE3,
1489   PREFIX_EVEX_0FE4,
1490   PREFIX_EVEX_0FE5,
1491   PREFIX_EVEX_0FE6,
1492   PREFIX_EVEX_0FE7,
1493   PREFIX_EVEX_0FE8,
1494   PREFIX_EVEX_0FE9,
1495   PREFIX_EVEX_0FEA,
1496   PREFIX_EVEX_0FEB,
1497   PREFIX_EVEX_0FEC,
1498   PREFIX_EVEX_0FED,
1499   PREFIX_EVEX_0FEE,
1500   PREFIX_EVEX_0FEF,
1501   PREFIX_EVEX_0FF1,
1502   PREFIX_EVEX_0FF2,
1503   PREFIX_EVEX_0FF3,
1504   PREFIX_EVEX_0FF4,
1505   PREFIX_EVEX_0FF5,
1506   PREFIX_EVEX_0FF6,
1507   PREFIX_EVEX_0FF8,
1508   PREFIX_EVEX_0FF9,
1509   PREFIX_EVEX_0FFA,
1510   PREFIX_EVEX_0FFB,
1511   PREFIX_EVEX_0FFC,
1512   PREFIX_EVEX_0FFD,
1513   PREFIX_EVEX_0FFE,
1514   PREFIX_EVEX_0F3800,
1515   PREFIX_EVEX_0F3804,
1516   PREFIX_EVEX_0F380B,
1517   PREFIX_EVEX_0F380C,
1518   PREFIX_EVEX_0F380D,
1519   PREFIX_EVEX_0F3810,
1520   PREFIX_EVEX_0F3811,
1521   PREFIX_EVEX_0F3812,
1522   PREFIX_EVEX_0F3813,
1523   PREFIX_EVEX_0F3814,
1524   PREFIX_EVEX_0F3815,
1525   PREFIX_EVEX_0F3816,
1526   PREFIX_EVEX_0F3818,
1527   PREFIX_EVEX_0F3819,
1528   PREFIX_EVEX_0F381A,
1529   PREFIX_EVEX_0F381B,
1530   PREFIX_EVEX_0F381C,
1531   PREFIX_EVEX_0F381D,
1532   PREFIX_EVEX_0F381E,
1533   PREFIX_EVEX_0F381F,
1534   PREFIX_EVEX_0F3820,
1535   PREFIX_EVEX_0F3821,
1536   PREFIX_EVEX_0F3822,
1537   PREFIX_EVEX_0F3823,
1538   PREFIX_EVEX_0F3824,
1539   PREFIX_EVEX_0F3825,
1540   PREFIX_EVEX_0F3826,
1541   PREFIX_EVEX_0F3827,
1542   PREFIX_EVEX_0F3828,
1543   PREFIX_EVEX_0F3829,
1544   PREFIX_EVEX_0F382A,
1545   PREFIX_EVEX_0F382B,
1546   PREFIX_EVEX_0F382C,
1547   PREFIX_EVEX_0F382D,
1548   PREFIX_EVEX_0F3830,
1549   PREFIX_EVEX_0F3831,
1550   PREFIX_EVEX_0F3832,
1551   PREFIX_EVEX_0F3833,
1552   PREFIX_EVEX_0F3834,
1553   PREFIX_EVEX_0F3835,
1554   PREFIX_EVEX_0F3836,
1555   PREFIX_EVEX_0F3837,
1556   PREFIX_EVEX_0F3838,
1557   PREFIX_EVEX_0F3839,
1558   PREFIX_EVEX_0F383A,
1559   PREFIX_EVEX_0F383B,
1560   PREFIX_EVEX_0F383C,
1561   PREFIX_EVEX_0F383D,
1562   PREFIX_EVEX_0F383E,
1563   PREFIX_EVEX_0F383F,
1564   PREFIX_EVEX_0F3840,
1565   PREFIX_EVEX_0F3842,
1566   PREFIX_EVEX_0F3843,
1567   PREFIX_EVEX_0F3844,
1568   PREFIX_EVEX_0F3845,
1569   PREFIX_EVEX_0F3846,
1570   PREFIX_EVEX_0F3847,
1571   PREFIX_EVEX_0F384C,
1572   PREFIX_EVEX_0F384D,
1573   PREFIX_EVEX_0F384E,
1574   PREFIX_EVEX_0F384F,
1575   PREFIX_EVEX_0F3852,
1576   PREFIX_EVEX_0F3853,
1577   PREFIX_EVEX_0F3855,
1578   PREFIX_EVEX_0F3858,
1579   PREFIX_EVEX_0F3859,
1580   PREFIX_EVEX_0F385A,
1581   PREFIX_EVEX_0F385B,
1582   PREFIX_EVEX_0F3862,
1583   PREFIX_EVEX_0F3863,
1584   PREFIX_EVEX_0F3864,
1585   PREFIX_EVEX_0F3865,
1586   PREFIX_EVEX_0F3866,
1587   PREFIX_EVEX_0F3870,
1588   PREFIX_EVEX_0F3871,
1589   PREFIX_EVEX_0F3872,
1590   PREFIX_EVEX_0F3873,
1591   PREFIX_EVEX_0F3875,
1592   PREFIX_EVEX_0F3876,
1593   PREFIX_EVEX_0F3877,
1594   PREFIX_EVEX_0F3878,
1595   PREFIX_EVEX_0F3879,
1596   PREFIX_EVEX_0F387A,
1597   PREFIX_EVEX_0F387B,
1598   PREFIX_EVEX_0F387C,
1599   PREFIX_EVEX_0F387D,
1600   PREFIX_EVEX_0F387E,
1601   PREFIX_EVEX_0F387F,
1602   PREFIX_EVEX_0F3883,
1603   PREFIX_EVEX_0F3888,
1604   PREFIX_EVEX_0F3889,
1605   PREFIX_EVEX_0F388A,
1606   PREFIX_EVEX_0F388B,
1607   PREFIX_EVEX_0F388D,
1608   PREFIX_EVEX_0F3890,
1609   PREFIX_EVEX_0F3891,
1610   PREFIX_EVEX_0F3892,
1611   PREFIX_EVEX_0F3893,
1612   PREFIX_EVEX_0F3896,
1613   PREFIX_EVEX_0F3897,
1614   PREFIX_EVEX_0F3898,
1615   PREFIX_EVEX_0F3899,
1616   PREFIX_EVEX_0F389A,
1617   PREFIX_EVEX_0F389B,
1618   PREFIX_EVEX_0F389C,
1619   PREFIX_EVEX_0F389D,
1620   PREFIX_EVEX_0F389E,
1621   PREFIX_EVEX_0F389F,
1622   PREFIX_EVEX_0F38A0,
1623   PREFIX_EVEX_0F38A1,
1624   PREFIX_EVEX_0F38A2,
1625   PREFIX_EVEX_0F38A3,
1626   PREFIX_EVEX_0F38A6,
1627   PREFIX_EVEX_0F38A7,
1628   PREFIX_EVEX_0F38A8,
1629   PREFIX_EVEX_0F38A9,
1630   PREFIX_EVEX_0F38AA,
1631   PREFIX_EVEX_0F38AB,
1632   PREFIX_EVEX_0F38AC,
1633   PREFIX_EVEX_0F38AD,
1634   PREFIX_EVEX_0F38AE,
1635   PREFIX_EVEX_0F38AF,
1636   PREFIX_EVEX_0F38B4,
1637   PREFIX_EVEX_0F38B5,
1638   PREFIX_EVEX_0F38B6,
1639   PREFIX_EVEX_0F38B7,
1640   PREFIX_EVEX_0F38B8,
1641   PREFIX_EVEX_0F38B9,
1642   PREFIX_EVEX_0F38BA,
1643   PREFIX_EVEX_0F38BB,
1644   PREFIX_EVEX_0F38BC,
1645   PREFIX_EVEX_0F38BD,
1646   PREFIX_EVEX_0F38BE,
1647   PREFIX_EVEX_0F38BF,
1648   PREFIX_EVEX_0F38C4,
1649   PREFIX_EVEX_0F38C6_REG_1,
1650   PREFIX_EVEX_0F38C6_REG_2,
1651   PREFIX_EVEX_0F38C6_REG_5,
1652   PREFIX_EVEX_0F38C6_REG_6,
1653   PREFIX_EVEX_0F38C7_REG_1,
1654   PREFIX_EVEX_0F38C7_REG_2,
1655   PREFIX_EVEX_0F38C7_REG_5,
1656   PREFIX_EVEX_0F38C7_REG_6,
1657   PREFIX_EVEX_0F38C8,
1658   PREFIX_EVEX_0F38CA,
1659   PREFIX_EVEX_0F38CB,
1660   PREFIX_EVEX_0F38CC,
1661   PREFIX_EVEX_0F38CD,
1662   PREFIX_EVEX_0F38CF,
1663   PREFIX_EVEX_0F38DC,
1664   PREFIX_EVEX_0F38DD,
1665   PREFIX_EVEX_0F38DE,
1666   PREFIX_EVEX_0F38DF,
1667
1668   PREFIX_EVEX_0F3A00,
1669   PREFIX_EVEX_0F3A01,
1670   PREFIX_EVEX_0F3A03,
1671   PREFIX_EVEX_0F3A04,
1672   PREFIX_EVEX_0F3A05,
1673   PREFIX_EVEX_0F3A08,
1674   PREFIX_EVEX_0F3A09,
1675   PREFIX_EVEX_0F3A0A,
1676   PREFIX_EVEX_0F3A0B,
1677   PREFIX_EVEX_0F3A0F,
1678   PREFIX_EVEX_0F3A14,
1679   PREFIX_EVEX_0F3A15,
1680   PREFIX_EVEX_0F3A16,
1681   PREFIX_EVEX_0F3A17,
1682   PREFIX_EVEX_0F3A18,
1683   PREFIX_EVEX_0F3A19,
1684   PREFIX_EVEX_0F3A1A,
1685   PREFIX_EVEX_0F3A1B,
1686   PREFIX_EVEX_0F3A1D,
1687   PREFIX_EVEX_0F3A1E,
1688   PREFIX_EVEX_0F3A1F,
1689   PREFIX_EVEX_0F3A20,
1690   PREFIX_EVEX_0F3A21,
1691   PREFIX_EVEX_0F3A22,
1692   PREFIX_EVEX_0F3A23,
1693   PREFIX_EVEX_0F3A25,
1694   PREFIX_EVEX_0F3A26,
1695   PREFIX_EVEX_0F3A27,
1696   PREFIX_EVEX_0F3A38,
1697   PREFIX_EVEX_0F3A39,
1698   PREFIX_EVEX_0F3A3A,
1699   PREFIX_EVEX_0F3A3B,
1700   PREFIX_EVEX_0F3A3E,
1701   PREFIX_EVEX_0F3A3F,
1702   PREFIX_EVEX_0F3A42,
1703   PREFIX_EVEX_0F3A43,
1704   PREFIX_EVEX_0F3A50,
1705   PREFIX_EVEX_0F3A51,
1706   PREFIX_EVEX_0F3A54,
1707   PREFIX_EVEX_0F3A55,
1708   PREFIX_EVEX_0F3A56,
1709   PREFIX_EVEX_0F3A57,
1710   PREFIX_EVEX_0F3A66,
1711   PREFIX_EVEX_0F3A67,
1712   PREFIX_EVEX_0F3A70,
1713   PREFIX_EVEX_0F3A71,
1714   PREFIX_EVEX_0F3A72,
1715   PREFIX_EVEX_0F3A73,
1716   PREFIX_EVEX_0F3ACE,
1717   PREFIX_EVEX_0F3ACF
1718 };
1719
1720 enum
1721 {
1722   X86_64_06 = 0,
1723   X86_64_07,
1724   X86_64_0D,
1725   X86_64_16,
1726   X86_64_17,
1727   X86_64_1E,
1728   X86_64_1F,
1729   X86_64_27,
1730   X86_64_2F,
1731   X86_64_37,
1732   X86_64_3F,
1733   X86_64_60,
1734   X86_64_61,
1735   X86_64_62,
1736   X86_64_63,
1737   X86_64_6D,
1738   X86_64_6F,
1739   X86_64_82,
1740   X86_64_9A,
1741   X86_64_C4,
1742   X86_64_C5,
1743   X86_64_CE,
1744   X86_64_D4,
1745   X86_64_D5,
1746   X86_64_E8,
1747   X86_64_E9,
1748   X86_64_EA,
1749   X86_64_0F01_REG_0,
1750   X86_64_0F01_REG_1,
1751   X86_64_0F01_REG_2,
1752   X86_64_0F01_REG_3
1753 };
1754
1755 enum
1756 {
1757   THREE_BYTE_0F38 = 0,
1758   THREE_BYTE_0F3A
1759 };
1760
1761 enum
1762 {
1763   XOP_08 = 0,
1764   XOP_09,
1765   XOP_0A
1766 };
1767
1768 enum
1769 {
1770   VEX_0F = 0,
1771   VEX_0F38,
1772   VEX_0F3A
1773 };
1774
1775 enum
1776 {
1777   EVEX_0F = 0,
1778   EVEX_0F38,
1779   EVEX_0F3A
1780 };
1781
1782 enum
1783 {
1784   VEX_LEN_0F10_P_1 = 0,
1785   VEX_LEN_0F10_P_3,
1786   VEX_LEN_0F11_P_1,
1787   VEX_LEN_0F11_P_3,
1788   VEX_LEN_0F12_P_0_M_0,
1789   VEX_LEN_0F12_P_0_M_1,
1790   VEX_LEN_0F12_P_2,
1791   VEX_LEN_0F13_M_0,
1792   VEX_LEN_0F16_P_0_M_0,
1793   VEX_LEN_0F16_P_0_M_1,
1794   VEX_LEN_0F16_P_2,
1795   VEX_LEN_0F17_M_0,
1796   VEX_LEN_0F2A_P_1,
1797   VEX_LEN_0F2A_P_3,
1798   VEX_LEN_0F2C_P_1,
1799   VEX_LEN_0F2C_P_3,
1800   VEX_LEN_0F2D_P_1,
1801   VEX_LEN_0F2D_P_3,
1802   VEX_LEN_0F2E_P_0,
1803   VEX_LEN_0F2E_P_2,
1804   VEX_LEN_0F2F_P_0,
1805   VEX_LEN_0F2F_P_2,
1806   VEX_LEN_0F41_P_0,
1807   VEX_LEN_0F41_P_2,
1808   VEX_LEN_0F42_P_0,
1809   VEX_LEN_0F42_P_2,
1810   VEX_LEN_0F44_P_0,
1811   VEX_LEN_0F44_P_2,
1812   VEX_LEN_0F45_P_0,
1813   VEX_LEN_0F45_P_2,
1814   VEX_LEN_0F46_P_0,
1815   VEX_LEN_0F46_P_2,
1816   VEX_LEN_0F47_P_0,
1817   VEX_LEN_0F47_P_2,
1818   VEX_LEN_0F4A_P_0,
1819   VEX_LEN_0F4A_P_2,
1820   VEX_LEN_0F4B_P_0,
1821   VEX_LEN_0F4B_P_2,
1822   VEX_LEN_0F51_P_1,
1823   VEX_LEN_0F51_P_3,
1824   VEX_LEN_0F52_P_1,
1825   VEX_LEN_0F53_P_1,
1826   VEX_LEN_0F58_P_1,
1827   VEX_LEN_0F58_P_3,
1828   VEX_LEN_0F59_P_1,
1829   VEX_LEN_0F59_P_3,
1830   VEX_LEN_0F5A_P_1,
1831   VEX_LEN_0F5A_P_3,
1832   VEX_LEN_0F5C_P_1,
1833   VEX_LEN_0F5C_P_3,
1834   VEX_LEN_0F5D_P_1,
1835   VEX_LEN_0F5D_P_3,
1836   VEX_LEN_0F5E_P_1,
1837   VEX_LEN_0F5E_P_3,
1838   VEX_LEN_0F5F_P_1,
1839   VEX_LEN_0F5F_P_3,
1840   VEX_LEN_0F6E_P_2,
1841   VEX_LEN_0F7E_P_1,
1842   VEX_LEN_0F7E_P_2,
1843   VEX_LEN_0F90_P_0,
1844   VEX_LEN_0F90_P_2,
1845   VEX_LEN_0F91_P_0,
1846   VEX_LEN_0F91_P_2,
1847   VEX_LEN_0F92_P_0,
1848   VEX_LEN_0F92_P_2,
1849   VEX_LEN_0F92_P_3,
1850   VEX_LEN_0F93_P_0,
1851   VEX_LEN_0F93_P_2,
1852   VEX_LEN_0F93_P_3,
1853   VEX_LEN_0F98_P_0,
1854   VEX_LEN_0F98_P_2,
1855   VEX_LEN_0F99_P_0,
1856   VEX_LEN_0F99_P_2,
1857   VEX_LEN_0FAE_R_2_M_0,
1858   VEX_LEN_0FAE_R_3_M_0,
1859   VEX_LEN_0FC2_P_1,
1860   VEX_LEN_0FC2_P_3,
1861   VEX_LEN_0FC4_P_2,
1862   VEX_LEN_0FC5_P_2,
1863   VEX_LEN_0FD6_P_2,
1864   VEX_LEN_0FF7_P_2,
1865   VEX_LEN_0F3816_P_2,
1866   VEX_LEN_0F3819_P_2,
1867   VEX_LEN_0F381A_P_2_M_0,
1868   VEX_LEN_0F3836_P_2,
1869   VEX_LEN_0F3841_P_2,
1870   VEX_LEN_0F385A_P_2_M_0,
1871   VEX_LEN_0F38DB_P_2,
1872   VEX_LEN_0F38F2_P_0,
1873   VEX_LEN_0F38F3_R_1_P_0,
1874   VEX_LEN_0F38F3_R_2_P_0,
1875   VEX_LEN_0F38F3_R_3_P_0,
1876   VEX_LEN_0F38F5_P_0,
1877   VEX_LEN_0F38F5_P_1,
1878   VEX_LEN_0F38F5_P_3,
1879   VEX_LEN_0F38F6_P_3,
1880   VEX_LEN_0F38F7_P_0,
1881   VEX_LEN_0F38F7_P_1,
1882   VEX_LEN_0F38F7_P_2,
1883   VEX_LEN_0F38F7_P_3,
1884   VEX_LEN_0F3A00_P_2,
1885   VEX_LEN_0F3A01_P_2,
1886   VEX_LEN_0F3A06_P_2,
1887   VEX_LEN_0F3A0A_P_2,
1888   VEX_LEN_0F3A0B_P_2,
1889   VEX_LEN_0F3A14_P_2,
1890   VEX_LEN_0F3A15_P_2,
1891   VEX_LEN_0F3A16_P_2,
1892   VEX_LEN_0F3A17_P_2,
1893   VEX_LEN_0F3A18_P_2,
1894   VEX_LEN_0F3A19_P_2,
1895   VEX_LEN_0F3A20_P_2,
1896   VEX_LEN_0F3A21_P_2,
1897   VEX_LEN_0F3A22_P_2,
1898   VEX_LEN_0F3A30_P_2,
1899   VEX_LEN_0F3A31_P_2,
1900   VEX_LEN_0F3A32_P_2,
1901   VEX_LEN_0F3A33_P_2,
1902   VEX_LEN_0F3A38_P_2,
1903   VEX_LEN_0F3A39_P_2,
1904   VEX_LEN_0F3A41_P_2,
1905   VEX_LEN_0F3A44_P_2,
1906   VEX_LEN_0F3A46_P_2,
1907   VEX_LEN_0F3A60_P_2,
1908   VEX_LEN_0F3A61_P_2,
1909   VEX_LEN_0F3A62_P_2,
1910   VEX_LEN_0F3A63_P_2,
1911   VEX_LEN_0F3A6A_P_2,
1912   VEX_LEN_0F3A6B_P_2,
1913   VEX_LEN_0F3A6E_P_2,
1914   VEX_LEN_0F3A6F_P_2,
1915   VEX_LEN_0F3A7A_P_2,
1916   VEX_LEN_0F3A7B_P_2,
1917   VEX_LEN_0F3A7E_P_2,
1918   VEX_LEN_0F3A7F_P_2,
1919   VEX_LEN_0F3ADF_P_2,
1920   VEX_LEN_0F3AF0_P_3,
1921   VEX_LEN_0FXOP_08_CC,
1922   VEX_LEN_0FXOP_08_CD,
1923   VEX_LEN_0FXOP_08_CE,
1924   VEX_LEN_0FXOP_08_CF,
1925   VEX_LEN_0FXOP_08_EC,
1926   VEX_LEN_0FXOP_08_ED,
1927   VEX_LEN_0FXOP_08_EE,
1928   VEX_LEN_0FXOP_08_EF,
1929   VEX_LEN_0FXOP_09_80,
1930   VEX_LEN_0FXOP_09_81
1931 };
1932
1933 enum
1934 {
1935   VEX_W_0F10_P_0 = 0,
1936   VEX_W_0F10_P_1,
1937   VEX_W_0F10_P_2,
1938   VEX_W_0F10_P_3,
1939   VEX_W_0F11_P_0,
1940   VEX_W_0F11_P_1,
1941   VEX_W_0F11_P_2,
1942   VEX_W_0F11_P_3,
1943   VEX_W_0F12_P_0_M_0,
1944   VEX_W_0F12_P_0_M_1,
1945   VEX_W_0F12_P_1,
1946   VEX_W_0F12_P_2,
1947   VEX_W_0F12_P_3,
1948   VEX_W_0F13_M_0,
1949   VEX_W_0F14,
1950   VEX_W_0F15,
1951   VEX_W_0F16_P_0_M_0,
1952   VEX_W_0F16_P_0_M_1,
1953   VEX_W_0F16_P_1,
1954   VEX_W_0F16_P_2,
1955   VEX_W_0F17_M_0,
1956   VEX_W_0F28,
1957   VEX_W_0F29,
1958   VEX_W_0F2B_M_0,
1959   VEX_W_0F2E_P_0,
1960   VEX_W_0F2E_P_2,
1961   VEX_W_0F2F_P_0,
1962   VEX_W_0F2F_P_2,
1963   VEX_W_0F41_P_0_LEN_1,
1964   VEX_W_0F41_P_2_LEN_1,
1965   VEX_W_0F42_P_0_LEN_1,
1966   VEX_W_0F42_P_2_LEN_1,
1967   VEX_W_0F44_P_0_LEN_0,
1968   VEX_W_0F44_P_2_LEN_0,
1969   VEX_W_0F45_P_0_LEN_1,
1970   VEX_W_0F45_P_2_LEN_1,
1971   VEX_W_0F46_P_0_LEN_1,
1972   VEX_W_0F46_P_2_LEN_1,
1973   VEX_W_0F47_P_0_LEN_1,
1974   VEX_W_0F47_P_2_LEN_1,
1975   VEX_W_0F4A_P_0_LEN_1,
1976   VEX_W_0F4A_P_2_LEN_1,
1977   VEX_W_0F4B_P_0_LEN_1,
1978   VEX_W_0F4B_P_2_LEN_1,
1979   VEX_W_0F50_M_0,
1980   VEX_W_0F51_P_0,
1981   VEX_W_0F51_P_1,
1982   VEX_W_0F51_P_2,
1983   VEX_W_0F51_P_3,
1984   VEX_W_0F52_P_0,
1985   VEX_W_0F52_P_1,
1986   VEX_W_0F53_P_0,
1987   VEX_W_0F53_P_1,
1988   VEX_W_0F58_P_0,
1989   VEX_W_0F58_P_1,
1990   VEX_W_0F58_P_2,
1991   VEX_W_0F58_P_3,
1992   VEX_W_0F59_P_0,
1993   VEX_W_0F59_P_1,
1994   VEX_W_0F59_P_2,
1995   VEX_W_0F59_P_3,
1996   VEX_W_0F5A_P_0,
1997   VEX_W_0F5A_P_1,
1998   VEX_W_0F5A_P_3,
1999   VEX_W_0F5B_P_0,
2000   VEX_W_0F5B_P_1,
2001   VEX_W_0F5B_P_2,
2002   VEX_W_0F5C_P_0,
2003   VEX_W_0F5C_P_1,
2004   VEX_W_0F5C_P_2,
2005   VEX_W_0F5C_P_3,
2006   VEX_W_0F5D_P_0,
2007   VEX_W_0F5D_P_1,
2008   VEX_W_0F5D_P_2,
2009   VEX_W_0F5D_P_3,
2010   VEX_W_0F5E_P_0,
2011   VEX_W_0F5E_P_1,
2012   VEX_W_0F5E_P_2,
2013   VEX_W_0F5E_P_3,
2014   VEX_W_0F5F_P_0,
2015   VEX_W_0F5F_P_1,
2016   VEX_W_0F5F_P_2,
2017   VEX_W_0F5F_P_3,
2018   VEX_W_0F60_P_2,
2019   VEX_W_0F61_P_2,
2020   VEX_W_0F62_P_2,
2021   VEX_W_0F63_P_2,
2022   VEX_W_0F64_P_2,
2023   VEX_W_0F65_P_2,
2024   VEX_W_0F66_P_2,
2025   VEX_W_0F67_P_2,
2026   VEX_W_0F68_P_2,
2027   VEX_W_0F69_P_2,
2028   VEX_W_0F6A_P_2,
2029   VEX_W_0F6B_P_2,
2030   VEX_W_0F6C_P_2,
2031   VEX_W_0F6D_P_2,
2032   VEX_W_0F6F_P_1,
2033   VEX_W_0F6F_P_2,
2034   VEX_W_0F70_P_1,
2035   VEX_W_0F70_P_2,
2036   VEX_W_0F70_P_3,
2037   VEX_W_0F71_R_2_P_2,
2038   VEX_W_0F71_R_4_P_2,
2039   VEX_W_0F71_R_6_P_2,
2040   VEX_W_0F72_R_2_P_2,
2041   VEX_W_0F72_R_4_P_2,
2042   VEX_W_0F72_R_6_P_2,
2043   VEX_W_0F73_R_2_P_2,
2044   VEX_W_0F73_R_3_P_2,
2045   VEX_W_0F73_R_6_P_2,
2046   VEX_W_0F73_R_7_P_2,
2047   VEX_W_0F74_P_2,
2048   VEX_W_0F75_P_2,
2049   VEX_W_0F76_P_2,
2050   VEX_W_0F77_P_0,
2051   VEX_W_0F7C_P_2,
2052   VEX_W_0F7C_P_3,
2053   VEX_W_0F7D_P_2,
2054   VEX_W_0F7D_P_3,
2055   VEX_W_0F7E_P_1,
2056   VEX_W_0F7F_P_1,
2057   VEX_W_0F7F_P_2,
2058   VEX_W_0F90_P_0_LEN_0,
2059   VEX_W_0F90_P_2_LEN_0,
2060   VEX_W_0F91_P_0_LEN_0,
2061   VEX_W_0F91_P_2_LEN_0,
2062   VEX_W_0F92_P_0_LEN_0,
2063   VEX_W_0F92_P_2_LEN_0,
2064   VEX_W_0F92_P_3_LEN_0,
2065   VEX_W_0F93_P_0_LEN_0,
2066   VEX_W_0F93_P_2_LEN_0,
2067   VEX_W_0F93_P_3_LEN_0,
2068   VEX_W_0F98_P_0_LEN_0,
2069   VEX_W_0F98_P_2_LEN_0,
2070   VEX_W_0F99_P_0_LEN_0,
2071   VEX_W_0F99_P_2_LEN_0,
2072   VEX_W_0FAE_R_2_M_0,
2073   VEX_W_0FAE_R_3_M_0,
2074   VEX_W_0FC2_P_0,
2075   VEX_W_0FC2_P_1,
2076   VEX_W_0FC2_P_2,
2077   VEX_W_0FC2_P_3,
2078   VEX_W_0FC4_P_2,
2079   VEX_W_0FC5_P_2,
2080   VEX_W_0FD0_P_2,
2081   VEX_W_0FD0_P_3,
2082   VEX_W_0FD1_P_2,
2083   VEX_W_0FD2_P_2,
2084   VEX_W_0FD3_P_2,
2085   VEX_W_0FD4_P_2,
2086   VEX_W_0FD5_P_2,
2087   VEX_W_0FD6_P_2,
2088   VEX_W_0FD7_P_2_M_1,
2089   VEX_W_0FD8_P_2,
2090   VEX_W_0FD9_P_2,
2091   VEX_W_0FDA_P_2,
2092   VEX_W_0FDB_P_2,
2093   VEX_W_0FDC_P_2,
2094   VEX_W_0FDD_P_2,
2095   VEX_W_0FDE_P_2,
2096   VEX_W_0FDF_P_2,
2097   VEX_W_0FE0_P_2,
2098   VEX_W_0FE1_P_2,
2099   VEX_W_0FE2_P_2,
2100   VEX_W_0FE3_P_2,
2101   VEX_W_0FE4_P_2,
2102   VEX_W_0FE5_P_2,
2103   VEX_W_0FE6_P_1,
2104   VEX_W_0FE6_P_2,
2105   VEX_W_0FE6_P_3,
2106   VEX_W_0FE7_P_2_M_0,
2107   VEX_W_0FE8_P_2,
2108   VEX_W_0FE9_P_2,
2109   VEX_W_0FEA_P_2,
2110   VEX_W_0FEB_P_2,
2111   VEX_W_0FEC_P_2,
2112   VEX_W_0FED_P_2,
2113   VEX_W_0FEE_P_2,
2114   VEX_W_0FEF_P_2,
2115   VEX_W_0FF0_P_3_M_0,
2116   VEX_W_0FF1_P_2,
2117   VEX_W_0FF2_P_2,
2118   VEX_W_0FF3_P_2,
2119   VEX_W_0FF4_P_2,
2120   VEX_W_0FF5_P_2,
2121   VEX_W_0FF6_P_2,
2122   VEX_W_0FF7_P_2,
2123   VEX_W_0FF8_P_2,
2124   VEX_W_0FF9_P_2,
2125   VEX_W_0FFA_P_2,
2126   VEX_W_0FFB_P_2,
2127   VEX_W_0FFC_P_2,
2128   VEX_W_0FFD_P_2,
2129   VEX_W_0FFE_P_2,
2130   VEX_W_0F3800_P_2,
2131   VEX_W_0F3801_P_2,
2132   VEX_W_0F3802_P_2,
2133   VEX_W_0F3803_P_2,
2134   VEX_W_0F3804_P_2,
2135   VEX_W_0F3805_P_2,
2136   VEX_W_0F3806_P_2,
2137   VEX_W_0F3807_P_2,
2138   VEX_W_0F3808_P_2,
2139   VEX_W_0F3809_P_2,
2140   VEX_W_0F380A_P_2,
2141   VEX_W_0F380B_P_2,
2142   VEX_W_0F380C_P_2,
2143   VEX_W_0F380D_P_2,
2144   VEX_W_0F380E_P_2,
2145   VEX_W_0F380F_P_2,
2146   VEX_W_0F3816_P_2,
2147   VEX_W_0F3817_P_2,
2148   VEX_W_0F3818_P_2,
2149   VEX_W_0F3819_P_2,
2150   VEX_W_0F381A_P_2_M_0,
2151   VEX_W_0F381C_P_2,
2152   VEX_W_0F381D_P_2,
2153   VEX_W_0F381E_P_2,
2154   VEX_W_0F3820_P_2,
2155   VEX_W_0F3821_P_2,
2156   VEX_W_0F3822_P_2,
2157   VEX_W_0F3823_P_2,
2158   VEX_W_0F3824_P_2,
2159   VEX_W_0F3825_P_2,
2160   VEX_W_0F3828_P_2,
2161   VEX_W_0F3829_P_2,
2162   VEX_W_0F382A_P_2_M_0,
2163   VEX_W_0F382B_P_2,
2164   VEX_W_0F382C_P_2_M_0,
2165   VEX_W_0F382D_P_2_M_0,
2166   VEX_W_0F382E_P_2_M_0,
2167   VEX_W_0F382F_P_2_M_0,
2168   VEX_W_0F3830_P_2,
2169   VEX_W_0F3831_P_2,
2170   VEX_W_0F3832_P_2,
2171   VEX_W_0F3833_P_2,
2172   VEX_W_0F3834_P_2,
2173   VEX_W_0F3835_P_2,
2174   VEX_W_0F3836_P_2,
2175   VEX_W_0F3837_P_2,
2176   VEX_W_0F3838_P_2,
2177   VEX_W_0F3839_P_2,
2178   VEX_W_0F383A_P_2,
2179   VEX_W_0F383B_P_2,
2180   VEX_W_0F383C_P_2,
2181   VEX_W_0F383D_P_2,
2182   VEX_W_0F383E_P_2,
2183   VEX_W_0F383F_P_2,
2184   VEX_W_0F3840_P_2,
2185   VEX_W_0F3841_P_2,
2186   VEX_W_0F3846_P_2,
2187   VEX_W_0F3858_P_2,
2188   VEX_W_0F3859_P_2,
2189   VEX_W_0F385A_P_2_M_0,
2190   VEX_W_0F3878_P_2,
2191   VEX_W_0F3879_P_2,
2192   VEX_W_0F38CF_P_2,
2193   VEX_W_0F38DB_P_2,
2194   VEX_W_0F3A00_P_2,
2195   VEX_W_0F3A01_P_2,
2196   VEX_W_0F3A02_P_2,
2197   VEX_W_0F3A04_P_2,
2198   VEX_W_0F3A05_P_2,
2199   VEX_W_0F3A06_P_2,
2200   VEX_W_0F3A08_P_2,
2201   VEX_W_0F3A09_P_2,
2202   VEX_W_0F3A0A_P_2,
2203   VEX_W_0F3A0B_P_2,
2204   VEX_W_0F3A0C_P_2,
2205   VEX_W_0F3A0D_P_2,
2206   VEX_W_0F3A0E_P_2,
2207   VEX_W_0F3A0F_P_2,
2208   VEX_W_0F3A14_P_2,
2209   VEX_W_0F3A15_P_2,
2210   VEX_W_0F3A18_P_2,
2211   VEX_W_0F3A19_P_2,
2212   VEX_W_0F3A20_P_2,
2213   VEX_W_0F3A21_P_2,
2214   VEX_W_0F3A30_P_2_LEN_0,
2215   VEX_W_0F3A31_P_2_LEN_0,
2216   VEX_W_0F3A32_P_2_LEN_0,
2217   VEX_W_0F3A33_P_2_LEN_0,
2218   VEX_W_0F3A38_P_2,
2219   VEX_W_0F3A39_P_2,
2220   VEX_W_0F3A40_P_2,
2221   VEX_W_0F3A41_P_2,
2222   VEX_W_0F3A42_P_2,
2223   VEX_W_0F3A44_P_2,
2224   VEX_W_0F3A46_P_2,
2225   VEX_W_0F3A48_P_2,
2226   VEX_W_0F3A49_P_2,
2227   VEX_W_0F3A4A_P_2,
2228   VEX_W_0F3A4B_P_2,
2229   VEX_W_0F3A4C_P_2,
2230   VEX_W_0F3A62_P_2,
2231   VEX_W_0F3A63_P_2,
2232   VEX_W_0F3ACE_P_2,
2233   VEX_W_0F3ACF_P_2,
2234   VEX_W_0F3ADF_P_2,
2235
2236   EVEX_W_0F10_P_0,
2237   EVEX_W_0F10_P_1_M_0,
2238   EVEX_W_0F10_P_1_M_1,
2239   EVEX_W_0F10_P_2,
2240   EVEX_W_0F10_P_3_M_0,
2241   EVEX_W_0F10_P_3_M_1,
2242   EVEX_W_0F11_P_0,
2243   EVEX_W_0F11_P_1_M_0,
2244   EVEX_W_0F11_P_1_M_1,
2245   EVEX_W_0F11_P_2,
2246   EVEX_W_0F11_P_3_M_0,
2247   EVEX_W_0F11_P_3_M_1,
2248   EVEX_W_0F12_P_0_M_0,
2249   EVEX_W_0F12_P_0_M_1,
2250   EVEX_W_0F12_P_1,
2251   EVEX_W_0F12_P_2,
2252   EVEX_W_0F12_P_3,
2253   EVEX_W_0F13_P_0,
2254   EVEX_W_0F13_P_2,
2255   EVEX_W_0F14_P_0,
2256   EVEX_W_0F14_P_2,
2257   EVEX_W_0F15_P_0,
2258   EVEX_W_0F15_P_2,
2259   EVEX_W_0F16_P_0_M_0,
2260   EVEX_W_0F16_P_0_M_1,
2261   EVEX_W_0F16_P_1,
2262   EVEX_W_0F16_P_2,
2263   EVEX_W_0F17_P_0,
2264   EVEX_W_0F17_P_2,
2265   EVEX_W_0F28_P_0,
2266   EVEX_W_0F28_P_2,
2267   EVEX_W_0F29_P_0,
2268   EVEX_W_0F29_P_2,
2269   EVEX_W_0F2A_P_1,
2270   EVEX_W_0F2A_P_3,
2271   EVEX_W_0F2B_P_0,
2272   EVEX_W_0F2B_P_2,
2273   EVEX_W_0F2E_P_0,
2274   EVEX_W_0F2E_P_2,
2275   EVEX_W_0F2F_P_0,
2276   EVEX_W_0F2F_P_2,
2277   EVEX_W_0F51_P_0,
2278   EVEX_W_0F51_P_1,
2279   EVEX_W_0F51_P_2,
2280   EVEX_W_0F51_P_3,
2281   EVEX_W_0F54_P_0,
2282   EVEX_W_0F54_P_2,
2283   EVEX_W_0F55_P_0,
2284   EVEX_W_0F55_P_2,
2285   EVEX_W_0F56_P_0,
2286   EVEX_W_0F56_P_2,
2287   EVEX_W_0F57_P_0,
2288   EVEX_W_0F57_P_2,
2289   EVEX_W_0F58_P_0,
2290   EVEX_W_0F58_P_1,
2291   EVEX_W_0F58_P_2,
2292   EVEX_W_0F58_P_3,
2293   EVEX_W_0F59_P_0,
2294   EVEX_W_0F59_P_1,
2295   EVEX_W_0F59_P_2,
2296   EVEX_W_0F59_P_3,
2297   EVEX_W_0F5A_P_0,
2298   EVEX_W_0F5A_P_1,
2299   EVEX_W_0F5A_P_2,
2300   EVEX_W_0F5A_P_3,
2301   EVEX_W_0F5B_P_0,
2302   EVEX_W_0F5B_P_1,
2303   EVEX_W_0F5B_P_2,
2304   EVEX_W_0F5C_P_0,
2305   EVEX_W_0F5C_P_1,
2306   EVEX_W_0F5C_P_2,
2307   EVEX_W_0F5C_P_3,
2308   EVEX_W_0F5D_P_0,
2309   EVEX_W_0F5D_P_1,
2310   EVEX_W_0F5D_P_2,
2311   EVEX_W_0F5D_P_3,
2312   EVEX_W_0F5E_P_0,
2313   EVEX_W_0F5E_P_1,
2314   EVEX_W_0F5E_P_2,
2315   EVEX_W_0F5E_P_3,
2316   EVEX_W_0F5F_P_0,
2317   EVEX_W_0F5F_P_1,
2318   EVEX_W_0F5F_P_2,
2319   EVEX_W_0F5F_P_3,
2320   EVEX_W_0F62_P_2,
2321   EVEX_W_0F66_P_2,
2322   EVEX_W_0F6A_P_2,
2323   EVEX_W_0F6B_P_2,
2324   EVEX_W_0F6C_P_2,
2325   EVEX_W_0F6D_P_2,
2326   EVEX_W_0F6E_P_2,
2327   EVEX_W_0F6F_P_1,
2328   EVEX_W_0F6F_P_2,
2329   EVEX_W_0F6F_P_3,
2330   EVEX_W_0F70_P_2,
2331   EVEX_W_0F72_R_2_P_2,
2332   EVEX_W_0F72_R_6_P_2,
2333   EVEX_W_0F73_R_2_P_2,
2334   EVEX_W_0F73_R_6_P_2,
2335   EVEX_W_0F76_P_2,
2336   EVEX_W_0F78_P_0,
2337   EVEX_W_0F78_P_2,
2338   EVEX_W_0F79_P_0,
2339   EVEX_W_0F79_P_2,
2340   EVEX_W_0F7A_P_1,
2341   EVEX_W_0F7A_P_2,
2342   EVEX_W_0F7A_P_3,
2343   EVEX_W_0F7B_P_1,
2344   EVEX_W_0F7B_P_2,
2345   EVEX_W_0F7B_P_3,
2346   EVEX_W_0F7E_P_1,
2347   EVEX_W_0F7E_P_2,
2348   EVEX_W_0F7F_P_1,
2349   EVEX_W_0F7F_P_2,
2350   EVEX_W_0F7F_P_3,
2351   EVEX_W_0FC2_P_0,
2352   EVEX_W_0FC2_P_1,
2353   EVEX_W_0FC2_P_2,
2354   EVEX_W_0FC2_P_3,
2355   EVEX_W_0FC6_P_0,
2356   EVEX_W_0FC6_P_2,
2357   EVEX_W_0FD2_P_2,
2358   EVEX_W_0FD3_P_2,
2359   EVEX_W_0FD4_P_2,
2360   EVEX_W_0FD6_P_2,
2361   EVEX_W_0FE6_P_1,
2362   EVEX_W_0FE6_P_2,
2363   EVEX_W_0FE6_P_3,
2364   EVEX_W_0FE7_P_2,
2365   EVEX_W_0FF2_P_2,
2366   EVEX_W_0FF3_P_2,
2367   EVEX_W_0FF4_P_2,
2368   EVEX_W_0FFA_P_2,
2369   EVEX_W_0FFB_P_2,
2370   EVEX_W_0FFE_P_2,
2371   EVEX_W_0F380C_P_2,
2372   EVEX_W_0F380D_P_2,
2373   EVEX_W_0F3810_P_1,
2374   EVEX_W_0F3810_P_2,
2375   EVEX_W_0F3811_P_1,
2376   EVEX_W_0F3811_P_2,
2377   EVEX_W_0F3812_P_1,
2378   EVEX_W_0F3812_P_2,
2379   EVEX_W_0F3813_P_1,
2380   EVEX_W_0F3813_P_2,
2381   EVEX_W_0F3814_P_1,
2382   EVEX_W_0F3815_P_1,
2383   EVEX_W_0F3818_P_2,
2384   EVEX_W_0F3819_P_2,
2385   EVEX_W_0F381A_P_2,
2386   EVEX_W_0F381B_P_2,
2387   EVEX_W_0F381E_P_2,
2388   EVEX_W_0F381F_P_2,
2389   EVEX_W_0F3820_P_1,
2390   EVEX_W_0F3821_P_1,
2391   EVEX_W_0F3822_P_1,
2392   EVEX_W_0F3823_P_1,
2393   EVEX_W_0F3824_P_1,
2394   EVEX_W_0F3825_P_1,
2395   EVEX_W_0F3825_P_2,
2396   EVEX_W_0F3826_P_1,
2397   EVEX_W_0F3826_P_2,
2398   EVEX_W_0F3828_P_1,
2399   EVEX_W_0F3828_P_2,
2400   EVEX_W_0F3829_P_1,
2401   EVEX_W_0F3829_P_2,
2402   EVEX_W_0F382A_P_1,
2403   EVEX_W_0F382A_P_2,
2404   EVEX_W_0F382B_P_2,
2405   EVEX_W_0F3830_P_1,
2406   EVEX_W_0F3831_P_1,
2407   EVEX_W_0F3832_P_1,
2408   EVEX_W_0F3833_P_1,
2409   EVEX_W_0F3834_P_1,
2410   EVEX_W_0F3835_P_1,
2411   EVEX_W_0F3835_P_2,
2412   EVEX_W_0F3837_P_2,
2413   EVEX_W_0F3838_P_1,
2414   EVEX_W_0F3839_P_1,
2415   EVEX_W_0F383A_P_1,
2416   EVEX_W_0F3840_P_2,
2417   EVEX_W_0F3855_P_2,
2418   EVEX_W_0F3858_P_2,
2419   EVEX_W_0F3859_P_2,
2420   EVEX_W_0F385A_P_2,
2421   EVEX_W_0F385B_P_2,
2422   EVEX_W_0F3862_P_2,
2423   EVEX_W_0F3863_P_2,
2424   EVEX_W_0F3866_P_2,
2425   EVEX_W_0F3870_P_2,
2426   EVEX_W_0F3871_P_2,
2427   EVEX_W_0F3872_P_2,
2428   EVEX_W_0F3873_P_2,
2429   EVEX_W_0F3875_P_2,
2430   EVEX_W_0F3878_P_2,
2431   EVEX_W_0F3879_P_2,
2432   EVEX_W_0F387A_P_2,
2433   EVEX_W_0F387B_P_2,
2434   EVEX_W_0F387D_P_2,
2435   EVEX_W_0F3883_P_2,
2436   EVEX_W_0F388D_P_2,
2437   EVEX_W_0F3891_P_2,
2438   EVEX_W_0F3893_P_2,
2439   EVEX_W_0F38A1_P_2,
2440   EVEX_W_0F38A3_P_2,
2441   EVEX_W_0F38C7_R_1_P_2,
2442   EVEX_W_0F38C7_R_2_P_2,
2443   EVEX_W_0F38C7_R_5_P_2,
2444   EVEX_W_0F38C7_R_6_P_2,
2445
2446   EVEX_W_0F3A00_P_2,
2447   EVEX_W_0F3A01_P_2,
2448   EVEX_W_0F3A04_P_2,
2449   EVEX_W_0F3A05_P_2,
2450   EVEX_W_0F3A08_P_2,
2451   EVEX_W_0F3A09_P_2,
2452   EVEX_W_0F3A0A_P_2,
2453   EVEX_W_0F3A0B_P_2,
2454   EVEX_W_0F3A16_P_2,
2455   EVEX_W_0F3A18_P_2,
2456   EVEX_W_0F3A19_P_2,
2457   EVEX_W_0F3A1A_P_2,
2458   EVEX_W_0F3A1B_P_2,
2459   EVEX_W_0F3A1D_P_2,
2460   EVEX_W_0F3A21_P_2,
2461   EVEX_W_0F3A22_P_2,
2462   EVEX_W_0F3A23_P_2,
2463   EVEX_W_0F3A38_P_2,
2464   EVEX_W_0F3A39_P_2,
2465   EVEX_W_0F3A3A_P_2,
2466   EVEX_W_0F3A3B_P_2,
2467   EVEX_W_0F3A3E_P_2,
2468   EVEX_W_0F3A3F_P_2,
2469   EVEX_W_0F3A42_P_2,
2470   EVEX_W_0F3A43_P_2,
2471   EVEX_W_0F3A50_P_2,
2472   EVEX_W_0F3A51_P_2,
2473   EVEX_W_0F3A56_P_2,
2474   EVEX_W_0F3A57_P_2,
2475   EVEX_W_0F3A66_P_2,
2476   EVEX_W_0F3A67_P_2,
2477   EVEX_W_0F3A70_P_2,
2478   EVEX_W_0F3A71_P_2,
2479   EVEX_W_0F3A72_P_2,
2480   EVEX_W_0F3A73_P_2,
2481   EVEX_W_0F3ACE_P_2,
2482   EVEX_W_0F3ACF_P_2
2483 };
2484
2485 typedef void (*op_rtn) (int bytemode, int sizeflag);
2486
2487 struct dis386 {
2488   const char *name;
2489   struct
2490     {
2491       op_rtn rtn;
2492       int bytemode;
2493     } op[MAX_OPERANDS];
2494   unsigned int prefix_requirement;
2495 };
2496
2497 /* Upper case letters in the instruction names here are macros.
2498    'A' => print 'b' if no register operands or suffix_always is true
2499    'B' => print 'b' if suffix_always is true
2500    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2501           size prefix
2502    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2503           suffix_always is true
2504    'E' => print 'e' if 32-bit form of jcxz
2505    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2506    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2507    'H' => print ",pt" or ",pn" branch hint
2508    'I' => honor following macro letter even in Intel mode (implemented only
2509           for some of the macro letters)
2510    'J' => print 'l'
2511    'K' => print 'd' or 'q' if rex prefix is present.
2512    'L' => print 'l' if suffix_always is true
2513    'M' => print 'r' if intel_mnemonic is false.
2514    'N' => print 'n' if instruction has no wait "prefix"
2515    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2516    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2517           or suffix_always is true.  print 'q' if rex prefix is present.
2518    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2519           is true
2520    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2521    'S' => print 'w', 'l' or 'q' if suffix_always is true
2522    'T' => print 'q' in 64bit mode if instruction has no operand size
2523           prefix and behave as 'P' otherwise
2524    'U' => print 'q' in 64bit mode if instruction has no operand size
2525           prefix and behave as 'Q' otherwise
2526    'V' => print 'q' in 64bit mode if instruction has no operand size
2527           prefix and behave as 'S' otherwise
2528    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2529    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2530    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2531           suffix_always is true.
2532    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2533    '!' => change condition from true to false or from false to true.
2534    '%' => add 1 upper case letter to the macro.
2535    '^' => print 'w' or 'l' depending on operand size prefix or
2536           suffix_always is true (lcall/ljmp).
2537    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2538           on operand size prefix.
2539    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2540           has no operand size prefix for AMD64 ISA, behave as 'P'
2541           otherwise
2542
2543    2 upper case letter macros:
2544    "XY" => print 'x' or 'y' if suffix_always is true or no register
2545            operands and no broadcast.
2546    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2547            register operands and no broadcast.
2548    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2549    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2550            or suffix_always is true
2551    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2552    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2553    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2554    "LW" => print 'd', 'q' depending on the VEX.W bit
2555    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2556            an operand size prefix, or suffix_always is true.  print
2557            'q' if rex prefix is present.
2558
2559    Many of the above letters print nothing in Intel mode.  See "putop"
2560    for the details.
2561
2562    Braces '{' and '}', and vertical bars '|', indicate alternative
2563    mnemonic strings for AT&T and Intel.  */
2564
2565 static const struct dis386 dis386[] = {
2566   /* 00 */
2567   { "addB",             { Ebh1, Gb }, 0 },
2568   { "addS",             { Evh1, Gv }, 0 },
2569   { "addB",             { Gb, EbS }, 0 },
2570   { "addS",             { Gv, EvS }, 0 },
2571   { "addB",             { AL, Ib }, 0 },
2572   { "addS",             { eAX, Iv }, 0 },
2573   { X86_64_TABLE (X86_64_06) },
2574   { X86_64_TABLE (X86_64_07) },
2575   /* 08 */
2576   { "orB",              { Ebh1, Gb }, 0 },
2577   { "orS",              { Evh1, Gv }, 0 },
2578   { "orB",              { Gb, EbS }, 0 },
2579   { "orS",              { Gv, EvS }, 0 },
2580   { "orB",              { AL, Ib }, 0 },
2581   { "orS",              { eAX, Iv }, 0 },
2582   { X86_64_TABLE (X86_64_0D) },
2583   { Bad_Opcode },       /* 0x0f extended opcode escape */
2584   /* 10 */
2585   { "adcB",             { Ebh1, Gb }, 0 },
2586   { "adcS",             { Evh1, Gv }, 0 },
2587   { "adcB",             { Gb, EbS }, 0 },
2588   { "adcS",             { Gv, EvS }, 0 },
2589   { "adcB",             { AL, Ib }, 0 },
2590   { "adcS",             { eAX, Iv }, 0 },
2591   { X86_64_TABLE (X86_64_16) },
2592   { X86_64_TABLE (X86_64_17) },
2593   /* 18 */
2594   { "sbbB",             { Ebh1, Gb }, 0 },
2595   { "sbbS",             { Evh1, Gv }, 0 },
2596   { "sbbB",             { Gb, EbS }, 0 },
2597   { "sbbS",             { Gv, EvS }, 0 },
2598   { "sbbB",             { AL, Ib }, 0 },
2599   { "sbbS",             { eAX, Iv }, 0 },
2600   { X86_64_TABLE (X86_64_1E) },
2601   { X86_64_TABLE (X86_64_1F) },
2602   /* 20 */
2603   { "andB",             { Ebh1, Gb }, 0 },
2604   { "andS",             { Evh1, Gv }, 0 },
2605   { "andB",             { Gb, EbS }, 0 },
2606   { "andS",             { Gv, EvS }, 0 },
2607   { "andB",             { AL, Ib }, 0 },
2608   { "andS",             { eAX, Iv }, 0 },
2609   { Bad_Opcode },       /* SEG ES prefix */
2610   { X86_64_TABLE (X86_64_27) },
2611   /* 28 */
2612   { "subB",             { Ebh1, Gb }, 0 },
2613   { "subS",             { Evh1, Gv }, 0 },
2614   { "subB",             { Gb, EbS }, 0 },
2615   { "subS",             { Gv, EvS }, 0 },
2616   { "subB",             { AL, Ib }, 0 },
2617   { "subS",             { eAX, Iv }, 0 },
2618   { Bad_Opcode },       /* SEG CS prefix */
2619   { X86_64_TABLE (X86_64_2F) },
2620   /* 30 */
2621   { "xorB",             { Ebh1, Gb }, 0 },
2622   { "xorS",             { Evh1, Gv }, 0 },
2623   { "xorB",             { Gb, EbS }, 0 },
2624   { "xorS",             { Gv, EvS }, 0 },
2625   { "xorB",             { AL, Ib }, 0 },
2626   { "xorS",             { eAX, Iv }, 0 },
2627   { Bad_Opcode },       /* SEG SS prefix */
2628   { X86_64_TABLE (X86_64_37) },
2629   /* 38 */
2630   { "cmpB",             { Eb, Gb }, 0 },
2631   { "cmpS",             { Ev, Gv }, 0 },
2632   { "cmpB",             { Gb, EbS }, 0 },
2633   { "cmpS",             { Gv, EvS }, 0 },
2634   { "cmpB",             { AL, Ib }, 0 },
2635   { "cmpS",             { eAX, Iv }, 0 },
2636   { Bad_Opcode },       /* SEG DS prefix */
2637   { X86_64_TABLE (X86_64_3F) },
2638   /* 40 */
2639   { "inc{S|}",          { RMeAX }, 0 },
2640   { "inc{S|}",          { RMeCX }, 0 },
2641   { "inc{S|}",          { RMeDX }, 0 },
2642   { "inc{S|}",          { RMeBX }, 0 },
2643   { "inc{S|}",          { RMeSP }, 0 },
2644   { "inc{S|}",          { RMeBP }, 0 },
2645   { "inc{S|}",          { RMeSI }, 0 },
2646   { "inc{S|}",          { RMeDI }, 0 },
2647   /* 48 */
2648   { "dec{S|}",          { RMeAX }, 0 },
2649   { "dec{S|}",          { RMeCX }, 0 },
2650   { "dec{S|}",          { RMeDX }, 0 },
2651   { "dec{S|}",          { RMeBX }, 0 },
2652   { "dec{S|}",          { RMeSP }, 0 },
2653   { "dec{S|}",          { RMeBP }, 0 },
2654   { "dec{S|}",          { RMeSI }, 0 },
2655   { "dec{S|}",          { RMeDI }, 0 },
2656   /* 50 */
2657   { "pushV",            { RMrAX }, 0 },
2658   { "pushV",            { RMrCX }, 0 },
2659   { "pushV",            { RMrDX }, 0 },
2660   { "pushV",            { RMrBX }, 0 },
2661   { "pushV",            { RMrSP }, 0 },
2662   { "pushV",            { RMrBP }, 0 },
2663   { "pushV",            { RMrSI }, 0 },
2664   { "pushV",            { RMrDI }, 0 },
2665   /* 58 */
2666   { "popV",             { RMrAX }, 0 },
2667   { "popV",             { RMrCX }, 0 },
2668   { "popV",             { RMrDX }, 0 },
2669   { "popV",             { RMrBX }, 0 },
2670   { "popV",             { RMrSP }, 0 },
2671   { "popV",             { RMrBP }, 0 },
2672   { "popV",             { RMrSI }, 0 },
2673   { "popV",             { RMrDI }, 0 },
2674   /* 60 */
2675   { X86_64_TABLE (X86_64_60) },
2676   { X86_64_TABLE (X86_64_61) },
2677   { X86_64_TABLE (X86_64_62) },
2678   { X86_64_TABLE (X86_64_63) },
2679   { Bad_Opcode },       /* seg fs */
2680   { Bad_Opcode },       /* seg gs */
2681   { Bad_Opcode },       /* op size prefix */
2682   { Bad_Opcode },       /* adr size prefix */
2683   /* 68 */
2684   { "pushT",            { sIv }, 0 },
2685   { "imulS",            { Gv, Ev, Iv }, 0 },
2686   { "pushT",            { sIbT }, 0 },
2687   { "imulS",            { Gv, Ev, sIb }, 0 },
2688   { "ins{b|}",          { Ybr, indirDX }, 0 },
2689   { X86_64_TABLE (X86_64_6D) },
2690   { "outs{b|}",         { indirDXr, Xb }, 0 },
2691   { X86_64_TABLE (X86_64_6F) },
2692   /* 70 */
2693   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2694   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2695   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2696   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2697   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2698   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2699   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2700   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2701   /* 78 */
2702   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2703   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2704   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2705   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2706   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2707   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2708   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2709   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2710   /* 80 */
2711   { REG_TABLE (REG_80) },
2712   { REG_TABLE (REG_81) },
2713   { X86_64_TABLE (X86_64_82) },
2714   { REG_TABLE (REG_83) },
2715   { "testB",            { Eb, Gb }, 0 },
2716   { "testS",            { Ev, Gv }, 0 },
2717   { "xchgB",            { Ebh2, Gb }, 0 },
2718   { "xchgS",            { Evh2, Gv }, 0 },
2719   /* 88 */
2720   { "movB",             { Ebh3, Gb }, 0 },
2721   { "movS",             { Evh3, Gv }, 0 },
2722   { "movB",             { Gb, EbS }, 0 },
2723   { "movS",             { Gv, EvS }, 0 },
2724   { "movD",             { Sv, Sw }, 0 },
2725   { MOD_TABLE (MOD_8D) },
2726   { "movD",             { Sw, Sv }, 0 },
2727   { REG_TABLE (REG_8F) },
2728   /* 90 */
2729   { PREFIX_TABLE (PREFIX_90) },
2730   { "xchgS",            { RMeCX, eAX }, 0 },
2731   { "xchgS",            { RMeDX, eAX }, 0 },
2732   { "xchgS",            { RMeBX, eAX }, 0 },
2733   { "xchgS",            { RMeSP, eAX }, 0 },
2734   { "xchgS",            { RMeBP, eAX }, 0 },
2735   { "xchgS",            { RMeSI, eAX }, 0 },
2736   { "xchgS",            { RMeDI, eAX }, 0 },
2737   /* 98 */
2738   { "cW{t|}R",          { XX }, 0 },
2739   { "cR{t|}O",          { XX }, 0 },
2740   { X86_64_TABLE (X86_64_9A) },
2741   { Bad_Opcode },       /* fwait */
2742   { "pushfT",           { XX }, 0 },
2743   { "popfT",            { XX }, 0 },
2744   { "sahf",             { XX }, 0 },
2745   { "lahf",             { XX }, 0 },
2746   /* a0 */
2747   { "mov%LB",           { AL, Ob }, 0 },
2748   { "mov%LS",           { eAX, Ov }, 0 },
2749   { "mov%LB",           { Ob, AL }, 0 },
2750   { "mov%LS",           { Ov, eAX }, 0 },
2751   { "movs{b|}",         { Ybr, Xb }, 0 },
2752   { "movs{R|}",         { Yvr, Xv }, 0 },
2753   { "cmps{b|}",         { Xb, Yb }, 0 },
2754   { "cmps{R|}",         { Xv, Yv }, 0 },
2755   /* a8 */
2756   { "testB",            { AL, Ib }, 0 },
2757   { "testS",            { eAX, Iv }, 0 },
2758   { "stosB",            { Ybr, AL }, 0 },
2759   { "stosS",            { Yvr, eAX }, 0 },
2760   { "lodsB",            { ALr, Xb }, 0 },
2761   { "lodsS",            { eAXr, Xv }, 0 },
2762   { "scasB",            { AL, Yb }, 0 },
2763   { "scasS",            { eAX, Yv }, 0 },
2764   /* b0 */
2765   { "movB",             { RMAL, Ib }, 0 },
2766   { "movB",             { RMCL, Ib }, 0 },
2767   { "movB",             { RMDL, Ib }, 0 },
2768   { "movB",             { RMBL, Ib }, 0 },
2769   { "movB",             { RMAH, Ib }, 0 },
2770   { "movB",             { RMCH, Ib }, 0 },
2771   { "movB",             { RMDH, Ib }, 0 },
2772   { "movB",             { RMBH, Ib }, 0 },
2773   /* b8 */
2774   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2775   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2776   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2777   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2778   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2779   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2780   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2781   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2782   /* c0 */
2783   { REG_TABLE (REG_C0) },
2784   { REG_TABLE (REG_C1) },
2785   { "retT",             { Iw, BND }, 0 },
2786   { "retT",             { BND }, 0 },
2787   { X86_64_TABLE (X86_64_C4) },
2788   { X86_64_TABLE (X86_64_C5) },
2789   { REG_TABLE (REG_C6) },
2790   { REG_TABLE (REG_C7) },
2791   /* c8 */
2792   { "enterT",           { Iw, Ib }, 0 },
2793   { "leaveT",           { XX }, 0 },
2794   { "Jret{|f}P",        { Iw }, 0 },
2795   { "Jret{|f}P",        { XX }, 0 },
2796   { "int3",             { XX }, 0 },
2797   { "int",              { Ib }, 0 },
2798   { X86_64_TABLE (X86_64_CE) },
2799   { "iret%LP",          { XX }, 0 },
2800   /* d0 */
2801   { REG_TABLE (REG_D0) },
2802   { REG_TABLE (REG_D1) },
2803   { REG_TABLE (REG_D2) },
2804   { REG_TABLE (REG_D3) },
2805   { X86_64_TABLE (X86_64_D4) },
2806   { X86_64_TABLE (X86_64_D5) },
2807   { Bad_Opcode },
2808   { "xlat",             { DSBX }, 0 },
2809   /* d8 */
2810   { FLOAT },
2811   { FLOAT },
2812   { FLOAT },
2813   { FLOAT },
2814   { FLOAT },
2815   { FLOAT },
2816   { FLOAT },
2817   { FLOAT },
2818   /* e0 */
2819   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2820   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2821   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2822   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2823   { "inB",              { AL, Ib }, 0 },
2824   { "inG",              { zAX, Ib }, 0 },
2825   { "outB",             { Ib, AL }, 0 },
2826   { "outG",             { Ib, zAX }, 0 },
2827   /* e8 */
2828   { X86_64_TABLE (X86_64_E8) },
2829   { X86_64_TABLE (X86_64_E9) },
2830   { X86_64_TABLE (X86_64_EA) },
2831   { "jmp",              { Jb, BND }, 0 },
2832   { "inB",              { AL, indirDX }, 0 },
2833   { "inG",              { zAX, indirDX }, 0 },
2834   { "outB",             { indirDX, AL }, 0 },
2835   { "outG",             { indirDX, zAX }, 0 },
2836   /* f0 */
2837   { Bad_Opcode },       /* lock prefix */
2838   { "icebp",            { XX }, 0 },
2839   { Bad_Opcode },       /* repne */
2840   { Bad_Opcode },       /* repz */
2841   { "hlt",              { XX }, 0 },
2842   { "cmc",              { XX }, 0 },
2843   { REG_TABLE (REG_F6) },
2844   { REG_TABLE (REG_F7) },
2845   /* f8 */
2846   { "clc",              { XX }, 0 },
2847   { "stc",              { XX }, 0 },
2848   { "cli",              { XX }, 0 },
2849   { "sti",              { XX }, 0 },
2850   { "cld",              { XX }, 0 },
2851   { "std",              { XX }, 0 },
2852   { REG_TABLE (REG_FE) },
2853   { REG_TABLE (REG_FF) },
2854 };
2855
2856 static const struct dis386 dis386_twobyte[] = {
2857   /* 00 */
2858   { REG_TABLE (REG_0F00 ) },
2859   { REG_TABLE (REG_0F01 ) },
2860   { "larS",             { Gv, Ew }, 0 },
2861   { "lslS",             { Gv, Ew }, 0 },
2862   { Bad_Opcode },
2863   { "syscall",          { XX }, 0 },
2864   { "clts",             { XX }, 0 },
2865   { "sysret%LP",                { XX }, 0 },
2866   /* 08 */
2867   { "invd",             { XX }, 0 },
2868   { "wbinvd",           { XX }, 0 },
2869   { Bad_Opcode },
2870   { "ud2",              { XX }, 0 },
2871   { Bad_Opcode },
2872   { REG_TABLE (REG_0F0D) },
2873   { "femms",            { XX }, 0 },
2874   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2875   /* 10 */
2876   { PREFIX_TABLE (PREFIX_0F10) },
2877   { PREFIX_TABLE (PREFIX_0F11) },
2878   { PREFIX_TABLE (PREFIX_0F12) },
2879   { MOD_TABLE (MOD_0F13) },
2880   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2881   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2882   { PREFIX_TABLE (PREFIX_0F16) },
2883   { MOD_TABLE (MOD_0F17) },
2884   /* 18 */
2885   { REG_TABLE (REG_0F18) },
2886   { "nopQ",             { Ev }, 0 },
2887   { PREFIX_TABLE (PREFIX_0F1A) },
2888   { PREFIX_TABLE (PREFIX_0F1B) },
2889   { "nopQ",             { Ev }, 0 },
2890   { "nopQ",             { Ev }, 0 },
2891   { PREFIX_TABLE (PREFIX_0F1E) },
2892   { "nopQ",             { Ev }, 0 },
2893   /* 20 */
2894   { "movZ",             { Rm, Cm }, 0 },
2895   { "movZ",             { Rm, Dm }, 0 },
2896   { "movZ",             { Cm, Rm }, 0 },
2897   { "movZ",             { Dm, Rm }, 0 },
2898   { MOD_TABLE (MOD_0F24) },
2899   { Bad_Opcode },
2900   { MOD_TABLE (MOD_0F26) },
2901   { Bad_Opcode },
2902   /* 28 */
2903   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2904   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2905   { PREFIX_TABLE (PREFIX_0F2A) },
2906   { PREFIX_TABLE (PREFIX_0F2B) },
2907   { PREFIX_TABLE (PREFIX_0F2C) },
2908   { PREFIX_TABLE (PREFIX_0F2D) },
2909   { PREFIX_TABLE (PREFIX_0F2E) },
2910   { PREFIX_TABLE (PREFIX_0F2F) },
2911   /* 30 */
2912   { "wrmsr",            { XX }, 0 },
2913   { "rdtsc",            { XX }, 0 },
2914   { "rdmsr",            { XX }, 0 },
2915   { "rdpmc",            { XX }, 0 },
2916   { "sysenter",         { XX }, 0 },
2917   { "sysexit",          { XX }, 0 },
2918   { Bad_Opcode },
2919   { "getsec",           { XX }, 0 },
2920   /* 38 */
2921   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2922   { Bad_Opcode },
2923   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2924   { Bad_Opcode },
2925   { Bad_Opcode },
2926   { Bad_Opcode },
2927   { Bad_Opcode },
2928   { Bad_Opcode },
2929   /* 40 */
2930   { "cmovoS",           { Gv, Ev }, 0 },
2931   { "cmovnoS",          { Gv, Ev }, 0 },
2932   { "cmovbS",           { Gv, Ev }, 0 },
2933   { "cmovaeS",          { Gv, Ev }, 0 },
2934   { "cmoveS",           { Gv, Ev }, 0 },
2935   { "cmovneS",          { Gv, Ev }, 0 },
2936   { "cmovbeS",          { Gv, Ev }, 0 },
2937   { "cmovaS",           { Gv, Ev }, 0 },
2938   /* 48 */
2939   { "cmovsS",           { Gv, Ev }, 0 },
2940   { "cmovnsS",          { Gv, Ev }, 0 },
2941   { "cmovpS",           { Gv, Ev }, 0 },
2942   { "cmovnpS",          { Gv, Ev }, 0 },
2943   { "cmovlS",           { Gv, Ev }, 0 },
2944   { "cmovgeS",          { Gv, Ev }, 0 },
2945   { "cmovleS",          { Gv, Ev }, 0 },
2946   { "cmovgS",           { Gv, Ev }, 0 },
2947   /* 50 */
2948   { MOD_TABLE (MOD_0F51) },
2949   { PREFIX_TABLE (PREFIX_0F51) },
2950   { PREFIX_TABLE (PREFIX_0F52) },
2951   { PREFIX_TABLE (PREFIX_0F53) },
2952   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2953   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2954   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2955   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2956   /* 58 */
2957   { PREFIX_TABLE (PREFIX_0F58) },
2958   { PREFIX_TABLE (PREFIX_0F59) },
2959   { PREFIX_TABLE (PREFIX_0F5A) },
2960   { PREFIX_TABLE (PREFIX_0F5B) },
2961   { PREFIX_TABLE (PREFIX_0F5C) },
2962   { PREFIX_TABLE (PREFIX_0F5D) },
2963   { PREFIX_TABLE (PREFIX_0F5E) },
2964   { PREFIX_TABLE (PREFIX_0F5F) },
2965   /* 60 */
2966   { PREFIX_TABLE (PREFIX_0F60) },
2967   { PREFIX_TABLE (PREFIX_0F61) },
2968   { PREFIX_TABLE (PREFIX_0F62) },
2969   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2970   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2971   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2972   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2973   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2974   /* 68 */
2975   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2976   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2977   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2978   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2979   { PREFIX_TABLE (PREFIX_0F6C) },
2980   { PREFIX_TABLE (PREFIX_0F6D) },
2981   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2982   { PREFIX_TABLE (PREFIX_0F6F) },
2983   /* 70 */
2984   { PREFIX_TABLE (PREFIX_0F70) },
2985   { REG_TABLE (REG_0F71) },
2986   { REG_TABLE (REG_0F72) },
2987   { REG_TABLE (REG_0F73) },
2988   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2989   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2990   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2991   { "emms",             { XX }, PREFIX_OPCODE },
2992   /* 78 */
2993   { PREFIX_TABLE (PREFIX_0F78) },
2994   { PREFIX_TABLE (PREFIX_0F79) },
2995   { Bad_Opcode },
2996   { Bad_Opcode },
2997   { PREFIX_TABLE (PREFIX_0F7C) },
2998   { PREFIX_TABLE (PREFIX_0F7D) },
2999   { PREFIX_TABLE (PREFIX_0F7E) },
3000   { PREFIX_TABLE (PREFIX_0F7F) },
3001   /* 80 */
3002   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
3003   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
3004   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
3005   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
3006   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
3007   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
3008   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
3009   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
3010   /* 88 */
3011   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
3012   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
3013   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
3014   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
3015   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
3016   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
3017   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
3018   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
3019   /* 90 */
3020   { "seto",             { Eb }, 0 },
3021   { "setno",            { Eb }, 0 },
3022   { "setb",             { Eb }, 0 },
3023   { "setae",            { Eb }, 0 },
3024   { "sete",             { Eb }, 0 },
3025   { "setne",            { Eb }, 0 },
3026   { "setbe",            { Eb }, 0 },
3027   { "seta",             { Eb }, 0 },
3028   /* 98 */
3029   { "sets",             { Eb }, 0 },
3030   { "setns",            { Eb }, 0 },
3031   { "setp",             { Eb }, 0 },
3032   { "setnp",            { Eb }, 0 },
3033   { "setl",             { Eb }, 0 },
3034   { "setge",            { Eb }, 0 },
3035   { "setle",            { Eb }, 0 },
3036   { "setg",             { Eb }, 0 },
3037   /* a0 */
3038   { "pushT",            { fs }, 0 },
3039   { "popT",             { fs }, 0 },
3040   { "cpuid",            { XX }, 0 },
3041   { "btS",              { Ev, Gv }, 0 },
3042   { "shldS",            { Ev, Gv, Ib }, 0 },
3043   { "shldS",            { Ev, Gv, CL }, 0 },
3044   { REG_TABLE (REG_0FA6) },
3045   { REG_TABLE (REG_0FA7) },
3046   /* a8 */
3047   { "pushT",            { gs }, 0 },
3048   { "popT",             { gs }, 0 },
3049   { "rsm",              { XX }, 0 },
3050   { "btsS",             { Evh1, Gv }, 0 },
3051   { "shrdS",            { Ev, Gv, Ib }, 0 },
3052   { "shrdS",            { Ev, Gv, CL }, 0 },
3053   { REG_TABLE (REG_0FAE) },
3054   { "imulS",            { Gv, Ev }, 0 },
3055   /* b0 */
3056   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3057   { "cmpxchgS",         { Evh1, Gv }, 0 },
3058   { MOD_TABLE (MOD_0FB2) },
3059   { "btrS",             { Evh1, Gv }, 0 },
3060   { MOD_TABLE (MOD_0FB4) },
3061   { MOD_TABLE (MOD_0FB5) },
3062   { "movz{bR|x}",       { Gv, Eb }, 0 },
3063   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3064   /* b8 */
3065   { PREFIX_TABLE (PREFIX_0FB8) },
3066   { "ud1",              { XX }, 0 },
3067   { REG_TABLE (REG_0FBA) },
3068   { "btcS",             { Evh1, Gv }, 0 },
3069   { PREFIX_TABLE (PREFIX_0FBC) },
3070   { PREFIX_TABLE (PREFIX_0FBD) },
3071   { "movs{bR|x}",       { Gv, Eb }, 0 },
3072   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3073   /* c0 */
3074   { "xaddB",            { Ebh1, Gb }, 0 },
3075   { "xaddS",            { Evh1, Gv }, 0 },
3076   { PREFIX_TABLE (PREFIX_0FC2) },
3077   { MOD_TABLE (MOD_0FC3) },
3078   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3079   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3080   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3081   { REG_TABLE (REG_0FC7) },
3082   /* c8 */
3083   { "bswap",            { RMeAX }, 0 },
3084   { "bswap",            { RMeCX }, 0 },
3085   { "bswap",            { RMeDX }, 0 },
3086   { "bswap",            { RMeBX }, 0 },
3087   { "bswap",            { RMeSP }, 0 },
3088   { "bswap",            { RMeBP }, 0 },
3089   { "bswap",            { RMeSI }, 0 },
3090   { "bswap",            { RMeDI }, 0 },
3091   /* d0 */
3092   { PREFIX_TABLE (PREFIX_0FD0) },
3093   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3094   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3095   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3096   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3097   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3098   { PREFIX_TABLE (PREFIX_0FD6) },
3099   { MOD_TABLE (MOD_0FD7) },
3100   /* d8 */
3101   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3102   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3103   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3104   { "pand",             { MX, EM }, PREFIX_OPCODE },
3105   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3106   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3107   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3108   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3109   /* e0 */
3110   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3111   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3112   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3113   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3114   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3115   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3116   { PREFIX_TABLE (PREFIX_0FE6) },
3117   { PREFIX_TABLE (PREFIX_0FE7) },
3118   /* e8 */
3119   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3120   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3121   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3122   { "por",              { MX, EM }, PREFIX_OPCODE },
3123   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3124   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3125   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3126   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3127   /* f0 */
3128   { PREFIX_TABLE (PREFIX_0FF0) },
3129   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3130   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3131   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3132   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3133   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3134   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3135   { PREFIX_TABLE (PREFIX_0FF7) },
3136   /* f8 */
3137   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3138   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3139   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3140   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3141   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3142   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3143   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3144   { Bad_Opcode },
3145 };
3146
3147 static const unsigned char onebyte_has_modrm[256] = {
3148   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3149   /*       -------------------------------        */
3150   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3151   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3152   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3153   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3154   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3155   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3156   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3157   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3158   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3159   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3160   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3161   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3162   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3163   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3164   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3165   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3166   /*       -------------------------------        */
3167   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3168 };
3169
3170 static const unsigned char twobyte_has_modrm[256] = {
3171   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3172   /*       -------------------------------        */
3173   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3174   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3175   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3176   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3177   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3178   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3179   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3180   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3181   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3182   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3183   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3184   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3185   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3186   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3187   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3188   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3189   /*       -------------------------------        */
3190   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3191 };
3192
3193 static char obuf[100];
3194 static char *obufp;
3195 static char *mnemonicendp;
3196 static char scratchbuf[100];
3197 static unsigned char *start_codep;
3198 static unsigned char *insn_codep;
3199 static unsigned char *codep;
3200 static unsigned char *end_codep;
3201 static int last_lock_prefix;
3202 static int last_repz_prefix;
3203 static int last_repnz_prefix;
3204 static int last_data_prefix;
3205 static int last_addr_prefix;
3206 static int last_rex_prefix;
3207 static int last_seg_prefix;
3208 static int fwait_prefix;
3209 /* The active segment register prefix.  */
3210 static int active_seg_prefix;
3211 #define MAX_CODE_LENGTH 15
3212 /* We can up to 14 prefixes since the maximum instruction length is
3213    15bytes.  */
3214 static int all_prefixes[MAX_CODE_LENGTH - 1];
3215 static disassemble_info *the_info;
3216 static struct
3217   {
3218     int mod;
3219     int reg;
3220     int rm;
3221   }
3222 modrm;
3223 static unsigned char need_modrm;
3224 static struct
3225   {
3226     int scale;
3227     int index;
3228     int base;
3229   }
3230 sib;
3231 static struct
3232   {
3233     int register_specifier;
3234     int length;
3235     int prefix;
3236     int w;
3237     int evex;
3238     int r;
3239     int v;
3240     int mask_register_specifier;
3241     int zeroing;
3242     int ll;
3243     int b;
3244   }
3245 vex;
3246 static unsigned char need_vex;
3247 static unsigned char need_vex_reg;
3248 static unsigned char vex_w_done;
3249
3250 struct op
3251   {
3252     const char *name;
3253     unsigned int len;
3254   };
3255
3256 /* If we are accessing mod/rm/reg without need_modrm set, then the
3257    values are stale.  Hitting this abort likely indicates that you
3258    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3259 #define MODRM_CHECK  if (!need_modrm) abort ()
3260
3261 static const char **names64;
3262 static const char **names32;
3263 static const char **names16;
3264 static const char **names8;
3265 static const char **names8rex;
3266 static const char **names_seg;
3267 static const char *index64;
3268 static const char *index32;
3269 static const char **index16;
3270 static const char **names_bnd;
3271
3272 static const char *intel_names64[] = {
3273   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3274   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3275 };
3276 static const char *intel_names32[] = {
3277   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3278   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3279 };
3280 static const char *intel_names16[] = {
3281   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3282   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3283 };
3284 static const char *intel_names8[] = {
3285   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3286 };
3287 static const char *intel_names8rex[] = {
3288   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3289   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3290 };
3291 static const char *intel_names_seg[] = {
3292   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3293 };
3294 static const char *intel_index64 = "riz";
3295 static const char *intel_index32 = "eiz";
3296 static const char *intel_index16[] = {
3297   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3298 };
3299
3300 static const char *att_names64[] = {
3301   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3302   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3303 };
3304 static const char *att_names32[] = {
3305   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3306   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3307 };
3308 static const char *att_names16[] = {
3309   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3310   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3311 };
3312 static const char *att_names8[] = {
3313   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3314 };
3315 static const char *att_names8rex[] = {
3316   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3317   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3318 };
3319 static const char *att_names_seg[] = {
3320   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3321 };
3322 static const char *att_index64 = "%riz";
3323 static const char *att_index32 = "%eiz";
3324 static const char *att_index16[] = {
3325   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3326 };
3327
3328 static const char **names_mm;
3329 static const char *intel_names_mm[] = {
3330   "mm0", "mm1", "mm2", "mm3",
3331   "mm4", "mm5", "mm6", "mm7"
3332 };
3333 static const char *att_names_mm[] = {
3334   "%mm0", "%mm1", "%mm2", "%mm3",
3335   "%mm4", "%mm5", "%mm6", "%mm7"
3336 };
3337
3338 static const char *intel_names_bnd[] = {
3339   "bnd0", "bnd1", "bnd2", "bnd3"
3340 };
3341
3342 static const char *att_names_bnd[] = {
3343   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3344 };
3345
3346 static const char **names_xmm;
3347 static const char *intel_names_xmm[] = {
3348   "xmm0", "xmm1", "xmm2", "xmm3",
3349   "xmm4", "xmm5", "xmm6", "xmm7",
3350   "xmm8", "xmm9", "xmm10", "xmm11",
3351   "xmm12", "xmm13", "xmm14", "xmm15",
3352   "xmm16", "xmm17", "xmm18", "xmm19",
3353   "xmm20", "xmm21", "xmm22", "xmm23",
3354   "xmm24", "xmm25", "xmm26", "xmm27",
3355   "xmm28", "xmm29", "xmm30", "xmm31"
3356 };
3357 static const char *att_names_xmm[] = {
3358   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3359   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3360   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3361   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3362   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3363   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3364   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3365   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3366 };
3367
3368 static const char **names_ymm;
3369 static const char *intel_names_ymm[] = {
3370   "ymm0", "ymm1", "ymm2", "ymm3",
3371   "ymm4", "ymm5", "ymm6", "ymm7",
3372   "ymm8", "ymm9", "ymm10", "ymm11",
3373   "ymm12", "ymm13", "ymm14", "ymm15",
3374   "ymm16", "ymm17", "ymm18", "ymm19",
3375   "ymm20", "ymm21", "ymm22", "ymm23",
3376   "ymm24", "ymm25", "ymm26", "ymm27",
3377   "ymm28", "ymm29", "ymm30", "ymm31"
3378 };
3379 static const char *att_names_ymm[] = {
3380   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3381   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3382   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3383   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3384   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3385   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3386   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3387   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3388 };
3389
3390 static const char **names_zmm;
3391 static const char *intel_names_zmm[] = {
3392   "zmm0", "zmm1", "zmm2", "zmm3",
3393   "zmm4", "zmm5", "zmm6", "zmm7",
3394   "zmm8", "zmm9", "zmm10", "zmm11",
3395   "zmm12", "zmm13", "zmm14", "zmm15",
3396   "zmm16", "zmm17", "zmm18", "zmm19",
3397   "zmm20", "zmm21", "zmm22", "zmm23",
3398   "zmm24", "zmm25", "zmm26", "zmm27",
3399   "zmm28", "zmm29", "zmm30", "zmm31"
3400 };
3401 static const char *att_names_zmm[] = {
3402   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3403   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3404   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3405   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3406   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3407   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3408   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3409   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3410 };
3411
3412 static const char **names_mask;
3413 static const char *intel_names_mask[] = {
3414   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3415 };
3416 static const char *att_names_mask[] = {
3417   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3418 };
3419
3420 static const char *names_rounding[] =
3421 {
3422   "{rn-sae}",
3423   "{rd-sae}",
3424   "{ru-sae}",
3425   "{rz-sae}"
3426 };
3427
3428 static const struct dis386 reg_table[][8] = {
3429   /* REG_80 */
3430   {
3431     { "addA",   { Ebh1, Ib }, 0 },
3432     { "orA",    { Ebh1, Ib }, 0 },
3433     { "adcA",   { Ebh1, Ib }, 0 },
3434     { "sbbA",   { Ebh1, Ib }, 0 },
3435     { "andA",   { Ebh1, Ib }, 0 },
3436     { "subA",   { Ebh1, Ib }, 0 },
3437     { "xorA",   { Ebh1, Ib }, 0 },
3438     { "cmpA",   { Eb, Ib }, 0 },
3439   },
3440   /* REG_81 */
3441   {
3442     { "addQ",   { Evh1, Iv }, 0 },
3443     { "orQ",    { Evh1, Iv }, 0 },
3444     { "adcQ",   { Evh1, Iv }, 0 },
3445     { "sbbQ",   { Evh1, Iv }, 0 },
3446     { "andQ",   { Evh1, Iv }, 0 },
3447     { "subQ",   { Evh1, Iv }, 0 },
3448     { "xorQ",   { Evh1, Iv }, 0 },
3449     { "cmpQ",   { Ev, Iv }, 0 },
3450   },
3451   /* REG_83 */
3452   {
3453     { "addQ",   { Evh1, sIb }, 0 },
3454     { "orQ",    { Evh1, sIb }, 0 },
3455     { "adcQ",   { Evh1, sIb }, 0 },
3456     { "sbbQ",   { Evh1, sIb }, 0 },
3457     { "andQ",   { Evh1, sIb }, 0 },
3458     { "subQ",   { Evh1, sIb }, 0 },
3459     { "xorQ",   { Evh1, sIb }, 0 },
3460     { "cmpQ",   { Ev, sIb }, 0 },
3461   },
3462   /* REG_8F */
3463   {
3464     { "popU",   { stackEv }, 0 },
3465     { XOP_8F_TABLE (XOP_09) },
3466     { Bad_Opcode },
3467     { Bad_Opcode },
3468     { Bad_Opcode },
3469     { XOP_8F_TABLE (XOP_09) },
3470   },
3471   /* REG_C0 */
3472   {
3473     { "rolA",   { Eb, Ib }, 0 },
3474     { "rorA",   { Eb, Ib }, 0 },
3475     { "rclA",   { Eb, Ib }, 0 },
3476     { "rcrA",   { Eb, Ib }, 0 },
3477     { "shlA",   { Eb, Ib }, 0 },
3478     { "shrA",   { Eb, Ib }, 0 },
3479     { "shlA",   { Eb, Ib }, 0 },
3480     { "sarA",   { Eb, Ib }, 0 },
3481   },
3482   /* REG_C1 */
3483   {
3484     { "rolQ",   { Ev, Ib }, 0 },
3485     { "rorQ",   { Ev, Ib }, 0 },
3486     { "rclQ",   { Ev, Ib }, 0 },
3487     { "rcrQ",   { Ev, Ib }, 0 },
3488     { "shlQ",   { Ev, Ib }, 0 },
3489     { "shrQ",   { Ev, Ib }, 0 },
3490     { "shlQ",   { Ev, Ib }, 0 },
3491     { "sarQ",   { Ev, Ib }, 0 },
3492   },
3493   /* REG_C6 */
3494   {
3495     { "movA",   { Ebh3, Ib }, 0 },
3496     { Bad_Opcode },
3497     { Bad_Opcode },
3498     { Bad_Opcode },
3499     { Bad_Opcode },
3500     { Bad_Opcode },
3501     { Bad_Opcode },
3502     { MOD_TABLE (MOD_C6_REG_7) },
3503   },
3504   /* REG_C7 */
3505   {
3506     { "movQ",   { Evh3, Iv }, 0 },
3507     { Bad_Opcode },
3508     { Bad_Opcode },
3509     { Bad_Opcode },
3510     { Bad_Opcode },
3511     { Bad_Opcode },
3512     { Bad_Opcode },
3513     { MOD_TABLE (MOD_C7_REG_7) },
3514   },
3515   /* REG_D0 */
3516   {
3517     { "rolA",   { Eb, I1 }, 0 },
3518     { "rorA",   { Eb, I1 }, 0 },
3519     { "rclA",   { Eb, I1 }, 0 },
3520     { "rcrA",   { Eb, I1 }, 0 },
3521     { "shlA",   { Eb, I1 }, 0 },
3522     { "shrA",   { Eb, I1 }, 0 },
3523     { "shlA",   { Eb, I1 }, 0 },
3524     { "sarA",   { Eb, I1 }, 0 },
3525   },
3526   /* REG_D1 */
3527   {
3528     { "rolQ",   { Ev, I1 }, 0 },
3529     { "rorQ",   { Ev, I1 }, 0 },
3530     { "rclQ",   { Ev, I1 }, 0 },
3531     { "rcrQ",   { Ev, I1 }, 0 },
3532     { "shlQ",   { Ev, I1 }, 0 },
3533     { "shrQ",   { Ev, I1 }, 0 },
3534     { "shlQ",   { Ev, I1 }, 0 },
3535     { "sarQ",   { Ev, I1 }, 0 },
3536   },
3537   /* REG_D2 */
3538   {
3539     { "rolA",   { Eb, CL }, 0 },
3540     { "rorA",   { Eb, CL }, 0 },
3541     { "rclA",   { Eb, CL }, 0 },
3542     { "rcrA",   { Eb, CL }, 0 },
3543     { "shlA",   { Eb, CL }, 0 },
3544     { "shrA",   { Eb, CL }, 0 },
3545     { "shlA",   { Eb, CL }, 0 },
3546     { "sarA",   { Eb, CL }, 0 },
3547   },
3548   /* REG_D3 */
3549   {
3550     { "rolQ",   { Ev, CL }, 0 },
3551     { "rorQ",   { Ev, CL }, 0 },
3552     { "rclQ",   { Ev, CL }, 0 },
3553     { "rcrQ",   { Ev, CL }, 0 },
3554     { "shlQ",   { Ev, CL }, 0 },
3555     { "shrQ",   { Ev, CL }, 0 },
3556     { "shlQ",   { Ev, CL }, 0 },
3557     { "sarQ",   { Ev, CL }, 0 },
3558   },
3559   /* REG_F6 */
3560   {
3561     { "testA",  { Eb, Ib }, 0 },
3562     { "testA",  { Eb, Ib }, 0 },
3563     { "notA",   { Ebh1 }, 0 },
3564     { "negA",   { Ebh1 }, 0 },
3565     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3566     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3567     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3568     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3569   },
3570   /* REG_F7 */
3571   {
3572     { "testQ",  { Ev, Iv }, 0 },
3573     { "testQ",  { Ev, Iv }, 0 },
3574     { "notQ",   { Evh1 }, 0 },
3575     { "negQ",   { Evh1 }, 0 },
3576     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3577     { "imulQ",  { Ev }, 0 },
3578     { "divQ",   { Ev }, 0 },
3579     { "idivQ",  { Ev }, 0 },
3580   },
3581   /* REG_FE */
3582   {
3583     { "incA",   { Ebh1 }, 0 },
3584     { "decA",   { Ebh1 }, 0 },
3585   },
3586   /* REG_FF */
3587   {
3588     { "incQ",   { Evh1 }, 0 },
3589     { "decQ",   { Evh1 }, 0 },
3590     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3591     { MOD_TABLE (MOD_FF_REG_3) },
3592     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3593     { MOD_TABLE (MOD_FF_REG_5) },
3594     { "pushU",  { stackEv }, 0 },
3595     { Bad_Opcode },
3596   },
3597   /* REG_0F00 */
3598   {
3599     { "sldtD",  { Sv }, 0 },
3600     { "strD",   { Sv }, 0 },
3601     { "lldt",   { Ew }, 0 },
3602     { "ltr",    { Ew }, 0 },
3603     { "verr",   { Ew }, 0 },
3604     { "verw",   { Ew }, 0 },
3605     { Bad_Opcode },
3606     { Bad_Opcode },
3607   },
3608   /* REG_0F01 */
3609   {
3610     { MOD_TABLE (MOD_0F01_REG_0) },
3611     { MOD_TABLE (MOD_0F01_REG_1) },
3612     { MOD_TABLE (MOD_0F01_REG_2) },
3613     { MOD_TABLE (MOD_0F01_REG_3) },
3614     { "smswD",  { Sv }, 0 },
3615     { MOD_TABLE (MOD_0F01_REG_5) },
3616     { "lmsw",   { Ew }, 0 },
3617     { MOD_TABLE (MOD_0F01_REG_7) },
3618   },
3619   /* REG_0F0D */
3620   {
3621     { "prefetch",       { Mb }, 0 },
3622     { "prefetchw",      { Mb }, 0 },
3623     { "prefetchwt1",    { Mb }, 0 },
3624     { "prefetch",       { Mb }, 0 },
3625     { "prefetch",       { Mb }, 0 },
3626     { "prefetch",       { Mb }, 0 },
3627     { "prefetch",       { Mb }, 0 },
3628     { "prefetch",       { Mb }, 0 },
3629   },
3630   /* REG_0F18 */
3631   {
3632     { MOD_TABLE (MOD_0F18_REG_0) },
3633     { MOD_TABLE (MOD_0F18_REG_1) },
3634     { MOD_TABLE (MOD_0F18_REG_2) },
3635     { MOD_TABLE (MOD_0F18_REG_3) },
3636     { MOD_TABLE (MOD_0F18_REG_4) },
3637     { MOD_TABLE (MOD_0F18_REG_5) },
3638     { MOD_TABLE (MOD_0F18_REG_6) },
3639     { MOD_TABLE (MOD_0F18_REG_7) },
3640   },
3641   /* REG_0F1E_MOD_3 */
3642   {
3643     { "nopQ",           { Ev }, 0 },
3644     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3645     { "nopQ",           { Ev }, 0 },
3646     { "nopQ",           { Ev }, 0 },
3647     { "nopQ",           { Ev }, 0 },
3648     { "nopQ",           { Ev }, 0 },
3649     { "nopQ",           { Ev }, 0 },
3650     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3651   },
3652   /* REG_0F71 */
3653   {
3654     { Bad_Opcode },
3655     { Bad_Opcode },
3656     { MOD_TABLE (MOD_0F71_REG_2) },
3657     { Bad_Opcode },
3658     { MOD_TABLE (MOD_0F71_REG_4) },
3659     { Bad_Opcode },
3660     { MOD_TABLE (MOD_0F71_REG_6) },
3661   },
3662   /* REG_0F72 */
3663   {
3664     { Bad_Opcode },
3665     { Bad_Opcode },
3666     { MOD_TABLE (MOD_0F72_REG_2) },
3667     { Bad_Opcode },
3668     { MOD_TABLE (MOD_0F72_REG_4) },
3669     { Bad_Opcode },
3670     { MOD_TABLE (MOD_0F72_REG_6) },
3671   },
3672   /* REG_0F73 */
3673   {
3674     { Bad_Opcode },
3675     { Bad_Opcode },
3676     { MOD_TABLE (MOD_0F73_REG_2) },
3677     { MOD_TABLE (MOD_0F73_REG_3) },
3678     { Bad_Opcode },
3679     { Bad_Opcode },
3680     { MOD_TABLE (MOD_0F73_REG_6) },
3681     { MOD_TABLE (MOD_0F73_REG_7) },
3682   },
3683   /* REG_0FA6 */
3684   {
3685     { "montmul",        { { OP_0f07, 0 } }, 0 },
3686     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3687     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3688   },
3689   /* REG_0FA7 */
3690   {
3691     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3692     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3693     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3694     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3695     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3696     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3697   },
3698   /* REG_0FAE */
3699   {
3700     { MOD_TABLE (MOD_0FAE_REG_0) },
3701     { MOD_TABLE (MOD_0FAE_REG_1) },
3702     { MOD_TABLE (MOD_0FAE_REG_2) },
3703     { MOD_TABLE (MOD_0FAE_REG_3) },
3704     { MOD_TABLE (MOD_0FAE_REG_4) },
3705     { MOD_TABLE (MOD_0FAE_REG_5) },
3706     { MOD_TABLE (MOD_0FAE_REG_6) },
3707     { MOD_TABLE (MOD_0FAE_REG_7) },
3708   },
3709   /* REG_0FBA */
3710   {
3711     { Bad_Opcode },
3712     { Bad_Opcode },
3713     { Bad_Opcode },
3714     { Bad_Opcode },
3715     { "btQ",    { Ev, Ib }, 0 },
3716     { "btsQ",   { Evh1, Ib }, 0 },
3717     { "btrQ",   { Evh1, Ib }, 0 },
3718     { "btcQ",   { Evh1, Ib }, 0 },
3719   },
3720   /* REG_0FC7 */
3721   {
3722     { Bad_Opcode },
3723     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3724     { Bad_Opcode },
3725     { MOD_TABLE (MOD_0FC7_REG_3) },
3726     { MOD_TABLE (MOD_0FC7_REG_4) },
3727     { MOD_TABLE (MOD_0FC7_REG_5) },
3728     { MOD_TABLE (MOD_0FC7_REG_6) },
3729     { MOD_TABLE (MOD_0FC7_REG_7) },
3730   },
3731   /* REG_VEX_0F71 */
3732   {
3733     { Bad_Opcode },
3734     { Bad_Opcode },
3735     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3736     { Bad_Opcode },
3737     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3738     { Bad_Opcode },
3739     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3740   },
3741   /* REG_VEX_0F72 */
3742   {
3743     { Bad_Opcode },
3744     { Bad_Opcode },
3745     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3746     { Bad_Opcode },
3747     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3748     { Bad_Opcode },
3749     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3750   },
3751   /* REG_VEX_0F73 */
3752   {
3753     { Bad_Opcode },
3754     { Bad_Opcode },
3755     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3756     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3757     { Bad_Opcode },
3758     { Bad_Opcode },
3759     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3760     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3761   },
3762   /* REG_VEX_0FAE */
3763   {
3764     { Bad_Opcode },
3765     { Bad_Opcode },
3766     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3767     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3768   },
3769   /* REG_VEX_0F38F3 */
3770   {
3771     { Bad_Opcode },
3772     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3773     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3774     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3775   },
3776   /* REG_XOP_LWPCB */
3777   {
3778     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3779     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3780   },
3781   /* REG_XOP_LWP */
3782   {
3783     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3784     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3785   },
3786   /* REG_XOP_TBM_01 */
3787   {
3788     { Bad_Opcode },
3789     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3790     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3791     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3792     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3793     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3794     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3795     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3796   },
3797   /* REG_XOP_TBM_02 */
3798   {
3799     { Bad_Opcode },
3800     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3801     { Bad_Opcode },
3802     { Bad_Opcode },
3803     { Bad_Opcode },
3804     { Bad_Opcode },
3805     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3806   },
3807 #define NEED_REG_TABLE
3808 #include "i386-dis-evex.h"
3809 #undef NEED_REG_TABLE
3810 };
3811
3812 static const struct dis386 prefix_table[][4] = {
3813   /* PREFIX_90 */
3814   {
3815     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3816     { "pause", { XX }, 0 },
3817     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3818     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3819   },
3820
3821   /* PREFIX_MOD_0_0F01_REG_5 */
3822   {
3823     { Bad_Opcode },
3824     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3825   },
3826
3827   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3828   {
3829     { Bad_Opcode },
3830     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3831   },
3832
3833   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3834   {
3835     { Bad_Opcode },
3836     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3837   },
3838
3839   /* PREFIX_0F10 */
3840   {
3841     { "movups", { XM, EXx }, PREFIX_OPCODE },
3842     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3843     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3844     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3845   },
3846
3847   /* PREFIX_0F11 */
3848   {
3849     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3850     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3851     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3852     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3853   },
3854
3855   /* PREFIX_0F12 */
3856   {
3857     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3858     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3859     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3860     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3861   },
3862
3863   /* PREFIX_0F16 */
3864   {
3865     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3866     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3867     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3868   },
3869
3870   /* PREFIX_0F1A */
3871   {
3872     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3873     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3874     { "bndmov", { Gbnd, Ebnd }, 0 },
3875     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3876   },
3877
3878   /* PREFIX_0F1B */
3879   {
3880     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3881     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3882     { "bndmov", { Ebnd, Gbnd }, 0 },
3883     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3884   },
3885
3886   /* PREFIX_0F1E */
3887   {
3888     { "nopQ",   { Ev }, PREFIX_OPCODE },
3889     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3890     { "nopQ",   { Ev }, PREFIX_OPCODE },
3891     { "nopQ",   { Ev }, PREFIX_OPCODE },
3892   },
3893
3894   /* PREFIX_0F2A */
3895   {
3896     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3897     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3898     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3899     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3900   },
3901
3902   /* PREFIX_0F2B */
3903   {
3904     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3905     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3906     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3907     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3908   },
3909
3910   /* PREFIX_0F2C */
3911   {
3912     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3913     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3914     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3915     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3916   },
3917
3918   /* PREFIX_0F2D */
3919   {
3920     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3921     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3922     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3923     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3924   },
3925
3926   /* PREFIX_0F2E */
3927   {
3928     { "ucomiss",{ XM, EXd }, 0 },
3929     { Bad_Opcode },
3930     { "ucomisd",{ XM, EXq }, 0 },
3931   },
3932
3933   /* PREFIX_0F2F */
3934   {
3935     { "comiss", { XM, EXd }, 0 },
3936     { Bad_Opcode },
3937     { "comisd", { XM, EXq }, 0 },
3938   },
3939
3940   /* PREFIX_0F51 */
3941   {
3942     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3943     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3944     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3945     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3946   },
3947
3948   /* PREFIX_0F52 */
3949   {
3950     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3951     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3952   },
3953
3954   /* PREFIX_0F53 */
3955   {
3956     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3957     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3958   },
3959
3960   /* PREFIX_0F58 */
3961   {
3962     { "addps", { XM, EXx }, PREFIX_OPCODE },
3963     { "addss", { XM, EXd }, PREFIX_OPCODE },
3964     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3965     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3966   },
3967
3968   /* PREFIX_0F59 */
3969   {
3970     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3971     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3972     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3973     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3974   },
3975
3976   /* PREFIX_0F5A */
3977   {
3978     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3979     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3980     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3981     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3982   },
3983
3984   /* PREFIX_0F5B */
3985   {
3986     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3987     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3988     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3989   },
3990
3991   /* PREFIX_0F5C */
3992   {
3993     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3994     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3995     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3996     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3997   },
3998
3999   /* PREFIX_0F5D */
4000   {
4001     { "minps",  { XM, EXx }, PREFIX_OPCODE },
4002     { "minss",  { XM, EXd }, PREFIX_OPCODE },
4003     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
4004     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
4005   },
4006
4007   /* PREFIX_0F5E */
4008   {
4009     { "divps",  { XM, EXx }, PREFIX_OPCODE },
4010     { "divss",  { XM, EXd }, PREFIX_OPCODE },
4011     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
4012     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
4013   },
4014
4015   /* PREFIX_0F5F */
4016   {
4017     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
4018     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
4019     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
4020     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
4021   },
4022
4023   /* PREFIX_0F60 */
4024   {
4025     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
4026     { Bad_Opcode },
4027     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
4028   },
4029
4030   /* PREFIX_0F61 */
4031   {
4032     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
4033     { Bad_Opcode },
4034     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4035   },
4036
4037   /* PREFIX_0F62 */
4038   {
4039     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4040     { Bad_Opcode },
4041     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4042   },
4043
4044   /* PREFIX_0F6C */
4045   {
4046     { Bad_Opcode },
4047     { Bad_Opcode },
4048     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4049   },
4050
4051   /* PREFIX_0F6D */
4052   {
4053     { Bad_Opcode },
4054     { Bad_Opcode },
4055     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4056   },
4057
4058   /* PREFIX_0F6F */
4059   {
4060     { "movq",   { MX, EM }, PREFIX_OPCODE },
4061     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4062     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4063   },
4064
4065   /* PREFIX_0F70 */
4066   {
4067     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4068     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4069     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4070     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4071   },
4072
4073   /* PREFIX_0F73_REG_3 */
4074   {
4075     { Bad_Opcode },
4076     { Bad_Opcode },
4077     { "psrldq", { XS, Ib }, 0 },
4078   },
4079
4080   /* PREFIX_0F73_REG_7 */
4081   {
4082     { Bad_Opcode },
4083     { Bad_Opcode },
4084     { "pslldq", { XS, Ib }, 0 },
4085   },
4086
4087   /* PREFIX_0F78 */
4088   {
4089     {"vmread",  { Em, Gm }, 0 },
4090     { Bad_Opcode },
4091     {"extrq",   { XS, Ib, Ib }, 0 },
4092     {"insertq", { XM, XS, Ib, Ib }, 0 },
4093   },
4094
4095   /* PREFIX_0F79 */
4096   {
4097     {"vmwrite", { Gm, Em }, 0 },
4098     { Bad_Opcode },
4099     {"extrq",   { XM, XS }, 0 },
4100     {"insertq", { XM, XS }, 0 },
4101   },
4102
4103   /* PREFIX_0F7C */
4104   {
4105     { Bad_Opcode },
4106     { Bad_Opcode },
4107     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4108     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4109   },
4110
4111   /* PREFIX_0F7D */
4112   {
4113     { Bad_Opcode },
4114     { Bad_Opcode },
4115     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4116     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4117   },
4118
4119   /* PREFIX_0F7E */
4120   {
4121     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4122     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4123     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4124   },
4125
4126   /* PREFIX_0F7F */
4127   {
4128     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4129     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4130     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4131   },
4132
4133   /* PREFIX_0FAE_REG_0 */
4134   {
4135     { Bad_Opcode },
4136     { "rdfsbase", { Ev }, 0 },
4137   },
4138
4139   /* PREFIX_0FAE_REG_1 */
4140   {
4141     { Bad_Opcode },
4142     { "rdgsbase", { Ev }, 0 },
4143   },
4144
4145   /* PREFIX_0FAE_REG_2 */
4146   {
4147     { Bad_Opcode },
4148     { "wrfsbase", { Ev }, 0 },
4149   },
4150
4151   /* PREFIX_0FAE_REG_3 */
4152   {
4153     { Bad_Opcode },
4154     { "wrgsbase", { Ev }, 0 },
4155   },
4156
4157   /* PREFIX_MOD_0_0FAE_REG_4 */
4158   {
4159     { "xsave",  { FXSAVE }, 0 },
4160     { "ptwrite%LQ", { Edq }, 0 },
4161   },
4162
4163   /* PREFIX_MOD_3_0FAE_REG_4 */
4164   {
4165     { Bad_Opcode },
4166     { "ptwrite%LQ", { Edq }, 0 },
4167   },
4168
4169   /* PREFIX_MOD_0_0FAE_REG_5 */
4170   {
4171     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4172   },
4173
4174   /* PREFIX_MOD_3_0FAE_REG_5 */
4175   {
4176     { "lfence",         { Skip_MODRM }, 0 },
4177     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4178   },
4179
4180   /* PREFIX_0FAE_REG_6 */
4181   {
4182     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4183     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4184     { "clwb",   { Mb }, PREFIX_OPCODE },
4185   },
4186
4187   /* PREFIX_0FAE_REG_7 */
4188   {
4189     { "clflush",        { Mb }, 0 },
4190     { Bad_Opcode },
4191     { "clflushopt",     { Mb }, 0 },
4192   },
4193
4194   /* PREFIX_0FB8 */
4195   {
4196     { Bad_Opcode },
4197     { "popcntS", { Gv, Ev }, 0 },
4198   },
4199
4200   /* PREFIX_0FBC */
4201   {
4202     { "bsfS",   { Gv, Ev }, 0 },
4203     { "tzcntS", { Gv, Ev }, 0 },
4204     { "bsfS",   { Gv, Ev }, 0 },
4205   },
4206
4207   /* PREFIX_0FBD */
4208   {
4209     { "bsrS",   { Gv, Ev }, 0 },
4210     { "lzcntS", { Gv, Ev }, 0 },
4211     { "bsrS",   { Gv, Ev }, 0 },
4212   },
4213
4214   /* PREFIX_0FC2 */
4215   {
4216     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4217     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4218     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4219     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4220   },
4221
4222   /* PREFIX_MOD_0_0FC3 */
4223   {
4224     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4225   },
4226
4227   /* PREFIX_MOD_0_0FC7_REG_6 */
4228   {
4229     { "vmptrld",{ Mq }, 0 },
4230     { "vmxon",  { Mq }, 0 },
4231     { "vmclear",{ Mq }, 0 },
4232   },
4233
4234   /* PREFIX_MOD_3_0FC7_REG_6 */
4235   {
4236     { "rdrand", { Ev }, 0 },
4237     { Bad_Opcode },
4238     { "rdrand", { Ev }, 0 }
4239   },
4240
4241   /* PREFIX_MOD_3_0FC7_REG_7 */
4242   {
4243     { "rdseed", { Ev }, 0 },
4244     { "rdpid",  { Em }, 0 },
4245     { "rdseed", { Ev }, 0 },
4246   },
4247
4248   /* PREFIX_0FD0 */
4249   {
4250     { Bad_Opcode },
4251     { Bad_Opcode },
4252     { "addsubpd", { XM, EXx }, 0 },
4253     { "addsubps", { XM, EXx }, 0 },
4254   },
4255
4256   /* PREFIX_0FD6 */
4257   {
4258     { Bad_Opcode },
4259     { "movq2dq",{ XM, MS }, 0 },
4260     { "movq",   { EXqS, XM }, 0 },
4261     { "movdq2q",{ MX, XS }, 0 },
4262   },
4263
4264   /* PREFIX_0FE6 */
4265   {
4266     { Bad_Opcode },
4267     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4268     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4269     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4270   },
4271
4272   /* PREFIX_0FE7 */
4273   {
4274     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4275     { Bad_Opcode },
4276     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4277   },
4278
4279   /* PREFIX_0FF0 */
4280   {
4281     { Bad_Opcode },
4282     { Bad_Opcode },
4283     { Bad_Opcode },
4284     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4285   },
4286
4287   /* PREFIX_0FF7 */
4288   {
4289     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4290     { Bad_Opcode },
4291     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4292   },
4293
4294   /* PREFIX_0F3810 */
4295   {
4296     { Bad_Opcode },
4297     { Bad_Opcode },
4298     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4299   },
4300
4301   /* PREFIX_0F3814 */
4302   {
4303     { Bad_Opcode },
4304     { Bad_Opcode },
4305     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4306   },
4307
4308   /* PREFIX_0F3815 */
4309   {
4310     { Bad_Opcode },
4311     { Bad_Opcode },
4312     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4313   },
4314
4315   /* PREFIX_0F3817 */
4316   {
4317     { Bad_Opcode },
4318     { Bad_Opcode },
4319     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4320   },
4321
4322   /* PREFIX_0F3820 */
4323   {
4324     { Bad_Opcode },
4325     { Bad_Opcode },
4326     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4327   },
4328
4329   /* PREFIX_0F3821 */
4330   {
4331     { Bad_Opcode },
4332     { Bad_Opcode },
4333     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4334   },
4335
4336   /* PREFIX_0F3822 */
4337   {
4338     { Bad_Opcode },
4339     { Bad_Opcode },
4340     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4341   },
4342
4343   /* PREFIX_0F3823 */
4344   {
4345     { Bad_Opcode },
4346     { Bad_Opcode },
4347     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4348   },
4349
4350   /* PREFIX_0F3824 */
4351   {
4352     { Bad_Opcode },
4353     { Bad_Opcode },
4354     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4355   },
4356
4357   /* PREFIX_0F3825 */
4358   {
4359     { Bad_Opcode },
4360     { Bad_Opcode },
4361     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4362   },
4363
4364   /* PREFIX_0F3828 */
4365   {
4366     { Bad_Opcode },
4367     { Bad_Opcode },
4368     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4369   },
4370
4371   /* PREFIX_0F3829 */
4372   {
4373     { Bad_Opcode },
4374     { Bad_Opcode },
4375     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4376   },
4377
4378   /* PREFIX_0F382A */
4379   {
4380     { Bad_Opcode },
4381     { Bad_Opcode },
4382     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4383   },
4384
4385   /* PREFIX_0F382B */
4386   {
4387     { Bad_Opcode },
4388     { Bad_Opcode },
4389     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4390   },
4391
4392   /* PREFIX_0F3830 */
4393   {
4394     { Bad_Opcode },
4395     { Bad_Opcode },
4396     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4397   },
4398
4399   /* PREFIX_0F3831 */
4400   {
4401     { Bad_Opcode },
4402     { Bad_Opcode },
4403     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4404   },
4405
4406   /* PREFIX_0F3832 */
4407   {
4408     { Bad_Opcode },
4409     { Bad_Opcode },
4410     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4411   },
4412
4413   /* PREFIX_0F3833 */
4414   {
4415     { Bad_Opcode },
4416     { Bad_Opcode },
4417     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4418   },
4419
4420   /* PREFIX_0F3834 */
4421   {
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4425   },
4426
4427   /* PREFIX_0F3835 */
4428   {
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4432   },
4433
4434   /* PREFIX_0F3837 */
4435   {
4436     { Bad_Opcode },
4437     { Bad_Opcode },
4438     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4439   },
4440
4441   /* PREFIX_0F3838 */
4442   {
4443     { Bad_Opcode },
4444     { Bad_Opcode },
4445     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4446   },
4447
4448   /* PREFIX_0F3839 */
4449   {
4450     { Bad_Opcode },
4451     { Bad_Opcode },
4452     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4453   },
4454
4455   /* PREFIX_0F383A */
4456   {
4457     { Bad_Opcode },
4458     { Bad_Opcode },
4459     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4460   },
4461
4462   /* PREFIX_0F383B */
4463   {
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4467   },
4468
4469   /* PREFIX_0F383C */
4470   {
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4474   },
4475
4476   /* PREFIX_0F383D */
4477   {
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4481   },
4482
4483   /* PREFIX_0F383E */
4484   {
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4488   },
4489
4490   /* PREFIX_0F383F */
4491   {
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4495   },
4496
4497   /* PREFIX_0F3840 */
4498   {
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4502   },
4503
4504   /* PREFIX_0F3841 */
4505   {
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4509   },
4510
4511   /* PREFIX_0F3880 */
4512   {
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4516   },
4517
4518   /* PREFIX_0F3881 */
4519   {
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4523   },
4524
4525   /* PREFIX_0F3882 */
4526   {
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4530   },
4531
4532   /* PREFIX_0F38C8 */
4533   {
4534     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4535   },
4536
4537   /* PREFIX_0F38C9 */
4538   {
4539     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4540   },
4541
4542   /* PREFIX_0F38CA */
4543   {
4544     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4545   },
4546
4547   /* PREFIX_0F38CB */
4548   {
4549     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4550   },
4551
4552   /* PREFIX_0F38CC */
4553   {
4554     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4555   },
4556
4557   /* PREFIX_0F38CD */
4558   {
4559     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4560   },
4561
4562   /* PREFIX_0F38CF */
4563   {
4564     { Bad_Opcode },
4565     { Bad_Opcode },
4566     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4567   },
4568
4569   /* PREFIX_0F38DB */
4570   {
4571     { Bad_Opcode },
4572     { Bad_Opcode },
4573     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4574   },
4575
4576   /* PREFIX_0F38DC */
4577   {
4578     { Bad_Opcode },
4579     { Bad_Opcode },
4580     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4581   },
4582
4583   /* PREFIX_0F38DD */
4584   {
4585     { Bad_Opcode },
4586     { Bad_Opcode },
4587     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4588   },
4589
4590   /* PREFIX_0F38DE */
4591   {
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4595   },
4596
4597   /* PREFIX_0F38DF */
4598   {
4599     { Bad_Opcode },
4600     { Bad_Opcode },
4601     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4602   },
4603
4604   /* PREFIX_0F38F0 */
4605   {
4606     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4607     { Bad_Opcode },
4608     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4609     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4610   },
4611
4612   /* PREFIX_0F38F1 */
4613   {
4614     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4615     { Bad_Opcode },
4616     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4617     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4618   },
4619
4620   /* PREFIX_0F38F5 */
4621   {
4622     { Bad_Opcode },
4623     { Bad_Opcode },
4624     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4625   },
4626
4627   /* PREFIX_0F38F6 */
4628   {
4629     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4630     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4631     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4632     { Bad_Opcode },
4633   },
4634
4635   /* PREFIX_0F3A08 */
4636   {
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4640   },
4641
4642   /* PREFIX_0F3A09 */
4643   {
4644     { Bad_Opcode },
4645     { Bad_Opcode },
4646     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4647   },
4648
4649   /* PREFIX_0F3A0A */
4650   {
4651     { Bad_Opcode },
4652     { Bad_Opcode },
4653     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4654   },
4655
4656   /* PREFIX_0F3A0B */
4657   {
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4661   },
4662
4663   /* PREFIX_0F3A0C */
4664   {
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4668   },
4669
4670   /* PREFIX_0F3A0D */
4671   {
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4675   },
4676
4677   /* PREFIX_0F3A0E */
4678   {
4679     { Bad_Opcode },
4680     { Bad_Opcode },
4681     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4682   },
4683
4684   /* PREFIX_0F3A14 */
4685   {
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4689   },
4690
4691   /* PREFIX_0F3A15 */
4692   {
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4696   },
4697
4698   /* PREFIX_0F3A16 */
4699   {
4700     { Bad_Opcode },
4701     { Bad_Opcode },
4702     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4703   },
4704
4705   /* PREFIX_0F3A17 */
4706   {
4707     { Bad_Opcode },
4708     { Bad_Opcode },
4709     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4710   },
4711
4712   /* PREFIX_0F3A20 */
4713   {
4714     { Bad_Opcode },
4715     { Bad_Opcode },
4716     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4717   },
4718
4719   /* PREFIX_0F3A21 */
4720   {
4721     { Bad_Opcode },
4722     { Bad_Opcode },
4723     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4724   },
4725
4726   /* PREFIX_0F3A22 */
4727   {
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4731   },
4732
4733   /* PREFIX_0F3A40 */
4734   {
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4738   },
4739
4740   /* PREFIX_0F3A41 */
4741   {
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4745   },
4746
4747   /* PREFIX_0F3A42 */
4748   {
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4752   },
4753
4754   /* PREFIX_0F3A44 */
4755   {
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4759   },
4760
4761   /* PREFIX_0F3A60 */
4762   {
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4766   },
4767
4768   /* PREFIX_0F3A61 */
4769   {
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4773   },
4774
4775   /* PREFIX_0F3A62 */
4776   {
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4780   },
4781
4782   /* PREFIX_0F3A63 */
4783   {
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4787   },
4788
4789   /* PREFIX_0F3ACC */
4790   {
4791     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4792   },
4793
4794   /* PREFIX_0F3ACE */
4795   {
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4799   },
4800
4801   /* PREFIX_0F3ACF */
4802   {
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4806   },
4807
4808   /* PREFIX_0F3ADF */
4809   {
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4813   },
4814
4815   /* PREFIX_VEX_0F10 */
4816   {
4817     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4818     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4819     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4820     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4821   },
4822
4823   /* PREFIX_VEX_0F11 */
4824   {
4825     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4826     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4827     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4828     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4829   },
4830
4831   /* PREFIX_VEX_0F12 */
4832   {
4833     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4834     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4835     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4836     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4837   },
4838
4839   /* PREFIX_VEX_0F16 */
4840   {
4841     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4842     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4843     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4844   },
4845
4846   /* PREFIX_VEX_0F2A */
4847   {
4848     { Bad_Opcode },
4849     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4850     { Bad_Opcode },
4851     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4852   },
4853
4854   /* PREFIX_VEX_0F2C */
4855   {
4856     { Bad_Opcode },
4857     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4858     { Bad_Opcode },
4859     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4860   },
4861
4862   /* PREFIX_VEX_0F2D */
4863   {
4864     { Bad_Opcode },
4865     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4866     { Bad_Opcode },
4867     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4868   },
4869
4870   /* PREFIX_VEX_0F2E */
4871   {
4872     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4873     { Bad_Opcode },
4874     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4875   },
4876
4877   /* PREFIX_VEX_0F2F */
4878   {
4879     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4880     { Bad_Opcode },
4881     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4882   },
4883
4884   /* PREFIX_VEX_0F41 */
4885   {
4886     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4887     { Bad_Opcode },
4888     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4889   },
4890
4891   /* PREFIX_VEX_0F42 */
4892   {
4893     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4894     { Bad_Opcode },
4895     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4896   },
4897
4898   /* PREFIX_VEX_0F44 */
4899   {
4900     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4901     { Bad_Opcode },
4902     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4903   },
4904
4905   /* PREFIX_VEX_0F45 */
4906   {
4907     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4908     { Bad_Opcode },
4909     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4910   },
4911
4912   /* PREFIX_VEX_0F46 */
4913   {
4914     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4915     { Bad_Opcode },
4916     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4917   },
4918
4919   /* PREFIX_VEX_0F47 */
4920   {
4921     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4922     { Bad_Opcode },
4923     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4924   },
4925
4926   /* PREFIX_VEX_0F4A */
4927   {
4928     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4929     { Bad_Opcode },
4930     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4931   },
4932
4933   /* PREFIX_VEX_0F4B */
4934   {
4935     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4936     { Bad_Opcode },
4937     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4938   },
4939
4940   /* PREFIX_VEX_0F51 */
4941   {
4942     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4943     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4944     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4945     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4946   },
4947
4948   /* PREFIX_VEX_0F52 */
4949   {
4950     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4951     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4952   },
4953
4954   /* PREFIX_VEX_0F53 */
4955   {
4956     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4957     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4958   },
4959
4960   /* PREFIX_VEX_0F58 */
4961   {
4962     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4963     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4964     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4965     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4966   },
4967
4968   /* PREFIX_VEX_0F59 */
4969   {
4970     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4971     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4972     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4973     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4974   },
4975
4976   /* PREFIX_VEX_0F5A */
4977   {
4978     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4979     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4980     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4981     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4982   },
4983
4984   /* PREFIX_VEX_0F5B */
4985   {
4986     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4987     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4988     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4989   },
4990
4991   /* PREFIX_VEX_0F5C */
4992   {
4993     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4994     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4995     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4996     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4997   },
4998
4999   /* PREFIX_VEX_0F5D */
5000   {
5001     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
5002     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
5003     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
5004     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
5005   },
5006
5007   /* PREFIX_VEX_0F5E */
5008   {
5009     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
5010     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
5011     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
5012     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
5013   },
5014
5015   /* PREFIX_VEX_0F5F */
5016   {
5017     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
5018     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
5019     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
5020     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
5021   },
5022
5023   /* PREFIX_VEX_0F60 */
5024   {
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { VEX_W_TABLE (VEX_W_0F60_P_2) },
5028   },
5029
5030   /* PREFIX_VEX_0F61 */
5031   {
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { VEX_W_TABLE (VEX_W_0F61_P_2) },
5035   },
5036
5037   /* PREFIX_VEX_0F62 */
5038   {
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { VEX_W_TABLE (VEX_W_0F62_P_2) },
5042   },
5043
5044   /* PREFIX_VEX_0F63 */
5045   {
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { VEX_W_TABLE (VEX_W_0F63_P_2) },
5049   },
5050
5051   /* PREFIX_VEX_0F64 */
5052   {
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { VEX_W_TABLE (VEX_W_0F64_P_2) },
5056   },
5057
5058   /* PREFIX_VEX_0F65 */
5059   {
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { VEX_W_TABLE (VEX_W_0F65_P_2) },
5063   },
5064
5065   /* PREFIX_VEX_0F66 */
5066   {
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { VEX_W_TABLE (VEX_W_0F66_P_2) },
5070   },
5071
5072   /* PREFIX_VEX_0F67 */
5073   {
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { VEX_W_TABLE (VEX_W_0F67_P_2) },
5077   },
5078
5079   /* PREFIX_VEX_0F68 */
5080   {
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { VEX_W_TABLE (VEX_W_0F68_P_2) },
5084   },
5085
5086   /* PREFIX_VEX_0F69 */
5087   {
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { VEX_W_TABLE (VEX_W_0F69_P_2) },
5091   },
5092
5093   /* PREFIX_VEX_0F6A */
5094   {
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5098   },
5099
5100   /* PREFIX_VEX_0F6B */
5101   {
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5105   },
5106
5107   /* PREFIX_VEX_0F6C */
5108   {
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5112   },
5113
5114   /* PREFIX_VEX_0F6D */
5115   {
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5119   },
5120
5121   /* PREFIX_VEX_0F6E */
5122   {
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5126   },
5127
5128   /* PREFIX_VEX_0F6F */
5129   {
5130     { Bad_Opcode },
5131     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5132     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5133   },
5134
5135   /* PREFIX_VEX_0F70 */
5136   {
5137     { Bad_Opcode },
5138     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5139     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5140     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5141   },
5142
5143   /* PREFIX_VEX_0F71_REG_2 */
5144   {
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5148   },
5149
5150   /* PREFIX_VEX_0F71_REG_4 */
5151   {
5152     { Bad_Opcode },
5153     { Bad_Opcode },
5154     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5155   },
5156
5157   /* PREFIX_VEX_0F71_REG_6 */
5158   {
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5162   },
5163
5164   /* PREFIX_VEX_0F72_REG_2 */
5165   {
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5169   },
5170
5171   /* PREFIX_VEX_0F72_REG_4 */
5172   {
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5176   },
5177
5178   /* PREFIX_VEX_0F72_REG_6 */
5179   {
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5183   },
5184
5185   /* PREFIX_VEX_0F73_REG_2 */
5186   {
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5190   },
5191
5192   /* PREFIX_VEX_0F73_REG_3 */
5193   {
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5197   },
5198
5199   /* PREFIX_VEX_0F73_REG_6 */
5200   {
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5204   },
5205
5206   /* PREFIX_VEX_0F73_REG_7 */
5207   {
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5211   },
5212
5213   /* PREFIX_VEX_0F74 */
5214   {
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5218   },
5219
5220   /* PREFIX_VEX_0F75 */
5221   {
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5225   },
5226
5227   /* PREFIX_VEX_0F76 */
5228   {
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5232   },
5233
5234   /* PREFIX_VEX_0F77 */
5235   {
5236     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5237   },
5238
5239   /* PREFIX_VEX_0F7C */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5244     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5245   },
5246
5247   /* PREFIX_VEX_0F7D */
5248   {
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5252     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5253   },
5254
5255   /* PREFIX_VEX_0F7E */
5256   {
5257     { Bad_Opcode },
5258     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5259     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5260   },
5261
5262   /* PREFIX_VEX_0F7F */
5263   {
5264     { Bad_Opcode },
5265     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5266     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5267   },
5268
5269   /* PREFIX_VEX_0F90 */
5270   {
5271     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5272     { Bad_Opcode },
5273     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5274   },
5275
5276   /* PREFIX_VEX_0F91 */
5277   {
5278     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5279     { Bad_Opcode },
5280     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5281   },
5282
5283   /* PREFIX_VEX_0F92 */
5284   {
5285     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5286     { Bad_Opcode },
5287     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5288     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5289   },
5290
5291   /* PREFIX_VEX_0F93 */
5292   {
5293     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5294     { Bad_Opcode },
5295     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5296     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5297   },
5298
5299   /* PREFIX_VEX_0F98 */
5300   {
5301     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5302     { Bad_Opcode },
5303     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5304   },
5305
5306   /* PREFIX_VEX_0F99 */
5307   {
5308     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5309     { Bad_Opcode },
5310     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5311   },
5312
5313   /* PREFIX_VEX_0FC2 */
5314   {
5315     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5316     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5317     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5318     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5319   },
5320
5321   /* PREFIX_VEX_0FC4 */
5322   {
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5326   },
5327
5328   /* PREFIX_VEX_0FC5 */
5329   {
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5333   },
5334
5335   /* PREFIX_VEX_0FD0 */
5336   {
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5340     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5341   },
5342
5343   /* PREFIX_VEX_0FD1 */
5344   {
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5348   },
5349
5350   /* PREFIX_VEX_0FD2 */
5351   {
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5355   },
5356
5357   /* PREFIX_VEX_0FD3 */
5358   {
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5362   },
5363
5364   /* PREFIX_VEX_0FD4 */
5365   {
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5369   },
5370
5371   /* PREFIX_VEX_0FD5 */
5372   {
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5376   },
5377
5378   /* PREFIX_VEX_0FD6 */
5379   {
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5383   },
5384
5385   /* PREFIX_VEX_0FD7 */
5386   {
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5390   },
5391
5392   /* PREFIX_VEX_0FD8 */
5393   {
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5397   },
5398
5399   /* PREFIX_VEX_0FD9 */
5400   {
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5404   },
5405
5406   /* PREFIX_VEX_0FDA */
5407   {
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5411   },
5412
5413   /* PREFIX_VEX_0FDB */
5414   {
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5418   },
5419
5420   /* PREFIX_VEX_0FDC */
5421   {
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5425   },
5426
5427   /* PREFIX_VEX_0FDD */
5428   {
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5432   },
5433
5434   /* PREFIX_VEX_0FDE */
5435   {
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5439   },
5440
5441   /* PREFIX_VEX_0FDF */
5442   {
5443     { Bad_Opcode },
5444     { Bad_Opcode },
5445     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5446   },
5447
5448   /* PREFIX_VEX_0FE0 */
5449   {
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5453   },
5454
5455   /* PREFIX_VEX_0FE1 */
5456   {
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5460   },
5461
5462   /* PREFIX_VEX_0FE2 */
5463   {
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5467   },
5468
5469   /* PREFIX_VEX_0FE3 */
5470   {
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5474   },
5475
5476   /* PREFIX_VEX_0FE4 */
5477   {
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5481   },
5482
5483   /* PREFIX_VEX_0FE5 */
5484   {
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5488   },
5489
5490   /* PREFIX_VEX_0FE6 */
5491   {
5492     { Bad_Opcode },
5493     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5494     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5495     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5496   },
5497
5498   /* PREFIX_VEX_0FE7 */
5499   {
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5503   },
5504
5505   /* PREFIX_VEX_0FE8 */
5506   {
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5510   },
5511
5512   /* PREFIX_VEX_0FE9 */
5513   {
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5517   },
5518
5519   /* PREFIX_VEX_0FEA */
5520   {
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5524   },
5525
5526   /* PREFIX_VEX_0FEB */
5527   {
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5531   },
5532
5533   /* PREFIX_VEX_0FEC */
5534   {
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5538   },
5539
5540   /* PREFIX_VEX_0FED */
5541   {
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5545   },
5546
5547   /* PREFIX_VEX_0FEE */
5548   {
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5552   },
5553
5554   /* PREFIX_VEX_0FEF */
5555   {
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5559   },
5560
5561   /* PREFIX_VEX_0FF0 */
5562   {
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5567   },
5568
5569   /* PREFIX_VEX_0FF1 */
5570   {
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5574   },
5575
5576   /* PREFIX_VEX_0FF2 */
5577   {
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5581   },
5582
5583   /* PREFIX_VEX_0FF3 */
5584   {
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5588   },
5589
5590   /* PREFIX_VEX_0FF4 */
5591   {
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5595   },
5596
5597   /* PREFIX_VEX_0FF5 */
5598   {
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5602   },
5603
5604   /* PREFIX_VEX_0FF6 */
5605   {
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5609   },
5610
5611   /* PREFIX_VEX_0FF7 */
5612   {
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5616   },
5617
5618   /* PREFIX_VEX_0FF8 */
5619   {
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5623   },
5624
5625   /* PREFIX_VEX_0FF9 */
5626   {
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5630   },
5631
5632   /* PREFIX_VEX_0FFA */
5633   {
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5637   },
5638
5639   /* PREFIX_VEX_0FFB */
5640   {
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5644   },
5645
5646   /* PREFIX_VEX_0FFC */
5647   {
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5651   },
5652
5653   /* PREFIX_VEX_0FFD */
5654   {
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5658   },
5659
5660   /* PREFIX_VEX_0FFE */
5661   {
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5665   },
5666
5667   /* PREFIX_VEX_0F3800 */
5668   {
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5672   },
5673
5674   /* PREFIX_VEX_0F3801 */
5675   {
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5679   },
5680
5681   /* PREFIX_VEX_0F3802 */
5682   {
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5686   },
5687
5688   /* PREFIX_VEX_0F3803 */
5689   {
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5693   },
5694
5695   /* PREFIX_VEX_0F3804 */
5696   {
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5700   },
5701
5702   /* PREFIX_VEX_0F3805 */
5703   {
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5707   },
5708
5709   /* PREFIX_VEX_0F3806 */
5710   {
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5714   },
5715
5716   /* PREFIX_VEX_0F3807 */
5717   {
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5721   },
5722
5723   /* PREFIX_VEX_0F3808 */
5724   {
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5728   },
5729
5730   /* PREFIX_VEX_0F3809 */
5731   {
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5735   },
5736
5737   /* PREFIX_VEX_0F380A */
5738   {
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5742   },
5743
5744   /* PREFIX_VEX_0F380B */
5745   {
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5749   },
5750
5751   /* PREFIX_VEX_0F380C */
5752   {
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5756   },
5757
5758   /* PREFIX_VEX_0F380D */
5759   {
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5763   },
5764
5765   /* PREFIX_VEX_0F380E */
5766   {
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5770   },
5771
5772   /* PREFIX_VEX_0F380F */
5773   {
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5777   },
5778
5779   /* PREFIX_VEX_0F3813 */
5780   {
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5784   },
5785
5786   /* PREFIX_VEX_0F3816 */
5787   {
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5791   },
5792
5793   /* PREFIX_VEX_0F3817 */
5794   {
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5798   },
5799
5800   /* PREFIX_VEX_0F3818 */
5801   {
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5805   },
5806
5807   /* PREFIX_VEX_0F3819 */
5808   {
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5812   },
5813
5814   /* PREFIX_VEX_0F381A */
5815   {
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5819   },
5820
5821   /* PREFIX_VEX_0F381C */
5822   {
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5826   },
5827
5828   /* PREFIX_VEX_0F381D */
5829   {
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5833   },
5834
5835   /* PREFIX_VEX_0F381E */
5836   {
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5840   },
5841
5842   /* PREFIX_VEX_0F3820 */
5843   {
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5847   },
5848
5849   /* PREFIX_VEX_0F3821 */
5850   {
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5854   },
5855
5856   /* PREFIX_VEX_0F3822 */
5857   {
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5861   },
5862
5863   /* PREFIX_VEX_0F3823 */
5864   {
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5868   },
5869
5870   /* PREFIX_VEX_0F3824 */
5871   {
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5875   },
5876
5877   /* PREFIX_VEX_0F3825 */
5878   {
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5882   },
5883
5884   /* PREFIX_VEX_0F3828 */
5885   {
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5889   },
5890
5891   /* PREFIX_VEX_0F3829 */
5892   {
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5896   },
5897
5898   /* PREFIX_VEX_0F382A */
5899   {
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5903   },
5904
5905   /* PREFIX_VEX_0F382B */
5906   {
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5910   },
5911
5912   /* PREFIX_VEX_0F382C */
5913   {
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5917   },
5918
5919   /* PREFIX_VEX_0F382D */
5920   {
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5924   },
5925
5926   /* PREFIX_VEX_0F382E */
5927   {
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5931   },
5932
5933   /* PREFIX_VEX_0F382F */
5934   {
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5938   },
5939
5940   /* PREFIX_VEX_0F3830 */
5941   {
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5945   },
5946
5947   /* PREFIX_VEX_0F3831 */
5948   {
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5952   },
5953
5954   /* PREFIX_VEX_0F3832 */
5955   {
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5959   },
5960
5961   /* PREFIX_VEX_0F3833 */
5962   {
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5966   },
5967
5968   /* PREFIX_VEX_0F3834 */
5969   {
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5973   },
5974
5975   /* PREFIX_VEX_0F3835 */
5976   {
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5980   },
5981
5982   /* PREFIX_VEX_0F3836 */
5983   {
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5987   },
5988
5989   /* PREFIX_VEX_0F3837 */
5990   {
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5994   },
5995
5996   /* PREFIX_VEX_0F3838 */
5997   {
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
6001   },
6002
6003   /* PREFIX_VEX_0F3839 */
6004   {
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
6008   },
6009
6010   /* PREFIX_VEX_0F383A */
6011   {
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
6015   },
6016
6017   /* PREFIX_VEX_0F383B */
6018   {
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
6022   },
6023
6024   /* PREFIX_VEX_0F383C */
6025   {
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
6029   },
6030
6031   /* PREFIX_VEX_0F383D */
6032   {
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
6036   },
6037
6038   /* PREFIX_VEX_0F383E */
6039   {
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
6043   },
6044
6045   /* PREFIX_VEX_0F383F */
6046   {
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
6050   },
6051
6052   /* PREFIX_VEX_0F3840 */
6053   {
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6057   },
6058
6059   /* PREFIX_VEX_0F3841 */
6060   {
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6064   },
6065
6066   /* PREFIX_VEX_0F3845 */
6067   {
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6071   },
6072
6073   /* PREFIX_VEX_0F3846 */
6074   {
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6078   },
6079
6080   /* PREFIX_VEX_0F3847 */
6081   {
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6085   },
6086
6087   /* PREFIX_VEX_0F3858 */
6088   {
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6092   },
6093
6094   /* PREFIX_VEX_0F3859 */
6095   {
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6099   },
6100
6101   /* PREFIX_VEX_0F385A */
6102   {
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6106   },
6107
6108   /* PREFIX_VEX_0F3878 */
6109   {
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6113   },
6114
6115   /* PREFIX_VEX_0F3879 */
6116   {
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6120   },
6121
6122   /* PREFIX_VEX_0F388C */
6123   {
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6127   },
6128
6129   /* PREFIX_VEX_0F388E */
6130   {
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6134   },
6135
6136   /* PREFIX_VEX_0F3890 */
6137   {
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6141   },
6142
6143   /* PREFIX_VEX_0F3891 */
6144   {
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6148   },
6149
6150   /* PREFIX_VEX_0F3892 */
6151   {
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6155   },
6156
6157   /* PREFIX_VEX_0F3893 */
6158   {
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6162   },
6163
6164   /* PREFIX_VEX_0F3896 */
6165   {
6166     { Bad_Opcode },
6167     { Bad_Opcode },
6168     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6169   },
6170
6171   /* PREFIX_VEX_0F3897 */
6172   {
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6176   },
6177
6178   /* PREFIX_VEX_0F3898 */
6179   {
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6183   },
6184
6185   /* PREFIX_VEX_0F3899 */
6186   {
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6190   },
6191
6192   /* PREFIX_VEX_0F389A */
6193   {
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6197   },
6198
6199   /* PREFIX_VEX_0F389B */
6200   {
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6204   },
6205
6206   /* PREFIX_VEX_0F389C */
6207   {
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6211   },
6212
6213   /* PREFIX_VEX_0F389D */
6214   {
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6218   },
6219
6220   /* PREFIX_VEX_0F389E */
6221   {
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6225   },
6226
6227   /* PREFIX_VEX_0F389F */
6228   {
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6232   },
6233
6234   /* PREFIX_VEX_0F38A6 */
6235   {
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6239     { Bad_Opcode },
6240   },
6241
6242   /* PREFIX_VEX_0F38A7 */
6243   {
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6247   },
6248
6249   /* PREFIX_VEX_0F38A8 */
6250   {
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6254   },
6255
6256   /* PREFIX_VEX_0F38A9 */
6257   {
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6261   },
6262
6263   /* PREFIX_VEX_0F38AA */
6264   {
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6268   },
6269
6270   /* PREFIX_VEX_0F38AB */
6271   {
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6275   },
6276
6277   /* PREFIX_VEX_0F38AC */
6278   {
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6282   },
6283
6284   /* PREFIX_VEX_0F38AD */
6285   {
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6289   },
6290
6291   /* PREFIX_VEX_0F38AE */
6292   {
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6296   },
6297
6298   /* PREFIX_VEX_0F38AF */
6299   {
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6303   },
6304
6305   /* PREFIX_VEX_0F38B6 */
6306   {
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6310   },
6311
6312   /* PREFIX_VEX_0F38B7 */
6313   {
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6317   },
6318
6319   /* PREFIX_VEX_0F38B8 */
6320   {
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6324   },
6325
6326   /* PREFIX_VEX_0F38B9 */
6327   {
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6331   },
6332
6333   /* PREFIX_VEX_0F38BA */
6334   {
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6338   },
6339
6340   /* PREFIX_VEX_0F38BB */
6341   {
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6345   },
6346
6347   /* PREFIX_VEX_0F38BC */
6348   {
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6352   },
6353
6354   /* PREFIX_VEX_0F38BD */
6355   {
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6359   },
6360
6361   /* PREFIX_VEX_0F38BE */
6362   {
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6366   },
6367
6368   /* PREFIX_VEX_0F38BF */
6369   {
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6373   },
6374
6375   /* PREFIX_VEX_0F38CF */
6376   {
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6380   },
6381
6382   /* PREFIX_VEX_0F38DB */
6383   {
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6387   },
6388
6389   /* PREFIX_VEX_0F38DC */
6390   {
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { "vaesenc",        { XM, Vex, EXx }, 0 },
6394   },
6395
6396   /* PREFIX_VEX_0F38DD */
6397   {
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6401   },
6402
6403   /* PREFIX_VEX_0F38DE */
6404   {
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { "vaesdec",        { XM, Vex, EXx }, 0 },
6408   },
6409
6410   /* PREFIX_VEX_0F38DF */
6411   {
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6415   },
6416
6417   /* PREFIX_VEX_0F38F2 */
6418   {
6419     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6420   },
6421
6422   /* PREFIX_VEX_0F38F3_REG_1 */
6423   {
6424     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6425   },
6426
6427   /* PREFIX_VEX_0F38F3_REG_2 */
6428   {
6429     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6430   },
6431
6432   /* PREFIX_VEX_0F38F3_REG_3 */
6433   {
6434     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6435   },
6436
6437   /* PREFIX_VEX_0F38F5 */
6438   {
6439     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6440     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6441     { Bad_Opcode },
6442     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6443   },
6444
6445   /* PREFIX_VEX_0F38F6 */
6446   {
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6451   },
6452
6453   /* PREFIX_VEX_0F38F7 */
6454   {
6455     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6456     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6457     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6458     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6459   },
6460
6461   /* PREFIX_VEX_0F3A00 */
6462   {
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6466   },
6467
6468   /* PREFIX_VEX_0F3A01 */
6469   {
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6473   },
6474
6475   /* PREFIX_VEX_0F3A02 */
6476   {
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6480   },
6481
6482   /* PREFIX_VEX_0F3A04 */
6483   {
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6487   },
6488
6489   /* PREFIX_VEX_0F3A05 */
6490   {
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6494   },
6495
6496   /* PREFIX_VEX_0F3A06 */
6497   {
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6501   },
6502
6503   /* PREFIX_VEX_0F3A08 */
6504   {
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6508   },
6509
6510   /* PREFIX_VEX_0F3A09 */
6511   {
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6515   },
6516
6517   /* PREFIX_VEX_0F3A0A */
6518   {
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6522   },
6523
6524   /* PREFIX_VEX_0F3A0B */
6525   {
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6529   },
6530
6531   /* PREFIX_VEX_0F3A0C */
6532   {
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6536   },
6537
6538   /* PREFIX_VEX_0F3A0D */
6539   {
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6543   },
6544
6545   /* PREFIX_VEX_0F3A0E */
6546   {
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6550   },
6551
6552   /* PREFIX_VEX_0F3A0F */
6553   {
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6557   },
6558
6559   /* PREFIX_VEX_0F3A14 */
6560   {
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6564   },
6565
6566   /* PREFIX_VEX_0F3A15 */
6567   {
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6571   },
6572
6573   /* PREFIX_VEX_0F3A16 */
6574   {
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6578   },
6579
6580   /* PREFIX_VEX_0F3A17 */
6581   {
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6585   },
6586
6587   /* PREFIX_VEX_0F3A18 */
6588   {
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6592   },
6593
6594   /* PREFIX_VEX_0F3A19 */
6595   {
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6599   },
6600
6601   /* PREFIX_VEX_0F3A1D */
6602   {
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6606   },
6607
6608   /* PREFIX_VEX_0F3A20 */
6609   {
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6613   },
6614
6615   /* PREFIX_VEX_0F3A21 */
6616   {
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6620   },
6621
6622   /* PREFIX_VEX_0F3A22 */
6623   {
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6627   },
6628
6629   /* PREFIX_VEX_0F3A30 */
6630   {
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6634   },
6635
6636   /* PREFIX_VEX_0F3A31 */
6637   {
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6641   },
6642
6643   /* PREFIX_VEX_0F3A32 */
6644   {
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6648   },
6649
6650   /* PREFIX_VEX_0F3A33 */
6651   {
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6655   },
6656
6657   /* PREFIX_VEX_0F3A38 */
6658   {
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6662   },
6663
6664   /* PREFIX_VEX_0F3A39 */
6665   {
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6669   },
6670
6671   /* PREFIX_VEX_0F3A40 */
6672   {
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6676   },
6677
6678   /* PREFIX_VEX_0F3A41 */
6679   {
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6683   },
6684
6685   /* PREFIX_VEX_0F3A42 */
6686   {
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6690   },
6691
6692   /* PREFIX_VEX_0F3A44 */
6693   {
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6697   },
6698
6699   /* PREFIX_VEX_0F3A46 */
6700   {
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6704   },
6705
6706   /* PREFIX_VEX_0F3A48 */
6707   {
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6711   },
6712
6713   /* PREFIX_VEX_0F3A49 */
6714   {
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6718   },
6719
6720   /* PREFIX_VEX_0F3A4A */
6721   {
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6725   },
6726
6727   /* PREFIX_VEX_0F3A4B */
6728   {
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6732   },
6733
6734   /* PREFIX_VEX_0F3A4C */
6735   {
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6739   },
6740
6741   /* PREFIX_VEX_0F3A5C */
6742   {
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6746   },
6747
6748   /* PREFIX_VEX_0F3A5D */
6749   {
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6753   },
6754
6755   /* PREFIX_VEX_0F3A5E */
6756   {
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6760   },
6761
6762   /* PREFIX_VEX_0F3A5F */
6763   {
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6767   },
6768
6769   /* PREFIX_VEX_0F3A60 */
6770   {
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6774     { Bad_Opcode },
6775   },
6776
6777   /* PREFIX_VEX_0F3A61 */
6778   {
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6782   },
6783
6784   /* PREFIX_VEX_0F3A62 */
6785   {
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6789   },
6790
6791   /* PREFIX_VEX_0F3A63 */
6792   {
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6796   },
6797
6798   /* PREFIX_VEX_0F3A68 */
6799   {
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6803   },
6804
6805   /* PREFIX_VEX_0F3A69 */
6806   {
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6810   },
6811
6812   /* PREFIX_VEX_0F3A6A */
6813   {
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6817   },
6818
6819   /* PREFIX_VEX_0F3A6B */
6820   {
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6824   },
6825
6826   /* PREFIX_VEX_0F3A6C */
6827   {
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6831   },
6832
6833   /* PREFIX_VEX_0F3A6D */
6834   {
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6838   },
6839
6840   /* PREFIX_VEX_0F3A6E */
6841   {
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6845   },
6846
6847   /* PREFIX_VEX_0F3A6F */
6848   {
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6852   },
6853
6854   /* PREFIX_VEX_0F3A78 */
6855   {
6856     { Bad_Opcode },
6857     { Bad_Opcode },
6858     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6859   },
6860
6861   /* PREFIX_VEX_0F3A79 */
6862   {
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6866   },
6867
6868   /* PREFIX_VEX_0F3A7A */
6869   {
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6873   },
6874
6875   /* PREFIX_VEX_0F3A7B */
6876   {
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6880   },
6881
6882   /* PREFIX_VEX_0F3A7C */
6883   {
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6887     { Bad_Opcode },
6888   },
6889
6890   /* PREFIX_VEX_0F3A7D */
6891   {
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6895   },
6896
6897   /* PREFIX_VEX_0F3A7E */
6898   {
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6902   },
6903
6904   /* PREFIX_VEX_0F3A7F */
6905   {
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6909   },
6910
6911   /* PREFIX_VEX_0F3ACE */
6912   {
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6916   },
6917
6918   /* PREFIX_VEX_0F3ACF */
6919   {
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6923   },
6924
6925   /* PREFIX_VEX_0F3ADF */
6926   {
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6930   },
6931
6932   /* PREFIX_VEX_0F3AF0 */
6933   {
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6938   },
6939
6940 #define NEED_PREFIX_TABLE
6941 #include "i386-dis-evex.h"
6942 #undef NEED_PREFIX_TABLE
6943 };
6944
6945 static const struct dis386 x86_64_table[][2] = {
6946   /* X86_64_06 */
6947   {
6948     { "pushP", { es }, 0 },
6949   },
6950
6951   /* X86_64_07 */
6952   {
6953     { "popP", { es }, 0 },
6954   },
6955
6956   /* X86_64_0D */
6957   {
6958     { "pushP", { cs }, 0 },
6959   },
6960
6961   /* X86_64_16 */
6962   {
6963     { "pushP", { ss }, 0 },
6964   },
6965
6966   /* X86_64_17 */
6967   {
6968     { "popP", { ss }, 0 },
6969   },
6970
6971   /* X86_64_1E */
6972   {
6973     { "pushP", { ds }, 0 },
6974   },
6975
6976   /* X86_64_1F */
6977   {
6978     { "popP", { ds }, 0 },
6979   },
6980
6981   /* X86_64_27 */
6982   {
6983     { "daa", { XX }, 0 },
6984   },
6985
6986   /* X86_64_2F */
6987   {
6988     { "das", { XX }, 0 },
6989   },
6990
6991   /* X86_64_37 */
6992   {
6993     { "aaa", { XX }, 0 },
6994   },
6995
6996   /* X86_64_3F */
6997   {
6998     { "aas", { XX }, 0 },
6999   },
7000
7001   /* X86_64_60 */
7002   {
7003     { "pushaP", { XX }, 0 },
7004   },
7005
7006   /* X86_64_61 */
7007   {
7008     { "popaP", { XX }, 0 },
7009   },
7010
7011   /* X86_64_62 */
7012   {
7013     { MOD_TABLE (MOD_62_32BIT) },
7014     { EVEX_TABLE (EVEX_0F) },
7015   },
7016
7017   /* X86_64_63 */
7018   {
7019     { "arpl", { Ew, Gw }, 0 },
7020     { "movs{lq|xd}", { Gv, Ed }, 0 },
7021   },
7022
7023   /* X86_64_6D */
7024   {
7025     { "ins{R|}", { Yzr, indirDX }, 0 },
7026     { "ins{G|}", { Yzr, indirDX }, 0 },
7027   },
7028
7029   /* X86_64_6F */
7030   {
7031     { "outs{R|}", { indirDXr, Xz }, 0 },
7032     { "outs{G|}", { indirDXr, Xz }, 0 },
7033   },
7034
7035   /* X86_64_82 */
7036   {
7037     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
7038     { REG_TABLE (REG_80) },
7039   },
7040
7041   /* X86_64_9A */
7042   {
7043     { "Jcall{T|}", { Ap }, 0 },
7044   },
7045
7046   /* X86_64_C4 */
7047   {
7048     { MOD_TABLE (MOD_C4_32BIT) },
7049     { VEX_C4_TABLE (VEX_0F) },
7050   },
7051
7052   /* X86_64_C5 */
7053   {
7054     { MOD_TABLE (MOD_C5_32BIT) },
7055     { VEX_C5_TABLE (VEX_0F) },
7056   },
7057
7058   /* X86_64_CE */
7059   {
7060     { "into", { XX }, 0 },
7061   },
7062
7063   /* X86_64_D4 */
7064   {
7065     { "aam", { Ib }, 0 },
7066   },
7067
7068   /* X86_64_D5 */
7069   {
7070     { "aad", { Ib }, 0 },
7071   },
7072
7073   /* X86_64_E8 */
7074   {
7075     { "callP",          { Jv, BND }, 0 },
7076     { "call@",          { Jv, BND }, 0 }
7077   },
7078
7079   /* X86_64_E9 */
7080   {
7081     { "jmpP",           { Jv, BND }, 0 },
7082     { "jmp@",           { Jv, BND }, 0 }
7083   },
7084
7085   /* X86_64_EA */
7086   {
7087     { "Jjmp{T|}", { Ap }, 0 },
7088   },
7089
7090   /* X86_64_0F01_REG_0 */
7091   {
7092     { "sgdt{Q|IQ}", { M }, 0 },
7093     { "sgdt", { M }, 0 },
7094   },
7095
7096   /* X86_64_0F01_REG_1 */
7097   {
7098     { "sidt{Q|IQ}", { M }, 0 },
7099     { "sidt", { M }, 0 },
7100   },
7101
7102   /* X86_64_0F01_REG_2 */
7103   {
7104     { "lgdt{Q|Q}", { M }, 0 },
7105     { "lgdt", { M }, 0 },
7106   },
7107
7108   /* X86_64_0F01_REG_3 */
7109   {
7110     { "lidt{Q|Q}", { M }, 0 },
7111     { "lidt", { M }, 0 },
7112   },
7113 };
7114
7115 static const struct dis386 three_byte_table[][256] = {
7116
7117   /* THREE_BYTE_0F38 */
7118   {
7119     /* 00 */
7120     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7121     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7122     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7123     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7124     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7125     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7126     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7127     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7128     /* 08 */
7129     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7130     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7131     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7132     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     /* 10 */
7138     { PREFIX_TABLE (PREFIX_0F3810) },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { PREFIX_TABLE (PREFIX_0F3814) },
7143     { PREFIX_TABLE (PREFIX_0F3815) },
7144     { Bad_Opcode },
7145     { PREFIX_TABLE (PREFIX_0F3817) },
7146     /* 18 */
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7152     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7153     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7154     { Bad_Opcode },
7155     /* 20 */
7156     { PREFIX_TABLE (PREFIX_0F3820) },
7157     { PREFIX_TABLE (PREFIX_0F3821) },
7158     { PREFIX_TABLE (PREFIX_0F3822) },
7159     { PREFIX_TABLE (PREFIX_0F3823) },
7160     { PREFIX_TABLE (PREFIX_0F3824) },
7161     { PREFIX_TABLE (PREFIX_0F3825) },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     /* 28 */
7165     { PREFIX_TABLE (PREFIX_0F3828) },
7166     { PREFIX_TABLE (PREFIX_0F3829) },
7167     { PREFIX_TABLE (PREFIX_0F382A) },
7168     { PREFIX_TABLE (PREFIX_0F382B) },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     /* 30 */
7174     { PREFIX_TABLE (PREFIX_0F3830) },
7175     { PREFIX_TABLE (PREFIX_0F3831) },
7176     { PREFIX_TABLE (PREFIX_0F3832) },
7177     { PREFIX_TABLE (PREFIX_0F3833) },
7178     { PREFIX_TABLE (PREFIX_0F3834) },
7179     { PREFIX_TABLE (PREFIX_0F3835) },
7180     { Bad_Opcode },
7181     { PREFIX_TABLE (PREFIX_0F3837) },
7182     /* 38 */
7183     { PREFIX_TABLE (PREFIX_0F3838) },
7184     { PREFIX_TABLE (PREFIX_0F3839) },
7185     { PREFIX_TABLE (PREFIX_0F383A) },
7186     { PREFIX_TABLE (PREFIX_0F383B) },
7187     { PREFIX_TABLE (PREFIX_0F383C) },
7188     { PREFIX_TABLE (PREFIX_0F383D) },
7189     { PREFIX_TABLE (PREFIX_0F383E) },
7190     { PREFIX_TABLE (PREFIX_0F383F) },
7191     /* 40 */
7192     { PREFIX_TABLE (PREFIX_0F3840) },
7193     { PREFIX_TABLE (PREFIX_0F3841) },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     /* 48 */
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     /* 50 */
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     /* 58 */
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     /* 60 */
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     /* 68 */
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     /* 70 */
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     /* 78 */
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     /* 80 */
7264     { PREFIX_TABLE (PREFIX_0F3880) },
7265     { PREFIX_TABLE (PREFIX_0F3881) },
7266     { PREFIX_TABLE (PREFIX_0F3882) },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     /* 88 */
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     /* 90 */
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     /* 98 */
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     /* a0 */
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     /* a8 */
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     /* b0 */
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     /* b8 */
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     /* c0 */
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     /* c8 */
7345     { PREFIX_TABLE (PREFIX_0F38C8) },
7346     { PREFIX_TABLE (PREFIX_0F38C9) },
7347     { PREFIX_TABLE (PREFIX_0F38CA) },
7348     { PREFIX_TABLE (PREFIX_0F38CB) },
7349     { PREFIX_TABLE (PREFIX_0F38CC) },
7350     { PREFIX_TABLE (PREFIX_0F38CD) },
7351     { Bad_Opcode },
7352     { PREFIX_TABLE (PREFIX_0F38CF) },
7353     /* d0 */
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     /* d8 */
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { PREFIX_TABLE (PREFIX_0F38DB) },
7367     { PREFIX_TABLE (PREFIX_0F38DC) },
7368     { PREFIX_TABLE (PREFIX_0F38DD) },
7369     { PREFIX_TABLE (PREFIX_0F38DE) },
7370     { PREFIX_TABLE (PREFIX_0F38DF) },
7371     /* e0 */
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     /* e8 */
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     /* f0 */
7390     { PREFIX_TABLE (PREFIX_0F38F0) },
7391     { PREFIX_TABLE (PREFIX_0F38F1) },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { PREFIX_TABLE (PREFIX_0F38F5) },
7396     { PREFIX_TABLE (PREFIX_0F38F6) },
7397     { Bad_Opcode },
7398     /* f8 */
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407   },
7408   /* THREE_BYTE_0F3A */
7409   {
7410     /* 00 */
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     /* 08 */
7420     { PREFIX_TABLE (PREFIX_0F3A08) },
7421     { PREFIX_TABLE (PREFIX_0F3A09) },
7422     { PREFIX_TABLE (PREFIX_0F3A0A) },
7423     { PREFIX_TABLE (PREFIX_0F3A0B) },
7424     { PREFIX_TABLE (PREFIX_0F3A0C) },
7425     { PREFIX_TABLE (PREFIX_0F3A0D) },
7426     { PREFIX_TABLE (PREFIX_0F3A0E) },
7427     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7428     /* 10 */
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { PREFIX_TABLE (PREFIX_0F3A14) },
7434     { PREFIX_TABLE (PREFIX_0F3A15) },
7435     { PREFIX_TABLE (PREFIX_0F3A16) },
7436     { PREFIX_TABLE (PREFIX_0F3A17) },
7437     /* 18 */
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     /* 20 */
7447     { PREFIX_TABLE (PREFIX_0F3A20) },
7448     { PREFIX_TABLE (PREFIX_0F3A21) },
7449     { PREFIX_TABLE (PREFIX_0F3A22) },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     /* 28 */
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     /* 30 */
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     /* 38 */
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     /* 40 */
7483     { PREFIX_TABLE (PREFIX_0F3A40) },
7484     { PREFIX_TABLE (PREFIX_0F3A41) },
7485     { PREFIX_TABLE (PREFIX_0F3A42) },
7486     { Bad_Opcode },
7487     { PREFIX_TABLE (PREFIX_0F3A44) },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     /* 48 */
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     /* 50 */
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     /* 58 */
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     /* 60 */
7519     { PREFIX_TABLE (PREFIX_0F3A60) },
7520     { PREFIX_TABLE (PREFIX_0F3A61) },
7521     { PREFIX_TABLE (PREFIX_0F3A62) },
7522     { PREFIX_TABLE (PREFIX_0F3A63) },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     /* 68 */
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     /* 70 */
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     /* 78 */
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     /* 80 */
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     /* 88 */
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     /* 90 */
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     /* 98 */
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     /* a0 */
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     /* a8 */
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     /* b0 */
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     /* b8 */
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     /* c0 */
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     /* c8 */
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { PREFIX_TABLE (PREFIX_0F3ACC) },
7641     { Bad_Opcode },
7642     { PREFIX_TABLE (PREFIX_0F3ACE) },
7643     { PREFIX_TABLE (PREFIX_0F3ACF) },
7644     /* d0 */
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     /* d8 */
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { PREFIX_TABLE (PREFIX_0F3ADF) },
7662     /* e0 */
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     /* e8 */
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     /* f0 */
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     /* f8 */
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698   },
7699 };
7700
7701 static const struct dis386 xop_table[][256] = {
7702   /* XOP_08 */
7703   {
7704     /* 00 */
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     /* 08 */
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     /* 10 */
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     /* 18 */
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     /* 20 */
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     /* 28 */
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     /* 30 */
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     /* 38 */
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     /* 40 */
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     /* 48 */
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     /* 50 */
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     /* 58 */
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     /* 60 */
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     /* 68 */
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     /* 70 */
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     /* 78 */
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     /* 80 */
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7855     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7856     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7857     /* 88 */
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7865     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7866     /* 90 */
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7873     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7874     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7875     /* 98 */
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7883     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7884     /* a0 */
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7888     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7892     { Bad_Opcode },
7893     /* a8 */
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     /* b0 */
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7910     { Bad_Opcode },
7911     /* b8 */
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     /* c0 */
7921     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7922     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7923     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7924     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     /* c8 */
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7935     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7936     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7937     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7938     /* d0 */
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     /* d8 */
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     /* e0 */
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     /* e8 */
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7971     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7972     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7973     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7974     /* f0 */
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     /* f8 */
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992   },
7993   /* XOP_09 */
7994   {
7995     /* 00 */
7996     { Bad_Opcode },
7997     { REG_TABLE (REG_XOP_TBM_01) },
7998     { REG_TABLE (REG_XOP_TBM_02) },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     /* 08 */
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     /* 10 */
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { REG_TABLE (REG_XOP_LWPCB) },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     /* 18 */
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     /* 20 */
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     /* 28 */
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     /* 30 */
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     /* 38 */
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     /* 40 */
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     /* 48 */
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     /* 50 */
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     /* 58 */
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     /* 60 */
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     /* 68 */
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     /* 70 */
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     /* 78 */
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     /* 80 */
8140     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8141     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8142     { "vfrczss",        { XM, EXd }, 0 },
8143     { "vfrczsd",        { XM, EXq }, 0 },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     /* 88 */
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     /* 90 */
8158     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8159     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8160     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8161     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8162     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8163     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8164     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8165     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8166     /* 98 */
8167     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8168     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8169     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8170     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     /* a0 */
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     /* a8 */
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     /* b0 */
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     /* b8 */
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     /* c0 */
8212     { Bad_Opcode },
8213     { "vphaddbw",       { XM, EXxmm }, 0 },
8214     { "vphaddbd",       { XM, EXxmm }, 0 },
8215     { "vphaddbq",       { XM, EXxmm }, 0 },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { "vphaddwd",       { XM, EXxmm }, 0 },
8219     { "vphaddwq",       { XM, EXxmm }, 0 },
8220     /* c8 */
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { "vphadddq",       { XM, EXxmm }, 0 },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     /* d0 */
8230     { Bad_Opcode },
8231     { "vphaddubw",      { XM, EXxmm }, 0 },
8232     { "vphaddubd",      { XM, EXxmm }, 0 },
8233     { "vphaddubq",      { XM, EXxmm }, 0 },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { "vphadduwd",      { XM, EXxmm }, 0 },
8237     { "vphadduwq",      { XM, EXxmm }, 0 },
8238     /* d8 */
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { "vphaddudq",      { XM, EXxmm }, 0 },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     /* e0 */
8248     { Bad_Opcode },
8249     { "vphsubbw",       { XM, EXxmm }, 0 },
8250     { "vphsubwd",       { XM, EXxmm }, 0 },
8251     { "vphsubdq",       { XM, EXxmm }, 0 },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     /* e8 */
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     /* f0 */
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     /* f8 */
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283   },
8284   /* XOP_0A */
8285   {
8286     /* 00 */
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     /* 08 */
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     /* 10 */
8305     { "bextr",  { Gv, Ev, Iq }, 0 },
8306     { Bad_Opcode },
8307     { REG_TABLE (REG_XOP_LWP) },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     /* 18 */
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     /* 20 */
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     /* 28 */
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     /* 30 */
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     /* 38 */
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     /* 40 */
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     /* 48 */
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     /* 50 */
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     /* 58 */
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     /* 60 */
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     /* 68 */
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     /* 70 */
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     /* 78 */
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     /* 80 */
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     /* 88 */
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     /* 90 */
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     /* 98 */
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     /* a0 */
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     /* a8 */
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     /* b0 */
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     /* b8 */
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     /* c0 */
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     /* c8 */
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     /* d0 */
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     /* d8 */
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     /* e0 */
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     /* e8 */
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     /* f0 */
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     /* f8 */
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574   },
8575 };
8576
8577 static const struct dis386 vex_table[][256] = {
8578   /* VEX_0F */
8579   {
8580     /* 00 */
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     /* 08 */
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     /* 10 */
8599     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8600     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8601     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8602     { MOD_TABLE (MOD_VEX_0F13) },
8603     { VEX_W_TABLE (VEX_W_0F14) },
8604     { VEX_W_TABLE (VEX_W_0F15) },
8605     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8606     { MOD_TABLE (MOD_VEX_0F17) },
8607     /* 18 */
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     /* 20 */
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     /* 28 */
8626     { VEX_W_TABLE (VEX_W_0F28) },
8627     { VEX_W_TABLE (VEX_W_0F29) },
8628     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8629     { MOD_TABLE (MOD_VEX_0F2B) },
8630     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8631     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8632     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8633     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8634     /* 30 */
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     /* 38 */
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     /* 40 */
8653     { Bad_Opcode },
8654     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8655     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8656     { Bad_Opcode },
8657     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8658     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8659     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8660     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8661     /* 48 */
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8665     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     /* 50 */
8671     { MOD_TABLE (MOD_VEX_0F50) },
8672     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8673     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8674     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8675     { "vandpX",         { XM, Vex, EXx }, 0 },
8676     { "vandnpX",        { XM, Vex, EXx }, 0 },
8677     { "vorpX",          { XM, Vex, EXx }, 0 },
8678     { "vxorpX",         { XM, Vex, EXx }, 0 },
8679     /* 58 */
8680     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8681     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8682     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8683     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8684     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8685     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8686     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8687     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8688     /* 60 */
8689     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8690     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8691     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8692     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8693     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8694     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8695     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8696     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8697     /* 68 */
8698     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8706     /* 70 */
8707     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8708     { REG_TABLE (REG_VEX_0F71) },
8709     { REG_TABLE (REG_VEX_0F72) },
8710     { REG_TABLE (REG_VEX_0F73) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8712     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8713     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8714     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8715     /* 78 */
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8721     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8723     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8724     /* 80 */
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     /* 88 */
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     /* 90 */
8743     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8745     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     /* 98 */
8752     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     /* a0 */
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     /* a8 */
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { REG_TABLE (REG_VEX_0FAE) },
8777     { Bad_Opcode },
8778     /* b0 */
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     /* b8 */
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     /* c0 */
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8800     { Bad_Opcode },
8801     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8802     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8803     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8804     { Bad_Opcode },
8805     /* c8 */
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     /* d0 */
8815     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8816     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8817     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8818     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8819     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8820     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8821     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8822     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8823     /* d8 */
8824     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8825     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8826     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8827     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8828     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8829     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8830     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8831     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8832     /* e0 */
8833     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8834     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8835     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8836     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8837     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8838     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8839     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8840     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8841     /* e8 */
8842     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8843     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8844     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8845     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8846     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8847     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8848     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8849     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8850     /* f0 */
8851     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8852     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8853     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8854     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8855     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8856     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8857     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8858     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8859     /* f8 */
8860     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8861     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8862     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8863     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8864     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8865     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8866     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8867     { Bad_Opcode },
8868   },
8869   /* VEX_0F38 */
8870   {
8871     /* 00 */
8872     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8873     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8874     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8875     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8876     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8877     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8878     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8879     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8880     /* 08 */
8881     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8882     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8883     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8889     /* 10 */
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8898     /* 18 */
8899     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8902     { Bad_Opcode },
8903     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8906     { Bad_Opcode },
8907     /* 20 */
8908     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8909     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     /* 28 */
8917     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8925     /* 30 */
8926     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8934     /* 38 */
8935     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8943     /* 40 */
8944     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8952     /* 48 */
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     /* 50 */
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     /* 58 */
8971     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     /* 60 */
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     /* 68 */
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     /* 70 */
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     /* 78 */
9007     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     /* 80 */
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     /* 88 */
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9030     { Bad_Opcode },
9031     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9032     { Bad_Opcode },
9033     /* 90 */
9034     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9035     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9036     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9037     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9042     /* 98 */
9043     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9045     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9046     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9051     /* a0 */
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9060     /* a8 */
9061     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9062     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9063     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9064     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9065     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9068     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9069     /* b0 */
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9078     /* b8 */
9079     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9080     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9081     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9082     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9083     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9084     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9085     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9086     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9087     /* c0 */
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     /* c8 */
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9105     /* d0 */
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     /* d8 */
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9119     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9123     /* e0 */
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     /* e8 */
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     /* f0 */
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9145     { REG_TABLE (REG_VEX_0F38F3) },
9146     { Bad_Opcode },
9147     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9148     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9149     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9150     /* f8 */
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159   },
9160   /* VEX_0F3A */
9161   {
9162     /* 00 */
9163     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9164     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9165     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9166     { Bad_Opcode },
9167     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9168     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9169     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9170     { Bad_Opcode },
9171     /* 08 */
9172     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9173     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9174     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9175     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9176     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9177     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9178     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9179     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9180     /* 10 */
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9186     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9187     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9188     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9189     /* 18 */
9190     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9191     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     /* 20 */
9199     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9200     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9201     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     /* 28 */
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     /* 30 */
9217     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9218     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9219     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9220     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     /* 38 */
9226     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9227     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     /* 40 */
9235     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9236     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9237     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9238     { Bad_Opcode },
9239     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9240     { Bad_Opcode },
9241     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9242     { Bad_Opcode },
9243     /* 48 */
9244     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9245     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9246     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9247     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9248     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     /* 50 */
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     /* 58 */
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9267     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9268     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9269     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9270     /* 60 */
9271     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9272     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9273     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9274     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     /* 68 */
9280     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9281     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9282     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9283     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9284     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9285     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9286     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9287     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9288     /* 70 */
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     /* 78 */
9298     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9299     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9300     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9301     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9302     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9303     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9304     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9305     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9306     /* 80 */
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     { Bad_Opcode },
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315     /* 88 */
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     /* 90 */
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     /* 98 */
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     /* a0 */
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347     { Bad_Opcode },
9348     { Bad_Opcode },
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     /* a8 */
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     /* b0 */
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     { Bad_Opcode },
9369     /* b8 */
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     { Bad_Opcode },
9373     { Bad_Opcode },
9374     { Bad_Opcode },
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     /* c0 */
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     /* c8 */
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9395     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9396     /* d0 */
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     /* d8 */
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     { Bad_Opcode },
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9414     /* e0 */
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     /* e8 */
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     { Bad_Opcode },
9427     { Bad_Opcode },
9428     { Bad_Opcode },
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     /* f0 */
9433     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     /* f8 */
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450   },
9451 };
9452
9453 #define NEED_OPCODE_TABLE
9454 #include "i386-dis-evex.h"
9455 #undef NEED_OPCODE_TABLE
9456 static const struct dis386 vex_len_table[][2] = {
9457   /* VEX_LEN_0F10_P_1 */
9458   {
9459     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9460     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9461   },
9462
9463   /* VEX_LEN_0F10_P_3 */
9464   {
9465     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9466     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9467   },
9468
9469   /* VEX_LEN_0F11_P_1 */
9470   {
9471     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9472     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9473   },
9474
9475   /* VEX_LEN_0F11_P_3 */
9476   {
9477     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9478     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9479   },
9480
9481   /* VEX_LEN_0F12_P_0_M_0 */
9482   {
9483     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9484   },
9485
9486   /* VEX_LEN_0F12_P_0_M_1 */
9487   {
9488     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9489   },
9490
9491   /* VEX_LEN_0F12_P_2 */
9492   {
9493     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9494   },
9495
9496   /* VEX_LEN_0F13_M_0 */
9497   {
9498     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9499   },
9500
9501   /* VEX_LEN_0F16_P_0_M_0 */
9502   {
9503     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9504   },
9505
9506   /* VEX_LEN_0F16_P_0_M_1 */
9507   {
9508     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9509   },
9510
9511   /* VEX_LEN_0F16_P_2 */
9512   {
9513     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9514   },
9515
9516   /* VEX_LEN_0F17_M_0 */
9517   {
9518     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9519   },
9520
9521   /* VEX_LEN_0F2A_P_1 */
9522   {
9523     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9524     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9525   },
9526
9527   /* VEX_LEN_0F2A_P_3 */
9528   {
9529     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9530     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9531   },
9532
9533   /* VEX_LEN_0F2C_P_1 */
9534   {
9535     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9536     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9537   },
9538
9539   /* VEX_LEN_0F2C_P_3 */
9540   {
9541     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9542     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9543   },
9544
9545   /* VEX_LEN_0F2D_P_1 */
9546   {
9547     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9548     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9549   },
9550
9551   /* VEX_LEN_0F2D_P_3 */
9552   {
9553     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9554     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9555   },
9556
9557   /* VEX_LEN_0F2E_P_0 */
9558   {
9559     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9560     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9561   },
9562
9563   /* VEX_LEN_0F2E_P_2 */
9564   {
9565     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9566     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9567   },
9568
9569   /* VEX_LEN_0F2F_P_0 */
9570   {
9571     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9572     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9573   },
9574
9575   /* VEX_LEN_0F2F_P_2 */
9576   {
9577     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9578     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9579   },
9580
9581   /* VEX_LEN_0F41_P_0 */
9582   {
9583     { Bad_Opcode },
9584     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9585   },
9586   /* VEX_LEN_0F41_P_2 */
9587   {
9588     { Bad_Opcode },
9589     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9590   },
9591   /* VEX_LEN_0F42_P_0 */
9592   {
9593     { Bad_Opcode },
9594     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9595   },
9596   /* VEX_LEN_0F42_P_2 */
9597   {
9598     { Bad_Opcode },
9599     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9600   },
9601   /* VEX_LEN_0F44_P_0 */
9602   {
9603     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9604   },
9605   /* VEX_LEN_0F44_P_2 */
9606   {
9607     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9608   },
9609   /* VEX_LEN_0F45_P_0 */
9610   {
9611     { Bad_Opcode },
9612     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9613   },
9614   /* VEX_LEN_0F45_P_2 */
9615   {
9616     { Bad_Opcode },
9617     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9618   },
9619   /* VEX_LEN_0F46_P_0 */
9620   {
9621     { Bad_Opcode },
9622     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9623   },
9624   /* VEX_LEN_0F46_P_2 */
9625   {
9626     { Bad_Opcode },
9627     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9628   },
9629   /* VEX_LEN_0F47_P_0 */
9630   {
9631     { Bad_Opcode },
9632     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9633   },
9634   /* VEX_LEN_0F47_P_2 */
9635   {
9636     { Bad_Opcode },
9637     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9638   },
9639   /* VEX_LEN_0F4A_P_0 */
9640   {
9641     { Bad_Opcode },
9642     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9643   },
9644   /* VEX_LEN_0F4A_P_2 */
9645   {
9646     { Bad_Opcode },
9647     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9648   },
9649   /* VEX_LEN_0F4B_P_0 */
9650   {
9651     { Bad_Opcode },
9652     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9653   },
9654   /* VEX_LEN_0F4B_P_2 */
9655   {
9656     { Bad_Opcode },
9657     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9658   },
9659
9660   /* VEX_LEN_0F51_P_1 */
9661   {
9662     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9663     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9664   },
9665
9666   /* VEX_LEN_0F51_P_3 */
9667   {
9668     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9669     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9670   },
9671
9672   /* VEX_LEN_0F52_P_1 */
9673   {
9674     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9675     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9676   },
9677
9678   /* VEX_LEN_0F53_P_1 */
9679   {
9680     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9681     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9682   },
9683
9684   /* VEX_LEN_0F58_P_1 */
9685   {
9686     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9687     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9688   },
9689
9690   /* VEX_LEN_0F58_P_3 */
9691   {
9692     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9693     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9694   },
9695
9696   /* VEX_LEN_0F59_P_1 */
9697   {
9698     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9699     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9700   },
9701
9702   /* VEX_LEN_0F59_P_3 */
9703   {
9704     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9705     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9706   },
9707
9708   /* VEX_LEN_0F5A_P_1 */
9709   {
9710     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9711     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9712   },
9713
9714   /* VEX_LEN_0F5A_P_3 */
9715   {
9716     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9717     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9718   },
9719
9720   /* VEX_LEN_0F5C_P_1 */
9721   {
9722     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9723     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9724   },
9725
9726   /* VEX_LEN_0F5C_P_3 */
9727   {
9728     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9729     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9730   },
9731
9732   /* VEX_LEN_0F5D_P_1 */
9733   {
9734     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9735     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9736   },
9737
9738   /* VEX_LEN_0F5D_P_3 */
9739   {
9740     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9741     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9742   },
9743
9744   /* VEX_LEN_0F5E_P_1 */
9745   {
9746     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9747     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9748   },
9749
9750   /* VEX_LEN_0F5E_P_3 */
9751   {
9752     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9753     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9754   },
9755
9756   /* VEX_LEN_0F5F_P_1 */
9757   {
9758     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9759     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9760   },
9761
9762   /* VEX_LEN_0F5F_P_3 */
9763   {
9764     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9765     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9766   },
9767
9768   /* VEX_LEN_0F6E_P_2 */
9769   {
9770     { "vmovK",          { XMScalar, Edq }, 0 },
9771     { "vmovK",          { XMScalar, Edq }, 0 },
9772   },
9773
9774   /* VEX_LEN_0F7E_P_1 */
9775   {
9776     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9777     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9778   },
9779
9780   /* VEX_LEN_0F7E_P_2 */
9781   {
9782     { "vmovK",          { Edq, XMScalar }, 0 },
9783     { "vmovK",          { Edq, XMScalar }, 0 },
9784   },
9785
9786   /* VEX_LEN_0F90_P_0 */
9787   {
9788     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9789   },
9790
9791   /* VEX_LEN_0F90_P_2 */
9792   {
9793     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9794   },
9795
9796   /* VEX_LEN_0F91_P_0 */
9797   {
9798     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9799   },
9800
9801   /* VEX_LEN_0F91_P_2 */
9802   {
9803     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9804   },
9805
9806   /* VEX_LEN_0F92_P_0 */
9807   {
9808     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9809   },
9810
9811   /* VEX_LEN_0F92_P_2 */
9812   {
9813     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9814   },
9815
9816   /* VEX_LEN_0F92_P_3 */
9817   {
9818     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9819   },
9820
9821   /* VEX_LEN_0F93_P_0 */
9822   {
9823     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9824   },
9825
9826   /* VEX_LEN_0F93_P_2 */
9827   {
9828     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9829   },
9830
9831   /* VEX_LEN_0F93_P_3 */
9832   {
9833     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9834   },
9835
9836   /* VEX_LEN_0F98_P_0 */
9837   {
9838     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9839   },
9840
9841   /* VEX_LEN_0F98_P_2 */
9842   {
9843     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9844   },
9845
9846   /* VEX_LEN_0F99_P_0 */
9847   {
9848     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9849   },
9850
9851   /* VEX_LEN_0F99_P_2 */
9852   {
9853     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9854   },
9855
9856   /* VEX_LEN_0FAE_R_2_M_0 */
9857   {
9858     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9859   },
9860
9861   /* VEX_LEN_0FAE_R_3_M_0 */
9862   {
9863     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9864   },
9865
9866   /* VEX_LEN_0FC2_P_1 */
9867   {
9868     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9869     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9870   },
9871
9872   /* VEX_LEN_0FC2_P_3 */
9873   {
9874     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9875     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9876   },
9877
9878   /* VEX_LEN_0FC4_P_2 */
9879   {
9880     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9881   },
9882
9883   /* VEX_LEN_0FC5_P_2 */
9884   {
9885     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9886   },
9887
9888   /* VEX_LEN_0FD6_P_2 */
9889   {
9890     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9891     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9892   },
9893
9894   /* VEX_LEN_0FF7_P_2 */
9895   {
9896     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9897   },
9898
9899   /* VEX_LEN_0F3816_P_2 */
9900   {
9901     { Bad_Opcode },
9902     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9903   },
9904
9905   /* VEX_LEN_0F3819_P_2 */
9906   {
9907     { Bad_Opcode },
9908     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9909   },
9910
9911   /* VEX_LEN_0F381A_P_2_M_0 */
9912   {
9913     { Bad_Opcode },
9914     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9915   },
9916
9917   /* VEX_LEN_0F3836_P_2 */
9918   {
9919     { Bad_Opcode },
9920     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9921   },
9922
9923   /* VEX_LEN_0F3841_P_2 */
9924   {
9925     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9926   },
9927
9928   /* VEX_LEN_0F385A_P_2_M_0 */
9929   {
9930     { Bad_Opcode },
9931     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9932   },
9933
9934   /* VEX_LEN_0F38DB_P_2 */
9935   {
9936     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9937   },
9938
9939   /* VEX_LEN_0F38F2_P_0 */
9940   {
9941     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9942   },
9943
9944   /* VEX_LEN_0F38F3_R_1_P_0 */
9945   {
9946     { "blsrS",          { VexGdq, Edq }, 0 },
9947   },
9948
9949   /* VEX_LEN_0F38F3_R_2_P_0 */
9950   {
9951     { "blsmskS",        { VexGdq, Edq }, 0 },
9952   },
9953
9954   /* VEX_LEN_0F38F3_R_3_P_0 */
9955   {
9956     { "blsiS",          { VexGdq, Edq }, 0 },
9957   },
9958
9959   /* VEX_LEN_0F38F5_P_0 */
9960   {
9961     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9962   },
9963
9964   /* VEX_LEN_0F38F5_P_1 */
9965   {
9966     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9967   },
9968
9969   /* VEX_LEN_0F38F5_P_3 */
9970   {
9971     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9972   },
9973
9974   /* VEX_LEN_0F38F6_P_3 */
9975   {
9976     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9977   },
9978
9979   /* VEX_LEN_0F38F7_P_0 */
9980   {
9981     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9982   },
9983
9984   /* VEX_LEN_0F38F7_P_1 */
9985   {
9986     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9987   },
9988
9989   /* VEX_LEN_0F38F7_P_2 */
9990   {
9991     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9992   },
9993
9994   /* VEX_LEN_0F38F7_P_3 */
9995   {
9996     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9997   },
9998
9999   /* VEX_LEN_0F3A00_P_2 */
10000   {
10001     { Bad_Opcode },
10002     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10003   },
10004
10005   /* VEX_LEN_0F3A01_P_2 */
10006   {
10007     { Bad_Opcode },
10008     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10009   },
10010
10011   /* VEX_LEN_0F3A06_P_2 */
10012   {
10013     { Bad_Opcode },
10014     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10015   },
10016
10017   /* VEX_LEN_0F3A0A_P_2 */
10018   {
10019     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10020     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10021   },
10022
10023   /* VEX_LEN_0F3A0B_P_2 */
10024   {
10025     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10026     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10027   },
10028
10029   /* VEX_LEN_0F3A14_P_2 */
10030   {
10031     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10032   },
10033
10034   /* VEX_LEN_0F3A15_P_2 */
10035   {
10036     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10037   },
10038
10039   /* VEX_LEN_0F3A16_P_2  */
10040   {
10041     { "vpextrK",        { Edq, XM, Ib }, 0 },
10042   },
10043
10044   /* VEX_LEN_0F3A17_P_2 */
10045   {
10046     { "vextractps",     { Edqd, XM, Ib }, 0 },
10047   },
10048
10049   /* VEX_LEN_0F3A18_P_2 */
10050   {
10051     { Bad_Opcode },
10052     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10053   },
10054
10055   /* VEX_LEN_0F3A19_P_2 */
10056   {
10057     { Bad_Opcode },
10058     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10059   },
10060
10061   /* VEX_LEN_0F3A20_P_2 */
10062   {
10063     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10064   },
10065
10066   /* VEX_LEN_0F3A21_P_2 */
10067   {
10068     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10069   },
10070
10071   /* VEX_LEN_0F3A22_P_2 */
10072   {
10073     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10074   },
10075
10076   /* VEX_LEN_0F3A30_P_2 */
10077   {
10078     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10079   },
10080
10081   /* VEX_LEN_0F3A31_P_2 */
10082   {
10083     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10084   },
10085
10086   /* VEX_LEN_0F3A32_P_2 */
10087   {
10088     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10089   },
10090
10091   /* VEX_LEN_0F3A33_P_2 */
10092   {
10093     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10094   },
10095
10096   /* VEX_LEN_0F3A38_P_2 */
10097   {
10098     { Bad_Opcode },
10099     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10100   },
10101
10102   /* VEX_LEN_0F3A39_P_2 */
10103   {
10104     { Bad_Opcode },
10105     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10106   },
10107
10108   /* VEX_LEN_0F3A41_P_2 */
10109   {
10110     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10111   },
10112
10113   /* VEX_LEN_0F3A44_P_2 */
10114   {
10115     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10116   },
10117
10118   /* VEX_LEN_0F3A46_P_2 */
10119   {
10120     { Bad_Opcode },
10121     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10122   },
10123
10124   /* VEX_LEN_0F3A60_P_2 */
10125   {
10126     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10127   },
10128
10129   /* VEX_LEN_0F3A61_P_2 */
10130   {
10131     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10132   },
10133
10134   /* VEX_LEN_0F3A62_P_2 */
10135   {
10136     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10137   },
10138
10139   /* VEX_LEN_0F3A63_P_2 */
10140   {
10141     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10142   },
10143
10144   /* VEX_LEN_0F3A6A_P_2 */
10145   {
10146     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10147   },
10148
10149   /* VEX_LEN_0F3A6B_P_2 */
10150   {
10151     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10152   },
10153
10154   /* VEX_LEN_0F3A6E_P_2 */
10155   {
10156     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10157   },
10158
10159   /* VEX_LEN_0F3A6F_P_2 */
10160   {
10161     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10162   },
10163
10164   /* VEX_LEN_0F3A7A_P_2 */
10165   {
10166     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10167   },
10168
10169   /* VEX_LEN_0F3A7B_P_2 */
10170   {
10171     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10172   },
10173
10174   /* VEX_LEN_0F3A7E_P_2 */
10175   {
10176     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10177   },
10178
10179   /* VEX_LEN_0F3A7F_P_2 */
10180   {
10181     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10182   },
10183
10184   /* VEX_LEN_0F3ADF_P_2 */
10185   {
10186     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10187   },
10188
10189   /* VEX_LEN_0F3AF0_P_3 */
10190   {
10191     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10192   },
10193
10194   /* VEX_LEN_0FXOP_08_CC */
10195   {
10196      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10197   },
10198
10199   /* VEX_LEN_0FXOP_08_CD */
10200   {
10201      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10202   },
10203
10204   /* VEX_LEN_0FXOP_08_CE */
10205   {
10206      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10207   },
10208
10209   /* VEX_LEN_0FXOP_08_CF */
10210   {
10211      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10212   },
10213
10214   /* VEX_LEN_0FXOP_08_EC */
10215   {
10216      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10217   },
10218
10219   /* VEX_LEN_0FXOP_08_ED */
10220   {
10221      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10222   },
10223
10224   /* VEX_LEN_0FXOP_08_EE */
10225   {
10226      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10227   },
10228
10229   /* VEX_LEN_0FXOP_08_EF */
10230   {
10231      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10232   },
10233
10234   /* VEX_LEN_0FXOP_09_80 */
10235   {
10236     { "vfrczps",        { XM, EXxmm }, 0 },
10237     { "vfrczps",        { XM, EXymmq }, 0 },
10238   },
10239
10240   /* VEX_LEN_0FXOP_09_81 */
10241   {
10242     { "vfrczpd",        { XM, EXxmm }, 0 },
10243     { "vfrczpd",        { XM, EXymmq }, 0 },
10244   },
10245 };
10246
10247 static const struct dis386 vex_w_table[][2] = {
10248   {
10249     /* VEX_W_0F10_P_0 */
10250     { "vmovups",        { XM, EXx }, 0 },
10251   },
10252   {
10253     /* VEX_W_0F10_P_1 */
10254     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10255   },
10256   {
10257     /* VEX_W_0F10_P_2 */
10258     { "vmovupd",        { XM, EXx }, 0 },
10259   },
10260   {
10261     /* VEX_W_0F10_P_3 */
10262     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10263   },
10264   {
10265     /* VEX_W_0F11_P_0 */
10266     { "vmovups",        { EXxS, XM }, 0 },
10267   },
10268   {
10269     /* VEX_W_0F11_P_1 */
10270     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10271   },
10272   {
10273     /* VEX_W_0F11_P_2 */
10274     { "vmovupd",        { EXxS, XM }, 0 },
10275   },
10276   {
10277     /* VEX_W_0F11_P_3 */
10278     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10279   },
10280   {
10281     /* VEX_W_0F12_P_0_M_0 */
10282     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10283   },
10284   {
10285     /* VEX_W_0F12_P_0_M_1 */
10286     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10287   },
10288   {
10289     /* VEX_W_0F12_P_1 */
10290     { "vmovsldup",      { XM, EXx }, 0 },
10291   },
10292   {
10293     /* VEX_W_0F12_P_2 */
10294     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10295   },
10296   {
10297     /* VEX_W_0F12_P_3 */
10298     { "vmovddup",       { XM, EXymmq }, 0 },
10299   },
10300   {
10301     /* VEX_W_0F13_M_0 */
10302     { "vmovlpX",        { EXq, XM }, 0 },
10303   },
10304   {
10305     /* VEX_W_0F14 */
10306     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10307   },
10308   {
10309     /* VEX_W_0F15 */
10310     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10311   },
10312   {
10313     /* VEX_W_0F16_P_0_M_0 */
10314     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10315   },
10316   {
10317     /* VEX_W_0F16_P_0_M_1 */
10318     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10319   },
10320   {
10321     /* VEX_W_0F16_P_1 */
10322     { "vmovshdup",      { XM, EXx }, 0 },
10323   },
10324   {
10325     /* VEX_W_0F16_P_2 */
10326     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10327   },
10328   {
10329     /* VEX_W_0F17_M_0 */
10330     { "vmovhpX",        { EXq, XM }, 0 },
10331   },
10332   {
10333     /* VEX_W_0F28 */
10334     { "vmovapX",        { XM, EXx }, 0 },
10335   },
10336   {
10337     /* VEX_W_0F29 */
10338     { "vmovapX",        { EXxS, XM }, 0 },
10339   },
10340   {
10341     /* VEX_W_0F2B_M_0 */
10342     { "vmovntpX",       { Mx, XM }, 0 },
10343   },
10344   {
10345     /* VEX_W_0F2E_P_0 */
10346     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10347   },
10348   {
10349     /* VEX_W_0F2E_P_2 */
10350     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10351   },
10352   {
10353     /* VEX_W_0F2F_P_0 */
10354     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10355   },
10356   {
10357     /* VEX_W_0F2F_P_2 */
10358     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10359   },
10360   {
10361     /* VEX_W_0F41_P_0_LEN_1 */
10362     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10363     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10364   },
10365   {
10366     /* VEX_W_0F41_P_2_LEN_1 */
10367     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10368     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10369   },
10370   {
10371     /* VEX_W_0F42_P_0_LEN_1 */
10372     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10373     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10374   },
10375   {
10376     /* VEX_W_0F42_P_2_LEN_1 */
10377     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10378     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10379   },
10380   {
10381     /* VEX_W_0F44_P_0_LEN_0 */
10382     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10383     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10384   },
10385   {
10386     /* VEX_W_0F44_P_2_LEN_0 */
10387     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10388     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10389   },
10390   {
10391     /* VEX_W_0F45_P_0_LEN_1 */
10392     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10393     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10394   },
10395   {
10396     /* VEX_W_0F45_P_2_LEN_1 */
10397     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10398     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10399   },
10400   {
10401     /* VEX_W_0F46_P_0_LEN_1 */
10402     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10403     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10404   },
10405   {
10406     /* VEX_W_0F46_P_2_LEN_1 */
10407     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10408     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10409   },
10410   {
10411     /* VEX_W_0F47_P_0_LEN_1 */
10412     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10413     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10414   },
10415   {
10416     /* VEX_W_0F47_P_2_LEN_1 */
10417     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10418     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10419   },
10420   {
10421     /* VEX_W_0F4A_P_0_LEN_1 */
10422     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10423     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10424   },
10425   {
10426     /* VEX_W_0F4A_P_2_LEN_1 */
10427     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10428     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10429   },
10430   {
10431     /* VEX_W_0F4B_P_0_LEN_1 */
10432     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10433     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10434   },
10435   {
10436     /* VEX_W_0F4B_P_2_LEN_1 */
10437     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10438   },
10439   {
10440     /* VEX_W_0F50_M_0 */
10441     { "vmovmskpX",      { Gdq, XS }, 0 },
10442   },
10443   {
10444     /* VEX_W_0F51_P_0 */
10445     { "vsqrtps",        { XM, EXx }, 0 },
10446   },
10447   {
10448     /* VEX_W_0F51_P_1 */
10449     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10450   },
10451   {
10452     /* VEX_W_0F51_P_2  */
10453     { "vsqrtpd",        { XM, EXx }, 0 },
10454   },
10455   {
10456     /* VEX_W_0F51_P_3 */
10457     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10458   },
10459   {
10460     /* VEX_W_0F52_P_0 */
10461     { "vrsqrtps",       { XM, EXx }, 0 },
10462   },
10463   {
10464     /* VEX_W_0F52_P_1 */
10465     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10466   },
10467   {
10468     /* VEX_W_0F53_P_0  */
10469     { "vrcpps",         { XM, EXx }, 0 },
10470   },
10471   {
10472     /* VEX_W_0F53_P_1  */
10473     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10474   },
10475   {
10476     /* VEX_W_0F58_P_0  */
10477     { "vaddps",         { XM, Vex, EXx }, 0 },
10478   },
10479   {
10480     /* VEX_W_0F58_P_1  */
10481     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10482   },
10483   {
10484     /* VEX_W_0F58_P_2  */
10485     { "vaddpd",         { XM, Vex, EXx }, 0 },
10486   },
10487   {
10488     /* VEX_W_0F58_P_3  */
10489     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10490   },
10491   {
10492     /* VEX_W_0F59_P_0  */
10493     { "vmulps",         { XM, Vex, EXx }, 0 },
10494   },
10495   {
10496     /* VEX_W_0F59_P_1  */
10497     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10498   },
10499   {
10500     /* VEX_W_0F59_P_2  */
10501     { "vmulpd",         { XM, Vex, EXx }, 0 },
10502   },
10503   {
10504     /* VEX_W_0F59_P_3  */
10505     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10506   },
10507   {
10508     /* VEX_W_0F5A_P_0  */
10509     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10510   },
10511   {
10512     /* VEX_W_0F5A_P_1  */
10513     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10514   },
10515   {
10516     /* VEX_W_0F5A_P_3  */
10517     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10518   },
10519   {
10520     /* VEX_W_0F5B_P_0  */
10521     { "vcvtdq2ps",      { XM, EXx }, 0 },
10522   },
10523   {
10524     /* VEX_W_0F5B_P_1  */
10525     { "vcvttps2dq",     { XM, EXx }, 0 },
10526   },
10527   {
10528     /* VEX_W_0F5B_P_2  */
10529     { "vcvtps2dq",      { XM, EXx }, 0 },
10530   },
10531   {
10532     /* VEX_W_0F5C_P_0  */
10533     { "vsubps",         { XM, Vex, EXx }, 0 },
10534   },
10535   {
10536     /* VEX_W_0F5C_P_1  */
10537     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10538   },
10539   {
10540     /* VEX_W_0F5C_P_2  */
10541     { "vsubpd",         { XM, Vex, EXx }, 0 },
10542   },
10543   {
10544     /* VEX_W_0F5C_P_3  */
10545     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10546   },
10547   {
10548     /* VEX_W_0F5D_P_0  */
10549     { "vminps",         { XM, Vex, EXx }, 0 },
10550   },
10551   {
10552     /* VEX_W_0F5D_P_1  */
10553     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10554   },
10555   {
10556     /* VEX_W_0F5D_P_2  */
10557     { "vminpd",         { XM, Vex, EXx }, 0 },
10558   },
10559   {
10560     /* VEX_W_0F5D_P_3  */
10561     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10562   },
10563   {
10564     /* VEX_W_0F5E_P_0  */
10565     { "vdivps",         { XM, Vex, EXx }, 0 },
10566   },
10567   {
10568     /* VEX_W_0F5E_P_1  */
10569     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10570   },
10571   {
10572     /* VEX_W_0F5E_P_2  */
10573     { "vdivpd",         { XM, Vex, EXx }, 0 },
10574   },
10575   {
10576     /* VEX_W_0F5E_P_3  */
10577     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10578   },
10579   {
10580     /* VEX_W_0F5F_P_0  */
10581     { "vmaxps",         { XM, Vex, EXx }, 0 },
10582   },
10583   {
10584     /* VEX_W_0F5F_P_1  */
10585     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10586   },
10587   {
10588     /* VEX_W_0F5F_P_2  */
10589     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10590   },
10591   {
10592     /* VEX_W_0F5F_P_3  */
10593     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10594   },
10595   {
10596     /* VEX_W_0F60_P_2  */
10597     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10598   },
10599   {
10600     /* VEX_W_0F61_P_2  */
10601     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10602   },
10603   {
10604     /* VEX_W_0F62_P_2  */
10605     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10606   },
10607   {
10608     /* VEX_W_0F63_P_2  */
10609     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10610   },
10611   {
10612     /* VEX_W_0F64_P_2  */
10613     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10614   },
10615   {
10616     /* VEX_W_0F65_P_2  */
10617     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10618   },
10619   {
10620     /* VEX_W_0F66_P_2  */
10621     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10622   },
10623   {
10624     /* VEX_W_0F67_P_2  */
10625     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10626   },
10627   {
10628     /* VEX_W_0F68_P_2  */
10629     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10630   },
10631   {
10632     /* VEX_W_0F69_P_2  */
10633     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10634   },
10635   {
10636     /* VEX_W_0F6A_P_2  */
10637     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10638   },
10639   {
10640     /* VEX_W_0F6B_P_2  */
10641     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10642   },
10643   {
10644     /* VEX_W_0F6C_P_2  */
10645     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10646   },
10647   {
10648     /* VEX_W_0F6D_P_2  */
10649     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10650   },
10651   {
10652     /* VEX_W_0F6F_P_1  */
10653     { "vmovdqu",        { XM, EXx }, 0 },
10654   },
10655   {
10656     /* VEX_W_0F6F_P_2  */
10657     { "vmovdqa",        { XM, EXx }, 0 },
10658   },
10659   {
10660     /* VEX_W_0F70_P_1 */
10661     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10662   },
10663   {
10664     /* VEX_W_0F70_P_2 */
10665     { "vpshufd",        { XM, EXx, Ib }, 0 },
10666   },
10667   {
10668     /* VEX_W_0F70_P_3 */
10669     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10670   },
10671   {
10672     /* VEX_W_0F71_R_2_P_2  */
10673     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10674   },
10675   {
10676     /* VEX_W_0F71_R_4_P_2  */
10677     { "vpsraw",         { Vex, XS, Ib }, 0 },
10678   },
10679   {
10680     /* VEX_W_0F71_R_6_P_2  */
10681     { "vpsllw",         { Vex, XS, Ib }, 0 },
10682   },
10683   {
10684     /* VEX_W_0F72_R_2_P_2  */
10685     { "vpsrld",         { Vex, XS, Ib }, 0 },
10686   },
10687   {
10688     /* VEX_W_0F72_R_4_P_2  */
10689     { "vpsrad",         { Vex, XS, Ib }, 0 },
10690   },
10691   {
10692     /* VEX_W_0F72_R_6_P_2  */
10693     { "vpslld",         { Vex, XS, Ib }, 0 },
10694   },
10695   {
10696     /* VEX_W_0F73_R_2_P_2  */
10697     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10698   },
10699   {
10700     /* VEX_W_0F73_R_3_P_2  */
10701     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10702   },
10703   {
10704     /* VEX_W_0F73_R_6_P_2  */
10705     { "vpsllq",         { Vex, XS, Ib }, 0 },
10706   },
10707   {
10708     /* VEX_W_0F73_R_7_P_2  */
10709     { "vpslldq",        { Vex, XS, Ib }, 0 },
10710   },
10711   {
10712     /* VEX_W_0F74_P_2 */
10713     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10714   },
10715   {
10716     /* VEX_W_0F75_P_2 */
10717     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10718   },
10719   {
10720     /* VEX_W_0F76_P_2 */
10721     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10722   },
10723   {
10724     /* VEX_W_0F77_P_0 */
10725     { "",               { VZERO }, 0 },
10726   },
10727   {
10728     /* VEX_W_0F7C_P_2 */
10729     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10730   },
10731   {
10732     /* VEX_W_0F7C_P_3 */
10733     { "vhaddps",        { XM, Vex, EXx }, 0 },
10734   },
10735   {
10736     /* VEX_W_0F7D_P_2 */
10737     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10738   },
10739   {
10740     /* VEX_W_0F7D_P_3 */
10741     { "vhsubps",        { XM, Vex, EXx }, 0 },
10742   },
10743   {
10744     /* VEX_W_0F7E_P_1 */
10745     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10746   },
10747   {
10748     /* VEX_W_0F7F_P_1 */
10749     { "vmovdqu",        { EXxS, XM }, 0 },
10750   },
10751   {
10752     /* VEX_W_0F7F_P_2 */
10753     { "vmovdqa",        { EXxS, XM }, 0 },
10754   },
10755   {
10756     /* VEX_W_0F90_P_0_LEN_0 */
10757     { "kmovw",          { MaskG, MaskE }, 0 },
10758     { "kmovq",          { MaskG, MaskE }, 0 },
10759   },
10760   {
10761     /* VEX_W_0F90_P_2_LEN_0 */
10762     { "kmovb",          { MaskG, MaskBDE }, 0 },
10763     { "kmovd",          { MaskG, MaskBDE }, 0 },
10764   },
10765   {
10766     /* VEX_W_0F91_P_0_LEN_0 */
10767     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10768     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10769   },
10770   {
10771     /* VEX_W_0F91_P_2_LEN_0 */
10772     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10773     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10774   },
10775   {
10776     /* VEX_W_0F92_P_0_LEN_0 */
10777     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10778   },
10779   {
10780     /* VEX_W_0F92_P_2_LEN_0 */
10781     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10782   },
10783   {
10784     /* VEX_W_0F92_P_3_LEN_0 */
10785     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10786     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10787   },
10788   {
10789     /* VEX_W_0F93_P_0_LEN_0 */
10790     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10791   },
10792   {
10793     /* VEX_W_0F93_P_2_LEN_0 */
10794     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10795   },
10796   {
10797     /* VEX_W_0F93_P_3_LEN_0 */
10798     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10799     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10800   },
10801   {
10802     /* VEX_W_0F98_P_0_LEN_0 */
10803     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10804     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10805   },
10806   {
10807     /* VEX_W_0F98_P_2_LEN_0 */
10808     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10809     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10810   },
10811   {
10812     /* VEX_W_0F99_P_0_LEN_0 */
10813     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10814     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10815   },
10816   {
10817     /* VEX_W_0F99_P_2_LEN_0 */
10818     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10819     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10820   },
10821   {
10822     /* VEX_W_0FAE_R_2_M_0 */
10823     { "vldmxcsr",       { Md }, 0 },
10824   },
10825   {
10826     /* VEX_W_0FAE_R_3_M_0 */
10827     { "vstmxcsr",       { Md }, 0 },
10828   },
10829   {
10830     /* VEX_W_0FC2_P_0 */
10831     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10832   },
10833   {
10834     /* VEX_W_0FC2_P_1 */
10835     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10836   },
10837   {
10838     /* VEX_W_0FC2_P_2 */
10839     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10840   },
10841   {
10842     /* VEX_W_0FC2_P_3 */
10843     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10844   },
10845   {
10846     /* VEX_W_0FC4_P_2 */
10847     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10848   },
10849   {
10850     /* VEX_W_0FC5_P_2 */
10851     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10852   },
10853   {
10854     /* VEX_W_0FD0_P_2 */
10855     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10856   },
10857   {
10858     /* VEX_W_0FD0_P_3 */
10859     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10860   },
10861   {
10862     /* VEX_W_0FD1_P_2 */
10863     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10864   },
10865   {
10866     /* VEX_W_0FD2_P_2 */
10867     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10868   },
10869   {
10870     /* VEX_W_0FD3_P_2 */
10871     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10872   },
10873   {
10874     /* VEX_W_0FD4_P_2 */
10875     { "vpaddq",         { XM, Vex, EXx }, 0 },
10876   },
10877   {
10878     /* VEX_W_0FD5_P_2 */
10879     { "vpmullw",        { XM, Vex, EXx }, 0 },
10880   },
10881   {
10882     /* VEX_W_0FD6_P_2 */
10883     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10884   },
10885   {
10886     /* VEX_W_0FD7_P_2_M_1 */
10887     { "vpmovmskb",      { Gdq, XS }, 0 },
10888   },
10889   {
10890     /* VEX_W_0FD8_P_2 */
10891     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10892   },
10893   {
10894     /* VEX_W_0FD9_P_2 */
10895     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10896   },
10897   {
10898     /* VEX_W_0FDA_P_2 */
10899     { "vpminub",        { XM, Vex, EXx }, 0 },
10900   },
10901   {
10902     /* VEX_W_0FDB_P_2 */
10903     { "vpand",          { XM, Vex, EXx }, 0 },
10904   },
10905   {
10906     /* VEX_W_0FDC_P_2 */
10907     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10908   },
10909   {
10910     /* VEX_W_0FDD_P_2 */
10911     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10912   },
10913   {
10914     /* VEX_W_0FDE_P_2 */
10915     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10916   },
10917   {
10918     /* VEX_W_0FDF_P_2 */
10919     { "vpandn",         { XM, Vex, EXx }, 0 },
10920   },
10921   {
10922     /* VEX_W_0FE0_P_2  */
10923     { "vpavgb",         { XM, Vex, EXx }, 0 },
10924   },
10925   {
10926     /* VEX_W_0FE1_P_2  */
10927     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10928   },
10929   {
10930     /* VEX_W_0FE2_P_2  */
10931     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10932   },
10933   {
10934     /* VEX_W_0FE3_P_2  */
10935     { "vpavgw",         { XM, Vex, EXx }, 0 },
10936   },
10937   {
10938     /* VEX_W_0FE4_P_2  */
10939     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
10940   },
10941   {
10942     /* VEX_W_0FE5_P_2  */
10943     { "vpmulhw",        { XM, Vex, EXx }, 0 },
10944   },
10945   {
10946     /* VEX_W_0FE6_P_1  */
10947     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
10948   },
10949   {
10950     /* VEX_W_0FE6_P_2  */
10951     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
10952   },
10953   {
10954     /* VEX_W_0FE6_P_3  */
10955     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
10956   },
10957   {
10958     /* VEX_W_0FE7_P_2_M_0 */
10959     { "vmovntdq",       { Mx, XM }, 0 },
10960   },
10961   {
10962     /* VEX_W_0FE8_P_2  */
10963     { "vpsubsb",        { XM, Vex, EXx }, 0 },
10964   },
10965   {
10966     /* VEX_W_0FE9_P_2  */
10967     { "vpsubsw",        { XM, Vex, EXx }, 0 },
10968   },
10969   {
10970     /* VEX_W_0FEA_P_2  */
10971     { "vpminsw",        { XM, Vex, EXx }, 0 },
10972   },
10973   {
10974     /* VEX_W_0FEB_P_2  */
10975     { "vpor",           { XM, Vex, EXx }, 0 },
10976   },
10977   {
10978     /* VEX_W_0FEC_P_2  */
10979     { "vpaddsb",        { XM, Vex, EXx }, 0 },
10980   },
10981   {
10982     /* VEX_W_0FED_P_2  */
10983     { "vpaddsw",        { XM, Vex, EXx }, 0 },
10984   },
10985   {
10986     /* VEX_W_0FEE_P_2  */
10987     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
10988   },
10989   {
10990     /* VEX_W_0FEF_P_2  */
10991     { "vpxor",          { XM, Vex, EXx }, 0 },
10992   },
10993   {
10994     /* VEX_W_0FF0_P_3_M_0 */
10995     { "vlddqu",         { XM, M }, 0 },
10996   },
10997   {
10998     /* VEX_W_0FF1_P_2 */
10999     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11000   },
11001   {
11002     /* VEX_W_0FF2_P_2 */
11003     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11004   },
11005   {
11006     /* VEX_W_0FF3_P_2 */
11007     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11008   },
11009   {
11010     /* VEX_W_0FF4_P_2 */
11011     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11012   },
11013   {
11014     /* VEX_W_0FF5_P_2 */
11015     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11016   },
11017   {
11018     /* VEX_W_0FF6_P_2 */
11019     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11020   },
11021   {
11022     /* VEX_W_0FF7_P_2 */
11023     { "vmaskmovdqu",    { XM, XS }, 0 },
11024   },
11025   {
11026     /* VEX_W_0FF8_P_2 */
11027     { "vpsubb",         { XM, Vex, EXx }, 0 },
11028   },
11029   {
11030     /* VEX_W_0FF9_P_2 */
11031     { "vpsubw",         { XM, Vex, EXx }, 0 },
11032   },
11033   {
11034     /* VEX_W_0FFA_P_2 */
11035     { "vpsubd",         { XM, Vex, EXx }, 0 },
11036   },
11037   {
11038     /* VEX_W_0FFB_P_2 */
11039     { "vpsubq",         { XM, Vex, EXx }, 0 },
11040   },
11041   {
11042     /* VEX_W_0FFC_P_2 */
11043     { "vpaddb",         { XM, Vex, EXx }, 0 },
11044   },
11045   {
11046     /* VEX_W_0FFD_P_2 */
11047     { "vpaddw",         { XM, Vex, EXx }, 0 },
11048   },
11049   {
11050     /* VEX_W_0FFE_P_2 */
11051     { "vpaddd",         { XM, Vex, EXx }, 0 },
11052   },
11053   {
11054     /* VEX_W_0F3800_P_2  */
11055     { "vpshufb",        { XM, Vex, EXx }, 0 },
11056   },
11057   {
11058     /* VEX_W_0F3801_P_2  */
11059     { "vphaddw",        { XM, Vex, EXx }, 0 },
11060   },
11061   {
11062     /* VEX_W_0F3802_P_2  */
11063     { "vphaddd",        { XM, Vex, EXx }, 0 },
11064   },
11065   {
11066     /* VEX_W_0F3803_P_2  */
11067     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11068   },
11069   {
11070     /* VEX_W_0F3804_P_2  */
11071     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11072   },
11073   {
11074     /* VEX_W_0F3805_P_2  */
11075     { "vphsubw",        { XM, Vex, EXx }, 0 },
11076   },
11077   {
11078     /* VEX_W_0F3806_P_2  */
11079     { "vphsubd",        { XM, Vex, EXx }, 0 },
11080   },
11081   {
11082     /* VEX_W_0F3807_P_2  */
11083     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11084   },
11085   {
11086     /* VEX_W_0F3808_P_2  */
11087     { "vpsignb",        { XM, Vex, EXx }, 0 },
11088   },
11089   {
11090     /* VEX_W_0F3809_P_2  */
11091     { "vpsignw",        { XM, Vex, EXx }, 0 },
11092   },
11093   {
11094     /* VEX_W_0F380A_P_2  */
11095     { "vpsignd",        { XM, Vex, EXx }, 0 },
11096   },
11097   {
11098     /* VEX_W_0F380B_P_2  */
11099     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11100   },
11101   {
11102     /* VEX_W_0F380C_P_2  */
11103     { "vpermilps",      { XM, Vex, EXx }, 0 },
11104   },
11105   {
11106     /* VEX_W_0F380D_P_2  */
11107     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11108   },
11109   {
11110     /* VEX_W_0F380E_P_2  */
11111     { "vtestps",        { XM, EXx }, 0 },
11112   },
11113   {
11114     /* VEX_W_0F380F_P_2  */
11115     { "vtestpd",        { XM, EXx }, 0 },
11116   },
11117   {
11118     /* VEX_W_0F3816_P_2  */
11119     { "vpermps",        { XM, Vex, EXx }, 0 },
11120   },
11121   {
11122     /* VEX_W_0F3817_P_2 */
11123     { "vptest",         { XM, EXx }, 0 },
11124   },
11125   {
11126     /* VEX_W_0F3818_P_2 */
11127     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11128   },
11129   {
11130     /* VEX_W_0F3819_P_2 */
11131     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11132   },
11133   {
11134     /* VEX_W_0F381A_P_2_M_0 */
11135     { "vbroadcastf128", { XM, Mxmm }, 0 },
11136   },
11137   {
11138     /* VEX_W_0F381C_P_2 */
11139     { "vpabsb",         { XM, EXx }, 0 },
11140   },
11141   {
11142     /* VEX_W_0F381D_P_2 */
11143     { "vpabsw",         { XM, EXx }, 0 },
11144   },
11145   {
11146     /* VEX_W_0F381E_P_2 */
11147     { "vpabsd",         { XM, EXx }, 0 },
11148   },
11149   {
11150     /* VEX_W_0F3820_P_2 */
11151     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11152   },
11153   {
11154     /* VEX_W_0F3821_P_2 */
11155     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11156   },
11157   {
11158     /* VEX_W_0F3822_P_2 */
11159     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11160   },
11161   {
11162     /* VEX_W_0F3823_P_2 */
11163     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11164   },
11165   {
11166     /* VEX_W_0F3824_P_2 */
11167     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11168   },
11169   {
11170     /* VEX_W_0F3825_P_2 */
11171     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11172   },
11173   {
11174     /* VEX_W_0F3828_P_2 */
11175     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11176   },
11177   {
11178     /* VEX_W_0F3829_P_2 */
11179     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11180   },
11181   {
11182     /* VEX_W_0F382A_P_2_M_0 */
11183     { "vmovntdqa",      { XM, Mx }, 0 },
11184   },
11185   {
11186     /* VEX_W_0F382B_P_2 */
11187     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11188   },
11189   {
11190     /* VEX_W_0F382C_P_2_M_0 */
11191     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11192   },
11193   {
11194     /* VEX_W_0F382D_P_2_M_0 */
11195     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11196   },
11197   {
11198     /* VEX_W_0F382E_P_2_M_0 */
11199     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11200   },
11201   {
11202     /* VEX_W_0F382F_P_2_M_0 */
11203     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11204   },
11205   {
11206     /* VEX_W_0F3830_P_2 */
11207     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11208   },
11209   {
11210     /* VEX_W_0F3831_P_2 */
11211     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11212   },
11213   {
11214     /* VEX_W_0F3832_P_2 */
11215     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11216   },
11217   {
11218     /* VEX_W_0F3833_P_2 */
11219     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11220   },
11221   {
11222     /* VEX_W_0F3834_P_2 */
11223     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11224   },
11225   {
11226     /* VEX_W_0F3835_P_2 */
11227     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11228   },
11229   {
11230     /* VEX_W_0F3836_P_2  */
11231     { "vpermd",         { XM, Vex, EXx }, 0 },
11232   },
11233   {
11234     /* VEX_W_0F3837_P_2 */
11235     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11236   },
11237   {
11238     /* VEX_W_0F3838_P_2 */
11239     { "vpminsb",        { XM, Vex, EXx }, 0 },
11240   },
11241   {
11242     /* VEX_W_0F3839_P_2 */
11243     { "vpminsd",        { XM, Vex, EXx }, 0 },
11244   },
11245   {
11246     /* VEX_W_0F383A_P_2 */
11247     { "vpminuw",        { XM, Vex, EXx }, 0 },
11248   },
11249   {
11250     /* VEX_W_0F383B_P_2 */
11251     { "vpminud",        { XM, Vex, EXx }, 0 },
11252   },
11253   {
11254     /* VEX_W_0F383C_P_2 */
11255     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11256   },
11257   {
11258     /* VEX_W_0F383D_P_2 */
11259     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11260   },
11261   {
11262     /* VEX_W_0F383E_P_2 */
11263     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11264   },
11265   {
11266     /* VEX_W_0F383F_P_2 */
11267     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11268   },
11269   {
11270     /* VEX_W_0F3840_P_2 */
11271     { "vpmulld",        { XM, Vex, EXx }, 0 },
11272   },
11273   {
11274     /* VEX_W_0F3841_P_2 */
11275     { "vphminposuw",    { XM, EXx }, 0 },
11276   },
11277   {
11278     /* VEX_W_0F3846_P_2 */
11279     { "vpsravd",        { XM, Vex, EXx }, 0 },
11280   },
11281   {
11282     /* VEX_W_0F3858_P_2 */
11283     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11284   },
11285   {
11286     /* VEX_W_0F3859_P_2 */
11287     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11288   },
11289   {
11290     /* VEX_W_0F385A_P_2_M_0 */
11291     { "vbroadcasti128", { XM, Mxmm }, 0 },
11292   },
11293   {
11294     /* VEX_W_0F3878_P_2 */
11295     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11296   },
11297   {
11298     /* VEX_W_0F3879_P_2 */
11299     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11300   },
11301   {
11302     /* VEX_W_0F38CF_P_2 */
11303     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
11304   },
11305   {
11306     /* VEX_W_0F38DB_P_2 */
11307     { "vaesimc",        { XM, EXx }, 0 },
11308   },
11309   {
11310     /* VEX_W_0F3A00_P_2 */
11311     { Bad_Opcode },
11312     { "vpermq",         { XM, EXx, Ib }, 0 },
11313   },
11314   {
11315     /* VEX_W_0F3A01_P_2 */
11316     { Bad_Opcode },
11317     { "vpermpd",        { XM, EXx, Ib }, 0 },
11318   },
11319   {
11320     /* VEX_W_0F3A02_P_2 */
11321     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11322   },
11323   {
11324     /* VEX_W_0F3A04_P_2 */
11325     { "vpermilps",      { XM, EXx, Ib }, 0 },
11326   },
11327   {
11328     /* VEX_W_0F3A05_P_2 */
11329     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11330   },
11331   {
11332     /* VEX_W_0F3A06_P_2 */
11333     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11334   },
11335   {
11336     /* VEX_W_0F3A08_P_2 */
11337     { "vroundps",       { XM, EXx, Ib }, 0 },
11338   },
11339   {
11340     /* VEX_W_0F3A09_P_2 */
11341     { "vroundpd",       { XM, EXx, Ib }, 0 },
11342   },
11343   {
11344     /* VEX_W_0F3A0A_P_2 */
11345     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11346   },
11347   {
11348     /* VEX_W_0F3A0B_P_2 */
11349     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11350   },
11351   {
11352     /* VEX_W_0F3A0C_P_2 */
11353     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11354   },
11355   {
11356     /* VEX_W_0F3A0D_P_2 */
11357     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11358   },
11359   {
11360     /* VEX_W_0F3A0E_P_2 */
11361     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11362   },
11363   {
11364     /* VEX_W_0F3A0F_P_2 */
11365     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11366   },
11367   {
11368     /* VEX_W_0F3A14_P_2 */
11369     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11370   },
11371   {
11372     /* VEX_W_0F3A15_P_2 */
11373     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11374   },
11375   {
11376     /* VEX_W_0F3A18_P_2 */
11377     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11378   },
11379   {
11380     /* VEX_W_0F3A19_P_2 */
11381     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11382   },
11383   {
11384     /* VEX_W_0F3A20_P_2 */
11385     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11386   },
11387   {
11388     /* VEX_W_0F3A21_P_2 */
11389     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11390   },
11391   {
11392     /* VEX_W_0F3A30_P_2_LEN_0 */
11393     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11394     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11395   },
11396   {
11397     /* VEX_W_0F3A31_P_2_LEN_0 */
11398     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11399     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11400   },
11401   {
11402     /* VEX_W_0F3A32_P_2_LEN_0 */
11403     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11404     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11405   },
11406   {
11407     /* VEX_W_0F3A33_P_2_LEN_0 */
11408     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11409     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11410   },
11411   {
11412     /* VEX_W_0F3A38_P_2 */
11413     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11414   },
11415   {
11416     /* VEX_W_0F3A39_P_2 */
11417     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11418   },
11419   {
11420     /* VEX_W_0F3A40_P_2 */
11421     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11422   },
11423   {
11424     /* VEX_W_0F3A41_P_2 */
11425     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11426   },
11427   {
11428     /* VEX_W_0F3A42_P_2 */
11429     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11430   },
11431   {
11432     /* VEX_W_0F3A44_P_2 */
11433     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11434   },
11435   {
11436     /* VEX_W_0F3A46_P_2 */
11437     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11438   },
11439   {
11440     /* VEX_W_0F3A48_P_2 */
11441     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11442     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11443   },
11444   {
11445     /* VEX_W_0F3A49_P_2 */
11446     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11447     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11448   },
11449   {
11450     /* VEX_W_0F3A4A_P_2 */
11451     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11452   },
11453   {
11454     /* VEX_W_0F3A4B_P_2 */
11455     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11456   },
11457   {
11458     /* VEX_W_0F3A4C_P_2 */
11459     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11460   },
11461   {
11462     /* VEX_W_0F3A62_P_2 */
11463     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11464   },
11465   {
11466     /* VEX_W_0F3A63_P_2 */
11467     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11468   },
11469   {
11470     /* VEX_W_0F3ACE_P_2 */
11471     { Bad_Opcode },
11472     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
11473   },
11474   {
11475     /* VEX_W_0F3ACF_P_2 */
11476     { Bad_Opcode },
11477     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
11478   },
11479   {
11480     /* VEX_W_0F3ADF_P_2 */
11481     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11482   },
11483 #define NEED_VEX_W_TABLE
11484 #include "i386-dis-evex.h"
11485 #undef NEED_VEX_W_TABLE
11486 };
11487
11488 static const struct dis386 mod_table[][2] = {
11489   {
11490     /* MOD_8D */
11491     { "leaS",           { Gv, M }, 0 },
11492   },
11493   {
11494     /* MOD_C6_REG_7 */
11495     { Bad_Opcode },
11496     { RM_TABLE (RM_C6_REG_7) },
11497   },
11498   {
11499     /* MOD_C7_REG_7 */
11500     { Bad_Opcode },
11501     { RM_TABLE (RM_C7_REG_7) },
11502   },
11503   {
11504     /* MOD_FF_REG_3 */
11505     { "Jcall^", { indirEp }, 0 },
11506   },
11507   {
11508     /* MOD_FF_REG_5 */
11509     { "Jjmp^", { indirEp }, 0 },
11510   },
11511   {
11512     /* MOD_0F01_REG_0 */
11513     { X86_64_TABLE (X86_64_0F01_REG_0) },
11514     { RM_TABLE (RM_0F01_REG_0) },
11515   },
11516   {
11517     /* MOD_0F01_REG_1 */
11518     { X86_64_TABLE (X86_64_0F01_REG_1) },
11519     { RM_TABLE (RM_0F01_REG_1) },
11520   },
11521   {
11522     /* MOD_0F01_REG_2 */
11523     { X86_64_TABLE (X86_64_0F01_REG_2) },
11524     { RM_TABLE (RM_0F01_REG_2) },
11525   },
11526   {
11527     /* MOD_0F01_REG_3 */
11528     { X86_64_TABLE (X86_64_0F01_REG_3) },
11529     { RM_TABLE (RM_0F01_REG_3) },
11530   },
11531   {
11532     /* MOD_0F01_REG_5 */
11533     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11534     { RM_TABLE (RM_0F01_REG_5) },
11535   },
11536   {
11537     /* MOD_0F01_REG_7 */
11538     { "invlpg",         { Mb }, 0 },
11539     { RM_TABLE (RM_0F01_REG_7) },
11540   },
11541   {
11542     /* MOD_0F12_PREFIX_0 */
11543     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11544     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11545   },
11546   {
11547     /* MOD_0F13 */
11548     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11549   },
11550   {
11551     /* MOD_0F16_PREFIX_0 */
11552     { "movhps",         { XM, EXq }, 0 },
11553     { "movlhps",        { XM, EXq }, 0 },
11554   },
11555   {
11556     /* MOD_0F17 */
11557     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11558   },
11559   {
11560     /* MOD_0F18_REG_0 */
11561     { "prefetchnta",    { Mb }, 0 },
11562   },
11563   {
11564     /* MOD_0F18_REG_1 */
11565     { "prefetcht0",     { Mb }, 0 },
11566   },
11567   {
11568     /* MOD_0F18_REG_2 */
11569     { "prefetcht1",     { Mb }, 0 },
11570   },
11571   {
11572     /* MOD_0F18_REG_3 */
11573     { "prefetcht2",     { Mb }, 0 },
11574   },
11575   {
11576     /* MOD_0F18_REG_4 */
11577     { "nop/reserved",   { Mb }, 0 },
11578   },
11579   {
11580     /* MOD_0F18_REG_5 */
11581     { "nop/reserved",   { Mb }, 0 },
11582   },
11583   {
11584     /* MOD_0F18_REG_6 */
11585     { "nop/reserved",   { Mb }, 0 },
11586   },
11587   {
11588     /* MOD_0F18_REG_7 */
11589     { "nop/reserved",   { Mb }, 0 },
11590   },
11591   {
11592     /* MOD_0F1A_PREFIX_0 */
11593     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11594     { "nopQ",           { Ev }, 0 },
11595   },
11596   {
11597     /* MOD_0F1B_PREFIX_0 */
11598     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11599     { "nopQ",           { Ev }, 0 },
11600   },
11601   {
11602     /* MOD_0F1B_PREFIX_1 */
11603     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11604     { "nopQ",           { Ev }, 0 },
11605   },
11606   {
11607     /* MOD_0F1E_PREFIX_1 */
11608     { "nopQ",           { Ev }, 0 },
11609     { REG_TABLE (REG_0F1E_MOD_3) },
11610   },
11611   {
11612     /* MOD_0F24 */
11613     { Bad_Opcode },
11614     { "movL",           { Rd, Td }, 0 },
11615   },
11616   {
11617     /* MOD_0F26 */
11618     { Bad_Opcode },
11619     { "movL",           { Td, Rd }, 0 },
11620   },
11621   {
11622     /* MOD_0F2B_PREFIX_0 */
11623     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11624   },
11625   {
11626     /* MOD_0F2B_PREFIX_1 */
11627     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11628   },
11629   {
11630     /* MOD_0F2B_PREFIX_2 */
11631     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11632   },
11633   {
11634     /* MOD_0F2B_PREFIX_3 */
11635     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11636   },
11637   {
11638     /* MOD_0F51 */
11639     { Bad_Opcode },
11640     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11641   },
11642   {
11643     /* MOD_0F71_REG_2 */
11644     { Bad_Opcode },
11645     { "psrlw",          { MS, Ib }, 0 },
11646   },
11647   {
11648     /* MOD_0F71_REG_4 */
11649     { Bad_Opcode },
11650     { "psraw",          { MS, Ib }, 0 },
11651   },
11652   {
11653     /* MOD_0F71_REG_6 */
11654     { Bad_Opcode },
11655     { "psllw",          { MS, Ib }, 0 },
11656   },
11657   {
11658     /* MOD_0F72_REG_2 */
11659     { Bad_Opcode },
11660     { "psrld",          { MS, Ib }, 0 },
11661   },
11662   {
11663     /* MOD_0F72_REG_4 */
11664     { Bad_Opcode },
11665     { "psrad",          { MS, Ib }, 0 },
11666   },
11667   {
11668     /* MOD_0F72_REG_6 */
11669     { Bad_Opcode },
11670     { "pslld",          { MS, Ib }, 0 },
11671   },
11672   {
11673     /* MOD_0F73_REG_2 */
11674     { Bad_Opcode },
11675     { "psrlq",          { MS, Ib }, 0 },
11676   },
11677   {
11678     /* MOD_0F73_REG_3 */
11679     { Bad_Opcode },
11680     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11681   },
11682   {
11683     /* MOD_0F73_REG_6 */
11684     { Bad_Opcode },
11685     { "psllq",          { MS, Ib }, 0 },
11686   },
11687   {
11688     /* MOD_0F73_REG_7 */
11689     { Bad_Opcode },
11690     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11691   },
11692   {
11693     /* MOD_0FAE_REG_0 */
11694     { "fxsave",         { FXSAVE }, 0 },
11695     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11696   },
11697   {
11698     /* MOD_0FAE_REG_1 */
11699     { "fxrstor",        { FXSAVE }, 0 },
11700     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11701   },
11702   {
11703     /* MOD_0FAE_REG_2 */
11704     { "ldmxcsr",        { Md }, 0 },
11705     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11706   },
11707   {
11708     /* MOD_0FAE_REG_3 */
11709     { "stmxcsr",        { Md }, 0 },
11710     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11711   },
11712   {
11713     /* MOD_0FAE_REG_4 */
11714     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11715     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11716   },
11717   {
11718     /* MOD_0FAE_REG_5 */
11719     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11720     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11721   },
11722   {
11723     /* MOD_0FAE_REG_6 */
11724     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11725     { RM_TABLE (RM_0FAE_REG_6) },
11726   },
11727   {
11728     /* MOD_0FAE_REG_7 */
11729     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11730     { RM_TABLE (RM_0FAE_REG_7) },
11731   },
11732   {
11733     /* MOD_0FB2 */
11734     { "lssS",           { Gv, Mp }, 0 },
11735   },
11736   {
11737     /* MOD_0FB4 */
11738     { "lfsS",           { Gv, Mp }, 0 },
11739   },
11740   {
11741     /* MOD_0FB5 */
11742     { "lgsS",           { Gv, Mp }, 0 },
11743   },
11744   {
11745     /* MOD_0FC3 */
11746     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11747   },
11748   {
11749     /* MOD_0FC7_REG_3 */
11750     { "xrstors",        { FXSAVE }, 0 },
11751   },
11752   {
11753     /* MOD_0FC7_REG_4 */
11754     { "xsavec",         { FXSAVE }, 0 },
11755   },
11756   {
11757     /* MOD_0FC7_REG_5 */
11758     { "xsaves",         { FXSAVE }, 0 },
11759   },
11760   {
11761     /* MOD_0FC7_REG_6 */
11762     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11763     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11764   },
11765   {
11766     /* MOD_0FC7_REG_7 */
11767     { "vmptrst",        { Mq }, 0 },
11768     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11769   },
11770   {
11771     /* MOD_0FD7 */
11772     { Bad_Opcode },
11773     { "pmovmskb",       { Gdq, MS }, 0 },
11774   },
11775   {
11776     /* MOD_0FE7_PREFIX_2 */
11777     { "movntdq",        { Mx, XM }, 0 },
11778   },
11779   {
11780     /* MOD_0FF0_PREFIX_3 */
11781     { "lddqu",          { XM, M }, 0 },
11782   },
11783   {
11784     /* MOD_0F382A_PREFIX_2 */
11785     { "movntdqa",       { XM, Mx }, 0 },
11786   },
11787   {
11788     /* MOD_0F38F5_PREFIX_2 */
11789     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11790   },
11791   {
11792     /* MOD_0F38F6_PREFIX_0 */
11793     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11794   },
11795   {
11796     /* MOD_62_32BIT */
11797     { "bound{S|}",      { Gv, Ma }, 0 },
11798     { EVEX_TABLE (EVEX_0F) },
11799   },
11800   {
11801     /* MOD_C4_32BIT */
11802     { "lesS",           { Gv, Mp }, 0 },
11803     { VEX_C4_TABLE (VEX_0F) },
11804   },
11805   {
11806     /* MOD_C5_32BIT */
11807     { "ldsS",           { Gv, Mp }, 0 },
11808     { VEX_C5_TABLE (VEX_0F) },
11809   },
11810   {
11811     /* MOD_VEX_0F12_PREFIX_0 */
11812     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11813     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11814   },
11815   {
11816     /* MOD_VEX_0F13 */
11817     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11818   },
11819   {
11820     /* MOD_VEX_0F16_PREFIX_0 */
11821     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11822     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11823   },
11824   {
11825     /* MOD_VEX_0F17 */
11826     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11827   },
11828   {
11829     /* MOD_VEX_0F2B */
11830     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11831   },
11832   {
11833     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11834     { Bad_Opcode },
11835     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11836   },
11837   {
11838     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11839     { Bad_Opcode },
11840     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11841   },
11842   {
11843     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11844     { Bad_Opcode },
11845     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11846   },
11847   {
11848     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11849     { Bad_Opcode },
11850     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11851   },
11852   {
11853     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11854     { Bad_Opcode },
11855     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11856   },
11857   {
11858     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11859     { Bad_Opcode },
11860     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11861   },
11862   {
11863     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11864     { Bad_Opcode },
11865     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11866   },
11867   {
11868     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11869     { Bad_Opcode },
11870     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11871   },
11872   {
11873     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11874     { Bad_Opcode },
11875     { "knotw",          { MaskG, MaskR }, 0 },
11876   },
11877   {
11878     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11879     { Bad_Opcode },
11880     { "knotq",          { MaskG, MaskR }, 0 },
11881   },
11882   {
11883     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11884     { Bad_Opcode },
11885     { "knotb",          { MaskG, MaskR }, 0 },
11886   },
11887   {
11888     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11889     { Bad_Opcode },
11890     { "knotd",          { MaskG, MaskR }, 0 },
11891   },
11892   {
11893     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11894     { Bad_Opcode },
11895     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11896   },
11897   {
11898     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11899     { Bad_Opcode },
11900     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11901   },
11902   {
11903     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11904     { Bad_Opcode },
11905     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11906   },
11907   {
11908     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11909     { Bad_Opcode },
11910     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11911   },
11912  {
11913     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11914     { Bad_Opcode },
11915     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11916   },
11917   {
11918     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11919     { Bad_Opcode },
11920     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11921   },
11922   {
11923     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11924     { Bad_Opcode },
11925     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11926   },
11927   {
11928     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11929     { Bad_Opcode },
11930     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11931   },
11932   {
11933     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11934     { Bad_Opcode },
11935     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11936   },
11937   {
11938     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11939     { Bad_Opcode },
11940     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11941   },
11942   {
11943     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11944     { Bad_Opcode },
11945     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11946   },
11947   {
11948     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11949     { Bad_Opcode },
11950     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11951   },
11952   {
11953     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11954     { Bad_Opcode },
11955     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11956   },
11957   {
11958     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11959     { Bad_Opcode },
11960     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11961   },
11962   {
11963     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11964     { Bad_Opcode },
11965     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11966   },
11967   {
11968     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11969     { Bad_Opcode },
11970     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11971   },
11972   {
11973     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11974     { Bad_Opcode },
11975     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11976   },
11977   {
11978     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11979     { Bad_Opcode },
11980     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11981   },
11982   {
11983     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11984     { Bad_Opcode },
11985     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11986   },
11987   {
11988     /* MOD_VEX_0F50 */
11989     { Bad_Opcode },
11990     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11991   },
11992   {
11993     /* MOD_VEX_0F71_REG_2 */
11994     { Bad_Opcode },
11995     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11996   },
11997   {
11998     /* MOD_VEX_0F71_REG_4 */
11999     { Bad_Opcode },
12000     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12001   },
12002   {
12003     /* MOD_VEX_0F71_REG_6 */
12004     { Bad_Opcode },
12005     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12006   },
12007   {
12008     /* MOD_VEX_0F72_REG_2 */
12009     { Bad_Opcode },
12010     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12011   },
12012   {
12013     /* MOD_VEX_0F72_REG_4 */
12014     { Bad_Opcode },
12015     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12016   },
12017   {
12018     /* MOD_VEX_0F72_REG_6 */
12019     { Bad_Opcode },
12020     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12021   },
12022   {
12023     /* MOD_VEX_0F73_REG_2 */
12024     { Bad_Opcode },
12025     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12026   },
12027   {
12028     /* MOD_VEX_0F73_REG_3 */
12029     { Bad_Opcode },
12030     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12031   },
12032   {
12033     /* MOD_VEX_0F73_REG_6 */
12034     { Bad_Opcode },
12035     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12036   },
12037   {
12038     /* MOD_VEX_0F73_REG_7 */
12039     { Bad_Opcode },
12040     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12041   },
12042   {
12043     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12044     { "kmovw",          { Ew, MaskG }, 0 },
12045     { Bad_Opcode },
12046   },
12047   {
12048     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12049     { "kmovq",          { Eq, MaskG }, 0 },
12050     { Bad_Opcode },
12051   },
12052   {
12053     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12054     { "kmovb",          { Eb, MaskG }, 0 },
12055     { Bad_Opcode },
12056   },
12057   {
12058     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12059     { "kmovd",          { Ed, MaskG }, 0 },
12060     { Bad_Opcode },
12061   },
12062   {
12063     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12064     { Bad_Opcode },
12065     { "kmovw",          { MaskG, Rdq }, 0 },
12066   },
12067   {
12068     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12069     { Bad_Opcode },
12070     { "kmovb",          { MaskG, Rdq }, 0 },
12071   },
12072   {
12073     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12074     { Bad_Opcode },
12075     { "kmovd",          { MaskG, Rdq }, 0 },
12076   },
12077   {
12078     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12079     { Bad_Opcode },
12080     { "kmovq",          { MaskG, Rdq }, 0 },
12081   },
12082   {
12083     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12084     { Bad_Opcode },
12085     { "kmovw",          { Gdq, MaskR }, 0 },
12086   },
12087   {
12088     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12089     { Bad_Opcode },
12090     { "kmovb",          { Gdq, MaskR }, 0 },
12091   },
12092   {
12093     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12094     { Bad_Opcode },
12095     { "kmovd",          { Gdq, MaskR }, 0 },
12096   },
12097   {
12098     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12099     { Bad_Opcode },
12100     { "kmovq",          { Gdq, MaskR }, 0 },
12101   },
12102   {
12103     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12104     { Bad_Opcode },
12105     { "kortestw", { MaskG, MaskR }, 0 },
12106   },
12107   {
12108     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12109     { Bad_Opcode },
12110     { "kortestq", { MaskG, MaskR }, 0 },
12111   },
12112   {
12113     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12114     { Bad_Opcode },
12115     { "kortestb", { MaskG, MaskR }, 0 },
12116   },
12117   {
12118     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12119     { Bad_Opcode },
12120     { "kortestd", { MaskG, MaskR }, 0 },
12121   },
12122   {
12123     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12124     { Bad_Opcode },
12125     { "ktestw", { MaskG, MaskR }, 0 },
12126   },
12127   {
12128     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12129     { Bad_Opcode },
12130     { "ktestq", { MaskG, MaskR }, 0 },
12131   },
12132   {
12133     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12134     { Bad_Opcode },
12135     { "ktestb", { MaskG, MaskR }, 0 },
12136   },
12137   {
12138     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12139     { Bad_Opcode },
12140     { "ktestd", { MaskG, MaskR }, 0 },
12141   },
12142   {
12143     /* MOD_VEX_0FAE_REG_2 */
12144     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12145   },
12146   {
12147     /* MOD_VEX_0FAE_REG_3 */
12148     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12149   },
12150   {
12151     /* MOD_VEX_0FD7_PREFIX_2 */
12152     { Bad_Opcode },
12153     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12154   },
12155   {
12156     /* MOD_VEX_0FE7_PREFIX_2 */
12157     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12158   },
12159   {
12160     /* MOD_VEX_0FF0_PREFIX_3 */
12161     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12162   },
12163   {
12164     /* MOD_VEX_0F381A_PREFIX_2 */
12165     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12166   },
12167   {
12168     /* MOD_VEX_0F382A_PREFIX_2 */
12169     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12170   },
12171   {
12172     /* MOD_VEX_0F382C_PREFIX_2 */
12173     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12174   },
12175   {
12176     /* MOD_VEX_0F382D_PREFIX_2 */
12177     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12178   },
12179   {
12180     /* MOD_VEX_0F382E_PREFIX_2 */
12181     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12182   },
12183   {
12184     /* MOD_VEX_0F382F_PREFIX_2 */
12185     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12186   },
12187   {
12188     /* MOD_VEX_0F385A_PREFIX_2 */
12189     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12190   },
12191   {
12192     /* MOD_VEX_0F388C_PREFIX_2 */
12193     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12194   },
12195   {
12196     /* MOD_VEX_0F388E_PREFIX_2 */
12197     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12198   },
12199   {
12200     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12201     { Bad_Opcode },
12202     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12203   },
12204   {
12205     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12206     { Bad_Opcode },
12207     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12208   },
12209   {
12210     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12211     { Bad_Opcode },
12212     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12213   },
12214   {
12215     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12216     { Bad_Opcode },
12217     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12218   },
12219   {
12220     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12221     { Bad_Opcode },
12222     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12223   },
12224   {
12225     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12226     { Bad_Opcode },
12227     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12228   },
12229   {
12230     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12231     { Bad_Opcode },
12232     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12233   },
12234   {
12235     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12236     { Bad_Opcode },
12237     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12238   },
12239 #define NEED_MOD_TABLE
12240 #include "i386-dis-evex.h"
12241 #undef NEED_MOD_TABLE
12242 };
12243
12244 static const struct dis386 rm_table[][8] = {
12245   {
12246     /* RM_C6_REG_7 */
12247     { "xabort",         { Skip_MODRM, Ib }, 0 },
12248   },
12249   {
12250     /* RM_C7_REG_7 */
12251     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12252   },
12253   {
12254     /* RM_0F01_REG_0 */
12255     { Bad_Opcode },
12256     { "vmcall",         { Skip_MODRM }, 0 },
12257     { "vmlaunch",       { Skip_MODRM }, 0 },
12258     { "vmresume",       { Skip_MODRM }, 0 },
12259     { "vmxoff",         { Skip_MODRM }, 0 },
12260   },
12261   {
12262     /* RM_0F01_REG_1 */
12263     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12264     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12265     { "clac",           { Skip_MODRM }, 0 },
12266     { "stac",           { Skip_MODRM }, 0 },
12267     { Bad_Opcode },
12268     { Bad_Opcode },
12269     { Bad_Opcode },
12270     { "encls",          { Skip_MODRM }, 0 },
12271   },
12272   {
12273     /* RM_0F01_REG_2 */
12274     { "xgetbv",         { Skip_MODRM }, 0 },
12275     { "xsetbv",         { Skip_MODRM }, 0 },
12276     { Bad_Opcode },
12277     { Bad_Opcode },
12278     { "vmfunc",         { Skip_MODRM }, 0 },
12279     { "xend",           { Skip_MODRM }, 0 },
12280     { "xtest",          { Skip_MODRM }, 0 },
12281     { "enclu",          { Skip_MODRM }, 0 },
12282   },
12283   {
12284     /* RM_0F01_REG_3 */
12285     { "vmrun",          { Skip_MODRM }, 0 },
12286     { "vmmcall",        { Skip_MODRM }, 0 },
12287     { "vmload",         { Skip_MODRM }, 0 },
12288     { "vmsave",         { Skip_MODRM }, 0 },
12289     { "stgi",           { Skip_MODRM }, 0 },
12290     { "clgi",           { Skip_MODRM }, 0 },
12291     { "skinit",         { Skip_MODRM }, 0 },
12292     { "invlpga",        { Skip_MODRM }, 0 },
12293   },
12294   {
12295     /* RM_0F01_REG_5 */
12296     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12297     { Bad_Opcode },
12298     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12299     { Bad_Opcode },
12300     { Bad_Opcode },
12301     { Bad_Opcode },
12302     { "rdpkru",         { Skip_MODRM }, 0 },
12303     { "wrpkru",         { Skip_MODRM }, 0 },
12304   },
12305   {
12306     /* RM_0F01_REG_7 */
12307     { "swapgs",         { Skip_MODRM }, 0  },
12308     { "rdtscp",         { Skip_MODRM }, 0  },
12309     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12310     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12311     { "clzero",         { Skip_MODRM }, 0  },
12312   },
12313   {
12314     /* RM_0F1E_MOD_3_REG_7 */
12315     { "nopQ",           { Ev }, 0 },
12316     { "nopQ",           { Ev }, 0 },
12317     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
12318     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
12319     { "nopQ",           { Ev }, 0 },
12320     { "nopQ",           { Ev }, 0 },
12321     { "nopQ",           { Ev }, 0 },
12322     { "nopQ",           { Ev }, 0 },
12323   },
12324   {
12325     /* RM_0FAE_REG_6 */
12326     { "mfence",         { Skip_MODRM }, 0 },
12327   },
12328   {
12329     /* RM_0FAE_REG_7 */
12330     { "sfence",         { Skip_MODRM }, 0 },
12331
12332   },
12333 };
12334
12335 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12336
12337 /* We use the high bit to indicate different name for the same
12338    prefix.  */
12339 #define REP_PREFIX      (0xf3 | 0x100)
12340 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12341 #define XRELEASE_PREFIX (0xf3 | 0x400)
12342 #define BND_PREFIX      (0xf2 | 0x400)
12343 #define NOTRACK_PREFIX  (0x3e | 0x100)
12344
12345 static int
12346 ckprefix (void)
12347 {
12348   int newrex, i, length;
12349   rex = 0;
12350   rex_ignored = 0;
12351   prefixes = 0;
12352   used_prefixes = 0;
12353   rex_used = 0;
12354   last_lock_prefix = -1;
12355   last_repz_prefix = -1;
12356   last_repnz_prefix = -1;
12357   last_data_prefix = -1;
12358   last_addr_prefix = -1;
12359   last_rex_prefix = -1;
12360   last_seg_prefix = -1;
12361   fwait_prefix = -1;
12362   active_seg_prefix = 0;
12363   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12364     all_prefixes[i] = 0;
12365   i = 0;
12366   length = 0;
12367   /* The maximum instruction length is 15bytes.  */
12368   while (length < MAX_CODE_LENGTH - 1)
12369     {
12370       FETCH_DATA (the_info, codep + 1);
12371       newrex = 0;
12372       switch (*codep)
12373         {
12374         /* REX prefixes family.  */
12375         case 0x40:
12376         case 0x41:
12377         case 0x42:
12378         case 0x43:
12379         case 0x44:
12380         case 0x45:
12381         case 0x46:
12382         case 0x47:
12383         case 0x48:
12384         case 0x49:
12385         case 0x4a:
12386         case 0x4b:
12387         case 0x4c:
12388         case 0x4d:
12389         case 0x4e:
12390         case 0x4f:
12391           if (address_mode == mode_64bit)
12392             newrex = *codep;
12393           else
12394             return 1;
12395           last_rex_prefix = i;
12396           break;
12397         case 0xf3:
12398           prefixes |= PREFIX_REPZ;
12399           last_repz_prefix = i;
12400           break;
12401         case 0xf2:
12402           prefixes |= PREFIX_REPNZ;
12403           last_repnz_prefix = i;
12404           break;
12405         case 0xf0:
12406           prefixes |= PREFIX_LOCK;
12407           last_lock_prefix = i;
12408           break;
12409         case 0x2e:
12410           prefixes |= PREFIX_CS;
12411           last_seg_prefix = i;
12412           active_seg_prefix = PREFIX_CS;
12413           break;
12414         case 0x36:
12415           prefixes |= PREFIX_SS;
12416           last_seg_prefix = i;
12417           active_seg_prefix = PREFIX_SS;
12418           break;
12419         case 0x3e:
12420           prefixes |= PREFIX_DS;
12421           last_seg_prefix = i;
12422           active_seg_prefix = PREFIX_DS;
12423           break;
12424         case 0x26:
12425           prefixes |= PREFIX_ES;
12426           last_seg_prefix = i;
12427           active_seg_prefix = PREFIX_ES;
12428           break;
12429         case 0x64:
12430           prefixes |= PREFIX_FS;
12431           last_seg_prefix = i;
12432           active_seg_prefix = PREFIX_FS;
12433           break;
12434         case 0x65:
12435           prefixes |= PREFIX_GS;
12436           last_seg_prefix = i;
12437           active_seg_prefix = PREFIX_GS;
12438           break;
12439         case 0x66:
12440           prefixes |= PREFIX_DATA;
12441           last_data_prefix = i;
12442           break;
12443         case 0x67:
12444           prefixes |= PREFIX_ADDR;
12445           last_addr_prefix = i;
12446           break;
12447         case FWAIT_OPCODE:
12448           /* fwait is really an instruction.  If there are prefixes
12449              before the fwait, they belong to the fwait, *not* to the
12450              following instruction.  */
12451           fwait_prefix = i;
12452           if (prefixes || rex)
12453             {
12454               prefixes |= PREFIX_FWAIT;
12455               codep++;
12456               /* This ensures that the previous REX prefixes are noticed
12457                  as unused prefixes, as in the return case below.  */
12458               rex_used = rex;
12459               return 1;
12460             }
12461           prefixes = PREFIX_FWAIT;
12462           break;
12463         default:
12464           return 1;
12465         }
12466       /* Rex is ignored when followed by another prefix.  */
12467       if (rex)
12468         {
12469           rex_used = rex;
12470           return 1;
12471         }
12472       if (*codep != FWAIT_OPCODE)
12473         all_prefixes[i++] = *codep;
12474       rex = newrex;
12475       codep++;
12476       length++;
12477     }
12478   return 0;
12479 }
12480
12481 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12482    prefix byte.  */
12483
12484 static const char *
12485 prefix_name (int pref, int sizeflag)
12486 {
12487   static const char *rexes [16] =
12488     {
12489       "rex",            /* 0x40 */
12490       "rex.B",          /* 0x41 */
12491       "rex.X",          /* 0x42 */
12492       "rex.XB",         /* 0x43 */
12493       "rex.R",          /* 0x44 */
12494       "rex.RB",         /* 0x45 */
12495       "rex.RX",         /* 0x46 */
12496       "rex.RXB",        /* 0x47 */
12497       "rex.W",          /* 0x48 */
12498       "rex.WB",         /* 0x49 */
12499       "rex.WX",         /* 0x4a */
12500       "rex.WXB",        /* 0x4b */
12501       "rex.WR",         /* 0x4c */
12502       "rex.WRB",        /* 0x4d */
12503       "rex.WRX",        /* 0x4e */
12504       "rex.WRXB",       /* 0x4f */
12505     };
12506
12507   switch (pref)
12508     {
12509     /* REX prefixes family.  */
12510     case 0x40:
12511     case 0x41:
12512     case 0x42:
12513     case 0x43:
12514     case 0x44:
12515     case 0x45:
12516     case 0x46:
12517     case 0x47:
12518     case 0x48:
12519     case 0x49:
12520     case 0x4a:
12521     case 0x4b:
12522     case 0x4c:
12523     case 0x4d:
12524     case 0x4e:
12525     case 0x4f:
12526       return rexes [pref - 0x40];
12527     case 0xf3:
12528       return "repz";
12529     case 0xf2:
12530       return "repnz";
12531     case 0xf0:
12532       return "lock";
12533     case 0x2e:
12534       return "cs";
12535     case 0x36:
12536       return "ss";
12537     case 0x3e:
12538       return "ds";
12539     case 0x26:
12540       return "es";
12541     case 0x64:
12542       return "fs";
12543     case 0x65:
12544       return "gs";
12545     case 0x66:
12546       return (sizeflag & DFLAG) ? "data16" : "data32";
12547     case 0x67:
12548       if (address_mode == mode_64bit)
12549         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12550       else
12551         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12552     case FWAIT_OPCODE:
12553       return "fwait";
12554     case REP_PREFIX:
12555       return "rep";
12556     case XACQUIRE_PREFIX:
12557       return "xacquire";
12558     case XRELEASE_PREFIX:
12559       return "xrelease";
12560     case BND_PREFIX:
12561       return "bnd";
12562     case NOTRACK_PREFIX:
12563       return "notrack";
12564     default:
12565       return NULL;
12566     }
12567 }
12568
12569 static char op_out[MAX_OPERANDS][100];
12570 static int op_ad, op_index[MAX_OPERANDS];
12571 static int two_source_ops;
12572 static bfd_vma op_address[MAX_OPERANDS];
12573 static bfd_vma op_riprel[MAX_OPERANDS];
12574 static bfd_vma start_pc;
12575
12576 /*
12577  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12578  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12579  *   section of the "Virtual 8086 Mode" chapter.)
12580  * 'pc' should be the address of this instruction, it will
12581  *   be used to print the target address if this is a relative jump or call
12582  * The function returns the length of this instruction in bytes.
12583  */
12584
12585 static char intel_syntax;
12586 static char intel_mnemonic = !SYSV386_COMPAT;
12587 static char open_char;
12588 static char close_char;
12589 static char separator_char;
12590 static char scale_char;
12591
12592 enum x86_64_isa
12593 {
12594   amd64 = 0,
12595   intel64
12596 };
12597
12598 static enum x86_64_isa isa64;
12599
12600 /* Here for backwards compatibility.  When gdb stops using
12601    print_insn_i386_att and print_insn_i386_intel these functions can
12602    disappear, and print_insn_i386 be merged into print_insn.  */
12603 int
12604 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12605 {
12606   intel_syntax = 0;
12607
12608   return print_insn (pc, info);
12609 }
12610
12611 int
12612 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12613 {
12614   intel_syntax = 1;
12615
12616   return print_insn (pc, info);
12617 }
12618
12619 int
12620 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12621 {
12622   intel_syntax = -1;
12623
12624   return print_insn (pc, info);
12625 }
12626
12627 void
12628 print_i386_disassembler_options (FILE *stream)
12629 {
12630   fprintf (stream, _("\n\
12631 The following i386/x86-64 specific disassembler options are supported for use\n\
12632 with the -M switch (multiple options should be separated by commas):\n"));
12633
12634   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12635   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12636   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12637   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12638   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12639   fprintf (stream, _("  att-mnemonic\n"
12640                      "              Display instruction in AT&T mnemonic\n"));
12641   fprintf (stream, _("  intel-mnemonic\n"
12642                      "              Display instruction in Intel mnemonic\n"));
12643   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12644   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12645   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12646   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12647   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12648   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12649   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12650   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12651 }
12652
12653 /* Bad opcode.  */
12654 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12655
12656 /* Get a pointer to struct dis386 with a valid name.  */
12657
12658 static const struct dis386 *
12659 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12660 {
12661   int vindex, vex_table_index;
12662
12663   if (dp->name != NULL)
12664     return dp;
12665
12666   switch (dp->op[0].bytemode)
12667     {
12668     case USE_REG_TABLE:
12669       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12670       break;
12671
12672     case USE_MOD_TABLE:
12673       vindex = modrm.mod == 0x3 ? 1 : 0;
12674       dp = &mod_table[dp->op[1].bytemode][vindex];
12675       break;
12676
12677     case USE_RM_TABLE:
12678       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12679       break;
12680
12681     case USE_PREFIX_TABLE:
12682       if (need_vex)
12683         {
12684           /* The prefix in VEX is implicit.  */
12685           switch (vex.prefix)
12686             {
12687             case 0:
12688               vindex = 0;
12689               break;
12690             case REPE_PREFIX_OPCODE:
12691               vindex = 1;
12692               break;
12693             case DATA_PREFIX_OPCODE:
12694               vindex = 2;
12695               break;
12696             case REPNE_PREFIX_OPCODE:
12697               vindex = 3;
12698               break;
12699             default:
12700               abort ();
12701               break;
12702             }
12703         }
12704       else
12705         {
12706           int last_prefix = -1;
12707           int prefix = 0;
12708           vindex = 0;
12709           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12710              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12711              last one wins.  */
12712           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12713             {
12714               if (last_repz_prefix > last_repnz_prefix)
12715                 {
12716                   vindex = 1;
12717                   prefix = PREFIX_REPZ;
12718                   last_prefix = last_repz_prefix;
12719                 }
12720               else
12721                 {
12722                   vindex = 3;
12723                   prefix = PREFIX_REPNZ;
12724                   last_prefix = last_repnz_prefix;
12725                 }
12726
12727               /* Check if prefix should be ignored.  */
12728               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12729                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12730                    & prefix) != 0)
12731                 vindex = 0;
12732             }
12733
12734           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12735             {
12736               vindex = 2;
12737               prefix = PREFIX_DATA;
12738               last_prefix = last_data_prefix;
12739             }
12740
12741           if (vindex != 0)
12742             {
12743               used_prefixes |= prefix;
12744               all_prefixes[last_prefix] = 0;
12745             }
12746         }
12747       dp = &prefix_table[dp->op[1].bytemode][vindex];
12748       break;
12749
12750     case USE_X86_64_TABLE:
12751       vindex = address_mode == mode_64bit ? 1 : 0;
12752       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12753       break;
12754
12755     case USE_3BYTE_TABLE:
12756       FETCH_DATA (info, codep + 2);
12757       vindex = *codep++;
12758       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12759       end_codep = codep;
12760       modrm.mod = (*codep >> 6) & 3;
12761       modrm.reg = (*codep >> 3) & 7;
12762       modrm.rm = *codep & 7;
12763       break;
12764
12765     case USE_VEX_LEN_TABLE:
12766       if (!need_vex)
12767         abort ();
12768
12769       switch (vex.length)
12770         {
12771         case 128:
12772           vindex = 0;
12773           break;
12774         case 256:
12775           vindex = 1;
12776           break;
12777         default:
12778           abort ();
12779           break;
12780         }
12781
12782       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12783       break;
12784
12785     case USE_XOP_8F_TABLE:
12786       FETCH_DATA (info, codep + 3);
12787       /* All bits in the REX prefix are ignored.  */
12788       rex_ignored = rex;
12789       rex = ~(*codep >> 5) & 0x7;
12790
12791       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12792       switch ((*codep & 0x1f))
12793         {
12794         default:
12795           dp = &bad_opcode;
12796           return dp;
12797         case 0x8:
12798           vex_table_index = XOP_08;
12799           break;
12800         case 0x9:
12801           vex_table_index = XOP_09;
12802           break;
12803         case 0xa:
12804           vex_table_index = XOP_0A;
12805           break;
12806         }
12807       codep++;
12808       vex.w = *codep & 0x80;
12809       if (vex.w && address_mode == mode_64bit)
12810         rex |= REX_W;
12811
12812       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12813       if (address_mode != mode_64bit)
12814         {
12815           /* In 16/32-bit mode REX_B is silently ignored.  */
12816           rex &= ~REX_B;
12817           if (vex.register_specifier > 0x7)
12818             {
12819               dp = &bad_opcode;
12820               return dp;
12821             }
12822         }
12823
12824       vex.length = (*codep & 0x4) ? 256 : 128;
12825       switch ((*codep & 0x3))
12826         {
12827         case 0:
12828           vex.prefix = 0;
12829           break;
12830         case 1:
12831           vex.prefix = DATA_PREFIX_OPCODE;
12832           break;
12833         case 2:
12834           vex.prefix = REPE_PREFIX_OPCODE;
12835           break;
12836         case 3:
12837           vex.prefix = REPNE_PREFIX_OPCODE;
12838           break;
12839         }
12840       need_vex = 1;
12841       need_vex_reg = 1;
12842       codep++;
12843       vindex = *codep++;
12844       dp = &xop_table[vex_table_index][vindex];
12845
12846       end_codep = codep;
12847       FETCH_DATA (info, codep + 1);
12848       modrm.mod = (*codep >> 6) & 3;
12849       modrm.reg = (*codep >> 3) & 7;
12850       modrm.rm = *codep & 7;
12851       break;
12852
12853     case USE_VEX_C4_TABLE:
12854       /* VEX prefix.  */
12855       FETCH_DATA (info, codep + 3);
12856       /* All bits in the REX prefix are ignored.  */
12857       rex_ignored = rex;
12858       rex = ~(*codep >> 5) & 0x7;
12859       switch ((*codep & 0x1f))
12860         {
12861         default:
12862           dp = &bad_opcode;
12863           return dp;
12864         case 0x1:
12865           vex_table_index = VEX_0F;
12866           break;
12867         case 0x2:
12868           vex_table_index = VEX_0F38;
12869           break;
12870         case 0x3:
12871           vex_table_index = VEX_0F3A;
12872           break;
12873         }
12874       codep++;
12875       vex.w = *codep & 0x80;
12876       if (address_mode == mode_64bit)
12877         {
12878           if (vex.w)
12879             rex |= REX_W;
12880           vex.register_specifier = (~(*codep >> 3)) & 0xf;
12881         }
12882       else
12883         {
12884           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12885              is ignored, other REX bits are 0 and the highest bit in
12886              VEX.vvvv is also ignored.  */
12887           rex = 0;
12888           vex.register_specifier = (~(*codep >> 3)) & 0x7;
12889         }
12890       vex.length = (*codep & 0x4) ? 256 : 128;
12891       switch ((*codep & 0x3))
12892         {
12893         case 0:
12894           vex.prefix = 0;
12895           break;
12896         case 1:
12897           vex.prefix = DATA_PREFIX_OPCODE;
12898           break;
12899         case 2:
12900           vex.prefix = REPE_PREFIX_OPCODE;
12901           break;
12902         case 3:
12903           vex.prefix = REPNE_PREFIX_OPCODE;
12904           break;
12905         }
12906       need_vex = 1;
12907       need_vex_reg = 1;
12908       codep++;
12909       vindex = *codep++;
12910       dp = &vex_table[vex_table_index][vindex];
12911       end_codep = codep;
12912       /* There is no MODRM byte for VEX0F 77.  */
12913       if (vex_table_index != VEX_0F || vindex != 0x77)
12914         {
12915           FETCH_DATA (info, codep + 1);
12916           modrm.mod = (*codep >> 6) & 3;
12917           modrm.reg = (*codep >> 3) & 7;
12918           modrm.rm = *codep & 7;
12919         }
12920       break;
12921
12922     case USE_VEX_C5_TABLE:
12923       /* VEX prefix.  */
12924       FETCH_DATA (info, codep + 2);
12925       /* All bits in the REX prefix are ignored.  */
12926       rex_ignored = rex;
12927       rex = (*codep & 0x80) ? 0 : REX_R;
12928
12929       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12930          VEX.vvvv is 1.  */
12931       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12932       vex.w = 0;
12933       vex.length = (*codep & 0x4) ? 256 : 128;
12934       switch ((*codep & 0x3))
12935         {
12936         case 0:
12937           vex.prefix = 0;
12938           break;
12939         case 1:
12940           vex.prefix = DATA_PREFIX_OPCODE;
12941           break;
12942         case 2:
12943           vex.prefix = REPE_PREFIX_OPCODE;
12944           break;
12945         case 3:
12946           vex.prefix = REPNE_PREFIX_OPCODE;
12947           break;
12948         }
12949       need_vex = 1;
12950       need_vex_reg = 1;
12951       codep++;
12952       vindex = *codep++;
12953       dp = &vex_table[dp->op[1].bytemode][vindex];
12954       end_codep = codep;
12955       /* There is no MODRM byte for VEX 77.  */
12956       if (vindex != 0x77)
12957         {
12958           FETCH_DATA (info, codep + 1);
12959           modrm.mod = (*codep >> 6) & 3;
12960           modrm.reg = (*codep >> 3) & 7;
12961           modrm.rm = *codep & 7;
12962         }
12963       break;
12964
12965     case USE_VEX_W_TABLE:
12966       if (!need_vex)
12967         abort ();
12968
12969       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12970       break;
12971
12972     case USE_EVEX_TABLE:
12973       two_source_ops = 0;
12974       /* EVEX prefix.  */
12975       vex.evex = 1;
12976       FETCH_DATA (info, codep + 4);
12977       /* All bits in the REX prefix are ignored.  */
12978       rex_ignored = rex;
12979       /* The first byte after 0x62.  */
12980       rex = ~(*codep >> 5) & 0x7;
12981       vex.r = *codep & 0x10;
12982       switch ((*codep & 0xf))
12983         {
12984         default:
12985           return &bad_opcode;
12986         case 0x1:
12987           vex_table_index = EVEX_0F;
12988           break;
12989         case 0x2:
12990           vex_table_index = EVEX_0F38;
12991           break;
12992         case 0x3:
12993           vex_table_index = EVEX_0F3A;
12994           break;
12995         }
12996
12997       /* The second byte after 0x62.  */
12998       codep++;
12999       vex.w = *codep & 0x80;
13000       if (vex.w && address_mode == mode_64bit)
13001         rex |= REX_W;
13002
13003       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13004       if (address_mode != mode_64bit)
13005         {
13006           /* In 16/32-bit mode silently ignore following bits.  */
13007           rex &= ~REX_B;
13008           vex.r = 1;
13009           vex.v = 1;
13010           vex.register_specifier &= 0x7;
13011         }
13012
13013       /* The U bit.  */
13014       if (!(*codep & 0x4))
13015         return &bad_opcode;
13016
13017       switch ((*codep & 0x3))
13018         {
13019         case 0:
13020           vex.prefix = 0;
13021           break;
13022         case 1:
13023           vex.prefix = DATA_PREFIX_OPCODE;
13024           break;
13025         case 2:
13026           vex.prefix = REPE_PREFIX_OPCODE;
13027           break;
13028         case 3:
13029           vex.prefix = REPNE_PREFIX_OPCODE;
13030           break;
13031         }
13032
13033       /* The third byte after 0x62.  */
13034       codep++;
13035
13036       /* Remember the static rounding bits.  */
13037       vex.ll = (*codep >> 5) & 3;
13038       vex.b = (*codep & 0x10) != 0;
13039
13040       vex.v = *codep & 0x8;
13041       vex.mask_register_specifier = *codep & 0x7;
13042       vex.zeroing = *codep & 0x80;
13043
13044       need_vex = 1;
13045       need_vex_reg = 1;
13046       codep++;
13047       vindex = *codep++;
13048       dp = &evex_table[vex_table_index][vindex];
13049       end_codep = codep;
13050       FETCH_DATA (info, codep + 1);
13051       modrm.mod = (*codep >> 6) & 3;
13052       modrm.reg = (*codep >> 3) & 7;
13053       modrm.rm = *codep & 7;
13054
13055       /* Set vector length.  */
13056       if (modrm.mod == 3 && vex.b)
13057         vex.length = 512;
13058       else
13059         {
13060           switch (vex.ll)
13061             {
13062             case 0x0:
13063               vex.length = 128;
13064               break;
13065             case 0x1:
13066               vex.length = 256;
13067               break;
13068             case 0x2:
13069               vex.length = 512;
13070               break;
13071             default:
13072               return &bad_opcode;
13073             }
13074         }
13075       break;
13076
13077     case 0:
13078       dp = &bad_opcode;
13079       break;
13080
13081     default:
13082       abort ();
13083     }
13084
13085   if (dp->name != NULL)
13086     return dp;
13087   else
13088     return get_valid_dis386 (dp, info);
13089 }
13090
13091 static void
13092 get_sib (disassemble_info *info, int sizeflag)
13093 {
13094   /* If modrm.mod == 3, operand must be register.  */
13095   if (need_modrm
13096       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13097       && modrm.mod != 3
13098       && modrm.rm == 4)
13099     {
13100       FETCH_DATA (info, codep + 2);
13101       sib.index = (codep [1] >> 3) & 7;
13102       sib.scale = (codep [1] >> 6) & 3;
13103       sib.base = codep [1] & 7;
13104     }
13105 }
13106
13107 static int
13108 print_insn (bfd_vma pc, disassemble_info *info)
13109 {
13110   const struct dis386 *dp;
13111   int i;
13112   char *op_txt[MAX_OPERANDS];
13113   int needcomma;
13114   int sizeflag, orig_sizeflag;
13115   const char *p;
13116   struct dis_private priv;
13117   int prefix_length;
13118
13119   priv.orig_sizeflag = AFLAG | DFLAG;
13120   if ((info->mach & bfd_mach_i386_i386) != 0)
13121     address_mode = mode_32bit;
13122   else if (info->mach == bfd_mach_i386_i8086)
13123     {
13124       address_mode = mode_16bit;
13125       priv.orig_sizeflag = 0;
13126     }
13127   else
13128     address_mode = mode_64bit;
13129
13130   if (intel_syntax == (char) -1)
13131     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13132
13133   for (p = info->disassembler_options; p != NULL; )
13134     {
13135       if (CONST_STRNEQ (p, "amd64"))
13136         isa64 = amd64;
13137       else if (CONST_STRNEQ (p, "intel64"))
13138         isa64 = intel64;
13139       else if (CONST_STRNEQ (p, "x86-64"))
13140         {
13141           address_mode = mode_64bit;
13142           priv.orig_sizeflag = AFLAG | DFLAG;
13143         }
13144       else if (CONST_STRNEQ (p, "i386"))
13145         {
13146           address_mode = mode_32bit;
13147           priv.orig_sizeflag = AFLAG | DFLAG;
13148         }
13149       else if (CONST_STRNEQ (p, "i8086"))
13150         {
13151           address_mode = mode_16bit;
13152           priv.orig_sizeflag = 0;
13153         }
13154       else if (CONST_STRNEQ (p, "intel"))
13155         {
13156           intel_syntax = 1;
13157           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13158             intel_mnemonic = 1;
13159         }
13160       else if (CONST_STRNEQ (p, "att"))
13161         {
13162           intel_syntax = 0;
13163           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13164             intel_mnemonic = 0;
13165         }
13166       else if (CONST_STRNEQ (p, "addr"))
13167         {
13168           if (address_mode == mode_64bit)
13169             {
13170               if (p[4] == '3' && p[5] == '2')
13171                 priv.orig_sizeflag &= ~AFLAG;
13172               else if (p[4] == '6' && p[5] == '4')
13173                 priv.orig_sizeflag |= AFLAG;
13174             }
13175           else
13176             {
13177               if (p[4] == '1' && p[5] == '6')
13178                 priv.orig_sizeflag &= ~AFLAG;
13179               else if (p[4] == '3' && p[5] == '2')
13180                 priv.orig_sizeflag |= AFLAG;
13181             }
13182         }
13183       else if (CONST_STRNEQ (p, "data"))
13184         {
13185           if (p[4] == '1' && p[5] == '6')
13186             priv.orig_sizeflag &= ~DFLAG;
13187           else if (p[4] == '3' && p[5] == '2')
13188             priv.orig_sizeflag |= DFLAG;
13189         }
13190       else if (CONST_STRNEQ (p, "suffix"))
13191         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13192
13193       p = strchr (p, ',');
13194       if (p != NULL)
13195         p++;
13196     }
13197
13198   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13199     {
13200       (*info->fprintf_func) (info->stream,
13201                              _("64-bit address is disabled"));
13202       return -1;
13203     }
13204
13205   if (intel_syntax)
13206     {
13207       names64 = intel_names64;
13208       names32 = intel_names32;
13209       names16 = intel_names16;
13210       names8 = intel_names8;
13211       names8rex = intel_names8rex;
13212       names_seg = intel_names_seg;
13213       names_mm = intel_names_mm;
13214       names_bnd = intel_names_bnd;
13215       names_xmm = intel_names_xmm;
13216       names_ymm = intel_names_ymm;
13217       names_zmm = intel_names_zmm;
13218       index64 = intel_index64;
13219       index32 = intel_index32;
13220       names_mask = intel_names_mask;
13221       index16 = intel_index16;
13222       open_char = '[';
13223       close_char = ']';
13224       separator_char = '+';
13225       scale_char = '*';
13226     }
13227   else
13228     {
13229       names64 = att_names64;
13230       names32 = att_names32;
13231       names16 = att_names16;
13232       names8 = att_names8;
13233       names8rex = att_names8rex;
13234       names_seg = att_names_seg;
13235       names_mm = att_names_mm;
13236       names_bnd = att_names_bnd;
13237       names_xmm = att_names_xmm;
13238       names_ymm = att_names_ymm;
13239       names_zmm = att_names_zmm;
13240       index64 = att_index64;
13241       index32 = att_index32;
13242       names_mask = att_names_mask;
13243       index16 = att_index16;
13244       open_char = '(';
13245       close_char =  ')';
13246       separator_char = ',';
13247       scale_char = ',';
13248     }
13249
13250   /* The output looks better if we put 7 bytes on a line, since that
13251      puts most long word instructions on a single line.  Use 8 bytes
13252      for Intel L1OM.  */
13253   if ((info->mach & bfd_mach_l1om) != 0)
13254     info->bytes_per_line = 8;
13255   else
13256     info->bytes_per_line = 7;
13257
13258   info->private_data = &priv;
13259   priv.max_fetched = priv.the_buffer;
13260   priv.insn_start = pc;
13261
13262   obuf[0] = 0;
13263   for (i = 0; i < MAX_OPERANDS; ++i)
13264     {
13265       op_out[i][0] = 0;
13266       op_index[i] = -1;
13267     }
13268
13269   the_info = info;
13270   start_pc = pc;
13271   start_codep = priv.the_buffer;
13272   codep = priv.the_buffer;
13273
13274   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13275     {
13276       const char *name;
13277
13278       /* Getting here means we tried for data but didn't get it.  That
13279          means we have an incomplete instruction of some sort.  Just
13280          print the first byte as a prefix or a .byte pseudo-op.  */
13281       if (codep > priv.the_buffer)
13282         {
13283           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13284           if (name != NULL)
13285             (*info->fprintf_func) (info->stream, "%s", name);
13286           else
13287             {
13288               /* Just print the first byte as a .byte instruction.  */
13289               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13290                                      (unsigned int) priv.the_buffer[0]);
13291             }
13292
13293           return 1;
13294         }
13295
13296       return -1;
13297     }
13298
13299   obufp = obuf;
13300   sizeflag = priv.orig_sizeflag;
13301
13302   if (!ckprefix () || rex_used)
13303     {
13304       /* Too many prefixes or unused REX prefixes.  */
13305       for (i = 0;
13306            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13307            i++)
13308         (*info->fprintf_func) (info->stream, "%s%s",
13309                                i == 0 ? "" : " ",
13310                                prefix_name (all_prefixes[i], sizeflag));
13311       return i;
13312     }
13313
13314   insn_codep = codep;
13315
13316   FETCH_DATA (info, codep + 1);
13317   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13318
13319   if (((prefixes & PREFIX_FWAIT)
13320        && ((*codep < 0xd8) || (*codep > 0xdf))))
13321     {
13322       /* Handle prefixes before fwait.  */
13323       for (i = 0; i < fwait_prefix && all_prefixes[i];
13324            i++)
13325         (*info->fprintf_func) (info->stream, "%s ",
13326                                prefix_name (all_prefixes[i], sizeflag));
13327       (*info->fprintf_func) (info->stream, "fwait");
13328       return i + 1;
13329     }
13330
13331   if (*codep == 0x0f)
13332     {
13333       unsigned char threebyte;
13334
13335       codep++;
13336       FETCH_DATA (info, codep + 1);
13337       threebyte = *codep;
13338       dp = &dis386_twobyte[threebyte];
13339       need_modrm = twobyte_has_modrm[*codep];
13340       codep++;
13341     }
13342   else
13343     {
13344       dp = &dis386[*codep];
13345       need_modrm = onebyte_has_modrm[*codep];
13346       codep++;
13347     }
13348
13349   /* Save sizeflag for printing the extra prefixes later before updating
13350      it for mnemonic and operand processing.  The prefix names depend
13351      only on the address mode.  */
13352   orig_sizeflag = sizeflag;
13353   if (prefixes & PREFIX_ADDR)
13354     sizeflag ^= AFLAG;
13355   if ((prefixes & PREFIX_DATA))
13356     sizeflag ^= DFLAG;
13357
13358   end_codep = codep;
13359   if (need_modrm)
13360     {
13361       FETCH_DATA (info, codep + 1);
13362       modrm.mod = (*codep >> 6) & 3;
13363       modrm.reg = (*codep >> 3) & 7;
13364       modrm.rm = *codep & 7;
13365     }
13366
13367   need_vex = 0;
13368   need_vex_reg = 0;
13369   vex_w_done = 0;
13370   vex.evex = 0;
13371
13372   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13373     {
13374       get_sib (info, sizeflag);
13375       dofloat (sizeflag);
13376     }
13377   else
13378     {
13379       dp = get_valid_dis386 (dp, info);
13380       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13381         {
13382           get_sib (info, sizeflag);
13383           for (i = 0; i < MAX_OPERANDS; ++i)
13384             {
13385               obufp = op_out[i];
13386               op_ad = MAX_OPERANDS - 1 - i;
13387               if (dp->op[i].rtn)
13388                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13389               /* For EVEX instruction after the last operand masking
13390                  should be printed.  */
13391               if (i == 0 && vex.evex)
13392                 {
13393                   /* Don't print {%k0}.  */
13394                   if (vex.mask_register_specifier)
13395                     {
13396                       oappend ("{");
13397                       oappend (names_mask[vex.mask_register_specifier]);
13398                       oappend ("}");
13399                     }
13400                   if (vex.zeroing)
13401                     oappend ("{z}");
13402                 }
13403             }
13404         }
13405     }
13406
13407   /* Check if the REX prefix is used.  */
13408   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13409     all_prefixes[last_rex_prefix] = 0;
13410
13411   /* Check if the SEG prefix is used.  */
13412   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13413                    | PREFIX_FS | PREFIX_GS)) != 0
13414       && (used_prefixes & active_seg_prefix) != 0)
13415     all_prefixes[last_seg_prefix] = 0;
13416
13417   /* Check if the ADDR prefix is used.  */
13418   if ((prefixes & PREFIX_ADDR) != 0
13419       && (used_prefixes & PREFIX_ADDR) != 0)
13420     all_prefixes[last_addr_prefix] = 0;
13421
13422   /* Check if the DATA prefix is used.  */
13423   if ((prefixes & PREFIX_DATA) != 0
13424       && (used_prefixes & PREFIX_DATA) != 0)
13425     all_prefixes[last_data_prefix] = 0;
13426
13427   /* Print the extra prefixes.  */
13428   prefix_length = 0;
13429   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13430     if (all_prefixes[i])
13431       {
13432         const char *name;
13433         name = prefix_name (all_prefixes[i], orig_sizeflag);
13434         if (name == NULL)
13435           abort ();
13436         prefix_length += strlen (name) + 1;
13437         (*info->fprintf_func) (info->stream, "%s ", name);
13438       }
13439
13440   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13441      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13442      used by putop and MMX/SSE operand and may be overriden by the
13443      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13444      separately.  */
13445   if (dp->prefix_requirement == PREFIX_OPCODE
13446       && dp != &bad_opcode
13447       && (((prefixes
13448             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13449            && (used_prefixes
13450                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13451           || ((((prefixes
13452                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13453                 == PREFIX_DATA)
13454                && (used_prefixes & PREFIX_DATA) == 0))))
13455     {
13456       (*info->fprintf_func) (info->stream, "(bad)");
13457       return end_codep - priv.the_buffer;
13458     }
13459
13460   /* Check maximum code length.  */
13461   if ((codep - start_codep) > MAX_CODE_LENGTH)
13462     {
13463       (*info->fprintf_func) (info->stream, "(bad)");
13464       return MAX_CODE_LENGTH;
13465     }
13466
13467   obufp = mnemonicendp;
13468   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13469     oappend (" ");
13470   oappend (" ");
13471   (*info->fprintf_func) (info->stream, "%s", obuf);
13472
13473   /* The enter and bound instructions are printed with operands in the same
13474      order as the intel book; everything else is printed in reverse order.  */
13475   if (intel_syntax || two_source_ops)
13476     {
13477       bfd_vma riprel;
13478
13479       for (i = 0; i < MAX_OPERANDS; ++i)
13480         op_txt[i] = op_out[i];
13481
13482       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13483           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13484         {
13485           op_txt[2] = op_out[3];
13486           op_txt[3] = op_out[2];
13487         }
13488
13489       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13490         {
13491           op_ad = op_index[i];
13492           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13493           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13494           riprel = op_riprel[i];
13495           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13496           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13497         }
13498     }
13499   else
13500     {
13501       for (i = 0; i < MAX_OPERANDS; ++i)
13502         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13503     }
13504
13505   needcomma = 0;
13506   for (i = 0; i < MAX_OPERANDS; ++i)
13507     if (*op_txt[i])
13508       {
13509         if (needcomma)
13510           (*info->fprintf_func) (info->stream, ",");
13511         if (op_index[i] != -1 && !op_riprel[i])
13512           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13513         else
13514           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13515         needcomma = 1;
13516       }
13517
13518   for (i = 0; i < MAX_OPERANDS; i++)
13519     if (op_index[i] != -1 && op_riprel[i])
13520       {
13521         (*info->fprintf_func) (info->stream, "        # ");
13522         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13523                                                 + op_address[op_index[i]]), info);
13524         break;
13525       }
13526   return codep - priv.the_buffer;
13527 }
13528
13529 static const char *float_mem[] = {
13530   /* d8 */
13531   "fadd{s|}",
13532   "fmul{s|}",
13533   "fcom{s|}",
13534   "fcomp{s|}",
13535   "fsub{s|}",
13536   "fsubr{s|}",
13537   "fdiv{s|}",
13538   "fdivr{s|}",
13539   /* d9 */
13540   "fld{s|}",
13541   "(bad)",
13542   "fst{s|}",
13543   "fstp{s|}",
13544   "fldenvIC",
13545   "fldcw",
13546   "fNstenvIC",
13547   "fNstcw",
13548   /* da */
13549   "fiadd{l|}",
13550   "fimul{l|}",
13551   "ficom{l|}",
13552   "ficomp{l|}",
13553   "fisub{l|}",
13554   "fisubr{l|}",
13555   "fidiv{l|}",
13556   "fidivr{l|}",
13557   /* db */
13558   "fild{l|}",
13559   "fisttp{l|}",
13560   "fist{l|}",
13561   "fistp{l|}",
13562   "(bad)",
13563   "fld{t||t|}",
13564   "(bad)",
13565   "fstp{t||t|}",
13566   /* dc */
13567   "fadd{l|}",
13568   "fmul{l|}",
13569   "fcom{l|}",
13570   "fcomp{l|}",
13571   "fsub{l|}",
13572   "fsubr{l|}",
13573   "fdiv{l|}",
13574   "fdivr{l|}",
13575   /* dd */
13576   "fld{l|}",
13577   "fisttp{ll|}",
13578   "fst{l||}",
13579   "fstp{l|}",
13580   "frstorIC",
13581   "(bad)",
13582   "fNsaveIC",
13583   "fNstsw",
13584   /* de */
13585   "fiadd",
13586   "fimul",
13587   "ficom",
13588   "ficomp",
13589   "fisub",
13590   "fisubr",
13591   "fidiv",
13592   "fidivr",
13593   /* df */
13594   "fild",
13595   "fisttp",
13596   "fist",
13597   "fistp",
13598   "fbld",
13599   "fild{ll|}",
13600   "fbstp",
13601   "fistp{ll|}",
13602 };
13603
13604 static const unsigned char float_mem_mode[] = {
13605   /* d8 */
13606   d_mode,
13607   d_mode,
13608   d_mode,
13609   d_mode,
13610   d_mode,
13611   d_mode,
13612   d_mode,
13613   d_mode,
13614   /* d9 */
13615   d_mode,
13616   0,
13617   d_mode,
13618   d_mode,
13619   0,
13620   w_mode,
13621   0,
13622   w_mode,
13623   /* da */
13624   d_mode,
13625   d_mode,
13626   d_mode,
13627   d_mode,
13628   d_mode,
13629   d_mode,
13630   d_mode,
13631   d_mode,
13632   /* db */
13633   d_mode,
13634   d_mode,
13635   d_mode,
13636   d_mode,
13637   0,
13638   t_mode,
13639   0,
13640   t_mode,
13641   /* dc */
13642   q_mode,
13643   q_mode,
13644   q_mode,
13645   q_mode,
13646   q_mode,
13647   q_mode,
13648   q_mode,
13649   q_mode,
13650   /* dd */
13651   q_mode,
13652   q_mode,
13653   q_mode,
13654   q_mode,
13655   0,
13656   0,
13657   0,
13658   w_mode,
13659   /* de */
13660   w_mode,
13661   w_mode,
13662   w_mode,
13663   w_mode,
13664   w_mode,
13665   w_mode,
13666   w_mode,
13667   w_mode,
13668   /* df */
13669   w_mode,
13670   w_mode,
13671   w_mode,
13672   w_mode,
13673   t_mode,
13674   q_mode,
13675   t_mode,
13676   q_mode
13677 };
13678
13679 #define ST { OP_ST, 0 }
13680 #define STi { OP_STi, 0 }
13681
13682 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13683 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13684 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13685 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13686 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13687 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13688 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13689 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13690 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13691
13692 static const struct dis386 float_reg[][8] = {
13693   /* d8 */
13694   {
13695     { "fadd",   { ST, STi }, 0 },
13696     { "fmul",   { ST, STi }, 0 },
13697     { "fcom",   { STi }, 0 },
13698     { "fcomp",  { STi }, 0 },
13699     { "fsub",   { ST, STi }, 0 },
13700     { "fsubr",  { ST, STi }, 0 },
13701     { "fdiv",   { ST, STi }, 0 },
13702     { "fdivr",  { ST, STi }, 0 },
13703   },
13704   /* d9 */
13705   {
13706     { "fld",    { STi }, 0 },
13707     { "fxch",   { STi }, 0 },
13708     { FGRPd9_2 },
13709     { Bad_Opcode },
13710     { FGRPd9_4 },
13711     { FGRPd9_5 },
13712     { FGRPd9_6 },
13713     { FGRPd9_7 },
13714   },
13715   /* da */
13716   {
13717     { "fcmovb", { ST, STi }, 0 },
13718     { "fcmove", { ST, STi }, 0 },
13719     { "fcmovbe",{ ST, STi }, 0 },
13720     { "fcmovu", { ST, STi }, 0 },
13721     { Bad_Opcode },
13722     { FGRPda_5 },
13723     { Bad_Opcode },
13724     { Bad_Opcode },
13725   },
13726   /* db */
13727   {
13728     { "fcmovnb",{ ST, STi }, 0 },
13729     { "fcmovne",{ ST, STi }, 0 },
13730     { "fcmovnbe",{ ST, STi }, 0 },
13731     { "fcmovnu",{ ST, STi }, 0 },
13732     { FGRPdb_4 },
13733     { "fucomi", { ST, STi }, 0 },
13734     { "fcomi",  { ST, STi }, 0 },
13735     { Bad_Opcode },
13736   },
13737   /* dc */
13738   {
13739     { "fadd",   { STi, ST }, 0 },
13740     { "fmul",   { STi, ST }, 0 },
13741     { Bad_Opcode },
13742     { Bad_Opcode },
13743     { "fsub!M", { STi, ST }, 0 },
13744     { "fsubM",  { STi, ST }, 0 },
13745     { "fdiv!M", { STi, ST }, 0 },
13746     { "fdivM",  { STi, ST }, 0 },
13747   },
13748   /* dd */
13749   {
13750     { "ffree",  { STi }, 0 },
13751     { Bad_Opcode },
13752     { "fst",    { STi }, 0 },
13753     { "fstp",   { STi }, 0 },
13754     { "fucom",  { STi }, 0 },
13755     { "fucomp", { STi }, 0 },
13756     { Bad_Opcode },
13757     { Bad_Opcode },
13758   },
13759   /* de */
13760   {
13761     { "faddp",  { STi, ST }, 0 },
13762     { "fmulp",  { STi, ST }, 0 },
13763     { Bad_Opcode },
13764     { FGRPde_3 },
13765     { "fsub!Mp", { STi, ST }, 0 },
13766     { "fsubMp", { STi, ST }, 0 },
13767     { "fdiv!Mp", { STi, ST }, 0 },
13768     { "fdivMp", { STi, ST }, 0 },
13769   },
13770   /* df */
13771   {
13772     { "ffreep", { STi }, 0 },
13773     { Bad_Opcode },
13774     { Bad_Opcode },
13775     { Bad_Opcode },
13776     { FGRPdf_4 },
13777     { "fucomip", { ST, STi }, 0 },
13778     { "fcomip", { ST, STi }, 0 },
13779     { Bad_Opcode },
13780   },
13781 };
13782
13783 static char *fgrps[][8] = {
13784   /* Bad opcode 0 */
13785   {
13786     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13787   },
13788
13789   /* d9_2  1 */
13790   {
13791     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13792   },
13793
13794   /* d9_4  2 */
13795   {
13796     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13797   },
13798
13799   /* d9_5  3 */
13800   {
13801     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13802   },
13803
13804   /* d9_6  4 */
13805   {
13806     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13807   },
13808
13809   /* d9_7  5 */
13810   {
13811     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13812   },
13813
13814   /* da_5  6 */
13815   {
13816     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13817   },
13818
13819   /* db_4  7 */
13820   {
13821     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13822     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13823   },
13824
13825   /* de_3  8 */
13826   {
13827     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13828   },
13829
13830   /* df_4  9 */
13831   {
13832     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13833   },
13834 };
13835
13836 static void
13837 swap_operand (void)
13838 {
13839   mnemonicendp[0] = '.';
13840   mnemonicendp[1] = 's';
13841   mnemonicendp += 2;
13842 }
13843
13844 static void
13845 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13846                int sizeflag ATTRIBUTE_UNUSED)
13847 {
13848   /* Skip mod/rm byte.  */
13849   MODRM_CHECK;
13850   codep++;
13851 }
13852
13853 static void
13854 dofloat (int sizeflag)
13855 {
13856   const struct dis386 *dp;
13857   unsigned char floatop;
13858
13859   floatop = codep[-1];
13860
13861   if (modrm.mod != 3)
13862     {
13863       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13864
13865       putop (float_mem[fp_indx], sizeflag);
13866       obufp = op_out[0];
13867       op_ad = 2;
13868       OP_E (float_mem_mode[fp_indx], sizeflag);
13869       return;
13870     }
13871   /* Skip mod/rm byte.  */
13872   MODRM_CHECK;
13873   codep++;
13874
13875   dp = &float_reg[floatop - 0xd8][modrm.reg];
13876   if (dp->name == NULL)
13877     {
13878       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13879
13880       /* Instruction fnstsw is only one with strange arg.  */
13881       if (floatop == 0xdf && codep[-1] == 0xe0)
13882         strcpy (op_out[0], names16[0]);
13883     }
13884   else
13885     {
13886       putop (dp->name, sizeflag);
13887
13888       obufp = op_out[0];
13889       op_ad = 2;
13890       if (dp->op[0].rtn)
13891         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13892
13893       obufp = op_out[1];
13894       op_ad = 1;
13895       if (dp->op[1].rtn)
13896         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13897     }
13898 }
13899
13900 /* Like oappend (below), but S is a string starting with '%'.
13901    In Intel syntax, the '%' is elided.  */
13902 static void
13903 oappend_maybe_intel (const char *s)
13904 {
13905   oappend (s + intel_syntax);
13906 }
13907
13908 static void
13909 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13910 {
13911   oappend_maybe_intel ("%st");
13912 }
13913
13914 static void
13915 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13916 {
13917   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13918   oappend_maybe_intel (scratchbuf);
13919 }
13920
13921 /* Capital letters in template are macros.  */
13922 static int
13923 putop (const char *in_template, int sizeflag)
13924 {
13925   const char *p;
13926   int alt = 0;
13927   int cond = 1;
13928   unsigned int l = 0, len = 1;
13929   char last[4];
13930
13931 #define SAVE_LAST(c)                    \
13932   if (l < len && l < sizeof (last))     \
13933     last[l++] = c;                      \
13934   else                                  \
13935     abort ();
13936
13937   for (p = in_template; *p; p++)
13938     {
13939       switch (*p)
13940         {
13941         default:
13942           *obufp++ = *p;
13943           break;
13944         case '%':
13945           len++;
13946           break;
13947         case '!':
13948           cond = 0;
13949           break;
13950         case '{':
13951           if (intel_syntax)
13952             {
13953               while (*++p != '|')
13954                 if (*p == '}' || *p == '\0')
13955                   abort ();
13956             }
13957           /* Fall through.  */
13958         case 'I':
13959           alt = 1;
13960           continue;
13961         case '|':
13962           while (*++p != '}')
13963             {
13964               if (*p == '\0')
13965                 abort ();
13966             }
13967           break;
13968         case '}':
13969           break;
13970         case 'A':
13971           if (intel_syntax)
13972             break;
13973           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13974             *obufp++ = 'b';
13975           break;
13976         case 'B':
13977           if (l == 0 && len == 1)
13978             {
13979 case_B:
13980               if (intel_syntax)
13981                 break;
13982               if (sizeflag & SUFFIX_ALWAYS)
13983                 *obufp++ = 'b';
13984             }
13985           else
13986             {
13987               if (l != 1
13988                   || len != 2
13989                   || last[0] != 'L')
13990                 {
13991                   SAVE_LAST (*p);
13992                   break;
13993                 }
13994
13995               if (address_mode == mode_64bit
13996                   && !(prefixes & PREFIX_ADDR))
13997                 {
13998                   *obufp++ = 'a';
13999                   *obufp++ = 'b';
14000                   *obufp++ = 's';
14001                 }
14002
14003               goto case_B;
14004             }
14005           break;
14006         case 'C':
14007           if (intel_syntax && !alt)
14008             break;
14009           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14010             {
14011               if (sizeflag & DFLAG)
14012                 *obufp++ = intel_syntax ? 'd' : 'l';
14013               else
14014                 *obufp++ = intel_syntax ? 'w' : 's';
14015               used_prefixes |= (prefixes & PREFIX_DATA);
14016             }
14017           break;
14018         case 'D':
14019           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14020             break;
14021           USED_REX (REX_W);
14022           if (modrm.mod == 3)
14023             {
14024               if (rex & REX_W)
14025                 *obufp++ = 'q';
14026               else
14027                 {
14028                   if (sizeflag & DFLAG)
14029                     *obufp++ = intel_syntax ? 'd' : 'l';
14030                   else
14031                     *obufp++ = 'w';
14032                   used_prefixes |= (prefixes & PREFIX_DATA);
14033                 }
14034             }
14035           else
14036             *obufp++ = 'w';
14037           break;
14038         case 'E':               /* For jcxz/jecxz */
14039           if (address_mode == mode_64bit)
14040             {
14041               if (sizeflag & AFLAG)
14042                 *obufp++ = 'r';
14043               else
14044                 *obufp++ = 'e';
14045             }
14046           else
14047             if (sizeflag & AFLAG)
14048               *obufp++ = 'e';
14049           used_prefixes |= (prefixes & PREFIX_ADDR);
14050           break;
14051         case 'F':
14052           if (intel_syntax)
14053             break;
14054           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14055             {
14056               if (sizeflag & AFLAG)
14057                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14058               else
14059                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14060               used_prefixes |= (prefixes & PREFIX_ADDR);
14061             }
14062           break;
14063         case 'G':
14064           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14065             break;
14066           if ((rex & REX_W) || (sizeflag & DFLAG))
14067             *obufp++ = 'l';
14068           else
14069             *obufp++ = 'w';
14070           if (!(rex & REX_W))
14071             used_prefixes |= (prefixes & PREFIX_DATA);
14072           break;
14073         case 'H':
14074           if (intel_syntax)
14075             break;
14076           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14077               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14078             {
14079               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14080               *obufp++ = ',';
14081               *obufp++ = 'p';
14082               if (prefixes & PREFIX_DS)
14083                 *obufp++ = 't';
14084               else
14085                 *obufp++ = 'n';
14086             }
14087           break;
14088         case 'J':
14089           if (intel_syntax)
14090             break;
14091           *obufp++ = 'l';
14092           break;
14093         case 'K':
14094           USED_REX (REX_W);
14095           if (rex & REX_W)
14096             *obufp++ = 'q';
14097           else
14098             *obufp++ = 'd';
14099           break;
14100         case 'Z':
14101           if (l != 0 || len != 1)
14102             {
14103               if (l != 1 || len != 2 || last[0] != 'X')
14104                 {
14105                   SAVE_LAST (*p);
14106                   break;
14107                 }
14108               if (!need_vex || !vex.evex)
14109                 abort ();
14110               if (intel_syntax
14111                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14112                 break;
14113               switch (vex.length)
14114                 {
14115                 case 128:
14116                   *obufp++ = 'x';
14117                   break;
14118                 case 256:
14119                   *obufp++ = 'y';
14120                   break;
14121                 case 512:
14122                   *obufp++ = 'z';
14123                   break;
14124                 default:
14125                   abort ();
14126                 }
14127               break;
14128             }
14129           if (intel_syntax)
14130             break;
14131           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14132             {
14133               *obufp++ = 'q';
14134               break;
14135             }
14136           /* Fall through.  */
14137           goto case_L;
14138         case 'L':
14139           if (l != 0 || len != 1)
14140             {
14141               SAVE_LAST (*p);
14142               break;
14143             }
14144 case_L:
14145           if (intel_syntax)
14146             break;
14147           if (sizeflag & SUFFIX_ALWAYS)
14148             *obufp++ = 'l';
14149           break;
14150         case 'M':
14151           if (intel_mnemonic != cond)
14152             *obufp++ = 'r';
14153           break;
14154         case 'N':
14155           if ((prefixes & PREFIX_FWAIT) == 0)
14156             *obufp++ = 'n';
14157           else
14158             used_prefixes |= PREFIX_FWAIT;
14159           break;
14160         case 'O':
14161           USED_REX (REX_W);
14162           if (rex & REX_W)
14163             *obufp++ = 'o';
14164           else if (intel_syntax && (sizeflag & DFLAG))
14165             *obufp++ = 'q';
14166           else
14167             *obufp++ = 'd';
14168           if (!(rex & REX_W))
14169             used_prefixes |= (prefixes & PREFIX_DATA);
14170           break;
14171         case '&':
14172           if (!intel_syntax
14173               && address_mode == mode_64bit
14174               && isa64 == intel64)
14175             {
14176               *obufp++ = 'q';
14177               break;
14178             }
14179           /* Fall through.  */
14180         case 'T':
14181           if (!intel_syntax
14182               && address_mode == mode_64bit
14183               && ((sizeflag & DFLAG) || (rex & REX_W)))
14184             {
14185               *obufp++ = 'q';
14186               break;
14187             }
14188           /* Fall through.  */
14189           goto case_P;
14190         case 'P':
14191           if (l == 0 && len == 1)
14192             {
14193 case_P:
14194               if (intel_syntax)
14195                 {
14196                   if ((rex & REX_W) == 0
14197                       && (prefixes & PREFIX_DATA))
14198                     {
14199                       if ((sizeflag & DFLAG) == 0)
14200                         *obufp++ = 'w';
14201                       used_prefixes |= (prefixes & PREFIX_DATA);
14202                     }
14203                   break;
14204                 }
14205               if ((prefixes & PREFIX_DATA)
14206                   || (rex & REX_W)
14207                   || (sizeflag & SUFFIX_ALWAYS))
14208                 {
14209                   USED_REX (REX_W);
14210                   if (rex & REX_W)
14211                     *obufp++ = 'q';
14212                   else
14213                     {
14214                       if (sizeflag & DFLAG)
14215                         *obufp++ = 'l';
14216                       else
14217                         *obufp++ = 'w';
14218                       used_prefixes |= (prefixes & PREFIX_DATA);
14219                     }
14220                 }
14221             }
14222           else
14223             {
14224               if (l != 1 || len != 2 || last[0] != 'L')
14225                 {
14226                   SAVE_LAST (*p);
14227                   break;
14228                 }
14229
14230               if ((prefixes & PREFIX_DATA)
14231                   || (rex & REX_W)
14232                   || (sizeflag & SUFFIX_ALWAYS))
14233                 {
14234                   USED_REX (REX_W);
14235                   if (rex & REX_W)
14236                     *obufp++ = 'q';
14237                   else
14238                     {
14239                       if (sizeflag & DFLAG)
14240                         *obufp++ = intel_syntax ? 'd' : 'l';
14241                       else
14242                         *obufp++ = 'w';
14243                       used_prefixes |= (prefixes & PREFIX_DATA);
14244                     }
14245                 }
14246             }
14247           break;
14248         case 'U':
14249           if (intel_syntax)
14250             break;
14251           if (address_mode == mode_64bit
14252               && ((sizeflag & DFLAG) || (rex & REX_W)))
14253             {
14254               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14255                 *obufp++ = 'q';
14256               break;
14257             }
14258           /* Fall through.  */
14259           goto case_Q;
14260         case 'Q':
14261           if (l == 0 && len == 1)
14262             {
14263 case_Q:
14264               if (intel_syntax && !alt)
14265                 break;
14266               USED_REX (REX_W);
14267               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14268                 {
14269                   if (rex & REX_W)
14270                     *obufp++ = 'q';
14271                   else
14272                     {
14273                       if (sizeflag & DFLAG)
14274                         *obufp++ = intel_syntax ? 'd' : 'l';
14275                       else
14276                         *obufp++ = 'w';
14277                       used_prefixes |= (prefixes & PREFIX_DATA);
14278                     }
14279                 }
14280             }
14281           else
14282             {
14283               if (l != 1 || len != 2 || last[0] != 'L')
14284                 {
14285                   SAVE_LAST (*p);
14286                   break;
14287                 }
14288               if (intel_syntax
14289                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14290                 break;
14291               if ((rex & REX_W))
14292                 {
14293                   USED_REX (REX_W);
14294                   *obufp++ = 'q';
14295                 }
14296               else
14297                 *obufp++ = 'l';
14298             }
14299           break;
14300         case 'R':
14301           USED_REX (REX_W);
14302           if (rex & REX_W)
14303             *obufp++ = 'q';
14304           else if (sizeflag & DFLAG)
14305             {
14306               if (intel_syntax)
14307                   *obufp++ = 'd';
14308               else
14309                   *obufp++ = 'l';
14310             }
14311           else
14312             *obufp++ = 'w';
14313           if (intel_syntax && !p[1]
14314               && ((rex & REX_W) || (sizeflag & DFLAG)))
14315             *obufp++ = 'e';
14316           if (!(rex & REX_W))
14317             used_prefixes |= (prefixes & PREFIX_DATA);
14318           break;
14319         case 'V':
14320           if (l == 0 && len == 1)
14321             {
14322               if (intel_syntax)
14323                 break;
14324               if (address_mode == mode_64bit
14325                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14326                 {
14327                   if (sizeflag & SUFFIX_ALWAYS)
14328                     *obufp++ = 'q';
14329                   break;
14330                 }
14331             }
14332           else
14333             {
14334               if (l != 1
14335                   || len != 2
14336                   || last[0] != 'L')
14337                 {
14338                   SAVE_LAST (*p);
14339                   break;
14340                 }
14341
14342               if (rex & REX_W)
14343                 {
14344                   *obufp++ = 'a';
14345                   *obufp++ = 'b';
14346                   *obufp++ = 's';
14347                 }
14348             }
14349           /* Fall through.  */
14350           goto case_S;
14351         case 'S':
14352           if (l == 0 && len == 1)
14353             {
14354 case_S:
14355               if (intel_syntax)
14356                 break;
14357               if (sizeflag & SUFFIX_ALWAYS)
14358                 {
14359                   if (rex & REX_W)
14360                     *obufp++ = 'q';
14361                   else
14362                     {
14363                       if (sizeflag & DFLAG)
14364                         *obufp++ = 'l';
14365                       else
14366                         *obufp++ = 'w';
14367                       used_prefixes |= (prefixes & PREFIX_DATA);
14368                     }
14369                 }
14370             }
14371           else
14372             {
14373               if (l != 1
14374                   || len != 2
14375                   || last[0] != 'L')
14376                 {
14377                   SAVE_LAST (*p);
14378                   break;
14379                 }
14380
14381               if (address_mode == mode_64bit
14382                   && !(prefixes & PREFIX_ADDR))
14383                 {
14384                   *obufp++ = 'a';
14385                   *obufp++ = 'b';
14386                   *obufp++ = 's';
14387                 }
14388
14389               goto case_S;
14390             }
14391           break;
14392         case 'X':
14393           if (l != 0 || len != 1)
14394             {
14395               SAVE_LAST (*p);
14396               break;
14397             }
14398           if (need_vex && vex.prefix)
14399             {
14400               if (vex.prefix == DATA_PREFIX_OPCODE)
14401                 *obufp++ = 'd';
14402               else
14403                 *obufp++ = 's';
14404             }
14405           else
14406             {
14407               if (prefixes & PREFIX_DATA)
14408                 *obufp++ = 'd';
14409               else
14410                 *obufp++ = 's';
14411               used_prefixes |= (prefixes & PREFIX_DATA);
14412             }
14413           break;
14414         case 'Y':
14415           if (l == 0 && len == 1)
14416             {
14417               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14418                 break;
14419               if (rex & REX_W)
14420                 {
14421                   USED_REX (REX_W);
14422                   *obufp++ = 'q';
14423                 }
14424               break;
14425             }
14426           else
14427             {
14428               if (l != 1 || len != 2 || last[0] != 'X')
14429                 {
14430                   SAVE_LAST (*p);
14431                   break;
14432                 }
14433               if (!need_vex)
14434                 abort ();
14435               if (intel_syntax
14436                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14437                 break;
14438               switch (vex.length)
14439                 {
14440                 case 128:
14441                   *obufp++ = 'x';
14442                   break;
14443                 case 256:
14444                   *obufp++ = 'y';
14445                   break;
14446                 case 512:
14447                   if (!vex.evex)
14448                 default:
14449                     abort ();
14450                 }
14451             }
14452           break;
14453         case 'W':
14454           if (l == 0 && len == 1)
14455             {
14456               /* operand size flag for cwtl, cbtw */
14457               USED_REX (REX_W);
14458               if (rex & REX_W)
14459                 {
14460                   if (intel_syntax)
14461                     *obufp++ = 'd';
14462                   else
14463                     *obufp++ = 'l';
14464                 }
14465               else if (sizeflag & DFLAG)
14466                 *obufp++ = 'w';
14467               else
14468                 *obufp++ = 'b';
14469               if (!(rex & REX_W))
14470                 used_prefixes |= (prefixes & PREFIX_DATA);
14471             }
14472           else
14473             {
14474               if (l != 1
14475                   || len != 2
14476                   || (last[0] != 'X'
14477                       && last[0] != 'L'))
14478                 {
14479                   SAVE_LAST (*p);
14480                   break;
14481                 }
14482               if (!need_vex)
14483                 abort ();
14484               if (last[0] == 'X')
14485                 *obufp++ = vex.w ? 'd': 's';
14486               else
14487                 *obufp++ = vex.w ? 'q': 'd';
14488             }
14489           break;
14490         case '^':
14491           if (intel_syntax)
14492             break;
14493           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14494             {
14495               if (sizeflag & DFLAG)
14496                 *obufp++ = 'l';
14497               else
14498                 *obufp++ = 'w';
14499               used_prefixes |= (prefixes & PREFIX_DATA);
14500             }
14501           break;
14502         case '@':
14503           if (intel_syntax)
14504             break;
14505           if (address_mode == mode_64bit
14506               && (isa64 == intel64
14507                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14508               *obufp++ = 'q';
14509           else if ((prefixes & PREFIX_DATA))
14510             {
14511               if (!(sizeflag & DFLAG))
14512                 *obufp++ = 'w';
14513               used_prefixes |= (prefixes & PREFIX_DATA);
14514             }
14515           break;
14516         }
14517       alt = 0;
14518     }
14519   *obufp = 0;
14520   mnemonicendp = obufp;
14521   return 0;
14522 }
14523
14524 static void
14525 oappend (const char *s)
14526 {
14527   obufp = stpcpy (obufp, s);
14528 }
14529
14530 static void
14531 append_seg (void)
14532 {
14533   /* Only print the active segment register.  */
14534   if (!active_seg_prefix)
14535     return;
14536
14537   used_prefixes |= active_seg_prefix;
14538   switch (active_seg_prefix)
14539     {
14540     case PREFIX_CS:
14541       oappend_maybe_intel ("%cs:");
14542       break;
14543     case PREFIX_DS:
14544       oappend_maybe_intel ("%ds:");
14545       break;
14546     case PREFIX_SS:
14547       oappend_maybe_intel ("%ss:");
14548       break;
14549     case PREFIX_ES:
14550       oappend_maybe_intel ("%es:");
14551       break;
14552     case PREFIX_FS:
14553       oappend_maybe_intel ("%fs:");
14554       break;
14555     case PREFIX_GS:
14556       oappend_maybe_intel ("%gs:");
14557       break;
14558     default:
14559       break;
14560     }
14561 }
14562
14563 static void
14564 OP_indirE (int bytemode, int sizeflag)
14565 {
14566   if (!intel_syntax)
14567     oappend ("*");
14568   OP_E (bytemode, sizeflag);
14569 }
14570
14571 static void
14572 print_operand_value (char *buf, int hex, bfd_vma disp)
14573 {
14574   if (address_mode == mode_64bit)
14575     {
14576       if (hex)
14577         {
14578           char tmp[30];
14579           int i;
14580           buf[0] = '0';
14581           buf[1] = 'x';
14582           sprintf_vma (tmp, disp);
14583           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14584           strcpy (buf + 2, tmp + i);
14585         }
14586       else
14587         {
14588           bfd_signed_vma v = disp;
14589           char tmp[30];
14590           int i;
14591           if (v < 0)
14592             {
14593               *(buf++) = '-';
14594               v = -disp;
14595               /* Check for possible overflow on 0x8000000000000000.  */
14596               if (v < 0)
14597                 {
14598                   strcpy (buf, "9223372036854775808");
14599                   return;
14600                 }
14601             }
14602           if (!v)
14603             {
14604               strcpy (buf, "0");
14605               return;
14606             }
14607
14608           i = 0;
14609           tmp[29] = 0;
14610           while (v)
14611             {
14612               tmp[28 - i] = (v % 10) + '0';
14613               v /= 10;
14614               i++;
14615             }
14616           strcpy (buf, tmp + 29 - i);
14617         }
14618     }
14619   else
14620     {
14621       if (hex)
14622         sprintf (buf, "0x%x", (unsigned int) disp);
14623       else
14624         sprintf (buf, "%d", (int) disp);
14625     }
14626 }
14627
14628 /* Put DISP in BUF as signed hex number.  */
14629
14630 static void
14631 print_displacement (char *buf, bfd_vma disp)
14632 {
14633   bfd_signed_vma val = disp;
14634   char tmp[30];
14635   int i, j = 0;
14636
14637   if (val < 0)
14638     {
14639       buf[j++] = '-';
14640       val = -disp;
14641
14642       /* Check for possible overflow.  */
14643       if (val < 0)
14644         {
14645           switch (address_mode)
14646             {
14647             case mode_64bit:
14648               strcpy (buf + j, "0x8000000000000000");
14649               break;
14650             case mode_32bit:
14651               strcpy (buf + j, "0x80000000");
14652               break;
14653             case mode_16bit:
14654               strcpy (buf + j, "0x8000");
14655               break;
14656             }
14657           return;
14658         }
14659     }
14660
14661   buf[j++] = '0';
14662   buf[j++] = 'x';
14663
14664   sprintf_vma (tmp, (bfd_vma) val);
14665   for (i = 0; tmp[i] == '0'; i++)
14666     continue;
14667   if (tmp[i] == '\0')
14668     i--;
14669   strcpy (buf + j, tmp + i);
14670 }
14671
14672 static void
14673 intel_operand_size (int bytemode, int sizeflag)
14674 {
14675   if (vex.evex
14676       && vex.b
14677       && (bytemode == x_mode
14678           || bytemode == evex_half_bcst_xmmq_mode))
14679     {
14680       if (vex.w)
14681         oappend ("QWORD PTR ");
14682       else
14683         oappend ("DWORD PTR ");
14684       return;
14685     }
14686   switch (bytemode)
14687     {
14688     case b_mode:
14689     case b_swap_mode:
14690     case dqb_mode:
14691     case db_mode:
14692       oappend ("BYTE PTR ");
14693       break;
14694     case w_mode:
14695     case dw_mode:
14696     case dqw_mode:
14697       oappend ("WORD PTR ");
14698       break;
14699     case indir_v_mode:
14700       if (address_mode == mode_64bit && isa64 == intel64)
14701         {
14702           oappend ("QWORD PTR ");
14703           break;
14704         }
14705       /* Fall through.  */
14706     case stack_v_mode:
14707       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14708         {
14709           oappend ("QWORD PTR ");
14710           break;
14711         }
14712       /* Fall through.  */
14713     case v_mode:
14714     case v_swap_mode:
14715     case dq_mode:
14716       USED_REX (REX_W);
14717       if (rex & REX_W)
14718         oappend ("QWORD PTR ");
14719       else
14720         {
14721           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14722             oappend ("DWORD PTR ");
14723           else
14724             oappend ("WORD PTR ");
14725           used_prefixes |= (prefixes & PREFIX_DATA);
14726         }
14727       break;
14728     case z_mode:
14729       if ((rex & REX_W) || (sizeflag & DFLAG))
14730         *obufp++ = 'D';
14731       oappend ("WORD PTR ");
14732       if (!(rex & REX_W))
14733         used_prefixes |= (prefixes & PREFIX_DATA);
14734       break;
14735     case a_mode:
14736       if (sizeflag & DFLAG)
14737         oappend ("QWORD PTR ");
14738       else
14739         oappend ("DWORD PTR ");
14740       used_prefixes |= (prefixes & PREFIX_DATA);
14741       break;
14742     case d_mode:
14743     case d_scalar_mode:
14744     case d_scalar_swap_mode:
14745     case d_swap_mode:
14746     case dqd_mode:
14747       oappend ("DWORD PTR ");
14748       break;
14749     case q_mode:
14750     case q_scalar_mode:
14751     case q_scalar_swap_mode:
14752     case q_swap_mode:
14753       oappend ("QWORD PTR ");
14754       break;
14755     case m_mode:
14756       if (address_mode == mode_64bit)
14757         oappend ("QWORD PTR ");
14758       else
14759         oappend ("DWORD PTR ");
14760       break;
14761     case f_mode:
14762       if (sizeflag & DFLAG)
14763         oappend ("FWORD PTR ");
14764       else
14765         oappend ("DWORD PTR ");
14766       used_prefixes |= (prefixes & PREFIX_DATA);
14767       break;
14768     case t_mode:
14769       oappend ("TBYTE PTR ");
14770       break;
14771     case x_mode:
14772     case x_swap_mode:
14773     case evex_x_gscat_mode:
14774     case evex_x_nobcst_mode:
14775     case b_scalar_mode:
14776     case w_scalar_mode:
14777       if (need_vex)
14778         {
14779           switch (vex.length)
14780             {
14781             case 128:
14782               oappend ("XMMWORD PTR ");
14783               break;
14784             case 256:
14785               oappend ("YMMWORD PTR ");
14786               break;
14787             case 512:
14788               oappend ("ZMMWORD PTR ");
14789               break;
14790             default:
14791               abort ();
14792             }
14793         }
14794       else
14795         oappend ("XMMWORD PTR ");
14796       break;
14797     case xmm_mode:
14798       oappend ("XMMWORD PTR ");
14799       break;
14800     case ymm_mode:
14801       oappend ("YMMWORD PTR ");
14802       break;
14803     case xmmq_mode:
14804     case evex_half_bcst_xmmq_mode:
14805       if (!need_vex)
14806         abort ();
14807
14808       switch (vex.length)
14809         {
14810         case 128:
14811           oappend ("QWORD PTR ");
14812           break;
14813         case 256:
14814           oappend ("XMMWORD PTR ");
14815           break;
14816         case 512:
14817           oappend ("YMMWORD PTR ");
14818           break;
14819         default:
14820           abort ();
14821         }
14822       break;
14823     case xmm_mb_mode:
14824       if (!need_vex)
14825         abort ();
14826
14827       switch (vex.length)
14828         {
14829         case 128:
14830         case 256:
14831         case 512:
14832           oappend ("BYTE PTR ");
14833           break;
14834         default:
14835           abort ();
14836         }
14837       break;
14838     case xmm_mw_mode:
14839       if (!need_vex)
14840         abort ();
14841
14842       switch (vex.length)
14843         {
14844         case 128:
14845         case 256:
14846         case 512:
14847           oappend ("WORD PTR ");
14848           break;
14849         default:
14850           abort ();
14851         }
14852       break;
14853     case xmm_md_mode:
14854       if (!need_vex)
14855         abort ();
14856
14857       switch (vex.length)
14858         {
14859         case 128:
14860         case 256:
14861         case 512:
14862           oappend ("DWORD PTR ");
14863           break;
14864         default:
14865           abort ();
14866         }
14867       break;
14868     case xmm_mq_mode:
14869       if (!need_vex)
14870         abort ();
14871
14872       switch (vex.length)
14873         {
14874         case 128:
14875         case 256:
14876         case 512:
14877           oappend ("QWORD PTR ");
14878           break;
14879         default:
14880           abort ();
14881         }
14882       break;
14883     case xmmdw_mode:
14884       if (!need_vex)
14885         abort ();
14886
14887       switch (vex.length)
14888         {
14889         case 128:
14890           oappend ("WORD PTR ");
14891           break;
14892         case 256:
14893           oappend ("DWORD PTR ");
14894           break;
14895         case 512:
14896           oappend ("QWORD PTR ");
14897           break;
14898         default:
14899           abort ();
14900         }
14901       break;
14902     case xmmqd_mode:
14903       if (!need_vex)
14904         abort ();
14905
14906       switch (vex.length)
14907         {
14908         case 128:
14909           oappend ("DWORD PTR ");
14910           break;
14911         case 256:
14912           oappend ("QWORD PTR ");
14913           break;
14914         case 512:
14915           oappend ("XMMWORD PTR ");
14916           break;
14917         default:
14918           abort ();
14919         }
14920       break;
14921     case ymmq_mode:
14922       if (!need_vex)
14923         abort ();
14924
14925       switch (vex.length)
14926         {
14927         case 128:
14928           oappend ("QWORD PTR ");
14929           break;
14930         case 256:
14931           oappend ("YMMWORD PTR ");
14932           break;
14933         case 512:
14934           oappend ("ZMMWORD PTR ");
14935           break;
14936         default:
14937           abort ();
14938         }
14939       break;
14940     case ymmxmm_mode:
14941       if (!need_vex)
14942         abort ();
14943
14944       switch (vex.length)
14945         {
14946         case 128:
14947         case 256:
14948           oappend ("XMMWORD PTR ");
14949           break;
14950         default:
14951           abort ();
14952         }
14953       break;
14954     case o_mode:
14955       oappend ("OWORD PTR ");
14956       break;
14957     case xmm_mdq_mode:
14958     case vex_w_dq_mode:
14959     case vex_scalar_w_dq_mode:
14960       if (!need_vex)
14961         abort ();
14962
14963       if (vex.w)
14964         oappend ("QWORD PTR ");
14965       else
14966         oappend ("DWORD PTR ");
14967       break;
14968     case vex_vsib_d_w_dq_mode:
14969     case vex_vsib_q_w_dq_mode:
14970       if (!need_vex)
14971         abort ();
14972
14973       if (!vex.evex)
14974         {
14975           if (vex.w)
14976             oappend ("QWORD PTR ");
14977           else
14978             oappend ("DWORD PTR ");
14979         }
14980       else
14981         {
14982           switch (vex.length)
14983             {
14984             case 128:
14985               oappend ("XMMWORD PTR ");
14986               break;
14987             case 256:
14988               oappend ("YMMWORD PTR ");
14989               break;
14990             case 512:
14991               oappend ("ZMMWORD PTR ");
14992               break;
14993             default:
14994               abort ();
14995             }
14996         }
14997       break;
14998     case vex_vsib_q_w_d_mode:
14999     case vex_vsib_d_w_d_mode:
15000       if (!need_vex || !vex.evex)
15001         abort ();
15002
15003       switch (vex.length)
15004         {
15005         case 128:
15006           oappend ("QWORD PTR ");
15007           break;
15008         case 256:
15009           oappend ("XMMWORD PTR ");
15010           break;
15011         case 512:
15012           oappend ("YMMWORD PTR ");
15013           break;
15014         default:
15015           abort ();
15016         }
15017
15018       break;
15019     case mask_bd_mode:
15020       if (!need_vex || vex.length != 128)
15021         abort ();
15022       if (vex.w)
15023         oappend ("DWORD PTR ");
15024       else
15025         oappend ("BYTE PTR ");
15026       break;
15027     case mask_mode:
15028       if (!need_vex)
15029         abort ();
15030       if (vex.w)
15031         oappend ("QWORD PTR ");
15032       else
15033         oappend ("WORD PTR ");
15034       break;
15035     case v_bnd_mode:
15036     default:
15037       break;
15038     }
15039 }
15040
15041 static void
15042 OP_E_register (int bytemode, int sizeflag)
15043 {
15044   int reg = modrm.rm;
15045   const char **names;
15046
15047   USED_REX (REX_B);
15048   if ((rex & REX_B))
15049     reg += 8;
15050
15051   if ((sizeflag & SUFFIX_ALWAYS)
15052       && (bytemode == b_swap_mode
15053           || bytemode == v_swap_mode))
15054     swap_operand ();
15055
15056   switch (bytemode)
15057     {
15058     case b_mode:
15059     case b_swap_mode:
15060       USED_REX (0);
15061       if (rex)
15062         names = names8rex;
15063       else
15064         names = names8;
15065       break;
15066     case w_mode:
15067       names = names16;
15068       break;
15069     case d_mode:
15070     case dw_mode:
15071     case db_mode:
15072       names = names32;
15073       break;
15074     case q_mode:
15075       names = names64;
15076       break;
15077     case m_mode:
15078     case v_bnd_mode:
15079       names = address_mode == mode_64bit ? names64 : names32;
15080       break;
15081     case bnd_mode:
15082       if (reg > 0x3)
15083         {
15084           oappend ("(bad)");
15085           return;
15086         }
15087       names = names_bnd;
15088       break;
15089     case indir_v_mode:
15090       if (address_mode == mode_64bit && isa64 == intel64)
15091         {
15092           names = names64;
15093           break;
15094         }
15095       /* Fall through.  */
15096     case stack_v_mode:
15097       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15098         {
15099           names = names64;
15100           break;
15101         }
15102       bytemode = v_mode;
15103       /* Fall through.  */
15104     case v_mode:
15105     case v_swap_mode:
15106     case dq_mode:
15107     case dqb_mode:
15108     case dqd_mode:
15109     case dqw_mode:
15110       USED_REX (REX_W);
15111       if (rex & REX_W)
15112         names = names64;
15113       else
15114         {
15115           if ((sizeflag & DFLAG)
15116               || (bytemode != v_mode
15117                   && bytemode != v_swap_mode))
15118             names = names32;
15119           else
15120             names = names16;
15121           used_prefixes |= (prefixes & PREFIX_DATA);
15122         }
15123       break;
15124     case mask_bd_mode:
15125     case mask_mode:
15126       if (reg > 0x7)
15127         {
15128           oappend ("(bad)");
15129           return;
15130         }
15131       names = names_mask;
15132       break;
15133     case 0:
15134       return;
15135     default:
15136       oappend (INTERNAL_DISASSEMBLER_ERROR);
15137       return;
15138     }
15139   oappend (names[reg]);
15140 }
15141
15142 static void
15143 OP_E_memory (int bytemode, int sizeflag)
15144 {
15145   bfd_vma disp = 0;
15146   int add = (rex & REX_B) ? 8 : 0;
15147   int riprel = 0;
15148   int shift;
15149
15150   if (vex.evex)
15151     {
15152       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15153       if (vex.b
15154           && bytemode != x_mode
15155           && bytemode != xmmq_mode
15156           && bytemode != evex_half_bcst_xmmq_mode)
15157         {
15158           BadOp ();
15159           return;
15160         }
15161       switch (bytemode)
15162         {
15163         case dqw_mode:
15164         case dw_mode:
15165           shift = 1;
15166           break;
15167         case dqb_mode:
15168         case db_mode:
15169           shift = 0;
15170           break;
15171         case vex_vsib_d_w_dq_mode:
15172         case vex_vsib_d_w_d_mode:
15173         case vex_vsib_q_w_dq_mode:
15174         case vex_vsib_q_w_d_mode:
15175         case evex_x_gscat_mode:
15176         case xmm_mdq_mode:
15177           shift = vex.w ? 3 : 2;
15178           break;
15179         case x_mode:
15180         case evex_half_bcst_xmmq_mode:
15181         case xmmq_mode:
15182           if (vex.b)
15183             {
15184               shift = vex.w ? 3 : 2;
15185               break;
15186             }
15187           /* Fall through.  */
15188         case xmmqd_mode:
15189         case xmmdw_mode:
15190         case ymmq_mode:
15191         case evex_x_nobcst_mode:
15192         case x_swap_mode:
15193           switch (vex.length)
15194             {
15195             case 128:
15196               shift = 4;
15197               break;
15198             case 256:
15199               shift = 5;
15200               break;
15201             case 512:
15202               shift = 6;
15203               break;
15204             default:
15205               abort ();
15206             }
15207           break;
15208         case ymm_mode:
15209           shift = 5;
15210           break;
15211         case xmm_mode:
15212           shift = 4;
15213           break;
15214         case xmm_mq_mode:
15215         case q_mode:
15216         case q_scalar_mode:
15217         case q_swap_mode:
15218         case q_scalar_swap_mode:
15219           shift = 3;
15220           break;
15221         case dqd_mode:
15222         case xmm_md_mode:
15223         case d_mode:
15224         case d_scalar_mode:
15225         case d_swap_mode:
15226         case d_scalar_swap_mode:
15227           shift = 2;
15228           break;
15229     case w_scalar_mode:
15230         case xmm_mw_mode:
15231           shift = 1;
15232           break;
15233     case b_scalar_mode:
15234         case xmm_mb_mode:
15235           shift = 0;
15236           break;
15237         default:
15238           abort ();
15239         }
15240       /* Make necessary corrections to shift for modes that need it.
15241          For these modes we currently have shift 4, 5 or 6 depending on
15242          vex.length (it corresponds to xmmword, ymmword or zmmword
15243          operand).  We might want to make it 3, 4 or 5 (e.g. for
15244          xmmq_mode).  In case of broadcast enabled the corrections
15245          aren't needed, as element size is always 32 or 64 bits.  */
15246       if (!vex.b
15247           && (bytemode == xmmq_mode
15248               || bytemode == evex_half_bcst_xmmq_mode))
15249         shift -= 1;
15250       else if (bytemode == xmmqd_mode)
15251         shift -= 2;
15252       else if (bytemode == xmmdw_mode)
15253         shift -= 3;
15254       else if (bytemode == ymmq_mode && vex.length == 128)
15255         shift -= 1;
15256     }
15257   else
15258     shift = 0;
15259
15260   USED_REX (REX_B);
15261   if (intel_syntax)
15262     intel_operand_size (bytemode, sizeflag);
15263   append_seg ();
15264
15265   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15266     {
15267       /* 32/64 bit address mode */
15268       int havedisp;
15269       int havesib;
15270       int havebase;
15271       int haveindex;
15272       int needindex;
15273       int base, rbase;
15274       int vindex = 0;
15275       int scale = 0;
15276       int addr32flag = !((sizeflag & AFLAG)
15277                          || bytemode == v_bnd_mode
15278                          || bytemode == bnd_mode);
15279       const char **indexes64 = names64;
15280       const char **indexes32 = names32;
15281
15282       havesib = 0;
15283       havebase = 1;
15284       haveindex = 0;
15285       base = modrm.rm;
15286
15287       if (base == 4)
15288         {
15289           havesib = 1;
15290           vindex = sib.index;
15291           USED_REX (REX_X);
15292           if (rex & REX_X)
15293             vindex += 8;
15294           switch (bytemode)
15295             {
15296             case vex_vsib_d_w_dq_mode:
15297             case vex_vsib_d_w_d_mode:
15298             case vex_vsib_q_w_dq_mode:
15299             case vex_vsib_q_w_d_mode:
15300               if (!need_vex)
15301                 abort ();
15302               if (vex.evex)
15303                 {
15304                   if (!vex.v)
15305                     vindex += 16;
15306                 }
15307
15308               haveindex = 1;
15309               switch (vex.length)
15310                 {
15311                 case 128:
15312                   indexes64 = indexes32 = names_xmm;
15313                   break;
15314                 case 256:
15315                   if (!vex.w
15316                       || bytemode == vex_vsib_q_w_dq_mode
15317                       || bytemode == vex_vsib_q_w_d_mode)
15318                     indexes64 = indexes32 = names_ymm;
15319                   else
15320                     indexes64 = indexes32 = names_xmm;
15321                   break;
15322                 case 512:
15323                   if (!vex.w
15324                       || bytemode == vex_vsib_q_w_dq_mode
15325                       || bytemode == vex_vsib_q_w_d_mode)
15326                     indexes64 = indexes32 = names_zmm;
15327                   else
15328                     indexes64 = indexes32 = names_ymm;
15329                   break;
15330                 default:
15331                   abort ();
15332                 }
15333               break;
15334             default:
15335               haveindex = vindex != 4;
15336               break;
15337             }
15338           scale = sib.scale;
15339           base = sib.base;
15340           codep++;
15341         }
15342       rbase = base + add;
15343
15344       switch (modrm.mod)
15345         {
15346         case 0:
15347           if (base == 5)
15348             {
15349               havebase = 0;
15350               if (address_mode == mode_64bit && !havesib)
15351                 riprel = 1;
15352               disp = get32s ();
15353             }
15354           break;
15355         case 1:
15356           FETCH_DATA (the_info, codep + 1);
15357           disp = *codep++;
15358           if ((disp & 0x80) != 0)
15359             disp -= 0x100;
15360           if (vex.evex && shift > 0)
15361             disp <<= shift;
15362           break;
15363         case 2:
15364           disp = get32s ();
15365           break;
15366         }
15367
15368       /* In 32bit mode, we need index register to tell [offset] from
15369          [eiz*1 + offset].  */
15370       needindex = (havesib
15371                    && !havebase
15372                    && !haveindex
15373                    && address_mode == mode_32bit);
15374       havedisp = (havebase
15375                   || needindex
15376                   || (havesib && (haveindex || scale != 0)));
15377
15378       if (!intel_syntax)
15379         if (modrm.mod != 0 || base == 5)
15380           {
15381             if (havedisp || riprel)
15382               print_displacement (scratchbuf, disp);
15383             else
15384               print_operand_value (scratchbuf, 1, disp);
15385             oappend (scratchbuf);
15386             if (riprel)
15387               {
15388                 set_op (disp, 1);
15389                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15390               }
15391           }
15392
15393       if ((havebase || haveindex || riprel)
15394           && (bytemode != v_bnd_mode)
15395           && (bytemode != bnd_mode))
15396         used_prefixes |= PREFIX_ADDR;
15397
15398       if (havedisp || (intel_syntax && riprel))
15399         {
15400           *obufp++ = open_char;
15401           if (intel_syntax && riprel)
15402             {
15403               set_op (disp, 1);
15404               oappend (!addr32flag ? "rip" : "eip");
15405             }
15406           *obufp = '\0';
15407           if (havebase)
15408             oappend (address_mode == mode_64bit && !addr32flag
15409                      ? names64[rbase] : names32[rbase]);
15410           if (havesib)
15411             {
15412               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15413                  print index to tell base + index from base.  */
15414               if (scale != 0
15415                   || needindex
15416                   || haveindex
15417                   || (havebase && base != ESP_REG_NUM))
15418                 {
15419                   if (!intel_syntax || havebase)
15420                     {
15421                       *obufp++ = separator_char;
15422                       *obufp = '\0';
15423                     }
15424                   if (haveindex)
15425                     oappend (address_mode == mode_64bit && !addr32flag
15426                              ? indexes64[vindex] : indexes32[vindex]);
15427                   else
15428                     oappend (address_mode == mode_64bit && !addr32flag
15429                              ? index64 : index32);
15430
15431                   *obufp++ = scale_char;
15432                   *obufp = '\0';
15433                   sprintf (scratchbuf, "%d", 1 << scale);
15434                   oappend (scratchbuf);
15435                 }
15436             }
15437           if (intel_syntax
15438               && (disp || modrm.mod != 0 || base == 5))
15439             {
15440               if (!havedisp || (bfd_signed_vma) disp >= 0)
15441                 {
15442                   *obufp++ = '+';
15443                   *obufp = '\0';
15444                 }
15445               else if (modrm.mod != 1 && disp != -disp)
15446                 {
15447                   *obufp++ = '-';
15448                   *obufp = '\0';
15449                   disp = - (bfd_signed_vma) disp;
15450                 }
15451
15452               if (havedisp)
15453                 print_displacement (scratchbuf, disp);
15454               else
15455                 print_operand_value (scratchbuf, 1, disp);
15456               oappend (scratchbuf);
15457             }
15458
15459           *obufp++ = close_char;
15460           *obufp = '\0';
15461         }
15462       else if (intel_syntax)
15463         {
15464           if (modrm.mod != 0 || base == 5)
15465             {
15466               if (!active_seg_prefix)
15467                 {
15468                   oappend (names_seg[ds_reg - es_reg]);
15469                   oappend (":");
15470                 }
15471               print_operand_value (scratchbuf, 1, disp);
15472               oappend (scratchbuf);
15473             }
15474         }
15475     }
15476   else
15477     {
15478       /* 16 bit address mode */
15479       used_prefixes |= prefixes & PREFIX_ADDR;
15480       switch (modrm.mod)
15481         {
15482         case 0:
15483           if (modrm.rm == 6)
15484             {
15485               disp = get16 ();
15486               if ((disp & 0x8000) != 0)
15487                 disp -= 0x10000;
15488             }
15489           break;
15490         case 1:
15491           FETCH_DATA (the_info, codep + 1);
15492           disp = *codep++;
15493           if ((disp & 0x80) != 0)
15494             disp -= 0x100;
15495           break;
15496         case 2:
15497           disp = get16 ();
15498           if ((disp & 0x8000) != 0)
15499             disp -= 0x10000;
15500           break;
15501         }
15502
15503       if (!intel_syntax)
15504         if (modrm.mod != 0 || modrm.rm == 6)
15505           {
15506             print_displacement (scratchbuf, disp);
15507             oappend (scratchbuf);
15508           }
15509
15510       if (modrm.mod != 0 || modrm.rm != 6)
15511         {
15512           *obufp++ = open_char;
15513           *obufp = '\0';
15514           oappend (index16[modrm.rm]);
15515           if (intel_syntax
15516               && (disp || modrm.mod != 0 || modrm.rm == 6))
15517             {
15518               if ((bfd_signed_vma) disp >= 0)
15519                 {
15520                   *obufp++ = '+';
15521                   *obufp = '\0';
15522                 }
15523               else if (modrm.mod != 1)
15524                 {
15525                   *obufp++ = '-';
15526                   *obufp = '\0';
15527                   disp = - (bfd_signed_vma) disp;
15528                 }
15529
15530               print_displacement (scratchbuf, disp);
15531               oappend (scratchbuf);
15532             }
15533
15534           *obufp++ = close_char;
15535           *obufp = '\0';
15536         }
15537       else if (intel_syntax)
15538         {
15539           if (!active_seg_prefix)
15540             {
15541               oappend (names_seg[ds_reg - es_reg]);
15542               oappend (":");
15543             }
15544           print_operand_value (scratchbuf, 1, disp & 0xffff);
15545           oappend (scratchbuf);
15546         }
15547     }
15548   if (vex.evex && vex.b
15549       && (bytemode == x_mode
15550           || bytemode == xmmq_mode
15551           || bytemode == evex_half_bcst_xmmq_mode))
15552     {
15553       if (vex.w
15554           || bytemode == xmmq_mode
15555           || bytemode == evex_half_bcst_xmmq_mode)
15556         {
15557           switch (vex.length)
15558             {
15559             case 128:
15560               oappend ("{1to2}");
15561               break;
15562             case 256:
15563               oappend ("{1to4}");
15564               break;
15565             case 512:
15566               oappend ("{1to8}");
15567               break;
15568             default:
15569               abort ();
15570             }
15571         }
15572       else
15573         {
15574           switch (vex.length)
15575             {
15576             case 128:
15577               oappend ("{1to4}");
15578               break;
15579             case 256:
15580               oappend ("{1to8}");
15581               break;
15582             case 512:
15583               oappend ("{1to16}");
15584               break;
15585             default:
15586               abort ();
15587             }
15588         }
15589     }
15590 }
15591
15592 static void
15593 OP_E (int bytemode, int sizeflag)
15594 {
15595   /* Skip mod/rm byte.  */
15596   MODRM_CHECK;
15597   codep++;
15598
15599   if (modrm.mod == 3)
15600     OP_E_register (bytemode, sizeflag);
15601   else
15602     OP_E_memory (bytemode, sizeflag);
15603 }
15604
15605 static void
15606 OP_G (int bytemode, int sizeflag)
15607 {
15608   int add = 0;
15609   USED_REX (REX_R);
15610   if (rex & REX_R)
15611     add += 8;
15612   switch (bytemode)
15613     {
15614     case b_mode:
15615       USED_REX (0);
15616       if (rex)
15617         oappend (names8rex[modrm.reg + add]);
15618       else
15619         oappend (names8[modrm.reg + add]);
15620       break;
15621     case w_mode:
15622       oappend (names16[modrm.reg + add]);
15623       break;
15624     case d_mode:
15625     case db_mode:
15626     case dw_mode:
15627       oappend (names32[modrm.reg + add]);
15628       break;
15629     case q_mode:
15630       oappend (names64[modrm.reg + add]);
15631       break;
15632     case bnd_mode:
15633       if (modrm.reg > 0x3)
15634         {
15635           oappend ("(bad)");
15636           return;
15637         }
15638       oappend (names_bnd[modrm.reg]);
15639       break;
15640     case v_mode:
15641     case dq_mode:
15642     case dqb_mode:
15643     case dqd_mode:
15644     case dqw_mode:
15645       USED_REX (REX_W);
15646       if (rex & REX_W)
15647         oappend (names64[modrm.reg + add]);
15648       else
15649         {
15650           if ((sizeflag & DFLAG) || bytemode != v_mode)
15651             oappend (names32[modrm.reg + add]);
15652           else
15653             oappend (names16[modrm.reg + add]);
15654           used_prefixes |= (prefixes & PREFIX_DATA);
15655         }
15656       break;
15657     case m_mode:
15658       if (address_mode == mode_64bit)
15659         oappend (names64[modrm.reg + add]);
15660       else
15661         oappend (names32[modrm.reg + add]);
15662       break;
15663     case mask_bd_mode:
15664     case mask_mode:
15665       if ((modrm.reg + add) > 0x7)
15666         {
15667           oappend ("(bad)");
15668           return;
15669         }
15670       oappend (names_mask[modrm.reg + add]);
15671       break;
15672     default:
15673       oappend (INTERNAL_DISASSEMBLER_ERROR);
15674       break;
15675     }
15676 }
15677
15678 static bfd_vma
15679 get64 (void)
15680 {
15681   bfd_vma x;
15682 #ifdef BFD64
15683   unsigned int a;
15684   unsigned int b;
15685
15686   FETCH_DATA (the_info, codep + 8);
15687   a = *codep++ & 0xff;
15688   a |= (*codep++ & 0xff) << 8;
15689   a |= (*codep++ & 0xff) << 16;
15690   a |= (*codep++ & 0xffu) << 24;
15691   b = *codep++ & 0xff;
15692   b |= (*codep++ & 0xff) << 8;
15693   b |= (*codep++ & 0xff) << 16;
15694   b |= (*codep++ & 0xffu) << 24;
15695   x = a + ((bfd_vma) b << 32);
15696 #else
15697   abort ();
15698   x = 0;
15699 #endif
15700   return x;
15701 }
15702
15703 static bfd_signed_vma
15704 get32 (void)
15705 {
15706   bfd_signed_vma x = 0;
15707
15708   FETCH_DATA (the_info, codep + 4);
15709   x = *codep++ & (bfd_signed_vma) 0xff;
15710   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15711   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15712   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15713   return x;
15714 }
15715
15716 static bfd_signed_vma
15717 get32s (void)
15718 {
15719   bfd_signed_vma x = 0;
15720
15721   FETCH_DATA (the_info, codep + 4);
15722   x = *codep++ & (bfd_signed_vma) 0xff;
15723   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15724   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15725   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15726
15727   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15728
15729   return x;
15730 }
15731
15732 static int
15733 get16 (void)
15734 {
15735   int x = 0;
15736
15737   FETCH_DATA (the_info, codep + 2);
15738   x = *codep++ & 0xff;
15739   x |= (*codep++ & 0xff) << 8;
15740   return x;
15741 }
15742
15743 static void
15744 set_op (bfd_vma op, int riprel)
15745 {
15746   op_index[op_ad] = op_ad;
15747   if (address_mode == mode_64bit)
15748     {
15749       op_address[op_ad] = op;
15750       op_riprel[op_ad] = riprel;
15751     }
15752   else
15753     {
15754       /* Mask to get a 32-bit address.  */
15755       op_address[op_ad] = op & 0xffffffff;
15756       op_riprel[op_ad] = riprel & 0xffffffff;
15757     }
15758 }
15759
15760 static void
15761 OP_REG (int code, int sizeflag)
15762 {
15763   const char *s;
15764   int add;
15765
15766   switch (code)
15767     {
15768     case es_reg: case ss_reg: case cs_reg:
15769     case ds_reg: case fs_reg: case gs_reg:
15770       oappend (names_seg[code - es_reg]);
15771       return;
15772     }
15773
15774   USED_REX (REX_B);
15775   if (rex & REX_B)
15776     add = 8;
15777   else
15778     add = 0;
15779
15780   switch (code)
15781     {
15782     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15783     case sp_reg: case bp_reg: case si_reg: case di_reg:
15784       s = names16[code - ax_reg + add];
15785       break;
15786     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15787     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15788       USED_REX (0);
15789       if (rex)
15790         s = names8rex[code - al_reg + add];
15791       else
15792         s = names8[code - al_reg];
15793       break;
15794     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15795     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15796       if (address_mode == mode_64bit
15797           && ((sizeflag & DFLAG) || (rex & REX_W)))
15798         {
15799           s = names64[code - rAX_reg + add];
15800           break;
15801         }
15802       code += eAX_reg - rAX_reg;
15803       /* Fall through.  */
15804     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15805     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15806       USED_REX (REX_W);
15807       if (rex & REX_W)
15808         s = names64[code - eAX_reg + add];
15809       else
15810         {
15811           if (sizeflag & DFLAG)
15812             s = names32[code - eAX_reg + add];
15813           else
15814             s = names16[code - eAX_reg + add];
15815           used_prefixes |= (prefixes & PREFIX_DATA);
15816         }
15817       break;
15818     default:
15819       s = INTERNAL_DISASSEMBLER_ERROR;
15820       break;
15821     }
15822   oappend (s);
15823 }
15824
15825 static void
15826 OP_IMREG (int code, int sizeflag)
15827 {
15828   const char *s;
15829
15830   switch (code)
15831     {
15832     case indir_dx_reg:
15833       if (intel_syntax)
15834         s = "dx";
15835       else
15836         s = "(%dx)";
15837       break;
15838     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15839     case sp_reg: case bp_reg: case si_reg: case di_reg:
15840       s = names16[code - ax_reg];
15841       break;
15842     case es_reg: case ss_reg: case cs_reg:
15843     case ds_reg: case fs_reg: case gs_reg:
15844       s = names_seg[code - es_reg];
15845       break;
15846     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15847     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15848       USED_REX (0);
15849       if (rex)
15850         s = names8rex[code - al_reg];
15851       else
15852         s = names8[code - al_reg];
15853       break;
15854     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15855     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15856       USED_REX (REX_W);
15857       if (rex & REX_W)
15858         s = names64[code - eAX_reg];
15859       else
15860         {
15861           if (sizeflag & DFLAG)
15862             s = names32[code - eAX_reg];
15863           else
15864             s = names16[code - eAX_reg];
15865           used_prefixes |= (prefixes & PREFIX_DATA);
15866         }
15867       break;
15868     case z_mode_ax_reg:
15869       if ((rex & REX_W) || (sizeflag & DFLAG))
15870         s = *names32;
15871       else
15872         s = *names16;
15873       if (!(rex & REX_W))
15874         used_prefixes |= (prefixes & PREFIX_DATA);
15875       break;
15876     default:
15877       s = INTERNAL_DISASSEMBLER_ERROR;
15878       break;
15879     }
15880   oappend (s);
15881 }
15882
15883 static void
15884 OP_I (int bytemode, int sizeflag)
15885 {
15886   bfd_signed_vma op;
15887   bfd_signed_vma mask = -1;
15888
15889   switch (bytemode)
15890     {
15891     case b_mode:
15892       FETCH_DATA (the_info, codep + 1);
15893       op = *codep++;
15894       mask = 0xff;
15895       break;
15896     case q_mode:
15897       if (address_mode == mode_64bit)
15898         {
15899           op = get32s ();
15900           break;
15901         }
15902       /* Fall through.  */
15903     case v_mode:
15904       USED_REX (REX_W);
15905       if (rex & REX_W)
15906         op = get32s ();
15907       else
15908         {
15909           if (sizeflag & DFLAG)
15910             {
15911               op = get32 ();
15912               mask = 0xffffffff;
15913             }
15914           else
15915             {
15916               op = get16 ();
15917               mask = 0xfffff;
15918             }
15919           used_prefixes |= (prefixes & PREFIX_DATA);
15920         }
15921       break;
15922     case w_mode:
15923       mask = 0xfffff;
15924       op = get16 ();
15925       break;
15926     case const_1_mode:
15927       if (intel_syntax)
15928         oappend ("1");
15929       return;
15930     default:
15931       oappend (INTERNAL_DISASSEMBLER_ERROR);
15932       return;
15933     }
15934
15935   op &= mask;
15936   scratchbuf[0] = '$';
15937   print_operand_value (scratchbuf + 1, 1, op);
15938   oappend_maybe_intel (scratchbuf);
15939   scratchbuf[0] = '\0';
15940 }
15941
15942 static void
15943 OP_I64 (int bytemode, int sizeflag)
15944 {
15945   bfd_signed_vma op;
15946   bfd_signed_vma mask = -1;
15947
15948   if (address_mode != mode_64bit)
15949     {
15950       OP_I (bytemode, sizeflag);
15951       return;
15952     }
15953
15954   switch (bytemode)
15955     {
15956     case b_mode:
15957       FETCH_DATA (the_info, codep + 1);
15958       op = *codep++;
15959       mask = 0xff;
15960       break;
15961     case v_mode:
15962       USED_REX (REX_W);
15963       if (rex & REX_W)
15964         op = get64 ();
15965       else
15966         {
15967           if (sizeflag & DFLAG)
15968             {
15969               op = get32 ();
15970               mask = 0xffffffff;
15971             }
15972           else
15973             {
15974               op = get16 ();
15975               mask = 0xfffff;
15976             }
15977           used_prefixes |= (prefixes & PREFIX_DATA);
15978         }
15979       break;
15980     case w_mode:
15981       mask = 0xfffff;
15982       op = get16 ();
15983       break;
15984     default:
15985       oappend (INTERNAL_DISASSEMBLER_ERROR);
15986       return;
15987     }
15988
15989   op &= mask;
15990   scratchbuf[0] = '$';
15991   print_operand_value (scratchbuf + 1, 1, op);
15992   oappend_maybe_intel (scratchbuf);
15993   scratchbuf[0] = '\0';
15994 }
15995
15996 static void
15997 OP_sI (int bytemode, int sizeflag)
15998 {
15999   bfd_signed_vma op;
16000
16001   switch (bytemode)
16002     {
16003     case b_mode:
16004     case b_T_mode:
16005       FETCH_DATA (the_info, codep + 1);
16006       op = *codep++;
16007       if ((op & 0x80) != 0)
16008         op -= 0x100;
16009       if (bytemode == b_T_mode)
16010         {
16011           if (address_mode != mode_64bit
16012               || !((sizeflag & DFLAG) || (rex & REX_W)))
16013             {
16014               /* The operand-size prefix is overridden by a REX prefix.  */
16015               if ((sizeflag & DFLAG) || (rex & REX_W))
16016                 op &= 0xffffffff;
16017               else
16018                 op &= 0xffff;
16019           }
16020         }
16021       else
16022         {
16023           if (!(rex & REX_W))
16024             {
16025               if (sizeflag & DFLAG)
16026                 op &= 0xffffffff;
16027               else
16028                 op &= 0xffff;
16029             }
16030         }
16031       break;
16032     case v_mode:
16033       /* The operand-size prefix is overridden by a REX prefix.  */
16034       if ((sizeflag & DFLAG) || (rex & REX_W))
16035         op = get32s ();
16036       else
16037         op = get16 ();
16038       break;
16039     default:
16040       oappend (INTERNAL_DISASSEMBLER_ERROR);
16041       return;
16042     }
16043
16044   scratchbuf[0] = '$';
16045   print_operand_value (scratchbuf + 1, 1, op);
16046   oappend_maybe_intel (scratchbuf);
16047 }
16048
16049 static void
16050 OP_J (int bytemode, int sizeflag)
16051 {
16052   bfd_vma disp;
16053   bfd_vma mask = -1;
16054   bfd_vma segment = 0;
16055
16056   switch (bytemode)
16057     {
16058     case b_mode:
16059       FETCH_DATA (the_info, codep + 1);
16060       disp = *codep++;
16061       if ((disp & 0x80) != 0)
16062         disp -= 0x100;
16063       break;
16064     case v_mode:
16065       if (isa64 == amd64)
16066         USED_REX (REX_W);
16067       if ((sizeflag & DFLAG)
16068           || (address_mode == mode_64bit
16069               && (isa64 != amd64 || (rex & REX_W))))
16070         disp = get32s ();
16071       else
16072         {
16073           disp = get16 ();
16074           if ((disp & 0x8000) != 0)
16075             disp -= 0x10000;
16076           /* In 16bit mode, address is wrapped around at 64k within
16077              the same segment.  Otherwise, a data16 prefix on a jump
16078              instruction means that the pc is masked to 16 bits after
16079              the displacement is added!  */
16080           mask = 0xffff;
16081           if ((prefixes & PREFIX_DATA) == 0)
16082             segment = ((start_pc + (codep - start_codep))
16083                        & ~((bfd_vma) 0xffff));
16084         }
16085       if (address_mode != mode_64bit
16086           || (isa64 == amd64 && !(rex & REX_W)))
16087         used_prefixes |= (prefixes & PREFIX_DATA);
16088       break;
16089     default:
16090       oappend (INTERNAL_DISASSEMBLER_ERROR);
16091       return;
16092     }
16093   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16094   set_op (disp, 0);
16095   print_operand_value (scratchbuf, 1, disp);
16096   oappend (scratchbuf);
16097 }
16098
16099 static void
16100 OP_SEG (int bytemode, int sizeflag)
16101 {
16102   if (bytemode == w_mode)
16103     oappend (names_seg[modrm.reg]);
16104   else
16105     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16106 }
16107
16108 static void
16109 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16110 {
16111   int seg, offset;
16112
16113   if (sizeflag & DFLAG)
16114     {
16115       offset = get32 ();
16116       seg = get16 ();
16117     }
16118   else
16119     {
16120       offset = get16 ();
16121       seg = get16 ();
16122     }
16123   used_prefixes |= (prefixes & PREFIX_DATA);
16124   if (intel_syntax)
16125     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16126   else
16127     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16128   oappend (scratchbuf);
16129 }
16130
16131 static void
16132 OP_OFF (int bytemode, int sizeflag)
16133 {
16134   bfd_vma off;
16135
16136   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16137     intel_operand_size (bytemode, sizeflag);
16138   append_seg ();
16139
16140   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16141     off = get32 ();
16142   else
16143     off = get16 ();
16144
16145   if (intel_syntax)
16146     {
16147       if (!active_seg_prefix)
16148         {
16149           oappend (names_seg[ds_reg - es_reg]);
16150           oappend (":");
16151         }
16152     }
16153   print_operand_value (scratchbuf, 1, off);
16154   oappend (scratchbuf);
16155 }
16156
16157 static void
16158 OP_OFF64 (int bytemode, int sizeflag)
16159 {
16160   bfd_vma off;
16161
16162   if (address_mode != mode_64bit
16163       || (prefixes & PREFIX_ADDR))
16164     {
16165       OP_OFF (bytemode, sizeflag);
16166       return;
16167     }
16168
16169   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16170     intel_operand_size (bytemode, sizeflag);
16171   append_seg ();
16172
16173   off = get64 ();
16174
16175   if (intel_syntax)
16176     {
16177       if (!active_seg_prefix)
16178         {
16179           oappend (names_seg[ds_reg - es_reg]);
16180           oappend (":");
16181         }
16182     }
16183   print_operand_value (scratchbuf, 1, off);
16184   oappend (scratchbuf);
16185 }
16186
16187 static void
16188 ptr_reg (int code, int sizeflag)
16189 {
16190   const char *s;
16191
16192   *obufp++ = open_char;
16193   used_prefixes |= (prefixes & PREFIX_ADDR);
16194   if (address_mode == mode_64bit)
16195     {
16196       if (!(sizeflag & AFLAG))
16197         s = names32[code - eAX_reg];
16198       else
16199         s = names64[code - eAX_reg];
16200     }
16201   else if (sizeflag & AFLAG)
16202     s = names32[code - eAX_reg];
16203   else
16204     s = names16[code - eAX_reg];
16205   oappend (s);
16206   *obufp++ = close_char;
16207   *obufp = 0;
16208 }
16209
16210 static void
16211 OP_ESreg (int code, int sizeflag)
16212 {
16213   if (intel_syntax)
16214     {
16215       switch (codep[-1])
16216         {
16217         case 0x6d:      /* insw/insl */
16218           intel_operand_size (z_mode, sizeflag);
16219           break;
16220         case 0xa5:      /* movsw/movsl/movsq */
16221         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16222         case 0xab:      /* stosw/stosl */
16223         case 0xaf:      /* scasw/scasl */
16224           intel_operand_size (v_mode, sizeflag);
16225           break;
16226         default:
16227           intel_operand_size (b_mode, sizeflag);
16228         }
16229     }
16230   oappend_maybe_intel ("%es:");
16231   ptr_reg (code, sizeflag);
16232 }
16233
16234 static void
16235 OP_DSreg (int code, int sizeflag)
16236 {
16237   if (intel_syntax)
16238     {
16239       switch (codep[-1])
16240         {
16241         case 0x6f:      /* outsw/outsl */
16242           intel_operand_size (z_mode, sizeflag);
16243           break;
16244         case 0xa5:      /* movsw/movsl/movsq */
16245         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16246         case 0xad:      /* lodsw/lodsl/lodsq */
16247           intel_operand_size (v_mode, sizeflag);
16248           break;
16249         default:
16250           intel_operand_size (b_mode, sizeflag);
16251         }
16252     }
16253   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16254      default segment register DS is printed.  */
16255   if (!active_seg_prefix)
16256     active_seg_prefix = PREFIX_DS;
16257   append_seg ();
16258   ptr_reg (code, sizeflag);
16259 }
16260
16261 static void
16262 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16263 {
16264   int add;
16265   if (rex & REX_R)
16266     {
16267       USED_REX (REX_R);
16268       add = 8;
16269     }
16270   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16271     {
16272       all_prefixes[last_lock_prefix] = 0;
16273       used_prefixes |= PREFIX_LOCK;
16274       add = 8;
16275     }
16276   else
16277     add = 0;
16278   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16279   oappend_maybe_intel (scratchbuf);
16280 }
16281
16282 static void
16283 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16284 {
16285   int add;
16286   USED_REX (REX_R);
16287   if (rex & REX_R)
16288     add = 8;
16289   else
16290     add = 0;
16291   if (intel_syntax)
16292     sprintf (scratchbuf, "db%d", modrm.reg + add);
16293   else
16294     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16295   oappend (scratchbuf);
16296 }
16297
16298 static void
16299 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16300 {
16301   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16302   oappend_maybe_intel (scratchbuf);
16303 }
16304
16305 static void
16306 OP_R (int bytemode, int sizeflag)
16307 {
16308   /* Skip mod/rm byte.  */
16309   MODRM_CHECK;
16310   codep++;
16311   OP_E_register (bytemode, sizeflag);
16312 }
16313
16314 static void
16315 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16316 {
16317   int reg = modrm.reg;
16318   const char **names;
16319
16320   used_prefixes |= (prefixes & PREFIX_DATA);
16321   if (prefixes & PREFIX_DATA)
16322     {
16323       names = names_xmm;
16324       USED_REX (REX_R);
16325       if (rex & REX_R)
16326         reg += 8;
16327     }
16328   else
16329     names = names_mm;
16330   oappend (names[reg]);
16331 }
16332
16333 static void
16334 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16335 {
16336   int reg = modrm.reg;
16337   const char **names;
16338
16339   USED_REX (REX_R);
16340   if (rex & REX_R)
16341     reg += 8;
16342   if (vex.evex)
16343     {
16344       if (!vex.r)
16345         reg += 16;
16346     }
16347
16348   if (need_vex
16349       && bytemode != xmm_mode
16350       && bytemode != xmmq_mode
16351       && bytemode != evex_half_bcst_xmmq_mode
16352       && bytemode != ymm_mode
16353       && bytemode != scalar_mode)
16354     {
16355       switch (vex.length)
16356         {
16357         case 128:
16358           names = names_xmm;
16359           break;
16360         case 256:
16361           if (vex.w
16362               || (bytemode != vex_vsib_q_w_dq_mode
16363                   && bytemode != vex_vsib_q_w_d_mode))
16364             names = names_ymm;
16365           else
16366             names = names_xmm;
16367           break;
16368         case 512:
16369           names = names_zmm;
16370           break;
16371         default:
16372           abort ();
16373         }
16374     }
16375   else if (bytemode == xmmq_mode
16376            || bytemode == evex_half_bcst_xmmq_mode)
16377     {
16378       switch (vex.length)
16379         {
16380         case 128:
16381         case 256:
16382           names = names_xmm;
16383           break;
16384         case 512:
16385           names = names_ymm;
16386           break;
16387         default:
16388           abort ();
16389         }
16390     }
16391   else if (bytemode == ymm_mode)
16392     names = names_ymm;
16393   else
16394     names = names_xmm;
16395   oappend (names[reg]);
16396 }
16397
16398 static void
16399 OP_EM (int bytemode, int sizeflag)
16400 {
16401   int reg;
16402   const char **names;
16403
16404   if (modrm.mod != 3)
16405     {
16406       if (intel_syntax
16407           && (bytemode == v_mode || bytemode == v_swap_mode))
16408         {
16409           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16410           used_prefixes |= (prefixes & PREFIX_DATA);
16411         }
16412       OP_E (bytemode, sizeflag);
16413       return;
16414     }
16415
16416   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16417     swap_operand ();
16418
16419   /* Skip mod/rm byte.  */
16420   MODRM_CHECK;
16421   codep++;
16422   used_prefixes |= (prefixes & PREFIX_DATA);
16423   reg = modrm.rm;
16424   if (prefixes & PREFIX_DATA)
16425     {
16426       names = names_xmm;
16427       USED_REX (REX_B);
16428       if (rex & REX_B)
16429         reg += 8;
16430     }
16431   else
16432     names = names_mm;
16433   oappend (names[reg]);
16434 }
16435
16436 /* cvt* are the only instructions in sse2 which have
16437    both SSE and MMX operands and also have 0x66 prefix
16438    in their opcode. 0x66 was originally used to differentiate
16439    between SSE and MMX instruction(operands). So we have to handle the
16440    cvt* separately using OP_EMC and OP_MXC */
16441 static void
16442 OP_EMC (int bytemode, int sizeflag)
16443 {
16444   if (modrm.mod != 3)
16445     {
16446       if (intel_syntax && bytemode == v_mode)
16447         {
16448           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16449           used_prefixes |= (prefixes & PREFIX_DATA);
16450         }
16451       OP_E (bytemode, sizeflag);
16452       return;
16453     }
16454
16455   /* Skip mod/rm byte.  */
16456   MODRM_CHECK;
16457   codep++;
16458   used_prefixes |= (prefixes & PREFIX_DATA);
16459   oappend (names_mm[modrm.rm]);
16460 }
16461
16462 static void
16463 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16464 {
16465   used_prefixes |= (prefixes & PREFIX_DATA);
16466   oappend (names_mm[modrm.reg]);
16467 }
16468
16469 static void
16470 OP_EX (int bytemode, int sizeflag)
16471 {
16472   int reg;
16473   const char **names;
16474
16475   /* Skip mod/rm byte.  */
16476   MODRM_CHECK;
16477   codep++;
16478
16479   if (modrm.mod != 3)
16480     {
16481       OP_E_memory (bytemode, sizeflag);
16482       return;
16483     }
16484
16485   reg = modrm.rm;
16486   USED_REX (REX_B);
16487   if (rex & REX_B)
16488     reg += 8;
16489   if (vex.evex)
16490     {
16491       USED_REX (REX_X);
16492       if ((rex & REX_X))
16493         reg += 16;
16494     }
16495
16496   if ((sizeflag & SUFFIX_ALWAYS)
16497       && (bytemode == x_swap_mode
16498           || bytemode == d_swap_mode
16499           || bytemode == d_scalar_swap_mode
16500           || bytemode == q_swap_mode
16501           || bytemode == q_scalar_swap_mode))
16502     swap_operand ();
16503
16504   if (need_vex
16505       && bytemode != xmm_mode
16506       && bytemode != xmmdw_mode
16507       && bytemode != xmmqd_mode
16508       && bytemode != xmm_mb_mode
16509       && bytemode != xmm_mw_mode
16510       && bytemode != xmm_md_mode
16511       && bytemode != xmm_mq_mode
16512       && bytemode != xmm_mdq_mode
16513       && bytemode != xmmq_mode
16514       && bytemode != evex_half_bcst_xmmq_mode
16515       && bytemode != ymm_mode
16516       && bytemode != d_scalar_mode
16517       && bytemode != d_scalar_swap_mode
16518       && bytemode != q_scalar_mode
16519       && bytemode != q_scalar_swap_mode
16520       && bytemode != vex_scalar_w_dq_mode)
16521     {
16522       switch (vex.length)
16523         {
16524         case 128:
16525           names = names_xmm;
16526           break;
16527         case 256:
16528           names = names_ymm;
16529           break;
16530         case 512:
16531           names = names_zmm;
16532           break;
16533         default:
16534           abort ();
16535         }
16536     }
16537   else if (bytemode == xmmq_mode
16538            || bytemode == evex_half_bcst_xmmq_mode)
16539     {
16540       switch (vex.length)
16541         {
16542         case 128:
16543         case 256:
16544           names = names_xmm;
16545           break;
16546         case 512:
16547           names = names_ymm;
16548           break;
16549         default:
16550           abort ();
16551         }
16552     }
16553   else if (bytemode == ymm_mode)
16554     names = names_ymm;
16555   else
16556     names = names_xmm;
16557   oappend (names[reg]);
16558 }
16559
16560 static void
16561 OP_MS (int bytemode, int sizeflag)
16562 {
16563   if (modrm.mod == 3)
16564     OP_EM (bytemode, sizeflag);
16565   else
16566     BadOp ();
16567 }
16568
16569 static void
16570 OP_XS (int bytemode, int sizeflag)
16571 {
16572   if (modrm.mod == 3)
16573     OP_EX (bytemode, sizeflag);
16574   else
16575     BadOp ();
16576 }
16577
16578 static void
16579 OP_M (int bytemode, int sizeflag)
16580 {
16581   if (modrm.mod == 3)
16582     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16583     BadOp ();
16584   else
16585     OP_E (bytemode, sizeflag);
16586 }
16587
16588 static void
16589 OP_0f07 (int bytemode, int sizeflag)
16590 {
16591   if (modrm.mod != 3 || modrm.rm != 0)
16592     BadOp ();
16593   else
16594     OP_E (bytemode, sizeflag);
16595 }
16596
16597 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16598    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16599
16600 static void
16601 NOP_Fixup1 (int bytemode, int sizeflag)
16602 {
16603   if ((prefixes & PREFIX_DATA) != 0
16604       || (rex != 0
16605           && rex != 0x48
16606           && address_mode == mode_64bit))
16607     OP_REG (bytemode, sizeflag);
16608   else
16609     strcpy (obuf, "nop");
16610 }
16611
16612 static void
16613 NOP_Fixup2 (int bytemode, int sizeflag)
16614 {
16615   if ((prefixes & PREFIX_DATA) != 0
16616       || (rex != 0
16617           && rex != 0x48
16618           && address_mode == mode_64bit))
16619     OP_IMREG (bytemode, sizeflag);
16620 }
16621
16622 static const char *const Suffix3DNow[] = {
16623 /* 00 */        NULL,           NULL,           NULL,           NULL,
16624 /* 04 */        NULL,           NULL,           NULL,           NULL,
16625 /* 08 */        NULL,           NULL,           NULL,           NULL,
16626 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16627 /* 10 */        NULL,           NULL,           NULL,           NULL,
16628 /* 14 */        NULL,           NULL,           NULL,           NULL,
16629 /* 18 */        NULL,           NULL,           NULL,           NULL,
16630 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16631 /* 20 */        NULL,           NULL,           NULL,           NULL,
16632 /* 24 */        NULL,           NULL,           NULL,           NULL,
16633 /* 28 */        NULL,           NULL,           NULL,           NULL,
16634 /* 2C */        NULL,           NULL,           NULL,           NULL,
16635 /* 30 */        NULL,           NULL,           NULL,           NULL,
16636 /* 34 */        NULL,           NULL,           NULL,           NULL,
16637 /* 38 */        NULL,           NULL,           NULL,           NULL,
16638 /* 3C */        NULL,           NULL,           NULL,           NULL,
16639 /* 40 */        NULL,           NULL,           NULL,           NULL,
16640 /* 44 */        NULL,           NULL,           NULL,           NULL,
16641 /* 48 */        NULL,           NULL,           NULL,           NULL,
16642 /* 4C */        NULL,           NULL,           NULL,           NULL,
16643 /* 50 */        NULL,           NULL,           NULL,           NULL,
16644 /* 54 */        NULL,           NULL,           NULL,           NULL,
16645 /* 58 */        NULL,           NULL,           NULL,           NULL,
16646 /* 5C */        NULL,           NULL,           NULL,           NULL,
16647 /* 60 */        NULL,           NULL,           NULL,           NULL,
16648 /* 64 */        NULL,           NULL,           NULL,           NULL,
16649 /* 68 */        NULL,           NULL,           NULL,           NULL,
16650 /* 6C */        NULL,           NULL,           NULL,           NULL,
16651 /* 70 */        NULL,           NULL,           NULL,           NULL,
16652 /* 74 */        NULL,           NULL,           NULL,           NULL,
16653 /* 78 */        NULL,           NULL,           NULL,           NULL,
16654 /* 7C */        NULL,           NULL,           NULL,           NULL,
16655 /* 80 */        NULL,           NULL,           NULL,           NULL,
16656 /* 84 */        NULL,           NULL,           NULL,           NULL,
16657 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16658 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16659 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16660 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16661 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16662 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16663 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16664 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16665 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16666 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16667 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16668 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16669 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16670 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16671 /* C0 */        NULL,           NULL,           NULL,           NULL,
16672 /* C4 */        NULL,           NULL,           NULL,           NULL,
16673 /* C8 */        NULL,           NULL,           NULL,           NULL,
16674 /* CC */        NULL,           NULL,           NULL,           NULL,
16675 /* D0 */        NULL,           NULL,           NULL,           NULL,
16676 /* D4 */        NULL,           NULL,           NULL,           NULL,
16677 /* D8 */        NULL,           NULL,           NULL,           NULL,
16678 /* DC */        NULL,           NULL,           NULL,           NULL,
16679 /* E0 */        NULL,           NULL,           NULL,           NULL,
16680 /* E4 */        NULL,           NULL,           NULL,           NULL,
16681 /* E8 */        NULL,           NULL,           NULL,           NULL,
16682 /* EC */        NULL,           NULL,           NULL,           NULL,
16683 /* F0 */        NULL,           NULL,           NULL,           NULL,
16684 /* F4 */        NULL,           NULL,           NULL,           NULL,
16685 /* F8 */        NULL,           NULL,           NULL,           NULL,
16686 /* FC */        NULL,           NULL,           NULL,           NULL,
16687 };
16688
16689 static void
16690 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16691 {
16692   const char *mnemonic;
16693
16694   FETCH_DATA (the_info, codep + 1);
16695   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16696      place where an 8-bit immediate would normally go.  ie. the last
16697      byte of the instruction.  */
16698   obufp = mnemonicendp;
16699   mnemonic = Suffix3DNow[*codep++ & 0xff];
16700   if (mnemonic)
16701     oappend (mnemonic);
16702   else
16703     {
16704       /* Since a variable sized modrm/sib chunk is between the start
16705          of the opcode (0x0f0f) and the opcode suffix, we need to do
16706          all the modrm processing first, and don't know until now that
16707          we have a bad opcode.  This necessitates some cleaning up.  */
16708       op_out[0][0] = '\0';
16709       op_out[1][0] = '\0';
16710       BadOp ();
16711     }
16712   mnemonicendp = obufp;
16713 }
16714
16715 static struct op simd_cmp_op[] =
16716 {
16717   { STRING_COMMA_LEN ("eq") },
16718   { STRING_COMMA_LEN ("lt") },
16719   { STRING_COMMA_LEN ("le") },
16720   { STRING_COMMA_LEN ("unord") },
16721   { STRING_COMMA_LEN ("neq") },
16722   { STRING_COMMA_LEN ("nlt") },
16723   { STRING_COMMA_LEN ("nle") },
16724   { STRING_COMMA_LEN ("ord") }
16725 };
16726
16727 static void
16728 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16729 {
16730   unsigned int cmp_type;
16731
16732   FETCH_DATA (the_info, codep + 1);
16733   cmp_type = *codep++ & 0xff;
16734   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16735     {
16736       char suffix [3];
16737       char *p = mnemonicendp - 2;
16738       suffix[0] = p[0];
16739       suffix[1] = p[1];
16740       suffix[2] = '\0';
16741       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16742       mnemonicendp += simd_cmp_op[cmp_type].len;
16743     }
16744   else
16745     {
16746       /* We have a reserved extension byte.  Output it directly.  */
16747       scratchbuf[0] = '$';
16748       print_operand_value (scratchbuf + 1, 1, cmp_type);
16749       oappend_maybe_intel (scratchbuf);
16750       scratchbuf[0] = '\0';
16751     }
16752 }
16753
16754 static void
16755 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16756           int sizeflag ATTRIBUTE_UNUSED)
16757 {
16758   /* mwaitx %eax,%ecx,%ebx */
16759   if (!intel_syntax)
16760     {
16761       const char **names = (address_mode == mode_64bit
16762                             ? names64 : names32);
16763       strcpy (op_out[0], names[0]);
16764       strcpy (op_out[1], names[1]);
16765       strcpy (op_out[2], names[3]);
16766       two_source_ops = 1;
16767     }
16768   /* Skip mod/rm byte.  */
16769   MODRM_CHECK;
16770   codep++;
16771 }
16772
16773 static void
16774 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16775           int sizeflag ATTRIBUTE_UNUSED)
16776 {
16777   /* mwait %eax,%ecx  */
16778   if (!intel_syntax)
16779     {
16780       const char **names = (address_mode == mode_64bit
16781                             ? names64 : names32);
16782       strcpy (op_out[0], names[0]);
16783       strcpy (op_out[1], names[1]);
16784       two_source_ops = 1;
16785     }
16786   /* Skip mod/rm byte.  */
16787   MODRM_CHECK;
16788   codep++;
16789 }
16790
16791 static void
16792 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16793             int sizeflag ATTRIBUTE_UNUSED)
16794 {
16795   /* monitor %eax,%ecx,%edx"  */
16796   if (!intel_syntax)
16797     {
16798       const char **op1_names;
16799       const char **names = (address_mode == mode_64bit
16800                             ? names64 : names32);
16801
16802       if (!(prefixes & PREFIX_ADDR))
16803         op1_names = (address_mode == mode_16bit
16804                      ? names16 : names);
16805       else
16806         {
16807           /* Remove "addr16/addr32".  */
16808           all_prefixes[last_addr_prefix] = 0;
16809           op1_names = (address_mode != mode_32bit
16810                        ? names32 : names16);
16811           used_prefixes |= PREFIX_ADDR;
16812         }
16813       strcpy (op_out[0], op1_names[0]);
16814       strcpy (op_out[1], names[1]);
16815       strcpy (op_out[2], names[2]);
16816       two_source_ops = 1;
16817     }
16818   /* Skip mod/rm byte.  */
16819   MODRM_CHECK;
16820   codep++;
16821 }
16822
16823 static void
16824 BadOp (void)
16825 {
16826   /* Throw away prefixes and 1st. opcode byte.  */
16827   codep = insn_codep + 1;
16828   oappend ("(bad)");
16829 }
16830
16831 static void
16832 REP_Fixup (int bytemode, int sizeflag)
16833 {
16834   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16835      lods and stos.  */
16836   if (prefixes & PREFIX_REPZ)
16837     all_prefixes[last_repz_prefix] = REP_PREFIX;
16838
16839   switch (bytemode)
16840     {
16841     case al_reg:
16842     case eAX_reg:
16843     case indir_dx_reg:
16844       OP_IMREG (bytemode, sizeflag);
16845       break;
16846     case eDI_reg:
16847       OP_ESreg (bytemode, sizeflag);
16848       break;
16849     case eSI_reg:
16850       OP_DSreg (bytemode, sizeflag);
16851       break;
16852     default:
16853       abort ();
16854       break;
16855     }
16856 }
16857
16858 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16859    "bnd".  */
16860
16861 static void
16862 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16863 {
16864   if (prefixes & PREFIX_REPNZ)
16865     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16866 }
16867
16868 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16869    "notrack".  */
16870
16871 static void
16872 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16873                int sizeflag ATTRIBUTE_UNUSED)
16874 {
16875   if (active_seg_prefix == PREFIX_DS
16876       && (address_mode != mode_64bit || last_data_prefix < 0))
16877     {
16878       /* NOTRACK prefix is only valid on indirect branch instructions.
16879          NB: DATA prefix is unsupported for Intel64.  */
16880       active_seg_prefix = 0;
16881       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16882     }
16883 }
16884
16885 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16886    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16887  */
16888
16889 static void
16890 HLE_Fixup1 (int bytemode, int sizeflag)
16891 {
16892   if (modrm.mod != 3
16893       && (prefixes & PREFIX_LOCK) != 0)
16894     {
16895       if (prefixes & PREFIX_REPZ)
16896         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16897       if (prefixes & PREFIX_REPNZ)
16898         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16899     }
16900
16901   OP_E (bytemode, sizeflag);
16902 }
16903
16904 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16905    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16906  */
16907
16908 static void
16909 HLE_Fixup2 (int bytemode, int sizeflag)
16910 {
16911   if (modrm.mod != 3)
16912     {
16913       if (prefixes & PREFIX_REPZ)
16914         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16915       if (prefixes & PREFIX_REPNZ)
16916         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16917     }
16918
16919   OP_E (bytemode, sizeflag);
16920 }
16921
16922 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16923    "xrelease" for memory operand.  No check for LOCK prefix.   */
16924
16925 static void
16926 HLE_Fixup3 (int bytemode, int sizeflag)
16927 {
16928   if (modrm.mod != 3
16929       && last_repz_prefix > last_repnz_prefix
16930       && (prefixes & PREFIX_REPZ) != 0)
16931     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16932
16933   OP_E (bytemode, sizeflag);
16934 }
16935
16936 static void
16937 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16938 {
16939   USED_REX (REX_W);
16940   if (rex & REX_W)
16941     {
16942       /* Change cmpxchg8b to cmpxchg16b.  */
16943       char *p = mnemonicendp - 2;
16944       mnemonicendp = stpcpy (p, "16b");
16945       bytemode = o_mode;
16946     }
16947   else if ((prefixes & PREFIX_LOCK) != 0)
16948     {
16949       if (prefixes & PREFIX_REPZ)
16950         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16951       if (prefixes & PREFIX_REPNZ)
16952         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16953     }
16954
16955   OP_M (bytemode, sizeflag);
16956 }
16957
16958 static void
16959 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16960 {
16961   const char **names;
16962
16963   if (need_vex)
16964     {
16965       switch (vex.length)
16966         {
16967         case 128:
16968           names = names_xmm;
16969           break;
16970         case 256:
16971           names = names_ymm;
16972           break;
16973         default:
16974           abort ();
16975         }
16976     }
16977   else
16978     names = names_xmm;
16979   oappend (names[reg]);
16980 }
16981
16982 static void
16983 CRC32_Fixup (int bytemode, int sizeflag)
16984 {
16985   /* Add proper suffix to "crc32".  */
16986   char *p = mnemonicendp;
16987
16988   switch (bytemode)
16989     {
16990     case b_mode:
16991       if (intel_syntax)
16992         goto skip;
16993
16994       *p++ = 'b';
16995       break;
16996     case v_mode:
16997       if (intel_syntax)
16998         goto skip;
16999
17000       USED_REX (REX_W);
17001       if (rex & REX_W)
17002         *p++ = 'q';
17003       else
17004         {
17005           if (sizeflag & DFLAG)
17006             *p++ = 'l';
17007           else
17008             *p++ = 'w';
17009           used_prefixes |= (prefixes & PREFIX_DATA);
17010         }
17011       break;
17012     default:
17013       oappend (INTERNAL_DISASSEMBLER_ERROR);
17014       break;
17015     }
17016   mnemonicendp = p;
17017   *p = '\0';
17018
17019 skip:
17020   if (modrm.mod == 3)
17021     {
17022       int add;
17023
17024       /* Skip mod/rm byte.  */
17025       MODRM_CHECK;
17026       codep++;
17027
17028       USED_REX (REX_B);
17029       add = (rex & REX_B) ? 8 : 0;
17030       if (bytemode == b_mode)
17031         {
17032           USED_REX (0);
17033           if (rex)
17034             oappend (names8rex[modrm.rm + add]);
17035           else
17036             oappend (names8[modrm.rm + add]);
17037         }
17038       else
17039         {
17040           USED_REX (REX_W);
17041           if (rex & REX_W)
17042             oappend (names64[modrm.rm + add]);
17043           else if ((prefixes & PREFIX_DATA))
17044             oappend (names16[modrm.rm + add]);
17045           else
17046             oappend (names32[modrm.rm + add]);
17047         }
17048     }
17049   else
17050     OP_E (bytemode, sizeflag);
17051 }
17052
17053 static void
17054 FXSAVE_Fixup (int bytemode, int sizeflag)
17055 {
17056   /* Add proper suffix to "fxsave" and "fxrstor".  */
17057   USED_REX (REX_W);
17058   if (rex & REX_W)
17059     {
17060       char *p = mnemonicendp;
17061       *p++ = '6';
17062       *p++ = '4';
17063       *p = '\0';
17064       mnemonicendp = p;
17065     }
17066   OP_M (bytemode, sizeflag);
17067 }
17068
17069 static void
17070 PCMPESTR_Fixup (int bytemode, int sizeflag)
17071 {
17072   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
17073   if (!intel_syntax)
17074     {
17075       char *p = mnemonicendp;
17076
17077       USED_REX (REX_W);
17078       if (rex & REX_W)
17079         *p++ = 'q';
17080       else if (sizeflag & SUFFIX_ALWAYS)
17081         *p++ = 'l';
17082
17083       *p = '\0';
17084       mnemonicendp = p;
17085     }
17086
17087   OP_EX (bytemode, sizeflag);
17088 }
17089
17090 /* Display the destination register operand for instructions with
17091    VEX. */
17092
17093 static void
17094 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17095 {
17096   int reg;
17097   const char **names;
17098
17099   if (!need_vex)
17100     abort ();
17101
17102   if (!need_vex_reg)
17103     return;
17104
17105   reg = vex.register_specifier;
17106   if (vex.evex)
17107     {
17108       if (!vex.v)
17109         reg += 16;
17110     }
17111
17112   if (bytemode == vex_scalar_mode)
17113     {
17114       oappend (names_xmm[reg]);
17115       return;
17116     }
17117
17118   switch (vex.length)
17119     {
17120     case 128:
17121       switch (bytemode)
17122         {
17123         case vex_mode:
17124         case vex128_mode:
17125         case vex_vsib_q_w_dq_mode:
17126         case vex_vsib_q_w_d_mode:
17127           names = names_xmm;
17128           break;
17129         case dq_mode:
17130           if (vex.w)
17131             names = names64;
17132           else
17133             names = names32;
17134           break;
17135         case mask_bd_mode:
17136         case mask_mode:
17137           if (reg > 0x7)
17138             {
17139               oappend ("(bad)");
17140               return;
17141             }
17142           names = names_mask;
17143           break;
17144         default:
17145           abort ();
17146           return;
17147         }
17148       break;
17149     case 256:
17150       switch (bytemode)
17151         {
17152         case vex_mode:
17153         case vex256_mode:
17154           names = names_ymm;
17155           break;
17156         case vex_vsib_q_w_dq_mode:
17157         case vex_vsib_q_w_d_mode:
17158           names = vex.w ? names_ymm : names_xmm;
17159           break;
17160         case mask_bd_mode:
17161         case mask_mode:
17162           if (reg > 0x7)
17163             {
17164               oappend ("(bad)");
17165               return;
17166             }
17167           names = names_mask;
17168           break;
17169         default:
17170           /* See PR binutils/20893 for a reproducer.  */
17171           oappend ("(bad)");
17172           return;
17173         }
17174       break;
17175     case 512:
17176       names = names_zmm;
17177       break;
17178     default:
17179       abort ();
17180       break;
17181     }
17182   oappend (names[reg]);
17183 }
17184
17185 /* Get the VEX immediate byte without moving codep.  */
17186
17187 static unsigned char
17188 get_vex_imm8 (int sizeflag, int opnum)
17189 {
17190   int bytes_before_imm = 0;
17191
17192   if (modrm.mod != 3)
17193     {
17194       /* There are SIB/displacement bytes.  */
17195       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17196         {
17197           /* 32/64 bit address mode */
17198           int base = modrm.rm;
17199
17200           /* Check SIB byte.  */
17201           if (base == 4)
17202             {
17203               FETCH_DATA (the_info, codep + 1);
17204               base = *codep & 7;
17205               /* When decoding the third source, don't increase
17206                  bytes_before_imm as this has already been incremented
17207                  by one in OP_E_memory while decoding the second
17208                  source operand.  */
17209               if (opnum == 0)
17210                 bytes_before_imm++;
17211             }
17212
17213           /* Don't increase bytes_before_imm when decoding the third source,
17214              it has already been incremented by OP_E_memory while decoding
17215              the second source operand.  */
17216           if (opnum == 0)
17217             {
17218               switch (modrm.mod)
17219                 {
17220                   case 0:
17221                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17222                        SIB == 5, there is a 4 byte displacement.  */
17223                     if (base != 5)
17224                       /* No displacement. */
17225                       break;
17226                     /* Fall through.  */
17227                   case 2:
17228                     /* 4 byte displacement.  */
17229                     bytes_before_imm += 4;
17230                     break;
17231                   case 1:
17232                     /* 1 byte displacement.  */
17233                     bytes_before_imm++;
17234                     break;
17235                 }
17236             }
17237         }
17238       else
17239         {
17240           /* 16 bit address mode */
17241           /* Don't increase bytes_before_imm when decoding the third source,
17242              it has already been incremented by OP_E_memory while decoding
17243              the second source operand.  */
17244           if (opnum == 0)
17245             {
17246               switch (modrm.mod)
17247                 {
17248                 case 0:
17249                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17250                   if (modrm.rm != 6)
17251                     /* No displacement. */
17252                     break;
17253                   /* Fall through.  */
17254                 case 2:
17255                   /* 2 byte displacement.  */
17256                   bytes_before_imm += 2;
17257                   break;
17258                 case 1:
17259                   /* 1 byte displacement: when decoding the third source,
17260                      don't increase bytes_before_imm as this has already
17261                      been incremented by one in OP_E_memory while decoding
17262                      the second source operand.  */
17263                   if (opnum == 0)
17264                     bytes_before_imm++;
17265
17266                   break;
17267                 }
17268             }
17269         }
17270     }
17271
17272   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17273   return codep [bytes_before_imm];
17274 }
17275
17276 static void
17277 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17278 {
17279   const char **names;
17280
17281   if (reg == -1 && modrm.mod != 3)
17282     {
17283       OP_E_memory (bytemode, sizeflag);
17284       return;
17285     }
17286   else
17287     {
17288       if (reg == -1)
17289         {
17290           reg = modrm.rm;
17291           USED_REX (REX_B);
17292           if (rex & REX_B)
17293             reg += 8;
17294         }
17295       else if (reg > 7 && address_mode != mode_64bit)
17296         BadOp ();
17297     }
17298
17299   switch (vex.length)
17300     {
17301     case 128:
17302       names = names_xmm;
17303       break;
17304     case 256:
17305       names = names_ymm;
17306       break;
17307     default:
17308       abort ();
17309     }
17310   oappend (names[reg]);
17311 }
17312
17313 static void
17314 OP_EX_VexImmW (int bytemode, int sizeflag)
17315 {
17316   int reg = -1;
17317   static unsigned char vex_imm8;
17318
17319   if (vex_w_done == 0)
17320     {
17321       vex_w_done = 1;
17322
17323       /* Skip mod/rm byte.  */
17324       MODRM_CHECK;
17325       codep++;
17326
17327       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17328
17329       if (vex.w)
17330           reg = vex_imm8 >> 4;
17331
17332       OP_EX_VexReg (bytemode, sizeflag, reg);
17333     }
17334   else if (vex_w_done == 1)
17335     {
17336       vex_w_done = 2;
17337
17338       if (!vex.w)
17339           reg = vex_imm8 >> 4;
17340
17341       OP_EX_VexReg (bytemode, sizeflag, reg);
17342     }
17343   else
17344     {
17345       /* Output the imm8 directly.  */
17346       scratchbuf[0] = '$';
17347       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17348       oappend_maybe_intel (scratchbuf);
17349       scratchbuf[0] = '\0';
17350       codep++;
17351     }
17352 }
17353
17354 static void
17355 OP_Vex_2src (int bytemode, int sizeflag)
17356 {
17357   if (modrm.mod == 3)
17358     {
17359       int reg = modrm.rm;
17360       USED_REX (REX_B);
17361       if (rex & REX_B)
17362         reg += 8;
17363       oappend (names_xmm[reg]);
17364     }
17365   else
17366     {
17367       if (intel_syntax
17368           && (bytemode == v_mode || bytemode == v_swap_mode))
17369         {
17370           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17371           used_prefixes |= (prefixes & PREFIX_DATA);
17372         }
17373       OP_E (bytemode, sizeflag);
17374     }
17375 }
17376
17377 static void
17378 OP_Vex_2src_1 (int bytemode, int sizeflag)
17379 {
17380   if (modrm.mod == 3)
17381     {
17382       /* Skip mod/rm byte.   */
17383       MODRM_CHECK;
17384       codep++;
17385     }
17386
17387   if (vex.w)
17388     oappend (names_xmm[vex.register_specifier]);
17389   else
17390     OP_Vex_2src (bytemode, sizeflag);
17391 }
17392
17393 static void
17394 OP_Vex_2src_2 (int bytemode, int sizeflag)
17395 {
17396   if (vex.w)
17397     OP_Vex_2src (bytemode, sizeflag);
17398   else
17399     oappend (names_xmm[vex.register_specifier]);
17400 }
17401
17402 static void
17403 OP_EX_VexW (int bytemode, int sizeflag)
17404 {
17405   int reg = -1;
17406
17407   if (!vex_w_done)
17408     {
17409       vex_w_done = 1;
17410
17411       /* Skip mod/rm byte.  */
17412       MODRM_CHECK;
17413       codep++;
17414
17415       if (vex.w)
17416         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17417     }
17418   else
17419     {
17420       if (!vex.w)
17421         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17422     }
17423
17424   OP_EX_VexReg (bytemode, sizeflag, reg);
17425 }
17426
17427 static void
17428 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17429              int sizeflag ATTRIBUTE_UNUSED)
17430 {
17431   /* Skip the immediate byte and check for invalid bits.  */
17432   FETCH_DATA (the_info, codep + 1);
17433   if (*codep++ & 0xf)
17434     BadOp ();
17435 }
17436
17437 static void
17438 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17439 {
17440   int reg;
17441   const char **names;
17442
17443   FETCH_DATA (the_info, codep + 1);
17444   reg = *codep++;
17445
17446   if (bytemode != x_mode)
17447     abort ();
17448
17449   if (reg & 0xf)
17450       BadOp ();
17451
17452   reg >>= 4;
17453   if (reg > 7 && address_mode != mode_64bit)
17454     BadOp ();
17455
17456   switch (vex.length)
17457     {
17458     case 128:
17459       names = names_xmm;
17460       break;
17461     case 256:
17462       names = names_ymm;
17463       break;
17464     default:
17465       abort ();
17466     }
17467   oappend (names[reg]);
17468 }
17469
17470 static void
17471 OP_XMM_VexW (int bytemode, int sizeflag)
17472 {
17473   /* Turn off the REX.W bit since it is used for swapping operands
17474      now.  */
17475   rex &= ~REX_W;
17476   OP_XMM (bytemode, sizeflag);
17477 }
17478
17479 static void
17480 OP_EX_Vex (int bytemode, int sizeflag)
17481 {
17482   if (modrm.mod != 3)
17483     {
17484       if (vex.register_specifier != 0)
17485         BadOp ();
17486       need_vex_reg = 0;
17487     }
17488   OP_EX (bytemode, sizeflag);
17489 }
17490
17491 static void
17492 OP_XMM_Vex (int bytemode, int sizeflag)
17493 {
17494   if (modrm.mod != 3)
17495     {
17496       if (vex.register_specifier != 0)
17497         BadOp ();
17498       need_vex_reg = 0;
17499     }
17500   OP_XMM (bytemode, sizeflag);
17501 }
17502
17503 static void
17504 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17505 {
17506   switch (vex.length)
17507     {
17508     case 128:
17509       mnemonicendp = stpcpy (obuf, "vzeroupper");
17510       break;
17511     case 256:
17512       mnemonicendp = stpcpy (obuf, "vzeroall");
17513       break;
17514     default:
17515       abort ();
17516     }
17517 }
17518
17519 static struct op vex_cmp_op[] =
17520 {
17521   { STRING_COMMA_LEN ("eq") },
17522   { STRING_COMMA_LEN ("lt") },
17523   { STRING_COMMA_LEN ("le") },
17524   { STRING_COMMA_LEN ("unord") },
17525   { STRING_COMMA_LEN ("neq") },
17526   { STRING_COMMA_LEN ("nlt") },
17527   { STRING_COMMA_LEN ("nle") },
17528   { STRING_COMMA_LEN ("ord") },
17529   { STRING_COMMA_LEN ("eq_uq") },
17530   { STRING_COMMA_LEN ("nge") },
17531   { STRING_COMMA_LEN ("ngt") },
17532   { STRING_COMMA_LEN ("false") },
17533   { STRING_COMMA_LEN ("neq_oq") },
17534   { STRING_COMMA_LEN ("ge") },
17535   { STRING_COMMA_LEN ("gt") },
17536   { STRING_COMMA_LEN ("true") },
17537   { STRING_COMMA_LEN ("eq_os") },
17538   { STRING_COMMA_LEN ("lt_oq") },
17539   { STRING_COMMA_LEN ("le_oq") },
17540   { STRING_COMMA_LEN ("unord_s") },
17541   { STRING_COMMA_LEN ("neq_us") },
17542   { STRING_COMMA_LEN ("nlt_uq") },
17543   { STRING_COMMA_LEN ("nle_uq") },
17544   { STRING_COMMA_LEN ("ord_s") },
17545   { STRING_COMMA_LEN ("eq_us") },
17546   { STRING_COMMA_LEN ("nge_uq") },
17547   { STRING_COMMA_LEN ("ngt_uq") },
17548   { STRING_COMMA_LEN ("false_os") },
17549   { STRING_COMMA_LEN ("neq_os") },
17550   { STRING_COMMA_LEN ("ge_oq") },
17551   { STRING_COMMA_LEN ("gt_oq") },
17552   { STRING_COMMA_LEN ("true_us") },
17553 };
17554
17555 static void
17556 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17557 {
17558   unsigned int cmp_type;
17559
17560   FETCH_DATA (the_info, codep + 1);
17561   cmp_type = *codep++ & 0xff;
17562   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17563     {
17564       char suffix [3];
17565       char *p = mnemonicendp - 2;
17566       suffix[0] = p[0];
17567       suffix[1] = p[1];
17568       suffix[2] = '\0';
17569       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17570       mnemonicendp += vex_cmp_op[cmp_type].len;
17571     }
17572   else
17573     {
17574       /* We have a reserved extension byte.  Output it directly.  */
17575       scratchbuf[0] = '$';
17576       print_operand_value (scratchbuf + 1, 1, cmp_type);
17577       oappend_maybe_intel (scratchbuf);
17578       scratchbuf[0] = '\0';
17579     }
17580 }
17581
17582 static void
17583 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17584              int sizeflag ATTRIBUTE_UNUSED)
17585 {
17586   unsigned int cmp_type;
17587
17588   if (!vex.evex)
17589     abort ();
17590
17591   FETCH_DATA (the_info, codep + 1);
17592   cmp_type = *codep++ & 0xff;
17593   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17594      If it's the case, print suffix, otherwise - print the immediate.  */
17595   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17596       && cmp_type != 3
17597       && cmp_type != 7)
17598     {
17599       char suffix [3];
17600       char *p = mnemonicendp - 2;
17601
17602       /* vpcmp* can have both one- and two-lettered suffix.  */
17603       if (p[0] == 'p')
17604         {
17605           p++;
17606           suffix[0] = p[0];
17607           suffix[1] = '\0';
17608         }
17609       else
17610         {
17611           suffix[0] = p[0];
17612           suffix[1] = p[1];
17613           suffix[2] = '\0';
17614         }
17615
17616       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17617       mnemonicendp += simd_cmp_op[cmp_type].len;
17618     }
17619   else
17620     {
17621       /* We have a reserved extension byte.  Output it directly.  */
17622       scratchbuf[0] = '$';
17623       print_operand_value (scratchbuf + 1, 1, cmp_type);
17624       oappend_maybe_intel (scratchbuf);
17625       scratchbuf[0] = '\0';
17626     }
17627 }
17628
17629 static const struct op pclmul_op[] =
17630 {
17631   { STRING_COMMA_LEN ("lql") },
17632   { STRING_COMMA_LEN ("hql") },
17633   { STRING_COMMA_LEN ("lqh") },
17634   { STRING_COMMA_LEN ("hqh") }
17635 };
17636
17637 static void
17638 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17639               int sizeflag ATTRIBUTE_UNUSED)
17640 {
17641   unsigned int pclmul_type;
17642
17643   FETCH_DATA (the_info, codep + 1);
17644   pclmul_type = *codep++ & 0xff;
17645   switch (pclmul_type)
17646     {
17647     case 0x10:
17648       pclmul_type = 2;
17649       break;
17650     case 0x11:
17651       pclmul_type = 3;
17652       break;
17653     default:
17654       break;
17655     }
17656   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17657     {
17658       char suffix [4];
17659       char *p = mnemonicendp - 3;
17660       suffix[0] = p[0];
17661       suffix[1] = p[1];
17662       suffix[2] = p[2];
17663       suffix[3] = '\0';
17664       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17665       mnemonicendp += pclmul_op[pclmul_type].len;
17666     }
17667   else
17668     {
17669       /* We have a reserved extension byte.  Output it directly.  */
17670       scratchbuf[0] = '$';
17671       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17672       oappend_maybe_intel (scratchbuf);
17673       scratchbuf[0] = '\0';
17674     }
17675 }
17676
17677 static void
17678 MOVBE_Fixup (int bytemode, int sizeflag)
17679 {
17680   /* Add proper suffix to "movbe".  */
17681   char *p = mnemonicendp;
17682
17683   switch (bytemode)
17684     {
17685     case v_mode:
17686       if (intel_syntax)
17687         goto skip;
17688
17689       USED_REX (REX_W);
17690       if (sizeflag & SUFFIX_ALWAYS)
17691         {
17692           if (rex & REX_W)
17693             *p++ = 'q';
17694           else
17695             {
17696               if (sizeflag & DFLAG)
17697                 *p++ = 'l';
17698               else
17699                 *p++ = 'w';
17700               used_prefixes |= (prefixes & PREFIX_DATA);
17701             }
17702         }
17703       break;
17704     default:
17705       oappend (INTERNAL_DISASSEMBLER_ERROR);
17706       break;
17707     }
17708   mnemonicendp = p;
17709   *p = '\0';
17710
17711 skip:
17712   OP_M (bytemode, sizeflag);
17713 }
17714
17715 static void
17716 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17717 {
17718   int reg;
17719   const char **names;
17720
17721   /* Skip mod/rm byte.  */
17722   MODRM_CHECK;
17723   codep++;
17724
17725   if (vex.w)
17726     names = names64;
17727   else
17728     names = names32;
17729
17730   reg = modrm.rm;
17731   USED_REX (REX_B);
17732   if (rex & REX_B)
17733     reg += 8;
17734
17735   oappend (names[reg]);
17736 }
17737
17738 static void
17739 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17740 {
17741   const char **names;
17742
17743   if (vex.w)
17744     names = names64;
17745   else
17746     names = names32;
17747
17748   oappend (names[vex.register_specifier]);
17749 }
17750
17751 static void
17752 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17753 {
17754   if (!vex.evex
17755       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17756     abort ();
17757
17758   USED_REX (REX_R);
17759   if ((rex & REX_R) != 0 || !vex.r)
17760     {
17761       BadOp ();
17762       return;
17763     }
17764
17765   oappend (names_mask [modrm.reg]);
17766 }
17767
17768 static void
17769 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17770 {
17771   if (!vex.evex
17772       || (bytemode != evex_rounding_mode
17773           && bytemode != evex_sae_mode))
17774     abort ();
17775   if (modrm.mod == 3 && vex.b)
17776     switch (bytemode)
17777       {
17778       case evex_rounding_mode:
17779         oappend (names_rounding[vex.ll]);
17780         break;
17781       case evex_sae_mode:
17782         oappend ("{sae}");
17783         break;
17784       default:
17785         break;
17786       }
17787 }