1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void OP_LWPCB_E (int, int);
121 static void OP_LWP_E (int, int);
122 static void OP_Vex_2src_1 (int, int);
123 static void OP_Vex_2src_2 (int, int);
125 static void MOVBE_Fixup (int, int);
127 static void OP_Mask (int, int);
130 /* Points to first byte not fetched. */
131 bfd_byte
*max_fetched
;
132 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
135 OPCODES_SIGJMP_BUF bailout
;
145 enum address_mode address_mode
;
147 /* Flags for the prefixes for the current instruction. See below. */
150 /* REX prefix the current instruction. See below. */
152 /* Bits of REX we've already used. */
154 /* REX bits in original REX prefix ignored. */
155 static int rex_ignored
;
156 /* Mark parts used in the REX prefix. When we are testing for
157 empty prefix (for 8bit register REX extension), just mask it
158 out. Otherwise test for REX bit is excuse for existence of REX
159 only in case value is nonzero. */
160 #define USED_REX(value) \
165 rex_used |= (value) | REX_OPCODE; \
168 rex_used |= REX_OPCODE; \
171 /* Flags for prefixes which we somehow handled when printing the
172 current instruction. */
173 static int used_prefixes
;
175 /* Flags stored in PREFIXES. */
176 #define PREFIX_REPZ 1
177 #define PREFIX_REPNZ 2
178 #define PREFIX_LOCK 4
180 #define PREFIX_SS 0x10
181 #define PREFIX_DS 0x20
182 #define PREFIX_ES 0x40
183 #define PREFIX_FS 0x80
184 #define PREFIX_GS 0x100
185 #define PREFIX_DATA 0x200
186 #define PREFIX_ADDR 0x400
187 #define PREFIX_FWAIT 0x800
189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
190 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
192 #define FETCH_DATA(info, addr) \
193 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
194 ? 1 : fetch_data ((info), (addr)))
197 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
200 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
201 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
203 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
204 status
= (*info
->read_memory_func
) (start
,
206 addr
- priv
->max_fetched
,
212 /* If we did manage to read at least one byte, then
213 print_insn_i386 will do something sensible. Otherwise, print
214 an error. We do that here because this is where we know
216 if (priv
->max_fetched
== priv
->the_buffer
)
217 (*info
->memory_error_func
) (status
, start
, info
);
218 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
221 priv
->max_fetched
= addr
;
225 /* Possible values for prefix requirement. */
226 #define PREFIX_IGNORED_SHIFT 16
227 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
228 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
233 /* Opcode prefixes. */
234 #define PREFIX_OPCODE (PREFIX_REPZ \
238 /* Prefixes ignored. */
239 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
240 | PREFIX_IGNORED_REPNZ \
241 | PREFIX_IGNORED_DATA)
243 #define XX { NULL, 0 }
244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
246 #define Eb { OP_E, b_mode }
247 #define Ebnd { OP_E, bnd_mode }
248 #define EbS { OP_E, b_swap_mode }
249 #define Ev { OP_E, v_mode }
250 #define Ev_bnd { OP_E, v_bnd_mode }
251 #define EvS { OP_E, v_swap_mode }
252 #define Ed { OP_E, d_mode }
253 #define Edq { OP_E, dq_mode }
254 #define Edqw { OP_E, dqw_mode }
255 #define EdqwS { OP_E, dqw_swap_mode }
256 #define Edqb { OP_E, dqb_mode }
257 #define Edb { OP_E, db_mode }
258 #define Edw { OP_E, dw_mode }
259 #define Edqd { OP_E, dqd_mode }
260 #define Eq { OP_E, q_mode }
261 #define indirEv { OP_indirE, stack_v_mode }
262 #define indirEp { OP_indirE, f_mode }
263 #define stackEv { OP_E, stack_v_mode }
264 #define Em { OP_E, m_mode }
265 #define Ew { OP_E, w_mode }
266 #define M { OP_M, 0 } /* lea, lgdt, etc. */
267 #define Ma { OP_M, a_mode }
268 #define Mb { OP_M, b_mode }
269 #define Md { OP_M, d_mode }
270 #define Mo { OP_M, o_mode }
271 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
272 #define Mq { OP_M, q_mode }
273 #define Mx { OP_M, x_mode }
274 #define Mxmm { OP_M, xmm_mode }
275 #define Gb { OP_G, b_mode }
276 #define Gbnd { OP_G, bnd_mode }
277 #define Gv { OP_G, v_mode }
278 #define Gd { OP_G, d_mode }
279 #define Gdq { OP_G, dq_mode }
280 #define Gm { OP_G, m_mode }
281 #define Gw { OP_G, w_mode }
282 #define Rd { OP_R, d_mode }
283 #define Rdq { OP_R, dq_mode }
284 #define Rm { OP_R, m_mode }
285 #define Ib { OP_I, b_mode }
286 #define sIb { OP_sI, b_mode } /* sign extened byte */
287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
288 #define Iv { OP_I, v_mode }
289 #define sIv { OP_sI, v_mode }
290 #define Iq { OP_I, q_mode }
291 #define Iv64 { OP_I64, v_mode }
292 #define Iw { OP_I, w_mode }
293 #define I1 { OP_I, const_1_mode }
294 #define Jb { OP_J, b_mode }
295 #define Jv { OP_J, v_mode }
296 #define Cm { OP_C, m_mode }
297 #define Dm { OP_D, m_mode }
298 #define Td { OP_T, d_mode }
299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
301 #define RMeAX { OP_REG, eAX_reg }
302 #define RMeBX { OP_REG, eBX_reg }
303 #define RMeCX { OP_REG, eCX_reg }
304 #define RMeDX { OP_REG, eDX_reg }
305 #define RMeSP { OP_REG, eSP_reg }
306 #define RMeBP { OP_REG, eBP_reg }
307 #define RMeSI { OP_REG, eSI_reg }
308 #define RMeDI { OP_REG, eDI_reg }
309 #define RMrAX { OP_REG, rAX_reg }
310 #define RMrBX { OP_REG, rBX_reg }
311 #define RMrCX { OP_REG, rCX_reg }
312 #define RMrDX { OP_REG, rDX_reg }
313 #define RMrSP { OP_REG, rSP_reg }
314 #define RMrBP { OP_REG, rBP_reg }
315 #define RMrSI { OP_REG, rSI_reg }
316 #define RMrDI { OP_REG, rDI_reg }
317 #define RMAL { OP_REG, al_reg }
318 #define RMCL { OP_REG, cl_reg }
319 #define RMDL { OP_REG, dl_reg }
320 #define RMBL { OP_REG, bl_reg }
321 #define RMAH { OP_REG, ah_reg }
322 #define RMCH { OP_REG, ch_reg }
323 #define RMDH { OP_REG, dh_reg }
324 #define RMBH { OP_REG, bh_reg }
325 #define RMAX { OP_REG, ax_reg }
326 #define RMDX { OP_REG, dx_reg }
328 #define eAX { OP_IMREG, eAX_reg }
329 #define eBX { OP_IMREG, eBX_reg }
330 #define eCX { OP_IMREG, eCX_reg }
331 #define eDX { OP_IMREG, eDX_reg }
332 #define eSP { OP_IMREG, eSP_reg }
333 #define eBP { OP_IMREG, eBP_reg }
334 #define eSI { OP_IMREG, eSI_reg }
335 #define eDI { OP_IMREG, eDI_reg }
336 #define AL { OP_IMREG, al_reg }
337 #define CL { OP_IMREG, cl_reg }
338 #define DL { OP_IMREG, dl_reg }
339 #define BL { OP_IMREG, bl_reg }
340 #define AH { OP_IMREG, ah_reg }
341 #define CH { OP_IMREG, ch_reg }
342 #define DH { OP_IMREG, dh_reg }
343 #define BH { OP_IMREG, bh_reg }
344 #define AX { OP_IMREG, ax_reg }
345 #define DX { OP_IMREG, dx_reg }
346 #define zAX { OP_IMREG, z_mode_ax_reg }
347 #define indirDX { OP_IMREG, indir_dx_reg }
349 #define Sw { OP_SEG, w_mode }
350 #define Sv { OP_SEG, v_mode }
351 #define Ap { OP_DIR, 0 }
352 #define Ob { OP_OFF64, b_mode }
353 #define Ov { OP_OFF64, v_mode }
354 #define Xb { OP_DSreg, eSI_reg }
355 #define Xv { OP_DSreg, eSI_reg }
356 #define Xz { OP_DSreg, eSI_reg }
357 #define Yb { OP_ESreg, eDI_reg }
358 #define Yv { OP_ESreg, eDI_reg }
359 #define DSBX { OP_DSreg, eBX_reg }
361 #define es { OP_REG, es_reg }
362 #define ss { OP_REG, ss_reg }
363 #define cs { OP_REG, cs_reg }
364 #define ds { OP_REG, ds_reg }
365 #define fs { OP_REG, fs_reg }
366 #define gs { OP_REG, gs_reg }
368 #define MX { OP_MMX, 0 }
369 #define XM { OP_XMM, 0 }
370 #define XMScalar { OP_XMM, scalar_mode }
371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
372 #define XMM { OP_XMM, xmm_mode }
373 #define XMxmmq { OP_XMM, xmmq_mode }
374 #define EM { OP_EM, v_mode }
375 #define EMS { OP_EM, v_swap_mode }
376 #define EMd { OP_EM, d_mode }
377 #define EMx { OP_EM, x_mode }
378 #define EXw { OP_EX, w_mode }
379 #define EXd { OP_EX, d_mode }
380 #define EXdScalar { OP_EX, d_scalar_mode }
381 #define EXdS { OP_EX, d_swap_mode }
382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
383 #define EXq { OP_EX, q_mode }
384 #define EXqScalar { OP_EX, q_scalar_mode }
385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
386 #define EXqS { OP_EX, q_swap_mode }
387 #define EXx { OP_EX, x_mode }
388 #define EXxS { OP_EX, x_swap_mode }
389 #define EXxmm { OP_EX, xmm_mode }
390 #define EXymm { OP_EX, ymm_mode }
391 #define EXxmmq { OP_EX, xmmq_mode }
392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
395 #define EXxmm_md { OP_EX, xmm_md_mode }
396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
398 #define EXxmmdw { OP_EX, xmmdw_mode }
399 #define EXxmmqd { OP_EX, xmmqd_mode }
400 #define EXymmq { OP_EX, ymmq_mode }
401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
405 #define MS { OP_MS, v_mode }
406 #define XS { OP_XS, v_mode }
407 #define EMCq { OP_EMC, q_mode }
408 #define MXC { OP_MXC, 0 }
409 #define OPSUF { OP_3DNowSuffix, 0 }
410 #define CMP { CMP_Fixup, 0 }
411 #define XMM0 { XMM_Fixup, 0 }
412 #define FXSAVE { FXSAVE_Fixup, 0 }
413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
416 #define Vex { OP_VEX, vex_mode }
417 #define VexScalar { OP_VEX, vex_scalar_mode }
418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
419 #define Vex128 { OP_VEX, vex128_mode }
420 #define Vex256 { OP_VEX, vex256_mode }
421 #define VexGdq { OP_VEX, dq_mode }
422 #define VexI4 { VEXI4_Fixup, 0}
423 #define EXdVex { OP_EX_Vex, d_mode }
424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
426 #define EXqVex { OP_EX_Vex, q_mode }
427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
429 #define EXVexW { OP_EX_VexW, x_mode }
430 #define EXdVexW { OP_EX_VexW, d_mode }
431 #define EXqVexW { OP_EX_VexW, q_mode }
432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
433 #define XMVex { OP_XMM_Vex, 0 }
434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
435 #define XMVexW { OP_XMM_VexW, 0 }
436 #define XMVexI4 { OP_REG_VexI4, x_mode }
437 #define PCLMUL { PCLMUL_Fixup, 0 }
438 #define VZERO { VZERO_Fixup, 0 }
439 #define VCMP { VCMP_Fixup, 0 }
440 #define VPCMP { VPCMP_Fixup, 0 }
442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
445 #define XMask { OP_Mask, mask_mode }
446 #define MaskG { OP_G, mask_mode }
447 #define MaskE { OP_E, mask_mode }
448 #define MaskBDE { OP_E, mask_bd_mode }
449 #define MaskR { OP_R, mask_mode }
450 #define MaskVex { OP_VEX, mask_mode }
452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
457 /* Used handle "rep" prefix for string instructions. */
458 #define Xbr { REP_Fixup, eSI_reg }
459 #define Xvr { REP_Fixup, eSI_reg }
460 #define Ybr { REP_Fixup, eDI_reg }
461 #define Yvr { REP_Fixup, eDI_reg }
462 #define Yzr { REP_Fixup, eDI_reg }
463 #define indirDXr { REP_Fixup, indir_dx_reg }
464 #define ALr { REP_Fixup, al_reg }
465 #define eAXr { REP_Fixup, eAX_reg }
467 /* Used handle HLE prefix for lockable instructions. */
468 #define Ebh1 { HLE_Fixup1, b_mode }
469 #define Evh1 { HLE_Fixup1, v_mode }
470 #define Ebh2 { HLE_Fixup2, b_mode }
471 #define Evh2 { HLE_Fixup2, v_mode }
472 #define Ebh3 { HLE_Fixup3, b_mode }
473 #define Evh3 { HLE_Fixup3, v_mode }
475 #define BND { BND_Fixup, 0 }
477 #define cond_jump_flag { NULL, cond_jump_mode }
478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
480 /* bits in sizeflag */
481 #define SUFFIX_ALWAYS 4
489 /* byte operand with operand swapped */
491 /* byte operand, sign extend like 'T' suffix */
493 /* operand size depends on prefixes */
495 /* operand size depends on prefixes with operand swapped */
499 /* double word operand */
501 /* double word operand with operand swapped */
503 /* quad word operand */
505 /* quad word operand with operand swapped */
507 /* ten-byte operand */
509 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
510 broadcast enabled. */
512 /* Similar to x_mode, but with different EVEX mem shifts. */
514 /* Similar to x_mode, but with disabled broadcast. */
516 /* Similar to x_mode, but with operands swapped and disabled broadcast
519 /* 16-byte XMM operand */
521 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
522 memory operand (depending on vector length). Broadcast isn't
525 /* Same as xmmq_mode, but broadcast is allowed. */
526 evex_half_bcst_xmmq_mode
,
527 /* XMM register or byte memory operand */
529 /* XMM register or word memory operand */
531 /* XMM register or double word memory operand */
533 /* XMM register or quad word memory operand */
535 /* XMM register or double/quad word memory operand, depending on
538 /* 16-byte XMM, word, double word or quad word operand. */
540 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
542 /* 32-byte YMM operand */
544 /* quad word, ymmword or zmmword memory operand. */
546 /* 32-byte YMM or 16-byte word operand */
548 /* d_mode in 32bit, q_mode in 64bit mode. */
550 /* pair of v_mode operands */
555 /* operand size depends on REX prefixes. */
557 /* registers like dq_mode, memory like w_mode. */
561 /* 4- or 6-byte pointer operand */
564 /* v_mode for stack-related opcodes. */
566 /* non-quad operand size depends on prefixes */
568 /* 16-byte operand */
570 /* registers like dq_mode, memory like b_mode. */
572 /* registers like d_mode, memory like b_mode. */
574 /* registers like d_mode, memory like w_mode. */
576 /* registers like dq_mode, memory like d_mode. */
578 /* normal vex mode */
580 /* 128bit vex mode */
582 /* 256bit vex mode */
584 /* operand size depends on the VEX.W bit. */
587 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
588 vex_vsib_d_w_dq_mode
,
589 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
591 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
592 vex_vsib_q_w_dq_mode
,
593 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
596 /* scalar, ignore vector length. */
598 /* like d_mode, ignore vector length. */
600 /* like d_swap_mode, ignore vector length. */
602 /* like q_mode, ignore vector length. */
604 /* like q_swap_mode, ignore vector length. */
606 /* like vex_mode, ignore vector length. */
608 /* like vex_w_dq_mode, ignore vector length. */
609 vex_scalar_w_dq_mode
,
611 /* Static rounding. */
613 /* Supress all exceptions. */
616 /* Mask register operand. */
618 /* Mask register operand. */
685 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
687 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
688 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
689 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
690 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
691 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
692 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
693 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
694 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
695 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
696 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
697 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
698 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
699 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
700 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
701 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
817 MOD_VEX_0F12_PREFIX_0
,
819 MOD_VEX_0F16_PREFIX_0
,
835 MOD_VEX_0FD7_PREFIX_2
,
836 MOD_VEX_0FE7_PREFIX_2
,
837 MOD_VEX_0FF0_PREFIX_3
,
838 MOD_VEX_0F381A_PREFIX_2
,
839 MOD_VEX_0F382A_PREFIX_2
,
840 MOD_VEX_0F382C_PREFIX_2
,
841 MOD_VEX_0F382D_PREFIX_2
,
842 MOD_VEX_0F382E_PREFIX_2
,
843 MOD_VEX_0F382F_PREFIX_2
,
844 MOD_VEX_0F385A_PREFIX_2
,
845 MOD_VEX_0F388C_PREFIX_2
,
846 MOD_VEX_0F388E_PREFIX_2
,
848 MOD_EVEX_0F10_PREFIX_1
,
849 MOD_EVEX_0F10_PREFIX_3
,
850 MOD_EVEX_0F11_PREFIX_1
,
851 MOD_EVEX_0F11_PREFIX_3
,
852 MOD_EVEX_0F12_PREFIX_0
,
853 MOD_EVEX_0F16_PREFIX_0
,
854 MOD_EVEX_0F38C6_REG_1
,
855 MOD_EVEX_0F38C6_REG_2
,
856 MOD_EVEX_0F38C6_REG_5
,
857 MOD_EVEX_0F38C6_REG_6
,
858 MOD_EVEX_0F38C7_REG_1
,
859 MOD_EVEX_0F38C7_REG_2
,
860 MOD_EVEX_0F38C7_REG_5
,
861 MOD_EVEX_0F38C7_REG_6
925 PREFIX_RM_0_0FAE_REG_7
,
931 PREFIX_MOD_0_0FC7_REG_6
,
932 PREFIX_MOD_3_0FC7_REG_6
,
933 PREFIX_MOD_3_0FC7_REG_7
,
1057 PREFIX_VEX_0F71_REG_2
,
1058 PREFIX_VEX_0F71_REG_4
,
1059 PREFIX_VEX_0F71_REG_6
,
1060 PREFIX_VEX_0F72_REG_2
,
1061 PREFIX_VEX_0F72_REG_4
,
1062 PREFIX_VEX_0F72_REG_6
,
1063 PREFIX_VEX_0F73_REG_2
,
1064 PREFIX_VEX_0F73_REG_3
,
1065 PREFIX_VEX_0F73_REG_6
,
1066 PREFIX_VEX_0F73_REG_7
,
1238 PREFIX_VEX_0F38F3_REG_1
,
1239 PREFIX_VEX_0F38F3_REG_2
,
1240 PREFIX_VEX_0F38F3_REG_3
,
1357 PREFIX_EVEX_0F71_REG_2
,
1358 PREFIX_EVEX_0F71_REG_4
,
1359 PREFIX_EVEX_0F71_REG_6
,
1360 PREFIX_EVEX_0F72_REG_0
,
1361 PREFIX_EVEX_0F72_REG_1
,
1362 PREFIX_EVEX_0F72_REG_2
,
1363 PREFIX_EVEX_0F72_REG_4
,
1364 PREFIX_EVEX_0F72_REG_6
,
1365 PREFIX_EVEX_0F73_REG_2
,
1366 PREFIX_EVEX_0F73_REG_3
,
1367 PREFIX_EVEX_0F73_REG_6
,
1368 PREFIX_EVEX_0F73_REG_7
,
1551 PREFIX_EVEX_0F38C6_REG_1
,
1552 PREFIX_EVEX_0F38C6_REG_2
,
1553 PREFIX_EVEX_0F38C6_REG_5
,
1554 PREFIX_EVEX_0F38C6_REG_6
,
1555 PREFIX_EVEX_0F38C7_REG_1
,
1556 PREFIX_EVEX_0F38C7_REG_2
,
1557 PREFIX_EVEX_0F38C7_REG_5
,
1558 PREFIX_EVEX_0F38C7_REG_6
,
1647 THREE_BYTE_0F38
= 0,
1675 VEX_LEN_0F10_P_1
= 0,
1679 VEX_LEN_0F12_P_0_M_0
,
1680 VEX_LEN_0F12_P_0_M_1
,
1683 VEX_LEN_0F16_P_0_M_0
,
1684 VEX_LEN_0F16_P_0_M_1
,
1748 VEX_LEN_0FAE_R_2_M_0
,
1749 VEX_LEN_0FAE_R_3_M_0
,
1758 VEX_LEN_0F381A_P_2_M_0
,
1761 VEX_LEN_0F385A_P_2_M_0
,
1768 VEX_LEN_0F38F3_R_1_P_0
,
1769 VEX_LEN_0F38F3_R_2_P_0
,
1770 VEX_LEN_0F38F3_R_3_P_0
,
1816 VEX_LEN_0FXOP_08_CC
,
1817 VEX_LEN_0FXOP_08_CD
,
1818 VEX_LEN_0FXOP_08_CE
,
1819 VEX_LEN_0FXOP_08_CF
,
1820 VEX_LEN_0FXOP_08_EC
,
1821 VEX_LEN_0FXOP_08_ED
,
1822 VEX_LEN_0FXOP_08_EE
,
1823 VEX_LEN_0FXOP_08_EF
,
1824 VEX_LEN_0FXOP_09_80
,
1858 VEX_W_0F41_P_0_LEN_1
,
1859 VEX_W_0F41_P_2_LEN_1
,
1860 VEX_W_0F42_P_0_LEN_1
,
1861 VEX_W_0F42_P_2_LEN_1
,
1862 VEX_W_0F44_P_0_LEN_0
,
1863 VEX_W_0F44_P_2_LEN_0
,
1864 VEX_W_0F45_P_0_LEN_1
,
1865 VEX_W_0F45_P_2_LEN_1
,
1866 VEX_W_0F46_P_0_LEN_1
,
1867 VEX_W_0F46_P_2_LEN_1
,
1868 VEX_W_0F47_P_0_LEN_1
,
1869 VEX_W_0F47_P_2_LEN_1
,
1870 VEX_W_0F4A_P_0_LEN_1
,
1871 VEX_W_0F4A_P_2_LEN_1
,
1872 VEX_W_0F4B_P_0_LEN_1
,
1873 VEX_W_0F4B_P_2_LEN_1
,
1953 VEX_W_0F90_P_0_LEN_0
,
1954 VEX_W_0F90_P_2_LEN_0
,
1955 VEX_W_0F91_P_0_LEN_0
,
1956 VEX_W_0F91_P_2_LEN_0
,
1957 VEX_W_0F92_P_0_LEN_0
,
1958 VEX_W_0F92_P_2_LEN_0
,
1959 VEX_W_0F92_P_3_LEN_0
,
1960 VEX_W_0F93_P_0_LEN_0
,
1961 VEX_W_0F93_P_2_LEN_0
,
1962 VEX_W_0F93_P_3_LEN_0
,
1963 VEX_W_0F98_P_0_LEN_0
,
1964 VEX_W_0F98_P_2_LEN_0
,
1965 VEX_W_0F99_P_0_LEN_0
,
1966 VEX_W_0F99_P_2_LEN_0
,
2045 VEX_W_0F381A_P_2_M_0
,
2057 VEX_W_0F382A_P_2_M_0
,
2059 VEX_W_0F382C_P_2_M_0
,
2060 VEX_W_0F382D_P_2_M_0
,
2061 VEX_W_0F382E_P_2_M_0
,
2062 VEX_W_0F382F_P_2_M_0
,
2084 VEX_W_0F385A_P_2_M_0
,
2112 VEX_W_0F3A30_P_2_LEN_0
,
2113 VEX_W_0F3A31_P_2_LEN_0
,
2114 VEX_W_0F3A32_P_2_LEN_0
,
2115 VEX_W_0F3A33_P_2_LEN_0
,
2135 EVEX_W_0F10_P_1_M_0
,
2136 EVEX_W_0F10_P_1_M_1
,
2138 EVEX_W_0F10_P_3_M_0
,
2139 EVEX_W_0F10_P_3_M_1
,
2141 EVEX_W_0F11_P_1_M_0
,
2142 EVEX_W_0F11_P_1_M_1
,
2144 EVEX_W_0F11_P_3_M_0
,
2145 EVEX_W_0F11_P_3_M_1
,
2146 EVEX_W_0F12_P_0_M_0
,
2147 EVEX_W_0F12_P_0_M_1
,
2157 EVEX_W_0F16_P_0_M_0
,
2158 EVEX_W_0F16_P_0_M_1
,
2229 EVEX_W_0F72_R_2_P_2
,
2230 EVEX_W_0F72_R_6_P_2
,
2231 EVEX_W_0F73_R_2_P_2
,
2232 EVEX_W_0F73_R_6_P_2
,
2332 EVEX_W_0F38C7_R_1_P_2
,
2333 EVEX_W_0F38C7_R_2_P_2
,
2334 EVEX_W_0F38C7_R_5_P_2
,
2335 EVEX_W_0F38C7_R_6_P_2
,
2370 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2379 unsigned int prefix_requirement
;
2382 /* Upper case letters in the instruction names here are macros.
2383 'A' => print 'b' if no register operands or suffix_always is true
2384 'B' => print 'b' if suffix_always is true
2385 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2387 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2388 suffix_always is true
2389 'E' => print 'e' if 32-bit form of jcxz
2390 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2391 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2392 'H' => print ",pt" or ",pn" branch hint
2393 'I' => honor following macro letter even in Intel mode (implemented only
2394 for some of the macro letters)
2396 'K' => print 'd' or 'q' if rex prefix is present.
2397 'L' => print 'l' if suffix_always is true
2398 'M' => print 'r' if intel_mnemonic is false.
2399 'N' => print 'n' if instruction has no wait "prefix"
2400 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2401 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2402 or suffix_always is true. print 'q' if rex prefix is present.
2403 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2405 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2406 'S' => print 'w', 'l' or 'q' if suffix_always is true
2407 'T' => print 'q' in 64bit mode if instruction has no operand size
2408 prefix and behave as 'P' otherwise
2409 'U' => print 'q' in 64bit mode if instruction has no operand size
2410 prefix and behave as 'Q' otherwise
2411 'V' => print 'q' in 64bit mode if instruction has no operand size
2412 prefix and behave as 'S' otherwise
2413 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2414 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2415 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2416 suffix_always is true.
2417 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2418 '!' => change condition from true to false or from false to true.
2419 '%' => add 1 upper case letter to the macro.
2420 '^' => print 'w' or 'l' depending on operand size prefix or
2421 suffix_always is true (lcall/ljmp).
2422 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2423 on operand size prefix.
2425 2 upper case letter macros:
2426 "XY" => print 'x' or 'y' if suffix_always is true or no register
2427 operands and no broadcast.
2428 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2429 register operands and no broadcast.
2430 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2431 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2432 or suffix_always is true
2433 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2434 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2435 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2436 "LW" => print 'd', 'q' depending on the VEX.W bit
2437 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2438 an operand size prefix, or suffix_always is true. print
2439 'q' if rex prefix is present.
2441 Many of the above letters print nothing in Intel mode. See "putop"
2444 Braces '{' and '}', and vertical bars '|', indicate alternative
2445 mnemonic strings for AT&T and Intel. */
2447 static const struct dis386 dis386
[] = {
2449 { "addB", { Ebh1
, Gb
}, 0 },
2450 { "addS", { Evh1
, Gv
}, 0 },
2451 { "addB", { Gb
, EbS
}, 0 },
2452 { "addS", { Gv
, EvS
}, 0 },
2453 { "addB", { AL
, Ib
}, 0 },
2454 { "addS", { eAX
, Iv
}, 0 },
2455 { X86_64_TABLE (X86_64_06
) },
2456 { X86_64_TABLE (X86_64_07
) },
2458 { "orB", { Ebh1
, Gb
}, 0 },
2459 { "orS", { Evh1
, Gv
}, 0 },
2460 { "orB", { Gb
, EbS
}, 0 },
2461 { "orS", { Gv
, EvS
}, 0 },
2462 { "orB", { AL
, Ib
}, 0 },
2463 { "orS", { eAX
, Iv
}, 0 },
2464 { X86_64_TABLE (X86_64_0D
) },
2465 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2467 { "adcB", { Ebh1
, Gb
}, 0 },
2468 { "adcS", { Evh1
, Gv
}, 0 },
2469 { "adcB", { Gb
, EbS
}, 0 },
2470 { "adcS", { Gv
, EvS
}, 0 },
2471 { "adcB", { AL
, Ib
}, 0 },
2472 { "adcS", { eAX
, Iv
}, 0 },
2473 { X86_64_TABLE (X86_64_16
) },
2474 { X86_64_TABLE (X86_64_17
) },
2476 { "sbbB", { Ebh1
, Gb
}, 0 },
2477 { "sbbS", { Evh1
, Gv
}, 0 },
2478 { "sbbB", { Gb
, EbS
}, 0 },
2479 { "sbbS", { Gv
, EvS
}, 0 },
2480 { "sbbB", { AL
, Ib
}, 0 },
2481 { "sbbS", { eAX
, Iv
}, 0 },
2482 { X86_64_TABLE (X86_64_1E
) },
2483 { X86_64_TABLE (X86_64_1F
) },
2485 { "andB", { Ebh1
, Gb
}, 0 },
2486 { "andS", { Evh1
, Gv
}, 0 },
2487 { "andB", { Gb
, EbS
}, 0 },
2488 { "andS", { Gv
, EvS
}, 0 },
2489 { "andB", { AL
, Ib
}, 0 },
2490 { "andS", { eAX
, Iv
}, 0 },
2491 { Bad_Opcode
}, /* SEG ES prefix */
2492 { X86_64_TABLE (X86_64_27
) },
2494 { "subB", { Ebh1
, Gb
}, 0 },
2495 { "subS", { Evh1
, Gv
}, 0 },
2496 { "subB", { Gb
, EbS
}, 0 },
2497 { "subS", { Gv
, EvS
}, 0 },
2498 { "subB", { AL
, Ib
}, 0 },
2499 { "subS", { eAX
, Iv
}, 0 },
2500 { Bad_Opcode
}, /* SEG CS prefix */
2501 { X86_64_TABLE (X86_64_2F
) },
2503 { "xorB", { Ebh1
, Gb
}, 0 },
2504 { "xorS", { Evh1
, Gv
}, 0 },
2505 { "xorB", { Gb
, EbS
}, 0 },
2506 { "xorS", { Gv
, EvS
}, 0 },
2507 { "xorB", { AL
, Ib
}, 0 },
2508 { "xorS", { eAX
, Iv
}, 0 },
2509 { Bad_Opcode
}, /* SEG SS prefix */
2510 { X86_64_TABLE (X86_64_37
) },
2512 { "cmpB", { Eb
, Gb
}, 0 },
2513 { "cmpS", { Ev
, Gv
}, 0 },
2514 { "cmpB", { Gb
, EbS
}, 0 },
2515 { "cmpS", { Gv
, EvS
}, 0 },
2516 { "cmpB", { AL
, Ib
}, 0 },
2517 { "cmpS", { eAX
, Iv
}, 0 },
2518 { Bad_Opcode
}, /* SEG DS prefix */
2519 { X86_64_TABLE (X86_64_3F
) },
2521 { "inc{S|}", { RMeAX
}, 0 },
2522 { "inc{S|}", { RMeCX
}, 0 },
2523 { "inc{S|}", { RMeDX
}, 0 },
2524 { "inc{S|}", { RMeBX
}, 0 },
2525 { "inc{S|}", { RMeSP
}, 0 },
2526 { "inc{S|}", { RMeBP
}, 0 },
2527 { "inc{S|}", { RMeSI
}, 0 },
2528 { "inc{S|}", { RMeDI
}, 0 },
2530 { "dec{S|}", { RMeAX
}, 0 },
2531 { "dec{S|}", { RMeCX
}, 0 },
2532 { "dec{S|}", { RMeDX
}, 0 },
2533 { "dec{S|}", { RMeBX
}, 0 },
2534 { "dec{S|}", { RMeSP
}, 0 },
2535 { "dec{S|}", { RMeBP
}, 0 },
2536 { "dec{S|}", { RMeSI
}, 0 },
2537 { "dec{S|}", { RMeDI
}, 0 },
2539 { "pushV", { RMrAX
}, 0 },
2540 { "pushV", { RMrCX
}, 0 },
2541 { "pushV", { RMrDX
}, 0 },
2542 { "pushV", { RMrBX
}, 0 },
2543 { "pushV", { RMrSP
}, 0 },
2544 { "pushV", { RMrBP
}, 0 },
2545 { "pushV", { RMrSI
}, 0 },
2546 { "pushV", { RMrDI
}, 0 },
2548 { "popV", { RMrAX
}, 0 },
2549 { "popV", { RMrCX
}, 0 },
2550 { "popV", { RMrDX
}, 0 },
2551 { "popV", { RMrBX
}, 0 },
2552 { "popV", { RMrSP
}, 0 },
2553 { "popV", { RMrBP
}, 0 },
2554 { "popV", { RMrSI
}, 0 },
2555 { "popV", { RMrDI
}, 0 },
2557 { X86_64_TABLE (X86_64_60
) },
2558 { X86_64_TABLE (X86_64_61
) },
2559 { X86_64_TABLE (X86_64_62
) },
2560 { X86_64_TABLE (X86_64_63
) },
2561 { Bad_Opcode
}, /* seg fs */
2562 { Bad_Opcode
}, /* seg gs */
2563 { Bad_Opcode
}, /* op size prefix */
2564 { Bad_Opcode
}, /* adr size prefix */
2566 { "pushT", { sIv
}, 0 },
2567 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2568 { "pushT", { sIbT
}, 0 },
2569 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2570 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2571 { X86_64_TABLE (X86_64_6D
) },
2572 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2573 { X86_64_TABLE (X86_64_6F
) },
2575 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2576 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2577 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2578 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2579 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2580 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2581 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2582 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2584 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2585 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2586 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2587 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2588 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2589 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2590 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2591 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2593 { REG_TABLE (REG_80
) },
2594 { REG_TABLE (REG_81
) },
2596 { REG_TABLE (REG_82
) },
2597 { "testB", { Eb
, Gb
}, 0 },
2598 { "testS", { Ev
, Gv
}, 0 },
2599 { "xchgB", { Ebh2
, Gb
}, 0 },
2600 { "xchgS", { Evh2
, Gv
}, 0 },
2602 { "movB", { Ebh3
, Gb
}, 0 },
2603 { "movS", { Evh3
, Gv
}, 0 },
2604 { "movB", { Gb
, EbS
}, 0 },
2605 { "movS", { Gv
, EvS
}, 0 },
2606 { "movD", { Sv
, Sw
}, 0 },
2607 { MOD_TABLE (MOD_8D
) },
2608 { "movD", { Sw
, Sv
}, 0 },
2609 { REG_TABLE (REG_8F
) },
2611 { PREFIX_TABLE (PREFIX_90
) },
2612 { "xchgS", { RMeCX
, eAX
}, 0 },
2613 { "xchgS", { RMeDX
, eAX
}, 0 },
2614 { "xchgS", { RMeBX
, eAX
}, 0 },
2615 { "xchgS", { RMeSP
, eAX
}, 0 },
2616 { "xchgS", { RMeBP
, eAX
}, 0 },
2617 { "xchgS", { RMeSI
, eAX
}, 0 },
2618 { "xchgS", { RMeDI
, eAX
}, 0 },
2620 { "cW{t|}R", { XX
}, 0 },
2621 { "cR{t|}O", { XX
}, 0 },
2622 { X86_64_TABLE (X86_64_9A
) },
2623 { Bad_Opcode
}, /* fwait */
2624 { "pushfT", { XX
}, 0 },
2625 { "popfT", { XX
}, 0 },
2626 { "sahf", { XX
}, 0 },
2627 { "lahf", { XX
}, 0 },
2629 { "mov%LB", { AL
, Ob
}, 0 },
2630 { "mov%LS", { eAX
, Ov
}, 0 },
2631 { "mov%LB", { Ob
, AL
}, 0 },
2632 { "mov%LS", { Ov
, eAX
}, 0 },
2633 { "movs{b|}", { Ybr
, Xb
}, 0 },
2634 { "movs{R|}", { Yvr
, Xv
}, 0 },
2635 { "cmps{b|}", { Xb
, Yb
}, 0 },
2636 { "cmps{R|}", { Xv
, Yv
}, 0 },
2638 { "testB", { AL
, Ib
}, 0 },
2639 { "testS", { eAX
, Iv
}, 0 },
2640 { "stosB", { Ybr
, AL
}, 0 },
2641 { "stosS", { Yvr
, eAX
}, 0 },
2642 { "lodsB", { ALr
, Xb
}, 0 },
2643 { "lodsS", { eAXr
, Xv
}, 0 },
2644 { "scasB", { AL
, Yb
}, 0 },
2645 { "scasS", { eAX
, Yv
}, 0 },
2647 { "movB", { RMAL
, Ib
}, 0 },
2648 { "movB", { RMCL
, Ib
}, 0 },
2649 { "movB", { RMDL
, Ib
}, 0 },
2650 { "movB", { RMBL
, Ib
}, 0 },
2651 { "movB", { RMAH
, Ib
}, 0 },
2652 { "movB", { RMCH
, Ib
}, 0 },
2653 { "movB", { RMDH
, Ib
}, 0 },
2654 { "movB", { RMBH
, Ib
}, 0 },
2656 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2657 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2658 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2659 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2660 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2661 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2662 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2663 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2665 { REG_TABLE (REG_C0
) },
2666 { REG_TABLE (REG_C1
) },
2667 { "retT", { Iw
, BND
}, 0 },
2668 { "retT", { BND
}, 0 },
2669 { X86_64_TABLE (X86_64_C4
) },
2670 { X86_64_TABLE (X86_64_C5
) },
2671 { REG_TABLE (REG_C6
) },
2672 { REG_TABLE (REG_C7
) },
2674 { "enterT", { Iw
, Ib
}, 0 },
2675 { "leaveT", { XX
}, 0 },
2676 { "Jret{|f}P", { Iw
}, 0 },
2677 { "Jret{|f}P", { XX
}, 0 },
2678 { "int3", { XX
}, 0 },
2679 { "int", { Ib
}, 0 },
2680 { X86_64_TABLE (X86_64_CE
) },
2681 { "iret%LP", { XX
}, 0 },
2683 { REG_TABLE (REG_D0
) },
2684 { REG_TABLE (REG_D1
) },
2685 { REG_TABLE (REG_D2
) },
2686 { REG_TABLE (REG_D3
) },
2687 { X86_64_TABLE (X86_64_D4
) },
2688 { X86_64_TABLE (X86_64_D5
) },
2690 { "xlat", { DSBX
}, 0 },
2701 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2702 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2703 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2704 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2705 { "inB", { AL
, Ib
}, 0 },
2706 { "inG", { zAX
, Ib
}, 0 },
2707 { "outB", { Ib
, AL
}, 0 },
2708 { "outG", { Ib
, zAX
}, 0 },
2710 { X86_64_TABLE (X86_64_E8
) },
2711 { X86_64_TABLE (X86_64_E9
) },
2712 { X86_64_TABLE (X86_64_EA
) },
2713 { "jmp", { Jb
, BND
}, 0 },
2714 { "inB", { AL
, indirDX
}, 0 },
2715 { "inG", { zAX
, indirDX
}, 0 },
2716 { "outB", { indirDX
, AL
}, 0 },
2717 { "outG", { indirDX
, zAX
}, 0 },
2719 { Bad_Opcode
}, /* lock prefix */
2720 { "icebp", { XX
}, 0 },
2721 { Bad_Opcode
}, /* repne */
2722 { Bad_Opcode
}, /* repz */
2723 { "hlt", { XX
}, 0 },
2724 { "cmc", { XX
}, 0 },
2725 { REG_TABLE (REG_F6
) },
2726 { REG_TABLE (REG_F7
) },
2728 { "clc", { XX
}, 0 },
2729 { "stc", { XX
}, 0 },
2730 { "cli", { XX
}, 0 },
2731 { "sti", { XX
}, 0 },
2732 { "cld", { XX
}, 0 },
2733 { "std", { XX
}, 0 },
2734 { REG_TABLE (REG_FE
) },
2735 { REG_TABLE (REG_FF
) },
2738 static const struct dis386 dis386_twobyte
[] = {
2740 { REG_TABLE (REG_0F00
) },
2741 { REG_TABLE (REG_0F01
) },
2742 { "larS", { Gv
, Ew
}, 0 },
2743 { "lslS", { Gv
, Ew
}, 0 },
2745 { "syscall", { XX
}, 0 },
2746 { "clts", { XX
}, 0 },
2747 { "sysret%LP", { XX
}, 0 },
2749 { "invd", { XX
}, 0 },
2750 { "wbinvd", { XX
}, 0 },
2752 { "ud2", { XX
}, 0 },
2754 { REG_TABLE (REG_0F0D
) },
2755 { "femms", { XX
}, 0 },
2756 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2758 { PREFIX_TABLE (PREFIX_0F10
) },
2759 { PREFIX_TABLE (PREFIX_0F11
) },
2760 { PREFIX_TABLE (PREFIX_0F12
) },
2761 { MOD_TABLE (MOD_0F13
) },
2762 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2763 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2764 { PREFIX_TABLE (PREFIX_0F16
) },
2765 { MOD_TABLE (MOD_0F17
) },
2767 { REG_TABLE (REG_0F18
) },
2768 { "nopQ", { Ev
}, 0 },
2769 { PREFIX_TABLE (PREFIX_0F1A
) },
2770 { PREFIX_TABLE (PREFIX_0F1B
) },
2771 { "nopQ", { Ev
}, 0 },
2772 { "nopQ", { Ev
}, 0 },
2773 { "nopQ", { Ev
}, 0 },
2774 { "nopQ", { Ev
}, 0 },
2776 { "movZ", { Rm
, Cm
}, 0 },
2777 { "movZ", { Rm
, Dm
}, 0 },
2778 { "movZ", { Cm
, Rm
}, 0 },
2779 { "movZ", { Dm
, Rm
}, 0 },
2780 { MOD_TABLE (MOD_0F24
) },
2782 { MOD_TABLE (MOD_0F26
) },
2785 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2786 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2787 { PREFIX_TABLE (PREFIX_0F2A
) },
2788 { PREFIX_TABLE (PREFIX_0F2B
) },
2789 { PREFIX_TABLE (PREFIX_0F2C
) },
2790 { PREFIX_TABLE (PREFIX_0F2D
) },
2791 { PREFIX_TABLE (PREFIX_0F2E
) },
2792 { PREFIX_TABLE (PREFIX_0F2F
) },
2794 { "wrmsr", { XX
}, 0 },
2795 { "rdtsc", { XX
}, 0 },
2796 { "rdmsr", { XX
}, 0 },
2797 { "rdpmc", { XX
}, 0 },
2798 { "sysenter", { XX
}, 0 },
2799 { "sysexit", { XX
}, 0 },
2801 { "getsec", { XX
}, 0 },
2803 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2805 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2812 { "cmovoS", { Gv
, Ev
}, 0 },
2813 { "cmovnoS", { Gv
, Ev
}, 0 },
2814 { "cmovbS", { Gv
, Ev
}, 0 },
2815 { "cmovaeS", { Gv
, Ev
}, 0 },
2816 { "cmoveS", { Gv
, Ev
}, 0 },
2817 { "cmovneS", { Gv
, Ev
}, 0 },
2818 { "cmovbeS", { Gv
, Ev
}, 0 },
2819 { "cmovaS", { Gv
, Ev
}, 0 },
2821 { "cmovsS", { Gv
, Ev
}, 0 },
2822 { "cmovnsS", { Gv
, Ev
}, 0 },
2823 { "cmovpS", { Gv
, Ev
}, 0 },
2824 { "cmovnpS", { Gv
, Ev
}, 0 },
2825 { "cmovlS", { Gv
, Ev
}, 0 },
2826 { "cmovgeS", { Gv
, Ev
}, 0 },
2827 { "cmovleS", { Gv
, Ev
}, 0 },
2828 { "cmovgS", { Gv
, Ev
}, 0 },
2830 { MOD_TABLE (MOD_0F51
) },
2831 { PREFIX_TABLE (PREFIX_0F51
) },
2832 { PREFIX_TABLE (PREFIX_0F52
) },
2833 { PREFIX_TABLE (PREFIX_0F53
) },
2834 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2835 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2836 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2837 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2839 { PREFIX_TABLE (PREFIX_0F58
) },
2840 { PREFIX_TABLE (PREFIX_0F59
) },
2841 { PREFIX_TABLE (PREFIX_0F5A
) },
2842 { PREFIX_TABLE (PREFIX_0F5B
) },
2843 { PREFIX_TABLE (PREFIX_0F5C
) },
2844 { PREFIX_TABLE (PREFIX_0F5D
) },
2845 { PREFIX_TABLE (PREFIX_0F5E
) },
2846 { PREFIX_TABLE (PREFIX_0F5F
) },
2848 { PREFIX_TABLE (PREFIX_0F60
) },
2849 { PREFIX_TABLE (PREFIX_0F61
) },
2850 { PREFIX_TABLE (PREFIX_0F62
) },
2851 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2852 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2853 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2854 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2855 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2857 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2858 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2859 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2860 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2861 { PREFIX_TABLE (PREFIX_0F6C
) },
2862 { PREFIX_TABLE (PREFIX_0F6D
) },
2863 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2864 { PREFIX_TABLE (PREFIX_0F6F
) },
2866 { PREFIX_TABLE (PREFIX_0F70
) },
2867 { REG_TABLE (REG_0F71
) },
2868 { REG_TABLE (REG_0F72
) },
2869 { REG_TABLE (REG_0F73
) },
2870 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2871 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2872 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2873 { "emms", { XX
}, PREFIX_OPCODE
},
2875 { PREFIX_TABLE (PREFIX_0F78
) },
2876 { PREFIX_TABLE (PREFIX_0F79
) },
2877 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2879 { PREFIX_TABLE (PREFIX_0F7C
) },
2880 { PREFIX_TABLE (PREFIX_0F7D
) },
2881 { PREFIX_TABLE (PREFIX_0F7E
) },
2882 { PREFIX_TABLE (PREFIX_0F7F
) },
2884 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2885 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2886 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2887 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2888 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2889 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2890 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2891 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2893 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2894 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2895 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2896 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2897 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2898 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2899 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2900 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2902 { "seto", { Eb
}, 0 },
2903 { "setno", { Eb
}, 0 },
2904 { "setb", { Eb
}, 0 },
2905 { "setae", { Eb
}, 0 },
2906 { "sete", { Eb
}, 0 },
2907 { "setne", { Eb
}, 0 },
2908 { "setbe", { Eb
}, 0 },
2909 { "seta", { Eb
}, 0 },
2911 { "sets", { Eb
}, 0 },
2912 { "setns", { Eb
}, 0 },
2913 { "setp", { Eb
}, 0 },
2914 { "setnp", { Eb
}, 0 },
2915 { "setl", { Eb
}, 0 },
2916 { "setge", { Eb
}, 0 },
2917 { "setle", { Eb
}, 0 },
2918 { "setg", { Eb
}, 0 },
2920 { "pushT", { fs
}, 0 },
2921 { "popT", { fs
}, 0 },
2922 { "cpuid", { XX
}, 0 },
2923 { "btS", { Ev
, Gv
}, 0 },
2924 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2925 { "shldS", { Ev
, Gv
, CL
}, 0 },
2926 { REG_TABLE (REG_0FA6
) },
2927 { REG_TABLE (REG_0FA7
) },
2929 { "pushT", { gs
}, 0 },
2930 { "popT", { gs
}, 0 },
2931 { "rsm", { XX
}, 0 },
2932 { "btsS", { Evh1
, Gv
}, 0 },
2933 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2934 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2935 { REG_TABLE (REG_0FAE
) },
2936 { "imulS", { Gv
, Ev
}, 0 },
2938 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2939 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2940 { MOD_TABLE (MOD_0FB2
) },
2941 { "btrS", { Evh1
, Gv
}, 0 },
2942 { MOD_TABLE (MOD_0FB4
) },
2943 { MOD_TABLE (MOD_0FB5
) },
2944 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2945 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2947 { PREFIX_TABLE (PREFIX_0FB8
) },
2948 { "ud1", { XX
}, 0 },
2949 { REG_TABLE (REG_0FBA
) },
2950 { "btcS", { Evh1
, Gv
}, 0 },
2951 { PREFIX_TABLE (PREFIX_0FBC
) },
2952 { PREFIX_TABLE (PREFIX_0FBD
) },
2953 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2954 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2956 { "xaddB", { Ebh1
, Gb
}, 0 },
2957 { "xaddS", { Evh1
, Gv
}, 0 },
2958 { PREFIX_TABLE (PREFIX_0FC2
) },
2959 { PREFIX_TABLE (PREFIX_0FC3
) },
2960 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2961 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2962 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2963 { REG_TABLE (REG_0FC7
) },
2965 { "bswap", { RMeAX
}, 0 },
2966 { "bswap", { RMeCX
}, 0 },
2967 { "bswap", { RMeDX
}, 0 },
2968 { "bswap", { RMeBX
}, 0 },
2969 { "bswap", { RMeSP
}, 0 },
2970 { "bswap", { RMeBP
}, 0 },
2971 { "bswap", { RMeSI
}, 0 },
2972 { "bswap", { RMeDI
}, 0 },
2974 { PREFIX_TABLE (PREFIX_0FD0
) },
2975 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2976 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2977 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2978 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2979 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2980 { PREFIX_TABLE (PREFIX_0FD6
) },
2981 { MOD_TABLE (MOD_0FD7
) },
2983 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2984 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2985 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2986 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2987 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2988 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2989 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2990 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2992 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2993 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2994 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2995 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2996 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2997 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2998 { PREFIX_TABLE (PREFIX_0FE6
) },
2999 { PREFIX_TABLE (PREFIX_0FE7
) },
3001 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
3002 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
3003 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
3004 { "por", { MX
, EM
}, PREFIX_OPCODE
},
3005 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
3006 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
3007 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
3008 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
3010 { PREFIX_TABLE (PREFIX_0FF0
) },
3011 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
3012 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
3013 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
3014 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
3015 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
3016 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
3017 { PREFIX_TABLE (PREFIX_0FF7
) },
3019 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
3020 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
3021 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
3022 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
3023 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
3024 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
3025 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
3029 static const unsigned char onebyte_has_modrm
[256] = {
3030 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3031 /* ------------------------------- */
3032 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3033 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3034 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3035 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3036 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3037 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3038 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3039 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3040 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3041 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3042 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3043 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3044 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3045 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3046 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3047 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3048 /* ------------------------------- */
3049 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3052 static const unsigned char twobyte_has_modrm
[256] = {
3053 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3054 /* ------------------------------- */
3055 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3056 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3057 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3058 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3059 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3060 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3061 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3062 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3063 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3064 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3065 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3066 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3067 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3068 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3069 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3070 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3071 /* ------------------------------- */
3072 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3075 static char obuf
[100];
3077 static char *mnemonicendp
;
3078 static char scratchbuf
[100];
3079 static unsigned char *start_codep
;
3080 static unsigned char *insn_codep
;
3081 static unsigned char *codep
;
3082 static unsigned char *end_codep
;
3083 static int last_lock_prefix
;
3084 static int last_repz_prefix
;
3085 static int last_repnz_prefix
;
3086 static int last_data_prefix
;
3087 static int last_addr_prefix
;
3088 static int last_rex_prefix
;
3089 static int last_seg_prefix
;
3090 static int fwait_prefix
;
3091 /* The active segment register prefix. */
3092 static int active_seg_prefix
;
3093 #define MAX_CODE_LENGTH 15
3094 /* We can up to 14 prefixes since the maximum instruction length is
3096 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3097 static disassemble_info
*the_info
;
3105 static unsigned char need_modrm
;
3115 int register_specifier
;
3122 int mask_register_specifier
;
3128 static unsigned char need_vex
;
3129 static unsigned char need_vex_reg
;
3130 static unsigned char vex_w_done
;
3138 /* If we are accessing mod/rm/reg without need_modrm set, then the
3139 values are stale. Hitting this abort likely indicates that you
3140 need to update onebyte_has_modrm or twobyte_has_modrm. */
3141 #define MODRM_CHECK if (!need_modrm) abort ()
3143 static const char **names64
;
3144 static const char **names32
;
3145 static const char **names16
;
3146 static const char **names8
;
3147 static const char **names8rex
;
3148 static const char **names_seg
;
3149 static const char *index64
;
3150 static const char *index32
;
3151 static const char **index16
;
3152 static const char **names_bnd
;
3154 static const char *intel_names64
[] = {
3155 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3156 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3158 static const char *intel_names32
[] = {
3159 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3160 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3162 static const char *intel_names16
[] = {
3163 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3164 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3166 static const char *intel_names8
[] = {
3167 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3169 static const char *intel_names8rex
[] = {
3170 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3171 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3173 static const char *intel_names_seg
[] = {
3174 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3176 static const char *intel_index64
= "riz";
3177 static const char *intel_index32
= "eiz";
3178 static const char *intel_index16
[] = {
3179 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3182 static const char *att_names64
[] = {
3183 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3184 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3186 static const char *att_names32
[] = {
3187 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3188 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3190 static const char *att_names16
[] = {
3191 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3192 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3194 static const char *att_names8
[] = {
3195 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3197 static const char *att_names8rex
[] = {
3198 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3199 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3201 static const char *att_names_seg
[] = {
3202 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3204 static const char *att_index64
= "%riz";
3205 static const char *att_index32
= "%eiz";
3206 static const char *att_index16
[] = {
3207 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3210 static const char **names_mm
;
3211 static const char *intel_names_mm
[] = {
3212 "mm0", "mm1", "mm2", "mm3",
3213 "mm4", "mm5", "mm6", "mm7"
3215 static const char *att_names_mm
[] = {
3216 "%mm0", "%mm1", "%mm2", "%mm3",
3217 "%mm4", "%mm5", "%mm6", "%mm7"
3220 static const char *intel_names_bnd
[] = {
3221 "bnd0", "bnd1", "bnd2", "bnd3"
3224 static const char *att_names_bnd
[] = {
3225 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3228 static const char **names_xmm
;
3229 static const char *intel_names_xmm
[] = {
3230 "xmm0", "xmm1", "xmm2", "xmm3",
3231 "xmm4", "xmm5", "xmm6", "xmm7",
3232 "xmm8", "xmm9", "xmm10", "xmm11",
3233 "xmm12", "xmm13", "xmm14", "xmm15",
3234 "xmm16", "xmm17", "xmm18", "xmm19",
3235 "xmm20", "xmm21", "xmm22", "xmm23",
3236 "xmm24", "xmm25", "xmm26", "xmm27",
3237 "xmm28", "xmm29", "xmm30", "xmm31"
3239 static const char *att_names_xmm
[] = {
3240 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3241 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3242 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3243 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3244 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3245 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3246 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3247 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3250 static const char **names_ymm
;
3251 static const char *intel_names_ymm
[] = {
3252 "ymm0", "ymm1", "ymm2", "ymm3",
3253 "ymm4", "ymm5", "ymm6", "ymm7",
3254 "ymm8", "ymm9", "ymm10", "ymm11",
3255 "ymm12", "ymm13", "ymm14", "ymm15",
3256 "ymm16", "ymm17", "ymm18", "ymm19",
3257 "ymm20", "ymm21", "ymm22", "ymm23",
3258 "ymm24", "ymm25", "ymm26", "ymm27",
3259 "ymm28", "ymm29", "ymm30", "ymm31"
3261 static const char *att_names_ymm
[] = {
3262 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3263 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3264 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3265 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3266 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3267 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3268 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3269 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3272 static const char **names_zmm
;
3273 static const char *intel_names_zmm
[] = {
3274 "zmm0", "zmm1", "zmm2", "zmm3",
3275 "zmm4", "zmm5", "zmm6", "zmm7",
3276 "zmm8", "zmm9", "zmm10", "zmm11",
3277 "zmm12", "zmm13", "zmm14", "zmm15",
3278 "zmm16", "zmm17", "zmm18", "zmm19",
3279 "zmm20", "zmm21", "zmm22", "zmm23",
3280 "zmm24", "zmm25", "zmm26", "zmm27",
3281 "zmm28", "zmm29", "zmm30", "zmm31"
3283 static const char *att_names_zmm
[] = {
3284 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3285 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3286 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3287 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3288 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3289 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3290 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3291 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3294 static const char **names_mask
;
3295 static const char *intel_names_mask
[] = {
3296 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3298 static const char *att_names_mask
[] = {
3299 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3302 static const char *names_rounding
[] =
3310 static const struct dis386 reg_table
[][8] = {
3313 { "addA", { Ebh1
, Ib
}, 0 },
3314 { "orA", { Ebh1
, Ib
}, 0 },
3315 { "adcA", { Ebh1
, Ib
}, 0 },
3316 { "sbbA", { Ebh1
, Ib
}, 0 },
3317 { "andA", { Ebh1
, Ib
}, 0 },
3318 { "subA", { Ebh1
, Ib
}, 0 },
3319 { "xorA", { Ebh1
, Ib
}, 0 },
3320 { "cmpA", { Eb
, Ib
}, 0 },
3324 { "addQ", { Evh1
, Iv
}, 0 },
3325 { "orQ", { Evh1
, Iv
}, 0 },
3326 { "adcQ", { Evh1
, Iv
}, 0 },
3327 { "sbbQ", { Evh1
, Iv
}, 0 },
3328 { "andQ", { Evh1
, Iv
}, 0 },
3329 { "subQ", { Evh1
, Iv
}, 0 },
3330 { "xorQ", { Evh1
, Iv
}, 0 },
3331 { "cmpQ", { Ev
, Iv
}, 0 },
3335 { "addQ", { Evh1
, sIb
}, 0 },
3336 { "orQ", { Evh1
, sIb
}, 0 },
3337 { "adcQ", { Evh1
, sIb
}, 0 },
3338 { "sbbQ", { Evh1
, sIb
}, 0 },
3339 { "andQ", { Evh1
, sIb
}, 0 },
3340 { "subQ", { Evh1
, sIb
}, 0 },
3341 { "xorQ", { Evh1
, sIb
}, 0 },
3342 { "cmpQ", { Ev
, sIb
}, 0 },
3346 { "popU", { stackEv
}, 0 },
3347 { XOP_8F_TABLE (XOP_09
) },
3351 { XOP_8F_TABLE (XOP_09
) },
3355 { "rolA", { Eb
, Ib
}, 0 },
3356 { "rorA", { Eb
, Ib
}, 0 },
3357 { "rclA", { Eb
, Ib
}, 0 },
3358 { "rcrA", { Eb
, Ib
}, 0 },
3359 { "shlA", { Eb
, Ib
}, 0 },
3360 { "shrA", { Eb
, Ib
}, 0 },
3362 { "sarA", { Eb
, Ib
}, 0 },
3366 { "rolQ", { Ev
, Ib
}, 0 },
3367 { "rorQ", { Ev
, Ib
}, 0 },
3368 { "rclQ", { Ev
, Ib
}, 0 },
3369 { "rcrQ", { Ev
, Ib
}, 0 },
3370 { "shlQ", { Ev
, Ib
}, 0 },
3371 { "shrQ", { Ev
, Ib
}, 0 },
3373 { "sarQ", { Ev
, Ib
}, 0 },
3377 { "movA", { Ebh3
, Ib
}, 0 },
3384 { MOD_TABLE (MOD_C6_REG_7
) },
3388 { "movQ", { Evh3
, Iv
}, 0 },
3395 { MOD_TABLE (MOD_C7_REG_7
) },
3399 { "rolA", { Eb
, I1
}, 0 },
3400 { "rorA", { Eb
, I1
}, 0 },
3401 { "rclA", { Eb
, I1
}, 0 },
3402 { "rcrA", { Eb
, I1
}, 0 },
3403 { "shlA", { Eb
, I1
}, 0 },
3404 { "shrA", { Eb
, I1
}, 0 },
3406 { "sarA", { Eb
, I1
}, 0 },
3410 { "rolQ", { Ev
, I1
}, 0 },
3411 { "rorQ", { Ev
, I1
}, 0 },
3412 { "rclQ", { Ev
, I1
}, 0 },
3413 { "rcrQ", { Ev
, I1
}, 0 },
3414 { "shlQ", { Ev
, I1
}, 0 },
3415 { "shrQ", { Ev
, I1
}, 0 },
3417 { "sarQ", { Ev
, I1
}, 0 },
3421 { "rolA", { Eb
, CL
}, 0 },
3422 { "rorA", { Eb
, CL
}, 0 },
3423 { "rclA", { Eb
, CL
}, 0 },
3424 { "rcrA", { Eb
, CL
}, 0 },
3425 { "shlA", { Eb
, CL
}, 0 },
3426 { "shrA", { Eb
, CL
}, 0 },
3428 { "sarA", { Eb
, CL
}, 0 },
3432 { "rolQ", { Ev
, CL
}, 0 },
3433 { "rorQ", { Ev
, CL
}, 0 },
3434 { "rclQ", { Ev
, CL
}, 0 },
3435 { "rcrQ", { Ev
, CL
}, 0 },
3436 { "shlQ", { Ev
, CL
}, 0 },
3437 { "shrQ", { Ev
, CL
}, 0 },
3439 { "sarQ", { Ev
, CL
}, 0 },
3443 { "testA", { Eb
, Ib
}, 0 },
3445 { "notA", { Ebh1
}, 0 },
3446 { "negA", { Ebh1
}, 0 },
3447 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3448 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3449 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3450 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3454 { "testQ", { Ev
, Iv
}, 0 },
3456 { "notQ", { Evh1
}, 0 },
3457 { "negQ", { Evh1
}, 0 },
3458 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3459 { "imulQ", { Ev
}, 0 },
3460 { "divQ", { Ev
}, 0 },
3461 { "idivQ", { Ev
}, 0 },
3465 { "incA", { Ebh1
}, 0 },
3466 { "decA", { Ebh1
}, 0 },
3470 { "incQ", { Evh1
}, 0 },
3471 { "decQ", { Evh1
}, 0 },
3472 { "call{T|}", { indirEv
, BND
}, 0 },
3473 { MOD_TABLE (MOD_FF_REG_3
) },
3474 { "jmp{T|}", { indirEv
, BND
}, 0 },
3475 { MOD_TABLE (MOD_FF_REG_5
) },
3476 { "pushU", { stackEv
}, 0 },
3481 { "sldtD", { Sv
}, 0 },
3482 { "strD", { Sv
}, 0 },
3483 { "lldt", { Ew
}, 0 },
3484 { "ltr", { Ew
}, 0 },
3485 { "verr", { Ew
}, 0 },
3486 { "verw", { Ew
}, 0 },
3492 { MOD_TABLE (MOD_0F01_REG_0
) },
3493 { MOD_TABLE (MOD_0F01_REG_1
) },
3494 { MOD_TABLE (MOD_0F01_REG_2
) },
3495 { MOD_TABLE (MOD_0F01_REG_3
) },
3496 { "smswD", { Sv
}, 0 },
3498 { "lmsw", { Ew
}, 0 },
3499 { MOD_TABLE (MOD_0F01_REG_7
) },
3503 { "prefetch", { Mb
}, 0 },
3504 { "prefetchw", { Mb
}, 0 },
3505 { "prefetchwt1", { Mb
}, 0 },
3506 { "prefetch", { Mb
}, 0 },
3507 { "prefetch", { Mb
}, 0 },
3508 { "prefetch", { Mb
}, 0 },
3509 { "prefetch", { Mb
}, 0 },
3510 { "prefetch", { Mb
}, 0 },
3514 { MOD_TABLE (MOD_0F18_REG_0
) },
3515 { MOD_TABLE (MOD_0F18_REG_1
) },
3516 { MOD_TABLE (MOD_0F18_REG_2
) },
3517 { MOD_TABLE (MOD_0F18_REG_3
) },
3518 { MOD_TABLE (MOD_0F18_REG_4
) },
3519 { MOD_TABLE (MOD_0F18_REG_5
) },
3520 { MOD_TABLE (MOD_0F18_REG_6
) },
3521 { MOD_TABLE (MOD_0F18_REG_7
) },
3527 { MOD_TABLE (MOD_0F71_REG_2
) },
3529 { MOD_TABLE (MOD_0F71_REG_4
) },
3531 { MOD_TABLE (MOD_0F71_REG_6
) },
3537 { MOD_TABLE (MOD_0F72_REG_2
) },
3539 { MOD_TABLE (MOD_0F72_REG_4
) },
3541 { MOD_TABLE (MOD_0F72_REG_6
) },
3547 { MOD_TABLE (MOD_0F73_REG_2
) },
3548 { MOD_TABLE (MOD_0F73_REG_3
) },
3551 { MOD_TABLE (MOD_0F73_REG_6
) },
3552 { MOD_TABLE (MOD_0F73_REG_7
) },
3556 { "montmul", { { OP_0f07
, 0 } }, 0 },
3557 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3558 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3562 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3563 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3564 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3565 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3566 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3567 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3571 { MOD_TABLE (MOD_0FAE_REG_0
) },
3572 { MOD_TABLE (MOD_0FAE_REG_1
) },
3573 { MOD_TABLE (MOD_0FAE_REG_2
) },
3574 { MOD_TABLE (MOD_0FAE_REG_3
) },
3575 { MOD_TABLE (MOD_0FAE_REG_4
) },
3576 { MOD_TABLE (MOD_0FAE_REG_5
) },
3577 { MOD_TABLE (MOD_0FAE_REG_6
) },
3578 { MOD_TABLE (MOD_0FAE_REG_7
) },
3586 { "btQ", { Ev
, Ib
}, 0 },
3587 { "btsQ", { Evh1
, Ib
}, 0 },
3588 { "btrQ", { Evh1
, Ib
}, 0 },
3589 { "btcQ", { Evh1
, Ib
}, 0 },
3594 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3596 { MOD_TABLE (MOD_0FC7_REG_3
) },
3597 { MOD_TABLE (MOD_0FC7_REG_4
) },
3598 { MOD_TABLE (MOD_0FC7_REG_5
) },
3599 { MOD_TABLE (MOD_0FC7_REG_6
) },
3600 { MOD_TABLE (MOD_0FC7_REG_7
) },
3606 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3608 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3610 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3616 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3618 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3620 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3626 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3627 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3630 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3631 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3637 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3638 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3640 /* REG_VEX_0F38F3 */
3643 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3644 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3645 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3649 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3650 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3654 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3655 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3657 /* REG_XOP_TBM_01 */
3660 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3661 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3662 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3663 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3664 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3665 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3666 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3668 /* REG_XOP_TBM_02 */
3671 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3676 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3678 #define NEED_REG_TABLE
3679 #include "i386-dis-evex.h"
3680 #undef NEED_REG_TABLE
3683 static const struct dis386 prefix_table
[][4] = {
3686 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3687 { "pause", { XX
}, 0 },
3688 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3689 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3694 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3695 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3696 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3697 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3702 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3703 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3704 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3705 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3710 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3711 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3712 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3713 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3718 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3719 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3720 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3725 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3726 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3727 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3728 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3733 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3734 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3735 { "bndmov", { Ebnd
, Gbnd
}, 0 },
3736 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3741 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3742 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_OPCODE
},
3743 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3744 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3749 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3750 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3751 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3752 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3757 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3758 { "cvttss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3759 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3760 { "cvttsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3765 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3766 { "cvtss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3767 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3768 { "cvtsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3773 { "ucomiss",{ XM
, EXd
}, 0 },
3775 { "ucomisd",{ XM
, EXq
}, 0 },
3780 { "comiss", { XM
, EXd
}, 0 },
3782 { "comisd", { XM
, EXq
}, 0 },
3787 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3788 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3789 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3790 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3795 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3796 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3801 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3802 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3807 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3808 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3809 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3810 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3815 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3816 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3817 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3818 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3823 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3824 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3825 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3826 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3831 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3832 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3833 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3838 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3839 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3840 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3841 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3846 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3847 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3848 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3849 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3854 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3855 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3856 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3857 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3862 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3863 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3864 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3865 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3870 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3872 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3877 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3879 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3884 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3886 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3893 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3900 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3905 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3906 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3907 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3912 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3913 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3914 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3915 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3918 /* PREFIX_0F73_REG_3 */
3922 { "psrldq", { XS
, Ib
}, 0 },
3925 /* PREFIX_0F73_REG_7 */
3929 { "pslldq", { XS
, Ib
}, 0 },
3934 {"vmread", { Em
, Gm
}, 0 },
3936 {"extrq", { XS
, Ib
, Ib
}, 0 },
3937 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3942 {"vmwrite", { Gm
, Em
}, 0 },
3944 {"extrq", { XM
, XS
}, 0 },
3945 {"insertq", { XM
, XS
}, 0 },
3952 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3953 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3960 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3961 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3966 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3967 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3968 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3973 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3974 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3975 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3978 /* PREFIX_0FAE_REG_0 */
3981 { "rdfsbase", { Ev
}, 0 },
3984 /* PREFIX_0FAE_REG_1 */
3987 { "rdgsbase", { Ev
}, 0 },
3990 /* PREFIX_0FAE_REG_2 */
3993 { "wrfsbase", { Ev
}, 0 },
3996 /* PREFIX_0FAE_REG_3 */
3999 { "wrgsbase", { Ev
}, 0 },
4002 /* PREFIX_0FAE_REG_6 */
4004 { "xsaveopt", { FXSAVE
}, 0 },
4006 { "clwb", { Mb
}, 0 },
4009 /* PREFIX_0FAE_REG_7 */
4011 { "clflush", { Mb
}, 0 },
4013 { "clflushopt", { Mb
}, 0 },
4016 /* PREFIX_RM_0_0FAE_REG_7 */
4018 { "sfence", { Skip_MODRM
}, 0 },
4020 { "pcommit", { Skip_MODRM
}, 0 },
4026 { "popcntS", { Gv
, Ev
}, 0 },
4031 { "bsfS", { Gv
, Ev
}, 0 },
4032 { "tzcntS", { Gv
, Ev
}, 0 },
4033 { "bsfS", { Gv
, Ev
}, 0 },
4038 { "bsrS", { Gv
, Ev
}, 0 },
4039 { "lzcntS", { Gv
, Ev
}, 0 },
4040 { "bsrS", { Gv
, Ev
}, 0 },
4045 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4046 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4047 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4048 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4053 { "movntiS", { Ma
, Gv
}, PREFIX_OPCODE
},
4056 /* PREFIX_MOD_0_0FC7_REG_6 */
4058 { "vmptrld",{ Mq
}, 0 },
4059 { "vmxon", { Mq
}, 0 },
4060 { "vmclear",{ Mq
}, 0 },
4063 /* PREFIX_MOD_3_0FC7_REG_6 */
4065 { "rdrand", { Ev
}, 0 },
4067 { "rdrand", { Ev
}, 0 }
4070 /* PREFIX_MOD_3_0FC7_REG_7 */
4072 { "rdseed", { Ev
}, 0 },
4074 { "rdseed", { Ev
}, 0 },
4081 { "addsubpd", { XM
, EXx
}, 0 },
4082 { "addsubps", { XM
, EXx
}, 0 },
4088 { "movq2dq",{ XM
, MS
}, 0 },
4089 { "movq", { EXqS
, XM
}, 0 },
4090 { "movdq2q",{ MX
, XS
}, 0 },
4096 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4097 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4098 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4103 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4105 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4113 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4118 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4120 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4127 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4134 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4141 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4148 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4155 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4162 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4169 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4176 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4183 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4190 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4197 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4204 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4211 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4218 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4225 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4232 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4239 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4246 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4253 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4260 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4267 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4274 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4281 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4288 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4295 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4302 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4309 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4316 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4323 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4330 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4337 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4344 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4351 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4358 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4363 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4368 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4373 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4378 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4383 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4388 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4395 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4402 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4409 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4416 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4423 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4428 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4430 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4431 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4436 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4438 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4439 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4445 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4446 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4454 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4461 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4468 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4475 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4482 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4489 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4496 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4503 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4510 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4517 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4524 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4531 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4538 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4545 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4552 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4559 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4566 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4573 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4580 { "pcmpestrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4587 { "pcmpestri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4594 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4601 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4606 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4613 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4616 /* PREFIX_VEX_0F10 */
4618 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4619 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4620 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4621 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4624 /* PREFIX_VEX_0F11 */
4626 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4627 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4628 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4629 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4632 /* PREFIX_VEX_0F12 */
4634 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4635 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4636 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4637 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4640 /* PREFIX_VEX_0F16 */
4642 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4643 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4644 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4647 /* PREFIX_VEX_0F2A */
4650 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4652 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4655 /* PREFIX_VEX_0F2C */
4658 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4660 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4663 /* PREFIX_VEX_0F2D */
4666 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4668 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4671 /* PREFIX_VEX_0F2E */
4673 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4675 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4678 /* PREFIX_VEX_0F2F */
4680 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4682 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4685 /* PREFIX_VEX_0F41 */
4687 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4689 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4692 /* PREFIX_VEX_0F42 */
4694 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4696 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4699 /* PREFIX_VEX_0F44 */
4701 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4703 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4706 /* PREFIX_VEX_0F45 */
4708 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4710 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4713 /* PREFIX_VEX_0F46 */
4715 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4717 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4720 /* PREFIX_VEX_0F47 */
4722 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4724 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4727 /* PREFIX_VEX_0F4A */
4729 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4731 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4734 /* PREFIX_VEX_0F4B */
4736 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4738 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4741 /* PREFIX_VEX_0F51 */
4743 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4744 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4745 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4746 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4749 /* PREFIX_VEX_0F52 */
4751 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4752 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
4755 /* PREFIX_VEX_0F53 */
4757 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
4758 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
4761 /* PREFIX_VEX_0F58 */
4763 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
4764 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
4765 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
4766 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
4769 /* PREFIX_VEX_0F59 */
4771 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
4772 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
4773 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
4774 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
4777 /* PREFIX_VEX_0F5A */
4779 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
4780 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
4781 { "vcvtpd2ps%XY", { XMM
, EXx
}, 0 },
4782 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
4785 /* PREFIX_VEX_0F5B */
4787 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
4788 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
4789 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
4792 /* PREFIX_VEX_0F5C */
4794 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
4795 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
4796 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
4797 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
4800 /* PREFIX_VEX_0F5D */
4802 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
4803 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
4804 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
4805 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
4808 /* PREFIX_VEX_0F5E */
4810 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
4811 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
4812 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
4813 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
4816 /* PREFIX_VEX_0F5F */
4818 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
4819 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
4820 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
4821 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
4824 /* PREFIX_VEX_0F60 */
4828 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
4831 /* PREFIX_VEX_0F61 */
4835 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
4838 /* PREFIX_VEX_0F62 */
4842 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
4845 /* PREFIX_VEX_0F63 */
4849 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
4852 /* PREFIX_VEX_0F64 */
4856 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
4859 /* PREFIX_VEX_0F65 */
4863 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
4866 /* PREFIX_VEX_0F66 */
4870 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
4873 /* PREFIX_VEX_0F67 */
4877 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
4880 /* PREFIX_VEX_0F68 */
4884 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
4887 /* PREFIX_VEX_0F69 */
4891 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
4894 /* PREFIX_VEX_0F6A */
4898 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
4901 /* PREFIX_VEX_0F6B */
4905 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
4908 /* PREFIX_VEX_0F6C */
4912 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
4915 /* PREFIX_VEX_0F6D */
4919 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
4922 /* PREFIX_VEX_0F6E */
4926 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4929 /* PREFIX_VEX_0F6F */
4932 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
4933 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
4936 /* PREFIX_VEX_0F70 */
4939 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
4940 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
4941 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
4944 /* PREFIX_VEX_0F71_REG_2 */
4948 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
4951 /* PREFIX_VEX_0F71_REG_4 */
4955 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
4958 /* PREFIX_VEX_0F71_REG_6 */
4962 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
4965 /* PREFIX_VEX_0F72_REG_2 */
4969 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
4972 /* PREFIX_VEX_0F72_REG_4 */
4976 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
4979 /* PREFIX_VEX_0F72_REG_6 */
4983 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
4986 /* PREFIX_VEX_0F73_REG_2 */
4990 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
4993 /* PREFIX_VEX_0F73_REG_3 */
4997 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
5000 /* PREFIX_VEX_0F73_REG_6 */
5004 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
5007 /* PREFIX_VEX_0F73_REG_7 */
5011 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
5014 /* PREFIX_VEX_0F74 */
5018 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
5021 /* PREFIX_VEX_0F75 */
5025 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
5028 /* PREFIX_VEX_0F76 */
5032 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
5035 /* PREFIX_VEX_0F77 */
5037 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
5040 /* PREFIX_VEX_0F7C */
5044 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
5045 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
5048 /* PREFIX_VEX_0F7D */
5052 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
5053 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
5056 /* PREFIX_VEX_0F7E */
5059 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5060 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5063 /* PREFIX_VEX_0F7F */
5066 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
5067 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
5070 /* PREFIX_VEX_0F90 */
5072 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5074 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5077 /* PREFIX_VEX_0F91 */
5079 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5081 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5084 /* PREFIX_VEX_0F92 */
5086 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5088 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5089 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5092 /* PREFIX_VEX_0F93 */
5094 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5096 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5097 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5100 /* PREFIX_VEX_0F98 */
5102 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5104 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5107 /* PREFIX_VEX_0F99 */
5109 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5111 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5114 /* PREFIX_VEX_0FC2 */
5116 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
5117 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
5118 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
5119 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
5122 /* PREFIX_VEX_0FC4 */
5126 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5129 /* PREFIX_VEX_0FC5 */
5133 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5136 /* PREFIX_VEX_0FD0 */
5140 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
5141 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
5144 /* PREFIX_VEX_0FD1 */
5148 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
5151 /* PREFIX_VEX_0FD2 */
5155 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
5158 /* PREFIX_VEX_0FD3 */
5162 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
5165 /* PREFIX_VEX_0FD4 */
5169 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
5172 /* PREFIX_VEX_0FD5 */
5176 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
5179 /* PREFIX_VEX_0FD6 */
5183 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5186 /* PREFIX_VEX_0FD7 */
5190 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5193 /* PREFIX_VEX_0FD8 */
5197 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
5200 /* PREFIX_VEX_0FD9 */
5204 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
5207 /* PREFIX_VEX_0FDA */
5211 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
5214 /* PREFIX_VEX_0FDB */
5218 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
5221 /* PREFIX_VEX_0FDC */
5225 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
5228 /* PREFIX_VEX_0FDD */
5232 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
5235 /* PREFIX_VEX_0FDE */
5239 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
5242 /* PREFIX_VEX_0FDF */
5246 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
5249 /* PREFIX_VEX_0FE0 */
5253 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
5256 /* PREFIX_VEX_0FE1 */
5260 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
5263 /* PREFIX_VEX_0FE2 */
5267 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
5270 /* PREFIX_VEX_0FE3 */
5274 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
5277 /* PREFIX_VEX_0FE4 */
5281 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
5284 /* PREFIX_VEX_0FE5 */
5288 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
5291 /* PREFIX_VEX_0FE6 */
5294 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
5295 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
5296 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5299 /* PREFIX_VEX_0FE7 */
5303 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5306 /* PREFIX_VEX_0FE8 */
5310 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5313 /* PREFIX_VEX_0FE9 */
5317 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5320 /* PREFIX_VEX_0FEA */
5324 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5327 /* PREFIX_VEX_0FEB */
5331 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5334 /* PREFIX_VEX_0FEC */
5338 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5341 /* PREFIX_VEX_0FED */
5345 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5348 /* PREFIX_VEX_0FEE */
5352 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5355 /* PREFIX_VEX_0FEF */
5359 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5362 /* PREFIX_VEX_0FF0 */
5367 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5370 /* PREFIX_VEX_0FF1 */
5374 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5377 /* PREFIX_VEX_0FF2 */
5381 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5384 /* PREFIX_VEX_0FF3 */
5388 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5391 /* PREFIX_VEX_0FF4 */
5395 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5398 /* PREFIX_VEX_0FF5 */
5402 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5405 /* PREFIX_VEX_0FF6 */
5409 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5412 /* PREFIX_VEX_0FF7 */
5416 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5419 /* PREFIX_VEX_0FF8 */
5423 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5426 /* PREFIX_VEX_0FF9 */
5430 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5433 /* PREFIX_VEX_0FFA */
5437 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5440 /* PREFIX_VEX_0FFB */
5444 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5447 /* PREFIX_VEX_0FFC */
5451 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5454 /* PREFIX_VEX_0FFD */
5458 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5461 /* PREFIX_VEX_0FFE */
5465 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5468 /* PREFIX_VEX_0F3800 */
5472 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5475 /* PREFIX_VEX_0F3801 */
5479 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5482 /* PREFIX_VEX_0F3802 */
5486 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5489 /* PREFIX_VEX_0F3803 */
5493 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5496 /* PREFIX_VEX_0F3804 */
5500 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5503 /* PREFIX_VEX_0F3805 */
5507 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5510 /* PREFIX_VEX_0F3806 */
5514 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5517 /* PREFIX_VEX_0F3807 */
5521 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5524 /* PREFIX_VEX_0F3808 */
5528 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5531 /* PREFIX_VEX_0F3809 */
5535 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5538 /* PREFIX_VEX_0F380A */
5542 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5545 /* PREFIX_VEX_0F380B */
5549 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5552 /* PREFIX_VEX_0F380C */
5556 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5559 /* PREFIX_VEX_0F380D */
5563 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5566 /* PREFIX_VEX_0F380E */
5570 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5573 /* PREFIX_VEX_0F380F */
5577 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5580 /* PREFIX_VEX_0F3813 */
5584 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5587 /* PREFIX_VEX_0F3816 */
5591 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5594 /* PREFIX_VEX_0F3817 */
5598 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5601 /* PREFIX_VEX_0F3818 */
5605 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5608 /* PREFIX_VEX_0F3819 */
5612 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5615 /* PREFIX_VEX_0F381A */
5619 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5622 /* PREFIX_VEX_0F381C */
5626 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5629 /* PREFIX_VEX_0F381D */
5633 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5636 /* PREFIX_VEX_0F381E */
5640 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5643 /* PREFIX_VEX_0F3820 */
5647 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5650 /* PREFIX_VEX_0F3821 */
5654 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5657 /* PREFIX_VEX_0F3822 */
5661 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5664 /* PREFIX_VEX_0F3823 */
5668 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5671 /* PREFIX_VEX_0F3824 */
5675 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5678 /* PREFIX_VEX_0F3825 */
5682 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5685 /* PREFIX_VEX_0F3828 */
5689 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5692 /* PREFIX_VEX_0F3829 */
5696 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5699 /* PREFIX_VEX_0F382A */
5703 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5706 /* PREFIX_VEX_0F382B */
5710 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5713 /* PREFIX_VEX_0F382C */
5717 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5720 /* PREFIX_VEX_0F382D */
5724 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5727 /* PREFIX_VEX_0F382E */
5731 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5734 /* PREFIX_VEX_0F382F */
5738 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5741 /* PREFIX_VEX_0F3830 */
5745 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5748 /* PREFIX_VEX_0F3831 */
5752 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
5755 /* PREFIX_VEX_0F3832 */
5759 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
5762 /* PREFIX_VEX_0F3833 */
5766 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
5769 /* PREFIX_VEX_0F3834 */
5773 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
5776 /* PREFIX_VEX_0F3835 */
5780 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
5783 /* PREFIX_VEX_0F3836 */
5787 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5790 /* PREFIX_VEX_0F3837 */
5794 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
5797 /* PREFIX_VEX_0F3838 */
5801 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
5804 /* PREFIX_VEX_0F3839 */
5808 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
5811 /* PREFIX_VEX_0F383A */
5815 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
5818 /* PREFIX_VEX_0F383B */
5822 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
5825 /* PREFIX_VEX_0F383C */
5829 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
5832 /* PREFIX_VEX_0F383D */
5836 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
5839 /* PREFIX_VEX_0F383E */
5843 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
5846 /* PREFIX_VEX_0F383F */
5850 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
5853 /* PREFIX_VEX_0F3840 */
5857 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
5860 /* PREFIX_VEX_0F3841 */
5864 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5867 /* PREFIX_VEX_0F3845 */
5871 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5874 /* PREFIX_VEX_0F3846 */
5878 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5881 /* PREFIX_VEX_0F3847 */
5885 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5888 /* PREFIX_VEX_0F3858 */
5892 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5895 /* PREFIX_VEX_0F3859 */
5899 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5902 /* PREFIX_VEX_0F385A */
5906 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5909 /* PREFIX_VEX_0F3878 */
5913 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5916 /* PREFIX_VEX_0F3879 */
5920 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5923 /* PREFIX_VEX_0F388C */
5927 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5930 /* PREFIX_VEX_0F388E */
5934 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5937 /* PREFIX_VEX_0F3890 */
5941 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5944 /* PREFIX_VEX_0F3891 */
5948 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5951 /* PREFIX_VEX_0F3892 */
5955 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5958 /* PREFIX_VEX_0F3893 */
5962 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5965 /* PREFIX_VEX_0F3896 */
5969 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
5972 /* PREFIX_VEX_0F3897 */
5976 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
5979 /* PREFIX_VEX_0F3898 */
5983 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
5986 /* PREFIX_VEX_0F3899 */
5990 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
5993 /* PREFIX_VEX_0F389A */
5997 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6000 /* PREFIX_VEX_0F389B */
6004 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6007 /* PREFIX_VEX_0F389C */
6011 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6014 /* PREFIX_VEX_0F389D */
6018 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6021 /* PREFIX_VEX_0F389E */
6025 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6028 /* PREFIX_VEX_0F389F */
6032 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6035 /* PREFIX_VEX_0F38A6 */
6039 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6043 /* PREFIX_VEX_0F38A7 */
6047 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6050 /* PREFIX_VEX_0F38A8 */
6054 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6057 /* PREFIX_VEX_0F38A9 */
6061 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6064 /* PREFIX_VEX_0F38AA */
6068 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6071 /* PREFIX_VEX_0F38AB */
6075 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6078 /* PREFIX_VEX_0F38AC */
6082 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6085 /* PREFIX_VEX_0F38AD */
6089 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6092 /* PREFIX_VEX_0F38AE */
6096 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6099 /* PREFIX_VEX_0F38AF */
6103 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6106 /* PREFIX_VEX_0F38B6 */
6110 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6113 /* PREFIX_VEX_0F38B7 */
6117 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6120 /* PREFIX_VEX_0F38B8 */
6124 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6127 /* PREFIX_VEX_0F38B9 */
6131 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6134 /* PREFIX_VEX_0F38BA */
6138 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6141 /* PREFIX_VEX_0F38BB */
6145 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6148 /* PREFIX_VEX_0F38BC */
6152 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6155 /* PREFIX_VEX_0F38BD */
6159 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6162 /* PREFIX_VEX_0F38BE */
6166 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6169 /* PREFIX_VEX_0F38BF */
6173 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6176 /* PREFIX_VEX_0F38DB */
6180 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6183 /* PREFIX_VEX_0F38DC */
6187 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
6190 /* PREFIX_VEX_0F38DD */
6194 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
6197 /* PREFIX_VEX_0F38DE */
6201 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
6204 /* PREFIX_VEX_0F38DF */
6208 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
6211 /* PREFIX_VEX_0F38F2 */
6213 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6216 /* PREFIX_VEX_0F38F3_REG_1 */
6218 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6221 /* PREFIX_VEX_0F38F3_REG_2 */
6223 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6226 /* PREFIX_VEX_0F38F3_REG_3 */
6228 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6231 /* PREFIX_VEX_0F38F5 */
6233 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6234 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6236 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6239 /* PREFIX_VEX_0F38F6 */
6244 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6247 /* PREFIX_VEX_0F38F7 */
6249 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6250 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6251 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6252 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6255 /* PREFIX_VEX_0F3A00 */
6259 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6262 /* PREFIX_VEX_0F3A01 */
6266 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6269 /* PREFIX_VEX_0F3A02 */
6273 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6276 /* PREFIX_VEX_0F3A04 */
6280 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6283 /* PREFIX_VEX_0F3A05 */
6287 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6290 /* PREFIX_VEX_0F3A06 */
6294 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6297 /* PREFIX_VEX_0F3A08 */
6301 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6304 /* PREFIX_VEX_0F3A09 */
6308 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6311 /* PREFIX_VEX_0F3A0A */
6315 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6318 /* PREFIX_VEX_0F3A0B */
6322 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6325 /* PREFIX_VEX_0F3A0C */
6329 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6332 /* PREFIX_VEX_0F3A0D */
6336 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6339 /* PREFIX_VEX_0F3A0E */
6343 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6346 /* PREFIX_VEX_0F3A0F */
6350 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6353 /* PREFIX_VEX_0F3A14 */
6357 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6360 /* PREFIX_VEX_0F3A15 */
6364 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6367 /* PREFIX_VEX_0F3A16 */
6371 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6374 /* PREFIX_VEX_0F3A17 */
6378 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6381 /* PREFIX_VEX_0F3A18 */
6385 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6388 /* PREFIX_VEX_0F3A19 */
6392 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6395 /* PREFIX_VEX_0F3A1D */
6399 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6402 /* PREFIX_VEX_0F3A20 */
6406 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6409 /* PREFIX_VEX_0F3A21 */
6413 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6416 /* PREFIX_VEX_0F3A22 */
6420 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6423 /* PREFIX_VEX_0F3A30 */
6427 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6430 /* PREFIX_VEX_0F3A31 */
6434 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6437 /* PREFIX_VEX_0F3A32 */
6441 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6444 /* PREFIX_VEX_0F3A33 */
6448 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6451 /* PREFIX_VEX_0F3A38 */
6455 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6458 /* PREFIX_VEX_0F3A39 */
6462 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6465 /* PREFIX_VEX_0F3A40 */
6469 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6472 /* PREFIX_VEX_0F3A41 */
6476 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6479 /* PREFIX_VEX_0F3A42 */
6483 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6486 /* PREFIX_VEX_0F3A44 */
6490 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
6493 /* PREFIX_VEX_0F3A46 */
6497 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6500 /* PREFIX_VEX_0F3A48 */
6504 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6507 /* PREFIX_VEX_0F3A49 */
6511 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6514 /* PREFIX_VEX_0F3A4A */
6518 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6521 /* PREFIX_VEX_0F3A4B */
6525 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6528 /* PREFIX_VEX_0F3A4C */
6532 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6535 /* PREFIX_VEX_0F3A5C */
6539 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6542 /* PREFIX_VEX_0F3A5D */
6546 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6549 /* PREFIX_VEX_0F3A5E */
6553 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6556 /* PREFIX_VEX_0F3A5F */
6560 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6563 /* PREFIX_VEX_0F3A60 */
6567 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6571 /* PREFIX_VEX_0F3A61 */
6575 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6578 /* PREFIX_VEX_0F3A62 */
6582 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6585 /* PREFIX_VEX_0F3A63 */
6589 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6592 /* PREFIX_VEX_0F3A68 */
6596 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6599 /* PREFIX_VEX_0F3A69 */
6603 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6606 /* PREFIX_VEX_0F3A6A */
6610 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6613 /* PREFIX_VEX_0F3A6B */
6617 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6620 /* PREFIX_VEX_0F3A6C */
6624 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6627 /* PREFIX_VEX_0F3A6D */
6631 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6634 /* PREFIX_VEX_0F3A6E */
6638 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6641 /* PREFIX_VEX_0F3A6F */
6645 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6648 /* PREFIX_VEX_0F3A78 */
6652 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6655 /* PREFIX_VEX_0F3A79 */
6659 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6662 /* PREFIX_VEX_0F3A7A */
6666 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6669 /* PREFIX_VEX_0F3A7B */
6673 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6676 /* PREFIX_VEX_0F3A7C */
6680 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6684 /* PREFIX_VEX_0F3A7D */
6688 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6691 /* PREFIX_VEX_0F3A7E */
6695 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6698 /* PREFIX_VEX_0F3A7F */
6702 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6705 /* PREFIX_VEX_0F3ADF */
6709 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6712 /* PREFIX_VEX_0F3AF0 */
6717 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6720 #define NEED_PREFIX_TABLE
6721 #include "i386-dis-evex.h"
6722 #undef NEED_PREFIX_TABLE
6725 static const struct dis386 x86_64_table
[][2] = {
6728 { "pushP", { es
}, 0 },
6733 { "popP", { es
}, 0 },
6738 { "pushP", { cs
}, 0 },
6743 { "pushP", { ss
}, 0 },
6748 { "popP", { ss
}, 0 },
6753 { "pushP", { ds
}, 0 },
6758 { "popP", { ds
}, 0 },
6763 { "daa", { XX
}, 0 },
6768 { "das", { XX
}, 0 },
6773 { "aaa", { XX
}, 0 },
6778 { "aas", { XX
}, 0 },
6783 { "pushaP", { XX
}, 0 },
6788 { "popaP", { XX
}, 0 },
6793 { MOD_TABLE (MOD_62_32BIT
) },
6794 { EVEX_TABLE (EVEX_0F
) },
6799 { "arpl", { Ew
, Gw
}, 0 },
6800 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6805 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6806 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6811 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6812 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6817 { "Jcall{T|}", { Ap
}, 0 },
6822 { MOD_TABLE (MOD_C4_32BIT
) },
6823 { VEX_C4_TABLE (VEX_0F
) },
6828 { MOD_TABLE (MOD_C5_32BIT
) },
6829 { VEX_C5_TABLE (VEX_0F
) },
6834 { "into", { XX
}, 0 },
6839 { "aam", { Ib
}, 0 },
6844 { "aad", { Ib
}, 0 },
6849 { "callP", { Jv
, BND
}, 0 },
6850 { "call@", { Jv
, BND
}, 0 }
6855 { "jmpP", { Jv
, BND
}, 0 },
6856 { "jmp@", { Jv
, BND
}, 0 }
6861 { "Jjmp{T|}", { Ap
}, 0 },
6864 /* X86_64_0F01_REG_0 */
6866 { "sgdt{Q|IQ}", { M
}, 0 },
6867 { "sgdt", { M
}, 0 },
6870 /* X86_64_0F01_REG_1 */
6872 { "sidt{Q|IQ}", { M
}, 0 },
6873 { "sidt", { M
}, 0 },
6876 /* X86_64_0F01_REG_2 */
6878 { "lgdt{Q|Q}", { M
}, 0 },
6879 { "lgdt", { M
}, 0 },
6882 /* X86_64_0F01_REG_3 */
6884 { "lidt{Q|Q}", { M
}, 0 },
6885 { "lidt", { M
}, 0 },
6889 static const struct dis386 three_byte_table
[][256] = {
6891 /* THREE_BYTE_0F38 */
6894 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6895 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6896 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6897 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6898 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6899 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6900 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6901 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6903 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6904 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6905 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6906 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6912 { PREFIX_TABLE (PREFIX_0F3810
) },
6916 { PREFIX_TABLE (PREFIX_0F3814
) },
6917 { PREFIX_TABLE (PREFIX_0F3815
) },
6919 { PREFIX_TABLE (PREFIX_0F3817
) },
6925 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
6926 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
6927 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
6930 { PREFIX_TABLE (PREFIX_0F3820
) },
6931 { PREFIX_TABLE (PREFIX_0F3821
) },
6932 { PREFIX_TABLE (PREFIX_0F3822
) },
6933 { PREFIX_TABLE (PREFIX_0F3823
) },
6934 { PREFIX_TABLE (PREFIX_0F3824
) },
6935 { PREFIX_TABLE (PREFIX_0F3825
) },
6939 { PREFIX_TABLE (PREFIX_0F3828
) },
6940 { PREFIX_TABLE (PREFIX_0F3829
) },
6941 { PREFIX_TABLE (PREFIX_0F382A
) },
6942 { PREFIX_TABLE (PREFIX_0F382B
) },
6948 { PREFIX_TABLE (PREFIX_0F3830
) },
6949 { PREFIX_TABLE (PREFIX_0F3831
) },
6950 { PREFIX_TABLE (PREFIX_0F3832
) },
6951 { PREFIX_TABLE (PREFIX_0F3833
) },
6952 { PREFIX_TABLE (PREFIX_0F3834
) },
6953 { PREFIX_TABLE (PREFIX_0F3835
) },
6955 { PREFIX_TABLE (PREFIX_0F3837
) },
6957 { PREFIX_TABLE (PREFIX_0F3838
) },
6958 { PREFIX_TABLE (PREFIX_0F3839
) },
6959 { PREFIX_TABLE (PREFIX_0F383A
) },
6960 { PREFIX_TABLE (PREFIX_0F383B
) },
6961 { PREFIX_TABLE (PREFIX_0F383C
) },
6962 { PREFIX_TABLE (PREFIX_0F383D
) },
6963 { PREFIX_TABLE (PREFIX_0F383E
) },
6964 { PREFIX_TABLE (PREFIX_0F383F
) },
6966 { PREFIX_TABLE (PREFIX_0F3840
) },
6967 { PREFIX_TABLE (PREFIX_0F3841
) },
7038 { PREFIX_TABLE (PREFIX_0F3880
) },
7039 { PREFIX_TABLE (PREFIX_0F3881
) },
7040 { PREFIX_TABLE (PREFIX_0F3882
) },
7119 { PREFIX_TABLE (PREFIX_0F38C8
) },
7120 { PREFIX_TABLE (PREFIX_0F38C9
) },
7121 { PREFIX_TABLE (PREFIX_0F38CA
) },
7122 { PREFIX_TABLE (PREFIX_0F38CB
) },
7123 { PREFIX_TABLE (PREFIX_0F38CC
) },
7124 { PREFIX_TABLE (PREFIX_0F38CD
) },
7140 { PREFIX_TABLE (PREFIX_0F38DB
) },
7141 { PREFIX_TABLE (PREFIX_0F38DC
) },
7142 { PREFIX_TABLE (PREFIX_0F38DD
) },
7143 { PREFIX_TABLE (PREFIX_0F38DE
) },
7144 { PREFIX_TABLE (PREFIX_0F38DF
) },
7164 { PREFIX_TABLE (PREFIX_0F38F0
) },
7165 { PREFIX_TABLE (PREFIX_0F38F1
) },
7170 { PREFIX_TABLE (PREFIX_0F38F6
) },
7182 /* THREE_BYTE_0F3A */
7194 { PREFIX_TABLE (PREFIX_0F3A08
) },
7195 { PREFIX_TABLE (PREFIX_0F3A09
) },
7196 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7197 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7198 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7199 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7200 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7201 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7207 { PREFIX_TABLE (PREFIX_0F3A14
) },
7208 { PREFIX_TABLE (PREFIX_0F3A15
) },
7209 { PREFIX_TABLE (PREFIX_0F3A16
) },
7210 { PREFIX_TABLE (PREFIX_0F3A17
) },
7221 { PREFIX_TABLE (PREFIX_0F3A20
) },
7222 { PREFIX_TABLE (PREFIX_0F3A21
) },
7223 { PREFIX_TABLE (PREFIX_0F3A22
) },
7257 { PREFIX_TABLE (PREFIX_0F3A40
) },
7258 { PREFIX_TABLE (PREFIX_0F3A41
) },
7259 { PREFIX_TABLE (PREFIX_0F3A42
) },
7261 { PREFIX_TABLE (PREFIX_0F3A44
) },
7293 { PREFIX_TABLE (PREFIX_0F3A60
) },
7294 { PREFIX_TABLE (PREFIX_0F3A61
) },
7295 { PREFIX_TABLE (PREFIX_0F3A62
) },
7296 { PREFIX_TABLE (PREFIX_0F3A63
) },
7414 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7435 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7474 /* THREE_BYTE_0F7A */
7513 { "ptest", { XX
}, PREFIX_OPCODE
},
7550 { "phaddbw", { XM
, EXq
}, PREFIX_OPCODE
},
7551 { "phaddbd", { XM
, EXq
}, PREFIX_OPCODE
},
7552 { "phaddbq", { XM
, EXq
}, PREFIX_OPCODE
},
7555 { "phaddwd", { XM
, EXq
}, PREFIX_OPCODE
},
7556 { "phaddwq", { XM
, EXq
}, PREFIX_OPCODE
},
7561 { "phadddq", { XM
, EXq
}, PREFIX_OPCODE
},
7568 { "phaddubw", { XM
, EXq
}, PREFIX_OPCODE
},
7569 { "phaddubd", { XM
, EXq
}, PREFIX_OPCODE
},
7570 { "phaddubq", { XM
, EXq
}, PREFIX_OPCODE
},
7573 { "phadduwd", { XM
, EXq
}, PREFIX_OPCODE
},
7574 { "phadduwq", { XM
, EXq
}, PREFIX_OPCODE
},
7579 { "phaddudq", { XM
, EXq
}, PREFIX_OPCODE
},
7586 { "phsubbw", { XM
, EXq
}, PREFIX_OPCODE
},
7587 { "phsubbd", { XM
, EXq
}, PREFIX_OPCODE
},
7588 { "phsubbq", { XM
, EXq
}, PREFIX_OPCODE
},
7767 static const struct dis386 xop_table
[][256] = {
7920 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7921 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7922 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7930 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7931 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7938 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7939 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7940 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7948 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7949 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7953 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7954 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7957 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7975 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7987 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7988 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7989 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7990 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
8000 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
8001 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
8002 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
8003 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
8036 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
8037 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
8038 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
8039 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
8063 { REG_TABLE (REG_XOP_TBM_01
) },
8064 { REG_TABLE (REG_XOP_TBM_02
) },
8082 { REG_TABLE (REG_XOP_LWPCB
) },
8206 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8207 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8208 { "vfrczss", { XM
, EXd
}, 0 },
8209 { "vfrczsd", { XM
, EXq
}, 0 },
8224 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8225 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8226 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8227 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8228 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8229 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8230 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8231 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8233 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8234 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8235 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8236 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8279 { "vphaddbw", { XM
, EXxmm
}, 0 },
8280 { "vphaddbd", { XM
, EXxmm
}, 0 },
8281 { "vphaddbq", { XM
, EXxmm
}, 0 },
8284 { "vphaddwd", { XM
, EXxmm
}, 0 },
8285 { "vphaddwq", { XM
, EXxmm
}, 0 },
8290 { "vphadddq", { XM
, EXxmm
}, 0 },
8297 { "vphaddubw", { XM
, EXxmm
}, 0 },
8298 { "vphaddubd", { XM
, EXxmm
}, 0 },
8299 { "vphaddubq", { XM
, EXxmm
}, 0 },
8302 { "vphadduwd", { XM
, EXxmm
}, 0 },
8303 { "vphadduwq", { XM
, EXxmm
}, 0 },
8308 { "vphaddudq", { XM
, EXxmm
}, 0 },
8315 { "vphsubbw", { XM
, EXxmm
}, 0 },
8316 { "vphsubwd", { XM
, EXxmm
}, 0 },
8317 { "vphsubdq", { XM
, EXxmm
}, 0 },
8371 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8373 { REG_TABLE (REG_XOP_LWP
) },
8643 static const struct dis386 vex_table
[][256] = {
8665 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8666 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8667 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8668 { MOD_TABLE (MOD_VEX_0F13
) },
8669 { VEX_W_TABLE (VEX_W_0F14
) },
8670 { VEX_W_TABLE (VEX_W_0F15
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8672 { MOD_TABLE (MOD_VEX_0F17
) },
8692 { VEX_W_TABLE (VEX_W_0F28
) },
8693 { VEX_W_TABLE (VEX_W_0F29
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8695 { MOD_TABLE (MOD_VEX_0F2B
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8737 { MOD_TABLE (MOD_VEX_0F50
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8741 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8742 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8743 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8744 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8746 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8774 { REG_TABLE (REG_VEX_0F71
) },
8775 { REG_TABLE (REG_VEX_0F72
) },
8776 { REG_TABLE (REG_VEX_0F73
) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8809 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8810 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8812 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8818 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8819 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8842 { REG_TABLE (REG_VEX_0FAE
) },
8865 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8867 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8869 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8881 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8882 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8884 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8895 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8896 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8917 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8924 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8926 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8927 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8928 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8929 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8963 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8979 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8983 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8984 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8985 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8988 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8989 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8990 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8992 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8994 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8995 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
9008 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
9010 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
9103 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
9107 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
9112 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
9113 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
9114 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
9115 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
9116 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
9127 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
9128 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
9129 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
9130 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
9131 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
9142 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
9143 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
9145 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
9146 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
9147 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
9148 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
9149 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
9150 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
9151 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
9152 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
9184 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9185 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9186 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9187 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9188 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9210 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9211 { REG_TABLE (REG_VEX_0F38F3
) },
9213 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9214 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9215 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9229 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9230 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9231 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9233 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9234 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9235 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9238 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9239 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9240 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9241 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9242 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9243 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9244 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9245 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9251 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9252 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9253 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9254 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9256 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9257 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9261 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9265 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9266 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9267 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9283 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9284 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9285 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9286 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9292 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9293 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9301 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9302 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9303 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9305 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9307 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9310 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9311 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9312 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9314 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9332 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9333 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9334 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9335 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9337 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9338 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9339 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9340 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9346 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9347 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9348 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9349 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9350 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9351 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9352 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9353 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9364 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9365 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9366 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9367 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9368 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9369 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9370 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9371 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9479 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9499 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9519 #define NEED_OPCODE_TABLE
9520 #include "i386-dis-evex.h"
9521 #undef NEED_OPCODE_TABLE
9522 static const struct dis386 vex_len_table
[][2] = {
9523 /* VEX_LEN_0F10_P_1 */
9525 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9526 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9529 /* VEX_LEN_0F10_P_3 */
9531 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9532 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9535 /* VEX_LEN_0F11_P_1 */
9537 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9538 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9541 /* VEX_LEN_0F11_P_3 */
9543 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9544 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9547 /* VEX_LEN_0F12_P_0_M_0 */
9549 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9552 /* VEX_LEN_0F12_P_0_M_1 */
9554 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9557 /* VEX_LEN_0F12_P_2 */
9559 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9562 /* VEX_LEN_0F13_M_0 */
9564 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9567 /* VEX_LEN_0F16_P_0_M_0 */
9569 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9572 /* VEX_LEN_0F16_P_0_M_1 */
9574 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9577 /* VEX_LEN_0F16_P_2 */
9579 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9582 /* VEX_LEN_0F17_M_0 */
9584 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9587 /* VEX_LEN_0F2A_P_1 */
9589 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9590 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9593 /* VEX_LEN_0F2A_P_3 */
9595 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9596 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9599 /* VEX_LEN_0F2C_P_1 */
9601 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9602 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9605 /* VEX_LEN_0F2C_P_3 */
9607 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9608 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9611 /* VEX_LEN_0F2D_P_1 */
9613 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9614 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9617 /* VEX_LEN_0F2D_P_3 */
9619 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9620 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9623 /* VEX_LEN_0F2E_P_0 */
9625 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9626 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9629 /* VEX_LEN_0F2E_P_2 */
9631 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9632 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9635 /* VEX_LEN_0F2F_P_0 */
9637 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9638 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9641 /* VEX_LEN_0F2F_P_2 */
9643 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9644 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9647 /* VEX_LEN_0F41_P_0 */
9650 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9652 /* VEX_LEN_0F41_P_2 */
9655 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9657 /* VEX_LEN_0F42_P_0 */
9660 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9662 /* VEX_LEN_0F42_P_2 */
9665 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9667 /* VEX_LEN_0F44_P_0 */
9669 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9671 /* VEX_LEN_0F44_P_2 */
9673 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9675 /* VEX_LEN_0F45_P_0 */
9678 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9680 /* VEX_LEN_0F45_P_2 */
9683 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9685 /* VEX_LEN_0F46_P_0 */
9688 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9690 /* VEX_LEN_0F46_P_2 */
9693 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9695 /* VEX_LEN_0F47_P_0 */
9698 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9700 /* VEX_LEN_0F47_P_2 */
9703 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9705 /* VEX_LEN_0F4A_P_0 */
9708 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9710 /* VEX_LEN_0F4A_P_2 */
9713 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9715 /* VEX_LEN_0F4B_P_0 */
9718 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9720 /* VEX_LEN_0F4B_P_2 */
9723 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9726 /* VEX_LEN_0F51_P_1 */
9728 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9729 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9732 /* VEX_LEN_0F51_P_3 */
9734 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9735 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9738 /* VEX_LEN_0F52_P_1 */
9740 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9741 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9744 /* VEX_LEN_0F53_P_1 */
9746 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9747 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9750 /* VEX_LEN_0F58_P_1 */
9752 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9753 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9756 /* VEX_LEN_0F58_P_3 */
9758 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9759 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9762 /* VEX_LEN_0F59_P_1 */
9764 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9765 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9768 /* VEX_LEN_0F59_P_3 */
9770 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9771 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9774 /* VEX_LEN_0F5A_P_1 */
9776 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9777 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9780 /* VEX_LEN_0F5A_P_3 */
9782 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9783 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9786 /* VEX_LEN_0F5C_P_1 */
9788 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9789 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9792 /* VEX_LEN_0F5C_P_3 */
9794 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9795 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9798 /* VEX_LEN_0F5D_P_1 */
9800 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9801 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9804 /* VEX_LEN_0F5D_P_3 */
9806 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9807 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9810 /* VEX_LEN_0F5E_P_1 */
9812 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9813 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9816 /* VEX_LEN_0F5E_P_3 */
9818 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9819 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9822 /* VEX_LEN_0F5F_P_1 */
9824 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9825 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9828 /* VEX_LEN_0F5F_P_3 */
9830 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9831 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9834 /* VEX_LEN_0F6E_P_2 */
9836 { "vmovK", { XMScalar
, Edq
}, 0 },
9837 { "vmovK", { XMScalar
, Edq
}, 0 },
9840 /* VEX_LEN_0F7E_P_1 */
9842 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9843 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9846 /* VEX_LEN_0F7E_P_2 */
9848 { "vmovK", { Edq
, XMScalar
}, 0 },
9849 { "vmovK", { Edq
, XMScalar
}, 0 },
9852 /* VEX_LEN_0F90_P_0 */
9854 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9857 /* VEX_LEN_0F90_P_2 */
9859 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9862 /* VEX_LEN_0F91_P_0 */
9864 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9867 /* VEX_LEN_0F91_P_2 */
9869 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9872 /* VEX_LEN_0F92_P_0 */
9874 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9877 /* VEX_LEN_0F92_P_2 */
9879 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9882 /* VEX_LEN_0F92_P_3 */
9884 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9887 /* VEX_LEN_0F93_P_0 */
9889 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9892 /* VEX_LEN_0F93_P_2 */
9894 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9897 /* VEX_LEN_0F93_P_3 */
9899 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9902 /* VEX_LEN_0F98_P_0 */
9904 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9907 /* VEX_LEN_0F98_P_2 */
9909 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9912 /* VEX_LEN_0F99_P_0 */
9914 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9917 /* VEX_LEN_0F99_P_2 */
9919 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9922 /* VEX_LEN_0FAE_R_2_M_0 */
9924 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
9927 /* VEX_LEN_0FAE_R_3_M_0 */
9929 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
9932 /* VEX_LEN_0FC2_P_1 */
9934 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9935 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9938 /* VEX_LEN_0FC2_P_3 */
9940 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9941 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9944 /* VEX_LEN_0FC4_P_2 */
9946 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
9949 /* VEX_LEN_0FC5_P_2 */
9951 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
9954 /* VEX_LEN_0FD6_P_2 */
9956 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9957 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9960 /* VEX_LEN_0FF7_P_2 */
9962 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
9965 /* VEX_LEN_0F3816_P_2 */
9968 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9971 /* VEX_LEN_0F3819_P_2 */
9974 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9977 /* VEX_LEN_0F381A_P_2_M_0 */
9980 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9983 /* VEX_LEN_0F3836_P_2 */
9986 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9989 /* VEX_LEN_0F3841_P_2 */
9991 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
9994 /* VEX_LEN_0F385A_P_2_M_0 */
9997 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
10000 /* VEX_LEN_0F38DB_P_2 */
10002 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
10005 /* VEX_LEN_0F38DC_P_2 */
10007 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
10010 /* VEX_LEN_0F38DD_P_2 */
10012 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
10015 /* VEX_LEN_0F38DE_P_2 */
10017 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
10020 /* VEX_LEN_0F38DF_P_2 */
10022 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
10025 /* VEX_LEN_0F38F2_P_0 */
10027 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
10030 /* VEX_LEN_0F38F3_R_1_P_0 */
10032 { "blsrS", { VexGdq
, Edq
}, 0 },
10035 /* VEX_LEN_0F38F3_R_2_P_0 */
10037 { "blsmskS", { VexGdq
, Edq
}, 0 },
10040 /* VEX_LEN_0F38F3_R_3_P_0 */
10042 { "blsiS", { VexGdq
, Edq
}, 0 },
10045 /* VEX_LEN_0F38F5_P_0 */
10047 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
10050 /* VEX_LEN_0F38F5_P_1 */
10052 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
10055 /* VEX_LEN_0F38F5_P_3 */
10057 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
10060 /* VEX_LEN_0F38F6_P_3 */
10062 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
10065 /* VEX_LEN_0F38F7_P_0 */
10067 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
10070 /* VEX_LEN_0F38F7_P_1 */
10072 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
10075 /* VEX_LEN_0F38F7_P_2 */
10077 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
10080 /* VEX_LEN_0F38F7_P_3 */
10082 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
10085 /* VEX_LEN_0F3A00_P_2 */
10088 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
10091 /* VEX_LEN_0F3A01_P_2 */
10094 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
10097 /* VEX_LEN_0F3A06_P_2 */
10100 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
10103 /* VEX_LEN_0F3A0A_P_2 */
10105 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10106 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10109 /* VEX_LEN_0F3A0B_P_2 */
10111 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10112 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10115 /* VEX_LEN_0F3A14_P_2 */
10117 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
10120 /* VEX_LEN_0F3A15_P_2 */
10122 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
10125 /* VEX_LEN_0F3A16_P_2 */
10127 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
10130 /* VEX_LEN_0F3A17_P_2 */
10132 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
10135 /* VEX_LEN_0F3A18_P_2 */
10138 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
10141 /* VEX_LEN_0F3A19_P_2 */
10144 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
10147 /* VEX_LEN_0F3A20_P_2 */
10149 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
10152 /* VEX_LEN_0F3A21_P_2 */
10154 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
10157 /* VEX_LEN_0F3A22_P_2 */
10159 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
10162 /* VEX_LEN_0F3A30_P_2 */
10164 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
10167 /* VEX_LEN_0F3A31_P_2 */
10169 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
10172 /* VEX_LEN_0F3A32_P_2 */
10174 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
10177 /* VEX_LEN_0F3A33_P_2 */
10179 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
10182 /* VEX_LEN_0F3A38_P_2 */
10185 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
10188 /* VEX_LEN_0F3A39_P_2 */
10191 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
10194 /* VEX_LEN_0F3A41_P_2 */
10196 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
10199 /* VEX_LEN_0F3A44_P_2 */
10201 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
10204 /* VEX_LEN_0F3A46_P_2 */
10207 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
10210 /* VEX_LEN_0F3A60_P_2 */
10212 { VEX_W_TABLE (VEX_W_0F3A60_P_2
) },
10215 /* VEX_LEN_0F3A61_P_2 */
10217 { VEX_W_TABLE (VEX_W_0F3A61_P_2
) },
10220 /* VEX_LEN_0F3A62_P_2 */
10222 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
10225 /* VEX_LEN_0F3A63_P_2 */
10227 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
10230 /* VEX_LEN_0F3A6A_P_2 */
10232 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10235 /* VEX_LEN_0F3A6B_P_2 */
10237 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10240 /* VEX_LEN_0F3A6E_P_2 */
10242 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10245 /* VEX_LEN_0F3A6F_P_2 */
10247 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10250 /* VEX_LEN_0F3A7A_P_2 */
10252 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10255 /* VEX_LEN_0F3A7B_P_2 */
10257 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10260 /* VEX_LEN_0F3A7E_P_2 */
10262 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10265 /* VEX_LEN_0F3A7F_P_2 */
10267 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10270 /* VEX_LEN_0F3ADF_P_2 */
10272 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
10275 /* VEX_LEN_0F3AF0_P_3 */
10277 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
10280 /* VEX_LEN_0FXOP_08_CC */
10282 { "vpcomb", { XM
, Vex128
, EXx
, Ib
}, 0 },
10285 /* VEX_LEN_0FXOP_08_CD */
10287 { "vpcomw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10290 /* VEX_LEN_0FXOP_08_CE */
10292 { "vpcomd", { XM
, Vex128
, EXx
, Ib
}, 0 },
10295 /* VEX_LEN_0FXOP_08_CF */
10297 { "vpcomq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10300 /* VEX_LEN_0FXOP_08_EC */
10302 { "vpcomub", { XM
, Vex128
, EXx
, Ib
}, 0 },
10305 /* VEX_LEN_0FXOP_08_ED */
10307 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10310 /* VEX_LEN_0FXOP_08_EE */
10312 { "vpcomud", { XM
, Vex128
, EXx
, Ib
}, 0 },
10315 /* VEX_LEN_0FXOP_08_EF */
10317 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10320 /* VEX_LEN_0FXOP_09_80 */
10322 { "vfrczps", { XM
, EXxmm
}, 0 },
10323 { "vfrczps", { XM
, EXymmq
}, 0 },
10326 /* VEX_LEN_0FXOP_09_81 */
10328 { "vfrczpd", { XM
, EXxmm
}, 0 },
10329 { "vfrczpd", { XM
, EXymmq
}, 0 },
10333 static const struct dis386 vex_w_table
[][2] = {
10335 /* VEX_W_0F10_P_0 */
10336 { "vmovups", { XM
, EXx
}, 0 },
10339 /* VEX_W_0F10_P_1 */
10340 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
10343 /* VEX_W_0F10_P_2 */
10344 { "vmovupd", { XM
, EXx
}, 0 },
10347 /* VEX_W_0F10_P_3 */
10348 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
10351 /* VEX_W_0F11_P_0 */
10352 { "vmovups", { EXxS
, XM
}, 0 },
10355 /* VEX_W_0F11_P_1 */
10356 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
10359 /* VEX_W_0F11_P_2 */
10360 { "vmovupd", { EXxS
, XM
}, 0 },
10363 /* VEX_W_0F11_P_3 */
10364 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
10367 /* VEX_W_0F12_P_0_M_0 */
10368 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
10371 /* VEX_W_0F12_P_0_M_1 */
10372 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
10375 /* VEX_W_0F12_P_1 */
10376 { "vmovsldup", { XM
, EXx
}, 0 },
10379 /* VEX_W_0F12_P_2 */
10380 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
10383 /* VEX_W_0F12_P_3 */
10384 { "vmovddup", { XM
, EXymmq
}, 0 },
10387 /* VEX_W_0F13_M_0 */
10388 { "vmovlpX", { EXq
, XM
}, 0 },
10392 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
10396 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
10399 /* VEX_W_0F16_P_0_M_0 */
10400 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
10403 /* VEX_W_0F16_P_0_M_1 */
10404 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
10407 /* VEX_W_0F16_P_1 */
10408 { "vmovshdup", { XM
, EXx
}, 0 },
10411 /* VEX_W_0F16_P_2 */
10412 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
10415 /* VEX_W_0F17_M_0 */
10416 { "vmovhpX", { EXq
, XM
}, 0 },
10420 { "vmovapX", { XM
, EXx
}, 0 },
10424 { "vmovapX", { EXxS
, XM
}, 0 },
10427 /* VEX_W_0F2B_M_0 */
10428 { "vmovntpX", { Mx
, XM
}, 0 },
10431 /* VEX_W_0F2E_P_0 */
10432 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
10435 /* VEX_W_0F2E_P_2 */
10436 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
10439 /* VEX_W_0F2F_P_0 */
10440 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
10443 /* VEX_W_0F2F_P_2 */
10444 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
10447 /* VEX_W_0F41_P_0_LEN_1 */
10448 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10449 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10452 /* VEX_W_0F41_P_2_LEN_1 */
10453 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10454 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10457 /* VEX_W_0F42_P_0_LEN_1 */
10458 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10459 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10462 /* VEX_W_0F42_P_2_LEN_1 */
10463 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10464 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10467 /* VEX_W_0F44_P_0_LEN_0 */
10468 { "knotw", { MaskG
, MaskR
}, 0 },
10469 { "knotq", { MaskG
, MaskR
}, 0 },
10472 /* VEX_W_0F44_P_2_LEN_0 */
10473 { "knotb", { MaskG
, MaskR
}, 0 },
10474 { "knotd", { MaskG
, MaskR
}, 0 },
10477 /* VEX_W_0F45_P_0_LEN_1 */
10478 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10479 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10482 /* VEX_W_0F45_P_2_LEN_1 */
10483 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10484 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10487 /* VEX_W_0F46_P_0_LEN_1 */
10488 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10489 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10492 /* VEX_W_0F46_P_2_LEN_1 */
10493 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10494 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10497 /* VEX_W_0F47_P_0_LEN_1 */
10498 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10499 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10502 /* VEX_W_0F47_P_2_LEN_1 */
10503 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10504 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10507 /* VEX_W_0F4A_P_0_LEN_1 */
10508 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10509 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10512 /* VEX_W_0F4A_P_2_LEN_1 */
10513 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10514 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10517 /* VEX_W_0F4B_P_0_LEN_1 */
10518 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10519 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10522 /* VEX_W_0F4B_P_2_LEN_1 */
10523 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10526 /* VEX_W_0F50_M_0 */
10527 { "vmovmskpX", { Gdq
, XS
}, 0 },
10530 /* VEX_W_0F51_P_0 */
10531 { "vsqrtps", { XM
, EXx
}, 0 },
10534 /* VEX_W_0F51_P_1 */
10535 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10538 /* VEX_W_0F51_P_2 */
10539 { "vsqrtpd", { XM
, EXx
}, 0 },
10542 /* VEX_W_0F51_P_3 */
10543 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10546 /* VEX_W_0F52_P_0 */
10547 { "vrsqrtps", { XM
, EXx
}, 0 },
10550 /* VEX_W_0F52_P_1 */
10551 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10554 /* VEX_W_0F53_P_0 */
10555 { "vrcpps", { XM
, EXx
}, 0 },
10558 /* VEX_W_0F53_P_1 */
10559 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10562 /* VEX_W_0F58_P_0 */
10563 { "vaddps", { XM
, Vex
, EXx
}, 0 },
10566 /* VEX_W_0F58_P_1 */
10567 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10570 /* VEX_W_0F58_P_2 */
10571 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
10574 /* VEX_W_0F58_P_3 */
10575 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10578 /* VEX_W_0F59_P_0 */
10579 { "vmulps", { XM
, Vex
, EXx
}, 0 },
10582 /* VEX_W_0F59_P_1 */
10583 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10586 /* VEX_W_0F59_P_2 */
10587 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
10590 /* VEX_W_0F59_P_3 */
10591 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10594 /* VEX_W_0F5A_P_0 */
10595 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
10598 /* VEX_W_0F5A_P_1 */
10599 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10602 /* VEX_W_0F5A_P_3 */
10603 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10606 /* VEX_W_0F5B_P_0 */
10607 { "vcvtdq2ps", { XM
, EXx
}, 0 },
10610 /* VEX_W_0F5B_P_1 */
10611 { "vcvttps2dq", { XM
, EXx
}, 0 },
10614 /* VEX_W_0F5B_P_2 */
10615 { "vcvtps2dq", { XM
, EXx
}, 0 },
10618 /* VEX_W_0F5C_P_0 */
10619 { "vsubps", { XM
, Vex
, EXx
}, 0 },
10622 /* VEX_W_0F5C_P_1 */
10623 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10626 /* VEX_W_0F5C_P_2 */
10627 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
10630 /* VEX_W_0F5C_P_3 */
10631 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10634 /* VEX_W_0F5D_P_0 */
10635 { "vminps", { XM
, Vex
, EXx
}, 0 },
10638 /* VEX_W_0F5D_P_1 */
10639 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10642 /* VEX_W_0F5D_P_2 */
10643 { "vminpd", { XM
, Vex
, EXx
}, 0 },
10646 /* VEX_W_0F5D_P_3 */
10647 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10650 /* VEX_W_0F5E_P_0 */
10651 { "vdivps", { XM
, Vex
, EXx
}, 0 },
10654 /* VEX_W_0F5E_P_1 */
10655 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10658 /* VEX_W_0F5E_P_2 */
10659 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
10662 /* VEX_W_0F5E_P_3 */
10663 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10666 /* VEX_W_0F5F_P_0 */
10667 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
10670 /* VEX_W_0F5F_P_1 */
10671 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10674 /* VEX_W_0F5F_P_2 */
10675 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
10678 /* VEX_W_0F5F_P_3 */
10679 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10682 /* VEX_W_0F60_P_2 */
10683 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
10686 /* VEX_W_0F61_P_2 */
10687 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
10690 /* VEX_W_0F62_P_2 */
10691 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
10694 /* VEX_W_0F63_P_2 */
10695 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
10698 /* VEX_W_0F64_P_2 */
10699 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
10702 /* VEX_W_0F65_P_2 */
10703 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
10706 /* VEX_W_0F66_P_2 */
10707 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
10710 /* VEX_W_0F67_P_2 */
10711 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
10714 /* VEX_W_0F68_P_2 */
10715 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
10718 /* VEX_W_0F69_P_2 */
10719 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
10722 /* VEX_W_0F6A_P_2 */
10723 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
10726 /* VEX_W_0F6B_P_2 */
10727 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
10730 /* VEX_W_0F6C_P_2 */
10731 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
10734 /* VEX_W_0F6D_P_2 */
10735 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
10738 /* VEX_W_0F6F_P_1 */
10739 { "vmovdqu", { XM
, EXx
}, 0 },
10742 /* VEX_W_0F6F_P_2 */
10743 { "vmovdqa", { XM
, EXx
}, 0 },
10746 /* VEX_W_0F70_P_1 */
10747 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
10750 /* VEX_W_0F70_P_2 */
10751 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
10754 /* VEX_W_0F70_P_3 */
10755 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
10758 /* VEX_W_0F71_R_2_P_2 */
10759 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
10762 /* VEX_W_0F71_R_4_P_2 */
10763 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
10766 /* VEX_W_0F71_R_6_P_2 */
10767 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
10770 /* VEX_W_0F72_R_2_P_2 */
10771 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
10774 /* VEX_W_0F72_R_4_P_2 */
10775 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
10778 /* VEX_W_0F72_R_6_P_2 */
10779 { "vpslld", { Vex
, XS
, Ib
}, 0 },
10782 /* VEX_W_0F73_R_2_P_2 */
10783 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
10786 /* VEX_W_0F73_R_3_P_2 */
10787 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
10790 /* VEX_W_0F73_R_6_P_2 */
10791 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
10794 /* VEX_W_0F73_R_7_P_2 */
10795 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
10798 /* VEX_W_0F74_P_2 */
10799 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
10802 /* VEX_W_0F75_P_2 */
10803 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
10806 /* VEX_W_0F76_P_2 */
10807 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
10810 /* VEX_W_0F77_P_0 */
10811 { "", { VZERO
}, 0 },
10814 /* VEX_W_0F7C_P_2 */
10815 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
10818 /* VEX_W_0F7C_P_3 */
10819 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
10822 /* VEX_W_0F7D_P_2 */
10823 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
10826 /* VEX_W_0F7D_P_3 */
10827 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
10830 /* VEX_W_0F7E_P_1 */
10831 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
10834 /* VEX_W_0F7F_P_1 */
10835 { "vmovdqu", { EXxS
, XM
}, 0 },
10838 /* VEX_W_0F7F_P_2 */
10839 { "vmovdqa", { EXxS
, XM
}, 0 },
10842 /* VEX_W_0F90_P_0_LEN_0 */
10843 { "kmovw", { MaskG
, MaskE
}, 0 },
10844 { "kmovq", { MaskG
, MaskE
}, 0 },
10847 /* VEX_W_0F90_P_2_LEN_0 */
10848 { "kmovb", { MaskG
, MaskBDE
}, 0 },
10849 { "kmovd", { MaskG
, MaskBDE
}, 0 },
10852 /* VEX_W_0F91_P_0_LEN_0 */
10853 { "kmovw", { Ew
, MaskG
}, 0 },
10854 { "kmovq", { Eq
, MaskG
}, 0 },
10857 /* VEX_W_0F91_P_2_LEN_0 */
10858 { "kmovb", { Eb
, MaskG
}, 0 },
10859 { "kmovd", { Ed
, MaskG
}, 0 },
10862 /* VEX_W_0F92_P_0_LEN_0 */
10863 { "kmovw", { MaskG
, Rdq
}, 0 },
10866 /* VEX_W_0F92_P_2_LEN_0 */
10867 { "kmovb", { MaskG
, Rdq
}, 0 },
10870 /* VEX_W_0F92_P_3_LEN_0 */
10871 { "kmovd", { MaskG
, Rdq
}, 0 },
10872 { "kmovq", { MaskG
, Rdq
}, 0 },
10875 /* VEX_W_0F93_P_0_LEN_0 */
10876 { "kmovw", { Gdq
, MaskR
}, 0 },
10879 /* VEX_W_0F93_P_2_LEN_0 */
10880 { "kmovb", { Gdq
, MaskR
}, 0 },
10883 /* VEX_W_0F93_P_3_LEN_0 */
10884 { "kmovd", { Gdq
, MaskR
}, 0 },
10885 { "kmovq", { Gdq
, MaskR
}, 0 },
10888 /* VEX_W_0F98_P_0_LEN_0 */
10889 { "kortestw", { MaskG
, MaskR
}, 0 },
10890 { "kortestq", { MaskG
, MaskR
}, 0 },
10893 /* VEX_W_0F98_P_2_LEN_0 */
10894 { "kortestb", { MaskG
, MaskR
}, 0 },
10895 { "kortestd", { MaskG
, MaskR
}, 0 },
10898 /* VEX_W_0F99_P_0_LEN_0 */
10899 { "ktestw", { MaskG
, MaskR
}, 0 },
10900 { "ktestq", { MaskG
, MaskR
}, 0 },
10903 /* VEX_W_0F99_P_2_LEN_0 */
10904 { "ktestb", { MaskG
, MaskR
}, 0 },
10905 { "ktestd", { MaskG
, MaskR
}, 0 },
10908 /* VEX_W_0FAE_R_2_M_0 */
10909 { "vldmxcsr", { Md
}, 0 },
10912 /* VEX_W_0FAE_R_3_M_0 */
10913 { "vstmxcsr", { Md
}, 0 },
10916 /* VEX_W_0FC2_P_0 */
10917 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
10920 /* VEX_W_0FC2_P_1 */
10921 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
10924 /* VEX_W_0FC2_P_2 */
10925 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
10928 /* VEX_W_0FC2_P_3 */
10929 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
10932 /* VEX_W_0FC4_P_2 */
10933 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
10936 /* VEX_W_0FC5_P_2 */
10937 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
10940 /* VEX_W_0FD0_P_2 */
10941 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
10944 /* VEX_W_0FD0_P_3 */
10945 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
10948 /* VEX_W_0FD1_P_2 */
10949 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
10952 /* VEX_W_0FD2_P_2 */
10953 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
10956 /* VEX_W_0FD3_P_2 */
10957 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
10960 /* VEX_W_0FD4_P_2 */
10961 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
10964 /* VEX_W_0FD5_P_2 */
10965 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
10968 /* VEX_W_0FD6_P_2 */
10969 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
10972 /* VEX_W_0FD7_P_2_M_1 */
10973 { "vpmovmskb", { Gdq
, XS
}, 0 },
10976 /* VEX_W_0FD8_P_2 */
10977 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
10980 /* VEX_W_0FD9_P_2 */
10981 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
10984 /* VEX_W_0FDA_P_2 */
10985 { "vpminub", { XM
, Vex
, EXx
}, 0 },
10988 /* VEX_W_0FDB_P_2 */
10989 { "vpand", { XM
, Vex
, EXx
}, 0 },
10992 /* VEX_W_0FDC_P_2 */
10993 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
10996 /* VEX_W_0FDD_P_2 */
10997 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
11000 /* VEX_W_0FDE_P_2 */
11001 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
11004 /* VEX_W_0FDF_P_2 */
11005 { "vpandn", { XM
, Vex
, EXx
}, 0 },
11008 /* VEX_W_0FE0_P_2 */
11009 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
11012 /* VEX_W_0FE1_P_2 */
11013 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
11016 /* VEX_W_0FE2_P_2 */
11017 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
11020 /* VEX_W_0FE3_P_2 */
11021 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
11024 /* VEX_W_0FE4_P_2 */
11025 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
11028 /* VEX_W_0FE5_P_2 */
11029 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
11032 /* VEX_W_0FE6_P_1 */
11033 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
11036 /* VEX_W_0FE6_P_2 */
11037 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
11040 /* VEX_W_0FE6_P_3 */
11041 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
11044 /* VEX_W_0FE7_P_2_M_0 */
11045 { "vmovntdq", { Mx
, XM
}, 0 },
11048 /* VEX_W_0FE8_P_2 */
11049 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
11052 /* VEX_W_0FE9_P_2 */
11053 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
11056 /* VEX_W_0FEA_P_2 */
11057 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
11060 /* VEX_W_0FEB_P_2 */
11061 { "vpor", { XM
, Vex
, EXx
}, 0 },
11064 /* VEX_W_0FEC_P_2 */
11065 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
11068 /* VEX_W_0FED_P_2 */
11069 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
11072 /* VEX_W_0FEE_P_2 */
11073 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
11076 /* VEX_W_0FEF_P_2 */
11077 { "vpxor", { XM
, Vex
, EXx
}, 0 },
11080 /* VEX_W_0FF0_P_3_M_0 */
11081 { "vlddqu", { XM
, M
}, 0 },
11084 /* VEX_W_0FF1_P_2 */
11085 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
11088 /* VEX_W_0FF2_P_2 */
11089 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
11092 /* VEX_W_0FF3_P_2 */
11093 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
11096 /* VEX_W_0FF4_P_2 */
11097 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
11100 /* VEX_W_0FF5_P_2 */
11101 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
11104 /* VEX_W_0FF6_P_2 */
11105 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
11108 /* VEX_W_0FF7_P_2 */
11109 { "vmaskmovdqu", { XM
, XS
}, 0 },
11112 /* VEX_W_0FF8_P_2 */
11113 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
11116 /* VEX_W_0FF9_P_2 */
11117 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
11120 /* VEX_W_0FFA_P_2 */
11121 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
11124 /* VEX_W_0FFB_P_2 */
11125 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
11128 /* VEX_W_0FFC_P_2 */
11129 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
11132 /* VEX_W_0FFD_P_2 */
11133 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
11136 /* VEX_W_0FFE_P_2 */
11137 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
11140 /* VEX_W_0F3800_P_2 */
11141 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
11144 /* VEX_W_0F3801_P_2 */
11145 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
11148 /* VEX_W_0F3802_P_2 */
11149 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
11152 /* VEX_W_0F3803_P_2 */
11153 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
11156 /* VEX_W_0F3804_P_2 */
11157 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
11160 /* VEX_W_0F3805_P_2 */
11161 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
11164 /* VEX_W_0F3806_P_2 */
11165 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
11168 /* VEX_W_0F3807_P_2 */
11169 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
11172 /* VEX_W_0F3808_P_2 */
11173 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
11176 /* VEX_W_0F3809_P_2 */
11177 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
11180 /* VEX_W_0F380A_P_2 */
11181 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
11184 /* VEX_W_0F380B_P_2 */
11185 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
11188 /* VEX_W_0F380C_P_2 */
11189 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
11192 /* VEX_W_0F380D_P_2 */
11193 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
11196 /* VEX_W_0F380E_P_2 */
11197 { "vtestps", { XM
, EXx
}, 0 },
11200 /* VEX_W_0F380F_P_2 */
11201 { "vtestpd", { XM
, EXx
}, 0 },
11204 /* VEX_W_0F3816_P_2 */
11205 { "vpermps", { XM
, Vex
, EXx
}, 0 },
11208 /* VEX_W_0F3817_P_2 */
11209 { "vptest", { XM
, EXx
}, 0 },
11212 /* VEX_W_0F3818_P_2 */
11213 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
11216 /* VEX_W_0F3819_P_2 */
11217 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
11220 /* VEX_W_0F381A_P_2_M_0 */
11221 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
11224 /* VEX_W_0F381C_P_2 */
11225 { "vpabsb", { XM
, EXx
}, 0 },
11228 /* VEX_W_0F381D_P_2 */
11229 { "vpabsw", { XM
, EXx
}, 0 },
11232 /* VEX_W_0F381E_P_2 */
11233 { "vpabsd", { XM
, EXx
}, 0 },
11236 /* VEX_W_0F3820_P_2 */
11237 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
11240 /* VEX_W_0F3821_P_2 */
11241 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
11244 /* VEX_W_0F3822_P_2 */
11245 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
11248 /* VEX_W_0F3823_P_2 */
11249 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
11252 /* VEX_W_0F3824_P_2 */
11253 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
11256 /* VEX_W_0F3825_P_2 */
11257 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
11260 /* VEX_W_0F3828_P_2 */
11261 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
11264 /* VEX_W_0F3829_P_2 */
11265 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
11268 /* VEX_W_0F382A_P_2_M_0 */
11269 { "vmovntdqa", { XM
, Mx
}, 0 },
11272 /* VEX_W_0F382B_P_2 */
11273 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
11276 /* VEX_W_0F382C_P_2_M_0 */
11277 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
11280 /* VEX_W_0F382D_P_2_M_0 */
11281 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
11284 /* VEX_W_0F382E_P_2_M_0 */
11285 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
11288 /* VEX_W_0F382F_P_2_M_0 */
11289 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
11292 /* VEX_W_0F3830_P_2 */
11293 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
11296 /* VEX_W_0F3831_P_2 */
11297 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
11300 /* VEX_W_0F3832_P_2 */
11301 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
11304 /* VEX_W_0F3833_P_2 */
11305 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
11308 /* VEX_W_0F3834_P_2 */
11309 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
11312 /* VEX_W_0F3835_P_2 */
11313 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
11316 /* VEX_W_0F3836_P_2 */
11317 { "vpermd", { XM
, Vex
, EXx
}, 0 },
11320 /* VEX_W_0F3837_P_2 */
11321 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
11324 /* VEX_W_0F3838_P_2 */
11325 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
11328 /* VEX_W_0F3839_P_2 */
11329 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
11332 /* VEX_W_0F383A_P_2 */
11333 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
11336 /* VEX_W_0F383B_P_2 */
11337 { "vpminud", { XM
, Vex
, EXx
}, 0 },
11340 /* VEX_W_0F383C_P_2 */
11341 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
11344 /* VEX_W_0F383D_P_2 */
11345 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
11348 /* VEX_W_0F383E_P_2 */
11349 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
11352 /* VEX_W_0F383F_P_2 */
11353 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
11356 /* VEX_W_0F3840_P_2 */
11357 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
11360 /* VEX_W_0F3841_P_2 */
11361 { "vphminposuw", { XM
, EXx
}, 0 },
11364 /* VEX_W_0F3846_P_2 */
11365 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
11368 /* VEX_W_0F3858_P_2 */
11369 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
11372 /* VEX_W_0F3859_P_2 */
11373 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
11376 /* VEX_W_0F385A_P_2_M_0 */
11377 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
11380 /* VEX_W_0F3878_P_2 */
11381 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
11384 /* VEX_W_0F3879_P_2 */
11385 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
11388 /* VEX_W_0F38DB_P_2 */
11389 { "vaesimc", { XM
, EXx
}, 0 },
11392 /* VEX_W_0F38DC_P_2 */
11393 { "vaesenc", { XM
, Vex128
, EXx
}, 0 },
11396 /* VEX_W_0F38DD_P_2 */
11397 { "vaesenclast", { XM
, Vex128
, EXx
}, 0 },
11400 /* VEX_W_0F38DE_P_2 */
11401 { "vaesdec", { XM
, Vex128
, EXx
}, 0 },
11404 /* VEX_W_0F38DF_P_2 */
11405 { "vaesdeclast", { XM
, Vex128
, EXx
}, 0 },
11408 /* VEX_W_0F3A00_P_2 */
11410 { "vpermq", { XM
, EXx
, Ib
}, 0 },
11413 /* VEX_W_0F3A01_P_2 */
11415 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
11418 /* VEX_W_0F3A02_P_2 */
11419 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
11422 /* VEX_W_0F3A04_P_2 */
11423 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
11426 /* VEX_W_0F3A05_P_2 */
11427 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
11430 /* VEX_W_0F3A06_P_2 */
11431 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11434 /* VEX_W_0F3A08_P_2 */
11435 { "vroundps", { XM
, EXx
, Ib
}, 0 },
11438 /* VEX_W_0F3A09_P_2 */
11439 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
11442 /* VEX_W_0F3A0A_P_2 */
11443 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
11446 /* VEX_W_0F3A0B_P_2 */
11447 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
11450 /* VEX_W_0F3A0C_P_2 */
11451 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
11454 /* VEX_W_0F3A0D_P_2 */
11455 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
11458 /* VEX_W_0F3A0E_P_2 */
11459 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
11462 /* VEX_W_0F3A0F_P_2 */
11463 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
11466 /* VEX_W_0F3A14_P_2 */
11467 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
11470 /* VEX_W_0F3A15_P_2 */
11471 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
11474 /* VEX_W_0F3A18_P_2 */
11475 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11478 /* VEX_W_0F3A19_P_2 */
11479 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
11482 /* VEX_W_0F3A20_P_2 */
11483 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
11486 /* VEX_W_0F3A21_P_2 */
11487 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
11490 /* VEX_W_0F3A30_P_2_LEN_0 */
11491 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
11492 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
11495 /* VEX_W_0F3A31_P_2_LEN_0 */
11496 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
11497 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
11500 /* VEX_W_0F3A32_P_2_LEN_0 */
11501 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
11502 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
11505 /* VEX_W_0F3A33_P_2_LEN_0 */
11506 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
11507 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
11510 /* VEX_W_0F3A38_P_2 */
11511 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11514 /* VEX_W_0F3A39_P_2 */
11515 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
11518 /* VEX_W_0F3A40_P_2 */
11519 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
11522 /* VEX_W_0F3A41_P_2 */
11523 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
11526 /* VEX_W_0F3A42_P_2 */
11527 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
11530 /* VEX_W_0F3A44_P_2 */
11531 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
}, 0 },
11534 /* VEX_W_0F3A46_P_2 */
11535 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11538 /* VEX_W_0F3A48_P_2 */
11539 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11540 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11543 /* VEX_W_0F3A49_P_2 */
11544 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11545 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11548 /* VEX_W_0F3A4A_P_2 */
11549 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11552 /* VEX_W_0F3A4B_P_2 */
11553 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11556 /* VEX_W_0F3A4C_P_2 */
11557 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11560 /* VEX_W_0F3A60_P_2 */
11561 { "vpcmpestrm", { XM
, EXx
, Ib
}, 0 },
11564 /* VEX_W_0F3A61_P_2 */
11565 { "vpcmpestri", { XM
, EXx
, Ib
}, 0 },
11568 /* VEX_W_0F3A62_P_2 */
11569 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
11572 /* VEX_W_0F3A63_P_2 */
11573 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
11576 /* VEX_W_0F3ADF_P_2 */
11577 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
11579 #define NEED_VEX_W_TABLE
11580 #include "i386-dis-evex.h"
11581 #undef NEED_VEX_W_TABLE
11584 static const struct dis386 mod_table
[][2] = {
11587 { "leaS", { Gv
, M
}, 0 },
11592 { RM_TABLE (RM_C6_REG_7
) },
11597 { RM_TABLE (RM_C7_REG_7
) },
11601 { "Jcall^", { indirEp
}, 0 },
11605 { "Jjmp^", { indirEp
}, 0 },
11608 /* MOD_0F01_REG_0 */
11609 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11610 { RM_TABLE (RM_0F01_REG_0
) },
11613 /* MOD_0F01_REG_1 */
11614 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11615 { RM_TABLE (RM_0F01_REG_1
) },
11618 /* MOD_0F01_REG_2 */
11619 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11620 { RM_TABLE (RM_0F01_REG_2
) },
11623 /* MOD_0F01_REG_3 */
11624 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11625 { RM_TABLE (RM_0F01_REG_3
) },
11628 /* MOD_0F01_REG_7 */
11629 { "invlpg", { Mb
}, 0 },
11630 { RM_TABLE (RM_0F01_REG_7
) },
11633 /* MOD_0F12_PREFIX_0 */
11634 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
11635 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
11639 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
11642 /* MOD_0F16_PREFIX_0 */
11643 { "movhps", { XM
, EXq
}, 0 },
11644 { "movlhps", { XM
, EXq
}, 0 },
11648 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
11651 /* MOD_0F18_REG_0 */
11652 { "prefetchnta", { Mb
}, 0 },
11655 /* MOD_0F18_REG_1 */
11656 { "prefetcht0", { Mb
}, 0 },
11659 /* MOD_0F18_REG_2 */
11660 { "prefetcht1", { Mb
}, 0 },
11663 /* MOD_0F18_REG_3 */
11664 { "prefetcht2", { Mb
}, 0 },
11667 /* MOD_0F18_REG_4 */
11668 { "nop/reserved", { Mb
}, 0 },
11671 /* MOD_0F18_REG_5 */
11672 { "nop/reserved", { Mb
}, 0 },
11675 /* MOD_0F18_REG_6 */
11676 { "nop/reserved", { Mb
}, 0 },
11679 /* MOD_0F18_REG_7 */
11680 { "nop/reserved", { Mb
}, 0 },
11683 /* MOD_0F1A_PREFIX_0 */
11684 { "bndldx", { Gbnd
, Ev_bnd
}, 0 },
11685 { "nopQ", { Ev
}, 0 },
11688 /* MOD_0F1B_PREFIX_0 */
11689 { "bndstx", { Ev_bnd
, Gbnd
}, 0 },
11690 { "nopQ", { Ev
}, 0 },
11693 /* MOD_0F1B_PREFIX_1 */
11694 { "bndmk", { Gbnd
, Ev_bnd
}, 0 },
11695 { "nopQ", { Ev
}, 0 },
11700 { "movL", { Rd
, Td
}, 0 },
11705 { "movL", { Td
, Rd
}, 0 },
11708 /* MOD_0F2B_PREFIX_0 */
11709 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
11712 /* MOD_0F2B_PREFIX_1 */
11713 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
11716 /* MOD_0F2B_PREFIX_2 */
11717 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
11720 /* MOD_0F2B_PREFIX_3 */
11721 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
11726 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
11729 /* MOD_0F71_REG_2 */
11731 { "psrlw", { MS
, Ib
}, 0 },
11734 /* MOD_0F71_REG_4 */
11736 { "psraw", { MS
, Ib
}, 0 },
11739 /* MOD_0F71_REG_6 */
11741 { "psllw", { MS
, Ib
}, 0 },
11744 /* MOD_0F72_REG_2 */
11746 { "psrld", { MS
, Ib
}, 0 },
11749 /* MOD_0F72_REG_4 */
11751 { "psrad", { MS
, Ib
}, 0 },
11754 /* MOD_0F72_REG_6 */
11756 { "pslld", { MS
, Ib
}, 0 },
11759 /* MOD_0F73_REG_2 */
11761 { "psrlq", { MS
, Ib
}, 0 },
11764 /* MOD_0F73_REG_3 */
11766 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11769 /* MOD_0F73_REG_6 */
11771 { "psllq", { MS
, Ib
}, 0 },
11774 /* MOD_0F73_REG_7 */
11776 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11779 /* MOD_0FAE_REG_0 */
11780 { "fxsave", { FXSAVE
}, 0 },
11781 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11784 /* MOD_0FAE_REG_1 */
11785 { "fxrstor", { FXSAVE
}, 0 },
11786 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11789 /* MOD_0FAE_REG_2 */
11790 { "ldmxcsr", { Md
}, 0 },
11791 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11794 /* MOD_0FAE_REG_3 */
11795 { "stmxcsr", { Md
}, 0 },
11796 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11799 /* MOD_0FAE_REG_4 */
11800 { "xsave", { FXSAVE
}, 0 },
11803 /* MOD_0FAE_REG_5 */
11804 { "xrstor", { FXSAVE
}, 0 },
11805 { RM_TABLE (RM_0FAE_REG_5
) },
11808 /* MOD_0FAE_REG_6 */
11809 { PREFIX_TABLE (PREFIX_0FAE_REG_6
) },
11810 { RM_TABLE (RM_0FAE_REG_6
) },
11813 /* MOD_0FAE_REG_7 */
11814 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11815 { RM_TABLE (RM_0FAE_REG_7
) },
11819 { "lssS", { Gv
, Mp
}, 0 },
11823 { "lfsS", { Gv
, Mp
}, 0 },
11827 { "lgsS", { Gv
, Mp
}, 0 },
11830 /* MOD_0FC7_REG_3 */
11831 { "xrstors", { FXSAVE
}, 0 },
11834 /* MOD_0FC7_REG_4 */
11835 { "xsavec", { FXSAVE
}, 0 },
11838 /* MOD_0FC7_REG_5 */
11839 { "xsaves", { FXSAVE
}, 0 },
11842 /* MOD_0FC7_REG_6 */
11843 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
11844 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
11847 /* MOD_0FC7_REG_7 */
11848 { "vmptrst", { Mq
}, 0 },
11849 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
11854 { "pmovmskb", { Gdq
, MS
}, 0 },
11857 /* MOD_0FE7_PREFIX_2 */
11858 { "movntdq", { Mx
, XM
}, 0 },
11861 /* MOD_0FF0_PREFIX_3 */
11862 { "lddqu", { XM
, M
}, 0 },
11865 /* MOD_0F382A_PREFIX_2 */
11866 { "movntdqa", { XM
, Mx
}, 0 },
11870 { "bound{S|}", { Gv
, Ma
}, 0 },
11871 { EVEX_TABLE (EVEX_0F
) },
11875 { "lesS", { Gv
, Mp
}, 0 },
11876 { VEX_C4_TABLE (VEX_0F
) },
11880 { "ldsS", { Gv
, Mp
}, 0 },
11881 { VEX_C5_TABLE (VEX_0F
) },
11884 /* MOD_VEX_0F12_PREFIX_0 */
11885 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11886 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11890 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11893 /* MOD_VEX_0F16_PREFIX_0 */
11894 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11895 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11899 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11903 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11908 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
11911 /* MOD_VEX_0F71_REG_2 */
11913 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
11916 /* MOD_VEX_0F71_REG_4 */
11918 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
11921 /* MOD_VEX_0F71_REG_6 */
11923 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
11926 /* MOD_VEX_0F72_REG_2 */
11928 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
11931 /* MOD_VEX_0F72_REG_4 */
11933 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
11936 /* MOD_VEX_0F72_REG_6 */
11938 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
11941 /* MOD_VEX_0F73_REG_2 */
11943 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
11946 /* MOD_VEX_0F73_REG_3 */
11948 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
11951 /* MOD_VEX_0F73_REG_6 */
11953 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
11956 /* MOD_VEX_0F73_REG_7 */
11958 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
11961 /* MOD_VEX_0FAE_REG_2 */
11962 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
11965 /* MOD_VEX_0FAE_REG_3 */
11966 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
11969 /* MOD_VEX_0FD7_PREFIX_2 */
11971 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
11974 /* MOD_VEX_0FE7_PREFIX_2 */
11975 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
11978 /* MOD_VEX_0FF0_PREFIX_3 */
11979 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
11982 /* MOD_VEX_0F381A_PREFIX_2 */
11983 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
11986 /* MOD_VEX_0F382A_PREFIX_2 */
11987 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
11990 /* MOD_VEX_0F382C_PREFIX_2 */
11991 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
11994 /* MOD_VEX_0F382D_PREFIX_2 */
11995 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
11998 /* MOD_VEX_0F382E_PREFIX_2 */
11999 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
12002 /* MOD_VEX_0F382F_PREFIX_2 */
12003 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
12006 /* MOD_VEX_0F385A_PREFIX_2 */
12007 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
12010 /* MOD_VEX_0F388C_PREFIX_2 */
12011 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
12014 /* MOD_VEX_0F388E_PREFIX_2 */
12015 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
12017 #define NEED_MOD_TABLE
12018 #include "i386-dis-evex.h"
12019 #undef NEED_MOD_TABLE
12022 static const struct dis386 rm_table
[][8] = {
12025 { "xabort", { Skip_MODRM
, Ib
}, 0 },
12029 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
12032 /* RM_0F01_REG_0 */
12034 { "vmcall", { Skip_MODRM
}, 0 },
12035 { "vmlaunch", { Skip_MODRM
}, 0 },
12036 { "vmresume", { Skip_MODRM
}, 0 },
12037 { "vmxoff", { Skip_MODRM
}, 0 },
12040 /* RM_0F01_REG_1 */
12041 { "monitor", { { OP_Monitor
, 0 } }, 0 },
12042 { "mwait", { { OP_Mwait
, 0 } }, 0 },
12043 { "clac", { Skip_MODRM
}, 0 },
12044 { "stac", { Skip_MODRM
}, 0 },
12048 { "encls", { Skip_MODRM
}, 0 },
12051 /* RM_0F01_REG_2 */
12052 { "xgetbv", { Skip_MODRM
}, 0 },
12053 { "xsetbv", { Skip_MODRM
}, 0 },
12056 { "vmfunc", { Skip_MODRM
}, 0 },
12057 { "xend", { Skip_MODRM
}, 0 },
12058 { "xtest", { Skip_MODRM
}, 0 },
12059 { "enclu", { Skip_MODRM
}, 0 },
12062 /* RM_0F01_REG_3 */
12063 { "vmrun", { Skip_MODRM
}, 0 },
12064 { "vmmcall", { Skip_MODRM
}, 0 },
12065 { "vmload", { Skip_MODRM
}, 0 },
12066 { "vmsave", { Skip_MODRM
}, 0 },
12067 { "stgi", { Skip_MODRM
}, 0 },
12068 { "clgi", { Skip_MODRM
}, 0 },
12069 { "skinit", { Skip_MODRM
}, 0 },
12070 { "invlpga", { Skip_MODRM
}, 0 },
12073 /* RM_0F01_REG_7 */
12074 { "swapgs", { Skip_MODRM
}, 0 },
12075 { "rdtscp", { Skip_MODRM
}, 0 },
12076 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
12077 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
12078 { "clzero", { Skip_MODRM
}, 0 },
12081 /* RM_0FAE_REG_5 */
12082 { "lfence", { Skip_MODRM
}, 0 },
12085 /* RM_0FAE_REG_6 */
12086 { "mfence", { Skip_MODRM
}, 0 },
12089 /* RM_0FAE_REG_7 */
12090 { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7
) },
12094 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12096 /* We use the high bit to indicate different name for the same
12098 #define REP_PREFIX (0xf3 | 0x100)
12099 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12100 #define XRELEASE_PREFIX (0xf3 | 0x400)
12101 #define BND_PREFIX (0xf2 | 0x400)
12106 int newrex
, i
, length
;
12112 last_lock_prefix
= -1;
12113 last_repz_prefix
= -1;
12114 last_repnz_prefix
= -1;
12115 last_data_prefix
= -1;
12116 last_addr_prefix
= -1;
12117 last_rex_prefix
= -1;
12118 last_seg_prefix
= -1;
12120 active_seg_prefix
= 0;
12121 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12122 all_prefixes
[i
] = 0;
12125 /* The maximum instruction length is 15bytes. */
12126 while (length
< MAX_CODE_LENGTH
- 1)
12128 FETCH_DATA (the_info
, codep
+ 1);
12132 /* REX prefixes family. */
12149 if (address_mode
== mode_64bit
)
12153 last_rex_prefix
= i
;
12156 prefixes
|= PREFIX_REPZ
;
12157 last_repz_prefix
= i
;
12160 prefixes
|= PREFIX_REPNZ
;
12161 last_repnz_prefix
= i
;
12164 prefixes
|= PREFIX_LOCK
;
12165 last_lock_prefix
= i
;
12168 prefixes
|= PREFIX_CS
;
12169 last_seg_prefix
= i
;
12170 active_seg_prefix
= PREFIX_CS
;
12173 prefixes
|= PREFIX_SS
;
12174 last_seg_prefix
= i
;
12175 active_seg_prefix
= PREFIX_SS
;
12178 prefixes
|= PREFIX_DS
;
12179 last_seg_prefix
= i
;
12180 active_seg_prefix
= PREFIX_DS
;
12183 prefixes
|= PREFIX_ES
;
12184 last_seg_prefix
= i
;
12185 active_seg_prefix
= PREFIX_ES
;
12188 prefixes
|= PREFIX_FS
;
12189 last_seg_prefix
= i
;
12190 active_seg_prefix
= PREFIX_FS
;
12193 prefixes
|= PREFIX_GS
;
12194 last_seg_prefix
= i
;
12195 active_seg_prefix
= PREFIX_GS
;
12198 prefixes
|= PREFIX_DATA
;
12199 last_data_prefix
= i
;
12202 prefixes
|= PREFIX_ADDR
;
12203 last_addr_prefix
= i
;
12206 /* fwait is really an instruction. If there are prefixes
12207 before the fwait, they belong to the fwait, *not* to the
12208 following instruction. */
12210 if (prefixes
|| rex
)
12212 prefixes
|= PREFIX_FWAIT
;
12214 /* This ensures that the previous REX prefixes are noticed
12215 as unused prefixes, as in the return case below. */
12219 prefixes
= PREFIX_FWAIT
;
12224 /* Rex is ignored when followed by another prefix. */
12230 if (*codep
!= FWAIT_OPCODE
)
12231 all_prefixes
[i
++] = *codep
;
12239 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12242 static const char *
12243 prefix_name (int pref
, int sizeflag
)
12245 static const char *rexes
[16] =
12248 "rex.B", /* 0x41 */
12249 "rex.X", /* 0x42 */
12250 "rex.XB", /* 0x43 */
12251 "rex.R", /* 0x44 */
12252 "rex.RB", /* 0x45 */
12253 "rex.RX", /* 0x46 */
12254 "rex.RXB", /* 0x47 */
12255 "rex.W", /* 0x48 */
12256 "rex.WB", /* 0x49 */
12257 "rex.WX", /* 0x4a */
12258 "rex.WXB", /* 0x4b */
12259 "rex.WR", /* 0x4c */
12260 "rex.WRB", /* 0x4d */
12261 "rex.WRX", /* 0x4e */
12262 "rex.WRXB", /* 0x4f */
12267 /* REX prefixes family. */
12284 return rexes
[pref
- 0x40];
12304 return (sizeflag
& DFLAG
) ? "data16" : "data32";
12306 if (address_mode
== mode_64bit
)
12307 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
12309 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
12314 case XACQUIRE_PREFIX
:
12316 case XRELEASE_PREFIX
:
12325 static char op_out
[MAX_OPERANDS
][100];
12326 static int op_ad
, op_index
[MAX_OPERANDS
];
12327 static int two_source_ops
;
12328 static bfd_vma op_address
[MAX_OPERANDS
];
12329 static bfd_vma op_riprel
[MAX_OPERANDS
];
12330 static bfd_vma start_pc
;
12333 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12334 * (see topic "Redundant prefixes" in the "Differences from 8086"
12335 * section of the "Virtual 8086 Mode" chapter.)
12336 * 'pc' should be the address of this instruction, it will
12337 * be used to print the target address if this is a relative jump or call
12338 * The function returns the length of this instruction in bytes.
12341 static char intel_syntax
;
12342 static char intel_mnemonic
= !SYSV386_COMPAT
;
12343 static char open_char
;
12344 static char close_char
;
12345 static char separator_char
;
12346 static char scale_char
;
12354 static enum x86_64_isa isa64
;
12356 /* Here for backwards compatibility. When gdb stops using
12357 print_insn_i386_att and print_insn_i386_intel these functions can
12358 disappear, and print_insn_i386 be merged into print_insn. */
12360 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
12364 return print_insn (pc
, info
);
12368 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
12372 return print_insn (pc
, info
);
12376 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
12380 return print_insn (pc
, info
);
12384 print_i386_disassembler_options (FILE *stream
)
12386 fprintf (stream
, _("\n\
12387 The following i386/x86-64 specific disassembler options are supported for use\n\
12388 with the -M switch (multiple options should be separated by commas):\n"));
12390 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
12391 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
12392 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
12393 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
12394 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
12395 fprintf (stream
, _(" att-mnemonic\n"
12396 " Display instruction in AT&T mnemonic\n"));
12397 fprintf (stream
, _(" intel-mnemonic\n"
12398 " Display instruction in Intel mnemonic\n"));
12399 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
12400 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
12401 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
12402 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
12403 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
12404 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12405 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
12406 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
12410 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
12412 /* Get a pointer to struct dis386 with a valid name. */
12414 static const struct dis386
*
12415 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
12417 int vindex
, vex_table_index
;
12419 if (dp
->name
!= NULL
)
12422 switch (dp
->op
[0].bytemode
)
12424 case USE_REG_TABLE
:
12425 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
12428 case USE_MOD_TABLE
:
12429 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
12430 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
12434 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
12437 case USE_PREFIX_TABLE
:
12440 /* The prefix in VEX is implicit. */
12441 switch (vex
.prefix
)
12446 case REPE_PREFIX_OPCODE
:
12449 case DATA_PREFIX_OPCODE
:
12452 case REPNE_PREFIX_OPCODE
:
12462 int last_prefix
= -1;
12465 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12466 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12468 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12470 if (last_repz_prefix
> last_repnz_prefix
)
12473 prefix
= PREFIX_REPZ
;
12474 last_prefix
= last_repz_prefix
;
12479 prefix
= PREFIX_REPNZ
;
12480 last_prefix
= last_repnz_prefix
;
12483 /* Check if prefix should be ignored. */
12484 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
12485 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
12490 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12493 prefix
= PREFIX_DATA
;
12494 last_prefix
= last_data_prefix
;
12499 used_prefixes
|= prefix
;
12500 all_prefixes
[last_prefix
] = 0;
12503 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12506 case USE_X86_64_TABLE
:
12507 vindex
= address_mode
== mode_64bit
? 1 : 0;
12508 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12511 case USE_3BYTE_TABLE
:
12512 FETCH_DATA (info
, codep
+ 2);
12514 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12516 modrm
.mod
= (*codep
>> 6) & 3;
12517 modrm
.reg
= (*codep
>> 3) & 7;
12518 modrm
.rm
= *codep
& 7;
12521 case USE_VEX_LEN_TABLE
:
12525 switch (vex
.length
)
12538 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12541 case USE_XOP_8F_TABLE
:
12542 FETCH_DATA (info
, codep
+ 3);
12543 /* All bits in the REX prefix are ignored. */
12545 rex
= ~(*codep
>> 5) & 0x7;
12547 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12548 switch ((*codep
& 0x1f))
12554 vex_table_index
= XOP_08
;
12557 vex_table_index
= XOP_09
;
12560 vex_table_index
= XOP_0A
;
12564 vex
.w
= *codep
& 0x80;
12565 if (vex
.w
&& address_mode
== mode_64bit
)
12568 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12569 if (address_mode
!= mode_64bit
12570 && vex
.register_specifier
> 0x7)
12576 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12577 switch ((*codep
& 0x3))
12583 vex
.prefix
= DATA_PREFIX_OPCODE
;
12586 vex
.prefix
= REPE_PREFIX_OPCODE
;
12589 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12596 dp
= &xop_table
[vex_table_index
][vindex
];
12599 FETCH_DATA (info
, codep
+ 1);
12600 modrm
.mod
= (*codep
>> 6) & 3;
12601 modrm
.reg
= (*codep
>> 3) & 7;
12602 modrm
.rm
= *codep
& 7;
12605 case USE_VEX_C4_TABLE
:
12607 FETCH_DATA (info
, codep
+ 3);
12608 /* All bits in the REX prefix are ignored. */
12610 rex
= ~(*codep
>> 5) & 0x7;
12611 switch ((*codep
& 0x1f))
12617 vex_table_index
= VEX_0F
;
12620 vex_table_index
= VEX_0F38
;
12623 vex_table_index
= VEX_0F3A
;
12627 vex
.w
= *codep
& 0x80;
12628 if (vex
.w
&& address_mode
== mode_64bit
)
12631 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12632 if (address_mode
!= mode_64bit
12633 && vex
.register_specifier
> 0x7)
12639 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12640 switch ((*codep
& 0x3))
12646 vex
.prefix
= DATA_PREFIX_OPCODE
;
12649 vex
.prefix
= REPE_PREFIX_OPCODE
;
12652 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12659 dp
= &vex_table
[vex_table_index
][vindex
];
12661 /* There is no MODRM byte for VEX [82|77]. */
12662 if (vindex
!= 0x77 && vindex
!= 0x82)
12664 FETCH_DATA (info
, codep
+ 1);
12665 modrm
.mod
= (*codep
>> 6) & 3;
12666 modrm
.reg
= (*codep
>> 3) & 7;
12667 modrm
.rm
= *codep
& 7;
12671 case USE_VEX_C5_TABLE
:
12673 FETCH_DATA (info
, codep
+ 2);
12674 /* All bits in the REX prefix are ignored. */
12676 rex
= (*codep
& 0x80) ? 0 : REX_R
;
12678 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12679 if (address_mode
!= mode_64bit
12680 && vex
.register_specifier
> 0x7)
12688 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12689 switch ((*codep
& 0x3))
12695 vex
.prefix
= DATA_PREFIX_OPCODE
;
12698 vex
.prefix
= REPE_PREFIX_OPCODE
;
12701 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12708 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
12710 /* There is no MODRM byte for VEX [82|77]. */
12711 if (vindex
!= 0x77 && vindex
!= 0x82)
12713 FETCH_DATA (info
, codep
+ 1);
12714 modrm
.mod
= (*codep
>> 6) & 3;
12715 modrm
.reg
= (*codep
>> 3) & 7;
12716 modrm
.rm
= *codep
& 7;
12720 case USE_VEX_W_TABLE
:
12724 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
12727 case USE_EVEX_TABLE
:
12728 two_source_ops
= 0;
12731 FETCH_DATA (info
, codep
+ 4);
12732 /* All bits in the REX prefix are ignored. */
12734 /* The first byte after 0x62. */
12735 rex
= ~(*codep
>> 5) & 0x7;
12736 vex
.r
= *codep
& 0x10;
12737 switch ((*codep
& 0xf))
12740 return &bad_opcode
;
12742 vex_table_index
= EVEX_0F
;
12745 vex_table_index
= EVEX_0F38
;
12748 vex_table_index
= EVEX_0F3A
;
12752 /* The second byte after 0x62. */
12754 vex
.w
= *codep
& 0x80;
12755 if (vex
.w
&& address_mode
== mode_64bit
)
12758 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12759 if (address_mode
!= mode_64bit
)
12761 /* In 16/32-bit mode silently ignore following bits. */
12765 vex
.register_specifier
&= 0x7;
12769 if (!(*codep
& 0x4))
12770 return &bad_opcode
;
12772 switch ((*codep
& 0x3))
12778 vex
.prefix
= DATA_PREFIX_OPCODE
;
12781 vex
.prefix
= REPE_PREFIX_OPCODE
;
12784 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12788 /* The third byte after 0x62. */
12791 /* Remember the static rounding bits. */
12792 vex
.ll
= (*codep
>> 5) & 3;
12793 vex
.b
= (*codep
& 0x10) != 0;
12795 vex
.v
= *codep
& 0x8;
12796 vex
.mask_register_specifier
= *codep
& 0x7;
12797 vex
.zeroing
= *codep
& 0x80;
12803 dp
= &evex_table
[vex_table_index
][vindex
];
12805 FETCH_DATA (info
, codep
+ 1);
12806 modrm
.mod
= (*codep
>> 6) & 3;
12807 modrm
.reg
= (*codep
>> 3) & 7;
12808 modrm
.rm
= *codep
& 7;
12810 /* Set vector length. */
12811 if (modrm
.mod
== 3 && vex
.b
)
12827 return &bad_opcode
;
12840 if (dp
->name
!= NULL
)
12843 return get_valid_dis386 (dp
, info
);
12847 get_sib (disassemble_info
*info
, int sizeflag
)
12849 /* If modrm.mod == 3, operand must be register. */
12851 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12855 FETCH_DATA (info
, codep
+ 2);
12856 sib
.index
= (codep
[1] >> 3) & 7;
12857 sib
.scale
= (codep
[1] >> 6) & 3;
12858 sib
.base
= codep
[1] & 7;
12863 print_insn (bfd_vma pc
, disassemble_info
*info
)
12865 const struct dis386
*dp
;
12867 char *op_txt
[MAX_OPERANDS
];
12869 int sizeflag
, orig_sizeflag
;
12871 struct dis_private priv
;
12874 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12875 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
12876 address_mode
= mode_32bit
;
12877 else if (info
->mach
== bfd_mach_i386_i8086
)
12879 address_mode
= mode_16bit
;
12880 priv
.orig_sizeflag
= 0;
12883 address_mode
= mode_64bit
;
12885 if (intel_syntax
== (char) -1)
12886 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
12888 for (p
= info
->disassembler_options
; p
!= NULL
; )
12890 if (CONST_STRNEQ (p
, "amd64"))
12892 else if (CONST_STRNEQ (p
, "intel64"))
12894 else if (CONST_STRNEQ (p
, "x86-64"))
12896 address_mode
= mode_64bit
;
12897 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12899 else if (CONST_STRNEQ (p
, "i386"))
12901 address_mode
= mode_32bit
;
12902 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12904 else if (CONST_STRNEQ (p
, "i8086"))
12906 address_mode
= mode_16bit
;
12907 priv
.orig_sizeflag
= 0;
12909 else if (CONST_STRNEQ (p
, "intel"))
12912 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
12913 intel_mnemonic
= 1;
12915 else if (CONST_STRNEQ (p
, "att"))
12918 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
12919 intel_mnemonic
= 0;
12921 else if (CONST_STRNEQ (p
, "addr"))
12923 if (address_mode
== mode_64bit
)
12925 if (p
[4] == '3' && p
[5] == '2')
12926 priv
.orig_sizeflag
&= ~AFLAG
;
12927 else if (p
[4] == '6' && p
[5] == '4')
12928 priv
.orig_sizeflag
|= AFLAG
;
12932 if (p
[4] == '1' && p
[5] == '6')
12933 priv
.orig_sizeflag
&= ~AFLAG
;
12934 else if (p
[4] == '3' && p
[5] == '2')
12935 priv
.orig_sizeflag
|= AFLAG
;
12938 else if (CONST_STRNEQ (p
, "data"))
12940 if (p
[4] == '1' && p
[5] == '6')
12941 priv
.orig_sizeflag
&= ~DFLAG
;
12942 else if (p
[4] == '3' && p
[5] == '2')
12943 priv
.orig_sizeflag
|= DFLAG
;
12945 else if (CONST_STRNEQ (p
, "suffix"))
12946 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
12948 p
= strchr (p
, ',');
12955 names64
= intel_names64
;
12956 names32
= intel_names32
;
12957 names16
= intel_names16
;
12958 names8
= intel_names8
;
12959 names8rex
= intel_names8rex
;
12960 names_seg
= intel_names_seg
;
12961 names_mm
= intel_names_mm
;
12962 names_bnd
= intel_names_bnd
;
12963 names_xmm
= intel_names_xmm
;
12964 names_ymm
= intel_names_ymm
;
12965 names_zmm
= intel_names_zmm
;
12966 index64
= intel_index64
;
12967 index32
= intel_index32
;
12968 names_mask
= intel_names_mask
;
12969 index16
= intel_index16
;
12972 separator_char
= '+';
12977 names64
= att_names64
;
12978 names32
= att_names32
;
12979 names16
= att_names16
;
12980 names8
= att_names8
;
12981 names8rex
= att_names8rex
;
12982 names_seg
= att_names_seg
;
12983 names_mm
= att_names_mm
;
12984 names_bnd
= att_names_bnd
;
12985 names_xmm
= att_names_xmm
;
12986 names_ymm
= att_names_ymm
;
12987 names_zmm
= att_names_zmm
;
12988 index64
= att_index64
;
12989 index32
= att_index32
;
12990 names_mask
= att_names_mask
;
12991 index16
= att_index16
;
12994 separator_char
= ',';
12998 /* The output looks better if we put 7 bytes on a line, since that
12999 puts most long word instructions on a single line. Use 8 bytes
13001 if ((info
->mach
& bfd_mach_l1om
) != 0)
13002 info
->bytes_per_line
= 8;
13004 info
->bytes_per_line
= 7;
13006 info
->private_data
= &priv
;
13007 priv
.max_fetched
= priv
.the_buffer
;
13008 priv
.insn_start
= pc
;
13011 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13019 start_codep
= priv
.the_buffer
;
13020 codep
= priv
.the_buffer
;
13022 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
13026 /* Getting here means we tried for data but didn't get it. That
13027 means we have an incomplete instruction of some sort. Just
13028 print the first byte as a prefix or a .byte pseudo-op. */
13029 if (codep
> priv
.the_buffer
)
13031 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
13033 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
13036 /* Just print the first byte as a .byte instruction. */
13037 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
13038 (unsigned int) priv
.the_buffer
[0]);
13048 sizeflag
= priv
.orig_sizeflag
;
13050 if (!ckprefix () || rex_used
)
13052 /* Too many prefixes or unused REX prefixes. */
13054 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
13056 (*info
->fprintf_func
) (info
->stream
, "%s%s",
13058 prefix_name (all_prefixes
[i
], sizeflag
));
13062 insn_codep
= codep
;
13064 FETCH_DATA (info
, codep
+ 1);
13065 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
13067 if (((prefixes
& PREFIX_FWAIT
)
13068 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
13070 /* Handle prefixes before fwait. */
13071 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
13073 (*info
->fprintf_func
) (info
->stream
, "%s ",
13074 prefix_name (all_prefixes
[i
], sizeflag
));
13075 (*info
->fprintf_func
) (info
->stream
, "fwait");
13079 if (*codep
== 0x0f)
13081 unsigned char threebyte
;
13082 FETCH_DATA (info
, codep
+ 2);
13083 threebyte
= *++codep
;
13084 dp
= &dis386_twobyte
[threebyte
];
13085 need_modrm
= twobyte_has_modrm
[*codep
];
13090 dp
= &dis386
[*codep
];
13091 need_modrm
= onebyte_has_modrm
[*codep
];
13095 /* Save sizeflag for printing the extra prefixes later before updating
13096 it for mnemonic and operand processing. The prefix names depend
13097 only on the address mode. */
13098 orig_sizeflag
= sizeflag
;
13099 if (prefixes
& PREFIX_ADDR
)
13101 if ((prefixes
& PREFIX_DATA
))
13107 FETCH_DATA (info
, codep
+ 1);
13108 modrm
.mod
= (*codep
>> 6) & 3;
13109 modrm
.reg
= (*codep
>> 3) & 7;
13110 modrm
.rm
= *codep
& 7;
13118 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
13120 get_sib (info
, sizeflag
);
13121 dofloat (sizeflag
);
13125 dp
= get_valid_dis386 (dp
, info
);
13126 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
13128 get_sib (info
, sizeflag
);
13129 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13132 op_ad
= MAX_OPERANDS
- 1 - i
;
13134 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
13135 /* For EVEX instruction after the last operand masking
13136 should be printed. */
13137 if (i
== 0 && vex
.evex
)
13139 /* Don't print {%k0}. */
13140 if (vex
.mask_register_specifier
)
13143 oappend (names_mask
[vex
.mask_register_specifier
]);
13153 /* Check if the REX prefix is used. */
13154 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
13155 all_prefixes
[last_rex_prefix
] = 0;
13157 /* Check if the SEG prefix is used. */
13158 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
13159 | PREFIX_FS
| PREFIX_GS
)) != 0
13160 && (used_prefixes
& active_seg_prefix
) != 0)
13161 all_prefixes
[last_seg_prefix
] = 0;
13163 /* Check if the ADDR prefix is used. */
13164 if ((prefixes
& PREFIX_ADDR
) != 0
13165 && (used_prefixes
& PREFIX_ADDR
) != 0)
13166 all_prefixes
[last_addr_prefix
] = 0;
13168 /* Check if the DATA prefix is used. */
13169 if ((prefixes
& PREFIX_DATA
) != 0
13170 && (used_prefixes
& PREFIX_DATA
) != 0)
13171 all_prefixes
[last_data_prefix
] = 0;
13173 /* Print the extra prefixes. */
13175 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
13176 if (all_prefixes
[i
])
13179 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
13182 prefix_length
+= strlen (name
) + 1;
13183 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
13186 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13187 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13188 used by putop and MMX/SSE operand and may be overriden by the
13189 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13191 if (dp
->prefix_requirement
== PREFIX_OPCODE
13192 && dp
!= &bad_opcode
13194 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
13196 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
13198 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
13200 && (used_prefixes
& PREFIX_DATA
) == 0))))
13202 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13203 return end_codep
- priv
.the_buffer
;
13206 /* Check maximum code length. */
13207 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
13209 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13210 return MAX_CODE_LENGTH
;
13213 obufp
= mnemonicendp
;
13214 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
13217 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
13219 /* The enter and bound instructions are printed with operands in the same
13220 order as the intel book; everything else is printed in reverse order. */
13221 if (intel_syntax
|| two_source_ops
)
13225 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13226 op_txt
[i
] = op_out
[i
];
13228 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
13229 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
13231 op_txt
[2] = op_out
[3];
13232 op_txt
[3] = op_out
[2];
13235 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
13237 op_ad
= op_index
[i
];
13238 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
13239 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
13240 riprel
= op_riprel
[i
];
13241 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
13242 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
13247 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13248 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
13252 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13256 (*info
->fprintf_func
) (info
->stream
, ",");
13257 if (op_index
[i
] != -1 && !op_riprel
[i
])
13258 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
13260 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
13264 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13265 if (op_index
[i
] != -1 && op_riprel
[i
])
13267 (*info
->fprintf_func
) (info
->stream
, " # ");
13268 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ codep
- start_codep
13269 + op_address
[op_index
[i
]]), info
);
13272 return codep
- priv
.the_buffer
;
13275 static const char *float_mem
[] = {
13350 static const unsigned char float_mem_mode
[] = {
13425 #define ST { OP_ST, 0 }
13426 #define STi { OP_STi, 0 }
13428 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13429 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13430 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13431 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13432 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13433 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13434 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13435 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13436 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13438 static const struct dis386 float_reg
[][8] = {
13441 { "fadd", { ST
, STi
}, 0 },
13442 { "fmul", { ST
, STi
}, 0 },
13443 { "fcom", { STi
}, 0 },
13444 { "fcomp", { STi
}, 0 },
13445 { "fsub", { ST
, STi
}, 0 },
13446 { "fsubr", { ST
, STi
}, 0 },
13447 { "fdiv", { ST
, STi
}, 0 },
13448 { "fdivr", { ST
, STi
}, 0 },
13452 { "fld", { STi
}, 0 },
13453 { "fxch", { STi
}, 0 },
13463 { "fcmovb", { ST
, STi
}, 0 },
13464 { "fcmove", { ST
, STi
}, 0 },
13465 { "fcmovbe",{ ST
, STi
}, 0 },
13466 { "fcmovu", { ST
, STi
}, 0 },
13474 { "fcmovnb",{ ST
, STi
}, 0 },
13475 { "fcmovne",{ ST
, STi
}, 0 },
13476 { "fcmovnbe",{ ST
, STi
}, 0 },
13477 { "fcmovnu",{ ST
, STi
}, 0 },
13479 { "fucomi", { ST
, STi
}, 0 },
13480 { "fcomi", { ST
, STi
}, 0 },
13485 { "fadd", { STi
, ST
}, 0 },
13486 { "fmul", { STi
, ST
}, 0 },
13489 { "fsub!M", { STi
, ST
}, 0 },
13490 { "fsubM", { STi
, ST
}, 0 },
13491 { "fdiv!M", { STi
, ST
}, 0 },
13492 { "fdivM", { STi
, ST
}, 0 },
13496 { "ffree", { STi
}, 0 },
13498 { "fst", { STi
}, 0 },
13499 { "fstp", { STi
}, 0 },
13500 { "fucom", { STi
}, 0 },
13501 { "fucomp", { STi
}, 0 },
13507 { "faddp", { STi
, ST
}, 0 },
13508 { "fmulp", { STi
, ST
}, 0 },
13511 { "fsub!Mp", { STi
, ST
}, 0 },
13512 { "fsubMp", { STi
, ST
}, 0 },
13513 { "fdiv!Mp", { STi
, ST
}, 0 },
13514 { "fdivMp", { STi
, ST
}, 0 },
13518 { "ffreep", { STi
}, 0 },
13523 { "fucomip", { ST
, STi
}, 0 },
13524 { "fcomip", { ST
, STi
}, 0 },
13529 static char *fgrps
[][8] = {
13532 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13537 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13542 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13547 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13552 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13557 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13562 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13563 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13568 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13573 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13578 swap_operand (void)
13580 mnemonicendp
[0] = '.';
13581 mnemonicendp
[1] = 's';
13586 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13587 int sizeflag ATTRIBUTE_UNUSED
)
13589 /* Skip mod/rm byte. */
13595 dofloat (int sizeflag
)
13597 const struct dis386
*dp
;
13598 unsigned char floatop
;
13600 floatop
= codep
[-1];
13602 if (modrm
.mod
!= 3)
13604 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13606 putop (float_mem
[fp_indx
], sizeflag
);
13609 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13612 /* Skip mod/rm byte. */
13616 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13617 if (dp
->name
== NULL
)
13619 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13621 /* Instruction fnstsw is only one with strange arg. */
13622 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13623 strcpy (op_out
[0], names16
[0]);
13627 putop (dp
->name
, sizeflag
);
13632 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13637 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
13641 /* Like oappend (below), but S is a string starting with '%'.
13642 In Intel syntax, the '%' is elided. */
13644 oappend_maybe_intel (const char *s
)
13646 oappend (s
+ intel_syntax
);
13650 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13652 oappend_maybe_intel ("%st");
13656 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13658 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
13659 oappend_maybe_intel (scratchbuf
);
13662 /* Capital letters in template are macros. */
13664 putop (const char *in_template
, int sizeflag
)
13669 unsigned int l
= 0, len
= 1;
13672 #define SAVE_LAST(c) \
13673 if (l < len && l < sizeof (last)) \
13678 for (p
= in_template
; *p
; p
++)
13695 while (*++p
!= '|')
13696 if (*p
== '}' || *p
== '\0')
13699 /* Fall through. */
13704 while (*++p
!= '}')
13715 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13719 if (l
== 0 && len
== 1)
13724 if (sizeflag
& SUFFIX_ALWAYS
)
13737 if (address_mode
== mode_64bit
13738 && !(prefixes
& PREFIX_ADDR
))
13749 if (intel_syntax
&& !alt
)
13751 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13753 if (sizeflag
& DFLAG
)
13754 *obufp
++ = intel_syntax
? 'd' : 'l';
13756 *obufp
++ = intel_syntax
? 'w' : 's';
13757 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13761 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
13764 if (modrm
.mod
== 3)
13770 if (sizeflag
& DFLAG
)
13771 *obufp
++ = intel_syntax
? 'd' : 'l';
13774 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13780 case 'E': /* For jcxz/jecxz */
13781 if (address_mode
== mode_64bit
)
13783 if (sizeflag
& AFLAG
)
13789 if (sizeflag
& AFLAG
)
13791 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13796 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
13798 if (sizeflag
& AFLAG
)
13799 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
13801 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
13802 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13806 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
13808 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13812 if (!(rex
& REX_W
))
13813 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13818 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
13819 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
13821 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
13824 if (prefixes
& PREFIX_DS
)
13843 if (l
!= 0 || len
!= 1)
13845 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13850 if (!need_vex
|| !vex
.evex
)
13853 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13855 switch (vex
.length
)
13873 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
13878 /* Fall through. */
13881 if (l
!= 0 || len
!= 1)
13889 if (sizeflag
& SUFFIX_ALWAYS
)
13893 if (intel_mnemonic
!= cond
)
13897 if ((prefixes
& PREFIX_FWAIT
) == 0)
13900 used_prefixes
|= PREFIX_FWAIT
;
13906 else if (intel_syntax
&& (sizeflag
& DFLAG
))
13910 if (!(rex
& REX_W
))
13911 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13915 && address_mode
== mode_64bit
13916 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13921 /* Fall through. */
13924 if (l
== 0 && len
== 1)
13929 if ((rex
& REX_W
) == 0
13930 && (prefixes
& PREFIX_DATA
))
13932 if ((sizeflag
& DFLAG
) == 0)
13934 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13938 if ((prefixes
& PREFIX_DATA
)
13940 || (sizeflag
& SUFFIX_ALWAYS
))
13947 if (sizeflag
& DFLAG
)
13951 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13957 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13963 if ((prefixes
& PREFIX_DATA
)
13965 || (sizeflag
& SUFFIX_ALWAYS
))
13972 if (sizeflag
& DFLAG
)
13973 *obufp
++ = intel_syntax
? 'd' : 'l';
13976 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13984 if (address_mode
== mode_64bit
13985 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13987 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13991 /* Fall through. */
13994 if (l
== 0 && len
== 1)
13997 if (intel_syntax
&& !alt
)
14000 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14006 if (sizeflag
& DFLAG
)
14007 *obufp
++ = intel_syntax
? 'd' : 'l';
14010 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14016 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14022 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
14037 else if (sizeflag
& DFLAG
)
14046 if (intel_syntax
&& !p
[1]
14047 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
14049 if (!(rex
& REX_W
))
14050 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14053 if (l
== 0 && len
== 1)
14057 if (address_mode
== mode_64bit
14058 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14060 if (sizeflag
& SUFFIX_ALWAYS
)
14082 /* Fall through. */
14085 if (l
== 0 && len
== 1)
14090 if (sizeflag
& SUFFIX_ALWAYS
)
14096 if (sizeflag
& DFLAG
)
14100 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14114 if (address_mode
== mode_64bit
14115 && !(prefixes
& PREFIX_ADDR
))
14126 if (l
!= 0 || len
!= 1)
14131 if (need_vex
&& vex
.prefix
)
14133 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
14140 if (prefixes
& PREFIX_DATA
)
14144 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14148 if (l
== 0 && len
== 1)
14150 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14161 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14169 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14171 switch (vex
.length
)
14187 if (l
== 0 && len
== 1)
14189 /* operand size flag for cwtl, cbtw */
14198 else if (sizeflag
& DFLAG
)
14202 if (!(rex
& REX_W
))
14203 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14210 && last
[0] != 'L'))
14217 if (last
[0] == 'X')
14218 *obufp
++ = vex
.w
? 'd': 's';
14220 *obufp
++ = vex
.w
? 'q': 'd';
14226 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14228 if (sizeflag
& DFLAG
)
14232 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14238 if (address_mode
== mode_64bit
14239 && (isa64
== intel64
14240 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
14242 else if ((prefixes
& PREFIX_DATA
))
14244 if (!(sizeflag
& DFLAG
))
14246 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14253 mnemonicendp
= obufp
;
14258 oappend (const char *s
)
14260 obufp
= stpcpy (obufp
, s
);
14266 /* Only print the active segment register. */
14267 if (!active_seg_prefix
)
14270 used_prefixes
|= active_seg_prefix
;
14271 switch (active_seg_prefix
)
14274 oappend_maybe_intel ("%cs:");
14277 oappend_maybe_intel ("%ds:");
14280 oappend_maybe_intel ("%ss:");
14283 oappend_maybe_intel ("%es:");
14286 oappend_maybe_intel ("%fs:");
14289 oappend_maybe_intel ("%gs:");
14297 OP_indirE (int bytemode
, int sizeflag
)
14301 OP_E (bytemode
, sizeflag
);
14305 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
14307 if (address_mode
== mode_64bit
)
14315 sprintf_vma (tmp
, disp
);
14316 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
14317 strcpy (buf
+ 2, tmp
+ i
);
14321 bfd_signed_vma v
= disp
;
14328 /* Check for possible overflow on 0x8000000000000000. */
14331 strcpy (buf
, "9223372036854775808");
14345 tmp
[28 - i
] = (v
% 10) + '0';
14349 strcpy (buf
, tmp
+ 29 - i
);
14355 sprintf (buf
, "0x%x", (unsigned int) disp
);
14357 sprintf (buf
, "%d", (int) disp
);
14361 /* Put DISP in BUF as signed hex number. */
14364 print_displacement (char *buf
, bfd_vma disp
)
14366 bfd_signed_vma val
= disp
;
14375 /* Check for possible overflow. */
14378 switch (address_mode
)
14381 strcpy (buf
+ j
, "0x8000000000000000");
14384 strcpy (buf
+ j
, "0x80000000");
14387 strcpy (buf
+ j
, "0x8000");
14397 sprintf_vma (tmp
, (bfd_vma
) val
);
14398 for (i
= 0; tmp
[i
] == '0'; i
++)
14400 if (tmp
[i
] == '\0')
14402 strcpy (buf
+ j
, tmp
+ i
);
14406 intel_operand_size (int bytemode
, int sizeflag
)
14410 && (bytemode
== x_mode
14411 || bytemode
== evex_half_bcst_xmmq_mode
))
14414 oappend ("QWORD PTR ");
14416 oappend ("DWORD PTR ");
14425 oappend ("BYTE PTR ");
14430 case dqw_swap_mode
:
14431 oappend ("WORD PTR ");
14434 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14436 oappend ("QWORD PTR ");
14445 oappend ("QWORD PTR ");
14448 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14449 oappend ("DWORD PTR ");
14451 oappend ("WORD PTR ");
14452 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14456 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14458 oappend ("WORD PTR ");
14459 if (!(rex
& REX_W
))
14460 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14463 if (sizeflag
& DFLAG
)
14464 oappend ("QWORD PTR ");
14466 oappend ("DWORD PTR ");
14467 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14470 case d_scalar_mode
:
14471 case d_scalar_swap_mode
:
14474 oappend ("DWORD PTR ");
14477 case q_scalar_mode
:
14478 case q_scalar_swap_mode
:
14480 oappend ("QWORD PTR ");
14483 if (address_mode
== mode_64bit
)
14484 oappend ("QWORD PTR ");
14486 oappend ("DWORD PTR ");
14489 if (sizeflag
& DFLAG
)
14490 oappend ("FWORD PTR ");
14492 oappend ("DWORD PTR ");
14493 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14496 oappend ("TBYTE PTR ");
14500 case evex_x_gscat_mode
:
14501 case evex_x_nobcst_mode
:
14504 switch (vex
.length
)
14507 oappend ("XMMWORD PTR ");
14510 oappend ("YMMWORD PTR ");
14513 oappend ("ZMMWORD PTR ");
14520 oappend ("XMMWORD PTR ");
14523 oappend ("XMMWORD PTR ");
14526 oappend ("YMMWORD PTR ");
14529 case evex_half_bcst_xmmq_mode
:
14533 switch (vex
.length
)
14536 oappend ("QWORD PTR ");
14539 oappend ("XMMWORD PTR ");
14542 oappend ("YMMWORD PTR ");
14552 switch (vex
.length
)
14557 oappend ("BYTE PTR ");
14567 switch (vex
.length
)
14572 oappend ("WORD PTR ");
14582 switch (vex
.length
)
14587 oappend ("DWORD PTR ");
14597 switch (vex
.length
)
14602 oappend ("QWORD PTR ");
14612 switch (vex
.length
)
14615 oappend ("WORD PTR ");
14618 oappend ("DWORD PTR ");
14621 oappend ("QWORD PTR ");
14631 switch (vex
.length
)
14634 oappend ("DWORD PTR ");
14637 oappend ("QWORD PTR ");
14640 oappend ("XMMWORD PTR ");
14650 switch (vex
.length
)
14653 oappend ("QWORD PTR ");
14656 oappend ("YMMWORD PTR ");
14659 oappend ("ZMMWORD PTR ");
14669 switch (vex
.length
)
14673 oappend ("XMMWORD PTR ");
14680 oappend ("OWORD PTR ");
14683 case vex_w_dq_mode
:
14684 case vex_scalar_w_dq_mode
:
14689 oappend ("QWORD PTR ");
14691 oappend ("DWORD PTR ");
14693 case vex_vsib_d_w_dq_mode
:
14694 case vex_vsib_q_w_dq_mode
:
14701 oappend ("QWORD PTR ");
14703 oappend ("DWORD PTR ");
14707 switch (vex
.length
)
14710 oappend ("XMMWORD PTR ");
14713 oappend ("YMMWORD PTR ");
14716 oappend ("ZMMWORD PTR ");
14723 case vex_vsib_q_w_d_mode
:
14724 case vex_vsib_d_w_d_mode
:
14725 if (!need_vex
|| !vex
.evex
)
14728 switch (vex
.length
)
14731 oappend ("QWORD PTR ");
14734 oappend ("XMMWORD PTR ");
14737 oappend ("YMMWORD PTR ");
14745 if (!need_vex
|| vex
.length
!= 128)
14748 oappend ("DWORD PTR ");
14750 oappend ("BYTE PTR ");
14756 oappend ("QWORD PTR ");
14758 oappend ("WORD PTR ");
14767 OP_E_register (int bytemode
, int sizeflag
)
14769 int reg
= modrm
.rm
;
14770 const char **names
;
14776 if ((sizeflag
& SUFFIX_ALWAYS
)
14777 && (bytemode
== b_swap_mode
14778 || bytemode
== v_swap_mode
14779 || bytemode
== dqw_swap_mode
))
14805 names
= address_mode
== mode_64bit
? names64
: names32
;
14811 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14824 case dqw_swap_mode
:
14830 if ((sizeflag
& DFLAG
)
14831 || (bytemode
!= v_mode
14832 && bytemode
!= v_swap_mode
))
14836 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14841 names
= names_mask
;
14846 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14849 oappend (names
[reg
]);
14853 OP_E_memory (int bytemode
, int sizeflag
)
14856 int add
= (rex
& REX_B
) ? 8 : 0;
14862 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14864 && bytemode
!= x_mode
14865 && bytemode
!= xmmq_mode
14866 && bytemode
!= evex_half_bcst_xmmq_mode
)
14875 case dqw_swap_mode
:
14882 case vex_vsib_d_w_dq_mode
:
14883 case vex_vsib_d_w_d_mode
:
14884 case vex_vsib_q_w_dq_mode
:
14885 case vex_vsib_q_w_d_mode
:
14886 case evex_x_gscat_mode
:
14888 shift
= vex
.w
? 3 : 2;
14891 case evex_half_bcst_xmmq_mode
:
14895 shift
= vex
.w
? 3 : 2;
14898 /* Fall through if vex.b == 0. */
14902 case evex_x_nobcst_mode
:
14904 switch (vex
.length
)
14927 case q_scalar_mode
:
14929 case q_scalar_swap_mode
:
14935 case d_scalar_mode
:
14937 case d_scalar_swap_mode
:
14949 /* Make necessary corrections to shift for modes that need it.
14950 For these modes we currently have shift 4, 5 or 6 depending on
14951 vex.length (it corresponds to xmmword, ymmword or zmmword
14952 operand). We might want to make it 3, 4 or 5 (e.g. for
14953 xmmq_mode). In case of broadcast enabled the corrections
14954 aren't needed, as element size is always 32 or 64 bits. */
14956 && (bytemode
== xmmq_mode
14957 || bytemode
== evex_half_bcst_xmmq_mode
))
14959 else if (bytemode
== xmmqd_mode
)
14961 else if (bytemode
== xmmdw_mode
)
14963 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14971 intel_operand_size (bytemode
, sizeflag
);
14974 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14976 /* 32/64 bit address mode */
14985 int addr32flag
= !((sizeflag
& AFLAG
)
14986 || bytemode
== v_bnd_mode
14987 || bytemode
== bnd_mode
);
14988 const char **indexes64
= names64
;
14989 const char **indexes32
= names32
;
14999 vindex
= sib
.index
;
15005 case vex_vsib_d_w_dq_mode
:
15006 case vex_vsib_d_w_d_mode
:
15007 case vex_vsib_q_w_dq_mode
:
15008 case vex_vsib_q_w_d_mode
:
15018 switch (vex
.length
)
15021 indexes64
= indexes32
= names_xmm
;
15025 || bytemode
== vex_vsib_q_w_dq_mode
15026 || bytemode
== vex_vsib_q_w_d_mode
)
15027 indexes64
= indexes32
= names_ymm
;
15029 indexes64
= indexes32
= names_xmm
;
15033 || bytemode
== vex_vsib_q_w_dq_mode
15034 || bytemode
== vex_vsib_q_w_d_mode
)
15035 indexes64
= indexes32
= names_zmm
;
15037 indexes64
= indexes32
= names_ymm
;
15044 haveindex
= vindex
!= 4;
15051 rbase
= base
+ add
;
15059 if (address_mode
== mode_64bit
&& !havesib
)
15065 FETCH_DATA (the_info
, codep
+ 1);
15067 if ((disp
& 0x80) != 0)
15069 if (vex
.evex
&& shift
> 0)
15077 /* In 32bit mode, we need index register to tell [offset] from
15078 [eiz*1 + offset]. */
15079 needindex
= (havesib
15082 && address_mode
== mode_32bit
);
15083 havedisp
= (havebase
15085 || (havesib
&& (haveindex
|| scale
!= 0)));
15088 if (modrm
.mod
!= 0 || base
== 5)
15090 if (havedisp
|| riprel
)
15091 print_displacement (scratchbuf
, disp
);
15093 print_operand_value (scratchbuf
, 1, disp
);
15094 oappend (scratchbuf
);
15098 oappend (sizeflag
& AFLAG
? "(%rip)" : "(%eip)");
15102 if ((havebase
|| haveindex
|| riprel
)
15103 && (bytemode
!= v_bnd_mode
)
15104 && (bytemode
!= bnd_mode
))
15105 used_prefixes
|= PREFIX_ADDR
;
15107 if (havedisp
|| (intel_syntax
&& riprel
))
15109 *obufp
++ = open_char
;
15110 if (intel_syntax
&& riprel
)
15113 oappend (sizeflag
& AFLAG
? "rip" : "eip");
15117 oappend (address_mode
== mode_64bit
&& !addr32flag
15118 ? names64
[rbase
] : names32
[rbase
]);
15121 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15122 print index to tell base + index from base. */
15126 || (havebase
&& base
!= ESP_REG_NUM
))
15128 if (!intel_syntax
|| havebase
)
15130 *obufp
++ = separator_char
;
15134 oappend (address_mode
== mode_64bit
&& !addr32flag
15135 ? indexes64
[vindex
] : indexes32
[vindex
]);
15137 oappend (address_mode
== mode_64bit
&& !addr32flag
15138 ? index64
: index32
);
15140 *obufp
++ = scale_char
;
15142 sprintf (scratchbuf
, "%d", 1 << scale
);
15143 oappend (scratchbuf
);
15147 && (disp
|| modrm
.mod
!= 0 || base
== 5))
15149 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
15154 else if (modrm
.mod
!= 1 && disp
!= -disp
)
15158 disp
= - (bfd_signed_vma
) disp
;
15162 print_displacement (scratchbuf
, disp
);
15164 print_operand_value (scratchbuf
, 1, disp
);
15165 oappend (scratchbuf
);
15168 *obufp
++ = close_char
;
15171 else if (intel_syntax
)
15173 if (modrm
.mod
!= 0 || base
== 5)
15175 if (!active_seg_prefix
)
15177 oappend (names_seg
[ds_reg
- es_reg
]);
15180 print_operand_value (scratchbuf
, 1, disp
);
15181 oappend (scratchbuf
);
15187 /* 16 bit address mode */
15188 used_prefixes
|= prefixes
& PREFIX_ADDR
;
15195 if ((disp
& 0x8000) != 0)
15200 FETCH_DATA (the_info
, codep
+ 1);
15202 if ((disp
& 0x80) != 0)
15207 if ((disp
& 0x8000) != 0)
15213 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
15215 print_displacement (scratchbuf
, disp
);
15216 oappend (scratchbuf
);
15219 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
15221 *obufp
++ = open_char
;
15223 oappend (index16
[modrm
.rm
]);
15225 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
15227 if ((bfd_signed_vma
) disp
>= 0)
15232 else if (modrm
.mod
!= 1)
15236 disp
= - (bfd_signed_vma
) disp
;
15239 print_displacement (scratchbuf
, disp
);
15240 oappend (scratchbuf
);
15243 *obufp
++ = close_char
;
15246 else if (intel_syntax
)
15248 if (!active_seg_prefix
)
15250 oappend (names_seg
[ds_reg
- es_reg
]);
15253 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
15254 oappend (scratchbuf
);
15257 if (vex
.evex
&& vex
.b
15258 && (bytemode
== x_mode
15259 || bytemode
== xmmq_mode
15260 || bytemode
== evex_half_bcst_xmmq_mode
))
15263 || bytemode
== xmmq_mode
15264 || bytemode
== evex_half_bcst_xmmq_mode
)
15266 switch (vex
.length
)
15269 oappend ("{1to2}");
15272 oappend ("{1to4}");
15275 oappend ("{1to8}");
15283 switch (vex
.length
)
15286 oappend ("{1to4}");
15289 oappend ("{1to8}");
15292 oappend ("{1to16}");
15302 OP_E (int bytemode
, int sizeflag
)
15304 /* Skip mod/rm byte. */
15308 if (modrm
.mod
== 3)
15309 OP_E_register (bytemode
, sizeflag
);
15311 OP_E_memory (bytemode
, sizeflag
);
15315 OP_G (int bytemode
, int sizeflag
)
15326 oappend (names8rex
[modrm
.reg
+ add
]);
15328 oappend (names8
[modrm
.reg
+ add
]);
15331 oappend (names16
[modrm
.reg
+ add
]);
15336 oappend (names32
[modrm
.reg
+ add
]);
15339 oappend (names64
[modrm
.reg
+ add
]);
15342 oappend (names_bnd
[modrm
.reg
]);
15349 case dqw_swap_mode
:
15352 oappend (names64
[modrm
.reg
+ add
]);
15355 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
15356 oappend (names32
[modrm
.reg
+ add
]);
15358 oappend (names16
[modrm
.reg
+ add
]);
15359 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15363 if (address_mode
== mode_64bit
)
15364 oappend (names64
[modrm
.reg
+ add
]);
15366 oappend (names32
[modrm
.reg
+ add
]);
15370 oappend (names_mask
[modrm
.reg
+ add
]);
15373 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15386 FETCH_DATA (the_info
, codep
+ 8);
15387 a
= *codep
++ & 0xff;
15388 a
|= (*codep
++ & 0xff) << 8;
15389 a
|= (*codep
++ & 0xff) << 16;
15390 a
|= (*codep
++ & 0xff) << 24;
15391 b
= *codep
++ & 0xff;
15392 b
|= (*codep
++ & 0xff) << 8;
15393 b
|= (*codep
++ & 0xff) << 16;
15394 b
|= (*codep
++ & 0xff) << 24;
15395 x
= a
+ ((bfd_vma
) b
<< 32);
15403 static bfd_signed_vma
15406 bfd_signed_vma x
= 0;
15408 FETCH_DATA (the_info
, codep
+ 4);
15409 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15410 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15411 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15412 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15416 static bfd_signed_vma
15419 bfd_signed_vma x
= 0;
15421 FETCH_DATA (the_info
, codep
+ 4);
15422 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15423 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15424 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15425 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15427 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15437 FETCH_DATA (the_info
, codep
+ 2);
15438 x
= *codep
++ & 0xff;
15439 x
|= (*codep
++ & 0xff) << 8;
15444 set_op (bfd_vma op
, int riprel
)
15446 op_index
[op_ad
] = op_ad
;
15447 if (address_mode
== mode_64bit
)
15449 op_address
[op_ad
] = op
;
15450 op_riprel
[op_ad
] = riprel
;
15454 /* Mask to get a 32-bit address. */
15455 op_address
[op_ad
] = op
& 0xffffffff;
15456 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15461 OP_REG (int code
, int sizeflag
)
15468 case es_reg
: case ss_reg
: case cs_reg
:
15469 case ds_reg
: case fs_reg
: case gs_reg
:
15470 oappend (names_seg
[code
- es_reg
]);
15482 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15483 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15484 s
= names16
[code
- ax_reg
+ add
];
15486 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15487 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15490 s
= names8rex
[code
- al_reg
+ add
];
15492 s
= names8
[code
- al_reg
];
15494 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15495 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15496 if (address_mode
== mode_64bit
15497 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15499 s
= names64
[code
- rAX_reg
+ add
];
15502 code
+= eAX_reg
- rAX_reg
;
15503 /* Fall through. */
15504 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15505 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15508 s
= names64
[code
- eAX_reg
+ add
];
15511 if (sizeflag
& DFLAG
)
15512 s
= names32
[code
- eAX_reg
+ add
];
15514 s
= names16
[code
- eAX_reg
+ add
];
15515 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15519 s
= INTERNAL_DISASSEMBLER_ERROR
;
15526 OP_IMREG (int code
, int sizeflag
)
15538 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15539 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15540 s
= names16
[code
- ax_reg
];
15542 case es_reg
: case ss_reg
: case cs_reg
:
15543 case ds_reg
: case fs_reg
: case gs_reg
:
15544 s
= names_seg
[code
- es_reg
];
15546 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15547 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15550 s
= names8rex
[code
- al_reg
];
15552 s
= names8
[code
- al_reg
];
15554 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15555 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15558 s
= names64
[code
- eAX_reg
];
15561 if (sizeflag
& DFLAG
)
15562 s
= names32
[code
- eAX_reg
];
15564 s
= names16
[code
- eAX_reg
];
15565 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15568 case z_mode_ax_reg
:
15569 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
15573 if (!(rex
& REX_W
))
15574 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15577 s
= INTERNAL_DISASSEMBLER_ERROR
;
15584 OP_I (int bytemode
, int sizeflag
)
15587 bfd_signed_vma mask
= -1;
15592 FETCH_DATA (the_info
, codep
+ 1);
15597 if (address_mode
== mode_64bit
)
15602 /* Fall through. */
15609 if (sizeflag
& DFLAG
)
15619 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15631 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15636 scratchbuf
[0] = '$';
15637 print_operand_value (scratchbuf
+ 1, 1, op
);
15638 oappend_maybe_intel (scratchbuf
);
15639 scratchbuf
[0] = '\0';
15643 OP_I64 (int bytemode
, int sizeflag
)
15646 bfd_signed_vma mask
= -1;
15648 if (address_mode
!= mode_64bit
)
15650 OP_I (bytemode
, sizeflag
);
15657 FETCH_DATA (the_info
, codep
+ 1);
15667 if (sizeflag
& DFLAG
)
15677 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15685 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15690 scratchbuf
[0] = '$';
15691 print_operand_value (scratchbuf
+ 1, 1, op
);
15692 oappend_maybe_intel (scratchbuf
);
15693 scratchbuf
[0] = '\0';
15697 OP_sI (int bytemode
, int sizeflag
)
15705 FETCH_DATA (the_info
, codep
+ 1);
15707 if ((op
& 0x80) != 0)
15709 if (bytemode
== b_T_mode
)
15711 if (address_mode
!= mode_64bit
15712 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15714 /* The operand-size prefix is overridden by a REX prefix. */
15715 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15723 if (!(rex
& REX_W
))
15725 if (sizeflag
& DFLAG
)
15733 /* The operand-size prefix is overridden by a REX prefix. */
15734 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15740 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15744 scratchbuf
[0] = '$';
15745 print_operand_value (scratchbuf
+ 1, 1, op
);
15746 oappend_maybe_intel (scratchbuf
);
15750 OP_J (int bytemode
, int sizeflag
)
15754 bfd_vma segment
= 0;
15759 FETCH_DATA (the_info
, codep
+ 1);
15761 if ((disp
& 0x80) != 0)
15765 if (isa64
== amd64
)
15767 if ((sizeflag
& DFLAG
)
15768 || (address_mode
== mode_64bit
15769 && (isa64
!= amd64
|| (rex
& REX_W
))))
15774 if ((disp
& 0x8000) != 0)
15776 /* In 16bit mode, address is wrapped around at 64k within
15777 the same segment. Otherwise, a data16 prefix on a jump
15778 instruction means that the pc is masked to 16 bits after
15779 the displacement is added! */
15781 if ((prefixes
& PREFIX_DATA
) == 0)
15782 segment
= ((start_pc
+ codep
- start_codep
)
15783 & ~((bfd_vma
) 0xffff));
15785 if (address_mode
!= mode_64bit
15786 || (isa64
== amd64
&& !(rex
& REX_W
)))
15787 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15790 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15793 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
15795 print_operand_value (scratchbuf
, 1, disp
);
15796 oappend (scratchbuf
);
15800 OP_SEG (int bytemode
, int sizeflag
)
15802 if (bytemode
== w_mode
)
15803 oappend (names_seg
[modrm
.reg
]);
15805 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
15809 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
15813 if (sizeflag
& DFLAG
)
15823 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15825 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
15827 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
15828 oappend (scratchbuf
);
15832 OP_OFF (int bytemode
, int sizeflag
)
15836 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15837 intel_operand_size (bytemode
, sizeflag
);
15840 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15847 if (!active_seg_prefix
)
15849 oappend (names_seg
[ds_reg
- es_reg
]);
15853 print_operand_value (scratchbuf
, 1, off
);
15854 oappend (scratchbuf
);
15858 OP_OFF64 (int bytemode
, int sizeflag
)
15862 if (address_mode
!= mode_64bit
15863 || (prefixes
& PREFIX_ADDR
))
15865 OP_OFF (bytemode
, sizeflag
);
15869 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15870 intel_operand_size (bytemode
, sizeflag
);
15877 if (!active_seg_prefix
)
15879 oappend (names_seg
[ds_reg
- es_reg
]);
15883 print_operand_value (scratchbuf
, 1, off
);
15884 oappend (scratchbuf
);
15888 ptr_reg (int code
, int sizeflag
)
15892 *obufp
++ = open_char
;
15893 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15894 if (address_mode
== mode_64bit
)
15896 if (!(sizeflag
& AFLAG
))
15897 s
= names32
[code
- eAX_reg
];
15899 s
= names64
[code
- eAX_reg
];
15901 else if (sizeflag
& AFLAG
)
15902 s
= names32
[code
- eAX_reg
];
15904 s
= names16
[code
- eAX_reg
];
15906 *obufp
++ = close_char
;
15911 OP_ESreg (int code
, int sizeflag
)
15917 case 0x6d: /* insw/insl */
15918 intel_operand_size (z_mode
, sizeflag
);
15920 case 0xa5: /* movsw/movsl/movsq */
15921 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15922 case 0xab: /* stosw/stosl */
15923 case 0xaf: /* scasw/scasl */
15924 intel_operand_size (v_mode
, sizeflag
);
15927 intel_operand_size (b_mode
, sizeflag
);
15930 oappend_maybe_intel ("%es:");
15931 ptr_reg (code
, sizeflag
);
15935 OP_DSreg (int code
, int sizeflag
)
15941 case 0x6f: /* outsw/outsl */
15942 intel_operand_size (z_mode
, sizeflag
);
15944 case 0xa5: /* movsw/movsl/movsq */
15945 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15946 case 0xad: /* lodsw/lodsl/lodsq */
15947 intel_operand_size (v_mode
, sizeflag
);
15950 intel_operand_size (b_mode
, sizeflag
);
15953 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15954 default segment register DS is printed. */
15955 if (!active_seg_prefix
)
15956 active_seg_prefix
= PREFIX_DS
;
15958 ptr_reg (code
, sizeflag
);
15962 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15970 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15972 all_prefixes
[last_lock_prefix
] = 0;
15973 used_prefixes
|= PREFIX_LOCK
;
15978 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15979 oappend_maybe_intel (scratchbuf
);
15983 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15992 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15994 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15995 oappend (scratchbuf
);
15999 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16001 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
16002 oappend_maybe_intel (scratchbuf
);
16006 OP_R (int bytemode
, int sizeflag
)
16008 /* Skip mod/rm byte. */
16011 OP_E_register (bytemode
, sizeflag
);
16015 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16017 int reg
= modrm
.reg
;
16018 const char **names
;
16020 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16021 if (prefixes
& PREFIX_DATA
)
16030 oappend (names
[reg
]);
16034 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16036 int reg
= modrm
.reg
;
16037 const char **names
;
16049 && bytemode
!= xmm_mode
16050 && bytemode
!= xmmq_mode
16051 && bytemode
!= evex_half_bcst_xmmq_mode
16052 && bytemode
!= ymm_mode
16053 && bytemode
!= scalar_mode
)
16055 switch (vex
.length
)
16062 || (bytemode
!= vex_vsib_q_w_dq_mode
16063 && bytemode
!= vex_vsib_q_w_d_mode
))
16075 else if (bytemode
== xmmq_mode
16076 || bytemode
== evex_half_bcst_xmmq_mode
)
16078 switch (vex
.length
)
16091 else if (bytemode
== ymm_mode
)
16095 oappend (names
[reg
]);
16099 OP_EM (int bytemode
, int sizeflag
)
16102 const char **names
;
16104 if (modrm
.mod
!= 3)
16107 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16109 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16110 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16112 OP_E (bytemode
, sizeflag
);
16116 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
16119 /* Skip mod/rm byte. */
16122 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16124 if (prefixes
& PREFIX_DATA
)
16133 oappend (names
[reg
]);
16136 /* cvt* are the only instructions in sse2 which have
16137 both SSE and MMX operands and also have 0x66 prefix
16138 in their opcode. 0x66 was originally used to differentiate
16139 between SSE and MMX instruction(operands). So we have to handle the
16140 cvt* separately using OP_EMC and OP_MXC */
16142 OP_EMC (int bytemode
, int sizeflag
)
16144 if (modrm
.mod
!= 3)
16146 if (intel_syntax
&& bytemode
== v_mode
)
16148 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16149 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16151 OP_E (bytemode
, sizeflag
);
16155 /* Skip mod/rm byte. */
16158 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16159 oappend (names_mm
[modrm
.rm
]);
16163 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16165 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16166 oappend (names_mm
[modrm
.reg
]);
16170 OP_EX (int bytemode
, int sizeflag
)
16173 const char **names
;
16175 /* Skip mod/rm byte. */
16179 if (modrm
.mod
!= 3)
16181 OP_E_memory (bytemode
, sizeflag
);
16196 if ((sizeflag
& SUFFIX_ALWAYS
)
16197 && (bytemode
== x_swap_mode
16198 || bytemode
== d_swap_mode
16199 || bytemode
== dqw_swap_mode
16200 || bytemode
== d_scalar_swap_mode
16201 || bytemode
== q_swap_mode
16202 || bytemode
== q_scalar_swap_mode
))
16206 && bytemode
!= xmm_mode
16207 && bytemode
!= xmmdw_mode
16208 && bytemode
!= xmmqd_mode
16209 && bytemode
!= xmm_mb_mode
16210 && bytemode
!= xmm_mw_mode
16211 && bytemode
!= xmm_md_mode
16212 && bytemode
!= xmm_mq_mode
16213 && bytemode
!= xmm_mdq_mode
16214 && bytemode
!= xmmq_mode
16215 && bytemode
!= evex_half_bcst_xmmq_mode
16216 && bytemode
!= ymm_mode
16217 && bytemode
!= d_scalar_mode
16218 && bytemode
!= d_scalar_swap_mode
16219 && bytemode
!= q_scalar_mode
16220 && bytemode
!= q_scalar_swap_mode
16221 && bytemode
!= vex_scalar_w_dq_mode
)
16223 switch (vex
.length
)
16238 else if (bytemode
== xmmq_mode
16239 || bytemode
== evex_half_bcst_xmmq_mode
)
16241 switch (vex
.length
)
16254 else if (bytemode
== ymm_mode
)
16258 oappend (names
[reg
]);
16262 OP_MS (int bytemode
, int sizeflag
)
16264 if (modrm
.mod
== 3)
16265 OP_EM (bytemode
, sizeflag
);
16271 OP_XS (int bytemode
, int sizeflag
)
16273 if (modrm
.mod
== 3)
16274 OP_EX (bytemode
, sizeflag
);
16280 OP_M (int bytemode
, int sizeflag
)
16282 if (modrm
.mod
== 3)
16283 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16286 OP_E (bytemode
, sizeflag
);
16290 OP_0f07 (int bytemode
, int sizeflag
)
16292 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
16295 OP_E (bytemode
, sizeflag
);
16298 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16299 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16302 NOP_Fixup1 (int bytemode
, int sizeflag
)
16304 if ((prefixes
& PREFIX_DATA
) != 0
16307 && address_mode
== mode_64bit
))
16308 OP_REG (bytemode
, sizeflag
);
16310 strcpy (obuf
, "nop");
16314 NOP_Fixup2 (int bytemode
, int sizeflag
)
16316 if ((prefixes
& PREFIX_DATA
) != 0
16319 && address_mode
== mode_64bit
))
16320 OP_IMREG (bytemode
, sizeflag
);
16323 static const char *const Suffix3DNow
[] = {
16324 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16325 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16326 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16327 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16328 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16329 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16330 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16331 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16332 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16333 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16334 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16335 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16336 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16337 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16338 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16339 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16340 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16341 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16342 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16343 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16344 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16345 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16346 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16347 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16348 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16349 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16350 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16351 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16352 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16353 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16354 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16355 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16356 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16357 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16358 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16359 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16360 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16361 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16362 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16363 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16364 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16365 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16366 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16367 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16368 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16369 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16370 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16371 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16372 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16373 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16374 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16375 /* CC */ NULL
, NULL
, NULL
, NULL
,
16376 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16377 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16378 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16379 /* DC */ NULL
, NULL
, NULL
, NULL
,
16380 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16381 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16382 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16383 /* EC */ NULL
, NULL
, NULL
, NULL
,
16384 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16385 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16386 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16387 /* FC */ NULL
, NULL
, NULL
, NULL
,
16391 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16393 const char *mnemonic
;
16395 FETCH_DATA (the_info
, codep
+ 1);
16396 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16397 place where an 8-bit immediate would normally go. ie. the last
16398 byte of the instruction. */
16399 obufp
= mnemonicendp
;
16400 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16402 oappend (mnemonic
);
16405 /* Since a variable sized modrm/sib chunk is between the start
16406 of the opcode (0x0f0f) and the opcode suffix, we need to do
16407 all the modrm processing first, and don't know until now that
16408 we have a bad opcode. This necessitates some cleaning up. */
16409 op_out
[0][0] = '\0';
16410 op_out
[1][0] = '\0';
16413 mnemonicendp
= obufp
;
16416 static struct op simd_cmp_op
[] =
16418 { STRING_COMMA_LEN ("eq") },
16419 { STRING_COMMA_LEN ("lt") },
16420 { STRING_COMMA_LEN ("le") },
16421 { STRING_COMMA_LEN ("unord") },
16422 { STRING_COMMA_LEN ("neq") },
16423 { STRING_COMMA_LEN ("nlt") },
16424 { STRING_COMMA_LEN ("nle") },
16425 { STRING_COMMA_LEN ("ord") }
16429 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16431 unsigned int cmp_type
;
16433 FETCH_DATA (the_info
, codep
+ 1);
16434 cmp_type
= *codep
++ & 0xff;
16435 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16438 char *p
= mnemonicendp
- 2;
16442 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16443 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16447 /* We have a reserved extension byte. Output it directly. */
16448 scratchbuf
[0] = '$';
16449 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16450 oappend_maybe_intel (scratchbuf
);
16451 scratchbuf
[0] = '\0';
16456 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
16457 int sizeflag ATTRIBUTE_UNUSED
)
16459 /* mwaitx %eax,%ecx,%ebx */
16462 const char **names
= (address_mode
== mode_64bit
16463 ? names64
: names32
);
16464 strcpy (op_out
[0], names
[0]);
16465 strcpy (op_out
[1], names
[1]);
16466 strcpy (op_out
[2], names
[3]);
16467 two_source_ops
= 1;
16469 /* Skip mod/rm byte. */
16475 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
16476 int sizeflag ATTRIBUTE_UNUSED
)
16478 /* mwait %eax,%ecx */
16481 const char **names
= (address_mode
== mode_64bit
16482 ? names64
: names32
);
16483 strcpy (op_out
[0], names
[0]);
16484 strcpy (op_out
[1], names
[1]);
16485 two_source_ops
= 1;
16487 /* Skip mod/rm byte. */
16493 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16494 int sizeflag ATTRIBUTE_UNUSED
)
16496 /* monitor %eax,%ecx,%edx" */
16499 const char **op1_names
;
16500 const char **names
= (address_mode
== mode_64bit
16501 ? names64
: names32
);
16503 if (!(prefixes
& PREFIX_ADDR
))
16504 op1_names
= (address_mode
== mode_16bit
16505 ? names16
: names
);
16508 /* Remove "addr16/addr32". */
16509 all_prefixes
[last_addr_prefix
] = 0;
16510 op1_names
= (address_mode
!= mode_32bit
16511 ? names32
: names16
);
16512 used_prefixes
|= PREFIX_ADDR
;
16514 strcpy (op_out
[0], op1_names
[0]);
16515 strcpy (op_out
[1], names
[1]);
16516 strcpy (op_out
[2], names
[2]);
16517 two_source_ops
= 1;
16519 /* Skip mod/rm byte. */
16527 /* Throw away prefixes and 1st. opcode byte. */
16528 codep
= insn_codep
+ 1;
16533 REP_Fixup (int bytemode
, int sizeflag
)
16535 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16537 if (prefixes
& PREFIX_REPZ
)
16538 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16545 OP_IMREG (bytemode
, sizeflag
);
16548 OP_ESreg (bytemode
, sizeflag
);
16551 OP_DSreg (bytemode
, sizeflag
);
16559 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16563 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16565 if (prefixes
& PREFIX_REPNZ
)
16566 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16569 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16570 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16574 HLE_Fixup1 (int bytemode
, int sizeflag
)
16577 && (prefixes
& PREFIX_LOCK
) != 0)
16579 if (prefixes
& PREFIX_REPZ
)
16580 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16581 if (prefixes
& PREFIX_REPNZ
)
16582 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16585 OP_E (bytemode
, sizeflag
);
16588 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16589 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16593 HLE_Fixup2 (int bytemode
, int sizeflag
)
16595 if (modrm
.mod
!= 3)
16597 if (prefixes
& PREFIX_REPZ
)
16598 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16599 if (prefixes
& PREFIX_REPNZ
)
16600 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16603 OP_E (bytemode
, sizeflag
);
16606 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16607 "xrelease" for memory operand. No check for LOCK prefix. */
16610 HLE_Fixup3 (int bytemode
, int sizeflag
)
16613 && last_repz_prefix
> last_repnz_prefix
16614 && (prefixes
& PREFIX_REPZ
) != 0)
16615 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16617 OP_E (bytemode
, sizeflag
);
16621 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
16626 /* Change cmpxchg8b to cmpxchg16b. */
16627 char *p
= mnemonicendp
- 2;
16628 mnemonicendp
= stpcpy (p
, "16b");
16631 else if ((prefixes
& PREFIX_LOCK
) != 0)
16633 if (prefixes
& PREFIX_REPZ
)
16634 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16635 if (prefixes
& PREFIX_REPNZ
)
16636 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16639 OP_M (bytemode
, sizeflag
);
16643 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
16645 const char **names
;
16649 switch (vex
.length
)
16663 oappend (names
[reg
]);
16667 CRC32_Fixup (int bytemode
, int sizeflag
)
16669 /* Add proper suffix to "crc32". */
16670 char *p
= mnemonicendp
;
16689 if (sizeflag
& DFLAG
)
16693 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16697 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16704 if (modrm
.mod
== 3)
16708 /* Skip mod/rm byte. */
16713 add
= (rex
& REX_B
) ? 8 : 0;
16714 if (bytemode
== b_mode
)
16718 oappend (names8rex
[modrm
.rm
+ add
]);
16720 oappend (names8
[modrm
.rm
+ add
]);
16726 oappend (names64
[modrm
.rm
+ add
]);
16727 else if ((prefixes
& PREFIX_DATA
))
16728 oappend (names16
[modrm
.rm
+ add
]);
16730 oappend (names32
[modrm
.rm
+ add
]);
16734 OP_E (bytemode
, sizeflag
);
16738 FXSAVE_Fixup (int bytemode
, int sizeflag
)
16740 /* Add proper suffix to "fxsave" and "fxrstor". */
16744 char *p
= mnemonicendp
;
16750 OP_M (bytemode
, sizeflag
);
16753 /* Display the destination register operand for instructions with
16757 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16760 const char **names
;
16768 reg
= vex
.register_specifier
;
16775 if (bytemode
== vex_scalar_mode
)
16777 oappend (names_xmm
[reg
]);
16781 switch (vex
.length
)
16788 case vex_vsib_q_w_dq_mode
:
16789 case vex_vsib_q_w_d_mode
:
16800 names
= names_mask
;
16814 case vex_vsib_q_w_dq_mode
:
16815 case vex_vsib_q_w_d_mode
:
16816 names
= vex
.w
? names_ymm
: names_xmm
;
16820 names
= names_mask
;
16834 oappend (names
[reg
]);
16837 /* Get the VEX immediate byte without moving codep. */
16839 static unsigned char
16840 get_vex_imm8 (int sizeflag
, int opnum
)
16842 int bytes_before_imm
= 0;
16844 if (modrm
.mod
!= 3)
16846 /* There are SIB/displacement bytes. */
16847 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16849 /* 32/64 bit address mode */
16850 int base
= modrm
.rm
;
16852 /* Check SIB byte. */
16855 FETCH_DATA (the_info
, codep
+ 1);
16857 /* When decoding the third source, don't increase
16858 bytes_before_imm as this has already been incremented
16859 by one in OP_E_memory while decoding the second
16862 bytes_before_imm
++;
16865 /* Don't increase bytes_before_imm when decoding the third source,
16866 it has already been incremented by OP_E_memory while decoding
16867 the second source operand. */
16873 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16874 SIB == 5, there is a 4 byte displacement. */
16876 /* No displacement. */
16879 /* 4 byte displacement. */
16880 bytes_before_imm
+= 4;
16883 /* 1 byte displacement. */
16884 bytes_before_imm
++;
16891 /* 16 bit address mode */
16892 /* Don't increase bytes_before_imm when decoding the third source,
16893 it has already been incremented by OP_E_memory while decoding
16894 the second source operand. */
16900 /* When modrm.rm == 6, there is a 2 byte displacement. */
16902 /* No displacement. */
16905 /* 2 byte displacement. */
16906 bytes_before_imm
+= 2;
16909 /* 1 byte displacement: when decoding the third source,
16910 don't increase bytes_before_imm as this has already
16911 been incremented by one in OP_E_memory while decoding
16912 the second source operand. */
16914 bytes_before_imm
++;
16922 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16923 return codep
[bytes_before_imm
];
16927 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16929 const char **names
;
16931 if (reg
== -1 && modrm
.mod
!= 3)
16933 OP_E_memory (bytemode
, sizeflag
);
16945 else if (reg
> 7 && address_mode
!= mode_64bit
)
16949 switch (vex
.length
)
16960 oappend (names
[reg
]);
16964 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16967 static unsigned char vex_imm8
;
16969 if (vex_w_done
== 0)
16973 /* Skip mod/rm byte. */
16977 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16980 reg
= vex_imm8
>> 4;
16982 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16984 else if (vex_w_done
== 1)
16989 reg
= vex_imm8
>> 4;
16991 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16995 /* Output the imm8 directly. */
16996 scratchbuf
[0] = '$';
16997 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16998 oappend_maybe_intel (scratchbuf
);
16999 scratchbuf
[0] = '\0';
17005 OP_Vex_2src (int bytemode
, int sizeflag
)
17007 if (modrm
.mod
== 3)
17009 int reg
= modrm
.rm
;
17013 oappend (names_xmm
[reg
]);
17018 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
17020 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
17021 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17023 OP_E (bytemode
, sizeflag
);
17028 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
17030 if (modrm
.mod
== 3)
17032 /* Skip mod/rm byte. */
17038 oappend (names_xmm
[vex
.register_specifier
]);
17040 OP_Vex_2src (bytemode
, sizeflag
);
17044 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
17047 OP_Vex_2src (bytemode
, sizeflag
);
17049 oappend (names_xmm
[vex
.register_specifier
]);
17053 OP_EX_VexW (int bytemode
, int sizeflag
)
17061 /* Skip mod/rm byte. */
17066 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
17071 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
17074 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17078 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17079 int sizeflag ATTRIBUTE_UNUSED
)
17081 /* Skip the immediate byte and check for invalid bits. */
17082 FETCH_DATA (the_info
, codep
+ 1);
17083 if (*codep
++ & 0xf)
17088 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17091 const char **names
;
17093 FETCH_DATA (the_info
, codep
+ 1);
17096 if (bytemode
!= x_mode
)
17103 if (reg
> 7 && address_mode
!= mode_64bit
)
17106 switch (vex
.length
)
17117 oappend (names
[reg
]);
17121 OP_XMM_VexW (int bytemode
, int sizeflag
)
17123 /* Turn off the REX.W bit since it is used for swapping operands
17126 OP_XMM (bytemode
, sizeflag
);
17130 OP_EX_Vex (int bytemode
, int sizeflag
)
17132 if (modrm
.mod
!= 3)
17134 if (vex
.register_specifier
!= 0)
17138 OP_EX (bytemode
, sizeflag
);
17142 OP_XMM_Vex (int bytemode
, int sizeflag
)
17144 if (modrm
.mod
!= 3)
17146 if (vex
.register_specifier
!= 0)
17150 OP_XMM (bytemode
, sizeflag
);
17154 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17156 switch (vex
.length
)
17159 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
17162 mnemonicendp
= stpcpy (obuf
, "vzeroall");
17169 static struct op vex_cmp_op
[] =
17171 { STRING_COMMA_LEN ("eq") },
17172 { STRING_COMMA_LEN ("lt") },
17173 { STRING_COMMA_LEN ("le") },
17174 { STRING_COMMA_LEN ("unord") },
17175 { STRING_COMMA_LEN ("neq") },
17176 { STRING_COMMA_LEN ("nlt") },
17177 { STRING_COMMA_LEN ("nle") },
17178 { STRING_COMMA_LEN ("ord") },
17179 { STRING_COMMA_LEN ("eq_uq") },
17180 { STRING_COMMA_LEN ("nge") },
17181 { STRING_COMMA_LEN ("ngt") },
17182 { STRING_COMMA_LEN ("false") },
17183 { STRING_COMMA_LEN ("neq_oq") },
17184 { STRING_COMMA_LEN ("ge") },
17185 { STRING_COMMA_LEN ("gt") },
17186 { STRING_COMMA_LEN ("true") },
17187 { STRING_COMMA_LEN ("eq_os") },
17188 { STRING_COMMA_LEN ("lt_oq") },
17189 { STRING_COMMA_LEN ("le_oq") },
17190 { STRING_COMMA_LEN ("unord_s") },
17191 { STRING_COMMA_LEN ("neq_us") },
17192 { STRING_COMMA_LEN ("nlt_uq") },
17193 { STRING_COMMA_LEN ("nle_uq") },
17194 { STRING_COMMA_LEN ("ord_s") },
17195 { STRING_COMMA_LEN ("eq_us") },
17196 { STRING_COMMA_LEN ("nge_uq") },
17197 { STRING_COMMA_LEN ("ngt_uq") },
17198 { STRING_COMMA_LEN ("false_os") },
17199 { STRING_COMMA_LEN ("neq_os") },
17200 { STRING_COMMA_LEN ("ge_oq") },
17201 { STRING_COMMA_LEN ("gt_oq") },
17202 { STRING_COMMA_LEN ("true_us") },
17206 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17208 unsigned int cmp_type
;
17210 FETCH_DATA (the_info
, codep
+ 1);
17211 cmp_type
= *codep
++ & 0xff;
17212 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
17215 char *p
= mnemonicendp
- 2;
17219 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
17220 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
17224 /* We have a reserved extension byte. Output it directly. */
17225 scratchbuf
[0] = '$';
17226 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17227 oappend_maybe_intel (scratchbuf
);
17228 scratchbuf
[0] = '\0';
17233 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17234 int sizeflag ATTRIBUTE_UNUSED
)
17236 unsigned int cmp_type
;
17241 FETCH_DATA (the_info
, codep
+ 1);
17242 cmp_type
= *codep
++ & 0xff;
17243 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17244 If it's the case, print suffix, otherwise - print the immediate. */
17245 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
17250 char *p
= mnemonicendp
- 2;
17252 /* vpcmp* can have both one- and two-lettered suffix. */
17266 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
17267 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
17271 /* We have a reserved extension byte. Output it directly. */
17272 scratchbuf
[0] = '$';
17273 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17274 oappend_maybe_intel (scratchbuf
);
17275 scratchbuf
[0] = '\0';
17279 static const struct op pclmul_op
[] =
17281 { STRING_COMMA_LEN ("lql") },
17282 { STRING_COMMA_LEN ("hql") },
17283 { STRING_COMMA_LEN ("lqh") },
17284 { STRING_COMMA_LEN ("hqh") }
17288 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17289 int sizeflag ATTRIBUTE_UNUSED
)
17291 unsigned int pclmul_type
;
17293 FETCH_DATA (the_info
, codep
+ 1);
17294 pclmul_type
= *codep
++ & 0xff;
17295 switch (pclmul_type
)
17306 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
17309 char *p
= mnemonicendp
- 3;
17314 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
17315 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
17319 /* We have a reserved extension byte. Output it directly. */
17320 scratchbuf
[0] = '$';
17321 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
17322 oappend_maybe_intel (scratchbuf
);
17323 scratchbuf
[0] = '\0';
17328 MOVBE_Fixup (int bytemode
, int sizeflag
)
17330 /* Add proper suffix to "movbe". */
17331 char *p
= mnemonicendp
;
17340 if (sizeflag
& SUFFIX_ALWAYS
)
17346 if (sizeflag
& DFLAG
)
17350 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17355 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17362 OP_M (bytemode
, sizeflag
);
17366 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17369 const char **names
;
17371 /* Skip mod/rm byte. */
17385 oappend (names
[reg
]);
17389 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17391 const char **names
;
17398 oappend (names
[vex
.register_specifier
]);
17402 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17405 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
17409 if ((rex
& REX_R
) != 0 || !vex
.r
)
17415 oappend (names_mask
[modrm
.reg
]);
17419 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17422 || (bytemode
!= evex_rounding_mode
17423 && bytemode
!= evex_sae_mode
))
17425 if (modrm
.mod
== 3 && vex
.b
)
17428 case evex_rounding_mode
:
17429 oappend (names_rounding
[vex
.ll
]);
17431 case evex_sae_mode
: