1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988, 89, 91, 93, 94, 95, 1996 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21 * 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 * modified by John Hassey (hassey@dg-rtp.dg.com)
27 * The main tables describing the instructions is essentially a copy
28 * of the "Opcode Map" chapter (Appendix A) of the Intel 80386
29 * Programmers Manual. Usually, there is a capital letter, followed
30 * by a small letter. The capital letter tell the addressing mode,
31 * and the small letter tells about the operand size. Refer to
32 * the Intel manual for details.
44 /* Points to first byte not fetched. */
45 bfd_byte
*max_fetched
;
46 bfd_byte the_buffer
[MAXLEN
];
51 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
52 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
54 #define FETCH_DATA(info, addr) \
55 ((addr) <= ((struct dis_private *)(info->private_data))->max_fetched \
56 ? 1 : fetch_data ((info), (addr)))
59 fetch_data (info
, addr
)
60 struct disassemble_info
*info
;
64 struct dis_private
*priv
= (struct dis_private
*)info
->private_data
;
65 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
67 status
= (*info
->read_memory_func
) (start
,
69 addr
- priv
->max_fetched
,
73 (*info
->memory_error_func
) (status
, start
, info
);
74 longjmp (priv
->bailout
, 1);
77 priv
->max_fetched
= addr
;
81 #define Eb OP_E, b_mode
82 #define indirEb OP_indirE, b_mode
83 #define Gb OP_G, b_mode
84 #define Ev OP_E, v_mode
85 #define indirEv OP_indirE, v_mode
86 #define Ew OP_E, w_mode
87 #define Ma OP_E, v_mode
89 #define Mp OP_E, 0 /* ? */
90 #define Gv OP_G, v_mode
91 #define Gw OP_G, w_mode
92 #define Rw OP_rm, w_mode
93 #define Rd OP_rm, d_mode
94 #define Ib OP_I, b_mode
95 #define sIb OP_sI, b_mode /* sign extened byte */
96 #define Iv OP_I, v_mode
97 #define Iw OP_I, w_mode
98 #define Jb OP_J, b_mode
99 #define Jv OP_J, v_mode
100 #define ONE OP_ONE, 0
101 #define Cd OP_C, d_mode
102 #define Dd OP_D, d_mode
103 #define Td OP_T, d_mode
105 #define eAX OP_REG, eAX_reg
106 #define eBX OP_REG, eBX_reg
107 #define eCX OP_REG, eCX_reg
108 #define eDX OP_REG, eDX_reg
109 #define eSP OP_REG, eSP_reg
110 #define eBP OP_REG, eBP_reg
111 #define eSI OP_REG, eSI_reg
112 #define eDI OP_REG, eDI_reg
113 #define AL OP_REG, al_reg
114 #define CL OP_REG, cl_reg
115 #define DL OP_REG, dl_reg
116 #define BL OP_REG, bl_reg
117 #define AH OP_REG, ah_reg
118 #define CH OP_REG, ch_reg
119 #define DH OP_REG, dh_reg
120 #define BH OP_REG, bh_reg
121 #define AX OP_REG, ax_reg
122 #define DX OP_REG, dx_reg
123 #define indirDX OP_REG, indir_dx_reg
125 #define Sw OP_SEG, w_mode
126 #define Ap OP_DIR, lptr
127 #define Av OP_DIR, v_mode
128 #define Ob OP_OFF, b_mode
129 #define Ov OP_OFF, v_mode
130 #define Xb OP_DSSI, b_mode
131 #define Xv OP_DSSI, v_mode
132 #define Yb OP_ESDI, b_mode
133 #define Yv OP_ESDI, v_mode
135 #define es OP_REG, es_reg
136 #define ss OP_REG, ss_reg
137 #define cs OP_REG, cs_reg
138 #define ds OP_REG, ds_reg
139 #define fs OP_REG, fs_reg
140 #define gs OP_REG, gs_reg
142 typedef int op_rtn
PARAMS ((int bytemode
, int aflag
, int dflag
));
144 static op_rtn OP_E
, OP_G
, OP_I
, OP_indirE
, OP_sI
, OP_REG
, OP_J
, OP_DIR
, OP_OFF
;
145 static op_rtn OP_ESDI
, OP_DSSI
, OP_SEG
, OP_ONE
, OP_C
, OP_D
, OP_T
, OP_rm
, OP_ST
;
146 static op_rtn OP_STi
;
148 static void append_prefix
PARAMS ((void));
149 static void set_op
PARAMS ((int op
));
150 static void putop
PARAMS ((char *template, int aflag
, int dflag
));
151 static void dofloat
PARAMS ((int aflag
, int dflag
));
152 static int get16
PARAMS ((void));
153 static int get32
PARAMS ((void));
154 static void ckprefix
PARAMS ((void));
196 #define indir_dx_reg 150
198 #define GRP1b NULL, NULL, 0
199 #define GRP1S NULL, NULL, 1
200 #define GRP1Ss NULL, NULL, 2
201 #define GRP2b NULL, NULL, 3
202 #define GRP2S NULL, NULL, 4
203 #define GRP2b_one NULL, NULL, 5
204 #define GRP2S_one NULL, NULL, 6
205 #define GRP2b_cl NULL, NULL, 7
206 #define GRP2S_cl NULL, NULL, 8
207 #define GRP3b NULL, NULL, 9
208 #define GRP3S NULL, NULL, 10
209 #define GRP4 NULL, NULL, 11
210 #define GRP5 NULL, NULL, 12
211 #define GRP6 NULL, NULL, 13
212 #define GRP7 NULL, NULL, 14
213 #define GRP8 NULL, NULL, 15
214 #define GRP9 NULL, NULL, 16
217 #define FLOAT NULL, NULL, FLOATCODE
229 static struct dis386 dis386
[] = {
247 { "(bad)" }, /* 0x0f extended opcode escape */
273 { "(bad)" }, /* SEG ES prefix */
282 { "(bad)" }, /* SEG CS prefix */
291 { "(bad)" }, /* SEG SS prefix */
300 { "(bad)" }, /* SEG DS prefix */
341 { "boundS", Gv
, Ma
},
343 { "(bad)" }, /* seg fs */
344 { "(bad)" }, /* seg gs */
345 { "(bad)" }, /* op size prefix */
346 { "(bad)" }, /* adr size prefix */
348 { "pushS", Iv
}, /* 386 book wrong */
349 { "imulS", Gv
, Ev
, Iv
},
350 { "pushl", sIb
}, /* push of byte really pushes 4 bytes */
351 { "imulS", Gv
, Ev
, Ib
},
352 { "insb", Yb
, indirDX
},
353 { "insS", Yv
, indirDX
},
354 { "outsb", indirDX
, Xb
},
355 { "outsS", indirDX
, Xv
},
394 { "xchgS", eCX
, eAX
},
395 { "xchgS", eDX
, eAX
},
396 { "xchgS", eBX
, eAX
},
397 { "xchgS", eSP
, eAX
},
398 { "xchgS", eBP
, eAX
},
399 { "xchgS", eSI
, eAX
},
400 { "xchgS", eDI
, eAX
},
405 { "(bad)" }, /* fwait */
421 { "testS", eAX
, Iv
},
423 { "stosS", Yv
, eAX
},
425 { "lodsS", eAX
, Xv
},
427 { "scasS", eAX
, Yv
},
496 { "inb", AL
, indirDX
},
497 { "inS", eAX
, indirDX
},
498 { "outb", indirDX
, AL
},
499 { "outS", indirDX
, eAX
},
501 { "(bad)" }, /* lock prefix */
503 { "(bad)" }, /* repne */
504 { "(bad)" }, /* repz */
520 static struct dis386 dis386_twobyte
[] = {
533 { "(bad)" }, { "ud2a" },
534 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
536 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
537 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
539 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
540 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
542 /* these are all backward in appendix A of the intel book */
552 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
553 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
555 { "wrmsr" }, { "rdtsc" }, { "rdmsr" }, { "rdpmc" },
556 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
558 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
559 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
561 { "cmovo", Gv
,Ev
}, { "cmovno", Gv
,Ev
}, { "cmovb", Gv
,Ev
}, { "cmovae", Gv
,Ev
},
562 { "cmove", Gv
,Ev
}, { "cmovne", Gv
,Ev
}, { "cmovbe", Gv
,Ev
}, { "cmova", Gv
,Ev
},
564 { "cmovs", Gv
,Ev
}, { "cmovns", Gv
,Ev
}, { "cmovp", Gv
,Ev
}, { "cmovnp", Gv
,Ev
},
565 { "cmovl", Gv
,Ev
}, { "cmovge", Gv
,Ev
}, { "cmovle", Gv
,Ev
}, { "cmovg", Gv
,Ev
},
567 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
568 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
570 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
571 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
573 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
574 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
576 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
577 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
579 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
580 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
582 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
583 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
625 { "shldS", Ev
, Gv
, Ib
},
626 { "shldS", Ev
, Gv
, CL
},
634 { "shrdS", Ev
, Gv
, Ib
},
635 { "shrdS", Ev
, Gv
, CL
},
639 { "cmpxchgb", Eb
, Gb
},
640 { "cmpxchgS", Ev
, Gv
},
641 { "lssS", Gv
, Mp
}, /* 386 lists only Mp */
643 { "lfsS", Gv
, Mp
}, /* 386 lists only Mp */
644 { "lgsS", Gv
, Mp
}, /* 386 lists only Mp */
645 { "movzbS", Gv
, Eb
},
646 { "movzwS", Gv
, Ew
},
654 { "movsbS", Gv
, Eb
},
655 { "movswS", Gv
, Ew
},
675 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
676 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
678 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
679 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
681 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
682 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
684 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
685 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
687 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
688 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
690 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
691 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
694 static const unsigned char onebyte_has_modrm
[256] = {
695 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
696 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
697 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
698 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
699 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
700 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
701 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0,
702 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
703 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
704 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
705 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
706 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
707 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0,
708 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1,
709 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
710 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1
713 static const unsigned char twobyte_has_modrm
[256] = {
714 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,
715 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
716 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,
717 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
718 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
719 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
720 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
721 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
722 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
723 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
724 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1,
725 1,1,1,1,1,1,1,1,0,0,1,1,1,1,1,1,
726 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,
727 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
728 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
729 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
732 static char obuf
[100];
734 static char scratchbuf
[100];
735 static unsigned char *start_codep
;
736 static unsigned char *codep
;
737 static disassemble_info
*the_info
;
741 static void oappend
PARAMS ((char *s
));
743 static char *names32
[]={
744 "%eax","%ecx","%edx","%ebx", "%esp","%ebp","%esi","%edi",
746 static char *names16
[] = {
747 "%ax","%cx","%dx","%bx","%sp","%bp","%si","%di",
749 static char *names8
[] = {
750 "%al","%cl","%dl","%bl","%ah","%ch","%dh","%bh",
752 static char *names_seg
[] = {
753 "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
755 static char *index16
[] = {
756 "bx+si","bx+di","bp+si","bp+di","si","di","bp","bx"
759 static struct dis386 grps
[][8] = {
877 { "imulS", eAX
, Ev
},
879 { "idivS", eAX
, Ev
},
897 { "lcall", indirEv
},
949 #define PREFIX_REPZ 1
950 #define PREFIX_REPNZ 2
951 #define PREFIX_LOCK 4
953 #define PREFIX_SS 0x10
954 #define PREFIX_DS 0x20
955 #define PREFIX_ES 0x40
956 #define PREFIX_FS 0x80
957 #define PREFIX_GS 0x100
958 #define PREFIX_DATA 0x200
959 #define PREFIX_ADR 0x400
960 #define PREFIX_FWAIT 0x800
970 FETCH_DATA (the_info
, codep
+ 1);
974 prefixes
|= PREFIX_REPZ
;
977 prefixes
|= PREFIX_REPNZ
;
980 prefixes
|= PREFIX_LOCK
;
983 prefixes
|= PREFIX_CS
;
986 prefixes
|= PREFIX_SS
;
989 prefixes
|= PREFIX_DS
;
992 prefixes
|= PREFIX_ES
;
995 prefixes
|= PREFIX_FS
;
998 prefixes
|= PREFIX_GS
;
1001 prefixes
|= PREFIX_DATA
;
1004 prefixes
|= PREFIX_ADR
;
1007 prefixes
|= PREFIX_FWAIT
;
1016 static char op1out
[100], op2out
[100], op3out
[100];
1017 static int op_address
[3], op_ad
, op_index
[3];
1018 static int start_pc
;
1022 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
1023 * (see topic "Redundant prefixes" in the "Differences from 8086"
1024 * section of the "Virtual 8086 Mode" chapter.)
1025 * 'pc' should be the address of this instruction, it will
1026 * be used to print the target address if this is a relative jump or call
1027 * The function returns the length of this instruction in bytes.
1030 int print_insn_x86
PARAMS ((bfd_vma pc
, disassemble_info
*info
, int aflag
,
1033 print_insn_i386 (pc
, info
)
1035 disassemble_info
*info
;
1037 print_insn_x86 (pc
, info
, 1, 1);
1041 print_insn_i8086 (pc
, info
)
1043 disassemble_info
*info
;
1045 print_insn_x86 (pc
, info
, 0, 0);
1049 print_insn_x86 (pc
, info
, aflag
, dflag
)
1051 disassemble_info
*info
;
1055 int enter_instruction
;
1056 char *first
, *second
, *third
;
1058 unsigned char need_modrm
;
1060 struct dis_private priv
;
1061 bfd_byte
*inbuf
= priv
.the_buffer
;
1063 info
->private_data
= (PTR
) &priv
;
1064 priv
.max_fetched
= priv
.the_buffer
;
1065 priv
.insn_start
= pc
;
1066 if (setjmp (priv
.bailout
) != 0)
1075 op_index
[0] = op_index
[1] = op_index
[2] = -1;
1079 start_codep
= inbuf
;
1084 FETCH_DATA (info
, codep
+ 1);
1086 enter_instruction
= 1;
1088 enter_instruction
= 0;
1092 if (prefixes
& PREFIX_REPZ
)
1094 if (prefixes
& PREFIX_REPNZ
)
1096 if (prefixes
& PREFIX_LOCK
)
1099 if ((prefixes
& PREFIX_FWAIT
)
1100 && ((*codep
< 0xd8) || (*codep
> 0xdf)))
1102 /* fwait not followed by floating point instruction */
1103 (*info
->fprintf_func
) (info
->stream
, "fwait");
1107 if (prefixes
& PREFIX_DATA
)
1110 if (prefixes
& PREFIX_ADR
)
1113 oappend ("addr16 ");
1118 FETCH_DATA (info
, codep
+ 2);
1119 dp
= &dis386_twobyte
[*++codep
];
1120 need_modrm
= twobyte_has_modrm
[*codep
];
1124 dp
= &dis386
[*codep
];
1125 need_modrm
= onebyte_has_modrm
[*codep
];
1131 FETCH_DATA (info
, codep
+ 1);
1132 mod
= (*codep
>> 6) & 3;
1133 reg
= (*codep
>> 3) & 7;
1137 if (dp
->name
== NULL
&& dp
->bytemode1
== FLOATCODE
)
1139 dofloat (aflag
, dflag
);
1143 if (dp
->name
== NULL
)
1144 dp
= &grps
[dp
->bytemode1
][reg
];
1146 putop (dp
->name
, aflag
, dflag
);
1151 (*dp
->op1
)(dp
->bytemode1
, aflag
, dflag
);
1156 (*dp
->op2
)(dp
->bytemode2
, aflag
, dflag
);
1161 (*dp
->op3
)(dp
->bytemode3
, aflag
, dflag
);
1164 obufp
= obuf
+ strlen (obuf
);
1165 for (i
= strlen (obuf
); i
< 6; i
++)
1168 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
1170 /* enter instruction is printed with operands in the
1171 * same order as the intel book; everything else
1172 * is printed in reverse order
1174 if (enter_instruction
)
1179 op_ad
= op_index
[0];
1180 op_index
[0] = op_index
[2];
1181 op_index
[2] = op_ad
;
1192 if (op_index
[0] != -1)
1193 (*info
->print_address_func
) (op_address
[op_index
[0]], info
);
1195 (*info
->fprintf_func
) (info
->stream
, "%s", first
);
1201 (*info
->fprintf_func
) (info
->stream
, ",");
1202 if (op_index
[1] != -1)
1203 (*info
->print_address_func
) (op_address
[op_index
[1]], info
);
1205 (*info
->fprintf_func
) (info
->stream
, "%s", second
);
1211 (*info
->fprintf_func
) (info
->stream
, ",");
1212 if (op_index
[2] != -1)
1213 (*info
->print_address_func
) (op_address
[op_index
[2]], info
);
1215 (*info
->fprintf_func
) (info
->stream
, "%s", third
);
1217 return (codep
- inbuf
);
1220 static char *float_mem
[] = {
1296 #define STi OP_STi, 0
1298 #define FGRPd9_2 NULL, NULL, 0
1299 #define FGRPd9_4 NULL, NULL, 1
1300 #define FGRPd9_5 NULL, NULL, 2
1301 #define FGRPd9_6 NULL, NULL, 3
1302 #define FGRPd9_7 NULL, NULL, 4
1303 #define FGRPda_5 NULL, NULL, 5
1304 #define FGRPdb_4 NULL, NULL, 6
1305 #define FGRPde_3 NULL, NULL, 7
1306 #define FGRPdf_4 NULL, NULL, 8
1308 static struct dis386 float_reg
[][8] = {
1311 { "fadd", ST
, STi
},
1312 { "fmul", ST
, STi
},
1315 { "fsub", ST
, STi
},
1316 { "fsubr", ST
, STi
},
1317 { "fdiv", ST
, STi
},
1318 { "fdivr", ST
, STi
},
1333 { "fcmovb", ST
, STi
},
1334 { "fcmove", ST
, STi
},
1335 { "fcmovbe",ST
, STi
},
1336 { "fcmovu", ST
, STi
},
1344 { "fcmovnb",ST
, STi
},
1345 { "fcmovne",ST
, STi
},
1346 { "fcmovnbe",ST
, STi
},
1347 { "fcmovnu",ST
, STi
},
1349 { "fucomi", ST
, STi
},
1350 { "fcomi", ST
, STi
},
1355 { "fadd", STi
, ST
},
1356 { "fmul", STi
, ST
},
1359 { "fsub", STi
, ST
},
1360 { "fsubr", STi
, ST
},
1361 { "fdiv", STi
, ST
},
1362 { "fdivr", STi
, ST
},
1377 { "faddp", STi
, ST
},
1378 { "fmulp", STi
, ST
},
1381 { "fsubp", STi
, ST
},
1382 { "fsubrp", STi
, ST
},
1383 { "fdivp", STi
, ST
},
1384 { "fdivrp", STi
, ST
},
1393 { "fucomip",ST
, STi
},
1394 { "fcomip", ST
, STi
},
1400 static char *fgrps
[][8] = {
1403 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1408 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
1413 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
1418 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
1423 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
1428 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1433 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
1434 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
1439 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1444 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1449 dofloat (aflag
, dflag
)
1454 unsigned char floatop
;
1456 floatop
= codep
[-1];
1460 putop (float_mem
[(floatop
- 0xd8) * 8 + reg
], aflag
, dflag
);
1462 OP_E (v_mode
, aflag
, dflag
);
1467 dp
= &float_reg
[floatop
- 0xd8][reg
];
1468 if (dp
->name
== NULL
)
1470 putop (fgrps
[dp
->bytemode1
][rm
], aflag
, dflag
);
1471 /* instruction fnstsw is only one with strange arg */
1473 && FETCH_DATA (the_info
, codep
+ 1)
1475 strcpy (op1out
, "%eax");
1479 putop (dp
->name
, aflag
, dflag
);
1482 (*dp
->op1
)(dp
->bytemode1
, aflag
, dflag
);
1485 (*dp
->op2
)(dp
->bytemode2
, aflag
, dflag
);
1491 OP_ST (ignore
, aflag
, dflag
)
1502 OP_STi (ignore
, aflag
, dflag
)
1507 sprintf (scratchbuf
, "%%st(%d)", rm
);
1508 oappend (scratchbuf
);
1513 /* capital letters in template are macros */
1515 putop (template, aflag
, dflag
)
1522 for (p
= template; *p
; p
++)
1529 case 'C': /* For jcxz/jecxz */
1534 if ((prefixes
& PREFIX_FWAIT
) == 0)
1538 /* operand size flag */
1554 obufp
+= strlen (s
);
1561 if (prefixes
& PREFIX_CS
)
1563 if (prefixes
& PREFIX_DS
)
1565 if (prefixes
& PREFIX_SS
)
1567 if (prefixes
& PREFIX_ES
)
1569 if (prefixes
& PREFIX_FS
)
1571 if (prefixes
& PREFIX_GS
)
1576 OP_indirE (bytemode
, aflag
, dflag
)
1582 return OP_E (bytemode
, aflag
, dflag
);
1586 OP_E (bytemode
, aflag
, dflag
)
1593 /* skip mod/rm byte */
1601 oappend (names8
[rm
]);
1604 oappend (names16
[rm
]);
1608 oappend (names32
[rm
]);
1610 oappend (names16
[rm
]);
1613 oappend ("<bad dis table>");
1622 if (aflag
) /* 32 bit address mode */
1637 FETCH_DATA (the_info
, codep
+ 1);
1638 scale
= (*codep
>> 6) & 3;
1639 index
= (*codep
>> 3) & 7;
1654 FETCH_DATA (the_info
, codep
+ 1);
1655 disp
= *(char *)codep
++;
1662 if (mod
!= 0 || base
== 5)
1664 sprintf (scratchbuf
, "0x%x", disp
);
1665 oappend (scratchbuf
);
1668 if (havebase
|| (havesib
&& (index
!= 4 || scale
!= 0)))
1672 oappend (names32
[base
]);
1677 sprintf (scratchbuf
, ",%s", names32
[index
]);
1678 oappend (scratchbuf
);
1680 sprintf (scratchbuf
, ",%d", 1 << scale
);
1681 oappend (scratchbuf
);
1687 { /* 16 bit address mode */
1692 disp
= (short) get16 ();
1695 FETCH_DATA (the_info
, codep
+ 1);
1696 disp
= *(char *)codep
++;
1699 disp
= (short) get16 ();
1703 if (mod
!= 0 || rm
== 6)
1705 sprintf (scratchbuf
, "0x%x", disp
);
1706 oappend (scratchbuf
);
1709 if (mod
!= 0 || rm
!= 6)
1712 oappend (index16
[rm
]);
1720 OP_G (bytemode
, aflag
, dflag
)
1728 oappend (names8
[reg
]);
1731 oappend (names16
[reg
]);
1734 oappend (names32
[reg
]);
1738 oappend (names32
[reg
]);
1740 oappend (names16
[reg
]);
1743 oappend ("<internal disassembler error>");
1754 FETCH_DATA (the_info
, codep
+ 4);
1755 x
= *codep
++ & 0xff;
1756 x
|= (*codep
++ & 0xff) << 8;
1757 x
|= (*codep
++ & 0xff) << 16;
1758 x
|= (*codep
++ & 0xff) << 24;
1767 FETCH_DATA (the_info
, codep
+ 2);
1768 x
= *codep
++ & 0xff;
1769 x
|= (*codep
++ & 0xff) << 8;
1777 op_index
[op_ad
] = op_ad
;
1778 op_address
[op_ad
] = op
;
1782 OP_REG (code
, aflag
, dflag
)
1791 case indir_dx_reg
: s
= "(%dx)"; break;
1792 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
1793 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
1794 s
= names16
[code
- ax_reg
];
1796 case es_reg
: case ss_reg
: case cs_reg
:
1797 case ds_reg
: case fs_reg
: case gs_reg
:
1798 s
= names_seg
[code
- es_reg
];
1800 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
1801 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
1802 s
= names8
[code
- al_reg
];
1804 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
1805 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
1807 s
= names32
[code
- eAX_reg
];
1809 s
= names16
[code
- eAX_reg
];
1812 s
= "<internal disassembler error>";
1820 OP_I (bytemode
, aflag
, dflag
)
1830 FETCH_DATA (the_info
, codep
+ 1);
1831 op
= *codep
++ & 0xff;
1843 oappend ("<internal disassembler error>");
1846 sprintf (scratchbuf
, "$0x%x", op
);
1847 oappend (scratchbuf
);
1852 OP_sI (bytemode
, aflag
, dflag
)
1862 FETCH_DATA (the_info
, codep
+ 1);
1863 op
= *(char *)codep
++;
1869 op
= (short)get16();
1872 op
= (short)get16 ();
1875 oappend ("<internal disassembler error>");
1878 sprintf (scratchbuf
, "$0x%x", op
);
1879 oappend (scratchbuf
);
1884 OP_J (bytemode
, aflag
, dflag
)
1895 FETCH_DATA (the_info
, codep
+ 1);
1896 disp
= *(char *)codep
++;
1903 disp
= (short)get16 ();
1904 /* for some reason, a data16 prefix on a jump instruction
1905 means that the pc is masked to 16 bits after the
1906 displacement is added! */
1911 oappend ("<internal disassembler error>");
1914 disp
= (start_pc
+ codep
- start_codep
+ disp
) & mask
;
1916 sprintf (scratchbuf
, "0x%x", disp
);
1917 oappend (scratchbuf
);
1923 OP_SEG (dummy
, aflag
, dflag
)
1928 static char *sreg
[] = {
1929 "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
1932 oappend (sreg
[reg
]);
1937 OP_DIR (size
, aflag
, dflag
)
1957 sprintf (scratchbuf
, "0x%x,0x%x", seg
, offset
);
1958 oappend (scratchbuf
);
1964 offset
= (short)get16 ();
1966 offset
= start_pc
+ codep
- start_codep
+ offset
;
1968 sprintf (scratchbuf
, "0x%x", offset
);
1969 oappend (scratchbuf
);
1972 oappend ("<internal disassembler error>");
1980 OP_OFF (bytemode
, aflag
, dflag
)
1994 sprintf (scratchbuf
, "0x%x", off
);
1995 oappend (scratchbuf
);
2001 OP_ESDI (dummy
, aflag
, dflag
)
2007 oappend (aflag
? "%edi" : "%di");
2014 OP_DSSI (dummy
, aflag
, dflag
)
2020 oappend (aflag
? "%esi" : "%si");
2027 OP_ONE (dummy
, aflag
, dflag
)
2038 OP_C (dummy
, aflag
, dflag
)
2043 codep
++; /* skip mod/rm */
2044 sprintf (scratchbuf
, "%%cr%d", reg
);
2045 oappend (scratchbuf
);
2051 OP_D (dummy
, aflag
, dflag
)
2056 codep
++; /* skip mod/rm */
2057 sprintf (scratchbuf
, "%%db%d", reg
);
2058 oappend (scratchbuf
);
2064 OP_T (dummy
, aflag
, dflag
)
2069 codep
++; /* skip mod/rm */
2070 sprintf (scratchbuf
, "%%tr%d", reg
);
2071 oappend (scratchbuf
);
2076 OP_rm (bytemode
, aflag
, dflag
)
2084 oappend (names32
[rm
]);
2087 oappend (names16
[rm
]);
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