opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_XMM_Vex (int, int);
  95 static void OP_XMM_VexW (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void CMPXCHG8B_Fixup (int, int);
 111 static void XMM_Fixup (int, int);
 112 static void CRC32_Fixup (int, int);
 113 static void OP_LWPCB_E (int, int);
 114 static void OP_LWP_E (int, int);
 115 static void OP_LWP_I (int, int);
 116 static void OP_Vex_2src_1 (int, int);
 117 static void OP_Vex_2src_2 (int, int);
 118
 119 static void MOVBE_Fixup (int, int);
 120
 121 struct dis_private {
 122   /* Points to first byte not fetched.  */
 123   bfd_byte *max_fetched;
 124   bfd_byte the_buffer[MAX_MNEM_SIZE];
 125   bfd_vma insn_start;
 126   int orig_sizeflag;
 127   jmp_buf bailout;
 128 };
 129
 130 enum address_mode
 131 {
 132   mode_16bit,
 133   mode_32bit,
 134   mode_64bit
 135 };
 136
 137 enum address_mode address_mode;
 138
 139 /* Flags for the prefixes for the current instruction.  See below.  */
 140 static int prefixes;
 141
 142 /* REX prefix the current instruction.  See below.  */
 143 static int rex;
 144 /* Bits of REX we've already used.  */
 145 static int rex_used;
 146 /* Original REX prefix.  */
 147 static int rex_original;
 148 /* REX bits in original REX prefix ignored.  It may not be the same
 149    as rex_original since some bits may not be ignored.  */
 150 static int rex_ignored;
 151 /* Mark parts used in the REX prefix.  When we are testing for
 152    empty prefix (for 8bit register REX extension), just mask it
 153    out.  Otherwise test for REX bit is excuse for existence of REX
 154    only in case value is nonzero.  */
 155 #define USED_REX(value)                                 \
 156   {                                                     \
 157     if (value)                                          \
 158       {                                                 \
 159         if ((rex & value))                              \
 160           rex_used |= (value) | REX_OPCODE;             \
 161       }                                                 \
 162     else                                                \
 163       rex_used |= REX_OPCODE;                           \
 164   }
 165
 166 /* Flags for prefixes which we somehow handled when printing the
 167    current instruction.  */
 168 static int used_prefixes;
 169
 170 /* Flags stored in PREFIXES.  */
 171 #define PREFIX_REPZ 1
 172 #define PREFIX_REPNZ 2
 173 #define PREFIX_LOCK 4
 174 #define PREFIX_CS 8
 175 #define PREFIX_SS 0x10
 176 #define PREFIX_DS 0x20
 177 #define PREFIX_ES 0x40
 178 #define PREFIX_FS 0x80
 179 #define PREFIX_GS 0x100
 180 #define PREFIX_DATA 0x200
 181 #define PREFIX_ADDR 0x400
 182 #define PREFIX_FWAIT 0x800
 183
 184 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 185    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 186    on error.  */
 187 #define FETCH_DATA(info, addr) \
 188   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 189    ? 1 : fetch_data ((info), (addr)))
 190
 191 static int
 192 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 193 {
 194   int status;
 195   struct dis_private *priv = (struct dis_private *) info->private_data;
 196   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 197
 198   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 199     status = (*info->read_memory_func) (start,
 200                                         priv->max_fetched,
 201                                         addr - priv->max_fetched,
 202                                         info);
 203   else
 204     status = -1;
 205   if (status != 0)
 206     {
 207       /* If we did manage to read at least one byte, then
 208          print_insn_i386 will do something sensible.  Otherwise, print
 209          an error.  We do that here because this is where we know
 210          STATUS.  */
 211       if (priv->max_fetched == priv->the_buffer)
 212         (*info->memory_error_func) (status, start, info);
 213       longjmp (priv->bailout, 1);
 214     }
 215   else
 216     priv->max_fetched = addr;
 217   return 1;
 218 }
 219
 220 #define XX { NULL, 0 }
 221
 222 #define Eb { OP_E, b_mode }
 223 #define EbS { OP_E, b_swap_mode }
 224 #define Ev { OP_E, v_mode }
 225 #define EvS { OP_E, v_swap_mode }
 226 #define Ed { OP_E, d_mode }
 227 #define Edq { OP_E, dq_mode }
 228 #define Edqw { OP_E, dqw_mode }
 229 #define Edqb { OP_E, dqb_mode }
 230 #define Edqd { OP_E, dqd_mode }
 231 #define Eq { OP_E, q_mode }
 232 #define indirEv { OP_indirE, stack_v_mode }
 233 #define indirEp { OP_indirE, f_mode }
 234 #define stackEv { OP_E, stack_v_mode }
 235 #define Em { OP_E, m_mode }
 236 #define Ew { OP_E, w_mode }
 237 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 238 #define Ma { OP_M, a_mode }
 239 #define Mb { OP_M, b_mode }
 240 #define Md { OP_M, d_mode }
 241 #define Mo { OP_M, o_mode }
 242 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 243 #define Mq { OP_M, q_mode }
 244 #define Mx { OP_M, x_mode }
 245 #define Mxmm { OP_M, xmm_mode }
 246 #define Gb { OP_G, b_mode }
 247 #define Gv { OP_G, v_mode }
 248 #define Gd { OP_G, d_mode }
 249 #define Gdq { OP_G, dq_mode }
 250 #define Gm { OP_G, m_mode }
 251 #define Gw { OP_G, w_mode }
 252 #define Rd { OP_R, d_mode }
 253 #define Rm { OP_R, m_mode }
 254 #define Ib { OP_I, b_mode }
 255 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 256 #define Iv { OP_I, v_mode }
 257 #define Iq { OP_I, q_mode }
 258 #define Iv64 { OP_I64, v_mode }
 259 #define Iw { OP_I, w_mode }
 260 #define I1 { OP_I, const_1_mode }
 261 #define Jb { OP_J, b_mode }
 262 #define Jv { OP_J, v_mode }
 263 #define Cm { OP_C, m_mode }
 264 #define Dm { OP_D, m_mode }
 265 #define Td { OP_T, d_mode }
 266 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 267
 268 #define RMeAX { OP_REG, eAX_reg }
 269 #define RMeBX { OP_REG, eBX_reg }
 270 #define RMeCX { OP_REG, eCX_reg }
 271 #define RMeDX { OP_REG, eDX_reg }
 272 #define RMeSP { OP_REG, eSP_reg }
 273 #define RMeBP { OP_REG, eBP_reg }
 274 #define RMeSI { OP_REG, eSI_reg }
 275 #define RMeDI { OP_REG, eDI_reg }
 276 #define RMrAX { OP_REG, rAX_reg }
 277 #define RMrBX { OP_REG, rBX_reg }
 278 #define RMrCX { OP_REG, rCX_reg }
 279 #define RMrDX { OP_REG, rDX_reg }
 280 #define RMrSP { OP_REG, rSP_reg }
 281 #define RMrBP { OP_REG, rBP_reg }
 282 #define RMrSI { OP_REG, rSI_reg }
 283 #define RMrDI { OP_REG, rDI_reg }
 284 #define RMAL { OP_REG, al_reg }
 285 #define RMAL { OP_REG, al_reg }
 286 #define RMCL { OP_REG, cl_reg }
 287 #define RMDL { OP_REG, dl_reg }
 288 #define RMBL { OP_REG, bl_reg }
 289 #define RMAH { OP_REG, ah_reg }
 290 #define RMCH { OP_REG, ch_reg }
 291 #define RMDH { OP_REG, dh_reg }
 292 #define RMBH { OP_REG, bh_reg }
 293 #define RMAX { OP_REG, ax_reg }
 294 #define RMDX { OP_REG, dx_reg }
 295
 296 #define eAX { OP_IMREG, eAX_reg }
 297 #define eBX { OP_IMREG, eBX_reg }
 298 #define eCX { OP_IMREG, eCX_reg }
 299 #define eDX { OP_IMREG, eDX_reg }
 300 #define eSP { OP_IMREG, eSP_reg }
 301 #define eBP { OP_IMREG, eBP_reg }
 302 #define eSI { OP_IMREG, eSI_reg }
 303 #define eDI { OP_IMREG, eDI_reg }
 304 #define AL { OP_IMREG, al_reg }
 305 #define CL { OP_IMREG, cl_reg }
 306 #define DL { OP_IMREG, dl_reg }
 307 #define BL { OP_IMREG, bl_reg }
 308 #define AH { OP_IMREG, ah_reg }
 309 #define CH { OP_IMREG, ch_reg }
 310 #define DH { OP_IMREG, dh_reg }
 311 #define BH { OP_IMREG, bh_reg }
 312 #define AX { OP_IMREG, ax_reg }
 313 #define DX { OP_IMREG, dx_reg }
 314 #define zAX { OP_IMREG, z_mode_ax_reg }
 315 #define indirDX { OP_IMREG, indir_dx_reg }
 316
 317 #define Sw { OP_SEG, w_mode }
 318 #define Sv { OP_SEG, v_mode }
 319 #define Ap { OP_DIR, 0 }
 320 #define Ob { OP_OFF64, b_mode }
 321 #define Ov { OP_OFF64, v_mode }
 322 #define Xb { OP_DSreg, eSI_reg }
 323 #define Xv { OP_DSreg, eSI_reg }
 324 #define Xz { OP_DSreg, eSI_reg }
 325 #define Yb { OP_ESreg, eDI_reg }
 326 #define Yv { OP_ESreg, eDI_reg }
 327 #define DSBX { OP_DSreg, eBX_reg }
 328
 329 #define es { OP_REG, es_reg }
 330 #define ss { OP_REG, ss_reg }
 331 #define cs { OP_REG, cs_reg }
 332 #define ds { OP_REG, ds_reg }
 333 #define fs { OP_REG, fs_reg }
 334 #define gs { OP_REG, gs_reg }
 335
 336 #define MX { OP_MMX, 0 }
 337 #define XM { OP_XMM, 0 }
 338 #define XMM { OP_XMM, xmm_mode }
 339 #define EM { OP_EM, v_mode }
 340 #define EMS { OP_EM, v_swap_mode }
 341 #define EMd { OP_EM, d_mode }
 342 #define EMx { OP_EM, x_mode }
 343 #define EXw { OP_EX, w_mode }
 344 #define EXd { OP_EX, d_mode }
 345 #define EXdS { OP_EX, d_swap_mode }
 346 #define EXq { OP_EX, q_mode }
 347 #define EXqS { OP_EX, q_swap_mode }
 348 #define EXx { OP_EX, x_mode }
 349 #define EXxS { OP_EX, x_swap_mode }
 350 #define EXxmm { OP_EX, xmm_mode }
 351 #define EXxmmq { OP_EX, xmmq_mode }
 352 #define EXymmq { OP_EX, ymmq_mode }
 353 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 354 #define MS { OP_MS, v_mode }
 355 #define XS { OP_XS, v_mode }
 356 #define EMCq { OP_EMC, q_mode }
 357 #define MXC { OP_MXC, 0 }
 358 #define OPSUF { OP_3DNowSuffix, 0 }
 359 #define CMP { CMP_Fixup, 0 }
 360 #define XMM0 { XMM_Fixup, 0 }
 361 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 362 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 363
 364 #define Vex { OP_VEX, vex_mode }
 365 #define Vex128 { OP_VEX, vex128_mode }
 366 #define Vex256 { OP_VEX, vex256_mode }
 367 #define VexI4 { VEXI4_Fixup, 0}
 368 #define EXdVex { OP_EX_Vex, d_mode }
 369 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 370 #define EXqVex { OP_EX_Vex, q_mode }
 371 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 372 #define EXVexW { OP_EX_VexW, x_mode }
 373 #define EXdVexW { OP_EX_VexW, d_mode }
 374 #define EXqVexW { OP_EX_VexW, q_mode }
 375 #define XMVex { OP_XMM_Vex, 0 }
 376 #define XMVexW { OP_XMM_VexW, 0 }
 377 #define XMVexI4 { OP_REG_VexI4, x_mode }
 378 #define PCLMUL { PCLMUL_Fixup, 0 }
 379 #define VZERO { VZERO_Fixup, 0 }
 380 #define VCMP { VCMP_Fixup, 0 }
 381
 382 /* Used handle "rep" prefix for string instructions.  */
 383 #define Xbr { REP_Fixup, eSI_reg }
 384 #define Xvr { REP_Fixup, eSI_reg }
 385 #define Ybr { REP_Fixup, eDI_reg }
 386 #define Yvr { REP_Fixup, eDI_reg }
 387 #define Yzr { REP_Fixup, eDI_reg }
 388 #define indirDXr { REP_Fixup, indir_dx_reg }
 389 #define ALr { REP_Fixup, al_reg }
 390 #define eAXr { REP_Fixup, eAX_reg }
 391
 392 #define cond_jump_flag { NULL, cond_jump_mode }
 393 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 394
 395 /* bits in sizeflag */
 396 #define SUFFIX_ALWAYS 4
 397 #define AFLAG 2
 398 #define DFLAG 1
 399
 400 enum
 401 {
 402   /* byte operand */
 403   b_mode = 1,
 404   /* byte operand with operand swapped */
 405   b_swap_mode,
 406   /* operand size depends on prefixes */
 407   v_mode,
 408   /* operand size depends on prefixes with operand swapped */
 409   v_swap_mode,
 410   /* word operand */
 411   w_mode,
 412   /* double word operand  */
 413   d_mode,
 414   /* double word operand with operand swapped */
 415   d_swap_mode,
 416   /* quad word operand */
 417   q_mode,
 418   /* quad word operand with operand swapped */
 419   q_swap_mode,
 420   /* ten-byte operand */
 421   t_mode,
 422   /* 16-byte XMM or 32-byte YMM operand */
 423   x_mode,
 424   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 425   x_swap_mode,
 426   /* 16-byte XMM operand */
 427   xmm_mode,
 428   /* 16-byte XMM or quad word operand */
 429   xmmq_mode,
 430   /* 32-byte YMM or quad word operand */
 431   ymmq_mode,
 432   /* d_mode in 32bit, q_mode in 64bit mode.  */
 433   m_mode,
 434   /* pair of v_mode operands */
 435   a_mode,
 436   cond_jump_mode,
 437   loop_jcxz_mode,
 438   /* operand size depends on REX prefixes.  */
 439   dq_mode,
 440   /* registers like dq_mode, memory like w_mode.  */
 441   dqw_mode,
 442   /* 4- or 6-byte pointer operand */
 443   f_mode,
 444   const_1_mode,
 445   /* v_mode for stack-related opcodes.  */
 446   stack_v_mode,
 447   /* non-quad operand size depends on prefixes */
 448   z_mode,
 449   /* 16-byte operand */
 450   o_mode,
 451   /* registers like dq_mode, memory like b_mode.  */
 452   dqb_mode,
 453   /* registers like dq_mode, memory like d_mode.  */
 454   dqd_mode,
 455   /* normal vex mode */
 456   vex_mode,
 457   /* 128bit vex mode */
 458   vex128_mode,
 459   /* 256bit vex mode */
 460   vex256_mode,
 461   /* operand size depends on the VEX.W bit.  */
 462   vex_w_dq_mode,
 463
 464   es_reg,
 465   cs_reg,
 466   ss_reg,
 467   ds_reg,
 468   fs_reg,
 469   gs_reg,
 470
 471   eAX_reg,
 472   eCX_reg,
 473   eDX_reg,
 474   eBX_reg,
 475   eSP_reg,
 476   eBP_reg,
 477   eSI_reg,
 478   eDI_reg,
 479
 480   al_reg,
 481   cl_reg,
 482   dl_reg,
 483   bl_reg,
 484   ah_reg,
 485   ch_reg,
 486   dh_reg,
 487   bh_reg,
 488
 489   ax_reg,
 490   cx_reg,
 491   dx_reg,
 492   bx_reg,
 493   sp_reg,
 494   bp_reg,
 495   si_reg,
 496   di_reg,
 497
 498   rAX_reg,
 499   rCX_reg,
 500   rDX_reg,
 501   rBX_reg,
 502   rSP_reg,
 503   rBP_reg,
 504   rSI_reg,
 505   rDI_reg,
 506
 507   z_mode_ax_reg,
 508   indir_dx_reg
 509 };
 510
 511 enum
 512 {
 513   FLOATCODE = 1,
 514   USE_REG_TABLE,
 515   USE_MOD_TABLE,
 516   USE_RM_TABLE,
 517   USE_PREFIX_TABLE,
 518   USE_X86_64_TABLE,
 519   USE_3BYTE_TABLE,
 520   USE_XOP_8F_TABLE,
 521   USE_VEX_C4_TABLE,
 522   USE_VEX_C5_TABLE,
 523   USE_VEX_LEN_TABLE
 524 };
 525
 526 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 527
 528 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 529 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 530 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 531 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 532 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 533 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 534 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 535 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 536 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 537 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 538 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 539
 540 enum
 541 {
 542   REG_80 = 0,
 543   REG_81,
 544   REG_82,
 545   REG_8F,
 546   REG_C0,
 547   REG_C1,
 548   REG_C6,
 549   REG_C7,
 550   REG_D0,
 551   REG_D1,
 552   REG_D2,
 553   REG_D3,
 554   REG_F6,
 555   REG_F7,
 556   REG_FE,
 557   REG_FF,
 558   REG_0F00,
 559   REG_0F01,
 560   REG_0F0D,
 561   REG_0F18,
 562   REG_0F71,
 563   REG_0F72,
 564   REG_0F73,
 565   REG_0FA6,
 566   REG_0FA7,
 567   REG_0FAE,
 568   REG_0FBA,
 569   REG_0FC7,
 570   REG_VEX_71,
 571   REG_VEX_72,
 572   REG_VEX_73,
 573   REG_VEX_AE,
 574   REG_XOP_LWPCB,
 575   REG_XOP_LWP
 576 };
 577
 578 enum
 579 {
 580   MOD_8D = 0,
 581   MOD_0F01_REG_0,
 582   MOD_0F01_REG_1,
 583   MOD_0F01_REG_2,
 584   MOD_0F01_REG_3,
 585   MOD_0F01_REG_7,
 586   MOD_0F12_PREFIX_0,
 587   MOD_0F13,
 588   MOD_0F16_PREFIX_0,
 589   MOD_0F17,
 590   MOD_0F18_REG_0,
 591   MOD_0F18_REG_1,
 592   MOD_0F18_REG_2,
 593   MOD_0F18_REG_3,
 594   MOD_0F20,
 595   MOD_0F21,
 596   MOD_0F22,
 597   MOD_0F23,
 598   MOD_0F24,
 599   MOD_0F26,
 600   MOD_0F2B_PREFIX_0,
 601   MOD_0F2B_PREFIX_1,
 602   MOD_0F2B_PREFIX_2,
 603   MOD_0F2B_PREFIX_3,
 604   MOD_0F51,
 605   MOD_0F71_REG_2,
 606   MOD_0F71_REG_4,
 607   MOD_0F71_REG_6,
 608   MOD_0F72_REG_2,
 609   MOD_0F72_REG_4,
 610   MOD_0F72_REG_6,
 611   MOD_0F73_REG_2,
 612   MOD_0F73_REG_3,
 613   MOD_0F73_REG_6,
 614   MOD_0F73_REG_7,
 615   MOD_0FAE_REG_0,
 616   MOD_0FAE_REG_1,
 617   MOD_0FAE_REG_2,
 618   MOD_0FAE_REG_3,
 619   MOD_0FAE_REG_4,
 620   MOD_0FAE_REG_5,
 621   MOD_0FAE_REG_6,
 622   MOD_0FAE_REG_7,
 623   MOD_0FB2,
 624   MOD_0FB4,
 625   MOD_0FB5,
 626   MOD_0FC7_REG_6,
 627   MOD_0FC7_REG_7,
 628   MOD_0FD7,
 629   MOD_0FE7_PREFIX_2,
 630   MOD_0FF0_PREFIX_3,
 631   MOD_0F382A_PREFIX_2,
 632   MOD_62_32BIT,
 633   MOD_C4_32BIT,
 634   MOD_C5_32BIT,
 635   MOD_VEX_12_PREFIX_0,
 636   MOD_VEX_13,
 637   MOD_VEX_16_PREFIX_0,
 638   MOD_VEX_17,
 639   MOD_VEX_2B,
 640   MOD_VEX_51,
 641   MOD_VEX_71_REG_2,
 642   MOD_VEX_71_REG_4,
 643   MOD_VEX_71_REG_6,
 644   MOD_VEX_72_REG_2,
 645   MOD_VEX_72_REG_4,
 646   MOD_VEX_72_REG_6,
 647   MOD_VEX_73_REG_2,
 648   MOD_VEX_73_REG_3,
 649   MOD_VEX_73_REG_6,
 650   MOD_VEX_73_REG_7,
 651   MOD_VEX_AE_REG_2,
 652   MOD_VEX_AE_REG_3,
 653   MOD_VEX_D7_PREFIX_2,
 654   MOD_VEX_E7_PREFIX_2,
 655   MOD_VEX_F0_PREFIX_3,
 656   MOD_VEX_3818_PREFIX_2,
 657   MOD_VEX_3819_PREFIX_2,
 658   MOD_VEX_381A_PREFIX_2,
 659   MOD_VEX_382A_PREFIX_2,
 660   MOD_VEX_382C_PREFIX_2,
 661   MOD_VEX_382D_PREFIX_2,
 662   MOD_VEX_382E_PREFIX_2,
 663   MOD_VEX_382F_PREFIX_2
 664 };
 665
 666 enum
 667 {
 668   RM_0F01_REG_0 = 0,
 669   RM_0F01_REG_1,
 670   RM_0F01_REG_2,
 671   RM_0F01_REG_3,
 672   RM_0F01_REG_7,
 673   RM_0FAE_REG_5,
 674   RM_0FAE_REG_6,
 675   RM_0FAE_REG_7
 676 };
 677
 678 enum
 679 {
 680   PREFIX_90 = 0,
 681   PREFIX_0F10,
 682   PREFIX_0F11,
 683   PREFIX_0F12,
 684   PREFIX_0F16,
 685   PREFIX_0F2A,
 686   PREFIX_0F2B,
 687   PREFIX_0F2C,
 688   PREFIX_0F2D,
 689   PREFIX_0F2E,
 690   PREFIX_0F2F,
 691   PREFIX_0F51,
 692   PREFIX_0F52,
 693   PREFIX_0F53,
 694   PREFIX_0F58,
 695   PREFIX_0F59,
 696   PREFIX_0F5A,
 697   PREFIX_0F5B,
 698   PREFIX_0F5C,
 699   PREFIX_0F5D,
 700   PREFIX_0F5E,
 701   PREFIX_0F5F,
 702   PREFIX_0F60,
 703   PREFIX_0F61,
 704   PREFIX_0F62,
 705   PREFIX_0F6C,
 706   PREFIX_0F6D,
 707   PREFIX_0F6F,
 708   PREFIX_0F70,
 709   PREFIX_0F73_REG_3,
 710   PREFIX_0F73_REG_7,
 711   PREFIX_0F78,
 712   PREFIX_0F79,
 713   PREFIX_0F7C,
 714   PREFIX_0F7D,
 715   PREFIX_0F7E,
 716   PREFIX_0F7F,
 717   PREFIX_0FB8,
 718   PREFIX_0FBD,
 719   PREFIX_0FC2,
 720   PREFIX_0FC3,
 721   PREFIX_0FC7_REG_6,
 722   PREFIX_0FD0,
 723   PREFIX_0FD6,
 724   PREFIX_0FE6,
 725   PREFIX_0FE7,
 726   PREFIX_0FF0,
 727   PREFIX_0FF7,
 728   PREFIX_0F3810,
 729   PREFIX_0F3814,
 730   PREFIX_0F3815,
 731   PREFIX_0F3817,
 732   PREFIX_0F3820,
 733   PREFIX_0F3821,
 734   PREFIX_0F3822,
 735   PREFIX_0F3823,
 736   PREFIX_0F3824,
 737   PREFIX_0F3825,
 738   PREFIX_0F3828,
 739   PREFIX_0F3829,
 740   PREFIX_0F382A,
 741   PREFIX_0F382B,
 742   PREFIX_0F3830,
 743   PREFIX_0F3831,
 744   PREFIX_0F3832,
 745   PREFIX_0F3833,
 746   PREFIX_0F3834,
 747   PREFIX_0F3835,
 748   PREFIX_0F3837,
 749   PREFIX_0F3838,
 750   PREFIX_0F3839,
 751   PREFIX_0F383A,
 752   PREFIX_0F383B,
 753   PREFIX_0F383C,
 754   PREFIX_0F383D,
 755   PREFIX_0F383E,
 756   PREFIX_0F383F,
 757   PREFIX_0F3840,
 758   PREFIX_0F3841,
 759   PREFIX_0F3880,
 760   PREFIX_0F3881,
 761   PREFIX_0F38DB,
 762   PREFIX_0F38DC,
 763   PREFIX_0F38DD,
 764   PREFIX_0F38DE,
 765   PREFIX_0F38DF,
 766   PREFIX_0F38F0,
 767   PREFIX_0F38F1,
 768   PREFIX_0F3A08,
 769   PREFIX_0F3A09,
 770   PREFIX_0F3A0A,
 771   PREFIX_0F3A0B,
 772   PREFIX_0F3A0C,
 773   PREFIX_0F3A0D,
 774   PREFIX_0F3A0E,
 775   PREFIX_0F3A14,
 776   PREFIX_0F3A15,
 777   PREFIX_0F3A16,
 778   PREFIX_0F3A17,
 779   PREFIX_0F3A20,
 780   PREFIX_0F3A21,
 781   PREFIX_0F3A22,
 782   PREFIX_0F3A40,
 783   PREFIX_0F3A41,
 784   PREFIX_0F3A42,
 785   PREFIX_0F3A44,
 786   PREFIX_0F3A60,
 787   PREFIX_0F3A61,
 788   PREFIX_0F3A62,
 789   PREFIX_0F3A63,
 790   PREFIX_0F3ADF,
 791   PREFIX_VEX_10,
 792   PREFIX_VEX_11,
 793   PREFIX_VEX_12,
 794   PREFIX_VEX_16,
 795   PREFIX_VEX_2A,
 796   PREFIX_VEX_2C,
 797   PREFIX_VEX_2D,
 798   PREFIX_VEX_2E,
 799   PREFIX_VEX_2F,
 800   PREFIX_VEX_51,
 801   PREFIX_VEX_52,
 802   PREFIX_VEX_53,
 803   PREFIX_VEX_58,
 804   PREFIX_VEX_59,
 805   PREFIX_VEX_5A,
 806   PREFIX_VEX_5B,
 807   PREFIX_VEX_5C,
 808   PREFIX_VEX_5D,
 809   PREFIX_VEX_5E,
 810   PREFIX_VEX_5F,
 811   PREFIX_VEX_60,
 812   PREFIX_VEX_61,
 813   PREFIX_VEX_62,
 814   PREFIX_VEX_63,
 815   PREFIX_VEX_64,
 816   PREFIX_VEX_65,
 817   PREFIX_VEX_66,
 818   PREFIX_VEX_67,
 819   PREFIX_VEX_68,
 820   PREFIX_VEX_69,
 821   PREFIX_VEX_6A,
 822   PREFIX_VEX_6B,
 823   PREFIX_VEX_6C,
 824   PREFIX_VEX_6D,
 825   PREFIX_VEX_6E,
 826   PREFIX_VEX_6F,
 827   PREFIX_VEX_70,
 828   PREFIX_VEX_71_REG_2,
 829   PREFIX_VEX_71_REG_4,
 830   PREFIX_VEX_71_REG_6,
 831   PREFIX_VEX_72_REG_2,
 832   PREFIX_VEX_72_REG_4,
 833   PREFIX_VEX_72_REG_6,
 834   PREFIX_VEX_73_REG_2,
 835   PREFIX_VEX_73_REG_3,
 836   PREFIX_VEX_73_REG_6,
 837   PREFIX_VEX_73_REG_7,
 838   PREFIX_VEX_74,
 839   PREFIX_VEX_75,
 840   PREFIX_VEX_76,
 841   PREFIX_VEX_77,
 842   PREFIX_VEX_7C,
 843   PREFIX_VEX_7D,
 844   PREFIX_VEX_7E,
 845   PREFIX_VEX_7F,
 846   PREFIX_VEX_C2,
 847   PREFIX_VEX_C4,
 848   PREFIX_VEX_C5,
 849   PREFIX_VEX_D0,
 850   PREFIX_VEX_D1,
 851   PREFIX_VEX_D2,
 852   PREFIX_VEX_D3,
 853   PREFIX_VEX_D4,
 854   PREFIX_VEX_D5,
 855   PREFIX_VEX_D6,
 856   PREFIX_VEX_D7,
 857   PREFIX_VEX_D8,
 858   PREFIX_VEX_D9,
 859   PREFIX_VEX_DA,
 860   PREFIX_VEX_DB,
 861   PREFIX_VEX_DC,
 862   PREFIX_VEX_DD,
 863   PREFIX_VEX_DE,
 864   PREFIX_VEX_DF,
 865   PREFIX_VEX_E0,
 866   PREFIX_VEX_E1,
 867   PREFIX_VEX_E2,
 868   PREFIX_VEX_E3,
 869   PREFIX_VEX_E4,
 870   PREFIX_VEX_E5,
 871   PREFIX_VEX_E6,
 872   PREFIX_VEX_E7,
 873   PREFIX_VEX_E8,
 874   PREFIX_VEX_E9,
 875   PREFIX_VEX_EA,
 876   PREFIX_VEX_EB,
 877   PREFIX_VEX_EC,
 878   PREFIX_VEX_ED,
 879   PREFIX_VEX_EE,
 880   PREFIX_VEX_EF,
 881   PREFIX_VEX_F0,
 882   PREFIX_VEX_F1,
 883   PREFIX_VEX_F2,
 884   PREFIX_VEX_F3,
 885   PREFIX_VEX_F4,
 886   PREFIX_VEX_F5,
 887   PREFIX_VEX_F6,
 888   PREFIX_VEX_F7,
 889   PREFIX_VEX_F8,
 890   PREFIX_VEX_F9,
 891   PREFIX_VEX_FA,
 892   PREFIX_VEX_FB,
 893   PREFIX_VEX_FC,
 894   PREFIX_VEX_FD,
 895   PREFIX_VEX_FE,
 896   PREFIX_VEX_3800,
 897   PREFIX_VEX_3801,
 898   PREFIX_VEX_3802,
 899   PREFIX_VEX_3803,
 900   PREFIX_VEX_3804,
 901   PREFIX_VEX_3805,
 902   PREFIX_VEX_3806,
 903   PREFIX_VEX_3807,
 904   PREFIX_VEX_3808,
 905   PREFIX_VEX_3809,
 906   PREFIX_VEX_380A,
 907   PREFIX_VEX_380B,
 908   PREFIX_VEX_380C,
 909   PREFIX_VEX_380D,
 910   PREFIX_VEX_380E,
 911   PREFIX_VEX_380F,
 912   PREFIX_VEX_3817,
 913   PREFIX_VEX_3818,
 914   PREFIX_VEX_3819,
 915   PREFIX_VEX_381A,
 916   PREFIX_VEX_381C,
 917   PREFIX_VEX_381D,
 918   PREFIX_VEX_381E,
 919   PREFIX_VEX_3820,
 920   PREFIX_VEX_3821,
 921   PREFIX_VEX_3822,
 922   PREFIX_VEX_3823,
 923   PREFIX_VEX_3824,
 924   PREFIX_VEX_3825,
 925   PREFIX_VEX_3828,
 926   PREFIX_VEX_3829,
 927   PREFIX_VEX_382A,
 928   PREFIX_VEX_382B,
 929   PREFIX_VEX_382C,
 930   PREFIX_VEX_382D,
 931   PREFIX_VEX_382E,
 932   PREFIX_VEX_382F,
 933   PREFIX_VEX_3830,
 934   PREFIX_VEX_3831,
 935   PREFIX_VEX_3832,
 936   PREFIX_VEX_3833,
 937   PREFIX_VEX_3834,
 938   PREFIX_VEX_3835,
 939   PREFIX_VEX_3837,
 940   PREFIX_VEX_3838,
 941   PREFIX_VEX_3839,
 942   PREFIX_VEX_383A,
 943   PREFIX_VEX_383B,
 944   PREFIX_VEX_383C,
 945   PREFIX_VEX_383D,
 946   PREFIX_VEX_383E,
 947   PREFIX_VEX_383F,
 948   PREFIX_VEX_3840,
 949   PREFIX_VEX_3841,
 950   PREFIX_VEX_3896,
 951   PREFIX_VEX_3897,
 952   PREFIX_VEX_3898,
 953   PREFIX_VEX_3899,
 954   PREFIX_VEX_389A,
 955   PREFIX_VEX_389B,
 956   PREFIX_VEX_389C,
 957   PREFIX_VEX_389D,
 958   PREFIX_VEX_389E,
 959   PREFIX_VEX_389F,
 960   PREFIX_VEX_38A6,
 961   PREFIX_VEX_38A7,
 962   PREFIX_VEX_38A8,
 963   PREFIX_VEX_38A9,
 964   PREFIX_VEX_38AA,
 965   PREFIX_VEX_38AB,
 966   PREFIX_VEX_38AC,
 967   PREFIX_VEX_38AD,
 968   PREFIX_VEX_38AE,
 969   PREFIX_VEX_38AF,
 970   PREFIX_VEX_38B6,
 971   PREFIX_VEX_38B7,
 972   PREFIX_VEX_38B8,
 973   PREFIX_VEX_38B9,
 974   PREFIX_VEX_38BA,
 975   PREFIX_VEX_38BB,
 976   PREFIX_VEX_38BC,
 977   PREFIX_VEX_38BD,
 978   PREFIX_VEX_38BE,
 979   PREFIX_VEX_38BF,
 980   PREFIX_VEX_38DB,
 981   PREFIX_VEX_38DC,
 982   PREFIX_VEX_38DD,
 983   PREFIX_VEX_38DE,
 984   PREFIX_VEX_38DF,
 985   PREFIX_VEX_3A04,
 986   PREFIX_VEX_3A05,
 987   PREFIX_VEX_3A06,
 988   PREFIX_VEX_3A08,
 989   PREFIX_VEX_3A09,
 990   PREFIX_VEX_3A0A,
 991   PREFIX_VEX_3A0B,
 992   PREFIX_VEX_3A0C,
 993   PREFIX_VEX_3A0D,
 994   PREFIX_VEX_3A0E,
 995   PREFIX_VEX_3A0F,
 996   PREFIX_VEX_3A14,
 997   PREFIX_VEX_3A15,
 998   PREFIX_VEX_3A16,
 999   PREFIX_VEX_3A17,
1000   PREFIX_VEX_3A18,
1001   PREFIX_VEX_3A19,
1002   PREFIX_VEX_3A20,
1003   PREFIX_VEX_3A21,
1004   PREFIX_VEX_3A22,
1005   PREFIX_VEX_3A40,
1006   PREFIX_VEX_3A41,
1007   PREFIX_VEX_3A42,
1008   PREFIX_VEX_3A44,
1009   PREFIX_VEX_3A4A,
1010   PREFIX_VEX_3A4B,
1011   PREFIX_VEX_3A4C,
1012   PREFIX_VEX_3A5C,
1013   PREFIX_VEX_3A5D,
1014   PREFIX_VEX_3A5E,
1015   PREFIX_VEX_3A5F,
1016   PREFIX_VEX_3A60,
1017   PREFIX_VEX_3A61,
1018   PREFIX_VEX_3A62,
1019   PREFIX_VEX_3A63,
1020   PREFIX_VEX_3A68,
1021   PREFIX_VEX_3A69,
1022   PREFIX_VEX_3A6A,
1023   PREFIX_VEX_3A6B,
1024   PREFIX_VEX_3A6C,
1025   PREFIX_VEX_3A6D,
1026   PREFIX_VEX_3A6E,
1027   PREFIX_VEX_3A6F,
1028   PREFIX_VEX_3A78,
1029   PREFIX_VEX_3A79,
1030   PREFIX_VEX_3A7A,
1031   PREFIX_VEX_3A7B,
1032   PREFIX_VEX_3A7C,
1033   PREFIX_VEX_3A7D,
1034   PREFIX_VEX_3A7E,
1035   PREFIX_VEX_3A7F,
1036   PREFIX_VEX_3ADF
1037 };
1038
1039 enum
1040 {
1041   X86_64_06 = 0,
1042   X86_64_07,
1043   X86_64_0D,
1044   X86_64_16,
1045   X86_64_17,
1046   X86_64_1E,
1047   X86_64_1F,
1048   X86_64_27,
1049   X86_64_2F,
1050   X86_64_37,
1051   X86_64_3F,
1052   X86_64_60,
1053   X86_64_61,
1054   X86_64_62,
1055   X86_64_63,
1056   X86_64_6D,
1057   X86_64_6F,
1058   X86_64_9A,
1059   X86_64_C4,
1060   X86_64_C5,
1061   X86_64_CE,
1062   X86_64_D4,
1063   X86_64_D5,
1064   X86_64_EA,
1065   X86_64_0F01_REG_0,
1066   X86_64_0F01_REG_1,
1067   X86_64_0F01_REG_2,
1068   X86_64_0F01_REG_3
1069 };
1070
1071 enum
1072 {
1073   THREE_BYTE_0F38 = 0,
1074   THREE_BYTE_0F3A,
1075   THREE_BYTE_0F7A
1076 };
1077
1078 enum
1079 {
1080   XOP_08 = 0,
1081   XOP_09,
1082   XOP_0A
1083 };
1084
1085 enum
1086 {
1087   VEX_0F = 0,
1088   VEX_0F38,
1089   VEX_0F3A
1090 };
1091
1092 enum
1093 {
1094   VEX_LEN_10_P_1 = 0,
1095   VEX_LEN_10_P_3,
1096   VEX_LEN_11_P_1,
1097   VEX_LEN_11_P_3,
1098   VEX_LEN_12_P_0_M_0,
1099   VEX_LEN_12_P_0_M_1,
1100   VEX_LEN_12_P_2,
1101   VEX_LEN_13_M_0,
1102   VEX_LEN_16_P_0_M_0,
1103   VEX_LEN_16_P_0_M_1,
1104   VEX_LEN_16_P_2,
1105   VEX_LEN_17_M_0,
1106   VEX_LEN_2A_P_1,
1107   VEX_LEN_2A_P_3,
1108   VEX_LEN_2C_P_1,
1109   VEX_LEN_2C_P_3,
1110   VEX_LEN_2D_P_1,
1111   VEX_LEN_2D_P_3,
1112   VEX_LEN_2E_P_0,
1113   VEX_LEN_2E_P_2,
1114   VEX_LEN_2F_P_0,
1115   VEX_LEN_2F_P_2,
1116   VEX_LEN_51_P_1,
1117   VEX_LEN_51_P_3,
1118   VEX_LEN_52_P_1,
1119   VEX_LEN_53_P_1,
1120   VEX_LEN_58_P_1,
1121   VEX_LEN_58_P_3,
1122   VEX_LEN_59_P_1,
1123   VEX_LEN_59_P_3,
1124   VEX_LEN_5A_P_1,
1125   VEX_LEN_5A_P_3,
1126   VEX_LEN_5C_P_1,
1127   VEX_LEN_5C_P_3,
1128   VEX_LEN_5D_P_1,
1129   VEX_LEN_5D_P_3,
1130   VEX_LEN_5E_P_1,
1131   VEX_LEN_5E_P_3,
1132   VEX_LEN_5F_P_1,
1133   VEX_LEN_5F_P_3,
1134   VEX_LEN_60_P_2,
1135   VEX_LEN_61_P_2,
1136   VEX_LEN_62_P_2,
1137   VEX_LEN_63_P_2,
1138   VEX_LEN_64_P_2,
1139   VEX_LEN_65_P_2,
1140   VEX_LEN_66_P_2,
1141   VEX_LEN_67_P_2,
1142   VEX_LEN_68_P_2,
1143   VEX_LEN_69_P_2,
1144   VEX_LEN_6A_P_2,
1145   VEX_LEN_6B_P_2,
1146   VEX_LEN_6C_P_2,
1147   VEX_LEN_6D_P_2,
1148   VEX_LEN_6E_P_2,
1149   VEX_LEN_70_P_1,
1150   VEX_LEN_70_P_2,
1151   VEX_LEN_70_P_3,
1152   VEX_LEN_71_R_2_P_2,
1153   VEX_LEN_71_R_4_P_2,
1154   VEX_LEN_71_R_6_P_2,
1155   VEX_LEN_72_R_2_P_2,
1156   VEX_LEN_72_R_4_P_2,
1157   VEX_LEN_72_R_6_P_2,
1158   VEX_LEN_73_R_2_P_2,
1159   VEX_LEN_73_R_3_P_2,
1160   VEX_LEN_73_R_6_P_2,
1161   VEX_LEN_73_R_7_P_2,
1162   VEX_LEN_74_P_2,
1163   VEX_LEN_75_P_2,
1164   VEX_LEN_76_P_2,
1165   VEX_LEN_7E_P_1,
1166   VEX_LEN_7E_P_2,
1167   VEX_LEN_AE_R_2_M_0,
1168   VEX_LEN_AE_R_3_M_0,
1169   VEX_LEN_C2_P_1,
1170   VEX_LEN_C2_P_3,
1171   VEX_LEN_C4_P_2,
1172   VEX_LEN_C5_P_2,
1173   VEX_LEN_D1_P_2,
1174   VEX_LEN_D2_P_2,
1175   VEX_LEN_D3_P_2,
1176   VEX_LEN_D4_P_2,
1177   VEX_LEN_D5_P_2,
1178   VEX_LEN_D6_P_2,
1179   VEX_LEN_D7_P_2_M_1,
1180   VEX_LEN_D8_P_2,
1181   VEX_LEN_D9_P_2,
1182   VEX_LEN_DA_P_2,
1183   VEX_LEN_DB_P_2,
1184   VEX_LEN_DC_P_2,
1185   VEX_LEN_DD_P_2,
1186   VEX_LEN_DE_P_2,
1187   VEX_LEN_DF_P_2,
1188   VEX_LEN_E0_P_2,
1189   VEX_LEN_E1_P_2,
1190   VEX_LEN_E2_P_2,
1191   VEX_LEN_E3_P_2,
1192   VEX_LEN_E4_P_2,
1193   VEX_LEN_E5_P_2,
1194   VEX_LEN_E8_P_2,
1195   VEX_LEN_E9_P_2,
1196   VEX_LEN_EA_P_2,
1197   VEX_LEN_EB_P_2,
1198   VEX_LEN_EC_P_2,
1199   VEX_LEN_ED_P_2,
1200   VEX_LEN_EE_P_2,
1201   VEX_LEN_EF_P_2,
1202   VEX_LEN_F1_P_2,
1203   VEX_LEN_F2_P_2,
1204   VEX_LEN_F3_P_2,
1205   VEX_LEN_F4_P_2,
1206   VEX_LEN_F5_P_2,
1207   VEX_LEN_F6_P_2,
1208   VEX_LEN_F7_P_2,
1209   VEX_LEN_F8_P_2,
1210   VEX_LEN_F9_P_2,
1211   VEX_LEN_FA_P_2,
1212   VEX_LEN_FB_P_2,
1213   VEX_LEN_FC_P_2,
1214   VEX_LEN_FD_P_2,
1215   VEX_LEN_FE_P_2,
1216   VEX_LEN_3800_P_2,
1217   VEX_LEN_3801_P_2,
1218   VEX_LEN_3802_P_2,
1219   VEX_LEN_3803_P_2,
1220   VEX_LEN_3804_P_2,
1221   VEX_LEN_3805_P_2,
1222   VEX_LEN_3806_P_2,
1223   VEX_LEN_3807_P_2,
1224   VEX_LEN_3808_P_2,
1225   VEX_LEN_3809_P_2,
1226   VEX_LEN_380A_P_2,
1227   VEX_LEN_380B_P_2,
1228   VEX_LEN_3819_P_2_M_0,
1229   VEX_LEN_381A_P_2_M_0,
1230   VEX_LEN_381C_P_2,
1231   VEX_LEN_381D_P_2,
1232   VEX_LEN_381E_P_2,
1233   VEX_LEN_3820_P_2,
1234   VEX_LEN_3821_P_2,
1235   VEX_LEN_3822_P_2,
1236   VEX_LEN_3823_P_2,
1237   VEX_LEN_3824_P_2,
1238   VEX_LEN_3825_P_2,
1239   VEX_LEN_3828_P_2,
1240   VEX_LEN_3829_P_2,
1241   VEX_LEN_382A_P_2_M_0,
1242   VEX_LEN_382B_P_2,
1243   VEX_LEN_3830_P_2,
1244   VEX_LEN_3831_P_2,
1245   VEX_LEN_3832_P_2,
1246   VEX_LEN_3833_P_2,
1247   VEX_LEN_3834_P_2,
1248   VEX_LEN_3835_P_2,
1249   VEX_LEN_3837_P_2,
1250   VEX_LEN_3838_P_2,
1251   VEX_LEN_3839_P_2,
1252   VEX_LEN_383A_P_2,
1253   VEX_LEN_383B_P_2,
1254   VEX_LEN_383C_P_2,
1255   VEX_LEN_383D_P_2,
1256   VEX_LEN_383E_P_2,
1257   VEX_LEN_383F_P_2,
1258   VEX_LEN_3840_P_2,
1259   VEX_LEN_3841_P_2,
1260   VEX_LEN_38DB_P_2,
1261   VEX_LEN_38DC_P_2,
1262   VEX_LEN_38DD_P_2,
1263   VEX_LEN_38DE_P_2,
1264   VEX_LEN_38DF_P_2,
1265   VEX_LEN_3A06_P_2,
1266   VEX_LEN_3A0A_P_2,
1267   VEX_LEN_3A0B_P_2,
1268   VEX_LEN_3A0E_P_2,
1269   VEX_LEN_3A0F_P_2,
1270   VEX_LEN_3A14_P_2,
1271   VEX_LEN_3A15_P_2,
1272   VEX_LEN_3A16_P_2,
1273   VEX_LEN_3A17_P_2,
1274   VEX_LEN_3A18_P_2,
1275   VEX_LEN_3A19_P_2,
1276   VEX_LEN_3A20_P_2,
1277   VEX_LEN_3A21_P_2,
1278   VEX_LEN_3A22_P_2,
1279   VEX_LEN_3A41_P_2,
1280   VEX_LEN_3A42_P_2,
1281   VEX_LEN_3A44_P_2,
1282   VEX_LEN_3A4C_P_2,
1283   VEX_LEN_3A60_P_2,
1284   VEX_LEN_3A61_P_2,
1285   VEX_LEN_3A62_P_2,
1286   VEX_LEN_3A63_P_2,
1287   VEX_LEN_3A6A_P_2,
1288   VEX_LEN_3A6B_P_2,
1289   VEX_LEN_3A6E_P_2,
1290   VEX_LEN_3A6F_P_2,
1291   VEX_LEN_3A7A_P_2,
1292   VEX_LEN_3A7B_P_2,
1293   VEX_LEN_3A7E_P_2,
1294   VEX_LEN_3A7F_P_2,
1295   VEX_LEN_3ADF_P_2,
1296   VEX_LEN_XOP_09_80,
1297   VEX_LEN_XOP_09_81
1298 };
1299
1300 typedef void (*op_rtn) (int bytemode, int sizeflag);
1301
1302 struct dis386 {
1303   const char *name;
1304   struct
1305     {
1306       op_rtn rtn;
1307       int bytemode;
1308     } op[MAX_OPERANDS];
1309 };
1310
1311 /* Upper case letters in the instruction names here are macros.
1312    'A' => print 'b' if no register operands or suffix_always is true
1313    'B' => print 'b' if suffix_always is true
1314    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1315           size prefix
1316    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1317           suffix_always is true
1318    'E' => print 'e' if 32-bit form of jcxz
1319    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1320    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1321    'H' => print ",pt" or ",pn" branch hint
1322    'I' => honor following macro letter even in Intel mode (implemented only
1323           for some of the macro letters)
1324    'J' => print 'l'
1325    'K' => print 'd' or 'q' if rex prefix is present.
1326    'L' => print 'l' if suffix_always is true
1327    'M' => print 'r' if intel_mnemonic is false.
1328    'N' => print 'n' if instruction has no wait "prefix"
1329    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1330    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1331           or suffix_always is true.  print 'q' if rex prefix is present.
1332    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1333           is true
1334    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1335    'S' => print 'w', 'l' or 'q' if suffix_always is true
1336    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1337    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1338    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1339    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1340    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1341    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1342           suffix_always is true.
1343    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1344    '!' => change condition from true to false or from false to true.
1345    '%' => add 1 upper case letter to the macro.
1346
1347    2 upper case letter macros:
1348    "XY" => print 'x' or 'y' if no register operands or suffix_always
1349            is true.
1350    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1351    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1352            or suffix_always is true
1353    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1354    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1355    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1356
1357    Many of the above letters print nothing in Intel mode.  See "putop"
1358    for the details.
1359
1360    Braces '{' and '}', and vertical bars '|', indicate alternative
1361    mnemonic strings for AT&T and Intel.  */
1362
1363 static const struct dis386 dis386[] = {
1364   /* 00 */
1365   { "addB",             { Eb, Gb } },
1366   { "addS",             { Ev, Gv } },
1367   { "addB",             { Gb, EbS } },
1368   { "addS",             { Gv, EvS } },
1369   { "addB",             { AL, Ib } },
1370   { "addS",             { eAX, Iv } },
1371   { X86_64_TABLE (X86_64_06) },
1372   { X86_64_TABLE (X86_64_07) },
1373   /* 08 */
1374   { "orB",              { Eb, Gb } },
1375   { "orS",              { Ev, Gv } },
1376   { "orB",              { Gb, EbS } },
1377   { "orS",              { Gv, EvS } },
1378   { "orB",              { AL, Ib } },
1379   { "orS",              { eAX, Iv } },
1380   { X86_64_TABLE (X86_64_0D) },
1381   { "(bad)",            { XX } },       /* 0x0f extended opcode escape */
1382   /* 10 */
1383   { "adcB",             { Eb, Gb } },
1384   { "adcS",             { Ev, Gv } },
1385   { "adcB",             { Gb, EbS } },
1386   { "adcS",             { Gv, EvS } },
1387   { "adcB",             { AL, Ib } },
1388   { "adcS",             { eAX, Iv } },
1389   { X86_64_TABLE (X86_64_16) },
1390   { X86_64_TABLE (X86_64_17) },
1391   /* 18 */
1392   { "sbbB",             { Eb, Gb } },
1393   { "sbbS",             { Ev, Gv } },
1394   { "sbbB",             { Gb, EbS } },
1395   { "sbbS",             { Gv, EvS } },
1396   { "sbbB",             { AL, Ib } },
1397   { "sbbS",             { eAX, Iv } },
1398   { X86_64_TABLE (X86_64_1E) },
1399   { X86_64_TABLE (X86_64_1F) },
1400   /* 20 */
1401   { "andB",             { Eb, Gb } },
1402   { "andS",             { Ev, Gv } },
1403   { "andB",             { Gb, EbS } },
1404   { "andS",             { Gv, EvS } },
1405   { "andB",             { AL, Ib } },
1406   { "andS",             { eAX, Iv } },
1407   { "(bad)",            { XX } },       /* SEG ES prefix */
1408   { X86_64_TABLE (X86_64_27) },
1409   /* 28 */
1410   { "subB",             { Eb, Gb } },
1411   { "subS",             { Ev, Gv } },
1412   { "subB",             { Gb, EbS } },
1413   { "subS",             { Gv, EvS } },
1414   { "subB",             { AL, Ib } },
1415   { "subS",             { eAX, Iv } },
1416   { "(bad)",            { XX } },       /* SEG CS prefix */
1417   { X86_64_TABLE (X86_64_2F) },
1418   /* 30 */
1419   { "xorB",             { Eb, Gb } },
1420   { "xorS",             { Ev, Gv } },
1421   { "xorB",             { Gb, EbS } },
1422   { "xorS",             { Gv, EvS } },
1423   { "xorB",             { AL, Ib } },
1424   { "xorS",             { eAX, Iv } },
1425   { "(bad)",            { XX } },       /* SEG SS prefix */
1426   { X86_64_TABLE (X86_64_37) },
1427   /* 38 */
1428   { "cmpB",             { Eb, Gb } },
1429   { "cmpS",             { Ev, Gv } },
1430   { "cmpB",             { Gb, EbS } },
1431   { "cmpS",             { Gv, EvS } },
1432   { "cmpB",             { AL, Ib } },
1433   { "cmpS",             { eAX, Iv } },
1434   { "(bad)",            { XX } },       /* SEG DS prefix */
1435   { X86_64_TABLE (X86_64_3F) },
1436   /* 40 */
1437   { "inc{S|}",          { RMeAX } },
1438   { "inc{S|}",          { RMeCX } },
1439   { "inc{S|}",          { RMeDX } },
1440   { "inc{S|}",          { RMeBX } },
1441   { "inc{S|}",          { RMeSP } },
1442   { "inc{S|}",          { RMeBP } },
1443   { "inc{S|}",          { RMeSI } },
1444   { "inc{S|}",          { RMeDI } },
1445   /* 48 */
1446   { "dec{S|}",          { RMeAX } },
1447   { "dec{S|}",          { RMeCX } },
1448   { "dec{S|}",          { RMeDX } },
1449   { "dec{S|}",          { RMeBX } },
1450   { "dec{S|}",          { RMeSP } },
1451   { "dec{S|}",          { RMeBP } },
1452   { "dec{S|}",          { RMeSI } },
1453   { "dec{S|}",          { RMeDI } },
1454   /* 50 */
1455   { "pushV",            { RMrAX } },
1456   { "pushV",            { RMrCX } },
1457   { "pushV",            { RMrDX } },
1458   { "pushV",            { RMrBX } },
1459   { "pushV",            { RMrSP } },
1460   { "pushV",            { RMrBP } },
1461   { "pushV",            { RMrSI } },
1462   { "pushV",            { RMrDI } },
1463   /* 58 */
1464   { "popV",             { RMrAX } },
1465   { "popV",             { RMrCX } },
1466   { "popV",             { RMrDX } },
1467   { "popV",             { RMrBX } },
1468   { "popV",             { RMrSP } },
1469   { "popV",             { RMrBP } },
1470   { "popV",             { RMrSI } },
1471   { "popV",             { RMrDI } },
1472   /* 60 */
1473   { X86_64_TABLE (X86_64_60) },
1474   { X86_64_TABLE (X86_64_61) },
1475   { X86_64_TABLE (X86_64_62) },
1476   { X86_64_TABLE (X86_64_63) },
1477   { "(bad)",            { XX } },       /* seg fs */
1478   { "(bad)",            { XX } },       /* seg gs */
1479   { "(bad)",            { XX } },       /* op size prefix */
1480   { "(bad)",            { XX } },       /* adr size prefix */
1481   /* 68 */
1482   { "pushT",            { Iq } },
1483   { "imulS",            { Gv, Ev, Iv } },
1484   { "pushT",            { sIb } },
1485   { "imulS",            { Gv, Ev, sIb } },
1486   { "ins{b|}",          { Ybr, indirDX } },
1487   { X86_64_TABLE (X86_64_6D) },
1488   { "outs{b|}",         { indirDXr, Xb } },
1489   { X86_64_TABLE (X86_64_6F) },
1490   /* 70 */
1491   { "joH",              { Jb, XX, cond_jump_flag } },
1492   { "jnoH",             { Jb, XX, cond_jump_flag } },
1493   { "jbH",              { Jb, XX, cond_jump_flag } },
1494   { "jaeH",             { Jb, XX, cond_jump_flag } },
1495   { "jeH",              { Jb, XX, cond_jump_flag } },
1496   { "jneH",             { Jb, XX, cond_jump_flag } },
1497   { "jbeH",             { Jb, XX, cond_jump_flag } },
1498   { "jaH",              { Jb, XX, cond_jump_flag } },
1499   /* 78 */
1500   { "jsH",              { Jb, XX, cond_jump_flag } },
1501   { "jnsH",             { Jb, XX, cond_jump_flag } },
1502   { "jpH",              { Jb, XX, cond_jump_flag } },
1503   { "jnpH",             { Jb, XX, cond_jump_flag } },
1504   { "jlH",              { Jb, XX, cond_jump_flag } },
1505   { "jgeH",             { Jb, XX, cond_jump_flag } },
1506   { "jleH",             { Jb, XX, cond_jump_flag } },
1507   { "jgH",              { Jb, XX, cond_jump_flag } },
1508   /* 80 */
1509   { REG_TABLE (REG_80) },
1510   { REG_TABLE (REG_81) },
1511   { "(bad)",            { XX } },
1512   { REG_TABLE (REG_82) },
1513   { "testB",            { Eb, Gb } },
1514   { "testS",            { Ev, Gv } },
1515   { "xchgB",            { Eb, Gb } },
1516   { "xchgS",            { Ev, Gv } },
1517   /* 88 */
1518   { "movB",             { Eb, Gb } },
1519   { "movS",             { Ev, Gv } },
1520   { "movB",             { Gb, EbS } },
1521   { "movS",             { Gv, EvS } },
1522   { "movD",             { Sv, Sw } },
1523   { MOD_TABLE (MOD_8D) },
1524   { "movD",             { Sw, Sv } },
1525   { REG_TABLE (REG_8F) },
1526   /* 90 */
1527   { PREFIX_TABLE (PREFIX_90) },
1528   { "xchgS",            { RMeCX, eAX } },
1529   { "xchgS",            { RMeDX, eAX } },
1530   { "xchgS",            { RMeBX, eAX } },
1531   { "xchgS",            { RMeSP, eAX } },
1532   { "xchgS",            { RMeBP, eAX } },
1533   { "xchgS",            { RMeSI, eAX } },
1534   { "xchgS",            { RMeDI, eAX } },
1535   /* 98 */
1536   { "cW{t|}R",          { XX } },
1537   { "cR{t|}O",          { XX } },
1538   { X86_64_TABLE (X86_64_9A) },
1539   { "(bad)",            { XX } },       /* fwait */
1540   { "pushfT",           { XX } },
1541   { "popfT",            { XX } },
1542   { "sahf",             { XX } },
1543   { "lahf",             { XX } },
1544   /* a0 */
1545   { "mov%LB",           { AL, Ob } },
1546   { "mov%LS",           { eAX, Ov } },
1547   { "mov%LB",           { Ob, AL } },
1548   { "mov%LS",           { Ov, eAX } },
1549   { "movs{b|}",         { Ybr, Xb } },
1550   { "movs{R|}",         { Yvr, Xv } },
1551   { "cmps{b|}",         { Xb, Yb } },
1552   { "cmps{R|}",         { Xv, Yv } },
1553   /* a8 */
1554   { "testB",            { AL, Ib } },
1555   { "testS",            { eAX, Iv } },
1556   { "stosB",            { Ybr, AL } },
1557   { "stosS",            { Yvr, eAX } },
1558   { "lodsB",            { ALr, Xb } },
1559   { "lodsS",            { eAXr, Xv } },
1560   { "scasB",            { AL, Yb } },
1561   { "scasS",            { eAX, Yv } },
1562   /* b0 */
1563   { "movB",             { RMAL, Ib } },
1564   { "movB",             { RMCL, Ib } },
1565   { "movB",             { RMDL, Ib } },
1566   { "movB",             { RMBL, Ib } },
1567   { "movB",             { RMAH, Ib } },
1568   { "movB",             { RMCH, Ib } },
1569   { "movB",             { RMDH, Ib } },
1570   { "movB",             { RMBH, Ib } },
1571   /* b8 */
1572   { "mov%LV",           { RMeAX, Iv64 } },
1573   { "mov%LV",           { RMeCX, Iv64 } },
1574   { "mov%LV",           { RMeDX, Iv64 } },
1575   { "mov%LV",           { RMeBX, Iv64 } },
1576   { "mov%LV",           { RMeSP, Iv64 } },
1577   { "mov%LV",           { RMeBP, Iv64 } },
1578   { "mov%LV",           { RMeSI, Iv64 } },
1579   { "mov%LV",           { RMeDI, Iv64 } },
1580   /* c0 */
1581   { REG_TABLE (REG_C0) },
1582   { REG_TABLE (REG_C1) },
1583   { "retT",             { Iw } },
1584   { "retT",             { XX } },
1585   { X86_64_TABLE (X86_64_C4) },
1586   { X86_64_TABLE (X86_64_C5) },
1587   { REG_TABLE (REG_C6) },
1588   { REG_TABLE (REG_C7) },
1589   /* c8 */
1590   { "enterT",           { Iw, Ib } },
1591   { "leaveT",           { XX } },
1592   { "Jret{|f}P",        { Iw } },
1593   { "Jret{|f}P",        { XX } },
1594   { "int3",             { XX } },
1595   { "int",              { Ib } },
1596   { X86_64_TABLE (X86_64_CE) },
1597   { "iretP",            { XX } },
1598   /* d0 */
1599   { REG_TABLE (REG_D0) },
1600   { REG_TABLE (REG_D1) },
1601   { REG_TABLE (REG_D2) },
1602   { REG_TABLE (REG_D3) },
1603   { X86_64_TABLE (X86_64_D4) },
1604   { X86_64_TABLE (X86_64_D5) },
1605   { "(bad)",            { XX } },
1606   { "xlat",             { DSBX } },
1607   /* d8 */
1608   { FLOAT },
1609   { FLOAT },
1610   { FLOAT },
1611   { FLOAT },
1612   { FLOAT },
1613   { FLOAT },
1614   { FLOAT },
1615   { FLOAT },
1616   /* e0 */
1617   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1618   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1619   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1620   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1621   { "inB",              { AL, Ib } },
1622   { "inG",              { zAX, Ib } },
1623   { "outB",             { Ib, AL } },
1624   { "outG",             { Ib, zAX } },
1625   /* e8 */
1626   { "callT",            { Jv } },
1627   { "jmpT",             { Jv } },
1628   { X86_64_TABLE (X86_64_EA) },
1629   { "jmp",              { Jb } },
1630   { "inB",              { AL, indirDX } },
1631   { "inG",              { zAX, indirDX } },
1632   { "outB",             { indirDX, AL } },
1633   { "outG",             { indirDX, zAX } },
1634   /* f0 */
1635   { "(bad)",            { XX } },       /* lock prefix */
1636   { "icebp",            { XX } },
1637   { "(bad)",            { XX } },       /* repne */
1638   { "(bad)",            { XX } },       /* repz */
1639   { "hlt",              { XX } },
1640   { "cmc",              { XX } },
1641   { REG_TABLE (REG_F6) },
1642   { REG_TABLE (REG_F7) },
1643   /* f8 */
1644   { "clc",              { XX } },
1645   { "stc",              { XX } },
1646   { "cli",              { XX } },
1647   { "sti",              { XX } },
1648   { "cld",              { XX } },
1649   { "std",              { XX } },
1650   { REG_TABLE (REG_FE) },
1651   { REG_TABLE (REG_FF) },
1652 };
1653
1654 static const struct dis386 dis386_twobyte[] = {
1655   /* 00 */
1656   { REG_TABLE (REG_0F00 ) },
1657   { REG_TABLE (REG_0F01 ) },
1658   { "larS",             { Gv, Ew } },
1659   { "lslS",             { Gv, Ew } },
1660   { "(bad)",            { XX } },
1661   { "syscall",          { XX } },
1662   { "clts",             { XX } },
1663   { "sysretP",          { XX } },
1664   /* 08 */
1665   { "invd",             { XX } },
1666   { "wbinvd",           { XX } },
1667   { "(bad)",            { XX } },
1668   { "ud2a",             { XX } },
1669   { "(bad)",            { XX } },
1670   { REG_TABLE (REG_0F0D) },
1671   { "femms",            { XX } },
1672   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1673   /* 10 */
1674   { PREFIX_TABLE (PREFIX_0F10) },
1675   { PREFIX_TABLE (PREFIX_0F11) },
1676   { PREFIX_TABLE (PREFIX_0F12) },
1677   { MOD_TABLE (MOD_0F13) },
1678   { "unpcklpX",         { XM, EXx } },
1679   { "unpckhpX",         { XM, EXx } },
1680   { PREFIX_TABLE (PREFIX_0F16) },
1681   { MOD_TABLE (MOD_0F17) },
1682   /* 18 */
1683   { REG_TABLE (REG_0F18) },
1684   { "nopQ",             { Ev } },
1685   { "nopQ",             { Ev } },
1686   { "nopQ",             { Ev } },
1687   { "nopQ",             { Ev } },
1688   { "nopQ",             { Ev } },
1689   { "nopQ",             { Ev } },
1690   { "nopQ",             { Ev } },
1691   /* 20 */
1692   { MOD_TABLE (MOD_0F20) },
1693   { MOD_TABLE (MOD_0F21) },
1694   { MOD_TABLE (MOD_0F22) },
1695   { MOD_TABLE (MOD_0F23) },
1696   { MOD_TABLE (MOD_0F24) },
1697   { "(bad)",            { XX } },
1698   { MOD_TABLE (MOD_0F26) },
1699   { "(bad)",            { XX } },
1700   /* 28 */
1701   { "movapX",           { XM, EXx } },
1702   { "movapX",           { EXxS, XM } },
1703   { PREFIX_TABLE (PREFIX_0F2A) },
1704   { PREFIX_TABLE (PREFIX_0F2B) },
1705   { PREFIX_TABLE (PREFIX_0F2C) },
1706   { PREFIX_TABLE (PREFIX_0F2D) },
1707   { PREFIX_TABLE (PREFIX_0F2E) },
1708   { PREFIX_TABLE (PREFIX_0F2F) },
1709   /* 30 */
1710   { "wrmsr",            { XX } },
1711   { "rdtsc",            { XX } },
1712   { "rdmsr",            { XX } },
1713   { "rdpmc",            { XX } },
1714   { "sysenter",         { XX } },
1715   { "sysexit",          { XX } },
1716   { "(bad)",            { XX } },
1717   { "getsec",           { XX } },
1718   /* 38 */
1719   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1720   { "(bad)",            { XX } },
1721   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1722   { "(bad)",            { XX } },
1723   { "(bad)",            { XX } },
1724   { "(bad)",            { XX } },
1725   { "(bad)",            { XX } },
1726   { "(bad)",            { XX } },
1727   /* 40 */
1728   { "cmovoS",           { Gv, Ev } },
1729   { "cmovnoS",          { Gv, Ev } },
1730   { "cmovbS",           { Gv, Ev } },
1731   { "cmovaeS",          { Gv, Ev } },
1732   { "cmoveS",           { Gv, Ev } },
1733   { "cmovneS",          { Gv, Ev } },
1734   { "cmovbeS",          { Gv, Ev } },
1735   { "cmovaS",           { Gv, Ev } },
1736   /* 48 */
1737   { "cmovsS",           { Gv, Ev } },
1738   { "cmovnsS",          { Gv, Ev } },
1739   { "cmovpS",           { Gv, Ev } },
1740   { "cmovnpS",          { Gv, Ev } },
1741   { "cmovlS",           { Gv, Ev } },
1742   { "cmovgeS",          { Gv, Ev } },
1743   { "cmovleS",          { Gv, Ev } },
1744   { "cmovgS",           { Gv, Ev } },
1745   /* 50 */
1746   { MOD_TABLE (MOD_0F51) },
1747   { PREFIX_TABLE (PREFIX_0F51) },
1748   { PREFIX_TABLE (PREFIX_0F52) },
1749   { PREFIX_TABLE (PREFIX_0F53) },
1750   { "andpX",            { XM, EXx } },
1751   { "andnpX",           { XM, EXx } },
1752   { "orpX",             { XM, EXx } },
1753   { "xorpX",            { XM, EXx } },
1754   /* 58 */
1755   { PREFIX_TABLE (PREFIX_0F58) },
1756   { PREFIX_TABLE (PREFIX_0F59) },
1757   { PREFIX_TABLE (PREFIX_0F5A) },
1758   { PREFIX_TABLE (PREFIX_0F5B) },
1759   { PREFIX_TABLE (PREFIX_0F5C) },
1760   { PREFIX_TABLE (PREFIX_0F5D) },
1761   { PREFIX_TABLE (PREFIX_0F5E) },
1762   { PREFIX_TABLE (PREFIX_0F5F) },
1763   /* 60 */
1764   { PREFIX_TABLE (PREFIX_0F60) },
1765   { PREFIX_TABLE (PREFIX_0F61) },
1766   { PREFIX_TABLE (PREFIX_0F62) },
1767   { "packsswb",         { MX, EM } },
1768   { "pcmpgtb",          { MX, EM } },
1769   { "pcmpgtw",          { MX, EM } },
1770   { "pcmpgtd",          { MX, EM } },
1771   { "packuswb",         { MX, EM } },
1772   /* 68 */
1773   { "punpckhbw",        { MX, EM } },
1774   { "punpckhwd",        { MX, EM } },
1775   { "punpckhdq",        { MX, EM } },
1776   { "packssdw",         { MX, EM } },
1777   { PREFIX_TABLE (PREFIX_0F6C) },
1778   { PREFIX_TABLE (PREFIX_0F6D) },
1779   { "movK",             { MX, Edq } },
1780   { PREFIX_TABLE (PREFIX_0F6F) },
1781   /* 70 */
1782   { PREFIX_TABLE (PREFIX_0F70) },
1783   { REG_TABLE (REG_0F71) },
1784   { REG_TABLE (REG_0F72) },
1785   { REG_TABLE (REG_0F73) },
1786   { "pcmpeqb",          { MX, EM } },
1787   { "pcmpeqw",          { MX, EM } },
1788   { "pcmpeqd",          { MX, EM } },
1789   { "emms",             { XX } },
1790   /* 78 */
1791   { PREFIX_TABLE (PREFIX_0F78) },
1792   { PREFIX_TABLE (PREFIX_0F79) },
1793   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1794   { "(bad)",            { XX } },
1795   { PREFIX_TABLE (PREFIX_0F7C) },
1796   { PREFIX_TABLE (PREFIX_0F7D) },
1797   { PREFIX_TABLE (PREFIX_0F7E) },
1798   { PREFIX_TABLE (PREFIX_0F7F) },
1799   /* 80 */
1800   { "joH",              { Jv, XX, cond_jump_flag } },
1801   { "jnoH",             { Jv, XX, cond_jump_flag } },
1802   { "jbH",              { Jv, XX, cond_jump_flag } },
1803   { "jaeH",             { Jv, XX, cond_jump_flag } },
1804   { "jeH",              { Jv, XX, cond_jump_flag } },
1805   { "jneH",             { Jv, XX, cond_jump_flag } },
1806   { "jbeH",             { Jv, XX, cond_jump_flag } },
1807   { "jaH",              { Jv, XX, cond_jump_flag } },
1808   /* 88 */
1809   { "jsH",              { Jv, XX, cond_jump_flag } },
1810   { "jnsH",             { Jv, XX, cond_jump_flag } },
1811   { "jpH",              { Jv, XX, cond_jump_flag } },
1812   { "jnpH",             { Jv, XX, cond_jump_flag } },
1813   { "jlH",              { Jv, XX, cond_jump_flag } },
1814   { "jgeH",             { Jv, XX, cond_jump_flag } },
1815   { "jleH",             { Jv, XX, cond_jump_flag } },
1816   { "jgH",              { Jv, XX, cond_jump_flag } },
1817   /* 90 */
1818   { "seto",             { Eb } },
1819   { "setno",            { Eb } },
1820   { "setb",             { Eb } },
1821   { "setae",            { Eb } },
1822   { "sete",             { Eb } },
1823   { "setne",            { Eb } },
1824   { "setbe",            { Eb } },
1825   { "seta",             { Eb } },
1826   /* 98 */
1827   { "sets",             { Eb } },
1828   { "setns",            { Eb } },
1829   { "setp",             { Eb } },
1830   { "setnp",            { Eb } },
1831   { "setl",             { Eb } },
1832   { "setge",            { Eb } },
1833   { "setle",            { Eb } },
1834   { "setg",             { Eb } },
1835   /* a0 */
1836   { "pushT",            { fs } },
1837   { "popT",             { fs } },
1838   { "cpuid",            { XX } },
1839   { "btS",              { Ev, Gv } },
1840   { "shldS",            { Ev, Gv, Ib } },
1841   { "shldS",            { Ev, Gv, CL } },
1842   { REG_TABLE (REG_0FA6) },
1843   { REG_TABLE (REG_0FA7) },
1844   /* a8 */
1845   { "pushT",            { gs } },
1846   { "popT",             { gs } },
1847   { "rsm",              { XX } },
1848   { "btsS",             { Ev, Gv } },
1849   { "shrdS",            { Ev, Gv, Ib } },
1850   { "shrdS",            { Ev, Gv, CL } },
1851   { REG_TABLE (REG_0FAE) },
1852   { "imulS",            { Gv, Ev } },
1853   /* b0 */
1854   { "cmpxchgB",         { Eb, Gb } },
1855   { "cmpxchgS",         { Ev, Gv } },
1856   { MOD_TABLE (MOD_0FB2) },
1857   { "btrS",             { Ev, Gv } },
1858   { MOD_TABLE (MOD_0FB4) },
1859   { MOD_TABLE (MOD_0FB5) },
1860   { "movz{bR|x}",       { Gv, Eb } },
1861   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
1862   /* b8 */
1863   { PREFIX_TABLE (PREFIX_0FB8) },
1864   { "ud2b",             { XX } },
1865   { REG_TABLE (REG_0FBA) },
1866   { "btcS",             { Ev, Gv } },
1867   { "bsfS",             { Gv, Ev } },
1868   { PREFIX_TABLE (PREFIX_0FBD) },
1869   { "movs{bR|x}",       { Gv, Eb } },
1870   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
1871   /* c0 */
1872   { "xaddB",            { Eb, Gb } },
1873   { "xaddS",            { Ev, Gv } },
1874   { PREFIX_TABLE (PREFIX_0FC2) },
1875   { PREFIX_TABLE (PREFIX_0FC3) },
1876   { "pinsrw",           { MX, Edqw, Ib } },
1877   { "pextrw",           { Gdq, MS, Ib } },
1878   { "shufpX",           { XM, EXx, Ib } },
1879   { REG_TABLE (REG_0FC7) },
1880   /* c8 */
1881   { "bswap",            { RMeAX } },
1882   { "bswap",            { RMeCX } },
1883   { "bswap",            { RMeDX } },
1884   { "bswap",            { RMeBX } },
1885   { "bswap",            { RMeSP } },
1886   { "bswap",            { RMeBP } },
1887   { "bswap",            { RMeSI } },
1888   { "bswap",            { RMeDI } },
1889   /* d0 */
1890   { PREFIX_TABLE (PREFIX_0FD0) },
1891   { "psrlw",            { MX, EM } },
1892   { "psrld",            { MX, EM } },
1893   { "psrlq",            { MX, EM } },
1894   { "paddq",            { MX, EM } },
1895   { "pmullw",           { MX, EM } },
1896   { PREFIX_TABLE (PREFIX_0FD6) },
1897   { MOD_TABLE (MOD_0FD7) },
1898   /* d8 */
1899   { "psubusb",          { MX, EM } },
1900   { "psubusw",          { MX, EM } },
1901   { "pminub",           { MX, EM } },
1902   { "pand",             { MX, EM } },
1903   { "paddusb",          { MX, EM } },
1904   { "paddusw",          { MX, EM } },
1905   { "pmaxub",           { MX, EM } },
1906   { "pandn",            { MX, EM } },
1907   /* e0 */
1908   { "pavgb",            { MX, EM } },
1909   { "psraw",            { MX, EM } },
1910   { "psrad",            { MX, EM } },
1911   { "pavgw",            { MX, EM } },
1912   { "pmulhuw",          { MX, EM } },
1913   { "pmulhw",           { MX, EM } },
1914   { PREFIX_TABLE (PREFIX_0FE6) },
1915   { PREFIX_TABLE (PREFIX_0FE7) },
1916   /* e8 */
1917   { "psubsb",           { MX, EM } },
1918   { "psubsw",           { MX, EM } },
1919   { "pminsw",           { MX, EM } },
1920   { "por",              { MX, EM } },
1921   { "paddsb",           { MX, EM } },
1922   { "paddsw",           { MX, EM } },
1923   { "pmaxsw",           { MX, EM } },
1924   { "pxor",             { MX, EM } },
1925   /* f0 */
1926   { PREFIX_TABLE (PREFIX_0FF0) },
1927   { "psllw",            { MX, EM } },
1928   { "pslld",            { MX, EM } },
1929   { "psllq",            { MX, EM } },
1930   { "pmuludq",          { MX, EM } },
1931   { "pmaddwd",          { MX, EM } },
1932   { "psadbw",           { MX, EM } },
1933   { PREFIX_TABLE (PREFIX_0FF7) },
1934   /* f8 */
1935   { "psubb",            { MX, EM } },
1936   { "psubw",            { MX, EM } },
1937   { "psubd",            { MX, EM } },
1938   { "psubq",            { MX, EM } },
1939   { "paddb",            { MX, EM } },
1940   { "paddw",            { MX, EM } },
1941   { "paddd",            { MX, EM } },
1942   { "(bad)",            { XX } },
1943 };
1944
1945 static const unsigned char onebyte_has_modrm[256] = {
1946   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1947   /*       -------------------------------        */
1948   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1949   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1950   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1951   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1952   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1953   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1954   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1955   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1956   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1957   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1958   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1959   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1960   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1961   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1962   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1963   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
1964   /*       -------------------------------        */
1965   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1966 };
1967
1968 static const unsigned char twobyte_has_modrm[256] = {
1969   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1970   /*       -------------------------------        */
1971   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1972   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1973   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1974   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1975   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1976   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1977   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1978   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1979   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1980   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1981   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1982   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1983   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1984   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1985   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1986   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
1987   /*       -------------------------------        */
1988   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1989 };
1990
1991 static char obuf[100];
1992 static char *obufp;
1993 static char *mnemonicendp;
1994 static char scratchbuf[100];
1995 static unsigned char *start_codep;
1996 static unsigned char *insn_codep;
1997 static unsigned char *codep;
1998 static int last_lock_prefix;
1999 static int last_repz_prefix;
2000 static int last_repnz_prefix;
2001 static int last_data_prefix;
2002 static int last_addr_prefix;
2003 static int last_rex_prefix;
2004 static int last_seg_prefix;
2005 #define MAX_CODE_LENGTH 15
2006 /* We can up to 14 prefixes since the maximum instruction length is
2007    15bytes.  */
2008 static int all_prefixes[MAX_CODE_LENGTH - 1];
2009 static disassemble_info *the_info;
2010 static struct
2011   {
2012     int mod;
2013     int reg;
2014     int rm;
2015   }
2016 modrm;
2017 static unsigned char need_modrm;
2018 static struct
2019   {
2020     int register_specifier;
2021     int length;
2022     int prefix;
2023     int w;
2024   }
2025 vex;
2026 static unsigned char need_vex;
2027 static unsigned char need_vex_reg;
2028 static unsigned char vex_w_done;
2029
2030 struct op
2031   {
2032     const char *name;
2033     unsigned int len;
2034   };
2035
2036 /* If we are accessing mod/rm/reg without need_modrm set, then the
2037    values are stale.  Hitting this abort likely indicates that you
2038    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2039 #define MODRM_CHECK  if (!need_modrm) abort ()
2040
2041 static const char **names64;
2042 static const char **names32;
2043 static const char **names16;
2044 static const char **names8;
2045 static const char **names8rex;
2046 static const char **names_seg;
2047 static const char *index64;
2048 static const char *index32;
2049 static const char **index16;
2050
2051 static const char *intel_names64[] = {
2052   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2053   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2054 };
2055 static const char *intel_names32[] = {
2056   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2057   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2058 };
2059 static const char *intel_names16[] = {
2060   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2061   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2062 };
2063 static const char *intel_names8[] = {
2064   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2065 };
2066 static const char *intel_names8rex[] = {
2067   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2068   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2069 };
2070 static const char *intel_names_seg[] = {
2071   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2072 };
2073 static const char *intel_index64 = "riz";
2074 static const char *intel_index32 = "eiz";
2075 static const char *intel_index16[] = {
2076   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2077 };
2078
2079 static const char *att_names64[] = {
2080   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2081   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2082 };
2083 static const char *att_names32[] = {
2084   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2085   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2086 };
2087 static const char *att_names16[] = {
2088   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2089   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2090 };
2091 static const char *att_names8[] = {
2092   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2093 };
2094 static const char *att_names8rex[] = {
2095   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2096   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2097 };
2098 static const char *att_names_seg[] = {
2099   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2100 };
2101 static const char *att_index64 = "%riz";
2102 static const char *att_index32 = "%eiz";
2103 static const char *att_index16[] = {
2104   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2105 };
2106
2107 static const struct dis386 reg_table[][8] = {
2108   /* REG_80 */
2109   {
2110     { "addA",   { Eb, Ib } },
2111     { "orA",    { Eb, Ib } },
2112     { "adcA",   { Eb, Ib } },
2113     { "sbbA",   { Eb, Ib } },
2114     { "andA",   { Eb, Ib } },
2115     { "subA",   { Eb, Ib } },
2116     { "xorA",   { Eb, Ib } },
2117     { "cmpA",   { Eb, Ib } },
2118   },
2119   /* REG_81 */
2120   {
2121     { "addQ",   { Ev, Iv } },
2122     { "orQ",    { Ev, Iv } },
2123     { "adcQ",   { Ev, Iv } },
2124     { "sbbQ",   { Ev, Iv } },
2125     { "andQ",   { Ev, Iv } },
2126     { "subQ",   { Ev, Iv } },
2127     { "xorQ",   { Ev, Iv } },
2128     { "cmpQ",   { Ev, Iv } },
2129   },
2130   /* REG_82 */
2131   {
2132     { "addQ",   { Ev, sIb } },
2133     { "orQ",    { Ev, sIb } },
2134     { "adcQ",   { Ev, sIb } },
2135     { "sbbQ",   { Ev, sIb } },
2136     { "andQ",   { Ev, sIb } },
2137     { "subQ",   { Ev, sIb } },
2138     { "xorQ",   { Ev, sIb } },
2139     { "cmpQ",   { Ev, sIb } },
2140   },
2141   /* REG_8F */
2142   {
2143     { "popU",   { stackEv } },
2144     { XOP_8F_TABLE (XOP_09) },
2145     { "(bad)",  { XX } },
2146     { "(bad)",  { XX } },
2147     { "(bad)",  { XX } },
2148     { XOP_8F_TABLE (XOP_09) },
2149     { "(bad)",  { XX } },
2150     { "(bad)",  { XX } },
2151   },
2152   /* REG_C0 */
2153   {
2154     { "rolA",   { Eb, Ib } },
2155     { "rorA",   { Eb, Ib } },
2156     { "rclA",   { Eb, Ib } },
2157     { "rcrA",   { Eb, Ib } },
2158     { "shlA",   { Eb, Ib } },
2159     { "shrA",   { Eb, Ib } },
2160     { "(bad)",  { XX } },
2161     { "sarA",   { Eb, Ib } },
2162   },
2163   /* REG_C1 */
2164   {
2165     { "rolQ",   { Ev, Ib } },
2166     { "rorQ",   { Ev, Ib } },
2167     { "rclQ",   { Ev, Ib } },
2168     { "rcrQ",   { Ev, Ib } },
2169     { "shlQ",   { Ev, Ib } },
2170     { "shrQ",   { Ev, Ib } },
2171     { "(bad)",  { XX } },
2172     { "sarQ",   { Ev, Ib } },
2173   },
2174   /* REG_C6 */
2175   {
2176     { "movA",   { Eb, Ib } },
2177     { "(bad)",  { XX } },
2178     { "(bad)",  { XX } },
2179     { "(bad)",  { XX } },
2180     { "(bad)",  { XX } },
2181     { "(bad)",  { XX } },
2182     { "(bad)",  { XX } },
2183     { "(bad)",  { XX } },
2184   },
2185   /* REG_C7 */
2186   {
2187     { "movQ",   { Ev, Iv } },
2188     { "(bad)",  { XX } },
2189     { "(bad)",  { XX } },
2190     { "(bad)",  { XX } },
2191     { "(bad)",  { XX } },
2192     { "(bad)",  { XX } },
2193     { "(bad)",  { XX } },
2194     { "(bad)",  { XX } },
2195   },
2196   /* REG_D0 */
2197   {
2198     { "rolA",   { Eb, I1 } },
2199     { "rorA",   { Eb, I1 } },
2200     { "rclA",   { Eb, I1 } },
2201     { "rcrA",   { Eb, I1 } },
2202     { "shlA",   { Eb, I1 } },
2203     { "shrA",   { Eb, I1 } },
2204     { "(bad)",  { XX } },
2205     { "sarA",   { Eb, I1 } },
2206   },
2207   /* REG_D1 */
2208   {
2209     { "rolQ",   { Ev, I1 } },
2210     { "rorQ",   { Ev, I1 } },
2211     { "rclQ",   { Ev, I1 } },
2212     { "rcrQ",   { Ev, I1 } },
2213     { "shlQ",   { Ev, I1 } },
2214     { "shrQ",   { Ev, I1 } },
2215     { "(bad)",  { XX } },
2216     { "sarQ",   { Ev, I1 } },
2217   },
2218   /* REG_D2 */
2219   {
2220     { "rolA",   { Eb, CL } },
2221     { "rorA",   { Eb, CL } },
2222     { "rclA",   { Eb, CL } },
2223     { "rcrA",   { Eb, CL } },
2224     { "shlA",   { Eb, CL } },
2225     { "shrA",   { Eb, CL } },
2226     { "(bad)",  { XX } },
2227     { "sarA",   { Eb, CL } },
2228   },
2229   /* REG_D3 */
2230   {
2231     { "rolQ",   { Ev, CL } },
2232     { "rorQ",   { Ev, CL } },
2233     { "rclQ",   { Ev, CL } },
2234     { "rcrQ",   { Ev, CL } },
2235     { "shlQ",   { Ev, CL } },
2236     { "shrQ",   { Ev, CL } },
2237     { "(bad)",  { XX } },
2238     { "sarQ",   { Ev, CL } },
2239   },
2240   /* REG_F6 */
2241   {
2242     { "testA",  { Eb, Ib } },
2243     { "(bad)",  { XX } },
2244     { "notA",   { Eb } },
2245     { "negA",   { Eb } },
2246     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2247     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2248     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2249     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2250   },
2251   /* REG_F7 */
2252   {
2253     { "testQ",  { Ev, Iv } },
2254     { "(bad)",  { XX } },
2255     { "notQ",   { Ev } },
2256     { "negQ",   { Ev } },
2257     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2258     { "imulQ",  { Ev } },
2259     { "divQ",   { Ev } },
2260     { "idivQ",  { Ev } },
2261   },
2262   /* REG_FE */
2263   {
2264     { "incA",   { Eb } },
2265     { "decA",   { Eb } },
2266     { "(bad)",  { XX } },
2267     { "(bad)",  { XX } },
2268     { "(bad)",  { XX } },
2269     { "(bad)",  { XX } },
2270     { "(bad)",  { XX } },
2271     { "(bad)",  { XX } },
2272   },
2273   /* REG_FF */
2274   {
2275     { "incQ",   { Ev } },
2276     { "decQ",   { Ev } },
2277     { "callT",  { indirEv } },
2278     { "JcallT", { indirEp } },
2279     { "jmpT",   { indirEv } },
2280     { "JjmpT",  { indirEp } },
2281     { "pushU",  { stackEv } },
2282     { "(bad)",  { XX } },
2283   },
2284   /* REG_0F00 */
2285   {
2286     { "sldtD",  { Sv } },
2287     { "strD",   { Sv } },
2288     { "lldt",   { Ew } },
2289     { "ltr",    { Ew } },
2290     { "verr",   { Ew } },
2291     { "verw",   { Ew } },
2292     { "(bad)",  { XX } },
2293     { "(bad)",  { XX } },
2294   },
2295   /* REG_0F01 */
2296   {
2297     { MOD_TABLE (MOD_0F01_REG_0) },
2298     { MOD_TABLE (MOD_0F01_REG_1) },
2299     { MOD_TABLE (MOD_0F01_REG_2) },
2300     { MOD_TABLE (MOD_0F01_REG_3) },
2301     { "smswD",  { Sv } },
2302     { "(bad)",  { XX } },
2303     { "lmsw",   { Ew } },
2304     { MOD_TABLE (MOD_0F01_REG_7) },
2305   },
2306   /* REG_0F0D */
2307   {
2308     { "prefetch",       { Eb } },
2309     { "prefetchw",      { Eb } },
2310     { "(bad)",          { XX } },
2311     { "(bad)",          { XX } },
2312     { "(bad)",          { XX } },
2313     { "(bad)",          { XX } },
2314     { "(bad)",          { XX } },
2315     { "(bad)",          { XX } },
2316   },
2317   /* REG_0F18 */
2318   {
2319     { MOD_TABLE (MOD_0F18_REG_0) },
2320     { MOD_TABLE (MOD_0F18_REG_1) },
2321     { MOD_TABLE (MOD_0F18_REG_2) },
2322     { MOD_TABLE (MOD_0F18_REG_3) },
2323     { "(bad)",  { XX } },
2324     { "(bad)",  { XX } },
2325     { "(bad)",  { XX } },
2326     { "(bad)",  { XX } },
2327   },
2328   /* REG_0F71 */
2329   {
2330     { "(bad)",  { XX } },
2331     { "(bad)",  { XX } },
2332     { MOD_TABLE (MOD_0F71_REG_2) },
2333     { "(bad)",  { XX } },
2334     { MOD_TABLE (MOD_0F71_REG_4) },
2335     { "(bad)",  { XX } },
2336     { MOD_TABLE (MOD_0F71_REG_6) },
2337     { "(bad)",  { XX } },
2338   },
2339   /* REG_0F72 */
2340   {
2341     { "(bad)",  { XX } },
2342     { "(bad)",  { XX } },
2343     { MOD_TABLE (MOD_0F72_REG_2) },
2344     { "(bad)",  { XX } },
2345     { MOD_TABLE (MOD_0F72_REG_4) },
2346     { "(bad)",  { XX } },
2347     { MOD_TABLE (MOD_0F72_REG_6) },
2348     { "(bad)",  { XX } },
2349   },
2350   /* REG_0F73 */
2351   {
2352     { "(bad)",  { XX } },
2353     { "(bad)",  { XX } },
2354     { MOD_TABLE (MOD_0F73_REG_2) },
2355     { MOD_TABLE (MOD_0F73_REG_3) },
2356     { "(bad)",  { XX } },
2357     { "(bad)",  { XX } },
2358     { MOD_TABLE (MOD_0F73_REG_6) },
2359     { MOD_TABLE (MOD_0F73_REG_7) },
2360   },
2361   /* REG_0FA6 */
2362   {
2363     { "montmul",        { { OP_0f07, 0 } } },
2364     { "xsha1",          { { OP_0f07, 0 } } },
2365     { "xsha256",        { { OP_0f07, 0 } } },
2366     { "(bad)",          { { OP_0f07, 0 } } },
2367     { "(bad)",          { { OP_0f07, 0 } } },
2368     { "(bad)",          { { OP_0f07, 0 } } },
2369     { "(bad)",          { { OP_0f07, 0 } } },
2370     { "(bad)",          { { OP_0f07, 0 } } },
2371   },
2372   /* REG_0FA7 */
2373   {
2374     { "xstore-rng",     { { OP_0f07, 0 } } },
2375     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2376     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2377     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2378     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2379     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2380     { "(bad)",          { { OP_0f07, 0 } } },
2381     { "(bad)",          { { OP_0f07, 0 } } },
2382   },
2383   /* REG_0FAE */
2384   {
2385     { MOD_TABLE (MOD_0FAE_REG_0) },
2386     { MOD_TABLE (MOD_0FAE_REG_1) },
2387     { MOD_TABLE (MOD_0FAE_REG_2) },
2388     { MOD_TABLE (MOD_0FAE_REG_3) },
2389     { MOD_TABLE (MOD_0FAE_REG_4) },
2390     { MOD_TABLE (MOD_0FAE_REG_5) },
2391     { MOD_TABLE (MOD_0FAE_REG_6) },
2392     { MOD_TABLE (MOD_0FAE_REG_7) },
2393   },
2394   /* REG_0FBA */
2395   {
2396     { "(bad)",  { XX } },
2397     { "(bad)",  { XX } },
2398     { "(bad)",  { XX } },
2399     { "(bad)",  { XX } },
2400     { "btQ",    { Ev, Ib } },
2401     { "btsQ",   { Ev, Ib } },
2402     { "btrQ",   { Ev, Ib } },
2403     { "btcQ",   { Ev, Ib } },
2404   },
2405   /* REG_0FC7 */
2406   {
2407     { "(bad)",  { XX } },
2408     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2409     { "(bad)",  { XX } },
2410     { "(bad)",  { XX } },
2411     { "(bad)",  { XX } },
2412     { "(bad)",  { XX } },
2413     { MOD_TABLE (MOD_0FC7_REG_6) },
2414     { MOD_TABLE (MOD_0FC7_REG_7) },
2415   },
2416   /* REG_VEX_71 */
2417   {
2418     { "(bad)",  { XX } },
2419     { "(bad)",  { XX } },
2420     { MOD_TABLE (MOD_VEX_71_REG_2) },
2421     { "(bad)",  { XX } },
2422     { MOD_TABLE (MOD_VEX_71_REG_4) },
2423     { "(bad)",  { XX } },
2424     { MOD_TABLE (MOD_VEX_71_REG_6) },
2425     { "(bad)",  { XX } },
2426   },
2427   /* REG_VEX_72 */
2428   {
2429     { "(bad)",  { XX } },
2430     { "(bad)",  { XX } },
2431     { MOD_TABLE (MOD_VEX_72_REG_2) },
2432     { "(bad)",  { XX } },
2433     { MOD_TABLE (MOD_VEX_72_REG_4) },
2434     { "(bad)",  { XX } },
2435     { MOD_TABLE (MOD_VEX_72_REG_6) },
2436     { "(bad)",  { XX } },
2437   },
2438   /* REG_VEX_73 */
2439   {
2440     { "(bad)",  { XX } },
2441     { "(bad)",  { XX } },
2442     { MOD_TABLE (MOD_VEX_73_REG_2) },
2443     { MOD_TABLE (MOD_VEX_73_REG_3) },
2444     { "(bad)",  { XX } },
2445     { "(bad)",  { XX } },
2446     { MOD_TABLE (MOD_VEX_73_REG_6) },
2447     { MOD_TABLE (MOD_VEX_73_REG_7) },
2448   },
2449   /* REG_VEX_AE */
2450   {
2451     { "(bad)",  { XX } },
2452     { "(bad)",  { XX } },
2453     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2454     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2455     { "(bad)",  { XX } },
2456     { "(bad)",  { XX } },
2457     { "(bad)",  { XX } },
2458     { "(bad)",  { XX } },
2459   },
2460   /* REG_XOP_LWPCB */
2461   {
2462     { "llwpcb", { { OP_LWPCB_E, 0 } } },
2463     { "slwpcb", { { OP_LWPCB_E, 0 } } },
2464     { "(bad)",  { XX } },
2465     { "(bad)",  { XX } },
2466     { "(bad)",  { XX } },
2467     { "(bad)",  { XX } },
2468     { "(bad)",  { XX } },
2469     { "(bad)",  { XX } },
2470   },
2471   /* REG_XOP_LWP */
2472   {
2473     { "lwpins", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2474     { "lwpval", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2475     { "(bad)",  { XX } },
2476     { "(bad)",  { XX } },
2477     { "(bad)",  { XX } },
2478     { "(bad)",  { XX } },
2479     { "(bad)",  { XX } },
2480     { "(bad)",  { XX } },
2481   },
2482 };
2483
2484 static const struct dis386 prefix_table[][4] = {
2485   /* PREFIX_90 */
2486   {
2487     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2488     { "pause", { XX } },
2489     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2490     { "(bad)", { XX } },
2491   },
2492
2493   /* PREFIX_0F10 */
2494   {
2495     { "movups", { XM, EXx } },
2496     { "movss",  { XM, EXd } },
2497     { "movupd", { XM, EXx } },
2498     { "movsd",  { XM, EXq } },
2499   },
2500
2501   /* PREFIX_0F11 */
2502   {
2503     { "movups", { EXxS, XM } },
2504     { "movss",  { EXdS, XM } },
2505     { "movupd", { EXxS, XM } },
2506     { "movsd",  { EXqS, XM } },
2507   },
2508
2509   /* PREFIX_0F12 */
2510   {
2511     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2512     { "movsldup", { XM, EXx } },
2513     { "movlpd", { XM, EXq } },
2514     { "movddup", { XM, EXq } },
2515   },
2516
2517   /* PREFIX_0F16 */
2518   {
2519     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2520     { "movshdup", { XM, EXx } },
2521     { "movhpd", { XM, EXq } },
2522     { "(bad)",  { XX } },
2523   },
2524
2525   /* PREFIX_0F2A */
2526   {
2527     { "cvtpi2ps", { XM, EMCq } },
2528     { "cvtsi2ss%LQ", { XM, Ev } },
2529     { "cvtpi2pd", { XM, EMCq } },
2530     { "cvtsi2sd%LQ", { XM, Ev } },
2531   },
2532
2533   /* PREFIX_0F2B */
2534   {
2535     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2536     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2537     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2538     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2539   },
2540
2541   /* PREFIX_0F2C */
2542   {
2543     { "cvttps2pi", { MXC, EXq } },
2544     { "cvttss2siY", { Gv, EXd } },
2545     { "cvttpd2pi", { MXC, EXx } },
2546     { "cvttsd2siY", { Gv, EXq } },
2547   },
2548
2549   /* PREFIX_0F2D */
2550   {
2551     { "cvtps2pi", { MXC, EXq } },
2552     { "cvtss2siY", { Gv, EXd } },
2553     { "cvtpd2pi", { MXC, EXx } },
2554     { "cvtsd2siY", { Gv, EXq } },
2555   },
2556
2557   /* PREFIX_0F2E */
2558   {
2559     { "ucomiss",{ XM, EXd } },
2560     { "(bad)",  { XX } },
2561     { "ucomisd",{ XM, EXq } },
2562     { "(bad)",  { XX } },
2563   },
2564
2565   /* PREFIX_0F2F */
2566   {
2567     { "comiss", { XM, EXd } },
2568     { "(bad)",  { XX } },
2569     { "comisd", { XM, EXq } },
2570     { "(bad)",  { XX } },
2571   },
2572
2573   /* PREFIX_0F51 */
2574   {
2575     { "sqrtps", { XM, EXx } },
2576     { "sqrtss", { XM, EXd } },
2577     { "sqrtpd", { XM, EXx } },
2578     { "sqrtsd", { XM, EXq } },
2579   },
2580
2581   /* PREFIX_0F52 */
2582   {
2583     { "rsqrtps",{ XM, EXx } },
2584     { "rsqrtss",{ XM, EXd } },
2585     { "(bad)",  { XX } },
2586     { "(bad)",  { XX } },
2587   },
2588
2589   /* PREFIX_0F53 */
2590   {
2591     { "rcpps",  { XM, EXx } },
2592     { "rcpss",  { XM, EXd } },
2593     { "(bad)",  { XX } },
2594     { "(bad)",  { XX } },
2595   },
2596
2597   /* PREFIX_0F58 */
2598   {
2599     { "addps", { XM, EXx } },
2600     { "addss", { XM, EXd } },
2601     { "addpd", { XM, EXx } },
2602     { "addsd", { XM, EXq } },
2603   },
2604
2605   /* PREFIX_0F59 */
2606   {
2607     { "mulps",  { XM, EXx } },
2608     { "mulss",  { XM, EXd } },
2609     { "mulpd",  { XM, EXx } },
2610     { "mulsd",  { XM, EXq } },
2611   },
2612
2613   /* PREFIX_0F5A */
2614   {
2615     { "cvtps2pd", { XM, EXq } },
2616     { "cvtss2sd", { XM, EXd } },
2617     { "cvtpd2ps", { XM, EXx } },
2618     { "cvtsd2ss", { XM, EXq } },
2619   },
2620
2621   /* PREFIX_0F5B */
2622   {
2623     { "cvtdq2ps", { XM, EXx } },
2624     { "cvttps2dq", { XM, EXx } },
2625     { "cvtps2dq", { XM, EXx } },
2626     { "(bad)",  { XX } },
2627   },
2628
2629   /* PREFIX_0F5C */
2630   {
2631     { "subps",  { XM, EXx } },
2632     { "subss",  { XM, EXd } },
2633     { "subpd",  { XM, EXx } },
2634     { "subsd",  { XM, EXq } },
2635   },
2636
2637   /* PREFIX_0F5D */
2638   {
2639     { "minps",  { XM, EXx } },
2640     { "minss",  { XM, EXd } },
2641     { "minpd",  { XM, EXx } },
2642     { "minsd",  { XM, EXq } },
2643   },
2644
2645   /* PREFIX_0F5E */
2646   {
2647     { "divps",  { XM, EXx } },
2648     { "divss",  { XM, EXd } },
2649     { "divpd",  { XM, EXx } },
2650     { "divsd",  { XM, EXq } },
2651   },
2652
2653   /* PREFIX_0F5F */
2654   {
2655     { "maxps",  { XM, EXx } },
2656     { "maxss",  { XM, EXd } },
2657     { "maxpd",  { XM, EXx } },
2658     { "maxsd",  { XM, EXq } },
2659   },
2660
2661   /* PREFIX_0F60 */
2662   {
2663     { "punpcklbw",{ MX, EMd } },
2664     { "(bad)",  { XX } },
2665     { "punpcklbw",{ MX, EMx } },
2666     { "(bad)",  { XX } },
2667   },
2668
2669   /* PREFIX_0F61 */
2670   {
2671     { "punpcklwd",{ MX, EMd } },
2672     { "(bad)",  { XX } },
2673     { "punpcklwd",{ MX, EMx } },
2674     { "(bad)",  { XX } },
2675   },
2676
2677   /* PREFIX_0F62 */
2678   {
2679     { "punpckldq",{ MX, EMd } },
2680     { "(bad)",  { XX } },
2681     { "punpckldq",{ MX, EMx } },
2682     { "(bad)",  { XX } },
2683   },
2684
2685   /* PREFIX_0F6C */
2686   {
2687     { "(bad)",  { XX } },
2688     { "(bad)",  { XX } },
2689     { "punpcklqdq", { XM, EXx } },
2690     { "(bad)",  { XX } },
2691   },
2692
2693   /* PREFIX_0F6D */
2694   {
2695     { "(bad)",  { XX } },
2696     { "(bad)",  { XX } },
2697     { "punpckhqdq", { XM, EXx } },
2698     { "(bad)",  { XX } },
2699   },
2700
2701   /* PREFIX_0F6F */
2702   {
2703     { "movq",   { MX, EM } },
2704     { "movdqu", { XM, EXx } },
2705     { "movdqa", { XM, EXx } },
2706     { "(bad)",  { XX } },
2707   },
2708
2709   /* PREFIX_0F70 */
2710   {
2711     { "pshufw", { MX, EM, Ib } },
2712     { "pshufhw",{ XM, EXx, Ib } },
2713     { "pshufd", { XM, EXx, Ib } },
2714     { "pshuflw",{ XM, EXx, Ib } },
2715   },
2716
2717   /* PREFIX_0F73_REG_3 */
2718   {
2719     { "(bad)",  { XX } },
2720     { "(bad)",  { XX } },
2721     { "psrldq", { XS, Ib } },
2722     { "(bad)",  { XX } },
2723   },
2724
2725   /* PREFIX_0F73_REG_7 */
2726   {
2727     { "(bad)",  { XX } },
2728     { "(bad)",  { XX } },
2729     { "pslldq", { XS, Ib } },
2730     { "(bad)",  { XX } },
2731   },
2732
2733   /* PREFIX_0F78 */
2734   {
2735     {"vmread",  { Em, Gm } },
2736     {"(bad)",   { XX } },
2737     {"extrq",   { XS, Ib, Ib } },
2738     {"insertq", { XM, XS, Ib, Ib } },
2739   },
2740
2741   /* PREFIX_0F79 */
2742   {
2743     {"vmwrite", { Gm, Em } },
2744     {"(bad)",   { XX } },
2745     {"extrq",   { XM, XS } },
2746     {"insertq", { XM, XS } },
2747   },
2748
2749   /* PREFIX_0F7C */
2750   {
2751     { "(bad)",  { XX } },
2752     { "(bad)",  { XX } },
2753     { "haddpd", { XM, EXx } },
2754     { "haddps", { XM, EXx } },
2755   },
2756
2757   /* PREFIX_0F7D */
2758   {
2759     { "(bad)",  { XX } },
2760     { "(bad)",  { XX } },
2761     { "hsubpd", { XM, EXx } },
2762     { "hsubps", { XM, EXx } },
2763   },
2764
2765   /* PREFIX_0F7E */
2766   {
2767     { "movK",   { Edq, MX } },
2768     { "movq",   { XM, EXq } },
2769     { "movK",   { Edq, XM } },
2770     { "(bad)",  { XX } },
2771   },
2772
2773   /* PREFIX_0F7F */
2774   {
2775     { "movq",   { EMS, MX } },
2776     { "movdqu", { EXxS, XM } },
2777     { "movdqa", { EXxS, XM } },
2778     { "(bad)",  { XX } },
2779   },
2780
2781   /* PREFIX_0FB8 */
2782   {
2783     { "(bad)", { XX } },
2784     { "popcntS", { Gv, Ev } },
2785     { "(bad)", { XX } },
2786     { "(bad)", { XX } },
2787   },
2788
2789   /* PREFIX_0FBD */
2790   {
2791     { "bsrS",   { Gv, Ev } },
2792     { "lzcntS", { Gv, Ev } },
2793     { "bsrS",   { Gv, Ev } },
2794     { "(bad)",  { XX } },
2795   },
2796
2797   /* PREFIX_0FC2 */
2798   {
2799     { "cmpps",  { XM, EXx, CMP } },
2800     { "cmpss",  { XM, EXd, CMP } },
2801     { "cmppd",  { XM, EXx, CMP } },
2802     { "cmpsd",  { XM, EXq, CMP } },
2803   },
2804
2805   /* PREFIX_0FC3 */
2806   {
2807     { "movntiS", { Ma, Gv } },
2808     { "(bad)",  { XX } },
2809     { "(bad)",  { XX } },
2810     { "(bad)",  { XX } },
2811   },
2812
2813   /* PREFIX_0FC7_REG_6 */
2814   {
2815     { "vmptrld",{ Mq } },
2816     { "vmxon",  { Mq } },
2817     { "vmclear",{ Mq } },
2818     { "(bad)",  { XX } },
2819   },
2820
2821   /* PREFIX_0FD0 */
2822   {
2823     { "(bad)",  { XX } },
2824     { "(bad)",  { XX } },
2825     { "addsubpd", { XM, EXx } },
2826     { "addsubps", { XM, EXx } },
2827   },
2828
2829   /* PREFIX_0FD6 */
2830   {
2831     { "(bad)",  { XX } },
2832     { "movq2dq",{ XM, MS } },
2833     { "movq",   { EXqS, XM } },
2834     { "movdq2q",{ MX, XS } },
2835   },
2836
2837   /* PREFIX_0FE6 */
2838   {
2839     { "(bad)",  { XX } },
2840     { "cvtdq2pd", { XM, EXq } },
2841     { "cvttpd2dq", { XM, EXx } },
2842     { "cvtpd2dq", { XM, EXx } },
2843   },
2844
2845   /* PREFIX_0FE7 */
2846   {
2847     { "movntq", { Mq, MX } },
2848     { "(bad)",  { XX } },
2849     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
2850     { "(bad)",  { XX } },
2851   },
2852
2853   /* PREFIX_0FF0 */
2854   {
2855     { "(bad)",  { XX } },
2856     { "(bad)",  { XX } },
2857     { "(bad)",  { XX } },
2858     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2859   },
2860
2861   /* PREFIX_0FF7 */
2862   {
2863     { "maskmovq", { MX, MS } },
2864     { "(bad)",  { XX } },
2865     { "maskmovdqu", { XM, XS } },
2866     { "(bad)",  { XX } },
2867   },
2868
2869   /* PREFIX_0F3810 */
2870   {
2871     { "(bad)",  { XX } },
2872     { "(bad)",  { XX } },
2873     { "pblendvb", { XM, EXx, XMM0 } },
2874     { "(bad)",  { XX } },
2875   },
2876
2877   /* PREFIX_0F3814 */
2878   {
2879     { "(bad)",  { XX } },
2880     { "(bad)",  { XX } },
2881     { "blendvps", { XM, EXx, XMM0 } },
2882     { "(bad)",  { XX } },
2883   },
2884
2885   /* PREFIX_0F3815 */
2886   {
2887     { "(bad)",  { XX } },
2888     { "(bad)",  { XX } },
2889     { "blendvpd", { XM, EXx, XMM0 } },
2890     { "(bad)",  { XX } },
2891   },
2892
2893   /* PREFIX_0F3817 */
2894   {
2895     { "(bad)",  { XX } },
2896     { "(bad)",  { XX } },
2897     { "ptest",  { XM, EXx } },
2898     { "(bad)",  { XX } },
2899   },
2900
2901   /* PREFIX_0F3820 */
2902   {
2903     { "(bad)",  { XX } },
2904     { "(bad)",  { XX } },
2905     { "pmovsxbw", { XM, EXq } },
2906     { "(bad)",  { XX } },
2907   },
2908
2909   /* PREFIX_0F3821 */
2910   {
2911     { "(bad)",  { XX } },
2912     { "(bad)",  { XX } },
2913     { "pmovsxbd", { XM, EXd } },
2914     { "(bad)",  { XX } },
2915   },
2916
2917   /* PREFIX_0F3822 */
2918   {
2919     { "(bad)",  { XX } },
2920     { "(bad)",  { XX } },
2921     { "pmovsxbq", { XM, EXw } },
2922     { "(bad)",  { XX } },
2923   },
2924
2925   /* PREFIX_0F3823 */
2926   {
2927     { "(bad)",  { XX } },
2928     { "(bad)",  { XX } },
2929     { "pmovsxwd", { XM, EXq } },
2930     { "(bad)",  { XX } },
2931   },
2932
2933   /* PREFIX_0F3824 */
2934   {
2935     { "(bad)",  { XX } },
2936     { "(bad)",  { XX } },
2937     { "pmovsxwq", { XM, EXd } },
2938     { "(bad)",  { XX } },
2939   },
2940
2941   /* PREFIX_0F3825 */
2942   {
2943     { "(bad)",  { XX } },
2944     { "(bad)",  { XX } },
2945     { "pmovsxdq", { XM, EXq } },
2946     { "(bad)",  { XX } },
2947   },
2948
2949   /* PREFIX_0F3828 */
2950   {
2951     { "(bad)",  { XX } },
2952     { "(bad)",  { XX } },
2953     { "pmuldq", { XM, EXx } },
2954     { "(bad)",  { XX } },
2955   },
2956
2957   /* PREFIX_0F3829 */
2958   {
2959     { "(bad)",  { XX } },
2960     { "(bad)",  { XX } },
2961     { "pcmpeqq", { XM, EXx } },
2962     { "(bad)",  { XX } },
2963   },
2964
2965   /* PREFIX_0F382A */
2966   {
2967     { "(bad)",  { XX } },
2968     { "(bad)",  { XX } },
2969     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
2970     { "(bad)",  { XX } },
2971   },
2972
2973   /* PREFIX_0F382B */
2974   {
2975     { "(bad)",  { XX } },
2976     { "(bad)",  { XX } },
2977     { "packusdw", { XM, EXx } },
2978     { "(bad)",  { XX } },
2979   },
2980
2981   /* PREFIX_0F3830 */
2982   {
2983     { "(bad)",  { XX } },
2984     { "(bad)",  { XX } },
2985     { "pmovzxbw", { XM, EXq } },
2986     { "(bad)",  { XX } },
2987   },
2988
2989   /* PREFIX_0F3831 */
2990   {
2991     { "(bad)",  { XX } },
2992     { "(bad)",  { XX } },
2993     { "pmovzxbd", { XM, EXd } },
2994     { "(bad)",  { XX } },
2995   },
2996
2997   /* PREFIX_0F3832 */
2998   {
2999     { "(bad)",  { XX } },
3000     { "(bad)",  { XX } },
3001     { "pmovzxbq", { XM, EXw } },
3002     { "(bad)",  { XX } },
3003   },
3004
3005   /* PREFIX_0F3833 */
3006   {
3007     { "(bad)",  { XX } },
3008     { "(bad)",  { XX } },
3009     { "pmovzxwd", { XM, EXq } },
3010     { "(bad)",  { XX } },
3011   },
3012
3013   /* PREFIX_0F3834 */
3014   {
3015     { "(bad)",  { XX } },
3016     { "(bad)",  { XX } },
3017     { "pmovzxwq", { XM, EXd } },
3018     { "(bad)",  { XX } },
3019   },
3020
3021   /* PREFIX_0F3835 */
3022   {
3023     { "(bad)",  { XX } },
3024     { "(bad)",  { XX } },
3025     { "pmovzxdq", { XM, EXq } },
3026     { "(bad)",  { XX } },
3027   },
3028
3029   /* PREFIX_0F3837 */
3030   {
3031     { "(bad)",  { XX } },
3032     { "(bad)",  { XX } },
3033     { "pcmpgtq", { XM, EXx } },
3034     { "(bad)",  { XX } },
3035   },
3036
3037   /* PREFIX_0F3838 */
3038   {
3039     { "(bad)",  { XX } },
3040     { "(bad)",  { XX } },
3041     { "pminsb", { XM, EXx } },
3042     { "(bad)",  { XX } },
3043   },
3044
3045   /* PREFIX_0F3839 */
3046   {
3047     { "(bad)",  { XX } },
3048     { "(bad)",  { XX } },
3049     { "pminsd", { XM, EXx } },
3050     { "(bad)",  { XX } },
3051   },
3052
3053   /* PREFIX_0F383A */
3054   {
3055     { "(bad)",  { XX } },
3056     { "(bad)",  { XX } },
3057     { "pminuw", { XM, EXx } },
3058     { "(bad)",  { XX } },
3059   },
3060
3061   /* PREFIX_0F383B */
3062   {
3063     { "(bad)",  { XX } },
3064     { "(bad)",  { XX } },
3065     { "pminud", { XM, EXx } },
3066     { "(bad)",  { XX } },
3067   },
3068
3069   /* PREFIX_0F383C */
3070   {
3071     { "(bad)",  { XX } },
3072     { "(bad)",  { XX } },
3073     { "pmaxsb", { XM, EXx } },
3074     { "(bad)",  { XX } },
3075   },
3076
3077   /* PREFIX_0F383D */
3078   {
3079     { "(bad)",  { XX } },
3080     { "(bad)",  { XX } },
3081     { "pmaxsd", { XM, EXx } },
3082     { "(bad)",  { XX } },
3083   },
3084
3085   /* PREFIX_0F383E */
3086   {
3087     { "(bad)",  { XX } },
3088     { "(bad)",  { XX } },
3089     { "pmaxuw", { XM, EXx } },
3090     { "(bad)",  { XX } },
3091   },
3092
3093   /* PREFIX_0F383F */
3094   {
3095     { "(bad)",  { XX } },
3096     { "(bad)",  { XX } },
3097     { "pmaxud", { XM, EXx } },
3098     { "(bad)",  { XX } },
3099   },
3100
3101   /* PREFIX_0F3840 */
3102   {
3103     { "(bad)",  { XX } },
3104     { "(bad)",  { XX } },
3105     { "pmulld", { XM, EXx } },
3106     { "(bad)",  { XX } },
3107   },
3108
3109   /* PREFIX_0F3841 */
3110   {
3111     { "(bad)",  { XX } },
3112     { "(bad)",  { XX } },
3113     { "phminposuw", { XM, EXx } },
3114     { "(bad)",  { XX } },
3115   },
3116
3117   /* PREFIX_0F3880 */
3118   {
3119     { "(bad)",  { XX } },
3120     { "(bad)",  { XX } },
3121     { "invept", { Gm, Mo } },
3122     { "(bad)",  { XX } },
3123   },
3124
3125   /* PREFIX_0F3881 */
3126   {
3127     { "(bad)",  { XX } },
3128     { "(bad)",  { XX } },
3129     { "invvpid", { Gm, Mo } },
3130     { "(bad)",  { XX } },
3131   },
3132
3133   /* PREFIX_0F38DB */
3134   {
3135     { "(bad)",  { XX } },
3136     { "(bad)",  { XX } },
3137     { "aesimc", { XM, EXx } },
3138     { "(bad)",  { XX } },
3139   },
3140
3141   /* PREFIX_0F38DC */
3142   {
3143     { "(bad)",  { XX } },
3144     { "(bad)",  { XX } },
3145     { "aesenc", { XM, EXx } },
3146     { "(bad)",  { XX } },
3147   },
3148
3149   /* PREFIX_0F38DD */
3150   {
3151     { "(bad)",  { XX } },
3152     { "(bad)",  { XX } },
3153     { "aesenclast", { XM, EXx } },
3154     { "(bad)",  { XX } },
3155   },
3156
3157   /* PREFIX_0F38DE */
3158   {
3159     { "(bad)",  { XX } },
3160     { "(bad)",  { XX } },
3161     { "aesdec", { XM, EXx } },
3162     { "(bad)",  { XX } },
3163   },
3164
3165   /* PREFIX_0F38DF */
3166   {
3167     { "(bad)",  { XX } },
3168     { "(bad)",  { XX } },
3169     { "aesdeclast", { XM, EXx } },
3170     { "(bad)",  { XX } },
3171   },
3172
3173   /* PREFIX_0F38F0 */
3174   {
3175     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3176     { "(bad)",  { XX } },
3177     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3178     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3179   },
3180
3181   /* PREFIX_0F38F1 */
3182   {
3183     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3184     { "(bad)",  { XX } },
3185     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3186     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3187   },
3188
3189   /* PREFIX_0F3A08 */
3190   {
3191     { "(bad)",  { XX } },
3192     { "(bad)",  { XX } },
3193     { "roundps", { XM, EXx, Ib } },
3194     { "(bad)",  { XX } },
3195   },
3196
3197   /* PREFIX_0F3A09 */
3198   {
3199     { "(bad)",  { XX } },
3200     { "(bad)",  { XX } },
3201     { "roundpd", { XM, EXx, Ib } },
3202     { "(bad)",  { XX } },
3203   },
3204
3205   /* PREFIX_0F3A0A */
3206   {
3207     { "(bad)",  { XX } },
3208     { "(bad)",  { XX } },
3209     { "roundss", { XM, EXd, Ib } },
3210     { "(bad)",  { XX } },
3211   },
3212
3213   /* PREFIX_0F3A0B */
3214   {
3215     { "(bad)",  { XX } },
3216     { "(bad)",  { XX } },
3217     { "roundsd", { XM, EXq, Ib } },
3218     { "(bad)",  { XX } },
3219   },
3220
3221   /* PREFIX_0F3A0C */
3222   {
3223     { "(bad)",  { XX } },
3224     { "(bad)",  { XX } },
3225     { "blendps", { XM, EXx, Ib } },
3226     { "(bad)",  { XX } },
3227   },
3228
3229   /* PREFIX_0F3A0D */
3230   {
3231     { "(bad)",  { XX } },
3232     { "(bad)",  { XX } },
3233     { "blendpd", { XM, EXx, Ib } },
3234     { "(bad)",  { XX } },
3235   },
3236
3237   /* PREFIX_0F3A0E */
3238   {
3239     { "(bad)",  { XX } },
3240     { "(bad)",  { XX } },
3241     { "pblendw", { XM, EXx, Ib } },
3242     { "(bad)",  { XX } },
3243   },
3244
3245   /* PREFIX_0F3A14 */
3246   {
3247     { "(bad)",  { XX } },
3248     { "(bad)",  { XX } },
3249     { "pextrb", { Edqb, XM, Ib } },
3250     { "(bad)",  { XX } },
3251   },
3252
3253   /* PREFIX_0F3A15 */
3254   {
3255     { "(bad)",  { XX } },
3256     { "(bad)",  { XX } },
3257     { "pextrw", { Edqw, XM, Ib } },
3258     { "(bad)",  { XX } },
3259   },
3260
3261   /* PREFIX_0F3A16 */
3262   {
3263     { "(bad)",  { XX } },
3264     { "(bad)",  { XX } },
3265     { "pextrK", { Edq, XM, Ib } },
3266     { "(bad)",  { XX } },
3267   },
3268
3269   /* PREFIX_0F3A17 */
3270   {
3271     { "(bad)",  { XX } },
3272     { "(bad)",  { XX } },
3273     { "extractps", { Edqd, XM, Ib } },
3274     { "(bad)",  { XX } },
3275   },
3276
3277   /* PREFIX_0F3A20 */
3278   {
3279     { "(bad)",  { XX } },
3280     { "(bad)",  { XX } },
3281     { "pinsrb", { XM, Edqb, Ib } },
3282     { "(bad)",  { XX } },
3283   },
3284
3285   /* PREFIX_0F3A21 */
3286   {
3287     { "(bad)",  { XX } },
3288     { "(bad)",  { XX } },
3289     { "insertps", { XM, EXd, Ib } },
3290     { "(bad)",  { XX } },
3291   },
3292
3293   /* PREFIX_0F3A22 */
3294   {
3295     { "(bad)",  { XX } },
3296     { "(bad)",  { XX } },
3297     { "pinsrK", { XM, Edq, Ib } },
3298     { "(bad)",  { XX } },
3299   },
3300
3301   /* PREFIX_0F3A40 */
3302   {
3303     { "(bad)",  { XX } },
3304     { "(bad)",  { XX } },
3305     { "dpps",   { XM, EXx, Ib } },
3306     { "(bad)",  { XX } },
3307   },
3308
3309   /* PREFIX_0F3A41 */
3310   {
3311     { "(bad)",  { XX } },
3312     { "(bad)",  { XX } },
3313     { "dppd",   { XM, EXx, Ib } },
3314     { "(bad)",  { XX } },
3315   },
3316
3317   /* PREFIX_0F3A42 */
3318   {
3319     { "(bad)",  { XX } },
3320     { "(bad)",  { XX } },
3321     { "mpsadbw", { XM, EXx, Ib } },
3322     { "(bad)",  { XX } },
3323   },
3324
3325   /* PREFIX_0F3A44 */
3326   {
3327     { "(bad)",  { XX } },
3328     { "(bad)",  { XX } },
3329     { "pclmulqdq", { XM, EXx, PCLMUL } },
3330     { "(bad)",  { XX } },
3331   },
3332
3333   /* PREFIX_0F3A60 */
3334   {
3335     { "(bad)",  { XX } },
3336     { "(bad)",  { XX } },
3337     { "pcmpestrm", { XM, EXx, Ib } },
3338     { "(bad)",  { XX } },
3339   },
3340
3341   /* PREFIX_0F3A61 */
3342   {
3343     { "(bad)",  { XX } },
3344     { "(bad)",  { XX } },
3345     { "pcmpestri", { XM, EXx, Ib } },
3346     { "(bad)",  { XX } },
3347   },
3348
3349   /* PREFIX_0F3A62 */
3350   {
3351     { "(bad)",  { XX } },
3352     { "(bad)",  { XX } },
3353     { "pcmpistrm", { XM, EXx, Ib } },
3354     { "(bad)",  { XX } },
3355   },
3356
3357   /* PREFIX_0F3A63 */
3358   {
3359     { "(bad)",  { XX } },
3360     { "(bad)",  { XX } },
3361     { "pcmpistri", { XM, EXx, Ib } },
3362     { "(bad)",  { XX } },
3363   },
3364
3365   /* PREFIX_0F3ADF */
3366   {
3367     { "(bad)",  { XX } },
3368     { "(bad)",  { XX } },
3369     { "aeskeygenassist", { XM, EXx, Ib } },
3370     { "(bad)",  { XX } },
3371   },
3372
3373   /* PREFIX_VEX_10 */
3374   {
3375     { "vmovups", { XM, EXx } },
3376     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3377     { "vmovupd", { XM, EXx } },
3378     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3379   },
3380
3381   /* PREFIX_VEX_11 */
3382   {
3383     { "vmovups", { EXxS, XM } },
3384     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3385     { "vmovupd", { EXxS, XM } },
3386     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3387   },
3388
3389   /* PREFIX_VEX_12 */
3390   {
3391     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3392     { "vmovsldup", { XM, EXx } },
3393     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3394     { "vmovddup", { XM, EXymmq } },
3395   },
3396
3397   /* PREFIX_VEX_16 */
3398   {
3399     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3400     { "vmovshdup", { XM, EXx } },
3401     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3402     { "(bad)",  { XX } },
3403   },
3404
3405   /* PREFIX_VEX_2A */
3406   {
3407     { "(bad)",  { XX } },
3408     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3409     { "(bad)",  { XX } },
3410     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3411   },
3412
3413   /* PREFIX_VEX_2C */
3414   {
3415     { "(bad)",  { XX } },
3416     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3417     { "(bad)",  { XX } },
3418     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3419   },
3420
3421   /* PREFIX_VEX_2D */
3422   {
3423     { "(bad)",  { XX } },
3424     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3425     { "(bad)",  { XX } },
3426     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3427   },
3428
3429   /* PREFIX_VEX_2E */
3430   {
3431     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3432     { "(bad)",  { XX } },
3433     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3434     { "(bad)",  { XX } },
3435   },
3436
3437   /* PREFIX_VEX_2F */
3438   {
3439     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3440     { "(bad)",  { XX } },
3441     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3442     { "(bad)",  { XX } },
3443   },
3444
3445   /* PREFIX_VEX_51 */
3446   {
3447     { "vsqrtps", { XM, EXx } },
3448     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3449     { "vsqrtpd", { XM, EXx } },
3450     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3451   },
3452
3453   /* PREFIX_VEX_52 */
3454   {
3455     { "vrsqrtps", { XM, EXx } },
3456     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3457     { "(bad)",  { XX } },
3458     { "(bad)",  { XX } },
3459   },
3460
3461   /* PREFIX_VEX_53 */
3462   {
3463     { "vrcpps", { XM, EXx } },
3464     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3465     { "(bad)",  { XX } },
3466     { "(bad)",  { XX } },
3467   },
3468
3469   /* PREFIX_VEX_58 */
3470   {
3471     { "vaddps", { XM, Vex, EXx } },
3472     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3473     { "vaddpd", { XM, Vex, EXx } },
3474     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3475   },
3476
3477   /* PREFIX_VEX_59 */
3478   {
3479     { "vmulps", { XM, Vex, EXx } },
3480     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3481     { "vmulpd", { XM, Vex, EXx } },
3482     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3483   },
3484
3485   /* PREFIX_VEX_5A */
3486   {
3487     { "vcvtps2pd", { XM, EXxmmq } },
3488     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3489     { "vcvtpd2ps%XY", { XMM, EXx } },
3490     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3491   },
3492
3493   /* PREFIX_VEX_5B */
3494   {
3495     { "vcvtdq2ps", { XM, EXx } },
3496     { "vcvttps2dq", { XM, EXx } },
3497     { "vcvtps2dq", { XM, EXx } },
3498     { "(bad)",  { XX } },
3499   },
3500
3501   /* PREFIX_VEX_5C */
3502   {
3503     { "vsubps", { XM, Vex, EXx } },
3504     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3505     { "vsubpd", { XM, Vex, EXx } },
3506     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3507   },
3508
3509   /* PREFIX_VEX_5D */
3510   {
3511     { "vminps", { XM, Vex, EXx } },
3512     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3513     { "vminpd", { XM, Vex, EXx } },
3514     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3515   },
3516
3517   /* PREFIX_VEX_5E */
3518   {
3519     { "vdivps", { XM, Vex, EXx } },
3520     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3521     { "vdivpd", { XM, Vex, EXx } },
3522     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3523   },
3524
3525   /* PREFIX_VEX_5F */
3526   {
3527     { "vmaxps", { XM, Vex, EXx } },
3528     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3529     { "vmaxpd", { XM, Vex, EXx } },
3530     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3531   },
3532
3533   /* PREFIX_VEX_60 */
3534   {
3535     { "(bad)",  { XX } },
3536     { "(bad)",  { XX } },
3537     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3538     { "(bad)",  { XX } },
3539   },
3540
3541   /* PREFIX_VEX_61 */
3542   {
3543     { "(bad)",  { XX } },
3544     { "(bad)",  { XX } },
3545     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3546     { "(bad)",  { XX } },
3547   },
3548
3549   /* PREFIX_VEX_62 */
3550   {
3551     { "(bad)",  { XX } },
3552     { "(bad)",  { XX } },
3553     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3554     { "(bad)",  { XX } },
3555   },
3556
3557   /* PREFIX_VEX_63 */
3558   {
3559     { "(bad)",  { XX } },
3560     { "(bad)",  { XX } },
3561     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3562     { "(bad)",  { XX } },
3563   },
3564
3565   /* PREFIX_VEX_64 */
3566   {
3567     { "(bad)",  { XX } },
3568     { "(bad)",  { XX } },
3569     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3570     { "(bad)",  { XX } },
3571   },
3572
3573   /* PREFIX_VEX_65 */
3574   {
3575     { "(bad)",  { XX } },
3576     { "(bad)",  { XX } },
3577     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3578     { "(bad)",  { XX } },
3579   },
3580
3581   /* PREFIX_VEX_66 */
3582   {
3583     { "(bad)",  { XX } },
3584     { "(bad)",  { XX } },
3585     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3586     { "(bad)",  { XX } },
3587   },
3588
3589   /* PREFIX_VEX_67 */
3590   {
3591     { "(bad)",  { XX } },
3592     { "(bad)",  { XX } },
3593     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3594     { "(bad)",  { XX } },
3595   },
3596
3597   /* PREFIX_VEX_68 */
3598   {
3599     { "(bad)",  { XX } },
3600     { "(bad)",  { XX } },
3601     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3602     { "(bad)",  { XX } },
3603   },
3604
3605   /* PREFIX_VEX_69 */
3606   {
3607     { "(bad)",  { XX } },
3608     { "(bad)",  { XX } },
3609     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3610     { "(bad)",  { XX } },
3611   },
3612
3613   /* PREFIX_VEX_6A */
3614   {
3615     { "(bad)",  { XX } },
3616     { "(bad)",  { XX } },
3617     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3618     { "(bad)",  { XX } },
3619   },
3620
3621   /* PREFIX_VEX_6B */
3622   {
3623     { "(bad)",  { XX } },
3624     { "(bad)",  { XX } },
3625     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3626     { "(bad)",  { XX } },
3627   },
3628
3629   /* PREFIX_VEX_6C */
3630   {
3631     { "(bad)",  { XX } },
3632     { "(bad)",  { XX } },
3633     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3634     { "(bad)",  { XX } },
3635   },
3636
3637   /* PREFIX_VEX_6D */
3638   {
3639     { "(bad)",  { XX } },
3640     { "(bad)",  { XX } },
3641     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3642     { "(bad)",  { XX } },
3643   },
3644
3645   /* PREFIX_VEX_6E */
3646   {
3647     { "(bad)",  { XX } },
3648     { "(bad)",  { XX } },
3649     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3650     { "(bad)",  { XX } },
3651   },
3652
3653   /* PREFIX_VEX_6F */
3654   {
3655     { "(bad)",  { XX } },
3656     { "vmovdqu", { XM, EXx } },
3657     { "vmovdqa", { XM, EXx } },
3658     { "(bad)",  { XX } },
3659   },
3660
3661   /* PREFIX_VEX_70 */
3662   {
3663     { "(bad)",  { XX } },
3664     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3665     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3666     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3667   },
3668
3669   /* PREFIX_VEX_71_REG_2 */
3670   {
3671     { "(bad)",  { XX } },
3672     { "(bad)",  { XX } },
3673     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3674     { "(bad)",  { XX } },
3675   },
3676
3677   /* PREFIX_VEX_71_REG_4 */
3678   {
3679     { "(bad)",  { XX } },
3680     { "(bad)",  { XX } },
3681     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3682     { "(bad)",  { XX } },
3683   },
3684
3685   /* PREFIX_VEX_71_REG_6 */
3686   {
3687     { "(bad)",  { XX } },
3688     { "(bad)",  { XX } },
3689     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3690     { "(bad)",  { XX } },
3691   },
3692
3693   /* PREFIX_VEX_72_REG_2 */
3694   {
3695     { "(bad)",  { XX } },
3696     { "(bad)",  { XX } },
3697     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3698     { "(bad)",  { XX } },
3699   },
3700
3701   /* PREFIX_VEX_72_REG_4 */
3702   {
3703     { "(bad)",  { XX } },
3704     { "(bad)",  { XX } },
3705     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3706     { "(bad)",  { XX } },
3707   },
3708
3709   /* PREFIX_VEX_72_REG_6 */
3710   {
3711     { "(bad)",  { XX } },
3712     { "(bad)",  { XX } },
3713     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3714     { "(bad)",  { XX } },
3715   },
3716
3717   /* PREFIX_VEX_73_REG_2 */
3718   {
3719     { "(bad)",  { XX } },
3720     { "(bad)",  { XX } },
3721     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3722     { "(bad)",  { XX } },
3723   },
3724
3725   /* PREFIX_VEX_73_REG_3 */
3726   {
3727     { "(bad)",  { XX } },
3728     { "(bad)",  { XX } },
3729     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3730     { "(bad)",  { XX } },
3731   },
3732
3733   /* PREFIX_VEX_73_REG_6 */
3734   {
3735     { "(bad)",  { XX } },
3736     { "(bad)",  { XX } },
3737     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3738     { "(bad)",  { XX } },
3739   },
3740
3741   /* PREFIX_VEX_73_REG_7 */
3742   {
3743     { "(bad)",  { XX } },
3744     { "(bad)",  { XX } },
3745     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3746     { "(bad)",  { XX } },
3747   },
3748
3749   /* PREFIX_VEX_74 */
3750   {
3751     { "(bad)",  { XX } },
3752     { "(bad)",  { XX } },
3753     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3754     { "(bad)",  { XX } },
3755   },
3756
3757   /* PREFIX_VEX_75 */
3758   {
3759     { "(bad)",  { XX } },
3760     { "(bad)",  { XX } },
3761     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3762     { "(bad)",  { XX } },
3763   },
3764
3765   /* PREFIX_VEX_76 */
3766   {
3767     { "(bad)",  { XX } },
3768     { "(bad)",  { XX } },
3769     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3770     { "(bad)",  { XX } },
3771   },
3772
3773   /* PREFIX_VEX_77 */
3774   {
3775     { "",       { VZERO } },
3776     { "(bad)",  { XX } },
3777     { "(bad)",  { XX } },
3778     { "(bad)",  { XX } },
3779   },
3780
3781   /* PREFIX_VEX_7C */
3782   {
3783     { "(bad)",  { XX } },
3784     { "(bad)",  { XX } },
3785     { "vhaddpd", { XM, Vex, EXx } },
3786     { "vhaddps", { XM, Vex, EXx } },
3787   },
3788
3789   /* PREFIX_VEX_7D */
3790   {
3791     { "(bad)",  { XX } },
3792     { "(bad)",  { XX } },
3793     { "vhsubpd", { XM, Vex, EXx } },
3794     { "vhsubps", { XM, Vex, EXx } },
3795   },
3796
3797   /* PREFIX_VEX_7E */
3798   {
3799     { "(bad)",  { XX } },
3800     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3801     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3802     { "(bad)",  { XX } },
3803   },
3804
3805   /* PREFIX_VEX_7F */
3806   {
3807     { "(bad)",  { XX } },
3808     { "vmovdqu", { EXxS, XM } },
3809     { "vmovdqa", { EXxS, XM } },
3810     { "(bad)",  { XX } },
3811   },
3812
3813   /* PREFIX_VEX_C2 */
3814   {
3815     { "vcmpps", { XM, Vex, EXx, VCMP } },
3816     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3817     { "vcmppd", { XM, Vex, EXx, VCMP } },
3818     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3819   },
3820
3821   /* PREFIX_VEX_C4 */
3822   {
3823     { "(bad)",  { XX } },
3824     { "(bad)",  { XX } },
3825     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3826     { "(bad)",  { XX } },
3827   },
3828
3829   /* PREFIX_VEX_C5 */
3830   {
3831     { "(bad)",  { XX } },
3832     { "(bad)",  { XX } },
3833     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3834     { "(bad)",  { XX } },
3835   },
3836
3837   /* PREFIX_VEX_D0 */
3838   {
3839     { "(bad)",  { XX } },
3840     { "(bad)",  { XX } },
3841     { "vaddsubpd", { XM, Vex, EXx } },
3842     { "vaddsubps", { XM, Vex, EXx } },
3843   },
3844
3845   /* PREFIX_VEX_D1 */
3846   {
3847     { "(bad)",  { XX } },
3848     { "(bad)",  { XX } },
3849     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3850     { "(bad)",  { XX } },
3851   },
3852
3853   /* PREFIX_VEX_D2 */
3854   {
3855     { "(bad)",  { XX } },
3856     { "(bad)",  { XX } },
3857     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3858     { "(bad)",  { XX } },
3859   },
3860
3861   /* PREFIX_VEX_D3 */
3862   {
3863     { "(bad)",  { XX } },
3864     { "(bad)",  { XX } },
3865     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3866     { "(bad)",  { XX } },
3867   },
3868
3869   /* PREFIX_VEX_D4 */
3870   {
3871     { "(bad)",  { XX } },
3872     { "(bad)",  { XX } },
3873     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3874     { "(bad)",  { XX } },
3875   },
3876
3877   /* PREFIX_VEX_D5 */
3878   {
3879     { "(bad)",  { XX } },
3880     { "(bad)",  { XX } },
3881     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3882     { "(bad)",  { XX } },
3883   },
3884
3885   /* PREFIX_VEX_D6 */
3886   {
3887     { "(bad)",  { XX } },
3888     { "(bad)",  { XX } },
3889     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3890     { "(bad)",  { XX } },
3891   },
3892
3893   /* PREFIX_VEX_D7 */
3894   {
3895     { "(bad)",  { XX } },
3896     { "(bad)",  { XX } },
3897     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3898     { "(bad)",  { XX } },
3899   },
3900
3901   /* PREFIX_VEX_D8 */
3902   {
3903     { "(bad)",  { XX } },
3904     { "(bad)",  { XX } },
3905     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3906     { "(bad)",  { XX } },
3907   },
3908
3909   /* PREFIX_VEX_D9 */
3910   {
3911     { "(bad)",  { XX } },
3912     { "(bad)",  { XX } },
3913     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3914     { "(bad)",  { XX } },
3915   },
3916
3917   /* PREFIX_VEX_DA */
3918   {
3919     { "(bad)",  { XX } },
3920     { "(bad)",  { XX } },
3921     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3922     { "(bad)",  { XX } },
3923   },
3924
3925   /* PREFIX_VEX_DB */
3926   {
3927     { "(bad)",  { XX } },
3928     { "(bad)",  { XX } },
3929     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3930     { "(bad)",  { XX } },
3931   },
3932
3933   /* PREFIX_VEX_DC */
3934   {
3935     { "(bad)",  { XX } },
3936     { "(bad)",  { XX } },
3937     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3938     { "(bad)",  { XX } },
3939   },
3940
3941   /* PREFIX_VEX_DD */
3942   {
3943     { "(bad)",  { XX } },
3944     { "(bad)",  { XX } },
3945     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3946     { "(bad)",  { XX } },
3947   },
3948
3949   /* PREFIX_VEX_DE */
3950   {
3951     { "(bad)",  { XX } },
3952     { "(bad)",  { XX } },
3953     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3954     { "(bad)",  { XX } },
3955   },
3956
3957   /* PREFIX_VEX_DF */
3958   {
3959     { "(bad)",  { XX } },
3960     { "(bad)",  { XX } },
3961     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3962     { "(bad)",  { XX } },
3963   },
3964
3965   /* PREFIX_VEX_E0 */
3966   {
3967     { "(bad)",  { XX } },
3968     { "(bad)",  { XX } },
3969     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3970     { "(bad)",  { XX } },
3971   },
3972
3973   /* PREFIX_VEX_E1 */
3974   {
3975     { "(bad)",  { XX } },
3976     { "(bad)",  { XX } },
3977     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3978     { "(bad)",  { XX } },
3979   },
3980
3981   /* PREFIX_VEX_E2 */
3982   {
3983     { "(bad)",  { XX } },
3984     { "(bad)",  { XX } },
3985     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3986     { "(bad)",  { XX } },
3987   },
3988
3989   /* PREFIX_VEX_E3 */
3990   {
3991     { "(bad)",  { XX } },
3992     { "(bad)",  { XX } },
3993     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3994     { "(bad)",  { XX } },
3995   },
3996
3997   /* PREFIX_VEX_E4 */
3998   {
3999     { "(bad)",  { XX } },
4000     { "(bad)",  { XX } },
4001     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
4002     { "(bad)",  { XX } },
4003   },
4004
4005   /* PREFIX_VEX_E5 */
4006   {
4007     { "(bad)",  { XX } },
4008     { "(bad)",  { XX } },
4009     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
4010     { "(bad)",  { XX } },
4011   },
4012
4013   /* PREFIX_VEX_E6 */
4014   {
4015     { "(bad)",  { XX } },
4016     { "vcvtdq2pd", { XM, EXxmmq } },
4017     { "vcvttpd2dq%XY", { XMM, EXx } },
4018     { "vcvtpd2dq%XY", { XMM, EXx } },
4019   },
4020
4021   /* PREFIX_VEX_E7 */
4022   {
4023     { "(bad)",  { XX } },
4024     { "(bad)",  { XX } },
4025     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
4026     { "(bad)",  { XX } },
4027   },
4028
4029   /* PREFIX_VEX_E8 */
4030   {
4031     { "(bad)",  { XX } },
4032     { "(bad)",  { XX } },
4033     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
4034     { "(bad)",  { XX } },
4035   },
4036
4037   /* PREFIX_VEX_E9 */
4038   {
4039     { "(bad)",  { XX } },
4040     { "(bad)",  { XX } },
4041     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
4042     { "(bad)",  { XX } },
4043   },
4044
4045   /* PREFIX_VEX_EA */
4046   {
4047     { "(bad)",  { XX } },
4048     { "(bad)",  { XX } },
4049     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4050     { "(bad)",  { XX } },
4051   },
4052
4053   /* PREFIX_VEX_EB */
4054   {
4055     { "(bad)",  { XX } },
4056     { "(bad)",  { XX } },
4057     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4058     { "(bad)",  { XX } },
4059   },
4060
4061   /* PREFIX_VEX_EC */
4062   {
4063     { "(bad)",  { XX } },
4064     { "(bad)",  { XX } },
4065     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4066     { "(bad)",  { XX } },
4067   },
4068
4069   /* PREFIX_VEX_ED */
4070   {
4071     { "(bad)",  { XX } },
4072     { "(bad)",  { XX } },
4073     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4074     { "(bad)",  { XX } },
4075   },
4076
4077   /* PREFIX_VEX_EE */
4078   {
4079     { "(bad)",  { XX } },
4080     { "(bad)",  { XX } },
4081     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4082     { "(bad)",  { XX } },
4083   },
4084
4085   /* PREFIX_VEX_EF */
4086   {
4087     { "(bad)",  { XX } },
4088     { "(bad)",  { XX } },
4089     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4090     { "(bad)",  { XX } },
4091   },
4092
4093   /* PREFIX_VEX_F0 */
4094   {
4095     { "(bad)",  { XX } },
4096     { "(bad)",  { XX } },
4097     { "(bad)",  { XX } },
4098     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4099   },
4100
4101   /* PREFIX_VEX_F1 */
4102   {
4103     { "(bad)",  { XX } },
4104     { "(bad)",  { XX } },
4105     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4106     { "(bad)",  { XX } },
4107   },
4108
4109   /* PREFIX_VEX_F2 */
4110   {
4111     { "(bad)",  { XX } },
4112     { "(bad)",  { XX } },
4113     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4114     { "(bad)",  { XX } },
4115   },
4116
4117   /* PREFIX_VEX_F3 */
4118   {
4119     { "(bad)",  { XX } },
4120     { "(bad)",  { XX } },
4121     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4122     { "(bad)",  { XX } },
4123   },
4124
4125   /* PREFIX_VEX_F4 */
4126   {
4127     { "(bad)",  { XX } },
4128     { "(bad)",  { XX } },
4129     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4130     { "(bad)",  { XX } },
4131   },
4132
4133   /* PREFIX_VEX_F5 */
4134   {
4135     { "(bad)",  { XX } },
4136     { "(bad)",  { XX } },
4137     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4138     { "(bad)",  { XX } },
4139   },
4140
4141   /* PREFIX_VEX_F6 */
4142   {
4143     { "(bad)",  { XX } },
4144     { "(bad)",  { XX } },
4145     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4146     { "(bad)",  { XX } },
4147   },
4148
4149   /* PREFIX_VEX_F7 */
4150   {
4151     { "(bad)",  { XX } },
4152     { "(bad)",  { XX } },
4153     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4154     { "(bad)",  { XX } },
4155   },
4156
4157   /* PREFIX_VEX_F8 */
4158   {
4159     { "(bad)",  { XX } },
4160     { "(bad)",  { XX } },
4161     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4162     { "(bad)",  { XX } },
4163   },
4164
4165   /* PREFIX_VEX_F9 */
4166   {
4167     { "(bad)",  { XX } },
4168     { "(bad)",  { XX } },
4169     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4170     { "(bad)",  { XX } },
4171   },
4172
4173   /* PREFIX_VEX_FA */
4174   {
4175     { "(bad)",  { XX } },
4176     { "(bad)",  { XX } },
4177     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4178     { "(bad)",  { XX } },
4179   },
4180
4181   /* PREFIX_VEX_FB */
4182   {
4183     { "(bad)",  { XX } },
4184     { "(bad)",  { XX } },
4185     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4186     { "(bad)",  { XX } },
4187   },
4188
4189   /* PREFIX_VEX_FC */
4190   {
4191     { "(bad)",  { XX } },
4192     { "(bad)",  { XX } },
4193     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4194     { "(bad)",  { XX } },
4195   },
4196
4197   /* PREFIX_VEX_FD */
4198   {
4199     { "(bad)",  { XX } },
4200     { "(bad)",  { XX } },
4201     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4202     { "(bad)",  { XX } },
4203   },
4204
4205   /* PREFIX_VEX_FE */
4206   {
4207     { "(bad)",  { XX } },
4208     { "(bad)",  { XX } },
4209     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4210     { "(bad)",  { XX } },
4211   },
4212
4213   /* PREFIX_VEX_3800 */
4214   {
4215     { "(bad)",  { XX } },
4216     { "(bad)",  { XX } },
4217     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4218     { "(bad)",  { XX } },
4219   },
4220
4221   /* PREFIX_VEX_3801 */
4222   {
4223     { "(bad)",  { XX } },
4224     { "(bad)",  { XX } },
4225     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4226     { "(bad)",  { XX } },
4227   },
4228
4229   /* PREFIX_VEX_3802 */
4230   {
4231     { "(bad)",  { XX } },
4232     { "(bad)",  { XX } },
4233     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4234     { "(bad)",  { XX } },
4235   },
4236
4237   /* PREFIX_VEX_3803 */
4238   {
4239     { "(bad)",  { XX } },
4240     { "(bad)",  { XX } },
4241     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4242     { "(bad)",  { XX } },
4243   },
4244
4245   /* PREFIX_VEX_3804 */
4246   {
4247     { "(bad)",  { XX } },
4248     { "(bad)",  { XX } },
4249     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4250     { "(bad)",  { XX } },
4251   },
4252
4253   /* PREFIX_VEX_3805 */
4254   {
4255     { "(bad)",  { XX } },
4256     { "(bad)",  { XX } },
4257     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4258     { "(bad)",  { XX } },
4259   },
4260
4261   /* PREFIX_VEX_3806 */
4262   {
4263     { "(bad)",  { XX } },
4264     { "(bad)",  { XX } },
4265     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4266     { "(bad)",  { XX } },
4267   },
4268
4269   /* PREFIX_VEX_3807 */
4270   {
4271     { "(bad)",  { XX } },
4272     { "(bad)",  { XX } },
4273     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4274     { "(bad)",  { XX } },
4275   },
4276
4277   /* PREFIX_VEX_3808 */
4278   {
4279     { "(bad)",  { XX } },
4280     { "(bad)",  { XX } },
4281     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4282     { "(bad)",  { XX } },
4283   },
4284
4285   /* PREFIX_VEX_3809 */
4286   {
4287     { "(bad)",  { XX } },
4288     { "(bad)",  { XX } },
4289     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4290     { "(bad)",  { XX } },
4291   },
4292
4293   /* PREFIX_VEX_380A */
4294   {
4295     { "(bad)",  { XX } },
4296     { "(bad)",  { XX } },
4297     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4298     { "(bad)",  { XX } },
4299   },
4300
4301   /* PREFIX_VEX_380B */
4302   {
4303     { "(bad)",  { XX } },
4304     { "(bad)",  { XX } },
4305     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4306     { "(bad)",  { XX } },
4307   },
4308
4309   /* PREFIX_VEX_380C */
4310   {
4311     { "(bad)",  { XX } },
4312     { "(bad)",  { XX } },
4313     { "vpermilps", { XM, Vex, EXx } },
4314     { "(bad)",  { XX } },
4315   },
4316
4317   /* PREFIX_VEX_380D */
4318   {
4319     { "(bad)",  { XX } },
4320     { "(bad)",  { XX } },
4321     { "vpermilpd", { XM, Vex, EXx } },
4322     { "(bad)",  { XX } },
4323   },
4324
4325   /* PREFIX_VEX_380E */
4326   {
4327     { "(bad)",  { XX } },
4328     { "(bad)",  { XX } },
4329     { "vtestps", { XM, EXx } },
4330     { "(bad)",  { XX } },
4331   },
4332
4333   /* PREFIX_VEX_380F */
4334   {
4335     { "(bad)",  { XX } },
4336     { "(bad)",  { XX } },
4337     { "vtestpd", { XM, EXx } },
4338     { "(bad)",  { XX } },
4339   },
4340
4341   /* PREFIX_VEX_3817 */
4342   {
4343     { "(bad)",  { XX } },
4344     { "(bad)",  { XX } },
4345     { "vptest", { XM, EXx } },
4346     { "(bad)",  { XX } },
4347   },
4348
4349   /* PREFIX_VEX_3818 */
4350   {
4351     { "(bad)",  { XX } },
4352     { "(bad)",  { XX } },
4353     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4354     { "(bad)",  { XX } },
4355   },
4356
4357   /* PREFIX_VEX_3819 */
4358   {
4359     { "(bad)",  { XX } },
4360     { "(bad)",  { XX } },
4361     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4362     { "(bad)",  { XX } },
4363   },
4364
4365   /* PREFIX_VEX_381A */
4366   {
4367     { "(bad)",  { XX } },
4368     { "(bad)",  { XX } },
4369     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4370     { "(bad)",  { XX } },
4371   },
4372
4373   /* PREFIX_VEX_381C */
4374   {
4375     { "(bad)",  { XX } },
4376     { "(bad)",  { XX } },
4377     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4378     { "(bad)",  { XX } },
4379   },
4380
4381   /* PREFIX_VEX_381D */
4382   {
4383     { "(bad)",  { XX } },
4384     { "(bad)",  { XX } },
4385     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4386     { "(bad)",  { XX } },
4387   },
4388
4389   /* PREFIX_VEX_381E */
4390   {
4391     { "(bad)",  { XX } },
4392     { "(bad)",  { XX } },
4393     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4394     { "(bad)",  { XX } },
4395   },
4396
4397   /* PREFIX_VEX_3820 */
4398   {
4399     { "(bad)",  { XX } },
4400     { "(bad)",  { XX } },
4401     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4402     { "(bad)",  { XX } },
4403   },
4404
4405   /* PREFIX_VEX_3821 */
4406   {
4407     { "(bad)",  { XX } },
4408     { "(bad)",  { XX } },
4409     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4410     { "(bad)",  { XX } },
4411   },
4412
4413   /* PREFIX_VEX_3822 */
4414   {
4415     { "(bad)",  { XX } },
4416     { "(bad)",  { XX } },
4417     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4418     { "(bad)",  { XX } },
4419   },
4420
4421   /* PREFIX_VEX_3823 */
4422   {
4423     { "(bad)",  { XX } },
4424     { "(bad)",  { XX } },
4425     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4426     { "(bad)",  { XX } },
4427   },
4428
4429   /* PREFIX_VEX_3824 */
4430   {
4431     { "(bad)",  { XX } },
4432     { "(bad)",  { XX } },
4433     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4434     { "(bad)",  { XX } },
4435   },
4436
4437   /* PREFIX_VEX_3825 */
4438   {
4439     { "(bad)",  { XX } },
4440     { "(bad)",  { XX } },
4441     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4442     { "(bad)",  { XX } },
4443   },
4444
4445   /* PREFIX_VEX_3828 */
4446   {
4447     { "(bad)",  { XX } },
4448     { "(bad)",  { XX } },
4449     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4450     { "(bad)",  { XX } },
4451   },
4452
4453   /* PREFIX_VEX_3829 */
4454   {
4455     { "(bad)",  { XX } },
4456     { "(bad)",  { XX } },
4457     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4458     { "(bad)",  { XX } },
4459   },
4460
4461   /* PREFIX_VEX_382A */
4462   {
4463     { "(bad)",  { XX } },
4464     { "(bad)",  { XX } },
4465     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4466     { "(bad)",  { XX } },
4467   },
4468
4469   /* PREFIX_VEX_382B */
4470   {
4471     { "(bad)",  { XX } },
4472     { "(bad)",  { XX } },
4473     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4474     { "(bad)",  { XX } },
4475   },
4476
4477   /* PREFIX_VEX_382C */
4478   {
4479     { "(bad)",  { XX } },
4480     { "(bad)",  { XX } },
4481      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4482     { "(bad)",  { XX } },
4483   },
4484
4485   /* PREFIX_VEX_382D */
4486   {
4487     { "(bad)",  { XX } },
4488     { "(bad)",  { XX } },
4489      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4490     { "(bad)",  { XX } },
4491   },
4492
4493   /* PREFIX_VEX_382E */
4494   {
4495     { "(bad)",  { XX } },
4496     { "(bad)",  { XX } },
4497      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4498     { "(bad)",  { XX } },
4499   },
4500
4501   /* PREFIX_VEX_382F */
4502   {
4503     { "(bad)",  { XX } },
4504     { "(bad)",  { XX } },
4505      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4506     { "(bad)",  { XX } },
4507   },
4508
4509   /* PREFIX_VEX_3830 */
4510   {
4511     { "(bad)",  { XX } },
4512     { "(bad)",  { XX } },
4513     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4514     { "(bad)",  { XX } },
4515   },
4516
4517   /* PREFIX_VEX_3831 */
4518   {
4519     { "(bad)",  { XX } },
4520     { "(bad)",  { XX } },
4521     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4522     { "(bad)",  { XX } },
4523   },
4524
4525   /* PREFIX_VEX_3832 */
4526   {
4527     { "(bad)",  { XX } },
4528     { "(bad)",  { XX } },
4529     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4530     { "(bad)",  { XX } },
4531   },
4532
4533   /* PREFIX_VEX_3833 */
4534   {
4535     { "(bad)",  { XX } },
4536     { "(bad)",  { XX } },
4537     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4538     { "(bad)",  { XX } },
4539   },
4540
4541   /* PREFIX_VEX_3834 */
4542   {
4543     { "(bad)",  { XX } },
4544     { "(bad)",  { XX } },
4545     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4546     { "(bad)",  { XX } },
4547   },
4548
4549   /* PREFIX_VEX_3835 */
4550   {
4551     { "(bad)",  { XX } },
4552     { "(bad)",  { XX } },
4553     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4554     { "(bad)",  { XX } },
4555   },
4556
4557   /* PREFIX_VEX_3837 */
4558   {
4559     { "(bad)",  { XX } },
4560     { "(bad)",  { XX } },
4561     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4562     { "(bad)",  { XX } },
4563   },
4564
4565   /* PREFIX_VEX_3838 */
4566   {
4567     { "(bad)",  { XX } },
4568     { "(bad)",  { XX } },
4569     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4570     { "(bad)",  { XX } },
4571   },
4572
4573   /* PREFIX_VEX_3839 */
4574   {
4575     { "(bad)",  { XX } },
4576     { "(bad)",  { XX } },
4577     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4578     { "(bad)",  { XX } },
4579   },
4580
4581   /* PREFIX_VEX_383A */
4582   {
4583     { "(bad)",  { XX } },
4584     { "(bad)",  { XX } },
4585     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4586     { "(bad)",  { XX } },
4587   },
4588
4589   /* PREFIX_VEX_383B */
4590   {
4591     { "(bad)",  { XX } },
4592     { "(bad)",  { XX } },
4593     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4594     { "(bad)",  { XX } },
4595   },
4596
4597   /* PREFIX_VEX_383C */
4598   {
4599     { "(bad)",  { XX } },
4600     { "(bad)",  { XX } },
4601     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4602     { "(bad)",  { XX } },
4603   },
4604
4605   /* PREFIX_VEX_383D */
4606   {
4607     { "(bad)",  { XX } },
4608     { "(bad)",  { XX } },
4609     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4610     { "(bad)",  { XX } },
4611   },
4612
4613   /* PREFIX_VEX_383E */
4614   {
4615     { "(bad)",  { XX } },
4616     { "(bad)",  { XX } },
4617     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4618     { "(bad)",  { XX } },
4619   },
4620
4621   /* PREFIX_VEX_383F */
4622   {
4623     { "(bad)",  { XX } },
4624     { "(bad)",  { XX } },
4625     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4626     { "(bad)",  { XX } },
4627   },
4628
4629   /* PREFIX_VEX_3840 */
4630   {
4631     { "(bad)",  { XX } },
4632     { "(bad)",  { XX } },
4633     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4634     { "(bad)",  { XX } },
4635   },
4636
4637   /* PREFIX_VEX_3841 */
4638   {
4639     { "(bad)",  { XX } },
4640     { "(bad)",  { XX } },
4641     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4642     { "(bad)",  { XX } },
4643   },
4644
4645   /* PREFIX_VEX_3896 */
4646   {
4647     { "(bad)",  { XX } },
4648     { "(bad)",  { XX } },
4649     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4650     { "(bad)",  { XX } },
4651   },
4652
4653   /* PREFIX_VEX_3897 */
4654   {
4655     { "(bad)",  { XX } },
4656     { "(bad)",  { XX } },
4657     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4658     { "(bad)",  { XX } },
4659   },
4660
4661   /* PREFIX_VEX_3898 */
4662   {
4663     { "(bad)",  { XX } },
4664     { "(bad)",  { XX } },
4665     { "vfmadd132p%XW", { XM, Vex, EXx } },
4666     { "(bad)",  { XX } },
4667   },
4668
4669   /* PREFIX_VEX_3899 */
4670   {
4671     { "(bad)",  { XX } },
4672     { "(bad)",  { XX } },
4673     { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
4674     { "(bad)",  { XX } },
4675   },
4676
4677   /* PREFIX_VEX_389A */
4678   {
4679     { "(bad)",  { XX } },
4680     { "(bad)",  { XX } },
4681     { "vfmsub132p%XW", { XM, Vex, EXx } },
4682     { "(bad)",  { XX } },
4683   },
4684
4685   /* PREFIX_VEX_389B */
4686   {
4687     { "(bad)",  { XX } },
4688     { "(bad)",  { XX } },
4689     { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
4690     { "(bad)",  { XX } },
4691   },
4692
4693   /* PREFIX_VEX_389C */
4694   {
4695     { "(bad)",  { XX } },
4696     { "(bad)",  { XX } },
4697     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4698     { "(bad)",  { XX } },
4699   },
4700
4701   /* PREFIX_VEX_389D */
4702   {
4703     { "(bad)",  { XX } },
4704     { "(bad)",  { XX } },
4705     { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
4706     { "(bad)",  { XX } },
4707   },
4708
4709   /* PREFIX_VEX_389E */
4710   {
4711     { "(bad)",  { XX } },
4712     { "(bad)",  { XX } },
4713     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4714     { "(bad)",  { XX } },
4715   },
4716
4717   /* PREFIX_VEX_389F */
4718   {
4719     { "(bad)",  { XX } },
4720     { "(bad)",  { XX } },
4721     { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
4722     { "(bad)",  { XX } },
4723   },
4724
4725   /* PREFIX_VEX_38A6 */
4726   {
4727     { "(bad)",  { XX } },
4728     { "(bad)",  { XX } },
4729     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4730     { "(bad)",  { XX } },
4731   },
4732
4733   /* PREFIX_VEX_38A7 */
4734   {
4735     { "(bad)",  { XX } },
4736     { "(bad)",  { XX } },
4737     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4738     { "(bad)",  { XX } },
4739   },
4740
4741   /* PREFIX_VEX_38A8 */
4742   {
4743     { "(bad)",  { XX } },
4744     { "(bad)",  { XX } },
4745     { "vfmadd213p%XW", { XM, Vex, EXx } },
4746     { "(bad)",  { XX } },
4747   },
4748
4749   /* PREFIX_VEX_38A9 */
4750   {
4751     { "(bad)",  { XX } },
4752     { "(bad)",  { XX } },
4753     { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
4754     { "(bad)",  { XX } },
4755   },
4756
4757   /* PREFIX_VEX_38AA */
4758   {
4759     { "(bad)",  { XX } },
4760     { "(bad)",  { XX } },
4761     { "vfmsub213p%XW", { XM, Vex, EXx } },
4762     { "(bad)",  { XX } },
4763   },
4764
4765   /* PREFIX_VEX_38AB */
4766   {
4767     { "(bad)",  { XX } },
4768     { "(bad)",  { XX } },
4769     { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
4770     { "(bad)",  { XX } },
4771   },
4772
4773   /* PREFIX_VEX_38AC */
4774   {
4775     { "(bad)",  { XX } },
4776     { "(bad)",  { XX } },
4777     { "vfnmadd213p%XW", { XM, Vex, EXx } },
4778     { "(bad)",  { XX } },
4779   },
4780
4781   /* PREFIX_VEX_38AD */
4782   {
4783     { "(bad)",  { XX } },
4784     { "(bad)",  { XX } },
4785     { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
4786     { "(bad)",  { XX } },
4787   },
4788
4789   /* PREFIX_VEX_38AE */
4790   {
4791     { "(bad)",  { XX } },
4792     { "(bad)",  { XX } },
4793     { "vfnmsub213p%XW", { XM, Vex, EXx } },
4794     { "(bad)",  { XX } },
4795   },
4796
4797   /* PREFIX_VEX_38AF */
4798   {
4799     { "(bad)",  { XX } },
4800     { "(bad)",  { XX } },
4801     { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
4802     { "(bad)",  { XX } },
4803   },
4804
4805   /* PREFIX_VEX_38B6 */
4806   {
4807     { "(bad)",  { XX } },
4808     { "(bad)",  { XX } },
4809     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4810     { "(bad)",  { XX } },
4811   },
4812
4813   /* PREFIX_VEX_38B7 */
4814   {
4815     { "(bad)",  { XX } },
4816     { "(bad)",  { XX } },
4817     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4818     { "(bad)",  { XX } },
4819   },
4820
4821   /* PREFIX_VEX_38B8 */
4822   {
4823     { "(bad)",  { XX } },
4824     { "(bad)",  { XX } },
4825     { "vfmadd231p%XW", { XM, Vex, EXx } },
4826     { "(bad)",  { XX } },
4827   },
4828
4829   /* PREFIX_VEX_38B9 */
4830   {
4831     { "(bad)",  { XX } },
4832     { "(bad)",  { XX } },
4833     { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
4834     { "(bad)",  { XX } },
4835   },
4836
4837   /* PREFIX_VEX_38BA */
4838   {
4839     { "(bad)",  { XX } },
4840     { "(bad)",  { XX } },
4841     { "vfmsub231p%XW", { XM, Vex, EXx } },
4842     { "(bad)",  { XX } },
4843   },
4844
4845   /* PREFIX_VEX_38BB */
4846   {
4847     { "(bad)",  { XX } },
4848     { "(bad)",  { XX } },
4849     { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
4850     { "(bad)",  { XX } },
4851   },
4852
4853   /* PREFIX_VEX_38BC */
4854   {
4855     { "(bad)",  { XX } },
4856     { "(bad)",  { XX } },
4857     { "vfnmadd231p%XW", { XM, Vex, EXx } },
4858     { "(bad)",  { XX } },
4859   },
4860
4861   /* PREFIX_VEX_38BD */
4862   {
4863     { "(bad)",  { XX } },
4864     { "(bad)",  { XX } },
4865     { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
4866     { "(bad)",  { XX } },
4867   },
4868
4869   /* PREFIX_VEX_38BE */
4870   {
4871     { "(bad)",  { XX } },
4872     { "(bad)",  { XX } },
4873     { "vfnmsub231p%XW", { XM, Vex, EXx } },
4874     { "(bad)",  { XX } },
4875   },
4876
4877   /* PREFIX_VEX_38BF */
4878   {
4879     { "(bad)",  { XX } },
4880     { "(bad)",  { XX } },
4881     { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
4882     { "(bad)",  { XX } },
4883   },
4884
4885   /* PREFIX_VEX_38DB */
4886   {
4887     { "(bad)",  { XX } },
4888     { "(bad)",  { XX } },
4889     { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4890     { "(bad)",  { XX } },
4891   },
4892
4893   /* PREFIX_VEX_38DC */
4894   {
4895     { "(bad)",  { XX } },
4896     { "(bad)",  { XX } },
4897     { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4898     { "(bad)",  { XX } },
4899   },
4900
4901   /* PREFIX_VEX_38DD */
4902   {
4903     { "(bad)",  { XX } },
4904     { "(bad)",  { XX } },
4905     { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4906     { "(bad)",  { XX } },
4907   },
4908
4909   /* PREFIX_VEX_38DE */
4910   {
4911     { "(bad)",  { XX } },
4912     { "(bad)",  { XX } },
4913     { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4914     { "(bad)",  { XX } },
4915   },
4916
4917   /* PREFIX_VEX_38DF */
4918   {
4919     { "(bad)",  { XX } },
4920     { "(bad)",  { XX } },
4921     { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4922     { "(bad)",  { XX } },
4923   },
4924
4925   /* PREFIX_VEX_3A04 */
4926   {
4927     { "(bad)",  { XX } },
4928     { "(bad)",  { XX } },
4929     { "vpermilps", { XM, EXx, Ib } },
4930     { "(bad)",  { XX } },
4931   },
4932
4933   /* PREFIX_VEX_3A05 */
4934   {
4935     { "(bad)",  { XX } },
4936     { "(bad)",  { XX } },
4937     { "vpermilpd", { XM, EXx, Ib } },
4938     { "(bad)",  { XX } },
4939   },
4940
4941   /* PREFIX_VEX_3A06 */
4942   {
4943     { "(bad)",  { XX } },
4944     { "(bad)",  { XX } },
4945     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4946     { "(bad)",  { XX } },
4947   },
4948
4949   /* PREFIX_VEX_3A08 */
4950   {
4951     { "(bad)",  { XX } },
4952     { "(bad)",  { XX } },
4953     { "vroundps", { XM, EXx, Ib } },
4954     { "(bad)",  { XX } },
4955   },
4956
4957   /* PREFIX_VEX_3A09 */
4958   {
4959     { "(bad)",  { XX } },
4960     { "(bad)",  { XX } },
4961     { "vroundpd", { XM, EXx, Ib } },
4962     { "(bad)",  { XX } },
4963   },
4964
4965   /* PREFIX_VEX_3A0A */
4966   {
4967     { "(bad)",  { XX } },
4968     { "(bad)",  { XX } },
4969     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4970     { "(bad)",  { XX } },
4971   },
4972
4973   /* PREFIX_VEX_3A0B */
4974   {
4975     { "(bad)",  { XX } },
4976     { "(bad)",  { XX } },
4977     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4978     { "(bad)",  { XX } },
4979   },
4980
4981   /* PREFIX_VEX_3A0C */
4982   {
4983     { "(bad)",  { XX } },
4984     { "(bad)",  { XX } },
4985     { "vblendps", { XM, Vex, EXx, Ib } },
4986     { "(bad)",  { XX } },
4987   },
4988
4989   /* PREFIX_VEX_3A0D */
4990   {
4991     { "(bad)",  { XX } },
4992     { "(bad)",  { XX } },
4993     { "vblendpd", { XM, Vex, EXx, Ib } },
4994     { "(bad)",  { XX } },
4995   },
4996
4997   /* PREFIX_VEX_3A0E */
4998   {
4999     { "(bad)",  { XX } },
5000     { "(bad)",  { XX } },
5001     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
5002     { "(bad)",  { XX } },
5003   },
5004
5005   /* PREFIX_VEX_3A0F */
5006   {
5007     { "(bad)",  { XX } },
5008     { "(bad)",  { XX } },
5009     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
5010     { "(bad)",  { XX } },
5011   },
5012
5013   /* PREFIX_VEX_3A14 */
5014   {
5015     { "(bad)",  { XX } },
5016     { "(bad)",  { XX } },
5017     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
5018     { "(bad)",  { XX } },
5019   },
5020
5021   /* PREFIX_VEX_3A15 */
5022   {
5023     { "(bad)",  { XX } },
5024     { "(bad)",  { XX } },
5025     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
5026     { "(bad)",  { XX } },
5027   },
5028
5029   /* PREFIX_VEX_3A16 */
5030   {
5031     { "(bad)",  { XX } },
5032     { "(bad)",  { XX } },
5033     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
5034     { "(bad)",  { XX } },
5035   },
5036
5037   /* PREFIX_VEX_3A17 */
5038   {
5039     { "(bad)",  { XX } },
5040     { "(bad)",  { XX } },
5041     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
5042     { "(bad)",  { XX } },
5043   },
5044
5045   /* PREFIX_VEX_3A18 */
5046   {
5047     { "(bad)",  { XX } },
5048     { "(bad)",  { XX } },
5049     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
5050     { "(bad)",  { XX } },
5051   },
5052
5053   /* PREFIX_VEX_3A19 */
5054   {
5055     { "(bad)",  { XX } },
5056     { "(bad)",  { XX } },
5057     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
5058     { "(bad)",  { XX } },
5059   },
5060
5061   /* PREFIX_VEX_3A20 */
5062   {
5063     { "(bad)",  { XX } },
5064     { "(bad)",  { XX } },
5065     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
5066     { "(bad)",  { XX } },
5067   },
5068
5069   /* PREFIX_VEX_3A21 */
5070   {
5071     { "(bad)",  { XX } },
5072     { "(bad)",  { XX } },
5073     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
5074     { "(bad)",  { XX } },
5075   },
5076
5077   /* PREFIX_VEX_3A22 */
5078   {
5079     { "(bad)",  { XX } },
5080     { "(bad)",  { XX } },
5081     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5082     { "(bad)",  { XX } },
5083   },
5084
5085   /* PREFIX_VEX_3A40 */
5086   {
5087     { "(bad)",  { XX } },
5088     { "(bad)",  { XX } },
5089     { "vdpps",  { XM, Vex, EXx, Ib } },
5090     { "(bad)",  { XX } },
5091   },
5092
5093   /* PREFIX_VEX_3A41 */
5094   {
5095     { "(bad)",  { XX } },
5096     { "(bad)",  { XX } },
5097     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5098     { "(bad)",  { XX } },
5099   },
5100
5101   /* PREFIX_VEX_3A42 */
5102   {
5103     { "(bad)",  { XX } },
5104     { "(bad)",  { XX } },
5105     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5106     { "(bad)",  { XX } },
5107   },
5108
5109   /* PREFIX_VEX_3A44 */
5110   {
5111     { "(bad)",  { XX } },
5112     { "(bad)",  { XX } },
5113     { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5114     { "(bad)",  { XX } },
5115   },
5116
5117   /* PREFIX_VEX_3A4A */
5118   {
5119     { "(bad)",  { XX } },
5120     { "(bad)",  { XX } },
5121     { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
5122     { "(bad)",  { XX } },
5123   },
5124
5125   /* PREFIX_VEX_3A4B */
5126   {
5127     { "(bad)",  { XX } },
5128     { "(bad)",  { XX } },
5129     { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
5130     { "(bad)",  { XX } },
5131   },
5132
5133   /* PREFIX_VEX_3A4C */
5134   {
5135     { "(bad)",  { XX } },
5136     { "(bad)",  { XX } },
5137     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5138     { "(bad)",  { XX } },
5139   },
5140
5141   /* PREFIX_VEX_3A5C */
5142   {
5143     { "(bad)",  { XX } },
5144     { "(bad)",  { XX } },
5145     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5146     { "(bad)",  { XX } },
5147   },
5148
5149   /* PREFIX_VEX_3A5D */
5150   {
5151     { "(bad)",  { XX } },
5152     { "(bad)",  { XX } },
5153     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5154     { "(bad)",  { XX } },
5155   },
5156
5157   /* PREFIX_VEX_3A5E */
5158   {
5159     { "(bad)",  { XX } },
5160     { "(bad)",  { XX } },
5161     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5162     { "(bad)",  { XX } },
5163   },
5164
5165   /* PREFIX_VEX_3A5F */
5166   {
5167     { "(bad)",  { XX } },
5168     { "(bad)",  { XX } },
5169     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5170     { "(bad)",  { XX } },
5171   },
5172
5173   /* PREFIX_VEX_3A60 */
5174   {
5175     { "(bad)",  { XX } },
5176     { "(bad)",  { XX } },
5177     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5178     { "(bad)",  { XX } },
5179   },
5180
5181   /* PREFIX_VEX_3A61 */
5182   {
5183     { "(bad)",  { XX } },
5184     { "(bad)",  { XX } },
5185     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5186     { "(bad)",  { XX } },
5187   },
5188
5189   /* PREFIX_VEX_3A62 */
5190   {
5191     { "(bad)",  { XX } },
5192     { "(bad)",  { XX } },
5193     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5194     { "(bad)",  { XX } },
5195   },
5196
5197   /* PREFIX_VEX_3A63 */
5198   {
5199     { "(bad)",  { XX } },
5200     { "(bad)",  { XX } },
5201     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5202     { "(bad)",  { XX } },
5203   },
5204
5205   /* PREFIX_VEX_3A68 */
5206   {
5207     { "(bad)",  { XX } },
5208     { "(bad)",  { XX } },
5209     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5210     { "(bad)",  { XX } },
5211   },
5212
5213   /* PREFIX_VEX_3A69 */
5214   {
5215     { "(bad)",  { XX } },
5216     { "(bad)",  { XX } },
5217     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5218     { "(bad)",  { XX } },
5219   },
5220
5221   /* PREFIX_VEX_3A6A */
5222   {
5223     { "(bad)",  { XX } },
5224     { "(bad)",  { XX } },
5225     { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5226     { "(bad)",  { XX } },
5227   },
5228
5229   /* PREFIX_VEX_3A6B */
5230   {
5231     { "(bad)",  { XX } },
5232     { "(bad)",  { XX } },
5233     { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5234     { "(bad)",  { XX } },
5235   },
5236
5237   /* PREFIX_VEX_3A6C */
5238   {
5239     { "(bad)",  { XX } },
5240     { "(bad)",  { XX } },
5241     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5242     { "(bad)",  { XX } },
5243   },
5244
5245   /* PREFIX_VEX_3A6D */
5246   {
5247     { "(bad)",  { XX } },
5248     { "(bad)",  { XX } },
5249     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5250     { "(bad)",  { XX } },
5251   },
5252
5253   /* PREFIX_VEX_3A6E */
5254   {
5255     { "(bad)",  { XX } },
5256     { "(bad)",  { XX } },
5257     { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5258     { "(bad)",  { XX } },
5259   },
5260
5261   /* PREFIX_VEX_3A6F */
5262   {
5263     { "(bad)",  { XX } },
5264     { "(bad)",  { XX } },
5265     { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5266     { "(bad)",  { XX } },
5267   },
5268
5269   /* PREFIX_VEX_3A78 */
5270   {
5271     { "(bad)",  { XX } },
5272     { "(bad)",  { XX } },
5273     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5274     { "(bad)",  { XX } },
5275   },
5276
5277   /* PREFIX_VEX_3A79 */
5278   {
5279     { "(bad)",  { XX } },
5280     { "(bad)",  { XX } },
5281     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5282     { "(bad)",  { XX } },
5283   },
5284
5285   /* PREFIX_VEX_3A7A */
5286   {
5287     { "(bad)",  { XX } },
5288     { "(bad)",  { XX } },
5289     { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5290     { "(bad)",  { XX } },
5291   },
5292
5293   /* PREFIX_VEX_3A7B */
5294   {
5295     { "(bad)",  { XX } },
5296     { "(bad)",  { XX } },
5297     { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5298     { "(bad)",  { XX } },
5299   },
5300
5301   /* PREFIX_VEX_3A7C */
5302   {
5303     { "(bad)",  { XX } },
5304     { "(bad)",  { XX } },
5305     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5306     { "(bad)",  { XX } },
5307   },
5308
5309   /* PREFIX_VEX_3A7D */
5310   {
5311     { "(bad)",  { XX } },
5312     { "(bad)",  { XX } },
5313     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5314     { "(bad)",  { XX } },
5315   },
5316
5317   /* PREFIX_VEX_3A7E */
5318   {
5319     { "(bad)",  { XX } },
5320     { "(bad)",  { XX } },
5321     { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5322     { "(bad)",  { XX } },
5323   },
5324
5325   /* PREFIX_VEX_3A7F */
5326   {
5327     { "(bad)",  { XX } },
5328     { "(bad)",  { XX } },
5329     { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5330     { "(bad)",  { XX } },
5331   },
5332
5333   /* PREFIX_VEX_3ADF */
5334   {
5335     { "(bad)",  { XX } },
5336     { "(bad)",  { XX } },
5337     { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5338     { "(bad)",  { XX } },
5339   },
5340 };
5341
5342 static const struct dis386 x86_64_table[][2] = {
5343   /* X86_64_06 */
5344   {
5345     { "push{T|}", { es } },
5346     { "(bad)", { XX } },
5347   },
5348
5349   /* X86_64_07 */
5350   {
5351     { "pop{T|}", { es } },
5352     { "(bad)", { XX } },
5353   },
5354
5355   /* X86_64_0D */
5356   {
5357     { "push{T|}", { cs } },
5358     { "(bad)", { XX } },
5359   },
5360
5361   /* X86_64_16 */
5362   {
5363     { "push{T|}", { ss } },
5364     { "(bad)", { XX } },
5365   },
5366
5367   /* X86_64_17 */
5368   {
5369     { "pop{T|}", { ss } },
5370     { "(bad)", { XX } },
5371   },
5372
5373   /* X86_64_1E */
5374   {
5375     { "push{T|}", { ds } },
5376     { "(bad)", { XX } },
5377   },
5378
5379   /* X86_64_1F */
5380   {
5381     { "pop{T|}", { ds } },
5382     { "(bad)", { XX } },
5383   },
5384
5385   /* X86_64_27 */
5386   {
5387     { "daa", { XX } },
5388     { "(bad)", { XX } },
5389   },
5390
5391   /* X86_64_2F */
5392   {
5393     { "das", { XX } },
5394     { "(bad)", { XX } },
5395   },
5396
5397   /* X86_64_37 */
5398   {
5399     { "aaa", { XX } },
5400     { "(bad)", { XX } },
5401   },
5402
5403   /* X86_64_3F */
5404   {
5405     { "aas", { XX } },
5406     { "(bad)", { XX } },
5407   },
5408
5409   /* X86_64_60 */
5410   {
5411     { "pusha{P|}", { XX } },
5412     { "(bad)", { XX } },
5413   },
5414
5415   /* X86_64_61 */
5416   {
5417     { "popa{P|}", { XX } },
5418     { "(bad)", { XX } },
5419   },
5420
5421   /* X86_64_62 */
5422   {
5423     { MOD_TABLE (MOD_62_32BIT) },
5424     { "(bad)", { XX } },
5425   },
5426
5427   /* X86_64_63 */
5428   {
5429     { "arpl", { Ew, Gw } },
5430     { "movs{lq|xd}", { Gv, Ed } },
5431   },
5432
5433   /* X86_64_6D */
5434   {
5435     { "ins{R|}", { Yzr, indirDX } },
5436     { "ins{G|}", { Yzr, indirDX } },
5437   },
5438
5439   /* X86_64_6F */
5440   {
5441     { "outs{R|}", { indirDXr, Xz } },
5442     { "outs{G|}", { indirDXr, Xz } },
5443   },
5444
5445   /* X86_64_9A */
5446   {
5447     { "Jcall{T|}", { Ap } },
5448     { "(bad)", { XX } },
5449   },
5450
5451   /* X86_64_C4 */
5452   {
5453     { MOD_TABLE (MOD_C4_32BIT) },
5454     { VEX_C4_TABLE (VEX_0F) },
5455   },
5456
5457   /* X86_64_C5 */
5458   {
5459     { MOD_TABLE (MOD_C5_32BIT) },
5460     { VEX_C5_TABLE (VEX_0F) },
5461   },
5462
5463   /* X86_64_CE */
5464   {
5465     { "into", { XX } },
5466     { "(bad)", { XX } },
5467   },
5468
5469   /* X86_64_D4 */
5470   {
5471     { "aam", { sIb } },
5472     { "(bad)", { XX } },
5473   },
5474
5475   /* X86_64_D5 */
5476   {
5477     { "aad", { sIb } },
5478     { "(bad)", { XX } },
5479   },
5480
5481   /* X86_64_EA */
5482   {
5483     { "Jjmp{T|}", { Ap } },
5484     { "(bad)", { XX } },
5485   },
5486
5487   /* X86_64_0F01_REG_0 */
5488   {
5489     { "sgdt{Q|IQ}", { M } },
5490     { "sgdt", { M } },
5491   },
5492
5493   /* X86_64_0F01_REG_1 */
5494   {
5495     { "sidt{Q|IQ}", { M } },
5496     { "sidt", { M } },
5497   },
5498
5499   /* X86_64_0F01_REG_2 */
5500   {
5501     { "lgdt{Q|Q}", { M } },
5502     { "lgdt", { M } },
5503   },
5504
5505   /* X86_64_0F01_REG_3 */
5506   {
5507     { "lidt{Q|Q}", { M } },
5508     { "lidt", { M } },
5509   },
5510 };
5511
5512 static const struct dis386 three_byte_table[][256] = {
5513
5514   /* THREE_BYTE_0F38 */
5515   {
5516     /* 00 */
5517     { "pshufb",         { MX, EM } },
5518     { "phaddw",         { MX, EM } },
5519     { "phaddd",         { MX, EM } },
5520     { "phaddsw",        { MX, EM } },
5521     { "pmaddubsw",      { MX, EM } },
5522     { "phsubw",         { MX, EM } },
5523     { "phsubd",         { MX, EM } },
5524     { "phsubsw",        { MX, EM } },
5525     /* 08 */
5526     { "psignb",         { MX, EM } },
5527     { "psignw",         { MX, EM } },
5528     { "psignd",         { MX, EM } },
5529     { "pmulhrsw",       { MX, EM } },
5530     { "(bad)",          { XX } },
5531     { "(bad)",          { XX } },
5532     { "(bad)",          { XX } },
5533     { "(bad)",          { XX } },
5534     /* 10 */
5535     { PREFIX_TABLE (PREFIX_0F3810) },
5536     { "(bad)",          { XX } },
5537     { "(bad)",          { XX } },
5538     { "(bad)",          { XX } },
5539     { PREFIX_TABLE (PREFIX_0F3814) },
5540     { PREFIX_TABLE (PREFIX_0F3815) },
5541     { "(bad)",          { XX } },
5542     { PREFIX_TABLE (PREFIX_0F3817) },
5543     /* 18 */
5544     { "(bad)",          { XX } },
5545     { "(bad)",          { XX } },
5546     { "(bad)",          { XX } },
5547     { "(bad)",          { XX } },
5548     { "pabsb",          { MX, EM } },
5549     { "pabsw",          { MX, EM } },
5550     { "pabsd",          { MX, EM } },
5551     { "(bad)",          { XX } },
5552     /* 20 */
5553     { PREFIX_TABLE (PREFIX_0F3820) },
5554     { PREFIX_TABLE (PREFIX_0F3821) },
5555     { PREFIX_TABLE (PREFIX_0F3822) },
5556     { PREFIX_TABLE (PREFIX_0F3823) },
5557     { PREFIX_TABLE (PREFIX_0F3824) },
5558     { PREFIX_TABLE (PREFIX_0F3825) },
5559     { "(bad)",          { XX } },
5560     { "(bad)",          { XX } },
5561     /* 28 */
5562     { PREFIX_TABLE (PREFIX_0F3828) },
5563     { PREFIX_TABLE (PREFIX_0F3829) },
5564     { PREFIX_TABLE (PREFIX_0F382A) },
5565     { PREFIX_TABLE (PREFIX_0F382B) },
5566     { "(bad)",          { XX } },
5567     { "(bad)",          { XX } },
5568     { "(bad)",          { XX } },
5569     { "(bad)",          { XX } },
5570     /* 30 */
5571     { PREFIX_TABLE (PREFIX_0F3830) },
5572     { PREFIX_TABLE (PREFIX_0F3831) },
5573     { PREFIX_TABLE (PREFIX_0F3832) },
5574     { PREFIX_TABLE (PREFIX_0F3833) },
5575     { PREFIX_TABLE (PREFIX_0F3834) },
5576     { PREFIX_TABLE (PREFIX_0F3835) },
5577     { "(bad)",          { XX } },
5578     { PREFIX_TABLE (PREFIX_0F3837) },
5579     /* 38 */
5580     { PREFIX_TABLE (PREFIX_0F3838) },
5581     { PREFIX_TABLE (PREFIX_0F3839) },
5582     { PREFIX_TABLE (PREFIX_0F383A) },
5583     { PREFIX_TABLE (PREFIX_0F383B) },
5584     { PREFIX_TABLE (PREFIX_0F383C) },
5585     { PREFIX_TABLE (PREFIX_0F383D) },
5586     { PREFIX_TABLE (PREFIX_0F383E) },
5587     { PREFIX_TABLE (PREFIX_0F383F) },
5588     /* 40 */
5589     { PREFIX_TABLE (PREFIX_0F3840) },
5590     { PREFIX_TABLE (PREFIX_0F3841) },
5591     { "(bad)",          { XX } },
5592     { "(bad)",          { XX } },
5593     { "(bad)",          { XX } },
5594     { "(bad)",          { XX } },
5595     { "(bad)",          { XX } },
5596     { "(bad)",          { XX } },
5597     /* 48 */
5598     { "(bad)",          { XX } },
5599     { "(bad)",          { XX } },
5600     { "(bad)",          { XX } },
5601     { "(bad)",          { XX } },
5602     { "(bad)",          { XX } },
5603     { "(bad)",          { XX } },
5604     { "(bad)",          { XX } },
5605     { "(bad)",          { XX } },
5606     /* 50 */
5607     { "(bad)",          { XX } },
5608     { "(bad)",          { XX } },
5609     { "(bad)",          { XX } },
5610     { "(bad)",          { XX } },
5611     { "(bad)",          { XX } },
5612     { "(bad)",          { XX } },
5613     { "(bad)",          { XX } },
5614     { "(bad)",          { XX } },
5615     /* 58 */
5616     { "(bad)",          { XX } },
5617     { "(bad)",          { XX } },
5618     { "(bad)",          { XX } },
5619     { "(bad)",          { XX } },
5620     { "(bad)",          { XX } },
5621     { "(bad)",          { XX } },
5622     { "(bad)",          { XX } },
5623     { "(bad)",          { XX } },
5624     /* 60 */
5625     { "(bad)",          { XX } },
5626     { "(bad)",          { XX } },
5627     { "(bad)",          { XX } },
5628     { "(bad)",          { XX } },
5629     { "(bad)",          { XX } },
5630     { "(bad)",          { XX } },
5631     { "(bad)",          { XX } },
5632     { "(bad)",          { XX } },
5633     /* 68 */
5634     { "(bad)",          { XX } },
5635     { "(bad)",          { XX } },
5636     { "(bad)",          { XX } },
5637     { "(bad)",          { XX } },
5638     { "(bad)",          { XX } },
5639     { "(bad)",          { XX } },
5640     { "(bad)",          { XX } },
5641     { "(bad)",          { XX } },
5642     /* 70 */
5643     { "(bad)",          { XX } },
5644     { "(bad)",          { XX } },
5645     { "(bad)",          { XX } },
5646     { "(bad)",          { XX } },
5647     { "(bad)",          { XX } },
5648     { "(bad)",          { XX } },
5649     { "(bad)",          { XX } },
5650     { "(bad)",          { XX } },
5651     /* 78 */
5652     { "(bad)",          { XX } },
5653     { "(bad)",          { XX } },
5654     { "(bad)",          { XX } },
5655     { "(bad)",          { XX } },
5656     { "(bad)",          { XX } },
5657     { "(bad)",          { XX } },
5658     { "(bad)",          { XX } },
5659     { "(bad)",          { XX } },
5660     /* 80 */
5661     { PREFIX_TABLE (PREFIX_0F3880) },
5662     { PREFIX_TABLE (PREFIX_0F3881) },
5663     { "(bad)",          { XX } },
5664     { "(bad)",          { XX } },
5665     { "(bad)",          { XX } },
5666     { "(bad)",          { XX } },
5667     { "(bad)",          { XX } },
5668     { "(bad)",          { XX } },
5669     /* 88 */
5670     { "(bad)",          { XX } },
5671     { "(bad)",          { XX } },
5672     { "(bad)",          { XX } },
5673     { "(bad)",          { XX } },
5674     { "(bad)",          { XX } },
5675     { "(bad)",          { XX } },
5676     { "(bad)",          { XX } },
5677     { "(bad)",          { XX } },
5678     /* 90 */
5679     { "(bad)",          { XX } },
5680     { "(bad)",          { XX } },
5681     { "(bad)",          { XX } },
5682     { "(bad)",          { XX } },
5683     { "(bad)",          { XX } },
5684     { "(bad)",          { XX } },
5685     { "(bad)",          { XX } },
5686     { "(bad)",          { XX } },
5687     /* 98 */
5688     { "(bad)",          { XX } },
5689     { "(bad)",          { XX } },
5690     { "(bad)",          { XX } },
5691     { "(bad)",          { XX } },
5692     { "(bad)",          { XX } },
5693     { "(bad)",          { XX } },
5694     { "(bad)",          { XX } },
5695     { "(bad)",          { XX } },
5696     /* a0 */
5697     { "(bad)",          { XX } },
5698     { "(bad)",          { XX } },
5699     { "(bad)",          { XX } },
5700     { "(bad)",          { XX } },
5701     { "(bad)",          { XX } },
5702     { "(bad)",          { XX } },
5703     { "(bad)",          { XX } },
5704     { "(bad)",          { XX } },
5705     /* a8 */
5706     { "(bad)",          { XX } },
5707     { "(bad)",          { XX } },
5708     { "(bad)",          { XX } },
5709     { "(bad)",          { XX } },
5710     { "(bad)",          { XX } },
5711     { "(bad)",          { XX } },
5712     { "(bad)",          { XX } },
5713     { "(bad)",          { XX } },
5714     /* b0 */
5715     { "(bad)",          { XX } },
5716     { "(bad)",          { XX } },
5717     { "(bad)",          { XX } },
5718     { "(bad)",          { XX } },
5719     { "(bad)",          { XX } },
5720     { "(bad)",          { XX } },
5721     { "(bad)",          { XX } },
5722     { "(bad)",          { XX } },
5723     /* b8 */
5724     { "(bad)",          { XX } },
5725     { "(bad)",          { XX } },
5726     { "(bad)",          { XX } },
5727     { "(bad)",          { XX } },
5728     { "(bad)",          { XX } },
5729     { "(bad)",          { XX } },
5730     { "(bad)",          { XX } },
5731     { "(bad)",          { XX } },
5732     /* c0 */
5733     { "(bad)",          { XX } },
5734     { "(bad)",          { XX } },
5735     { "(bad)",          { XX } },
5736     { "(bad)",          { XX } },
5737     { "(bad)",          { XX } },
5738     { "(bad)",          { XX } },
5739     { "(bad)",          { XX } },
5740     { "(bad)",          { XX } },
5741     /* c8 */
5742     { "(bad)",          { XX } },
5743     { "(bad)",          { XX } },
5744     { "(bad)",          { XX } },
5745     { "(bad)",          { XX } },
5746     { "(bad)",          { XX } },
5747     { "(bad)",          { XX } },
5748     { "(bad)",          { XX } },
5749     { "(bad)",          { XX } },
5750     /* d0 */
5751     { "(bad)",          { XX } },
5752     { "(bad)",          { XX } },
5753     { "(bad)",          { XX } },
5754     { "(bad)",          { XX } },
5755     { "(bad)",          { XX } },
5756     { "(bad)",          { XX } },
5757     { "(bad)",          { XX } },
5758     { "(bad)",          { XX } },
5759     /* d8 */
5760     { "(bad)",          { XX } },
5761     { "(bad)",          { XX } },
5762     { "(bad)",          { XX } },
5763     { PREFIX_TABLE (PREFIX_0F38DB) },
5764     { PREFIX_TABLE (PREFIX_0F38DC) },
5765     { PREFIX_TABLE (PREFIX_0F38DD) },
5766     { PREFIX_TABLE (PREFIX_0F38DE) },
5767     { PREFIX_TABLE (PREFIX_0F38DF) },
5768     /* e0 */
5769     { "(bad)",          { XX } },
5770     { "(bad)",          { XX } },
5771     { "(bad)",          { XX } },
5772     { "(bad)",          { XX } },
5773     { "(bad)",          { XX } },
5774     { "(bad)",          { XX } },
5775     { "(bad)",          { XX } },
5776     { "(bad)",          { XX } },
5777     /* e8 */
5778     { "(bad)",          { XX } },
5779     { "(bad)",          { XX } },
5780     { "(bad)",          { XX } },
5781     { "(bad)",          { XX } },
5782     { "(bad)",          { XX } },
5783     { "(bad)",          { XX } },
5784     { "(bad)",          { XX } },
5785     { "(bad)",          { XX } },
5786     /* f0 */
5787     { PREFIX_TABLE (PREFIX_0F38F0) },
5788     { PREFIX_TABLE (PREFIX_0F38F1) },
5789     { "(bad)",          { XX } },
5790     { "(bad)",          { XX } },
5791     { "(bad)",          { XX } },
5792     { "(bad)",          { XX } },
5793     { "(bad)",          { XX } },
5794     { "(bad)",          { XX } },
5795     /* f8 */
5796     { "(bad)",          { XX } },
5797     { "(bad)",          { XX } },
5798     { "(bad)",          { XX } },
5799     { "(bad)",          { XX } },
5800     { "(bad)",          { XX } },
5801     { "(bad)",          { XX } },
5802     { "(bad)",          { XX } },
5803     { "(bad)",          { XX } },
5804   },
5805   /* THREE_BYTE_0F3A */
5806   {
5807     /* 00 */
5808     { "(bad)",          { XX } },
5809     { "(bad)",          { XX } },
5810     { "(bad)",          { XX } },
5811     { "(bad)",          { XX } },
5812     { "(bad)",          { XX } },
5813     { "(bad)",          { XX } },
5814     { "(bad)",          { XX } },
5815     { "(bad)",          { XX } },
5816     /* 08 */
5817     { PREFIX_TABLE (PREFIX_0F3A08) },
5818     { PREFIX_TABLE (PREFIX_0F3A09) },
5819     { PREFIX_TABLE (PREFIX_0F3A0A) },
5820     { PREFIX_TABLE (PREFIX_0F3A0B) },
5821     { PREFIX_TABLE (PREFIX_0F3A0C) },
5822     { PREFIX_TABLE (PREFIX_0F3A0D) },
5823     { PREFIX_TABLE (PREFIX_0F3A0E) },
5824     { "palignr",        { MX, EM, Ib } },
5825     /* 10 */
5826     { "(bad)",          { XX } },
5827     { "(bad)",          { XX } },
5828     { "(bad)",          { XX } },
5829     { "(bad)",          { XX } },
5830     { PREFIX_TABLE (PREFIX_0F3A14) },
5831     { PREFIX_TABLE (PREFIX_0F3A15) },
5832     { PREFIX_TABLE (PREFIX_0F3A16) },
5833     { PREFIX_TABLE (PREFIX_0F3A17) },
5834     /* 18 */
5835     { "(bad)",          { XX } },
5836     { "(bad)",          { XX } },
5837     { "(bad)",          { XX } },
5838     { "(bad)",          { XX } },
5839     { "(bad)",          { XX } },
5840     { "(bad)",          { XX } },
5841     { "(bad)",          { XX } },
5842     { "(bad)",          { XX } },
5843     /* 20 */
5844     { PREFIX_TABLE (PREFIX_0F3A20) },
5845     { PREFIX_TABLE (PREFIX_0F3A21) },
5846     { PREFIX_TABLE (PREFIX_0F3A22) },
5847     { "(bad)",          { XX } },
5848     { "(bad)",          { XX } },
5849     { "(bad)",          { XX } },
5850     { "(bad)",          { XX } },
5851     { "(bad)",          { XX } },
5852     /* 28 */
5853     { "(bad)",          { XX } },
5854     { "(bad)",          { XX } },
5855     { "(bad)",          { XX } },
5856     { "(bad)",          { XX } },
5857     { "(bad)",          { XX } },
5858     { "(bad)",          { XX } },
5859     { "(bad)",          { XX } },
5860     { "(bad)",          { XX } },
5861     /* 30 */
5862     { "(bad)",          { XX } },
5863     { "(bad)",          { XX } },
5864     { "(bad)",          { XX } },
5865     { "(bad)",          { XX } },
5866     { "(bad)",          { XX } },
5867     { "(bad)",          { XX } },
5868     { "(bad)",          { XX } },
5869     { "(bad)",          { XX } },
5870     /* 38 */
5871     { "(bad)",          { XX } },
5872     { "(bad)",          { XX } },
5873     { "(bad)",          { XX } },
5874     { "(bad)",          { XX } },
5875     { "(bad)",          { XX } },
5876     { "(bad)",          { XX } },
5877     { "(bad)",          { XX } },
5878     { "(bad)",          { XX } },
5879     /* 40 */
5880     { PREFIX_TABLE (PREFIX_0F3A40) },
5881     { PREFIX_TABLE (PREFIX_0F3A41) },
5882     { PREFIX_TABLE (PREFIX_0F3A42) },
5883     { "(bad)",          { XX } },
5884     { PREFIX_TABLE (PREFIX_0F3A44) },
5885     { "(bad)",          { XX } },
5886     { "(bad)",          { XX } },
5887     { "(bad)",          { XX } },
5888     /* 48 */
5889     { "(bad)",          { XX } },
5890     { "(bad)",          { XX } },
5891     { "(bad)",          { XX } },
5892     { "(bad)",          { XX } },
5893     { "(bad)",          { XX } },
5894     { "(bad)",          { XX } },
5895     { "(bad)",          { XX } },
5896     { "(bad)",          { XX } },
5897     /* 50 */
5898     { "(bad)",          { XX } },
5899     { "(bad)",          { XX } },
5900     { "(bad)",          { XX } },
5901     { "(bad)",          { XX } },
5902     { "(bad)",          { XX } },
5903     { "(bad)",          { XX } },
5904     { "(bad)",          { XX } },
5905     { "(bad)",          { XX } },
5906     /* 58 */
5907     { "(bad)",          { XX } },
5908     { "(bad)",          { XX } },
5909     { "(bad)",          { XX } },
5910     { "(bad)",          { XX } },
5911     { "(bad)",          { XX } },
5912     { "(bad)",          { XX } },
5913     { "(bad)",          { XX } },
5914     { "(bad)",          { XX } },
5915     /* 60 */
5916     { PREFIX_TABLE (PREFIX_0F3A60) },
5917     { PREFIX_TABLE (PREFIX_0F3A61) },
5918     { PREFIX_TABLE (PREFIX_0F3A62) },
5919     { PREFIX_TABLE (PREFIX_0F3A63) },
5920     { "(bad)",          { XX } },
5921     { "(bad)",          { XX } },
5922     { "(bad)",          { XX } },
5923     { "(bad)",          { XX } },
5924     /* 68 */
5925     { "(bad)",          { XX } },
5926     { "(bad)",          { XX } },
5927     { "(bad)",          { XX } },
5928     { "(bad)",          { XX } },
5929     { "(bad)",          { XX } },
5930     { "(bad)",          { XX } },
5931     { "(bad)",          { XX } },
5932     { "(bad)",          { XX } },
5933     /* 70 */
5934     { "(bad)",          { XX } },
5935     { "(bad)",          { XX } },
5936     { "(bad)",          { XX } },
5937     { "(bad)",          { XX } },
5938     { "(bad)",          { XX } },
5939     { "(bad)",          { XX } },
5940     { "(bad)",          { XX } },
5941     { "(bad)",          { XX } },
5942     /* 78 */
5943     { "(bad)",          { XX } },
5944     { "(bad)",          { XX } },
5945     { "(bad)",          { XX } },
5946     { "(bad)",          { XX } },
5947     { "(bad)",          { XX } },
5948     { "(bad)",          { XX } },
5949     { "(bad)",          { XX } },
5950     { "(bad)",          { XX } },
5951     /* 80 */
5952     { "(bad)",          { XX } },
5953     { "(bad)",          { XX } },
5954     { "(bad)",          { XX } },
5955     { "(bad)",          { XX } },
5956     { "(bad)",          { XX } },
5957     { "(bad)",          { XX } },
5958     { "(bad)",          { XX } },
5959     { "(bad)",          { XX } },
5960     /* 88 */
5961     { "(bad)",          { XX } },
5962     { "(bad)",          { XX } },
5963     { "(bad)",          { XX } },
5964     { "(bad)",          { XX } },
5965     { "(bad)",          { XX } },
5966     { "(bad)",          { XX } },
5967     { "(bad)",          { XX } },
5968     { "(bad)",          { XX } },
5969     /* 90 */
5970     { "(bad)",          { XX } },
5971     { "(bad)",          { XX } },
5972     { "(bad)",          { XX } },
5973     { "(bad)",          { XX } },
5974     { "(bad)",          { XX } },
5975     { "(bad)",          { XX } },
5976     { "(bad)",          { XX } },
5977     { "(bad)",          { XX } },
5978     /* 98 */
5979     { "(bad)",          { XX } },
5980     { "(bad)",          { XX } },
5981     { "(bad)",          { XX } },
5982     { "(bad)",          { XX } },
5983     { "(bad)",          { XX } },
5984     { "(bad)",          { XX } },
5985     { "(bad)",          { XX } },
5986     { "(bad)",          { XX } },
5987     /* a0 */
5988     { "(bad)",          { XX } },
5989     { "(bad)",          { XX } },
5990     { "(bad)",          { XX } },
5991     { "(bad)",          { XX } },
5992     { "(bad)",          { XX } },
5993     { "(bad)",          { XX } },
5994     { "(bad)",          { XX } },
5995     { "(bad)",          { XX } },
5996     /* a8 */
5997     { "(bad)",          { XX } },
5998     { "(bad)",          { XX } },
5999     { "(bad)",          { XX } },
6000     { "(bad)",          { XX } },
6001     { "(bad)",          { XX } },
6002     { "(bad)",          { XX } },
6003     { "(bad)",          { XX } },
6004     { "(bad)",          { XX } },
6005     /* b0 */
6006     { "(bad)",          { XX } },
6007     { "(bad)",          { XX } },
6008     { "(bad)",          { XX } },
6009     { "(bad)",          { XX } },
6010     { "(bad)",          { XX } },
6011     { "(bad)",          { XX } },
6012     { "(bad)",          { XX } },
6013     { "(bad)",          { XX } },
6014     /* b8 */
6015     { "(bad)",          { XX } },
6016     { "(bad)",          { XX } },
6017     { "(bad)",          { XX } },
6018     { "(bad)",          { XX } },
6019     { "(bad)",          { XX } },
6020     { "(bad)",          { XX } },
6021     { "(bad)",          { XX } },
6022     { "(bad)",          { XX } },
6023     /* c0 */
6024     { "(bad)",          { XX } },
6025     { "(bad)",          { XX } },
6026     { "(bad)",          { XX } },
6027     { "(bad)",          { XX } },
6028     { "(bad)",          { XX } },
6029     { "(bad)",          { XX } },
6030     { "(bad)",          { XX } },
6031     { "(bad)",          { XX } },
6032     /* c8 */
6033     { "(bad)",          { XX } },
6034     { "(bad)",          { XX } },
6035     { "(bad)",          { XX } },
6036     { "(bad)",          { XX } },
6037     { "(bad)",          { XX } },
6038     { "(bad)",          { XX } },
6039     { "(bad)",          { XX } },
6040     { "(bad)",          { XX } },
6041     /* d0 */
6042     { "(bad)",          { XX } },
6043     { "(bad)",          { XX } },
6044     { "(bad)",          { XX } },
6045     { "(bad)",          { XX } },
6046     { "(bad)",          { XX } },
6047     { "(bad)",          { XX } },
6048     { "(bad)",          { XX } },
6049     { "(bad)",          { XX } },
6050     /* d8 */
6051     { "(bad)",          { XX } },
6052     { "(bad)",          { XX } },
6053     { "(bad)",          { XX } },
6054     { "(bad)",          { XX } },
6055     { "(bad)",          { XX } },
6056     { "(bad)",          { XX } },
6057     { "(bad)",          { XX } },
6058     { PREFIX_TABLE (PREFIX_0F3ADF) },
6059     /* e0 */
6060     { "(bad)",          { XX } },
6061     { "(bad)",          { XX } },
6062     { "(bad)",          { XX } },
6063     { "(bad)",          { XX } },
6064     { "(bad)",          { XX } },
6065     { "(bad)",          { XX } },
6066     { "(bad)",          { XX } },
6067     { "(bad)",          { XX } },
6068     /* e8 */
6069     { "(bad)",          { XX } },
6070     { "(bad)",          { XX } },
6071     { "(bad)",          { XX } },
6072     { "(bad)",          { XX } },
6073     { "(bad)",          { XX } },
6074     { "(bad)",          { XX } },
6075     { "(bad)",          { XX } },
6076     { "(bad)",          { XX } },
6077     /* f0 */
6078     { "(bad)",          { XX } },
6079     { "(bad)",          { XX } },
6080     { "(bad)",          { XX } },
6081     { "(bad)",          { XX } },
6082     { "(bad)",          { XX } },
6083     { "(bad)",          { XX } },
6084     { "(bad)",          { XX } },
6085     { "(bad)",          { XX } },
6086     /* f8 */
6087     { "(bad)",          { XX } },
6088     { "(bad)",          { XX } },
6089     { "(bad)",          { XX } },
6090     { "(bad)",          { XX } },
6091     { "(bad)",          { XX } },
6092     { "(bad)",          { XX } },
6093     { "(bad)",          { XX } },
6094     { "(bad)",          { XX } },
6095   },
6096
6097   /* THREE_BYTE_0F7A */
6098   {
6099     /* 00 */
6100     { "(bad)",          { XX } },
6101     { "(bad)",          { XX } },
6102     { "(bad)",          { XX } },
6103     { "(bad)",          { XX } },
6104     { "(bad)",          { XX } },
6105     { "(bad)",          { XX } },
6106     { "(bad)",          { XX } },
6107     { "(bad)",          { XX } },
6108     /* 08 */
6109     { "(bad)",          { XX } },
6110     { "(bad)",          { XX } },
6111     { "(bad)",          { XX } },
6112     { "(bad)",          { XX } },
6113     { "(bad)",          { XX } },
6114     { "(bad)",          { XX } },
6115     { "(bad)",          { XX } },
6116     { "(bad)",          { XX } },
6117     /* 10 */
6118     { "(bad)",          { XX } },
6119     { "(bad)",          { XX } },
6120     { "(bad)",          { XX } },
6121     { "(bad)",          { XX } },
6122     { "(bad)",          { XX } },
6123     { "(bad)",          { XX } },
6124     { "(bad)",          { XX } },
6125     { "(bad)",          { XX } },
6126     /* 18 */
6127     { "(bad)",          { XX } },
6128     { "(bad)",          { XX } },
6129     { "(bad)",          { XX } },
6130     { "(bad)",          { XX } },
6131     { "(bad)",          { XX } },
6132     { "(bad)",          { XX } },
6133     { "(bad)",          { XX } },
6134     { "(bad)",          { XX } },
6135     /* 20 */
6136     { "ptest",          { XX } },
6137     { "(bad)",          { XX } },
6138     { "(bad)",          { XX } },
6139     { "(bad)",          { XX } },
6140     { "(bad)",          { XX } },
6141     { "(bad)",          { XX } },
6142     { "(bad)",          { XX } },
6143     { "(bad)",          { XX } },
6144     /* 28 */
6145     { "(bad)",          { XX } },
6146     { "(bad)",          { XX } },
6147     { "(bad)",          { XX } },
6148     { "(bad)",          { XX } },
6149     { "(bad)",          { XX } },
6150     { "(bad)",          { XX } },
6151     { "(bad)",          { XX } },
6152     { "(bad)",          { XX } },
6153     /* 30 */
6154     { "(bad)",          { XX } },
6155     { "(bad)",          { XX } },
6156     { "(bad)",          { XX } },
6157     { "(bad)",          { XX } },
6158     { "(bad)",          { XX } },
6159     { "(bad)",          { XX } },
6160     { "(bad)",          { XX } },
6161     { "(bad)",          { XX } },
6162     /* 38 */
6163     { "(bad)",          { XX } },
6164     { "(bad)",          { XX } },
6165     { "(bad)",          { XX } },
6166     { "(bad)",          { XX } },
6167     { "(bad)",          { XX } },
6168     { "(bad)",          { XX } },
6169     { "(bad)",          { XX } },
6170     { "(bad)",          { XX } },
6171     /* 40 */
6172     { "(bad)",          { XX } },
6173     { "phaddbw",        { XM, EXq } },
6174     { "phaddbd",        { XM, EXq } },
6175     { "phaddbq",        { XM, EXq } },
6176     { "(bad)",          { XX } },
6177     { "(bad)",          { XX } },
6178     { "phaddwd",        { XM, EXq } },
6179     { "phaddwq",        { XM, EXq } },
6180     /* 48 */
6181     { "(bad)",          { XX } },
6182     { "(bad)",          { XX } },
6183     { "(bad)",          { XX } },
6184     { "phadddq",        { XM, EXq } },
6185     { "(bad)",          { XX } },
6186     { "(bad)",          { XX } },
6187     { "(bad)",          { XX } },
6188     { "(bad)",          { XX } },
6189     /* 50 */
6190     { "(bad)",          { XX } },
6191     { "phaddubw",       { XM, EXq } },
6192     { "phaddubd",       { XM, EXq } },
6193     { "phaddubq",       { XM, EXq } },
6194     { "(bad)",          { XX } },
6195     { "(bad)",          { XX } },
6196     { "phadduwd",       { XM, EXq } },
6197     { "phadduwq",       { XM, EXq } },
6198     /* 58 */
6199     { "(bad)",          { XX } },
6200     { "(bad)",          { XX } },
6201     { "(bad)",          { XX } },
6202     { "phaddudq",       { XM, EXq } },
6203     { "(bad)",          { XX } },
6204     { "(bad)",          { XX } },
6205     { "(bad)",          { XX } },
6206     { "(bad)",          { XX } },
6207     /* 60 */
6208     { "(bad)",          { XX } },
6209     { "phsubbw",        { XM, EXq } },
6210     { "phsubbd",        { XM, EXq } },
6211     { "phsubbq",        { XM, EXq } },
6212     { "(bad)",          { XX } },
6213     { "(bad)",          { XX } },
6214     { "(bad)",          { XX } },
6215     { "(bad)",          { XX } },
6216     /* 68 */
6217     { "(bad)",          { XX } },
6218     { "(bad)",          { XX } },
6219     { "(bad)",          { XX } },
6220     { "(bad)",          { XX } },
6221     { "(bad)",          { XX } },
6222     { "(bad)",          { XX } },
6223     { "(bad)",          { XX } },
6224     { "(bad)",          { XX } },
6225     /* 70 */
6226     { "(bad)",          { XX } },
6227     { "(bad)",          { XX } },
6228     { "(bad)",          { XX } },
6229     { "(bad)",          { XX } },
6230     { "(bad)",          { XX } },
6231     { "(bad)",          { XX } },
6232     { "(bad)",          { XX } },
6233     { "(bad)",          { XX } },
6234     /* 78 */
6235     { "(bad)",          { XX } },
6236     { "(bad)",          { XX } },
6237     { "(bad)",          { XX } },
6238     { "(bad)",          { XX } },
6239     { "(bad)",          { XX } },
6240     { "(bad)",          { XX } },
6241     { "(bad)",          { XX } },
6242     { "(bad)",          { XX } },
6243     /* 80 */
6244     { "(bad)",          { XX } },
6245     { "(bad)",          { XX } },
6246     { "(bad)",          { XX } },
6247     { "(bad)",          { XX } },
6248     { "(bad)",          { XX } },
6249     { "(bad)",          { XX } },
6250     { "(bad)",          { XX } },
6251     { "(bad)",          { XX } },
6252     /* 88 */
6253     { "(bad)",          { XX } },
6254     { "(bad)",          { XX } },
6255     { "(bad)",          { XX } },
6256     { "(bad)",          { XX } },
6257     { "(bad)",          { XX } },
6258     { "(bad)",          { XX } },
6259     { "(bad)",          { XX } },
6260     { "(bad)",          { XX } },
6261     /* 90 */
6262     { "(bad)",          { XX } },
6263     { "(bad)",          { XX } },
6264     { "(bad)",          { XX } },
6265     { "(bad)",          { XX } },
6266     { "(bad)",          { XX } },
6267     { "(bad)",          { XX } },
6268     { "(bad)",          { XX } },
6269     { "(bad)",          { XX } },
6270     /* 98 */
6271     { "(bad)",          { XX } },
6272     { "(bad)",          { XX } },
6273     { "(bad)",          { XX } },
6274     { "(bad)",          { XX } },
6275     { "(bad)",          { XX } },
6276     { "(bad)",          { XX } },
6277     { "(bad)",          { XX } },
6278     { "(bad)",          { XX } },
6279     /* a0 */
6280     { "(bad)",          { XX } },
6281     { "(bad)",          { XX } },
6282     { "(bad)",          { XX } },
6283     { "(bad)",          { XX } },
6284     { "(bad)",          { XX } },
6285     { "(bad)",          { XX } },
6286     { "(bad)",          { XX } },
6287     { "(bad)",          { XX } },
6288     /* a8 */
6289     { "(bad)",          { XX } },
6290     { "(bad)",          { XX } },
6291     { "(bad)",          { XX } },
6292     { "(bad)",          { XX } },
6293     { "(bad)",          { XX } },
6294     { "(bad)",          { XX } },
6295     { "(bad)",          { XX } },
6296     { "(bad)",          { XX } },
6297     /* b0 */
6298     { "(bad)",          { XX } },
6299     { "(bad)",          { XX } },
6300     { "(bad)",          { XX } },
6301     { "(bad)",          { XX } },
6302     { "(bad)",          { XX } },
6303     { "(bad)",          { XX } },
6304     { "(bad)",          { XX } },
6305     { "(bad)",          { XX } },
6306     /* b8 */
6307     { "(bad)",          { XX } },
6308     { "(bad)",          { XX } },
6309     { "(bad)",          { XX } },
6310     { "(bad)",          { XX } },
6311     { "(bad)",          { XX } },
6312     { "(bad)",          { XX } },
6313     { "(bad)",          { XX } },
6314     { "(bad)",          { XX } },
6315     /* c0 */
6316     { "(bad)",          { XX } },
6317     { "(bad)",          { XX } },
6318     { "(bad)",          { XX } },
6319     { "(bad)",          { XX } },
6320     { "(bad)",          { XX } },
6321     { "(bad)",          { XX } },
6322     { "(bad)",          { XX } },
6323     { "(bad)",          { XX } },
6324     /* c8 */
6325     { "(bad)",          { XX } },
6326     { "(bad)",          { XX } },
6327     { "(bad)",          { XX } },
6328     { "(bad)",          { XX } },
6329     { "(bad)",          { XX } },
6330     { "(bad)",          { XX } },
6331     { "(bad)",          { XX } },
6332     { "(bad)",          { XX } },
6333     /* d0 */
6334     { "(bad)",          { XX } },
6335     { "(bad)",          { XX } },
6336     { "(bad)",          { XX } },
6337     { "(bad)",          { XX } },
6338     { "(bad)",          { XX } },
6339     { "(bad)",          { XX } },
6340     { "(bad)",          { XX } },
6341     { "(bad)",          { XX } },
6342     /* d8 */
6343     { "(bad)",          { XX } },
6344     { "(bad)",          { XX } },
6345     { "(bad)",          { XX } },
6346     { "(bad)",          { XX } },
6347     { "(bad)",          { XX } },
6348     { "(bad)",          { XX } },
6349     { "(bad)",          { XX } },
6350     { "(bad)",          { XX } },
6351     /* e0 */
6352     { "(bad)",          { XX } },
6353     { "(bad)",          { XX } },
6354     { "(bad)",          { XX } },
6355     { "(bad)",          { XX } },
6356     { "(bad)",          { XX } },
6357     { "(bad)",          { XX } },
6358     { "(bad)",          { XX } },
6359     { "(bad)",          { XX } },
6360     /* e8 */
6361     { "(bad)",          { XX } },
6362     { "(bad)",          { XX } },
6363     { "(bad)",          { XX } },
6364     { "(bad)",          { XX } },
6365     { "(bad)",          { XX } },
6366     { "(bad)",          { XX } },
6367     { "(bad)",          { XX } },
6368     { "(bad)",          { XX } },
6369     /* f0 */
6370     { "(bad)",          { XX } },
6371     { "(bad)",          { XX } },
6372     { "(bad)",          { XX } },
6373     { "(bad)",          { XX } },
6374     { "(bad)",          { XX } },
6375     { "(bad)",          { XX } },
6376     { "(bad)",          { XX } },
6377     { "(bad)",          { XX } },
6378     /* f8 */
6379     { "(bad)",          { XX } },
6380     { "(bad)",          { XX } },
6381     { "(bad)",          { XX } },
6382     { "(bad)",          { XX } },
6383     { "(bad)",          { XX } },
6384     { "(bad)",          { XX } },
6385     { "(bad)",          { XX } },
6386     { "(bad)",          { XX } },
6387   },
6388 };
6389
6390 static const struct dis386 xop_table[][256] = {
6391   /* XOP_08 */
6392   {
6393     /* 00 */
6394     { "(bad)",          { XX } },
6395     { "(bad)",          { XX } },
6396     { "(bad)",          { XX } },
6397     { "(bad)",          { XX } },
6398     { "(bad)",          { XX } },
6399     { "(bad)",          { XX } },
6400     { "(bad)",          { XX } },
6401     { "(bad)",          { XX } },
6402     /* 08 */
6403     { "(bad)",          { XX } },
6404     { "(bad)",          { XX } },
6405     { "(bad)",          { XX } },
6406     { "(bad)",          { XX } },
6407     { "(bad)",          { XX } },
6408     { "(bad)",          { XX } },
6409     { "(bad)",          { XX } },
6410     { "(bad)",          { XX } },
6411     /* 10 */
6412     { "(bad)",          { XX } },
6413     { "(bad)",          { XX } },
6414     { "(bad)",          { XX } },
6415     { "(bad)",          { XX } },
6416     { "(bad)",          { XX } },
6417     { "(bad)",          { XX } },
6418     { "(bad)",          { XX } },
6419     { "(bad)",          { XX } },
6420     /* 18 */
6421     { "(bad)",          { XX } },
6422     { "(bad)",          { XX } },
6423     { "(bad)",          { XX } },
6424     { "(bad)",          { XX } },
6425     { "(bad)",          { XX } },
6426     { "(bad)",          { XX } },
6427     { "(bad)",          { XX } },
6428     { "(bad)",          { XX } },
6429     /* 20 */
6430     { "(bad)",          { XX } },
6431     { "(bad)",          { XX } },
6432     { "(bad)",          { XX } },
6433     { "(bad)",          { XX } },
6434     { "(bad)",          { XX } },
6435     { "(bad)",          { XX } },
6436     { "(bad)",          { XX } },
6437     { "(bad)",          { XX } },
6438     /* 28 */
6439     { "(bad)",          { XX } },
6440     { "(bad)",          { XX } },
6441     { "(bad)",          { XX } },
6442     { "(bad)",          { XX } },
6443     { "(bad)",          { XX } },
6444     { "(bad)",          { XX } },
6445     { "(bad)",          { XX } },
6446     { "(bad)",          { XX } },
6447     /* 30 */
6448     { "(bad)",          { XX } },
6449     { "(bad)",          { XX } },
6450     { "(bad)",          { XX } },
6451     { "(bad)",          { XX } },
6452     { "(bad)",          { XX } },
6453     { "(bad)",          { XX } },
6454     { "(bad)",          { XX } },
6455     { "(bad)",          { XX } },
6456     /* 38 */
6457     { "(bad)",          { XX } },
6458     { "(bad)",          { XX } },
6459     { "(bad)",          { XX } },
6460     { "(bad)",          { XX } },
6461     { "(bad)",          { XX } },
6462     { "(bad)",          { XX } },
6463     { "(bad)",          { XX } },
6464     { "(bad)",          { XX } },
6465     /* 40 */
6466     { "(bad)",          { XX } },
6467     { "(bad)",          { XX } },
6468     { "(bad)",          { XX } },
6469     { "(bad)",          { XX } },
6470     { "(bad)",          { XX } },
6471     { "(bad)",          { XX } },
6472     { "(bad)",          { XX } },
6473     { "(bad)",          { XX } },
6474     /* 48 */
6475     { "(bad)",          { XX } },
6476     { "(bad)",          { XX } },
6477     { "(bad)",          { XX } },
6478     { "(bad)",          { XX } },
6479     { "(bad)",          { XX } },
6480     { "(bad)",          { XX } },
6481     { "(bad)",          { XX } },
6482     { "(bad)",          { XX } },
6483     /* 50 */
6484     { "(bad)",          { XX } },
6485     { "(bad)",          { XX } },
6486     { "(bad)",          { XX } },
6487     { "(bad)",          { XX } },
6488     { "(bad)",          { XX } },
6489     { "(bad)",          { XX } },
6490     { "(bad)",          { XX } },
6491     { "(bad)",          { XX } },
6492     /* 58 */
6493     { "(bad)",          { XX } },
6494     { "(bad)",          { XX } },
6495     { "(bad)",          { XX } },
6496     { "(bad)",          { XX } },
6497     { "(bad)",          { XX } },
6498     { "(bad)",          { XX } },
6499     { "(bad)",          { XX } },
6500     { "(bad)",          { XX } },
6501     /* 60 */
6502     { "(bad)",          { XX } },
6503     { "(bad)",          { XX } },
6504     { "(bad)",          { XX } },
6505     { "(bad)",          { XX } },
6506     { "(bad)",          { XX } },
6507     { "(bad)",          { XX } },
6508     { "(bad)",          { XX } },
6509     { "(bad)",          { XX } },
6510     /* 68 */
6511     { "(bad)",          { XX } },
6512     { "(bad)",          { XX } },
6513     { "(bad)",          { XX } },
6514     { "(bad)",          { XX } },
6515     { "(bad)",          { XX } },
6516     { "(bad)",          { XX } },
6517     { "(bad)",          { XX } },
6518     { "(bad)",          { XX } },
6519     /* 70 */
6520     { "(bad)",          { XX } },
6521     { "(bad)",          { XX } },
6522     { "(bad)",          { XX } },
6523     { "(bad)",          { XX } },
6524     { "(bad)",          { XX } },
6525     { "(bad)",          { XX } },
6526     { "(bad)",          { XX } },
6527     { "(bad)",          { XX } },
6528     /* 78 */
6529     { "(bad)",          { XX } },
6530     { "(bad)",          { XX } },
6531     { "(bad)",          { XX } },
6532     { "(bad)",          { XX } },
6533     { "(bad)",          { XX } },
6534     { "(bad)",          { XX } },
6535     { "(bad)",          { XX } },
6536     { "(bad)",          { XX } },
6537     /* 80 */
6538     { "(bad)",          { XX } },
6539     { "(bad)",          { XX } },
6540     { "(bad)",          { XX } },
6541     { "(bad)",          { XX } },
6542     { "(bad)",          { XX } },
6543     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6544     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6545     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6546     /* 88 */
6547     { "(bad)",          { XX } },
6548     { "(bad)",          { XX } },
6549     { "(bad)",          { XX } },
6550     { "(bad)",          { XX } },
6551     { "(bad)",          { XX } },
6552     { "(bad)",          { XX } },
6553     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6554     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6555     /* 90 */
6556     { "(bad)",          { XX } },
6557     { "(bad)",          { XX } },
6558     { "(bad)",          { XX } },
6559     { "(bad)",          { XX } },
6560     { "(bad)",          { XX } },
6561     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6562     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6563     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6564     /* 98 */
6565     { "(bad)",          { XX } },
6566     { "(bad)",          { XX } },
6567     { "(bad)",          { XX } },
6568     { "(bad)",          { XX } },
6569     { "(bad)",          { XX } },
6570     { "(bad)",          { XX } },
6571     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6572     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6573     /* a0 */
6574     { "(bad)",          { XX } },
6575     { "(bad)",          { XX } },
6576     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6577     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6578     { "(bad)",          { XX } },
6579     { "(bad)",          { XX } },
6580     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6581     { "(bad)",          { XX } },
6582     /* a8 */
6583     { "(bad)",          { XX } },
6584     { "(bad)",          { XX } },
6585     { "(bad)",          { XX } },
6586     { "(bad)",          { XX } },
6587     { "(bad)",          { XX } },
6588     { "(bad)",          { XX } },
6589     { "(bad)",          { XX } },
6590     { "(bad)",          { XX } },
6591     /* b0 */
6592     { "(bad)",          { XX } },
6593     { "(bad)",          { XX } },
6594     { "(bad)",          { XX } },
6595     { "(bad)",          { XX } },
6596     { "(bad)",          { XX } },
6597     { "(bad)",          { XX } },
6598     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6599     { "(bad)",          { XX } },
6600     /* b8 */
6601     { "(bad)",          { XX } },
6602     { "(bad)",          { XX } },
6603     { "(bad)",          { XX } },
6604     { "(bad)",          { XX } },
6605     { "(bad)",          { XX } },
6606     { "(bad)",          { XX } },
6607     { "(bad)",          { XX } },
6608     { "(bad)",          { XX } },
6609     /* c0 */
6610     { "vprotb",         { XM, Vex_2src_1, Ib } },
6611     { "vprotw",         { XM, Vex_2src_1, Ib } },
6612     { "vprotd",         { XM, Vex_2src_1, Ib } },
6613     { "vprotq",         { XM, Vex_2src_1, Ib } },
6614     { "(bad)",          { XX } },
6615     { "(bad)",          { XX } },
6616     { "(bad)",          { XX } },
6617     { "(bad)",          { XX } },
6618     /* c8 */
6619     { "(bad)",          { XX } },
6620     { "(bad)",          { XX } },
6621     { "(bad)",          { XX } },
6622     { "(bad)",          { XX } },
6623     { "vpcomb",         { XM, Vex128, EXx, Ib } },
6624     { "vpcomw",         { XM, Vex128, EXx, Ib } },
6625     { "vpcomd",         { XM, Vex128, EXx, Ib } },
6626     { "vpcomq",         { XM, Vex128, EXx, Ib } },
6627     /* d0 */
6628     { "(bad)",          { XX } },
6629     { "(bad)",          { XX } },
6630     { "(bad)",          { XX } },
6631     { "(bad)",          { XX } },
6632     { "(bad)",          { XX } },
6633     { "(bad)",          { XX } },
6634     { "(bad)",          { XX } },
6635     { "(bad)",          { XX } },
6636     /* d8 */
6637     { "(bad)",          { XX } },
6638     { "(bad)",          { XX } },
6639     { "(bad)",          { XX } },
6640     { "(bad)",          { XX } },
6641     { "(bad)",          { XX } },
6642     { "(bad)",          { XX } },
6643     { "(bad)",          { XX } },
6644     { "(bad)",          { XX } },
6645     /* e0 */
6646     { "(bad)",          { XX } },
6647     { "(bad)",          { XX } },
6648     { "(bad)",          { XX } },
6649     { "(bad)",          { XX } },
6650     { "(bad)",          { XX } },
6651     { "(bad)",          { XX } },
6652     { "(bad)",          { XX } },
6653     { "(bad)",          { XX } },
6654     /* e8 */
6655     { "(bad)",          { XX } },
6656     { "(bad)",          { XX } },
6657     { "(bad)",          { XX } },
6658     { "(bad)",          { XX } },
6659     { "vpcomub",        { XM, Vex128, EXx, Ib } },
6660     { "vpcomuw",        { XM, Vex128, EXx, Ib } },
6661     { "vpcomud",        { XM, Vex128, EXx, Ib } },
6662     { "vpcomuq",        { XM, Vex128, EXx, Ib } },
6663     /* f0 */
6664     { "(bad)",          { XX } },
6665     { "(bad)",          { XX } },
6666     { "(bad)",          { XX } },
6667     { "(bad)",          { XX } },
6668     { "(bad)",          { XX } },
6669     { "(bad)",          { XX } },
6670     { "(bad)",          { XX } },
6671     { "(bad)",          { XX } },
6672     /* f8 */
6673     { "(bad)",          { XX } },
6674     { "(bad)",          { XX } },
6675     { "(bad)",          { XX } },
6676     { "(bad)",          { XX } },
6677     { "(bad)",          { XX } },
6678     { "(bad)",          { XX } },
6679     { "(bad)",          { XX } },
6680     { "(bad)",          { XX } },
6681   },
6682   /* XOP_09 */
6683   {
6684     /* 00 */
6685     { "(bad)",          { XX } },
6686     { "(bad)",          { XX } },
6687     { "(bad)",          { XX } },
6688     { "(bad)",          { XX } },
6689     { "(bad)",          { XX } },
6690     { "(bad)",          { XX } },
6691     { "(bad)",          { XX } },
6692     { "(bad)",          { XX } },
6693     /* 08 */
6694     { "(bad)",          { XX } },
6695     { "(bad)",          { XX } },
6696     { "(bad)",          { XX } },
6697     { "(bad)",          { XX } },
6698     { "(bad)",          { XX } },
6699     { "(bad)",          { XX } },
6700     { "(bad)",          { XX } },
6701     { "(bad)",          { XX } },
6702     /* 10 */
6703     { "(bad)",          { XX } },
6704     { "(bad)",          { XX } },
6705     { REG_TABLE (REG_XOP_LWPCB) },
6706     { "(bad)",          { XX } },
6707     { "(bad)",          { XX } },
6708     { "(bad)",          { XX } },
6709     { "(bad)",          { XX } },
6710     { "(bad)",          { XX } },
6711     /* 18 */
6712     { "(bad)",          { XX } },
6713     { "(bad)",          { XX } },
6714     { "(bad)",          { XX } },
6715     { "(bad)",          { XX } },
6716     { "(bad)",          { XX } },
6717     { "(bad)",          { XX } },
6718     { "(bad)",          { XX } },
6719     { "(bad)",          { XX } },
6720     /* 20 */
6721     { "(bad)",          { XX } },
6722     { "(bad)",          { XX } },
6723     { "(bad)",          { XX } },
6724     { "(bad)",          { XX } },
6725     { "(bad)",          { XX } },
6726     { "(bad)",          { XX } },
6727     { "(bad)",          { XX } },
6728     { "(bad)",          { XX } },
6729     /* 28 */
6730     { "(bad)",          { XX } },
6731     { "(bad)",          { XX } },
6732     { "(bad)",          { XX } },
6733     { "(bad)",          { XX } },
6734     { "(bad)",          { XX } },
6735     { "(bad)",          { XX } },
6736     { "(bad)",          { XX } },
6737     { "(bad)",          { XX } },
6738     /* 30 */
6739     { "(bad)",          { XX } },
6740     { "(bad)",          { XX } },
6741     { "(bad)",          { XX } },
6742     { "(bad)",          { XX } },
6743     { "(bad)",          { XX } },
6744     { "(bad)",          { XX } },
6745     { "(bad)",          { XX } },
6746     { "(bad)",          { XX } },
6747     /* 38 */
6748     { "(bad)",          { XX } },
6749     { "(bad)",          { XX } },
6750     { "(bad)",          { XX } },
6751     { "(bad)",          { XX } },
6752     { "(bad)",          { XX } },
6753     { "(bad)",          { XX } },
6754     { "(bad)",          { XX } },
6755     { "(bad)",          { XX } },
6756     /* 40 */
6757     { "(bad)",          { XX } },
6758     { "(bad)",          { XX } },
6759     { "(bad)",          { XX } },
6760     { "(bad)",          { XX } },
6761     { "(bad)",          { XX } },
6762     { "(bad)",          { XX } },
6763     { "(bad)",          { XX } },
6764     { "(bad)",          { XX } },
6765     /* 48 */
6766     { "(bad)",          { XX } },
6767     { "(bad)",          { XX } },
6768     { "(bad)",          { XX } },
6769     { "(bad)",          { XX } },
6770     { "(bad)",          { XX } },
6771     { "(bad)",          { XX } },
6772     { "(bad)",          { XX } },
6773     { "(bad)",          { XX } },
6774     /* 50 */
6775     { "(bad)",          { XX } },
6776     { "(bad)",          { XX } },
6777     { "(bad)",          { XX } },
6778     { "(bad)",          { XX } },
6779     { "(bad)",          { XX } },
6780     { "(bad)",          { XX } },
6781     { "(bad)",          { XX } },
6782     { "(bad)",          { XX } },
6783     /* 58 */
6784     { "(bad)",          { XX } },
6785     { "(bad)",          { XX } },
6786     { "(bad)",          { XX } },
6787     { "(bad)",          { XX } },
6788     { "(bad)",          { XX } },
6789     { "(bad)",          { XX } },
6790     { "(bad)",          { XX } },
6791     { "(bad)",          { XX } },
6792     /* 60 */
6793     { "(bad)",          { XX } },
6794     { "(bad)",          { XX } },
6795     { "(bad)",          { XX } },
6796     { "(bad)",          { XX } },
6797     { "(bad)",          { XX } },
6798     { "(bad)",          { XX } },
6799     { "(bad)",          { XX } },
6800     { "(bad)",          { XX } },
6801     /* 68 */
6802     { "(bad)",          { XX } },
6803     { "(bad)",          { XX } },
6804     { "(bad)",          { XX } },
6805     { "(bad)",          { XX } },
6806     { "(bad)",          { XX } },
6807     { "(bad)",          { XX } },
6808     { "(bad)",          { XX } },
6809     { "(bad)",          { XX } },
6810     /* 70 */
6811     { "(bad)",          { XX } },
6812     { "(bad)",          { XX } },
6813     { "(bad)",          { XX } },
6814     { "(bad)",          { XX } },
6815     { "(bad)",          { XX } },
6816     { "(bad)",          { XX } },
6817     { "(bad)",          { XX } },
6818     { "(bad)",          { XX } },
6819     /* 78 */
6820     { "(bad)",          { XX } },
6821     { "(bad)",          { XX } },
6822     { "(bad)",          { XX } },
6823     { "(bad)",          { XX } },
6824     { "(bad)",          { XX } },
6825     { "(bad)",          { XX } },
6826     { "(bad)",          { XX } },
6827     { "(bad)",          { XX } },
6828     /* 80 */
6829     { VEX_LEN_TABLE (VEX_LEN_XOP_09_80) },
6830     { VEX_LEN_TABLE (VEX_LEN_XOP_09_81) },
6831     { "vfrczss",        { XM, EXd } },
6832     { "vfrczsd",        { XM, EXq } },
6833     { "(bad)",          { XX } },
6834     { "(bad)",          { XX } },
6835     { "(bad)",          { XX } },
6836     { "(bad)",          { XX } },
6837     /* 88 */
6838     { "(bad)",          { XX } },
6839     { "(bad)",          { XX } },
6840     { "(bad)",          { XX } },
6841     { "(bad)",          { XX } },
6842     { "(bad)",          { XX } },
6843     { "(bad)",          { XX } },
6844     { "(bad)",          { XX } },
6845     { "(bad)",          { XX } },
6846     /* 90 */
6847     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
6848     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
6849     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
6850     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
6851     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
6852     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
6853     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
6854     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
6855     /* 98 */
6856     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
6857     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
6858     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
6859     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
6860     { "(bad)",          { XX } },
6861     { "(bad)",          { XX } },
6862     { "(bad)",          { XX } },
6863     { "(bad)",          { XX } },
6864     /* a0 */
6865     { "(bad)",          { XX } },
6866     { "(bad)",          { XX } },
6867     { "(bad)",          { XX } },
6868     { "(bad)",          { XX } },
6869     { "(bad)",          { XX } },
6870     { "(bad)",          { XX } },
6871     { "(bad)",          { XX } },
6872     { "(bad)",          { XX } },
6873     /* a8 */
6874     { "(bad)",          { XX } },
6875     { "(bad)",          { XX } },
6876     { "(bad)",          { XX } },
6877     { "(bad)",          { XX } },
6878     { "(bad)",          { XX } },
6879     { "(bad)",          { XX } },
6880     { "(bad)",          { XX } },
6881     { "(bad)",          { XX } },
6882     /* b0 */
6883     { "(bad)",          { XX } },
6884     { "(bad)",          { XX } },
6885     { "(bad)",          { XX } },
6886     { "(bad)",          { XX } },
6887     { "(bad)",          { XX } },
6888     { "(bad)",          { XX } },
6889     { "(bad)",          { XX } },
6890     { "(bad)",          { XX } },
6891     /* b8 */
6892     { "(bad)",          { XX } },
6893     { "(bad)",          { XX } },
6894     { "(bad)",          { XX } },
6895     { "(bad)",          { XX } },
6896     { "(bad)",          { XX } },
6897     { "(bad)",          { XX } },
6898     { "(bad)",          { XX } },
6899     { "(bad)",          { XX } },
6900     /* c0 */
6901     { "(bad)",          { XX } },
6902     { "vphaddbw",       { XM, EXxmm } },
6903     { "vphaddbd",       { XM, EXxmm } },
6904     { "vphaddbq",       { XM, EXxmm } },
6905     { "(bad)",          { XX } },
6906     { "(bad)",          { XX } },
6907     { "vphaddwd",       { XM, EXxmm } },
6908     { "vphaddwq",       { XM, EXxmm } },
6909     /* c8 */
6910     { "(bad)",          { XX } },
6911     { "(bad)",          { XX } },
6912     { "(bad)",          { XX } },
6913     { "vphadddq",       { XM, EXxmm } },
6914     { "(bad)",          { XX } },
6915     { "(bad)",          { XX } },
6916     { "(bad)",          { XX } },
6917     { "(bad)",          { XX } },
6918     /* d0 */
6919     { "(bad)",          { XX } },
6920     { "vphaddubw",      { XM, EXxmm } },
6921     { "vphaddubd",      { XM, EXxmm } },
6922     { "vphaddubq",      { XM, EXxmm } },
6923     { "(bad)",          { XX } },
6924     { "(bad)",          { XX } },
6925     { "vphadduwd",      { XM, EXxmm } },
6926     { "vphadduwq",      { XM, EXxmm } },
6927     /* d8 */
6928     { "(bad)",          { XX } },
6929     { "(bad)",          { XX } },
6930     { "(bad)",          { XX } },
6931     { "vphaddudq",      { XM, EXxmm } },
6932     { "(bad)",          { XX } },
6933     { "(bad)",          { XX } },
6934     { "(bad)",          { XX } },
6935     { "(bad)",          { XX } },
6936     /* e0 */
6937     { "(bad)",          { XX } },
6938     { "vphsubbw",       { XM, EXxmm } },
6939     { "vphsubwd",       { XM, EXxmm } },
6940     { "vphsubdq",       { XM, EXxmm } },
6941     { "(bad)",          { XX } },
6942     { "(bad)",          { XX } },
6943     { "(bad)",          { XX } },
6944     { "(bad)",          { XX } },
6945     /* e8 */
6946     { "(bad)",          { XX } },
6947     { "(bad)",          { XX } },
6948     { "(bad)",          { XX } },
6949     { "(bad)",          { XX } },
6950     { "(bad)",          { XX } },
6951     { "(bad)",          { XX } },
6952     { "(bad)",          { XX } },
6953     { "(bad)",          { XX } },
6954     /* f0 */
6955     { "(bad)",          { XX } },
6956     { "(bad)",          { XX } },
6957     { "(bad)",          { XX } },
6958     { "(bad)",          { XX } },
6959     { "(bad)",          { XX } },
6960     { "(bad)",          { XX } },
6961     { "(bad)",          { XX } },
6962     { "(bad)",          { XX } },
6963     /* f8 */
6964     { "(bad)",          { XX } },
6965     { "(bad)",          { XX } },
6966     { "(bad)",          { XX } },
6967     { "(bad)",          { XX } },
6968     { "(bad)",          { XX } },
6969     { "(bad)",          { XX } },
6970     { "(bad)",          { XX } },
6971     { "(bad)",          { XX } },
6972   },
6973   /* XOP_0A */
6974   {
6975     /* 00 */
6976     { "(bad)",          { XX } },
6977     { "(bad)",          { XX } },
6978     { "(bad)",          { XX } },
6979     { "(bad)",          { XX } },
6980     { "(bad)",          { XX } },
6981     { "(bad)",          { XX } },
6982     { "(bad)",          { XX } },
6983     { "(bad)",          { XX } },
6984     /* 08 */
6985     { "(bad)",          { XX } },
6986     { "(bad)",          { XX } },
6987     { "(bad)",          { XX } },
6988     { "(bad)",          { XX } },
6989     { "(bad)",          { XX } },
6990     { "(bad)",          { XX } },
6991     { "(bad)",          { XX } },
6992     { "(bad)",          { XX } },
6993     /* 10 */
6994     { "(bad)",          { XX } },
6995     { "(bad)",          { XX } },
6996     { REG_TABLE (REG_XOP_LWP) },
6997     { "(bad)",          { XX } },
6998     { "(bad)",          { XX } },
6999     { "(bad)",          { XX } },
7000     { "(bad)",          { XX } },
7001     { "(bad)",          { XX } },
7002     /* 18 */
7003     { "(bad)",          { XX } },
7004     { "(bad)",          { XX } },
7005     { "(bad)",          { XX } },
7006     { "(bad)",          { XX } },
7007     { "(bad)",          { XX } },
7008     { "(bad)",          { XX } },
7009     { "(bad)",          { XX } },
7010     { "(bad)",          { XX } },
7011     /* 20 */
7012     { "(bad)",          { XX } },
7013     { "(bad)",          { XX } },
7014     { "(bad)",          { XX } },
7015     { "(bad)",          { XX } },
7016     { "(bad)",          { XX } },
7017     { "(bad)",          { XX } },
7018     { "(bad)",          { XX } },
7019     { "(bad)",          { XX } },
7020     /* 28 */
7021     { "(bad)",          { XX } },
7022     { "(bad)",          { XX } },
7023     { "(bad)",          { XX } },
7024     { "(bad)",          { XX } },
7025     { "(bad)",          { XX } },
7026     { "(bad)",          { XX } },
7027     { "(bad)",          { XX } },
7028     { "(bad)",          { XX } },
7029     /* 30 */
7030     { "(bad)",          { XX } },
7031     { "(bad)",          { XX } },
7032     { "(bad)",          { XX } },
7033     { "(bad)",          { XX } },
7034     { "(bad)",          { XX } },
7035     { "(bad)",          { XX } },
7036     { "(bad)",          { XX } },
7037     { "(bad)",          { XX } },
7038     /* 38 */
7039     { "(bad)",          { XX } },
7040     { "(bad)",          { XX } },
7041     { "(bad)",          { XX } },
7042     { "(bad)",          { XX } },
7043     { "(bad)",          { XX } },
7044     { "(bad)",          { XX } },
7045     { "(bad)",          { XX } },
7046     { "(bad)",          { XX } },
7047     /* 40 */
7048     { "(bad)",          { XX } },
7049     { "(bad)",          { XX } },
7050     { "(bad)",          { XX } },
7051     { "(bad)",          { XX } },
7052     { "(bad)",          { XX } },
7053     { "(bad)",          { XX } },
7054     { "(bad)",          { XX } },
7055     { "(bad)",          { XX } },
7056     /* 48 */
7057     { "(bad)",          { XX } },
7058     { "(bad)",          { XX } },
7059     { "(bad)",          { XX } },
7060     { "(bad)",          { XX } },
7061     { "(bad)",          { XX } },
7062     { "(bad)",          { XX } },
7063     { "(bad)",          { XX } },
7064     { "(bad)",          { XX } },
7065     /* 50 */
7066     { "(bad)",          { XX } },
7067     { "(bad)",          { XX } },
7068     { "(bad)",          { XX } },
7069     { "(bad)",          { XX } },
7070     { "(bad)",          { XX } },
7071     { "(bad)",          { XX } },
7072     { "(bad)",          { XX } },
7073     { "(bad)",          { XX } },
7074     /* 58 */
7075     { "(bad)",          { XX } },
7076     { "(bad)",          { XX } },
7077     { "(bad)",          { XX } },
7078     { "(bad)",          { XX } },
7079     { "(bad)",          { XX } },
7080     { "(bad)",          { XX } },
7081     { "(bad)",          { XX } },
7082     { "(bad)",          { XX } },
7083     /* 60 */
7084     { "(bad)",          { XX } },
7085     { "(bad)",          { XX } },
7086     { "(bad)",          { XX } },
7087     { "(bad)",          { XX } },
7088     { "(bad)",          { XX } },
7089     { "(bad)",          { XX } },
7090     { "(bad)",          { XX } },
7091     { "(bad)",          { XX } },
7092     /* 68 */
7093     { "(bad)",          { XX } },
7094     { "(bad)",          { XX } },
7095     { "(bad)",          { XX } },
7096     { "(bad)",          { XX } },
7097     { "(bad)",          { XX } },
7098     { "(bad)",          { XX } },
7099     { "(bad)",          { XX } },
7100     { "(bad)",          { XX } },
7101     /* 70 */
7102     { "(bad)",          { XX } },
7103     { "(bad)",          { XX } },
7104     { "(bad)",          { XX } },
7105     { "(bad)",          { XX } },
7106     { "(bad)",          { XX } },
7107     { "(bad)",          { XX } },
7108     { "(bad)",          { XX } },
7109     { "(bad)",          { XX } },
7110     /* 78 */
7111     { "(bad)",          { XX } },
7112     { "(bad)",          { XX } },
7113     { "(bad)",          { XX } },
7114     { "(bad)",          { XX } },
7115     { "(bad)",          { XX } },
7116     { "(bad)",          { XX } },
7117     { "(bad)",          { XX } },
7118     { "(bad)",          { XX } },
7119     /* 80 */
7120     { "(bad)",          { XX } },
7121     { "(bad)",          { XX } },
7122     { "(bad)",          { XX } },
7123     { "(bad)",          { XX } },
7124     { "(bad)",          { XX } },
7125     { "(bad)",          { XX } },
7126     { "(bad)",          { XX } },
7127     { "(bad)",          { XX } },
7128     /* 88 */
7129     { "(bad)",          { XX } },
7130     { "(bad)",          { XX } },
7131     { "(bad)",          { XX } },
7132     { "(bad)",          { XX } },
7133     { "(bad)",          { XX } },
7134     { "(bad)",          { XX } },
7135     { "(bad)",          { XX } },
7136     { "(bad)",          { XX } },
7137     /* 90 */
7138     { "(bad)",          { XX } },
7139     { "(bad)",          { XX } },
7140     { "(bad)",          { XX } },
7141     { "(bad)",          { XX } },
7142     { "(bad)",          { XX } },
7143     { "(bad)",          { XX } },
7144     { "(bad)",          { XX } },
7145     { "(bad)",          { XX } },
7146     /* 98 */
7147     { "(bad)",          { XX } },
7148     { "(bad)",          { XX } },
7149     { "(bad)",          { XX } },
7150     { "(bad)",          { XX } },
7151     { "(bad)",          { XX } },
7152     { "(bad)",          { XX } },
7153     { "(bad)",          { XX } },
7154     { "(bad)",          { XX } },
7155     /* a0 */
7156     { "(bad)",          { XX } },
7157     { "(bad)",          { XX } },
7158     { "(bad)",          { XX } },
7159     { "(bad)",          { XX } },
7160     { "(bad)",          { XX } },
7161     { "(bad)",          { XX } },
7162     { "(bad)",          { XX } },
7163     { "(bad)",          { XX } },
7164     /* a8 */
7165     { "(bad)",          { XX } },
7166     { "(bad)",          { XX } },
7167     { "(bad)",          { XX } },
7168     { "(bad)",          { XX } },
7169     { "(bad)",          { XX } },
7170     { "(bad)",          { XX } },
7171     { "(bad)",          { XX } },
7172     { "(bad)",          { XX } },
7173     /* b0 */
7174     { "(bad)",          { XX } },
7175     { "(bad)",          { XX } },
7176     { "(bad)",          { XX } },
7177     { "(bad)",          { XX } },
7178     { "(bad)",          { XX } },
7179     { "(bad)",          { XX } },
7180     { "(bad)",          { XX } },
7181     { "(bad)",          { XX } },
7182     /* b8 */
7183     { "(bad)",          { XX } },
7184     { "(bad)",          { XX } },
7185     { "(bad)",          { XX } },
7186     { "(bad)",          { XX } },
7187     { "(bad)",          { XX } },
7188     { "(bad)",          { XX } },
7189     { "(bad)",          { XX } },
7190     { "(bad)",          { XX } },
7191     /* c0 */
7192     { "(bad)",          { XX } },
7193     { "(bad)",          { XX } },
7194     { "(bad)",          { XX } },
7195     { "(bad)",          { XX } },
7196     { "(bad)",          { XX } },
7197     { "(bad)",          { XX } },
7198     { "(bad)",          { XX } },
7199     { "(bad)",          { XX } },
7200     /* c8 */
7201     { "(bad)",          { XX } },
7202     { "(bad)",          { XX } },
7203     { "(bad)",          { XX } },
7204     { "(bad)",          { XX } },
7205     { "(bad)",          { XX } },
7206     { "(bad)",          { XX } },
7207     { "(bad)",          { XX } },
7208     { "(bad)",          { XX } },
7209     /* d0 */
7210     { "(bad)",          { XX } },
7211     { "(bad)",          { XX } },
7212     { "(bad)",          { XX } },
7213     { "(bad)",          { XX } },
7214     { "(bad)",          { XX } },
7215     { "(bad)",          { XX } },
7216     { "(bad)",          { XX } },
7217     { "(bad)",          { XX } },
7218     /* d8 */
7219     { "(bad)",          { XX } },
7220     { "(bad)",          { XX } },
7221     { "(bad)",          { XX } },
7222     { "(bad)",          { XX } },
7223     { "(bad)",          { XX } },
7224     { "(bad)",          { XX } },
7225     { "(bad)",          { XX } },
7226     { "(bad)",          { XX } },
7227     /* e0 */
7228     { "(bad)",          { XX } },
7229     { "(bad)",          { XX } },
7230     { "(bad)",          { XX } },
7231     { "(bad)",          { XX } },
7232     { "(bad)",          { XX } },
7233     { "(bad)",          { XX } },
7234     { "(bad)",          { XX } },
7235     { "(bad)",          { XX } },
7236     /* e8 */
7237     { "(bad)",          { XX } },
7238     { "(bad)",          { XX } },
7239     { "(bad)",          { XX } },
7240     { "(bad)",          { XX } },
7241     { "(bad)",          { XX } },
7242     { "(bad)",          { XX } },
7243     { "(bad)",          { XX } },
7244     { "(bad)",          { XX } },
7245     /* f0 */
7246     { "(bad)",          { XX } },
7247     { "(bad)",          { XX } },
7248     { "(bad)",          { XX } },
7249     { "(bad)",          { XX } },
7250     { "(bad)",          { XX } },
7251     { "(bad)",          { XX } },
7252     { "(bad)",          { XX } },
7253     { "(bad)",          { XX } },
7254     /* f8 */
7255     { "(bad)",          { XX } },
7256     { "(bad)",          { XX } },
7257     { "(bad)",          { XX } },
7258     { "(bad)",          { XX } },
7259     { "(bad)",          { XX } },
7260     { "(bad)",          { XX } },
7261     { "(bad)",          { XX } },
7262     { "(bad)",          { XX } },
7263   },
7264 };
7265
7266 static const struct dis386 vex_table[][256] = {
7267   /* VEX_0F */
7268   {
7269     /* 00 */
7270     { "(bad)",          { XX } },
7271     { "(bad)",          { XX } },
7272     { "(bad)",          { XX } },
7273     { "(bad)",          { XX } },
7274     { "(bad)",          { XX } },
7275     { "(bad)",          { XX } },
7276     { "(bad)",          { XX } },
7277     { "(bad)",          { XX } },
7278     /* 08 */
7279     { "(bad)",          { XX } },
7280     { "(bad)",          { XX } },
7281     { "(bad)",          { XX } },
7282     { "(bad)",          { XX } },
7283     { "(bad)",          { XX } },
7284     { "(bad)",          { XX } },
7285     { "(bad)",          { XX } },
7286     { "(bad)",          { XX } },
7287     /* 10 */
7288     { PREFIX_TABLE (PREFIX_VEX_10) },
7289     { PREFIX_TABLE (PREFIX_VEX_11) },
7290     { PREFIX_TABLE (PREFIX_VEX_12) },
7291     { MOD_TABLE (MOD_VEX_13) },
7292     { "vunpcklpX",      { XM, Vex, EXx } },
7293     { "vunpckhpX",      { XM, Vex, EXx } },
7294     { PREFIX_TABLE (PREFIX_VEX_16) },
7295     { MOD_TABLE (MOD_VEX_17) },
7296     /* 18 */
7297     { "(bad)",          { XX } },
7298     { "(bad)",          { XX } },
7299     { "(bad)",          { XX } },
7300     { "(bad)",          { XX } },
7301     { "(bad)",          { XX } },
7302     { "(bad)",          { XX } },
7303     { "(bad)",          { XX } },
7304     { "(bad)",          { XX } },
7305     /* 20 */
7306     { "(bad)",          { XX } },
7307     { "(bad)",          { XX } },
7308     { "(bad)",          { XX } },
7309     { "(bad)",          { XX } },
7310     { "(bad)",          { XX } },
7311     { "(bad)",          { XX } },
7312     { "(bad)",          { XX } },
7313     { "(bad)",          { XX } },
7314     /* 28 */
7315     { "vmovapX",        { XM, EXx } },
7316     { "vmovapX",        { EXxS, XM } },
7317     { PREFIX_TABLE (PREFIX_VEX_2A) },
7318     { MOD_TABLE (MOD_VEX_2B) },
7319     { PREFIX_TABLE (PREFIX_VEX_2C) },
7320     { PREFIX_TABLE (PREFIX_VEX_2D) },
7321     { PREFIX_TABLE (PREFIX_VEX_2E) },
7322     { PREFIX_TABLE (PREFIX_VEX_2F) },
7323     /* 30 */
7324     { "(bad)",          { XX } },
7325     { "(bad)",          { XX } },
7326     { "(bad)",          { XX } },
7327     { "(bad)",          { XX } },
7328     { "(bad)",          { XX } },
7329     { "(bad)",          { XX } },
7330     { "(bad)",          { XX } },
7331     { "(bad)",          { XX } },
7332     /* 38 */
7333     { "(bad)",          { XX } },
7334     { "(bad)",          { XX } },
7335     { "(bad)",          { XX } },
7336     { "(bad)",          { XX } },
7337     { "(bad)",          { XX } },
7338     { "(bad)",          { XX } },
7339     { "(bad)",          { XX } },
7340     { "(bad)",          { XX } },
7341     /* 40 */
7342     { "(bad)",          { XX } },
7343     { "(bad)",          { XX } },
7344     { "(bad)",          { XX } },
7345     { "(bad)",          { XX } },
7346     { "(bad)",          { XX } },
7347     { "(bad)",          { XX } },
7348     { "(bad)",          { XX } },
7349     { "(bad)",          { XX } },
7350     /* 48 */
7351     { "(bad)",          { XX } },
7352     { "(bad)",          { XX } },
7353     { "(bad)",          { XX } },
7354     { "(bad)",          { XX } },
7355     { "(bad)",          { XX } },
7356     { "(bad)",          { XX } },
7357     { "(bad)",          { XX } },
7358     { "(bad)",          { XX } },
7359     /* 50 */
7360     { MOD_TABLE (MOD_VEX_51) },
7361     { PREFIX_TABLE (PREFIX_VEX_51) },
7362     { PREFIX_TABLE (PREFIX_VEX_52) },
7363     { PREFIX_TABLE (PREFIX_VEX_53) },
7364     { "vandpX",         { XM, Vex, EXx } },
7365     { "vandnpX",        { XM, Vex, EXx } },
7366     { "vorpX",          { XM, Vex, EXx } },
7367     { "vxorpX",         { XM, Vex, EXx } },
7368     /* 58 */
7369     { PREFIX_TABLE (PREFIX_VEX_58) },
7370     { PREFIX_TABLE (PREFIX_VEX_59) },
7371     { PREFIX_TABLE (PREFIX_VEX_5A) },
7372     { PREFIX_TABLE (PREFIX_VEX_5B) },
7373     { PREFIX_TABLE (PREFIX_VEX_5C) },
7374     { PREFIX_TABLE (PREFIX_VEX_5D) },
7375     { PREFIX_TABLE (PREFIX_VEX_5E) },
7376     { PREFIX_TABLE (PREFIX_VEX_5F) },
7377     /* 60 */
7378     { PREFIX_TABLE (PREFIX_VEX_60) },
7379     { PREFIX_TABLE (PREFIX_VEX_61) },
7380     { PREFIX_TABLE (PREFIX_VEX_62) },
7381     { PREFIX_TABLE (PREFIX_VEX_63) },
7382     { PREFIX_TABLE (PREFIX_VEX_64) },
7383     { PREFIX_TABLE (PREFIX_VEX_65) },
7384     { PREFIX_TABLE (PREFIX_VEX_66) },
7385     { PREFIX_TABLE (PREFIX_VEX_67) },
7386     /* 68 */
7387     { PREFIX_TABLE (PREFIX_VEX_68) },
7388     { PREFIX_TABLE (PREFIX_VEX_69) },
7389     { PREFIX_TABLE (PREFIX_VEX_6A) },
7390     { PREFIX_TABLE (PREFIX_VEX_6B) },
7391     { PREFIX_TABLE (PREFIX_VEX_6C) },
7392     { PREFIX_TABLE (PREFIX_VEX_6D) },
7393     { PREFIX_TABLE (PREFIX_VEX_6E) },
7394     { PREFIX_TABLE (PREFIX_VEX_6F) },
7395     /* 70 */
7396     { PREFIX_TABLE (PREFIX_VEX_70) },
7397     { REG_TABLE (REG_VEX_71) },
7398     { REG_TABLE (REG_VEX_72) },
7399     { REG_TABLE (REG_VEX_73) },
7400     { PREFIX_TABLE (PREFIX_VEX_74) },
7401     { PREFIX_TABLE (PREFIX_VEX_75) },
7402     { PREFIX_TABLE (PREFIX_VEX_76) },
7403     { PREFIX_TABLE (PREFIX_VEX_77) },
7404     /* 78 */
7405     { "(bad)",          { XX } },
7406     { "(bad)",          { XX } },
7407     { "(bad)",          { XX } },
7408     { "(bad)",          { XX } },
7409     { PREFIX_TABLE (PREFIX_VEX_7C) },
7410     { PREFIX_TABLE (PREFIX_VEX_7D) },
7411     { PREFIX_TABLE (PREFIX_VEX_7E) },
7412     { PREFIX_TABLE (PREFIX_VEX_7F) },
7413     /* 80 */
7414     { "(bad)",          { XX } },
7415     { "(bad)",          { XX } },
7416     { "(bad)",          { XX } },
7417     { "(bad)",          { XX } },
7418     { "(bad)",          { XX } },
7419     { "(bad)",          { XX } },
7420     { "(bad)",          { XX } },
7421     { "(bad)",          { XX } },
7422     /* 88 */
7423     { "(bad)",          { XX } },
7424     { "(bad)",          { XX } },
7425     { "(bad)",          { XX } },
7426     { "(bad)",          { XX } },
7427     { "(bad)",          { XX } },
7428     { "(bad)",          { XX } },
7429     { "(bad)",          { XX } },
7430     { "(bad)",          { XX } },
7431     /* 90 */
7432     { "(bad)",          { XX } },
7433     { "(bad)",          { XX } },
7434     { "(bad)",          { XX } },
7435     { "(bad)",          { XX } },
7436     { "(bad)",          { XX } },
7437     { "(bad)",          { XX } },
7438     { "(bad)",          { XX } },
7439     { "(bad)",          { XX } },
7440     /* 98 */
7441     { "(bad)",          { XX } },
7442     { "(bad)",          { XX } },
7443     { "(bad)",          { XX } },
7444     { "(bad)",          { XX } },
7445     { "(bad)",          { XX } },
7446     { "(bad)",          { XX } },
7447     { "(bad)",          { XX } },
7448     { "(bad)",          { XX } },
7449     /* a0 */
7450     { "(bad)",          { XX } },
7451     { "(bad)",          { XX } },
7452     { "(bad)",          { XX } },
7453     { "(bad)",          { XX } },
7454     { "(bad)",          { XX } },
7455     { "(bad)",          { XX } },
7456     { "(bad)",          { XX } },
7457     { "(bad)",          { XX } },
7458     /* a8 */
7459     { "(bad)",          { XX } },
7460     { "(bad)",          { XX } },
7461     { "(bad)",          { XX } },
7462     { "(bad)",          { XX } },
7463     { "(bad)",          { XX } },
7464     { "(bad)",          { XX } },
7465     { REG_TABLE (REG_VEX_AE) },
7466     { "(bad)",          { XX } },
7467     /* b0 */
7468     { "(bad)",          { XX } },
7469     { "(bad)",          { XX } },
7470     { "(bad)",          { XX } },
7471     { "(bad)",          { XX } },
7472     { "(bad)",          { XX } },
7473     { "(bad)",          { XX } },
7474     { "(bad)",          { XX } },
7475     { "(bad)",          { XX } },
7476     /* b8 */
7477     { "(bad)",          { XX } },
7478     { "(bad)",          { XX } },
7479     { "(bad)",          { XX } },
7480     { "(bad)",          { XX } },
7481     { "(bad)",          { XX } },
7482     { "(bad)",          { XX } },
7483     { "(bad)",          { XX } },
7484     { "(bad)",          { XX } },
7485     /* c0 */
7486     { "(bad)",          { XX } },
7487     { "(bad)",          { XX } },
7488     { PREFIX_TABLE (PREFIX_VEX_C2) },
7489     { "(bad)",          { XX } },
7490     { PREFIX_TABLE (PREFIX_VEX_C4) },
7491     { PREFIX_TABLE (PREFIX_VEX_C5) },
7492     { "vshufpX",        { XM, Vex, EXx, Ib } },
7493     { "(bad)",          { XX } },
7494     /* c8 */
7495     { "(bad)",          { XX } },
7496     { "(bad)",          { XX } },
7497     { "(bad)",          { XX } },
7498     { "(bad)",          { XX } },
7499     { "(bad)",          { XX } },
7500     { "(bad)",          { XX } },
7501     { "(bad)",          { XX } },
7502     { "(bad)",          { XX } },
7503     /* d0 */
7504     { PREFIX_TABLE (PREFIX_VEX_D0) },
7505     { PREFIX_TABLE (PREFIX_VEX_D1) },
7506     { PREFIX_TABLE (PREFIX_VEX_D2) },
7507     { PREFIX_TABLE (PREFIX_VEX_D3) },
7508     { PREFIX_TABLE (PREFIX_VEX_D4) },
7509     { PREFIX_TABLE (PREFIX_VEX_D5) },
7510     { PREFIX_TABLE (PREFIX_VEX_D6) },
7511     { PREFIX_TABLE (PREFIX_VEX_D7) },
7512     /* d8 */
7513     { PREFIX_TABLE (PREFIX_VEX_D8) },
7514     { PREFIX_TABLE (PREFIX_VEX_D9) },
7515     { PREFIX_TABLE (PREFIX_VEX_DA) },
7516     { PREFIX_TABLE (PREFIX_VEX_DB) },
7517     { PREFIX_TABLE (PREFIX_VEX_DC) },
7518     { PREFIX_TABLE (PREFIX_VEX_DD) },
7519     { PREFIX_TABLE (PREFIX_VEX_DE) },
7520     { PREFIX_TABLE (PREFIX_VEX_DF) },
7521     /* e0 */
7522     { PREFIX_TABLE (PREFIX_VEX_E0) },
7523     { PREFIX_TABLE (PREFIX_VEX_E1) },
7524     { PREFIX_TABLE (PREFIX_VEX_E2) },
7525     { PREFIX_TABLE (PREFIX_VEX_E3) },
7526     { PREFIX_TABLE (PREFIX_VEX_E4) },
7527     { PREFIX_TABLE (PREFIX_VEX_E5) },
7528     { PREFIX_TABLE (PREFIX_VEX_E6) },
7529     { PREFIX_TABLE (PREFIX_VEX_E7) },
7530     /* e8 */
7531     { PREFIX_TABLE (PREFIX_VEX_E8) },
7532     { PREFIX_TABLE (PREFIX_VEX_E9) },
7533     { PREFIX_TABLE (PREFIX_VEX_EA) },
7534     { PREFIX_TABLE (PREFIX_VEX_EB) },
7535     { PREFIX_TABLE (PREFIX_VEX_EC) },
7536     { PREFIX_TABLE (PREFIX_VEX_ED) },
7537     { PREFIX_TABLE (PREFIX_VEX_EE) },
7538     { PREFIX_TABLE (PREFIX_VEX_EF) },
7539     /* f0 */
7540     { PREFIX_TABLE (PREFIX_VEX_F0) },
7541     { PREFIX_TABLE (PREFIX_VEX_F1) },
7542     { PREFIX_TABLE (PREFIX_VEX_F2) },
7543     { PREFIX_TABLE (PREFIX_VEX_F3) },
7544     { PREFIX_TABLE (PREFIX_VEX_F4) },
7545     { PREFIX_TABLE (PREFIX_VEX_F5) },
7546     { PREFIX_TABLE (PREFIX_VEX_F6) },
7547     { PREFIX_TABLE (PREFIX_VEX_F7) },
7548     /* f8 */
7549     { PREFIX_TABLE (PREFIX_VEX_F8) },
7550     { PREFIX_TABLE (PREFIX_VEX_F9) },
7551     { PREFIX_TABLE (PREFIX_VEX_FA) },
7552     { PREFIX_TABLE (PREFIX_VEX_FB) },
7553     { PREFIX_TABLE (PREFIX_VEX_FC) },
7554     { PREFIX_TABLE (PREFIX_VEX_FD) },
7555     { PREFIX_TABLE (PREFIX_VEX_FE) },
7556     { "(bad)",          { XX } },
7557   },
7558   /* VEX_0F38 */
7559   {
7560     /* 00 */
7561     { PREFIX_TABLE (PREFIX_VEX_3800) },
7562     { PREFIX_TABLE (PREFIX_VEX_3801) },
7563     { PREFIX_TABLE (PREFIX_VEX_3802) },
7564     { PREFIX_TABLE (PREFIX_VEX_3803) },
7565     { PREFIX_TABLE (PREFIX_VEX_3804) },
7566     { PREFIX_TABLE (PREFIX_VEX_3805) },
7567     { PREFIX_TABLE (PREFIX_VEX_3806) },
7568     { PREFIX_TABLE (PREFIX_VEX_3807) },
7569     /* 08 */
7570     { PREFIX_TABLE (PREFIX_VEX_3808) },
7571     { PREFIX_TABLE (PREFIX_VEX_3809) },
7572     { PREFIX_TABLE (PREFIX_VEX_380A) },
7573     { PREFIX_TABLE (PREFIX_VEX_380B) },
7574     { PREFIX_TABLE (PREFIX_VEX_380C) },
7575     { PREFIX_TABLE (PREFIX_VEX_380D) },
7576     { PREFIX_TABLE (PREFIX_VEX_380E) },
7577     { PREFIX_TABLE (PREFIX_VEX_380F) },
7578     /* 10 */
7579     { "(bad)",          { XX } },
7580     { "(bad)",          { XX } },
7581     { "(bad)",          { XX } },
7582     { "(bad)",          { XX } },
7583     { "(bad)",          { XX } },
7584     { "(bad)",          { XX } },
7585     { "(bad)",          { XX } },
7586     { PREFIX_TABLE (PREFIX_VEX_3817) },
7587     /* 18 */
7588     { PREFIX_TABLE (PREFIX_VEX_3818) },
7589     { PREFIX_TABLE (PREFIX_VEX_3819) },
7590     { PREFIX_TABLE (PREFIX_VEX_381A) },
7591     { "(bad)",          { XX } },
7592     { PREFIX_TABLE (PREFIX_VEX_381C) },
7593     { PREFIX_TABLE (PREFIX_VEX_381D) },
7594     { PREFIX_TABLE (PREFIX_VEX_381E) },
7595     { "(bad)",          { XX } },
7596     /* 20 */
7597     { PREFIX_TABLE (PREFIX_VEX_3820) },
7598     { PREFIX_TABLE (PREFIX_VEX_3821) },
7599     { PREFIX_TABLE (PREFIX_VEX_3822) },
7600     { PREFIX_TABLE (PREFIX_VEX_3823) },
7601     { PREFIX_TABLE (PREFIX_VEX_3824) },
7602     { PREFIX_TABLE (PREFIX_VEX_3825) },
7603     { "(bad)",          { XX } },
7604     { "(bad)",          { XX } },
7605     /* 28 */
7606     { PREFIX_TABLE (PREFIX_VEX_3828) },
7607     { PREFIX_TABLE (PREFIX_VEX_3829) },
7608     { PREFIX_TABLE (PREFIX_VEX_382A) },
7609     { PREFIX_TABLE (PREFIX_VEX_382B) },
7610     { PREFIX_TABLE (PREFIX_VEX_382C) },
7611     { PREFIX_TABLE (PREFIX_VEX_382D) },
7612     { PREFIX_TABLE (PREFIX_VEX_382E) },
7613     { PREFIX_TABLE (PREFIX_VEX_382F) },
7614     /* 30 */
7615     { PREFIX_TABLE (PREFIX_VEX_3830) },
7616     { PREFIX_TABLE (PREFIX_VEX_3831) },
7617     { PREFIX_TABLE (PREFIX_VEX_3832) },
7618     { PREFIX_TABLE (PREFIX_VEX_3833) },
7619     { PREFIX_TABLE (PREFIX_VEX_3834) },
7620     { PREFIX_TABLE (PREFIX_VEX_3835) },
7621     { "(bad)",          { XX } },
7622     { PREFIX_TABLE (PREFIX_VEX_3837) },
7623     /* 38 */
7624     { PREFIX_TABLE (PREFIX_VEX_3838) },
7625     { PREFIX_TABLE (PREFIX_VEX_3839) },
7626     { PREFIX_TABLE (PREFIX_VEX_383A) },
7627     { PREFIX_TABLE (PREFIX_VEX_383B) },
7628     { PREFIX_TABLE (PREFIX_VEX_383C) },
7629     { PREFIX_TABLE (PREFIX_VEX_383D) },
7630     { PREFIX_TABLE (PREFIX_VEX_383E) },
7631     { PREFIX_TABLE (PREFIX_VEX_383F) },
7632     /* 40 */
7633     { PREFIX_TABLE (PREFIX_VEX_3840) },
7634     { PREFIX_TABLE (PREFIX_VEX_3841) },
7635     { "(bad)",          { XX } },
7636     { "(bad)",          { XX } },
7637     { "(bad)",          { XX } },
7638     { "(bad)",          { XX } },
7639     { "(bad)",          { XX } },
7640     { "(bad)",          { XX } },
7641     /* 48 */
7642     { "(bad)",          { XX } },
7643     { "(bad)",          { XX } },
7644     { "(bad)",          { XX } },
7645     { "(bad)",          { XX } },
7646     { "(bad)",          { XX } },
7647     { "(bad)",          { XX } },
7648     { "(bad)",          { XX } },
7649     { "(bad)",          { XX } },
7650     /* 50 */
7651     { "(bad)",          { XX } },
7652     { "(bad)",          { XX } },
7653     { "(bad)",          { XX } },
7654     { "(bad)",          { XX } },
7655     { "(bad)",          { XX } },
7656     { "(bad)",          { XX } },
7657     { "(bad)",          { XX } },
7658     { "(bad)",          { XX } },
7659     /* 58 */
7660     { "(bad)",          { XX } },
7661     { "(bad)",          { XX } },
7662     { "(bad)",          { XX } },
7663     { "(bad)",          { XX } },
7664     { "(bad)",          { XX } },
7665     { "(bad)",          { XX } },
7666     { "(bad)",          { XX } },
7667     { "(bad)",          { XX } },
7668     /* 60 */
7669     { "(bad)",          { XX } },
7670     { "(bad)",          { XX } },
7671     { "(bad)",          { XX } },
7672     { "(bad)",          { XX } },
7673     { "(bad)",          { XX } },
7674     { "(bad)",          { XX } },
7675     { "(bad)",          { XX } },
7676     { "(bad)",          { XX } },
7677     /* 68 */
7678     { "(bad)",          { XX } },
7679     { "(bad)",          { XX } },
7680     { "(bad)",          { XX } },
7681     { "(bad)",          { XX } },
7682     { "(bad)",          { XX } },
7683     { "(bad)",          { XX } },
7684     { "(bad)",          { XX } },
7685     { "(bad)",          { XX } },
7686     /* 70 */
7687     { "(bad)",          { XX } },
7688     { "(bad)",          { XX } },
7689     { "(bad)",          { XX } },
7690     { "(bad)",          { XX } },
7691     { "(bad)",          { XX } },
7692     { "(bad)",          { XX } },
7693     { "(bad)",          { XX } },
7694     { "(bad)",          { XX } },
7695     /* 78 */
7696     { "(bad)",          { XX } },
7697     { "(bad)",          { XX } },
7698     { "(bad)",          { XX } },
7699     { "(bad)",          { XX } },
7700     { "(bad)",          { XX } },
7701     { "(bad)",          { XX } },
7702     { "(bad)",          { XX } },
7703     { "(bad)",          { XX } },
7704     /* 80 */
7705     { "(bad)",          { XX } },
7706     { "(bad)",          { XX } },
7707     { "(bad)",          { XX } },
7708     { "(bad)",          { XX } },
7709     { "(bad)",          { XX } },
7710     { "(bad)",          { XX } },
7711     { "(bad)",          { XX } },
7712     { "(bad)",          { XX } },
7713     /* 88 */
7714     { "(bad)",          { XX } },
7715     { "(bad)",          { XX } },
7716     { "(bad)",          { XX } },
7717     { "(bad)",          { XX } },
7718     { "(bad)",          { XX } },
7719     { "(bad)",          { XX } },
7720     { "(bad)",          { XX } },
7721     { "(bad)",          { XX } },
7722     /* 90 */
7723     { "(bad)",          { XX } },
7724     { "(bad)",          { XX } },
7725     { "(bad)",          { XX } },
7726     { "(bad)",          { XX } },
7727     { "(bad)",          { XX } },
7728     { "(bad)",          { XX } },
7729     { PREFIX_TABLE (PREFIX_VEX_3896) },
7730     { PREFIX_TABLE (PREFIX_VEX_3897) },
7731     /* 98 */
7732     { PREFIX_TABLE (PREFIX_VEX_3898) },
7733     { PREFIX_TABLE (PREFIX_VEX_3899) },
7734     { PREFIX_TABLE (PREFIX_VEX_389A) },
7735     { PREFIX_TABLE (PREFIX_VEX_389B) },
7736     { PREFIX_TABLE (PREFIX_VEX_389C) },
7737     { PREFIX_TABLE (PREFIX_VEX_389D) },
7738     { PREFIX_TABLE (PREFIX_VEX_389E) },
7739     { PREFIX_TABLE (PREFIX_VEX_389F) },
7740     /* a0 */
7741     { "(bad)",          { XX } },
7742     { "(bad)",          { XX } },
7743     { "(bad)",          { XX } },
7744     { "(bad)",          { XX } },
7745     { "(bad)",          { XX } },
7746     { "(bad)",          { XX } },
7747     { PREFIX_TABLE (PREFIX_VEX_38A6) },
7748     { PREFIX_TABLE (PREFIX_VEX_38A7) },
7749     /* a8 */
7750     { PREFIX_TABLE (PREFIX_VEX_38A8) },
7751     { PREFIX_TABLE (PREFIX_VEX_38A9) },
7752     { PREFIX_TABLE (PREFIX_VEX_38AA) },
7753     { PREFIX_TABLE (PREFIX_VEX_38AB) },
7754     { PREFIX_TABLE (PREFIX_VEX_38AC) },
7755     { PREFIX_TABLE (PREFIX_VEX_38AD) },
7756     { PREFIX_TABLE (PREFIX_VEX_38AE) },
7757     { PREFIX_TABLE (PREFIX_VEX_38AF) },
7758     /* b0 */
7759     { "(bad)",          { XX } },
7760     { "(bad)",          { XX } },
7761     { "(bad)",          { XX } },
7762     { "(bad)",          { XX } },
7763     { "(bad)",          { XX } },
7764     { "(bad)",          { XX } },
7765     { PREFIX_TABLE (PREFIX_VEX_38B6) },
7766     { PREFIX_TABLE (PREFIX_VEX_38B7) },
7767     /* b8 */
7768     { PREFIX_TABLE (PREFIX_VEX_38B8) },
7769     { PREFIX_TABLE (PREFIX_VEX_38B9) },
7770     { PREFIX_TABLE (PREFIX_VEX_38BA) },
7771     { PREFIX_TABLE (PREFIX_VEX_38BB) },
7772     { PREFIX_TABLE (PREFIX_VEX_38BC) },
7773     { PREFIX_TABLE (PREFIX_VEX_38BD) },
7774     { PREFIX_TABLE (PREFIX_VEX_38BE) },
7775     { PREFIX_TABLE (PREFIX_VEX_38BF) },
7776     /* c0 */
7777     { "(bad)",          { XX } },
7778     { "(bad)",          { XX } },
7779     { "(bad)",          { XX } },
7780     { "(bad)",          { XX } },
7781     { "(bad)",          { XX } },
7782     { "(bad)",          { XX } },
7783     { "(bad)",          { XX } },
7784     { "(bad)",          { XX } },
7785     /* c8 */
7786     { "(bad)",          { XX } },
7787     { "(bad)",          { XX } },
7788     { "(bad)",          { XX } },
7789     { "(bad)",          { XX } },
7790     { "(bad)",          { XX } },
7791     { "(bad)",          { XX } },
7792     { "(bad)",          { XX } },
7793     { "(bad)",          { XX } },
7794     /* d0 */
7795     { "(bad)",          { XX } },
7796     { "(bad)",          { XX } },
7797     { "(bad)",          { XX } },
7798     { "(bad)",          { XX } },
7799     { "(bad)",          { XX } },
7800     { "(bad)",          { XX } },
7801     { "(bad)",          { XX } },
7802     { "(bad)",          { XX } },
7803     /* d8 */
7804     { "(bad)",          { XX } },
7805     { "(bad)",          { XX } },
7806     { "(bad)",          { XX } },
7807     { PREFIX_TABLE (PREFIX_VEX_38DB) },
7808     { PREFIX_TABLE (PREFIX_VEX_38DC) },
7809     { PREFIX_TABLE (PREFIX_VEX_38DD) },
7810     { PREFIX_TABLE (PREFIX_VEX_38DE) },
7811     { PREFIX_TABLE (PREFIX_VEX_38DF) },
7812     /* e0 */
7813     { "(bad)",          { XX } },
7814     { "(bad)",          { XX } },
7815     { "(bad)",          { XX } },
7816     { "(bad)",          { XX } },
7817     { "(bad)",          { XX } },
7818     { "(bad)",          { XX } },
7819     { "(bad)",          { XX } },
7820     { "(bad)",          { XX } },
7821     /* e8 */
7822     { "(bad)",          { XX } },
7823     { "(bad)",          { XX } },
7824     { "(bad)",          { XX } },
7825     { "(bad)",          { XX } },
7826     { "(bad)",          { XX } },
7827     { "(bad)",          { XX } },
7828     { "(bad)",          { XX } },
7829     { "(bad)",          { XX } },
7830     /* f0 */
7831     { "(bad)",          { XX } },
7832     { "(bad)",          { XX } },
7833     { "(bad)",          { XX } },
7834     { "(bad)",          { XX } },
7835     { "(bad)",          { XX } },
7836     { "(bad)",          { XX } },
7837     { "(bad)",          { XX } },
7838     { "(bad)",          { XX } },
7839     /* f8 */
7840     { "(bad)",          { XX } },
7841     { "(bad)",          { XX } },
7842     { "(bad)",          { XX } },
7843     { "(bad)",          { XX } },
7844     { "(bad)",          { XX } },
7845     { "(bad)",          { XX } },
7846     { "(bad)",          { XX } },
7847     { "(bad)",          { XX } },
7848   },
7849   /* VEX_0F3A */
7850   {
7851     /* 00 */
7852     { "(bad)",          { XX } },
7853     { "(bad)",          { XX } },
7854     { "(bad)",          { XX } },
7855     { "(bad)",          { XX } },
7856     { PREFIX_TABLE (PREFIX_VEX_3A04) },
7857     { PREFIX_TABLE (PREFIX_VEX_3A05) },
7858     { PREFIX_TABLE (PREFIX_VEX_3A06) },
7859     { "(bad)",          { XX } },
7860     /* 08 */
7861     { PREFIX_TABLE (PREFIX_VEX_3A08) },
7862     { PREFIX_TABLE (PREFIX_VEX_3A09) },
7863     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7864     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7865     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7866     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7867     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7868     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7869     /* 10 */
7870     { "(bad)",          { XX } },
7871     { "(bad)",          { XX } },
7872     { "(bad)",          { XX } },
7873     { "(bad)",          { XX } },
7874     { PREFIX_TABLE (PREFIX_VEX_3A14) },
7875     { PREFIX_TABLE (PREFIX_VEX_3A15) },
7876     { PREFIX_TABLE (PREFIX_VEX_3A16) },
7877     { PREFIX_TABLE (PREFIX_VEX_3A17) },
7878     /* 18 */
7879     { PREFIX_TABLE (PREFIX_VEX_3A18) },
7880     { PREFIX_TABLE (PREFIX_VEX_3A19) },
7881     { "(bad)",          { XX } },
7882     { "(bad)",          { XX } },
7883     { "(bad)",          { XX } },
7884     { "(bad)",          { XX } },
7885     { "(bad)",          { XX } },
7886     { "(bad)",          { XX } },
7887     /* 20 */
7888     { PREFIX_TABLE (PREFIX_VEX_3A20) },
7889     { PREFIX_TABLE (PREFIX_VEX_3A21) },
7890     { PREFIX_TABLE (PREFIX_VEX_3A22) },
7891     { "(bad)",          { XX } },
7892     { "(bad)",          { XX } },
7893     { "(bad)",          { XX } },
7894     { "(bad)",          { XX } },
7895     { "(bad)",          { XX } },
7896     /* 28 */
7897     { "(bad)",          { XX } },
7898     { "(bad)",          { XX } },
7899     { "(bad)",          { XX } },
7900     { "(bad)",          { XX } },
7901     { "(bad)",          { XX } },
7902     { "(bad)",          { XX } },
7903     { "(bad)",          { XX } },
7904     { "(bad)",          { XX } },
7905     /* 30 */
7906     { "(bad)",          { XX } },
7907     { "(bad)",          { XX } },
7908     { "(bad)",          { XX } },
7909     { "(bad)",          { XX } },
7910     { "(bad)",          { XX } },
7911     { "(bad)",          { XX } },
7912     { "(bad)",          { XX } },
7913     { "(bad)",          { XX } },
7914     /* 38 */
7915     { "(bad)",          { XX } },
7916     { "(bad)",          { XX } },
7917     { "(bad)",          { XX } },
7918     { "(bad)",          { XX } },
7919     { "(bad)",          { XX } },
7920     { "(bad)",          { XX } },
7921     { "(bad)",          { XX } },
7922     { "(bad)",          { XX } },
7923     /* 40 */
7924     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7925     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7926     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7927     { "(bad)",          { XX } },
7928     { PREFIX_TABLE (PREFIX_VEX_3A44) },
7929     { "(bad)",          { XX } },
7930     { "(bad)",          { XX } },
7931     { "(bad)",          { XX } },
7932     /* 48 */
7933     { "(bad)",          { XX } },
7934     { "(bad)",          { XX } },
7935     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7936     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7937     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7938     { "(bad)",          { XX } },
7939     { "(bad)",          { XX } },
7940     { "(bad)",          { XX } },
7941     /* 50 */
7942     { "(bad)",          { XX } },
7943     { "(bad)",          { XX } },
7944     { "(bad)",          { XX } },
7945     { "(bad)",          { XX } },
7946     { "(bad)",          { XX } },
7947     { "(bad)",          { XX } },
7948     { "(bad)",          { XX } },
7949     { "(bad)",          { XX } },
7950     /* 58 */
7951     { "(bad)",          { XX } },
7952     { "(bad)",          { XX } },
7953     { "(bad)",          { XX } },
7954     { "(bad)",          { XX } },
7955     { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7956     { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7957     { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7958     { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7959     /* 60 */
7960     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7961     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7962     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7963     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7964     { "(bad)",          { XX } },
7965     { "(bad)",          { XX } },
7966     { "(bad)",          { XX } },
7967     { "(bad)",          { XX } },
7968     /* 68 */
7969     { PREFIX_TABLE (PREFIX_VEX_3A68) },
7970     { PREFIX_TABLE (PREFIX_VEX_3A69) },
7971     { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7972     { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7973     { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7974     { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7975     { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7976     { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7977     /* 70 */
7978     { "(bad)",          { XX } },
7979     { "(bad)",          { XX } },
7980     { "(bad)",          { XX } },
7981     { "(bad)",          { XX } },
7982     { "(bad)",          { XX } },
7983     { "(bad)",          { XX } },
7984     { "(bad)",          { XX } },
7985     { "(bad)",          { XX } },
7986     /* 78 */
7987     { PREFIX_TABLE (PREFIX_VEX_3A78) },
7988     { PREFIX_TABLE (PREFIX_VEX_3A79) },
7989     { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7990     { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7991     { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7992     { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7993     { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7994     { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7995     /* 80 */
7996     { "(bad)",          { XX } },
7997     { "(bad)",          { XX } },
7998     { "(bad)",          { XX } },
7999     { "(bad)",          { XX } },
8000     { "(bad)",          { XX } },
8001     { "(bad)",          { XX } },
8002     { "(bad)",          { XX } },
8003     { "(bad)",          { XX } },
8004     /* 88 */
8005     { "(bad)",          { XX } },
8006     { "(bad)",          { XX } },
8007     { "(bad)",          { XX } },
8008     { "(bad)",          { XX } },
8009     { "(bad)",          { XX } },
8010     { "(bad)",          { XX } },
8011     { "(bad)",          { XX } },
8012     { "(bad)",          { XX } },
8013     /* 90 */
8014     { "(bad)",          { XX } },
8015     { "(bad)",          { XX } },
8016     { "(bad)",          { XX } },
8017     { "(bad)",          { XX } },
8018     { "(bad)",          { XX } },
8019     { "(bad)",          { XX } },
8020     { "(bad)",          { XX } },
8021     { "(bad)",          { XX } },
8022     /* 98 */
8023     { "(bad)",          { XX } },
8024     { "(bad)",          { XX } },
8025     { "(bad)",          { XX } },
8026     { "(bad)",          { XX } },
8027     { "(bad)",          { XX } },
8028     { "(bad)",          { XX } },
8029     { "(bad)",          { XX } },
8030     { "(bad)",          { XX } },
8031     /* a0 */
8032     { "(bad)",          { XX } },
8033     { "(bad)",          { XX } },
8034     { "(bad)",          { XX } },
8035     { "(bad)",          { XX } },
8036     { "(bad)",          { XX } },
8037     { "(bad)",          { XX } },
8038     { "(bad)",          { XX } },
8039     { "(bad)",          { XX } },
8040     /* a8 */
8041     { "(bad)",          { XX } },
8042     { "(bad)",          { XX } },
8043     { "(bad)",          { XX } },
8044     { "(bad)",          { XX } },
8045     { "(bad)",          { XX } },
8046     { "(bad)",          { XX } },
8047     { "(bad)",          { XX } },
8048     { "(bad)",          { XX } },
8049     /* b0 */
8050     { "(bad)",          { XX } },
8051     { "(bad)",          { XX } },
8052     { "(bad)",          { XX } },
8053     { "(bad)",          { XX } },
8054     { "(bad)",          { XX } },
8055     { "(bad)",          { XX } },
8056     { "(bad)",          { XX } },
8057     { "(bad)",          { XX } },
8058     /* b8 */
8059     { "(bad)",          { XX } },
8060     { "(bad)",          { XX } },
8061     { "(bad)",          { XX } },
8062     { "(bad)",          { XX } },
8063     { "(bad)",          { XX } },
8064     { "(bad)",          { XX } },
8065     { "(bad)",          { XX } },
8066     { "(bad)",          { XX } },
8067     /* c0 */
8068     { "(bad)",          { XX } },
8069     { "(bad)",          { XX } },
8070     { "(bad)",          { XX } },
8071     { "(bad)",          { XX } },
8072     { "(bad)",          { XX } },
8073     { "(bad)",          { XX } },
8074     { "(bad)",          { XX } },
8075     { "(bad)",          { XX } },
8076     /* c8 */
8077     { "(bad)",          { XX } },
8078     { "(bad)",          { XX } },
8079     { "(bad)",          { XX } },
8080     { "(bad)",          { XX } },
8081     { "(bad)",          { XX } },
8082     { "(bad)",          { XX } },
8083     { "(bad)",          { XX } },
8084     { "(bad)",          { XX } },
8085     /* d0 */
8086     { "(bad)",          { XX } },
8087     { "(bad)",          { XX } },
8088     { "(bad)",          { XX } },
8089     { "(bad)",          { XX } },
8090     { "(bad)",          { XX } },
8091     { "(bad)",          { XX } },
8092     { "(bad)",          { XX } },
8093     { "(bad)",          { XX } },
8094     /* d8 */
8095     { "(bad)",          { XX } },
8096     { "(bad)",          { XX } },
8097     { "(bad)",          { XX } },
8098     { "(bad)",          { XX } },
8099     { "(bad)",          { XX } },
8100     { "(bad)",          { XX } },
8101     { "(bad)",          { XX } },
8102     { PREFIX_TABLE (PREFIX_VEX_3ADF) },
8103     /* e0 */
8104     { "(bad)",          { XX } },
8105     { "(bad)",          { XX } },
8106     { "(bad)",          { XX } },
8107     { "(bad)",          { XX } },
8108     { "(bad)",          { XX } },
8109     { "(bad)",          { XX } },
8110     { "(bad)",          { XX } },
8111     { "(bad)",          { XX } },
8112     /* e8 */
8113     { "(bad)",          { XX } },
8114     { "(bad)",          { XX } },
8115     { "(bad)",          { XX } },
8116     { "(bad)",          { XX } },
8117     { "(bad)",          { XX } },
8118     { "(bad)",          { XX } },
8119     { "(bad)",          { XX } },
8120     { "(bad)",          { XX } },
8121     /* f0 */
8122     { "(bad)",          { XX } },
8123     { "(bad)",          { XX } },
8124     { "(bad)",          { XX } },
8125     { "(bad)",          { XX } },
8126     { "(bad)",          { XX } },
8127     { "(bad)",          { XX } },
8128     { "(bad)",          { XX } },
8129     { "(bad)",          { XX } },
8130     /* f8 */
8131     { "(bad)",          { XX } },
8132     { "(bad)",          { XX } },
8133     { "(bad)",          { XX } },
8134     { "(bad)",          { XX } },
8135     { "(bad)",          { XX } },
8136     { "(bad)",          { XX } },
8137     { "(bad)",          { XX } },
8138     { "(bad)",          { XX } },
8139   },
8140 };
8141
8142 static const struct dis386 vex_len_table[][2] = {
8143   /* VEX_LEN_10_P_1 */
8144   {
8145     { "vmovss",         { XMVex, Vex128, EXd } },
8146     { "(bad)",          { XX } },
8147   },
8148
8149   /* VEX_LEN_10_P_3 */
8150   {
8151     { "vmovsd",         { XMVex, Vex128, EXq } },
8152     { "(bad)",          { XX } },
8153   },
8154
8155   /* VEX_LEN_11_P_1 */
8156   {
8157     { "vmovss",         { EXdVexS, Vex128, XM } },
8158     { "(bad)",          { XX } },
8159   },
8160
8161   /* VEX_LEN_11_P_3 */
8162   {
8163     { "vmovsd",         { EXqVexS, Vex128, XM } },
8164     { "(bad)",          { XX } },
8165   },
8166
8167   /* VEX_LEN_12_P_0_M_0 */
8168   {
8169     { "vmovlps",        { XM, Vex128, EXq } },
8170     { "(bad)",          { XX } },
8171   },
8172
8173   /* VEX_LEN_12_P_0_M_1 */
8174   {
8175     { "vmovhlps",       { XM, Vex128, EXq } },
8176     { "(bad)",          { XX } },
8177   },
8178
8179   /* VEX_LEN_12_P_2 */
8180   {
8181     { "vmovlpd",        { XM, Vex128, EXq } },
8182     { "(bad)",          { XX } },
8183   },
8184
8185   /* VEX_LEN_13_M_0 */
8186   {
8187     { "vmovlpX",        { EXq, XM } },
8188     { "(bad)",          { XX } },
8189   },
8190
8191   /* VEX_LEN_16_P_0_M_0 */
8192   {
8193     { "vmovhps",        { XM, Vex128, EXq } },
8194     { "(bad)",          { XX } },
8195   },
8196
8197   /* VEX_LEN_16_P_0_M_1 */
8198   {
8199     { "vmovlhps",       { XM, Vex128, EXq } },
8200     { "(bad)",          { XX } },
8201   },
8202
8203   /* VEX_LEN_16_P_2 */
8204   {
8205     { "vmovhpd",        { XM, Vex128, EXq } },
8206     { "(bad)",          { XX } },
8207   },
8208
8209   /* VEX_LEN_17_M_0 */
8210   {
8211     { "vmovhpX",        { EXq, XM } },
8212     { "(bad)",          { XX } },
8213   },
8214
8215   /* VEX_LEN_2A_P_1 */
8216   {
8217     { "vcvtsi2ss%LQ",   { XM, Vex128, Ev } },
8218     { "(bad)",          { XX } },
8219   },
8220
8221   /* VEX_LEN_2A_P_3 */
8222   {
8223     { "vcvtsi2sd%LQ",   { XM, Vex128, Ev } },
8224     { "(bad)",          { XX } },
8225   },
8226
8227   /* VEX_LEN_2C_P_1 */
8228   {
8229     { "vcvttss2siY",    { Gv, EXd } },
8230     { "(bad)",          { XX } },
8231   },
8232
8233   /* VEX_LEN_2C_P_3 */
8234   {
8235     { "vcvttsd2siY",    { Gv, EXq } },
8236     { "(bad)",          { XX } },
8237   },
8238
8239   /* VEX_LEN_2D_P_1 */
8240   {
8241     { "vcvtss2siY",     { Gv, EXd } },
8242     { "(bad)",          { XX } },
8243   },
8244
8245   /* VEX_LEN_2D_P_3 */
8246   {
8247     { "vcvtsd2siY",     { Gv, EXq } },
8248     { "(bad)",          { XX } },
8249   },
8250
8251   /* VEX_LEN_2E_P_0 */
8252   {
8253     { "vucomiss",       { XM, EXd } },
8254     { "(bad)",          { XX } },
8255   },
8256
8257   /* VEX_LEN_2E_P_2 */
8258   {
8259     { "vucomisd",       { XM, EXq } },
8260     { "(bad)",          { XX } },
8261   },
8262
8263   /* VEX_LEN_2F_P_0 */
8264   {
8265     { "vcomiss",        { XM, EXd } },
8266     { "(bad)",          { XX } },
8267   },
8268
8269   /* VEX_LEN_2F_P_2 */
8270   {
8271     { "vcomisd",        { XM, EXq } },
8272     { "(bad)",          { XX } },
8273   },
8274
8275   /* VEX_LEN_51_P_1 */
8276   {
8277     { "vsqrtss",        { XM, Vex128, EXd } },
8278     { "(bad)",          { XX } },
8279   },
8280
8281   /* VEX_LEN_51_P_3 */
8282   {
8283     { "vsqrtsd",        { XM, Vex128, EXq } },
8284     { "(bad)",          { XX } },
8285   },
8286
8287   /* VEX_LEN_52_P_1 */
8288   {
8289     { "vrsqrtss",       { XM, Vex128, EXd } },
8290     { "(bad)",          { XX } },
8291   },
8292
8293   /* VEX_LEN_53_P_1 */
8294   {
8295     { "vrcpss",         { XM, Vex128, EXd } },
8296     { "(bad)",          { XX } },
8297   },
8298
8299   /* VEX_LEN_58_P_1 */
8300   {
8301     { "vaddss",         { XM, Vex128, EXd } },
8302     { "(bad)",          { XX } },
8303   },
8304
8305   /* VEX_LEN_58_P_3 */
8306   {
8307     { "vaddsd",         { XM, Vex128, EXq } },
8308     { "(bad)",          { XX } },
8309   },
8310
8311   /* VEX_LEN_59_P_1 */
8312   {
8313     { "vmulss",         { XM, Vex128, EXd } },
8314     { "(bad)",          { XX } },
8315   },
8316
8317   /* VEX_LEN_59_P_3 */
8318   {
8319     { "vmulsd",         { XM, Vex128, EXq } },
8320     { "(bad)",          { XX } },
8321   },
8322
8323   /* VEX_LEN_5A_P_1 */
8324   {
8325     { "vcvtss2sd",      { XM, Vex128, EXd } },
8326     { "(bad)",          { XX } },
8327   },
8328
8329   /* VEX_LEN_5A_P_3 */
8330   {
8331     { "vcvtsd2ss",      { XM, Vex128, EXq } },
8332     { "(bad)",          { XX } },
8333   },
8334
8335   /* VEX_LEN_5C_P_1 */
8336   {
8337     { "vsubss",         { XM, Vex128, EXd } },
8338     { "(bad)",          { XX } },
8339   },
8340
8341   /* VEX_LEN_5C_P_3 */
8342   {
8343     { "vsubsd",         { XM, Vex128, EXq } },
8344     { "(bad)",          { XX } },
8345   },
8346
8347   /* VEX_LEN_5D_P_1 */
8348   {
8349     { "vminss",         { XM, Vex128, EXd } },
8350     { "(bad)",          { XX } },
8351   },
8352
8353   /* VEX_LEN_5D_P_3 */
8354   {
8355     { "vminsd",         { XM, Vex128, EXq } },
8356     { "(bad)",          { XX } },
8357   },
8358
8359   /* VEX_LEN_5E_P_1 */
8360   {
8361     { "vdivss",         { XM, Vex128, EXd } },
8362     { "(bad)",          { XX } },
8363   },
8364
8365   /* VEX_LEN_5E_P_3 */
8366   {
8367     { "vdivsd",         { XM, Vex128, EXq } },
8368     { "(bad)",          { XX } },
8369   },
8370
8371   /* VEX_LEN_5F_P_1 */
8372   {
8373     { "vmaxss",         { XM, Vex128, EXd } },
8374     { "(bad)",          { XX } },
8375   },
8376
8377   /* VEX_LEN_5F_P_3 */
8378   {
8379     { "vmaxsd",         { XM, Vex128, EXq } },
8380     { "(bad)",          { XX } },
8381   },
8382
8383   /* VEX_LEN_60_P_2 */
8384   {
8385     { "vpunpcklbw",     { XM, Vex128, EXx } },
8386     { "(bad)",          { XX } },
8387   },
8388
8389   /* VEX_LEN_61_P_2 */
8390   {
8391     { "vpunpcklwd",     { XM, Vex128, EXx } },
8392     { "(bad)",          { XX } },
8393   },
8394
8395   /* VEX_LEN_62_P_2 */
8396   {
8397     { "vpunpckldq",     { XM, Vex128, EXx } },
8398     { "(bad)",          { XX } },
8399   },
8400
8401   /* VEX_LEN_63_P_2 */
8402   {
8403     { "vpacksswb",      { XM, Vex128, EXx } },
8404     { "(bad)",          { XX } },
8405   },
8406
8407   /* VEX_LEN_64_P_2 */
8408   {
8409     { "vpcmpgtb",       { XM, Vex128, EXx } },
8410     { "(bad)",          { XX } },
8411   },
8412
8413   /* VEX_LEN_65_P_2 */
8414   {
8415     { "vpcmpgtw",       { XM, Vex128, EXx } },
8416     { "(bad)",          { XX } },
8417   },
8418
8419   /* VEX_LEN_66_P_2 */
8420   {
8421     { "vpcmpgtd",       { XM, Vex128, EXx } },
8422     { "(bad)",          { XX } },
8423   },
8424
8425   /* VEX_LEN_67_P_2 */
8426   {
8427     { "vpackuswb",      { XM, Vex128, EXx } },
8428     { "(bad)",          { XX } },
8429   },
8430
8431   /* VEX_LEN_68_P_2 */
8432   {
8433     { "vpunpckhbw",     { XM, Vex128, EXx } },
8434     { "(bad)",          { XX } },
8435   },
8436
8437   /* VEX_LEN_69_P_2 */
8438   {
8439     { "vpunpckhwd",     { XM, Vex128, EXx } },
8440     { "(bad)",          { XX } },
8441   },
8442
8443   /* VEX_LEN_6A_P_2 */
8444   {
8445     { "vpunpckhdq",     { XM, Vex128, EXx } },
8446     { "(bad)",          { XX } },
8447   },
8448
8449   /* VEX_LEN_6B_P_2 */
8450   {
8451     { "vpackssdw",      { XM, Vex128, EXx } },
8452     { "(bad)",          { XX } },
8453   },
8454
8455   /* VEX_LEN_6C_P_2 */
8456   {
8457     { "vpunpcklqdq",    { XM, Vex128, EXx } },
8458     { "(bad)",          { XX } },
8459   },
8460
8461   /* VEX_LEN_6D_P_2 */
8462   {
8463     { "vpunpckhqdq",    { XM, Vex128, EXx } },
8464     { "(bad)",          { XX } },
8465   },
8466
8467   /* VEX_LEN_6E_P_2 */
8468   {
8469     { "vmovK",          { XM, Edq } },
8470     { "(bad)",          { XX } },
8471   },
8472
8473   /* VEX_LEN_70_P_1 */
8474   {
8475     { "vpshufhw",       { XM, EXx, Ib } },
8476     { "(bad)",          { XX } },
8477   },
8478
8479   /* VEX_LEN_70_P_2 */
8480   {
8481     { "vpshufd",        { XM, EXx, Ib } },
8482     { "(bad)",          { XX } },
8483   },
8484
8485   /* VEX_LEN_70_P_3 */
8486   {
8487     { "vpshuflw",       { XM, EXx, Ib } },
8488     { "(bad)",          { XX } },
8489   },
8490
8491   /* VEX_LEN_71_R_2_P_2 */
8492   {
8493     { "vpsrlw",         { Vex128, XS, Ib } },
8494     { "(bad)",          { XX } },
8495   },
8496
8497   /* VEX_LEN_71_R_4_P_2 */
8498   {
8499     { "vpsraw",         { Vex128, XS, Ib } },
8500     { "(bad)",          { XX } },
8501   },
8502
8503   /* VEX_LEN_71_R_6_P_2 */
8504   {
8505     { "vpsllw",         { Vex128, XS, Ib } },
8506     { "(bad)",          { XX } },
8507   },
8508
8509   /* VEX_LEN_72_R_2_P_2 */
8510   {
8511     { "vpsrld",         { Vex128, XS, Ib } },
8512     { "(bad)",          { XX } },
8513   },
8514
8515   /* VEX_LEN_72_R_4_P_2 */
8516   {
8517     { "vpsrad",         { Vex128, XS, Ib } },
8518     { "(bad)",          { XX } },
8519   },
8520
8521   /* VEX_LEN_72_R_6_P_2 */
8522   {
8523     { "vpslld",         { Vex128, XS, Ib } },
8524     { "(bad)",          { XX } },
8525   },
8526
8527   /* VEX_LEN_73_R_2_P_2 */
8528   {
8529     { "vpsrlq",         { Vex128, XS, Ib } },
8530     { "(bad)",          { XX } },
8531   },
8532
8533   /* VEX_LEN_73_R_3_P_2 */
8534   {
8535     { "vpsrldq",        { Vex128, XS, Ib } },
8536     { "(bad)",          { XX } },
8537   },
8538
8539   /* VEX_LEN_73_R_6_P_2 */
8540   {
8541     { "vpsllq",         { Vex128, XS, Ib } },
8542     { "(bad)",          { XX } },
8543   },
8544
8545   /* VEX_LEN_73_R_7_P_2 */
8546   {
8547     { "vpslldq",        { Vex128, XS, Ib } },
8548     { "(bad)",          { XX } },
8549   },
8550
8551   /* VEX_LEN_74_P_2 */
8552   {
8553     { "vpcmpeqb",       { XM, Vex128, EXx } },
8554     { "(bad)",          { XX } },
8555   },
8556
8557   /* VEX_LEN_75_P_2 */
8558   {
8559     { "vpcmpeqw",       { XM, Vex128, EXx } },
8560     { "(bad)",          { XX } },
8561   },
8562
8563   /* VEX_LEN_76_P_2 */
8564   {
8565     { "vpcmpeqd",       { XM, Vex128, EXx } },
8566     { "(bad)",          { XX } },
8567   },
8568
8569   /* VEX_LEN_7E_P_1 */
8570   {
8571     { "vmovq",          { XM, EXq } },
8572     { "(bad)",          { XX } },
8573   },
8574
8575   /* VEX_LEN_7E_P_2 */
8576   {
8577     { "vmovK",          { Edq, XM } },
8578     { "(bad)",          { XX } },
8579   },
8580
8581   /* VEX_LEN_AE_R_2_M_0 */
8582   {
8583     { "vldmxcsr",       { Md } },
8584     { "(bad)",          { XX } },
8585   },
8586
8587   /* VEX_LEN_AE_R_3_M_0 */
8588   {
8589     { "vstmxcsr",       { Md } },
8590     { "(bad)",          { XX } },
8591   },
8592
8593   /* VEX_LEN_C2_P_1 */
8594   {
8595     { "vcmpss",         { XM, Vex128, EXd, VCMP } },
8596     { "(bad)",          { XX } },
8597   },
8598
8599   /* VEX_LEN_C2_P_3 */
8600   {
8601     { "vcmpsd",         { XM, Vex128, EXq, VCMP } },
8602     { "(bad)",          { XX } },
8603   },
8604
8605   /* VEX_LEN_C4_P_2 */
8606   {
8607     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
8608     { "(bad)",          { XX } },
8609   },
8610
8611   /* VEX_LEN_C5_P_2 */
8612   {
8613     { "vpextrw",        { Gdq, XS, Ib } },
8614     { "(bad)",          { XX } },
8615   },
8616
8617   /* VEX_LEN_D1_P_2 */
8618   {
8619     { "vpsrlw",         { XM, Vex128, EXx } },
8620     { "(bad)",          { XX } },
8621   },
8622
8623   /* VEX_LEN_D2_P_2 */
8624   {
8625     { "vpsrld",         { XM, Vex128, EXx } },
8626     { "(bad)",          { XX } },
8627   },
8628
8629   /* VEX_LEN_D3_P_2 */
8630   {
8631     { "vpsrlq",         { XM, Vex128, EXx } },
8632     { "(bad)",          { XX } },
8633   },
8634
8635   /* VEX_LEN_D4_P_2 */
8636   {
8637     { "vpaddq",         { XM, Vex128, EXx } },
8638     { "(bad)",          { XX } },
8639   },
8640
8641   /* VEX_LEN_D5_P_2 */
8642   {
8643     { "vpmullw",        { XM, Vex128, EXx } },
8644     { "(bad)",          { XX } },
8645   },
8646
8647   /* VEX_LEN_D6_P_2 */
8648   {
8649     { "vmovq",          { EXqS, XM } },
8650     { "(bad)",          { XX } },
8651   },
8652
8653   /* VEX_LEN_D7_P_2_M_1 */
8654   {
8655     { "vpmovmskb",      { Gdq, XS } },
8656     { "(bad)",          { XX } },
8657   },
8658
8659   /* VEX_LEN_D8_P_2 */
8660   {
8661     { "vpsubusb",       { XM, Vex128, EXx } },
8662     { "(bad)",          { XX } },
8663   },
8664
8665   /* VEX_LEN_D9_P_2 */
8666   {
8667     { "vpsubusw",       { XM, Vex128, EXx } },
8668     { "(bad)",          { XX } },
8669   },
8670
8671   /* VEX_LEN_DA_P_2 */
8672   {
8673     { "vpminub",        { XM, Vex128, EXx } },
8674     { "(bad)",          { XX } },
8675   },
8676
8677   /* VEX_LEN_DB_P_2 */
8678   {
8679     { "vpand",          { XM, Vex128, EXx } },
8680     { "(bad)",          { XX } },
8681   },
8682
8683   /* VEX_LEN_DC_P_2 */
8684   {
8685     { "vpaddusb",       { XM, Vex128, EXx } },
8686     { "(bad)",          { XX } },
8687   },
8688
8689   /* VEX_LEN_DD_P_2 */
8690   {
8691     { "vpaddusw",       { XM, Vex128, EXx } },
8692     { "(bad)",          { XX } },
8693   },
8694
8695   /* VEX_LEN_DE_P_2 */
8696   {
8697     { "vpmaxub",        { XM, Vex128, EXx } },
8698     { "(bad)",          { XX } },
8699   },
8700
8701   /* VEX_LEN_DF_P_2 */
8702   {
8703     { "vpandn",         { XM, Vex128, EXx } },
8704     { "(bad)",          { XX } },
8705   },
8706
8707   /* VEX_LEN_E0_P_2 */
8708   {
8709     { "vpavgb",         { XM, Vex128, EXx } },
8710     { "(bad)",          { XX } },
8711   },
8712
8713   /* VEX_LEN_E1_P_2 */
8714   {
8715     { "vpsraw",         { XM, Vex128, EXx } },
8716     { "(bad)",          { XX } },
8717   },
8718
8719   /* VEX_LEN_E2_P_2 */
8720   {
8721     { "vpsrad",         { XM, Vex128, EXx } },
8722     { "(bad)",          { XX } },
8723   },
8724
8725   /* VEX_LEN_E3_P_2 */
8726   {
8727     { "vpavgw",         { XM, Vex128, EXx } },
8728     { "(bad)",          { XX } },
8729   },
8730
8731   /* VEX_LEN_E4_P_2 */
8732   {
8733     { "vpmulhuw",       { XM, Vex128, EXx } },
8734     { "(bad)",          { XX } },
8735   },
8736
8737   /* VEX_LEN_E5_P_2 */
8738   {
8739     { "vpmulhw",        { XM, Vex128, EXx } },
8740     { "(bad)",          { XX } },
8741   },
8742
8743   /* VEX_LEN_E8_P_2 */
8744   {
8745     { "vpsubsb",        { XM, Vex128, EXx } },
8746     { "(bad)",          { XX } },
8747   },
8748
8749   /* VEX_LEN_E9_P_2 */
8750   {
8751     { "vpsubsw",        { XM, Vex128, EXx } },
8752     { "(bad)",          { XX } },
8753   },
8754
8755   /* VEX_LEN_EA_P_2 */
8756   {
8757     { "vpminsw",        { XM, Vex128, EXx } },
8758     { "(bad)",          { XX } },
8759   },
8760
8761   /* VEX_LEN_EB_P_2 */
8762   {
8763     { "vpor",           { XM, Vex128, EXx } },
8764     { "(bad)",          { XX } },
8765   },
8766
8767   /* VEX_LEN_EC_P_2 */
8768   {
8769     { "vpaddsb",        { XM, Vex128, EXx } },
8770     { "(bad)",          { XX } },
8771   },
8772
8773   /* VEX_LEN_ED_P_2 */
8774   {
8775     { "vpaddsw",        { XM, Vex128, EXx } },
8776     { "(bad)",          { XX } },
8777   },
8778
8779   /* VEX_LEN_EE_P_2 */
8780   {
8781     { "vpmaxsw",        { XM, Vex128, EXx } },
8782     { "(bad)",          { XX } },
8783   },
8784
8785   /* VEX_LEN_EF_P_2 */
8786   {
8787     { "vpxor",          { XM, Vex128, EXx } },
8788     { "(bad)",          { XX } },
8789   },
8790
8791   /* VEX_LEN_F1_P_2 */
8792   {
8793     { "vpsllw",         { XM, Vex128, EXx } },
8794     { "(bad)",          { XX } },
8795   },
8796
8797   /* VEX_LEN_F2_P_2 */
8798   {
8799     { "vpslld",         { XM, Vex128, EXx } },
8800     { "(bad)",          { XX } },
8801   },
8802
8803   /* VEX_LEN_F3_P_2 */
8804   {
8805     { "vpsllq",         { XM, Vex128, EXx } },
8806     { "(bad)",          { XX } },
8807   },
8808
8809   /* VEX_LEN_F4_P_2 */
8810   {
8811     { "vpmuludq",       { XM, Vex128, EXx } },
8812     { "(bad)",          { XX } },
8813   },
8814
8815   /* VEX_LEN_F5_P_2 */
8816   {
8817     { "vpmaddwd",       { XM, Vex128, EXx } },
8818     { "(bad)",          { XX } },
8819   },
8820
8821   /* VEX_LEN_F6_P_2 */
8822   {
8823     { "vpsadbw",        { XM, Vex128, EXx } },
8824     { "(bad)",          { XX } },
8825   },
8826
8827   /* VEX_LEN_F7_P_2 */
8828   {
8829     { "vmaskmovdqu",    { XM, XS } },
8830     { "(bad)",          { XX } },
8831   },
8832
8833   /* VEX_LEN_F8_P_2 */
8834   {
8835     { "vpsubb",         { XM, Vex128, EXx } },
8836     { "(bad)",          { XX } },
8837   },
8838
8839   /* VEX_LEN_F9_P_2 */
8840   {
8841     { "vpsubw",         { XM, Vex128, EXx } },
8842     { "(bad)",          { XX } },
8843   },
8844
8845   /* VEX_LEN_FA_P_2 */
8846   {
8847     { "vpsubd",         { XM, Vex128, EXx } },
8848     { "(bad)",          { XX } },
8849   },
8850
8851   /* VEX_LEN_FB_P_2 */
8852   {
8853     { "vpsubq",         { XM, Vex128, EXx } },
8854     { "(bad)",          { XX } },
8855   },
8856
8857   /* VEX_LEN_FC_P_2 */
8858   {
8859     { "vpaddb",         { XM, Vex128, EXx } },
8860     { "(bad)",          { XX } },
8861   },
8862
8863   /* VEX_LEN_FD_P_2 */
8864   {
8865     { "vpaddw",         { XM, Vex128, EXx } },
8866     { "(bad)",          { XX } },
8867   },
8868
8869   /* VEX_LEN_FE_P_2 */
8870   {
8871     { "vpaddd",         { XM, Vex128, EXx } },
8872     { "(bad)",          { XX } },
8873   },
8874
8875   /* VEX_LEN_3800_P_2 */
8876   {
8877     { "vpshufb",        { XM, Vex128, EXx } },
8878     { "(bad)",          { XX } },
8879   },
8880
8881   /* VEX_LEN_3801_P_2 */
8882   {
8883     { "vphaddw",        { XM, Vex128, EXx } },
8884     { "(bad)",          { XX } },
8885   },
8886
8887   /* VEX_LEN_3802_P_2 */
8888   {
8889     { "vphaddd",        { XM, Vex128, EXx } },
8890     { "(bad)",          { XX } },
8891   },
8892
8893   /* VEX_LEN_3803_P_2 */
8894   {
8895     { "vphaddsw",       { XM, Vex128, EXx } },
8896     { "(bad)",          { XX } },
8897   },
8898
8899   /* VEX_LEN_3804_P_2 */
8900   {
8901     { "vpmaddubsw",     { XM, Vex128, EXx } },
8902     { "(bad)",          { XX } },
8903   },
8904
8905   /* VEX_LEN_3805_P_2 */
8906   {
8907     { "vphsubw",        { XM, Vex128, EXx } },
8908     { "(bad)",          { XX } },
8909   },
8910
8911   /* VEX_LEN_3806_P_2 */
8912   {
8913     { "vphsubd",        { XM, Vex128, EXx } },
8914     { "(bad)",          { XX } },
8915   },
8916
8917   /* VEX_LEN_3807_P_2 */
8918   {
8919     { "vphsubsw",       { XM, Vex128, EXx } },
8920     { "(bad)",          { XX } },
8921   },
8922
8923   /* VEX_LEN_3808_P_2 */
8924   {
8925     { "vpsignb",        { XM, Vex128, EXx } },
8926     { "(bad)",          { XX } },
8927   },
8928
8929   /* VEX_LEN_3809_P_2 */
8930   {
8931     { "vpsignw",        { XM, Vex128, EXx } },
8932     { "(bad)",          { XX } },
8933   },
8934
8935   /* VEX_LEN_380A_P_2 */
8936   {
8937     { "vpsignd",        { XM, Vex128, EXx } },
8938     { "(bad)",          { XX } },
8939   },
8940
8941   /* VEX_LEN_380B_P_2 */
8942   {
8943     { "vpmulhrsw",      { XM, Vex128, EXx } },
8944     { "(bad)",          { XX } },
8945   },
8946
8947   /* VEX_LEN_3819_P_2_M_0 */
8948   {
8949     { "(bad)",          { XX } },
8950     { "vbroadcastsd",   { XM, Mq } },
8951   },
8952
8953   /* VEX_LEN_381A_P_2_M_0 */
8954   {
8955     { "(bad)",          { XX } },
8956     { "vbroadcastf128", { XM, Mxmm } },
8957   },
8958
8959   /* VEX_LEN_381C_P_2 */
8960   {
8961     { "vpabsb",         { XM, EXx } },
8962     { "(bad)",          { XX } },
8963   },
8964
8965   /* VEX_LEN_381D_P_2 */
8966   {
8967     { "vpabsw",         { XM, EXx } },
8968     { "(bad)",          { XX } },
8969   },
8970
8971   /* VEX_LEN_381E_P_2 */
8972   {
8973     { "vpabsd",         { XM, EXx } },
8974     { "(bad)",          { XX } },
8975   },
8976
8977   /* VEX_LEN_3820_P_2 */
8978   {
8979     { "vpmovsxbw",      { XM, EXq } },
8980     { "(bad)",          { XX } },
8981   },
8982
8983   /* VEX_LEN_3821_P_2 */
8984   {
8985     { "vpmovsxbd",      { XM, EXd } },
8986     { "(bad)",          { XX } },
8987   },
8988
8989   /* VEX_LEN_3822_P_2 */
8990   {
8991     { "vpmovsxbq",      { XM, EXw } },
8992     { "(bad)",          { XX } },
8993   },
8994
8995   /* VEX_LEN_3823_P_2 */
8996   {
8997     { "vpmovsxwd",      { XM, EXq } },
8998     { "(bad)",          { XX } },
8999   },
9000
9001   /* VEX_LEN_3824_P_2 */
9002   {
9003     { "vpmovsxwq",      { XM, EXd } },
9004     { "(bad)",          { XX } },
9005   },
9006
9007   /* VEX_LEN_3825_P_2 */
9008   {
9009     { "vpmovsxdq",      { XM, EXq } },
9010     { "(bad)",          { XX } },
9011   },
9012
9013   /* VEX_LEN_3828_P_2 */
9014   {
9015     { "vpmuldq",        { XM, Vex128, EXx } },
9016     { "(bad)",          { XX } },
9017   },
9018
9019   /* VEX_LEN_3829_P_2 */
9020   {
9021     { "vpcmpeqq",       { XM, Vex128, EXx } },
9022     { "(bad)",          { XX } },
9023   },
9024
9025   /* VEX_LEN_382A_P_2_M_0 */
9026   {
9027     { "vmovntdqa",      { XM, Mx } },
9028     { "(bad)",          { XX } },
9029   },
9030
9031   /* VEX_LEN_382B_P_2 */
9032   {
9033     { "vpackusdw",      { XM, Vex128, EXx } },
9034     { "(bad)",          { XX } },
9035   },
9036
9037   /* VEX_LEN_3830_P_2 */
9038   {
9039     { "vpmovzxbw",      { XM, EXq } },
9040     { "(bad)",          { XX } },
9041   },
9042
9043   /* VEX_LEN_3831_P_2 */
9044   {
9045     { "vpmovzxbd",      { XM, EXd } },
9046     { "(bad)",          { XX } },
9047   },
9048
9049   /* VEX_LEN_3832_P_2 */
9050   {
9051     { "vpmovzxbq",      { XM, EXw } },
9052     { "(bad)",          { XX } },
9053   },
9054
9055   /* VEX_LEN_3833_P_2 */
9056   {
9057     { "vpmovzxwd",      { XM, EXq } },
9058     { "(bad)",          { XX } },
9059   },
9060
9061   /* VEX_LEN_3834_P_2 */
9062   {
9063     { "vpmovzxwq",      { XM, EXd } },
9064     { "(bad)",          { XX } },
9065   },
9066
9067   /* VEX_LEN_3835_P_2 */
9068   {
9069     { "vpmovzxdq",      { XM, EXq } },
9070     { "(bad)",          { XX } },
9071   },
9072
9073   /* VEX_LEN_3837_P_2 */
9074   {
9075     { "vpcmpgtq",       { XM, Vex128, EXx } },
9076     { "(bad)",          { XX } },
9077   },
9078
9079   /* VEX_LEN_3838_P_2 */
9080   {
9081     { "vpminsb",        { XM, Vex128, EXx } },
9082     { "(bad)",          { XX } },
9083   },
9084
9085   /* VEX_LEN_3839_P_2 */
9086   {
9087     { "vpminsd",        { XM, Vex128, EXx } },
9088     { "(bad)",          { XX } },
9089   },
9090
9091   /* VEX_LEN_383A_P_2 */
9092   {
9093     { "vpminuw",        { XM, Vex128, EXx } },
9094     { "(bad)",          { XX } },
9095   },
9096
9097   /* VEX_LEN_383B_P_2 */
9098   {
9099     { "vpminud",        { XM, Vex128, EXx } },
9100     { "(bad)",          { XX } },
9101   },
9102
9103   /* VEX_LEN_383C_P_2 */
9104   {
9105     { "vpmaxsb",        { XM, Vex128, EXx } },
9106     { "(bad)",          { XX } },
9107   },
9108
9109   /* VEX_LEN_383D_P_2 */
9110   {
9111     { "vpmaxsd",        { XM, Vex128, EXx } },
9112     { "(bad)",          { XX } },
9113   },
9114
9115   /* VEX_LEN_383E_P_2 */
9116   {
9117     { "vpmaxuw",        { XM, Vex128, EXx } },
9118     { "(bad)",          { XX } },
9119   },
9120
9121   /* VEX_LEN_383F_P_2 */
9122   {
9123     { "vpmaxud",        { XM, Vex128, EXx } },
9124     { "(bad)",          { XX } },
9125   },
9126
9127   /* VEX_LEN_3840_P_2 */
9128   {
9129     { "vpmulld",        { XM, Vex128, EXx } },
9130     { "(bad)",          { XX } },
9131   },
9132
9133   /* VEX_LEN_3841_P_2 */
9134   {
9135     { "vphminposuw",    { XM, EXx } },
9136     { "(bad)",          { XX } },
9137   },
9138
9139   /* VEX_LEN_38DB_P_2 */
9140   {
9141     { "vaesimc",        { XM, EXx } },
9142     { "(bad)",          { XX } },
9143   },
9144
9145   /* VEX_LEN_38DC_P_2 */
9146   {
9147     { "vaesenc",        { XM, Vex128, EXx } },
9148     { "(bad)",          { XX } },
9149   },
9150
9151   /* VEX_LEN_38DD_P_2 */
9152   {
9153     { "vaesenclast",    { XM, Vex128, EXx } },
9154     { "(bad)",          { XX } },
9155   },
9156
9157   /* VEX_LEN_38DE_P_2 */
9158   {
9159     { "vaesdec",        { XM, Vex128, EXx } },
9160     { "(bad)",          { XX } },
9161   },
9162
9163   /* VEX_LEN_38DF_P_2 */
9164   {
9165     { "vaesdeclast",    { XM, Vex128, EXx } },
9166     { "(bad)",          { XX } },
9167   },
9168
9169   /* VEX_LEN_3A06_P_2 */
9170   {
9171     { "(bad)",          { XX } },
9172     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
9173   },
9174
9175   /* VEX_LEN_3A0A_P_2 */
9176   {
9177     { "vroundss",       { XM, Vex128, EXd, Ib } },
9178     { "(bad)",          { XX } },
9179   },
9180
9181   /* VEX_LEN_3A0B_P_2 */
9182   {
9183     { "vroundsd",       { XM, Vex128, EXq, Ib } },
9184     { "(bad)",          { XX } },
9185   },
9186
9187   /* VEX_LEN_3A0E_P_2 */
9188   {
9189     { "vpblendw",       { XM, Vex128, EXx, Ib } },
9190     { "(bad)",          { XX } },
9191   },
9192
9193   /* VEX_LEN_3A0F_P_2 */
9194   {
9195     { "vpalignr",       { XM, Vex128, EXx, Ib } },
9196     { "(bad)",          { XX } },
9197   },
9198
9199   /* VEX_LEN_3A14_P_2 */
9200   {
9201     { "vpextrb",        { Edqb, XM, Ib } },
9202     { "(bad)",          { XX } },
9203   },
9204
9205   /* VEX_LEN_3A15_P_2 */
9206   {
9207     { "vpextrw",        { Edqw, XM, Ib } },
9208     { "(bad)",          { XX } },
9209   },
9210
9211   /* VEX_LEN_3A16_P_2  */
9212   {
9213     { "vpextrK",        { Edq, XM, Ib } },
9214     { "(bad)",          { XX } },
9215   },
9216
9217   /* VEX_LEN_3A17_P_2 */
9218   {
9219     { "vextractps",     { Edqd, XM, Ib } },
9220     { "(bad)",          { XX } },
9221   },
9222
9223   /* VEX_LEN_3A18_P_2 */
9224   {
9225     { "(bad)",          { XX } },
9226     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
9227   },
9228
9229   /* VEX_LEN_3A19_P_2 */
9230   {
9231     { "(bad)",          { XX } },
9232     { "vextractf128",   { EXxmm, XM, Ib } },
9233   },
9234
9235   /* VEX_LEN_3A20_P_2 */
9236   {
9237     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
9238     { "(bad)",          { XX } },
9239   },
9240
9241   /* VEX_LEN_3A21_P_2 */
9242   {
9243     { "vinsertps",      { XM, Vex128, EXd, Ib } },
9244     { "(bad)",          { XX } },
9245   },
9246
9247   /* VEX_LEN_3A22_P_2 */
9248   {
9249     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
9250     { "(bad)",          { XX } },
9251   },
9252
9253   /* VEX_LEN_3A41_P_2 */
9254   {
9255     { "vdppd",          { XM, Vex128, EXx, Ib } },
9256     { "(bad)",          { XX } },
9257   },
9258
9259   /* VEX_LEN_3A42_P_2 */
9260   {
9261     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
9262     { "(bad)",          { XX } },
9263   },
9264
9265   /* VEX_LEN_3A44_P_2 */
9266   {
9267     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
9268     { "(bad)",          { XX } },
9269   },
9270
9271   /* VEX_LEN_3A4C_P_2 */
9272   {
9273     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
9274     { "(bad)",          { XX } },
9275   },
9276
9277   /* VEX_LEN_3A60_P_2 */
9278   {
9279     { "vpcmpestrm",     { XM, EXx, Ib } },
9280     { "(bad)",          { XX } },
9281   },
9282
9283   /* VEX_LEN_3A61_P_2 */
9284   {
9285     { "vpcmpestri",     { XM, EXx, Ib } },
9286     { "(bad)",          { XX } },
9287   },
9288
9289   /* VEX_LEN_3A62_P_2 */
9290   {
9291     { "vpcmpistrm",     { XM, EXx, Ib } },
9292     { "(bad)",          { XX } },
9293   },
9294
9295   /* VEX_LEN_3A63_P_2 */
9296   {
9297     { "vpcmpistri",     { XM, EXx, Ib } },
9298     { "(bad)",          { XX } },
9299   },
9300
9301   /* VEX_LEN_3A6A_P_2 */
9302   {
9303     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9304     { "(bad)",          { XX } },
9305   },
9306
9307   /* VEX_LEN_3A6B_P_2 */
9308   {
9309     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9310     { "(bad)",          { XX } },
9311   },
9312
9313   /* VEX_LEN_3A6E_P_2 */
9314   {
9315     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9316     { "(bad)",          { XX } },
9317   },
9318
9319   /* VEX_LEN_3A6F_P_2 */
9320   {
9321     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9322     { "(bad)",          { XX } },
9323   },
9324
9325   /* VEX_LEN_3A7A_P_2 */
9326   {
9327     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9328     { "(bad)",          { XX } },
9329   },
9330
9331   /* VEX_LEN_3A7B_P_2 */
9332   {
9333     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9334     { "(bad)",          { XX } },
9335   },
9336
9337   /* VEX_LEN_3A7E_P_2 */
9338   {
9339     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9340     { "(bad)",          { XX } },
9341   },
9342
9343   /* VEX_LEN_3A7F_P_2 */
9344   {
9345     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9346     { "(bad)",          { XX } },
9347   },
9348
9349   /* VEX_LEN_3ADF_P_2 */
9350   {
9351     { "vaeskeygenassist", { XM, EXx, Ib } },
9352     { "(bad)",          { XX } },
9353   },
9354   /* VEX_LEN_XOP_09_80 */
9355   {
9356     { "vfrczps", { XM, EXxmm } },
9357     { "vfrczps", { XM, EXymmq } },
9358   },
9359   /* VEX_LEN_XOP_09_81 */
9360   {
9361     { "vfrczpd", { XM, EXxmm } },
9362     { "vfrczpd", { XM, EXymmq } },
9363   },
9364 };
9365
9366 static const struct dis386 mod_table[][2] = {
9367   {
9368     /* MOD_8D */
9369     { "leaS",           { Gv, M } },
9370     { "(bad)",          { XX } },
9371   },
9372   {
9373     /* MOD_0F01_REG_0 */
9374     { X86_64_TABLE (X86_64_0F01_REG_0) },
9375     { RM_TABLE (RM_0F01_REG_0) },
9376   },
9377   {
9378     /* MOD_0F01_REG_1 */
9379     { X86_64_TABLE (X86_64_0F01_REG_1) },
9380     { RM_TABLE (RM_0F01_REG_1) },
9381   },
9382   {
9383     /* MOD_0F01_REG_2 */
9384     { X86_64_TABLE (X86_64_0F01_REG_2) },
9385     { RM_TABLE (RM_0F01_REG_2) },
9386   },
9387   {
9388     /* MOD_0F01_REG_3 */
9389     { X86_64_TABLE (X86_64_0F01_REG_3) },
9390     { RM_TABLE (RM_0F01_REG_3) },
9391   },
9392   {
9393     /* MOD_0F01_REG_7 */
9394     { "invlpg",         { Mb } },
9395     { RM_TABLE (RM_0F01_REG_7) },
9396   },
9397   {
9398     /* MOD_0F12_PREFIX_0 */
9399     { "movlps",         { XM, EXq } },
9400     { "movhlps",        { XM, EXq } },
9401   },
9402   {
9403     /* MOD_0F13 */
9404     { "movlpX",         { EXq, XM } },
9405     { "(bad)",          { XX } },
9406   },
9407   {
9408     /* MOD_0F16_PREFIX_0 */
9409     { "movhps",         { XM, EXq } },
9410     { "movlhps",        { XM, EXq } },
9411   },
9412   {
9413     /* MOD_0F17 */
9414     { "movhpX",         { EXq, XM } },
9415     { "(bad)",          { XX } },
9416   },
9417   {
9418     /* MOD_0F18_REG_0 */
9419     { "prefetchnta",    { Mb } },
9420     { "(bad)",          { XX } },
9421   },
9422   {
9423     /* MOD_0F18_REG_1 */
9424     { "prefetcht0",     { Mb } },
9425     { "(bad)",          { XX } },
9426   },
9427   {
9428     /* MOD_0F18_REG_2 */
9429     { "prefetcht1",     { Mb } },
9430     { "(bad)",          { XX } },
9431   },
9432   {
9433     /* MOD_0F18_REG_3 */
9434     { "prefetcht2",     { Mb } },
9435     { "(bad)",          { XX } },
9436   },
9437   {
9438     /* MOD_0F20 */
9439     { "(bad)",          { XX } },
9440     { "movZ",           { Rm, Cm } },
9441   },
9442   {
9443     /* MOD_0F21 */
9444     { "(bad)",          { XX } },
9445     { "movZ",           { Rm, Dm } },
9446   },
9447   {
9448     /* MOD_0F22 */
9449     { "(bad)",          { XX } },
9450     { "movZ",           { Cm, Rm } },
9451   },
9452   {
9453     /* MOD_0F23 */
9454     { "(bad)",          { XX } },
9455     { "movZ",           { Dm, Rm } },
9456   },
9457   {
9458     /* MOD_0F24 */
9459     { "(bad)",          { XX } },
9460     { "movL",           { Rd, Td } },
9461   },
9462   {
9463     /* MOD_0F26 */
9464     { "(bad)",          { XX } },
9465     { "movL",           { Td, Rd } },
9466   },
9467   {
9468     /* MOD_0F2B_PREFIX_0 */
9469     {"movntps",         { Mx, XM } },
9470     { "(bad)",          { XX } },
9471   },
9472   {
9473     /* MOD_0F2B_PREFIX_1 */
9474     {"movntss",         { Md, XM } },
9475     { "(bad)",          { XX } },
9476   },
9477   {
9478     /* MOD_0F2B_PREFIX_2 */
9479     {"movntpd",         { Mx, XM } },
9480     { "(bad)",          { XX } },
9481   },
9482   {
9483     /* MOD_0F2B_PREFIX_3 */
9484     {"movntsd",         { Mq, XM } },
9485     { "(bad)",          { XX } },
9486   },
9487   {
9488     /* MOD_0F51 */
9489     { "(bad)",          { XX } },
9490     { "movmskpX",       { Gdq, XS } },
9491   },
9492   {
9493     /* MOD_0F71_REG_2 */
9494     { "(bad)",          { XX } },
9495     { "psrlw",          { MS, Ib } },
9496   },
9497   {
9498     /* MOD_0F71_REG_4 */
9499     { "(bad)",          { XX } },
9500     { "psraw",          { MS, Ib } },
9501   },
9502   {
9503     /* MOD_0F71_REG_6 */
9504     { "(bad)",          { XX } },
9505     { "psllw",          { MS, Ib } },
9506   },
9507   {
9508     /* MOD_0F72_REG_2 */
9509     { "(bad)",          { XX } },
9510     { "psrld",          { MS, Ib } },
9511   },
9512   {
9513     /* MOD_0F72_REG_4 */
9514     { "(bad)",          { XX } },
9515     { "psrad",          { MS, Ib } },
9516   },
9517   {
9518     /* MOD_0F72_REG_6 */
9519     { "(bad)",          { XX } },
9520     { "pslld",          { MS, Ib } },
9521   },
9522   {
9523     /* MOD_0F73_REG_2 */
9524     { "(bad)",          { XX } },
9525     { "psrlq",          { MS, Ib } },
9526   },
9527   {
9528     /* MOD_0F73_REG_3 */
9529     { "(bad)",          { XX } },
9530     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
9531   },
9532   {
9533     /* MOD_0F73_REG_6 */
9534     { "(bad)",          { XX } },
9535     { "psllq",          { MS, Ib } },
9536   },
9537   {
9538     /* MOD_0F73_REG_7 */
9539     { "(bad)",          { XX } },
9540     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
9541   },
9542   {
9543     /* MOD_0FAE_REG_0 */
9544     { "fxsave",         { M } },
9545     { "(bad)",          { XX } },
9546   },
9547   {
9548     /* MOD_0FAE_REG_1 */
9549     { "fxrstor",        { M } },
9550     { "(bad)",          { XX } },
9551   },
9552   {
9553     /* MOD_0FAE_REG_2 */
9554     { "ldmxcsr",        { Md } },
9555     { "(bad)",          { XX } },
9556   },
9557   {
9558     /* MOD_0FAE_REG_3 */
9559     { "stmxcsr",        { Md } },
9560     { "(bad)",          { XX } },
9561   },
9562   {
9563     /* MOD_0FAE_REG_4 */
9564     { "xsave",          { M } },
9565     { "(bad)",          { XX } },
9566   },
9567   {
9568     /* MOD_0FAE_REG_5 */
9569     { "xrstor",         { M } },
9570     { RM_TABLE (RM_0FAE_REG_5) },
9571   },
9572   {
9573     /* MOD_0FAE_REG_6 */
9574     { "xsaveopt",       { M } },
9575     { RM_TABLE (RM_0FAE_REG_6) },
9576   },
9577   {
9578     /* MOD_0FAE_REG_7 */
9579     { "clflush",        { Mb } },
9580     { RM_TABLE (RM_0FAE_REG_7) },
9581   },
9582   {
9583     /* MOD_0FB2 */
9584     { "lssS",           { Gv, Mp } },
9585     { "(bad)",          { XX } },
9586   },
9587   {
9588     /* MOD_0FB4 */
9589     { "lfsS",           { Gv, Mp } },
9590     { "(bad)",          { XX } },
9591   },
9592   {
9593     /* MOD_0FB5 */
9594     { "lgsS",           { Gv, Mp } },
9595     { "(bad)",          { XX } },
9596   },
9597   {
9598     /* MOD_0FC7_REG_6 */
9599     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
9600     { "(bad)",          { XX } },
9601   },
9602   {
9603     /* MOD_0FC7_REG_7 */
9604     { "vmptrst",        { Mq } },
9605     { "(bad)",          { XX } },
9606   },
9607   {
9608     /* MOD_0FD7 */
9609     { "(bad)",          { XX } },
9610     { "pmovmskb",       { Gdq, MS } },
9611   },
9612   {
9613     /* MOD_0FE7_PREFIX_2 */
9614     { "movntdq",        { Mx, XM } },
9615     { "(bad)",          { XX } },
9616   },
9617   {
9618     /* MOD_0FF0_PREFIX_3 */
9619     { "lddqu",          { XM, M } },
9620     { "(bad)",          { XX } },
9621   },
9622   {
9623     /* MOD_0F382A_PREFIX_2 */
9624     { "movntdqa",       { XM, Mx } },
9625     { "(bad)",          { XX } },
9626   },
9627   {
9628     /* MOD_62_32BIT */
9629     { "bound{S|}",      { Gv, Ma } },
9630     { "(bad)",          { XX } },
9631   },
9632   {
9633     /* MOD_C4_32BIT */
9634     { "lesS",           { Gv, Mp } },
9635     { VEX_C4_TABLE (VEX_0F) },
9636   },
9637   {
9638     /* MOD_C5_32BIT */
9639     { "ldsS",           { Gv, Mp } },
9640     { VEX_C5_TABLE (VEX_0F) },
9641   },
9642   {
9643     /* MOD_VEX_12_PREFIX_0 */
9644     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
9645     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
9646   },
9647   {
9648     /* MOD_VEX_13 */
9649     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
9650     { "(bad)",          { XX } },
9651   },
9652   {
9653     /* MOD_VEX_16_PREFIX_0 */
9654     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
9655     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
9656   },
9657   {
9658     /* MOD_VEX_17 */
9659     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
9660     { "(bad)",          { XX } },
9661   },
9662   {
9663     /* MOD_VEX_2B */
9664     { "vmovntpX",       { Mx, XM } },
9665     { "(bad)",          { XX } },
9666   },
9667   {
9668     /* MOD_VEX_51 */
9669     { "(bad)",          { XX } },
9670     { "vmovmskpX",      { Gdq, XS } },
9671   },
9672   {
9673     /* MOD_VEX_71_REG_2 */
9674     { "(bad)",          { XX } },
9675     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
9676   },
9677   {
9678     /* MOD_VEX_71_REG_4 */
9679     { "(bad)",          { XX } },
9680     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
9681   },
9682   {
9683     /* MOD_VEX_71_REG_6 */
9684     { "(bad)",          { XX } },
9685     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
9686   },
9687   {
9688     /* MOD_VEX_72_REG_2 */
9689     { "(bad)",          { XX } },
9690     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
9691   },
9692   {
9693     /* MOD_VEX_72_REG_4 */
9694     { "(bad)",          { XX } },
9695     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
9696   },
9697   {
9698     /* MOD_VEX_72_REG_6 */
9699     { "(bad)",          { XX } },
9700     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
9701   },
9702   {
9703     /* MOD_VEX_73_REG_2 */
9704     { "(bad)",          { XX } },
9705     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
9706   },
9707   {
9708     /* MOD_VEX_73_REG_3 */
9709     { "(bad)",          { XX } },
9710     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
9711   },
9712   {
9713     /* MOD_VEX_73_REG_6 */
9714     { "(bad)",          { XX } },
9715     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
9716   },
9717   {
9718     /* MOD_VEX_73_REG_7 */
9719     { "(bad)",          { XX } },
9720     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
9721   },
9722   {
9723     /* MOD_VEX_AE_REG_2 */
9724     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
9725     { "(bad)",          { XX } },
9726   },
9727   {
9728     /* MOD_VEX_AE_REG_3 */
9729     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
9730     { "(bad)",          { XX } },
9731   },
9732   {
9733     /* MOD_VEX_D7_PREFIX_2 */
9734     { "(bad)",          { XX } },
9735     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
9736   },
9737   {
9738     /* MOD_VEX_E7_PREFIX_2 */
9739     { "vmovntdq",       { Mx, XM } },
9740     { "(bad)",          { XX } },
9741   },
9742   {
9743     /* MOD_VEX_F0_PREFIX_3 */
9744     { "vlddqu",         { XM, M } },
9745     { "(bad)",          { XX } },
9746   },
9747   {
9748     /* MOD_VEX_3818_PREFIX_2 */
9749     { "vbroadcastss",   { XM, Md } },
9750     { "(bad)",          { XX } },
9751   },
9752   {
9753     /* MOD_VEX_3819_PREFIX_2 */
9754     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
9755     { "(bad)",          { XX } },
9756   },
9757   {
9758     /* MOD_VEX_381A_PREFIX_2 */
9759     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
9760     { "(bad)",          { XX } },
9761   },
9762   {
9763     /* MOD_VEX_382A_PREFIX_2 */
9764     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
9765     { "(bad)",          { XX } },
9766   },
9767   {
9768     /* MOD_VEX_382C_PREFIX_2 */
9769     { "vmaskmovps",     { XM, Vex, Mx } },
9770     { "(bad)",          { XX } },
9771   },
9772   {
9773     /* MOD_VEX_382D_PREFIX_2 */
9774     { "vmaskmovpd",     { XM, Vex, Mx } },
9775     { "(bad)",          { XX } },
9776   },
9777   {
9778     /* MOD_VEX_382E_PREFIX_2 */
9779     { "vmaskmovps",     { Mx, Vex, XM } },
9780     { "(bad)",          { XX } },
9781   },
9782   {
9783     /* MOD_VEX_382F_PREFIX_2 */
9784     { "vmaskmovpd",     { Mx, Vex, XM } },
9785     { "(bad)",          { XX } },
9786   },
9787 };
9788
9789 static const struct dis386 rm_table[][8] = {
9790   {
9791     /* RM_0F01_REG_0 */
9792     { "(bad)",          { XX } },
9793     { "vmcall",         { Skip_MODRM } },
9794     { "vmlaunch",       { Skip_MODRM } },
9795     { "vmresume",       { Skip_MODRM } },
9796     { "vmxoff",         { Skip_MODRM } },
9797     { "(bad)",          { XX } },
9798     { "(bad)",          { XX } },
9799     { "(bad)",          { XX } },
9800   },
9801   {
9802     /* RM_0F01_REG_1 */
9803     { "monitor",        { { OP_Monitor, 0 } } },
9804     { "mwait",          { { OP_Mwait, 0 } } },
9805     { "(bad)",          { XX } },
9806     { "(bad)",          { XX } },
9807     { "(bad)",          { XX } },
9808     { "(bad)",          { XX } },
9809     { "(bad)",          { XX } },
9810     { "(bad)",          { XX } },
9811   },
9812   {
9813     /* RM_0F01_REG_2 */
9814     { "xgetbv",         { Skip_MODRM } },
9815     { "xsetbv",         { Skip_MODRM } },
9816     { "(bad)",          { XX } },
9817     { "(bad)",          { XX } },
9818     { "(bad)",          { XX } },
9819     { "(bad)",          { XX } },
9820     { "(bad)",          { XX } },
9821     { "(bad)",          { XX } },
9822   },
9823   {
9824     /* RM_0F01_REG_3 */
9825     { "vmrun",          { Skip_MODRM } },
9826     { "vmmcall",        { Skip_MODRM } },
9827     { "vmload",         { Skip_MODRM } },
9828     { "vmsave",         { Skip_MODRM } },
9829     { "stgi",           { Skip_MODRM } },
9830     { "clgi",           { Skip_MODRM } },
9831     { "skinit",         { Skip_MODRM } },
9832     { "invlpga",        { Skip_MODRM } },
9833   },
9834   {
9835     /* RM_0F01_REG_7 */
9836     { "swapgs",         { Skip_MODRM } },
9837     { "rdtscp",         { Skip_MODRM } },
9838     { "(bad)",          { XX } },
9839     { "(bad)",          { XX } },
9840     { "(bad)",          { XX } },
9841     { "(bad)",          { XX } },
9842     { "(bad)",          { XX } },
9843     { "(bad)",          { XX } },
9844   },
9845   {
9846     /* RM_0FAE_REG_5 */
9847     { "lfence",         { Skip_MODRM } },
9848     { "(bad)",          { XX } },
9849     { "(bad)",          { XX } },
9850     { "(bad)",          { XX } },
9851     { "(bad)",          { XX } },
9852     { "(bad)",          { XX } },
9853     { "(bad)",          { XX } },
9854     { "(bad)",          { XX } },
9855   },
9856   {
9857     /* RM_0FAE_REG_6 */
9858     { "mfence",         { Skip_MODRM } },
9859     { "(bad)",          { XX } },
9860     { "(bad)",          { XX } },
9861     { "(bad)",          { XX } },
9862     { "(bad)",          { XX } },
9863     { "(bad)",          { XX } },
9864     { "(bad)",          { XX } },
9865     { "(bad)",          { XX } },
9866   },
9867   {
9868     /* RM_0FAE_REG_7 */
9869     { "sfence",         { Skip_MODRM } },
9870     { "(bad)",          { XX } },
9871     { "(bad)",          { XX } },
9872     { "(bad)",          { XX } },
9873     { "(bad)",          { XX } },
9874     { "(bad)",          { XX } },
9875     { "(bad)",          { XX } },
9876     { "(bad)",          { XX } },
9877   },
9878 };
9879
9880 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9881
9882 /* We use the high bit to indicate different name for the same
9883    prefix.  */
9884 #define ADDR16_PREFIX   (0x67 | 0x100)
9885 #define ADDR32_PREFIX   (0x67 | 0x200)
9886 #define DATA16_PREFIX   (0x66 | 0x100)
9887 #define DATA32_PREFIX   (0x66 | 0x200)
9888 #define REP_PREFIX      (0xf3 | 0x100)
9889
9890 static int
9891 ckprefix (void)
9892 {
9893   int newrex, i, length;
9894   rex = 0;
9895   rex_original = 0;
9896   rex_ignored = 0;
9897   prefixes = 0;
9898   used_prefixes = 0;
9899   rex_used = 0;
9900   last_lock_prefix = -1;
9901   last_repz_prefix = -1;
9902   last_repnz_prefix = -1;
9903   last_data_prefix = -1;
9904   last_addr_prefix = -1;
9905   last_rex_prefix = -1;
9906   last_seg_prefix = -1;
9907   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9908     all_prefixes[i] = 0;
9909   i = 0;
9910   length = 0;
9911   /* The maximum instruction length is 15bytes.  */
9912   while (length < MAX_CODE_LENGTH - 1)
9913     {
9914       FETCH_DATA (the_info, codep + 1);
9915       newrex = 0;
9916       switch (*codep)
9917         {
9918         /* REX prefixes family.  */
9919         case 0x40:
9920         case 0x41:
9921         case 0x42:
9922         case 0x43:
9923         case 0x44:
9924         case 0x45:
9925         case 0x46:
9926         case 0x47:
9927         case 0x48:
9928         case 0x49:
9929         case 0x4a:
9930         case 0x4b:
9931         case 0x4c:
9932         case 0x4d:
9933         case 0x4e:
9934         case 0x4f:
9935           if (address_mode == mode_64bit)
9936             newrex = *codep;
9937           else
9938             return 1;
9939           last_rex_prefix = i;
9940           break;
9941         case 0xf3:
9942           prefixes |= PREFIX_REPZ;
9943           last_repz_prefix = i;
9944           break;
9945         case 0xf2:
9946           prefixes |= PREFIX_REPNZ;
9947           last_repnz_prefix = i;
9948           break;
9949         case 0xf0:
9950           prefixes |= PREFIX_LOCK;
9951           last_lock_prefix = i;
9952           break;
9953         case 0x2e:
9954           prefixes |= PREFIX_CS;
9955           last_seg_prefix = i;
9956           break;
9957         case 0x36:
9958           prefixes |= PREFIX_SS;
9959           last_seg_prefix = i;
9960           break;
9961         case 0x3e:
9962           prefixes |= PREFIX_DS;
9963           last_seg_prefix = i;
9964           break;
9965         case 0x26:
9966           prefixes |= PREFIX_ES;
9967           last_seg_prefix = i;
9968           break;
9969         case 0x64:
9970           prefixes |= PREFIX_FS;
9971           last_seg_prefix = i;
9972           break;
9973         case 0x65:
9974           prefixes |= PREFIX_GS;
9975           last_seg_prefix = i;
9976           break;
9977         case 0x66:
9978           prefixes |= PREFIX_DATA;
9979           last_data_prefix = i;
9980           break;
9981         case 0x67:
9982           prefixes |= PREFIX_ADDR;
9983           last_addr_prefix = i;
9984           break;
9985         case FWAIT_OPCODE:
9986           /* fwait is really an instruction.  If there are prefixes
9987              before the fwait, they belong to the fwait, *not* to the
9988              following instruction.  */
9989           if (prefixes || rex)
9990             {
9991               prefixes |= PREFIX_FWAIT;
9992               codep++;
9993               return 1;
9994             }
9995           prefixes = PREFIX_FWAIT;
9996           break;
9997         default:
9998           return 1;
9999         }
10000       /* Rex is ignored when followed by another prefix.  */
10001       if (rex)
10002         {
10003           rex_used = rex;
10004           return 1;
10005         }
10006       if (*codep != FWAIT_OPCODE)
10007         all_prefixes[i++] = *codep;
10008       rex = newrex;
10009       rex_original = rex;
10010       codep++;
10011       length++;
10012     }
10013   return 0;
10014 }
10015
10016 static int
10017 seg_prefix (int pref)
10018 {
10019   switch (pref)
10020     {
10021     case 0x2e:
10022       return PREFIX_CS;
10023     case 0x36:
10024       return PREFIX_SS;
10025     case 0x3e:
10026       return PREFIX_DS;
10027     case 0x26:
10028       return PREFIX_ES;
10029     case 0x64:
10030       return PREFIX_FS;
10031     case 0x65:
10032       return PREFIX_GS;
10033     default:
10034       return 0;
10035     }
10036 }
10037
10038 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10039    prefix byte.  */
10040
10041 static const char *
10042 prefix_name (int pref, int sizeflag)
10043 {
10044   static const char *rexes [16] =
10045     {
10046       "rex",            /* 0x40 */
10047       "rex.B",          /* 0x41 */
10048       "rex.X",          /* 0x42 */
10049       "rex.XB",         /* 0x43 */
10050       "rex.R",          /* 0x44 */
10051       "rex.RB",         /* 0x45 */
10052       "rex.RX",         /* 0x46 */
10053       "rex.RXB",        /* 0x47 */
10054       "rex.W",          /* 0x48 */
10055       "rex.WB",         /* 0x49 */
10056       "rex.WX",         /* 0x4a */
10057       "rex.WXB",        /* 0x4b */
10058       "rex.WR",         /* 0x4c */
10059       "rex.WRB",        /* 0x4d */
10060       "rex.WRX",        /* 0x4e */
10061       "rex.WRXB",       /* 0x4f */
10062     };
10063
10064   switch (pref)
10065     {
10066     /* REX prefixes family.  */
10067     case 0x40:
10068     case 0x41:
10069     case 0x42:
10070     case 0x43:
10071     case 0x44:
10072     case 0x45:
10073     case 0x46:
10074     case 0x47:
10075     case 0x48:
10076     case 0x49:
10077     case 0x4a:
10078     case 0x4b:
10079     case 0x4c:
10080     case 0x4d:
10081     case 0x4e:
10082     case 0x4f:
10083       return rexes [pref - 0x40];
10084     case 0xf3:
10085       return "repz";
10086     case 0xf2:
10087       return "repnz";
10088     case 0xf0:
10089       return "lock";
10090     case 0x2e:
10091       return "cs";
10092     case 0x36:
10093       return "ss";
10094     case 0x3e:
10095       return "ds";
10096     case 0x26:
10097       return "es";
10098     case 0x64:
10099       return "fs";
10100     case 0x65:
10101       return "gs";
10102     case 0x66:
10103       return (sizeflag & DFLAG) ? "data16" : "data32";
10104     case 0x67:
10105       if (address_mode == mode_64bit)
10106         return (sizeflag & AFLAG) ? "addr32" : "addr64";
10107       else
10108         return (sizeflag & AFLAG) ? "addr16" : "addr32";
10109     case FWAIT_OPCODE:
10110       return "fwait";
10111     case ADDR16_PREFIX:
10112       return "addr16";
10113     case ADDR32_PREFIX:
10114       return "addr32";
10115     case DATA16_PREFIX:
10116       return "data16";
10117     case DATA32_PREFIX:
10118       return "data32";
10119     case REP_PREFIX:
10120       return "rep";
10121     default:
10122       return NULL;
10123     }
10124 }
10125
10126 static char op_out[MAX_OPERANDS][100];
10127 static int op_ad, op_index[MAX_OPERANDS];
10128 static int two_source_ops;
10129 static bfd_vma op_address[MAX_OPERANDS];
10130 static bfd_vma op_riprel[MAX_OPERANDS];
10131 static bfd_vma start_pc;
10132
10133 /*
10134  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10135  *   (see topic "Redundant prefixes" in the "Differences from 8086"
10136  *   section of the "Virtual 8086 Mode" chapter.)
10137  * 'pc' should be the address of this instruction, it will
10138  *   be used to print the target address if this is a relative jump or call
10139  * The function returns the length of this instruction in bytes.
10140  */
10141
10142 static char intel_syntax;
10143 static char intel_mnemonic = !SYSV386_COMPAT;
10144 static char open_char;
10145 static char close_char;
10146 static char separator_char;
10147 static char scale_char;
10148
10149 /* Here for backwards compatibility.  When gdb stops using
10150    print_insn_i386_att and print_insn_i386_intel these functions can
10151    disappear, and print_insn_i386 be merged into print_insn.  */
10152 int
10153 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10154 {
10155   intel_syntax = 0;
10156
10157   return print_insn (pc, info);
10158 }
10159
10160 int
10161 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10162 {
10163   intel_syntax = 1;
10164
10165   return print_insn (pc, info);
10166 }
10167
10168 int
10169 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10170 {
10171   intel_syntax = -1;
10172
10173   return print_insn (pc, info);
10174 }
10175
10176 void
10177 print_i386_disassembler_options (FILE *stream)
10178 {
10179   fprintf (stream, _("\n\
10180 The following i386/x86-64 specific disassembler options are supported for use\n\
10181 with the -M switch (multiple options should be separated by commas):\n"));
10182
10183   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
10184   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
10185   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
10186   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
10187   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
10188   fprintf (stream, _("  att-mnemonic\n"
10189                      "              Display instruction in AT&T mnemonic\n"));
10190   fprintf (stream, _("  intel-mnemonic\n"
10191                      "              Display instruction in Intel mnemonic\n"));
10192   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
10193   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
10194   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
10195   fprintf (stream, _("  data32      Assume 32bit data size\n"));
10196   fprintf (stream, _("  data16      Assume 16bit data size\n"));
10197   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
10198 }
10199
10200 /* Get a pointer to struct dis386 with a valid name.  */
10201
10202 static const struct dis386 *
10203 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10204 {
10205   int index, vex_table_index;
10206
10207   if (dp->name != NULL)
10208     return dp;
10209
10210   switch (dp->op[0].bytemode)
10211     {
10212     case USE_REG_TABLE:
10213       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
10214       break;
10215
10216     case USE_MOD_TABLE:
10217       index = modrm.mod == 0x3 ? 1 : 0;
10218       dp = &mod_table[dp->op[1].bytemode][index];
10219       break;
10220
10221     case USE_RM_TABLE:
10222       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
10223       break;
10224
10225     case USE_PREFIX_TABLE:
10226       if (need_vex)
10227         {
10228           /* The prefix in VEX is implicit.  */
10229           switch (vex.prefix)
10230             {
10231             case 0:
10232               index = 0;
10233               break;
10234             case REPE_PREFIX_OPCODE:
10235               index = 1;
10236               break;
10237             case DATA_PREFIX_OPCODE:
10238               index = 2;
10239               break;
10240             case REPNE_PREFIX_OPCODE:
10241               index = 3;
10242               break;
10243             default:
10244               abort ();
10245               break;
10246             }
10247         }
10248       else
10249         {
10250           index = 0;
10251           used_prefixes |= (prefixes & PREFIX_REPZ);
10252           if (prefixes & PREFIX_REPZ)
10253             {
10254               index = 1;
10255               all_prefixes[last_repz_prefix] = 0;
10256             }
10257           else
10258             {
10259               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
10260                  PREFIX_DATA.  */
10261               used_prefixes |= (prefixes & PREFIX_REPNZ);
10262               if (prefixes & PREFIX_REPNZ)
10263                 {
10264                   index = 3;
10265                   all_prefixes[last_repnz_prefix] = 0;
10266                 }
10267               else
10268                 {
10269                   used_prefixes |= (prefixes & PREFIX_DATA);
10270                   if (prefixes & PREFIX_DATA)
10271                     {
10272                       index = 2;
10273                       all_prefixes[last_data_prefix] = 0;
10274                     }
10275                 }
10276             }
10277         }
10278       dp = &prefix_table[dp->op[1].bytemode][index];
10279       break;
10280
10281     case USE_X86_64_TABLE:
10282       index = address_mode == mode_64bit ? 1 : 0;
10283       dp = &x86_64_table[dp->op[1].bytemode][index];
10284       break;
10285
10286     case USE_3BYTE_TABLE:
10287       FETCH_DATA (info, codep + 2);
10288       index = *codep++;
10289       dp = &three_byte_table[dp->op[1].bytemode][index];
10290       modrm.mod = (*codep >> 6) & 3;
10291       modrm.reg = (*codep >> 3) & 7;
10292       modrm.rm = *codep & 7;
10293       break;
10294
10295     case USE_VEX_LEN_TABLE:
10296       if (!need_vex)
10297         abort ();
10298
10299       switch (vex.length)
10300         {
10301         case 128:
10302           index = 0;
10303           break;
10304         case 256:
10305           index = 1;
10306           break;
10307         default:
10308           abort ();
10309           break;
10310         }
10311
10312       dp = &vex_len_table[dp->op[1].bytemode][index];
10313       break;
10314
10315     case USE_XOP_8F_TABLE:
10316       FETCH_DATA (info, codep + 3);
10317       /* All bits in the REX prefix are ignored.  */
10318       rex_ignored = rex;
10319       rex = ~(*codep >> 5) & 0x7;
10320
10321       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
10322       switch ((*codep & 0x1f))
10323         {
10324         default:
10325           BadOp ();
10326         case 0x8:
10327           vex_table_index = XOP_08;
10328           break;
10329         case 0x9:
10330           vex_table_index = XOP_09;
10331           break;
10332         case 0xa:
10333           vex_table_index = XOP_0A;
10334           break;
10335         }
10336       codep++;
10337       vex.w = *codep & 0x80;
10338       if (vex.w && address_mode == mode_64bit)
10339         rex |= REX_W;
10340
10341       vex.register_specifier = (~(*codep >> 3)) & 0xf;
10342       if (address_mode != mode_64bit
10343           && vex.register_specifier > 0x7)
10344         BadOp ();
10345
10346       vex.length = (*codep & 0x4) ? 256 : 128;
10347       switch ((*codep & 0x3))
10348         {
10349         case 0:
10350           vex.prefix = 0;
10351           break;
10352         case 1:
10353           vex.prefix = DATA_PREFIX_OPCODE;
10354           break;
10355         case 2:
10356           vex.prefix = REPE_PREFIX_OPCODE;
10357           break;
10358         case 3:
10359           vex.prefix = REPNE_PREFIX_OPCODE;
10360           break;
10361         }
10362       need_vex = 1;
10363       need_vex_reg = 1;
10364       codep++;
10365       index = *codep++;
10366       dp = &xop_table[vex_table_index][index];
10367
10368       FETCH_DATA (info, codep + 1);
10369       modrm.mod = (*codep >> 6) & 3;
10370       modrm.reg = (*codep >> 3) & 7;
10371       modrm.rm = *codep & 7;
10372       break;
10373
10374     case USE_VEX_C4_TABLE:
10375       FETCH_DATA (info, codep + 3);
10376       /* All bits in the REX prefix are ignored.  */
10377       rex_ignored = rex;
10378       rex = ~(*codep >> 5) & 0x7;
10379       switch ((*codep & 0x1f))
10380         {
10381         default:
10382           BadOp ();
10383         case 0x1:
10384           vex_table_index = VEX_0F;
10385           break;
10386         case 0x2:
10387           vex_table_index = VEX_0F38;
10388           break;
10389         case 0x3:
10390           vex_table_index = VEX_0F3A;
10391           break;
10392         }
10393       codep++;
10394       vex.w = *codep & 0x80;
10395       if (vex.w && address_mode == mode_64bit)
10396         rex |= REX_W;
10397
10398       vex.register_specifier = (~(*codep >> 3)) & 0xf;
10399       if (address_mode != mode_64bit
10400           && vex.register_specifier > 0x7)
10401         BadOp ();
10402
10403       vex.length = (*codep & 0x4) ? 256 : 128;
10404       switch ((*codep & 0x3))
10405         {
10406         case 0:
10407           vex.prefix = 0;
10408           break;
10409         case 1:
10410           vex.prefix = DATA_PREFIX_OPCODE;
10411           break;
10412         case 2:
10413           vex.prefix = REPE_PREFIX_OPCODE;
10414           break;
10415         case 3:
10416           vex.prefix = REPNE_PREFIX_OPCODE;
10417           break;
10418         }
10419       need_vex = 1;
10420       need_vex_reg = 1;
10421       codep++;
10422       index = *codep++;
10423       dp = &vex_table[vex_table_index][index];
10424       /* There is no MODRM byte for VEX [82|77].  */
10425       if (index != 0x77 && index != 0x82)
10426         {
10427           FETCH_DATA (info, codep + 1);
10428           modrm.mod = (*codep >> 6) & 3;
10429           modrm.reg = (*codep >> 3) & 7;
10430           modrm.rm = *codep & 7;
10431         }
10432       break;
10433
10434     case USE_VEX_C5_TABLE:
10435       FETCH_DATA (info, codep + 2);
10436       /* All bits in the REX prefix are ignored.  */
10437       rex_ignored = rex;
10438       rex = (*codep & 0x80) ? 0 : REX_R;
10439
10440       vex.register_specifier = (~(*codep >> 3)) & 0xf;
10441       if (address_mode != mode_64bit
10442           && vex.register_specifier > 0x7)
10443         BadOp ();
10444
10445       vex.length = (*codep & 0x4) ? 256 : 128;
10446       switch ((*codep & 0x3))
10447         {
10448         case 0:
10449           vex.prefix = 0;
10450           break;
10451         case 1:
10452           vex.prefix = DATA_PREFIX_OPCODE;
10453           break;
10454         case 2:
10455           vex.prefix = REPE_PREFIX_OPCODE;
10456           break;
10457         case 3:
10458           vex.prefix = REPNE_PREFIX_OPCODE;
10459           break;
10460         }
10461       need_vex = 1;
10462       need_vex_reg = 1;
10463       codep++;
10464       index = *codep++;
10465       dp = &vex_table[dp->op[1].bytemode][index];
10466       /* There is no MODRM byte for VEX [82|77].  */
10467       if (index != 0x77 && index != 0x82)
10468         {
10469           FETCH_DATA (info, codep + 1);
10470           modrm.mod = (*codep >> 6) & 3;
10471           modrm.reg = (*codep >> 3) & 7;
10472           modrm.rm = *codep & 7;
10473         }
10474       break;
10475
10476     default:
10477       abort ();
10478     }
10479
10480   if (dp->name != NULL)
10481     return dp;
10482   else
10483     return get_valid_dis386 (dp, info);
10484 }
10485
10486 static int
10487 print_insn (bfd_vma pc, disassemble_info *info)
10488 {
10489   const struct dis386 *dp;
10490   int i;
10491   char *op_txt[MAX_OPERANDS];
10492   int needcomma;
10493   int sizeflag;
10494   const char *p;
10495   struct dis_private priv;
10496   unsigned char op;
10497   int prefix_length;
10498   int default_prefixes;
10499
10500   if (info->mach == bfd_mach_x86_64_intel_syntax
10501       || info->mach == bfd_mach_x86_64
10502       || info->mach == bfd_mach_l1om
10503       || info->mach == bfd_mach_l1om_intel_syntax)
10504     address_mode = mode_64bit;
10505   else
10506     address_mode = mode_32bit;
10507
10508   if (intel_syntax == (char) -1)
10509     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
10510                     || info->mach == bfd_mach_x86_64_intel_syntax
10511                     || info->mach == bfd_mach_l1om_intel_syntax);
10512
10513   if (info->mach == bfd_mach_i386_i386
10514       || info->mach == bfd_mach_x86_64
10515       || info->mach == bfd_mach_l1om
10516       || info->mach == bfd_mach_i386_i386_intel_syntax
10517       || info->mach == bfd_mach_x86_64_intel_syntax
10518       || info->mach == bfd_mach_l1om_intel_syntax)
10519     priv.orig_sizeflag = AFLAG | DFLAG;
10520   else if (info->mach == bfd_mach_i386_i8086)
10521     priv.orig_sizeflag = 0;
10522   else
10523     abort ();
10524
10525   for (p = info->disassembler_options; p != NULL; )
10526     {
10527       if (CONST_STRNEQ (p, "x86-64"))
10528         {
10529           address_mode = mode_64bit;
10530           priv.orig_sizeflag = AFLAG | DFLAG;
10531         }
10532       else if (CONST_STRNEQ (p, "i386"))
10533         {
10534           address_mode = mode_32bit;
10535           priv.orig_sizeflag = AFLAG | DFLAG;
10536         }
10537       else if (CONST_STRNEQ (p, "i8086"))
10538         {
10539           address_mode = mode_16bit;
10540           priv.orig_sizeflag = 0;
10541         }
10542       else if (CONST_STRNEQ (p, "intel"))
10543         {
10544           intel_syntax = 1;
10545           if (CONST_STRNEQ (p + 5, "-mnemonic"))
10546             intel_mnemonic = 1;
10547         }
10548       else if (CONST_STRNEQ (p, "att"))
10549         {
10550           intel_syntax = 0;
10551           if (CONST_STRNEQ (p + 3, "-mnemonic"))
10552             intel_mnemonic = 0;
10553         }
10554       else if (CONST_STRNEQ (p, "addr"))
10555         {
10556           if (address_mode == mode_64bit)
10557             {
10558               if (p[4] == '3' && p[5] == '2')
10559                 priv.orig_sizeflag &= ~AFLAG;
10560               else if (p[4] == '6' && p[5] == '4')
10561                 priv.orig_sizeflag |= AFLAG;
10562             }
10563           else
10564             {
10565               if (p[4] == '1' && p[5] == '6')
10566                 priv.orig_sizeflag &= ~AFLAG;
10567               else if (p[4] == '3' && p[5] == '2')
10568                 priv.orig_sizeflag |= AFLAG;
10569             }
10570         }
10571       else if (CONST_STRNEQ (p, "data"))
10572         {
10573           if (p[4] == '1' && p[5] == '6')
10574             priv.orig_sizeflag &= ~DFLAG;
10575           else if (p[4] == '3' && p[5] == '2')
10576             priv.orig_sizeflag |= DFLAG;
10577         }
10578       else if (CONST_STRNEQ (p, "suffix"))
10579         priv.orig_sizeflag |= SUFFIX_ALWAYS;
10580
10581       p = strchr (p, ',');
10582       if (p != NULL)
10583         p++;
10584     }
10585
10586   if (intel_syntax)
10587     {
10588       names64 = intel_names64;
10589       names32 = intel_names32;
10590       names16 = intel_names16;
10591       names8 = intel_names8;
10592       names8rex = intel_names8rex;
10593       names_seg = intel_names_seg;
10594       index64 = intel_index64;
10595       index32 = intel_index32;
10596       index16 = intel_index16;
10597       open_char = '[';
10598       close_char = ']';
10599       separator_char = '+';
10600       scale_char = '*';
10601     }
10602   else
10603     {
10604       names64 = att_names64;
10605       names32 = att_names32;
10606       names16 = att_names16;
10607       names8 = att_names8;
10608       names8rex = att_names8rex;
10609       names_seg = att_names_seg;
10610       index64 = att_index64;
10611       index32 = att_index32;
10612       index16 = att_index16;
10613       open_char = '(';
10614       close_char =  ')';
10615       separator_char = ',';
10616       scale_char = ',';
10617     }
10618
10619   /* The output looks better if we put 7 bytes on a line, since that
10620      puts most long word instructions on a single line.  Use 8 bytes
10621      for Intel L1OM.  */
10622   if (info->mach == bfd_mach_l1om
10623       || info->mach == bfd_mach_l1om_intel_syntax)
10624     info->bytes_per_line = 8;
10625   else
10626     info->bytes_per_line = 7;
10627
10628   info->private_data = &priv;
10629   priv.max_fetched = priv.the_buffer;
10630   priv.insn_start = pc;
10631
10632   obuf[0] = 0;
10633   for (i = 0; i < MAX_OPERANDS; ++i)
10634     {
10635       op_out[i][0] = 0;
10636       op_index[i] = -1;
10637     }
10638
10639   the_info = info;
10640   start_pc = pc;
10641   start_codep = priv.the_buffer;
10642   codep = priv.the_buffer;
10643
10644   if (setjmp (priv.bailout) != 0)
10645     {
10646       const char *name;
10647
10648       /* Getting here means we tried for data but didn't get it.  That
10649          means we have an incomplete instruction of some sort.  Just
10650          print the first byte as a prefix or a .byte pseudo-op.  */
10651       if (codep > priv.the_buffer)
10652         {
10653           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10654           if (name != NULL)
10655             (*info->fprintf_func) (info->stream, "%s", name);
10656           else
10657             {
10658               /* Just print the first byte as a .byte instruction.  */
10659               (*info->fprintf_func) (info->stream, ".byte 0x%x",
10660                                      (unsigned int) priv.the_buffer[0]);
10661             }
10662
10663           return 1;
10664         }
10665
10666       return -1;
10667     }
10668
10669   obufp = obuf;
10670   sizeflag = priv.orig_sizeflag;
10671
10672   if (!ckprefix () || rex_used)
10673     {
10674       /* Too many prefixes or unused REX prefixes.  */
10675       for (i = 0;
10676            all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
10677            i++)
10678         (*info->fprintf_func) (info->stream, "%s",
10679                                prefix_name (all_prefixes[i], sizeflag));
10680       return 1;
10681     }
10682
10683   insn_codep = codep;
10684
10685   FETCH_DATA (info, codep + 1);
10686   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
10687
10688   if (((prefixes & PREFIX_FWAIT)
10689        && ((*codep < 0xd8) || (*codep > 0xdf))))
10690     {
10691       (*info->fprintf_func) (info->stream, "fwait");
10692       return 1;
10693     }
10694
10695   op = 0;
10696
10697   if (*codep == 0x0f)
10698     {
10699       unsigned char threebyte;
10700       FETCH_DATA (info, codep + 2);
10701       threebyte = *++codep;
10702       dp = &dis386_twobyte[threebyte];
10703       need_modrm = twobyte_has_modrm[*codep];
10704       codep++;
10705     }
10706   else
10707     {
10708       dp = &dis386[*codep];
10709       need_modrm = onebyte_has_modrm[*codep];
10710       codep++;
10711     }
10712
10713   if ((prefixes & PREFIX_REPZ))
10714     used_prefixes |= PREFIX_REPZ;
10715   if ((prefixes & PREFIX_REPNZ))
10716     used_prefixes |= PREFIX_REPNZ;
10717   if ((prefixes & PREFIX_LOCK))
10718     used_prefixes |= PREFIX_LOCK;
10719
10720   default_prefixes = 0;
10721   if (prefixes & PREFIX_ADDR)
10722     {
10723       sizeflag ^= AFLAG;
10724       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
10725         {
10726           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
10727             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
10728           else
10729             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
10730           default_prefixes |= PREFIX_ADDR;
10731         }
10732     }
10733
10734   if ((prefixes & PREFIX_DATA))
10735     {
10736       sizeflag ^= DFLAG;
10737       if (dp->op[2].bytemode == cond_jump_mode
10738           && dp->op[0].bytemode == v_mode
10739           && !intel_syntax)
10740         {
10741           if (sizeflag & DFLAG)
10742             all_prefixes[last_data_prefix] = DATA32_PREFIX;
10743           else
10744             all_prefixes[last_data_prefix] = DATA16_PREFIX;
10745           default_prefixes |= PREFIX_DATA;
10746         }
10747       else if (rex & REX_W)
10748         {
10749           /* REX_W will override PREFIX_DATA.  */
10750           default_prefixes |= PREFIX_DATA;
10751         }
10752     }
10753
10754   if (need_modrm)
10755     {
10756       FETCH_DATA (info, codep + 1);
10757       modrm.mod = (*codep >> 6) & 3;
10758       modrm.reg = (*codep >> 3) & 7;
10759       modrm.rm = *codep & 7;
10760     }
10761
10762    need_vex = 0;
10763    need_vex_reg = 0;
10764    vex_w_done = 0;
10765
10766   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
10767     {
10768       dofloat (sizeflag);
10769     }
10770   else
10771     {
10772       dp = get_valid_dis386 (dp, info);
10773       if (dp != NULL && putop (dp->name, sizeflag) == 0)
10774         {
10775           for (i = 0; i < MAX_OPERANDS; ++i)
10776             {
10777               obufp = op_out[i];
10778               op_ad = MAX_OPERANDS - 1 - i;
10779               if (dp->op[i].rtn)
10780                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10781             }
10782         }
10783     }
10784
10785   /* See if any prefixes were not used.  If so, print the first one
10786      separately.  If we don't do this, we'll wind up printing an
10787      instruction stream which does not precisely correspond to the
10788      bytes we are disassembling.  */
10789   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
10790     {
10791       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10792         if (all_prefixes[i])
10793           {
10794             const char *name;
10795             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
10796             if (name == NULL)
10797               name = INTERNAL_DISASSEMBLER_ERROR;
10798             (*info->fprintf_func) (info->stream, "%s", name);
10799             return 1;
10800           }
10801     }
10802
10803   /* Check if the REX prefix used.  */
10804   if (rex_ignored == 0 && (rex ^ rex_used) == 0)
10805     all_prefixes[last_rex_prefix] = 0;
10806
10807   /* Check if the SEG prefix used.  */
10808   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
10809                    | PREFIX_FS | PREFIX_GS)) != 0
10810       && (used_prefixes
10811           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
10812     all_prefixes[last_seg_prefix] = 0;
10813
10814   /* Check if the ADDR prefix used.  */
10815   if ((prefixes & PREFIX_ADDR) != 0
10816       && (used_prefixes & PREFIX_ADDR) != 0)
10817     all_prefixes[last_addr_prefix] = 0;
10818
10819   /* Check if the DATA prefix used.  */
10820   if ((prefixes & PREFIX_DATA) != 0
10821       && (used_prefixes & PREFIX_DATA) != 0)
10822     all_prefixes[last_data_prefix] = 0;
10823
10824   prefix_length = 0;
10825   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10826     if (all_prefixes[i])
10827       {
10828         const char *name;
10829         name = prefix_name (all_prefixes[i], sizeflag);
10830         if (name == NULL)
10831           abort ();
10832         prefix_length += strlen (name) + 1;
10833         (*info->fprintf_func) (info->stream, "%s ", name);
10834       }
10835
10836   /* Check maximum code length.  */
10837   if ((codep - start_codep) > MAX_CODE_LENGTH)
10838     {
10839       (*info->fprintf_func) (info->stream, "(bad)");
10840       return MAX_CODE_LENGTH;
10841     }
10842
10843   obufp = mnemonicendp;
10844   for (i = strlen (obuf) + prefix_length; i < 6; i++)
10845     oappend (" ");
10846   oappend (" ");
10847   (*info->fprintf_func) (info->stream, "%s", obuf);
10848
10849   /* The enter and bound instructions are printed with operands in the same
10850      order as the intel book; everything else is printed in reverse order.  */
10851   if (intel_syntax || two_source_ops)
10852     {
10853       bfd_vma riprel;
10854
10855       for (i = 0; i < MAX_OPERANDS; ++i)
10856         op_txt[i] = op_out[i];
10857
10858       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10859         {
10860           op_ad = op_index[i];
10861           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10862           op_index[MAX_OPERANDS - 1 - i] = op_ad;
10863           riprel = op_riprel[i];
10864           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10865           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10866         }
10867     }
10868   else
10869     {
10870       for (i = 0; i < MAX_OPERANDS; ++i)
10871         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10872     }
10873
10874   needcomma = 0;
10875   for (i = 0; i < MAX_OPERANDS; ++i)
10876     if (*op_txt[i])
10877       {
10878         if (needcomma)
10879           (*info->fprintf_func) (info->stream, ",");
10880         if (op_index[i] != -1 && !op_riprel[i])
10881           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
10882         else
10883           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10884         needcomma = 1;
10885       }
10886
10887   for (i = 0; i < MAX_OPERANDS; i++)
10888     if (op_index[i] != -1 && op_riprel[i])
10889       {
10890         (*info->fprintf_func) (info->stream, "        # ");
10891         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
10892                                                 + op_address[op_index[i]]), info);
10893         break;
10894       }
10895   return codep - priv.the_buffer;
10896 }
10897
10898 static const char *float_mem[] = {
10899   /* d8 */
10900   "fadd{s|}",
10901   "fmul{s|}",
10902   "fcom{s|}",
10903   "fcomp{s|}",
10904   "fsub{s|}",
10905   "fsubr{s|}",
10906   "fdiv{s|}",
10907   "fdivr{s|}",
10908   /* d9 */
10909   "fld{s|}",
10910   "(bad)",
10911   "fst{s|}",
10912   "fstp{s|}",
10913   "fldenvIC",
10914   "fldcw",
10915   "fNstenvIC",
10916   "fNstcw",
10917   /* da */
10918   "fiadd{l|}",
10919   "fimul{l|}",
10920   "ficom{l|}",
10921   "ficomp{l|}",
10922   "fisub{l|}",
10923   "fisubr{l|}",
10924   "fidiv{l|}",
10925   "fidivr{l|}",
10926   /* db */
10927   "fild{l|}",
10928   "fisttp{l|}",
10929   "fist{l|}",
10930   "fistp{l|}",
10931   "(bad)",
10932   "fld{t||t|}",
10933   "(bad)",
10934   "fstp{t||t|}",
10935   /* dc */
10936   "fadd{l|}",
10937   "fmul{l|}",
10938   "fcom{l|}",
10939   "fcomp{l|}",
10940   "fsub{l|}",
10941   "fsubr{l|}",
10942   "fdiv{l|}",
10943   "fdivr{l|}",
10944   /* dd */
10945   "fld{l|}",
10946   "fisttp{ll|}",
10947   "fst{l||}",
10948   "fstp{l|}",
10949   "frstorIC",
10950   "(bad)",
10951   "fNsaveIC",
10952   "fNstsw",
10953   /* de */
10954   "fiadd",
10955   "fimul",
10956   "ficom",
10957   "ficomp",
10958   "fisub",
10959   "fisubr",
10960   "fidiv",
10961   "fidivr",
10962   /* df */
10963   "fild",
10964   "fisttp",
10965   "fist",
10966   "fistp",
10967   "fbld",
10968   "fild{ll|}",
10969   "fbstp",
10970   "fistp{ll|}",
10971 };
10972
10973 static const unsigned char float_mem_mode[] = {
10974   /* d8 */
10975   d_mode,
10976   d_mode,
10977   d_mode,
10978   d_mode,
10979   d_mode,
10980   d_mode,
10981   d_mode,
10982   d_mode,
10983   /* d9 */
10984   d_mode,
10985   0,
10986   d_mode,
10987   d_mode,
10988   0,
10989   w_mode,
10990   0,
10991   w_mode,
10992   /* da */
10993   d_mode,
10994   d_mode,
10995   d_mode,
10996   d_mode,
10997   d_mode,
10998   d_mode,
10999   d_mode,
11000   d_mode,
11001   /* db */
11002   d_mode,
11003   d_mode,
11004   d_mode,
11005   d_mode,
11006   0,
11007   t_mode,
11008   0,
11009   t_mode,
11010   /* dc */
11011   q_mode,
11012   q_mode,
11013   q_mode,
11014   q_mode,
11015   q_mode,
11016   q_mode,
11017   q_mode,
11018   q_mode,
11019   /* dd */
11020   q_mode,
11021   q_mode,
11022   q_mode,
11023   q_mode,
11024   0,
11025   0,
11026   0,
11027   w_mode,
11028   /* de */
11029   w_mode,
11030   w_mode,
11031   w_mode,
11032   w_mode,
11033   w_mode,
11034   w_mode,
11035   w_mode,
11036   w_mode,
11037   /* df */
11038   w_mode,
11039   w_mode,
11040   w_mode,
11041   w_mode,
11042   t_mode,
11043   q_mode,
11044   t_mode,
11045   q_mode
11046 };
11047
11048 #define ST { OP_ST, 0 }
11049 #define STi { OP_STi, 0 }
11050
11051 #define FGRPd9_2 NULL, { { NULL, 0 } }
11052 #define FGRPd9_4 NULL, { { NULL, 1 } }
11053 #define FGRPd9_5 NULL, { { NULL, 2 } }
11054 #define FGRPd9_6 NULL, { { NULL, 3 } }
11055 #define FGRPd9_7 NULL, { { NULL, 4 } }
11056 #define FGRPda_5 NULL, { { NULL, 5 } }
11057 #define FGRPdb_4 NULL, { { NULL, 6 } }
11058 #define FGRPde_3 NULL, { { NULL, 7 } }
11059 #define FGRPdf_4 NULL, { { NULL, 8 } }
11060
11061 static const struct dis386 float_reg[][8] = {
11062   /* d8 */
11063   {
11064     { "fadd",   { ST, STi } },
11065     { "fmul",   { ST, STi } },
11066     { "fcom",   { STi } },
11067     { "fcomp",  { STi } },
11068     { "fsub",   { ST, STi } },
11069     { "fsubr",  { ST, STi } },
11070     { "fdiv",   { ST, STi } },
11071     { "fdivr",  { ST, STi } },
11072   },
11073   /* d9 */
11074   {
11075     { "fld",    { STi } },
11076     { "fxch",   { STi } },
11077     { FGRPd9_2 },
11078     { "(bad)",  { XX } },
11079     { FGRPd9_4 },
11080     { FGRPd9_5 },
11081     { FGRPd9_6 },
11082     { FGRPd9_7 },
11083   },
11084   /* da */
11085   {
11086     { "fcmovb", { ST, STi } },
11087     { "fcmove", { ST, STi } },
11088     { "fcmovbe",{ ST, STi } },
11089     { "fcmovu", { ST, STi } },
11090     { "(bad)",  { XX } },
11091     { FGRPda_5 },
11092     { "(bad)",  { XX } },
11093     { "(bad)",  { XX } },
11094   },
11095   /* db */
11096   {
11097     { "fcmovnb",{ ST, STi } },
11098     { "fcmovne",{ ST, STi } },
11099     { "fcmovnbe",{ ST, STi } },
11100     { "fcmovnu",{ ST, STi } },
11101     { FGRPdb_4 },
11102     { "fucomi", { ST, STi } },
11103     { "fcomi",  { ST, STi } },
11104     { "(bad)",  { XX } },
11105   },
11106   /* dc */
11107   {
11108     { "fadd",   { STi, ST } },
11109     { "fmul",   { STi, ST } },
11110     { "(bad)",  { XX } },
11111     { "(bad)",  { XX } },
11112     { "fsub!M", { STi, ST } },
11113     { "fsubM",  { STi, ST } },
11114     { "fdiv!M", { STi, ST } },
11115     { "fdivM",  { STi, ST } },
11116   },
11117   /* dd */
11118   {
11119     { "ffree",  { STi } },
11120     { "(bad)",  { XX } },
11121     { "fst",    { STi } },
11122     { "fstp",   { STi } },
11123     { "fucom",  { STi } },
11124     { "fucomp", { STi } },
11125     { "(bad)",  { XX } },
11126     { "(bad)",  { XX } },
11127   },
11128   /* de */
11129   {
11130     { "faddp",  { STi, ST } },
11131     { "fmulp",  { STi, ST } },
11132     { "(bad)",  { XX } },
11133     { FGRPde_3 },
11134     { "fsub!Mp", { STi, ST } },
11135     { "fsubMp", { STi, ST } },
11136     { "fdiv!Mp", { STi, ST } },
11137     { "fdivMp", { STi, ST } },
11138   },
11139   /* df */
11140   {
11141     { "ffreep", { STi } },
11142     { "(bad)",  { XX } },
11143     { "(bad)",  { XX } },
11144     { "(bad)",  { XX } },
11145     { FGRPdf_4 },
11146     { "fucomip", { ST, STi } },
11147     { "fcomip", { ST, STi } },
11148     { "(bad)",  { XX } },
11149   },
11150 };
11151
11152 static char *fgrps[][8] = {
11153   /* d9_2  0 */
11154   {
11155     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11156   },
11157
11158   /* d9_4  1 */
11159   {
11160     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11161   },
11162
11163   /* d9_5  2 */
11164   {
11165     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11166   },
11167
11168   /* d9_6  3 */
11169   {
11170     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11171   },
11172
11173   /* d9_7  4 */
11174   {
11175     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11176   },
11177
11178   /* da_5  5 */
11179   {
11180     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11181   },
11182
11183   /* db_4  6 */
11184   {
11185     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11186     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11187   },
11188
11189   /* de_3  7 */
11190   {
11191     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11192   },
11193
11194   /* df_4  8 */
11195   {
11196     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11197   },
11198 };
11199
11200 static void
11201 swap_operand (void)
11202 {
11203   mnemonicendp[0] = '.';
11204   mnemonicendp[1] = 's';
11205   mnemonicendp += 2;
11206 }
11207
11208 static void
11209 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
11210                int sizeflag ATTRIBUTE_UNUSED)
11211 {
11212   /* Skip mod/rm byte.  */
11213   MODRM_CHECK;
11214   codep++;
11215 }
11216
11217 static void
11218 dofloat (int sizeflag)
11219 {
11220   const struct dis386 *dp;
11221   unsigned char floatop;
11222
11223   floatop = codep[-1];
11224
11225   if (modrm.mod != 3)
11226     {
11227       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
11228
11229       putop (float_mem[fp_indx], sizeflag);
11230       obufp = op_out[0];
11231       op_ad = 2;
11232       OP_E (float_mem_mode[fp_indx], sizeflag);
11233       return;
11234     }
11235   /* Skip mod/rm byte.  */
11236   MODRM_CHECK;
11237   codep++;
11238
11239   dp = &float_reg[floatop - 0xd8][modrm.reg];
11240   if (dp->name == NULL)
11241     {
11242       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
11243
11244       /* Instruction fnstsw is only one with strange arg.  */
11245       if (floatop == 0xdf && codep[-1] == 0xe0)
11246         strcpy (op_out[0], names16[0]);
11247     }
11248   else
11249     {
11250       putop (dp->name, sizeflag);
11251
11252       obufp = op_out[0];
11253       op_ad = 2;
11254       if (dp->op[0].rtn)
11255         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
11256
11257       obufp = op_out[1];
11258       op_ad = 1;
11259       if (dp->op[1].rtn)
11260         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
11261     }
11262 }
11263
11264 static void
11265 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11266 {
11267   oappend ("%st" + intel_syntax);
11268 }
11269
11270 static void
11271 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11272 {
11273   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
11274   oappend (scratchbuf + intel_syntax);
11275 }
11276
11277 /* Capital letters in template are macros.  */
11278 static int
11279 putop (const char *in_template, int sizeflag)
11280 {
11281   const char *p;
11282   int alt = 0;
11283   int cond = 1;
11284   unsigned int l = 0, len = 1;
11285   char last[4];
11286
11287 #define SAVE_LAST(c)                    \
11288   if (l < len && l < sizeof (last))     \
11289     last[l++] = c;                      \
11290   else                                  \
11291     abort ();
11292
11293   for (p = in_template; *p; p++)
11294     {
11295       switch (*p)
11296         {
11297         default:
11298           *obufp++ = *p;
11299           break;
11300         case '%':
11301           len++;
11302           break;
11303         case '!':
11304           cond = 0;
11305           break;
11306         case '{':
11307           alt = 0;
11308           if (intel_syntax)
11309             {
11310               while (*++p != '|')
11311                 if (*p == '}' || *p == '\0')
11312                   abort ();
11313             }
11314           /* Fall through.  */
11315         case 'I':
11316           alt = 1;
11317           continue;
11318         case '|':
11319           while (*++p != '}')
11320             {
11321               if (*p == '\0')
11322                 abort ();
11323             }
11324           break;
11325         case '}':
11326           break;
11327         case 'A':
11328           if (intel_syntax)
11329             break;
11330           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11331             *obufp++ = 'b';
11332           break;
11333         case 'B':
11334           if (l == 0 && len == 1)
11335             {
11336 case_B:
11337               if (intel_syntax)
11338                 break;
11339               if (sizeflag & SUFFIX_ALWAYS)
11340                 *obufp++ = 'b';
11341             }
11342           else
11343             {
11344               if (l != 1
11345                   || len != 2
11346                   || last[0] != 'L')
11347                 {
11348                   SAVE_LAST (*p);
11349                   break;
11350                 }
11351
11352               if (address_mode == mode_64bit
11353                   && !(prefixes & PREFIX_ADDR))
11354                 {
11355                   *obufp++ = 'a';
11356                   *obufp++ = 'b';
11357                   *obufp++ = 's';
11358                 }
11359
11360               goto case_B;
11361             }
11362           break;
11363         case 'C':
11364           if (intel_syntax && !alt)
11365             break;
11366           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11367             {
11368               if (sizeflag & DFLAG)
11369                 *obufp++ = intel_syntax ? 'd' : 'l';
11370               else
11371                 *obufp++ = intel_syntax ? 'w' : 's';
11372               used_prefixes |= (prefixes & PREFIX_DATA);
11373             }
11374           break;
11375         case 'D':
11376           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11377             break;
11378           USED_REX (REX_W);
11379           if (modrm.mod == 3)
11380             {
11381               if (rex & REX_W)
11382                 *obufp++ = 'q';
11383               else
11384                 {
11385                   if (sizeflag & DFLAG)
11386                     *obufp++ = intel_syntax ? 'd' : 'l';
11387                   else
11388                     *obufp++ = 'w';
11389                   used_prefixes |= (prefixes & PREFIX_DATA);
11390                 }
11391             }
11392           else
11393             *obufp++ = 'w';
11394           break;
11395         case 'E':               /* For jcxz/jecxz */
11396           if (address_mode == mode_64bit)
11397             {
11398               if (sizeflag & AFLAG)
11399                 *obufp++ = 'r';
11400               else
11401                 *obufp++ = 'e';
11402             }
11403           else
11404             if (sizeflag & AFLAG)
11405               *obufp++ = 'e';
11406           used_prefixes |= (prefixes & PREFIX_ADDR);
11407           break;
11408         case 'F':
11409           if (intel_syntax)
11410             break;
11411           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
11412             {
11413               if (sizeflag & AFLAG)
11414                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
11415               else
11416                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
11417               used_prefixes |= (prefixes & PREFIX_ADDR);
11418             }
11419           break;
11420         case 'G':
11421           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
11422             break;
11423           if ((rex & REX_W) || (sizeflag & DFLAG))
11424             *obufp++ = 'l';
11425           else
11426             *obufp++ = 'w';
11427           if (!(rex & REX_W))
11428             used_prefixes |= (prefixes & PREFIX_DATA);
11429           break;
11430         case 'H':
11431           if (intel_syntax)
11432             break;
11433           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
11434               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
11435             {
11436               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
11437               *obufp++ = ',';
11438               *obufp++ = 'p';
11439               if (prefixes & PREFIX_DS)
11440                 *obufp++ = 't';
11441               else
11442                 *obufp++ = 'n';
11443             }
11444           break;
11445         case 'J':
11446           if (intel_syntax)
11447             break;
11448           *obufp++ = 'l';
11449           break;
11450         case 'K':
11451           USED_REX (REX_W);
11452           if (rex & REX_W)
11453             *obufp++ = 'q';
11454           else
11455             *obufp++ = 'd';
11456           break;
11457         case 'Z':
11458           if (intel_syntax)
11459             break;
11460           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
11461             {
11462               *obufp++ = 'q';
11463               break;
11464             }
11465           /* Fall through.  */
11466           goto case_L;
11467         case 'L':
11468           if (l != 0 || len != 1)
11469             {
11470               SAVE_LAST (*p);
11471               break;
11472             }
11473 case_L:
11474           if (intel_syntax)
11475             break;
11476           if (sizeflag & SUFFIX_ALWAYS)
11477             *obufp++ = 'l';
11478           break;
11479         case 'M':
11480           if (intel_mnemonic != cond)
11481             *obufp++ = 'r';
11482           break;
11483         case 'N':
11484           if ((prefixes & PREFIX_FWAIT) == 0)
11485             *obufp++ = 'n';
11486           else
11487             used_prefixes |= PREFIX_FWAIT;
11488           break;
11489         case 'O':
11490           USED_REX (REX_W);
11491           if (rex & REX_W)
11492             *obufp++ = 'o';
11493           else if (intel_syntax && (sizeflag & DFLAG))
11494             *obufp++ = 'q';
11495           else
11496             *obufp++ = 'd';
11497           if (!(rex & REX_W))
11498             used_prefixes |= (prefixes & PREFIX_DATA);
11499           break;
11500         case 'T':
11501           if (intel_syntax)
11502             break;
11503           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11504             {
11505               *obufp++ = 'q';
11506               break;
11507             }
11508           /* Fall through.  */
11509         case 'P':
11510           if (intel_syntax)
11511             break;
11512           if ((prefixes & PREFIX_DATA)
11513               || (rex & REX_W)
11514               || (sizeflag & SUFFIX_ALWAYS))
11515             {
11516               USED_REX (REX_W);
11517               if (rex & REX_W)
11518                 *obufp++ = 'q';
11519               else
11520                 {
11521                    if (sizeflag & DFLAG)
11522                       *obufp++ = 'l';
11523                    else
11524                      *obufp++ = 'w';
11525                    used_prefixes |= (prefixes & PREFIX_DATA);
11526                 }
11527             }
11528           break;
11529         case 'U':
11530           if (intel_syntax)
11531             break;
11532           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11533             {
11534               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11535                 *obufp++ = 'q';
11536               break;
11537             }
11538           /* Fall through.  */
11539           goto case_Q;
11540         case 'Q':
11541           if (l == 0 && len == 1)
11542             {
11543 case_Q:
11544               if (intel_syntax && !alt)
11545                 break;
11546               USED_REX (REX_W);
11547               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11548                 {
11549                   if (rex & REX_W)
11550                     *obufp++ = 'q';
11551                   else
11552                     {
11553                       if (sizeflag & DFLAG)
11554                         *obufp++ = intel_syntax ? 'd' : 'l';
11555                       else
11556                         *obufp++ = 'w';
11557                       used_prefixes |= (prefixes & PREFIX_DATA);
11558                     }
11559                 }
11560             }
11561           else
11562             {
11563               if (l != 1 || len != 2 || last[0] != 'L')
11564                 {
11565                   SAVE_LAST (*p);
11566                   break;
11567                 }
11568               if (intel_syntax
11569                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11570                 break;
11571               if ((rex & REX_W))
11572                 {
11573                   USED_REX (REX_W);
11574                   *obufp++ = 'q';
11575                 }
11576               else
11577                 *obufp++ = 'l';
11578             }
11579           break;
11580         case 'R':
11581           USED_REX (REX_W);
11582           if (rex & REX_W)
11583             *obufp++ = 'q';
11584           else if (sizeflag & DFLAG)
11585             {
11586               if (intel_syntax)
11587                   *obufp++ = 'd';
11588               else
11589                   *obufp++ = 'l';
11590             }
11591           else
11592             *obufp++ = 'w';
11593           if (intel_syntax && !p[1]
11594               && ((rex & REX_W) || (sizeflag & DFLAG)))
11595             *obufp++ = 'e';
11596           if (!(rex & REX_W))
11597             used_prefixes |= (prefixes & PREFIX_DATA);
11598           break;
11599         case 'V':
11600           if (l == 0 && len == 1)
11601             {
11602               if (intel_syntax)
11603                 break;
11604               if (address_mode == mode_64bit && (sizeflag & DFLAG))
11605                 {
11606                   if (sizeflag & SUFFIX_ALWAYS)
11607                     *obufp++ = 'q';
11608                   break;
11609                 }
11610             }
11611           else
11612             {
11613               if (l != 1
11614                   || len != 2
11615                   || last[0] != 'L')
11616                 {
11617                   SAVE_LAST (*p);
11618                   break;
11619                 }
11620
11621               if (rex & REX_W)
11622                 {
11623                   *obufp++ = 'a';
11624                   *obufp++ = 'b';
11625                   *obufp++ = 's';
11626                 }
11627             }
11628           /* Fall through.  */
11629           goto case_S;
11630         case 'S':
11631           if (l == 0 && len == 1)
11632             {
11633 case_S:
11634               if (intel_syntax)
11635                 break;
11636               if (sizeflag & SUFFIX_ALWAYS)
11637                 {
11638                   if (rex & REX_W)
11639                     *obufp++ = 'q';
11640                   else
11641                     {
11642                       if (sizeflag & DFLAG)
11643                         *obufp++ = 'l';
11644                       else
11645                         *obufp++ = 'w';
11646                       used_prefixes |= (prefixes & PREFIX_DATA);
11647                     }
11648                 }
11649             }
11650           else
11651             {
11652               if (l != 1
11653                   || len != 2
11654                   || last[0] != 'L')
11655                 {
11656                   SAVE_LAST (*p);
11657                   break;
11658                 }
11659
11660               if (address_mode == mode_64bit
11661                   && !(prefixes & PREFIX_ADDR))
11662                 {
11663                   *obufp++ = 'a';
11664                   *obufp++ = 'b';
11665                   *obufp++ = 's';
11666                 }
11667
11668               goto case_S;
11669             }
11670           break;
11671         case 'X':
11672           if (l != 0 || len != 1)
11673             {
11674               SAVE_LAST (*p);
11675               break;
11676             }
11677           if (need_vex && vex.prefix)
11678             {
11679               if (vex.prefix == DATA_PREFIX_OPCODE)
11680                 *obufp++ = 'd';
11681               else
11682                 *obufp++ = 's';
11683             }
11684           else
11685             {
11686               if (prefixes & PREFIX_DATA)
11687                 *obufp++ = 'd';
11688               else
11689                 *obufp++ = 's';
11690               used_prefixes |= (prefixes & PREFIX_DATA);
11691             }
11692           break;
11693         case 'Y':
11694           if (l == 0 && len == 1)
11695             {
11696               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11697                 break;
11698               if (rex & REX_W)
11699                 {
11700                   USED_REX (REX_W);
11701                   *obufp++ = 'q';
11702                 }
11703               break;
11704             }
11705           else
11706             {
11707               if (l != 1 || len != 2 || last[0] != 'X')
11708                 {
11709                   SAVE_LAST (*p);
11710                   break;
11711                 }
11712               if (!need_vex)
11713                 abort ();
11714               if (intel_syntax
11715                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11716                 break;
11717               switch (vex.length)
11718                 {
11719                 case 128:
11720                   *obufp++ = 'x';
11721                   break;
11722                 case 256:
11723                   *obufp++ = 'y';
11724                   break;
11725                 default:
11726                   abort ();
11727                 }
11728             }
11729           break;
11730         case 'W':
11731           if (l == 0 && len == 1)
11732             {
11733               /* operand size flag for cwtl, cbtw */
11734               USED_REX (REX_W);
11735               if (rex & REX_W)
11736                 {
11737                   if (intel_syntax)
11738                     *obufp++ = 'd';
11739                   else
11740                     *obufp++ = 'l';
11741                 }
11742               else if (sizeflag & DFLAG)
11743                 *obufp++ = 'w';
11744               else
11745                 *obufp++ = 'b';
11746               if (!(rex & REX_W))
11747                 used_prefixes |= (prefixes & PREFIX_DATA);
11748             }
11749           else
11750             {
11751               if (l != 1 || len != 2 || last[0] != 'X')
11752                 {
11753                   SAVE_LAST (*p);
11754                   break;
11755                 }
11756               if (!need_vex)
11757                 abort ();
11758               *obufp++ = vex.w ? 'd': 's';
11759             }
11760           break;
11761         }
11762       alt = 0;
11763     }
11764   *obufp = 0;
11765   mnemonicendp = obufp;
11766   return 0;
11767 }
11768
11769 static void
11770 oappend (const char *s)
11771 {
11772   obufp = stpcpy (obufp, s);
11773 }
11774
11775 static void
11776 append_seg (void)
11777 {
11778   if (prefixes & PREFIX_CS)
11779     {
11780       used_prefixes |= PREFIX_CS;
11781       oappend ("%cs:" + intel_syntax);
11782     }
11783   if (prefixes & PREFIX_DS)
11784     {
11785       used_prefixes |= PREFIX_DS;
11786       oappend ("%ds:" + intel_syntax);
11787     }
11788   if (prefixes & PREFIX_SS)
11789     {
11790       used_prefixes |= PREFIX_SS;
11791       oappend ("%ss:" + intel_syntax);
11792     }
11793   if (prefixes & PREFIX_ES)
11794     {
11795       used_prefixes |= PREFIX_ES;
11796       oappend ("%es:" + intel_syntax);
11797     }
11798   if (prefixes & PREFIX_FS)
11799     {
11800       used_prefixes |= PREFIX_FS;
11801       oappend ("%fs:" + intel_syntax);
11802     }
11803   if (prefixes & PREFIX_GS)
11804     {
11805       used_prefixes |= PREFIX_GS;
11806       oappend ("%gs:" + intel_syntax);
11807     }
11808 }
11809
11810 static void
11811 OP_indirE (int bytemode, int sizeflag)
11812 {
11813   if (!intel_syntax)
11814     oappend ("*");
11815   OP_E (bytemode, sizeflag);
11816 }
11817
11818 static void
11819 print_operand_value (char *buf, int hex, bfd_vma disp)
11820 {
11821   if (address_mode == mode_64bit)
11822     {
11823       if (hex)
11824         {
11825           char tmp[30];
11826           int i;
11827           buf[0] = '0';
11828           buf[1] = 'x';
11829           sprintf_vma (tmp, disp);
11830           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11831           strcpy (buf + 2, tmp + i);
11832         }
11833       else
11834         {
11835           bfd_signed_vma v = disp;
11836           char tmp[30];
11837           int i;
11838           if (v < 0)
11839             {
11840               *(buf++) = '-';
11841               v = -disp;
11842               /* Check for possible overflow on 0x8000000000000000.  */
11843               if (v < 0)
11844                 {
11845                   strcpy (buf, "9223372036854775808");
11846                   return;
11847                 }
11848             }
11849           if (!v)
11850             {
11851               strcpy (buf, "0");
11852               return;
11853             }
11854
11855           i = 0;
11856           tmp[29] = 0;
11857           while (v)
11858             {
11859               tmp[28 - i] = (v % 10) + '0';
11860               v /= 10;
11861               i++;
11862             }
11863           strcpy (buf, tmp + 29 - i);
11864         }
11865     }
11866   else
11867     {
11868       if (hex)
11869         sprintf (buf, "0x%x", (unsigned int) disp);
11870       else
11871         sprintf (buf, "%d", (int) disp);
11872     }
11873 }
11874
11875 /* Put DISP in BUF as signed hex number.  */
11876
11877 static void
11878 print_displacement (char *buf, bfd_vma disp)
11879 {
11880   bfd_signed_vma val = disp;
11881   char tmp[30];
11882   int i, j = 0;
11883
11884   if (val < 0)
11885     {
11886       buf[j++] = '-';
11887       val = -disp;
11888
11889       /* Check for possible overflow.  */
11890       if (val < 0)
11891         {
11892           switch (address_mode)
11893             {
11894             case mode_64bit:
11895               strcpy (buf + j, "0x8000000000000000");
11896               break;
11897             case mode_32bit:
11898               strcpy (buf + j, "0x80000000");
11899               break;
11900             case mode_16bit:
11901               strcpy (buf + j, "0x8000");
11902               break;
11903             }
11904           return;
11905         }
11906     }
11907
11908   buf[j++] = '0';
11909   buf[j++] = 'x';
11910
11911   sprintf_vma (tmp, (bfd_vma) val);
11912   for (i = 0; tmp[i] == '0'; i++)
11913     continue;
11914   if (tmp[i] == '\0')
11915     i--;
11916   strcpy (buf + j, tmp + i);
11917 }
11918
11919 static void
11920 intel_operand_size (int bytemode, int sizeflag)
11921 {
11922   switch (bytemode)
11923     {
11924     case b_mode:
11925     case b_swap_mode:
11926     case dqb_mode:
11927       oappend ("BYTE PTR ");
11928       break;
11929     case w_mode:
11930     case dqw_mode:
11931       oappend ("WORD PTR ");
11932       break;
11933     case stack_v_mode:
11934       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11935         {
11936           oappend ("QWORD PTR ");
11937           break;
11938         }
11939       /* FALLTHRU */
11940     case v_mode:
11941     case v_swap_mode:
11942     case dq_mode:
11943       USED_REX (REX_W);
11944       if (rex & REX_W)
11945         oappend ("QWORD PTR ");
11946       else
11947         {
11948           if ((sizeflag & DFLAG) || bytemode == dq_mode)
11949             oappend ("DWORD PTR ");
11950           else
11951             oappend ("WORD PTR ");
11952           used_prefixes |= (prefixes & PREFIX_DATA);
11953         }
11954       break;
11955     case z_mode:
11956       if ((rex & REX_W) || (sizeflag & DFLAG))
11957         *obufp++ = 'D';
11958       oappend ("WORD PTR ");
11959       if (!(rex & REX_W))
11960         used_prefixes |= (prefixes & PREFIX_DATA);
11961       break;
11962     case a_mode:
11963       if (sizeflag & DFLAG)
11964         oappend ("QWORD PTR ");
11965       else
11966         oappend ("DWORD PTR ");
11967       used_prefixes |= (prefixes & PREFIX_DATA);
11968       break;
11969     case d_mode:
11970     case d_swap_mode:
11971     case dqd_mode:
11972       oappend ("DWORD PTR ");
11973       break;
11974     case q_mode:
11975     case q_swap_mode:
11976       oappend ("QWORD PTR ");
11977       break;
11978     case m_mode:
11979       if (address_mode == mode_64bit)
11980         oappend ("QWORD PTR ");
11981       else
11982         oappend ("DWORD PTR ");
11983       break;
11984     case f_mode:
11985       if (sizeflag & DFLAG)
11986         oappend ("FWORD PTR ");
11987       else
11988         oappend ("DWORD PTR ");
11989       used_prefixes |= (prefixes & PREFIX_DATA);
11990       break;
11991     case t_mode:
11992       oappend ("TBYTE PTR ");
11993       break;
11994     case x_mode:
11995     case x_swap_mode:
11996       if (need_vex)
11997         {
11998           switch (vex.length)
11999             {
12000             case 128:
12001               oappend ("XMMWORD PTR ");
12002               break;
12003             case 256:
12004               oappend ("YMMWORD PTR ");
12005               break;
12006             default:
12007               abort ();
12008             }
12009         }
12010       else
12011         oappend ("XMMWORD PTR ");
12012       break;
12013     case xmm_mode:
12014       oappend ("XMMWORD PTR ");
12015       break;
12016     case xmmq_mode:
12017       if (!need_vex)
12018         abort ();
12019
12020       switch (vex.length)
12021         {
12022         case 128:
12023           oappend ("QWORD PTR ");
12024           break;
12025         case 256:
12026           oappend ("XMMWORD PTR ");
12027           break;
12028         default:
12029           abort ();
12030         }
12031       break;
12032     case ymmq_mode:
12033       if (!need_vex)
12034         abort ();
12035
12036       switch (vex.length)
12037         {
12038         case 128:
12039           oappend ("QWORD PTR ");
12040           break;
12041         case 256:
12042           oappend ("YMMWORD PTR ");
12043           break;
12044         default:
12045           abort ();
12046         }
12047       break;
12048     case o_mode:
12049       oappend ("OWORD PTR ");
12050       break;
12051     case vex_w_dq_mode:
12052       if (!need_vex)
12053         abort ();
12054
12055       if (vex.w)
12056         oappend ("QWORD PTR ");
12057       else
12058         oappend ("DWORD PTR ");
12059       break;
12060     default:
12061       break;
12062     }
12063 }
12064
12065 static void
12066 OP_E_register (int bytemode, int sizeflag)
12067 {
12068   int reg = modrm.rm;
12069   const char **names;
12070
12071   USED_REX (REX_B);
12072   if ((rex & REX_B))
12073     reg += 8;
12074
12075   if ((sizeflag & SUFFIX_ALWAYS)
12076       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
12077     swap_operand ();
12078
12079   switch (bytemode)
12080     {
12081     case b_mode:
12082     case b_swap_mode:
12083       USED_REX (0);
12084       if (rex)
12085         names = names8rex;
12086       else
12087         names = names8;
12088       break;
12089     case w_mode:
12090       names = names16;
12091       break;
12092     case d_mode:
12093       names = names32;
12094       break;
12095     case q_mode:
12096       names = names64;
12097       break;
12098     case m_mode:
12099       names = address_mode == mode_64bit ? names64 : names32;
12100       break;
12101     case stack_v_mode:
12102       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12103         {
12104           names = names64;
12105           break;
12106         }
12107       bytemode = v_mode;
12108       /* FALLTHRU */
12109     case v_mode:
12110     case v_swap_mode:
12111     case dq_mode:
12112     case dqb_mode:
12113     case dqd_mode:
12114     case dqw_mode:
12115       USED_REX (REX_W);
12116       if (rex & REX_W)
12117         names = names64;
12118       else
12119         {
12120           if ((sizeflag & DFLAG)
12121               || (bytemode != v_mode
12122                   && bytemode != v_swap_mode))
12123             names = names32;
12124           else
12125             names = names16;
12126           used_prefixes |= (prefixes & PREFIX_DATA);
12127         }
12128       break;
12129     case 0:
12130       return;
12131     default:
12132       oappend (INTERNAL_DISASSEMBLER_ERROR);
12133       return;
12134     }
12135   oappend (names[reg]);
12136 }
12137
12138 static void
12139 OP_E_memory (int bytemode, int sizeflag)
12140 {
12141   bfd_vma disp = 0;
12142   int add = (rex & REX_B) ? 8 : 0;
12143   int riprel = 0;
12144
12145   USED_REX (REX_B);
12146   if (intel_syntax)
12147     intel_operand_size (bytemode, sizeflag);
12148   append_seg ();
12149
12150   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12151     {
12152       /* 32/64 bit address mode */
12153       int havedisp;
12154       int havesib;
12155       int havebase;
12156       int haveindex;
12157       int needindex;
12158       int base, rbase;
12159       int index = 0;
12160       int scale = 0;
12161
12162       havesib = 0;
12163       havebase = 1;
12164       haveindex = 0;
12165       base = modrm.rm;
12166
12167       if (base == 4)
12168         {
12169           havesib = 1;
12170           FETCH_DATA (the_info, codep + 1);
12171           index = (*codep >> 3) & 7;
12172           scale = (*codep >> 6) & 3;
12173           base = *codep & 7;
12174           USED_REX (REX_X);
12175           if (rex & REX_X)
12176             index += 8;
12177           haveindex = index != 4;
12178           codep++;
12179         }
12180       rbase = base + add;
12181
12182       switch (modrm.mod)
12183         {
12184         case 0:
12185           if (base == 5)
12186             {
12187               havebase = 0;
12188               if (address_mode == mode_64bit && !havesib)
12189                 riprel = 1;
12190               disp = get32s ();
12191             }
12192           break;
12193         case 1:
12194           FETCH_DATA (the_info, codep + 1);
12195           disp = *codep++;
12196           if ((disp & 0x80) != 0)
12197             disp -= 0x100;
12198           break;
12199         case 2:
12200           disp = get32s ();
12201           break;
12202         }
12203
12204       /* In 32bit mode, we need index register to tell [offset] from
12205          [eiz*1 + offset].  */
12206       needindex = (havesib
12207                    && !havebase
12208                    && !haveindex
12209                    && address_mode == mode_32bit);
12210       havedisp = (havebase
12211                   || needindex
12212                   || (havesib && (haveindex || scale != 0)));
12213
12214       if (!intel_syntax)
12215         if (modrm.mod != 0 || base == 5)
12216           {
12217             if (havedisp || riprel)
12218               print_displacement (scratchbuf, disp);
12219             else
12220               print_operand_value (scratchbuf, 1, disp);
12221             oappend (scratchbuf);
12222             if (riprel)
12223               {
12224                 set_op (disp, 1);
12225                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
12226               }
12227           }
12228
12229       if (havebase || haveindex || riprel)
12230         used_prefixes |= PREFIX_ADDR;
12231
12232       if (havedisp || (intel_syntax && riprel))
12233         {
12234           *obufp++ = open_char;
12235           if (intel_syntax && riprel)
12236             {
12237               set_op (disp, 1);
12238               oappend (sizeflag & AFLAG ? "rip" : "eip");
12239             }
12240           *obufp = '\0';
12241           if (havebase)
12242             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
12243                      ? names64[rbase] : names32[rbase]);
12244           if (havesib)
12245             {
12246               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
12247                  print index to tell base + index from base.  */
12248               if (scale != 0
12249                   || needindex
12250                   || haveindex
12251                   || (havebase && base != ESP_REG_NUM))
12252                 {
12253                   if (!intel_syntax || havebase)
12254                     {
12255                       *obufp++ = separator_char;
12256                       *obufp = '\0';
12257                     }
12258                   if (haveindex)
12259                     oappend (address_mode == mode_64bit
12260                              && (sizeflag & AFLAG)
12261                              ? names64[index] : names32[index]);
12262                   else
12263                     oappend (address_mode == mode_64bit
12264                              && (sizeflag & AFLAG)
12265                              ? index64 : index32);
12266
12267                   *obufp++ = scale_char;
12268                   *obufp = '\0';
12269                   sprintf (scratchbuf, "%d", 1 << scale);
12270                   oappend (scratchbuf);
12271                 }
12272             }
12273           if (intel_syntax
12274               && (disp || modrm.mod != 0 || base == 5))
12275             {
12276               if (!havedisp || (bfd_signed_vma) disp >= 0)
12277                 {
12278                   *obufp++ = '+';
12279                   *obufp = '\0';
12280                 }
12281               else if (modrm.mod != 1 && disp != -disp)
12282                 {
12283                   *obufp++ = '-';
12284                   *obufp = '\0';
12285                   disp = - (bfd_signed_vma) disp;
12286                 }
12287
12288               if (havedisp)
12289                 print_displacement (scratchbuf, disp);
12290               else
12291                 print_operand_value (scratchbuf, 1, disp);
12292               oappend (scratchbuf);
12293             }
12294
12295           *obufp++ = close_char;
12296           *obufp = '\0';
12297         }
12298       else if (intel_syntax)
12299         {
12300           if (modrm.mod != 0 || base == 5)
12301             {
12302               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12303                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
12304                 ;
12305               else
12306                 {
12307                   oappend (names_seg[ds_reg - es_reg]);
12308                   oappend (":");
12309                 }
12310               print_operand_value (scratchbuf, 1, disp);
12311               oappend (scratchbuf);
12312             }
12313         }
12314     }
12315   else
12316     {
12317       /* 16 bit address mode */
12318       used_prefixes |= prefixes & PREFIX_ADDR;
12319       switch (modrm.mod)
12320         {
12321         case 0:
12322           if (modrm.rm == 6)
12323             {
12324               disp = get16 ();
12325               if ((disp & 0x8000) != 0)
12326                 disp -= 0x10000;
12327             }
12328           break;
12329         case 1:
12330           FETCH_DATA (the_info, codep + 1);
12331           disp = *codep++;
12332           if ((disp & 0x80) != 0)
12333             disp -= 0x100;
12334           break;
12335         case 2:
12336           disp = get16 ();
12337           if ((disp & 0x8000) != 0)
12338             disp -= 0x10000;
12339           break;
12340         }
12341
12342       if (!intel_syntax)
12343         if (modrm.mod != 0 || modrm.rm == 6)
12344           {
12345             print_displacement (scratchbuf, disp);
12346             oappend (scratchbuf);
12347           }
12348
12349       if (modrm.mod != 0 || modrm.rm != 6)
12350         {
12351           *obufp++ = open_char;
12352           *obufp = '\0';
12353           oappend (index16[modrm.rm]);
12354           if (intel_syntax
12355               && (disp || modrm.mod != 0 || modrm.rm == 6))
12356             {
12357               if ((bfd_signed_vma) disp >= 0)
12358                 {
12359                   *obufp++ = '+';
12360                   *obufp = '\0';
12361                 }
12362               else if (modrm.mod != 1)
12363                 {
12364                   *obufp++ = '-';
12365                   *obufp = '\0';
12366                   disp = - (bfd_signed_vma) disp;
12367                 }
12368
12369               print_displacement (scratchbuf, disp);
12370               oappend (scratchbuf);
12371             }
12372
12373           *obufp++ = close_char;
12374           *obufp = '\0';
12375         }
12376       else if (intel_syntax)
12377         {
12378           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12379                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
12380             ;
12381           else
12382             {
12383               oappend (names_seg[ds_reg - es_reg]);
12384               oappend (":");
12385             }
12386           print_operand_value (scratchbuf, 1, disp & 0xffff);
12387           oappend (scratchbuf);
12388         }
12389     }
12390 }
12391
12392 static void
12393 OP_E (int bytemode, int sizeflag)
12394 {
12395   /* Skip mod/rm byte.  */
12396   MODRM_CHECK;
12397   codep++;
12398
12399   if (modrm.mod == 3)
12400     OP_E_register (bytemode, sizeflag);
12401   else
12402     OP_E_memory (bytemode, sizeflag);
12403 }
12404
12405 static void
12406 OP_G (int bytemode, int sizeflag)
12407 {
12408   int add = 0;
12409   USED_REX (REX_R);
12410   if (rex & REX_R)
12411     add += 8;
12412   switch (bytemode)
12413     {
12414     case b_mode:
12415       USED_REX (0);
12416       if (rex)
12417         oappend (names8rex[modrm.reg + add]);
12418       else
12419         oappend (names8[modrm.reg + add]);
12420       break;
12421     case w_mode:
12422       oappend (names16[modrm.reg + add]);
12423       break;
12424     case d_mode:
12425       oappend (names32[modrm.reg + add]);
12426       break;
12427     case q_mode:
12428       oappend (names64[modrm.reg + add]);
12429       break;
12430     case v_mode:
12431     case dq_mode:
12432     case dqb_mode:
12433     case dqd_mode:
12434     case dqw_mode:
12435       USED_REX (REX_W);
12436       if (rex & REX_W)
12437         oappend (names64[modrm.reg + add]);
12438       else
12439         {
12440           if ((sizeflag & DFLAG) || bytemode != v_mode)
12441             oappend (names32[modrm.reg + add]);
12442           else
12443             oappend (names16[modrm.reg + add]);
12444           used_prefixes |= (prefixes & PREFIX_DATA);
12445         }
12446       break;
12447     case m_mode:
12448       if (address_mode == mode_64bit)
12449         oappend (names64[modrm.reg + add]);
12450       else
12451         oappend (names32[modrm.reg + add]);
12452       break;
12453     default:
12454       oappend (INTERNAL_DISASSEMBLER_ERROR);
12455       break;
12456     }
12457 }
12458
12459 static bfd_vma
12460 get64 (void)
12461 {
12462   bfd_vma x;
12463 #ifdef BFD64
12464   unsigned int a;
12465   unsigned int b;
12466
12467   FETCH_DATA (the_info, codep + 8);
12468   a = *codep++ & 0xff;
12469   a |= (*codep++ & 0xff) << 8;
12470   a |= (*codep++ & 0xff) << 16;
12471   a |= (*codep++ & 0xff) << 24;
12472   b = *codep++ & 0xff;
12473   b |= (*codep++ & 0xff) << 8;
12474   b |= (*codep++ & 0xff) << 16;
12475   b |= (*codep++ & 0xff) << 24;
12476   x = a + ((bfd_vma) b << 32);
12477 #else
12478   abort ();
12479   x = 0;
12480 #endif
12481   return x;
12482 }
12483
12484 static bfd_signed_vma
12485 get32 (void)
12486 {
12487   bfd_signed_vma x = 0;
12488
12489   FETCH_DATA (the_info, codep + 4);
12490   x = *codep++ & (bfd_signed_vma) 0xff;
12491   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12492   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12493   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12494   return x;
12495 }
12496
12497 static bfd_signed_vma
12498 get32s (void)
12499 {
12500   bfd_signed_vma x = 0;
12501
12502   FETCH_DATA (the_info, codep + 4);
12503   x = *codep++ & (bfd_signed_vma) 0xff;
12504   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12505   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12506   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12507
12508   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
12509
12510   return x;
12511 }
12512
12513 static int
12514 get16 (void)
12515 {
12516   int x = 0;
12517
12518   FETCH_DATA (the_info, codep + 2);
12519   x = *codep++ & 0xff;
12520   x |= (*codep++ & 0xff) << 8;
12521   return x;
12522 }
12523
12524 static void
12525 set_op (bfd_vma op, int riprel)
12526 {
12527   op_index[op_ad] = op_ad;
12528   if (address_mode == mode_64bit)
12529     {
12530       op_address[op_ad] = op;
12531       op_riprel[op_ad] = riprel;
12532     }
12533   else
12534     {
12535       /* Mask to get a 32-bit address.  */
12536       op_address[op_ad] = op & 0xffffffff;
12537       op_riprel[op_ad] = riprel & 0xffffffff;
12538     }
12539 }
12540
12541 static void
12542 OP_REG (int code, int sizeflag)
12543 {
12544   const char *s;
12545   int add;
12546   USED_REX (REX_B);
12547   if (rex & REX_B)
12548     add = 8;
12549   else
12550     add = 0;
12551
12552   switch (code)
12553     {
12554     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12555     case sp_reg: case bp_reg: case si_reg: case di_reg:
12556       s = names16[code - ax_reg + add];
12557       break;
12558     case es_reg: case ss_reg: case cs_reg:
12559     case ds_reg: case fs_reg: case gs_reg:
12560       s = names_seg[code - es_reg + add];
12561       break;
12562     case al_reg: case ah_reg: case cl_reg: case ch_reg:
12563     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12564       USED_REX (0);
12565       if (rex)
12566         s = names8rex[code - al_reg + add];
12567       else
12568         s = names8[code - al_reg];
12569       break;
12570     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12571     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12572       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12573         {
12574           s = names64[code - rAX_reg + add];
12575           break;
12576         }
12577       code += eAX_reg - rAX_reg;
12578       /* Fall through.  */
12579     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12580     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12581       USED_REX (REX_W);
12582       if (rex & REX_W)
12583         s = names64[code - eAX_reg + add];
12584       else
12585         {
12586           if (sizeflag & DFLAG)
12587             s = names32[code - eAX_reg + add];
12588           else
12589             s = names16[code - eAX_reg + add];
12590           used_prefixes |= (prefixes & PREFIX_DATA);
12591         }
12592       break;
12593     default:
12594       s = INTERNAL_DISASSEMBLER_ERROR;
12595       break;
12596     }
12597   oappend (s);
12598 }
12599
12600 static void
12601 OP_IMREG (int code, int sizeflag)
12602 {
12603   const char *s;
12604
12605   switch (code)
12606     {
12607     case indir_dx_reg:
12608       if (intel_syntax)
12609         s = "dx";
12610       else
12611         s = "(%dx)";
12612       break;
12613     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12614     case sp_reg: case bp_reg: case si_reg: case di_reg:
12615       s = names16[code - ax_reg];
12616       break;
12617     case es_reg: case ss_reg: case cs_reg:
12618     case ds_reg: case fs_reg: case gs_reg:
12619       s = names_seg[code - es_reg];
12620       break;
12621     case al_reg: case ah_reg: case cl_reg: case ch_reg:
12622     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12623       USED_REX (0);
12624       if (rex)
12625         s = names8rex[code - al_reg];
12626       else
12627         s = names8[code - al_reg];
12628       break;
12629     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12630     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12631       USED_REX (REX_W);
12632       if (rex & REX_W)
12633         s = names64[code - eAX_reg];
12634       else
12635         {
12636           if (sizeflag & DFLAG)
12637             s = names32[code - eAX_reg];
12638           else
12639             s = names16[code - eAX_reg];
12640           used_prefixes |= (prefixes & PREFIX_DATA);
12641         }
12642       break;
12643     case z_mode_ax_reg:
12644       if ((rex & REX_W) || (sizeflag & DFLAG))
12645         s = *names32;
12646       else
12647         s = *names16;
12648       if (!(rex & REX_W))
12649         used_prefixes |= (prefixes & PREFIX_DATA);
12650       break;
12651     default:
12652       s = INTERNAL_DISASSEMBLER_ERROR;
12653       break;
12654     }
12655   oappend (s);
12656 }
12657
12658 static void
12659 OP_I (int bytemode, int sizeflag)
12660 {
12661   bfd_signed_vma op;
12662   bfd_signed_vma mask = -1;
12663
12664   switch (bytemode)
12665     {
12666     case b_mode:
12667       FETCH_DATA (the_info, codep + 1);
12668       op = *codep++;
12669       mask = 0xff;
12670       break;
12671     case q_mode:
12672       if (address_mode == mode_64bit)
12673         {
12674           op = get32s ();
12675           break;
12676         }
12677       /* Fall through.  */
12678     case v_mode:
12679       USED_REX (REX_W);
12680       if (rex & REX_W)
12681         op = get32s ();
12682       else
12683         {
12684           if (sizeflag & DFLAG)
12685             {
12686               op = get32 ();
12687               mask = 0xffffffff;
12688             }
12689           else
12690             {
12691               op = get16 ();
12692               mask = 0xfffff;
12693             }
12694           used_prefixes |= (prefixes & PREFIX_DATA);
12695         }
12696       break;
12697     case w_mode:
12698       mask = 0xfffff;
12699       op = get16 ();
12700       break;
12701     case const_1_mode:
12702       if (intel_syntax)
12703         oappend ("1");
12704       return;
12705     default:
12706       oappend (INTERNAL_DISASSEMBLER_ERROR);
12707       return;
12708     }
12709
12710   op &= mask;
12711   scratchbuf[0] = '$';
12712   print_operand_value (scratchbuf + 1, 1, op);
12713   oappend (scratchbuf + intel_syntax);
12714   scratchbuf[0] = '\0';
12715 }
12716
12717 static void
12718 OP_I64 (int bytemode, int sizeflag)
12719 {
12720   bfd_signed_vma op;
12721   bfd_signed_vma mask = -1;
12722
12723   if (address_mode != mode_64bit)
12724     {
12725       OP_I (bytemode, sizeflag);
12726       return;
12727     }
12728
12729   switch (bytemode)
12730     {
12731     case b_mode:
12732       FETCH_DATA (the_info, codep + 1);
12733       op = *codep++;
12734       mask = 0xff;
12735       break;
12736     case v_mode:
12737       USED_REX (REX_W);
12738       if (rex & REX_W)
12739         op = get64 ();
12740       else
12741         {
12742           if (sizeflag & DFLAG)
12743             {
12744               op = get32 ();
12745               mask = 0xffffffff;
12746             }
12747           else
12748             {
12749               op = get16 ();
12750               mask = 0xfffff;
12751             }
12752           used_prefixes |= (prefixes & PREFIX_DATA);
12753         }
12754       break;
12755     case w_mode:
12756       mask = 0xfffff;
12757       op = get16 ();
12758       break;
12759     default:
12760       oappend (INTERNAL_DISASSEMBLER_ERROR);
12761       return;
12762     }
12763
12764   op &= mask;
12765   scratchbuf[0] = '$';
12766   print_operand_value (scratchbuf + 1, 1, op);
12767   oappend (scratchbuf + intel_syntax);
12768   scratchbuf[0] = '\0';
12769 }
12770
12771 static void
12772 OP_sI (int bytemode, int sizeflag)
12773 {
12774   bfd_signed_vma op;
12775   bfd_signed_vma mask = -1;
12776
12777   switch (bytemode)
12778     {
12779     case b_mode:
12780       FETCH_DATA (the_info, codep + 1);
12781       op = *codep++;
12782       if ((op & 0x80) != 0)
12783         op -= 0x100;
12784       mask = 0xffffffff;
12785       break;
12786     case v_mode:
12787       USED_REX (REX_W);
12788       if (rex & REX_W)
12789         op = get32s ();
12790       else
12791         {
12792           if (sizeflag & DFLAG)
12793             {
12794               op = get32s ();
12795               mask = 0xffffffff;
12796             }
12797           else
12798             {
12799               mask = 0xffffffff;
12800               op = get16 ();
12801               if ((op & 0x8000) != 0)
12802                 op -= 0x10000;
12803             }
12804           used_prefixes |= (prefixes & PREFIX_DATA);
12805         }
12806       break;
12807     case w_mode:
12808       op = get16 ();
12809       mask = 0xffffffff;
12810       if ((op & 0x8000) != 0)
12811         op -= 0x10000;
12812       break;
12813     default:
12814       oappend (INTERNAL_DISASSEMBLER_ERROR);
12815       return;
12816     }
12817
12818   scratchbuf[0] = '$';
12819   print_operand_value (scratchbuf + 1, 1, op);
12820   oappend (scratchbuf + intel_syntax);
12821 }
12822
12823 static void
12824 OP_J (int bytemode, int sizeflag)
12825 {
12826   bfd_vma disp;
12827   bfd_vma mask = -1;
12828   bfd_vma segment = 0;
12829
12830   switch (bytemode)
12831     {
12832     case b_mode:
12833       FETCH_DATA (the_info, codep + 1);
12834       disp = *codep++;
12835       if ((disp & 0x80) != 0)
12836         disp -= 0x100;
12837       break;
12838     case v_mode:
12839       USED_REX (REX_W);
12840       if ((sizeflag & DFLAG) || (rex & REX_W))
12841         disp = get32s ();
12842       else
12843         {
12844           disp = get16 ();
12845           if ((disp & 0x8000) != 0)
12846             disp -= 0x10000;
12847           /* In 16bit mode, address is wrapped around at 64k within
12848              the same segment.  Otherwise, a data16 prefix on a jump
12849              instruction means that the pc is masked to 16 bits after
12850              the displacement is added!  */
12851           mask = 0xffff;
12852           if ((prefixes & PREFIX_DATA) == 0)
12853             segment = ((start_pc + codep - start_codep)
12854                        & ~((bfd_vma) 0xffff));
12855         }
12856       if (!(rex & REX_W))
12857         used_prefixes |= (prefixes & PREFIX_DATA);
12858       break;
12859     default:
12860       oappend (INTERNAL_DISASSEMBLER_ERROR);
12861       return;
12862     }
12863   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
12864   set_op (disp, 0);
12865   print_operand_value (scratchbuf, 1, disp);
12866   oappend (scratchbuf);
12867 }
12868
12869 static void
12870 OP_SEG (int bytemode, int sizeflag)
12871 {
12872   if (bytemode == w_mode)
12873     oappend (names_seg[modrm.reg]);
12874   else
12875     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12876 }
12877
12878 static void
12879 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12880 {
12881   int seg, offset;
12882
12883   if (sizeflag & DFLAG)
12884     {
12885       offset = get32 ();
12886       seg = get16 ();
12887     }
12888   else
12889     {
12890       offset = get16 ();
12891       seg = get16 ();
12892     }
12893   used_prefixes |= (prefixes & PREFIX_DATA);
12894   if (intel_syntax)
12895     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12896   else
12897     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12898   oappend (scratchbuf);
12899 }
12900
12901 static void
12902 OP_OFF (int bytemode, int sizeflag)
12903 {
12904   bfd_vma off;
12905
12906   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12907     intel_operand_size (bytemode, sizeflag);
12908   append_seg ();
12909
12910   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12911     off = get32 ();
12912   else
12913     off = get16 ();
12914
12915   if (intel_syntax)
12916     {
12917       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12918                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12919         {
12920           oappend (names_seg[ds_reg - es_reg]);
12921           oappend (":");
12922         }
12923     }
12924   print_operand_value (scratchbuf, 1, off);
12925   oappend (scratchbuf);
12926 }
12927
12928 static void
12929 OP_OFF64 (int bytemode, int sizeflag)
12930 {
12931   bfd_vma off;
12932
12933   if (address_mode != mode_64bit
12934       || (prefixes & PREFIX_ADDR))
12935     {
12936       OP_OFF (bytemode, sizeflag);
12937       return;
12938     }
12939
12940   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12941     intel_operand_size (bytemode, sizeflag);
12942   append_seg ();
12943
12944   off = get64 ();
12945
12946   if (intel_syntax)
12947     {
12948       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12949                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12950         {
12951           oappend (names_seg[ds_reg - es_reg]);
12952           oappend (":");
12953         }
12954     }
12955   print_operand_value (scratchbuf, 1, off);
12956   oappend (scratchbuf);
12957 }
12958
12959 static void
12960 ptr_reg (int code, int sizeflag)
12961 {
12962   const char *s;
12963
12964   *obufp++ = open_char;
12965   used_prefixes |= (prefixes & PREFIX_ADDR);
12966   if (address_mode == mode_64bit)
12967     {
12968       if (!(sizeflag & AFLAG))
12969         s = names32[code - eAX_reg];
12970       else
12971         s = names64[code - eAX_reg];
12972     }
12973   else if (sizeflag & AFLAG)
12974     s = names32[code - eAX_reg];
12975   else
12976     s = names16[code - eAX_reg];
12977   oappend (s);
12978   *obufp++ = close_char;
12979   *obufp = 0;
12980 }
12981
12982 static void
12983 OP_ESreg (int code, int sizeflag)
12984 {
12985   if (intel_syntax)
12986     {
12987       switch (codep[-1])
12988         {
12989         case 0x6d:      /* insw/insl */
12990           intel_operand_size (z_mode, sizeflag);
12991           break;
12992         case 0xa5:      /* movsw/movsl/movsq */
12993         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12994         case 0xab:      /* stosw/stosl */
12995         case 0xaf:      /* scasw/scasl */
12996           intel_operand_size (v_mode, sizeflag);
12997           break;
12998         default:
12999           intel_operand_size (b_mode, sizeflag);
13000         }
13001     }
13002   oappend ("%es:" + intel_syntax);
13003   ptr_reg (code, sizeflag);
13004 }
13005
13006 static void
13007 OP_DSreg (int code, int sizeflag)
13008 {
13009   if (intel_syntax)
13010     {
13011       switch (codep[-1])
13012         {
13013         case 0x6f:      /* outsw/outsl */
13014           intel_operand_size (z_mode, sizeflag);
13015           break;
13016         case 0xa5:      /* movsw/movsl/movsq */
13017         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13018         case 0xad:      /* lodsw/lodsl/lodsq */
13019           intel_operand_size (v_mode, sizeflag);
13020           break;
13021         default:
13022           intel_operand_size (b_mode, sizeflag);
13023         }
13024     }
13025   if ((prefixes
13026        & (PREFIX_CS
13027           | PREFIX_DS
13028           | PREFIX_SS
13029           | PREFIX_ES
13030           | PREFIX_FS
13031           | PREFIX_GS)) == 0)
13032     prefixes |= PREFIX_DS;
13033   append_seg ();
13034   ptr_reg (code, sizeflag);
13035 }
13036
13037 static void
13038 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13039 {
13040   int add;
13041   if (rex & REX_R)
13042     {
13043       USED_REX (REX_R);
13044       add = 8;
13045     }
13046   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13047     {
13048       all_prefixes[last_lock_prefix] = 0;
13049       used_prefixes |= PREFIX_LOCK;
13050       add = 8;
13051     }
13052   else
13053     add = 0;
13054   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13055   oappend (scratchbuf + intel_syntax);
13056 }
13057
13058 static void
13059 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13060 {
13061   int add;
13062   USED_REX (REX_R);
13063   if (rex & REX_R)
13064     add = 8;
13065   else
13066     add = 0;
13067   if (intel_syntax)
13068     sprintf (scratchbuf, "db%d", modrm.reg + add);
13069   else
13070     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13071   oappend (scratchbuf);
13072 }
13073
13074 static void
13075 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13076 {
13077   sprintf (scratchbuf, "%%tr%d", modrm.reg);
13078   oappend (scratchbuf + intel_syntax);
13079 }
13080
13081 static void
13082 OP_R (int bytemode, int sizeflag)
13083 {
13084   if (modrm.mod == 3)
13085     OP_E (bytemode, sizeflag);
13086   else
13087     BadOp ();
13088 }
13089
13090 static void
13091 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13092 {
13093   used_prefixes |= (prefixes & PREFIX_DATA);
13094   if (prefixes & PREFIX_DATA)
13095     {
13096       int add;
13097       USED_REX (REX_R);
13098       if (rex & REX_R)
13099         add = 8;
13100       else
13101         add = 0;
13102       sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
13103     }
13104   else
13105     sprintf (scratchbuf, "%%mm%d", modrm.reg);
13106   oappend (scratchbuf + intel_syntax);
13107 }
13108
13109 static void
13110 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13111 {
13112   int add;
13113   USED_REX (REX_R);
13114   if (rex & REX_R)
13115     add = 8;
13116   else
13117     add = 0;
13118   if (need_vex && bytemode != xmm_mode)
13119     {
13120       switch (vex.length)
13121         {
13122         case 128:
13123           sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
13124           break;
13125         case 256:
13126           sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
13127           break;
13128         default:
13129           abort ();
13130         }
13131     }
13132   else
13133     sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
13134   oappend (scratchbuf + intel_syntax);
13135 }
13136
13137 static void
13138 OP_EM (int bytemode, int sizeflag)
13139 {
13140   if (modrm.mod != 3)
13141     {
13142       if (intel_syntax
13143           && (bytemode == v_mode || bytemode == v_swap_mode))
13144         {
13145           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13146           used_prefixes |= (prefixes & PREFIX_DATA);
13147         }
13148       OP_E (bytemode, sizeflag);
13149       return;
13150     }
13151
13152   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13153     swap_operand ();
13154
13155   /* Skip mod/rm byte.  */
13156   MODRM_CHECK;
13157   codep++;
13158   used_prefixes |= (prefixes & PREFIX_DATA);
13159   if (prefixes & PREFIX_DATA)
13160     {
13161       int add;
13162
13163       USED_REX (REX_B);
13164       if (rex & REX_B)
13165         add = 8;
13166       else
13167         add = 0;
13168       sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
13169     }
13170   else
13171     sprintf (scratchbuf, "%%mm%d", modrm.rm);
13172   oappend (scratchbuf + intel_syntax);
13173 }
13174
13175 /* cvt* are the only instructions in sse2 which have
13176    both SSE and MMX operands and also have 0x66 prefix
13177    in their opcode. 0x66 was originally used to differentiate
13178    between SSE and MMX instruction(operands). So we have to handle the
13179    cvt* separately using OP_EMC and OP_MXC */
13180 static void
13181 OP_EMC (int bytemode, int sizeflag)
13182 {
13183   if (modrm.mod != 3)
13184     {
13185       if (intel_syntax && bytemode == v_mode)
13186         {
13187           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13188           used_prefixes |= (prefixes & PREFIX_DATA);
13189         }
13190       OP_E (bytemode, sizeflag);
13191       return;
13192     }
13193
13194   /* Skip mod/rm byte.  */
13195   MODRM_CHECK;
13196   codep++;
13197   used_prefixes |= (prefixes & PREFIX_DATA);
13198   sprintf (scratchbuf, "%%mm%d", modrm.rm);
13199   oappend (scratchbuf + intel_syntax);
13200 }
13201
13202 static void
13203 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13204 {
13205   used_prefixes |= (prefixes & PREFIX_DATA);
13206   sprintf (scratchbuf, "%%mm%d", modrm.reg);
13207   oappend (scratchbuf + intel_syntax);
13208 }
13209
13210 static void
13211 OP_EX (int bytemode, int sizeflag)
13212 {
13213   int add;
13214
13215   /* Skip mod/rm byte.  */
13216   MODRM_CHECK;
13217   codep++;
13218
13219   if (modrm.mod != 3)
13220     {
13221       OP_E_memory (bytemode, sizeflag);
13222       return;
13223     }
13224
13225   USED_REX (REX_B);
13226   if (rex & REX_B)
13227     add = 8;
13228   else
13229     add = 0;
13230
13231   if ((sizeflag & SUFFIX_ALWAYS)
13232       && (bytemode == x_swap_mode
13233           || bytemode == d_swap_mode
13234           || bytemode == q_swap_mode))
13235     swap_operand ();
13236
13237   if (need_vex
13238       && bytemode != xmm_mode
13239       && bytemode != xmmq_mode)
13240     {
13241       switch (vex.length)
13242         {
13243         case 128:
13244           sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
13245           break;
13246         case 256:
13247           sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
13248           break;
13249         default:
13250           abort ();
13251         }
13252     }
13253   else
13254     sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
13255   oappend (scratchbuf + intel_syntax);
13256 }
13257
13258 static void
13259 OP_MS (int bytemode, int sizeflag)
13260 {
13261   if (modrm.mod == 3)
13262     OP_EM (bytemode, sizeflag);
13263   else
13264     BadOp ();
13265 }
13266
13267 static void
13268 OP_XS (int bytemode, int sizeflag)
13269 {
13270   if (modrm.mod == 3)
13271     OP_EX (bytemode, sizeflag);
13272   else
13273     BadOp ();
13274 }
13275
13276 static void
13277 OP_M (int bytemode, int sizeflag)
13278 {
13279   if (modrm.mod == 3)
13280     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13281     BadOp ();
13282   else
13283     OP_E (bytemode, sizeflag);
13284 }
13285
13286 static void
13287 OP_0f07 (int bytemode, int sizeflag)
13288 {
13289   if (modrm.mod != 3 || modrm.rm != 0)
13290     BadOp ();
13291   else
13292     OP_E (bytemode, sizeflag);
13293 }
13294
13295 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13296    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
13297
13298 static void
13299 NOP_Fixup1 (int bytemode, int sizeflag)
13300 {
13301   if ((prefixes & PREFIX_DATA) != 0
13302       || (rex != 0
13303           && rex != 0x48
13304           && address_mode == mode_64bit))
13305     OP_REG (bytemode, sizeflag);
13306   else
13307     strcpy (obuf, "nop");
13308 }
13309
13310 static void
13311 NOP_Fixup2 (int bytemode, int sizeflag)
13312 {
13313   if ((prefixes & PREFIX_DATA) != 0
13314       || (rex != 0
13315           && rex != 0x48
13316           && address_mode == mode_64bit))
13317     OP_IMREG (bytemode, sizeflag);
13318 }
13319
13320 static const char *const Suffix3DNow[] = {
13321 /* 00 */        NULL,           NULL,           NULL,           NULL,
13322 /* 04 */        NULL,           NULL,           NULL,           NULL,
13323 /* 08 */        NULL,           NULL,           NULL,           NULL,
13324 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
13325 /* 10 */        NULL,           NULL,           NULL,           NULL,
13326 /* 14 */        NULL,           NULL,           NULL,           NULL,
13327 /* 18 */        NULL,           NULL,           NULL,           NULL,
13328 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
13329 /* 20 */        NULL,           NULL,           NULL,           NULL,
13330 /* 24 */        NULL,           NULL,           NULL,           NULL,
13331 /* 28 */        NULL,           NULL,           NULL,           NULL,
13332 /* 2C */        NULL,           NULL,           NULL,           NULL,
13333 /* 30 */        NULL,           NULL,           NULL,           NULL,
13334 /* 34 */        NULL,           NULL,           NULL,           NULL,
13335 /* 38 */        NULL,           NULL,           NULL,           NULL,
13336 /* 3C */        NULL,           NULL,           NULL,           NULL,
13337 /* 40 */        NULL,           NULL,           NULL,           NULL,
13338 /* 44 */        NULL,           NULL,           NULL,           NULL,
13339 /* 48 */        NULL,           NULL,           NULL,           NULL,
13340 /* 4C */        NULL,           NULL,           NULL,           NULL,
13341 /* 50 */        NULL,           NULL,           NULL,           NULL,
13342 /* 54 */        NULL,           NULL,           NULL,           NULL,
13343 /* 58 */        NULL,           NULL,           NULL,           NULL,
13344 /* 5C */        NULL,           NULL,           NULL,           NULL,
13345 /* 60 */        NULL,           NULL,           NULL,           NULL,
13346 /* 64 */        NULL,           NULL,           NULL,           NULL,
13347 /* 68 */        NULL,           NULL,           NULL,           NULL,
13348 /* 6C */        NULL,           NULL,           NULL,           NULL,
13349 /* 70 */        NULL,           NULL,           NULL,           NULL,
13350 /* 74 */        NULL,           NULL,           NULL,           NULL,
13351 /* 78 */        NULL,           NULL,           NULL,           NULL,
13352 /* 7C */        NULL,           NULL,           NULL,           NULL,
13353 /* 80 */        NULL,           NULL,           NULL,           NULL,
13354 /* 84 */        NULL,           NULL,           NULL,           NULL,
13355 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
13356 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
13357 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
13358 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
13359 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
13360 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
13361 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
13362 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
13363 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
13364 /* AC */        NULL,           NULL,           "pfacc",        NULL,
13365 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
13366 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
13367 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
13368 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
13369 /* C0 */        NULL,           NULL,           NULL,           NULL,
13370 /* C4 */        NULL,           NULL,           NULL,           NULL,
13371 /* C8 */        NULL,           NULL,           NULL,           NULL,
13372 /* CC */        NULL,           NULL,           NULL,           NULL,
13373 /* D0 */        NULL,           NULL,           NULL,           NULL,
13374 /* D4 */        NULL,           NULL,           NULL,           NULL,
13375 /* D8 */        NULL,           NULL,           NULL,           NULL,
13376 /* DC */        NULL,           NULL,           NULL,           NULL,
13377 /* E0 */        NULL,           NULL,           NULL,           NULL,
13378 /* E4 */        NULL,           NULL,           NULL,           NULL,
13379 /* E8 */        NULL,           NULL,           NULL,           NULL,
13380 /* EC */        NULL,           NULL,           NULL,           NULL,
13381 /* F0 */        NULL,           NULL,           NULL,           NULL,
13382 /* F4 */        NULL,           NULL,           NULL,           NULL,
13383 /* F8 */        NULL,           NULL,           NULL,           NULL,
13384 /* FC */        NULL,           NULL,           NULL,           NULL,
13385 };
13386
13387 static void
13388 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13389 {
13390   const char *mnemonic;
13391
13392   FETCH_DATA (the_info, codep + 1);
13393   /* AMD 3DNow! instructions are specified by an opcode suffix in the
13394      place where an 8-bit immediate would normally go.  ie. the last
13395      byte of the instruction.  */
13396   obufp = mnemonicendp;
13397   mnemonic = Suffix3DNow[*codep++ & 0xff];
13398   if (mnemonic)
13399     oappend (mnemonic);
13400   else
13401     {
13402       /* Since a variable sized modrm/sib chunk is between the start
13403          of the opcode (0x0f0f) and the opcode suffix, we need to do
13404          all the modrm processing first, and don't know until now that
13405          we have a bad opcode.  This necessitates some cleaning up.  */
13406       op_out[0][0] = '\0';
13407       op_out[1][0] = '\0';
13408       BadOp ();
13409     }
13410   mnemonicendp = obufp;
13411 }
13412
13413 static struct op simd_cmp_op[] =
13414 {
13415   { STRING_COMMA_LEN ("eq") },
13416   { STRING_COMMA_LEN ("lt") },
13417   { STRING_COMMA_LEN ("le") },
13418   { STRING_COMMA_LEN ("unord") },
13419   { STRING_COMMA_LEN ("neq") },
13420   { STRING_COMMA_LEN ("nlt") },
13421   { STRING_COMMA_LEN ("nle") },
13422   { STRING_COMMA_LEN ("ord") }
13423 };
13424
13425 static void
13426 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13427 {
13428   unsigned int cmp_type;
13429
13430   FETCH_DATA (the_info, codep + 1);
13431   cmp_type = *codep++ & 0xff;
13432   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13433     {
13434       char suffix [3];
13435       char *p = mnemonicendp - 2;
13436       suffix[0] = p[0];
13437       suffix[1] = p[1];
13438       suffix[2] = '\0';
13439       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13440       mnemonicendp += simd_cmp_op[cmp_type].len;
13441     }
13442   else
13443     {
13444       /* We have a reserved extension byte.  Output it directly.  */
13445       scratchbuf[0] = '$';
13446       print_operand_value (scratchbuf + 1, 1, cmp_type);
13447       oappend (scratchbuf + intel_syntax);
13448       scratchbuf[0] = '\0';
13449     }
13450 }
13451
13452 static void
13453 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
13454           int sizeflag ATTRIBUTE_UNUSED)
13455 {
13456   /* mwait %eax,%ecx  */
13457   if (!intel_syntax)
13458     {
13459       const char **names = (address_mode == mode_64bit
13460                             ? names64 : names32);
13461       strcpy (op_out[0], names[0]);
13462       strcpy (op_out[1], names[1]);
13463       two_source_ops = 1;
13464     }
13465   /* Skip mod/rm byte.  */
13466   MODRM_CHECK;
13467   codep++;
13468 }
13469
13470 static void
13471 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13472             int sizeflag ATTRIBUTE_UNUSED)
13473 {
13474   /* monitor %eax,%ecx,%edx"  */
13475   if (!intel_syntax)
13476     {
13477       const char **op1_names;
13478       const char **names = (address_mode == mode_64bit
13479                             ? names64 : names32);
13480
13481       if (!(prefixes & PREFIX_ADDR))
13482         op1_names = (address_mode == mode_16bit
13483                      ? names16 : names);
13484       else
13485         {
13486           /* Remove "addr16/addr32".  */
13487           all_prefixes[last_addr_prefix] = 0;
13488           op1_names = (address_mode != mode_32bit
13489                        ? names32 : names16);
13490           used_prefixes |= PREFIX_ADDR;
13491         }
13492       strcpy (op_out[0], op1_names[0]);
13493       strcpy (op_out[1], names[1]);
13494       strcpy (op_out[2], names[2]);
13495       two_source_ops = 1;
13496     }
13497   /* Skip mod/rm byte.  */
13498   MODRM_CHECK;
13499   codep++;
13500 }
13501
13502 static void
13503 BadOp (void)
13504 {
13505   /* Throw away prefixes and 1st. opcode byte.  */
13506   codep = insn_codep + 1;
13507   oappend ("(bad)");
13508 }
13509
13510 static void
13511 REP_Fixup (int bytemode, int sizeflag)
13512 {
13513   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13514      lods and stos.  */
13515   if (prefixes & PREFIX_REPZ)
13516     all_prefixes[last_repz_prefix] = REP_PREFIX;
13517
13518   switch (bytemode)
13519     {
13520     case al_reg:
13521     case eAX_reg:
13522     case indir_dx_reg:
13523       OP_IMREG (bytemode, sizeflag);
13524       break;
13525     case eDI_reg:
13526       OP_ESreg (bytemode, sizeflag);
13527       break;
13528     case eSI_reg:
13529       OP_DSreg (bytemode, sizeflag);
13530       break;
13531     default:
13532       abort ();
13533       break;
13534     }
13535 }
13536
13537 static void
13538 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13539 {
13540   USED_REX (REX_W);
13541   if (rex & REX_W)
13542     {
13543       /* Change cmpxchg8b to cmpxchg16b.  */
13544       char *p = mnemonicendp - 2;
13545       mnemonicendp = stpcpy (p, "16b");
13546       bytemode = o_mode;
13547     }
13548   OP_M (bytemode, sizeflag);
13549 }
13550
13551 static void
13552 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13553 {
13554   if (need_vex)
13555     {
13556       switch (vex.length)
13557         {
13558         case 128:
13559           sprintf (scratchbuf, "%%xmm%d", reg);
13560           break;
13561         case 256:
13562           sprintf (scratchbuf, "%%ymm%d", reg);
13563           break;
13564         default:
13565           abort ();
13566         }
13567     }
13568   else
13569     sprintf (scratchbuf, "%%xmm%d", reg);
13570   oappend (scratchbuf + intel_syntax);
13571 }
13572
13573 static void
13574 CRC32_Fixup (int bytemode, int sizeflag)
13575 {
13576   /* Add proper suffix to "crc32".  */
13577   char *p = mnemonicendp;
13578
13579   switch (bytemode)
13580     {
13581     case b_mode:
13582       if (intel_syntax)
13583         goto skip;
13584
13585       *p++ = 'b';
13586       break;
13587     case v_mode:
13588       if (intel_syntax)
13589         goto skip;
13590
13591       USED_REX (REX_W);
13592       if (rex & REX_W)
13593         *p++ = 'q';
13594       else
13595         {
13596           if (sizeflag & DFLAG)
13597             *p++ = 'l';
13598           else
13599             *p++ = 'w';
13600           used_prefixes |= (prefixes & PREFIX_DATA);
13601         }
13602       break;
13603     default:
13604       oappend (INTERNAL_DISASSEMBLER_ERROR);
13605       break;
13606     }
13607   mnemonicendp = p;
13608   *p = '\0';
13609
13610 skip:
13611   if (modrm.mod == 3)
13612     {
13613       int add;
13614
13615       /* Skip mod/rm byte.  */
13616       MODRM_CHECK;
13617       codep++;
13618
13619       USED_REX (REX_B);
13620       add = (rex & REX_B) ? 8 : 0;
13621       if (bytemode == b_mode)
13622         {
13623           USED_REX (0);
13624           if (rex)
13625             oappend (names8rex[modrm.rm + add]);
13626           else
13627             oappend (names8[modrm.rm + add]);
13628         }
13629       else
13630         {
13631           USED_REX (REX_W);
13632           if (rex & REX_W)
13633             oappend (names64[modrm.rm + add]);
13634           else if ((prefixes & PREFIX_DATA))
13635             oappend (names16[modrm.rm + add]);
13636           else
13637             oappend (names32[modrm.rm + add]);
13638         }
13639     }
13640   else
13641     OP_E (bytemode, sizeflag);
13642 }
13643
13644 /* Display the destination register operand for instructions with
13645    VEX. */
13646
13647 static void
13648 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13649 {
13650   if (!need_vex)
13651     abort ();
13652
13653   if (!need_vex_reg)
13654     return;
13655
13656   switch (vex.length)
13657     {
13658     case 128:
13659       switch (bytemode)
13660         {
13661         case vex_mode:
13662         case vex128_mode:
13663           break;
13664         default:
13665           abort ();
13666           return;
13667         }
13668
13669       sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13670       break;
13671     case 256:
13672       switch (bytemode)
13673         {
13674         case vex_mode:
13675         case vex256_mode:
13676           break;
13677         default:
13678           abort ();
13679           return;
13680         }
13681
13682       sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
13683       break;
13684     default:
13685       abort ();
13686       break;
13687     }
13688   oappend (scratchbuf + intel_syntax);
13689 }
13690
13691 /* Get the VEX immediate byte without moving codep.  */
13692
13693 static unsigned char
13694 get_vex_imm8 (int sizeflag)
13695 {
13696   int bytes_before_imm = 0;
13697
13698   if (modrm.mod != 3)
13699     {
13700       /* There are SIB/displacement bytes.  */
13701       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13702         {
13703           /* 32/64 bit address mode */
13704           int base = modrm.rm;
13705
13706           /* Check SIB byte.  */
13707           if (base == 4)
13708             {
13709               FETCH_DATA (the_info, codep + 1);
13710               base = *codep & 7;
13711               /* Don't increase bytes_before_imm as this has already
13712                  been done in OP_E_memory.  */
13713             }
13714
13715           switch (modrm.mod)
13716             {
13717             case 0:
13718               /* When modrm.rm == 5 or modrm.rm == 4 and base in
13719                  SIB == 5, there is a 4 byte displacement.  */
13720               if (base != 5)
13721                 /* No displacement. */
13722                 break;
13723             case 2:
13724               /* 4 byte displacement.  */
13725               bytes_before_imm += 4;
13726               break;
13727             case 1:
13728               /* 1 byte displacement: codep has already been
13729                  incremented by 1 in OP_E_memory.  */
13730               break;
13731             }
13732         }
13733       else
13734         { /* 16 bit address mode */
13735           switch (modrm.mod)
13736             {
13737             case 0:
13738               /* When modrm.rm == 6, there is a 2 byte displacement.  */
13739               if (modrm.rm != 6)
13740                 /* No displacement. */
13741                 break;
13742             case 2:
13743               /* 2 byte displacement.  */
13744               bytes_before_imm += 2;
13745               break;
13746             case 1:
13747               /* 1 byte displacement: codep has already been
13748                  incremented by 1 in OP_E_memory.  */
13749               break;
13750             }
13751         }
13752     }
13753
13754   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
13755   return codep [bytes_before_imm];
13756 }
13757
13758 static void
13759 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
13760 {
13761   if (reg == -1 && modrm.mod != 3)
13762     {
13763       OP_E_memory (bytemode, sizeflag);
13764       return;
13765     }
13766   else
13767     {
13768       if (reg == -1)
13769         {
13770           reg = modrm.rm;
13771           USED_REX (REX_B);
13772           if (rex & REX_B)
13773             reg += 8;
13774         }
13775       else if (reg > 7 && address_mode != mode_64bit)
13776         BadOp ();
13777     }
13778
13779   switch (vex.length)
13780     {
13781     case 128:
13782       sprintf (scratchbuf, "%%xmm%d", reg);
13783       break;
13784     case 256:
13785       sprintf (scratchbuf, "%%ymm%d", reg);
13786       break;
13787     default:
13788       abort ();
13789     }
13790   oappend (scratchbuf + intel_syntax);
13791 }
13792
13793 static void
13794 OP_Vex_2src (int bytemode, int sizeflag)
13795 {
13796   if (modrm.mod == 3)
13797     {
13798       USED_REX (REX_B);
13799       sprintf (scratchbuf, "%%xmm%d", rex & REX_B ? modrm.rm + 8 : modrm.rm);
13800       oappend (scratchbuf + intel_syntax);
13801     }
13802   else
13803     {
13804       if (intel_syntax
13805           && (bytemode == v_mode || bytemode == v_swap_mode))
13806         {
13807           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13808           used_prefixes |= (prefixes & PREFIX_DATA);
13809         }
13810       OP_E (bytemode, sizeflag);
13811     }
13812 }
13813
13814 static void
13815 OP_Vex_2src_1 (int bytemode, int sizeflag)
13816 {
13817   if (modrm.mod == 3)
13818     {
13819       /* Skip mod/rm byte.   */
13820       MODRM_CHECK;
13821       codep++;
13822     }
13823
13824   if (vex.w)
13825     {
13826       sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13827       oappend (scratchbuf + intel_syntax);
13828     }
13829   else
13830     OP_Vex_2src (bytemode, sizeflag);
13831 }
13832
13833 static void
13834 OP_Vex_2src_2 (int bytemode, int sizeflag)
13835 {
13836   if (vex.w)
13837     OP_Vex_2src (bytemode, sizeflag);
13838   else
13839     {
13840       sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13841       oappend (scratchbuf + intel_syntax);
13842     }
13843 }
13844
13845 static void
13846 OP_EX_VexW (int bytemode, int sizeflag)
13847 {
13848   int reg = -1;
13849
13850   if (!vex_w_done)
13851     {
13852       vex_w_done = 1;
13853
13854       /* Skip mod/rm byte.  */
13855       MODRM_CHECK;
13856       codep++;
13857
13858       if (vex.w)
13859         reg = get_vex_imm8 (sizeflag) >> 4;
13860     }
13861   else
13862     {
13863       if (!vex.w)
13864         reg = get_vex_imm8 (sizeflag) >> 4;
13865     }
13866
13867   OP_EX_VexReg (bytemode, sizeflag, reg);
13868 }
13869
13870 static void
13871 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
13872              int sizeflag ATTRIBUTE_UNUSED)
13873 {
13874   /* Skip the immediate byte and check for invalid bits.  */
13875   FETCH_DATA (the_info, codep + 1);
13876   if (*codep++ & 0xf)
13877     BadOp ();
13878 }
13879
13880 static void
13881 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13882 {
13883   int reg;
13884   FETCH_DATA (the_info, codep + 1);
13885   reg = *codep++;
13886
13887   if (bytemode != x_mode)
13888     abort ();
13889
13890   if (reg & 0xf)
13891       BadOp ();
13892
13893   reg >>= 4;
13894   if (reg > 7 && address_mode != mode_64bit)
13895     BadOp ();
13896
13897   switch (vex.length)
13898     {
13899     case 128:
13900       sprintf (scratchbuf, "%%xmm%d", reg);
13901       break;
13902     case 256:
13903       sprintf (scratchbuf, "%%ymm%d", reg);
13904       break;
13905     default:
13906       abort ();
13907     }
13908   oappend (scratchbuf + intel_syntax);
13909 }
13910
13911 static void
13912 OP_XMM_VexW (int bytemode, int sizeflag)
13913 {
13914   /* Turn off the REX.W bit since it is used for swapping operands
13915      now.  */
13916   rex &= ~REX_W;
13917   OP_XMM (bytemode, sizeflag);
13918 }
13919
13920 static void
13921 OP_EX_Vex (int bytemode, int sizeflag)
13922 {
13923   if (modrm.mod != 3)
13924     {
13925       if (vex.register_specifier != 0)
13926         BadOp ();
13927       need_vex_reg = 0;
13928     }
13929   OP_EX (bytemode, sizeflag);
13930 }
13931
13932 static void
13933 OP_XMM_Vex (int bytemode, int sizeflag)
13934 {
13935   if (modrm.mod != 3)
13936     {
13937       if (vex.register_specifier != 0)
13938         BadOp ();
13939       need_vex_reg = 0;
13940     }
13941   OP_XMM (bytemode, sizeflag);
13942 }
13943
13944 static void
13945 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13946 {
13947   switch (vex.length)
13948     {
13949     case 128:
13950       mnemonicendp = stpcpy (obuf, "vzeroupper");
13951       break;
13952     case 256:
13953       mnemonicendp = stpcpy (obuf, "vzeroall");
13954       break;
13955     default:
13956       abort ();
13957     }
13958 }
13959
13960 static struct op vex_cmp_op[] =
13961 {
13962   { STRING_COMMA_LEN ("eq") },
13963   { STRING_COMMA_LEN ("lt") },
13964   { STRING_COMMA_LEN ("le") },
13965   { STRING_COMMA_LEN ("unord") },
13966   { STRING_COMMA_LEN ("neq") },
13967   { STRING_COMMA_LEN ("nlt") },
13968   { STRING_COMMA_LEN ("nle") },
13969   { STRING_COMMA_LEN ("ord") },
13970   { STRING_COMMA_LEN ("eq_uq") },
13971   { STRING_COMMA_LEN ("nge") },
13972   { STRING_COMMA_LEN ("ngt") },
13973   { STRING_COMMA_LEN ("false") },
13974   { STRING_COMMA_LEN ("neq_oq") },
13975   { STRING_COMMA_LEN ("ge") },
13976   { STRING_COMMA_LEN ("gt") },
13977   { STRING_COMMA_LEN ("true") },
13978   { STRING_COMMA_LEN ("eq_os") },
13979   { STRING_COMMA_LEN ("lt_oq") },
13980   { STRING_COMMA_LEN ("le_oq") },
13981   { STRING_COMMA_LEN ("unord_s") },
13982   { STRING_COMMA_LEN ("neq_us") },
13983   { STRING_COMMA_LEN ("nlt_uq") },
13984   { STRING_COMMA_LEN ("nle_uq") },
13985   { STRING_COMMA_LEN ("ord_s") },
13986   { STRING_COMMA_LEN ("eq_us") },
13987   { STRING_COMMA_LEN ("nge_uq") },
13988   { STRING_COMMA_LEN ("ngt_uq") },
13989   { STRING_COMMA_LEN ("false_os") },
13990   { STRING_COMMA_LEN ("neq_os") },
13991   { STRING_COMMA_LEN ("ge_oq") },
13992   { STRING_COMMA_LEN ("gt_oq") },
13993   { STRING_COMMA_LEN ("true_us") },
13994 };
13995
13996 static void
13997 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13998 {
13999   unsigned int cmp_type;
14000
14001   FETCH_DATA (the_info, codep + 1);
14002   cmp_type = *codep++ & 0xff;
14003   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
14004     {
14005       char suffix [3];
14006       char *p = mnemonicendp - 2;
14007       suffix[0] = p[0];
14008       suffix[1] = p[1];
14009       suffix[2] = '\0';
14010       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
14011       mnemonicendp += vex_cmp_op[cmp_type].len;
14012     }
14013   else
14014     {
14015       /* We have a reserved extension byte.  Output it directly.  */
14016       scratchbuf[0] = '$';
14017       print_operand_value (scratchbuf + 1, 1, cmp_type);
14018       oappend (scratchbuf + intel_syntax);
14019       scratchbuf[0] = '\0';
14020     }
14021 }
14022
14023 static const struct op pclmul_op[] =
14024 {
14025   { STRING_COMMA_LEN ("lql") },
14026   { STRING_COMMA_LEN ("hql") },
14027   { STRING_COMMA_LEN ("lqh") },
14028   { STRING_COMMA_LEN ("hqh") }
14029 };
14030
14031 static void
14032 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
14033               int sizeflag ATTRIBUTE_UNUSED)
14034 {
14035   unsigned int pclmul_type;
14036
14037   FETCH_DATA (the_info, codep + 1);
14038   pclmul_type = *codep++ & 0xff;
14039   switch (pclmul_type)
14040     {
14041     case 0x10:
14042       pclmul_type = 2;
14043       break;
14044     case 0x11:
14045       pclmul_type = 3;
14046       break;
14047     default:
14048       break;
14049     }
14050   if (pclmul_type < ARRAY_SIZE (pclmul_op))
14051     {
14052       char suffix [4];
14053       char *p = mnemonicendp - 3;
14054       suffix[0] = p[0];
14055       suffix[1] = p[1];
14056       suffix[2] = p[2];
14057       suffix[3] = '\0';
14058       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14059       mnemonicendp += pclmul_op[pclmul_type].len;
14060     }
14061   else
14062     {
14063       /* We have a reserved extension byte.  Output it directly.  */
14064       scratchbuf[0] = '$';
14065       print_operand_value (scratchbuf + 1, 1, pclmul_type);
14066       oappend (scratchbuf + intel_syntax);
14067       scratchbuf[0] = '\0';
14068     }
14069 }
14070
14071 static void
14072 MOVBE_Fixup (int bytemode, int sizeflag)
14073 {
14074   /* Add proper suffix to "movbe".  */
14075   char *p = mnemonicendp;
14076
14077   switch (bytemode)
14078     {
14079     case v_mode:
14080       if (intel_syntax)
14081         goto skip;
14082
14083       USED_REX (REX_W);
14084       if (sizeflag & SUFFIX_ALWAYS)
14085         {
14086           if (rex & REX_W)
14087             *p++ = 'q';
14088           else
14089             {
14090               if (sizeflag & DFLAG)
14091                 *p++ = 'l';
14092               else
14093                 *p++ = 'w';
14094               used_prefixes |= (prefixes & PREFIX_DATA);
14095             }
14096         }
14097       break;
14098     default:
14099       oappend (INTERNAL_DISASSEMBLER_ERROR);
14100       break;
14101     }
14102   mnemonicendp = p;
14103   *p = '\0';
14104
14105 skip:
14106   OP_M (bytemode, sizeflag);
14107 }
14108
14109 static void
14110 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14111 {
14112   int reg;
14113   const char **names;
14114
14115   /* Skip mod/rm byte.  */
14116   MODRM_CHECK;
14117   codep++;
14118
14119   if (vex.w)
14120     names = names64;
14121   else if (vex.length == 256)
14122     names = names32;
14123   else
14124     names = names16;
14125
14126   reg = modrm.rm;
14127   USED_REX (REX_B);
14128   if (rex & REX_B)
14129     reg += 8;
14130
14131   oappend (names[reg]);
14132 }
14133
14134 static void
14135 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14136 {
14137   const char **names;
14138
14139   if (vex.w)
14140     names = names64;
14141   else if (vex.length == 256)
14142     names = names32;
14143   else
14144     names = names16;
14145
14146   oappend (names[vex.register_specifier]);
14147 }
14148
14149 static void
14150 OP_LWP_I (int bytemode ATTRIBUTE_UNUSED, int sizeflag)
14151 {
14152   if (vex.w || vex.length == 256)
14153     OP_I (q_mode, sizeflag);
14154   else
14155     OP_I (w_mode, sizeflag);
14156 }
14157