1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void NOP_Fixup1 (int, int);
105 static void NOP_Fixup2 (int, int);
106 static void OP_3DNowSuffix (int, int);
107 static void CMP_Fixup (int, int);
108 static void BadOp (void);
109 static void REP_Fixup (int, int);
110 static void SEP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
127 static void MOVSXD_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte
*max_fetched
;
134 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
137 OPCODES_SIGJMP_BUF bailout
;
147 enum address_mode address_mode
;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* REX bits in original REX prefix ignored. */
157 static int rex_ignored
;
158 /* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162 #define USED_REX(value) \
167 rex_used |= (value) | REX_OPCODE; \
170 rex_used |= REX_OPCODE; \
173 /* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175 static int used_prefixes
;
177 /* Flags stored in PREFIXES. */
178 #define PREFIX_REPZ 1
179 #define PREFIX_REPNZ 2
180 #define PREFIX_LOCK 4
182 #define PREFIX_SS 0x10
183 #define PREFIX_DS 0x20
184 #define PREFIX_ES 0x40
185 #define PREFIX_FS 0x80
186 #define PREFIX_GS 0x100
187 #define PREFIX_DATA 0x200
188 #define PREFIX_ADDR 0x400
189 #define PREFIX_FWAIT 0x800
191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
194 #define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
199 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
202 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
203 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
205 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
206 status
= (*info
->read_memory_func
) (start
,
208 addr
- priv
->max_fetched
,
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
218 if (priv
->max_fetched
== priv
->the_buffer
)
219 (*info
->memory_error_func
) (status
, start
, info
);
220 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
223 priv
->max_fetched
= addr
;
227 /* Possible values for prefix requirement. */
228 #define PREFIX_IGNORED_SHIFT 16
229 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
235 /* Opcode prefixes. */
236 #define PREFIX_OPCODE (PREFIX_REPZ \
240 /* Prefixes ignored. */
241 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
245 #define XX { NULL, 0 }
246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
248 #define Eb { OP_E, b_mode }
249 #define Ebnd { OP_E, bnd_mode }
250 #define EbS { OP_E, b_swap_mode }
251 #define EbndS { OP_E, bnd_swap_mode }
252 #define Ev { OP_E, v_mode }
253 #define Eva { OP_E, va_mode }
254 #define Ev_bnd { OP_E, v_bnd_mode }
255 #define EvS { OP_E, v_swap_mode }
256 #define Ed { OP_E, d_mode }
257 #define Edq { OP_E, dq_mode }
258 #define Edqw { OP_E, dqw_mode }
259 #define Edqb { OP_E, dqb_mode }
260 #define Edb { OP_E, db_mode }
261 #define Edw { OP_E, dw_mode }
262 #define Edqd { OP_E, dqd_mode }
263 #define Eq { OP_E, q_mode }
264 #define indirEv { OP_indirE, indir_v_mode }
265 #define indirEp { OP_indirE, f_mode }
266 #define stackEv { OP_E, stack_v_mode }
267 #define Em { OP_E, m_mode }
268 #define Ew { OP_E, w_mode }
269 #define M { OP_M, 0 } /* lea, lgdt, etc. */
270 #define Ma { OP_M, a_mode }
271 #define Mb { OP_M, b_mode }
272 #define Md { OP_M, d_mode }
273 #define Mo { OP_M, o_mode }
274 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
275 #define Mq { OP_M, q_mode }
276 #define Mv_bnd { OP_M, v_bndmk_mode }
277 #define Mx { OP_M, x_mode }
278 #define Mxmm { OP_M, xmm_mode }
279 #define Gb { OP_G, b_mode }
280 #define Gbnd { OP_G, bnd_mode }
281 #define Gv { OP_G, v_mode }
282 #define Gd { OP_G, d_mode }
283 #define Gdq { OP_G, dq_mode }
284 #define Gm { OP_G, m_mode }
285 #define Gva { OP_G, va_mode }
286 #define Gw { OP_G, w_mode }
287 #define Rd { OP_R, d_mode }
288 #define Rdq { OP_R, dq_mode }
289 #define Rm { OP_R, m_mode }
290 #define Ib { OP_I, b_mode }
291 #define sIb { OP_sI, b_mode } /* sign extened byte */
292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
293 #define Iv { OP_I, v_mode }
294 #define sIv { OP_sI, v_mode }
295 #define Iv64 { OP_I64, v_mode }
296 #define Id { OP_I, d_mode }
297 #define Iw { OP_I, w_mode }
298 #define I1 { OP_I, const_1_mode }
299 #define Jb { OP_J, b_mode }
300 #define Jv { OP_J, v_mode }
301 #define Jdqw { OP_J, dqw_mode }
302 #define Cm { OP_C, m_mode }
303 #define Dm { OP_D, m_mode }
304 #define Td { OP_T, d_mode }
305 #define Skip_MODRM { OP_Skip_MODRM, 0 }
307 #define RMeAX { OP_REG, eAX_reg }
308 #define RMeBX { OP_REG, eBX_reg }
309 #define RMeCX { OP_REG, eCX_reg }
310 #define RMeDX { OP_REG, eDX_reg }
311 #define RMeSP { OP_REG, eSP_reg }
312 #define RMeBP { OP_REG, eBP_reg }
313 #define RMeSI { OP_REG, eSI_reg }
314 #define RMeDI { OP_REG, eDI_reg }
315 #define RMrAX { OP_REG, rAX_reg }
316 #define RMrBX { OP_REG, rBX_reg }
317 #define RMrCX { OP_REG, rCX_reg }
318 #define RMrDX { OP_REG, rDX_reg }
319 #define RMrSP { OP_REG, rSP_reg }
320 #define RMrBP { OP_REG, rBP_reg }
321 #define RMrSI { OP_REG, rSI_reg }
322 #define RMrDI { OP_REG, rDI_reg }
323 #define RMAL { OP_REG, al_reg }
324 #define RMCL { OP_REG, cl_reg }
325 #define RMDL { OP_REG, dl_reg }
326 #define RMBL { OP_REG, bl_reg }
327 #define RMAH { OP_REG, ah_reg }
328 #define RMCH { OP_REG, ch_reg }
329 #define RMDH { OP_REG, dh_reg }
330 #define RMBH { OP_REG, bh_reg }
331 #define RMAX { OP_REG, ax_reg }
332 #define RMDX { OP_REG, dx_reg }
334 #define eAX { OP_IMREG, eAX_reg }
335 #define eBX { OP_IMREG, eBX_reg }
336 #define eCX { OP_IMREG, eCX_reg }
337 #define eDX { OP_IMREG, eDX_reg }
338 #define eSP { OP_IMREG, eSP_reg }
339 #define eBP { OP_IMREG, eBP_reg }
340 #define eSI { OP_IMREG, eSI_reg }
341 #define eDI { OP_IMREG, eDI_reg }
342 #define AL { OP_IMREG, al_reg }
343 #define CL { OP_IMREG, cl_reg }
344 #define DL { OP_IMREG, dl_reg }
345 #define BL { OP_IMREG, bl_reg }
346 #define AH { OP_IMREG, ah_reg }
347 #define CH { OP_IMREG, ch_reg }
348 #define DH { OP_IMREG, dh_reg }
349 #define BH { OP_IMREG, bh_reg }
350 #define AX { OP_IMREG, ax_reg }
351 #define DX { OP_IMREG, dx_reg }
352 #define zAX { OP_IMREG, z_mode_ax_reg }
353 #define indirDX { OP_IMREG, indir_dx_reg }
355 #define Sw { OP_SEG, w_mode }
356 #define Sv { OP_SEG, v_mode }
357 #define Ap { OP_DIR, 0 }
358 #define Ob { OP_OFF64, b_mode }
359 #define Ov { OP_OFF64, v_mode }
360 #define Xb { OP_DSreg, eSI_reg }
361 #define Xv { OP_DSreg, eSI_reg }
362 #define Xz { OP_DSreg, eSI_reg }
363 #define Yb { OP_ESreg, eDI_reg }
364 #define Yv { OP_ESreg, eDI_reg }
365 #define DSBX { OP_DSreg, eBX_reg }
367 #define es { OP_REG, es_reg }
368 #define ss { OP_REG, ss_reg }
369 #define cs { OP_REG, cs_reg }
370 #define ds { OP_REG, ds_reg }
371 #define fs { OP_REG, fs_reg }
372 #define gs { OP_REG, gs_reg }
374 #define MX { OP_MMX, 0 }
375 #define XM { OP_XMM, 0 }
376 #define XMScalar { OP_XMM, scalar_mode }
377 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
378 #define XMM { OP_XMM, xmm_mode }
379 #define XMxmmq { OP_XMM, xmmq_mode }
380 #define EM { OP_EM, v_mode }
381 #define EMS { OP_EM, v_swap_mode }
382 #define EMd { OP_EM, d_mode }
383 #define EMx { OP_EM, x_mode }
384 #define EXbScalar { OP_EX, b_scalar_mode }
385 #define EXw { OP_EX, w_mode }
386 #define EXwScalar { OP_EX, w_scalar_mode }
387 #define EXd { OP_EX, d_mode }
388 #define EXdScalar { OP_EX, d_scalar_mode }
389 #define EXdS { OP_EX, d_swap_mode }
390 #define EXq { OP_EX, q_mode }
391 #define EXqScalar { OP_EX, q_scalar_mode }
392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
393 #define EXqS { OP_EX, q_swap_mode }
394 #define EXx { OP_EX, x_mode }
395 #define EXxS { OP_EX, x_swap_mode }
396 #define EXxmm { OP_EX, xmm_mode }
397 #define EXymm { OP_EX, ymm_mode }
398 #define EXxmmq { OP_EX, xmmq_mode }
399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
402 #define EXxmm_md { OP_EX, xmm_md_mode }
403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
405 #define EXxmmdw { OP_EX, xmmdw_mode }
406 #define EXxmmqd { OP_EX, xmmqd_mode }
407 #define EXymmq { OP_EX, ymmq_mode }
408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
412 #define MS { OP_MS, v_mode }
413 #define XS { OP_XS, v_mode }
414 #define EMCq { OP_EMC, q_mode }
415 #define MXC { OP_MXC, 0 }
416 #define OPSUF { OP_3DNowSuffix, 0 }
417 #define SEP { SEP_Fixup, 0 }
418 #define CMP { CMP_Fixup, 0 }
419 #define XMM0 { XMM_Fixup, 0 }
420 #define FXSAVE { FXSAVE_Fixup, 0 }
421 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
422 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
424 #define Vex { OP_VEX, vex_mode }
425 #define VexScalar { OP_VEX, vex_scalar_mode }
426 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
427 #define Vex128 { OP_VEX, vex128_mode }
428 #define Vex256 { OP_VEX, vex256_mode }
429 #define VexGdq { OP_VEX, dq_mode }
430 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
431 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
432 #define EXVexW { OP_EX_VexW, x_mode }
433 #define EXdVexW { OP_EX_VexW, d_mode }
434 #define EXqVexW { OP_EX_VexW, q_mode }
435 #define EXVexImmW { OP_EX_VexImmW, x_mode }
436 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
437 #define XMVexW { OP_XMM_VexW, 0 }
438 #define XMVexI4 { OP_REG_VexI4, x_mode }
439 #define PCLMUL { PCLMUL_Fixup, 0 }
440 #define VCMP { VCMP_Fixup, 0 }
441 #define VPCMP { VPCMP_Fixup, 0 }
442 #define VPCOM { VPCOM_Fixup, 0 }
444 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
445 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
446 #define EXxEVexS { OP_Rounding, evex_sae_mode }
448 #define XMask { OP_Mask, mask_mode }
449 #define MaskG { OP_G, mask_mode }
450 #define MaskE { OP_E, mask_mode }
451 #define MaskBDE { OP_E, mask_bd_mode }
452 #define MaskR { OP_R, mask_mode }
453 #define MaskVex { OP_VEX, mask_mode }
455 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
456 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
457 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
458 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
460 /* Used handle "rep" prefix for string instructions. */
461 #define Xbr { REP_Fixup, eSI_reg }
462 #define Xvr { REP_Fixup, eSI_reg }
463 #define Ybr { REP_Fixup, eDI_reg }
464 #define Yvr { REP_Fixup, eDI_reg }
465 #define Yzr { REP_Fixup, eDI_reg }
466 #define indirDXr { REP_Fixup, indir_dx_reg }
467 #define ALr { REP_Fixup, al_reg }
468 #define eAXr { REP_Fixup, eAX_reg }
470 /* Used handle HLE prefix for lockable instructions. */
471 #define Ebh1 { HLE_Fixup1, b_mode }
472 #define Evh1 { HLE_Fixup1, v_mode }
473 #define Ebh2 { HLE_Fixup2, b_mode }
474 #define Evh2 { HLE_Fixup2, v_mode }
475 #define Ebh3 { HLE_Fixup3, b_mode }
476 #define Evh3 { HLE_Fixup3, v_mode }
478 #define BND { BND_Fixup, 0 }
479 #define NOTRACK { NOTRACK_Fixup, 0 }
481 #define cond_jump_flag { NULL, cond_jump_mode }
482 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
484 /* bits in sizeflag */
485 #define SUFFIX_ALWAYS 4
493 /* byte operand with operand swapped */
495 /* byte operand, sign extend like 'T' suffix */
497 /* operand size depends on prefixes */
499 /* operand size depends on prefixes with operand swapped */
501 /* operand size depends on address prefix */
505 /* double word operand */
507 /* double word operand with operand swapped */
509 /* quad word operand */
511 /* quad word operand with operand swapped */
513 /* ten-byte operand */
515 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
516 broadcast enabled. */
518 /* Similar to x_mode, but with different EVEX mem shifts. */
520 /* Similar to x_mode, but with disabled broadcast. */
522 /* Similar to x_mode, but with operands swapped and disabled broadcast
525 /* 16-byte XMM operand */
527 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
528 memory operand (depending on vector length). Broadcast isn't
531 /* Same as xmmq_mode, but broadcast is allowed. */
532 evex_half_bcst_xmmq_mode
,
533 /* XMM register or byte memory operand */
535 /* XMM register or word memory operand */
537 /* XMM register or double word memory operand */
539 /* XMM register or quad word memory operand */
541 /* XMM register or double/quad word memory operand, depending on
544 /* 16-byte XMM, word, double word or quad word operand. */
546 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
548 /* 32-byte YMM operand */
550 /* quad word, ymmword or zmmword memory operand. */
552 /* 32-byte YMM or 16-byte word operand */
554 /* d_mode in 32bit, q_mode in 64bit mode. */
556 /* pair of v_mode operands */
562 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
564 /* operand size depends on REX prefixes. */
566 /* registers like dq_mode, memory like w_mode, displacements like
567 v_mode without considering Intel64 ISA. */
571 /* bounds operand with operand swapped */
573 /* 4- or 6-byte pointer operand */
576 /* v_mode for indirect branch opcodes. */
578 /* v_mode for stack-related opcodes. */
580 /* non-quad operand size depends on prefixes */
582 /* 16-byte operand */
584 /* registers like dq_mode, memory like b_mode. */
586 /* registers like d_mode, memory like b_mode. */
588 /* registers like d_mode, memory like w_mode. */
590 /* registers like dq_mode, memory like d_mode. */
592 /* normal vex mode */
594 /* 128bit vex mode */
596 /* 256bit vex mode */
598 /* operand size depends on the VEX.W bit. */
601 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
602 vex_vsib_d_w_dq_mode
,
603 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
605 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
606 vex_vsib_q_w_dq_mode
,
607 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
610 /* scalar, ignore vector length. */
612 /* like b_mode, ignore vector length. */
614 /* like w_mode, ignore vector length. */
616 /* like d_mode, ignore vector length. */
618 /* like d_swap_mode, ignore vector length. */
620 /* like q_mode, ignore vector length. */
622 /* like q_swap_mode, ignore vector length. */
624 /* like vex_mode, ignore vector length. */
626 /* like vex_w_dq_mode, ignore vector length. */
627 vex_scalar_w_dq_mode
,
629 /* Static rounding. */
631 /* Static rounding, 64-bit mode only. */
632 evex_rounding_64_mode
,
633 /* Supress all exceptions. */
636 /* Mask register operand. */
638 /* Mask register operand. */
706 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
708 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
709 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
710 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
711 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
712 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
713 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
714 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
715 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
716 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
717 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
718 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
719 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
720 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
721 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
722 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
723 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
851 MOD_VEX_0F12_PREFIX_0
,
853 MOD_VEX_0F16_PREFIX_0
,
856 MOD_VEX_W_0_0F41_P_0_LEN_1
,
857 MOD_VEX_W_1_0F41_P_0_LEN_1
,
858 MOD_VEX_W_0_0F41_P_2_LEN_1
,
859 MOD_VEX_W_1_0F41_P_2_LEN_1
,
860 MOD_VEX_W_0_0F42_P_0_LEN_1
,
861 MOD_VEX_W_1_0F42_P_0_LEN_1
,
862 MOD_VEX_W_0_0F42_P_2_LEN_1
,
863 MOD_VEX_W_1_0F42_P_2_LEN_1
,
864 MOD_VEX_W_0_0F44_P_0_LEN_1
,
865 MOD_VEX_W_1_0F44_P_0_LEN_1
,
866 MOD_VEX_W_0_0F44_P_2_LEN_1
,
867 MOD_VEX_W_1_0F44_P_2_LEN_1
,
868 MOD_VEX_W_0_0F45_P_0_LEN_1
,
869 MOD_VEX_W_1_0F45_P_0_LEN_1
,
870 MOD_VEX_W_0_0F45_P_2_LEN_1
,
871 MOD_VEX_W_1_0F45_P_2_LEN_1
,
872 MOD_VEX_W_0_0F46_P_0_LEN_1
,
873 MOD_VEX_W_1_0F46_P_0_LEN_1
,
874 MOD_VEX_W_0_0F46_P_2_LEN_1
,
875 MOD_VEX_W_1_0F46_P_2_LEN_1
,
876 MOD_VEX_W_0_0F47_P_0_LEN_1
,
877 MOD_VEX_W_1_0F47_P_0_LEN_1
,
878 MOD_VEX_W_0_0F47_P_2_LEN_1
,
879 MOD_VEX_W_1_0F47_P_2_LEN_1
,
880 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
881 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
882 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
883 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
884 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
885 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
886 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
898 MOD_VEX_W_0_0F91_P_0_LEN_0
,
899 MOD_VEX_W_1_0F91_P_0_LEN_0
,
900 MOD_VEX_W_0_0F91_P_2_LEN_0
,
901 MOD_VEX_W_1_0F91_P_2_LEN_0
,
902 MOD_VEX_W_0_0F92_P_0_LEN_0
,
903 MOD_VEX_W_0_0F92_P_2_LEN_0
,
904 MOD_VEX_0F92_P_3_LEN_0
,
905 MOD_VEX_W_0_0F93_P_0_LEN_0
,
906 MOD_VEX_W_0_0F93_P_2_LEN_0
,
907 MOD_VEX_0F93_P_3_LEN_0
,
908 MOD_VEX_W_0_0F98_P_0_LEN_0
,
909 MOD_VEX_W_1_0F98_P_0_LEN_0
,
910 MOD_VEX_W_0_0F98_P_2_LEN_0
,
911 MOD_VEX_W_1_0F98_P_2_LEN_0
,
912 MOD_VEX_W_0_0F99_P_0_LEN_0
,
913 MOD_VEX_W_1_0F99_P_0_LEN_0
,
914 MOD_VEX_W_0_0F99_P_2_LEN_0
,
915 MOD_VEX_W_1_0F99_P_2_LEN_0
,
918 MOD_VEX_0FD7_PREFIX_2
,
919 MOD_VEX_0FE7_PREFIX_2
,
920 MOD_VEX_0FF0_PREFIX_3
,
921 MOD_VEX_0F381A_PREFIX_2
,
922 MOD_VEX_0F382A_PREFIX_2
,
923 MOD_VEX_0F382C_PREFIX_2
,
924 MOD_VEX_0F382D_PREFIX_2
,
925 MOD_VEX_0F382E_PREFIX_2
,
926 MOD_VEX_0F382F_PREFIX_2
,
927 MOD_VEX_0F385A_PREFIX_2
,
928 MOD_VEX_0F388C_PREFIX_2
,
929 MOD_VEX_0F388E_PREFIX_2
,
930 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
931 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
932 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
933 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
934 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
935 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
936 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
937 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
939 MOD_EVEX_0F12_PREFIX_0
,
940 MOD_EVEX_0F16_PREFIX_0
,
941 MOD_EVEX_0F38C6_REG_1
,
942 MOD_EVEX_0F38C6_REG_2
,
943 MOD_EVEX_0F38C6_REG_5
,
944 MOD_EVEX_0F38C6_REG_6
,
945 MOD_EVEX_0F38C7_REG_1
,
946 MOD_EVEX_0F38C7_REG_2
,
947 MOD_EVEX_0F38C7_REG_5
,
948 MOD_EVEX_0F38C7_REG_6
961 RM_0F1E_P_1_MOD_3_REG_7
,
962 RM_0FAE_REG_6_MOD_3_P_0
,
969 PREFIX_0F01_REG_5_MOD_0
,
970 PREFIX_0F01_REG_5_MOD_3_RM_0
,
971 PREFIX_0F01_REG_5_MOD_3_RM_2
,
972 PREFIX_0F01_REG_7_MOD_3_RM_2
,
973 PREFIX_0F01_REG_7_MOD_3_RM_3
,
1015 PREFIX_0FAE_REG_0_MOD_3
,
1016 PREFIX_0FAE_REG_1_MOD_3
,
1017 PREFIX_0FAE_REG_2_MOD_3
,
1018 PREFIX_0FAE_REG_3_MOD_3
,
1019 PREFIX_0FAE_REG_4_MOD_0
,
1020 PREFIX_0FAE_REG_4_MOD_3
,
1021 PREFIX_0FAE_REG_5_MOD_0
,
1022 PREFIX_0FAE_REG_5_MOD_3
,
1023 PREFIX_0FAE_REG_6_MOD_0
,
1024 PREFIX_0FAE_REG_6_MOD_3
,
1025 PREFIX_0FAE_REG_7_MOD_0
,
1031 PREFIX_0FC7_REG_6_MOD_0
,
1032 PREFIX_0FC7_REG_6_MOD_3
,
1033 PREFIX_0FC7_REG_7_MOD_3
,
1163 PREFIX_VEX_0F71_REG_2
,
1164 PREFIX_VEX_0F71_REG_4
,
1165 PREFIX_VEX_0F71_REG_6
,
1166 PREFIX_VEX_0F72_REG_2
,
1167 PREFIX_VEX_0F72_REG_4
,
1168 PREFIX_VEX_0F72_REG_6
,
1169 PREFIX_VEX_0F73_REG_2
,
1170 PREFIX_VEX_0F73_REG_3
,
1171 PREFIX_VEX_0F73_REG_6
,
1172 PREFIX_VEX_0F73_REG_7
,
1345 PREFIX_VEX_0F38F3_REG_1
,
1346 PREFIX_VEX_0F38F3_REG_2
,
1347 PREFIX_VEX_0F38F3_REG_3
,
1466 PREFIX_EVEX_0F71_REG_2
,
1467 PREFIX_EVEX_0F71_REG_4
,
1468 PREFIX_EVEX_0F71_REG_6
,
1469 PREFIX_EVEX_0F72_REG_0
,
1470 PREFIX_EVEX_0F72_REG_1
,
1471 PREFIX_EVEX_0F72_REG_2
,
1472 PREFIX_EVEX_0F72_REG_4
,
1473 PREFIX_EVEX_0F72_REG_6
,
1474 PREFIX_EVEX_0F73_REG_2
,
1475 PREFIX_EVEX_0F73_REG_3
,
1476 PREFIX_EVEX_0F73_REG_6
,
1477 PREFIX_EVEX_0F73_REG_7
,
1674 PREFIX_EVEX_0F38C6_REG_1
,
1675 PREFIX_EVEX_0F38C6_REG_2
,
1676 PREFIX_EVEX_0F38C6_REG_5
,
1677 PREFIX_EVEX_0F38C6_REG_6
,
1678 PREFIX_EVEX_0F38C7_REG_1
,
1679 PREFIX_EVEX_0F38C7_REG_2
,
1680 PREFIX_EVEX_0F38C7_REG_5
,
1681 PREFIX_EVEX_0F38C7_REG_6
,
1785 THREE_BYTE_0F38
= 0,
1812 VEX_LEN_0F12_P_0_M_0
= 0,
1813 VEX_LEN_0F12_P_0_M_1
,
1816 VEX_LEN_0F16_P_0_M_0
,
1817 VEX_LEN_0F16_P_0_M_1
,
1854 VEX_LEN_0FAE_R_2_M_0
,
1855 VEX_LEN_0FAE_R_3_M_0
,
1862 VEX_LEN_0F381A_P_2_M_0
,
1865 VEX_LEN_0F385A_P_2_M_0
,
1868 VEX_LEN_0F38F3_R_1_P_0
,
1869 VEX_LEN_0F38F3_R_2_P_0
,
1870 VEX_LEN_0F38F3_R_3_P_0
,
1913 VEX_LEN_0FXOP_08_CC
,
1914 VEX_LEN_0FXOP_08_CD
,
1915 VEX_LEN_0FXOP_08_CE
,
1916 VEX_LEN_0FXOP_08_CF
,
1917 VEX_LEN_0FXOP_08_EC
,
1918 VEX_LEN_0FXOP_08_ED
,
1919 VEX_LEN_0FXOP_08_EE
,
1920 VEX_LEN_0FXOP_08_EF
,
1921 VEX_LEN_0FXOP_09_80
,
1927 EVEX_LEN_0F6E_P_2
= 0,
1931 EVEX_LEN_0F3819_P_2_W_0
,
1932 EVEX_LEN_0F3819_P_2_W_1
,
1933 EVEX_LEN_0F381A_P_2_W_0
,
1934 EVEX_LEN_0F381A_P_2_W_1
,
1935 EVEX_LEN_0F381B_P_2_W_0
,
1936 EVEX_LEN_0F381B_P_2_W_1
,
1937 EVEX_LEN_0F385A_P_2_W_0
,
1938 EVEX_LEN_0F385A_P_2_W_1
,
1939 EVEX_LEN_0F385B_P_2_W_0
,
1940 EVEX_LEN_0F385B_P_2_W_1
,
1941 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1942 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1943 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1944 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1945 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1946 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1947 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1948 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1949 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1950 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1951 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1952 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1953 EVEX_LEN_0F3A18_P_2_W_0
,
1954 EVEX_LEN_0F3A18_P_2_W_1
,
1955 EVEX_LEN_0F3A19_P_2_W_0
,
1956 EVEX_LEN_0F3A19_P_2_W_1
,
1957 EVEX_LEN_0F3A1A_P_2_W_0
,
1958 EVEX_LEN_0F3A1A_P_2_W_1
,
1959 EVEX_LEN_0F3A1B_P_2_W_0
,
1960 EVEX_LEN_0F3A1B_P_2_W_1
,
1961 EVEX_LEN_0F3A23_P_2_W_0
,
1962 EVEX_LEN_0F3A23_P_2_W_1
,
1963 EVEX_LEN_0F3A38_P_2_W_0
,
1964 EVEX_LEN_0F3A38_P_2_W_1
,
1965 EVEX_LEN_0F3A39_P_2_W_0
,
1966 EVEX_LEN_0F3A39_P_2_W_1
,
1967 EVEX_LEN_0F3A3A_P_2_W_0
,
1968 EVEX_LEN_0F3A3A_P_2_W_1
,
1969 EVEX_LEN_0F3A3B_P_2_W_0
,
1970 EVEX_LEN_0F3A3B_P_2_W_1
,
1971 EVEX_LEN_0F3A43_P_2_W_0
,
1972 EVEX_LEN_0F3A43_P_2_W_1
1977 VEX_W_0F41_P_0_LEN_1
= 0,
1978 VEX_W_0F41_P_2_LEN_1
,
1979 VEX_W_0F42_P_0_LEN_1
,
1980 VEX_W_0F42_P_2_LEN_1
,
1981 VEX_W_0F44_P_0_LEN_0
,
1982 VEX_W_0F44_P_2_LEN_0
,
1983 VEX_W_0F45_P_0_LEN_1
,
1984 VEX_W_0F45_P_2_LEN_1
,
1985 VEX_W_0F46_P_0_LEN_1
,
1986 VEX_W_0F46_P_2_LEN_1
,
1987 VEX_W_0F47_P_0_LEN_1
,
1988 VEX_W_0F47_P_2_LEN_1
,
1989 VEX_W_0F4A_P_0_LEN_1
,
1990 VEX_W_0F4A_P_2_LEN_1
,
1991 VEX_W_0F4B_P_0_LEN_1
,
1992 VEX_W_0F4B_P_2_LEN_1
,
1993 VEX_W_0F90_P_0_LEN_0
,
1994 VEX_W_0F90_P_2_LEN_0
,
1995 VEX_W_0F91_P_0_LEN_0
,
1996 VEX_W_0F91_P_2_LEN_0
,
1997 VEX_W_0F92_P_0_LEN_0
,
1998 VEX_W_0F92_P_2_LEN_0
,
1999 VEX_W_0F93_P_0_LEN_0
,
2000 VEX_W_0F93_P_2_LEN_0
,
2001 VEX_W_0F98_P_0_LEN_0
,
2002 VEX_W_0F98_P_2_LEN_0
,
2003 VEX_W_0F99_P_0_LEN_0
,
2004 VEX_W_0F99_P_2_LEN_0
,
2012 VEX_W_0F381A_P_2_M_0
,
2013 VEX_W_0F382C_P_2_M_0
,
2014 VEX_W_0F382D_P_2_M_0
,
2015 VEX_W_0F382E_P_2_M_0
,
2016 VEX_W_0F382F_P_2_M_0
,
2021 VEX_W_0F385A_P_2_M_0
,
2033 VEX_W_0F3A30_P_2_LEN_0
,
2034 VEX_W_0F3A31_P_2_LEN_0
,
2035 VEX_W_0F3A32_P_2_LEN_0
,
2036 VEX_W_0F3A33_P_2_LEN_0
,
2056 EVEX_W_0F12_P_0_M_0
,
2057 EVEX_W_0F12_P_0_M_1
,
2067 EVEX_W_0F16_P_0_M_0
,
2068 EVEX_W_0F16_P_0_M_1
,
2137 EVEX_W_0F72_R_2_P_2
,
2138 EVEX_W_0F72_R_6_P_2
,
2139 EVEX_W_0F73_R_2_P_2
,
2140 EVEX_W_0F73_R_6_P_2
,
2250 EVEX_W_0F38C7_R_1_P_2
,
2251 EVEX_W_0F38C7_R_2_P_2
,
2252 EVEX_W_0F38C7_R_5_P_2
,
2253 EVEX_W_0F38C7_R_6_P_2
,
2292 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2301 unsigned int prefix_requirement
;
2304 /* Upper case letters in the instruction names here are macros.
2305 'A' => print 'b' if no register operands or suffix_always is true
2306 'B' => print 'b' if suffix_always is true
2307 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2309 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2310 suffix_always is true
2311 'E' => print 'e' if 32-bit form of jcxz
2312 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2313 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2314 'H' => print ",pt" or ",pn" branch hint
2315 'I' => honor following macro letter even in Intel mode (implemented only
2316 for some of the macro letters)
2318 'K' => print 'd' or 'q' if rex prefix is present.
2319 'L' => print 'l' if suffix_always is true
2320 'M' => print 'r' if intel_mnemonic is false.
2321 'N' => print 'n' if instruction has no wait "prefix"
2322 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2323 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2324 or suffix_always is true. print 'q' if rex prefix is present.
2325 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2327 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2328 'S' => print 'w', 'l' or 'q' if suffix_always is true
2329 'T' => print 'q' in 64bit mode if instruction has no operand size
2330 prefix and behave as 'P' otherwise
2331 'U' => print 'q' in 64bit mode if instruction has no operand size
2332 prefix and behave as 'Q' otherwise
2333 'V' => print 'q' in 64bit mode if instruction has no operand size
2334 prefix and behave as 'S' otherwise
2335 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2336 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2338 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2339 '!' => change condition from true to false or from false to true.
2340 '%' => add 1 upper case letter to the macro.
2341 '^' => print 'w' or 'l' depending on operand size prefix or
2342 suffix_always is true (lcall/ljmp).
2343 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2344 on operand size prefix.
2345 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2346 has no operand size prefix for AMD64 ISA, behave as 'P'
2349 2 upper case letter macros:
2350 "XY" => print 'x' or 'y' if suffix_always is true or no register
2351 operands and no broadcast.
2352 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2353 register operands and no broadcast.
2354 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2355 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2356 or suffix_always is true
2357 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2358 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2359 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2360 "LW" => print 'd', 'q' depending on the VEX.W bit
2361 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2362 an operand size prefix, or suffix_always is true. print
2363 'q' if rex prefix is present.
2365 Many of the above letters print nothing in Intel mode. See "putop"
2368 Braces '{' and '}', and vertical bars '|', indicate alternative
2369 mnemonic strings for AT&T and Intel. */
2371 static const struct dis386 dis386
[] = {
2373 { "addB", { Ebh1
, Gb
}, 0 },
2374 { "addS", { Evh1
, Gv
}, 0 },
2375 { "addB", { Gb
, EbS
}, 0 },
2376 { "addS", { Gv
, EvS
}, 0 },
2377 { "addB", { AL
, Ib
}, 0 },
2378 { "addS", { eAX
, Iv
}, 0 },
2379 { X86_64_TABLE (X86_64_06
) },
2380 { X86_64_TABLE (X86_64_07
) },
2382 { "orB", { Ebh1
, Gb
}, 0 },
2383 { "orS", { Evh1
, Gv
}, 0 },
2384 { "orB", { Gb
, EbS
}, 0 },
2385 { "orS", { Gv
, EvS
}, 0 },
2386 { "orB", { AL
, Ib
}, 0 },
2387 { "orS", { eAX
, Iv
}, 0 },
2388 { X86_64_TABLE (X86_64_0D
) },
2389 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2391 { "adcB", { Ebh1
, Gb
}, 0 },
2392 { "adcS", { Evh1
, Gv
}, 0 },
2393 { "adcB", { Gb
, EbS
}, 0 },
2394 { "adcS", { Gv
, EvS
}, 0 },
2395 { "adcB", { AL
, Ib
}, 0 },
2396 { "adcS", { eAX
, Iv
}, 0 },
2397 { X86_64_TABLE (X86_64_16
) },
2398 { X86_64_TABLE (X86_64_17
) },
2400 { "sbbB", { Ebh1
, Gb
}, 0 },
2401 { "sbbS", { Evh1
, Gv
}, 0 },
2402 { "sbbB", { Gb
, EbS
}, 0 },
2403 { "sbbS", { Gv
, EvS
}, 0 },
2404 { "sbbB", { AL
, Ib
}, 0 },
2405 { "sbbS", { eAX
, Iv
}, 0 },
2406 { X86_64_TABLE (X86_64_1E
) },
2407 { X86_64_TABLE (X86_64_1F
) },
2409 { "andB", { Ebh1
, Gb
}, 0 },
2410 { "andS", { Evh1
, Gv
}, 0 },
2411 { "andB", { Gb
, EbS
}, 0 },
2412 { "andS", { Gv
, EvS
}, 0 },
2413 { "andB", { AL
, Ib
}, 0 },
2414 { "andS", { eAX
, Iv
}, 0 },
2415 { Bad_Opcode
}, /* SEG ES prefix */
2416 { X86_64_TABLE (X86_64_27
) },
2418 { "subB", { Ebh1
, Gb
}, 0 },
2419 { "subS", { Evh1
, Gv
}, 0 },
2420 { "subB", { Gb
, EbS
}, 0 },
2421 { "subS", { Gv
, EvS
}, 0 },
2422 { "subB", { AL
, Ib
}, 0 },
2423 { "subS", { eAX
, Iv
}, 0 },
2424 { Bad_Opcode
}, /* SEG CS prefix */
2425 { X86_64_TABLE (X86_64_2F
) },
2427 { "xorB", { Ebh1
, Gb
}, 0 },
2428 { "xorS", { Evh1
, Gv
}, 0 },
2429 { "xorB", { Gb
, EbS
}, 0 },
2430 { "xorS", { Gv
, EvS
}, 0 },
2431 { "xorB", { AL
, Ib
}, 0 },
2432 { "xorS", { eAX
, Iv
}, 0 },
2433 { Bad_Opcode
}, /* SEG SS prefix */
2434 { X86_64_TABLE (X86_64_37
) },
2436 { "cmpB", { Eb
, Gb
}, 0 },
2437 { "cmpS", { Ev
, Gv
}, 0 },
2438 { "cmpB", { Gb
, EbS
}, 0 },
2439 { "cmpS", { Gv
, EvS
}, 0 },
2440 { "cmpB", { AL
, Ib
}, 0 },
2441 { "cmpS", { eAX
, Iv
}, 0 },
2442 { Bad_Opcode
}, /* SEG DS prefix */
2443 { X86_64_TABLE (X86_64_3F
) },
2445 { "inc{S|}", { RMeAX
}, 0 },
2446 { "inc{S|}", { RMeCX
}, 0 },
2447 { "inc{S|}", { RMeDX
}, 0 },
2448 { "inc{S|}", { RMeBX
}, 0 },
2449 { "inc{S|}", { RMeSP
}, 0 },
2450 { "inc{S|}", { RMeBP
}, 0 },
2451 { "inc{S|}", { RMeSI
}, 0 },
2452 { "inc{S|}", { RMeDI
}, 0 },
2454 { "dec{S|}", { RMeAX
}, 0 },
2455 { "dec{S|}", { RMeCX
}, 0 },
2456 { "dec{S|}", { RMeDX
}, 0 },
2457 { "dec{S|}", { RMeBX
}, 0 },
2458 { "dec{S|}", { RMeSP
}, 0 },
2459 { "dec{S|}", { RMeBP
}, 0 },
2460 { "dec{S|}", { RMeSI
}, 0 },
2461 { "dec{S|}", { RMeDI
}, 0 },
2463 { "pushV", { RMrAX
}, 0 },
2464 { "pushV", { RMrCX
}, 0 },
2465 { "pushV", { RMrDX
}, 0 },
2466 { "pushV", { RMrBX
}, 0 },
2467 { "pushV", { RMrSP
}, 0 },
2468 { "pushV", { RMrBP
}, 0 },
2469 { "pushV", { RMrSI
}, 0 },
2470 { "pushV", { RMrDI
}, 0 },
2472 { "popV", { RMrAX
}, 0 },
2473 { "popV", { RMrCX
}, 0 },
2474 { "popV", { RMrDX
}, 0 },
2475 { "popV", { RMrBX
}, 0 },
2476 { "popV", { RMrSP
}, 0 },
2477 { "popV", { RMrBP
}, 0 },
2478 { "popV", { RMrSI
}, 0 },
2479 { "popV", { RMrDI
}, 0 },
2481 { X86_64_TABLE (X86_64_60
) },
2482 { X86_64_TABLE (X86_64_61
) },
2483 { X86_64_TABLE (X86_64_62
) },
2484 { X86_64_TABLE (X86_64_63
) },
2485 { Bad_Opcode
}, /* seg fs */
2486 { Bad_Opcode
}, /* seg gs */
2487 { Bad_Opcode
}, /* op size prefix */
2488 { Bad_Opcode
}, /* adr size prefix */
2490 { "pushT", { sIv
}, 0 },
2491 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2492 { "pushT", { sIbT
}, 0 },
2493 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2494 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2495 { X86_64_TABLE (X86_64_6D
) },
2496 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2497 { X86_64_TABLE (X86_64_6F
) },
2499 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2500 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2501 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2502 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2503 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2504 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2505 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2506 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2508 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2509 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2510 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2511 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2512 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2513 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2514 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2515 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2517 { REG_TABLE (REG_80
) },
2518 { REG_TABLE (REG_81
) },
2519 { X86_64_TABLE (X86_64_82
) },
2520 { REG_TABLE (REG_83
) },
2521 { "testB", { Eb
, Gb
}, 0 },
2522 { "testS", { Ev
, Gv
}, 0 },
2523 { "xchgB", { Ebh2
, Gb
}, 0 },
2524 { "xchgS", { Evh2
, Gv
}, 0 },
2526 { "movB", { Ebh3
, Gb
}, 0 },
2527 { "movS", { Evh3
, Gv
}, 0 },
2528 { "movB", { Gb
, EbS
}, 0 },
2529 { "movS", { Gv
, EvS
}, 0 },
2530 { "movD", { Sv
, Sw
}, 0 },
2531 { MOD_TABLE (MOD_8D
) },
2532 { "movD", { Sw
, Sv
}, 0 },
2533 { REG_TABLE (REG_8F
) },
2535 { PREFIX_TABLE (PREFIX_90
) },
2536 { "xchgS", { RMeCX
, eAX
}, 0 },
2537 { "xchgS", { RMeDX
, eAX
}, 0 },
2538 { "xchgS", { RMeBX
, eAX
}, 0 },
2539 { "xchgS", { RMeSP
, eAX
}, 0 },
2540 { "xchgS", { RMeBP
, eAX
}, 0 },
2541 { "xchgS", { RMeSI
, eAX
}, 0 },
2542 { "xchgS", { RMeDI
, eAX
}, 0 },
2544 { "cW{t|}R", { XX
}, 0 },
2545 { "cR{t|}O", { XX
}, 0 },
2546 { X86_64_TABLE (X86_64_9A
) },
2547 { Bad_Opcode
}, /* fwait */
2548 { "pushfT", { XX
}, 0 },
2549 { "popfT", { XX
}, 0 },
2550 { "sahf", { XX
}, 0 },
2551 { "lahf", { XX
}, 0 },
2553 { "mov%LB", { AL
, Ob
}, 0 },
2554 { "mov%LS", { eAX
, Ov
}, 0 },
2555 { "mov%LB", { Ob
, AL
}, 0 },
2556 { "mov%LS", { Ov
, eAX
}, 0 },
2557 { "movs{b|}", { Ybr
, Xb
}, 0 },
2558 { "movs{R|}", { Yvr
, Xv
}, 0 },
2559 { "cmps{b|}", { Xb
, Yb
}, 0 },
2560 { "cmps{R|}", { Xv
, Yv
}, 0 },
2562 { "testB", { AL
, Ib
}, 0 },
2563 { "testS", { eAX
, Iv
}, 0 },
2564 { "stosB", { Ybr
, AL
}, 0 },
2565 { "stosS", { Yvr
, eAX
}, 0 },
2566 { "lodsB", { ALr
, Xb
}, 0 },
2567 { "lodsS", { eAXr
, Xv
}, 0 },
2568 { "scasB", { AL
, Yb
}, 0 },
2569 { "scasS", { eAX
, Yv
}, 0 },
2571 { "movB", { RMAL
, Ib
}, 0 },
2572 { "movB", { RMCL
, Ib
}, 0 },
2573 { "movB", { RMDL
, Ib
}, 0 },
2574 { "movB", { RMBL
, Ib
}, 0 },
2575 { "movB", { RMAH
, Ib
}, 0 },
2576 { "movB", { RMCH
, Ib
}, 0 },
2577 { "movB", { RMDH
, Ib
}, 0 },
2578 { "movB", { RMBH
, Ib
}, 0 },
2580 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2581 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2582 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2583 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2584 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2585 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2586 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2587 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2589 { REG_TABLE (REG_C0
) },
2590 { REG_TABLE (REG_C1
) },
2591 { X86_64_TABLE (X86_64_C2
) },
2592 { X86_64_TABLE (X86_64_C3
) },
2593 { X86_64_TABLE (X86_64_C4
) },
2594 { X86_64_TABLE (X86_64_C5
) },
2595 { REG_TABLE (REG_C6
) },
2596 { REG_TABLE (REG_C7
) },
2598 { "enterT", { Iw
, Ib
}, 0 },
2599 { "leaveT", { XX
}, 0 },
2600 { "Jret{|f}P", { Iw
}, 0 },
2601 { "Jret{|f}P", { XX
}, 0 },
2602 { "int3", { XX
}, 0 },
2603 { "int", { Ib
}, 0 },
2604 { X86_64_TABLE (X86_64_CE
) },
2605 { "iret%LP", { XX
}, 0 },
2607 { REG_TABLE (REG_D0
) },
2608 { REG_TABLE (REG_D1
) },
2609 { REG_TABLE (REG_D2
) },
2610 { REG_TABLE (REG_D3
) },
2611 { X86_64_TABLE (X86_64_D4
) },
2612 { X86_64_TABLE (X86_64_D5
) },
2614 { "xlat", { DSBX
}, 0 },
2625 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2626 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2627 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2628 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2629 { "inB", { AL
, Ib
}, 0 },
2630 { "inG", { zAX
, Ib
}, 0 },
2631 { "outB", { Ib
, AL
}, 0 },
2632 { "outG", { Ib
, zAX
}, 0 },
2634 { X86_64_TABLE (X86_64_E8
) },
2635 { X86_64_TABLE (X86_64_E9
) },
2636 { X86_64_TABLE (X86_64_EA
) },
2637 { "jmp", { Jb
, BND
}, 0 },
2638 { "inB", { AL
, indirDX
}, 0 },
2639 { "inG", { zAX
, indirDX
}, 0 },
2640 { "outB", { indirDX
, AL
}, 0 },
2641 { "outG", { indirDX
, zAX
}, 0 },
2643 { Bad_Opcode
}, /* lock prefix */
2644 { "icebp", { XX
}, 0 },
2645 { Bad_Opcode
}, /* repne */
2646 { Bad_Opcode
}, /* repz */
2647 { "hlt", { XX
}, 0 },
2648 { "cmc", { XX
}, 0 },
2649 { REG_TABLE (REG_F6
) },
2650 { REG_TABLE (REG_F7
) },
2652 { "clc", { XX
}, 0 },
2653 { "stc", { XX
}, 0 },
2654 { "cli", { XX
}, 0 },
2655 { "sti", { XX
}, 0 },
2656 { "cld", { XX
}, 0 },
2657 { "std", { XX
}, 0 },
2658 { REG_TABLE (REG_FE
) },
2659 { REG_TABLE (REG_FF
) },
2662 static const struct dis386 dis386_twobyte
[] = {
2664 { REG_TABLE (REG_0F00
) },
2665 { REG_TABLE (REG_0F01
) },
2666 { "larS", { Gv
, Ew
}, 0 },
2667 { "lslS", { Gv
, Ew
}, 0 },
2669 { "syscall", { XX
}, 0 },
2670 { "clts", { XX
}, 0 },
2671 { "sysret%LP", { XX
}, 0 },
2673 { "invd", { XX
}, 0 },
2674 { PREFIX_TABLE (PREFIX_0F09
) },
2676 { "ud2", { XX
}, 0 },
2678 { REG_TABLE (REG_0F0D
) },
2679 { "femms", { XX
}, 0 },
2680 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2682 { PREFIX_TABLE (PREFIX_0F10
) },
2683 { PREFIX_TABLE (PREFIX_0F11
) },
2684 { PREFIX_TABLE (PREFIX_0F12
) },
2685 { MOD_TABLE (MOD_0F13
) },
2686 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2687 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2688 { PREFIX_TABLE (PREFIX_0F16
) },
2689 { MOD_TABLE (MOD_0F17
) },
2691 { REG_TABLE (REG_0F18
) },
2692 { "nopQ", { Ev
}, 0 },
2693 { PREFIX_TABLE (PREFIX_0F1A
) },
2694 { PREFIX_TABLE (PREFIX_0F1B
) },
2695 { PREFIX_TABLE (PREFIX_0F1C
) },
2696 { "nopQ", { Ev
}, 0 },
2697 { PREFIX_TABLE (PREFIX_0F1E
) },
2698 { "nopQ", { Ev
}, 0 },
2700 { "movZ", { Rm
, Cm
}, 0 },
2701 { "movZ", { Rm
, Dm
}, 0 },
2702 { "movZ", { Cm
, Rm
}, 0 },
2703 { "movZ", { Dm
, Rm
}, 0 },
2704 { MOD_TABLE (MOD_0F24
) },
2706 { MOD_TABLE (MOD_0F26
) },
2709 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2710 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2711 { PREFIX_TABLE (PREFIX_0F2A
) },
2712 { PREFIX_TABLE (PREFIX_0F2B
) },
2713 { PREFIX_TABLE (PREFIX_0F2C
) },
2714 { PREFIX_TABLE (PREFIX_0F2D
) },
2715 { PREFIX_TABLE (PREFIX_0F2E
) },
2716 { PREFIX_TABLE (PREFIX_0F2F
) },
2718 { "wrmsr", { XX
}, 0 },
2719 { "rdtsc", { XX
}, 0 },
2720 { "rdmsr", { XX
}, 0 },
2721 { "rdpmc", { XX
}, 0 },
2722 { "sysenter", { SEP
}, 0 },
2723 { "sysexit", { SEP
}, 0 },
2725 { "getsec", { XX
}, 0 },
2727 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2729 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2736 { "cmovoS", { Gv
, Ev
}, 0 },
2737 { "cmovnoS", { Gv
, Ev
}, 0 },
2738 { "cmovbS", { Gv
, Ev
}, 0 },
2739 { "cmovaeS", { Gv
, Ev
}, 0 },
2740 { "cmoveS", { Gv
, Ev
}, 0 },
2741 { "cmovneS", { Gv
, Ev
}, 0 },
2742 { "cmovbeS", { Gv
, Ev
}, 0 },
2743 { "cmovaS", { Gv
, Ev
}, 0 },
2745 { "cmovsS", { Gv
, Ev
}, 0 },
2746 { "cmovnsS", { Gv
, Ev
}, 0 },
2747 { "cmovpS", { Gv
, Ev
}, 0 },
2748 { "cmovnpS", { Gv
, Ev
}, 0 },
2749 { "cmovlS", { Gv
, Ev
}, 0 },
2750 { "cmovgeS", { Gv
, Ev
}, 0 },
2751 { "cmovleS", { Gv
, Ev
}, 0 },
2752 { "cmovgS", { Gv
, Ev
}, 0 },
2754 { MOD_TABLE (MOD_0F51
) },
2755 { PREFIX_TABLE (PREFIX_0F51
) },
2756 { PREFIX_TABLE (PREFIX_0F52
) },
2757 { PREFIX_TABLE (PREFIX_0F53
) },
2758 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2759 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2760 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2761 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2763 { PREFIX_TABLE (PREFIX_0F58
) },
2764 { PREFIX_TABLE (PREFIX_0F59
) },
2765 { PREFIX_TABLE (PREFIX_0F5A
) },
2766 { PREFIX_TABLE (PREFIX_0F5B
) },
2767 { PREFIX_TABLE (PREFIX_0F5C
) },
2768 { PREFIX_TABLE (PREFIX_0F5D
) },
2769 { PREFIX_TABLE (PREFIX_0F5E
) },
2770 { PREFIX_TABLE (PREFIX_0F5F
) },
2772 { PREFIX_TABLE (PREFIX_0F60
) },
2773 { PREFIX_TABLE (PREFIX_0F61
) },
2774 { PREFIX_TABLE (PREFIX_0F62
) },
2775 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2776 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2777 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2778 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2779 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2781 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2782 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2783 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2784 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2785 { PREFIX_TABLE (PREFIX_0F6C
) },
2786 { PREFIX_TABLE (PREFIX_0F6D
) },
2787 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2788 { PREFIX_TABLE (PREFIX_0F6F
) },
2790 { PREFIX_TABLE (PREFIX_0F70
) },
2791 { REG_TABLE (REG_0F71
) },
2792 { REG_TABLE (REG_0F72
) },
2793 { REG_TABLE (REG_0F73
) },
2794 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2795 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2796 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2797 { "emms", { XX
}, PREFIX_OPCODE
},
2799 { PREFIX_TABLE (PREFIX_0F78
) },
2800 { PREFIX_TABLE (PREFIX_0F79
) },
2803 { PREFIX_TABLE (PREFIX_0F7C
) },
2804 { PREFIX_TABLE (PREFIX_0F7D
) },
2805 { PREFIX_TABLE (PREFIX_0F7E
) },
2806 { PREFIX_TABLE (PREFIX_0F7F
) },
2808 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2809 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2810 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2811 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2812 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2813 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2814 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2815 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2817 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2818 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2819 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2820 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2821 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2822 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2823 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2824 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2826 { "seto", { Eb
}, 0 },
2827 { "setno", { Eb
}, 0 },
2828 { "setb", { Eb
}, 0 },
2829 { "setae", { Eb
}, 0 },
2830 { "sete", { Eb
}, 0 },
2831 { "setne", { Eb
}, 0 },
2832 { "setbe", { Eb
}, 0 },
2833 { "seta", { Eb
}, 0 },
2835 { "sets", { Eb
}, 0 },
2836 { "setns", { Eb
}, 0 },
2837 { "setp", { Eb
}, 0 },
2838 { "setnp", { Eb
}, 0 },
2839 { "setl", { Eb
}, 0 },
2840 { "setge", { Eb
}, 0 },
2841 { "setle", { Eb
}, 0 },
2842 { "setg", { Eb
}, 0 },
2844 { "pushT", { fs
}, 0 },
2845 { "popT", { fs
}, 0 },
2846 { "cpuid", { XX
}, 0 },
2847 { "btS", { Ev
, Gv
}, 0 },
2848 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2849 { "shldS", { Ev
, Gv
, CL
}, 0 },
2850 { REG_TABLE (REG_0FA6
) },
2851 { REG_TABLE (REG_0FA7
) },
2853 { "pushT", { gs
}, 0 },
2854 { "popT", { gs
}, 0 },
2855 { "rsm", { XX
}, 0 },
2856 { "btsS", { Evh1
, Gv
}, 0 },
2857 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2858 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2859 { REG_TABLE (REG_0FAE
) },
2860 { "imulS", { Gv
, Ev
}, 0 },
2862 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2863 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2864 { MOD_TABLE (MOD_0FB2
) },
2865 { "btrS", { Evh1
, Gv
}, 0 },
2866 { MOD_TABLE (MOD_0FB4
) },
2867 { MOD_TABLE (MOD_0FB5
) },
2868 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2869 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2871 { PREFIX_TABLE (PREFIX_0FB8
) },
2872 { "ud1S", { Gv
, Ev
}, 0 },
2873 { REG_TABLE (REG_0FBA
) },
2874 { "btcS", { Evh1
, Gv
}, 0 },
2875 { PREFIX_TABLE (PREFIX_0FBC
) },
2876 { PREFIX_TABLE (PREFIX_0FBD
) },
2877 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2878 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2880 { "xaddB", { Ebh1
, Gb
}, 0 },
2881 { "xaddS", { Evh1
, Gv
}, 0 },
2882 { PREFIX_TABLE (PREFIX_0FC2
) },
2883 { MOD_TABLE (MOD_0FC3
) },
2884 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2885 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2886 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2887 { REG_TABLE (REG_0FC7
) },
2889 { "bswap", { RMeAX
}, 0 },
2890 { "bswap", { RMeCX
}, 0 },
2891 { "bswap", { RMeDX
}, 0 },
2892 { "bswap", { RMeBX
}, 0 },
2893 { "bswap", { RMeSP
}, 0 },
2894 { "bswap", { RMeBP
}, 0 },
2895 { "bswap", { RMeSI
}, 0 },
2896 { "bswap", { RMeDI
}, 0 },
2898 { PREFIX_TABLE (PREFIX_0FD0
) },
2899 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2900 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2901 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2902 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2903 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2904 { PREFIX_TABLE (PREFIX_0FD6
) },
2905 { MOD_TABLE (MOD_0FD7
) },
2907 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2908 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2909 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2910 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2911 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2912 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2913 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2914 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2916 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2917 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2918 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2919 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2920 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2921 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2922 { PREFIX_TABLE (PREFIX_0FE6
) },
2923 { PREFIX_TABLE (PREFIX_0FE7
) },
2925 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2926 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2927 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2928 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2929 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2930 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2931 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2932 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2934 { PREFIX_TABLE (PREFIX_0FF0
) },
2935 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2936 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2937 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2938 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2939 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2940 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2941 { PREFIX_TABLE (PREFIX_0FF7
) },
2943 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2944 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2945 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2946 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2947 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2948 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2949 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2950 { "ud0S", { Gv
, Ev
}, 0 },
2953 static const unsigned char onebyte_has_modrm
[256] = {
2954 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2955 /* ------------------------------- */
2956 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2957 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2958 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2959 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2960 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2961 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2962 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2963 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2964 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2965 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2966 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2967 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2968 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2969 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2970 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2971 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2972 /* ------------------------------- */
2973 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2976 static const unsigned char twobyte_has_modrm
[256] = {
2977 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2978 /* ------------------------------- */
2979 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2980 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2981 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2982 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2983 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2984 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2985 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2986 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2987 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2988 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2989 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2990 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2991 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2992 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2993 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2994 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2995 /* ------------------------------- */
2996 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2999 static char obuf
[100];
3001 static char *mnemonicendp
;
3002 static char scratchbuf
[100];
3003 static unsigned char *start_codep
;
3004 static unsigned char *insn_codep
;
3005 static unsigned char *codep
;
3006 static unsigned char *end_codep
;
3007 static int last_lock_prefix
;
3008 static int last_repz_prefix
;
3009 static int last_repnz_prefix
;
3010 static int last_data_prefix
;
3011 static int last_addr_prefix
;
3012 static int last_rex_prefix
;
3013 static int last_seg_prefix
;
3014 static int fwait_prefix
;
3015 /* The active segment register prefix. */
3016 static int active_seg_prefix
;
3017 #define MAX_CODE_LENGTH 15
3018 /* We can up to 14 prefixes since the maximum instruction length is
3020 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3021 static disassemble_info
*the_info
;
3029 static unsigned char need_modrm
;
3039 int register_specifier
;
3046 int mask_register_specifier
;
3052 static unsigned char need_vex
;
3053 static unsigned char need_vex_reg
;
3054 static unsigned char vex_w_done
;
3062 /* If we are accessing mod/rm/reg without need_modrm set, then the
3063 values are stale. Hitting this abort likely indicates that you
3064 need to update onebyte_has_modrm or twobyte_has_modrm. */
3065 #define MODRM_CHECK if (!need_modrm) abort ()
3067 static const char **names64
;
3068 static const char **names32
;
3069 static const char **names16
;
3070 static const char **names8
;
3071 static const char **names8rex
;
3072 static const char **names_seg
;
3073 static const char *index64
;
3074 static const char *index32
;
3075 static const char **index16
;
3076 static const char **names_bnd
;
3078 static const char *intel_names64
[] = {
3079 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3080 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3082 static const char *intel_names32
[] = {
3083 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3084 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3086 static const char *intel_names16
[] = {
3087 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3088 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3090 static const char *intel_names8
[] = {
3091 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3093 static const char *intel_names8rex
[] = {
3094 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3095 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3097 static const char *intel_names_seg
[] = {
3098 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3100 static const char *intel_index64
= "riz";
3101 static const char *intel_index32
= "eiz";
3102 static const char *intel_index16
[] = {
3103 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3106 static const char *att_names64
[] = {
3107 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3108 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3110 static const char *att_names32
[] = {
3111 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3112 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3114 static const char *att_names16
[] = {
3115 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3116 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3118 static const char *att_names8
[] = {
3119 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3121 static const char *att_names8rex
[] = {
3122 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3123 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3125 static const char *att_names_seg
[] = {
3126 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3128 static const char *att_index64
= "%riz";
3129 static const char *att_index32
= "%eiz";
3130 static const char *att_index16
[] = {
3131 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3134 static const char **names_mm
;
3135 static const char *intel_names_mm
[] = {
3136 "mm0", "mm1", "mm2", "mm3",
3137 "mm4", "mm5", "mm6", "mm7"
3139 static const char *att_names_mm
[] = {
3140 "%mm0", "%mm1", "%mm2", "%mm3",
3141 "%mm4", "%mm5", "%mm6", "%mm7"
3144 static const char *intel_names_bnd
[] = {
3145 "bnd0", "bnd1", "bnd2", "bnd3"
3148 static const char *att_names_bnd
[] = {
3149 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3152 static const char **names_xmm
;
3153 static const char *intel_names_xmm
[] = {
3154 "xmm0", "xmm1", "xmm2", "xmm3",
3155 "xmm4", "xmm5", "xmm6", "xmm7",
3156 "xmm8", "xmm9", "xmm10", "xmm11",
3157 "xmm12", "xmm13", "xmm14", "xmm15",
3158 "xmm16", "xmm17", "xmm18", "xmm19",
3159 "xmm20", "xmm21", "xmm22", "xmm23",
3160 "xmm24", "xmm25", "xmm26", "xmm27",
3161 "xmm28", "xmm29", "xmm30", "xmm31"
3163 static const char *att_names_xmm
[] = {
3164 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3165 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3166 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3167 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3168 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3169 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3170 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3171 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3174 static const char **names_ymm
;
3175 static const char *intel_names_ymm
[] = {
3176 "ymm0", "ymm1", "ymm2", "ymm3",
3177 "ymm4", "ymm5", "ymm6", "ymm7",
3178 "ymm8", "ymm9", "ymm10", "ymm11",
3179 "ymm12", "ymm13", "ymm14", "ymm15",
3180 "ymm16", "ymm17", "ymm18", "ymm19",
3181 "ymm20", "ymm21", "ymm22", "ymm23",
3182 "ymm24", "ymm25", "ymm26", "ymm27",
3183 "ymm28", "ymm29", "ymm30", "ymm31"
3185 static const char *att_names_ymm
[] = {
3186 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3187 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3188 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3189 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3190 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3191 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3192 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3193 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3196 static const char **names_zmm
;
3197 static const char *intel_names_zmm
[] = {
3198 "zmm0", "zmm1", "zmm2", "zmm3",
3199 "zmm4", "zmm5", "zmm6", "zmm7",
3200 "zmm8", "zmm9", "zmm10", "zmm11",
3201 "zmm12", "zmm13", "zmm14", "zmm15",
3202 "zmm16", "zmm17", "zmm18", "zmm19",
3203 "zmm20", "zmm21", "zmm22", "zmm23",
3204 "zmm24", "zmm25", "zmm26", "zmm27",
3205 "zmm28", "zmm29", "zmm30", "zmm31"
3207 static const char *att_names_zmm
[] = {
3208 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3209 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3210 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3211 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3212 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3213 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3214 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3215 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3218 static const char **names_mask
;
3219 static const char *intel_names_mask
[] = {
3220 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3222 static const char *att_names_mask
[] = {
3223 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3226 static const char *names_rounding
[] =
3234 static const struct dis386 reg_table
[][8] = {
3237 { "addA", { Ebh1
, Ib
}, 0 },
3238 { "orA", { Ebh1
, Ib
}, 0 },
3239 { "adcA", { Ebh1
, Ib
}, 0 },
3240 { "sbbA", { Ebh1
, Ib
}, 0 },
3241 { "andA", { Ebh1
, Ib
}, 0 },
3242 { "subA", { Ebh1
, Ib
}, 0 },
3243 { "xorA", { Ebh1
, Ib
}, 0 },
3244 { "cmpA", { Eb
, Ib
}, 0 },
3248 { "addQ", { Evh1
, Iv
}, 0 },
3249 { "orQ", { Evh1
, Iv
}, 0 },
3250 { "adcQ", { Evh1
, Iv
}, 0 },
3251 { "sbbQ", { Evh1
, Iv
}, 0 },
3252 { "andQ", { Evh1
, Iv
}, 0 },
3253 { "subQ", { Evh1
, Iv
}, 0 },
3254 { "xorQ", { Evh1
, Iv
}, 0 },
3255 { "cmpQ", { Ev
, Iv
}, 0 },
3259 { "addQ", { Evh1
, sIb
}, 0 },
3260 { "orQ", { Evh1
, sIb
}, 0 },
3261 { "adcQ", { Evh1
, sIb
}, 0 },
3262 { "sbbQ", { Evh1
, sIb
}, 0 },
3263 { "andQ", { Evh1
, sIb
}, 0 },
3264 { "subQ", { Evh1
, sIb
}, 0 },
3265 { "xorQ", { Evh1
, sIb
}, 0 },
3266 { "cmpQ", { Ev
, sIb
}, 0 },
3270 { "popU", { stackEv
}, 0 },
3271 { XOP_8F_TABLE (XOP_09
) },
3275 { XOP_8F_TABLE (XOP_09
) },
3279 { "rolA", { Eb
, Ib
}, 0 },
3280 { "rorA", { Eb
, Ib
}, 0 },
3281 { "rclA", { Eb
, Ib
}, 0 },
3282 { "rcrA", { Eb
, Ib
}, 0 },
3283 { "shlA", { Eb
, Ib
}, 0 },
3284 { "shrA", { Eb
, Ib
}, 0 },
3285 { "shlA", { Eb
, Ib
}, 0 },
3286 { "sarA", { Eb
, Ib
}, 0 },
3290 { "rolQ", { Ev
, Ib
}, 0 },
3291 { "rorQ", { Ev
, Ib
}, 0 },
3292 { "rclQ", { Ev
, Ib
}, 0 },
3293 { "rcrQ", { Ev
, Ib
}, 0 },
3294 { "shlQ", { Ev
, Ib
}, 0 },
3295 { "shrQ", { Ev
, Ib
}, 0 },
3296 { "shlQ", { Ev
, Ib
}, 0 },
3297 { "sarQ", { Ev
, Ib
}, 0 },
3301 { "movA", { Ebh3
, Ib
}, 0 },
3308 { MOD_TABLE (MOD_C6_REG_7
) },
3312 { "movQ", { Evh3
, Iv
}, 0 },
3319 { MOD_TABLE (MOD_C7_REG_7
) },
3323 { "rolA", { Eb
, I1
}, 0 },
3324 { "rorA", { Eb
, I1
}, 0 },
3325 { "rclA", { Eb
, I1
}, 0 },
3326 { "rcrA", { Eb
, I1
}, 0 },
3327 { "shlA", { Eb
, I1
}, 0 },
3328 { "shrA", { Eb
, I1
}, 0 },
3329 { "shlA", { Eb
, I1
}, 0 },
3330 { "sarA", { Eb
, I1
}, 0 },
3334 { "rolQ", { Ev
, I1
}, 0 },
3335 { "rorQ", { Ev
, I1
}, 0 },
3336 { "rclQ", { Ev
, I1
}, 0 },
3337 { "rcrQ", { Ev
, I1
}, 0 },
3338 { "shlQ", { Ev
, I1
}, 0 },
3339 { "shrQ", { Ev
, I1
}, 0 },
3340 { "shlQ", { Ev
, I1
}, 0 },
3341 { "sarQ", { Ev
, I1
}, 0 },
3345 { "rolA", { Eb
, CL
}, 0 },
3346 { "rorA", { Eb
, CL
}, 0 },
3347 { "rclA", { Eb
, CL
}, 0 },
3348 { "rcrA", { Eb
, CL
}, 0 },
3349 { "shlA", { Eb
, CL
}, 0 },
3350 { "shrA", { Eb
, CL
}, 0 },
3351 { "shlA", { Eb
, CL
}, 0 },
3352 { "sarA", { Eb
, CL
}, 0 },
3356 { "rolQ", { Ev
, CL
}, 0 },
3357 { "rorQ", { Ev
, CL
}, 0 },
3358 { "rclQ", { Ev
, CL
}, 0 },
3359 { "rcrQ", { Ev
, CL
}, 0 },
3360 { "shlQ", { Ev
, CL
}, 0 },
3361 { "shrQ", { Ev
, CL
}, 0 },
3362 { "shlQ", { Ev
, CL
}, 0 },
3363 { "sarQ", { Ev
, CL
}, 0 },
3367 { "testA", { Eb
, Ib
}, 0 },
3368 { "testA", { Eb
, Ib
}, 0 },
3369 { "notA", { Ebh1
}, 0 },
3370 { "negA", { Ebh1
}, 0 },
3371 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3372 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3373 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3374 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3378 { "testQ", { Ev
, Iv
}, 0 },
3379 { "testQ", { Ev
, Iv
}, 0 },
3380 { "notQ", { Evh1
}, 0 },
3381 { "negQ", { Evh1
}, 0 },
3382 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3383 { "imulQ", { Ev
}, 0 },
3384 { "divQ", { Ev
}, 0 },
3385 { "idivQ", { Ev
}, 0 },
3389 { "incA", { Ebh1
}, 0 },
3390 { "decA", { Ebh1
}, 0 },
3394 { "incQ", { Evh1
}, 0 },
3395 { "decQ", { Evh1
}, 0 },
3396 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3397 { MOD_TABLE (MOD_FF_REG_3
) },
3398 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3399 { MOD_TABLE (MOD_FF_REG_5
) },
3400 { "pushU", { stackEv
}, 0 },
3405 { "sldtD", { Sv
}, 0 },
3406 { "strD", { Sv
}, 0 },
3407 { "lldt", { Ew
}, 0 },
3408 { "ltr", { Ew
}, 0 },
3409 { "verr", { Ew
}, 0 },
3410 { "verw", { Ew
}, 0 },
3416 { MOD_TABLE (MOD_0F01_REG_0
) },
3417 { MOD_TABLE (MOD_0F01_REG_1
) },
3418 { MOD_TABLE (MOD_0F01_REG_2
) },
3419 { MOD_TABLE (MOD_0F01_REG_3
) },
3420 { "smswD", { Sv
}, 0 },
3421 { MOD_TABLE (MOD_0F01_REG_5
) },
3422 { "lmsw", { Ew
}, 0 },
3423 { MOD_TABLE (MOD_0F01_REG_7
) },
3427 { "prefetch", { Mb
}, 0 },
3428 { "prefetchw", { Mb
}, 0 },
3429 { "prefetchwt1", { Mb
}, 0 },
3430 { "prefetch", { Mb
}, 0 },
3431 { "prefetch", { Mb
}, 0 },
3432 { "prefetch", { Mb
}, 0 },
3433 { "prefetch", { Mb
}, 0 },
3434 { "prefetch", { Mb
}, 0 },
3438 { MOD_TABLE (MOD_0F18_REG_0
) },
3439 { MOD_TABLE (MOD_0F18_REG_1
) },
3440 { MOD_TABLE (MOD_0F18_REG_2
) },
3441 { MOD_TABLE (MOD_0F18_REG_3
) },
3442 { MOD_TABLE (MOD_0F18_REG_4
) },
3443 { MOD_TABLE (MOD_0F18_REG_5
) },
3444 { MOD_TABLE (MOD_0F18_REG_6
) },
3445 { MOD_TABLE (MOD_0F18_REG_7
) },
3447 /* REG_0F1C_P_0_MOD_0 */
3449 { "cldemote", { Mb
}, 0 },
3450 { "nopQ", { Ev
}, 0 },
3451 { "nopQ", { Ev
}, 0 },
3452 { "nopQ", { Ev
}, 0 },
3453 { "nopQ", { Ev
}, 0 },
3454 { "nopQ", { Ev
}, 0 },
3455 { "nopQ", { Ev
}, 0 },
3456 { "nopQ", { Ev
}, 0 },
3458 /* REG_0F1E_P_1_MOD_3 */
3460 { "nopQ", { Ev
}, 0 },
3461 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3462 { "nopQ", { Ev
}, 0 },
3463 { "nopQ", { Ev
}, 0 },
3464 { "nopQ", { Ev
}, 0 },
3465 { "nopQ", { Ev
}, 0 },
3466 { "nopQ", { Ev
}, 0 },
3467 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
3473 { MOD_TABLE (MOD_0F71_REG_2
) },
3475 { MOD_TABLE (MOD_0F71_REG_4
) },
3477 { MOD_TABLE (MOD_0F71_REG_6
) },
3483 { MOD_TABLE (MOD_0F72_REG_2
) },
3485 { MOD_TABLE (MOD_0F72_REG_4
) },
3487 { MOD_TABLE (MOD_0F72_REG_6
) },
3493 { MOD_TABLE (MOD_0F73_REG_2
) },
3494 { MOD_TABLE (MOD_0F73_REG_3
) },
3497 { MOD_TABLE (MOD_0F73_REG_6
) },
3498 { MOD_TABLE (MOD_0F73_REG_7
) },
3502 { "montmul", { { OP_0f07
, 0 } }, 0 },
3503 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3504 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3508 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3509 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3510 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3511 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3512 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3513 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3517 { MOD_TABLE (MOD_0FAE_REG_0
) },
3518 { MOD_TABLE (MOD_0FAE_REG_1
) },
3519 { MOD_TABLE (MOD_0FAE_REG_2
) },
3520 { MOD_TABLE (MOD_0FAE_REG_3
) },
3521 { MOD_TABLE (MOD_0FAE_REG_4
) },
3522 { MOD_TABLE (MOD_0FAE_REG_5
) },
3523 { MOD_TABLE (MOD_0FAE_REG_6
) },
3524 { MOD_TABLE (MOD_0FAE_REG_7
) },
3532 { "btQ", { Ev
, Ib
}, 0 },
3533 { "btsQ", { Evh1
, Ib
}, 0 },
3534 { "btrQ", { Evh1
, Ib
}, 0 },
3535 { "btcQ", { Evh1
, Ib
}, 0 },
3540 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3542 { MOD_TABLE (MOD_0FC7_REG_3
) },
3543 { MOD_TABLE (MOD_0FC7_REG_4
) },
3544 { MOD_TABLE (MOD_0FC7_REG_5
) },
3545 { MOD_TABLE (MOD_0FC7_REG_6
) },
3546 { MOD_TABLE (MOD_0FC7_REG_7
) },
3552 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3554 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3556 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3562 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3564 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3566 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3572 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3573 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3576 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3577 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3583 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3584 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3586 /* REG_VEX_0F38F3 */
3589 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3590 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3591 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3595 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3596 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3600 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3601 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3603 /* REG_XOP_TBM_01 */
3606 { "blcfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3607 { "blsfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3608 { "blcs", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3609 { "tzmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3610 { "blcic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3611 { "blsic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3612 { "t1mskc", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3614 /* REG_XOP_TBM_02 */
3617 { "blcmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3622 { "blci", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3625 #include "i386-dis-evex-reg.h"
3628 static const struct dis386 prefix_table
[][4] = {
3631 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3632 { "pause", { XX
}, 0 },
3633 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3634 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3637 /* PREFIX_0F01_REG_5_MOD_0 */
3640 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3643 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3646 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3649 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3652 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3655 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3657 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3658 { "mcommit", { Skip_MODRM
}, 0 },
3661 /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3663 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, 0 },
3668 { "wbinvd", { XX
}, 0 },
3669 { "wbnoinvd", { XX
}, 0 },
3674 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3675 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3676 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3677 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3682 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3683 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3684 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3685 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3690 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3691 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3692 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3693 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3698 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3699 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3700 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3705 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3706 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3707 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3708 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3713 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3714 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3715 { "bndmov", { EbndS
, Gbnd
}, 0 },
3716 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3721 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3722 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3723 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3724 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3729 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3730 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3731 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3732 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3737 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3738 { "cvtsi2ss%LQ", { XM
, Edq
}, PREFIX_OPCODE
},
3739 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3740 { "cvtsi2sd%LQ", { XM
, Edq
}, 0 },
3745 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3746 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3747 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3748 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3753 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3754 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3755 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3756 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3761 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3762 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3763 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3764 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3769 { "ucomiss",{ XM
, EXd
}, 0 },
3771 { "ucomisd",{ XM
, EXq
}, 0 },
3776 { "comiss", { XM
, EXd
}, 0 },
3778 { "comisd", { XM
, EXq
}, 0 },
3783 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3784 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3785 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3786 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3791 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3792 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3797 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3798 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3803 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3804 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3805 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3806 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3811 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3812 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3813 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3814 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3819 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3820 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3821 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3822 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3827 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3828 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3829 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3834 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3835 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3836 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3837 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3842 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3843 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3844 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3845 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3850 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3851 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3852 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3853 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3858 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3859 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3860 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3861 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3866 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3868 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3873 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3875 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3880 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3882 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3889 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3896 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3901 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3902 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3903 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3908 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3909 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3910 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3911 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3914 /* PREFIX_0F73_REG_3 */
3918 { "psrldq", { XS
, Ib
}, 0 },
3921 /* PREFIX_0F73_REG_7 */
3925 { "pslldq", { XS
, Ib
}, 0 },
3930 {"vmread", { Em
, Gm
}, 0 },
3932 {"extrq", { XS
, Ib
, Ib
}, 0 },
3933 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3938 {"vmwrite", { Gm
, Em
}, 0 },
3940 {"extrq", { XM
, XS
}, 0 },
3941 {"insertq", { XM
, XS
}, 0 },
3948 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3949 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3956 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3957 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3962 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3963 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3964 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3969 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3970 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3971 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3974 /* PREFIX_0FAE_REG_0_MOD_3 */
3977 { "rdfsbase", { Ev
}, 0 },
3980 /* PREFIX_0FAE_REG_1_MOD_3 */
3983 { "rdgsbase", { Ev
}, 0 },
3986 /* PREFIX_0FAE_REG_2_MOD_3 */
3989 { "wrfsbase", { Ev
}, 0 },
3992 /* PREFIX_0FAE_REG_3_MOD_3 */
3995 { "wrgsbase", { Ev
}, 0 },
3998 /* PREFIX_0FAE_REG_4_MOD_0 */
4000 { "xsave", { FXSAVE
}, 0 },
4001 { "ptwrite%LQ", { Edq
}, 0 },
4004 /* PREFIX_0FAE_REG_4_MOD_3 */
4007 { "ptwrite%LQ", { Edq
}, 0 },
4010 /* PREFIX_0FAE_REG_5_MOD_0 */
4012 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
4015 /* PREFIX_0FAE_REG_5_MOD_3 */
4017 { "lfence", { Skip_MODRM
}, 0 },
4018 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
4021 /* PREFIX_0FAE_REG_6_MOD_0 */
4023 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
4024 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
4025 { "clwb", { Mb
}, PREFIX_OPCODE
},
4028 /* PREFIX_0FAE_REG_6_MOD_3 */
4030 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
4031 { "umonitor", { Eva
}, PREFIX_OPCODE
},
4032 { "tpause", { Edq
}, PREFIX_OPCODE
},
4033 { "umwait", { Edq
}, PREFIX_OPCODE
},
4036 /* PREFIX_0FAE_REG_7_MOD_0 */
4038 { "clflush", { Mb
}, 0 },
4040 { "clflushopt", { Mb
}, 0 },
4046 { "popcntS", { Gv
, Ev
}, 0 },
4051 { "bsfS", { Gv
, Ev
}, 0 },
4052 { "tzcntS", { Gv
, Ev
}, 0 },
4053 { "bsfS", { Gv
, Ev
}, 0 },
4058 { "bsrS", { Gv
, Ev
}, 0 },
4059 { "lzcntS", { Gv
, Ev
}, 0 },
4060 { "bsrS", { Gv
, Ev
}, 0 },
4065 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4066 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4067 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4068 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4071 /* PREFIX_0FC3_MOD_0 */
4073 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
4076 /* PREFIX_0FC7_REG_6_MOD_0 */
4078 { "vmptrld",{ Mq
}, 0 },
4079 { "vmxon", { Mq
}, 0 },
4080 { "vmclear",{ Mq
}, 0 },
4083 /* PREFIX_0FC7_REG_6_MOD_3 */
4085 { "rdrand", { Ev
}, 0 },
4087 { "rdrand", { Ev
}, 0 }
4090 /* PREFIX_0FC7_REG_7_MOD_3 */
4092 { "rdseed", { Ev
}, 0 },
4093 { "rdpid", { Em
}, 0 },
4094 { "rdseed", { Ev
}, 0 },
4101 { "addsubpd", { XM
, EXx
}, 0 },
4102 { "addsubps", { XM
, EXx
}, 0 },
4108 { "movq2dq",{ XM
, MS
}, 0 },
4109 { "movq", { EXqS
, XM
}, 0 },
4110 { "movdq2q",{ MX
, XS
}, 0 },
4116 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4117 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4118 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4123 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4125 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4133 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4138 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4140 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4147 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4154 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4161 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4168 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4175 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4182 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4189 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4196 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4203 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4210 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4217 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4224 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4231 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4238 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4245 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4252 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4259 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4266 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4273 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4280 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4287 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4294 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4301 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4308 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4315 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4322 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4329 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4336 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4343 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4350 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4357 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4364 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4371 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4378 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4383 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4388 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4393 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4398 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4403 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4408 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4415 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4422 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4429 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4436 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4443 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4450 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4455 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4457 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4458 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4463 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4465 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4466 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4473 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4478 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4479 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4480 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4487 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4488 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4489 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4494 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4501 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4508 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4515 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4522 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4529 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4536 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4543 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4550 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4557 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4564 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4571 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4578 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4585 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4592 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4599 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4606 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4613 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4620 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4627 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4634 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4641 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4648 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4653 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4660 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4667 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4674 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4677 /* PREFIX_VEX_0F10 */
4679 { "vmovups", { XM
, EXx
}, 0 },
4680 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
4681 { "vmovupd", { XM
, EXx
}, 0 },
4682 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
4685 /* PREFIX_VEX_0F11 */
4687 { "vmovups", { EXxS
, XM
}, 0 },
4688 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4689 { "vmovupd", { EXxS
, XM
}, 0 },
4690 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4693 /* PREFIX_VEX_0F12 */
4695 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4696 { "vmovsldup", { XM
, EXx
}, 0 },
4697 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4698 { "vmovddup", { XM
, EXymmq
}, 0 },
4701 /* PREFIX_VEX_0F16 */
4703 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4704 { "vmovshdup", { XM
, EXx
}, 0 },
4705 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4708 /* PREFIX_VEX_0F2A */
4711 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4713 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4716 /* PREFIX_VEX_0F2C */
4719 { "vcvttss2si", { Gdq
, EXdScalar
}, 0 },
4721 { "vcvttsd2si", { Gdq
, EXqScalar
}, 0 },
4724 /* PREFIX_VEX_0F2D */
4727 { "vcvtss2si", { Gdq
, EXdScalar
}, 0 },
4729 { "vcvtsd2si", { Gdq
, EXqScalar
}, 0 },
4732 /* PREFIX_VEX_0F2E */
4734 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
4736 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
4739 /* PREFIX_VEX_0F2F */
4741 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
4743 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
4746 /* PREFIX_VEX_0F41 */
4748 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4750 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4753 /* PREFIX_VEX_0F42 */
4755 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4757 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4760 /* PREFIX_VEX_0F44 */
4762 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4764 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4767 /* PREFIX_VEX_0F45 */
4769 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4771 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4774 /* PREFIX_VEX_0F46 */
4776 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4778 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4781 /* PREFIX_VEX_0F47 */
4783 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4785 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4788 /* PREFIX_VEX_0F4A */
4790 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4792 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4795 /* PREFIX_VEX_0F4B */
4797 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4799 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4802 /* PREFIX_VEX_0F51 */
4804 { "vsqrtps", { XM
, EXx
}, 0 },
4805 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4806 { "vsqrtpd", { XM
, EXx
}, 0 },
4807 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4810 /* PREFIX_VEX_0F52 */
4812 { "vrsqrtps", { XM
, EXx
}, 0 },
4813 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4816 /* PREFIX_VEX_0F53 */
4818 { "vrcpps", { XM
, EXx
}, 0 },
4819 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4822 /* PREFIX_VEX_0F58 */
4824 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4825 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4826 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4827 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4830 /* PREFIX_VEX_0F59 */
4832 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4833 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4834 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4835 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4838 /* PREFIX_VEX_0F5A */
4840 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4841 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4842 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4843 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4846 /* PREFIX_VEX_0F5B */
4848 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4849 { "vcvttps2dq", { XM
, EXx
}, 0 },
4850 { "vcvtps2dq", { XM
, EXx
}, 0 },
4853 /* PREFIX_VEX_0F5C */
4855 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4856 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4857 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4858 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4861 /* PREFIX_VEX_0F5D */
4863 { "vminps", { XM
, Vex
, EXx
}, 0 },
4864 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4865 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4866 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4869 /* PREFIX_VEX_0F5E */
4871 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4872 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4873 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4874 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4877 /* PREFIX_VEX_0F5F */
4879 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4880 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4881 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4882 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4885 /* PREFIX_VEX_0F60 */
4889 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4892 /* PREFIX_VEX_0F61 */
4896 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4899 /* PREFIX_VEX_0F62 */
4903 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4906 /* PREFIX_VEX_0F63 */
4910 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4913 /* PREFIX_VEX_0F64 */
4917 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4920 /* PREFIX_VEX_0F65 */
4924 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4927 /* PREFIX_VEX_0F66 */
4931 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4934 /* PREFIX_VEX_0F67 */
4938 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4941 /* PREFIX_VEX_0F68 */
4945 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4948 /* PREFIX_VEX_0F69 */
4952 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4955 /* PREFIX_VEX_0F6A */
4959 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4962 /* PREFIX_VEX_0F6B */
4966 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4969 /* PREFIX_VEX_0F6C */
4973 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4976 /* PREFIX_VEX_0F6D */
4980 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4983 /* PREFIX_VEX_0F6E */
4987 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4990 /* PREFIX_VEX_0F6F */
4993 { "vmovdqu", { XM
, EXx
}, 0 },
4994 { "vmovdqa", { XM
, EXx
}, 0 },
4997 /* PREFIX_VEX_0F70 */
5000 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
5001 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
5002 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
5005 /* PREFIX_VEX_0F71_REG_2 */
5009 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
5012 /* PREFIX_VEX_0F71_REG_4 */
5016 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
5019 /* PREFIX_VEX_0F71_REG_6 */
5023 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
5026 /* PREFIX_VEX_0F72_REG_2 */
5030 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
5033 /* PREFIX_VEX_0F72_REG_4 */
5037 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
5040 /* PREFIX_VEX_0F72_REG_6 */
5044 { "vpslld", { Vex
, XS
, Ib
}, 0 },
5047 /* PREFIX_VEX_0F73_REG_2 */
5051 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5054 /* PREFIX_VEX_0F73_REG_3 */
5058 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5061 /* PREFIX_VEX_0F73_REG_6 */
5065 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5068 /* PREFIX_VEX_0F73_REG_7 */
5072 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5075 /* PREFIX_VEX_0F74 */
5079 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5082 /* PREFIX_VEX_0F75 */
5086 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5089 /* PREFIX_VEX_0F76 */
5093 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5096 /* PREFIX_VEX_0F77 */
5098 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5101 /* PREFIX_VEX_0F7C */
5105 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5106 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5109 /* PREFIX_VEX_0F7D */
5113 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5114 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5117 /* PREFIX_VEX_0F7E */
5120 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5121 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5124 /* PREFIX_VEX_0F7F */
5127 { "vmovdqu", { EXxS
, XM
}, 0 },
5128 { "vmovdqa", { EXxS
, XM
}, 0 },
5131 /* PREFIX_VEX_0F90 */
5133 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5135 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5138 /* PREFIX_VEX_0F91 */
5140 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5142 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5145 /* PREFIX_VEX_0F92 */
5147 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5149 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5150 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5153 /* PREFIX_VEX_0F93 */
5155 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5157 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5158 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5161 /* PREFIX_VEX_0F98 */
5163 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5165 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5168 /* PREFIX_VEX_0F99 */
5170 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5172 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5175 /* PREFIX_VEX_0FC2 */
5177 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5178 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
5179 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5180 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
5183 /* PREFIX_VEX_0FC4 */
5187 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5190 /* PREFIX_VEX_0FC5 */
5194 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5197 /* PREFIX_VEX_0FD0 */
5201 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5202 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5205 /* PREFIX_VEX_0FD1 */
5209 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5212 /* PREFIX_VEX_0FD2 */
5216 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5219 /* PREFIX_VEX_0FD3 */
5223 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5226 /* PREFIX_VEX_0FD4 */
5230 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5233 /* PREFIX_VEX_0FD5 */
5237 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5240 /* PREFIX_VEX_0FD6 */
5244 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5247 /* PREFIX_VEX_0FD7 */
5251 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5254 /* PREFIX_VEX_0FD8 */
5258 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5261 /* PREFIX_VEX_0FD9 */
5265 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5268 /* PREFIX_VEX_0FDA */
5272 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5275 /* PREFIX_VEX_0FDB */
5279 { "vpand", { XM
, Vex
, EXx
}, 0 },
5282 /* PREFIX_VEX_0FDC */
5286 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5289 /* PREFIX_VEX_0FDD */
5293 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5296 /* PREFIX_VEX_0FDE */
5300 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5303 /* PREFIX_VEX_0FDF */
5307 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5310 /* PREFIX_VEX_0FE0 */
5314 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5317 /* PREFIX_VEX_0FE1 */
5321 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5324 /* PREFIX_VEX_0FE2 */
5328 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5331 /* PREFIX_VEX_0FE3 */
5335 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5338 /* PREFIX_VEX_0FE4 */
5342 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5345 /* PREFIX_VEX_0FE5 */
5349 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5352 /* PREFIX_VEX_0FE6 */
5355 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5356 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5357 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5360 /* PREFIX_VEX_0FE7 */
5364 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5367 /* PREFIX_VEX_0FE8 */
5371 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5374 /* PREFIX_VEX_0FE9 */
5378 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5381 /* PREFIX_VEX_0FEA */
5385 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5388 /* PREFIX_VEX_0FEB */
5392 { "vpor", { XM
, Vex
, EXx
}, 0 },
5395 /* PREFIX_VEX_0FEC */
5399 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5402 /* PREFIX_VEX_0FED */
5406 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5409 /* PREFIX_VEX_0FEE */
5413 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5416 /* PREFIX_VEX_0FEF */
5420 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5423 /* PREFIX_VEX_0FF0 */
5428 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5431 /* PREFIX_VEX_0FF1 */
5435 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5438 /* PREFIX_VEX_0FF2 */
5442 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5445 /* PREFIX_VEX_0FF3 */
5449 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5452 /* PREFIX_VEX_0FF4 */
5456 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5459 /* PREFIX_VEX_0FF5 */
5463 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5466 /* PREFIX_VEX_0FF6 */
5470 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5473 /* PREFIX_VEX_0FF7 */
5477 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5480 /* PREFIX_VEX_0FF8 */
5484 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5487 /* PREFIX_VEX_0FF9 */
5491 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5494 /* PREFIX_VEX_0FFA */
5498 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5501 /* PREFIX_VEX_0FFB */
5505 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5508 /* PREFIX_VEX_0FFC */
5512 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5515 /* PREFIX_VEX_0FFD */
5519 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5522 /* PREFIX_VEX_0FFE */
5526 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5529 /* PREFIX_VEX_0F3800 */
5533 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5536 /* PREFIX_VEX_0F3801 */
5540 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5543 /* PREFIX_VEX_0F3802 */
5547 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5550 /* PREFIX_VEX_0F3803 */
5554 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5557 /* PREFIX_VEX_0F3804 */
5561 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5564 /* PREFIX_VEX_0F3805 */
5568 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5571 /* PREFIX_VEX_0F3806 */
5575 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5578 /* PREFIX_VEX_0F3807 */
5582 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5585 /* PREFIX_VEX_0F3808 */
5589 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5592 /* PREFIX_VEX_0F3809 */
5596 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5599 /* PREFIX_VEX_0F380A */
5603 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5606 /* PREFIX_VEX_0F380B */
5610 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5613 /* PREFIX_VEX_0F380C */
5617 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5620 /* PREFIX_VEX_0F380D */
5624 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5627 /* PREFIX_VEX_0F380E */
5631 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5634 /* PREFIX_VEX_0F380F */
5638 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5641 /* PREFIX_VEX_0F3813 */
5645 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5648 /* PREFIX_VEX_0F3816 */
5652 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5655 /* PREFIX_VEX_0F3817 */
5659 { "vptest", { XM
, EXx
}, 0 },
5662 /* PREFIX_VEX_0F3818 */
5666 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5669 /* PREFIX_VEX_0F3819 */
5673 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5676 /* PREFIX_VEX_0F381A */
5680 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5683 /* PREFIX_VEX_0F381C */
5687 { "vpabsb", { XM
, EXx
}, 0 },
5690 /* PREFIX_VEX_0F381D */
5694 { "vpabsw", { XM
, EXx
}, 0 },
5697 /* PREFIX_VEX_0F381E */
5701 { "vpabsd", { XM
, EXx
}, 0 },
5704 /* PREFIX_VEX_0F3820 */
5708 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5711 /* PREFIX_VEX_0F3821 */
5715 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5718 /* PREFIX_VEX_0F3822 */
5722 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5725 /* PREFIX_VEX_0F3823 */
5729 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5732 /* PREFIX_VEX_0F3824 */
5736 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5739 /* PREFIX_VEX_0F3825 */
5743 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5746 /* PREFIX_VEX_0F3828 */
5750 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5753 /* PREFIX_VEX_0F3829 */
5757 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5760 /* PREFIX_VEX_0F382A */
5764 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5767 /* PREFIX_VEX_0F382B */
5771 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5774 /* PREFIX_VEX_0F382C */
5778 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5781 /* PREFIX_VEX_0F382D */
5785 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5788 /* PREFIX_VEX_0F382E */
5792 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5795 /* PREFIX_VEX_0F382F */
5799 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5802 /* PREFIX_VEX_0F3830 */
5806 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5809 /* PREFIX_VEX_0F3831 */
5813 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5816 /* PREFIX_VEX_0F3832 */
5820 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5823 /* PREFIX_VEX_0F3833 */
5827 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5830 /* PREFIX_VEX_0F3834 */
5834 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5837 /* PREFIX_VEX_0F3835 */
5841 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5844 /* PREFIX_VEX_0F3836 */
5848 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5851 /* PREFIX_VEX_0F3837 */
5855 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5858 /* PREFIX_VEX_0F3838 */
5862 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5865 /* PREFIX_VEX_0F3839 */
5869 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5872 /* PREFIX_VEX_0F383A */
5876 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5879 /* PREFIX_VEX_0F383B */
5883 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5886 /* PREFIX_VEX_0F383C */
5890 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5893 /* PREFIX_VEX_0F383D */
5897 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5900 /* PREFIX_VEX_0F383E */
5904 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5907 /* PREFIX_VEX_0F383F */
5911 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5914 /* PREFIX_VEX_0F3840 */
5918 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5921 /* PREFIX_VEX_0F3841 */
5925 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5928 /* PREFIX_VEX_0F3845 */
5932 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5935 /* PREFIX_VEX_0F3846 */
5939 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5942 /* PREFIX_VEX_0F3847 */
5946 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5949 /* PREFIX_VEX_0F3858 */
5953 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5956 /* PREFIX_VEX_0F3859 */
5960 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5963 /* PREFIX_VEX_0F385A */
5967 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5970 /* PREFIX_VEX_0F3878 */
5974 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5977 /* PREFIX_VEX_0F3879 */
5981 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5984 /* PREFIX_VEX_0F388C */
5988 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5991 /* PREFIX_VEX_0F388E */
5995 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5998 /* PREFIX_VEX_0F3890 */
6002 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6005 /* PREFIX_VEX_0F3891 */
6009 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6012 /* PREFIX_VEX_0F3892 */
6016 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6019 /* PREFIX_VEX_0F3893 */
6023 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6026 /* PREFIX_VEX_0F3896 */
6030 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6033 /* PREFIX_VEX_0F3897 */
6037 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6040 /* PREFIX_VEX_0F3898 */
6044 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6047 /* PREFIX_VEX_0F3899 */
6051 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6054 /* PREFIX_VEX_0F389A */
6058 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6061 /* PREFIX_VEX_0F389B */
6065 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6068 /* PREFIX_VEX_0F389C */
6072 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6075 /* PREFIX_VEX_0F389D */
6079 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6082 /* PREFIX_VEX_0F389E */
6086 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6089 /* PREFIX_VEX_0F389F */
6093 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6096 /* PREFIX_VEX_0F38A6 */
6100 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6104 /* PREFIX_VEX_0F38A7 */
6108 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6111 /* PREFIX_VEX_0F38A8 */
6115 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6118 /* PREFIX_VEX_0F38A9 */
6122 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6125 /* PREFIX_VEX_0F38AA */
6129 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6132 /* PREFIX_VEX_0F38AB */
6136 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6139 /* PREFIX_VEX_0F38AC */
6143 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6146 /* PREFIX_VEX_0F38AD */
6150 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6153 /* PREFIX_VEX_0F38AE */
6157 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6160 /* PREFIX_VEX_0F38AF */
6164 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6167 /* PREFIX_VEX_0F38B6 */
6171 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6174 /* PREFIX_VEX_0F38B7 */
6178 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6181 /* PREFIX_VEX_0F38B8 */
6185 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6188 /* PREFIX_VEX_0F38B9 */
6192 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6195 /* PREFIX_VEX_0F38BA */
6199 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6202 /* PREFIX_VEX_0F38BB */
6206 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6209 /* PREFIX_VEX_0F38BC */
6213 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6216 /* PREFIX_VEX_0F38BD */
6220 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6223 /* PREFIX_VEX_0F38BE */
6227 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6230 /* PREFIX_VEX_0F38BF */
6234 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6237 /* PREFIX_VEX_0F38CF */
6241 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6244 /* PREFIX_VEX_0F38DB */
6248 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6251 /* PREFIX_VEX_0F38DC */
6255 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6258 /* PREFIX_VEX_0F38DD */
6262 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6265 /* PREFIX_VEX_0F38DE */
6269 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6272 /* PREFIX_VEX_0F38DF */
6276 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6279 /* PREFIX_VEX_0F38F2 */
6281 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6284 /* PREFIX_VEX_0F38F3_REG_1 */
6286 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6289 /* PREFIX_VEX_0F38F3_REG_2 */
6291 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6294 /* PREFIX_VEX_0F38F3_REG_3 */
6296 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6299 /* PREFIX_VEX_0F38F5 */
6301 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6302 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6304 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6307 /* PREFIX_VEX_0F38F6 */
6312 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6315 /* PREFIX_VEX_0F38F7 */
6317 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6318 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6319 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6320 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6323 /* PREFIX_VEX_0F3A00 */
6327 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6330 /* PREFIX_VEX_0F3A01 */
6334 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6337 /* PREFIX_VEX_0F3A02 */
6341 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6344 /* PREFIX_VEX_0F3A04 */
6348 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6351 /* PREFIX_VEX_0F3A05 */
6355 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6358 /* PREFIX_VEX_0F3A06 */
6362 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6365 /* PREFIX_VEX_0F3A08 */
6369 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6372 /* PREFIX_VEX_0F3A09 */
6376 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6379 /* PREFIX_VEX_0F3A0A */
6383 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
6386 /* PREFIX_VEX_0F3A0B */
6390 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
6393 /* PREFIX_VEX_0F3A0C */
6397 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6400 /* PREFIX_VEX_0F3A0D */
6404 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6407 /* PREFIX_VEX_0F3A0E */
6411 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6414 /* PREFIX_VEX_0F3A0F */
6418 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6421 /* PREFIX_VEX_0F3A14 */
6425 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6428 /* PREFIX_VEX_0F3A15 */
6432 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6435 /* PREFIX_VEX_0F3A16 */
6439 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6442 /* PREFIX_VEX_0F3A17 */
6446 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6449 /* PREFIX_VEX_0F3A18 */
6453 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6456 /* PREFIX_VEX_0F3A19 */
6460 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6463 /* PREFIX_VEX_0F3A1D */
6467 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6470 /* PREFIX_VEX_0F3A20 */
6474 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6477 /* PREFIX_VEX_0F3A21 */
6481 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6484 /* PREFIX_VEX_0F3A22 */
6488 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6491 /* PREFIX_VEX_0F3A30 */
6495 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6498 /* PREFIX_VEX_0F3A31 */
6502 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6505 /* PREFIX_VEX_0F3A32 */
6509 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6512 /* PREFIX_VEX_0F3A33 */
6516 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6519 /* PREFIX_VEX_0F3A38 */
6523 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6526 /* PREFIX_VEX_0F3A39 */
6530 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6533 /* PREFIX_VEX_0F3A40 */
6537 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6540 /* PREFIX_VEX_0F3A41 */
6544 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6547 /* PREFIX_VEX_0F3A42 */
6551 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6554 /* PREFIX_VEX_0F3A44 */
6558 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6561 /* PREFIX_VEX_0F3A46 */
6565 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6568 /* PREFIX_VEX_0F3A48 */
6572 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6575 /* PREFIX_VEX_0F3A49 */
6579 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6582 /* PREFIX_VEX_0F3A4A */
6586 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6589 /* PREFIX_VEX_0F3A4B */
6593 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6596 /* PREFIX_VEX_0F3A4C */
6600 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6603 /* PREFIX_VEX_0F3A5C */
6607 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6610 /* PREFIX_VEX_0F3A5D */
6614 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6617 /* PREFIX_VEX_0F3A5E */
6621 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6624 /* PREFIX_VEX_0F3A5F */
6628 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6631 /* PREFIX_VEX_0F3A60 */
6635 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6639 /* PREFIX_VEX_0F3A61 */
6643 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6646 /* PREFIX_VEX_0F3A62 */
6650 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6653 /* PREFIX_VEX_0F3A63 */
6657 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6660 /* PREFIX_VEX_0F3A68 */
6664 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6667 /* PREFIX_VEX_0F3A69 */
6671 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6674 /* PREFIX_VEX_0F3A6A */
6678 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6681 /* PREFIX_VEX_0F3A6B */
6685 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6688 /* PREFIX_VEX_0F3A6C */
6692 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6695 /* PREFIX_VEX_0F3A6D */
6699 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6702 /* PREFIX_VEX_0F3A6E */
6706 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6709 /* PREFIX_VEX_0F3A6F */
6713 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6716 /* PREFIX_VEX_0F3A78 */
6720 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6723 /* PREFIX_VEX_0F3A79 */
6727 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6730 /* PREFIX_VEX_0F3A7A */
6734 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6737 /* PREFIX_VEX_0F3A7B */
6741 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6744 /* PREFIX_VEX_0F3A7C */
6748 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6752 /* PREFIX_VEX_0F3A7D */
6756 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6759 /* PREFIX_VEX_0F3A7E */
6763 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6766 /* PREFIX_VEX_0F3A7F */
6770 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6773 /* PREFIX_VEX_0F3ACE */
6777 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6780 /* PREFIX_VEX_0F3ACF */
6784 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6787 /* PREFIX_VEX_0F3ADF */
6791 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6794 /* PREFIX_VEX_0F3AF0 */
6799 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6802 #include "i386-dis-evex-prefix.h"
6805 static const struct dis386 x86_64_table
[][2] = {
6808 { "pushP", { es
}, 0 },
6813 { "popP", { es
}, 0 },
6818 { "pushP", { cs
}, 0 },
6823 { "pushP", { ss
}, 0 },
6828 { "popP", { ss
}, 0 },
6833 { "pushP", { ds
}, 0 },
6838 { "popP", { ds
}, 0 },
6843 { "daa", { XX
}, 0 },
6848 { "das", { XX
}, 0 },
6853 { "aaa", { XX
}, 0 },
6858 { "aas", { XX
}, 0 },
6863 { "pushaP", { XX
}, 0 },
6868 { "popaP", { XX
}, 0 },
6873 { MOD_TABLE (MOD_62_32BIT
) },
6874 { EVEX_TABLE (EVEX_0F
) },
6879 { "arpl", { Ew
, Gw
}, 0 },
6880 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
6885 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6886 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6891 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6892 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6897 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6898 { REG_TABLE (REG_80
) },
6903 { "Jcall{T|}", { Ap
}, 0 },
6908 { "retP", { Iw
, BND
}, 0 },
6909 { "ret@", { Iw
, BND
}, 0 },
6914 { "retP", { BND
}, 0 },
6915 { "ret@", { BND
}, 0 },
6920 { MOD_TABLE (MOD_C4_32BIT
) },
6921 { VEX_C4_TABLE (VEX_0F
) },
6926 { MOD_TABLE (MOD_C5_32BIT
) },
6927 { VEX_C5_TABLE (VEX_0F
) },
6932 { "into", { XX
}, 0 },
6937 { "aam", { Ib
}, 0 },
6942 { "aad", { Ib
}, 0 },
6947 { "callP", { Jv
, BND
}, 0 },
6948 { "call@", { Jv
, BND
}, 0 }
6953 { "jmpP", { Jv
, BND
}, 0 },
6954 { "jmp@", { Jv
, BND
}, 0 }
6959 { "Jjmp{T|}", { Ap
}, 0 },
6962 /* X86_64_0F01_REG_0 */
6964 { "sgdt{Q|IQ}", { M
}, 0 },
6965 { "sgdt", { M
}, 0 },
6968 /* X86_64_0F01_REG_1 */
6970 { "sidt{Q|IQ}", { M
}, 0 },
6971 { "sidt", { M
}, 0 },
6974 /* X86_64_0F01_REG_2 */
6976 { "lgdt{Q|Q}", { M
}, 0 },
6977 { "lgdt", { M
}, 0 },
6980 /* X86_64_0F01_REG_3 */
6982 { "lidt{Q|Q}", { M
}, 0 },
6983 { "lidt", { M
}, 0 },
6987 static const struct dis386 three_byte_table
[][256] = {
6989 /* THREE_BYTE_0F38 */
6992 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6993 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6994 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6995 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6996 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6997 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6998 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6999 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
7001 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
7002 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
7003 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
7004 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
7010 { PREFIX_TABLE (PREFIX_0F3810
) },
7014 { PREFIX_TABLE (PREFIX_0F3814
) },
7015 { PREFIX_TABLE (PREFIX_0F3815
) },
7017 { PREFIX_TABLE (PREFIX_0F3817
) },
7023 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7024 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7025 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7028 { PREFIX_TABLE (PREFIX_0F3820
) },
7029 { PREFIX_TABLE (PREFIX_0F3821
) },
7030 { PREFIX_TABLE (PREFIX_0F3822
) },
7031 { PREFIX_TABLE (PREFIX_0F3823
) },
7032 { PREFIX_TABLE (PREFIX_0F3824
) },
7033 { PREFIX_TABLE (PREFIX_0F3825
) },
7037 { PREFIX_TABLE (PREFIX_0F3828
) },
7038 { PREFIX_TABLE (PREFIX_0F3829
) },
7039 { PREFIX_TABLE (PREFIX_0F382A
) },
7040 { PREFIX_TABLE (PREFIX_0F382B
) },
7046 { PREFIX_TABLE (PREFIX_0F3830
) },
7047 { PREFIX_TABLE (PREFIX_0F3831
) },
7048 { PREFIX_TABLE (PREFIX_0F3832
) },
7049 { PREFIX_TABLE (PREFIX_0F3833
) },
7050 { PREFIX_TABLE (PREFIX_0F3834
) },
7051 { PREFIX_TABLE (PREFIX_0F3835
) },
7053 { PREFIX_TABLE (PREFIX_0F3837
) },
7055 { PREFIX_TABLE (PREFIX_0F3838
) },
7056 { PREFIX_TABLE (PREFIX_0F3839
) },
7057 { PREFIX_TABLE (PREFIX_0F383A
) },
7058 { PREFIX_TABLE (PREFIX_0F383B
) },
7059 { PREFIX_TABLE (PREFIX_0F383C
) },
7060 { PREFIX_TABLE (PREFIX_0F383D
) },
7061 { PREFIX_TABLE (PREFIX_0F383E
) },
7062 { PREFIX_TABLE (PREFIX_0F383F
) },
7064 { PREFIX_TABLE (PREFIX_0F3840
) },
7065 { PREFIX_TABLE (PREFIX_0F3841
) },
7136 { PREFIX_TABLE (PREFIX_0F3880
) },
7137 { PREFIX_TABLE (PREFIX_0F3881
) },
7138 { PREFIX_TABLE (PREFIX_0F3882
) },
7217 { PREFIX_TABLE (PREFIX_0F38C8
) },
7218 { PREFIX_TABLE (PREFIX_0F38C9
) },
7219 { PREFIX_TABLE (PREFIX_0F38CA
) },
7220 { PREFIX_TABLE (PREFIX_0F38CB
) },
7221 { PREFIX_TABLE (PREFIX_0F38CC
) },
7222 { PREFIX_TABLE (PREFIX_0F38CD
) },
7224 { PREFIX_TABLE (PREFIX_0F38CF
) },
7238 { PREFIX_TABLE (PREFIX_0F38DB
) },
7239 { PREFIX_TABLE (PREFIX_0F38DC
) },
7240 { PREFIX_TABLE (PREFIX_0F38DD
) },
7241 { PREFIX_TABLE (PREFIX_0F38DE
) },
7242 { PREFIX_TABLE (PREFIX_0F38DF
) },
7262 { PREFIX_TABLE (PREFIX_0F38F0
) },
7263 { PREFIX_TABLE (PREFIX_0F38F1
) },
7267 { PREFIX_TABLE (PREFIX_0F38F5
) },
7268 { PREFIX_TABLE (PREFIX_0F38F6
) },
7271 { PREFIX_TABLE (PREFIX_0F38F8
) },
7272 { PREFIX_TABLE (PREFIX_0F38F9
) },
7280 /* THREE_BYTE_0F3A */
7292 { PREFIX_TABLE (PREFIX_0F3A08
) },
7293 { PREFIX_TABLE (PREFIX_0F3A09
) },
7294 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7295 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7296 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7297 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7298 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7299 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7305 { PREFIX_TABLE (PREFIX_0F3A14
) },
7306 { PREFIX_TABLE (PREFIX_0F3A15
) },
7307 { PREFIX_TABLE (PREFIX_0F3A16
) },
7308 { PREFIX_TABLE (PREFIX_0F3A17
) },
7319 { PREFIX_TABLE (PREFIX_0F3A20
) },
7320 { PREFIX_TABLE (PREFIX_0F3A21
) },
7321 { PREFIX_TABLE (PREFIX_0F3A22
) },
7355 { PREFIX_TABLE (PREFIX_0F3A40
) },
7356 { PREFIX_TABLE (PREFIX_0F3A41
) },
7357 { PREFIX_TABLE (PREFIX_0F3A42
) },
7359 { PREFIX_TABLE (PREFIX_0F3A44
) },
7391 { PREFIX_TABLE (PREFIX_0F3A60
) },
7392 { PREFIX_TABLE (PREFIX_0F3A61
) },
7393 { PREFIX_TABLE (PREFIX_0F3A62
) },
7394 { PREFIX_TABLE (PREFIX_0F3A63
) },
7512 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7514 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7515 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7533 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7573 static const struct dis386 xop_table
[][256] = {
7726 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7727 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7728 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7736 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7737 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7744 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7745 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7746 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7754 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7755 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7759 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7760 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7763 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7781 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7793 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7794 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7795 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7796 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7806 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7807 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7808 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7809 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7842 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7843 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7844 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7845 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7869 { REG_TABLE (REG_XOP_TBM_01
) },
7870 { REG_TABLE (REG_XOP_TBM_02
) },
7888 { REG_TABLE (REG_XOP_LWPCB
) },
8012 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8013 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8014 { "vfrczss", { XM
, EXd
}, 0 },
8015 { "vfrczsd", { XM
, EXq
}, 0 },
8030 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8031 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8032 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8033 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8034 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8035 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8036 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8037 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8039 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8040 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8041 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8042 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8085 { "vphaddbw", { XM
, EXxmm
}, 0 },
8086 { "vphaddbd", { XM
, EXxmm
}, 0 },
8087 { "vphaddbq", { XM
, EXxmm
}, 0 },
8090 { "vphaddwd", { XM
, EXxmm
}, 0 },
8091 { "vphaddwq", { XM
, EXxmm
}, 0 },
8096 { "vphadddq", { XM
, EXxmm
}, 0 },
8103 { "vphaddubw", { XM
, EXxmm
}, 0 },
8104 { "vphaddubd", { XM
, EXxmm
}, 0 },
8105 { "vphaddubq", { XM
, EXxmm
}, 0 },
8108 { "vphadduwd", { XM
, EXxmm
}, 0 },
8109 { "vphadduwq", { XM
, EXxmm
}, 0 },
8114 { "vphaddudq", { XM
, EXxmm
}, 0 },
8121 { "vphsubbw", { XM
, EXxmm
}, 0 },
8122 { "vphsubwd", { XM
, EXxmm
}, 0 },
8123 { "vphsubdq", { XM
, EXxmm
}, 0 },
8177 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8179 { REG_TABLE (REG_XOP_LWP
) },
8449 static const struct dis386 vex_table
[][256] = {
8471 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8472 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8473 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8474 { MOD_TABLE (MOD_VEX_0F13
) },
8475 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
8476 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
8477 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8478 { MOD_TABLE (MOD_VEX_0F17
) },
8498 { "vmovapX", { XM
, EXx
}, 0 },
8499 { "vmovapX", { EXxS
, XM
}, 0 },
8500 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8501 { MOD_TABLE (MOD_VEX_0F2B
) },
8502 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8503 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8504 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8505 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8526 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8527 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8529 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8530 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8531 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8532 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8536 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8537 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8543 { MOD_TABLE (MOD_VEX_0F50
) },
8544 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8545 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8546 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8547 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8548 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8549 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8550 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8552 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8553 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8555 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8556 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8557 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8558 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8559 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8561 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8562 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8563 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8564 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8565 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8566 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8567 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8568 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8570 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8571 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8572 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8573 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8574 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8575 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8576 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8577 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8579 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8580 { REG_TABLE (REG_VEX_0F71
) },
8581 { REG_TABLE (REG_VEX_0F72
) },
8582 { REG_TABLE (REG_VEX_0F73
) },
8583 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8584 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8585 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8586 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8592 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8593 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8594 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8595 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8615 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8616 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8617 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8618 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8624 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8625 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8648 { REG_TABLE (REG_VEX_0FAE
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8675 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8687 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8688 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8690 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8745 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8808 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8809 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8810 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8812 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8813 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8814 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8816 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8817 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8821 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8822 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8823 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8843 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8844 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8845 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8879 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8880 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8990 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8991 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8992 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8994 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9017 { REG_TABLE (REG_VEX_0F38F3
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9020 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9035 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9036 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9107 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9113 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9116 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9117 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9118 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9139 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9140 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9141 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9143 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9144 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9145 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9146 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9152 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9159 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9170 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9171 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9172 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9173 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9174 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9175 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9176 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9177 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9266 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9267 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9285 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9305 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9325 #include "i386-dis-evex.h"
9327 static const struct dis386 vex_len_table
[][2] = {
9328 /* VEX_LEN_0F12_P_0_M_0 */
9330 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
9333 /* VEX_LEN_0F12_P_0_M_1 */
9335 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9338 /* VEX_LEN_0F12_P_2 */
9340 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
9343 /* VEX_LEN_0F13_M_0 */
9345 { "vmovlpX", { EXq
, XM
}, 0 },
9348 /* VEX_LEN_0F16_P_0_M_0 */
9350 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
9353 /* VEX_LEN_0F16_P_0_M_1 */
9355 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9358 /* VEX_LEN_0F16_P_2 */
9360 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
9363 /* VEX_LEN_0F17_M_0 */
9365 { "vmovhpX", { EXq
, XM
}, 0 },
9368 /* VEX_LEN_0F41_P_0 */
9371 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9373 /* VEX_LEN_0F41_P_2 */
9376 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9378 /* VEX_LEN_0F42_P_0 */
9381 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9383 /* VEX_LEN_0F42_P_2 */
9386 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9388 /* VEX_LEN_0F44_P_0 */
9390 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9392 /* VEX_LEN_0F44_P_2 */
9394 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9396 /* VEX_LEN_0F45_P_0 */
9399 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9401 /* VEX_LEN_0F45_P_2 */
9404 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9406 /* VEX_LEN_0F46_P_0 */
9409 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9411 /* VEX_LEN_0F46_P_2 */
9414 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9416 /* VEX_LEN_0F47_P_0 */
9419 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9421 /* VEX_LEN_0F47_P_2 */
9424 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9426 /* VEX_LEN_0F4A_P_0 */
9429 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9431 /* VEX_LEN_0F4A_P_2 */
9434 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9436 /* VEX_LEN_0F4B_P_0 */
9439 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9441 /* VEX_LEN_0F4B_P_2 */
9444 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9447 /* VEX_LEN_0F6E_P_2 */
9449 { "vmovK", { XMScalar
, Edq
}, 0 },
9452 /* VEX_LEN_0F77_P_1 */
9454 { "vzeroupper", { XX
}, 0 },
9455 { "vzeroall", { XX
}, 0 },
9458 /* VEX_LEN_0F7E_P_1 */
9460 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
9463 /* VEX_LEN_0F7E_P_2 */
9465 { "vmovK", { Edq
, XMScalar
}, 0 },
9468 /* VEX_LEN_0F90_P_0 */
9470 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9473 /* VEX_LEN_0F90_P_2 */
9475 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9478 /* VEX_LEN_0F91_P_0 */
9480 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9483 /* VEX_LEN_0F91_P_2 */
9485 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9488 /* VEX_LEN_0F92_P_0 */
9490 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9493 /* VEX_LEN_0F92_P_2 */
9495 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9498 /* VEX_LEN_0F92_P_3 */
9500 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9503 /* VEX_LEN_0F93_P_0 */
9505 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9508 /* VEX_LEN_0F93_P_2 */
9510 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9513 /* VEX_LEN_0F93_P_3 */
9515 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9518 /* VEX_LEN_0F98_P_0 */
9520 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9523 /* VEX_LEN_0F98_P_2 */
9525 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9528 /* VEX_LEN_0F99_P_0 */
9530 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9533 /* VEX_LEN_0F99_P_2 */
9535 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9538 /* VEX_LEN_0FAE_R_2_M_0 */
9540 { "vldmxcsr", { Md
}, 0 },
9543 /* VEX_LEN_0FAE_R_3_M_0 */
9545 { "vstmxcsr", { Md
}, 0 },
9548 /* VEX_LEN_0FC4_P_2 */
9550 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9553 /* VEX_LEN_0FC5_P_2 */
9555 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9558 /* VEX_LEN_0FD6_P_2 */
9560 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
9563 /* VEX_LEN_0FF7_P_2 */
9565 { "vmaskmovdqu", { XM
, XS
}, 0 },
9568 /* VEX_LEN_0F3816_P_2 */
9571 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9574 /* VEX_LEN_0F3819_P_2 */
9577 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9580 /* VEX_LEN_0F381A_P_2_M_0 */
9583 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9586 /* VEX_LEN_0F3836_P_2 */
9589 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9592 /* VEX_LEN_0F3841_P_2 */
9594 { "vphminposuw", { XM
, EXx
}, 0 },
9597 /* VEX_LEN_0F385A_P_2_M_0 */
9600 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9603 /* VEX_LEN_0F38DB_P_2 */
9605 { "vaesimc", { XM
, EXx
}, 0 },
9608 /* VEX_LEN_0F38F2_P_0 */
9610 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9613 /* VEX_LEN_0F38F3_R_1_P_0 */
9615 { "blsrS", { VexGdq
, Edq
}, 0 },
9618 /* VEX_LEN_0F38F3_R_2_P_0 */
9620 { "blsmskS", { VexGdq
, Edq
}, 0 },
9623 /* VEX_LEN_0F38F3_R_3_P_0 */
9625 { "blsiS", { VexGdq
, Edq
}, 0 },
9628 /* VEX_LEN_0F38F5_P_0 */
9630 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9633 /* VEX_LEN_0F38F5_P_1 */
9635 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9638 /* VEX_LEN_0F38F5_P_3 */
9640 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9643 /* VEX_LEN_0F38F6_P_3 */
9645 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9648 /* VEX_LEN_0F38F7_P_0 */
9650 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9653 /* VEX_LEN_0F38F7_P_1 */
9655 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9658 /* VEX_LEN_0F38F7_P_2 */
9660 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9663 /* VEX_LEN_0F38F7_P_3 */
9665 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9668 /* VEX_LEN_0F3A00_P_2 */
9671 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9674 /* VEX_LEN_0F3A01_P_2 */
9677 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9680 /* VEX_LEN_0F3A06_P_2 */
9683 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9686 /* VEX_LEN_0F3A14_P_2 */
9688 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9691 /* VEX_LEN_0F3A15_P_2 */
9693 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9696 /* VEX_LEN_0F3A16_P_2 */
9698 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9701 /* VEX_LEN_0F3A17_P_2 */
9703 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9706 /* VEX_LEN_0F3A18_P_2 */
9709 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9712 /* VEX_LEN_0F3A19_P_2 */
9715 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9718 /* VEX_LEN_0F3A20_P_2 */
9720 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9723 /* VEX_LEN_0F3A21_P_2 */
9725 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9728 /* VEX_LEN_0F3A22_P_2 */
9730 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9733 /* VEX_LEN_0F3A30_P_2 */
9735 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9738 /* VEX_LEN_0F3A31_P_2 */
9740 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9743 /* VEX_LEN_0F3A32_P_2 */
9745 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9748 /* VEX_LEN_0F3A33_P_2 */
9750 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9753 /* VEX_LEN_0F3A38_P_2 */
9756 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9759 /* VEX_LEN_0F3A39_P_2 */
9762 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9765 /* VEX_LEN_0F3A41_P_2 */
9767 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9770 /* VEX_LEN_0F3A46_P_2 */
9773 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9776 /* VEX_LEN_0F3A60_P_2 */
9778 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9781 /* VEX_LEN_0F3A61_P_2 */
9783 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9786 /* VEX_LEN_0F3A62_P_2 */
9788 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9791 /* VEX_LEN_0F3A63_P_2 */
9793 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9796 /* VEX_LEN_0F3A6A_P_2 */
9798 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9801 /* VEX_LEN_0F3A6B_P_2 */
9803 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9806 /* VEX_LEN_0F3A6E_P_2 */
9808 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9811 /* VEX_LEN_0F3A6F_P_2 */
9813 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9816 /* VEX_LEN_0F3A7A_P_2 */
9818 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9821 /* VEX_LEN_0F3A7B_P_2 */
9823 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9826 /* VEX_LEN_0F3A7E_P_2 */
9828 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9831 /* VEX_LEN_0F3A7F_P_2 */
9833 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9836 /* VEX_LEN_0F3ADF_P_2 */
9838 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9841 /* VEX_LEN_0F3AF0_P_3 */
9843 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9846 /* VEX_LEN_0FXOP_08_CC */
9848 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9851 /* VEX_LEN_0FXOP_08_CD */
9853 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9856 /* VEX_LEN_0FXOP_08_CE */
9858 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9861 /* VEX_LEN_0FXOP_08_CF */
9863 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9866 /* VEX_LEN_0FXOP_08_EC */
9868 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9871 /* VEX_LEN_0FXOP_08_ED */
9873 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9876 /* VEX_LEN_0FXOP_08_EE */
9878 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9881 /* VEX_LEN_0FXOP_08_EF */
9883 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9886 /* VEX_LEN_0FXOP_09_80 */
9888 { "vfrczps", { XM
, EXxmm
}, 0 },
9889 { "vfrczps", { XM
, EXymmq
}, 0 },
9892 /* VEX_LEN_0FXOP_09_81 */
9894 { "vfrczpd", { XM
, EXxmm
}, 0 },
9895 { "vfrczpd", { XM
, EXymmq
}, 0 },
9899 #include "i386-dis-evex-len.h"
9901 static const struct dis386 vex_w_table
[][2] = {
9903 /* VEX_W_0F41_P_0_LEN_1 */
9904 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9905 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9908 /* VEX_W_0F41_P_2_LEN_1 */
9909 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9910 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9913 /* VEX_W_0F42_P_0_LEN_1 */
9914 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9915 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9918 /* VEX_W_0F42_P_2_LEN_1 */
9919 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9920 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9923 /* VEX_W_0F44_P_0_LEN_0 */
9924 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9925 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9928 /* VEX_W_0F44_P_2_LEN_0 */
9929 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9930 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9933 /* VEX_W_0F45_P_0_LEN_1 */
9934 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9935 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9938 /* VEX_W_0F45_P_2_LEN_1 */
9939 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9940 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9943 /* VEX_W_0F46_P_0_LEN_1 */
9944 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9945 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9948 /* VEX_W_0F46_P_2_LEN_1 */
9949 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9950 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9953 /* VEX_W_0F47_P_0_LEN_1 */
9954 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9955 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9958 /* VEX_W_0F47_P_2_LEN_1 */
9959 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9960 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9963 /* VEX_W_0F4A_P_0_LEN_1 */
9964 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9965 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9968 /* VEX_W_0F4A_P_2_LEN_1 */
9969 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9970 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9973 /* VEX_W_0F4B_P_0_LEN_1 */
9974 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9975 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9978 /* VEX_W_0F4B_P_2_LEN_1 */
9979 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9982 /* VEX_W_0F90_P_0_LEN_0 */
9983 { "kmovw", { MaskG
, MaskE
}, 0 },
9984 { "kmovq", { MaskG
, MaskE
}, 0 },
9987 /* VEX_W_0F90_P_2_LEN_0 */
9988 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9989 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9992 /* VEX_W_0F91_P_0_LEN_0 */
9993 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9994 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9997 /* VEX_W_0F91_P_2_LEN_0 */
9998 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
9999 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
10002 /* VEX_W_0F92_P_0_LEN_0 */
10003 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10006 /* VEX_W_0F92_P_2_LEN_0 */
10007 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10010 /* VEX_W_0F93_P_0_LEN_0 */
10011 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10014 /* VEX_W_0F93_P_2_LEN_0 */
10015 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10018 /* VEX_W_0F98_P_0_LEN_0 */
10019 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10020 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10023 /* VEX_W_0F98_P_2_LEN_0 */
10024 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10025 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10028 /* VEX_W_0F99_P_0_LEN_0 */
10029 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10030 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10033 /* VEX_W_0F99_P_2_LEN_0 */
10034 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10035 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10038 /* VEX_W_0F380C_P_2 */
10039 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10042 /* VEX_W_0F380D_P_2 */
10043 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10046 /* VEX_W_0F380E_P_2 */
10047 { "vtestps", { XM
, EXx
}, 0 },
10050 /* VEX_W_0F380F_P_2 */
10051 { "vtestpd", { XM
, EXx
}, 0 },
10054 /* VEX_W_0F3816_P_2 */
10055 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10058 /* VEX_W_0F3818_P_2 */
10059 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10062 /* VEX_W_0F3819_P_2 */
10063 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10066 /* VEX_W_0F381A_P_2_M_0 */
10067 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10070 /* VEX_W_0F382C_P_2_M_0 */
10071 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10074 /* VEX_W_0F382D_P_2_M_0 */
10075 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10078 /* VEX_W_0F382E_P_2_M_0 */
10079 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10082 /* VEX_W_0F382F_P_2_M_0 */
10083 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10086 /* VEX_W_0F3836_P_2 */
10087 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10090 /* VEX_W_0F3846_P_2 */
10091 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10094 /* VEX_W_0F3858_P_2 */
10095 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10098 /* VEX_W_0F3859_P_2 */
10099 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10102 /* VEX_W_0F385A_P_2_M_0 */
10103 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10106 /* VEX_W_0F3878_P_2 */
10107 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10110 /* VEX_W_0F3879_P_2 */
10111 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10114 /* VEX_W_0F38CF_P_2 */
10115 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10118 /* VEX_W_0F3A00_P_2 */
10120 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10123 /* VEX_W_0F3A01_P_2 */
10125 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10128 /* VEX_W_0F3A02_P_2 */
10129 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10132 /* VEX_W_0F3A04_P_2 */
10133 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10136 /* VEX_W_0F3A05_P_2 */
10137 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10140 /* VEX_W_0F3A06_P_2 */
10141 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10144 /* VEX_W_0F3A18_P_2 */
10145 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10148 /* VEX_W_0F3A19_P_2 */
10149 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10152 /* VEX_W_0F3A30_P_2_LEN_0 */
10153 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10154 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10157 /* VEX_W_0F3A31_P_2_LEN_0 */
10158 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10159 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10162 /* VEX_W_0F3A32_P_2_LEN_0 */
10163 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10164 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10167 /* VEX_W_0F3A33_P_2_LEN_0 */
10168 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10169 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10172 /* VEX_W_0F3A38_P_2 */
10173 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10176 /* VEX_W_0F3A39_P_2 */
10177 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10180 /* VEX_W_0F3A46_P_2 */
10181 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10184 /* VEX_W_0F3A48_P_2 */
10185 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10186 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10189 /* VEX_W_0F3A49_P_2 */
10190 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10191 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10194 /* VEX_W_0F3A4A_P_2 */
10195 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10198 /* VEX_W_0F3A4B_P_2 */
10199 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10202 /* VEX_W_0F3A4C_P_2 */
10203 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10206 /* VEX_W_0F3ACE_P_2 */
10208 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10211 /* VEX_W_0F3ACF_P_2 */
10213 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10216 #include "i386-dis-evex-w.h"
10219 static const struct dis386 mod_table
[][2] = {
10222 { "leaS", { Gv
, M
}, 0 },
10227 { RM_TABLE (RM_C6_REG_7
) },
10232 { RM_TABLE (RM_C7_REG_7
) },
10236 { "Jcall^", { indirEp
}, 0 },
10240 { "Jjmp^", { indirEp
}, 0 },
10243 /* MOD_0F01_REG_0 */
10244 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10245 { RM_TABLE (RM_0F01_REG_0
) },
10248 /* MOD_0F01_REG_1 */
10249 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10250 { RM_TABLE (RM_0F01_REG_1
) },
10253 /* MOD_0F01_REG_2 */
10254 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10255 { RM_TABLE (RM_0F01_REG_2
) },
10258 /* MOD_0F01_REG_3 */
10259 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10260 { RM_TABLE (RM_0F01_REG_3
) },
10263 /* MOD_0F01_REG_5 */
10264 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
10265 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
10268 /* MOD_0F01_REG_7 */
10269 { "invlpg", { Mb
}, 0 },
10270 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
10273 /* MOD_0F12_PREFIX_0 */
10274 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
10275 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
10279 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10282 /* MOD_0F16_PREFIX_0 */
10283 { "movhps", { XM
, EXq
}, 0 },
10284 { "movlhps", { XM
, EXq
}, 0 },
10288 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10291 /* MOD_0F18_REG_0 */
10292 { "prefetchnta", { Mb
}, 0 },
10295 /* MOD_0F18_REG_1 */
10296 { "prefetcht0", { Mb
}, 0 },
10299 /* MOD_0F18_REG_2 */
10300 { "prefetcht1", { Mb
}, 0 },
10303 /* MOD_0F18_REG_3 */
10304 { "prefetcht2", { Mb
}, 0 },
10307 /* MOD_0F18_REG_4 */
10308 { "nop/reserved", { Mb
}, 0 },
10311 /* MOD_0F18_REG_5 */
10312 { "nop/reserved", { Mb
}, 0 },
10315 /* MOD_0F18_REG_6 */
10316 { "nop/reserved", { Mb
}, 0 },
10319 /* MOD_0F18_REG_7 */
10320 { "nop/reserved", { Mb
}, 0 },
10323 /* MOD_0F1A_PREFIX_0 */
10324 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10325 { "nopQ", { Ev
}, 0 },
10328 /* MOD_0F1B_PREFIX_0 */
10329 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10330 { "nopQ", { Ev
}, 0 },
10333 /* MOD_0F1B_PREFIX_1 */
10334 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10335 { "nopQ", { Ev
}, 0 },
10338 /* MOD_0F1C_PREFIX_0 */
10339 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
10340 { "nopQ", { Ev
}, 0 },
10343 /* MOD_0F1E_PREFIX_1 */
10344 { "nopQ", { Ev
}, 0 },
10345 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
10350 { "movL", { Rd
, Td
}, 0 },
10355 { "movL", { Td
, Rd
}, 0 },
10358 /* MOD_0F2B_PREFIX_0 */
10359 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10362 /* MOD_0F2B_PREFIX_1 */
10363 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10366 /* MOD_0F2B_PREFIX_2 */
10367 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10370 /* MOD_0F2B_PREFIX_3 */
10371 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10376 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10379 /* MOD_0F71_REG_2 */
10381 { "psrlw", { MS
, Ib
}, 0 },
10384 /* MOD_0F71_REG_4 */
10386 { "psraw", { MS
, Ib
}, 0 },
10389 /* MOD_0F71_REG_6 */
10391 { "psllw", { MS
, Ib
}, 0 },
10394 /* MOD_0F72_REG_2 */
10396 { "psrld", { MS
, Ib
}, 0 },
10399 /* MOD_0F72_REG_4 */
10401 { "psrad", { MS
, Ib
}, 0 },
10404 /* MOD_0F72_REG_6 */
10406 { "pslld", { MS
, Ib
}, 0 },
10409 /* MOD_0F73_REG_2 */
10411 { "psrlq", { MS
, Ib
}, 0 },
10414 /* MOD_0F73_REG_3 */
10416 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10419 /* MOD_0F73_REG_6 */
10421 { "psllq", { MS
, Ib
}, 0 },
10424 /* MOD_0F73_REG_7 */
10426 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10429 /* MOD_0FAE_REG_0 */
10430 { "fxsave", { FXSAVE
}, 0 },
10431 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
10434 /* MOD_0FAE_REG_1 */
10435 { "fxrstor", { FXSAVE
}, 0 },
10436 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
10439 /* MOD_0FAE_REG_2 */
10440 { "ldmxcsr", { Md
}, 0 },
10441 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
10444 /* MOD_0FAE_REG_3 */
10445 { "stmxcsr", { Md
}, 0 },
10446 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
10449 /* MOD_0FAE_REG_4 */
10450 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
10451 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
10454 /* MOD_0FAE_REG_5 */
10455 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0
) },
10456 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
10459 /* MOD_0FAE_REG_6 */
10460 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
10461 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
10464 /* MOD_0FAE_REG_7 */
10465 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
10466 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
10470 { "lssS", { Gv
, Mp
}, 0 },
10474 { "lfsS", { Gv
, Mp
}, 0 },
10478 { "lgsS", { Gv
, Mp
}, 0 },
10482 { PREFIX_TABLE (PREFIX_0FC3_MOD_0
) },
10485 /* MOD_0FC7_REG_3 */
10486 { "xrstors", { FXSAVE
}, 0 },
10489 /* MOD_0FC7_REG_4 */
10490 { "xsavec", { FXSAVE
}, 0 },
10493 /* MOD_0FC7_REG_5 */
10494 { "xsaves", { FXSAVE
}, 0 },
10497 /* MOD_0FC7_REG_6 */
10498 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
10499 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
10502 /* MOD_0FC7_REG_7 */
10503 { "vmptrst", { Mq
}, 0 },
10504 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
10509 { "pmovmskb", { Gdq
, MS
}, 0 },
10512 /* MOD_0FE7_PREFIX_2 */
10513 { "movntdq", { Mx
, XM
}, 0 },
10516 /* MOD_0FF0_PREFIX_3 */
10517 { "lddqu", { XM
, M
}, 0 },
10520 /* MOD_0F382A_PREFIX_2 */
10521 { "movntdqa", { XM
, Mx
}, 0 },
10524 /* MOD_0F38F5_PREFIX_2 */
10525 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10528 /* MOD_0F38F6_PREFIX_0 */
10529 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10532 /* MOD_0F38F8_PREFIX_1 */
10533 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
10536 /* MOD_0F38F8_PREFIX_2 */
10537 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10540 /* MOD_0F38F8_PREFIX_3 */
10541 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
10544 /* MOD_0F38F9_PREFIX_0 */
10545 { "movdiri", { Ev
, Gv
}, PREFIX_OPCODE
},
10549 { "bound{S|}", { Gv
, Ma
}, 0 },
10550 { EVEX_TABLE (EVEX_0F
) },
10554 { "lesS", { Gv
, Mp
}, 0 },
10555 { VEX_C4_TABLE (VEX_0F
) },
10559 { "ldsS", { Gv
, Mp
}, 0 },
10560 { VEX_C5_TABLE (VEX_0F
) },
10563 /* MOD_VEX_0F12_PREFIX_0 */
10564 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10565 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10569 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10572 /* MOD_VEX_0F16_PREFIX_0 */
10573 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10574 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10578 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10582 { "vmovntpX", { Mx
, XM
}, 0 },
10585 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10587 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10590 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10592 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10595 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10597 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10600 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10602 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10605 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10607 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10610 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10612 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10615 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10617 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10620 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10622 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10625 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10627 { "knotw", { MaskG
, MaskR
}, 0 },
10630 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10632 { "knotq", { MaskG
, MaskR
}, 0 },
10635 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10637 { "knotb", { MaskG
, MaskR
}, 0 },
10640 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10642 { "knotd", { MaskG
, MaskR
}, 0 },
10645 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10647 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10650 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10652 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10655 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10657 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10660 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10662 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10665 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10667 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10670 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10672 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10675 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10677 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10680 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10682 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10685 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10687 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10690 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10692 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10695 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10697 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10700 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10702 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10705 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10707 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10710 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10712 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10715 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10717 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10720 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10722 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10725 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10727 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10730 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10732 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10735 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10737 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10742 { "vmovmskpX", { Gdq
, XS
}, 0 },
10745 /* MOD_VEX_0F71_REG_2 */
10747 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10750 /* MOD_VEX_0F71_REG_4 */
10752 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10755 /* MOD_VEX_0F71_REG_6 */
10757 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10760 /* MOD_VEX_0F72_REG_2 */
10762 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10765 /* MOD_VEX_0F72_REG_4 */
10767 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10770 /* MOD_VEX_0F72_REG_6 */
10772 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10775 /* MOD_VEX_0F73_REG_2 */
10777 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10780 /* MOD_VEX_0F73_REG_3 */
10782 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10785 /* MOD_VEX_0F73_REG_6 */
10787 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10790 /* MOD_VEX_0F73_REG_7 */
10792 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10795 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10796 { "kmovw", { Ew
, MaskG
}, 0 },
10800 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10801 { "kmovq", { Eq
, MaskG
}, 0 },
10805 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10806 { "kmovb", { Eb
, MaskG
}, 0 },
10810 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10811 { "kmovd", { Ed
, MaskG
}, 0 },
10815 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10817 { "kmovw", { MaskG
, Rdq
}, 0 },
10820 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10822 { "kmovb", { MaskG
, Rdq
}, 0 },
10825 /* MOD_VEX_0F92_P_3_LEN_0 */
10827 { "kmovK", { MaskG
, Rdq
}, 0 },
10830 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10832 { "kmovw", { Gdq
, MaskR
}, 0 },
10835 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10837 { "kmovb", { Gdq
, MaskR
}, 0 },
10840 /* MOD_VEX_0F93_P_3_LEN_0 */
10842 { "kmovK", { Gdq
, MaskR
}, 0 },
10845 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10847 { "kortestw", { MaskG
, MaskR
}, 0 },
10850 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10852 { "kortestq", { MaskG
, MaskR
}, 0 },
10855 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10857 { "kortestb", { MaskG
, MaskR
}, 0 },
10860 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10862 { "kortestd", { MaskG
, MaskR
}, 0 },
10865 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10867 { "ktestw", { MaskG
, MaskR
}, 0 },
10870 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10872 { "ktestq", { MaskG
, MaskR
}, 0 },
10875 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10877 { "ktestb", { MaskG
, MaskR
}, 0 },
10880 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10882 { "ktestd", { MaskG
, MaskR
}, 0 },
10885 /* MOD_VEX_0FAE_REG_2 */
10886 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10889 /* MOD_VEX_0FAE_REG_3 */
10890 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10893 /* MOD_VEX_0FD7_PREFIX_2 */
10895 { "vpmovmskb", { Gdq
, XS
}, 0 },
10898 /* MOD_VEX_0FE7_PREFIX_2 */
10899 { "vmovntdq", { Mx
, XM
}, 0 },
10902 /* MOD_VEX_0FF0_PREFIX_3 */
10903 { "vlddqu", { XM
, M
}, 0 },
10906 /* MOD_VEX_0F381A_PREFIX_2 */
10907 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10910 /* MOD_VEX_0F382A_PREFIX_2 */
10911 { "vmovntdqa", { XM
, Mx
}, 0 },
10914 /* MOD_VEX_0F382C_PREFIX_2 */
10915 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10918 /* MOD_VEX_0F382D_PREFIX_2 */
10919 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10922 /* MOD_VEX_0F382E_PREFIX_2 */
10923 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10926 /* MOD_VEX_0F382F_PREFIX_2 */
10927 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10930 /* MOD_VEX_0F385A_PREFIX_2 */
10931 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10934 /* MOD_VEX_0F388C_PREFIX_2 */
10935 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10938 /* MOD_VEX_0F388E_PREFIX_2 */
10939 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10942 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10944 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10947 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10949 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10952 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10954 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10957 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10959 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10962 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10964 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10967 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10969 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10972 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10974 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10977 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10979 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10982 #include "i386-dis-evex-mod.h"
10985 static const struct dis386 rm_table
[][8] = {
10988 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10992 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
10995 /* RM_0F01_REG_0 */
10996 { "enclv", { Skip_MODRM
}, 0 },
10997 { "vmcall", { Skip_MODRM
}, 0 },
10998 { "vmlaunch", { Skip_MODRM
}, 0 },
10999 { "vmresume", { Skip_MODRM
}, 0 },
11000 { "vmxoff", { Skip_MODRM
}, 0 },
11001 { "pconfig", { Skip_MODRM
}, 0 },
11004 /* RM_0F01_REG_1 */
11005 { "monitor", { { OP_Monitor
, 0 } }, 0 },
11006 { "mwait", { { OP_Mwait
, 0 } }, 0 },
11007 { "clac", { Skip_MODRM
}, 0 },
11008 { "stac", { Skip_MODRM
}, 0 },
11012 { "encls", { Skip_MODRM
}, 0 },
11015 /* RM_0F01_REG_2 */
11016 { "xgetbv", { Skip_MODRM
}, 0 },
11017 { "xsetbv", { Skip_MODRM
}, 0 },
11020 { "vmfunc", { Skip_MODRM
}, 0 },
11021 { "xend", { Skip_MODRM
}, 0 },
11022 { "xtest", { Skip_MODRM
}, 0 },
11023 { "enclu", { Skip_MODRM
}, 0 },
11026 /* RM_0F01_REG_3 */
11027 { "vmrun", { Skip_MODRM
}, 0 },
11028 { "vmmcall", { Skip_MODRM
}, 0 },
11029 { "vmload", { Skip_MODRM
}, 0 },
11030 { "vmsave", { Skip_MODRM
}, 0 },
11031 { "stgi", { Skip_MODRM
}, 0 },
11032 { "clgi", { Skip_MODRM
}, 0 },
11033 { "skinit", { Skip_MODRM
}, 0 },
11034 { "invlpga", { Skip_MODRM
}, 0 },
11037 /* RM_0F01_REG_5_MOD_3 */
11038 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
11040 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
11044 { "rdpkru", { Skip_MODRM
}, 0 },
11045 { "wrpkru", { Skip_MODRM
}, 0 },
11048 /* RM_0F01_REG_7_MOD_3 */
11049 { "swapgs", { Skip_MODRM
}, 0 },
11050 { "rdtscp", { Skip_MODRM
}, 0 },
11051 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
11052 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3
) },
11053 { "clzero", { Skip_MODRM
}, 0 },
11054 { "rdpru", { Skip_MODRM
}, 0 },
11057 /* RM_0F1E_P_1_MOD_3_REG_7 */
11058 { "nopQ", { Ev
}, 0 },
11059 { "nopQ", { Ev
}, 0 },
11060 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11061 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11062 { "nopQ", { Ev
}, 0 },
11063 { "nopQ", { Ev
}, 0 },
11064 { "nopQ", { Ev
}, 0 },
11065 { "nopQ", { Ev
}, 0 },
11068 /* RM_0FAE_REG_6_MOD_3 */
11069 { "mfence", { Skip_MODRM
}, 0 },
11072 /* RM_0FAE_REG_7_MOD_3 */
11073 { "sfence", { Skip_MODRM
}, 0 },
11078 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11080 /* We use the high bit to indicate different name for the same
11082 #define REP_PREFIX (0xf3 | 0x100)
11083 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11084 #define XRELEASE_PREFIX (0xf3 | 0x400)
11085 #define BND_PREFIX (0xf2 | 0x400)
11086 #define NOTRACK_PREFIX (0x3e | 0x100)
11088 /* Remember if the current op is a jump instruction. */
11089 static bfd_boolean op_is_jump
= FALSE
;
11094 int newrex
, i
, length
;
11100 last_lock_prefix
= -1;
11101 last_repz_prefix
= -1;
11102 last_repnz_prefix
= -1;
11103 last_data_prefix
= -1;
11104 last_addr_prefix
= -1;
11105 last_rex_prefix
= -1;
11106 last_seg_prefix
= -1;
11108 active_seg_prefix
= 0;
11109 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11110 all_prefixes
[i
] = 0;
11113 /* The maximum instruction length is 15bytes. */
11114 while (length
< MAX_CODE_LENGTH
- 1)
11116 FETCH_DATA (the_info
, codep
+ 1);
11120 /* REX prefixes family. */
11137 if (address_mode
== mode_64bit
)
11141 last_rex_prefix
= i
;
11144 prefixes
|= PREFIX_REPZ
;
11145 last_repz_prefix
= i
;
11148 prefixes
|= PREFIX_REPNZ
;
11149 last_repnz_prefix
= i
;
11152 prefixes
|= PREFIX_LOCK
;
11153 last_lock_prefix
= i
;
11156 prefixes
|= PREFIX_CS
;
11157 last_seg_prefix
= i
;
11158 active_seg_prefix
= PREFIX_CS
;
11161 prefixes
|= PREFIX_SS
;
11162 last_seg_prefix
= i
;
11163 active_seg_prefix
= PREFIX_SS
;
11166 prefixes
|= PREFIX_DS
;
11167 last_seg_prefix
= i
;
11168 active_seg_prefix
= PREFIX_DS
;
11171 prefixes
|= PREFIX_ES
;
11172 last_seg_prefix
= i
;
11173 active_seg_prefix
= PREFIX_ES
;
11176 prefixes
|= PREFIX_FS
;
11177 last_seg_prefix
= i
;
11178 active_seg_prefix
= PREFIX_FS
;
11181 prefixes
|= PREFIX_GS
;
11182 last_seg_prefix
= i
;
11183 active_seg_prefix
= PREFIX_GS
;
11186 prefixes
|= PREFIX_DATA
;
11187 last_data_prefix
= i
;
11190 prefixes
|= PREFIX_ADDR
;
11191 last_addr_prefix
= i
;
11194 /* fwait is really an instruction. If there are prefixes
11195 before the fwait, they belong to the fwait, *not* to the
11196 following instruction. */
11198 if (prefixes
|| rex
)
11200 prefixes
|= PREFIX_FWAIT
;
11202 /* This ensures that the previous REX prefixes are noticed
11203 as unused prefixes, as in the return case below. */
11207 prefixes
= PREFIX_FWAIT
;
11212 /* Rex is ignored when followed by another prefix. */
11218 if (*codep
!= FWAIT_OPCODE
)
11219 all_prefixes
[i
++] = *codep
;
11227 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11230 static const char *
11231 prefix_name (int pref
, int sizeflag
)
11233 static const char *rexes
[16] =
11236 "rex.B", /* 0x41 */
11237 "rex.X", /* 0x42 */
11238 "rex.XB", /* 0x43 */
11239 "rex.R", /* 0x44 */
11240 "rex.RB", /* 0x45 */
11241 "rex.RX", /* 0x46 */
11242 "rex.RXB", /* 0x47 */
11243 "rex.W", /* 0x48 */
11244 "rex.WB", /* 0x49 */
11245 "rex.WX", /* 0x4a */
11246 "rex.WXB", /* 0x4b */
11247 "rex.WR", /* 0x4c */
11248 "rex.WRB", /* 0x4d */
11249 "rex.WRX", /* 0x4e */
11250 "rex.WRXB", /* 0x4f */
11255 /* REX prefixes family. */
11272 return rexes
[pref
- 0x40];
11292 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11294 if (address_mode
== mode_64bit
)
11295 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11297 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11302 case XACQUIRE_PREFIX
:
11304 case XRELEASE_PREFIX
:
11308 case NOTRACK_PREFIX
:
11315 static char op_out
[MAX_OPERANDS
][100];
11316 static int op_ad
, op_index
[MAX_OPERANDS
];
11317 static int two_source_ops
;
11318 static bfd_vma op_address
[MAX_OPERANDS
];
11319 static bfd_vma op_riprel
[MAX_OPERANDS
];
11320 static bfd_vma start_pc
;
11323 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11324 * (see topic "Redundant prefixes" in the "Differences from 8086"
11325 * section of the "Virtual 8086 Mode" chapter.)
11326 * 'pc' should be the address of this instruction, it will
11327 * be used to print the target address if this is a relative jump or call
11328 * The function returns the length of this instruction in bytes.
11331 static char intel_syntax
;
11332 static char intel_mnemonic
= !SYSV386_COMPAT
;
11333 static char open_char
;
11334 static char close_char
;
11335 static char separator_char
;
11336 static char scale_char
;
11344 static enum x86_64_isa isa64
;
11346 /* Here for backwards compatibility. When gdb stops using
11347 print_insn_i386_att and print_insn_i386_intel these functions can
11348 disappear, and print_insn_i386 be merged into print_insn. */
11350 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11354 return print_insn (pc
, info
);
11358 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11362 return print_insn (pc
, info
);
11366 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11370 return print_insn (pc
, info
);
11374 print_i386_disassembler_options (FILE *stream
)
11376 fprintf (stream
, _("\n\
11377 The following i386/x86-64 specific disassembler options are supported for use\n\
11378 with the -M switch (multiple options should be separated by commas):\n"));
11380 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11381 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11382 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11383 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11384 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11385 fprintf (stream
, _(" att-mnemonic\n"
11386 " Display instruction in AT&T mnemonic\n"));
11387 fprintf (stream
, _(" intel-mnemonic\n"
11388 " Display instruction in Intel mnemonic\n"));
11389 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11390 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11391 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11392 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11393 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11394 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11395 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11396 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11400 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11402 /* Get a pointer to struct dis386 with a valid name. */
11404 static const struct dis386
*
11405 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11407 int vindex
, vex_table_index
;
11409 if (dp
->name
!= NULL
)
11412 switch (dp
->op
[0].bytemode
)
11414 case USE_REG_TABLE
:
11415 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11418 case USE_MOD_TABLE
:
11419 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11420 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11424 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11427 case USE_PREFIX_TABLE
:
11430 /* The prefix in VEX is implicit. */
11431 switch (vex
.prefix
)
11436 case REPE_PREFIX_OPCODE
:
11439 case DATA_PREFIX_OPCODE
:
11442 case REPNE_PREFIX_OPCODE
:
11452 int last_prefix
= -1;
11455 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11456 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11458 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11460 if (last_repz_prefix
> last_repnz_prefix
)
11463 prefix
= PREFIX_REPZ
;
11464 last_prefix
= last_repz_prefix
;
11469 prefix
= PREFIX_REPNZ
;
11470 last_prefix
= last_repnz_prefix
;
11473 /* Check if prefix should be ignored. */
11474 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11475 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11480 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11483 prefix
= PREFIX_DATA
;
11484 last_prefix
= last_data_prefix
;
11489 used_prefixes
|= prefix
;
11490 all_prefixes
[last_prefix
] = 0;
11493 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11496 case USE_X86_64_TABLE
:
11497 vindex
= address_mode
== mode_64bit
? 1 : 0;
11498 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11501 case USE_3BYTE_TABLE
:
11502 FETCH_DATA (info
, codep
+ 2);
11504 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11506 modrm
.mod
= (*codep
>> 6) & 3;
11507 modrm
.reg
= (*codep
>> 3) & 7;
11508 modrm
.rm
= *codep
& 7;
11511 case USE_VEX_LEN_TABLE
:
11515 switch (vex
.length
)
11528 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11531 case USE_EVEX_LEN_TABLE
:
11535 switch (vex
.length
)
11551 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11554 case USE_XOP_8F_TABLE
:
11555 FETCH_DATA (info
, codep
+ 3);
11556 /* All bits in the REX prefix are ignored. */
11558 rex
= ~(*codep
>> 5) & 0x7;
11560 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11561 switch ((*codep
& 0x1f))
11567 vex_table_index
= XOP_08
;
11570 vex_table_index
= XOP_09
;
11573 vex_table_index
= XOP_0A
;
11577 vex
.w
= *codep
& 0x80;
11578 if (vex
.w
&& address_mode
== mode_64bit
)
11581 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11582 if (address_mode
!= mode_64bit
)
11584 /* In 16/32-bit mode REX_B is silently ignored. */
11588 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11589 switch ((*codep
& 0x3))
11594 vex
.prefix
= DATA_PREFIX_OPCODE
;
11597 vex
.prefix
= REPE_PREFIX_OPCODE
;
11600 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11607 dp
= &xop_table
[vex_table_index
][vindex
];
11610 FETCH_DATA (info
, codep
+ 1);
11611 modrm
.mod
= (*codep
>> 6) & 3;
11612 modrm
.reg
= (*codep
>> 3) & 7;
11613 modrm
.rm
= *codep
& 7;
11616 case USE_VEX_C4_TABLE
:
11618 FETCH_DATA (info
, codep
+ 3);
11619 /* All bits in the REX prefix are ignored. */
11621 rex
= ~(*codep
>> 5) & 0x7;
11622 switch ((*codep
& 0x1f))
11628 vex_table_index
= VEX_0F
;
11631 vex_table_index
= VEX_0F38
;
11634 vex_table_index
= VEX_0F3A
;
11638 vex
.w
= *codep
& 0x80;
11639 if (address_mode
== mode_64bit
)
11646 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11647 is ignored, other REX bits are 0 and the highest bit in
11648 VEX.vvvv is also ignored (but we mustn't clear it here). */
11651 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11652 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11653 switch ((*codep
& 0x3))
11658 vex
.prefix
= DATA_PREFIX_OPCODE
;
11661 vex
.prefix
= REPE_PREFIX_OPCODE
;
11664 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11671 dp
= &vex_table
[vex_table_index
][vindex
];
11673 /* There is no MODRM byte for VEX0F 77. */
11674 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11676 FETCH_DATA (info
, codep
+ 1);
11677 modrm
.mod
= (*codep
>> 6) & 3;
11678 modrm
.reg
= (*codep
>> 3) & 7;
11679 modrm
.rm
= *codep
& 7;
11683 case USE_VEX_C5_TABLE
:
11685 FETCH_DATA (info
, codep
+ 2);
11686 /* All bits in the REX prefix are ignored. */
11688 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11690 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11692 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11693 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11694 switch ((*codep
& 0x3))
11699 vex
.prefix
= DATA_PREFIX_OPCODE
;
11702 vex
.prefix
= REPE_PREFIX_OPCODE
;
11705 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11712 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11714 /* There is no MODRM byte for VEX 77. */
11715 if (vindex
!= 0x77)
11717 FETCH_DATA (info
, codep
+ 1);
11718 modrm
.mod
= (*codep
>> 6) & 3;
11719 modrm
.reg
= (*codep
>> 3) & 7;
11720 modrm
.rm
= *codep
& 7;
11724 case USE_VEX_W_TABLE
:
11728 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11731 case USE_EVEX_TABLE
:
11732 two_source_ops
= 0;
11735 FETCH_DATA (info
, codep
+ 4);
11736 /* All bits in the REX prefix are ignored. */
11738 /* The first byte after 0x62. */
11739 rex
= ~(*codep
>> 5) & 0x7;
11740 vex
.r
= *codep
& 0x10;
11741 switch ((*codep
& 0xf))
11744 return &bad_opcode
;
11746 vex_table_index
= EVEX_0F
;
11749 vex_table_index
= EVEX_0F38
;
11752 vex_table_index
= EVEX_0F3A
;
11756 /* The second byte after 0x62. */
11758 vex
.w
= *codep
& 0x80;
11759 if (vex
.w
&& address_mode
== mode_64bit
)
11762 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11765 if (!(*codep
& 0x4))
11766 return &bad_opcode
;
11768 switch ((*codep
& 0x3))
11773 vex
.prefix
= DATA_PREFIX_OPCODE
;
11776 vex
.prefix
= REPE_PREFIX_OPCODE
;
11779 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11783 /* The third byte after 0x62. */
11786 /* Remember the static rounding bits. */
11787 vex
.ll
= (*codep
>> 5) & 3;
11788 vex
.b
= (*codep
& 0x10) != 0;
11790 vex
.v
= *codep
& 0x8;
11791 vex
.mask_register_specifier
= *codep
& 0x7;
11792 vex
.zeroing
= *codep
& 0x80;
11794 if (address_mode
!= mode_64bit
)
11796 /* In 16/32-bit mode silently ignore following bits. */
11806 dp
= &evex_table
[vex_table_index
][vindex
];
11808 FETCH_DATA (info
, codep
+ 1);
11809 modrm
.mod
= (*codep
>> 6) & 3;
11810 modrm
.reg
= (*codep
>> 3) & 7;
11811 modrm
.rm
= *codep
& 7;
11813 /* Set vector length. */
11814 if (modrm
.mod
== 3 && vex
.b
)
11830 return &bad_opcode
;
11843 if (dp
->name
!= NULL
)
11846 return get_valid_dis386 (dp
, info
);
11850 get_sib (disassemble_info
*info
, int sizeflag
)
11852 /* If modrm.mod == 3, operand must be register. */
11854 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11858 FETCH_DATA (info
, codep
+ 2);
11859 sib
.index
= (codep
[1] >> 3) & 7;
11860 sib
.scale
= (codep
[1] >> 6) & 3;
11861 sib
.base
= codep
[1] & 7;
11866 print_insn (bfd_vma pc
, disassemble_info
*info
)
11868 const struct dis386
*dp
;
11870 char *op_txt
[MAX_OPERANDS
];
11872 int sizeflag
, orig_sizeflag
;
11874 struct dis_private priv
;
11877 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11878 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11879 address_mode
= mode_32bit
;
11880 else if (info
->mach
== bfd_mach_i386_i8086
)
11882 address_mode
= mode_16bit
;
11883 priv
.orig_sizeflag
= 0;
11886 address_mode
= mode_64bit
;
11888 if (intel_syntax
== (char) -1)
11889 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11891 for (p
= info
->disassembler_options
; p
!= NULL
; )
11893 if (CONST_STRNEQ (p
, "amd64"))
11895 else if (CONST_STRNEQ (p
, "intel64"))
11897 else if (CONST_STRNEQ (p
, "x86-64"))
11899 address_mode
= mode_64bit
;
11900 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11902 else if (CONST_STRNEQ (p
, "i386"))
11904 address_mode
= mode_32bit
;
11905 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11907 else if (CONST_STRNEQ (p
, "i8086"))
11909 address_mode
= mode_16bit
;
11910 priv
.orig_sizeflag
= 0;
11912 else if (CONST_STRNEQ (p
, "intel"))
11915 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11916 intel_mnemonic
= 1;
11918 else if (CONST_STRNEQ (p
, "att"))
11921 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11922 intel_mnemonic
= 0;
11924 else if (CONST_STRNEQ (p
, "addr"))
11926 if (address_mode
== mode_64bit
)
11928 if (p
[4] == '3' && p
[5] == '2')
11929 priv
.orig_sizeflag
&= ~AFLAG
;
11930 else if (p
[4] == '6' && p
[5] == '4')
11931 priv
.orig_sizeflag
|= AFLAG
;
11935 if (p
[4] == '1' && p
[5] == '6')
11936 priv
.orig_sizeflag
&= ~AFLAG
;
11937 else if (p
[4] == '3' && p
[5] == '2')
11938 priv
.orig_sizeflag
|= AFLAG
;
11941 else if (CONST_STRNEQ (p
, "data"))
11943 if (p
[4] == '1' && p
[5] == '6')
11944 priv
.orig_sizeflag
&= ~DFLAG
;
11945 else if (p
[4] == '3' && p
[5] == '2')
11946 priv
.orig_sizeflag
|= DFLAG
;
11948 else if (CONST_STRNEQ (p
, "suffix"))
11949 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11951 p
= strchr (p
, ',');
11956 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11958 (*info
->fprintf_func
) (info
->stream
,
11959 _("64-bit address is disabled"));
11965 names64
= intel_names64
;
11966 names32
= intel_names32
;
11967 names16
= intel_names16
;
11968 names8
= intel_names8
;
11969 names8rex
= intel_names8rex
;
11970 names_seg
= intel_names_seg
;
11971 names_mm
= intel_names_mm
;
11972 names_bnd
= intel_names_bnd
;
11973 names_xmm
= intel_names_xmm
;
11974 names_ymm
= intel_names_ymm
;
11975 names_zmm
= intel_names_zmm
;
11976 index64
= intel_index64
;
11977 index32
= intel_index32
;
11978 names_mask
= intel_names_mask
;
11979 index16
= intel_index16
;
11982 separator_char
= '+';
11987 names64
= att_names64
;
11988 names32
= att_names32
;
11989 names16
= att_names16
;
11990 names8
= att_names8
;
11991 names8rex
= att_names8rex
;
11992 names_seg
= att_names_seg
;
11993 names_mm
= att_names_mm
;
11994 names_bnd
= att_names_bnd
;
11995 names_xmm
= att_names_xmm
;
11996 names_ymm
= att_names_ymm
;
11997 names_zmm
= att_names_zmm
;
11998 index64
= att_index64
;
11999 index32
= att_index32
;
12000 names_mask
= att_names_mask
;
12001 index16
= att_index16
;
12004 separator_char
= ',';
12008 /* The output looks better if we put 7 bytes on a line, since that
12009 puts most long word instructions on a single line. Use 8 bytes
12011 if ((info
->mach
& bfd_mach_l1om
) != 0)
12012 info
->bytes_per_line
= 8;
12014 info
->bytes_per_line
= 7;
12016 info
->private_data
= &priv
;
12017 priv
.max_fetched
= priv
.the_buffer
;
12018 priv
.insn_start
= pc
;
12021 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12029 start_codep
= priv
.the_buffer
;
12030 codep
= priv
.the_buffer
;
12032 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12036 /* Getting here means we tried for data but didn't get it. That
12037 means we have an incomplete instruction of some sort. Just
12038 print the first byte as a prefix or a .byte pseudo-op. */
12039 if (codep
> priv
.the_buffer
)
12041 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12043 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12046 /* Just print the first byte as a .byte instruction. */
12047 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12048 (unsigned int) priv
.the_buffer
[0]);
12058 sizeflag
= priv
.orig_sizeflag
;
12060 if (!ckprefix () || rex_used
)
12062 /* Too many prefixes or unused REX prefixes. */
12064 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12066 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12068 prefix_name (all_prefixes
[i
], sizeflag
));
12072 insn_codep
= codep
;
12074 FETCH_DATA (info
, codep
+ 1);
12075 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12077 if (((prefixes
& PREFIX_FWAIT
)
12078 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12080 /* Handle prefixes before fwait. */
12081 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12083 (*info
->fprintf_func
) (info
->stream
, "%s ",
12084 prefix_name (all_prefixes
[i
], sizeflag
));
12085 (*info
->fprintf_func
) (info
->stream
, "fwait");
12089 if (*codep
== 0x0f)
12091 unsigned char threebyte
;
12094 FETCH_DATA (info
, codep
+ 1);
12095 threebyte
= *codep
;
12096 dp
= &dis386_twobyte
[threebyte
];
12097 need_modrm
= twobyte_has_modrm
[*codep
];
12102 dp
= &dis386
[*codep
];
12103 need_modrm
= onebyte_has_modrm
[*codep
];
12107 /* Save sizeflag for printing the extra prefixes later before updating
12108 it for mnemonic and operand processing. The prefix names depend
12109 only on the address mode. */
12110 orig_sizeflag
= sizeflag
;
12111 if (prefixes
& PREFIX_ADDR
)
12113 if ((prefixes
& PREFIX_DATA
))
12119 FETCH_DATA (info
, codep
+ 1);
12120 modrm
.mod
= (*codep
>> 6) & 3;
12121 modrm
.reg
= (*codep
>> 3) & 7;
12122 modrm
.rm
= *codep
& 7;
12128 memset (&vex
, 0, sizeof (vex
));
12130 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12132 get_sib (info
, sizeflag
);
12133 dofloat (sizeflag
);
12137 dp
= get_valid_dis386 (dp
, info
);
12138 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12140 get_sib (info
, sizeflag
);
12141 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12144 op_ad
= MAX_OPERANDS
- 1 - i
;
12146 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12147 /* For EVEX instruction after the last operand masking
12148 should be printed. */
12149 if (i
== 0 && vex
.evex
)
12151 /* Don't print {%k0}. */
12152 if (vex
.mask_register_specifier
)
12155 oappend (names_mask
[vex
.mask_register_specifier
]);
12165 /* Clear instruction information. */
12168 the_info
->insn_info_valid
= 0;
12169 the_info
->branch_delay_insns
= 0;
12170 the_info
->data_size
= 0;
12171 the_info
->insn_type
= dis_noninsn
;
12172 the_info
->target
= 0;
12173 the_info
->target2
= 0;
12176 /* Reset jump operation indicator. */
12177 op_is_jump
= FALSE
;
12180 int jump_detection
= 0;
12182 /* Extract flags. */
12183 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12185 if ((dp
->op
[i
].rtn
== OP_J
)
12186 || (dp
->op
[i
].rtn
== OP_indirE
))
12187 jump_detection
|= 1;
12188 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
12189 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
12190 jump_detection
|= 2;
12191 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
12192 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
12193 jump_detection
|= 4;
12196 /* Determine if this is a jump or branch. */
12197 if ((jump_detection
& 0x3) == 0x3)
12200 if (jump_detection
& 0x4)
12201 the_info
->insn_type
= dis_condbranch
;
12203 the_info
->insn_type
=
12204 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
12205 ? dis_jsr
: dis_branch
;
12209 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12210 are all 0s in inverted form. */
12211 if (need_vex
&& vex
.register_specifier
!= 0)
12213 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12214 return end_codep
- priv
.the_buffer
;
12217 /* Check if the REX prefix is used. */
12218 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
12219 all_prefixes
[last_rex_prefix
] = 0;
12221 /* Check if the SEG prefix is used. */
12222 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12223 | PREFIX_FS
| PREFIX_GS
)) != 0
12224 && (used_prefixes
& active_seg_prefix
) != 0)
12225 all_prefixes
[last_seg_prefix
] = 0;
12227 /* Check if the ADDR prefix is used. */
12228 if ((prefixes
& PREFIX_ADDR
) != 0
12229 && (used_prefixes
& PREFIX_ADDR
) != 0)
12230 all_prefixes
[last_addr_prefix
] = 0;
12232 /* Check if the DATA prefix is used. */
12233 if ((prefixes
& PREFIX_DATA
) != 0
12234 && (used_prefixes
& PREFIX_DATA
) != 0)
12235 all_prefixes
[last_data_prefix
] = 0;
12237 /* Print the extra prefixes. */
12239 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12240 if (all_prefixes
[i
])
12243 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12246 prefix_length
+= strlen (name
) + 1;
12247 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12250 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12251 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12252 used by putop and MMX/SSE operand and may be overriden by the
12253 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12255 if (dp
->prefix_requirement
== PREFIX_OPCODE
12256 && dp
!= &bad_opcode
12258 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
12260 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12262 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12264 && (used_prefixes
& PREFIX_DATA
) == 0))))
12266 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12267 return end_codep
- priv
.the_buffer
;
12270 /* Check maximum code length. */
12271 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12273 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12274 return MAX_CODE_LENGTH
;
12277 obufp
= mnemonicendp
;
12278 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12281 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12283 /* The enter and bound instructions are printed with operands in the same
12284 order as the intel book; everything else is printed in reverse order. */
12285 if (intel_syntax
|| two_source_ops
)
12289 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12290 op_txt
[i
] = op_out
[i
];
12292 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12293 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12295 op_txt
[2] = op_out
[3];
12296 op_txt
[3] = op_out
[2];
12299 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12301 op_ad
= op_index
[i
];
12302 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12303 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12304 riprel
= op_riprel
[i
];
12305 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12306 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12311 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12312 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12316 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12320 (*info
->fprintf_func
) (info
->stream
, ",");
12321 if (op_index
[i
] != -1 && !op_riprel
[i
])
12323 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
12325 if (the_info
&& op_is_jump
)
12327 the_info
->insn_info_valid
= 1;
12328 the_info
->branch_delay_insns
= 0;
12329 the_info
->data_size
= 0;
12330 the_info
->target
= target
;
12331 the_info
->target2
= 0;
12333 (*info
->print_address_func
) (target
, info
);
12336 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12340 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12341 if (op_index
[i
] != -1 && op_riprel
[i
])
12343 (*info
->fprintf_func
) (info
->stream
, " # ");
12344 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12345 + op_address
[op_index
[i
]]), info
);
12348 return codep
- priv
.the_buffer
;
12351 static const char *float_mem
[] = {
12426 static const unsigned char float_mem_mode
[] = {
12501 #define ST { OP_ST, 0 }
12502 #define STi { OP_STi, 0 }
12504 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12505 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12506 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12507 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12508 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12509 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12510 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12511 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12512 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12514 static const struct dis386 float_reg
[][8] = {
12517 { "fadd", { ST
, STi
}, 0 },
12518 { "fmul", { ST
, STi
}, 0 },
12519 { "fcom", { STi
}, 0 },
12520 { "fcomp", { STi
}, 0 },
12521 { "fsub", { ST
, STi
}, 0 },
12522 { "fsubr", { ST
, STi
}, 0 },
12523 { "fdiv", { ST
, STi
}, 0 },
12524 { "fdivr", { ST
, STi
}, 0 },
12528 { "fld", { STi
}, 0 },
12529 { "fxch", { STi
}, 0 },
12539 { "fcmovb", { ST
, STi
}, 0 },
12540 { "fcmove", { ST
, STi
}, 0 },
12541 { "fcmovbe",{ ST
, STi
}, 0 },
12542 { "fcmovu", { ST
, STi
}, 0 },
12550 { "fcmovnb",{ ST
, STi
}, 0 },
12551 { "fcmovne",{ ST
, STi
}, 0 },
12552 { "fcmovnbe",{ ST
, STi
}, 0 },
12553 { "fcmovnu",{ ST
, STi
}, 0 },
12555 { "fucomi", { ST
, STi
}, 0 },
12556 { "fcomi", { ST
, STi
}, 0 },
12561 { "fadd", { STi
, ST
}, 0 },
12562 { "fmul", { STi
, ST
}, 0 },
12565 { "fsub{!M|r}", { STi
, ST
}, 0 },
12566 { "fsub{M|}", { STi
, ST
}, 0 },
12567 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12568 { "fdiv{M|}", { STi
, ST
}, 0 },
12572 { "ffree", { STi
}, 0 },
12574 { "fst", { STi
}, 0 },
12575 { "fstp", { STi
}, 0 },
12576 { "fucom", { STi
}, 0 },
12577 { "fucomp", { STi
}, 0 },
12583 { "faddp", { STi
, ST
}, 0 },
12584 { "fmulp", { STi
, ST
}, 0 },
12587 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12588 { "fsub{M|}p", { STi
, ST
}, 0 },
12589 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12590 { "fdiv{M|}p", { STi
, ST
}, 0 },
12594 { "ffreep", { STi
}, 0 },
12599 { "fucomip", { ST
, STi
}, 0 },
12600 { "fcomip", { ST
, STi
}, 0 },
12605 static char *fgrps
[][8] = {
12608 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12613 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12618 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12623 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12628 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12633 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12638 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12643 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12644 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12649 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12654 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12659 swap_operand (void)
12661 mnemonicendp
[0] = '.';
12662 mnemonicendp
[1] = 's';
12667 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12668 int sizeflag ATTRIBUTE_UNUSED
)
12670 /* Skip mod/rm byte. */
12676 dofloat (int sizeflag
)
12678 const struct dis386
*dp
;
12679 unsigned char floatop
;
12681 floatop
= codep
[-1];
12683 if (modrm
.mod
!= 3)
12685 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12687 putop (float_mem
[fp_indx
], sizeflag
);
12690 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12693 /* Skip mod/rm byte. */
12697 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12698 if (dp
->name
== NULL
)
12700 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12702 /* Instruction fnstsw is only one with strange arg. */
12703 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12704 strcpy (op_out
[0], names16
[0]);
12708 putop (dp
->name
, sizeflag
);
12713 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12718 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12722 /* Like oappend (below), but S is a string starting with '%'.
12723 In Intel syntax, the '%' is elided. */
12725 oappend_maybe_intel (const char *s
)
12727 oappend (s
+ intel_syntax
);
12731 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12733 oappend_maybe_intel ("%st");
12737 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12739 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12740 oappend_maybe_intel (scratchbuf
);
12743 /* Capital letters in template are macros. */
12745 putop (const char *in_template
, int sizeflag
)
12750 unsigned int l
= 0, len
= 1;
12753 #define SAVE_LAST(c) \
12754 if (l < len && l < sizeof (last)) \
12759 for (p
= in_template
; *p
; p
++)
12775 while (*++p
!= '|')
12776 if (*p
== '}' || *p
== '\0')
12779 /* Fall through. */
12784 while (*++p
!= '}')
12795 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12799 if (l
== 0 && len
== 1)
12804 if (sizeflag
& SUFFIX_ALWAYS
)
12817 if (address_mode
== mode_64bit
12818 && !(prefixes
& PREFIX_ADDR
))
12829 if (intel_syntax
&& !alt
)
12831 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12833 if (sizeflag
& DFLAG
)
12834 *obufp
++ = intel_syntax
? 'd' : 'l';
12836 *obufp
++ = intel_syntax
? 'w' : 's';
12837 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12841 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12844 if (modrm
.mod
== 3)
12850 if (sizeflag
& DFLAG
)
12851 *obufp
++ = intel_syntax
? 'd' : 'l';
12854 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12860 case 'E': /* For jcxz/jecxz */
12861 if (address_mode
== mode_64bit
)
12863 if (sizeflag
& AFLAG
)
12869 if (sizeflag
& AFLAG
)
12871 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12876 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12878 if (sizeflag
& AFLAG
)
12879 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12881 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12882 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12886 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12888 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12892 if (!(rex
& REX_W
))
12893 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12898 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12899 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12901 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12904 if (prefixes
& PREFIX_DS
)
12923 if (l
!= 0 || len
!= 1)
12925 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12930 if (!need_vex
|| !vex
.evex
)
12933 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12935 switch (vex
.length
)
12953 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12958 /* Fall through. */
12961 if (l
!= 0 || len
!= 1)
12969 if (sizeflag
& SUFFIX_ALWAYS
)
12973 if (intel_mnemonic
!= cond
)
12977 if ((prefixes
& PREFIX_FWAIT
) == 0)
12980 used_prefixes
|= PREFIX_FWAIT
;
12986 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12990 if (!(rex
& REX_W
))
12991 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12995 && address_mode
== mode_64bit
12996 && isa64
== intel64
)
13001 /* Fall through. */
13004 && address_mode
== mode_64bit
13005 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13010 /* Fall through. */
13013 if (l
== 0 && len
== 1)
13018 if ((rex
& REX_W
) == 0
13019 && (prefixes
& PREFIX_DATA
))
13021 if ((sizeflag
& DFLAG
) == 0)
13023 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13027 if ((prefixes
& PREFIX_DATA
)
13029 || (sizeflag
& SUFFIX_ALWAYS
))
13036 if (sizeflag
& DFLAG
)
13040 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13046 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13052 if ((prefixes
& PREFIX_DATA
)
13054 || (sizeflag
& SUFFIX_ALWAYS
))
13061 if (sizeflag
& DFLAG
)
13062 *obufp
++ = intel_syntax
? 'd' : 'l';
13065 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13073 if (address_mode
== mode_64bit
13074 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13076 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13080 /* Fall through. */
13083 if (l
== 0 && len
== 1)
13086 if (intel_syntax
&& !alt
)
13089 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13095 if (sizeflag
& DFLAG
)
13096 *obufp
++ = intel_syntax
? 'd' : 'l';
13099 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13105 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13111 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13126 else if (sizeflag
& DFLAG
)
13135 if (intel_syntax
&& !p
[1]
13136 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13138 if (!(rex
& REX_W
))
13139 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13142 if (l
== 0 && len
== 1)
13146 if (address_mode
== mode_64bit
13147 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13149 if (sizeflag
& SUFFIX_ALWAYS
)
13171 /* Fall through. */
13174 if (l
== 0 && len
== 1)
13179 if (sizeflag
& SUFFIX_ALWAYS
)
13185 if (sizeflag
& DFLAG
)
13189 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13203 if (address_mode
== mode_64bit
13204 && !(prefixes
& PREFIX_ADDR
))
13215 if (l
!= 0 || len
!= 1)
13220 if (need_vex
&& vex
.prefix
)
13222 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
13229 if (prefixes
& PREFIX_DATA
)
13233 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13237 if (l
== 0 && len
== 1)
13241 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13249 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13251 switch (vex
.length
)
13267 if (l
== 0 && len
== 1)
13269 /* operand size flag for cwtl, cbtw */
13278 else if (sizeflag
& DFLAG
)
13282 if (!(rex
& REX_W
))
13283 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13290 && last
[0] != 'L'))
13297 if (last
[0] == 'X')
13298 *obufp
++ = vex
.w
? 'd': 's';
13300 *obufp
++ = vex
.w
? 'q': 'd';
13306 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13308 if (sizeflag
& DFLAG
)
13312 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13318 if (address_mode
== mode_64bit
13319 && (isa64
== intel64
13320 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13322 else if ((prefixes
& PREFIX_DATA
))
13324 if (!(sizeflag
& DFLAG
))
13326 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13333 mnemonicendp
= obufp
;
13338 oappend (const char *s
)
13340 obufp
= stpcpy (obufp
, s
);
13346 /* Only print the active segment register. */
13347 if (!active_seg_prefix
)
13350 used_prefixes
|= active_seg_prefix
;
13351 switch (active_seg_prefix
)
13354 oappend_maybe_intel ("%cs:");
13357 oappend_maybe_intel ("%ds:");
13360 oappend_maybe_intel ("%ss:");
13363 oappend_maybe_intel ("%es:");
13366 oappend_maybe_intel ("%fs:");
13369 oappend_maybe_intel ("%gs:");
13377 OP_indirE (int bytemode
, int sizeflag
)
13381 OP_E (bytemode
, sizeflag
);
13385 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13387 if (address_mode
== mode_64bit
)
13395 sprintf_vma (tmp
, disp
);
13396 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13397 strcpy (buf
+ 2, tmp
+ i
);
13401 bfd_signed_vma v
= disp
;
13408 /* Check for possible overflow on 0x8000000000000000. */
13411 strcpy (buf
, "9223372036854775808");
13425 tmp
[28 - i
] = (v
% 10) + '0';
13429 strcpy (buf
, tmp
+ 29 - i
);
13435 sprintf (buf
, "0x%x", (unsigned int) disp
);
13437 sprintf (buf
, "%d", (int) disp
);
13441 /* Put DISP in BUF as signed hex number. */
13444 print_displacement (char *buf
, bfd_vma disp
)
13446 bfd_signed_vma val
= disp
;
13455 /* Check for possible overflow. */
13458 switch (address_mode
)
13461 strcpy (buf
+ j
, "0x8000000000000000");
13464 strcpy (buf
+ j
, "0x80000000");
13467 strcpy (buf
+ j
, "0x8000");
13477 sprintf_vma (tmp
, (bfd_vma
) val
);
13478 for (i
= 0; tmp
[i
] == '0'; i
++)
13480 if (tmp
[i
] == '\0')
13482 strcpy (buf
+ j
, tmp
+ i
);
13486 intel_operand_size (int bytemode
, int sizeflag
)
13490 && (bytemode
== x_mode
13491 || bytemode
== evex_half_bcst_xmmq_mode
))
13494 oappend ("QWORD PTR ");
13496 oappend ("DWORD PTR ");
13505 oappend ("BYTE PTR ");
13510 oappend ("WORD PTR ");
13513 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13515 oappend ("QWORD PTR ");
13518 /* Fall through. */
13520 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13522 oappend ("QWORD PTR ");
13525 /* Fall through. */
13531 oappend ("QWORD PTR ");
13534 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13535 oappend ("DWORD PTR ");
13537 oappend ("WORD PTR ");
13538 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13542 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13544 oappend ("WORD PTR ");
13545 if (!(rex
& REX_W
))
13546 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13549 if (sizeflag
& DFLAG
)
13550 oappend ("QWORD PTR ");
13552 oappend ("DWORD PTR ");
13553 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13556 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13557 oappend ("WORD PTR ");
13559 oappend ("DWORD PTR ");
13560 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13563 case d_scalar_mode
:
13564 case d_scalar_swap_mode
:
13567 oappend ("DWORD PTR ");
13570 case q_scalar_mode
:
13571 case q_scalar_swap_mode
:
13573 oappend ("QWORD PTR ");
13576 if (address_mode
== mode_64bit
)
13577 oappend ("QWORD PTR ");
13579 oappend ("DWORD PTR ");
13582 if (sizeflag
& DFLAG
)
13583 oappend ("FWORD PTR ");
13585 oappend ("DWORD PTR ");
13586 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13589 oappend ("TBYTE PTR ");
13593 case evex_x_gscat_mode
:
13594 case evex_x_nobcst_mode
:
13595 case b_scalar_mode
:
13596 case w_scalar_mode
:
13599 switch (vex
.length
)
13602 oappend ("XMMWORD PTR ");
13605 oappend ("YMMWORD PTR ");
13608 oappend ("ZMMWORD PTR ");
13615 oappend ("XMMWORD PTR ");
13618 oappend ("XMMWORD PTR ");
13621 oappend ("YMMWORD PTR ");
13624 case evex_half_bcst_xmmq_mode
:
13628 switch (vex
.length
)
13631 oappend ("QWORD PTR ");
13634 oappend ("XMMWORD PTR ");
13637 oappend ("YMMWORD PTR ");
13647 switch (vex
.length
)
13652 oappend ("BYTE PTR ");
13662 switch (vex
.length
)
13667 oappend ("WORD PTR ");
13677 switch (vex
.length
)
13682 oappend ("DWORD PTR ");
13692 switch (vex
.length
)
13697 oappend ("QWORD PTR ");
13707 switch (vex
.length
)
13710 oappend ("WORD PTR ");
13713 oappend ("DWORD PTR ");
13716 oappend ("QWORD PTR ");
13726 switch (vex
.length
)
13729 oappend ("DWORD PTR ");
13732 oappend ("QWORD PTR ");
13735 oappend ("XMMWORD PTR ");
13745 switch (vex
.length
)
13748 oappend ("QWORD PTR ");
13751 oappend ("YMMWORD PTR ");
13754 oappend ("ZMMWORD PTR ");
13764 switch (vex
.length
)
13768 oappend ("XMMWORD PTR ");
13775 oappend ("OWORD PTR ");
13778 case vex_w_dq_mode
:
13779 case vex_scalar_w_dq_mode
:
13784 oappend ("QWORD PTR ");
13786 oappend ("DWORD PTR ");
13788 case vex_vsib_d_w_dq_mode
:
13789 case vex_vsib_q_w_dq_mode
:
13796 oappend ("QWORD PTR ");
13798 oappend ("DWORD PTR ");
13802 switch (vex
.length
)
13805 oappend ("XMMWORD PTR ");
13808 oappend ("YMMWORD PTR ");
13811 oappend ("ZMMWORD PTR ");
13818 case vex_vsib_q_w_d_mode
:
13819 case vex_vsib_d_w_d_mode
:
13820 if (!need_vex
|| !vex
.evex
)
13823 switch (vex
.length
)
13826 oappend ("QWORD PTR ");
13829 oappend ("XMMWORD PTR ");
13832 oappend ("YMMWORD PTR ");
13840 if (!need_vex
|| vex
.length
!= 128)
13843 oappend ("DWORD PTR ");
13845 oappend ("BYTE PTR ");
13851 oappend ("QWORD PTR ");
13853 oappend ("WORD PTR ");
13863 OP_E_register (int bytemode
, int sizeflag
)
13865 int reg
= modrm
.rm
;
13866 const char **names
;
13872 if ((sizeflag
& SUFFIX_ALWAYS
)
13873 && (bytemode
== b_swap_mode
13874 || bytemode
== bnd_swap_mode
13875 || bytemode
== v_swap_mode
))
13901 names
= address_mode
== mode_64bit
? names64
: names32
;
13904 case bnd_swap_mode
:
13913 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13918 /* Fall through. */
13920 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13926 /* Fall through. */
13938 if ((sizeflag
& DFLAG
)
13939 || (bytemode
!= v_mode
13940 && bytemode
!= v_swap_mode
))
13944 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13948 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13952 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13955 names
= (address_mode
== mode_64bit
13956 ? names64
: names32
);
13957 if (!(prefixes
& PREFIX_ADDR
))
13958 names
= (address_mode
== mode_16bit
13959 ? names16
: names
);
13962 /* Remove "addr16/addr32". */
13963 all_prefixes
[last_addr_prefix
] = 0;
13964 names
= (address_mode
!= mode_32bit
13965 ? names32
: names16
);
13966 used_prefixes
|= PREFIX_ADDR
;
13976 names
= names_mask
;
13981 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13984 oappend (names
[reg
]);
13988 OP_E_memory (int bytemode
, int sizeflag
)
13991 int add
= (rex
& REX_B
) ? 8 : 0;
13997 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13999 && bytemode
!= x_mode
14000 && bytemode
!= xmmq_mode
14001 && bytemode
!= evex_half_bcst_xmmq_mode
)
14017 if (address_mode
!= mode_64bit
)
14023 case vex_vsib_d_w_dq_mode
:
14024 case vex_vsib_d_w_d_mode
:
14025 case vex_vsib_q_w_dq_mode
:
14026 case vex_vsib_q_w_d_mode
:
14027 case evex_x_gscat_mode
:
14029 shift
= vex
.w
? 3 : 2;
14032 case evex_half_bcst_xmmq_mode
:
14036 shift
= vex
.w
? 3 : 2;
14039 /* Fall through. */
14043 case evex_x_nobcst_mode
:
14045 switch (vex
.length
)
14068 case q_scalar_mode
:
14070 case q_scalar_swap_mode
:
14076 case d_scalar_mode
:
14078 case d_scalar_swap_mode
:
14081 case w_scalar_mode
:
14085 case b_scalar_mode
:
14092 /* Make necessary corrections to shift for modes that need it.
14093 For these modes we currently have shift 4, 5 or 6 depending on
14094 vex.length (it corresponds to xmmword, ymmword or zmmword
14095 operand). We might want to make it 3, 4 or 5 (e.g. for
14096 xmmq_mode). In case of broadcast enabled the corrections
14097 aren't needed, as element size is always 32 or 64 bits. */
14099 && (bytemode
== xmmq_mode
14100 || bytemode
== evex_half_bcst_xmmq_mode
))
14102 else if (bytemode
== xmmqd_mode
)
14104 else if (bytemode
== xmmdw_mode
)
14106 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14114 intel_operand_size (bytemode
, sizeflag
);
14117 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14119 /* 32/64 bit address mode */
14129 int addr32flag
= !((sizeflag
& AFLAG
)
14130 || bytemode
== v_bnd_mode
14131 || bytemode
== v_bndmk_mode
14132 || bytemode
== bnd_mode
14133 || bytemode
== bnd_swap_mode
);
14134 const char **indexes64
= names64
;
14135 const char **indexes32
= names32
;
14145 vindex
= sib
.index
;
14151 case vex_vsib_d_w_dq_mode
:
14152 case vex_vsib_d_w_d_mode
:
14153 case vex_vsib_q_w_dq_mode
:
14154 case vex_vsib_q_w_d_mode
:
14164 switch (vex
.length
)
14167 indexes64
= indexes32
= names_xmm
;
14171 || bytemode
== vex_vsib_q_w_dq_mode
14172 || bytemode
== vex_vsib_q_w_d_mode
)
14173 indexes64
= indexes32
= names_ymm
;
14175 indexes64
= indexes32
= names_xmm
;
14179 || bytemode
== vex_vsib_q_w_dq_mode
14180 || bytemode
== vex_vsib_q_w_d_mode
)
14181 indexes64
= indexes32
= names_zmm
;
14183 indexes64
= indexes32
= names_ymm
;
14190 haveindex
= vindex
!= 4;
14197 rbase
= base
+ add
;
14205 if (address_mode
== mode_64bit
&& !havesib
)
14208 if (riprel
&& bytemode
== v_bndmk_mode
)
14216 FETCH_DATA (the_info
, codep
+ 1);
14218 if ((disp
& 0x80) != 0)
14220 if (vex
.evex
&& shift
> 0)
14233 && address_mode
!= mode_16bit
)
14235 if (address_mode
== mode_64bit
)
14237 /* Display eiz instead of addr32. */
14238 needindex
= addr32flag
;
14243 /* In 32-bit mode, we need index register to tell [offset]
14244 from [eiz*1 + offset]. */
14249 havedisp
= (havebase
14251 || (havesib
&& (haveindex
|| scale
!= 0)));
14254 if (modrm
.mod
!= 0 || base
== 5)
14256 if (havedisp
|| riprel
)
14257 print_displacement (scratchbuf
, disp
);
14259 print_operand_value (scratchbuf
, 1, disp
);
14260 oappend (scratchbuf
);
14264 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14268 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14269 && (bytemode
!= v_bnd_mode
)
14270 && (bytemode
!= v_bndmk_mode
)
14271 && (bytemode
!= bnd_mode
)
14272 && (bytemode
!= bnd_swap_mode
))
14273 used_prefixes
|= PREFIX_ADDR
;
14275 if (havedisp
|| (intel_syntax
&& riprel
))
14277 *obufp
++ = open_char
;
14278 if (intel_syntax
&& riprel
)
14281 oappend (!addr32flag
? "rip" : "eip");
14285 oappend (address_mode
== mode_64bit
&& !addr32flag
14286 ? names64
[rbase
] : names32
[rbase
]);
14289 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14290 print index to tell base + index from base. */
14294 || (havebase
&& base
!= ESP_REG_NUM
))
14296 if (!intel_syntax
|| havebase
)
14298 *obufp
++ = separator_char
;
14302 oappend (address_mode
== mode_64bit
&& !addr32flag
14303 ? indexes64
[vindex
] : indexes32
[vindex
]);
14305 oappend (address_mode
== mode_64bit
&& !addr32flag
14306 ? index64
: index32
);
14308 *obufp
++ = scale_char
;
14310 sprintf (scratchbuf
, "%d", 1 << scale
);
14311 oappend (scratchbuf
);
14315 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14317 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14322 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14326 disp
= - (bfd_signed_vma
) disp
;
14330 print_displacement (scratchbuf
, disp
);
14332 print_operand_value (scratchbuf
, 1, disp
);
14333 oappend (scratchbuf
);
14336 *obufp
++ = close_char
;
14339 else if (intel_syntax
)
14341 if (modrm
.mod
!= 0 || base
== 5)
14343 if (!active_seg_prefix
)
14345 oappend (names_seg
[ds_reg
- es_reg
]);
14348 print_operand_value (scratchbuf
, 1, disp
);
14349 oappend (scratchbuf
);
14355 /* 16 bit address mode */
14356 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14363 if ((disp
& 0x8000) != 0)
14368 FETCH_DATA (the_info
, codep
+ 1);
14370 if ((disp
& 0x80) != 0)
14372 if (vex
.evex
&& shift
> 0)
14377 if ((disp
& 0x8000) != 0)
14383 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14385 print_displacement (scratchbuf
, disp
);
14386 oappend (scratchbuf
);
14389 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14391 *obufp
++ = open_char
;
14393 oappend (index16
[modrm
.rm
]);
14395 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14397 if ((bfd_signed_vma
) disp
>= 0)
14402 else if (modrm
.mod
!= 1)
14406 disp
= - (bfd_signed_vma
) disp
;
14409 print_displacement (scratchbuf
, disp
);
14410 oappend (scratchbuf
);
14413 *obufp
++ = close_char
;
14416 else if (intel_syntax
)
14418 if (!active_seg_prefix
)
14420 oappend (names_seg
[ds_reg
- es_reg
]);
14423 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14424 oappend (scratchbuf
);
14427 if (vex
.evex
&& vex
.b
14428 && (bytemode
== x_mode
14429 || bytemode
== xmmq_mode
14430 || bytemode
== evex_half_bcst_xmmq_mode
))
14433 || bytemode
== xmmq_mode
14434 || bytemode
== evex_half_bcst_xmmq_mode
)
14436 switch (vex
.length
)
14439 oappend ("{1to2}");
14442 oappend ("{1to4}");
14445 oappend ("{1to8}");
14453 switch (vex
.length
)
14456 oappend ("{1to4}");
14459 oappend ("{1to8}");
14462 oappend ("{1to16}");
14472 OP_E (int bytemode
, int sizeflag
)
14474 /* Skip mod/rm byte. */
14478 if (modrm
.mod
== 3)
14479 OP_E_register (bytemode
, sizeflag
);
14481 OP_E_memory (bytemode
, sizeflag
);
14485 OP_G (int bytemode
, int sizeflag
)
14488 const char **names
;
14497 oappend (names8rex
[modrm
.reg
+ add
]);
14499 oappend (names8
[modrm
.reg
+ add
]);
14502 oappend (names16
[modrm
.reg
+ add
]);
14507 oappend (names32
[modrm
.reg
+ add
]);
14510 oappend (names64
[modrm
.reg
+ add
]);
14513 if (modrm
.reg
> 0x3)
14518 oappend (names_bnd
[modrm
.reg
]);
14528 oappend (names64
[modrm
.reg
+ add
]);
14531 if ((sizeflag
& DFLAG
)
14532 || (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
))
14533 oappend (names32
[modrm
.reg
+ add
]);
14535 oappend (names16
[modrm
.reg
+ add
]);
14536 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14540 names
= (address_mode
== mode_64bit
14541 ? names64
: names32
);
14542 if (!(prefixes
& PREFIX_ADDR
))
14544 if (address_mode
== mode_16bit
)
14549 /* Remove "addr16/addr32". */
14550 all_prefixes
[last_addr_prefix
] = 0;
14551 names
= (address_mode
!= mode_32bit
14552 ? names32
: names16
);
14553 used_prefixes
|= PREFIX_ADDR
;
14555 oappend (names
[modrm
.reg
+ add
]);
14558 if (address_mode
== mode_64bit
)
14559 oappend (names64
[modrm
.reg
+ add
]);
14561 oappend (names32
[modrm
.reg
+ add
]);
14565 if ((modrm
.reg
+ add
) > 0x7)
14570 oappend (names_mask
[modrm
.reg
+ add
]);
14573 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14586 FETCH_DATA (the_info
, codep
+ 8);
14587 a
= *codep
++ & 0xff;
14588 a
|= (*codep
++ & 0xff) << 8;
14589 a
|= (*codep
++ & 0xff) << 16;
14590 a
|= (*codep
++ & 0xffu
) << 24;
14591 b
= *codep
++ & 0xff;
14592 b
|= (*codep
++ & 0xff) << 8;
14593 b
|= (*codep
++ & 0xff) << 16;
14594 b
|= (*codep
++ & 0xffu
) << 24;
14595 x
= a
+ ((bfd_vma
) b
<< 32);
14603 static bfd_signed_vma
14606 bfd_signed_vma x
= 0;
14608 FETCH_DATA (the_info
, codep
+ 4);
14609 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14610 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14611 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14612 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14616 static bfd_signed_vma
14619 bfd_signed_vma x
= 0;
14621 FETCH_DATA (the_info
, codep
+ 4);
14622 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14623 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14624 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14625 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14627 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14637 FETCH_DATA (the_info
, codep
+ 2);
14638 x
= *codep
++ & 0xff;
14639 x
|= (*codep
++ & 0xff) << 8;
14644 set_op (bfd_vma op
, int riprel
)
14646 op_index
[op_ad
] = op_ad
;
14647 if (address_mode
== mode_64bit
)
14649 op_address
[op_ad
] = op
;
14650 op_riprel
[op_ad
] = riprel
;
14654 /* Mask to get a 32-bit address. */
14655 op_address
[op_ad
] = op
& 0xffffffff;
14656 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14661 OP_REG (int code
, int sizeflag
)
14668 case es_reg
: case ss_reg
: case cs_reg
:
14669 case ds_reg
: case fs_reg
: case gs_reg
:
14670 oappend (names_seg
[code
- es_reg
]);
14682 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14683 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14684 s
= names16
[code
- ax_reg
+ add
];
14686 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14687 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14690 s
= names8rex
[code
- al_reg
+ add
];
14692 s
= names8
[code
- al_reg
];
14694 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14695 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14696 if (address_mode
== mode_64bit
14697 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14699 s
= names64
[code
- rAX_reg
+ add
];
14702 code
+= eAX_reg
- rAX_reg
;
14703 /* Fall through. */
14704 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14705 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14708 s
= names64
[code
- eAX_reg
+ add
];
14711 if (sizeflag
& DFLAG
)
14712 s
= names32
[code
- eAX_reg
+ add
];
14714 s
= names16
[code
- eAX_reg
+ add
];
14715 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14719 s
= INTERNAL_DISASSEMBLER_ERROR
;
14726 OP_IMREG (int code
, int sizeflag
)
14738 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14739 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14740 s
= names16
[code
- ax_reg
];
14742 case es_reg
: case ss_reg
: case cs_reg
:
14743 case ds_reg
: case fs_reg
: case gs_reg
:
14744 s
= names_seg
[code
- es_reg
];
14746 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14747 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14750 s
= names8rex
[code
- al_reg
];
14752 s
= names8
[code
- al_reg
];
14754 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14755 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14758 s
= names64
[code
- eAX_reg
];
14761 if (sizeflag
& DFLAG
)
14762 s
= names32
[code
- eAX_reg
];
14764 s
= names16
[code
- eAX_reg
];
14765 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14768 case z_mode_ax_reg
:
14769 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14773 if (!(rex
& REX_W
))
14774 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14777 s
= INTERNAL_DISASSEMBLER_ERROR
;
14784 OP_I (int bytemode
, int sizeflag
)
14787 bfd_signed_vma mask
= -1;
14792 FETCH_DATA (the_info
, codep
+ 1);
14802 if (sizeflag
& DFLAG
)
14812 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14828 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14833 scratchbuf
[0] = '$';
14834 print_operand_value (scratchbuf
+ 1, 1, op
);
14835 oappend_maybe_intel (scratchbuf
);
14836 scratchbuf
[0] = '\0';
14840 OP_I64 (int bytemode
, int sizeflag
)
14842 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
14844 OP_I (bytemode
, sizeflag
);
14850 scratchbuf
[0] = '$';
14851 print_operand_value (scratchbuf
+ 1, 1, get64 ());
14852 oappend_maybe_intel (scratchbuf
);
14853 scratchbuf
[0] = '\0';
14857 OP_sI (int bytemode
, int sizeflag
)
14865 FETCH_DATA (the_info
, codep
+ 1);
14867 if ((op
& 0x80) != 0)
14869 if (bytemode
== b_T_mode
)
14871 if (address_mode
!= mode_64bit
14872 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14874 /* The operand-size prefix is overridden by a REX prefix. */
14875 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14883 if (!(rex
& REX_W
))
14885 if (sizeflag
& DFLAG
)
14893 /* The operand-size prefix is overridden by a REX prefix. */
14894 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14900 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14904 scratchbuf
[0] = '$';
14905 print_operand_value (scratchbuf
+ 1, 1, op
);
14906 oappend_maybe_intel (scratchbuf
);
14910 OP_J (int bytemode
, int sizeflag
)
14914 bfd_vma segment
= 0;
14919 FETCH_DATA (the_info
, codep
+ 1);
14921 if ((disp
& 0x80) != 0)
14925 if (isa64
!= intel64
)
14928 if ((sizeflag
& DFLAG
)
14929 || (address_mode
== mode_64bit
14930 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
14931 || (rex
& REX_W
))))
14936 if ((disp
& 0x8000) != 0)
14938 /* In 16bit mode, address is wrapped around at 64k within
14939 the same segment. Otherwise, a data16 prefix on a jump
14940 instruction means that the pc is masked to 16 bits after
14941 the displacement is added! */
14943 if ((prefixes
& PREFIX_DATA
) == 0)
14944 segment
= ((start_pc
+ (codep
- start_codep
))
14945 & ~((bfd_vma
) 0xffff));
14947 if (address_mode
!= mode_64bit
14948 || (isa64
!= intel64
&& !(rex
& REX_W
)))
14949 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14952 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14955 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14957 print_operand_value (scratchbuf
, 1, disp
);
14958 oappend (scratchbuf
);
14962 OP_SEG (int bytemode
, int sizeflag
)
14964 if (bytemode
== w_mode
)
14965 oappend (names_seg
[modrm
.reg
]);
14967 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14971 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14975 if (sizeflag
& DFLAG
)
14985 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14987 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14989 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14990 oappend (scratchbuf
);
14994 OP_OFF (int bytemode
, int sizeflag
)
14998 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14999 intel_operand_size (bytemode
, sizeflag
);
15002 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15009 if (!active_seg_prefix
)
15011 oappend (names_seg
[ds_reg
- es_reg
]);
15015 print_operand_value (scratchbuf
, 1, off
);
15016 oappend (scratchbuf
);
15020 OP_OFF64 (int bytemode
, int sizeflag
)
15024 if (address_mode
!= mode_64bit
15025 || (prefixes
& PREFIX_ADDR
))
15027 OP_OFF (bytemode
, sizeflag
);
15031 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15032 intel_operand_size (bytemode
, sizeflag
);
15039 if (!active_seg_prefix
)
15041 oappend (names_seg
[ds_reg
- es_reg
]);
15045 print_operand_value (scratchbuf
, 1, off
);
15046 oappend (scratchbuf
);
15050 ptr_reg (int code
, int sizeflag
)
15054 *obufp
++ = open_char
;
15055 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15056 if (address_mode
== mode_64bit
)
15058 if (!(sizeflag
& AFLAG
))
15059 s
= names32
[code
- eAX_reg
];
15061 s
= names64
[code
- eAX_reg
];
15063 else if (sizeflag
& AFLAG
)
15064 s
= names32
[code
- eAX_reg
];
15066 s
= names16
[code
- eAX_reg
];
15068 *obufp
++ = close_char
;
15073 OP_ESreg (int code
, int sizeflag
)
15079 case 0x6d: /* insw/insl */
15080 intel_operand_size (z_mode
, sizeflag
);
15082 case 0xa5: /* movsw/movsl/movsq */
15083 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15084 case 0xab: /* stosw/stosl */
15085 case 0xaf: /* scasw/scasl */
15086 intel_operand_size (v_mode
, sizeflag
);
15089 intel_operand_size (b_mode
, sizeflag
);
15092 oappend_maybe_intel ("%es:");
15093 ptr_reg (code
, sizeflag
);
15097 OP_DSreg (int code
, int sizeflag
)
15103 case 0x6f: /* outsw/outsl */
15104 intel_operand_size (z_mode
, sizeflag
);
15106 case 0xa5: /* movsw/movsl/movsq */
15107 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15108 case 0xad: /* lodsw/lodsl/lodsq */
15109 intel_operand_size (v_mode
, sizeflag
);
15112 intel_operand_size (b_mode
, sizeflag
);
15115 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15116 default segment register DS is printed. */
15117 if (!active_seg_prefix
)
15118 active_seg_prefix
= PREFIX_DS
;
15120 ptr_reg (code
, sizeflag
);
15124 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15132 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15134 all_prefixes
[last_lock_prefix
] = 0;
15135 used_prefixes
|= PREFIX_LOCK
;
15140 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15141 oappend_maybe_intel (scratchbuf
);
15145 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15154 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15156 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15157 oappend (scratchbuf
);
15161 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15163 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15164 oappend_maybe_intel (scratchbuf
);
15168 OP_R (int bytemode
, int sizeflag
)
15170 /* Skip mod/rm byte. */
15173 OP_E_register (bytemode
, sizeflag
);
15177 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15179 int reg
= modrm
.reg
;
15180 const char **names
;
15182 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15183 if (prefixes
& PREFIX_DATA
)
15192 oappend (names
[reg
]);
15196 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15198 int reg
= modrm
.reg
;
15199 const char **names
;
15211 && bytemode
!= xmm_mode
15212 && bytemode
!= xmmq_mode
15213 && bytemode
!= evex_half_bcst_xmmq_mode
15214 && bytemode
!= ymm_mode
15215 && bytemode
!= scalar_mode
)
15217 switch (vex
.length
)
15224 || (bytemode
!= vex_vsib_q_w_dq_mode
15225 && bytemode
!= vex_vsib_q_w_d_mode
))
15237 else if (bytemode
== xmmq_mode
15238 || bytemode
== evex_half_bcst_xmmq_mode
)
15240 switch (vex
.length
)
15253 else if (bytemode
== ymm_mode
)
15257 oappend (names
[reg
]);
15261 OP_EM (int bytemode
, int sizeflag
)
15264 const char **names
;
15266 if (modrm
.mod
!= 3)
15269 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15271 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15272 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15274 OP_E (bytemode
, sizeflag
);
15278 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15281 /* Skip mod/rm byte. */
15284 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15286 if (prefixes
& PREFIX_DATA
)
15295 oappend (names
[reg
]);
15298 /* cvt* are the only instructions in sse2 which have
15299 both SSE and MMX operands and also have 0x66 prefix
15300 in their opcode. 0x66 was originally used to differentiate
15301 between SSE and MMX instruction(operands). So we have to handle the
15302 cvt* separately using OP_EMC and OP_MXC */
15304 OP_EMC (int bytemode
, int sizeflag
)
15306 if (modrm
.mod
!= 3)
15308 if (intel_syntax
&& bytemode
== v_mode
)
15310 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15311 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15313 OP_E (bytemode
, sizeflag
);
15317 /* Skip mod/rm byte. */
15320 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15321 oappend (names_mm
[modrm
.rm
]);
15325 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15327 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15328 oappend (names_mm
[modrm
.reg
]);
15332 OP_EX (int bytemode
, int sizeflag
)
15335 const char **names
;
15337 /* Skip mod/rm byte. */
15341 if (modrm
.mod
!= 3)
15343 OP_E_memory (bytemode
, sizeflag
);
15358 if ((sizeflag
& SUFFIX_ALWAYS
)
15359 && (bytemode
== x_swap_mode
15360 || bytemode
== d_swap_mode
15361 || bytemode
== d_scalar_swap_mode
15362 || bytemode
== q_swap_mode
15363 || bytemode
== q_scalar_swap_mode
))
15367 && bytemode
!= xmm_mode
15368 && bytemode
!= xmmdw_mode
15369 && bytemode
!= xmmqd_mode
15370 && bytemode
!= xmm_mb_mode
15371 && bytemode
!= xmm_mw_mode
15372 && bytemode
!= xmm_md_mode
15373 && bytemode
!= xmm_mq_mode
15374 && bytemode
!= xmm_mdq_mode
15375 && bytemode
!= xmmq_mode
15376 && bytemode
!= evex_half_bcst_xmmq_mode
15377 && bytemode
!= ymm_mode
15378 && bytemode
!= d_scalar_mode
15379 && bytemode
!= d_scalar_swap_mode
15380 && bytemode
!= q_scalar_mode
15381 && bytemode
!= q_scalar_swap_mode
15382 && bytemode
!= vex_scalar_w_dq_mode
)
15384 switch (vex
.length
)
15399 else if (bytemode
== xmmq_mode
15400 || bytemode
== evex_half_bcst_xmmq_mode
)
15402 switch (vex
.length
)
15415 else if (bytemode
== ymm_mode
)
15419 oappend (names
[reg
]);
15423 OP_MS (int bytemode
, int sizeflag
)
15425 if (modrm
.mod
== 3)
15426 OP_EM (bytemode
, sizeflag
);
15432 OP_XS (int bytemode
, int sizeflag
)
15434 if (modrm
.mod
== 3)
15435 OP_EX (bytemode
, sizeflag
);
15441 OP_M (int bytemode
, int sizeflag
)
15443 if (modrm
.mod
== 3)
15444 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15447 OP_E (bytemode
, sizeflag
);
15451 OP_0f07 (int bytemode
, int sizeflag
)
15453 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15456 OP_E (bytemode
, sizeflag
);
15459 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15460 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15463 NOP_Fixup1 (int bytemode
, int sizeflag
)
15465 if ((prefixes
& PREFIX_DATA
) != 0
15468 && address_mode
== mode_64bit
))
15469 OP_REG (bytemode
, sizeflag
);
15471 strcpy (obuf
, "nop");
15475 NOP_Fixup2 (int bytemode
, int sizeflag
)
15477 if ((prefixes
& PREFIX_DATA
) != 0
15480 && address_mode
== mode_64bit
))
15481 OP_IMREG (bytemode
, sizeflag
);
15484 static const char *const Suffix3DNow
[] = {
15485 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15486 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15487 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15488 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15489 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15490 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15491 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15492 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15493 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15494 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15495 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15496 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15497 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15498 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15499 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15500 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15501 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15502 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15503 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15504 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15505 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15506 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15507 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15508 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15509 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15510 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15511 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15512 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15513 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15514 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15515 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15516 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15517 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15518 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15519 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15520 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15521 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15522 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15523 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15524 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15525 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15526 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15527 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15528 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15529 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15530 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15531 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15532 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15533 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15534 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15535 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15536 /* CC */ NULL
, NULL
, NULL
, NULL
,
15537 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15538 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15539 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15540 /* DC */ NULL
, NULL
, NULL
, NULL
,
15541 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15542 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15543 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15544 /* EC */ NULL
, NULL
, NULL
, NULL
,
15545 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15546 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15547 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15548 /* FC */ NULL
, NULL
, NULL
, NULL
,
15552 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15554 const char *mnemonic
;
15556 FETCH_DATA (the_info
, codep
+ 1);
15557 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15558 place where an 8-bit immediate would normally go. ie. the last
15559 byte of the instruction. */
15560 obufp
= mnemonicendp
;
15561 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15563 oappend (mnemonic
);
15566 /* Since a variable sized modrm/sib chunk is between the start
15567 of the opcode (0x0f0f) and the opcode suffix, we need to do
15568 all the modrm processing first, and don't know until now that
15569 we have a bad opcode. This necessitates some cleaning up. */
15570 op_out
[0][0] = '\0';
15571 op_out
[1][0] = '\0';
15574 mnemonicendp
= obufp
;
15577 static struct op simd_cmp_op
[] =
15579 { STRING_COMMA_LEN ("eq") },
15580 { STRING_COMMA_LEN ("lt") },
15581 { STRING_COMMA_LEN ("le") },
15582 { STRING_COMMA_LEN ("unord") },
15583 { STRING_COMMA_LEN ("neq") },
15584 { STRING_COMMA_LEN ("nlt") },
15585 { STRING_COMMA_LEN ("nle") },
15586 { STRING_COMMA_LEN ("ord") }
15590 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15592 unsigned int cmp_type
;
15594 FETCH_DATA (the_info
, codep
+ 1);
15595 cmp_type
= *codep
++ & 0xff;
15596 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15599 char *p
= mnemonicendp
- 2;
15603 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15604 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15608 /* We have a reserved extension byte. Output it directly. */
15609 scratchbuf
[0] = '$';
15610 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15611 oappend_maybe_intel (scratchbuf
);
15612 scratchbuf
[0] = '\0';
15617 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15619 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
15622 strcpy (op_out
[0], names32
[0]);
15623 strcpy (op_out
[1], names32
[1]);
15624 if (bytemode
== eBX_reg
)
15625 strcpy (op_out
[2], names32
[3]);
15626 two_source_ops
= 1;
15628 /* Skip mod/rm byte. */
15634 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15635 int sizeflag ATTRIBUTE_UNUSED
)
15637 /* monitor %{e,r,}ax,%ecx,%edx" */
15640 const char **names
= (address_mode
== mode_64bit
15641 ? names64
: names32
);
15643 if (prefixes
& PREFIX_ADDR
)
15645 /* Remove "addr16/addr32". */
15646 all_prefixes
[last_addr_prefix
] = 0;
15647 names
= (address_mode
!= mode_32bit
15648 ? names32
: names16
);
15649 used_prefixes
|= PREFIX_ADDR
;
15651 else if (address_mode
== mode_16bit
)
15653 strcpy (op_out
[0], names
[0]);
15654 strcpy (op_out
[1], names32
[1]);
15655 strcpy (op_out
[2], names32
[2]);
15656 two_source_ops
= 1;
15658 /* Skip mod/rm byte. */
15666 /* Throw away prefixes and 1st. opcode byte. */
15667 codep
= insn_codep
+ 1;
15672 REP_Fixup (int bytemode
, int sizeflag
)
15674 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15676 if (prefixes
& PREFIX_REPZ
)
15677 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15684 OP_IMREG (bytemode
, sizeflag
);
15687 OP_ESreg (bytemode
, sizeflag
);
15690 OP_DSreg (bytemode
, sizeflag
);
15699 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15701 if ( isa64
!= amd64
)
15706 mnemonicendp
= obufp
;
15710 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15714 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15716 if (prefixes
& PREFIX_REPNZ
)
15717 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15720 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15724 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15725 int sizeflag ATTRIBUTE_UNUSED
)
15727 if (active_seg_prefix
== PREFIX_DS
15728 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15730 /* NOTRACK prefix is only valid on indirect branch instructions.
15731 NB: DATA prefix is unsupported for Intel64. */
15732 active_seg_prefix
= 0;
15733 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15737 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15738 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15742 HLE_Fixup1 (int bytemode
, int sizeflag
)
15745 && (prefixes
& PREFIX_LOCK
) != 0)
15747 if (prefixes
& PREFIX_REPZ
)
15748 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15749 if (prefixes
& PREFIX_REPNZ
)
15750 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15753 OP_E (bytemode
, sizeflag
);
15756 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15757 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15761 HLE_Fixup2 (int bytemode
, int sizeflag
)
15763 if (modrm
.mod
!= 3)
15765 if (prefixes
& PREFIX_REPZ
)
15766 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15767 if (prefixes
& PREFIX_REPNZ
)
15768 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15771 OP_E (bytemode
, sizeflag
);
15774 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15775 "xrelease" for memory operand. No check for LOCK prefix. */
15778 HLE_Fixup3 (int bytemode
, int sizeflag
)
15781 && last_repz_prefix
> last_repnz_prefix
15782 && (prefixes
& PREFIX_REPZ
) != 0)
15783 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15785 OP_E (bytemode
, sizeflag
);
15789 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15794 /* Change cmpxchg8b to cmpxchg16b. */
15795 char *p
= mnemonicendp
- 2;
15796 mnemonicendp
= stpcpy (p
, "16b");
15799 else if ((prefixes
& PREFIX_LOCK
) != 0)
15801 if (prefixes
& PREFIX_REPZ
)
15802 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15803 if (prefixes
& PREFIX_REPNZ
)
15804 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15807 OP_M (bytemode
, sizeflag
);
15811 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15813 const char **names
;
15817 switch (vex
.length
)
15831 oappend (names
[reg
]);
15835 CRC32_Fixup (int bytemode
, int sizeflag
)
15837 /* Add proper suffix to "crc32". */
15838 char *p
= mnemonicendp
;
15857 if (sizeflag
& DFLAG
)
15861 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15865 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15872 if (modrm
.mod
== 3)
15876 /* Skip mod/rm byte. */
15881 add
= (rex
& REX_B
) ? 8 : 0;
15882 if (bytemode
== b_mode
)
15886 oappend (names8rex
[modrm
.rm
+ add
]);
15888 oappend (names8
[modrm
.rm
+ add
]);
15894 oappend (names64
[modrm
.rm
+ add
]);
15895 else if ((prefixes
& PREFIX_DATA
))
15896 oappend (names16
[modrm
.rm
+ add
]);
15898 oappend (names32
[modrm
.rm
+ add
]);
15902 OP_E (bytemode
, sizeflag
);
15906 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15908 /* Add proper suffix to "fxsave" and "fxrstor". */
15912 char *p
= mnemonicendp
;
15918 OP_M (bytemode
, sizeflag
);
15922 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15924 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15927 char *p
= mnemonicendp
;
15932 else if (sizeflag
& SUFFIX_ALWAYS
)
15939 OP_EX (bytemode
, sizeflag
);
15942 /* Display the destination register operand for instructions with
15946 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15949 const char **names
;
15957 reg
= vex
.register_specifier
;
15958 vex
.register_specifier
= 0;
15959 if (address_mode
!= mode_64bit
)
15961 else if (vex
.evex
&& !vex
.v
)
15964 if (bytemode
== vex_scalar_mode
)
15966 oappend (names_xmm
[reg
]);
15970 switch (vex
.length
)
15977 case vex_vsib_q_w_dq_mode
:
15978 case vex_vsib_q_w_d_mode
:
15994 names
= names_mask
;
16008 case vex_vsib_q_w_dq_mode
:
16009 case vex_vsib_q_w_d_mode
:
16010 names
= vex
.w
? names_ymm
: names_xmm
;
16019 names
= names_mask
;
16022 /* See PR binutils/20893 for a reproducer. */
16034 oappend (names
[reg
]);
16037 /* Get the VEX immediate byte without moving codep. */
16039 static unsigned char
16040 get_vex_imm8 (int sizeflag
, int opnum
)
16042 int bytes_before_imm
= 0;
16044 if (modrm
.mod
!= 3)
16046 /* There are SIB/displacement bytes. */
16047 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16049 /* 32/64 bit address mode */
16050 int base
= modrm
.rm
;
16052 /* Check SIB byte. */
16055 FETCH_DATA (the_info
, codep
+ 1);
16057 /* When decoding the third source, don't increase
16058 bytes_before_imm as this has already been incremented
16059 by one in OP_E_memory while decoding the second
16062 bytes_before_imm
++;
16065 /* Don't increase bytes_before_imm when decoding the third source,
16066 it has already been incremented by OP_E_memory while decoding
16067 the second source operand. */
16073 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16074 SIB == 5, there is a 4 byte displacement. */
16076 /* No displacement. */
16078 /* Fall through. */
16080 /* 4 byte displacement. */
16081 bytes_before_imm
+= 4;
16084 /* 1 byte displacement. */
16085 bytes_before_imm
++;
16092 /* 16 bit address mode */
16093 /* Don't increase bytes_before_imm when decoding the third source,
16094 it has already been incremented by OP_E_memory while decoding
16095 the second source operand. */
16101 /* When modrm.rm == 6, there is a 2 byte displacement. */
16103 /* No displacement. */
16105 /* Fall through. */
16107 /* 2 byte displacement. */
16108 bytes_before_imm
+= 2;
16111 /* 1 byte displacement: when decoding the third source,
16112 don't increase bytes_before_imm as this has already
16113 been incremented by one in OP_E_memory while decoding
16114 the second source operand. */
16116 bytes_before_imm
++;
16124 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16125 return codep
[bytes_before_imm
];
16129 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16131 const char **names
;
16133 if (reg
== -1 && modrm
.mod
!= 3)
16135 OP_E_memory (bytemode
, sizeflag
);
16147 if (address_mode
!= mode_64bit
)
16151 switch (vex
.length
)
16162 oappend (names
[reg
]);
16166 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16169 static unsigned char vex_imm8
;
16171 if (vex_w_done
== 0)
16175 /* Skip mod/rm byte. */
16179 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16182 reg
= vex_imm8
>> 4;
16184 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16186 else if (vex_w_done
== 1)
16191 reg
= vex_imm8
>> 4;
16193 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16197 /* Output the imm8 directly. */
16198 scratchbuf
[0] = '$';
16199 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16200 oappend_maybe_intel (scratchbuf
);
16201 scratchbuf
[0] = '\0';
16207 OP_Vex_2src (int bytemode
, int sizeflag
)
16209 if (modrm
.mod
== 3)
16211 int reg
= modrm
.rm
;
16215 oappend (names_xmm
[reg
]);
16220 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16222 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16223 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16225 OP_E (bytemode
, sizeflag
);
16230 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16232 if (modrm
.mod
== 3)
16234 /* Skip mod/rm byte. */
16241 unsigned int reg
= vex
.register_specifier
;
16242 vex
.register_specifier
= 0;
16244 if (address_mode
!= mode_64bit
)
16246 oappend (names_xmm
[reg
]);
16249 OP_Vex_2src (bytemode
, sizeflag
);
16253 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16256 OP_Vex_2src (bytemode
, sizeflag
);
16259 unsigned int reg
= vex
.register_specifier
;
16260 vex
.register_specifier
= 0;
16262 if (address_mode
!= mode_64bit
)
16264 oappend (names_xmm
[reg
]);
16269 OP_EX_VexW (int bytemode
, int sizeflag
)
16275 /* Skip mod/rm byte. */
16280 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16285 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16288 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16296 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16299 const char **names
;
16301 FETCH_DATA (the_info
, codep
+ 1);
16304 if (bytemode
!= x_mode
)
16308 if (address_mode
!= mode_64bit
)
16311 switch (vex
.length
)
16322 oappend (names
[reg
]);
16326 OP_XMM_VexW (int bytemode
, int sizeflag
)
16328 /* Turn off the REX.W bit since it is used for swapping operands
16331 OP_XMM (bytemode
, sizeflag
);
16335 OP_EX_Vex (int bytemode
, int sizeflag
)
16337 if (modrm
.mod
!= 3)
16339 OP_EX (bytemode
, sizeflag
);
16343 OP_XMM_Vex (int bytemode
, int sizeflag
)
16345 if (modrm
.mod
!= 3)
16347 OP_XMM (bytemode
, sizeflag
);
16350 static struct op vex_cmp_op
[] =
16352 { STRING_COMMA_LEN ("eq") },
16353 { STRING_COMMA_LEN ("lt") },
16354 { STRING_COMMA_LEN ("le") },
16355 { STRING_COMMA_LEN ("unord") },
16356 { STRING_COMMA_LEN ("neq") },
16357 { STRING_COMMA_LEN ("nlt") },
16358 { STRING_COMMA_LEN ("nle") },
16359 { STRING_COMMA_LEN ("ord") },
16360 { STRING_COMMA_LEN ("eq_uq") },
16361 { STRING_COMMA_LEN ("nge") },
16362 { STRING_COMMA_LEN ("ngt") },
16363 { STRING_COMMA_LEN ("false") },
16364 { STRING_COMMA_LEN ("neq_oq") },
16365 { STRING_COMMA_LEN ("ge") },
16366 { STRING_COMMA_LEN ("gt") },
16367 { STRING_COMMA_LEN ("true") },
16368 { STRING_COMMA_LEN ("eq_os") },
16369 { STRING_COMMA_LEN ("lt_oq") },
16370 { STRING_COMMA_LEN ("le_oq") },
16371 { STRING_COMMA_LEN ("unord_s") },
16372 { STRING_COMMA_LEN ("neq_us") },
16373 { STRING_COMMA_LEN ("nlt_uq") },
16374 { STRING_COMMA_LEN ("nle_uq") },
16375 { STRING_COMMA_LEN ("ord_s") },
16376 { STRING_COMMA_LEN ("eq_us") },
16377 { STRING_COMMA_LEN ("nge_uq") },
16378 { STRING_COMMA_LEN ("ngt_uq") },
16379 { STRING_COMMA_LEN ("false_os") },
16380 { STRING_COMMA_LEN ("neq_os") },
16381 { STRING_COMMA_LEN ("ge_oq") },
16382 { STRING_COMMA_LEN ("gt_oq") },
16383 { STRING_COMMA_LEN ("true_us") },
16387 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16389 unsigned int cmp_type
;
16391 FETCH_DATA (the_info
, codep
+ 1);
16392 cmp_type
= *codep
++ & 0xff;
16393 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16396 char *p
= mnemonicendp
- 2;
16400 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16401 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16405 /* We have a reserved extension byte. Output it directly. */
16406 scratchbuf
[0] = '$';
16407 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16408 oappend_maybe_intel (scratchbuf
);
16409 scratchbuf
[0] = '\0';
16414 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16415 int sizeflag ATTRIBUTE_UNUSED
)
16417 unsigned int cmp_type
;
16422 FETCH_DATA (the_info
, codep
+ 1);
16423 cmp_type
= *codep
++ & 0xff;
16424 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16425 If it's the case, print suffix, otherwise - print the immediate. */
16426 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16431 char *p
= mnemonicendp
- 2;
16433 /* vpcmp* can have both one- and two-lettered suffix. */
16447 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16448 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16452 /* We have a reserved extension byte. Output it directly. */
16453 scratchbuf
[0] = '$';
16454 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16455 oappend_maybe_intel (scratchbuf
);
16456 scratchbuf
[0] = '\0';
16460 static const struct op xop_cmp_op
[] =
16462 { STRING_COMMA_LEN ("lt") },
16463 { STRING_COMMA_LEN ("le") },
16464 { STRING_COMMA_LEN ("gt") },
16465 { STRING_COMMA_LEN ("ge") },
16466 { STRING_COMMA_LEN ("eq") },
16467 { STRING_COMMA_LEN ("neq") },
16468 { STRING_COMMA_LEN ("false") },
16469 { STRING_COMMA_LEN ("true") }
16473 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16474 int sizeflag ATTRIBUTE_UNUSED
)
16476 unsigned int cmp_type
;
16478 FETCH_DATA (the_info
, codep
+ 1);
16479 cmp_type
= *codep
++ & 0xff;
16480 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16483 char *p
= mnemonicendp
- 2;
16485 /* vpcom* can have both one- and two-lettered suffix. */
16499 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16500 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16504 /* We have a reserved extension byte. Output it directly. */
16505 scratchbuf
[0] = '$';
16506 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16507 oappend_maybe_intel (scratchbuf
);
16508 scratchbuf
[0] = '\0';
16512 static const struct op pclmul_op
[] =
16514 { STRING_COMMA_LEN ("lql") },
16515 { STRING_COMMA_LEN ("hql") },
16516 { STRING_COMMA_LEN ("lqh") },
16517 { STRING_COMMA_LEN ("hqh") }
16521 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16522 int sizeflag ATTRIBUTE_UNUSED
)
16524 unsigned int pclmul_type
;
16526 FETCH_DATA (the_info
, codep
+ 1);
16527 pclmul_type
= *codep
++ & 0xff;
16528 switch (pclmul_type
)
16539 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16542 char *p
= mnemonicendp
- 3;
16547 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16548 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16552 /* We have a reserved extension byte. Output it directly. */
16553 scratchbuf
[0] = '$';
16554 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16555 oappend_maybe_intel (scratchbuf
);
16556 scratchbuf
[0] = '\0';
16561 MOVBE_Fixup (int bytemode
, int sizeflag
)
16563 /* Add proper suffix to "movbe". */
16564 char *p
= mnemonicendp
;
16573 if (sizeflag
& SUFFIX_ALWAYS
)
16579 if (sizeflag
& DFLAG
)
16583 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16588 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16595 OP_M (bytemode
, sizeflag
);
16599 MOVSXD_Fixup (int bytemode
, int sizeflag
)
16601 /* Add proper suffix to "movsxd". */
16602 char *p
= mnemonicendp
;
16627 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16634 OP_E (bytemode
, sizeflag
);
16638 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16641 const char **names
;
16643 /* Skip mod/rm byte. */
16657 oappend (names
[reg
]);
16661 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16663 const char **names
;
16664 unsigned int reg
= vex
.register_specifier
;
16665 vex
.register_specifier
= 0;
16672 if (address_mode
!= mode_64bit
)
16674 oappend (names
[reg
]);
16678 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16681 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16685 if ((rex
& REX_R
) != 0 || !vex
.r
)
16691 oappend (names_mask
[modrm
.reg
]);
16695 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16698 || (bytemode
!= evex_rounding_mode
16699 && bytemode
!= evex_rounding_64_mode
16700 && bytemode
!= evex_sae_mode
))
16702 if (modrm
.mod
== 3 && vex
.b
)
16705 case evex_rounding_64_mode
:
16706 if (address_mode
!= mode_64bit
)
16711 /* Fall through. */
16712 case evex_rounding_mode
:
16713 oappend (names_rounding
[vex
.ll
]);
16715 case evex_sae_mode
: