1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2018 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void OP_Mwaitx (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
128 static void OP_Mask (int, int);
131 /* Points to first byte not fetched. */
132 bfd_byte
*max_fetched
;
133 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
136 OPCODES_SIGJMP_BUF bailout
;
146 enum address_mode address_mode
;
148 /* Flags for the prefixes for the current instruction. See below. */
151 /* REX prefix the current instruction. See below. */
153 /* Bits of REX we've already used. */
155 /* REX bits in original REX prefix ignored. */
156 static int rex_ignored
;
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes
;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
201 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
202 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
204 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
205 status
= (*info
->read_memory_func
) (start
,
207 addr
- priv
->max_fetched
,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv
->max_fetched
== priv
->the_buffer
)
218 (*info
->memory_error_func
) (status
, start
, info
);
219 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
222 priv
->max_fetched
= addr
;
226 /* Possible values for prefix requirement. */
227 #define PREFIX_IGNORED_SHIFT 16
228 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234 /* Opcode prefixes. */
235 #define PREFIX_OPCODE (PREFIX_REPZ \
239 /* Prefixes ignored. */
240 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
241 | PREFIX_IGNORED_REPNZ \
242 | PREFIX_IGNORED_DATA)
244 #define XX { NULL, 0 }
245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
247 #define Eb { OP_E, b_mode }
248 #define Ebnd { OP_E, bnd_mode }
249 #define EbS { OP_E, b_swap_mode }
250 #define EbndS { OP_E, bnd_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Eva { OP_E, va_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Edqa { OP_E, dqa_mode }
263 #define Eq { OP_E, q_mode }
264 #define indirEv { OP_indirE, indir_v_mode }
265 #define indirEp { OP_indirE, f_mode }
266 #define stackEv { OP_E, stack_v_mode }
267 #define Em { OP_E, m_mode }
268 #define Ew { OP_E, w_mode }
269 #define M { OP_M, 0 } /* lea, lgdt, etc. */
270 #define Ma { OP_M, a_mode }
271 #define Mb { OP_M, b_mode }
272 #define Md { OP_M, d_mode }
273 #define Mo { OP_M, o_mode }
274 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
275 #define Mq { OP_M, q_mode }
276 #define Mv_bnd { OP_M, v_bndmk_mode }
277 #define Mx { OP_M, x_mode }
278 #define Mxmm { OP_M, xmm_mode }
279 #define Gb { OP_G, b_mode }
280 #define Gbnd { OP_G, bnd_mode }
281 #define Gv { OP_G, v_mode }
282 #define Gd { OP_G, d_mode }
283 #define Gdq { OP_G, dq_mode }
284 #define Gm { OP_G, m_mode }
285 #define Gva { OP_G, va_mode }
286 #define Gw { OP_G, w_mode }
287 #define Rd { OP_R, d_mode }
288 #define Rdq { OP_R, dq_mode }
289 #define Rm { OP_R, m_mode }
290 #define Ib { OP_I, b_mode }
291 #define sIb { OP_sI, b_mode } /* sign extened byte */
292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
293 #define Iv { OP_I, v_mode }
294 #define sIv { OP_sI, v_mode }
295 #define Iq { OP_I, q_mode }
296 #define Iv64 { OP_I64, v_mode }
297 #define Iw { OP_I, w_mode }
298 #define I1 { OP_I, const_1_mode }
299 #define Jb { OP_J, b_mode }
300 #define Jv { OP_J, v_mode }
301 #define Cm { OP_C, m_mode }
302 #define Dm { OP_D, m_mode }
303 #define Td { OP_T, d_mode }
304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
306 #define RMeAX { OP_REG, eAX_reg }
307 #define RMeBX { OP_REG, eBX_reg }
308 #define RMeCX { OP_REG, eCX_reg }
309 #define RMeDX { OP_REG, eDX_reg }
310 #define RMeSP { OP_REG, eSP_reg }
311 #define RMeBP { OP_REG, eBP_reg }
312 #define RMeSI { OP_REG, eSI_reg }
313 #define RMeDI { OP_REG, eDI_reg }
314 #define RMrAX { OP_REG, rAX_reg }
315 #define RMrBX { OP_REG, rBX_reg }
316 #define RMrCX { OP_REG, rCX_reg }
317 #define RMrDX { OP_REG, rDX_reg }
318 #define RMrSP { OP_REG, rSP_reg }
319 #define RMrBP { OP_REG, rBP_reg }
320 #define RMrSI { OP_REG, rSI_reg }
321 #define RMrDI { OP_REG, rDI_reg }
322 #define RMAL { OP_REG, al_reg }
323 #define RMCL { OP_REG, cl_reg }
324 #define RMDL { OP_REG, dl_reg }
325 #define RMBL { OP_REG, bl_reg }
326 #define RMAH { OP_REG, ah_reg }
327 #define RMCH { OP_REG, ch_reg }
328 #define RMDH { OP_REG, dh_reg }
329 #define RMBH { OP_REG, bh_reg }
330 #define RMAX { OP_REG, ax_reg }
331 #define RMDX { OP_REG, dx_reg }
333 #define eAX { OP_IMREG, eAX_reg }
334 #define eBX { OP_IMREG, eBX_reg }
335 #define eCX { OP_IMREG, eCX_reg }
336 #define eDX { OP_IMREG, eDX_reg }
337 #define eSP { OP_IMREG, eSP_reg }
338 #define eBP { OP_IMREG, eBP_reg }
339 #define eSI { OP_IMREG, eSI_reg }
340 #define eDI { OP_IMREG, eDI_reg }
341 #define AL { OP_IMREG, al_reg }
342 #define CL { OP_IMREG, cl_reg }
343 #define DL { OP_IMREG, dl_reg }
344 #define BL { OP_IMREG, bl_reg }
345 #define AH { OP_IMREG, ah_reg }
346 #define CH { OP_IMREG, ch_reg }
347 #define DH { OP_IMREG, dh_reg }
348 #define BH { OP_IMREG, bh_reg }
349 #define AX { OP_IMREG, ax_reg }
350 #define DX { OP_IMREG, dx_reg }
351 #define zAX { OP_IMREG, z_mode_ax_reg }
352 #define indirDX { OP_IMREG, indir_dx_reg }
354 #define Sw { OP_SEG, w_mode }
355 #define Sv { OP_SEG, v_mode }
356 #define Ap { OP_DIR, 0 }
357 #define Ob { OP_OFF64, b_mode }
358 #define Ov { OP_OFF64, v_mode }
359 #define Xb { OP_DSreg, eSI_reg }
360 #define Xv { OP_DSreg, eSI_reg }
361 #define Xz { OP_DSreg, eSI_reg }
362 #define Yb { OP_ESreg, eDI_reg }
363 #define Yv { OP_ESreg, eDI_reg }
364 #define DSBX { OP_DSreg, eBX_reg }
366 #define es { OP_REG, es_reg }
367 #define ss { OP_REG, ss_reg }
368 #define cs { OP_REG, cs_reg }
369 #define ds { OP_REG, ds_reg }
370 #define fs { OP_REG, fs_reg }
371 #define gs { OP_REG, gs_reg }
373 #define MX { OP_MMX, 0 }
374 #define XM { OP_XMM, 0 }
375 #define XMScalar { OP_XMM, scalar_mode }
376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
377 #define XMM { OP_XMM, xmm_mode }
378 #define XMxmmq { OP_XMM, xmmq_mode }
379 #define EM { OP_EM, v_mode }
380 #define EMS { OP_EM, v_swap_mode }
381 #define EMd { OP_EM, d_mode }
382 #define EMx { OP_EM, x_mode }
383 #define EXbScalar { OP_EX, b_scalar_mode }
384 #define EXw { OP_EX, w_mode }
385 #define EXwScalar { OP_EX, w_scalar_mode }
386 #define EXd { OP_EX, d_mode }
387 #define EXdScalar { OP_EX, d_scalar_mode }
388 #define EXdS { OP_EX, d_swap_mode }
389 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
390 #define EXq { OP_EX, q_mode }
391 #define EXqScalar { OP_EX, q_scalar_mode }
392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
393 #define EXqS { OP_EX, q_swap_mode }
394 #define EXx { OP_EX, x_mode }
395 #define EXxS { OP_EX, x_swap_mode }
396 #define EXxmm { OP_EX, xmm_mode }
397 #define EXymm { OP_EX, ymm_mode }
398 #define EXxmmq { OP_EX, xmmq_mode }
399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
402 #define EXxmm_md { OP_EX, xmm_md_mode }
403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
405 #define EXxmmdw { OP_EX, xmmdw_mode }
406 #define EXxmmqd { OP_EX, xmmqd_mode }
407 #define EXymmq { OP_EX, ymmq_mode }
408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
412 #define MS { OP_MS, v_mode }
413 #define XS { OP_XS, v_mode }
414 #define EMCq { OP_EMC, q_mode }
415 #define MXC { OP_MXC, 0 }
416 #define OPSUF { OP_3DNowSuffix, 0 }
417 #define CMP { CMP_Fixup, 0 }
418 #define XMM0 { XMM_Fixup, 0 }
419 #define FXSAVE { FXSAVE_Fixup, 0 }
420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
423 #define Vex { OP_VEX, vex_mode }
424 #define VexScalar { OP_VEX, vex_scalar_mode }
425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
426 #define Vex128 { OP_VEX, vex128_mode }
427 #define Vex256 { OP_VEX, vex256_mode }
428 #define VexGdq { OP_VEX, dq_mode }
429 #define EXdVex { OP_EX_Vex, d_mode }
430 #define EXdVexS { OP_EX_Vex, d_swap_mode }
431 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
432 #define EXqVex { OP_EX_Vex, q_mode }
433 #define EXqVexS { OP_EX_Vex, q_swap_mode }
434 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
435 #define EXVexW { OP_EX_VexW, x_mode }
436 #define EXdVexW { OP_EX_VexW, d_mode }
437 #define EXqVexW { OP_EX_VexW, q_mode }
438 #define EXVexImmW { OP_EX_VexImmW, x_mode }
439 #define XMVex { OP_XMM_Vex, 0 }
440 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
441 #define XMVexW { OP_XMM_VexW, 0 }
442 #define XMVexI4 { OP_REG_VexI4, x_mode }
443 #define PCLMUL { PCLMUL_Fixup, 0 }
444 #define VCMP { VCMP_Fixup, 0 }
445 #define VPCMP { VPCMP_Fixup, 0 }
446 #define VPCOM { VPCOM_Fixup, 0 }
448 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
449 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
450 #define EXxEVexS { OP_Rounding, evex_sae_mode }
452 #define XMask { OP_Mask, mask_mode }
453 #define MaskG { OP_G, mask_mode }
454 #define MaskE { OP_E, mask_mode }
455 #define MaskBDE { OP_E, mask_bd_mode }
456 #define MaskR { OP_R, mask_mode }
457 #define MaskVex { OP_VEX, mask_mode }
459 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
460 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
461 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
462 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
464 /* Used handle "rep" prefix for string instructions. */
465 #define Xbr { REP_Fixup, eSI_reg }
466 #define Xvr { REP_Fixup, eSI_reg }
467 #define Ybr { REP_Fixup, eDI_reg }
468 #define Yvr { REP_Fixup, eDI_reg }
469 #define Yzr { REP_Fixup, eDI_reg }
470 #define indirDXr { REP_Fixup, indir_dx_reg }
471 #define ALr { REP_Fixup, al_reg }
472 #define eAXr { REP_Fixup, eAX_reg }
474 /* Used handle HLE prefix for lockable instructions. */
475 #define Ebh1 { HLE_Fixup1, b_mode }
476 #define Evh1 { HLE_Fixup1, v_mode }
477 #define Ebh2 { HLE_Fixup2, b_mode }
478 #define Evh2 { HLE_Fixup2, v_mode }
479 #define Ebh3 { HLE_Fixup3, b_mode }
480 #define Evh3 { HLE_Fixup3, v_mode }
482 #define BND { BND_Fixup, 0 }
483 #define NOTRACK { NOTRACK_Fixup, 0 }
485 #define cond_jump_flag { NULL, cond_jump_mode }
486 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
488 /* bits in sizeflag */
489 #define SUFFIX_ALWAYS 4
497 /* byte operand with operand swapped */
499 /* byte operand, sign extend like 'T' suffix */
501 /* operand size depends on prefixes */
503 /* operand size depends on prefixes with operand swapped */
505 /* operand size depends on address prefix */
509 /* double word operand */
511 /* double word operand with operand swapped */
513 /* quad word operand */
515 /* quad word operand with operand swapped */
517 /* ten-byte operand */
519 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
520 broadcast enabled. */
522 /* Similar to x_mode, but with different EVEX mem shifts. */
524 /* Similar to x_mode, but with disabled broadcast. */
526 /* Similar to x_mode, but with operands swapped and disabled broadcast
529 /* 16-byte XMM operand */
531 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
532 memory operand (depending on vector length). Broadcast isn't
535 /* Same as xmmq_mode, but broadcast is allowed. */
536 evex_half_bcst_xmmq_mode
,
537 /* XMM register or byte memory operand */
539 /* XMM register or word memory operand */
541 /* XMM register or double word memory operand */
543 /* XMM register or quad word memory operand */
545 /* XMM register or double/quad word memory operand, depending on
548 /* 16-byte XMM, word, double word or quad word operand. */
550 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
552 /* 32-byte YMM operand */
554 /* quad word, ymmword or zmmword memory operand. */
556 /* 32-byte YMM or 16-byte word operand */
558 /* d_mode in 32bit, q_mode in 64bit mode. */
560 /* pair of v_mode operands */
565 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
567 /* operand size depends on REX prefixes. */
569 /* registers like dq_mode, memory like w_mode. */
573 /* bounds operand with operand swapped */
575 /* 4- or 6-byte pointer operand */
578 /* v_mode for indirect branch opcodes. */
580 /* v_mode for stack-related opcodes. */
582 /* non-quad operand size depends on prefixes */
584 /* 16-byte operand */
586 /* registers like dq_mode, memory like b_mode. */
588 /* registers like d_mode, memory like b_mode. */
590 /* registers like d_mode, memory like w_mode. */
592 /* registers like dq_mode, memory like d_mode. */
594 /* operand size depends on the W bit as well as address mode. */
596 /* normal vex mode */
598 /* 128bit vex mode */
600 /* 256bit vex mode */
602 /* operand size depends on the VEX.W bit. */
605 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
606 vex_vsib_d_w_dq_mode
,
607 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
609 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
610 vex_vsib_q_w_dq_mode
,
611 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
614 /* scalar, ignore vector length. */
616 /* like b_mode, ignore vector length. */
618 /* like w_mode, ignore vector length. */
620 /* like d_mode, ignore vector length. */
622 /* like d_swap_mode, ignore vector length. */
624 /* like q_mode, ignore vector length. */
626 /* like q_swap_mode, ignore vector length. */
628 /* like vex_mode, ignore vector length. */
630 /* like vex_w_dq_mode, ignore vector length. */
631 vex_scalar_w_dq_mode
,
633 /* Static rounding. */
635 /* Static rounding, 64-bit mode only. */
636 evex_rounding_64_mode
,
637 /* Supress all exceptions. */
640 /* Mask register operand. */
642 /* Mask register operand. */
710 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
712 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
713 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
714 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
715 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
716 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
717 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
718 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
719 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
720 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
721 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
722 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
723 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
724 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
725 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
726 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
727 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
853 MOD_VEX_0F12_PREFIX_0
,
855 MOD_VEX_0F16_PREFIX_0
,
858 MOD_VEX_W_0_0F41_P_0_LEN_1
,
859 MOD_VEX_W_1_0F41_P_0_LEN_1
,
860 MOD_VEX_W_0_0F41_P_2_LEN_1
,
861 MOD_VEX_W_1_0F41_P_2_LEN_1
,
862 MOD_VEX_W_0_0F42_P_0_LEN_1
,
863 MOD_VEX_W_1_0F42_P_0_LEN_1
,
864 MOD_VEX_W_0_0F42_P_2_LEN_1
,
865 MOD_VEX_W_1_0F42_P_2_LEN_1
,
866 MOD_VEX_W_0_0F44_P_0_LEN_1
,
867 MOD_VEX_W_1_0F44_P_0_LEN_1
,
868 MOD_VEX_W_0_0F44_P_2_LEN_1
,
869 MOD_VEX_W_1_0F44_P_2_LEN_1
,
870 MOD_VEX_W_0_0F45_P_0_LEN_1
,
871 MOD_VEX_W_1_0F45_P_0_LEN_1
,
872 MOD_VEX_W_0_0F45_P_2_LEN_1
,
873 MOD_VEX_W_1_0F45_P_2_LEN_1
,
874 MOD_VEX_W_0_0F46_P_0_LEN_1
,
875 MOD_VEX_W_1_0F46_P_0_LEN_1
,
876 MOD_VEX_W_0_0F46_P_2_LEN_1
,
877 MOD_VEX_W_1_0F46_P_2_LEN_1
,
878 MOD_VEX_W_0_0F47_P_0_LEN_1
,
879 MOD_VEX_W_1_0F47_P_0_LEN_1
,
880 MOD_VEX_W_0_0F47_P_2_LEN_1
,
881 MOD_VEX_W_1_0F47_P_2_LEN_1
,
882 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
883 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
884 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
885 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
886 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
887 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
888 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
900 MOD_VEX_W_0_0F91_P_0_LEN_0
,
901 MOD_VEX_W_1_0F91_P_0_LEN_0
,
902 MOD_VEX_W_0_0F91_P_2_LEN_0
,
903 MOD_VEX_W_1_0F91_P_2_LEN_0
,
904 MOD_VEX_W_0_0F92_P_0_LEN_0
,
905 MOD_VEX_W_0_0F92_P_2_LEN_0
,
906 MOD_VEX_W_0_0F92_P_3_LEN_0
,
907 MOD_VEX_W_1_0F92_P_3_LEN_0
,
908 MOD_VEX_W_0_0F93_P_0_LEN_0
,
909 MOD_VEX_W_0_0F93_P_2_LEN_0
,
910 MOD_VEX_W_0_0F93_P_3_LEN_0
,
911 MOD_VEX_W_1_0F93_P_3_LEN_0
,
912 MOD_VEX_W_0_0F98_P_0_LEN_0
,
913 MOD_VEX_W_1_0F98_P_0_LEN_0
,
914 MOD_VEX_W_0_0F98_P_2_LEN_0
,
915 MOD_VEX_W_1_0F98_P_2_LEN_0
,
916 MOD_VEX_W_0_0F99_P_0_LEN_0
,
917 MOD_VEX_W_1_0F99_P_0_LEN_0
,
918 MOD_VEX_W_0_0F99_P_2_LEN_0
,
919 MOD_VEX_W_1_0F99_P_2_LEN_0
,
922 MOD_VEX_0FD7_PREFIX_2
,
923 MOD_VEX_0FE7_PREFIX_2
,
924 MOD_VEX_0FF0_PREFIX_3
,
925 MOD_VEX_0F381A_PREFIX_2
,
926 MOD_VEX_0F382A_PREFIX_2
,
927 MOD_VEX_0F382C_PREFIX_2
,
928 MOD_VEX_0F382D_PREFIX_2
,
929 MOD_VEX_0F382E_PREFIX_2
,
930 MOD_VEX_0F382F_PREFIX_2
,
931 MOD_VEX_0F385A_PREFIX_2
,
932 MOD_VEX_0F388C_PREFIX_2
,
933 MOD_VEX_0F388E_PREFIX_2
,
934 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
935 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
936 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
937 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
938 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
939 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
940 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
941 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
943 MOD_EVEX_0F10_PREFIX_1
,
944 MOD_EVEX_0F10_PREFIX_3
,
945 MOD_EVEX_0F11_PREFIX_1
,
946 MOD_EVEX_0F11_PREFIX_3
,
947 MOD_EVEX_0F12_PREFIX_0
,
948 MOD_EVEX_0F16_PREFIX_0
,
949 MOD_EVEX_0F38C6_REG_1
,
950 MOD_EVEX_0F38C6_REG_2
,
951 MOD_EVEX_0F38C6_REG_5
,
952 MOD_EVEX_0F38C6_REG_6
,
953 MOD_EVEX_0F38C7_REG_1
,
954 MOD_EVEX_0F38C7_REG_2
,
955 MOD_EVEX_0F38C7_REG_5
,
956 MOD_EVEX_0F38C7_REG_6
977 PREFIX_MOD_0_0F01_REG_5
,
978 PREFIX_MOD_3_0F01_REG_5_RM_0
,
979 PREFIX_MOD_3_0F01_REG_5_RM_2
,
1025 PREFIX_MOD_0_0FAE_REG_4
,
1026 PREFIX_MOD_3_0FAE_REG_4
,
1027 PREFIX_MOD_0_0FAE_REG_5
,
1028 PREFIX_MOD_3_0FAE_REG_5
,
1029 PREFIX_MOD_0_0FAE_REG_6
,
1030 PREFIX_MOD_1_0FAE_REG_6
,
1037 PREFIX_MOD_0_0FC7_REG_6
,
1038 PREFIX_MOD_3_0FC7_REG_6
,
1039 PREFIX_MOD_3_0FC7_REG_7
,
1169 PREFIX_VEX_0F71_REG_2
,
1170 PREFIX_VEX_0F71_REG_4
,
1171 PREFIX_VEX_0F71_REG_6
,
1172 PREFIX_VEX_0F72_REG_2
,
1173 PREFIX_VEX_0F72_REG_4
,
1174 PREFIX_VEX_0F72_REG_6
,
1175 PREFIX_VEX_0F73_REG_2
,
1176 PREFIX_VEX_0F73_REG_3
,
1177 PREFIX_VEX_0F73_REG_6
,
1178 PREFIX_VEX_0F73_REG_7
,
1351 PREFIX_VEX_0F38F3_REG_1
,
1352 PREFIX_VEX_0F38F3_REG_2
,
1353 PREFIX_VEX_0F38F3_REG_3
,
1472 PREFIX_EVEX_0F71_REG_2
,
1473 PREFIX_EVEX_0F71_REG_4
,
1474 PREFIX_EVEX_0F71_REG_6
,
1475 PREFIX_EVEX_0F72_REG_0
,
1476 PREFIX_EVEX_0F72_REG_1
,
1477 PREFIX_EVEX_0F72_REG_2
,
1478 PREFIX_EVEX_0F72_REG_4
,
1479 PREFIX_EVEX_0F72_REG_6
,
1480 PREFIX_EVEX_0F73_REG_2
,
1481 PREFIX_EVEX_0F73_REG_3
,
1482 PREFIX_EVEX_0F73_REG_6
,
1483 PREFIX_EVEX_0F73_REG_7
,
1679 PREFIX_EVEX_0F38C6_REG_1
,
1680 PREFIX_EVEX_0F38C6_REG_2
,
1681 PREFIX_EVEX_0F38C6_REG_5
,
1682 PREFIX_EVEX_0F38C6_REG_6
,
1683 PREFIX_EVEX_0F38C7_REG_1
,
1684 PREFIX_EVEX_0F38C7_REG_2
,
1685 PREFIX_EVEX_0F38C7_REG_5
,
1686 PREFIX_EVEX_0F38C7_REG_6
,
1788 THREE_BYTE_0F38
= 0,
1815 VEX_LEN_0F12_P_0_M_0
= 0,
1816 VEX_LEN_0F12_P_0_M_1
,
1819 VEX_LEN_0F16_P_0_M_0
,
1820 VEX_LEN_0F16_P_0_M_1
,
1863 VEX_LEN_0FAE_R_2_M_0
,
1864 VEX_LEN_0FAE_R_3_M_0
,
1871 VEX_LEN_0F381A_P_2_M_0
,
1874 VEX_LEN_0F385A_P_2_M_0
,
1877 VEX_LEN_0F38F3_R_1_P_0
,
1878 VEX_LEN_0F38F3_R_2_P_0
,
1879 VEX_LEN_0F38F3_R_3_P_0
,
1922 VEX_LEN_0FXOP_08_CC
,
1923 VEX_LEN_0FXOP_08_CD
,
1924 VEX_LEN_0FXOP_08_CE
,
1925 VEX_LEN_0FXOP_08_CF
,
1926 VEX_LEN_0FXOP_08_EC
,
1927 VEX_LEN_0FXOP_08_ED
,
1928 VEX_LEN_0FXOP_08_EE
,
1929 VEX_LEN_0FXOP_08_EF
,
1930 VEX_LEN_0FXOP_09_80
,
1936 EVEX_LEN_0F6E_P_2
= 0,
1944 VEX_W_0F41_P_0_LEN_1
= 0,
1945 VEX_W_0F41_P_2_LEN_1
,
1946 VEX_W_0F42_P_0_LEN_1
,
1947 VEX_W_0F42_P_2_LEN_1
,
1948 VEX_W_0F44_P_0_LEN_0
,
1949 VEX_W_0F44_P_2_LEN_0
,
1950 VEX_W_0F45_P_0_LEN_1
,
1951 VEX_W_0F45_P_2_LEN_1
,
1952 VEX_W_0F46_P_0_LEN_1
,
1953 VEX_W_0F46_P_2_LEN_1
,
1954 VEX_W_0F47_P_0_LEN_1
,
1955 VEX_W_0F47_P_2_LEN_1
,
1956 VEX_W_0F4A_P_0_LEN_1
,
1957 VEX_W_0F4A_P_2_LEN_1
,
1958 VEX_W_0F4B_P_0_LEN_1
,
1959 VEX_W_0F4B_P_2_LEN_1
,
1960 VEX_W_0F90_P_0_LEN_0
,
1961 VEX_W_0F90_P_2_LEN_0
,
1962 VEX_W_0F91_P_0_LEN_0
,
1963 VEX_W_0F91_P_2_LEN_0
,
1964 VEX_W_0F92_P_0_LEN_0
,
1965 VEX_W_0F92_P_2_LEN_0
,
1966 VEX_W_0F92_P_3_LEN_0
,
1967 VEX_W_0F93_P_0_LEN_0
,
1968 VEX_W_0F93_P_2_LEN_0
,
1969 VEX_W_0F93_P_3_LEN_0
,
1970 VEX_W_0F98_P_0_LEN_0
,
1971 VEX_W_0F98_P_2_LEN_0
,
1972 VEX_W_0F99_P_0_LEN_0
,
1973 VEX_W_0F99_P_2_LEN_0
,
1981 VEX_W_0F381A_P_2_M_0
,
1982 VEX_W_0F382C_P_2_M_0
,
1983 VEX_W_0F382D_P_2_M_0
,
1984 VEX_W_0F382E_P_2_M_0
,
1985 VEX_W_0F382F_P_2_M_0
,
1990 VEX_W_0F385A_P_2_M_0
,
2002 VEX_W_0F3A30_P_2_LEN_0
,
2003 VEX_W_0F3A31_P_2_LEN_0
,
2004 VEX_W_0F3A32_P_2_LEN_0
,
2005 VEX_W_0F3A33_P_2_LEN_0
,
2018 EVEX_W_0F10_P_1_M_0
,
2019 EVEX_W_0F10_P_1_M_1
,
2021 EVEX_W_0F10_P_3_M_0
,
2022 EVEX_W_0F10_P_3_M_1
,
2024 EVEX_W_0F11_P_1_M_0
,
2025 EVEX_W_0F11_P_1_M_1
,
2027 EVEX_W_0F11_P_3_M_0
,
2028 EVEX_W_0F11_P_3_M_1
,
2029 EVEX_W_0F12_P_0_M_0
,
2030 EVEX_W_0F12_P_0_M_1
,
2040 EVEX_W_0F16_P_0_M_0
,
2041 EVEX_W_0F16_P_0_M_1
,
2112 EVEX_W_0F72_R_2_P_2
,
2113 EVEX_W_0F72_R_6_P_2
,
2114 EVEX_W_0F73_R_2_P_2
,
2115 EVEX_W_0F73_R_6_P_2
,
2223 EVEX_W_0F38C7_R_1_P_2
,
2224 EVEX_W_0F38C7_R_2_P_2
,
2225 EVEX_W_0F38C7_R_5_P_2
,
2226 EVEX_W_0F38C7_R_6_P_2
,
2265 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2274 unsigned int prefix_requirement
;
2277 /* Upper case letters in the instruction names here are macros.
2278 'A' => print 'b' if no register operands or suffix_always is true
2279 'B' => print 'b' if suffix_always is true
2280 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2282 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2283 suffix_always is true
2284 'E' => print 'e' if 32-bit form of jcxz
2285 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2286 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2287 'H' => print ",pt" or ",pn" branch hint
2288 'I' => honor following macro letter even in Intel mode (implemented only
2289 for some of the macro letters)
2291 'K' => print 'd' or 'q' if rex prefix is present.
2292 'L' => print 'l' if suffix_always is true
2293 'M' => print 'r' if intel_mnemonic is false.
2294 'N' => print 'n' if instruction has no wait "prefix"
2295 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2296 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2297 or suffix_always is true. print 'q' if rex prefix is present.
2298 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2300 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2301 'S' => print 'w', 'l' or 'q' if suffix_always is true
2302 'T' => print 'q' in 64bit mode if instruction has no operand size
2303 prefix and behave as 'P' otherwise
2304 'U' => print 'q' in 64bit mode if instruction has no operand size
2305 prefix and behave as 'Q' otherwise
2306 'V' => print 'q' in 64bit mode if instruction has no operand size
2307 prefix and behave as 'S' otherwise
2308 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2309 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2311 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2312 '!' => change condition from true to false or from false to true.
2313 '%' => add 1 upper case letter to the macro.
2314 '^' => print 'w' or 'l' depending on operand size prefix or
2315 suffix_always is true (lcall/ljmp).
2316 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2317 on operand size prefix.
2318 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2319 has no operand size prefix for AMD64 ISA, behave as 'P'
2322 2 upper case letter macros:
2323 "XY" => print 'x' or 'y' if suffix_always is true or no register
2324 operands and no broadcast.
2325 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2326 register operands and no broadcast.
2327 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2328 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2329 or suffix_always is true
2330 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2331 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2332 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2333 "LW" => print 'd', 'q' depending on the VEX.W bit
2334 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2335 an operand size prefix, or suffix_always is true. print
2336 'q' if rex prefix is present.
2338 Many of the above letters print nothing in Intel mode. See "putop"
2341 Braces '{' and '}', and vertical bars '|', indicate alternative
2342 mnemonic strings for AT&T and Intel. */
2344 static const struct dis386 dis386
[] = {
2346 { "addB", { Ebh1
, Gb
}, 0 },
2347 { "addS", { Evh1
, Gv
}, 0 },
2348 { "addB", { Gb
, EbS
}, 0 },
2349 { "addS", { Gv
, EvS
}, 0 },
2350 { "addB", { AL
, Ib
}, 0 },
2351 { "addS", { eAX
, Iv
}, 0 },
2352 { X86_64_TABLE (X86_64_06
) },
2353 { X86_64_TABLE (X86_64_07
) },
2355 { "orB", { Ebh1
, Gb
}, 0 },
2356 { "orS", { Evh1
, Gv
}, 0 },
2357 { "orB", { Gb
, EbS
}, 0 },
2358 { "orS", { Gv
, EvS
}, 0 },
2359 { "orB", { AL
, Ib
}, 0 },
2360 { "orS", { eAX
, Iv
}, 0 },
2361 { X86_64_TABLE (X86_64_0D
) },
2362 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2364 { "adcB", { Ebh1
, Gb
}, 0 },
2365 { "adcS", { Evh1
, Gv
}, 0 },
2366 { "adcB", { Gb
, EbS
}, 0 },
2367 { "adcS", { Gv
, EvS
}, 0 },
2368 { "adcB", { AL
, Ib
}, 0 },
2369 { "adcS", { eAX
, Iv
}, 0 },
2370 { X86_64_TABLE (X86_64_16
) },
2371 { X86_64_TABLE (X86_64_17
) },
2373 { "sbbB", { Ebh1
, Gb
}, 0 },
2374 { "sbbS", { Evh1
, Gv
}, 0 },
2375 { "sbbB", { Gb
, EbS
}, 0 },
2376 { "sbbS", { Gv
, EvS
}, 0 },
2377 { "sbbB", { AL
, Ib
}, 0 },
2378 { "sbbS", { eAX
, Iv
}, 0 },
2379 { X86_64_TABLE (X86_64_1E
) },
2380 { X86_64_TABLE (X86_64_1F
) },
2382 { "andB", { Ebh1
, Gb
}, 0 },
2383 { "andS", { Evh1
, Gv
}, 0 },
2384 { "andB", { Gb
, EbS
}, 0 },
2385 { "andS", { Gv
, EvS
}, 0 },
2386 { "andB", { AL
, Ib
}, 0 },
2387 { "andS", { eAX
, Iv
}, 0 },
2388 { Bad_Opcode
}, /* SEG ES prefix */
2389 { X86_64_TABLE (X86_64_27
) },
2391 { "subB", { Ebh1
, Gb
}, 0 },
2392 { "subS", { Evh1
, Gv
}, 0 },
2393 { "subB", { Gb
, EbS
}, 0 },
2394 { "subS", { Gv
, EvS
}, 0 },
2395 { "subB", { AL
, Ib
}, 0 },
2396 { "subS", { eAX
, Iv
}, 0 },
2397 { Bad_Opcode
}, /* SEG CS prefix */
2398 { X86_64_TABLE (X86_64_2F
) },
2400 { "xorB", { Ebh1
, Gb
}, 0 },
2401 { "xorS", { Evh1
, Gv
}, 0 },
2402 { "xorB", { Gb
, EbS
}, 0 },
2403 { "xorS", { Gv
, EvS
}, 0 },
2404 { "xorB", { AL
, Ib
}, 0 },
2405 { "xorS", { eAX
, Iv
}, 0 },
2406 { Bad_Opcode
}, /* SEG SS prefix */
2407 { X86_64_TABLE (X86_64_37
) },
2409 { "cmpB", { Eb
, Gb
}, 0 },
2410 { "cmpS", { Ev
, Gv
}, 0 },
2411 { "cmpB", { Gb
, EbS
}, 0 },
2412 { "cmpS", { Gv
, EvS
}, 0 },
2413 { "cmpB", { AL
, Ib
}, 0 },
2414 { "cmpS", { eAX
, Iv
}, 0 },
2415 { Bad_Opcode
}, /* SEG DS prefix */
2416 { X86_64_TABLE (X86_64_3F
) },
2418 { "inc{S|}", { RMeAX
}, 0 },
2419 { "inc{S|}", { RMeCX
}, 0 },
2420 { "inc{S|}", { RMeDX
}, 0 },
2421 { "inc{S|}", { RMeBX
}, 0 },
2422 { "inc{S|}", { RMeSP
}, 0 },
2423 { "inc{S|}", { RMeBP
}, 0 },
2424 { "inc{S|}", { RMeSI
}, 0 },
2425 { "inc{S|}", { RMeDI
}, 0 },
2427 { "dec{S|}", { RMeAX
}, 0 },
2428 { "dec{S|}", { RMeCX
}, 0 },
2429 { "dec{S|}", { RMeDX
}, 0 },
2430 { "dec{S|}", { RMeBX
}, 0 },
2431 { "dec{S|}", { RMeSP
}, 0 },
2432 { "dec{S|}", { RMeBP
}, 0 },
2433 { "dec{S|}", { RMeSI
}, 0 },
2434 { "dec{S|}", { RMeDI
}, 0 },
2436 { "pushV", { RMrAX
}, 0 },
2437 { "pushV", { RMrCX
}, 0 },
2438 { "pushV", { RMrDX
}, 0 },
2439 { "pushV", { RMrBX
}, 0 },
2440 { "pushV", { RMrSP
}, 0 },
2441 { "pushV", { RMrBP
}, 0 },
2442 { "pushV", { RMrSI
}, 0 },
2443 { "pushV", { RMrDI
}, 0 },
2445 { "popV", { RMrAX
}, 0 },
2446 { "popV", { RMrCX
}, 0 },
2447 { "popV", { RMrDX
}, 0 },
2448 { "popV", { RMrBX
}, 0 },
2449 { "popV", { RMrSP
}, 0 },
2450 { "popV", { RMrBP
}, 0 },
2451 { "popV", { RMrSI
}, 0 },
2452 { "popV", { RMrDI
}, 0 },
2454 { X86_64_TABLE (X86_64_60
) },
2455 { X86_64_TABLE (X86_64_61
) },
2456 { X86_64_TABLE (X86_64_62
) },
2457 { X86_64_TABLE (X86_64_63
) },
2458 { Bad_Opcode
}, /* seg fs */
2459 { Bad_Opcode
}, /* seg gs */
2460 { Bad_Opcode
}, /* op size prefix */
2461 { Bad_Opcode
}, /* adr size prefix */
2463 { "pushT", { sIv
}, 0 },
2464 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2465 { "pushT", { sIbT
}, 0 },
2466 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2467 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2468 { X86_64_TABLE (X86_64_6D
) },
2469 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2470 { X86_64_TABLE (X86_64_6F
) },
2472 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2473 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2474 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2475 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2476 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2477 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2478 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2479 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2481 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2482 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2483 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2484 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2485 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2486 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2487 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2488 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2490 { REG_TABLE (REG_80
) },
2491 { REG_TABLE (REG_81
) },
2492 { X86_64_TABLE (X86_64_82
) },
2493 { REG_TABLE (REG_83
) },
2494 { "testB", { Eb
, Gb
}, 0 },
2495 { "testS", { Ev
, Gv
}, 0 },
2496 { "xchgB", { Ebh2
, Gb
}, 0 },
2497 { "xchgS", { Evh2
, Gv
}, 0 },
2499 { "movB", { Ebh3
, Gb
}, 0 },
2500 { "movS", { Evh3
, Gv
}, 0 },
2501 { "movB", { Gb
, EbS
}, 0 },
2502 { "movS", { Gv
, EvS
}, 0 },
2503 { "movD", { Sv
, Sw
}, 0 },
2504 { MOD_TABLE (MOD_8D
) },
2505 { "movD", { Sw
, Sv
}, 0 },
2506 { REG_TABLE (REG_8F
) },
2508 { PREFIX_TABLE (PREFIX_90
) },
2509 { "xchgS", { RMeCX
, eAX
}, 0 },
2510 { "xchgS", { RMeDX
, eAX
}, 0 },
2511 { "xchgS", { RMeBX
, eAX
}, 0 },
2512 { "xchgS", { RMeSP
, eAX
}, 0 },
2513 { "xchgS", { RMeBP
, eAX
}, 0 },
2514 { "xchgS", { RMeSI
, eAX
}, 0 },
2515 { "xchgS", { RMeDI
, eAX
}, 0 },
2517 { "cW{t|}R", { XX
}, 0 },
2518 { "cR{t|}O", { XX
}, 0 },
2519 { X86_64_TABLE (X86_64_9A
) },
2520 { Bad_Opcode
}, /* fwait */
2521 { "pushfT", { XX
}, 0 },
2522 { "popfT", { XX
}, 0 },
2523 { "sahf", { XX
}, 0 },
2524 { "lahf", { XX
}, 0 },
2526 { "mov%LB", { AL
, Ob
}, 0 },
2527 { "mov%LS", { eAX
, Ov
}, 0 },
2528 { "mov%LB", { Ob
, AL
}, 0 },
2529 { "mov%LS", { Ov
, eAX
}, 0 },
2530 { "movs{b|}", { Ybr
, Xb
}, 0 },
2531 { "movs{R|}", { Yvr
, Xv
}, 0 },
2532 { "cmps{b|}", { Xb
, Yb
}, 0 },
2533 { "cmps{R|}", { Xv
, Yv
}, 0 },
2535 { "testB", { AL
, Ib
}, 0 },
2536 { "testS", { eAX
, Iv
}, 0 },
2537 { "stosB", { Ybr
, AL
}, 0 },
2538 { "stosS", { Yvr
, eAX
}, 0 },
2539 { "lodsB", { ALr
, Xb
}, 0 },
2540 { "lodsS", { eAXr
, Xv
}, 0 },
2541 { "scasB", { AL
, Yb
}, 0 },
2542 { "scasS", { eAX
, Yv
}, 0 },
2544 { "movB", { RMAL
, Ib
}, 0 },
2545 { "movB", { RMCL
, Ib
}, 0 },
2546 { "movB", { RMDL
, Ib
}, 0 },
2547 { "movB", { RMBL
, Ib
}, 0 },
2548 { "movB", { RMAH
, Ib
}, 0 },
2549 { "movB", { RMCH
, Ib
}, 0 },
2550 { "movB", { RMDH
, Ib
}, 0 },
2551 { "movB", { RMBH
, Ib
}, 0 },
2553 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2554 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2555 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2556 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2557 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2558 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2559 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2560 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2562 { REG_TABLE (REG_C0
) },
2563 { REG_TABLE (REG_C1
) },
2564 { "retT", { Iw
, BND
}, 0 },
2565 { "retT", { BND
}, 0 },
2566 { X86_64_TABLE (X86_64_C4
) },
2567 { X86_64_TABLE (X86_64_C5
) },
2568 { REG_TABLE (REG_C6
) },
2569 { REG_TABLE (REG_C7
) },
2571 { "enterT", { Iw
, Ib
}, 0 },
2572 { "leaveT", { XX
}, 0 },
2573 { "Jret{|f}P", { Iw
}, 0 },
2574 { "Jret{|f}P", { XX
}, 0 },
2575 { "int3", { XX
}, 0 },
2576 { "int", { Ib
}, 0 },
2577 { X86_64_TABLE (X86_64_CE
) },
2578 { "iret%LP", { XX
}, 0 },
2580 { REG_TABLE (REG_D0
) },
2581 { REG_TABLE (REG_D1
) },
2582 { REG_TABLE (REG_D2
) },
2583 { REG_TABLE (REG_D3
) },
2584 { X86_64_TABLE (X86_64_D4
) },
2585 { X86_64_TABLE (X86_64_D5
) },
2587 { "xlat", { DSBX
}, 0 },
2598 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2599 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2600 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2601 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2602 { "inB", { AL
, Ib
}, 0 },
2603 { "inG", { zAX
, Ib
}, 0 },
2604 { "outB", { Ib
, AL
}, 0 },
2605 { "outG", { Ib
, zAX
}, 0 },
2607 { X86_64_TABLE (X86_64_E8
) },
2608 { X86_64_TABLE (X86_64_E9
) },
2609 { X86_64_TABLE (X86_64_EA
) },
2610 { "jmp", { Jb
, BND
}, 0 },
2611 { "inB", { AL
, indirDX
}, 0 },
2612 { "inG", { zAX
, indirDX
}, 0 },
2613 { "outB", { indirDX
, AL
}, 0 },
2614 { "outG", { indirDX
, zAX
}, 0 },
2616 { Bad_Opcode
}, /* lock prefix */
2617 { "icebp", { XX
}, 0 },
2618 { Bad_Opcode
}, /* repne */
2619 { Bad_Opcode
}, /* repz */
2620 { "hlt", { XX
}, 0 },
2621 { "cmc", { XX
}, 0 },
2622 { REG_TABLE (REG_F6
) },
2623 { REG_TABLE (REG_F7
) },
2625 { "clc", { XX
}, 0 },
2626 { "stc", { XX
}, 0 },
2627 { "cli", { XX
}, 0 },
2628 { "sti", { XX
}, 0 },
2629 { "cld", { XX
}, 0 },
2630 { "std", { XX
}, 0 },
2631 { REG_TABLE (REG_FE
) },
2632 { REG_TABLE (REG_FF
) },
2635 static const struct dis386 dis386_twobyte
[] = {
2637 { REG_TABLE (REG_0F00
) },
2638 { REG_TABLE (REG_0F01
) },
2639 { "larS", { Gv
, Ew
}, 0 },
2640 { "lslS", { Gv
, Ew
}, 0 },
2642 { "syscall", { XX
}, 0 },
2643 { "clts", { XX
}, 0 },
2644 { "sysret%LP", { XX
}, 0 },
2646 { "invd", { XX
}, 0 },
2647 { PREFIX_TABLE (PREFIX_0F09
) },
2649 { "ud2", { XX
}, 0 },
2651 { REG_TABLE (REG_0F0D
) },
2652 { "femms", { XX
}, 0 },
2653 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2655 { PREFIX_TABLE (PREFIX_0F10
) },
2656 { PREFIX_TABLE (PREFIX_0F11
) },
2657 { PREFIX_TABLE (PREFIX_0F12
) },
2658 { MOD_TABLE (MOD_0F13
) },
2659 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2660 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2661 { PREFIX_TABLE (PREFIX_0F16
) },
2662 { MOD_TABLE (MOD_0F17
) },
2664 { REG_TABLE (REG_0F18
) },
2665 { "nopQ", { Ev
}, 0 },
2666 { PREFIX_TABLE (PREFIX_0F1A
) },
2667 { PREFIX_TABLE (PREFIX_0F1B
) },
2668 { PREFIX_TABLE (PREFIX_0F1C
) },
2669 { "nopQ", { Ev
}, 0 },
2670 { PREFIX_TABLE (PREFIX_0F1E
) },
2671 { "nopQ", { Ev
}, 0 },
2673 { "movZ", { Rm
, Cm
}, 0 },
2674 { "movZ", { Rm
, Dm
}, 0 },
2675 { "movZ", { Cm
, Rm
}, 0 },
2676 { "movZ", { Dm
, Rm
}, 0 },
2677 { MOD_TABLE (MOD_0F24
) },
2679 { MOD_TABLE (MOD_0F26
) },
2682 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2683 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2684 { PREFIX_TABLE (PREFIX_0F2A
) },
2685 { PREFIX_TABLE (PREFIX_0F2B
) },
2686 { PREFIX_TABLE (PREFIX_0F2C
) },
2687 { PREFIX_TABLE (PREFIX_0F2D
) },
2688 { PREFIX_TABLE (PREFIX_0F2E
) },
2689 { PREFIX_TABLE (PREFIX_0F2F
) },
2691 { "wrmsr", { XX
}, 0 },
2692 { "rdtsc", { XX
}, 0 },
2693 { "rdmsr", { XX
}, 0 },
2694 { "rdpmc", { XX
}, 0 },
2695 { "sysenter", { XX
}, 0 },
2696 { "sysexit", { XX
}, 0 },
2698 { "getsec", { XX
}, 0 },
2700 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2702 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2709 { "cmovoS", { Gv
, Ev
}, 0 },
2710 { "cmovnoS", { Gv
, Ev
}, 0 },
2711 { "cmovbS", { Gv
, Ev
}, 0 },
2712 { "cmovaeS", { Gv
, Ev
}, 0 },
2713 { "cmoveS", { Gv
, Ev
}, 0 },
2714 { "cmovneS", { Gv
, Ev
}, 0 },
2715 { "cmovbeS", { Gv
, Ev
}, 0 },
2716 { "cmovaS", { Gv
, Ev
}, 0 },
2718 { "cmovsS", { Gv
, Ev
}, 0 },
2719 { "cmovnsS", { Gv
, Ev
}, 0 },
2720 { "cmovpS", { Gv
, Ev
}, 0 },
2721 { "cmovnpS", { Gv
, Ev
}, 0 },
2722 { "cmovlS", { Gv
, Ev
}, 0 },
2723 { "cmovgeS", { Gv
, Ev
}, 0 },
2724 { "cmovleS", { Gv
, Ev
}, 0 },
2725 { "cmovgS", { Gv
, Ev
}, 0 },
2727 { MOD_TABLE (MOD_0F51
) },
2728 { PREFIX_TABLE (PREFIX_0F51
) },
2729 { PREFIX_TABLE (PREFIX_0F52
) },
2730 { PREFIX_TABLE (PREFIX_0F53
) },
2731 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2732 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2733 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2734 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2736 { PREFIX_TABLE (PREFIX_0F58
) },
2737 { PREFIX_TABLE (PREFIX_0F59
) },
2738 { PREFIX_TABLE (PREFIX_0F5A
) },
2739 { PREFIX_TABLE (PREFIX_0F5B
) },
2740 { PREFIX_TABLE (PREFIX_0F5C
) },
2741 { PREFIX_TABLE (PREFIX_0F5D
) },
2742 { PREFIX_TABLE (PREFIX_0F5E
) },
2743 { PREFIX_TABLE (PREFIX_0F5F
) },
2745 { PREFIX_TABLE (PREFIX_0F60
) },
2746 { PREFIX_TABLE (PREFIX_0F61
) },
2747 { PREFIX_TABLE (PREFIX_0F62
) },
2748 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2749 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2750 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2751 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2752 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2754 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2755 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2756 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2757 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2758 { PREFIX_TABLE (PREFIX_0F6C
) },
2759 { PREFIX_TABLE (PREFIX_0F6D
) },
2760 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2761 { PREFIX_TABLE (PREFIX_0F6F
) },
2763 { PREFIX_TABLE (PREFIX_0F70
) },
2764 { REG_TABLE (REG_0F71
) },
2765 { REG_TABLE (REG_0F72
) },
2766 { REG_TABLE (REG_0F73
) },
2767 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2768 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2769 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2770 { "emms", { XX
}, PREFIX_OPCODE
},
2772 { PREFIX_TABLE (PREFIX_0F78
) },
2773 { PREFIX_TABLE (PREFIX_0F79
) },
2776 { PREFIX_TABLE (PREFIX_0F7C
) },
2777 { PREFIX_TABLE (PREFIX_0F7D
) },
2778 { PREFIX_TABLE (PREFIX_0F7E
) },
2779 { PREFIX_TABLE (PREFIX_0F7F
) },
2781 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2782 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2783 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2784 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2785 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2786 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2787 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2788 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2790 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2791 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2792 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2793 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2794 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2795 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2796 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2797 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2799 { "seto", { Eb
}, 0 },
2800 { "setno", { Eb
}, 0 },
2801 { "setb", { Eb
}, 0 },
2802 { "setae", { Eb
}, 0 },
2803 { "sete", { Eb
}, 0 },
2804 { "setne", { Eb
}, 0 },
2805 { "setbe", { Eb
}, 0 },
2806 { "seta", { Eb
}, 0 },
2808 { "sets", { Eb
}, 0 },
2809 { "setns", { Eb
}, 0 },
2810 { "setp", { Eb
}, 0 },
2811 { "setnp", { Eb
}, 0 },
2812 { "setl", { Eb
}, 0 },
2813 { "setge", { Eb
}, 0 },
2814 { "setle", { Eb
}, 0 },
2815 { "setg", { Eb
}, 0 },
2817 { "pushT", { fs
}, 0 },
2818 { "popT", { fs
}, 0 },
2819 { "cpuid", { XX
}, 0 },
2820 { "btS", { Ev
, Gv
}, 0 },
2821 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2822 { "shldS", { Ev
, Gv
, CL
}, 0 },
2823 { REG_TABLE (REG_0FA6
) },
2824 { REG_TABLE (REG_0FA7
) },
2826 { "pushT", { gs
}, 0 },
2827 { "popT", { gs
}, 0 },
2828 { "rsm", { XX
}, 0 },
2829 { "btsS", { Evh1
, Gv
}, 0 },
2830 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2831 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2832 { REG_TABLE (REG_0FAE
) },
2833 { "imulS", { Gv
, Ev
}, 0 },
2835 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2836 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2837 { MOD_TABLE (MOD_0FB2
) },
2838 { "btrS", { Evh1
, Gv
}, 0 },
2839 { MOD_TABLE (MOD_0FB4
) },
2840 { MOD_TABLE (MOD_0FB5
) },
2841 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2842 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2844 { PREFIX_TABLE (PREFIX_0FB8
) },
2845 { "ud1S", { Gv
, Ev
}, 0 },
2846 { REG_TABLE (REG_0FBA
) },
2847 { "btcS", { Evh1
, Gv
}, 0 },
2848 { PREFIX_TABLE (PREFIX_0FBC
) },
2849 { PREFIX_TABLE (PREFIX_0FBD
) },
2850 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2851 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2853 { "xaddB", { Ebh1
, Gb
}, 0 },
2854 { "xaddS", { Evh1
, Gv
}, 0 },
2855 { PREFIX_TABLE (PREFIX_0FC2
) },
2856 { MOD_TABLE (MOD_0FC3
) },
2857 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2858 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2859 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2860 { REG_TABLE (REG_0FC7
) },
2862 { "bswap", { RMeAX
}, 0 },
2863 { "bswap", { RMeCX
}, 0 },
2864 { "bswap", { RMeDX
}, 0 },
2865 { "bswap", { RMeBX
}, 0 },
2866 { "bswap", { RMeSP
}, 0 },
2867 { "bswap", { RMeBP
}, 0 },
2868 { "bswap", { RMeSI
}, 0 },
2869 { "bswap", { RMeDI
}, 0 },
2871 { PREFIX_TABLE (PREFIX_0FD0
) },
2872 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2873 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2874 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2875 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2876 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2877 { PREFIX_TABLE (PREFIX_0FD6
) },
2878 { MOD_TABLE (MOD_0FD7
) },
2880 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2881 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2882 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2883 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2884 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2885 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2886 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2887 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2889 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2890 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2891 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2892 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2893 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2894 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2895 { PREFIX_TABLE (PREFIX_0FE6
) },
2896 { PREFIX_TABLE (PREFIX_0FE7
) },
2898 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2899 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2900 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2901 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2902 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2903 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2904 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2905 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2907 { PREFIX_TABLE (PREFIX_0FF0
) },
2908 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2909 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2910 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2911 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2912 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2913 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2914 { PREFIX_TABLE (PREFIX_0FF7
) },
2916 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2917 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2918 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2919 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2920 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2921 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2922 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2923 { "ud0S", { Gv
, Ev
}, 0 },
2926 static const unsigned char onebyte_has_modrm
[256] = {
2927 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2928 /* ------------------------------- */
2929 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2930 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2931 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2932 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2933 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2934 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2935 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2936 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2937 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2938 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2939 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2940 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2941 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2942 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2943 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2944 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2945 /* ------------------------------- */
2946 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2949 static const unsigned char twobyte_has_modrm
[256] = {
2950 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2951 /* ------------------------------- */
2952 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2953 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2954 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2955 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2956 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2957 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2958 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2959 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2960 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2961 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2962 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2963 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2964 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2965 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2966 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2967 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2968 /* ------------------------------- */
2969 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2972 static char obuf
[100];
2974 static char *mnemonicendp
;
2975 static char scratchbuf
[100];
2976 static unsigned char *start_codep
;
2977 static unsigned char *insn_codep
;
2978 static unsigned char *codep
;
2979 static unsigned char *end_codep
;
2980 static int last_lock_prefix
;
2981 static int last_repz_prefix
;
2982 static int last_repnz_prefix
;
2983 static int last_data_prefix
;
2984 static int last_addr_prefix
;
2985 static int last_rex_prefix
;
2986 static int last_seg_prefix
;
2987 static int fwait_prefix
;
2988 /* The active segment register prefix. */
2989 static int active_seg_prefix
;
2990 #define MAX_CODE_LENGTH 15
2991 /* We can up to 14 prefixes since the maximum instruction length is
2993 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2994 static disassemble_info
*the_info
;
3002 static unsigned char need_modrm
;
3012 int register_specifier
;
3019 int mask_register_specifier
;
3025 static unsigned char need_vex
;
3026 static unsigned char need_vex_reg
;
3027 static unsigned char vex_w_done
;
3035 /* If we are accessing mod/rm/reg without need_modrm set, then the
3036 values are stale. Hitting this abort likely indicates that you
3037 need to update onebyte_has_modrm or twobyte_has_modrm. */
3038 #define MODRM_CHECK if (!need_modrm) abort ()
3040 static const char **names64
;
3041 static const char **names32
;
3042 static const char **names16
;
3043 static const char **names8
;
3044 static const char **names8rex
;
3045 static const char **names_seg
;
3046 static const char *index64
;
3047 static const char *index32
;
3048 static const char **index16
;
3049 static const char **names_bnd
;
3051 static const char *intel_names64
[] = {
3052 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3053 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3055 static const char *intel_names32
[] = {
3056 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3057 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3059 static const char *intel_names16
[] = {
3060 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3061 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3063 static const char *intel_names8
[] = {
3064 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3066 static const char *intel_names8rex
[] = {
3067 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3068 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3070 static const char *intel_names_seg
[] = {
3071 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3073 static const char *intel_index64
= "riz";
3074 static const char *intel_index32
= "eiz";
3075 static const char *intel_index16
[] = {
3076 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3079 static const char *att_names64
[] = {
3080 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3081 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3083 static const char *att_names32
[] = {
3084 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3085 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3087 static const char *att_names16
[] = {
3088 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3089 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3091 static const char *att_names8
[] = {
3092 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3094 static const char *att_names8rex
[] = {
3095 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3096 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3098 static const char *att_names_seg
[] = {
3099 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3101 static const char *att_index64
= "%riz";
3102 static const char *att_index32
= "%eiz";
3103 static const char *att_index16
[] = {
3104 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3107 static const char **names_mm
;
3108 static const char *intel_names_mm
[] = {
3109 "mm0", "mm1", "mm2", "mm3",
3110 "mm4", "mm5", "mm6", "mm7"
3112 static const char *att_names_mm
[] = {
3113 "%mm0", "%mm1", "%mm2", "%mm3",
3114 "%mm4", "%mm5", "%mm6", "%mm7"
3117 static const char *intel_names_bnd
[] = {
3118 "bnd0", "bnd1", "bnd2", "bnd3"
3121 static const char *att_names_bnd
[] = {
3122 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3125 static const char **names_xmm
;
3126 static const char *intel_names_xmm
[] = {
3127 "xmm0", "xmm1", "xmm2", "xmm3",
3128 "xmm4", "xmm5", "xmm6", "xmm7",
3129 "xmm8", "xmm9", "xmm10", "xmm11",
3130 "xmm12", "xmm13", "xmm14", "xmm15",
3131 "xmm16", "xmm17", "xmm18", "xmm19",
3132 "xmm20", "xmm21", "xmm22", "xmm23",
3133 "xmm24", "xmm25", "xmm26", "xmm27",
3134 "xmm28", "xmm29", "xmm30", "xmm31"
3136 static const char *att_names_xmm
[] = {
3137 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3138 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3139 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3140 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3141 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3142 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3143 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3144 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3147 static const char **names_ymm
;
3148 static const char *intel_names_ymm
[] = {
3149 "ymm0", "ymm1", "ymm2", "ymm3",
3150 "ymm4", "ymm5", "ymm6", "ymm7",
3151 "ymm8", "ymm9", "ymm10", "ymm11",
3152 "ymm12", "ymm13", "ymm14", "ymm15",
3153 "ymm16", "ymm17", "ymm18", "ymm19",
3154 "ymm20", "ymm21", "ymm22", "ymm23",
3155 "ymm24", "ymm25", "ymm26", "ymm27",
3156 "ymm28", "ymm29", "ymm30", "ymm31"
3158 static const char *att_names_ymm
[] = {
3159 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3160 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3161 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3162 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3163 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3164 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3165 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3166 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3169 static const char **names_zmm
;
3170 static const char *intel_names_zmm
[] = {
3171 "zmm0", "zmm1", "zmm2", "zmm3",
3172 "zmm4", "zmm5", "zmm6", "zmm7",
3173 "zmm8", "zmm9", "zmm10", "zmm11",
3174 "zmm12", "zmm13", "zmm14", "zmm15",
3175 "zmm16", "zmm17", "zmm18", "zmm19",
3176 "zmm20", "zmm21", "zmm22", "zmm23",
3177 "zmm24", "zmm25", "zmm26", "zmm27",
3178 "zmm28", "zmm29", "zmm30", "zmm31"
3180 static const char *att_names_zmm
[] = {
3181 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3182 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3183 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3184 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3185 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3186 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3187 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3188 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3191 static const char **names_mask
;
3192 static const char *intel_names_mask
[] = {
3193 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3195 static const char *att_names_mask
[] = {
3196 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3199 static const char *names_rounding
[] =
3207 static const struct dis386 reg_table
[][8] = {
3210 { "addA", { Ebh1
, Ib
}, 0 },
3211 { "orA", { Ebh1
, Ib
}, 0 },
3212 { "adcA", { Ebh1
, Ib
}, 0 },
3213 { "sbbA", { Ebh1
, Ib
}, 0 },
3214 { "andA", { Ebh1
, Ib
}, 0 },
3215 { "subA", { Ebh1
, Ib
}, 0 },
3216 { "xorA", { Ebh1
, Ib
}, 0 },
3217 { "cmpA", { Eb
, Ib
}, 0 },
3221 { "addQ", { Evh1
, Iv
}, 0 },
3222 { "orQ", { Evh1
, Iv
}, 0 },
3223 { "adcQ", { Evh1
, Iv
}, 0 },
3224 { "sbbQ", { Evh1
, Iv
}, 0 },
3225 { "andQ", { Evh1
, Iv
}, 0 },
3226 { "subQ", { Evh1
, Iv
}, 0 },
3227 { "xorQ", { Evh1
, Iv
}, 0 },
3228 { "cmpQ", { Ev
, Iv
}, 0 },
3232 { "addQ", { Evh1
, sIb
}, 0 },
3233 { "orQ", { Evh1
, sIb
}, 0 },
3234 { "adcQ", { Evh1
, sIb
}, 0 },
3235 { "sbbQ", { Evh1
, sIb
}, 0 },
3236 { "andQ", { Evh1
, sIb
}, 0 },
3237 { "subQ", { Evh1
, sIb
}, 0 },
3238 { "xorQ", { Evh1
, sIb
}, 0 },
3239 { "cmpQ", { Ev
, sIb
}, 0 },
3243 { "popU", { stackEv
}, 0 },
3244 { XOP_8F_TABLE (XOP_09
) },
3248 { XOP_8F_TABLE (XOP_09
) },
3252 { "rolA", { Eb
, Ib
}, 0 },
3253 { "rorA", { Eb
, Ib
}, 0 },
3254 { "rclA", { Eb
, Ib
}, 0 },
3255 { "rcrA", { Eb
, Ib
}, 0 },
3256 { "shlA", { Eb
, Ib
}, 0 },
3257 { "shrA", { Eb
, Ib
}, 0 },
3258 { "shlA", { Eb
, Ib
}, 0 },
3259 { "sarA", { Eb
, Ib
}, 0 },
3263 { "rolQ", { Ev
, Ib
}, 0 },
3264 { "rorQ", { Ev
, Ib
}, 0 },
3265 { "rclQ", { Ev
, Ib
}, 0 },
3266 { "rcrQ", { Ev
, Ib
}, 0 },
3267 { "shlQ", { Ev
, Ib
}, 0 },
3268 { "shrQ", { Ev
, Ib
}, 0 },
3269 { "shlQ", { Ev
, Ib
}, 0 },
3270 { "sarQ", { Ev
, Ib
}, 0 },
3274 { "movA", { Ebh3
, Ib
}, 0 },
3281 { MOD_TABLE (MOD_C6_REG_7
) },
3285 { "movQ", { Evh3
, Iv
}, 0 },
3292 { MOD_TABLE (MOD_C7_REG_7
) },
3296 { "rolA", { Eb
, I1
}, 0 },
3297 { "rorA", { Eb
, I1
}, 0 },
3298 { "rclA", { Eb
, I1
}, 0 },
3299 { "rcrA", { Eb
, I1
}, 0 },
3300 { "shlA", { Eb
, I1
}, 0 },
3301 { "shrA", { Eb
, I1
}, 0 },
3302 { "shlA", { Eb
, I1
}, 0 },
3303 { "sarA", { Eb
, I1
}, 0 },
3307 { "rolQ", { Ev
, I1
}, 0 },
3308 { "rorQ", { Ev
, I1
}, 0 },
3309 { "rclQ", { Ev
, I1
}, 0 },
3310 { "rcrQ", { Ev
, I1
}, 0 },
3311 { "shlQ", { Ev
, I1
}, 0 },
3312 { "shrQ", { Ev
, I1
}, 0 },
3313 { "shlQ", { Ev
, I1
}, 0 },
3314 { "sarQ", { Ev
, I1
}, 0 },
3318 { "rolA", { Eb
, CL
}, 0 },
3319 { "rorA", { Eb
, CL
}, 0 },
3320 { "rclA", { Eb
, CL
}, 0 },
3321 { "rcrA", { Eb
, CL
}, 0 },
3322 { "shlA", { Eb
, CL
}, 0 },
3323 { "shrA", { Eb
, CL
}, 0 },
3324 { "shlA", { Eb
, CL
}, 0 },
3325 { "sarA", { Eb
, CL
}, 0 },
3329 { "rolQ", { Ev
, CL
}, 0 },
3330 { "rorQ", { Ev
, CL
}, 0 },
3331 { "rclQ", { Ev
, CL
}, 0 },
3332 { "rcrQ", { Ev
, CL
}, 0 },
3333 { "shlQ", { Ev
, CL
}, 0 },
3334 { "shrQ", { Ev
, CL
}, 0 },
3335 { "shlQ", { Ev
, CL
}, 0 },
3336 { "sarQ", { Ev
, CL
}, 0 },
3340 { "testA", { Eb
, Ib
}, 0 },
3341 { "testA", { Eb
, Ib
}, 0 },
3342 { "notA", { Ebh1
}, 0 },
3343 { "negA", { Ebh1
}, 0 },
3344 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3345 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3346 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3347 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3351 { "testQ", { Ev
, Iv
}, 0 },
3352 { "testQ", { Ev
, Iv
}, 0 },
3353 { "notQ", { Evh1
}, 0 },
3354 { "negQ", { Evh1
}, 0 },
3355 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3356 { "imulQ", { Ev
}, 0 },
3357 { "divQ", { Ev
}, 0 },
3358 { "idivQ", { Ev
}, 0 },
3362 { "incA", { Ebh1
}, 0 },
3363 { "decA", { Ebh1
}, 0 },
3367 { "incQ", { Evh1
}, 0 },
3368 { "decQ", { Evh1
}, 0 },
3369 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3370 { MOD_TABLE (MOD_FF_REG_3
) },
3371 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3372 { MOD_TABLE (MOD_FF_REG_5
) },
3373 { "pushU", { stackEv
}, 0 },
3378 { "sldtD", { Sv
}, 0 },
3379 { "strD", { Sv
}, 0 },
3380 { "lldt", { Ew
}, 0 },
3381 { "ltr", { Ew
}, 0 },
3382 { "verr", { Ew
}, 0 },
3383 { "verw", { Ew
}, 0 },
3389 { MOD_TABLE (MOD_0F01_REG_0
) },
3390 { MOD_TABLE (MOD_0F01_REG_1
) },
3391 { MOD_TABLE (MOD_0F01_REG_2
) },
3392 { MOD_TABLE (MOD_0F01_REG_3
) },
3393 { "smswD", { Sv
}, 0 },
3394 { MOD_TABLE (MOD_0F01_REG_5
) },
3395 { "lmsw", { Ew
}, 0 },
3396 { MOD_TABLE (MOD_0F01_REG_7
) },
3400 { "prefetch", { Mb
}, 0 },
3401 { "prefetchw", { Mb
}, 0 },
3402 { "prefetchwt1", { Mb
}, 0 },
3403 { "prefetch", { Mb
}, 0 },
3404 { "prefetch", { Mb
}, 0 },
3405 { "prefetch", { Mb
}, 0 },
3406 { "prefetch", { Mb
}, 0 },
3407 { "prefetch", { Mb
}, 0 },
3411 { MOD_TABLE (MOD_0F18_REG_0
) },
3412 { MOD_TABLE (MOD_0F18_REG_1
) },
3413 { MOD_TABLE (MOD_0F18_REG_2
) },
3414 { MOD_TABLE (MOD_0F18_REG_3
) },
3415 { MOD_TABLE (MOD_0F18_REG_4
) },
3416 { MOD_TABLE (MOD_0F18_REG_5
) },
3417 { MOD_TABLE (MOD_0F18_REG_6
) },
3418 { MOD_TABLE (MOD_0F18_REG_7
) },
3420 /* REG_0F1C_MOD_0 */
3422 { "cldemote", { Mb
}, 0 },
3423 { "nopQ", { Ev
}, 0 },
3424 { "nopQ", { Ev
}, 0 },
3425 { "nopQ", { Ev
}, 0 },
3426 { "nopQ", { Ev
}, 0 },
3427 { "nopQ", { Ev
}, 0 },
3428 { "nopQ", { Ev
}, 0 },
3429 { "nopQ", { Ev
}, 0 },
3431 /* REG_0F1E_MOD_3 */
3433 { "nopQ", { Ev
}, 0 },
3434 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3435 { "nopQ", { Ev
}, 0 },
3436 { "nopQ", { Ev
}, 0 },
3437 { "nopQ", { Ev
}, 0 },
3438 { "nopQ", { Ev
}, 0 },
3439 { "nopQ", { Ev
}, 0 },
3440 { RM_TABLE (RM_0F1E_MOD_3_REG_7
) },
3446 { MOD_TABLE (MOD_0F71_REG_2
) },
3448 { MOD_TABLE (MOD_0F71_REG_4
) },
3450 { MOD_TABLE (MOD_0F71_REG_6
) },
3456 { MOD_TABLE (MOD_0F72_REG_2
) },
3458 { MOD_TABLE (MOD_0F72_REG_4
) },
3460 { MOD_TABLE (MOD_0F72_REG_6
) },
3466 { MOD_TABLE (MOD_0F73_REG_2
) },
3467 { MOD_TABLE (MOD_0F73_REG_3
) },
3470 { MOD_TABLE (MOD_0F73_REG_6
) },
3471 { MOD_TABLE (MOD_0F73_REG_7
) },
3475 { "montmul", { { OP_0f07
, 0 } }, 0 },
3476 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3477 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3481 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3482 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3483 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3484 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3485 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3486 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3490 { MOD_TABLE (MOD_0FAE_REG_0
) },
3491 { MOD_TABLE (MOD_0FAE_REG_1
) },
3492 { MOD_TABLE (MOD_0FAE_REG_2
) },
3493 { MOD_TABLE (MOD_0FAE_REG_3
) },
3494 { MOD_TABLE (MOD_0FAE_REG_4
) },
3495 { MOD_TABLE (MOD_0FAE_REG_5
) },
3496 { MOD_TABLE (MOD_0FAE_REG_6
) },
3497 { MOD_TABLE (MOD_0FAE_REG_7
) },
3505 { "btQ", { Ev
, Ib
}, 0 },
3506 { "btsQ", { Evh1
, Ib
}, 0 },
3507 { "btrQ", { Evh1
, Ib
}, 0 },
3508 { "btcQ", { Evh1
, Ib
}, 0 },
3513 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3515 { MOD_TABLE (MOD_0FC7_REG_3
) },
3516 { MOD_TABLE (MOD_0FC7_REG_4
) },
3517 { MOD_TABLE (MOD_0FC7_REG_5
) },
3518 { MOD_TABLE (MOD_0FC7_REG_6
) },
3519 { MOD_TABLE (MOD_0FC7_REG_7
) },
3525 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3527 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3529 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3535 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3537 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3539 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3545 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3546 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3549 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3550 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3556 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3557 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3559 /* REG_VEX_0F38F3 */
3562 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3563 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3564 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3568 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3569 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3573 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3574 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3576 /* REG_XOP_TBM_01 */
3579 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3580 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3581 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3582 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3583 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3584 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3585 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3587 /* REG_XOP_TBM_02 */
3590 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3595 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3597 #define NEED_REG_TABLE
3598 #include "i386-dis-evex.h"
3599 #undef NEED_REG_TABLE
3602 static const struct dis386 prefix_table
[][4] = {
3605 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3606 { "pause", { XX
}, 0 },
3607 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3608 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3611 /* PREFIX_MOD_0_0F01_REG_5 */
3614 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3617 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3620 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3623 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3626 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3631 { "wbinvd", { XX
}, 0 },
3632 { "wbnoinvd", { XX
}, 0 },
3637 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3638 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3639 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3640 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3645 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3646 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3647 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3648 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3653 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3654 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3655 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3656 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3661 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3662 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3663 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3668 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3669 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3670 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3671 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3676 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3677 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3678 { "bndmov", { EbndS
, Gbnd
}, 0 },
3679 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3684 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3685 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3686 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3687 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3692 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3693 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3694 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3695 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3700 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3701 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_OPCODE
},
3702 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3703 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3708 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3709 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3710 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3711 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3716 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3717 { "cvttss2si", { Gv
, EXd
}, PREFIX_OPCODE
},
3718 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3719 { "cvttsd2si", { Gv
, EXq
}, PREFIX_OPCODE
},
3724 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3725 { "cvtss2si", { Gv
, EXd
}, PREFIX_OPCODE
},
3726 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3727 { "cvtsd2si", { Gv
, EXq
}, PREFIX_OPCODE
},
3732 { "ucomiss",{ XM
, EXd
}, 0 },
3734 { "ucomisd",{ XM
, EXq
}, 0 },
3739 { "comiss", { XM
, EXd
}, 0 },
3741 { "comisd", { XM
, EXq
}, 0 },
3746 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3747 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3748 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3749 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3754 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3755 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3760 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3761 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3766 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3767 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3768 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3769 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3774 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3775 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3776 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3777 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3782 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3783 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3784 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3785 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3790 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3791 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3792 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3797 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3798 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3799 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3800 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3805 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3806 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3807 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3808 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3813 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3814 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3815 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3816 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3821 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3822 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3823 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3824 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3829 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3831 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3836 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3838 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3843 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3845 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3852 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3859 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3864 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3865 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3866 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3871 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3872 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3873 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3874 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3877 /* PREFIX_0F73_REG_3 */
3881 { "psrldq", { XS
, Ib
}, 0 },
3884 /* PREFIX_0F73_REG_7 */
3888 { "pslldq", { XS
, Ib
}, 0 },
3893 {"vmread", { Em
, Gm
}, 0 },
3895 {"extrq", { XS
, Ib
, Ib
}, 0 },
3896 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3901 {"vmwrite", { Gm
, Em
}, 0 },
3903 {"extrq", { XM
, XS
}, 0 },
3904 {"insertq", { XM
, XS
}, 0 },
3911 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3912 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3919 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3920 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3925 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3926 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3927 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3932 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3933 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3934 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3937 /* PREFIX_0FAE_REG_0 */
3940 { "rdfsbase", { Ev
}, 0 },
3943 /* PREFIX_0FAE_REG_1 */
3946 { "rdgsbase", { Ev
}, 0 },
3949 /* PREFIX_0FAE_REG_2 */
3952 { "wrfsbase", { Ev
}, 0 },
3955 /* PREFIX_0FAE_REG_3 */
3958 { "wrgsbase", { Ev
}, 0 },
3961 /* PREFIX_MOD_0_0FAE_REG_4 */
3963 { "xsave", { FXSAVE
}, 0 },
3964 { "ptwrite%LQ", { Edq
}, 0 },
3967 /* PREFIX_MOD_3_0FAE_REG_4 */
3970 { "ptwrite%LQ", { Edq
}, 0 },
3973 /* PREFIX_MOD_0_0FAE_REG_5 */
3975 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
3978 /* PREFIX_MOD_3_0FAE_REG_5 */
3980 { "lfence", { Skip_MODRM
}, 0 },
3981 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
3984 /* PREFIX_MOD_0_0FAE_REG_6 */
3986 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3987 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3988 { "clwb", { Mb
}, PREFIX_OPCODE
},
3991 /* PREFIX_MOD_1_0FAE_REG_6 */
3993 { RM_TABLE (RM_0FAE_REG_6
) },
3994 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3995 { "tpause", { Edq
}, PREFIX_OPCODE
},
3996 { "umwait", { Edq
}, PREFIX_OPCODE
},
3999 /* PREFIX_0FAE_REG_7 */
4001 { "clflush", { Mb
}, 0 },
4003 { "clflushopt", { Mb
}, 0 },
4009 { "popcntS", { Gv
, Ev
}, 0 },
4014 { "bsfS", { Gv
, Ev
}, 0 },
4015 { "tzcntS", { Gv
, Ev
}, 0 },
4016 { "bsfS", { Gv
, Ev
}, 0 },
4021 { "bsrS", { Gv
, Ev
}, 0 },
4022 { "lzcntS", { Gv
, Ev
}, 0 },
4023 { "bsrS", { Gv
, Ev
}, 0 },
4028 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4029 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4030 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4031 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4034 /* PREFIX_MOD_0_0FC3 */
4036 { "movntiS", { Ev
, Gv
}, PREFIX_OPCODE
},
4039 /* PREFIX_MOD_0_0FC7_REG_6 */
4041 { "vmptrld",{ Mq
}, 0 },
4042 { "vmxon", { Mq
}, 0 },
4043 { "vmclear",{ Mq
}, 0 },
4046 /* PREFIX_MOD_3_0FC7_REG_6 */
4048 { "rdrand", { Ev
}, 0 },
4050 { "rdrand", { Ev
}, 0 }
4053 /* PREFIX_MOD_3_0FC7_REG_7 */
4055 { "rdseed", { Ev
}, 0 },
4056 { "rdpid", { Em
}, 0 },
4057 { "rdseed", { Ev
}, 0 },
4064 { "addsubpd", { XM
, EXx
}, 0 },
4065 { "addsubps", { XM
, EXx
}, 0 },
4071 { "movq2dq",{ XM
, MS
}, 0 },
4072 { "movq", { EXqS
, XM
}, 0 },
4073 { "movdq2q",{ MX
, XS
}, 0 },
4079 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4080 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4081 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4086 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4088 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4096 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4101 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4103 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4110 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4117 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4124 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4131 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4138 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4145 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4152 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4159 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4166 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4173 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4180 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4187 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4194 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4201 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4208 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4215 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4222 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4229 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4236 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4243 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4250 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4257 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4264 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4271 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4278 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4285 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4292 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4299 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4306 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4313 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4320 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4327 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4334 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4341 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4346 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4351 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4356 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4361 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4366 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4371 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4378 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4385 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4392 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4399 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4406 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4413 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4418 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4420 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4421 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4426 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4428 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4429 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4436 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4441 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4442 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4443 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4451 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4456 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4463 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4470 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4477 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4484 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4491 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4498 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4505 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4512 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4519 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4526 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4533 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4540 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4547 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4554 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4561 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4568 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4575 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4582 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4589 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4596 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4603 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4610 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4615 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4622 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4629 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4636 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4639 /* PREFIX_VEX_0F10 */
4641 { "vmovups", { XM
, EXx
}, 0 },
4642 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
4643 { "vmovupd", { XM
, EXx
}, 0 },
4644 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
4647 /* PREFIX_VEX_0F11 */
4649 { "vmovups", { EXxS
, XM
}, 0 },
4650 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4651 { "vmovupd", { EXxS
, XM
}, 0 },
4652 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4655 /* PREFIX_VEX_0F12 */
4657 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4658 { "vmovsldup", { XM
, EXx
}, 0 },
4659 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4660 { "vmovddup", { XM
, EXymmq
}, 0 },
4663 /* PREFIX_VEX_0F16 */
4665 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4666 { "vmovshdup", { XM
, EXx
}, 0 },
4667 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4670 /* PREFIX_VEX_0F2A */
4673 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4675 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4678 /* PREFIX_VEX_0F2C */
4681 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4683 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4686 /* PREFIX_VEX_0F2D */
4689 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4691 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4694 /* PREFIX_VEX_0F2E */
4696 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
4698 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
4701 /* PREFIX_VEX_0F2F */
4703 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
4705 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
4708 /* PREFIX_VEX_0F41 */
4710 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4712 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4715 /* PREFIX_VEX_0F42 */
4717 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4719 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4722 /* PREFIX_VEX_0F44 */
4724 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4726 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4729 /* PREFIX_VEX_0F45 */
4731 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4733 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4736 /* PREFIX_VEX_0F46 */
4738 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4740 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4743 /* PREFIX_VEX_0F47 */
4745 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4747 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4750 /* PREFIX_VEX_0F4A */
4752 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4754 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4757 /* PREFIX_VEX_0F4B */
4759 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4761 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4764 /* PREFIX_VEX_0F51 */
4766 { "vsqrtps", { XM
, EXx
}, 0 },
4767 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4768 { "vsqrtpd", { XM
, EXx
}, 0 },
4769 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4772 /* PREFIX_VEX_0F52 */
4774 { "vrsqrtps", { XM
, EXx
}, 0 },
4775 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4778 /* PREFIX_VEX_0F53 */
4780 { "vrcpps", { XM
, EXx
}, 0 },
4781 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4784 /* PREFIX_VEX_0F58 */
4786 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4787 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4788 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4789 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4792 /* PREFIX_VEX_0F59 */
4794 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4795 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4796 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4797 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4800 /* PREFIX_VEX_0F5A */
4802 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4803 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4804 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4805 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4808 /* PREFIX_VEX_0F5B */
4810 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4811 { "vcvttps2dq", { XM
, EXx
}, 0 },
4812 { "vcvtps2dq", { XM
, EXx
}, 0 },
4815 /* PREFIX_VEX_0F5C */
4817 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4818 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4819 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4820 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4823 /* PREFIX_VEX_0F5D */
4825 { "vminps", { XM
, Vex
, EXx
}, 0 },
4826 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4827 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4828 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4831 /* PREFIX_VEX_0F5E */
4833 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4834 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4835 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4836 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4839 /* PREFIX_VEX_0F5F */
4841 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4842 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4843 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4844 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4847 /* PREFIX_VEX_0F60 */
4851 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4854 /* PREFIX_VEX_0F61 */
4858 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4861 /* PREFIX_VEX_0F62 */
4865 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4868 /* PREFIX_VEX_0F63 */
4872 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4875 /* PREFIX_VEX_0F64 */
4879 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4882 /* PREFIX_VEX_0F65 */
4886 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4889 /* PREFIX_VEX_0F66 */
4893 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4896 /* PREFIX_VEX_0F67 */
4900 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4903 /* PREFIX_VEX_0F68 */
4907 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4910 /* PREFIX_VEX_0F69 */
4914 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4917 /* PREFIX_VEX_0F6A */
4921 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4924 /* PREFIX_VEX_0F6B */
4928 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4931 /* PREFIX_VEX_0F6C */
4935 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4938 /* PREFIX_VEX_0F6D */
4942 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4945 /* PREFIX_VEX_0F6E */
4949 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4952 /* PREFIX_VEX_0F6F */
4955 { "vmovdqu", { XM
, EXx
}, 0 },
4956 { "vmovdqa", { XM
, EXx
}, 0 },
4959 /* PREFIX_VEX_0F70 */
4962 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4963 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4964 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4967 /* PREFIX_VEX_0F71_REG_2 */
4971 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
4974 /* PREFIX_VEX_0F71_REG_4 */
4978 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
4981 /* PREFIX_VEX_0F71_REG_6 */
4985 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
4988 /* PREFIX_VEX_0F72_REG_2 */
4992 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
4995 /* PREFIX_VEX_0F72_REG_4 */
4999 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
5002 /* PREFIX_VEX_0F72_REG_6 */
5006 { "vpslld", { Vex
, XS
, Ib
}, 0 },
5009 /* PREFIX_VEX_0F73_REG_2 */
5013 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5016 /* PREFIX_VEX_0F73_REG_3 */
5020 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5023 /* PREFIX_VEX_0F73_REG_6 */
5027 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5030 /* PREFIX_VEX_0F73_REG_7 */
5034 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5037 /* PREFIX_VEX_0F74 */
5041 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5044 /* PREFIX_VEX_0F75 */
5048 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5051 /* PREFIX_VEX_0F76 */
5055 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5058 /* PREFIX_VEX_0F77 */
5060 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5063 /* PREFIX_VEX_0F7C */
5067 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5068 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5071 /* PREFIX_VEX_0F7D */
5075 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5076 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5079 /* PREFIX_VEX_0F7E */
5082 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5083 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5086 /* PREFIX_VEX_0F7F */
5089 { "vmovdqu", { EXxS
, XM
}, 0 },
5090 { "vmovdqa", { EXxS
, XM
}, 0 },
5093 /* PREFIX_VEX_0F90 */
5095 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5097 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5100 /* PREFIX_VEX_0F91 */
5102 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5104 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5107 /* PREFIX_VEX_0F92 */
5109 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5111 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5112 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5115 /* PREFIX_VEX_0F93 */
5117 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5119 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5120 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5123 /* PREFIX_VEX_0F98 */
5125 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5127 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5130 /* PREFIX_VEX_0F99 */
5132 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5134 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5137 /* PREFIX_VEX_0FC2 */
5139 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5140 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
5141 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5142 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
5145 /* PREFIX_VEX_0FC4 */
5149 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5152 /* PREFIX_VEX_0FC5 */
5156 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5159 /* PREFIX_VEX_0FD0 */
5163 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5164 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5167 /* PREFIX_VEX_0FD1 */
5171 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5174 /* PREFIX_VEX_0FD2 */
5178 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5181 /* PREFIX_VEX_0FD3 */
5185 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5188 /* PREFIX_VEX_0FD4 */
5192 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5195 /* PREFIX_VEX_0FD5 */
5199 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5202 /* PREFIX_VEX_0FD6 */
5206 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5209 /* PREFIX_VEX_0FD7 */
5213 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5216 /* PREFIX_VEX_0FD8 */
5220 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5223 /* PREFIX_VEX_0FD9 */
5227 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5230 /* PREFIX_VEX_0FDA */
5234 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5237 /* PREFIX_VEX_0FDB */
5241 { "vpand", { XM
, Vex
, EXx
}, 0 },
5244 /* PREFIX_VEX_0FDC */
5248 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5251 /* PREFIX_VEX_0FDD */
5255 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5258 /* PREFIX_VEX_0FDE */
5262 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5265 /* PREFIX_VEX_0FDF */
5269 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5272 /* PREFIX_VEX_0FE0 */
5276 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5279 /* PREFIX_VEX_0FE1 */
5283 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5286 /* PREFIX_VEX_0FE2 */
5290 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5293 /* PREFIX_VEX_0FE3 */
5297 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5300 /* PREFIX_VEX_0FE4 */
5304 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5307 /* PREFIX_VEX_0FE5 */
5311 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5314 /* PREFIX_VEX_0FE6 */
5317 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5318 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5319 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5322 /* PREFIX_VEX_0FE7 */
5326 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5329 /* PREFIX_VEX_0FE8 */
5333 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5336 /* PREFIX_VEX_0FE9 */
5340 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5343 /* PREFIX_VEX_0FEA */
5347 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5350 /* PREFIX_VEX_0FEB */
5354 { "vpor", { XM
, Vex
, EXx
}, 0 },
5357 /* PREFIX_VEX_0FEC */
5361 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5364 /* PREFIX_VEX_0FED */
5368 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5371 /* PREFIX_VEX_0FEE */
5375 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5378 /* PREFIX_VEX_0FEF */
5382 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5385 /* PREFIX_VEX_0FF0 */
5390 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5393 /* PREFIX_VEX_0FF1 */
5397 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5400 /* PREFIX_VEX_0FF2 */
5404 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5407 /* PREFIX_VEX_0FF3 */
5411 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5414 /* PREFIX_VEX_0FF4 */
5418 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5421 /* PREFIX_VEX_0FF5 */
5425 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5428 /* PREFIX_VEX_0FF6 */
5432 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5435 /* PREFIX_VEX_0FF7 */
5439 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5442 /* PREFIX_VEX_0FF8 */
5446 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5449 /* PREFIX_VEX_0FF9 */
5453 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5456 /* PREFIX_VEX_0FFA */
5460 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5463 /* PREFIX_VEX_0FFB */
5467 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5470 /* PREFIX_VEX_0FFC */
5474 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5477 /* PREFIX_VEX_0FFD */
5481 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5484 /* PREFIX_VEX_0FFE */
5488 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5491 /* PREFIX_VEX_0F3800 */
5495 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5498 /* PREFIX_VEX_0F3801 */
5502 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5505 /* PREFIX_VEX_0F3802 */
5509 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5512 /* PREFIX_VEX_0F3803 */
5516 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5519 /* PREFIX_VEX_0F3804 */
5523 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5526 /* PREFIX_VEX_0F3805 */
5530 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5533 /* PREFIX_VEX_0F3806 */
5537 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5540 /* PREFIX_VEX_0F3807 */
5544 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5547 /* PREFIX_VEX_0F3808 */
5551 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5554 /* PREFIX_VEX_0F3809 */
5558 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5561 /* PREFIX_VEX_0F380A */
5565 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5568 /* PREFIX_VEX_0F380B */
5572 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5575 /* PREFIX_VEX_0F380C */
5579 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5582 /* PREFIX_VEX_0F380D */
5586 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5589 /* PREFIX_VEX_0F380E */
5593 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5596 /* PREFIX_VEX_0F380F */
5600 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5603 /* PREFIX_VEX_0F3813 */
5607 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5610 /* PREFIX_VEX_0F3816 */
5614 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5617 /* PREFIX_VEX_0F3817 */
5621 { "vptest", { XM
, EXx
}, 0 },
5624 /* PREFIX_VEX_0F3818 */
5628 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5631 /* PREFIX_VEX_0F3819 */
5635 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5638 /* PREFIX_VEX_0F381A */
5642 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5645 /* PREFIX_VEX_0F381C */
5649 { "vpabsb", { XM
, EXx
}, 0 },
5652 /* PREFIX_VEX_0F381D */
5656 { "vpabsw", { XM
, EXx
}, 0 },
5659 /* PREFIX_VEX_0F381E */
5663 { "vpabsd", { XM
, EXx
}, 0 },
5666 /* PREFIX_VEX_0F3820 */
5670 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5673 /* PREFIX_VEX_0F3821 */
5677 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5680 /* PREFIX_VEX_0F3822 */
5684 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5687 /* PREFIX_VEX_0F3823 */
5691 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5694 /* PREFIX_VEX_0F3824 */
5698 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5701 /* PREFIX_VEX_0F3825 */
5705 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5708 /* PREFIX_VEX_0F3828 */
5712 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5715 /* PREFIX_VEX_0F3829 */
5719 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5722 /* PREFIX_VEX_0F382A */
5726 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5729 /* PREFIX_VEX_0F382B */
5733 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5736 /* PREFIX_VEX_0F382C */
5740 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5743 /* PREFIX_VEX_0F382D */
5747 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5750 /* PREFIX_VEX_0F382E */
5754 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5757 /* PREFIX_VEX_0F382F */
5761 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5764 /* PREFIX_VEX_0F3830 */
5768 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5771 /* PREFIX_VEX_0F3831 */
5775 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5778 /* PREFIX_VEX_0F3832 */
5782 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5785 /* PREFIX_VEX_0F3833 */
5789 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5792 /* PREFIX_VEX_0F3834 */
5796 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5799 /* PREFIX_VEX_0F3835 */
5803 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5806 /* PREFIX_VEX_0F3836 */
5810 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5813 /* PREFIX_VEX_0F3837 */
5817 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5820 /* PREFIX_VEX_0F3838 */
5824 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5827 /* PREFIX_VEX_0F3839 */
5831 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5834 /* PREFIX_VEX_0F383A */
5838 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5841 /* PREFIX_VEX_0F383B */
5845 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5848 /* PREFIX_VEX_0F383C */
5852 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5855 /* PREFIX_VEX_0F383D */
5859 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5862 /* PREFIX_VEX_0F383E */
5866 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5869 /* PREFIX_VEX_0F383F */
5873 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5876 /* PREFIX_VEX_0F3840 */
5880 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5883 /* PREFIX_VEX_0F3841 */
5887 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5890 /* PREFIX_VEX_0F3845 */
5894 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5897 /* PREFIX_VEX_0F3846 */
5901 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5904 /* PREFIX_VEX_0F3847 */
5908 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5911 /* PREFIX_VEX_0F3858 */
5915 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5918 /* PREFIX_VEX_0F3859 */
5922 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5925 /* PREFIX_VEX_0F385A */
5929 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5932 /* PREFIX_VEX_0F3878 */
5936 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5939 /* PREFIX_VEX_0F3879 */
5943 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5946 /* PREFIX_VEX_0F388C */
5950 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5953 /* PREFIX_VEX_0F388E */
5957 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5960 /* PREFIX_VEX_0F3890 */
5964 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5967 /* PREFIX_VEX_0F3891 */
5971 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5974 /* PREFIX_VEX_0F3892 */
5978 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5981 /* PREFIX_VEX_0F3893 */
5985 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5988 /* PREFIX_VEX_0F3896 */
5992 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
5995 /* PREFIX_VEX_0F3897 */
5999 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6002 /* PREFIX_VEX_0F3898 */
6006 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6009 /* PREFIX_VEX_0F3899 */
6013 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6016 /* PREFIX_VEX_0F389A */
6020 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6023 /* PREFIX_VEX_0F389B */
6027 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6030 /* PREFIX_VEX_0F389C */
6034 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6037 /* PREFIX_VEX_0F389D */
6041 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6044 /* PREFIX_VEX_0F389E */
6048 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6051 /* PREFIX_VEX_0F389F */
6055 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6058 /* PREFIX_VEX_0F38A6 */
6062 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6066 /* PREFIX_VEX_0F38A7 */
6070 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6073 /* PREFIX_VEX_0F38A8 */
6077 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6080 /* PREFIX_VEX_0F38A9 */
6084 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6087 /* PREFIX_VEX_0F38AA */
6091 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6094 /* PREFIX_VEX_0F38AB */
6098 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6101 /* PREFIX_VEX_0F38AC */
6105 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6108 /* PREFIX_VEX_0F38AD */
6112 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6115 /* PREFIX_VEX_0F38AE */
6119 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6122 /* PREFIX_VEX_0F38AF */
6126 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6129 /* PREFIX_VEX_0F38B6 */
6133 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6136 /* PREFIX_VEX_0F38B7 */
6140 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6143 /* PREFIX_VEX_0F38B8 */
6147 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6150 /* PREFIX_VEX_0F38B9 */
6154 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6157 /* PREFIX_VEX_0F38BA */
6161 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6164 /* PREFIX_VEX_0F38BB */
6168 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6171 /* PREFIX_VEX_0F38BC */
6175 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6178 /* PREFIX_VEX_0F38BD */
6182 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6185 /* PREFIX_VEX_0F38BE */
6189 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6192 /* PREFIX_VEX_0F38BF */
6196 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6199 /* PREFIX_VEX_0F38CF */
6203 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6206 /* PREFIX_VEX_0F38DB */
6210 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6213 /* PREFIX_VEX_0F38DC */
6217 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6220 /* PREFIX_VEX_0F38DD */
6224 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6227 /* PREFIX_VEX_0F38DE */
6231 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6234 /* PREFIX_VEX_0F38DF */
6238 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6241 /* PREFIX_VEX_0F38F2 */
6243 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6246 /* PREFIX_VEX_0F38F3_REG_1 */
6248 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6251 /* PREFIX_VEX_0F38F3_REG_2 */
6253 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6256 /* PREFIX_VEX_0F38F3_REG_3 */
6258 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6261 /* PREFIX_VEX_0F38F5 */
6263 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6264 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6266 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6269 /* PREFIX_VEX_0F38F6 */
6274 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6277 /* PREFIX_VEX_0F38F7 */
6279 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6280 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6281 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6282 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6285 /* PREFIX_VEX_0F3A00 */
6289 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6292 /* PREFIX_VEX_0F3A01 */
6296 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6299 /* PREFIX_VEX_0F3A02 */
6303 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6306 /* PREFIX_VEX_0F3A04 */
6310 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6313 /* PREFIX_VEX_0F3A05 */
6317 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6320 /* PREFIX_VEX_0F3A06 */
6324 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6327 /* PREFIX_VEX_0F3A08 */
6331 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6334 /* PREFIX_VEX_0F3A09 */
6338 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6341 /* PREFIX_VEX_0F3A0A */
6345 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
6348 /* PREFIX_VEX_0F3A0B */
6352 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
6355 /* PREFIX_VEX_0F3A0C */
6359 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6362 /* PREFIX_VEX_0F3A0D */
6366 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6369 /* PREFIX_VEX_0F3A0E */
6373 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6376 /* PREFIX_VEX_0F3A0F */
6380 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6383 /* PREFIX_VEX_0F3A14 */
6387 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6390 /* PREFIX_VEX_0F3A15 */
6394 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6397 /* PREFIX_VEX_0F3A16 */
6401 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6404 /* PREFIX_VEX_0F3A17 */
6408 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6411 /* PREFIX_VEX_0F3A18 */
6415 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6418 /* PREFIX_VEX_0F3A19 */
6422 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6425 /* PREFIX_VEX_0F3A1D */
6429 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6432 /* PREFIX_VEX_0F3A20 */
6436 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6439 /* PREFIX_VEX_0F3A21 */
6443 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6446 /* PREFIX_VEX_0F3A22 */
6450 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6453 /* PREFIX_VEX_0F3A30 */
6457 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6460 /* PREFIX_VEX_0F3A31 */
6464 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6467 /* PREFIX_VEX_0F3A32 */
6471 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6474 /* PREFIX_VEX_0F3A33 */
6478 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6481 /* PREFIX_VEX_0F3A38 */
6485 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6488 /* PREFIX_VEX_0F3A39 */
6492 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6495 /* PREFIX_VEX_0F3A40 */
6499 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6502 /* PREFIX_VEX_0F3A41 */
6506 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6509 /* PREFIX_VEX_0F3A42 */
6513 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6516 /* PREFIX_VEX_0F3A44 */
6520 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6523 /* PREFIX_VEX_0F3A46 */
6527 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6530 /* PREFIX_VEX_0F3A48 */
6534 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6537 /* PREFIX_VEX_0F3A49 */
6541 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6544 /* PREFIX_VEX_0F3A4A */
6548 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6551 /* PREFIX_VEX_0F3A4B */
6555 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6558 /* PREFIX_VEX_0F3A4C */
6562 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6565 /* PREFIX_VEX_0F3A5C */
6569 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6572 /* PREFIX_VEX_0F3A5D */
6576 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6579 /* PREFIX_VEX_0F3A5E */
6583 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6586 /* PREFIX_VEX_0F3A5F */
6590 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6593 /* PREFIX_VEX_0F3A60 */
6597 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6601 /* PREFIX_VEX_0F3A61 */
6605 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6608 /* PREFIX_VEX_0F3A62 */
6612 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6615 /* PREFIX_VEX_0F3A63 */
6619 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6622 /* PREFIX_VEX_0F3A68 */
6626 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6629 /* PREFIX_VEX_0F3A69 */
6633 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6636 /* PREFIX_VEX_0F3A6A */
6640 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6643 /* PREFIX_VEX_0F3A6B */
6647 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6650 /* PREFIX_VEX_0F3A6C */
6654 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6657 /* PREFIX_VEX_0F3A6D */
6661 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6664 /* PREFIX_VEX_0F3A6E */
6668 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6671 /* PREFIX_VEX_0F3A6F */
6675 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6678 /* PREFIX_VEX_0F3A78 */
6682 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6685 /* PREFIX_VEX_0F3A79 */
6689 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6692 /* PREFIX_VEX_0F3A7A */
6696 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6699 /* PREFIX_VEX_0F3A7B */
6703 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6706 /* PREFIX_VEX_0F3A7C */
6710 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6714 /* PREFIX_VEX_0F3A7D */
6718 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6721 /* PREFIX_VEX_0F3A7E */
6725 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6728 /* PREFIX_VEX_0F3A7F */
6732 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6735 /* PREFIX_VEX_0F3ACE */
6739 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6742 /* PREFIX_VEX_0F3ACF */
6746 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6749 /* PREFIX_VEX_0F3ADF */
6753 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6756 /* PREFIX_VEX_0F3AF0 */
6761 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6764 #define NEED_PREFIX_TABLE
6765 #include "i386-dis-evex.h"
6766 #undef NEED_PREFIX_TABLE
6769 static const struct dis386 x86_64_table
[][2] = {
6772 { "pushP", { es
}, 0 },
6777 { "popP", { es
}, 0 },
6782 { "pushP", { cs
}, 0 },
6787 { "pushP", { ss
}, 0 },
6792 { "popP", { ss
}, 0 },
6797 { "pushP", { ds
}, 0 },
6802 { "popP", { ds
}, 0 },
6807 { "daa", { XX
}, 0 },
6812 { "das", { XX
}, 0 },
6817 { "aaa", { XX
}, 0 },
6822 { "aas", { XX
}, 0 },
6827 { "pushaP", { XX
}, 0 },
6832 { "popaP", { XX
}, 0 },
6837 { MOD_TABLE (MOD_62_32BIT
) },
6838 { EVEX_TABLE (EVEX_0F
) },
6843 { "arpl", { Ew
, Gw
}, 0 },
6844 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6849 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6850 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6855 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6856 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6861 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6862 { REG_TABLE (REG_80
) },
6867 { "Jcall{T|}", { Ap
}, 0 },
6872 { MOD_TABLE (MOD_C4_32BIT
) },
6873 { VEX_C4_TABLE (VEX_0F
) },
6878 { MOD_TABLE (MOD_C5_32BIT
) },
6879 { VEX_C5_TABLE (VEX_0F
) },
6884 { "into", { XX
}, 0 },
6889 { "aam", { Ib
}, 0 },
6894 { "aad", { Ib
}, 0 },
6899 { "callP", { Jv
, BND
}, 0 },
6900 { "call@", { Jv
, BND
}, 0 }
6905 { "jmpP", { Jv
, BND
}, 0 },
6906 { "jmp@", { Jv
, BND
}, 0 }
6911 { "Jjmp{T|}", { Ap
}, 0 },
6914 /* X86_64_0F01_REG_0 */
6916 { "sgdt{Q|IQ}", { M
}, 0 },
6917 { "sgdt", { M
}, 0 },
6920 /* X86_64_0F01_REG_1 */
6922 { "sidt{Q|IQ}", { M
}, 0 },
6923 { "sidt", { M
}, 0 },
6926 /* X86_64_0F01_REG_2 */
6928 { "lgdt{Q|Q}", { M
}, 0 },
6929 { "lgdt", { M
}, 0 },
6932 /* X86_64_0F01_REG_3 */
6934 { "lidt{Q|Q}", { M
}, 0 },
6935 { "lidt", { M
}, 0 },
6939 static const struct dis386 three_byte_table
[][256] = {
6941 /* THREE_BYTE_0F38 */
6944 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6945 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6946 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6947 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6948 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6949 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6950 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6951 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6953 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6954 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6955 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6956 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6962 { PREFIX_TABLE (PREFIX_0F3810
) },
6966 { PREFIX_TABLE (PREFIX_0F3814
) },
6967 { PREFIX_TABLE (PREFIX_0F3815
) },
6969 { PREFIX_TABLE (PREFIX_0F3817
) },
6975 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
6976 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
6977 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
6980 { PREFIX_TABLE (PREFIX_0F3820
) },
6981 { PREFIX_TABLE (PREFIX_0F3821
) },
6982 { PREFIX_TABLE (PREFIX_0F3822
) },
6983 { PREFIX_TABLE (PREFIX_0F3823
) },
6984 { PREFIX_TABLE (PREFIX_0F3824
) },
6985 { PREFIX_TABLE (PREFIX_0F3825
) },
6989 { PREFIX_TABLE (PREFIX_0F3828
) },
6990 { PREFIX_TABLE (PREFIX_0F3829
) },
6991 { PREFIX_TABLE (PREFIX_0F382A
) },
6992 { PREFIX_TABLE (PREFIX_0F382B
) },
6998 { PREFIX_TABLE (PREFIX_0F3830
) },
6999 { PREFIX_TABLE (PREFIX_0F3831
) },
7000 { PREFIX_TABLE (PREFIX_0F3832
) },
7001 { PREFIX_TABLE (PREFIX_0F3833
) },
7002 { PREFIX_TABLE (PREFIX_0F3834
) },
7003 { PREFIX_TABLE (PREFIX_0F3835
) },
7005 { PREFIX_TABLE (PREFIX_0F3837
) },
7007 { PREFIX_TABLE (PREFIX_0F3838
) },
7008 { PREFIX_TABLE (PREFIX_0F3839
) },
7009 { PREFIX_TABLE (PREFIX_0F383A
) },
7010 { PREFIX_TABLE (PREFIX_0F383B
) },
7011 { PREFIX_TABLE (PREFIX_0F383C
) },
7012 { PREFIX_TABLE (PREFIX_0F383D
) },
7013 { PREFIX_TABLE (PREFIX_0F383E
) },
7014 { PREFIX_TABLE (PREFIX_0F383F
) },
7016 { PREFIX_TABLE (PREFIX_0F3840
) },
7017 { PREFIX_TABLE (PREFIX_0F3841
) },
7088 { PREFIX_TABLE (PREFIX_0F3880
) },
7089 { PREFIX_TABLE (PREFIX_0F3881
) },
7090 { PREFIX_TABLE (PREFIX_0F3882
) },
7169 { PREFIX_TABLE (PREFIX_0F38C8
) },
7170 { PREFIX_TABLE (PREFIX_0F38C9
) },
7171 { PREFIX_TABLE (PREFIX_0F38CA
) },
7172 { PREFIX_TABLE (PREFIX_0F38CB
) },
7173 { PREFIX_TABLE (PREFIX_0F38CC
) },
7174 { PREFIX_TABLE (PREFIX_0F38CD
) },
7176 { PREFIX_TABLE (PREFIX_0F38CF
) },
7190 { PREFIX_TABLE (PREFIX_0F38DB
) },
7191 { PREFIX_TABLE (PREFIX_0F38DC
) },
7192 { PREFIX_TABLE (PREFIX_0F38DD
) },
7193 { PREFIX_TABLE (PREFIX_0F38DE
) },
7194 { PREFIX_TABLE (PREFIX_0F38DF
) },
7214 { PREFIX_TABLE (PREFIX_0F38F0
) },
7215 { PREFIX_TABLE (PREFIX_0F38F1
) },
7219 { PREFIX_TABLE (PREFIX_0F38F5
) },
7220 { PREFIX_TABLE (PREFIX_0F38F6
) },
7223 { PREFIX_TABLE (PREFIX_0F38F8
) },
7224 { PREFIX_TABLE (PREFIX_0F38F9
) },
7232 /* THREE_BYTE_0F3A */
7244 { PREFIX_TABLE (PREFIX_0F3A08
) },
7245 { PREFIX_TABLE (PREFIX_0F3A09
) },
7246 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7247 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7248 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7249 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7250 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7251 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7257 { PREFIX_TABLE (PREFIX_0F3A14
) },
7258 { PREFIX_TABLE (PREFIX_0F3A15
) },
7259 { PREFIX_TABLE (PREFIX_0F3A16
) },
7260 { PREFIX_TABLE (PREFIX_0F3A17
) },
7271 { PREFIX_TABLE (PREFIX_0F3A20
) },
7272 { PREFIX_TABLE (PREFIX_0F3A21
) },
7273 { PREFIX_TABLE (PREFIX_0F3A22
) },
7307 { PREFIX_TABLE (PREFIX_0F3A40
) },
7308 { PREFIX_TABLE (PREFIX_0F3A41
) },
7309 { PREFIX_TABLE (PREFIX_0F3A42
) },
7311 { PREFIX_TABLE (PREFIX_0F3A44
) },
7343 { PREFIX_TABLE (PREFIX_0F3A60
) },
7344 { PREFIX_TABLE (PREFIX_0F3A61
) },
7345 { PREFIX_TABLE (PREFIX_0F3A62
) },
7346 { PREFIX_TABLE (PREFIX_0F3A63
) },
7464 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7466 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7467 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7485 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7525 static const struct dis386 xop_table
[][256] = {
7678 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7679 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7680 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7688 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7689 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7696 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7697 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7698 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7706 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7707 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7711 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7712 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7715 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7733 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7745 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7746 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7747 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7748 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7758 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7759 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7760 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7761 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7794 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7795 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7796 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7797 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7821 { REG_TABLE (REG_XOP_TBM_01
) },
7822 { REG_TABLE (REG_XOP_TBM_02
) },
7840 { REG_TABLE (REG_XOP_LWPCB
) },
7964 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7965 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7966 { "vfrczss", { XM
, EXd
}, 0 },
7967 { "vfrczsd", { XM
, EXq
}, 0 },
7982 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7983 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7984 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7985 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7986 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7987 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7988 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7989 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7991 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7992 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7993 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7994 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8037 { "vphaddbw", { XM
, EXxmm
}, 0 },
8038 { "vphaddbd", { XM
, EXxmm
}, 0 },
8039 { "vphaddbq", { XM
, EXxmm
}, 0 },
8042 { "vphaddwd", { XM
, EXxmm
}, 0 },
8043 { "vphaddwq", { XM
, EXxmm
}, 0 },
8048 { "vphadddq", { XM
, EXxmm
}, 0 },
8055 { "vphaddubw", { XM
, EXxmm
}, 0 },
8056 { "vphaddubd", { XM
, EXxmm
}, 0 },
8057 { "vphaddubq", { XM
, EXxmm
}, 0 },
8060 { "vphadduwd", { XM
, EXxmm
}, 0 },
8061 { "vphadduwq", { XM
, EXxmm
}, 0 },
8066 { "vphaddudq", { XM
, EXxmm
}, 0 },
8073 { "vphsubbw", { XM
, EXxmm
}, 0 },
8074 { "vphsubwd", { XM
, EXxmm
}, 0 },
8075 { "vphsubdq", { XM
, EXxmm
}, 0 },
8129 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8131 { REG_TABLE (REG_XOP_LWP
) },
8401 static const struct dis386 vex_table
[][256] = {
8423 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8424 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8425 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8426 { MOD_TABLE (MOD_VEX_0F13
) },
8427 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
8428 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
8429 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8430 { MOD_TABLE (MOD_VEX_0F17
) },
8450 { "vmovapX", { XM
, EXx
}, 0 },
8451 { "vmovapX", { EXxS
, XM
}, 0 },
8452 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8453 { MOD_TABLE (MOD_VEX_0F2B
) },
8454 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8455 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8456 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8457 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8478 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8479 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8481 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8482 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8483 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8484 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8488 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8489 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8495 { MOD_TABLE (MOD_VEX_0F50
) },
8496 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8497 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8498 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8499 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8500 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8501 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8502 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8504 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8505 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8506 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8507 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8508 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8509 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8510 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8511 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8513 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8514 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8515 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8516 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8517 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8518 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8519 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8520 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8522 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8523 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8524 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8525 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8526 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8527 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8528 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8529 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8531 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8532 { REG_TABLE (REG_VEX_0F71
) },
8533 { REG_TABLE (REG_VEX_0F72
) },
8534 { REG_TABLE (REG_VEX_0F73
) },
8535 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8536 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8537 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8538 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8544 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8545 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8546 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8547 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8567 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8568 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8569 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8570 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8576 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8577 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8600 { REG_TABLE (REG_VEX_0FAE
) },
8623 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8625 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8626 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8627 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8639 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8640 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8641 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8642 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8643 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8644 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8645 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8646 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8648 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8649 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8650 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8651 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8652 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8653 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8654 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8655 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8657 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8658 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8659 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8660 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8661 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8662 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8663 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8664 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8666 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8667 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8668 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8672 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8677 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8686 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8688 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8690 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8743 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8745 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8831 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8832 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8853 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8855 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8858 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8859 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8860 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8861 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8864 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8865 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8867 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8870 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8871 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8872 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8873 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8874 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8882 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8969 { REG_TABLE (REG_VEX_0F38F3
) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
8988 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
8989 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
8991 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
8992 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9010 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9104 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9105 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9107 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9127 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9128 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9129 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9218 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9219 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9237 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9257 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9277 #define NEED_OPCODE_TABLE
9278 #include "i386-dis-evex.h"
9279 #undef NEED_OPCODE_TABLE
9280 static const struct dis386 vex_len_table
[][2] = {
9281 /* VEX_LEN_0F12_P_0_M_0 */
9283 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
9286 /* VEX_LEN_0F12_P_0_M_1 */
9288 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9291 /* VEX_LEN_0F12_P_2 */
9293 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
9296 /* VEX_LEN_0F13_M_0 */
9298 { "vmovlpX", { EXq
, XM
}, 0 },
9301 /* VEX_LEN_0F16_P_0_M_0 */
9303 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
9306 /* VEX_LEN_0F16_P_0_M_1 */
9308 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9311 /* VEX_LEN_0F16_P_2 */
9313 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
9316 /* VEX_LEN_0F17_M_0 */
9318 { "vmovhpX", { EXq
, XM
}, 0 },
9321 /* VEX_LEN_0F2A_P_1 */
9323 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9324 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9327 /* VEX_LEN_0F2A_P_3 */
9329 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9330 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9333 /* VEX_LEN_0F2C_P_1 */
9335 { "vcvttss2si", { Gv
, EXdScalar
}, 0 },
9336 { "vcvttss2si", { Gv
, EXdScalar
}, 0 },
9339 /* VEX_LEN_0F2C_P_3 */
9341 { "vcvttsd2si", { Gv
, EXqScalar
}, 0 },
9342 { "vcvttsd2si", { Gv
, EXqScalar
}, 0 },
9345 /* VEX_LEN_0F2D_P_1 */
9347 { "vcvtss2si", { Gv
, EXdScalar
}, 0 },
9348 { "vcvtss2si", { Gv
, EXdScalar
}, 0 },
9351 /* VEX_LEN_0F2D_P_3 */
9353 { "vcvtsd2si", { Gv
, EXqScalar
}, 0 },
9354 { "vcvtsd2si", { Gv
, EXqScalar
}, 0 },
9357 /* VEX_LEN_0F41_P_0 */
9360 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9362 /* VEX_LEN_0F41_P_2 */
9365 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9367 /* VEX_LEN_0F42_P_0 */
9370 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9372 /* VEX_LEN_0F42_P_2 */
9375 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9377 /* VEX_LEN_0F44_P_0 */
9379 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9381 /* VEX_LEN_0F44_P_2 */
9383 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9385 /* VEX_LEN_0F45_P_0 */
9388 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9390 /* VEX_LEN_0F45_P_2 */
9393 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9395 /* VEX_LEN_0F46_P_0 */
9398 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9400 /* VEX_LEN_0F46_P_2 */
9403 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9405 /* VEX_LEN_0F47_P_0 */
9408 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9410 /* VEX_LEN_0F47_P_2 */
9413 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9415 /* VEX_LEN_0F4A_P_0 */
9418 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9420 /* VEX_LEN_0F4A_P_2 */
9423 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9425 /* VEX_LEN_0F4B_P_0 */
9428 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9430 /* VEX_LEN_0F4B_P_2 */
9433 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9436 /* VEX_LEN_0F6E_P_2 */
9438 { "vmovK", { XMScalar
, Edq
}, 0 },
9441 /* VEX_LEN_0F77_P_1 */
9443 { "vzeroupper", { XX
}, 0 },
9444 { "vzeroall", { XX
}, 0 },
9447 /* VEX_LEN_0F7E_P_1 */
9449 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
9452 /* VEX_LEN_0F7E_P_2 */
9454 { "vmovK", { Edq
, XMScalar
}, 0 },
9457 /* VEX_LEN_0F90_P_0 */
9459 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9462 /* VEX_LEN_0F90_P_2 */
9464 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9467 /* VEX_LEN_0F91_P_0 */
9469 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9472 /* VEX_LEN_0F91_P_2 */
9474 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9477 /* VEX_LEN_0F92_P_0 */
9479 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9482 /* VEX_LEN_0F92_P_2 */
9484 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9487 /* VEX_LEN_0F92_P_3 */
9489 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9492 /* VEX_LEN_0F93_P_0 */
9494 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9497 /* VEX_LEN_0F93_P_2 */
9499 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9502 /* VEX_LEN_0F93_P_3 */
9504 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9507 /* VEX_LEN_0F98_P_0 */
9509 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9512 /* VEX_LEN_0F98_P_2 */
9514 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9517 /* VEX_LEN_0F99_P_0 */
9519 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9522 /* VEX_LEN_0F99_P_2 */
9524 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9527 /* VEX_LEN_0FAE_R_2_M_0 */
9529 { "vldmxcsr", { Md
}, 0 },
9532 /* VEX_LEN_0FAE_R_3_M_0 */
9534 { "vstmxcsr", { Md
}, 0 },
9537 /* VEX_LEN_0FC4_P_2 */
9539 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9542 /* VEX_LEN_0FC5_P_2 */
9544 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9547 /* VEX_LEN_0FD6_P_2 */
9549 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
9552 /* VEX_LEN_0FF7_P_2 */
9554 { "vmaskmovdqu", { XM
, XS
}, 0 },
9557 /* VEX_LEN_0F3816_P_2 */
9560 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9563 /* VEX_LEN_0F3819_P_2 */
9566 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9569 /* VEX_LEN_0F381A_P_2_M_0 */
9572 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9575 /* VEX_LEN_0F3836_P_2 */
9578 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9581 /* VEX_LEN_0F3841_P_2 */
9583 { "vphminposuw", { XM
, EXx
}, 0 },
9586 /* VEX_LEN_0F385A_P_2_M_0 */
9589 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9592 /* VEX_LEN_0F38DB_P_2 */
9594 { "vaesimc", { XM
, EXx
}, 0 },
9597 /* VEX_LEN_0F38F2_P_0 */
9599 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9602 /* VEX_LEN_0F38F3_R_1_P_0 */
9604 { "blsrS", { VexGdq
, Edq
}, 0 },
9607 /* VEX_LEN_0F38F3_R_2_P_0 */
9609 { "blsmskS", { VexGdq
, Edq
}, 0 },
9612 /* VEX_LEN_0F38F3_R_3_P_0 */
9614 { "blsiS", { VexGdq
, Edq
}, 0 },
9617 /* VEX_LEN_0F38F5_P_0 */
9619 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9622 /* VEX_LEN_0F38F5_P_1 */
9624 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9627 /* VEX_LEN_0F38F5_P_3 */
9629 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9632 /* VEX_LEN_0F38F6_P_3 */
9634 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9637 /* VEX_LEN_0F38F7_P_0 */
9639 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9642 /* VEX_LEN_0F38F7_P_1 */
9644 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9647 /* VEX_LEN_0F38F7_P_2 */
9649 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9652 /* VEX_LEN_0F38F7_P_3 */
9654 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9657 /* VEX_LEN_0F3A00_P_2 */
9660 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9663 /* VEX_LEN_0F3A01_P_2 */
9666 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9669 /* VEX_LEN_0F3A06_P_2 */
9672 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9675 /* VEX_LEN_0F3A14_P_2 */
9677 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9680 /* VEX_LEN_0F3A15_P_2 */
9682 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9685 /* VEX_LEN_0F3A16_P_2 */
9687 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9690 /* VEX_LEN_0F3A17_P_2 */
9692 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9695 /* VEX_LEN_0F3A18_P_2 */
9698 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9701 /* VEX_LEN_0F3A19_P_2 */
9704 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9707 /* VEX_LEN_0F3A20_P_2 */
9709 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9712 /* VEX_LEN_0F3A21_P_2 */
9714 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9717 /* VEX_LEN_0F3A22_P_2 */
9719 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9722 /* VEX_LEN_0F3A30_P_2 */
9724 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9727 /* VEX_LEN_0F3A31_P_2 */
9729 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9732 /* VEX_LEN_0F3A32_P_2 */
9734 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9737 /* VEX_LEN_0F3A33_P_2 */
9739 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9742 /* VEX_LEN_0F3A38_P_2 */
9745 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9748 /* VEX_LEN_0F3A39_P_2 */
9751 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9754 /* VEX_LEN_0F3A41_P_2 */
9756 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9759 /* VEX_LEN_0F3A46_P_2 */
9762 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9765 /* VEX_LEN_0F3A60_P_2 */
9767 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9770 /* VEX_LEN_0F3A61_P_2 */
9772 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9775 /* VEX_LEN_0F3A62_P_2 */
9777 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9780 /* VEX_LEN_0F3A63_P_2 */
9782 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9785 /* VEX_LEN_0F3A6A_P_2 */
9787 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9790 /* VEX_LEN_0F3A6B_P_2 */
9792 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9795 /* VEX_LEN_0F3A6E_P_2 */
9797 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9800 /* VEX_LEN_0F3A6F_P_2 */
9802 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9805 /* VEX_LEN_0F3A7A_P_2 */
9807 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9810 /* VEX_LEN_0F3A7B_P_2 */
9812 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9815 /* VEX_LEN_0F3A7E_P_2 */
9817 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9820 /* VEX_LEN_0F3A7F_P_2 */
9822 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9825 /* VEX_LEN_0F3ADF_P_2 */
9827 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9830 /* VEX_LEN_0F3AF0_P_3 */
9832 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9835 /* VEX_LEN_0FXOP_08_CC */
9837 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9840 /* VEX_LEN_0FXOP_08_CD */
9842 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9845 /* VEX_LEN_0FXOP_08_CE */
9847 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9850 /* VEX_LEN_0FXOP_08_CF */
9852 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9855 /* VEX_LEN_0FXOP_08_EC */
9857 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9860 /* VEX_LEN_0FXOP_08_ED */
9862 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9865 /* VEX_LEN_0FXOP_08_EE */
9867 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9870 /* VEX_LEN_0FXOP_08_EF */
9872 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9875 /* VEX_LEN_0FXOP_09_80 */
9877 { "vfrczps", { XM
, EXxmm
}, 0 },
9878 { "vfrczps", { XM
, EXymmq
}, 0 },
9881 /* VEX_LEN_0FXOP_09_81 */
9883 { "vfrczpd", { XM
, EXxmm
}, 0 },
9884 { "vfrczpd", { XM
, EXymmq
}, 0 },
9888 static const struct dis386 evex_len_table
[][3] = {
9889 #define NEED_EVEX_LEN_TABLE
9890 #include "i386-dis-evex.h"
9891 #undef NEED_EVEX_LEN_TABLE
9894 static const struct dis386 vex_w_table
[][2] = {
9896 /* VEX_W_0F41_P_0_LEN_1 */
9897 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9898 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9901 /* VEX_W_0F41_P_2_LEN_1 */
9902 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9903 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9906 /* VEX_W_0F42_P_0_LEN_1 */
9907 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9908 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9911 /* VEX_W_0F42_P_2_LEN_1 */
9912 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9913 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9916 /* VEX_W_0F44_P_0_LEN_0 */
9917 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9918 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9921 /* VEX_W_0F44_P_2_LEN_0 */
9922 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9923 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9926 /* VEX_W_0F45_P_0_LEN_1 */
9927 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9928 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9931 /* VEX_W_0F45_P_2_LEN_1 */
9932 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9933 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9936 /* VEX_W_0F46_P_0_LEN_1 */
9937 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9938 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9941 /* VEX_W_0F46_P_2_LEN_1 */
9942 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9943 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9946 /* VEX_W_0F47_P_0_LEN_1 */
9947 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9948 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9951 /* VEX_W_0F47_P_2_LEN_1 */
9952 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9953 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9956 /* VEX_W_0F4A_P_0_LEN_1 */
9957 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9958 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9961 /* VEX_W_0F4A_P_2_LEN_1 */
9962 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9963 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9966 /* VEX_W_0F4B_P_0_LEN_1 */
9967 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9968 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9971 /* VEX_W_0F4B_P_2_LEN_1 */
9972 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9975 /* VEX_W_0F90_P_0_LEN_0 */
9976 { "kmovw", { MaskG
, MaskE
}, 0 },
9977 { "kmovq", { MaskG
, MaskE
}, 0 },
9980 /* VEX_W_0F90_P_2_LEN_0 */
9981 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9982 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9985 /* VEX_W_0F91_P_0_LEN_0 */
9986 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9987 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9990 /* VEX_W_0F91_P_2_LEN_0 */
9991 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
9992 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
9995 /* VEX_W_0F92_P_0_LEN_0 */
9996 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
9999 /* VEX_W_0F92_P_2_LEN_0 */
10000 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10003 /* VEX_W_0F92_P_3_LEN_0 */
10004 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0
) },
10005 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0
) },
10008 /* VEX_W_0F93_P_0_LEN_0 */
10009 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10012 /* VEX_W_0F93_P_2_LEN_0 */
10013 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10016 /* VEX_W_0F93_P_3_LEN_0 */
10017 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0
) },
10018 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0
) },
10021 /* VEX_W_0F98_P_0_LEN_0 */
10022 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10023 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10026 /* VEX_W_0F98_P_2_LEN_0 */
10027 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10028 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10031 /* VEX_W_0F99_P_0_LEN_0 */
10032 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10033 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10036 /* VEX_W_0F99_P_2_LEN_0 */
10037 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10038 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10041 /* VEX_W_0F380C_P_2 */
10042 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10045 /* VEX_W_0F380D_P_2 */
10046 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10049 /* VEX_W_0F380E_P_2 */
10050 { "vtestps", { XM
, EXx
}, 0 },
10053 /* VEX_W_0F380F_P_2 */
10054 { "vtestpd", { XM
, EXx
}, 0 },
10057 /* VEX_W_0F3816_P_2 */
10058 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10061 /* VEX_W_0F3818_P_2 */
10062 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10065 /* VEX_W_0F3819_P_2 */
10066 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10069 /* VEX_W_0F381A_P_2_M_0 */
10070 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10073 /* VEX_W_0F382C_P_2_M_0 */
10074 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10077 /* VEX_W_0F382D_P_2_M_0 */
10078 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10081 /* VEX_W_0F382E_P_2_M_0 */
10082 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10085 /* VEX_W_0F382F_P_2_M_0 */
10086 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10089 /* VEX_W_0F3836_P_2 */
10090 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10093 /* VEX_W_0F3846_P_2 */
10094 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10097 /* VEX_W_0F3858_P_2 */
10098 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10101 /* VEX_W_0F3859_P_2 */
10102 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10105 /* VEX_W_0F385A_P_2_M_0 */
10106 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10109 /* VEX_W_0F3878_P_2 */
10110 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10113 /* VEX_W_0F3879_P_2 */
10114 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10117 /* VEX_W_0F38CF_P_2 */
10118 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10121 /* VEX_W_0F3A00_P_2 */
10123 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10126 /* VEX_W_0F3A01_P_2 */
10128 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10131 /* VEX_W_0F3A02_P_2 */
10132 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10135 /* VEX_W_0F3A04_P_2 */
10136 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10139 /* VEX_W_0F3A05_P_2 */
10140 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10143 /* VEX_W_0F3A06_P_2 */
10144 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10147 /* VEX_W_0F3A18_P_2 */
10148 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10151 /* VEX_W_0F3A19_P_2 */
10152 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10155 /* VEX_W_0F3A30_P_2_LEN_0 */
10156 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10157 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10160 /* VEX_W_0F3A31_P_2_LEN_0 */
10161 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10162 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10165 /* VEX_W_0F3A32_P_2_LEN_0 */
10166 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10167 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10170 /* VEX_W_0F3A33_P_2_LEN_0 */
10171 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10172 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10175 /* VEX_W_0F3A38_P_2 */
10176 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10179 /* VEX_W_0F3A39_P_2 */
10180 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10183 /* VEX_W_0F3A46_P_2 */
10184 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10187 /* VEX_W_0F3A48_P_2 */
10188 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10189 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10192 /* VEX_W_0F3A49_P_2 */
10193 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10194 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10197 /* VEX_W_0F3A4A_P_2 */
10198 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10201 /* VEX_W_0F3A4B_P_2 */
10202 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10205 /* VEX_W_0F3A4C_P_2 */
10206 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10209 /* VEX_W_0F3ACE_P_2 */
10211 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10214 /* VEX_W_0F3ACF_P_2 */
10216 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10218 #define NEED_VEX_W_TABLE
10219 #include "i386-dis-evex.h"
10220 #undef NEED_VEX_W_TABLE
10223 static const struct dis386 mod_table
[][2] = {
10226 { "leaS", { Gv
, M
}, 0 },
10231 { RM_TABLE (RM_C6_REG_7
) },
10236 { RM_TABLE (RM_C7_REG_7
) },
10240 { "Jcall^", { indirEp
}, 0 },
10244 { "Jjmp^", { indirEp
}, 0 },
10247 /* MOD_0F01_REG_0 */
10248 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10249 { RM_TABLE (RM_0F01_REG_0
) },
10252 /* MOD_0F01_REG_1 */
10253 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10254 { RM_TABLE (RM_0F01_REG_1
) },
10257 /* MOD_0F01_REG_2 */
10258 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10259 { RM_TABLE (RM_0F01_REG_2
) },
10262 /* MOD_0F01_REG_3 */
10263 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10264 { RM_TABLE (RM_0F01_REG_3
) },
10267 /* MOD_0F01_REG_5 */
10268 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5
) },
10269 { RM_TABLE (RM_0F01_REG_5
) },
10272 /* MOD_0F01_REG_7 */
10273 { "invlpg", { Mb
}, 0 },
10274 { RM_TABLE (RM_0F01_REG_7
) },
10277 /* MOD_0F12_PREFIX_0 */
10278 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
10279 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
10283 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10286 /* MOD_0F16_PREFIX_0 */
10287 { "movhps", { XM
, EXq
}, 0 },
10288 { "movlhps", { XM
, EXq
}, 0 },
10292 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10295 /* MOD_0F18_REG_0 */
10296 { "prefetchnta", { Mb
}, 0 },
10299 /* MOD_0F18_REG_1 */
10300 { "prefetcht0", { Mb
}, 0 },
10303 /* MOD_0F18_REG_2 */
10304 { "prefetcht1", { Mb
}, 0 },
10307 /* MOD_0F18_REG_3 */
10308 { "prefetcht2", { Mb
}, 0 },
10311 /* MOD_0F18_REG_4 */
10312 { "nop/reserved", { Mb
}, 0 },
10315 /* MOD_0F18_REG_5 */
10316 { "nop/reserved", { Mb
}, 0 },
10319 /* MOD_0F18_REG_6 */
10320 { "nop/reserved", { Mb
}, 0 },
10323 /* MOD_0F18_REG_7 */
10324 { "nop/reserved", { Mb
}, 0 },
10327 /* MOD_0F1A_PREFIX_0 */
10328 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10329 { "nopQ", { Ev
}, 0 },
10332 /* MOD_0F1B_PREFIX_0 */
10333 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10334 { "nopQ", { Ev
}, 0 },
10337 /* MOD_0F1B_PREFIX_1 */
10338 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10339 { "nopQ", { Ev
}, 0 },
10342 /* MOD_0F1C_PREFIX_0 */
10343 { REG_TABLE (REG_0F1C_MOD_0
) },
10344 { "nopQ", { Ev
}, 0 },
10347 /* MOD_0F1E_PREFIX_1 */
10348 { "nopQ", { Ev
}, 0 },
10349 { REG_TABLE (REG_0F1E_MOD_3
) },
10354 { "movL", { Rd
, Td
}, 0 },
10359 { "movL", { Td
, Rd
}, 0 },
10362 /* MOD_0F2B_PREFIX_0 */
10363 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10366 /* MOD_0F2B_PREFIX_1 */
10367 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10370 /* MOD_0F2B_PREFIX_2 */
10371 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10374 /* MOD_0F2B_PREFIX_3 */
10375 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10380 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10383 /* MOD_0F71_REG_2 */
10385 { "psrlw", { MS
, Ib
}, 0 },
10388 /* MOD_0F71_REG_4 */
10390 { "psraw", { MS
, Ib
}, 0 },
10393 /* MOD_0F71_REG_6 */
10395 { "psllw", { MS
, Ib
}, 0 },
10398 /* MOD_0F72_REG_2 */
10400 { "psrld", { MS
, Ib
}, 0 },
10403 /* MOD_0F72_REG_4 */
10405 { "psrad", { MS
, Ib
}, 0 },
10408 /* MOD_0F72_REG_6 */
10410 { "pslld", { MS
, Ib
}, 0 },
10413 /* MOD_0F73_REG_2 */
10415 { "psrlq", { MS
, Ib
}, 0 },
10418 /* MOD_0F73_REG_3 */
10420 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10423 /* MOD_0F73_REG_6 */
10425 { "psllq", { MS
, Ib
}, 0 },
10428 /* MOD_0F73_REG_7 */
10430 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10433 /* MOD_0FAE_REG_0 */
10434 { "fxsave", { FXSAVE
}, 0 },
10435 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
10438 /* MOD_0FAE_REG_1 */
10439 { "fxrstor", { FXSAVE
}, 0 },
10440 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
10443 /* MOD_0FAE_REG_2 */
10444 { "ldmxcsr", { Md
}, 0 },
10445 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
10448 /* MOD_0FAE_REG_3 */
10449 { "stmxcsr", { Md
}, 0 },
10450 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
10453 /* MOD_0FAE_REG_4 */
10454 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4
) },
10455 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4
) },
10458 /* MOD_0FAE_REG_5 */
10459 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5
) },
10460 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5
) },
10463 /* MOD_0FAE_REG_6 */
10464 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6
) },
10465 { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6
) },
10468 /* MOD_0FAE_REG_7 */
10469 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
10470 { RM_TABLE (RM_0FAE_REG_7
) },
10474 { "lssS", { Gv
, Mp
}, 0 },
10478 { "lfsS", { Gv
, Mp
}, 0 },
10482 { "lgsS", { Gv
, Mp
}, 0 },
10486 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
10489 /* MOD_0FC7_REG_3 */
10490 { "xrstors", { FXSAVE
}, 0 },
10493 /* MOD_0FC7_REG_4 */
10494 { "xsavec", { FXSAVE
}, 0 },
10497 /* MOD_0FC7_REG_5 */
10498 { "xsaves", { FXSAVE
}, 0 },
10501 /* MOD_0FC7_REG_6 */
10502 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
10503 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
10506 /* MOD_0FC7_REG_7 */
10507 { "vmptrst", { Mq
}, 0 },
10508 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
10513 { "pmovmskb", { Gdq
, MS
}, 0 },
10516 /* MOD_0FE7_PREFIX_2 */
10517 { "movntdq", { Mx
, XM
}, 0 },
10520 /* MOD_0FF0_PREFIX_3 */
10521 { "lddqu", { XM
, M
}, 0 },
10524 /* MOD_0F382A_PREFIX_2 */
10525 { "movntdqa", { XM
, Mx
}, 0 },
10528 /* MOD_0F38F5_PREFIX_2 */
10529 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10532 /* MOD_0F38F6_PREFIX_0 */
10533 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10536 /* MOD_0F38F8_PREFIX_2 */
10537 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10540 /* MOD_0F38F9_PREFIX_0 */
10541 { "movdiri", { Em
, Gv
}, PREFIX_OPCODE
},
10545 { "bound{S|}", { Gv
, Ma
}, 0 },
10546 { EVEX_TABLE (EVEX_0F
) },
10550 { "lesS", { Gv
, Mp
}, 0 },
10551 { VEX_C4_TABLE (VEX_0F
) },
10555 { "ldsS", { Gv
, Mp
}, 0 },
10556 { VEX_C5_TABLE (VEX_0F
) },
10559 /* MOD_VEX_0F12_PREFIX_0 */
10560 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10561 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10565 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10568 /* MOD_VEX_0F16_PREFIX_0 */
10569 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10570 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10574 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10578 { "vmovntpX", { Mx
, XM
}, 0 },
10581 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10583 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10586 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10588 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10591 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10593 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10596 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10598 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10601 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10603 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10606 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10608 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10611 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10613 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10616 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10618 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10621 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10623 { "knotw", { MaskG
, MaskR
}, 0 },
10626 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10628 { "knotq", { MaskG
, MaskR
}, 0 },
10631 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10633 { "knotb", { MaskG
, MaskR
}, 0 },
10636 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10638 { "knotd", { MaskG
, MaskR
}, 0 },
10641 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10643 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10646 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10648 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10651 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10653 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10656 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10658 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10661 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10663 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10666 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10668 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10671 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10673 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10676 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10678 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10681 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10683 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10686 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10688 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10691 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10693 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10696 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10698 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10701 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10703 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10706 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10708 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10711 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10713 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10716 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10718 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10721 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10723 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10726 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10728 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10731 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10733 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10738 { "vmovmskpX", { Gdq
, XS
}, 0 },
10741 /* MOD_VEX_0F71_REG_2 */
10743 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10746 /* MOD_VEX_0F71_REG_4 */
10748 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10751 /* MOD_VEX_0F71_REG_6 */
10753 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10756 /* MOD_VEX_0F72_REG_2 */
10758 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10761 /* MOD_VEX_0F72_REG_4 */
10763 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10766 /* MOD_VEX_0F72_REG_6 */
10768 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10771 /* MOD_VEX_0F73_REG_2 */
10773 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10776 /* MOD_VEX_0F73_REG_3 */
10778 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10781 /* MOD_VEX_0F73_REG_6 */
10783 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10786 /* MOD_VEX_0F73_REG_7 */
10788 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10791 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10792 { "kmovw", { Ew
, MaskG
}, 0 },
10796 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10797 { "kmovq", { Eq
, MaskG
}, 0 },
10801 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10802 { "kmovb", { Eb
, MaskG
}, 0 },
10806 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10807 { "kmovd", { Ed
, MaskG
}, 0 },
10811 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10813 { "kmovw", { MaskG
, Rdq
}, 0 },
10816 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10818 { "kmovb", { MaskG
, Rdq
}, 0 },
10821 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
10823 { "kmovd", { MaskG
, Rdq
}, 0 },
10826 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
10828 { "kmovq", { MaskG
, Rdq
}, 0 },
10831 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10833 { "kmovw", { Gdq
, MaskR
}, 0 },
10836 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10838 { "kmovb", { Gdq
, MaskR
}, 0 },
10841 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
10843 { "kmovd", { Gdq
, MaskR
}, 0 },
10846 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
10848 { "kmovq", { Gdq
, MaskR
}, 0 },
10851 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10853 { "kortestw", { MaskG
, MaskR
}, 0 },
10856 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10858 { "kortestq", { MaskG
, MaskR
}, 0 },
10861 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10863 { "kortestb", { MaskG
, MaskR
}, 0 },
10866 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10868 { "kortestd", { MaskG
, MaskR
}, 0 },
10871 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10873 { "ktestw", { MaskG
, MaskR
}, 0 },
10876 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10878 { "ktestq", { MaskG
, MaskR
}, 0 },
10881 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10883 { "ktestb", { MaskG
, MaskR
}, 0 },
10886 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10888 { "ktestd", { MaskG
, MaskR
}, 0 },
10891 /* MOD_VEX_0FAE_REG_2 */
10892 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10895 /* MOD_VEX_0FAE_REG_3 */
10896 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10899 /* MOD_VEX_0FD7_PREFIX_2 */
10901 { "vpmovmskb", { Gdq
, XS
}, 0 },
10904 /* MOD_VEX_0FE7_PREFIX_2 */
10905 { "vmovntdq", { Mx
, XM
}, 0 },
10908 /* MOD_VEX_0FF0_PREFIX_3 */
10909 { "vlddqu", { XM
, M
}, 0 },
10912 /* MOD_VEX_0F381A_PREFIX_2 */
10913 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10916 /* MOD_VEX_0F382A_PREFIX_2 */
10917 { "vmovntdqa", { XM
, Mx
}, 0 },
10920 /* MOD_VEX_0F382C_PREFIX_2 */
10921 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10924 /* MOD_VEX_0F382D_PREFIX_2 */
10925 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10928 /* MOD_VEX_0F382E_PREFIX_2 */
10929 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10932 /* MOD_VEX_0F382F_PREFIX_2 */
10933 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10936 /* MOD_VEX_0F385A_PREFIX_2 */
10937 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10940 /* MOD_VEX_0F388C_PREFIX_2 */
10941 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10944 /* MOD_VEX_0F388E_PREFIX_2 */
10945 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10948 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10950 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10953 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10955 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10958 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10960 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10963 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10965 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10968 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10970 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10973 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10975 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10978 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10980 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10983 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10985 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10987 #define NEED_MOD_TABLE
10988 #include "i386-dis-evex.h"
10989 #undef NEED_MOD_TABLE
10992 static const struct dis386 rm_table
[][8] = {
10995 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10999 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
11002 /* RM_0F01_REG_0 */
11003 { "enclv", { Skip_MODRM
}, 0 },
11004 { "vmcall", { Skip_MODRM
}, 0 },
11005 { "vmlaunch", { Skip_MODRM
}, 0 },
11006 { "vmresume", { Skip_MODRM
}, 0 },
11007 { "vmxoff", { Skip_MODRM
}, 0 },
11008 { "pconfig", { Skip_MODRM
}, 0 },
11011 /* RM_0F01_REG_1 */
11012 { "monitor", { { OP_Monitor
, 0 } }, 0 },
11013 { "mwait", { { OP_Mwait
, 0 } }, 0 },
11014 { "clac", { Skip_MODRM
}, 0 },
11015 { "stac", { Skip_MODRM
}, 0 },
11019 { "encls", { Skip_MODRM
}, 0 },
11022 /* RM_0F01_REG_2 */
11023 { "xgetbv", { Skip_MODRM
}, 0 },
11024 { "xsetbv", { Skip_MODRM
}, 0 },
11027 { "vmfunc", { Skip_MODRM
}, 0 },
11028 { "xend", { Skip_MODRM
}, 0 },
11029 { "xtest", { Skip_MODRM
}, 0 },
11030 { "enclu", { Skip_MODRM
}, 0 },
11033 /* RM_0F01_REG_3 */
11034 { "vmrun", { Skip_MODRM
}, 0 },
11035 { "vmmcall", { Skip_MODRM
}, 0 },
11036 { "vmload", { Skip_MODRM
}, 0 },
11037 { "vmsave", { Skip_MODRM
}, 0 },
11038 { "stgi", { Skip_MODRM
}, 0 },
11039 { "clgi", { Skip_MODRM
}, 0 },
11040 { "skinit", { Skip_MODRM
}, 0 },
11041 { "invlpga", { Skip_MODRM
}, 0 },
11044 /* RM_0F01_REG_5 */
11045 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0
) },
11047 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2
) },
11051 { "rdpkru", { Skip_MODRM
}, 0 },
11052 { "wrpkru", { Skip_MODRM
}, 0 },
11055 /* RM_0F01_REG_7 */
11056 { "swapgs", { Skip_MODRM
}, 0 },
11057 { "rdtscp", { Skip_MODRM
}, 0 },
11058 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
11059 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
11060 { "clzero", { Skip_MODRM
}, 0 },
11063 /* RM_0F1E_MOD_3_REG_7 */
11064 { "nopQ", { Ev
}, 0 },
11065 { "nopQ", { Ev
}, 0 },
11066 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11067 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11068 { "nopQ", { Ev
}, 0 },
11069 { "nopQ", { Ev
}, 0 },
11070 { "nopQ", { Ev
}, 0 },
11071 { "nopQ", { Ev
}, 0 },
11074 /* RM_0FAE_REG_6 */
11075 { "mfence", { Skip_MODRM
}, 0 },
11078 /* RM_0FAE_REG_7 */
11079 { "sfence", { Skip_MODRM
}, 0 },
11084 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11086 /* We use the high bit to indicate different name for the same
11088 #define REP_PREFIX (0xf3 | 0x100)
11089 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11090 #define XRELEASE_PREFIX (0xf3 | 0x400)
11091 #define BND_PREFIX (0xf2 | 0x400)
11092 #define NOTRACK_PREFIX (0x3e | 0x100)
11097 int newrex
, i
, length
;
11103 last_lock_prefix
= -1;
11104 last_repz_prefix
= -1;
11105 last_repnz_prefix
= -1;
11106 last_data_prefix
= -1;
11107 last_addr_prefix
= -1;
11108 last_rex_prefix
= -1;
11109 last_seg_prefix
= -1;
11111 active_seg_prefix
= 0;
11112 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11113 all_prefixes
[i
] = 0;
11116 /* The maximum instruction length is 15bytes. */
11117 while (length
< MAX_CODE_LENGTH
- 1)
11119 FETCH_DATA (the_info
, codep
+ 1);
11123 /* REX prefixes family. */
11140 if (address_mode
== mode_64bit
)
11144 last_rex_prefix
= i
;
11147 prefixes
|= PREFIX_REPZ
;
11148 last_repz_prefix
= i
;
11151 prefixes
|= PREFIX_REPNZ
;
11152 last_repnz_prefix
= i
;
11155 prefixes
|= PREFIX_LOCK
;
11156 last_lock_prefix
= i
;
11159 prefixes
|= PREFIX_CS
;
11160 last_seg_prefix
= i
;
11161 active_seg_prefix
= PREFIX_CS
;
11164 prefixes
|= PREFIX_SS
;
11165 last_seg_prefix
= i
;
11166 active_seg_prefix
= PREFIX_SS
;
11169 prefixes
|= PREFIX_DS
;
11170 last_seg_prefix
= i
;
11171 active_seg_prefix
= PREFIX_DS
;
11174 prefixes
|= PREFIX_ES
;
11175 last_seg_prefix
= i
;
11176 active_seg_prefix
= PREFIX_ES
;
11179 prefixes
|= PREFIX_FS
;
11180 last_seg_prefix
= i
;
11181 active_seg_prefix
= PREFIX_FS
;
11184 prefixes
|= PREFIX_GS
;
11185 last_seg_prefix
= i
;
11186 active_seg_prefix
= PREFIX_GS
;
11189 prefixes
|= PREFIX_DATA
;
11190 last_data_prefix
= i
;
11193 prefixes
|= PREFIX_ADDR
;
11194 last_addr_prefix
= i
;
11197 /* fwait is really an instruction. If there are prefixes
11198 before the fwait, they belong to the fwait, *not* to the
11199 following instruction. */
11201 if (prefixes
|| rex
)
11203 prefixes
|= PREFIX_FWAIT
;
11205 /* This ensures that the previous REX prefixes are noticed
11206 as unused prefixes, as in the return case below. */
11210 prefixes
= PREFIX_FWAIT
;
11215 /* Rex is ignored when followed by another prefix. */
11221 if (*codep
!= FWAIT_OPCODE
)
11222 all_prefixes
[i
++] = *codep
;
11230 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11233 static const char *
11234 prefix_name (int pref
, int sizeflag
)
11236 static const char *rexes
[16] =
11239 "rex.B", /* 0x41 */
11240 "rex.X", /* 0x42 */
11241 "rex.XB", /* 0x43 */
11242 "rex.R", /* 0x44 */
11243 "rex.RB", /* 0x45 */
11244 "rex.RX", /* 0x46 */
11245 "rex.RXB", /* 0x47 */
11246 "rex.W", /* 0x48 */
11247 "rex.WB", /* 0x49 */
11248 "rex.WX", /* 0x4a */
11249 "rex.WXB", /* 0x4b */
11250 "rex.WR", /* 0x4c */
11251 "rex.WRB", /* 0x4d */
11252 "rex.WRX", /* 0x4e */
11253 "rex.WRXB", /* 0x4f */
11258 /* REX prefixes family. */
11275 return rexes
[pref
- 0x40];
11295 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11297 if (address_mode
== mode_64bit
)
11298 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11300 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11305 case XACQUIRE_PREFIX
:
11307 case XRELEASE_PREFIX
:
11311 case NOTRACK_PREFIX
:
11318 static char op_out
[MAX_OPERANDS
][100];
11319 static int op_ad
, op_index
[MAX_OPERANDS
];
11320 static int two_source_ops
;
11321 static bfd_vma op_address
[MAX_OPERANDS
];
11322 static bfd_vma op_riprel
[MAX_OPERANDS
];
11323 static bfd_vma start_pc
;
11326 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11327 * (see topic "Redundant prefixes" in the "Differences from 8086"
11328 * section of the "Virtual 8086 Mode" chapter.)
11329 * 'pc' should be the address of this instruction, it will
11330 * be used to print the target address if this is a relative jump or call
11331 * The function returns the length of this instruction in bytes.
11334 static char intel_syntax
;
11335 static char intel_mnemonic
= !SYSV386_COMPAT
;
11336 static char open_char
;
11337 static char close_char
;
11338 static char separator_char
;
11339 static char scale_char
;
11347 static enum x86_64_isa isa64
;
11349 /* Here for backwards compatibility. When gdb stops using
11350 print_insn_i386_att and print_insn_i386_intel these functions can
11351 disappear, and print_insn_i386 be merged into print_insn. */
11353 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11357 return print_insn (pc
, info
);
11361 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11365 return print_insn (pc
, info
);
11369 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11373 return print_insn (pc
, info
);
11377 print_i386_disassembler_options (FILE *stream
)
11379 fprintf (stream
, _("\n\
11380 The following i386/x86-64 specific disassembler options are supported for use\n\
11381 with the -M switch (multiple options should be separated by commas):\n"));
11383 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11384 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11385 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11386 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11387 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11388 fprintf (stream
, _(" att-mnemonic\n"
11389 " Display instruction in AT&T mnemonic\n"));
11390 fprintf (stream
, _(" intel-mnemonic\n"
11391 " Display instruction in Intel mnemonic\n"));
11392 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11393 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11394 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11395 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11396 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11397 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11398 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11399 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11403 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11405 /* Get a pointer to struct dis386 with a valid name. */
11407 static const struct dis386
*
11408 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11410 int vindex
, vex_table_index
;
11412 if (dp
->name
!= NULL
)
11415 switch (dp
->op
[0].bytemode
)
11417 case USE_REG_TABLE
:
11418 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11421 case USE_MOD_TABLE
:
11422 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11423 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11427 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11430 case USE_PREFIX_TABLE
:
11433 /* The prefix in VEX is implicit. */
11434 switch (vex
.prefix
)
11439 case REPE_PREFIX_OPCODE
:
11442 case DATA_PREFIX_OPCODE
:
11445 case REPNE_PREFIX_OPCODE
:
11455 int last_prefix
= -1;
11458 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11459 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11461 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11463 if (last_repz_prefix
> last_repnz_prefix
)
11466 prefix
= PREFIX_REPZ
;
11467 last_prefix
= last_repz_prefix
;
11472 prefix
= PREFIX_REPNZ
;
11473 last_prefix
= last_repnz_prefix
;
11476 /* Check if prefix should be ignored. */
11477 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11478 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11483 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11486 prefix
= PREFIX_DATA
;
11487 last_prefix
= last_data_prefix
;
11492 used_prefixes
|= prefix
;
11493 all_prefixes
[last_prefix
] = 0;
11496 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11499 case USE_X86_64_TABLE
:
11500 vindex
= address_mode
== mode_64bit
? 1 : 0;
11501 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11504 case USE_3BYTE_TABLE
:
11505 FETCH_DATA (info
, codep
+ 2);
11507 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11509 modrm
.mod
= (*codep
>> 6) & 3;
11510 modrm
.reg
= (*codep
>> 3) & 7;
11511 modrm
.rm
= *codep
& 7;
11514 case USE_VEX_LEN_TABLE
:
11518 switch (vex
.length
)
11531 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11534 case USE_EVEX_LEN_TABLE
:
11538 switch (vex
.length
)
11554 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11557 case USE_XOP_8F_TABLE
:
11558 FETCH_DATA (info
, codep
+ 3);
11559 /* All bits in the REX prefix are ignored. */
11561 rex
= ~(*codep
>> 5) & 0x7;
11563 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11564 switch ((*codep
& 0x1f))
11570 vex_table_index
= XOP_08
;
11573 vex_table_index
= XOP_09
;
11576 vex_table_index
= XOP_0A
;
11580 vex
.w
= *codep
& 0x80;
11581 if (vex
.w
&& address_mode
== mode_64bit
)
11584 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11585 if (address_mode
!= mode_64bit
)
11587 /* In 16/32-bit mode REX_B is silently ignored. */
11591 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11592 switch ((*codep
& 0x3))
11597 vex
.prefix
= DATA_PREFIX_OPCODE
;
11600 vex
.prefix
= REPE_PREFIX_OPCODE
;
11603 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11610 dp
= &xop_table
[vex_table_index
][vindex
];
11613 FETCH_DATA (info
, codep
+ 1);
11614 modrm
.mod
= (*codep
>> 6) & 3;
11615 modrm
.reg
= (*codep
>> 3) & 7;
11616 modrm
.rm
= *codep
& 7;
11619 case USE_VEX_C4_TABLE
:
11621 FETCH_DATA (info
, codep
+ 3);
11622 /* All bits in the REX prefix are ignored. */
11624 rex
= ~(*codep
>> 5) & 0x7;
11625 switch ((*codep
& 0x1f))
11631 vex_table_index
= VEX_0F
;
11634 vex_table_index
= VEX_0F38
;
11637 vex_table_index
= VEX_0F3A
;
11641 vex
.w
= *codep
& 0x80;
11642 if (address_mode
== mode_64bit
)
11649 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11650 is ignored, other REX bits are 0 and the highest bit in
11651 VEX.vvvv is also ignored (but we mustn't clear it here). */
11654 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11655 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11656 switch ((*codep
& 0x3))
11661 vex
.prefix
= DATA_PREFIX_OPCODE
;
11664 vex
.prefix
= REPE_PREFIX_OPCODE
;
11667 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11674 dp
= &vex_table
[vex_table_index
][vindex
];
11676 /* There is no MODRM byte for VEX0F 77. */
11677 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11679 FETCH_DATA (info
, codep
+ 1);
11680 modrm
.mod
= (*codep
>> 6) & 3;
11681 modrm
.reg
= (*codep
>> 3) & 7;
11682 modrm
.rm
= *codep
& 7;
11686 case USE_VEX_C5_TABLE
:
11688 FETCH_DATA (info
, codep
+ 2);
11689 /* All bits in the REX prefix are ignored. */
11691 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11693 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11695 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11696 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11697 switch ((*codep
& 0x3))
11702 vex
.prefix
= DATA_PREFIX_OPCODE
;
11705 vex
.prefix
= REPE_PREFIX_OPCODE
;
11708 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11715 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11717 /* There is no MODRM byte for VEX 77. */
11718 if (vindex
!= 0x77)
11720 FETCH_DATA (info
, codep
+ 1);
11721 modrm
.mod
= (*codep
>> 6) & 3;
11722 modrm
.reg
= (*codep
>> 3) & 7;
11723 modrm
.rm
= *codep
& 7;
11727 case USE_VEX_W_TABLE
:
11731 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11734 case USE_EVEX_TABLE
:
11735 two_source_ops
= 0;
11738 FETCH_DATA (info
, codep
+ 4);
11739 /* All bits in the REX prefix are ignored. */
11741 /* The first byte after 0x62. */
11742 rex
= ~(*codep
>> 5) & 0x7;
11743 vex
.r
= *codep
& 0x10;
11744 switch ((*codep
& 0xf))
11747 return &bad_opcode
;
11749 vex_table_index
= EVEX_0F
;
11752 vex_table_index
= EVEX_0F38
;
11755 vex_table_index
= EVEX_0F3A
;
11759 /* The second byte after 0x62. */
11761 vex
.w
= *codep
& 0x80;
11762 if (vex
.w
&& address_mode
== mode_64bit
)
11765 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11768 if (!(*codep
& 0x4))
11769 return &bad_opcode
;
11771 switch ((*codep
& 0x3))
11776 vex
.prefix
= DATA_PREFIX_OPCODE
;
11779 vex
.prefix
= REPE_PREFIX_OPCODE
;
11782 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11786 /* The third byte after 0x62. */
11789 /* Remember the static rounding bits. */
11790 vex
.ll
= (*codep
>> 5) & 3;
11791 vex
.b
= (*codep
& 0x10) != 0;
11793 vex
.v
= *codep
& 0x8;
11794 vex
.mask_register_specifier
= *codep
& 0x7;
11795 vex
.zeroing
= *codep
& 0x80;
11797 if (address_mode
!= mode_64bit
)
11799 /* In 16/32-bit mode silently ignore following bits. */
11809 dp
= &evex_table
[vex_table_index
][vindex
];
11811 FETCH_DATA (info
, codep
+ 1);
11812 modrm
.mod
= (*codep
>> 6) & 3;
11813 modrm
.reg
= (*codep
>> 3) & 7;
11814 modrm
.rm
= *codep
& 7;
11816 /* Set vector length. */
11817 if (modrm
.mod
== 3 && vex
.b
)
11833 return &bad_opcode
;
11846 if (dp
->name
!= NULL
)
11849 return get_valid_dis386 (dp
, info
);
11853 get_sib (disassemble_info
*info
, int sizeflag
)
11855 /* If modrm.mod == 3, operand must be register. */
11857 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11861 FETCH_DATA (info
, codep
+ 2);
11862 sib
.index
= (codep
[1] >> 3) & 7;
11863 sib
.scale
= (codep
[1] >> 6) & 3;
11864 sib
.base
= codep
[1] & 7;
11869 print_insn (bfd_vma pc
, disassemble_info
*info
)
11871 const struct dis386
*dp
;
11873 char *op_txt
[MAX_OPERANDS
];
11875 int sizeflag
, orig_sizeflag
;
11877 struct dis_private priv
;
11880 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11881 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11882 address_mode
= mode_32bit
;
11883 else if (info
->mach
== bfd_mach_i386_i8086
)
11885 address_mode
= mode_16bit
;
11886 priv
.orig_sizeflag
= 0;
11889 address_mode
= mode_64bit
;
11891 if (intel_syntax
== (char) -1)
11892 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11894 for (p
= info
->disassembler_options
; p
!= NULL
; )
11896 if (CONST_STRNEQ (p
, "amd64"))
11898 else if (CONST_STRNEQ (p
, "intel64"))
11900 else if (CONST_STRNEQ (p
, "x86-64"))
11902 address_mode
= mode_64bit
;
11903 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11905 else if (CONST_STRNEQ (p
, "i386"))
11907 address_mode
= mode_32bit
;
11908 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11910 else if (CONST_STRNEQ (p
, "i8086"))
11912 address_mode
= mode_16bit
;
11913 priv
.orig_sizeflag
= 0;
11915 else if (CONST_STRNEQ (p
, "intel"))
11918 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11919 intel_mnemonic
= 1;
11921 else if (CONST_STRNEQ (p
, "att"))
11924 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11925 intel_mnemonic
= 0;
11927 else if (CONST_STRNEQ (p
, "addr"))
11929 if (address_mode
== mode_64bit
)
11931 if (p
[4] == '3' && p
[5] == '2')
11932 priv
.orig_sizeflag
&= ~AFLAG
;
11933 else if (p
[4] == '6' && p
[5] == '4')
11934 priv
.orig_sizeflag
|= AFLAG
;
11938 if (p
[4] == '1' && p
[5] == '6')
11939 priv
.orig_sizeflag
&= ~AFLAG
;
11940 else if (p
[4] == '3' && p
[5] == '2')
11941 priv
.orig_sizeflag
|= AFLAG
;
11944 else if (CONST_STRNEQ (p
, "data"))
11946 if (p
[4] == '1' && p
[5] == '6')
11947 priv
.orig_sizeflag
&= ~DFLAG
;
11948 else if (p
[4] == '3' && p
[5] == '2')
11949 priv
.orig_sizeflag
|= DFLAG
;
11951 else if (CONST_STRNEQ (p
, "suffix"))
11952 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11954 p
= strchr (p
, ',');
11959 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11961 (*info
->fprintf_func
) (info
->stream
,
11962 _("64-bit address is disabled"));
11968 names64
= intel_names64
;
11969 names32
= intel_names32
;
11970 names16
= intel_names16
;
11971 names8
= intel_names8
;
11972 names8rex
= intel_names8rex
;
11973 names_seg
= intel_names_seg
;
11974 names_mm
= intel_names_mm
;
11975 names_bnd
= intel_names_bnd
;
11976 names_xmm
= intel_names_xmm
;
11977 names_ymm
= intel_names_ymm
;
11978 names_zmm
= intel_names_zmm
;
11979 index64
= intel_index64
;
11980 index32
= intel_index32
;
11981 names_mask
= intel_names_mask
;
11982 index16
= intel_index16
;
11985 separator_char
= '+';
11990 names64
= att_names64
;
11991 names32
= att_names32
;
11992 names16
= att_names16
;
11993 names8
= att_names8
;
11994 names8rex
= att_names8rex
;
11995 names_seg
= att_names_seg
;
11996 names_mm
= att_names_mm
;
11997 names_bnd
= att_names_bnd
;
11998 names_xmm
= att_names_xmm
;
11999 names_ymm
= att_names_ymm
;
12000 names_zmm
= att_names_zmm
;
12001 index64
= att_index64
;
12002 index32
= att_index32
;
12003 names_mask
= att_names_mask
;
12004 index16
= att_index16
;
12007 separator_char
= ',';
12011 /* The output looks better if we put 7 bytes on a line, since that
12012 puts most long word instructions on a single line. Use 8 bytes
12014 if ((info
->mach
& bfd_mach_l1om
) != 0)
12015 info
->bytes_per_line
= 8;
12017 info
->bytes_per_line
= 7;
12019 info
->private_data
= &priv
;
12020 priv
.max_fetched
= priv
.the_buffer
;
12021 priv
.insn_start
= pc
;
12024 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12032 start_codep
= priv
.the_buffer
;
12033 codep
= priv
.the_buffer
;
12035 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12039 /* Getting here means we tried for data but didn't get it. That
12040 means we have an incomplete instruction of some sort. Just
12041 print the first byte as a prefix or a .byte pseudo-op. */
12042 if (codep
> priv
.the_buffer
)
12044 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12046 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12049 /* Just print the first byte as a .byte instruction. */
12050 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12051 (unsigned int) priv
.the_buffer
[0]);
12061 sizeflag
= priv
.orig_sizeflag
;
12063 if (!ckprefix () || rex_used
)
12065 /* Too many prefixes or unused REX prefixes. */
12067 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12069 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12071 prefix_name (all_prefixes
[i
], sizeflag
));
12075 insn_codep
= codep
;
12077 FETCH_DATA (info
, codep
+ 1);
12078 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12080 if (((prefixes
& PREFIX_FWAIT
)
12081 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12083 /* Handle prefixes before fwait. */
12084 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12086 (*info
->fprintf_func
) (info
->stream
, "%s ",
12087 prefix_name (all_prefixes
[i
], sizeflag
));
12088 (*info
->fprintf_func
) (info
->stream
, "fwait");
12092 if (*codep
== 0x0f)
12094 unsigned char threebyte
;
12097 FETCH_DATA (info
, codep
+ 1);
12098 threebyte
= *codep
;
12099 dp
= &dis386_twobyte
[threebyte
];
12100 need_modrm
= twobyte_has_modrm
[*codep
];
12105 dp
= &dis386
[*codep
];
12106 need_modrm
= onebyte_has_modrm
[*codep
];
12110 /* Save sizeflag for printing the extra prefixes later before updating
12111 it for mnemonic and operand processing. The prefix names depend
12112 only on the address mode. */
12113 orig_sizeflag
= sizeflag
;
12114 if (prefixes
& PREFIX_ADDR
)
12116 if ((prefixes
& PREFIX_DATA
))
12122 FETCH_DATA (info
, codep
+ 1);
12123 modrm
.mod
= (*codep
>> 6) & 3;
12124 modrm
.reg
= (*codep
>> 3) & 7;
12125 modrm
.rm
= *codep
& 7;
12131 memset (&vex
, 0, sizeof (vex
));
12133 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12135 get_sib (info
, sizeflag
);
12136 dofloat (sizeflag
);
12140 dp
= get_valid_dis386 (dp
, info
);
12141 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12143 get_sib (info
, sizeflag
);
12144 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12147 op_ad
= MAX_OPERANDS
- 1 - i
;
12149 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12150 /* For EVEX instruction after the last operand masking
12151 should be printed. */
12152 if (i
== 0 && vex
.evex
)
12154 /* Don't print {%k0}. */
12155 if (vex
.mask_register_specifier
)
12158 oappend (names_mask
[vex
.mask_register_specifier
]);
12168 /* Check if the REX prefix is used. */
12169 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
12170 all_prefixes
[last_rex_prefix
] = 0;
12172 /* Check if the SEG prefix is used. */
12173 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12174 | PREFIX_FS
| PREFIX_GS
)) != 0
12175 && (used_prefixes
& active_seg_prefix
) != 0)
12176 all_prefixes
[last_seg_prefix
] = 0;
12178 /* Check if the ADDR prefix is used. */
12179 if ((prefixes
& PREFIX_ADDR
) != 0
12180 && (used_prefixes
& PREFIX_ADDR
) != 0)
12181 all_prefixes
[last_addr_prefix
] = 0;
12183 /* Check if the DATA prefix is used. */
12184 if ((prefixes
& PREFIX_DATA
) != 0
12185 && (used_prefixes
& PREFIX_DATA
) != 0)
12186 all_prefixes
[last_data_prefix
] = 0;
12188 /* Print the extra prefixes. */
12190 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12191 if (all_prefixes
[i
])
12194 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12197 prefix_length
+= strlen (name
) + 1;
12198 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12201 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12202 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12203 used by putop and MMX/SSE operand and may be overriden by the
12204 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12206 if (dp
->prefix_requirement
== PREFIX_OPCODE
12207 && dp
!= &bad_opcode
12209 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
12211 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12213 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12215 && (used_prefixes
& PREFIX_DATA
) == 0))))
12217 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12218 return end_codep
- priv
.the_buffer
;
12221 /* Check maximum code length. */
12222 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12224 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12225 return MAX_CODE_LENGTH
;
12228 obufp
= mnemonicendp
;
12229 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12232 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12234 /* The enter and bound instructions are printed with operands in the same
12235 order as the intel book; everything else is printed in reverse order. */
12236 if (intel_syntax
|| two_source_ops
)
12240 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12241 op_txt
[i
] = op_out
[i
];
12243 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12244 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12246 op_txt
[2] = op_out
[3];
12247 op_txt
[3] = op_out
[2];
12250 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12252 op_ad
= op_index
[i
];
12253 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12254 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12255 riprel
= op_riprel
[i
];
12256 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12257 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12262 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12263 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12267 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12271 (*info
->fprintf_func
) (info
->stream
, ",");
12272 if (op_index
[i
] != -1 && !op_riprel
[i
])
12273 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
12275 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12279 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12280 if (op_index
[i
] != -1 && op_riprel
[i
])
12282 (*info
->fprintf_func
) (info
->stream
, " # ");
12283 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12284 + op_address
[op_index
[i
]]), info
);
12287 return codep
- priv
.the_buffer
;
12290 static const char *float_mem
[] = {
12365 static const unsigned char float_mem_mode
[] = {
12440 #define ST { OP_ST, 0 }
12441 #define STi { OP_STi, 0 }
12443 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12444 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12445 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12446 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12447 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12448 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12449 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12450 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12451 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12453 static const struct dis386 float_reg
[][8] = {
12456 { "fadd", { ST
, STi
}, 0 },
12457 { "fmul", { ST
, STi
}, 0 },
12458 { "fcom", { STi
}, 0 },
12459 { "fcomp", { STi
}, 0 },
12460 { "fsub", { ST
, STi
}, 0 },
12461 { "fsubr", { ST
, STi
}, 0 },
12462 { "fdiv", { ST
, STi
}, 0 },
12463 { "fdivr", { ST
, STi
}, 0 },
12467 { "fld", { STi
}, 0 },
12468 { "fxch", { STi
}, 0 },
12478 { "fcmovb", { ST
, STi
}, 0 },
12479 { "fcmove", { ST
, STi
}, 0 },
12480 { "fcmovbe",{ ST
, STi
}, 0 },
12481 { "fcmovu", { ST
, STi
}, 0 },
12489 { "fcmovnb",{ ST
, STi
}, 0 },
12490 { "fcmovne",{ ST
, STi
}, 0 },
12491 { "fcmovnbe",{ ST
, STi
}, 0 },
12492 { "fcmovnu",{ ST
, STi
}, 0 },
12494 { "fucomi", { ST
, STi
}, 0 },
12495 { "fcomi", { ST
, STi
}, 0 },
12500 { "fadd", { STi
, ST
}, 0 },
12501 { "fmul", { STi
, ST
}, 0 },
12504 { "fsub{!M|r}", { STi
, ST
}, 0 },
12505 { "fsub{M|}", { STi
, ST
}, 0 },
12506 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12507 { "fdiv{M|}", { STi
, ST
}, 0 },
12511 { "ffree", { STi
}, 0 },
12513 { "fst", { STi
}, 0 },
12514 { "fstp", { STi
}, 0 },
12515 { "fucom", { STi
}, 0 },
12516 { "fucomp", { STi
}, 0 },
12522 { "faddp", { STi
, ST
}, 0 },
12523 { "fmulp", { STi
, ST
}, 0 },
12526 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12527 { "fsub{M|}p", { STi
, ST
}, 0 },
12528 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12529 { "fdiv{M|}p", { STi
, ST
}, 0 },
12533 { "ffreep", { STi
}, 0 },
12538 { "fucomip", { ST
, STi
}, 0 },
12539 { "fcomip", { ST
, STi
}, 0 },
12544 static char *fgrps
[][8] = {
12547 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12552 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12557 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12562 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12567 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12572 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12577 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12582 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12583 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12588 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12593 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12598 swap_operand (void)
12600 mnemonicendp
[0] = '.';
12601 mnemonicendp
[1] = 's';
12606 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12607 int sizeflag ATTRIBUTE_UNUSED
)
12609 /* Skip mod/rm byte. */
12615 dofloat (int sizeflag
)
12617 const struct dis386
*dp
;
12618 unsigned char floatop
;
12620 floatop
= codep
[-1];
12622 if (modrm
.mod
!= 3)
12624 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12626 putop (float_mem
[fp_indx
], sizeflag
);
12629 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12632 /* Skip mod/rm byte. */
12636 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12637 if (dp
->name
== NULL
)
12639 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12641 /* Instruction fnstsw is only one with strange arg. */
12642 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12643 strcpy (op_out
[0], names16
[0]);
12647 putop (dp
->name
, sizeflag
);
12652 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12657 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12661 /* Like oappend (below), but S is a string starting with '%'.
12662 In Intel syntax, the '%' is elided. */
12664 oappend_maybe_intel (const char *s
)
12666 oappend (s
+ intel_syntax
);
12670 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12672 oappend_maybe_intel ("%st");
12676 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12678 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12679 oappend_maybe_intel (scratchbuf
);
12682 /* Capital letters in template are macros. */
12684 putop (const char *in_template
, int sizeflag
)
12689 unsigned int l
= 0, len
= 1;
12692 #define SAVE_LAST(c) \
12693 if (l < len && l < sizeof (last)) \
12698 for (p
= in_template
; *p
; p
++)
12714 while (*++p
!= '|')
12715 if (*p
== '}' || *p
== '\0')
12718 /* Fall through. */
12723 while (*++p
!= '}')
12734 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12738 if (l
== 0 && len
== 1)
12743 if (sizeflag
& SUFFIX_ALWAYS
)
12756 if (address_mode
== mode_64bit
12757 && !(prefixes
& PREFIX_ADDR
))
12768 if (intel_syntax
&& !alt
)
12770 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12772 if (sizeflag
& DFLAG
)
12773 *obufp
++ = intel_syntax
? 'd' : 'l';
12775 *obufp
++ = intel_syntax
? 'w' : 's';
12776 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12780 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12783 if (modrm
.mod
== 3)
12789 if (sizeflag
& DFLAG
)
12790 *obufp
++ = intel_syntax
? 'd' : 'l';
12793 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12799 case 'E': /* For jcxz/jecxz */
12800 if (address_mode
== mode_64bit
)
12802 if (sizeflag
& AFLAG
)
12808 if (sizeflag
& AFLAG
)
12810 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12815 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12817 if (sizeflag
& AFLAG
)
12818 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12820 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12821 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12825 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12827 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12831 if (!(rex
& REX_W
))
12832 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12837 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12838 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12840 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12843 if (prefixes
& PREFIX_DS
)
12862 if (l
!= 0 || len
!= 1)
12864 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12869 if (!need_vex
|| !vex
.evex
)
12872 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12874 switch (vex
.length
)
12892 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12897 /* Fall through. */
12900 if (l
!= 0 || len
!= 1)
12908 if (sizeflag
& SUFFIX_ALWAYS
)
12912 if (intel_mnemonic
!= cond
)
12916 if ((prefixes
& PREFIX_FWAIT
) == 0)
12919 used_prefixes
|= PREFIX_FWAIT
;
12925 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12929 if (!(rex
& REX_W
))
12930 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12934 && address_mode
== mode_64bit
12935 && isa64
== intel64
)
12940 /* Fall through. */
12943 && address_mode
== mode_64bit
12944 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12949 /* Fall through. */
12952 if (l
== 0 && len
== 1)
12957 if ((rex
& REX_W
) == 0
12958 && (prefixes
& PREFIX_DATA
))
12960 if ((sizeflag
& DFLAG
) == 0)
12962 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12966 if ((prefixes
& PREFIX_DATA
)
12968 || (sizeflag
& SUFFIX_ALWAYS
))
12975 if (sizeflag
& DFLAG
)
12979 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12985 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12991 if ((prefixes
& PREFIX_DATA
)
12993 || (sizeflag
& SUFFIX_ALWAYS
))
13000 if (sizeflag
& DFLAG
)
13001 *obufp
++ = intel_syntax
? 'd' : 'l';
13004 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13012 if (address_mode
== mode_64bit
13013 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13015 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13019 /* Fall through. */
13022 if (l
== 0 && len
== 1)
13025 if (intel_syntax
&& !alt
)
13028 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13034 if (sizeflag
& DFLAG
)
13035 *obufp
++ = intel_syntax
? 'd' : 'l';
13038 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13044 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13050 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13065 else if (sizeflag
& DFLAG
)
13074 if (intel_syntax
&& !p
[1]
13075 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13077 if (!(rex
& REX_W
))
13078 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13081 if (l
== 0 && len
== 1)
13085 if (address_mode
== mode_64bit
13086 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13088 if (sizeflag
& SUFFIX_ALWAYS
)
13110 /* Fall through. */
13113 if (l
== 0 && len
== 1)
13118 if (sizeflag
& SUFFIX_ALWAYS
)
13124 if (sizeflag
& DFLAG
)
13128 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13142 if (address_mode
== mode_64bit
13143 && !(prefixes
& PREFIX_ADDR
))
13154 if (l
!= 0 || len
!= 1)
13159 if (need_vex
&& vex
.prefix
)
13161 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
13168 if (prefixes
& PREFIX_DATA
)
13172 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13176 if (l
== 0 && len
== 1)
13180 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13188 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13190 switch (vex
.length
)
13206 if (l
== 0 && len
== 1)
13208 /* operand size flag for cwtl, cbtw */
13217 else if (sizeflag
& DFLAG
)
13221 if (!(rex
& REX_W
))
13222 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13229 && last
[0] != 'L'))
13236 if (last
[0] == 'X')
13237 *obufp
++ = vex
.w
? 'd': 's';
13239 *obufp
++ = vex
.w
? 'q': 'd';
13245 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13247 if (sizeflag
& DFLAG
)
13251 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13257 if (address_mode
== mode_64bit
13258 && (isa64
== intel64
13259 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13261 else if ((prefixes
& PREFIX_DATA
))
13263 if (!(sizeflag
& DFLAG
))
13265 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13272 mnemonicendp
= obufp
;
13277 oappend (const char *s
)
13279 obufp
= stpcpy (obufp
, s
);
13285 /* Only print the active segment register. */
13286 if (!active_seg_prefix
)
13289 used_prefixes
|= active_seg_prefix
;
13290 switch (active_seg_prefix
)
13293 oappend_maybe_intel ("%cs:");
13296 oappend_maybe_intel ("%ds:");
13299 oappend_maybe_intel ("%ss:");
13302 oappend_maybe_intel ("%es:");
13305 oappend_maybe_intel ("%fs:");
13308 oappend_maybe_intel ("%gs:");
13316 OP_indirE (int bytemode
, int sizeflag
)
13320 OP_E (bytemode
, sizeflag
);
13324 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13326 if (address_mode
== mode_64bit
)
13334 sprintf_vma (tmp
, disp
);
13335 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13336 strcpy (buf
+ 2, tmp
+ i
);
13340 bfd_signed_vma v
= disp
;
13347 /* Check for possible overflow on 0x8000000000000000. */
13350 strcpy (buf
, "9223372036854775808");
13364 tmp
[28 - i
] = (v
% 10) + '0';
13368 strcpy (buf
, tmp
+ 29 - i
);
13374 sprintf (buf
, "0x%x", (unsigned int) disp
);
13376 sprintf (buf
, "%d", (int) disp
);
13380 /* Put DISP in BUF as signed hex number. */
13383 print_displacement (char *buf
, bfd_vma disp
)
13385 bfd_signed_vma val
= disp
;
13394 /* Check for possible overflow. */
13397 switch (address_mode
)
13400 strcpy (buf
+ j
, "0x8000000000000000");
13403 strcpy (buf
+ j
, "0x80000000");
13406 strcpy (buf
+ j
, "0x8000");
13416 sprintf_vma (tmp
, (bfd_vma
) val
);
13417 for (i
= 0; tmp
[i
] == '0'; i
++)
13419 if (tmp
[i
] == '\0')
13421 strcpy (buf
+ j
, tmp
+ i
);
13425 intel_operand_size (int bytemode
, int sizeflag
)
13429 && (bytemode
== x_mode
13430 || bytemode
== evex_half_bcst_xmmq_mode
))
13433 oappend ("QWORD PTR ");
13435 oappend ("DWORD PTR ");
13444 oappend ("BYTE PTR ");
13449 oappend ("WORD PTR ");
13452 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13454 oappend ("QWORD PTR ");
13457 /* Fall through. */
13459 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13461 oappend ("QWORD PTR ");
13464 /* Fall through. */
13470 oappend ("QWORD PTR ");
13473 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13474 oappend ("DWORD PTR ");
13476 oappend ("WORD PTR ");
13477 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13481 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13483 oappend ("WORD PTR ");
13484 if (!(rex
& REX_W
))
13485 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13488 if (sizeflag
& DFLAG
)
13489 oappend ("QWORD PTR ");
13491 oappend ("DWORD PTR ");
13492 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13495 case d_scalar_mode
:
13496 case d_scalar_swap_mode
:
13499 oappend ("DWORD PTR ");
13502 case q_scalar_mode
:
13503 case q_scalar_swap_mode
:
13505 oappend ("QWORD PTR ");
13509 if (address_mode
== mode_64bit
)
13510 oappend ("QWORD PTR ");
13512 oappend ("DWORD PTR ");
13515 if (sizeflag
& DFLAG
)
13516 oappend ("FWORD PTR ");
13518 oappend ("DWORD PTR ");
13519 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13522 oappend ("TBYTE PTR ");
13526 case evex_x_gscat_mode
:
13527 case evex_x_nobcst_mode
:
13528 case b_scalar_mode
:
13529 case w_scalar_mode
:
13532 switch (vex
.length
)
13535 oappend ("XMMWORD PTR ");
13538 oappend ("YMMWORD PTR ");
13541 oappend ("ZMMWORD PTR ");
13548 oappend ("XMMWORD PTR ");
13551 oappend ("XMMWORD PTR ");
13554 oappend ("YMMWORD PTR ");
13557 case evex_half_bcst_xmmq_mode
:
13561 switch (vex
.length
)
13564 oappend ("QWORD PTR ");
13567 oappend ("XMMWORD PTR ");
13570 oappend ("YMMWORD PTR ");
13580 switch (vex
.length
)
13585 oappend ("BYTE PTR ");
13595 switch (vex
.length
)
13600 oappend ("WORD PTR ");
13610 switch (vex
.length
)
13615 oappend ("DWORD PTR ");
13625 switch (vex
.length
)
13630 oappend ("QWORD PTR ");
13640 switch (vex
.length
)
13643 oappend ("WORD PTR ");
13646 oappend ("DWORD PTR ");
13649 oappend ("QWORD PTR ");
13659 switch (vex
.length
)
13662 oappend ("DWORD PTR ");
13665 oappend ("QWORD PTR ");
13668 oappend ("XMMWORD PTR ");
13678 switch (vex
.length
)
13681 oappend ("QWORD PTR ");
13684 oappend ("YMMWORD PTR ");
13687 oappend ("ZMMWORD PTR ");
13697 switch (vex
.length
)
13701 oappend ("XMMWORD PTR ");
13708 oappend ("OWORD PTR ");
13711 case vex_w_dq_mode
:
13712 case vex_scalar_w_dq_mode
:
13717 oappend ("QWORD PTR ");
13719 oappend ("DWORD PTR ");
13721 case vex_vsib_d_w_dq_mode
:
13722 case vex_vsib_q_w_dq_mode
:
13729 oappend ("QWORD PTR ");
13731 oappend ("DWORD PTR ");
13735 switch (vex
.length
)
13738 oappend ("XMMWORD PTR ");
13741 oappend ("YMMWORD PTR ");
13744 oappend ("ZMMWORD PTR ");
13751 case vex_vsib_q_w_d_mode
:
13752 case vex_vsib_d_w_d_mode
:
13753 if (!need_vex
|| !vex
.evex
)
13756 switch (vex
.length
)
13759 oappend ("QWORD PTR ");
13762 oappend ("XMMWORD PTR ");
13765 oappend ("YMMWORD PTR ");
13773 if (!need_vex
|| vex
.length
!= 128)
13776 oappend ("DWORD PTR ");
13778 oappend ("BYTE PTR ");
13784 oappend ("QWORD PTR ");
13786 oappend ("WORD PTR ");
13796 OP_E_register (int bytemode
, int sizeflag
)
13798 int reg
= modrm
.rm
;
13799 const char **names
;
13805 if ((sizeflag
& SUFFIX_ALWAYS
)
13806 && (bytemode
== b_swap_mode
13807 || bytemode
== bnd_swap_mode
13808 || bytemode
== v_swap_mode
))
13834 names
= address_mode
== mode_64bit
? names64
: names32
;
13837 case bnd_swap_mode
:
13846 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13851 /* Fall through. */
13853 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13859 /* Fall through. */
13872 if ((sizeflag
& DFLAG
)
13873 || (bytemode
!= v_mode
13874 && bytemode
!= v_swap_mode
))
13878 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13882 names
= (address_mode
== mode_64bit
13883 ? names64
: names32
);
13884 if (!(prefixes
& PREFIX_ADDR
))
13885 names
= (address_mode
== mode_16bit
13886 ? names16
: names
);
13889 /* Remove "addr16/addr32". */
13890 all_prefixes
[last_addr_prefix
] = 0;
13891 names
= (address_mode
!= mode_32bit
13892 ? names32
: names16
);
13893 used_prefixes
|= PREFIX_ADDR
;
13903 names
= names_mask
;
13908 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13911 oappend (names
[reg
]);
13915 OP_E_memory (int bytemode
, int sizeflag
)
13918 int add
= (rex
& REX_B
) ? 8 : 0;
13924 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13926 && bytemode
!= x_mode
13927 && bytemode
!= xmmq_mode
13928 && bytemode
!= evex_half_bcst_xmmq_mode
)
13944 if (address_mode
!= mode_64bit
)
13950 case vex_vsib_d_w_dq_mode
:
13951 case vex_vsib_d_w_d_mode
:
13952 case vex_vsib_q_w_dq_mode
:
13953 case vex_vsib_q_w_d_mode
:
13954 case evex_x_gscat_mode
:
13956 shift
= vex
.w
? 3 : 2;
13959 case evex_half_bcst_xmmq_mode
:
13963 shift
= vex
.w
? 3 : 2;
13966 /* Fall through. */
13970 case evex_x_nobcst_mode
:
13972 switch (vex
.length
)
13995 case q_scalar_mode
:
13997 case q_scalar_swap_mode
:
14003 case d_scalar_mode
:
14005 case d_scalar_swap_mode
:
14008 case w_scalar_mode
:
14012 case b_scalar_mode
:
14017 shift
= address_mode
== mode_64bit
? 3 : 2;
14022 /* Make necessary corrections to shift for modes that need it.
14023 For these modes we currently have shift 4, 5 or 6 depending on
14024 vex.length (it corresponds to xmmword, ymmword or zmmword
14025 operand). We might want to make it 3, 4 or 5 (e.g. for
14026 xmmq_mode). In case of broadcast enabled the corrections
14027 aren't needed, as element size is always 32 or 64 bits. */
14029 && (bytemode
== xmmq_mode
14030 || bytemode
== evex_half_bcst_xmmq_mode
))
14032 else if (bytemode
== xmmqd_mode
)
14034 else if (bytemode
== xmmdw_mode
)
14036 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14044 intel_operand_size (bytemode
, sizeflag
);
14047 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14049 /* 32/64 bit address mode */
14059 int addr32flag
= !((sizeflag
& AFLAG
)
14060 || bytemode
== v_bnd_mode
14061 || bytemode
== v_bndmk_mode
14062 || bytemode
== bnd_mode
14063 || bytemode
== bnd_swap_mode
);
14064 const char **indexes64
= names64
;
14065 const char **indexes32
= names32
;
14075 vindex
= sib
.index
;
14081 case vex_vsib_d_w_dq_mode
:
14082 case vex_vsib_d_w_d_mode
:
14083 case vex_vsib_q_w_dq_mode
:
14084 case vex_vsib_q_w_d_mode
:
14094 switch (vex
.length
)
14097 indexes64
= indexes32
= names_xmm
;
14101 || bytemode
== vex_vsib_q_w_dq_mode
14102 || bytemode
== vex_vsib_q_w_d_mode
)
14103 indexes64
= indexes32
= names_ymm
;
14105 indexes64
= indexes32
= names_xmm
;
14109 || bytemode
== vex_vsib_q_w_dq_mode
14110 || bytemode
== vex_vsib_q_w_d_mode
)
14111 indexes64
= indexes32
= names_zmm
;
14113 indexes64
= indexes32
= names_ymm
;
14120 haveindex
= vindex
!= 4;
14127 rbase
= base
+ add
;
14135 if (address_mode
== mode_64bit
&& !havesib
)
14138 if (riprel
&& bytemode
== v_bndmk_mode
)
14146 FETCH_DATA (the_info
, codep
+ 1);
14148 if ((disp
& 0x80) != 0)
14150 if (vex
.evex
&& shift
> 0)
14163 && address_mode
!= mode_16bit
)
14165 if (address_mode
== mode_64bit
)
14167 /* Display eiz instead of addr32. */
14168 needindex
= addr32flag
;
14173 /* In 32-bit mode, we need index register to tell [offset]
14174 from [eiz*1 + offset]. */
14179 havedisp
= (havebase
14181 || (havesib
&& (haveindex
|| scale
!= 0)));
14184 if (modrm
.mod
!= 0 || base
== 5)
14186 if (havedisp
|| riprel
)
14187 print_displacement (scratchbuf
, disp
);
14189 print_operand_value (scratchbuf
, 1, disp
);
14190 oappend (scratchbuf
);
14194 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14198 if ((havebase
|| haveindex
|| needaddr32
|| riprel
)
14199 && (bytemode
!= v_bnd_mode
)
14200 && (bytemode
!= v_bndmk_mode
)
14201 && (bytemode
!= bnd_mode
)
14202 && (bytemode
!= bnd_swap_mode
))
14203 used_prefixes
|= PREFIX_ADDR
;
14205 if (havedisp
|| (intel_syntax
&& riprel
))
14207 *obufp
++ = open_char
;
14208 if (intel_syntax
&& riprel
)
14211 oappend (!addr32flag
? "rip" : "eip");
14215 oappend (address_mode
== mode_64bit
&& !addr32flag
14216 ? names64
[rbase
] : names32
[rbase
]);
14219 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14220 print index to tell base + index from base. */
14224 || (havebase
&& base
!= ESP_REG_NUM
))
14226 if (!intel_syntax
|| havebase
)
14228 *obufp
++ = separator_char
;
14232 oappend (address_mode
== mode_64bit
&& !addr32flag
14233 ? indexes64
[vindex
] : indexes32
[vindex
]);
14235 oappend (address_mode
== mode_64bit
&& !addr32flag
14236 ? index64
: index32
);
14238 *obufp
++ = scale_char
;
14240 sprintf (scratchbuf
, "%d", 1 << scale
);
14241 oappend (scratchbuf
);
14245 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14247 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14252 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14256 disp
= - (bfd_signed_vma
) disp
;
14260 print_displacement (scratchbuf
, disp
);
14262 print_operand_value (scratchbuf
, 1, disp
);
14263 oappend (scratchbuf
);
14266 *obufp
++ = close_char
;
14269 else if (intel_syntax
)
14271 if (modrm
.mod
!= 0 || base
== 5)
14273 if (!active_seg_prefix
)
14275 oappend (names_seg
[ds_reg
- es_reg
]);
14278 print_operand_value (scratchbuf
, 1, disp
);
14279 oappend (scratchbuf
);
14285 /* 16 bit address mode */
14286 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14293 if ((disp
& 0x8000) != 0)
14298 FETCH_DATA (the_info
, codep
+ 1);
14300 if ((disp
& 0x80) != 0)
14302 if (vex
.evex
&& shift
> 0)
14307 if ((disp
& 0x8000) != 0)
14313 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14315 print_displacement (scratchbuf
, disp
);
14316 oappend (scratchbuf
);
14319 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14321 *obufp
++ = open_char
;
14323 oappend (index16
[modrm
.rm
]);
14325 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14327 if ((bfd_signed_vma
) disp
>= 0)
14332 else if (modrm
.mod
!= 1)
14336 disp
= - (bfd_signed_vma
) disp
;
14339 print_displacement (scratchbuf
, disp
);
14340 oappend (scratchbuf
);
14343 *obufp
++ = close_char
;
14346 else if (intel_syntax
)
14348 if (!active_seg_prefix
)
14350 oappend (names_seg
[ds_reg
- es_reg
]);
14353 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14354 oappend (scratchbuf
);
14357 if (vex
.evex
&& vex
.b
14358 && (bytemode
== x_mode
14359 || bytemode
== xmmq_mode
14360 || bytemode
== evex_half_bcst_xmmq_mode
))
14363 || bytemode
== xmmq_mode
14364 || bytemode
== evex_half_bcst_xmmq_mode
)
14366 switch (vex
.length
)
14369 oappend ("{1to2}");
14372 oappend ("{1to4}");
14375 oappend ("{1to8}");
14383 switch (vex
.length
)
14386 oappend ("{1to4}");
14389 oappend ("{1to8}");
14392 oappend ("{1to16}");
14402 OP_E (int bytemode
, int sizeflag
)
14404 /* Skip mod/rm byte. */
14408 if (modrm
.mod
== 3)
14409 OP_E_register (bytemode
, sizeflag
);
14411 OP_E_memory (bytemode
, sizeflag
);
14415 OP_G (int bytemode
, int sizeflag
)
14418 const char **names
;
14427 oappend (names8rex
[modrm
.reg
+ add
]);
14429 oappend (names8
[modrm
.reg
+ add
]);
14432 oappend (names16
[modrm
.reg
+ add
]);
14437 oappend (names32
[modrm
.reg
+ add
]);
14440 oappend (names64
[modrm
.reg
+ add
]);
14443 if (modrm
.reg
> 0x3)
14448 oappend (names_bnd
[modrm
.reg
]);
14457 oappend (names64
[modrm
.reg
+ add
]);
14460 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
14461 oappend (names32
[modrm
.reg
+ add
]);
14463 oappend (names16
[modrm
.reg
+ add
]);
14464 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14468 names
= (address_mode
== mode_64bit
14469 ? names64
: names32
);
14470 if (!(prefixes
& PREFIX_ADDR
))
14472 if (address_mode
== mode_16bit
)
14477 /* Remove "addr16/addr32". */
14478 all_prefixes
[last_addr_prefix
] = 0;
14479 names
= (address_mode
!= mode_32bit
14480 ? names32
: names16
);
14481 used_prefixes
|= PREFIX_ADDR
;
14483 oappend (names
[modrm
.reg
+ add
]);
14486 if (address_mode
== mode_64bit
)
14487 oappend (names64
[modrm
.reg
+ add
]);
14489 oappend (names32
[modrm
.reg
+ add
]);
14493 if ((modrm
.reg
+ add
) > 0x7)
14498 oappend (names_mask
[modrm
.reg
+ add
]);
14501 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14514 FETCH_DATA (the_info
, codep
+ 8);
14515 a
= *codep
++ & 0xff;
14516 a
|= (*codep
++ & 0xff) << 8;
14517 a
|= (*codep
++ & 0xff) << 16;
14518 a
|= (*codep
++ & 0xffu
) << 24;
14519 b
= *codep
++ & 0xff;
14520 b
|= (*codep
++ & 0xff) << 8;
14521 b
|= (*codep
++ & 0xff) << 16;
14522 b
|= (*codep
++ & 0xffu
) << 24;
14523 x
= a
+ ((bfd_vma
) b
<< 32);
14531 static bfd_signed_vma
14534 bfd_signed_vma x
= 0;
14536 FETCH_DATA (the_info
, codep
+ 4);
14537 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14538 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14539 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14540 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14544 static bfd_signed_vma
14547 bfd_signed_vma x
= 0;
14549 FETCH_DATA (the_info
, codep
+ 4);
14550 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14551 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14552 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14553 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14555 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14565 FETCH_DATA (the_info
, codep
+ 2);
14566 x
= *codep
++ & 0xff;
14567 x
|= (*codep
++ & 0xff) << 8;
14572 set_op (bfd_vma op
, int riprel
)
14574 op_index
[op_ad
] = op_ad
;
14575 if (address_mode
== mode_64bit
)
14577 op_address
[op_ad
] = op
;
14578 op_riprel
[op_ad
] = riprel
;
14582 /* Mask to get a 32-bit address. */
14583 op_address
[op_ad
] = op
& 0xffffffff;
14584 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14589 OP_REG (int code
, int sizeflag
)
14596 case es_reg
: case ss_reg
: case cs_reg
:
14597 case ds_reg
: case fs_reg
: case gs_reg
:
14598 oappend (names_seg
[code
- es_reg
]);
14610 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14611 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14612 s
= names16
[code
- ax_reg
+ add
];
14614 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14615 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14618 s
= names8rex
[code
- al_reg
+ add
];
14620 s
= names8
[code
- al_reg
];
14622 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14623 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14624 if (address_mode
== mode_64bit
14625 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14627 s
= names64
[code
- rAX_reg
+ add
];
14630 code
+= eAX_reg
- rAX_reg
;
14631 /* Fall through. */
14632 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14633 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14636 s
= names64
[code
- eAX_reg
+ add
];
14639 if (sizeflag
& DFLAG
)
14640 s
= names32
[code
- eAX_reg
+ add
];
14642 s
= names16
[code
- eAX_reg
+ add
];
14643 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14647 s
= INTERNAL_DISASSEMBLER_ERROR
;
14654 OP_IMREG (int code
, int sizeflag
)
14666 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14667 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14668 s
= names16
[code
- ax_reg
];
14670 case es_reg
: case ss_reg
: case cs_reg
:
14671 case ds_reg
: case fs_reg
: case gs_reg
:
14672 s
= names_seg
[code
- es_reg
];
14674 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14675 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14678 s
= names8rex
[code
- al_reg
];
14680 s
= names8
[code
- al_reg
];
14682 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14683 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14686 s
= names64
[code
- eAX_reg
];
14689 if (sizeflag
& DFLAG
)
14690 s
= names32
[code
- eAX_reg
];
14692 s
= names16
[code
- eAX_reg
];
14693 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14696 case z_mode_ax_reg
:
14697 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14701 if (!(rex
& REX_W
))
14702 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14705 s
= INTERNAL_DISASSEMBLER_ERROR
;
14712 OP_I (int bytemode
, int sizeflag
)
14715 bfd_signed_vma mask
= -1;
14720 FETCH_DATA (the_info
, codep
+ 1);
14725 if (address_mode
== mode_64bit
)
14730 /* Fall through. */
14737 if (sizeflag
& DFLAG
)
14747 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14759 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14764 scratchbuf
[0] = '$';
14765 print_operand_value (scratchbuf
+ 1, 1, op
);
14766 oappend_maybe_intel (scratchbuf
);
14767 scratchbuf
[0] = '\0';
14771 OP_I64 (int bytemode
, int sizeflag
)
14774 bfd_signed_vma mask
= -1;
14776 if (address_mode
!= mode_64bit
)
14778 OP_I (bytemode
, sizeflag
);
14785 FETCH_DATA (the_info
, codep
+ 1);
14795 if (sizeflag
& DFLAG
)
14805 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14813 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14818 scratchbuf
[0] = '$';
14819 print_operand_value (scratchbuf
+ 1, 1, op
);
14820 oappend_maybe_intel (scratchbuf
);
14821 scratchbuf
[0] = '\0';
14825 OP_sI (int bytemode
, int sizeflag
)
14833 FETCH_DATA (the_info
, codep
+ 1);
14835 if ((op
& 0x80) != 0)
14837 if (bytemode
== b_T_mode
)
14839 if (address_mode
!= mode_64bit
14840 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14842 /* The operand-size prefix is overridden by a REX prefix. */
14843 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14851 if (!(rex
& REX_W
))
14853 if (sizeflag
& DFLAG
)
14861 /* The operand-size prefix is overridden by a REX prefix. */
14862 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14868 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14872 scratchbuf
[0] = '$';
14873 print_operand_value (scratchbuf
+ 1, 1, op
);
14874 oappend_maybe_intel (scratchbuf
);
14878 OP_J (int bytemode
, int sizeflag
)
14882 bfd_vma segment
= 0;
14887 FETCH_DATA (the_info
, codep
+ 1);
14889 if ((disp
& 0x80) != 0)
14893 if (isa64
== amd64
)
14895 if ((sizeflag
& DFLAG
)
14896 || (address_mode
== mode_64bit
14897 && (isa64
!= amd64
|| (rex
& REX_W
))))
14902 if ((disp
& 0x8000) != 0)
14904 /* In 16bit mode, address is wrapped around at 64k within
14905 the same segment. Otherwise, a data16 prefix on a jump
14906 instruction means that the pc is masked to 16 bits after
14907 the displacement is added! */
14909 if ((prefixes
& PREFIX_DATA
) == 0)
14910 segment
= ((start_pc
+ (codep
- start_codep
))
14911 & ~((bfd_vma
) 0xffff));
14913 if (address_mode
!= mode_64bit
14914 || (isa64
== amd64
&& !(rex
& REX_W
)))
14915 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14918 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14921 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14923 print_operand_value (scratchbuf
, 1, disp
);
14924 oappend (scratchbuf
);
14928 OP_SEG (int bytemode
, int sizeflag
)
14930 if (bytemode
== w_mode
)
14931 oappend (names_seg
[modrm
.reg
]);
14933 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14937 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14941 if (sizeflag
& DFLAG
)
14951 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14953 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14955 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14956 oappend (scratchbuf
);
14960 OP_OFF (int bytemode
, int sizeflag
)
14964 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14965 intel_operand_size (bytemode
, sizeflag
);
14968 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14975 if (!active_seg_prefix
)
14977 oappend (names_seg
[ds_reg
- es_reg
]);
14981 print_operand_value (scratchbuf
, 1, off
);
14982 oappend (scratchbuf
);
14986 OP_OFF64 (int bytemode
, int sizeflag
)
14990 if (address_mode
!= mode_64bit
14991 || (prefixes
& PREFIX_ADDR
))
14993 OP_OFF (bytemode
, sizeflag
);
14997 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14998 intel_operand_size (bytemode
, sizeflag
);
15005 if (!active_seg_prefix
)
15007 oappend (names_seg
[ds_reg
- es_reg
]);
15011 print_operand_value (scratchbuf
, 1, off
);
15012 oappend (scratchbuf
);
15016 ptr_reg (int code
, int sizeflag
)
15020 *obufp
++ = open_char
;
15021 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15022 if (address_mode
== mode_64bit
)
15024 if (!(sizeflag
& AFLAG
))
15025 s
= names32
[code
- eAX_reg
];
15027 s
= names64
[code
- eAX_reg
];
15029 else if (sizeflag
& AFLAG
)
15030 s
= names32
[code
- eAX_reg
];
15032 s
= names16
[code
- eAX_reg
];
15034 *obufp
++ = close_char
;
15039 OP_ESreg (int code
, int sizeflag
)
15045 case 0x6d: /* insw/insl */
15046 intel_operand_size (z_mode
, sizeflag
);
15048 case 0xa5: /* movsw/movsl/movsq */
15049 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15050 case 0xab: /* stosw/stosl */
15051 case 0xaf: /* scasw/scasl */
15052 intel_operand_size (v_mode
, sizeflag
);
15055 intel_operand_size (b_mode
, sizeflag
);
15058 oappend_maybe_intel ("%es:");
15059 ptr_reg (code
, sizeflag
);
15063 OP_DSreg (int code
, int sizeflag
)
15069 case 0x6f: /* outsw/outsl */
15070 intel_operand_size (z_mode
, sizeflag
);
15072 case 0xa5: /* movsw/movsl/movsq */
15073 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15074 case 0xad: /* lodsw/lodsl/lodsq */
15075 intel_operand_size (v_mode
, sizeflag
);
15078 intel_operand_size (b_mode
, sizeflag
);
15081 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15082 default segment register DS is printed. */
15083 if (!active_seg_prefix
)
15084 active_seg_prefix
= PREFIX_DS
;
15086 ptr_reg (code
, sizeflag
);
15090 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15098 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15100 all_prefixes
[last_lock_prefix
] = 0;
15101 used_prefixes
|= PREFIX_LOCK
;
15106 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15107 oappend_maybe_intel (scratchbuf
);
15111 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15120 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15122 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15123 oappend (scratchbuf
);
15127 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15129 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15130 oappend_maybe_intel (scratchbuf
);
15134 OP_R (int bytemode
, int sizeflag
)
15136 /* Skip mod/rm byte. */
15139 OP_E_register (bytemode
, sizeflag
);
15143 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15145 int reg
= modrm
.reg
;
15146 const char **names
;
15148 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15149 if (prefixes
& PREFIX_DATA
)
15158 oappend (names
[reg
]);
15162 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15164 int reg
= modrm
.reg
;
15165 const char **names
;
15177 && bytemode
!= xmm_mode
15178 && bytemode
!= xmmq_mode
15179 && bytemode
!= evex_half_bcst_xmmq_mode
15180 && bytemode
!= ymm_mode
15181 && bytemode
!= scalar_mode
)
15183 switch (vex
.length
)
15190 || (bytemode
!= vex_vsib_q_w_dq_mode
15191 && bytemode
!= vex_vsib_q_w_d_mode
))
15203 else if (bytemode
== xmmq_mode
15204 || bytemode
== evex_half_bcst_xmmq_mode
)
15206 switch (vex
.length
)
15219 else if (bytemode
== ymm_mode
)
15223 oappend (names
[reg
]);
15227 OP_EM (int bytemode
, int sizeflag
)
15230 const char **names
;
15232 if (modrm
.mod
!= 3)
15235 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15237 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15238 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15240 OP_E (bytemode
, sizeflag
);
15244 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15247 /* Skip mod/rm byte. */
15250 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15252 if (prefixes
& PREFIX_DATA
)
15261 oappend (names
[reg
]);
15264 /* cvt* are the only instructions in sse2 which have
15265 both SSE and MMX operands and also have 0x66 prefix
15266 in their opcode. 0x66 was originally used to differentiate
15267 between SSE and MMX instruction(operands). So we have to handle the
15268 cvt* separately using OP_EMC and OP_MXC */
15270 OP_EMC (int bytemode
, int sizeflag
)
15272 if (modrm
.mod
!= 3)
15274 if (intel_syntax
&& bytemode
== v_mode
)
15276 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15277 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15279 OP_E (bytemode
, sizeflag
);
15283 /* Skip mod/rm byte. */
15286 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15287 oappend (names_mm
[modrm
.rm
]);
15291 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15293 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15294 oappend (names_mm
[modrm
.reg
]);
15298 OP_EX (int bytemode
, int sizeflag
)
15301 const char **names
;
15303 /* Skip mod/rm byte. */
15307 if (modrm
.mod
!= 3)
15309 OP_E_memory (bytemode
, sizeflag
);
15324 if ((sizeflag
& SUFFIX_ALWAYS
)
15325 && (bytemode
== x_swap_mode
15326 || bytemode
== d_swap_mode
15327 || bytemode
== d_scalar_swap_mode
15328 || bytemode
== q_swap_mode
15329 || bytemode
== q_scalar_swap_mode
))
15333 && bytemode
!= xmm_mode
15334 && bytemode
!= xmmdw_mode
15335 && bytemode
!= xmmqd_mode
15336 && bytemode
!= xmm_mb_mode
15337 && bytemode
!= xmm_mw_mode
15338 && bytemode
!= xmm_md_mode
15339 && bytemode
!= xmm_mq_mode
15340 && bytemode
!= xmm_mdq_mode
15341 && bytemode
!= xmmq_mode
15342 && bytemode
!= evex_half_bcst_xmmq_mode
15343 && bytemode
!= ymm_mode
15344 && bytemode
!= d_scalar_mode
15345 && bytemode
!= d_scalar_swap_mode
15346 && bytemode
!= q_scalar_mode
15347 && bytemode
!= q_scalar_swap_mode
15348 && bytemode
!= vex_scalar_w_dq_mode
)
15350 switch (vex
.length
)
15365 else if (bytemode
== xmmq_mode
15366 || bytemode
== evex_half_bcst_xmmq_mode
)
15368 switch (vex
.length
)
15381 else if (bytemode
== ymm_mode
)
15385 oappend (names
[reg
]);
15389 OP_MS (int bytemode
, int sizeflag
)
15391 if (modrm
.mod
== 3)
15392 OP_EM (bytemode
, sizeflag
);
15398 OP_XS (int bytemode
, int sizeflag
)
15400 if (modrm
.mod
== 3)
15401 OP_EX (bytemode
, sizeflag
);
15407 OP_M (int bytemode
, int sizeflag
)
15409 if (modrm
.mod
== 3)
15410 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15413 OP_E (bytemode
, sizeflag
);
15417 OP_0f07 (int bytemode
, int sizeflag
)
15419 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15422 OP_E (bytemode
, sizeflag
);
15425 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15426 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15429 NOP_Fixup1 (int bytemode
, int sizeflag
)
15431 if ((prefixes
& PREFIX_DATA
) != 0
15434 && address_mode
== mode_64bit
))
15435 OP_REG (bytemode
, sizeflag
);
15437 strcpy (obuf
, "nop");
15441 NOP_Fixup2 (int bytemode
, int sizeflag
)
15443 if ((prefixes
& PREFIX_DATA
) != 0
15446 && address_mode
== mode_64bit
))
15447 OP_IMREG (bytemode
, sizeflag
);
15450 static const char *const Suffix3DNow
[] = {
15451 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15452 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15453 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15454 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15455 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15456 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15457 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15458 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15459 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15460 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15461 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15462 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15463 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15464 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15465 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15466 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15467 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15468 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15469 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15470 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15471 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15472 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15473 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15474 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15475 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15476 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15477 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15478 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15479 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15480 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15481 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15482 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15483 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15484 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15485 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15486 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15487 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15488 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15489 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15490 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15491 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15492 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15493 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15494 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15495 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15496 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15497 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15498 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15499 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15500 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15501 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15502 /* CC */ NULL
, NULL
, NULL
, NULL
,
15503 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15504 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15505 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15506 /* DC */ NULL
, NULL
, NULL
, NULL
,
15507 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15508 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15509 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15510 /* EC */ NULL
, NULL
, NULL
, NULL
,
15511 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15512 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15513 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15514 /* FC */ NULL
, NULL
, NULL
, NULL
,
15518 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15520 const char *mnemonic
;
15522 FETCH_DATA (the_info
, codep
+ 1);
15523 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15524 place where an 8-bit immediate would normally go. ie. the last
15525 byte of the instruction. */
15526 obufp
= mnemonicendp
;
15527 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15529 oappend (mnemonic
);
15532 /* Since a variable sized modrm/sib chunk is between the start
15533 of the opcode (0x0f0f) and the opcode suffix, we need to do
15534 all the modrm processing first, and don't know until now that
15535 we have a bad opcode. This necessitates some cleaning up. */
15536 op_out
[0][0] = '\0';
15537 op_out
[1][0] = '\0';
15540 mnemonicendp
= obufp
;
15543 static struct op simd_cmp_op
[] =
15545 { STRING_COMMA_LEN ("eq") },
15546 { STRING_COMMA_LEN ("lt") },
15547 { STRING_COMMA_LEN ("le") },
15548 { STRING_COMMA_LEN ("unord") },
15549 { STRING_COMMA_LEN ("neq") },
15550 { STRING_COMMA_LEN ("nlt") },
15551 { STRING_COMMA_LEN ("nle") },
15552 { STRING_COMMA_LEN ("ord") }
15556 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15558 unsigned int cmp_type
;
15560 FETCH_DATA (the_info
, codep
+ 1);
15561 cmp_type
= *codep
++ & 0xff;
15562 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15565 char *p
= mnemonicendp
- 2;
15569 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15570 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15574 /* We have a reserved extension byte. Output it directly. */
15575 scratchbuf
[0] = '$';
15576 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15577 oappend_maybe_intel (scratchbuf
);
15578 scratchbuf
[0] = '\0';
15583 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
15584 int sizeflag ATTRIBUTE_UNUSED
)
15586 /* mwaitx %eax,%ecx,%ebx */
15589 const char **names
= (address_mode
== mode_64bit
15590 ? names64
: names32
);
15591 strcpy (op_out
[0], names
[0]);
15592 strcpy (op_out
[1], names
[1]);
15593 strcpy (op_out
[2], names
[3]);
15594 two_source_ops
= 1;
15596 /* Skip mod/rm byte. */
15602 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
15603 int sizeflag ATTRIBUTE_UNUSED
)
15605 /* mwait %eax,%ecx */
15608 const char **names
= (address_mode
== mode_64bit
15609 ? names64
: names32
);
15610 strcpy (op_out
[0], names
[0]);
15611 strcpy (op_out
[1], names
[1]);
15612 two_source_ops
= 1;
15614 /* Skip mod/rm byte. */
15620 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15621 int sizeflag ATTRIBUTE_UNUSED
)
15623 /* monitor %eax,%ecx,%edx" */
15626 const char **op1_names
;
15627 const char **names
= (address_mode
== mode_64bit
15628 ? names64
: names32
);
15630 if (!(prefixes
& PREFIX_ADDR
))
15631 op1_names
= (address_mode
== mode_16bit
15632 ? names16
: names
);
15635 /* Remove "addr16/addr32". */
15636 all_prefixes
[last_addr_prefix
] = 0;
15637 op1_names
= (address_mode
!= mode_32bit
15638 ? names32
: names16
);
15639 used_prefixes
|= PREFIX_ADDR
;
15641 strcpy (op_out
[0], op1_names
[0]);
15642 strcpy (op_out
[1], names
[1]);
15643 strcpy (op_out
[2], names
[2]);
15644 two_source_ops
= 1;
15646 /* Skip mod/rm byte. */
15654 /* Throw away prefixes and 1st. opcode byte. */
15655 codep
= insn_codep
+ 1;
15660 REP_Fixup (int bytemode
, int sizeflag
)
15662 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15664 if (prefixes
& PREFIX_REPZ
)
15665 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15672 OP_IMREG (bytemode
, sizeflag
);
15675 OP_ESreg (bytemode
, sizeflag
);
15678 OP_DSreg (bytemode
, sizeflag
);
15686 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15690 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15692 if (prefixes
& PREFIX_REPNZ
)
15693 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15696 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15700 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15701 int sizeflag ATTRIBUTE_UNUSED
)
15703 if (active_seg_prefix
== PREFIX_DS
15704 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15706 /* NOTRACK prefix is only valid on indirect branch instructions.
15707 NB: DATA prefix is unsupported for Intel64. */
15708 active_seg_prefix
= 0;
15709 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15713 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15714 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15718 HLE_Fixup1 (int bytemode
, int sizeflag
)
15721 && (prefixes
& PREFIX_LOCK
) != 0)
15723 if (prefixes
& PREFIX_REPZ
)
15724 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15725 if (prefixes
& PREFIX_REPNZ
)
15726 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15729 OP_E (bytemode
, sizeflag
);
15732 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15733 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15737 HLE_Fixup2 (int bytemode
, int sizeflag
)
15739 if (modrm
.mod
!= 3)
15741 if (prefixes
& PREFIX_REPZ
)
15742 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15743 if (prefixes
& PREFIX_REPNZ
)
15744 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15747 OP_E (bytemode
, sizeflag
);
15750 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15751 "xrelease" for memory operand. No check for LOCK prefix. */
15754 HLE_Fixup3 (int bytemode
, int sizeflag
)
15757 && last_repz_prefix
> last_repnz_prefix
15758 && (prefixes
& PREFIX_REPZ
) != 0)
15759 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15761 OP_E (bytemode
, sizeflag
);
15765 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15770 /* Change cmpxchg8b to cmpxchg16b. */
15771 char *p
= mnemonicendp
- 2;
15772 mnemonicendp
= stpcpy (p
, "16b");
15775 else if ((prefixes
& PREFIX_LOCK
) != 0)
15777 if (prefixes
& PREFIX_REPZ
)
15778 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15779 if (prefixes
& PREFIX_REPNZ
)
15780 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15783 OP_M (bytemode
, sizeflag
);
15787 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15789 const char **names
;
15793 switch (vex
.length
)
15807 oappend (names
[reg
]);
15811 CRC32_Fixup (int bytemode
, int sizeflag
)
15813 /* Add proper suffix to "crc32". */
15814 char *p
= mnemonicendp
;
15833 if (sizeflag
& DFLAG
)
15837 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15841 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15848 if (modrm
.mod
== 3)
15852 /* Skip mod/rm byte. */
15857 add
= (rex
& REX_B
) ? 8 : 0;
15858 if (bytemode
== b_mode
)
15862 oappend (names8rex
[modrm
.rm
+ add
]);
15864 oappend (names8
[modrm
.rm
+ add
]);
15870 oappend (names64
[modrm
.rm
+ add
]);
15871 else if ((prefixes
& PREFIX_DATA
))
15872 oappend (names16
[modrm
.rm
+ add
]);
15874 oappend (names32
[modrm
.rm
+ add
]);
15878 OP_E (bytemode
, sizeflag
);
15882 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15884 /* Add proper suffix to "fxsave" and "fxrstor". */
15888 char *p
= mnemonicendp
;
15894 OP_M (bytemode
, sizeflag
);
15898 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15900 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15903 char *p
= mnemonicendp
;
15908 else if (sizeflag
& SUFFIX_ALWAYS
)
15915 OP_EX (bytemode
, sizeflag
);
15918 /* Display the destination register operand for instructions with
15922 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15925 const char **names
;
15933 reg
= vex
.register_specifier
;
15934 if (address_mode
!= mode_64bit
)
15936 else if (vex
.evex
&& !vex
.v
)
15939 if (bytemode
== vex_scalar_mode
)
15941 oappend (names_xmm
[reg
]);
15945 switch (vex
.length
)
15952 case vex_vsib_q_w_dq_mode
:
15953 case vex_vsib_q_w_d_mode
:
15969 names
= names_mask
;
15983 case vex_vsib_q_w_dq_mode
:
15984 case vex_vsib_q_w_d_mode
:
15985 names
= vex
.w
? names_ymm
: names_xmm
;
15994 names
= names_mask
;
15997 /* See PR binutils/20893 for a reproducer. */
16009 oappend (names
[reg
]);
16012 /* Get the VEX immediate byte without moving codep. */
16014 static unsigned char
16015 get_vex_imm8 (int sizeflag
, int opnum
)
16017 int bytes_before_imm
= 0;
16019 if (modrm
.mod
!= 3)
16021 /* There are SIB/displacement bytes. */
16022 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16024 /* 32/64 bit address mode */
16025 int base
= modrm
.rm
;
16027 /* Check SIB byte. */
16030 FETCH_DATA (the_info
, codep
+ 1);
16032 /* When decoding the third source, don't increase
16033 bytes_before_imm as this has already been incremented
16034 by one in OP_E_memory while decoding the second
16037 bytes_before_imm
++;
16040 /* Don't increase bytes_before_imm when decoding the third source,
16041 it has already been incremented by OP_E_memory while decoding
16042 the second source operand. */
16048 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16049 SIB == 5, there is a 4 byte displacement. */
16051 /* No displacement. */
16053 /* Fall through. */
16055 /* 4 byte displacement. */
16056 bytes_before_imm
+= 4;
16059 /* 1 byte displacement. */
16060 bytes_before_imm
++;
16067 /* 16 bit address mode */
16068 /* Don't increase bytes_before_imm when decoding the third source,
16069 it has already been incremented by OP_E_memory while decoding
16070 the second source operand. */
16076 /* When modrm.rm == 6, there is a 2 byte displacement. */
16078 /* No displacement. */
16080 /* Fall through. */
16082 /* 2 byte displacement. */
16083 bytes_before_imm
+= 2;
16086 /* 1 byte displacement: when decoding the third source,
16087 don't increase bytes_before_imm as this has already
16088 been incremented by one in OP_E_memory while decoding
16089 the second source operand. */
16091 bytes_before_imm
++;
16099 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16100 return codep
[bytes_before_imm
];
16104 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16106 const char **names
;
16108 if (reg
== -1 && modrm
.mod
!= 3)
16110 OP_E_memory (bytemode
, sizeflag
);
16122 if (address_mode
!= mode_64bit
)
16126 switch (vex
.length
)
16137 oappend (names
[reg
]);
16141 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16144 static unsigned char vex_imm8
;
16146 if (vex_w_done
== 0)
16150 /* Skip mod/rm byte. */
16154 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16157 reg
= vex_imm8
>> 4;
16159 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16161 else if (vex_w_done
== 1)
16166 reg
= vex_imm8
>> 4;
16168 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16172 /* Output the imm8 directly. */
16173 scratchbuf
[0] = '$';
16174 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16175 oappend_maybe_intel (scratchbuf
);
16176 scratchbuf
[0] = '\0';
16182 OP_Vex_2src (int bytemode
, int sizeflag
)
16184 if (modrm
.mod
== 3)
16186 int reg
= modrm
.rm
;
16190 oappend (names_xmm
[reg
]);
16195 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16197 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16198 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16200 OP_E (bytemode
, sizeflag
);
16205 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16207 if (modrm
.mod
== 3)
16209 /* Skip mod/rm byte. */
16216 unsigned int reg
= vex
.register_specifier
;
16218 if (address_mode
!= mode_64bit
)
16220 oappend (names_xmm
[reg
]);
16223 OP_Vex_2src (bytemode
, sizeflag
);
16227 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16230 OP_Vex_2src (bytemode
, sizeflag
);
16233 unsigned int reg
= vex
.register_specifier
;
16235 if (address_mode
!= mode_64bit
)
16237 oappend (names_xmm
[reg
]);
16242 OP_EX_VexW (int bytemode
, int sizeflag
)
16248 /* Skip mod/rm byte. */
16253 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16258 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16261 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16269 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16272 const char **names
;
16274 FETCH_DATA (the_info
, codep
+ 1);
16277 if (bytemode
!= x_mode
)
16281 if (address_mode
!= mode_64bit
)
16284 switch (vex
.length
)
16295 oappend (names
[reg
]);
16299 OP_XMM_VexW (int bytemode
, int sizeflag
)
16301 /* Turn off the REX.W bit since it is used for swapping operands
16304 OP_XMM (bytemode
, sizeflag
);
16308 OP_EX_Vex (int bytemode
, int sizeflag
)
16310 if (modrm
.mod
!= 3)
16312 if (vex
.register_specifier
!= 0)
16316 OP_EX (bytemode
, sizeflag
);
16320 OP_XMM_Vex (int bytemode
, int sizeflag
)
16322 if (modrm
.mod
!= 3)
16324 if (vex
.register_specifier
!= 0)
16328 OP_XMM (bytemode
, sizeflag
);
16331 static struct op vex_cmp_op
[] =
16333 { STRING_COMMA_LEN ("eq") },
16334 { STRING_COMMA_LEN ("lt") },
16335 { STRING_COMMA_LEN ("le") },
16336 { STRING_COMMA_LEN ("unord") },
16337 { STRING_COMMA_LEN ("neq") },
16338 { STRING_COMMA_LEN ("nlt") },
16339 { STRING_COMMA_LEN ("nle") },
16340 { STRING_COMMA_LEN ("ord") },
16341 { STRING_COMMA_LEN ("eq_uq") },
16342 { STRING_COMMA_LEN ("nge") },
16343 { STRING_COMMA_LEN ("ngt") },
16344 { STRING_COMMA_LEN ("false") },
16345 { STRING_COMMA_LEN ("neq_oq") },
16346 { STRING_COMMA_LEN ("ge") },
16347 { STRING_COMMA_LEN ("gt") },
16348 { STRING_COMMA_LEN ("true") },
16349 { STRING_COMMA_LEN ("eq_os") },
16350 { STRING_COMMA_LEN ("lt_oq") },
16351 { STRING_COMMA_LEN ("le_oq") },
16352 { STRING_COMMA_LEN ("unord_s") },
16353 { STRING_COMMA_LEN ("neq_us") },
16354 { STRING_COMMA_LEN ("nlt_uq") },
16355 { STRING_COMMA_LEN ("nle_uq") },
16356 { STRING_COMMA_LEN ("ord_s") },
16357 { STRING_COMMA_LEN ("eq_us") },
16358 { STRING_COMMA_LEN ("nge_uq") },
16359 { STRING_COMMA_LEN ("ngt_uq") },
16360 { STRING_COMMA_LEN ("false_os") },
16361 { STRING_COMMA_LEN ("neq_os") },
16362 { STRING_COMMA_LEN ("ge_oq") },
16363 { STRING_COMMA_LEN ("gt_oq") },
16364 { STRING_COMMA_LEN ("true_us") },
16368 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16370 unsigned int cmp_type
;
16372 FETCH_DATA (the_info
, codep
+ 1);
16373 cmp_type
= *codep
++ & 0xff;
16374 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16377 char *p
= mnemonicendp
- 2;
16381 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16382 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16386 /* We have a reserved extension byte. Output it directly. */
16387 scratchbuf
[0] = '$';
16388 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16389 oappend_maybe_intel (scratchbuf
);
16390 scratchbuf
[0] = '\0';
16395 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16396 int sizeflag ATTRIBUTE_UNUSED
)
16398 unsigned int cmp_type
;
16403 FETCH_DATA (the_info
, codep
+ 1);
16404 cmp_type
= *codep
++ & 0xff;
16405 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16406 If it's the case, print suffix, otherwise - print the immediate. */
16407 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16412 char *p
= mnemonicendp
- 2;
16414 /* vpcmp* can have both one- and two-lettered suffix. */
16428 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16429 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16433 /* We have a reserved extension byte. Output it directly. */
16434 scratchbuf
[0] = '$';
16435 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16436 oappend_maybe_intel (scratchbuf
);
16437 scratchbuf
[0] = '\0';
16441 static const struct op xop_cmp_op
[] =
16443 { STRING_COMMA_LEN ("lt") },
16444 { STRING_COMMA_LEN ("le") },
16445 { STRING_COMMA_LEN ("gt") },
16446 { STRING_COMMA_LEN ("ge") },
16447 { STRING_COMMA_LEN ("eq") },
16448 { STRING_COMMA_LEN ("neq") },
16449 { STRING_COMMA_LEN ("false") },
16450 { STRING_COMMA_LEN ("true") }
16454 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16455 int sizeflag ATTRIBUTE_UNUSED
)
16457 unsigned int cmp_type
;
16459 FETCH_DATA (the_info
, codep
+ 1);
16460 cmp_type
= *codep
++ & 0xff;
16461 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16464 char *p
= mnemonicendp
- 2;
16466 /* vpcom* can have both one- and two-lettered suffix. */
16480 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16481 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16485 /* We have a reserved extension byte. Output it directly. */
16486 scratchbuf
[0] = '$';
16487 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16488 oappend_maybe_intel (scratchbuf
);
16489 scratchbuf
[0] = '\0';
16493 static const struct op pclmul_op
[] =
16495 { STRING_COMMA_LEN ("lql") },
16496 { STRING_COMMA_LEN ("hql") },
16497 { STRING_COMMA_LEN ("lqh") },
16498 { STRING_COMMA_LEN ("hqh") }
16502 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16503 int sizeflag ATTRIBUTE_UNUSED
)
16505 unsigned int pclmul_type
;
16507 FETCH_DATA (the_info
, codep
+ 1);
16508 pclmul_type
= *codep
++ & 0xff;
16509 switch (pclmul_type
)
16520 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16523 char *p
= mnemonicendp
- 3;
16528 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16529 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16533 /* We have a reserved extension byte. Output it directly. */
16534 scratchbuf
[0] = '$';
16535 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16536 oappend_maybe_intel (scratchbuf
);
16537 scratchbuf
[0] = '\0';
16542 MOVBE_Fixup (int bytemode
, int sizeflag
)
16544 /* Add proper suffix to "movbe". */
16545 char *p
= mnemonicendp
;
16554 if (sizeflag
& SUFFIX_ALWAYS
)
16560 if (sizeflag
& DFLAG
)
16564 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16569 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16576 OP_M (bytemode
, sizeflag
);
16580 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16583 const char **names
;
16585 /* Skip mod/rm byte. */
16599 oappend (names
[reg
]);
16603 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16605 const char **names
;
16606 unsigned int reg
= vex
.register_specifier
;
16613 if (address_mode
!= mode_64bit
)
16615 oappend (names
[reg
]);
16619 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16622 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16626 if ((rex
& REX_R
) != 0 || !vex
.r
)
16632 oappend (names_mask
[modrm
.reg
]);
16636 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16639 || (bytemode
!= evex_rounding_mode
16640 && bytemode
!= evex_rounding_64_mode
16641 && bytemode
!= evex_sae_mode
))
16643 if (modrm
.mod
== 3 && vex
.b
)
16646 case evex_rounding_64_mode
:
16647 if (address_mode
!= mode_64bit
)
16652 /* Fall through. */
16653 case evex_rounding_mode
:
16654 oappend (names_rounding
[vex
.ll
]);
16656 case evex_sae_mode
: