opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2015 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void OP_LWPCB_E (int, int);
 120 static void OP_LWP_E (int, int);
 121 static void OP_Vex_2src_1 (int, int);
 122 static void OP_Vex_2src_2 (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125
 126 static void OP_Mask (int, int);
 127
 128 struct dis_private {
 129   /* Points to first byte not fetched.  */
 130   bfd_byte *max_fetched;
 131   bfd_byte the_buffer[MAX_MNEM_SIZE];
 132   bfd_vma insn_start;
 133   int orig_sizeflag;
 134   OPCODES_SIGJMP_BUF bailout;
 135 };
 136
 137 enum address_mode
 138 {
 139   mode_16bit,
 140   mode_32bit,
 141   mode_64bit
 142 };
 143
 144 enum address_mode address_mode;
 145
 146 /* Flags for the prefixes for the current instruction.  See below.  */
 147 static int prefixes;
 148
 149 /* REX prefix the current instruction.  See below.  */
 150 static int rex;
 151 /* Bits of REX we've already used.  */
 152 static int rex_used;
 153 /* REX bits in original REX prefix ignored.  */
 154 static int rex_ignored;
 155 /* Mark parts used in the REX prefix.  When we are testing for
 156    empty prefix (for 8bit register REX extension), just mask it
 157    out.  Otherwise test for REX bit is excuse for existence of REX
 158    only in case value is nonzero.  */
 159 #define USED_REX(value)                                 \
 160   {                                                     \
 161     if (value)                                          \
 162       {                                                 \
 163         if ((rex & value))                              \
 164           rex_used |= (value) | REX_OPCODE;             \
 165       }                                                 \
 166     else                                                \
 167       rex_used |= REX_OPCODE;                           \
 168   }
 169
 170 /* Flags for prefixes which we somehow handled when printing the
 171    current instruction.  */
 172 static int used_prefixes;
 173
 174 /* Flags stored in PREFIXES.  */
 175 #define PREFIX_REPZ 1
 176 #define PREFIX_REPNZ 2
 177 #define PREFIX_LOCK 4
 178 #define PREFIX_CS 8
 179 #define PREFIX_SS 0x10
 180 #define PREFIX_DS 0x20
 181 #define PREFIX_ES 0x40
 182 #define PREFIX_FS 0x80
 183 #define PREFIX_GS 0x100
 184 #define PREFIX_DATA 0x200
 185 #define PREFIX_ADDR 0x400
 186 #define PREFIX_FWAIT 0x800
 187
 188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 189    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 190    on error.  */
 191 #define FETCH_DATA(info, addr) \
 192   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 193    ? 1 : fetch_data ((info), (addr)))
 194
 195 static int
 196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 197 {
 198   int status;
 199   struct dis_private *priv = (struct dis_private *) info->private_data;
 200   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 201
 202   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 203     status = (*info->read_memory_func) (start,
 204                                         priv->max_fetched,
 205                                         addr - priv->max_fetched,
 206                                         info);
 207   else
 208     status = -1;
 209   if (status != 0)
 210     {
 211       /* If we did manage to read at least one byte, then
 212          print_insn_i386 will do something sensible.  Otherwise, print
 213          an error.  We do that here because this is where we know
 214          STATUS.  */
 215       if (priv->max_fetched == priv->the_buffer)
 216         (*info->memory_error_func) (status, start, info);
 217       OPCODES_SIGLONGJMP (priv->bailout, 1);
 218     }
 219   else
 220     priv->max_fetched = addr;
 221   return 1;
 222 }
 223
 224 /* Possible values for prefix requirement.  */
 225 #define PREFIX_MANDATORY_REPZ   PREFIX_REPZ
 226 #define PREFIX_MANDATORY_REPNZ  PREFIX_REPNZ
 227 #define PREFIX_MANDATORY_DATA   PREFIX_DATA
 228 #define PREFIX_MANDATORY_ADDR   PREFIX_ADDR
 229 #define PREFIX_MANDATORY_LOCK   PREFIX_LOCK
 230 #define PREFIX_UD_SHIFT         16
 231 #define PREFIX_UD_REPZ          (PREFIX_MANDATORY_REPZ << PREFIX_UD_SHIFT)
 232 #define PREFIX_UD_REPNZ         (PREFIX_MANDATORY_REPNZ << PREFIX_UD_SHIFT)
 233 #define PREFIX_UD_DATA          (PREFIX_MANDATORY_DATA << PREFIX_UD_SHIFT)
 234 #define PREFIX_UD_ADDR          (PREFIX_MANDATORY_ADDR << PREFIX_UD_SHIFT)
 235 #define PREFIX_UD_LOCK          (PREFIX_MANDATORY_LOCK << PREFIX_UD_SHIFT)
 236
 237 #define PREFIX_MANDATORY        (PREFIX_MANDATORY_REPZ \
 238                                  | PREFIX_MANDATORY_REPNZ \
 239                                  | PREFIX_MANDATORY_DATA)
 240
 241 #define XX { NULL, 0 }
 242 #define Bad_Opcode NULL, { { NULL, 0 } }, PREFIX_MANDATORY
 243
 244 #define Eb { OP_E, b_mode }
 245 #define Ebnd { OP_E, bnd_mode }
 246 #define EbS { OP_E, b_swap_mode }
 247 #define Ev { OP_E, v_mode }
 248 #define Ev_bnd { OP_E, v_bnd_mode }
 249 #define EvS { OP_E, v_swap_mode }
 250 #define Ed { OP_E, d_mode }
 251 #define Edq { OP_E, dq_mode }
 252 #define Edqw { OP_E, dqw_mode }
 253 #define EdqwS { OP_E, dqw_swap_mode }
 254 #define Edqb { OP_E, dqb_mode }
 255 #define Edb { OP_E, db_mode }
 256 #define Edw { OP_E, dw_mode }
 257 #define Edqd { OP_E, dqd_mode }
 258 #define Eq { OP_E, q_mode }
 259 #define indirEv { OP_indirE, stack_v_mode }
 260 #define indirEp { OP_indirE, f_mode }
 261 #define stackEv { OP_E, stack_v_mode }
 262 #define Em { OP_E, m_mode }
 263 #define Ew { OP_E, w_mode }
 264 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 265 #define Ma { OP_M, a_mode }
 266 #define Mb { OP_M, b_mode }
 267 #define Md { OP_M, d_mode }
 268 #define Mo { OP_M, o_mode }
 269 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 270 #define Mq { OP_M, q_mode }
 271 #define Mx { OP_M, x_mode }
 272 #define Mxmm { OP_M, xmm_mode }
 273 #define Gb { OP_G, b_mode }
 274 #define Gbnd { OP_G, bnd_mode }
 275 #define Gv { OP_G, v_mode }
 276 #define Gd { OP_G, d_mode }
 277 #define Gdq { OP_G, dq_mode }
 278 #define Gm { OP_G, m_mode }
 279 #define Gw { OP_G, w_mode }
 280 #define Rd { OP_R, d_mode }
 281 #define Rdq { OP_R, dq_mode }
 282 #define Rm { OP_R, m_mode }
 283 #define Ib { OP_I, b_mode }
 284 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 285 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 286 #define Iv { OP_I, v_mode }
 287 #define sIv { OP_sI, v_mode }
 288 #define Iq { OP_I, q_mode }
 289 #define Iv64 { OP_I64, v_mode }
 290 #define Iw { OP_I, w_mode }
 291 #define I1 { OP_I, const_1_mode }
 292 #define Jb { OP_J, b_mode }
 293 #define Jv { OP_J, v_mode }
 294 #define Cm { OP_C, m_mode }
 295 #define Dm { OP_D, m_mode }
 296 #define Td { OP_T, d_mode }
 297 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 298
 299 #define RMeAX { OP_REG, eAX_reg }
 300 #define RMeBX { OP_REG, eBX_reg }
 301 #define RMeCX { OP_REG, eCX_reg }
 302 #define RMeDX { OP_REG, eDX_reg }
 303 #define RMeSP { OP_REG, eSP_reg }
 304 #define RMeBP { OP_REG, eBP_reg }
 305 #define RMeSI { OP_REG, eSI_reg }
 306 #define RMeDI { OP_REG, eDI_reg }
 307 #define RMrAX { OP_REG, rAX_reg }
 308 #define RMrBX { OP_REG, rBX_reg }
 309 #define RMrCX { OP_REG, rCX_reg }
 310 #define RMrDX { OP_REG, rDX_reg }
 311 #define RMrSP { OP_REG, rSP_reg }
 312 #define RMrBP { OP_REG, rBP_reg }
 313 #define RMrSI { OP_REG, rSI_reg }
 314 #define RMrDI { OP_REG, rDI_reg }
 315 #define RMAL { OP_REG, al_reg }
 316 #define RMCL { OP_REG, cl_reg }
 317 #define RMDL { OP_REG, dl_reg }
 318 #define RMBL { OP_REG, bl_reg }
 319 #define RMAH { OP_REG, ah_reg }
 320 #define RMCH { OP_REG, ch_reg }
 321 #define RMDH { OP_REG, dh_reg }
 322 #define RMBH { OP_REG, bh_reg }
 323 #define RMAX { OP_REG, ax_reg }
 324 #define RMDX { OP_REG, dx_reg }
 325
 326 #define eAX { OP_IMREG, eAX_reg }
 327 #define eBX { OP_IMREG, eBX_reg }
 328 #define eCX { OP_IMREG, eCX_reg }
 329 #define eDX { OP_IMREG, eDX_reg }
 330 #define eSP { OP_IMREG, eSP_reg }
 331 #define eBP { OP_IMREG, eBP_reg }
 332 #define eSI { OP_IMREG, eSI_reg }
 333 #define eDI { OP_IMREG, eDI_reg }
 334 #define AL { OP_IMREG, al_reg }
 335 #define CL { OP_IMREG, cl_reg }
 336 #define DL { OP_IMREG, dl_reg }
 337 #define BL { OP_IMREG, bl_reg }
 338 #define AH { OP_IMREG, ah_reg }
 339 #define CH { OP_IMREG, ch_reg }
 340 #define DH { OP_IMREG, dh_reg }
 341 #define BH { OP_IMREG, bh_reg }
 342 #define AX { OP_IMREG, ax_reg }
 343 #define DX { OP_IMREG, dx_reg }
 344 #define zAX { OP_IMREG, z_mode_ax_reg }
 345 #define indirDX { OP_IMREG, indir_dx_reg }
 346
 347 #define Sw { OP_SEG, w_mode }
 348 #define Sv { OP_SEG, v_mode }
 349 #define Ap { OP_DIR, 0 }
 350 #define Ob { OP_OFF64, b_mode }
 351 #define Ov { OP_OFF64, v_mode }
 352 #define Xb { OP_DSreg, eSI_reg }
 353 #define Xv { OP_DSreg, eSI_reg }
 354 #define Xz { OP_DSreg, eSI_reg }
 355 #define Yb { OP_ESreg, eDI_reg }
 356 #define Yv { OP_ESreg, eDI_reg }
 357 #define DSBX { OP_DSreg, eBX_reg }
 358
 359 #define es { OP_REG, es_reg }
 360 #define ss { OP_REG, ss_reg }
 361 #define cs { OP_REG, cs_reg }
 362 #define ds { OP_REG, ds_reg }
 363 #define fs { OP_REG, fs_reg }
 364 #define gs { OP_REG, gs_reg }
 365
 366 #define MX { OP_MMX, 0 }
 367 #define XM { OP_XMM, 0 }
 368 #define XMScalar { OP_XMM, scalar_mode }
 369 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 370 #define XMM { OP_XMM, xmm_mode }
 371 #define XMxmmq { OP_XMM, xmmq_mode }
 372 #define EM { OP_EM, v_mode }
 373 #define EMS { OP_EM, v_swap_mode }
 374 #define EMd { OP_EM, d_mode }
 375 #define EMx { OP_EM, x_mode }
 376 #define EXw { OP_EX, w_mode }
 377 #define EXd { OP_EX, d_mode }
 378 #define EXdScalar { OP_EX, d_scalar_mode }
 379 #define EXdS { OP_EX, d_swap_mode }
 380 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 381 #define EXq { OP_EX, q_mode }
 382 #define EXqScalar { OP_EX, q_scalar_mode }
 383 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 384 #define EXqS { OP_EX, q_swap_mode }
 385 #define EXx { OP_EX, x_mode }
 386 #define EXxS { OP_EX, x_swap_mode }
 387 #define EXxmm { OP_EX, xmm_mode }
 388 #define EXymm { OP_EX, ymm_mode }
 389 #define EXxmmq { OP_EX, xmmq_mode }
 390 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 391 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 392 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 393 #define EXxmm_md { OP_EX, xmm_md_mode }
 394 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 395 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 396 #define EXxmmdw { OP_EX, xmmdw_mode }
 397 #define EXxmmqd { OP_EX, xmmqd_mode }
 398 #define EXymmq { OP_EX, ymmq_mode }
 399 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 400 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 401 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 402 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 403 #define MS { OP_MS, v_mode }
 404 #define XS { OP_XS, v_mode }
 405 #define EMCq { OP_EMC, q_mode }
 406 #define MXC { OP_MXC, 0 }
 407 #define OPSUF { OP_3DNowSuffix, 0 }
 408 #define CMP { CMP_Fixup, 0 }
 409 #define XMM0 { XMM_Fixup, 0 }
 410 #define FXSAVE { FXSAVE_Fixup, 0 }
 411 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 412 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 413
 414 #define Vex { OP_VEX, vex_mode }
 415 #define VexScalar { OP_VEX, vex_scalar_mode }
 416 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 417 #define Vex128 { OP_VEX, vex128_mode }
 418 #define Vex256 { OP_VEX, vex256_mode }
 419 #define VexGdq { OP_VEX, dq_mode }
 420 #define VexI4 { VEXI4_Fixup, 0}
 421 #define EXdVex { OP_EX_Vex, d_mode }
 422 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 423 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 424 #define EXqVex { OP_EX_Vex, q_mode }
 425 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 426 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 427 #define EXVexW { OP_EX_VexW, x_mode }
 428 #define EXdVexW { OP_EX_VexW, d_mode }
 429 #define EXqVexW { OP_EX_VexW, q_mode }
 430 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 431 #define XMVex { OP_XMM_Vex, 0 }
 432 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 433 #define XMVexW { OP_XMM_VexW, 0 }
 434 #define XMVexI4 { OP_REG_VexI4, x_mode }
 435 #define PCLMUL { PCLMUL_Fixup, 0 }
 436 #define VZERO { VZERO_Fixup, 0 }
 437 #define VCMP { VCMP_Fixup, 0 }
 438 #define VPCMP { VPCMP_Fixup, 0 }
 439
 440 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 441 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 442
 443 #define XMask { OP_Mask, mask_mode }
 444 #define MaskG { OP_G, mask_mode }
 445 #define MaskE { OP_E, mask_mode }
 446 #define MaskBDE { OP_E, mask_bd_mode }
 447 #define MaskR { OP_R, mask_mode }
 448 #define MaskVex { OP_VEX, mask_mode }
 449
 450 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 451 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 452 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 453 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 454
 455 /* Used handle "rep" prefix for string instructions.  */
 456 #define Xbr { REP_Fixup, eSI_reg }
 457 #define Xvr { REP_Fixup, eSI_reg }
 458 #define Ybr { REP_Fixup, eDI_reg }
 459 #define Yvr { REP_Fixup, eDI_reg }
 460 #define Yzr { REP_Fixup, eDI_reg }
 461 #define indirDXr { REP_Fixup, indir_dx_reg }
 462 #define ALr { REP_Fixup, al_reg }
 463 #define eAXr { REP_Fixup, eAX_reg }
 464
 465 /* Used handle HLE prefix for lockable instructions.  */
 466 #define Ebh1 { HLE_Fixup1, b_mode }
 467 #define Evh1 { HLE_Fixup1, v_mode }
 468 #define Ebh2 { HLE_Fixup2, b_mode }
 469 #define Evh2 { HLE_Fixup2, v_mode }
 470 #define Ebh3 { HLE_Fixup3, b_mode }
 471 #define Evh3 { HLE_Fixup3, v_mode }
 472
 473 #define BND { BND_Fixup, 0 }
 474
 475 #define cond_jump_flag { NULL, cond_jump_mode }
 476 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 477
 478 /* bits in sizeflag */
 479 #define SUFFIX_ALWAYS 4
 480 #define AFLAG 2
 481 #define DFLAG 1
 482
 483 enum
 484 {
 485   /* byte operand */
 486   b_mode = 1,
 487   /* byte operand with operand swapped */
 488   b_swap_mode,
 489   /* byte operand, sign extend like 'T' suffix */
 490   b_T_mode,
 491   /* operand size depends on prefixes */
 492   v_mode,
 493   /* operand size depends on prefixes with operand swapped */
 494   v_swap_mode,
 495   /* word operand */
 496   w_mode,
 497   /* double word operand  */
 498   d_mode,
 499   /* double word operand with operand swapped */
 500   d_swap_mode,
 501   /* quad word operand */
 502   q_mode,
 503   /* quad word operand with operand swapped */
 504   q_swap_mode,
 505   /* ten-byte operand */
 506   t_mode,
 507   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 508      broadcast enabled.  */
 509   x_mode,
 510   /* Similar to x_mode, but with different EVEX mem shifts.  */
 511   evex_x_gscat_mode,
 512   /* Similar to x_mode, but with disabled broadcast.  */
 513   evex_x_nobcst_mode,
 514   /* Similar to x_mode, but with operands swapped and disabled broadcast
 515      in EVEX.  */
 516   x_swap_mode,
 517   /* 16-byte XMM operand */
 518   xmm_mode,
 519   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 520      memory operand (depending on vector length).  Broadcast isn't
 521      allowed.  */
 522   xmmq_mode,
 523   /* Same as xmmq_mode, but broadcast is allowed.  */
 524   evex_half_bcst_xmmq_mode,
 525   /* XMM register or byte memory operand */
 526   xmm_mb_mode,
 527   /* XMM register or word memory operand */
 528   xmm_mw_mode,
 529   /* XMM register or double word memory operand */
 530   xmm_md_mode,
 531   /* XMM register or quad word memory operand */
 532   xmm_mq_mode,
 533   /* XMM register or double/quad word memory operand, depending on
 534      VEX.W.  */
 535   xmm_mdq_mode,
 536   /* 16-byte XMM, word, double word or quad word operand.  */
 537   xmmdw_mode,
 538   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 539   xmmqd_mode,
 540   /* 32-byte YMM operand */
 541   ymm_mode,
 542   /* quad word, ymmword or zmmword memory operand.  */
 543   ymmq_mode,
 544   /* 32-byte YMM or 16-byte word operand */
 545   ymmxmm_mode,
 546   /* d_mode in 32bit, q_mode in 64bit mode.  */
 547   m_mode,
 548   /* pair of v_mode operands */
 549   a_mode,
 550   cond_jump_mode,
 551   loop_jcxz_mode,
 552   v_bnd_mode,
 553   /* operand size depends on REX prefixes.  */
 554   dq_mode,
 555   /* registers like dq_mode, memory like w_mode.  */
 556   dqw_mode,
 557   dqw_swap_mode,
 558   bnd_mode,
 559   /* 4- or 6-byte pointer operand */
 560   f_mode,
 561   const_1_mode,
 562   /* v_mode for stack-related opcodes.  */
 563   stack_v_mode,
 564   /* non-quad operand size depends on prefixes */
 565   z_mode,
 566   /* 16-byte operand */
 567   o_mode,
 568   /* registers like dq_mode, memory like b_mode.  */
 569   dqb_mode,
 570   /* registers like d_mode, memory like b_mode.  */
 571   db_mode,
 572   /* registers like d_mode, memory like w_mode.  */
 573   dw_mode,
 574   /* registers like dq_mode, memory like d_mode.  */
 575   dqd_mode,
 576   /* normal vex mode */
 577   vex_mode,
 578   /* 128bit vex mode */
 579   vex128_mode,
 580   /* 256bit vex mode */
 581   vex256_mode,
 582   /* operand size depends on the VEX.W bit.  */
 583   vex_w_dq_mode,
 584
 585   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 586   vex_vsib_d_w_dq_mode,
 587   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 588   vex_vsib_d_w_d_mode,
 589   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 590   vex_vsib_q_w_dq_mode,
 591   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 592   vex_vsib_q_w_d_mode,
 593
 594   /* scalar, ignore vector length.  */
 595   scalar_mode,
 596   /* like d_mode, ignore vector length.  */
 597   d_scalar_mode,
 598   /* like d_swap_mode, ignore vector length.  */
 599   d_scalar_swap_mode,
 600   /* like q_mode, ignore vector length.  */
 601   q_scalar_mode,
 602   /* like q_swap_mode, ignore vector length.  */
 603   q_scalar_swap_mode,
 604   /* like vex_mode, ignore vector length.  */
 605   vex_scalar_mode,
 606   /* like vex_w_dq_mode, ignore vector length.  */
 607   vex_scalar_w_dq_mode,
 608
 609   /* Static rounding.  */
 610   evex_rounding_mode,
 611   /* Supress all exceptions.  */
 612   evex_sae_mode,
 613
 614   /* Mask register operand.  */
 615   mask_mode,
 616   /* Mask register operand.  */
 617   mask_bd_mode,
 618
 619   es_reg,
 620   cs_reg,
 621   ss_reg,
 622   ds_reg,
 623   fs_reg,
 624   gs_reg,
 625
 626   eAX_reg,
 627   eCX_reg,
 628   eDX_reg,
 629   eBX_reg,
 630   eSP_reg,
 631   eBP_reg,
 632   eSI_reg,
 633   eDI_reg,
 634
 635   al_reg,
 636   cl_reg,
 637   dl_reg,
 638   bl_reg,
 639   ah_reg,
 640   ch_reg,
 641   dh_reg,
 642   bh_reg,
 643
 644   ax_reg,
 645   cx_reg,
 646   dx_reg,
 647   bx_reg,
 648   sp_reg,
 649   bp_reg,
 650   si_reg,
 651   di_reg,
 652
 653   rAX_reg,
 654   rCX_reg,
 655   rDX_reg,
 656   rBX_reg,
 657   rSP_reg,
 658   rBP_reg,
 659   rSI_reg,
 660   rDI_reg,
 661
 662   z_mode_ax_reg,
 663   indir_dx_reg
 664 };
 665
 666 enum
 667 {
 668   FLOATCODE = 1,
 669   USE_REG_TABLE,
 670   USE_MOD_TABLE,
 671   USE_RM_TABLE,
 672   USE_PREFIX_TABLE,
 673   USE_X86_64_TABLE,
 674   USE_3BYTE_TABLE,
 675   USE_XOP_8F_TABLE,
 676   USE_VEX_C4_TABLE,
 677   USE_VEX_C5_TABLE,
 678   USE_VEX_LEN_TABLE,
 679   USE_VEX_W_TABLE,
 680   USE_EVEX_TABLE
 681 };
 682
 683 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 684
 685 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 686 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 687 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 688 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 689 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 690 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 691 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 692 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 693 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 694 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 695 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 696 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 697 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 698 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 699 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 700
 701 enum
 702 {
 703   REG_80 = 0,
 704   REG_81,
 705   REG_82,
 706   REG_8F,
 707   REG_C0,
 708   REG_C1,
 709   REG_C6,
 710   REG_C7,
 711   REG_D0,
 712   REG_D1,
 713   REG_D2,
 714   REG_D3,
 715   REG_F6,
 716   REG_F7,
 717   REG_FE,
 718   REG_FF,
 719   REG_0F00,
 720   REG_0F01,
 721   REG_0F0D,
 722   REG_0F18,
 723   REG_0F71,
 724   REG_0F72,
 725   REG_0F73,
 726   REG_0FA6,
 727   REG_0FA7,
 728   REG_0FAE,
 729   REG_0FBA,
 730   REG_0FC7,
 731   REG_VEX_0F71,
 732   REG_VEX_0F72,
 733   REG_VEX_0F73,
 734   REG_VEX_0FAE,
 735   REG_VEX_0F38F3,
 736   REG_XOP_LWPCB,
 737   REG_XOP_LWP,
 738   REG_XOP_TBM_01,
 739   REG_XOP_TBM_02,
 740
 741   REG_EVEX_0F71,
 742   REG_EVEX_0F72,
 743   REG_EVEX_0F73,
 744   REG_EVEX_0F38C6,
 745   REG_EVEX_0F38C7
 746 };
 747
 748 enum
 749 {
 750   MOD_8D = 0,
 751   MOD_C6_REG_7,
 752   MOD_C7_REG_7,
 753   MOD_FF_REG_3,
 754   MOD_FF_REG_5,
 755   MOD_0F01_REG_0,
 756   MOD_0F01_REG_1,
 757   MOD_0F01_REG_2,
 758   MOD_0F01_REG_3,
 759   MOD_0F01_REG_7,
 760   MOD_0F12_PREFIX_0,
 761   MOD_0F13,
 762   MOD_0F16_PREFIX_0,
 763   MOD_0F17,
 764   MOD_0F18_REG_0,
 765   MOD_0F18_REG_1,
 766   MOD_0F18_REG_2,
 767   MOD_0F18_REG_3,
 768   MOD_0F18_REG_4,
 769   MOD_0F18_REG_5,
 770   MOD_0F18_REG_6,
 771   MOD_0F18_REG_7,
 772   MOD_0F1A_PREFIX_0,
 773   MOD_0F1B_PREFIX_0,
 774   MOD_0F1B_PREFIX_1,
 775   MOD_0F24,
 776   MOD_0F26,
 777   MOD_0F2B_PREFIX_0,
 778   MOD_0F2B_PREFIX_1,
 779   MOD_0F2B_PREFIX_2,
 780   MOD_0F2B_PREFIX_3,
 781   MOD_0F51,
 782   MOD_0F71_REG_2,
 783   MOD_0F71_REG_4,
 784   MOD_0F71_REG_6,
 785   MOD_0F72_REG_2,
 786   MOD_0F72_REG_4,
 787   MOD_0F72_REG_6,
 788   MOD_0F73_REG_2,
 789   MOD_0F73_REG_3,
 790   MOD_0F73_REG_6,
 791   MOD_0F73_REG_7,
 792   MOD_0FAE_REG_0,
 793   MOD_0FAE_REG_1,
 794   MOD_0FAE_REG_2,
 795   MOD_0FAE_REG_3,
 796   MOD_0FAE_REG_4,
 797   MOD_0FAE_REG_5,
 798   MOD_0FAE_REG_6,
 799   MOD_0FAE_REG_7,
 800   MOD_0FB2,
 801   MOD_0FB4,
 802   MOD_0FB5,
 803   MOD_0FC7_REG_3,
 804   MOD_0FC7_REG_4,
 805   MOD_0FC7_REG_5,
 806   MOD_0FC7_REG_6,
 807   MOD_0FC7_REG_7,
 808   MOD_0FD7,
 809   MOD_0FE7_PREFIX_2,
 810   MOD_0FF0_PREFIX_3,
 811   MOD_0F382A_PREFIX_2,
 812   MOD_62_32BIT,
 813   MOD_C4_32BIT,
 814   MOD_C5_32BIT,
 815   MOD_VEX_0F12_PREFIX_0,
 816   MOD_VEX_0F13,
 817   MOD_VEX_0F16_PREFIX_0,
 818   MOD_VEX_0F17,
 819   MOD_VEX_0F2B,
 820   MOD_VEX_0F50,
 821   MOD_VEX_0F71_REG_2,
 822   MOD_VEX_0F71_REG_4,
 823   MOD_VEX_0F71_REG_6,
 824   MOD_VEX_0F72_REG_2,
 825   MOD_VEX_0F72_REG_4,
 826   MOD_VEX_0F72_REG_6,
 827   MOD_VEX_0F73_REG_2,
 828   MOD_VEX_0F73_REG_3,
 829   MOD_VEX_0F73_REG_6,
 830   MOD_VEX_0F73_REG_7,
 831   MOD_VEX_0FAE_REG_2,
 832   MOD_VEX_0FAE_REG_3,
 833   MOD_VEX_0FD7_PREFIX_2,
 834   MOD_VEX_0FE7_PREFIX_2,
 835   MOD_VEX_0FF0_PREFIX_3,
 836   MOD_VEX_0F381A_PREFIX_2,
 837   MOD_VEX_0F382A_PREFIX_2,
 838   MOD_VEX_0F382C_PREFIX_2,
 839   MOD_VEX_0F382D_PREFIX_2,
 840   MOD_VEX_0F382E_PREFIX_2,
 841   MOD_VEX_0F382F_PREFIX_2,
 842   MOD_VEX_0F385A_PREFIX_2,
 843   MOD_VEX_0F388C_PREFIX_2,
 844   MOD_VEX_0F388E_PREFIX_2,
 845
 846   MOD_EVEX_0F10_PREFIX_1,
 847   MOD_EVEX_0F10_PREFIX_3,
 848   MOD_EVEX_0F11_PREFIX_1,
 849   MOD_EVEX_0F11_PREFIX_3,
 850   MOD_EVEX_0F12_PREFIX_0,
 851   MOD_EVEX_0F16_PREFIX_0,
 852   MOD_EVEX_0F38C6_REG_1,
 853   MOD_EVEX_0F38C6_REG_2,
 854   MOD_EVEX_0F38C6_REG_5,
 855   MOD_EVEX_0F38C6_REG_6,
 856   MOD_EVEX_0F38C7_REG_1,
 857   MOD_EVEX_0F38C7_REG_2,
 858   MOD_EVEX_0F38C7_REG_5,
 859   MOD_EVEX_0F38C7_REG_6
 860 };
 861
 862 enum
 863 {
 864   RM_C6_REG_7 = 0,
 865   RM_C7_REG_7,
 866   RM_0F01_REG_0,
 867   RM_0F01_REG_1,
 868   RM_0F01_REG_2,
 869   RM_0F01_REG_3,
 870   RM_0F01_REG_7,
 871   RM_0FAE_REG_5,
 872   RM_0FAE_REG_6,
 873   RM_0FAE_REG_7
 874 };
 875
 876 enum
 877 {
 878   PREFIX_90 = 0,
 879   PREFIX_0F10,
 880   PREFIX_0F11,
 881   PREFIX_0F12,
 882   PREFIX_0F16,
 883   PREFIX_0F1A,
 884   PREFIX_0F1B,
 885   PREFIX_0F2A,
 886   PREFIX_0F2B,
 887   PREFIX_0F2C,
 888   PREFIX_0F2D,
 889   PREFIX_0F2E,
 890   PREFIX_0F2F,
 891   PREFIX_0F51,
 892   PREFIX_0F52,
 893   PREFIX_0F53,
 894   PREFIX_0F58,
 895   PREFIX_0F59,
 896   PREFIX_0F5A,
 897   PREFIX_0F5B,
 898   PREFIX_0F5C,
 899   PREFIX_0F5D,
 900   PREFIX_0F5E,
 901   PREFIX_0F5F,
 902   PREFIX_0F60,
 903   PREFIX_0F61,
 904   PREFIX_0F62,
 905   PREFIX_0F6C,
 906   PREFIX_0F6D,
 907   PREFIX_0F6F,
 908   PREFIX_0F70,
 909   PREFIX_0F73_REG_3,
 910   PREFIX_0F73_REG_7,
 911   PREFIX_0F78,
 912   PREFIX_0F79,
 913   PREFIX_0F7C,
 914   PREFIX_0F7D,
 915   PREFIX_0F7E,
 916   PREFIX_0F7F,
 917   PREFIX_0FAE_REG_0,
 918   PREFIX_0FAE_REG_1,
 919   PREFIX_0FAE_REG_2,
 920   PREFIX_0FAE_REG_3,
 921   PREFIX_0FAE_REG_6,
 922   PREFIX_0FAE_REG_7,
 923   PREFIX_RM_0_0FAE_REG_7,
 924   PREFIX_0FB8,
 925   PREFIX_0FBC,
 926   PREFIX_0FBD,
 927   PREFIX_0FC2,
 928   PREFIX_0FC3,
 929   PREFIX_0FC7_REG_6,
 930   PREFIX_0FD0,
 931   PREFIX_0FD6,
 932   PREFIX_0FE6,
 933   PREFIX_0FE7,
 934   PREFIX_0FF0,
 935   PREFIX_0FF7,
 936   PREFIX_0F3810,
 937   PREFIX_0F3814,
 938   PREFIX_0F3815,
 939   PREFIX_0F3817,
 940   PREFIX_0F3820,
 941   PREFIX_0F3821,
 942   PREFIX_0F3822,
 943   PREFIX_0F3823,
 944   PREFIX_0F3824,
 945   PREFIX_0F3825,
 946   PREFIX_0F3828,
 947   PREFIX_0F3829,
 948   PREFIX_0F382A,
 949   PREFIX_0F382B,
 950   PREFIX_0F3830,
 951   PREFIX_0F3831,
 952   PREFIX_0F3832,
 953   PREFIX_0F3833,
 954   PREFIX_0F3834,
 955   PREFIX_0F3835,
 956   PREFIX_0F3837,
 957   PREFIX_0F3838,
 958   PREFIX_0F3839,
 959   PREFIX_0F383A,
 960   PREFIX_0F383B,
 961   PREFIX_0F383C,
 962   PREFIX_0F383D,
 963   PREFIX_0F383E,
 964   PREFIX_0F383F,
 965   PREFIX_0F3840,
 966   PREFIX_0F3841,
 967   PREFIX_0F3880,
 968   PREFIX_0F3881,
 969   PREFIX_0F3882,
 970   PREFIX_0F38C8,
 971   PREFIX_0F38C9,
 972   PREFIX_0F38CA,
 973   PREFIX_0F38CB,
 974   PREFIX_0F38CC,
 975   PREFIX_0F38CD,
 976   PREFIX_0F38DB,
 977   PREFIX_0F38DC,
 978   PREFIX_0F38DD,
 979   PREFIX_0F38DE,
 980   PREFIX_0F38DF,
 981   PREFIX_0F38F0,
 982   PREFIX_0F38F1,
 983   PREFIX_0F38F6,
 984   PREFIX_0F3A08,
 985   PREFIX_0F3A09,
 986   PREFIX_0F3A0A,
 987   PREFIX_0F3A0B,
 988   PREFIX_0F3A0C,
 989   PREFIX_0F3A0D,
 990   PREFIX_0F3A0E,
 991   PREFIX_0F3A14,
 992   PREFIX_0F3A15,
 993   PREFIX_0F3A16,
 994   PREFIX_0F3A17,
 995   PREFIX_0F3A20,
 996   PREFIX_0F3A21,
 997   PREFIX_0F3A22,
 998   PREFIX_0F3A40,
 999   PREFIX_0F3A41,
1000   PREFIX_0F3A42,
1001   PREFIX_0F3A44,
1002   PREFIX_0F3A60,
1003   PREFIX_0F3A61,
1004   PREFIX_0F3A62,
1005   PREFIX_0F3A63,
1006   PREFIX_0F3ACC,
1007   PREFIX_0F3ADF,
1008   PREFIX_VEX_0F10,
1009   PREFIX_VEX_0F11,
1010   PREFIX_VEX_0F12,
1011   PREFIX_VEX_0F16,
1012   PREFIX_VEX_0F2A,
1013   PREFIX_VEX_0F2C,
1014   PREFIX_VEX_0F2D,
1015   PREFIX_VEX_0F2E,
1016   PREFIX_VEX_0F2F,
1017   PREFIX_VEX_0F41,
1018   PREFIX_VEX_0F42,
1019   PREFIX_VEX_0F44,
1020   PREFIX_VEX_0F45,
1021   PREFIX_VEX_0F46,
1022   PREFIX_VEX_0F47,
1023   PREFIX_VEX_0F4A,
1024   PREFIX_VEX_0F4B,
1025   PREFIX_VEX_0F51,
1026   PREFIX_VEX_0F52,
1027   PREFIX_VEX_0F53,
1028   PREFIX_VEX_0F58,
1029   PREFIX_VEX_0F59,
1030   PREFIX_VEX_0F5A,
1031   PREFIX_VEX_0F5B,
1032   PREFIX_VEX_0F5C,
1033   PREFIX_VEX_0F5D,
1034   PREFIX_VEX_0F5E,
1035   PREFIX_VEX_0F5F,
1036   PREFIX_VEX_0F60,
1037   PREFIX_VEX_0F61,
1038   PREFIX_VEX_0F62,
1039   PREFIX_VEX_0F63,
1040   PREFIX_VEX_0F64,
1041   PREFIX_VEX_0F65,
1042   PREFIX_VEX_0F66,
1043   PREFIX_VEX_0F67,
1044   PREFIX_VEX_0F68,
1045   PREFIX_VEX_0F69,
1046   PREFIX_VEX_0F6A,
1047   PREFIX_VEX_0F6B,
1048   PREFIX_VEX_0F6C,
1049   PREFIX_VEX_0F6D,
1050   PREFIX_VEX_0F6E,
1051   PREFIX_VEX_0F6F,
1052   PREFIX_VEX_0F70,
1053   PREFIX_VEX_0F71_REG_2,
1054   PREFIX_VEX_0F71_REG_4,
1055   PREFIX_VEX_0F71_REG_6,
1056   PREFIX_VEX_0F72_REG_2,
1057   PREFIX_VEX_0F72_REG_4,
1058   PREFIX_VEX_0F72_REG_6,
1059   PREFIX_VEX_0F73_REG_2,
1060   PREFIX_VEX_0F73_REG_3,
1061   PREFIX_VEX_0F73_REG_6,
1062   PREFIX_VEX_0F73_REG_7,
1063   PREFIX_VEX_0F74,
1064   PREFIX_VEX_0F75,
1065   PREFIX_VEX_0F76,
1066   PREFIX_VEX_0F77,
1067   PREFIX_VEX_0F7C,
1068   PREFIX_VEX_0F7D,
1069   PREFIX_VEX_0F7E,
1070   PREFIX_VEX_0F7F,
1071   PREFIX_VEX_0F90,
1072   PREFIX_VEX_0F91,
1073   PREFIX_VEX_0F92,
1074   PREFIX_VEX_0F93,
1075   PREFIX_VEX_0F98,
1076   PREFIX_VEX_0F99,
1077   PREFIX_VEX_0FC2,
1078   PREFIX_VEX_0FC4,
1079   PREFIX_VEX_0FC5,
1080   PREFIX_VEX_0FD0,
1081   PREFIX_VEX_0FD1,
1082   PREFIX_VEX_0FD2,
1083   PREFIX_VEX_0FD3,
1084   PREFIX_VEX_0FD4,
1085   PREFIX_VEX_0FD5,
1086   PREFIX_VEX_0FD6,
1087   PREFIX_VEX_0FD7,
1088   PREFIX_VEX_0FD8,
1089   PREFIX_VEX_0FD9,
1090   PREFIX_VEX_0FDA,
1091   PREFIX_VEX_0FDB,
1092   PREFIX_VEX_0FDC,
1093   PREFIX_VEX_0FDD,
1094   PREFIX_VEX_0FDE,
1095   PREFIX_VEX_0FDF,
1096   PREFIX_VEX_0FE0,
1097   PREFIX_VEX_0FE1,
1098   PREFIX_VEX_0FE2,
1099   PREFIX_VEX_0FE3,
1100   PREFIX_VEX_0FE4,
1101   PREFIX_VEX_0FE5,
1102   PREFIX_VEX_0FE6,
1103   PREFIX_VEX_0FE7,
1104   PREFIX_VEX_0FE8,
1105   PREFIX_VEX_0FE9,
1106   PREFIX_VEX_0FEA,
1107   PREFIX_VEX_0FEB,
1108   PREFIX_VEX_0FEC,
1109   PREFIX_VEX_0FED,
1110   PREFIX_VEX_0FEE,
1111   PREFIX_VEX_0FEF,
1112   PREFIX_VEX_0FF0,
1113   PREFIX_VEX_0FF1,
1114   PREFIX_VEX_0FF2,
1115   PREFIX_VEX_0FF3,
1116   PREFIX_VEX_0FF4,
1117   PREFIX_VEX_0FF5,
1118   PREFIX_VEX_0FF6,
1119   PREFIX_VEX_0FF7,
1120   PREFIX_VEX_0FF8,
1121   PREFIX_VEX_0FF9,
1122   PREFIX_VEX_0FFA,
1123   PREFIX_VEX_0FFB,
1124   PREFIX_VEX_0FFC,
1125   PREFIX_VEX_0FFD,
1126   PREFIX_VEX_0FFE,
1127   PREFIX_VEX_0F3800,
1128   PREFIX_VEX_0F3801,
1129   PREFIX_VEX_0F3802,
1130   PREFIX_VEX_0F3803,
1131   PREFIX_VEX_0F3804,
1132   PREFIX_VEX_0F3805,
1133   PREFIX_VEX_0F3806,
1134   PREFIX_VEX_0F3807,
1135   PREFIX_VEX_0F3808,
1136   PREFIX_VEX_0F3809,
1137   PREFIX_VEX_0F380A,
1138   PREFIX_VEX_0F380B,
1139   PREFIX_VEX_0F380C,
1140   PREFIX_VEX_0F380D,
1141   PREFIX_VEX_0F380E,
1142   PREFIX_VEX_0F380F,
1143   PREFIX_VEX_0F3813,
1144   PREFIX_VEX_0F3816,
1145   PREFIX_VEX_0F3817,
1146   PREFIX_VEX_0F3818,
1147   PREFIX_VEX_0F3819,
1148   PREFIX_VEX_0F381A,
1149   PREFIX_VEX_0F381C,
1150   PREFIX_VEX_0F381D,
1151   PREFIX_VEX_0F381E,
1152   PREFIX_VEX_0F3820,
1153   PREFIX_VEX_0F3821,
1154   PREFIX_VEX_0F3822,
1155   PREFIX_VEX_0F3823,
1156   PREFIX_VEX_0F3824,
1157   PREFIX_VEX_0F3825,
1158   PREFIX_VEX_0F3828,
1159   PREFIX_VEX_0F3829,
1160   PREFIX_VEX_0F382A,
1161   PREFIX_VEX_0F382B,
1162   PREFIX_VEX_0F382C,
1163   PREFIX_VEX_0F382D,
1164   PREFIX_VEX_0F382E,
1165   PREFIX_VEX_0F382F,
1166   PREFIX_VEX_0F3830,
1167   PREFIX_VEX_0F3831,
1168   PREFIX_VEX_0F3832,
1169   PREFIX_VEX_0F3833,
1170   PREFIX_VEX_0F3834,
1171   PREFIX_VEX_0F3835,
1172   PREFIX_VEX_0F3836,
1173   PREFIX_VEX_0F3837,
1174   PREFIX_VEX_0F3838,
1175   PREFIX_VEX_0F3839,
1176   PREFIX_VEX_0F383A,
1177   PREFIX_VEX_0F383B,
1178   PREFIX_VEX_0F383C,
1179   PREFIX_VEX_0F383D,
1180   PREFIX_VEX_0F383E,
1181   PREFIX_VEX_0F383F,
1182   PREFIX_VEX_0F3840,
1183   PREFIX_VEX_0F3841,
1184   PREFIX_VEX_0F3845,
1185   PREFIX_VEX_0F3846,
1186   PREFIX_VEX_0F3847,
1187   PREFIX_VEX_0F3858,
1188   PREFIX_VEX_0F3859,
1189   PREFIX_VEX_0F385A,
1190   PREFIX_VEX_0F3878,
1191   PREFIX_VEX_0F3879,
1192   PREFIX_VEX_0F388C,
1193   PREFIX_VEX_0F388E,
1194   PREFIX_VEX_0F3890,
1195   PREFIX_VEX_0F3891,
1196   PREFIX_VEX_0F3892,
1197   PREFIX_VEX_0F3893,
1198   PREFIX_VEX_0F3896,
1199   PREFIX_VEX_0F3897,
1200   PREFIX_VEX_0F3898,
1201   PREFIX_VEX_0F3899,
1202   PREFIX_VEX_0F389A,
1203   PREFIX_VEX_0F389B,
1204   PREFIX_VEX_0F389C,
1205   PREFIX_VEX_0F389D,
1206   PREFIX_VEX_0F389E,
1207   PREFIX_VEX_0F389F,
1208   PREFIX_VEX_0F38A6,
1209   PREFIX_VEX_0F38A7,
1210   PREFIX_VEX_0F38A8,
1211   PREFIX_VEX_0F38A9,
1212   PREFIX_VEX_0F38AA,
1213   PREFIX_VEX_0F38AB,
1214   PREFIX_VEX_0F38AC,
1215   PREFIX_VEX_0F38AD,
1216   PREFIX_VEX_0F38AE,
1217   PREFIX_VEX_0F38AF,
1218   PREFIX_VEX_0F38B6,
1219   PREFIX_VEX_0F38B7,
1220   PREFIX_VEX_0F38B8,
1221   PREFIX_VEX_0F38B9,
1222   PREFIX_VEX_0F38BA,
1223   PREFIX_VEX_0F38BB,
1224   PREFIX_VEX_0F38BC,
1225   PREFIX_VEX_0F38BD,
1226   PREFIX_VEX_0F38BE,
1227   PREFIX_VEX_0F38BF,
1228   PREFIX_VEX_0F38DB,
1229   PREFIX_VEX_0F38DC,
1230   PREFIX_VEX_0F38DD,
1231   PREFIX_VEX_0F38DE,
1232   PREFIX_VEX_0F38DF,
1233   PREFIX_VEX_0F38F2,
1234   PREFIX_VEX_0F38F3_REG_1,
1235   PREFIX_VEX_0F38F3_REG_2,
1236   PREFIX_VEX_0F38F3_REG_3,
1237   PREFIX_VEX_0F38F5,
1238   PREFIX_VEX_0F38F6,
1239   PREFIX_VEX_0F38F7,
1240   PREFIX_VEX_0F3A00,
1241   PREFIX_VEX_0F3A01,
1242   PREFIX_VEX_0F3A02,
1243   PREFIX_VEX_0F3A04,
1244   PREFIX_VEX_0F3A05,
1245   PREFIX_VEX_0F3A06,
1246   PREFIX_VEX_0F3A08,
1247   PREFIX_VEX_0F3A09,
1248   PREFIX_VEX_0F3A0A,
1249   PREFIX_VEX_0F3A0B,
1250   PREFIX_VEX_0F3A0C,
1251   PREFIX_VEX_0F3A0D,
1252   PREFIX_VEX_0F3A0E,
1253   PREFIX_VEX_0F3A0F,
1254   PREFIX_VEX_0F3A14,
1255   PREFIX_VEX_0F3A15,
1256   PREFIX_VEX_0F3A16,
1257   PREFIX_VEX_0F3A17,
1258   PREFIX_VEX_0F3A18,
1259   PREFIX_VEX_0F3A19,
1260   PREFIX_VEX_0F3A1D,
1261   PREFIX_VEX_0F3A20,
1262   PREFIX_VEX_0F3A21,
1263   PREFIX_VEX_0F3A22,
1264   PREFIX_VEX_0F3A30,
1265   PREFIX_VEX_0F3A31,
1266   PREFIX_VEX_0F3A32,
1267   PREFIX_VEX_0F3A33,
1268   PREFIX_VEX_0F3A38,
1269   PREFIX_VEX_0F3A39,
1270   PREFIX_VEX_0F3A40,
1271   PREFIX_VEX_0F3A41,
1272   PREFIX_VEX_0F3A42,
1273   PREFIX_VEX_0F3A44,
1274   PREFIX_VEX_0F3A46,
1275   PREFIX_VEX_0F3A48,
1276   PREFIX_VEX_0F3A49,
1277   PREFIX_VEX_0F3A4A,
1278   PREFIX_VEX_0F3A4B,
1279   PREFIX_VEX_0F3A4C,
1280   PREFIX_VEX_0F3A5C,
1281   PREFIX_VEX_0F3A5D,
1282   PREFIX_VEX_0F3A5E,
1283   PREFIX_VEX_0F3A5F,
1284   PREFIX_VEX_0F3A60,
1285   PREFIX_VEX_0F3A61,
1286   PREFIX_VEX_0F3A62,
1287   PREFIX_VEX_0F3A63,
1288   PREFIX_VEX_0F3A68,
1289   PREFIX_VEX_0F3A69,
1290   PREFIX_VEX_0F3A6A,
1291   PREFIX_VEX_0F3A6B,
1292   PREFIX_VEX_0F3A6C,
1293   PREFIX_VEX_0F3A6D,
1294   PREFIX_VEX_0F3A6E,
1295   PREFIX_VEX_0F3A6F,
1296   PREFIX_VEX_0F3A78,
1297   PREFIX_VEX_0F3A79,
1298   PREFIX_VEX_0F3A7A,
1299   PREFIX_VEX_0F3A7B,
1300   PREFIX_VEX_0F3A7C,
1301   PREFIX_VEX_0F3A7D,
1302   PREFIX_VEX_0F3A7E,
1303   PREFIX_VEX_0F3A7F,
1304   PREFIX_VEX_0F3ADF,
1305   PREFIX_VEX_0F3AF0,
1306
1307   PREFIX_EVEX_0F10,
1308   PREFIX_EVEX_0F11,
1309   PREFIX_EVEX_0F12,
1310   PREFIX_EVEX_0F13,
1311   PREFIX_EVEX_0F14,
1312   PREFIX_EVEX_0F15,
1313   PREFIX_EVEX_0F16,
1314   PREFIX_EVEX_0F17,
1315   PREFIX_EVEX_0F28,
1316   PREFIX_EVEX_0F29,
1317   PREFIX_EVEX_0F2A,
1318   PREFIX_EVEX_0F2B,
1319   PREFIX_EVEX_0F2C,
1320   PREFIX_EVEX_0F2D,
1321   PREFIX_EVEX_0F2E,
1322   PREFIX_EVEX_0F2F,
1323   PREFIX_EVEX_0F51,
1324   PREFIX_EVEX_0F54,
1325   PREFIX_EVEX_0F55,
1326   PREFIX_EVEX_0F56,
1327   PREFIX_EVEX_0F57,
1328   PREFIX_EVEX_0F58,
1329   PREFIX_EVEX_0F59,
1330   PREFIX_EVEX_0F5A,
1331   PREFIX_EVEX_0F5B,
1332   PREFIX_EVEX_0F5C,
1333   PREFIX_EVEX_0F5D,
1334   PREFIX_EVEX_0F5E,
1335   PREFIX_EVEX_0F5F,
1336   PREFIX_EVEX_0F60,
1337   PREFIX_EVEX_0F61,
1338   PREFIX_EVEX_0F62,
1339   PREFIX_EVEX_0F63,
1340   PREFIX_EVEX_0F64,
1341   PREFIX_EVEX_0F65,
1342   PREFIX_EVEX_0F66,
1343   PREFIX_EVEX_0F67,
1344   PREFIX_EVEX_0F68,
1345   PREFIX_EVEX_0F69,
1346   PREFIX_EVEX_0F6A,
1347   PREFIX_EVEX_0F6B,
1348   PREFIX_EVEX_0F6C,
1349   PREFIX_EVEX_0F6D,
1350   PREFIX_EVEX_0F6E,
1351   PREFIX_EVEX_0F6F,
1352   PREFIX_EVEX_0F70,
1353   PREFIX_EVEX_0F71_REG_2,
1354   PREFIX_EVEX_0F71_REG_4,
1355   PREFIX_EVEX_0F71_REG_6,
1356   PREFIX_EVEX_0F72_REG_0,
1357   PREFIX_EVEX_0F72_REG_1,
1358   PREFIX_EVEX_0F72_REG_2,
1359   PREFIX_EVEX_0F72_REG_4,
1360   PREFIX_EVEX_0F72_REG_6,
1361   PREFIX_EVEX_0F73_REG_2,
1362   PREFIX_EVEX_0F73_REG_3,
1363   PREFIX_EVEX_0F73_REG_6,
1364   PREFIX_EVEX_0F73_REG_7,
1365   PREFIX_EVEX_0F74,
1366   PREFIX_EVEX_0F75,
1367   PREFIX_EVEX_0F76,
1368   PREFIX_EVEX_0F78,
1369   PREFIX_EVEX_0F79,
1370   PREFIX_EVEX_0F7A,
1371   PREFIX_EVEX_0F7B,
1372   PREFIX_EVEX_0F7E,
1373   PREFIX_EVEX_0F7F,
1374   PREFIX_EVEX_0FC2,
1375   PREFIX_EVEX_0FC4,
1376   PREFIX_EVEX_0FC5,
1377   PREFIX_EVEX_0FC6,
1378   PREFIX_EVEX_0FD1,
1379   PREFIX_EVEX_0FD2,
1380   PREFIX_EVEX_0FD3,
1381   PREFIX_EVEX_0FD4,
1382   PREFIX_EVEX_0FD5,
1383   PREFIX_EVEX_0FD6,
1384   PREFIX_EVEX_0FD8,
1385   PREFIX_EVEX_0FD9,
1386   PREFIX_EVEX_0FDA,
1387   PREFIX_EVEX_0FDB,
1388   PREFIX_EVEX_0FDC,
1389   PREFIX_EVEX_0FDD,
1390   PREFIX_EVEX_0FDE,
1391   PREFIX_EVEX_0FDF,
1392   PREFIX_EVEX_0FE0,
1393   PREFIX_EVEX_0FE1,
1394   PREFIX_EVEX_0FE2,
1395   PREFIX_EVEX_0FE3,
1396   PREFIX_EVEX_0FE4,
1397   PREFIX_EVEX_0FE5,
1398   PREFIX_EVEX_0FE6,
1399   PREFIX_EVEX_0FE7,
1400   PREFIX_EVEX_0FE8,
1401   PREFIX_EVEX_0FE9,
1402   PREFIX_EVEX_0FEA,
1403   PREFIX_EVEX_0FEB,
1404   PREFIX_EVEX_0FEC,
1405   PREFIX_EVEX_0FED,
1406   PREFIX_EVEX_0FEE,
1407   PREFIX_EVEX_0FEF,
1408   PREFIX_EVEX_0FF1,
1409   PREFIX_EVEX_0FF2,
1410   PREFIX_EVEX_0FF3,
1411   PREFIX_EVEX_0FF4,
1412   PREFIX_EVEX_0FF5,
1413   PREFIX_EVEX_0FF6,
1414   PREFIX_EVEX_0FF8,
1415   PREFIX_EVEX_0FF9,
1416   PREFIX_EVEX_0FFA,
1417   PREFIX_EVEX_0FFB,
1418   PREFIX_EVEX_0FFC,
1419   PREFIX_EVEX_0FFD,
1420   PREFIX_EVEX_0FFE,
1421   PREFIX_EVEX_0F3800,
1422   PREFIX_EVEX_0F3804,
1423   PREFIX_EVEX_0F380B,
1424   PREFIX_EVEX_0F380C,
1425   PREFIX_EVEX_0F380D,
1426   PREFIX_EVEX_0F3810,
1427   PREFIX_EVEX_0F3811,
1428   PREFIX_EVEX_0F3812,
1429   PREFIX_EVEX_0F3813,
1430   PREFIX_EVEX_0F3814,
1431   PREFIX_EVEX_0F3815,
1432   PREFIX_EVEX_0F3816,
1433   PREFIX_EVEX_0F3818,
1434   PREFIX_EVEX_0F3819,
1435   PREFIX_EVEX_0F381A,
1436   PREFIX_EVEX_0F381B,
1437   PREFIX_EVEX_0F381C,
1438   PREFIX_EVEX_0F381D,
1439   PREFIX_EVEX_0F381E,
1440   PREFIX_EVEX_0F381F,
1441   PREFIX_EVEX_0F3820,
1442   PREFIX_EVEX_0F3821,
1443   PREFIX_EVEX_0F3822,
1444   PREFIX_EVEX_0F3823,
1445   PREFIX_EVEX_0F3824,
1446   PREFIX_EVEX_0F3825,
1447   PREFIX_EVEX_0F3826,
1448   PREFIX_EVEX_0F3827,
1449   PREFIX_EVEX_0F3828,
1450   PREFIX_EVEX_0F3829,
1451   PREFIX_EVEX_0F382A,
1452   PREFIX_EVEX_0F382B,
1453   PREFIX_EVEX_0F382C,
1454   PREFIX_EVEX_0F382D,
1455   PREFIX_EVEX_0F3830,
1456   PREFIX_EVEX_0F3831,
1457   PREFIX_EVEX_0F3832,
1458   PREFIX_EVEX_0F3833,
1459   PREFIX_EVEX_0F3834,
1460   PREFIX_EVEX_0F3835,
1461   PREFIX_EVEX_0F3836,
1462   PREFIX_EVEX_0F3837,
1463   PREFIX_EVEX_0F3838,
1464   PREFIX_EVEX_0F3839,
1465   PREFIX_EVEX_0F383A,
1466   PREFIX_EVEX_0F383B,
1467   PREFIX_EVEX_0F383C,
1468   PREFIX_EVEX_0F383D,
1469   PREFIX_EVEX_0F383E,
1470   PREFIX_EVEX_0F383F,
1471   PREFIX_EVEX_0F3840,
1472   PREFIX_EVEX_0F3842,
1473   PREFIX_EVEX_0F3843,
1474   PREFIX_EVEX_0F3844,
1475   PREFIX_EVEX_0F3845,
1476   PREFIX_EVEX_0F3846,
1477   PREFIX_EVEX_0F3847,
1478   PREFIX_EVEX_0F384C,
1479   PREFIX_EVEX_0F384D,
1480   PREFIX_EVEX_0F384E,
1481   PREFIX_EVEX_0F384F,
1482   PREFIX_EVEX_0F3858,
1483   PREFIX_EVEX_0F3859,
1484   PREFIX_EVEX_0F385A,
1485   PREFIX_EVEX_0F385B,
1486   PREFIX_EVEX_0F3864,
1487   PREFIX_EVEX_0F3865,
1488   PREFIX_EVEX_0F3866,
1489   PREFIX_EVEX_0F3875,
1490   PREFIX_EVEX_0F3876,
1491   PREFIX_EVEX_0F3877,
1492   PREFIX_EVEX_0F3878,
1493   PREFIX_EVEX_0F3879,
1494   PREFIX_EVEX_0F387A,
1495   PREFIX_EVEX_0F387B,
1496   PREFIX_EVEX_0F387C,
1497   PREFIX_EVEX_0F387D,
1498   PREFIX_EVEX_0F387E,
1499   PREFIX_EVEX_0F387F,
1500   PREFIX_EVEX_0F3883,
1501   PREFIX_EVEX_0F3888,
1502   PREFIX_EVEX_0F3889,
1503   PREFIX_EVEX_0F388A,
1504   PREFIX_EVEX_0F388B,
1505   PREFIX_EVEX_0F388D,
1506   PREFIX_EVEX_0F3890,
1507   PREFIX_EVEX_0F3891,
1508   PREFIX_EVEX_0F3892,
1509   PREFIX_EVEX_0F3893,
1510   PREFIX_EVEX_0F3896,
1511   PREFIX_EVEX_0F3897,
1512   PREFIX_EVEX_0F3898,
1513   PREFIX_EVEX_0F3899,
1514   PREFIX_EVEX_0F389A,
1515   PREFIX_EVEX_0F389B,
1516   PREFIX_EVEX_0F389C,
1517   PREFIX_EVEX_0F389D,
1518   PREFIX_EVEX_0F389E,
1519   PREFIX_EVEX_0F389F,
1520   PREFIX_EVEX_0F38A0,
1521   PREFIX_EVEX_0F38A1,
1522   PREFIX_EVEX_0F38A2,
1523   PREFIX_EVEX_0F38A3,
1524   PREFIX_EVEX_0F38A6,
1525   PREFIX_EVEX_0F38A7,
1526   PREFIX_EVEX_0F38A8,
1527   PREFIX_EVEX_0F38A9,
1528   PREFIX_EVEX_0F38AA,
1529   PREFIX_EVEX_0F38AB,
1530   PREFIX_EVEX_0F38AC,
1531   PREFIX_EVEX_0F38AD,
1532   PREFIX_EVEX_0F38AE,
1533   PREFIX_EVEX_0F38AF,
1534   PREFIX_EVEX_0F38B4,
1535   PREFIX_EVEX_0F38B5,
1536   PREFIX_EVEX_0F38B6,
1537   PREFIX_EVEX_0F38B7,
1538   PREFIX_EVEX_0F38B8,
1539   PREFIX_EVEX_0F38B9,
1540   PREFIX_EVEX_0F38BA,
1541   PREFIX_EVEX_0F38BB,
1542   PREFIX_EVEX_0F38BC,
1543   PREFIX_EVEX_0F38BD,
1544   PREFIX_EVEX_0F38BE,
1545   PREFIX_EVEX_0F38BF,
1546   PREFIX_EVEX_0F38C4,
1547   PREFIX_EVEX_0F38C6_REG_1,
1548   PREFIX_EVEX_0F38C6_REG_2,
1549   PREFIX_EVEX_0F38C6_REG_5,
1550   PREFIX_EVEX_0F38C6_REG_6,
1551   PREFIX_EVEX_0F38C7_REG_1,
1552   PREFIX_EVEX_0F38C7_REG_2,
1553   PREFIX_EVEX_0F38C7_REG_5,
1554   PREFIX_EVEX_0F38C7_REG_6,
1555   PREFIX_EVEX_0F38C8,
1556   PREFIX_EVEX_0F38CA,
1557   PREFIX_EVEX_0F38CB,
1558   PREFIX_EVEX_0F38CC,
1559   PREFIX_EVEX_0F38CD,
1560
1561   PREFIX_EVEX_0F3A00,
1562   PREFIX_EVEX_0F3A01,
1563   PREFIX_EVEX_0F3A03,
1564   PREFIX_EVEX_0F3A04,
1565   PREFIX_EVEX_0F3A05,
1566   PREFIX_EVEX_0F3A08,
1567   PREFIX_EVEX_0F3A09,
1568   PREFIX_EVEX_0F3A0A,
1569   PREFIX_EVEX_0F3A0B,
1570   PREFIX_EVEX_0F3A0F,
1571   PREFIX_EVEX_0F3A14,
1572   PREFIX_EVEX_0F3A15,
1573   PREFIX_EVEX_0F3A16,
1574   PREFIX_EVEX_0F3A17,
1575   PREFIX_EVEX_0F3A18,
1576   PREFIX_EVEX_0F3A19,
1577   PREFIX_EVEX_0F3A1A,
1578   PREFIX_EVEX_0F3A1B,
1579   PREFIX_EVEX_0F3A1D,
1580   PREFIX_EVEX_0F3A1E,
1581   PREFIX_EVEX_0F3A1F,
1582   PREFIX_EVEX_0F3A20,
1583   PREFIX_EVEX_0F3A21,
1584   PREFIX_EVEX_0F3A22,
1585   PREFIX_EVEX_0F3A23,
1586   PREFIX_EVEX_0F3A25,
1587   PREFIX_EVEX_0F3A26,
1588   PREFIX_EVEX_0F3A27,
1589   PREFIX_EVEX_0F3A38,
1590   PREFIX_EVEX_0F3A39,
1591   PREFIX_EVEX_0F3A3A,
1592   PREFIX_EVEX_0F3A3B,
1593   PREFIX_EVEX_0F3A3E,
1594   PREFIX_EVEX_0F3A3F,
1595   PREFIX_EVEX_0F3A42,
1596   PREFIX_EVEX_0F3A43,
1597   PREFIX_EVEX_0F3A50,
1598   PREFIX_EVEX_0F3A51,
1599   PREFIX_EVEX_0F3A54,
1600   PREFIX_EVEX_0F3A55,
1601   PREFIX_EVEX_0F3A56,
1602   PREFIX_EVEX_0F3A57,
1603   PREFIX_EVEX_0F3A66,
1604   PREFIX_EVEX_0F3A67
1605 };
1606
1607 enum
1608 {
1609   X86_64_06 = 0,
1610   X86_64_07,
1611   X86_64_0D,
1612   X86_64_16,
1613   X86_64_17,
1614   X86_64_1E,
1615   X86_64_1F,
1616   X86_64_27,
1617   X86_64_2F,
1618   X86_64_37,
1619   X86_64_3F,
1620   X86_64_60,
1621   X86_64_61,
1622   X86_64_62,
1623   X86_64_63,
1624   X86_64_6D,
1625   X86_64_6F,
1626   X86_64_9A,
1627   X86_64_C4,
1628   X86_64_C5,
1629   X86_64_CE,
1630   X86_64_D4,
1631   X86_64_D5,
1632   X86_64_EA,
1633   X86_64_0F01_REG_0,
1634   X86_64_0F01_REG_1,
1635   X86_64_0F01_REG_2,
1636   X86_64_0F01_REG_3
1637 };
1638
1639 enum
1640 {
1641   THREE_BYTE_0F38 = 0,
1642   THREE_BYTE_0F3A,
1643   THREE_BYTE_0F7A
1644 };
1645
1646 enum
1647 {
1648   XOP_08 = 0,
1649   XOP_09,
1650   XOP_0A
1651 };
1652
1653 enum
1654 {
1655   VEX_0F = 0,
1656   VEX_0F38,
1657   VEX_0F3A
1658 };
1659
1660 enum
1661 {
1662   EVEX_0F = 0,
1663   EVEX_0F38,
1664   EVEX_0F3A
1665 };
1666
1667 enum
1668 {
1669   VEX_LEN_0F10_P_1 = 0,
1670   VEX_LEN_0F10_P_3,
1671   VEX_LEN_0F11_P_1,
1672   VEX_LEN_0F11_P_3,
1673   VEX_LEN_0F12_P_0_M_0,
1674   VEX_LEN_0F12_P_0_M_1,
1675   VEX_LEN_0F12_P_2,
1676   VEX_LEN_0F13_M_0,
1677   VEX_LEN_0F16_P_0_M_0,
1678   VEX_LEN_0F16_P_0_M_1,
1679   VEX_LEN_0F16_P_2,
1680   VEX_LEN_0F17_M_0,
1681   VEX_LEN_0F2A_P_1,
1682   VEX_LEN_0F2A_P_3,
1683   VEX_LEN_0F2C_P_1,
1684   VEX_LEN_0F2C_P_3,
1685   VEX_LEN_0F2D_P_1,
1686   VEX_LEN_0F2D_P_3,
1687   VEX_LEN_0F2E_P_0,
1688   VEX_LEN_0F2E_P_2,
1689   VEX_LEN_0F2F_P_0,
1690   VEX_LEN_0F2F_P_2,
1691   VEX_LEN_0F41_P_0,
1692   VEX_LEN_0F41_P_2,
1693   VEX_LEN_0F42_P_0,
1694   VEX_LEN_0F42_P_2,
1695   VEX_LEN_0F44_P_0,
1696   VEX_LEN_0F44_P_2,
1697   VEX_LEN_0F45_P_0,
1698   VEX_LEN_0F45_P_2,
1699   VEX_LEN_0F46_P_0,
1700   VEX_LEN_0F46_P_2,
1701   VEX_LEN_0F47_P_0,
1702   VEX_LEN_0F47_P_2,
1703   VEX_LEN_0F4A_P_0,
1704   VEX_LEN_0F4A_P_2,
1705   VEX_LEN_0F4B_P_0,
1706   VEX_LEN_0F4B_P_2,
1707   VEX_LEN_0F51_P_1,
1708   VEX_LEN_0F51_P_3,
1709   VEX_LEN_0F52_P_1,
1710   VEX_LEN_0F53_P_1,
1711   VEX_LEN_0F58_P_1,
1712   VEX_LEN_0F58_P_3,
1713   VEX_LEN_0F59_P_1,
1714   VEX_LEN_0F59_P_3,
1715   VEX_LEN_0F5A_P_1,
1716   VEX_LEN_0F5A_P_3,
1717   VEX_LEN_0F5C_P_1,
1718   VEX_LEN_0F5C_P_3,
1719   VEX_LEN_0F5D_P_1,
1720   VEX_LEN_0F5D_P_3,
1721   VEX_LEN_0F5E_P_1,
1722   VEX_LEN_0F5E_P_3,
1723   VEX_LEN_0F5F_P_1,
1724   VEX_LEN_0F5F_P_3,
1725   VEX_LEN_0F6E_P_2,
1726   VEX_LEN_0F7E_P_1,
1727   VEX_LEN_0F7E_P_2,
1728   VEX_LEN_0F90_P_0,
1729   VEX_LEN_0F90_P_2,
1730   VEX_LEN_0F91_P_0,
1731   VEX_LEN_0F91_P_2,
1732   VEX_LEN_0F92_P_0,
1733   VEX_LEN_0F92_P_2,
1734   VEX_LEN_0F92_P_3,
1735   VEX_LEN_0F93_P_0,
1736   VEX_LEN_0F93_P_2,
1737   VEX_LEN_0F93_P_3,
1738   VEX_LEN_0F98_P_0,
1739   VEX_LEN_0F98_P_2,
1740   VEX_LEN_0F99_P_0,
1741   VEX_LEN_0F99_P_2,
1742   VEX_LEN_0FAE_R_2_M_0,
1743   VEX_LEN_0FAE_R_3_M_0,
1744   VEX_LEN_0FC2_P_1,
1745   VEX_LEN_0FC2_P_3,
1746   VEX_LEN_0FC4_P_2,
1747   VEX_LEN_0FC5_P_2,
1748   VEX_LEN_0FD6_P_2,
1749   VEX_LEN_0FF7_P_2,
1750   VEX_LEN_0F3816_P_2,
1751   VEX_LEN_0F3819_P_2,
1752   VEX_LEN_0F381A_P_2_M_0,
1753   VEX_LEN_0F3836_P_2,
1754   VEX_LEN_0F3841_P_2,
1755   VEX_LEN_0F385A_P_2_M_0,
1756   VEX_LEN_0F38DB_P_2,
1757   VEX_LEN_0F38DC_P_2,
1758   VEX_LEN_0F38DD_P_2,
1759   VEX_LEN_0F38DE_P_2,
1760   VEX_LEN_0F38DF_P_2,
1761   VEX_LEN_0F38F2_P_0,
1762   VEX_LEN_0F38F3_R_1_P_0,
1763   VEX_LEN_0F38F3_R_2_P_0,
1764   VEX_LEN_0F38F3_R_3_P_0,
1765   VEX_LEN_0F38F5_P_0,
1766   VEX_LEN_0F38F5_P_1,
1767   VEX_LEN_0F38F5_P_3,
1768   VEX_LEN_0F38F6_P_3,
1769   VEX_LEN_0F38F7_P_0,
1770   VEX_LEN_0F38F7_P_1,
1771   VEX_LEN_0F38F7_P_2,
1772   VEX_LEN_0F38F7_P_3,
1773   VEX_LEN_0F3A00_P_2,
1774   VEX_LEN_0F3A01_P_2,
1775   VEX_LEN_0F3A06_P_2,
1776   VEX_LEN_0F3A0A_P_2,
1777   VEX_LEN_0F3A0B_P_2,
1778   VEX_LEN_0F3A14_P_2,
1779   VEX_LEN_0F3A15_P_2,
1780   VEX_LEN_0F3A16_P_2,
1781   VEX_LEN_0F3A17_P_2,
1782   VEX_LEN_0F3A18_P_2,
1783   VEX_LEN_0F3A19_P_2,
1784   VEX_LEN_0F3A20_P_2,
1785   VEX_LEN_0F3A21_P_2,
1786   VEX_LEN_0F3A22_P_2,
1787   VEX_LEN_0F3A30_P_2,
1788   VEX_LEN_0F3A31_P_2,
1789   VEX_LEN_0F3A32_P_2,
1790   VEX_LEN_0F3A33_P_2,
1791   VEX_LEN_0F3A38_P_2,
1792   VEX_LEN_0F3A39_P_2,
1793   VEX_LEN_0F3A41_P_2,
1794   VEX_LEN_0F3A44_P_2,
1795   VEX_LEN_0F3A46_P_2,
1796   VEX_LEN_0F3A60_P_2,
1797   VEX_LEN_0F3A61_P_2,
1798   VEX_LEN_0F3A62_P_2,
1799   VEX_LEN_0F3A63_P_2,
1800   VEX_LEN_0F3A6A_P_2,
1801   VEX_LEN_0F3A6B_P_2,
1802   VEX_LEN_0F3A6E_P_2,
1803   VEX_LEN_0F3A6F_P_2,
1804   VEX_LEN_0F3A7A_P_2,
1805   VEX_LEN_0F3A7B_P_2,
1806   VEX_LEN_0F3A7E_P_2,
1807   VEX_LEN_0F3A7F_P_2,
1808   VEX_LEN_0F3ADF_P_2,
1809   VEX_LEN_0F3AF0_P_3,
1810   VEX_LEN_0FXOP_08_CC,
1811   VEX_LEN_0FXOP_08_CD,
1812   VEX_LEN_0FXOP_08_CE,
1813   VEX_LEN_0FXOP_08_CF,
1814   VEX_LEN_0FXOP_08_EC,
1815   VEX_LEN_0FXOP_08_ED,
1816   VEX_LEN_0FXOP_08_EE,
1817   VEX_LEN_0FXOP_08_EF,
1818   VEX_LEN_0FXOP_09_80,
1819   VEX_LEN_0FXOP_09_81
1820 };
1821
1822 enum
1823 {
1824   VEX_W_0F10_P_0 = 0,
1825   VEX_W_0F10_P_1,
1826   VEX_W_0F10_P_2,
1827   VEX_W_0F10_P_3,
1828   VEX_W_0F11_P_0,
1829   VEX_W_0F11_P_1,
1830   VEX_W_0F11_P_2,
1831   VEX_W_0F11_P_3,
1832   VEX_W_0F12_P_0_M_0,
1833   VEX_W_0F12_P_0_M_1,
1834   VEX_W_0F12_P_1,
1835   VEX_W_0F12_P_2,
1836   VEX_W_0F12_P_3,
1837   VEX_W_0F13_M_0,
1838   VEX_W_0F14,
1839   VEX_W_0F15,
1840   VEX_W_0F16_P_0_M_0,
1841   VEX_W_0F16_P_0_M_1,
1842   VEX_W_0F16_P_1,
1843   VEX_W_0F16_P_2,
1844   VEX_W_0F17_M_0,
1845   VEX_W_0F28,
1846   VEX_W_0F29,
1847   VEX_W_0F2B_M_0,
1848   VEX_W_0F2E_P_0,
1849   VEX_W_0F2E_P_2,
1850   VEX_W_0F2F_P_0,
1851   VEX_W_0F2F_P_2,
1852   VEX_W_0F41_P_0_LEN_1,
1853   VEX_W_0F41_P_2_LEN_1,
1854   VEX_W_0F42_P_0_LEN_1,
1855   VEX_W_0F42_P_2_LEN_1,
1856   VEX_W_0F44_P_0_LEN_0,
1857   VEX_W_0F44_P_2_LEN_0,
1858   VEX_W_0F45_P_0_LEN_1,
1859   VEX_W_0F45_P_2_LEN_1,
1860   VEX_W_0F46_P_0_LEN_1,
1861   VEX_W_0F46_P_2_LEN_1,
1862   VEX_W_0F47_P_0_LEN_1,
1863   VEX_W_0F47_P_2_LEN_1,
1864   VEX_W_0F4A_P_0_LEN_1,
1865   VEX_W_0F4A_P_2_LEN_1,
1866   VEX_W_0F4B_P_0_LEN_1,
1867   VEX_W_0F4B_P_2_LEN_1,
1868   VEX_W_0F50_M_0,
1869   VEX_W_0F51_P_0,
1870   VEX_W_0F51_P_1,
1871   VEX_W_0F51_P_2,
1872   VEX_W_0F51_P_3,
1873   VEX_W_0F52_P_0,
1874   VEX_W_0F52_P_1,
1875   VEX_W_0F53_P_0,
1876   VEX_W_0F53_P_1,
1877   VEX_W_0F58_P_0,
1878   VEX_W_0F58_P_1,
1879   VEX_W_0F58_P_2,
1880   VEX_W_0F58_P_3,
1881   VEX_W_0F59_P_0,
1882   VEX_W_0F59_P_1,
1883   VEX_W_0F59_P_2,
1884   VEX_W_0F59_P_3,
1885   VEX_W_0F5A_P_0,
1886   VEX_W_0F5A_P_1,
1887   VEX_W_0F5A_P_3,
1888   VEX_W_0F5B_P_0,
1889   VEX_W_0F5B_P_1,
1890   VEX_W_0F5B_P_2,
1891   VEX_W_0F5C_P_0,
1892   VEX_W_0F5C_P_1,
1893   VEX_W_0F5C_P_2,
1894   VEX_W_0F5C_P_3,
1895   VEX_W_0F5D_P_0,
1896   VEX_W_0F5D_P_1,
1897   VEX_W_0F5D_P_2,
1898   VEX_W_0F5D_P_3,
1899   VEX_W_0F5E_P_0,
1900   VEX_W_0F5E_P_1,
1901   VEX_W_0F5E_P_2,
1902   VEX_W_0F5E_P_3,
1903   VEX_W_0F5F_P_0,
1904   VEX_W_0F5F_P_1,
1905   VEX_W_0F5F_P_2,
1906   VEX_W_0F5F_P_3,
1907   VEX_W_0F60_P_2,
1908   VEX_W_0F61_P_2,
1909   VEX_W_0F62_P_2,
1910   VEX_W_0F63_P_2,
1911   VEX_W_0F64_P_2,
1912   VEX_W_0F65_P_2,
1913   VEX_W_0F66_P_2,
1914   VEX_W_0F67_P_2,
1915   VEX_W_0F68_P_2,
1916   VEX_W_0F69_P_2,
1917   VEX_W_0F6A_P_2,
1918   VEX_W_0F6B_P_2,
1919   VEX_W_0F6C_P_2,
1920   VEX_W_0F6D_P_2,
1921   VEX_W_0F6F_P_1,
1922   VEX_W_0F6F_P_2,
1923   VEX_W_0F70_P_1,
1924   VEX_W_0F70_P_2,
1925   VEX_W_0F70_P_3,
1926   VEX_W_0F71_R_2_P_2,
1927   VEX_W_0F71_R_4_P_2,
1928   VEX_W_0F71_R_6_P_2,
1929   VEX_W_0F72_R_2_P_2,
1930   VEX_W_0F72_R_4_P_2,
1931   VEX_W_0F72_R_6_P_2,
1932   VEX_W_0F73_R_2_P_2,
1933   VEX_W_0F73_R_3_P_2,
1934   VEX_W_0F73_R_6_P_2,
1935   VEX_W_0F73_R_7_P_2,
1936   VEX_W_0F74_P_2,
1937   VEX_W_0F75_P_2,
1938   VEX_W_0F76_P_2,
1939   VEX_W_0F77_P_0,
1940   VEX_W_0F7C_P_2,
1941   VEX_W_0F7C_P_3,
1942   VEX_W_0F7D_P_2,
1943   VEX_W_0F7D_P_3,
1944   VEX_W_0F7E_P_1,
1945   VEX_W_0F7F_P_1,
1946   VEX_W_0F7F_P_2,
1947   VEX_W_0F90_P_0_LEN_0,
1948   VEX_W_0F90_P_2_LEN_0,
1949   VEX_W_0F91_P_0_LEN_0,
1950   VEX_W_0F91_P_2_LEN_0,
1951   VEX_W_0F92_P_0_LEN_0,
1952   VEX_W_0F92_P_2_LEN_0,
1953   VEX_W_0F92_P_3_LEN_0,
1954   VEX_W_0F93_P_0_LEN_0,
1955   VEX_W_0F93_P_2_LEN_0,
1956   VEX_W_0F93_P_3_LEN_0,
1957   VEX_W_0F98_P_0_LEN_0,
1958   VEX_W_0F98_P_2_LEN_0,
1959   VEX_W_0F99_P_0_LEN_0,
1960   VEX_W_0F99_P_2_LEN_0,
1961   VEX_W_0FAE_R_2_M_0,
1962   VEX_W_0FAE_R_3_M_0,
1963   VEX_W_0FC2_P_0,
1964   VEX_W_0FC2_P_1,
1965   VEX_W_0FC2_P_2,
1966   VEX_W_0FC2_P_3,
1967   VEX_W_0FC4_P_2,
1968   VEX_W_0FC5_P_2,
1969   VEX_W_0FD0_P_2,
1970   VEX_W_0FD0_P_3,
1971   VEX_W_0FD1_P_2,
1972   VEX_W_0FD2_P_2,
1973   VEX_W_0FD3_P_2,
1974   VEX_W_0FD4_P_2,
1975   VEX_W_0FD5_P_2,
1976   VEX_W_0FD6_P_2,
1977   VEX_W_0FD7_P_2_M_1,
1978   VEX_W_0FD8_P_2,
1979   VEX_W_0FD9_P_2,
1980   VEX_W_0FDA_P_2,
1981   VEX_W_0FDB_P_2,
1982   VEX_W_0FDC_P_2,
1983   VEX_W_0FDD_P_2,
1984   VEX_W_0FDE_P_2,
1985   VEX_W_0FDF_P_2,
1986   VEX_W_0FE0_P_2,
1987   VEX_W_0FE1_P_2,
1988   VEX_W_0FE2_P_2,
1989   VEX_W_0FE3_P_2,
1990   VEX_W_0FE4_P_2,
1991   VEX_W_0FE5_P_2,
1992   VEX_W_0FE6_P_1,
1993   VEX_W_0FE6_P_2,
1994   VEX_W_0FE6_P_3,
1995   VEX_W_0FE7_P_2_M_0,
1996   VEX_W_0FE8_P_2,
1997   VEX_W_0FE9_P_2,
1998   VEX_W_0FEA_P_2,
1999   VEX_W_0FEB_P_2,
2000   VEX_W_0FEC_P_2,
2001   VEX_W_0FED_P_2,
2002   VEX_W_0FEE_P_2,
2003   VEX_W_0FEF_P_2,
2004   VEX_W_0FF0_P_3_M_0,
2005   VEX_W_0FF1_P_2,
2006   VEX_W_0FF2_P_2,
2007   VEX_W_0FF3_P_2,
2008   VEX_W_0FF4_P_2,
2009   VEX_W_0FF5_P_2,
2010   VEX_W_0FF6_P_2,
2011   VEX_W_0FF7_P_2,
2012   VEX_W_0FF8_P_2,
2013   VEX_W_0FF9_P_2,
2014   VEX_W_0FFA_P_2,
2015   VEX_W_0FFB_P_2,
2016   VEX_W_0FFC_P_2,
2017   VEX_W_0FFD_P_2,
2018   VEX_W_0FFE_P_2,
2019   VEX_W_0F3800_P_2,
2020   VEX_W_0F3801_P_2,
2021   VEX_W_0F3802_P_2,
2022   VEX_W_0F3803_P_2,
2023   VEX_W_0F3804_P_2,
2024   VEX_W_0F3805_P_2,
2025   VEX_W_0F3806_P_2,
2026   VEX_W_0F3807_P_2,
2027   VEX_W_0F3808_P_2,
2028   VEX_W_0F3809_P_2,
2029   VEX_W_0F380A_P_2,
2030   VEX_W_0F380B_P_2,
2031   VEX_W_0F380C_P_2,
2032   VEX_W_0F380D_P_2,
2033   VEX_W_0F380E_P_2,
2034   VEX_W_0F380F_P_2,
2035   VEX_W_0F3816_P_2,
2036   VEX_W_0F3817_P_2,
2037   VEX_W_0F3818_P_2,
2038   VEX_W_0F3819_P_2,
2039   VEX_W_0F381A_P_2_M_0,
2040   VEX_W_0F381C_P_2,
2041   VEX_W_0F381D_P_2,
2042   VEX_W_0F381E_P_2,
2043   VEX_W_0F3820_P_2,
2044   VEX_W_0F3821_P_2,
2045   VEX_W_0F3822_P_2,
2046   VEX_W_0F3823_P_2,
2047   VEX_W_0F3824_P_2,
2048   VEX_W_0F3825_P_2,
2049   VEX_W_0F3828_P_2,
2050   VEX_W_0F3829_P_2,
2051   VEX_W_0F382A_P_2_M_0,
2052   VEX_W_0F382B_P_2,
2053   VEX_W_0F382C_P_2_M_0,
2054   VEX_W_0F382D_P_2_M_0,
2055   VEX_W_0F382E_P_2_M_0,
2056   VEX_W_0F382F_P_2_M_0,
2057   VEX_W_0F3830_P_2,
2058   VEX_W_0F3831_P_2,
2059   VEX_W_0F3832_P_2,
2060   VEX_W_0F3833_P_2,
2061   VEX_W_0F3834_P_2,
2062   VEX_W_0F3835_P_2,
2063   VEX_W_0F3836_P_2,
2064   VEX_W_0F3837_P_2,
2065   VEX_W_0F3838_P_2,
2066   VEX_W_0F3839_P_2,
2067   VEX_W_0F383A_P_2,
2068   VEX_W_0F383B_P_2,
2069   VEX_W_0F383C_P_2,
2070   VEX_W_0F383D_P_2,
2071   VEX_W_0F383E_P_2,
2072   VEX_W_0F383F_P_2,
2073   VEX_W_0F3840_P_2,
2074   VEX_W_0F3841_P_2,
2075   VEX_W_0F3846_P_2,
2076   VEX_W_0F3858_P_2,
2077   VEX_W_0F3859_P_2,
2078   VEX_W_0F385A_P_2_M_0,
2079   VEX_W_0F3878_P_2,
2080   VEX_W_0F3879_P_2,
2081   VEX_W_0F38DB_P_2,
2082   VEX_W_0F38DC_P_2,
2083   VEX_W_0F38DD_P_2,
2084   VEX_W_0F38DE_P_2,
2085   VEX_W_0F38DF_P_2,
2086   VEX_W_0F3A00_P_2,
2087   VEX_W_0F3A01_P_2,
2088   VEX_W_0F3A02_P_2,
2089   VEX_W_0F3A04_P_2,
2090   VEX_W_0F3A05_P_2,
2091   VEX_W_0F3A06_P_2,
2092   VEX_W_0F3A08_P_2,
2093   VEX_W_0F3A09_P_2,
2094   VEX_W_0F3A0A_P_2,
2095   VEX_W_0F3A0B_P_2,
2096   VEX_W_0F3A0C_P_2,
2097   VEX_W_0F3A0D_P_2,
2098   VEX_W_0F3A0E_P_2,
2099   VEX_W_0F3A0F_P_2,
2100   VEX_W_0F3A14_P_2,
2101   VEX_W_0F3A15_P_2,
2102   VEX_W_0F3A18_P_2,
2103   VEX_W_0F3A19_P_2,
2104   VEX_W_0F3A20_P_2,
2105   VEX_W_0F3A21_P_2,
2106   VEX_W_0F3A30_P_2_LEN_0,
2107   VEX_W_0F3A31_P_2_LEN_0,
2108   VEX_W_0F3A32_P_2_LEN_0,
2109   VEX_W_0F3A33_P_2_LEN_0,
2110   VEX_W_0F3A38_P_2,
2111   VEX_W_0F3A39_P_2,
2112   VEX_W_0F3A40_P_2,
2113   VEX_W_0F3A41_P_2,
2114   VEX_W_0F3A42_P_2,
2115   VEX_W_0F3A44_P_2,
2116   VEX_W_0F3A46_P_2,
2117   VEX_W_0F3A48_P_2,
2118   VEX_W_0F3A49_P_2,
2119   VEX_W_0F3A4A_P_2,
2120   VEX_W_0F3A4B_P_2,
2121   VEX_W_0F3A4C_P_2,
2122   VEX_W_0F3A60_P_2,
2123   VEX_W_0F3A61_P_2,
2124   VEX_W_0F3A62_P_2,
2125   VEX_W_0F3A63_P_2,
2126   VEX_W_0F3ADF_P_2,
2127
2128   EVEX_W_0F10_P_0,
2129   EVEX_W_0F10_P_1_M_0,
2130   EVEX_W_0F10_P_1_M_1,
2131   EVEX_W_0F10_P_2,
2132   EVEX_W_0F10_P_3_M_0,
2133   EVEX_W_0F10_P_3_M_1,
2134   EVEX_W_0F11_P_0,
2135   EVEX_W_0F11_P_1_M_0,
2136   EVEX_W_0F11_P_1_M_1,
2137   EVEX_W_0F11_P_2,
2138   EVEX_W_0F11_P_3_M_0,
2139   EVEX_W_0F11_P_3_M_1,
2140   EVEX_W_0F12_P_0_M_0,
2141   EVEX_W_0F12_P_0_M_1,
2142   EVEX_W_0F12_P_1,
2143   EVEX_W_0F12_P_2,
2144   EVEX_W_0F12_P_3,
2145   EVEX_W_0F13_P_0,
2146   EVEX_W_0F13_P_2,
2147   EVEX_W_0F14_P_0,
2148   EVEX_W_0F14_P_2,
2149   EVEX_W_0F15_P_0,
2150   EVEX_W_0F15_P_2,
2151   EVEX_W_0F16_P_0_M_0,
2152   EVEX_W_0F16_P_0_M_1,
2153   EVEX_W_0F16_P_1,
2154   EVEX_W_0F16_P_2,
2155   EVEX_W_0F17_P_0,
2156   EVEX_W_0F17_P_2,
2157   EVEX_W_0F28_P_0,
2158   EVEX_W_0F28_P_2,
2159   EVEX_W_0F29_P_0,
2160   EVEX_W_0F29_P_2,
2161   EVEX_W_0F2A_P_1,
2162   EVEX_W_0F2A_P_3,
2163   EVEX_W_0F2B_P_0,
2164   EVEX_W_0F2B_P_2,
2165   EVEX_W_0F2E_P_0,
2166   EVEX_W_0F2E_P_2,
2167   EVEX_W_0F2F_P_0,
2168   EVEX_W_0F2F_P_2,
2169   EVEX_W_0F51_P_0,
2170   EVEX_W_0F51_P_1,
2171   EVEX_W_0F51_P_2,
2172   EVEX_W_0F51_P_3,
2173   EVEX_W_0F54_P_0,
2174   EVEX_W_0F54_P_2,
2175   EVEX_W_0F55_P_0,
2176   EVEX_W_0F55_P_2,
2177   EVEX_W_0F56_P_0,
2178   EVEX_W_0F56_P_2,
2179   EVEX_W_0F57_P_0,
2180   EVEX_W_0F57_P_2,
2181   EVEX_W_0F58_P_0,
2182   EVEX_W_0F58_P_1,
2183   EVEX_W_0F58_P_2,
2184   EVEX_W_0F58_P_3,
2185   EVEX_W_0F59_P_0,
2186   EVEX_W_0F59_P_1,
2187   EVEX_W_0F59_P_2,
2188   EVEX_W_0F59_P_3,
2189   EVEX_W_0F5A_P_0,
2190   EVEX_W_0F5A_P_1,
2191   EVEX_W_0F5A_P_2,
2192   EVEX_W_0F5A_P_3,
2193   EVEX_W_0F5B_P_0,
2194   EVEX_W_0F5B_P_1,
2195   EVEX_W_0F5B_P_2,
2196   EVEX_W_0F5C_P_0,
2197   EVEX_W_0F5C_P_1,
2198   EVEX_W_0F5C_P_2,
2199   EVEX_W_0F5C_P_3,
2200   EVEX_W_0F5D_P_0,
2201   EVEX_W_0F5D_P_1,
2202   EVEX_W_0F5D_P_2,
2203   EVEX_W_0F5D_P_3,
2204   EVEX_W_0F5E_P_0,
2205   EVEX_W_0F5E_P_1,
2206   EVEX_W_0F5E_P_2,
2207   EVEX_W_0F5E_P_3,
2208   EVEX_W_0F5F_P_0,
2209   EVEX_W_0F5F_P_1,
2210   EVEX_W_0F5F_P_2,
2211   EVEX_W_0F5F_P_3,
2212   EVEX_W_0F62_P_2,
2213   EVEX_W_0F66_P_2,
2214   EVEX_W_0F6A_P_2,
2215   EVEX_W_0F6B_P_2,
2216   EVEX_W_0F6C_P_2,
2217   EVEX_W_0F6D_P_2,
2218   EVEX_W_0F6E_P_2,
2219   EVEX_W_0F6F_P_1,
2220   EVEX_W_0F6F_P_2,
2221   EVEX_W_0F6F_P_3,
2222   EVEX_W_0F70_P_2,
2223   EVEX_W_0F72_R_2_P_2,
2224   EVEX_W_0F72_R_6_P_2,
2225   EVEX_W_0F73_R_2_P_2,
2226   EVEX_W_0F73_R_6_P_2,
2227   EVEX_W_0F76_P_2,
2228   EVEX_W_0F78_P_0,
2229   EVEX_W_0F78_P_2,
2230   EVEX_W_0F79_P_0,
2231   EVEX_W_0F79_P_2,
2232   EVEX_W_0F7A_P_1,
2233   EVEX_W_0F7A_P_2,
2234   EVEX_W_0F7A_P_3,
2235   EVEX_W_0F7B_P_1,
2236   EVEX_W_0F7B_P_2,
2237   EVEX_W_0F7B_P_3,
2238   EVEX_W_0F7E_P_1,
2239   EVEX_W_0F7E_P_2,
2240   EVEX_W_0F7F_P_1,
2241   EVEX_W_0F7F_P_2,
2242   EVEX_W_0F7F_P_3,
2243   EVEX_W_0FC2_P_0,
2244   EVEX_W_0FC2_P_1,
2245   EVEX_W_0FC2_P_2,
2246   EVEX_W_0FC2_P_3,
2247   EVEX_W_0FC6_P_0,
2248   EVEX_W_0FC6_P_2,
2249   EVEX_W_0FD2_P_2,
2250   EVEX_W_0FD3_P_2,
2251   EVEX_W_0FD4_P_2,
2252   EVEX_W_0FD6_P_2,
2253   EVEX_W_0FE6_P_1,
2254   EVEX_W_0FE6_P_2,
2255   EVEX_W_0FE6_P_3,
2256   EVEX_W_0FE7_P_2,
2257   EVEX_W_0FF2_P_2,
2258   EVEX_W_0FF3_P_2,
2259   EVEX_W_0FF4_P_2,
2260   EVEX_W_0FFA_P_2,
2261   EVEX_W_0FFB_P_2,
2262   EVEX_W_0FFE_P_2,
2263   EVEX_W_0F380C_P_2,
2264   EVEX_W_0F380D_P_2,
2265   EVEX_W_0F3810_P_1,
2266   EVEX_W_0F3810_P_2,
2267   EVEX_W_0F3811_P_1,
2268   EVEX_W_0F3811_P_2,
2269   EVEX_W_0F3812_P_1,
2270   EVEX_W_0F3812_P_2,
2271   EVEX_W_0F3813_P_1,
2272   EVEX_W_0F3813_P_2,
2273   EVEX_W_0F3814_P_1,
2274   EVEX_W_0F3815_P_1,
2275   EVEX_W_0F3818_P_2,
2276   EVEX_W_0F3819_P_2,
2277   EVEX_W_0F381A_P_2,
2278   EVEX_W_0F381B_P_2,
2279   EVEX_W_0F381E_P_2,
2280   EVEX_W_0F381F_P_2,
2281   EVEX_W_0F3820_P_1,
2282   EVEX_W_0F3821_P_1,
2283   EVEX_W_0F3822_P_1,
2284   EVEX_W_0F3823_P_1,
2285   EVEX_W_0F3824_P_1,
2286   EVEX_W_0F3825_P_1,
2287   EVEX_W_0F3825_P_2,
2288   EVEX_W_0F3826_P_1,
2289   EVEX_W_0F3826_P_2,
2290   EVEX_W_0F3828_P_1,
2291   EVEX_W_0F3828_P_2,
2292   EVEX_W_0F3829_P_1,
2293   EVEX_W_0F3829_P_2,
2294   EVEX_W_0F382A_P_1,
2295   EVEX_W_0F382A_P_2,
2296   EVEX_W_0F382B_P_2,
2297   EVEX_W_0F3830_P_1,
2298   EVEX_W_0F3831_P_1,
2299   EVEX_W_0F3832_P_1,
2300   EVEX_W_0F3833_P_1,
2301   EVEX_W_0F3834_P_1,
2302   EVEX_W_0F3835_P_1,
2303   EVEX_W_0F3835_P_2,
2304   EVEX_W_0F3837_P_2,
2305   EVEX_W_0F3838_P_1,
2306   EVEX_W_0F3839_P_1,
2307   EVEX_W_0F383A_P_1,
2308   EVEX_W_0F3840_P_2,
2309   EVEX_W_0F3858_P_2,
2310   EVEX_W_0F3859_P_2,
2311   EVEX_W_0F385A_P_2,
2312   EVEX_W_0F385B_P_2,
2313   EVEX_W_0F3866_P_2,
2314   EVEX_W_0F3875_P_2,
2315   EVEX_W_0F3878_P_2,
2316   EVEX_W_0F3879_P_2,
2317   EVEX_W_0F387A_P_2,
2318   EVEX_W_0F387B_P_2,
2319   EVEX_W_0F387D_P_2,
2320   EVEX_W_0F3883_P_2,
2321   EVEX_W_0F388D_P_2,
2322   EVEX_W_0F3891_P_2,
2323   EVEX_W_0F3893_P_2,
2324   EVEX_W_0F38A1_P_2,
2325   EVEX_W_0F38A3_P_2,
2326   EVEX_W_0F38C7_R_1_P_2,
2327   EVEX_W_0F38C7_R_2_P_2,
2328   EVEX_W_0F38C7_R_5_P_2,
2329   EVEX_W_0F38C7_R_6_P_2,
2330
2331   EVEX_W_0F3A00_P_2,
2332   EVEX_W_0F3A01_P_2,
2333   EVEX_W_0F3A04_P_2,
2334   EVEX_W_0F3A05_P_2,
2335   EVEX_W_0F3A08_P_2,
2336   EVEX_W_0F3A09_P_2,
2337   EVEX_W_0F3A0A_P_2,
2338   EVEX_W_0F3A0B_P_2,
2339   EVEX_W_0F3A16_P_2,
2340   EVEX_W_0F3A18_P_2,
2341   EVEX_W_0F3A19_P_2,
2342   EVEX_W_0F3A1A_P_2,
2343   EVEX_W_0F3A1B_P_2,
2344   EVEX_W_0F3A1D_P_2,
2345   EVEX_W_0F3A21_P_2,
2346   EVEX_W_0F3A22_P_2,
2347   EVEX_W_0F3A23_P_2,
2348   EVEX_W_0F3A38_P_2,
2349   EVEX_W_0F3A39_P_2,
2350   EVEX_W_0F3A3A_P_2,
2351   EVEX_W_0F3A3B_P_2,
2352   EVEX_W_0F3A3E_P_2,
2353   EVEX_W_0F3A3F_P_2,
2354   EVEX_W_0F3A42_P_2,
2355   EVEX_W_0F3A43_P_2,
2356   EVEX_W_0F3A50_P_2,
2357   EVEX_W_0F3A51_P_2,
2358   EVEX_W_0F3A56_P_2,
2359   EVEX_W_0F3A57_P_2,
2360   EVEX_W_0F3A66_P_2,
2361   EVEX_W_0F3A67_P_2
2362 };
2363
2364 typedef void (*op_rtn) (int bytemode, int sizeflag);
2365
2366 struct dis386 {
2367   const char *name;
2368   struct
2369     {
2370       op_rtn rtn;
2371       int bytemode;
2372     } op[MAX_OPERANDS];
2373   unsigned int prefix_requirement;
2374 };
2375
2376 /* Upper case letters in the instruction names here are macros.
2377    'A' => print 'b' if no register operands or suffix_always is true
2378    'B' => print 'b' if suffix_always is true
2379    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2380           size prefix
2381    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2382           suffix_always is true
2383    'E' => print 'e' if 32-bit form of jcxz
2384    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2385    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2386    'H' => print ",pt" or ",pn" branch hint
2387    'I' => honor following macro letter even in Intel mode (implemented only
2388           for some of the macro letters)
2389    'J' => print 'l'
2390    'K' => print 'd' or 'q' if rex prefix is present.
2391    'L' => print 'l' if suffix_always is true
2392    'M' => print 'r' if intel_mnemonic is false.
2393    'N' => print 'n' if instruction has no wait "prefix"
2394    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2395    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2396           or suffix_always is true.  print 'q' if rex prefix is present.
2397    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2398           is true
2399    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2400    'S' => print 'w', 'l' or 'q' if suffix_always is true
2401    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2402    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2403    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2404    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2405    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2406    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2407           suffix_always is true.
2408    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2409    '!' => change condition from true to false or from false to true.
2410    '%' => add 1 upper case letter to the macro.
2411
2412    2 upper case letter macros:
2413    "XY" => print 'x' or 'y' if no register operands or suffix_always
2414            is true.
2415    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2416    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2417            or suffix_always is true
2418    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2419    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2420    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2421    "LW" => print 'd', 'q' depending on the VEX.W bit
2422    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2423            an operand size prefix, or suffix_always is true.  print
2424            'q' if rex prefix is present.
2425
2426    Many of the above letters print nothing in Intel mode.  See "putop"
2427    for the details.
2428
2429    Braces '{' and '}', and vertical bars '|', indicate alternative
2430    mnemonic strings for AT&T and Intel.  */
2431
2432 static const struct dis386 dis386[] = {
2433   /* 00 */
2434   { "addB",             { Ebh1, Gb }, 0 },
2435   { "addS",             { Evh1, Gv }, 0 },
2436   { "addB",             { Gb, EbS }, 0 },
2437   { "addS",             { Gv, EvS }, 0 },
2438   { "addB",             { AL, Ib }, 0 },
2439   { "addS",             { eAX, Iv }, 0 },
2440   { X86_64_TABLE (X86_64_06) },
2441   { X86_64_TABLE (X86_64_07) },
2442   /* 08 */
2443   { "orB",              { Ebh1, Gb }, 0 },
2444   { "orS",              { Evh1, Gv }, 0 },
2445   { "orB",              { Gb, EbS }, 0 },
2446   { "orS",              { Gv, EvS }, 0 },
2447   { "orB",              { AL, Ib }, 0 },
2448   { "orS",              { eAX, Iv }, 0 },
2449   { X86_64_TABLE (X86_64_0D) },
2450   { Bad_Opcode },       /* 0x0f extended opcode escape */
2451   /* 10 */
2452   { "adcB",             { Ebh1, Gb }, 0 },
2453   { "adcS",             { Evh1, Gv }, 0 },
2454   { "adcB",             { Gb, EbS }, 0 },
2455   { "adcS",             { Gv, EvS }, 0 },
2456   { "adcB",             { AL, Ib }, 0 },
2457   { "adcS",             { eAX, Iv }, 0 },
2458   { X86_64_TABLE (X86_64_16) },
2459   { X86_64_TABLE (X86_64_17) },
2460   /* 18 */
2461   { "sbbB",             { Ebh1, Gb }, 0 },
2462   { "sbbS",             { Evh1, Gv }, 0 },
2463   { "sbbB",             { Gb, EbS }, 0 },
2464   { "sbbS",             { Gv, EvS }, 0 },
2465   { "sbbB",             { AL, Ib }, 0 },
2466   { "sbbS",             { eAX, Iv }, 0 },
2467   { X86_64_TABLE (X86_64_1E) },
2468   { X86_64_TABLE (X86_64_1F) },
2469   /* 20 */
2470   { "andB",             { Ebh1, Gb }, 0 },
2471   { "andS",             { Evh1, Gv }, 0 },
2472   { "andB",             { Gb, EbS }, 0 },
2473   { "andS",             { Gv, EvS }, 0 },
2474   { "andB",             { AL, Ib }, 0 },
2475   { "andS",             { eAX, Iv }, 0 },
2476   { Bad_Opcode },       /* SEG ES prefix */
2477   { X86_64_TABLE (X86_64_27) },
2478   /* 28 */
2479   { "subB",             { Ebh1, Gb }, 0 },
2480   { "subS",             { Evh1, Gv }, 0 },
2481   { "subB",             { Gb, EbS }, 0 },
2482   { "subS",             { Gv, EvS }, 0 },
2483   { "subB",             { AL, Ib }, 0 },
2484   { "subS",             { eAX, Iv }, 0 },
2485   { Bad_Opcode },       /* SEG CS prefix */
2486   { X86_64_TABLE (X86_64_2F) },
2487   /* 30 */
2488   { "xorB",             { Ebh1, Gb }, 0 },
2489   { "xorS",             { Evh1, Gv }, 0 },
2490   { "xorB",             { Gb, EbS }, 0 },
2491   { "xorS",             { Gv, EvS }, 0 },
2492   { "xorB",             { AL, Ib }, 0 },
2493   { "xorS",             { eAX, Iv }, 0 },
2494   { Bad_Opcode },       /* SEG SS prefix */
2495   { X86_64_TABLE (X86_64_37) },
2496   /* 38 */
2497   { "cmpB",             { Eb, Gb }, 0 },
2498   { "cmpS",             { Ev, Gv }, 0 },
2499   { "cmpB",             { Gb, EbS }, 0 },
2500   { "cmpS",             { Gv, EvS }, 0 },
2501   { "cmpB",             { AL, Ib }, 0 },
2502   { "cmpS",             { eAX, Iv }, 0 },
2503   { Bad_Opcode },       /* SEG DS prefix */
2504   { X86_64_TABLE (X86_64_3F) },
2505   /* 40 */
2506   { "inc{S|}",          { RMeAX }, 0 },
2507   { "inc{S|}",          { RMeCX }, 0 },
2508   { "inc{S|}",          { RMeDX }, 0 },
2509   { "inc{S|}",          { RMeBX }, 0 },
2510   { "inc{S|}",          { RMeSP }, 0 },
2511   { "inc{S|}",          { RMeBP }, 0 },
2512   { "inc{S|}",          { RMeSI }, 0 },
2513   { "inc{S|}",          { RMeDI }, 0 },
2514   /* 48 */
2515   { "dec{S|}",          { RMeAX }, 0 },
2516   { "dec{S|}",          { RMeCX }, 0 },
2517   { "dec{S|}",          { RMeDX }, 0 },
2518   { "dec{S|}",          { RMeBX }, 0 },
2519   { "dec{S|}",          { RMeSP }, 0 },
2520   { "dec{S|}",          { RMeBP }, 0 },
2521   { "dec{S|}",          { RMeSI }, 0 },
2522   { "dec{S|}",          { RMeDI }, 0 },
2523   /* 50 */
2524   { "pushV",            { RMrAX }, 0 },
2525   { "pushV",            { RMrCX }, 0 },
2526   { "pushV",            { RMrDX }, 0 },
2527   { "pushV",            { RMrBX }, 0 },
2528   { "pushV",            { RMrSP }, 0 },
2529   { "pushV",            { RMrBP }, 0 },
2530   { "pushV",            { RMrSI }, 0 },
2531   { "pushV",            { RMrDI }, 0 },
2532   /* 58 */
2533   { "popV",             { RMrAX }, 0 },
2534   { "popV",             { RMrCX }, 0 },
2535   { "popV",             { RMrDX }, 0 },
2536   { "popV",             { RMrBX }, 0 },
2537   { "popV",             { RMrSP }, 0 },
2538   { "popV",             { RMrBP }, 0 },
2539   { "popV",             { RMrSI }, 0 },
2540   { "popV",             { RMrDI }, 0 },
2541   /* 60 */
2542   { X86_64_TABLE (X86_64_60) },
2543   { X86_64_TABLE (X86_64_61) },
2544   { X86_64_TABLE (X86_64_62) },
2545   { X86_64_TABLE (X86_64_63) },
2546   { Bad_Opcode },       /* seg fs */
2547   { Bad_Opcode },       /* seg gs */
2548   { Bad_Opcode },       /* op size prefix */
2549   { Bad_Opcode },       /* adr size prefix */
2550   /* 68 */
2551   { "pushT",            { sIv }, 0 },
2552   { "imulS",            { Gv, Ev, Iv }, 0 },
2553   { "pushT",            { sIbT }, 0 },
2554   { "imulS",            { Gv, Ev, sIb }, 0 },
2555   { "ins{b|}",          { Ybr, indirDX }, 0 },
2556   { X86_64_TABLE (X86_64_6D) },
2557   { "outs{b|}",         { indirDXr, Xb }, 0 },
2558   { X86_64_TABLE (X86_64_6F) },
2559   /* 70 */
2560   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2561   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2562   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2563   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2564   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2565   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2566   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2567   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2568   /* 78 */
2569   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2570   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2571   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2572   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2573   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2574   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2575   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2576   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2577   /* 80 */
2578   { REG_TABLE (REG_80) },
2579   { REG_TABLE (REG_81) },
2580   { Bad_Opcode },
2581   { REG_TABLE (REG_82) },
2582   { "testB",            { Eb, Gb }, 0 },
2583   { "testS",            { Ev, Gv }, 0 },
2584   { "xchgB",            { Ebh2, Gb }, 0 },
2585   { "xchgS",            { Evh2, Gv }, 0 },
2586   /* 88 */
2587   { "movB",             { Ebh3, Gb }, 0 },
2588   { "movS",             { Evh3, Gv }, 0 },
2589   { "movB",             { Gb, EbS }, 0 },
2590   { "movS",             { Gv, EvS }, 0 },
2591   { "movD",             { Sv, Sw }, 0 },
2592   { MOD_TABLE (MOD_8D) },
2593   { "movD",             { Sw, Sv }, 0 },
2594   { REG_TABLE (REG_8F) },
2595   /* 90 */
2596   { PREFIX_TABLE (PREFIX_90) },
2597   { "xchgS",            { RMeCX, eAX }, 0 },
2598   { "xchgS",            { RMeDX, eAX }, 0 },
2599   { "xchgS",            { RMeBX, eAX }, 0 },
2600   { "xchgS",            { RMeSP, eAX }, 0 },
2601   { "xchgS",            { RMeBP, eAX }, 0 },
2602   { "xchgS",            { RMeSI, eAX }, 0 },
2603   { "xchgS",            { RMeDI, eAX }, 0 },
2604   /* 98 */
2605   { "cW{t|}R",          { XX }, 0 },
2606   { "cR{t|}O",          { XX }, 0 },
2607   { X86_64_TABLE (X86_64_9A) },
2608   { Bad_Opcode },       /* fwait */
2609   { "pushfT",           { XX }, 0 },
2610   { "popfT",            { XX }, 0 },
2611   { "sahf",             { XX }, 0 },
2612   { "lahf",             { XX }, 0 },
2613   /* a0 */
2614   { "mov%LB",           { AL, Ob }, 0 },
2615   { "mov%LS",           { eAX, Ov }, 0 },
2616   { "mov%LB",           { Ob, AL }, 0 },
2617   { "mov%LS",           { Ov, eAX }, 0 },
2618   { "movs{b|}",         { Ybr, Xb }, 0 },
2619   { "movs{R|}",         { Yvr, Xv }, 0 },
2620   { "cmps{b|}",         { Xb, Yb }, 0 },
2621   { "cmps{R|}",         { Xv, Yv }, 0 },
2622   /* a8 */
2623   { "testB",            { AL, Ib }, 0 },
2624   { "testS",            { eAX, Iv }, 0 },
2625   { "stosB",            { Ybr, AL }, 0 },
2626   { "stosS",            { Yvr, eAX }, 0 },
2627   { "lodsB",            { ALr, Xb }, 0 },
2628   { "lodsS",            { eAXr, Xv }, 0 },
2629   { "scasB",            { AL, Yb }, 0 },
2630   { "scasS",            { eAX, Yv }, 0 },
2631   /* b0 */
2632   { "movB",             { RMAL, Ib }, 0 },
2633   { "movB",             { RMCL, Ib }, 0 },
2634   { "movB",             { RMDL, Ib }, 0 },
2635   { "movB",             { RMBL, Ib }, 0 },
2636   { "movB",             { RMAH, Ib }, 0 },
2637   { "movB",             { RMCH, Ib }, 0 },
2638   { "movB",             { RMDH, Ib }, 0 },
2639   { "movB",             { RMBH, Ib }, 0 },
2640   /* b8 */
2641   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2642   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2643   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2644   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2645   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2646   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2647   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2648   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2649   /* c0 */
2650   { REG_TABLE (REG_C0) },
2651   { REG_TABLE (REG_C1) },
2652   { "retT",             { Iw, BND }, 0 },
2653   { "retT",             { BND }, 0 },
2654   { X86_64_TABLE (X86_64_C4) },
2655   { X86_64_TABLE (X86_64_C5) },
2656   { REG_TABLE (REG_C6) },
2657   { REG_TABLE (REG_C7) },
2658   /* c8 */
2659   { "enterT",           { Iw, Ib }, 0 },
2660   { "leaveT",           { XX }, 0 },
2661   { "Jret{|f}P",        { Iw }, 0 },
2662   { "Jret{|f}P",        { XX }, 0 },
2663   { "int3",             { XX }, 0 },
2664   { "int",              { Ib }, 0 },
2665   { X86_64_TABLE (X86_64_CE) },
2666   { "iret%LP",          { XX }, 0 },
2667   /* d0 */
2668   { REG_TABLE (REG_D0) },
2669   { REG_TABLE (REG_D1) },
2670   { REG_TABLE (REG_D2) },
2671   { REG_TABLE (REG_D3) },
2672   { X86_64_TABLE (X86_64_D4) },
2673   { X86_64_TABLE (X86_64_D5) },
2674   { Bad_Opcode },
2675   { "xlat",             { DSBX }, 0 },
2676   /* d8 */
2677   { FLOAT },
2678   { FLOAT },
2679   { FLOAT },
2680   { FLOAT },
2681   { FLOAT },
2682   { FLOAT },
2683   { FLOAT },
2684   { FLOAT },
2685   /* e0 */
2686   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2687   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2688   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2689   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2690   { "inB",              { AL, Ib }, 0 },
2691   { "inG",              { zAX, Ib }, 0 },
2692   { "outB",             { Ib, AL }, 0 },
2693   { "outG",             { Ib, zAX }, 0 },
2694   /* e8 */
2695   { "callT",            { Jv, BND }, 0 },
2696   { "jmpT",             { Jv, BND }, 0 },
2697   { X86_64_TABLE (X86_64_EA) },
2698   { "jmp",              { Jb, BND }, 0 },
2699   { "inB",              { AL, indirDX }, 0 },
2700   { "inG",              { zAX, indirDX }, 0 },
2701   { "outB",             { indirDX, AL }, 0 },
2702   { "outG",             { indirDX, zAX }, 0 },
2703   /* f0 */
2704   { Bad_Opcode },       /* lock prefix */
2705   { "icebp",            { XX }, 0 },
2706   { Bad_Opcode },       /* repne */
2707   { Bad_Opcode },       /* repz */
2708   { "hlt",              { XX }, 0 },
2709   { "cmc",              { XX }, 0 },
2710   { REG_TABLE (REG_F6) },
2711   { REG_TABLE (REG_F7) },
2712   /* f8 */
2713   { "clc",              { XX }, 0 },
2714   { "stc",              { XX }, 0 },
2715   { "cli",              { XX }, 0 },
2716   { "sti",              { XX }, 0 },
2717   { "cld",              { XX }, 0 },
2718   { "std",              { XX }, 0 },
2719   { REG_TABLE (REG_FE) },
2720   { REG_TABLE (REG_FF) },
2721 };
2722
2723 static const struct dis386 dis386_twobyte[] = {
2724   /* 00 */
2725   { REG_TABLE (REG_0F00 ) },
2726   { REG_TABLE (REG_0F01 ) },
2727   { "larS",             { Gv, Ew }, 0 },
2728   { "lslS",             { Gv, Ew }, 0 },
2729   { Bad_Opcode },
2730   { "syscall",          { XX }, 0 },
2731   { "clts",             { XX }, 0 },
2732   { "sysret%LP",                { XX }, 0 },
2733   /* 08 */
2734   { "invd",             { XX }, 0 },
2735   { "wbinvd",           { XX }, 0 },
2736   { Bad_Opcode },
2737   { "ud2",              { XX }, 0 },
2738   { Bad_Opcode },
2739   { REG_TABLE (REG_0F0D) },
2740   { "femms",            { XX }, 0 },
2741   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2742   /* 10 */
2743   { PREFIX_TABLE (PREFIX_0F10) },
2744   { PREFIX_TABLE (PREFIX_0F11) },
2745   { PREFIX_TABLE (PREFIX_0F12) },
2746   { MOD_TABLE (MOD_0F13) },
2747   { "unpcklpX",         { XM, EXx }, PREFIX_MANDATORY },
2748   { "unpckhpX",         { XM, EXx }, PREFIX_MANDATORY },
2749   { PREFIX_TABLE (PREFIX_0F16) },
2750   { MOD_TABLE (MOD_0F17) },
2751   /* 18 */
2752   { REG_TABLE (REG_0F18) },
2753   { "nopQ",             { Ev }, 0 },
2754   { PREFIX_TABLE (PREFIX_0F1A) },
2755   { PREFIX_TABLE (PREFIX_0F1B) },
2756   { "nopQ",             { Ev }, 0 },
2757   { "nopQ",             { Ev }, 0 },
2758   { "nopQ",             { Ev }, 0 },
2759   { "nopQ",             { Ev }, 0 },
2760   /* 20 */
2761   { "movZ",             { Rm, Cm }, 0 },
2762   { "movZ",             { Rm, Dm }, 0 },
2763   { "movZ",             { Cm, Rm }, 0 },
2764   { "movZ",             { Dm, Rm }, 0 },
2765   { MOD_TABLE (MOD_0F24) },
2766   { Bad_Opcode },
2767   { MOD_TABLE (MOD_0F26) },
2768   { Bad_Opcode },
2769   /* 28 */
2770   { "movapX",           { XM, EXx }, PREFIX_MANDATORY },
2771   { "movapX",           { EXxS, XM }, PREFIX_MANDATORY },
2772   { PREFIX_TABLE (PREFIX_0F2A) },
2773   { PREFIX_TABLE (PREFIX_0F2B) },
2774   { PREFIX_TABLE (PREFIX_0F2C) },
2775   { PREFIX_TABLE (PREFIX_0F2D) },
2776   { PREFIX_TABLE (PREFIX_0F2E) },
2777   { PREFIX_TABLE (PREFIX_0F2F) },
2778   /* 30 */
2779   { "wrmsr",            { XX }, 0 },
2780   { "rdtsc",            { XX }, 0 },
2781   { "rdmsr",            { XX }, 0 },
2782   { "rdpmc",            { XX }, 0 },
2783   { "sysenter",         { XX }, 0 },
2784   { "sysexit",          { XX }, 0 },
2785   { Bad_Opcode },
2786   { "getsec",           { XX }, 0 },
2787   /* 38 */
2788   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_MANDATORY) },
2789   { Bad_Opcode },
2790   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_MANDATORY) },
2791   { Bad_Opcode },
2792   { Bad_Opcode },
2793   { Bad_Opcode },
2794   { Bad_Opcode },
2795   { Bad_Opcode },
2796   /* 40 */
2797   { "cmovoS",           { Gv, Ev }, 0 },
2798   { "cmovnoS",          { Gv, Ev }, 0 },
2799   { "cmovbS",           { Gv, Ev }, 0 },
2800   { "cmovaeS",          { Gv, Ev }, 0 },
2801   { "cmoveS",           { Gv, Ev }, 0 },
2802   { "cmovneS",          { Gv, Ev }, 0 },
2803   { "cmovbeS",          { Gv, Ev }, 0 },
2804   { "cmovaS",           { Gv, Ev }, 0 },
2805   /* 48 */
2806   { "cmovsS",           { Gv, Ev }, 0 },
2807   { "cmovnsS",          { Gv, Ev }, 0 },
2808   { "cmovpS",           { Gv, Ev }, 0 },
2809   { "cmovnpS",          { Gv, Ev }, 0 },
2810   { "cmovlS",           { Gv, Ev }, 0 },
2811   { "cmovgeS",          { Gv, Ev }, 0 },
2812   { "cmovleS",          { Gv, Ev }, 0 },
2813   { "cmovgS",           { Gv, Ev }, 0 },
2814   /* 50 */
2815   { MOD_TABLE (MOD_0F51) },
2816   { PREFIX_TABLE (PREFIX_0F51) },
2817   { PREFIX_TABLE (PREFIX_0F52) },
2818   { PREFIX_TABLE (PREFIX_0F53) },
2819   { "andpX",            { XM, EXx }, PREFIX_MANDATORY },
2820   { "andnpX",           { XM, EXx }, PREFIX_MANDATORY },
2821   { "orpX",             { XM, EXx }, PREFIX_MANDATORY },
2822   { "xorpX",            { XM, EXx }, PREFIX_MANDATORY },
2823   /* 58 */
2824   { PREFIX_TABLE (PREFIX_0F58) },
2825   { PREFIX_TABLE (PREFIX_0F59) },
2826   { PREFIX_TABLE (PREFIX_0F5A) },
2827   { PREFIX_TABLE (PREFIX_0F5B) },
2828   { PREFIX_TABLE (PREFIX_0F5C) },
2829   { PREFIX_TABLE (PREFIX_0F5D) },
2830   { PREFIX_TABLE (PREFIX_0F5E) },
2831   { PREFIX_TABLE (PREFIX_0F5F) },
2832   /* 60 */
2833   { PREFIX_TABLE (PREFIX_0F60) },
2834   { PREFIX_TABLE (PREFIX_0F61) },
2835   { PREFIX_TABLE (PREFIX_0F62) },
2836   { "packsswb",         { MX, EM }, PREFIX_MANDATORY },
2837   { "pcmpgtb",          { MX, EM }, PREFIX_MANDATORY },
2838   { "pcmpgtw",          { MX, EM }, PREFIX_MANDATORY },
2839   { "pcmpgtd",          { MX, EM }, PREFIX_MANDATORY },
2840   { "packuswb",         { MX, EM }, PREFIX_MANDATORY },
2841   /* 68 */
2842   { "punpckhbw",        { MX, EM }, PREFIX_MANDATORY },
2843   { "punpckhwd",        { MX, EM }, PREFIX_MANDATORY },
2844   { "punpckhdq",        { MX, EM }, PREFIX_MANDATORY },
2845   { "packssdw",         { MX, EM }, PREFIX_MANDATORY },
2846   { PREFIX_TABLE (PREFIX_0F6C) },
2847   { PREFIX_TABLE (PREFIX_0F6D) },
2848   { "movK",             { MX, Edq }, PREFIX_MANDATORY },
2849   { PREFIX_TABLE (PREFIX_0F6F) },
2850   /* 70 */
2851   { PREFIX_TABLE (PREFIX_0F70) },
2852   { REG_TABLE (REG_0F71) },
2853   { REG_TABLE (REG_0F72) },
2854   { REG_TABLE (REG_0F73) },
2855   { "pcmpeqb",          { MX, EM }, PREFIX_MANDATORY },
2856   { "pcmpeqw",          { MX, EM }, PREFIX_MANDATORY },
2857   { "pcmpeqd",          { MX, EM }, PREFIX_MANDATORY },
2858   { "emms",             { XX }, PREFIX_MANDATORY },
2859   /* 78 */
2860   { PREFIX_TABLE (PREFIX_0F78) },
2861   { PREFIX_TABLE (PREFIX_0F79) },
2862   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2863   { Bad_Opcode },
2864   { PREFIX_TABLE (PREFIX_0F7C) },
2865   { PREFIX_TABLE (PREFIX_0F7D) },
2866   { PREFIX_TABLE (PREFIX_0F7E) },
2867   { PREFIX_TABLE (PREFIX_0F7F) },
2868   /* 80 */
2869   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2870   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2871   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2872   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2873   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2874   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2875   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2876   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2877   /* 88 */
2878   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2879   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2880   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2881   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2882   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2883   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2884   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2885   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2886   /* 90 */
2887   { "seto",             { Eb }, 0 },
2888   { "setno",            { Eb }, 0 },
2889   { "setb",             { Eb }, 0 },
2890   { "setae",            { Eb }, 0 },
2891   { "sete",             { Eb }, 0 },
2892   { "setne",            { Eb }, 0 },
2893   { "setbe",            { Eb }, 0 },
2894   { "seta",             { Eb }, 0 },
2895   /* 98 */
2896   { "sets",             { Eb }, 0 },
2897   { "setns",            { Eb }, 0 },
2898   { "setp",             { Eb }, 0 },
2899   { "setnp",            { Eb }, 0 },
2900   { "setl",             { Eb }, 0 },
2901   { "setge",            { Eb }, 0 },
2902   { "setle",            { Eb }, 0 },
2903   { "setg",             { Eb }, 0 },
2904   /* a0 */
2905   { "pushT",            { fs }, 0 },
2906   { "popT",             { fs }, 0 },
2907   { "cpuid",            { XX }, 0 },
2908   { "btS",              { Ev, Gv }, 0 },
2909   { "shldS",            { Ev, Gv, Ib }, 0 },
2910   { "shldS",            { Ev, Gv, CL }, 0 },
2911   { REG_TABLE (REG_0FA6) },
2912   { REG_TABLE (REG_0FA7) },
2913   /* a8 */
2914   { "pushT",            { gs }, 0 },
2915   { "popT",             { gs }, 0 },
2916   { "rsm",              { XX }, 0 },
2917   { "btsS",             { Evh1, Gv }, 0 },
2918   { "shrdS",            { Ev, Gv, Ib }, 0 },
2919   { "shrdS",            { Ev, Gv, CL }, 0 },
2920   { REG_TABLE (REG_0FAE) },
2921   { "imulS",            { Gv, Ev }, 0 },
2922   /* b0 */
2923   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2924   { "cmpxchgS",         { Evh1, Gv }, 0 },
2925   { MOD_TABLE (MOD_0FB2) },
2926   { "btrS",             { Evh1, Gv }, 0 },
2927   { MOD_TABLE (MOD_0FB4) },
2928   { MOD_TABLE (MOD_0FB5) },
2929   { "movz{bR|x}",       { Gv, Eb }, 0 },
2930   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2931   /* b8 */
2932   { PREFIX_TABLE (PREFIX_0FB8) },
2933   { "ud1",              { XX }, 0 },
2934   { REG_TABLE (REG_0FBA) },
2935   { "btcS",             { Evh1, Gv }, 0 },
2936   { PREFIX_TABLE (PREFIX_0FBC) },
2937   { PREFIX_TABLE (PREFIX_0FBD) },
2938   { "movs{bR|x}",       { Gv, Eb }, 0 },
2939   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2940   /* c0 */
2941   { "xaddB",            { Ebh1, Gb }, 0 },
2942   { "xaddS",            { Evh1, Gv }, 0 },
2943   { PREFIX_TABLE (PREFIX_0FC2) },
2944   { PREFIX_TABLE (PREFIX_0FC3) },
2945   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_MANDATORY },
2946   { "pextrw",           { Gdq, MS, Ib }, PREFIX_MANDATORY },
2947   { "shufpX",           { XM, EXx, Ib }, PREFIX_MANDATORY },
2948   { REG_TABLE (REG_0FC7) },
2949   /* c8 */
2950   { "bswap",            { RMeAX }, 0 },
2951   { "bswap",            { RMeCX }, 0 },
2952   { "bswap",            { RMeDX }, 0 },
2953   { "bswap",            { RMeBX }, 0 },
2954   { "bswap",            { RMeSP }, 0 },
2955   { "bswap",            { RMeBP }, 0 },
2956   { "bswap",            { RMeSI }, 0 },
2957   { "bswap",            { RMeDI }, 0 },
2958   /* d0 */
2959   { PREFIX_TABLE (PREFIX_0FD0) },
2960   { "psrlw",            { MX, EM }, PREFIX_MANDATORY },
2961   { "psrld",            { MX, EM }, PREFIX_MANDATORY },
2962   { "psrlq",            { MX, EM }, PREFIX_MANDATORY },
2963   { "paddq",            { MX, EM }, PREFIX_MANDATORY },
2964   { "pmullw",           { MX, EM }, PREFIX_MANDATORY },
2965   { PREFIX_TABLE (PREFIX_0FD6) },
2966   { MOD_TABLE (MOD_0FD7) },
2967   /* d8 */
2968   { "psubusb",          { MX, EM }, PREFIX_MANDATORY },
2969   { "psubusw",          { MX, EM }, PREFIX_MANDATORY },
2970   { "pminub",           { MX, EM }, PREFIX_MANDATORY },
2971   { "pand",             { MX, EM }, PREFIX_MANDATORY },
2972   { "paddusb",          { MX, EM }, PREFIX_MANDATORY },
2973   { "paddusw",          { MX, EM }, PREFIX_MANDATORY },
2974   { "pmaxub",           { MX, EM }, PREFIX_MANDATORY },
2975   { "pandn",            { MX, EM }, PREFIX_MANDATORY },
2976   /* e0 */
2977   { "pavgb",            { MX, EM }, PREFIX_MANDATORY },
2978   { "psraw",            { MX, EM }, PREFIX_MANDATORY },
2979   { "psrad",            { MX, EM }, PREFIX_MANDATORY },
2980   { "pavgw",            { MX, EM }, PREFIX_MANDATORY },
2981   { "pmulhuw",          { MX, EM }, PREFIX_MANDATORY },
2982   { "pmulhw",           { MX, EM }, PREFIX_MANDATORY },
2983   { PREFIX_TABLE (PREFIX_0FE6) },
2984   { PREFIX_TABLE (PREFIX_0FE7) },
2985   /* e8 */
2986   { "psubsb",           { MX, EM }, PREFIX_MANDATORY },
2987   { "psubsw",           { MX, EM }, PREFIX_MANDATORY },
2988   { "pminsw",           { MX, EM }, PREFIX_MANDATORY },
2989   { "por",              { MX, EM }, PREFIX_MANDATORY },
2990   { "paddsb",           { MX, EM }, PREFIX_MANDATORY },
2991   { "paddsw",           { MX, EM }, PREFIX_MANDATORY },
2992   { "pmaxsw",           { MX, EM }, PREFIX_MANDATORY },
2993   { "pxor",             { MX, EM }, PREFIX_MANDATORY },
2994   /* f0 */
2995   { PREFIX_TABLE (PREFIX_0FF0) },
2996   { "psllw",            { MX, EM }, PREFIX_MANDATORY },
2997   { "pslld",            { MX, EM }, PREFIX_MANDATORY },
2998   { "psllq",            { MX, EM }, PREFIX_MANDATORY },
2999   { "pmuludq",          { MX, EM }, PREFIX_MANDATORY },
3000   { "pmaddwd",          { MX, EM }, PREFIX_MANDATORY },
3001   { "psadbw",           { MX, EM }, PREFIX_MANDATORY },
3002   { PREFIX_TABLE (PREFIX_0FF7) },
3003   /* f8 */
3004   { "psubb",            { MX, EM }, PREFIX_MANDATORY },
3005   { "psubw",            { MX, EM }, PREFIX_MANDATORY },
3006   { "psubd",            { MX, EM }, PREFIX_MANDATORY },
3007   { "psubq",            { MX, EM }, PREFIX_MANDATORY },
3008   { "paddb",            { MX, EM }, PREFIX_MANDATORY },
3009   { "paddw",            { MX, EM }, PREFIX_MANDATORY },
3010   { "paddd",            { MX, EM }, PREFIX_MANDATORY },
3011   { Bad_Opcode },
3012 };
3013
3014 static const unsigned char onebyte_has_modrm[256] = {
3015   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3016   /*       -------------------------------        */
3017   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3018   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3019   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3020   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3021   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3022   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3023   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3024   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3025   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3026   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3027   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3028   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3029   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3030   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3031   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3032   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3033   /*       -------------------------------        */
3034   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3035 };
3036
3037 static const unsigned char twobyte_has_modrm[256] = {
3038   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3039   /*       -------------------------------        */
3040   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3041   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3042   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3043   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3044   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3045   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3046   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3047   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3048   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3049   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3050   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3051   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3052   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3053   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3054   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3055   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3056   /*       -------------------------------        */
3057   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3058 };
3059
3060 static char obuf[100];
3061 static char *obufp;
3062 static char *mnemonicendp;
3063 static char scratchbuf[100];
3064 static unsigned char *start_codep;
3065 static unsigned char *insn_codep;
3066 static unsigned char *codep;
3067 static unsigned char *end_codep;
3068 static int last_lock_prefix;
3069 static int last_repz_prefix;
3070 static int last_repnz_prefix;
3071 static int last_data_prefix;
3072 static int last_addr_prefix;
3073 static int last_rex_prefix;
3074 static int last_seg_prefix;
3075 static int fwait_prefix;
3076 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory.  */
3077 static int mandatory_prefix;
3078 /* The active segment register prefix.  */
3079 static int active_seg_prefix;
3080 #define MAX_CODE_LENGTH 15
3081 /* We can up to 14 prefixes since the maximum instruction length is
3082    15bytes.  */
3083 static int all_prefixes[MAX_CODE_LENGTH - 1];
3084 static disassemble_info *the_info;
3085 static struct
3086   {
3087     int mod;
3088     int reg;
3089     int rm;
3090   }
3091 modrm;
3092 static unsigned char need_modrm;
3093 static struct
3094   {
3095     int scale;
3096     int index;
3097     int base;
3098   }
3099 sib;
3100 static struct
3101   {
3102     int register_specifier;
3103     int length;
3104     int prefix;
3105     int w;
3106     int evex;
3107     int r;
3108     int v;
3109     int mask_register_specifier;
3110     int zeroing;
3111     int ll;
3112     int b;
3113   }
3114 vex;
3115 static unsigned char need_vex;
3116 static unsigned char need_vex_reg;
3117 static unsigned char vex_w_done;
3118
3119 struct op
3120   {
3121     const char *name;
3122     unsigned int len;
3123   };
3124
3125 /* If we are accessing mod/rm/reg without need_modrm set, then the
3126    values are stale.  Hitting this abort likely indicates that you
3127    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3128 #define MODRM_CHECK  if (!need_modrm) abort ()
3129
3130 static const char **names64;
3131 static const char **names32;
3132 static const char **names16;
3133 static const char **names8;
3134 static const char **names8rex;
3135 static const char **names_seg;
3136 static const char *index64;
3137 static const char *index32;
3138 static const char **index16;
3139 static const char **names_bnd;
3140
3141 static const char *intel_names64[] = {
3142   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3143   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3144 };
3145 static const char *intel_names32[] = {
3146   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3147   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3148 };
3149 static const char *intel_names16[] = {
3150   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3151   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3152 };
3153 static const char *intel_names8[] = {
3154   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3155 };
3156 static const char *intel_names8rex[] = {
3157   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3158   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3159 };
3160 static const char *intel_names_seg[] = {
3161   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3162 };
3163 static const char *intel_index64 = "riz";
3164 static const char *intel_index32 = "eiz";
3165 static const char *intel_index16[] = {
3166   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3167 };
3168
3169 static const char *att_names64[] = {
3170   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3171   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3172 };
3173 static const char *att_names32[] = {
3174   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3175   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3176 };
3177 static const char *att_names16[] = {
3178   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3179   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3180 };
3181 static const char *att_names8[] = {
3182   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3183 };
3184 static const char *att_names8rex[] = {
3185   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3186   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3187 };
3188 static const char *att_names_seg[] = {
3189   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3190 };
3191 static const char *att_index64 = "%riz";
3192 static const char *att_index32 = "%eiz";
3193 static const char *att_index16[] = {
3194   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3195 };
3196
3197 static const char **names_mm;
3198 static const char *intel_names_mm[] = {
3199   "mm0", "mm1", "mm2", "mm3",
3200   "mm4", "mm5", "mm6", "mm7"
3201 };
3202 static const char *att_names_mm[] = {
3203   "%mm0", "%mm1", "%mm2", "%mm3",
3204   "%mm4", "%mm5", "%mm6", "%mm7"
3205 };
3206
3207 static const char *intel_names_bnd[] = {
3208   "bnd0", "bnd1", "bnd2", "bnd3"
3209 };
3210
3211 static const char *att_names_bnd[] = {
3212   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3213 };
3214
3215 static const char **names_xmm;
3216 static const char *intel_names_xmm[] = {
3217   "xmm0", "xmm1", "xmm2", "xmm3",
3218   "xmm4", "xmm5", "xmm6", "xmm7",
3219   "xmm8", "xmm9", "xmm10", "xmm11",
3220   "xmm12", "xmm13", "xmm14", "xmm15",
3221   "xmm16", "xmm17", "xmm18", "xmm19",
3222   "xmm20", "xmm21", "xmm22", "xmm23",
3223   "xmm24", "xmm25", "xmm26", "xmm27",
3224   "xmm28", "xmm29", "xmm30", "xmm31"
3225 };
3226 static const char *att_names_xmm[] = {
3227   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3228   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3229   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3230   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3231   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3232   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3233   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3234   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3235 };
3236
3237 static const char **names_ymm;
3238 static const char *intel_names_ymm[] = {
3239   "ymm0", "ymm1", "ymm2", "ymm3",
3240   "ymm4", "ymm5", "ymm6", "ymm7",
3241   "ymm8", "ymm9", "ymm10", "ymm11",
3242   "ymm12", "ymm13", "ymm14", "ymm15",
3243   "ymm16", "ymm17", "ymm18", "ymm19",
3244   "ymm20", "ymm21", "ymm22", "ymm23",
3245   "ymm24", "ymm25", "ymm26", "ymm27",
3246   "ymm28", "ymm29", "ymm30", "ymm31"
3247 };
3248 static const char *att_names_ymm[] = {
3249   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3250   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3251   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3252   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3253   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3254   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3255   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3256   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3257 };
3258
3259 static const char **names_zmm;
3260 static const char *intel_names_zmm[] = {
3261   "zmm0", "zmm1", "zmm2", "zmm3",
3262   "zmm4", "zmm5", "zmm6", "zmm7",
3263   "zmm8", "zmm9", "zmm10", "zmm11",
3264   "zmm12", "zmm13", "zmm14", "zmm15",
3265   "zmm16", "zmm17", "zmm18", "zmm19",
3266   "zmm20", "zmm21", "zmm22", "zmm23",
3267   "zmm24", "zmm25", "zmm26", "zmm27",
3268   "zmm28", "zmm29", "zmm30", "zmm31"
3269 };
3270 static const char *att_names_zmm[] = {
3271   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3272   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3273   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3274   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3275   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3276   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3277   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3278   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3279 };
3280
3281 static const char **names_mask;
3282 static const char *intel_names_mask[] = {
3283   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3284 };
3285 static const char *att_names_mask[] = {
3286   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3287 };
3288
3289 static const char *names_rounding[] =
3290 {
3291   "{rn-sae}",
3292   "{rd-sae}",
3293   "{ru-sae}",
3294   "{rz-sae}"
3295 };
3296
3297 static const struct dis386 reg_table[][8] = {
3298   /* REG_80 */
3299   {
3300     { "addA",   { Ebh1, Ib }, 0 },
3301     { "orA",    { Ebh1, Ib }, 0 },
3302     { "adcA",   { Ebh1, Ib }, 0 },
3303     { "sbbA",   { Ebh1, Ib }, 0 },
3304     { "andA",   { Ebh1, Ib }, 0 },
3305     { "subA",   { Ebh1, Ib }, 0 },
3306     { "xorA",   { Ebh1, Ib }, 0 },
3307     { "cmpA",   { Eb, Ib }, 0 },
3308   },
3309   /* REG_81 */
3310   {
3311     { "addQ",   { Evh1, Iv }, 0 },
3312     { "orQ",    { Evh1, Iv }, 0 },
3313     { "adcQ",   { Evh1, Iv }, 0 },
3314     { "sbbQ",   { Evh1, Iv }, 0 },
3315     { "andQ",   { Evh1, Iv }, 0 },
3316     { "subQ",   { Evh1, Iv }, 0 },
3317     { "xorQ",   { Evh1, Iv }, 0 },
3318     { "cmpQ",   { Ev, Iv }, 0 },
3319   },
3320   /* REG_82 */
3321   {
3322     { "addQ",   { Evh1, sIb }, 0 },
3323     { "orQ",    { Evh1, sIb }, 0 },
3324     { "adcQ",   { Evh1, sIb }, 0 },
3325     { "sbbQ",   { Evh1, sIb }, 0 },
3326     { "andQ",   { Evh1, sIb }, 0 },
3327     { "subQ",   { Evh1, sIb }, 0 },
3328     { "xorQ",   { Evh1, sIb }, 0 },
3329     { "cmpQ",   { Ev, sIb }, 0 },
3330   },
3331   /* REG_8F */
3332   {
3333     { "popU",   { stackEv }, 0 },
3334     { XOP_8F_TABLE (XOP_09) },
3335     { Bad_Opcode },
3336     { Bad_Opcode },
3337     { Bad_Opcode },
3338     { XOP_8F_TABLE (XOP_09) },
3339   },
3340   /* REG_C0 */
3341   {
3342     { "rolA",   { Eb, Ib }, 0 },
3343     { "rorA",   { Eb, Ib }, 0 },
3344     { "rclA",   { Eb, Ib }, 0 },
3345     { "rcrA",   { Eb, Ib }, 0 },
3346     { "shlA",   { Eb, Ib }, 0 },
3347     { "shrA",   { Eb, Ib }, 0 },
3348     { Bad_Opcode },
3349     { "sarA",   { Eb, Ib }, 0 },
3350   },
3351   /* REG_C1 */
3352   {
3353     { "rolQ",   { Ev, Ib }, 0 },
3354     { "rorQ",   { Ev, Ib }, 0 },
3355     { "rclQ",   { Ev, Ib }, 0 },
3356     { "rcrQ",   { Ev, Ib }, 0 },
3357     { "shlQ",   { Ev, Ib }, 0 },
3358     { "shrQ",   { Ev, Ib }, 0 },
3359     { Bad_Opcode },
3360     { "sarQ",   { Ev, Ib }, 0 },
3361   },
3362   /* REG_C6 */
3363   {
3364     { "movA",   { Ebh3, Ib }, 0 },
3365     { Bad_Opcode },
3366     { Bad_Opcode },
3367     { Bad_Opcode },
3368     { Bad_Opcode },
3369     { Bad_Opcode },
3370     { Bad_Opcode },
3371     { MOD_TABLE (MOD_C6_REG_7) },
3372   },
3373   /* REG_C7 */
3374   {
3375     { "movQ",   { Evh3, Iv }, 0 },
3376     { Bad_Opcode },
3377     { Bad_Opcode },
3378     { Bad_Opcode },
3379     { Bad_Opcode },
3380     { Bad_Opcode },
3381     { Bad_Opcode },
3382     { MOD_TABLE (MOD_C7_REG_7) },
3383   },
3384   /* REG_D0 */
3385   {
3386     { "rolA",   { Eb, I1 }, 0 },
3387     { "rorA",   { Eb, I1 }, 0 },
3388     { "rclA",   { Eb, I1 }, 0 },
3389     { "rcrA",   { Eb, I1 }, 0 },
3390     { "shlA",   { Eb, I1 }, 0 },
3391     { "shrA",   { Eb, I1 }, 0 },
3392     { Bad_Opcode },
3393     { "sarA",   { Eb, I1 }, 0 },
3394   },
3395   /* REG_D1 */
3396   {
3397     { "rolQ",   { Ev, I1 }, 0 },
3398     { "rorQ",   { Ev, I1 }, 0 },
3399     { "rclQ",   { Ev, I1 }, 0 },
3400     { "rcrQ",   { Ev, I1 }, 0 },
3401     { "shlQ",   { Ev, I1 }, 0 },
3402     { "shrQ",   { Ev, I1 }, 0 },
3403     { Bad_Opcode },
3404     { "sarQ",   { Ev, I1 }, 0 },
3405   },
3406   /* REG_D2 */
3407   {
3408     { "rolA",   { Eb, CL }, 0 },
3409     { "rorA",   { Eb, CL }, 0 },
3410     { "rclA",   { Eb, CL }, 0 },
3411     { "rcrA",   { Eb, CL }, 0 },
3412     { "shlA",   { Eb, CL }, 0 },
3413     { "shrA",   { Eb, CL }, 0 },
3414     { Bad_Opcode },
3415     { "sarA",   { Eb, CL }, 0 },
3416   },
3417   /* REG_D3 */
3418   {
3419     { "rolQ",   { Ev, CL }, 0 },
3420     { "rorQ",   { Ev, CL }, 0 },
3421     { "rclQ",   { Ev, CL }, 0 },
3422     { "rcrQ",   { Ev, CL }, 0 },
3423     { "shlQ",   { Ev, CL }, 0 },
3424     { "shrQ",   { Ev, CL }, 0 },
3425     { Bad_Opcode },
3426     { "sarQ",   { Ev, CL }, 0 },
3427   },
3428   /* REG_F6 */
3429   {
3430     { "testA",  { Eb, Ib }, 0 },
3431     { Bad_Opcode },
3432     { "notA",   { Ebh1 }, 0 },
3433     { "negA",   { Ebh1 }, 0 },
3434     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3435     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3436     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3437     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3438   },
3439   /* REG_F7 */
3440   {
3441     { "testQ",  { Ev, Iv }, 0 },
3442     { Bad_Opcode },
3443     { "notQ",   { Evh1 }, 0 },
3444     { "negQ",   { Evh1 }, 0 },
3445     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3446     { "imulQ",  { Ev }, 0 },
3447     { "divQ",   { Ev }, 0 },
3448     { "idivQ",  { Ev }, 0 },
3449   },
3450   /* REG_FE */
3451   {
3452     { "incA",   { Ebh1 }, 0 },
3453     { "decA",   { Ebh1 }, 0 },
3454   },
3455   /* REG_FF */
3456   {
3457     { "incQ",   { Evh1 }, 0 },
3458     { "decQ",   { Evh1 }, 0 },
3459     { "call{T|}", { indirEv, BND }, 0 },
3460     { MOD_TABLE (MOD_FF_REG_3) },
3461     { "jmp{T|}", { indirEv, BND }, 0 },
3462     { MOD_TABLE (MOD_FF_REG_5) },
3463     { "pushU",  { stackEv }, 0 },
3464     { Bad_Opcode },
3465   },
3466   /* REG_0F00 */
3467   {
3468     { "sldtD",  { Sv }, 0 },
3469     { "strD",   { Sv }, 0 },
3470     { "lldt",   { Ew }, 0 },
3471     { "ltr",    { Ew }, 0 },
3472     { "verr",   { Ew }, 0 },
3473     { "verw",   { Ew }, 0 },
3474     { Bad_Opcode },
3475     { Bad_Opcode },
3476   },
3477   /* REG_0F01 */
3478   {
3479     { MOD_TABLE (MOD_0F01_REG_0) },
3480     { MOD_TABLE (MOD_0F01_REG_1) },
3481     { MOD_TABLE (MOD_0F01_REG_2) },
3482     { MOD_TABLE (MOD_0F01_REG_3) },
3483     { "smswD",  { Sv }, 0 },
3484     { Bad_Opcode },
3485     { "lmsw",   { Ew }, 0 },
3486     { MOD_TABLE (MOD_0F01_REG_7) },
3487   },
3488   /* REG_0F0D */
3489   {
3490     { "prefetch",       { Mb }, 0 },
3491     { "prefetchw",      { Mb }, 0 },
3492     { "prefetchwt1",    { Mb }, 0 },
3493     { "prefetch",       { Mb }, 0 },
3494     { "prefetch",       { Mb }, 0 },
3495     { "prefetch",       { Mb }, 0 },
3496     { "prefetch",       { Mb }, 0 },
3497     { "prefetch",       { Mb }, 0 },
3498   },
3499   /* REG_0F18 */
3500   {
3501     { MOD_TABLE (MOD_0F18_REG_0) },
3502     { MOD_TABLE (MOD_0F18_REG_1) },
3503     { MOD_TABLE (MOD_0F18_REG_2) },
3504     { MOD_TABLE (MOD_0F18_REG_3) },
3505     { MOD_TABLE (MOD_0F18_REG_4) },
3506     { MOD_TABLE (MOD_0F18_REG_5) },
3507     { MOD_TABLE (MOD_0F18_REG_6) },
3508     { MOD_TABLE (MOD_0F18_REG_7) },
3509   },
3510   /* REG_0F71 */
3511   {
3512     { Bad_Opcode },
3513     { Bad_Opcode },
3514     { MOD_TABLE (MOD_0F71_REG_2) },
3515     { Bad_Opcode },
3516     { MOD_TABLE (MOD_0F71_REG_4) },
3517     { Bad_Opcode },
3518     { MOD_TABLE (MOD_0F71_REG_6) },
3519   },
3520   /* REG_0F72 */
3521   {
3522     { Bad_Opcode },
3523     { Bad_Opcode },
3524     { MOD_TABLE (MOD_0F72_REG_2) },
3525     { Bad_Opcode },
3526     { MOD_TABLE (MOD_0F72_REG_4) },
3527     { Bad_Opcode },
3528     { MOD_TABLE (MOD_0F72_REG_6) },
3529   },
3530   /* REG_0F73 */
3531   {
3532     { Bad_Opcode },
3533     { Bad_Opcode },
3534     { MOD_TABLE (MOD_0F73_REG_2) },
3535     { MOD_TABLE (MOD_0F73_REG_3) },
3536     { Bad_Opcode },
3537     { Bad_Opcode },
3538     { MOD_TABLE (MOD_0F73_REG_6) },
3539     { MOD_TABLE (MOD_0F73_REG_7) },
3540   },
3541   /* REG_0FA6 */
3542   {
3543     { "montmul",        { { OP_0f07, 0 } }, 0 },
3544     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3545     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3546   },
3547   /* REG_0FA7 */
3548   {
3549     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3550     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3551     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3552     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3553     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3554     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3555   },
3556   /* REG_0FAE */
3557   {
3558     { MOD_TABLE (MOD_0FAE_REG_0) },
3559     { MOD_TABLE (MOD_0FAE_REG_1) },
3560     { MOD_TABLE (MOD_0FAE_REG_2) },
3561     { MOD_TABLE (MOD_0FAE_REG_3) },
3562     { MOD_TABLE (MOD_0FAE_REG_4) },
3563     { MOD_TABLE (MOD_0FAE_REG_5) },
3564     { MOD_TABLE (MOD_0FAE_REG_6) },
3565     { MOD_TABLE (MOD_0FAE_REG_7) },
3566   },
3567   /* REG_0FBA */
3568   {
3569     { Bad_Opcode },
3570     { Bad_Opcode },
3571     { Bad_Opcode },
3572     { Bad_Opcode },
3573     { "btQ",    { Ev, Ib }, 0 },
3574     { "btsQ",   { Evh1, Ib }, 0 },
3575     { "btrQ",   { Evh1, Ib }, 0 },
3576     { "btcQ",   { Evh1, Ib }, 0 },
3577   },
3578   /* REG_0FC7 */
3579   {
3580     { Bad_Opcode },
3581     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3582     { Bad_Opcode },
3583     { MOD_TABLE (MOD_0FC7_REG_3) },
3584     { MOD_TABLE (MOD_0FC7_REG_4) },
3585     { MOD_TABLE (MOD_0FC7_REG_5) },
3586     { MOD_TABLE (MOD_0FC7_REG_6) },
3587     { MOD_TABLE (MOD_0FC7_REG_7) },
3588   },
3589   /* REG_VEX_0F71 */
3590   {
3591     { Bad_Opcode },
3592     { Bad_Opcode },
3593     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3594     { Bad_Opcode },
3595     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3596     { Bad_Opcode },
3597     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3598   },
3599   /* REG_VEX_0F72 */
3600   {
3601     { Bad_Opcode },
3602     { Bad_Opcode },
3603     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3604     { Bad_Opcode },
3605     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3606     { Bad_Opcode },
3607     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3608   },
3609   /* REG_VEX_0F73 */
3610   {
3611     { Bad_Opcode },
3612     { Bad_Opcode },
3613     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3614     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3615     { Bad_Opcode },
3616     { Bad_Opcode },
3617     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3618     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3619   },
3620   /* REG_VEX_0FAE */
3621   {
3622     { Bad_Opcode },
3623     { Bad_Opcode },
3624     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3625     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3626   },
3627   /* REG_VEX_0F38F3 */
3628   {
3629     { Bad_Opcode },
3630     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3631     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3632     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3633   },
3634   /* REG_XOP_LWPCB */
3635   {
3636     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3637     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3638   },
3639   /* REG_XOP_LWP */
3640   {
3641     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3642     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3643   },
3644   /* REG_XOP_TBM_01 */
3645   {
3646     { Bad_Opcode },
3647     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3648     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3649     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3650     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3651     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3652     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3653     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3654   },
3655   /* REG_XOP_TBM_02 */
3656   {
3657     { Bad_Opcode },
3658     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3659     { Bad_Opcode },
3660     { Bad_Opcode },
3661     { Bad_Opcode },
3662     { Bad_Opcode },
3663     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3664   },
3665 #define NEED_REG_TABLE
3666 #include "i386-dis-evex.h"
3667 #undef NEED_REG_TABLE
3668 };
3669
3670 static const struct dis386 prefix_table[][4] = {
3671   /* PREFIX_90 */
3672   {
3673     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3674     { "pause", { XX }, 0 },
3675     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3676   },
3677
3678   /* PREFIX_0F10 */
3679   {
3680     { "movups", { XM, EXx }, PREFIX_MANDATORY },
3681     { "movss",  { XM, EXd }, PREFIX_MANDATORY },
3682     { "movupd", { XM, EXx }, PREFIX_MANDATORY },
3683     { "movsd",  { XM, EXq }, PREFIX_MANDATORY },
3684   },
3685
3686   /* PREFIX_0F11 */
3687   {
3688     { "movups", { EXxS, XM }, PREFIX_MANDATORY },
3689     { "movss",  { EXdS, XM }, PREFIX_MANDATORY },
3690     { "movupd", { EXxS, XM }, PREFIX_MANDATORY },
3691     { "movsd",  { EXqS, XM }, PREFIX_MANDATORY },
3692   },
3693
3694   /* PREFIX_0F12 */
3695   {
3696     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3697     { "movsldup", { XM, EXx }, PREFIX_MANDATORY },
3698     { "movlpd", { XM, EXq }, PREFIX_MANDATORY },
3699     { "movddup", { XM, EXq }, PREFIX_MANDATORY },
3700   },
3701
3702   /* PREFIX_0F16 */
3703   {
3704     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3705     { "movshdup", { XM, EXx }, PREFIX_MANDATORY },
3706     { "movhpd", { XM, EXq }, PREFIX_MANDATORY },
3707   },
3708
3709   /* PREFIX_0F1A */
3710   {
3711     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3712     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3713     { "bndmov", { Gbnd, Ebnd }, 0 },
3714     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3715   },
3716
3717   /* PREFIX_0F1B */
3718   {
3719     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3720     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3721     { "bndmov", { Ebnd, Gbnd }, 0 },
3722     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3723   },
3724
3725   /* PREFIX_0F2A */
3726   {
3727     { "cvtpi2ps", { XM, EMCq }, PREFIX_MANDATORY },
3728     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_MANDATORY },
3729     { "cvtpi2pd", { XM, EMCq }, PREFIX_MANDATORY },
3730     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3731   },
3732
3733   /* PREFIX_0F2B */
3734   {
3735     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3736     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3737     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3738     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3739   },
3740
3741   /* PREFIX_0F2C */
3742   {
3743     { "cvttps2pi", { MXC, EXq }, PREFIX_MANDATORY },
3744     { "cvttss2siY", { Gv, EXd }, PREFIX_MANDATORY },
3745     { "cvttpd2pi", { MXC, EXx }, PREFIX_MANDATORY },
3746     { "cvttsd2siY", { Gv, EXq }, PREFIX_MANDATORY },
3747   },
3748
3749   /* PREFIX_0F2D */
3750   {
3751     { "cvtps2pi", { MXC, EXq }, PREFIX_MANDATORY },
3752     { "cvtss2siY", { Gv, EXd }, PREFIX_MANDATORY },
3753     { "cvtpd2pi", { MXC, EXx }, PREFIX_MANDATORY },
3754     { "cvtsd2siY", { Gv, EXq }, PREFIX_MANDATORY },
3755   },
3756
3757   /* PREFIX_0F2E */
3758   {
3759     { "ucomiss",{ XM, EXd }, 0 },
3760     { Bad_Opcode },
3761     { "ucomisd",{ XM, EXq }, 0 },
3762   },
3763
3764   /* PREFIX_0F2F */
3765   {
3766     { "comiss", { XM, EXd }, 0 },
3767     { Bad_Opcode },
3768     { "comisd", { XM, EXq }, 0 },
3769   },
3770
3771   /* PREFIX_0F51 */
3772   {
3773     { "sqrtps", { XM, EXx }, PREFIX_MANDATORY },
3774     { "sqrtss", { XM, EXd }, PREFIX_MANDATORY },
3775     { "sqrtpd", { XM, EXx }, PREFIX_MANDATORY },
3776     { "sqrtsd", { XM, EXq }, PREFIX_MANDATORY },
3777   },
3778
3779   /* PREFIX_0F52 */
3780   {
3781     { "rsqrtps",{ XM, EXx }, PREFIX_MANDATORY },
3782     { "rsqrtss",{ XM, EXd }, PREFIX_MANDATORY },
3783   },
3784
3785   /* PREFIX_0F53 */
3786   {
3787     { "rcpps",  { XM, EXx }, PREFIX_MANDATORY },
3788     { "rcpss",  { XM, EXd }, PREFIX_MANDATORY },
3789   },
3790
3791   /* PREFIX_0F58 */
3792   {
3793     { "addps", { XM, EXx }, PREFIX_MANDATORY },
3794     { "addss", { XM, EXd }, PREFIX_MANDATORY },
3795     { "addpd", { XM, EXx }, PREFIX_MANDATORY },
3796     { "addsd", { XM, EXq }, PREFIX_MANDATORY },
3797   },
3798
3799   /* PREFIX_0F59 */
3800   {
3801     { "mulps",  { XM, EXx }, PREFIX_MANDATORY },
3802     { "mulss",  { XM, EXd }, PREFIX_MANDATORY },
3803     { "mulpd",  { XM, EXx }, PREFIX_MANDATORY },
3804     { "mulsd",  { XM, EXq }, PREFIX_MANDATORY },
3805   },
3806
3807   /* PREFIX_0F5A */
3808   {
3809     { "cvtps2pd", { XM, EXq }, PREFIX_MANDATORY },
3810     { "cvtss2sd", { XM, EXd }, PREFIX_MANDATORY },
3811     { "cvtpd2ps", { XM, EXx }, PREFIX_MANDATORY },
3812     { "cvtsd2ss", { XM, EXq }, PREFIX_MANDATORY },
3813   },
3814
3815   /* PREFIX_0F5B */
3816   {
3817     { "cvtdq2ps", { XM, EXx }, PREFIX_MANDATORY },
3818     { "cvttps2dq", { XM, EXx }, PREFIX_MANDATORY },
3819     { "cvtps2dq", { XM, EXx }, PREFIX_MANDATORY },
3820   },
3821
3822   /* PREFIX_0F5C */
3823   {
3824     { "subps",  { XM, EXx }, PREFIX_MANDATORY },
3825     { "subss",  { XM, EXd }, PREFIX_MANDATORY },
3826     { "subpd",  { XM, EXx }, PREFIX_MANDATORY },
3827     { "subsd",  { XM, EXq }, PREFIX_MANDATORY },
3828   },
3829
3830   /* PREFIX_0F5D */
3831   {
3832     { "minps",  { XM, EXx }, PREFIX_MANDATORY },
3833     { "minss",  { XM, EXd }, PREFIX_MANDATORY },
3834     { "minpd",  { XM, EXx }, PREFIX_MANDATORY },
3835     { "minsd",  { XM, EXq }, PREFIX_MANDATORY },
3836   },
3837
3838   /* PREFIX_0F5E */
3839   {
3840     { "divps",  { XM, EXx }, PREFIX_MANDATORY },
3841     { "divss",  { XM, EXd }, PREFIX_MANDATORY },
3842     { "divpd",  { XM, EXx }, PREFIX_MANDATORY },
3843     { "divsd",  { XM, EXq }, PREFIX_MANDATORY },
3844   },
3845
3846   /* PREFIX_0F5F */
3847   {
3848     { "maxps",  { XM, EXx }, PREFIX_MANDATORY },
3849     { "maxss",  { XM, EXd }, PREFIX_MANDATORY },
3850     { "maxpd",  { XM, EXx }, PREFIX_MANDATORY },
3851     { "maxsd",  { XM, EXq }, PREFIX_MANDATORY },
3852   },
3853
3854   /* PREFIX_0F60 */
3855   {
3856     { "punpcklbw",{ MX, EMd }, PREFIX_MANDATORY },
3857     { Bad_Opcode },
3858     { "punpcklbw",{ MX, EMx }, PREFIX_MANDATORY },
3859   },
3860
3861   /* PREFIX_0F61 */
3862   {
3863     { "punpcklwd",{ MX, EMd }, PREFIX_MANDATORY },
3864     { Bad_Opcode },
3865     { "punpcklwd",{ MX, EMx }, PREFIX_MANDATORY },
3866   },
3867
3868   /* PREFIX_0F62 */
3869   {
3870     { "punpckldq",{ MX, EMd }, PREFIX_MANDATORY },
3871     { Bad_Opcode },
3872     { "punpckldq",{ MX, EMx }, PREFIX_MANDATORY },
3873   },
3874
3875   /* PREFIX_0F6C */
3876   {
3877     { Bad_Opcode },
3878     { Bad_Opcode },
3879     { "punpcklqdq", { XM, EXx }, PREFIX_MANDATORY },
3880   },
3881
3882   /* PREFIX_0F6D */
3883   {
3884     { Bad_Opcode },
3885     { Bad_Opcode },
3886     { "punpckhqdq", { XM, EXx }, PREFIX_MANDATORY },
3887   },
3888
3889   /* PREFIX_0F6F */
3890   {
3891     { "movq",   { MX, EM }, PREFIX_MANDATORY },
3892     { "movdqu", { XM, EXx }, PREFIX_MANDATORY },
3893     { "movdqa", { XM, EXx }, PREFIX_MANDATORY },
3894   },
3895
3896   /* PREFIX_0F70 */
3897   {
3898     { "pshufw", { MX, EM, Ib }, PREFIX_MANDATORY },
3899     { "pshufhw",{ XM, EXx, Ib }, PREFIX_MANDATORY },
3900     { "pshufd", { XM, EXx, Ib }, PREFIX_MANDATORY },
3901     { "pshuflw",{ XM, EXx, Ib }, PREFIX_MANDATORY },
3902   },
3903
3904   /* PREFIX_0F73_REG_3 */
3905   {
3906     { Bad_Opcode },
3907     { Bad_Opcode },
3908     { "psrldq", { XS, Ib }, 0 },
3909   },
3910
3911   /* PREFIX_0F73_REG_7 */
3912   {
3913     { Bad_Opcode },
3914     { Bad_Opcode },
3915     { "pslldq", { XS, Ib }, 0 },
3916   },
3917
3918   /* PREFIX_0F78 */
3919   {
3920     {"vmread",  { Em, Gm }, 0 },
3921     { Bad_Opcode },
3922     {"extrq",   { XS, Ib, Ib }, 0 },
3923     {"insertq", { XM, XS, Ib, Ib }, 0 },
3924   },
3925
3926   /* PREFIX_0F79 */
3927   {
3928     {"vmwrite", { Gm, Em }, 0 },
3929     { Bad_Opcode },
3930     {"extrq",   { XM, XS }, 0 },
3931     {"insertq", { XM, XS }, 0 },
3932   },
3933
3934   /* PREFIX_0F7C */
3935   {
3936     { Bad_Opcode },
3937     { Bad_Opcode },
3938     { "haddpd", { XM, EXx }, PREFIX_MANDATORY },
3939     { "haddps", { XM, EXx }, PREFIX_MANDATORY },
3940   },
3941
3942   /* PREFIX_0F7D */
3943   {
3944     { Bad_Opcode },
3945     { Bad_Opcode },
3946     { "hsubpd", { XM, EXx }, PREFIX_MANDATORY },
3947     { "hsubps", { XM, EXx }, PREFIX_MANDATORY },
3948   },
3949
3950   /* PREFIX_0F7E */
3951   {
3952     { "movK",   { Edq, MX }, PREFIX_MANDATORY },
3953     { "movq",   { XM, EXq }, PREFIX_MANDATORY },
3954     { "movK",   { Edq, XM }, PREFIX_MANDATORY },
3955   },
3956
3957   /* PREFIX_0F7F */
3958   {
3959     { "movq",   { EMS, MX }, PREFIX_MANDATORY },
3960     { "movdqu", { EXxS, XM }, PREFIX_MANDATORY },
3961     { "movdqa", { EXxS, XM }, PREFIX_MANDATORY },
3962   },
3963
3964   /* PREFIX_0FAE_REG_0 */
3965   {
3966     { Bad_Opcode },
3967     { "rdfsbase", { Ev }, 0 },
3968   },
3969
3970   /* PREFIX_0FAE_REG_1 */
3971   {
3972     { Bad_Opcode },
3973     { "rdgsbase", { Ev }, 0 },
3974   },
3975
3976   /* PREFIX_0FAE_REG_2 */
3977   {
3978     { Bad_Opcode },
3979     { "wrfsbase", { Ev }, 0 },
3980   },
3981
3982   /* PREFIX_0FAE_REG_3 */
3983   {
3984     { Bad_Opcode },
3985     { "wrgsbase", { Ev }, 0 },
3986   },
3987
3988   /* PREFIX_0FAE_REG_6 */
3989   {
3990     { "xsaveopt",      { FXSAVE }, 0 },
3991     { Bad_Opcode },
3992     { "clwb",   { Mb }, 0 },
3993   },
3994
3995   /* PREFIX_0FAE_REG_7 */
3996   {
3997     { "clflush",        { Mb }, 0 },
3998     { Bad_Opcode },
3999     { "clflushopt",     { Mb }, 0 },
4000   },
4001
4002   /* PREFIX_RM_0_0FAE_REG_7 */
4003   {
4004     { "sfence",         { Skip_MODRM }, 0 },
4005     { Bad_Opcode },
4006     { "pcommit",                { Skip_MODRM }, 0 },
4007   },
4008
4009   /* PREFIX_0FB8 */
4010   {
4011     { Bad_Opcode },
4012     { "popcntS", { Gv, Ev }, 0 },
4013   },
4014
4015   /* PREFIX_0FBC */
4016   {
4017     { "bsfS",   { Gv, Ev }, 0 },
4018     { "tzcntS", { Gv, Ev }, 0 },
4019     { "bsfS",   { Gv, Ev }, 0 },
4020   },
4021
4022   /* PREFIX_0FBD */
4023   {
4024     { "bsrS",   { Gv, Ev }, 0 },
4025     { "lzcntS", { Gv, Ev }, 0 },
4026     { "bsrS",   { Gv, Ev }, 0 },
4027   },
4028
4029   /* PREFIX_0FC2 */
4030   {
4031     { "cmpps",  { XM, EXx, CMP }, PREFIX_MANDATORY },
4032     { "cmpss",  { XM, EXd, CMP }, PREFIX_MANDATORY },
4033     { "cmppd",  { XM, EXx, CMP }, PREFIX_MANDATORY },
4034     { "cmpsd",  { XM, EXq, CMP }, PREFIX_MANDATORY },
4035   },
4036
4037   /* PREFIX_0FC3 */
4038   {
4039     { "movntiS", { Ma, Gv }, PREFIX_MANDATORY },
4040   },
4041
4042   /* PREFIX_0FC7_REG_6 */
4043   {
4044     { "vmptrld",{ Mq }, 0 },
4045     { "vmxon",  { Mq }, 0 },
4046     { "vmclear",{ Mq }, 0 },
4047   },
4048
4049   /* PREFIX_0FD0 */
4050   {
4051     { Bad_Opcode },
4052     { Bad_Opcode },
4053     { "addsubpd", { XM, EXx }, 0 },
4054     { "addsubps", { XM, EXx }, 0 },
4055   },
4056
4057   /* PREFIX_0FD6 */
4058   {
4059     { Bad_Opcode },
4060     { "movq2dq",{ XM, MS }, 0 },
4061     { "movq",   { EXqS, XM }, 0 },
4062     { "movdq2q",{ MX, XS }, 0 },
4063   },
4064
4065   /* PREFIX_0FE6 */
4066   {
4067     { Bad_Opcode },
4068     { "cvtdq2pd", { XM, EXq }, PREFIX_MANDATORY },
4069     { "cvttpd2dq", { XM, EXx }, PREFIX_MANDATORY },
4070     { "cvtpd2dq", { XM, EXx }, PREFIX_MANDATORY },
4071   },
4072
4073   /* PREFIX_0FE7 */
4074   {
4075     { "movntq", { Mq, MX }, PREFIX_MANDATORY },
4076     { Bad_Opcode },
4077     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4078   },
4079
4080   /* PREFIX_0FF0 */
4081   {
4082     { Bad_Opcode },
4083     { Bad_Opcode },
4084     { Bad_Opcode },
4085     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4086   },
4087
4088   /* PREFIX_0FF7 */
4089   {
4090     { "maskmovq", { MX, MS }, PREFIX_MANDATORY },
4091     { Bad_Opcode },
4092     { "maskmovdqu", { XM, XS }, PREFIX_MANDATORY },
4093   },
4094
4095   /* PREFIX_0F3810 */
4096   {
4097     { Bad_Opcode },
4098     { Bad_Opcode },
4099     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_MANDATORY },
4100   },
4101
4102   /* PREFIX_0F3814 */
4103   {
4104     { Bad_Opcode },
4105     { Bad_Opcode },
4106     { "blendvps", { XM, EXx, XMM0 }, PREFIX_MANDATORY },
4107   },
4108
4109   /* PREFIX_0F3815 */
4110   {
4111     { Bad_Opcode },
4112     { Bad_Opcode },
4113     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_MANDATORY },
4114   },
4115
4116   /* PREFIX_0F3817 */
4117   {
4118     { Bad_Opcode },
4119     { Bad_Opcode },
4120     { "ptest",  { XM, EXx }, PREFIX_MANDATORY },
4121   },
4122
4123   /* PREFIX_0F3820 */
4124   {
4125     { Bad_Opcode },
4126     { Bad_Opcode },
4127     { "pmovsxbw", { XM, EXq }, PREFIX_MANDATORY },
4128   },
4129
4130   /* PREFIX_0F3821 */
4131   {
4132     { Bad_Opcode },
4133     { Bad_Opcode },
4134     { "pmovsxbd", { XM, EXd }, PREFIX_MANDATORY },
4135   },
4136
4137   /* PREFIX_0F3822 */
4138   {
4139     { Bad_Opcode },
4140     { Bad_Opcode },
4141     { "pmovsxbq", { XM, EXw }, PREFIX_MANDATORY },
4142   },
4143
4144   /* PREFIX_0F3823 */
4145   {
4146     { Bad_Opcode },
4147     { Bad_Opcode },
4148     { "pmovsxwd", { XM, EXq }, PREFIX_MANDATORY },
4149   },
4150
4151   /* PREFIX_0F3824 */
4152   {
4153     { Bad_Opcode },
4154     { Bad_Opcode },
4155     { "pmovsxwq", { XM, EXd }, PREFIX_MANDATORY },
4156   },
4157
4158   /* PREFIX_0F3825 */
4159   {
4160     { Bad_Opcode },
4161     { Bad_Opcode },
4162     { "pmovsxdq", { XM, EXq }, PREFIX_MANDATORY },
4163   },
4164
4165   /* PREFIX_0F3828 */
4166   {
4167     { Bad_Opcode },
4168     { Bad_Opcode },
4169     { "pmuldq", { XM, EXx }, PREFIX_MANDATORY },
4170   },
4171
4172   /* PREFIX_0F3829 */
4173   {
4174     { Bad_Opcode },
4175     { Bad_Opcode },
4176     { "pcmpeqq", { XM, EXx }, PREFIX_MANDATORY },
4177   },
4178
4179   /* PREFIX_0F382A */
4180   {
4181     { Bad_Opcode },
4182     { Bad_Opcode },
4183     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4184   },
4185
4186   /* PREFIX_0F382B */
4187   {
4188     { Bad_Opcode },
4189     { Bad_Opcode },
4190     { "packusdw", { XM, EXx }, PREFIX_MANDATORY },
4191   },
4192
4193   /* PREFIX_0F3830 */
4194   {
4195     { Bad_Opcode },
4196     { Bad_Opcode },
4197     { "pmovzxbw", { XM, EXq }, PREFIX_MANDATORY },
4198   },
4199
4200   /* PREFIX_0F3831 */
4201   {
4202     { Bad_Opcode },
4203     { Bad_Opcode },
4204     { "pmovzxbd", { XM, EXd }, PREFIX_MANDATORY },
4205   },
4206
4207   /* PREFIX_0F3832 */
4208   {
4209     { Bad_Opcode },
4210     { Bad_Opcode },
4211     { "pmovzxbq", { XM, EXw }, PREFIX_MANDATORY },
4212   },
4213
4214   /* PREFIX_0F3833 */
4215   {
4216     { Bad_Opcode },
4217     { Bad_Opcode },
4218     { "pmovzxwd", { XM, EXq }, PREFIX_MANDATORY },
4219   },
4220
4221   /* PREFIX_0F3834 */
4222   {
4223     { Bad_Opcode },
4224     { Bad_Opcode },
4225     { "pmovzxwq", { XM, EXd }, PREFIX_MANDATORY },
4226   },
4227
4228   /* PREFIX_0F3835 */
4229   {
4230     { Bad_Opcode },
4231     { Bad_Opcode },
4232     { "pmovzxdq", { XM, EXq }, PREFIX_MANDATORY },
4233   },
4234
4235   /* PREFIX_0F3837 */
4236   {
4237     { Bad_Opcode },
4238     { Bad_Opcode },
4239     { "pcmpgtq", { XM, EXx }, PREFIX_MANDATORY },
4240   },
4241
4242   /* PREFIX_0F3838 */
4243   {
4244     { Bad_Opcode },
4245     { Bad_Opcode },
4246     { "pminsb", { XM, EXx }, PREFIX_MANDATORY },
4247   },
4248
4249   /* PREFIX_0F3839 */
4250   {
4251     { Bad_Opcode },
4252     { Bad_Opcode },
4253     { "pminsd", { XM, EXx }, PREFIX_MANDATORY },
4254   },
4255
4256   /* PREFIX_0F383A */
4257   {
4258     { Bad_Opcode },
4259     { Bad_Opcode },
4260     { "pminuw", { XM, EXx }, PREFIX_MANDATORY },
4261   },
4262
4263   /* PREFIX_0F383B */
4264   {
4265     { Bad_Opcode },
4266     { Bad_Opcode },
4267     { "pminud", { XM, EXx }, PREFIX_MANDATORY },
4268   },
4269
4270   /* PREFIX_0F383C */
4271   {
4272     { Bad_Opcode },
4273     { Bad_Opcode },
4274     { "pmaxsb", { XM, EXx }, PREFIX_MANDATORY },
4275   },
4276
4277   /* PREFIX_0F383D */
4278   {
4279     { Bad_Opcode },
4280     { Bad_Opcode },
4281     { "pmaxsd", { XM, EXx }, PREFIX_MANDATORY },
4282   },
4283
4284   /* PREFIX_0F383E */
4285   {
4286     { Bad_Opcode },
4287     { Bad_Opcode },
4288     { "pmaxuw", { XM, EXx }, PREFIX_MANDATORY },
4289   },
4290
4291   /* PREFIX_0F383F */
4292   {
4293     { Bad_Opcode },
4294     { Bad_Opcode },
4295     { "pmaxud", { XM, EXx }, PREFIX_MANDATORY },
4296   },
4297
4298   /* PREFIX_0F3840 */
4299   {
4300     { Bad_Opcode },
4301     { Bad_Opcode },
4302     { "pmulld", { XM, EXx }, PREFIX_MANDATORY },
4303   },
4304
4305   /* PREFIX_0F3841 */
4306   {
4307     { Bad_Opcode },
4308     { Bad_Opcode },
4309     { "phminposuw", { XM, EXx }, PREFIX_MANDATORY },
4310   },
4311
4312   /* PREFIX_0F3880 */
4313   {
4314     { Bad_Opcode },
4315     { Bad_Opcode },
4316     { "invept", { Gm, Mo }, PREFIX_MANDATORY },
4317   },
4318
4319   /* PREFIX_0F3881 */
4320   {
4321     { Bad_Opcode },
4322     { Bad_Opcode },
4323     { "invvpid", { Gm, Mo }, PREFIX_MANDATORY },
4324   },
4325
4326   /* PREFIX_0F3882 */
4327   {
4328     { Bad_Opcode },
4329     { Bad_Opcode },
4330     { "invpcid", { Gm, M }, PREFIX_MANDATORY },
4331   },
4332
4333   /* PREFIX_0F38C8 */
4334   {
4335     { "sha1nexte", { XM, EXxmm }, PREFIX_MANDATORY },
4336   },
4337
4338   /* PREFIX_0F38C9 */
4339   {
4340     { "sha1msg1", { XM, EXxmm }, PREFIX_MANDATORY },
4341   },
4342
4343   /* PREFIX_0F38CA */
4344   {
4345     { "sha1msg2", { XM, EXxmm }, PREFIX_MANDATORY },
4346   },
4347
4348   /* PREFIX_0F38CB */
4349   {
4350     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_MANDATORY },
4351   },
4352
4353   /* PREFIX_0F38CC */
4354   {
4355     { "sha256msg1", { XM, EXxmm }, PREFIX_MANDATORY },
4356   },
4357
4358   /* PREFIX_0F38CD */
4359   {
4360     { "sha256msg2", { XM, EXxmm }, PREFIX_MANDATORY },
4361   },
4362
4363   /* PREFIX_0F38DB */
4364   {
4365     { Bad_Opcode },
4366     { Bad_Opcode },
4367     { "aesimc", { XM, EXx }, PREFIX_MANDATORY },
4368   },
4369
4370   /* PREFIX_0F38DC */
4371   {
4372     { Bad_Opcode },
4373     { Bad_Opcode },
4374     { "aesenc", { XM, EXx }, PREFIX_MANDATORY },
4375   },
4376
4377   /* PREFIX_0F38DD */
4378   {
4379     { Bad_Opcode },
4380     { Bad_Opcode },
4381     { "aesenclast", { XM, EXx }, PREFIX_MANDATORY },
4382   },
4383
4384   /* PREFIX_0F38DE */
4385   {
4386     { Bad_Opcode },
4387     { Bad_Opcode },
4388     { "aesdec", { XM, EXx }, PREFIX_MANDATORY },
4389   },
4390
4391   /* PREFIX_0F38DF */
4392   {
4393     { Bad_Opcode },
4394     { Bad_Opcode },
4395     { "aesdeclast", { XM, EXx }, PREFIX_MANDATORY },
4396   },
4397
4398   /* PREFIX_0F38F0 */
4399   {
4400     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_MANDATORY },
4401     { Bad_Opcode },
4402     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_MANDATORY },
4403     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_MANDATORY },
4404   },
4405
4406   /* PREFIX_0F38F1 */
4407   {
4408     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_MANDATORY },
4409     { Bad_Opcode },
4410     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_MANDATORY },
4411     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_MANDATORY },
4412   },
4413
4414   /* PREFIX_0F38F6 */
4415   {
4416     { Bad_Opcode },
4417     { "adoxS",  { Gdq, Edq}, PREFIX_MANDATORY },
4418     { "adcxS",  { Gdq, Edq}, PREFIX_MANDATORY },
4419     { Bad_Opcode },
4420   },
4421
4422   /* PREFIX_0F3A08 */
4423   {
4424     { Bad_Opcode },
4425     { Bad_Opcode },
4426     { "roundps", { XM, EXx, Ib }, PREFIX_MANDATORY },
4427   },
4428
4429   /* PREFIX_0F3A09 */
4430   {
4431     { Bad_Opcode },
4432     { Bad_Opcode },
4433     { "roundpd", { XM, EXx, Ib }, PREFIX_MANDATORY },
4434   },
4435
4436   /* PREFIX_0F3A0A */
4437   {
4438     { Bad_Opcode },
4439     { Bad_Opcode },
4440     { "roundss", { XM, EXd, Ib }, PREFIX_MANDATORY },
4441   },
4442
4443   /* PREFIX_0F3A0B */
4444   {
4445     { Bad_Opcode },
4446     { Bad_Opcode },
4447     { "roundsd", { XM, EXq, Ib }, PREFIX_MANDATORY },
4448   },
4449
4450   /* PREFIX_0F3A0C */
4451   {
4452     { Bad_Opcode },
4453     { Bad_Opcode },
4454     { "blendps", { XM, EXx, Ib }, PREFIX_MANDATORY },
4455   },
4456
4457   /* PREFIX_0F3A0D */
4458   {
4459     { Bad_Opcode },
4460     { Bad_Opcode },
4461     { "blendpd", { XM, EXx, Ib }, PREFIX_MANDATORY },
4462   },
4463
4464   /* PREFIX_0F3A0E */
4465   {
4466     { Bad_Opcode },
4467     { Bad_Opcode },
4468     { "pblendw", { XM, EXx, Ib }, PREFIX_MANDATORY },
4469   },
4470
4471   /* PREFIX_0F3A14 */
4472   {
4473     { Bad_Opcode },
4474     { Bad_Opcode },
4475     { "pextrb", { Edqb, XM, Ib }, PREFIX_MANDATORY },
4476   },
4477
4478   /* PREFIX_0F3A15 */
4479   {
4480     { Bad_Opcode },
4481     { Bad_Opcode },
4482     { "pextrw", { Edqw, XM, Ib }, PREFIX_MANDATORY },
4483   },
4484
4485   /* PREFIX_0F3A16 */
4486   {
4487     { Bad_Opcode },
4488     { Bad_Opcode },
4489     { "pextrK", { Edq, XM, Ib }, PREFIX_MANDATORY },
4490   },
4491
4492   /* PREFIX_0F3A17 */
4493   {
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     { "extractps", { Edqd, XM, Ib }, PREFIX_MANDATORY },
4497   },
4498
4499   /* PREFIX_0F3A20 */
4500   {
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     { "pinsrb", { XM, Edqb, Ib }, PREFIX_MANDATORY },
4504   },
4505
4506   /* PREFIX_0F3A21 */
4507   {
4508     { Bad_Opcode },
4509     { Bad_Opcode },
4510     { "insertps", { XM, EXd, Ib }, PREFIX_MANDATORY },
4511   },
4512
4513   /* PREFIX_0F3A22 */
4514   {
4515     { Bad_Opcode },
4516     { Bad_Opcode },
4517     { "pinsrK", { XM, Edq, Ib }, PREFIX_MANDATORY },
4518   },
4519
4520   /* PREFIX_0F3A40 */
4521   {
4522     { Bad_Opcode },
4523     { Bad_Opcode },
4524     { "dpps",   { XM, EXx, Ib }, PREFIX_MANDATORY },
4525   },
4526
4527   /* PREFIX_0F3A41 */
4528   {
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531     { "dppd",   { XM, EXx, Ib }, PREFIX_MANDATORY },
4532   },
4533
4534   /* PREFIX_0F3A42 */
4535   {
4536     { Bad_Opcode },
4537     { Bad_Opcode },
4538     { "mpsadbw", { XM, EXx, Ib }, PREFIX_MANDATORY },
4539   },
4540
4541   /* PREFIX_0F3A44 */
4542   {
4543     { Bad_Opcode },
4544     { Bad_Opcode },
4545     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_MANDATORY },
4546   },
4547
4548   /* PREFIX_0F3A60 */
4549   {
4550     { Bad_Opcode },
4551     { Bad_Opcode },
4552     { "pcmpestrm", { XM, EXx, Ib }, PREFIX_MANDATORY },
4553   },
4554
4555   /* PREFIX_0F3A61 */
4556   {
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559     { "pcmpestri", { XM, EXx, Ib }, PREFIX_MANDATORY },
4560   },
4561
4562   /* PREFIX_0F3A62 */
4563   {
4564     { Bad_Opcode },
4565     { Bad_Opcode },
4566     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_MANDATORY },
4567   },
4568
4569   /* PREFIX_0F3A63 */
4570   {
4571     { Bad_Opcode },
4572     { Bad_Opcode },
4573     { "pcmpistri", { XM, EXx, Ib }, PREFIX_MANDATORY },
4574   },
4575
4576   /* PREFIX_0F3ACC */
4577   {
4578     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_MANDATORY },
4579   },
4580
4581   /* PREFIX_0F3ADF */
4582   {
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_MANDATORY },
4586   },
4587
4588   /* PREFIX_VEX_0F10 */
4589   {
4590     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4591     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4592     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4593     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4594   },
4595
4596   /* PREFIX_VEX_0F11 */
4597   {
4598     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4599     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4600     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4601     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4602   },
4603
4604   /* PREFIX_VEX_0F12 */
4605   {
4606     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4607     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4608     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4609     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4610   },
4611
4612   /* PREFIX_VEX_0F16 */
4613   {
4614     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4615     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4616     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4617   },
4618
4619   /* PREFIX_VEX_0F2A */
4620   {
4621     { Bad_Opcode },
4622     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4623     { Bad_Opcode },
4624     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4625   },
4626
4627   /* PREFIX_VEX_0F2C */
4628   {
4629     { Bad_Opcode },
4630     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4631     { Bad_Opcode },
4632     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4633   },
4634
4635   /* PREFIX_VEX_0F2D */
4636   {
4637     { Bad_Opcode },
4638     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4639     { Bad_Opcode },
4640     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4641   },
4642
4643   /* PREFIX_VEX_0F2E */
4644   {
4645     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4646     { Bad_Opcode },
4647     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4648   },
4649
4650   /* PREFIX_VEX_0F2F */
4651   {
4652     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4653     { Bad_Opcode },
4654     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4655   },
4656
4657   /* PREFIX_VEX_0F41 */
4658   {
4659     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4660     { Bad_Opcode },
4661     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4662   },
4663
4664   /* PREFIX_VEX_0F42 */
4665   {
4666     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4667     { Bad_Opcode },
4668     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4669   },
4670
4671   /* PREFIX_VEX_0F44 */
4672   {
4673     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4674     { Bad_Opcode },
4675     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4676   },
4677
4678   /* PREFIX_VEX_0F45 */
4679   {
4680     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4681     { Bad_Opcode },
4682     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4683   },
4684
4685   /* PREFIX_VEX_0F46 */
4686   {
4687     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4688     { Bad_Opcode },
4689     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4690   },
4691
4692   /* PREFIX_VEX_0F47 */
4693   {
4694     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4695     { Bad_Opcode },
4696     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4697   },
4698
4699   /* PREFIX_VEX_0F4A */
4700   {
4701     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4702     { Bad_Opcode },
4703     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4704   },
4705
4706   /* PREFIX_VEX_0F4B */
4707   {
4708     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4709     { Bad_Opcode },
4710     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4711   },
4712
4713   /* PREFIX_VEX_0F51 */
4714   {
4715     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4716     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4717     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4718     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4719   },
4720
4721   /* PREFIX_VEX_0F52 */
4722   {
4723     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4724     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4725   },
4726
4727   /* PREFIX_VEX_0F53 */
4728   {
4729     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4730     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4731   },
4732
4733   /* PREFIX_VEX_0F58 */
4734   {
4735     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4736     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4737     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4738     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4739   },
4740
4741   /* PREFIX_VEX_0F59 */
4742   {
4743     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4744     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4745     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4746     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4747   },
4748
4749   /* PREFIX_VEX_0F5A */
4750   {
4751     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4752     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4753     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4754     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4755   },
4756
4757   /* PREFIX_VEX_0F5B */
4758   {
4759     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4760     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4761     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4762   },
4763
4764   /* PREFIX_VEX_0F5C */
4765   {
4766     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4767     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4768     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4769     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4770   },
4771
4772   /* PREFIX_VEX_0F5D */
4773   {
4774     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4775     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4776     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4777     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4778   },
4779
4780   /* PREFIX_VEX_0F5E */
4781   {
4782     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4783     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4784     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4785     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4786   },
4787
4788   /* PREFIX_VEX_0F5F */
4789   {
4790     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4791     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4792     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4793     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4794   },
4795
4796   /* PREFIX_VEX_0F60 */
4797   {
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4801   },
4802
4803   /* PREFIX_VEX_0F61 */
4804   {
4805     { Bad_Opcode },
4806     { Bad_Opcode },
4807     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4808   },
4809
4810   /* PREFIX_VEX_0F62 */
4811   {
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4815   },
4816
4817   /* PREFIX_VEX_0F63 */
4818   {
4819     { Bad_Opcode },
4820     { Bad_Opcode },
4821     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4822   },
4823
4824   /* PREFIX_VEX_0F64 */
4825   {
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4829   },
4830
4831   /* PREFIX_VEX_0F65 */
4832   {
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4836   },
4837
4838   /* PREFIX_VEX_0F66 */
4839   {
4840     { Bad_Opcode },
4841     { Bad_Opcode },
4842     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4843   },
4844
4845   /* PREFIX_VEX_0F67 */
4846   {
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4850   },
4851
4852   /* PREFIX_VEX_0F68 */
4853   {
4854     { Bad_Opcode },
4855     { Bad_Opcode },
4856     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4857   },
4858
4859   /* PREFIX_VEX_0F69 */
4860   {
4861     { Bad_Opcode },
4862     { Bad_Opcode },
4863     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4864   },
4865
4866   /* PREFIX_VEX_0F6A */
4867   {
4868     { Bad_Opcode },
4869     { Bad_Opcode },
4870     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4871   },
4872
4873   /* PREFIX_VEX_0F6B */
4874   {
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4878   },
4879
4880   /* PREFIX_VEX_0F6C */
4881   {
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4885   },
4886
4887   /* PREFIX_VEX_0F6D */
4888   {
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4892   },
4893
4894   /* PREFIX_VEX_0F6E */
4895   {
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4899   },
4900
4901   /* PREFIX_VEX_0F6F */
4902   {
4903     { Bad_Opcode },
4904     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4905     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4906   },
4907
4908   /* PREFIX_VEX_0F70 */
4909   {
4910     { Bad_Opcode },
4911     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4912     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4913     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4914   },
4915
4916   /* PREFIX_VEX_0F71_REG_2 */
4917   {
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4921   },
4922
4923   /* PREFIX_VEX_0F71_REG_4 */
4924   {
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4928   },
4929
4930   /* PREFIX_VEX_0F71_REG_6 */
4931   {
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4935   },
4936
4937   /* PREFIX_VEX_0F72_REG_2 */
4938   {
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4942   },
4943
4944   /* PREFIX_VEX_0F72_REG_4 */
4945   {
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4949   },
4950
4951   /* PREFIX_VEX_0F72_REG_6 */
4952   {
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4956   },
4957
4958   /* PREFIX_VEX_0F73_REG_2 */
4959   {
4960     { Bad_Opcode },
4961     { Bad_Opcode },
4962     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4963   },
4964
4965   /* PREFIX_VEX_0F73_REG_3 */
4966   {
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4970   },
4971
4972   /* PREFIX_VEX_0F73_REG_6 */
4973   {
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4977   },
4978
4979   /* PREFIX_VEX_0F73_REG_7 */
4980   {
4981     { Bad_Opcode },
4982     { Bad_Opcode },
4983     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4984   },
4985
4986   /* PREFIX_VEX_0F74 */
4987   {
4988     { Bad_Opcode },
4989     { Bad_Opcode },
4990     { VEX_W_TABLE (VEX_W_0F74_P_2) },
4991   },
4992
4993   /* PREFIX_VEX_0F75 */
4994   {
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { VEX_W_TABLE (VEX_W_0F75_P_2) },
4998   },
4999
5000   /* PREFIX_VEX_0F76 */
5001   {
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5005   },
5006
5007   /* PREFIX_VEX_0F77 */
5008   {
5009     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5010   },
5011
5012   /* PREFIX_VEX_0F7C */
5013   {
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5017     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5018   },
5019
5020   /* PREFIX_VEX_0F7D */
5021   {
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5025     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5026   },
5027
5028   /* PREFIX_VEX_0F7E */
5029   {
5030     { Bad_Opcode },
5031     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5032     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5033   },
5034
5035   /* PREFIX_VEX_0F7F */
5036   {
5037     { Bad_Opcode },
5038     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5039     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5040   },
5041
5042   /* PREFIX_VEX_0F90 */
5043   {
5044     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5045     { Bad_Opcode },
5046     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5047   },
5048
5049   /* PREFIX_VEX_0F91 */
5050   {
5051     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5052     { Bad_Opcode },
5053     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5054   },
5055
5056   /* PREFIX_VEX_0F92 */
5057   {
5058     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5059     { Bad_Opcode },
5060     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5061     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5062   },
5063
5064   /* PREFIX_VEX_0F93 */
5065   {
5066     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5067     { Bad_Opcode },
5068     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5069     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5070   },
5071
5072   /* PREFIX_VEX_0F98 */
5073   {
5074     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5075     { Bad_Opcode },
5076     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5077   },
5078
5079   /* PREFIX_VEX_0F99 */
5080   {
5081     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5082     { Bad_Opcode },
5083     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5084   },
5085
5086   /* PREFIX_VEX_0FC2 */
5087   {
5088     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5089     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5090     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5091     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5092   },
5093
5094   /* PREFIX_VEX_0FC4 */
5095   {
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5099   },
5100
5101   /* PREFIX_VEX_0FC5 */
5102   {
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5106   },
5107
5108   /* PREFIX_VEX_0FD0 */
5109   {
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5113     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5114   },
5115
5116   /* PREFIX_VEX_0FD1 */
5117   {
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5121   },
5122
5123   /* PREFIX_VEX_0FD2 */
5124   {
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5128   },
5129
5130   /* PREFIX_VEX_0FD3 */
5131   {
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5135   },
5136
5137   /* PREFIX_VEX_0FD4 */
5138   {
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5142   },
5143
5144   /* PREFIX_VEX_0FD5 */
5145   {
5146     { Bad_Opcode },
5147     { Bad_Opcode },
5148     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5149   },
5150
5151   /* PREFIX_VEX_0FD6 */
5152   {
5153     { Bad_Opcode },
5154     { Bad_Opcode },
5155     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5156   },
5157
5158   /* PREFIX_VEX_0FD7 */
5159   {
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5163   },
5164
5165   /* PREFIX_VEX_0FD8 */
5166   {
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5170   },
5171
5172   /* PREFIX_VEX_0FD9 */
5173   {
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5177   },
5178
5179   /* PREFIX_VEX_0FDA */
5180   {
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5184   },
5185
5186   /* PREFIX_VEX_0FDB */
5187   {
5188     { Bad_Opcode },
5189     { Bad_Opcode },
5190     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5191   },
5192
5193   /* PREFIX_VEX_0FDC */
5194   {
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5198   },
5199
5200   /* PREFIX_VEX_0FDD */
5201   {
5202     { Bad_Opcode },
5203     { Bad_Opcode },
5204     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5205   },
5206
5207   /* PREFIX_VEX_0FDE */
5208   {
5209     { Bad_Opcode },
5210     { Bad_Opcode },
5211     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5212   },
5213
5214   /* PREFIX_VEX_0FDF */
5215   {
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5219   },
5220
5221   /* PREFIX_VEX_0FE0 */
5222   {
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5226   },
5227
5228   /* PREFIX_VEX_0FE1 */
5229   {
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5233   },
5234
5235   /* PREFIX_VEX_0FE2 */
5236   {
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5240   },
5241
5242   /* PREFIX_VEX_0FE3 */
5243   {
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5247   },
5248
5249   /* PREFIX_VEX_0FE4 */
5250   {
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5254   },
5255
5256   /* PREFIX_VEX_0FE5 */
5257   {
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5261   },
5262
5263   /* PREFIX_VEX_0FE6 */
5264   {
5265     { Bad_Opcode },
5266     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5267     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5268     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5269   },
5270
5271   /* PREFIX_VEX_0FE7 */
5272   {
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5276   },
5277
5278   /* PREFIX_VEX_0FE8 */
5279   {
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5283   },
5284
5285   /* PREFIX_VEX_0FE9 */
5286   {
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5290   },
5291
5292   /* PREFIX_VEX_0FEA */
5293   {
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5297   },
5298
5299   /* PREFIX_VEX_0FEB */
5300   {
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5304   },
5305
5306   /* PREFIX_VEX_0FEC */
5307   {
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5311   },
5312
5313   /* PREFIX_VEX_0FED */
5314   {
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5318   },
5319
5320   /* PREFIX_VEX_0FEE */
5321   {
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5325   },
5326
5327   /* PREFIX_VEX_0FEF */
5328   {
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5332   },
5333
5334   /* PREFIX_VEX_0FF0 */
5335   {
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5340   },
5341
5342   /* PREFIX_VEX_0FF1 */
5343   {
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5347   },
5348
5349   /* PREFIX_VEX_0FF2 */
5350   {
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5354   },
5355
5356   /* PREFIX_VEX_0FF3 */
5357   {
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5361   },
5362
5363   /* PREFIX_VEX_0FF4 */
5364   {
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5368   },
5369
5370   /* PREFIX_VEX_0FF5 */
5371   {
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5375   },
5376
5377   /* PREFIX_VEX_0FF6 */
5378   {
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5382   },
5383
5384   /* PREFIX_VEX_0FF7 */
5385   {
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5389   },
5390
5391   /* PREFIX_VEX_0FF8 */
5392   {
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5396   },
5397
5398   /* PREFIX_VEX_0FF9 */
5399   {
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5403   },
5404
5405   /* PREFIX_VEX_0FFA */
5406   {
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5410   },
5411
5412   /* PREFIX_VEX_0FFB */
5413   {
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5417   },
5418
5419   /* PREFIX_VEX_0FFC */
5420   {
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5424   },
5425
5426   /* PREFIX_VEX_0FFD */
5427   {
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5431   },
5432
5433   /* PREFIX_VEX_0FFE */
5434   {
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5438   },
5439
5440   /* PREFIX_VEX_0F3800 */
5441   {
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5445   },
5446
5447   /* PREFIX_VEX_0F3801 */
5448   {
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5452   },
5453
5454   /* PREFIX_VEX_0F3802 */
5455   {
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5459   },
5460
5461   /* PREFIX_VEX_0F3803 */
5462   {
5463     { Bad_Opcode },
5464     { Bad_Opcode },
5465     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5466   },
5467
5468   /* PREFIX_VEX_0F3804 */
5469   {
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5473   },
5474
5475   /* PREFIX_VEX_0F3805 */
5476   {
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5480   },
5481
5482   /* PREFIX_VEX_0F3806 */
5483   {
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5487   },
5488
5489   /* PREFIX_VEX_0F3807 */
5490   {
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5494   },
5495
5496   /* PREFIX_VEX_0F3808 */
5497   {
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5501   },
5502
5503   /* PREFIX_VEX_0F3809 */
5504   {
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5508   },
5509
5510   /* PREFIX_VEX_0F380A */
5511   {
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5515   },
5516
5517   /* PREFIX_VEX_0F380B */
5518   {
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5522   },
5523
5524   /* PREFIX_VEX_0F380C */
5525   {
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5529   },
5530
5531   /* PREFIX_VEX_0F380D */
5532   {
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5536   },
5537
5538   /* PREFIX_VEX_0F380E */
5539   {
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5543   },
5544
5545   /* PREFIX_VEX_0F380F */
5546   {
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5550   },
5551
5552   /* PREFIX_VEX_0F3813 */
5553   {
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5557   },
5558
5559   /* PREFIX_VEX_0F3816 */
5560   {
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5564   },
5565
5566   /* PREFIX_VEX_0F3817 */
5567   {
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5571   },
5572
5573   /* PREFIX_VEX_0F3818 */
5574   {
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5578   },
5579
5580   /* PREFIX_VEX_0F3819 */
5581   {
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5585   },
5586
5587   /* PREFIX_VEX_0F381A */
5588   {
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5592   },
5593
5594   /* PREFIX_VEX_0F381C */
5595   {
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5599   },
5600
5601   /* PREFIX_VEX_0F381D */
5602   {
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5606   },
5607
5608   /* PREFIX_VEX_0F381E */
5609   {
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5613   },
5614
5615   /* PREFIX_VEX_0F3820 */
5616   {
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5620   },
5621
5622   /* PREFIX_VEX_0F3821 */
5623   {
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5627   },
5628
5629   /* PREFIX_VEX_0F3822 */
5630   {
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5634   },
5635
5636   /* PREFIX_VEX_0F3823 */
5637   {
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5641   },
5642
5643   /* PREFIX_VEX_0F3824 */
5644   {
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5648   },
5649
5650   /* PREFIX_VEX_0F3825 */
5651   {
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5655   },
5656
5657   /* PREFIX_VEX_0F3828 */
5658   {
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5662   },
5663
5664   /* PREFIX_VEX_0F3829 */
5665   {
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5669   },
5670
5671   /* PREFIX_VEX_0F382A */
5672   {
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5676   },
5677
5678   /* PREFIX_VEX_0F382B */
5679   {
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5683   },
5684
5685   /* PREFIX_VEX_0F382C */
5686   {
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5690   },
5691
5692   /* PREFIX_VEX_0F382D */
5693   {
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5697   },
5698
5699   /* PREFIX_VEX_0F382E */
5700   {
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5704   },
5705
5706   /* PREFIX_VEX_0F382F */
5707   {
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5711   },
5712
5713   /* PREFIX_VEX_0F3830 */
5714   {
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5718   },
5719
5720   /* PREFIX_VEX_0F3831 */
5721   {
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5725   },
5726
5727   /* PREFIX_VEX_0F3832 */
5728   {
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5732   },
5733
5734   /* PREFIX_VEX_0F3833 */
5735   {
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5739   },
5740
5741   /* PREFIX_VEX_0F3834 */
5742   {
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5746   },
5747
5748   /* PREFIX_VEX_0F3835 */
5749   {
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5753   },
5754
5755   /* PREFIX_VEX_0F3836 */
5756   {
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5760   },
5761
5762   /* PREFIX_VEX_0F3837 */
5763   {
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5767   },
5768
5769   /* PREFIX_VEX_0F3838 */
5770   {
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5774   },
5775
5776   /* PREFIX_VEX_0F3839 */
5777   {
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5781   },
5782
5783   /* PREFIX_VEX_0F383A */
5784   {
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5788   },
5789
5790   /* PREFIX_VEX_0F383B */
5791   {
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5795   },
5796
5797   /* PREFIX_VEX_0F383C */
5798   {
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5802   },
5803
5804   /* PREFIX_VEX_0F383D */
5805   {
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5809   },
5810
5811   /* PREFIX_VEX_0F383E */
5812   {
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5816   },
5817
5818   /* PREFIX_VEX_0F383F */
5819   {
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5823   },
5824
5825   /* PREFIX_VEX_0F3840 */
5826   {
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5830   },
5831
5832   /* PREFIX_VEX_0F3841 */
5833   {
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5837   },
5838
5839   /* PREFIX_VEX_0F3845 */
5840   {
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5844   },
5845
5846   /* PREFIX_VEX_0F3846 */
5847   {
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5851   },
5852
5853   /* PREFIX_VEX_0F3847 */
5854   {
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5858   },
5859
5860   /* PREFIX_VEX_0F3858 */
5861   {
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5865   },
5866
5867   /* PREFIX_VEX_0F3859 */
5868   {
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5872   },
5873
5874   /* PREFIX_VEX_0F385A */
5875   {
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5879   },
5880
5881   /* PREFIX_VEX_0F3878 */
5882   {
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5886   },
5887
5888   /* PREFIX_VEX_0F3879 */
5889   {
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5893   },
5894
5895   /* PREFIX_VEX_0F388C */
5896   {
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5900   },
5901
5902   /* PREFIX_VEX_0F388E */
5903   {
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5907   },
5908
5909   /* PREFIX_VEX_0F3890 */
5910   {
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5914   },
5915
5916   /* PREFIX_VEX_0F3891 */
5917   {
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5921   },
5922
5923   /* PREFIX_VEX_0F3892 */
5924   {
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5928   },
5929
5930   /* PREFIX_VEX_0F3893 */
5931   {
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5935   },
5936
5937   /* PREFIX_VEX_0F3896 */
5938   {
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
5942   },
5943
5944   /* PREFIX_VEX_0F3897 */
5945   {
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
5949   },
5950
5951   /* PREFIX_VEX_0F3898 */
5952   {
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
5956   },
5957
5958   /* PREFIX_VEX_0F3899 */
5959   {
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5963   },
5964
5965   /* PREFIX_VEX_0F389A */
5966   {
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5970   },
5971
5972   /* PREFIX_VEX_0F389B */
5973   {
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5977   },
5978
5979   /* PREFIX_VEX_0F389C */
5980   {
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
5984   },
5985
5986   /* PREFIX_VEX_0F389D */
5987   {
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5991   },
5992
5993   /* PREFIX_VEX_0F389E */
5994   {
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
5998   },
5999
6000   /* PREFIX_VEX_0F389F */
6001   {
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6005   },
6006
6007   /* PREFIX_VEX_0F38A6 */
6008   {
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6012     { Bad_Opcode },
6013   },
6014
6015   /* PREFIX_VEX_0F38A7 */
6016   {
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6020   },
6021
6022   /* PREFIX_VEX_0F38A8 */
6023   {
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6027   },
6028
6029   /* PREFIX_VEX_0F38A9 */
6030   {
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6034   },
6035
6036   /* PREFIX_VEX_0F38AA */
6037   {
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6041   },
6042
6043   /* PREFIX_VEX_0F38AB */
6044   {
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6048   },
6049
6050   /* PREFIX_VEX_0F38AC */
6051   {
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6055   },
6056
6057   /* PREFIX_VEX_0F38AD */
6058   {
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6062   },
6063
6064   /* PREFIX_VEX_0F38AE */
6065   {
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6069   },
6070
6071   /* PREFIX_VEX_0F38AF */
6072   {
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6076   },
6077
6078   /* PREFIX_VEX_0F38B6 */
6079   {
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6083   },
6084
6085   /* PREFIX_VEX_0F38B7 */
6086   {
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6090   },
6091
6092   /* PREFIX_VEX_0F38B8 */
6093   {
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6097   },
6098
6099   /* PREFIX_VEX_0F38B9 */
6100   {
6101     { Bad_Opcode },
6102     { Bad_Opcode },
6103     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6104   },
6105
6106   /* PREFIX_VEX_0F38BA */
6107   {
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6111   },
6112
6113   /* PREFIX_VEX_0F38BB */
6114   {
6115     { Bad_Opcode },
6116     { Bad_Opcode },
6117     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6118   },
6119
6120   /* PREFIX_VEX_0F38BC */
6121   {
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6125   },
6126
6127   /* PREFIX_VEX_0F38BD */
6128   {
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6132   },
6133
6134   /* PREFIX_VEX_0F38BE */
6135   {
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6139   },
6140
6141   /* PREFIX_VEX_0F38BF */
6142   {
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6146   },
6147
6148   /* PREFIX_VEX_0F38DB */
6149   {
6150     { Bad_Opcode },
6151     { Bad_Opcode },
6152     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6153   },
6154
6155   /* PREFIX_VEX_0F38DC */
6156   {
6157     { Bad_Opcode },
6158     { Bad_Opcode },
6159     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6160   },
6161
6162   /* PREFIX_VEX_0F38DD */
6163   {
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6167   },
6168
6169   /* PREFIX_VEX_0F38DE */
6170   {
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6174   },
6175
6176   /* PREFIX_VEX_0F38DF */
6177   {
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6181   },
6182
6183   /* PREFIX_VEX_0F38F2 */
6184   {
6185     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6186   },
6187
6188   /* PREFIX_VEX_0F38F3_REG_1 */
6189   {
6190     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6191   },
6192
6193   /* PREFIX_VEX_0F38F3_REG_2 */
6194   {
6195     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6196   },
6197
6198   /* PREFIX_VEX_0F38F3_REG_3 */
6199   {
6200     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6201   },
6202
6203   /* PREFIX_VEX_0F38F5 */
6204   {
6205     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6206     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6207     { Bad_Opcode },
6208     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6209   },
6210
6211   /* PREFIX_VEX_0F38F6 */
6212   {
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6217   },
6218
6219   /* PREFIX_VEX_0F38F7 */
6220   {
6221     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6222     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6223     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6224     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6225   },
6226
6227   /* PREFIX_VEX_0F3A00 */
6228   {
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6232   },
6233
6234   /* PREFIX_VEX_0F3A01 */
6235   {
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6239   },
6240
6241   /* PREFIX_VEX_0F3A02 */
6242   {
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6246   },
6247
6248   /* PREFIX_VEX_0F3A04 */
6249   {
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6253   },
6254
6255   /* PREFIX_VEX_0F3A05 */
6256   {
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6260   },
6261
6262   /* PREFIX_VEX_0F3A06 */
6263   {
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6267   },
6268
6269   /* PREFIX_VEX_0F3A08 */
6270   {
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6274   },
6275
6276   /* PREFIX_VEX_0F3A09 */
6277   {
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6281   },
6282
6283   /* PREFIX_VEX_0F3A0A */
6284   {
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6288   },
6289
6290   /* PREFIX_VEX_0F3A0B */
6291   {
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6295   },
6296
6297   /* PREFIX_VEX_0F3A0C */
6298   {
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6302   },
6303
6304   /* PREFIX_VEX_0F3A0D */
6305   {
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6309   },
6310
6311   /* PREFIX_VEX_0F3A0E */
6312   {
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6316   },
6317
6318   /* PREFIX_VEX_0F3A0F */
6319   {
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6323   },
6324
6325   /* PREFIX_VEX_0F3A14 */
6326   {
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6330   },
6331
6332   /* PREFIX_VEX_0F3A15 */
6333   {
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6337   },
6338
6339   /* PREFIX_VEX_0F3A16 */
6340   {
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6344   },
6345
6346   /* PREFIX_VEX_0F3A17 */
6347   {
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6351   },
6352
6353   /* PREFIX_VEX_0F3A18 */
6354   {
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6358   },
6359
6360   /* PREFIX_VEX_0F3A19 */
6361   {
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6365   },
6366
6367   /* PREFIX_VEX_0F3A1D */
6368   {
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6372   },
6373
6374   /* PREFIX_VEX_0F3A20 */
6375   {
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6379   },
6380
6381   /* PREFIX_VEX_0F3A21 */
6382   {
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6386   },
6387
6388   /* PREFIX_VEX_0F3A22 */
6389   {
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6393   },
6394
6395   /* PREFIX_VEX_0F3A30 */
6396   {
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6400   },
6401
6402   /* PREFIX_VEX_0F3A31 */
6403   {
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6407   },
6408
6409   /* PREFIX_VEX_0F3A32 */
6410   {
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6414   },
6415
6416   /* PREFIX_VEX_0F3A33 */
6417   {
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6421   },
6422
6423   /* PREFIX_VEX_0F3A38 */
6424   {
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6428   },
6429
6430   /* PREFIX_VEX_0F3A39 */
6431   {
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6435   },
6436
6437   /* PREFIX_VEX_0F3A40 */
6438   {
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6442   },
6443
6444   /* PREFIX_VEX_0F3A41 */
6445   {
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6449   },
6450
6451   /* PREFIX_VEX_0F3A42 */
6452   {
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6456   },
6457
6458   /* PREFIX_VEX_0F3A44 */
6459   {
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6463   },
6464
6465   /* PREFIX_VEX_0F3A46 */
6466   {
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6470   },
6471
6472   /* PREFIX_VEX_0F3A48 */
6473   {
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6477   },
6478
6479   /* PREFIX_VEX_0F3A49 */
6480   {
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6484   },
6485
6486   /* PREFIX_VEX_0F3A4A */
6487   {
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6491   },
6492
6493   /* PREFIX_VEX_0F3A4B */
6494   {
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6498   },
6499
6500   /* PREFIX_VEX_0F3A4C */
6501   {
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6505   },
6506
6507   /* PREFIX_VEX_0F3A5C */
6508   {
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6512   },
6513
6514   /* PREFIX_VEX_0F3A5D */
6515   {
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6519   },
6520
6521   /* PREFIX_VEX_0F3A5E */
6522   {
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6526   },
6527
6528   /* PREFIX_VEX_0F3A5F */
6529   {
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6533   },
6534
6535   /* PREFIX_VEX_0F3A60 */
6536   {
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6540     { Bad_Opcode },
6541   },
6542
6543   /* PREFIX_VEX_0F3A61 */
6544   {
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6548   },
6549
6550   /* PREFIX_VEX_0F3A62 */
6551   {
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6555   },
6556
6557   /* PREFIX_VEX_0F3A63 */
6558   {
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6562   },
6563
6564   /* PREFIX_VEX_0F3A68 */
6565   {
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6569   },
6570
6571   /* PREFIX_VEX_0F3A69 */
6572   {
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6576   },
6577
6578   /* PREFIX_VEX_0F3A6A */
6579   {
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6583   },
6584
6585   /* PREFIX_VEX_0F3A6B */
6586   {
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6590   },
6591
6592   /* PREFIX_VEX_0F3A6C */
6593   {
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6597   },
6598
6599   /* PREFIX_VEX_0F3A6D */
6600   {
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6604   },
6605
6606   /* PREFIX_VEX_0F3A6E */
6607   {
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6611   },
6612
6613   /* PREFIX_VEX_0F3A6F */
6614   {
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6618   },
6619
6620   /* PREFIX_VEX_0F3A78 */
6621   {
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6625   },
6626
6627   /* PREFIX_VEX_0F3A79 */
6628   {
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6632   },
6633
6634   /* PREFIX_VEX_0F3A7A */
6635   {
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6639   },
6640
6641   /* PREFIX_VEX_0F3A7B */
6642   {
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6646   },
6647
6648   /* PREFIX_VEX_0F3A7C */
6649   {
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6653     { Bad_Opcode },
6654   },
6655
6656   /* PREFIX_VEX_0F3A7D */
6657   {
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6661   },
6662
6663   /* PREFIX_VEX_0F3A7E */
6664   {
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6668   },
6669
6670   /* PREFIX_VEX_0F3A7F */
6671   {
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6675   },
6676
6677   /* PREFIX_VEX_0F3ADF */
6678   {
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6682   },
6683
6684   /* PREFIX_VEX_0F3AF0 */
6685   {
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6690   },
6691
6692 #define NEED_PREFIX_TABLE
6693 #include "i386-dis-evex.h"
6694 #undef NEED_PREFIX_TABLE
6695 };
6696
6697 static const struct dis386 x86_64_table[][2] = {
6698   /* X86_64_06 */
6699   {
6700     { "pushP", { es }, 0 },
6701   },
6702
6703   /* X86_64_07 */
6704   {
6705     { "popP", { es }, 0 },
6706   },
6707
6708   /* X86_64_0D */
6709   {
6710     { "pushP", { cs }, 0 },
6711   },
6712
6713   /* X86_64_16 */
6714   {
6715     { "pushP", { ss }, 0 },
6716   },
6717
6718   /* X86_64_17 */
6719   {
6720     { "popP", { ss }, 0 },
6721   },
6722
6723   /* X86_64_1E */
6724   {
6725     { "pushP", { ds }, 0 },
6726   },
6727
6728   /* X86_64_1F */
6729   {
6730     { "popP", { ds }, 0 },
6731   },
6732
6733   /* X86_64_27 */
6734   {
6735     { "daa", { XX }, 0 },
6736   },
6737
6738   /* X86_64_2F */
6739   {
6740     { "das", { XX }, 0 },
6741   },
6742
6743   /* X86_64_37 */
6744   {
6745     { "aaa", { XX }, 0 },
6746   },
6747
6748   /* X86_64_3F */
6749   {
6750     { "aas", { XX }, 0 },
6751   },
6752
6753   /* X86_64_60 */
6754   {
6755     { "pushaP", { XX }, 0 },
6756   },
6757
6758   /* X86_64_61 */
6759   {
6760     { "popaP", { XX }, 0 },
6761   },
6762
6763   /* X86_64_62 */
6764   {
6765     { MOD_TABLE (MOD_62_32BIT) },
6766     { EVEX_TABLE (EVEX_0F) },
6767   },
6768
6769   /* X86_64_63 */
6770   {
6771     { "arpl", { Ew, Gw }, 0 },
6772     { "movs{lq|xd}", { Gv, Ed }, 0 },
6773   },
6774
6775   /* X86_64_6D */
6776   {
6777     { "ins{R|}", { Yzr, indirDX }, 0 },
6778     { "ins{G|}", { Yzr, indirDX }, 0 },
6779   },
6780
6781   /* X86_64_6F */
6782   {
6783     { "outs{R|}", { indirDXr, Xz }, 0 },
6784     { "outs{G|}", { indirDXr, Xz }, 0 },
6785   },
6786
6787   /* X86_64_9A */
6788   {
6789     { "Jcall{T|}", { Ap }, 0 },
6790   },
6791
6792   /* X86_64_C4 */
6793   {
6794     { MOD_TABLE (MOD_C4_32BIT) },
6795     { VEX_C4_TABLE (VEX_0F) },
6796   },
6797
6798   /* X86_64_C5 */
6799   {
6800     { MOD_TABLE (MOD_C5_32BIT) },
6801     { VEX_C5_TABLE (VEX_0F) },
6802   },
6803
6804   /* X86_64_CE */
6805   {
6806     { "into", { XX }, 0 },
6807   },
6808
6809   /* X86_64_D4 */
6810   {
6811     { "aam", { Ib }, 0 },
6812   },
6813
6814   /* X86_64_D5 */
6815   {
6816     { "aad", { Ib }, 0 },
6817   },
6818
6819   /* X86_64_EA */
6820   {
6821     { "Jjmp{T|}", { Ap }, 0 },
6822   },
6823
6824   /* X86_64_0F01_REG_0 */
6825   {
6826     { "sgdt{Q|IQ}", { M }, 0 },
6827     { "sgdt", { M }, 0 },
6828   },
6829
6830   /* X86_64_0F01_REG_1 */
6831   {
6832     { "sidt{Q|IQ}", { M }, 0 },
6833     { "sidt", { M }, 0 },
6834   },
6835
6836   /* X86_64_0F01_REG_2 */
6837   {
6838     { "lgdt{Q|Q}", { M }, 0 },
6839     { "lgdt", { M }, 0 },
6840   },
6841
6842   /* X86_64_0F01_REG_3 */
6843   {
6844     { "lidt{Q|Q}", { M }, 0 },
6845     { "lidt", { M }, 0 },
6846   },
6847 };
6848
6849 static const struct dis386 three_byte_table[][256] = {
6850
6851   /* THREE_BYTE_0F38 */
6852   {
6853     /* 00 */
6854     { "pshufb",         { MX, EM }, PREFIX_MANDATORY },
6855     { "phaddw",         { MX, EM }, PREFIX_MANDATORY },
6856     { "phaddd",         { MX, EM }, PREFIX_MANDATORY },
6857     { "phaddsw",        { MX, EM }, PREFIX_MANDATORY },
6858     { "pmaddubsw",      { MX, EM }, PREFIX_MANDATORY },
6859     { "phsubw",         { MX, EM }, PREFIX_MANDATORY },
6860     { "phsubd",         { MX, EM }, PREFIX_MANDATORY },
6861     { "phsubsw",        { MX, EM }, PREFIX_MANDATORY },
6862     /* 08 */
6863     { "psignb",         { MX, EM }, PREFIX_MANDATORY },
6864     { "psignw",         { MX, EM }, PREFIX_MANDATORY },
6865     { "psignd",         { MX, EM }, PREFIX_MANDATORY },
6866     { "pmulhrsw",       { MX, EM }, PREFIX_MANDATORY },
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     /* 10 */
6872     { PREFIX_TABLE (PREFIX_0F3810) },
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { PREFIX_TABLE (PREFIX_0F3814) },
6877     { PREFIX_TABLE (PREFIX_0F3815) },
6878     { Bad_Opcode },
6879     { PREFIX_TABLE (PREFIX_0F3817) },
6880     /* 18 */
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { "pabsb",          { MX, EM }, PREFIX_MANDATORY },
6886     { "pabsw",          { MX, EM }, PREFIX_MANDATORY },
6887     { "pabsd",          { MX, EM }, PREFIX_MANDATORY },
6888     { Bad_Opcode },
6889     /* 20 */
6890     { PREFIX_TABLE (PREFIX_0F3820) },
6891     { PREFIX_TABLE (PREFIX_0F3821) },
6892     { PREFIX_TABLE (PREFIX_0F3822) },
6893     { PREFIX_TABLE (PREFIX_0F3823) },
6894     { PREFIX_TABLE (PREFIX_0F3824) },
6895     { PREFIX_TABLE (PREFIX_0F3825) },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     /* 28 */
6899     { PREFIX_TABLE (PREFIX_0F3828) },
6900     { PREFIX_TABLE (PREFIX_0F3829) },
6901     { PREFIX_TABLE (PREFIX_0F382A) },
6902     { PREFIX_TABLE (PREFIX_0F382B) },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     /* 30 */
6908     { PREFIX_TABLE (PREFIX_0F3830) },
6909     { PREFIX_TABLE (PREFIX_0F3831) },
6910     { PREFIX_TABLE (PREFIX_0F3832) },
6911     { PREFIX_TABLE (PREFIX_0F3833) },
6912     { PREFIX_TABLE (PREFIX_0F3834) },
6913     { PREFIX_TABLE (PREFIX_0F3835) },
6914     { Bad_Opcode },
6915     { PREFIX_TABLE (PREFIX_0F3837) },
6916     /* 38 */
6917     { PREFIX_TABLE (PREFIX_0F3838) },
6918     { PREFIX_TABLE (PREFIX_0F3839) },
6919     { PREFIX_TABLE (PREFIX_0F383A) },
6920     { PREFIX_TABLE (PREFIX_0F383B) },
6921     { PREFIX_TABLE (PREFIX_0F383C) },
6922     { PREFIX_TABLE (PREFIX_0F383D) },
6923     { PREFIX_TABLE (PREFIX_0F383E) },
6924     { PREFIX_TABLE (PREFIX_0F383F) },
6925     /* 40 */
6926     { PREFIX_TABLE (PREFIX_0F3840) },
6927     { PREFIX_TABLE (PREFIX_0F3841) },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     /* 48 */
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     /* 50 */
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     /* 58 */
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     /* 60 */
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     /* 68 */
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     /* 70 */
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     /* 78 */
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     /* 80 */
6998     { PREFIX_TABLE (PREFIX_0F3880) },
6999     { PREFIX_TABLE (PREFIX_0F3881) },
7000     { PREFIX_TABLE (PREFIX_0F3882) },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     /* 88 */
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     /* 90 */
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     /* 98 */
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     /* a0 */
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     /* a8 */
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     /* b0 */
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     /* b8 */
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     /* c0 */
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     /* c8 */
7079     { PREFIX_TABLE (PREFIX_0F38C8) },
7080     { PREFIX_TABLE (PREFIX_0F38C9) },
7081     { PREFIX_TABLE (PREFIX_0F38CA) },
7082     { PREFIX_TABLE (PREFIX_0F38CB) },
7083     { PREFIX_TABLE (PREFIX_0F38CC) },
7084     { PREFIX_TABLE (PREFIX_0F38CD) },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     /* d0 */
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     /* d8 */
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { PREFIX_TABLE (PREFIX_0F38DB) },
7101     { PREFIX_TABLE (PREFIX_0F38DC) },
7102     { PREFIX_TABLE (PREFIX_0F38DD) },
7103     { PREFIX_TABLE (PREFIX_0F38DE) },
7104     { PREFIX_TABLE (PREFIX_0F38DF) },
7105     /* e0 */
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     /* e8 */
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     /* f0 */
7124     { PREFIX_TABLE (PREFIX_0F38F0) },
7125     { PREFIX_TABLE (PREFIX_0F38F1) },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { PREFIX_TABLE (PREFIX_0F38F6) },
7131     { Bad_Opcode },
7132     /* f8 */
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141   },
7142   /* THREE_BYTE_0F3A */
7143   {
7144     /* 00 */
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     /* 08 */
7154     { PREFIX_TABLE (PREFIX_0F3A08) },
7155     { PREFIX_TABLE (PREFIX_0F3A09) },
7156     { PREFIX_TABLE (PREFIX_0F3A0A) },
7157     { PREFIX_TABLE (PREFIX_0F3A0B) },
7158     { PREFIX_TABLE (PREFIX_0F3A0C) },
7159     { PREFIX_TABLE (PREFIX_0F3A0D) },
7160     { PREFIX_TABLE (PREFIX_0F3A0E) },
7161     { "palignr",        { MX, EM, Ib }, PREFIX_MANDATORY },
7162     /* 10 */
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { PREFIX_TABLE (PREFIX_0F3A14) },
7168     { PREFIX_TABLE (PREFIX_0F3A15) },
7169     { PREFIX_TABLE (PREFIX_0F3A16) },
7170     { PREFIX_TABLE (PREFIX_0F3A17) },
7171     /* 18 */
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     /* 20 */
7181     { PREFIX_TABLE (PREFIX_0F3A20) },
7182     { PREFIX_TABLE (PREFIX_0F3A21) },
7183     { PREFIX_TABLE (PREFIX_0F3A22) },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     /* 28 */
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     /* 30 */
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     /* 38 */
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     /* 40 */
7217     { PREFIX_TABLE (PREFIX_0F3A40) },
7218     { PREFIX_TABLE (PREFIX_0F3A41) },
7219     { PREFIX_TABLE (PREFIX_0F3A42) },
7220     { Bad_Opcode },
7221     { PREFIX_TABLE (PREFIX_0F3A44) },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     /* 48 */
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     /* 50 */
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     /* 58 */
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     /* 60 */
7253     { PREFIX_TABLE (PREFIX_0F3A60) },
7254     { PREFIX_TABLE (PREFIX_0F3A61) },
7255     { PREFIX_TABLE (PREFIX_0F3A62) },
7256     { PREFIX_TABLE (PREFIX_0F3A63) },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     /* 68 */
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     /* 70 */
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     /* 78 */
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     /* 80 */
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     /* 88 */
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     /* 90 */
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     /* 98 */
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     /* a0 */
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     /* a8 */
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     /* b0 */
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     /* b8 */
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     /* c0 */
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     /* c8 */
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { PREFIX_TABLE (PREFIX_0F3ACC) },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     /* d0 */
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     /* d8 */
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { PREFIX_TABLE (PREFIX_0F3ADF) },
7396     /* e0 */
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     /* e8 */
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     /* f0 */
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     /* f8 */
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432   },
7433
7434   /* THREE_BYTE_0F7A */
7435   {
7436     /* 00 */
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     /* 08 */
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     /* 10 */
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     /* 18 */
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     /* 20 */
7473     { "ptest",          { XX }, PREFIX_MANDATORY },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     /* 28 */
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     /* 30 */
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     /* 38 */
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     /* 40 */
7509     { Bad_Opcode },
7510     { "phaddbw",        { XM, EXq }, PREFIX_MANDATORY },
7511     { "phaddbd",        { XM, EXq }, PREFIX_MANDATORY },
7512     { "phaddbq",        { XM, EXq }, PREFIX_MANDATORY },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { "phaddwd",        { XM, EXq }, PREFIX_MANDATORY },
7516     { "phaddwq",        { XM, EXq }, PREFIX_MANDATORY },
7517     /* 48 */
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { "phadddq",        { XM, EXq }, PREFIX_MANDATORY },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     /* 50 */
7527     { Bad_Opcode },
7528     { "phaddubw",       { XM, EXq }, PREFIX_MANDATORY },
7529     { "phaddubd",       { XM, EXq }, PREFIX_MANDATORY },
7530     { "phaddubq",       { XM, EXq }, PREFIX_MANDATORY },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { "phadduwd",       { XM, EXq }, PREFIX_MANDATORY },
7534     { "phadduwq",       { XM, EXq }, PREFIX_MANDATORY },
7535     /* 58 */
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { "phaddudq",       { XM, EXq }, PREFIX_MANDATORY },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     /* 60 */
7545     { Bad_Opcode },
7546     { "phsubbw",        { XM, EXq }, PREFIX_MANDATORY },
7547     { "phsubbd",        { XM, EXq }, PREFIX_MANDATORY },
7548     { "phsubbq",        { XM, EXq }, PREFIX_MANDATORY },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     /* 68 */
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     /* 70 */
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     /* 78 */
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     /* 80 */
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     /* 88 */
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     /* 90 */
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     /* 98 */
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     /* a0 */
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     /* a8 */
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     /* b0 */
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     /* b8 */
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     /* c0 */
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     /* c8 */
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     /* d0 */
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     /* d8 */
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     /* e0 */
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     /* e8 */
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     /* f0 */
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     /* f8 */
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724   },
7725 };
7726
7727 static const struct dis386 xop_table[][256] = {
7728   /* XOP_08 */
7729   {
7730     /* 00 */
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     /* 08 */
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     /* 10 */
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     /* 18 */
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     /* 20 */
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     /* 28 */
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     /* 30 */
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     /* 38 */
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     /* 40 */
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     /* 48 */
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     /* 50 */
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     /* 58 */
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     /* 60 */
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     /* 68 */
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     /* 70 */
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     /* 78 */
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     /* 80 */
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7881     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7882     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7883     /* 88 */
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7891     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7892     /* 90 */
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7899     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7900     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7901     /* 98 */
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7909     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7910     /* a0 */
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7914     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7918     { Bad_Opcode },
7919     /* a8 */
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     /* b0 */
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7936     { Bad_Opcode },
7937     /* b8 */
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     /* c0 */
7947     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7948     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7949     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7950     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     /* c8 */
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7961     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7962     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7963     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7964     /* d0 */
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     /* d8 */
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     /* e0 */
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     /* e8 */
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7997     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7998     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7999     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8000     /* f0 */
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     /* f8 */
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018   },
8019   /* XOP_09 */
8020   {
8021     /* 00 */
8022     { Bad_Opcode },
8023     { REG_TABLE (REG_XOP_TBM_01) },
8024     { REG_TABLE (REG_XOP_TBM_02) },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     /* 08 */
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     /* 10 */
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { REG_TABLE (REG_XOP_LWPCB) },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     /* 18 */
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     /* 20 */
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     /* 28 */
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     /* 30 */
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     /* 38 */
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     /* 40 */
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     /* 48 */
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     /* 50 */
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     /* 58 */
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     /* 60 */
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     /* 68 */
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     /* 70 */
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     /* 78 */
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     /* 80 */
8166     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8167     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8168     { "vfrczss",        { XM, EXd }, 0 },
8169     { "vfrczsd",        { XM, EXq }, 0 },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     /* 88 */
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     /* 90 */
8184     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8185     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8186     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8187     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8188     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8189     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8190     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8191     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8192     /* 98 */
8193     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8194     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8195     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8196     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     /* a0 */
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     /* a8 */
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     /* b0 */
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     /* b8 */
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     /* c0 */
8238     { Bad_Opcode },
8239     { "vphaddbw",       { XM, EXxmm }, 0 },
8240     { "vphaddbd",       { XM, EXxmm }, 0 },
8241     { "vphaddbq",       { XM, EXxmm }, 0 },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { "vphaddwd",       { XM, EXxmm }, 0 },
8245     { "vphaddwq",       { XM, EXxmm }, 0 },
8246     /* c8 */
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { "vphadddq",       { XM, EXxmm }, 0 },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     /* d0 */
8256     { Bad_Opcode },
8257     { "vphaddubw",      { XM, EXxmm }, 0 },
8258     { "vphaddubd",      { XM, EXxmm }, 0 },
8259     { "vphaddubq",      { XM, EXxmm }, 0 },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { "vphadduwd",      { XM, EXxmm }, 0 },
8263     { "vphadduwq",      { XM, EXxmm }, 0 },
8264     /* d8 */
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { "vphaddudq",      { XM, EXxmm }, 0 },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     /* e0 */
8274     { Bad_Opcode },
8275     { "vphsubbw",       { XM, EXxmm }, 0 },
8276     { "vphsubwd",       { XM, EXxmm }, 0 },
8277     { "vphsubdq",       { XM, EXxmm }, 0 },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     /* e8 */
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     /* f0 */
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     /* f8 */
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309   },
8310   /* XOP_0A */
8311   {
8312     /* 00 */
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     /* 08 */
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     /* 10 */
8331     { "bextr",  { Gv, Ev, Iq }, 0 },
8332     { Bad_Opcode },
8333     { REG_TABLE (REG_XOP_LWP) },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     /* 18 */
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     /* 20 */
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     /* 28 */
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     /* 30 */
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     /* 38 */
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     /* 40 */
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     /* 48 */
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     /* 50 */
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     /* 58 */
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     /* 60 */
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     /* 68 */
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     /* 70 */
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     /* 78 */
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     /* 80 */
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     /* 88 */
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     /* 90 */
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     /* 98 */
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     /* a0 */
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     /* a8 */
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     /* b0 */
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     /* b8 */
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     /* c0 */
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     /* c8 */
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     /* d0 */
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     /* d8 */
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     /* e0 */
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     /* e8 */
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     /* f0 */
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     /* f8 */
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600   },
8601 };
8602
8603 static const struct dis386 vex_table[][256] = {
8604   /* VEX_0F */
8605   {
8606     /* 00 */
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     /* 08 */
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     /* 10 */
8625     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8626     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8627     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8628     { MOD_TABLE (MOD_VEX_0F13) },
8629     { VEX_W_TABLE (VEX_W_0F14) },
8630     { VEX_W_TABLE (VEX_W_0F15) },
8631     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8632     { MOD_TABLE (MOD_VEX_0F17) },
8633     /* 18 */
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     /* 20 */
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     /* 28 */
8652     { VEX_W_TABLE (VEX_W_0F28) },
8653     { VEX_W_TABLE (VEX_W_0F29) },
8654     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8655     { MOD_TABLE (MOD_VEX_0F2B) },
8656     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8657     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8658     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8659     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8660     /* 30 */
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     /* 38 */
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     /* 40 */
8679     { Bad_Opcode },
8680     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8681     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8682     { Bad_Opcode },
8683     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8684     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8685     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8686     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8687     /* 48 */
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8691     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     /* 50 */
8697     { MOD_TABLE (MOD_VEX_0F50) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8701     { "vandpX",         { XM, Vex, EXx }, 0 },
8702     { "vandnpX",        { XM, Vex, EXx }, 0 },
8703     { "vorpX",          { XM, Vex, EXx }, 0 },
8704     { "vxorpX",         { XM, Vex, EXx }, 0 },
8705     /* 58 */
8706     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8712     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8713     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8714     /* 60 */
8715     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8716     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8717     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8718     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8719     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8720     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8721     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8723     /* 68 */
8724     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8732     /* 70 */
8733     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8734     { REG_TABLE (REG_VEX_0F71) },
8735     { REG_TABLE (REG_VEX_0F72) },
8736     { REG_TABLE (REG_VEX_0F73) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8741     /* 78 */
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8750     /* 80 */
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     { Bad_Opcode },
8759     /* 88 */
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     /* 90 */
8769     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     /* 98 */
8778     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     /* a0 */
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     /* a8 */
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { REG_TABLE (REG_VEX_0FAE) },
8803     { Bad_Opcode },
8804     /* b0 */
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     /* b8 */
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     /* c0 */
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8826     { Bad_Opcode },
8827     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8828     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8829     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8830     { Bad_Opcode },
8831     /* c8 */
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     /* d0 */
8841     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8842     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8843     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8844     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8845     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8846     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8847     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8848     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8849     /* d8 */
8850     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8851     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8852     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8853     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8854     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8855     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8856     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8857     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8858     /* e0 */
8859     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8860     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8861     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8862     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8863     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8864     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8865     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8866     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8867     /* e8 */
8868     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8869     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8870     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8871     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8872     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8873     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8874     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8875     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8876     /* f0 */
8877     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8878     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8879     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8880     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8881     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8882     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8883     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8884     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8885     /* f8 */
8886     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8887     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8888     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8889     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8890     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8891     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8892     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8893     { Bad_Opcode },
8894   },
8895   /* VEX_0F38 */
8896   {
8897     /* 00 */
8898     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8906     /* 08 */
8907     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8909     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8915     /* 10 */
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8924     /* 18 */
8925     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8928     { Bad_Opcode },
8929     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8932     { Bad_Opcode },
8933     /* 20 */
8934     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     /* 28 */
8943     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8951     /* 30 */
8952     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8958     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8960     /* 38 */
8961     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8963     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8964     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8965     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8969     /* 40 */
8970     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8976     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8978     /* 48 */
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     /* 50 */
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     /* 58 */
8997     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     /* 60 */
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     /* 68 */
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     /* 70 */
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     /* 78 */
9033     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9034     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     /* 80 */
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     /* 88 */
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9056     { Bad_Opcode },
9057     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9058     { Bad_Opcode },
9059     /* 90 */
9060     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9061     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9062     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9063     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9068     /* 98 */
9069     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9077     /* a0 */
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9085     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9086     /* a8 */
9087     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9095     /* b0 */
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9103     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9104     /* b8 */
9105     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9106     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9107     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9108     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9113     /* c0 */
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     /* c8 */
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     /* d0 */
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     /* d8 */
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9145     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9146     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9147     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9148     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9149     /* e0 */
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     /* e8 */
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     /* f0 */
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9171     { REG_TABLE (REG_VEX_0F38F3) },
9172     { Bad_Opcode },
9173     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9174     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9175     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9176     /* f8 */
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185   },
9186   /* VEX_0F3A */
9187   {
9188     /* 00 */
9189     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9190     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9191     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9192     { Bad_Opcode },
9193     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9194     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9195     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9196     { Bad_Opcode },
9197     /* 08 */
9198     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9199     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9200     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9201     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9202     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9203     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9204     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9205     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9206     /* 10 */
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9212     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9213     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9214     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9215     /* 18 */
9216     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9217     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     /* 20 */
9225     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9226     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9227     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     /* 28 */
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     /* 30 */
9243     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9244     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9245     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9246     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     /* 38 */
9252     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9253     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     /* 40 */
9261     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9262     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9263     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9264     { Bad_Opcode },
9265     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9266     { Bad_Opcode },
9267     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9268     { Bad_Opcode },
9269     /* 48 */
9270     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9271     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9272     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9273     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9274     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     /* 50 */
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     /* 58 */
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9293     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9294     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9295     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9296     /* 60 */
9297     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9298     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9299     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9300     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     /* 68 */
9306     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9307     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9308     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9309     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9310     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9311     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9312     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9313     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9314     /* 70 */
9315     { Bad_Opcode },
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     /* 78 */
9324     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9325     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9326     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9327     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9328     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9329     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9330     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9331     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9332     /* 80 */
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     /* 88 */
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347     { Bad_Opcode },
9348     { Bad_Opcode },
9349     { Bad_Opcode },
9350     /* 90 */
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     /* 98 */
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     /* a0 */
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     { Bad_Opcode },
9373     { Bad_Opcode },
9374     { Bad_Opcode },
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     /* a8 */
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     /* b0 */
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     /* b8 */
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     /* c0 */
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     { Bad_Opcode },
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     /* c8 */
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     /* d0 */
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     { Bad_Opcode },
9427     { Bad_Opcode },
9428     { Bad_Opcode },
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     /* d8 */
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9440     /* e0 */
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     /* e8 */
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     /* f0 */
9459     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9460     { Bad_Opcode },
9461     { Bad_Opcode },
9462     { Bad_Opcode },
9463     { Bad_Opcode },
9464     { Bad_Opcode },
9465     { Bad_Opcode },
9466     { Bad_Opcode },
9467     /* f8 */
9468     { Bad_Opcode },
9469     { Bad_Opcode },
9470     { Bad_Opcode },
9471     { Bad_Opcode },
9472     { Bad_Opcode },
9473     { Bad_Opcode },
9474     { Bad_Opcode },
9475     { Bad_Opcode },
9476   },
9477 };
9478
9479 #define NEED_OPCODE_TABLE
9480 #include "i386-dis-evex.h"
9481 #undef NEED_OPCODE_TABLE
9482 static const struct dis386 vex_len_table[][2] = {
9483   /* VEX_LEN_0F10_P_1 */
9484   {
9485     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9486     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9487   },
9488
9489   /* VEX_LEN_0F10_P_3 */
9490   {
9491     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9492     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9493   },
9494
9495   /* VEX_LEN_0F11_P_1 */
9496   {
9497     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9498     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9499   },
9500
9501   /* VEX_LEN_0F11_P_3 */
9502   {
9503     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9504     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9505   },
9506
9507   /* VEX_LEN_0F12_P_0_M_0 */
9508   {
9509     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9510   },
9511
9512   /* VEX_LEN_0F12_P_0_M_1 */
9513   {
9514     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9515   },
9516
9517   /* VEX_LEN_0F12_P_2 */
9518   {
9519     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9520   },
9521
9522   /* VEX_LEN_0F13_M_0 */
9523   {
9524     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9525   },
9526
9527   /* VEX_LEN_0F16_P_0_M_0 */
9528   {
9529     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9530   },
9531
9532   /* VEX_LEN_0F16_P_0_M_1 */
9533   {
9534     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9535   },
9536
9537   /* VEX_LEN_0F16_P_2 */
9538   {
9539     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9540   },
9541
9542   /* VEX_LEN_0F17_M_0 */
9543   {
9544     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9545   },
9546
9547   /* VEX_LEN_0F2A_P_1 */
9548   {
9549     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9550     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9551   },
9552
9553   /* VEX_LEN_0F2A_P_3 */
9554   {
9555     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9556     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9557   },
9558
9559   /* VEX_LEN_0F2C_P_1 */
9560   {
9561     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9562     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9563   },
9564
9565   /* VEX_LEN_0F2C_P_3 */
9566   {
9567     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9568     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9569   },
9570
9571   /* VEX_LEN_0F2D_P_1 */
9572   {
9573     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9574     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9575   },
9576
9577   /* VEX_LEN_0F2D_P_3 */
9578   {
9579     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9580     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9581   },
9582
9583   /* VEX_LEN_0F2E_P_0 */
9584   {
9585     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9586     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9587   },
9588
9589   /* VEX_LEN_0F2E_P_2 */
9590   {
9591     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9592     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9593   },
9594
9595   /* VEX_LEN_0F2F_P_0 */
9596   {
9597     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9598     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9599   },
9600
9601   /* VEX_LEN_0F2F_P_2 */
9602   {
9603     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9604     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9605   },
9606
9607   /* VEX_LEN_0F41_P_0 */
9608   {
9609     { Bad_Opcode },
9610     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9611   },
9612   /* VEX_LEN_0F41_P_2 */
9613   {
9614     { Bad_Opcode },
9615     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9616   },
9617   /* VEX_LEN_0F42_P_0 */
9618   {
9619     { Bad_Opcode },
9620     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9621   },
9622   /* VEX_LEN_0F42_P_2 */
9623   {
9624     { Bad_Opcode },
9625     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9626   },
9627   /* VEX_LEN_0F44_P_0 */
9628   {
9629     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9630   },
9631   /* VEX_LEN_0F44_P_2 */
9632   {
9633     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9634   },
9635   /* VEX_LEN_0F45_P_0 */
9636   {
9637     { Bad_Opcode },
9638     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9639   },
9640   /* VEX_LEN_0F45_P_2 */
9641   {
9642     { Bad_Opcode },
9643     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9644   },
9645   /* VEX_LEN_0F46_P_0 */
9646   {
9647     { Bad_Opcode },
9648     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9649   },
9650   /* VEX_LEN_0F46_P_2 */
9651   {
9652     { Bad_Opcode },
9653     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9654   },
9655   /* VEX_LEN_0F47_P_0 */
9656   {
9657     { Bad_Opcode },
9658     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9659   },
9660   /* VEX_LEN_0F47_P_2 */
9661   {
9662     { Bad_Opcode },
9663     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9664   },
9665   /* VEX_LEN_0F4A_P_0 */
9666   {
9667     { Bad_Opcode },
9668     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9669   },
9670   /* VEX_LEN_0F4A_P_2 */
9671   {
9672     { Bad_Opcode },
9673     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9674   },
9675   /* VEX_LEN_0F4B_P_0 */
9676   {
9677     { Bad_Opcode },
9678     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9679   },
9680   /* VEX_LEN_0F4B_P_2 */
9681   {
9682     { Bad_Opcode },
9683     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9684   },
9685
9686   /* VEX_LEN_0F51_P_1 */
9687   {
9688     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9689     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9690   },
9691
9692   /* VEX_LEN_0F51_P_3 */
9693   {
9694     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9695     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9696   },
9697
9698   /* VEX_LEN_0F52_P_1 */
9699   {
9700     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9701     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9702   },
9703
9704   /* VEX_LEN_0F53_P_1 */
9705   {
9706     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9707     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9708   },
9709
9710   /* VEX_LEN_0F58_P_1 */
9711   {
9712     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9713     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9714   },
9715
9716   /* VEX_LEN_0F58_P_3 */
9717   {
9718     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9719     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9720   },
9721
9722   /* VEX_LEN_0F59_P_1 */
9723   {
9724     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9725     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9726   },
9727
9728   /* VEX_LEN_0F59_P_3 */
9729   {
9730     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9731     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9732   },
9733
9734   /* VEX_LEN_0F5A_P_1 */
9735   {
9736     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9737     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9738   },
9739
9740   /* VEX_LEN_0F5A_P_3 */
9741   {
9742     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9743     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9744   },
9745
9746   /* VEX_LEN_0F5C_P_1 */
9747   {
9748     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9749     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9750   },
9751
9752   /* VEX_LEN_0F5C_P_3 */
9753   {
9754     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9755     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9756   },
9757
9758   /* VEX_LEN_0F5D_P_1 */
9759   {
9760     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9761     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9762   },
9763
9764   /* VEX_LEN_0F5D_P_3 */
9765   {
9766     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9767     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9768   },
9769
9770   /* VEX_LEN_0F5E_P_1 */
9771   {
9772     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9773     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9774   },
9775
9776   /* VEX_LEN_0F5E_P_3 */
9777   {
9778     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9779     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9780   },
9781
9782   /* VEX_LEN_0F5F_P_1 */
9783   {
9784     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9785     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9786   },
9787
9788   /* VEX_LEN_0F5F_P_3 */
9789   {
9790     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9791     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9792   },
9793
9794   /* VEX_LEN_0F6E_P_2 */
9795   {
9796     { "vmovK",          { XMScalar, Edq }, 0 },
9797     { "vmovK",          { XMScalar, Edq }, 0 },
9798   },
9799
9800   /* VEX_LEN_0F7E_P_1 */
9801   {
9802     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9803     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9804   },
9805
9806   /* VEX_LEN_0F7E_P_2 */
9807   {
9808     { "vmovK",          { Edq, XMScalar }, 0 },
9809     { "vmovK",          { Edq, XMScalar }, 0 },
9810   },
9811
9812   /* VEX_LEN_0F90_P_0 */
9813   {
9814     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9815   },
9816
9817   /* VEX_LEN_0F90_P_2 */
9818   {
9819     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9820   },
9821
9822   /* VEX_LEN_0F91_P_0 */
9823   {
9824     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9825   },
9826
9827   /* VEX_LEN_0F91_P_2 */
9828   {
9829     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9830   },
9831
9832   /* VEX_LEN_0F92_P_0 */
9833   {
9834     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9835   },
9836
9837   /* VEX_LEN_0F92_P_2 */
9838   {
9839     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9840   },
9841
9842   /* VEX_LEN_0F92_P_3 */
9843   {
9844     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9845   },
9846
9847   /* VEX_LEN_0F93_P_0 */
9848   {
9849     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9850   },
9851
9852   /* VEX_LEN_0F93_P_2 */
9853   {
9854     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9855   },
9856
9857   /* VEX_LEN_0F93_P_3 */
9858   {
9859     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9860   },
9861
9862   /* VEX_LEN_0F98_P_0 */
9863   {
9864     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9865   },
9866
9867   /* VEX_LEN_0F98_P_2 */
9868   {
9869     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9870   },
9871
9872   /* VEX_LEN_0F99_P_0 */
9873   {
9874     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9875   },
9876
9877   /* VEX_LEN_0F99_P_2 */
9878   {
9879     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9880   },
9881
9882   /* VEX_LEN_0FAE_R_2_M_0 */
9883   {
9884     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9885   },
9886
9887   /* VEX_LEN_0FAE_R_3_M_0 */
9888   {
9889     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9890   },
9891
9892   /* VEX_LEN_0FC2_P_1 */
9893   {
9894     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9895     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9896   },
9897
9898   /* VEX_LEN_0FC2_P_3 */
9899   {
9900     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9901     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9902   },
9903
9904   /* VEX_LEN_0FC4_P_2 */
9905   {
9906     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9907   },
9908
9909   /* VEX_LEN_0FC5_P_2 */
9910   {
9911     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9912   },
9913
9914   /* VEX_LEN_0FD6_P_2 */
9915   {
9916     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9917     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9918   },
9919
9920   /* VEX_LEN_0FF7_P_2 */
9921   {
9922     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9923   },
9924
9925   /* VEX_LEN_0F3816_P_2 */
9926   {
9927     { Bad_Opcode },
9928     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9929   },
9930
9931   /* VEX_LEN_0F3819_P_2 */
9932   {
9933     { Bad_Opcode },
9934     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9935   },
9936
9937   /* VEX_LEN_0F381A_P_2_M_0 */
9938   {
9939     { Bad_Opcode },
9940     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9941   },
9942
9943   /* VEX_LEN_0F3836_P_2 */
9944   {
9945     { Bad_Opcode },
9946     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9947   },
9948
9949   /* VEX_LEN_0F3841_P_2 */
9950   {
9951     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9952   },
9953
9954   /* VEX_LEN_0F385A_P_2_M_0 */
9955   {
9956     { Bad_Opcode },
9957     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9958   },
9959
9960   /* VEX_LEN_0F38DB_P_2 */
9961   {
9962     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9963   },
9964
9965   /* VEX_LEN_0F38DC_P_2 */
9966   {
9967     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9968   },
9969
9970   /* VEX_LEN_0F38DD_P_2 */
9971   {
9972     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9973   },
9974
9975   /* VEX_LEN_0F38DE_P_2 */
9976   {
9977     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9978   },
9979
9980   /* VEX_LEN_0F38DF_P_2 */
9981   {
9982     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9983   },
9984
9985   /* VEX_LEN_0F38F2_P_0 */
9986   {
9987     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9988   },
9989
9990   /* VEX_LEN_0F38F3_R_1_P_0 */
9991   {
9992     { "blsrS",          { VexGdq, Edq }, 0 },
9993   },
9994
9995   /* VEX_LEN_0F38F3_R_2_P_0 */
9996   {
9997     { "blsmskS",        { VexGdq, Edq }, 0 },
9998   },
9999
10000   /* VEX_LEN_0F38F3_R_3_P_0 */
10001   {
10002     { "blsiS",          { VexGdq, Edq }, 0 },
10003   },
10004
10005   /* VEX_LEN_0F38F5_P_0 */
10006   {
10007     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
10008   },
10009
10010   /* VEX_LEN_0F38F5_P_1 */
10011   {
10012     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
10013   },
10014
10015   /* VEX_LEN_0F38F5_P_3 */
10016   {
10017     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
10018   },
10019
10020   /* VEX_LEN_0F38F6_P_3 */
10021   {
10022     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
10023   },
10024
10025   /* VEX_LEN_0F38F7_P_0 */
10026   {
10027     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
10028   },
10029
10030   /* VEX_LEN_0F38F7_P_1 */
10031   {
10032     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10033   },
10034
10035   /* VEX_LEN_0F38F7_P_2 */
10036   {
10037     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10038   },
10039
10040   /* VEX_LEN_0F38F7_P_3 */
10041   {
10042     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10043   },
10044
10045   /* VEX_LEN_0F3A00_P_2 */
10046   {
10047     { Bad_Opcode },
10048     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10049   },
10050
10051   /* VEX_LEN_0F3A01_P_2 */
10052   {
10053     { Bad_Opcode },
10054     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10055   },
10056
10057   /* VEX_LEN_0F3A06_P_2 */
10058   {
10059     { Bad_Opcode },
10060     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10061   },
10062
10063   /* VEX_LEN_0F3A0A_P_2 */
10064   {
10065     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10066     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10067   },
10068
10069   /* VEX_LEN_0F3A0B_P_2 */
10070   {
10071     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10072     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10073   },
10074
10075   /* VEX_LEN_0F3A14_P_2 */
10076   {
10077     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10078   },
10079
10080   /* VEX_LEN_0F3A15_P_2 */
10081   {
10082     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10083   },
10084
10085   /* VEX_LEN_0F3A16_P_2  */
10086   {
10087     { "vpextrK",        { Edq, XM, Ib }, 0 },
10088   },
10089
10090   /* VEX_LEN_0F3A17_P_2 */
10091   {
10092     { "vextractps",     { Edqd, XM, Ib }, 0 },
10093   },
10094
10095   /* VEX_LEN_0F3A18_P_2 */
10096   {
10097     { Bad_Opcode },
10098     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10099   },
10100
10101   /* VEX_LEN_0F3A19_P_2 */
10102   {
10103     { Bad_Opcode },
10104     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10105   },
10106
10107   /* VEX_LEN_0F3A20_P_2 */
10108   {
10109     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10110   },
10111
10112   /* VEX_LEN_0F3A21_P_2 */
10113   {
10114     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10115   },
10116
10117   /* VEX_LEN_0F3A22_P_2 */
10118   {
10119     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10120   },
10121
10122   /* VEX_LEN_0F3A30_P_2 */
10123   {
10124     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10125   },
10126
10127   /* VEX_LEN_0F3A31_P_2 */
10128   {
10129     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10130   },
10131
10132   /* VEX_LEN_0F3A32_P_2 */
10133   {
10134     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10135   },
10136
10137   /* VEX_LEN_0F3A33_P_2 */
10138   {
10139     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10140   },
10141
10142   /* VEX_LEN_0F3A38_P_2 */
10143   {
10144     { Bad_Opcode },
10145     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10146   },
10147
10148   /* VEX_LEN_0F3A39_P_2 */
10149   {
10150     { Bad_Opcode },
10151     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10152   },
10153
10154   /* VEX_LEN_0F3A41_P_2 */
10155   {
10156     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10157   },
10158
10159   /* VEX_LEN_0F3A44_P_2 */
10160   {
10161     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10162   },
10163
10164   /* VEX_LEN_0F3A46_P_2 */
10165   {
10166     { Bad_Opcode },
10167     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10168   },
10169
10170   /* VEX_LEN_0F3A60_P_2 */
10171   {
10172     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10173   },
10174
10175   /* VEX_LEN_0F3A61_P_2 */
10176   {
10177     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10178   },
10179
10180   /* VEX_LEN_0F3A62_P_2 */
10181   {
10182     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10183   },
10184
10185   /* VEX_LEN_0F3A63_P_2 */
10186   {
10187     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10188   },
10189
10190   /* VEX_LEN_0F3A6A_P_2 */
10191   {
10192     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10193   },
10194
10195   /* VEX_LEN_0F3A6B_P_2 */
10196   {
10197     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10198   },
10199
10200   /* VEX_LEN_0F3A6E_P_2 */
10201   {
10202     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10203   },
10204
10205   /* VEX_LEN_0F3A6F_P_2 */
10206   {
10207     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10208   },
10209
10210   /* VEX_LEN_0F3A7A_P_2 */
10211   {
10212     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10213   },
10214
10215   /* VEX_LEN_0F3A7B_P_2 */
10216   {
10217     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10218   },
10219
10220   /* VEX_LEN_0F3A7E_P_2 */
10221   {
10222     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10223   },
10224
10225   /* VEX_LEN_0F3A7F_P_2 */
10226   {
10227     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10228   },
10229
10230   /* VEX_LEN_0F3ADF_P_2 */
10231   {
10232     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10233   },
10234
10235   /* VEX_LEN_0F3AF0_P_3 */
10236   {
10237     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10238   },
10239
10240   /* VEX_LEN_0FXOP_08_CC */
10241   {
10242      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10243   },
10244
10245   /* VEX_LEN_0FXOP_08_CD */
10246   {
10247      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10248   },
10249
10250   /* VEX_LEN_0FXOP_08_CE */
10251   {
10252      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10253   },
10254
10255   /* VEX_LEN_0FXOP_08_CF */
10256   {
10257      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10258   },
10259
10260   /* VEX_LEN_0FXOP_08_EC */
10261   {
10262      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10263   },
10264
10265   /* VEX_LEN_0FXOP_08_ED */
10266   {
10267      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10268   },
10269
10270   /* VEX_LEN_0FXOP_08_EE */
10271   {
10272      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10273   },
10274
10275   /* VEX_LEN_0FXOP_08_EF */
10276   {
10277      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10278   },
10279
10280   /* VEX_LEN_0FXOP_09_80 */
10281   {
10282     { "vfrczps",        { XM, EXxmm }, 0 },
10283     { "vfrczps",        { XM, EXymmq }, 0 },
10284   },
10285
10286   /* VEX_LEN_0FXOP_09_81 */
10287   {
10288     { "vfrczpd",        { XM, EXxmm }, 0 },
10289     { "vfrczpd",        { XM, EXymmq }, 0 },
10290   },
10291 };
10292
10293 static const struct dis386 vex_w_table[][2] = {
10294   {
10295     /* VEX_W_0F10_P_0 */
10296     { "vmovups",        { XM, EXx }, 0 },
10297   },
10298   {
10299     /* VEX_W_0F10_P_1 */
10300     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10301   },
10302   {
10303     /* VEX_W_0F10_P_2 */
10304     { "vmovupd",        { XM, EXx }, 0 },
10305   },
10306   {
10307     /* VEX_W_0F10_P_3 */
10308     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10309   },
10310   {
10311     /* VEX_W_0F11_P_0 */
10312     { "vmovups",        { EXxS, XM }, 0 },
10313   },
10314   {
10315     /* VEX_W_0F11_P_1 */
10316     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10317   },
10318   {
10319     /* VEX_W_0F11_P_2 */
10320     { "vmovupd",        { EXxS, XM }, 0 },
10321   },
10322   {
10323     /* VEX_W_0F11_P_3 */
10324     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10325   },
10326   {
10327     /* VEX_W_0F12_P_0_M_0 */
10328     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10329   },
10330   {
10331     /* VEX_W_0F12_P_0_M_1 */
10332     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10333   },
10334   {
10335     /* VEX_W_0F12_P_1 */
10336     { "vmovsldup",      { XM, EXx }, 0 },
10337   },
10338   {
10339     /* VEX_W_0F12_P_2 */
10340     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10341   },
10342   {
10343     /* VEX_W_0F12_P_3 */
10344     { "vmovddup",       { XM, EXymmq }, 0 },
10345   },
10346   {
10347     /* VEX_W_0F13_M_0 */
10348     { "vmovlpX",        { EXq, XM }, 0 },
10349   },
10350   {
10351     /* VEX_W_0F14 */
10352     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10353   },
10354   {
10355     /* VEX_W_0F15 */
10356     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10357   },
10358   {
10359     /* VEX_W_0F16_P_0_M_0 */
10360     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10361   },
10362   {
10363     /* VEX_W_0F16_P_0_M_1 */
10364     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10365   },
10366   {
10367     /* VEX_W_0F16_P_1 */
10368     { "vmovshdup",      { XM, EXx }, 0 },
10369   },
10370   {
10371     /* VEX_W_0F16_P_2 */
10372     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10373   },
10374   {
10375     /* VEX_W_0F17_M_0 */
10376     { "vmovhpX",        { EXq, XM }, 0 },
10377   },
10378   {
10379     /* VEX_W_0F28 */
10380     { "vmovapX",        { XM, EXx }, 0 },
10381   },
10382   {
10383     /* VEX_W_0F29 */
10384     { "vmovapX",        { EXxS, XM }, 0 },
10385   },
10386   {
10387     /* VEX_W_0F2B_M_0 */
10388     { "vmovntpX",       { Mx, XM }, 0 },
10389   },
10390   {
10391     /* VEX_W_0F2E_P_0 */
10392     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10393   },
10394   {
10395     /* VEX_W_0F2E_P_2 */
10396     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10397   },
10398   {
10399     /* VEX_W_0F2F_P_0 */
10400     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10401   },
10402   {
10403     /* VEX_W_0F2F_P_2 */
10404     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10405   },
10406   {
10407     /* VEX_W_0F41_P_0_LEN_1 */
10408     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10409     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10410   },
10411   {
10412     /* VEX_W_0F41_P_2_LEN_1 */
10413     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10414     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10415   },
10416   {
10417     /* VEX_W_0F42_P_0_LEN_1 */
10418     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10419     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10420   },
10421   {
10422     /* VEX_W_0F42_P_2_LEN_1 */
10423     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10424     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10425   },
10426   {
10427     /* VEX_W_0F44_P_0_LEN_0 */
10428     { "knotw",          { MaskG, MaskR }, 0 },
10429     { "knotq",          { MaskG, MaskR }, 0 },
10430   },
10431   {
10432     /* VEX_W_0F44_P_2_LEN_0 */
10433     { "knotb",          { MaskG, MaskR }, 0 },
10434     { "knotd",          { MaskG, MaskR }, 0 },
10435   },
10436   {
10437     /* VEX_W_0F45_P_0_LEN_1 */
10438     { "korw",           { MaskG, MaskVex, MaskR }, 0 },
10439     { "korq",           { MaskG, MaskVex, MaskR }, 0 },
10440   },
10441   {
10442     /* VEX_W_0F45_P_2_LEN_1 */
10443     { "korb",           { MaskG, MaskVex, MaskR }, 0 },
10444     { "kord",           { MaskG, MaskVex, MaskR }, 0 },
10445   },
10446   {
10447     /* VEX_W_0F46_P_0_LEN_1 */
10448     { "kxnorw",         { MaskG, MaskVex, MaskR }, 0 },
10449     { "kxnorq",         { MaskG, MaskVex, MaskR }, 0 },
10450   },
10451   {
10452     /* VEX_W_0F46_P_2_LEN_1 */
10453     { "kxnorb",         { MaskG, MaskVex, MaskR }, 0 },
10454     { "kxnord",         { MaskG, MaskVex, MaskR }, 0 },
10455   },
10456   {
10457     /* VEX_W_0F47_P_0_LEN_1 */
10458     { "kxorw",          { MaskG, MaskVex, MaskR }, 0 },
10459     { "kxorq",          { MaskG, MaskVex, MaskR }, 0 },
10460   },
10461   {
10462     /* VEX_W_0F47_P_2_LEN_1 */
10463     { "kxorb",          { MaskG, MaskVex, MaskR }, 0 },
10464     { "kxord",          { MaskG, MaskVex, MaskR }, 0 },
10465   },
10466   {
10467     /* VEX_W_0F4A_P_0_LEN_1 */
10468     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10469     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10470   },
10471   {
10472     /* VEX_W_0F4A_P_2_LEN_1 */
10473     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10474     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10475   },
10476   {
10477     /* VEX_W_0F4B_P_0_LEN_1 */
10478     { "kunpckwd",       { MaskG, MaskVex, MaskR }, 0 },
10479     { "kunpckdq",       { MaskG, MaskVex, MaskR }, 0 },
10480   },
10481   {
10482     /* VEX_W_0F4B_P_2_LEN_1 */
10483     { "kunpckbw",       { MaskG, MaskVex, MaskR }, 0 },
10484   },
10485   {
10486     /* VEX_W_0F50_M_0 */
10487     { "vmovmskpX",      { Gdq, XS }, 0 },
10488   },
10489   {
10490     /* VEX_W_0F51_P_0 */
10491     { "vsqrtps",        { XM, EXx }, 0 },
10492   },
10493   {
10494     /* VEX_W_0F51_P_1 */
10495     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10496   },
10497   {
10498     /* VEX_W_0F51_P_2  */
10499     { "vsqrtpd",        { XM, EXx }, 0 },
10500   },
10501   {
10502     /* VEX_W_0F51_P_3 */
10503     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10504   },
10505   {
10506     /* VEX_W_0F52_P_0 */
10507     { "vrsqrtps",       { XM, EXx }, 0 },
10508   },
10509   {
10510     /* VEX_W_0F52_P_1 */
10511     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10512   },
10513   {
10514     /* VEX_W_0F53_P_0  */
10515     { "vrcpps",         { XM, EXx }, 0 },
10516   },
10517   {
10518     /* VEX_W_0F53_P_1  */
10519     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10520   },
10521   {
10522     /* VEX_W_0F58_P_0  */
10523     { "vaddps",         { XM, Vex, EXx }, 0 },
10524   },
10525   {
10526     /* VEX_W_0F58_P_1  */
10527     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10528   },
10529   {
10530     /* VEX_W_0F58_P_2  */
10531     { "vaddpd",         { XM, Vex, EXx }, 0 },
10532   },
10533   {
10534     /* VEX_W_0F58_P_3  */
10535     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10536   },
10537   {
10538     /* VEX_W_0F59_P_0  */
10539     { "vmulps",         { XM, Vex, EXx }, 0 },
10540   },
10541   {
10542     /* VEX_W_0F59_P_1  */
10543     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10544   },
10545   {
10546     /* VEX_W_0F59_P_2  */
10547     { "vmulpd",         { XM, Vex, EXx }, 0 },
10548   },
10549   {
10550     /* VEX_W_0F59_P_3  */
10551     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10552   },
10553   {
10554     /* VEX_W_0F5A_P_0  */
10555     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10556   },
10557   {
10558     /* VEX_W_0F5A_P_1  */
10559     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10560   },
10561   {
10562     /* VEX_W_0F5A_P_3  */
10563     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10564   },
10565   {
10566     /* VEX_W_0F5B_P_0  */
10567     { "vcvtdq2ps",      { XM, EXx }, 0 },
10568   },
10569   {
10570     /* VEX_W_0F5B_P_1  */
10571     { "vcvttps2dq",     { XM, EXx }, 0 },
10572   },
10573   {
10574     /* VEX_W_0F5B_P_2  */
10575     { "vcvtps2dq",      { XM, EXx }, 0 },
10576   },
10577   {
10578     /* VEX_W_0F5C_P_0  */
10579     { "vsubps",         { XM, Vex, EXx }, 0 },
10580   },
10581   {
10582     /* VEX_W_0F5C_P_1  */
10583     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10584   },
10585   {
10586     /* VEX_W_0F5C_P_2  */
10587     { "vsubpd",         { XM, Vex, EXx }, 0 },
10588   },
10589   {
10590     /* VEX_W_0F5C_P_3  */
10591     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10592   },
10593   {
10594     /* VEX_W_0F5D_P_0  */
10595     { "vminps",         { XM, Vex, EXx }, 0 },
10596   },
10597   {
10598     /* VEX_W_0F5D_P_1  */
10599     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10600   },
10601   {
10602     /* VEX_W_0F5D_P_2  */
10603     { "vminpd",         { XM, Vex, EXx }, 0 },
10604   },
10605   {
10606     /* VEX_W_0F5D_P_3  */
10607     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10608   },
10609   {
10610     /* VEX_W_0F5E_P_0  */
10611     { "vdivps",         { XM, Vex, EXx }, 0 },
10612   },
10613   {
10614     /* VEX_W_0F5E_P_1  */
10615     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10616   },
10617   {
10618     /* VEX_W_0F5E_P_2  */
10619     { "vdivpd",         { XM, Vex, EXx }, 0 },
10620   },
10621   {
10622     /* VEX_W_0F5E_P_3  */
10623     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10624   },
10625   {
10626     /* VEX_W_0F5F_P_0  */
10627     { "vmaxps",         { XM, Vex, EXx }, 0 },
10628   },
10629   {
10630     /* VEX_W_0F5F_P_1  */
10631     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10632   },
10633   {
10634     /* VEX_W_0F5F_P_2  */
10635     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10636   },
10637   {
10638     /* VEX_W_0F5F_P_3  */
10639     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10640   },
10641   {
10642     /* VEX_W_0F60_P_2  */
10643     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10644   },
10645   {
10646     /* VEX_W_0F61_P_2  */
10647     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10648   },
10649   {
10650     /* VEX_W_0F62_P_2  */
10651     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10652   },
10653   {
10654     /* VEX_W_0F63_P_2  */
10655     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10656   },
10657   {
10658     /* VEX_W_0F64_P_2  */
10659     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10660   },
10661   {
10662     /* VEX_W_0F65_P_2  */
10663     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10664   },
10665   {
10666     /* VEX_W_0F66_P_2  */
10667     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10668   },
10669   {
10670     /* VEX_W_0F67_P_2  */
10671     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10672   },
10673   {
10674     /* VEX_W_0F68_P_2  */
10675     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10676   },
10677   {
10678     /* VEX_W_0F69_P_2  */
10679     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10680   },
10681   {
10682     /* VEX_W_0F6A_P_2  */
10683     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10684   },
10685   {
10686     /* VEX_W_0F6B_P_2  */
10687     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10688   },
10689   {
10690     /* VEX_W_0F6C_P_2  */
10691     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10692   },
10693   {
10694     /* VEX_W_0F6D_P_2  */
10695     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10696   },
10697   {
10698     /* VEX_W_0F6F_P_1  */
10699     { "vmovdqu",        { XM, EXx }, 0 },
10700   },
10701   {
10702     /* VEX_W_0F6F_P_2  */
10703     { "vmovdqa",        { XM, EXx }, 0 },
10704   },
10705   {
10706     /* VEX_W_0F70_P_1 */
10707     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10708   },
10709   {
10710     /* VEX_W_0F70_P_2 */
10711     { "vpshufd",        { XM, EXx, Ib }, 0 },
10712   },
10713   {
10714     /* VEX_W_0F70_P_3 */
10715     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10716   },
10717   {
10718     /* VEX_W_0F71_R_2_P_2  */
10719     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10720   },
10721   {
10722     /* VEX_W_0F71_R_4_P_2  */
10723     { "vpsraw",         { Vex, XS, Ib }, 0 },
10724   },
10725   {
10726     /* VEX_W_0F71_R_6_P_2  */
10727     { "vpsllw",         { Vex, XS, Ib }, 0 },
10728   },
10729   {
10730     /* VEX_W_0F72_R_2_P_2  */
10731     { "vpsrld",         { Vex, XS, Ib }, 0 },
10732   },
10733   {
10734     /* VEX_W_0F72_R_4_P_2  */
10735     { "vpsrad",         { Vex, XS, Ib }, 0 },
10736   },
10737   {
10738     /* VEX_W_0F72_R_6_P_2  */
10739     { "vpslld",         { Vex, XS, Ib }, 0 },
10740   },
10741   {
10742     /* VEX_W_0F73_R_2_P_2  */
10743     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10744   },
10745   {
10746     /* VEX_W_0F73_R_3_P_2  */
10747     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10748   },
10749   {
10750     /* VEX_W_0F73_R_6_P_2  */
10751     { "vpsllq",         { Vex, XS, Ib }, 0 },
10752   },
10753   {
10754     /* VEX_W_0F73_R_7_P_2  */
10755     { "vpslldq",        { Vex, XS, Ib }, 0 },
10756   },
10757   {
10758     /* VEX_W_0F74_P_2 */
10759     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10760   },
10761   {
10762     /* VEX_W_0F75_P_2 */
10763     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10764   },
10765   {
10766     /* VEX_W_0F76_P_2 */
10767     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10768   },
10769   {
10770     /* VEX_W_0F77_P_0 */
10771     { "",               { VZERO }, 0 },
10772   },
10773   {
10774     /* VEX_W_0F7C_P_2 */
10775     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10776   },
10777   {
10778     /* VEX_W_0F7C_P_3 */
10779     { "vhaddps",        { XM, Vex, EXx }, 0 },
10780   },
10781   {
10782     /* VEX_W_0F7D_P_2 */
10783     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10784   },
10785   {
10786     /* VEX_W_0F7D_P_3 */
10787     { "vhsubps",        { XM, Vex, EXx }, 0 },
10788   },
10789   {
10790     /* VEX_W_0F7E_P_1 */
10791     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10792   },
10793   {
10794     /* VEX_W_0F7F_P_1 */
10795     { "vmovdqu",        { EXxS, XM }, 0 },
10796   },
10797   {
10798     /* VEX_W_0F7F_P_2 */
10799     { "vmovdqa",        { EXxS, XM }, 0 },
10800   },
10801   {
10802     /* VEX_W_0F90_P_0_LEN_0 */
10803     { "kmovw",          { MaskG, MaskE }, 0 },
10804     { "kmovq",          { MaskG, MaskE }, 0 },
10805   },
10806   {
10807     /* VEX_W_0F90_P_2_LEN_0 */
10808     { "kmovb",          { MaskG, MaskBDE }, 0 },
10809     { "kmovd",          { MaskG, MaskBDE }, 0 },
10810   },
10811   {
10812     /* VEX_W_0F91_P_0_LEN_0 */
10813     { "kmovw",          { Ew, MaskG }, 0 },
10814     { "kmovq",          { Eq, MaskG }, 0 },
10815   },
10816   {
10817     /* VEX_W_0F91_P_2_LEN_0 */
10818     { "kmovb",          { Eb, MaskG }, 0 },
10819     { "kmovd",          { Ed, MaskG }, 0 },
10820   },
10821   {
10822     /* VEX_W_0F92_P_0_LEN_0 */
10823     { "kmovw",          { MaskG, Rdq }, 0 },
10824   },
10825   {
10826     /* VEX_W_0F92_P_2_LEN_0 */
10827     { "kmovb",          { MaskG, Rdq }, 0 },
10828   },
10829   {
10830     /* VEX_W_0F92_P_3_LEN_0 */
10831     { "kmovd",          { MaskG, Rdq }, 0 },
10832     { "kmovq",          { MaskG, Rdq }, 0 },
10833   },
10834   {
10835     /* VEX_W_0F93_P_0_LEN_0 */
10836     { "kmovw",          { Gdq, MaskR }, 0 },
10837   },
10838   {
10839     /* VEX_W_0F93_P_2_LEN_0 */
10840     { "kmovb",          { Gdq, MaskR }, 0 },
10841   },
10842   {
10843     /* VEX_W_0F93_P_3_LEN_0 */
10844     { "kmovd",          { Gdq, MaskR }, 0 },
10845     { "kmovq",          { Gdq, MaskR }, 0 },
10846   },
10847   {
10848     /* VEX_W_0F98_P_0_LEN_0 */
10849     { "kortestw",       { MaskG, MaskR }, 0 },
10850     { "kortestq",       { MaskG, MaskR }, 0 },
10851   },
10852   {
10853     /* VEX_W_0F98_P_2_LEN_0 */
10854     { "kortestb",       { MaskG, MaskR }, 0 },
10855     { "kortestd",       { MaskG, MaskR }, 0 },
10856   },
10857   {
10858     /* VEX_W_0F99_P_0_LEN_0 */
10859     { "ktestw", { MaskG, MaskR }, 0 },
10860     { "ktestq", { MaskG, MaskR }, 0 },
10861   },
10862   {
10863     /* VEX_W_0F99_P_2_LEN_0 */
10864     { "ktestb", { MaskG, MaskR }, 0 },
10865     { "ktestd", { MaskG, MaskR }, 0 },
10866   },
10867   {
10868     /* VEX_W_0FAE_R_2_M_0 */
10869     { "vldmxcsr",       { Md }, 0 },
10870   },
10871   {
10872     /* VEX_W_0FAE_R_3_M_0 */
10873     { "vstmxcsr",       { Md }, 0 },
10874   },
10875   {
10876     /* VEX_W_0FC2_P_0 */
10877     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10878   },
10879   {
10880     /* VEX_W_0FC2_P_1 */
10881     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10882   },
10883   {
10884     /* VEX_W_0FC2_P_2 */
10885     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10886   },
10887   {
10888     /* VEX_W_0FC2_P_3 */
10889     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10890   },
10891   {
10892     /* VEX_W_0FC4_P_2 */
10893     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10894   },
10895   {
10896     /* VEX_W_0FC5_P_2 */
10897     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10898   },
10899   {
10900     /* VEX_W_0FD0_P_2 */
10901     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10902   },
10903   {
10904     /* VEX_W_0FD0_P_3 */
10905     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10906   },
10907   {
10908     /* VEX_W_0FD1_P_2 */
10909     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10910   },
10911   {
10912     /* VEX_W_0FD2_P_2 */
10913     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10914   },
10915   {
10916     /* VEX_W_0FD3_P_2 */
10917     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10918   },
10919   {
10920     /* VEX_W_0FD4_P_2 */
10921     { "vpaddq",         { XM, Vex, EXx }, 0 },
10922   },
10923   {
10924     /* VEX_W_0FD5_P_2 */
10925     { "vpmullw",        { XM, Vex, EXx }, 0 },
10926   },
10927   {
10928     /* VEX_W_0FD6_P_2 */
10929     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10930   },
10931   {
10932     /* VEX_W_0FD7_P_2_M_1 */
10933     { "vpmovmskb",      { Gdq, XS }, 0 },
10934   },
10935   {
10936     /* VEX_W_0FD8_P_2 */
10937     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10938   },
10939   {
10940     /* VEX_W_0FD9_P_2 */
10941     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10942   },
10943   {
10944     /* VEX_W_0FDA_P_2 */
10945     { "vpminub",        { XM, Vex, EXx }, 0 },
10946   },
10947   {
10948     /* VEX_W_0FDB_P_2 */
10949     { "vpand",          { XM, Vex, EXx }, 0 },
10950   },
10951   {
10952     /* VEX_W_0FDC_P_2 */
10953     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10954   },
10955   {
10956     /* VEX_W_0FDD_P_2 */
10957     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10958   },
10959   {
10960     /* VEX_W_0FDE_P_2 */
10961     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10962   },
10963   {
10964     /* VEX_W_0FDF_P_2 */
10965     { "vpandn",         { XM, Vex, EXx }, 0 },
10966   },
10967   {
10968     /* VEX_W_0FE0_P_2  */
10969     { "vpavgb",         { XM, Vex, EXx }, 0 },
10970   },
10971   {
10972     /* VEX_W_0FE1_P_2  */
10973     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10974   },
10975   {
10976     /* VEX_W_0FE2_P_2  */
10977     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10978   },
10979   {
10980     /* VEX_W_0FE3_P_2  */
10981     { "vpavgw",         { XM, Vex, EXx }, 0 },
10982   },
10983   {
10984     /* VEX_W_0FE4_P_2  */
10985     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
10986   },
10987   {
10988     /* VEX_W_0FE5_P_2  */
10989     { "vpmulhw",        { XM, Vex, EXx }, 0 },
10990   },
10991   {
10992     /* VEX_W_0FE6_P_1  */
10993     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
10994   },
10995   {
10996     /* VEX_W_0FE6_P_2  */
10997     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
10998   },
10999   {
11000     /* VEX_W_0FE6_P_3  */
11001     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
11002   },
11003   {
11004     /* VEX_W_0FE7_P_2_M_0 */
11005     { "vmovntdq",       { Mx, XM }, 0 },
11006   },
11007   {
11008     /* VEX_W_0FE8_P_2  */
11009     { "vpsubsb",        { XM, Vex, EXx }, 0 },
11010   },
11011   {
11012     /* VEX_W_0FE9_P_2  */
11013     { "vpsubsw",        { XM, Vex, EXx }, 0 },
11014   },
11015   {
11016     /* VEX_W_0FEA_P_2  */
11017     { "vpminsw",        { XM, Vex, EXx }, 0 },
11018   },
11019   {
11020     /* VEX_W_0FEB_P_2  */
11021     { "vpor",           { XM, Vex, EXx }, 0 },
11022   },
11023   {
11024     /* VEX_W_0FEC_P_2  */
11025     { "vpaddsb",        { XM, Vex, EXx }, 0 },
11026   },
11027   {
11028     /* VEX_W_0FED_P_2  */
11029     { "vpaddsw",        { XM, Vex, EXx }, 0 },
11030   },
11031   {
11032     /* VEX_W_0FEE_P_2  */
11033     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
11034   },
11035   {
11036     /* VEX_W_0FEF_P_2  */
11037     { "vpxor",          { XM, Vex, EXx }, 0 },
11038   },
11039   {
11040     /* VEX_W_0FF0_P_3_M_0 */
11041     { "vlddqu",         { XM, M }, 0 },
11042   },
11043   {
11044     /* VEX_W_0FF1_P_2 */
11045     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11046   },
11047   {
11048     /* VEX_W_0FF2_P_2 */
11049     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11050   },
11051   {
11052     /* VEX_W_0FF3_P_2 */
11053     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11054   },
11055   {
11056     /* VEX_W_0FF4_P_2 */
11057     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11058   },
11059   {
11060     /* VEX_W_0FF5_P_2 */
11061     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11062   },
11063   {
11064     /* VEX_W_0FF6_P_2 */
11065     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11066   },
11067   {
11068     /* VEX_W_0FF7_P_2 */
11069     { "vmaskmovdqu",    { XM, XS }, 0 },
11070   },
11071   {
11072     /* VEX_W_0FF8_P_2 */
11073     { "vpsubb",         { XM, Vex, EXx }, 0 },
11074   },
11075   {
11076     /* VEX_W_0FF9_P_2 */
11077     { "vpsubw",         { XM, Vex, EXx }, 0 },
11078   },
11079   {
11080     /* VEX_W_0FFA_P_2 */
11081     { "vpsubd",         { XM, Vex, EXx }, 0 },
11082   },
11083   {
11084     /* VEX_W_0FFB_P_2 */
11085     { "vpsubq",         { XM, Vex, EXx }, 0 },
11086   },
11087   {
11088     /* VEX_W_0FFC_P_2 */
11089     { "vpaddb",         { XM, Vex, EXx }, 0 },
11090   },
11091   {
11092     /* VEX_W_0FFD_P_2 */
11093     { "vpaddw",         { XM, Vex, EXx }, 0 },
11094   },
11095   {
11096     /* VEX_W_0FFE_P_2 */
11097     { "vpaddd",         { XM, Vex, EXx }, 0 },
11098   },
11099   {
11100     /* VEX_W_0F3800_P_2  */
11101     { "vpshufb",        { XM, Vex, EXx }, 0 },
11102   },
11103   {
11104     /* VEX_W_0F3801_P_2  */
11105     { "vphaddw",        { XM, Vex, EXx }, 0 },
11106   },
11107   {
11108     /* VEX_W_0F3802_P_2  */
11109     { "vphaddd",        { XM, Vex, EXx }, 0 },
11110   },
11111   {
11112     /* VEX_W_0F3803_P_2  */
11113     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11114   },
11115   {
11116     /* VEX_W_0F3804_P_2  */
11117     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11118   },
11119   {
11120     /* VEX_W_0F3805_P_2  */
11121     { "vphsubw",        { XM, Vex, EXx }, 0 },
11122   },
11123   {
11124     /* VEX_W_0F3806_P_2  */
11125     { "vphsubd",        { XM, Vex, EXx }, 0 },
11126   },
11127   {
11128     /* VEX_W_0F3807_P_2  */
11129     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11130   },
11131   {
11132     /* VEX_W_0F3808_P_2  */
11133     { "vpsignb",        { XM, Vex, EXx }, 0 },
11134   },
11135   {
11136     /* VEX_W_0F3809_P_2  */
11137     { "vpsignw",        { XM, Vex, EXx }, 0 },
11138   },
11139   {
11140     /* VEX_W_0F380A_P_2  */
11141     { "vpsignd",        { XM, Vex, EXx }, 0 },
11142   },
11143   {
11144     /* VEX_W_0F380B_P_2  */
11145     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11146   },
11147   {
11148     /* VEX_W_0F380C_P_2  */
11149     { "vpermilps",      { XM, Vex, EXx }, 0 },
11150   },
11151   {
11152     /* VEX_W_0F380D_P_2  */
11153     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11154   },
11155   {
11156     /* VEX_W_0F380E_P_2  */
11157     { "vtestps",        { XM, EXx }, 0 },
11158   },
11159   {
11160     /* VEX_W_0F380F_P_2  */
11161     { "vtestpd",        { XM, EXx }, 0 },
11162   },
11163   {
11164     /* VEX_W_0F3816_P_2  */
11165     { "vpermps",        { XM, Vex, EXx }, 0 },
11166   },
11167   {
11168     /* VEX_W_0F3817_P_2 */
11169     { "vptest",         { XM, EXx }, 0 },
11170   },
11171   {
11172     /* VEX_W_0F3818_P_2 */
11173     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11174   },
11175   {
11176     /* VEX_W_0F3819_P_2 */
11177     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11178   },
11179   {
11180     /* VEX_W_0F381A_P_2_M_0 */
11181     { "vbroadcastf128", { XM, Mxmm }, 0 },
11182   },
11183   {
11184     /* VEX_W_0F381C_P_2 */
11185     { "vpabsb",         { XM, EXx }, 0 },
11186   },
11187   {
11188     /* VEX_W_0F381D_P_2 */
11189     { "vpabsw",         { XM, EXx }, 0 },
11190   },
11191   {
11192     /* VEX_W_0F381E_P_2 */
11193     { "vpabsd",         { XM, EXx }, 0 },
11194   },
11195   {
11196     /* VEX_W_0F3820_P_2 */
11197     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11198   },
11199   {
11200     /* VEX_W_0F3821_P_2 */
11201     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11202   },
11203   {
11204     /* VEX_W_0F3822_P_2 */
11205     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11206   },
11207   {
11208     /* VEX_W_0F3823_P_2 */
11209     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11210   },
11211   {
11212     /* VEX_W_0F3824_P_2 */
11213     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11214   },
11215   {
11216     /* VEX_W_0F3825_P_2 */
11217     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11218   },
11219   {
11220     /* VEX_W_0F3828_P_2 */
11221     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11222   },
11223   {
11224     /* VEX_W_0F3829_P_2 */
11225     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11226   },
11227   {
11228     /* VEX_W_0F382A_P_2_M_0 */
11229     { "vmovntdqa",      { XM, Mx }, 0 },
11230   },
11231   {
11232     /* VEX_W_0F382B_P_2 */
11233     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11234   },
11235   {
11236     /* VEX_W_0F382C_P_2_M_0 */
11237     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11238   },
11239   {
11240     /* VEX_W_0F382D_P_2_M_0 */
11241     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11242   },
11243   {
11244     /* VEX_W_0F382E_P_2_M_0 */
11245     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11246   },
11247   {
11248     /* VEX_W_0F382F_P_2_M_0 */
11249     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11250   },
11251   {
11252     /* VEX_W_0F3830_P_2 */
11253     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11254   },
11255   {
11256     /* VEX_W_0F3831_P_2 */
11257     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11258   },
11259   {
11260     /* VEX_W_0F3832_P_2 */
11261     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11262   },
11263   {
11264     /* VEX_W_0F3833_P_2 */
11265     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11266   },
11267   {
11268     /* VEX_W_0F3834_P_2 */
11269     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11270   },
11271   {
11272     /* VEX_W_0F3835_P_2 */
11273     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11274   },
11275   {
11276     /* VEX_W_0F3836_P_2  */
11277     { "vpermd",         { XM, Vex, EXx }, 0 },
11278   },
11279   {
11280     /* VEX_W_0F3837_P_2 */
11281     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11282   },
11283   {
11284     /* VEX_W_0F3838_P_2 */
11285     { "vpminsb",        { XM, Vex, EXx }, 0 },
11286   },
11287   {
11288     /* VEX_W_0F3839_P_2 */
11289     { "vpminsd",        { XM, Vex, EXx }, 0 },
11290   },
11291   {
11292     /* VEX_W_0F383A_P_2 */
11293     { "vpminuw",        { XM, Vex, EXx }, 0 },
11294   },
11295   {
11296     /* VEX_W_0F383B_P_2 */
11297     { "vpminud",        { XM, Vex, EXx }, 0 },
11298   },
11299   {
11300     /* VEX_W_0F383C_P_2 */
11301     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11302   },
11303   {
11304     /* VEX_W_0F383D_P_2 */
11305     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11306   },
11307   {
11308     /* VEX_W_0F383E_P_2 */
11309     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11310   },
11311   {
11312     /* VEX_W_0F383F_P_2 */
11313     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11314   },
11315   {
11316     /* VEX_W_0F3840_P_2 */
11317     { "vpmulld",        { XM, Vex, EXx }, 0 },
11318   },
11319   {
11320     /* VEX_W_0F3841_P_2 */
11321     { "vphminposuw",    { XM, EXx }, 0 },
11322   },
11323   {
11324     /* VEX_W_0F3846_P_2 */
11325     { "vpsravd",        { XM, Vex, EXx }, 0 },
11326   },
11327   {
11328     /* VEX_W_0F3858_P_2 */
11329     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11330   },
11331   {
11332     /* VEX_W_0F3859_P_2 */
11333     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11334   },
11335   {
11336     /* VEX_W_0F385A_P_2_M_0 */
11337     { "vbroadcasti128", { XM, Mxmm }, 0 },
11338   },
11339   {
11340     /* VEX_W_0F3878_P_2 */
11341     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11342   },
11343   {
11344     /* VEX_W_0F3879_P_2 */
11345     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11346   },
11347   {
11348     /* VEX_W_0F38DB_P_2 */
11349     { "vaesimc",        { XM, EXx }, 0 },
11350   },
11351   {
11352     /* VEX_W_0F38DC_P_2 */
11353     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11354   },
11355   {
11356     /* VEX_W_0F38DD_P_2 */
11357     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11358   },
11359   {
11360     /* VEX_W_0F38DE_P_2 */
11361     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11362   },
11363   {
11364     /* VEX_W_0F38DF_P_2 */
11365     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11366   },
11367   {
11368     /* VEX_W_0F3A00_P_2 */
11369     { Bad_Opcode },
11370     { "vpermq",         { XM, EXx, Ib }, 0 },
11371   },
11372   {
11373     /* VEX_W_0F3A01_P_2 */
11374     { Bad_Opcode },
11375     { "vpermpd",        { XM, EXx, Ib }, 0 },
11376   },
11377   {
11378     /* VEX_W_0F3A02_P_2 */
11379     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11380   },
11381   {
11382     /* VEX_W_0F3A04_P_2 */
11383     { "vpermilps",      { XM, EXx, Ib }, 0 },
11384   },
11385   {
11386     /* VEX_W_0F3A05_P_2 */
11387     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11388   },
11389   {
11390     /* VEX_W_0F3A06_P_2 */
11391     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11392   },
11393   {
11394     /* VEX_W_0F3A08_P_2 */
11395     { "vroundps",       { XM, EXx, Ib }, 0 },
11396   },
11397   {
11398     /* VEX_W_0F3A09_P_2 */
11399     { "vroundpd",       { XM, EXx, Ib }, 0 },
11400   },
11401   {
11402     /* VEX_W_0F3A0A_P_2 */
11403     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11404   },
11405   {
11406     /* VEX_W_0F3A0B_P_2 */
11407     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11408   },
11409   {
11410     /* VEX_W_0F3A0C_P_2 */
11411     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11412   },
11413   {
11414     /* VEX_W_0F3A0D_P_2 */
11415     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11416   },
11417   {
11418     /* VEX_W_0F3A0E_P_2 */
11419     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11420   },
11421   {
11422     /* VEX_W_0F3A0F_P_2 */
11423     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11424   },
11425   {
11426     /* VEX_W_0F3A14_P_2 */
11427     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11428   },
11429   {
11430     /* VEX_W_0F3A15_P_2 */
11431     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11432   },
11433   {
11434     /* VEX_W_0F3A18_P_2 */
11435     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11436   },
11437   {
11438     /* VEX_W_0F3A19_P_2 */
11439     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11440   },
11441   {
11442     /* VEX_W_0F3A20_P_2 */
11443     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11444   },
11445   {
11446     /* VEX_W_0F3A21_P_2 */
11447     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11448   },
11449   {
11450     /* VEX_W_0F3A30_P_2_LEN_0 */
11451     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
11452     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
11453   },
11454   {
11455     /* VEX_W_0F3A31_P_2_LEN_0 */
11456     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
11457     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
11458   },
11459   {
11460     /* VEX_W_0F3A32_P_2_LEN_0 */
11461     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
11462     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
11463   },
11464   {
11465     /* VEX_W_0F3A33_P_2_LEN_0 */
11466     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
11467     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
11468   },
11469   {
11470     /* VEX_W_0F3A38_P_2 */
11471     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11472   },
11473   {
11474     /* VEX_W_0F3A39_P_2 */
11475     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11476   },
11477   {
11478     /* VEX_W_0F3A40_P_2 */
11479     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11480   },
11481   {
11482     /* VEX_W_0F3A41_P_2 */
11483     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11484   },
11485   {
11486     /* VEX_W_0F3A42_P_2 */
11487     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11488   },
11489   {
11490     /* VEX_W_0F3A44_P_2 */
11491     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11492   },
11493   {
11494     /* VEX_W_0F3A46_P_2 */
11495     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11496   },
11497   {
11498     /* VEX_W_0F3A48_P_2 */
11499     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11500     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11501   },
11502   {
11503     /* VEX_W_0F3A49_P_2 */
11504     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11505     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11506   },
11507   {
11508     /* VEX_W_0F3A4A_P_2 */
11509     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11510   },
11511   {
11512     /* VEX_W_0F3A4B_P_2 */
11513     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11514   },
11515   {
11516     /* VEX_W_0F3A4C_P_2 */
11517     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11518   },
11519   {
11520     /* VEX_W_0F3A60_P_2 */
11521     { "vpcmpestrm",     { XM, EXx, Ib }, 0 },
11522   },
11523   {
11524     /* VEX_W_0F3A61_P_2 */
11525     { "vpcmpestri",     { XM, EXx, Ib }, 0 },
11526   },
11527   {
11528     /* VEX_W_0F3A62_P_2 */
11529     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11530   },
11531   {
11532     /* VEX_W_0F3A63_P_2 */
11533     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11534   },
11535   {
11536     /* VEX_W_0F3ADF_P_2 */
11537     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11538   },
11539 #define NEED_VEX_W_TABLE
11540 #include "i386-dis-evex.h"
11541 #undef NEED_VEX_W_TABLE
11542 };
11543
11544 static const struct dis386 mod_table[][2] = {
11545   {
11546     /* MOD_8D */
11547     { "leaS",           { Gv, M }, 0 },
11548   },
11549   {
11550     /* MOD_C6_REG_7 */
11551     { Bad_Opcode },
11552     { RM_TABLE (RM_C6_REG_7) },
11553   },
11554   {
11555     /* MOD_C7_REG_7 */
11556     { Bad_Opcode },
11557     { RM_TABLE (RM_C7_REG_7) },
11558   },
11559   {
11560     /* MOD_FF_REG_3 */
11561     { "Jcall{T|}", { indirEp }, 0 },
11562   },
11563   {
11564     /* MOD_FF_REG_5 */
11565     { "Jjmp{T|}", { indirEp }, 0 },
11566   },
11567   {
11568     /* MOD_0F01_REG_0 */
11569     { X86_64_TABLE (X86_64_0F01_REG_0) },
11570     { RM_TABLE (RM_0F01_REG_0) },
11571   },
11572   {
11573     /* MOD_0F01_REG_1 */
11574     { X86_64_TABLE (X86_64_0F01_REG_1) },
11575     { RM_TABLE (RM_0F01_REG_1) },
11576   },
11577   {
11578     /* MOD_0F01_REG_2 */
11579     { X86_64_TABLE (X86_64_0F01_REG_2) },
11580     { RM_TABLE (RM_0F01_REG_2) },
11581   },
11582   {
11583     /* MOD_0F01_REG_3 */
11584     { X86_64_TABLE (X86_64_0F01_REG_3) },
11585     { RM_TABLE (RM_0F01_REG_3) },
11586   },
11587   {
11588     /* MOD_0F01_REG_7 */
11589     { "invlpg",         { Mb }, 0 },
11590     { RM_TABLE (RM_0F01_REG_7) },
11591   },
11592   {
11593     /* MOD_0F12_PREFIX_0 */
11594     { "movlps",         { XM, EXq }, PREFIX_MANDATORY },
11595     { "movhlps",        { XM, EXq }, PREFIX_MANDATORY },
11596   },
11597   {
11598     /* MOD_0F13 */
11599     { "movlpX",         { EXq, XM }, PREFIX_MANDATORY },
11600   },
11601   {
11602     /* MOD_0F16_PREFIX_0 */
11603     { "movhps",         { XM, EXq }, 0 },
11604     { "movlhps",        { XM, EXq }, 0 },
11605   },
11606   {
11607     /* MOD_0F17 */
11608     { "movhpX",         { EXq, XM }, PREFIX_MANDATORY },
11609   },
11610   {
11611     /* MOD_0F18_REG_0 */
11612     { "prefetchnta",    { Mb }, 0 },
11613   },
11614   {
11615     /* MOD_0F18_REG_1 */
11616     { "prefetcht0",     { Mb }, 0 },
11617   },
11618   {
11619     /* MOD_0F18_REG_2 */
11620     { "prefetcht1",     { Mb }, 0 },
11621   },
11622   {
11623     /* MOD_0F18_REG_3 */
11624     { "prefetcht2",     { Mb }, 0 },
11625   },
11626   {
11627     /* MOD_0F18_REG_4 */
11628     { "nop/reserved",   { Mb }, 0 },
11629   },
11630   {
11631     /* MOD_0F18_REG_5 */
11632     { "nop/reserved",   { Mb }, 0 },
11633   },
11634   {
11635     /* MOD_0F18_REG_6 */
11636     { "nop/reserved",   { Mb }, 0 },
11637   },
11638   {
11639     /* MOD_0F18_REG_7 */
11640     { "nop/reserved",   { Mb }, 0 },
11641   },
11642   {
11643     /* MOD_0F1A_PREFIX_0 */
11644     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11645     { "nopQ",           { Ev }, 0 },
11646   },
11647   {
11648     /* MOD_0F1B_PREFIX_0 */
11649     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11650     { "nopQ",           { Ev }, 0 },
11651   },
11652   {
11653     /* MOD_0F1B_PREFIX_1 */
11654     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11655     { "nopQ",           { Ev }, 0 },
11656   },
11657   {
11658     /* MOD_0F24 */
11659     { Bad_Opcode },
11660     { "movL",           { Rd, Td }, 0 },
11661   },
11662   {
11663     /* MOD_0F26 */
11664     { Bad_Opcode },
11665     { "movL",           { Td, Rd }, 0 },
11666   },
11667   {
11668     /* MOD_0F2B_PREFIX_0 */
11669     {"movntps",         { Mx, XM }, PREFIX_MANDATORY },
11670   },
11671   {
11672     /* MOD_0F2B_PREFIX_1 */
11673     {"movntss",         { Md, XM }, PREFIX_MANDATORY },
11674   },
11675   {
11676     /* MOD_0F2B_PREFIX_2 */
11677     {"movntpd",         { Mx, XM }, PREFIX_MANDATORY },
11678   },
11679   {
11680     /* MOD_0F2B_PREFIX_3 */
11681     {"movntsd",         { Mq, XM }, PREFIX_MANDATORY },
11682   },
11683   {
11684     /* MOD_0F51 */
11685     { Bad_Opcode },
11686     { "movmskpX",       { Gdq, XS }, PREFIX_MANDATORY },
11687   },
11688   {
11689     /* MOD_0F71_REG_2 */
11690     { Bad_Opcode },
11691     { "psrlw",          { MS, Ib }, 0 },
11692   },
11693   {
11694     /* MOD_0F71_REG_4 */
11695     { Bad_Opcode },
11696     { "psraw",          { MS, Ib }, 0 },
11697   },
11698   {
11699     /* MOD_0F71_REG_6 */
11700     { Bad_Opcode },
11701     { "psllw",          { MS, Ib }, 0 },
11702   },
11703   {
11704     /* MOD_0F72_REG_2 */
11705     { Bad_Opcode },
11706     { "psrld",          { MS, Ib }, 0 },
11707   },
11708   {
11709     /* MOD_0F72_REG_4 */
11710     { Bad_Opcode },
11711     { "psrad",          { MS, Ib }, 0 },
11712   },
11713   {
11714     /* MOD_0F72_REG_6 */
11715     { Bad_Opcode },
11716     { "pslld",          { MS, Ib }, 0 },
11717   },
11718   {
11719     /* MOD_0F73_REG_2 */
11720     { Bad_Opcode },
11721     { "psrlq",          { MS, Ib }, 0 },
11722   },
11723   {
11724     /* MOD_0F73_REG_3 */
11725     { Bad_Opcode },
11726     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11727   },
11728   {
11729     /* MOD_0F73_REG_6 */
11730     { Bad_Opcode },
11731     { "psllq",          { MS, Ib }, 0 },
11732   },
11733   {
11734     /* MOD_0F73_REG_7 */
11735     { Bad_Opcode },
11736     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11737   },
11738   {
11739     /* MOD_0FAE_REG_0 */
11740     { "fxsave",         { FXSAVE }, 0 },
11741     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11742   },
11743   {
11744     /* MOD_0FAE_REG_1 */
11745     { "fxrstor",        { FXSAVE }, 0 },
11746     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11747   },
11748   {
11749     /* MOD_0FAE_REG_2 */
11750     { "ldmxcsr",        { Md }, 0 },
11751     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11752   },
11753   {
11754     /* MOD_0FAE_REG_3 */
11755     { "stmxcsr",        { Md }, 0 },
11756     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11757   },
11758   {
11759     /* MOD_0FAE_REG_4 */
11760     { "xsave",          { FXSAVE }, 0 },
11761   },
11762   {
11763     /* MOD_0FAE_REG_5 */
11764     { "xrstor",         { FXSAVE }, 0 },
11765     { RM_TABLE (RM_0FAE_REG_5) },
11766   },
11767   {
11768     /* MOD_0FAE_REG_6 */
11769     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11770     { RM_TABLE (RM_0FAE_REG_6) },
11771   },
11772   {
11773     /* MOD_0FAE_REG_7 */
11774     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11775     { RM_TABLE (RM_0FAE_REG_7) },
11776   },
11777   {
11778     /* MOD_0FB2 */
11779     { "lssS",           { Gv, Mp }, 0 },
11780   },
11781   {
11782     /* MOD_0FB4 */
11783     { "lfsS",           { Gv, Mp }, 0 },
11784   },
11785   {
11786     /* MOD_0FB5 */
11787     { "lgsS",           { Gv, Mp }, 0 },
11788   },
11789   {
11790     /* MOD_0FC7_REG_3 */
11791     { "xrstors",                { FXSAVE }, 0 },
11792   },
11793   {
11794     /* MOD_0FC7_REG_4 */
11795     { "xsavec",         { FXSAVE }, 0 },
11796   },
11797   {
11798     /* MOD_0FC7_REG_5 */
11799     { "xsaves",         { FXSAVE }, 0 },
11800   },
11801   {
11802     /* MOD_0FC7_REG_6 */
11803     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11804     { "rdrand",         { Ev }, 0 },
11805   },
11806   {
11807     /* MOD_0FC7_REG_7 */
11808     { "vmptrst",        { Mq }, 0 },
11809     { "rdseed",         { Ev }, 0 },
11810   },
11811   {
11812     /* MOD_0FD7 */
11813     { Bad_Opcode },
11814     { "pmovmskb",       { Gdq, MS }, 0 },
11815   },
11816   {
11817     /* MOD_0FE7_PREFIX_2 */
11818     { "movntdq",        { Mx, XM }, 0 },
11819   },
11820   {
11821     /* MOD_0FF0_PREFIX_3 */
11822     { "lddqu",          { XM, M }, 0 },
11823   },
11824   {
11825     /* MOD_0F382A_PREFIX_2 */
11826     { "movntdqa",       { XM, Mx }, 0 },
11827   },
11828   {
11829     /* MOD_62_32BIT */
11830     { "bound{S|}",      { Gv, Ma }, 0 },
11831     { EVEX_TABLE (EVEX_0F) },
11832   },
11833   {
11834     /* MOD_C4_32BIT */
11835     { "lesS",           { Gv, Mp }, 0 },
11836     { VEX_C4_TABLE (VEX_0F) },
11837   },
11838   {
11839     /* MOD_C5_32BIT */
11840     { "ldsS",           { Gv, Mp }, 0 },
11841     { VEX_C5_TABLE (VEX_0F) },
11842   },
11843   {
11844     /* MOD_VEX_0F12_PREFIX_0 */
11845     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11846     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11847   },
11848   {
11849     /* MOD_VEX_0F13 */
11850     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11851   },
11852   {
11853     /* MOD_VEX_0F16_PREFIX_0 */
11854     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11855     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11856   },
11857   {
11858     /* MOD_VEX_0F17 */
11859     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11860   },
11861   {
11862     /* MOD_VEX_0F2B */
11863     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11864   },
11865   {
11866     /* MOD_VEX_0F50 */
11867     { Bad_Opcode },
11868     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11869   },
11870   {
11871     /* MOD_VEX_0F71_REG_2 */
11872     { Bad_Opcode },
11873     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11874   },
11875   {
11876     /* MOD_VEX_0F71_REG_4 */
11877     { Bad_Opcode },
11878     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11879   },
11880   {
11881     /* MOD_VEX_0F71_REG_6 */
11882     { Bad_Opcode },
11883     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11884   },
11885   {
11886     /* MOD_VEX_0F72_REG_2 */
11887     { Bad_Opcode },
11888     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11889   },
11890   {
11891     /* MOD_VEX_0F72_REG_4 */
11892     { Bad_Opcode },
11893     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11894   },
11895   {
11896     /* MOD_VEX_0F72_REG_6 */
11897     { Bad_Opcode },
11898     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11899   },
11900   {
11901     /* MOD_VEX_0F73_REG_2 */
11902     { Bad_Opcode },
11903     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11904   },
11905   {
11906     /* MOD_VEX_0F73_REG_3 */
11907     { Bad_Opcode },
11908     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11909   },
11910   {
11911     /* MOD_VEX_0F73_REG_6 */
11912     { Bad_Opcode },
11913     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11914   },
11915   {
11916     /* MOD_VEX_0F73_REG_7 */
11917     { Bad_Opcode },
11918     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11919   },
11920   {
11921     /* MOD_VEX_0FAE_REG_2 */
11922     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11923   },
11924   {
11925     /* MOD_VEX_0FAE_REG_3 */
11926     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11927   },
11928   {
11929     /* MOD_VEX_0FD7_PREFIX_2 */
11930     { Bad_Opcode },
11931     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11932   },
11933   {
11934     /* MOD_VEX_0FE7_PREFIX_2 */
11935     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11936   },
11937   {
11938     /* MOD_VEX_0FF0_PREFIX_3 */
11939     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11940   },
11941   {
11942     /* MOD_VEX_0F381A_PREFIX_2 */
11943     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11944   },
11945   {
11946     /* MOD_VEX_0F382A_PREFIX_2 */
11947     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11948   },
11949   {
11950     /* MOD_VEX_0F382C_PREFIX_2 */
11951     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11952   },
11953   {
11954     /* MOD_VEX_0F382D_PREFIX_2 */
11955     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11956   },
11957   {
11958     /* MOD_VEX_0F382E_PREFIX_2 */
11959     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11960   },
11961   {
11962     /* MOD_VEX_0F382F_PREFIX_2 */
11963     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11964   },
11965   {
11966     /* MOD_VEX_0F385A_PREFIX_2 */
11967     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11968   },
11969   {
11970     /* MOD_VEX_0F388C_PREFIX_2 */
11971     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
11972   },
11973   {
11974     /* MOD_VEX_0F388E_PREFIX_2 */
11975     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
11976   },
11977 #define NEED_MOD_TABLE
11978 #include "i386-dis-evex.h"
11979 #undef NEED_MOD_TABLE
11980 };
11981
11982 static const struct dis386 rm_table[][8] = {
11983   {
11984     /* RM_C6_REG_7 */
11985     { "xabort",         { Skip_MODRM, Ib }, 0 },
11986   },
11987   {
11988     /* RM_C7_REG_7 */
11989     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
11990   },
11991   {
11992     /* RM_0F01_REG_0 */
11993     { Bad_Opcode },
11994     { "vmcall",         { Skip_MODRM }, 0 },
11995     { "vmlaunch",       { Skip_MODRM }, 0 },
11996     { "vmresume",       { Skip_MODRM }, 0 },
11997     { "vmxoff",         { Skip_MODRM }, 0 },
11998   },
11999   {
12000     /* RM_0F01_REG_1 */
12001     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12002     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12003     { "clac",           { Skip_MODRM }, 0 },
12004     { "stac",           { Skip_MODRM }, 0 },
12005     { Bad_Opcode },
12006     { Bad_Opcode },
12007     { Bad_Opcode },
12008     { "encls",          { Skip_MODRM }, 0 },
12009   },
12010   {
12011     /* RM_0F01_REG_2 */
12012     { "xgetbv",         { Skip_MODRM }, 0 },
12013     { "xsetbv",         { Skip_MODRM }, 0 },
12014     { Bad_Opcode },
12015     { Bad_Opcode },
12016     { "vmfunc",         { Skip_MODRM }, 0 },
12017     { "xend",           { Skip_MODRM }, 0 },
12018     { "xtest",          { Skip_MODRM }, 0 },
12019     { "enclu",          { Skip_MODRM }, 0 },
12020   },
12021   {
12022     /* RM_0F01_REG_3 */
12023     { "vmrun",          { Skip_MODRM }, 0 },
12024     { "vmmcall",        { Skip_MODRM }, 0 },
12025     { "vmload",         { Skip_MODRM }, 0 },
12026     { "vmsave",         { Skip_MODRM }, 0 },
12027     { "stgi",           { Skip_MODRM }, 0 },
12028     { "clgi",           { Skip_MODRM }, 0 },
12029     { "skinit",         { Skip_MODRM }, 0 },
12030     { "invlpga",        { Skip_MODRM }, 0 },
12031   },
12032   {
12033     /* RM_0F01_REG_7 */
12034     { "swapgs",         { Skip_MODRM }, 0  },
12035     { "rdtscp",         { Skip_MODRM }, 0  },
12036     { Bad_Opcode },
12037     { Bad_Opcode },
12038     { "clzero",         { Skip_MODRM }, 0  },
12039   },
12040   {
12041     /* RM_0FAE_REG_5 */
12042     { "lfence",         { Skip_MODRM }, 0 },
12043   },
12044   {
12045     /* RM_0FAE_REG_6 */
12046     { "mfence",         { Skip_MODRM }, 0 },
12047   },
12048   {
12049     /* RM_0FAE_REG_7 */
12050     { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
12051   },
12052 };
12053
12054 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12055
12056 /* We use the high bit to indicate different name for the same
12057    prefix.  */
12058 #define REP_PREFIX      (0xf3 | 0x100)
12059 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12060 #define XRELEASE_PREFIX (0xf3 | 0x400)
12061 #define BND_PREFIX      (0xf2 | 0x400)
12062
12063 static int
12064 ckprefix (void)
12065 {
12066   int newrex, i, length;
12067   rex = 0;
12068   rex_ignored = 0;
12069   prefixes = 0;
12070   used_prefixes = 0;
12071   rex_used = 0;
12072   last_lock_prefix = -1;
12073   last_repz_prefix = -1;
12074   last_repnz_prefix = -1;
12075   last_data_prefix = -1;
12076   last_addr_prefix = -1;
12077   last_rex_prefix = -1;
12078   last_seg_prefix = -1;
12079   fwait_prefix = -1;
12080   active_seg_prefix = 0;
12081   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12082     all_prefixes[i] = 0;
12083   i = 0;
12084   length = 0;
12085   /* The maximum instruction length is 15bytes.  */
12086   while (length < MAX_CODE_LENGTH - 1)
12087     {
12088       FETCH_DATA (the_info, codep + 1);
12089       newrex = 0;
12090       switch (*codep)
12091         {
12092         /* REX prefixes family.  */
12093         case 0x40:
12094         case 0x41:
12095         case 0x42:
12096         case 0x43:
12097         case 0x44:
12098         case 0x45:
12099         case 0x46:
12100         case 0x47:
12101         case 0x48:
12102         case 0x49:
12103         case 0x4a:
12104         case 0x4b:
12105         case 0x4c:
12106         case 0x4d:
12107         case 0x4e:
12108         case 0x4f:
12109           if (address_mode == mode_64bit)
12110             newrex = *codep;
12111           else
12112             return 1;
12113           last_rex_prefix = i;
12114           break;
12115         case 0xf3:
12116           prefixes |= PREFIX_REPZ;
12117           last_repz_prefix = i;
12118           break;
12119         case 0xf2:
12120           prefixes |= PREFIX_REPNZ;
12121           last_repnz_prefix = i;
12122           break;
12123         case 0xf0:
12124           prefixes |= PREFIX_LOCK;
12125           last_lock_prefix = i;
12126           break;
12127         case 0x2e:
12128           prefixes |= PREFIX_CS;
12129           last_seg_prefix = i;
12130           active_seg_prefix = PREFIX_CS;
12131           break;
12132         case 0x36:
12133           prefixes |= PREFIX_SS;
12134           last_seg_prefix = i;
12135           active_seg_prefix = PREFIX_SS;
12136           break;
12137         case 0x3e:
12138           prefixes |= PREFIX_DS;
12139           last_seg_prefix = i;
12140           active_seg_prefix = PREFIX_DS;
12141           break;
12142         case 0x26:
12143           prefixes |= PREFIX_ES;
12144           last_seg_prefix = i;
12145           active_seg_prefix = PREFIX_ES;
12146           break;
12147         case 0x64:
12148           prefixes |= PREFIX_FS;
12149           last_seg_prefix = i;
12150           active_seg_prefix = PREFIX_FS;
12151           break;
12152         case 0x65:
12153           prefixes |= PREFIX_GS;
12154           last_seg_prefix = i;
12155           active_seg_prefix = PREFIX_GS;
12156           break;
12157         case 0x66:
12158           prefixes |= PREFIX_DATA;
12159           last_data_prefix = i;
12160           break;
12161         case 0x67:
12162           prefixes |= PREFIX_ADDR;
12163           last_addr_prefix = i;
12164           break;
12165         case FWAIT_OPCODE:
12166           /* fwait is really an instruction.  If there are prefixes
12167              before the fwait, they belong to the fwait, *not* to the
12168              following instruction.  */
12169           fwait_prefix = i;
12170           if (prefixes || rex)
12171             {
12172               prefixes |= PREFIX_FWAIT;
12173               codep++;
12174               /* This ensures that the previous REX prefixes are noticed
12175                  as unused prefixes, as in the return case below.  */
12176               rex_used = rex;
12177               return 1;
12178             }
12179           prefixes = PREFIX_FWAIT;
12180           break;
12181         default:
12182           return 1;
12183         }
12184       /* Rex is ignored when followed by another prefix.  */
12185       if (rex)
12186         {
12187           rex_used = rex;
12188           return 1;
12189         }
12190       if (*codep != FWAIT_OPCODE)
12191         all_prefixes[i++] = *codep;
12192       rex = newrex;
12193       codep++;
12194       length++;
12195     }
12196   return 0;
12197 }
12198
12199 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12200    prefix byte.  */
12201
12202 static const char *
12203 prefix_name (int pref, int sizeflag)
12204 {
12205   static const char *rexes [16] =
12206     {
12207       "rex",            /* 0x40 */
12208       "rex.B",          /* 0x41 */
12209       "rex.X",          /* 0x42 */
12210       "rex.XB",         /* 0x43 */
12211       "rex.R",          /* 0x44 */
12212       "rex.RB",         /* 0x45 */
12213       "rex.RX",         /* 0x46 */
12214       "rex.RXB",        /* 0x47 */
12215       "rex.W",          /* 0x48 */
12216       "rex.WB",         /* 0x49 */
12217       "rex.WX",         /* 0x4a */
12218       "rex.WXB",        /* 0x4b */
12219       "rex.WR",         /* 0x4c */
12220       "rex.WRB",        /* 0x4d */
12221       "rex.WRX",        /* 0x4e */
12222       "rex.WRXB",       /* 0x4f */
12223     };
12224
12225   switch (pref)
12226     {
12227     /* REX prefixes family.  */
12228     case 0x40:
12229     case 0x41:
12230     case 0x42:
12231     case 0x43:
12232     case 0x44:
12233     case 0x45:
12234     case 0x46:
12235     case 0x47:
12236     case 0x48:
12237     case 0x49:
12238     case 0x4a:
12239     case 0x4b:
12240     case 0x4c:
12241     case 0x4d:
12242     case 0x4e:
12243     case 0x4f:
12244       return rexes [pref - 0x40];
12245     case 0xf3:
12246       return "repz";
12247     case 0xf2:
12248       return "repnz";
12249     case 0xf0:
12250       return "lock";
12251     case 0x2e:
12252       return "cs";
12253     case 0x36:
12254       return "ss";
12255     case 0x3e:
12256       return "ds";
12257     case 0x26:
12258       return "es";
12259     case 0x64:
12260       return "fs";
12261     case 0x65:
12262       return "gs";
12263     case 0x66:
12264       return (sizeflag & DFLAG) ? "data16" : "data32";
12265     case 0x67:
12266       if (address_mode == mode_64bit)
12267         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12268       else
12269         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12270     case FWAIT_OPCODE:
12271       return "fwait";
12272     case REP_PREFIX:
12273       return "rep";
12274     case XACQUIRE_PREFIX:
12275       return "xacquire";
12276     case XRELEASE_PREFIX:
12277       return "xrelease";
12278     case BND_PREFIX:
12279       return "bnd";
12280     default:
12281       return NULL;
12282     }
12283 }
12284
12285 static char op_out[MAX_OPERANDS][100];
12286 static int op_ad, op_index[MAX_OPERANDS];
12287 static int two_source_ops;
12288 static bfd_vma op_address[MAX_OPERANDS];
12289 static bfd_vma op_riprel[MAX_OPERANDS];
12290 static bfd_vma start_pc;
12291
12292 /*
12293  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12294  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12295  *   section of the "Virtual 8086 Mode" chapter.)
12296  * 'pc' should be the address of this instruction, it will
12297  *   be used to print the target address if this is a relative jump or call
12298  * The function returns the length of this instruction in bytes.
12299  */
12300
12301 static char intel_syntax;
12302 static char intel_mnemonic = !SYSV386_COMPAT;
12303 static char open_char;
12304 static char close_char;
12305 static char separator_char;
12306 static char scale_char;
12307
12308 /* Here for backwards compatibility.  When gdb stops using
12309    print_insn_i386_att and print_insn_i386_intel these functions can
12310    disappear, and print_insn_i386 be merged into print_insn.  */
12311 int
12312 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12313 {
12314   intel_syntax = 0;
12315
12316   return print_insn (pc, info);
12317 }
12318
12319 int
12320 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12321 {
12322   intel_syntax = 1;
12323
12324   return print_insn (pc, info);
12325 }
12326
12327 int
12328 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12329 {
12330   intel_syntax = -1;
12331
12332   return print_insn (pc, info);
12333 }
12334
12335 void
12336 print_i386_disassembler_options (FILE *stream)
12337 {
12338   fprintf (stream, _("\n\
12339 The following i386/x86-64 specific disassembler options are supported for use\n\
12340 with the -M switch (multiple options should be separated by commas):\n"));
12341
12342   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12343   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12344   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12345   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12346   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12347   fprintf (stream, _("  att-mnemonic\n"
12348                      "              Display instruction in AT&T mnemonic\n"));
12349   fprintf (stream, _("  intel-mnemonic\n"
12350                      "              Display instruction in Intel mnemonic\n"));
12351   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12352   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12353   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12354   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12355   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12356   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12357 }
12358
12359 /* Bad opcode.  */
12360 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12361
12362 /* Get a pointer to struct dis386 with a valid name.  */
12363
12364 static const struct dis386 *
12365 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12366 {
12367   int vindex, vex_table_index;
12368
12369   if (dp->name != NULL)
12370     return dp;
12371
12372   switch (dp->op[0].bytemode)
12373     {
12374     case USE_REG_TABLE:
12375       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12376       break;
12377
12378     case USE_MOD_TABLE:
12379       vindex = modrm.mod == 0x3 ? 1 : 0;
12380       dp = &mod_table[dp->op[1].bytemode][vindex];
12381       break;
12382
12383     case USE_RM_TABLE:
12384       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12385       break;
12386
12387     case USE_PREFIX_TABLE:
12388       if (need_vex)
12389         {
12390           /* The prefix in VEX is implicit.  */
12391           switch (vex.prefix)
12392             {
12393             case 0:
12394               vindex = 0;
12395               break;
12396             case REPE_PREFIX_OPCODE:
12397               vindex = 1;
12398               break;
12399             case DATA_PREFIX_OPCODE:
12400               vindex = 2;
12401               break;
12402             case REPNE_PREFIX_OPCODE:
12403               vindex = 3;
12404               break;
12405             default:
12406               abort ();
12407               break;
12408             }
12409         }
12410       else
12411         {
12412           int last_prefix = -1;
12413           int prefix = 0;
12414           vindex = 0;
12415           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12416              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12417              last one wins.  */
12418           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12419             {
12420               if (last_repz_prefix > last_repnz_prefix)
12421                 {
12422                   vindex = 1;
12423                   prefix = PREFIX_REPZ;
12424                   last_prefix = last_repz_prefix;
12425                 }
12426               else
12427                 {
12428                   vindex = 3;
12429                   prefix = PREFIX_REPNZ;
12430                   last_prefix = last_repnz_prefix;
12431                 }
12432
12433               /* Ignore the invalid index if it isn't mandatory.  */
12434               if (!mandatory_prefix
12435                   && (prefix_table[dp->op[1].bytemode][vindex].name
12436                       == NULL)
12437                   && (prefix_table[dp->op[1].bytemode][vindex].op[0].bytemode
12438                       == 0))
12439                 vindex = 0;
12440             }
12441
12442           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12443             {
12444               vindex = 2;
12445               prefix = PREFIX_DATA;
12446               last_prefix = last_data_prefix;
12447             }
12448
12449           if (vindex != 0)
12450             {
12451               used_prefixes |= prefix;
12452               all_prefixes[last_prefix] = 0;
12453             }
12454         }
12455       dp = &prefix_table[dp->op[1].bytemode][vindex];
12456       break;
12457
12458     case USE_X86_64_TABLE:
12459       vindex = address_mode == mode_64bit ? 1 : 0;
12460       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12461       break;
12462
12463     case USE_3BYTE_TABLE:
12464       FETCH_DATA (info, codep + 2);
12465       vindex = *codep++;
12466       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12467       end_codep = codep;
12468       modrm.mod = (*codep >> 6) & 3;
12469       modrm.reg = (*codep >> 3) & 7;
12470       modrm.rm = *codep & 7;
12471       break;
12472
12473     case USE_VEX_LEN_TABLE:
12474       if (!need_vex)
12475         abort ();
12476
12477       switch (vex.length)
12478         {
12479         case 128:
12480           vindex = 0;
12481           break;
12482         case 256:
12483           vindex = 1;
12484           break;
12485         default:
12486           abort ();
12487           break;
12488         }
12489
12490       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12491       break;
12492
12493     case USE_XOP_8F_TABLE:
12494       FETCH_DATA (info, codep + 3);
12495       /* All bits in the REX prefix are ignored.  */
12496       rex_ignored = rex;
12497       rex = ~(*codep >> 5) & 0x7;
12498
12499       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12500       switch ((*codep & 0x1f))
12501         {
12502         default:
12503           dp = &bad_opcode;
12504           return dp;
12505         case 0x8:
12506           vex_table_index = XOP_08;
12507           break;
12508         case 0x9:
12509           vex_table_index = XOP_09;
12510           break;
12511         case 0xa:
12512           vex_table_index = XOP_0A;
12513           break;
12514         }
12515       codep++;
12516       vex.w = *codep & 0x80;
12517       if (vex.w && address_mode == mode_64bit)
12518         rex |= REX_W;
12519
12520       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12521       if (address_mode != mode_64bit
12522           && vex.register_specifier > 0x7)
12523         {
12524           dp = &bad_opcode;
12525           return dp;
12526         }
12527
12528       vex.length = (*codep & 0x4) ? 256 : 128;
12529       switch ((*codep & 0x3))
12530         {
12531         case 0:
12532           vex.prefix = 0;
12533           break;
12534         case 1:
12535           vex.prefix = DATA_PREFIX_OPCODE;
12536           break;
12537         case 2:
12538           vex.prefix = REPE_PREFIX_OPCODE;
12539           break;
12540         case 3:
12541           vex.prefix = REPNE_PREFIX_OPCODE;
12542           break;
12543         }
12544       need_vex = 1;
12545       need_vex_reg = 1;
12546       codep++;
12547       vindex = *codep++;
12548       dp = &xop_table[vex_table_index][vindex];
12549
12550       end_codep = codep;
12551       FETCH_DATA (info, codep + 1);
12552       modrm.mod = (*codep >> 6) & 3;
12553       modrm.reg = (*codep >> 3) & 7;
12554       modrm.rm = *codep & 7;
12555       break;
12556
12557     case USE_VEX_C4_TABLE:
12558       /* VEX prefix.  */
12559       FETCH_DATA (info, codep + 3);
12560       /* All bits in the REX prefix are ignored.  */
12561       rex_ignored = rex;
12562       rex = ~(*codep >> 5) & 0x7;
12563       switch ((*codep & 0x1f))
12564         {
12565         default:
12566           dp = &bad_opcode;
12567           return dp;
12568         case 0x1:
12569           vex_table_index = VEX_0F;
12570           break;
12571         case 0x2:
12572           vex_table_index = VEX_0F38;
12573           break;
12574         case 0x3:
12575           vex_table_index = VEX_0F3A;
12576           break;
12577         }
12578       codep++;
12579       vex.w = *codep & 0x80;
12580       if (vex.w && address_mode == mode_64bit)
12581         rex |= REX_W;
12582
12583       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12584       if (address_mode != mode_64bit
12585           && vex.register_specifier > 0x7)
12586         {
12587           dp = &bad_opcode;
12588           return dp;
12589         }
12590
12591       vex.length = (*codep & 0x4) ? 256 : 128;
12592       switch ((*codep & 0x3))
12593         {
12594         case 0:
12595           vex.prefix = 0;
12596           break;
12597         case 1:
12598           vex.prefix = DATA_PREFIX_OPCODE;
12599           break;
12600         case 2:
12601           vex.prefix = REPE_PREFIX_OPCODE;
12602           break;
12603         case 3:
12604           vex.prefix = REPNE_PREFIX_OPCODE;
12605           break;
12606         }
12607       need_vex = 1;
12608       need_vex_reg = 1;
12609       codep++;
12610       vindex = *codep++;
12611       dp = &vex_table[vex_table_index][vindex];
12612       end_codep = codep;
12613       /* There is no MODRM byte for VEX [82|77].  */
12614       if (vindex != 0x77 && vindex != 0x82)
12615         {
12616           FETCH_DATA (info, codep + 1);
12617           modrm.mod = (*codep >> 6) & 3;
12618           modrm.reg = (*codep >> 3) & 7;
12619           modrm.rm = *codep & 7;
12620         }
12621       break;
12622
12623     case USE_VEX_C5_TABLE:
12624       /* VEX prefix.  */
12625       FETCH_DATA (info, codep + 2);
12626       /* All bits in the REX prefix are ignored.  */
12627       rex_ignored = rex;
12628       rex = (*codep & 0x80) ? 0 : REX_R;
12629
12630       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12631       if (address_mode != mode_64bit
12632           && vex.register_specifier > 0x7)
12633         {
12634           dp = &bad_opcode;
12635           return dp;
12636         }
12637
12638       vex.w = 0;
12639
12640       vex.length = (*codep & 0x4) ? 256 : 128;
12641       switch ((*codep & 0x3))
12642         {
12643         case 0:
12644           vex.prefix = 0;
12645           break;
12646         case 1:
12647           vex.prefix = DATA_PREFIX_OPCODE;
12648           break;
12649         case 2:
12650           vex.prefix = REPE_PREFIX_OPCODE;
12651           break;
12652         case 3:
12653           vex.prefix = REPNE_PREFIX_OPCODE;
12654           break;
12655         }
12656       need_vex = 1;
12657       need_vex_reg = 1;
12658       codep++;
12659       vindex = *codep++;
12660       dp = &vex_table[dp->op[1].bytemode][vindex];
12661       end_codep = codep;
12662       /* There is no MODRM byte for VEX [82|77].  */
12663       if (vindex != 0x77 && vindex != 0x82)
12664         {
12665           FETCH_DATA (info, codep + 1);
12666           modrm.mod = (*codep >> 6) & 3;
12667           modrm.reg = (*codep >> 3) & 7;
12668           modrm.rm = *codep & 7;
12669         }
12670       break;
12671
12672     case USE_VEX_W_TABLE:
12673       if (!need_vex)
12674         abort ();
12675
12676       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12677       break;
12678
12679     case USE_EVEX_TABLE:
12680       two_source_ops = 0;
12681       /* EVEX prefix.  */
12682       vex.evex = 1;
12683       FETCH_DATA (info, codep + 4);
12684       /* All bits in the REX prefix are ignored.  */
12685       rex_ignored = rex;
12686       /* The first byte after 0x62.  */
12687       rex = ~(*codep >> 5) & 0x7;
12688       vex.r = *codep & 0x10;
12689       switch ((*codep & 0xf))
12690         {
12691         default:
12692           return &bad_opcode;
12693         case 0x1:
12694           vex_table_index = EVEX_0F;
12695           break;
12696         case 0x2:
12697           vex_table_index = EVEX_0F38;
12698           break;
12699         case 0x3:
12700           vex_table_index = EVEX_0F3A;
12701           break;
12702         }
12703
12704       /* The second byte after 0x62.  */
12705       codep++;
12706       vex.w = *codep & 0x80;
12707       if (vex.w && address_mode == mode_64bit)
12708         rex |= REX_W;
12709
12710       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12711       if (address_mode != mode_64bit)
12712         {
12713           /* In 16/32-bit mode silently ignore following bits.  */
12714           rex &= ~REX_B;
12715           vex.r = 1;
12716           vex.v = 1;
12717           vex.register_specifier &= 0x7;
12718         }
12719
12720       /* The U bit.  */
12721       if (!(*codep & 0x4))
12722         return &bad_opcode;
12723
12724       switch ((*codep & 0x3))
12725         {
12726         case 0:
12727           vex.prefix = 0;
12728           break;
12729         case 1:
12730           vex.prefix = DATA_PREFIX_OPCODE;
12731           break;
12732         case 2:
12733           vex.prefix = REPE_PREFIX_OPCODE;
12734           break;
12735         case 3:
12736           vex.prefix = REPNE_PREFIX_OPCODE;
12737           break;
12738         }
12739
12740       /* The third byte after 0x62.  */
12741       codep++;
12742
12743       /* Remember the static rounding bits.  */
12744       vex.ll = (*codep >> 5) & 3;
12745       vex.b = (*codep & 0x10) != 0;
12746
12747       vex.v = *codep & 0x8;
12748       vex.mask_register_specifier = *codep & 0x7;
12749       vex.zeroing = *codep & 0x80;
12750
12751       need_vex = 1;
12752       need_vex_reg = 1;
12753       codep++;
12754       vindex = *codep++;
12755       dp = &evex_table[vex_table_index][vindex];
12756       end_codep = codep;
12757       FETCH_DATA (info, codep + 1);
12758       modrm.mod = (*codep >> 6) & 3;
12759       modrm.reg = (*codep >> 3) & 7;
12760       modrm.rm = *codep & 7;
12761
12762       /* Set vector length.  */
12763       if (modrm.mod == 3 && vex.b)
12764         vex.length = 512;
12765       else
12766         {
12767           switch (vex.ll)
12768             {
12769             case 0x0:
12770               vex.length = 128;
12771               break;
12772             case 0x1:
12773               vex.length = 256;
12774               break;
12775             case 0x2:
12776               vex.length = 512;
12777               break;
12778             default:
12779               return &bad_opcode;
12780             }
12781         }
12782       break;
12783
12784     case 0:
12785       dp = &bad_opcode;
12786       break;
12787
12788     default:
12789       abort ();
12790     }
12791
12792   if (dp->name != NULL)
12793     return dp;
12794   else
12795     return get_valid_dis386 (dp, info);
12796 }
12797
12798 static void
12799 get_sib (disassemble_info *info, int sizeflag)
12800 {
12801   /* If modrm.mod == 3, operand must be register.  */
12802   if (need_modrm
12803       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12804       && modrm.mod != 3
12805       && modrm.rm == 4)
12806     {
12807       FETCH_DATA (info, codep + 2);
12808       sib.index = (codep [1] >> 3) & 7;
12809       sib.scale = (codep [1] >> 6) & 3;
12810       sib.base = codep [1] & 7;
12811     }
12812 }
12813
12814 static int
12815 print_insn (bfd_vma pc, disassemble_info *info)
12816 {
12817   const struct dis386 *dp;
12818   int i;
12819   char *op_txt[MAX_OPERANDS];
12820   int needcomma;
12821   int sizeflag, orig_sizeflag;
12822   const char *p;
12823   struct dis_private priv;
12824   int prefix_length;
12825
12826   priv.orig_sizeflag = AFLAG | DFLAG;
12827   if ((info->mach & bfd_mach_i386_i386) != 0)
12828     address_mode = mode_32bit;
12829   else if (info->mach == bfd_mach_i386_i8086)
12830     {
12831       address_mode = mode_16bit;
12832       priv.orig_sizeflag = 0;
12833     }
12834   else
12835     address_mode = mode_64bit;
12836
12837   if (intel_syntax == (char) -1)
12838     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12839
12840   for (p = info->disassembler_options; p != NULL; )
12841     {
12842       if (CONST_STRNEQ (p, "x86-64"))
12843         {
12844           address_mode = mode_64bit;
12845           priv.orig_sizeflag = AFLAG | DFLAG;
12846         }
12847       else if (CONST_STRNEQ (p, "i386"))
12848         {
12849           address_mode = mode_32bit;
12850           priv.orig_sizeflag = AFLAG | DFLAG;
12851         }
12852       else if (CONST_STRNEQ (p, "i8086"))
12853         {
12854           address_mode = mode_16bit;
12855           priv.orig_sizeflag = 0;
12856         }
12857       else if (CONST_STRNEQ (p, "intel"))
12858         {
12859           intel_syntax = 1;
12860           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12861             intel_mnemonic = 1;
12862         }
12863       else if (CONST_STRNEQ (p, "att"))
12864         {
12865           intel_syntax = 0;
12866           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12867             intel_mnemonic = 0;
12868         }
12869       else if (CONST_STRNEQ (p, "addr"))
12870         {
12871           if (address_mode == mode_64bit)
12872             {
12873               if (p[4] == '3' && p[5] == '2')
12874                 priv.orig_sizeflag &= ~AFLAG;
12875               else if (p[4] == '6' && p[5] == '4')
12876                 priv.orig_sizeflag |= AFLAG;
12877             }
12878           else
12879             {
12880               if (p[4] == '1' && p[5] == '6')
12881                 priv.orig_sizeflag &= ~AFLAG;
12882               else if (p[4] == '3' && p[5] == '2')
12883                 priv.orig_sizeflag |= AFLAG;
12884             }
12885         }
12886       else if (CONST_STRNEQ (p, "data"))
12887         {
12888           if (p[4] == '1' && p[5] == '6')
12889             priv.orig_sizeflag &= ~DFLAG;
12890           else if (p[4] == '3' && p[5] == '2')
12891             priv.orig_sizeflag |= DFLAG;
12892         }
12893       else if (CONST_STRNEQ (p, "suffix"))
12894         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12895
12896       p = strchr (p, ',');
12897       if (p != NULL)
12898         p++;
12899     }
12900
12901   if (intel_syntax)
12902     {
12903       names64 = intel_names64;
12904       names32 = intel_names32;
12905       names16 = intel_names16;
12906       names8 = intel_names8;
12907       names8rex = intel_names8rex;
12908       names_seg = intel_names_seg;
12909       names_mm = intel_names_mm;
12910       names_bnd = intel_names_bnd;
12911       names_xmm = intel_names_xmm;
12912       names_ymm = intel_names_ymm;
12913       names_zmm = intel_names_zmm;
12914       index64 = intel_index64;
12915       index32 = intel_index32;
12916       names_mask = intel_names_mask;
12917       index16 = intel_index16;
12918       open_char = '[';
12919       close_char = ']';
12920       separator_char = '+';
12921       scale_char = '*';
12922     }
12923   else
12924     {
12925       names64 = att_names64;
12926       names32 = att_names32;
12927       names16 = att_names16;
12928       names8 = att_names8;
12929       names8rex = att_names8rex;
12930       names_seg = att_names_seg;
12931       names_mm = att_names_mm;
12932       names_bnd = att_names_bnd;
12933       names_xmm = att_names_xmm;
12934       names_ymm = att_names_ymm;
12935       names_zmm = att_names_zmm;
12936       index64 = att_index64;
12937       index32 = att_index32;
12938       names_mask = att_names_mask;
12939       index16 = att_index16;
12940       open_char = '(';
12941       close_char =  ')';
12942       separator_char = ',';
12943       scale_char = ',';
12944     }
12945
12946   /* The output looks better if we put 7 bytes on a line, since that
12947      puts most long word instructions on a single line.  Use 8 bytes
12948      for Intel L1OM.  */
12949   if ((info->mach & bfd_mach_l1om) != 0)
12950     info->bytes_per_line = 8;
12951   else
12952     info->bytes_per_line = 7;
12953
12954   info->private_data = &priv;
12955   priv.max_fetched = priv.the_buffer;
12956   priv.insn_start = pc;
12957
12958   obuf[0] = 0;
12959   for (i = 0; i < MAX_OPERANDS; ++i)
12960     {
12961       op_out[i][0] = 0;
12962       op_index[i] = -1;
12963     }
12964
12965   the_info = info;
12966   start_pc = pc;
12967   start_codep = priv.the_buffer;
12968   codep = priv.the_buffer;
12969
12970   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12971     {
12972       const char *name;
12973
12974       /* Getting here means we tried for data but didn't get it.  That
12975          means we have an incomplete instruction of some sort.  Just
12976          print the first byte as a prefix or a .byte pseudo-op.  */
12977       if (codep > priv.the_buffer)
12978         {
12979           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12980           if (name != NULL)
12981             (*info->fprintf_func) (info->stream, "%s", name);
12982           else
12983             {
12984               /* Just print the first byte as a .byte instruction.  */
12985               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12986                                      (unsigned int) priv.the_buffer[0]);
12987             }
12988
12989           return 1;
12990         }
12991
12992       return -1;
12993     }
12994
12995   obufp = obuf;
12996   sizeflag = priv.orig_sizeflag;
12997
12998   if (!ckprefix () || rex_used)
12999     {
13000       /* Too many prefixes or unused REX prefixes.  */
13001       for (i = 0;
13002            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13003            i++)
13004         (*info->fprintf_func) (info->stream, "%s%s",
13005                                i == 0 ? "" : " ",
13006                                prefix_name (all_prefixes[i], sizeflag));
13007       return i;
13008     }
13009
13010   insn_codep = codep;
13011
13012   FETCH_DATA (info, codep + 1);
13013   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13014
13015   if (((prefixes & PREFIX_FWAIT)
13016        && ((*codep < 0xd8) || (*codep > 0xdf))))
13017     {
13018       /* Handle prefixes before fwait.  */
13019       for (i = 0; i < fwait_prefix && all_prefixes[i];
13020            i++)
13021         (*info->fprintf_func) (info->stream, "%s ",
13022                                prefix_name (all_prefixes[i], sizeflag));
13023       (*info->fprintf_func) (info->stream, "fwait");
13024       return i + 1;
13025     }
13026
13027   if (*codep == 0x0f)
13028     {
13029       unsigned char threebyte;
13030       FETCH_DATA (info, codep + 2);
13031       threebyte = *++codep;
13032       dp = &dis386_twobyte[threebyte];
13033       need_modrm = twobyte_has_modrm[*codep];
13034       mandatory_prefix = dp->prefix_requirement;
13035       codep++;
13036     }
13037   else
13038     {
13039       dp = &dis386[*codep];
13040       need_modrm = onebyte_has_modrm[*codep];
13041       mandatory_prefix = 0;
13042       codep++;
13043     }
13044
13045   /* Save sizeflag for printing the extra prefixes later before updating
13046      it for mnemonic and operand processing.  The prefix names depend
13047      only on the address mode.  */
13048   orig_sizeflag = sizeflag;
13049   if (prefixes & PREFIX_ADDR)
13050     sizeflag ^= AFLAG;
13051   if ((prefixes & PREFIX_DATA))
13052     sizeflag ^= DFLAG;
13053
13054   end_codep = codep;
13055   if (need_modrm)
13056     {
13057       FETCH_DATA (info, codep + 1);
13058       modrm.mod = (*codep >> 6) & 3;
13059       modrm.reg = (*codep >> 3) & 7;
13060       modrm.rm = *codep & 7;
13061     }
13062
13063   need_vex = 0;
13064   need_vex_reg = 0;
13065   vex_w_done = 0;
13066   vex.evex = 0;
13067
13068   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13069     {
13070       get_sib (info, sizeflag);
13071       dofloat (sizeflag);
13072     }
13073   else
13074     {
13075       dp = get_valid_dis386 (dp, info);
13076       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13077         {
13078           get_sib (info, sizeflag);
13079           for (i = 0; i < MAX_OPERANDS; ++i)
13080             {
13081               obufp = op_out[i];
13082               op_ad = MAX_OPERANDS - 1 - i;
13083               if (dp->op[i].rtn)
13084                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13085               /* For EVEX instruction after the last operand masking
13086                  should be printed.  */
13087               if (i == 0 && vex.evex)
13088                 {
13089                   /* Don't print {%k0}.  */
13090                   if (vex.mask_register_specifier)
13091                     {
13092                       oappend ("{");
13093                       oappend (names_mask[vex.mask_register_specifier]);
13094                       oappend ("}");
13095                     }
13096                   if (vex.zeroing)
13097                     oappend ("{z}");
13098                 }
13099             }
13100         }
13101     }
13102
13103   /* Check if the REX prefix is used.  */
13104   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13105     all_prefixes[last_rex_prefix] = 0;
13106
13107   /* Check if the SEG prefix is used.  */
13108   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13109                    | PREFIX_FS | PREFIX_GS)) != 0
13110       && (used_prefixes & active_seg_prefix) != 0)
13111     all_prefixes[last_seg_prefix] = 0;
13112
13113   /* Check if the ADDR prefix is used.  */
13114   if ((prefixes & PREFIX_ADDR) != 0
13115       && (used_prefixes & PREFIX_ADDR) != 0)
13116     all_prefixes[last_addr_prefix] = 0;
13117
13118   /* Check if the DATA prefix is used.  */
13119   if ((prefixes & PREFIX_DATA) != 0
13120       && (used_prefixes & PREFIX_DATA) != 0)
13121     all_prefixes[last_data_prefix] = 0;
13122
13123   /* Print the extra prefixes.  */
13124   prefix_length = 0;
13125   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13126     if (all_prefixes[i])
13127       {
13128         const char *name;
13129         name = prefix_name (all_prefixes[i], orig_sizeflag);
13130         if (name == NULL)
13131           abort ();
13132         prefix_length += strlen (name) + 1;
13133         (*info->fprintf_func) (info->stream, "%s ", name);
13134       }
13135
13136   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13137      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13138      used by putop and MMX/SSE operand and may be overriden by the
13139      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13140      separately.  */
13141   /* TODO we should check which prefix is mandatory.  */
13142   if (mandatory_prefix
13143       && dp != &bad_opcode
13144       && (((prefixes
13145             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13146            && (used_prefixes
13147                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13148           || ((((prefixes
13149                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13150                 == PREFIX_DATA)
13151                && (used_prefixes & PREFIX_DATA) == 0))))
13152     {
13153       (*info->fprintf_func) (info->stream, "(bad)");
13154       return end_codep - priv.the_buffer;
13155     }
13156
13157   /* Check maximum code length.  */
13158   if ((codep - start_codep) > MAX_CODE_LENGTH)
13159     {
13160       (*info->fprintf_func) (info->stream, "(bad)");
13161       return MAX_CODE_LENGTH;
13162     }
13163
13164   obufp = mnemonicendp;
13165   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13166     oappend (" ");
13167   oappend (" ");
13168   (*info->fprintf_func) (info->stream, "%s", obuf);
13169
13170   /* The enter and bound instructions are printed with operands in the same
13171      order as the intel book; everything else is printed in reverse order.  */
13172   if (intel_syntax || two_source_ops)
13173     {
13174       bfd_vma riprel;
13175
13176       for (i = 0; i < MAX_OPERANDS; ++i)
13177         op_txt[i] = op_out[i];
13178
13179       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13180         {
13181           op_ad = op_index[i];
13182           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13183           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13184           riprel = op_riprel[i];
13185           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13186           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13187         }
13188     }
13189   else
13190     {
13191       for (i = 0; i < MAX_OPERANDS; ++i)
13192         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13193     }
13194
13195   needcomma = 0;
13196   for (i = 0; i < MAX_OPERANDS; ++i)
13197     if (*op_txt[i])
13198       {
13199         if (needcomma)
13200           (*info->fprintf_func) (info->stream, ",");
13201         if (op_index[i] != -1 && !op_riprel[i])
13202           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13203         else
13204           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13205         needcomma = 1;
13206       }
13207
13208   for (i = 0; i < MAX_OPERANDS; i++)
13209     if (op_index[i] != -1 && op_riprel[i])
13210       {
13211         (*info->fprintf_func) (info->stream, "        # ");
13212         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13213                                                 + op_address[op_index[i]]), info);
13214         break;
13215       }
13216   return codep - priv.the_buffer;
13217 }
13218
13219 static const char *float_mem[] = {
13220   /* d8 */
13221   "fadd{s|}",
13222   "fmul{s|}",
13223   "fcom{s|}",
13224   "fcomp{s|}",
13225   "fsub{s|}",
13226   "fsubr{s|}",
13227   "fdiv{s|}",
13228   "fdivr{s|}",
13229   /* d9 */
13230   "fld{s|}",
13231   "(bad)",
13232   "fst{s|}",
13233   "fstp{s|}",
13234   "fldenvIC",
13235   "fldcw",
13236   "fNstenvIC",
13237   "fNstcw",
13238   /* da */
13239   "fiadd{l|}",
13240   "fimul{l|}",
13241   "ficom{l|}",
13242   "ficomp{l|}",
13243   "fisub{l|}",
13244   "fisubr{l|}",
13245   "fidiv{l|}",
13246   "fidivr{l|}",
13247   /* db */
13248   "fild{l|}",
13249   "fisttp{l|}",
13250   "fist{l|}",
13251   "fistp{l|}",
13252   "(bad)",
13253   "fld{t||t|}",
13254   "(bad)",
13255   "fstp{t||t|}",
13256   /* dc */
13257   "fadd{l|}",
13258   "fmul{l|}",
13259   "fcom{l|}",
13260   "fcomp{l|}",
13261   "fsub{l|}",
13262   "fsubr{l|}",
13263   "fdiv{l|}",
13264   "fdivr{l|}",
13265   /* dd */
13266   "fld{l|}",
13267   "fisttp{ll|}",
13268   "fst{l||}",
13269   "fstp{l|}",
13270   "frstorIC",
13271   "(bad)",
13272   "fNsaveIC",
13273   "fNstsw",
13274   /* de */
13275   "fiadd",
13276   "fimul",
13277   "ficom",
13278   "ficomp",
13279   "fisub",
13280   "fisubr",
13281   "fidiv",
13282   "fidivr",
13283   /* df */
13284   "fild",
13285   "fisttp",
13286   "fist",
13287   "fistp",
13288   "fbld",
13289   "fild{ll|}",
13290   "fbstp",
13291   "fistp{ll|}",
13292 };
13293
13294 static const unsigned char float_mem_mode[] = {
13295   /* d8 */
13296   d_mode,
13297   d_mode,
13298   d_mode,
13299   d_mode,
13300   d_mode,
13301   d_mode,
13302   d_mode,
13303   d_mode,
13304   /* d9 */
13305   d_mode,
13306   0,
13307   d_mode,
13308   d_mode,
13309   0,
13310   w_mode,
13311   0,
13312   w_mode,
13313   /* da */
13314   d_mode,
13315   d_mode,
13316   d_mode,
13317   d_mode,
13318   d_mode,
13319   d_mode,
13320   d_mode,
13321   d_mode,
13322   /* db */
13323   d_mode,
13324   d_mode,
13325   d_mode,
13326   d_mode,
13327   0,
13328   t_mode,
13329   0,
13330   t_mode,
13331   /* dc */
13332   q_mode,
13333   q_mode,
13334   q_mode,
13335   q_mode,
13336   q_mode,
13337   q_mode,
13338   q_mode,
13339   q_mode,
13340   /* dd */
13341   q_mode,
13342   q_mode,
13343   q_mode,
13344   q_mode,
13345   0,
13346   0,
13347   0,
13348   w_mode,
13349   /* de */
13350   w_mode,
13351   w_mode,
13352   w_mode,
13353   w_mode,
13354   w_mode,
13355   w_mode,
13356   w_mode,
13357   w_mode,
13358   /* df */
13359   w_mode,
13360   w_mode,
13361   w_mode,
13362   w_mode,
13363   t_mode,
13364   q_mode,
13365   t_mode,
13366   q_mode
13367 };
13368
13369 #define ST { OP_ST, 0 }
13370 #define STi { OP_STi, 0 }
13371
13372 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13373 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13374 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13375 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13376 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13377 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13378 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13379 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13380 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13381
13382 static const struct dis386 float_reg[][8] = {
13383   /* d8 */
13384   {
13385     { "fadd",   { ST, STi }, 0 },
13386     { "fmul",   { ST, STi }, 0 },
13387     { "fcom",   { STi }, 0 },
13388     { "fcomp",  { STi }, 0 },
13389     { "fsub",   { ST, STi }, 0 },
13390     { "fsubr",  { ST, STi }, 0 },
13391     { "fdiv",   { ST, STi }, 0 },
13392     { "fdivr",  { ST, STi }, 0 },
13393   },
13394   /* d9 */
13395   {
13396     { "fld",    { STi }, 0 },
13397     { "fxch",   { STi }, 0 },
13398     { FGRPd9_2 },
13399     { Bad_Opcode },
13400     { FGRPd9_4 },
13401     { FGRPd9_5 },
13402     { FGRPd9_6 },
13403     { FGRPd9_7 },
13404   },
13405   /* da */
13406   {
13407     { "fcmovb", { ST, STi }, 0 },
13408     { "fcmove", { ST, STi }, 0 },
13409     { "fcmovbe",{ ST, STi }, 0 },
13410     { "fcmovu", { ST, STi }, 0 },
13411     { Bad_Opcode },
13412     { FGRPda_5 },
13413     { Bad_Opcode },
13414     { Bad_Opcode },
13415   },
13416   /* db */
13417   {
13418     { "fcmovnb",{ ST, STi }, 0 },
13419     { "fcmovne",{ ST, STi }, 0 },
13420     { "fcmovnbe",{ ST, STi }, 0 },
13421     { "fcmovnu",{ ST, STi }, 0 },
13422     { FGRPdb_4 },
13423     { "fucomi", { ST, STi }, 0 },
13424     { "fcomi",  { ST, STi }, 0 },
13425     { Bad_Opcode },
13426   },
13427   /* dc */
13428   {
13429     { "fadd",   { STi, ST }, 0 },
13430     { "fmul",   { STi, ST }, 0 },
13431     { Bad_Opcode },
13432     { Bad_Opcode },
13433     { "fsub!M", { STi, ST }, 0 },
13434     { "fsubM",  { STi, ST }, 0 },
13435     { "fdiv!M", { STi, ST }, 0 },
13436     { "fdivM",  { STi, ST }, 0 },
13437   },
13438   /* dd */
13439   {
13440     { "ffree",  { STi }, 0 },
13441     { Bad_Opcode },
13442     { "fst",    { STi }, 0 },
13443     { "fstp",   { STi }, 0 },
13444     { "fucom",  { STi }, 0 },
13445     { "fucomp", { STi }, 0 },
13446     { Bad_Opcode },
13447     { Bad_Opcode },
13448   },
13449   /* de */
13450   {
13451     { "faddp",  { STi, ST }, 0 },
13452     { "fmulp",  { STi, ST }, 0 },
13453     { Bad_Opcode },
13454     { FGRPde_3 },
13455     { "fsub!Mp", { STi, ST }, 0 },
13456     { "fsubMp", { STi, ST }, 0 },
13457     { "fdiv!Mp", { STi, ST }, 0 },
13458     { "fdivMp", { STi, ST }, 0 },
13459   },
13460   /* df */
13461   {
13462     { "ffreep", { STi }, 0 },
13463     { Bad_Opcode },
13464     { Bad_Opcode },
13465     { Bad_Opcode },
13466     { FGRPdf_4 },
13467     { "fucomip", { ST, STi }, 0 },
13468     { "fcomip", { ST, STi }, 0 },
13469     { Bad_Opcode },
13470   },
13471 };
13472
13473 static char *fgrps[][8] = {
13474   /* d9_2  0 */
13475   {
13476     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13477   },
13478
13479   /* d9_4  1 */
13480   {
13481     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13482   },
13483
13484   /* d9_5  2 */
13485   {
13486     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13487   },
13488
13489   /* d9_6  3 */
13490   {
13491     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13492   },
13493
13494   /* d9_7  4 */
13495   {
13496     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13497   },
13498
13499   /* da_5  5 */
13500   {
13501     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13502   },
13503
13504   /* db_4  6 */
13505   {
13506     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13507     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13508   },
13509
13510   /* de_3  7 */
13511   {
13512     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13513   },
13514
13515   /* df_4  8 */
13516   {
13517     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13518   },
13519 };
13520
13521 static void
13522 swap_operand (void)
13523 {
13524   mnemonicendp[0] = '.';
13525   mnemonicendp[1] = 's';
13526   mnemonicendp += 2;
13527 }
13528
13529 static void
13530 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13531                int sizeflag ATTRIBUTE_UNUSED)
13532 {
13533   /* Skip mod/rm byte.  */
13534   MODRM_CHECK;
13535   codep++;
13536 }
13537
13538 static void
13539 dofloat (int sizeflag)
13540 {
13541   const struct dis386 *dp;
13542   unsigned char floatop;
13543
13544   floatop = codep[-1];
13545
13546   if (modrm.mod != 3)
13547     {
13548       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13549
13550       putop (float_mem[fp_indx], sizeflag);
13551       obufp = op_out[0];
13552       op_ad = 2;
13553       OP_E (float_mem_mode[fp_indx], sizeflag);
13554       return;
13555     }
13556   /* Skip mod/rm byte.  */
13557   MODRM_CHECK;
13558   codep++;
13559
13560   dp = &float_reg[floatop - 0xd8][modrm.reg];
13561   if (dp->name == NULL)
13562     {
13563       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13564
13565       /* Instruction fnstsw is only one with strange arg.  */
13566       if (floatop == 0xdf && codep[-1] == 0xe0)
13567         strcpy (op_out[0], names16[0]);
13568     }
13569   else
13570     {
13571       putop (dp->name, sizeflag);
13572
13573       obufp = op_out[0];
13574       op_ad = 2;
13575       if (dp->op[0].rtn)
13576         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13577
13578       obufp = op_out[1];
13579       op_ad = 1;
13580       if (dp->op[1].rtn)
13581         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13582     }
13583 }
13584
13585 /* Like oappend (below), but S is a string starting with '%'.
13586    In Intel syntax, the '%' is elided.  */
13587 static void
13588 oappend_maybe_intel (const char *s)
13589 {
13590   oappend (s + intel_syntax);
13591 }
13592
13593 static void
13594 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13595 {
13596   oappend_maybe_intel ("%st");
13597 }
13598
13599 static void
13600 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13601 {
13602   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13603   oappend_maybe_intel (scratchbuf);
13604 }
13605
13606 /* Capital letters in template are macros.  */
13607 static int
13608 putop (const char *in_template, int sizeflag)
13609 {
13610   const char *p;
13611   int alt = 0;
13612   int cond = 1;
13613   unsigned int l = 0, len = 1;
13614   char last[4];
13615
13616 #define SAVE_LAST(c)                    \
13617   if (l < len && l < sizeof (last))     \
13618     last[l++] = c;                      \
13619   else                                  \
13620     abort ();
13621
13622   for (p = in_template; *p; p++)
13623     {
13624       switch (*p)
13625         {
13626         default:
13627           *obufp++ = *p;
13628           break;
13629         case '%':
13630           len++;
13631           break;
13632         case '!':
13633           cond = 0;
13634           break;
13635         case '{':
13636           alt = 0;
13637           if (intel_syntax)
13638             {
13639               while (*++p != '|')
13640                 if (*p == '}' || *p == '\0')
13641                   abort ();
13642             }
13643           /* Fall through.  */
13644         case 'I':
13645           alt = 1;
13646           continue;
13647         case '|':
13648           while (*++p != '}')
13649             {
13650               if (*p == '\0')
13651                 abort ();
13652             }
13653           break;
13654         case '}':
13655           break;
13656         case 'A':
13657           if (intel_syntax)
13658             break;
13659           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13660             *obufp++ = 'b';
13661           break;
13662         case 'B':
13663           if (l == 0 && len == 1)
13664             {
13665 case_B:
13666               if (intel_syntax)
13667                 break;
13668               if (sizeflag & SUFFIX_ALWAYS)
13669                 *obufp++ = 'b';
13670             }
13671           else
13672             {
13673               if (l != 1
13674                   || len != 2
13675                   || last[0] != 'L')
13676                 {
13677                   SAVE_LAST (*p);
13678                   break;
13679                 }
13680
13681               if (address_mode == mode_64bit
13682                   && !(prefixes & PREFIX_ADDR))
13683                 {
13684                   *obufp++ = 'a';
13685                   *obufp++ = 'b';
13686                   *obufp++ = 's';
13687                 }
13688
13689               goto case_B;
13690             }
13691           break;
13692         case 'C':
13693           if (intel_syntax && !alt)
13694             break;
13695           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13696             {
13697               if (sizeflag & DFLAG)
13698                 *obufp++ = intel_syntax ? 'd' : 'l';
13699               else
13700                 *obufp++ = intel_syntax ? 'w' : 's';
13701               used_prefixes |= (prefixes & PREFIX_DATA);
13702             }
13703           break;
13704         case 'D':
13705           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13706             break;
13707           USED_REX (REX_W);
13708           if (modrm.mod == 3)
13709             {
13710               if (rex & REX_W)
13711                 *obufp++ = 'q';
13712               else
13713                 {
13714                   if (sizeflag & DFLAG)
13715                     *obufp++ = intel_syntax ? 'd' : 'l';
13716                   else
13717                     *obufp++ = 'w';
13718                   used_prefixes |= (prefixes & PREFIX_DATA);
13719                 }
13720             }
13721           else
13722             *obufp++ = 'w';
13723           break;
13724         case 'E':               /* For jcxz/jecxz */
13725           if (address_mode == mode_64bit)
13726             {
13727               if (sizeflag & AFLAG)
13728                 *obufp++ = 'r';
13729               else
13730                 *obufp++ = 'e';
13731             }
13732           else
13733             if (sizeflag & AFLAG)
13734               *obufp++ = 'e';
13735           used_prefixes |= (prefixes & PREFIX_ADDR);
13736           break;
13737         case 'F':
13738           if (intel_syntax)
13739             break;
13740           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13741             {
13742               if (sizeflag & AFLAG)
13743                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13744               else
13745                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13746               used_prefixes |= (prefixes & PREFIX_ADDR);
13747             }
13748           break;
13749         case 'G':
13750           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13751             break;
13752           if ((rex & REX_W) || (sizeflag & DFLAG))
13753             *obufp++ = 'l';
13754           else
13755             *obufp++ = 'w';
13756           if (!(rex & REX_W))
13757             used_prefixes |= (prefixes & PREFIX_DATA);
13758           break;
13759         case 'H':
13760           if (intel_syntax)
13761             break;
13762           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13763               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13764             {
13765               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13766               *obufp++ = ',';
13767               *obufp++ = 'p';
13768               if (prefixes & PREFIX_DS)
13769                 *obufp++ = 't';
13770               else
13771                 *obufp++ = 'n';
13772             }
13773           break;
13774         case 'J':
13775           if (intel_syntax)
13776             break;
13777           *obufp++ = 'l';
13778           break;
13779         case 'K':
13780           USED_REX (REX_W);
13781           if (rex & REX_W)
13782             *obufp++ = 'q';
13783           else
13784             *obufp++ = 'd';
13785           break;
13786         case 'Z':
13787           if (intel_syntax)
13788             break;
13789           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13790             {
13791               *obufp++ = 'q';
13792               break;
13793             }
13794           /* Fall through.  */
13795           goto case_L;
13796         case 'L':
13797           if (l != 0 || len != 1)
13798             {
13799               SAVE_LAST (*p);
13800               break;
13801             }
13802 case_L:
13803           if (intel_syntax)
13804             break;
13805           if (sizeflag & SUFFIX_ALWAYS)
13806             *obufp++ = 'l';
13807           break;
13808         case 'M':
13809           if (intel_mnemonic != cond)
13810             *obufp++ = 'r';
13811           break;
13812         case 'N':
13813           if ((prefixes & PREFIX_FWAIT) == 0)
13814             *obufp++ = 'n';
13815           else
13816             used_prefixes |= PREFIX_FWAIT;
13817           break;
13818         case 'O':
13819           USED_REX (REX_W);
13820           if (rex & REX_W)
13821             *obufp++ = 'o';
13822           else if (intel_syntax && (sizeflag & DFLAG))
13823             *obufp++ = 'q';
13824           else
13825             *obufp++ = 'd';
13826           if (!(rex & REX_W))
13827             used_prefixes |= (prefixes & PREFIX_DATA);
13828           break;
13829         case 'T':
13830           if (!intel_syntax
13831               && address_mode == mode_64bit
13832               && ((sizeflag & DFLAG) || (rex & REX_W)))
13833             {
13834               *obufp++ = 'q';
13835               break;
13836             }
13837           /* Fall through.  */
13838           goto case_P;
13839         case 'P':
13840           if (l == 0 && len == 1)
13841             {
13842 case_P:
13843               if (intel_syntax)
13844                 {
13845                   if ((rex & REX_W) == 0
13846                       && (prefixes & PREFIX_DATA))
13847                     {
13848                       if ((sizeflag & DFLAG) == 0)
13849                         *obufp++ = 'w';
13850                       used_prefixes |= (prefixes & PREFIX_DATA);
13851                     }
13852                   break;
13853                 }
13854               if ((prefixes & PREFIX_DATA)
13855                   || (rex & REX_W)
13856                   || (sizeflag & SUFFIX_ALWAYS))
13857                 {
13858                   USED_REX (REX_W);
13859                   if (rex & REX_W)
13860                     *obufp++ = 'q';
13861                   else
13862                     {
13863                       if (sizeflag & DFLAG)
13864                         *obufp++ = 'l';
13865                       else
13866                         *obufp++ = 'w';
13867                       used_prefixes |= (prefixes & PREFIX_DATA);
13868                     }
13869                 }
13870             }
13871           else
13872             {
13873               if (l != 1 || len != 2 || last[0] != 'L')
13874                 {
13875                   SAVE_LAST (*p);
13876                   break;
13877                 }
13878
13879               if ((prefixes & PREFIX_DATA)
13880                   || (rex & REX_W)
13881                   || (sizeflag & SUFFIX_ALWAYS))
13882                 {
13883                   USED_REX (REX_W);
13884                   if (rex & REX_W)
13885                     *obufp++ = 'q';
13886                   else
13887                     {
13888                       if (sizeflag & DFLAG)
13889                         *obufp++ = intel_syntax ? 'd' : 'l';
13890                       else
13891                         *obufp++ = 'w';
13892                       used_prefixes |= (prefixes & PREFIX_DATA);
13893                     }
13894                 }
13895             }
13896           break;
13897         case 'U':
13898           if (intel_syntax)
13899             break;
13900           if (address_mode == mode_64bit
13901               && ((sizeflag & DFLAG) || (rex & REX_W)))
13902             {
13903               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13904                 *obufp++ = 'q';
13905               break;
13906             }
13907           /* Fall through.  */
13908           goto case_Q;
13909         case 'Q':
13910           if (l == 0 && len == 1)
13911             {
13912 case_Q:
13913               if (intel_syntax && !alt)
13914                 break;
13915               USED_REX (REX_W);
13916               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13917                 {
13918                   if (rex & REX_W)
13919                     *obufp++ = 'q';
13920                   else
13921                     {
13922                       if (sizeflag & DFLAG)
13923                         *obufp++ = intel_syntax ? 'd' : 'l';
13924                       else
13925                         *obufp++ = 'w';
13926                       used_prefixes |= (prefixes & PREFIX_DATA);
13927                     }
13928                 }
13929             }
13930           else
13931             {
13932               if (l != 1 || len != 2 || last[0] != 'L')
13933                 {
13934                   SAVE_LAST (*p);
13935                   break;
13936                 }
13937               if (intel_syntax
13938                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13939                 break;
13940               if ((rex & REX_W))
13941                 {
13942                   USED_REX (REX_W);
13943                   *obufp++ = 'q';
13944                 }
13945               else
13946                 *obufp++ = 'l';
13947             }
13948           break;
13949         case 'R':
13950           USED_REX (REX_W);
13951           if (rex & REX_W)
13952             *obufp++ = 'q';
13953           else if (sizeflag & DFLAG)
13954             {
13955               if (intel_syntax)
13956                   *obufp++ = 'd';
13957               else
13958                   *obufp++ = 'l';
13959             }
13960           else
13961             *obufp++ = 'w';
13962           if (intel_syntax && !p[1]
13963               && ((rex & REX_W) || (sizeflag & DFLAG)))
13964             *obufp++ = 'e';
13965           if (!(rex & REX_W))
13966             used_prefixes |= (prefixes & PREFIX_DATA);
13967           break;
13968         case 'V':
13969           if (l == 0 && len == 1)
13970             {
13971               if (intel_syntax)
13972                 break;
13973               if (address_mode == mode_64bit
13974                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13975                 {
13976                   if (sizeflag & SUFFIX_ALWAYS)
13977                     *obufp++ = 'q';
13978                   break;
13979                 }
13980             }
13981           else
13982             {
13983               if (l != 1
13984                   || len != 2
13985                   || last[0] != 'L')
13986                 {
13987                   SAVE_LAST (*p);
13988                   break;
13989                 }
13990
13991               if (rex & REX_W)
13992                 {
13993                   *obufp++ = 'a';
13994                   *obufp++ = 'b';
13995                   *obufp++ = 's';
13996                 }
13997             }
13998           /* Fall through.  */
13999           goto case_S;
14000         case 'S':
14001           if (l == 0 && len == 1)
14002             {
14003 case_S:
14004               if (intel_syntax)
14005                 break;
14006               if (sizeflag & SUFFIX_ALWAYS)
14007                 {
14008                   if (rex & REX_W)
14009                     *obufp++ = 'q';
14010                   else
14011                     {
14012                       if (sizeflag & DFLAG)
14013                         *obufp++ = 'l';
14014                       else
14015                         *obufp++ = 'w';
14016                       used_prefixes |= (prefixes & PREFIX_DATA);
14017                     }
14018                 }
14019             }
14020           else
14021             {
14022               if (l != 1
14023                   || len != 2
14024                   || last[0] != 'L')
14025                 {
14026                   SAVE_LAST (*p);
14027                   break;
14028                 }
14029
14030               if (address_mode == mode_64bit
14031                   && !(prefixes & PREFIX_ADDR))
14032                 {
14033                   *obufp++ = 'a';
14034                   *obufp++ = 'b';
14035                   *obufp++ = 's';
14036                 }
14037
14038               goto case_S;
14039             }
14040           break;
14041         case 'X':
14042           if (l != 0 || len != 1)
14043             {
14044               SAVE_LAST (*p);
14045               break;
14046             }
14047           if (need_vex && vex.prefix)
14048             {
14049               if (vex.prefix == DATA_PREFIX_OPCODE)
14050                 *obufp++ = 'd';
14051               else
14052                 *obufp++ = 's';
14053             }
14054           else
14055             {
14056               if (prefixes & PREFIX_DATA)
14057                 *obufp++ = 'd';
14058               else
14059                 *obufp++ = 's';
14060               used_prefixes |= (prefixes & PREFIX_DATA);
14061             }
14062           break;
14063         case 'Y':
14064           if (l == 0 && len == 1)
14065             {
14066               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14067                 break;
14068               if (rex & REX_W)
14069                 {
14070                   USED_REX (REX_W);
14071                   *obufp++ = 'q';
14072                 }
14073               break;
14074             }
14075           else
14076             {
14077               if (l != 1 || len != 2 || last[0] != 'X')
14078                 {
14079                   SAVE_LAST (*p);
14080                   break;
14081                 }
14082               if (!need_vex)
14083                 abort ();
14084               if (intel_syntax
14085                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14086                 break;
14087               switch (vex.length)
14088                 {
14089                 case 128:
14090                   *obufp++ = 'x';
14091                   break;
14092                 case 256:
14093                   *obufp++ = 'y';
14094                   break;
14095                 default:
14096                   abort ();
14097                 }
14098             }
14099           break;
14100         case 'W':
14101           if (l == 0 && len == 1)
14102             {
14103               /* operand size flag for cwtl, cbtw */
14104               USED_REX (REX_W);
14105               if (rex & REX_W)
14106                 {
14107                   if (intel_syntax)
14108                     *obufp++ = 'd';
14109                   else
14110                     *obufp++ = 'l';
14111                 }
14112               else if (sizeflag & DFLAG)
14113                 *obufp++ = 'w';
14114               else
14115                 *obufp++ = 'b';
14116               if (!(rex & REX_W))
14117                 used_prefixes |= (prefixes & PREFIX_DATA);
14118             }
14119           else
14120             {
14121               if (l != 1
14122                   || len != 2
14123                   || (last[0] != 'X'
14124                       && last[0] != 'L'))
14125                 {
14126                   SAVE_LAST (*p);
14127                   break;
14128                 }
14129               if (!need_vex)
14130                 abort ();
14131               if (last[0] == 'X')
14132                 *obufp++ = vex.w ? 'd': 's';
14133               else
14134                 *obufp++ = vex.w ? 'q': 'd';
14135             }
14136           break;
14137         }
14138       alt = 0;
14139     }
14140   *obufp = 0;
14141   mnemonicendp = obufp;
14142   return 0;
14143 }
14144
14145 static void
14146 oappend (const char *s)
14147 {
14148   obufp = stpcpy (obufp, s);
14149 }
14150
14151 static void
14152 append_seg (void)
14153 {
14154   /* Only print the active segment register.  */
14155   if (!active_seg_prefix)
14156     return;
14157
14158   used_prefixes |= active_seg_prefix;
14159   switch (active_seg_prefix)
14160     {
14161     case PREFIX_CS:
14162       oappend_maybe_intel ("%cs:");
14163       break;
14164     case PREFIX_DS:
14165       oappend_maybe_intel ("%ds:");
14166       break;
14167     case PREFIX_SS:
14168       oappend_maybe_intel ("%ss:");
14169       break;
14170     case PREFIX_ES:
14171       oappend_maybe_intel ("%es:");
14172       break;
14173     case PREFIX_FS:
14174       oappend_maybe_intel ("%fs:");
14175       break;
14176     case PREFIX_GS:
14177       oappend_maybe_intel ("%gs:");
14178       break;
14179     default:
14180       break;
14181     }
14182 }
14183
14184 static void
14185 OP_indirE (int bytemode, int sizeflag)
14186 {
14187   if (!intel_syntax)
14188     oappend ("*");
14189   OP_E (bytemode, sizeflag);
14190 }
14191
14192 static void
14193 print_operand_value (char *buf, int hex, bfd_vma disp)
14194 {
14195   if (address_mode == mode_64bit)
14196     {
14197       if (hex)
14198         {
14199           char tmp[30];
14200           int i;
14201           buf[0] = '0';
14202           buf[1] = 'x';
14203           sprintf_vma (tmp, disp);
14204           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14205           strcpy (buf + 2, tmp + i);
14206         }
14207       else
14208         {
14209           bfd_signed_vma v = disp;
14210           char tmp[30];
14211           int i;
14212           if (v < 0)
14213             {
14214               *(buf++) = '-';
14215               v = -disp;
14216               /* Check for possible overflow on 0x8000000000000000.  */
14217               if (v < 0)
14218                 {
14219                   strcpy (buf, "9223372036854775808");
14220                   return;
14221                 }
14222             }
14223           if (!v)
14224             {
14225               strcpy (buf, "0");
14226               return;
14227             }
14228
14229           i = 0;
14230           tmp[29] = 0;
14231           while (v)
14232             {
14233               tmp[28 - i] = (v % 10) + '0';
14234               v /= 10;
14235               i++;
14236             }
14237           strcpy (buf, tmp + 29 - i);
14238         }
14239     }
14240   else
14241     {
14242       if (hex)
14243         sprintf (buf, "0x%x", (unsigned int) disp);
14244       else
14245         sprintf (buf, "%d", (int) disp);
14246     }
14247 }
14248
14249 /* Put DISP in BUF as signed hex number.  */
14250
14251 static void
14252 print_displacement (char *buf, bfd_vma disp)
14253 {
14254   bfd_signed_vma val = disp;
14255   char tmp[30];
14256   int i, j = 0;
14257
14258   if (val < 0)
14259     {
14260       buf[j++] = '-';
14261       val = -disp;
14262
14263       /* Check for possible overflow.  */
14264       if (val < 0)
14265         {
14266           switch (address_mode)
14267             {
14268             case mode_64bit:
14269               strcpy (buf + j, "0x8000000000000000");
14270               break;
14271             case mode_32bit:
14272               strcpy (buf + j, "0x80000000");
14273               break;
14274             case mode_16bit:
14275               strcpy (buf + j, "0x8000");
14276               break;
14277             }
14278           return;
14279         }
14280     }
14281
14282   buf[j++] = '0';
14283   buf[j++] = 'x';
14284
14285   sprintf_vma (tmp, (bfd_vma) val);
14286   for (i = 0; tmp[i] == '0'; i++)
14287     continue;
14288   if (tmp[i] == '\0')
14289     i--;
14290   strcpy (buf + j, tmp + i);
14291 }
14292
14293 static void
14294 intel_operand_size (int bytemode, int sizeflag)
14295 {
14296   if (vex.evex
14297       && vex.b
14298       && (bytemode == x_mode
14299           || bytemode == evex_half_bcst_xmmq_mode))
14300     {
14301       if (vex.w)
14302         oappend ("QWORD PTR ");
14303       else
14304         oappend ("DWORD PTR ");
14305       return;
14306     }
14307   switch (bytemode)
14308     {
14309     case b_mode:
14310     case b_swap_mode:
14311     case dqb_mode:
14312     case db_mode:
14313       oappend ("BYTE PTR ");
14314       break;
14315     case w_mode:
14316     case dw_mode:
14317     case dqw_mode:
14318     case dqw_swap_mode:
14319       oappend ("WORD PTR ");
14320       break;
14321     case stack_v_mode:
14322       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14323         {
14324           oappend ("QWORD PTR ");
14325           break;
14326         }
14327       /* FALLTHRU */
14328     case v_mode:
14329     case v_swap_mode:
14330     case dq_mode:
14331       USED_REX (REX_W);
14332       if (rex & REX_W)
14333         oappend ("QWORD PTR ");
14334       else
14335         {
14336           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14337             oappend ("DWORD PTR ");
14338           else
14339             oappend ("WORD PTR ");
14340           used_prefixes |= (prefixes & PREFIX_DATA);
14341         }
14342       break;
14343     case z_mode:
14344       if ((rex & REX_W) || (sizeflag & DFLAG))
14345         *obufp++ = 'D';
14346       oappend ("WORD PTR ");
14347       if (!(rex & REX_W))
14348         used_prefixes |= (prefixes & PREFIX_DATA);
14349       break;
14350     case a_mode:
14351       if (sizeflag & DFLAG)
14352         oappend ("QWORD PTR ");
14353       else
14354         oappend ("DWORD PTR ");
14355       used_prefixes |= (prefixes & PREFIX_DATA);
14356       break;
14357     case d_mode:
14358     case d_scalar_mode:
14359     case d_scalar_swap_mode:
14360     case d_swap_mode:
14361     case dqd_mode:
14362       oappend ("DWORD PTR ");
14363       break;
14364     case q_mode:
14365     case q_scalar_mode:
14366     case q_scalar_swap_mode:
14367     case q_swap_mode:
14368       oappend ("QWORD PTR ");
14369       break;
14370     case m_mode:
14371       if (address_mode == mode_64bit)
14372         oappend ("QWORD PTR ");
14373       else
14374         oappend ("DWORD PTR ");
14375       break;
14376     case f_mode:
14377       if (sizeflag & DFLAG)
14378         oappend ("FWORD PTR ");
14379       else
14380         oappend ("DWORD PTR ");
14381       used_prefixes |= (prefixes & PREFIX_DATA);
14382       break;
14383     case t_mode:
14384       oappend ("TBYTE PTR ");
14385       break;
14386     case x_mode:
14387     case x_swap_mode:
14388     case evex_x_gscat_mode:
14389     case evex_x_nobcst_mode:
14390       if (need_vex)
14391         {
14392           switch (vex.length)
14393             {
14394             case 128:
14395               oappend ("XMMWORD PTR ");
14396               break;
14397             case 256:
14398               oappend ("YMMWORD PTR ");
14399               break;
14400             case 512:
14401               oappend ("ZMMWORD PTR ");
14402               break;
14403             default:
14404               abort ();
14405             }
14406         }
14407       else
14408         oappend ("XMMWORD PTR ");
14409       break;
14410     case xmm_mode:
14411       oappend ("XMMWORD PTR ");
14412       break;
14413     case ymm_mode:
14414       oappend ("YMMWORD PTR ");
14415       break;
14416     case xmmq_mode:
14417     case evex_half_bcst_xmmq_mode:
14418       if (!need_vex)
14419         abort ();
14420
14421       switch (vex.length)
14422         {
14423         case 128:
14424           oappend ("QWORD PTR ");
14425           break;
14426         case 256:
14427           oappend ("XMMWORD PTR ");
14428           break;
14429         case 512:
14430           oappend ("YMMWORD PTR ");
14431           break;
14432         default:
14433           abort ();
14434         }
14435       break;
14436     case xmm_mb_mode:
14437       if (!need_vex)
14438         abort ();
14439
14440       switch (vex.length)
14441         {
14442         case 128:
14443         case 256:
14444         case 512:
14445           oappend ("BYTE PTR ");
14446           break;
14447         default:
14448           abort ();
14449         }
14450       break;
14451     case xmm_mw_mode:
14452       if (!need_vex)
14453         abort ();
14454
14455       switch (vex.length)
14456         {
14457         case 128:
14458         case 256:
14459         case 512:
14460           oappend ("WORD PTR ");
14461           break;
14462         default:
14463           abort ();
14464         }
14465       break;
14466     case xmm_md_mode:
14467       if (!need_vex)
14468         abort ();
14469
14470       switch (vex.length)
14471         {
14472         case 128:
14473         case 256:
14474         case 512:
14475           oappend ("DWORD PTR ");
14476           break;
14477         default:
14478           abort ();
14479         }
14480       break;
14481     case xmm_mq_mode:
14482       if (!need_vex)
14483         abort ();
14484
14485       switch (vex.length)
14486         {
14487         case 128:
14488         case 256:
14489         case 512:
14490           oappend ("QWORD PTR ");
14491           break;
14492         default:
14493           abort ();
14494         }
14495       break;
14496     case xmmdw_mode:
14497       if (!need_vex)
14498         abort ();
14499
14500       switch (vex.length)
14501         {
14502         case 128:
14503           oappend ("WORD PTR ");
14504           break;
14505         case 256:
14506           oappend ("DWORD PTR ");
14507           break;
14508         case 512:
14509           oappend ("QWORD PTR ");
14510           break;
14511         default:
14512           abort ();
14513         }
14514       break;
14515     case xmmqd_mode:
14516       if (!need_vex)
14517         abort ();
14518
14519       switch (vex.length)
14520         {
14521         case 128:
14522           oappend ("DWORD PTR ");
14523           break;
14524         case 256:
14525           oappend ("QWORD PTR ");
14526           break;
14527         case 512:
14528           oappend ("XMMWORD PTR ");
14529           break;
14530         default:
14531           abort ();
14532         }
14533       break;
14534     case ymmq_mode:
14535       if (!need_vex)
14536         abort ();
14537
14538       switch (vex.length)
14539         {
14540         case 128:
14541           oappend ("QWORD PTR ");
14542           break;
14543         case 256:
14544           oappend ("YMMWORD PTR ");
14545           break;
14546         case 512:
14547           oappend ("ZMMWORD PTR ");
14548           break;
14549         default:
14550           abort ();
14551         }
14552       break;
14553     case ymmxmm_mode:
14554       if (!need_vex)
14555         abort ();
14556
14557       switch (vex.length)
14558         {
14559         case 128:
14560         case 256:
14561           oappend ("XMMWORD PTR ");
14562           break;
14563         default:
14564           abort ();
14565         }
14566       break;
14567     case o_mode:
14568       oappend ("OWORD PTR ");
14569       break;
14570     case xmm_mdq_mode:
14571     case vex_w_dq_mode:
14572     case vex_scalar_w_dq_mode:
14573       if (!need_vex)
14574         abort ();
14575
14576       if (vex.w)
14577         oappend ("QWORD PTR ");
14578       else
14579         oappend ("DWORD PTR ");
14580       break;
14581     case vex_vsib_d_w_dq_mode:
14582     case vex_vsib_q_w_dq_mode:
14583       if (!need_vex)
14584         abort ();
14585
14586       if (!vex.evex)
14587         {
14588           if (vex.w)
14589             oappend ("QWORD PTR ");
14590           else
14591             oappend ("DWORD PTR ");
14592         }
14593       else
14594         {
14595           switch (vex.length)
14596             {
14597             case 128:
14598               oappend ("XMMWORD PTR ");
14599               break;
14600             case 256:
14601               oappend ("YMMWORD PTR ");
14602               break;
14603             case 512:
14604               oappend ("ZMMWORD PTR ");
14605               break;
14606             default:
14607               abort ();
14608             }
14609         }
14610       break;
14611     case vex_vsib_q_w_d_mode:
14612     case vex_vsib_d_w_d_mode:
14613       if (!need_vex || !vex.evex)
14614         abort ();
14615
14616       switch (vex.length)
14617         {
14618         case 128:
14619           oappend ("QWORD PTR ");
14620           break;
14621         case 256:
14622           oappend ("XMMWORD PTR ");
14623           break;
14624         case 512:
14625           oappend ("YMMWORD PTR ");
14626           break;
14627         default:
14628           abort ();
14629         }
14630
14631       break;
14632     case mask_bd_mode:
14633       if (!need_vex || vex.length != 128)
14634         abort ();
14635       if (vex.w)
14636         oappend ("DWORD PTR ");
14637       else
14638         oappend ("BYTE PTR ");
14639       break;
14640     case mask_mode:
14641       if (!need_vex)
14642         abort ();
14643       if (vex.w)
14644         oappend ("QWORD PTR ");
14645       else
14646         oappend ("WORD PTR ");
14647       break;
14648     case v_bnd_mode:
14649     default:
14650       break;
14651     }
14652 }
14653
14654 static void
14655 OP_E_register (int bytemode, int sizeflag)
14656 {
14657   int reg = modrm.rm;
14658   const char **names;
14659
14660   USED_REX (REX_B);
14661   if ((rex & REX_B))
14662     reg += 8;
14663
14664   if ((sizeflag & SUFFIX_ALWAYS)
14665       && (bytemode == b_swap_mode
14666           || bytemode == v_swap_mode
14667           || bytemode == dqw_swap_mode))
14668     swap_operand ();
14669
14670   switch (bytemode)
14671     {
14672     case b_mode:
14673     case b_swap_mode:
14674       USED_REX (0);
14675       if (rex)
14676         names = names8rex;
14677       else
14678         names = names8;
14679       break;
14680     case w_mode:
14681       names = names16;
14682       break;
14683     case d_mode:
14684     case dw_mode:
14685     case db_mode:
14686       names = names32;
14687       break;
14688     case q_mode:
14689       names = names64;
14690       break;
14691     case m_mode:
14692     case v_bnd_mode:
14693       names = address_mode == mode_64bit ? names64 : names32;
14694       break;
14695     case bnd_mode:
14696       names = names_bnd;
14697       break;
14698     case stack_v_mode:
14699       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14700         {
14701           names = names64;
14702           break;
14703         }
14704       bytemode = v_mode;
14705       /* FALLTHRU */
14706     case v_mode:
14707     case v_swap_mode:
14708     case dq_mode:
14709     case dqb_mode:
14710     case dqd_mode:
14711     case dqw_mode:
14712     case dqw_swap_mode:
14713       USED_REX (REX_W);
14714       if (rex & REX_W)
14715         names = names64;
14716       else
14717         {
14718           if ((sizeflag & DFLAG)
14719               || (bytemode != v_mode
14720                   && bytemode != v_swap_mode))
14721             names = names32;
14722           else
14723             names = names16;
14724           used_prefixes |= (prefixes & PREFIX_DATA);
14725         }
14726       break;
14727     case mask_bd_mode:
14728     case mask_mode:
14729       names = names_mask;
14730       break;
14731     case 0:
14732       return;
14733     default:
14734       oappend (INTERNAL_DISASSEMBLER_ERROR);
14735       return;
14736     }
14737   oappend (names[reg]);
14738 }
14739
14740 static void
14741 OP_E_memory (int bytemode, int sizeflag)
14742 {
14743   bfd_vma disp = 0;
14744   int add = (rex & REX_B) ? 8 : 0;
14745   int riprel = 0;
14746   int shift;
14747
14748   if (vex.evex)
14749     {
14750       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14751       if (vex.b
14752           && bytemode != x_mode
14753           && bytemode != xmmq_mode
14754           && bytemode != evex_half_bcst_xmmq_mode)
14755         {
14756           BadOp ();
14757           return;
14758         }
14759       switch (bytemode)
14760         {
14761         case dqw_mode:
14762         case dw_mode:
14763         case dqw_swap_mode:
14764           shift = 1;
14765           break;
14766         case dqb_mode:
14767         case db_mode:
14768           shift = 0;
14769           break;
14770         case vex_vsib_d_w_dq_mode:
14771         case vex_vsib_d_w_d_mode:
14772         case vex_vsib_q_w_dq_mode:
14773         case vex_vsib_q_w_d_mode:
14774         case evex_x_gscat_mode:
14775         case xmm_mdq_mode:
14776           shift = vex.w ? 3 : 2;
14777           break;
14778         case x_mode:
14779         case evex_half_bcst_xmmq_mode:
14780         case xmmq_mode:
14781           if (vex.b)
14782             {
14783               shift = vex.w ? 3 : 2;
14784               break;
14785             }
14786           /* Fall through if vex.b == 0.  */
14787         case xmmqd_mode:
14788         case xmmdw_mode:
14789         case ymmq_mode:
14790         case evex_x_nobcst_mode:
14791         case x_swap_mode:
14792           switch (vex.length)
14793             {
14794             case 128:
14795               shift = 4;
14796               break;
14797             case 256:
14798               shift = 5;
14799               break;
14800             case 512:
14801               shift = 6;
14802               break;
14803             default:
14804               abort ();
14805             }
14806           break;
14807         case ymm_mode:
14808           shift = 5;
14809           break;
14810         case xmm_mode:
14811           shift = 4;
14812           break;
14813         case xmm_mq_mode:
14814         case q_mode:
14815         case q_scalar_mode:
14816         case q_swap_mode:
14817         case q_scalar_swap_mode:
14818           shift = 3;
14819           break;
14820         case dqd_mode:
14821         case xmm_md_mode:
14822         case d_mode:
14823         case d_scalar_mode:
14824         case d_swap_mode:
14825         case d_scalar_swap_mode:
14826           shift = 2;
14827           break;
14828         case xmm_mw_mode:
14829           shift = 1;
14830           break;
14831         case xmm_mb_mode:
14832           shift = 0;
14833           break;
14834         default:
14835           abort ();
14836         }
14837       /* Make necessary corrections to shift for modes that need it.
14838          For these modes we currently have shift 4, 5 or 6 depending on
14839          vex.length (it corresponds to xmmword, ymmword or zmmword
14840          operand).  We might want to make it 3, 4 or 5 (e.g. for
14841          xmmq_mode).  In case of broadcast enabled the corrections
14842          aren't needed, as element size is always 32 or 64 bits.  */
14843       if (!vex.b
14844           && (bytemode == xmmq_mode
14845               || bytemode == evex_half_bcst_xmmq_mode))
14846         shift -= 1;
14847       else if (bytemode == xmmqd_mode)
14848         shift -= 2;
14849       else if (bytemode == xmmdw_mode)
14850         shift -= 3;
14851       else if (bytemode == ymmq_mode && vex.length == 128)
14852         shift -= 1;
14853     }
14854   else
14855     shift = 0;
14856
14857   USED_REX (REX_B);
14858   if (intel_syntax)
14859     intel_operand_size (bytemode, sizeflag);
14860   append_seg ();
14861
14862   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14863     {
14864       /* 32/64 bit address mode */
14865       int havedisp;
14866       int havesib;
14867       int havebase;
14868       int haveindex;
14869       int needindex;
14870       int base, rbase;
14871       int vindex = 0;
14872       int scale = 0;
14873       int addr32flag = !((sizeflag & AFLAG)
14874                          || bytemode == v_bnd_mode
14875                          || bytemode == bnd_mode);
14876       const char **indexes64 = names64;
14877       const char **indexes32 = names32;
14878
14879       havesib = 0;
14880       havebase = 1;
14881       haveindex = 0;
14882       base = modrm.rm;
14883
14884       if (base == 4)
14885         {
14886           havesib = 1;
14887           vindex = sib.index;
14888           USED_REX (REX_X);
14889           if (rex & REX_X)
14890             vindex += 8;
14891           switch (bytemode)
14892             {
14893             case vex_vsib_d_w_dq_mode:
14894             case vex_vsib_d_w_d_mode:
14895             case vex_vsib_q_w_dq_mode:
14896             case vex_vsib_q_w_d_mode:
14897               if (!need_vex)
14898                 abort ();
14899               if (vex.evex)
14900                 {
14901                   if (!vex.v)
14902                     vindex += 16;
14903                 }
14904
14905               haveindex = 1;
14906               switch (vex.length)
14907                 {
14908                 case 128:
14909                   indexes64 = indexes32 = names_xmm;
14910                   break;
14911                 case 256:
14912                   if (!vex.w
14913                       || bytemode == vex_vsib_q_w_dq_mode
14914                       || bytemode == vex_vsib_q_w_d_mode)
14915                     indexes64 = indexes32 = names_ymm;
14916                   else
14917                     indexes64 = indexes32 = names_xmm;
14918                   break;
14919                 case 512:
14920                   if (!vex.w
14921                       || bytemode == vex_vsib_q_w_dq_mode
14922                       || bytemode == vex_vsib_q_w_d_mode)
14923                     indexes64 = indexes32 = names_zmm;
14924                   else
14925                     indexes64 = indexes32 = names_ymm;
14926                   break;
14927                 default:
14928                   abort ();
14929                 }
14930               break;
14931             default:
14932               haveindex = vindex != 4;
14933               break;
14934             }
14935           scale = sib.scale;
14936           base = sib.base;
14937           codep++;
14938         }
14939       rbase = base + add;
14940
14941       switch (modrm.mod)
14942         {
14943         case 0:
14944           if (base == 5)
14945             {
14946               havebase = 0;
14947               if (address_mode == mode_64bit && !havesib)
14948                 riprel = 1;
14949               disp = get32s ();
14950             }
14951           break;
14952         case 1:
14953           FETCH_DATA (the_info, codep + 1);
14954           disp = *codep++;
14955           if ((disp & 0x80) != 0)
14956             disp -= 0x100;
14957           if (vex.evex && shift > 0)
14958             disp <<= shift;
14959           break;
14960         case 2:
14961           disp = get32s ();
14962           break;
14963         }
14964
14965       /* In 32bit mode, we need index register to tell [offset] from
14966          [eiz*1 + offset].  */
14967       needindex = (havesib
14968                    && !havebase
14969                    && !haveindex
14970                    && address_mode == mode_32bit);
14971       havedisp = (havebase
14972                   || needindex
14973                   || (havesib && (haveindex || scale != 0)));
14974
14975       if (!intel_syntax)
14976         if (modrm.mod != 0 || base == 5)
14977           {
14978             if (havedisp || riprel)
14979               print_displacement (scratchbuf, disp);
14980             else
14981               print_operand_value (scratchbuf, 1, disp);
14982             oappend (scratchbuf);
14983             if (riprel)
14984               {
14985                 set_op (disp, 1);
14986                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14987               }
14988           }
14989
14990       if ((havebase || haveindex || riprel)
14991           && (bytemode != v_bnd_mode)
14992           && (bytemode != bnd_mode))
14993         used_prefixes |= PREFIX_ADDR;
14994
14995       if (havedisp || (intel_syntax && riprel))
14996         {
14997           *obufp++ = open_char;
14998           if (intel_syntax && riprel)
14999             {
15000               set_op (disp, 1);
15001               oappend (sizeflag & AFLAG ? "rip" : "eip");
15002             }
15003           *obufp = '\0';
15004           if (havebase)
15005             oappend (address_mode == mode_64bit && !addr32flag
15006                      ? names64[rbase] : names32[rbase]);
15007           if (havesib)
15008             {
15009               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15010                  print index to tell base + index from base.  */
15011               if (scale != 0
15012                   || needindex
15013                   || haveindex
15014                   || (havebase && base != ESP_REG_NUM))
15015                 {
15016                   if (!intel_syntax || havebase)
15017                     {
15018                       *obufp++ = separator_char;
15019                       *obufp = '\0';
15020                     }
15021                   if (haveindex)
15022                     oappend (address_mode == mode_64bit && !addr32flag
15023                              ? indexes64[vindex] : indexes32[vindex]);
15024                   else
15025                     oappend (address_mode == mode_64bit && !addr32flag
15026                              ? index64 : index32);
15027
15028                   *obufp++ = scale_char;
15029                   *obufp = '\0';
15030                   sprintf (scratchbuf, "%d", 1 << scale);
15031                   oappend (scratchbuf);
15032                 }
15033             }
15034           if (intel_syntax
15035               && (disp || modrm.mod != 0 || base == 5))
15036             {
15037               if (!havedisp || (bfd_signed_vma) disp >= 0)
15038                 {
15039                   *obufp++ = '+';
15040                   *obufp = '\0';
15041                 }
15042               else if (modrm.mod != 1 && disp != -disp)
15043                 {
15044                   *obufp++ = '-';
15045                   *obufp = '\0';
15046                   disp = - (bfd_signed_vma) disp;
15047                 }
15048
15049               if (havedisp)
15050                 print_displacement (scratchbuf, disp);
15051               else
15052                 print_operand_value (scratchbuf, 1, disp);
15053               oappend (scratchbuf);
15054             }
15055
15056           *obufp++ = close_char;
15057           *obufp = '\0';
15058         }
15059       else if (intel_syntax)
15060         {
15061           if (modrm.mod != 0 || base == 5)
15062             {
15063               if (!active_seg_prefix)
15064                 {
15065                   oappend (names_seg[ds_reg - es_reg]);
15066                   oappend (":");
15067                 }
15068               print_operand_value (scratchbuf, 1, disp);
15069               oappend (scratchbuf);
15070             }
15071         }
15072     }
15073   else
15074     {
15075       /* 16 bit address mode */
15076       used_prefixes |= prefixes & PREFIX_ADDR;
15077       switch (modrm.mod)
15078         {
15079         case 0:
15080           if (modrm.rm == 6)
15081             {
15082               disp = get16 ();
15083               if ((disp & 0x8000) != 0)
15084                 disp -= 0x10000;
15085             }
15086           break;
15087         case 1:
15088           FETCH_DATA (the_info, codep + 1);
15089           disp = *codep++;
15090           if ((disp & 0x80) != 0)
15091             disp -= 0x100;
15092           break;
15093         case 2:
15094           disp = get16 ();
15095           if ((disp & 0x8000) != 0)
15096             disp -= 0x10000;
15097           break;
15098         }
15099
15100       if (!intel_syntax)
15101         if (modrm.mod != 0 || modrm.rm == 6)
15102           {
15103             print_displacement (scratchbuf, disp);
15104             oappend (scratchbuf);
15105           }
15106
15107       if (modrm.mod != 0 || modrm.rm != 6)
15108         {
15109           *obufp++ = open_char;
15110           *obufp = '\0';
15111           oappend (index16[modrm.rm]);
15112           if (intel_syntax
15113               && (disp || modrm.mod != 0 || modrm.rm == 6))
15114             {
15115               if ((bfd_signed_vma) disp >= 0)
15116                 {
15117                   *obufp++ = '+';
15118                   *obufp = '\0';
15119                 }
15120               else if (modrm.mod != 1)
15121                 {
15122                   *obufp++ = '-';
15123                   *obufp = '\0';
15124                   disp = - (bfd_signed_vma) disp;
15125                 }
15126
15127               print_displacement (scratchbuf, disp);
15128               oappend (scratchbuf);
15129             }
15130
15131           *obufp++ = close_char;
15132           *obufp = '\0';
15133         }
15134       else if (intel_syntax)
15135         {
15136           if (!active_seg_prefix)
15137             {
15138               oappend (names_seg[ds_reg - es_reg]);
15139               oappend (":");
15140             }
15141           print_operand_value (scratchbuf, 1, disp & 0xffff);
15142           oappend (scratchbuf);
15143         }
15144     }
15145   if (vex.evex && vex.b
15146       && (bytemode == x_mode
15147           || bytemode == xmmq_mode
15148           || bytemode == evex_half_bcst_xmmq_mode))
15149     {
15150       if (vex.w
15151           || bytemode == xmmq_mode
15152           || bytemode == evex_half_bcst_xmmq_mode)
15153         {
15154           switch (vex.length)
15155             {
15156             case 128:
15157               oappend ("{1to2}");
15158               break;
15159             case 256:
15160               oappend ("{1to4}");
15161               break;
15162             case 512:
15163               oappend ("{1to8}");
15164               break;
15165             default:
15166               abort ();
15167             }
15168         }
15169       else
15170         {
15171           switch (vex.length)
15172             {
15173             case 128:
15174               oappend ("{1to4}");
15175               break;
15176             case 256:
15177               oappend ("{1to8}");
15178               break;
15179             case 512:
15180               oappend ("{1to16}");
15181               break;
15182             default:
15183               abort ();
15184             }
15185         }
15186     }
15187 }
15188
15189 static void
15190 OP_E (int bytemode, int sizeflag)
15191 {
15192   /* Skip mod/rm byte.  */
15193   MODRM_CHECK;
15194   codep++;
15195
15196   if (modrm.mod == 3)
15197     OP_E_register (bytemode, sizeflag);
15198   else
15199     OP_E_memory (bytemode, sizeflag);
15200 }
15201
15202 static void
15203 OP_G (int bytemode, int sizeflag)
15204 {
15205   int add = 0;
15206   USED_REX (REX_R);
15207   if (rex & REX_R)
15208     add += 8;
15209   switch (bytemode)
15210     {
15211     case b_mode:
15212       USED_REX (0);
15213       if (rex)
15214         oappend (names8rex[modrm.reg + add]);
15215       else
15216         oappend (names8[modrm.reg + add]);
15217       break;
15218     case w_mode:
15219       oappend (names16[modrm.reg + add]);
15220       break;
15221     case d_mode:
15222     case db_mode:
15223     case dw_mode:
15224       oappend (names32[modrm.reg + add]);
15225       break;
15226     case q_mode:
15227       oappend (names64[modrm.reg + add]);
15228       break;
15229     case bnd_mode:
15230       oappend (names_bnd[modrm.reg]);
15231       break;
15232     case v_mode:
15233     case dq_mode:
15234     case dqb_mode:
15235     case dqd_mode:
15236     case dqw_mode:
15237     case dqw_swap_mode:
15238       USED_REX (REX_W);
15239       if (rex & REX_W)
15240         oappend (names64[modrm.reg + add]);
15241       else
15242         {
15243           if ((sizeflag & DFLAG) || bytemode != v_mode)
15244             oappend (names32[modrm.reg + add]);
15245           else
15246             oappend (names16[modrm.reg + add]);
15247           used_prefixes |= (prefixes & PREFIX_DATA);
15248         }
15249       break;
15250     case m_mode:
15251       if (address_mode == mode_64bit)
15252         oappend (names64[modrm.reg + add]);
15253       else
15254         oappend (names32[modrm.reg + add]);
15255       break;
15256     case mask_bd_mode:
15257     case mask_mode:
15258       oappend (names_mask[modrm.reg + add]);
15259       break;
15260     default:
15261       oappend (INTERNAL_DISASSEMBLER_ERROR);
15262       break;
15263     }
15264 }
15265
15266 static bfd_vma
15267 get64 (void)
15268 {
15269   bfd_vma x;
15270 #ifdef BFD64
15271   unsigned int a;
15272   unsigned int b;
15273
15274   FETCH_DATA (the_info, codep + 8);
15275   a = *codep++ & 0xff;
15276   a |= (*codep++ & 0xff) << 8;
15277   a |= (*codep++ & 0xff) << 16;
15278   a |= (*codep++ & 0xff) << 24;
15279   b = *codep++ & 0xff;
15280   b |= (*codep++ & 0xff) << 8;
15281   b |= (*codep++ & 0xff) << 16;
15282   b |= (*codep++ & 0xff) << 24;
15283   x = a + ((bfd_vma) b << 32);
15284 #else
15285   abort ();
15286   x = 0;
15287 #endif
15288   return x;
15289 }
15290
15291 static bfd_signed_vma
15292 get32 (void)
15293 {
15294   bfd_signed_vma x = 0;
15295
15296   FETCH_DATA (the_info, codep + 4);
15297   x = *codep++ & (bfd_signed_vma) 0xff;
15298   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15299   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15300   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15301   return x;
15302 }
15303
15304 static bfd_signed_vma
15305 get32s (void)
15306 {
15307   bfd_signed_vma x = 0;
15308
15309   FETCH_DATA (the_info, codep + 4);
15310   x = *codep++ & (bfd_signed_vma) 0xff;
15311   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15312   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15313   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15314
15315   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15316
15317   return x;
15318 }
15319
15320 static int
15321 get16 (void)
15322 {
15323   int x = 0;
15324
15325   FETCH_DATA (the_info, codep + 2);
15326   x = *codep++ & 0xff;
15327   x |= (*codep++ & 0xff) << 8;
15328   return x;
15329 }
15330
15331 static void
15332 set_op (bfd_vma op, int riprel)
15333 {
15334   op_index[op_ad] = op_ad;
15335   if (address_mode == mode_64bit)
15336     {
15337       op_address[op_ad] = op;
15338       op_riprel[op_ad] = riprel;
15339     }
15340   else
15341     {
15342       /* Mask to get a 32-bit address.  */
15343       op_address[op_ad] = op & 0xffffffff;
15344       op_riprel[op_ad] = riprel & 0xffffffff;
15345     }
15346 }
15347
15348 static void
15349 OP_REG (int code, int sizeflag)
15350 {
15351   const char *s;
15352   int add;
15353
15354   switch (code)
15355     {
15356     case es_reg: case ss_reg: case cs_reg:
15357     case ds_reg: case fs_reg: case gs_reg:
15358       oappend (names_seg[code - es_reg]);
15359       return;
15360     }
15361
15362   USED_REX (REX_B);
15363   if (rex & REX_B)
15364     add = 8;
15365   else
15366     add = 0;
15367
15368   switch (code)
15369     {
15370     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15371     case sp_reg: case bp_reg: case si_reg: case di_reg:
15372       s = names16[code - ax_reg + add];
15373       break;
15374     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15375     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15376       USED_REX (0);
15377       if (rex)
15378         s = names8rex[code - al_reg + add];
15379       else
15380         s = names8[code - al_reg];
15381       break;
15382     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15383     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15384       if (address_mode == mode_64bit
15385           && ((sizeflag & DFLAG) || (rex & REX_W)))
15386         {
15387           s = names64[code - rAX_reg + add];
15388           break;
15389         }
15390       code += eAX_reg - rAX_reg;
15391       /* Fall through.  */
15392     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15393     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15394       USED_REX (REX_W);
15395       if (rex & REX_W)
15396         s = names64[code - eAX_reg + add];
15397       else
15398         {
15399           if (sizeflag & DFLAG)
15400             s = names32[code - eAX_reg + add];
15401           else
15402             s = names16[code - eAX_reg + add];
15403           used_prefixes |= (prefixes & PREFIX_DATA);
15404         }
15405       break;
15406     default:
15407       s = INTERNAL_DISASSEMBLER_ERROR;
15408       break;
15409     }
15410   oappend (s);
15411 }
15412
15413 static void
15414 OP_IMREG (int code, int sizeflag)
15415 {
15416   const char *s;
15417
15418   switch (code)
15419     {
15420     case indir_dx_reg:
15421       if (intel_syntax)
15422         s = "dx";
15423       else
15424         s = "(%dx)";
15425       break;
15426     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15427     case sp_reg: case bp_reg: case si_reg: case di_reg:
15428       s = names16[code - ax_reg];
15429       break;
15430     case es_reg: case ss_reg: case cs_reg:
15431     case ds_reg: case fs_reg: case gs_reg:
15432       s = names_seg[code - es_reg];
15433       break;
15434     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15435     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15436       USED_REX (0);
15437       if (rex)
15438         s = names8rex[code - al_reg];
15439       else
15440         s = names8[code - al_reg];
15441       break;
15442     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15443     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15444       USED_REX (REX_W);
15445       if (rex & REX_W)
15446         s = names64[code - eAX_reg];
15447       else
15448         {
15449           if (sizeflag & DFLAG)
15450             s = names32[code - eAX_reg];
15451           else
15452             s = names16[code - eAX_reg];
15453           used_prefixes |= (prefixes & PREFIX_DATA);
15454         }
15455       break;
15456     case z_mode_ax_reg:
15457       if ((rex & REX_W) || (sizeflag & DFLAG))
15458         s = *names32;
15459       else
15460         s = *names16;
15461       if (!(rex & REX_W))
15462         used_prefixes |= (prefixes & PREFIX_DATA);
15463       break;
15464     default:
15465       s = INTERNAL_DISASSEMBLER_ERROR;
15466       break;
15467     }
15468   oappend (s);
15469 }
15470
15471 static void
15472 OP_I (int bytemode, int sizeflag)
15473 {
15474   bfd_signed_vma op;
15475   bfd_signed_vma mask = -1;
15476
15477   switch (bytemode)
15478     {
15479     case b_mode:
15480       FETCH_DATA (the_info, codep + 1);
15481       op = *codep++;
15482       mask = 0xff;
15483       break;
15484     case q_mode:
15485       if (address_mode == mode_64bit)
15486         {
15487           op = get32s ();
15488           break;
15489         }
15490       /* Fall through.  */
15491     case v_mode:
15492       USED_REX (REX_W);
15493       if (rex & REX_W)
15494         op = get32s ();
15495       else
15496         {
15497           if (sizeflag & DFLAG)
15498             {
15499               op = get32 ();
15500               mask = 0xffffffff;
15501             }
15502           else
15503             {
15504               op = get16 ();
15505               mask = 0xfffff;
15506             }
15507           used_prefixes |= (prefixes & PREFIX_DATA);
15508         }
15509       break;
15510     case w_mode:
15511       mask = 0xfffff;
15512       op = get16 ();
15513       break;
15514     case const_1_mode:
15515       if (intel_syntax)
15516         oappend ("1");
15517       return;
15518     default:
15519       oappend (INTERNAL_DISASSEMBLER_ERROR);
15520       return;
15521     }
15522
15523   op &= mask;
15524   scratchbuf[0] = '$';
15525   print_operand_value (scratchbuf + 1, 1, op);
15526   oappend_maybe_intel (scratchbuf);
15527   scratchbuf[0] = '\0';
15528 }
15529
15530 static void
15531 OP_I64 (int bytemode, int sizeflag)
15532 {
15533   bfd_signed_vma op;
15534   bfd_signed_vma mask = -1;
15535
15536   if (address_mode != mode_64bit)
15537     {
15538       OP_I (bytemode, sizeflag);
15539       return;
15540     }
15541
15542   switch (bytemode)
15543     {
15544     case b_mode:
15545       FETCH_DATA (the_info, codep + 1);
15546       op = *codep++;
15547       mask = 0xff;
15548       break;
15549     case v_mode:
15550       USED_REX (REX_W);
15551       if (rex & REX_W)
15552         op = get64 ();
15553       else
15554         {
15555           if (sizeflag & DFLAG)
15556             {
15557               op = get32 ();
15558               mask = 0xffffffff;
15559             }
15560           else
15561             {
15562               op = get16 ();
15563               mask = 0xfffff;
15564             }
15565           used_prefixes |= (prefixes & PREFIX_DATA);
15566         }
15567       break;
15568     case w_mode:
15569       mask = 0xfffff;
15570       op = get16 ();
15571       break;
15572     default:
15573       oappend (INTERNAL_DISASSEMBLER_ERROR);
15574       return;
15575     }
15576
15577   op &= mask;
15578   scratchbuf[0] = '$';
15579   print_operand_value (scratchbuf + 1, 1, op);
15580   oappend_maybe_intel (scratchbuf);
15581   scratchbuf[0] = '\0';
15582 }
15583
15584 static void
15585 OP_sI (int bytemode, int sizeflag)
15586 {
15587   bfd_signed_vma op;
15588
15589   switch (bytemode)
15590     {
15591     case b_mode:
15592     case b_T_mode:
15593       FETCH_DATA (the_info, codep + 1);
15594       op = *codep++;
15595       if ((op & 0x80) != 0)
15596         op -= 0x100;
15597       if (bytemode == b_T_mode)
15598         {
15599           if (address_mode != mode_64bit
15600               || !((sizeflag & DFLAG) || (rex & REX_W)))
15601             {
15602               /* The operand-size prefix is overridden by a REX prefix.  */
15603               if ((sizeflag & DFLAG) || (rex & REX_W))
15604                 op &= 0xffffffff;
15605               else
15606                 op &= 0xffff;
15607           }
15608         }
15609       else
15610         {
15611           if (!(rex & REX_W))
15612             {
15613               if (sizeflag & DFLAG)
15614                 op &= 0xffffffff;
15615               else
15616                 op &= 0xffff;
15617             }
15618         }
15619       break;
15620     case v_mode:
15621       /* The operand-size prefix is overridden by a REX prefix.  */
15622       if ((sizeflag & DFLAG) || (rex & REX_W))
15623         op = get32s ();
15624       else
15625         op = get16 ();
15626       break;
15627     default:
15628       oappend (INTERNAL_DISASSEMBLER_ERROR);
15629       return;
15630     }
15631
15632   scratchbuf[0] = '$';
15633   print_operand_value (scratchbuf + 1, 1, op);
15634   oappend_maybe_intel (scratchbuf);
15635 }
15636
15637 static void
15638 OP_J (int bytemode, int sizeflag)
15639 {
15640   bfd_vma disp;
15641   bfd_vma mask = -1;
15642   bfd_vma segment = 0;
15643
15644   switch (bytemode)
15645     {
15646     case b_mode:
15647       FETCH_DATA (the_info, codep + 1);
15648       disp = *codep++;
15649       if ((disp & 0x80) != 0)
15650         disp -= 0x100;
15651       break;
15652     case v_mode:
15653       USED_REX (REX_W);
15654       if ((sizeflag & DFLAG) || (rex & REX_W))
15655         disp = get32s ();
15656       else
15657         {
15658           disp = get16 ();
15659           if ((disp & 0x8000) != 0)
15660             disp -= 0x10000;
15661           /* In 16bit mode, address is wrapped around at 64k within
15662              the same segment.  Otherwise, a data16 prefix on a jump
15663              instruction means that the pc is masked to 16 bits after
15664              the displacement is added!  */
15665           mask = 0xffff;
15666           if ((prefixes & PREFIX_DATA) == 0)
15667             segment = ((start_pc + codep - start_codep)
15668                        & ~((bfd_vma) 0xffff));
15669         }
15670       if (!(rex & REX_W))
15671         used_prefixes |= (prefixes & PREFIX_DATA);
15672       break;
15673     default:
15674       oappend (INTERNAL_DISASSEMBLER_ERROR);
15675       return;
15676     }
15677   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15678   set_op (disp, 0);
15679   print_operand_value (scratchbuf, 1, disp);
15680   oappend (scratchbuf);
15681 }
15682
15683 static void
15684 OP_SEG (int bytemode, int sizeflag)
15685 {
15686   if (bytemode == w_mode)
15687     oappend (names_seg[modrm.reg]);
15688   else
15689     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15690 }
15691
15692 static void
15693 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15694 {
15695   int seg, offset;
15696
15697   if (sizeflag & DFLAG)
15698     {
15699       offset = get32 ();
15700       seg = get16 ();
15701     }
15702   else
15703     {
15704       offset = get16 ();
15705       seg = get16 ();
15706     }
15707   used_prefixes |= (prefixes & PREFIX_DATA);
15708   if (intel_syntax)
15709     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15710   else
15711     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15712   oappend (scratchbuf);
15713 }
15714
15715 static void
15716 OP_OFF (int bytemode, int sizeflag)
15717 {
15718   bfd_vma off;
15719
15720   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15721     intel_operand_size (bytemode, sizeflag);
15722   append_seg ();
15723
15724   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15725     off = get32 ();
15726   else
15727     off = get16 ();
15728
15729   if (intel_syntax)
15730     {
15731       if (!active_seg_prefix)
15732         {
15733           oappend (names_seg[ds_reg - es_reg]);
15734           oappend (":");
15735         }
15736     }
15737   print_operand_value (scratchbuf, 1, off);
15738   oappend (scratchbuf);
15739 }
15740
15741 static void
15742 OP_OFF64 (int bytemode, int sizeflag)
15743 {
15744   bfd_vma off;
15745
15746   if (address_mode != mode_64bit
15747       || (prefixes & PREFIX_ADDR))
15748     {
15749       OP_OFF (bytemode, sizeflag);
15750       return;
15751     }
15752
15753   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15754     intel_operand_size (bytemode, sizeflag);
15755   append_seg ();
15756
15757   off = get64 ();
15758
15759   if (intel_syntax)
15760     {
15761       if (!active_seg_prefix)
15762         {
15763           oappend (names_seg[ds_reg - es_reg]);
15764           oappend (":");
15765         }
15766     }
15767   print_operand_value (scratchbuf, 1, off);
15768   oappend (scratchbuf);
15769 }
15770
15771 static void
15772 ptr_reg (int code, int sizeflag)
15773 {
15774   const char *s;
15775
15776   *obufp++ = open_char;
15777   used_prefixes |= (prefixes & PREFIX_ADDR);
15778   if (address_mode == mode_64bit)
15779     {
15780       if (!(sizeflag & AFLAG))
15781         s = names32[code - eAX_reg];
15782       else
15783         s = names64[code - eAX_reg];
15784     }
15785   else if (sizeflag & AFLAG)
15786     s = names32[code - eAX_reg];
15787   else
15788     s = names16[code - eAX_reg];
15789   oappend (s);
15790   *obufp++ = close_char;
15791   *obufp = 0;
15792 }
15793
15794 static void
15795 OP_ESreg (int code, int sizeflag)
15796 {
15797   if (intel_syntax)
15798     {
15799       switch (codep[-1])
15800         {
15801         case 0x6d:      /* insw/insl */
15802           intel_operand_size (z_mode, sizeflag);
15803           break;
15804         case 0xa5:      /* movsw/movsl/movsq */
15805         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15806         case 0xab:      /* stosw/stosl */
15807         case 0xaf:      /* scasw/scasl */
15808           intel_operand_size (v_mode, sizeflag);
15809           break;
15810         default:
15811           intel_operand_size (b_mode, sizeflag);
15812         }
15813     }
15814   oappend_maybe_intel ("%es:");
15815   ptr_reg (code, sizeflag);
15816 }
15817
15818 static void
15819 OP_DSreg (int code, int sizeflag)
15820 {
15821   if (intel_syntax)
15822     {
15823       switch (codep[-1])
15824         {
15825         case 0x6f:      /* outsw/outsl */
15826           intel_operand_size (z_mode, sizeflag);
15827           break;
15828         case 0xa5:      /* movsw/movsl/movsq */
15829         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15830         case 0xad:      /* lodsw/lodsl/lodsq */
15831           intel_operand_size (v_mode, sizeflag);
15832           break;
15833         default:
15834           intel_operand_size (b_mode, sizeflag);
15835         }
15836     }
15837   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15838      default segment register DS is printed.  */
15839   if (!active_seg_prefix)
15840     active_seg_prefix = PREFIX_DS;
15841   append_seg ();
15842   ptr_reg (code, sizeflag);
15843 }
15844
15845 static void
15846 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15847 {
15848   int add;
15849   if (rex & REX_R)
15850     {
15851       USED_REX (REX_R);
15852       add = 8;
15853     }
15854   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15855     {
15856       all_prefixes[last_lock_prefix] = 0;
15857       used_prefixes |= PREFIX_LOCK;
15858       add = 8;
15859     }
15860   else
15861     add = 0;
15862   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15863   oappend_maybe_intel (scratchbuf);
15864 }
15865
15866 static void
15867 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15868 {
15869   int add;
15870   USED_REX (REX_R);
15871   if (rex & REX_R)
15872     add = 8;
15873   else
15874     add = 0;
15875   if (intel_syntax)
15876     sprintf (scratchbuf, "db%d", modrm.reg + add);
15877   else
15878     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15879   oappend (scratchbuf);
15880 }
15881
15882 static void
15883 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15884 {
15885   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15886   oappend_maybe_intel (scratchbuf);
15887 }
15888
15889 static void
15890 OP_R (int bytemode, int sizeflag)
15891 {
15892   /* Skip mod/rm byte.  */
15893   MODRM_CHECK;
15894   codep++;
15895   OP_E_register (bytemode, sizeflag);
15896 }
15897
15898 static void
15899 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15900 {
15901   int reg = modrm.reg;
15902   const char **names;
15903
15904   used_prefixes |= (prefixes & PREFIX_DATA);
15905   if (prefixes & PREFIX_DATA)
15906     {
15907       names = names_xmm;
15908       USED_REX (REX_R);
15909       if (rex & REX_R)
15910         reg += 8;
15911     }
15912   else
15913     names = names_mm;
15914   oappend (names[reg]);
15915 }
15916
15917 static void
15918 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15919 {
15920   int reg = modrm.reg;
15921   const char **names;
15922
15923   USED_REX (REX_R);
15924   if (rex & REX_R)
15925     reg += 8;
15926   if (vex.evex)
15927     {
15928       if (!vex.r)
15929         reg += 16;
15930     }
15931
15932   if (need_vex
15933       && bytemode != xmm_mode
15934       && bytemode != xmmq_mode
15935       && bytemode != evex_half_bcst_xmmq_mode
15936       && bytemode != ymm_mode
15937       && bytemode != scalar_mode)
15938     {
15939       switch (vex.length)
15940         {
15941         case 128:
15942           names = names_xmm;
15943           break;
15944         case 256:
15945           if (vex.w
15946               || (bytemode != vex_vsib_q_w_dq_mode
15947                   && bytemode != vex_vsib_q_w_d_mode))
15948             names = names_ymm;
15949           else
15950             names = names_xmm;
15951           break;
15952         case 512:
15953           names = names_zmm;
15954           break;
15955         default:
15956           abort ();
15957         }
15958     }
15959   else if (bytemode == xmmq_mode
15960            || bytemode == evex_half_bcst_xmmq_mode)
15961     {
15962       switch (vex.length)
15963         {
15964         case 128:
15965         case 256:
15966           names = names_xmm;
15967           break;
15968         case 512:
15969           names = names_ymm;
15970           break;
15971         default:
15972           abort ();
15973         }
15974     }
15975   else if (bytemode == ymm_mode)
15976     names = names_ymm;
15977   else
15978     names = names_xmm;
15979   oappend (names[reg]);
15980 }
15981
15982 static void
15983 OP_EM (int bytemode, int sizeflag)
15984 {
15985   int reg;
15986   const char **names;
15987
15988   if (modrm.mod != 3)
15989     {
15990       if (intel_syntax
15991           && (bytemode == v_mode || bytemode == v_swap_mode))
15992         {
15993           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15994           used_prefixes |= (prefixes & PREFIX_DATA);
15995         }
15996       OP_E (bytemode, sizeflag);
15997       return;
15998     }
15999
16000   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16001     swap_operand ();
16002
16003   /* Skip mod/rm byte.  */
16004   MODRM_CHECK;
16005   codep++;
16006   used_prefixes |= (prefixes & PREFIX_DATA);
16007   reg = modrm.rm;
16008   if (prefixes & PREFIX_DATA)
16009     {
16010       names = names_xmm;
16011       USED_REX (REX_B);
16012       if (rex & REX_B)
16013         reg += 8;
16014     }
16015   else
16016     names = names_mm;
16017   oappend (names[reg]);
16018 }
16019
16020 /* cvt* are the only instructions in sse2 which have
16021    both SSE and MMX operands and also have 0x66 prefix
16022    in their opcode. 0x66 was originally used to differentiate
16023    between SSE and MMX instruction(operands). So we have to handle the
16024    cvt* separately using OP_EMC and OP_MXC */
16025 static void
16026 OP_EMC (int bytemode, int sizeflag)
16027 {
16028   if (modrm.mod != 3)
16029     {
16030       if (intel_syntax && bytemode == v_mode)
16031         {
16032           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16033           used_prefixes |= (prefixes & PREFIX_DATA);
16034         }
16035       OP_E (bytemode, sizeflag);
16036       return;
16037     }
16038
16039   /* Skip mod/rm byte.  */
16040   MODRM_CHECK;
16041   codep++;
16042   used_prefixes |= (prefixes & PREFIX_DATA);
16043   oappend (names_mm[modrm.rm]);
16044 }
16045
16046 static void
16047 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16048 {
16049   used_prefixes |= (prefixes & PREFIX_DATA);
16050   oappend (names_mm[modrm.reg]);
16051 }
16052
16053 static void
16054 OP_EX (int bytemode, int sizeflag)
16055 {
16056   int reg;
16057   const char **names;
16058
16059   /* Skip mod/rm byte.  */
16060   MODRM_CHECK;
16061   codep++;
16062
16063   if (modrm.mod != 3)
16064     {
16065       OP_E_memory (bytemode, sizeflag);
16066       return;
16067     }
16068
16069   reg = modrm.rm;
16070   USED_REX (REX_B);
16071   if (rex & REX_B)
16072     reg += 8;
16073   if (vex.evex)
16074     {
16075       USED_REX (REX_X);
16076       if ((rex & REX_X))
16077         reg += 16;
16078     }
16079
16080   if ((sizeflag & SUFFIX_ALWAYS)
16081       && (bytemode == x_swap_mode
16082           || bytemode == d_swap_mode
16083           || bytemode == dqw_swap_mode
16084           || bytemode == d_scalar_swap_mode
16085           || bytemode == q_swap_mode
16086           || bytemode == q_scalar_swap_mode))
16087     swap_operand ();
16088
16089   if (need_vex
16090       && bytemode != xmm_mode
16091       && bytemode != xmmdw_mode
16092       && bytemode != xmmqd_mode
16093       && bytemode != xmm_mb_mode
16094       && bytemode != xmm_mw_mode
16095       && bytemode != xmm_md_mode
16096       && bytemode != xmm_mq_mode
16097       && bytemode != xmm_mdq_mode
16098       && bytemode != xmmq_mode
16099       && bytemode != evex_half_bcst_xmmq_mode
16100       && bytemode != ymm_mode
16101       && bytemode != d_scalar_mode
16102       && bytemode != d_scalar_swap_mode
16103       && bytemode != q_scalar_mode
16104       && bytemode != q_scalar_swap_mode
16105       && bytemode != vex_scalar_w_dq_mode)
16106     {
16107       switch (vex.length)
16108         {
16109         case 128:
16110           names = names_xmm;
16111           break;
16112         case 256:
16113           names = names_ymm;
16114           break;
16115         case 512:
16116           names = names_zmm;
16117           break;
16118         default:
16119           abort ();
16120         }
16121     }
16122   else if (bytemode == xmmq_mode
16123            || bytemode == evex_half_bcst_xmmq_mode)
16124     {
16125       switch (vex.length)
16126         {
16127         case 128:
16128         case 256:
16129           names = names_xmm;
16130           break;
16131         case 512:
16132           names = names_ymm;
16133           break;
16134         default:
16135           abort ();
16136         }
16137     }
16138   else if (bytemode == ymm_mode)
16139     names = names_ymm;
16140   else
16141     names = names_xmm;
16142   oappend (names[reg]);
16143 }
16144
16145 static void
16146 OP_MS (int bytemode, int sizeflag)
16147 {
16148   if (modrm.mod == 3)
16149     OP_EM (bytemode, sizeflag);
16150   else
16151     BadOp ();
16152 }
16153
16154 static void
16155 OP_XS (int bytemode, int sizeflag)
16156 {
16157   if (modrm.mod == 3)
16158     OP_EX (bytemode, sizeflag);
16159   else
16160     BadOp ();
16161 }
16162
16163 static void
16164 OP_M (int bytemode, int sizeflag)
16165 {
16166   if (modrm.mod == 3)
16167     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16168     BadOp ();
16169   else
16170     OP_E (bytemode, sizeflag);
16171 }
16172
16173 static void
16174 OP_0f07 (int bytemode, int sizeflag)
16175 {
16176   if (modrm.mod != 3 || modrm.rm != 0)
16177     BadOp ();
16178   else
16179     OP_E (bytemode, sizeflag);
16180 }
16181
16182 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16183    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16184
16185 static void
16186 NOP_Fixup1 (int bytemode, int sizeflag)
16187 {
16188   if ((prefixes & PREFIX_DATA) != 0
16189       || (rex != 0
16190           && rex != 0x48
16191           && address_mode == mode_64bit))
16192     OP_REG (bytemode, sizeflag);
16193   else
16194     strcpy (obuf, "nop");
16195 }
16196
16197 static void
16198 NOP_Fixup2 (int bytemode, int sizeflag)
16199 {
16200   if ((prefixes & PREFIX_DATA) != 0
16201       || (rex != 0
16202           && rex != 0x48
16203           && address_mode == mode_64bit))
16204     OP_IMREG (bytemode, sizeflag);
16205 }
16206
16207 static const char *const Suffix3DNow[] = {
16208 /* 00 */        NULL,           NULL,           NULL,           NULL,
16209 /* 04 */        NULL,           NULL,           NULL,           NULL,
16210 /* 08 */        NULL,           NULL,           NULL,           NULL,
16211 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16212 /* 10 */        NULL,           NULL,           NULL,           NULL,
16213 /* 14 */        NULL,           NULL,           NULL,           NULL,
16214 /* 18 */        NULL,           NULL,           NULL,           NULL,
16215 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16216 /* 20 */        NULL,           NULL,           NULL,           NULL,
16217 /* 24 */        NULL,           NULL,           NULL,           NULL,
16218 /* 28 */        NULL,           NULL,           NULL,           NULL,
16219 /* 2C */        NULL,           NULL,           NULL,           NULL,
16220 /* 30 */        NULL,           NULL,           NULL,           NULL,
16221 /* 34 */        NULL,           NULL,           NULL,           NULL,
16222 /* 38 */        NULL,           NULL,           NULL,           NULL,
16223 /* 3C */        NULL,           NULL,           NULL,           NULL,
16224 /* 40 */        NULL,           NULL,           NULL,           NULL,
16225 /* 44 */        NULL,           NULL,           NULL,           NULL,
16226 /* 48 */        NULL,           NULL,           NULL,           NULL,
16227 /* 4C */        NULL,           NULL,           NULL,           NULL,
16228 /* 50 */        NULL,           NULL,           NULL,           NULL,
16229 /* 54 */        NULL,           NULL,           NULL,           NULL,
16230 /* 58 */        NULL,           NULL,           NULL,           NULL,
16231 /* 5C */        NULL,           NULL,           NULL,           NULL,
16232 /* 60 */        NULL,           NULL,           NULL,           NULL,
16233 /* 64 */        NULL,           NULL,           NULL,           NULL,
16234 /* 68 */        NULL,           NULL,           NULL,           NULL,
16235 /* 6C */        NULL,           NULL,           NULL,           NULL,
16236 /* 70 */        NULL,           NULL,           NULL,           NULL,
16237 /* 74 */        NULL,           NULL,           NULL,           NULL,
16238 /* 78 */        NULL,           NULL,           NULL,           NULL,
16239 /* 7C */        NULL,           NULL,           NULL,           NULL,
16240 /* 80 */        NULL,           NULL,           NULL,           NULL,
16241 /* 84 */        NULL,           NULL,           NULL,           NULL,
16242 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16243 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16244 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16245 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16246 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16247 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16248 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16249 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16250 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16251 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16252 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16253 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16254 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16255 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16256 /* C0 */        NULL,           NULL,           NULL,           NULL,
16257 /* C4 */        NULL,           NULL,           NULL,           NULL,
16258 /* C8 */        NULL,           NULL,           NULL,           NULL,
16259 /* CC */        NULL,           NULL,           NULL,           NULL,
16260 /* D0 */        NULL,           NULL,           NULL,           NULL,
16261 /* D4 */        NULL,           NULL,           NULL,           NULL,
16262 /* D8 */        NULL,           NULL,           NULL,           NULL,
16263 /* DC */        NULL,           NULL,           NULL,           NULL,
16264 /* E0 */        NULL,           NULL,           NULL,           NULL,
16265 /* E4 */        NULL,           NULL,           NULL,           NULL,
16266 /* E8 */        NULL,           NULL,           NULL,           NULL,
16267 /* EC */        NULL,           NULL,           NULL,           NULL,
16268 /* F0 */        NULL,           NULL,           NULL,           NULL,
16269 /* F4 */        NULL,           NULL,           NULL,           NULL,
16270 /* F8 */        NULL,           NULL,           NULL,           NULL,
16271 /* FC */        NULL,           NULL,           NULL,           NULL,
16272 };
16273
16274 static void
16275 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16276 {
16277   const char *mnemonic;
16278
16279   FETCH_DATA (the_info, codep + 1);
16280   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16281      place where an 8-bit immediate would normally go.  ie. the last
16282      byte of the instruction.  */
16283   obufp = mnemonicendp;
16284   mnemonic = Suffix3DNow[*codep++ & 0xff];
16285   if (mnemonic)
16286     oappend (mnemonic);
16287   else
16288     {
16289       /* Since a variable sized modrm/sib chunk is between the start
16290          of the opcode (0x0f0f) and the opcode suffix, we need to do
16291          all the modrm processing first, and don't know until now that
16292          we have a bad opcode.  This necessitates some cleaning up.  */
16293       op_out[0][0] = '\0';
16294       op_out[1][0] = '\0';
16295       BadOp ();
16296     }
16297   mnemonicendp = obufp;
16298 }
16299
16300 static struct op simd_cmp_op[] =
16301 {
16302   { STRING_COMMA_LEN ("eq") },
16303   { STRING_COMMA_LEN ("lt") },
16304   { STRING_COMMA_LEN ("le") },
16305   { STRING_COMMA_LEN ("unord") },
16306   { STRING_COMMA_LEN ("neq") },
16307   { STRING_COMMA_LEN ("nlt") },
16308   { STRING_COMMA_LEN ("nle") },
16309   { STRING_COMMA_LEN ("ord") }
16310 };
16311
16312 static void
16313 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16314 {
16315   unsigned int cmp_type;
16316
16317   FETCH_DATA (the_info, codep + 1);
16318   cmp_type = *codep++ & 0xff;
16319   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16320     {
16321       char suffix [3];
16322       char *p = mnemonicendp - 2;
16323       suffix[0] = p[0];
16324       suffix[1] = p[1];
16325       suffix[2] = '\0';
16326       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16327       mnemonicendp += simd_cmp_op[cmp_type].len;
16328     }
16329   else
16330     {
16331       /* We have a reserved extension byte.  Output it directly.  */
16332       scratchbuf[0] = '$';
16333       print_operand_value (scratchbuf + 1, 1, cmp_type);
16334       oappend_maybe_intel (scratchbuf);
16335       scratchbuf[0] = '\0';
16336     }
16337 }
16338
16339 static void
16340 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16341           int sizeflag ATTRIBUTE_UNUSED)
16342 {
16343   /* mwait %eax,%ecx  */
16344   if (!intel_syntax)
16345     {
16346       const char **names = (address_mode == mode_64bit
16347                             ? names64 : names32);
16348       strcpy (op_out[0], names[0]);
16349       strcpy (op_out[1], names[1]);
16350       two_source_ops = 1;
16351     }
16352   /* Skip mod/rm byte.  */
16353   MODRM_CHECK;
16354   codep++;
16355 }
16356
16357 static void
16358 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16359             int sizeflag ATTRIBUTE_UNUSED)
16360 {
16361   /* monitor %eax,%ecx,%edx"  */
16362   if (!intel_syntax)
16363     {
16364       const char **op1_names;
16365       const char **names = (address_mode == mode_64bit
16366                             ? names64 : names32);
16367
16368       if (!(prefixes & PREFIX_ADDR))
16369         op1_names = (address_mode == mode_16bit
16370                      ? names16 : names);
16371       else
16372         {
16373           /* Remove "addr16/addr32".  */
16374           all_prefixes[last_addr_prefix] = 0;
16375           op1_names = (address_mode != mode_32bit
16376                        ? names32 : names16);
16377           used_prefixes |= PREFIX_ADDR;
16378         }
16379       strcpy (op_out[0], op1_names[0]);
16380       strcpy (op_out[1], names[1]);
16381       strcpy (op_out[2], names[2]);
16382       two_source_ops = 1;
16383     }
16384   /* Skip mod/rm byte.  */
16385   MODRM_CHECK;
16386   codep++;
16387 }
16388
16389 static void
16390 BadOp (void)
16391 {
16392   /* Throw away prefixes and 1st. opcode byte.  */
16393   codep = insn_codep + 1;
16394   oappend ("(bad)");
16395 }
16396
16397 static void
16398 REP_Fixup (int bytemode, int sizeflag)
16399 {
16400   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16401      lods and stos.  */
16402   if (prefixes & PREFIX_REPZ)
16403     all_prefixes[last_repz_prefix] = REP_PREFIX;
16404
16405   switch (bytemode)
16406     {
16407     case al_reg:
16408     case eAX_reg:
16409     case indir_dx_reg:
16410       OP_IMREG (bytemode, sizeflag);
16411       break;
16412     case eDI_reg:
16413       OP_ESreg (bytemode, sizeflag);
16414       break;
16415     case eSI_reg:
16416       OP_DSreg (bytemode, sizeflag);
16417       break;
16418     default:
16419       abort ();
16420       break;
16421     }
16422 }
16423
16424 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16425    "bnd".  */
16426
16427 static void
16428 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16429 {
16430   if (prefixes & PREFIX_REPNZ)
16431     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16432 }
16433
16434 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16435    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16436  */
16437
16438 static void
16439 HLE_Fixup1 (int bytemode, int sizeflag)
16440 {
16441   if (modrm.mod != 3
16442       && (prefixes & PREFIX_LOCK) != 0)
16443     {
16444       if (prefixes & PREFIX_REPZ)
16445         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16446       if (prefixes & PREFIX_REPNZ)
16447         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16448     }
16449
16450   OP_E (bytemode, sizeflag);
16451 }
16452
16453 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16454    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16455  */
16456
16457 static void
16458 HLE_Fixup2 (int bytemode, int sizeflag)
16459 {
16460   if (modrm.mod != 3)
16461     {
16462       if (prefixes & PREFIX_REPZ)
16463         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16464       if (prefixes & PREFIX_REPNZ)
16465         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16466     }
16467
16468   OP_E (bytemode, sizeflag);
16469 }
16470
16471 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16472    "xrelease" for memory operand.  No check for LOCK prefix.   */
16473
16474 static void
16475 HLE_Fixup3 (int bytemode, int sizeflag)
16476 {
16477   if (modrm.mod != 3
16478       && last_repz_prefix > last_repnz_prefix
16479       && (prefixes & PREFIX_REPZ) != 0)
16480     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16481
16482   OP_E (bytemode, sizeflag);
16483 }
16484
16485 static void
16486 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16487 {
16488   USED_REX (REX_W);
16489   if (rex & REX_W)
16490     {
16491       /* Change cmpxchg8b to cmpxchg16b.  */
16492       char *p = mnemonicendp - 2;
16493       mnemonicendp = stpcpy (p, "16b");
16494       bytemode = o_mode;
16495     }
16496   else if ((prefixes & PREFIX_LOCK) != 0)
16497     {
16498       if (prefixes & PREFIX_REPZ)
16499         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16500       if (prefixes & PREFIX_REPNZ)
16501         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16502     }
16503
16504   OP_M (bytemode, sizeflag);
16505 }
16506
16507 static void
16508 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16509 {
16510   const char **names;
16511
16512   if (need_vex)
16513     {
16514       switch (vex.length)
16515         {
16516         case 128:
16517           names = names_xmm;
16518           break;
16519         case 256:
16520           names = names_ymm;
16521           break;
16522         default:
16523           abort ();
16524         }
16525     }
16526   else
16527     names = names_xmm;
16528   oappend (names[reg]);
16529 }
16530
16531 static void
16532 CRC32_Fixup (int bytemode, int sizeflag)
16533 {
16534   /* Add proper suffix to "crc32".  */
16535   char *p = mnemonicendp;
16536
16537   switch (bytemode)
16538     {
16539     case b_mode:
16540       if (intel_syntax)
16541         goto skip;
16542
16543       *p++ = 'b';
16544       break;
16545     case v_mode:
16546       if (intel_syntax)
16547         goto skip;
16548
16549       USED_REX (REX_W);
16550       if (rex & REX_W)
16551         *p++ = 'q';
16552       else
16553         {
16554           if (sizeflag & DFLAG)
16555             *p++ = 'l';
16556           else
16557             *p++ = 'w';
16558           used_prefixes |= (prefixes & PREFIX_DATA);
16559         }
16560       break;
16561     default:
16562       oappend (INTERNAL_DISASSEMBLER_ERROR);
16563       break;
16564     }
16565   mnemonicendp = p;
16566   *p = '\0';
16567
16568 skip:
16569   if (modrm.mod == 3)
16570     {
16571       int add;
16572
16573       /* Skip mod/rm byte.  */
16574       MODRM_CHECK;
16575       codep++;
16576
16577       USED_REX (REX_B);
16578       add = (rex & REX_B) ? 8 : 0;
16579       if (bytemode == b_mode)
16580         {
16581           USED_REX (0);
16582           if (rex)
16583             oappend (names8rex[modrm.rm + add]);
16584           else
16585             oappend (names8[modrm.rm + add]);
16586         }
16587       else
16588         {
16589           USED_REX (REX_W);
16590           if (rex & REX_W)
16591             oappend (names64[modrm.rm + add]);
16592           else if ((prefixes & PREFIX_DATA))
16593             oappend (names16[modrm.rm + add]);
16594           else
16595             oappend (names32[modrm.rm + add]);
16596         }
16597     }
16598   else
16599     OP_E (bytemode, sizeflag);
16600 }
16601
16602 static void
16603 FXSAVE_Fixup (int bytemode, int sizeflag)
16604 {
16605   /* Add proper suffix to "fxsave" and "fxrstor".  */
16606   USED_REX (REX_W);
16607   if (rex & REX_W)
16608     {
16609       char *p = mnemonicendp;
16610       *p++ = '6';
16611       *p++ = '4';
16612       *p = '\0';
16613       mnemonicendp = p;
16614     }
16615   OP_M (bytemode, sizeflag);
16616 }
16617
16618 /* Display the destination register operand for instructions with
16619    VEX. */
16620
16621 static void
16622 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16623 {
16624   int reg;
16625   const char **names;
16626
16627   if (!need_vex)
16628     abort ();
16629
16630   if (!need_vex_reg)
16631     return;
16632
16633   reg = vex.register_specifier;
16634   if (vex.evex)
16635     {
16636       if (!vex.v)
16637         reg += 16;
16638     }
16639
16640   if (bytemode == vex_scalar_mode)
16641     {
16642       oappend (names_xmm[reg]);
16643       return;
16644     }
16645
16646   switch (vex.length)
16647     {
16648     case 128:
16649       switch (bytemode)
16650         {
16651         case vex_mode:
16652         case vex128_mode:
16653         case vex_vsib_q_w_dq_mode:
16654         case vex_vsib_q_w_d_mode:
16655           names = names_xmm;
16656           break;
16657         case dq_mode:
16658           if (vex.w)
16659             names = names64;
16660           else
16661             names = names32;
16662           break;
16663         case mask_bd_mode:
16664         case mask_mode:
16665           names = names_mask;
16666           break;
16667         default:
16668           abort ();
16669           return;
16670         }
16671       break;
16672     case 256:
16673       switch (bytemode)
16674         {
16675         case vex_mode:
16676         case vex256_mode:
16677           names = names_ymm;
16678           break;
16679         case vex_vsib_q_w_dq_mode:
16680         case vex_vsib_q_w_d_mode:
16681           names = vex.w ? names_ymm : names_xmm;
16682           break;
16683         case mask_bd_mode:
16684         case mask_mode:
16685           names = names_mask;
16686           break;
16687         default:
16688           abort ();
16689           return;
16690         }
16691       break;
16692     case 512:
16693       names = names_zmm;
16694       break;
16695     default:
16696       abort ();
16697       break;
16698     }
16699   oappend (names[reg]);
16700 }
16701
16702 /* Get the VEX immediate byte without moving codep.  */
16703
16704 static unsigned char
16705 get_vex_imm8 (int sizeflag, int opnum)
16706 {
16707   int bytes_before_imm = 0;
16708
16709   if (modrm.mod != 3)
16710     {
16711       /* There are SIB/displacement bytes.  */
16712       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16713         {
16714           /* 32/64 bit address mode */
16715           int base = modrm.rm;
16716
16717           /* Check SIB byte.  */
16718           if (base == 4)
16719             {
16720               FETCH_DATA (the_info, codep + 1);
16721               base = *codep & 7;
16722               /* When decoding the third source, don't increase
16723                  bytes_before_imm as this has already been incremented
16724                  by one in OP_E_memory while decoding the second
16725                  source operand.  */
16726               if (opnum == 0)
16727                 bytes_before_imm++;
16728             }
16729
16730           /* Don't increase bytes_before_imm when decoding the third source,
16731              it has already been incremented by OP_E_memory while decoding
16732              the second source operand.  */
16733           if (opnum == 0)
16734             {
16735               switch (modrm.mod)
16736                 {
16737                   case 0:
16738                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16739                        SIB == 5, there is a 4 byte displacement.  */
16740                     if (base != 5)
16741                       /* No displacement. */
16742                       break;
16743                   case 2:
16744                     /* 4 byte displacement.  */
16745                     bytes_before_imm += 4;
16746                     break;
16747                   case 1:
16748                     /* 1 byte displacement.  */
16749                     bytes_before_imm++;
16750                     break;
16751                 }
16752             }
16753         }
16754       else
16755         {
16756           /* 16 bit address mode */
16757           /* Don't increase bytes_before_imm when decoding the third source,
16758              it has already been incremented by OP_E_memory while decoding
16759              the second source operand.  */
16760           if (opnum == 0)
16761             {
16762               switch (modrm.mod)
16763                 {
16764                 case 0:
16765                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16766                   if (modrm.rm != 6)
16767                     /* No displacement. */
16768                     break;
16769                 case 2:
16770                   /* 2 byte displacement.  */
16771                   bytes_before_imm += 2;
16772                   break;
16773                 case 1:
16774                   /* 1 byte displacement: when decoding the third source,
16775                      don't increase bytes_before_imm as this has already
16776                      been incremented by one in OP_E_memory while decoding
16777                      the second source operand.  */
16778                   if (opnum == 0)
16779                     bytes_before_imm++;
16780
16781                   break;
16782                 }
16783             }
16784         }
16785     }
16786
16787   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16788   return codep [bytes_before_imm];
16789 }
16790
16791 static void
16792 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16793 {
16794   const char **names;
16795
16796   if (reg == -1 && modrm.mod != 3)
16797     {
16798       OP_E_memory (bytemode, sizeflag);
16799       return;
16800     }
16801   else
16802     {
16803       if (reg == -1)
16804         {
16805           reg = modrm.rm;
16806           USED_REX (REX_B);
16807           if (rex & REX_B)
16808             reg += 8;
16809         }
16810       else if (reg > 7 && address_mode != mode_64bit)
16811         BadOp ();
16812     }
16813
16814   switch (vex.length)
16815     {
16816     case 128:
16817       names = names_xmm;
16818       break;
16819     case 256:
16820       names = names_ymm;
16821       break;
16822     default:
16823       abort ();
16824     }
16825   oappend (names[reg]);
16826 }
16827
16828 static void
16829 OP_EX_VexImmW (int bytemode, int sizeflag)
16830 {
16831   int reg = -1;
16832   static unsigned char vex_imm8;
16833
16834   if (vex_w_done == 0)
16835     {
16836       vex_w_done = 1;
16837
16838       /* Skip mod/rm byte.  */
16839       MODRM_CHECK;
16840       codep++;
16841
16842       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16843
16844       if (vex.w)
16845           reg = vex_imm8 >> 4;
16846
16847       OP_EX_VexReg (bytemode, sizeflag, reg);
16848     }
16849   else if (vex_w_done == 1)
16850     {
16851       vex_w_done = 2;
16852
16853       if (!vex.w)
16854           reg = vex_imm8 >> 4;
16855
16856       OP_EX_VexReg (bytemode, sizeflag, reg);
16857     }
16858   else
16859     {
16860       /* Output the imm8 directly.  */
16861       scratchbuf[0] = '$';
16862       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16863       oappend_maybe_intel (scratchbuf);
16864       scratchbuf[0] = '\0';
16865       codep++;
16866     }
16867 }
16868
16869 static void
16870 OP_Vex_2src (int bytemode, int sizeflag)
16871 {
16872   if (modrm.mod == 3)
16873     {
16874       int reg = modrm.rm;
16875       USED_REX (REX_B);
16876       if (rex & REX_B)
16877         reg += 8;
16878       oappend (names_xmm[reg]);
16879     }
16880   else
16881     {
16882       if (intel_syntax
16883           && (bytemode == v_mode || bytemode == v_swap_mode))
16884         {
16885           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16886           used_prefixes |= (prefixes & PREFIX_DATA);
16887         }
16888       OP_E (bytemode, sizeflag);
16889     }
16890 }
16891
16892 static void
16893 OP_Vex_2src_1 (int bytemode, int sizeflag)
16894 {
16895   if (modrm.mod == 3)
16896     {
16897       /* Skip mod/rm byte.   */
16898       MODRM_CHECK;
16899       codep++;
16900     }
16901
16902   if (vex.w)
16903     oappend (names_xmm[vex.register_specifier]);
16904   else
16905     OP_Vex_2src (bytemode, sizeflag);
16906 }
16907
16908 static void
16909 OP_Vex_2src_2 (int bytemode, int sizeflag)
16910 {
16911   if (vex.w)
16912     OP_Vex_2src (bytemode, sizeflag);
16913   else
16914     oappend (names_xmm[vex.register_specifier]);
16915 }
16916
16917 static void
16918 OP_EX_VexW (int bytemode, int sizeflag)
16919 {
16920   int reg = -1;
16921
16922   if (!vex_w_done)
16923     {
16924       vex_w_done = 1;
16925
16926       /* Skip mod/rm byte.  */
16927       MODRM_CHECK;
16928       codep++;
16929
16930       if (vex.w)
16931         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16932     }
16933   else
16934     {
16935       if (!vex.w)
16936         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16937     }
16938
16939   OP_EX_VexReg (bytemode, sizeflag, reg);
16940 }
16941
16942 static void
16943 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16944              int sizeflag ATTRIBUTE_UNUSED)
16945 {
16946   /* Skip the immediate byte and check for invalid bits.  */
16947   FETCH_DATA (the_info, codep + 1);
16948   if (*codep++ & 0xf)
16949     BadOp ();
16950 }
16951
16952 static void
16953 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16954 {
16955   int reg;
16956   const char **names;
16957
16958   FETCH_DATA (the_info, codep + 1);
16959   reg = *codep++;
16960
16961   if (bytemode != x_mode)
16962     abort ();
16963
16964   if (reg & 0xf)
16965       BadOp ();
16966
16967   reg >>= 4;
16968   if (reg > 7 && address_mode != mode_64bit)
16969     BadOp ();
16970
16971   switch (vex.length)
16972     {
16973     case 128:
16974       names = names_xmm;
16975       break;
16976     case 256:
16977       names = names_ymm;
16978       break;
16979     default:
16980       abort ();
16981     }
16982   oappend (names[reg]);
16983 }
16984
16985 static void
16986 OP_XMM_VexW (int bytemode, int sizeflag)
16987 {
16988   /* Turn off the REX.W bit since it is used for swapping operands
16989      now.  */
16990   rex &= ~REX_W;
16991   OP_XMM (bytemode, sizeflag);
16992 }
16993
16994 static void
16995 OP_EX_Vex (int bytemode, int sizeflag)
16996 {
16997   if (modrm.mod != 3)
16998     {
16999       if (vex.register_specifier != 0)
17000         BadOp ();
17001       need_vex_reg = 0;
17002     }
17003   OP_EX (bytemode, sizeflag);
17004 }
17005
17006 static void
17007 OP_XMM_Vex (int bytemode, int sizeflag)
17008 {
17009   if (modrm.mod != 3)
17010     {
17011       if (vex.register_specifier != 0)
17012         BadOp ();
17013       need_vex_reg = 0;
17014     }
17015   OP_XMM (bytemode, sizeflag);
17016 }
17017
17018 static void
17019 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17020 {
17021   switch (vex.length)
17022     {
17023     case 128:
17024       mnemonicendp = stpcpy (obuf, "vzeroupper");
17025       break;
17026     case 256:
17027       mnemonicendp = stpcpy (obuf, "vzeroall");
17028       break;
17029     default:
17030       abort ();
17031     }
17032 }
17033
17034 static struct op vex_cmp_op[] =
17035 {
17036   { STRING_COMMA_LEN ("eq") },
17037   { STRING_COMMA_LEN ("lt") },
17038   { STRING_COMMA_LEN ("le") },
17039   { STRING_COMMA_LEN ("unord") },
17040   { STRING_COMMA_LEN ("neq") },
17041   { STRING_COMMA_LEN ("nlt") },
17042   { STRING_COMMA_LEN ("nle") },
17043   { STRING_COMMA_LEN ("ord") },
17044   { STRING_COMMA_LEN ("eq_uq") },
17045   { STRING_COMMA_LEN ("nge") },
17046   { STRING_COMMA_LEN ("ngt") },
17047   { STRING_COMMA_LEN ("false") },
17048   { STRING_COMMA_LEN ("neq_oq") },
17049   { STRING_COMMA_LEN ("ge") },
17050   { STRING_COMMA_LEN ("gt") },
17051   { STRING_COMMA_LEN ("true") },
17052   { STRING_COMMA_LEN ("eq_os") },
17053   { STRING_COMMA_LEN ("lt_oq") },
17054   { STRING_COMMA_LEN ("le_oq") },
17055   { STRING_COMMA_LEN ("unord_s") },
17056   { STRING_COMMA_LEN ("neq_us") },
17057   { STRING_COMMA_LEN ("nlt_uq") },
17058   { STRING_COMMA_LEN ("nle_uq") },
17059   { STRING_COMMA_LEN ("ord_s") },
17060   { STRING_COMMA_LEN ("eq_us") },
17061   { STRING_COMMA_LEN ("nge_uq") },
17062   { STRING_COMMA_LEN ("ngt_uq") },
17063   { STRING_COMMA_LEN ("false_os") },
17064   { STRING_COMMA_LEN ("neq_os") },
17065   { STRING_COMMA_LEN ("ge_oq") },
17066   { STRING_COMMA_LEN ("gt_oq") },
17067   { STRING_COMMA_LEN ("true_us") },
17068 };
17069
17070 static void
17071 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17072 {
17073   unsigned int cmp_type;
17074
17075   FETCH_DATA (the_info, codep + 1);
17076   cmp_type = *codep++ & 0xff;
17077   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17078     {
17079       char suffix [3];
17080       char *p = mnemonicendp - 2;
17081       suffix[0] = p[0];
17082       suffix[1] = p[1];
17083       suffix[2] = '\0';
17084       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17085       mnemonicendp += vex_cmp_op[cmp_type].len;
17086     }
17087   else
17088     {
17089       /* We have a reserved extension byte.  Output it directly.  */
17090       scratchbuf[0] = '$';
17091       print_operand_value (scratchbuf + 1, 1, cmp_type);
17092       oappend_maybe_intel (scratchbuf);
17093       scratchbuf[0] = '\0';
17094     }
17095 }
17096
17097 static void
17098 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17099              int sizeflag ATTRIBUTE_UNUSED)
17100 {
17101   unsigned int cmp_type;
17102
17103   if (!vex.evex)
17104     abort ();
17105
17106   FETCH_DATA (the_info, codep + 1);
17107   cmp_type = *codep++ & 0xff;
17108   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17109      If it's the case, print suffix, otherwise - print the immediate.  */
17110   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17111       && cmp_type != 3
17112       && cmp_type != 7)
17113     {
17114       char suffix [3];
17115       char *p = mnemonicendp - 2;
17116
17117       /* vpcmp* can have both one- and two-lettered suffix.  */
17118       if (p[0] == 'p')
17119         {
17120           p++;
17121           suffix[0] = p[0];
17122           suffix[1] = '\0';
17123         }
17124       else
17125         {
17126           suffix[0] = p[0];
17127           suffix[1] = p[1];
17128           suffix[2] = '\0';
17129         }
17130
17131       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17132       mnemonicendp += simd_cmp_op[cmp_type].len;
17133     }
17134   else
17135     {
17136       /* We have a reserved extension byte.  Output it directly.  */
17137       scratchbuf[0] = '$';
17138       print_operand_value (scratchbuf + 1, 1, cmp_type);
17139       oappend_maybe_intel (scratchbuf);
17140       scratchbuf[0] = '\0';
17141     }
17142 }
17143
17144 static const struct op pclmul_op[] =
17145 {
17146   { STRING_COMMA_LEN ("lql") },
17147   { STRING_COMMA_LEN ("hql") },
17148   { STRING_COMMA_LEN ("lqh") },
17149   { STRING_COMMA_LEN ("hqh") }
17150 };
17151
17152 static void
17153 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17154               int sizeflag ATTRIBUTE_UNUSED)
17155 {
17156   unsigned int pclmul_type;
17157
17158   FETCH_DATA (the_info, codep + 1);
17159   pclmul_type = *codep++ & 0xff;
17160   switch (pclmul_type)
17161     {
17162     case 0x10:
17163       pclmul_type = 2;
17164       break;
17165     case 0x11:
17166       pclmul_type = 3;
17167       break;
17168     default:
17169       break;
17170     }
17171   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17172     {
17173       char suffix [4];
17174       char *p = mnemonicendp - 3;
17175       suffix[0] = p[0];
17176       suffix[1] = p[1];
17177       suffix[2] = p[2];
17178       suffix[3] = '\0';
17179       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17180       mnemonicendp += pclmul_op[pclmul_type].len;
17181     }
17182   else
17183     {
17184       /* We have a reserved extension byte.  Output it directly.  */
17185       scratchbuf[0] = '$';
17186       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17187       oappend_maybe_intel (scratchbuf);
17188       scratchbuf[0] = '\0';
17189     }
17190 }
17191
17192 static void
17193 MOVBE_Fixup (int bytemode, int sizeflag)
17194 {
17195   /* Add proper suffix to "movbe".  */
17196   char *p = mnemonicendp;
17197
17198   switch (bytemode)
17199     {
17200     case v_mode:
17201       if (intel_syntax)
17202         goto skip;
17203
17204       USED_REX (REX_W);
17205       if (sizeflag & SUFFIX_ALWAYS)
17206         {
17207           if (rex & REX_W)
17208             *p++ = 'q';
17209           else
17210             {
17211               if (sizeflag & DFLAG)
17212                 *p++ = 'l';
17213               else
17214                 *p++ = 'w';
17215               used_prefixes |= (prefixes & PREFIX_DATA);
17216             }
17217         }
17218       break;
17219     default:
17220       oappend (INTERNAL_DISASSEMBLER_ERROR);
17221       break;
17222     }
17223   mnemonicendp = p;
17224   *p = '\0';
17225
17226 skip:
17227   OP_M (bytemode, sizeflag);
17228 }
17229
17230 static void
17231 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17232 {
17233   int reg;
17234   const char **names;
17235
17236   /* Skip mod/rm byte.  */
17237   MODRM_CHECK;
17238   codep++;
17239
17240   if (vex.w)
17241     names = names64;
17242   else
17243     names = names32;
17244
17245   reg = modrm.rm;
17246   USED_REX (REX_B);
17247   if (rex & REX_B)
17248     reg += 8;
17249
17250   oappend (names[reg]);
17251 }
17252
17253 static void
17254 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17255 {
17256   const char **names;
17257
17258   if (vex.w)
17259     names = names64;
17260   else
17261     names = names32;
17262
17263   oappend (names[vex.register_specifier]);
17264 }
17265
17266 static void
17267 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17268 {
17269   if (!vex.evex
17270       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17271     abort ();
17272
17273   USED_REX (REX_R);
17274   if ((rex & REX_R) != 0 || !vex.r)
17275     {
17276       BadOp ();
17277       return;
17278     }
17279
17280   oappend (names_mask [modrm.reg]);
17281 }
17282
17283 static void
17284 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17285 {
17286   if (!vex.evex
17287       || (bytemode != evex_rounding_mode
17288           && bytemode != evex_sae_mode))
17289     abort ();
17290   if (modrm.mod == 3 && vex.b)
17291     switch (bytemode)
17292       {
17293       case evex_rounding_mode:
17294         oappend (names_rounding[vex.ll]);
17295         break;
17296       case evex_sae_mode:
17297         oappend ("{sae}");
17298         break;
17299       default:
17300         break;
17301       }
17302 }