1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
44 static int print_insn (bfd_vma
, disassemble_info
*);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma
);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma
);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma
get64 (void);
59 static bfd_signed_vma
get32 (void);
60 static bfd_signed_vma
get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma
, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_VexR (int, int);
91 static void OP_VexW (int, int);
92 static void OP_Rounding (int, int);
93 static void OP_REG_VexI4 (int, int);
94 static void OP_VexI4 (int, int);
95 static void PCLMUL_Fixup (int, int);
96 static void VPCMP_Fixup (int, int);
97 static void VPCOM_Fixup (int, int);
98 static void OP_0f07 (int, int);
99 static void OP_Monitor (int, int);
100 static void OP_Mwait (int, int);
101 static void NOP_Fixup1 (int, int);
102 static void NOP_Fixup2 (int, int);
103 static void OP_3DNowSuffix (int, int);
104 static void CMP_Fixup (int, int);
105 static void BadOp (void);
106 static void REP_Fixup (int, int);
107 static void SEP_Fixup (int, int);
108 static void BND_Fixup (int, int);
109 static void NOTRACK_Fixup (int, int);
110 static void HLE_Fixup1 (int, int);
111 static void HLE_Fixup2 (int, int);
112 static void HLE_Fixup3 (int, int);
113 static void CMPXCHG8B_Fixup (int, int);
114 static void XMM_Fixup (int, int);
115 static void FXSAVE_Fixup (int, int);
117 static void MOVSXD_Fixup (int, int);
119 static void OP_Mask (int, int);
122 /* Points to first byte not fetched. */
123 bfd_byte
*max_fetched
;
124 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
127 OPCODES_SIGJMP_BUF bailout
;
137 enum address_mode address_mode
;
139 /* Flags for the prefixes for the current instruction. See below. */
142 /* REX prefix the current instruction. See below. */
144 /* Bits of REX we've already used. */
146 /* Mark parts used in the REX prefix. When we are testing for
147 empty prefix (for 8bit register REX extension), just mask it
148 out. Otherwise test for REX bit is excuse for existence of REX
149 only in case value is nonzero. */
150 #define USED_REX(value) \
155 rex_used |= (value) | REX_OPCODE; \
158 rex_used |= REX_OPCODE; \
161 /* Flags for prefixes which we somehow handled when printing the
162 current instruction. */
163 static int used_prefixes
;
165 /* Flags stored in PREFIXES. */
166 #define PREFIX_REPZ 1
167 #define PREFIX_REPNZ 2
168 #define PREFIX_LOCK 4
170 #define PREFIX_SS 0x10
171 #define PREFIX_DS 0x20
172 #define PREFIX_ES 0x40
173 #define PREFIX_FS 0x80
174 #define PREFIX_GS 0x100
175 #define PREFIX_DATA 0x200
176 #define PREFIX_ADDR 0x400
177 #define PREFIX_FWAIT 0x800
179 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
180 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
182 #define FETCH_DATA(info, addr) \
183 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
184 ? 1 : fetch_data ((info), (addr)))
187 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
190 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
191 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
193 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
194 status
= (*info
->read_memory_func
) (start
,
196 addr
- priv
->max_fetched
,
202 /* If we did manage to read at least one byte, then
203 print_insn_i386 will do something sensible. Otherwise, print
204 an error. We do that here because this is where we know
206 if (priv
->max_fetched
== priv
->the_buffer
)
207 (*info
->memory_error_func
) (status
, start
, info
);
208 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
211 priv
->max_fetched
= addr
;
215 /* Possible values for prefix requirement. */
216 #define PREFIX_IGNORED_SHIFT 16
217 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
218 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
219 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
220 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
221 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
223 /* Opcode prefixes. */
224 #define PREFIX_OPCODE (PREFIX_REPZ \
228 /* Prefixes ignored. */
229 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
230 | PREFIX_IGNORED_REPNZ \
231 | PREFIX_IGNORED_DATA)
233 #define XX { NULL, 0 }
234 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
236 #define Eb { OP_E, b_mode }
237 #define Ebnd { OP_E, bnd_mode }
238 #define EbS { OP_E, b_swap_mode }
239 #define EbndS { OP_E, bnd_swap_mode }
240 #define Ev { OP_E, v_mode }
241 #define Eva { OP_E, va_mode }
242 #define Ev_bnd { OP_E, v_bnd_mode }
243 #define EvS { OP_E, v_swap_mode }
244 #define Ed { OP_E, d_mode }
245 #define Edq { OP_E, dq_mode }
246 #define Edqw { OP_E, dqw_mode }
247 #define Edqb { OP_E, dqb_mode }
248 #define Edb { OP_E, db_mode }
249 #define Edw { OP_E, dw_mode }
250 #define Edqd { OP_E, dqd_mode }
251 #define Eq { OP_E, q_mode }
252 #define indirEv { OP_indirE, indir_v_mode }
253 #define indirEp { OP_indirE, f_mode }
254 #define stackEv { OP_E, stack_v_mode }
255 #define Em { OP_E, m_mode }
256 #define Ew { OP_E, w_mode }
257 #define M { OP_M, 0 } /* lea, lgdt, etc. */
258 #define Ma { OP_M, a_mode }
259 #define Mb { OP_M, b_mode }
260 #define Md { OP_M, d_mode }
261 #define Mo { OP_M, o_mode }
262 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
263 #define Mq { OP_M, q_mode }
264 #define Mv { OP_M, v_mode }
265 #define Mv_bnd { OP_M, v_bndmk_mode }
266 #define Mx { OP_M, x_mode }
267 #define Mxmm { OP_M, xmm_mode }
268 #define Gb { OP_G, b_mode }
269 #define Gbnd { OP_G, bnd_mode }
270 #define Gv { OP_G, v_mode }
271 #define Gd { OP_G, d_mode }
272 #define Gdq { OP_G, dq_mode }
273 #define Gm { OP_G, m_mode }
274 #define Gva { OP_G, va_mode }
275 #define Gw { OP_G, w_mode }
276 #define Ib { OP_I, b_mode }
277 #define sIb { OP_sI, b_mode } /* sign extened byte */
278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
279 #define Iv { OP_I, v_mode }
280 #define sIv { OP_sI, v_mode }
281 #define Iv64 { OP_I64, v_mode }
282 #define Id { OP_I, d_mode }
283 #define Iw { OP_I, w_mode }
284 #define I1 { OP_I, const_1_mode }
285 #define Jb { OP_J, b_mode }
286 #define Jv { OP_J, v_mode }
287 #define Jdqw { OP_J, dqw_mode }
288 #define Cm { OP_C, m_mode }
289 #define Dm { OP_D, m_mode }
290 #define Td { OP_T, d_mode }
291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
293 #define RMeAX { OP_REG, eAX_reg }
294 #define RMeBX { OP_REG, eBX_reg }
295 #define RMeCX { OP_REG, eCX_reg }
296 #define RMeDX { OP_REG, eDX_reg }
297 #define RMeSP { OP_REG, eSP_reg }
298 #define RMeBP { OP_REG, eBP_reg }
299 #define RMeSI { OP_REG, eSI_reg }
300 #define RMeDI { OP_REG, eDI_reg }
301 #define RMrAX { OP_REG, rAX_reg }
302 #define RMrBX { OP_REG, rBX_reg }
303 #define RMrCX { OP_REG, rCX_reg }
304 #define RMrDX { OP_REG, rDX_reg }
305 #define RMrSP { OP_REG, rSP_reg }
306 #define RMrBP { OP_REG, rBP_reg }
307 #define RMrSI { OP_REG, rSI_reg }
308 #define RMrDI { OP_REG, rDI_reg }
309 #define RMAL { OP_REG, al_reg }
310 #define RMCL { OP_REG, cl_reg }
311 #define RMDL { OP_REG, dl_reg }
312 #define RMBL { OP_REG, bl_reg }
313 #define RMAH { OP_REG, ah_reg }
314 #define RMCH { OP_REG, ch_reg }
315 #define RMDH { OP_REG, dh_reg }
316 #define RMBH { OP_REG, bh_reg }
317 #define RMAX { OP_REG, ax_reg }
318 #define RMDX { OP_REG, dx_reg }
320 #define eAX { OP_IMREG, eAX_reg }
321 #define AL { OP_IMREG, al_reg }
322 #define CL { OP_IMREG, cl_reg }
323 #define zAX { OP_IMREG, z_mode_ax_reg }
324 #define indirDX { OP_IMREG, indir_dx_reg }
326 #define Sw { OP_SEG, w_mode }
327 #define Sv { OP_SEG, v_mode }
328 #define Ap { OP_DIR, 0 }
329 #define Ob { OP_OFF64, b_mode }
330 #define Ov { OP_OFF64, v_mode }
331 #define Xb { OP_DSreg, eSI_reg }
332 #define Xv { OP_DSreg, eSI_reg }
333 #define Xz { OP_DSreg, eSI_reg }
334 #define Yb { OP_ESreg, eDI_reg }
335 #define Yv { OP_ESreg, eDI_reg }
336 #define DSBX { OP_DSreg, eBX_reg }
338 #define es { OP_REG, es_reg }
339 #define ss { OP_REG, ss_reg }
340 #define cs { OP_REG, cs_reg }
341 #define ds { OP_REG, ds_reg }
342 #define fs { OP_REG, fs_reg }
343 #define gs { OP_REG, gs_reg }
345 #define MX { OP_MMX, 0 }
346 #define XM { OP_XMM, 0 }
347 #define XMScalar { OP_XMM, scalar_mode }
348 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
349 #define XMM { OP_XMM, xmm_mode }
350 #define TMM { OP_XMM, tmm_mode }
351 #define XMxmmq { OP_XMM, xmmq_mode }
352 #define EM { OP_EM, v_mode }
353 #define EMS { OP_EM, v_swap_mode }
354 #define EMd { OP_EM, d_mode }
355 #define EMx { OP_EM, x_mode }
356 #define EXbwUnit { OP_EX, bw_unit_mode }
357 #define EXw { OP_EX, w_mode }
358 #define EXd { OP_EX, d_mode }
359 #define EXdS { OP_EX, d_swap_mode }
360 #define EXq { OP_EX, q_mode }
361 #define EXqS { OP_EX, q_swap_mode }
362 #define EXx { OP_EX, x_mode }
363 #define EXxS { OP_EX, x_swap_mode }
364 #define EXxmm { OP_EX, xmm_mode }
365 #define EXymm { OP_EX, ymm_mode }
366 #define EXtmm { OP_EX, tmm_mode }
367 #define EXxmmq { OP_EX, xmmq_mode }
368 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
369 #define EXxmm_mb { OP_EX, xmm_mb_mode }
370 #define EXxmm_mw { OP_EX, xmm_mw_mode }
371 #define EXxmm_md { OP_EX, xmm_md_mode }
372 #define EXxmm_mq { OP_EX, xmm_mq_mode }
373 #define EXxmmdw { OP_EX, xmmdw_mode }
374 #define EXxmmqd { OP_EX, xmmqd_mode }
375 #define EXymmq { OP_EX, ymmq_mode }
376 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
377 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
378 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
379 #define MS { OP_MS, v_mode }
380 #define XS { OP_XS, v_mode }
381 #define EMCq { OP_EMC, q_mode }
382 #define MXC { OP_MXC, 0 }
383 #define OPSUF { OP_3DNowSuffix, 0 }
384 #define SEP { SEP_Fixup, 0 }
385 #define CMP { CMP_Fixup, 0 }
386 #define XMM0 { XMM_Fixup, 0 }
387 #define FXSAVE { FXSAVE_Fixup, 0 }
389 #define Vex { OP_VEX, vex_mode }
390 #define VexW { OP_VexW, vex_mode }
391 #define VexScalar { OP_VEX, vex_scalar_mode }
392 #define VexScalarR { OP_VexR, vex_scalar_mode }
393 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
394 #define VexGdq { OP_VEX, dq_mode }
395 #define VexTmm { OP_VEX, tmm_mode }
396 #define XMVexI4 { OP_REG_VexI4, x_mode }
397 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
398 #define VexI4 { OP_VexI4, 0 }
399 #define PCLMUL { PCLMUL_Fixup, 0 }
400 #define VPCMP { VPCMP_Fixup, 0 }
401 #define VPCOM { VPCOM_Fixup, 0 }
403 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
404 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
405 #define EXxEVexS { OP_Rounding, evex_sae_mode }
407 #define XMask { OP_Mask, mask_mode }
408 #define MaskG { OP_G, mask_mode }
409 #define MaskE { OP_E, mask_mode }
410 #define MaskBDE { OP_E, mask_bd_mode }
411 #define MaskVex { OP_VEX, mask_mode }
413 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
414 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
415 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
416 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
418 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
420 /* Used handle "rep" prefix for string instructions. */
421 #define Xbr { REP_Fixup, eSI_reg }
422 #define Xvr { REP_Fixup, eSI_reg }
423 #define Ybr { REP_Fixup, eDI_reg }
424 #define Yvr { REP_Fixup, eDI_reg }
425 #define Yzr { REP_Fixup, eDI_reg }
426 #define indirDXr { REP_Fixup, indir_dx_reg }
427 #define ALr { REP_Fixup, al_reg }
428 #define eAXr { REP_Fixup, eAX_reg }
430 /* Used handle HLE prefix for lockable instructions. */
431 #define Ebh1 { HLE_Fixup1, b_mode }
432 #define Evh1 { HLE_Fixup1, v_mode }
433 #define Ebh2 { HLE_Fixup2, b_mode }
434 #define Evh2 { HLE_Fixup2, v_mode }
435 #define Ebh3 { HLE_Fixup3, b_mode }
436 #define Evh3 { HLE_Fixup3, v_mode }
438 #define BND { BND_Fixup, 0 }
439 #define NOTRACK { NOTRACK_Fixup, 0 }
441 #define cond_jump_flag { NULL, cond_jump_mode }
442 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
444 /* bits in sizeflag */
445 #define SUFFIX_ALWAYS 4
453 /* byte operand with operand swapped */
455 /* byte operand, sign extend like 'T' suffix */
457 /* operand size depends on prefixes */
459 /* operand size depends on prefixes with operand swapped */
461 /* operand size depends on address prefix */
465 /* double word operand */
467 /* double word operand with operand swapped */
469 /* quad word operand */
471 /* quad word operand with operand swapped */
473 /* ten-byte operand */
475 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
476 broadcast enabled. */
478 /* Similar to x_mode, but with different EVEX mem shifts. */
480 /* Similar to x_mode, but with yet different EVEX mem shifts. */
482 /* Similar to x_mode, but with disabled broadcast. */
484 /* Similar to x_mode, but with operands swapped and disabled broadcast
487 /* 16-byte XMM operand */
489 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
490 memory operand (depending on vector length). Broadcast isn't
493 /* Same as xmmq_mode, but broadcast is allowed. */
494 evex_half_bcst_xmmq_mode
,
495 /* XMM register or byte memory operand */
497 /* XMM register or word memory operand */
499 /* XMM register or double word memory operand */
501 /* XMM register or quad word memory operand */
503 /* 16-byte XMM, word, double word or quad word operand. */
505 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
507 /* 32-byte YMM operand */
509 /* quad word, ymmword or zmmword memory operand. */
511 /* 32-byte YMM or 16-byte word operand */
515 /* d_mode in 32bit, q_mode in 64bit mode. */
517 /* pair of v_mode operands */
523 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
525 /* operand size depends on REX prefixes. */
527 /* registers like dq_mode, memory like w_mode, displacements like
528 v_mode without considering Intel64 ISA. */
532 /* bounds operand with operand swapped */
534 /* 4- or 6-byte pointer operand */
537 /* v_mode for indirect branch opcodes. */
539 /* v_mode for stack-related opcodes. */
541 /* non-quad operand size depends on prefixes */
543 /* 16-byte operand */
545 /* registers like dq_mode, memory like b_mode. */
547 /* registers like d_mode, memory like b_mode. */
549 /* registers like d_mode, memory like w_mode. */
551 /* registers like dq_mode, memory like d_mode. */
553 /* normal vex mode */
556 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
557 vex_vsib_d_w_dq_mode
,
558 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
560 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
561 vex_vsib_q_w_dq_mode
,
562 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
564 /* mandatory non-vector SIB. */
567 /* scalar, ignore vector length. */
569 /* like vex_mode, ignore vector length. */
571 /* Operand size depends on the VEX.W bit, ignore vector length. */
572 vex_scalar_w_dq_mode
,
574 /* Static rounding. */
576 /* Static rounding, 64-bit mode only. */
577 evex_rounding_64_mode
,
578 /* Supress all exceptions. */
581 /* Mask register operand. */
583 /* Mask register operand. */
651 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
653 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
654 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
655 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
656 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
657 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
658 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
659 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
660 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
661 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
662 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
663 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
664 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
665 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
666 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
667 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
668 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
695 REG_0F3A0F_PREFIX_1_MOD_3
,
708 REG_VEX_0F3849_X86_64_P_0_W_0_M_1
,
713 REG_0FXOP_09_12_M_1_L_0
,
807 MOD_VEX_0F12_PREFIX_0
,
808 MOD_VEX_0F12_PREFIX_2
,
810 MOD_VEX_0F16_PREFIX_0
,
811 MOD_VEX_0F16_PREFIX_2
,
814 MOD_VEX_W_0_0F41_P_0_LEN_1
,
815 MOD_VEX_W_1_0F41_P_0_LEN_1
,
816 MOD_VEX_W_0_0F41_P_2_LEN_1
,
817 MOD_VEX_W_1_0F41_P_2_LEN_1
,
818 MOD_VEX_W_0_0F42_P_0_LEN_1
,
819 MOD_VEX_W_1_0F42_P_0_LEN_1
,
820 MOD_VEX_W_0_0F42_P_2_LEN_1
,
821 MOD_VEX_W_1_0F42_P_2_LEN_1
,
822 MOD_VEX_W_0_0F44_P_0_LEN_1
,
823 MOD_VEX_W_1_0F44_P_0_LEN_1
,
824 MOD_VEX_W_0_0F44_P_2_LEN_1
,
825 MOD_VEX_W_1_0F44_P_2_LEN_1
,
826 MOD_VEX_W_0_0F45_P_0_LEN_1
,
827 MOD_VEX_W_1_0F45_P_0_LEN_1
,
828 MOD_VEX_W_0_0F45_P_2_LEN_1
,
829 MOD_VEX_W_1_0F45_P_2_LEN_1
,
830 MOD_VEX_W_0_0F46_P_0_LEN_1
,
831 MOD_VEX_W_1_0F46_P_0_LEN_1
,
832 MOD_VEX_W_0_0F46_P_2_LEN_1
,
833 MOD_VEX_W_1_0F46_P_2_LEN_1
,
834 MOD_VEX_W_0_0F47_P_0_LEN_1
,
835 MOD_VEX_W_1_0F47_P_0_LEN_1
,
836 MOD_VEX_W_0_0F47_P_2_LEN_1
,
837 MOD_VEX_W_1_0F47_P_2_LEN_1
,
838 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
839 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
840 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
841 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
842 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
843 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
844 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
856 MOD_VEX_W_0_0F91_P_0_LEN_0
,
857 MOD_VEX_W_1_0F91_P_0_LEN_0
,
858 MOD_VEX_W_0_0F91_P_2_LEN_0
,
859 MOD_VEX_W_1_0F91_P_2_LEN_0
,
860 MOD_VEX_W_0_0F92_P_0_LEN_0
,
861 MOD_VEX_W_0_0F92_P_2_LEN_0
,
862 MOD_VEX_0F92_P_3_LEN_0
,
863 MOD_VEX_W_0_0F93_P_0_LEN_0
,
864 MOD_VEX_W_0_0F93_P_2_LEN_0
,
865 MOD_VEX_0F93_P_3_LEN_0
,
866 MOD_VEX_W_0_0F98_P_0_LEN_0
,
867 MOD_VEX_W_1_0F98_P_0_LEN_0
,
868 MOD_VEX_W_0_0F98_P_2_LEN_0
,
869 MOD_VEX_W_1_0F98_P_2_LEN_0
,
870 MOD_VEX_W_0_0F99_P_0_LEN_0
,
871 MOD_VEX_W_1_0F99_P_0_LEN_0
,
872 MOD_VEX_W_0_0F99_P_2_LEN_0
,
873 MOD_VEX_W_1_0F99_P_2_LEN_0
,
878 MOD_VEX_0FF0_PREFIX_3
,
885 MOD_VEX_0F3849_X86_64_P_0_W_0
,
886 MOD_VEX_0F3849_X86_64_P_2_W_0
,
887 MOD_VEX_0F3849_X86_64_P_3_W_0
,
888 MOD_VEX_0F384B_X86_64_P_1_W_0
,
889 MOD_VEX_0F384B_X86_64_P_2_W_0
,
890 MOD_VEX_0F384B_X86_64_P_3_W_0
,
892 MOD_VEX_0F385C_X86_64_P_1_W_0
,
893 MOD_VEX_0F385E_X86_64_P_0_W_0
,
894 MOD_VEX_0F385E_X86_64_P_1_W_0
,
895 MOD_VEX_0F385E_X86_64_P_2_W_0
,
896 MOD_VEX_0F385E_X86_64_P_3_W_0
,
906 MOD_EVEX_0F12_PREFIX_0
,
907 MOD_EVEX_0F12_PREFIX_2
,
909 MOD_EVEX_0F16_PREFIX_0
,
910 MOD_EVEX_0F16_PREFIX_2
,
918 MOD_EVEX_0F382A_P_1_W_1
,
920 MOD_EVEX_0F383A_P_1_W_0
,
928 MOD_EVEX_0F38C6_REG_1
,
929 MOD_EVEX_0F38C6_REG_2
,
930 MOD_EVEX_0F38C6_REG_5
,
931 MOD_EVEX_0F38C6_REG_6
,
932 MOD_EVEX_0F38C7_REG_1
,
933 MOD_EVEX_0F38C7_REG_2
,
934 MOD_EVEX_0F38C7_REG_5
,
935 MOD_EVEX_0F38C7_REG_6
948 RM_0F1E_P_1_MOD_3_REG_7
,
949 RM_0F3A0F_P_1_MOD_3_REG_0
,
950 RM_0FAE_REG_6_MOD_3_P_0
,
952 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
958 PREFIX_0F01_REG_1_RM_4
,
959 PREFIX_0F01_REG_1_RM_5
,
960 PREFIX_0F01_REG_1_RM_6
,
961 PREFIX_0F01_REG_1_RM_7
,
962 PREFIX_0F01_REG_3_RM_1
,
963 PREFIX_0F01_REG_5_MOD_0
,
964 PREFIX_0F01_REG_5_MOD_3_RM_0
,
965 PREFIX_0F01_REG_5_MOD_3_RM_1
,
966 PREFIX_0F01_REG_5_MOD_3_RM_2
,
967 PREFIX_0F01_REG_5_MOD_3_RM_4
,
968 PREFIX_0F01_REG_5_MOD_3_RM_5
,
969 PREFIX_0F01_REG_5_MOD_3_RM_6
,
970 PREFIX_0F01_REG_5_MOD_3_RM_7
,
971 PREFIX_0F01_REG_7_MOD_3_RM_2
,
1009 PREFIX_0FAE_REG_0_MOD_3
,
1010 PREFIX_0FAE_REG_1_MOD_3
,
1011 PREFIX_0FAE_REG_2_MOD_3
,
1012 PREFIX_0FAE_REG_3_MOD_3
,
1013 PREFIX_0FAE_REG_4_MOD_0
,
1014 PREFIX_0FAE_REG_4_MOD_3
,
1015 PREFIX_0FAE_REG_5_MOD_3
,
1016 PREFIX_0FAE_REG_6_MOD_0
,
1017 PREFIX_0FAE_REG_6_MOD_3
,
1018 PREFIX_0FAE_REG_7_MOD_0
,
1023 PREFIX_0FC7_REG_6_MOD_0
,
1024 PREFIX_0FC7_REG_6_MOD_3
,
1025 PREFIX_0FC7_REG_7_MOD_3
,
1088 PREFIX_VEX_0F3849_X86_64
,
1089 PREFIX_VEX_0F384B_X86_64
,
1090 PREFIX_VEX_0F385C_X86_64
,
1091 PREFIX_VEX_0F385E_X86_64
,
1190 X86_64_0F01_REG_1_RM_5_PREFIX_2
,
1191 X86_64_0F01_REG_1_RM_6_PREFIX_2
,
1192 X86_64_0F01_REG_1_RM_7_PREFIX_2
,
1201 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1
,
1202 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1
,
1203 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1
,
1204 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1
,
1205 X86_64_0FC7_REG_6_MOD_3_PREFIX_1
1210 THREE_BYTE_0F38
= 0,
1237 VEX_LEN_0F12_P_0_M_0
= 0,
1238 VEX_LEN_0F12_P_0_M_1
,
1239 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1241 VEX_LEN_0F16_P_0_M_0
,
1242 VEX_LEN_0F16_P_0_M_1
,
1243 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1279 VEX_LEN_0FAE_R_2_M_0
,
1280 VEX_LEN_0FAE_R_3_M_0
,
1290 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
,
1291 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
,
1292 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
,
1293 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
,
1294 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
,
1295 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
,
1296 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
,
1298 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
,
1299 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
,
1300 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
,
1301 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
,
1302 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
,
1342 VEX_LEN_0FXOP_08_85
,
1343 VEX_LEN_0FXOP_08_86
,
1344 VEX_LEN_0FXOP_08_87
,
1345 VEX_LEN_0FXOP_08_8E
,
1346 VEX_LEN_0FXOP_08_8F
,
1347 VEX_LEN_0FXOP_08_95
,
1348 VEX_LEN_0FXOP_08_96
,
1349 VEX_LEN_0FXOP_08_97
,
1350 VEX_LEN_0FXOP_08_9E
,
1351 VEX_LEN_0FXOP_08_9F
,
1352 VEX_LEN_0FXOP_08_A3
,
1353 VEX_LEN_0FXOP_08_A6
,
1354 VEX_LEN_0FXOP_08_B6
,
1355 VEX_LEN_0FXOP_08_C0
,
1356 VEX_LEN_0FXOP_08_C1
,
1357 VEX_LEN_0FXOP_08_C2
,
1358 VEX_LEN_0FXOP_08_C3
,
1359 VEX_LEN_0FXOP_08_CC
,
1360 VEX_LEN_0FXOP_08_CD
,
1361 VEX_LEN_0FXOP_08_CE
,
1362 VEX_LEN_0FXOP_08_CF
,
1363 VEX_LEN_0FXOP_08_EC
,
1364 VEX_LEN_0FXOP_08_ED
,
1365 VEX_LEN_0FXOP_08_EE
,
1366 VEX_LEN_0FXOP_08_EF
,
1367 VEX_LEN_0FXOP_09_01
,
1368 VEX_LEN_0FXOP_09_02
,
1369 VEX_LEN_0FXOP_09_12_M_1
,
1370 VEX_LEN_0FXOP_09_82_W_0
,
1371 VEX_LEN_0FXOP_09_83_W_0
,
1372 VEX_LEN_0FXOP_09_90
,
1373 VEX_LEN_0FXOP_09_91
,
1374 VEX_LEN_0FXOP_09_92
,
1375 VEX_LEN_0FXOP_09_93
,
1376 VEX_LEN_0FXOP_09_94
,
1377 VEX_LEN_0FXOP_09_95
,
1378 VEX_LEN_0FXOP_09_96
,
1379 VEX_LEN_0FXOP_09_97
,
1380 VEX_LEN_0FXOP_09_98
,
1381 VEX_LEN_0FXOP_09_99
,
1382 VEX_LEN_0FXOP_09_9A
,
1383 VEX_LEN_0FXOP_09_9B
,
1384 VEX_LEN_0FXOP_09_C1
,
1385 VEX_LEN_0FXOP_09_C2
,
1386 VEX_LEN_0FXOP_09_C3
,
1387 VEX_LEN_0FXOP_09_C6
,
1388 VEX_LEN_0FXOP_09_C7
,
1389 VEX_LEN_0FXOP_09_CB
,
1390 VEX_LEN_0FXOP_09_D1
,
1391 VEX_LEN_0FXOP_09_D2
,
1392 VEX_LEN_0FXOP_09_D3
,
1393 VEX_LEN_0FXOP_09_D6
,
1394 VEX_LEN_0FXOP_09_D7
,
1395 VEX_LEN_0FXOP_09_DB
,
1396 VEX_LEN_0FXOP_09_E1
,
1397 VEX_LEN_0FXOP_09_E2
,
1398 VEX_LEN_0FXOP_09_E3
,
1399 VEX_LEN_0FXOP_0A_12
,
1411 EVEX_LEN_0F3819_W_0
,
1412 EVEX_LEN_0F3819_W_1
,
1413 EVEX_LEN_0F381A_W_0_M_0
,
1414 EVEX_LEN_0F381A_W_1_M_0
,
1415 EVEX_LEN_0F381B_W_0_M_0
,
1416 EVEX_LEN_0F381B_W_1_M_0
,
1418 EVEX_LEN_0F385A_W_0_M_0
,
1419 EVEX_LEN_0F385A_W_1_M_0
,
1420 EVEX_LEN_0F385B_W_0_M_0
,
1421 EVEX_LEN_0F385B_W_1_M_0
,
1422 EVEX_LEN_0F38C6_R_1_M_0
,
1423 EVEX_LEN_0F38C6_R_2_M_0
,
1424 EVEX_LEN_0F38C6_R_5_M_0
,
1425 EVEX_LEN_0F38C6_R_6_M_0
,
1426 EVEX_LEN_0F38C7_R_1_M_0_W_0
,
1427 EVEX_LEN_0F38C7_R_1_M_0_W_1
,
1428 EVEX_LEN_0F38C7_R_2_M_0_W_0
,
1429 EVEX_LEN_0F38C7_R_2_M_0_W_1
,
1430 EVEX_LEN_0F38C7_R_5_M_0_W_0
,
1431 EVEX_LEN_0F38C7_R_5_M_0_W_1
,
1432 EVEX_LEN_0F38C7_R_6_M_0_W_0
,
1433 EVEX_LEN_0F38C7_R_6_M_0_W_1
,
1434 EVEX_LEN_0F3A00_W_1
,
1435 EVEX_LEN_0F3A01_W_1
,
1440 EVEX_LEN_0F3A18_W_0
,
1441 EVEX_LEN_0F3A18_W_1
,
1442 EVEX_LEN_0F3A19_W_0
,
1443 EVEX_LEN_0F3A19_W_1
,
1444 EVEX_LEN_0F3A1A_W_0
,
1445 EVEX_LEN_0F3A1A_W_1
,
1446 EVEX_LEN_0F3A1B_W_0
,
1447 EVEX_LEN_0F3A1B_W_1
,
1449 EVEX_LEN_0F3A21_W_0
,
1451 EVEX_LEN_0F3A23_W_0
,
1452 EVEX_LEN_0F3A23_W_1
,
1453 EVEX_LEN_0F3A38_W_0
,
1454 EVEX_LEN_0F3A38_W_1
,
1455 EVEX_LEN_0F3A39_W_0
,
1456 EVEX_LEN_0F3A39_W_1
,
1457 EVEX_LEN_0F3A3A_W_0
,
1458 EVEX_LEN_0F3A3A_W_1
,
1459 EVEX_LEN_0F3A3B_W_0
,
1460 EVEX_LEN_0F3A3B_W_1
,
1461 EVEX_LEN_0F3A43_W_0
,
1467 VEX_W_0F41_P_0_LEN_1
= 0,
1468 VEX_W_0F41_P_2_LEN_1
,
1469 VEX_W_0F42_P_0_LEN_1
,
1470 VEX_W_0F42_P_2_LEN_1
,
1471 VEX_W_0F44_P_0_LEN_0
,
1472 VEX_W_0F44_P_2_LEN_0
,
1473 VEX_W_0F45_P_0_LEN_1
,
1474 VEX_W_0F45_P_2_LEN_1
,
1475 VEX_W_0F46_P_0_LEN_1
,
1476 VEX_W_0F46_P_2_LEN_1
,
1477 VEX_W_0F47_P_0_LEN_1
,
1478 VEX_W_0F47_P_2_LEN_1
,
1479 VEX_W_0F4A_P_0_LEN_1
,
1480 VEX_W_0F4A_P_2_LEN_1
,
1481 VEX_W_0F4B_P_0_LEN_1
,
1482 VEX_W_0F4B_P_2_LEN_1
,
1483 VEX_W_0F90_P_0_LEN_0
,
1484 VEX_W_0F90_P_2_LEN_0
,
1485 VEX_W_0F91_P_0_LEN_0
,
1486 VEX_W_0F91_P_2_LEN_0
,
1487 VEX_W_0F92_P_0_LEN_0
,
1488 VEX_W_0F92_P_2_LEN_0
,
1489 VEX_W_0F93_P_0_LEN_0
,
1490 VEX_W_0F93_P_2_LEN_0
,
1491 VEX_W_0F98_P_0_LEN_0
,
1492 VEX_W_0F98_P_2_LEN_0
,
1493 VEX_W_0F99_P_0_LEN_0
,
1494 VEX_W_0F99_P_2_LEN_0
,
1503 VEX_W_0F381A_M_0_L_1
,
1510 VEX_W_0F3849_X86_64_P_0
,
1511 VEX_W_0F3849_X86_64_P_2
,
1512 VEX_W_0F3849_X86_64_P_3
,
1513 VEX_W_0F384B_X86_64_P_1
,
1514 VEX_W_0F384B_X86_64_P_2
,
1515 VEX_W_0F384B_X86_64_P_3
,
1518 VEX_W_0F385A_M_0_L_0
,
1519 VEX_W_0F385C_X86_64_P_1
,
1520 VEX_W_0F385E_X86_64_P_0
,
1521 VEX_W_0F385E_X86_64_P_1
,
1522 VEX_W_0F385E_X86_64_P_2
,
1523 VEX_W_0F385E_X86_64_P_3
,
1545 VEX_W_0FXOP_08_85_L_0
,
1546 VEX_W_0FXOP_08_86_L_0
,
1547 VEX_W_0FXOP_08_87_L_0
,
1548 VEX_W_0FXOP_08_8E_L_0
,
1549 VEX_W_0FXOP_08_8F_L_0
,
1550 VEX_W_0FXOP_08_95_L_0
,
1551 VEX_W_0FXOP_08_96_L_0
,
1552 VEX_W_0FXOP_08_97_L_0
,
1553 VEX_W_0FXOP_08_9E_L_0
,
1554 VEX_W_0FXOP_08_9F_L_0
,
1555 VEX_W_0FXOP_08_A6_L_0
,
1556 VEX_W_0FXOP_08_B6_L_0
,
1557 VEX_W_0FXOP_08_C0_L_0
,
1558 VEX_W_0FXOP_08_C1_L_0
,
1559 VEX_W_0FXOP_08_C2_L_0
,
1560 VEX_W_0FXOP_08_C3_L_0
,
1561 VEX_W_0FXOP_08_CC_L_0
,
1562 VEX_W_0FXOP_08_CD_L_0
,
1563 VEX_W_0FXOP_08_CE_L_0
,
1564 VEX_W_0FXOP_08_CF_L_0
,
1565 VEX_W_0FXOP_08_EC_L_0
,
1566 VEX_W_0FXOP_08_ED_L_0
,
1567 VEX_W_0FXOP_08_EE_L_0
,
1568 VEX_W_0FXOP_08_EF_L_0
,
1574 VEX_W_0FXOP_09_C1_L_0
,
1575 VEX_W_0FXOP_09_C2_L_0
,
1576 VEX_W_0FXOP_09_C3_L_0
,
1577 VEX_W_0FXOP_09_C6_L_0
,
1578 VEX_W_0FXOP_09_C7_L_0
,
1579 VEX_W_0FXOP_09_CB_L_0
,
1580 VEX_W_0FXOP_09_D1_L_0
,
1581 VEX_W_0FXOP_09_D2_L_0
,
1582 VEX_W_0FXOP_09_D3_L_0
,
1583 VEX_W_0FXOP_09_D6_L_0
,
1584 VEX_W_0FXOP_09_D7_L_0
,
1585 VEX_W_0FXOP_09_DB_L_0
,
1586 VEX_W_0FXOP_09_E1_L_0
,
1587 VEX_W_0FXOP_09_E2_L_0
,
1588 VEX_W_0FXOP_09_E3_L_0
,
1594 EVEX_W_0F12_P_0_M_1
,
1597 EVEX_W_0F16_P_0_M_1
,
1717 EVEX_W_0F38C7_R_1_M_0
,
1718 EVEX_W_0F38C7_R_2_M_0
,
1719 EVEX_W_0F38C7_R_5_M_0
,
1720 EVEX_W_0F38C7_R_6_M_0
,
1745 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
1754 unsigned int prefix_requirement
;
1757 /* Upper case letters in the instruction names here are macros.
1758 'A' => print 'b' if no register operands or suffix_always is true
1759 'B' => print 'b' if suffix_always is true
1760 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1762 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1763 suffix_always is true
1764 'E' => print 'e' if 32-bit form of jcxz
1765 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1766 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1767 'H' => print ",pt" or ",pn" branch hint
1770 'K' => print 'd' or 'q' if rex prefix is present.
1772 'M' => print 'r' if intel_mnemonic is false.
1773 'N' => print 'n' if instruction has no wait "prefix"
1774 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1775 'P' => behave as 'T' except with register operand outside of suffix_always
1777 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1779 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1780 'S' => print 'w', 'l' or 'q' if suffix_always is true
1781 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1782 prefix or if suffix_always is true.
1785 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1786 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1788 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1789 '!' => change condition from true to false or from false to true.
1790 '%' => add 1 upper case letter to the macro.
1791 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1792 prefix or suffix_always is true (lcall/ljmp).
1793 '@' => in 64bit mode for Intel64 ISA or if instruction
1794 has no operand sizing prefix, print 'q' if suffix_always is true or
1795 nothing otherwise; behave as 'P' in all other cases
1797 2 upper case letter macros:
1798 "XY" => print 'x' or 'y' if suffix_always is true or no register
1799 operands and no broadcast.
1800 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1801 register operands and no broadcast.
1802 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1803 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1804 being false, or no operand at all in 64bit mode, or if suffix_always
1806 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1807 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1808 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1809 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1810 "BW" => print 'b' or 'w' depending on the VEX.W bit
1811 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1812 an operand size prefix, or suffix_always is true. print
1813 'q' if rex prefix is present.
1815 Many of the above letters print nothing in Intel mode. See "putop"
1818 Braces '{' and '}', and vertical bars '|', indicate alternative
1819 mnemonic strings for AT&T and Intel. */
1821 static const struct dis386 dis386
[] = {
1823 { "addB", { Ebh1
, Gb
}, 0 },
1824 { "addS", { Evh1
, Gv
}, 0 },
1825 { "addB", { Gb
, EbS
}, 0 },
1826 { "addS", { Gv
, EvS
}, 0 },
1827 { "addB", { AL
, Ib
}, 0 },
1828 { "addS", { eAX
, Iv
}, 0 },
1829 { X86_64_TABLE (X86_64_06
) },
1830 { X86_64_TABLE (X86_64_07
) },
1832 { "orB", { Ebh1
, Gb
}, 0 },
1833 { "orS", { Evh1
, Gv
}, 0 },
1834 { "orB", { Gb
, EbS
}, 0 },
1835 { "orS", { Gv
, EvS
}, 0 },
1836 { "orB", { AL
, Ib
}, 0 },
1837 { "orS", { eAX
, Iv
}, 0 },
1838 { X86_64_TABLE (X86_64_0E
) },
1839 { Bad_Opcode
}, /* 0x0f extended opcode escape */
1841 { "adcB", { Ebh1
, Gb
}, 0 },
1842 { "adcS", { Evh1
, Gv
}, 0 },
1843 { "adcB", { Gb
, EbS
}, 0 },
1844 { "adcS", { Gv
, EvS
}, 0 },
1845 { "adcB", { AL
, Ib
}, 0 },
1846 { "adcS", { eAX
, Iv
}, 0 },
1847 { X86_64_TABLE (X86_64_16
) },
1848 { X86_64_TABLE (X86_64_17
) },
1850 { "sbbB", { Ebh1
, Gb
}, 0 },
1851 { "sbbS", { Evh1
, Gv
}, 0 },
1852 { "sbbB", { Gb
, EbS
}, 0 },
1853 { "sbbS", { Gv
, EvS
}, 0 },
1854 { "sbbB", { AL
, Ib
}, 0 },
1855 { "sbbS", { eAX
, Iv
}, 0 },
1856 { X86_64_TABLE (X86_64_1E
) },
1857 { X86_64_TABLE (X86_64_1F
) },
1859 { "andB", { Ebh1
, Gb
}, 0 },
1860 { "andS", { Evh1
, Gv
}, 0 },
1861 { "andB", { Gb
, EbS
}, 0 },
1862 { "andS", { Gv
, EvS
}, 0 },
1863 { "andB", { AL
, Ib
}, 0 },
1864 { "andS", { eAX
, Iv
}, 0 },
1865 { Bad_Opcode
}, /* SEG ES prefix */
1866 { X86_64_TABLE (X86_64_27
) },
1868 { "subB", { Ebh1
, Gb
}, 0 },
1869 { "subS", { Evh1
, Gv
}, 0 },
1870 { "subB", { Gb
, EbS
}, 0 },
1871 { "subS", { Gv
, EvS
}, 0 },
1872 { "subB", { AL
, Ib
}, 0 },
1873 { "subS", { eAX
, Iv
}, 0 },
1874 { Bad_Opcode
}, /* SEG CS prefix */
1875 { X86_64_TABLE (X86_64_2F
) },
1877 { "xorB", { Ebh1
, Gb
}, 0 },
1878 { "xorS", { Evh1
, Gv
}, 0 },
1879 { "xorB", { Gb
, EbS
}, 0 },
1880 { "xorS", { Gv
, EvS
}, 0 },
1881 { "xorB", { AL
, Ib
}, 0 },
1882 { "xorS", { eAX
, Iv
}, 0 },
1883 { Bad_Opcode
}, /* SEG SS prefix */
1884 { X86_64_TABLE (X86_64_37
) },
1886 { "cmpB", { Eb
, Gb
}, 0 },
1887 { "cmpS", { Ev
, Gv
}, 0 },
1888 { "cmpB", { Gb
, EbS
}, 0 },
1889 { "cmpS", { Gv
, EvS
}, 0 },
1890 { "cmpB", { AL
, Ib
}, 0 },
1891 { "cmpS", { eAX
, Iv
}, 0 },
1892 { Bad_Opcode
}, /* SEG DS prefix */
1893 { X86_64_TABLE (X86_64_3F
) },
1895 { "inc{S|}", { RMeAX
}, 0 },
1896 { "inc{S|}", { RMeCX
}, 0 },
1897 { "inc{S|}", { RMeDX
}, 0 },
1898 { "inc{S|}", { RMeBX
}, 0 },
1899 { "inc{S|}", { RMeSP
}, 0 },
1900 { "inc{S|}", { RMeBP
}, 0 },
1901 { "inc{S|}", { RMeSI
}, 0 },
1902 { "inc{S|}", { RMeDI
}, 0 },
1904 { "dec{S|}", { RMeAX
}, 0 },
1905 { "dec{S|}", { RMeCX
}, 0 },
1906 { "dec{S|}", { RMeDX
}, 0 },
1907 { "dec{S|}", { RMeBX
}, 0 },
1908 { "dec{S|}", { RMeSP
}, 0 },
1909 { "dec{S|}", { RMeBP
}, 0 },
1910 { "dec{S|}", { RMeSI
}, 0 },
1911 { "dec{S|}", { RMeDI
}, 0 },
1913 { "push{!P|}", { RMrAX
}, 0 },
1914 { "push{!P|}", { RMrCX
}, 0 },
1915 { "push{!P|}", { RMrDX
}, 0 },
1916 { "push{!P|}", { RMrBX
}, 0 },
1917 { "push{!P|}", { RMrSP
}, 0 },
1918 { "push{!P|}", { RMrBP
}, 0 },
1919 { "push{!P|}", { RMrSI
}, 0 },
1920 { "push{!P|}", { RMrDI
}, 0 },
1922 { "pop{!P|}", { RMrAX
}, 0 },
1923 { "pop{!P|}", { RMrCX
}, 0 },
1924 { "pop{!P|}", { RMrDX
}, 0 },
1925 { "pop{!P|}", { RMrBX
}, 0 },
1926 { "pop{!P|}", { RMrSP
}, 0 },
1927 { "pop{!P|}", { RMrBP
}, 0 },
1928 { "pop{!P|}", { RMrSI
}, 0 },
1929 { "pop{!P|}", { RMrDI
}, 0 },
1931 { X86_64_TABLE (X86_64_60
) },
1932 { X86_64_TABLE (X86_64_61
) },
1933 { X86_64_TABLE (X86_64_62
) },
1934 { X86_64_TABLE (X86_64_63
) },
1935 { Bad_Opcode
}, /* seg fs */
1936 { Bad_Opcode
}, /* seg gs */
1937 { Bad_Opcode
}, /* op size prefix */
1938 { Bad_Opcode
}, /* adr size prefix */
1940 { "pushP", { sIv
}, 0 },
1941 { "imulS", { Gv
, Ev
, Iv
}, 0 },
1942 { "pushP", { sIbT
}, 0 },
1943 { "imulS", { Gv
, Ev
, sIb
}, 0 },
1944 { "ins{b|}", { Ybr
, indirDX
}, 0 },
1945 { X86_64_TABLE (X86_64_6D
) },
1946 { "outs{b|}", { indirDXr
, Xb
}, 0 },
1947 { X86_64_TABLE (X86_64_6F
) },
1949 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
1950 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
1951 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
1952 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1953 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1954 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
1955 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1956 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
1958 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
1959 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
1960 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
1961 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
1962 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
1963 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1964 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
1965 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
1967 { REG_TABLE (REG_80
) },
1968 { REG_TABLE (REG_81
) },
1969 { X86_64_TABLE (X86_64_82
) },
1970 { REG_TABLE (REG_83
) },
1971 { "testB", { Eb
, Gb
}, 0 },
1972 { "testS", { Ev
, Gv
}, 0 },
1973 { "xchgB", { Ebh2
, Gb
}, 0 },
1974 { "xchgS", { Evh2
, Gv
}, 0 },
1976 { "movB", { Ebh3
, Gb
}, 0 },
1977 { "movS", { Evh3
, Gv
}, 0 },
1978 { "movB", { Gb
, EbS
}, 0 },
1979 { "movS", { Gv
, EvS
}, 0 },
1980 { "movD", { Sv
, Sw
}, 0 },
1981 { MOD_TABLE (MOD_8D
) },
1982 { "movD", { Sw
, Sv
}, 0 },
1983 { REG_TABLE (REG_8F
) },
1985 { PREFIX_TABLE (PREFIX_90
) },
1986 { "xchgS", { RMeCX
, eAX
}, 0 },
1987 { "xchgS", { RMeDX
, eAX
}, 0 },
1988 { "xchgS", { RMeBX
, eAX
}, 0 },
1989 { "xchgS", { RMeSP
, eAX
}, 0 },
1990 { "xchgS", { RMeBP
, eAX
}, 0 },
1991 { "xchgS", { RMeSI
, eAX
}, 0 },
1992 { "xchgS", { RMeDI
, eAX
}, 0 },
1994 { "cW{t|}R", { XX
}, 0 },
1995 { "cR{t|}O", { XX
}, 0 },
1996 { X86_64_TABLE (X86_64_9A
) },
1997 { Bad_Opcode
}, /* fwait */
1998 { "pushfP", { XX
}, 0 },
1999 { "popfP", { XX
}, 0 },
2000 { "sahf", { XX
}, 0 },
2001 { "lahf", { XX
}, 0 },
2003 { "mov%LB", { AL
, Ob
}, 0 },
2004 { "mov%LS", { eAX
, Ov
}, 0 },
2005 { "mov%LB", { Ob
, AL
}, 0 },
2006 { "mov%LS", { Ov
, eAX
}, 0 },
2007 { "movs{b|}", { Ybr
, Xb
}, 0 },
2008 { "movs{R|}", { Yvr
, Xv
}, 0 },
2009 { "cmps{b|}", { Xb
, Yb
}, 0 },
2010 { "cmps{R|}", { Xv
, Yv
}, 0 },
2012 { "testB", { AL
, Ib
}, 0 },
2013 { "testS", { eAX
, Iv
}, 0 },
2014 { "stosB", { Ybr
, AL
}, 0 },
2015 { "stosS", { Yvr
, eAX
}, 0 },
2016 { "lodsB", { ALr
, Xb
}, 0 },
2017 { "lodsS", { eAXr
, Xv
}, 0 },
2018 { "scasB", { AL
, Yb
}, 0 },
2019 { "scasS", { eAX
, Yv
}, 0 },
2021 { "movB", { RMAL
, Ib
}, 0 },
2022 { "movB", { RMCL
, Ib
}, 0 },
2023 { "movB", { RMDL
, Ib
}, 0 },
2024 { "movB", { RMBL
, Ib
}, 0 },
2025 { "movB", { RMAH
, Ib
}, 0 },
2026 { "movB", { RMCH
, Ib
}, 0 },
2027 { "movB", { RMDH
, Ib
}, 0 },
2028 { "movB", { RMBH
, Ib
}, 0 },
2030 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2031 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2032 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2033 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2034 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2035 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2036 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2037 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2039 { REG_TABLE (REG_C0
) },
2040 { REG_TABLE (REG_C1
) },
2041 { X86_64_TABLE (X86_64_C2
) },
2042 { X86_64_TABLE (X86_64_C3
) },
2043 { X86_64_TABLE (X86_64_C4
) },
2044 { X86_64_TABLE (X86_64_C5
) },
2045 { REG_TABLE (REG_C6
) },
2046 { REG_TABLE (REG_C7
) },
2048 { "enterP", { Iw
, Ib
}, 0 },
2049 { "leaveP", { XX
}, 0 },
2050 { "{l|}ret{|f}%LP", { Iw
}, 0 },
2051 { "{l|}ret{|f}%LP", { XX
}, 0 },
2052 { "int3", { XX
}, 0 },
2053 { "int", { Ib
}, 0 },
2054 { X86_64_TABLE (X86_64_CE
) },
2055 { "iret%LP", { XX
}, 0 },
2057 { REG_TABLE (REG_D0
) },
2058 { REG_TABLE (REG_D1
) },
2059 { REG_TABLE (REG_D2
) },
2060 { REG_TABLE (REG_D3
) },
2061 { X86_64_TABLE (X86_64_D4
) },
2062 { X86_64_TABLE (X86_64_D5
) },
2064 { "xlat", { DSBX
}, 0 },
2075 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2076 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2077 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2078 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2079 { "inB", { AL
, Ib
}, 0 },
2080 { "inG", { zAX
, Ib
}, 0 },
2081 { "outB", { Ib
, AL
}, 0 },
2082 { "outG", { Ib
, zAX
}, 0 },
2084 { X86_64_TABLE (X86_64_E8
) },
2085 { X86_64_TABLE (X86_64_E9
) },
2086 { X86_64_TABLE (X86_64_EA
) },
2087 { "jmp", { Jb
, BND
}, 0 },
2088 { "inB", { AL
, indirDX
}, 0 },
2089 { "inG", { zAX
, indirDX
}, 0 },
2090 { "outB", { indirDX
, AL
}, 0 },
2091 { "outG", { indirDX
, zAX
}, 0 },
2093 { Bad_Opcode
}, /* lock prefix */
2094 { "icebp", { XX
}, 0 },
2095 { Bad_Opcode
}, /* repne */
2096 { Bad_Opcode
}, /* repz */
2097 { "hlt", { XX
}, 0 },
2098 { "cmc", { XX
}, 0 },
2099 { REG_TABLE (REG_F6
) },
2100 { REG_TABLE (REG_F7
) },
2102 { "clc", { XX
}, 0 },
2103 { "stc", { XX
}, 0 },
2104 { "cli", { XX
}, 0 },
2105 { "sti", { XX
}, 0 },
2106 { "cld", { XX
}, 0 },
2107 { "std", { XX
}, 0 },
2108 { REG_TABLE (REG_FE
) },
2109 { REG_TABLE (REG_FF
) },
2112 static const struct dis386 dis386_twobyte
[] = {
2114 { REG_TABLE (REG_0F00
) },
2115 { REG_TABLE (REG_0F01
) },
2116 { "larS", { Gv
, Ew
}, 0 },
2117 { "lslS", { Gv
, Ew
}, 0 },
2119 { "syscall", { XX
}, 0 },
2120 { "clts", { XX
}, 0 },
2121 { "sysret%LQ", { XX
}, 0 },
2123 { "invd", { XX
}, 0 },
2124 { PREFIX_TABLE (PREFIX_0F09
) },
2126 { "ud2", { XX
}, 0 },
2128 { REG_TABLE (REG_0F0D
) },
2129 { "femms", { XX
}, 0 },
2130 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2132 { PREFIX_TABLE (PREFIX_0F10
) },
2133 { PREFIX_TABLE (PREFIX_0F11
) },
2134 { PREFIX_TABLE (PREFIX_0F12
) },
2135 { MOD_TABLE (MOD_0F13
) },
2136 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2137 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2138 { PREFIX_TABLE (PREFIX_0F16
) },
2139 { MOD_TABLE (MOD_0F17
) },
2141 { REG_TABLE (REG_0F18
) },
2142 { "nopQ", { Ev
}, 0 },
2143 { PREFIX_TABLE (PREFIX_0F1A
) },
2144 { PREFIX_TABLE (PREFIX_0F1B
) },
2145 { PREFIX_TABLE (PREFIX_0F1C
) },
2146 { "nopQ", { Ev
}, 0 },
2147 { PREFIX_TABLE (PREFIX_0F1E
) },
2148 { "nopQ", { Ev
}, 0 },
2150 { "movZ", { Em
, Cm
}, 0 },
2151 { "movZ", { Em
, Dm
}, 0 },
2152 { "movZ", { Cm
, Em
}, 0 },
2153 { "movZ", { Dm
, Em
}, 0 },
2154 { X86_64_TABLE (X86_64_0F24
) },
2156 { X86_64_TABLE (X86_64_0F26
) },
2159 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2160 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2161 { PREFIX_TABLE (PREFIX_0F2A
) },
2162 { PREFIX_TABLE (PREFIX_0F2B
) },
2163 { PREFIX_TABLE (PREFIX_0F2C
) },
2164 { PREFIX_TABLE (PREFIX_0F2D
) },
2165 { PREFIX_TABLE (PREFIX_0F2E
) },
2166 { PREFIX_TABLE (PREFIX_0F2F
) },
2168 { "wrmsr", { XX
}, 0 },
2169 { "rdtsc", { XX
}, 0 },
2170 { "rdmsr", { XX
}, 0 },
2171 { "rdpmc", { XX
}, 0 },
2172 { "sysenter", { SEP
}, 0 },
2173 { "sysexit", { SEP
}, 0 },
2175 { "getsec", { XX
}, 0 },
2177 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2179 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2186 { "cmovoS", { Gv
, Ev
}, 0 },
2187 { "cmovnoS", { Gv
, Ev
}, 0 },
2188 { "cmovbS", { Gv
, Ev
}, 0 },
2189 { "cmovaeS", { Gv
, Ev
}, 0 },
2190 { "cmoveS", { Gv
, Ev
}, 0 },
2191 { "cmovneS", { Gv
, Ev
}, 0 },
2192 { "cmovbeS", { Gv
, Ev
}, 0 },
2193 { "cmovaS", { Gv
, Ev
}, 0 },
2195 { "cmovsS", { Gv
, Ev
}, 0 },
2196 { "cmovnsS", { Gv
, Ev
}, 0 },
2197 { "cmovpS", { Gv
, Ev
}, 0 },
2198 { "cmovnpS", { Gv
, Ev
}, 0 },
2199 { "cmovlS", { Gv
, Ev
}, 0 },
2200 { "cmovgeS", { Gv
, Ev
}, 0 },
2201 { "cmovleS", { Gv
, Ev
}, 0 },
2202 { "cmovgS", { Gv
, Ev
}, 0 },
2204 { MOD_TABLE (MOD_0F50
) },
2205 { PREFIX_TABLE (PREFIX_0F51
) },
2206 { PREFIX_TABLE (PREFIX_0F52
) },
2207 { PREFIX_TABLE (PREFIX_0F53
) },
2208 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2209 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2210 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2211 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2213 { PREFIX_TABLE (PREFIX_0F58
) },
2214 { PREFIX_TABLE (PREFIX_0F59
) },
2215 { PREFIX_TABLE (PREFIX_0F5A
) },
2216 { PREFIX_TABLE (PREFIX_0F5B
) },
2217 { PREFIX_TABLE (PREFIX_0F5C
) },
2218 { PREFIX_TABLE (PREFIX_0F5D
) },
2219 { PREFIX_TABLE (PREFIX_0F5E
) },
2220 { PREFIX_TABLE (PREFIX_0F5F
) },
2222 { PREFIX_TABLE (PREFIX_0F60
) },
2223 { PREFIX_TABLE (PREFIX_0F61
) },
2224 { PREFIX_TABLE (PREFIX_0F62
) },
2225 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2226 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2227 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2228 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2229 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2231 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2232 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2233 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2234 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2235 { "punpcklqdq", { XM
, EXx
}, PREFIX_DATA
},
2236 { "punpckhqdq", { XM
, EXx
}, PREFIX_DATA
},
2237 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2238 { PREFIX_TABLE (PREFIX_0F6F
) },
2240 { PREFIX_TABLE (PREFIX_0F70
) },
2241 { REG_TABLE (REG_0F71
) },
2242 { REG_TABLE (REG_0F72
) },
2243 { REG_TABLE (REG_0F73
) },
2244 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2245 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2246 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2247 { "emms", { XX
}, PREFIX_OPCODE
},
2249 { PREFIX_TABLE (PREFIX_0F78
) },
2250 { PREFIX_TABLE (PREFIX_0F79
) },
2253 { PREFIX_TABLE (PREFIX_0F7C
) },
2254 { PREFIX_TABLE (PREFIX_0F7D
) },
2255 { PREFIX_TABLE (PREFIX_0F7E
) },
2256 { PREFIX_TABLE (PREFIX_0F7F
) },
2258 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2259 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2260 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2261 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2262 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2263 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2264 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2265 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2267 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2268 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2269 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2270 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2271 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2272 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2273 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2274 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2276 { "seto", { Eb
}, 0 },
2277 { "setno", { Eb
}, 0 },
2278 { "setb", { Eb
}, 0 },
2279 { "setae", { Eb
}, 0 },
2280 { "sete", { Eb
}, 0 },
2281 { "setne", { Eb
}, 0 },
2282 { "setbe", { Eb
}, 0 },
2283 { "seta", { Eb
}, 0 },
2285 { "sets", { Eb
}, 0 },
2286 { "setns", { Eb
}, 0 },
2287 { "setp", { Eb
}, 0 },
2288 { "setnp", { Eb
}, 0 },
2289 { "setl", { Eb
}, 0 },
2290 { "setge", { Eb
}, 0 },
2291 { "setle", { Eb
}, 0 },
2292 { "setg", { Eb
}, 0 },
2294 { "pushP", { fs
}, 0 },
2295 { "popP", { fs
}, 0 },
2296 { "cpuid", { XX
}, 0 },
2297 { "btS", { Ev
, Gv
}, 0 },
2298 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2299 { "shldS", { Ev
, Gv
, CL
}, 0 },
2300 { REG_TABLE (REG_0FA6
) },
2301 { REG_TABLE (REG_0FA7
) },
2303 { "pushP", { gs
}, 0 },
2304 { "popP", { gs
}, 0 },
2305 { "rsm", { XX
}, 0 },
2306 { "btsS", { Evh1
, Gv
}, 0 },
2307 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2308 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2309 { REG_TABLE (REG_0FAE
) },
2310 { "imulS", { Gv
, Ev
}, 0 },
2312 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2313 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2314 { MOD_TABLE (MOD_0FB2
) },
2315 { "btrS", { Evh1
, Gv
}, 0 },
2316 { MOD_TABLE (MOD_0FB4
) },
2317 { MOD_TABLE (MOD_0FB5
) },
2318 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2319 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2321 { PREFIX_TABLE (PREFIX_0FB8
) },
2322 { "ud1S", { Gv
, Ev
}, 0 },
2323 { REG_TABLE (REG_0FBA
) },
2324 { "btcS", { Evh1
, Gv
}, 0 },
2325 { PREFIX_TABLE (PREFIX_0FBC
) },
2326 { PREFIX_TABLE (PREFIX_0FBD
) },
2327 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2328 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2330 { "xaddB", { Ebh1
, Gb
}, 0 },
2331 { "xaddS", { Evh1
, Gv
}, 0 },
2332 { PREFIX_TABLE (PREFIX_0FC2
) },
2333 { MOD_TABLE (MOD_0FC3
) },
2334 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2335 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2336 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2337 { REG_TABLE (REG_0FC7
) },
2339 { "bswap", { RMeAX
}, 0 },
2340 { "bswap", { RMeCX
}, 0 },
2341 { "bswap", { RMeDX
}, 0 },
2342 { "bswap", { RMeBX
}, 0 },
2343 { "bswap", { RMeSP
}, 0 },
2344 { "bswap", { RMeBP
}, 0 },
2345 { "bswap", { RMeSI
}, 0 },
2346 { "bswap", { RMeDI
}, 0 },
2348 { PREFIX_TABLE (PREFIX_0FD0
) },
2349 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2350 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2351 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2352 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2353 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2354 { PREFIX_TABLE (PREFIX_0FD6
) },
2355 { MOD_TABLE (MOD_0FD7
) },
2357 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2358 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2359 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2360 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2361 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2362 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2363 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2364 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2366 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2367 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2368 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2369 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2370 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2371 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2372 { PREFIX_TABLE (PREFIX_0FE6
) },
2373 { PREFIX_TABLE (PREFIX_0FE7
) },
2375 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2376 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2377 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2378 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2379 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2380 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2381 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2382 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2384 { PREFIX_TABLE (PREFIX_0FF0
) },
2385 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2386 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2387 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2388 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2389 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2390 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2391 { PREFIX_TABLE (PREFIX_0FF7
) },
2393 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2394 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2395 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2396 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2397 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2398 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2399 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2400 { "ud0S", { Gv
, Ev
}, 0 },
2403 static const unsigned char onebyte_has_modrm
[256] = {
2404 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2405 /* ------------------------------- */
2406 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2407 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2408 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2409 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2410 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2411 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2412 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2413 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2414 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2415 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2416 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2417 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2418 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2419 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2420 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2421 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2422 /* ------------------------------- */
2423 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2426 static const unsigned char twobyte_has_modrm
[256] = {
2427 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2428 /* ------------------------------- */
2429 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2430 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2431 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2432 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2433 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2434 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2435 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2436 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2437 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2438 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2439 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2440 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2441 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2442 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2443 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2444 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2445 /* ------------------------------- */
2446 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2449 static char obuf
[100];
2451 static char *mnemonicendp
;
2452 static char scratchbuf
[100];
2453 static unsigned char *start_codep
;
2454 static unsigned char *insn_codep
;
2455 static unsigned char *codep
;
2456 static unsigned char *end_codep
;
2457 static int last_lock_prefix
;
2458 static int last_repz_prefix
;
2459 static int last_repnz_prefix
;
2460 static int last_data_prefix
;
2461 static int last_addr_prefix
;
2462 static int last_rex_prefix
;
2463 static int last_seg_prefix
;
2464 static int fwait_prefix
;
2465 /* The active segment register prefix. */
2466 static int active_seg_prefix
;
2467 #define MAX_CODE_LENGTH 15
2468 /* We can up to 14 prefixes since the maximum instruction length is
2470 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2471 static disassemble_info
*the_info
;
2479 static unsigned char need_modrm
;
2489 int register_specifier
;
2496 int mask_register_specifier
;
2502 static unsigned char need_vex
;
2510 /* If we are accessing mod/rm/reg without need_modrm set, then the
2511 values are stale. Hitting this abort likely indicates that you
2512 need to update onebyte_has_modrm or twobyte_has_modrm. */
2513 #define MODRM_CHECK if (!need_modrm) abort ()
2515 static const char **names64
;
2516 static const char **names32
;
2517 static const char **names16
;
2518 static const char **names8
;
2519 static const char **names8rex
;
2520 static const char **names_seg
;
2521 static const char *index64
;
2522 static const char *index32
;
2523 static const char **index16
;
2524 static const char **names_bnd
;
2526 static const char *intel_names64
[] = {
2527 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2528 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2530 static const char *intel_names32
[] = {
2531 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2532 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2534 static const char *intel_names16
[] = {
2535 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2536 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2538 static const char *intel_names8
[] = {
2539 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2541 static const char *intel_names8rex
[] = {
2542 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2543 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2545 static const char *intel_names_seg
[] = {
2546 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2548 static const char *intel_index64
= "riz";
2549 static const char *intel_index32
= "eiz";
2550 static const char *intel_index16
[] = {
2551 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2554 static const char *att_names64
[] = {
2555 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2556 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2558 static const char *att_names32
[] = {
2559 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2560 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2562 static const char *att_names16
[] = {
2563 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2564 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2566 static const char *att_names8
[] = {
2567 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2569 static const char *att_names8rex
[] = {
2570 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2571 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2573 static const char *att_names_seg
[] = {
2574 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2576 static const char *att_index64
= "%riz";
2577 static const char *att_index32
= "%eiz";
2578 static const char *att_index16
[] = {
2579 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2582 static const char **names_mm
;
2583 static const char *intel_names_mm
[] = {
2584 "mm0", "mm1", "mm2", "mm3",
2585 "mm4", "mm5", "mm6", "mm7"
2587 static const char *att_names_mm
[] = {
2588 "%mm0", "%mm1", "%mm2", "%mm3",
2589 "%mm4", "%mm5", "%mm6", "%mm7"
2592 static const char *intel_names_bnd
[] = {
2593 "bnd0", "bnd1", "bnd2", "bnd3"
2596 static const char *att_names_bnd
[] = {
2597 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2600 static const char **names_xmm
;
2601 static const char *intel_names_xmm
[] = {
2602 "xmm0", "xmm1", "xmm2", "xmm3",
2603 "xmm4", "xmm5", "xmm6", "xmm7",
2604 "xmm8", "xmm9", "xmm10", "xmm11",
2605 "xmm12", "xmm13", "xmm14", "xmm15",
2606 "xmm16", "xmm17", "xmm18", "xmm19",
2607 "xmm20", "xmm21", "xmm22", "xmm23",
2608 "xmm24", "xmm25", "xmm26", "xmm27",
2609 "xmm28", "xmm29", "xmm30", "xmm31"
2611 static const char *att_names_xmm
[] = {
2612 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2613 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2614 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2615 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2616 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2617 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2618 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2619 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2622 static const char **names_ymm
;
2623 static const char *intel_names_ymm
[] = {
2624 "ymm0", "ymm1", "ymm2", "ymm3",
2625 "ymm4", "ymm5", "ymm6", "ymm7",
2626 "ymm8", "ymm9", "ymm10", "ymm11",
2627 "ymm12", "ymm13", "ymm14", "ymm15",
2628 "ymm16", "ymm17", "ymm18", "ymm19",
2629 "ymm20", "ymm21", "ymm22", "ymm23",
2630 "ymm24", "ymm25", "ymm26", "ymm27",
2631 "ymm28", "ymm29", "ymm30", "ymm31"
2633 static const char *att_names_ymm
[] = {
2634 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2635 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2636 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2637 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2638 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2639 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2640 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2641 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2644 static const char **names_zmm
;
2645 static const char *intel_names_zmm
[] = {
2646 "zmm0", "zmm1", "zmm2", "zmm3",
2647 "zmm4", "zmm5", "zmm6", "zmm7",
2648 "zmm8", "zmm9", "zmm10", "zmm11",
2649 "zmm12", "zmm13", "zmm14", "zmm15",
2650 "zmm16", "zmm17", "zmm18", "zmm19",
2651 "zmm20", "zmm21", "zmm22", "zmm23",
2652 "zmm24", "zmm25", "zmm26", "zmm27",
2653 "zmm28", "zmm29", "zmm30", "zmm31"
2655 static const char *att_names_zmm
[] = {
2656 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2657 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2658 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2659 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2660 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2661 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2662 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2663 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2666 static const char **names_tmm
;
2667 static const char *intel_names_tmm
[] = {
2668 "tmm0", "tmm1", "tmm2", "tmm3",
2669 "tmm4", "tmm5", "tmm6", "tmm7"
2671 static const char *att_names_tmm
[] = {
2672 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2673 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2676 static const char **names_mask
;
2677 static const char *intel_names_mask
[] = {
2678 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2680 static const char *att_names_mask
[] = {
2681 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2684 static const char *names_rounding
[] =
2692 static const struct dis386 reg_table
[][8] = {
2695 { "addA", { Ebh1
, Ib
}, 0 },
2696 { "orA", { Ebh1
, Ib
}, 0 },
2697 { "adcA", { Ebh1
, Ib
}, 0 },
2698 { "sbbA", { Ebh1
, Ib
}, 0 },
2699 { "andA", { Ebh1
, Ib
}, 0 },
2700 { "subA", { Ebh1
, Ib
}, 0 },
2701 { "xorA", { Ebh1
, Ib
}, 0 },
2702 { "cmpA", { Eb
, Ib
}, 0 },
2706 { "addQ", { Evh1
, Iv
}, 0 },
2707 { "orQ", { Evh1
, Iv
}, 0 },
2708 { "adcQ", { Evh1
, Iv
}, 0 },
2709 { "sbbQ", { Evh1
, Iv
}, 0 },
2710 { "andQ", { Evh1
, Iv
}, 0 },
2711 { "subQ", { Evh1
, Iv
}, 0 },
2712 { "xorQ", { Evh1
, Iv
}, 0 },
2713 { "cmpQ", { Ev
, Iv
}, 0 },
2717 { "addQ", { Evh1
, sIb
}, 0 },
2718 { "orQ", { Evh1
, sIb
}, 0 },
2719 { "adcQ", { Evh1
, sIb
}, 0 },
2720 { "sbbQ", { Evh1
, sIb
}, 0 },
2721 { "andQ", { Evh1
, sIb
}, 0 },
2722 { "subQ", { Evh1
, sIb
}, 0 },
2723 { "xorQ", { Evh1
, sIb
}, 0 },
2724 { "cmpQ", { Ev
, sIb
}, 0 },
2728 { "pop{P|}", { stackEv
}, 0 },
2729 { XOP_8F_TABLE (XOP_09
) },
2733 { XOP_8F_TABLE (XOP_09
) },
2737 { "rolA", { Eb
, Ib
}, 0 },
2738 { "rorA", { Eb
, Ib
}, 0 },
2739 { "rclA", { Eb
, Ib
}, 0 },
2740 { "rcrA", { Eb
, Ib
}, 0 },
2741 { "shlA", { Eb
, Ib
}, 0 },
2742 { "shrA", { Eb
, Ib
}, 0 },
2743 { "shlA", { Eb
, Ib
}, 0 },
2744 { "sarA", { Eb
, Ib
}, 0 },
2748 { "rolQ", { Ev
, Ib
}, 0 },
2749 { "rorQ", { Ev
, Ib
}, 0 },
2750 { "rclQ", { Ev
, Ib
}, 0 },
2751 { "rcrQ", { Ev
, Ib
}, 0 },
2752 { "shlQ", { Ev
, Ib
}, 0 },
2753 { "shrQ", { Ev
, Ib
}, 0 },
2754 { "shlQ", { Ev
, Ib
}, 0 },
2755 { "sarQ", { Ev
, Ib
}, 0 },
2759 { "movA", { Ebh3
, Ib
}, 0 },
2766 { MOD_TABLE (MOD_C6_REG_7
) },
2770 { "movQ", { Evh3
, Iv
}, 0 },
2777 { MOD_TABLE (MOD_C7_REG_7
) },
2781 { "rolA", { Eb
, I1
}, 0 },
2782 { "rorA", { Eb
, I1
}, 0 },
2783 { "rclA", { Eb
, I1
}, 0 },
2784 { "rcrA", { Eb
, I1
}, 0 },
2785 { "shlA", { Eb
, I1
}, 0 },
2786 { "shrA", { Eb
, I1
}, 0 },
2787 { "shlA", { Eb
, I1
}, 0 },
2788 { "sarA", { Eb
, I1
}, 0 },
2792 { "rolQ", { Ev
, I1
}, 0 },
2793 { "rorQ", { Ev
, I1
}, 0 },
2794 { "rclQ", { Ev
, I1
}, 0 },
2795 { "rcrQ", { Ev
, I1
}, 0 },
2796 { "shlQ", { Ev
, I1
}, 0 },
2797 { "shrQ", { Ev
, I1
}, 0 },
2798 { "shlQ", { Ev
, I1
}, 0 },
2799 { "sarQ", { Ev
, I1
}, 0 },
2803 { "rolA", { Eb
, CL
}, 0 },
2804 { "rorA", { Eb
, CL
}, 0 },
2805 { "rclA", { Eb
, CL
}, 0 },
2806 { "rcrA", { Eb
, CL
}, 0 },
2807 { "shlA", { Eb
, CL
}, 0 },
2808 { "shrA", { Eb
, CL
}, 0 },
2809 { "shlA", { Eb
, CL
}, 0 },
2810 { "sarA", { Eb
, CL
}, 0 },
2814 { "rolQ", { Ev
, CL
}, 0 },
2815 { "rorQ", { Ev
, CL
}, 0 },
2816 { "rclQ", { Ev
, CL
}, 0 },
2817 { "rcrQ", { Ev
, CL
}, 0 },
2818 { "shlQ", { Ev
, CL
}, 0 },
2819 { "shrQ", { Ev
, CL
}, 0 },
2820 { "shlQ", { Ev
, CL
}, 0 },
2821 { "sarQ", { Ev
, CL
}, 0 },
2825 { "testA", { Eb
, Ib
}, 0 },
2826 { "testA", { Eb
, Ib
}, 0 },
2827 { "notA", { Ebh1
}, 0 },
2828 { "negA", { Ebh1
}, 0 },
2829 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
2830 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
2831 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
2832 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
2836 { "testQ", { Ev
, Iv
}, 0 },
2837 { "testQ", { Ev
, Iv
}, 0 },
2838 { "notQ", { Evh1
}, 0 },
2839 { "negQ", { Evh1
}, 0 },
2840 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
2841 { "imulQ", { Ev
}, 0 },
2842 { "divQ", { Ev
}, 0 },
2843 { "idivQ", { Ev
}, 0 },
2847 { "incA", { Ebh1
}, 0 },
2848 { "decA", { Ebh1
}, 0 },
2852 { "incQ", { Evh1
}, 0 },
2853 { "decQ", { Evh1
}, 0 },
2854 { "call{@|}", { NOTRACK
, indirEv
, BND
}, 0 },
2855 { MOD_TABLE (MOD_FF_REG_3
) },
2856 { "jmp{@|}", { NOTRACK
, indirEv
, BND
}, 0 },
2857 { MOD_TABLE (MOD_FF_REG_5
) },
2858 { "push{P|}", { stackEv
}, 0 },
2863 { "sldtD", { Sv
}, 0 },
2864 { "strD", { Sv
}, 0 },
2865 { "lldt", { Ew
}, 0 },
2866 { "ltr", { Ew
}, 0 },
2867 { "verr", { Ew
}, 0 },
2868 { "verw", { Ew
}, 0 },
2874 { MOD_TABLE (MOD_0F01_REG_0
) },
2875 { MOD_TABLE (MOD_0F01_REG_1
) },
2876 { MOD_TABLE (MOD_0F01_REG_2
) },
2877 { MOD_TABLE (MOD_0F01_REG_3
) },
2878 { "smswD", { Sv
}, 0 },
2879 { MOD_TABLE (MOD_0F01_REG_5
) },
2880 { "lmsw", { Ew
}, 0 },
2881 { MOD_TABLE (MOD_0F01_REG_7
) },
2885 { "prefetch", { Mb
}, 0 },
2886 { "prefetchw", { Mb
}, 0 },
2887 { "prefetchwt1", { Mb
}, 0 },
2888 { "prefetch", { Mb
}, 0 },
2889 { "prefetch", { Mb
}, 0 },
2890 { "prefetch", { Mb
}, 0 },
2891 { "prefetch", { Mb
}, 0 },
2892 { "prefetch", { Mb
}, 0 },
2896 { MOD_TABLE (MOD_0F18_REG_0
) },
2897 { MOD_TABLE (MOD_0F18_REG_1
) },
2898 { MOD_TABLE (MOD_0F18_REG_2
) },
2899 { MOD_TABLE (MOD_0F18_REG_3
) },
2900 { MOD_TABLE (MOD_0F18_REG_4
) },
2901 { MOD_TABLE (MOD_0F18_REG_5
) },
2902 { MOD_TABLE (MOD_0F18_REG_6
) },
2903 { MOD_TABLE (MOD_0F18_REG_7
) },
2905 /* REG_0F1C_P_0_MOD_0 */
2907 { "cldemote", { Mb
}, 0 },
2908 { "nopQ", { Ev
}, 0 },
2909 { "nopQ", { Ev
}, 0 },
2910 { "nopQ", { Ev
}, 0 },
2911 { "nopQ", { Ev
}, 0 },
2912 { "nopQ", { Ev
}, 0 },
2913 { "nopQ", { Ev
}, 0 },
2914 { "nopQ", { Ev
}, 0 },
2916 /* REG_0F1E_P_1_MOD_3 */
2918 { "nopQ", { Ev
}, 0 },
2919 { "rdsspK", { Edq
}, PREFIX_OPCODE
},
2920 { "nopQ", { Ev
}, 0 },
2921 { "nopQ", { Ev
}, 0 },
2922 { "nopQ", { Ev
}, 0 },
2923 { "nopQ", { Ev
}, 0 },
2924 { "nopQ", { Ev
}, 0 },
2925 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
2927 /* REG_0F38D8_PREFIX_1 */
2929 { "aesencwide128kl", { M
}, 0 },
2930 { "aesdecwide128kl", { M
}, 0 },
2931 { "aesencwide256kl", { M
}, 0 },
2932 { "aesdecwide256kl", { M
}, 0 },
2934 /* REG_0F3A0F_PREFIX_1_MOD_3 */
2936 { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0
) },
2942 { MOD_TABLE (MOD_0F71_REG_2
) },
2944 { MOD_TABLE (MOD_0F71_REG_4
) },
2946 { MOD_TABLE (MOD_0F71_REG_6
) },
2952 { MOD_TABLE (MOD_0F72_REG_2
) },
2954 { MOD_TABLE (MOD_0F72_REG_4
) },
2956 { MOD_TABLE (MOD_0F72_REG_6
) },
2962 { MOD_TABLE (MOD_0F73_REG_2
) },
2963 { MOD_TABLE (MOD_0F73_REG_3
) },
2966 { MOD_TABLE (MOD_0F73_REG_6
) },
2967 { MOD_TABLE (MOD_0F73_REG_7
) },
2971 { "montmul", { { OP_0f07
, 0 } }, 0 },
2972 { "xsha1", { { OP_0f07
, 0 } }, 0 },
2973 { "xsha256", { { OP_0f07
, 0 } }, 0 },
2977 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
2978 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
2979 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
2980 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
2981 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
2982 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
2986 { MOD_TABLE (MOD_0FAE_REG_0
) },
2987 { MOD_TABLE (MOD_0FAE_REG_1
) },
2988 { MOD_TABLE (MOD_0FAE_REG_2
) },
2989 { MOD_TABLE (MOD_0FAE_REG_3
) },
2990 { MOD_TABLE (MOD_0FAE_REG_4
) },
2991 { MOD_TABLE (MOD_0FAE_REG_5
) },
2992 { MOD_TABLE (MOD_0FAE_REG_6
) },
2993 { MOD_TABLE (MOD_0FAE_REG_7
) },
3001 { "btQ", { Ev
, Ib
}, 0 },
3002 { "btsQ", { Evh1
, Ib
}, 0 },
3003 { "btrQ", { Evh1
, Ib
}, 0 },
3004 { "btcQ", { Evh1
, Ib
}, 0 },
3009 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3011 { MOD_TABLE (MOD_0FC7_REG_3
) },
3012 { MOD_TABLE (MOD_0FC7_REG_4
) },
3013 { MOD_TABLE (MOD_0FC7_REG_5
) },
3014 { MOD_TABLE (MOD_0FC7_REG_6
) },
3015 { MOD_TABLE (MOD_0FC7_REG_7
) },
3021 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3023 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3025 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3031 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3033 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3035 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3041 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3042 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3045 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3046 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3052 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3053 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3055 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3057 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
) },
3059 /* REG_VEX_0F38F3 */
3062 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1
) },
3063 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2
) },
3064 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3
) },
3066 /* REG_0FXOP_09_01_L_0 */
3069 { "blcfill", { VexGdq
, Edq
}, 0 },
3070 { "blsfill", { VexGdq
, Edq
}, 0 },
3071 { "blcs", { VexGdq
, Edq
}, 0 },
3072 { "tzmsk", { VexGdq
, Edq
}, 0 },
3073 { "blcic", { VexGdq
, Edq
}, 0 },
3074 { "blsic", { VexGdq
, Edq
}, 0 },
3075 { "t1mskc", { VexGdq
, Edq
}, 0 },
3077 /* REG_0FXOP_09_02_L_0 */
3080 { "blcmsk", { VexGdq
, Edq
}, 0 },
3085 { "blci", { VexGdq
, Edq
}, 0 },
3087 /* REG_0FXOP_09_12_M_1_L_0 */
3089 { "llwpcb", { Edq
}, 0 },
3090 { "slwpcb", { Edq
}, 0 },
3092 /* REG_0FXOP_0A_12_L_0 */
3094 { "lwpins", { VexGdq
, Ed
, Id
}, 0 },
3095 { "lwpval", { VexGdq
, Ed
, Id
}, 0 },
3098 #include "i386-dis-evex-reg.h"
3101 static const struct dis386 prefix_table
[][4] = {
3104 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3105 { "pause", { XX
}, 0 },
3106 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3107 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3110 /* PREFIX_0F01_REG_1_RM_4 */
3114 { "tdcall", { Skip_MODRM
}, 0 },
3118 /* PREFIX_0F01_REG_1_RM_5 */
3122 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2
) },
3126 /* PREFIX_0F01_REG_1_RM_6 */
3130 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2
) },
3134 /* PREFIX_0F01_REG_1_RM_7 */
3136 { "encls", { Skip_MODRM
}, 0 },
3138 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2
) },
3142 /* PREFIX_0F01_REG_3_RM_1 */
3144 { "vmmcall", { Skip_MODRM
}, 0 },
3145 { "vmgexit", { Skip_MODRM
}, 0 },
3147 { "vmgexit", { Skip_MODRM
}, 0 },
3150 /* PREFIX_0F01_REG_5_MOD_0 */
3153 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3156 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3158 { "serialize", { Skip_MODRM
}, PREFIX_OPCODE
},
3159 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3161 { "xsusldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3164 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3169 { "xresldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3172 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3175 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3178 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3181 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1
) },
3184 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3187 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1
) },
3190 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3192 { "rdpkru", { Skip_MODRM
}, 0 },
3193 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1
) },
3196 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3198 { "wrpkru", { Skip_MODRM
}, 0 },
3199 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1
) },
3202 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3204 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3205 { "mcommit", { Skip_MODRM
}, 0 },
3210 { "wbinvd", { XX
}, 0 },
3211 { "wbnoinvd", { XX
}, 0 },
3216 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3217 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3218 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3219 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3224 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3225 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3226 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3227 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3232 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3233 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3234 { MOD_TABLE (MOD_0F12_PREFIX_2
) },
3235 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3240 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3241 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3242 { MOD_TABLE (MOD_0F16_PREFIX_2
) },
3247 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3248 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3249 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3250 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3255 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3256 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3257 { "bndmov", { EbndS
, Gbnd
}, 0 },
3258 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3263 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3264 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3265 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3266 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3271 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3272 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3273 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3274 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3279 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3280 { "cvtsi2ss{%LQ|}", { XM
, Edq
}, PREFIX_OPCODE
},
3281 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3282 { "cvtsi2sd{%LQ|}", { XM
, Edq
}, 0 },
3287 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3288 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3289 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3290 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3295 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3296 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3297 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3298 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3303 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3304 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3305 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3306 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3311 { "ucomiss",{ XM
, EXd
}, 0 },
3313 { "ucomisd",{ XM
, EXq
}, 0 },
3318 { "comiss", { XM
, EXd
}, 0 },
3320 { "comisd", { XM
, EXq
}, 0 },
3325 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3326 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3327 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3328 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3333 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3334 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3339 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3340 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3345 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3346 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3347 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3348 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3353 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3354 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3355 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3356 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3361 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3362 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3363 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3364 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3369 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3370 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3371 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3376 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3377 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3378 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3379 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3384 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3385 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3386 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3387 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3392 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3393 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3394 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3395 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3400 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3401 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3402 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3403 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3408 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3410 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3415 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3417 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3422 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3424 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3429 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3430 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3431 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3436 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3437 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3438 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3439 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3444 {"vmread", { Em
, Gm
}, 0 },
3446 {"extrq", { XS
, Ib
, Ib
}, 0 },
3447 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3452 {"vmwrite", { Gm
, Em
}, 0 },
3454 {"extrq", { XM
, XS
}, 0 },
3455 {"insertq", { XM
, XS
}, 0 },
3462 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3463 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3470 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3471 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3476 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3477 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3478 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3483 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3484 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3485 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3488 /* PREFIX_0FAE_REG_0_MOD_3 */
3491 { "rdfsbase", { Ev
}, 0 },
3494 /* PREFIX_0FAE_REG_1_MOD_3 */
3497 { "rdgsbase", { Ev
}, 0 },
3500 /* PREFIX_0FAE_REG_2_MOD_3 */
3503 { "wrfsbase", { Ev
}, 0 },
3506 /* PREFIX_0FAE_REG_3_MOD_3 */
3509 { "wrgsbase", { Ev
}, 0 },
3512 /* PREFIX_0FAE_REG_4_MOD_0 */
3514 { "xsave", { FXSAVE
}, 0 },
3515 { "ptwrite{%LQ|}", { Edq
}, 0 },
3518 /* PREFIX_0FAE_REG_4_MOD_3 */
3521 { "ptwrite{%LQ|}", { Edq
}, 0 },
3524 /* PREFIX_0FAE_REG_5_MOD_3 */
3526 { "lfence", { Skip_MODRM
}, 0 },
3527 { "incsspK", { Edq
}, PREFIX_OPCODE
},
3530 /* PREFIX_0FAE_REG_6_MOD_0 */
3532 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3533 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3534 { "clwb", { Mb
}, PREFIX_OPCODE
},
3537 /* PREFIX_0FAE_REG_6_MOD_3 */
3539 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
3540 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3541 { "tpause", { Edq
}, PREFIX_OPCODE
},
3542 { "umwait", { Edq
}, PREFIX_OPCODE
},
3545 /* PREFIX_0FAE_REG_7_MOD_0 */
3547 { "clflush", { Mb
}, 0 },
3549 { "clflushopt", { Mb
}, 0 },
3555 { "popcntS", { Gv
, Ev
}, 0 },
3560 { "bsfS", { Gv
, Ev
}, 0 },
3561 { "tzcntS", { Gv
, Ev
}, 0 },
3562 { "bsfS", { Gv
, Ev
}, 0 },
3567 { "bsrS", { Gv
, Ev
}, 0 },
3568 { "lzcntS", { Gv
, Ev
}, 0 },
3569 { "bsrS", { Gv
, Ev
}, 0 },
3574 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3575 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
3576 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3577 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
3580 /* PREFIX_0FC7_REG_6_MOD_0 */
3582 { "vmptrld",{ Mq
}, 0 },
3583 { "vmxon", { Mq
}, 0 },
3584 { "vmclear",{ Mq
}, 0 },
3587 /* PREFIX_0FC7_REG_6_MOD_3 */
3589 { "rdrand", { Ev
}, 0 },
3590 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1
) },
3591 { "rdrand", { Ev
}, 0 }
3594 /* PREFIX_0FC7_REG_7_MOD_3 */
3596 { "rdseed", { Ev
}, 0 },
3597 { "rdpid", { Em
}, 0 },
3598 { "rdseed", { Ev
}, 0 },
3605 { "addsubpd", { XM
, EXx
}, 0 },
3606 { "addsubps", { XM
, EXx
}, 0 },
3612 { "movq2dq",{ XM
, MS
}, 0 },
3613 { "movq", { EXqS
, XM
}, 0 },
3614 { "movdq2q",{ MX
, XS
}, 0 },
3620 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3621 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3622 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3627 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
3629 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3637 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3642 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
3644 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
3650 { REG_TABLE (REG_0F38D8_PREFIX_1
) },
3656 { MOD_TABLE (MOD_0F38DC_PREFIX_1
) },
3657 { "aesenc", { XM
, EXx
}, 0 },
3663 { MOD_TABLE (MOD_0F38DD_PREFIX_1
) },
3664 { "aesenclast", { XM
, EXx
}, 0 },
3670 { MOD_TABLE (MOD_0F38DE_PREFIX_1
) },
3671 { "aesdec", { XM
, EXx
}, 0 },
3677 { MOD_TABLE (MOD_0F38DF_PREFIX_1
) },
3678 { "aesdeclast", { XM
, EXx
}, 0 },
3683 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
3685 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
3686 { "crc32A", { Gdq
, Eb
}, PREFIX_OPCODE
},
3691 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
3693 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
3694 { "crc32Q", { Gdq
, Ev
}, PREFIX_OPCODE
},
3699 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
3700 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
3701 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
3708 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
3709 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
3710 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
3715 { MOD_TABLE (MOD_0F38FA_PREFIX_1
) },
3721 { MOD_TABLE (MOD_0F38FB_PREFIX_1
) },
3727 { MOD_TABLE (MOD_0F3A0F_PREFIX_1
)},
3730 /* PREFIX_VEX_0F10 */
3732 { "vmovups", { XM
, EXx
}, 0 },
3733 { "vmovss", { XMScalar
, VexScalarR
, EXxmm_md
}, 0 },
3734 { "vmovupd", { XM
, EXx
}, 0 },
3735 { "vmovsd", { XMScalar
, VexScalarR
, EXxmm_mq
}, 0 },
3738 /* PREFIX_VEX_0F11 */
3740 { "vmovups", { EXxS
, XM
}, 0 },
3741 { "vmovss", { EXdS
, VexScalarR
, XMScalar
}, 0 },
3742 { "vmovupd", { EXxS
, XM
}, 0 },
3743 { "vmovsd", { EXqS
, VexScalarR
, XMScalar
}, 0 },
3746 /* PREFIX_VEX_0F12 */
3748 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
3749 { "vmovsldup", { XM
, EXx
}, 0 },
3750 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2
) },
3751 { "vmovddup", { XM
, EXymmq
}, 0 },
3754 /* PREFIX_VEX_0F16 */
3756 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
3757 { "vmovshdup", { XM
, EXx
}, 0 },
3758 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2
) },
3761 /* PREFIX_VEX_0F2A */
3764 { "vcvtsi2ss{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
3766 { "vcvtsi2sd{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
3769 /* PREFIX_VEX_0F2C */
3772 { "vcvttss2si", { Gdq
, EXxmm_md
, EXxEVexS
}, 0 },
3774 { "vcvttsd2si", { Gdq
, EXxmm_mq
, EXxEVexS
}, 0 },
3777 /* PREFIX_VEX_0F2D */
3780 { "vcvtss2si", { Gdq
, EXxmm_md
, EXxEVexR
}, 0 },
3782 { "vcvtsd2si", { Gdq
, EXxmm_mq
, EXxEVexR
}, 0 },
3785 /* PREFIX_VEX_0F2E */
3787 { "vucomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
3789 { "vucomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
3792 /* PREFIX_VEX_0F2F */
3794 { "vcomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
3796 { "vcomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
3799 /* PREFIX_VEX_0F41 */
3801 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
3803 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
3806 /* PREFIX_VEX_0F42 */
3808 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
3810 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
3813 /* PREFIX_VEX_0F44 */
3815 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
3817 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
3820 /* PREFIX_VEX_0F45 */
3822 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
3824 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
3827 /* PREFIX_VEX_0F46 */
3829 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
3831 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
3834 /* PREFIX_VEX_0F47 */
3836 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
3838 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
3841 /* PREFIX_VEX_0F4A */
3843 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
3845 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
3848 /* PREFIX_VEX_0F4B */
3850 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
3852 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
3855 /* PREFIX_VEX_0F51 */
3857 { "vsqrtps", { XM
, EXx
}, 0 },
3858 { "vsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3859 { "vsqrtpd", { XM
, EXx
}, 0 },
3860 { "vsqrtsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3863 /* PREFIX_VEX_0F52 */
3865 { "vrsqrtps", { XM
, EXx
}, 0 },
3866 { "vrsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3869 /* PREFIX_VEX_0F53 */
3871 { "vrcpps", { XM
, EXx
}, 0 },
3872 { "vrcpss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3875 /* PREFIX_VEX_0F58 */
3877 { "vaddps", { XM
, Vex
, EXx
}, 0 },
3878 { "vaddss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3879 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
3880 { "vaddsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3883 /* PREFIX_VEX_0F59 */
3885 { "vmulps", { XM
, Vex
, EXx
}, 0 },
3886 { "vmulss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3887 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
3888 { "vmulsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3891 /* PREFIX_VEX_0F5A */
3893 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
3894 { "vcvtss2sd", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3895 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
3896 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3899 /* PREFIX_VEX_0F5B */
3901 { "vcvtdq2ps", { XM
, EXx
}, 0 },
3902 { "vcvttps2dq", { XM
, EXx
}, 0 },
3903 { "vcvtps2dq", { XM
, EXx
}, 0 },
3906 /* PREFIX_VEX_0F5C */
3908 { "vsubps", { XM
, Vex
, EXx
}, 0 },
3909 { "vsubss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3910 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
3911 { "vsubsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3914 /* PREFIX_VEX_0F5D */
3916 { "vminps", { XM
, Vex
, EXx
}, 0 },
3917 { "vminss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3918 { "vminpd", { XM
, Vex
, EXx
}, 0 },
3919 { "vminsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3922 /* PREFIX_VEX_0F5E */
3924 { "vdivps", { XM
, Vex
, EXx
}, 0 },
3925 { "vdivss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3926 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
3927 { "vdivsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3930 /* PREFIX_VEX_0F5F */
3932 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
3933 { "vmaxss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3934 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
3935 { "vmaxsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3938 /* PREFIX_VEX_0F6F */
3941 { "vmovdqu", { XM
, EXx
}, 0 },
3942 { "vmovdqa", { XM
, EXx
}, 0 },
3945 /* PREFIX_VEX_0F70 */
3948 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
3949 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
3950 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
3953 /* PREFIX_VEX_0F7C */
3957 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
3958 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
3961 /* PREFIX_VEX_0F7D */
3965 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
3966 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
3969 /* PREFIX_VEX_0F7E */
3972 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
3973 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
3976 /* PREFIX_VEX_0F7F */
3979 { "vmovdqu", { EXxS
, XM
}, 0 },
3980 { "vmovdqa", { EXxS
, XM
}, 0 },
3983 /* PREFIX_VEX_0F90 */
3985 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
3987 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
3990 /* PREFIX_VEX_0F91 */
3992 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
3994 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
3997 /* PREFIX_VEX_0F92 */
3999 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
4001 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
4002 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
4005 /* PREFIX_VEX_0F93 */
4007 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
4009 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
4010 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
4013 /* PREFIX_VEX_0F98 */
4015 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
4017 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
4020 /* PREFIX_VEX_0F99 */
4022 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
4024 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
4027 /* PREFIX_VEX_0FC2 */
4029 { "vcmpps", { XM
, Vex
, EXx
, CMP
}, 0 },
4030 { "vcmpss", { XMScalar
, VexScalar
, EXxmm_md
, CMP
}, 0 },
4031 { "vcmppd", { XM
, Vex
, EXx
, CMP
}, 0 },
4032 { "vcmpsd", { XMScalar
, VexScalar
, EXxmm_mq
, CMP
}, 0 },
4035 /* PREFIX_VEX_0FD0 */
4039 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
4040 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
4043 /* PREFIX_VEX_0FE6 */
4046 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
4047 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
4048 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
4051 /* PREFIX_VEX_0FF0 */
4056 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
4059 /* PREFIX_VEX_0F3849_X86_64 */
4061 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0
) },
4063 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2
) },
4064 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3
) },
4067 /* PREFIX_VEX_0F384B_X86_64 */
4070 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1
) },
4071 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2
) },
4072 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3
) },
4075 /* PREFIX_VEX_0F385C_X86_64 */
4078 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1
) },
4082 /* PREFIX_VEX_0F385E_X86_64 */
4084 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0
) },
4085 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1
) },
4086 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2
) },
4087 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3
) },
4090 /* PREFIX_VEX_0F38F5 */
4092 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
4093 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
4095 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
4098 /* PREFIX_VEX_0F38F6 */
4103 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
4106 /* PREFIX_VEX_0F38F7 */
4108 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
4109 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
4110 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
4111 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
4114 /* PREFIX_VEX_0F3AF0 */
4119 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
4122 #include "i386-dis-evex-prefix.h"
4125 static const struct dis386 x86_64_table
[][2] = {
4128 { "pushP", { es
}, 0 },
4133 { "popP", { es
}, 0 },
4138 { "pushP", { cs
}, 0 },
4143 { "pushP", { ss
}, 0 },
4148 { "popP", { ss
}, 0 },
4153 { "pushP", { ds
}, 0 },
4158 { "popP", { ds
}, 0 },
4163 { "daa", { XX
}, 0 },
4168 { "das", { XX
}, 0 },
4173 { "aaa", { XX
}, 0 },
4178 { "aas", { XX
}, 0 },
4183 { "pushaP", { XX
}, 0 },
4188 { "popaP", { XX
}, 0 },
4193 { MOD_TABLE (MOD_62_32BIT
) },
4194 { EVEX_TABLE (EVEX_0F
) },
4199 { "arpl", { Ew
, Gw
}, 0 },
4200 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
4205 { "ins{R|}", { Yzr
, indirDX
}, 0 },
4206 { "ins{G|}", { Yzr
, indirDX
}, 0 },
4211 { "outs{R|}", { indirDXr
, Xz
}, 0 },
4212 { "outs{G|}", { indirDXr
, Xz
}, 0 },
4217 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4218 { REG_TABLE (REG_80
) },
4223 { "{l|}call{P|}", { Ap
}, 0 },
4228 { "retP", { Iw
, BND
}, 0 },
4229 { "ret@", { Iw
, BND
}, 0 },
4234 { "retP", { BND
}, 0 },
4235 { "ret@", { BND
}, 0 },
4240 { MOD_TABLE (MOD_C4_32BIT
) },
4241 { VEX_C4_TABLE (VEX_0F
) },
4246 { MOD_TABLE (MOD_C5_32BIT
) },
4247 { VEX_C5_TABLE (VEX_0F
) },
4252 { "into", { XX
}, 0 },
4257 { "aam", { Ib
}, 0 },
4262 { "aad", { Ib
}, 0 },
4267 { "callP", { Jv
, BND
}, 0 },
4268 { "call@", { Jv
, BND
}, 0 }
4273 { "jmpP", { Jv
, BND
}, 0 },
4274 { "jmp@", { Jv
, BND
}, 0 }
4279 { "{l|}jmp{P|}", { Ap
}, 0 },
4282 /* X86_64_0F01_REG_0 */
4284 { "sgdt{Q|Q}", { M
}, 0 },
4285 { "sgdt", { M
}, 0 },
4288 /* X86_64_0F01_REG_1 */
4290 { "sidt{Q|Q}", { M
}, 0 },
4291 { "sidt", { M
}, 0 },
4294 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4297 { "seamret", { Skip_MODRM
}, 0 },
4300 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4303 { "seamops", { Skip_MODRM
}, 0 },
4306 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4309 { "seamcall", { Skip_MODRM
}, 0 },
4312 /* X86_64_0F01_REG_2 */
4314 { "lgdt{Q|Q}", { M
}, 0 },
4315 { "lgdt", { M
}, 0 },
4318 /* X86_64_0F01_REG_3 */
4320 { "lidt{Q|Q}", { M
}, 0 },
4321 { "lidt", { M
}, 0 },
4326 { "movZ", { Em
, Td
}, 0 },
4331 { "movZ", { Td
, Em
}, 0 },
4334 /* X86_64_VEX_0F3849 */
4337 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64
) },
4340 /* X86_64_VEX_0F384B */
4343 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64
) },
4346 /* X86_64_VEX_0F385C */
4349 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64
) },
4352 /* X86_64_VEX_0F385E */
4355 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64
) },
4358 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4361 { "uiret", { Skip_MODRM
}, 0 },
4364 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4367 { "testui", { Skip_MODRM
}, 0 },
4370 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4373 { "clui", { Skip_MODRM
}, 0 },
4376 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4379 { "stui", { Skip_MODRM
}, 0 },
4382 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4385 { "senduipi", { Eq
}, 0 },
4389 static const struct dis386 three_byte_table
[][256] = {
4391 /* THREE_BYTE_0F38 */
4394 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
4395 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
4396 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
4397 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
4398 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
4399 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
4400 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
4401 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
4403 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
4404 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
4405 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
4406 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
4412 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4416 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4417 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4419 { "ptest", { XM
, EXx
}, PREFIX_DATA
},
4425 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
4426 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
4427 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
4430 { "pmovsxbw", { XM
, EXq
}, PREFIX_DATA
},
4431 { "pmovsxbd", { XM
, EXd
}, PREFIX_DATA
},
4432 { "pmovsxbq", { XM
, EXw
}, PREFIX_DATA
},
4433 { "pmovsxwd", { XM
, EXq
}, PREFIX_DATA
},
4434 { "pmovsxwq", { XM
, EXd
}, PREFIX_DATA
},
4435 { "pmovsxdq", { XM
, EXq
}, PREFIX_DATA
},
4439 { "pmuldq", { XM
, EXx
}, PREFIX_DATA
},
4440 { "pcmpeqq", { XM
, EXx
}, PREFIX_DATA
},
4441 { MOD_TABLE (MOD_0F382A
) },
4442 { "packusdw", { XM
, EXx
}, PREFIX_DATA
},
4448 { "pmovzxbw", { XM
, EXq
}, PREFIX_DATA
},
4449 { "pmovzxbd", { XM
, EXd
}, PREFIX_DATA
},
4450 { "pmovzxbq", { XM
, EXw
}, PREFIX_DATA
},
4451 { "pmovzxwd", { XM
, EXq
}, PREFIX_DATA
},
4452 { "pmovzxwq", { XM
, EXd
}, PREFIX_DATA
},
4453 { "pmovzxdq", { XM
, EXq
}, PREFIX_DATA
},
4455 { "pcmpgtq", { XM
, EXx
}, PREFIX_DATA
},
4457 { "pminsb", { XM
, EXx
}, PREFIX_DATA
},
4458 { "pminsd", { XM
, EXx
}, PREFIX_DATA
},
4459 { "pminuw", { XM
, EXx
}, PREFIX_DATA
},
4460 { "pminud", { XM
, EXx
}, PREFIX_DATA
},
4461 { "pmaxsb", { XM
, EXx
}, PREFIX_DATA
},
4462 { "pmaxsd", { XM
, EXx
}, PREFIX_DATA
},
4463 { "pmaxuw", { XM
, EXx
}, PREFIX_DATA
},
4464 { "pmaxud", { XM
, EXx
}, PREFIX_DATA
},
4466 { "pmulld", { XM
, EXx
}, PREFIX_DATA
},
4467 { "phminposuw", { XM
, EXx
}, PREFIX_DATA
},
4538 { "invept", { Gm
, Mo
}, PREFIX_DATA
},
4539 { "invvpid", { Gm
, Mo
}, PREFIX_DATA
},
4540 { "invpcid", { Gm
, M
}, PREFIX_DATA
},
4619 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4620 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4621 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4622 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4623 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4624 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4626 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_DATA
},
4637 { PREFIX_TABLE (PREFIX_0F38D8
) },
4640 { "aesimc", { XM
, EXx
}, PREFIX_DATA
},
4641 { PREFIX_TABLE (PREFIX_0F38DC
) },
4642 { PREFIX_TABLE (PREFIX_0F38DD
) },
4643 { PREFIX_TABLE (PREFIX_0F38DE
) },
4644 { PREFIX_TABLE (PREFIX_0F38DF
) },
4664 { PREFIX_TABLE (PREFIX_0F38F0
) },
4665 { PREFIX_TABLE (PREFIX_0F38F1
) },
4669 { MOD_TABLE (MOD_0F38F5
) },
4670 { PREFIX_TABLE (PREFIX_0F38F6
) },
4673 { PREFIX_TABLE (PREFIX_0F38F8
) },
4674 { MOD_TABLE (MOD_0F38F9
) },
4675 { PREFIX_TABLE (PREFIX_0F38FA
) },
4676 { PREFIX_TABLE (PREFIX_0F38FB
) },
4682 /* THREE_BYTE_0F3A */
4694 { "roundps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4695 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4696 { "roundss", { XM
, EXd
, Ib
}, PREFIX_DATA
},
4697 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_DATA
},
4698 { "blendps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4699 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4700 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4701 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
4707 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_DATA
},
4708 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_DATA
},
4709 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_DATA
},
4710 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_DATA
},
4721 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_DATA
},
4722 { "insertps", { XM
, EXd
, Ib
}, PREFIX_DATA
},
4723 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_DATA
},
4757 { "dpps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4758 { "dppd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4759 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4761 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_DATA
},
4793 { "pcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4794 { "pcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4795 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4796 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4914 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4916 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_DATA
},
4917 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_DATA
},
4935 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4955 { PREFIX_TABLE (PREFIX_0F3A0F
) },
4975 static const struct dis386 xop_table
[][256] = {
5128 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85
) },
5129 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86
) },
5130 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87
) },
5138 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E
) },
5139 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F
) },
5146 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95
) },
5147 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96
) },
5148 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97
) },
5156 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E
) },
5157 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F
) },
5161 { "vpcmov", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
5162 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3
) },
5165 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6
) },
5183 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6
) },
5195 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0
) },
5196 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1
) },
5197 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2
) },
5198 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3
) },
5208 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
5209 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
5210 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
5211 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
5244 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
5245 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
5246 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
5247 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
5271 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01
) },
5272 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02
) },
5290 { MOD_TABLE (MOD_VEX_0FXOP_09_12
) },
5414 { VEX_W_TABLE (VEX_W_0FXOP_09_80
) },
5415 { VEX_W_TABLE (VEX_W_0FXOP_09_81
) },
5416 { VEX_W_TABLE (VEX_W_0FXOP_09_82
) },
5417 { VEX_W_TABLE (VEX_W_0FXOP_09_83
) },
5432 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90
) },
5433 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91
) },
5434 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92
) },
5435 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93
) },
5436 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94
) },
5437 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95
) },
5438 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96
) },
5439 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97
) },
5441 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98
) },
5442 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99
) },
5443 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A
) },
5444 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B
) },
5487 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1
) },
5488 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2
) },
5489 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3
) },
5492 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6
) },
5493 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7
) },
5498 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB
) },
5505 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1
) },
5506 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2
) },
5507 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3
) },
5510 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6
) },
5511 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7
) },
5516 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB
) },
5523 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1
) },
5524 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2
) },
5525 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3
) },
5579 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
5581 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12
) },
5851 static const struct dis386 vex_table
[][256] = {
5873 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
5874 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
5875 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
5876 { MOD_TABLE (MOD_VEX_0F13
) },
5877 { "vunpcklpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5878 { "vunpckhpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5879 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
5880 { MOD_TABLE (MOD_VEX_0F17
) },
5900 { "vmovapX", { XM
, EXx
}, PREFIX_OPCODE
},
5901 { "vmovapX", { EXxS
, XM
}, PREFIX_OPCODE
},
5902 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
5903 { MOD_TABLE (MOD_VEX_0F2B
) },
5904 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
5905 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
5906 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
5907 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
5928 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
5929 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
5931 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
5932 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
5933 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
5934 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
5938 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
5939 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
5945 { MOD_TABLE (MOD_VEX_0F50
) },
5946 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
5947 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
5948 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
5949 { "vandpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5950 { "vandnpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5951 { "vorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5952 { "vxorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5954 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
5955 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
5956 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
5957 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
5958 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
5959 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
5960 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
5961 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
5963 { "vpunpcklbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5964 { "vpunpcklwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5965 { "vpunpckldq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5966 { "vpacksswb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5967 { "vpcmpgtb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5968 { "vpcmpgtw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5969 { "vpcmpgtd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5970 { "vpackuswb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5972 { "vpunpckhbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5973 { "vpunpckhwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5974 { "vpunpckhdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5975 { "vpackssdw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5976 { "vpunpcklqdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5977 { "vpunpckhqdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5978 { VEX_LEN_TABLE (VEX_LEN_0F6E
) },
5979 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
5981 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
5982 { REG_TABLE (REG_VEX_0F71
) },
5983 { REG_TABLE (REG_VEX_0F72
) },
5984 { REG_TABLE (REG_VEX_0F73
) },
5985 { "vpcmpeqb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5986 { "vpcmpeqw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5987 { "vpcmpeqd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5988 { VEX_LEN_TABLE (VEX_LEN_0F77
) },
5994 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
5995 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
5996 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
5997 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
6017 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
6018 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
6019 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
6020 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
6026 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
6027 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
6050 { REG_TABLE (REG_VEX_0FAE
) },
6073 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
6075 { VEX_LEN_TABLE (VEX_LEN_0FC4
) },
6076 { VEX_LEN_TABLE (VEX_LEN_0FC5
) },
6077 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, PREFIX_OPCODE
},
6089 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
6090 { "vpsrlw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6091 { "vpsrld", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6092 { "vpsrlq", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6093 { "vpaddq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6094 { "vpmullw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6095 { VEX_LEN_TABLE (VEX_LEN_0FD6
) },
6096 { MOD_TABLE (MOD_VEX_0FD7
) },
6098 { "vpsubusb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6099 { "vpsubusw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6100 { "vpminub", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6101 { "vpand", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6102 { "vpaddusb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6103 { "vpaddusw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6104 { "vpmaxub", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6105 { "vpandn", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6107 { "vpavgb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6108 { "vpsraw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6109 { "vpsrad", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6110 { "vpavgw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6111 { "vpmulhuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6112 { "vpmulhw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6113 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
6114 { MOD_TABLE (MOD_VEX_0FE7
) },
6116 { "vpsubsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6117 { "vpsubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6118 { "vpminsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6119 { "vpor", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6120 { "vpaddsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6121 { "vpaddsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6122 { "vpmaxsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6123 { "vpxor", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6125 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
6126 { "vpsllw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6127 { "vpslld", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6128 { "vpsllq", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6129 { "vpmuludq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6130 { "vpmaddwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6131 { "vpsadbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6132 { VEX_LEN_TABLE (VEX_LEN_0FF7
) },
6134 { "vpsubb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6135 { "vpsubw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6136 { "vpsubd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6137 { "vpsubq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6138 { "vpaddb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6139 { "vpaddw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6140 { "vpaddd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6146 { "vpshufb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6147 { "vphaddw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6148 { "vphaddd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6149 { "vphaddsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6150 { "vpmaddubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6151 { "vphsubw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6152 { "vphsubd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6153 { "vphsubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6155 { "vpsignb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6156 { "vpsignw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6157 { "vpsignd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6158 { "vpmulhrsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6159 { VEX_W_TABLE (VEX_W_0F380C
) },
6160 { VEX_W_TABLE (VEX_W_0F380D
) },
6161 { VEX_W_TABLE (VEX_W_0F380E
) },
6162 { VEX_W_TABLE (VEX_W_0F380F
) },
6167 { VEX_W_TABLE (VEX_W_0F3813
) },
6170 { VEX_LEN_TABLE (VEX_LEN_0F3816
) },
6171 { "vptest", { XM
, EXx
}, PREFIX_DATA
},
6173 { VEX_W_TABLE (VEX_W_0F3818
) },
6174 { VEX_LEN_TABLE (VEX_LEN_0F3819
) },
6175 { MOD_TABLE (MOD_VEX_0F381A
) },
6177 { "vpabsb", { XM
, EXx
}, PREFIX_DATA
},
6178 { "vpabsw", { XM
, EXx
}, PREFIX_DATA
},
6179 { "vpabsd", { XM
, EXx
}, PREFIX_DATA
},
6182 { "vpmovsxbw", { XM
, EXxmmq
}, PREFIX_DATA
},
6183 { "vpmovsxbd", { XM
, EXxmmqd
}, PREFIX_DATA
},
6184 { "vpmovsxbq", { XM
, EXxmmdw
}, PREFIX_DATA
},
6185 { "vpmovsxwd", { XM
, EXxmmq
}, PREFIX_DATA
},
6186 { "vpmovsxwq", { XM
, EXxmmqd
}, PREFIX_DATA
},
6187 { "vpmovsxdq", { XM
, EXxmmq
}, PREFIX_DATA
},
6191 { "vpmuldq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6192 { "vpcmpeqq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6193 { MOD_TABLE (MOD_VEX_0F382A
) },
6194 { "vpackusdw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6195 { MOD_TABLE (MOD_VEX_0F382C
) },
6196 { MOD_TABLE (MOD_VEX_0F382D
) },
6197 { MOD_TABLE (MOD_VEX_0F382E
) },
6198 { MOD_TABLE (MOD_VEX_0F382F
) },
6200 { "vpmovzxbw", { XM
, EXxmmq
}, PREFIX_DATA
},
6201 { "vpmovzxbd", { XM
, EXxmmqd
}, PREFIX_DATA
},
6202 { "vpmovzxbq", { XM
, EXxmmdw
}, PREFIX_DATA
},
6203 { "vpmovzxwd", { XM
, EXxmmq
}, PREFIX_DATA
},
6204 { "vpmovzxwq", { XM
, EXxmmqd
}, PREFIX_DATA
},
6205 { "vpmovzxdq", { XM
, EXxmmq
}, PREFIX_DATA
},
6206 { VEX_LEN_TABLE (VEX_LEN_0F3836
) },
6207 { "vpcmpgtq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6209 { "vpminsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6210 { "vpminsd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6211 { "vpminuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6212 { "vpminud", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6213 { "vpmaxsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6214 { "vpmaxsd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6215 { "vpmaxuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6216 { "vpmaxud", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6218 { "vpmulld", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6219 { VEX_LEN_TABLE (VEX_LEN_0F3841
) },
6223 { "vpsrlv%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6224 { VEX_W_TABLE (VEX_W_0F3846
) },
6225 { "vpsllv%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6228 { X86_64_TABLE (X86_64_VEX_0F3849
) },
6230 { X86_64_TABLE (X86_64_VEX_0F384B
) },
6245 { VEX_W_TABLE (VEX_W_0F3858
) },
6246 { VEX_W_TABLE (VEX_W_0F3859
) },
6247 { MOD_TABLE (MOD_VEX_0F385A
) },
6249 { X86_64_TABLE (X86_64_VEX_0F385C
) },
6251 { X86_64_TABLE (X86_64_VEX_0F385E
) },
6281 { VEX_W_TABLE (VEX_W_0F3878
) },
6282 { VEX_W_TABLE (VEX_W_0F3879
) },
6303 { MOD_TABLE (MOD_VEX_0F388C
) },
6305 { MOD_TABLE (MOD_VEX_0F388E
) },
6308 { "vpgatherd%DQ", { XM
, MVexVSIBDWpX
, Vex
}, PREFIX_DATA
},
6309 { "vpgatherq%DQ", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, PREFIX_DATA
},
6310 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, PREFIX_DATA
},
6311 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, PREFIX_DATA
},
6314 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6315 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6317 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6318 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6319 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6320 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6321 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6322 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6323 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6324 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6332 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6333 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6335 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6336 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6337 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6338 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6339 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6340 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6341 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6342 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6350 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6351 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6353 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6354 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6355 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6356 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6357 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6358 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6359 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6360 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6378 { VEX_W_TABLE (VEX_W_0F38CF
) },
6392 { VEX_LEN_TABLE (VEX_LEN_0F38DB
) },
6393 { "vaesenc", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6394 { "vaesenclast", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6395 { "vaesdec", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6396 { "vaesdeclast", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6418 { VEX_LEN_TABLE (VEX_LEN_0F38F2
) },
6419 { REG_TABLE (REG_VEX_0F38F3
) },
6421 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
6422 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
6423 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
6437 { VEX_LEN_TABLE (VEX_LEN_0F3A00
) },
6438 { VEX_LEN_TABLE (VEX_LEN_0F3A01
) },
6439 { VEX_W_TABLE (VEX_W_0F3A02
) },
6441 { VEX_W_TABLE (VEX_W_0F3A04
) },
6442 { VEX_W_TABLE (VEX_W_0F3A05
) },
6443 { VEX_LEN_TABLE (VEX_LEN_0F3A06
) },
6446 { "vroundps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
6447 { "vroundpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
6448 { "vroundss", { XMScalar
, VexScalar
, EXxmm_md
, Ib
}, PREFIX_DATA
},
6449 { "vroundsd", { XMScalar
, VexScalar
, EXxmm_mq
, Ib
}, PREFIX_DATA
},
6450 { "vblendps", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6451 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6452 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6453 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6459 { VEX_LEN_TABLE (VEX_LEN_0F3A14
) },
6460 { VEX_LEN_TABLE (VEX_LEN_0F3A15
) },
6461 { VEX_LEN_TABLE (VEX_LEN_0F3A16
) },
6462 { VEX_LEN_TABLE (VEX_LEN_0F3A17
) },
6464 { VEX_LEN_TABLE (VEX_LEN_0F3A18
) },
6465 { VEX_LEN_TABLE (VEX_LEN_0F3A19
) },
6469 { VEX_W_TABLE (VEX_W_0F3A1D
) },
6473 { VEX_LEN_TABLE (VEX_LEN_0F3A20
) },
6474 { VEX_LEN_TABLE (VEX_LEN_0F3A21
) },
6475 { VEX_LEN_TABLE (VEX_LEN_0F3A22
) },
6491 { VEX_LEN_TABLE (VEX_LEN_0F3A30
) },
6492 { VEX_LEN_TABLE (VEX_LEN_0F3A31
) },
6493 { VEX_LEN_TABLE (VEX_LEN_0F3A32
) },
6494 { VEX_LEN_TABLE (VEX_LEN_0F3A33
) },
6500 { VEX_LEN_TABLE (VEX_LEN_0F3A38
) },
6501 { VEX_LEN_TABLE (VEX_LEN_0F3A39
) },
6509 { "vdpps", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6510 { VEX_LEN_TABLE (VEX_LEN_0F3A41
) },
6511 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6513 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, PREFIX_DATA
},
6515 { VEX_LEN_TABLE (VEX_LEN_0F3A46
) },
6518 { "vpermil2ps", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, PREFIX_DATA
},
6519 { "vpermil2pd", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, PREFIX_DATA
},
6520 { VEX_W_TABLE (VEX_W_0F3A4A
) },
6521 { VEX_W_TABLE (VEX_W_0F3A4B
) },
6522 { VEX_W_TABLE (VEX_W_0F3A4C
) },
6540 { "vfmaddsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6541 { "vfmaddsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6542 { "vfmsubaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6543 { "vfmsubaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6545 { VEX_LEN_TABLE (VEX_LEN_0F3A60
) },
6546 { VEX_LEN_TABLE (VEX_LEN_0F3A61
) },
6547 { VEX_LEN_TABLE (VEX_LEN_0F3A62
) },
6548 { VEX_LEN_TABLE (VEX_LEN_0F3A63
) },
6554 { "vfmaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6555 { "vfmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6556 { "vfmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6557 { "vfmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6558 { "vfmsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6559 { "vfmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6560 { "vfmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6561 { "vfmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6572 { "vfnmaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6573 { "vfnmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6574 { "vfnmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6575 { "vfnmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6576 { "vfnmsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6577 { "vfnmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6578 { "vfnmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6579 { "vfnmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6668 { VEX_W_TABLE (VEX_W_0F3ACE
) },
6669 { VEX_W_TABLE (VEX_W_0F3ACF
) },
6687 { VEX_LEN_TABLE (VEX_LEN_0F3ADF
) },
6707 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
6727 #include "i386-dis-evex.h"
6729 static const struct dis386 vex_len_table
[][2] = {
6730 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6732 { "vmovlpX", { XM
, Vex
, EXq
}, 0 },
6735 /* VEX_LEN_0F12_P_0_M_1 */
6737 { "vmovhlps", { XM
, Vex
, EXq
}, 0 },
6740 /* VEX_LEN_0F13_M_0 */
6742 { "vmovlpX", { EXq
, XM
}, PREFIX_OPCODE
},
6745 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6747 { "vmovhpX", { XM
, Vex
, EXq
}, 0 },
6750 /* VEX_LEN_0F16_P_0_M_1 */
6752 { "vmovlhps", { XM
, Vex
, EXq
}, 0 },
6755 /* VEX_LEN_0F17_M_0 */
6757 { "vmovhpX", { EXq
, XM
}, PREFIX_OPCODE
},
6760 /* VEX_LEN_0F41_P_0 */
6763 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
6765 /* VEX_LEN_0F41_P_2 */
6768 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
6770 /* VEX_LEN_0F42_P_0 */
6773 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
6775 /* VEX_LEN_0F42_P_2 */
6778 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
6780 /* VEX_LEN_0F44_P_0 */
6782 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
6784 /* VEX_LEN_0F44_P_2 */
6786 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
6788 /* VEX_LEN_0F45_P_0 */
6791 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
6793 /* VEX_LEN_0F45_P_2 */
6796 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
6798 /* VEX_LEN_0F46_P_0 */
6801 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
6803 /* VEX_LEN_0F46_P_2 */
6806 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
6808 /* VEX_LEN_0F47_P_0 */
6811 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
6813 /* VEX_LEN_0F47_P_2 */
6816 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
6818 /* VEX_LEN_0F4A_P_0 */
6821 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
6823 /* VEX_LEN_0F4A_P_2 */
6826 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
6828 /* VEX_LEN_0F4B_P_0 */
6831 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
6833 /* VEX_LEN_0F4B_P_2 */
6836 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
6841 { "vmovK", { XMScalar
, Edq
}, PREFIX_DATA
},
6846 { "vzeroupper", { XX
}, 0 },
6847 { "vzeroall", { XX
}, 0 },
6850 /* VEX_LEN_0F7E_P_1 */
6852 { "vmovq", { XMScalar
, EXxmm_mq
}, 0 },
6855 /* VEX_LEN_0F7E_P_2 */
6857 { "vmovK", { Edq
, XMScalar
}, 0 },
6860 /* VEX_LEN_0F90_P_0 */
6862 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
6865 /* VEX_LEN_0F90_P_2 */
6867 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
6870 /* VEX_LEN_0F91_P_0 */
6872 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
6875 /* VEX_LEN_0F91_P_2 */
6877 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
6880 /* VEX_LEN_0F92_P_0 */
6882 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
6885 /* VEX_LEN_0F92_P_2 */
6887 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
6890 /* VEX_LEN_0F92_P_3 */
6892 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
6895 /* VEX_LEN_0F93_P_0 */
6897 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
6900 /* VEX_LEN_0F93_P_2 */
6902 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
6905 /* VEX_LEN_0F93_P_3 */
6907 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
6910 /* VEX_LEN_0F98_P_0 */
6912 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
6915 /* VEX_LEN_0F98_P_2 */
6917 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
6920 /* VEX_LEN_0F99_P_0 */
6922 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
6925 /* VEX_LEN_0F99_P_2 */
6927 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
6930 /* VEX_LEN_0FAE_R_2_M_0 */
6932 { "vldmxcsr", { Md
}, 0 },
6935 /* VEX_LEN_0FAE_R_3_M_0 */
6937 { "vstmxcsr", { Md
}, 0 },
6942 { "vpinsrw", { XM
, Vex
, Edqw
, Ib
}, PREFIX_DATA
},
6947 { "vpextrw", { Gdq
, XS
, Ib
}, PREFIX_DATA
},
6952 { "vmovq", { EXqS
, XMScalar
}, PREFIX_DATA
},
6957 { "vmaskmovdqu", { XM
, XS
}, PREFIX_DATA
},
6960 /* VEX_LEN_0F3816 */
6963 { VEX_W_TABLE (VEX_W_0F3816_L_1
) },
6966 /* VEX_LEN_0F3819 */
6969 { VEX_W_TABLE (VEX_W_0F3819_L_1
) },
6972 /* VEX_LEN_0F381A_M_0 */
6975 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1
) },
6978 /* VEX_LEN_0F3836 */
6981 { VEX_W_TABLE (VEX_W_0F3836
) },
6984 /* VEX_LEN_0F3841 */
6986 { "vphminposuw", { XM
, EXx
}, PREFIX_DATA
},
6989 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6991 { "ldtilecfg", { M
}, 0 },
6994 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6996 { "tilerelease", { Skip_MODRM
}, 0 },
6999 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
7001 { "sttilecfg", { M
}, 0 },
7004 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
7006 { "tilezero", { TMM
, Skip_MODRM
}, 0 },
7009 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
7011 { "tilestored", { MVexSIBMEM
, TMM
}, 0 },
7013 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
7015 { "tileloaddt1", { TMM
, MVexSIBMEM
}, 0 },
7018 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
7020 { "tileloadd", { TMM
, MVexSIBMEM
}, 0 },
7023 /* VEX_LEN_0F385A_M_0 */
7026 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0
) },
7029 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
7031 { "tdpbf16ps", { TMM
, EXtmm
, VexTmm
}, 0 },
7034 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
7036 { "tdpbuud", {TMM
, EXtmm
, VexTmm
}, 0 },
7039 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
7041 { "tdpbsud", {TMM
, EXtmm
, VexTmm
}, 0 },
7044 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
7046 { "tdpbusd", {TMM
, EXtmm
, VexTmm
}, 0 },
7049 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
7051 { "tdpbssd", {TMM
, EXtmm
, VexTmm
}, 0 },
7054 /* VEX_LEN_0F38DB */
7056 { "vaesimc", { XM
, EXx
}, PREFIX_DATA
},
7059 /* VEX_LEN_0F38F2 */
7061 { "andnS", { Gdq
, VexGdq
, Edq
}, PREFIX_OPCODE
},
7064 /* VEX_LEN_0F38F3_R_1 */
7066 { "blsrS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
7069 /* VEX_LEN_0F38F3_R_2 */
7071 { "blsmskS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
7074 /* VEX_LEN_0F38F3_R_3 */
7076 { "blsiS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
7079 /* VEX_LEN_0F38F5_P_0 */
7081 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
7084 /* VEX_LEN_0F38F5_P_1 */
7086 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
7089 /* VEX_LEN_0F38F5_P_3 */
7091 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
7094 /* VEX_LEN_0F38F6_P_3 */
7096 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
7099 /* VEX_LEN_0F38F7_P_0 */
7101 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
7104 /* VEX_LEN_0F38F7_P_1 */
7106 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
7109 /* VEX_LEN_0F38F7_P_2 */
7111 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
7114 /* VEX_LEN_0F38F7_P_3 */
7116 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
7119 /* VEX_LEN_0F3A00 */
7122 { VEX_W_TABLE (VEX_W_0F3A00_L_1
) },
7125 /* VEX_LEN_0F3A01 */
7128 { VEX_W_TABLE (VEX_W_0F3A01_L_1
) },
7131 /* VEX_LEN_0F3A06 */
7134 { VEX_W_TABLE (VEX_W_0F3A06_L_1
) },
7137 /* VEX_LEN_0F3A14 */
7139 { "vpextrb", { Edqb
, XM
, Ib
}, PREFIX_DATA
},
7142 /* VEX_LEN_0F3A15 */
7144 { "vpextrw", { Edqw
, XM
, Ib
}, PREFIX_DATA
},
7147 /* VEX_LEN_0F3A16 */
7149 { "vpextrK", { Edq
, XM
, Ib
}, PREFIX_DATA
},
7152 /* VEX_LEN_0F3A17 */
7154 { "vextractps", { Edqd
, XM
, Ib
}, PREFIX_DATA
},
7157 /* VEX_LEN_0F3A18 */
7160 { VEX_W_TABLE (VEX_W_0F3A18_L_1
) },
7163 /* VEX_LEN_0F3A19 */
7166 { VEX_W_TABLE (VEX_W_0F3A19_L_1
) },
7169 /* VEX_LEN_0F3A20 */
7171 { "vpinsrb", { XM
, Vex
, Edqb
, Ib
}, PREFIX_DATA
},
7174 /* VEX_LEN_0F3A21 */
7176 { "vinsertps", { XM
, Vex
, EXd
, Ib
}, PREFIX_DATA
},
7179 /* VEX_LEN_0F3A22 */
7181 { "vpinsrK", { XM
, Vex
, Edq
, Ib
}, PREFIX_DATA
},
7184 /* VEX_LEN_0F3A30 */
7186 { MOD_TABLE (MOD_VEX_0F3A30_L_0
) },
7189 /* VEX_LEN_0F3A31 */
7191 { MOD_TABLE (MOD_VEX_0F3A31_L_0
) },
7194 /* VEX_LEN_0F3A32 */
7196 { MOD_TABLE (MOD_VEX_0F3A32_L_0
) },
7199 /* VEX_LEN_0F3A33 */
7201 { MOD_TABLE (MOD_VEX_0F3A33_L_0
) },
7204 /* VEX_LEN_0F3A38 */
7207 { VEX_W_TABLE (VEX_W_0F3A38_L_1
) },
7210 /* VEX_LEN_0F3A39 */
7213 { VEX_W_TABLE (VEX_W_0F3A39_L_1
) },
7216 /* VEX_LEN_0F3A41 */
7218 { "vdppd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7221 /* VEX_LEN_0F3A46 */
7224 { VEX_W_TABLE (VEX_W_0F3A46_L_1
) },
7227 /* VEX_LEN_0F3A60 */
7229 { "vpcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7232 /* VEX_LEN_0F3A61 */
7234 { "vpcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7237 /* VEX_LEN_0F3A62 */
7239 { "vpcmpistrm", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7242 /* VEX_LEN_0F3A63 */
7244 { "vpcmpistri", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7247 /* VEX_LEN_0F3ADF */
7249 { "vaeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7252 /* VEX_LEN_0F3AF0_P_3 */
7254 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
7257 /* VEX_LEN_0FXOP_08_85 */
7259 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0
) },
7262 /* VEX_LEN_0FXOP_08_86 */
7264 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0
) },
7267 /* VEX_LEN_0FXOP_08_87 */
7269 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0
) },
7272 /* VEX_LEN_0FXOP_08_8E */
7274 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0
) },
7277 /* VEX_LEN_0FXOP_08_8F */
7279 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0
) },
7282 /* VEX_LEN_0FXOP_08_95 */
7284 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0
) },
7287 /* VEX_LEN_0FXOP_08_96 */
7289 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0
) },
7292 /* VEX_LEN_0FXOP_08_97 */
7294 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0
) },
7297 /* VEX_LEN_0FXOP_08_9E */
7299 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0
) },
7302 /* VEX_LEN_0FXOP_08_9F */
7304 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0
) },
7307 /* VEX_LEN_0FXOP_08_A3 */
7309 { "vpperm", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7312 /* VEX_LEN_0FXOP_08_A6 */
7314 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0
) },
7317 /* VEX_LEN_0FXOP_08_B6 */
7319 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0
) },
7322 /* VEX_LEN_0FXOP_08_C0 */
7324 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0
) },
7327 /* VEX_LEN_0FXOP_08_C1 */
7329 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0
) },
7332 /* VEX_LEN_0FXOP_08_C2 */
7334 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0
) },
7337 /* VEX_LEN_0FXOP_08_C3 */
7339 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0
) },
7342 /* VEX_LEN_0FXOP_08_CC */
7344 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0
) },
7347 /* VEX_LEN_0FXOP_08_CD */
7349 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0
) },
7352 /* VEX_LEN_0FXOP_08_CE */
7354 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0
) },
7357 /* VEX_LEN_0FXOP_08_CF */
7359 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0
) },
7362 /* VEX_LEN_0FXOP_08_EC */
7364 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0
) },
7367 /* VEX_LEN_0FXOP_08_ED */
7369 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0
) },
7372 /* VEX_LEN_0FXOP_08_EE */
7374 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0
) },
7377 /* VEX_LEN_0FXOP_08_EF */
7379 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0
) },
7382 /* VEX_LEN_0FXOP_09_01 */
7384 { REG_TABLE (REG_0FXOP_09_01_L_0
) },
7387 /* VEX_LEN_0FXOP_09_02 */
7389 { REG_TABLE (REG_0FXOP_09_02_L_0
) },
7392 /* VEX_LEN_0FXOP_09_12_M_1 */
7394 { REG_TABLE (REG_0FXOP_09_12_M_1_L_0
) },
7397 /* VEX_LEN_0FXOP_09_82_W_0 */
7399 { "vfrczss", { XM
, EXd
}, 0 },
7402 /* VEX_LEN_0FXOP_09_83_W_0 */
7404 { "vfrczsd", { XM
, EXq
}, 0 },
7407 /* VEX_LEN_0FXOP_09_90 */
7409 { "vprotb", { XM
, EXx
, VexW
}, 0 },
7412 /* VEX_LEN_0FXOP_09_91 */
7414 { "vprotw", { XM
, EXx
, VexW
}, 0 },
7417 /* VEX_LEN_0FXOP_09_92 */
7419 { "vprotd", { XM
, EXx
, VexW
}, 0 },
7422 /* VEX_LEN_0FXOP_09_93 */
7424 { "vprotq", { XM
, EXx
, VexW
}, 0 },
7427 /* VEX_LEN_0FXOP_09_94 */
7429 { "vpshlb", { XM
, EXx
, VexW
}, 0 },
7432 /* VEX_LEN_0FXOP_09_95 */
7434 { "vpshlw", { XM
, EXx
, VexW
}, 0 },
7437 /* VEX_LEN_0FXOP_09_96 */
7439 { "vpshld", { XM
, EXx
, VexW
}, 0 },
7442 /* VEX_LEN_0FXOP_09_97 */
7444 { "vpshlq", { XM
, EXx
, VexW
}, 0 },
7447 /* VEX_LEN_0FXOP_09_98 */
7449 { "vpshab", { XM
, EXx
, VexW
}, 0 },
7452 /* VEX_LEN_0FXOP_09_99 */
7454 { "vpshaw", { XM
, EXx
, VexW
}, 0 },
7457 /* VEX_LEN_0FXOP_09_9A */
7459 { "vpshad", { XM
, EXx
, VexW
}, 0 },
7462 /* VEX_LEN_0FXOP_09_9B */
7464 { "vpshaq", { XM
, EXx
, VexW
}, 0 },
7467 /* VEX_LEN_0FXOP_09_C1 */
7469 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0
) },
7472 /* VEX_LEN_0FXOP_09_C2 */
7474 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0
) },
7477 /* VEX_LEN_0FXOP_09_C3 */
7479 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0
) },
7482 /* VEX_LEN_0FXOP_09_C6 */
7484 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0
) },
7487 /* VEX_LEN_0FXOP_09_C7 */
7489 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0
) },
7492 /* VEX_LEN_0FXOP_09_CB */
7494 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0
) },
7497 /* VEX_LEN_0FXOP_09_D1 */
7499 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0
) },
7502 /* VEX_LEN_0FXOP_09_D2 */
7504 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0
) },
7507 /* VEX_LEN_0FXOP_09_D3 */
7509 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0
) },
7512 /* VEX_LEN_0FXOP_09_D6 */
7514 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0
) },
7517 /* VEX_LEN_0FXOP_09_D7 */
7519 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0
) },
7522 /* VEX_LEN_0FXOP_09_DB */
7524 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0
) },
7527 /* VEX_LEN_0FXOP_09_E1 */
7529 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0
) },
7532 /* VEX_LEN_0FXOP_09_E2 */
7534 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0
) },
7537 /* VEX_LEN_0FXOP_09_E3 */
7539 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0
) },
7542 /* VEX_LEN_0FXOP_0A_12 */
7544 { REG_TABLE (REG_0FXOP_0A_12_L_0
) },
7548 #include "i386-dis-evex-len.h"
7550 static const struct dis386 vex_w_table
[][2] = {
7552 /* VEX_W_0F41_P_0_LEN_1 */
7553 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
7554 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
7557 /* VEX_W_0F41_P_2_LEN_1 */
7558 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
7559 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
7562 /* VEX_W_0F42_P_0_LEN_1 */
7563 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
7564 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
7567 /* VEX_W_0F42_P_2_LEN_1 */
7568 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
7569 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
7572 /* VEX_W_0F44_P_0_LEN_0 */
7573 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
7574 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
7577 /* VEX_W_0F44_P_2_LEN_0 */
7578 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
7579 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
7582 /* VEX_W_0F45_P_0_LEN_1 */
7583 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
7584 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
7587 /* VEX_W_0F45_P_2_LEN_1 */
7588 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
7589 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
7592 /* VEX_W_0F46_P_0_LEN_1 */
7593 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
7594 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
7597 /* VEX_W_0F46_P_2_LEN_1 */
7598 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
7599 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
7602 /* VEX_W_0F47_P_0_LEN_1 */
7603 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
7604 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
7607 /* VEX_W_0F47_P_2_LEN_1 */
7608 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
7609 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
7612 /* VEX_W_0F4A_P_0_LEN_1 */
7613 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
7614 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
7617 /* VEX_W_0F4A_P_2_LEN_1 */
7618 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
7619 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
7622 /* VEX_W_0F4B_P_0_LEN_1 */
7623 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
7624 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
7627 /* VEX_W_0F4B_P_2_LEN_1 */
7628 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
7631 /* VEX_W_0F90_P_0_LEN_0 */
7632 { "kmovw", { MaskG
, MaskE
}, 0 },
7633 { "kmovq", { MaskG
, MaskE
}, 0 },
7636 /* VEX_W_0F90_P_2_LEN_0 */
7637 { "kmovb", { MaskG
, MaskBDE
}, 0 },
7638 { "kmovd", { MaskG
, MaskBDE
}, 0 },
7641 /* VEX_W_0F91_P_0_LEN_0 */
7642 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
7643 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
7646 /* VEX_W_0F91_P_2_LEN_0 */
7647 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
7648 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
7651 /* VEX_W_0F92_P_0_LEN_0 */
7652 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
7655 /* VEX_W_0F92_P_2_LEN_0 */
7656 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
7659 /* VEX_W_0F93_P_0_LEN_0 */
7660 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
7663 /* VEX_W_0F93_P_2_LEN_0 */
7664 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
7667 /* VEX_W_0F98_P_0_LEN_0 */
7668 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
7669 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
7672 /* VEX_W_0F98_P_2_LEN_0 */
7673 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
7674 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
7677 /* VEX_W_0F99_P_0_LEN_0 */
7678 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
7679 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
7682 /* VEX_W_0F99_P_2_LEN_0 */
7683 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
7684 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
7688 { "vpermilps", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7692 { "vpermilpd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7696 { "vtestps", { XM
, EXx
}, PREFIX_DATA
},
7700 { "vtestpd", { XM
, EXx
}, PREFIX_DATA
},
7704 { "vcvtph2ps", { XM
, EXxmmq
}, PREFIX_DATA
},
7707 /* VEX_W_0F3816_L_1 */
7708 { "vpermps", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7712 { "vbroadcastss", { XM
, EXxmm_md
}, PREFIX_DATA
},
7715 /* VEX_W_0F3819_L_1 */
7716 { "vbroadcastsd", { XM
, EXxmm_mq
}, PREFIX_DATA
},
7719 /* VEX_W_0F381A_M_0_L_1 */
7720 { "vbroadcastf128", { XM
, Mxmm
}, PREFIX_DATA
},
7723 /* VEX_W_0F382C_M_0 */
7724 { "vmaskmovps", { XM
, Vex
, Mx
}, PREFIX_DATA
},
7727 /* VEX_W_0F382D_M_0 */
7728 { "vmaskmovpd", { XM
, Vex
, Mx
}, PREFIX_DATA
},
7731 /* VEX_W_0F382E_M_0 */
7732 { "vmaskmovps", { Mx
, Vex
, XM
}, PREFIX_DATA
},
7735 /* VEX_W_0F382F_M_0 */
7736 { "vmaskmovpd", { Mx
, Vex
, XM
}, PREFIX_DATA
},
7740 { "vpermd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7744 { "vpsravd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7747 /* VEX_W_0F3849_X86_64_P_0 */
7748 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0
) },
7751 /* VEX_W_0F3849_X86_64_P_2 */
7752 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0
) },
7755 /* VEX_W_0F3849_X86_64_P_3 */
7756 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0
) },
7759 /* VEX_W_0F384B_X86_64_P_1 */
7760 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0
) },
7763 /* VEX_W_0F384B_X86_64_P_2 */
7764 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0
) },
7767 /* VEX_W_0F384B_X86_64_P_3 */
7768 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0
) },
7772 { "vpbroadcastd", { XM
, EXxmm_md
}, PREFIX_DATA
},
7776 { "vpbroadcastq", { XM
, EXxmm_mq
}, PREFIX_DATA
},
7779 /* VEX_W_0F385A_M_0_L_0 */
7780 { "vbroadcasti128", { XM
, Mxmm
}, PREFIX_DATA
},
7783 /* VEX_W_0F385C_X86_64_P_1 */
7784 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0
) },
7787 /* VEX_W_0F385E_X86_64_P_0 */
7788 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0
) },
7791 /* VEX_W_0F385E_X86_64_P_1 */
7792 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0
) },
7795 /* VEX_W_0F385E_X86_64_P_2 */
7796 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0
) },
7799 /* VEX_W_0F385E_X86_64_P_3 */
7800 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0
) },
7804 { "vpbroadcastb", { XM
, EXxmm_mb
}, PREFIX_DATA
},
7808 { "vpbroadcastw", { XM
, EXxmm_mw
}, PREFIX_DATA
},
7812 { "vgf2p8mulb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7815 /* VEX_W_0F3A00_L_1 */
7817 { "vpermq", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7820 /* VEX_W_0F3A01_L_1 */
7822 { "vpermpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7826 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7830 { "vpermilps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7834 { "vpermilpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7837 /* VEX_W_0F3A06_L_1 */
7838 { "vperm2f128", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7841 /* VEX_W_0F3A18_L_1 */
7842 { "vinsertf128", { XM
, Vex
, EXxmm
, Ib
}, PREFIX_DATA
},
7845 /* VEX_W_0F3A19_L_1 */
7846 { "vextractf128", { EXxmm
, XM
, Ib
}, PREFIX_DATA
},
7850 { "vcvtps2ph", { EXxmmq
, XM
, EXxEVexS
, Ib
}, PREFIX_DATA
},
7853 /* VEX_W_0F3A38_L_1 */
7854 { "vinserti128", { XM
, Vex
, EXxmm
, Ib
}, PREFIX_DATA
},
7857 /* VEX_W_0F3A39_L_1 */
7858 { "vextracti128", { EXxmm
, XM
, Ib
}, PREFIX_DATA
},
7861 /* VEX_W_0F3A46_L_1 */
7862 { "vperm2i128", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7866 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7870 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7874 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7879 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7884 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7886 /* VEX_W_0FXOP_08_85_L_0 */
7888 { "vpmacssww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7890 /* VEX_W_0FXOP_08_86_L_0 */
7892 { "vpmacsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7894 /* VEX_W_0FXOP_08_87_L_0 */
7896 { "vpmacssdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7898 /* VEX_W_0FXOP_08_8E_L_0 */
7900 { "vpmacssdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7902 /* VEX_W_0FXOP_08_8F_L_0 */
7904 { "vpmacssdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7906 /* VEX_W_0FXOP_08_95_L_0 */
7908 { "vpmacsww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7910 /* VEX_W_0FXOP_08_96_L_0 */
7912 { "vpmacswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7914 /* VEX_W_0FXOP_08_97_L_0 */
7916 { "vpmacsdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7918 /* VEX_W_0FXOP_08_9E_L_0 */
7920 { "vpmacsdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7922 /* VEX_W_0FXOP_08_9F_L_0 */
7924 { "vpmacsdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7926 /* VEX_W_0FXOP_08_A6_L_0 */
7928 { "vpmadcsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7930 /* VEX_W_0FXOP_08_B6_L_0 */
7932 { "vpmadcswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7934 /* VEX_W_0FXOP_08_C0_L_0 */
7936 { "vprotb", { XM
, EXx
, Ib
}, 0 },
7938 /* VEX_W_0FXOP_08_C1_L_0 */
7940 { "vprotw", { XM
, EXx
, Ib
}, 0 },
7942 /* VEX_W_0FXOP_08_C2_L_0 */
7944 { "vprotd", { XM
, EXx
, Ib
}, 0 },
7946 /* VEX_W_0FXOP_08_C3_L_0 */
7948 { "vprotq", { XM
, EXx
, Ib
}, 0 },
7950 /* VEX_W_0FXOP_08_CC_L_0 */
7952 { "vpcomb", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7954 /* VEX_W_0FXOP_08_CD_L_0 */
7956 { "vpcomw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7958 /* VEX_W_0FXOP_08_CE_L_0 */
7960 { "vpcomd", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7962 /* VEX_W_0FXOP_08_CF_L_0 */
7964 { "vpcomq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7966 /* VEX_W_0FXOP_08_EC_L_0 */
7968 { "vpcomub", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7970 /* VEX_W_0FXOP_08_ED_L_0 */
7972 { "vpcomuw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7974 /* VEX_W_0FXOP_08_EE_L_0 */
7976 { "vpcomud", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7978 /* VEX_W_0FXOP_08_EF_L_0 */
7980 { "vpcomuq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7982 /* VEX_W_0FXOP_09_80 */
7984 { "vfrczps", { XM
, EXx
}, 0 },
7986 /* VEX_W_0FXOP_09_81 */
7988 { "vfrczpd", { XM
, EXx
}, 0 },
7990 /* VEX_W_0FXOP_09_82 */
7992 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0
) },
7994 /* VEX_W_0FXOP_09_83 */
7996 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0
) },
7998 /* VEX_W_0FXOP_09_C1_L_0 */
8000 { "vphaddbw", { XM
, EXxmm
}, 0 },
8002 /* VEX_W_0FXOP_09_C2_L_0 */
8004 { "vphaddbd", { XM
, EXxmm
}, 0 },
8006 /* VEX_W_0FXOP_09_C3_L_0 */
8008 { "vphaddbq", { XM
, EXxmm
}, 0 },
8010 /* VEX_W_0FXOP_09_C6_L_0 */
8012 { "vphaddwd", { XM
, EXxmm
}, 0 },
8014 /* VEX_W_0FXOP_09_C7_L_0 */
8016 { "vphaddwq", { XM
, EXxmm
}, 0 },
8018 /* VEX_W_0FXOP_09_CB_L_0 */
8020 { "vphadddq", { XM
, EXxmm
}, 0 },
8022 /* VEX_W_0FXOP_09_D1_L_0 */
8024 { "vphaddubw", { XM
, EXxmm
}, 0 },
8026 /* VEX_W_0FXOP_09_D2_L_0 */
8028 { "vphaddubd", { XM
, EXxmm
}, 0 },
8030 /* VEX_W_0FXOP_09_D3_L_0 */
8032 { "vphaddubq", { XM
, EXxmm
}, 0 },
8034 /* VEX_W_0FXOP_09_D6_L_0 */
8036 { "vphadduwd", { XM
, EXxmm
}, 0 },
8038 /* VEX_W_0FXOP_09_D7_L_0 */
8040 { "vphadduwq", { XM
, EXxmm
}, 0 },
8042 /* VEX_W_0FXOP_09_DB_L_0 */
8044 { "vphaddudq", { XM
, EXxmm
}, 0 },
8046 /* VEX_W_0FXOP_09_E1_L_0 */
8048 { "vphsubbw", { XM
, EXxmm
}, 0 },
8050 /* VEX_W_0FXOP_09_E2_L_0 */
8052 { "vphsubwd", { XM
, EXxmm
}, 0 },
8054 /* VEX_W_0FXOP_09_E3_L_0 */
8056 { "vphsubdq", { XM
, EXxmm
}, 0 },
8059 #include "i386-dis-evex-w.h"
8062 static const struct dis386 mod_table
[][2] = {
8065 { "leaS", { Gv
, M
}, 0 },
8070 { RM_TABLE (RM_C6_REG_7
) },
8075 { RM_TABLE (RM_C7_REG_7
) },
8079 { "{l|}call^", { indirEp
}, 0 },
8083 { "{l|}jmp^", { indirEp
}, 0 },
8086 /* MOD_0F01_REG_0 */
8087 { X86_64_TABLE (X86_64_0F01_REG_0
) },
8088 { RM_TABLE (RM_0F01_REG_0
) },
8091 /* MOD_0F01_REG_1 */
8092 { X86_64_TABLE (X86_64_0F01_REG_1
) },
8093 { RM_TABLE (RM_0F01_REG_1
) },
8096 /* MOD_0F01_REG_2 */
8097 { X86_64_TABLE (X86_64_0F01_REG_2
) },
8098 { RM_TABLE (RM_0F01_REG_2
) },
8101 /* MOD_0F01_REG_3 */
8102 { X86_64_TABLE (X86_64_0F01_REG_3
) },
8103 { RM_TABLE (RM_0F01_REG_3
) },
8106 /* MOD_0F01_REG_5 */
8107 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
8108 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
8111 /* MOD_0F01_REG_7 */
8112 { "invlpg", { Mb
}, 0 },
8113 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
8116 /* MOD_0F12_PREFIX_0 */
8117 { "movlpX", { XM
, EXq
}, 0 },
8118 { "movhlps", { XM
, EXq
}, 0 },
8121 /* MOD_0F12_PREFIX_2 */
8122 { "movlpX", { XM
, EXq
}, 0 },
8126 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
8129 /* MOD_0F16_PREFIX_0 */
8130 { "movhpX", { XM
, EXq
}, 0 },
8131 { "movlhps", { XM
, EXq
}, 0 },
8134 /* MOD_0F16_PREFIX_2 */
8135 { "movhpX", { XM
, EXq
}, 0 },
8139 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
8142 /* MOD_0F18_REG_0 */
8143 { "prefetchnta", { Mb
}, 0 },
8146 /* MOD_0F18_REG_1 */
8147 { "prefetcht0", { Mb
}, 0 },
8150 /* MOD_0F18_REG_2 */
8151 { "prefetcht1", { Mb
}, 0 },
8154 /* MOD_0F18_REG_3 */
8155 { "prefetcht2", { Mb
}, 0 },
8158 /* MOD_0F18_REG_4 */
8159 { "nop/reserved", { Mb
}, 0 },
8162 /* MOD_0F18_REG_5 */
8163 { "nop/reserved", { Mb
}, 0 },
8166 /* MOD_0F18_REG_6 */
8167 { "nop/reserved", { Mb
}, 0 },
8170 /* MOD_0F18_REG_7 */
8171 { "nop/reserved", { Mb
}, 0 },
8174 /* MOD_0F1A_PREFIX_0 */
8175 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
8176 { "nopQ", { Ev
}, 0 },
8179 /* MOD_0F1B_PREFIX_0 */
8180 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
8181 { "nopQ", { Ev
}, 0 },
8184 /* MOD_0F1B_PREFIX_1 */
8185 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
8186 { "nopQ", { Ev
}, 0 },
8189 /* MOD_0F1C_PREFIX_0 */
8190 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
8191 { "nopQ", { Ev
}, 0 },
8194 /* MOD_0F1E_PREFIX_1 */
8195 { "nopQ", { Ev
}, 0 },
8196 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
8199 /* MOD_0F2B_PREFIX_0 */
8200 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
8203 /* MOD_0F2B_PREFIX_1 */
8204 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
8207 /* MOD_0F2B_PREFIX_2 */
8208 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
8211 /* MOD_0F2B_PREFIX_3 */
8212 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
8217 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
8220 /* MOD_0F71_REG_2 */
8222 { "psrlw", { MS
, Ib
}, PREFIX_OPCODE
},
8225 /* MOD_0F71_REG_4 */
8227 { "psraw", { MS
, Ib
}, PREFIX_OPCODE
},
8230 /* MOD_0F71_REG_6 */
8232 { "psllw", { MS
, Ib
}, PREFIX_OPCODE
},
8235 /* MOD_0F72_REG_2 */
8237 { "psrld", { MS
, Ib
}, PREFIX_OPCODE
},
8240 /* MOD_0F72_REG_4 */
8242 { "psrad", { MS
, Ib
}, PREFIX_OPCODE
},
8245 /* MOD_0F72_REG_6 */
8247 { "pslld", { MS
, Ib
}, PREFIX_OPCODE
},
8250 /* MOD_0F73_REG_2 */
8252 { "psrlq", { MS
, Ib
}, PREFIX_OPCODE
},
8255 /* MOD_0F73_REG_3 */
8257 { "psrldq", { XS
, Ib
}, PREFIX_DATA
},
8260 /* MOD_0F73_REG_6 */
8262 { "psllq", { MS
, Ib
}, PREFIX_OPCODE
},
8265 /* MOD_0F73_REG_7 */
8267 { "pslldq", { XS
, Ib
}, PREFIX_DATA
},
8270 /* MOD_0FAE_REG_0 */
8271 { "fxsave", { FXSAVE
}, 0 },
8272 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
8275 /* MOD_0FAE_REG_1 */
8276 { "fxrstor", { FXSAVE
}, 0 },
8277 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
8280 /* MOD_0FAE_REG_2 */
8281 { "ldmxcsr", { Md
}, 0 },
8282 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
8285 /* MOD_0FAE_REG_3 */
8286 { "stmxcsr", { Md
}, 0 },
8287 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
8290 /* MOD_0FAE_REG_4 */
8291 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
8292 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
8295 /* MOD_0FAE_REG_5 */
8296 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
8297 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
8300 /* MOD_0FAE_REG_6 */
8301 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
8302 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
8305 /* MOD_0FAE_REG_7 */
8306 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
8307 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
8311 { "lssS", { Gv
, Mp
}, 0 },
8315 { "lfsS", { Gv
, Mp
}, 0 },
8319 { "lgsS", { Gv
, Mp
}, 0 },
8323 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
8326 /* MOD_0FC7_REG_3 */
8327 { "xrstors", { FXSAVE
}, 0 },
8330 /* MOD_0FC7_REG_4 */
8331 { "xsavec", { FXSAVE
}, 0 },
8334 /* MOD_0FC7_REG_5 */
8335 { "xsaves", { FXSAVE
}, 0 },
8338 /* MOD_0FC7_REG_6 */
8339 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
8340 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
8343 /* MOD_0FC7_REG_7 */
8344 { "vmptrst", { Mq
}, 0 },
8345 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
8350 { "pmovmskb", { Gdq
, MS
}, 0 },
8353 /* MOD_0FE7_PREFIX_2 */
8354 { "movntdq", { Mx
, XM
}, 0 },
8357 /* MOD_0FF0_PREFIX_3 */
8358 { "lddqu", { XM
, M
}, 0 },
8362 { "movntdqa", { XM
, Mx
}, PREFIX_DATA
},
8365 /* MOD_0F38DC_PREFIX_1 */
8366 { "aesenc128kl", { XM
, M
}, 0 },
8367 { "loadiwkey", { XM
, EXx
}, 0 },
8370 /* MOD_0F38DD_PREFIX_1 */
8371 { "aesdec128kl", { XM
, M
}, 0 },
8374 /* MOD_0F38DE_PREFIX_1 */
8375 { "aesenc256kl", { XM
, M
}, 0 },
8378 /* MOD_0F38DF_PREFIX_1 */
8379 { "aesdec256kl", { XM
, M
}, 0 },
8383 { "wrussK", { M
, Gdq
}, PREFIX_DATA
},
8386 /* MOD_0F38F6_PREFIX_0 */
8387 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
8390 /* MOD_0F38F8_PREFIX_1 */
8391 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
8394 /* MOD_0F38F8_PREFIX_2 */
8395 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
8398 /* MOD_0F38F8_PREFIX_3 */
8399 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
8403 { "movdiri", { Edq
, Gdq
}, PREFIX_OPCODE
},
8406 /* MOD_0F38FA_PREFIX_1 */
8408 { "encodekey128", { Gd
, Ed
}, 0 },
8411 /* MOD_0F38FB_PREFIX_1 */
8413 { "encodekey256", { Gd
, Ed
}, 0 },
8416 /* MOD_0F3A0F_PREFIX_1 */
8418 { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3
) },
8422 { "bound{S|}", { Gv
, Ma
}, 0 },
8423 { EVEX_TABLE (EVEX_0F
) },
8427 { "lesS", { Gv
, Mp
}, 0 },
8428 { VEX_C4_TABLE (VEX_0F
) },
8432 { "ldsS", { Gv
, Mp
}, 0 },
8433 { VEX_C5_TABLE (VEX_0F
) },
8436 /* MOD_VEX_0F12_PREFIX_0 */
8437 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
8438 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
8441 /* MOD_VEX_0F12_PREFIX_2 */
8442 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0
) },
8446 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
8449 /* MOD_VEX_0F16_PREFIX_0 */
8450 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
8451 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
8454 /* MOD_VEX_0F16_PREFIX_2 */
8455 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0
) },
8459 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
8463 { "vmovntpX", { Mx
, XM
}, PREFIX_OPCODE
},
8466 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
8468 { "kandw", { MaskG
, MaskVex
, MaskE
}, 0 },
8471 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
8473 { "kandq", { MaskG
, MaskVex
, MaskE
}, 0 },
8476 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
8478 { "kandb", { MaskG
, MaskVex
, MaskE
}, 0 },
8481 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
8483 { "kandd", { MaskG
, MaskVex
, MaskE
}, 0 },
8486 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
8488 { "kandnw", { MaskG
, MaskVex
, MaskE
}, 0 },
8491 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
8493 { "kandnq", { MaskG
, MaskVex
, MaskE
}, 0 },
8496 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
8498 { "kandnb", { MaskG
, MaskVex
, MaskE
}, 0 },
8501 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
8503 { "kandnd", { MaskG
, MaskVex
, MaskE
}, 0 },
8506 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
8508 { "knotw", { MaskG
, MaskE
}, 0 },
8511 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
8513 { "knotq", { MaskG
, MaskE
}, 0 },
8516 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
8518 { "knotb", { MaskG
, MaskE
}, 0 },
8521 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
8523 { "knotd", { MaskG
, MaskE
}, 0 },
8526 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
8528 { "korw", { MaskG
, MaskVex
, MaskE
}, 0 },
8531 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
8533 { "korq", { MaskG
, MaskVex
, MaskE
}, 0 },
8536 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
8538 { "korb", { MaskG
, MaskVex
, MaskE
}, 0 },
8541 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
8543 { "kord", { MaskG
, MaskVex
, MaskE
}, 0 },
8546 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
8548 { "kxnorw", { MaskG
, MaskVex
, MaskE
}, 0 },
8551 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
8553 { "kxnorq", { MaskG
, MaskVex
, MaskE
}, 0 },
8556 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
8558 { "kxnorb", { MaskG
, MaskVex
, MaskE
}, 0 },
8561 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
8563 { "kxnord", { MaskG
, MaskVex
, MaskE
}, 0 },
8566 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
8568 { "kxorw", { MaskG
, MaskVex
, MaskE
}, 0 },
8571 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
8573 { "kxorq", { MaskG
, MaskVex
, MaskE
}, 0 },
8576 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
8578 { "kxorb", { MaskG
, MaskVex
, MaskE
}, 0 },
8581 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
8583 { "kxord", { MaskG
, MaskVex
, MaskE
}, 0 },
8586 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
8588 { "kaddw", { MaskG
, MaskVex
, MaskE
}, 0 },
8591 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
8593 { "kaddq", { MaskG
, MaskVex
, MaskE
}, 0 },
8596 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
8598 { "kaddb", { MaskG
, MaskVex
, MaskE
}, 0 },
8601 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
8603 { "kaddd", { MaskG
, MaskVex
, MaskE
}, 0 },
8606 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
8608 { "kunpckwd", { MaskG
, MaskVex
, MaskE
}, 0 },
8611 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
8613 { "kunpckdq", { MaskG
, MaskVex
, MaskE
}, 0 },
8616 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
8618 { "kunpckbw", { MaskG
, MaskVex
, MaskE
}, 0 },
8623 { "vmovmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
8626 /* MOD_VEX_0F71_REG_2 */
8628 { "vpsrlw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8631 /* MOD_VEX_0F71_REG_4 */
8633 { "vpsraw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8636 /* MOD_VEX_0F71_REG_6 */
8638 { "vpsllw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8641 /* MOD_VEX_0F72_REG_2 */
8643 { "vpsrld", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8646 /* MOD_VEX_0F72_REG_4 */
8648 { "vpsrad", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8651 /* MOD_VEX_0F72_REG_6 */
8653 { "vpslld", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8656 /* MOD_VEX_0F73_REG_2 */
8658 { "vpsrlq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8661 /* MOD_VEX_0F73_REG_3 */
8663 { "vpsrldq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8666 /* MOD_VEX_0F73_REG_6 */
8668 { "vpsllq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8671 /* MOD_VEX_0F73_REG_7 */
8673 { "vpslldq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8676 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8677 { "kmovw", { Ew
, MaskG
}, 0 },
8681 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8682 { "kmovq", { Eq
, MaskG
}, 0 },
8686 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8687 { "kmovb", { Eb
, MaskG
}, 0 },
8691 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8692 { "kmovd", { Ed
, MaskG
}, 0 },
8696 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
8698 { "kmovw", { MaskG
, Edq
}, 0 },
8701 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
8703 { "kmovb", { MaskG
, Edq
}, 0 },
8706 /* MOD_VEX_0F92_P_3_LEN_0 */
8708 { "kmovK", { MaskG
, Edq
}, 0 },
8711 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
8713 { "kmovw", { Gdq
, MaskE
}, 0 },
8716 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
8718 { "kmovb", { Gdq
, MaskE
}, 0 },
8721 /* MOD_VEX_0F93_P_3_LEN_0 */
8723 { "kmovK", { Gdq
, MaskE
}, 0 },
8726 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
8728 { "kortestw", { MaskG
, MaskE
}, 0 },
8731 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
8733 { "kortestq", { MaskG
, MaskE
}, 0 },
8736 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
8738 { "kortestb", { MaskG
, MaskE
}, 0 },
8741 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
8743 { "kortestd", { MaskG
, MaskE
}, 0 },
8746 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
8748 { "ktestw", { MaskG
, MaskE
}, 0 },
8751 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
8753 { "ktestq", { MaskG
, MaskE
}, 0 },
8756 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
8758 { "ktestb", { MaskG
, MaskE
}, 0 },
8761 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
8763 { "ktestd", { MaskG
, MaskE
}, 0 },
8766 /* MOD_VEX_0FAE_REG_2 */
8767 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
8770 /* MOD_VEX_0FAE_REG_3 */
8771 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
8776 { "vpmovmskb", { Gdq
, XS
}, PREFIX_DATA
},
8780 { "vmovntdq", { Mx
, XM
}, PREFIX_DATA
},
8783 /* MOD_VEX_0FF0_PREFIX_3 */
8784 { "vlddqu", { XM
, M
}, 0 },
8787 /* MOD_VEX_0F381A */
8788 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0
) },
8791 /* MOD_VEX_0F382A */
8792 { "vmovntdqa", { XM
, Mx
}, PREFIX_DATA
},
8795 /* MOD_VEX_0F382C */
8796 { VEX_W_TABLE (VEX_W_0F382C_M_0
) },
8799 /* MOD_VEX_0F382D */
8800 { VEX_W_TABLE (VEX_W_0F382D_M_0
) },
8803 /* MOD_VEX_0F382E */
8804 { VEX_W_TABLE (VEX_W_0F382E_M_0
) },
8807 /* MOD_VEX_0F382F */
8808 { VEX_W_TABLE (VEX_W_0F382F_M_0
) },
8811 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8812 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
) },
8813 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1
) },
8816 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8817 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
) },
8820 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8822 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
) },
8825 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8826 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
) },
8829 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8830 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
) },
8833 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8834 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
) },
8837 /* MOD_VEX_0F385A */
8838 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0
) },
8841 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8843 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
) },
8846 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8848 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
) },
8851 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8853 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
) },
8856 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8858 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
) },
8861 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8863 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
) },
8866 /* MOD_VEX_0F388C */
8867 { "vpmaskmov%DQ", { XM
, Vex
, Mx
}, PREFIX_DATA
},
8870 /* MOD_VEX_0F388E */
8871 { "vpmaskmov%DQ", { Mx
, Vex
, XM
}, PREFIX_DATA
},
8874 /* MOD_VEX_0F3A30_L_0 */
8876 { "kshiftr%BW", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8879 /* MOD_VEX_0F3A31_L_0 */
8881 { "kshiftr%DQ", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8884 /* MOD_VEX_0F3A32_L_0 */
8886 { "kshiftl%BW", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8889 /* MOD_VEX_0F3A33_L_0 */
8891 { "kshiftl%DQ", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8894 /* MOD_VEX_0FXOP_09_12 */
8896 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1
) },
8899 #include "i386-dis-evex-mod.h"
8902 static const struct dis386 rm_table
[][8] = {
8905 { "xabort", { Skip_MODRM
, Ib
}, 0 },
8909 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
8913 { "enclv", { Skip_MODRM
}, 0 },
8914 { "vmcall", { Skip_MODRM
}, 0 },
8915 { "vmlaunch", { Skip_MODRM
}, 0 },
8916 { "vmresume", { Skip_MODRM
}, 0 },
8917 { "vmxoff", { Skip_MODRM
}, 0 },
8918 { "pconfig", { Skip_MODRM
}, 0 },
8922 { "monitor", { { OP_Monitor
, 0 } }, 0 },
8923 { "mwait", { { OP_Mwait
, 0 } }, 0 },
8924 { "clac", { Skip_MODRM
}, 0 },
8925 { "stac", { Skip_MODRM
}, 0 },
8926 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4
) },
8927 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5
) },
8928 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6
) },
8929 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7
) },
8933 { "xgetbv", { Skip_MODRM
}, 0 },
8934 { "xsetbv", { Skip_MODRM
}, 0 },
8937 { "vmfunc", { Skip_MODRM
}, 0 },
8938 { "xend", { Skip_MODRM
}, 0 },
8939 { "xtest", { Skip_MODRM
}, 0 },
8940 { "enclu", { Skip_MODRM
}, 0 },
8944 { "vmrun", { Skip_MODRM
}, 0 },
8945 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
8946 { "vmload", { Skip_MODRM
}, 0 },
8947 { "vmsave", { Skip_MODRM
}, 0 },
8948 { "stgi", { Skip_MODRM
}, 0 },
8949 { "clgi", { Skip_MODRM
}, 0 },
8950 { "skinit", { Skip_MODRM
}, 0 },
8951 { "invlpga", { Skip_MODRM
}, 0 },
8954 /* RM_0F01_REG_5_MOD_3 */
8955 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
8956 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1
) },
8957 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
8959 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4
) },
8960 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5
) },
8961 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6
) },
8962 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7
) },
8965 /* RM_0F01_REG_7_MOD_3 */
8966 { "swapgs", { Skip_MODRM
}, 0 },
8967 { "rdtscp", { Skip_MODRM
}, 0 },
8968 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
8969 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, PREFIX_OPCODE
},
8970 { "clzero", { Skip_MODRM
}, 0 },
8971 { "rdpru", { Skip_MODRM
}, 0 },
8974 /* RM_0F1E_P_1_MOD_3_REG_7 */
8975 { "nopQ", { Ev
}, 0 },
8976 { "nopQ", { Ev
}, 0 },
8977 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
8978 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
8979 { "nopQ", { Ev
}, 0 },
8980 { "nopQ", { Ev
}, 0 },
8981 { "nopQ", { Ev
}, 0 },
8982 { "nopQ", { Ev
}, 0 },
8985 /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8986 { "hreset", { Skip_MODRM
, Ib
}, 0 },
8989 /* RM_0FAE_REG_6_MOD_3 */
8990 { "mfence", { Skip_MODRM
}, 0 },
8993 /* RM_0FAE_REG_7_MOD_3 */
8994 { "sfence", { Skip_MODRM
}, 0 },
8998 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8999 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
) },
9003 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9005 /* We use the high bit to indicate different name for the same
9007 #define REP_PREFIX (0xf3 | 0x100)
9008 #define XACQUIRE_PREFIX (0xf2 | 0x200)
9009 #define XRELEASE_PREFIX (0xf3 | 0x400)
9010 #define BND_PREFIX (0xf2 | 0x400)
9011 #define NOTRACK_PREFIX (0x3e | 0x100)
9013 /* Remember if the current op is a jump instruction. */
9014 static bfd_boolean op_is_jump
= FALSE
;
9019 int newrex
, i
, length
;
9024 last_lock_prefix
= -1;
9025 last_repz_prefix
= -1;
9026 last_repnz_prefix
= -1;
9027 last_data_prefix
= -1;
9028 last_addr_prefix
= -1;
9029 last_rex_prefix
= -1;
9030 last_seg_prefix
= -1;
9032 active_seg_prefix
= 0;
9033 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
9034 all_prefixes
[i
] = 0;
9037 /* The maximum instruction length is 15bytes. */
9038 while (length
< MAX_CODE_LENGTH
- 1)
9040 FETCH_DATA (the_info
, codep
+ 1);
9044 /* REX prefixes family. */
9061 if (address_mode
== mode_64bit
)
9065 last_rex_prefix
= i
;
9068 prefixes
|= PREFIX_REPZ
;
9069 last_repz_prefix
= i
;
9072 prefixes
|= PREFIX_REPNZ
;
9073 last_repnz_prefix
= i
;
9076 prefixes
|= PREFIX_LOCK
;
9077 last_lock_prefix
= i
;
9080 prefixes
|= PREFIX_CS
;
9081 last_seg_prefix
= i
;
9082 active_seg_prefix
= PREFIX_CS
;
9085 prefixes
|= PREFIX_SS
;
9086 last_seg_prefix
= i
;
9087 active_seg_prefix
= PREFIX_SS
;
9090 prefixes
|= PREFIX_DS
;
9091 last_seg_prefix
= i
;
9092 active_seg_prefix
= PREFIX_DS
;
9095 prefixes
|= PREFIX_ES
;
9096 last_seg_prefix
= i
;
9097 active_seg_prefix
= PREFIX_ES
;
9100 prefixes
|= PREFIX_FS
;
9101 last_seg_prefix
= i
;
9102 active_seg_prefix
= PREFIX_FS
;
9105 prefixes
|= PREFIX_GS
;
9106 last_seg_prefix
= i
;
9107 active_seg_prefix
= PREFIX_GS
;
9110 prefixes
|= PREFIX_DATA
;
9111 last_data_prefix
= i
;
9114 prefixes
|= PREFIX_ADDR
;
9115 last_addr_prefix
= i
;
9118 /* fwait is really an instruction. If there are prefixes
9119 before the fwait, they belong to the fwait, *not* to the
9120 following instruction. */
9122 if (prefixes
|| rex
)
9124 prefixes
|= PREFIX_FWAIT
;
9126 /* This ensures that the previous REX prefixes are noticed
9127 as unused prefixes, as in the return case below. */
9131 prefixes
= PREFIX_FWAIT
;
9136 /* Rex is ignored when followed by another prefix. */
9142 if (*codep
!= FWAIT_OPCODE
)
9143 all_prefixes
[i
++] = *codep
;
9151 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9155 prefix_name (int pref
, int sizeflag
)
9157 static const char *rexes
[16] =
9162 "rex.XB", /* 0x43 */
9164 "rex.RB", /* 0x45 */
9165 "rex.RX", /* 0x46 */
9166 "rex.RXB", /* 0x47 */
9168 "rex.WB", /* 0x49 */
9169 "rex.WX", /* 0x4a */
9170 "rex.WXB", /* 0x4b */
9171 "rex.WR", /* 0x4c */
9172 "rex.WRB", /* 0x4d */
9173 "rex.WRX", /* 0x4e */
9174 "rex.WRXB", /* 0x4f */
9179 /* REX prefixes family. */
9196 return rexes
[pref
- 0x40];
9216 return (sizeflag
& DFLAG
) ? "data16" : "data32";
9218 if (address_mode
== mode_64bit
)
9219 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
9221 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
9226 case XACQUIRE_PREFIX
:
9228 case XRELEASE_PREFIX
:
9232 case NOTRACK_PREFIX
:
9239 static char op_out
[MAX_OPERANDS
][100];
9240 static int op_ad
, op_index
[MAX_OPERANDS
];
9241 static int two_source_ops
;
9242 static bfd_vma op_address
[MAX_OPERANDS
];
9243 static bfd_vma op_riprel
[MAX_OPERANDS
];
9244 static bfd_vma start_pc
;
9247 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9248 * (see topic "Redundant prefixes" in the "Differences from 8086"
9249 * section of the "Virtual 8086 Mode" chapter.)
9250 * 'pc' should be the address of this instruction, it will
9251 * be used to print the target address if this is a relative jump or call
9252 * The function returns the length of this instruction in bytes.
9255 static char intel_syntax
;
9256 static char intel_mnemonic
= !SYSV386_COMPAT
;
9257 static char open_char
;
9258 static char close_char
;
9259 static char separator_char
;
9260 static char scale_char
;
9268 static enum x86_64_isa isa64
;
9270 /* Here for backwards compatibility. When gdb stops using
9271 print_insn_i386_att and print_insn_i386_intel these functions can
9272 disappear, and print_insn_i386 be merged into print_insn. */
9274 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
9278 return print_insn (pc
, info
);
9282 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
9286 return print_insn (pc
, info
);
9290 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
9294 return print_insn (pc
, info
);
9298 print_i386_disassembler_options (FILE *stream
)
9300 fprintf (stream
, _("\n\
9301 The following i386/x86-64 specific disassembler options are supported for use\n\
9302 with the -M switch (multiple options should be separated by commas):\n"));
9304 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
9305 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
9306 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
9307 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
9308 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
9309 fprintf (stream
, _(" att-mnemonic\n"
9310 " Display instruction in AT&T mnemonic\n"));
9311 fprintf (stream
, _(" intel-mnemonic\n"
9312 " Display instruction in Intel mnemonic\n"));
9313 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
9314 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
9315 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
9316 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
9317 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
9318 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9319 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
9320 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
9324 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
9326 /* Get a pointer to struct dis386 with a valid name. */
9328 static const struct dis386
*
9329 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
9331 int vindex
, vex_table_index
;
9333 if (dp
->name
!= NULL
)
9336 switch (dp
->op
[0].bytemode
)
9339 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
9343 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
9344 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
9348 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
9351 case USE_PREFIX_TABLE
:
9354 /* The prefix in VEX is implicit. */
9360 case REPE_PREFIX_OPCODE
:
9363 case DATA_PREFIX_OPCODE
:
9366 case REPNE_PREFIX_OPCODE
:
9376 int last_prefix
= -1;
9379 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9380 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9382 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
9384 if (last_repz_prefix
> last_repnz_prefix
)
9387 prefix
= PREFIX_REPZ
;
9388 last_prefix
= last_repz_prefix
;
9393 prefix
= PREFIX_REPNZ
;
9394 last_prefix
= last_repnz_prefix
;
9397 /* Check if prefix should be ignored. */
9398 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
9399 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
9404 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
9407 prefix
= PREFIX_DATA
;
9408 last_prefix
= last_data_prefix
;
9413 used_prefixes
|= prefix
;
9414 all_prefixes
[last_prefix
] = 0;
9417 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
9420 case USE_X86_64_TABLE
:
9421 vindex
= address_mode
== mode_64bit
? 1 : 0;
9422 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
9425 case USE_3BYTE_TABLE
:
9426 FETCH_DATA (info
, codep
+ 2);
9428 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
9430 modrm
.mod
= (*codep
>> 6) & 3;
9431 modrm
.reg
= (*codep
>> 3) & 7;
9432 modrm
.rm
= *codep
& 7;
9435 case USE_VEX_LEN_TABLE
:
9452 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
9455 case USE_EVEX_LEN_TABLE
:
9475 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
9478 case USE_XOP_8F_TABLE
:
9479 FETCH_DATA (info
, codep
+ 3);
9480 rex
= ~(*codep
>> 5) & 0x7;
9482 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9483 switch ((*codep
& 0x1f))
9489 vex_table_index
= XOP_08
;
9492 vex_table_index
= XOP_09
;
9495 vex_table_index
= XOP_0A
;
9499 vex
.w
= *codep
& 0x80;
9500 if (vex
.w
&& address_mode
== mode_64bit
)
9503 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9504 if (address_mode
!= mode_64bit
)
9506 /* In 16/32-bit mode REX_B is silently ignored. */
9510 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9511 switch ((*codep
& 0x3))
9516 vex
.prefix
= DATA_PREFIX_OPCODE
;
9519 vex
.prefix
= REPE_PREFIX_OPCODE
;
9522 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9528 dp
= &xop_table
[vex_table_index
][vindex
];
9531 FETCH_DATA (info
, codep
+ 1);
9532 modrm
.mod
= (*codep
>> 6) & 3;
9533 modrm
.reg
= (*codep
>> 3) & 7;
9534 modrm
.rm
= *codep
& 7;
9536 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9537 having to decode the bits for every otherwise valid encoding. */
9542 case USE_VEX_C4_TABLE
:
9544 FETCH_DATA (info
, codep
+ 3);
9545 rex
= ~(*codep
>> 5) & 0x7;
9546 switch ((*codep
& 0x1f))
9552 vex_table_index
= VEX_0F
;
9555 vex_table_index
= VEX_0F38
;
9558 vex_table_index
= VEX_0F3A
;
9562 vex
.w
= *codep
& 0x80;
9563 if (address_mode
== mode_64bit
)
9570 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9571 is ignored, other REX bits are 0 and the highest bit in
9572 VEX.vvvv is also ignored (but we mustn't clear it here). */
9575 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9576 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9577 switch ((*codep
& 0x3))
9582 vex
.prefix
= DATA_PREFIX_OPCODE
;
9585 vex
.prefix
= REPE_PREFIX_OPCODE
;
9588 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9594 dp
= &vex_table
[vex_table_index
][vindex
];
9596 /* There is no MODRM byte for VEX0F 77. */
9597 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
9599 FETCH_DATA (info
, codep
+ 1);
9600 modrm
.mod
= (*codep
>> 6) & 3;
9601 modrm
.reg
= (*codep
>> 3) & 7;
9602 modrm
.rm
= *codep
& 7;
9606 case USE_VEX_C5_TABLE
:
9608 FETCH_DATA (info
, codep
+ 2);
9609 rex
= (*codep
& 0x80) ? 0 : REX_R
;
9611 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9613 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9614 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9615 switch ((*codep
& 0x3))
9620 vex
.prefix
= DATA_PREFIX_OPCODE
;
9623 vex
.prefix
= REPE_PREFIX_OPCODE
;
9626 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9632 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
9634 /* There is no MODRM byte for VEX 77. */
9637 FETCH_DATA (info
, codep
+ 1);
9638 modrm
.mod
= (*codep
>> 6) & 3;
9639 modrm
.reg
= (*codep
>> 3) & 7;
9640 modrm
.rm
= *codep
& 7;
9644 case USE_VEX_W_TABLE
:
9648 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
9651 case USE_EVEX_TABLE
:
9655 FETCH_DATA (info
, codep
+ 4);
9656 /* The first byte after 0x62. */
9657 rex
= ~(*codep
>> 5) & 0x7;
9658 vex
.r
= *codep
& 0x10;
9659 switch ((*codep
& 0xf))
9664 vex_table_index
= EVEX_0F
;
9667 vex_table_index
= EVEX_0F38
;
9670 vex_table_index
= EVEX_0F3A
;
9674 /* The second byte after 0x62. */
9676 vex
.w
= *codep
& 0x80;
9677 if (vex
.w
&& address_mode
== mode_64bit
)
9680 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9683 if (!(*codep
& 0x4))
9686 switch ((*codep
& 0x3))
9691 vex
.prefix
= DATA_PREFIX_OPCODE
;
9694 vex
.prefix
= REPE_PREFIX_OPCODE
;
9697 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9701 /* The third byte after 0x62. */
9704 /* Remember the static rounding bits. */
9705 vex
.ll
= (*codep
>> 5) & 3;
9706 vex
.b
= (*codep
& 0x10) != 0;
9708 vex
.v
= *codep
& 0x8;
9709 vex
.mask_register_specifier
= *codep
& 0x7;
9710 vex
.zeroing
= *codep
& 0x80;
9712 if (address_mode
!= mode_64bit
)
9714 /* In 16/32-bit mode silently ignore following bits. */
9723 dp
= &evex_table
[vex_table_index
][vindex
];
9725 FETCH_DATA (info
, codep
+ 1);
9726 modrm
.mod
= (*codep
>> 6) & 3;
9727 modrm
.reg
= (*codep
>> 3) & 7;
9728 modrm
.rm
= *codep
& 7;
9730 /* Set vector length. */
9731 if (modrm
.mod
== 3 && vex
.b
)
9760 if (dp
->name
!= NULL
)
9763 return get_valid_dis386 (dp
, info
);
9767 get_sib (disassemble_info
*info
, int sizeflag
)
9769 /* If modrm.mod == 3, operand must be register. */
9771 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
9775 FETCH_DATA (info
, codep
+ 2);
9776 sib
.index
= (codep
[1] >> 3) & 7;
9777 sib
.scale
= (codep
[1] >> 6) & 3;
9778 sib
.base
= codep
[1] & 7;
9783 print_insn (bfd_vma pc
, disassemble_info
*info
)
9785 const struct dis386
*dp
;
9787 char *op_txt
[MAX_OPERANDS
];
9789 int sizeflag
, orig_sizeflag
;
9791 struct dis_private priv
;
9794 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
9795 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
9796 address_mode
= mode_32bit
;
9797 else if (info
->mach
== bfd_mach_i386_i8086
)
9799 address_mode
= mode_16bit
;
9800 priv
.orig_sizeflag
= 0;
9803 address_mode
= mode_64bit
;
9805 if (intel_syntax
== (char) -1)
9806 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
9808 for (p
= info
->disassembler_options
; p
!= NULL
; )
9810 if (CONST_STRNEQ (p
, "amd64"))
9812 else if (CONST_STRNEQ (p
, "intel64"))
9814 else if (CONST_STRNEQ (p
, "x86-64"))
9816 address_mode
= mode_64bit
;
9817 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
9819 else if (CONST_STRNEQ (p
, "i386"))
9821 address_mode
= mode_32bit
;
9822 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
9824 else if (CONST_STRNEQ (p
, "i8086"))
9826 address_mode
= mode_16bit
;
9827 priv
.orig_sizeflag
&= ~(AFLAG
| DFLAG
);
9829 else if (CONST_STRNEQ (p
, "intel"))
9832 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
9835 else if (CONST_STRNEQ (p
, "att"))
9838 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
9841 else if (CONST_STRNEQ (p
, "addr"))
9843 if (address_mode
== mode_64bit
)
9845 if (p
[4] == '3' && p
[5] == '2')
9846 priv
.orig_sizeflag
&= ~AFLAG
;
9847 else if (p
[4] == '6' && p
[5] == '4')
9848 priv
.orig_sizeflag
|= AFLAG
;
9852 if (p
[4] == '1' && p
[5] == '6')
9853 priv
.orig_sizeflag
&= ~AFLAG
;
9854 else if (p
[4] == '3' && p
[5] == '2')
9855 priv
.orig_sizeflag
|= AFLAG
;
9858 else if (CONST_STRNEQ (p
, "data"))
9860 if (p
[4] == '1' && p
[5] == '6')
9861 priv
.orig_sizeflag
&= ~DFLAG
;
9862 else if (p
[4] == '3' && p
[5] == '2')
9863 priv
.orig_sizeflag
|= DFLAG
;
9865 else if (CONST_STRNEQ (p
, "suffix"))
9866 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
9868 p
= strchr (p
, ',');
9873 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
9875 (*info
->fprintf_func
) (info
->stream
,
9876 _("64-bit address is disabled"));
9882 names64
= intel_names64
;
9883 names32
= intel_names32
;
9884 names16
= intel_names16
;
9885 names8
= intel_names8
;
9886 names8rex
= intel_names8rex
;
9887 names_seg
= intel_names_seg
;
9888 names_mm
= intel_names_mm
;
9889 names_bnd
= intel_names_bnd
;
9890 names_xmm
= intel_names_xmm
;
9891 names_ymm
= intel_names_ymm
;
9892 names_zmm
= intel_names_zmm
;
9893 names_tmm
= intel_names_tmm
;
9894 index64
= intel_index64
;
9895 index32
= intel_index32
;
9896 names_mask
= intel_names_mask
;
9897 index16
= intel_index16
;
9900 separator_char
= '+';
9905 names64
= att_names64
;
9906 names32
= att_names32
;
9907 names16
= att_names16
;
9908 names8
= att_names8
;
9909 names8rex
= att_names8rex
;
9910 names_seg
= att_names_seg
;
9911 names_mm
= att_names_mm
;
9912 names_bnd
= att_names_bnd
;
9913 names_xmm
= att_names_xmm
;
9914 names_ymm
= att_names_ymm
;
9915 names_zmm
= att_names_zmm
;
9916 names_tmm
= att_names_tmm
;
9917 index64
= att_index64
;
9918 index32
= att_index32
;
9919 names_mask
= att_names_mask
;
9920 index16
= att_index16
;
9923 separator_char
= ',';
9927 /* The output looks better if we put 7 bytes on a line, since that
9928 puts most long word instructions on a single line. Use 8 bytes
9930 if ((info
->mach
& bfd_mach_l1om
) != 0)
9931 info
->bytes_per_line
= 8;
9933 info
->bytes_per_line
= 7;
9935 info
->private_data
= &priv
;
9936 priv
.max_fetched
= priv
.the_buffer
;
9937 priv
.insn_start
= pc
;
9940 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9948 start_codep
= priv
.the_buffer
;
9949 codep
= priv
.the_buffer
;
9951 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
9955 /* Getting here means we tried for data but didn't get it. That
9956 means we have an incomplete instruction of some sort. Just
9957 print the first byte as a prefix or a .byte pseudo-op. */
9958 if (codep
> priv
.the_buffer
)
9960 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
9962 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
9965 /* Just print the first byte as a .byte instruction. */
9966 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
9967 (unsigned int) priv
.the_buffer
[0]);
9977 sizeflag
= priv
.orig_sizeflag
;
9979 if (!ckprefix () || rex_used
)
9981 /* Too many prefixes or unused REX prefixes. */
9983 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
9985 (*info
->fprintf_func
) (info
->stream
, "%s%s",
9987 prefix_name (all_prefixes
[i
], sizeflag
));
9993 FETCH_DATA (info
, codep
+ 1);
9994 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
9996 if (((prefixes
& PREFIX_FWAIT
)
9997 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
9999 /* Handle prefixes before fwait. */
10000 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
10002 (*info
->fprintf_func
) (info
->stream
, "%s ",
10003 prefix_name (all_prefixes
[i
], sizeflag
));
10004 (*info
->fprintf_func
) (info
->stream
, "fwait");
10008 if (*codep
== 0x0f)
10010 unsigned char threebyte
;
10013 FETCH_DATA (info
, codep
+ 1);
10014 threebyte
= *codep
;
10015 dp
= &dis386_twobyte
[threebyte
];
10016 need_modrm
= twobyte_has_modrm
[threebyte
];
10021 dp
= &dis386
[*codep
];
10022 need_modrm
= onebyte_has_modrm
[*codep
];
10026 /* Save sizeflag for printing the extra prefixes later before updating
10027 it for mnemonic and operand processing. The prefix names depend
10028 only on the address mode. */
10029 orig_sizeflag
= sizeflag
;
10030 if (prefixes
& PREFIX_ADDR
)
10032 if ((prefixes
& PREFIX_DATA
))
10038 FETCH_DATA (info
, codep
+ 1);
10039 modrm
.mod
= (*codep
>> 6) & 3;
10040 modrm
.reg
= (*codep
>> 3) & 7;
10041 modrm
.rm
= *codep
& 7;
10044 memset (&modrm
, 0, sizeof (modrm
));
10047 memset (&vex
, 0, sizeof (vex
));
10049 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
10051 get_sib (info
, sizeflag
);
10052 dofloat (sizeflag
);
10056 dp
= get_valid_dis386 (dp
, info
);
10057 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
10059 get_sib (info
, sizeflag
);
10060 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
10063 op_ad
= MAX_OPERANDS
- 1 - i
;
10065 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
10066 /* For EVEX instruction after the last operand masking
10067 should be printed. */
10068 if (i
== 0 && vex
.evex
)
10070 /* Don't print {%k0}. */
10071 if (vex
.mask_register_specifier
)
10074 oappend (names_mask
[vex
.mask_register_specifier
]);
10084 /* Clear instruction information. */
10087 the_info
->insn_info_valid
= 0;
10088 the_info
->branch_delay_insns
= 0;
10089 the_info
->data_size
= 0;
10090 the_info
->insn_type
= dis_noninsn
;
10091 the_info
->target
= 0;
10092 the_info
->target2
= 0;
10095 /* Reset jump operation indicator. */
10096 op_is_jump
= FALSE
;
10099 int jump_detection
= 0;
10101 /* Extract flags. */
10102 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
10104 if ((dp
->op
[i
].rtn
== OP_J
)
10105 || (dp
->op
[i
].rtn
== OP_indirE
))
10106 jump_detection
|= 1;
10107 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
10108 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
10109 jump_detection
|= 2;
10110 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
10111 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
10112 jump_detection
|= 4;
10115 /* Determine if this is a jump or branch. */
10116 if ((jump_detection
& 0x3) == 0x3)
10119 if (jump_detection
& 0x4)
10120 the_info
->insn_type
= dis_condbranch
;
10122 the_info
->insn_type
=
10123 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
10124 ? dis_jsr
: dis_branch
;
10128 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
10129 are all 0s in inverted form. */
10130 if (need_vex
&& vex
.register_specifier
!= 0)
10132 (*info
->fprintf_func
) (info
->stream
, "(bad)");
10133 return end_codep
- priv
.the_buffer
;
10136 switch (dp
->prefix_requirement
)
10139 /* If only the data prefix is marked as mandatory, its absence renders
10140 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
10141 if (need_vex
? !vex
.prefix
: !(prefixes
& PREFIX_DATA
))
10143 (*info
->fprintf_func
) (info
->stream
, "(bad)");
10144 return end_codep
- priv
.the_buffer
;
10146 used_prefixes
|= PREFIX_DATA
;
10147 /* Fall through. */
10148 case PREFIX_OPCODE
:
10149 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
10150 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
10151 used by putop and MMX/SSE operand and may be overridden by the
10152 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
10155 ? vex
.prefix
== REPE_PREFIX_OPCODE
10156 || vex
.prefix
== REPNE_PREFIX_OPCODE
10158 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
10160 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
10162 ? vex
.prefix
== DATA_PREFIX_OPCODE
10164 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
10166 && (used_prefixes
& PREFIX_DATA
) == 0))
10167 || (vex
.evex
&& dp
->prefix_requirement
!= PREFIX_DATA
10168 && !vex
.w
!= !(used_prefixes
& PREFIX_DATA
)))
10170 (*info
->fprintf_func
) (info
->stream
, "(bad)");
10171 return end_codep
- priv
.the_buffer
;
10176 /* Check if the REX prefix is used. */
10177 if ((rex
^ rex_used
) == 0 && !need_vex
&& last_rex_prefix
>= 0)
10178 all_prefixes
[last_rex_prefix
] = 0;
10180 /* Check if the SEG prefix is used. */
10181 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
10182 | PREFIX_FS
| PREFIX_GS
)) != 0
10183 && (used_prefixes
& active_seg_prefix
) != 0)
10184 all_prefixes
[last_seg_prefix
] = 0;
10186 /* Check if the ADDR prefix is used. */
10187 if ((prefixes
& PREFIX_ADDR
) != 0
10188 && (used_prefixes
& PREFIX_ADDR
) != 0)
10189 all_prefixes
[last_addr_prefix
] = 0;
10191 /* Check if the DATA prefix is used. */
10192 if ((prefixes
& PREFIX_DATA
) != 0
10193 && (used_prefixes
& PREFIX_DATA
) != 0
10195 all_prefixes
[last_data_prefix
] = 0;
10197 /* Print the extra prefixes. */
10199 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
10200 if (all_prefixes
[i
])
10203 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
10206 prefix_length
+= strlen (name
) + 1;
10207 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
10210 /* Check maximum code length. */
10211 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
10213 (*info
->fprintf_func
) (info
->stream
, "(bad)");
10214 return MAX_CODE_LENGTH
;
10217 obufp
= mnemonicendp
;
10218 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
10221 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
10223 /* The enter and bound instructions are printed with operands in the same
10224 order as the intel book; everything else is printed in reverse order. */
10225 if (intel_syntax
|| two_source_ops
)
10229 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
10230 op_txt
[i
] = op_out
[i
];
10232 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
10233 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
10235 op_txt
[2] = op_out
[3];
10236 op_txt
[3] = op_out
[2];
10239 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
10241 op_ad
= op_index
[i
];
10242 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
10243 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
10244 riprel
= op_riprel
[i
];
10245 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
10246 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
10251 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
10252 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
10256 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
10260 (*info
->fprintf_func
) (info
->stream
, ",");
10261 if (op_index
[i
] != -1 && !op_riprel
[i
])
10263 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
10265 if (the_info
&& op_is_jump
)
10267 the_info
->insn_info_valid
= 1;
10268 the_info
->branch_delay_insns
= 0;
10269 the_info
->data_size
= 0;
10270 the_info
->target
= target
;
10271 the_info
->target2
= 0;
10273 (*info
->print_address_func
) (target
, info
);
10276 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
10280 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10281 if (op_index
[i
] != -1 && op_riprel
[i
])
10283 (*info
->fprintf_func
) (info
->stream
, " # ");
10284 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
10285 + op_address
[op_index
[i
]]), info
);
10288 return codep
- priv
.the_buffer
;
10291 static const char *float_mem
[] = {
10366 static const unsigned char float_mem_mode
[] = {
10441 #define ST { OP_ST, 0 }
10442 #define STi { OP_STi, 0 }
10444 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10445 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10446 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10447 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10448 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10449 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10450 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10451 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10452 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10454 static const struct dis386 float_reg
[][8] = {
10457 { "fadd", { ST
, STi
}, 0 },
10458 { "fmul", { ST
, STi
}, 0 },
10459 { "fcom", { STi
}, 0 },
10460 { "fcomp", { STi
}, 0 },
10461 { "fsub", { ST
, STi
}, 0 },
10462 { "fsubr", { ST
, STi
}, 0 },
10463 { "fdiv", { ST
, STi
}, 0 },
10464 { "fdivr", { ST
, STi
}, 0 },
10468 { "fld", { STi
}, 0 },
10469 { "fxch", { STi
}, 0 },
10479 { "fcmovb", { ST
, STi
}, 0 },
10480 { "fcmove", { ST
, STi
}, 0 },
10481 { "fcmovbe",{ ST
, STi
}, 0 },
10482 { "fcmovu", { ST
, STi
}, 0 },
10490 { "fcmovnb",{ ST
, STi
}, 0 },
10491 { "fcmovne",{ ST
, STi
}, 0 },
10492 { "fcmovnbe",{ ST
, STi
}, 0 },
10493 { "fcmovnu",{ ST
, STi
}, 0 },
10495 { "fucomi", { ST
, STi
}, 0 },
10496 { "fcomi", { ST
, STi
}, 0 },
10501 { "fadd", { STi
, ST
}, 0 },
10502 { "fmul", { STi
, ST
}, 0 },
10505 { "fsub{!M|r}", { STi
, ST
}, 0 },
10506 { "fsub{M|}", { STi
, ST
}, 0 },
10507 { "fdiv{!M|r}", { STi
, ST
}, 0 },
10508 { "fdiv{M|}", { STi
, ST
}, 0 },
10512 { "ffree", { STi
}, 0 },
10514 { "fst", { STi
}, 0 },
10515 { "fstp", { STi
}, 0 },
10516 { "fucom", { STi
}, 0 },
10517 { "fucomp", { STi
}, 0 },
10523 { "faddp", { STi
, ST
}, 0 },
10524 { "fmulp", { STi
, ST
}, 0 },
10527 { "fsub{!M|r}p", { STi
, ST
}, 0 },
10528 { "fsub{M|}p", { STi
, ST
}, 0 },
10529 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
10530 { "fdiv{M|}p", { STi
, ST
}, 0 },
10534 { "ffreep", { STi
}, 0 },
10539 { "fucomip", { ST
, STi
}, 0 },
10540 { "fcomip", { ST
, STi
}, 0 },
10545 static char *fgrps
[][8] = {
10548 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10553 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10558 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10563 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10568 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10573 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10578 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10583 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10584 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10589 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10594 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10599 swap_operand (void)
10601 mnemonicendp
[0] = '.';
10602 mnemonicendp
[1] = 's';
10607 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
10608 int sizeflag ATTRIBUTE_UNUSED
)
10610 /* Skip mod/rm byte. */
10616 dofloat (int sizeflag
)
10618 const struct dis386
*dp
;
10619 unsigned char floatop
;
10621 floatop
= codep
[-1];
10623 if (modrm
.mod
!= 3)
10625 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
10627 putop (float_mem
[fp_indx
], sizeflag
);
10630 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
10633 /* Skip mod/rm byte. */
10637 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
10638 if (dp
->name
== NULL
)
10640 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
10642 /* Instruction fnstsw is only one with strange arg. */
10643 if (floatop
== 0xdf && codep
[-1] == 0xe0)
10644 strcpy (op_out
[0], names16
[0]);
10648 putop (dp
->name
, sizeflag
);
10653 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
10658 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
10662 /* Like oappend (below), but S is a string starting with '%'.
10663 In Intel syntax, the '%' is elided. */
10665 oappend_maybe_intel (const char *s
)
10667 oappend (s
+ intel_syntax
);
10671 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
10673 oappend_maybe_intel ("%st");
10677 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
10679 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
10680 oappend_maybe_intel (scratchbuf
);
10683 /* Capital letters in template are macros. */
10685 putop (const char *in_template
, int sizeflag
)
10690 unsigned int l
= 0, len
= 0;
10693 for (p
= in_template
; *p
; p
++)
10697 if (l
>= sizeof (last
) || !ISUPPER (*p
))
10716 while (*++p
!= '|')
10717 if (*p
== '}' || *p
== '\0')
10723 while (*++p
!= '}')
10735 if ((need_modrm
&& modrm
.mod
!= 3)
10736 || (sizeflag
& SUFFIX_ALWAYS
))
10745 if (sizeflag
& SUFFIX_ALWAYS
)
10748 else if (l
== 1 && last
[0] == 'L')
10750 if (address_mode
== mode_64bit
10751 && !(prefixes
& PREFIX_ADDR
))
10764 if (intel_syntax
&& !alt
)
10766 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
10768 if (sizeflag
& DFLAG
)
10769 *obufp
++ = intel_syntax
? 'd' : 'l';
10771 *obufp
++ = intel_syntax
? 'w' : 's';
10772 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10776 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
10779 if (modrm
.mod
== 3)
10785 if (sizeflag
& DFLAG
)
10786 *obufp
++ = intel_syntax
? 'd' : 'l';
10789 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10795 case 'E': /* For jcxz/jecxz */
10796 if (address_mode
== mode_64bit
)
10798 if (sizeflag
& AFLAG
)
10804 if (sizeflag
& AFLAG
)
10806 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
10811 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
10813 if (sizeflag
& AFLAG
)
10814 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
10816 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
10817 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
10821 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
10823 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
10827 if (!(rex
& REX_W
))
10828 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10833 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
10834 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
10836 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
10839 if (prefixes
& PREFIX_DS
)
10855 if (intel_mnemonic
!= cond
)
10859 if ((prefixes
& PREFIX_FWAIT
) == 0)
10862 used_prefixes
|= PREFIX_FWAIT
;
10868 else if (intel_syntax
&& (sizeflag
& DFLAG
))
10872 if (!(rex
& REX_W
))
10873 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10876 if (address_mode
== mode_64bit
10877 && (isa64
== intel64
|| (rex
& REX_W
)
10878 || !(prefixes
& PREFIX_DATA
)))
10880 if (sizeflag
& SUFFIX_ALWAYS
)
10884 /* Fall through. */
10888 if ((modrm
.mod
== 3 || !cond
)
10889 && !(sizeflag
& SUFFIX_ALWAYS
))
10891 /* Fall through. */
10893 if ((!(rex
& REX_W
) && (prefixes
& PREFIX_DATA
))
10894 || ((sizeflag
& SUFFIX_ALWAYS
)
10895 && address_mode
!= mode_64bit
))
10897 *obufp
++ = (sizeflag
& DFLAG
) ?
10898 intel_syntax
? 'd' : 'l' : 'w';
10899 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10901 else if (sizeflag
& SUFFIX_ALWAYS
)
10904 else if (l
== 1 && last
[0] == 'L')
10906 if ((prefixes
& PREFIX_DATA
)
10908 || (sizeflag
& SUFFIX_ALWAYS
))
10915 if (sizeflag
& DFLAG
)
10916 *obufp
++ = intel_syntax
? 'd' : 'l';
10919 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10929 if (intel_syntax
&& !alt
)
10932 if ((need_modrm
&& modrm
.mod
!= 3)
10933 || (sizeflag
& SUFFIX_ALWAYS
))
10939 if (sizeflag
& DFLAG
)
10940 *obufp
++ = intel_syntax
? 'd' : 'l';
10943 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10947 else if (l
== 1 && last
[0] == 'D')
10948 *obufp
++ = vex
.w
? 'q' : 'd';
10949 else if (l
== 1 && last
[0] == 'L')
10951 if (cond
? modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)
10952 : address_mode
!= mode_64bit
)
10959 else if((address_mode
== mode_64bit
&& cond
)
10960 || (sizeflag
& SUFFIX_ALWAYS
))
10961 *obufp
++ = intel_syntax
? 'd' : 'l';
10970 else if (sizeflag
& DFLAG
)
10979 if (intel_syntax
&& !p
[1]
10980 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
10982 if (!(rex
& REX_W
))
10983 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10991 if (sizeflag
& SUFFIX_ALWAYS
)
10997 if (sizeflag
& DFLAG
)
11001 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11005 else if (l
== 1 && last
[0] == 'L')
11007 if (address_mode
== mode_64bit
11008 && !(prefixes
& PREFIX_ADDR
))
11023 else if (l
== 1 && last
[0] == 'L')
11038 /* operand size flag for cwtl, cbtw */
11047 else if (sizeflag
& DFLAG
)
11051 if (!(rex
& REX_W
))
11052 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11058 if (last
[0] == 'X')
11059 *obufp
++ = vex
.w
? 'd': 's';
11060 else if (last
[0] == 'B')
11061 *obufp
++ = vex
.w
? 'w': 'b';
11072 ? vex
.prefix
== DATA_PREFIX_OPCODE
11073 : prefixes
& PREFIX_DATA
)
11076 used_prefixes
|= PREFIX_DATA
;
11082 if (l
== 1 && last
[0] == 'X')
11087 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
11089 switch (vex
.length
)
11109 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
11111 if (!intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
11112 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
11114 else if (l
== 1 && last
[0] == 'X')
11116 if (!need_vex
|| !vex
.evex
)
11119 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
11121 switch (vex
.length
)
11142 if (isa64
== intel64
&& (rex
& REX_W
))
11148 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
11150 if (sizeflag
& DFLAG
)
11154 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11163 mnemonicendp
= obufp
;
11168 oappend (const char *s
)
11170 obufp
= stpcpy (obufp
, s
);
11176 /* Only print the active segment register. */
11177 if (!active_seg_prefix
)
11180 used_prefixes
|= active_seg_prefix
;
11181 switch (active_seg_prefix
)
11184 oappend_maybe_intel ("%cs:");
11187 oappend_maybe_intel ("%ds:");
11190 oappend_maybe_intel ("%ss:");
11193 oappend_maybe_intel ("%es:");
11196 oappend_maybe_intel ("%fs:");
11199 oappend_maybe_intel ("%gs:");
11207 OP_indirE (int bytemode
, int sizeflag
)
11211 OP_E (bytemode
, sizeflag
);
11215 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
11217 if (address_mode
== mode_64bit
)
11225 sprintf_vma (tmp
, disp
);
11226 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
11227 strcpy (buf
+ 2, tmp
+ i
);
11231 bfd_signed_vma v
= disp
;
11238 /* Check for possible overflow on 0x8000000000000000. */
11241 strcpy (buf
, "9223372036854775808");
11255 tmp
[28 - i
] = (v
% 10) + '0';
11259 strcpy (buf
, tmp
+ 29 - i
);
11265 sprintf (buf
, "0x%x", (unsigned int) disp
);
11267 sprintf (buf
, "%d", (int) disp
);
11271 /* Put DISP in BUF as signed hex number. */
11274 print_displacement (char *buf
, bfd_vma disp
)
11276 bfd_signed_vma val
= disp
;
11285 /* Check for possible overflow. */
11288 switch (address_mode
)
11291 strcpy (buf
+ j
, "0x8000000000000000");
11294 strcpy (buf
+ j
, "0x80000000");
11297 strcpy (buf
+ j
, "0x8000");
11307 sprintf_vma (tmp
, (bfd_vma
) val
);
11308 for (i
= 0; tmp
[i
] == '0'; i
++)
11310 if (tmp
[i
] == '\0')
11312 strcpy (buf
+ j
, tmp
+ i
);
11316 intel_operand_size (int bytemode
, int sizeflag
)
11320 && (bytemode
== x_mode
11321 || bytemode
== evex_half_bcst_xmmq_mode
))
11324 oappend ("QWORD PTR ");
11326 oappend ("DWORD PTR ");
11335 oappend ("BYTE PTR ");
11340 oappend ("WORD PTR ");
11343 if (address_mode
== mode_64bit
&& isa64
== intel64
)
11345 oappend ("QWORD PTR ");
11348 /* Fall through. */
11350 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
11352 oappend ("QWORD PTR ");
11355 /* Fall through. */
11361 oappend ("QWORD PTR ");
11362 else if (bytemode
== dq_mode
)
11363 oappend ("DWORD PTR ");
11366 if (sizeflag
& DFLAG
)
11367 oappend ("DWORD PTR ");
11369 oappend ("WORD PTR ");
11370 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11374 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
11376 oappend ("WORD PTR ");
11377 if (!(rex
& REX_W
))
11378 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11381 if (sizeflag
& DFLAG
)
11382 oappend ("QWORD PTR ");
11384 oappend ("DWORD PTR ");
11385 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11388 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
11389 oappend ("WORD PTR ");
11391 oappend ("DWORD PTR ");
11392 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11397 oappend ("DWORD PTR ");
11401 oappend ("QWORD PTR ");
11404 if (address_mode
== mode_64bit
)
11405 oappend ("QWORD PTR ");
11407 oappend ("DWORD PTR ");
11410 if (sizeflag
& DFLAG
)
11411 oappend ("FWORD PTR ");
11413 oappend ("DWORD PTR ");
11414 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11417 oappend ("TBYTE PTR ");
11421 case evex_x_gscat_mode
:
11422 case evex_x_nobcst_mode
:
11426 switch (vex
.length
)
11429 oappend ("XMMWORD PTR ");
11432 oappend ("YMMWORD PTR ");
11435 oappend ("ZMMWORD PTR ");
11442 oappend ("XMMWORD PTR ");
11445 oappend ("XMMWORD PTR ");
11448 oappend ("YMMWORD PTR ");
11451 case evex_half_bcst_xmmq_mode
:
11455 switch (vex
.length
)
11458 oappend ("QWORD PTR ");
11461 oappend ("XMMWORD PTR ");
11464 oappend ("YMMWORD PTR ");
11474 switch (vex
.length
)
11479 oappend ("BYTE PTR ");
11489 switch (vex
.length
)
11494 oappend ("WORD PTR ");
11504 switch (vex
.length
)
11509 oappend ("DWORD PTR ");
11519 switch (vex
.length
)
11524 oappend ("QWORD PTR ");
11534 switch (vex
.length
)
11537 oappend ("WORD PTR ");
11540 oappend ("DWORD PTR ");
11543 oappend ("QWORD PTR ");
11553 switch (vex
.length
)
11556 oappend ("DWORD PTR ");
11559 oappend ("QWORD PTR ");
11562 oappend ("XMMWORD PTR ");
11572 switch (vex
.length
)
11575 oappend ("QWORD PTR ");
11578 oappend ("YMMWORD PTR ");
11581 oappend ("ZMMWORD PTR ");
11591 switch (vex
.length
)
11595 oappend ("XMMWORD PTR ");
11602 oappend ("OWORD PTR ");
11604 case vex_scalar_w_dq_mode
:
11609 oappend ("QWORD PTR ");
11611 oappend ("DWORD PTR ");
11613 case vex_vsib_d_w_dq_mode
:
11614 case vex_vsib_q_w_dq_mode
:
11621 oappend ("QWORD PTR ");
11623 oappend ("DWORD PTR ");
11627 switch (vex
.length
)
11630 oappend ("XMMWORD PTR ");
11633 oappend ("YMMWORD PTR ");
11636 oappend ("ZMMWORD PTR ");
11643 case vex_vsib_q_w_d_mode
:
11644 case vex_vsib_d_w_d_mode
:
11645 if (!need_vex
|| !vex
.evex
)
11648 switch (vex
.length
)
11651 oappend ("QWORD PTR ");
11654 oappend ("XMMWORD PTR ");
11657 oappend ("YMMWORD PTR ");
11665 if (!need_vex
|| vex
.length
!= 128)
11668 oappend ("DWORD PTR ");
11670 oappend ("BYTE PTR ");
11676 oappend ("QWORD PTR ");
11678 oappend ("WORD PTR ");
11688 OP_E_register (int bytemode
, int sizeflag
)
11690 int reg
= modrm
.rm
;
11691 const char **names
;
11697 if ((sizeflag
& SUFFIX_ALWAYS
)
11698 && (bytemode
== b_swap_mode
11699 || bytemode
== bnd_swap_mode
11700 || bytemode
== v_swap_mode
))
11727 names
= address_mode
== mode_64bit
? names64
: names32
;
11730 case bnd_swap_mode
:
11739 if (address_mode
== mode_64bit
&& isa64
== intel64
)
11744 /* Fall through. */
11746 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
11752 /* Fall through. */
11762 else if (bytemode
!= v_mode
&& bytemode
!= v_swap_mode
)
11766 if (sizeflag
& DFLAG
)
11770 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11774 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
11778 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11781 names
= (address_mode
== mode_64bit
11782 ? names64
: names32
);
11783 if (!(prefixes
& PREFIX_ADDR
))
11784 names
= (address_mode
== mode_16bit
11785 ? names16
: names
);
11788 /* Remove "addr16/addr32". */
11789 all_prefixes
[last_addr_prefix
] = 0;
11790 names
= (address_mode
!= mode_32bit
11791 ? names32
: names16
);
11792 used_prefixes
|= PREFIX_ADDR
;
11802 names
= names_mask
;
11807 oappend (INTERNAL_DISASSEMBLER_ERROR
);
11810 oappend (names
[reg
]);
11814 OP_E_memory (int bytemode
, int sizeflag
)
11817 int add
= (rex
& REX_B
) ? 8 : 0;
11823 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
11825 && bytemode
!= x_mode
11826 && bytemode
!= xmmq_mode
11827 && bytemode
!= evex_half_bcst_xmmq_mode
)
11845 if (address_mode
!= mode_64bit
)
11855 case vex_scalar_w_dq_mode
:
11856 case vex_vsib_d_w_dq_mode
:
11857 case vex_vsib_d_w_d_mode
:
11858 case vex_vsib_q_w_dq_mode
:
11859 case vex_vsib_q_w_d_mode
:
11860 case evex_x_gscat_mode
:
11861 shift
= vex
.w
? 3 : 2;
11864 case evex_half_bcst_xmmq_mode
:
11868 shift
= vex
.w
? 3 : 2;
11871 /* Fall through. */
11875 case evex_x_nobcst_mode
:
11877 switch (vex
.length
)
11891 /* Make necessary corrections to shift for modes that need it. */
11892 if (bytemode
== xmmq_mode
11893 || bytemode
== evex_half_bcst_xmmq_mode
11894 || (bytemode
== ymmq_mode
&& vex
.length
== 128))
11896 else if (bytemode
== xmmqd_mode
)
11898 else if (bytemode
== xmmdw_mode
)
11913 shift
= vex
.w
? 1 : 0;
11924 intel_operand_size (bytemode
, sizeflag
);
11927 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11929 /* 32/64 bit address mode */
11939 int addr32flag
= !((sizeflag
& AFLAG
)
11940 || bytemode
== v_bnd_mode
11941 || bytemode
== v_bndmk_mode
11942 || bytemode
== bnd_mode
11943 || bytemode
== bnd_swap_mode
);
11944 const char **indexes64
= names64
;
11945 const char **indexes32
= names32
;
11955 vindex
= sib
.index
;
11961 case vex_vsib_d_w_dq_mode
:
11962 case vex_vsib_d_w_d_mode
:
11963 case vex_vsib_q_w_dq_mode
:
11964 case vex_vsib_q_w_d_mode
:
11974 switch (vex
.length
)
11977 indexes64
= indexes32
= names_xmm
;
11981 || bytemode
== vex_vsib_q_w_dq_mode
11982 || bytemode
== vex_vsib_q_w_d_mode
)
11983 indexes64
= indexes32
= names_ymm
;
11985 indexes64
= indexes32
= names_xmm
;
11989 || bytemode
== vex_vsib_q_w_dq_mode
11990 || bytemode
== vex_vsib_q_w_d_mode
)
11991 indexes64
= indexes32
= names_zmm
;
11993 indexes64
= indexes32
= names_ymm
;
12000 haveindex
= vindex
!= 4;
12009 /* mandatory non-vector SIB must have sib */
12010 if (bytemode
== vex_sibmem_mode
)
12016 rbase
= base
+ add
;
12024 if (address_mode
== mode_64bit
&& !havesib
)
12027 if (riprel
&& bytemode
== v_bndmk_mode
)
12035 FETCH_DATA (the_info
, codep
+ 1);
12037 if ((disp
& 0x80) != 0)
12039 if (vex
.evex
&& shift
> 0)
12052 && address_mode
!= mode_16bit
)
12054 if (address_mode
== mode_64bit
)
12058 /* Without base nor index registers, zero-extend the
12059 lower 32-bit displacement to 64 bits. */
12060 disp
= (unsigned int) disp
;
12067 /* In 32-bit mode, we need index register to tell [offset]
12068 from [eiz*1 + offset]. */
12073 havedisp
= (havebase
12075 || (havesib
&& (haveindex
|| scale
!= 0)));
12078 if (modrm
.mod
!= 0 || base
== 5)
12080 if (havedisp
|| riprel
)
12081 print_displacement (scratchbuf
, disp
);
12083 print_operand_value (scratchbuf
, 1, disp
);
12084 oappend (scratchbuf
);
12088 oappend (!addr32flag
? "(%rip)" : "(%eip)");
12092 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
12093 && (address_mode
!= mode_64bit
12094 || ((bytemode
!= v_bnd_mode
)
12095 && (bytemode
!= v_bndmk_mode
)
12096 && (bytemode
!= bnd_mode
)
12097 && (bytemode
!= bnd_swap_mode
))))
12098 used_prefixes
|= PREFIX_ADDR
;
12100 if (havedisp
|| (intel_syntax
&& riprel
))
12102 *obufp
++ = open_char
;
12103 if (intel_syntax
&& riprel
)
12106 oappend (!addr32flag
? "rip" : "eip");
12110 oappend (address_mode
== mode_64bit
&& !addr32flag
12111 ? names64
[rbase
] : names32
[rbase
]);
12114 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
12115 print index to tell base + index from base. */
12119 || (havebase
&& base
!= ESP_REG_NUM
))
12121 if (!intel_syntax
|| havebase
)
12123 *obufp
++ = separator_char
;
12127 oappend (address_mode
== mode_64bit
&& !addr32flag
12128 ? indexes64
[vindex
] : indexes32
[vindex
]);
12130 oappend (address_mode
== mode_64bit
&& !addr32flag
12131 ? index64
: index32
);
12133 *obufp
++ = scale_char
;
12135 sprintf (scratchbuf
, "%d", 1 << scale
);
12136 oappend (scratchbuf
);
12140 && (disp
|| modrm
.mod
!= 0 || base
== 5))
12142 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
12147 else if (modrm
.mod
!= 1 && disp
!= -disp
)
12155 print_displacement (scratchbuf
, disp
);
12157 print_operand_value (scratchbuf
, 1, disp
);
12158 oappend (scratchbuf
);
12161 *obufp
++ = close_char
;
12164 else if (intel_syntax
)
12166 if (modrm
.mod
!= 0 || base
== 5)
12168 if (!active_seg_prefix
)
12170 oappend (names_seg
[ds_reg
- es_reg
]);
12173 print_operand_value (scratchbuf
, 1, disp
);
12174 oappend (scratchbuf
);
12178 else if (bytemode
== v_bnd_mode
12179 || bytemode
== v_bndmk_mode
12180 || bytemode
== bnd_mode
12181 || bytemode
== bnd_swap_mode
)
12188 /* 16 bit address mode */
12189 used_prefixes
|= prefixes
& PREFIX_ADDR
;
12196 if ((disp
& 0x8000) != 0)
12201 FETCH_DATA (the_info
, codep
+ 1);
12203 if ((disp
& 0x80) != 0)
12205 if (vex
.evex
&& shift
> 0)
12210 if ((disp
& 0x8000) != 0)
12216 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
12218 print_displacement (scratchbuf
, disp
);
12219 oappend (scratchbuf
);
12222 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
12224 *obufp
++ = open_char
;
12226 oappend (index16
[modrm
.rm
]);
12228 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
12230 if ((bfd_signed_vma
) disp
>= 0)
12235 else if (modrm
.mod
!= 1)
12242 print_displacement (scratchbuf
, disp
);
12243 oappend (scratchbuf
);
12246 *obufp
++ = close_char
;
12249 else if (intel_syntax
)
12251 if (!active_seg_prefix
)
12253 oappend (names_seg
[ds_reg
- es_reg
]);
12256 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
12257 oappend (scratchbuf
);
12260 if (vex
.evex
&& vex
.b
12261 && (bytemode
== x_mode
12262 || bytemode
== xmmq_mode
12263 || bytemode
== evex_half_bcst_xmmq_mode
))
12266 || bytemode
== xmmq_mode
12267 || bytemode
== evex_half_bcst_xmmq_mode
)
12269 switch (vex
.length
)
12272 oappend ("{1to2}");
12275 oappend ("{1to4}");
12278 oappend ("{1to8}");
12286 switch (vex
.length
)
12289 oappend ("{1to4}");
12292 oappend ("{1to8}");
12295 oappend ("{1to16}");
12305 OP_E (int bytemode
, int sizeflag
)
12307 /* Skip mod/rm byte. */
12311 if (modrm
.mod
== 3)
12312 OP_E_register (bytemode
, sizeflag
);
12314 OP_E_memory (bytemode
, sizeflag
);
12318 OP_G (int bytemode
, int sizeflag
)
12321 const char **names
;
12331 oappend (names8rex
[modrm
.reg
+ add
]);
12333 oappend (names8
[modrm
.reg
+ add
]);
12336 oappend (names16
[modrm
.reg
+ add
]);
12341 oappend (names32
[modrm
.reg
+ add
]);
12344 oappend (names64
[modrm
.reg
+ add
]);
12347 if (modrm
.reg
> 0x3)
12352 oappend (names_bnd
[modrm
.reg
]);
12362 oappend (names64
[modrm
.reg
+ add
]);
12363 else if (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
)
12364 oappend (names32
[modrm
.reg
+ add
]);
12367 if (sizeflag
& DFLAG
)
12368 oappend (names32
[modrm
.reg
+ add
]);
12370 oappend (names16
[modrm
.reg
+ add
]);
12371 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12375 names
= (address_mode
== mode_64bit
12376 ? names64
: names32
);
12377 if (!(prefixes
& PREFIX_ADDR
))
12379 if (address_mode
== mode_16bit
)
12384 /* Remove "addr16/addr32". */
12385 all_prefixes
[last_addr_prefix
] = 0;
12386 names
= (address_mode
!= mode_32bit
12387 ? names32
: names16
);
12388 used_prefixes
|= PREFIX_ADDR
;
12390 oappend (names
[modrm
.reg
+ add
]);
12393 if (address_mode
== mode_64bit
)
12394 oappend (names64
[modrm
.reg
+ add
]);
12396 oappend (names32
[modrm
.reg
+ add
]);
12400 if ((modrm
.reg
+ add
) > 0x7)
12405 oappend (names_mask
[modrm
.reg
+ add
]);
12408 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12421 FETCH_DATA (the_info
, codep
+ 8);
12422 a
= *codep
++ & 0xff;
12423 a
|= (*codep
++ & 0xff) << 8;
12424 a
|= (*codep
++ & 0xff) << 16;
12425 a
|= (*codep
++ & 0xffu
) << 24;
12426 b
= *codep
++ & 0xff;
12427 b
|= (*codep
++ & 0xff) << 8;
12428 b
|= (*codep
++ & 0xff) << 16;
12429 b
|= (*codep
++ & 0xffu
) << 24;
12430 x
= a
+ ((bfd_vma
) b
<< 32);
12438 static bfd_signed_vma
12443 FETCH_DATA (the_info
, codep
+ 4);
12444 x
= *codep
++ & (bfd_vma
) 0xff;
12445 x
|= (*codep
++ & (bfd_vma
) 0xff) << 8;
12446 x
|= (*codep
++ & (bfd_vma
) 0xff) << 16;
12447 x
|= (*codep
++ & (bfd_vma
) 0xff) << 24;
12451 static bfd_signed_vma
12456 FETCH_DATA (the_info
, codep
+ 4);
12457 x
= *codep
++ & (bfd_vma
) 0xff;
12458 x
|= (*codep
++ & (bfd_vma
) 0xff) << 8;
12459 x
|= (*codep
++ & (bfd_vma
) 0xff) << 16;
12460 x
|= (*codep
++ & (bfd_vma
) 0xff) << 24;
12462 x
= (x
^ ((bfd_vma
) 1 << 31)) - ((bfd_vma
) 1 << 31);
12472 FETCH_DATA (the_info
, codep
+ 2);
12473 x
= *codep
++ & 0xff;
12474 x
|= (*codep
++ & 0xff) << 8;
12479 set_op (bfd_vma op
, int riprel
)
12481 op_index
[op_ad
] = op_ad
;
12482 if (address_mode
== mode_64bit
)
12484 op_address
[op_ad
] = op
;
12485 op_riprel
[op_ad
] = riprel
;
12489 /* Mask to get a 32-bit address. */
12490 op_address
[op_ad
] = op
& 0xffffffff;
12491 op_riprel
[op_ad
] = riprel
& 0xffffffff;
12496 OP_REG (int code
, int sizeflag
)
12503 case es_reg
: case ss_reg
: case cs_reg
:
12504 case ds_reg
: case fs_reg
: case gs_reg
:
12505 oappend (names_seg
[code
- es_reg
]);
12517 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
12518 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
12519 s
= names16
[code
- ax_reg
+ add
];
12521 case ah_reg
: case ch_reg
: case dh_reg
: case bh_reg
:
12523 /* Fall through. */
12524 case al_reg
: case cl_reg
: case dl_reg
: case bl_reg
:
12526 s
= names8rex
[code
- al_reg
+ add
];
12528 s
= names8
[code
- al_reg
];
12530 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
12531 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
12532 if (address_mode
== mode_64bit
12533 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12535 s
= names64
[code
- rAX_reg
+ add
];
12538 code
+= eAX_reg
- rAX_reg
;
12539 /* Fall through. */
12540 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
12541 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
12544 s
= names64
[code
- eAX_reg
+ add
];
12547 if (sizeflag
& DFLAG
)
12548 s
= names32
[code
- eAX_reg
+ add
];
12550 s
= names16
[code
- eAX_reg
+ add
];
12551 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12555 s
= INTERNAL_DISASSEMBLER_ERROR
;
12562 OP_IMREG (int code
, int sizeflag
)
12574 case al_reg
: case cl_reg
:
12575 s
= names8
[code
- al_reg
];
12584 /* Fall through. */
12585 case z_mode_ax_reg
:
12586 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12590 if (!(rex
& REX_W
))
12591 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12594 s
= INTERNAL_DISASSEMBLER_ERROR
;
12601 OP_I (int bytemode
, int sizeflag
)
12604 bfd_signed_vma mask
= -1;
12609 FETCH_DATA (the_info
, codep
+ 1);
12619 if (sizeflag
& DFLAG
)
12629 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12645 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12650 scratchbuf
[0] = '$';
12651 print_operand_value (scratchbuf
+ 1, 1, op
);
12652 oappend_maybe_intel (scratchbuf
);
12653 scratchbuf
[0] = '\0';
12657 OP_I64 (int bytemode
, int sizeflag
)
12659 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
12661 OP_I (bytemode
, sizeflag
);
12667 scratchbuf
[0] = '$';
12668 print_operand_value (scratchbuf
+ 1, 1, get64 ());
12669 oappend_maybe_intel (scratchbuf
);
12670 scratchbuf
[0] = '\0';
12674 OP_sI (int bytemode
, int sizeflag
)
12682 FETCH_DATA (the_info
, codep
+ 1);
12684 if ((op
& 0x80) != 0)
12686 if (bytemode
== b_T_mode
)
12688 if (address_mode
!= mode_64bit
12689 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12691 /* The operand-size prefix is overridden by a REX prefix. */
12692 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
12700 if (!(rex
& REX_W
))
12702 if (sizeflag
& DFLAG
)
12710 /* The operand-size prefix is overridden by a REX prefix. */
12711 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
12717 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12721 scratchbuf
[0] = '$';
12722 print_operand_value (scratchbuf
+ 1, 1, op
);
12723 oappend_maybe_intel (scratchbuf
);
12727 OP_J (int bytemode
, int sizeflag
)
12731 bfd_vma segment
= 0;
12736 FETCH_DATA (the_info
, codep
+ 1);
12738 if ((disp
& 0x80) != 0)
12743 if ((sizeflag
& DFLAG
)
12744 || (address_mode
== mode_64bit
12745 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
12746 || (rex
& REX_W
))))
12751 if ((disp
& 0x8000) != 0)
12753 /* In 16bit mode, address is wrapped around at 64k within
12754 the same segment. Otherwise, a data16 prefix on a jump
12755 instruction means that the pc is masked to 16 bits after
12756 the displacement is added! */
12758 if ((prefixes
& PREFIX_DATA
) == 0)
12759 segment
= ((start_pc
+ (codep
- start_codep
))
12760 & ~((bfd_vma
) 0xffff));
12762 if (address_mode
!= mode_64bit
12763 || (isa64
!= intel64
&& !(rex
& REX_W
)))
12764 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12767 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12770 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
12772 print_operand_value (scratchbuf
, 1, disp
);
12773 oappend (scratchbuf
);
12777 OP_SEG (int bytemode
, int sizeflag
)
12779 if (bytemode
== w_mode
)
12780 oappend (names_seg
[modrm
.reg
]);
12782 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
12786 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
12790 if (sizeflag
& DFLAG
)
12800 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12802 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
12804 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
12805 oappend (scratchbuf
);
12809 OP_OFF (int bytemode
, int sizeflag
)
12813 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
12814 intel_operand_size (bytemode
, sizeflag
);
12817 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12824 if (!active_seg_prefix
)
12826 oappend (names_seg
[ds_reg
- es_reg
]);
12830 print_operand_value (scratchbuf
, 1, off
);
12831 oappend (scratchbuf
);
12835 OP_OFF64 (int bytemode
, int sizeflag
)
12839 if (address_mode
!= mode_64bit
12840 || (prefixes
& PREFIX_ADDR
))
12842 OP_OFF (bytemode
, sizeflag
);
12846 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
12847 intel_operand_size (bytemode
, sizeflag
);
12854 if (!active_seg_prefix
)
12856 oappend (names_seg
[ds_reg
- es_reg
]);
12860 print_operand_value (scratchbuf
, 1, off
);
12861 oappend (scratchbuf
);
12865 ptr_reg (int code
, int sizeflag
)
12869 *obufp
++ = open_char
;
12870 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12871 if (address_mode
== mode_64bit
)
12873 if (!(sizeflag
& AFLAG
))
12874 s
= names32
[code
- eAX_reg
];
12876 s
= names64
[code
- eAX_reg
];
12878 else if (sizeflag
& AFLAG
)
12879 s
= names32
[code
- eAX_reg
];
12881 s
= names16
[code
- eAX_reg
];
12883 *obufp
++ = close_char
;
12888 OP_ESreg (int code
, int sizeflag
)
12894 case 0x6d: /* insw/insl */
12895 intel_operand_size (z_mode
, sizeflag
);
12897 case 0xa5: /* movsw/movsl/movsq */
12898 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12899 case 0xab: /* stosw/stosl */
12900 case 0xaf: /* scasw/scasl */
12901 intel_operand_size (v_mode
, sizeflag
);
12904 intel_operand_size (b_mode
, sizeflag
);
12907 oappend_maybe_intel ("%es:");
12908 ptr_reg (code
, sizeflag
);
12912 OP_DSreg (int code
, int sizeflag
)
12918 case 0x6f: /* outsw/outsl */
12919 intel_operand_size (z_mode
, sizeflag
);
12921 case 0xa5: /* movsw/movsl/movsq */
12922 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12923 case 0xad: /* lodsw/lodsl/lodsq */
12924 intel_operand_size (v_mode
, sizeflag
);
12927 intel_operand_size (b_mode
, sizeflag
);
12930 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12931 default segment register DS is printed. */
12932 if (!active_seg_prefix
)
12933 active_seg_prefix
= PREFIX_DS
;
12935 ptr_reg (code
, sizeflag
);
12939 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12947 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
12949 all_prefixes
[last_lock_prefix
] = 0;
12950 used_prefixes
|= PREFIX_LOCK
;
12955 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
12956 oappend_maybe_intel (scratchbuf
);
12960 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12969 sprintf (scratchbuf
, "dr%d", modrm
.reg
+ add
);
12971 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
12972 oappend (scratchbuf
);
12976 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12978 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
12979 oappend_maybe_intel (scratchbuf
);
12983 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12985 int reg
= modrm
.reg
;
12986 const char **names
;
12988 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12989 if (prefixes
& PREFIX_DATA
)
12998 oappend (names
[reg
]);
13002 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13004 int reg
= modrm
.reg
;
13005 const char **names
;
13017 && bytemode
!= xmm_mode
13018 && bytemode
!= xmmq_mode
13019 && bytemode
!= evex_half_bcst_xmmq_mode
13020 && bytemode
!= ymm_mode
13021 && bytemode
!= tmm_mode
13022 && bytemode
!= scalar_mode
)
13024 switch (vex
.length
)
13031 || (bytemode
!= vex_vsib_q_w_dq_mode
13032 && bytemode
!= vex_vsib_q_w_d_mode
))
13044 else if (bytemode
== xmmq_mode
13045 || bytemode
== evex_half_bcst_xmmq_mode
)
13047 switch (vex
.length
)
13060 else if (bytemode
== tmm_mode
)
13070 else if (bytemode
== ymm_mode
)
13074 oappend (names
[reg
]);
13078 OP_EM (int bytemode
, int sizeflag
)
13081 const char **names
;
13083 if (modrm
.mod
!= 3)
13086 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
13088 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
13089 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13091 OP_E (bytemode
, sizeflag
);
13095 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
13098 /* Skip mod/rm byte. */
13101 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13103 if (prefixes
& PREFIX_DATA
)
13112 oappend (names
[reg
]);
13115 /* cvt* are the only instructions in sse2 which have
13116 both SSE and MMX operands and also have 0x66 prefix
13117 in their opcode. 0x66 was originally used to differentiate
13118 between SSE and MMX instruction(operands). So we have to handle the
13119 cvt* separately using OP_EMC and OP_MXC */
13121 OP_EMC (int bytemode
, int sizeflag
)
13123 if (modrm
.mod
!= 3)
13125 if (intel_syntax
&& bytemode
== v_mode
)
13127 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
13128 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13130 OP_E (bytemode
, sizeflag
);
13134 /* Skip mod/rm byte. */
13137 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13138 oappend (names_mm
[modrm
.rm
]);
13142 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13144 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13145 oappend (names_mm
[modrm
.reg
]);
13149 OP_EX (int bytemode
, int sizeflag
)
13152 const char **names
;
13154 /* Skip mod/rm byte. */
13158 if (modrm
.mod
!= 3)
13160 OP_E_memory (bytemode
, sizeflag
);
13175 if ((sizeflag
& SUFFIX_ALWAYS
)
13176 && (bytemode
== x_swap_mode
13177 || bytemode
== d_swap_mode
13178 || bytemode
== q_swap_mode
))
13182 && bytemode
!= xmm_mode
13183 && bytemode
!= xmmdw_mode
13184 && bytemode
!= xmmqd_mode
13185 && bytemode
!= xmm_mb_mode
13186 && bytemode
!= xmm_mw_mode
13187 && bytemode
!= xmm_md_mode
13188 && bytemode
!= xmm_mq_mode
13189 && bytemode
!= xmmq_mode
13190 && bytemode
!= evex_half_bcst_xmmq_mode
13191 && bytemode
!= ymm_mode
13192 && bytemode
!= tmm_mode
13193 && bytemode
!= vex_scalar_w_dq_mode
)
13195 switch (vex
.length
)
13210 else if (bytemode
== xmmq_mode
13211 || bytemode
== evex_half_bcst_xmmq_mode
)
13213 switch (vex
.length
)
13226 else if (bytemode
== tmm_mode
)
13236 else if (bytemode
== ymm_mode
)
13240 oappend (names
[reg
]);
13244 OP_MS (int bytemode
, int sizeflag
)
13246 if (modrm
.mod
== 3)
13247 OP_EM (bytemode
, sizeflag
);
13253 OP_XS (int bytemode
, int sizeflag
)
13255 if (modrm
.mod
== 3)
13256 OP_EX (bytemode
, sizeflag
);
13262 OP_M (int bytemode
, int sizeflag
)
13264 if (modrm
.mod
== 3)
13265 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13268 OP_E (bytemode
, sizeflag
);
13272 OP_0f07 (int bytemode
, int sizeflag
)
13274 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
13277 OP_E (bytemode
, sizeflag
);
13280 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13281 32bit mode and "xchg %rax,%rax" in 64bit mode. */
13284 NOP_Fixup1 (int bytemode
, int sizeflag
)
13286 if ((prefixes
& PREFIX_DATA
) != 0
13289 && address_mode
== mode_64bit
))
13290 OP_REG (bytemode
, sizeflag
);
13292 strcpy (obuf
, "nop");
13296 NOP_Fixup2 (int bytemode
, int sizeflag
)
13298 if ((prefixes
& PREFIX_DATA
) != 0
13301 && address_mode
== mode_64bit
))
13302 OP_IMREG (bytemode
, sizeflag
);
13305 static const char *const Suffix3DNow
[] = {
13306 /* 00 */ NULL
, NULL
, NULL
, NULL
,
13307 /* 04 */ NULL
, NULL
, NULL
, NULL
,
13308 /* 08 */ NULL
, NULL
, NULL
, NULL
,
13309 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
13310 /* 10 */ NULL
, NULL
, NULL
, NULL
,
13311 /* 14 */ NULL
, NULL
, NULL
, NULL
,
13312 /* 18 */ NULL
, NULL
, NULL
, NULL
,
13313 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
13314 /* 20 */ NULL
, NULL
, NULL
, NULL
,
13315 /* 24 */ NULL
, NULL
, NULL
, NULL
,
13316 /* 28 */ NULL
, NULL
, NULL
, NULL
,
13317 /* 2C */ NULL
, NULL
, NULL
, NULL
,
13318 /* 30 */ NULL
, NULL
, NULL
, NULL
,
13319 /* 34 */ NULL
, NULL
, NULL
, NULL
,
13320 /* 38 */ NULL
, NULL
, NULL
, NULL
,
13321 /* 3C */ NULL
, NULL
, NULL
, NULL
,
13322 /* 40 */ NULL
, NULL
, NULL
, NULL
,
13323 /* 44 */ NULL
, NULL
, NULL
, NULL
,
13324 /* 48 */ NULL
, NULL
, NULL
, NULL
,
13325 /* 4C */ NULL
, NULL
, NULL
, NULL
,
13326 /* 50 */ NULL
, NULL
, NULL
, NULL
,
13327 /* 54 */ NULL
, NULL
, NULL
, NULL
,
13328 /* 58 */ NULL
, NULL
, NULL
, NULL
,
13329 /* 5C */ NULL
, NULL
, NULL
, NULL
,
13330 /* 60 */ NULL
, NULL
, NULL
, NULL
,
13331 /* 64 */ NULL
, NULL
, NULL
, NULL
,
13332 /* 68 */ NULL
, NULL
, NULL
, NULL
,
13333 /* 6C */ NULL
, NULL
, NULL
, NULL
,
13334 /* 70 */ NULL
, NULL
, NULL
, NULL
,
13335 /* 74 */ NULL
, NULL
, NULL
, NULL
,
13336 /* 78 */ NULL
, NULL
, NULL
, NULL
,
13337 /* 7C */ NULL
, NULL
, NULL
, NULL
,
13338 /* 80 */ NULL
, NULL
, NULL
, NULL
,
13339 /* 84 */ NULL
, NULL
, NULL
, NULL
,
13340 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
13341 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
13342 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
13343 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
13344 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
13345 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
13346 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
13347 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
13348 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
13349 /* AC */ NULL
, NULL
, "pfacc", NULL
,
13350 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
13351 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
13352 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
13353 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
13354 /* C0 */ NULL
, NULL
, NULL
, NULL
,
13355 /* C4 */ NULL
, NULL
, NULL
, NULL
,
13356 /* C8 */ NULL
, NULL
, NULL
, NULL
,
13357 /* CC */ NULL
, NULL
, NULL
, NULL
,
13358 /* D0 */ NULL
, NULL
, NULL
, NULL
,
13359 /* D4 */ NULL
, NULL
, NULL
, NULL
,
13360 /* D8 */ NULL
, NULL
, NULL
, NULL
,
13361 /* DC */ NULL
, NULL
, NULL
, NULL
,
13362 /* E0 */ NULL
, NULL
, NULL
, NULL
,
13363 /* E4 */ NULL
, NULL
, NULL
, NULL
,
13364 /* E8 */ NULL
, NULL
, NULL
, NULL
,
13365 /* EC */ NULL
, NULL
, NULL
, NULL
,
13366 /* F0 */ NULL
, NULL
, NULL
, NULL
,
13367 /* F4 */ NULL
, NULL
, NULL
, NULL
,
13368 /* F8 */ NULL
, NULL
, NULL
, NULL
,
13369 /* FC */ NULL
, NULL
, NULL
, NULL
,
13373 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13375 const char *mnemonic
;
13377 FETCH_DATA (the_info
, codep
+ 1);
13378 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13379 place where an 8-bit immediate would normally go. ie. the last
13380 byte of the instruction. */
13381 obufp
= mnemonicendp
;
13382 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
13384 oappend (mnemonic
);
13387 /* Since a variable sized modrm/sib chunk is between the start
13388 of the opcode (0x0f0f) and the opcode suffix, we need to do
13389 all the modrm processing first, and don't know until now that
13390 we have a bad opcode. This necessitates some cleaning up. */
13391 op_out
[0][0] = '\0';
13392 op_out
[1][0] = '\0';
13395 mnemonicendp
= obufp
;
13398 static const struct op simd_cmp_op
[] =
13400 { STRING_COMMA_LEN ("eq") },
13401 { STRING_COMMA_LEN ("lt") },
13402 { STRING_COMMA_LEN ("le") },
13403 { STRING_COMMA_LEN ("unord") },
13404 { STRING_COMMA_LEN ("neq") },
13405 { STRING_COMMA_LEN ("nlt") },
13406 { STRING_COMMA_LEN ("nle") },
13407 { STRING_COMMA_LEN ("ord") }
13410 static const struct op vex_cmp_op
[] =
13412 { STRING_COMMA_LEN ("eq_uq") },
13413 { STRING_COMMA_LEN ("nge") },
13414 { STRING_COMMA_LEN ("ngt") },
13415 { STRING_COMMA_LEN ("false") },
13416 { STRING_COMMA_LEN ("neq_oq") },
13417 { STRING_COMMA_LEN ("ge") },
13418 { STRING_COMMA_LEN ("gt") },
13419 { STRING_COMMA_LEN ("true") },
13420 { STRING_COMMA_LEN ("eq_os") },
13421 { STRING_COMMA_LEN ("lt_oq") },
13422 { STRING_COMMA_LEN ("le_oq") },
13423 { STRING_COMMA_LEN ("unord_s") },
13424 { STRING_COMMA_LEN ("neq_us") },
13425 { STRING_COMMA_LEN ("nlt_uq") },
13426 { STRING_COMMA_LEN ("nle_uq") },
13427 { STRING_COMMA_LEN ("ord_s") },
13428 { STRING_COMMA_LEN ("eq_us") },
13429 { STRING_COMMA_LEN ("nge_uq") },
13430 { STRING_COMMA_LEN ("ngt_uq") },
13431 { STRING_COMMA_LEN ("false_os") },
13432 { STRING_COMMA_LEN ("neq_os") },
13433 { STRING_COMMA_LEN ("ge_oq") },
13434 { STRING_COMMA_LEN ("gt_oq") },
13435 { STRING_COMMA_LEN ("true_us") },
13439 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13441 unsigned int cmp_type
;
13443 FETCH_DATA (the_info
, codep
+ 1);
13444 cmp_type
= *codep
++ & 0xff;
13445 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
13448 char *p
= mnemonicendp
- 2;
13452 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
13453 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
13456 && cmp_type
< ARRAY_SIZE (simd_cmp_op
) + ARRAY_SIZE (vex_cmp_op
))
13459 char *p
= mnemonicendp
- 2;
13463 cmp_type
-= ARRAY_SIZE (simd_cmp_op
);
13464 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
13465 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
13469 /* We have a reserved extension byte. Output it directly. */
13470 scratchbuf
[0] = '$';
13471 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13472 oappend_maybe_intel (scratchbuf
);
13473 scratchbuf
[0] = '\0';
13478 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13480 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13483 strcpy (op_out
[0], names32
[0]);
13484 strcpy (op_out
[1], names32
[1]);
13485 if (bytemode
== eBX_reg
)
13486 strcpy (op_out
[2], names32
[3]);
13487 two_source_ops
= 1;
13489 /* Skip mod/rm byte. */
13495 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
13496 int sizeflag ATTRIBUTE_UNUSED
)
13498 /* monitor %{e,r,}ax,%ecx,%edx" */
13501 const char **names
= (address_mode
== mode_64bit
13502 ? names64
: names32
);
13504 if (prefixes
& PREFIX_ADDR
)
13506 /* Remove "addr16/addr32". */
13507 all_prefixes
[last_addr_prefix
] = 0;
13508 names
= (address_mode
!= mode_32bit
13509 ? names32
: names16
);
13510 used_prefixes
|= PREFIX_ADDR
;
13512 else if (address_mode
== mode_16bit
)
13514 strcpy (op_out
[0], names
[0]);
13515 strcpy (op_out
[1], names32
[1]);
13516 strcpy (op_out
[2], names32
[2]);
13517 two_source_ops
= 1;
13519 /* Skip mod/rm byte. */
13527 /* Throw away prefixes and 1st. opcode byte. */
13528 codep
= insn_codep
+ 1;
13533 REP_Fixup (int bytemode
, int sizeflag
)
13535 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13537 if (prefixes
& PREFIX_REPZ
)
13538 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
13545 OP_IMREG (bytemode
, sizeflag
);
13548 OP_ESreg (bytemode
, sizeflag
);
13551 OP_DSreg (bytemode
, sizeflag
);
13560 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13562 if ( isa64
!= amd64
)
13567 mnemonicendp
= obufp
;
13571 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13575 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13577 if (prefixes
& PREFIX_REPNZ
)
13578 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
13581 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13585 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13586 int sizeflag ATTRIBUTE_UNUSED
)
13588 if (active_seg_prefix
== PREFIX_DS
13589 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
13591 /* NOTRACK prefix is only valid on indirect branch instructions.
13592 NB: DATA prefix is unsupported for Intel64. */
13593 active_seg_prefix
= 0;
13594 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
13598 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13599 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13603 HLE_Fixup1 (int bytemode
, int sizeflag
)
13606 && (prefixes
& PREFIX_LOCK
) != 0)
13608 if (prefixes
& PREFIX_REPZ
)
13609 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13610 if (prefixes
& PREFIX_REPNZ
)
13611 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13614 OP_E (bytemode
, sizeflag
);
13617 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13618 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13622 HLE_Fixup2 (int bytemode
, int sizeflag
)
13624 if (modrm
.mod
!= 3)
13626 if (prefixes
& PREFIX_REPZ
)
13627 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13628 if (prefixes
& PREFIX_REPNZ
)
13629 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13632 OP_E (bytemode
, sizeflag
);
13635 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13636 "xrelease" for memory operand. No check for LOCK prefix. */
13639 HLE_Fixup3 (int bytemode
, int sizeflag
)
13642 && last_repz_prefix
> last_repnz_prefix
13643 && (prefixes
& PREFIX_REPZ
) != 0)
13644 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13646 OP_E (bytemode
, sizeflag
);
13650 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
13655 /* Change cmpxchg8b to cmpxchg16b. */
13656 char *p
= mnemonicendp
- 2;
13657 mnemonicendp
= stpcpy (p
, "16b");
13660 else if ((prefixes
& PREFIX_LOCK
) != 0)
13662 if (prefixes
& PREFIX_REPZ
)
13663 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13664 if (prefixes
& PREFIX_REPNZ
)
13665 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13668 OP_M (bytemode
, sizeflag
);
13672 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
13674 const char **names
;
13678 switch (vex
.length
)
13692 oappend (names
[reg
]);
13696 FXSAVE_Fixup (int bytemode
, int sizeflag
)
13698 /* Add proper suffix to "fxsave" and "fxrstor". */
13702 char *p
= mnemonicendp
;
13708 OP_M (bytemode
, sizeflag
);
13711 /* Display the destination register operand for instructions with
13715 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13718 const char **names
;
13723 reg
= vex
.register_specifier
;
13724 vex
.register_specifier
= 0;
13725 if (address_mode
!= mode_64bit
)
13727 else if (vex
.evex
&& !vex
.v
)
13730 if (bytemode
== vex_scalar_mode
)
13732 oappend (names_xmm
[reg
]);
13736 if (bytemode
== tmm_mode
)
13738 /* All 3 TMM registers must be distinct. */
13743 /* This must be the 3rd operand. */
13744 if (obufp
!= op_out
[2])
13746 oappend (names_tmm
[reg
]);
13747 if (reg
== modrm
.reg
|| reg
== modrm
.rm
)
13748 strcpy (obufp
, "/(bad)");
13751 if (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
|| modrm
.rm
== reg
)
13754 && (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
))
13755 strcat (op_out
[0], "/(bad)");
13757 && (modrm
.rm
== modrm
.reg
|| modrm
.rm
== reg
))
13758 strcat (op_out
[1], "/(bad)");
13764 switch (vex
.length
)
13770 case vex_vsib_q_w_dq_mode
:
13771 case vex_vsib_q_w_d_mode
:
13787 names
= names_mask
;
13800 case vex_vsib_q_w_dq_mode
:
13801 case vex_vsib_q_w_d_mode
:
13802 names
= vex
.w
? names_ymm
: names_xmm
;
13811 names
= names_mask
;
13814 /* See PR binutils/20893 for a reproducer. */
13826 oappend (names
[reg
]);
13830 OP_VexR (int bytemode
, int sizeflag
)
13832 if (modrm
.mod
== 3)
13833 OP_VEX (bytemode
, sizeflag
);
13837 OP_VexW (int bytemode
, int sizeflag
)
13839 OP_VEX (bytemode
, sizeflag
);
13843 /* Swap 2nd and 3rd operands. */
13844 strcpy (scratchbuf
, op_out
[2]);
13845 strcpy (op_out
[2], op_out
[1]);
13846 strcpy (op_out
[1], scratchbuf
);
13851 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13854 const char **names
= names_xmm
;
13856 FETCH_DATA (the_info
, codep
+ 1);
13859 if (bytemode
!= x_mode
&& bytemode
!= scalar_mode
)
13863 if (address_mode
!= mode_64bit
)
13866 if (bytemode
== x_mode
&& vex
.length
== 256)
13869 oappend (names
[reg
]);
13873 /* Swap 3rd and 4th operands. */
13874 strcpy (scratchbuf
, op_out
[3]);
13875 strcpy (op_out
[3], op_out
[2]);
13876 strcpy (op_out
[2], scratchbuf
);
13881 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED
,
13882 int sizeflag ATTRIBUTE_UNUSED
)
13884 scratchbuf
[0] = '$';
13885 print_operand_value (scratchbuf
+ 1, 1, codep
[-1] & 0xf);
13886 oappend_maybe_intel (scratchbuf
);
13890 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13891 int sizeflag ATTRIBUTE_UNUSED
)
13893 unsigned int cmp_type
;
13898 FETCH_DATA (the_info
, codep
+ 1);
13899 cmp_type
= *codep
++ & 0xff;
13900 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13901 If it's the case, print suffix, otherwise - print the immediate. */
13902 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
13907 char *p
= mnemonicendp
- 2;
13909 /* vpcmp* can have both one- and two-lettered suffix. */
13923 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
13924 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
13928 /* We have a reserved extension byte. Output it directly. */
13929 scratchbuf
[0] = '$';
13930 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13931 oappend_maybe_intel (scratchbuf
);
13932 scratchbuf
[0] = '\0';
13936 static const struct op xop_cmp_op
[] =
13938 { STRING_COMMA_LEN ("lt") },
13939 { STRING_COMMA_LEN ("le") },
13940 { STRING_COMMA_LEN ("gt") },
13941 { STRING_COMMA_LEN ("ge") },
13942 { STRING_COMMA_LEN ("eq") },
13943 { STRING_COMMA_LEN ("neq") },
13944 { STRING_COMMA_LEN ("false") },
13945 { STRING_COMMA_LEN ("true") }
13949 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13950 int sizeflag ATTRIBUTE_UNUSED
)
13952 unsigned int cmp_type
;
13954 FETCH_DATA (the_info
, codep
+ 1);
13955 cmp_type
= *codep
++ & 0xff;
13956 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
13959 char *p
= mnemonicendp
- 2;
13961 /* vpcom* can have both one- and two-lettered suffix. */
13975 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
13976 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
13980 /* We have a reserved extension byte. Output it directly. */
13981 scratchbuf
[0] = '$';
13982 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13983 oappend_maybe_intel (scratchbuf
);
13984 scratchbuf
[0] = '\0';
13988 static const struct op pclmul_op
[] =
13990 { STRING_COMMA_LEN ("lql") },
13991 { STRING_COMMA_LEN ("hql") },
13992 { STRING_COMMA_LEN ("lqh") },
13993 { STRING_COMMA_LEN ("hqh") }
13997 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13998 int sizeflag ATTRIBUTE_UNUSED
)
14000 unsigned int pclmul_type
;
14002 FETCH_DATA (the_info
, codep
+ 1);
14003 pclmul_type
= *codep
++ & 0xff;
14004 switch (pclmul_type
)
14015 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
14018 char *p
= mnemonicendp
- 3;
14023 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
14024 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
14028 /* We have a reserved extension byte. Output it directly. */
14029 scratchbuf
[0] = '$';
14030 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
14031 oappend_maybe_intel (scratchbuf
);
14032 scratchbuf
[0] = '\0';
14037 MOVSXD_Fixup (int bytemode
, int sizeflag
)
14039 /* Add proper suffix to "movsxd". */
14040 char *p
= mnemonicendp
;
14065 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14072 OP_E (bytemode
, sizeflag
);
14076 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
14079 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
14083 if ((rex
& REX_R
) != 0 || !vex
.r
)
14089 oappend (names_mask
[modrm
.reg
]);
14093 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
14095 if (modrm
.mod
== 3 && vex
.b
)
14098 case evex_rounding_64_mode
:
14099 if (address_mode
!= mode_64bit
)
14104 /* Fall through. */
14105 case evex_rounding_mode
:
14106 oappend (names_rounding
[vex
.ll
]);
14108 case evex_sae_mode
: