opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2017 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Ev_bnd { OP_E, v_bnd_mode }
 253 #define EvS { OP_E, v_swap_mode }
 254 #define Ed { OP_E, d_mode }
 255 #define Edq { OP_E, dq_mode }
 256 #define Edqw { OP_E, dqw_mode }
 257 #define Edqb { OP_E, dqb_mode }
 258 #define Edb { OP_E, db_mode }
 259 #define Edw { OP_E, dw_mode }
 260 #define Edqd { OP_E, dqd_mode }
 261 #define Eq { OP_E, q_mode }
 262 #define indirEv { OP_indirE, indir_v_mode }
 263 #define indirEp { OP_indirE, f_mode }
 264 #define stackEv { OP_E, stack_v_mode }
 265 #define Em { OP_E, m_mode }
 266 #define Ew { OP_E, w_mode }
 267 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 268 #define Ma { OP_M, a_mode }
 269 #define Mb { OP_M, b_mode }
 270 #define Md { OP_M, d_mode }
 271 #define Mo { OP_M, o_mode }
 272 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 273 #define Mq { OP_M, q_mode }
 274 #define Mx { OP_M, x_mode }
 275 #define Mxmm { OP_M, xmm_mode }
 276 #define Gb { OP_G, b_mode }
 277 #define Gbnd { OP_G, bnd_mode }
 278 #define Gv { OP_G, v_mode }
 279 #define Gd { OP_G, d_mode }
 280 #define Gdq { OP_G, dq_mode }
 281 #define Gm { OP_G, m_mode }
 282 #define Gw { OP_G, w_mode }
 283 #define Rd { OP_R, d_mode }
 284 #define Rdq { OP_R, dq_mode }
 285 #define Rm { OP_R, m_mode }
 286 #define Ib { OP_I, b_mode }
 287 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 288 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 289 #define Iv { OP_I, v_mode }
 290 #define sIv { OP_sI, v_mode }
 291 #define Iq { OP_I, q_mode }
 292 #define Iv64 { OP_I64, v_mode }
 293 #define Iw { OP_I, w_mode }
 294 #define I1 { OP_I, const_1_mode }
 295 #define Jb { OP_J, b_mode }
 296 #define Jv { OP_J, v_mode }
 297 #define Cm { OP_C, m_mode }
 298 #define Dm { OP_D, m_mode }
 299 #define Td { OP_T, d_mode }
 300 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 301
 302 #define RMeAX { OP_REG, eAX_reg }
 303 #define RMeBX { OP_REG, eBX_reg }
 304 #define RMeCX { OP_REG, eCX_reg }
 305 #define RMeDX { OP_REG, eDX_reg }
 306 #define RMeSP { OP_REG, eSP_reg }
 307 #define RMeBP { OP_REG, eBP_reg }
 308 #define RMeSI { OP_REG, eSI_reg }
 309 #define RMeDI { OP_REG, eDI_reg }
 310 #define RMrAX { OP_REG, rAX_reg }
 311 #define RMrBX { OP_REG, rBX_reg }
 312 #define RMrCX { OP_REG, rCX_reg }
 313 #define RMrDX { OP_REG, rDX_reg }
 314 #define RMrSP { OP_REG, rSP_reg }
 315 #define RMrBP { OP_REG, rBP_reg }
 316 #define RMrSI { OP_REG, rSI_reg }
 317 #define RMrDI { OP_REG, rDI_reg }
 318 #define RMAL { OP_REG, al_reg }
 319 #define RMCL { OP_REG, cl_reg }
 320 #define RMDL { OP_REG, dl_reg }
 321 #define RMBL { OP_REG, bl_reg }
 322 #define RMAH { OP_REG, ah_reg }
 323 #define RMCH { OP_REG, ch_reg }
 324 #define RMDH { OP_REG, dh_reg }
 325 #define RMBH { OP_REG, bh_reg }
 326 #define RMAX { OP_REG, ax_reg }
 327 #define RMDX { OP_REG, dx_reg }
 328
 329 #define eAX { OP_IMREG, eAX_reg }
 330 #define eBX { OP_IMREG, eBX_reg }
 331 #define eCX { OP_IMREG, eCX_reg }
 332 #define eDX { OP_IMREG, eDX_reg }
 333 #define eSP { OP_IMREG, eSP_reg }
 334 #define eBP { OP_IMREG, eBP_reg }
 335 #define eSI { OP_IMREG, eSI_reg }
 336 #define eDI { OP_IMREG, eDI_reg }
 337 #define AL { OP_IMREG, al_reg }
 338 #define CL { OP_IMREG, cl_reg }
 339 #define DL { OP_IMREG, dl_reg }
 340 #define BL { OP_IMREG, bl_reg }
 341 #define AH { OP_IMREG, ah_reg }
 342 #define CH { OP_IMREG, ch_reg }
 343 #define DH { OP_IMREG, dh_reg }
 344 #define BH { OP_IMREG, bh_reg }
 345 #define AX { OP_IMREG, ax_reg }
 346 #define DX { OP_IMREG, dx_reg }
 347 #define zAX { OP_IMREG, z_mode_ax_reg }
 348 #define indirDX { OP_IMREG, indir_dx_reg }
 349
 350 #define Sw { OP_SEG, w_mode }
 351 #define Sv { OP_SEG, v_mode }
 352 #define Ap { OP_DIR, 0 }
 353 #define Ob { OP_OFF64, b_mode }
 354 #define Ov { OP_OFF64, v_mode }
 355 #define Xb { OP_DSreg, eSI_reg }
 356 #define Xv { OP_DSreg, eSI_reg }
 357 #define Xz { OP_DSreg, eSI_reg }
 358 #define Yb { OP_ESreg, eDI_reg }
 359 #define Yv { OP_ESreg, eDI_reg }
 360 #define DSBX { OP_DSreg, eBX_reg }
 361
 362 #define es { OP_REG, es_reg }
 363 #define ss { OP_REG, ss_reg }
 364 #define cs { OP_REG, cs_reg }
 365 #define ds { OP_REG, ds_reg }
 366 #define fs { OP_REG, fs_reg }
 367 #define gs { OP_REG, gs_reg }
 368
 369 #define MX { OP_MMX, 0 }
 370 #define XM { OP_XMM, 0 }
 371 #define XMScalar { OP_XMM, scalar_mode }
 372 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 373 #define XMM { OP_XMM, xmm_mode }
 374 #define XMxmmq { OP_XMM, xmmq_mode }
 375 #define EM { OP_EM, v_mode }
 376 #define EMS { OP_EM, v_swap_mode }
 377 #define EMd { OP_EM, d_mode }
 378 #define EMx { OP_EM, x_mode }
 379 #define EXbScalar { OP_EX, b_scalar_mode }
 380 #define EXw { OP_EX, w_mode }
 381 #define EXwScalar { OP_EX, w_scalar_mode }
 382 #define EXd { OP_EX, d_mode }
 383 #define EXdScalar { OP_EX, d_scalar_mode }
 384 #define EXdS { OP_EX, d_swap_mode }
 385 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 386 #define EXq { OP_EX, q_mode }
 387 #define EXqScalar { OP_EX, q_scalar_mode }
 388 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 389 #define EXqS { OP_EX, q_swap_mode }
 390 #define EXx { OP_EX, x_mode }
 391 #define EXxS { OP_EX, x_swap_mode }
 392 #define EXxmm { OP_EX, xmm_mode }
 393 #define EXymm { OP_EX, ymm_mode }
 394 #define EXxmmq { OP_EX, xmmq_mode }
 395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 398 #define EXxmm_md { OP_EX, xmm_md_mode }
 399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 400 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 401 #define EXxmmdw { OP_EX, xmmdw_mode }
 402 #define EXxmmqd { OP_EX, xmmqd_mode }
 403 #define EXymmq { OP_EX, ymmq_mode }
 404 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 405 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 406 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 407 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 408 #define MS { OP_MS, v_mode }
 409 #define XS { OP_XS, v_mode }
 410 #define EMCq { OP_EMC, q_mode }
 411 #define MXC { OP_MXC, 0 }
 412 #define OPSUF { OP_3DNowSuffix, 0 }
 413 #define CMP { CMP_Fixup, 0 }
 414 #define XMM0 { XMM_Fixup, 0 }
 415 #define FXSAVE { FXSAVE_Fixup, 0 }
 416 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 417 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 418
 419 #define Vex { OP_VEX, vex_mode }
 420 #define VexScalar { OP_VEX, vex_scalar_mode }
 421 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 422 #define Vex128 { OP_VEX, vex128_mode }
 423 #define Vex256 { OP_VEX, vex256_mode }
 424 #define VexGdq { OP_VEX, dq_mode }
 425 #define VexI4 { VEXI4_Fixup, 0}
 426 #define EXdVex { OP_EX_Vex, d_mode }
 427 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 428 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 429 #define EXqVex { OP_EX_Vex, q_mode }
 430 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 431 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 432 #define EXVexW { OP_EX_VexW, x_mode }
 433 #define EXdVexW { OP_EX_VexW, d_mode }
 434 #define EXqVexW { OP_EX_VexW, q_mode }
 435 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 436 #define XMVex { OP_XMM_Vex, 0 }
 437 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 438 #define XMVexW { OP_XMM_VexW, 0 }
 439 #define XMVexI4 { OP_REG_VexI4, x_mode }
 440 #define PCLMUL { PCLMUL_Fixup, 0 }
 441 #define VZERO { VZERO_Fixup, 0 }
 442 #define VCMP { VCMP_Fixup, 0 }
 443 #define VPCMP { VPCMP_Fixup, 0 }
 444
 445 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 446 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 447
 448 #define XMask { OP_Mask, mask_mode }
 449 #define MaskG { OP_G, mask_mode }
 450 #define MaskE { OP_E, mask_mode }
 451 #define MaskBDE { OP_E, mask_bd_mode }
 452 #define MaskR { OP_R, mask_mode }
 453 #define MaskVex { OP_VEX, mask_mode }
 454
 455 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 456 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 457 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 458 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 459
 460 /* Used handle "rep" prefix for string instructions.  */
 461 #define Xbr { REP_Fixup, eSI_reg }
 462 #define Xvr { REP_Fixup, eSI_reg }
 463 #define Ybr { REP_Fixup, eDI_reg }
 464 #define Yvr { REP_Fixup, eDI_reg }
 465 #define Yzr { REP_Fixup, eDI_reg }
 466 #define indirDXr { REP_Fixup, indir_dx_reg }
 467 #define ALr { REP_Fixup, al_reg }
 468 #define eAXr { REP_Fixup, eAX_reg }
 469
 470 /* Used handle HLE prefix for lockable instructions.  */
 471 #define Ebh1 { HLE_Fixup1, b_mode }
 472 #define Evh1 { HLE_Fixup1, v_mode }
 473 #define Ebh2 { HLE_Fixup2, b_mode }
 474 #define Evh2 { HLE_Fixup2, v_mode }
 475 #define Ebh3 { HLE_Fixup3, b_mode }
 476 #define Evh3 { HLE_Fixup3, v_mode }
 477
 478 #define BND { BND_Fixup, 0 }
 479 #define NOTRACK { NOTRACK_Fixup, 0 }
 480
 481 #define cond_jump_flag { NULL, cond_jump_mode }
 482 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 483
 484 /* bits in sizeflag */
 485 #define SUFFIX_ALWAYS 4
 486 #define AFLAG 2
 487 #define DFLAG 1
 488
 489 enum
 490 {
 491   /* byte operand */
 492   b_mode = 1,
 493   /* byte operand with operand swapped */
 494   b_swap_mode,
 495   /* byte operand, sign extend like 'T' suffix */
 496   b_T_mode,
 497   /* operand size depends on prefixes */
 498   v_mode,
 499   /* operand size depends on prefixes with operand swapped */
 500   v_swap_mode,
 501   /* word operand */
 502   w_mode,
 503   /* double word operand  */
 504   d_mode,
 505   /* double word operand with operand swapped */
 506   d_swap_mode,
 507   /* quad word operand */
 508   q_mode,
 509   /* quad word operand with operand swapped */
 510   q_swap_mode,
 511   /* ten-byte operand */
 512   t_mode,
 513   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 514      broadcast enabled.  */
 515   x_mode,
 516   /* Similar to x_mode, but with different EVEX mem shifts.  */
 517   evex_x_gscat_mode,
 518   /* Similar to x_mode, but with disabled broadcast.  */
 519   evex_x_nobcst_mode,
 520   /* Similar to x_mode, but with operands swapped and disabled broadcast
 521      in EVEX.  */
 522   x_swap_mode,
 523   /* 16-byte XMM operand */
 524   xmm_mode,
 525   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 526      memory operand (depending on vector length).  Broadcast isn't
 527      allowed.  */
 528   xmmq_mode,
 529   /* Same as xmmq_mode, but broadcast is allowed.  */
 530   evex_half_bcst_xmmq_mode,
 531   /* XMM register or byte memory operand */
 532   xmm_mb_mode,
 533   /* XMM register or word memory operand */
 534   xmm_mw_mode,
 535   /* XMM register or double word memory operand */
 536   xmm_md_mode,
 537   /* XMM register or quad word memory operand */
 538   xmm_mq_mode,
 539   /* XMM register or double/quad word memory operand, depending on
 540      VEX.W.  */
 541   xmm_mdq_mode,
 542   /* 16-byte XMM, word, double word or quad word operand.  */
 543   xmmdw_mode,
 544   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 545   xmmqd_mode,
 546   /* 32-byte YMM operand */
 547   ymm_mode,
 548   /* quad word, ymmword or zmmword memory operand.  */
 549   ymmq_mode,
 550   /* 32-byte YMM or 16-byte word operand */
 551   ymmxmm_mode,
 552   /* d_mode in 32bit, q_mode in 64bit mode.  */
 553   m_mode,
 554   /* pair of v_mode operands */
 555   a_mode,
 556   cond_jump_mode,
 557   loop_jcxz_mode,
 558   v_bnd_mode,
 559   /* operand size depends on REX prefixes.  */
 560   dq_mode,
 561   /* registers like dq_mode, memory like w_mode.  */
 562   dqw_mode,
 563   bnd_mode,
 564   /* 4- or 6-byte pointer operand */
 565   f_mode,
 566   const_1_mode,
 567   /* v_mode for indirect branch opcodes.  */
 568   indir_v_mode,
 569   /* v_mode for stack-related opcodes.  */
 570   stack_v_mode,
 571   /* non-quad operand size depends on prefixes */
 572   z_mode,
 573   /* 16-byte operand */
 574   o_mode,
 575   /* registers like dq_mode, memory like b_mode.  */
 576   dqb_mode,
 577   /* registers like d_mode, memory like b_mode.  */
 578   db_mode,
 579   /* registers like d_mode, memory like w_mode.  */
 580   dw_mode,
 581   /* registers like dq_mode, memory like d_mode.  */
 582   dqd_mode,
 583   /* normal vex mode */
 584   vex_mode,
 585   /* 128bit vex mode */
 586   vex128_mode,
 587   /* 256bit vex mode */
 588   vex256_mode,
 589   /* operand size depends on the VEX.W bit.  */
 590   vex_w_dq_mode,
 591
 592   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 593   vex_vsib_d_w_dq_mode,
 594   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 595   vex_vsib_d_w_d_mode,
 596   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 597   vex_vsib_q_w_dq_mode,
 598   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 599   vex_vsib_q_w_d_mode,
 600
 601   /* scalar, ignore vector length.  */
 602   scalar_mode,
 603   /* like b_mode, ignore vector length.  */
 604   b_scalar_mode,
 605   /* like w_mode, ignore vector length.  */
 606   w_scalar_mode,
 607   /* like d_mode, ignore vector length.  */
 608   d_scalar_mode,
 609   /* like d_swap_mode, ignore vector length.  */
 610   d_scalar_swap_mode,
 611   /* like q_mode, ignore vector length.  */
 612   q_scalar_mode,
 613   /* like q_swap_mode, ignore vector length.  */
 614   q_scalar_swap_mode,
 615   /* like vex_mode, ignore vector length.  */
 616   vex_scalar_mode,
 617   /* like vex_w_dq_mode, ignore vector length.  */
 618   vex_scalar_w_dq_mode,
 619
 620   /* Static rounding.  */
 621   evex_rounding_mode,
 622   /* Supress all exceptions.  */
 623   evex_sae_mode,
 624
 625   /* Mask register operand.  */
 626   mask_mode,
 627   /* Mask register operand.  */
 628   mask_bd_mode,
 629
 630   es_reg,
 631   cs_reg,
 632   ss_reg,
 633   ds_reg,
 634   fs_reg,
 635   gs_reg,
 636
 637   eAX_reg,
 638   eCX_reg,
 639   eDX_reg,
 640   eBX_reg,
 641   eSP_reg,
 642   eBP_reg,
 643   eSI_reg,
 644   eDI_reg,
 645
 646   al_reg,
 647   cl_reg,
 648   dl_reg,
 649   bl_reg,
 650   ah_reg,
 651   ch_reg,
 652   dh_reg,
 653   bh_reg,
 654
 655   ax_reg,
 656   cx_reg,
 657   dx_reg,
 658   bx_reg,
 659   sp_reg,
 660   bp_reg,
 661   si_reg,
 662   di_reg,
 663
 664   rAX_reg,
 665   rCX_reg,
 666   rDX_reg,
 667   rBX_reg,
 668   rSP_reg,
 669   rBP_reg,
 670   rSI_reg,
 671   rDI_reg,
 672
 673   z_mode_ax_reg,
 674   indir_dx_reg
 675 };
 676
 677 enum
 678 {
 679   FLOATCODE = 1,
 680   USE_REG_TABLE,
 681   USE_MOD_TABLE,
 682   USE_RM_TABLE,
 683   USE_PREFIX_TABLE,
 684   USE_X86_64_TABLE,
 685   USE_3BYTE_TABLE,
 686   USE_XOP_8F_TABLE,
 687   USE_VEX_C4_TABLE,
 688   USE_VEX_C5_TABLE,
 689   USE_VEX_LEN_TABLE,
 690   USE_VEX_W_TABLE,
 691   USE_EVEX_TABLE
 692 };
 693
 694 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 695
 696 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 697 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 698 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 699 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 700 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 701 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 702 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 703 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 704 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 705 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 706 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 707 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 708 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 709 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 710 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 711
 712 enum
 713 {
 714   REG_80 = 0,
 715   REG_81,
 716   REG_83,
 717   REG_8F,
 718   REG_C0,
 719   REG_C1,
 720   REG_C6,
 721   REG_C7,
 722   REG_D0,
 723   REG_D1,
 724   REG_D2,
 725   REG_D3,
 726   REG_F6,
 727   REG_F7,
 728   REG_FE,
 729   REG_FF,
 730   REG_0F00,
 731   REG_0F01,
 732   REG_0F0D,
 733   REG_0F18,
 734   REG_0F1E_MOD_3,
 735   REG_0F71,
 736   REG_0F72,
 737   REG_0F73,
 738   REG_0FA6,
 739   REG_0FA7,
 740   REG_0FAE,
 741   REG_0FBA,
 742   REG_0FC7,
 743   REG_VEX_0F71,
 744   REG_VEX_0F72,
 745   REG_VEX_0F73,
 746   REG_VEX_0FAE,
 747   REG_VEX_0F38F3,
 748   REG_XOP_LWPCB,
 749   REG_XOP_LWP,
 750   REG_XOP_TBM_01,
 751   REG_XOP_TBM_02,
 752
 753   REG_EVEX_0F71,
 754   REG_EVEX_0F72,
 755   REG_EVEX_0F73,
 756   REG_EVEX_0F38C6,
 757   REG_EVEX_0F38C7
 758 };
 759
 760 enum
 761 {
 762   MOD_8D = 0,
 763   MOD_C6_REG_7,
 764   MOD_C7_REG_7,
 765   MOD_FF_REG_3,
 766   MOD_FF_REG_5,
 767   MOD_0F01_REG_0,
 768   MOD_0F01_REG_1,
 769   MOD_0F01_REG_2,
 770   MOD_0F01_REG_3,
 771   MOD_0F01_REG_5,
 772   MOD_0F01_REG_7,
 773   MOD_0F12_PREFIX_0,
 774   MOD_0F13,
 775   MOD_0F16_PREFIX_0,
 776   MOD_0F17,
 777   MOD_0F18_REG_0,
 778   MOD_0F18_REG_1,
 779   MOD_0F18_REG_2,
 780   MOD_0F18_REG_3,
 781   MOD_0F18_REG_4,
 782   MOD_0F18_REG_5,
 783   MOD_0F18_REG_6,
 784   MOD_0F18_REG_7,
 785   MOD_0F1A_PREFIX_0,
 786   MOD_0F1B_PREFIX_0,
 787   MOD_0F1B_PREFIX_1,
 788   MOD_0F1E_PREFIX_1,
 789   MOD_0F24,
 790   MOD_0F26,
 791   MOD_0F2B_PREFIX_0,
 792   MOD_0F2B_PREFIX_1,
 793   MOD_0F2B_PREFIX_2,
 794   MOD_0F2B_PREFIX_3,
 795   MOD_0F51,
 796   MOD_0F71_REG_2,
 797   MOD_0F71_REG_4,
 798   MOD_0F71_REG_6,
 799   MOD_0F72_REG_2,
 800   MOD_0F72_REG_4,
 801   MOD_0F72_REG_6,
 802   MOD_0F73_REG_2,
 803   MOD_0F73_REG_3,
 804   MOD_0F73_REG_6,
 805   MOD_0F73_REG_7,
 806   MOD_0FAE_REG_0,
 807   MOD_0FAE_REG_1,
 808   MOD_0FAE_REG_2,
 809   MOD_0FAE_REG_3,
 810   MOD_0FAE_REG_4,
 811   MOD_0FAE_REG_5,
 812   MOD_0FAE_REG_6,
 813   MOD_0FAE_REG_7,
 814   MOD_0FB2,
 815   MOD_0FB4,
 816   MOD_0FB5,
 817   MOD_0FC3,
 818   MOD_0FC7_REG_3,
 819   MOD_0FC7_REG_4,
 820   MOD_0FC7_REG_5,
 821   MOD_0FC7_REG_6,
 822   MOD_0FC7_REG_7,
 823   MOD_0FD7,
 824   MOD_0FE7_PREFIX_2,
 825   MOD_0FF0_PREFIX_3,
 826   MOD_0F382A_PREFIX_2,
 827   MOD_0F38F5_PREFIX_2,
 828   MOD_0F38F6_PREFIX_0,
 829   MOD_62_32BIT,
 830   MOD_C4_32BIT,
 831   MOD_C5_32BIT,
 832   MOD_VEX_0F12_PREFIX_0,
 833   MOD_VEX_0F13,
 834   MOD_VEX_0F16_PREFIX_0,
 835   MOD_VEX_0F17,
 836   MOD_VEX_0F2B,
 837   MOD_VEX_W_0_0F41_P_0_LEN_1,
 838   MOD_VEX_W_1_0F41_P_0_LEN_1,
 839   MOD_VEX_W_0_0F41_P_2_LEN_1,
 840   MOD_VEX_W_1_0F41_P_2_LEN_1,
 841   MOD_VEX_W_0_0F42_P_0_LEN_1,
 842   MOD_VEX_W_1_0F42_P_0_LEN_1,
 843   MOD_VEX_W_0_0F42_P_2_LEN_1,
 844   MOD_VEX_W_1_0F42_P_2_LEN_1,
 845   MOD_VEX_W_0_0F44_P_0_LEN_1,
 846   MOD_VEX_W_1_0F44_P_0_LEN_1,
 847   MOD_VEX_W_0_0F44_P_2_LEN_1,
 848   MOD_VEX_W_1_0F44_P_2_LEN_1,
 849   MOD_VEX_W_0_0F45_P_0_LEN_1,
 850   MOD_VEX_W_1_0F45_P_0_LEN_1,
 851   MOD_VEX_W_0_0F45_P_2_LEN_1,
 852   MOD_VEX_W_1_0F45_P_2_LEN_1,
 853   MOD_VEX_W_0_0F46_P_0_LEN_1,
 854   MOD_VEX_W_1_0F46_P_0_LEN_1,
 855   MOD_VEX_W_0_0F46_P_2_LEN_1,
 856   MOD_VEX_W_1_0F46_P_2_LEN_1,
 857   MOD_VEX_W_0_0F47_P_0_LEN_1,
 858   MOD_VEX_W_1_0F47_P_0_LEN_1,
 859   MOD_VEX_W_0_0F47_P_2_LEN_1,
 860   MOD_VEX_W_1_0F47_P_2_LEN_1,
 861   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 862   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 863   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 864   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 865   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 866   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 867   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 868   MOD_VEX_0F50,
 869   MOD_VEX_0F71_REG_2,
 870   MOD_VEX_0F71_REG_4,
 871   MOD_VEX_0F71_REG_6,
 872   MOD_VEX_0F72_REG_2,
 873   MOD_VEX_0F72_REG_4,
 874   MOD_VEX_0F72_REG_6,
 875   MOD_VEX_0F73_REG_2,
 876   MOD_VEX_0F73_REG_3,
 877   MOD_VEX_0F73_REG_6,
 878   MOD_VEX_0F73_REG_7,
 879   MOD_VEX_W_0_0F91_P_0_LEN_0,
 880   MOD_VEX_W_1_0F91_P_0_LEN_0,
 881   MOD_VEX_W_0_0F91_P_2_LEN_0,
 882   MOD_VEX_W_1_0F91_P_2_LEN_0,
 883   MOD_VEX_W_0_0F92_P_0_LEN_0,
 884   MOD_VEX_W_0_0F92_P_2_LEN_0,
 885   MOD_VEX_W_0_0F92_P_3_LEN_0,
 886   MOD_VEX_W_1_0F92_P_3_LEN_0,
 887   MOD_VEX_W_0_0F93_P_0_LEN_0,
 888   MOD_VEX_W_0_0F93_P_2_LEN_0,
 889   MOD_VEX_W_0_0F93_P_3_LEN_0,
 890   MOD_VEX_W_1_0F93_P_3_LEN_0,
 891   MOD_VEX_W_0_0F98_P_0_LEN_0,
 892   MOD_VEX_W_1_0F98_P_0_LEN_0,
 893   MOD_VEX_W_0_0F98_P_2_LEN_0,
 894   MOD_VEX_W_1_0F98_P_2_LEN_0,
 895   MOD_VEX_W_0_0F99_P_0_LEN_0,
 896   MOD_VEX_W_1_0F99_P_0_LEN_0,
 897   MOD_VEX_W_0_0F99_P_2_LEN_0,
 898   MOD_VEX_W_1_0F99_P_2_LEN_0,
 899   MOD_VEX_0FAE_REG_2,
 900   MOD_VEX_0FAE_REG_3,
 901   MOD_VEX_0FD7_PREFIX_2,
 902   MOD_VEX_0FE7_PREFIX_2,
 903   MOD_VEX_0FF0_PREFIX_3,
 904   MOD_VEX_0F381A_PREFIX_2,
 905   MOD_VEX_0F382A_PREFIX_2,
 906   MOD_VEX_0F382C_PREFIX_2,
 907   MOD_VEX_0F382D_PREFIX_2,
 908   MOD_VEX_0F382E_PREFIX_2,
 909   MOD_VEX_0F382F_PREFIX_2,
 910   MOD_VEX_0F385A_PREFIX_2,
 911   MOD_VEX_0F388C_PREFIX_2,
 912   MOD_VEX_0F388E_PREFIX_2,
 913   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 914   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 915   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 916   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 917   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 918   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 919   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 920   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 921
 922   MOD_EVEX_0F10_PREFIX_1,
 923   MOD_EVEX_0F10_PREFIX_3,
 924   MOD_EVEX_0F11_PREFIX_1,
 925   MOD_EVEX_0F11_PREFIX_3,
 926   MOD_EVEX_0F12_PREFIX_0,
 927   MOD_EVEX_0F16_PREFIX_0,
 928   MOD_EVEX_0F38C6_REG_1,
 929   MOD_EVEX_0F38C6_REG_2,
 930   MOD_EVEX_0F38C6_REG_5,
 931   MOD_EVEX_0F38C6_REG_6,
 932   MOD_EVEX_0F38C7_REG_1,
 933   MOD_EVEX_0F38C7_REG_2,
 934   MOD_EVEX_0F38C7_REG_5,
 935   MOD_EVEX_0F38C7_REG_6
 936 };
 937
 938 enum
 939 {
 940   RM_C6_REG_7 = 0,
 941   RM_C7_REG_7,
 942   RM_0F01_REG_0,
 943   RM_0F01_REG_1,
 944   RM_0F01_REG_2,
 945   RM_0F01_REG_3,
 946   RM_0F01_REG_5,
 947   RM_0F01_REG_7,
 948   RM_0F1E_MOD_3_REG_7,
 949   RM_0FAE_REG_6,
 950   RM_0FAE_REG_7
 951 };
 952
 953 enum
 954 {
 955   PREFIX_90 = 0,
 956   PREFIX_MOD_0_0F01_REG_5,
 957   PREFIX_MOD_3_0F01_REG_5_RM_0,
 958   PREFIX_MOD_3_0F01_REG_5_RM_2,
 959   PREFIX_0F10,
 960   PREFIX_0F11,
 961   PREFIX_0F12,
 962   PREFIX_0F16,
 963   PREFIX_0F1A,
 964   PREFIX_0F1B,
 965   PREFIX_0F1E,
 966   PREFIX_0F2A,
 967   PREFIX_0F2B,
 968   PREFIX_0F2C,
 969   PREFIX_0F2D,
 970   PREFIX_0F2E,
 971   PREFIX_0F2F,
 972   PREFIX_0F51,
 973   PREFIX_0F52,
 974   PREFIX_0F53,
 975   PREFIX_0F58,
 976   PREFIX_0F59,
 977   PREFIX_0F5A,
 978   PREFIX_0F5B,
 979   PREFIX_0F5C,
 980   PREFIX_0F5D,
 981   PREFIX_0F5E,
 982   PREFIX_0F5F,
 983   PREFIX_0F60,
 984   PREFIX_0F61,
 985   PREFIX_0F62,
 986   PREFIX_0F6C,
 987   PREFIX_0F6D,
 988   PREFIX_0F6F,
 989   PREFIX_0F70,
 990   PREFIX_0F73_REG_3,
 991   PREFIX_0F73_REG_7,
 992   PREFIX_0F78,
 993   PREFIX_0F79,
 994   PREFIX_0F7C,
 995   PREFIX_0F7D,
 996   PREFIX_0F7E,
 997   PREFIX_0F7F,
 998   PREFIX_0FAE_REG_0,
 999   PREFIX_0FAE_REG_1,
1000   PREFIX_0FAE_REG_2,
1001   PREFIX_0FAE_REG_3,
1002   PREFIX_MOD_0_0FAE_REG_4,
1003   PREFIX_MOD_3_0FAE_REG_4,
1004   PREFIX_MOD_0_0FAE_REG_5,
1005   PREFIX_MOD_3_0FAE_REG_5,
1006   PREFIX_0FAE_REG_6,
1007   PREFIX_0FAE_REG_7,
1008   PREFIX_0FB8,
1009   PREFIX_0FBC,
1010   PREFIX_0FBD,
1011   PREFIX_0FC2,
1012   PREFIX_MOD_0_0FC3,
1013   PREFIX_MOD_0_0FC7_REG_6,
1014   PREFIX_MOD_3_0FC7_REG_6,
1015   PREFIX_MOD_3_0FC7_REG_7,
1016   PREFIX_0FD0,
1017   PREFIX_0FD6,
1018   PREFIX_0FE6,
1019   PREFIX_0FE7,
1020   PREFIX_0FF0,
1021   PREFIX_0FF7,
1022   PREFIX_0F3810,
1023   PREFIX_0F3814,
1024   PREFIX_0F3815,
1025   PREFIX_0F3817,
1026   PREFIX_0F3820,
1027   PREFIX_0F3821,
1028   PREFIX_0F3822,
1029   PREFIX_0F3823,
1030   PREFIX_0F3824,
1031   PREFIX_0F3825,
1032   PREFIX_0F3828,
1033   PREFIX_0F3829,
1034   PREFIX_0F382A,
1035   PREFIX_0F382B,
1036   PREFIX_0F3830,
1037   PREFIX_0F3831,
1038   PREFIX_0F3832,
1039   PREFIX_0F3833,
1040   PREFIX_0F3834,
1041   PREFIX_0F3835,
1042   PREFIX_0F3837,
1043   PREFIX_0F3838,
1044   PREFIX_0F3839,
1045   PREFIX_0F383A,
1046   PREFIX_0F383B,
1047   PREFIX_0F383C,
1048   PREFIX_0F383D,
1049   PREFIX_0F383E,
1050   PREFIX_0F383F,
1051   PREFIX_0F3840,
1052   PREFIX_0F3841,
1053   PREFIX_0F3880,
1054   PREFIX_0F3881,
1055   PREFIX_0F3882,
1056   PREFIX_0F38C8,
1057   PREFIX_0F38C9,
1058   PREFIX_0F38CA,
1059   PREFIX_0F38CB,
1060   PREFIX_0F38CC,
1061   PREFIX_0F38CD,
1062   PREFIX_0F38CF,
1063   PREFIX_0F38DB,
1064   PREFIX_0F38DC,
1065   PREFIX_0F38DD,
1066   PREFIX_0F38DE,
1067   PREFIX_0F38DF,
1068   PREFIX_0F38F0,
1069   PREFIX_0F38F1,
1070   PREFIX_0F38F5,
1071   PREFIX_0F38F6,
1072   PREFIX_0F3A08,
1073   PREFIX_0F3A09,
1074   PREFIX_0F3A0A,
1075   PREFIX_0F3A0B,
1076   PREFIX_0F3A0C,
1077   PREFIX_0F3A0D,
1078   PREFIX_0F3A0E,
1079   PREFIX_0F3A14,
1080   PREFIX_0F3A15,
1081   PREFIX_0F3A16,
1082   PREFIX_0F3A17,
1083   PREFIX_0F3A20,
1084   PREFIX_0F3A21,
1085   PREFIX_0F3A22,
1086   PREFIX_0F3A40,
1087   PREFIX_0F3A41,
1088   PREFIX_0F3A42,
1089   PREFIX_0F3A44,
1090   PREFIX_0F3A60,
1091   PREFIX_0F3A61,
1092   PREFIX_0F3A62,
1093   PREFIX_0F3A63,
1094   PREFIX_0F3ACC,
1095   PREFIX_0F3ACE,
1096   PREFIX_0F3ACF,
1097   PREFIX_0F3ADF,
1098   PREFIX_VEX_0F10,
1099   PREFIX_VEX_0F11,
1100   PREFIX_VEX_0F12,
1101   PREFIX_VEX_0F16,
1102   PREFIX_VEX_0F2A,
1103   PREFIX_VEX_0F2C,
1104   PREFIX_VEX_0F2D,
1105   PREFIX_VEX_0F2E,
1106   PREFIX_VEX_0F2F,
1107   PREFIX_VEX_0F41,
1108   PREFIX_VEX_0F42,
1109   PREFIX_VEX_0F44,
1110   PREFIX_VEX_0F45,
1111   PREFIX_VEX_0F46,
1112   PREFIX_VEX_0F47,
1113   PREFIX_VEX_0F4A,
1114   PREFIX_VEX_0F4B,
1115   PREFIX_VEX_0F51,
1116   PREFIX_VEX_0F52,
1117   PREFIX_VEX_0F53,
1118   PREFIX_VEX_0F58,
1119   PREFIX_VEX_0F59,
1120   PREFIX_VEX_0F5A,
1121   PREFIX_VEX_0F5B,
1122   PREFIX_VEX_0F5C,
1123   PREFIX_VEX_0F5D,
1124   PREFIX_VEX_0F5E,
1125   PREFIX_VEX_0F5F,
1126   PREFIX_VEX_0F60,
1127   PREFIX_VEX_0F61,
1128   PREFIX_VEX_0F62,
1129   PREFIX_VEX_0F63,
1130   PREFIX_VEX_0F64,
1131   PREFIX_VEX_0F65,
1132   PREFIX_VEX_0F66,
1133   PREFIX_VEX_0F67,
1134   PREFIX_VEX_0F68,
1135   PREFIX_VEX_0F69,
1136   PREFIX_VEX_0F6A,
1137   PREFIX_VEX_0F6B,
1138   PREFIX_VEX_0F6C,
1139   PREFIX_VEX_0F6D,
1140   PREFIX_VEX_0F6E,
1141   PREFIX_VEX_0F6F,
1142   PREFIX_VEX_0F70,
1143   PREFIX_VEX_0F71_REG_2,
1144   PREFIX_VEX_0F71_REG_4,
1145   PREFIX_VEX_0F71_REG_6,
1146   PREFIX_VEX_0F72_REG_2,
1147   PREFIX_VEX_0F72_REG_4,
1148   PREFIX_VEX_0F72_REG_6,
1149   PREFIX_VEX_0F73_REG_2,
1150   PREFIX_VEX_0F73_REG_3,
1151   PREFIX_VEX_0F73_REG_6,
1152   PREFIX_VEX_0F73_REG_7,
1153   PREFIX_VEX_0F74,
1154   PREFIX_VEX_0F75,
1155   PREFIX_VEX_0F76,
1156   PREFIX_VEX_0F77,
1157   PREFIX_VEX_0F7C,
1158   PREFIX_VEX_0F7D,
1159   PREFIX_VEX_0F7E,
1160   PREFIX_VEX_0F7F,
1161   PREFIX_VEX_0F90,
1162   PREFIX_VEX_0F91,
1163   PREFIX_VEX_0F92,
1164   PREFIX_VEX_0F93,
1165   PREFIX_VEX_0F98,
1166   PREFIX_VEX_0F99,
1167   PREFIX_VEX_0FC2,
1168   PREFIX_VEX_0FC4,
1169   PREFIX_VEX_0FC5,
1170   PREFIX_VEX_0FD0,
1171   PREFIX_VEX_0FD1,
1172   PREFIX_VEX_0FD2,
1173   PREFIX_VEX_0FD3,
1174   PREFIX_VEX_0FD4,
1175   PREFIX_VEX_0FD5,
1176   PREFIX_VEX_0FD6,
1177   PREFIX_VEX_0FD7,
1178   PREFIX_VEX_0FD8,
1179   PREFIX_VEX_0FD9,
1180   PREFIX_VEX_0FDA,
1181   PREFIX_VEX_0FDB,
1182   PREFIX_VEX_0FDC,
1183   PREFIX_VEX_0FDD,
1184   PREFIX_VEX_0FDE,
1185   PREFIX_VEX_0FDF,
1186   PREFIX_VEX_0FE0,
1187   PREFIX_VEX_0FE1,
1188   PREFIX_VEX_0FE2,
1189   PREFIX_VEX_0FE3,
1190   PREFIX_VEX_0FE4,
1191   PREFIX_VEX_0FE5,
1192   PREFIX_VEX_0FE6,
1193   PREFIX_VEX_0FE7,
1194   PREFIX_VEX_0FE8,
1195   PREFIX_VEX_0FE9,
1196   PREFIX_VEX_0FEA,
1197   PREFIX_VEX_0FEB,
1198   PREFIX_VEX_0FEC,
1199   PREFIX_VEX_0FED,
1200   PREFIX_VEX_0FEE,
1201   PREFIX_VEX_0FEF,
1202   PREFIX_VEX_0FF0,
1203   PREFIX_VEX_0FF1,
1204   PREFIX_VEX_0FF2,
1205   PREFIX_VEX_0FF3,
1206   PREFIX_VEX_0FF4,
1207   PREFIX_VEX_0FF5,
1208   PREFIX_VEX_0FF6,
1209   PREFIX_VEX_0FF7,
1210   PREFIX_VEX_0FF8,
1211   PREFIX_VEX_0FF9,
1212   PREFIX_VEX_0FFA,
1213   PREFIX_VEX_0FFB,
1214   PREFIX_VEX_0FFC,
1215   PREFIX_VEX_0FFD,
1216   PREFIX_VEX_0FFE,
1217   PREFIX_VEX_0F3800,
1218   PREFIX_VEX_0F3801,
1219   PREFIX_VEX_0F3802,
1220   PREFIX_VEX_0F3803,
1221   PREFIX_VEX_0F3804,
1222   PREFIX_VEX_0F3805,
1223   PREFIX_VEX_0F3806,
1224   PREFIX_VEX_0F3807,
1225   PREFIX_VEX_0F3808,
1226   PREFIX_VEX_0F3809,
1227   PREFIX_VEX_0F380A,
1228   PREFIX_VEX_0F380B,
1229   PREFIX_VEX_0F380C,
1230   PREFIX_VEX_0F380D,
1231   PREFIX_VEX_0F380E,
1232   PREFIX_VEX_0F380F,
1233   PREFIX_VEX_0F3813,
1234   PREFIX_VEX_0F3816,
1235   PREFIX_VEX_0F3817,
1236   PREFIX_VEX_0F3818,
1237   PREFIX_VEX_0F3819,
1238   PREFIX_VEX_0F381A,
1239   PREFIX_VEX_0F381C,
1240   PREFIX_VEX_0F381D,
1241   PREFIX_VEX_0F381E,
1242   PREFIX_VEX_0F3820,
1243   PREFIX_VEX_0F3821,
1244   PREFIX_VEX_0F3822,
1245   PREFIX_VEX_0F3823,
1246   PREFIX_VEX_0F3824,
1247   PREFIX_VEX_0F3825,
1248   PREFIX_VEX_0F3828,
1249   PREFIX_VEX_0F3829,
1250   PREFIX_VEX_0F382A,
1251   PREFIX_VEX_0F382B,
1252   PREFIX_VEX_0F382C,
1253   PREFIX_VEX_0F382D,
1254   PREFIX_VEX_0F382E,
1255   PREFIX_VEX_0F382F,
1256   PREFIX_VEX_0F3830,
1257   PREFIX_VEX_0F3831,
1258   PREFIX_VEX_0F3832,
1259   PREFIX_VEX_0F3833,
1260   PREFIX_VEX_0F3834,
1261   PREFIX_VEX_0F3835,
1262   PREFIX_VEX_0F3836,
1263   PREFIX_VEX_0F3837,
1264   PREFIX_VEX_0F3838,
1265   PREFIX_VEX_0F3839,
1266   PREFIX_VEX_0F383A,
1267   PREFIX_VEX_0F383B,
1268   PREFIX_VEX_0F383C,
1269   PREFIX_VEX_0F383D,
1270   PREFIX_VEX_0F383E,
1271   PREFIX_VEX_0F383F,
1272   PREFIX_VEX_0F3840,
1273   PREFIX_VEX_0F3841,
1274   PREFIX_VEX_0F3845,
1275   PREFIX_VEX_0F3846,
1276   PREFIX_VEX_0F3847,
1277   PREFIX_VEX_0F3858,
1278   PREFIX_VEX_0F3859,
1279   PREFIX_VEX_0F385A,
1280   PREFIX_VEX_0F3878,
1281   PREFIX_VEX_0F3879,
1282   PREFIX_VEX_0F388C,
1283   PREFIX_VEX_0F388E,
1284   PREFIX_VEX_0F3890,
1285   PREFIX_VEX_0F3891,
1286   PREFIX_VEX_0F3892,
1287   PREFIX_VEX_0F3893,
1288   PREFIX_VEX_0F3896,
1289   PREFIX_VEX_0F3897,
1290   PREFIX_VEX_0F3898,
1291   PREFIX_VEX_0F3899,
1292   PREFIX_VEX_0F389A,
1293   PREFIX_VEX_0F389B,
1294   PREFIX_VEX_0F389C,
1295   PREFIX_VEX_0F389D,
1296   PREFIX_VEX_0F389E,
1297   PREFIX_VEX_0F389F,
1298   PREFIX_VEX_0F38A6,
1299   PREFIX_VEX_0F38A7,
1300   PREFIX_VEX_0F38A8,
1301   PREFIX_VEX_0F38A9,
1302   PREFIX_VEX_0F38AA,
1303   PREFIX_VEX_0F38AB,
1304   PREFIX_VEX_0F38AC,
1305   PREFIX_VEX_0F38AD,
1306   PREFIX_VEX_0F38AE,
1307   PREFIX_VEX_0F38AF,
1308   PREFIX_VEX_0F38B6,
1309   PREFIX_VEX_0F38B7,
1310   PREFIX_VEX_0F38B8,
1311   PREFIX_VEX_0F38B9,
1312   PREFIX_VEX_0F38BA,
1313   PREFIX_VEX_0F38BB,
1314   PREFIX_VEX_0F38BC,
1315   PREFIX_VEX_0F38BD,
1316   PREFIX_VEX_0F38BE,
1317   PREFIX_VEX_0F38BF,
1318   PREFIX_VEX_0F38CF,
1319   PREFIX_VEX_0F38DB,
1320   PREFIX_VEX_0F38DC,
1321   PREFIX_VEX_0F38DD,
1322   PREFIX_VEX_0F38DE,
1323   PREFIX_VEX_0F38DF,
1324   PREFIX_VEX_0F38F2,
1325   PREFIX_VEX_0F38F3_REG_1,
1326   PREFIX_VEX_0F38F3_REG_2,
1327   PREFIX_VEX_0F38F3_REG_3,
1328   PREFIX_VEX_0F38F5,
1329   PREFIX_VEX_0F38F6,
1330   PREFIX_VEX_0F38F7,
1331   PREFIX_VEX_0F3A00,
1332   PREFIX_VEX_0F3A01,
1333   PREFIX_VEX_0F3A02,
1334   PREFIX_VEX_0F3A04,
1335   PREFIX_VEX_0F3A05,
1336   PREFIX_VEX_0F3A06,
1337   PREFIX_VEX_0F3A08,
1338   PREFIX_VEX_0F3A09,
1339   PREFIX_VEX_0F3A0A,
1340   PREFIX_VEX_0F3A0B,
1341   PREFIX_VEX_0F3A0C,
1342   PREFIX_VEX_0F3A0D,
1343   PREFIX_VEX_0F3A0E,
1344   PREFIX_VEX_0F3A0F,
1345   PREFIX_VEX_0F3A14,
1346   PREFIX_VEX_0F3A15,
1347   PREFIX_VEX_0F3A16,
1348   PREFIX_VEX_0F3A17,
1349   PREFIX_VEX_0F3A18,
1350   PREFIX_VEX_0F3A19,
1351   PREFIX_VEX_0F3A1D,
1352   PREFIX_VEX_0F3A20,
1353   PREFIX_VEX_0F3A21,
1354   PREFIX_VEX_0F3A22,
1355   PREFIX_VEX_0F3A30,
1356   PREFIX_VEX_0F3A31,
1357   PREFIX_VEX_0F3A32,
1358   PREFIX_VEX_0F3A33,
1359   PREFIX_VEX_0F3A38,
1360   PREFIX_VEX_0F3A39,
1361   PREFIX_VEX_0F3A40,
1362   PREFIX_VEX_0F3A41,
1363   PREFIX_VEX_0F3A42,
1364   PREFIX_VEX_0F3A44,
1365   PREFIX_VEX_0F3A46,
1366   PREFIX_VEX_0F3A48,
1367   PREFIX_VEX_0F3A49,
1368   PREFIX_VEX_0F3A4A,
1369   PREFIX_VEX_0F3A4B,
1370   PREFIX_VEX_0F3A4C,
1371   PREFIX_VEX_0F3A5C,
1372   PREFIX_VEX_0F3A5D,
1373   PREFIX_VEX_0F3A5E,
1374   PREFIX_VEX_0F3A5F,
1375   PREFIX_VEX_0F3A60,
1376   PREFIX_VEX_0F3A61,
1377   PREFIX_VEX_0F3A62,
1378   PREFIX_VEX_0F3A63,
1379   PREFIX_VEX_0F3A68,
1380   PREFIX_VEX_0F3A69,
1381   PREFIX_VEX_0F3A6A,
1382   PREFIX_VEX_0F3A6B,
1383   PREFIX_VEX_0F3A6C,
1384   PREFIX_VEX_0F3A6D,
1385   PREFIX_VEX_0F3A6E,
1386   PREFIX_VEX_0F3A6F,
1387   PREFIX_VEX_0F3A78,
1388   PREFIX_VEX_0F3A79,
1389   PREFIX_VEX_0F3A7A,
1390   PREFIX_VEX_0F3A7B,
1391   PREFIX_VEX_0F3A7C,
1392   PREFIX_VEX_0F3A7D,
1393   PREFIX_VEX_0F3A7E,
1394   PREFIX_VEX_0F3A7F,
1395   PREFIX_VEX_0F3ACE,
1396   PREFIX_VEX_0F3ACF,
1397   PREFIX_VEX_0F3ADF,
1398   PREFIX_VEX_0F3AF0,
1399
1400   PREFIX_EVEX_0F10,
1401   PREFIX_EVEX_0F11,
1402   PREFIX_EVEX_0F12,
1403   PREFIX_EVEX_0F13,
1404   PREFIX_EVEX_0F14,
1405   PREFIX_EVEX_0F15,
1406   PREFIX_EVEX_0F16,
1407   PREFIX_EVEX_0F17,
1408   PREFIX_EVEX_0F28,
1409   PREFIX_EVEX_0F29,
1410   PREFIX_EVEX_0F2A,
1411   PREFIX_EVEX_0F2B,
1412   PREFIX_EVEX_0F2C,
1413   PREFIX_EVEX_0F2D,
1414   PREFIX_EVEX_0F2E,
1415   PREFIX_EVEX_0F2F,
1416   PREFIX_EVEX_0F51,
1417   PREFIX_EVEX_0F54,
1418   PREFIX_EVEX_0F55,
1419   PREFIX_EVEX_0F56,
1420   PREFIX_EVEX_0F57,
1421   PREFIX_EVEX_0F58,
1422   PREFIX_EVEX_0F59,
1423   PREFIX_EVEX_0F5A,
1424   PREFIX_EVEX_0F5B,
1425   PREFIX_EVEX_0F5C,
1426   PREFIX_EVEX_0F5D,
1427   PREFIX_EVEX_0F5E,
1428   PREFIX_EVEX_0F5F,
1429   PREFIX_EVEX_0F60,
1430   PREFIX_EVEX_0F61,
1431   PREFIX_EVEX_0F62,
1432   PREFIX_EVEX_0F63,
1433   PREFIX_EVEX_0F64,
1434   PREFIX_EVEX_0F65,
1435   PREFIX_EVEX_0F66,
1436   PREFIX_EVEX_0F67,
1437   PREFIX_EVEX_0F68,
1438   PREFIX_EVEX_0F69,
1439   PREFIX_EVEX_0F6A,
1440   PREFIX_EVEX_0F6B,
1441   PREFIX_EVEX_0F6C,
1442   PREFIX_EVEX_0F6D,
1443   PREFIX_EVEX_0F6E,
1444   PREFIX_EVEX_0F6F,
1445   PREFIX_EVEX_0F70,
1446   PREFIX_EVEX_0F71_REG_2,
1447   PREFIX_EVEX_0F71_REG_4,
1448   PREFIX_EVEX_0F71_REG_6,
1449   PREFIX_EVEX_0F72_REG_0,
1450   PREFIX_EVEX_0F72_REG_1,
1451   PREFIX_EVEX_0F72_REG_2,
1452   PREFIX_EVEX_0F72_REG_4,
1453   PREFIX_EVEX_0F72_REG_6,
1454   PREFIX_EVEX_0F73_REG_2,
1455   PREFIX_EVEX_0F73_REG_3,
1456   PREFIX_EVEX_0F73_REG_6,
1457   PREFIX_EVEX_0F73_REG_7,
1458   PREFIX_EVEX_0F74,
1459   PREFIX_EVEX_0F75,
1460   PREFIX_EVEX_0F76,
1461   PREFIX_EVEX_0F78,
1462   PREFIX_EVEX_0F79,
1463   PREFIX_EVEX_0F7A,
1464   PREFIX_EVEX_0F7B,
1465   PREFIX_EVEX_0F7E,
1466   PREFIX_EVEX_0F7F,
1467   PREFIX_EVEX_0FC2,
1468   PREFIX_EVEX_0FC4,
1469   PREFIX_EVEX_0FC5,
1470   PREFIX_EVEX_0FC6,
1471   PREFIX_EVEX_0FD1,
1472   PREFIX_EVEX_0FD2,
1473   PREFIX_EVEX_0FD3,
1474   PREFIX_EVEX_0FD4,
1475   PREFIX_EVEX_0FD5,
1476   PREFIX_EVEX_0FD6,
1477   PREFIX_EVEX_0FD8,
1478   PREFIX_EVEX_0FD9,
1479   PREFIX_EVEX_0FDA,
1480   PREFIX_EVEX_0FDB,
1481   PREFIX_EVEX_0FDC,
1482   PREFIX_EVEX_0FDD,
1483   PREFIX_EVEX_0FDE,
1484   PREFIX_EVEX_0FDF,
1485   PREFIX_EVEX_0FE0,
1486   PREFIX_EVEX_0FE1,
1487   PREFIX_EVEX_0FE2,
1488   PREFIX_EVEX_0FE3,
1489   PREFIX_EVEX_0FE4,
1490   PREFIX_EVEX_0FE5,
1491   PREFIX_EVEX_0FE6,
1492   PREFIX_EVEX_0FE7,
1493   PREFIX_EVEX_0FE8,
1494   PREFIX_EVEX_0FE9,
1495   PREFIX_EVEX_0FEA,
1496   PREFIX_EVEX_0FEB,
1497   PREFIX_EVEX_0FEC,
1498   PREFIX_EVEX_0FED,
1499   PREFIX_EVEX_0FEE,
1500   PREFIX_EVEX_0FEF,
1501   PREFIX_EVEX_0FF1,
1502   PREFIX_EVEX_0FF2,
1503   PREFIX_EVEX_0FF3,
1504   PREFIX_EVEX_0FF4,
1505   PREFIX_EVEX_0FF5,
1506   PREFIX_EVEX_0FF6,
1507   PREFIX_EVEX_0FF8,
1508   PREFIX_EVEX_0FF9,
1509   PREFIX_EVEX_0FFA,
1510   PREFIX_EVEX_0FFB,
1511   PREFIX_EVEX_0FFC,
1512   PREFIX_EVEX_0FFD,
1513   PREFIX_EVEX_0FFE,
1514   PREFIX_EVEX_0F3800,
1515   PREFIX_EVEX_0F3804,
1516   PREFIX_EVEX_0F380B,
1517   PREFIX_EVEX_0F380C,
1518   PREFIX_EVEX_0F380D,
1519   PREFIX_EVEX_0F3810,
1520   PREFIX_EVEX_0F3811,
1521   PREFIX_EVEX_0F3812,
1522   PREFIX_EVEX_0F3813,
1523   PREFIX_EVEX_0F3814,
1524   PREFIX_EVEX_0F3815,
1525   PREFIX_EVEX_0F3816,
1526   PREFIX_EVEX_0F3818,
1527   PREFIX_EVEX_0F3819,
1528   PREFIX_EVEX_0F381A,
1529   PREFIX_EVEX_0F381B,
1530   PREFIX_EVEX_0F381C,
1531   PREFIX_EVEX_0F381D,
1532   PREFIX_EVEX_0F381E,
1533   PREFIX_EVEX_0F381F,
1534   PREFIX_EVEX_0F3820,
1535   PREFIX_EVEX_0F3821,
1536   PREFIX_EVEX_0F3822,
1537   PREFIX_EVEX_0F3823,
1538   PREFIX_EVEX_0F3824,
1539   PREFIX_EVEX_0F3825,
1540   PREFIX_EVEX_0F3826,
1541   PREFIX_EVEX_0F3827,
1542   PREFIX_EVEX_0F3828,
1543   PREFIX_EVEX_0F3829,
1544   PREFIX_EVEX_0F382A,
1545   PREFIX_EVEX_0F382B,
1546   PREFIX_EVEX_0F382C,
1547   PREFIX_EVEX_0F382D,
1548   PREFIX_EVEX_0F3830,
1549   PREFIX_EVEX_0F3831,
1550   PREFIX_EVEX_0F3832,
1551   PREFIX_EVEX_0F3833,
1552   PREFIX_EVEX_0F3834,
1553   PREFIX_EVEX_0F3835,
1554   PREFIX_EVEX_0F3836,
1555   PREFIX_EVEX_0F3837,
1556   PREFIX_EVEX_0F3838,
1557   PREFIX_EVEX_0F3839,
1558   PREFIX_EVEX_0F383A,
1559   PREFIX_EVEX_0F383B,
1560   PREFIX_EVEX_0F383C,
1561   PREFIX_EVEX_0F383D,
1562   PREFIX_EVEX_0F383E,
1563   PREFIX_EVEX_0F383F,
1564   PREFIX_EVEX_0F3840,
1565   PREFIX_EVEX_0F3842,
1566   PREFIX_EVEX_0F3843,
1567   PREFIX_EVEX_0F3844,
1568   PREFIX_EVEX_0F3845,
1569   PREFIX_EVEX_0F3846,
1570   PREFIX_EVEX_0F3847,
1571   PREFIX_EVEX_0F384C,
1572   PREFIX_EVEX_0F384D,
1573   PREFIX_EVEX_0F384E,
1574   PREFIX_EVEX_0F384F,
1575   PREFIX_EVEX_0F3850,
1576   PREFIX_EVEX_0F3851,
1577   PREFIX_EVEX_0F3852,
1578   PREFIX_EVEX_0F3853,
1579   PREFIX_EVEX_0F3854,
1580   PREFIX_EVEX_0F3855,
1581   PREFIX_EVEX_0F3858,
1582   PREFIX_EVEX_0F3859,
1583   PREFIX_EVEX_0F385A,
1584   PREFIX_EVEX_0F385B,
1585   PREFIX_EVEX_0F3862,
1586   PREFIX_EVEX_0F3863,
1587   PREFIX_EVEX_0F3864,
1588   PREFIX_EVEX_0F3865,
1589   PREFIX_EVEX_0F3866,
1590   PREFIX_EVEX_0F3870,
1591   PREFIX_EVEX_0F3871,
1592   PREFIX_EVEX_0F3872,
1593   PREFIX_EVEX_0F3873,
1594   PREFIX_EVEX_0F3875,
1595   PREFIX_EVEX_0F3876,
1596   PREFIX_EVEX_0F3877,
1597   PREFIX_EVEX_0F3878,
1598   PREFIX_EVEX_0F3879,
1599   PREFIX_EVEX_0F387A,
1600   PREFIX_EVEX_0F387B,
1601   PREFIX_EVEX_0F387C,
1602   PREFIX_EVEX_0F387D,
1603   PREFIX_EVEX_0F387E,
1604   PREFIX_EVEX_0F387F,
1605   PREFIX_EVEX_0F3883,
1606   PREFIX_EVEX_0F3888,
1607   PREFIX_EVEX_0F3889,
1608   PREFIX_EVEX_0F388A,
1609   PREFIX_EVEX_0F388B,
1610   PREFIX_EVEX_0F388D,
1611   PREFIX_EVEX_0F388F,
1612   PREFIX_EVEX_0F3890,
1613   PREFIX_EVEX_0F3891,
1614   PREFIX_EVEX_0F3892,
1615   PREFIX_EVEX_0F3893,
1616   PREFIX_EVEX_0F3896,
1617   PREFIX_EVEX_0F3897,
1618   PREFIX_EVEX_0F3898,
1619   PREFIX_EVEX_0F3899,
1620   PREFIX_EVEX_0F389A,
1621   PREFIX_EVEX_0F389B,
1622   PREFIX_EVEX_0F389C,
1623   PREFIX_EVEX_0F389D,
1624   PREFIX_EVEX_0F389E,
1625   PREFIX_EVEX_0F389F,
1626   PREFIX_EVEX_0F38A0,
1627   PREFIX_EVEX_0F38A1,
1628   PREFIX_EVEX_0F38A2,
1629   PREFIX_EVEX_0F38A3,
1630   PREFIX_EVEX_0F38A6,
1631   PREFIX_EVEX_0F38A7,
1632   PREFIX_EVEX_0F38A8,
1633   PREFIX_EVEX_0F38A9,
1634   PREFIX_EVEX_0F38AA,
1635   PREFIX_EVEX_0F38AB,
1636   PREFIX_EVEX_0F38AC,
1637   PREFIX_EVEX_0F38AD,
1638   PREFIX_EVEX_0F38AE,
1639   PREFIX_EVEX_0F38AF,
1640   PREFIX_EVEX_0F38B4,
1641   PREFIX_EVEX_0F38B5,
1642   PREFIX_EVEX_0F38B6,
1643   PREFIX_EVEX_0F38B7,
1644   PREFIX_EVEX_0F38B8,
1645   PREFIX_EVEX_0F38B9,
1646   PREFIX_EVEX_0F38BA,
1647   PREFIX_EVEX_0F38BB,
1648   PREFIX_EVEX_0F38BC,
1649   PREFIX_EVEX_0F38BD,
1650   PREFIX_EVEX_0F38BE,
1651   PREFIX_EVEX_0F38BF,
1652   PREFIX_EVEX_0F38C4,
1653   PREFIX_EVEX_0F38C6_REG_1,
1654   PREFIX_EVEX_0F38C6_REG_2,
1655   PREFIX_EVEX_0F38C6_REG_5,
1656   PREFIX_EVEX_0F38C6_REG_6,
1657   PREFIX_EVEX_0F38C7_REG_1,
1658   PREFIX_EVEX_0F38C7_REG_2,
1659   PREFIX_EVEX_0F38C7_REG_5,
1660   PREFIX_EVEX_0F38C7_REG_6,
1661   PREFIX_EVEX_0F38C8,
1662   PREFIX_EVEX_0F38CA,
1663   PREFIX_EVEX_0F38CB,
1664   PREFIX_EVEX_0F38CC,
1665   PREFIX_EVEX_0F38CD,
1666   PREFIX_EVEX_0F38CF,
1667   PREFIX_EVEX_0F38DC,
1668   PREFIX_EVEX_0F38DD,
1669   PREFIX_EVEX_0F38DE,
1670   PREFIX_EVEX_0F38DF,
1671
1672   PREFIX_EVEX_0F3A00,
1673   PREFIX_EVEX_0F3A01,
1674   PREFIX_EVEX_0F3A03,
1675   PREFIX_EVEX_0F3A04,
1676   PREFIX_EVEX_0F3A05,
1677   PREFIX_EVEX_0F3A08,
1678   PREFIX_EVEX_0F3A09,
1679   PREFIX_EVEX_0F3A0A,
1680   PREFIX_EVEX_0F3A0B,
1681   PREFIX_EVEX_0F3A0F,
1682   PREFIX_EVEX_0F3A14,
1683   PREFIX_EVEX_0F3A15,
1684   PREFIX_EVEX_0F3A16,
1685   PREFIX_EVEX_0F3A17,
1686   PREFIX_EVEX_0F3A18,
1687   PREFIX_EVEX_0F3A19,
1688   PREFIX_EVEX_0F3A1A,
1689   PREFIX_EVEX_0F3A1B,
1690   PREFIX_EVEX_0F3A1D,
1691   PREFIX_EVEX_0F3A1E,
1692   PREFIX_EVEX_0F3A1F,
1693   PREFIX_EVEX_0F3A20,
1694   PREFIX_EVEX_0F3A21,
1695   PREFIX_EVEX_0F3A22,
1696   PREFIX_EVEX_0F3A23,
1697   PREFIX_EVEX_0F3A25,
1698   PREFIX_EVEX_0F3A26,
1699   PREFIX_EVEX_0F3A27,
1700   PREFIX_EVEX_0F3A38,
1701   PREFIX_EVEX_0F3A39,
1702   PREFIX_EVEX_0F3A3A,
1703   PREFIX_EVEX_0F3A3B,
1704   PREFIX_EVEX_0F3A3E,
1705   PREFIX_EVEX_0F3A3F,
1706   PREFIX_EVEX_0F3A42,
1707   PREFIX_EVEX_0F3A43,
1708   PREFIX_EVEX_0F3A44,
1709   PREFIX_EVEX_0F3A50,
1710   PREFIX_EVEX_0F3A51,
1711   PREFIX_EVEX_0F3A54,
1712   PREFIX_EVEX_0F3A55,
1713   PREFIX_EVEX_0F3A56,
1714   PREFIX_EVEX_0F3A57,
1715   PREFIX_EVEX_0F3A66,
1716   PREFIX_EVEX_0F3A67,
1717   PREFIX_EVEX_0F3A70,
1718   PREFIX_EVEX_0F3A71,
1719   PREFIX_EVEX_0F3A72,
1720   PREFIX_EVEX_0F3A73,
1721   PREFIX_EVEX_0F3ACE,
1722   PREFIX_EVEX_0F3ACF
1723 };
1724
1725 enum
1726 {
1727   X86_64_06 = 0,
1728   X86_64_07,
1729   X86_64_0D,
1730   X86_64_16,
1731   X86_64_17,
1732   X86_64_1E,
1733   X86_64_1F,
1734   X86_64_27,
1735   X86_64_2F,
1736   X86_64_37,
1737   X86_64_3F,
1738   X86_64_60,
1739   X86_64_61,
1740   X86_64_62,
1741   X86_64_63,
1742   X86_64_6D,
1743   X86_64_6F,
1744   X86_64_82,
1745   X86_64_9A,
1746   X86_64_C4,
1747   X86_64_C5,
1748   X86_64_CE,
1749   X86_64_D4,
1750   X86_64_D5,
1751   X86_64_E8,
1752   X86_64_E9,
1753   X86_64_EA,
1754   X86_64_0F01_REG_0,
1755   X86_64_0F01_REG_1,
1756   X86_64_0F01_REG_2,
1757   X86_64_0F01_REG_3
1758 };
1759
1760 enum
1761 {
1762   THREE_BYTE_0F38 = 0,
1763   THREE_BYTE_0F3A
1764 };
1765
1766 enum
1767 {
1768   XOP_08 = 0,
1769   XOP_09,
1770   XOP_0A
1771 };
1772
1773 enum
1774 {
1775   VEX_0F = 0,
1776   VEX_0F38,
1777   VEX_0F3A
1778 };
1779
1780 enum
1781 {
1782   EVEX_0F = 0,
1783   EVEX_0F38,
1784   EVEX_0F3A
1785 };
1786
1787 enum
1788 {
1789   VEX_LEN_0F10_P_1 = 0,
1790   VEX_LEN_0F10_P_3,
1791   VEX_LEN_0F11_P_1,
1792   VEX_LEN_0F11_P_3,
1793   VEX_LEN_0F12_P_0_M_0,
1794   VEX_LEN_0F12_P_0_M_1,
1795   VEX_LEN_0F12_P_2,
1796   VEX_LEN_0F13_M_0,
1797   VEX_LEN_0F16_P_0_M_0,
1798   VEX_LEN_0F16_P_0_M_1,
1799   VEX_LEN_0F16_P_2,
1800   VEX_LEN_0F17_M_0,
1801   VEX_LEN_0F2A_P_1,
1802   VEX_LEN_0F2A_P_3,
1803   VEX_LEN_0F2C_P_1,
1804   VEX_LEN_0F2C_P_3,
1805   VEX_LEN_0F2D_P_1,
1806   VEX_LEN_0F2D_P_3,
1807   VEX_LEN_0F2E_P_0,
1808   VEX_LEN_0F2E_P_2,
1809   VEX_LEN_0F2F_P_0,
1810   VEX_LEN_0F2F_P_2,
1811   VEX_LEN_0F41_P_0,
1812   VEX_LEN_0F41_P_2,
1813   VEX_LEN_0F42_P_0,
1814   VEX_LEN_0F42_P_2,
1815   VEX_LEN_0F44_P_0,
1816   VEX_LEN_0F44_P_2,
1817   VEX_LEN_0F45_P_0,
1818   VEX_LEN_0F45_P_2,
1819   VEX_LEN_0F46_P_0,
1820   VEX_LEN_0F46_P_2,
1821   VEX_LEN_0F47_P_0,
1822   VEX_LEN_0F47_P_2,
1823   VEX_LEN_0F4A_P_0,
1824   VEX_LEN_0F4A_P_2,
1825   VEX_LEN_0F4B_P_0,
1826   VEX_LEN_0F4B_P_2,
1827   VEX_LEN_0F51_P_1,
1828   VEX_LEN_0F51_P_3,
1829   VEX_LEN_0F52_P_1,
1830   VEX_LEN_0F53_P_1,
1831   VEX_LEN_0F58_P_1,
1832   VEX_LEN_0F58_P_3,
1833   VEX_LEN_0F59_P_1,
1834   VEX_LEN_0F59_P_3,
1835   VEX_LEN_0F5A_P_1,
1836   VEX_LEN_0F5A_P_3,
1837   VEX_LEN_0F5C_P_1,
1838   VEX_LEN_0F5C_P_3,
1839   VEX_LEN_0F5D_P_1,
1840   VEX_LEN_0F5D_P_3,
1841   VEX_LEN_0F5E_P_1,
1842   VEX_LEN_0F5E_P_3,
1843   VEX_LEN_0F5F_P_1,
1844   VEX_LEN_0F5F_P_3,
1845   VEX_LEN_0F6E_P_2,
1846   VEX_LEN_0F7E_P_1,
1847   VEX_LEN_0F7E_P_2,
1848   VEX_LEN_0F90_P_0,
1849   VEX_LEN_0F90_P_2,
1850   VEX_LEN_0F91_P_0,
1851   VEX_LEN_0F91_P_2,
1852   VEX_LEN_0F92_P_0,
1853   VEX_LEN_0F92_P_2,
1854   VEX_LEN_0F92_P_3,
1855   VEX_LEN_0F93_P_0,
1856   VEX_LEN_0F93_P_2,
1857   VEX_LEN_0F93_P_3,
1858   VEX_LEN_0F98_P_0,
1859   VEX_LEN_0F98_P_2,
1860   VEX_LEN_0F99_P_0,
1861   VEX_LEN_0F99_P_2,
1862   VEX_LEN_0FAE_R_2_M_0,
1863   VEX_LEN_0FAE_R_3_M_0,
1864   VEX_LEN_0FC2_P_1,
1865   VEX_LEN_0FC2_P_3,
1866   VEX_LEN_0FC4_P_2,
1867   VEX_LEN_0FC5_P_2,
1868   VEX_LEN_0FD6_P_2,
1869   VEX_LEN_0FF7_P_2,
1870   VEX_LEN_0F3816_P_2,
1871   VEX_LEN_0F3819_P_2,
1872   VEX_LEN_0F381A_P_2_M_0,
1873   VEX_LEN_0F3836_P_2,
1874   VEX_LEN_0F3841_P_2,
1875   VEX_LEN_0F385A_P_2_M_0,
1876   VEX_LEN_0F38DB_P_2,
1877   VEX_LEN_0F38F2_P_0,
1878   VEX_LEN_0F38F3_R_1_P_0,
1879   VEX_LEN_0F38F3_R_2_P_0,
1880   VEX_LEN_0F38F3_R_3_P_0,
1881   VEX_LEN_0F38F5_P_0,
1882   VEX_LEN_0F38F5_P_1,
1883   VEX_LEN_0F38F5_P_3,
1884   VEX_LEN_0F38F6_P_3,
1885   VEX_LEN_0F38F7_P_0,
1886   VEX_LEN_0F38F7_P_1,
1887   VEX_LEN_0F38F7_P_2,
1888   VEX_LEN_0F38F7_P_3,
1889   VEX_LEN_0F3A00_P_2,
1890   VEX_LEN_0F3A01_P_2,
1891   VEX_LEN_0F3A06_P_2,
1892   VEX_LEN_0F3A0A_P_2,
1893   VEX_LEN_0F3A0B_P_2,
1894   VEX_LEN_0F3A14_P_2,
1895   VEX_LEN_0F3A15_P_2,
1896   VEX_LEN_0F3A16_P_2,
1897   VEX_LEN_0F3A17_P_2,
1898   VEX_LEN_0F3A18_P_2,
1899   VEX_LEN_0F3A19_P_2,
1900   VEX_LEN_0F3A20_P_2,
1901   VEX_LEN_0F3A21_P_2,
1902   VEX_LEN_0F3A22_P_2,
1903   VEX_LEN_0F3A30_P_2,
1904   VEX_LEN_0F3A31_P_2,
1905   VEX_LEN_0F3A32_P_2,
1906   VEX_LEN_0F3A33_P_2,
1907   VEX_LEN_0F3A38_P_2,
1908   VEX_LEN_0F3A39_P_2,
1909   VEX_LEN_0F3A41_P_2,
1910   VEX_LEN_0F3A46_P_2,
1911   VEX_LEN_0F3A60_P_2,
1912   VEX_LEN_0F3A61_P_2,
1913   VEX_LEN_0F3A62_P_2,
1914   VEX_LEN_0F3A63_P_2,
1915   VEX_LEN_0F3A6A_P_2,
1916   VEX_LEN_0F3A6B_P_2,
1917   VEX_LEN_0F3A6E_P_2,
1918   VEX_LEN_0F3A6F_P_2,
1919   VEX_LEN_0F3A7A_P_2,
1920   VEX_LEN_0F3A7B_P_2,
1921   VEX_LEN_0F3A7E_P_2,
1922   VEX_LEN_0F3A7F_P_2,
1923   VEX_LEN_0F3ADF_P_2,
1924   VEX_LEN_0F3AF0_P_3,
1925   VEX_LEN_0FXOP_08_CC,
1926   VEX_LEN_0FXOP_08_CD,
1927   VEX_LEN_0FXOP_08_CE,
1928   VEX_LEN_0FXOP_08_CF,
1929   VEX_LEN_0FXOP_08_EC,
1930   VEX_LEN_0FXOP_08_ED,
1931   VEX_LEN_0FXOP_08_EE,
1932   VEX_LEN_0FXOP_08_EF,
1933   VEX_LEN_0FXOP_09_80,
1934   VEX_LEN_0FXOP_09_81
1935 };
1936
1937 enum
1938 {
1939   VEX_W_0F10_P_0 = 0,
1940   VEX_W_0F10_P_1,
1941   VEX_W_0F10_P_2,
1942   VEX_W_0F10_P_3,
1943   VEX_W_0F11_P_0,
1944   VEX_W_0F11_P_1,
1945   VEX_W_0F11_P_2,
1946   VEX_W_0F11_P_3,
1947   VEX_W_0F12_P_0_M_0,
1948   VEX_W_0F12_P_0_M_1,
1949   VEX_W_0F12_P_1,
1950   VEX_W_0F12_P_2,
1951   VEX_W_0F12_P_3,
1952   VEX_W_0F13_M_0,
1953   VEX_W_0F14,
1954   VEX_W_0F15,
1955   VEX_W_0F16_P_0_M_0,
1956   VEX_W_0F16_P_0_M_1,
1957   VEX_W_0F16_P_1,
1958   VEX_W_0F16_P_2,
1959   VEX_W_0F17_M_0,
1960   VEX_W_0F28,
1961   VEX_W_0F29,
1962   VEX_W_0F2B_M_0,
1963   VEX_W_0F2E_P_0,
1964   VEX_W_0F2E_P_2,
1965   VEX_W_0F2F_P_0,
1966   VEX_W_0F2F_P_2,
1967   VEX_W_0F41_P_0_LEN_1,
1968   VEX_W_0F41_P_2_LEN_1,
1969   VEX_W_0F42_P_0_LEN_1,
1970   VEX_W_0F42_P_2_LEN_1,
1971   VEX_W_0F44_P_0_LEN_0,
1972   VEX_W_0F44_P_2_LEN_0,
1973   VEX_W_0F45_P_0_LEN_1,
1974   VEX_W_0F45_P_2_LEN_1,
1975   VEX_W_0F46_P_0_LEN_1,
1976   VEX_W_0F46_P_2_LEN_1,
1977   VEX_W_0F47_P_0_LEN_1,
1978   VEX_W_0F47_P_2_LEN_1,
1979   VEX_W_0F4A_P_0_LEN_1,
1980   VEX_W_0F4A_P_2_LEN_1,
1981   VEX_W_0F4B_P_0_LEN_1,
1982   VEX_W_0F4B_P_2_LEN_1,
1983   VEX_W_0F50_M_0,
1984   VEX_W_0F51_P_0,
1985   VEX_W_0F51_P_1,
1986   VEX_W_0F51_P_2,
1987   VEX_W_0F51_P_3,
1988   VEX_W_0F52_P_0,
1989   VEX_W_0F52_P_1,
1990   VEX_W_0F53_P_0,
1991   VEX_W_0F53_P_1,
1992   VEX_W_0F58_P_0,
1993   VEX_W_0F58_P_1,
1994   VEX_W_0F58_P_2,
1995   VEX_W_0F58_P_3,
1996   VEX_W_0F59_P_0,
1997   VEX_W_0F59_P_1,
1998   VEX_W_0F59_P_2,
1999   VEX_W_0F59_P_3,
2000   VEX_W_0F5A_P_0,
2001   VEX_W_0F5A_P_1,
2002   VEX_W_0F5A_P_3,
2003   VEX_W_0F5B_P_0,
2004   VEX_W_0F5B_P_1,
2005   VEX_W_0F5B_P_2,
2006   VEX_W_0F5C_P_0,
2007   VEX_W_0F5C_P_1,
2008   VEX_W_0F5C_P_2,
2009   VEX_W_0F5C_P_3,
2010   VEX_W_0F5D_P_0,
2011   VEX_W_0F5D_P_1,
2012   VEX_W_0F5D_P_2,
2013   VEX_W_0F5D_P_3,
2014   VEX_W_0F5E_P_0,
2015   VEX_W_0F5E_P_1,
2016   VEX_W_0F5E_P_2,
2017   VEX_W_0F5E_P_3,
2018   VEX_W_0F5F_P_0,
2019   VEX_W_0F5F_P_1,
2020   VEX_W_0F5F_P_2,
2021   VEX_W_0F5F_P_3,
2022   VEX_W_0F60_P_2,
2023   VEX_W_0F61_P_2,
2024   VEX_W_0F62_P_2,
2025   VEX_W_0F63_P_2,
2026   VEX_W_0F64_P_2,
2027   VEX_W_0F65_P_2,
2028   VEX_W_0F66_P_2,
2029   VEX_W_0F67_P_2,
2030   VEX_W_0F68_P_2,
2031   VEX_W_0F69_P_2,
2032   VEX_W_0F6A_P_2,
2033   VEX_W_0F6B_P_2,
2034   VEX_W_0F6C_P_2,
2035   VEX_W_0F6D_P_2,
2036   VEX_W_0F6F_P_1,
2037   VEX_W_0F6F_P_2,
2038   VEX_W_0F70_P_1,
2039   VEX_W_0F70_P_2,
2040   VEX_W_0F70_P_3,
2041   VEX_W_0F71_R_2_P_2,
2042   VEX_W_0F71_R_4_P_2,
2043   VEX_W_0F71_R_6_P_2,
2044   VEX_W_0F72_R_2_P_2,
2045   VEX_W_0F72_R_4_P_2,
2046   VEX_W_0F72_R_6_P_2,
2047   VEX_W_0F73_R_2_P_2,
2048   VEX_W_0F73_R_3_P_2,
2049   VEX_W_0F73_R_6_P_2,
2050   VEX_W_0F73_R_7_P_2,
2051   VEX_W_0F74_P_2,
2052   VEX_W_0F75_P_2,
2053   VEX_W_0F76_P_2,
2054   VEX_W_0F77_P_0,
2055   VEX_W_0F7C_P_2,
2056   VEX_W_0F7C_P_3,
2057   VEX_W_0F7D_P_2,
2058   VEX_W_0F7D_P_3,
2059   VEX_W_0F7E_P_1,
2060   VEX_W_0F7F_P_1,
2061   VEX_W_0F7F_P_2,
2062   VEX_W_0F90_P_0_LEN_0,
2063   VEX_W_0F90_P_2_LEN_0,
2064   VEX_W_0F91_P_0_LEN_0,
2065   VEX_W_0F91_P_2_LEN_0,
2066   VEX_W_0F92_P_0_LEN_0,
2067   VEX_W_0F92_P_2_LEN_0,
2068   VEX_W_0F92_P_3_LEN_0,
2069   VEX_W_0F93_P_0_LEN_0,
2070   VEX_W_0F93_P_2_LEN_0,
2071   VEX_W_0F93_P_3_LEN_0,
2072   VEX_W_0F98_P_0_LEN_0,
2073   VEX_W_0F98_P_2_LEN_0,
2074   VEX_W_0F99_P_0_LEN_0,
2075   VEX_W_0F99_P_2_LEN_0,
2076   VEX_W_0FAE_R_2_M_0,
2077   VEX_W_0FAE_R_3_M_0,
2078   VEX_W_0FC2_P_0,
2079   VEX_W_0FC2_P_1,
2080   VEX_W_0FC2_P_2,
2081   VEX_W_0FC2_P_3,
2082   VEX_W_0FC4_P_2,
2083   VEX_W_0FC5_P_2,
2084   VEX_W_0FD0_P_2,
2085   VEX_W_0FD0_P_3,
2086   VEX_W_0FD1_P_2,
2087   VEX_W_0FD2_P_2,
2088   VEX_W_0FD3_P_2,
2089   VEX_W_0FD4_P_2,
2090   VEX_W_0FD5_P_2,
2091   VEX_W_0FD6_P_2,
2092   VEX_W_0FD7_P_2_M_1,
2093   VEX_W_0FD8_P_2,
2094   VEX_W_0FD9_P_2,
2095   VEX_W_0FDA_P_2,
2096   VEX_W_0FDB_P_2,
2097   VEX_W_0FDC_P_2,
2098   VEX_W_0FDD_P_2,
2099   VEX_W_0FDE_P_2,
2100   VEX_W_0FDF_P_2,
2101   VEX_W_0FE0_P_2,
2102   VEX_W_0FE1_P_2,
2103   VEX_W_0FE2_P_2,
2104   VEX_W_0FE3_P_2,
2105   VEX_W_0FE4_P_2,
2106   VEX_W_0FE5_P_2,
2107   VEX_W_0FE6_P_1,
2108   VEX_W_0FE6_P_2,
2109   VEX_W_0FE6_P_3,
2110   VEX_W_0FE7_P_2_M_0,
2111   VEX_W_0FE8_P_2,
2112   VEX_W_0FE9_P_2,
2113   VEX_W_0FEA_P_2,
2114   VEX_W_0FEB_P_2,
2115   VEX_W_0FEC_P_2,
2116   VEX_W_0FED_P_2,
2117   VEX_W_0FEE_P_2,
2118   VEX_W_0FEF_P_2,
2119   VEX_W_0FF0_P_3_M_0,
2120   VEX_W_0FF1_P_2,
2121   VEX_W_0FF2_P_2,
2122   VEX_W_0FF3_P_2,
2123   VEX_W_0FF4_P_2,
2124   VEX_W_0FF5_P_2,
2125   VEX_W_0FF6_P_2,
2126   VEX_W_0FF7_P_2,
2127   VEX_W_0FF8_P_2,
2128   VEX_W_0FF9_P_2,
2129   VEX_W_0FFA_P_2,
2130   VEX_W_0FFB_P_2,
2131   VEX_W_0FFC_P_2,
2132   VEX_W_0FFD_P_2,
2133   VEX_W_0FFE_P_2,
2134   VEX_W_0F3800_P_2,
2135   VEX_W_0F3801_P_2,
2136   VEX_W_0F3802_P_2,
2137   VEX_W_0F3803_P_2,
2138   VEX_W_0F3804_P_2,
2139   VEX_W_0F3805_P_2,
2140   VEX_W_0F3806_P_2,
2141   VEX_W_0F3807_P_2,
2142   VEX_W_0F3808_P_2,
2143   VEX_W_0F3809_P_2,
2144   VEX_W_0F380A_P_2,
2145   VEX_W_0F380B_P_2,
2146   VEX_W_0F380C_P_2,
2147   VEX_W_0F380D_P_2,
2148   VEX_W_0F380E_P_2,
2149   VEX_W_0F380F_P_2,
2150   VEX_W_0F3816_P_2,
2151   VEX_W_0F3817_P_2,
2152   VEX_W_0F3818_P_2,
2153   VEX_W_0F3819_P_2,
2154   VEX_W_0F381A_P_2_M_0,
2155   VEX_W_0F381C_P_2,
2156   VEX_W_0F381D_P_2,
2157   VEX_W_0F381E_P_2,
2158   VEX_W_0F3820_P_2,
2159   VEX_W_0F3821_P_2,
2160   VEX_W_0F3822_P_2,
2161   VEX_W_0F3823_P_2,
2162   VEX_W_0F3824_P_2,
2163   VEX_W_0F3825_P_2,
2164   VEX_W_0F3828_P_2,
2165   VEX_W_0F3829_P_2,
2166   VEX_W_0F382A_P_2_M_0,
2167   VEX_W_0F382B_P_2,
2168   VEX_W_0F382C_P_2_M_0,
2169   VEX_W_0F382D_P_2_M_0,
2170   VEX_W_0F382E_P_2_M_0,
2171   VEX_W_0F382F_P_2_M_0,
2172   VEX_W_0F3830_P_2,
2173   VEX_W_0F3831_P_2,
2174   VEX_W_0F3832_P_2,
2175   VEX_W_0F3833_P_2,
2176   VEX_W_0F3834_P_2,
2177   VEX_W_0F3835_P_2,
2178   VEX_W_0F3836_P_2,
2179   VEX_W_0F3837_P_2,
2180   VEX_W_0F3838_P_2,
2181   VEX_W_0F3839_P_2,
2182   VEX_W_0F383A_P_2,
2183   VEX_W_0F383B_P_2,
2184   VEX_W_0F383C_P_2,
2185   VEX_W_0F383D_P_2,
2186   VEX_W_0F383E_P_2,
2187   VEX_W_0F383F_P_2,
2188   VEX_W_0F3840_P_2,
2189   VEX_W_0F3841_P_2,
2190   VEX_W_0F3846_P_2,
2191   VEX_W_0F3858_P_2,
2192   VEX_W_0F3859_P_2,
2193   VEX_W_0F385A_P_2_M_0,
2194   VEX_W_0F3878_P_2,
2195   VEX_W_0F3879_P_2,
2196   VEX_W_0F38CF_P_2,
2197   VEX_W_0F38DB_P_2,
2198   VEX_W_0F3A00_P_2,
2199   VEX_W_0F3A01_P_2,
2200   VEX_W_0F3A02_P_2,
2201   VEX_W_0F3A04_P_2,
2202   VEX_W_0F3A05_P_2,
2203   VEX_W_0F3A06_P_2,
2204   VEX_W_0F3A08_P_2,
2205   VEX_W_0F3A09_P_2,
2206   VEX_W_0F3A0A_P_2,
2207   VEX_W_0F3A0B_P_2,
2208   VEX_W_0F3A0C_P_2,
2209   VEX_W_0F3A0D_P_2,
2210   VEX_W_0F3A0E_P_2,
2211   VEX_W_0F3A0F_P_2,
2212   VEX_W_0F3A14_P_2,
2213   VEX_W_0F3A15_P_2,
2214   VEX_W_0F3A18_P_2,
2215   VEX_W_0F3A19_P_2,
2216   VEX_W_0F3A20_P_2,
2217   VEX_W_0F3A21_P_2,
2218   VEX_W_0F3A30_P_2_LEN_0,
2219   VEX_W_0F3A31_P_2_LEN_0,
2220   VEX_W_0F3A32_P_2_LEN_0,
2221   VEX_W_0F3A33_P_2_LEN_0,
2222   VEX_W_0F3A38_P_2,
2223   VEX_W_0F3A39_P_2,
2224   VEX_W_0F3A40_P_2,
2225   VEX_W_0F3A41_P_2,
2226   VEX_W_0F3A42_P_2,
2227   VEX_W_0F3A46_P_2,
2228   VEX_W_0F3A48_P_2,
2229   VEX_W_0F3A49_P_2,
2230   VEX_W_0F3A4A_P_2,
2231   VEX_W_0F3A4B_P_2,
2232   VEX_W_0F3A4C_P_2,
2233   VEX_W_0F3A62_P_2,
2234   VEX_W_0F3A63_P_2,
2235   VEX_W_0F3ACE_P_2,
2236   VEX_W_0F3ACF_P_2,
2237   VEX_W_0F3ADF_P_2,
2238
2239   EVEX_W_0F10_P_0,
2240   EVEX_W_0F10_P_1_M_0,
2241   EVEX_W_0F10_P_1_M_1,
2242   EVEX_W_0F10_P_2,
2243   EVEX_W_0F10_P_3_M_0,
2244   EVEX_W_0F10_P_3_M_1,
2245   EVEX_W_0F11_P_0,
2246   EVEX_W_0F11_P_1_M_0,
2247   EVEX_W_0F11_P_1_M_1,
2248   EVEX_W_0F11_P_2,
2249   EVEX_W_0F11_P_3_M_0,
2250   EVEX_W_0F11_P_3_M_1,
2251   EVEX_W_0F12_P_0_M_0,
2252   EVEX_W_0F12_P_0_M_1,
2253   EVEX_W_0F12_P_1,
2254   EVEX_W_0F12_P_2,
2255   EVEX_W_0F12_P_3,
2256   EVEX_W_0F13_P_0,
2257   EVEX_W_0F13_P_2,
2258   EVEX_W_0F14_P_0,
2259   EVEX_W_0F14_P_2,
2260   EVEX_W_0F15_P_0,
2261   EVEX_W_0F15_P_2,
2262   EVEX_W_0F16_P_0_M_0,
2263   EVEX_W_0F16_P_0_M_1,
2264   EVEX_W_0F16_P_1,
2265   EVEX_W_0F16_P_2,
2266   EVEX_W_0F17_P_0,
2267   EVEX_W_0F17_P_2,
2268   EVEX_W_0F28_P_0,
2269   EVEX_W_0F28_P_2,
2270   EVEX_W_0F29_P_0,
2271   EVEX_W_0F29_P_2,
2272   EVEX_W_0F2A_P_1,
2273   EVEX_W_0F2A_P_3,
2274   EVEX_W_0F2B_P_0,
2275   EVEX_W_0F2B_P_2,
2276   EVEX_W_0F2E_P_0,
2277   EVEX_W_0F2E_P_2,
2278   EVEX_W_0F2F_P_0,
2279   EVEX_W_0F2F_P_2,
2280   EVEX_W_0F51_P_0,
2281   EVEX_W_0F51_P_1,
2282   EVEX_W_0F51_P_2,
2283   EVEX_W_0F51_P_3,
2284   EVEX_W_0F54_P_0,
2285   EVEX_W_0F54_P_2,
2286   EVEX_W_0F55_P_0,
2287   EVEX_W_0F55_P_2,
2288   EVEX_W_0F56_P_0,
2289   EVEX_W_0F56_P_2,
2290   EVEX_W_0F57_P_0,
2291   EVEX_W_0F57_P_2,
2292   EVEX_W_0F58_P_0,
2293   EVEX_W_0F58_P_1,
2294   EVEX_W_0F58_P_2,
2295   EVEX_W_0F58_P_3,
2296   EVEX_W_0F59_P_0,
2297   EVEX_W_0F59_P_1,
2298   EVEX_W_0F59_P_2,
2299   EVEX_W_0F59_P_3,
2300   EVEX_W_0F5A_P_0,
2301   EVEX_W_0F5A_P_1,
2302   EVEX_W_0F5A_P_2,
2303   EVEX_W_0F5A_P_3,
2304   EVEX_W_0F5B_P_0,
2305   EVEX_W_0F5B_P_1,
2306   EVEX_W_0F5B_P_2,
2307   EVEX_W_0F5C_P_0,
2308   EVEX_W_0F5C_P_1,
2309   EVEX_W_0F5C_P_2,
2310   EVEX_W_0F5C_P_3,
2311   EVEX_W_0F5D_P_0,
2312   EVEX_W_0F5D_P_1,
2313   EVEX_W_0F5D_P_2,
2314   EVEX_W_0F5D_P_3,
2315   EVEX_W_0F5E_P_0,
2316   EVEX_W_0F5E_P_1,
2317   EVEX_W_0F5E_P_2,
2318   EVEX_W_0F5E_P_3,
2319   EVEX_W_0F5F_P_0,
2320   EVEX_W_0F5F_P_1,
2321   EVEX_W_0F5F_P_2,
2322   EVEX_W_0F5F_P_3,
2323   EVEX_W_0F62_P_2,
2324   EVEX_W_0F66_P_2,
2325   EVEX_W_0F6A_P_2,
2326   EVEX_W_0F6B_P_2,
2327   EVEX_W_0F6C_P_2,
2328   EVEX_W_0F6D_P_2,
2329   EVEX_W_0F6E_P_2,
2330   EVEX_W_0F6F_P_1,
2331   EVEX_W_0F6F_P_2,
2332   EVEX_W_0F6F_P_3,
2333   EVEX_W_0F70_P_2,
2334   EVEX_W_0F72_R_2_P_2,
2335   EVEX_W_0F72_R_6_P_2,
2336   EVEX_W_0F73_R_2_P_2,
2337   EVEX_W_0F73_R_6_P_2,
2338   EVEX_W_0F76_P_2,
2339   EVEX_W_0F78_P_0,
2340   EVEX_W_0F78_P_2,
2341   EVEX_W_0F79_P_0,
2342   EVEX_W_0F79_P_2,
2343   EVEX_W_0F7A_P_1,
2344   EVEX_W_0F7A_P_2,
2345   EVEX_W_0F7A_P_3,
2346   EVEX_W_0F7B_P_1,
2347   EVEX_W_0F7B_P_2,
2348   EVEX_W_0F7B_P_3,
2349   EVEX_W_0F7E_P_1,
2350   EVEX_W_0F7E_P_2,
2351   EVEX_W_0F7F_P_1,
2352   EVEX_W_0F7F_P_2,
2353   EVEX_W_0F7F_P_3,
2354   EVEX_W_0FC2_P_0,
2355   EVEX_W_0FC2_P_1,
2356   EVEX_W_0FC2_P_2,
2357   EVEX_W_0FC2_P_3,
2358   EVEX_W_0FC6_P_0,
2359   EVEX_W_0FC6_P_2,
2360   EVEX_W_0FD2_P_2,
2361   EVEX_W_0FD3_P_2,
2362   EVEX_W_0FD4_P_2,
2363   EVEX_W_0FD6_P_2,
2364   EVEX_W_0FE6_P_1,
2365   EVEX_W_0FE6_P_2,
2366   EVEX_W_0FE6_P_3,
2367   EVEX_W_0FE7_P_2,
2368   EVEX_W_0FF2_P_2,
2369   EVEX_W_0FF3_P_2,
2370   EVEX_W_0FF4_P_2,
2371   EVEX_W_0FFA_P_2,
2372   EVEX_W_0FFB_P_2,
2373   EVEX_W_0FFE_P_2,
2374   EVEX_W_0F380C_P_2,
2375   EVEX_W_0F380D_P_2,
2376   EVEX_W_0F3810_P_1,
2377   EVEX_W_0F3810_P_2,
2378   EVEX_W_0F3811_P_1,
2379   EVEX_W_0F3811_P_2,
2380   EVEX_W_0F3812_P_1,
2381   EVEX_W_0F3812_P_2,
2382   EVEX_W_0F3813_P_1,
2383   EVEX_W_0F3813_P_2,
2384   EVEX_W_0F3814_P_1,
2385   EVEX_W_0F3815_P_1,
2386   EVEX_W_0F3818_P_2,
2387   EVEX_W_0F3819_P_2,
2388   EVEX_W_0F381A_P_2,
2389   EVEX_W_0F381B_P_2,
2390   EVEX_W_0F381E_P_2,
2391   EVEX_W_0F381F_P_2,
2392   EVEX_W_0F3820_P_1,
2393   EVEX_W_0F3821_P_1,
2394   EVEX_W_0F3822_P_1,
2395   EVEX_W_0F3823_P_1,
2396   EVEX_W_0F3824_P_1,
2397   EVEX_W_0F3825_P_1,
2398   EVEX_W_0F3825_P_2,
2399   EVEX_W_0F3826_P_1,
2400   EVEX_W_0F3826_P_2,
2401   EVEX_W_0F3828_P_1,
2402   EVEX_W_0F3828_P_2,
2403   EVEX_W_0F3829_P_1,
2404   EVEX_W_0F3829_P_2,
2405   EVEX_W_0F382A_P_1,
2406   EVEX_W_0F382A_P_2,
2407   EVEX_W_0F382B_P_2,
2408   EVEX_W_0F3830_P_1,
2409   EVEX_W_0F3831_P_1,
2410   EVEX_W_0F3832_P_1,
2411   EVEX_W_0F3833_P_1,
2412   EVEX_W_0F3834_P_1,
2413   EVEX_W_0F3835_P_1,
2414   EVEX_W_0F3835_P_2,
2415   EVEX_W_0F3837_P_2,
2416   EVEX_W_0F3838_P_1,
2417   EVEX_W_0F3839_P_1,
2418   EVEX_W_0F383A_P_1,
2419   EVEX_W_0F3840_P_2,
2420   EVEX_W_0F3854_P_2,
2421   EVEX_W_0F3855_P_2,
2422   EVEX_W_0F3858_P_2,
2423   EVEX_W_0F3859_P_2,
2424   EVEX_W_0F385A_P_2,
2425   EVEX_W_0F385B_P_2,
2426   EVEX_W_0F3862_P_2,
2427   EVEX_W_0F3863_P_2,
2428   EVEX_W_0F3866_P_2,
2429   EVEX_W_0F3870_P_2,
2430   EVEX_W_0F3871_P_2,
2431   EVEX_W_0F3872_P_2,
2432   EVEX_W_0F3873_P_2,
2433   EVEX_W_0F3875_P_2,
2434   EVEX_W_0F3878_P_2,
2435   EVEX_W_0F3879_P_2,
2436   EVEX_W_0F387A_P_2,
2437   EVEX_W_0F387B_P_2,
2438   EVEX_W_0F387D_P_2,
2439   EVEX_W_0F3883_P_2,
2440   EVEX_W_0F388D_P_2,
2441   EVEX_W_0F3891_P_2,
2442   EVEX_W_0F3893_P_2,
2443   EVEX_W_0F38A1_P_2,
2444   EVEX_W_0F38A3_P_2,
2445   EVEX_W_0F38C7_R_1_P_2,
2446   EVEX_W_0F38C7_R_2_P_2,
2447   EVEX_W_0F38C7_R_5_P_2,
2448   EVEX_W_0F38C7_R_6_P_2,
2449
2450   EVEX_W_0F3A00_P_2,
2451   EVEX_W_0F3A01_P_2,
2452   EVEX_W_0F3A04_P_2,
2453   EVEX_W_0F3A05_P_2,
2454   EVEX_W_0F3A08_P_2,
2455   EVEX_W_0F3A09_P_2,
2456   EVEX_W_0F3A0A_P_2,
2457   EVEX_W_0F3A0B_P_2,
2458   EVEX_W_0F3A16_P_2,
2459   EVEX_W_0F3A18_P_2,
2460   EVEX_W_0F3A19_P_2,
2461   EVEX_W_0F3A1A_P_2,
2462   EVEX_W_0F3A1B_P_2,
2463   EVEX_W_0F3A1D_P_2,
2464   EVEX_W_0F3A21_P_2,
2465   EVEX_W_0F3A22_P_2,
2466   EVEX_W_0F3A23_P_2,
2467   EVEX_W_0F3A38_P_2,
2468   EVEX_W_0F3A39_P_2,
2469   EVEX_W_0F3A3A_P_2,
2470   EVEX_W_0F3A3B_P_2,
2471   EVEX_W_0F3A3E_P_2,
2472   EVEX_W_0F3A3F_P_2,
2473   EVEX_W_0F3A42_P_2,
2474   EVEX_W_0F3A43_P_2,
2475   EVEX_W_0F3A50_P_2,
2476   EVEX_W_0F3A51_P_2,
2477   EVEX_W_0F3A56_P_2,
2478   EVEX_W_0F3A57_P_2,
2479   EVEX_W_0F3A66_P_2,
2480   EVEX_W_0F3A67_P_2,
2481   EVEX_W_0F3A70_P_2,
2482   EVEX_W_0F3A71_P_2,
2483   EVEX_W_0F3A72_P_2,
2484   EVEX_W_0F3A73_P_2,
2485   EVEX_W_0F3ACE_P_2,
2486   EVEX_W_0F3ACF_P_2
2487 };
2488
2489 typedef void (*op_rtn) (int bytemode, int sizeflag);
2490
2491 struct dis386 {
2492   const char *name;
2493   struct
2494     {
2495       op_rtn rtn;
2496       int bytemode;
2497     } op[MAX_OPERANDS];
2498   unsigned int prefix_requirement;
2499 };
2500
2501 /* Upper case letters in the instruction names here are macros.
2502    'A' => print 'b' if no register operands or suffix_always is true
2503    'B' => print 'b' if suffix_always is true
2504    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2505           size prefix
2506    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2507           suffix_always is true
2508    'E' => print 'e' if 32-bit form of jcxz
2509    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2510    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2511    'H' => print ",pt" or ",pn" branch hint
2512    'I' => honor following macro letter even in Intel mode (implemented only
2513           for some of the macro letters)
2514    'J' => print 'l'
2515    'K' => print 'd' or 'q' if rex prefix is present.
2516    'L' => print 'l' if suffix_always is true
2517    'M' => print 'r' if intel_mnemonic is false.
2518    'N' => print 'n' if instruction has no wait "prefix"
2519    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2520    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2521           or suffix_always is true.  print 'q' if rex prefix is present.
2522    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2523           is true
2524    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2525    'S' => print 'w', 'l' or 'q' if suffix_always is true
2526    'T' => print 'q' in 64bit mode if instruction has no operand size
2527           prefix and behave as 'P' otherwise
2528    'U' => print 'q' in 64bit mode if instruction has no operand size
2529           prefix and behave as 'Q' otherwise
2530    'V' => print 'q' in 64bit mode if instruction has no operand size
2531           prefix and behave as 'S' otherwise
2532    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2533    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2534    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2535           suffix_always is true.
2536    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2537    '!' => change condition from true to false or from false to true.
2538    '%' => add 1 upper case letter to the macro.
2539    '^' => print 'w' or 'l' depending on operand size prefix or
2540           suffix_always is true (lcall/ljmp).
2541    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2542           on operand size prefix.
2543    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2544           has no operand size prefix for AMD64 ISA, behave as 'P'
2545           otherwise
2546
2547    2 upper case letter macros:
2548    "XY" => print 'x' or 'y' if suffix_always is true or no register
2549            operands and no broadcast.
2550    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2551            register operands and no broadcast.
2552    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2553    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2554            or suffix_always is true
2555    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2556    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2557    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2558    "LW" => print 'd', 'q' depending on the VEX.W bit
2559    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2560            an operand size prefix, or suffix_always is true.  print
2561            'q' if rex prefix is present.
2562
2563    Many of the above letters print nothing in Intel mode.  See "putop"
2564    for the details.
2565
2566    Braces '{' and '}', and vertical bars '|', indicate alternative
2567    mnemonic strings for AT&T and Intel.  */
2568
2569 static const struct dis386 dis386[] = {
2570   /* 00 */
2571   { "addB",             { Ebh1, Gb }, 0 },
2572   { "addS",             { Evh1, Gv }, 0 },
2573   { "addB",             { Gb, EbS }, 0 },
2574   { "addS",             { Gv, EvS }, 0 },
2575   { "addB",             { AL, Ib }, 0 },
2576   { "addS",             { eAX, Iv }, 0 },
2577   { X86_64_TABLE (X86_64_06) },
2578   { X86_64_TABLE (X86_64_07) },
2579   /* 08 */
2580   { "orB",              { Ebh1, Gb }, 0 },
2581   { "orS",              { Evh1, Gv }, 0 },
2582   { "orB",              { Gb, EbS }, 0 },
2583   { "orS",              { Gv, EvS }, 0 },
2584   { "orB",              { AL, Ib }, 0 },
2585   { "orS",              { eAX, Iv }, 0 },
2586   { X86_64_TABLE (X86_64_0D) },
2587   { Bad_Opcode },       /* 0x0f extended opcode escape */
2588   /* 10 */
2589   { "adcB",             { Ebh1, Gb }, 0 },
2590   { "adcS",             { Evh1, Gv }, 0 },
2591   { "adcB",             { Gb, EbS }, 0 },
2592   { "adcS",             { Gv, EvS }, 0 },
2593   { "adcB",             { AL, Ib }, 0 },
2594   { "adcS",             { eAX, Iv }, 0 },
2595   { X86_64_TABLE (X86_64_16) },
2596   { X86_64_TABLE (X86_64_17) },
2597   /* 18 */
2598   { "sbbB",             { Ebh1, Gb }, 0 },
2599   { "sbbS",             { Evh1, Gv }, 0 },
2600   { "sbbB",             { Gb, EbS }, 0 },
2601   { "sbbS",             { Gv, EvS }, 0 },
2602   { "sbbB",             { AL, Ib }, 0 },
2603   { "sbbS",             { eAX, Iv }, 0 },
2604   { X86_64_TABLE (X86_64_1E) },
2605   { X86_64_TABLE (X86_64_1F) },
2606   /* 20 */
2607   { "andB",             { Ebh1, Gb }, 0 },
2608   { "andS",             { Evh1, Gv }, 0 },
2609   { "andB",             { Gb, EbS }, 0 },
2610   { "andS",             { Gv, EvS }, 0 },
2611   { "andB",             { AL, Ib }, 0 },
2612   { "andS",             { eAX, Iv }, 0 },
2613   { Bad_Opcode },       /* SEG ES prefix */
2614   { X86_64_TABLE (X86_64_27) },
2615   /* 28 */
2616   { "subB",             { Ebh1, Gb }, 0 },
2617   { "subS",             { Evh1, Gv }, 0 },
2618   { "subB",             { Gb, EbS }, 0 },
2619   { "subS",             { Gv, EvS }, 0 },
2620   { "subB",             { AL, Ib }, 0 },
2621   { "subS",             { eAX, Iv }, 0 },
2622   { Bad_Opcode },       /* SEG CS prefix */
2623   { X86_64_TABLE (X86_64_2F) },
2624   /* 30 */
2625   { "xorB",             { Ebh1, Gb }, 0 },
2626   { "xorS",             { Evh1, Gv }, 0 },
2627   { "xorB",             { Gb, EbS }, 0 },
2628   { "xorS",             { Gv, EvS }, 0 },
2629   { "xorB",             { AL, Ib }, 0 },
2630   { "xorS",             { eAX, Iv }, 0 },
2631   { Bad_Opcode },       /* SEG SS prefix */
2632   { X86_64_TABLE (X86_64_37) },
2633   /* 38 */
2634   { "cmpB",             { Eb, Gb }, 0 },
2635   { "cmpS",             { Ev, Gv }, 0 },
2636   { "cmpB",             { Gb, EbS }, 0 },
2637   { "cmpS",             { Gv, EvS }, 0 },
2638   { "cmpB",             { AL, Ib }, 0 },
2639   { "cmpS",             { eAX, Iv }, 0 },
2640   { Bad_Opcode },       /* SEG DS prefix */
2641   { X86_64_TABLE (X86_64_3F) },
2642   /* 40 */
2643   { "inc{S|}",          { RMeAX }, 0 },
2644   { "inc{S|}",          { RMeCX }, 0 },
2645   { "inc{S|}",          { RMeDX }, 0 },
2646   { "inc{S|}",          { RMeBX }, 0 },
2647   { "inc{S|}",          { RMeSP }, 0 },
2648   { "inc{S|}",          { RMeBP }, 0 },
2649   { "inc{S|}",          { RMeSI }, 0 },
2650   { "inc{S|}",          { RMeDI }, 0 },
2651   /* 48 */
2652   { "dec{S|}",          { RMeAX }, 0 },
2653   { "dec{S|}",          { RMeCX }, 0 },
2654   { "dec{S|}",          { RMeDX }, 0 },
2655   { "dec{S|}",          { RMeBX }, 0 },
2656   { "dec{S|}",          { RMeSP }, 0 },
2657   { "dec{S|}",          { RMeBP }, 0 },
2658   { "dec{S|}",          { RMeSI }, 0 },
2659   { "dec{S|}",          { RMeDI }, 0 },
2660   /* 50 */
2661   { "pushV",            { RMrAX }, 0 },
2662   { "pushV",            { RMrCX }, 0 },
2663   { "pushV",            { RMrDX }, 0 },
2664   { "pushV",            { RMrBX }, 0 },
2665   { "pushV",            { RMrSP }, 0 },
2666   { "pushV",            { RMrBP }, 0 },
2667   { "pushV",            { RMrSI }, 0 },
2668   { "pushV",            { RMrDI }, 0 },
2669   /* 58 */
2670   { "popV",             { RMrAX }, 0 },
2671   { "popV",             { RMrCX }, 0 },
2672   { "popV",             { RMrDX }, 0 },
2673   { "popV",             { RMrBX }, 0 },
2674   { "popV",             { RMrSP }, 0 },
2675   { "popV",             { RMrBP }, 0 },
2676   { "popV",             { RMrSI }, 0 },
2677   { "popV",             { RMrDI }, 0 },
2678   /* 60 */
2679   { X86_64_TABLE (X86_64_60) },
2680   { X86_64_TABLE (X86_64_61) },
2681   { X86_64_TABLE (X86_64_62) },
2682   { X86_64_TABLE (X86_64_63) },
2683   { Bad_Opcode },       /* seg fs */
2684   { Bad_Opcode },       /* seg gs */
2685   { Bad_Opcode },       /* op size prefix */
2686   { Bad_Opcode },       /* adr size prefix */
2687   /* 68 */
2688   { "pushT",            { sIv }, 0 },
2689   { "imulS",            { Gv, Ev, Iv }, 0 },
2690   { "pushT",            { sIbT }, 0 },
2691   { "imulS",            { Gv, Ev, sIb }, 0 },
2692   { "ins{b|}",          { Ybr, indirDX }, 0 },
2693   { X86_64_TABLE (X86_64_6D) },
2694   { "outs{b|}",         { indirDXr, Xb }, 0 },
2695   { X86_64_TABLE (X86_64_6F) },
2696   /* 70 */
2697   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2698   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2699   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2700   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2701   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2702   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2703   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2704   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2705   /* 78 */
2706   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2707   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2708   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2709   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2710   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2711   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2712   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2713   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2714   /* 80 */
2715   { REG_TABLE (REG_80) },
2716   { REG_TABLE (REG_81) },
2717   { X86_64_TABLE (X86_64_82) },
2718   { REG_TABLE (REG_83) },
2719   { "testB",            { Eb, Gb }, 0 },
2720   { "testS",            { Ev, Gv }, 0 },
2721   { "xchgB",            { Ebh2, Gb }, 0 },
2722   { "xchgS",            { Evh2, Gv }, 0 },
2723   /* 88 */
2724   { "movB",             { Ebh3, Gb }, 0 },
2725   { "movS",             { Evh3, Gv }, 0 },
2726   { "movB",             { Gb, EbS }, 0 },
2727   { "movS",             { Gv, EvS }, 0 },
2728   { "movD",             { Sv, Sw }, 0 },
2729   { MOD_TABLE (MOD_8D) },
2730   { "movD",             { Sw, Sv }, 0 },
2731   { REG_TABLE (REG_8F) },
2732   /* 90 */
2733   { PREFIX_TABLE (PREFIX_90) },
2734   { "xchgS",            { RMeCX, eAX }, 0 },
2735   { "xchgS",            { RMeDX, eAX }, 0 },
2736   { "xchgS",            { RMeBX, eAX }, 0 },
2737   { "xchgS",            { RMeSP, eAX }, 0 },
2738   { "xchgS",            { RMeBP, eAX }, 0 },
2739   { "xchgS",            { RMeSI, eAX }, 0 },
2740   { "xchgS",            { RMeDI, eAX }, 0 },
2741   /* 98 */
2742   { "cW{t|}R",          { XX }, 0 },
2743   { "cR{t|}O",          { XX }, 0 },
2744   { X86_64_TABLE (X86_64_9A) },
2745   { Bad_Opcode },       /* fwait */
2746   { "pushfT",           { XX }, 0 },
2747   { "popfT",            { XX }, 0 },
2748   { "sahf",             { XX }, 0 },
2749   { "lahf",             { XX }, 0 },
2750   /* a0 */
2751   { "mov%LB",           { AL, Ob }, 0 },
2752   { "mov%LS",           { eAX, Ov }, 0 },
2753   { "mov%LB",           { Ob, AL }, 0 },
2754   { "mov%LS",           { Ov, eAX }, 0 },
2755   { "movs{b|}",         { Ybr, Xb }, 0 },
2756   { "movs{R|}",         { Yvr, Xv }, 0 },
2757   { "cmps{b|}",         { Xb, Yb }, 0 },
2758   { "cmps{R|}",         { Xv, Yv }, 0 },
2759   /* a8 */
2760   { "testB",            { AL, Ib }, 0 },
2761   { "testS",            { eAX, Iv }, 0 },
2762   { "stosB",            { Ybr, AL }, 0 },
2763   { "stosS",            { Yvr, eAX }, 0 },
2764   { "lodsB",            { ALr, Xb }, 0 },
2765   { "lodsS",            { eAXr, Xv }, 0 },
2766   { "scasB",            { AL, Yb }, 0 },
2767   { "scasS",            { eAX, Yv }, 0 },
2768   /* b0 */
2769   { "movB",             { RMAL, Ib }, 0 },
2770   { "movB",             { RMCL, Ib }, 0 },
2771   { "movB",             { RMDL, Ib }, 0 },
2772   { "movB",             { RMBL, Ib }, 0 },
2773   { "movB",             { RMAH, Ib }, 0 },
2774   { "movB",             { RMCH, Ib }, 0 },
2775   { "movB",             { RMDH, Ib }, 0 },
2776   { "movB",             { RMBH, Ib }, 0 },
2777   /* b8 */
2778   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2779   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2780   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2781   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2782   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2783   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2784   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2785   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2786   /* c0 */
2787   { REG_TABLE (REG_C0) },
2788   { REG_TABLE (REG_C1) },
2789   { "retT",             { Iw, BND }, 0 },
2790   { "retT",             { BND }, 0 },
2791   { X86_64_TABLE (X86_64_C4) },
2792   { X86_64_TABLE (X86_64_C5) },
2793   { REG_TABLE (REG_C6) },
2794   { REG_TABLE (REG_C7) },
2795   /* c8 */
2796   { "enterT",           { Iw, Ib }, 0 },
2797   { "leaveT",           { XX }, 0 },
2798   { "Jret{|f}P",        { Iw }, 0 },
2799   { "Jret{|f}P",        { XX }, 0 },
2800   { "int3",             { XX }, 0 },
2801   { "int",              { Ib }, 0 },
2802   { X86_64_TABLE (X86_64_CE) },
2803   { "iret%LP",          { XX }, 0 },
2804   /* d0 */
2805   { REG_TABLE (REG_D0) },
2806   { REG_TABLE (REG_D1) },
2807   { REG_TABLE (REG_D2) },
2808   { REG_TABLE (REG_D3) },
2809   { X86_64_TABLE (X86_64_D4) },
2810   { X86_64_TABLE (X86_64_D5) },
2811   { Bad_Opcode },
2812   { "xlat",             { DSBX }, 0 },
2813   /* d8 */
2814   { FLOAT },
2815   { FLOAT },
2816   { FLOAT },
2817   { FLOAT },
2818   { FLOAT },
2819   { FLOAT },
2820   { FLOAT },
2821   { FLOAT },
2822   /* e0 */
2823   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2824   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2825   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2826   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2827   { "inB",              { AL, Ib }, 0 },
2828   { "inG",              { zAX, Ib }, 0 },
2829   { "outB",             { Ib, AL }, 0 },
2830   { "outG",             { Ib, zAX }, 0 },
2831   /* e8 */
2832   { X86_64_TABLE (X86_64_E8) },
2833   { X86_64_TABLE (X86_64_E9) },
2834   { X86_64_TABLE (X86_64_EA) },
2835   { "jmp",              { Jb, BND }, 0 },
2836   { "inB",              { AL, indirDX }, 0 },
2837   { "inG",              { zAX, indirDX }, 0 },
2838   { "outB",             { indirDX, AL }, 0 },
2839   { "outG",             { indirDX, zAX }, 0 },
2840   /* f0 */
2841   { Bad_Opcode },       /* lock prefix */
2842   { "icebp",            { XX }, 0 },
2843   { Bad_Opcode },       /* repne */
2844   { Bad_Opcode },       /* repz */
2845   { "hlt",              { XX }, 0 },
2846   { "cmc",              { XX }, 0 },
2847   { REG_TABLE (REG_F6) },
2848   { REG_TABLE (REG_F7) },
2849   /* f8 */
2850   { "clc",              { XX }, 0 },
2851   { "stc",              { XX }, 0 },
2852   { "cli",              { XX }, 0 },
2853   { "sti",              { XX }, 0 },
2854   { "cld",              { XX }, 0 },
2855   { "std",              { XX }, 0 },
2856   { REG_TABLE (REG_FE) },
2857   { REG_TABLE (REG_FF) },
2858 };
2859
2860 static const struct dis386 dis386_twobyte[] = {
2861   /* 00 */
2862   { REG_TABLE (REG_0F00 ) },
2863   { REG_TABLE (REG_0F01 ) },
2864   { "larS",             { Gv, Ew }, 0 },
2865   { "lslS",             { Gv, Ew }, 0 },
2866   { Bad_Opcode },
2867   { "syscall",          { XX }, 0 },
2868   { "clts",             { XX }, 0 },
2869   { "sysret%LP",                { XX }, 0 },
2870   /* 08 */
2871   { "invd",             { XX }, 0 },
2872   { "wbinvd",           { XX }, 0 },
2873   { Bad_Opcode },
2874   { "ud2",              { XX }, 0 },
2875   { Bad_Opcode },
2876   { REG_TABLE (REG_0F0D) },
2877   { "femms",            { XX }, 0 },
2878   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2879   /* 10 */
2880   { PREFIX_TABLE (PREFIX_0F10) },
2881   { PREFIX_TABLE (PREFIX_0F11) },
2882   { PREFIX_TABLE (PREFIX_0F12) },
2883   { MOD_TABLE (MOD_0F13) },
2884   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2885   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2886   { PREFIX_TABLE (PREFIX_0F16) },
2887   { MOD_TABLE (MOD_0F17) },
2888   /* 18 */
2889   { REG_TABLE (REG_0F18) },
2890   { "nopQ",             { Ev }, 0 },
2891   { PREFIX_TABLE (PREFIX_0F1A) },
2892   { PREFIX_TABLE (PREFIX_0F1B) },
2893   { "nopQ",             { Ev }, 0 },
2894   { "nopQ",             { Ev }, 0 },
2895   { PREFIX_TABLE (PREFIX_0F1E) },
2896   { "nopQ",             { Ev }, 0 },
2897   /* 20 */
2898   { "movZ",             { Rm, Cm }, 0 },
2899   { "movZ",             { Rm, Dm }, 0 },
2900   { "movZ",             { Cm, Rm }, 0 },
2901   { "movZ",             { Dm, Rm }, 0 },
2902   { MOD_TABLE (MOD_0F24) },
2903   { Bad_Opcode },
2904   { MOD_TABLE (MOD_0F26) },
2905   { Bad_Opcode },
2906   /* 28 */
2907   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2908   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2909   { PREFIX_TABLE (PREFIX_0F2A) },
2910   { PREFIX_TABLE (PREFIX_0F2B) },
2911   { PREFIX_TABLE (PREFIX_0F2C) },
2912   { PREFIX_TABLE (PREFIX_0F2D) },
2913   { PREFIX_TABLE (PREFIX_0F2E) },
2914   { PREFIX_TABLE (PREFIX_0F2F) },
2915   /* 30 */
2916   { "wrmsr",            { XX }, 0 },
2917   { "rdtsc",            { XX }, 0 },
2918   { "rdmsr",            { XX }, 0 },
2919   { "rdpmc",            { XX }, 0 },
2920   { "sysenter",         { XX }, 0 },
2921   { "sysexit",          { XX }, 0 },
2922   { Bad_Opcode },
2923   { "getsec",           { XX }, 0 },
2924   /* 38 */
2925   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2926   { Bad_Opcode },
2927   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2928   { Bad_Opcode },
2929   { Bad_Opcode },
2930   { Bad_Opcode },
2931   { Bad_Opcode },
2932   { Bad_Opcode },
2933   /* 40 */
2934   { "cmovoS",           { Gv, Ev }, 0 },
2935   { "cmovnoS",          { Gv, Ev }, 0 },
2936   { "cmovbS",           { Gv, Ev }, 0 },
2937   { "cmovaeS",          { Gv, Ev }, 0 },
2938   { "cmoveS",           { Gv, Ev }, 0 },
2939   { "cmovneS",          { Gv, Ev }, 0 },
2940   { "cmovbeS",          { Gv, Ev }, 0 },
2941   { "cmovaS",           { Gv, Ev }, 0 },
2942   /* 48 */
2943   { "cmovsS",           { Gv, Ev }, 0 },
2944   { "cmovnsS",          { Gv, Ev }, 0 },
2945   { "cmovpS",           { Gv, Ev }, 0 },
2946   { "cmovnpS",          { Gv, Ev }, 0 },
2947   { "cmovlS",           { Gv, Ev }, 0 },
2948   { "cmovgeS",          { Gv, Ev }, 0 },
2949   { "cmovleS",          { Gv, Ev }, 0 },
2950   { "cmovgS",           { Gv, Ev }, 0 },
2951   /* 50 */
2952   { MOD_TABLE (MOD_0F51) },
2953   { PREFIX_TABLE (PREFIX_0F51) },
2954   { PREFIX_TABLE (PREFIX_0F52) },
2955   { PREFIX_TABLE (PREFIX_0F53) },
2956   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2957   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2958   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2959   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2960   /* 58 */
2961   { PREFIX_TABLE (PREFIX_0F58) },
2962   { PREFIX_TABLE (PREFIX_0F59) },
2963   { PREFIX_TABLE (PREFIX_0F5A) },
2964   { PREFIX_TABLE (PREFIX_0F5B) },
2965   { PREFIX_TABLE (PREFIX_0F5C) },
2966   { PREFIX_TABLE (PREFIX_0F5D) },
2967   { PREFIX_TABLE (PREFIX_0F5E) },
2968   { PREFIX_TABLE (PREFIX_0F5F) },
2969   /* 60 */
2970   { PREFIX_TABLE (PREFIX_0F60) },
2971   { PREFIX_TABLE (PREFIX_0F61) },
2972   { PREFIX_TABLE (PREFIX_0F62) },
2973   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2974   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2975   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2976   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2977   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2978   /* 68 */
2979   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2980   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2981   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2982   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2983   { PREFIX_TABLE (PREFIX_0F6C) },
2984   { PREFIX_TABLE (PREFIX_0F6D) },
2985   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2986   { PREFIX_TABLE (PREFIX_0F6F) },
2987   /* 70 */
2988   { PREFIX_TABLE (PREFIX_0F70) },
2989   { REG_TABLE (REG_0F71) },
2990   { REG_TABLE (REG_0F72) },
2991   { REG_TABLE (REG_0F73) },
2992   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2993   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2994   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2995   { "emms",             { XX }, PREFIX_OPCODE },
2996   /* 78 */
2997   { PREFIX_TABLE (PREFIX_0F78) },
2998   { PREFIX_TABLE (PREFIX_0F79) },
2999   { Bad_Opcode },
3000   { Bad_Opcode },
3001   { PREFIX_TABLE (PREFIX_0F7C) },
3002   { PREFIX_TABLE (PREFIX_0F7D) },
3003   { PREFIX_TABLE (PREFIX_0F7E) },
3004   { PREFIX_TABLE (PREFIX_0F7F) },
3005   /* 80 */
3006   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
3007   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
3008   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
3009   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
3010   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
3011   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
3012   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
3013   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
3014   /* 88 */
3015   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
3016   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
3017   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
3018   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
3019   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
3020   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
3021   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
3022   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
3023   /* 90 */
3024   { "seto",             { Eb }, 0 },
3025   { "setno",            { Eb }, 0 },
3026   { "setb",             { Eb }, 0 },
3027   { "setae",            { Eb }, 0 },
3028   { "sete",             { Eb }, 0 },
3029   { "setne",            { Eb }, 0 },
3030   { "setbe",            { Eb }, 0 },
3031   { "seta",             { Eb }, 0 },
3032   /* 98 */
3033   { "sets",             { Eb }, 0 },
3034   { "setns",            { Eb }, 0 },
3035   { "setp",             { Eb }, 0 },
3036   { "setnp",            { Eb }, 0 },
3037   { "setl",             { Eb }, 0 },
3038   { "setge",            { Eb }, 0 },
3039   { "setle",            { Eb }, 0 },
3040   { "setg",             { Eb }, 0 },
3041   /* a0 */
3042   { "pushT",            { fs }, 0 },
3043   { "popT",             { fs }, 0 },
3044   { "cpuid",            { XX }, 0 },
3045   { "btS",              { Ev, Gv }, 0 },
3046   { "shldS",            { Ev, Gv, Ib }, 0 },
3047   { "shldS",            { Ev, Gv, CL }, 0 },
3048   { REG_TABLE (REG_0FA6) },
3049   { REG_TABLE (REG_0FA7) },
3050   /* a8 */
3051   { "pushT",            { gs }, 0 },
3052   { "popT",             { gs }, 0 },
3053   { "rsm",              { XX }, 0 },
3054   { "btsS",             { Evh1, Gv }, 0 },
3055   { "shrdS",            { Ev, Gv, Ib }, 0 },
3056   { "shrdS",            { Ev, Gv, CL }, 0 },
3057   { REG_TABLE (REG_0FAE) },
3058   { "imulS",            { Gv, Ev }, 0 },
3059   /* b0 */
3060   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3061   { "cmpxchgS",         { Evh1, Gv }, 0 },
3062   { MOD_TABLE (MOD_0FB2) },
3063   { "btrS",             { Evh1, Gv }, 0 },
3064   { MOD_TABLE (MOD_0FB4) },
3065   { MOD_TABLE (MOD_0FB5) },
3066   { "movz{bR|x}",       { Gv, Eb }, 0 },
3067   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3068   /* b8 */
3069   { PREFIX_TABLE (PREFIX_0FB8) },
3070   { "ud1",              { XX }, 0 },
3071   { REG_TABLE (REG_0FBA) },
3072   { "btcS",             { Evh1, Gv }, 0 },
3073   { PREFIX_TABLE (PREFIX_0FBC) },
3074   { PREFIX_TABLE (PREFIX_0FBD) },
3075   { "movs{bR|x}",       { Gv, Eb }, 0 },
3076   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3077   /* c0 */
3078   { "xaddB",            { Ebh1, Gb }, 0 },
3079   { "xaddS",            { Evh1, Gv }, 0 },
3080   { PREFIX_TABLE (PREFIX_0FC2) },
3081   { MOD_TABLE (MOD_0FC3) },
3082   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3083   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3084   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3085   { REG_TABLE (REG_0FC7) },
3086   /* c8 */
3087   { "bswap",            { RMeAX }, 0 },
3088   { "bswap",            { RMeCX }, 0 },
3089   { "bswap",            { RMeDX }, 0 },
3090   { "bswap",            { RMeBX }, 0 },
3091   { "bswap",            { RMeSP }, 0 },
3092   { "bswap",            { RMeBP }, 0 },
3093   { "bswap",            { RMeSI }, 0 },
3094   { "bswap",            { RMeDI }, 0 },
3095   /* d0 */
3096   { PREFIX_TABLE (PREFIX_0FD0) },
3097   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3098   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3099   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3100   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3101   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3102   { PREFIX_TABLE (PREFIX_0FD6) },
3103   { MOD_TABLE (MOD_0FD7) },
3104   /* d8 */
3105   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3106   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3107   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3108   { "pand",             { MX, EM }, PREFIX_OPCODE },
3109   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3110   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3111   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3112   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3113   /* e0 */
3114   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3115   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3116   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3117   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3118   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3119   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3120   { PREFIX_TABLE (PREFIX_0FE6) },
3121   { PREFIX_TABLE (PREFIX_0FE7) },
3122   /* e8 */
3123   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3124   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3125   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3126   { "por",              { MX, EM }, PREFIX_OPCODE },
3127   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3128   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3129   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3130   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3131   /* f0 */
3132   { PREFIX_TABLE (PREFIX_0FF0) },
3133   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3134   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3135   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3136   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3137   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3138   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3139   { PREFIX_TABLE (PREFIX_0FF7) },
3140   /* f8 */
3141   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3142   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3143   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3144   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3145   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3146   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3147   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3148   { Bad_Opcode },
3149 };
3150
3151 static const unsigned char onebyte_has_modrm[256] = {
3152   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3153   /*       -------------------------------        */
3154   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3155   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3156   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3157   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3158   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3159   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3160   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3161   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3162   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3163   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3164   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3165   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3166   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3167   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3168   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3169   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3170   /*       -------------------------------        */
3171   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3172 };
3173
3174 static const unsigned char twobyte_has_modrm[256] = {
3175   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3176   /*       -------------------------------        */
3177   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3178   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3179   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3180   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3181   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3182   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3183   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3184   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3185   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3186   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3187   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3188   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3189   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3190   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3191   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3192   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3193   /*       -------------------------------        */
3194   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3195 };
3196
3197 static char obuf[100];
3198 static char *obufp;
3199 static char *mnemonicendp;
3200 static char scratchbuf[100];
3201 static unsigned char *start_codep;
3202 static unsigned char *insn_codep;
3203 static unsigned char *codep;
3204 static unsigned char *end_codep;
3205 static int last_lock_prefix;
3206 static int last_repz_prefix;
3207 static int last_repnz_prefix;
3208 static int last_data_prefix;
3209 static int last_addr_prefix;
3210 static int last_rex_prefix;
3211 static int last_seg_prefix;
3212 static int fwait_prefix;
3213 /* The active segment register prefix.  */
3214 static int active_seg_prefix;
3215 #define MAX_CODE_LENGTH 15
3216 /* We can up to 14 prefixes since the maximum instruction length is
3217    15bytes.  */
3218 static int all_prefixes[MAX_CODE_LENGTH - 1];
3219 static disassemble_info *the_info;
3220 static struct
3221   {
3222     int mod;
3223     int reg;
3224     int rm;
3225   }
3226 modrm;
3227 static unsigned char need_modrm;
3228 static struct
3229   {
3230     int scale;
3231     int index;
3232     int base;
3233   }
3234 sib;
3235 static struct
3236   {
3237     int register_specifier;
3238     int length;
3239     int prefix;
3240     int w;
3241     int evex;
3242     int r;
3243     int v;
3244     int mask_register_specifier;
3245     int zeroing;
3246     int ll;
3247     int b;
3248   }
3249 vex;
3250 static unsigned char need_vex;
3251 static unsigned char need_vex_reg;
3252 static unsigned char vex_w_done;
3253
3254 struct op
3255   {
3256     const char *name;
3257     unsigned int len;
3258   };
3259
3260 /* If we are accessing mod/rm/reg without need_modrm set, then the
3261    values are stale.  Hitting this abort likely indicates that you
3262    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3263 #define MODRM_CHECK  if (!need_modrm) abort ()
3264
3265 static const char **names64;
3266 static const char **names32;
3267 static const char **names16;
3268 static const char **names8;
3269 static const char **names8rex;
3270 static const char **names_seg;
3271 static const char *index64;
3272 static const char *index32;
3273 static const char **index16;
3274 static const char **names_bnd;
3275
3276 static const char *intel_names64[] = {
3277   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3278   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3279 };
3280 static const char *intel_names32[] = {
3281   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3282   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3283 };
3284 static const char *intel_names16[] = {
3285   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3286   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3287 };
3288 static const char *intel_names8[] = {
3289   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3290 };
3291 static const char *intel_names8rex[] = {
3292   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3293   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3294 };
3295 static const char *intel_names_seg[] = {
3296   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3297 };
3298 static const char *intel_index64 = "riz";
3299 static const char *intel_index32 = "eiz";
3300 static const char *intel_index16[] = {
3301   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3302 };
3303
3304 static const char *att_names64[] = {
3305   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3306   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3307 };
3308 static const char *att_names32[] = {
3309   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3310   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3311 };
3312 static const char *att_names16[] = {
3313   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3314   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3315 };
3316 static const char *att_names8[] = {
3317   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3318 };
3319 static const char *att_names8rex[] = {
3320   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3321   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3322 };
3323 static const char *att_names_seg[] = {
3324   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3325 };
3326 static const char *att_index64 = "%riz";
3327 static const char *att_index32 = "%eiz";
3328 static const char *att_index16[] = {
3329   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3330 };
3331
3332 static const char **names_mm;
3333 static const char *intel_names_mm[] = {
3334   "mm0", "mm1", "mm2", "mm3",
3335   "mm4", "mm5", "mm6", "mm7"
3336 };
3337 static const char *att_names_mm[] = {
3338   "%mm0", "%mm1", "%mm2", "%mm3",
3339   "%mm4", "%mm5", "%mm6", "%mm7"
3340 };
3341
3342 static const char *intel_names_bnd[] = {
3343   "bnd0", "bnd1", "bnd2", "bnd3"
3344 };
3345
3346 static const char *att_names_bnd[] = {
3347   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3348 };
3349
3350 static const char **names_xmm;
3351 static const char *intel_names_xmm[] = {
3352   "xmm0", "xmm1", "xmm2", "xmm3",
3353   "xmm4", "xmm5", "xmm6", "xmm7",
3354   "xmm8", "xmm9", "xmm10", "xmm11",
3355   "xmm12", "xmm13", "xmm14", "xmm15",
3356   "xmm16", "xmm17", "xmm18", "xmm19",
3357   "xmm20", "xmm21", "xmm22", "xmm23",
3358   "xmm24", "xmm25", "xmm26", "xmm27",
3359   "xmm28", "xmm29", "xmm30", "xmm31"
3360 };
3361 static const char *att_names_xmm[] = {
3362   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3363   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3364   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3365   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3366   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3367   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3368   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3369   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3370 };
3371
3372 static const char **names_ymm;
3373 static const char *intel_names_ymm[] = {
3374   "ymm0", "ymm1", "ymm2", "ymm3",
3375   "ymm4", "ymm5", "ymm6", "ymm7",
3376   "ymm8", "ymm9", "ymm10", "ymm11",
3377   "ymm12", "ymm13", "ymm14", "ymm15",
3378   "ymm16", "ymm17", "ymm18", "ymm19",
3379   "ymm20", "ymm21", "ymm22", "ymm23",
3380   "ymm24", "ymm25", "ymm26", "ymm27",
3381   "ymm28", "ymm29", "ymm30", "ymm31"
3382 };
3383 static const char *att_names_ymm[] = {
3384   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3385   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3386   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3387   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3388   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3389   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3390   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3391   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3392 };
3393
3394 static const char **names_zmm;
3395 static const char *intel_names_zmm[] = {
3396   "zmm0", "zmm1", "zmm2", "zmm3",
3397   "zmm4", "zmm5", "zmm6", "zmm7",
3398   "zmm8", "zmm9", "zmm10", "zmm11",
3399   "zmm12", "zmm13", "zmm14", "zmm15",
3400   "zmm16", "zmm17", "zmm18", "zmm19",
3401   "zmm20", "zmm21", "zmm22", "zmm23",
3402   "zmm24", "zmm25", "zmm26", "zmm27",
3403   "zmm28", "zmm29", "zmm30", "zmm31"
3404 };
3405 static const char *att_names_zmm[] = {
3406   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3407   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3408   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3409   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3410   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3411   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3412   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3413   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3414 };
3415
3416 static const char **names_mask;
3417 static const char *intel_names_mask[] = {
3418   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3419 };
3420 static const char *att_names_mask[] = {
3421   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3422 };
3423
3424 static const char *names_rounding[] =
3425 {
3426   "{rn-sae}",
3427   "{rd-sae}",
3428   "{ru-sae}",
3429   "{rz-sae}"
3430 };
3431
3432 static const struct dis386 reg_table[][8] = {
3433   /* REG_80 */
3434   {
3435     { "addA",   { Ebh1, Ib }, 0 },
3436     { "orA",    { Ebh1, Ib }, 0 },
3437     { "adcA",   { Ebh1, Ib }, 0 },
3438     { "sbbA",   { Ebh1, Ib }, 0 },
3439     { "andA",   { Ebh1, Ib }, 0 },
3440     { "subA",   { Ebh1, Ib }, 0 },
3441     { "xorA",   { Ebh1, Ib }, 0 },
3442     { "cmpA",   { Eb, Ib }, 0 },
3443   },
3444   /* REG_81 */
3445   {
3446     { "addQ",   { Evh1, Iv }, 0 },
3447     { "orQ",    { Evh1, Iv }, 0 },
3448     { "adcQ",   { Evh1, Iv }, 0 },
3449     { "sbbQ",   { Evh1, Iv }, 0 },
3450     { "andQ",   { Evh1, Iv }, 0 },
3451     { "subQ",   { Evh1, Iv }, 0 },
3452     { "xorQ",   { Evh1, Iv }, 0 },
3453     { "cmpQ",   { Ev, Iv }, 0 },
3454   },
3455   /* REG_83 */
3456   {
3457     { "addQ",   { Evh1, sIb }, 0 },
3458     { "orQ",    { Evh1, sIb }, 0 },
3459     { "adcQ",   { Evh1, sIb }, 0 },
3460     { "sbbQ",   { Evh1, sIb }, 0 },
3461     { "andQ",   { Evh1, sIb }, 0 },
3462     { "subQ",   { Evh1, sIb }, 0 },
3463     { "xorQ",   { Evh1, sIb }, 0 },
3464     { "cmpQ",   { Ev, sIb }, 0 },
3465   },
3466   /* REG_8F */
3467   {
3468     { "popU",   { stackEv }, 0 },
3469     { XOP_8F_TABLE (XOP_09) },
3470     { Bad_Opcode },
3471     { Bad_Opcode },
3472     { Bad_Opcode },
3473     { XOP_8F_TABLE (XOP_09) },
3474   },
3475   /* REG_C0 */
3476   {
3477     { "rolA",   { Eb, Ib }, 0 },
3478     { "rorA",   { Eb, Ib }, 0 },
3479     { "rclA",   { Eb, Ib }, 0 },
3480     { "rcrA",   { Eb, Ib }, 0 },
3481     { "shlA",   { Eb, Ib }, 0 },
3482     { "shrA",   { Eb, Ib }, 0 },
3483     { "shlA",   { Eb, Ib }, 0 },
3484     { "sarA",   { Eb, Ib }, 0 },
3485   },
3486   /* REG_C1 */
3487   {
3488     { "rolQ",   { Ev, Ib }, 0 },
3489     { "rorQ",   { Ev, Ib }, 0 },
3490     { "rclQ",   { Ev, Ib }, 0 },
3491     { "rcrQ",   { Ev, Ib }, 0 },
3492     { "shlQ",   { Ev, Ib }, 0 },
3493     { "shrQ",   { Ev, Ib }, 0 },
3494     { "shlQ",   { Ev, Ib }, 0 },
3495     { "sarQ",   { Ev, Ib }, 0 },
3496   },
3497   /* REG_C6 */
3498   {
3499     { "movA",   { Ebh3, Ib }, 0 },
3500     { Bad_Opcode },
3501     { Bad_Opcode },
3502     { Bad_Opcode },
3503     { Bad_Opcode },
3504     { Bad_Opcode },
3505     { Bad_Opcode },
3506     { MOD_TABLE (MOD_C6_REG_7) },
3507   },
3508   /* REG_C7 */
3509   {
3510     { "movQ",   { Evh3, Iv }, 0 },
3511     { Bad_Opcode },
3512     { Bad_Opcode },
3513     { Bad_Opcode },
3514     { Bad_Opcode },
3515     { Bad_Opcode },
3516     { Bad_Opcode },
3517     { MOD_TABLE (MOD_C7_REG_7) },
3518   },
3519   /* REG_D0 */
3520   {
3521     { "rolA",   { Eb, I1 }, 0 },
3522     { "rorA",   { Eb, I1 }, 0 },
3523     { "rclA",   { Eb, I1 }, 0 },
3524     { "rcrA",   { Eb, I1 }, 0 },
3525     { "shlA",   { Eb, I1 }, 0 },
3526     { "shrA",   { Eb, I1 }, 0 },
3527     { "shlA",   { Eb, I1 }, 0 },
3528     { "sarA",   { Eb, I1 }, 0 },
3529   },
3530   /* REG_D1 */
3531   {
3532     { "rolQ",   { Ev, I1 }, 0 },
3533     { "rorQ",   { Ev, I1 }, 0 },
3534     { "rclQ",   { Ev, I1 }, 0 },
3535     { "rcrQ",   { Ev, I1 }, 0 },
3536     { "shlQ",   { Ev, I1 }, 0 },
3537     { "shrQ",   { Ev, I1 }, 0 },
3538     { "shlQ",   { Ev, I1 }, 0 },
3539     { "sarQ",   { Ev, I1 }, 0 },
3540   },
3541   /* REG_D2 */
3542   {
3543     { "rolA",   { Eb, CL }, 0 },
3544     { "rorA",   { Eb, CL }, 0 },
3545     { "rclA",   { Eb, CL }, 0 },
3546     { "rcrA",   { Eb, CL }, 0 },
3547     { "shlA",   { Eb, CL }, 0 },
3548     { "shrA",   { Eb, CL }, 0 },
3549     { "shlA",   { Eb, CL }, 0 },
3550     { "sarA",   { Eb, CL }, 0 },
3551   },
3552   /* REG_D3 */
3553   {
3554     { "rolQ",   { Ev, CL }, 0 },
3555     { "rorQ",   { Ev, CL }, 0 },
3556     { "rclQ",   { Ev, CL }, 0 },
3557     { "rcrQ",   { Ev, CL }, 0 },
3558     { "shlQ",   { Ev, CL }, 0 },
3559     { "shrQ",   { Ev, CL }, 0 },
3560     { "shlQ",   { Ev, CL }, 0 },
3561     { "sarQ",   { Ev, CL }, 0 },
3562   },
3563   /* REG_F6 */
3564   {
3565     { "testA",  { Eb, Ib }, 0 },
3566     { "testA",  { Eb, Ib }, 0 },
3567     { "notA",   { Ebh1 }, 0 },
3568     { "negA",   { Ebh1 }, 0 },
3569     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3570     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3571     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3572     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3573   },
3574   /* REG_F7 */
3575   {
3576     { "testQ",  { Ev, Iv }, 0 },
3577     { "testQ",  { Ev, Iv }, 0 },
3578     { "notQ",   { Evh1 }, 0 },
3579     { "negQ",   { Evh1 }, 0 },
3580     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3581     { "imulQ",  { Ev }, 0 },
3582     { "divQ",   { Ev }, 0 },
3583     { "idivQ",  { Ev }, 0 },
3584   },
3585   /* REG_FE */
3586   {
3587     { "incA",   { Ebh1 }, 0 },
3588     { "decA",   { Ebh1 }, 0 },
3589   },
3590   /* REG_FF */
3591   {
3592     { "incQ",   { Evh1 }, 0 },
3593     { "decQ",   { Evh1 }, 0 },
3594     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3595     { MOD_TABLE (MOD_FF_REG_3) },
3596     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3597     { MOD_TABLE (MOD_FF_REG_5) },
3598     { "pushU",  { stackEv }, 0 },
3599     { Bad_Opcode },
3600   },
3601   /* REG_0F00 */
3602   {
3603     { "sldtD",  { Sv }, 0 },
3604     { "strD",   { Sv }, 0 },
3605     { "lldt",   { Ew }, 0 },
3606     { "ltr",    { Ew }, 0 },
3607     { "verr",   { Ew }, 0 },
3608     { "verw",   { Ew }, 0 },
3609     { Bad_Opcode },
3610     { Bad_Opcode },
3611   },
3612   /* REG_0F01 */
3613   {
3614     { MOD_TABLE (MOD_0F01_REG_0) },
3615     { MOD_TABLE (MOD_0F01_REG_1) },
3616     { MOD_TABLE (MOD_0F01_REG_2) },
3617     { MOD_TABLE (MOD_0F01_REG_3) },
3618     { "smswD",  { Sv }, 0 },
3619     { MOD_TABLE (MOD_0F01_REG_5) },
3620     { "lmsw",   { Ew }, 0 },
3621     { MOD_TABLE (MOD_0F01_REG_7) },
3622   },
3623   /* REG_0F0D */
3624   {
3625     { "prefetch",       { Mb }, 0 },
3626     { "prefetchw",      { Mb }, 0 },
3627     { "prefetchwt1",    { Mb }, 0 },
3628     { "prefetch",       { Mb }, 0 },
3629     { "prefetch",       { Mb }, 0 },
3630     { "prefetch",       { Mb }, 0 },
3631     { "prefetch",       { Mb }, 0 },
3632     { "prefetch",       { Mb }, 0 },
3633   },
3634   /* REG_0F18 */
3635   {
3636     { MOD_TABLE (MOD_0F18_REG_0) },
3637     { MOD_TABLE (MOD_0F18_REG_1) },
3638     { MOD_TABLE (MOD_0F18_REG_2) },
3639     { MOD_TABLE (MOD_0F18_REG_3) },
3640     { MOD_TABLE (MOD_0F18_REG_4) },
3641     { MOD_TABLE (MOD_0F18_REG_5) },
3642     { MOD_TABLE (MOD_0F18_REG_6) },
3643     { MOD_TABLE (MOD_0F18_REG_7) },
3644   },
3645   /* REG_0F1E_MOD_3 */
3646   {
3647     { "nopQ",           { Ev }, 0 },
3648     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3649     { "nopQ",           { Ev }, 0 },
3650     { "nopQ",           { Ev }, 0 },
3651     { "nopQ",           { Ev }, 0 },
3652     { "nopQ",           { Ev }, 0 },
3653     { "nopQ",           { Ev }, 0 },
3654     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3655   },
3656   /* REG_0F71 */
3657   {
3658     { Bad_Opcode },
3659     { Bad_Opcode },
3660     { MOD_TABLE (MOD_0F71_REG_2) },
3661     { Bad_Opcode },
3662     { MOD_TABLE (MOD_0F71_REG_4) },
3663     { Bad_Opcode },
3664     { MOD_TABLE (MOD_0F71_REG_6) },
3665   },
3666   /* REG_0F72 */
3667   {
3668     { Bad_Opcode },
3669     { Bad_Opcode },
3670     { MOD_TABLE (MOD_0F72_REG_2) },
3671     { Bad_Opcode },
3672     { MOD_TABLE (MOD_0F72_REG_4) },
3673     { Bad_Opcode },
3674     { MOD_TABLE (MOD_0F72_REG_6) },
3675   },
3676   /* REG_0F73 */
3677   {
3678     { Bad_Opcode },
3679     { Bad_Opcode },
3680     { MOD_TABLE (MOD_0F73_REG_2) },
3681     { MOD_TABLE (MOD_0F73_REG_3) },
3682     { Bad_Opcode },
3683     { Bad_Opcode },
3684     { MOD_TABLE (MOD_0F73_REG_6) },
3685     { MOD_TABLE (MOD_0F73_REG_7) },
3686   },
3687   /* REG_0FA6 */
3688   {
3689     { "montmul",        { { OP_0f07, 0 } }, 0 },
3690     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3691     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3692   },
3693   /* REG_0FA7 */
3694   {
3695     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3696     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3697     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3698     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3699     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3700     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3701   },
3702   /* REG_0FAE */
3703   {
3704     { MOD_TABLE (MOD_0FAE_REG_0) },
3705     { MOD_TABLE (MOD_0FAE_REG_1) },
3706     { MOD_TABLE (MOD_0FAE_REG_2) },
3707     { MOD_TABLE (MOD_0FAE_REG_3) },
3708     { MOD_TABLE (MOD_0FAE_REG_4) },
3709     { MOD_TABLE (MOD_0FAE_REG_5) },
3710     { MOD_TABLE (MOD_0FAE_REG_6) },
3711     { MOD_TABLE (MOD_0FAE_REG_7) },
3712   },
3713   /* REG_0FBA */
3714   {
3715     { Bad_Opcode },
3716     { Bad_Opcode },
3717     { Bad_Opcode },
3718     { Bad_Opcode },
3719     { "btQ",    { Ev, Ib }, 0 },
3720     { "btsQ",   { Evh1, Ib }, 0 },
3721     { "btrQ",   { Evh1, Ib }, 0 },
3722     { "btcQ",   { Evh1, Ib }, 0 },
3723   },
3724   /* REG_0FC7 */
3725   {
3726     { Bad_Opcode },
3727     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3728     { Bad_Opcode },
3729     { MOD_TABLE (MOD_0FC7_REG_3) },
3730     { MOD_TABLE (MOD_0FC7_REG_4) },
3731     { MOD_TABLE (MOD_0FC7_REG_5) },
3732     { MOD_TABLE (MOD_0FC7_REG_6) },
3733     { MOD_TABLE (MOD_0FC7_REG_7) },
3734   },
3735   /* REG_VEX_0F71 */
3736   {
3737     { Bad_Opcode },
3738     { Bad_Opcode },
3739     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3740     { Bad_Opcode },
3741     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3742     { Bad_Opcode },
3743     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3744   },
3745   /* REG_VEX_0F72 */
3746   {
3747     { Bad_Opcode },
3748     { Bad_Opcode },
3749     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3750     { Bad_Opcode },
3751     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3752     { Bad_Opcode },
3753     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3754   },
3755   /* REG_VEX_0F73 */
3756   {
3757     { Bad_Opcode },
3758     { Bad_Opcode },
3759     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3760     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3761     { Bad_Opcode },
3762     { Bad_Opcode },
3763     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3764     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3765   },
3766   /* REG_VEX_0FAE */
3767   {
3768     { Bad_Opcode },
3769     { Bad_Opcode },
3770     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3771     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3772   },
3773   /* REG_VEX_0F38F3 */
3774   {
3775     { Bad_Opcode },
3776     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3777     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3778     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3779   },
3780   /* REG_XOP_LWPCB */
3781   {
3782     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3783     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3784   },
3785   /* REG_XOP_LWP */
3786   {
3787     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3788     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3789   },
3790   /* REG_XOP_TBM_01 */
3791   {
3792     { Bad_Opcode },
3793     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3794     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3795     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3796     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3797     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3798     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3799     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3800   },
3801   /* REG_XOP_TBM_02 */
3802   {
3803     { Bad_Opcode },
3804     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3805     { Bad_Opcode },
3806     { Bad_Opcode },
3807     { Bad_Opcode },
3808     { Bad_Opcode },
3809     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3810   },
3811 #define NEED_REG_TABLE
3812 #include "i386-dis-evex.h"
3813 #undef NEED_REG_TABLE
3814 };
3815
3816 static const struct dis386 prefix_table[][4] = {
3817   /* PREFIX_90 */
3818   {
3819     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3820     { "pause", { XX }, 0 },
3821     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3822     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3823   },
3824
3825   /* PREFIX_MOD_0_0F01_REG_5 */
3826   {
3827     { Bad_Opcode },
3828     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3829   },
3830
3831   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3832   {
3833     { Bad_Opcode },
3834     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3835   },
3836
3837   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3838   {
3839     { Bad_Opcode },
3840     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3841   },
3842
3843   /* PREFIX_0F10 */
3844   {
3845     { "movups", { XM, EXx }, PREFIX_OPCODE },
3846     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3847     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3848     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3849   },
3850
3851   /* PREFIX_0F11 */
3852   {
3853     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3854     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3855     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3856     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3857   },
3858
3859   /* PREFIX_0F12 */
3860   {
3861     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3862     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3863     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3864     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3865   },
3866
3867   /* PREFIX_0F16 */
3868   {
3869     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3870     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3871     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3872   },
3873
3874   /* PREFIX_0F1A */
3875   {
3876     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3877     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3878     { "bndmov", { Gbnd, Ebnd }, 0 },
3879     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3880   },
3881
3882   /* PREFIX_0F1B */
3883   {
3884     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3885     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3886     { "bndmov", { Ebnd, Gbnd }, 0 },
3887     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3888   },
3889
3890   /* PREFIX_0F1E */
3891   {
3892     { "nopQ",   { Ev }, PREFIX_OPCODE },
3893     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3894     { "nopQ",   { Ev }, PREFIX_OPCODE },
3895     { "nopQ",   { Ev }, PREFIX_OPCODE },
3896   },
3897
3898   /* PREFIX_0F2A */
3899   {
3900     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3901     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3902     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3903     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3904   },
3905
3906   /* PREFIX_0F2B */
3907   {
3908     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3909     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3910     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3911     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3912   },
3913
3914   /* PREFIX_0F2C */
3915   {
3916     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3917     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3918     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3919     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3920   },
3921
3922   /* PREFIX_0F2D */
3923   {
3924     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3925     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3926     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3927     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3928   },
3929
3930   /* PREFIX_0F2E */
3931   {
3932     { "ucomiss",{ XM, EXd }, 0 },
3933     { Bad_Opcode },
3934     { "ucomisd",{ XM, EXq }, 0 },
3935   },
3936
3937   /* PREFIX_0F2F */
3938   {
3939     { "comiss", { XM, EXd }, 0 },
3940     { Bad_Opcode },
3941     { "comisd", { XM, EXq }, 0 },
3942   },
3943
3944   /* PREFIX_0F51 */
3945   {
3946     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3947     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3948     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3949     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3950   },
3951
3952   /* PREFIX_0F52 */
3953   {
3954     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3955     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3956   },
3957
3958   /* PREFIX_0F53 */
3959   {
3960     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3961     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3962   },
3963
3964   /* PREFIX_0F58 */
3965   {
3966     { "addps", { XM, EXx }, PREFIX_OPCODE },
3967     { "addss", { XM, EXd }, PREFIX_OPCODE },
3968     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3969     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3970   },
3971
3972   /* PREFIX_0F59 */
3973   {
3974     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3975     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3976     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3977     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3978   },
3979
3980   /* PREFIX_0F5A */
3981   {
3982     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3983     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3984     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3985     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3986   },
3987
3988   /* PREFIX_0F5B */
3989   {
3990     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3991     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3992     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3993   },
3994
3995   /* PREFIX_0F5C */
3996   {
3997     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3998     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3999     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
4000     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
4001   },
4002
4003   /* PREFIX_0F5D */
4004   {
4005     { "minps",  { XM, EXx }, PREFIX_OPCODE },
4006     { "minss",  { XM, EXd }, PREFIX_OPCODE },
4007     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
4008     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
4009   },
4010
4011   /* PREFIX_0F5E */
4012   {
4013     { "divps",  { XM, EXx }, PREFIX_OPCODE },
4014     { "divss",  { XM, EXd }, PREFIX_OPCODE },
4015     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
4016     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
4017   },
4018
4019   /* PREFIX_0F5F */
4020   {
4021     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
4022     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
4023     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
4024     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
4025   },
4026
4027   /* PREFIX_0F60 */
4028   {
4029     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
4030     { Bad_Opcode },
4031     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
4032   },
4033
4034   /* PREFIX_0F61 */
4035   {
4036     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
4037     { Bad_Opcode },
4038     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4039   },
4040
4041   /* PREFIX_0F62 */
4042   {
4043     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4044     { Bad_Opcode },
4045     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4046   },
4047
4048   /* PREFIX_0F6C */
4049   {
4050     { Bad_Opcode },
4051     { Bad_Opcode },
4052     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4053   },
4054
4055   /* PREFIX_0F6D */
4056   {
4057     { Bad_Opcode },
4058     { Bad_Opcode },
4059     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4060   },
4061
4062   /* PREFIX_0F6F */
4063   {
4064     { "movq",   { MX, EM }, PREFIX_OPCODE },
4065     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4066     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4067   },
4068
4069   /* PREFIX_0F70 */
4070   {
4071     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4072     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4073     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4074     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4075   },
4076
4077   /* PREFIX_0F73_REG_3 */
4078   {
4079     { Bad_Opcode },
4080     { Bad_Opcode },
4081     { "psrldq", { XS, Ib }, 0 },
4082   },
4083
4084   /* PREFIX_0F73_REG_7 */
4085   {
4086     { Bad_Opcode },
4087     { Bad_Opcode },
4088     { "pslldq", { XS, Ib }, 0 },
4089   },
4090
4091   /* PREFIX_0F78 */
4092   {
4093     {"vmread",  { Em, Gm }, 0 },
4094     { Bad_Opcode },
4095     {"extrq",   { XS, Ib, Ib }, 0 },
4096     {"insertq", { XM, XS, Ib, Ib }, 0 },
4097   },
4098
4099   /* PREFIX_0F79 */
4100   {
4101     {"vmwrite", { Gm, Em }, 0 },
4102     { Bad_Opcode },
4103     {"extrq",   { XM, XS }, 0 },
4104     {"insertq", { XM, XS }, 0 },
4105   },
4106
4107   /* PREFIX_0F7C */
4108   {
4109     { Bad_Opcode },
4110     { Bad_Opcode },
4111     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4112     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4113   },
4114
4115   /* PREFIX_0F7D */
4116   {
4117     { Bad_Opcode },
4118     { Bad_Opcode },
4119     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4120     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4121   },
4122
4123   /* PREFIX_0F7E */
4124   {
4125     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4126     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4127     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4128   },
4129
4130   /* PREFIX_0F7F */
4131   {
4132     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4133     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4134     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4135   },
4136
4137   /* PREFIX_0FAE_REG_0 */
4138   {
4139     { Bad_Opcode },
4140     { "rdfsbase", { Ev }, 0 },
4141   },
4142
4143   /* PREFIX_0FAE_REG_1 */
4144   {
4145     { Bad_Opcode },
4146     { "rdgsbase", { Ev }, 0 },
4147   },
4148
4149   /* PREFIX_0FAE_REG_2 */
4150   {
4151     { Bad_Opcode },
4152     { "wrfsbase", { Ev }, 0 },
4153   },
4154
4155   /* PREFIX_0FAE_REG_3 */
4156   {
4157     { Bad_Opcode },
4158     { "wrgsbase", { Ev }, 0 },
4159   },
4160
4161   /* PREFIX_MOD_0_0FAE_REG_4 */
4162   {
4163     { "xsave",  { FXSAVE }, 0 },
4164     { "ptwrite%LQ", { Edq }, 0 },
4165   },
4166
4167   /* PREFIX_MOD_3_0FAE_REG_4 */
4168   {
4169     { Bad_Opcode },
4170     { "ptwrite%LQ", { Edq }, 0 },
4171   },
4172
4173   /* PREFIX_MOD_0_0FAE_REG_5 */
4174   {
4175     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4176   },
4177
4178   /* PREFIX_MOD_3_0FAE_REG_5 */
4179   {
4180     { "lfence",         { Skip_MODRM }, 0 },
4181     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4182   },
4183
4184   /* PREFIX_0FAE_REG_6 */
4185   {
4186     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4187     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4188     { "clwb",   { Mb }, PREFIX_OPCODE },
4189   },
4190
4191   /* PREFIX_0FAE_REG_7 */
4192   {
4193     { "clflush",        { Mb }, 0 },
4194     { Bad_Opcode },
4195     { "clflushopt",     { Mb }, 0 },
4196   },
4197
4198   /* PREFIX_0FB8 */
4199   {
4200     { Bad_Opcode },
4201     { "popcntS", { Gv, Ev }, 0 },
4202   },
4203
4204   /* PREFIX_0FBC */
4205   {
4206     { "bsfS",   { Gv, Ev }, 0 },
4207     { "tzcntS", { Gv, Ev }, 0 },
4208     { "bsfS",   { Gv, Ev }, 0 },
4209   },
4210
4211   /* PREFIX_0FBD */
4212   {
4213     { "bsrS",   { Gv, Ev }, 0 },
4214     { "lzcntS", { Gv, Ev }, 0 },
4215     { "bsrS",   { Gv, Ev }, 0 },
4216   },
4217
4218   /* PREFIX_0FC2 */
4219   {
4220     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4221     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4222     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4223     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4224   },
4225
4226   /* PREFIX_MOD_0_0FC3 */
4227   {
4228     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4229   },
4230
4231   /* PREFIX_MOD_0_0FC7_REG_6 */
4232   {
4233     { "vmptrld",{ Mq }, 0 },
4234     { "vmxon",  { Mq }, 0 },
4235     { "vmclear",{ Mq }, 0 },
4236   },
4237
4238   /* PREFIX_MOD_3_0FC7_REG_6 */
4239   {
4240     { "rdrand", { Ev }, 0 },
4241     { Bad_Opcode },
4242     { "rdrand", { Ev }, 0 }
4243   },
4244
4245   /* PREFIX_MOD_3_0FC7_REG_7 */
4246   {
4247     { "rdseed", { Ev }, 0 },
4248     { "rdpid",  { Em }, 0 },
4249     { "rdseed", { Ev }, 0 },
4250   },
4251
4252   /* PREFIX_0FD0 */
4253   {
4254     { Bad_Opcode },
4255     { Bad_Opcode },
4256     { "addsubpd", { XM, EXx }, 0 },
4257     { "addsubps", { XM, EXx }, 0 },
4258   },
4259
4260   /* PREFIX_0FD6 */
4261   {
4262     { Bad_Opcode },
4263     { "movq2dq",{ XM, MS }, 0 },
4264     { "movq",   { EXqS, XM }, 0 },
4265     { "movdq2q",{ MX, XS }, 0 },
4266   },
4267
4268   /* PREFIX_0FE6 */
4269   {
4270     { Bad_Opcode },
4271     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4272     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4273     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4274   },
4275
4276   /* PREFIX_0FE7 */
4277   {
4278     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4279     { Bad_Opcode },
4280     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4281   },
4282
4283   /* PREFIX_0FF0 */
4284   {
4285     { Bad_Opcode },
4286     { Bad_Opcode },
4287     { Bad_Opcode },
4288     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4289   },
4290
4291   /* PREFIX_0FF7 */
4292   {
4293     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4294     { Bad_Opcode },
4295     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4296   },
4297
4298   /* PREFIX_0F3810 */
4299   {
4300     { Bad_Opcode },
4301     { Bad_Opcode },
4302     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4303   },
4304
4305   /* PREFIX_0F3814 */
4306   {
4307     { Bad_Opcode },
4308     { Bad_Opcode },
4309     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4310   },
4311
4312   /* PREFIX_0F3815 */
4313   {
4314     { Bad_Opcode },
4315     { Bad_Opcode },
4316     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4317   },
4318
4319   /* PREFIX_0F3817 */
4320   {
4321     { Bad_Opcode },
4322     { Bad_Opcode },
4323     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4324   },
4325
4326   /* PREFIX_0F3820 */
4327   {
4328     { Bad_Opcode },
4329     { Bad_Opcode },
4330     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4331   },
4332
4333   /* PREFIX_0F3821 */
4334   {
4335     { Bad_Opcode },
4336     { Bad_Opcode },
4337     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4338   },
4339
4340   /* PREFIX_0F3822 */
4341   {
4342     { Bad_Opcode },
4343     { Bad_Opcode },
4344     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4345   },
4346
4347   /* PREFIX_0F3823 */
4348   {
4349     { Bad_Opcode },
4350     { Bad_Opcode },
4351     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4352   },
4353
4354   /* PREFIX_0F3824 */
4355   {
4356     { Bad_Opcode },
4357     { Bad_Opcode },
4358     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4359   },
4360
4361   /* PREFIX_0F3825 */
4362   {
4363     { Bad_Opcode },
4364     { Bad_Opcode },
4365     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4366   },
4367
4368   /* PREFIX_0F3828 */
4369   {
4370     { Bad_Opcode },
4371     { Bad_Opcode },
4372     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4373   },
4374
4375   /* PREFIX_0F3829 */
4376   {
4377     { Bad_Opcode },
4378     { Bad_Opcode },
4379     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4380   },
4381
4382   /* PREFIX_0F382A */
4383   {
4384     { Bad_Opcode },
4385     { Bad_Opcode },
4386     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4387   },
4388
4389   /* PREFIX_0F382B */
4390   {
4391     { Bad_Opcode },
4392     { Bad_Opcode },
4393     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4394   },
4395
4396   /* PREFIX_0F3830 */
4397   {
4398     { Bad_Opcode },
4399     { Bad_Opcode },
4400     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4401   },
4402
4403   /* PREFIX_0F3831 */
4404   {
4405     { Bad_Opcode },
4406     { Bad_Opcode },
4407     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4408   },
4409
4410   /* PREFIX_0F3832 */
4411   {
4412     { Bad_Opcode },
4413     { Bad_Opcode },
4414     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4415   },
4416
4417   /* PREFIX_0F3833 */
4418   {
4419     { Bad_Opcode },
4420     { Bad_Opcode },
4421     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4422   },
4423
4424   /* PREFIX_0F3834 */
4425   {
4426     { Bad_Opcode },
4427     { Bad_Opcode },
4428     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4429   },
4430
4431   /* PREFIX_0F3835 */
4432   {
4433     { Bad_Opcode },
4434     { Bad_Opcode },
4435     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4436   },
4437
4438   /* PREFIX_0F3837 */
4439   {
4440     { Bad_Opcode },
4441     { Bad_Opcode },
4442     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4443   },
4444
4445   /* PREFIX_0F3838 */
4446   {
4447     { Bad_Opcode },
4448     { Bad_Opcode },
4449     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4450   },
4451
4452   /* PREFIX_0F3839 */
4453   {
4454     { Bad_Opcode },
4455     { Bad_Opcode },
4456     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4457   },
4458
4459   /* PREFIX_0F383A */
4460   {
4461     { Bad_Opcode },
4462     { Bad_Opcode },
4463     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4464   },
4465
4466   /* PREFIX_0F383B */
4467   {
4468     { Bad_Opcode },
4469     { Bad_Opcode },
4470     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4471   },
4472
4473   /* PREFIX_0F383C */
4474   {
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4478   },
4479
4480   /* PREFIX_0F383D */
4481   {
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4485   },
4486
4487   /* PREFIX_0F383E */
4488   {
4489     { Bad_Opcode },
4490     { Bad_Opcode },
4491     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4492   },
4493
4494   /* PREFIX_0F383F */
4495   {
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4499   },
4500
4501   /* PREFIX_0F3840 */
4502   {
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4506   },
4507
4508   /* PREFIX_0F3841 */
4509   {
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4513   },
4514
4515   /* PREFIX_0F3880 */
4516   {
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4520   },
4521
4522   /* PREFIX_0F3881 */
4523   {
4524     { Bad_Opcode },
4525     { Bad_Opcode },
4526     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4527   },
4528
4529   /* PREFIX_0F3882 */
4530   {
4531     { Bad_Opcode },
4532     { Bad_Opcode },
4533     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4534   },
4535
4536   /* PREFIX_0F38C8 */
4537   {
4538     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4539   },
4540
4541   /* PREFIX_0F38C9 */
4542   {
4543     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4544   },
4545
4546   /* PREFIX_0F38CA */
4547   {
4548     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4549   },
4550
4551   /* PREFIX_0F38CB */
4552   {
4553     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4554   },
4555
4556   /* PREFIX_0F38CC */
4557   {
4558     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4559   },
4560
4561   /* PREFIX_0F38CD */
4562   {
4563     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4564   },
4565
4566   /* PREFIX_0F38CF */
4567   {
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F38DB */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4578   },
4579
4580   /* PREFIX_0F38DC */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4585   },
4586
4587   /* PREFIX_0F38DD */
4588   {
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4592   },
4593
4594   /* PREFIX_0F38DE */
4595   {
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4599   },
4600
4601   /* PREFIX_0F38DF */
4602   {
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4606   },
4607
4608   /* PREFIX_0F38F0 */
4609   {
4610     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4611     { Bad_Opcode },
4612     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4613     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4614   },
4615
4616   /* PREFIX_0F38F1 */
4617   {
4618     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4619     { Bad_Opcode },
4620     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4621     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4622   },
4623
4624   /* PREFIX_0F38F5 */
4625   {
4626     { Bad_Opcode },
4627     { Bad_Opcode },
4628     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4629   },
4630
4631   /* PREFIX_0F38F6 */
4632   {
4633     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4634     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4635     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4636     { Bad_Opcode },
4637   },
4638
4639   /* PREFIX_0F3A08 */
4640   {
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4644   },
4645
4646   /* PREFIX_0F3A09 */
4647   {
4648     { Bad_Opcode },
4649     { Bad_Opcode },
4650     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4651   },
4652
4653   /* PREFIX_0F3A0A */
4654   {
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4658   },
4659
4660   /* PREFIX_0F3A0B */
4661   {
4662     { Bad_Opcode },
4663     { Bad_Opcode },
4664     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4665   },
4666
4667   /* PREFIX_0F3A0C */
4668   {
4669     { Bad_Opcode },
4670     { Bad_Opcode },
4671     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4672   },
4673
4674   /* PREFIX_0F3A0D */
4675   {
4676     { Bad_Opcode },
4677     { Bad_Opcode },
4678     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4679   },
4680
4681   /* PREFIX_0F3A0E */
4682   {
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4686   },
4687
4688   /* PREFIX_0F3A14 */
4689   {
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4693   },
4694
4695   /* PREFIX_0F3A15 */
4696   {
4697     { Bad_Opcode },
4698     { Bad_Opcode },
4699     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4700   },
4701
4702   /* PREFIX_0F3A16 */
4703   {
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4707   },
4708
4709   /* PREFIX_0F3A17 */
4710   {
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4714   },
4715
4716   /* PREFIX_0F3A20 */
4717   {
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4721   },
4722
4723   /* PREFIX_0F3A21 */
4724   {
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4728   },
4729
4730   /* PREFIX_0F3A22 */
4731   {
4732     { Bad_Opcode },
4733     { Bad_Opcode },
4734     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4735   },
4736
4737   /* PREFIX_0F3A40 */
4738   {
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4742   },
4743
4744   /* PREFIX_0F3A41 */
4745   {
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4749   },
4750
4751   /* PREFIX_0F3A42 */
4752   {
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4756   },
4757
4758   /* PREFIX_0F3A44 */
4759   {
4760     { Bad_Opcode },
4761     { Bad_Opcode },
4762     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4763   },
4764
4765   /* PREFIX_0F3A60 */
4766   {
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4770   },
4771
4772   /* PREFIX_0F3A61 */
4773   {
4774     { Bad_Opcode },
4775     { Bad_Opcode },
4776     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4777   },
4778
4779   /* PREFIX_0F3A62 */
4780   {
4781     { Bad_Opcode },
4782     { Bad_Opcode },
4783     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4784   },
4785
4786   /* PREFIX_0F3A63 */
4787   {
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4791   },
4792
4793   /* PREFIX_0F3ACC */
4794   {
4795     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4796   },
4797
4798   /* PREFIX_0F3ACE */
4799   {
4800     { Bad_Opcode },
4801     { Bad_Opcode },
4802     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4803   },
4804
4805   /* PREFIX_0F3ACF */
4806   {
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4810   },
4811
4812   /* PREFIX_0F3ADF */
4813   {
4814     { Bad_Opcode },
4815     { Bad_Opcode },
4816     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4817   },
4818
4819   /* PREFIX_VEX_0F10 */
4820   {
4821     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4822     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4823     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4824     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4825   },
4826
4827   /* PREFIX_VEX_0F11 */
4828   {
4829     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4830     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4831     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4832     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4833   },
4834
4835   /* PREFIX_VEX_0F12 */
4836   {
4837     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4838     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4839     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4840     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4841   },
4842
4843   /* PREFIX_VEX_0F16 */
4844   {
4845     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4846     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4847     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4848   },
4849
4850   /* PREFIX_VEX_0F2A */
4851   {
4852     { Bad_Opcode },
4853     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4854     { Bad_Opcode },
4855     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4856   },
4857
4858   /* PREFIX_VEX_0F2C */
4859   {
4860     { Bad_Opcode },
4861     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4862     { Bad_Opcode },
4863     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4864   },
4865
4866   /* PREFIX_VEX_0F2D */
4867   {
4868     { Bad_Opcode },
4869     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4870     { Bad_Opcode },
4871     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4872   },
4873
4874   /* PREFIX_VEX_0F2E */
4875   {
4876     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4877     { Bad_Opcode },
4878     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4879   },
4880
4881   /* PREFIX_VEX_0F2F */
4882   {
4883     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4884     { Bad_Opcode },
4885     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4886   },
4887
4888   /* PREFIX_VEX_0F41 */
4889   {
4890     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4891     { Bad_Opcode },
4892     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4893   },
4894
4895   /* PREFIX_VEX_0F42 */
4896   {
4897     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4898     { Bad_Opcode },
4899     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4900   },
4901
4902   /* PREFIX_VEX_0F44 */
4903   {
4904     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4905     { Bad_Opcode },
4906     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4907   },
4908
4909   /* PREFIX_VEX_0F45 */
4910   {
4911     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4912     { Bad_Opcode },
4913     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4914   },
4915
4916   /* PREFIX_VEX_0F46 */
4917   {
4918     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4919     { Bad_Opcode },
4920     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4921   },
4922
4923   /* PREFIX_VEX_0F47 */
4924   {
4925     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4926     { Bad_Opcode },
4927     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4928   },
4929
4930   /* PREFIX_VEX_0F4A */
4931   {
4932     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4933     { Bad_Opcode },
4934     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4935   },
4936
4937   /* PREFIX_VEX_0F4B */
4938   {
4939     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4940     { Bad_Opcode },
4941     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4942   },
4943
4944   /* PREFIX_VEX_0F51 */
4945   {
4946     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4947     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4948     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4949     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4950   },
4951
4952   /* PREFIX_VEX_0F52 */
4953   {
4954     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4955     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4956   },
4957
4958   /* PREFIX_VEX_0F53 */
4959   {
4960     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4961     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4962   },
4963
4964   /* PREFIX_VEX_0F58 */
4965   {
4966     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4967     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4968     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4969     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4970   },
4971
4972   /* PREFIX_VEX_0F59 */
4973   {
4974     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4975     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4976     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4977     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4978   },
4979
4980   /* PREFIX_VEX_0F5A */
4981   {
4982     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4983     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4984     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4985     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4986   },
4987
4988   /* PREFIX_VEX_0F5B */
4989   {
4990     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4991     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4992     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4993   },
4994
4995   /* PREFIX_VEX_0F5C */
4996   {
4997     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4998     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4999     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
5000     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
5001   },
5002
5003   /* PREFIX_VEX_0F5D */
5004   {
5005     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
5006     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
5007     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
5008     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
5009   },
5010
5011   /* PREFIX_VEX_0F5E */
5012   {
5013     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
5014     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
5015     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
5016     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
5017   },
5018
5019   /* PREFIX_VEX_0F5F */
5020   {
5021     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
5022     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
5023     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
5024     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
5025   },
5026
5027   /* PREFIX_VEX_0F60 */
5028   {
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { VEX_W_TABLE (VEX_W_0F60_P_2) },
5032   },
5033
5034   /* PREFIX_VEX_0F61 */
5035   {
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { VEX_W_TABLE (VEX_W_0F61_P_2) },
5039   },
5040
5041   /* PREFIX_VEX_0F62 */
5042   {
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { VEX_W_TABLE (VEX_W_0F62_P_2) },
5046   },
5047
5048   /* PREFIX_VEX_0F63 */
5049   {
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { VEX_W_TABLE (VEX_W_0F63_P_2) },
5053   },
5054
5055   /* PREFIX_VEX_0F64 */
5056   {
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { VEX_W_TABLE (VEX_W_0F64_P_2) },
5060   },
5061
5062   /* PREFIX_VEX_0F65 */
5063   {
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { VEX_W_TABLE (VEX_W_0F65_P_2) },
5067   },
5068
5069   /* PREFIX_VEX_0F66 */
5070   {
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { VEX_W_TABLE (VEX_W_0F66_P_2) },
5074   },
5075
5076   /* PREFIX_VEX_0F67 */
5077   {
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { VEX_W_TABLE (VEX_W_0F67_P_2) },
5081   },
5082
5083   /* PREFIX_VEX_0F68 */
5084   {
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { VEX_W_TABLE (VEX_W_0F68_P_2) },
5088   },
5089
5090   /* PREFIX_VEX_0F69 */
5091   {
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { VEX_W_TABLE (VEX_W_0F69_P_2) },
5095   },
5096
5097   /* PREFIX_VEX_0F6A */
5098   {
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5102   },
5103
5104   /* PREFIX_VEX_0F6B */
5105   {
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5109   },
5110
5111   /* PREFIX_VEX_0F6C */
5112   {
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5116   },
5117
5118   /* PREFIX_VEX_0F6D */
5119   {
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5123   },
5124
5125   /* PREFIX_VEX_0F6E */
5126   {
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5130   },
5131
5132   /* PREFIX_VEX_0F6F */
5133   {
5134     { Bad_Opcode },
5135     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5136     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5137   },
5138
5139   /* PREFIX_VEX_0F70 */
5140   {
5141     { Bad_Opcode },
5142     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5143     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5144     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5145   },
5146
5147   /* PREFIX_VEX_0F71_REG_2 */
5148   {
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5152   },
5153
5154   /* PREFIX_VEX_0F71_REG_4 */
5155   {
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5159   },
5160
5161   /* PREFIX_VEX_0F71_REG_6 */
5162   {
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5166   },
5167
5168   /* PREFIX_VEX_0F72_REG_2 */
5169   {
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5173   },
5174
5175   /* PREFIX_VEX_0F72_REG_4 */
5176   {
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5180   },
5181
5182   /* PREFIX_VEX_0F72_REG_6 */
5183   {
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5187   },
5188
5189   /* PREFIX_VEX_0F73_REG_2 */
5190   {
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5194   },
5195
5196   /* PREFIX_VEX_0F73_REG_3 */
5197   {
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5201   },
5202
5203   /* PREFIX_VEX_0F73_REG_6 */
5204   {
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5208   },
5209
5210   /* PREFIX_VEX_0F73_REG_7 */
5211   {
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5215   },
5216
5217   /* PREFIX_VEX_0F74 */
5218   {
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5222   },
5223
5224   /* PREFIX_VEX_0F75 */
5225   {
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5229   },
5230
5231   /* PREFIX_VEX_0F76 */
5232   {
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5236   },
5237
5238   /* PREFIX_VEX_0F77 */
5239   {
5240     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5241   },
5242
5243   /* PREFIX_VEX_0F7C */
5244   {
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5248     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5249   },
5250
5251   /* PREFIX_VEX_0F7D */
5252   {
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5256     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5257   },
5258
5259   /* PREFIX_VEX_0F7E */
5260   {
5261     { Bad_Opcode },
5262     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5263     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5264   },
5265
5266   /* PREFIX_VEX_0F7F */
5267   {
5268     { Bad_Opcode },
5269     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5270     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5271   },
5272
5273   /* PREFIX_VEX_0F90 */
5274   {
5275     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5276     { Bad_Opcode },
5277     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5278   },
5279
5280   /* PREFIX_VEX_0F91 */
5281   {
5282     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5283     { Bad_Opcode },
5284     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5285   },
5286
5287   /* PREFIX_VEX_0F92 */
5288   {
5289     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5290     { Bad_Opcode },
5291     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5292     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5293   },
5294
5295   /* PREFIX_VEX_0F93 */
5296   {
5297     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5298     { Bad_Opcode },
5299     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5300     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5301   },
5302
5303   /* PREFIX_VEX_0F98 */
5304   {
5305     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5306     { Bad_Opcode },
5307     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5308   },
5309
5310   /* PREFIX_VEX_0F99 */
5311   {
5312     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5313     { Bad_Opcode },
5314     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5315   },
5316
5317   /* PREFIX_VEX_0FC2 */
5318   {
5319     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5320     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5321     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5322     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5323   },
5324
5325   /* PREFIX_VEX_0FC4 */
5326   {
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5330   },
5331
5332   /* PREFIX_VEX_0FC5 */
5333   {
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5337   },
5338
5339   /* PREFIX_VEX_0FD0 */
5340   {
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5344     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5345   },
5346
5347   /* PREFIX_VEX_0FD1 */
5348   {
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5352   },
5353
5354   /* PREFIX_VEX_0FD2 */
5355   {
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5359   },
5360
5361   /* PREFIX_VEX_0FD3 */
5362   {
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5366   },
5367
5368   /* PREFIX_VEX_0FD4 */
5369   {
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5373   },
5374
5375   /* PREFIX_VEX_0FD5 */
5376   {
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5380   },
5381
5382   /* PREFIX_VEX_0FD6 */
5383   {
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5387   },
5388
5389   /* PREFIX_VEX_0FD7 */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5394   },
5395
5396   /* PREFIX_VEX_0FD8 */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5401   },
5402
5403   /* PREFIX_VEX_0FD9 */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5408   },
5409
5410   /* PREFIX_VEX_0FDA */
5411   {
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5415   },
5416
5417   /* PREFIX_VEX_0FDB */
5418   {
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5422   },
5423
5424   /* PREFIX_VEX_0FDC */
5425   {
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5429   },
5430
5431   /* PREFIX_VEX_0FDD */
5432   {
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5436   },
5437
5438   /* PREFIX_VEX_0FDE */
5439   {
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5443   },
5444
5445   /* PREFIX_VEX_0FDF */
5446   {
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5450   },
5451
5452   /* PREFIX_VEX_0FE0 */
5453   {
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5457   },
5458
5459   /* PREFIX_VEX_0FE1 */
5460   {
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5464   },
5465
5466   /* PREFIX_VEX_0FE2 */
5467   {
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5471   },
5472
5473   /* PREFIX_VEX_0FE3 */
5474   {
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5478   },
5479
5480   /* PREFIX_VEX_0FE4 */
5481   {
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5485   },
5486
5487   /* PREFIX_VEX_0FE5 */
5488   {
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5492   },
5493
5494   /* PREFIX_VEX_0FE6 */
5495   {
5496     { Bad_Opcode },
5497     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5498     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5499     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5500   },
5501
5502   /* PREFIX_VEX_0FE7 */
5503   {
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5507   },
5508
5509   /* PREFIX_VEX_0FE8 */
5510   {
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5514   },
5515
5516   /* PREFIX_VEX_0FE9 */
5517   {
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5521   },
5522
5523   /* PREFIX_VEX_0FEA */
5524   {
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5528   },
5529
5530   /* PREFIX_VEX_0FEB */
5531   {
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5535   },
5536
5537   /* PREFIX_VEX_0FEC */
5538   {
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5542   },
5543
5544   /* PREFIX_VEX_0FED */
5545   {
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5549   },
5550
5551   /* PREFIX_VEX_0FEE */
5552   {
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5556   },
5557
5558   /* PREFIX_VEX_0FEF */
5559   {
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5563   },
5564
5565   /* PREFIX_VEX_0FF0 */
5566   {
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5571   },
5572
5573   /* PREFIX_VEX_0FF1 */
5574   {
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5578   },
5579
5580   /* PREFIX_VEX_0FF2 */
5581   {
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5585   },
5586
5587   /* PREFIX_VEX_0FF3 */
5588   {
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5592   },
5593
5594   /* PREFIX_VEX_0FF4 */
5595   {
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5599   },
5600
5601   /* PREFIX_VEX_0FF5 */
5602   {
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5606   },
5607
5608   /* PREFIX_VEX_0FF6 */
5609   {
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5613   },
5614
5615   /* PREFIX_VEX_0FF7 */
5616   {
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5620   },
5621
5622   /* PREFIX_VEX_0FF8 */
5623   {
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5627   },
5628
5629   /* PREFIX_VEX_0FF9 */
5630   {
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5634   },
5635
5636   /* PREFIX_VEX_0FFA */
5637   {
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5641   },
5642
5643   /* PREFIX_VEX_0FFB */
5644   {
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5648   },
5649
5650   /* PREFIX_VEX_0FFC */
5651   {
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5655   },
5656
5657   /* PREFIX_VEX_0FFD */
5658   {
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5662   },
5663
5664   /* PREFIX_VEX_0FFE */
5665   {
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5669   },
5670
5671   /* PREFIX_VEX_0F3800 */
5672   {
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5676   },
5677
5678   /* PREFIX_VEX_0F3801 */
5679   {
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5683   },
5684
5685   /* PREFIX_VEX_0F3802 */
5686   {
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5690   },
5691
5692   /* PREFIX_VEX_0F3803 */
5693   {
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5697   },
5698
5699   /* PREFIX_VEX_0F3804 */
5700   {
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5704   },
5705
5706   /* PREFIX_VEX_0F3805 */
5707   {
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5711   },
5712
5713   /* PREFIX_VEX_0F3806 */
5714   {
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5718   },
5719
5720   /* PREFIX_VEX_0F3807 */
5721   {
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5725   },
5726
5727   /* PREFIX_VEX_0F3808 */
5728   {
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5732   },
5733
5734   /* PREFIX_VEX_0F3809 */
5735   {
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5739   },
5740
5741   /* PREFIX_VEX_0F380A */
5742   {
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5746   },
5747
5748   /* PREFIX_VEX_0F380B */
5749   {
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5753   },
5754
5755   /* PREFIX_VEX_0F380C */
5756   {
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5760   },
5761
5762   /* PREFIX_VEX_0F380D */
5763   {
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5767   },
5768
5769   /* PREFIX_VEX_0F380E */
5770   {
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5774   },
5775
5776   /* PREFIX_VEX_0F380F */
5777   {
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5781   },
5782
5783   /* PREFIX_VEX_0F3813 */
5784   {
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5788   },
5789
5790   /* PREFIX_VEX_0F3816 */
5791   {
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5795   },
5796
5797   /* PREFIX_VEX_0F3817 */
5798   {
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5802   },
5803
5804   /* PREFIX_VEX_0F3818 */
5805   {
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5809   },
5810
5811   /* PREFIX_VEX_0F3819 */
5812   {
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5816   },
5817
5818   /* PREFIX_VEX_0F381A */
5819   {
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5823   },
5824
5825   /* PREFIX_VEX_0F381C */
5826   {
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5830   },
5831
5832   /* PREFIX_VEX_0F381D */
5833   {
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5837   },
5838
5839   /* PREFIX_VEX_0F381E */
5840   {
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5844   },
5845
5846   /* PREFIX_VEX_0F3820 */
5847   {
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5851   },
5852
5853   /* PREFIX_VEX_0F3821 */
5854   {
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5858   },
5859
5860   /* PREFIX_VEX_0F3822 */
5861   {
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5865   },
5866
5867   /* PREFIX_VEX_0F3823 */
5868   {
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5872   },
5873
5874   /* PREFIX_VEX_0F3824 */
5875   {
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5879   },
5880
5881   /* PREFIX_VEX_0F3825 */
5882   {
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5886   },
5887
5888   /* PREFIX_VEX_0F3828 */
5889   {
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5893   },
5894
5895   /* PREFIX_VEX_0F3829 */
5896   {
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5900   },
5901
5902   /* PREFIX_VEX_0F382A */
5903   {
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5907   },
5908
5909   /* PREFIX_VEX_0F382B */
5910   {
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5914   },
5915
5916   /* PREFIX_VEX_0F382C */
5917   {
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5921   },
5922
5923   /* PREFIX_VEX_0F382D */
5924   {
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5928   },
5929
5930   /* PREFIX_VEX_0F382E */
5931   {
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5935   },
5936
5937   /* PREFIX_VEX_0F382F */
5938   {
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5942   },
5943
5944   /* PREFIX_VEX_0F3830 */
5945   {
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5949   },
5950
5951   /* PREFIX_VEX_0F3831 */
5952   {
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5956   },
5957
5958   /* PREFIX_VEX_0F3832 */
5959   {
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5963   },
5964
5965   /* PREFIX_VEX_0F3833 */
5966   {
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5970   },
5971
5972   /* PREFIX_VEX_0F3834 */
5973   {
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5977   },
5978
5979   /* PREFIX_VEX_0F3835 */
5980   {
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5984   },
5985
5986   /* PREFIX_VEX_0F3836 */
5987   {
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5991   },
5992
5993   /* PREFIX_VEX_0F3837 */
5994   {
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5998   },
5999
6000   /* PREFIX_VEX_0F3838 */
6001   {
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
6005   },
6006
6007   /* PREFIX_VEX_0F3839 */
6008   {
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
6012   },
6013
6014   /* PREFIX_VEX_0F383A */
6015   {
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
6019   },
6020
6021   /* PREFIX_VEX_0F383B */
6022   {
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
6026   },
6027
6028   /* PREFIX_VEX_0F383C */
6029   {
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
6033   },
6034
6035   /* PREFIX_VEX_0F383D */
6036   {
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
6040   },
6041
6042   /* PREFIX_VEX_0F383E */
6043   {
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
6047   },
6048
6049   /* PREFIX_VEX_0F383F */
6050   {
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
6054   },
6055
6056   /* PREFIX_VEX_0F3840 */
6057   {
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6061   },
6062
6063   /* PREFIX_VEX_0F3841 */
6064   {
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6068   },
6069
6070   /* PREFIX_VEX_0F3845 */
6071   {
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6075   },
6076
6077   /* PREFIX_VEX_0F3846 */
6078   {
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6082   },
6083
6084   /* PREFIX_VEX_0F3847 */
6085   {
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6089   },
6090
6091   /* PREFIX_VEX_0F3858 */
6092   {
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6096   },
6097
6098   /* PREFIX_VEX_0F3859 */
6099   {
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6103   },
6104
6105   /* PREFIX_VEX_0F385A */
6106   {
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6110   },
6111
6112   /* PREFIX_VEX_0F3878 */
6113   {
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6117   },
6118
6119   /* PREFIX_VEX_0F3879 */
6120   {
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6124   },
6125
6126   /* PREFIX_VEX_0F388C */
6127   {
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6131   },
6132
6133   /* PREFIX_VEX_0F388E */
6134   {
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6138   },
6139
6140   /* PREFIX_VEX_0F3890 */
6141   {
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6145   },
6146
6147   /* PREFIX_VEX_0F3891 */
6148   {
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6152   },
6153
6154   /* PREFIX_VEX_0F3892 */
6155   {
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6159   },
6160
6161   /* PREFIX_VEX_0F3893 */
6162   {
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6166   },
6167
6168   /* PREFIX_VEX_0F3896 */
6169   {
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6173   },
6174
6175   /* PREFIX_VEX_0F3897 */
6176   {
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6180   },
6181
6182   /* PREFIX_VEX_0F3898 */
6183   {
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6187   },
6188
6189   /* PREFIX_VEX_0F3899 */
6190   {
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6194   },
6195
6196   /* PREFIX_VEX_0F389A */
6197   {
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6201   },
6202
6203   /* PREFIX_VEX_0F389B */
6204   {
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6208   },
6209
6210   /* PREFIX_VEX_0F389C */
6211   {
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6215   },
6216
6217   /* PREFIX_VEX_0F389D */
6218   {
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6222   },
6223
6224   /* PREFIX_VEX_0F389E */
6225   {
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6229   },
6230
6231   /* PREFIX_VEX_0F389F */
6232   {
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6236   },
6237
6238   /* PREFIX_VEX_0F38A6 */
6239   {
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6243     { Bad_Opcode },
6244   },
6245
6246   /* PREFIX_VEX_0F38A7 */
6247   {
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6251   },
6252
6253   /* PREFIX_VEX_0F38A8 */
6254   {
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6258   },
6259
6260   /* PREFIX_VEX_0F38A9 */
6261   {
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6265   },
6266
6267   /* PREFIX_VEX_0F38AA */
6268   {
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6272   },
6273
6274   /* PREFIX_VEX_0F38AB */
6275   {
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6279   },
6280
6281   /* PREFIX_VEX_0F38AC */
6282   {
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6286   },
6287
6288   /* PREFIX_VEX_0F38AD */
6289   {
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6293   },
6294
6295   /* PREFIX_VEX_0F38AE */
6296   {
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6300   },
6301
6302   /* PREFIX_VEX_0F38AF */
6303   {
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6307   },
6308
6309   /* PREFIX_VEX_0F38B6 */
6310   {
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6314   },
6315
6316   /* PREFIX_VEX_0F38B7 */
6317   {
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6321   },
6322
6323   /* PREFIX_VEX_0F38B8 */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6328   },
6329
6330   /* PREFIX_VEX_0F38B9 */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6335   },
6336
6337   /* PREFIX_VEX_0F38BA */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6342   },
6343
6344   /* PREFIX_VEX_0F38BB */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6349   },
6350
6351   /* PREFIX_VEX_0F38BC */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6356   },
6357
6358   /* PREFIX_VEX_0F38BD */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6363   },
6364
6365   /* PREFIX_VEX_0F38BE */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6370   },
6371
6372   /* PREFIX_VEX_0F38BF */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6377   },
6378
6379   /* PREFIX_VEX_0F38CF */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6384   },
6385
6386   /* PREFIX_VEX_0F38DB */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6391   },
6392
6393   /* PREFIX_VEX_0F38DC */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { "vaesenc",        { XM, Vex, EXx }, 0 },
6398   },
6399
6400   /* PREFIX_VEX_0F38DD */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6405   },
6406
6407   /* PREFIX_VEX_0F38DE */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { "vaesdec",        { XM, Vex, EXx }, 0 },
6412   },
6413
6414   /* PREFIX_VEX_0F38DF */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6419   },
6420
6421   /* PREFIX_VEX_0F38F2 */
6422   {
6423     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6424   },
6425
6426   /* PREFIX_VEX_0F38F3_REG_1 */
6427   {
6428     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6429   },
6430
6431   /* PREFIX_VEX_0F38F3_REG_2 */
6432   {
6433     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6434   },
6435
6436   /* PREFIX_VEX_0F38F3_REG_3 */
6437   {
6438     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6439   },
6440
6441   /* PREFIX_VEX_0F38F5 */
6442   {
6443     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6444     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6445     { Bad_Opcode },
6446     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6447   },
6448
6449   /* PREFIX_VEX_0F38F6 */
6450   {
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6455   },
6456
6457   /* PREFIX_VEX_0F38F7 */
6458   {
6459     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6460     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6461     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6462     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6463   },
6464
6465   /* PREFIX_VEX_0F3A00 */
6466   {
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6470   },
6471
6472   /* PREFIX_VEX_0F3A01 */
6473   {
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6477   },
6478
6479   /* PREFIX_VEX_0F3A02 */
6480   {
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6484   },
6485
6486   /* PREFIX_VEX_0F3A04 */
6487   {
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6491   },
6492
6493   /* PREFIX_VEX_0F3A05 */
6494   {
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6498   },
6499
6500   /* PREFIX_VEX_0F3A06 */
6501   {
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6505   },
6506
6507   /* PREFIX_VEX_0F3A08 */
6508   {
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6512   },
6513
6514   /* PREFIX_VEX_0F3A09 */
6515   {
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6519   },
6520
6521   /* PREFIX_VEX_0F3A0A */
6522   {
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6526   },
6527
6528   /* PREFIX_VEX_0F3A0B */
6529   {
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6533   },
6534
6535   /* PREFIX_VEX_0F3A0C */
6536   {
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6540   },
6541
6542   /* PREFIX_VEX_0F3A0D */
6543   {
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6547   },
6548
6549   /* PREFIX_VEX_0F3A0E */
6550   {
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6554   },
6555
6556   /* PREFIX_VEX_0F3A0F */
6557   {
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6561   },
6562
6563   /* PREFIX_VEX_0F3A14 */
6564   {
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6568   },
6569
6570   /* PREFIX_VEX_0F3A15 */
6571   {
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6575   },
6576
6577   /* PREFIX_VEX_0F3A16 */
6578   {
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6582   },
6583
6584   /* PREFIX_VEX_0F3A17 */
6585   {
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6589   },
6590
6591   /* PREFIX_VEX_0F3A18 */
6592   {
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6596   },
6597
6598   /* PREFIX_VEX_0F3A19 */
6599   {
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6603   },
6604
6605   /* PREFIX_VEX_0F3A1D */
6606   {
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6610   },
6611
6612   /* PREFIX_VEX_0F3A20 */
6613   {
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6617   },
6618
6619   /* PREFIX_VEX_0F3A21 */
6620   {
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6624   },
6625
6626   /* PREFIX_VEX_0F3A22 */
6627   {
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6631   },
6632
6633   /* PREFIX_VEX_0F3A30 */
6634   {
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6638   },
6639
6640   /* PREFIX_VEX_0F3A31 */
6641   {
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6645   },
6646
6647   /* PREFIX_VEX_0F3A32 */
6648   {
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6652   },
6653
6654   /* PREFIX_VEX_0F3A33 */
6655   {
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6659   },
6660
6661   /* PREFIX_VEX_0F3A38 */
6662   {
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6666   },
6667
6668   /* PREFIX_VEX_0F3A39 */
6669   {
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6673   },
6674
6675   /* PREFIX_VEX_0F3A40 */
6676   {
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6680   },
6681
6682   /* PREFIX_VEX_0F3A41 */
6683   {
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6687   },
6688
6689   /* PREFIX_VEX_0F3A42 */
6690   {
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6694   },
6695
6696   /* PREFIX_VEX_0F3A44 */
6697   {
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6701   },
6702
6703   /* PREFIX_VEX_0F3A46 */
6704   {
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6708   },
6709
6710   /* PREFIX_VEX_0F3A48 */
6711   {
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6715   },
6716
6717   /* PREFIX_VEX_0F3A49 */
6718   {
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6722   },
6723
6724   /* PREFIX_VEX_0F3A4A */
6725   {
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6729   },
6730
6731   /* PREFIX_VEX_0F3A4B */
6732   {
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6736   },
6737
6738   /* PREFIX_VEX_0F3A4C */
6739   {
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6743   },
6744
6745   /* PREFIX_VEX_0F3A5C */
6746   {
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6750   },
6751
6752   /* PREFIX_VEX_0F3A5D */
6753   {
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6757   },
6758
6759   /* PREFIX_VEX_0F3A5E */
6760   {
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6764   },
6765
6766   /* PREFIX_VEX_0F3A5F */
6767   {
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6771   },
6772
6773   /* PREFIX_VEX_0F3A60 */
6774   {
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6778     { Bad_Opcode },
6779   },
6780
6781   /* PREFIX_VEX_0F3A61 */
6782   {
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6786   },
6787
6788   /* PREFIX_VEX_0F3A62 */
6789   {
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6793   },
6794
6795   /* PREFIX_VEX_0F3A63 */
6796   {
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6800   },
6801
6802   /* PREFIX_VEX_0F3A68 */
6803   {
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6807   },
6808
6809   /* PREFIX_VEX_0F3A69 */
6810   {
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6814   },
6815
6816   /* PREFIX_VEX_0F3A6A */
6817   {
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6821   },
6822
6823   /* PREFIX_VEX_0F3A6B */
6824   {
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6828   },
6829
6830   /* PREFIX_VEX_0F3A6C */
6831   {
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6835   },
6836
6837   /* PREFIX_VEX_0F3A6D */
6838   {
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6842   },
6843
6844   /* PREFIX_VEX_0F3A6E */
6845   {
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6849   },
6850
6851   /* PREFIX_VEX_0F3A6F */
6852   {
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6856   },
6857
6858   /* PREFIX_VEX_0F3A78 */
6859   {
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6863   },
6864
6865   /* PREFIX_VEX_0F3A79 */
6866   {
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6870   },
6871
6872   /* PREFIX_VEX_0F3A7A */
6873   {
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6877   },
6878
6879   /* PREFIX_VEX_0F3A7B */
6880   {
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6884   },
6885
6886   /* PREFIX_VEX_0F3A7C */
6887   {
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6891     { Bad_Opcode },
6892   },
6893
6894   /* PREFIX_VEX_0F3A7D */
6895   {
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6899   },
6900
6901   /* PREFIX_VEX_0F3A7E */
6902   {
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6906   },
6907
6908   /* PREFIX_VEX_0F3A7F */
6909   {
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6913   },
6914
6915   /* PREFIX_VEX_0F3ACE */
6916   {
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6920   },
6921
6922   /* PREFIX_VEX_0F3ACF */
6923   {
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6927   },
6928
6929   /* PREFIX_VEX_0F3ADF */
6930   {
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6934   },
6935
6936   /* PREFIX_VEX_0F3AF0 */
6937   {
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6942   },
6943
6944 #define NEED_PREFIX_TABLE
6945 #include "i386-dis-evex.h"
6946 #undef NEED_PREFIX_TABLE
6947 };
6948
6949 static const struct dis386 x86_64_table[][2] = {
6950   /* X86_64_06 */
6951   {
6952     { "pushP", { es }, 0 },
6953   },
6954
6955   /* X86_64_07 */
6956   {
6957     { "popP", { es }, 0 },
6958   },
6959
6960   /* X86_64_0D */
6961   {
6962     { "pushP", { cs }, 0 },
6963   },
6964
6965   /* X86_64_16 */
6966   {
6967     { "pushP", { ss }, 0 },
6968   },
6969
6970   /* X86_64_17 */
6971   {
6972     { "popP", { ss }, 0 },
6973   },
6974
6975   /* X86_64_1E */
6976   {
6977     { "pushP", { ds }, 0 },
6978   },
6979
6980   /* X86_64_1F */
6981   {
6982     { "popP", { ds }, 0 },
6983   },
6984
6985   /* X86_64_27 */
6986   {
6987     { "daa", { XX }, 0 },
6988   },
6989
6990   /* X86_64_2F */
6991   {
6992     { "das", { XX }, 0 },
6993   },
6994
6995   /* X86_64_37 */
6996   {
6997     { "aaa", { XX }, 0 },
6998   },
6999
7000   /* X86_64_3F */
7001   {
7002     { "aas", { XX }, 0 },
7003   },
7004
7005   /* X86_64_60 */
7006   {
7007     { "pushaP", { XX }, 0 },
7008   },
7009
7010   /* X86_64_61 */
7011   {
7012     { "popaP", { XX }, 0 },
7013   },
7014
7015   /* X86_64_62 */
7016   {
7017     { MOD_TABLE (MOD_62_32BIT) },
7018     { EVEX_TABLE (EVEX_0F) },
7019   },
7020
7021   /* X86_64_63 */
7022   {
7023     { "arpl", { Ew, Gw }, 0 },
7024     { "movs{lq|xd}", { Gv, Ed }, 0 },
7025   },
7026
7027   /* X86_64_6D */
7028   {
7029     { "ins{R|}", { Yzr, indirDX }, 0 },
7030     { "ins{G|}", { Yzr, indirDX }, 0 },
7031   },
7032
7033   /* X86_64_6F */
7034   {
7035     { "outs{R|}", { indirDXr, Xz }, 0 },
7036     { "outs{G|}", { indirDXr, Xz }, 0 },
7037   },
7038
7039   /* X86_64_82 */
7040   {
7041     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
7042     { REG_TABLE (REG_80) },
7043   },
7044
7045   /* X86_64_9A */
7046   {
7047     { "Jcall{T|}", { Ap }, 0 },
7048   },
7049
7050   /* X86_64_C4 */
7051   {
7052     { MOD_TABLE (MOD_C4_32BIT) },
7053     { VEX_C4_TABLE (VEX_0F) },
7054   },
7055
7056   /* X86_64_C5 */
7057   {
7058     { MOD_TABLE (MOD_C5_32BIT) },
7059     { VEX_C5_TABLE (VEX_0F) },
7060   },
7061
7062   /* X86_64_CE */
7063   {
7064     { "into", { XX }, 0 },
7065   },
7066
7067   /* X86_64_D4 */
7068   {
7069     { "aam", { Ib }, 0 },
7070   },
7071
7072   /* X86_64_D5 */
7073   {
7074     { "aad", { Ib }, 0 },
7075   },
7076
7077   /* X86_64_E8 */
7078   {
7079     { "callP",          { Jv, BND }, 0 },
7080     { "call@",          { Jv, BND }, 0 }
7081   },
7082
7083   /* X86_64_E9 */
7084   {
7085     { "jmpP",           { Jv, BND }, 0 },
7086     { "jmp@",           { Jv, BND }, 0 }
7087   },
7088
7089   /* X86_64_EA */
7090   {
7091     { "Jjmp{T|}", { Ap }, 0 },
7092   },
7093
7094   /* X86_64_0F01_REG_0 */
7095   {
7096     { "sgdt{Q|IQ}", { M }, 0 },
7097     { "sgdt", { M }, 0 },
7098   },
7099
7100   /* X86_64_0F01_REG_1 */
7101   {
7102     { "sidt{Q|IQ}", { M }, 0 },
7103     { "sidt", { M }, 0 },
7104   },
7105
7106   /* X86_64_0F01_REG_2 */
7107   {
7108     { "lgdt{Q|Q}", { M }, 0 },
7109     { "lgdt", { M }, 0 },
7110   },
7111
7112   /* X86_64_0F01_REG_3 */
7113   {
7114     { "lidt{Q|Q}", { M }, 0 },
7115     { "lidt", { M }, 0 },
7116   },
7117 };
7118
7119 static const struct dis386 three_byte_table[][256] = {
7120
7121   /* THREE_BYTE_0F38 */
7122   {
7123     /* 00 */
7124     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7125     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7126     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7127     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7128     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7129     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7130     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7131     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7132     /* 08 */
7133     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7134     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7135     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7136     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     /* 10 */
7142     { PREFIX_TABLE (PREFIX_0F3810) },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { PREFIX_TABLE (PREFIX_0F3814) },
7147     { PREFIX_TABLE (PREFIX_0F3815) },
7148     { Bad_Opcode },
7149     { PREFIX_TABLE (PREFIX_0F3817) },
7150     /* 18 */
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7156     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7157     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7158     { Bad_Opcode },
7159     /* 20 */
7160     { PREFIX_TABLE (PREFIX_0F3820) },
7161     { PREFIX_TABLE (PREFIX_0F3821) },
7162     { PREFIX_TABLE (PREFIX_0F3822) },
7163     { PREFIX_TABLE (PREFIX_0F3823) },
7164     { PREFIX_TABLE (PREFIX_0F3824) },
7165     { PREFIX_TABLE (PREFIX_0F3825) },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     /* 28 */
7169     { PREFIX_TABLE (PREFIX_0F3828) },
7170     { PREFIX_TABLE (PREFIX_0F3829) },
7171     { PREFIX_TABLE (PREFIX_0F382A) },
7172     { PREFIX_TABLE (PREFIX_0F382B) },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     /* 30 */
7178     { PREFIX_TABLE (PREFIX_0F3830) },
7179     { PREFIX_TABLE (PREFIX_0F3831) },
7180     { PREFIX_TABLE (PREFIX_0F3832) },
7181     { PREFIX_TABLE (PREFIX_0F3833) },
7182     { PREFIX_TABLE (PREFIX_0F3834) },
7183     { PREFIX_TABLE (PREFIX_0F3835) },
7184     { Bad_Opcode },
7185     { PREFIX_TABLE (PREFIX_0F3837) },
7186     /* 38 */
7187     { PREFIX_TABLE (PREFIX_0F3838) },
7188     { PREFIX_TABLE (PREFIX_0F3839) },
7189     { PREFIX_TABLE (PREFIX_0F383A) },
7190     { PREFIX_TABLE (PREFIX_0F383B) },
7191     { PREFIX_TABLE (PREFIX_0F383C) },
7192     { PREFIX_TABLE (PREFIX_0F383D) },
7193     { PREFIX_TABLE (PREFIX_0F383E) },
7194     { PREFIX_TABLE (PREFIX_0F383F) },
7195     /* 40 */
7196     { PREFIX_TABLE (PREFIX_0F3840) },
7197     { PREFIX_TABLE (PREFIX_0F3841) },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     /* 48 */
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     /* 50 */
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     /* 58 */
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     /* 60 */
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     /* 68 */
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     /* 70 */
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     /* 78 */
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     /* 80 */
7268     { PREFIX_TABLE (PREFIX_0F3880) },
7269     { PREFIX_TABLE (PREFIX_0F3881) },
7270     { PREFIX_TABLE (PREFIX_0F3882) },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     /* 88 */
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     /* 90 */
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     /* 98 */
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     /* a0 */
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     /* a8 */
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     /* b0 */
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     /* b8 */
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     /* c0 */
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     /* c8 */
7349     { PREFIX_TABLE (PREFIX_0F38C8) },
7350     { PREFIX_TABLE (PREFIX_0F38C9) },
7351     { PREFIX_TABLE (PREFIX_0F38CA) },
7352     { PREFIX_TABLE (PREFIX_0F38CB) },
7353     { PREFIX_TABLE (PREFIX_0F38CC) },
7354     { PREFIX_TABLE (PREFIX_0F38CD) },
7355     { Bad_Opcode },
7356     { PREFIX_TABLE (PREFIX_0F38CF) },
7357     /* d0 */
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     /* d8 */
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { PREFIX_TABLE (PREFIX_0F38DB) },
7371     { PREFIX_TABLE (PREFIX_0F38DC) },
7372     { PREFIX_TABLE (PREFIX_0F38DD) },
7373     { PREFIX_TABLE (PREFIX_0F38DE) },
7374     { PREFIX_TABLE (PREFIX_0F38DF) },
7375     /* e0 */
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     /* e8 */
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     /* f0 */
7394     { PREFIX_TABLE (PREFIX_0F38F0) },
7395     { PREFIX_TABLE (PREFIX_0F38F1) },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { PREFIX_TABLE (PREFIX_0F38F5) },
7400     { PREFIX_TABLE (PREFIX_0F38F6) },
7401     { Bad_Opcode },
7402     /* f8 */
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411   },
7412   /* THREE_BYTE_0F3A */
7413   {
7414     /* 00 */
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     /* 08 */
7424     { PREFIX_TABLE (PREFIX_0F3A08) },
7425     { PREFIX_TABLE (PREFIX_0F3A09) },
7426     { PREFIX_TABLE (PREFIX_0F3A0A) },
7427     { PREFIX_TABLE (PREFIX_0F3A0B) },
7428     { PREFIX_TABLE (PREFIX_0F3A0C) },
7429     { PREFIX_TABLE (PREFIX_0F3A0D) },
7430     { PREFIX_TABLE (PREFIX_0F3A0E) },
7431     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7432     /* 10 */
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { PREFIX_TABLE (PREFIX_0F3A14) },
7438     { PREFIX_TABLE (PREFIX_0F3A15) },
7439     { PREFIX_TABLE (PREFIX_0F3A16) },
7440     { PREFIX_TABLE (PREFIX_0F3A17) },
7441     /* 18 */
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     /* 20 */
7451     { PREFIX_TABLE (PREFIX_0F3A20) },
7452     { PREFIX_TABLE (PREFIX_0F3A21) },
7453     { PREFIX_TABLE (PREFIX_0F3A22) },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     /* 28 */
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     /* 30 */
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     /* 38 */
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     /* 40 */
7487     { PREFIX_TABLE (PREFIX_0F3A40) },
7488     { PREFIX_TABLE (PREFIX_0F3A41) },
7489     { PREFIX_TABLE (PREFIX_0F3A42) },
7490     { Bad_Opcode },
7491     { PREFIX_TABLE (PREFIX_0F3A44) },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     /* 48 */
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     /* 50 */
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     /* 58 */
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     /* 60 */
7523     { PREFIX_TABLE (PREFIX_0F3A60) },
7524     { PREFIX_TABLE (PREFIX_0F3A61) },
7525     { PREFIX_TABLE (PREFIX_0F3A62) },
7526     { PREFIX_TABLE (PREFIX_0F3A63) },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     /* 68 */
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     /* 70 */
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     /* 78 */
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     /* 80 */
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     /* 88 */
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     /* 90 */
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     /* 98 */
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     /* a0 */
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     /* a8 */
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     /* b0 */
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     /* b8 */
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     /* c0 */
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     /* c8 */
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { PREFIX_TABLE (PREFIX_0F3ACC) },
7645     { Bad_Opcode },
7646     { PREFIX_TABLE (PREFIX_0F3ACE) },
7647     { PREFIX_TABLE (PREFIX_0F3ACF) },
7648     /* d0 */
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     /* d8 */
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { PREFIX_TABLE (PREFIX_0F3ADF) },
7666     /* e0 */
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     /* e8 */
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     /* f0 */
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     /* f8 */
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702   },
7703 };
7704
7705 static const struct dis386 xop_table[][256] = {
7706   /* XOP_08 */
7707   {
7708     /* 00 */
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     /* 08 */
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     /* 10 */
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     /* 18 */
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     /* 20 */
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     /* 28 */
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     /* 30 */
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     /* 38 */
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     /* 40 */
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     /* 48 */
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     /* 50 */
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     /* 58 */
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     /* 60 */
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     /* 68 */
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     /* 70 */
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     /* 78 */
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     /* 80 */
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7859     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7860     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7861     /* 88 */
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7869     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7870     /* 90 */
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7877     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7878     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7879     /* 98 */
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7887     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7888     /* a0 */
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7892     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7896     { Bad_Opcode },
7897     /* a8 */
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     /* b0 */
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7914     { Bad_Opcode },
7915     /* b8 */
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     /* c0 */
7925     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7926     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7927     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7928     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     /* c8 */
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7939     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7940     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7941     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7942     /* d0 */
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     /* d8 */
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     /* e0 */
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     /* e8 */
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7975     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7976     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7977     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7978     /* f0 */
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     /* f8 */
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996   },
7997   /* XOP_09 */
7998   {
7999     /* 00 */
8000     { Bad_Opcode },
8001     { REG_TABLE (REG_XOP_TBM_01) },
8002     { REG_TABLE (REG_XOP_TBM_02) },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     /* 08 */
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     /* 10 */
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { REG_TABLE (REG_XOP_LWPCB) },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     /* 18 */
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     /* 20 */
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     /* 28 */
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     /* 30 */
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     /* 38 */
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     /* 40 */
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     /* 48 */
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     /* 50 */
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     /* 58 */
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     /* 60 */
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     /* 68 */
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     /* 70 */
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     /* 78 */
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     /* 80 */
8144     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8145     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8146     { "vfrczss",        { XM, EXd }, 0 },
8147     { "vfrczsd",        { XM, EXq }, 0 },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     /* 88 */
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     /* 90 */
8162     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8163     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8164     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8165     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8166     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8167     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8168     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8169     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8170     /* 98 */
8171     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8172     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8173     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8174     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     /* a0 */
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     /* a8 */
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     /* b0 */
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     /* b8 */
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     /* c0 */
8216     { Bad_Opcode },
8217     { "vphaddbw",       { XM, EXxmm }, 0 },
8218     { "vphaddbd",       { XM, EXxmm }, 0 },
8219     { "vphaddbq",       { XM, EXxmm }, 0 },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { "vphaddwd",       { XM, EXxmm }, 0 },
8223     { "vphaddwq",       { XM, EXxmm }, 0 },
8224     /* c8 */
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { "vphadddq",       { XM, EXxmm }, 0 },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     /* d0 */
8234     { Bad_Opcode },
8235     { "vphaddubw",      { XM, EXxmm }, 0 },
8236     { "vphaddubd",      { XM, EXxmm }, 0 },
8237     { "vphaddubq",      { XM, EXxmm }, 0 },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { "vphadduwd",      { XM, EXxmm }, 0 },
8241     { "vphadduwq",      { XM, EXxmm }, 0 },
8242     /* d8 */
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { "vphaddudq",      { XM, EXxmm }, 0 },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     /* e0 */
8252     { Bad_Opcode },
8253     { "vphsubbw",       { XM, EXxmm }, 0 },
8254     { "vphsubwd",       { XM, EXxmm }, 0 },
8255     { "vphsubdq",       { XM, EXxmm }, 0 },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     /* e8 */
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     /* f0 */
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     /* f8 */
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287   },
8288   /* XOP_0A */
8289   {
8290     /* 00 */
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     /* 08 */
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     /* 10 */
8309     { "bextr",  { Gv, Ev, Iq }, 0 },
8310     { Bad_Opcode },
8311     { REG_TABLE (REG_XOP_LWP) },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     /* 18 */
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     /* 20 */
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     /* 28 */
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     /* 30 */
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     /* 38 */
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     /* 40 */
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     /* 48 */
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     /* 50 */
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     /* 58 */
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     /* 60 */
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     /* 68 */
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     /* 70 */
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     /* 78 */
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     /* 80 */
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     /* 88 */
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     /* 90 */
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     /* 98 */
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     /* a0 */
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     /* a8 */
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     /* b0 */
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     /* b8 */
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     /* c0 */
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     /* c8 */
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     /* d0 */
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     /* d8 */
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     /* e0 */
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     /* e8 */
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     /* f0 */
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     /* f8 */
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578   },
8579 };
8580
8581 static const struct dis386 vex_table[][256] = {
8582   /* VEX_0F */
8583   {
8584     /* 00 */
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     /* 08 */
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     /* 10 */
8603     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8604     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8605     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8606     { MOD_TABLE (MOD_VEX_0F13) },
8607     { VEX_W_TABLE (VEX_W_0F14) },
8608     { VEX_W_TABLE (VEX_W_0F15) },
8609     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8610     { MOD_TABLE (MOD_VEX_0F17) },
8611     /* 18 */
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     /* 20 */
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     /* 28 */
8630     { VEX_W_TABLE (VEX_W_0F28) },
8631     { VEX_W_TABLE (VEX_W_0F29) },
8632     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8633     { MOD_TABLE (MOD_VEX_0F2B) },
8634     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8635     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8636     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8637     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8638     /* 30 */
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     /* 38 */
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     /* 40 */
8657     { Bad_Opcode },
8658     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8659     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8660     { Bad_Opcode },
8661     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8662     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8663     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8664     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8665     /* 48 */
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8669     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     /* 50 */
8675     { MOD_TABLE (MOD_VEX_0F50) },
8676     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8677     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8678     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8679     { "vandpX",         { XM, Vex, EXx }, 0 },
8680     { "vandnpX",        { XM, Vex, EXx }, 0 },
8681     { "vorpX",          { XM, Vex, EXx }, 0 },
8682     { "vxorpX",         { XM, Vex, EXx }, 0 },
8683     /* 58 */
8684     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8685     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8686     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8687     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8688     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8689     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8690     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8691     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8692     /* 60 */
8693     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8694     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8695     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8696     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8701     /* 68 */
8702     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8710     /* 70 */
8711     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8712     { REG_TABLE (REG_VEX_0F71) },
8713     { REG_TABLE (REG_VEX_0F72) },
8714     { REG_TABLE (REG_VEX_0F73) },
8715     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8716     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8717     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8718     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8719     /* 78 */
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8728     /* 80 */
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     /* 88 */
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     /* 90 */
8747     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     /* 98 */
8756     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     /* a0 */
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     { Bad_Opcode },
8773     /* a8 */
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { REG_TABLE (REG_VEX_0FAE) },
8781     { Bad_Opcode },
8782     /* b0 */
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     /* b8 */
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     /* c0 */
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8804     { Bad_Opcode },
8805     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8806     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8807     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8808     { Bad_Opcode },
8809     /* c8 */
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     /* d0 */
8819     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8820     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8821     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8822     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8823     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8824     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8825     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8826     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8827     /* d8 */
8828     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8829     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8830     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8831     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8832     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8833     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8834     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8835     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8836     /* e0 */
8837     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8838     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8839     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8840     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8841     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8842     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8843     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8844     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8845     /* e8 */
8846     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8847     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8848     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8849     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8850     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8851     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8852     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8853     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8854     /* f0 */
8855     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8856     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8857     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8858     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8859     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8860     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8861     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8862     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8863     /* f8 */
8864     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8865     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8866     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8867     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8868     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8869     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8870     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8871     { Bad_Opcode },
8872   },
8873   /* VEX_0F38 */
8874   {
8875     /* 00 */
8876     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8877     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8878     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8879     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8880     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8881     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8882     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8883     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8884     /* 08 */
8885     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8893     /* 10 */
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8902     /* 18 */
8903     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8906     { Bad_Opcode },
8907     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8909     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8910     { Bad_Opcode },
8911     /* 20 */
8912     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     /* 28 */
8921     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8925     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8929     /* 30 */
8930     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8938     /* 38 */
8939     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8947     /* 40 */
8948     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8956     /* 48 */
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     /* 50 */
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     /* 58 */
8975     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8976     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     /* 60 */
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     /* 68 */
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     /* 70 */
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     /* 78 */
9011     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     /* 80 */
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     /* 88 */
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9034     { Bad_Opcode },
9035     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9036     { Bad_Opcode },
9037     /* 90 */
9038     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9045     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9046     /* 98 */
9047     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9051     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9054     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9055     /* a0 */
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9063     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9064     /* a8 */
9065     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9068     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9069     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9073     /* b0 */
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9081     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9082     /* b8 */
9083     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9084     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9085     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9086     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9087     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9091     /* c0 */
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     /* c8 */
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9109     /* d0 */
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     /* d8 */
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9127     /* e0 */
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     /* e8 */
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     /* f0 */
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9149     { REG_TABLE (REG_VEX_0F38F3) },
9150     { Bad_Opcode },
9151     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9152     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9153     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9154     /* f8 */
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163   },
9164   /* VEX_0F3A */
9165   {
9166     /* 00 */
9167     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9168     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9169     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9170     { Bad_Opcode },
9171     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9172     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9173     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9174     { Bad_Opcode },
9175     /* 08 */
9176     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9177     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9178     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9179     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9180     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9181     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9182     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9183     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9184     /* 10 */
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9190     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9191     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9192     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9193     /* 18 */
9194     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9195     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     /* 20 */
9203     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9204     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9205     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     /* 28 */
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     /* 30 */
9221     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9222     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9223     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9224     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     /* 38 */
9230     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9231     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     /* 40 */
9239     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9240     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9241     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9242     { Bad_Opcode },
9243     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9244     { Bad_Opcode },
9245     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9246     { Bad_Opcode },
9247     /* 48 */
9248     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9249     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9250     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9251     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9252     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     /* 50 */
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     /* 58 */
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9271     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9272     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9273     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9274     /* 60 */
9275     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9276     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9277     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9278     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     /* 68 */
9284     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9285     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9286     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9287     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9288     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9289     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9290     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9291     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9292     /* 70 */
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     /* 78 */
9302     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9303     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9304     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9305     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9306     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9307     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9308     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9309     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9310     /* 80 */
9311     { Bad_Opcode },
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315     { Bad_Opcode },
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     /* 88 */
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     /* 90 */
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     /* 98 */
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     /* a0 */
9347     { Bad_Opcode },
9348     { Bad_Opcode },
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     /* a8 */
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     /* b0 */
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     { Bad_Opcode },
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     { Bad_Opcode },
9373     /* b8 */
9374     { Bad_Opcode },
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     /* c0 */
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     /* c8 */
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9399     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9400     /* d0 */
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     { Bad_Opcode },
9409     /* d8 */
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9418     /* e0 */
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     { Bad_Opcode },
9427     /* e8 */
9428     { Bad_Opcode },
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     /* f0 */
9437     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     { Bad_Opcode },
9445     /* f8 */
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     { Bad_Opcode },
9454   },
9455 };
9456
9457 #define NEED_OPCODE_TABLE
9458 #include "i386-dis-evex.h"
9459 #undef NEED_OPCODE_TABLE
9460 static const struct dis386 vex_len_table[][2] = {
9461   /* VEX_LEN_0F10_P_1 */
9462   {
9463     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9464     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9465   },
9466
9467   /* VEX_LEN_0F10_P_3 */
9468   {
9469     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9470     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9471   },
9472
9473   /* VEX_LEN_0F11_P_1 */
9474   {
9475     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9476     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9477   },
9478
9479   /* VEX_LEN_0F11_P_3 */
9480   {
9481     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9482     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9483   },
9484
9485   /* VEX_LEN_0F12_P_0_M_0 */
9486   {
9487     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9488   },
9489
9490   /* VEX_LEN_0F12_P_0_M_1 */
9491   {
9492     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9493   },
9494
9495   /* VEX_LEN_0F12_P_2 */
9496   {
9497     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9498   },
9499
9500   /* VEX_LEN_0F13_M_0 */
9501   {
9502     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9503   },
9504
9505   /* VEX_LEN_0F16_P_0_M_0 */
9506   {
9507     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9508   },
9509
9510   /* VEX_LEN_0F16_P_0_M_1 */
9511   {
9512     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9513   },
9514
9515   /* VEX_LEN_0F16_P_2 */
9516   {
9517     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9518   },
9519
9520   /* VEX_LEN_0F17_M_0 */
9521   {
9522     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9523   },
9524
9525   /* VEX_LEN_0F2A_P_1 */
9526   {
9527     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9528     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9529   },
9530
9531   /* VEX_LEN_0F2A_P_3 */
9532   {
9533     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9534     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9535   },
9536
9537   /* VEX_LEN_0F2C_P_1 */
9538   {
9539     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9540     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9541   },
9542
9543   /* VEX_LEN_0F2C_P_3 */
9544   {
9545     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9546     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9547   },
9548
9549   /* VEX_LEN_0F2D_P_1 */
9550   {
9551     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9552     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9553   },
9554
9555   /* VEX_LEN_0F2D_P_3 */
9556   {
9557     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9558     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9559   },
9560
9561   /* VEX_LEN_0F2E_P_0 */
9562   {
9563     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9564     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9565   },
9566
9567   /* VEX_LEN_0F2E_P_2 */
9568   {
9569     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9570     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9571   },
9572
9573   /* VEX_LEN_0F2F_P_0 */
9574   {
9575     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9576     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9577   },
9578
9579   /* VEX_LEN_0F2F_P_2 */
9580   {
9581     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9582     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9583   },
9584
9585   /* VEX_LEN_0F41_P_0 */
9586   {
9587     { Bad_Opcode },
9588     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9589   },
9590   /* VEX_LEN_0F41_P_2 */
9591   {
9592     { Bad_Opcode },
9593     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9594   },
9595   /* VEX_LEN_0F42_P_0 */
9596   {
9597     { Bad_Opcode },
9598     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9599   },
9600   /* VEX_LEN_0F42_P_2 */
9601   {
9602     { Bad_Opcode },
9603     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9604   },
9605   /* VEX_LEN_0F44_P_0 */
9606   {
9607     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9608   },
9609   /* VEX_LEN_0F44_P_2 */
9610   {
9611     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9612   },
9613   /* VEX_LEN_0F45_P_0 */
9614   {
9615     { Bad_Opcode },
9616     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9617   },
9618   /* VEX_LEN_0F45_P_2 */
9619   {
9620     { Bad_Opcode },
9621     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9622   },
9623   /* VEX_LEN_0F46_P_0 */
9624   {
9625     { Bad_Opcode },
9626     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9627   },
9628   /* VEX_LEN_0F46_P_2 */
9629   {
9630     { Bad_Opcode },
9631     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9632   },
9633   /* VEX_LEN_0F47_P_0 */
9634   {
9635     { Bad_Opcode },
9636     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9637   },
9638   /* VEX_LEN_0F47_P_2 */
9639   {
9640     { Bad_Opcode },
9641     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9642   },
9643   /* VEX_LEN_0F4A_P_0 */
9644   {
9645     { Bad_Opcode },
9646     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9647   },
9648   /* VEX_LEN_0F4A_P_2 */
9649   {
9650     { Bad_Opcode },
9651     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9652   },
9653   /* VEX_LEN_0F4B_P_0 */
9654   {
9655     { Bad_Opcode },
9656     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9657   },
9658   /* VEX_LEN_0F4B_P_2 */
9659   {
9660     { Bad_Opcode },
9661     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9662   },
9663
9664   /* VEX_LEN_0F51_P_1 */
9665   {
9666     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9667     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9668   },
9669
9670   /* VEX_LEN_0F51_P_3 */
9671   {
9672     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9673     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9674   },
9675
9676   /* VEX_LEN_0F52_P_1 */
9677   {
9678     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9679     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9680   },
9681
9682   /* VEX_LEN_0F53_P_1 */
9683   {
9684     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9685     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9686   },
9687
9688   /* VEX_LEN_0F58_P_1 */
9689   {
9690     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9691     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9692   },
9693
9694   /* VEX_LEN_0F58_P_3 */
9695   {
9696     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9697     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9698   },
9699
9700   /* VEX_LEN_0F59_P_1 */
9701   {
9702     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9703     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9704   },
9705
9706   /* VEX_LEN_0F59_P_3 */
9707   {
9708     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9709     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9710   },
9711
9712   /* VEX_LEN_0F5A_P_1 */
9713   {
9714     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9715     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9716   },
9717
9718   /* VEX_LEN_0F5A_P_3 */
9719   {
9720     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9721     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9722   },
9723
9724   /* VEX_LEN_0F5C_P_1 */
9725   {
9726     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9727     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9728   },
9729
9730   /* VEX_LEN_0F5C_P_3 */
9731   {
9732     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9733     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9734   },
9735
9736   /* VEX_LEN_0F5D_P_1 */
9737   {
9738     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9739     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9740   },
9741
9742   /* VEX_LEN_0F5D_P_3 */
9743   {
9744     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9745     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9746   },
9747
9748   /* VEX_LEN_0F5E_P_1 */
9749   {
9750     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9751     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9752   },
9753
9754   /* VEX_LEN_0F5E_P_3 */
9755   {
9756     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9757     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9758   },
9759
9760   /* VEX_LEN_0F5F_P_1 */
9761   {
9762     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9763     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9764   },
9765
9766   /* VEX_LEN_0F5F_P_3 */
9767   {
9768     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9769     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9770   },
9771
9772   /* VEX_LEN_0F6E_P_2 */
9773   {
9774     { "vmovK",          { XMScalar, Edq }, 0 },
9775     { "vmovK",          { XMScalar, Edq }, 0 },
9776   },
9777
9778   /* VEX_LEN_0F7E_P_1 */
9779   {
9780     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9781     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9782   },
9783
9784   /* VEX_LEN_0F7E_P_2 */
9785   {
9786     { "vmovK",          { Edq, XMScalar }, 0 },
9787     { "vmovK",          { Edq, XMScalar }, 0 },
9788   },
9789
9790   /* VEX_LEN_0F90_P_0 */
9791   {
9792     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9793   },
9794
9795   /* VEX_LEN_0F90_P_2 */
9796   {
9797     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9798   },
9799
9800   /* VEX_LEN_0F91_P_0 */
9801   {
9802     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9803   },
9804
9805   /* VEX_LEN_0F91_P_2 */
9806   {
9807     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9808   },
9809
9810   /* VEX_LEN_0F92_P_0 */
9811   {
9812     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9813   },
9814
9815   /* VEX_LEN_0F92_P_2 */
9816   {
9817     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9818   },
9819
9820   /* VEX_LEN_0F92_P_3 */
9821   {
9822     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9823   },
9824
9825   /* VEX_LEN_0F93_P_0 */
9826   {
9827     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9828   },
9829
9830   /* VEX_LEN_0F93_P_2 */
9831   {
9832     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9833   },
9834
9835   /* VEX_LEN_0F93_P_3 */
9836   {
9837     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9838   },
9839
9840   /* VEX_LEN_0F98_P_0 */
9841   {
9842     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9843   },
9844
9845   /* VEX_LEN_0F98_P_2 */
9846   {
9847     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9848   },
9849
9850   /* VEX_LEN_0F99_P_0 */
9851   {
9852     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9853   },
9854
9855   /* VEX_LEN_0F99_P_2 */
9856   {
9857     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9858   },
9859
9860   /* VEX_LEN_0FAE_R_2_M_0 */
9861   {
9862     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9863   },
9864
9865   /* VEX_LEN_0FAE_R_3_M_0 */
9866   {
9867     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9868   },
9869
9870   /* VEX_LEN_0FC2_P_1 */
9871   {
9872     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9873     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9874   },
9875
9876   /* VEX_LEN_0FC2_P_3 */
9877   {
9878     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9879     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9880   },
9881
9882   /* VEX_LEN_0FC4_P_2 */
9883   {
9884     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9885   },
9886
9887   /* VEX_LEN_0FC5_P_2 */
9888   {
9889     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9890   },
9891
9892   /* VEX_LEN_0FD6_P_2 */
9893   {
9894     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9895     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9896   },
9897
9898   /* VEX_LEN_0FF7_P_2 */
9899   {
9900     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9901   },
9902
9903   /* VEX_LEN_0F3816_P_2 */
9904   {
9905     { Bad_Opcode },
9906     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9907   },
9908
9909   /* VEX_LEN_0F3819_P_2 */
9910   {
9911     { Bad_Opcode },
9912     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9913   },
9914
9915   /* VEX_LEN_0F381A_P_2_M_0 */
9916   {
9917     { Bad_Opcode },
9918     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9919   },
9920
9921   /* VEX_LEN_0F3836_P_2 */
9922   {
9923     { Bad_Opcode },
9924     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9925   },
9926
9927   /* VEX_LEN_0F3841_P_2 */
9928   {
9929     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9930   },
9931
9932   /* VEX_LEN_0F385A_P_2_M_0 */
9933   {
9934     { Bad_Opcode },
9935     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9936   },
9937
9938   /* VEX_LEN_0F38DB_P_2 */
9939   {
9940     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9941   },
9942
9943   /* VEX_LEN_0F38F2_P_0 */
9944   {
9945     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9946   },
9947
9948   /* VEX_LEN_0F38F3_R_1_P_0 */
9949   {
9950     { "blsrS",          { VexGdq, Edq }, 0 },
9951   },
9952
9953   /* VEX_LEN_0F38F3_R_2_P_0 */
9954   {
9955     { "blsmskS",        { VexGdq, Edq }, 0 },
9956   },
9957
9958   /* VEX_LEN_0F38F3_R_3_P_0 */
9959   {
9960     { "blsiS",          { VexGdq, Edq }, 0 },
9961   },
9962
9963   /* VEX_LEN_0F38F5_P_0 */
9964   {
9965     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9966   },
9967
9968   /* VEX_LEN_0F38F5_P_1 */
9969   {
9970     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9971   },
9972
9973   /* VEX_LEN_0F38F5_P_3 */
9974   {
9975     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9976   },
9977
9978   /* VEX_LEN_0F38F6_P_3 */
9979   {
9980     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9981   },
9982
9983   /* VEX_LEN_0F38F7_P_0 */
9984   {
9985     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9986   },
9987
9988   /* VEX_LEN_0F38F7_P_1 */
9989   {
9990     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9991   },
9992
9993   /* VEX_LEN_0F38F7_P_2 */
9994   {
9995     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9996   },
9997
9998   /* VEX_LEN_0F38F7_P_3 */
9999   {
10000     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10001   },
10002
10003   /* VEX_LEN_0F3A00_P_2 */
10004   {
10005     { Bad_Opcode },
10006     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10007   },
10008
10009   /* VEX_LEN_0F3A01_P_2 */
10010   {
10011     { Bad_Opcode },
10012     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10013   },
10014
10015   /* VEX_LEN_0F3A06_P_2 */
10016   {
10017     { Bad_Opcode },
10018     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10019   },
10020
10021   /* VEX_LEN_0F3A0A_P_2 */
10022   {
10023     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10024     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10025   },
10026
10027   /* VEX_LEN_0F3A0B_P_2 */
10028   {
10029     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10030     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10031   },
10032
10033   /* VEX_LEN_0F3A14_P_2 */
10034   {
10035     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10036   },
10037
10038   /* VEX_LEN_0F3A15_P_2 */
10039   {
10040     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10041   },
10042
10043   /* VEX_LEN_0F3A16_P_2  */
10044   {
10045     { "vpextrK",        { Edq, XM, Ib }, 0 },
10046   },
10047
10048   /* VEX_LEN_0F3A17_P_2 */
10049   {
10050     { "vextractps",     { Edqd, XM, Ib }, 0 },
10051   },
10052
10053   /* VEX_LEN_0F3A18_P_2 */
10054   {
10055     { Bad_Opcode },
10056     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10057   },
10058
10059   /* VEX_LEN_0F3A19_P_2 */
10060   {
10061     { Bad_Opcode },
10062     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10063   },
10064
10065   /* VEX_LEN_0F3A20_P_2 */
10066   {
10067     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10068   },
10069
10070   /* VEX_LEN_0F3A21_P_2 */
10071   {
10072     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10073   },
10074
10075   /* VEX_LEN_0F3A22_P_2 */
10076   {
10077     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10078   },
10079
10080   /* VEX_LEN_0F3A30_P_2 */
10081   {
10082     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10083   },
10084
10085   /* VEX_LEN_0F3A31_P_2 */
10086   {
10087     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10088   },
10089
10090   /* VEX_LEN_0F3A32_P_2 */
10091   {
10092     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10093   },
10094
10095   /* VEX_LEN_0F3A33_P_2 */
10096   {
10097     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10098   },
10099
10100   /* VEX_LEN_0F3A38_P_2 */
10101   {
10102     { Bad_Opcode },
10103     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10104   },
10105
10106   /* VEX_LEN_0F3A39_P_2 */
10107   {
10108     { Bad_Opcode },
10109     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10110   },
10111
10112   /* VEX_LEN_0F3A41_P_2 */
10113   {
10114     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10115   },
10116
10117   /* VEX_LEN_0F3A46_P_2 */
10118   {
10119     { Bad_Opcode },
10120     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10121   },
10122
10123   /* VEX_LEN_0F3A60_P_2 */
10124   {
10125     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10126   },
10127
10128   /* VEX_LEN_0F3A61_P_2 */
10129   {
10130     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10131   },
10132
10133   /* VEX_LEN_0F3A62_P_2 */
10134   {
10135     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10136   },
10137
10138   /* VEX_LEN_0F3A63_P_2 */
10139   {
10140     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10141   },
10142
10143   /* VEX_LEN_0F3A6A_P_2 */
10144   {
10145     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10146   },
10147
10148   /* VEX_LEN_0F3A6B_P_2 */
10149   {
10150     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10151   },
10152
10153   /* VEX_LEN_0F3A6E_P_2 */
10154   {
10155     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10156   },
10157
10158   /* VEX_LEN_0F3A6F_P_2 */
10159   {
10160     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10161   },
10162
10163   /* VEX_LEN_0F3A7A_P_2 */
10164   {
10165     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10166   },
10167
10168   /* VEX_LEN_0F3A7B_P_2 */
10169   {
10170     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10171   },
10172
10173   /* VEX_LEN_0F3A7E_P_2 */
10174   {
10175     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10176   },
10177
10178   /* VEX_LEN_0F3A7F_P_2 */
10179   {
10180     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10181   },
10182
10183   /* VEX_LEN_0F3ADF_P_2 */
10184   {
10185     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10186   },
10187
10188   /* VEX_LEN_0F3AF0_P_3 */
10189   {
10190     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10191   },
10192
10193   /* VEX_LEN_0FXOP_08_CC */
10194   {
10195      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10196   },
10197
10198   /* VEX_LEN_0FXOP_08_CD */
10199   {
10200      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10201   },
10202
10203   /* VEX_LEN_0FXOP_08_CE */
10204   {
10205      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10206   },
10207
10208   /* VEX_LEN_0FXOP_08_CF */
10209   {
10210      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10211   },
10212
10213   /* VEX_LEN_0FXOP_08_EC */
10214   {
10215      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10216   },
10217
10218   /* VEX_LEN_0FXOP_08_ED */
10219   {
10220      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10221   },
10222
10223   /* VEX_LEN_0FXOP_08_EE */
10224   {
10225      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10226   },
10227
10228   /* VEX_LEN_0FXOP_08_EF */
10229   {
10230      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10231   },
10232
10233   /* VEX_LEN_0FXOP_09_80 */
10234   {
10235     { "vfrczps",        { XM, EXxmm }, 0 },
10236     { "vfrczps",        { XM, EXymmq }, 0 },
10237   },
10238
10239   /* VEX_LEN_0FXOP_09_81 */
10240   {
10241     { "vfrczpd",        { XM, EXxmm }, 0 },
10242     { "vfrczpd",        { XM, EXymmq }, 0 },
10243   },
10244 };
10245
10246 static const struct dis386 vex_w_table[][2] = {
10247   {
10248     /* VEX_W_0F10_P_0 */
10249     { "vmovups",        { XM, EXx }, 0 },
10250   },
10251   {
10252     /* VEX_W_0F10_P_1 */
10253     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10254   },
10255   {
10256     /* VEX_W_0F10_P_2 */
10257     { "vmovupd",        { XM, EXx }, 0 },
10258   },
10259   {
10260     /* VEX_W_0F10_P_3 */
10261     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10262   },
10263   {
10264     /* VEX_W_0F11_P_0 */
10265     { "vmovups",        { EXxS, XM }, 0 },
10266   },
10267   {
10268     /* VEX_W_0F11_P_1 */
10269     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10270   },
10271   {
10272     /* VEX_W_0F11_P_2 */
10273     { "vmovupd",        { EXxS, XM }, 0 },
10274   },
10275   {
10276     /* VEX_W_0F11_P_3 */
10277     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10278   },
10279   {
10280     /* VEX_W_0F12_P_0_M_0 */
10281     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10282   },
10283   {
10284     /* VEX_W_0F12_P_0_M_1 */
10285     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10286   },
10287   {
10288     /* VEX_W_0F12_P_1 */
10289     { "vmovsldup",      { XM, EXx }, 0 },
10290   },
10291   {
10292     /* VEX_W_0F12_P_2 */
10293     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10294   },
10295   {
10296     /* VEX_W_0F12_P_3 */
10297     { "vmovddup",       { XM, EXymmq }, 0 },
10298   },
10299   {
10300     /* VEX_W_0F13_M_0 */
10301     { "vmovlpX",        { EXq, XM }, 0 },
10302   },
10303   {
10304     /* VEX_W_0F14 */
10305     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10306   },
10307   {
10308     /* VEX_W_0F15 */
10309     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10310   },
10311   {
10312     /* VEX_W_0F16_P_0_M_0 */
10313     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10314   },
10315   {
10316     /* VEX_W_0F16_P_0_M_1 */
10317     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10318   },
10319   {
10320     /* VEX_W_0F16_P_1 */
10321     { "vmovshdup",      { XM, EXx }, 0 },
10322   },
10323   {
10324     /* VEX_W_0F16_P_2 */
10325     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10326   },
10327   {
10328     /* VEX_W_0F17_M_0 */
10329     { "vmovhpX",        { EXq, XM }, 0 },
10330   },
10331   {
10332     /* VEX_W_0F28 */
10333     { "vmovapX",        { XM, EXx }, 0 },
10334   },
10335   {
10336     /* VEX_W_0F29 */
10337     { "vmovapX",        { EXxS, XM }, 0 },
10338   },
10339   {
10340     /* VEX_W_0F2B_M_0 */
10341     { "vmovntpX",       { Mx, XM }, 0 },
10342   },
10343   {
10344     /* VEX_W_0F2E_P_0 */
10345     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10346   },
10347   {
10348     /* VEX_W_0F2E_P_2 */
10349     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10350   },
10351   {
10352     /* VEX_W_0F2F_P_0 */
10353     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10354   },
10355   {
10356     /* VEX_W_0F2F_P_2 */
10357     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10358   },
10359   {
10360     /* VEX_W_0F41_P_0_LEN_1 */
10361     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10362     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10363   },
10364   {
10365     /* VEX_W_0F41_P_2_LEN_1 */
10366     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10367     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10368   },
10369   {
10370     /* VEX_W_0F42_P_0_LEN_1 */
10371     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10372     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10373   },
10374   {
10375     /* VEX_W_0F42_P_2_LEN_1 */
10376     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10377     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10378   },
10379   {
10380     /* VEX_W_0F44_P_0_LEN_0 */
10381     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10382     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10383   },
10384   {
10385     /* VEX_W_0F44_P_2_LEN_0 */
10386     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10387     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10388   },
10389   {
10390     /* VEX_W_0F45_P_0_LEN_1 */
10391     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10392     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10393   },
10394   {
10395     /* VEX_W_0F45_P_2_LEN_1 */
10396     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10397     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10398   },
10399   {
10400     /* VEX_W_0F46_P_0_LEN_1 */
10401     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10402     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10403   },
10404   {
10405     /* VEX_W_0F46_P_2_LEN_1 */
10406     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10407     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10408   },
10409   {
10410     /* VEX_W_0F47_P_0_LEN_1 */
10411     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10412     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10413   },
10414   {
10415     /* VEX_W_0F47_P_2_LEN_1 */
10416     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10417     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10418   },
10419   {
10420     /* VEX_W_0F4A_P_0_LEN_1 */
10421     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10422     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10423   },
10424   {
10425     /* VEX_W_0F4A_P_2_LEN_1 */
10426     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10427     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10428   },
10429   {
10430     /* VEX_W_0F4B_P_0_LEN_1 */
10431     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10432     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10433   },
10434   {
10435     /* VEX_W_0F4B_P_2_LEN_1 */
10436     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10437   },
10438   {
10439     /* VEX_W_0F50_M_0 */
10440     { "vmovmskpX",      { Gdq, XS }, 0 },
10441   },
10442   {
10443     /* VEX_W_0F51_P_0 */
10444     { "vsqrtps",        { XM, EXx }, 0 },
10445   },
10446   {
10447     /* VEX_W_0F51_P_1 */
10448     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10449   },
10450   {
10451     /* VEX_W_0F51_P_2  */
10452     { "vsqrtpd",        { XM, EXx }, 0 },
10453   },
10454   {
10455     /* VEX_W_0F51_P_3 */
10456     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10457   },
10458   {
10459     /* VEX_W_0F52_P_0 */
10460     { "vrsqrtps",       { XM, EXx }, 0 },
10461   },
10462   {
10463     /* VEX_W_0F52_P_1 */
10464     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10465   },
10466   {
10467     /* VEX_W_0F53_P_0  */
10468     { "vrcpps",         { XM, EXx }, 0 },
10469   },
10470   {
10471     /* VEX_W_0F53_P_1  */
10472     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10473   },
10474   {
10475     /* VEX_W_0F58_P_0  */
10476     { "vaddps",         { XM, Vex, EXx }, 0 },
10477   },
10478   {
10479     /* VEX_W_0F58_P_1  */
10480     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10481   },
10482   {
10483     /* VEX_W_0F58_P_2  */
10484     { "vaddpd",         { XM, Vex, EXx }, 0 },
10485   },
10486   {
10487     /* VEX_W_0F58_P_3  */
10488     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10489   },
10490   {
10491     /* VEX_W_0F59_P_0  */
10492     { "vmulps",         { XM, Vex, EXx }, 0 },
10493   },
10494   {
10495     /* VEX_W_0F59_P_1  */
10496     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10497   },
10498   {
10499     /* VEX_W_0F59_P_2  */
10500     { "vmulpd",         { XM, Vex, EXx }, 0 },
10501   },
10502   {
10503     /* VEX_W_0F59_P_3  */
10504     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10505   },
10506   {
10507     /* VEX_W_0F5A_P_0  */
10508     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10509   },
10510   {
10511     /* VEX_W_0F5A_P_1  */
10512     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10513   },
10514   {
10515     /* VEX_W_0F5A_P_3  */
10516     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10517   },
10518   {
10519     /* VEX_W_0F5B_P_0  */
10520     { "vcvtdq2ps",      { XM, EXx }, 0 },
10521   },
10522   {
10523     /* VEX_W_0F5B_P_1  */
10524     { "vcvttps2dq",     { XM, EXx }, 0 },
10525   },
10526   {
10527     /* VEX_W_0F5B_P_2  */
10528     { "vcvtps2dq",      { XM, EXx }, 0 },
10529   },
10530   {
10531     /* VEX_W_0F5C_P_0  */
10532     { "vsubps",         { XM, Vex, EXx }, 0 },
10533   },
10534   {
10535     /* VEX_W_0F5C_P_1  */
10536     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10537   },
10538   {
10539     /* VEX_W_0F5C_P_2  */
10540     { "vsubpd",         { XM, Vex, EXx }, 0 },
10541   },
10542   {
10543     /* VEX_W_0F5C_P_3  */
10544     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10545   },
10546   {
10547     /* VEX_W_0F5D_P_0  */
10548     { "vminps",         { XM, Vex, EXx }, 0 },
10549   },
10550   {
10551     /* VEX_W_0F5D_P_1  */
10552     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10553   },
10554   {
10555     /* VEX_W_0F5D_P_2  */
10556     { "vminpd",         { XM, Vex, EXx }, 0 },
10557   },
10558   {
10559     /* VEX_W_0F5D_P_3  */
10560     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10561   },
10562   {
10563     /* VEX_W_0F5E_P_0  */
10564     { "vdivps",         { XM, Vex, EXx }, 0 },
10565   },
10566   {
10567     /* VEX_W_0F5E_P_1  */
10568     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10569   },
10570   {
10571     /* VEX_W_0F5E_P_2  */
10572     { "vdivpd",         { XM, Vex, EXx }, 0 },
10573   },
10574   {
10575     /* VEX_W_0F5E_P_3  */
10576     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10577   },
10578   {
10579     /* VEX_W_0F5F_P_0  */
10580     { "vmaxps",         { XM, Vex, EXx }, 0 },
10581   },
10582   {
10583     /* VEX_W_0F5F_P_1  */
10584     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10585   },
10586   {
10587     /* VEX_W_0F5F_P_2  */
10588     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10589   },
10590   {
10591     /* VEX_W_0F5F_P_3  */
10592     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10593   },
10594   {
10595     /* VEX_W_0F60_P_2  */
10596     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10597   },
10598   {
10599     /* VEX_W_0F61_P_2  */
10600     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10601   },
10602   {
10603     /* VEX_W_0F62_P_2  */
10604     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10605   },
10606   {
10607     /* VEX_W_0F63_P_2  */
10608     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10609   },
10610   {
10611     /* VEX_W_0F64_P_2  */
10612     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10613   },
10614   {
10615     /* VEX_W_0F65_P_2  */
10616     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10617   },
10618   {
10619     /* VEX_W_0F66_P_2  */
10620     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10621   },
10622   {
10623     /* VEX_W_0F67_P_2  */
10624     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10625   },
10626   {
10627     /* VEX_W_0F68_P_2  */
10628     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10629   },
10630   {
10631     /* VEX_W_0F69_P_2  */
10632     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10633   },
10634   {
10635     /* VEX_W_0F6A_P_2  */
10636     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10637   },
10638   {
10639     /* VEX_W_0F6B_P_2  */
10640     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10641   },
10642   {
10643     /* VEX_W_0F6C_P_2  */
10644     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10645   },
10646   {
10647     /* VEX_W_0F6D_P_2  */
10648     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10649   },
10650   {
10651     /* VEX_W_0F6F_P_1  */
10652     { "vmovdqu",        { XM, EXx }, 0 },
10653   },
10654   {
10655     /* VEX_W_0F6F_P_2  */
10656     { "vmovdqa",        { XM, EXx }, 0 },
10657   },
10658   {
10659     /* VEX_W_0F70_P_1 */
10660     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10661   },
10662   {
10663     /* VEX_W_0F70_P_2 */
10664     { "vpshufd",        { XM, EXx, Ib }, 0 },
10665   },
10666   {
10667     /* VEX_W_0F70_P_3 */
10668     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10669   },
10670   {
10671     /* VEX_W_0F71_R_2_P_2  */
10672     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10673   },
10674   {
10675     /* VEX_W_0F71_R_4_P_2  */
10676     { "vpsraw",         { Vex, XS, Ib }, 0 },
10677   },
10678   {
10679     /* VEX_W_0F71_R_6_P_2  */
10680     { "vpsllw",         { Vex, XS, Ib }, 0 },
10681   },
10682   {
10683     /* VEX_W_0F72_R_2_P_2  */
10684     { "vpsrld",         { Vex, XS, Ib }, 0 },
10685   },
10686   {
10687     /* VEX_W_0F72_R_4_P_2  */
10688     { "vpsrad",         { Vex, XS, Ib }, 0 },
10689   },
10690   {
10691     /* VEX_W_0F72_R_6_P_2  */
10692     { "vpslld",         { Vex, XS, Ib }, 0 },
10693   },
10694   {
10695     /* VEX_W_0F73_R_2_P_2  */
10696     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10697   },
10698   {
10699     /* VEX_W_0F73_R_3_P_2  */
10700     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10701   },
10702   {
10703     /* VEX_W_0F73_R_6_P_2  */
10704     { "vpsllq",         { Vex, XS, Ib }, 0 },
10705   },
10706   {
10707     /* VEX_W_0F73_R_7_P_2  */
10708     { "vpslldq",        { Vex, XS, Ib }, 0 },
10709   },
10710   {
10711     /* VEX_W_0F74_P_2 */
10712     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10713   },
10714   {
10715     /* VEX_W_0F75_P_2 */
10716     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10717   },
10718   {
10719     /* VEX_W_0F76_P_2 */
10720     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10721   },
10722   {
10723     /* VEX_W_0F77_P_0 */
10724     { "",               { VZERO }, 0 },
10725   },
10726   {
10727     /* VEX_W_0F7C_P_2 */
10728     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10729   },
10730   {
10731     /* VEX_W_0F7C_P_3 */
10732     { "vhaddps",        { XM, Vex, EXx }, 0 },
10733   },
10734   {
10735     /* VEX_W_0F7D_P_2 */
10736     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10737   },
10738   {
10739     /* VEX_W_0F7D_P_3 */
10740     { "vhsubps",        { XM, Vex, EXx }, 0 },
10741   },
10742   {
10743     /* VEX_W_0F7E_P_1 */
10744     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10745   },
10746   {
10747     /* VEX_W_0F7F_P_1 */
10748     { "vmovdqu",        { EXxS, XM }, 0 },
10749   },
10750   {
10751     /* VEX_W_0F7F_P_2 */
10752     { "vmovdqa",        { EXxS, XM }, 0 },
10753   },
10754   {
10755     /* VEX_W_0F90_P_0_LEN_0 */
10756     { "kmovw",          { MaskG, MaskE }, 0 },
10757     { "kmovq",          { MaskG, MaskE }, 0 },
10758   },
10759   {
10760     /* VEX_W_0F90_P_2_LEN_0 */
10761     { "kmovb",          { MaskG, MaskBDE }, 0 },
10762     { "kmovd",          { MaskG, MaskBDE }, 0 },
10763   },
10764   {
10765     /* VEX_W_0F91_P_0_LEN_0 */
10766     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10767     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10768   },
10769   {
10770     /* VEX_W_0F91_P_2_LEN_0 */
10771     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10772     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10773   },
10774   {
10775     /* VEX_W_0F92_P_0_LEN_0 */
10776     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10777   },
10778   {
10779     /* VEX_W_0F92_P_2_LEN_0 */
10780     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10781   },
10782   {
10783     /* VEX_W_0F92_P_3_LEN_0 */
10784     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10785     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10786   },
10787   {
10788     /* VEX_W_0F93_P_0_LEN_0 */
10789     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10790   },
10791   {
10792     /* VEX_W_0F93_P_2_LEN_0 */
10793     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10794   },
10795   {
10796     /* VEX_W_0F93_P_3_LEN_0 */
10797     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10798     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10799   },
10800   {
10801     /* VEX_W_0F98_P_0_LEN_0 */
10802     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10803     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10804   },
10805   {
10806     /* VEX_W_0F98_P_2_LEN_0 */
10807     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10808     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10809   },
10810   {
10811     /* VEX_W_0F99_P_0_LEN_0 */
10812     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10813     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10814   },
10815   {
10816     /* VEX_W_0F99_P_2_LEN_0 */
10817     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10818     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10819   },
10820   {
10821     /* VEX_W_0FAE_R_2_M_0 */
10822     { "vldmxcsr",       { Md }, 0 },
10823   },
10824   {
10825     /* VEX_W_0FAE_R_3_M_0 */
10826     { "vstmxcsr",       { Md }, 0 },
10827   },
10828   {
10829     /* VEX_W_0FC2_P_0 */
10830     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10831   },
10832   {
10833     /* VEX_W_0FC2_P_1 */
10834     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10835   },
10836   {
10837     /* VEX_W_0FC2_P_2 */
10838     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10839   },
10840   {
10841     /* VEX_W_0FC2_P_3 */
10842     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10843   },
10844   {
10845     /* VEX_W_0FC4_P_2 */
10846     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10847   },
10848   {
10849     /* VEX_W_0FC5_P_2 */
10850     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10851   },
10852   {
10853     /* VEX_W_0FD0_P_2 */
10854     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10855   },
10856   {
10857     /* VEX_W_0FD0_P_3 */
10858     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10859   },
10860   {
10861     /* VEX_W_0FD1_P_2 */
10862     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10863   },
10864   {
10865     /* VEX_W_0FD2_P_2 */
10866     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10867   },
10868   {
10869     /* VEX_W_0FD3_P_2 */
10870     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10871   },
10872   {
10873     /* VEX_W_0FD4_P_2 */
10874     { "vpaddq",         { XM, Vex, EXx }, 0 },
10875   },
10876   {
10877     /* VEX_W_0FD5_P_2 */
10878     { "vpmullw",        { XM, Vex, EXx }, 0 },
10879   },
10880   {
10881     /* VEX_W_0FD6_P_2 */
10882     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10883   },
10884   {
10885     /* VEX_W_0FD7_P_2_M_1 */
10886     { "vpmovmskb",      { Gdq, XS }, 0 },
10887   },
10888   {
10889     /* VEX_W_0FD8_P_2 */
10890     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10891   },
10892   {
10893     /* VEX_W_0FD9_P_2 */
10894     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10895   },
10896   {
10897     /* VEX_W_0FDA_P_2 */
10898     { "vpminub",        { XM, Vex, EXx }, 0 },
10899   },
10900   {
10901     /* VEX_W_0FDB_P_2 */
10902     { "vpand",          { XM, Vex, EXx }, 0 },
10903   },
10904   {
10905     /* VEX_W_0FDC_P_2 */
10906     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10907   },
10908   {
10909     /* VEX_W_0FDD_P_2 */
10910     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10911   },
10912   {
10913     /* VEX_W_0FDE_P_2 */
10914     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10915   },
10916   {
10917     /* VEX_W_0FDF_P_2 */
10918     { "vpandn",         { XM, Vex, EXx }, 0 },
10919   },
10920   {
10921     /* VEX_W_0FE0_P_2  */
10922     { "vpavgb",         { XM, Vex, EXx }, 0 },
10923   },
10924   {
10925     /* VEX_W_0FE1_P_2  */
10926     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10927   },
10928   {
10929     /* VEX_W_0FE2_P_2  */
10930     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10931   },
10932   {
10933     /* VEX_W_0FE3_P_2  */
10934     { "vpavgw",         { XM, Vex, EXx }, 0 },
10935   },
10936   {
10937     /* VEX_W_0FE4_P_2  */
10938     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
10939   },
10940   {
10941     /* VEX_W_0FE5_P_2  */
10942     { "vpmulhw",        { XM, Vex, EXx }, 0 },
10943   },
10944   {
10945     /* VEX_W_0FE6_P_1  */
10946     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
10947   },
10948   {
10949     /* VEX_W_0FE6_P_2  */
10950     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
10951   },
10952   {
10953     /* VEX_W_0FE6_P_3  */
10954     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
10955   },
10956   {
10957     /* VEX_W_0FE7_P_2_M_0 */
10958     { "vmovntdq",       { Mx, XM }, 0 },
10959   },
10960   {
10961     /* VEX_W_0FE8_P_2  */
10962     { "vpsubsb",        { XM, Vex, EXx }, 0 },
10963   },
10964   {
10965     /* VEX_W_0FE9_P_2  */
10966     { "vpsubsw",        { XM, Vex, EXx }, 0 },
10967   },
10968   {
10969     /* VEX_W_0FEA_P_2  */
10970     { "vpminsw",        { XM, Vex, EXx }, 0 },
10971   },
10972   {
10973     /* VEX_W_0FEB_P_2  */
10974     { "vpor",           { XM, Vex, EXx }, 0 },
10975   },
10976   {
10977     /* VEX_W_0FEC_P_2  */
10978     { "vpaddsb",        { XM, Vex, EXx }, 0 },
10979   },
10980   {
10981     /* VEX_W_0FED_P_2  */
10982     { "vpaddsw",        { XM, Vex, EXx }, 0 },
10983   },
10984   {
10985     /* VEX_W_0FEE_P_2  */
10986     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
10987   },
10988   {
10989     /* VEX_W_0FEF_P_2  */
10990     { "vpxor",          { XM, Vex, EXx }, 0 },
10991   },
10992   {
10993     /* VEX_W_0FF0_P_3_M_0 */
10994     { "vlddqu",         { XM, M }, 0 },
10995   },
10996   {
10997     /* VEX_W_0FF1_P_2 */
10998     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
10999   },
11000   {
11001     /* VEX_W_0FF2_P_2 */
11002     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11003   },
11004   {
11005     /* VEX_W_0FF3_P_2 */
11006     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11007   },
11008   {
11009     /* VEX_W_0FF4_P_2 */
11010     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11011   },
11012   {
11013     /* VEX_W_0FF5_P_2 */
11014     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11015   },
11016   {
11017     /* VEX_W_0FF6_P_2 */
11018     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11019   },
11020   {
11021     /* VEX_W_0FF7_P_2 */
11022     { "vmaskmovdqu",    { XM, XS }, 0 },
11023   },
11024   {
11025     /* VEX_W_0FF8_P_2 */
11026     { "vpsubb",         { XM, Vex, EXx }, 0 },
11027   },
11028   {
11029     /* VEX_W_0FF9_P_2 */
11030     { "vpsubw",         { XM, Vex, EXx }, 0 },
11031   },
11032   {
11033     /* VEX_W_0FFA_P_2 */
11034     { "vpsubd",         { XM, Vex, EXx }, 0 },
11035   },
11036   {
11037     /* VEX_W_0FFB_P_2 */
11038     { "vpsubq",         { XM, Vex, EXx }, 0 },
11039   },
11040   {
11041     /* VEX_W_0FFC_P_2 */
11042     { "vpaddb",         { XM, Vex, EXx }, 0 },
11043   },
11044   {
11045     /* VEX_W_0FFD_P_2 */
11046     { "vpaddw",         { XM, Vex, EXx }, 0 },
11047   },
11048   {
11049     /* VEX_W_0FFE_P_2 */
11050     { "vpaddd",         { XM, Vex, EXx }, 0 },
11051   },
11052   {
11053     /* VEX_W_0F3800_P_2  */
11054     { "vpshufb",        { XM, Vex, EXx }, 0 },
11055   },
11056   {
11057     /* VEX_W_0F3801_P_2  */
11058     { "vphaddw",        { XM, Vex, EXx }, 0 },
11059   },
11060   {
11061     /* VEX_W_0F3802_P_2  */
11062     { "vphaddd",        { XM, Vex, EXx }, 0 },
11063   },
11064   {
11065     /* VEX_W_0F3803_P_2  */
11066     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11067   },
11068   {
11069     /* VEX_W_0F3804_P_2  */
11070     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11071   },
11072   {
11073     /* VEX_W_0F3805_P_2  */
11074     { "vphsubw",        { XM, Vex, EXx }, 0 },
11075   },
11076   {
11077     /* VEX_W_0F3806_P_2  */
11078     { "vphsubd",        { XM, Vex, EXx }, 0 },
11079   },
11080   {
11081     /* VEX_W_0F3807_P_2  */
11082     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11083   },
11084   {
11085     /* VEX_W_0F3808_P_2  */
11086     { "vpsignb",        { XM, Vex, EXx }, 0 },
11087   },
11088   {
11089     /* VEX_W_0F3809_P_2  */
11090     { "vpsignw",        { XM, Vex, EXx }, 0 },
11091   },
11092   {
11093     /* VEX_W_0F380A_P_2  */
11094     { "vpsignd",        { XM, Vex, EXx }, 0 },
11095   },
11096   {
11097     /* VEX_W_0F380B_P_2  */
11098     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11099   },
11100   {
11101     /* VEX_W_0F380C_P_2  */
11102     { "vpermilps",      { XM, Vex, EXx }, 0 },
11103   },
11104   {
11105     /* VEX_W_0F380D_P_2  */
11106     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11107   },
11108   {
11109     /* VEX_W_0F380E_P_2  */
11110     { "vtestps",        { XM, EXx }, 0 },
11111   },
11112   {
11113     /* VEX_W_0F380F_P_2  */
11114     { "vtestpd",        { XM, EXx }, 0 },
11115   },
11116   {
11117     /* VEX_W_0F3816_P_2  */
11118     { "vpermps",        { XM, Vex, EXx }, 0 },
11119   },
11120   {
11121     /* VEX_W_0F3817_P_2 */
11122     { "vptest",         { XM, EXx }, 0 },
11123   },
11124   {
11125     /* VEX_W_0F3818_P_2 */
11126     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11127   },
11128   {
11129     /* VEX_W_0F3819_P_2 */
11130     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11131   },
11132   {
11133     /* VEX_W_0F381A_P_2_M_0 */
11134     { "vbroadcastf128", { XM, Mxmm }, 0 },
11135   },
11136   {
11137     /* VEX_W_0F381C_P_2 */
11138     { "vpabsb",         { XM, EXx }, 0 },
11139   },
11140   {
11141     /* VEX_W_0F381D_P_2 */
11142     { "vpabsw",         { XM, EXx }, 0 },
11143   },
11144   {
11145     /* VEX_W_0F381E_P_2 */
11146     { "vpabsd",         { XM, EXx }, 0 },
11147   },
11148   {
11149     /* VEX_W_0F3820_P_2 */
11150     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11151   },
11152   {
11153     /* VEX_W_0F3821_P_2 */
11154     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11155   },
11156   {
11157     /* VEX_W_0F3822_P_2 */
11158     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11159   },
11160   {
11161     /* VEX_W_0F3823_P_2 */
11162     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11163   },
11164   {
11165     /* VEX_W_0F3824_P_2 */
11166     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11167   },
11168   {
11169     /* VEX_W_0F3825_P_2 */
11170     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11171   },
11172   {
11173     /* VEX_W_0F3828_P_2 */
11174     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11175   },
11176   {
11177     /* VEX_W_0F3829_P_2 */
11178     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11179   },
11180   {
11181     /* VEX_W_0F382A_P_2_M_0 */
11182     { "vmovntdqa",      { XM, Mx }, 0 },
11183   },
11184   {
11185     /* VEX_W_0F382B_P_2 */
11186     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11187   },
11188   {
11189     /* VEX_W_0F382C_P_2_M_0 */
11190     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11191   },
11192   {
11193     /* VEX_W_0F382D_P_2_M_0 */
11194     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11195   },
11196   {
11197     /* VEX_W_0F382E_P_2_M_0 */
11198     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11199   },
11200   {
11201     /* VEX_W_0F382F_P_2_M_0 */
11202     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11203   },
11204   {
11205     /* VEX_W_0F3830_P_2 */
11206     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11207   },
11208   {
11209     /* VEX_W_0F3831_P_2 */
11210     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11211   },
11212   {
11213     /* VEX_W_0F3832_P_2 */
11214     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11215   },
11216   {
11217     /* VEX_W_0F3833_P_2 */
11218     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11219   },
11220   {
11221     /* VEX_W_0F3834_P_2 */
11222     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11223   },
11224   {
11225     /* VEX_W_0F3835_P_2 */
11226     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11227   },
11228   {
11229     /* VEX_W_0F3836_P_2  */
11230     { "vpermd",         { XM, Vex, EXx }, 0 },
11231   },
11232   {
11233     /* VEX_W_0F3837_P_2 */
11234     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11235   },
11236   {
11237     /* VEX_W_0F3838_P_2 */
11238     { "vpminsb",        { XM, Vex, EXx }, 0 },
11239   },
11240   {
11241     /* VEX_W_0F3839_P_2 */
11242     { "vpminsd",        { XM, Vex, EXx }, 0 },
11243   },
11244   {
11245     /* VEX_W_0F383A_P_2 */
11246     { "vpminuw",        { XM, Vex, EXx }, 0 },
11247   },
11248   {
11249     /* VEX_W_0F383B_P_2 */
11250     { "vpminud",        { XM, Vex, EXx }, 0 },
11251   },
11252   {
11253     /* VEX_W_0F383C_P_2 */
11254     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11255   },
11256   {
11257     /* VEX_W_0F383D_P_2 */
11258     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11259   },
11260   {
11261     /* VEX_W_0F383E_P_2 */
11262     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11263   },
11264   {
11265     /* VEX_W_0F383F_P_2 */
11266     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11267   },
11268   {
11269     /* VEX_W_0F3840_P_2 */
11270     { "vpmulld",        { XM, Vex, EXx }, 0 },
11271   },
11272   {
11273     /* VEX_W_0F3841_P_2 */
11274     { "vphminposuw",    { XM, EXx }, 0 },
11275   },
11276   {
11277     /* VEX_W_0F3846_P_2 */
11278     { "vpsravd",        { XM, Vex, EXx }, 0 },
11279   },
11280   {
11281     /* VEX_W_0F3858_P_2 */
11282     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11283   },
11284   {
11285     /* VEX_W_0F3859_P_2 */
11286     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11287   },
11288   {
11289     /* VEX_W_0F385A_P_2_M_0 */
11290     { "vbroadcasti128", { XM, Mxmm }, 0 },
11291   },
11292   {
11293     /* VEX_W_0F3878_P_2 */
11294     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11295   },
11296   {
11297     /* VEX_W_0F3879_P_2 */
11298     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11299   },
11300   {
11301     /* VEX_W_0F38CF_P_2 */
11302     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
11303   },
11304   {
11305     /* VEX_W_0F38DB_P_2 */
11306     { "vaesimc",        { XM, EXx }, 0 },
11307   },
11308   {
11309     /* VEX_W_0F3A00_P_2 */
11310     { Bad_Opcode },
11311     { "vpermq",         { XM, EXx, Ib }, 0 },
11312   },
11313   {
11314     /* VEX_W_0F3A01_P_2 */
11315     { Bad_Opcode },
11316     { "vpermpd",        { XM, EXx, Ib }, 0 },
11317   },
11318   {
11319     /* VEX_W_0F3A02_P_2 */
11320     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11321   },
11322   {
11323     /* VEX_W_0F3A04_P_2 */
11324     { "vpermilps",      { XM, EXx, Ib }, 0 },
11325   },
11326   {
11327     /* VEX_W_0F3A05_P_2 */
11328     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11329   },
11330   {
11331     /* VEX_W_0F3A06_P_2 */
11332     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11333   },
11334   {
11335     /* VEX_W_0F3A08_P_2 */
11336     { "vroundps",       { XM, EXx, Ib }, 0 },
11337   },
11338   {
11339     /* VEX_W_0F3A09_P_2 */
11340     { "vroundpd",       { XM, EXx, Ib }, 0 },
11341   },
11342   {
11343     /* VEX_W_0F3A0A_P_2 */
11344     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11345   },
11346   {
11347     /* VEX_W_0F3A0B_P_2 */
11348     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11349   },
11350   {
11351     /* VEX_W_0F3A0C_P_2 */
11352     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11353   },
11354   {
11355     /* VEX_W_0F3A0D_P_2 */
11356     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11357   },
11358   {
11359     /* VEX_W_0F3A0E_P_2 */
11360     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11361   },
11362   {
11363     /* VEX_W_0F3A0F_P_2 */
11364     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11365   },
11366   {
11367     /* VEX_W_0F3A14_P_2 */
11368     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11369   },
11370   {
11371     /* VEX_W_0F3A15_P_2 */
11372     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11373   },
11374   {
11375     /* VEX_W_0F3A18_P_2 */
11376     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11377   },
11378   {
11379     /* VEX_W_0F3A19_P_2 */
11380     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11381   },
11382   {
11383     /* VEX_W_0F3A20_P_2 */
11384     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11385   },
11386   {
11387     /* VEX_W_0F3A21_P_2 */
11388     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11389   },
11390   {
11391     /* VEX_W_0F3A30_P_2_LEN_0 */
11392     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11393     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11394   },
11395   {
11396     /* VEX_W_0F3A31_P_2_LEN_0 */
11397     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11398     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11399   },
11400   {
11401     /* VEX_W_0F3A32_P_2_LEN_0 */
11402     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11403     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11404   },
11405   {
11406     /* VEX_W_0F3A33_P_2_LEN_0 */
11407     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11408     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11409   },
11410   {
11411     /* VEX_W_0F3A38_P_2 */
11412     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11413   },
11414   {
11415     /* VEX_W_0F3A39_P_2 */
11416     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11417   },
11418   {
11419     /* VEX_W_0F3A40_P_2 */
11420     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11421   },
11422   {
11423     /* VEX_W_0F3A41_P_2 */
11424     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11425   },
11426   {
11427     /* VEX_W_0F3A42_P_2 */
11428     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11429   },
11430   {
11431     /* VEX_W_0F3A46_P_2 */
11432     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11433   },
11434   {
11435     /* VEX_W_0F3A48_P_2 */
11436     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11437     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11438   },
11439   {
11440     /* VEX_W_0F3A49_P_2 */
11441     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11442     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11443   },
11444   {
11445     /* VEX_W_0F3A4A_P_2 */
11446     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11447   },
11448   {
11449     /* VEX_W_0F3A4B_P_2 */
11450     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11451   },
11452   {
11453     /* VEX_W_0F3A4C_P_2 */
11454     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11455   },
11456   {
11457     /* VEX_W_0F3A62_P_2 */
11458     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11459   },
11460   {
11461     /* VEX_W_0F3A63_P_2 */
11462     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11463   },
11464   {
11465     /* VEX_W_0F3ACE_P_2 */
11466     { Bad_Opcode },
11467     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
11468   },
11469   {
11470     /* VEX_W_0F3ACF_P_2 */
11471     { Bad_Opcode },
11472     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
11473   },
11474   {
11475     /* VEX_W_0F3ADF_P_2 */
11476     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11477   },
11478 #define NEED_VEX_W_TABLE
11479 #include "i386-dis-evex.h"
11480 #undef NEED_VEX_W_TABLE
11481 };
11482
11483 static const struct dis386 mod_table[][2] = {
11484   {
11485     /* MOD_8D */
11486     { "leaS",           { Gv, M }, 0 },
11487   },
11488   {
11489     /* MOD_C6_REG_7 */
11490     { Bad_Opcode },
11491     { RM_TABLE (RM_C6_REG_7) },
11492   },
11493   {
11494     /* MOD_C7_REG_7 */
11495     { Bad_Opcode },
11496     { RM_TABLE (RM_C7_REG_7) },
11497   },
11498   {
11499     /* MOD_FF_REG_3 */
11500     { "Jcall^", { indirEp }, 0 },
11501   },
11502   {
11503     /* MOD_FF_REG_5 */
11504     { "Jjmp^", { indirEp }, 0 },
11505   },
11506   {
11507     /* MOD_0F01_REG_0 */
11508     { X86_64_TABLE (X86_64_0F01_REG_0) },
11509     { RM_TABLE (RM_0F01_REG_0) },
11510   },
11511   {
11512     /* MOD_0F01_REG_1 */
11513     { X86_64_TABLE (X86_64_0F01_REG_1) },
11514     { RM_TABLE (RM_0F01_REG_1) },
11515   },
11516   {
11517     /* MOD_0F01_REG_2 */
11518     { X86_64_TABLE (X86_64_0F01_REG_2) },
11519     { RM_TABLE (RM_0F01_REG_2) },
11520   },
11521   {
11522     /* MOD_0F01_REG_3 */
11523     { X86_64_TABLE (X86_64_0F01_REG_3) },
11524     { RM_TABLE (RM_0F01_REG_3) },
11525   },
11526   {
11527     /* MOD_0F01_REG_5 */
11528     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11529     { RM_TABLE (RM_0F01_REG_5) },
11530   },
11531   {
11532     /* MOD_0F01_REG_7 */
11533     { "invlpg",         { Mb }, 0 },
11534     { RM_TABLE (RM_0F01_REG_7) },
11535   },
11536   {
11537     /* MOD_0F12_PREFIX_0 */
11538     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11539     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11540   },
11541   {
11542     /* MOD_0F13 */
11543     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11544   },
11545   {
11546     /* MOD_0F16_PREFIX_0 */
11547     { "movhps",         { XM, EXq }, 0 },
11548     { "movlhps",        { XM, EXq }, 0 },
11549   },
11550   {
11551     /* MOD_0F17 */
11552     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11553   },
11554   {
11555     /* MOD_0F18_REG_0 */
11556     { "prefetchnta",    { Mb }, 0 },
11557   },
11558   {
11559     /* MOD_0F18_REG_1 */
11560     { "prefetcht0",     { Mb }, 0 },
11561   },
11562   {
11563     /* MOD_0F18_REG_2 */
11564     { "prefetcht1",     { Mb }, 0 },
11565   },
11566   {
11567     /* MOD_0F18_REG_3 */
11568     { "prefetcht2",     { Mb }, 0 },
11569   },
11570   {
11571     /* MOD_0F18_REG_4 */
11572     { "nop/reserved",   { Mb }, 0 },
11573   },
11574   {
11575     /* MOD_0F18_REG_5 */
11576     { "nop/reserved",   { Mb }, 0 },
11577   },
11578   {
11579     /* MOD_0F18_REG_6 */
11580     { "nop/reserved",   { Mb }, 0 },
11581   },
11582   {
11583     /* MOD_0F18_REG_7 */
11584     { "nop/reserved",   { Mb }, 0 },
11585   },
11586   {
11587     /* MOD_0F1A_PREFIX_0 */
11588     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11589     { "nopQ",           { Ev }, 0 },
11590   },
11591   {
11592     /* MOD_0F1B_PREFIX_0 */
11593     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11594     { "nopQ",           { Ev }, 0 },
11595   },
11596   {
11597     /* MOD_0F1B_PREFIX_1 */
11598     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11599     { "nopQ",           { Ev }, 0 },
11600   },
11601   {
11602     /* MOD_0F1E_PREFIX_1 */
11603     { "nopQ",           { Ev }, 0 },
11604     { REG_TABLE (REG_0F1E_MOD_3) },
11605   },
11606   {
11607     /* MOD_0F24 */
11608     { Bad_Opcode },
11609     { "movL",           { Rd, Td }, 0 },
11610   },
11611   {
11612     /* MOD_0F26 */
11613     { Bad_Opcode },
11614     { "movL",           { Td, Rd }, 0 },
11615   },
11616   {
11617     /* MOD_0F2B_PREFIX_0 */
11618     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11619   },
11620   {
11621     /* MOD_0F2B_PREFIX_1 */
11622     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11623   },
11624   {
11625     /* MOD_0F2B_PREFIX_2 */
11626     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11627   },
11628   {
11629     /* MOD_0F2B_PREFIX_3 */
11630     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11631   },
11632   {
11633     /* MOD_0F51 */
11634     { Bad_Opcode },
11635     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11636   },
11637   {
11638     /* MOD_0F71_REG_2 */
11639     { Bad_Opcode },
11640     { "psrlw",          { MS, Ib }, 0 },
11641   },
11642   {
11643     /* MOD_0F71_REG_4 */
11644     { Bad_Opcode },
11645     { "psraw",          { MS, Ib }, 0 },
11646   },
11647   {
11648     /* MOD_0F71_REG_6 */
11649     { Bad_Opcode },
11650     { "psllw",          { MS, Ib }, 0 },
11651   },
11652   {
11653     /* MOD_0F72_REG_2 */
11654     { Bad_Opcode },
11655     { "psrld",          { MS, Ib }, 0 },
11656   },
11657   {
11658     /* MOD_0F72_REG_4 */
11659     { Bad_Opcode },
11660     { "psrad",          { MS, Ib }, 0 },
11661   },
11662   {
11663     /* MOD_0F72_REG_6 */
11664     { Bad_Opcode },
11665     { "pslld",          { MS, Ib }, 0 },
11666   },
11667   {
11668     /* MOD_0F73_REG_2 */
11669     { Bad_Opcode },
11670     { "psrlq",          { MS, Ib }, 0 },
11671   },
11672   {
11673     /* MOD_0F73_REG_3 */
11674     { Bad_Opcode },
11675     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11676   },
11677   {
11678     /* MOD_0F73_REG_6 */
11679     { Bad_Opcode },
11680     { "psllq",          { MS, Ib }, 0 },
11681   },
11682   {
11683     /* MOD_0F73_REG_7 */
11684     { Bad_Opcode },
11685     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11686   },
11687   {
11688     /* MOD_0FAE_REG_0 */
11689     { "fxsave",         { FXSAVE }, 0 },
11690     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11691   },
11692   {
11693     /* MOD_0FAE_REG_1 */
11694     { "fxrstor",        { FXSAVE }, 0 },
11695     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11696   },
11697   {
11698     /* MOD_0FAE_REG_2 */
11699     { "ldmxcsr",        { Md }, 0 },
11700     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11701   },
11702   {
11703     /* MOD_0FAE_REG_3 */
11704     { "stmxcsr",        { Md }, 0 },
11705     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11706   },
11707   {
11708     /* MOD_0FAE_REG_4 */
11709     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11710     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11711   },
11712   {
11713     /* MOD_0FAE_REG_5 */
11714     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11715     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11716   },
11717   {
11718     /* MOD_0FAE_REG_6 */
11719     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11720     { RM_TABLE (RM_0FAE_REG_6) },
11721   },
11722   {
11723     /* MOD_0FAE_REG_7 */
11724     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11725     { RM_TABLE (RM_0FAE_REG_7) },
11726   },
11727   {
11728     /* MOD_0FB2 */
11729     { "lssS",           { Gv, Mp }, 0 },
11730   },
11731   {
11732     /* MOD_0FB4 */
11733     { "lfsS",           { Gv, Mp }, 0 },
11734   },
11735   {
11736     /* MOD_0FB5 */
11737     { "lgsS",           { Gv, Mp }, 0 },
11738   },
11739   {
11740     /* MOD_0FC3 */
11741     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11742   },
11743   {
11744     /* MOD_0FC7_REG_3 */
11745     { "xrstors",        { FXSAVE }, 0 },
11746   },
11747   {
11748     /* MOD_0FC7_REG_4 */
11749     { "xsavec",         { FXSAVE }, 0 },
11750   },
11751   {
11752     /* MOD_0FC7_REG_5 */
11753     { "xsaves",         { FXSAVE }, 0 },
11754   },
11755   {
11756     /* MOD_0FC7_REG_6 */
11757     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11758     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11759   },
11760   {
11761     /* MOD_0FC7_REG_7 */
11762     { "vmptrst",        { Mq }, 0 },
11763     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11764   },
11765   {
11766     /* MOD_0FD7 */
11767     { Bad_Opcode },
11768     { "pmovmskb",       { Gdq, MS }, 0 },
11769   },
11770   {
11771     /* MOD_0FE7_PREFIX_2 */
11772     { "movntdq",        { Mx, XM }, 0 },
11773   },
11774   {
11775     /* MOD_0FF0_PREFIX_3 */
11776     { "lddqu",          { XM, M }, 0 },
11777   },
11778   {
11779     /* MOD_0F382A_PREFIX_2 */
11780     { "movntdqa",       { XM, Mx }, 0 },
11781   },
11782   {
11783     /* MOD_0F38F5_PREFIX_2 */
11784     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11785   },
11786   {
11787     /* MOD_0F38F6_PREFIX_0 */
11788     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11789   },
11790   {
11791     /* MOD_62_32BIT */
11792     { "bound{S|}",      { Gv, Ma }, 0 },
11793     { EVEX_TABLE (EVEX_0F) },
11794   },
11795   {
11796     /* MOD_C4_32BIT */
11797     { "lesS",           { Gv, Mp }, 0 },
11798     { VEX_C4_TABLE (VEX_0F) },
11799   },
11800   {
11801     /* MOD_C5_32BIT */
11802     { "ldsS",           { Gv, Mp }, 0 },
11803     { VEX_C5_TABLE (VEX_0F) },
11804   },
11805   {
11806     /* MOD_VEX_0F12_PREFIX_0 */
11807     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11808     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11809   },
11810   {
11811     /* MOD_VEX_0F13 */
11812     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11813   },
11814   {
11815     /* MOD_VEX_0F16_PREFIX_0 */
11816     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11817     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11818   },
11819   {
11820     /* MOD_VEX_0F17 */
11821     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11822   },
11823   {
11824     /* MOD_VEX_0F2B */
11825     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11826   },
11827   {
11828     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11829     { Bad_Opcode },
11830     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11831   },
11832   {
11833     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11834     { Bad_Opcode },
11835     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11836   },
11837   {
11838     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11839     { Bad_Opcode },
11840     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11841   },
11842   {
11843     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11844     { Bad_Opcode },
11845     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11846   },
11847   {
11848     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11849     { Bad_Opcode },
11850     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11851   },
11852   {
11853     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11854     { Bad_Opcode },
11855     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11856   },
11857   {
11858     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11859     { Bad_Opcode },
11860     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11861   },
11862   {
11863     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11864     { Bad_Opcode },
11865     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11866   },
11867   {
11868     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11869     { Bad_Opcode },
11870     { "knotw",          { MaskG, MaskR }, 0 },
11871   },
11872   {
11873     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11874     { Bad_Opcode },
11875     { "knotq",          { MaskG, MaskR }, 0 },
11876   },
11877   {
11878     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11879     { Bad_Opcode },
11880     { "knotb",          { MaskG, MaskR }, 0 },
11881   },
11882   {
11883     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11884     { Bad_Opcode },
11885     { "knotd",          { MaskG, MaskR }, 0 },
11886   },
11887   {
11888     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11889     { Bad_Opcode },
11890     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11891   },
11892   {
11893     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11894     { Bad_Opcode },
11895     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11896   },
11897   {
11898     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11899     { Bad_Opcode },
11900     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11901   },
11902   {
11903     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11904     { Bad_Opcode },
11905     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11906   },
11907  {
11908     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11909     { Bad_Opcode },
11910     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11911   },
11912   {
11913     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11914     { Bad_Opcode },
11915     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11916   },
11917   {
11918     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11919     { Bad_Opcode },
11920     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11921   },
11922   {
11923     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11924     { Bad_Opcode },
11925     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11926   },
11927   {
11928     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11929     { Bad_Opcode },
11930     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11931   },
11932   {
11933     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11934     { Bad_Opcode },
11935     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11936   },
11937   {
11938     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11939     { Bad_Opcode },
11940     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11941   },
11942   {
11943     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11944     { Bad_Opcode },
11945     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11946   },
11947   {
11948     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11949     { Bad_Opcode },
11950     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11951   },
11952   {
11953     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11954     { Bad_Opcode },
11955     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11956   },
11957   {
11958     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11959     { Bad_Opcode },
11960     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11961   },
11962   {
11963     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11964     { Bad_Opcode },
11965     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11966   },
11967   {
11968     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11969     { Bad_Opcode },
11970     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11971   },
11972   {
11973     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11974     { Bad_Opcode },
11975     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11976   },
11977   {
11978     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11979     { Bad_Opcode },
11980     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11981   },
11982   {
11983     /* MOD_VEX_0F50 */
11984     { Bad_Opcode },
11985     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11986   },
11987   {
11988     /* MOD_VEX_0F71_REG_2 */
11989     { Bad_Opcode },
11990     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11991   },
11992   {
11993     /* MOD_VEX_0F71_REG_4 */
11994     { Bad_Opcode },
11995     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11996   },
11997   {
11998     /* MOD_VEX_0F71_REG_6 */
11999     { Bad_Opcode },
12000     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12001   },
12002   {
12003     /* MOD_VEX_0F72_REG_2 */
12004     { Bad_Opcode },
12005     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12006   },
12007   {
12008     /* MOD_VEX_0F72_REG_4 */
12009     { Bad_Opcode },
12010     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12011   },
12012   {
12013     /* MOD_VEX_0F72_REG_6 */
12014     { Bad_Opcode },
12015     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12016   },
12017   {
12018     /* MOD_VEX_0F73_REG_2 */
12019     { Bad_Opcode },
12020     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12021   },
12022   {
12023     /* MOD_VEX_0F73_REG_3 */
12024     { Bad_Opcode },
12025     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12026   },
12027   {
12028     /* MOD_VEX_0F73_REG_6 */
12029     { Bad_Opcode },
12030     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12031   },
12032   {
12033     /* MOD_VEX_0F73_REG_7 */
12034     { Bad_Opcode },
12035     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12036   },
12037   {
12038     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12039     { "kmovw",          { Ew, MaskG }, 0 },
12040     { Bad_Opcode },
12041   },
12042   {
12043     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12044     { "kmovq",          { Eq, MaskG }, 0 },
12045     { Bad_Opcode },
12046   },
12047   {
12048     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12049     { "kmovb",          { Eb, MaskG }, 0 },
12050     { Bad_Opcode },
12051   },
12052   {
12053     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12054     { "kmovd",          { Ed, MaskG }, 0 },
12055     { Bad_Opcode },
12056   },
12057   {
12058     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12059     { Bad_Opcode },
12060     { "kmovw",          { MaskG, Rdq }, 0 },
12061   },
12062   {
12063     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12064     { Bad_Opcode },
12065     { "kmovb",          { MaskG, Rdq }, 0 },
12066   },
12067   {
12068     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12069     { Bad_Opcode },
12070     { "kmovd",          { MaskG, Rdq }, 0 },
12071   },
12072   {
12073     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12074     { Bad_Opcode },
12075     { "kmovq",          { MaskG, Rdq }, 0 },
12076   },
12077   {
12078     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12079     { Bad_Opcode },
12080     { "kmovw",          { Gdq, MaskR }, 0 },
12081   },
12082   {
12083     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12084     { Bad_Opcode },
12085     { "kmovb",          { Gdq, MaskR }, 0 },
12086   },
12087   {
12088     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12089     { Bad_Opcode },
12090     { "kmovd",          { Gdq, MaskR }, 0 },
12091   },
12092   {
12093     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12094     { Bad_Opcode },
12095     { "kmovq",          { Gdq, MaskR }, 0 },
12096   },
12097   {
12098     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12099     { Bad_Opcode },
12100     { "kortestw", { MaskG, MaskR }, 0 },
12101   },
12102   {
12103     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12104     { Bad_Opcode },
12105     { "kortestq", { MaskG, MaskR }, 0 },
12106   },
12107   {
12108     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12109     { Bad_Opcode },
12110     { "kortestb", { MaskG, MaskR }, 0 },
12111   },
12112   {
12113     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12114     { Bad_Opcode },
12115     { "kortestd", { MaskG, MaskR }, 0 },
12116   },
12117   {
12118     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12119     { Bad_Opcode },
12120     { "ktestw", { MaskG, MaskR }, 0 },
12121   },
12122   {
12123     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12124     { Bad_Opcode },
12125     { "ktestq", { MaskG, MaskR }, 0 },
12126   },
12127   {
12128     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12129     { Bad_Opcode },
12130     { "ktestb", { MaskG, MaskR }, 0 },
12131   },
12132   {
12133     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12134     { Bad_Opcode },
12135     { "ktestd", { MaskG, MaskR }, 0 },
12136   },
12137   {
12138     /* MOD_VEX_0FAE_REG_2 */
12139     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12140   },
12141   {
12142     /* MOD_VEX_0FAE_REG_3 */
12143     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12144   },
12145   {
12146     /* MOD_VEX_0FD7_PREFIX_2 */
12147     { Bad_Opcode },
12148     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12149   },
12150   {
12151     /* MOD_VEX_0FE7_PREFIX_2 */
12152     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12153   },
12154   {
12155     /* MOD_VEX_0FF0_PREFIX_3 */
12156     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12157   },
12158   {
12159     /* MOD_VEX_0F381A_PREFIX_2 */
12160     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12161   },
12162   {
12163     /* MOD_VEX_0F382A_PREFIX_2 */
12164     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12165   },
12166   {
12167     /* MOD_VEX_0F382C_PREFIX_2 */
12168     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12169   },
12170   {
12171     /* MOD_VEX_0F382D_PREFIX_2 */
12172     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12173   },
12174   {
12175     /* MOD_VEX_0F382E_PREFIX_2 */
12176     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12177   },
12178   {
12179     /* MOD_VEX_0F382F_PREFIX_2 */
12180     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12181   },
12182   {
12183     /* MOD_VEX_0F385A_PREFIX_2 */
12184     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12185   },
12186   {
12187     /* MOD_VEX_0F388C_PREFIX_2 */
12188     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12189   },
12190   {
12191     /* MOD_VEX_0F388E_PREFIX_2 */
12192     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12193   },
12194   {
12195     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12196     { Bad_Opcode },
12197     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12198   },
12199   {
12200     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12201     { Bad_Opcode },
12202     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12203   },
12204   {
12205     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12206     { Bad_Opcode },
12207     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12208   },
12209   {
12210     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12211     { Bad_Opcode },
12212     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12213   },
12214   {
12215     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12216     { Bad_Opcode },
12217     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12218   },
12219   {
12220     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12221     { Bad_Opcode },
12222     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12223   },
12224   {
12225     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12226     { Bad_Opcode },
12227     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12228   },
12229   {
12230     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12231     { Bad_Opcode },
12232     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12233   },
12234 #define NEED_MOD_TABLE
12235 #include "i386-dis-evex.h"
12236 #undef NEED_MOD_TABLE
12237 };
12238
12239 static const struct dis386 rm_table[][8] = {
12240   {
12241     /* RM_C6_REG_7 */
12242     { "xabort",         { Skip_MODRM, Ib }, 0 },
12243   },
12244   {
12245     /* RM_C7_REG_7 */
12246     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12247   },
12248   {
12249     /* RM_0F01_REG_0 */
12250     { Bad_Opcode },
12251     { "vmcall",         { Skip_MODRM }, 0 },
12252     { "vmlaunch",       { Skip_MODRM }, 0 },
12253     { "vmresume",       { Skip_MODRM }, 0 },
12254     { "vmxoff",         { Skip_MODRM }, 0 },
12255   },
12256   {
12257     /* RM_0F01_REG_1 */
12258     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12259     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12260     { "clac",           { Skip_MODRM }, 0 },
12261     { "stac",           { Skip_MODRM }, 0 },
12262     { Bad_Opcode },
12263     { Bad_Opcode },
12264     { Bad_Opcode },
12265     { "encls",          { Skip_MODRM }, 0 },
12266   },
12267   {
12268     /* RM_0F01_REG_2 */
12269     { "xgetbv",         { Skip_MODRM }, 0 },
12270     { "xsetbv",         { Skip_MODRM }, 0 },
12271     { Bad_Opcode },
12272     { Bad_Opcode },
12273     { "vmfunc",         { Skip_MODRM }, 0 },
12274     { "xend",           { Skip_MODRM }, 0 },
12275     { "xtest",          { Skip_MODRM }, 0 },
12276     { "enclu",          { Skip_MODRM }, 0 },
12277   },
12278   {
12279     /* RM_0F01_REG_3 */
12280     { "vmrun",          { Skip_MODRM }, 0 },
12281     { "vmmcall",        { Skip_MODRM }, 0 },
12282     { "vmload",         { Skip_MODRM }, 0 },
12283     { "vmsave",         { Skip_MODRM }, 0 },
12284     { "stgi",           { Skip_MODRM }, 0 },
12285     { "clgi",           { Skip_MODRM }, 0 },
12286     { "skinit",         { Skip_MODRM }, 0 },
12287     { "invlpga",        { Skip_MODRM }, 0 },
12288   },
12289   {
12290     /* RM_0F01_REG_5 */
12291     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12292     { Bad_Opcode },
12293     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12294     { Bad_Opcode },
12295     { Bad_Opcode },
12296     { Bad_Opcode },
12297     { "rdpkru",         { Skip_MODRM }, 0 },
12298     { "wrpkru",         { Skip_MODRM }, 0 },
12299   },
12300   {
12301     /* RM_0F01_REG_7 */
12302     { "swapgs",         { Skip_MODRM }, 0  },
12303     { "rdtscp",         { Skip_MODRM }, 0  },
12304     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12305     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12306     { "clzero",         { Skip_MODRM }, 0  },
12307   },
12308   {
12309     /* RM_0F1E_MOD_3_REG_7 */
12310     { "nopQ",           { Ev }, 0 },
12311     { "nopQ",           { Ev }, 0 },
12312     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
12313     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
12314     { "nopQ",           { Ev }, 0 },
12315     { "nopQ",           { Ev }, 0 },
12316     { "nopQ",           { Ev }, 0 },
12317     { "nopQ",           { Ev }, 0 },
12318   },
12319   {
12320     /* RM_0FAE_REG_6 */
12321     { "mfence",         { Skip_MODRM }, 0 },
12322   },
12323   {
12324     /* RM_0FAE_REG_7 */
12325     { "sfence",         { Skip_MODRM }, 0 },
12326
12327   },
12328 };
12329
12330 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12331
12332 /* We use the high bit to indicate different name for the same
12333    prefix.  */
12334 #define REP_PREFIX      (0xf3 | 0x100)
12335 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12336 #define XRELEASE_PREFIX (0xf3 | 0x400)
12337 #define BND_PREFIX      (0xf2 | 0x400)
12338 #define NOTRACK_PREFIX  (0x3e | 0x100)
12339
12340 static int
12341 ckprefix (void)
12342 {
12343   int newrex, i, length;
12344   rex = 0;
12345   rex_ignored = 0;
12346   prefixes = 0;
12347   used_prefixes = 0;
12348   rex_used = 0;
12349   last_lock_prefix = -1;
12350   last_repz_prefix = -1;
12351   last_repnz_prefix = -1;
12352   last_data_prefix = -1;
12353   last_addr_prefix = -1;
12354   last_rex_prefix = -1;
12355   last_seg_prefix = -1;
12356   fwait_prefix = -1;
12357   active_seg_prefix = 0;
12358   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12359     all_prefixes[i] = 0;
12360   i = 0;
12361   length = 0;
12362   /* The maximum instruction length is 15bytes.  */
12363   while (length < MAX_CODE_LENGTH - 1)
12364     {
12365       FETCH_DATA (the_info, codep + 1);
12366       newrex = 0;
12367       switch (*codep)
12368         {
12369         /* REX prefixes family.  */
12370         case 0x40:
12371         case 0x41:
12372         case 0x42:
12373         case 0x43:
12374         case 0x44:
12375         case 0x45:
12376         case 0x46:
12377         case 0x47:
12378         case 0x48:
12379         case 0x49:
12380         case 0x4a:
12381         case 0x4b:
12382         case 0x4c:
12383         case 0x4d:
12384         case 0x4e:
12385         case 0x4f:
12386           if (address_mode == mode_64bit)
12387             newrex = *codep;
12388           else
12389             return 1;
12390           last_rex_prefix = i;
12391           break;
12392         case 0xf3:
12393           prefixes |= PREFIX_REPZ;
12394           last_repz_prefix = i;
12395           break;
12396         case 0xf2:
12397           prefixes |= PREFIX_REPNZ;
12398           last_repnz_prefix = i;
12399           break;
12400         case 0xf0:
12401           prefixes |= PREFIX_LOCK;
12402           last_lock_prefix = i;
12403           break;
12404         case 0x2e:
12405           prefixes |= PREFIX_CS;
12406           last_seg_prefix = i;
12407           active_seg_prefix = PREFIX_CS;
12408           break;
12409         case 0x36:
12410           prefixes |= PREFIX_SS;
12411           last_seg_prefix = i;
12412           active_seg_prefix = PREFIX_SS;
12413           break;
12414         case 0x3e:
12415           prefixes |= PREFIX_DS;
12416           last_seg_prefix = i;
12417           active_seg_prefix = PREFIX_DS;
12418           break;
12419         case 0x26:
12420           prefixes |= PREFIX_ES;
12421           last_seg_prefix = i;
12422           active_seg_prefix = PREFIX_ES;
12423           break;
12424         case 0x64:
12425           prefixes |= PREFIX_FS;
12426           last_seg_prefix = i;
12427           active_seg_prefix = PREFIX_FS;
12428           break;
12429         case 0x65:
12430           prefixes |= PREFIX_GS;
12431           last_seg_prefix = i;
12432           active_seg_prefix = PREFIX_GS;
12433           break;
12434         case 0x66:
12435           prefixes |= PREFIX_DATA;
12436           last_data_prefix = i;
12437           break;
12438         case 0x67:
12439           prefixes |= PREFIX_ADDR;
12440           last_addr_prefix = i;
12441           break;
12442         case FWAIT_OPCODE:
12443           /* fwait is really an instruction.  If there are prefixes
12444              before the fwait, they belong to the fwait, *not* to the
12445              following instruction.  */
12446           fwait_prefix = i;
12447           if (prefixes || rex)
12448             {
12449               prefixes |= PREFIX_FWAIT;
12450               codep++;
12451               /* This ensures that the previous REX prefixes are noticed
12452                  as unused prefixes, as in the return case below.  */
12453               rex_used = rex;
12454               return 1;
12455             }
12456           prefixes = PREFIX_FWAIT;
12457           break;
12458         default:
12459           return 1;
12460         }
12461       /* Rex is ignored when followed by another prefix.  */
12462       if (rex)
12463         {
12464           rex_used = rex;
12465           return 1;
12466         }
12467       if (*codep != FWAIT_OPCODE)
12468         all_prefixes[i++] = *codep;
12469       rex = newrex;
12470       codep++;
12471       length++;
12472     }
12473   return 0;
12474 }
12475
12476 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12477    prefix byte.  */
12478
12479 static const char *
12480 prefix_name (int pref, int sizeflag)
12481 {
12482   static const char *rexes [16] =
12483     {
12484       "rex",            /* 0x40 */
12485       "rex.B",          /* 0x41 */
12486       "rex.X",          /* 0x42 */
12487       "rex.XB",         /* 0x43 */
12488       "rex.R",          /* 0x44 */
12489       "rex.RB",         /* 0x45 */
12490       "rex.RX",         /* 0x46 */
12491       "rex.RXB",        /* 0x47 */
12492       "rex.W",          /* 0x48 */
12493       "rex.WB",         /* 0x49 */
12494       "rex.WX",         /* 0x4a */
12495       "rex.WXB",        /* 0x4b */
12496       "rex.WR",         /* 0x4c */
12497       "rex.WRB",        /* 0x4d */
12498       "rex.WRX",        /* 0x4e */
12499       "rex.WRXB",       /* 0x4f */
12500     };
12501
12502   switch (pref)
12503     {
12504     /* REX prefixes family.  */
12505     case 0x40:
12506     case 0x41:
12507     case 0x42:
12508     case 0x43:
12509     case 0x44:
12510     case 0x45:
12511     case 0x46:
12512     case 0x47:
12513     case 0x48:
12514     case 0x49:
12515     case 0x4a:
12516     case 0x4b:
12517     case 0x4c:
12518     case 0x4d:
12519     case 0x4e:
12520     case 0x4f:
12521       return rexes [pref - 0x40];
12522     case 0xf3:
12523       return "repz";
12524     case 0xf2:
12525       return "repnz";
12526     case 0xf0:
12527       return "lock";
12528     case 0x2e:
12529       return "cs";
12530     case 0x36:
12531       return "ss";
12532     case 0x3e:
12533       return "ds";
12534     case 0x26:
12535       return "es";
12536     case 0x64:
12537       return "fs";
12538     case 0x65:
12539       return "gs";
12540     case 0x66:
12541       return (sizeflag & DFLAG) ? "data16" : "data32";
12542     case 0x67:
12543       if (address_mode == mode_64bit)
12544         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12545       else
12546         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12547     case FWAIT_OPCODE:
12548       return "fwait";
12549     case REP_PREFIX:
12550       return "rep";
12551     case XACQUIRE_PREFIX:
12552       return "xacquire";
12553     case XRELEASE_PREFIX:
12554       return "xrelease";
12555     case BND_PREFIX:
12556       return "bnd";
12557     case NOTRACK_PREFIX:
12558       return "notrack";
12559     default:
12560       return NULL;
12561     }
12562 }
12563
12564 static char op_out[MAX_OPERANDS][100];
12565 static int op_ad, op_index[MAX_OPERANDS];
12566 static int two_source_ops;
12567 static bfd_vma op_address[MAX_OPERANDS];
12568 static bfd_vma op_riprel[MAX_OPERANDS];
12569 static bfd_vma start_pc;
12570
12571 /*
12572  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12573  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12574  *   section of the "Virtual 8086 Mode" chapter.)
12575  * 'pc' should be the address of this instruction, it will
12576  *   be used to print the target address if this is a relative jump or call
12577  * The function returns the length of this instruction in bytes.
12578  */
12579
12580 static char intel_syntax;
12581 static char intel_mnemonic = !SYSV386_COMPAT;
12582 static char open_char;
12583 static char close_char;
12584 static char separator_char;
12585 static char scale_char;
12586
12587 enum x86_64_isa
12588 {
12589   amd64 = 0,
12590   intel64
12591 };
12592
12593 static enum x86_64_isa isa64;
12594
12595 /* Here for backwards compatibility.  When gdb stops using
12596    print_insn_i386_att and print_insn_i386_intel these functions can
12597    disappear, and print_insn_i386 be merged into print_insn.  */
12598 int
12599 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12600 {
12601   intel_syntax = 0;
12602
12603   return print_insn (pc, info);
12604 }
12605
12606 int
12607 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12608 {
12609   intel_syntax = 1;
12610
12611   return print_insn (pc, info);
12612 }
12613
12614 int
12615 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12616 {
12617   intel_syntax = -1;
12618
12619   return print_insn (pc, info);
12620 }
12621
12622 void
12623 print_i386_disassembler_options (FILE *stream)
12624 {
12625   fprintf (stream, _("\n\
12626 The following i386/x86-64 specific disassembler options are supported for use\n\
12627 with the -M switch (multiple options should be separated by commas):\n"));
12628
12629   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12630   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12631   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12632   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12633   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12634   fprintf (stream, _("  att-mnemonic\n"
12635                      "              Display instruction in AT&T mnemonic\n"));
12636   fprintf (stream, _("  intel-mnemonic\n"
12637                      "              Display instruction in Intel mnemonic\n"));
12638   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12639   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12640   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12641   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12642   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12643   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12644   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12645   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12646 }
12647
12648 /* Bad opcode.  */
12649 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12650
12651 /* Get a pointer to struct dis386 with a valid name.  */
12652
12653 static const struct dis386 *
12654 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12655 {
12656   int vindex, vex_table_index;
12657
12658   if (dp->name != NULL)
12659     return dp;
12660
12661   switch (dp->op[0].bytemode)
12662     {
12663     case USE_REG_TABLE:
12664       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12665       break;
12666
12667     case USE_MOD_TABLE:
12668       vindex = modrm.mod == 0x3 ? 1 : 0;
12669       dp = &mod_table[dp->op[1].bytemode][vindex];
12670       break;
12671
12672     case USE_RM_TABLE:
12673       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12674       break;
12675
12676     case USE_PREFIX_TABLE:
12677       if (need_vex)
12678         {
12679           /* The prefix in VEX is implicit.  */
12680           switch (vex.prefix)
12681             {
12682             case 0:
12683               vindex = 0;
12684               break;
12685             case REPE_PREFIX_OPCODE:
12686               vindex = 1;
12687               break;
12688             case DATA_PREFIX_OPCODE:
12689               vindex = 2;
12690               break;
12691             case REPNE_PREFIX_OPCODE:
12692               vindex = 3;
12693               break;
12694             default:
12695               abort ();
12696               break;
12697             }
12698         }
12699       else
12700         {
12701           int last_prefix = -1;
12702           int prefix = 0;
12703           vindex = 0;
12704           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12705              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12706              last one wins.  */
12707           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12708             {
12709               if (last_repz_prefix > last_repnz_prefix)
12710                 {
12711                   vindex = 1;
12712                   prefix = PREFIX_REPZ;
12713                   last_prefix = last_repz_prefix;
12714                 }
12715               else
12716                 {
12717                   vindex = 3;
12718                   prefix = PREFIX_REPNZ;
12719                   last_prefix = last_repnz_prefix;
12720                 }
12721
12722               /* Check if prefix should be ignored.  */
12723               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12724                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12725                    & prefix) != 0)
12726                 vindex = 0;
12727             }
12728
12729           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12730             {
12731               vindex = 2;
12732               prefix = PREFIX_DATA;
12733               last_prefix = last_data_prefix;
12734             }
12735
12736           if (vindex != 0)
12737             {
12738               used_prefixes |= prefix;
12739               all_prefixes[last_prefix] = 0;
12740             }
12741         }
12742       dp = &prefix_table[dp->op[1].bytemode][vindex];
12743       break;
12744
12745     case USE_X86_64_TABLE:
12746       vindex = address_mode == mode_64bit ? 1 : 0;
12747       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12748       break;
12749
12750     case USE_3BYTE_TABLE:
12751       FETCH_DATA (info, codep + 2);
12752       vindex = *codep++;
12753       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12754       end_codep = codep;
12755       modrm.mod = (*codep >> 6) & 3;
12756       modrm.reg = (*codep >> 3) & 7;
12757       modrm.rm = *codep & 7;
12758       break;
12759
12760     case USE_VEX_LEN_TABLE:
12761       if (!need_vex)
12762         abort ();
12763
12764       switch (vex.length)
12765         {
12766         case 128:
12767           vindex = 0;
12768           break;
12769         case 256:
12770           vindex = 1;
12771           break;
12772         default:
12773           abort ();
12774           break;
12775         }
12776
12777       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12778       break;
12779
12780     case USE_XOP_8F_TABLE:
12781       FETCH_DATA (info, codep + 3);
12782       /* All bits in the REX prefix are ignored.  */
12783       rex_ignored = rex;
12784       rex = ~(*codep >> 5) & 0x7;
12785
12786       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12787       switch ((*codep & 0x1f))
12788         {
12789         default:
12790           dp = &bad_opcode;
12791           return dp;
12792         case 0x8:
12793           vex_table_index = XOP_08;
12794           break;
12795         case 0x9:
12796           vex_table_index = XOP_09;
12797           break;
12798         case 0xa:
12799           vex_table_index = XOP_0A;
12800           break;
12801         }
12802       codep++;
12803       vex.w = *codep & 0x80;
12804       if (vex.w && address_mode == mode_64bit)
12805         rex |= REX_W;
12806
12807       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12808       if (address_mode != mode_64bit)
12809         {
12810           /* In 16/32-bit mode REX_B is silently ignored.  */
12811           rex &= ~REX_B;
12812           if (vex.register_specifier > 0x7)
12813             {
12814               dp = &bad_opcode;
12815               return dp;
12816             }
12817         }
12818
12819       vex.length = (*codep & 0x4) ? 256 : 128;
12820       switch ((*codep & 0x3))
12821         {
12822         case 0:
12823           vex.prefix = 0;
12824           break;
12825         case 1:
12826           vex.prefix = DATA_PREFIX_OPCODE;
12827           break;
12828         case 2:
12829           vex.prefix = REPE_PREFIX_OPCODE;
12830           break;
12831         case 3:
12832           vex.prefix = REPNE_PREFIX_OPCODE;
12833           break;
12834         }
12835       need_vex = 1;
12836       need_vex_reg = 1;
12837       codep++;
12838       vindex = *codep++;
12839       dp = &xop_table[vex_table_index][vindex];
12840
12841       end_codep = codep;
12842       FETCH_DATA (info, codep + 1);
12843       modrm.mod = (*codep >> 6) & 3;
12844       modrm.reg = (*codep >> 3) & 7;
12845       modrm.rm = *codep & 7;
12846       break;
12847
12848     case USE_VEX_C4_TABLE:
12849       /* VEX prefix.  */
12850       FETCH_DATA (info, codep + 3);
12851       /* All bits in the REX prefix are ignored.  */
12852       rex_ignored = rex;
12853       rex = ~(*codep >> 5) & 0x7;
12854       switch ((*codep & 0x1f))
12855         {
12856         default:
12857           dp = &bad_opcode;
12858           return dp;
12859         case 0x1:
12860           vex_table_index = VEX_0F;
12861           break;
12862         case 0x2:
12863           vex_table_index = VEX_0F38;
12864           break;
12865         case 0x3:
12866           vex_table_index = VEX_0F3A;
12867           break;
12868         }
12869       codep++;
12870       vex.w = *codep & 0x80;
12871       if (address_mode == mode_64bit)
12872         {
12873           if (vex.w)
12874             rex |= REX_W;
12875           vex.register_specifier = (~(*codep >> 3)) & 0xf;
12876         }
12877       else
12878         {
12879           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12880              is ignored, other REX bits are 0 and the highest bit in
12881              VEX.vvvv is also ignored.  */
12882           rex = 0;
12883           vex.register_specifier = (~(*codep >> 3)) & 0x7;
12884         }
12885       vex.length = (*codep & 0x4) ? 256 : 128;
12886       switch ((*codep & 0x3))
12887         {
12888         case 0:
12889           vex.prefix = 0;
12890           break;
12891         case 1:
12892           vex.prefix = DATA_PREFIX_OPCODE;
12893           break;
12894         case 2:
12895           vex.prefix = REPE_PREFIX_OPCODE;
12896           break;
12897         case 3:
12898           vex.prefix = REPNE_PREFIX_OPCODE;
12899           break;
12900         }
12901       need_vex = 1;
12902       need_vex_reg = 1;
12903       codep++;
12904       vindex = *codep++;
12905       dp = &vex_table[vex_table_index][vindex];
12906       end_codep = codep;
12907       /* There is no MODRM byte for VEX0F 77.  */
12908       if (vex_table_index != VEX_0F || vindex != 0x77)
12909         {
12910           FETCH_DATA (info, codep + 1);
12911           modrm.mod = (*codep >> 6) & 3;
12912           modrm.reg = (*codep >> 3) & 7;
12913           modrm.rm = *codep & 7;
12914         }
12915       break;
12916
12917     case USE_VEX_C5_TABLE:
12918       /* VEX prefix.  */
12919       FETCH_DATA (info, codep + 2);
12920       /* All bits in the REX prefix are ignored.  */
12921       rex_ignored = rex;
12922       rex = (*codep & 0x80) ? 0 : REX_R;
12923
12924       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12925          VEX.vvvv is 1.  */
12926       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12927       vex.w = 0;
12928       vex.length = (*codep & 0x4) ? 256 : 128;
12929       switch ((*codep & 0x3))
12930         {
12931         case 0:
12932           vex.prefix = 0;
12933           break;
12934         case 1:
12935           vex.prefix = DATA_PREFIX_OPCODE;
12936           break;
12937         case 2:
12938           vex.prefix = REPE_PREFIX_OPCODE;
12939           break;
12940         case 3:
12941           vex.prefix = REPNE_PREFIX_OPCODE;
12942           break;
12943         }
12944       need_vex = 1;
12945       need_vex_reg = 1;
12946       codep++;
12947       vindex = *codep++;
12948       dp = &vex_table[dp->op[1].bytemode][vindex];
12949       end_codep = codep;
12950       /* There is no MODRM byte for VEX 77.  */
12951       if (vindex != 0x77)
12952         {
12953           FETCH_DATA (info, codep + 1);
12954           modrm.mod = (*codep >> 6) & 3;
12955           modrm.reg = (*codep >> 3) & 7;
12956           modrm.rm = *codep & 7;
12957         }
12958       break;
12959
12960     case USE_VEX_W_TABLE:
12961       if (!need_vex)
12962         abort ();
12963
12964       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12965       break;
12966
12967     case USE_EVEX_TABLE:
12968       two_source_ops = 0;
12969       /* EVEX prefix.  */
12970       vex.evex = 1;
12971       FETCH_DATA (info, codep + 4);
12972       /* All bits in the REX prefix are ignored.  */
12973       rex_ignored = rex;
12974       /* The first byte after 0x62.  */
12975       rex = ~(*codep >> 5) & 0x7;
12976       vex.r = *codep & 0x10;
12977       switch ((*codep & 0xf))
12978         {
12979         default:
12980           return &bad_opcode;
12981         case 0x1:
12982           vex_table_index = EVEX_0F;
12983           break;
12984         case 0x2:
12985           vex_table_index = EVEX_0F38;
12986           break;
12987         case 0x3:
12988           vex_table_index = EVEX_0F3A;
12989           break;
12990         }
12991
12992       /* The second byte after 0x62.  */
12993       codep++;
12994       vex.w = *codep & 0x80;
12995       if (vex.w && address_mode == mode_64bit)
12996         rex |= REX_W;
12997
12998       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12999       if (address_mode != mode_64bit)
13000         {
13001           /* In 16/32-bit mode silently ignore following bits.  */
13002           rex &= ~REX_B;
13003           vex.r = 1;
13004           vex.v = 1;
13005           vex.register_specifier &= 0x7;
13006         }
13007
13008       /* The U bit.  */
13009       if (!(*codep & 0x4))
13010         return &bad_opcode;
13011
13012       switch ((*codep & 0x3))
13013         {
13014         case 0:
13015           vex.prefix = 0;
13016           break;
13017         case 1:
13018           vex.prefix = DATA_PREFIX_OPCODE;
13019           break;
13020         case 2:
13021           vex.prefix = REPE_PREFIX_OPCODE;
13022           break;
13023         case 3:
13024           vex.prefix = REPNE_PREFIX_OPCODE;
13025           break;
13026         }
13027
13028       /* The third byte after 0x62.  */
13029       codep++;
13030
13031       /* Remember the static rounding bits.  */
13032       vex.ll = (*codep >> 5) & 3;
13033       vex.b = (*codep & 0x10) != 0;
13034
13035       vex.v = *codep & 0x8;
13036       vex.mask_register_specifier = *codep & 0x7;
13037       vex.zeroing = *codep & 0x80;
13038
13039       need_vex = 1;
13040       need_vex_reg = 1;
13041       codep++;
13042       vindex = *codep++;
13043       dp = &evex_table[vex_table_index][vindex];
13044       end_codep = codep;
13045       FETCH_DATA (info, codep + 1);
13046       modrm.mod = (*codep >> 6) & 3;
13047       modrm.reg = (*codep >> 3) & 7;
13048       modrm.rm = *codep & 7;
13049
13050       /* Set vector length.  */
13051       if (modrm.mod == 3 && vex.b)
13052         vex.length = 512;
13053       else
13054         {
13055           switch (vex.ll)
13056             {
13057             case 0x0:
13058               vex.length = 128;
13059               break;
13060             case 0x1:
13061               vex.length = 256;
13062               break;
13063             case 0x2:
13064               vex.length = 512;
13065               break;
13066             default:
13067               return &bad_opcode;
13068             }
13069         }
13070       break;
13071
13072     case 0:
13073       dp = &bad_opcode;
13074       break;
13075
13076     default:
13077       abort ();
13078     }
13079
13080   if (dp->name != NULL)
13081     return dp;
13082   else
13083     return get_valid_dis386 (dp, info);
13084 }
13085
13086 static void
13087 get_sib (disassemble_info *info, int sizeflag)
13088 {
13089   /* If modrm.mod == 3, operand must be register.  */
13090   if (need_modrm
13091       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13092       && modrm.mod != 3
13093       && modrm.rm == 4)
13094     {
13095       FETCH_DATA (info, codep + 2);
13096       sib.index = (codep [1] >> 3) & 7;
13097       sib.scale = (codep [1] >> 6) & 3;
13098       sib.base = codep [1] & 7;
13099     }
13100 }
13101
13102 static int
13103 print_insn (bfd_vma pc, disassemble_info *info)
13104 {
13105   const struct dis386 *dp;
13106   int i;
13107   char *op_txt[MAX_OPERANDS];
13108   int needcomma;
13109   int sizeflag, orig_sizeflag;
13110   const char *p;
13111   struct dis_private priv;
13112   int prefix_length;
13113
13114   priv.orig_sizeflag = AFLAG | DFLAG;
13115   if ((info->mach & bfd_mach_i386_i386) != 0)
13116     address_mode = mode_32bit;
13117   else if (info->mach == bfd_mach_i386_i8086)
13118     {
13119       address_mode = mode_16bit;
13120       priv.orig_sizeflag = 0;
13121     }
13122   else
13123     address_mode = mode_64bit;
13124
13125   if (intel_syntax == (char) -1)
13126     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13127
13128   for (p = info->disassembler_options; p != NULL; )
13129     {
13130       if (CONST_STRNEQ (p, "amd64"))
13131         isa64 = amd64;
13132       else if (CONST_STRNEQ (p, "intel64"))
13133         isa64 = intel64;
13134       else if (CONST_STRNEQ (p, "x86-64"))
13135         {
13136           address_mode = mode_64bit;
13137           priv.orig_sizeflag = AFLAG | DFLAG;
13138         }
13139       else if (CONST_STRNEQ (p, "i386"))
13140         {
13141           address_mode = mode_32bit;
13142           priv.orig_sizeflag = AFLAG | DFLAG;
13143         }
13144       else if (CONST_STRNEQ (p, "i8086"))
13145         {
13146           address_mode = mode_16bit;
13147           priv.orig_sizeflag = 0;
13148         }
13149       else if (CONST_STRNEQ (p, "intel"))
13150         {
13151           intel_syntax = 1;
13152           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13153             intel_mnemonic = 1;
13154         }
13155       else if (CONST_STRNEQ (p, "att"))
13156         {
13157           intel_syntax = 0;
13158           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13159             intel_mnemonic = 0;
13160         }
13161       else if (CONST_STRNEQ (p, "addr"))
13162         {
13163           if (address_mode == mode_64bit)
13164             {
13165               if (p[4] == '3' && p[5] == '2')
13166                 priv.orig_sizeflag &= ~AFLAG;
13167               else if (p[4] == '6' && p[5] == '4')
13168                 priv.orig_sizeflag |= AFLAG;
13169             }
13170           else
13171             {
13172               if (p[4] == '1' && p[5] == '6')
13173                 priv.orig_sizeflag &= ~AFLAG;
13174               else if (p[4] == '3' && p[5] == '2')
13175                 priv.orig_sizeflag |= AFLAG;
13176             }
13177         }
13178       else if (CONST_STRNEQ (p, "data"))
13179         {
13180           if (p[4] == '1' && p[5] == '6')
13181             priv.orig_sizeflag &= ~DFLAG;
13182           else if (p[4] == '3' && p[5] == '2')
13183             priv.orig_sizeflag |= DFLAG;
13184         }
13185       else if (CONST_STRNEQ (p, "suffix"))
13186         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13187
13188       p = strchr (p, ',');
13189       if (p != NULL)
13190         p++;
13191     }
13192
13193   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13194     {
13195       (*info->fprintf_func) (info->stream,
13196                              _("64-bit address is disabled"));
13197       return -1;
13198     }
13199
13200   if (intel_syntax)
13201     {
13202       names64 = intel_names64;
13203       names32 = intel_names32;
13204       names16 = intel_names16;
13205       names8 = intel_names8;
13206       names8rex = intel_names8rex;
13207       names_seg = intel_names_seg;
13208       names_mm = intel_names_mm;
13209       names_bnd = intel_names_bnd;
13210       names_xmm = intel_names_xmm;
13211       names_ymm = intel_names_ymm;
13212       names_zmm = intel_names_zmm;
13213       index64 = intel_index64;
13214       index32 = intel_index32;
13215       names_mask = intel_names_mask;
13216       index16 = intel_index16;
13217       open_char = '[';
13218       close_char = ']';
13219       separator_char = '+';
13220       scale_char = '*';
13221     }
13222   else
13223     {
13224       names64 = att_names64;
13225       names32 = att_names32;
13226       names16 = att_names16;
13227       names8 = att_names8;
13228       names8rex = att_names8rex;
13229       names_seg = att_names_seg;
13230       names_mm = att_names_mm;
13231       names_bnd = att_names_bnd;
13232       names_xmm = att_names_xmm;
13233       names_ymm = att_names_ymm;
13234       names_zmm = att_names_zmm;
13235       index64 = att_index64;
13236       index32 = att_index32;
13237       names_mask = att_names_mask;
13238       index16 = att_index16;
13239       open_char = '(';
13240       close_char =  ')';
13241       separator_char = ',';
13242       scale_char = ',';
13243     }
13244
13245   /* The output looks better if we put 7 bytes on a line, since that
13246      puts most long word instructions on a single line.  Use 8 bytes
13247      for Intel L1OM.  */
13248   if ((info->mach & bfd_mach_l1om) != 0)
13249     info->bytes_per_line = 8;
13250   else
13251     info->bytes_per_line = 7;
13252
13253   info->private_data = &priv;
13254   priv.max_fetched = priv.the_buffer;
13255   priv.insn_start = pc;
13256
13257   obuf[0] = 0;
13258   for (i = 0; i < MAX_OPERANDS; ++i)
13259     {
13260       op_out[i][0] = 0;
13261       op_index[i] = -1;
13262     }
13263
13264   the_info = info;
13265   start_pc = pc;
13266   start_codep = priv.the_buffer;
13267   codep = priv.the_buffer;
13268
13269   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13270     {
13271       const char *name;
13272
13273       /* Getting here means we tried for data but didn't get it.  That
13274          means we have an incomplete instruction of some sort.  Just
13275          print the first byte as a prefix or a .byte pseudo-op.  */
13276       if (codep > priv.the_buffer)
13277         {
13278           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13279           if (name != NULL)
13280             (*info->fprintf_func) (info->stream, "%s", name);
13281           else
13282             {
13283               /* Just print the first byte as a .byte instruction.  */
13284               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13285                                      (unsigned int) priv.the_buffer[0]);
13286             }
13287
13288           return 1;
13289         }
13290
13291       return -1;
13292     }
13293
13294   obufp = obuf;
13295   sizeflag = priv.orig_sizeflag;
13296
13297   if (!ckprefix () || rex_used)
13298     {
13299       /* Too many prefixes or unused REX prefixes.  */
13300       for (i = 0;
13301            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13302            i++)
13303         (*info->fprintf_func) (info->stream, "%s%s",
13304                                i == 0 ? "" : " ",
13305                                prefix_name (all_prefixes[i], sizeflag));
13306       return i;
13307     }
13308
13309   insn_codep = codep;
13310
13311   FETCH_DATA (info, codep + 1);
13312   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13313
13314   if (((prefixes & PREFIX_FWAIT)
13315        && ((*codep < 0xd8) || (*codep > 0xdf))))
13316     {
13317       /* Handle prefixes before fwait.  */
13318       for (i = 0; i < fwait_prefix && all_prefixes[i];
13319            i++)
13320         (*info->fprintf_func) (info->stream, "%s ",
13321                                prefix_name (all_prefixes[i], sizeflag));
13322       (*info->fprintf_func) (info->stream, "fwait");
13323       return i + 1;
13324     }
13325
13326   if (*codep == 0x0f)
13327     {
13328       unsigned char threebyte;
13329
13330       codep++;
13331       FETCH_DATA (info, codep + 1);
13332       threebyte = *codep;
13333       dp = &dis386_twobyte[threebyte];
13334       need_modrm = twobyte_has_modrm[*codep];
13335       codep++;
13336     }
13337   else
13338     {
13339       dp = &dis386[*codep];
13340       need_modrm = onebyte_has_modrm[*codep];
13341       codep++;
13342     }
13343
13344   /* Save sizeflag for printing the extra prefixes later before updating
13345      it for mnemonic and operand processing.  The prefix names depend
13346      only on the address mode.  */
13347   orig_sizeflag = sizeflag;
13348   if (prefixes & PREFIX_ADDR)
13349     sizeflag ^= AFLAG;
13350   if ((prefixes & PREFIX_DATA))
13351     sizeflag ^= DFLAG;
13352
13353   end_codep = codep;
13354   if (need_modrm)
13355     {
13356       FETCH_DATA (info, codep + 1);
13357       modrm.mod = (*codep >> 6) & 3;
13358       modrm.reg = (*codep >> 3) & 7;
13359       modrm.rm = *codep & 7;
13360     }
13361
13362   need_vex = 0;
13363   need_vex_reg = 0;
13364   vex_w_done = 0;
13365   vex.evex = 0;
13366
13367   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13368     {
13369       get_sib (info, sizeflag);
13370       dofloat (sizeflag);
13371     }
13372   else
13373     {
13374       dp = get_valid_dis386 (dp, info);
13375       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13376         {
13377           get_sib (info, sizeflag);
13378           for (i = 0; i < MAX_OPERANDS; ++i)
13379             {
13380               obufp = op_out[i];
13381               op_ad = MAX_OPERANDS - 1 - i;
13382               if (dp->op[i].rtn)
13383                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13384               /* For EVEX instruction after the last operand masking
13385                  should be printed.  */
13386               if (i == 0 && vex.evex)
13387                 {
13388                   /* Don't print {%k0}.  */
13389                   if (vex.mask_register_specifier)
13390                     {
13391                       oappend ("{");
13392                       oappend (names_mask[vex.mask_register_specifier]);
13393                       oappend ("}");
13394                     }
13395                   if (vex.zeroing)
13396                     oappend ("{z}");
13397                 }
13398             }
13399         }
13400     }
13401
13402   /* Check if the REX prefix is used.  */
13403   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13404     all_prefixes[last_rex_prefix] = 0;
13405
13406   /* Check if the SEG prefix is used.  */
13407   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13408                    | PREFIX_FS | PREFIX_GS)) != 0
13409       && (used_prefixes & active_seg_prefix) != 0)
13410     all_prefixes[last_seg_prefix] = 0;
13411
13412   /* Check if the ADDR prefix is used.  */
13413   if ((prefixes & PREFIX_ADDR) != 0
13414       && (used_prefixes & PREFIX_ADDR) != 0)
13415     all_prefixes[last_addr_prefix] = 0;
13416
13417   /* Check if the DATA prefix is used.  */
13418   if ((prefixes & PREFIX_DATA) != 0
13419       && (used_prefixes & PREFIX_DATA) != 0)
13420     all_prefixes[last_data_prefix] = 0;
13421
13422   /* Print the extra prefixes.  */
13423   prefix_length = 0;
13424   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13425     if (all_prefixes[i])
13426       {
13427         const char *name;
13428         name = prefix_name (all_prefixes[i], orig_sizeflag);
13429         if (name == NULL)
13430           abort ();
13431         prefix_length += strlen (name) + 1;
13432         (*info->fprintf_func) (info->stream, "%s ", name);
13433       }
13434
13435   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13436      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13437      used by putop and MMX/SSE operand and may be overriden by the
13438      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13439      separately.  */
13440   if (dp->prefix_requirement == PREFIX_OPCODE
13441       && dp != &bad_opcode
13442       && (((prefixes
13443             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13444            && (used_prefixes
13445                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13446           || ((((prefixes
13447                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13448                 == PREFIX_DATA)
13449                && (used_prefixes & PREFIX_DATA) == 0))))
13450     {
13451       (*info->fprintf_func) (info->stream, "(bad)");
13452       return end_codep - priv.the_buffer;
13453     }
13454
13455   /* Check maximum code length.  */
13456   if ((codep - start_codep) > MAX_CODE_LENGTH)
13457     {
13458       (*info->fprintf_func) (info->stream, "(bad)");
13459       return MAX_CODE_LENGTH;
13460     }
13461
13462   obufp = mnemonicendp;
13463   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13464     oappend (" ");
13465   oappend (" ");
13466   (*info->fprintf_func) (info->stream, "%s", obuf);
13467
13468   /* The enter and bound instructions are printed with operands in the same
13469      order as the intel book; everything else is printed in reverse order.  */
13470   if (intel_syntax || two_source_ops)
13471     {
13472       bfd_vma riprel;
13473
13474       for (i = 0; i < MAX_OPERANDS; ++i)
13475         op_txt[i] = op_out[i];
13476
13477       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13478           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13479         {
13480           op_txt[2] = op_out[3];
13481           op_txt[3] = op_out[2];
13482         }
13483
13484       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13485         {
13486           op_ad = op_index[i];
13487           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13488           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13489           riprel = op_riprel[i];
13490           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13491           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13492         }
13493     }
13494   else
13495     {
13496       for (i = 0; i < MAX_OPERANDS; ++i)
13497         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13498     }
13499
13500   needcomma = 0;
13501   for (i = 0; i < MAX_OPERANDS; ++i)
13502     if (*op_txt[i])
13503       {
13504         if (needcomma)
13505           (*info->fprintf_func) (info->stream, ",");
13506         if (op_index[i] != -1 && !op_riprel[i])
13507           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13508         else
13509           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13510         needcomma = 1;
13511       }
13512
13513   for (i = 0; i < MAX_OPERANDS; i++)
13514     if (op_index[i] != -1 && op_riprel[i])
13515       {
13516         (*info->fprintf_func) (info->stream, "        # ");
13517         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13518                                                 + op_address[op_index[i]]), info);
13519         break;
13520       }
13521   return codep - priv.the_buffer;
13522 }
13523
13524 static const char *float_mem[] = {
13525   /* d8 */
13526   "fadd{s|}",
13527   "fmul{s|}",
13528   "fcom{s|}",
13529   "fcomp{s|}",
13530   "fsub{s|}",
13531   "fsubr{s|}",
13532   "fdiv{s|}",
13533   "fdivr{s|}",
13534   /* d9 */
13535   "fld{s|}",
13536   "(bad)",
13537   "fst{s|}",
13538   "fstp{s|}",
13539   "fldenvIC",
13540   "fldcw",
13541   "fNstenvIC",
13542   "fNstcw",
13543   /* da */
13544   "fiadd{l|}",
13545   "fimul{l|}",
13546   "ficom{l|}",
13547   "ficomp{l|}",
13548   "fisub{l|}",
13549   "fisubr{l|}",
13550   "fidiv{l|}",
13551   "fidivr{l|}",
13552   /* db */
13553   "fild{l|}",
13554   "fisttp{l|}",
13555   "fist{l|}",
13556   "fistp{l|}",
13557   "(bad)",
13558   "fld{t||t|}",
13559   "(bad)",
13560   "fstp{t||t|}",
13561   /* dc */
13562   "fadd{l|}",
13563   "fmul{l|}",
13564   "fcom{l|}",
13565   "fcomp{l|}",
13566   "fsub{l|}",
13567   "fsubr{l|}",
13568   "fdiv{l|}",
13569   "fdivr{l|}",
13570   /* dd */
13571   "fld{l|}",
13572   "fisttp{ll|}",
13573   "fst{l||}",
13574   "fstp{l|}",
13575   "frstorIC",
13576   "(bad)",
13577   "fNsaveIC",
13578   "fNstsw",
13579   /* de */
13580   "fiadd",
13581   "fimul",
13582   "ficom",
13583   "ficomp",
13584   "fisub",
13585   "fisubr",
13586   "fidiv",
13587   "fidivr",
13588   /* df */
13589   "fild",
13590   "fisttp",
13591   "fist",
13592   "fistp",
13593   "fbld",
13594   "fild{ll|}",
13595   "fbstp",
13596   "fistp{ll|}",
13597 };
13598
13599 static const unsigned char float_mem_mode[] = {
13600   /* d8 */
13601   d_mode,
13602   d_mode,
13603   d_mode,
13604   d_mode,
13605   d_mode,
13606   d_mode,
13607   d_mode,
13608   d_mode,
13609   /* d9 */
13610   d_mode,
13611   0,
13612   d_mode,
13613   d_mode,
13614   0,
13615   w_mode,
13616   0,
13617   w_mode,
13618   /* da */
13619   d_mode,
13620   d_mode,
13621   d_mode,
13622   d_mode,
13623   d_mode,
13624   d_mode,
13625   d_mode,
13626   d_mode,
13627   /* db */
13628   d_mode,
13629   d_mode,
13630   d_mode,
13631   d_mode,
13632   0,
13633   t_mode,
13634   0,
13635   t_mode,
13636   /* dc */
13637   q_mode,
13638   q_mode,
13639   q_mode,
13640   q_mode,
13641   q_mode,
13642   q_mode,
13643   q_mode,
13644   q_mode,
13645   /* dd */
13646   q_mode,
13647   q_mode,
13648   q_mode,
13649   q_mode,
13650   0,
13651   0,
13652   0,
13653   w_mode,
13654   /* de */
13655   w_mode,
13656   w_mode,
13657   w_mode,
13658   w_mode,
13659   w_mode,
13660   w_mode,
13661   w_mode,
13662   w_mode,
13663   /* df */
13664   w_mode,
13665   w_mode,
13666   w_mode,
13667   w_mode,
13668   t_mode,
13669   q_mode,
13670   t_mode,
13671   q_mode
13672 };
13673
13674 #define ST { OP_ST, 0 }
13675 #define STi { OP_STi, 0 }
13676
13677 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13678 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13679 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13680 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13681 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13682 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13683 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13684 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13685 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13686
13687 static const struct dis386 float_reg[][8] = {
13688   /* d8 */
13689   {
13690     { "fadd",   { ST, STi }, 0 },
13691     { "fmul",   { ST, STi }, 0 },
13692     { "fcom",   { STi }, 0 },
13693     { "fcomp",  { STi }, 0 },
13694     { "fsub",   { ST, STi }, 0 },
13695     { "fsubr",  { ST, STi }, 0 },
13696     { "fdiv",   { ST, STi }, 0 },
13697     { "fdivr",  { ST, STi }, 0 },
13698   },
13699   /* d9 */
13700   {
13701     { "fld",    { STi }, 0 },
13702     { "fxch",   { STi }, 0 },
13703     { FGRPd9_2 },
13704     { Bad_Opcode },
13705     { FGRPd9_4 },
13706     { FGRPd9_5 },
13707     { FGRPd9_6 },
13708     { FGRPd9_7 },
13709   },
13710   /* da */
13711   {
13712     { "fcmovb", { ST, STi }, 0 },
13713     { "fcmove", { ST, STi }, 0 },
13714     { "fcmovbe",{ ST, STi }, 0 },
13715     { "fcmovu", { ST, STi }, 0 },
13716     { Bad_Opcode },
13717     { FGRPda_5 },
13718     { Bad_Opcode },
13719     { Bad_Opcode },
13720   },
13721   /* db */
13722   {
13723     { "fcmovnb",{ ST, STi }, 0 },
13724     { "fcmovne",{ ST, STi }, 0 },
13725     { "fcmovnbe",{ ST, STi }, 0 },
13726     { "fcmovnu",{ ST, STi }, 0 },
13727     { FGRPdb_4 },
13728     { "fucomi", { ST, STi }, 0 },
13729     { "fcomi",  { ST, STi }, 0 },
13730     { Bad_Opcode },
13731   },
13732   /* dc */
13733   {
13734     { "fadd",   { STi, ST }, 0 },
13735     { "fmul",   { STi, ST }, 0 },
13736     { Bad_Opcode },
13737     { Bad_Opcode },
13738     { "fsub!M", { STi, ST }, 0 },
13739     { "fsubM",  { STi, ST }, 0 },
13740     { "fdiv!M", { STi, ST }, 0 },
13741     { "fdivM",  { STi, ST }, 0 },
13742   },
13743   /* dd */
13744   {
13745     { "ffree",  { STi }, 0 },
13746     { Bad_Opcode },
13747     { "fst",    { STi }, 0 },
13748     { "fstp",   { STi }, 0 },
13749     { "fucom",  { STi }, 0 },
13750     { "fucomp", { STi }, 0 },
13751     { Bad_Opcode },
13752     { Bad_Opcode },
13753   },
13754   /* de */
13755   {
13756     { "faddp",  { STi, ST }, 0 },
13757     { "fmulp",  { STi, ST }, 0 },
13758     { Bad_Opcode },
13759     { FGRPde_3 },
13760     { "fsub!Mp", { STi, ST }, 0 },
13761     { "fsubMp", { STi, ST }, 0 },
13762     { "fdiv!Mp", { STi, ST }, 0 },
13763     { "fdivMp", { STi, ST }, 0 },
13764   },
13765   /* df */
13766   {
13767     { "ffreep", { STi }, 0 },
13768     { Bad_Opcode },
13769     { Bad_Opcode },
13770     { Bad_Opcode },
13771     { FGRPdf_4 },
13772     { "fucomip", { ST, STi }, 0 },
13773     { "fcomip", { ST, STi }, 0 },
13774     { Bad_Opcode },
13775   },
13776 };
13777
13778 static char *fgrps[][8] = {
13779   /* Bad opcode 0 */
13780   {
13781     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13782   },
13783
13784   /* d9_2  1 */
13785   {
13786     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13787   },
13788
13789   /* d9_4  2 */
13790   {
13791     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13792   },
13793
13794   /* d9_5  3 */
13795   {
13796     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13797   },
13798
13799   /* d9_6  4 */
13800   {
13801     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13802   },
13803
13804   /* d9_7  5 */
13805   {
13806     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13807   },
13808
13809   /* da_5  6 */
13810   {
13811     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13812   },
13813
13814   /* db_4  7 */
13815   {
13816     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13817     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13818   },
13819
13820   /* de_3  8 */
13821   {
13822     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13823   },
13824
13825   /* df_4  9 */
13826   {
13827     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13828   },
13829 };
13830
13831 static void
13832 swap_operand (void)
13833 {
13834   mnemonicendp[0] = '.';
13835   mnemonicendp[1] = 's';
13836   mnemonicendp += 2;
13837 }
13838
13839 static void
13840 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13841                int sizeflag ATTRIBUTE_UNUSED)
13842 {
13843   /* Skip mod/rm byte.  */
13844   MODRM_CHECK;
13845   codep++;
13846 }
13847
13848 static void
13849 dofloat (int sizeflag)
13850 {
13851   const struct dis386 *dp;
13852   unsigned char floatop;
13853
13854   floatop = codep[-1];
13855
13856   if (modrm.mod != 3)
13857     {
13858       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13859
13860       putop (float_mem[fp_indx], sizeflag);
13861       obufp = op_out[0];
13862       op_ad = 2;
13863       OP_E (float_mem_mode[fp_indx], sizeflag);
13864       return;
13865     }
13866   /* Skip mod/rm byte.  */
13867   MODRM_CHECK;
13868   codep++;
13869
13870   dp = &float_reg[floatop - 0xd8][modrm.reg];
13871   if (dp->name == NULL)
13872     {
13873       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13874
13875       /* Instruction fnstsw is only one with strange arg.  */
13876       if (floatop == 0xdf && codep[-1] == 0xe0)
13877         strcpy (op_out[0], names16[0]);
13878     }
13879   else
13880     {
13881       putop (dp->name, sizeflag);
13882
13883       obufp = op_out[0];
13884       op_ad = 2;
13885       if (dp->op[0].rtn)
13886         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13887
13888       obufp = op_out[1];
13889       op_ad = 1;
13890       if (dp->op[1].rtn)
13891         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13892     }
13893 }
13894
13895 /* Like oappend (below), but S is a string starting with '%'.
13896    In Intel syntax, the '%' is elided.  */
13897 static void
13898 oappend_maybe_intel (const char *s)
13899 {
13900   oappend (s + intel_syntax);
13901 }
13902
13903 static void
13904 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13905 {
13906   oappend_maybe_intel ("%st");
13907 }
13908
13909 static void
13910 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13911 {
13912   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13913   oappend_maybe_intel (scratchbuf);
13914 }
13915
13916 /* Capital letters in template are macros.  */
13917 static int
13918 putop (const char *in_template, int sizeflag)
13919 {
13920   const char *p;
13921   int alt = 0;
13922   int cond = 1;
13923   unsigned int l = 0, len = 1;
13924   char last[4];
13925
13926 #define SAVE_LAST(c)                    \
13927   if (l < len && l < sizeof (last))     \
13928     last[l++] = c;                      \
13929   else                                  \
13930     abort ();
13931
13932   for (p = in_template; *p; p++)
13933     {
13934       switch (*p)
13935         {
13936         default:
13937           *obufp++ = *p;
13938           break;
13939         case '%':
13940           len++;
13941           break;
13942         case '!':
13943           cond = 0;
13944           break;
13945         case '{':
13946           if (intel_syntax)
13947             {
13948               while (*++p != '|')
13949                 if (*p == '}' || *p == '\0')
13950                   abort ();
13951             }
13952           /* Fall through.  */
13953         case 'I':
13954           alt = 1;
13955           continue;
13956         case '|':
13957           while (*++p != '}')
13958             {
13959               if (*p == '\0')
13960                 abort ();
13961             }
13962           break;
13963         case '}':
13964           break;
13965         case 'A':
13966           if (intel_syntax)
13967             break;
13968           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13969             *obufp++ = 'b';
13970           break;
13971         case 'B':
13972           if (l == 0 && len == 1)
13973             {
13974 case_B:
13975               if (intel_syntax)
13976                 break;
13977               if (sizeflag & SUFFIX_ALWAYS)
13978                 *obufp++ = 'b';
13979             }
13980           else
13981             {
13982               if (l != 1
13983                   || len != 2
13984                   || last[0] != 'L')
13985                 {
13986                   SAVE_LAST (*p);
13987                   break;
13988                 }
13989
13990               if (address_mode == mode_64bit
13991                   && !(prefixes & PREFIX_ADDR))
13992                 {
13993                   *obufp++ = 'a';
13994                   *obufp++ = 'b';
13995                   *obufp++ = 's';
13996                 }
13997
13998               goto case_B;
13999             }
14000           break;
14001         case 'C':
14002           if (intel_syntax && !alt)
14003             break;
14004           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14005             {
14006               if (sizeflag & DFLAG)
14007                 *obufp++ = intel_syntax ? 'd' : 'l';
14008               else
14009                 *obufp++ = intel_syntax ? 'w' : 's';
14010               used_prefixes |= (prefixes & PREFIX_DATA);
14011             }
14012           break;
14013         case 'D':
14014           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14015             break;
14016           USED_REX (REX_W);
14017           if (modrm.mod == 3)
14018             {
14019               if (rex & REX_W)
14020                 *obufp++ = 'q';
14021               else
14022                 {
14023                   if (sizeflag & DFLAG)
14024                     *obufp++ = intel_syntax ? 'd' : 'l';
14025                   else
14026                     *obufp++ = 'w';
14027                   used_prefixes |= (prefixes & PREFIX_DATA);
14028                 }
14029             }
14030           else
14031             *obufp++ = 'w';
14032           break;
14033         case 'E':               /* For jcxz/jecxz */
14034           if (address_mode == mode_64bit)
14035             {
14036               if (sizeflag & AFLAG)
14037                 *obufp++ = 'r';
14038               else
14039                 *obufp++ = 'e';
14040             }
14041           else
14042             if (sizeflag & AFLAG)
14043               *obufp++ = 'e';
14044           used_prefixes |= (prefixes & PREFIX_ADDR);
14045           break;
14046         case 'F':
14047           if (intel_syntax)
14048             break;
14049           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14050             {
14051               if (sizeflag & AFLAG)
14052                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14053               else
14054                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14055               used_prefixes |= (prefixes & PREFIX_ADDR);
14056             }
14057           break;
14058         case 'G':
14059           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14060             break;
14061           if ((rex & REX_W) || (sizeflag & DFLAG))
14062             *obufp++ = 'l';
14063           else
14064             *obufp++ = 'w';
14065           if (!(rex & REX_W))
14066             used_prefixes |= (prefixes & PREFIX_DATA);
14067           break;
14068         case 'H':
14069           if (intel_syntax)
14070             break;
14071           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14072               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14073             {
14074               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14075               *obufp++ = ',';
14076               *obufp++ = 'p';
14077               if (prefixes & PREFIX_DS)
14078                 *obufp++ = 't';
14079               else
14080                 *obufp++ = 'n';
14081             }
14082           break;
14083         case 'J':
14084           if (intel_syntax)
14085             break;
14086           *obufp++ = 'l';
14087           break;
14088         case 'K':
14089           USED_REX (REX_W);
14090           if (rex & REX_W)
14091             *obufp++ = 'q';
14092           else
14093             *obufp++ = 'd';
14094           break;
14095         case 'Z':
14096           if (l != 0 || len != 1)
14097             {
14098               if (l != 1 || len != 2 || last[0] != 'X')
14099                 {
14100                   SAVE_LAST (*p);
14101                   break;
14102                 }
14103               if (!need_vex || !vex.evex)
14104                 abort ();
14105               if (intel_syntax
14106                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14107                 break;
14108               switch (vex.length)
14109                 {
14110                 case 128:
14111                   *obufp++ = 'x';
14112                   break;
14113                 case 256:
14114                   *obufp++ = 'y';
14115                   break;
14116                 case 512:
14117                   *obufp++ = 'z';
14118                   break;
14119                 default:
14120                   abort ();
14121                 }
14122               break;
14123             }
14124           if (intel_syntax)
14125             break;
14126           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14127             {
14128               *obufp++ = 'q';
14129               break;
14130             }
14131           /* Fall through.  */
14132           goto case_L;
14133         case 'L':
14134           if (l != 0 || len != 1)
14135             {
14136               SAVE_LAST (*p);
14137               break;
14138             }
14139 case_L:
14140           if (intel_syntax)
14141             break;
14142           if (sizeflag & SUFFIX_ALWAYS)
14143             *obufp++ = 'l';
14144           break;
14145         case 'M':
14146           if (intel_mnemonic != cond)
14147             *obufp++ = 'r';
14148           break;
14149         case 'N':
14150           if ((prefixes & PREFIX_FWAIT) == 0)
14151             *obufp++ = 'n';
14152           else
14153             used_prefixes |= PREFIX_FWAIT;
14154           break;
14155         case 'O':
14156           USED_REX (REX_W);
14157           if (rex & REX_W)
14158             *obufp++ = 'o';
14159           else if (intel_syntax && (sizeflag & DFLAG))
14160             *obufp++ = 'q';
14161           else
14162             *obufp++ = 'd';
14163           if (!(rex & REX_W))
14164             used_prefixes |= (prefixes & PREFIX_DATA);
14165           break;
14166         case '&':
14167           if (!intel_syntax
14168               && address_mode == mode_64bit
14169               && isa64 == intel64)
14170             {
14171               *obufp++ = 'q';
14172               break;
14173             }
14174           /* Fall through.  */
14175         case 'T':
14176           if (!intel_syntax
14177               && address_mode == mode_64bit
14178               && ((sizeflag & DFLAG) || (rex & REX_W)))
14179             {
14180               *obufp++ = 'q';
14181               break;
14182             }
14183           /* Fall through.  */
14184           goto case_P;
14185         case 'P':
14186           if (l == 0 && len == 1)
14187             {
14188 case_P:
14189               if (intel_syntax)
14190                 {
14191                   if ((rex & REX_W) == 0
14192                       && (prefixes & PREFIX_DATA))
14193                     {
14194                       if ((sizeflag & DFLAG) == 0)
14195                         *obufp++ = 'w';
14196                       used_prefixes |= (prefixes & PREFIX_DATA);
14197                     }
14198                   break;
14199                 }
14200               if ((prefixes & PREFIX_DATA)
14201                   || (rex & REX_W)
14202                   || (sizeflag & SUFFIX_ALWAYS))
14203                 {
14204                   USED_REX (REX_W);
14205                   if (rex & REX_W)
14206                     *obufp++ = 'q';
14207                   else
14208                     {
14209                       if (sizeflag & DFLAG)
14210                         *obufp++ = 'l';
14211                       else
14212                         *obufp++ = 'w';
14213                       used_prefixes |= (prefixes & PREFIX_DATA);
14214                     }
14215                 }
14216             }
14217           else
14218             {
14219               if (l != 1 || len != 2 || last[0] != 'L')
14220                 {
14221                   SAVE_LAST (*p);
14222                   break;
14223                 }
14224
14225               if ((prefixes & PREFIX_DATA)
14226                   || (rex & REX_W)
14227                   || (sizeflag & SUFFIX_ALWAYS))
14228                 {
14229                   USED_REX (REX_W);
14230                   if (rex & REX_W)
14231                     *obufp++ = 'q';
14232                   else
14233                     {
14234                       if (sizeflag & DFLAG)
14235                         *obufp++ = intel_syntax ? 'd' : 'l';
14236                       else
14237                         *obufp++ = 'w';
14238                       used_prefixes |= (prefixes & PREFIX_DATA);
14239                     }
14240                 }
14241             }
14242           break;
14243         case 'U':
14244           if (intel_syntax)
14245             break;
14246           if (address_mode == mode_64bit
14247               && ((sizeflag & DFLAG) || (rex & REX_W)))
14248             {
14249               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14250                 *obufp++ = 'q';
14251               break;
14252             }
14253           /* Fall through.  */
14254           goto case_Q;
14255         case 'Q':
14256           if (l == 0 && len == 1)
14257             {
14258 case_Q:
14259               if (intel_syntax && !alt)
14260                 break;
14261               USED_REX (REX_W);
14262               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14263                 {
14264                   if (rex & REX_W)
14265                     *obufp++ = 'q';
14266                   else
14267                     {
14268                       if (sizeflag & DFLAG)
14269                         *obufp++ = intel_syntax ? 'd' : 'l';
14270                       else
14271                         *obufp++ = 'w';
14272                       used_prefixes |= (prefixes & PREFIX_DATA);
14273                     }
14274                 }
14275             }
14276           else
14277             {
14278               if (l != 1 || len != 2 || last[0] != 'L')
14279                 {
14280                   SAVE_LAST (*p);
14281                   break;
14282                 }
14283               if (intel_syntax
14284                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14285                 break;
14286               if ((rex & REX_W))
14287                 {
14288                   USED_REX (REX_W);
14289                   *obufp++ = 'q';
14290                 }
14291               else
14292                 *obufp++ = 'l';
14293             }
14294           break;
14295         case 'R':
14296           USED_REX (REX_W);
14297           if (rex & REX_W)
14298             *obufp++ = 'q';
14299           else if (sizeflag & DFLAG)
14300             {
14301               if (intel_syntax)
14302                   *obufp++ = 'd';
14303               else
14304                   *obufp++ = 'l';
14305             }
14306           else
14307             *obufp++ = 'w';
14308           if (intel_syntax && !p[1]
14309               && ((rex & REX_W) || (sizeflag & DFLAG)))
14310             *obufp++ = 'e';
14311           if (!(rex & REX_W))
14312             used_prefixes |= (prefixes & PREFIX_DATA);
14313           break;
14314         case 'V':
14315           if (l == 0 && len == 1)
14316             {
14317               if (intel_syntax)
14318                 break;
14319               if (address_mode == mode_64bit
14320                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14321                 {
14322                   if (sizeflag & SUFFIX_ALWAYS)
14323                     *obufp++ = 'q';
14324                   break;
14325                 }
14326             }
14327           else
14328             {
14329               if (l != 1
14330                   || len != 2
14331                   || last[0] != 'L')
14332                 {
14333                   SAVE_LAST (*p);
14334                   break;
14335                 }
14336
14337               if (rex & REX_W)
14338                 {
14339                   *obufp++ = 'a';
14340                   *obufp++ = 'b';
14341                   *obufp++ = 's';
14342                 }
14343             }
14344           /* Fall through.  */
14345           goto case_S;
14346         case 'S':
14347           if (l == 0 && len == 1)
14348             {
14349 case_S:
14350               if (intel_syntax)
14351                 break;
14352               if (sizeflag & SUFFIX_ALWAYS)
14353                 {
14354                   if (rex & REX_W)
14355                     *obufp++ = 'q';
14356                   else
14357                     {
14358                       if (sizeflag & DFLAG)
14359                         *obufp++ = 'l';
14360                       else
14361                         *obufp++ = 'w';
14362                       used_prefixes |= (prefixes & PREFIX_DATA);
14363                     }
14364                 }
14365             }
14366           else
14367             {
14368               if (l != 1
14369                   || len != 2
14370                   || last[0] != 'L')
14371                 {
14372                   SAVE_LAST (*p);
14373                   break;
14374                 }
14375
14376               if (address_mode == mode_64bit
14377                   && !(prefixes & PREFIX_ADDR))
14378                 {
14379                   *obufp++ = 'a';
14380                   *obufp++ = 'b';
14381                   *obufp++ = 's';
14382                 }
14383
14384               goto case_S;
14385             }
14386           break;
14387         case 'X':
14388           if (l != 0 || len != 1)
14389             {
14390               SAVE_LAST (*p);
14391               break;
14392             }
14393           if (need_vex && vex.prefix)
14394             {
14395               if (vex.prefix == DATA_PREFIX_OPCODE)
14396                 *obufp++ = 'd';
14397               else
14398                 *obufp++ = 's';
14399             }
14400           else
14401             {
14402               if (prefixes & PREFIX_DATA)
14403                 *obufp++ = 'd';
14404               else
14405                 *obufp++ = 's';
14406               used_prefixes |= (prefixes & PREFIX_DATA);
14407             }
14408           break;
14409         case 'Y':
14410           if (l == 0 && len == 1)
14411             {
14412               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14413                 break;
14414               if (rex & REX_W)
14415                 {
14416                   USED_REX (REX_W);
14417                   *obufp++ = 'q';
14418                 }
14419               break;
14420             }
14421           else
14422             {
14423               if (l != 1 || len != 2 || last[0] != 'X')
14424                 {
14425                   SAVE_LAST (*p);
14426                   break;
14427                 }
14428               if (!need_vex)
14429                 abort ();
14430               if (intel_syntax
14431                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14432                 break;
14433               switch (vex.length)
14434                 {
14435                 case 128:
14436                   *obufp++ = 'x';
14437                   break;
14438                 case 256:
14439                   *obufp++ = 'y';
14440                   break;
14441                 case 512:
14442                   if (!vex.evex)
14443                 default:
14444                     abort ();
14445                 }
14446             }
14447           break;
14448         case 'W':
14449           if (l == 0 && len == 1)
14450             {
14451               /* operand size flag for cwtl, cbtw */
14452               USED_REX (REX_W);
14453               if (rex & REX_W)
14454                 {
14455                   if (intel_syntax)
14456                     *obufp++ = 'd';
14457                   else
14458                     *obufp++ = 'l';
14459                 }
14460               else if (sizeflag & DFLAG)
14461                 *obufp++ = 'w';
14462               else
14463                 *obufp++ = 'b';
14464               if (!(rex & REX_W))
14465                 used_prefixes |= (prefixes & PREFIX_DATA);
14466             }
14467           else
14468             {
14469               if (l != 1
14470                   || len != 2
14471                   || (last[0] != 'X'
14472                       && last[0] != 'L'))
14473                 {
14474                   SAVE_LAST (*p);
14475                   break;
14476                 }
14477               if (!need_vex)
14478                 abort ();
14479               if (last[0] == 'X')
14480                 *obufp++ = vex.w ? 'd': 's';
14481               else
14482                 *obufp++ = vex.w ? 'q': 'd';
14483             }
14484           break;
14485         case '^':
14486           if (intel_syntax)
14487             break;
14488           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14489             {
14490               if (sizeflag & DFLAG)
14491                 *obufp++ = 'l';
14492               else
14493                 *obufp++ = 'w';
14494               used_prefixes |= (prefixes & PREFIX_DATA);
14495             }
14496           break;
14497         case '@':
14498           if (intel_syntax)
14499             break;
14500           if (address_mode == mode_64bit
14501               && (isa64 == intel64
14502                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14503               *obufp++ = 'q';
14504           else if ((prefixes & PREFIX_DATA))
14505             {
14506               if (!(sizeflag & DFLAG))
14507                 *obufp++ = 'w';
14508               used_prefixes |= (prefixes & PREFIX_DATA);
14509             }
14510           break;
14511         }
14512       alt = 0;
14513     }
14514   *obufp = 0;
14515   mnemonicendp = obufp;
14516   return 0;
14517 }
14518
14519 static void
14520 oappend (const char *s)
14521 {
14522   obufp = stpcpy (obufp, s);
14523 }
14524
14525 static void
14526 append_seg (void)
14527 {
14528   /* Only print the active segment register.  */
14529   if (!active_seg_prefix)
14530     return;
14531
14532   used_prefixes |= active_seg_prefix;
14533   switch (active_seg_prefix)
14534     {
14535     case PREFIX_CS:
14536       oappend_maybe_intel ("%cs:");
14537       break;
14538     case PREFIX_DS:
14539       oappend_maybe_intel ("%ds:");
14540       break;
14541     case PREFIX_SS:
14542       oappend_maybe_intel ("%ss:");
14543       break;
14544     case PREFIX_ES:
14545       oappend_maybe_intel ("%es:");
14546       break;
14547     case PREFIX_FS:
14548       oappend_maybe_intel ("%fs:");
14549       break;
14550     case PREFIX_GS:
14551       oappend_maybe_intel ("%gs:");
14552       break;
14553     default:
14554       break;
14555     }
14556 }
14557
14558 static void
14559 OP_indirE (int bytemode, int sizeflag)
14560 {
14561   if (!intel_syntax)
14562     oappend ("*");
14563   OP_E (bytemode, sizeflag);
14564 }
14565
14566 static void
14567 print_operand_value (char *buf, int hex, bfd_vma disp)
14568 {
14569   if (address_mode == mode_64bit)
14570     {
14571       if (hex)
14572         {
14573           char tmp[30];
14574           int i;
14575           buf[0] = '0';
14576           buf[1] = 'x';
14577           sprintf_vma (tmp, disp);
14578           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14579           strcpy (buf + 2, tmp + i);
14580         }
14581       else
14582         {
14583           bfd_signed_vma v = disp;
14584           char tmp[30];
14585           int i;
14586           if (v < 0)
14587             {
14588               *(buf++) = '-';
14589               v = -disp;
14590               /* Check for possible overflow on 0x8000000000000000.  */
14591               if (v < 0)
14592                 {
14593                   strcpy (buf, "9223372036854775808");
14594                   return;
14595                 }
14596             }
14597           if (!v)
14598             {
14599               strcpy (buf, "0");
14600               return;
14601             }
14602
14603           i = 0;
14604           tmp[29] = 0;
14605           while (v)
14606             {
14607               tmp[28 - i] = (v % 10) + '0';
14608               v /= 10;
14609               i++;
14610             }
14611           strcpy (buf, tmp + 29 - i);
14612         }
14613     }
14614   else
14615     {
14616       if (hex)
14617         sprintf (buf, "0x%x", (unsigned int) disp);
14618       else
14619         sprintf (buf, "%d", (int) disp);
14620     }
14621 }
14622
14623 /* Put DISP in BUF as signed hex number.  */
14624
14625 static void
14626 print_displacement (char *buf, bfd_vma disp)
14627 {
14628   bfd_signed_vma val = disp;
14629   char tmp[30];
14630   int i, j = 0;
14631
14632   if (val < 0)
14633     {
14634       buf[j++] = '-';
14635       val = -disp;
14636
14637       /* Check for possible overflow.  */
14638       if (val < 0)
14639         {
14640           switch (address_mode)
14641             {
14642             case mode_64bit:
14643               strcpy (buf + j, "0x8000000000000000");
14644               break;
14645             case mode_32bit:
14646               strcpy (buf + j, "0x80000000");
14647               break;
14648             case mode_16bit:
14649               strcpy (buf + j, "0x8000");
14650               break;
14651             }
14652           return;
14653         }
14654     }
14655
14656   buf[j++] = '0';
14657   buf[j++] = 'x';
14658
14659   sprintf_vma (tmp, (bfd_vma) val);
14660   for (i = 0; tmp[i] == '0'; i++)
14661     continue;
14662   if (tmp[i] == '\0')
14663     i--;
14664   strcpy (buf + j, tmp + i);
14665 }
14666
14667 static void
14668 intel_operand_size (int bytemode, int sizeflag)
14669 {
14670   if (vex.evex
14671       && vex.b
14672       && (bytemode == x_mode
14673           || bytemode == evex_half_bcst_xmmq_mode))
14674     {
14675       if (vex.w)
14676         oappend ("QWORD PTR ");
14677       else
14678         oappend ("DWORD PTR ");
14679       return;
14680     }
14681   switch (bytemode)
14682     {
14683     case b_mode:
14684     case b_swap_mode:
14685     case dqb_mode:
14686     case db_mode:
14687       oappend ("BYTE PTR ");
14688       break;
14689     case w_mode:
14690     case dw_mode:
14691     case dqw_mode:
14692       oappend ("WORD PTR ");
14693       break;
14694     case indir_v_mode:
14695       if (address_mode == mode_64bit && isa64 == intel64)
14696         {
14697           oappend ("QWORD PTR ");
14698           break;
14699         }
14700       /* Fall through.  */
14701     case stack_v_mode:
14702       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14703         {
14704           oappend ("QWORD PTR ");
14705           break;
14706         }
14707       /* Fall through.  */
14708     case v_mode:
14709     case v_swap_mode:
14710     case dq_mode:
14711       USED_REX (REX_W);
14712       if (rex & REX_W)
14713         oappend ("QWORD PTR ");
14714       else
14715         {
14716           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14717             oappend ("DWORD PTR ");
14718           else
14719             oappend ("WORD PTR ");
14720           used_prefixes |= (prefixes & PREFIX_DATA);
14721         }
14722       break;
14723     case z_mode:
14724       if ((rex & REX_W) || (sizeflag & DFLAG))
14725         *obufp++ = 'D';
14726       oappend ("WORD PTR ");
14727       if (!(rex & REX_W))
14728         used_prefixes |= (prefixes & PREFIX_DATA);
14729       break;
14730     case a_mode:
14731       if (sizeflag & DFLAG)
14732         oappend ("QWORD PTR ");
14733       else
14734         oappend ("DWORD PTR ");
14735       used_prefixes |= (prefixes & PREFIX_DATA);
14736       break;
14737     case d_mode:
14738     case d_scalar_mode:
14739     case d_scalar_swap_mode:
14740     case d_swap_mode:
14741     case dqd_mode:
14742       oappend ("DWORD PTR ");
14743       break;
14744     case q_mode:
14745     case q_scalar_mode:
14746     case q_scalar_swap_mode:
14747     case q_swap_mode:
14748       oappend ("QWORD PTR ");
14749       break;
14750     case m_mode:
14751       if (address_mode == mode_64bit)
14752         oappend ("QWORD PTR ");
14753       else
14754         oappend ("DWORD PTR ");
14755       break;
14756     case f_mode:
14757       if (sizeflag & DFLAG)
14758         oappend ("FWORD PTR ");
14759       else
14760         oappend ("DWORD PTR ");
14761       used_prefixes |= (prefixes & PREFIX_DATA);
14762       break;
14763     case t_mode:
14764       oappend ("TBYTE PTR ");
14765       break;
14766     case x_mode:
14767     case x_swap_mode:
14768     case evex_x_gscat_mode:
14769     case evex_x_nobcst_mode:
14770     case b_scalar_mode:
14771     case w_scalar_mode:
14772       if (need_vex)
14773         {
14774           switch (vex.length)
14775             {
14776             case 128:
14777               oappend ("XMMWORD PTR ");
14778               break;
14779             case 256:
14780               oappend ("YMMWORD PTR ");
14781               break;
14782             case 512:
14783               oappend ("ZMMWORD PTR ");
14784               break;
14785             default:
14786               abort ();
14787             }
14788         }
14789       else
14790         oappend ("XMMWORD PTR ");
14791       break;
14792     case xmm_mode:
14793       oappend ("XMMWORD PTR ");
14794       break;
14795     case ymm_mode:
14796       oappend ("YMMWORD PTR ");
14797       break;
14798     case xmmq_mode:
14799     case evex_half_bcst_xmmq_mode:
14800       if (!need_vex)
14801         abort ();
14802
14803       switch (vex.length)
14804         {
14805         case 128:
14806           oappend ("QWORD PTR ");
14807           break;
14808         case 256:
14809           oappend ("XMMWORD PTR ");
14810           break;
14811         case 512:
14812           oappend ("YMMWORD PTR ");
14813           break;
14814         default:
14815           abort ();
14816         }
14817       break;
14818     case xmm_mb_mode:
14819       if (!need_vex)
14820         abort ();
14821
14822       switch (vex.length)
14823         {
14824         case 128:
14825         case 256:
14826         case 512:
14827           oappend ("BYTE PTR ");
14828           break;
14829         default:
14830           abort ();
14831         }
14832       break;
14833     case xmm_mw_mode:
14834       if (!need_vex)
14835         abort ();
14836
14837       switch (vex.length)
14838         {
14839         case 128:
14840         case 256:
14841         case 512:
14842           oappend ("WORD PTR ");
14843           break;
14844         default:
14845           abort ();
14846         }
14847       break;
14848     case xmm_md_mode:
14849       if (!need_vex)
14850         abort ();
14851
14852       switch (vex.length)
14853         {
14854         case 128:
14855         case 256:
14856         case 512:
14857           oappend ("DWORD PTR ");
14858           break;
14859         default:
14860           abort ();
14861         }
14862       break;
14863     case xmm_mq_mode:
14864       if (!need_vex)
14865         abort ();
14866
14867       switch (vex.length)
14868         {
14869         case 128:
14870         case 256:
14871         case 512:
14872           oappend ("QWORD PTR ");
14873           break;
14874         default:
14875           abort ();
14876         }
14877       break;
14878     case xmmdw_mode:
14879       if (!need_vex)
14880         abort ();
14881
14882       switch (vex.length)
14883         {
14884         case 128:
14885           oappend ("WORD PTR ");
14886           break;
14887         case 256:
14888           oappend ("DWORD PTR ");
14889           break;
14890         case 512:
14891           oappend ("QWORD PTR ");
14892           break;
14893         default:
14894           abort ();
14895         }
14896       break;
14897     case xmmqd_mode:
14898       if (!need_vex)
14899         abort ();
14900
14901       switch (vex.length)
14902         {
14903         case 128:
14904           oappend ("DWORD PTR ");
14905           break;
14906         case 256:
14907           oappend ("QWORD PTR ");
14908           break;
14909         case 512:
14910           oappend ("XMMWORD PTR ");
14911           break;
14912         default:
14913           abort ();
14914         }
14915       break;
14916     case ymmq_mode:
14917       if (!need_vex)
14918         abort ();
14919
14920       switch (vex.length)
14921         {
14922         case 128:
14923           oappend ("QWORD PTR ");
14924           break;
14925         case 256:
14926           oappend ("YMMWORD PTR ");
14927           break;
14928         case 512:
14929           oappend ("ZMMWORD PTR ");
14930           break;
14931         default:
14932           abort ();
14933         }
14934       break;
14935     case ymmxmm_mode:
14936       if (!need_vex)
14937         abort ();
14938
14939       switch (vex.length)
14940         {
14941         case 128:
14942         case 256:
14943           oappend ("XMMWORD PTR ");
14944           break;
14945         default:
14946           abort ();
14947         }
14948       break;
14949     case o_mode:
14950       oappend ("OWORD PTR ");
14951       break;
14952     case xmm_mdq_mode:
14953     case vex_w_dq_mode:
14954     case vex_scalar_w_dq_mode:
14955       if (!need_vex)
14956         abort ();
14957
14958       if (vex.w)
14959         oappend ("QWORD PTR ");
14960       else
14961         oappend ("DWORD PTR ");
14962       break;
14963     case vex_vsib_d_w_dq_mode:
14964     case vex_vsib_q_w_dq_mode:
14965       if (!need_vex)
14966         abort ();
14967
14968       if (!vex.evex)
14969         {
14970           if (vex.w)
14971             oappend ("QWORD PTR ");
14972           else
14973             oappend ("DWORD PTR ");
14974         }
14975       else
14976         {
14977           switch (vex.length)
14978             {
14979             case 128:
14980               oappend ("XMMWORD PTR ");
14981               break;
14982             case 256:
14983               oappend ("YMMWORD PTR ");
14984               break;
14985             case 512:
14986               oappend ("ZMMWORD PTR ");
14987               break;
14988             default:
14989               abort ();
14990             }
14991         }
14992       break;
14993     case vex_vsib_q_w_d_mode:
14994     case vex_vsib_d_w_d_mode:
14995       if (!need_vex || !vex.evex)
14996         abort ();
14997
14998       switch (vex.length)
14999         {
15000         case 128:
15001           oappend ("QWORD PTR ");
15002           break;
15003         case 256:
15004           oappend ("XMMWORD PTR ");
15005           break;
15006         case 512:
15007           oappend ("YMMWORD PTR ");
15008           break;
15009         default:
15010           abort ();
15011         }
15012
15013       break;
15014     case mask_bd_mode:
15015       if (!need_vex || vex.length != 128)
15016         abort ();
15017       if (vex.w)
15018         oappend ("DWORD PTR ");
15019       else
15020         oappend ("BYTE PTR ");
15021       break;
15022     case mask_mode:
15023       if (!need_vex)
15024         abort ();
15025       if (vex.w)
15026         oappend ("QWORD PTR ");
15027       else
15028         oappend ("WORD PTR ");
15029       break;
15030     case v_bnd_mode:
15031     default:
15032       break;
15033     }
15034 }
15035
15036 static void
15037 OP_E_register (int bytemode, int sizeflag)
15038 {
15039   int reg = modrm.rm;
15040   const char **names;
15041
15042   USED_REX (REX_B);
15043   if ((rex & REX_B))
15044     reg += 8;
15045
15046   if ((sizeflag & SUFFIX_ALWAYS)
15047       && (bytemode == b_swap_mode
15048           || bytemode == v_swap_mode))
15049     swap_operand ();
15050
15051   switch (bytemode)
15052     {
15053     case b_mode:
15054     case b_swap_mode:
15055       USED_REX (0);
15056       if (rex)
15057         names = names8rex;
15058       else
15059         names = names8;
15060       break;
15061     case w_mode:
15062       names = names16;
15063       break;
15064     case d_mode:
15065     case dw_mode:
15066     case db_mode:
15067       names = names32;
15068       break;
15069     case q_mode:
15070       names = names64;
15071       break;
15072     case m_mode:
15073     case v_bnd_mode:
15074       names = address_mode == mode_64bit ? names64 : names32;
15075       break;
15076     case bnd_mode:
15077       if (reg > 0x3)
15078         {
15079           oappend ("(bad)");
15080           return;
15081         }
15082       names = names_bnd;
15083       break;
15084     case indir_v_mode:
15085       if (address_mode == mode_64bit && isa64 == intel64)
15086         {
15087           names = names64;
15088           break;
15089         }
15090       /* Fall through.  */
15091     case stack_v_mode:
15092       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15093         {
15094           names = names64;
15095           break;
15096         }
15097       bytemode = v_mode;
15098       /* Fall through.  */
15099     case v_mode:
15100     case v_swap_mode:
15101     case dq_mode:
15102     case dqb_mode:
15103     case dqd_mode:
15104     case dqw_mode:
15105       USED_REX (REX_W);
15106       if (rex & REX_W)
15107         names = names64;
15108       else
15109         {
15110           if ((sizeflag & DFLAG)
15111               || (bytemode != v_mode
15112                   && bytemode != v_swap_mode))
15113             names = names32;
15114           else
15115             names = names16;
15116           used_prefixes |= (prefixes & PREFIX_DATA);
15117         }
15118       break;
15119     case mask_bd_mode:
15120     case mask_mode:
15121       if (reg > 0x7)
15122         {
15123           oappend ("(bad)");
15124           return;
15125         }
15126       names = names_mask;
15127       break;
15128     case 0:
15129       return;
15130     default:
15131       oappend (INTERNAL_DISASSEMBLER_ERROR);
15132       return;
15133     }
15134   oappend (names[reg]);
15135 }
15136
15137 static void
15138 OP_E_memory (int bytemode, int sizeflag)
15139 {
15140   bfd_vma disp = 0;
15141   int add = (rex & REX_B) ? 8 : 0;
15142   int riprel = 0;
15143   int shift;
15144
15145   if (vex.evex)
15146     {
15147       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15148       if (vex.b
15149           && bytemode != x_mode
15150           && bytemode != xmmq_mode
15151           && bytemode != evex_half_bcst_xmmq_mode)
15152         {
15153           BadOp ();
15154           return;
15155         }
15156       switch (bytemode)
15157         {
15158         case dqw_mode:
15159         case dw_mode:
15160           shift = 1;
15161           break;
15162         case dqb_mode:
15163         case db_mode:
15164           shift = 0;
15165           break;
15166         case vex_vsib_d_w_dq_mode:
15167         case vex_vsib_d_w_d_mode:
15168         case vex_vsib_q_w_dq_mode:
15169         case vex_vsib_q_w_d_mode:
15170         case evex_x_gscat_mode:
15171         case xmm_mdq_mode:
15172           shift = vex.w ? 3 : 2;
15173           break;
15174         case x_mode:
15175         case evex_half_bcst_xmmq_mode:
15176         case xmmq_mode:
15177           if (vex.b)
15178             {
15179               shift = vex.w ? 3 : 2;
15180               break;
15181             }
15182           /* Fall through.  */
15183         case xmmqd_mode:
15184         case xmmdw_mode:
15185         case ymmq_mode:
15186         case evex_x_nobcst_mode:
15187         case x_swap_mode:
15188           switch (vex.length)
15189             {
15190             case 128:
15191               shift = 4;
15192               break;
15193             case 256:
15194               shift = 5;
15195               break;
15196             case 512:
15197               shift = 6;
15198               break;
15199             default:
15200               abort ();
15201             }
15202           break;
15203         case ymm_mode:
15204           shift = 5;
15205           break;
15206         case xmm_mode:
15207           shift = 4;
15208           break;
15209         case xmm_mq_mode:
15210         case q_mode:
15211         case q_scalar_mode:
15212         case q_swap_mode:
15213         case q_scalar_swap_mode:
15214           shift = 3;
15215           break;
15216         case dqd_mode:
15217         case xmm_md_mode:
15218         case d_mode:
15219         case d_scalar_mode:
15220         case d_swap_mode:
15221         case d_scalar_swap_mode:
15222           shift = 2;
15223           break;
15224     case w_scalar_mode:
15225         case xmm_mw_mode:
15226           shift = 1;
15227           break;
15228     case b_scalar_mode:
15229         case xmm_mb_mode:
15230           shift = 0;
15231           break;
15232         default:
15233           abort ();
15234         }
15235       /* Make necessary corrections to shift for modes that need it.
15236          For these modes we currently have shift 4, 5 or 6 depending on
15237          vex.length (it corresponds to xmmword, ymmword or zmmword
15238          operand).  We might want to make it 3, 4 or 5 (e.g. for
15239          xmmq_mode).  In case of broadcast enabled the corrections
15240          aren't needed, as element size is always 32 or 64 bits.  */
15241       if (!vex.b
15242           && (bytemode == xmmq_mode
15243               || bytemode == evex_half_bcst_xmmq_mode))
15244         shift -= 1;
15245       else if (bytemode == xmmqd_mode)
15246         shift -= 2;
15247       else if (bytemode == xmmdw_mode)
15248         shift -= 3;
15249       else if (bytemode == ymmq_mode && vex.length == 128)
15250         shift -= 1;
15251     }
15252   else
15253     shift = 0;
15254
15255   USED_REX (REX_B);
15256   if (intel_syntax)
15257     intel_operand_size (bytemode, sizeflag);
15258   append_seg ();
15259
15260   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15261     {
15262       /* 32/64 bit address mode */
15263       int havedisp;
15264       int havesib;
15265       int havebase;
15266       int haveindex;
15267       int needindex;
15268       int base, rbase;
15269       int vindex = 0;
15270       int scale = 0;
15271       int addr32flag = !((sizeflag & AFLAG)
15272                          || bytemode == v_bnd_mode
15273                          || bytemode == bnd_mode);
15274       const char **indexes64 = names64;
15275       const char **indexes32 = names32;
15276
15277       havesib = 0;
15278       havebase = 1;
15279       haveindex = 0;
15280       base = modrm.rm;
15281
15282       if (base == 4)
15283         {
15284           havesib = 1;
15285           vindex = sib.index;
15286           USED_REX (REX_X);
15287           if (rex & REX_X)
15288             vindex += 8;
15289           switch (bytemode)
15290             {
15291             case vex_vsib_d_w_dq_mode:
15292             case vex_vsib_d_w_d_mode:
15293             case vex_vsib_q_w_dq_mode:
15294             case vex_vsib_q_w_d_mode:
15295               if (!need_vex)
15296                 abort ();
15297               if (vex.evex)
15298                 {
15299                   if (!vex.v)
15300                     vindex += 16;
15301                 }
15302
15303               haveindex = 1;
15304               switch (vex.length)
15305                 {
15306                 case 128:
15307                   indexes64 = indexes32 = names_xmm;
15308                   break;
15309                 case 256:
15310                   if (!vex.w
15311                       || bytemode == vex_vsib_q_w_dq_mode
15312                       || bytemode == vex_vsib_q_w_d_mode)
15313                     indexes64 = indexes32 = names_ymm;
15314                   else
15315                     indexes64 = indexes32 = names_xmm;
15316                   break;
15317                 case 512:
15318                   if (!vex.w
15319                       || bytemode == vex_vsib_q_w_dq_mode
15320                       || bytemode == vex_vsib_q_w_d_mode)
15321                     indexes64 = indexes32 = names_zmm;
15322                   else
15323                     indexes64 = indexes32 = names_ymm;
15324                   break;
15325                 default:
15326                   abort ();
15327                 }
15328               break;
15329             default:
15330               haveindex = vindex != 4;
15331               break;
15332             }
15333           scale = sib.scale;
15334           base = sib.base;
15335           codep++;
15336         }
15337       rbase = base + add;
15338
15339       switch (modrm.mod)
15340         {
15341         case 0:
15342           if (base == 5)
15343             {
15344               havebase = 0;
15345               if (address_mode == mode_64bit && !havesib)
15346                 riprel = 1;
15347               disp = get32s ();
15348             }
15349           break;
15350         case 1:
15351           FETCH_DATA (the_info, codep + 1);
15352           disp = *codep++;
15353           if ((disp & 0x80) != 0)
15354             disp -= 0x100;
15355           if (vex.evex && shift > 0)
15356             disp <<= shift;
15357           break;
15358         case 2:
15359           disp = get32s ();
15360           break;
15361         }
15362
15363       /* In 32bit mode, we need index register to tell [offset] from
15364          [eiz*1 + offset].  */
15365       needindex = (havesib
15366                    && !havebase
15367                    && !haveindex
15368                    && address_mode == mode_32bit);
15369       havedisp = (havebase
15370                   || needindex
15371                   || (havesib && (haveindex || scale != 0)));
15372
15373       if (!intel_syntax)
15374         if (modrm.mod != 0 || base == 5)
15375           {
15376             if (havedisp || riprel)
15377               print_displacement (scratchbuf, disp);
15378             else
15379               print_operand_value (scratchbuf, 1, disp);
15380             oappend (scratchbuf);
15381             if (riprel)
15382               {
15383                 set_op (disp, 1);
15384                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15385               }
15386           }
15387
15388       if ((havebase || haveindex || riprel)
15389           && (bytemode != v_bnd_mode)
15390           && (bytemode != bnd_mode))
15391         used_prefixes |= PREFIX_ADDR;
15392
15393       if (havedisp || (intel_syntax && riprel))
15394         {
15395           *obufp++ = open_char;
15396           if (intel_syntax && riprel)
15397             {
15398               set_op (disp, 1);
15399               oappend (!addr32flag ? "rip" : "eip");
15400             }
15401           *obufp = '\0';
15402           if (havebase)
15403             oappend (address_mode == mode_64bit && !addr32flag
15404                      ? names64[rbase] : names32[rbase]);
15405           if (havesib)
15406             {
15407               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15408                  print index to tell base + index from base.  */
15409               if (scale != 0
15410                   || needindex
15411                   || haveindex
15412                   || (havebase && base != ESP_REG_NUM))
15413                 {
15414                   if (!intel_syntax || havebase)
15415                     {
15416                       *obufp++ = separator_char;
15417                       *obufp = '\0';
15418                     }
15419                   if (haveindex)
15420                     oappend (address_mode == mode_64bit && !addr32flag
15421                              ? indexes64[vindex] : indexes32[vindex]);
15422                   else
15423                     oappend (address_mode == mode_64bit && !addr32flag
15424                              ? index64 : index32);
15425
15426                   *obufp++ = scale_char;
15427                   *obufp = '\0';
15428                   sprintf (scratchbuf, "%d", 1 << scale);
15429                   oappend (scratchbuf);
15430                 }
15431             }
15432           if (intel_syntax
15433               && (disp || modrm.mod != 0 || base == 5))
15434             {
15435               if (!havedisp || (bfd_signed_vma) disp >= 0)
15436                 {
15437                   *obufp++ = '+';
15438                   *obufp = '\0';
15439                 }
15440               else if (modrm.mod != 1 && disp != -disp)
15441                 {
15442                   *obufp++ = '-';
15443                   *obufp = '\0';
15444                   disp = - (bfd_signed_vma) disp;
15445                 }
15446
15447               if (havedisp)
15448                 print_displacement (scratchbuf, disp);
15449               else
15450                 print_operand_value (scratchbuf, 1, disp);
15451               oappend (scratchbuf);
15452             }
15453
15454           *obufp++ = close_char;
15455           *obufp = '\0';
15456         }
15457       else if (intel_syntax)
15458         {
15459           if (modrm.mod != 0 || base == 5)
15460             {
15461               if (!active_seg_prefix)
15462                 {
15463                   oappend (names_seg[ds_reg - es_reg]);
15464                   oappend (":");
15465                 }
15466               print_operand_value (scratchbuf, 1, disp);
15467               oappend (scratchbuf);
15468             }
15469         }
15470     }
15471   else
15472     {
15473       /* 16 bit address mode */
15474       used_prefixes |= prefixes & PREFIX_ADDR;
15475       switch (modrm.mod)
15476         {
15477         case 0:
15478           if (modrm.rm == 6)
15479             {
15480               disp = get16 ();
15481               if ((disp & 0x8000) != 0)
15482                 disp -= 0x10000;
15483             }
15484           break;
15485         case 1:
15486           FETCH_DATA (the_info, codep + 1);
15487           disp = *codep++;
15488           if ((disp & 0x80) != 0)
15489             disp -= 0x100;
15490           break;
15491         case 2:
15492           disp = get16 ();
15493           if ((disp & 0x8000) != 0)
15494             disp -= 0x10000;
15495           break;
15496         }
15497
15498       if (!intel_syntax)
15499         if (modrm.mod != 0 || modrm.rm == 6)
15500           {
15501             print_displacement (scratchbuf, disp);
15502             oappend (scratchbuf);
15503           }
15504
15505       if (modrm.mod != 0 || modrm.rm != 6)
15506         {
15507           *obufp++ = open_char;
15508           *obufp = '\0';
15509           oappend (index16[modrm.rm]);
15510           if (intel_syntax
15511               && (disp || modrm.mod != 0 || modrm.rm == 6))
15512             {
15513               if ((bfd_signed_vma) disp >= 0)
15514                 {
15515                   *obufp++ = '+';
15516                   *obufp = '\0';
15517                 }
15518               else if (modrm.mod != 1)
15519                 {
15520                   *obufp++ = '-';
15521                   *obufp = '\0';
15522                   disp = - (bfd_signed_vma) disp;
15523                 }
15524
15525               print_displacement (scratchbuf, disp);
15526               oappend (scratchbuf);
15527             }
15528
15529           *obufp++ = close_char;
15530           *obufp = '\0';
15531         }
15532       else if (intel_syntax)
15533         {
15534           if (!active_seg_prefix)
15535             {
15536               oappend (names_seg[ds_reg - es_reg]);
15537               oappend (":");
15538             }
15539           print_operand_value (scratchbuf, 1, disp & 0xffff);
15540           oappend (scratchbuf);
15541         }
15542     }
15543   if (vex.evex && vex.b
15544       && (bytemode == x_mode
15545           || bytemode == xmmq_mode
15546           || bytemode == evex_half_bcst_xmmq_mode))
15547     {
15548       if (vex.w
15549           || bytemode == xmmq_mode
15550           || bytemode == evex_half_bcst_xmmq_mode)
15551         {
15552           switch (vex.length)
15553             {
15554             case 128:
15555               oappend ("{1to2}");
15556               break;
15557             case 256:
15558               oappend ("{1to4}");
15559               break;
15560             case 512:
15561               oappend ("{1to8}");
15562               break;
15563             default:
15564               abort ();
15565             }
15566         }
15567       else
15568         {
15569           switch (vex.length)
15570             {
15571             case 128:
15572               oappend ("{1to4}");
15573               break;
15574             case 256:
15575               oappend ("{1to8}");
15576               break;
15577             case 512:
15578               oappend ("{1to16}");
15579               break;
15580             default:
15581               abort ();
15582             }
15583         }
15584     }
15585 }
15586
15587 static void
15588 OP_E (int bytemode, int sizeflag)
15589 {
15590   /* Skip mod/rm byte.  */
15591   MODRM_CHECK;
15592   codep++;
15593
15594   if (modrm.mod == 3)
15595     OP_E_register (bytemode, sizeflag);
15596   else
15597     OP_E_memory (bytemode, sizeflag);
15598 }
15599
15600 static void
15601 OP_G (int bytemode, int sizeflag)
15602 {
15603   int add = 0;
15604   USED_REX (REX_R);
15605   if (rex & REX_R)
15606     add += 8;
15607   switch (bytemode)
15608     {
15609     case b_mode:
15610       USED_REX (0);
15611       if (rex)
15612         oappend (names8rex[modrm.reg + add]);
15613       else
15614         oappend (names8[modrm.reg + add]);
15615       break;
15616     case w_mode:
15617       oappend (names16[modrm.reg + add]);
15618       break;
15619     case d_mode:
15620     case db_mode:
15621     case dw_mode:
15622       oappend (names32[modrm.reg + add]);
15623       break;
15624     case q_mode:
15625       oappend (names64[modrm.reg + add]);
15626       break;
15627     case bnd_mode:
15628       if (modrm.reg > 0x3)
15629         {
15630           oappend ("(bad)");
15631           return;
15632         }
15633       oappend (names_bnd[modrm.reg]);
15634       break;
15635     case v_mode:
15636     case dq_mode:
15637     case dqb_mode:
15638     case dqd_mode:
15639     case dqw_mode:
15640       USED_REX (REX_W);
15641       if (rex & REX_W)
15642         oappend (names64[modrm.reg + add]);
15643       else
15644         {
15645           if ((sizeflag & DFLAG) || bytemode != v_mode)
15646             oappend (names32[modrm.reg + add]);
15647           else
15648             oappend (names16[modrm.reg + add]);
15649           used_prefixes |= (prefixes & PREFIX_DATA);
15650         }
15651       break;
15652     case m_mode:
15653       if (address_mode == mode_64bit)
15654         oappend (names64[modrm.reg + add]);
15655       else
15656         oappend (names32[modrm.reg + add]);
15657       break;
15658     case mask_bd_mode:
15659     case mask_mode:
15660       if ((modrm.reg + add) > 0x7)
15661         {
15662           oappend ("(bad)");
15663           return;
15664         }
15665       oappend (names_mask[modrm.reg + add]);
15666       break;
15667     default:
15668       oappend (INTERNAL_DISASSEMBLER_ERROR);
15669       break;
15670     }
15671 }
15672
15673 static bfd_vma
15674 get64 (void)
15675 {
15676   bfd_vma x;
15677 #ifdef BFD64
15678   unsigned int a;
15679   unsigned int b;
15680
15681   FETCH_DATA (the_info, codep + 8);
15682   a = *codep++ & 0xff;
15683   a |= (*codep++ & 0xff) << 8;
15684   a |= (*codep++ & 0xff) << 16;
15685   a |= (*codep++ & 0xffu) << 24;
15686   b = *codep++ & 0xff;
15687   b |= (*codep++ & 0xff) << 8;
15688   b |= (*codep++ & 0xff) << 16;
15689   b |= (*codep++ & 0xffu) << 24;
15690   x = a + ((bfd_vma) b << 32);
15691 #else
15692   abort ();
15693   x = 0;
15694 #endif
15695   return x;
15696 }
15697
15698 static bfd_signed_vma
15699 get32 (void)
15700 {
15701   bfd_signed_vma x = 0;
15702
15703   FETCH_DATA (the_info, codep + 4);
15704   x = *codep++ & (bfd_signed_vma) 0xff;
15705   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15706   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15707   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15708   return x;
15709 }
15710
15711 static bfd_signed_vma
15712 get32s (void)
15713 {
15714   bfd_signed_vma x = 0;
15715
15716   FETCH_DATA (the_info, codep + 4);
15717   x = *codep++ & (bfd_signed_vma) 0xff;
15718   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15719   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15720   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15721
15722   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15723
15724   return x;
15725 }
15726
15727 static int
15728 get16 (void)
15729 {
15730   int x = 0;
15731
15732   FETCH_DATA (the_info, codep + 2);
15733   x = *codep++ & 0xff;
15734   x |= (*codep++ & 0xff) << 8;
15735   return x;
15736 }
15737
15738 static void
15739 set_op (bfd_vma op, int riprel)
15740 {
15741   op_index[op_ad] = op_ad;
15742   if (address_mode == mode_64bit)
15743     {
15744       op_address[op_ad] = op;
15745       op_riprel[op_ad] = riprel;
15746     }
15747   else
15748     {
15749       /* Mask to get a 32-bit address.  */
15750       op_address[op_ad] = op & 0xffffffff;
15751       op_riprel[op_ad] = riprel & 0xffffffff;
15752     }
15753 }
15754
15755 static void
15756 OP_REG (int code, int sizeflag)
15757 {
15758   const char *s;
15759   int add;
15760
15761   switch (code)
15762     {
15763     case es_reg: case ss_reg: case cs_reg:
15764     case ds_reg: case fs_reg: case gs_reg:
15765       oappend (names_seg[code - es_reg]);
15766       return;
15767     }
15768
15769   USED_REX (REX_B);
15770   if (rex & REX_B)
15771     add = 8;
15772   else
15773     add = 0;
15774
15775   switch (code)
15776     {
15777     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15778     case sp_reg: case bp_reg: case si_reg: case di_reg:
15779       s = names16[code - ax_reg + add];
15780       break;
15781     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15782     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15783       USED_REX (0);
15784       if (rex)
15785         s = names8rex[code - al_reg + add];
15786       else
15787         s = names8[code - al_reg];
15788       break;
15789     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15790     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15791       if (address_mode == mode_64bit
15792           && ((sizeflag & DFLAG) || (rex & REX_W)))
15793         {
15794           s = names64[code - rAX_reg + add];
15795           break;
15796         }
15797       code += eAX_reg - rAX_reg;
15798       /* Fall through.  */
15799     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15800     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15801       USED_REX (REX_W);
15802       if (rex & REX_W)
15803         s = names64[code - eAX_reg + add];
15804       else
15805         {
15806           if (sizeflag & DFLAG)
15807             s = names32[code - eAX_reg + add];
15808           else
15809             s = names16[code - eAX_reg + add];
15810           used_prefixes |= (prefixes & PREFIX_DATA);
15811         }
15812       break;
15813     default:
15814       s = INTERNAL_DISASSEMBLER_ERROR;
15815       break;
15816     }
15817   oappend (s);
15818 }
15819
15820 static void
15821 OP_IMREG (int code, int sizeflag)
15822 {
15823   const char *s;
15824
15825   switch (code)
15826     {
15827     case indir_dx_reg:
15828       if (intel_syntax)
15829         s = "dx";
15830       else
15831         s = "(%dx)";
15832       break;
15833     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15834     case sp_reg: case bp_reg: case si_reg: case di_reg:
15835       s = names16[code - ax_reg];
15836       break;
15837     case es_reg: case ss_reg: case cs_reg:
15838     case ds_reg: case fs_reg: case gs_reg:
15839       s = names_seg[code - es_reg];
15840       break;
15841     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15842     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15843       USED_REX (0);
15844       if (rex)
15845         s = names8rex[code - al_reg];
15846       else
15847         s = names8[code - al_reg];
15848       break;
15849     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15850     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15851       USED_REX (REX_W);
15852       if (rex & REX_W)
15853         s = names64[code - eAX_reg];
15854       else
15855         {
15856           if (sizeflag & DFLAG)
15857             s = names32[code - eAX_reg];
15858           else
15859             s = names16[code - eAX_reg];
15860           used_prefixes |= (prefixes & PREFIX_DATA);
15861         }
15862       break;
15863     case z_mode_ax_reg:
15864       if ((rex & REX_W) || (sizeflag & DFLAG))
15865         s = *names32;
15866       else
15867         s = *names16;
15868       if (!(rex & REX_W))
15869         used_prefixes |= (prefixes & PREFIX_DATA);
15870       break;
15871     default:
15872       s = INTERNAL_DISASSEMBLER_ERROR;
15873       break;
15874     }
15875   oappend (s);
15876 }
15877
15878 static void
15879 OP_I (int bytemode, int sizeflag)
15880 {
15881   bfd_signed_vma op;
15882   bfd_signed_vma mask = -1;
15883
15884   switch (bytemode)
15885     {
15886     case b_mode:
15887       FETCH_DATA (the_info, codep + 1);
15888       op = *codep++;
15889       mask = 0xff;
15890       break;
15891     case q_mode:
15892       if (address_mode == mode_64bit)
15893         {
15894           op = get32s ();
15895           break;
15896         }
15897       /* Fall through.  */
15898     case v_mode:
15899       USED_REX (REX_W);
15900       if (rex & REX_W)
15901         op = get32s ();
15902       else
15903         {
15904           if (sizeflag & DFLAG)
15905             {
15906               op = get32 ();
15907               mask = 0xffffffff;
15908             }
15909           else
15910             {
15911               op = get16 ();
15912               mask = 0xfffff;
15913             }
15914           used_prefixes |= (prefixes & PREFIX_DATA);
15915         }
15916       break;
15917     case w_mode:
15918       mask = 0xfffff;
15919       op = get16 ();
15920       break;
15921     case const_1_mode:
15922       if (intel_syntax)
15923         oappend ("1");
15924       return;
15925     default:
15926       oappend (INTERNAL_DISASSEMBLER_ERROR);
15927       return;
15928     }
15929
15930   op &= mask;
15931   scratchbuf[0] = '$';
15932   print_operand_value (scratchbuf + 1, 1, op);
15933   oappend_maybe_intel (scratchbuf);
15934   scratchbuf[0] = '\0';
15935 }
15936
15937 static void
15938 OP_I64 (int bytemode, int sizeflag)
15939 {
15940   bfd_signed_vma op;
15941   bfd_signed_vma mask = -1;
15942
15943   if (address_mode != mode_64bit)
15944     {
15945       OP_I (bytemode, sizeflag);
15946       return;
15947     }
15948
15949   switch (bytemode)
15950     {
15951     case b_mode:
15952       FETCH_DATA (the_info, codep + 1);
15953       op = *codep++;
15954       mask = 0xff;
15955       break;
15956     case v_mode:
15957       USED_REX (REX_W);
15958       if (rex & REX_W)
15959         op = get64 ();
15960       else
15961         {
15962           if (sizeflag & DFLAG)
15963             {
15964               op = get32 ();
15965               mask = 0xffffffff;
15966             }
15967           else
15968             {
15969               op = get16 ();
15970               mask = 0xfffff;
15971             }
15972           used_prefixes |= (prefixes & PREFIX_DATA);
15973         }
15974       break;
15975     case w_mode:
15976       mask = 0xfffff;
15977       op = get16 ();
15978       break;
15979     default:
15980       oappend (INTERNAL_DISASSEMBLER_ERROR);
15981       return;
15982     }
15983
15984   op &= mask;
15985   scratchbuf[0] = '$';
15986   print_operand_value (scratchbuf + 1, 1, op);
15987   oappend_maybe_intel (scratchbuf);
15988   scratchbuf[0] = '\0';
15989 }
15990
15991 static void
15992 OP_sI (int bytemode, int sizeflag)
15993 {
15994   bfd_signed_vma op;
15995
15996   switch (bytemode)
15997     {
15998     case b_mode:
15999     case b_T_mode:
16000       FETCH_DATA (the_info, codep + 1);
16001       op = *codep++;
16002       if ((op & 0x80) != 0)
16003         op -= 0x100;
16004       if (bytemode == b_T_mode)
16005         {
16006           if (address_mode != mode_64bit
16007               || !((sizeflag & DFLAG) || (rex & REX_W)))
16008             {
16009               /* The operand-size prefix is overridden by a REX prefix.  */
16010               if ((sizeflag & DFLAG) || (rex & REX_W))
16011                 op &= 0xffffffff;
16012               else
16013                 op &= 0xffff;
16014           }
16015         }
16016       else
16017         {
16018           if (!(rex & REX_W))
16019             {
16020               if (sizeflag & DFLAG)
16021                 op &= 0xffffffff;
16022               else
16023                 op &= 0xffff;
16024             }
16025         }
16026       break;
16027     case v_mode:
16028       /* The operand-size prefix is overridden by a REX prefix.  */
16029       if ((sizeflag & DFLAG) || (rex & REX_W))
16030         op = get32s ();
16031       else
16032         op = get16 ();
16033       break;
16034     default:
16035       oappend (INTERNAL_DISASSEMBLER_ERROR);
16036       return;
16037     }
16038
16039   scratchbuf[0] = '$';
16040   print_operand_value (scratchbuf + 1, 1, op);
16041   oappend_maybe_intel (scratchbuf);
16042 }
16043
16044 static void
16045 OP_J (int bytemode, int sizeflag)
16046 {
16047   bfd_vma disp;
16048   bfd_vma mask = -1;
16049   bfd_vma segment = 0;
16050
16051   switch (bytemode)
16052     {
16053     case b_mode:
16054       FETCH_DATA (the_info, codep + 1);
16055       disp = *codep++;
16056       if ((disp & 0x80) != 0)
16057         disp -= 0x100;
16058       break;
16059     case v_mode:
16060       if (isa64 == amd64)
16061         USED_REX (REX_W);
16062       if ((sizeflag & DFLAG)
16063           || (address_mode == mode_64bit
16064               && (isa64 != amd64 || (rex & REX_W))))
16065         disp = get32s ();
16066       else
16067         {
16068           disp = get16 ();
16069           if ((disp & 0x8000) != 0)
16070             disp -= 0x10000;
16071           /* In 16bit mode, address is wrapped around at 64k within
16072              the same segment.  Otherwise, a data16 prefix on a jump
16073              instruction means that the pc is masked to 16 bits after
16074              the displacement is added!  */
16075           mask = 0xffff;
16076           if ((prefixes & PREFIX_DATA) == 0)
16077             segment = ((start_pc + (codep - start_codep))
16078                        & ~((bfd_vma) 0xffff));
16079         }
16080       if (address_mode != mode_64bit
16081           || (isa64 == amd64 && !(rex & REX_W)))
16082         used_prefixes |= (prefixes & PREFIX_DATA);
16083       break;
16084     default:
16085       oappend (INTERNAL_DISASSEMBLER_ERROR);
16086       return;
16087     }
16088   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16089   set_op (disp, 0);
16090   print_operand_value (scratchbuf, 1, disp);
16091   oappend (scratchbuf);
16092 }
16093
16094 static void
16095 OP_SEG (int bytemode, int sizeflag)
16096 {
16097   if (bytemode == w_mode)
16098     oappend (names_seg[modrm.reg]);
16099   else
16100     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16101 }
16102
16103 static void
16104 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16105 {
16106   int seg, offset;
16107
16108   if (sizeflag & DFLAG)
16109     {
16110       offset = get32 ();
16111       seg = get16 ();
16112     }
16113   else
16114     {
16115       offset = get16 ();
16116       seg = get16 ();
16117     }
16118   used_prefixes |= (prefixes & PREFIX_DATA);
16119   if (intel_syntax)
16120     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16121   else
16122     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16123   oappend (scratchbuf);
16124 }
16125
16126 static void
16127 OP_OFF (int bytemode, int sizeflag)
16128 {
16129   bfd_vma off;
16130
16131   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16132     intel_operand_size (bytemode, sizeflag);
16133   append_seg ();
16134
16135   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16136     off = get32 ();
16137   else
16138     off = get16 ();
16139
16140   if (intel_syntax)
16141     {
16142       if (!active_seg_prefix)
16143         {
16144           oappend (names_seg[ds_reg - es_reg]);
16145           oappend (":");
16146         }
16147     }
16148   print_operand_value (scratchbuf, 1, off);
16149   oappend (scratchbuf);
16150 }
16151
16152 static void
16153 OP_OFF64 (int bytemode, int sizeflag)
16154 {
16155   bfd_vma off;
16156
16157   if (address_mode != mode_64bit
16158       || (prefixes & PREFIX_ADDR))
16159     {
16160       OP_OFF (bytemode, sizeflag);
16161       return;
16162     }
16163
16164   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16165     intel_operand_size (bytemode, sizeflag);
16166   append_seg ();
16167
16168   off = get64 ();
16169
16170   if (intel_syntax)
16171     {
16172       if (!active_seg_prefix)
16173         {
16174           oappend (names_seg[ds_reg - es_reg]);
16175           oappend (":");
16176         }
16177     }
16178   print_operand_value (scratchbuf, 1, off);
16179   oappend (scratchbuf);
16180 }
16181
16182 static void
16183 ptr_reg (int code, int sizeflag)
16184 {
16185   const char *s;
16186
16187   *obufp++ = open_char;
16188   used_prefixes |= (prefixes & PREFIX_ADDR);
16189   if (address_mode == mode_64bit)
16190     {
16191       if (!(sizeflag & AFLAG))
16192         s = names32[code - eAX_reg];
16193       else
16194         s = names64[code - eAX_reg];
16195     }
16196   else if (sizeflag & AFLAG)
16197     s = names32[code - eAX_reg];
16198   else
16199     s = names16[code - eAX_reg];
16200   oappend (s);
16201   *obufp++ = close_char;
16202   *obufp = 0;
16203 }
16204
16205 static void
16206 OP_ESreg (int code, int sizeflag)
16207 {
16208   if (intel_syntax)
16209     {
16210       switch (codep[-1])
16211         {
16212         case 0x6d:      /* insw/insl */
16213           intel_operand_size (z_mode, sizeflag);
16214           break;
16215         case 0xa5:      /* movsw/movsl/movsq */
16216         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16217         case 0xab:      /* stosw/stosl */
16218         case 0xaf:      /* scasw/scasl */
16219           intel_operand_size (v_mode, sizeflag);
16220           break;
16221         default:
16222           intel_operand_size (b_mode, sizeflag);
16223         }
16224     }
16225   oappend_maybe_intel ("%es:");
16226   ptr_reg (code, sizeflag);
16227 }
16228
16229 static void
16230 OP_DSreg (int code, int sizeflag)
16231 {
16232   if (intel_syntax)
16233     {
16234       switch (codep[-1])
16235         {
16236         case 0x6f:      /* outsw/outsl */
16237           intel_operand_size (z_mode, sizeflag);
16238           break;
16239         case 0xa5:      /* movsw/movsl/movsq */
16240         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16241         case 0xad:      /* lodsw/lodsl/lodsq */
16242           intel_operand_size (v_mode, sizeflag);
16243           break;
16244         default:
16245           intel_operand_size (b_mode, sizeflag);
16246         }
16247     }
16248   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16249      default segment register DS is printed.  */
16250   if (!active_seg_prefix)
16251     active_seg_prefix = PREFIX_DS;
16252   append_seg ();
16253   ptr_reg (code, sizeflag);
16254 }
16255
16256 static void
16257 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16258 {
16259   int add;
16260   if (rex & REX_R)
16261     {
16262       USED_REX (REX_R);
16263       add = 8;
16264     }
16265   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16266     {
16267       all_prefixes[last_lock_prefix] = 0;
16268       used_prefixes |= PREFIX_LOCK;
16269       add = 8;
16270     }
16271   else
16272     add = 0;
16273   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16274   oappend_maybe_intel (scratchbuf);
16275 }
16276
16277 static void
16278 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16279 {
16280   int add;
16281   USED_REX (REX_R);
16282   if (rex & REX_R)
16283     add = 8;
16284   else
16285     add = 0;
16286   if (intel_syntax)
16287     sprintf (scratchbuf, "db%d", modrm.reg + add);
16288   else
16289     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16290   oappend (scratchbuf);
16291 }
16292
16293 static void
16294 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16295 {
16296   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16297   oappend_maybe_intel (scratchbuf);
16298 }
16299
16300 static void
16301 OP_R (int bytemode, int sizeflag)
16302 {
16303   /* Skip mod/rm byte.  */
16304   MODRM_CHECK;
16305   codep++;
16306   OP_E_register (bytemode, sizeflag);
16307 }
16308
16309 static void
16310 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16311 {
16312   int reg = modrm.reg;
16313   const char **names;
16314
16315   used_prefixes |= (prefixes & PREFIX_DATA);
16316   if (prefixes & PREFIX_DATA)
16317     {
16318       names = names_xmm;
16319       USED_REX (REX_R);
16320       if (rex & REX_R)
16321         reg += 8;
16322     }
16323   else
16324     names = names_mm;
16325   oappend (names[reg]);
16326 }
16327
16328 static void
16329 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16330 {
16331   int reg = modrm.reg;
16332   const char **names;
16333
16334   USED_REX (REX_R);
16335   if (rex & REX_R)
16336     reg += 8;
16337   if (vex.evex)
16338     {
16339       if (!vex.r)
16340         reg += 16;
16341     }
16342
16343   if (need_vex
16344       && bytemode != xmm_mode
16345       && bytemode != xmmq_mode
16346       && bytemode != evex_half_bcst_xmmq_mode
16347       && bytemode != ymm_mode
16348       && bytemode != scalar_mode)
16349     {
16350       switch (vex.length)
16351         {
16352         case 128:
16353           names = names_xmm;
16354           break;
16355         case 256:
16356           if (vex.w
16357               || (bytemode != vex_vsib_q_w_dq_mode
16358                   && bytemode != vex_vsib_q_w_d_mode))
16359             names = names_ymm;
16360           else
16361             names = names_xmm;
16362           break;
16363         case 512:
16364           names = names_zmm;
16365           break;
16366         default:
16367           abort ();
16368         }
16369     }
16370   else if (bytemode == xmmq_mode
16371            || bytemode == evex_half_bcst_xmmq_mode)
16372     {
16373       switch (vex.length)
16374         {
16375         case 128:
16376         case 256:
16377           names = names_xmm;
16378           break;
16379         case 512:
16380           names = names_ymm;
16381           break;
16382         default:
16383           abort ();
16384         }
16385     }
16386   else if (bytemode == ymm_mode)
16387     names = names_ymm;
16388   else
16389     names = names_xmm;
16390   oappend (names[reg]);
16391 }
16392
16393 static void
16394 OP_EM (int bytemode, int sizeflag)
16395 {
16396   int reg;
16397   const char **names;
16398
16399   if (modrm.mod != 3)
16400     {
16401       if (intel_syntax
16402           && (bytemode == v_mode || bytemode == v_swap_mode))
16403         {
16404           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16405           used_prefixes |= (prefixes & PREFIX_DATA);
16406         }
16407       OP_E (bytemode, sizeflag);
16408       return;
16409     }
16410
16411   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16412     swap_operand ();
16413
16414   /* Skip mod/rm byte.  */
16415   MODRM_CHECK;
16416   codep++;
16417   used_prefixes |= (prefixes & PREFIX_DATA);
16418   reg = modrm.rm;
16419   if (prefixes & PREFIX_DATA)
16420     {
16421       names = names_xmm;
16422       USED_REX (REX_B);
16423       if (rex & REX_B)
16424         reg += 8;
16425     }
16426   else
16427     names = names_mm;
16428   oappend (names[reg]);
16429 }
16430
16431 /* cvt* are the only instructions in sse2 which have
16432    both SSE and MMX operands and also have 0x66 prefix
16433    in their opcode. 0x66 was originally used to differentiate
16434    between SSE and MMX instruction(operands). So we have to handle the
16435    cvt* separately using OP_EMC and OP_MXC */
16436 static void
16437 OP_EMC (int bytemode, int sizeflag)
16438 {
16439   if (modrm.mod != 3)
16440     {
16441       if (intel_syntax && bytemode == v_mode)
16442         {
16443           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16444           used_prefixes |= (prefixes & PREFIX_DATA);
16445         }
16446       OP_E (bytemode, sizeflag);
16447       return;
16448     }
16449
16450   /* Skip mod/rm byte.  */
16451   MODRM_CHECK;
16452   codep++;
16453   used_prefixes |= (prefixes & PREFIX_DATA);
16454   oappend (names_mm[modrm.rm]);
16455 }
16456
16457 static void
16458 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16459 {
16460   used_prefixes |= (prefixes & PREFIX_DATA);
16461   oappend (names_mm[modrm.reg]);
16462 }
16463
16464 static void
16465 OP_EX (int bytemode, int sizeflag)
16466 {
16467   int reg;
16468   const char **names;
16469
16470   /* Skip mod/rm byte.  */
16471   MODRM_CHECK;
16472   codep++;
16473
16474   if (modrm.mod != 3)
16475     {
16476       OP_E_memory (bytemode, sizeflag);
16477       return;
16478     }
16479
16480   reg = modrm.rm;
16481   USED_REX (REX_B);
16482   if (rex & REX_B)
16483     reg += 8;
16484   if (vex.evex)
16485     {
16486       USED_REX (REX_X);
16487       if ((rex & REX_X))
16488         reg += 16;
16489     }
16490
16491   if ((sizeflag & SUFFIX_ALWAYS)
16492       && (bytemode == x_swap_mode
16493           || bytemode == d_swap_mode
16494           || bytemode == d_scalar_swap_mode
16495           || bytemode == q_swap_mode
16496           || bytemode == q_scalar_swap_mode))
16497     swap_operand ();
16498
16499   if (need_vex
16500       && bytemode != xmm_mode
16501       && bytemode != xmmdw_mode
16502       && bytemode != xmmqd_mode
16503       && bytemode != xmm_mb_mode
16504       && bytemode != xmm_mw_mode
16505       && bytemode != xmm_md_mode
16506       && bytemode != xmm_mq_mode
16507       && bytemode != xmm_mdq_mode
16508       && bytemode != xmmq_mode
16509       && bytemode != evex_half_bcst_xmmq_mode
16510       && bytemode != ymm_mode
16511       && bytemode != d_scalar_mode
16512       && bytemode != d_scalar_swap_mode
16513       && bytemode != q_scalar_mode
16514       && bytemode != q_scalar_swap_mode
16515       && bytemode != vex_scalar_w_dq_mode)
16516     {
16517       switch (vex.length)
16518         {
16519         case 128:
16520           names = names_xmm;
16521           break;
16522         case 256:
16523           names = names_ymm;
16524           break;
16525         case 512:
16526           names = names_zmm;
16527           break;
16528         default:
16529           abort ();
16530         }
16531     }
16532   else if (bytemode == xmmq_mode
16533            || bytemode == evex_half_bcst_xmmq_mode)
16534     {
16535       switch (vex.length)
16536         {
16537         case 128:
16538         case 256:
16539           names = names_xmm;
16540           break;
16541         case 512:
16542           names = names_ymm;
16543           break;
16544         default:
16545           abort ();
16546         }
16547     }
16548   else if (bytemode == ymm_mode)
16549     names = names_ymm;
16550   else
16551     names = names_xmm;
16552   oappend (names[reg]);
16553 }
16554
16555 static void
16556 OP_MS (int bytemode, int sizeflag)
16557 {
16558   if (modrm.mod == 3)
16559     OP_EM (bytemode, sizeflag);
16560   else
16561     BadOp ();
16562 }
16563
16564 static void
16565 OP_XS (int bytemode, int sizeflag)
16566 {
16567   if (modrm.mod == 3)
16568     OP_EX (bytemode, sizeflag);
16569   else
16570     BadOp ();
16571 }
16572
16573 static void
16574 OP_M (int bytemode, int sizeflag)
16575 {
16576   if (modrm.mod == 3)
16577     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16578     BadOp ();
16579   else
16580     OP_E (bytemode, sizeflag);
16581 }
16582
16583 static void
16584 OP_0f07 (int bytemode, int sizeflag)
16585 {
16586   if (modrm.mod != 3 || modrm.rm != 0)
16587     BadOp ();
16588   else
16589     OP_E (bytemode, sizeflag);
16590 }
16591
16592 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16593    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16594
16595 static void
16596 NOP_Fixup1 (int bytemode, int sizeflag)
16597 {
16598   if ((prefixes & PREFIX_DATA) != 0
16599       || (rex != 0
16600           && rex != 0x48
16601           && address_mode == mode_64bit))
16602     OP_REG (bytemode, sizeflag);
16603   else
16604     strcpy (obuf, "nop");
16605 }
16606
16607 static void
16608 NOP_Fixup2 (int bytemode, int sizeflag)
16609 {
16610   if ((prefixes & PREFIX_DATA) != 0
16611       || (rex != 0
16612           && rex != 0x48
16613           && address_mode == mode_64bit))
16614     OP_IMREG (bytemode, sizeflag);
16615 }
16616
16617 static const char *const Suffix3DNow[] = {
16618 /* 00 */        NULL,           NULL,           NULL,           NULL,
16619 /* 04 */        NULL,           NULL,           NULL,           NULL,
16620 /* 08 */        NULL,           NULL,           NULL,           NULL,
16621 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16622 /* 10 */        NULL,           NULL,           NULL,           NULL,
16623 /* 14 */        NULL,           NULL,           NULL,           NULL,
16624 /* 18 */        NULL,           NULL,           NULL,           NULL,
16625 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16626 /* 20 */        NULL,           NULL,           NULL,           NULL,
16627 /* 24 */        NULL,           NULL,           NULL,           NULL,
16628 /* 28 */        NULL,           NULL,           NULL,           NULL,
16629 /* 2C */        NULL,           NULL,           NULL,           NULL,
16630 /* 30 */        NULL,           NULL,           NULL,           NULL,
16631 /* 34 */        NULL,           NULL,           NULL,           NULL,
16632 /* 38 */        NULL,           NULL,           NULL,           NULL,
16633 /* 3C */        NULL,           NULL,           NULL,           NULL,
16634 /* 40 */        NULL,           NULL,           NULL,           NULL,
16635 /* 44 */        NULL,           NULL,           NULL,           NULL,
16636 /* 48 */        NULL,           NULL,           NULL,           NULL,
16637 /* 4C */        NULL,           NULL,           NULL,           NULL,
16638 /* 50 */        NULL,           NULL,           NULL,           NULL,
16639 /* 54 */        NULL,           NULL,           NULL,           NULL,
16640 /* 58 */        NULL,           NULL,           NULL,           NULL,
16641 /* 5C */        NULL,           NULL,           NULL,           NULL,
16642 /* 60 */        NULL,           NULL,           NULL,           NULL,
16643 /* 64 */        NULL,           NULL,           NULL,           NULL,
16644 /* 68 */        NULL,           NULL,           NULL,           NULL,
16645 /* 6C */        NULL,           NULL,           NULL,           NULL,
16646 /* 70 */        NULL,           NULL,           NULL,           NULL,
16647 /* 74 */        NULL,           NULL,           NULL,           NULL,
16648 /* 78 */        NULL,           NULL,           NULL,           NULL,
16649 /* 7C */        NULL,           NULL,           NULL,           NULL,
16650 /* 80 */        NULL,           NULL,           NULL,           NULL,
16651 /* 84 */        NULL,           NULL,           NULL,           NULL,
16652 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16653 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16654 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16655 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16656 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16657 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16658 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16659 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16660 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16661 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16662 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16663 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16664 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16665 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16666 /* C0 */        NULL,           NULL,           NULL,           NULL,
16667 /* C4 */        NULL,           NULL,           NULL,           NULL,
16668 /* C8 */        NULL,           NULL,           NULL,           NULL,
16669 /* CC */        NULL,           NULL,           NULL,           NULL,
16670 /* D0 */        NULL,           NULL,           NULL,           NULL,
16671 /* D4 */        NULL,           NULL,           NULL,           NULL,
16672 /* D8 */        NULL,           NULL,           NULL,           NULL,
16673 /* DC */        NULL,           NULL,           NULL,           NULL,
16674 /* E0 */        NULL,           NULL,           NULL,           NULL,
16675 /* E4 */        NULL,           NULL,           NULL,           NULL,
16676 /* E8 */        NULL,           NULL,           NULL,           NULL,
16677 /* EC */        NULL,           NULL,           NULL,           NULL,
16678 /* F0 */        NULL,           NULL,           NULL,           NULL,
16679 /* F4 */        NULL,           NULL,           NULL,           NULL,
16680 /* F8 */        NULL,           NULL,           NULL,           NULL,
16681 /* FC */        NULL,           NULL,           NULL,           NULL,
16682 };
16683
16684 static void
16685 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16686 {
16687   const char *mnemonic;
16688
16689   FETCH_DATA (the_info, codep + 1);
16690   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16691      place where an 8-bit immediate would normally go.  ie. the last
16692      byte of the instruction.  */
16693   obufp = mnemonicendp;
16694   mnemonic = Suffix3DNow[*codep++ & 0xff];
16695   if (mnemonic)
16696     oappend (mnemonic);
16697   else
16698     {
16699       /* Since a variable sized modrm/sib chunk is between the start
16700          of the opcode (0x0f0f) and the opcode suffix, we need to do
16701          all the modrm processing first, and don't know until now that
16702          we have a bad opcode.  This necessitates some cleaning up.  */
16703       op_out[0][0] = '\0';
16704       op_out[1][0] = '\0';
16705       BadOp ();
16706     }
16707   mnemonicendp = obufp;
16708 }
16709
16710 static struct op simd_cmp_op[] =
16711 {
16712   { STRING_COMMA_LEN ("eq") },
16713   { STRING_COMMA_LEN ("lt") },
16714   { STRING_COMMA_LEN ("le") },
16715   { STRING_COMMA_LEN ("unord") },
16716   { STRING_COMMA_LEN ("neq") },
16717   { STRING_COMMA_LEN ("nlt") },
16718   { STRING_COMMA_LEN ("nle") },
16719   { STRING_COMMA_LEN ("ord") }
16720 };
16721
16722 static void
16723 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16724 {
16725   unsigned int cmp_type;
16726
16727   FETCH_DATA (the_info, codep + 1);
16728   cmp_type = *codep++ & 0xff;
16729   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16730     {
16731       char suffix [3];
16732       char *p = mnemonicendp - 2;
16733       suffix[0] = p[0];
16734       suffix[1] = p[1];
16735       suffix[2] = '\0';
16736       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16737       mnemonicendp += simd_cmp_op[cmp_type].len;
16738     }
16739   else
16740     {
16741       /* We have a reserved extension byte.  Output it directly.  */
16742       scratchbuf[0] = '$';
16743       print_operand_value (scratchbuf + 1, 1, cmp_type);
16744       oappend_maybe_intel (scratchbuf);
16745       scratchbuf[0] = '\0';
16746     }
16747 }
16748
16749 static void
16750 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16751           int sizeflag ATTRIBUTE_UNUSED)
16752 {
16753   /* mwaitx %eax,%ecx,%ebx */
16754   if (!intel_syntax)
16755     {
16756       const char **names = (address_mode == mode_64bit
16757                             ? names64 : names32);
16758       strcpy (op_out[0], names[0]);
16759       strcpy (op_out[1], names[1]);
16760       strcpy (op_out[2], names[3]);
16761       two_source_ops = 1;
16762     }
16763   /* Skip mod/rm byte.  */
16764   MODRM_CHECK;
16765   codep++;
16766 }
16767
16768 static void
16769 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16770           int sizeflag ATTRIBUTE_UNUSED)
16771 {
16772   /* mwait %eax,%ecx  */
16773   if (!intel_syntax)
16774     {
16775       const char **names = (address_mode == mode_64bit
16776                             ? names64 : names32);
16777       strcpy (op_out[0], names[0]);
16778       strcpy (op_out[1], names[1]);
16779       two_source_ops = 1;
16780     }
16781   /* Skip mod/rm byte.  */
16782   MODRM_CHECK;
16783   codep++;
16784 }
16785
16786 static void
16787 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16788             int sizeflag ATTRIBUTE_UNUSED)
16789 {
16790   /* monitor %eax,%ecx,%edx"  */
16791   if (!intel_syntax)
16792     {
16793       const char **op1_names;
16794       const char **names = (address_mode == mode_64bit
16795                             ? names64 : names32);
16796
16797       if (!(prefixes & PREFIX_ADDR))
16798         op1_names = (address_mode == mode_16bit
16799                      ? names16 : names);
16800       else
16801         {
16802           /* Remove "addr16/addr32".  */
16803           all_prefixes[last_addr_prefix] = 0;
16804           op1_names = (address_mode != mode_32bit
16805                        ? names32 : names16);
16806           used_prefixes |= PREFIX_ADDR;
16807         }
16808       strcpy (op_out[0], op1_names[0]);
16809       strcpy (op_out[1], names[1]);
16810       strcpy (op_out[2], names[2]);
16811       two_source_ops = 1;
16812     }
16813   /* Skip mod/rm byte.  */
16814   MODRM_CHECK;
16815   codep++;
16816 }
16817
16818 static void
16819 BadOp (void)
16820 {
16821   /* Throw away prefixes and 1st. opcode byte.  */
16822   codep = insn_codep + 1;
16823   oappend ("(bad)");
16824 }
16825
16826 static void
16827 REP_Fixup (int bytemode, int sizeflag)
16828 {
16829   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16830      lods and stos.  */
16831   if (prefixes & PREFIX_REPZ)
16832     all_prefixes[last_repz_prefix] = REP_PREFIX;
16833
16834   switch (bytemode)
16835     {
16836     case al_reg:
16837     case eAX_reg:
16838     case indir_dx_reg:
16839       OP_IMREG (bytemode, sizeflag);
16840       break;
16841     case eDI_reg:
16842       OP_ESreg (bytemode, sizeflag);
16843       break;
16844     case eSI_reg:
16845       OP_DSreg (bytemode, sizeflag);
16846       break;
16847     default:
16848       abort ();
16849       break;
16850     }
16851 }
16852
16853 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16854    "bnd".  */
16855
16856 static void
16857 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16858 {
16859   if (prefixes & PREFIX_REPNZ)
16860     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16861 }
16862
16863 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16864    "notrack".  */
16865
16866 static void
16867 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16868                int sizeflag ATTRIBUTE_UNUSED)
16869 {
16870   if (active_seg_prefix == PREFIX_DS
16871       && (address_mode != mode_64bit || last_data_prefix < 0))
16872     {
16873       /* NOTRACK prefix is only valid on indirect branch instructions.
16874          NB: DATA prefix is unsupported for Intel64.  */
16875       active_seg_prefix = 0;
16876       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16877     }
16878 }
16879
16880 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16881    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16882  */
16883
16884 static void
16885 HLE_Fixup1 (int bytemode, int sizeflag)
16886 {
16887   if (modrm.mod != 3
16888       && (prefixes & PREFIX_LOCK) != 0)
16889     {
16890       if (prefixes & PREFIX_REPZ)
16891         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16892       if (prefixes & PREFIX_REPNZ)
16893         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16894     }
16895
16896   OP_E (bytemode, sizeflag);
16897 }
16898
16899 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16900    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16901  */
16902
16903 static void
16904 HLE_Fixup2 (int bytemode, int sizeflag)
16905 {
16906   if (modrm.mod != 3)
16907     {
16908       if (prefixes & PREFIX_REPZ)
16909         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16910       if (prefixes & PREFIX_REPNZ)
16911         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16912     }
16913
16914   OP_E (bytemode, sizeflag);
16915 }
16916
16917 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16918    "xrelease" for memory operand.  No check for LOCK prefix.   */
16919
16920 static void
16921 HLE_Fixup3 (int bytemode, int sizeflag)
16922 {
16923   if (modrm.mod != 3
16924       && last_repz_prefix > last_repnz_prefix
16925       && (prefixes & PREFIX_REPZ) != 0)
16926     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16927
16928   OP_E (bytemode, sizeflag);
16929 }
16930
16931 static void
16932 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16933 {
16934   USED_REX (REX_W);
16935   if (rex & REX_W)
16936     {
16937       /* Change cmpxchg8b to cmpxchg16b.  */
16938       char *p = mnemonicendp - 2;
16939       mnemonicendp = stpcpy (p, "16b");
16940       bytemode = o_mode;
16941     }
16942   else if ((prefixes & PREFIX_LOCK) != 0)
16943     {
16944       if (prefixes & PREFIX_REPZ)
16945         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16946       if (prefixes & PREFIX_REPNZ)
16947         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16948     }
16949
16950   OP_M (bytemode, sizeflag);
16951 }
16952
16953 static void
16954 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16955 {
16956   const char **names;
16957
16958   if (need_vex)
16959     {
16960       switch (vex.length)
16961         {
16962         case 128:
16963           names = names_xmm;
16964           break;
16965         case 256:
16966           names = names_ymm;
16967           break;
16968         default:
16969           abort ();
16970         }
16971     }
16972   else
16973     names = names_xmm;
16974   oappend (names[reg]);
16975 }
16976
16977 static void
16978 CRC32_Fixup (int bytemode, int sizeflag)
16979 {
16980   /* Add proper suffix to "crc32".  */
16981   char *p = mnemonicendp;
16982
16983   switch (bytemode)
16984     {
16985     case b_mode:
16986       if (intel_syntax)
16987         goto skip;
16988
16989       *p++ = 'b';
16990       break;
16991     case v_mode:
16992       if (intel_syntax)
16993         goto skip;
16994
16995       USED_REX (REX_W);
16996       if (rex & REX_W)
16997         *p++ = 'q';
16998       else
16999         {
17000           if (sizeflag & DFLAG)
17001             *p++ = 'l';
17002           else
17003             *p++ = 'w';
17004           used_prefixes |= (prefixes & PREFIX_DATA);
17005         }
17006       break;
17007     default:
17008       oappend (INTERNAL_DISASSEMBLER_ERROR);
17009       break;
17010     }
17011   mnemonicendp = p;
17012   *p = '\0';
17013
17014 skip:
17015   if (modrm.mod == 3)
17016     {
17017       int add;
17018
17019       /* Skip mod/rm byte.  */
17020       MODRM_CHECK;
17021       codep++;
17022
17023       USED_REX (REX_B);
17024       add = (rex & REX_B) ? 8 : 0;
17025       if (bytemode == b_mode)
17026         {
17027           USED_REX (0);
17028           if (rex)
17029             oappend (names8rex[modrm.rm + add]);
17030           else
17031             oappend (names8[modrm.rm + add]);
17032         }
17033       else
17034         {
17035           USED_REX (REX_W);
17036           if (rex & REX_W)
17037             oappend (names64[modrm.rm + add]);
17038           else if ((prefixes & PREFIX_DATA))
17039             oappend (names16[modrm.rm + add]);
17040           else
17041             oappend (names32[modrm.rm + add]);
17042         }
17043     }
17044   else
17045     OP_E (bytemode, sizeflag);
17046 }
17047
17048 static void
17049 FXSAVE_Fixup (int bytemode, int sizeflag)
17050 {
17051   /* Add proper suffix to "fxsave" and "fxrstor".  */
17052   USED_REX (REX_W);
17053   if (rex & REX_W)
17054     {
17055       char *p = mnemonicendp;
17056       *p++ = '6';
17057       *p++ = '4';
17058       *p = '\0';
17059       mnemonicendp = p;
17060     }
17061   OP_M (bytemode, sizeflag);
17062 }
17063
17064 static void
17065 PCMPESTR_Fixup (int bytemode, int sizeflag)
17066 {
17067   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
17068   if (!intel_syntax)
17069     {
17070       char *p = mnemonicendp;
17071
17072       USED_REX (REX_W);
17073       if (rex & REX_W)
17074         *p++ = 'q';
17075       else if (sizeflag & SUFFIX_ALWAYS)
17076         *p++ = 'l';
17077
17078       *p = '\0';
17079       mnemonicendp = p;
17080     }
17081
17082   OP_EX (bytemode, sizeflag);
17083 }
17084
17085 /* Display the destination register operand for instructions with
17086    VEX. */
17087
17088 static void
17089 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17090 {
17091   int reg;
17092   const char **names;
17093
17094   if (!need_vex)
17095     abort ();
17096
17097   if (!need_vex_reg)
17098     return;
17099
17100   reg = vex.register_specifier;
17101   if (vex.evex)
17102     {
17103       if (!vex.v)
17104         reg += 16;
17105     }
17106
17107   if (bytemode == vex_scalar_mode)
17108     {
17109       oappend (names_xmm[reg]);
17110       return;
17111     }
17112
17113   switch (vex.length)
17114     {
17115     case 128:
17116       switch (bytemode)
17117         {
17118         case vex_mode:
17119         case vex128_mode:
17120         case vex_vsib_q_w_dq_mode:
17121         case vex_vsib_q_w_d_mode:
17122           names = names_xmm;
17123           break;
17124         case dq_mode:
17125           if (vex.w)
17126             names = names64;
17127           else
17128             names = names32;
17129           break;
17130         case mask_bd_mode:
17131         case mask_mode:
17132           if (reg > 0x7)
17133             {
17134               oappend ("(bad)");
17135               return;
17136             }
17137           names = names_mask;
17138           break;
17139         default:
17140           abort ();
17141           return;
17142         }
17143       break;
17144     case 256:
17145       switch (bytemode)
17146         {
17147         case vex_mode:
17148         case vex256_mode:
17149           names = names_ymm;
17150           break;
17151         case vex_vsib_q_w_dq_mode:
17152         case vex_vsib_q_w_d_mode:
17153           names = vex.w ? names_ymm : names_xmm;
17154           break;
17155         case mask_bd_mode:
17156         case mask_mode:
17157           if (reg > 0x7)
17158             {
17159               oappend ("(bad)");
17160               return;
17161             }
17162           names = names_mask;
17163           break;
17164         default:
17165           /* See PR binutils/20893 for a reproducer.  */
17166           oappend ("(bad)");
17167           return;
17168         }
17169       break;
17170     case 512:
17171       names = names_zmm;
17172       break;
17173     default:
17174       abort ();
17175       break;
17176     }
17177   oappend (names[reg]);
17178 }
17179
17180 /* Get the VEX immediate byte without moving codep.  */
17181
17182 static unsigned char
17183 get_vex_imm8 (int sizeflag, int opnum)
17184 {
17185   int bytes_before_imm = 0;
17186
17187   if (modrm.mod != 3)
17188     {
17189       /* There are SIB/displacement bytes.  */
17190       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17191         {
17192           /* 32/64 bit address mode */
17193           int base = modrm.rm;
17194
17195           /* Check SIB byte.  */
17196           if (base == 4)
17197             {
17198               FETCH_DATA (the_info, codep + 1);
17199               base = *codep & 7;
17200               /* When decoding the third source, don't increase
17201                  bytes_before_imm as this has already been incremented
17202                  by one in OP_E_memory while decoding the second
17203                  source operand.  */
17204               if (opnum == 0)
17205                 bytes_before_imm++;
17206             }
17207
17208           /* Don't increase bytes_before_imm when decoding the third source,
17209              it has already been incremented by OP_E_memory while decoding
17210              the second source operand.  */
17211           if (opnum == 0)
17212             {
17213               switch (modrm.mod)
17214                 {
17215                   case 0:
17216                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17217                        SIB == 5, there is a 4 byte displacement.  */
17218                     if (base != 5)
17219                       /* No displacement. */
17220                       break;
17221                     /* Fall through.  */
17222                   case 2:
17223                     /* 4 byte displacement.  */
17224                     bytes_before_imm += 4;
17225                     break;
17226                   case 1:
17227                     /* 1 byte displacement.  */
17228                     bytes_before_imm++;
17229                     break;
17230                 }
17231             }
17232         }
17233       else
17234         {
17235           /* 16 bit address mode */
17236           /* Don't increase bytes_before_imm when decoding the third source,
17237              it has already been incremented by OP_E_memory while decoding
17238              the second source operand.  */
17239           if (opnum == 0)
17240             {
17241               switch (modrm.mod)
17242                 {
17243                 case 0:
17244                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17245                   if (modrm.rm != 6)
17246                     /* No displacement. */
17247                     break;
17248                   /* Fall through.  */
17249                 case 2:
17250                   /* 2 byte displacement.  */
17251                   bytes_before_imm += 2;
17252                   break;
17253                 case 1:
17254                   /* 1 byte displacement: when decoding the third source,
17255                      don't increase bytes_before_imm as this has already
17256                      been incremented by one in OP_E_memory while decoding
17257                      the second source operand.  */
17258                   if (opnum == 0)
17259                     bytes_before_imm++;
17260
17261                   break;
17262                 }
17263             }
17264         }
17265     }
17266
17267   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17268   return codep [bytes_before_imm];
17269 }
17270
17271 static void
17272 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17273 {
17274   const char **names;
17275
17276   if (reg == -1 && modrm.mod != 3)
17277     {
17278       OP_E_memory (bytemode, sizeflag);
17279       return;
17280     }
17281   else
17282     {
17283       if (reg == -1)
17284         {
17285           reg = modrm.rm;
17286           USED_REX (REX_B);
17287           if (rex & REX_B)
17288             reg += 8;
17289         }
17290       else if (reg > 7 && address_mode != mode_64bit)
17291         BadOp ();
17292     }
17293
17294   switch (vex.length)
17295     {
17296     case 128:
17297       names = names_xmm;
17298       break;
17299     case 256:
17300       names = names_ymm;
17301       break;
17302     default:
17303       abort ();
17304     }
17305   oappend (names[reg]);
17306 }
17307
17308 static void
17309 OP_EX_VexImmW (int bytemode, int sizeflag)
17310 {
17311   int reg = -1;
17312   static unsigned char vex_imm8;
17313
17314   if (vex_w_done == 0)
17315     {
17316       vex_w_done = 1;
17317
17318       /* Skip mod/rm byte.  */
17319       MODRM_CHECK;
17320       codep++;
17321
17322       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17323
17324       if (vex.w)
17325           reg = vex_imm8 >> 4;
17326
17327       OP_EX_VexReg (bytemode, sizeflag, reg);
17328     }
17329   else if (vex_w_done == 1)
17330     {
17331       vex_w_done = 2;
17332
17333       if (!vex.w)
17334           reg = vex_imm8 >> 4;
17335
17336       OP_EX_VexReg (bytemode, sizeflag, reg);
17337     }
17338   else
17339     {
17340       /* Output the imm8 directly.  */
17341       scratchbuf[0] = '$';
17342       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17343       oappend_maybe_intel (scratchbuf);
17344       scratchbuf[0] = '\0';
17345       codep++;
17346     }
17347 }
17348
17349 static void
17350 OP_Vex_2src (int bytemode, int sizeflag)
17351 {
17352   if (modrm.mod == 3)
17353     {
17354       int reg = modrm.rm;
17355       USED_REX (REX_B);
17356       if (rex & REX_B)
17357         reg += 8;
17358       oappend (names_xmm[reg]);
17359     }
17360   else
17361     {
17362       if (intel_syntax
17363           && (bytemode == v_mode || bytemode == v_swap_mode))
17364         {
17365           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17366           used_prefixes |= (prefixes & PREFIX_DATA);
17367         }
17368       OP_E (bytemode, sizeflag);
17369     }
17370 }
17371
17372 static void
17373 OP_Vex_2src_1 (int bytemode, int sizeflag)
17374 {
17375   if (modrm.mod == 3)
17376     {
17377       /* Skip mod/rm byte.   */
17378       MODRM_CHECK;
17379       codep++;
17380     }
17381
17382   if (vex.w)
17383     oappend (names_xmm[vex.register_specifier]);
17384   else
17385     OP_Vex_2src (bytemode, sizeflag);
17386 }
17387
17388 static void
17389 OP_Vex_2src_2 (int bytemode, int sizeflag)
17390 {
17391   if (vex.w)
17392     OP_Vex_2src (bytemode, sizeflag);
17393   else
17394     oappend (names_xmm[vex.register_specifier]);
17395 }
17396
17397 static void
17398 OP_EX_VexW (int bytemode, int sizeflag)
17399 {
17400   int reg = -1;
17401
17402   if (!vex_w_done)
17403     {
17404       vex_w_done = 1;
17405
17406       /* Skip mod/rm byte.  */
17407       MODRM_CHECK;
17408       codep++;
17409
17410       if (vex.w)
17411         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17412     }
17413   else
17414     {
17415       if (!vex.w)
17416         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17417     }
17418
17419   OP_EX_VexReg (bytemode, sizeflag, reg);
17420 }
17421
17422 static void
17423 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17424              int sizeflag ATTRIBUTE_UNUSED)
17425 {
17426   /* Skip the immediate byte and check for invalid bits.  */
17427   FETCH_DATA (the_info, codep + 1);
17428   if (*codep++ & 0xf)
17429     BadOp ();
17430 }
17431
17432 static void
17433 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17434 {
17435   int reg;
17436   const char **names;
17437
17438   FETCH_DATA (the_info, codep + 1);
17439   reg = *codep++;
17440
17441   if (bytemode != x_mode)
17442     abort ();
17443
17444   if (reg & 0xf)
17445       BadOp ();
17446
17447   reg >>= 4;
17448   if (reg > 7 && address_mode != mode_64bit)
17449     BadOp ();
17450
17451   switch (vex.length)
17452     {
17453     case 128:
17454       names = names_xmm;
17455       break;
17456     case 256:
17457       names = names_ymm;
17458       break;
17459     default:
17460       abort ();
17461     }
17462   oappend (names[reg]);
17463 }
17464
17465 static void
17466 OP_XMM_VexW (int bytemode, int sizeflag)
17467 {
17468   /* Turn off the REX.W bit since it is used for swapping operands
17469      now.  */
17470   rex &= ~REX_W;
17471   OP_XMM (bytemode, sizeflag);
17472 }
17473
17474 static void
17475 OP_EX_Vex (int bytemode, int sizeflag)
17476 {
17477   if (modrm.mod != 3)
17478     {
17479       if (vex.register_specifier != 0)
17480         BadOp ();
17481       need_vex_reg = 0;
17482     }
17483   OP_EX (bytemode, sizeflag);
17484 }
17485
17486 static void
17487 OP_XMM_Vex (int bytemode, int sizeflag)
17488 {
17489   if (modrm.mod != 3)
17490     {
17491       if (vex.register_specifier != 0)
17492         BadOp ();
17493       need_vex_reg = 0;
17494     }
17495   OP_XMM (bytemode, sizeflag);
17496 }
17497
17498 static void
17499 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17500 {
17501   switch (vex.length)
17502     {
17503     case 128:
17504       mnemonicendp = stpcpy (obuf, "vzeroupper");
17505       break;
17506     case 256:
17507       mnemonicendp = stpcpy (obuf, "vzeroall");
17508       break;
17509     default:
17510       abort ();
17511     }
17512 }
17513
17514 static struct op vex_cmp_op[] =
17515 {
17516   { STRING_COMMA_LEN ("eq") },
17517   { STRING_COMMA_LEN ("lt") },
17518   { STRING_COMMA_LEN ("le") },
17519   { STRING_COMMA_LEN ("unord") },
17520   { STRING_COMMA_LEN ("neq") },
17521   { STRING_COMMA_LEN ("nlt") },
17522   { STRING_COMMA_LEN ("nle") },
17523   { STRING_COMMA_LEN ("ord") },
17524   { STRING_COMMA_LEN ("eq_uq") },
17525   { STRING_COMMA_LEN ("nge") },
17526   { STRING_COMMA_LEN ("ngt") },
17527   { STRING_COMMA_LEN ("false") },
17528   { STRING_COMMA_LEN ("neq_oq") },
17529   { STRING_COMMA_LEN ("ge") },
17530   { STRING_COMMA_LEN ("gt") },
17531   { STRING_COMMA_LEN ("true") },
17532   { STRING_COMMA_LEN ("eq_os") },
17533   { STRING_COMMA_LEN ("lt_oq") },
17534   { STRING_COMMA_LEN ("le_oq") },
17535   { STRING_COMMA_LEN ("unord_s") },
17536   { STRING_COMMA_LEN ("neq_us") },
17537   { STRING_COMMA_LEN ("nlt_uq") },
17538   { STRING_COMMA_LEN ("nle_uq") },
17539   { STRING_COMMA_LEN ("ord_s") },
17540   { STRING_COMMA_LEN ("eq_us") },
17541   { STRING_COMMA_LEN ("nge_uq") },
17542   { STRING_COMMA_LEN ("ngt_uq") },
17543   { STRING_COMMA_LEN ("false_os") },
17544   { STRING_COMMA_LEN ("neq_os") },
17545   { STRING_COMMA_LEN ("ge_oq") },
17546   { STRING_COMMA_LEN ("gt_oq") },
17547   { STRING_COMMA_LEN ("true_us") },
17548 };
17549
17550 static void
17551 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17552 {
17553   unsigned int cmp_type;
17554
17555   FETCH_DATA (the_info, codep + 1);
17556   cmp_type = *codep++ & 0xff;
17557   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17558     {
17559       char suffix [3];
17560       char *p = mnemonicendp - 2;
17561       suffix[0] = p[0];
17562       suffix[1] = p[1];
17563       suffix[2] = '\0';
17564       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17565       mnemonicendp += vex_cmp_op[cmp_type].len;
17566     }
17567   else
17568     {
17569       /* We have a reserved extension byte.  Output it directly.  */
17570       scratchbuf[0] = '$';
17571       print_operand_value (scratchbuf + 1, 1, cmp_type);
17572       oappend_maybe_intel (scratchbuf);
17573       scratchbuf[0] = '\0';
17574     }
17575 }
17576
17577 static void
17578 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17579              int sizeflag ATTRIBUTE_UNUSED)
17580 {
17581   unsigned int cmp_type;
17582
17583   if (!vex.evex)
17584     abort ();
17585
17586   FETCH_DATA (the_info, codep + 1);
17587   cmp_type = *codep++ & 0xff;
17588   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17589      If it's the case, print suffix, otherwise - print the immediate.  */
17590   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17591       && cmp_type != 3
17592       && cmp_type != 7)
17593     {
17594       char suffix [3];
17595       char *p = mnemonicendp - 2;
17596
17597       /* vpcmp* can have both one- and two-lettered suffix.  */
17598       if (p[0] == 'p')
17599         {
17600           p++;
17601           suffix[0] = p[0];
17602           suffix[1] = '\0';
17603         }
17604       else
17605         {
17606           suffix[0] = p[0];
17607           suffix[1] = p[1];
17608           suffix[2] = '\0';
17609         }
17610
17611       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17612       mnemonicendp += simd_cmp_op[cmp_type].len;
17613     }
17614   else
17615     {
17616       /* We have a reserved extension byte.  Output it directly.  */
17617       scratchbuf[0] = '$';
17618       print_operand_value (scratchbuf + 1, 1, cmp_type);
17619       oappend_maybe_intel (scratchbuf);
17620       scratchbuf[0] = '\0';
17621     }
17622 }
17623
17624 static const struct op pclmul_op[] =
17625 {
17626   { STRING_COMMA_LEN ("lql") },
17627   { STRING_COMMA_LEN ("hql") },
17628   { STRING_COMMA_LEN ("lqh") },
17629   { STRING_COMMA_LEN ("hqh") }
17630 };
17631
17632 static void
17633 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17634               int sizeflag ATTRIBUTE_UNUSED)
17635 {
17636   unsigned int pclmul_type;
17637
17638   FETCH_DATA (the_info, codep + 1);
17639   pclmul_type = *codep++ & 0xff;
17640   switch (pclmul_type)
17641     {
17642     case 0x10:
17643       pclmul_type = 2;
17644       break;
17645     case 0x11:
17646       pclmul_type = 3;
17647       break;
17648     default:
17649       break;
17650     }
17651   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17652     {
17653       char suffix [4];
17654       char *p = mnemonicendp - 3;
17655       suffix[0] = p[0];
17656       suffix[1] = p[1];
17657       suffix[2] = p[2];
17658       suffix[3] = '\0';
17659       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17660       mnemonicendp += pclmul_op[pclmul_type].len;
17661     }
17662   else
17663     {
17664       /* We have a reserved extension byte.  Output it directly.  */
17665       scratchbuf[0] = '$';
17666       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17667       oappend_maybe_intel (scratchbuf);
17668       scratchbuf[0] = '\0';
17669     }
17670 }
17671
17672 static void
17673 MOVBE_Fixup (int bytemode, int sizeflag)
17674 {
17675   /* Add proper suffix to "movbe".  */
17676   char *p = mnemonicendp;
17677
17678   switch (bytemode)
17679     {
17680     case v_mode:
17681       if (intel_syntax)
17682         goto skip;
17683
17684       USED_REX (REX_W);
17685       if (sizeflag & SUFFIX_ALWAYS)
17686         {
17687           if (rex & REX_W)
17688             *p++ = 'q';
17689           else
17690             {
17691               if (sizeflag & DFLAG)
17692                 *p++ = 'l';
17693               else
17694                 *p++ = 'w';
17695               used_prefixes |= (prefixes & PREFIX_DATA);
17696             }
17697         }
17698       break;
17699     default:
17700       oappend (INTERNAL_DISASSEMBLER_ERROR);
17701       break;
17702     }
17703   mnemonicendp = p;
17704   *p = '\0';
17705
17706 skip:
17707   OP_M (bytemode, sizeflag);
17708 }
17709
17710 static void
17711 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17712 {
17713   int reg;
17714   const char **names;
17715
17716   /* Skip mod/rm byte.  */
17717   MODRM_CHECK;
17718   codep++;
17719
17720   if (vex.w)
17721     names = names64;
17722   else
17723     names = names32;
17724
17725   reg = modrm.rm;
17726   USED_REX (REX_B);
17727   if (rex & REX_B)
17728     reg += 8;
17729
17730   oappend (names[reg]);
17731 }
17732
17733 static void
17734 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17735 {
17736   const char **names;
17737
17738   if (vex.w)
17739     names = names64;
17740   else
17741     names = names32;
17742
17743   oappend (names[vex.register_specifier]);
17744 }
17745
17746 static void
17747 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17748 {
17749   if (!vex.evex
17750       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17751     abort ();
17752
17753   USED_REX (REX_R);
17754   if ((rex & REX_R) != 0 || !vex.r)
17755     {
17756       BadOp ();
17757       return;
17758     }
17759
17760   oappend (names_mask [modrm.reg]);
17761 }
17762
17763 static void
17764 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17765 {
17766   if (!vex.evex
17767       || (bytemode != evex_rounding_mode
17768           && bytemode != evex_sae_mode))
17769     abort ();
17770   if (modrm.mod == 3 && vex.b)
17771     switch (bytemode)
17772       {
17773       case evex_rounding_mode:
17774         oappend (names_rounding[vex.ll]);
17775         break;
17776       case evex_sae_mode:
17777         oappend ("{sae}");
17778         break;
17779       default:
17780         break;
17781       }
17782 }